2006.245.08:37:51.34:Log Opened: Mark IV Field System Version 9.7.7 2006.245.08:37:51.34:location,TSUKUB32,-140.09,36.10,61.0 2006.245.08:37:51.35:horizon1,0.,5.,360. 2006.245.08:37:51.35:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.245.08:37:51.35:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.245.08:37:51.35:drivev11,330,270,no 2006.245.08:37:51.35:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.245.08:37:51.35:drivev13,15.000,268,10.000,10.000,10.000 2006.245.08:37:51.35:drivev21,330,270,no 2006.245.08:37:51.35:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.245.08:37:51.35:drivev23,15.000,268,10.000,10.000,10.000 2006.245.08:37:51.35:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.245.08:37:51.35:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.245.08:37:51.35:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.245.08:37:51.35:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.245.08:37:51.35:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.245.08:37:51.35:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.245.08:37:51.35:time,-0.364,101.533,rate 2006.245.08:37:51.35:flagr,200 2006.245.08:37:51.35:proc=k06246ts 2006.245.08:37:51.35:" k06246 2006 tsukub32 t ts 2006.245.08:37:51.35:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.245.08:37:51.35:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.245.08:37:51.35:" 108 tsukub32 14 17400 2006.245.08:37:51.35:" drudg version 050216 compiled under fs 9.7.07 2006.245.08:37:51.35:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.245.08:37:51.35:!2006.246.06:29:50 2006.246.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.246.06:29:50.03:!2006.246.07:19:50 2006.246.07:19:50.00:unstow 2006.246.07:19:50.00&unstow/antenna=e 2006.246.07:19:50.00&unstow/!+10s 2006.246.07:19:50.00&unstow/antenna=m2 2006.246.07:20:02.01:scan_name=246-0730,k06246,60 2006.246.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.246.07:20:03.13#antcn#PM 1 00019 2005 228 00 22 31 00 2006.246.07:20:03.13#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.246.07:20:03.13#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.246.07:20:03.13#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.246.07:20:03.13#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.246.07:20:03.13#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.246.07:20:04.13:ready_k5 2006.246.07:20:04.13&ready_k5/obsinfo=st 2006.246.07:20:04.13&ready_k5/autoobs=1 2006.246.07:20:04.13&ready_k5/autoobs=2 2006.246.07:20:04.13&ready_k5/autoobs=3 2006.246.07:20:04.13&ready_k5/autoobs=4 2006.246.07:20:04.13&ready_k5/obsinfo 2006.246.07:20:04.13#flagr#flagr/antenna,new-source 2006.246.07:20:04.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.246.07:20:07.35/autoobs//k5ts1/ autoobs started! 2006.246.07:20:10.47/autoobs//k5ts2/ autoobs started! 2006.246.07:20:13.58/autoobs//k5ts3/ autoobs started! 2006.246.07:20:16.74/autoobs//k5ts4/ autoobs started! 2006.246.07:20:16.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:20:16.77:4f8m12a=1 2006.246.07:20:16.77&4f8m12a/xlog=on 2006.246.07:20:16.77&4f8m12a/echo=on 2006.246.07:20:16.77&4f8m12a/pcalon 2006.246.07:20:16.77&4f8m12a/"tpicd=stop 2006.246.07:20:16.77&4f8m12a/vc4f8 2006.246.07:20:16.77&4f8m12a/ifd4f 2006.246.07:20:16.77&4f8m12a/"form=m,16.000,1:2 2006.246.07:20:16.77&4f8m12a/"tpicd 2006.246.07:20:16.77&4f8m12a/echo=off 2006.246.07:20:16.77&4f8m12a/xlog=off 2006.246.07:20:16.77$4f8m12a/echo=on 2006.246.07:20:16.77$4f8m12a/pcalon 2006.246.07:20:16.77&pcalon/"no phase cal control is implemented here 2006.246.07:20:16.77$pcalon/"no phase cal control is implemented here 2006.246.07:20:16.77$4f8m12a/"tpicd=stop 2006.246.07:20:16.77$4f8m12a/vc4f8 2006.246.07:20:16.77&vc4f8/valo=1,532.99 2006.246.07:20:16.77&vc4f8/va=1,8 2006.246.07:20:16.77&vc4f8/valo=2,572.99 2006.246.07:20:16.77&vc4f8/va=2,7 2006.246.07:20:16.77&vc4f8/valo=3,672.99 2006.246.07:20:16.77&vc4f8/va=3,6 2006.246.07:20:16.77&vc4f8/valo=4,832.99 2006.246.07:20:16.77&vc4f8/va=4,7 2006.246.07:20:16.77&vc4f8/valo=5,652.99 2006.246.07:20:16.77&vc4f8/va=5,7 2006.246.07:20:16.77&vc4f8/valo=6,772.99 2006.246.07:20:16.77&vc4f8/va=6,7 2006.246.07:20:16.77&vc4f8/valo=7,832.99 2006.246.07:20:16.77&vc4f8/va=7,7 2006.246.07:20:16.77&vc4f8/valo=8,852.99 2006.246.07:20:16.77&vc4f8/va=8,8 2006.246.07:20:16.77&vc4f8/vblo=1,632.99 2006.246.07:20:16.77&vc4f8/vb=1,4 2006.246.07:20:16.77&vc4f8/vblo=2,640.99 2006.246.07:20:16.77&vc4f8/vb=2,4 2006.246.07:20:16.77&vc4f8/vblo=3,656.99 2006.246.07:20:16.77&vc4f8/vb=3,4 2006.246.07:20:16.77&vc4f8/vblo=4,712.99 2006.246.07:20:16.77&vc4f8/vb=4,4 2006.246.07:20:16.77&vc4f8/vblo=5,744.99 2006.246.07:20:16.77&vc4f8/vb=5,3 2006.246.07:20:16.77&vc4f8/vblo=6,752.99 2006.246.07:20:16.77&vc4f8/vb=6,3 2006.246.07:20:16.77&vc4f8/vabw=wide 2006.246.07:20:16.77&vc4f8/vbbw=wide 2006.246.07:20:16.77$vc4f8/valo=1,532.99 2006.246.07:20:16.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:20:16.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:20:16.77#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:16.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:16.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:16.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:16.77#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:20:16.77#ibcon#first serial, iclass 5, count 0 2006.246.07:20:16.77#ibcon#enter sib2, iclass 5, count 0 2006.246.07:20:16.77#ibcon#flushed, iclass 5, count 0 2006.246.07:20:16.77#ibcon#about to write, iclass 5, count 0 2006.246.07:20:16.77#ibcon#wrote, iclass 5, count 0 2006.246.07:20:16.77#ibcon#about to read 3, iclass 5, count 0 2006.246.07:20:16.81#ibcon#read 3, iclass 5, count 0 2006.246.07:20:16.81#ibcon#about to read 4, iclass 5, count 0 2006.246.07:20:16.81#ibcon#read 4, iclass 5, count 0 2006.246.07:20:16.81#ibcon#about to read 5, iclass 5, count 0 2006.246.07:20:16.81#ibcon#read 5, iclass 5, count 0 2006.246.07:20:16.81#ibcon#about to read 6, iclass 5, count 0 2006.246.07:20:16.81#ibcon#read 6, iclass 5, count 0 2006.246.07:20:16.81#ibcon#end of sib2, iclass 5, count 0 2006.246.07:20:16.81#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:20:16.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:20:16.81#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:20:16.81#ibcon#*before write, iclass 5, count 0 2006.246.07:20:16.81#ibcon#enter sib2, iclass 5, count 0 2006.246.07:20:16.81#ibcon#flushed, iclass 5, count 0 2006.246.07:20:16.81#ibcon#about to write, iclass 5, count 0 2006.246.07:20:16.81#ibcon#wrote, iclass 5, count 0 2006.246.07:20:16.81#ibcon#about to read 3, iclass 5, count 0 2006.246.07:20:16.86#ibcon#read 3, iclass 5, count 0 2006.246.07:20:16.86#ibcon#about to read 4, iclass 5, count 0 2006.246.07:20:16.86#ibcon#read 4, iclass 5, count 0 2006.246.07:20:16.86#ibcon#about to read 5, iclass 5, count 0 2006.246.07:20:16.86#ibcon#read 5, iclass 5, count 0 2006.246.07:20:16.86#ibcon#about to read 6, iclass 5, count 0 2006.246.07:20:16.86#ibcon#read 6, iclass 5, count 0 2006.246.07:20:16.86#ibcon#end of sib2, iclass 5, count 0 2006.246.07:20:16.86#ibcon#*after write, iclass 5, count 0 2006.246.07:20:16.86#ibcon#*before return 0, iclass 5, count 0 2006.246.07:20:16.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:16.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:16.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:20:16.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:20:16.86$vc4f8/va=1,8 2006.246.07:20:16.86#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:20:16.86#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:20:16.86#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:16.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:16.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:16.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:16.86#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:20:16.86#ibcon#first serial, iclass 7, count 2 2006.246.07:20:16.86#ibcon#enter sib2, iclass 7, count 2 2006.246.07:20:16.86#ibcon#flushed, iclass 7, count 2 2006.246.07:20:16.86#ibcon#about to write, iclass 7, count 2 2006.246.07:20:16.86#ibcon#wrote, iclass 7, count 2 2006.246.07:20:16.86#ibcon#about to read 3, iclass 7, count 2 2006.246.07:20:16.88#ibcon#read 3, iclass 7, count 2 2006.246.07:20:16.88#ibcon#about to read 4, iclass 7, count 2 2006.246.07:20:16.88#ibcon#read 4, iclass 7, count 2 2006.246.07:20:16.88#ibcon#about to read 5, iclass 7, count 2 2006.246.07:20:16.88#ibcon#read 5, iclass 7, count 2 2006.246.07:20:16.88#ibcon#about to read 6, iclass 7, count 2 2006.246.07:20:16.88#ibcon#read 6, iclass 7, count 2 2006.246.07:20:16.88#ibcon#end of sib2, iclass 7, count 2 2006.246.07:20:16.88#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:20:16.88#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:20:16.88#ibcon#[25=AT01-08\r\n] 2006.246.07:20:16.88#ibcon#*before write, iclass 7, count 2 2006.246.07:20:16.88#ibcon#enter sib2, iclass 7, count 2 2006.246.07:20:16.88#ibcon#flushed, iclass 7, count 2 2006.246.07:20:16.88#ibcon#about to write, iclass 7, count 2 2006.246.07:20:16.88#ibcon#wrote, iclass 7, count 2 2006.246.07:20:16.88#ibcon#about to read 3, iclass 7, count 2 2006.246.07:20:16.91#ibcon#read 3, iclass 7, count 2 2006.246.07:20:16.91#ibcon#about to read 4, iclass 7, count 2 2006.246.07:20:16.91#ibcon#read 4, iclass 7, count 2 2006.246.07:20:16.91#ibcon#about to read 5, iclass 7, count 2 2006.246.07:20:16.91#ibcon#read 5, iclass 7, count 2 2006.246.07:20:16.91#ibcon#about to read 6, iclass 7, count 2 2006.246.07:20:16.91#ibcon#read 6, iclass 7, count 2 2006.246.07:20:16.91#ibcon#end of sib2, iclass 7, count 2 2006.246.07:20:16.91#ibcon#*after write, iclass 7, count 2 2006.246.07:20:16.91#ibcon#*before return 0, iclass 7, count 2 2006.246.07:20:16.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:16.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:16.91#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:20:16.91#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:16.91#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:17.03#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:17.03#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:17.03#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:20:17.03#ibcon#first serial, iclass 7, count 0 2006.246.07:20:17.03#ibcon#enter sib2, iclass 7, count 0 2006.246.07:20:17.03#ibcon#flushed, iclass 7, count 0 2006.246.07:20:17.03#ibcon#about to write, iclass 7, count 0 2006.246.07:20:17.03#ibcon#wrote, iclass 7, count 0 2006.246.07:20:17.03#ibcon#about to read 3, iclass 7, count 0 2006.246.07:20:17.05#ibcon#read 3, iclass 7, count 0 2006.246.07:20:17.05#ibcon#about to read 4, iclass 7, count 0 2006.246.07:20:17.05#ibcon#read 4, iclass 7, count 0 2006.246.07:20:17.05#ibcon#about to read 5, iclass 7, count 0 2006.246.07:20:17.05#ibcon#read 5, iclass 7, count 0 2006.246.07:20:17.05#ibcon#about to read 6, iclass 7, count 0 2006.246.07:20:17.05#ibcon#read 6, iclass 7, count 0 2006.246.07:20:17.05#ibcon#end of sib2, iclass 7, count 0 2006.246.07:20:17.05#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:20:17.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:20:17.05#ibcon#[25=USB\r\n] 2006.246.07:20:17.05#ibcon#*before write, iclass 7, count 0 2006.246.07:20:17.05#ibcon#enter sib2, iclass 7, count 0 2006.246.07:20:17.05#ibcon#flushed, iclass 7, count 0 2006.246.07:20:17.05#ibcon#about to write, iclass 7, count 0 2006.246.07:20:17.05#ibcon#wrote, iclass 7, count 0 2006.246.07:20:17.05#ibcon#about to read 3, iclass 7, count 0 2006.246.07:20:17.08#ibcon#read 3, iclass 7, count 0 2006.246.07:20:17.08#ibcon#about to read 4, iclass 7, count 0 2006.246.07:20:17.08#ibcon#read 4, iclass 7, count 0 2006.246.07:20:17.08#ibcon#about to read 5, iclass 7, count 0 2006.246.07:20:17.08#ibcon#read 5, iclass 7, count 0 2006.246.07:20:17.08#ibcon#about to read 6, iclass 7, count 0 2006.246.07:20:17.08#ibcon#read 6, iclass 7, count 0 2006.246.07:20:17.08#ibcon#end of sib2, iclass 7, count 0 2006.246.07:20:17.08#ibcon#*after write, iclass 7, count 0 2006.246.07:20:17.08#ibcon#*before return 0, iclass 7, count 0 2006.246.07:20:17.08#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:17.08#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:17.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:20:17.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:20:17.08$vc4f8/valo=2,572.99 2006.246.07:20:17.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:20:17.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:20:17.08#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:17.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:17.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:17.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:17.08#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:20:17.08#ibcon#first serial, iclass 11, count 0 2006.246.07:20:17.08#ibcon#enter sib2, iclass 11, count 0 2006.246.07:20:17.08#ibcon#flushed, iclass 11, count 0 2006.246.07:20:17.08#ibcon#about to write, iclass 11, count 0 2006.246.07:20:17.08#ibcon#wrote, iclass 11, count 0 2006.246.07:20:17.08#ibcon#about to read 3, iclass 11, count 0 2006.246.07:20:17.10#ibcon#read 3, iclass 11, count 0 2006.246.07:20:17.10#ibcon#about to read 4, iclass 11, count 0 2006.246.07:20:17.10#ibcon#read 4, iclass 11, count 0 2006.246.07:20:17.10#ibcon#about to read 5, iclass 11, count 0 2006.246.07:20:17.10#ibcon#read 5, iclass 11, count 0 2006.246.07:20:17.10#ibcon#about to read 6, iclass 11, count 0 2006.246.07:20:17.10#ibcon#read 6, iclass 11, count 0 2006.246.07:20:17.10#ibcon#end of sib2, iclass 11, count 0 2006.246.07:20:17.10#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:20:17.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:20:17.10#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:20:17.10#ibcon#*before write, iclass 11, count 0 2006.246.07:20:17.10#ibcon#enter sib2, iclass 11, count 0 2006.246.07:20:17.10#ibcon#flushed, iclass 11, count 0 2006.246.07:20:17.10#ibcon#about to write, iclass 11, count 0 2006.246.07:20:17.10#ibcon#wrote, iclass 11, count 0 2006.246.07:20:17.10#ibcon#about to read 3, iclass 11, count 0 2006.246.07:20:17.14#ibcon#read 3, iclass 11, count 0 2006.246.07:20:17.14#ibcon#about to read 4, iclass 11, count 0 2006.246.07:20:17.14#ibcon#read 4, iclass 11, count 0 2006.246.07:20:17.14#ibcon#about to read 5, iclass 11, count 0 2006.246.07:20:17.14#ibcon#read 5, iclass 11, count 0 2006.246.07:20:17.14#ibcon#about to read 6, iclass 11, count 0 2006.246.07:20:17.14#ibcon#read 6, iclass 11, count 0 2006.246.07:20:17.14#ibcon#end of sib2, iclass 11, count 0 2006.246.07:20:17.14#ibcon#*after write, iclass 11, count 0 2006.246.07:20:17.14#ibcon#*before return 0, iclass 11, count 0 2006.246.07:20:17.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:17.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:17.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:20:17.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:20:17.14$vc4f8/va=2,7 2006.246.07:20:17.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:20:17.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:20:17.14#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:17.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:17.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:17.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:17.20#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:20:17.20#ibcon#first serial, iclass 13, count 2 2006.246.07:20:17.20#ibcon#enter sib2, iclass 13, count 2 2006.246.07:20:17.20#ibcon#flushed, iclass 13, count 2 2006.246.07:20:17.20#ibcon#about to write, iclass 13, count 2 2006.246.07:20:17.20#ibcon#wrote, iclass 13, count 2 2006.246.07:20:17.20#ibcon#about to read 3, iclass 13, count 2 2006.246.07:20:17.22#ibcon#read 3, iclass 13, count 2 2006.246.07:20:17.22#ibcon#about to read 4, iclass 13, count 2 2006.246.07:20:17.22#ibcon#read 4, iclass 13, count 2 2006.246.07:20:17.22#ibcon#about to read 5, iclass 13, count 2 2006.246.07:20:17.22#ibcon#read 5, iclass 13, count 2 2006.246.07:20:17.22#ibcon#about to read 6, iclass 13, count 2 2006.246.07:20:17.22#ibcon#read 6, iclass 13, count 2 2006.246.07:20:17.22#ibcon#end of sib2, iclass 13, count 2 2006.246.07:20:17.22#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:20:17.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:20:17.22#ibcon#[25=AT02-07\r\n] 2006.246.07:20:17.22#ibcon#*before write, iclass 13, count 2 2006.246.07:20:17.22#ibcon#enter sib2, iclass 13, count 2 2006.246.07:20:17.22#ibcon#flushed, iclass 13, count 2 2006.246.07:20:17.22#ibcon#about to write, iclass 13, count 2 2006.246.07:20:17.22#ibcon#wrote, iclass 13, count 2 2006.246.07:20:17.22#ibcon#about to read 3, iclass 13, count 2 2006.246.07:20:17.25#ibcon#read 3, iclass 13, count 2 2006.246.07:20:17.25#ibcon#about to read 4, iclass 13, count 2 2006.246.07:20:17.25#ibcon#read 4, iclass 13, count 2 2006.246.07:20:17.25#ibcon#about to read 5, iclass 13, count 2 2006.246.07:20:17.25#ibcon#read 5, iclass 13, count 2 2006.246.07:20:17.25#ibcon#about to read 6, iclass 13, count 2 2006.246.07:20:17.25#ibcon#read 6, iclass 13, count 2 2006.246.07:20:17.25#ibcon#end of sib2, iclass 13, count 2 2006.246.07:20:17.25#ibcon#*after write, iclass 13, count 2 2006.246.07:20:17.25#ibcon#*before return 0, iclass 13, count 2 2006.246.07:20:17.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:17.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:17.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:20:17.25#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:17.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:17.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:17.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:17.37#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:20:17.38#ibcon#first serial, iclass 13, count 0 2006.246.07:20:17.38#ibcon#enter sib2, iclass 13, count 0 2006.246.07:20:17.38#ibcon#flushed, iclass 13, count 0 2006.246.07:20:17.38#ibcon#about to write, iclass 13, count 0 2006.246.07:20:17.38#ibcon#wrote, iclass 13, count 0 2006.246.07:20:17.38#ibcon#about to read 3, iclass 13, count 0 2006.246.07:20:17.39#ibcon#read 3, iclass 13, count 0 2006.246.07:20:17.39#ibcon#about to read 4, iclass 13, count 0 2006.246.07:20:17.39#ibcon#read 4, iclass 13, count 0 2006.246.07:20:17.39#ibcon#about to read 5, iclass 13, count 0 2006.246.07:20:17.39#ibcon#read 5, iclass 13, count 0 2006.246.07:20:17.39#ibcon#about to read 6, iclass 13, count 0 2006.246.07:20:17.39#ibcon#read 6, iclass 13, count 0 2006.246.07:20:17.39#ibcon#end of sib2, iclass 13, count 0 2006.246.07:20:17.39#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:20:17.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:20:17.39#ibcon#[25=USB\r\n] 2006.246.07:20:17.39#ibcon#*before write, iclass 13, count 0 2006.246.07:20:17.39#ibcon#enter sib2, iclass 13, count 0 2006.246.07:20:17.39#ibcon#flushed, iclass 13, count 0 2006.246.07:20:17.39#ibcon#about to write, iclass 13, count 0 2006.246.07:20:17.39#ibcon#wrote, iclass 13, count 0 2006.246.07:20:17.39#ibcon#about to read 3, iclass 13, count 0 2006.246.07:20:17.42#ibcon#read 3, iclass 13, count 0 2006.246.07:20:17.42#ibcon#about to read 4, iclass 13, count 0 2006.246.07:20:17.42#ibcon#read 4, iclass 13, count 0 2006.246.07:20:17.42#ibcon#about to read 5, iclass 13, count 0 2006.246.07:20:17.42#ibcon#read 5, iclass 13, count 0 2006.246.07:20:17.42#ibcon#about to read 6, iclass 13, count 0 2006.246.07:20:17.42#ibcon#read 6, iclass 13, count 0 2006.246.07:20:17.42#ibcon#end of sib2, iclass 13, count 0 2006.246.07:20:17.42#ibcon#*after write, iclass 13, count 0 2006.246.07:20:17.42#ibcon#*before return 0, iclass 13, count 0 2006.246.07:20:17.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:17.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:17.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:20:17.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:20:17.42$vc4f8/valo=3,672.99 2006.246.07:20:17.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:20:17.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:20:17.42#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:17.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:17.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:17.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:17.42#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:20:17.42#ibcon#first serial, iclass 15, count 0 2006.246.07:20:17.42#ibcon#enter sib2, iclass 15, count 0 2006.246.07:20:17.42#ibcon#flushed, iclass 15, count 0 2006.246.07:20:17.42#ibcon#about to write, iclass 15, count 0 2006.246.07:20:17.42#ibcon#wrote, iclass 15, count 0 2006.246.07:20:17.42#ibcon#about to read 3, iclass 15, count 0 2006.246.07:20:17.45#ibcon#read 3, iclass 15, count 0 2006.246.07:20:17.45#ibcon#about to read 4, iclass 15, count 0 2006.246.07:20:17.45#ibcon#read 4, iclass 15, count 0 2006.246.07:20:17.45#ibcon#about to read 5, iclass 15, count 0 2006.246.07:20:17.45#ibcon#read 5, iclass 15, count 0 2006.246.07:20:17.45#ibcon#about to read 6, iclass 15, count 0 2006.246.07:20:17.45#ibcon#read 6, iclass 15, count 0 2006.246.07:20:17.45#ibcon#end of sib2, iclass 15, count 0 2006.246.07:20:17.45#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:20:17.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:20:17.45#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:20:17.45#ibcon#*before write, iclass 15, count 0 2006.246.07:20:17.45#ibcon#enter sib2, iclass 15, count 0 2006.246.07:20:17.45#ibcon#flushed, iclass 15, count 0 2006.246.07:20:17.45#ibcon#about to write, iclass 15, count 0 2006.246.07:20:17.45#ibcon#wrote, iclass 15, count 0 2006.246.07:20:17.45#ibcon#about to read 3, iclass 15, count 0 2006.246.07:20:17.49#ibcon#read 3, iclass 15, count 0 2006.246.07:20:17.49#ibcon#about to read 4, iclass 15, count 0 2006.246.07:20:17.49#ibcon#read 4, iclass 15, count 0 2006.246.07:20:17.49#ibcon#about to read 5, iclass 15, count 0 2006.246.07:20:17.49#ibcon#read 5, iclass 15, count 0 2006.246.07:20:17.49#ibcon#about to read 6, iclass 15, count 0 2006.246.07:20:17.49#ibcon#read 6, iclass 15, count 0 2006.246.07:20:17.49#ibcon#end of sib2, iclass 15, count 0 2006.246.07:20:17.49#ibcon#*after write, iclass 15, count 0 2006.246.07:20:17.49#ibcon#*before return 0, iclass 15, count 0 2006.246.07:20:17.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:17.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:17.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:20:17.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:20:17.49$vc4f8/va=3,6 2006.246.07:20:17.49#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.07:20:17.49#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.07:20:17.49#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:17.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:17.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:17.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:17.54#ibcon#enter wrdev, iclass 17, count 2 2006.246.07:20:17.54#ibcon#first serial, iclass 17, count 2 2006.246.07:20:17.54#ibcon#enter sib2, iclass 17, count 2 2006.246.07:20:17.54#ibcon#flushed, iclass 17, count 2 2006.246.07:20:17.54#ibcon#about to write, iclass 17, count 2 2006.246.07:20:17.54#ibcon#wrote, iclass 17, count 2 2006.246.07:20:17.54#ibcon#about to read 3, iclass 17, count 2 2006.246.07:20:17.56#ibcon#read 3, iclass 17, count 2 2006.246.07:20:17.56#ibcon#about to read 4, iclass 17, count 2 2006.246.07:20:17.56#ibcon#read 4, iclass 17, count 2 2006.246.07:20:17.56#ibcon#about to read 5, iclass 17, count 2 2006.246.07:20:17.56#ibcon#read 5, iclass 17, count 2 2006.246.07:20:17.56#ibcon#about to read 6, iclass 17, count 2 2006.246.07:20:17.56#ibcon#read 6, iclass 17, count 2 2006.246.07:20:17.56#ibcon#end of sib2, iclass 17, count 2 2006.246.07:20:17.56#ibcon#*mode == 0, iclass 17, count 2 2006.246.07:20:17.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.07:20:17.56#ibcon#[25=AT03-06\r\n] 2006.246.07:20:17.56#ibcon#*before write, iclass 17, count 2 2006.246.07:20:17.56#ibcon#enter sib2, iclass 17, count 2 2006.246.07:20:17.56#ibcon#flushed, iclass 17, count 2 2006.246.07:20:17.56#ibcon#about to write, iclass 17, count 2 2006.246.07:20:17.56#ibcon#wrote, iclass 17, count 2 2006.246.07:20:17.56#ibcon#about to read 3, iclass 17, count 2 2006.246.07:20:17.59#ibcon#read 3, iclass 17, count 2 2006.246.07:20:17.59#ibcon#about to read 4, iclass 17, count 2 2006.246.07:20:17.59#ibcon#read 4, iclass 17, count 2 2006.246.07:20:17.59#ibcon#about to read 5, iclass 17, count 2 2006.246.07:20:17.59#ibcon#read 5, iclass 17, count 2 2006.246.07:20:17.59#ibcon#about to read 6, iclass 17, count 2 2006.246.07:20:17.59#ibcon#read 6, iclass 17, count 2 2006.246.07:20:17.59#ibcon#end of sib2, iclass 17, count 2 2006.246.07:20:17.59#ibcon#*after write, iclass 17, count 2 2006.246.07:20:17.59#ibcon#*before return 0, iclass 17, count 2 2006.246.07:20:17.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:17.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:17.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.07:20:17.59#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:17.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:17.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:17.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:17.71#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:20:17.71#ibcon#first serial, iclass 17, count 0 2006.246.07:20:17.71#ibcon#enter sib2, iclass 17, count 0 2006.246.07:20:17.71#ibcon#flushed, iclass 17, count 0 2006.246.07:20:17.71#ibcon#about to write, iclass 17, count 0 2006.246.07:20:17.71#ibcon#wrote, iclass 17, count 0 2006.246.07:20:17.71#ibcon#about to read 3, iclass 17, count 0 2006.246.07:20:17.73#ibcon#read 3, iclass 17, count 0 2006.246.07:20:17.73#ibcon#about to read 4, iclass 17, count 0 2006.246.07:20:17.73#ibcon#read 4, iclass 17, count 0 2006.246.07:20:17.73#ibcon#about to read 5, iclass 17, count 0 2006.246.07:20:17.73#ibcon#read 5, iclass 17, count 0 2006.246.07:20:17.73#ibcon#about to read 6, iclass 17, count 0 2006.246.07:20:17.73#ibcon#read 6, iclass 17, count 0 2006.246.07:20:17.73#ibcon#end of sib2, iclass 17, count 0 2006.246.07:20:17.73#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:20:17.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:20:17.73#ibcon#[25=USB\r\n] 2006.246.07:20:17.73#ibcon#*before write, iclass 17, count 0 2006.246.07:20:17.73#ibcon#enter sib2, iclass 17, count 0 2006.246.07:20:17.73#ibcon#flushed, iclass 17, count 0 2006.246.07:20:17.73#ibcon#about to write, iclass 17, count 0 2006.246.07:20:17.73#ibcon#wrote, iclass 17, count 0 2006.246.07:20:17.73#ibcon#about to read 3, iclass 17, count 0 2006.246.07:20:17.76#ibcon#read 3, iclass 17, count 0 2006.246.07:20:17.76#ibcon#about to read 4, iclass 17, count 0 2006.246.07:20:17.76#ibcon#read 4, iclass 17, count 0 2006.246.07:20:17.76#ibcon#about to read 5, iclass 17, count 0 2006.246.07:20:17.76#ibcon#read 5, iclass 17, count 0 2006.246.07:20:17.76#ibcon#about to read 6, iclass 17, count 0 2006.246.07:20:17.76#ibcon#read 6, iclass 17, count 0 2006.246.07:20:17.76#ibcon#end of sib2, iclass 17, count 0 2006.246.07:20:17.76#ibcon#*after write, iclass 17, count 0 2006.246.07:20:17.76#ibcon#*before return 0, iclass 17, count 0 2006.246.07:20:17.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:17.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:17.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:20:17.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:20:17.76$vc4f8/valo=4,832.99 2006.246.07:20:17.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:20:17.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:20:17.76#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:17.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:17.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:17.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:17.76#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:20:17.76#ibcon#first serial, iclass 19, count 0 2006.246.07:20:17.76#ibcon#enter sib2, iclass 19, count 0 2006.246.07:20:17.76#ibcon#flushed, iclass 19, count 0 2006.246.07:20:17.76#ibcon#about to write, iclass 19, count 0 2006.246.07:20:17.76#ibcon#wrote, iclass 19, count 0 2006.246.07:20:17.76#ibcon#about to read 3, iclass 19, count 0 2006.246.07:20:17.78#ibcon#read 3, iclass 19, count 0 2006.246.07:20:17.78#ibcon#about to read 4, iclass 19, count 0 2006.246.07:20:17.78#ibcon#read 4, iclass 19, count 0 2006.246.07:20:17.78#ibcon#about to read 5, iclass 19, count 0 2006.246.07:20:17.78#ibcon#read 5, iclass 19, count 0 2006.246.07:20:17.78#ibcon#about to read 6, iclass 19, count 0 2006.246.07:20:17.78#ibcon#read 6, iclass 19, count 0 2006.246.07:20:17.78#ibcon#end of sib2, iclass 19, count 0 2006.246.07:20:17.78#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:20:17.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:20:17.78#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:20:17.78#ibcon#*before write, iclass 19, count 0 2006.246.07:20:17.78#ibcon#enter sib2, iclass 19, count 0 2006.246.07:20:17.78#ibcon#flushed, iclass 19, count 0 2006.246.07:20:17.78#ibcon#about to write, iclass 19, count 0 2006.246.07:20:17.78#ibcon#wrote, iclass 19, count 0 2006.246.07:20:17.78#ibcon#about to read 3, iclass 19, count 0 2006.246.07:20:17.82#ibcon#read 3, iclass 19, count 0 2006.246.07:20:17.82#ibcon#about to read 4, iclass 19, count 0 2006.246.07:20:17.82#ibcon#read 4, iclass 19, count 0 2006.246.07:20:17.82#ibcon#about to read 5, iclass 19, count 0 2006.246.07:20:17.82#ibcon#read 5, iclass 19, count 0 2006.246.07:20:17.82#ibcon#about to read 6, iclass 19, count 0 2006.246.07:20:17.82#ibcon#read 6, iclass 19, count 0 2006.246.07:20:17.82#ibcon#end of sib2, iclass 19, count 0 2006.246.07:20:17.82#ibcon#*after write, iclass 19, count 0 2006.246.07:20:17.82#ibcon#*before return 0, iclass 19, count 0 2006.246.07:20:17.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:17.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:17.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:20:17.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:20:17.82$vc4f8/va=4,7 2006.246.07:20:17.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:20:17.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:20:17.82#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:17.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:17.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:17.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:17.88#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:20:17.88#ibcon#first serial, iclass 21, count 2 2006.246.07:20:17.88#ibcon#enter sib2, iclass 21, count 2 2006.246.07:20:17.88#ibcon#flushed, iclass 21, count 2 2006.246.07:20:17.88#ibcon#about to write, iclass 21, count 2 2006.246.07:20:17.88#ibcon#wrote, iclass 21, count 2 2006.246.07:20:17.88#ibcon#about to read 3, iclass 21, count 2 2006.246.07:20:17.90#ibcon#read 3, iclass 21, count 2 2006.246.07:20:17.90#ibcon#about to read 4, iclass 21, count 2 2006.246.07:20:17.90#ibcon#read 4, iclass 21, count 2 2006.246.07:20:17.90#ibcon#about to read 5, iclass 21, count 2 2006.246.07:20:17.90#ibcon#read 5, iclass 21, count 2 2006.246.07:20:17.90#ibcon#about to read 6, iclass 21, count 2 2006.246.07:20:17.90#ibcon#read 6, iclass 21, count 2 2006.246.07:20:17.90#ibcon#end of sib2, iclass 21, count 2 2006.246.07:20:17.90#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:20:17.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:20:17.90#ibcon#[25=AT04-07\r\n] 2006.246.07:20:17.90#ibcon#*before write, iclass 21, count 2 2006.246.07:20:17.90#ibcon#enter sib2, iclass 21, count 2 2006.246.07:20:17.90#ibcon#flushed, iclass 21, count 2 2006.246.07:20:17.90#ibcon#about to write, iclass 21, count 2 2006.246.07:20:17.90#ibcon#wrote, iclass 21, count 2 2006.246.07:20:17.90#ibcon#about to read 3, iclass 21, count 2 2006.246.07:20:17.93#ibcon#read 3, iclass 21, count 2 2006.246.07:20:17.93#ibcon#about to read 4, iclass 21, count 2 2006.246.07:20:17.93#ibcon#read 4, iclass 21, count 2 2006.246.07:20:17.93#ibcon#about to read 5, iclass 21, count 2 2006.246.07:20:17.93#ibcon#read 5, iclass 21, count 2 2006.246.07:20:17.93#ibcon#about to read 6, iclass 21, count 2 2006.246.07:20:17.93#ibcon#read 6, iclass 21, count 2 2006.246.07:20:17.93#ibcon#end of sib2, iclass 21, count 2 2006.246.07:20:17.93#ibcon#*after write, iclass 21, count 2 2006.246.07:20:17.93#ibcon#*before return 0, iclass 21, count 2 2006.246.07:20:17.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:17.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:17.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:20:17.93#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:17.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:18.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:18.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:18.05#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:20:18.05#ibcon#first serial, iclass 21, count 0 2006.246.07:20:18.05#ibcon#enter sib2, iclass 21, count 0 2006.246.07:20:18.05#ibcon#flushed, iclass 21, count 0 2006.246.07:20:18.05#ibcon#about to write, iclass 21, count 0 2006.246.07:20:18.05#ibcon#wrote, iclass 21, count 0 2006.246.07:20:18.05#ibcon#about to read 3, iclass 21, count 0 2006.246.07:20:18.07#ibcon#read 3, iclass 21, count 0 2006.246.07:20:18.07#ibcon#about to read 4, iclass 21, count 0 2006.246.07:20:18.07#ibcon#read 4, iclass 21, count 0 2006.246.07:20:18.07#ibcon#about to read 5, iclass 21, count 0 2006.246.07:20:18.07#ibcon#read 5, iclass 21, count 0 2006.246.07:20:18.07#ibcon#about to read 6, iclass 21, count 0 2006.246.07:20:18.07#ibcon#read 6, iclass 21, count 0 2006.246.07:20:18.07#ibcon#end of sib2, iclass 21, count 0 2006.246.07:20:18.07#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:20:18.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:20:18.07#ibcon#[25=USB\r\n] 2006.246.07:20:18.07#ibcon#*before write, iclass 21, count 0 2006.246.07:20:18.07#ibcon#enter sib2, iclass 21, count 0 2006.246.07:20:18.07#ibcon#flushed, iclass 21, count 0 2006.246.07:20:18.07#ibcon#about to write, iclass 21, count 0 2006.246.07:20:18.07#ibcon#wrote, iclass 21, count 0 2006.246.07:20:18.07#ibcon#about to read 3, iclass 21, count 0 2006.246.07:20:18.10#ibcon#read 3, iclass 21, count 0 2006.246.07:20:18.10#ibcon#about to read 4, iclass 21, count 0 2006.246.07:20:18.10#ibcon#read 4, iclass 21, count 0 2006.246.07:20:18.10#ibcon#about to read 5, iclass 21, count 0 2006.246.07:20:18.10#ibcon#read 5, iclass 21, count 0 2006.246.07:20:18.10#ibcon#about to read 6, iclass 21, count 0 2006.246.07:20:18.10#ibcon#read 6, iclass 21, count 0 2006.246.07:20:18.10#ibcon#end of sib2, iclass 21, count 0 2006.246.07:20:18.10#ibcon#*after write, iclass 21, count 0 2006.246.07:20:18.10#ibcon#*before return 0, iclass 21, count 0 2006.246.07:20:18.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:18.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:18.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:20:18.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:20:18.10$vc4f8/valo=5,652.99 2006.246.07:20:18.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:20:18.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:20:18.10#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:18.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:18.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:18.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:18.10#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:20:18.10#ibcon#first serial, iclass 23, count 0 2006.246.07:20:18.10#ibcon#enter sib2, iclass 23, count 0 2006.246.07:20:18.10#ibcon#flushed, iclass 23, count 0 2006.246.07:20:18.10#ibcon#about to write, iclass 23, count 0 2006.246.07:20:18.10#ibcon#wrote, iclass 23, count 0 2006.246.07:20:18.10#ibcon#about to read 3, iclass 23, count 0 2006.246.07:20:18.12#ibcon#read 3, iclass 23, count 0 2006.246.07:20:18.12#ibcon#about to read 4, iclass 23, count 0 2006.246.07:20:18.12#ibcon#read 4, iclass 23, count 0 2006.246.07:20:18.12#ibcon#about to read 5, iclass 23, count 0 2006.246.07:20:18.12#ibcon#read 5, iclass 23, count 0 2006.246.07:20:18.12#ibcon#about to read 6, iclass 23, count 0 2006.246.07:20:18.12#ibcon#read 6, iclass 23, count 0 2006.246.07:20:18.12#ibcon#end of sib2, iclass 23, count 0 2006.246.07:20:18.12#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:20:18.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:20:18.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:20:18.12#ibcon#*before write, iclass 23, count 0 2006.246.07:20:18.12#ibcon#enter sib2, iclass 23, count 0 2006.246.07:20:18.12#ibcon#flushed, iclass 23, count 0 2006.246.07:20:18.12#ibcon#about to write, iclass 23, count 0 2006.246.07:20:18.12#ibcon#wrote, iclass 23, count 0 2006.246.07:20:18.12#ibcon#about to read 3, iclass 23, count 0 2006.246.07:20:18.16#ibcon#read 3, iclass 23, count 0 2006.246.07:20:18.16#ibcon#about to read 4, iclass 23, count 0 2006.246.07:20:18.16#ibcon#read 4, iclass 23, count 0 2006.246.07:20:18.16#ibcon#about to read 5, iclass 23, count 0 2006.246.07:20:18.16#ibcon#read 5, iclass 23, count 0 2006.246.07:20:18.16#ibcon#about to read 6, iclass 23, count 0 2006.246.07:20:18.16#ibcon#read 6, iclass 23, count 0 2006.246.07:20:18.16#ibcon#end of sib2, iclass 23, count 0 2006.246.07:20:18.16#ibcon#*after write, iclass 23, count 0 2006.246.07:20:18.16#ibcon#*before return 0, iclass 23, count 0 2006.246.07:20:18.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:18.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:18.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:20:18.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:20:18.16$vc4f8/va=5,7 2006.246.07:20:18.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:20:18.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:20:18.16#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:18.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:18.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:18.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:18.22#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:20:18.22#ibcon#first serial, iclass 25, count 2 2006.246.07:20:18.22#ibcon#enter sib2, iclass 25, count 2 2006.246.07:20:18.22#ibcon#flushed, iclass 25, count 2 2006.246.07:20:18.22#ibcon#about to write, iclass 25, count 2 2006.246.07:20:18.22#ibcon#wrote, iclass 25, count 2 2006.246.07:20:18.22#ibcon#about to read 3, iclass 25, count 2 2006.246.07:20:18.24#ibcon#read 3, iclass 25, count 2 2006.246.07:20:18.24#ibcon#about to read 4, iclass 25, count 2 2006.246.07:20:18.24#ibcon#read 4, iclass 25, count 2 2006.246.07:20:18.24#ibcon#about to read 5, iclass 25, count 2 2006.246.07:20:18.24#ibcon#read 5, iclass 25, count 2 2006.246.07:20:18.24#ibcon#about to read 6, iclass 25, count 2 2006.246.07:20:18.24#ibcon#read 6, iclass 25, count 2 2006.246.07:20:18.24#ibcon#end of sib2, iclass 25, count 2 2006.246.07:20:18.24#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:20:18.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:20:18.24#ibcon#[25=AT05-07\r\n] 2006.246.07:20:18.24#ibcon#*before write, iclass 25, count 2 2006.246.07:20:18.24#ibcon#enter sib2, iclass 25, count 2 2006.246.07:20:18.24#ibcon#flushed, iclass 25, count 2 2006.246.07:20:18.24#ibcon#about to write, iclass 25, count 2 2006.246.07:20:18.24#ibcon#wrote, iclass 25, count 2 2006.246.07:20:18.24#ibcon#about to read 3, iclass 25, count 2 2006.246.07:20:18.27#ibcon#read 3, iclass 25, count 2 2006.246.07:20:18.27#ibcon#about to read 4, iclass 25, count 2 2006.246.07:20:18.27#ibcon#read 4, iclass 25, count 2 2006.246.07:20:18.27#ibcon#about to read 5, iclass 25, count 2 2006.246.07:20:18.27#ibcon#read 5, iclass 25, count 2 2006.246.07:20:18.27#ibcon#about to read 6, iclass 25, count 2 2006.246.07:20:18.27#ibcon#read 6, iclass 25, count 2 2006.246.07:20:18.27#ibcon#end of sib2, iclass 25, count 2 2006.246.07:20:18.27#ibcon#*after write, iclass 25, count 2 2006.246.07:20:18.27#ibcon#*before return 0, iclass 25, count 2 2006.246.07:20:18.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:18.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:18.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:20:18.27#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:18.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:18.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:18.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:18.39#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:20:18.39#ibcon#first serial, iclass 25, count 0 2006.246.07:20:18.39#ibcon#enter sib2, iclass 25, count 0 2006.246.07:20:18.39#ibcon#flushed, iclass 25, count 0 2006.246.07:20:18.39#ibcon#about to write, iclass 25, count 0 2006.246.07:20:18.39#ibcon#wrote, iclass 25, count 0 2006.246.07:20:18.39#ibcon#about to read 3, iclass 25, count 0 2006.246.07:20:18.41#ibcon#read 3, iclass 25, count 0 2006.246.07:20:18.41#ibcon#about to read 4, iclass 25, count 0 2006.246.07:20:18.41#ibcon#read 4, iclass 25, count 0 2006.246.07:20:18.41#ibcon#about to read 5, iclass 25, count 0 2006.246.07:20:18.41#ibcon#read 5, iclass 25, count 0 2006.246.07:20:18.41#ibcon#about to read 6, iclass 25, count 0 2006.246.07:20:18.41#ibcon#read 6, iclass 25, count 0 2006.246.07:20:18.41#ibcon#end of sib2, iclass 25, count 0 2006.246.07:20:18.41#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:20:18.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:20:18.41#ibcon#[25=USB\r\n] 2006.246.07:20:18.41#ibcon#*before write, iclass 25, count 0 2006.246.07:20:18.41#ibcon#enter sib2, iclass 25, count 0 2006.246.07:20:18.41#ibcon#flushed, iclass 25, count 0 2006.246.07:20:18.41#ibcon#about to write, iclass 25, count 0 2006.246.07:20:18.41#ibcon#wrote, iclass 25, count 0 2006.246.07:20:18.41#ibcon#about to read 3, iclass 25, count 0 2006.246.07:20:18.44#ibcon#read 3, iclass 25, count 0 2006.246.07:20:18.44#ibcon#about to read 4, iclass 25, count 0 2006.246.07:20:18.44#ibcon#read 4, iclass 25, count 0 2006.246.07:20:18.44#ibcon#about to read 5, iclass 25, count 0 2006.246.07:20:18.44#ibcon#read 5, iclass 25, count 0 2006.246.07:20:18.44#ibcon#about to read 6, iclass 25, count 0 2006.246.07:20:18.44#ibcon#read 6, iclass 25, count 0 2006.246.07:20:18.44#ibcon#end of sib2, iclass 25, count 0 2006.246.07:20:18.44#ibcon#*after write, iclass 25, count 0 2006.246.07:20:18.44#ibcon#*before return 0, iclass 25, count 0 2006.246.07:20:18.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:18.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:18.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:20:18.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:20:18.44$vc4f8/valo=6,772.99 2006.246.07:20:18.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:20:18.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:20:18.44#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:18.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:18.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:18.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:18.44#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:20:18.44#ibcon#first serial, iclass 27, count 0 2006.246.07:20:18.44#ibcon#enter sib2, iclass 27, count 0 2006.246.07:20:18.44#ibcon#flushed, iclass 27, count 0 2006.246.07:20:18.44#ibcon#about to write, iclass 27, count 0 2006.246.07:20:18.44#ibcon#wrote, iclass 27, count 0 2006.246.07:20:18.44#ibcon#about to read 3, iclass 27, count 0 2006.246.07:20:18.46#ibcon#read 3, iclass 27, count 0 2006.246.07:20:18.46#ibcon#about to read 4, iclass 27, count 0 2006.246.07:20:18.46#ibcon#read 4, iclass 27, count 0 2006.246.07:20:18.46#ibcon#about to read 5, iclass 27, count 0 2006.246.07:20:18.46#ibcon#read 5, iclass 27, count 0 2006.246.07:20:18.46#ibcon#about to read 6, iclass 27, count 0 2006.246.07:20:18.46#ibcon#read 6, iclass 27, count 0 2006.246.07:20:18.46#ibcon#end of sib2, iclass 27, count 0 2006.246.07:20:18.46#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:20:18.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:20:18.46#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:20:18.46#ibcon#*before write, iclass 27, count 0 2006.246.07:20:18.46#ibcon#enter sib2, iclass 27, count 0 2006.246.07:20:18.46#ibcon#flushed, iclass 27, count 0 2006.246.07:20:18.46#ibcon#about to write, iclass 27, count 0 2006.246.07:20:18.46#ibcon#wrote, iclass 27, count 0 2006.246.07:20:18.46#ibcon#about to read 3, iclass 27, count 0 2006.246.07:20:18.50#ibcon#read 3, iclass 27, count 0 2006.246.07:20:18.50#ibcon#about to read 4, iclass 27, count 0 2006.246.07:20:18.50#ibcon#read 4, iclass 27, count 0 2006.246.07:20:18.50#ibcon#about to read 5, iclass 27, count 0 2006.246.07:20:18.50#ibcon#read 5, iclass 27, count 0 2006.246.07:20:18.50#ibcon#about to read 6, iclass 27, count 0 2006.246.07:20:18.50#ibcon#read 6, iclass 27, count 0 2006.246.07:20:18.50#ibcon#end of sib2, iclass 27, count 0 2006.246.07:20:18.50#ibcon#*after write, iclass 27, count 0 2006.246.07:20:18.50#ibcon#*before return 0, iclass 27, count 0 2006.246.07:20:18.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:18.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:18.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:20:18.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:20:18.50$vc4f8/va=6,7 2006.246.07:20:18.50#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.07:20:18.50#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.07:20:18.50#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:18.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:20:18.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:20:18.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:20:18.56#ibcon#enter wrdev, iclass 29, count 2 2006.246.07:20:18.56#ibcon#first serial, iclass 29, count 2 2006.246.07:20:18.56#ibcon#enter sib2, iclass 29, count 2 2006.246.07:20:18.56#ibcon#flushed, iclass 29, count 2 2006.246.07:20:18.56#ibcon#about to write, iclass 29, count 2 2006.246.07:20:18.56#ibcon#wrote, iclass 29, count 2 2006.246.07:20:18.56#ibcon#about to read 3, iclass 29, count 2 2006.246.07:20:18.58#ibcon#read 3, iclass 29, count 2 2006.246.07:20:18.58#ibcon#about to read 4, iclass 29, count 2 2006.246.07:20:18.58#ibcon#read 4, iclass 29, count 2 2006.246.07:20:18.58#ibcon#about to read 5, iclass 29, count 2 2006.246.07:20:18.58#ibcon#read 5, iclass 29, count 2 2006.246.07:20:18.58#ibcon#about to read 6, iclass 29, count 2 2006.246.07:20:18.58#ibcon#read 6, iclass 29, count 2 2006.246.07:20:18.58#ibcon#end of sib2, iclass 29, count 2 2006.246.07:20:18.58#ibcon#*mode == 0, iclass 29, count 2 2006.246.07:20:18.58#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.07:20:18.58#ibcon#[25=AT06-07\r\n] 2006.246.07:20:18.58#ibcon#*before write, iclass 29, count 2 2006.246.07:20:18.58#ibcon#enter sib2, iclass 29, count 2 2006.246.07:20:18.58#ibcon#flushed, iclass 29, count 2 2006.246.07:20:18.58#ibcon#about to write, iclass 29, count 2 2006.246.07:20:18.58#ibcon#wrote, iclass 29, count 2 2006.246.07:20:18.58#ibcon#about to read 3, iclass 29, count 2 2006.246.07:20:18.61#ibcon#read 3, iclass 29, count 2 2006.246.07:20:18.61#ibcon#about to read 4, iclass 29, count 2 2006.246.07:20:18.61#ibcon#read 4, iclass 29, count 2 2006.246.07:20:18.61#ibcon#about to read 5, iclass 29, count 2 2006.246.07:20:18.61#ibcon#read 5, iclass 29, count 2 2006.246.07:20:18.61#ibcon#about to read 6, iclass 29, count 2 2006.246.07:20:18.61#ibcon#read 6, iclass 29, count 2 2006.246.07:20:18.61#ibcon#end of sib2, iclass 29, count 2 2006.246.07:20:18.61#ibcon#*after write, iclass 29, count 2 2006.246.07:20:18.61#ibcon#*before return 0, iclass 29, count 2 2006.246.07:20:18.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:20:18.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:20:18.61#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.07:20:18.61#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:18.61#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:20:18.73#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:20:18.73#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:20:18.73#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:20:18.73#ibcon#first serial, iclass 29, count 0 2006.246.07:20:18.73#ibcon#enter sib2, iclass 29, count 0 2006.246.07:20:18.73#ibcon#flushed, iclass 29, count 0 2006.246.07:20:18.73#ibcon#about to write, iclass 29, count 0 2006.246.07:20:18.73#ibcon#wrote, iclass 29, count 0 2006.246.07:20:18.73#ibcon#about to read 3, iclass 29, count 0 2006.246.07:20:18.75#ibcon#read 3, iclass 29, count 0 2006.246.07:20:18.75#ibcon#about to read 4, iclass 29, count 0 2006.246.07:20:18.75#ibcon#read 4, iclass 29, count 0 2006.246.07:20:18.75#ibcon#about to read 5, iclass 29, count 0 2006.246.07:20:18.75#ibcon#read 5, iclass 29, count 0 2006.246.07:20:18.75#ibcon#about to read 6, iclass 29, count 0 2006.246.07:20:18.75#ibcon#read 6, iclass 29, count 0 2006.246.07:20:18.75#ibcon#end of sib2, iclass 29, count 0 2006.246.07:20:18.75#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:20:18.75#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:20:18.75#ibcon#[25=USB\r\n] 2006.246.07:20:18.75#ibcon#*before write, iclass 29, count 0 2006.246.07:20:18.75#ibcon#enter sib2, iclass 29, count 0 2006.246.07:20:18.75#ibcon#flushed, iclass 29, count 0 2006.246.07:20:18.75#ibcon#about to write, iclass 29, count 0 2006.246.07:20:18.75#ibcon#wrote, iclass 29, count 0 2006.246.07:20:18.75#ibcon#about to read 3, iclass 29, count 0 2006.246.07:20:18.78#ibcon#read 3, iclass 29, count 0 2006.246.07:20:18.78#ibcon#about to read 4, iclass 29, count 0 2006.246.07:20:18.78#ibcon#read 4, iclass 29, count 0 2006.246.07:20:18.78#ibcon#about to read 5, iclass 29, count 0 2006.246.07:20:18.78#ibcon#read 5, iclass 29, count 0 2006.246.07:20:18.78#ibcon#about to read 6, iclass 29, count 0 2006.246.07:20:18.78#ibcon#read 6, iclass 29, count 0 2006.246.07:20:18.78#ibcon#end of sib2, iclass 29, count 0 2006.246.07:20:18.78#ibcon#*after write, iclass 29, count 0 2006.246.07:20:18.78#ibcon#*before return 0, iclass 29, count 0 2006.246.07:20:18.78#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:20:18.78#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:20:18.78#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:20:18.78#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:20:18.78$vc4f8/valo=7,832.99 2006.246.07:20:18.78#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.07:20:18.78#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.07:20:18.78#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:18.78#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:20:18.78#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:20:18.78#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:20:18.78#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:20:18.78#ibcon#first serial, iclass 31, count 0 2006.246.07:20:18.78#ibcon#enter sib2, iclass 31, count 0 2006.246.07:20:18.78#ibcon#flushed, iclass 31, count 0 2006.246.07:20:18.78#ibcon#about to write, iclass 31, count 0 2006.246.07:20:18.78#ibcon#wrote, iclass 31, count 0 2006.246.07:20:18.78#ibcon#about to read 3, iclass 31, count 0 2006.246.07:20:18.80#ibcon#read 3, iclass 31, count 0 2006.246.07:20:18.80#ibcon#about to read 4, iclass 31, count 0 2006.246.07:20:18.80#ibcon#read 4, iclass 31, count 0 2006.246.07:20:18.80#ibcon#about to read 5, iclass 31, count 0 2006.246.07:20:18.80#ibcon#read 5, iclass 31, count 0 2006.246.07:20:18.80#ibcon#about to read 6, iclass 31, count 0 2006.246.07:20:18.80#ibcon#read 6, iclass 31, count 0 2006.246.07:20:18.80#ibcon#end of sib2, iclass 31, count 0 2006.246.07:20:18.80#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:20:18.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:20:18.80#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:20:18.80#ibcon#*before write, iclass 31, count 0 2006.246.07:20:18.80#ibcon#enter sib2, iclass 31, count 0 2006.246.07:20:18.80#ibcon#flushed, iclass 31, count 0 2006.246.07:20:18.80#ibcon#about to write, iclass 31, count 0 2006.246.07:20:18.80#ibcon#wrote, iclass 31, count 0 2006.246.07:20:18.80#ibcon#about to read 3, iclass 31, count 0 2006.246.07:20:18.84#ibcon#read 3, iclass 31, count 0 2006.246.07:20:18.84#ibcon#about to read 4, iclass 31, count 0 2006.246.07:20:18.84#ibcon#read 4, iclass 31, count 0 2006.246.07:20:18.84#ibcon#about to read 5, iclass 31, count 0 2006.246.07:20:18.84#ibcon#read 5, iclass 31, count 0 2006.246.07:20:18.84#ibcon#about to read 6, iclass 31, count 0 2006.246.07:20:18.84#ibcon#read 6, iclass 31, count 0 2006.246.07:20:18.84#ibcon#end of sib2, iclass 31, count 0 2006.246.07:20:18.84#ibcon#*after write, iclass 31, count 0 2006.246.07:20:18.84#ibcon#*before return 0, iclass 31, count 0 2006.246.07:20:18.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:20:18.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:20:18.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:20:18.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:20:18.84$vc4f8/va=7,7 2006.246.07:20:18.84#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.07:20:18.84#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.07:20:18.84#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:18.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:20:18.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:20:18.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:20:18.90#ibcon#enter wrdev, iclass 33, count 2 2006.246.07:20:18.90#ibcon#first serial, iclass 33, count 2 2006.246.07:20:18.90#ibcon#enter sib2, iclass 33, count 2 2006.246.07:20:18.90#ibcon#flushed, iclass 33, count 2 2006.246.07:20:18.90#ibcon#about to write, iclass 33, count 2 2006.246.07:20:18.90#ibcon#wrote, iclass 33, count 2 2006.246.07:20:18.90#ibcon#about to read 3, iclass 33, count 2 2006.246.07:20:18.92#ibcon#read 3, iclass 33, count 2 2006.246.07:20:18.92#ibcon#about to read 4, iclass 33, count 2 2006.246.07:20:18.92#ibcon#read 4, iclass 33, count 2 2006.246.07:20:18.92#ibcon#about to read 5, iclass 33, count 2 2006.246.07:20:18.92#ibcon#read 5, iclass 33, count 2 2006.246.07:20:18.92#ibcon#about to read 6, iclass 33, count 2 2006.246.07:20:18.92#ibcon#read 6, iclass 33, count 2 2006.246.07:20:18.92#ibcon#end of sib2, iclass 33, count 2 2006.246.07:20:18.92#ibcon#*mode == 0, iclass 33, count 2 2006.246.07:20:18.92#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.07:20:18.92#ibcon#[25=AT07-07\r\n] 2006.246.07:20:18.92#ibcon#*before write, iclass 33, count 2 2006.246.07:20:18.92#ibcon#enter sib2, iclass 33, count 2 2006.246.07:20:18.92#ibcon#flushed, iclass 33, count 2 2006.246.07:20:18.92#ibcon#about to write, iclass 33, count 2 2006.246.07:20:18.92#ibcon#wrote, iclass 33, count 2 2006.246.07:20:18.92#ibcon#about to read 3, iclass 33, count 2 2006.246.07:20:18.95#ibcon#read 3, iclass 33, count 2 2006.246.07:20:18.95#ibcon#about to read 4, iclass 33, count 2 2006.246.07:20:18.95#ibcon#read 4, iclass 33, count 2 2006.246.07:20:18.95#ibcon#about to read 5, iclass 33, count 2 2006.246.07:20:18.95#ibcon#read 5, iclass 33, count 2 2006.246.07:20:18.95#ibcon#about to read 6, iclass 33, count 2 2006.246.07:20:18.95#ibcon#read 6, iclass 33, count 2 2006.246.07:20:18.95#ibcon#end of sib2, iclass 33, count 2 2006.246.07:20:18.95#ibcon#*after write, iclass 33, count 2 2006.246.07:20:18.95#ibcon#*before return 0, iclass 33, count 2 2006.246.07:20:18.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:20:18.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:20:18.95#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.07:20:18.95#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:18.95#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:20:19.07#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:20:19.07#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:20:19.07#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:20:19.07#ibcon#first serial, iclass 33, count 0 2006.246.07:20:19.07#ibcon#enter sib2, iclass 33, count 0 2006.246.07:20:19.07#ibcon#flushed, iclass 33, count 0 2006.246.07:20:19.07#ibcon#about to write, iclass 33, count 0 2006.246.07:20:19.07#ibcon#wrote, iclass 33, count 0 2006.246.07:20:19.07#ibcon#about to read 3, iclass 33, count 0 2006.246.07:20:19.09#ibcon#read 3, iclass 33, count 0 2006.246.07:20:19.09#ibcon#about to read 4, iclass 33, count 0 2006.246.07:20:19.09#ibcon#read 4, iclass 33, count 0 2006.246.07:20:19.09#ibcon#about to read 5, iclass 33, count 0 2006.246.07:20:19.09#ibcon#read 5, iclass 33, count 0 2006.246.07:20:19.09#ibcon#about to read 6, iclass 33, count 0 2006.246.07:20:19.09#ibcon#read 6, iclass 33, count 0 2006.246.07:20:19.09#ibcon#end of sib2, iclass 33, count 0 2006.246.07:20:19.09#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:20:19.09#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:20:19.09#ibcon#[25=USB\r\n] 2006.246.07:20:19.09#ibcon#*before write, iclass 33, count 0 2006.246.07:20:19.09#ibcon#enter sib2, iclass 33, count 0 2006.246.07:20:19.09#ibcon#flushed, iclass 33, count 0 2006.246.07:20:19.09#ibcon#about to write, iclass 33, count 0 2006.246.07:20:19.09#ibcon#wrote, iclass 33, count 0 2006.246.07:20:19.09#ibcon#about to read 3, iclass 33, count 0 2006.246.07:20:19.12#ibcon#read 3, iclass 33, count 0 2006.246.07:20:19.12#ibcon#about to read 4, iclass 33, count 0 2006.246.07:20:19.12#ibcon#read 4, iclass 33, count 0 2006.246.07:20:19.12#ibcon#about to read 5, iclass 33, count 0 2006.246.07:20:19.12#ibcon#read 5, iclass 33, count 0 2006.246.07:20:19.12#ibcon#about to read 6, iclass 33, count 0 2006.246.07:20:19.12#ibcon#read 6, iclass 33, count 0 2006.246.07:20:19.12#ibcon#end of sib2, iclass 33, count 0 2006.246.07:20:19.12#ibcon#*after write, iclass 33, count 0 2006.246.07:20:19.12#ibcon#*before return 0, iclass 33, count 0 2006.246.07:20:19.12#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:20:19.12#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:20:19.12#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:20:19.12#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:20:19.12$vc4f8/valo=8,852.99 2006.246.07:20:19.12#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.07:20:19.12#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.07:20:19.12#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:19.12#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:20:19.12#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:20:19.12#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:20:19.12#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:20:19.12#ibcon#first serial, iclass 35, count 0 2006.246.07:20:19.12#ibcon#enter sib2, iclass 35, count 0 2006.246.07:20:19.12#ibcon#flushed, iclass 35, count 0 2006.246.07:20:19.12#ibcon#about to write, iclass 35, count 0 2006.246.07:20:19.12#ibcon#wrote, iclass 35, count 0 2006.246.07:20:19.12#ibcon#about to read 3, iclass 35, count 0 2006.246.07:20:19.14#ibcon#read 3, iclass 35, count 0 2006.246.07:20:19.14#ibcon#about to read 4, iclass 35, count 0 2006.246.07:20:19.14#ibcon#read 4, iclass 35, count 0 2006.246.07:20:19.14#ibcon#about to read 5, iclass 35, count 0 2006.246.07:20:19.14#ibcon#read 5, iclass 35, count 0 2006.246.07:20:19.14#ibcon#about to read 6, iclass 35, count 0 2006.246.07:20:19.14#ibcon#read 6, iclass 35, count 0 2006.246.07:20:19.14#ibcon#end of sib2, iclass 35, count 0 2006.246.07:20:19.14#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:20:19.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:20:19.14#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:20:19.14#ibcon#*before write, iclass 35, count 0 2006.246.07:20:19.14#ibcon#enter sib2, iclass 35, count 0 2006.246.07:20:19.14#ibcon#flushed, iclass 35, count 0 2006.246.07:20:19.14#ibcon#about to write, iclass 35, count 0 2006.246.07:20:19.14#ibcon#wrote, iclass 35, count 0 2006.246.07:20:19.14#ibcon#about to read 3, iclass 35, count 0 2006.246.07:20:19.18#ibcon#read 3, iclass 35, count 0 2006.246.07:20:19.18#ibcon#about to read 4, iclass 35, count 0 2006.246.07:20:19.18#ibcon#read 4, iclass 35, count 0 2006.246.07:20:19.18#ibcon#about to read 5, iclass 35, count 0 2006.246.07:20:19.18#ibcon#read 5, iclass 35, count 0 2006.246.07:20:19.18#ibcon#about to read 6, iclass 35, count 0 2006.246.07:20:19.18#ibcon#read 6, iclass 35, count 0 2006.246.07:20:19.18#ibcon#end of sib2, iclass 35, count 0 2006.246.07:20:19.18#ibcon#*after write, iclass 35, count 0 2006.246.07:20:19.18#ibcon#*before return 0, iclass 35, count 0 2006.246.07:20:19.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:20:19.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:20:19.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:20:19.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:20:19.18$vc4f8/va=8,8 2006.246.07:20:19.18#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.07:20:19.18#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.07:20:19.18#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:19.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:20:19.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:20:19.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:20:19.24#ibcon#enter wrdev, iclass 37, count 2 2006.246.07:20:19.24#ibcon#first serial, iclass 37, count 2 2006.246.07:20:19.24#ibcon#enter sib2, iclass 37, count 2 2006.246.07:20:19.24#ibcon#flushed, iclass 37, count 2 2006.246.07:20:19.24#ibcon#about to write, iclass 37, count 2 2006.246.07:20:19.24#ibcon#wrote, iclass 37, count 2 2006.246.07:20:19.24#ibcon#about to read 3, iclass 37, count 2 2006.246.07:20:19.26#ibcon#read 3, iclass 37, count 2 2006.246.07:20:19.26#ibcon#about to read 4, iclass 37, count 2 2006.246.07:20:19.26#ibcon#read 4, iclass 37, count 2 2006.246.07:20:19.26#ibcon#about to read 5, iclass 37, count 2 2006.246.07:20:19.26#ibcon#read 5, iclass 37, count 2 2006.246.07:20:19.26#ibcon#about to read 6, iclass 37, count 2 2006.246.07:20:19.26#ibcon#read 6, iclass 37, count 2 2006.246.07:20:19.26#ibcon#end of sib2, iclass 37, count 2 2006.246.07:20:19.26#ibcon#*mode == 0, iclass 37, count 2 2006.246.07:20:19.26#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.07:20:19.26#ibcon#[25=AT08-08\r\n] 2006.246.07:20:19.26#ibcon#*before write, iclass 37, count 2 2006.246.07:20:19.26#ibcon#enter sib2, iclass 37, count 2 2006.246.07:20:19.26#ibcon#flushed, iclass 37, count 2 2006.246.07:20:19.26#ibcon#about to write, iclass 37, count 2 2006.246.07:20:19.26#ibcon#wrote, iclass 37, count 2 2006.246.07:20:19.26#ibcon#about to read 3, iclass 37, count 2 2006.246.07:20:19.29#ibcon#read 3, iclass 37, count 2 2006.246.07:20:19.29#ibcon#about to read 4, iclass 37, count 2 2006.246.07:20:19.29#ibcon#read 4, iclass 37, count 2 2006.246.07:20:19.29#ibcon#about to read 5, iclass 37, count 2 2006.246.07:20:19.29#ibcon#read 5, iclass 37, count 2 2006.246.07:20:19.29#ibcon#about to read 6, iclass 37, count 2 2006.246.07:20:19.29#ibcon#read 6, iclass 37, count 2 2006.246.07:20:19.29#ibcon#end of sib2, iclass 37, count 2 2006.246.07:20:19.29#ibcon#*after write, iclass 37, count 2 2006.246.07:20:19.29#ibcon#*before return 0, iclass 37, count 2 2006.246.07:20:19.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:20:19.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:20:19.29#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.07:20:19.29#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:19.29#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:20:19.41#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:20:19.41#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:20:19.41#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:20:19.41#ibcon#first serial, iclass 37, count 0 2006.246.07:20:19.41#ibcon#enter sib2, iclass 37, count 0 2006.246.07:20:19.41#ibcon#flushed, iclass 37, count 0 2006.246.07:20:19.41#ibcon#about to write, iclass 37, count 0 2006.246.07:20:19.41#ibcon#wrote, iclass 37, count 0 2006.246.07:20:19.41#ibcon#about to read 3, iclass 37, count 0 2006.246.07:20:19.43#ibcon#read 3, iclass 37, count 0 2006.246.07:20:19.43#ibcon#about to read 4, iclass 37, count 0 2006.246.07:20:19.43#ibcon#read 4, iclass 37, count 0 2006.246.07:20:19.43#ibcon#about to read 5, iclass 37, count 0 2006.246.07:20:19.43#ibcon#read 5, iclass 37, count 0 2006.246.07:20:19.43#ibcon#about to read 6, iclass 37, count 0 2006.246.07:20:19.43#ibcon#read 6, iclass 37, count 0 2006.246.07:20:19.43#ibcon#end of sib2, iclass 37, count 0 2006.246.07:20:19.43#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:20:19.43#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:20:19.43#ibcon#[25=USB\r\n] 2006.246.07:20:19.43#ibcon#*before write, iclass 37, count 0 2006.246.07:20:19.43#ibcon#enter sib2, iclass 37, count 0 2006.246.07:20:19.43#ibcon#flushed, iclass 37, count 0 2006.246.07:20:19.43#ibcon#about to write, iclass 37, count 0 2006.246.07:20:19.43#ibcon#wrote, iclass 37, count 0 2006.246.07:20:19.43#ibcon#about to read 3, iclass 37, count 0 2006.246.07:20:19.46#ibcon#read 3, iclass 37, count 0 2006.246.07:20:19.46#ibcon#about to read 4, iclass 37, count 0 2006.246.07:20:19.46#ibcon#read 4, iclass 37, count 0 2006.246.07:20:19.46#ibcon#about to read 5, iclass 37, count 0 2006.246.07:20:19.46#ibcon#read 5, iclass 37, count 0 2006.246.07:20:19.46#ibcon#about to read 6, iclass 37, count 0 2006.246.07:20:19.46#ibcon#read 6, iclass 37, count 0 2006.246.07:20:19.46#ibcon#end of sib2, iclass 37, count 0 2006.246.07:20:19.46#ibcon#*after write, iclass 37, count 0 2006.246.07:20:19.46#ibcon#*before return 0, iclass 37, count 0 2006.246.07:20:19.46#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:20:19.46#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:20:19.46#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:20:19.46#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:20:19.46$vc4f8/vblo=1,632.99 2006.246.07:20:19.46#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:20:19.46#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:20:19.46#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:19.46#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:20:19.46#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:20:19.46#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:20:19.46#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:20:19.46#ibcon#first serial, iclass 39, count 0 2006.246.07:20:19.46#ibcon#enter sib2, iclass 39, count 0 2006.246.07:20:19.46#ibcon#flushed, iclass 39, count 0 2006.246.07:20:19.46#ibcon#about to write, iclass 39, count 0 2006.246.07:20:19.46#ibcon#wrote, iclass 39, count 0 2006.246.07:20:19.46#ibcon#about to read 3, iclass 39, count 0 2006.246.07:20:19.48#ibcon#read 3, iclass 39, count 0 2006.246.07:20:19.48#ibcon#about to read 4, iclass 39, count 0 2006.246.07:20:19.48#ibcon#read 4, iclass 39, count 0 2006.246.07:20:19.48#ibcon#about to read 5, iclass 39, count 0 2006.246.07:20:19.48#ibcon#read 5, iclass 39, count 0 2006.246.07:20:19.48#ibcon#about to read 6, iclass 39, count 0 2006.246.07:20:19.48#ibcon#read 6, iclass 39, count 0 2006.246.07:20:19.48#ibcon#end of sib2, iclass 39, count 0 2006.246.07:20:19.48#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:20:19.48#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:20:19.48#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:20:19.48#ibcon#*before write, iclass 39, count 0 2006.246.07:20:19.48#ibcon#enter sib2, iclass 39, count 0 2006.246.07:20:19.48#ibcon#flushed, iclass 39, count 0 2006.246.07:20:19.48#ibcon#about to write, iclass 39, count 0 2006.246.07:20:19.48#ibcon#wrote, iclass 39, count 0 2006.246.07:20:19.48#ibcon#about to read 3, iclass 39, count 0 2006.246.07:20:19.52#ibcon#read 3, iclass 39, count 0 2006.246.07:20:19.52#ibcon#about to read 4, iclass 39, count 0 2006.246.07:20:19.52#ibcon#read 4, iclass 39, count 0 2006.246.07:20:19.52#ibcon#about to read 5, iclass 39, count 0 2006.246.07:20:19.52#ibcon#read 5, iclass 39, count 0 2006.246.07:20:19.52#ibcon#about to read 6, iclass 39, count 0 2006.246.07:20:19.52#ibcon#read 6, iclass 39, count 0 2006.246.07:20:19.52#ibcon#end of sib2, iclass 39, count 0 2006.246.07:20:19.52#ibcon#*after write, iclass 39, count 0 2006.246.07:20:19.52#ibcon#*before return 0, iclass 39, count 0 2006.246.07:20:19.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:20:19.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:20:19.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:20:19.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:20:19.52$vc4f8/vb=1,4 2006.246.07:20:19.52#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.07:20:19.52#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.07:20:19.52#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:19.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:20:19.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:20:19.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:20:19.52#ibcon#enter wrdev, iclass 3, count 2 2006.246.07:20:19.52#ibcon#first serial, iclass 3, count 2 2006.246.07:20:19.52#ibcon#enter sib2, iclass 3, count 2 2006.246.07:20:19.52#ibcon#flushed, iclass 3, count 2 2006.246.07:20:19.52#ibcon#about to write, iclass 3, count 2 2006.246.07:20:19.52#ibcon#wrote, iclass 3, count 2 2006.246.07:20:19.52#ibcon#about to read 3, iclass 3, count 2 2006.246.07:20:19.54#ibcon#read 3, iclass 3, count 2 2006.246.07:20:19.54#ibcon#about to read 4, iclass 3, count 2 2006.246.07:20:19.54#ibcon#read 4, iclass 3, count 2 2006.246.07:20:19.54#ibcon#about to read 5, iclass 3, count 2 2006.246.07:20:19.54#ibcon#read 5, iclass 3, count 2 2006.246.07:20:19.54#ibcon#about to read 6, iclass 3, count 2 2006.246.07:20:19.54#ibcon#read 6, iclass 3, count 2 2006.246.07:20:19.54#ibcon#end of sib2, iclass 3, count 2 2006.246.07:20:19.54#ibcon#*mode == 0, iclass 3, count 2 2006.246.07:20:19.54#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.07:20:19.54#ibcon#[27=AT01-04\r\n] 2006.246.07:20:19.54#ibcon#*before write, iclass 3, count 2 2006.246.07:20:19.54#ibcon#enter sib2, iclass 3, count 2 2006.246.07:20:19.54#ibcon#flushed, iclass 3, count 2 2006.246.07:20:19.54#ibcon#about to write, iclass 3, count 2 2006.246.07:20:19.54#ibcon#wrote, iclass 3, count 2 2006.246.07:20:19.54#ibcon#about to read 3, iclass 3, count 2 2006.246.07:20:19.57#ibcon#read 3, iclass 3, count 2 2006.246.07:20:19.57#ibcon#about to read 4, iclass 3, count 2 2006.246.07:20:19.57#ibcon#read 4, iclass 3, count 2 2006.246.07:20:19.57#ibcon#about to read 5, iclass 3, count 2 2006.246.07:20:19.57#ibcon#read 5, iclass 3, count 2 2006.246.07:20:19.57#ibcon#about to read 6, iclass 3, count 2 2006.246.07:20:19.57#ibcon#read 6, iclass 3, count 2 2006.246.07:20:19.57#ibcon#end of sib2, iclass 3, count 2 2006.246.07:20:19.57#ibcon#*after write, iclass 3, count 2 2006.246.07:20:19.57#ibcon#*before return 0, iclass 3, count 2 2006.246.07:20:19.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:20:19.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:20:19.57#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.07:20:19.57#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:19.57#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:20:19.69#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:20:19.69#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:20:19.69#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:20:19.69#ibcon#first serial, iclass 3, count 0 2006.246.07:20:19.69#ibcon#enter sib2, iclass 3, count 0 2006.246.07:20:19.69#ibcon#flushed, iclass 3, count 0 2006.246.07:20:19.69#ibcon#about to write, iclass 3, count 0 2006.246.07:20:19.69#ibcon#wrote, iclass 3, count 0 2006.246.07:20:19.69#ibcon#about to read 3, iclass 3, count 0 2006.246.07:20:19.71#ibcon#read 3, iclass 3, count 0 2006.246.07:20:19.71#ibcon#about to read 4, iclass 3, count 0 2006.246.07:20:19.71#ibcon#read 4, iclass 3, count 0 2006.246.07:20:19.71#ibcon#about to read 5, iclass 3, count 0 2006.246.07:20:19.71#ibcon#read 5, iclass 3, count 0 2006.246.07:20:19.71#ibcon#about to read 6, iclass 3, count 0 2006.246.07:20:19.71#ibcon#read 6, iclass 3, count 0 2006.246.07:20:19.71#ibcon#end of sib2, iclass 3, count 0 2006.246.07:20:19.71#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:20:19.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:20:19.71#ibcon#[27=USB\r\n] 2006.246.07:20:19.71#ibcon#*before write, iclass 3, count 0 2006.246.07:20:19.71#ibcon#enter sib2, iclass 3, count 0 2006.246.07:20:19.71#ibcon#flushed, iclass 3, count 0 2006.246.07:20:19.71#ibcon#about to write, iclass 3, count 0 2006.246.07:20:19.71#ibcon#wrote, iclass 3, count 0 2006.246.07:20:19.71#ibcon#about to read 3, iclass 3, count 0 2006.246.07:20:19.74#ibcon#read 3, iclass 3, count 0 2006.246.07:20:19.74#ibcon#about to read 4, iclass 3, count 0 2006.246.07:20:19.74#ibcon#read 4, iclass 3, count 0 2006.246.07:20:19.74#ibcon#about to read 5, iclass 3, count 0 2006.246.07:20:19.74#ibcon#read 5, iclass 3, count 0 2006.246.07:20:19.74#ibcon#about to read 6, iclass 3, count 0 2006.246.07:20:19.74#ibcon#read 6, iclass 3, count 0 2006.246.07:20:19.74#ibcon#end of sib2, iclass 3, count 0 2006.246.07:20:19.74#ibcon#*after write, iclass 3, count 0 2006.246.07:20:19.74#ibcon#*before return 0, iclass 3, count 0 2006.246.07:20:19.74#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:20:19.74#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:20:19.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:20:19.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:20:19.74$vc4f8/vblo=2,640.99 2006.246.07:20:19.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:20:19.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:20:19.74#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:19.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:19.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:19.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:19.74#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:20:19.74#ibcon#first serial, iclass 5, count 0 2006.246.07:20:19.74#ibcon#enter sib2, iclass 5, count 0 2006.246.07:20:19.74#ibcon#flushed, iclass 5, count 0 2006.246.07:20:19.74#ibcon#about to write, iclass 5, count 0 2006.246.07:20:19.74#ibcon#wrote, iclass 5, count 0 2006.246.07:20:19.74#ibcon#about to read 3, iclass 5, count 0 2006.246.07:20:19.76#ibcon#read 3, iclass 5, count 0 2006.246.07:20:19.76#ibcon#about to read 4, iclass 5, count 0 2006.246.07:20:19.76#ibcon#read 4, iclass 5, count 0 2006.246.07:20:19.76#ibcon#about to read 5, iclass 5, count 0 2006.246.07:20:19.76#ibcon#read 5, iclass 5, count 0 2006.246.07:20:19.76#ibcon#about to read 6, iclass 5, count 0 2006.246.07:20:19.76#ibcon#read 6, iclass 5, count 0 2006.246.07:20:19.76#ibcon#end of sib2, iclass 5, count 0 2006.246.07:20:19.76#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:20:19.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:20:19.76#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:20:19.76#ibcon#*before write, iclass 5, count 0 2006.246.07:20:19.76#ibcon#enter sib2, iclass 5, count 0 2006.246.07:20:19.76#ibcon#flushed, iclass 5, count 0 2006.246.07:20:19.76#ibcon#about to write, iclass 5, count 0 2006.246.07:20:19.76#ibcon#wrote, iclass 5, count 0 2006.246.07:20:19.76#ibcon#about to read 3, iclass 5, count 0 2006.246.07:20:19.80#ibcon#read 3, iclass 5, count 0 2006.246.07:20:19.80#ibcon#about to read 4, iclass 5, count 0 2006.246.07:20:19.80#ibcon#read 4, iclass 5, count 0 2006.246.07:20:19.80#ibcon#about to read 5, iclass 5, count 0 2006.246.07:20:19.80#ibcon#read 5, iclass 5, count 0 2006.246.07:20:19.80#ibcon#about to read 6, iclass 5, count 0 2006.246.07:20:19.80#ibcon#read 6, iclass 5, count 0 2006.246.07:20:19.80#ibcon#end of sib2, iclass 5, count 0 2006.246.07:20:19.80#ibcon#*after write, iclass 5, count 0 2006.246.07:20:19.80#ibcon#*before return 0, iclass 5, count 0 2006.246.07:20:19.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:19.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:20:19.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:20:19.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:20:19.80$vc4f8/vb=2,4 2006.246.07:20:19.80#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:20:19.80#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:20:19.80#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:19.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:19.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:19.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:19.86#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:20:19.86#ibcon#first serial, iclass 7, count 2 2006.246.07:20:19.86#ibcon#enter sib2, iclass 7, count 2 2006.246.07:20:19.86#ibcon#flushed, iclass 7, count 2 2006.246.07:20:19.86#ibcon#about to write, iclass 7, count 2 2006.246.07:20:19.86#ibcon#wrote, iclass 7, count 2 2006.246.07:20:19.86#ibcon#about to read 3, iclass 7, count 2 2006.246.07:20:19.88#ibcon#read 3, iclass 7, count 2 2006.246.07:20:19.88#ibcon#about to read 4, iclass 7, count 2 2006.246.07:20:19.88#ibcon#read 4, iclass 7, count 2 2006.246.07:20:19.88#ibcon#about to read 5, iclass 7, count 2 2006.246.07:20:19.88#ibcon#read 5, iclass 7, count 2 2006.246.07:20:19.88#ibcon#about to read 6, iclass 7, count 2 2006.246.07:20:19.88#ibcon#read 6, iclass 7, count 2 2006.246.07:20:19.88#ibcon#end of sib2, iclass 7, count 2 2006.246.07:20:19.88#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:20:19.88#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:20:19.88#ibcon#[27=AT02-04\r\n] 2006.246.07:20:19.88#ibcon#*before write, iclass 7, count 2 2006.246.07:20:19.88#ibcon#enter sib2, iclass 7, count 2 2006.246.07:20:19.88#ibcon#flushed, iclass 7, count 2 2006.246.07:20:19.88#ibcon#about to write, iclass 7, count 2 2006.246.07:20:19.88#ibcon#wrote, iclass 7, count 2 2006.246.07:20:19.88#ibcon#about to read 3, iclass 7, count 2 2006.246.07:20:19.91#ibcon#read 3, iclass 7, count 2 2006.246.07:20:19.91#ibcon#about to read 4, iclass 7, count 2 2006.246.07:20:19.91#ibcon#read 4, iclass 7, count 2 2006.246.07:20:19.91#ibcon#about to read 5, iclass 7, count 2 2006.246.07:20:19.91#ibcon#read 5, iclass 7, count 2 2006.246.07:20:19.91#ibcon#about to read 6, iclass 7, count 2 2006.246.07:20:19.91#ibcon#read 6, iclass 7, count 2 2006.246.07:20:19.91#ibcon#end of sib2, iclass 7, count 2 2006.246.07:20:19.91#ibcon#*after write, iclass 7, count 2 2006.246.07:20:19.91#ibcon#*before return 0, iclass 7, count 2 2006.246.07:20:19.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:19.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:20:19.91#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:20:19.91#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:19.91#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:20.03#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:20.03#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:20.03#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:20:20.03#ibcon#first serial, iclass 7, count 0 2006.246.07:20:20.03#ibcon#enter sib2, iclass 7, count 0 2006.246.07:20:20.03#ibcon#flushed, iclass 7, count 0 2006.246.07:20:20.03#ibcon#about to write, iclass 7, count 0 2006.246.07:20:20.03#ibcon#wrote, iclass 7, count 0 2006.246.07:20:20.03#ibcon#about to read 3, iclass 7, count 0 2006.246.07:20:20.05#ibcon#read 3, iclass 7, count 0 2006.246.07:20:20.05#ibcon#about to read 4, iclass 7, count 0 2006.246.07:20:20.05#ibcon#read 4, iclass 7, count 0 2006.246.07:20:20.05#ibcon#about to read 5, iclass 7, count 0 2006.246.07:20:20.05#ibcon#read 5, iclass 7, count 0 2006.246.07:20:20.05#ibcon#about to read 6, iclass 7, count 0 2006.246.07:20:20.05#ibcon#read 6, iclass 7, count 0 2006.246.07:20:20.05#ibcon#end of sib2, iclass 7, count 0 2006.246.07:20:20.05#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:20:20.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:20:20.05#ibcon#[27=USB\r\n] 2006.246.07:20:20.05#ibcon#*before write, iclass 7, count 0 2006.246.07:20:20.05#ibcon#enter sib2, iclass 7, count 0 2006.246.07:20:20.05#ibcon#flushed, iclass 7, count 0 2006.246.07:20:20.05#ibcon#about to write, iclass 7, count 0 2006.246.07:20:20.05#ibcon#wrote, iclass 7, count 0 2006.246.07:20:20.05#ibcon#about to read 3, iclass 7, count 0 2006.246.07:20:20.08#ibcon#read 3, iclass 7, count 0 2006.246.07:20:20.08#ibcon#about to read 4, iclass 7, count 0 2006.246.07:20:20.08#ibcon#read 4, iclass 7, count 0 2006.246.07:20:20.08#ibcon#about to read 5, iclass 7, count 0 2006.246.07:20:20.08#ibcon#read 5, iclass 7, count 0 2006.246.07:20:20.08#ibcon#about to read 6, iclass 7, count 0 2006.246.07:20:20.08#ibcon#read 6, iclass 7, count 0 2006.246.07:20:20.08#ibcon#end of sib2, iclass 7, count 0 2006.246.07:20:20.08#ibcon#*after write, iclass 7, count 0 2006.246.07:20:20.08#ibcon#*before return 0, iclass 7, count 0 2006.246.07:20:20.08#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:20.08#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:20:20.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:20:20.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:20:20.08$vc4f8/vblo=3,656.99 2006.246.07:20:20.08#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:20:20.08#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:20:20.08#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:20.08#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:20.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:20.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:20.08#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:20:20.08#ibcon#first serial, iclass 11, count 0 2006.246.07:20:20.08#ibcon#enter sib2, iclass 11, count 0 2006.246.07:20:20.08#ibcon#flushed, iclass 11, count 0 2006.246.07:20:20.08#ibcon#about to write, iclass 11, count 0 2006.246.07:20:20.08#ibcon#wrote, iclass 11, count 0 2006.246.07:20:20.08#ibcon#about to read 3, iclass 11, count 0 2006.246.07:20:20.10#ibcon#read 3, iclass 11, count 0 2006.246.07:20:20.10#ibcon#about to read 4, iclass 11, count 0 2006.246.07:20:20.10#ibcon#read 4, iclass 11, count 0 2006.246.07:20:20.10#ibcon#about to read 5, iclass 11, count 0 2006.246.07:20:20.10#ibcon#read 5, iclass 11, count 0 2006.246.07:20:20.10#ibcon#about to read 6, iclass 11, count 0 2006.246.07:20:20.10#ibcon#read 6, iclass 11, count 0 2006.246.07:20:20.10#ibcon#end of sib2, iclass 11, count 0 2006.246.07:20:20.10#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:20:20.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:20:20.10#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:20:20.10#ibcon#*before write, iclass 11, count 0 2006.246.07:20:20.10#ibcon#enter sib2, iclass 11, count 0 2006.246.07:20:20.10#ibcon#flushed, iclass 11, count 0 2006.246.07:20:20.10#ibcon#about to write, iclass 11, count 0 2006.246.07:20:20.10#ibcon#wrote, iclass 11, count 0 2006.246.07:20:20.10#ibcon#about to read 3, iclass 11, count 0 2006.246.07:20:20.14#ibcon#read 3, iclass 11, count 0 2006.246.07:20:20.14#ibcon#about to read 4, iclass 11, count 0 2006.246.07:20:20.14#ibcon#read 4, iclass 11, count 0 2006.246.07:20:20.14#ibcon#about to read 5, iclass 11, count 0 2006.246.07:20:20.14#ibcon#read 5, iclass 11, count 0 2006.246.07:20:20.14#ibcon#about to read 6, iclass 11, count 0 2006.246.07:20:20.14#ibcon#read 6, iclass 11, count 0 2006.246.07:20:20.14#ibcon#end of sib2, iclass 11, count 0 2006.246.07:20:20.14#ibcon#*after write, iclass 11, count 0 2006.246.07:20:20.14#ibcon#*before return 0, iclass 11, count 0 2006.246.07:20:20.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:20.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:20:20.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:20:20.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:20:20.14$vc4f8/vb=3,4 2006.246.07:20:20.14#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:20:20.14#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:20:20.14#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:20.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:20.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:20.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:20.20#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:20:20.20#ibcon#first serial, iclass 13, count 2 2006.246.07:20:20.20#ibcon#enter sib2, iclass 13, count 2 2006.246.07:20:20.20#ibcon#flushed, iclass 13, count 2 2006.246.07:20:20.20#ibcon#about to write, iclass 13, count 2 2006.246.07:20:20.20#ibcon#wrote, iclass 13, count 2 2006.246.07:20:20.20#ibcon#about to read 3, iclass 13, count 2 2006.246.07:20:20.22#ibcon#read 3, iclass 13, count 2 2006.246.07:20:20.22#ibcon#about to read 4, iclass 13, count 2 2006.246.07:20:20.22#ibcon#read 4, iclass 13, count 2 2006.246.07:20:20.22#ibcon#about to read 5, iclass 13, count 2 2006.246.07:20:20.22#ibcon#read 5, iclass 13, count 2 2006.246.07:20:20.22#ibcon#about to read 6, iclass 13, count 2 2006.246.07:20:20.22#ibcon#read 6, iclass 13, count 2 2006.246.07:20:20.22#ibcon#end of sib2, iclass 13, count 2 2006.246.07:20:20.22#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:20:20.22#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:20:20.22#ibcon#[27=AT03-04\r\n] 2006.246.07:20:20.22#ibcon#*before write, iclass 13, count 2 2006.246.07:20:20.22#ibcon#enter sib2, iclass 13, count 2 2006.246.07:20:20.22#ibcon#flushed, iclass 13, count 2 2006.246.07:20:20.22#ibcon#about to write, iclass 13, count 2 2006.246.07:20:20.22#ibcon#wrote, iclass 13, count 2 2006.246.07:20:20.22#ibcon#about to read 3, iclass 13, count 2 2006.246.07:20:20.25#ibcon#read 3, iclass 13, count 2 2006.246.07:20:20.25#ibcon#about to read 4, iclass 13, count 2 2006.246.07:20:20.25#ibcon#read 4, iclass 13, count 2 2006.246.07:20:20.25#ibcon#about to read 5, iclass 13, count 2 2006.246.07:20:20.25#ibcon#read 5, iclass 13, count 2 2006.246.07:20:20.25#ibcon#about to read 6, iclass 13, count 2 2006.246.07:20:20.25#ibcon#read 6, iclass 13, count 2 2006.246.07:20:20.25#ibcon#end of sib2, iclass 13, count 2 2006.246.07:20:20.25#ibcon#*after write, iclass 13, count 2 2006.246.07:20:20.25#ibcon#*before return 0, iclass 13, count 2 2006.246.07:20:20.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:20.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:20:20.25#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:20:20.25#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:20.25#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:20.37#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:20.37#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:20.37#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:20:20.37#ibcon#first serial, iclass 13, count 0 2006.246.07:20:20.37#ibcon#enter sib2, iclass 13, count 0 2006.246.07:20:20.37#ibcon#flushed, iclass 13, count 0 2006.246.07:20:20.37#ibcon#about to write, iclass 13, count 0 2006.246.07:20:20.37#ibcon#wrote, iclass 13, count 0 2006.246.07:20:20.37#ibcon#about to read 3, iclass 13, count 0 2006.246.07:20:20.39#ibcon#read 3, iclass 13, count 0 2006.246.07:20:20.39#ibcon#about to read 4, iclass 13, count 0 2006.246.07:20:20.39#ibcon#read 4, iclass 13, count 0 2006.246.07:20:20.39#ibcon#about to read 5, iclass 13, count 0 2006.246.07:20:20.39#ibcon#read 5, iclass 13, count 0 2006.246.07:20:20.39#ibcon#about to read 6, iclass 13, count 0 2006.246.07:20:20.39#ibcon#read 6, iclass 13, count 0 2006.246.07:20:20.39#ibcon#end of sib2, iclass 13, count 0 2006.246.07:20:20.39#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:20:20.39#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:20:20.39#ibcon#[27=USB\r\n] 2006.246.07:20:20.39#ibcon#*before write, iclass 13, count 0 2006.246.07:20:20.39#ibcon#enter sib2, iclass 13, count 0 2006.246.07:20:20.39#ibcon#flushed, iclass 13, count 0 2006.246.07:20:20.39#ibcon#about to write, iclass 13, count 0 2006.246.07:20:20.39#ibcon#wrote, iclass 13, count 0 2006.246.07:20:20.39#ibcon#about to read 3, iclass 13, count 0 2006.246.07:20:20.42#ibcon#read 3, iclass 13, count 0 2006.246.07:20:20.42#ibcon#about to read 4, iclass 13, count 0 2006.246.07:20:20.42#ibcon#read 4, iclass 13, count 0 2006.246.07:20:20.42#ibcon#about to read 5, iclass 13, count 0 2006.246.07:20:20.42#ibcon#read 5, iclass 13, count 0 2006.246.07:20:20.42#ibcon#about to read 6, iclass 13, count 0 2006.246.07:20:20.42#ibcon#read 6, iclass 13, count 0 2006.246.07:20:20.42#ibcon#end of sib2, iclass 13, count 0 2006.246.07:20:20.42#ibcon#*after write, iclass 13, count 0 2006.246.07:20:20.42#ibcon#*before return 0, iclass 13, count 0 2006.246.07:20:20.42#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:20.42#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:20:20.42#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:20:20.42#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:20:20.42$vc4f8/vblo=4,712.99 2006.246.07:20:20.42#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:20:20.42#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:20:20.42#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:20.42#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:20.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:20.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:20.42#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:20:20.42#ibcon#first serial, iclass 15, count 0 2006.246.07:20:20.42#ibcon#enter sib2, iclass 15, count 0 2006.246.07:20:20.42#ibcon#flushed, iclass 15, count 0 2006.246.07:20:20.42#ibcon#about to write, iclass 15, count 0 2006.246.07:20:20.42#ibcon#wrote, iclass 15, count 0 2006.246.07:20:20.42#ibcon#about to read 3, iclass 15, count 0 2006.246.07:20:20.44#ibcon#read 3, iclass 15, count 0 2006.246.07:20:20.44#ibcon#about to read 4, iclass 15, count 0 2006.246.07:20:20.44#ibcon#read 4, iclass 15, count 0 2006.246.07:20:20.44#ibcon#about to read 5, iclass 15, count 0 2006.246.07:20:20.44#ibcon#read 5, iclass 15, count 0 2006.246.07:20:20.44#ibcon#about to read 6, iclass 15, count 0 2006.246.07:20:20.44#ibcon#read 6, iclass 15, count 0 2006.246.07:20:20.44#ibcon#end of sib2, iclass 15, count 0 2006.246.07:20:20.44#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:20:20.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:20:20.44#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:20:20.44#ibcon#*before write, iclass 15, count 0 2006.246.07:20:20.44#ibcon#enter sib2, iclass 15, count 0 2006.246.07:20:20.44#ibcon#flushed, iclass 15, count 0 2006.246.07:20:20.44#ibcon#about to write, iclass 15, count 0 2006.246.07:20:20.44#ibcon#wrote, iclass 15, count 0 2006.246.07:20:20.44#ibcon#about to read 3, iclass 15, count 0 2006.246.07:20:20.48#ibcon#read 3, iclass 15, count 0 2006.246.07:20:20.48#ibcon#about to read 4, iclass 15, count 0 2006.246.07:20:20.48#ibcon#read 4, iclass 15, count 0 2006.246.07:20:20.48#ibcon#about to read 5, iclass 15, count 0 2006.246.07:20:20.48#ibcon#read 5, iclass 15, count 0 2006.246.07:20:20.48#ibcon#about to read 6, iclass 15, count 0 2006.246.07:20:20.48#ibcon#read 6, iclass 15, count 0 2006.246.07:20:20.48#ibcon#end of sib2, iclass 15, count 0 2006.246.07:20:20.48#ibcon#*after write, iclass 15, count 0 2006.246.07:20:20.48#ibcon#*before return 0, iclass 15, count 0 2006.246.07:20:20.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:20.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:20:20.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:20:20.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:20:20.48$vc4f8/vb=4,4 2006.246.07:20:20.48#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.07:20:20.48#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.07:20:20.48#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:20.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:20.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:20.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:20.54#ibcon#enter wrdev, iclass 17, count 2 2006.246.07:20:20.54#ibcon#first serial, iclass 17, count 2 2006.246.07:20:20.54#ibcon#enter sib2, iclass 17, count 2 2006.246.07:20:20.54#ibcon#flushed, iclass 17, count 2 2006.246.07:20:20.54#ibcon#about to write, iclass 17, count 2 2006.246.07:20:20.54#ibcon#wrote, iclass 17, count 2 2006.246.07:20:20.54#ibcon#about to read 3, iclass 17, count 2 2006.246.07:20:20.56#ibcon#read 3, iclass 17, count 2 2006.246.07:20:20.56#ibcon#about to read 4, iclass 17, count 2 2006.246.07:20:20.56#ibcon#read 4, iclass 17, count 2 2006.246.07:20:20.56#ibcon#about to read 5, iclass 17, count 2 2006.246.07:20:20.56#ibcon#read 5, iclass 17, count 2 2006.246.07:20:20.56#ibcon#about to read 6, iclass 17, count 2 2006.246.07:20:20.56#ibcon#read 6, iclass 17, count 2 2006.246.07:20:20.56#ibcon#end of sib2, iclass 17, count 2 2006.246.07:20:20.56#ibcon#*mode == 0, iclass 17, count 2 2006.246.07:20:20.56#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.07:20:20.56#ibcon#[27=AT04-04\r\n] 2006.246.07:20:20.56#ibcon#*before write, iclass 17, count 2 2006.246.07:20:20.56#ibcon#enter sib2, iclass 17, count 2 2006.246.07:20:20.56#ibcon#flushed, iclass 17, count 2 2006.246.07:20:20.56#ibcon#about to write, iclass 17, count 2 2006.246.07:20:20.56#ibcon#wrote, iclass 17, count 2 2006.246.07:20:20.56#ibcon#about to read 3, iclass 17, count 2 2006.246.07:20:20.59#ibcon#read 3, iclass 17, count 2 2006.246.07:20:20.59#ibcon#about to read 4, iclass 17, count 2 2006.246.07:20:20.59#ibcon#read 4, iclass 17, count 2 2006.246.07:20:20.59#ibcon#about to read 5, iclass 17, count 2 2006.246.07:20:20.59#ibcon#read 5, iclass 17, count 2 2006.246.07:20:20.59#ibcon#about to read 6, iclass 17, count 2 2006.246.07:20:20.59#ibcon#read 6, iclass 17, count 2 2006.246.07:20:20.59#ibcon#end of sib2, iclass 17, count 2 2006.246.07:20:20.59#ibcon#*after write, iclass 17, count 2 2006.246.07:20:20.59#ibcon#*before return 0, iclass 17, count 2 2006.246.07:20:20.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:20.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:20:20.59#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.07:20:20.59#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:20.59#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:20.71#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:20.71#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:20.71#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:20:20.71#ibcon#first serial, iclass 17, count 0 2006.246.07:20:20.71#ibcon#enter sib2, iclass 17, count 0 2006.246.07:20:20.71#ibcon#flushed, iclass 17, count 0 2006.246.07:20:20.71#ibcon#about to write, iclass 17, count 0 2006.246.07:20:20.71#ibcon#wrote, iclass 17, count 0 2006.246.07:20:20.71#ibcon#about to read 3, iclass 17, count 0 2006.246.07:20:20.73#ibcon#read 3, iclass 17, count 0 2006.246.07:20:20.73#ibcon#about to read 4, iclass 17, count 0 2006.246.07:20:20.73#ibcon#read 4, iclass 17, count 0 2006.246.07:20:20.73#ibcon#about to read 5, iclass 17, count 0 2006.246.07:20:20.73#ibcon#read 5, iclass 17, count 0 2006.246.07:20:20.73#ibcon#about to read 6, iclass 17, count 0 2006.246.07:20:20.73#ibcon#read 6, iclass 17, count 0 2006.246.07:20:20.73#ibcon#end of sib2, iclass 17, count 0 2006.246.07:20:20.73#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:20:20.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:20:20.73#ibcon#[27=USB\r\n] 2006.246.07:20:20.73#ibcon#*before write, iclass 17, count 0 2006.246.07:20:20.73#ibcon#enter sib2, iclass 17, count 0 2006.246.07:20:20.73#ibcon#flushed, iclass 17, count 0 2006.246.07:20:20.73#ibcon#about to write, iclass 17, count 0 2006.246.07:20:20.73#ibcon#wrote, iclass 17, count 0 2006.246.07:20:20.73#ibcon#about to read 3, iclass 17, count 0 2006.246.07:20:20.76#ibcon#read 3, iclass 17, count 0 2006.246.07:20:20.76#ibcon#about to read 4, iclass 17, count 0 2006.246.07:20:20.76#ibcon#read 4, iclass 17, count 0 2006.246.07:20:20.76#ibcon#about to read 5, iclass 17, count 0 2006.246.07:20:20.76#ibcon#read 5, iclass 17, count 0 2006.246.07:20:20.76#ibcon#about to read 6, iclass 17, count 0 2006.246.07:20:20.76#ibcon#read 6, iclass 17, count 0 2006.246.07:20:20.76#ibcon#end of sib2, iclass 17, count 0 2006.246.07:20:20.76#ibcon#*after write, iclass 17, count 0 2006.246.07:20:20.76#ibcon#*before return 0, iclass 17, count 0 2006.246.07:20:20.76#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:20.76#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:20:20.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:20:20.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:20:20.76$vc4f8/vblo=5,744.99 2006.246.07:20:20.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:20:20.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:20:20.76#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:20.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:20.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:20.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:20.76#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:20:20.76#ibcon#first serial, iclass 19, count 0 2006.246.07:20:20.76#ibcon#enter sib2, iclass 19, count 0 2006.246.07:20:20.76#ibcon#flushed, iclass 19, count 0 2006.246.07:20:20.76#ibcon#about to write, iclass 19, count 0 2006.246.07:20:20.76#ibcon#wrote, iclass 19, count 0 2006.246.07:20:20.76#ibcon#about to read 3, iclass 19, count 0 2006.246.07:20:20.78#ibcon#read 3, iclass 19, count 0 2006.246.07:20:20.78#ibcon#about to read 4, iclass 19, count 0 2006.246.07:20:20.78#ibcon#read 4, iclass 19, count 0 2006.246.07:20:20.78#ibcon#about to read 5, iclass 19, count 0 2006.246.07:20:20.78#ibcon#read 5, iclass 19, count 0 2006.246.07:20:20.78#ibcon#about to read 6, iclass 19, count 0 2006.246.07:20:20.78#ibcon#read 6, iclass 19, count 0 2006.246.07:20:20.78#ibcon#end of sib2, iclass 19, count 0 2006.246.07:20:20.78#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:20:20.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:20:20.78#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:20:20.78#ibcon#*before write, iclass 19, count 0 2006.246.07:20:20.78#ibcon#enter sib2, iclass 19, count 0 2006.246.07:20:20.78#ibcon#flushed, iclass 19, count 0 2006.246.07:20:20.78#ibcon#about to write, iclass 19, count 0 2006.246.07:20:20.78#ibcon#wrote, iclass 19, count 0 2006.246.07:20:20.78#ibcon#about to read 3, iclass 19, count 0 2006.246.07:20:20.82#ibcon#read 3, iclass 19, count 0 2006.246.07:20:20.82#ibcon#about to read 4, iclass 19, count 0 2006.246.07:20:20.82#ibcon#read 4, iclass 19, count 0 2006.246.07:20:20.82#ibcon#about to read 5, iclass 19, count 0 2006.246.07:20:20.82#ibcon#read 5, iclass 19, count 0 2006.246.07:20:20.82#ibcon#about to read 6, iclass 19, count 0 2006.246.07:20:20.82#ibcon#read 6, iclass 19, count 0 2006.246.07:20:20.82#ibcon#end of sib2, iclass 19, count 0 2006.246.07:20:20.82#ibcon#*after write, iclass 19, count 0 2006.246.07:20:20.82#ibcon#*before return 0, iclass 19, count 0 2006.246.07:20:20.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:20.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:20:20.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:20:20.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:20:20.82$vc4f8/vb=5,3 2006.246.07:20:20.82#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:20:20.82#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:20:20.82#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:20.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:20.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:20.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:20.88#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:20:20.88#ibcon#first serial, iclass 21, count 2 2006.246.07:20:20.88#ibcon#enter sib2, iclass 21, count 2 2006.246.07:20:20.88#ibcon#flushed, iclass 21, count 2 2006.246.07:20:20.88#ibcon#about to write, iclass 21, count 2 2006.246.07:20:20.88#ibcon#wrote, iclass 21, count 2 2006.246.07:20:20.88#ibcon#about to read 3, iclass 21, count 2 2006.246.07:20:20.90#ibcon#read 3, iclass 21, count 2 2006.246.07:20:20.90#ibcon#about to read 4, iclass 21, count 2 2006.246.07:20:20.90#ibcon#read 4, iclass 21, count 2 2006.246.07:20:20.90#ibcon#about to read 5, iclass 21, count 2 2006.246.07:20:20.90#ibcon#read 5, iclass 21, count 2 2006.246.07:20:20.90#ibcon#about to read 6, iclass 21, count 2 2006.246.07:20:20.90#ibcon#read 6, iclass 21, count 2 2006.246.07:20:20.90#ibcon#end of sib2, iclass 21, count 2 2006.246.07:20:20.90#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:20:20.90#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:20:20.90#ibcon#[27=AT05-03\r\n] 2006.246.07:20:20.90#ibcon#*before write, iclass 21, count 2 2006.246.07:20:20.90#ibcon#enter sib2, iclass 21, count 2 2006.246.07:20:20.90#ibcon#flushed, iclass 21, count 2 2006.246.07:20:20.90#ibcon#about to write, iclass 21, count 2 2006.246.07:20:20.90#ibcon#wrote, iclass 21, count 2 2006.246.07:20:20.90#ibcon#about to read 3, iclass 21, count 2 2006.246.07:20:20.93#ibcon#read 3, iclass 21, count 2 2006.246.07:20:20.93#ibcon#about to read 4, iclass 21, count 2 2006.246.07:20:20.93#ibcon#read 4, iclass 21, count 2 2006.246.07:20:20.93#ibcon#about to read 5, iclass 21, count 2 2006.246.07:20:20.93#ibcon#read 5, iclass 21, count 2 2006.246.07:20:20.93#ibcon#about to read 6, iclass 21, count 2 2006.246.07:20:20.93#ibcon#read 6, iclass 21, count 2 2006.246.07:20:20.93#ibcon#end of sib2, iclass 21, count 2 2006.246.07:20:20.93#ibcon#*after write, iclass 21, count 2 2006.246.07:20:20.93#ibcon#*before return 0, iclass 21, count 2 2006.246.07:20:20.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:20.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:20:20.93#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:20:20.93#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:20.93#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:21.05#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:21.05#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:21.05#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:20:21.05#ibcon#first serial, iclass 21, count 0 2006.246.07:20:21.05#ibcon#enter sib2, iclass 21, count 0 2006.246.07:20:21.05#ibcon#flushed, iclass 21, count 0 2006.246.07:20:21.05#ibcon#about to write, iclass 21, count 0 2006.246.07:20:21.05#ibcon#wrote, iclass 21, count 0 2006.246.07:20:21.05#ibcon#about to read 3, iclass 21, count 0 2006.246.07:20:21.07#ibcon#read 3, iclass 21, count 0 2006.246.07:20:21.07#ibcon#about to read 4, iclass 21, count 0 2006.246.07:20:21.07#ibcon#read 4, iclass 21, count 0 2006.246.07:20:21.07#ibcon#about to read 5, iclass 21, count 0 2006.246.07:20:21.07#ibcon#read 5, iclass 21, count 0 2006.246.07:20:21.07#ibcon#about to read 6, iclass 21, count 0 2006.246.07:20:21.07#ibcon#read 6, iclass 21, count 0 2006.246.07:20:21.07#ibcon#end of sib2, iclass 21, count 0 2006.246.07:20:21.07#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:20:21.07#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:20:21.07#ibcon#[27=USB\r\n] 2006.246.07:20:21.07#ibcon#*before write, iclass 21, count 0 2006.246.07:20:21.07#ibcon#enter sib2, iclass 21, count 0 2006.246.07:20:21.07#ibcon#flushed, iclass 21, count 0 2006.246.07:20:21.07#ibcon#about to write, iclass 21, count 0 2006.246.07:20:21.07#ibcon#wrote, iclass 21, count 0 2006.246.07:20:21.07#ibcon#about to read 3, iclass 21, count 0 2006.246.07:20:21.10#ibcon#read 3, iclass 21, count 0 2006.246.07:20:21.10#ibcon#about to read 4, iclass 21, count 0 2006.246.07:20:21.10#ibcon#read 4, iclass 21, count 0 2006.246.07:20:21.10#ibcon#about to read 5, iclass 21, count 0 2006.246.07:20:21.10#ibcon#read 5, iclass 21, count 0 2006.246.07:20:21.10#ibcon#about to read 6, iclass 21, count 0 2006.246.07:20:21.10#ibcon#read 6, iclass 21, count 0 2006.246.07:20:21.10#ibcon#end of sib2, iclass 21, count 0 2006.246.07:20:21.10#ibcon#*after write, iclass 21, count 0 2006.246.07:20:21.10#ibcon#*before return 0, iclass 21, count 0 2006.246.07:20:21.10#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:21.10#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:20:21.10#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:20:21.10#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:20:21.10$vc4f8/vblo=6,752.99 2006.246.07:20:21.10#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:20:21.10#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:20:21.10#ibcon#ireg 17 cls_cnt 0 2006.246.07:20:21.10#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:21.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:21.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:21.10#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:20:21.10#ibcon#first serial, iclass 23, count 0 2006.246.07:20:21.10#ibcon#enter sib2, iclass 23, count 0 2006.246.07:20:21.10#ibcon#flushed, iclass 23, count 0 2006.246.07:20:21.10#ibcon#about to write, iclass 23, count 0 2006.246.07:20:21.10#ibcon#wrote, iclass 23, count 0 2006.246.07:20:21.10#ibcon#about to read 3, iclass 23, count 0 2006.246.07:20:21.12#ibcon#read 3, iclass 23, count 0 2006.246.07:20:21.12#ibcon#about to read 4, iclass 23, count 0 2006.246.07:20:21.12#ibcon#read 4, iclass 23, count 0 2006.246.07:20:21.12#ibcon#about to read 5, iclass 23, count 0 2006.246.07:20:21.12#ibcon#read 5, iclass 23, count 0 2006.246.07:20:21.12#ibcon#about to read 6, iclass 23, count 0 2006.246.07:20:21.12#ibcon#read 6, iclass 23, count 0 2006.246.07:20:21.12#ibcon#end of sib2, iclass 23, count 0 2006.246.07:20:21.12#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:20:21.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:20:21.12#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:20:21.12#ibcon#*before write, iclass 23, count 0 2006.246.07:20:21.12#ibcon#enter sib2, iclass 23, count 0 2006.246.07:20:21.12#ibcon#flushed, iclass 23, count 0 2006.246.07:20:21.12#ibcon#about to write, iclass 23, count 0 2006.246.07:20:21.12#ibcon#wrote, iclass 23, count 0 2006.246.07:20:21.12#ibcon#about to read 3, iclass 23, count 0 2006.246.07:20:21.16#ibcon#read 3, iclass 23, count 0 2006.246.07:20:21.16#ibcon#about to read 4, iclass 23, count 0 2006.246.07:20:21.16#ibcon#read 4, iclass 23, count 0 2006.246.07:20:21.16#ibcon#about to read 5, iclass 23, count 0 2006.246.07:20:21.16#ibcon#read 5, iclass 23, count 0 2006.246.07:20:21.16#ibcon#about to read 6, iclass 23, count 0 2006.246.07:20:21.16#ibcon#read 6, iclass 23, count 0 2006.246.07:20:21.16#ibcon#end of sib2, iclass 23, count 0 2006.246.07:20:21.16#ibcon#*after write, iclass 23, count 0 2006.246.07:20:21.16#ibcon#*before return 0, iclass 23, count 0 2006.246.07:20:21.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:21.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:20:21.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:20:21.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:20:21.16$vc4f8/vb=6,3 2006.246.07:20:21.16#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:20:21.16#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:20:21.16#ibcon#ireg 11 cls_cnt 2 2006.246.07:20:21.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:21.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:21.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:21.22#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:20:21.22#ibcon#first serial, iclass 25, count 2 2006.246.07:20:21.22#ibcon#enter sib2, iclass 25, count 2 2006.246.07:20:21.22#ibcon#flushed, iclass 25, count 2 2006.246.07:20:21.22#ibcon#about to write, iclass 25, count 2 2006.246.07:20:21.22#ibcon#wrote, iclass 25, count 2 2006.246.07:20:21.22#ibcon#about to read 3, iclass 25, count 2 2006.246.07:20:21.24#ibcon#read 3, iclass 25, count 2 2006.246.07:20:21.24#ibcon#about to read 4, iclass 25, count 2 2006.246.07:20:21.24#ibcon#read 4, iclass 25, count 2 2006.246.07:20:21.24#ibcon#about to read 5, iclass 25, count 2 2006.246.07:20:21.24#ibcon#read 5, iclass 25, count 2 2006.246.07:20:21.24#ibcon#about to read 6, iclass 25, count 2 2006.246.07:20:21.24#ibcon#read 6, iclass 25, count 2 2006.246.07:20:21.24#ibcon#end of sib2, iclass 25, count 2 2006.246.07:20:21.24#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:20:21.24#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:20:21.24#ibcon#[27=AT06-03\r\n] 2006.246.07:20:21.24#ibcon#*before write, iclass 25, count 2 2006.246.07:20:21.24#ibcon#enter sib2, iclass 25, count 2 2006.246.07:20:21.24#ibcon#flushed, iclass 25, count 2 2006.246.07:20:21.24#ibcon#about to write, iclass 25, count 2 2006.246.07:20:21.24#ibcon#wrote, iclass 25, count 2 2006.246.07:20:21.24#ibcon#about to read 3, iclass 25, count 2 2006.246.07:20:21.27#ibcon#read 3, iclass 25, count 2 2006.246.07:20:21.27#ibcon#about to read 4, iclass 25, count 2 2006.246.07:20:21.27#ibcon#read 4, iclass 25, count 2 2006.246.07:20:21.27#ibcon#about to read 5, iclass 25, count 2 2006.246.07:20:21.27#ibcon#read 5, iclass 25, count 2 2006.246.07:20:21.27#ibcon#about to read 6, iclass 25, count 2 2006.246.07:20:21.27#ibcon#read 6, iclass 25, count 2 2006.246.07:20:21.27#ibcon#end of sib2, iclass 25, count 2 2006.246.07:20:21.27#ibcon#*after write, iclass 25, count 2 2006.246.07:20:21.27#ibcon#*before return 0, iclass 25, count 2 2006.246.07:20:21.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:21.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:20:21.27#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:20:21.27#ibcon#ireg 7 cls_cnt 0 2006.246.07:20:21.27#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:21.39#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:21.39#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:21.39#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:20:21.39#ibcon#first serial, iclass 25, count 0 2006.246.07:20:21.39#ibcon#enter sib2, iclass 25, count 0 2006.246.07:20:21.39#ibcon#flushed, iclass 25, count 0 2006.246.07:20:21.39#ibcon#about to write, iclass 25, count 0 2006.246.07:20:21.39#ibcon#wrote, iclass 25, count 0 2006.246.07:20:21.39#ibcon#about to read 3, iclass 25, count 0 2006.246.07:20:21.41#ibcon#read 3, iclass 25, count 0 2006.246.07:20:21.41#ibcon#about to read 4, iclass 25, count 0 2006.246.07:20:21.41#ibcon#read 4, iclass 25, count 0 2006.246.07:20:21.41#ibcon#about to read 5, iclass 25, count 0 2006.246.07:20:21.41#ibcon#read 5, iclass 25, count 0 2006.246.07:20:21.41#ibcon#about to read 6, iclass 25, count 0 2006.246.07:20:21.41#ibcon#read 6, iclass 25, count 0 2006.246.07:20:21.41#ibcon#end of sib2, iclass 25, count 0 2006.246.07:20:21.41#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:20:21.41#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:20:21.41#ibcon#[27=USB\r\n] 2006.246.07:20:21.41#ibcon#*before write, iclass 25, count 0 2006.246.07:20:21.41#ibcon#enter sib2, iclass 25, count 0 2006.246.07:20:21.41#ibcon#flushed, iclass 25, count 0 2006.246.07:20:21.41#ibcon#about to write, iclass 25, count 0 2006.246.07:20:21.41#ibcon#wrote, iclass 25, count 0 2006.246.07:20:21.41#ibcon#about to read 3, iclass 25, count 0 2006.246.07:20:21.44#ibcon#read 3, iclass 25, count 0 2006.246.07:20:21.44#ibcon#about to read 4, iclass 25, count 0 2006.246.07:20:21.44#ibcon#read 4, iclass 25, count 0 2006.246.07:20:21.44#ibcon#about to read 5, iclass 25, count 0 2006.246.07:20:21.44#ibcon#read 5, iclass 25, count 0 2006.246.07:20:21.44#ibcon#about to read 6, iclass 25, count 0 2006.246.07:20:21.44#ibcon#read 6, iclass 25, count 0 2006.246.07:20:21.44#ibcon#end of sib2, iclass 25, count 0 2006.246.07:20:21.44#ibcon#*after write, iclass 25, count 0 2006.246.07:20:21.44#ibcon#*before return 0, iclass 25, count 0 2006.246.07:20:21.44#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:21.44#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:20:21.44#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:20:21.44#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:20:21.44$vc4f8/vabw=wide 2006.246.07:20:21.44#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:20:21.44#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:20:21.44#ibcon#ireg 8 cls_cnt 0 2006.246.07:20:21.44#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:21.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:21.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:21.44#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:20:21.44#ibcon#first serial, iclass 27, count 0 2006.246.07:20:21.44#ibcon#enter sib2, iclass 27, count 0 2006.246.07:20:21.44#ibcon#flushed, iclass 27, count 0 2006.246.07:20:21.44#ibcon#about to write, iclass 27, count 0 2006.246.07:20:21.44#ibcon#wrote, iclass 27, count 0 2006.246.07:20:21.44#ibcon#about to read 3, iclass 27, count 0 2006.246.07:20:21.46#ibcon#read 3, iclass 27, count 0 2006.246.07:20:21.46#ibcon#about to read 4, iclass 27, count 0 2006.246.07:20:21.46#ibcon#read 4, iclass 27, count 0 2006.246.07:20:21.46#ibcon#about to read 5, iclass 27, count 0 2006.246.07:20:21.46#ibcon#read 5, iclass 27, count 0 2006.246.07:20:21.46#ibcon#about to read 6, iclass 27, count 0 2006.246.07:20:21.46#ibcon#read 6, iclass 27, count 0 2006.246.07:20:21.46#ibcon#end of sib2, iclass 27, count 0 2006.246.07:20:21.46#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:20:21.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:20:21.46#ibcon#[25=BW32\r\n] 2006.246.07:20:21.46#ibcon#*before write, iclass 27, count 0 2006.246.07:20:21.46#ibcon#enter sib2, iclass 27, count 0 2006.246.07:20:21.46#ibcon#flushed, iclass 27, count 0 2006.246.07:20:21.46#ibcon#about to write, iclass 27, count 0 2006.246.07:20:21.46#ibcon#wrote, iclass 27, count 0 2006.246.07:20:21.46#ibcon#about to read 3, iclass 27, count 0 2006.246.07:20:21.49#ibcon#read 3, iclass 27, count 0 2006.246.07:20:21.49#ibcon#about to read 4, iclass 27, count 0 2006.246.07:20:21.49#ibcon#read 4, iclass 27, count 0 2006.246.07:20:21.49#ibcon#about to read 5, iclass 27, count 0 2006.246.07:20:21.49#ibcon#read 5, iclass 27, count 0 2006.246.07:20:21.49#ibcon#about to read 6, iclass 27, count 0 2006.246.07:20:21.49#ibcon#read 6, iclass 27, count 0 2006.246.07:20:21.49#ibcon#end of sib2, iclass 27, count 0 2006.246.07:20:21.49#ibcon#*after write, iclass 27, count 0 2006.246.07:20:21.49#ibcon#*before return 0, iclass 27, count 0 2006.246.07:20:21.49#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:21.49#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:20:21.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:20:21.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:20:21.49$vc4f8/vbbw=wide 2006.246.07:20:21.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:20:21.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:20:21.49#ibcon#ireg 8 cls_cnt 0 2006.246.07:20:21.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:20:21.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:20:21.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:20:21.56#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:20:21.56#ibcon#first serial, iclass 29, count 0 2006.246.07:20:21.56#ibcon#enter sib2, iclass 29, count 0 2006.246.07:20:21.56#ibcon#flushed, iclass 29, count 0 2006.246.07:20:21.56#ibcon#about to write, iclass 29, count 0 2006.246.07:20:21.56#ibcon#wrote, iclass 29, count 0 2006.246.07:20:21.56#ibcon#about to read 3, iclass 29, count 0 2006.246.07:20:21.58#ibcon#read 3, iclass 29, count 0 2006.246.07:20:21.58#ibcon#about to read 4, iclass 29, count 0 2006.246.07:20:21.58#ibcon#read 4, iclass 29, count 0 2006.246.07:20:21.58#ibcon#about to read 5, iclass 29, count 0 2006.246.07:20:21.58#ibcon#read 5, iclass 29, count 0 2006.246.07:20:21.58#ibcon#about to read 6, iclass 29, count 0 2006.246.07:20:21.58#ibcon#read 6, iclass 29, count 0 2006.246.07:20:21.58#ibcon#end of sib2, iclass 29, count 0 2006.246.07:20:21.58#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:20:21.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:20:21.58#ibcon#[27=BW32\r\n] 2006.246.07:20:21.58#ibcon#*before write, iclass 29, count 0 2006.246.07:20:21.58#ibcon#enter sib2, iclass 29, count 0 2006.246.07:20:21.58#ibcon#flushed, iclass 29, count 0 2006.246.07:20:21.58#ibcon#about to write, iclass 29, count 0 2006.246.07:20:21.58#ibcon#wrote, iclass 29, count 0 2006.246.07:20:21.58#ibcon#about to read 3, iclass 29, count 0 2006.246.07:20:21.61#ibcon#read 3, iclass 29, count 0 2006.246.07:20:21.61#ibcon#about to read 4, iclass 29, count 0 2006.246.07:20:21.61#ibcon#read 4, iclass 29, count 0 2006.246.07:20:21.61#ibcon#about to read 5, iclass 29, count 0 2006.246.07:20:21.61#ibcon#read 5, iclass 29, count 0 2006.246.07:20:21.61#ibcon#about to read 6, iclass 29, count 0 2006.246.07:20:21.61#ibcon#read 6, iclass 29, count 0 2006.246.07:20:21.61#ibcon#end of sib2, iclass 29, count 0 2006.246.07:20:21.61#ibcon#*after write, iclass 29, count 0 2006.246.07:20:21.61#ibcon#*before return 0, iclass 29, count 0 2006.246.07:20:21.61#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:20:21.61#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:20:21.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:20:21.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:20:21.61$4f8m12a/ifd4f 2006.246.07:20:21.61&ifd4f/lo= 2006.246.07:20:21.61&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:20:21.61&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:20:21.61&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:20:21.61&ifd4f/patch= 2006.246.07:20:21.61&ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:20:21.61&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:20:21.61&ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:20:21.61$ifd4f/lo= 2006.246.07:20:21.61$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:20:21.61$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:20:21.61$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:20:21.61$ifd4f/patch= 2006.246.07:20:21.61$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:20:21.61$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:20:21.61$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:20:21.61$4f8m12a/"form=m,16.000,1:2 2006.246.07:20:21.61$4f8m12a/"tpicd 2006.246.07:20:21.61$4f8m12a/echo=off 2006.246.07:20:21.61$4f8m12a/xlog=off 2006.246.07:20:21.61:!2006.246.07:29:50 2006.246.07:20:33.13#trakl#Source acquired 2006.246.07:20:35.13#flagr#flagr/antenna,acquired 2006.246.07:29:50.00:preob 2006.246.07:29:50.00&preob/onsource 2006.246.07:29:51.14/onsource/TRACKING 2006.246.07:29:51.14:!2006.246.07:30:00 2006.246.07:30:00.00:data_valid=on 2006.246.07:30:00.00:midob 2006.246.07:30:00.00&midob/onsource 2006.246.07:30:00.00&midob/wx 2006.246.07:30:00.00&midob/cable 2006.246.07:30:00.00&midob/va 2006.246.07:30:00.00&midob/valo 2006.246.07:30:00.00&midob/vb 2006.246.07:30:00.00&midob/vblo 2006.246.07:30:00.00&midob/vabw 2006.246.07:30:00.00&midob/vbbw 2006.246.07:30:00.00&midob/"form 2006.246.07:30:00.00&midob/xfe 2006.246.07:30:00.00&midob/ifatt 2006.246.07:30:00.00&midob/clockoff 2006.246.07:30:00.00&midob/sy=logmail 2006.246.07:30:00.00&midob/"sy=run setcl adapt & 2006.246.07:30:00.14/onsource/TRACKING 2006.246.07:30:00.14/wx/26.83,1005.6,74 2006.246.07:30:00.22/cable/+6.4127E-03 2006.246.07:30:01.31/va/01,08,usb,yes,31,33 2006.246.07:30:01.31/va/02,07,usb,yes,31,33 2006.246.07:30:01.31/va/03,06,usb,yes,33,33 2006.246.07:30:01.31/va/04,07,usb,yes,32,35 2006.246.07:30:01.31/va/05,07,usb,yes,34,36 2006.246.07:30:01.31/va/06,07,usb,yes,30,30 2006.246.07:30:01.31/va/07,07,usb,yes,30,30 2006.246.07:30:01.31/va/08,08,usb,yes,26,26 2006.246.07:30:01.54/valo/01,532.99,yes,locked 2006.246.07:30:01.54/valo/02,572.99,yes,locked 2006.246.07:30:01.54/valo/03,672.99,yes,locked 2006.246.07:30:01.54/valo/04,832.99,yes,locked 2006.246.07:30:01.54/valo/05,652.99,yes,locked 2006.246.07:30:01.54/valo/06,772.99,yes,locked 2006.246.07:30:01.54/valo/07,832.99,yes,locked 2006.246.07:30:01.54/valo/08,852.99,yes,locked 2006.246.07:30:02.63/vb/01,04,usb,yes,31,30 2006.246.07:30:02.63/vb/02,04,usb,yes,33,35 2006.246.07:30:02.63/vb/03,04,usb,yes,29,33 2006.246.07:30:02.63/vb/04,04,usb,yes,30,30 2006.246.07:30:02.63/vb/05,03,usb,yes,36,40 2006.246.07:30:02.63/vb/06,03,usb,yes,36,40 2006.246.07:30:02.63/vb/07,04,usb,yes,32,32 2006.246.07:30:02.63/vb/08,03,usb,yes,36,40 2006.246.07:30:02.87/vblo/01,632.99,yes,locked 2006.246.07:30:02.87/vblo/02,640.99,yes,locked 2006.246.07:30:02.87/vblo/03,656.99,yes,locked 2006.246.07:30:02.87/vblo/04,712.99,yes,locked 2006.246.07:30:02.87/vblo/05,744.99,yes,locked 2006.246.07:30:02.87/vblo/06,752.99,yes,locked 2006.246.07:30:02.87/vblo/07,734.99,yes,locked 2006.246.07:30:02.87/vblo/08,744.99,yes,locked 2006.246.07:30:03.02/vabw/8 2006.246.07:30:03.17/vbbw/8 2006.246.07:30:03.26/xfe/off,on,13.5 2006.246.07:30:03.63/ifatt/23,28,28,28 2006.246.07:30:03.63&clockoff/"gps-fmout=1p 2006.246.07:30:03.63&clockoff/fmout-gps=1p 2006.246.07:30:04.08/fmout-gps/S +4.33E-07 2006.246.07:30:04.16:!2006.246.07:31:00 2006.246.07:31:00.00:data_valid=off 2006.246.07:31:00.00:postob 2006.246.07:31:00.00&postob/cable 2006.246.07:31:00.01&postob/wx 2006.246.07:31:00.01&postob/clockoff 2006.246.07:31:00.11/cable/+6.4117E-03 2006.246.07:31:00.11/wx/26.83,1005.5,72 2006.246.07:31:01.08/fmout-gps/S +4.32E-07 2006.246.07:31:01.08:scan_name=246-0733,k06246,60 2006.246.07:31:01.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.246.07:31:01.14#flagr#flagr/antenna,new-source 2006.246.07:31:02.14:checkk5 2006.246.07:31:02.14&checkk5/chk_autoobs=1 2006.246.07:31:02.14&checkk5/chk_autoobs=2 2006.246.07:31:02.15&checkk5/chk_autoobs=3 2006.246.07:31:02.15&checkk5/chk_autoobs=4 2006.246.07:31:02.15&checkk5/chk_obsdata=1 2006.246.07:31:02.15&checkk5/chk_obsdata=2 2006.246.07:31:02.15&checkk5/chk_obsdata=3 2006.246.07:31:02.15&checkk5/chk_obsdata=4 2006.246.07:31:02.15&checkk5/k5log=1 2006.246.07:31:02.15&checkk5/k5log=2 2006.246.07:31:02.15&checkk5/k5log=3 2006.246.07:31:02.15&checkk5/k5log=4 2006.246.07:31:02.15&checkk5/obsinfo 2006.246.07:31:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:31:02.93/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:31:03.31/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:31:03.69/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:31:04.05/chk_obsdata//k5ts1/T2460730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:31:04.42/chk_obsdata//k5ts2/T2460730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:31:04.79/chk_obsdata//k5ts3/T2460730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:31:05.16/chk_obsdata//k5ts4/T2460730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:31:05.86/k5log//k5ts1_log_newline 2006.246.07:31:06.54/k5log//k5ts2_log_newline 2006.246.07:31:07.23/k5log//k5ts3_log_newline 2006.246.07:31:07.92/k5log//k5ts4_log_newline 2006.246.07:31:07.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:31:07.94:4f8m12a=1 2006.246.07:31:07.94$4f8m12a/echo=on 2006.246.07:31:07.94$4f8m12a/pcalon 2006.246.07:31:07.94$pcalon/"no phase cal control is implemented here 2006.246.07:31:07.94$4f8m12a/"tpicd=stop 2006.246.07:31:07.94$4f8m12a/vc4f8 2006.246.07:31:07.94$vc4f8/valo=1,532.99 2006.246.07:31:07.95#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.07:31:07.95#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.07:31:07.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:07.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:07.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:07.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:07.95#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:31:07.95#ibcon#first serial, iclass 36, count 0 2006.246.07:31:07.95#ibcon#enter sib2, iclass 36, count 0 2006.246.07:31:07.95#ibcon#flushed, iclass 36, count 0 2006.246.07:31:07.95#ibcon#about to write, iclass 36, count 0 2006.246.07:31:07.95#ibcon#wrote, iclass 36, count 0 2006.246.07:31:07.95#ibcon#about to read 3, iclass 36, count 0 2006.246.07:31:07.99#ibcon#read 3, iclass 36, count 0 2006.246.07:31:07.99#ibcon#about to read 4, iclass 36, count 0 2006.246.07:31:07.99#ibcon#read 4, iclass 36, count 0 2006.246.07:31:07.99#ibcon#about to read 5, iclass 36, count 0 2006.246.07:31:07.99#ibcon#read 5, iclass 36, count 0 2006.246.07:31:07.99#ibcon#about to read 6, iclass 36, count 0 2006.246.07:31:07.99#ibcon#read 6, iclass 36, count 0 2006.246.07:31:07.99#ibcon#end of sib2, iclass 36, count 0 2006.246.07:31:07.99#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:31:07.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:31:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:31:07.99#ibcon#*before write, iclass 36, count 0 2006.246.07:31:07.99#ibcon#enter sib2, iclass 36, count 0 2006.246.07:31:07.99#ibcon#flushed, iclass 36, count 0 2006.246.07:31:07.99#ibcon#about to write, iclass 36, count 0 2006.246.07:31:07.99#ibcon#wrote, iclass 36, count 0 2006.246.07:31:07.99#ibcon#about to read 3, iclass 36, count 0 2006.246.07:31:08.04#ibcon#read 3, iclass 36, count 0 2006.246.07:31:08.04#ibcon#about to read 4, iclass 36, count 0 2006.246.07:31:08.04#ibcon#read 4, iclass 36, count 0 2006.246.07:31:08.04#ibcon#about to read 5, iclass 36, count 0 2006.246.07:31:08.04#ibcon#read 5, iclass 36, count 0 2006.246.07:31:08.04#ibcon#about to read 6, iclass 36, count 0 2006.246.07:31:08.04#ibcon#read 6, iclass 36, count 0 2006.246.07:31:08.04#ibcon#end of sib2, iclass 36, count 0 2006.246.07:31:08.04#ibcon#*after write, iclass 36, count 0 2006.246.07:31:08.04#ibcon#*before return 0, iclass 36, count 0 2006.246.07:31:08.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:08.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:08.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:31:08.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:31:08.04$vc4f8/va=1,8 2006.246.07:31:08.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.07:31:08.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.07:31:08.04#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:08.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:08.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:08.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:08.04#ibcon#enter wrdev, iclass 38, count 2 2006.246.07:31:08.04#ibcon#first serial, iclass 38, count 2 2006.246.07:31:08.04#ibcon#enter sib2, iclass 38, count 2 2006.246.07:31:08.04#ibcon#flushed, iclass 38, count 2 2006.246.07:31:08.04#ibcon#about to write, iclass 38, count 2 2006.246.07:31:08.04#ibcon#wrote, iclass 38, count 2 2006.246.07:31:08.04#ibcon#about to read 3, iclass 38, count 2 2006.246.07:31:08.06#ibcon#read 3, iclass 38, count 2 2006.246.07:31:08.06#ibcon#about to read 4, iclass 38, count 2 2006.246.07:31:08.06#ibcon#read 4, iclass 38, count 2 2006.246.07:31:08.06#ibcon#about to read 5, iclass 38, count 2 2006.246.07:31:08.06#ibcon#read 5, iclass 38, count 2 2006.246.07:31:08.06#ibcon#about to read 6, iclass 38, count 2 2006.246.07:31:08.06#ibcon#read 6, iclass 38, count 2 2006.246.07:31:08.06#ibcon#end of sib2, iclass 38, count 2 2006.246.07:31:08.06#ibcon#*mode == 0, iclass 38, count 2 2006.246.07:31:08.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.07:31:08.06#ibcon#[25=AT01-08\r\n] 2006.246.07:31:08.06#ibcon#*before write, iclass 38, count 2 2006.246.07:31:08.06#ibcon#enter sib2, iclass 38, count 2 2006.246.07:31:08.06#ibcon#flushed, iclass 38, count 2 2006.246.07:31:08.06#ibcon#about to write, iclass 38, count 2 2006.246.07:31:08.06#ibcon#wrote, iclass 38, count 2 2006.246.07:31:08.06#ibcon#about to read 3, iclass 38, count 2 2006.246.07:31:08.09#ibcon#read 3, iclass 38, count 2 2006.246.07:31:08.09#ibcon#about to read 4, iclass 38, count 2 2006.246.07:31:08.09#ibcon#read 4, iclass 38, count 2 2006.246.07:31:08.09#ibcon#about to read 5, iclass 38, count 2 2006.246.07:31:08.09#ibcon#read 5, iclass 38, count 2 2006.246.07:31:08.09#ibcon#about to read 6, iclass 38, count 2 2006.246.07:31:08.09#ibcon#read 6, iclass 38, count 2 2006.246.07:31:08.09#ibcon#end of sib2, iclass 38, count 2 2006.246.07:31:08.09#ibcon#*after write, iclass 38, count 2 2006.246.07:31:08.09#ibcon#*before return 0, iclass 38, count 2 2006.246.07:31:08.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:08.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:08.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.07:31:08.09#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:08.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:08.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:08.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:08.21#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:31:08.21#ibcon#first serial, iclass 38, count 0 2006.246.07:31:08.21#ibcon#enter sib2, iclass 38, count 0 2006.246.07:31:08.21#ibcon#flushed, iclass 38, count 0 2006.246.07:31:08.21#ibcon#about to write, iclass 38, count 0 2006.246.07:31:08.21#ibcon#wrote, iclass 38, count 0 2006.246.07:31:08.21#ibcon#about to read 3, iclass 38, count 0 2006.246.07:31:08.23#ibcon#read 3, iclass 38, count 0 2006.246.07:31:08.23#ibcon#about to read 4, iclass 38, count 0 2006.246.07:31:08.23#ibcon#read 4, iclass 38, count 0 2006.246.07:31:08.23#ibcon#about to read 5, iclass 38, count 0 2006.246.07:31:08.23#ibcon#read 5, iclass 38, count 0 2006.246.07:31:08.23#ibcon#about to read 6, iclass 38, count 0 2006.246.07:31:08.23#ibcon#read 6, iclass 38, count 0 2006.246.07:31:08.23#ibcon#end of sib2, iclass 38, count 0 2006.246.07:31:08.23#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:31:08.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:31:08.23#ibcon#[25=USB\r\n] 2006.246.07:31:08.23#ibcon#*before write, iclass 38, count 0 2006.246.07:31:08.23#ibcon#enter sib2, iclass 38, count 0 2006.246.07:31:08.23#ibcon#flushed, iclass 38, count 0 2006.246.07:31:08.23#ibcon#about to write, iclass 38, count 0 2006.246.07:31:08.23#ibcon#wrote, iclass 38, count 0 2006.246.07:31:08.23#ibcon#about to read 3, iclass 38, count 0 2006.246.07:31:08.26#ibcon#read 3, iclass 38, count 0 2006.246.07:31:08.26#ibcon#about to read 4, iclass 38, count 0 2006.246.07:31:08.26#ibcon#read 4, iclass 38, count 0 2006.246.07:31:08.26#ibcon#about to read 5, iclass 38, count 0 2006.246.07:31:08.26#ibcon#read 5, iclass 38, count 0 2006.246.07:31:08.26#ibcon#about to read 6, iclass 38, count 0 2006.246.07:31:08.26#ibcon#read 6, iclass 38, count 0 2006.246.07:31:08.26#ibcon#end of sib2, iclass 38, count 0 2006.246.07:31:08.26#ibcon#*after write, iclass 38, count 0 2006.246.07:31:08.26#ibcon#*before return 0, iclass 38, count 0 2006.246.07:31:08.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:08.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:08.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:31:08.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:31:08.26$vc4f8/valo=2,572.99 2006.246.07:31:08.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:31:08.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:31:08.26#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:08.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:08.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:08.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:08.26#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:31:08.26#ibcon#first serial, iclass 40, count 0 2006.246.07:31:08.26#ibcon#enter sib2, iclass 40, count 0 2006.246.07:31:08.26#ibcon#flushed, iclass 40, count 0 2006.246.07:31:08.26#ibcon#about to write, iclass 40, count 0 2006.246.07:31:08.26#ibcon#wrote, iclass 40, count 0 2006.246.07:31:08.26#ibcon#about to read 3, iclass 40, count 0 2006.246.07:31:08.28#ibcon#read 3, iclass 40, count 0 2006.246.07:31:08.28#ibcon#about to read 4, iclass 40, count 0 2006.246.07:31:08.28#ibcon#read 4, iclass 40, count 0 2006.246.07:31:08.28#ibcon#about to read 5, iclass 40, count 0 2006.246.07:31:08.28#ibcon#read 5, iclass 40, count 0 2006.246.07:31:08.28#ibcon#about to read 6, iclass 40, count 0 2006.246.07:31:08.28#ibcon#read 6, iclass 40, count 0 2006.246.07:31:08.28#ibcon#end of sib2, iclass 40, count 0 2006.246.07:31:08.28#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:31:08.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:31:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:31:08.28#ibcon#*before write, iclass 40, count 0 2006.246.07:31:08.28#ibcon#enter sib2, iclass 40, count 0 2006.246.07:31:08.28#ibcon#flushed, iclass 40, count 0 2006.246.07:31:08.28#ibcon#about to write, iclass 40, count 0 2006.246.07:31:08.28#ibcon#wrote, iclass 40, count 0 2006.246.07:31:08.28#ibcon#about to read 3, iclass 40, count 0 2006.246.07:31:08.33#ibcon#read 3, iclass 40, count 0 2006.246.07:31:08.33#ibcon#about to read 4, iclass 40, count 0 2006.246.07:31:08.33#ibcon#read 4, iclass 40, count 0 2006.246.07:31:08.33#ibcon#about to read 5, iclass 40, count 0 2006.246.07:31:08.33#ibcon#read 5, iclass 40, count 0 2006.246.07:31:08.33#ibcon#about to read 6, iclass 40, count 0 2006.246.07:31:08.33#ibcon#read 6, iclass 40, count 0 2006.246.07:31:08.33#ibcon#end of sib2, iclass 40, count 0 2006.246.07:31:08.33#ibcon#*after write, iclass 40, count 0 2006.246.07:31:08.33#ibcon#*before return 0, iclass 40, count 0 2006.246.07:31:08.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:08.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:08.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:31:08.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:31:08.33$vc4f8/va=2,7 2006.246.07:31:08.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.07:31:08.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.07:31:08.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:08.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:08.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:08.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:08.38#ibcon#enter wrdev, iclass 4, count 2 2006.246.07:31:08.38#ibcon#first serial, iclass 4, count 2 2006.246.07:31:08.38#ibcon#enter sib2, iclass 4, count 2 2006.246.07:31:08.38#ibcon#flushed, iclass 4, count 2 2006.246.07:31:08.38#ibcon#about to write, iclass 4, count 2 2006.246.07:31:08.38#ibcon#wrote, iclass 4, count 2 2006.246.07:31:08.38#ibcon#about to read 3, iclass 4, count 2 2006.246.07:31:08.40#ibcon#read 3, iclass 4, count 2 2006.246.07:31:08.40#ibcon#about to read 4, iclass 4, count 2 2006.246.07:31:08.40#ibcon#read 4, iclass 4, count 2 2006.246.07:31:08.40#ibcon#about to read 5, iclass 4, count 2 2006.246.07:31:08.40#ibcon#read 5, iclass 4, count 2 2006.246.07:31:08.40#ibcon#about to read 6, iclass 4, count 2 2006.246.07:31:08.40#ibcon#read 6, iclass 4, count 2 2006.246.07:31:08.40#ibcon#end of sib2, iclass 4, count 2 2006.246.07:31:08.40#ibcon#*mode == 0, iclass 4, count 2 2006.246.07:31:08.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.07:31:08.40#ibcon#[25=AT02-07\r\n] 2006.246.07:31:08.40#ibcon#*before write, iclass 4, count 2 2006.246.07:31:08.40#ibcon#enter sib2, iclass 4, count 2 2006.246.07:31:08.40#ibcon#flushed, iclass 4, count 2 2006.246.07:31:08.40#ibcon#about to write, iclass 4, count 2 2006.246.07:31:08.40#ibcon#wrote, iclass 4, count 2 2006.246.07:31:08.40#ibcon#about to read 3, iclass 4, count 2 2006.246.07:31:08.43#ibcon#read 3, iclass 4, count 2 2006.246.07:31:08.43#ibcon#about to read 4, iclass 4, count 2 2006.246.07:31:08.43#ibcon#read 4, iclass 4, count 2 2006.246.07:31:08.43#ibcon#about to read 5, iclass 4, count 2 2006.246.07:31:08.43#ibcon#read 5, iclass 4, count 2 2006.246.07:31:08.43#ibcon#about to read 6, iclass 4, count 2 2006.246.07:31:08.43#ibcon#read 6, iclass 4, count 2 2006.246.07:31:08.43#ibcon#end of sib2, iclass 4, count 2 2006.246.07:31:08.43#ibcon#*after write, iclass 4, count 2 2006.246.07:31:08.43#ibcon#*before return 0, iclass 4, count 2 2006.246.07:31:08.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:08.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:08.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.07:31:08.43#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:08.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:08.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:08.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:08.55#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:31:08.55#ibcon#first serial, iclass 4, count 0 2006.246.07:31:08.55#ibcon#enter sib2, iclass 4, count 0 2006.246.07:31:08.55#ibcon#flushed, iclass 4, count 0 2006.246.07:31:08.55#ibcon#about to write, iclass 4, count 0 2006.246.07:31:08.55#ibcon#wrote, iclass 4, count 0 2006.246.07:31:08.55#ibcon#about to read 3, iclass 4, count 0 2006.246.07:31:08.57#ibcon#read 3, iclass 4, count 0 2006.246.07:31:08.57#ibcon#about to read 4, iclass 4, count 0 2006.246.07:31:08.57#ibcon#read 4, iclass 4, count 0 2006.246.07:31:08.57#ibcon#about to read 5, iclass 4, count 0 2006.246.07:31:08.57#ibcon#read 5, iclass 4, count 0 2006.246.07:31:08.57#ibcon#about to read 6, iclass 4, count 0 2006.246.07:31:08.57#ibcon#read 6, iclass 4, count 0 2006.246.07:31:08.57#ibcon#end of sib2, iclass 4, count 0 2006.246.07:31:08.57#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:31:08.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:31:08.57#ibcon#[25=USB\r\n] 2006.246.07:31:08.57#ibcon#*before write, iclass 4, count 0 2006.246.07:31:08.57#ibcon#enter sib2, iclass 4, count 0 2006.246.07:31:08.57#ibcon#flushed, iclass 4, count 0 2006.246.07:31:08.57#ibcon#about to write, iclass 4, count 0 2006.246.07:31:08.57#ibcon#wrote, iclass 4, count 0 2006.246.07:31:08.57#ibcon#about to read 3, iclass 4, count 0 2006.246.07:31:08.60#ibcon#read 3, iclass 4, count 0 2006.246.07:31:08.60#ibcon#about to read 4, iclass 4, count 0 2006.246.07:31:08.60#ibcon#read 4, iclass 4, count 0 2006.246.07:31:08.60#ibcon#about to read 5, iclass 4, count 0 2006.246.07:31:08.60#ibcon#read 5, iclass 4, count 0 2006.246.07:31:08.60#ibcon#about to read 6, iclass 4, count 0 2006.246.07:31:08.60#ibcon#read 6, iclass 4, count 0 2006.246.07:31:08.60#ibcon#end of sib2, iclass 4, count 0 2006.246.07:31:08.60#ibcon#*after write, iclass 4, count 0 2006.246.07:31:08.60#ibcon#*before return 0, iclass 4, count 0 2006.246.07:31:08.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:08.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:08.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:31:08.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:31:08.60$vc4f8/valo=3,672.99 2006.246.07:31:08.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.07:31:08.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.07:31:08.60#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:08.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:08.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:08.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:08.60#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:31:08.60#ibcon#first serial, iclass 6, count 0 2006.246.07:31:08.60#ibcon#enter sib2, iclass 6, count 0 2006.246.07:31:08.60#ibcon#flushed, iclass 6, count 0 2006.246.07:31:08.60#ibcon#about to write, iclass 6, count 0 2006.246.07:31:08.60#ibcon#wrote, iclass 6, count 0 2006.246.07:31:08.60#ibcon#about to read 3, iclass 6, count 0 2006.246.07:31:08.62#ibcon#read 3, iclass 6, count 0 2006.246.07:31:08.62#ibcon#about to read 4, iclass 6, count 0 2006.246.07:31:08.62#ibcon#read 4, iclass 6, count 0 2006.246.07:31:08.62#ibcon#about to read 5, iclass 6, count 0 2006.246.07:31:08.62#ibcon#read 5, iclass 6, count 0 2006.246.07:31:08.62#ibcon#about to read 6, iclass 6, count 0 2006.246.07:31:08.62#ibcon#read 6, iclass 6, count 0 2006.246.07:31:08.62#ibcon#end of sib2, iclass 6, count 0 2006.246.07:31:08.62#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:31:08.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:31:08.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:31:08.62#ibcon#*before write, iclass 6, count 0 2006.246.07:31:08.62#ibcon#enter sib2, iclass 6, count 0 2006.246.07:31:08.62#ibcon#flushed, iclass 6, count 0 2006.246.07:31:08.62#ibcon#about to write, iclass 6, count 0 2006.246.07:31:08.62#ibcon#wrote, iclass 6, count 0 2006.246.07:31:08.62#ibcon#about to read 3, iclass 6, count 0 2006.246.07:31:08.67#ibcon#read 3, iclass 6, count 0 2006.246.07:31:08.67#ibcon#about to read 4, iclass 6, count 0 2006.246.07:31:08.67#ibcon#read 4, iclass 6, count 0 2006.246.07:31:08.67#ibcon#about to read 5, iclass 6, count 0 2006.246.07:31:08.67#ibcon#read 5, iclass 6, count 0 2006.246.07:31:08.67#ibcon#about to read 6, iclass 6, count 0 2006.246.07:31:08.67#ibcon#read 6, iclass 6, count 0 2006.246.07:31:08.67#ibcon#end of sib2, iclass 6, count 0 2006.246.07:31:08.67#ibcon#*after write, iclass 6, count 0 2006.246.07:31:08.67#ibcon#*before return 0, iclass 6, count 0 2006.246.07:31:08.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:08.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:08.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:31:08.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:31:08.67$vc4f8/va=3,6 2006.246.07:31:08.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.07:31:08.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.07:31:08.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:08.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:08.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:08.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:08.72#ibcon#enter wrdev, iclass 10, count 2 2006.246.07:31:08.72#ibcon#first serial, iclass 10, count 2 2006.246.07:31:08.72#ibcon#enter sib2, iclass 10, count 2 2006.246.07:31:08.72#ibcon#flushed, iclass 10, count 2 2006.246.07:31:08.72#ibcon#about to write, iclass 10, count 2 2006.246.07:31:08.72#ibcon#wrote, iclass 10, count 2 2006.246.07:31:08.72#ibcon#about to read 3, iclass 10, count 2 2006.246.07:31:08.74#ibcon#read 3, iclass 10, count 2 2006.246.07:31:08.74#ibcon#about to read 4, iclass 10, count 2 2006.246.07:31:08.74#ibcon#read 4, iclass 10, count 2 2006.246.07:31:08.74#ibcon#about to read 5, iclass 10, count 2 2006.246.07:31:08.74#ibcon#read 5, iclass 10, count 2 2006.246.07:31:08.74#ibcon#about to read 6, iclass 10, count 2 2006.246.07:31:08.74#ibcon#read 6, iclass 10, count 2 2006.246.07:31:08.74#ibcon#end of sib2, iclass 10, count 2 2006.246.07:31:08.74#ibcon#*mode == 0, iclass 10, count 2 2006.246.07:31:08.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.07:31:08.74#ibcon#[25=AT03-06\r\n] 2006.246.07:31:08.74#ibcon#*before write, iclass 10, count 2 2006.246.07:31:08.74#ibcon#enter sib2, iclass 10, count 2 2006.246.07:31:08.74#ibcon#flushed, iclass 10, count 2 2006.246.07:31:08.74#ibcon#about to write, iclass 10, count 2 2006.246.07:31:08.74#ibcon#wrote, iclass 10, count 2 2006.246.07:31:08.74#ibcon#about to read 3, iclass 10, count 2 2006.246.07:31:08.77#ibcon#read 3, iclass 10, count 2 2006.246.07:31:08.77#ibcon#about to read 4, iclass 10, count 2 2006.246.07:31:08.77#ibcon#read 4, iclass 10, count 2 2006.246.07:31:08.77#ibcon#about to read 5, iclass 10, count 2 2006.246.07:31:08.77#ibcon#read 5, iclass 10, count 2 2006.246.07:31:08.77#ibcon#about to read 6, iclass 10, count 2 2006.246.07:31:08.77#ibcon#read 6, iclass 10, count 2 2006.246.07:31:08.77#ibcon#end of sib2, iclass 10, count 2 2006.246.07:31:08.77#ibcon#*after write, iclass 10, count 2 2006.246.07:31:08.77#ibcon#*before return 0, iclass 10, count 2 2006.246.07:31:08.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:08.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:08.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.07:31:08.77#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:08.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:08.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:08.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:08.89#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:31:08.89#ibcon#first serial, iclass 10, count 0 2006.246.07:31:08.89#ibcon#enter sib2, iclass 10, count 0 2006.246.07:31:08.89#ibcon#flushed, iclass 10, count 0 2006.246.07:31:08.89#ibcon#about to write, iclass 10, count 0 2006.246.07:31:08.89#ibcon#wrote, iclass 10, count 0 2006.246.07:31:08.89#ibcon#about to read 3, iclass 10, count 0 2006.246.07:31:08.91#ibcon#read 3, iclass 10, count 0 2006.246.07:31:08.91#ibcon#about to read 4, iclass 10, count 0 2006.246.07:31:08.91#ibcon#read 4, iclass 10, count 0 2006.246.07:31:08.91#ibcon#about to read 5, iclass 10, count 0 2006.246.07:31:08.91#ibcon#read 5, iclass 10, count 0 2006.246.07:31:08.91#ibcon#about to read 6, iclass 10, count 0 2006.246.07:31:08.91#ibcon#read 6, iclass 10, count 0 2006.246.07:31:08.91#ibcon#end of sib2, iclass 10, count 0 2006.246.07:31:08.91#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:31:08.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:31:08.91#ibcon#[25=USB\r\n] 2006.246.07:31:08.91#ibcon#*before write, iclass 10, count 0 2006.246.07:31:08.91#ibcon#enter sib2, iclass 10, count 0 2006.246.07:31:08.91#ibcon#flushed, iclass 10, count 0 2006.246.07:31:08.91#ibcon#about to write, iclass 10, count 0 2006.246.07:31:08.91#ibcon#wrote, iclass 10, count 0 2006.246.07:31:08.91#ibcon#about to read 3, iclass 10, count 0 2006.246.07:31:08.94#ibcon#read 3, iclass 10, count 0 2006.246.07:31:08.94#ibcon#about to read 4, iclass 10, count 0 2006.246.07:31:08.94#ibcon#read 4, iclass 10, count 0 2006.246.07:31:08.94#ibcon#about to read 5, iclass 10, count 0 2006.246.07:31:08.94#ibcon#read 5, iclass 10, count 0 2006.246.07:31:08.94#ibcon#about to read 6, iclass 10, count 0 2006.246.07:31:08.94#ibcon#read 6, iclass 10, count 0 2006.246.07:31:08.94#ibcon#end of sib2, iclass 10, count 0 2006.246.07:31:08.94#ibcon#*after write, iclass 10, count 0 2006.246.07:31:08.94#ibcon#*before return 0, iclass 10, count 0 2006.246.07:31:08.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:08.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:08.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:31:08.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:31:08.94$vc4f8/valo=4,832.99 2006.246.07:31:08.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.07:31:08.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.07:31:08.94#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:08.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:08.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:08.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:08.94#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:31:08.94#ibcon#first serial, iclass 12, count 0 2006.246.07:31:08.94#ibcon#enter sib2, iclass 12, count 0 2006.246.07:31:08.94#ibcon#flushed, iclass 12, count 0 2006.246.07:31:08.94#ibcon#about to write, iclass 12, count 0 2006.246.07:31:08.94#ibcon#wrote, iclass 12, count 0 2006.246.07:31:08.94#ibcon#about to read 3, iclass 12, count 0 2006.246.07:31:08.96#ibcon#read 3, iclass 12, count 0 2006.246.07:31:08.96#ibcon#about to read 4, iclass 12, count 0 2006.246.07:31:08.96#ibcon#read 4, iclass 12, count 0 2006.246.07:31:08.96#ibcon#about to read 5, iclass 12, count 0 2006.246.07:31:08.96#ibcon#read 5, iclass 12, count 0 2006.246.07:31:08.96#ibcon#about to read 6, iclass 12, count 0 2006.246.07:31:08.96#ibcon#read 6, iclass 12, count 0 2006.246.07:31:08.96#ibcon#end of sib2, iclass 12, count 0 2006.246.07:31:08.96#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:31:08.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:31:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:31:08.96#ibcon#*before write, iclass 12, count 0 2006.246.07:31:08.96#ibcon#enter sib2, iclass 12, count 0 2006.246.07:31:08.96#ibcon#flushed, iclass 12, count 0 2006.246.07:31:08.96#ibcon#about to write, iclass 12, count 0 2006.246.07:31:08.96#ibcon#wrote, iclass 12, count 0 2006.246.07:31:08.96#ibcon#about to read 3, iclass 12, count 0 2006.246.07:31:09.00#ibcon#read 3, iclass 12, count 0 2006.246.07:31:09.00#ibcon#about to read 4, iclass 12, count 0 2006.246.07:31:09.00#ibcon#read 4, iclass 12, count 0 2006.246.07:31:09.00#ibcon#about to read 5, iclass 12, count 0 2006.246.07:31:09.00#ibcon#read 5, iclass 12, count 0 2006.246.07:31:09.00#ibcon#about to read 6, iclass 12, count 0 2006.246.07:31:09.00#ibcon#read 6, iclass 12, count 0 2006.246.07:31:09.00#ibcon#end of sib2, iclass 12, count 0 2006.246.07:31:09.00#ibcon#*after write, iclass 12, count 0 2006.246.07:31:09.00#ibcon#*before return 0, iclass 12, count 0 2006.246.07:31:09.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:09.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:09.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:31:09.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:31:09.00$vc4f8/va=4,7 2006.246.07:31:09.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.07:31:09.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.07:31:09.00#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:09.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:09.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:09.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:09.06#ibcon#enter wrdev, iclass 14, count 2 2006.246.07:31:09.06#ibcon#first serial, iclass 14, count 2 2006.246.07:31:09.06#ibcon#enter sib2, iclass 14, count 2 2006.246.07:31:09.06#ibcon#flushed, iclass 14, count 2 2006.246.07:31:09.06#ibcon#about to write, iclass 14, count 2 2006.246.07:31:09.06#ibcon#wrote, iclass 14, count 2 2006.246.07:31:09.06#ibcon#about to read 3, iclass 14, count 2 2006.246.07:31:09.08#ibcon#read 3, iclass 14, count 2 2006.246.07:31:09.08#ibcon#about to read 4, iclass 14, count 2 2006.246.07:31:09.08#ibcon#read 4, iclass 14, count 2 2006.246.07:31:09.08#ibcon#about to read 5, iclass 14, count 2 2006.246.07:31:09.08#ibcon#read 5, iclass 14, count 2 2006.246.07:31:09.08#ibcon#about to read 6, iclass 14, count 2 2006.246.07:31:09.08#ibcon#read 6, iclass 14, count 2 2006.246.07:31:09.08#ibcon#end of sib2, iclass 14, count 2 2006.246.07:31:09.08#ibcon#*mode == 0, iclass 14, count 2 2006.246.07:31:09.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.07:31:09.08#ibcon#[25=AT04-07\r\n] 2006.246.07:31:09.08#ibcon#*before write, iclass 14, count 2 2006.246.07:31:09.08#ibcon#enter sib2, iclass 14, count 2 2006.246.07:31:09.08#ibcon#flushed, iclass 14, count 2 2006.246.07:31:09.08#ibcon#about to write, iclass 14, count 2 2006.246.07:31:09.08#ibcon#wrote, iclass 14, count 2 2006.246.07:31:09.08#ibcon#about to read 3, iclass 14, count 2 2006.246.07:31:09.11#ibcon#read 3, iclass 14, count 2 2006.246.07:31:09.11#ibcon#about to read 4, iclass 14, count 2 2006.246.07:31:09.11#ibcon#read 4, iclass 14, count 2 2006.246.07:31:09.11#ibcon#about to read 5, iclass 14, count 2 2006.246.07:31:09.11#ibcon#read 5, iclass 14, count 2 2006.246.07:31:09.11#ibcon#about to read 6, iclass 14, count 2 2006.246.07:31:09.11#ibcon#read 6, iclass 14, count 2 2006.246.07:31:09.11#ibcon#end of sib2, iclass 14, count 2 2006.246.07:31:09.11#ibcon#*after write, iclass 14, count 2 2006.246.07:31:09.11#ibcon#*before return 0, iclass 14, count 2 2006.246.07:31:09.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:09.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:09.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.07:31:09.11#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:09.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:09.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:09.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:09.23#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:31:09.23#ibcon#first serial, iclass 14, count 0 2006.246.07:31:09.23#ibcon#enter sib2, iclass 14, count 0 2006.246.07:31:09.23#ibcon#flushed, iclass 14, count 0 2006.246.07:31:09.23#ibcon#about to write, iclass 14, count 0 2006.246.07:31:09.23#ibcon#wrote, iclass 14, count 0 2006.246.07:31:09.23#ibcon#about to read 3, iclass 14, count 0 2006.246.07:31:09.25#ibcon#read 3, iclass 14, count 0 2006.246.07:31:09.25#ibcon#about to read 4, iclass 14, count 0 2006.246.07:31:09.25#ibcon#read 4, iclass 14, count 0 2006.246.07:31:09.25#ibcon#about to read 5, iclass 14, count 0 2006.246.07:31:09.25#ibcon#read 5, iclass 14, count 0 2006.246.07:31:09.25#ibcon#about to read 6, iclass 14, count 0 2006.246.07:31:09.25#ibcon#read 6, iclass 14, count 0 2006.246.07:31:09.25#ibcon#end of sib2, iclass 14, count 0 2006.246.07:31:09.25#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:31:09.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:31:09.25#ibcon#[25=USB\r\n] 2006.246.07:31:09.25#ibcon#*before write, iclass 14, count 0 2006.246.07:31:09.25#ibcon#enter sib2, iclass 14, count 0 2006.246.07:31:09.25#ibcon#flushed, iclass 14, count 0 2006.246.07:31:09.25#ibcon#about to write, iclass 14, count 0 2006.246.07:31:09.25#ibcon#wrote, iclass 14, count 0 2006.246.07:31:09.25#ibcon#about to read 3, iclass 14, count 0 2006.246.07:31:09.28#ibcon#read 3, iclass 14, count 0 2006.246.07:31:09.28#ibcon#about to read 4, iclass 14, count 0 2006.246.07:31:09.28#ibcon#read 4, iclass 14, count 0 2006.246.07:31:09.28#ibcon#about to read 5, iclass 14, count 0 2006.246.07:31:09.28#ibcon#read 5, iclass 14, count 0 2006.246.07:31:09.28#ibcon#about to read 6, iclass 14, count 0 2006.246.07:31:09.28#ibcon#read 6, iclass 14, count 0 2006.246.07:31:09.28#ibcon#end of sib2, iclass 14, count 0 2006.246.07:31:09.28#ibcon#*after write, iclass 14, count 0 2006.246.07:31:09.28#ibcon#*before return 0, iclass 14, count 0 2006.246.07:31:09.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:09.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:09.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:31:09.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:31:09.28$vc4f8/valo=5,652.99 2006.246.07:31:09.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.07:31:09.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.07:31:09.28#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:09.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:09.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:09.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:09.28#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:31:09.28#ibcon#first serial, iclass 16, count 0 2006.246.07:31:09.28#ibcon#enter sib2, iclass 16, count 0 2006.246.07:31:09.28#ibcon#flushed, iclass 16, count 0 2006.246.07:31:09.28#ibcon#about to write, iclass 16, count 0 2006.246.07:31:09.28#ibcon#wrote, iclass 16, count 0 2006.246.07:31:09.28#ibcon#about to read 3, iclass 16, count 0 2006.246.07:31:09.30#ibcon#read 3, iclass 16, count 0 2006.246.07:31:09.30#ibcon#about to read 4, iclass 16, count 0 2006.246.07:31:09.30#ibcon#read 4, iclass 16, count 0 2006.246.07:31:09.30#ibcon#about to read 5, iclass 16, count 0 2006.246.07:31:09.30#ibcon#read 5, iclass 16, count 0 2006.246.07:31:09.30#ibcon#about to read 6, iclass 16, count 0 2006.246.07:31:09.30#ibcon#read 6, iclass 16, count 0 2006.246.07:31:09.30#ibcon#end of sib2, iclass 16, count 0 2006.246.07:31:09.30#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:31:09.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:31:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:31:09.30#ibcon#*before write, iclass 16, count 0 2006.246.07:31:09.30#ibcon#enter sib2, iclass 16, count 0 2006.246.07:31:09.30#ibcon#flushed, iclass 16, count 0 2006.246.07:31:09.30#ibcon#about to write, iclass 16, count 0 2006.246.07:31:09.30#ibcon#wrote, iclass 16, count 0 2006.246.07:31:09.30#ibcon#about to read 3, iclass 16, count 0 2006.246.07:31:09.34#ibcon#read 3, iclass 16, count 0 2006.246.07:31:09.34#ibcon#about to read 4, iclass 16, count 0 2006.246.07:31:09.34#ibcon#read 4, iclass 16, count 0 2006.246.07:31:09.34#ibcon#about to read 5, iclass 16, count 0 2006.246.07:31:09.34#ibcon#read 5, iclass 16, count 0 2006.246.07:31:09.34#ibcon#about to read 6, iclass 16, count 0 2006.246.07:31:09.34#ibcon#read 6, iclass 16, count 0 2006.246.07:31:09.34#ibcon#end of sib2, iclass 16, count 0 2006.246.07:31:09.34#ibcon#*after write, iclass 16, count 0 2006.246.07:31:09.34#ibcon#*before return 0, iclass 16, count 0 2006.246.07:31:09.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:09.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:09.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:31:09.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:31:09.34$vc4f8/va=5,7 2006.246.07:31:09.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.07:31:09.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.07:31:09.34#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:09.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:09.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:09.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:09.40#ibcon#enter wrdev, iclass 18, count 2 2006.246.07:31:09.40#ibcon#first serial, iclass 18, count 2 2006.246.07:31:09.40#ibcon#enter sib2, iclass 18, count 2 2006.246.07:31:09.40#ibcon#flushed, iclass 18, count 2 2006.246.07:31:09.40#ibcon#about to write, iclass 18, count 2 2006.246.07:31:09.40#ibcon#wrote, iclass 18, count 2 2006.246.07:31:09.40#ibcon#about to read 3, iclass 18, count 2 2006.246.07:31:09.42#ibcon#read 3, iclass 18, count 2 2006.246.07:31:09.42#ibcon#about to read 4, iclass 18, count 2 2006.246.07:31:09.42#ibcon#read 4, iclass 18, count 2 2006.246.07:31:09.42#ibcon#about to read 5, iclass 18, count 2 2006.246.07:31:09.42#ibcon#read 5, iclass 18, count 2 2006.246.07:31:09.42#ibcon#about to read 6, iclass 18, count 2 2006.246.07:31:09.42#ibcon#read 6, iclass 18, count 2 2006.246.07:31:09.42#ibcon#end of sib2, iclass 18, count 2 2006.246.07:31:09.42#ibcon#*mode == 0, iclass 18, count 2 2006.246.07:31:09.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.07:31:09.42#ibcon#[25=AT05-07\r\n] 2006.246.07:31:09.42#ibcon#*before write, iclass 18, count 2 2006.246.07:31:09.42#ibcon#enter sib2, iclass 18, count 2 2006.246.07:31:09.42#ibcon#flushed, iclass 18, count 2 2006.246.07:31:09.42#ibcon#about to write, iclass 18, count 2 2006.246.07:31:09.42#ibcon#wrote, iclass 18, count 2 2006.246.07:31:09.42#ibcon#about to read 3, iclass 18, count 2 2006.246.07:31:09.45#ibcon#read 3, iclass 18, count 2 2006.246.07:31:09.45#ibcon#about to read 4, iclass 18, count 2 2006.246.07:31:09.45#ibcon#read 4, iclass 18, count 2 2006.246.07:31:09.45#ibcon#about to read 5, iclass 18, count 2 2006.246.07:31:09.45#ibcon#read 5, iclass 18, count 2 2006.246.07:31:09.45#ibcon#about to read 6, iclass 18, count 2 2006.246.07:31:09.45#ibcon#read 6, iclass 18, count 2 2006.246.07:31:09.45#ibcon#end of sib2, iclass 18, count 2 2006.246.07:31:09.45#ibcon#*after write, iclass 18, count 2 2006.246.07:31:09.45#ibcon#*before return 0, iclass 18, count 2 2006.246.07:31:09.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:09.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:09.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.07:31:09.45#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:09.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:09.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:09.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:09.57#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:31:09.57#ibcon#first serial, iclass 18, count 0 2006.246.07:31:09.57#ibcon#enter sib2, iclass 18, count 0 2006.246.07:31:09.57#ibcon#flushed, iclass 18, count 0 2006.246.07:31:09.57#ibcon#about to write, iclass 18, count 0 2006.246.07:31:09.57#ibcon#wrote, iclass 18, count 0 2006.246.07:31:09.57#ibcon#about to read 3, iclass 18, count 0 2006.246.07:31:09.59#ibcon#read 3, iclass 18, count 0 2006.246.07:31:09.59#ibcon#about to read 4, iclass 18, count 0 2006.246.07:31:09.59#ibcon#read 4, iclass 18, count 0 2006.246.07:31:09.59#ibcon#about to read 5, iclass 18, count 0 2006.246.07:31:09.59#ibcon#read 5, iclass 18, count 0 2006.246.07:31:09.59#ibcon#about to read 6, iclass 18, count 0 2006.246.07:31:09.59#ibcon#read 6, iclass 18, count 0 2006.246.07:31:09.59#ibcon#end of sib2, iclass 18, count 0 2006.246.07:31:09.59#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:31:09.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:31:09.59#ibcon#[25=USB\r\n] 2006.246.07:31:09.59#ibcon#*before write, iclass 18, count 0 2006.246.07:31:09.59#ibcon#enter sib2, iclass 18, count 0 2006.246.07:31:09.59#ibcon#flushed, iclass 18, count 0 2006.246.07:31:09.59#ibcon#about to write, iclass 18, count 0 2006.246.07:31:09.59#ibcon#wrote, iclass 18, count 0 2006.246.07:31:09.59#ibcon#about to read 3, iclass 18, count 0 2006.246.07:31:09.62#ibcon#read 3, iclass 18, count 0 2006.246.07:31:09.62#ibcon#about to read 4, iclass 18, count 0 2006.246.07:31:09.62#ibcon#read 4, iclass 18, count 0 2006.246.07:31:09.62#ibcon#about to read 5, iclass 18, count 0 2006.246.07:31:09.62#ibcon#read 5, iclass 18, count 0 2006.246.07:31:09.62#ibcon#about to read 6, iclass 18, count 0 2006.246.07:31:09.62#ibcon#read 6, iclass 18, count 0 2006.246.07:31:09.62#ibcon#end of sib2, iclass 18, count 0 2006.246.07:31:09.62#ibcon#*after write, iclass 18, count 0 2006.246.07:31:09.62#ibcon#*before return 0, iclass 18, count 0 2006.246.07:31:09.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:09.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:09.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:31:09.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:31:09.62$vc4f8/valo=6,772.99 2006.246.07:31:09.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.07:31:09.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.07:31:09.62#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:09.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:09.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:09.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:09.62#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:31:09.62#ibcon#first serial, iclass 20, count 0 2006.246.07:31:09.62#ibcon#enter sib2, iclass 20, count 0 2006.246.07:31:09.62#ibcon#flushed, iclass 20, count 0 2006.246.07:31:09.62#ibcon#about to write, iclass 20, count 0 2006.246.07:31:09.62#ibcon#wrote, iclass 20, count 0 2006.246.07:31:09.62#ibcon#about to read 3, iclass 20, count 0 2006.246.07:31:09.64#ibcon#read 3, iclass 20, count 0 2006.246.07:31:09.64#ibcon#about to read 4, iclass 20, count 0 2006.246.07:31:09.64#ibcon#read 4, iclass 20, count 0 2006.246.07:31:09.64#ibcon#about to read 5, iclass 20, count 0 2006.246.07:31:09.64#ibcon#read 5, iclass 20, count 0 2006.246.07:31:09.64#ibcon#about to read 6, iclass 20, count 0 2006.246.07:31:09.64#ibcon#read 6, iclass 20, count 0 2006.246.07:31:09.64#ibcon#end of sib2, iclass 20, count 0 2006.246.07:31:09.64#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:31:09.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:31:09.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:31:09.64#ibcon#*before write, iclass 20, count 0 2006.246.07:31:09.64#ibcon#enter sib2, iclass 20, count 0 2006.246.07:31:09.64#ibcon#flushed, iclass 20, count 0 2006.246.07:31:09.64#ibcon#about to write, iclass 20, count 0 2006.246.07:31:09.64#ibcon#wrote, iclass 20, count 0 2006.246.07:31:09.64#ibcon#about to read 3, iclass 20, count 0 2006.246.07:31:09.69#ibcon#read 3, iclass 20, count 0 2006.246.07:31:09.69#ibcon#about to read 4, iclass 20, count 0 2006.246.07:31:09.69#ibcon#read 4, iclass 20, count 0 2006.246.07:31:09.69#ibcon#about to read 5, iclass 20, count 0 2006.246.07:31:09.69#ibcon#read 5, iclass 20, count 0 2006.246.07:31:09.69#ibcon#about to read 6, iclass 20, count 0 2006.246.07:31:09.69#ibcon#read 6, iclass 20, count 0 2006.246.07:31:09.69#ibcon#end of sib2, iclass 20, count 0 2006.246.07:31:09.69#ibcon#*after write, iclass 20, count 0 2006.246.07:31:09.69#ibcon#*before return 0, iclass 20, count 0 2006.246.07:31:09.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:09.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:09.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:31:09.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:31:09.69$vc4f8/va=6,7 2006.246.07:31:09.69#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.07:31:09.69#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.07:31:09.69#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:09.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:31:09.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:31:09.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:31:09.74#ibcon#enter wrdev, iclass 22, count 2 2006.246.07:31:09.74#ibcon#first serial, iclass 22, count 2 2006.246.07:31:09.74#ibcon#enter sib2, iclass 22, count 2 2006.246.07:31:09.74#ibcon#flushed, iclass 22, count 2 2006.246.07:31:09.74#ibcon#about to write, iclass 22, count 2 2006.246.07:31:09.74#ibcon#wrote, iclass 22, count 2 2006.246.07:31:09.74#ibcon#about to read 3, iclass 22, count 2 2006.246.07:31:09.76#ibcon#read 3, iclass 22, count 2 2006.246.07:31:09.76#ibcon#about to read 4, iclass 22, count 2 2006.246.07:31:09.76#ibcon#read 4, iclass 22, count 2 2006.246.07:31:09.76#ibcon#about to read 5, iclass 22, count 2 2006.246.07:31:09.76#ibcon#read 5, iclass 22, count 2 2006.246.07:31:09.76#ibcon#about to read 6, iclass 22, count 2 2006.246.07:31:09.76#ibcon#read 6, iclass 22, count 2 2006.246.07:31:09.76#ibcon#end of sib2, iclass 22, count 2 2006.246.07:31:09.76#ibcon#*mode == 0, iclass 22, count 2 2006.246.07:31:09.76#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.07:31:09.76#ibcon#[25=AT06-07\r\n] 2006.246.07:31:09.76#ibcon#*before write, iclass 22, count 2 2006.246.07:31:09.76#ibcon#enter sib2, iclass 22, count 2 2006.246.07:31:09.76#ibcon#flushed, iclass 22, count 2 2006.246.07:31:09.76#ibcon#about to write, iclass 22, count 2 2006.246.07:31:09.76#ibcon#wrote, iclass 22, count 2 2006.246.07:31:09.76#ibcon#about to read 3, iclass 22, count 2 2006.246.07:31:09.79#ibcon#read 3, iclass 22, count 2 2006.246.07:31:09.79#ibcon#about to read 4, iclass 22, count 2 2006.246.07:31:09.79#ibcon#read 4, iclass 22, count 2 2006.246.07:31:09.79#ibcon#about to read 5, iclass 22, count 2 2006.246.07:31:09.79#ibcon#read 5, iclass 22, count 2 2006.246.07:31:09.79#ibcon#about to read 6, iclass 22, count 2 2006.246.07:31:09.79#ibcon#read 6, iclass 22, count 2 2006.246.07:31:09.79#ibcon#end of sib2, iclass 22, count 2 2006.246.07:31:09.79#ibcon#*after write, iclass 22, count 2 2006.246.07:31:09.79#ibcon#*before return 0, iclass 22, count 2 2006.246.07:31:09.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:31:09.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:31:09.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.07:31:09.79#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:09.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:31:09.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:31:09.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:31:09.91#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:31:09.91#ibcon#first serial, iclass 22, count 0 2006.246.07:31:09.91#ibcon#enter sib2, iclass 22, count 0 2006.246.07:31:09.91#ibcon#flushed, iclass 22, count 0 2006.246.07:31:09.91#ibcon#about to write, iclass 22, count 0 2006.246.07:31:09.91#ibcon#wrote, iclass 22, count 0 2006.246.07:31:09.91#ibcon#about to read 3, iclass 22, count 0 2006.246.07:31:09.93#ibcon#read 3, iclass 22, count 0 2006.246.07:31:09.93#ibcon#about to read 4, iclass 22, count 0 2006.246.07:31:09.93#ibcon#read 4, iclass 22, count 0 2006.246.07:31:09.93#ibcon#about to read 5, iclass 22, count 0 2006.246.07:31:09.93#ibcon#read 5, iclass 22, count 0 2006.246.07:31:09.93#ibcon#about to read 6, iclass 22, count 0 2006.246.07:31:09.93#ibcon#read 6, iclass 22, count 0 2006.246.07:31:09.93#ibcon#end of sib2, iclass 22, count 0 2006.246.07:31:09.93#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:31:09.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:31:09.93#ibcon#[25=USB\r\n] 2006.246.07:31:09.93#ibcon#*before write, iclass 22, count 0 2006.246.07:31:09.93#ibcon#enter sib2, iclass 22, count 0 2006.246.07:31:09.93#ibcon#flushed, iclass 22, count 0 2006.246.07:31:09.93#ibcon#about to write, iclass 22, count 0 2006.246.07:31:09.93#ibcon#wrote, iclass 22, count 0 2006.246.07:31:09.93#ibcon#about to read 3, iclass 22, count 0 2006.246.07:31:09.96#ibcon#read 3, iclass 22, count 0 2006.246.07:31:09.96#ibcon#about to read 4, iclass 22, count 0 2006.246.07:31:09.96#ibcon#read 4, iclass 22, count 0 2006.246.07:31:09.96#ibcon#about to read 5, iclass 22, count 0 2006.246.07:31:09.96#ibcon#read 5, iclass 22, count 0 2006.246.07:31:09.96#ibcon#about to read 6, iclass 22, count 0 2006.246.07:31:09.96#ibcon#read 6, iclass 22, count 0 2006.246.07:31:09.96#ibcon#end of sib2, iclass 22, count 0 2006.246.07:31:09.96#ibcon#*after write, iclass 22, count 0 2006.246.07:31:09.96#ibcon#*before return 0, iclass 22, count 0 2006.246.07:31:09.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:31:09.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:31:09.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:31:09.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:31:09.96$vc4f8/valo=7,832.99 2006.246.07:31:09.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.07:31:09.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.07:31:09.96#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:09.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:31:09.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:31:09.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:31:09.96#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:31:09.96#ibcon#first serial, iclass 24, count 0 2006.246.07:31:09.96#ibcon#enter sib2, iclass 24, count 0 2006.246.07:31:09.96#ibcon#flushed, iclass 24, count 0 2006.246.07:31:09.96#ibcon#about to write, iclass 24, count 0 2006.246.07:31:09.96#ibcon#wrote, iclass 24, count 0 2006.246.07:31:09.96#ibcon#about to read 3, iclass 24, count 0 2006.246.07:31:09.98#ibcon#read 3, iclass 24, count 0 2006.246.07:31:09.98#ibcon#about to read 4, iclass 24, count 0 2006.246.07:31:09.98#ibcon#read 4, iclass 24, count 0 2006.246.07:31:09.98#ibcon#about to read 5, iclass 24, count 0 2006.246.07:31:09.98#ibcon#read 5, iclass 24, count 0 2006.246.07:31:09.98#ibcon#about to read 6, iclass 24, count 0 2006.246.07:31:09.98#ibcon#read 6, iclass 24, count 0 2006.246.07:31:09.98#ibcon#end of sib2, iclass 24, count 0 2006.246.07:31:09.98#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:31:09.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:31:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:31:09.98#ibcon#*before write, iclass 24, count 0 2006.246.07:31:09.98#ibcon#enter sib2, iclass 24, count 0 2006.246.07:31:09.98#ibcon#flushed, iclass 24, count 0 2006.246.07:31:09.98#ibcon#about to write, iclass 24, count 0 2006.246.07:31:09.98#ibcon#wrote, iclass 24, count 0 2006.246.07:31:09.98#ibcon#about to read 3, iclass 24, count 0 2006.246.07:31:10.02#ibcon#read 3, iclass 24, count 0 2006.246.07:31:10.02#ibcon#about to read 4, iclass 24, count 0 2006.246.07:31:10.02#ibcon#read 4, iclass 24, count 0 2006.246.07:31:10.02#ibcon#about to read 5, iclass 24, count 0 2006.246.07:31:10.02#ibcon#read 5, iclass 24, count 0 2006.246.07:31:10.02#ibcon#about to read 6, iclass 24, count 0 2006.246.07:31:10.02#ibcon#read 6, iclass 24, count 0 2006.246.07:31:10.02#ibcon#end of sib2, iclass 24, count 0 2006.246.07:31:10.02#ibcon#*after write, iclass 24, count 0 2006.246.07:31:10.02#ibcon#*before return 0, iclass 24, count 0 2006.246.07:31:10.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:31:10.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:31:10.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:31:10.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:31:10.02$vc4f8/va=7,7 2006.246.07:31:10.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.07:31:10.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.07:31:10.02#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:10.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:31:10.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:31:10.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:31:10.08#ibcon#enter wrdev, iclass 26, count 2 2006.246.07:31:10.08#ibcon#first serial, iclass 26, count 2 2006.246.07:31:10.08#ibcon#enter sib2, iclass 26, count 2 2006.246.07:31:10.08#ibcon#flushed, iclass 26, count 2 2006.246.07:31:10.08#ibcon#about to write, iclass 26, count 2 2006.246.07:31:10.08#ibcon#wrote, iclass 26, count 2 2006.246.07:31:10.08#ibcon#about to read 3, iclass 26, count 2 2006.246.07:31:10.10#ibcon#read 3, iclass 26, count 2 2006.246.07:31:10.10#ibcon#about to read 4, iclass 26, count 2 2006.246.07:31:10.10#ibcon#read 4, iclass 26, count 2 2006.246.07:31:10.10#ibcon#about to read 5, iclass 26, count 2 2006.246.07:31:10.10#ibcon#read 5, iclass 26, count 2 2006.246.07:31:10.10#ibcon#about to read 6, iclass 26, count 2 2006.246.07:31:10.10#ibcon#read 6, iclass 26, count 2 2006.246.07:31:10.10#ibcon#end of sib2, iclass 26, count 2 2006.246.07:31:10.10#ibcon#*mode == 0, iclass 26, count 2 2006.246.07:31:10.10#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.07:31:10.10#ibcon#[25=AT07-07\r\n] 2006.246.07:31:10.10#ibcon#*before write, iclass 26, count 2 2006.246.07:31:10.10#ibcon#enter sib2, iclass 26, count 2 2006.246.07:31:10.10#ibcon#flushed, iclass 26, count 2 2006.246.07:31:10.10#ibcon#about to write, iclass 26, count 2 2006.246.07:31:10.10#ibcon#wrote, iclass 26, count 2 2006.246.07:31:10.10#ibcon#about to read 3, iclass 26, count 2 2006.246.07:31:10.13#ibcon#read 3, iclass 26, count 2 2006.246.07:31:10.13#ibcon#about to read 4, iclass 26, count 2 2006.246.07:31:10.13#ibcon#read 4, iclass 26, count 2 2006.246.07:31:10.13#ibcon#about to read 5, iclass 26, count 2 2006.246.07:31:10.13#ibcon#read 5, iclass 26, count 2 2006.246.07:31:10.13#ibcon#about to read 6, iclass 26, count 2 2006.246.07:31:10.13#ibcon#read 6, iclass 26, count 2 2006.246.07:31:10.13#ibcon#end of sib2, iclass 26, count 2 2006.246.07:31:10.13#ibcon#*after write, iclass 26, count 2 2006.246.07:31:10.13#ibcon#*before return 0, iclass 26, count 2 2006.246.07:31:10.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:31:10.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:31:10.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.07:31:10.13#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:10.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:31:10.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:31:10.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:31:10.25#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:31:10.25#ibcon#first serial, iclass 26, count 0 2006.246.07:31:10.25#ibcon#enter sib2, iclass 26, count 0 2006.246.07:31:10.25#ibcon#flushed, iclass 26, count 0 2006.246.07:31:10.25#ibcon#about to write, iclass 26, count 0 2006.246.07:31:10.25#ibcon#wrote, iclass 26, count 0 2006.246.07:31:10.25#ibcon#about to read 3, iclass 26, count 0 2006.246.07:31:10.27#ibcon#read 3, iclass 26, count 0 2006.246.07:31:10.27#ibcon#about to read 4, iclass 26, count 0 2006.246.07:31:10.27#ibcon#read 4, iclass 26, count 0 2006.246.07:31:10.27#ibcon#about to read 5, iclass 26, count 0 2006.246.07:31:10.27#ibcon#read 5, iclass 26, count 0 2006.246.07:31:10.27#ibcon#about to read 6, iclass 26, count 0 2006.246.07:31:10.27#ibcon#read 6, iclass 26, count 0 2006.246.07:31:10.27#ibcon#end of sib2, iclass 26, count 0 2006.246.07:31:10.27#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:31:10.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:31:10.27#ibcon#[25=USB\r\n] 2006.246.07:31:10.27#ibcon#*before write, iclass 26, count 0 2006.246.07:31:10.27#ibcon#enter sib2, iclass 26, count 0 2006.246.07:31:10.27#ibcon#flushed, iclass 26, count 0 2006.246.07:31:10.27#ibcon#about to write, iclass 26, count 0 2006.246.07:31:10.27#ibcon#wrote, iclass 26, count 0 2006.246.07:31:10.27#ibcon#about to read 3, iclass 26, count 0 2006.246.07:31:10.30#ibcon#read 3, iclass 26, count 0 2006.246.07:31:10.30#ibcon#about to read 4, iclass 26, count 0 2006.246.07:31:10.30#ibcon#read 4, iclass 26, count 0 2006.246.07:31:10.30#ibcon#about to read 5, iclass 26, count 0 2006.246.07:31:10.30#ibcon#read 5, iclass 26, count 0 2006.246.07:31:10.30#ibcon#about to read 6, iclass 26, count 0 2006.246.07:31:10.30#ibcon#read 6, iclass 26, count 0 2006.246.07:31:10.30#ibcon#end of sib2, iclass 26, count 0 2006.246.07:31:10.30#ibcon#*after write, iclass 26, count 0 2006.246.07:31:10.30#ibcon#*before return 0, iclass 26, count 0 2006.246.07:31:10.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:31:10.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:31:10.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:31:10.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:31:10.30$vc4f8/valo=8,852.99 2006.246.07:31:10.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.07:31:10.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.07:31:10.30#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:10.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:31:10.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:31:10.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:31:10.30#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:31:10.30#ibcon#first serial, iclass 28, count 0 2006.246.07:31:10.30#ibcon#enter sib2, iclass 28, count 0 2006.246.07:31:10.30#ibcon#flushed, iclass 28, count 0 2006.246.07:31:10.30#ibcon#about to write, iclass 28, count 0 2006.246.07:31:10.30#ibcon#wrote, iclass 28, count 0 2006.246.07:31:10.30#ibcon#about to read 3, iclass 28, count 0 2006.246.07:31:10.32#ibcon#read 3, iclass 28, count 0 2006.246.07:31:10.32#ibcon#about to read 4, iclass 28, count 0 2006.246.07:31:10.32#ibcon#read 4, iclass 28, count 0 2006.246.07:31:10.32#ibcon#about to read 5, iclass 28, count 0 2006.246.07:31:10.32#ibcon#read 5, iclass 28, count 0 2006.246.07:31:10.32#ibcon#about to read 6, iclass 28, count 0 2006.246.07:31:10.32#ibcon#read 6, iclass 28, count 0 2006.246.07:31:10.32#ibcon#end of sib2, iclass 28, count 0 2006.246.07:31:10.32#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:31:10.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:31:10.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:31:10.32#ibcon#*before write, iclass 28, count 0 2006.246.07:31:10.32#ibcon#enter sib2, iclass 28, count 0 2006.246.07:31:10.32#ibcon#flushed, iclass 28, count 0 2006.246.07:31:10.32#ibcon#about to write, iclass 28, count 0 2006.246.07:31:10.32#ibcon#wrote, iclass 28, count 0 2006.246.07:31:10.32#ibcon#about to read 3, iclass 28, count 0 2006.246.07:31:10.37#ibcon#read 3, iclass 28, count 0 2006.246.07:31:10.37#ibcon#about to read 4, iclass 28, count 0 2006.246.07:31:10.37#ibcon#read 4, iclass 28, count 0 2006.246.07:31:10.37#ibcon#about to read 5, iclass 28, count 0 2006.246.07:31:10.37#ibcon#read 5, iclass 28, count 0 2006.246.07:31:10.37#ibcon#about to read 6, iclass 28, count 0 2006.246.07:31:10.37#ibcon#read 6, iclass 28, count 0 2006.246.07:31:10.37#ibcon#end of sib2, iclass 28, count 0 2006.246.07:31:10.37#ibcon#*after write, iclass 28, count 0 2006.246.07:31:10.37#ibcon#*before return 0, iclass 28, count 0 2006.246.07:31:10.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:31:10.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:31:10.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:31:10.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:31:10.37$vc4f8/va=8,8 2006.246.07:31:10.37#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.07:31:10.37#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.07:31:10.37#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:10.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:31:10.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:31:10.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:31:10.42#ibcon#enter wrdev, iclass 30, count 2 2006.246.07:31:10.42#ibcon#first serial, iclass 30, count 2 2006.246.07:31:10.42#ibcon#enter sib2, iclass 30, count 2 2006.246.07:31:10.42#ibcon#flushed, iclass 30, count 2 2006.246.07:31:10.42#ibcon#about to write, iclass 30, count 2 2006.246.07:31:10.42#ibcon#wrote, iclass 30, count 2 2006.246.07:31:10.42#ibcon#about to read 3, iclass 30, count 2 2006.246.07:31:10.44#ibcon#read 3, iclass 30, count 2 2006.246.07:31:10.44#ibcon#about to read 4, iclass 30, count 2 2006.246.07:31:10.44#ibcon#read 4, iclass 30, count 2 2006.246.07:31:10.44#ibcon#about to read 5, iclass 30, count 2 2006.246.07:31:10.44#ibcon#read 5, iclass 30, count 2 2006.246.07:31:10.44#ibcon#about to read 6, iclass 30, count 2 2006.246.07:31:10.44#ibcon#read 6, iclass 30, count 2 2006.246.07:31:10.44#ibcon#end of sib2, iclass 30, count 2 2006.246.07:31:10.44#ibcon#*mode == 0, iclass 30, count 2 2006.246.07:31:10.44#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.07:31:10.44#ibcon#[25=AT08-08\r\n] 2006.246.07:31:10.44#ibcon#*before write, iclass 30, count 2 2006.246.07:31:10.44#ibcon#enter sib2, iclass 30, count 2 2006.246.07:31:10.44#ibcon#flushed, iclass 30, count 2 2006.246.07:31:10.44#ibcon#about to write, iclass 30, count 2 2006.246.07:31:10.44#ibcon#wrote, iclass 30, count 2 2006.246.07:31:10.44#ibcon#about to read 3, iclass 30, count 2 2006.246.07:31:10.47#ibcon#read 3, iclass 30, count 2 2006.246.07:31:10.47#ibcon#about to read 4, iclass 30, count 2 2006.246.07:31:10.47#ibcon#read 4, iclass 30, count 2 2006.246.07:31:10.47#ibcon#about to read 5, iclass 30, count 2 2006.246.07:31:10.47#ibcon#read 5, iclass 30, count 2 2006.246.07:31:10.47#ibcon#about to read 6, iclass 30, count 2 2006.246.07:31:10.47#ibcon#read 6, iclass 30, count 2 2006.246.07:31:10.47#ibcon#end of sib2, iclass 30, count 2 2006.246.07:31:10.47#ibcon#*after write, iclass 30, count 2 2006.246.07:31:10.47#ibcon#*before return 0, iclass 30, count 2 2006.246.07:31:10.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:31:10.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:31:10.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.07:31:10.47#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:10.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:31:10.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:31:10.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:31:10.59#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:31:10.59#ibcon#first serial, iclass 30, count 0 2006.246.07:31:10.59#ibcon#enter sib2, iclass 30, count 0 2006.246.07:31:10.59#ibcon#flushed, iclass 30, count 0 2006.246.07:31:10.59#ibcon#about to write, iclass 30, count 0 2006.246.07:31:10.59#ibcon#wrote, iclass 30, count 0 2006.246.07:31:10.59#ibcon#about to read 3, iclass 30, count 0 2006.246.07:31:10.61#ibcon#read 3, iclass 30, count 0 2006.246.07:31:10.61#ibcon#about to read 4, iclass 30, count 0 2006.246.07:31:10.61#ibcon#read 4, iclass 30, count 0 2006.246.07:31:10.61#ibcon#about to read 5, iclass 30, count 0 2006.246.07:31:10.61#ibcon#read 5, iclass 30, count 0 2006.246.07:31:10.61#ibcon#about to read 6, iclass 30, count 0 2006.246.07:31:10.61#ibcon#read 6, iclass 30, count 0 2006.246.07:31:10.61#ibcon#end of sib2, iclass 30, count 0 2006.246.07:31:10.61#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:31:10.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:31:10.61#ibcon#[25=USB\r\n] 2006.246.07:31:10.61#ibcon#*before write, iclass 30, count 0 2006.246.07:31:10.61#ibcon#enter sib2, iclass 30, count 0 2006.246.07:31:10.61#ibcon#flushed, iclass 30, count 0 2006.246.07:31:10.61#ibcon#about to write, iclass 30, count 0 2006.246.07:31:10.61#ibcon#wrote, iclass 30, count 0 2006.246.07:31:10.61#ibcon#about to read 3, iclass 30, count 0 2006.246.07:31:10.64#ibcon#read 3, iclass 30, count 0 2006.246.07:31:10.64#ibcon#about to read 4, iclass 30, count 0 2006.246.07:31:10.64#ibcon#read 4, iclass 30, count 0 2006.246.07:31:10.64#ibcon#about to read 5, iclass 30, count 0 2006.246.07:31:10.64#ibcon#read 5, iclass 30, count 0 2006.246.07:31:10.64#ibcon#about to read 6, iclass 30, count 0 2006.246.07:31:10.64#ibcon#read 6, iclass 30, count 0 2006.246.07:31:10.64#ibcon#end of sib2, iclass 30, count 0 2006.246.07:31:10.64#ibcon#*after write, iclass 30, count 0 2006.246.07:31:10.64#ibcon#*before return 0, iclass 30, count 0 2006.246.07:31:10.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:31:10.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:31:10.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:31:10.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:31:10.64$vc4f8/vblo=1,632.99 2006.246.07:31:10.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.07:31:10.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.07:31:10.64#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:10.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:31:10.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:31:10.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:31:10.64#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:31:10.64#ibcon#first serial, iclass 32, count 0 2006.246.07:31:10.64#ibcon#enter sib2, iclass 32, count 0 2006.246.07:31:10.64#ibcon#flushed, iclass 32, count 0 2006.246.07:31:10.64#ibcon#about to write, iclass 32, count 0 2006.246.07:31:10.64#ibcon#wrote, iclass 32, count 0 2006.246.07:31:10.64#ibcon#about to read 3, iclass 32, count 0 2006.246.07:31:10.66#ibcon#read 3, iclass 32, count 0 2006.246.07:31:10.66#ibcon#about to read 4, iclass 32, count 0 2006.246.07:31:10.66#ibcon#read 4, iclass 32, count 0 2006.246.07:31:10.66#ibcon#about to read 5, iclass 32, count 0 2006.246.07:31:10.66#ibcon#read 5, iclass 32, count 0 2006.246.07:31:10.66#ibcon#about to read 6, iclass 32, count 0 2006.246.07:31:10.66#ibcon#read 6, iclass 32, count 0 2006.246.07:31:10.66#ibcon#end of sib2, iclass 32, count 0 2006.246.07:31:10.66#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:31:10.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:31:10.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:31:10.66#ibcon#*before write, iclass 32, count 0 2006.246.07:31:10.66#ibcon#enter sib2, iclass 32, count 0 2006.246.07:31:10.66#ibcon#flushed, iclass 32, count 0 2006.246.07:31:10.66#ibcon#about to write, iclass 32, count 0 2006.246.07:31:10.66#ibcon#wrote, iclass 32, count 0 2006.246.07:31:10.66#ibcon#about to read 3, iclass 32, count 0 2006.246.07:31:10.70#ibcon#read 3, iclass 32, count 0 2006.246.07:31:10.70#ibcon#about to read 4, iclass 32, count 0 2006.246.07:31:10.70#ibcon#read 4, iclass 32, count 0 2006.246.07:31:10.70#ibcon#about to read 5, iclass 32, count 0 2006.246.07:31:10.70#ibcon#read 5, iclass 32, count 0 2006.246.07:31:10.70#ibcon#about to read 6, iclass 32, count 0 2006.246.07:31:10.70#ibcon#read 6, iclass 32, count 0 2006.246.07:31:10.70#ibcon#end of sib2, iclass 32, count 0 2006.246.07:31:10.70#ibcon#*after write, iclass 32, count 0 2006.246.07:31:10.70#ibcon#*before return 0, iclass 32, count 0 2006.246.07:31:10.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:31:10.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:31:10.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:31:10.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:31:10.70$vc4f8/vb=1,4 2006.246.07:31:10.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.07:31:10.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.07:31:10.70#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:10.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:31:10.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:31:10.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:31:10.70#ibcon#enter wrdev, iclass 34, count 2 2006.246.07:31:10.70#ibcon#first serial, iclass 34, count 2 2006.246.07:31:10.70#ibcon#enter sib2, iclass 34, count 2 2006.246.07:31:10.70#ibcon#flushed, iclass 34, count 2 2006.246.07:31:10.70#ibcon#about to write, iclass 34, count 2 2006.246.07:31:10.70#ibcon#wrote, iclass 34, count 2 2006.246.07:31:10.70#ibcon#about to read 3, iclass 34, count 2 2006.246.07:31:10.72#ibcon#read 3, iclass 34, count 2 2006.246.07:31:10.72#ibcon#about to read 4, iclass 34, count 2 2006.246.07:31:10.72#ibcon#read 4, iclass 34, count 2 2006.246.07:31:10.72#ibcon#about to read 5, iclass 34, count 2 2006.246.07:31:10.72#ibcon#read 5, iclass 34, count 2 2006.246.07:31:10.72#ibcon#about to read 6, iclass 34, count 2 2006.246.07:31:10.72#ibcon#read 6, iclass 34, count 2 2006.246.07:31:10.72#ibcon#end of sib2, iclass 34, count 2 2006.246.07:31:10.72#ibcon#*mode == 0, iclass 34, count 2 2006.246.07:31:10.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.07:31:10.72#ibcon#[27=AT01-04\r\n] 2006.246.07:31:10.72#ibcon#*before write, iclass 34, count 2 2006.246.07:31:10.72#ibcon#enter sib2, iclass 34, count 2 2006.246.07:31:10.72#ibcon#flushed, iclass 34, count 2 2006.246.07:31:10.72#ibcon#about to write, iclass 34, count 2 2006.246.07:31:10.72#ibcon#wrote, iclass 34, count 2 2006.246.07:31:10.72#ibcon#about to read 3, iclass 34, count 2 2006.246.07:31:10.75#ibcon#read 3, iclass 34, count 2 2006.246.07:31:10.75#ibcon#about to read 4, iclass 34, count 2 2006.246.07:31:10.75#ibcon#read 4, iclass 34, count 2 2006.246.07:31:10.75#ibcon#about to read 5, iclass 34, count 2 2006.246.07:31:10.75#ibcon#read 5, iclass 34, count 2 2006.246.07:31:10.75#ibcon#about to read 6, iclass 34, count 2 2006.246.07:31:10.75#ibcon#read 6, iclass 34, count 2 2006.246.07:31:10.75#ibcon#end of sib2, iclass 34, count 2 2006.246.07:31:10.75#ibcon#*after write, iclass 34, count 2 2006.246.07:31:10.75#ibcon#*before return 0, iclass 34, count 2 2006.246.07:31:10.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:31:10.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:31:10.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.07:31:10.75#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:10.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:31:10.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:31:10.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:31:10.87#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:31:10.87#ibcon#first serial, iclass 34, count 0 2006.246.07:31:10.87#ibcon#enter sib2, iclass 34, count 0 2006.246.07:31:10.87#ibcon#flushed, iclass 34, count 0 2006.246.07:31:10.87#ibcon#about to write, iclass 34, count 0 2006.246.07:31:10.87#ibcon#wrote, iclass 34, count 0 2006.246.07:31:10.87#ibcon#about to read 3, iclass 34, count 0 2006.246.07:31:10.89#ibcon#read 3, iclass 34, count 0 2006.246.07:31:10.89#ibcon#about to read 4, iclass 34, count 0 2006.246.07:31:10.89#ibcon#read 4, iclass 34, count 0 2006.246.07:31:10.89#ibcon#about to read 5, iclass 34, count 0 2006.246.07:31:10.89#ibcon#read 5, iclass 34, count 0 2006.246.07:31:10.89#ibcon#about to read 6, iclass 34, count 0 2006.246.07:31:10.89#ibcon#read 6, iclass 34, count 0 2006.246.07:31:10.89#ibcon#end of sib2, iclass 34, count 0 2006.246.07:31:10.89#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:31:10.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:31:10.89#ibcon#[27=USB\r\n] 2006.246.07:31:10.89#ibcon#*before write, iclass 34, count 0 2006.246.07:31:10.89#ibcon#enter sib2, iclass 34, count 0 2006.246.07:31:10.89#ibcon#flushed, iclass 34, count 0 2006.246.07:31:10.89#ibcon#about to write, iclass 34, count 0 2006.246.07:31:10.89#ibcon#wrote, iclass 34, count 0 2006.246.07:31:10.89#ibcon#about to read 3, iclass 34, count 0 2006.246.07:31:10.92#ibcon#read 3, iclass 34, count 0 2006.246.07:31:10.92#ibcon#about to read 4, iclass 34, count 0 2006.246.07:31:10.92#ibcon#read 4, iclass 34, count 0 2006.246.07:31:10.92#ibcon#about to read 5, iclass 34, count 0 2006.246.07:31:10.92#ibcon#read 5, iclass 34, count 0 2006.246.07:31:10.92#ibcon#about to read 6, iclass 34, count 0 2006.246.07:31:10.92#ibcon#read 6, iclass 34, count 0 2006.246.07:31:10.92#ibcon#end of sib2, iclass 34, count 0 2006.246.07:31:10.92#ibcon#*after write, iclass 34, count 0 2006.246.07:31:10.92#ibcon#*before return 0, iclass 34, count 0 2006.246.07:31:10.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:31:10.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:31:10.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:31:10.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:31:10.92$vc4f8/vblo=2,640.99 2006.246.07:31:10.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.07:31:10.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.07:31:10.92#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:10.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:10.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:10.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:10.92#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:31:10.92#ibcon#first serial, iclass 36, count 0 2006.246.07:31:10.92#ibcon#enter sib2, iclass 36, count 0 2006.246.07:31:10.92#ibcon#flushed, iclass 36, count 0 2006.246.07:31:10.92#ibcon#about to write, iclass 36, count 0 2006.246.07:31:10.92#ibcon#wrote, iclass 36, count 0 2006.246.07:31:10.92#ibcon#about to read 3, iclass 36, count 0 2006.246.07:31:10.94#ibcon#read 3, iclass 36, count 0 2006.246.07:31:10.94#ibcon#about to read 4, iclass 36, count 0 2006.246.07:31:10.94#ibcon#read 4, iclass 36, count 0 2006.246.07:31:10.94#ibcon#about to read 5, iclass 36, count 0 2006.246.07:31:10.94#ibcon#read 5, iclass 36, count 0 2006.246.07:31:10.94#ibcon#about to read 6, iclass 36, count 0 2006.246.07:31:10.94#ibcon#read 6, iclass 36, count 0 2006.246.07:31:10.94#ibcon#end of sib2, iclass 36, count 0 2006.246.07:31:10.94#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:31:10.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:31:10.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:31:10.94#ibcon#*before write, iclass 36, count 0 2006.246.07:31:10.94#ibcon#enter sib2, iclass 36, count 0 2006.246.07:31:10.94#ibcon#flushed, iclass 36, count 0 2006.246.07:31:10.94#ibcon#about to write, iclass 36, count 0 2006.246.07:31:10.94#ibcon#wrote, iclass 36, count 0 2006.246.07:31:10.94#ibcon#about to read 3, iclass 36, count 0 2006.246.07:31:10.98#ibcon#read 3, iclass 36, count 0 2006.246.07:31:10.98#ibcon#about to read 4, iclass 36, count 0 2006.246.07:31:10.98#ibcon#read 4, iclass 36, count 0 2006.246.07:31:10.98#ibcon#about to read 5, iclass 36, count 0 2006.246.07:31:10.98#ibcon#read 5, iclass 36, count 0 2006.246.07:31:10.98#ibcon#about to read 6, iclass 36, count 0 2006.246.07:31:10.98#ibcon#read 6, iclass 36, count 0 2006.246.07:31:10.98#ibcon#end of sib2, iclass 36, count 0 2006.246.07:31:10.98#ibcon#*after write, iclass 36, count 0 2006.246.07:31:10.98#ibcon#*before return 0, iclass 36, count 0 2006.246.07:31:10.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:10.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:31:10.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:31:10.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:31:10.98$vc4f8/vb=2,4 2006.246.07:31:10.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.07:31:10.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.07:31:10.98#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:10.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:11.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:11.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:11.04#ibcon#enter wrdev, iclass 38, count 2 2006.246.07:31:11.04#ibcon#first serial, iclass 38, count 2 2006.246.07:31:11.04#ibcon#enter sib2, iclass 38, count 2 2006.246.07:31:11.04#ibcon#flushed, iclass 38, count 2 2006.246.07:31:11.04#ibcon#about to write, iclass 38, count 2 2006.246.07:31:11.04#ibcon#wrote, iclass 38, count 2 2006.246.07:31:11.04#ibcon#about to read 3, iclass 38, count 2 2006.246.07:31:11.06#ibcon#read 3, iclass 38, count 2 2006.246.07:31:11.06#ibcon#about to read 4, iclass 38, count 2 2006.246.07:31:11.06#ibcon#read 4, iclass 38, count 2 2006.246.07:31:11.06#ibcon#about to read 5, iclass 38, count 2 2006.246.07:31:11.06#ibcon#read 5, iclass 38, count 2 2006.246.07:31:11.06#ibcon#about to read 6, iclass 38, count 2 2006.246.07:31:11.06#ibcon#read 6, iclass 38, count 2 2006.246.07:31:11.06#ibcon#end of sib2, iclass 38, count 2 2006.246.07:31:11.06#ibcon#*mode == 0, iclass 38, count 2 2006.246.07:31:11.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.07:31:11.06#ibcon#[27=AT02-04\r\n] 2006.246.07:31:11.06#ibcon#*before write, iclass 38, count 2 2006.246.07:31:11.06#ibcon#enter sib2, iclass 38, count 2 2006.246.07:31:11.06#ibcon#flushed, iclass 38, count 2 2006.246.07:31:11.06#ibcon#about to write, iclass 38, count 2 2006.246.07:31:11.06#ibcon#wrote, iclass 38, count 2 2006.246.07:31:11.06#ibcon#about to read 3, iclass 38, count 2 2006.246.07:31:11.09#ibcon#read 3, iclass 38, count 2 2006.246.07:31:11.09#ibcon#about to read 4, iclass 38, count 2 2006.246.07:31:11.09#ibcon#read 4, iclass 38, count 2 2006.246.07:31:11.09#ibcon#about to read 5, iclass 38, count 2 2006.246.07:31:11.09#ibcon#read 5, iclass 38, count 2 2006.246.07:31:11.09#ibcon#about to read 6, iclass 38, count 2 2006.246.07:31:11.09#ibcon#read 6, iclass 38, count 2 2006.246.07:31:11.09#ibcon#end of sib2, iclass 38, count 2 2006.246.07:31:11.09#ibcon#*after write, iclass 38, count 2 2006.246.07:31:11.09#ibcon#*before return 0, iclass 38, count 2 2006.246.07:31:11.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:11.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:31:11.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.07:31:11.09#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:11.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:11.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:11.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:11.21#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:31:11.21#ibcon#first serial, iclass 38, count 0 2006.246.07:31:11.21#ibcon#enter sib2, iclass 38, count 0 2006.246.07:31:11.21#ibcon#flushed, iclass 38, count 0 2006.246.07:31:11.21#ibcon#about to write, iclass 38, count 0 2006.246.07:31:11.21#ibcon#wrote, iclass 38, count 0 2006.246.07:31:11.21#ibcon#about to read 3, iclass 38, count 0 2006.246.07:31:11.24#ibcon#read 3, iclass 38, count 0 2006.246.07:31:11.24#ibcon#about to read 4, iclass 38, count 0 2006.246.07:31:11.24#ibcon#read 4, iclass 38, count 0 2006.246.07:31:11.24#ibcon#about to read 5, iclass 38, count 0 2006.246.07:31:11.24#ibcon#read 5, iclass 38, count 0 2006.246.07:31:11.24#ibcon#about to read 6, iclass 38, count 0 2006.246.07:31:11.24#ibcon#read 6, iclass 38, count 0 2006.246.07:31:11.24#ibcon#end of sib2, iclass 38, count 0 2006.246.07:31:11.24#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:31:11.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:31:11.24#ibcon#[27=USB\r\n] 2006.246.07:31:11.24#ibcon#*before write, iclass 38, count 0 2006.246.07:31:11.24#ibcon#enter sib2, iclass 38, count 0 2006.246.07:31:11.24#ibcon#flushed, iclass 38, count 0 2006.246.07:31:11.24#ibcon#about to write, iclass 38, count 0 2006.246.07:31:11.24#ibcon#wrote, iclass 38, count 0 2006.246.07:31:11.24#ibcon#about to read 3, iclass 38, count 0 2006.246.07:31:11.27#ibcon#read 3, iclass 38, count 0 2006.246.07:31:11.27#ibcon#about to read 4, iclass 38, count 0 2006.246.07:31:11.27#ibcon#read 4, iclass 38, count 0 2006.246.07:31:11.27#ibcon#about to read 5, iclass 38, count 0 2006.246.07:31:11.27#ibcon#read 5, iclass 38, count 0 2006.246.07:31:11.27#ibcon#about to read 6, iclass 38, count 0 2006.246.07:31:11.27#ibcon#read 6, iclass 38, count 0 2006.246.07:31:11.27#ibcon#end of sib2, iclass 38, count 0 2006.246.07:31:11.27#ibcon#*after write, iclass 38, count 0 2006.246.07:31:11.27#ibcon#*before return 0, iclass 38, count 0 2006.246.07:31:11.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:11.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:31:11.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:31:11.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:31:11.27$vc4f8/vblo=3,656.99 2006.246.07:31:11.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:31:11.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:31:11.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:11.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:11.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:11.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:11.27#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:31:11.27#ibcon#first serial, iclass 40, count 0 2006.246.07:31:11.27#ibcon#enter sib2, iclass 40, count 0 2006.246.07:31:11.27#ibcon#flushed, iclass 40, count 0 2006.246.07:31:11.27#ibcon#about to write, iclass 40, count 0 2006.246.07:31:11.27#ibcon#wrote, iclass 40, count 0 2006.246.07:31:11.27#ibcon#about to read 3, iclass 40, count 0 2006.246.07:31:11.29#ibcon#read 3, iclass 40, count 0 2006.246.07:31:11.29#ibcon#about to read 4, iclass 40, count 0 2006.246.07:31:11.29#ibcon#read 4, iclass 40, count 0 2006.246.07:31:11.29#ibcon#about to read 5, iclass 40, count 0 2006.246.07:31:11.29#ibcon#read 5, iclass 40, count 0 2006.246.07:31:11.29#ibcon#about to read 6, iclass 40, count 0 2006.246.07:31:11.29#ibcon#read 6, iclass 40, count 0 2006.246.07:31:11.29#ibcon#end of sib2, iclass 40, count 0 2006.246.07:31:11.29#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:31:11.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:31:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:31:11.29#ibcon#*before write, iclass 40, count 0 2006.246.07:31:11.29#ibcon#enter sib2, iclass 40, count 0 2006.246.07:31:11.29#ibcon#flushed, iclass 40, count 0 2006.246.07:31:11.29#ibcon#about to write, iclass 40, count 0 2006.246.07:31:11.29#ibcon#wrote, iclass 40, count 0 2006.246.07:31:11.29#ibcon#about to read 3, iclass 40, count 0 2006.246.07:31:11.33#ibcon#read 3, iclass 40, count 0 2006.246.07:31:11.33#ibcon#about to read 4, iclass 40, count 0 2006.246.07:31:11.33#ibcon#read 4, iclass 40, count 0 2006.246.07:31:11.33#ibcon#about to read 5, iclass 40, count 0 2006.246.07:31:11.33#ibcon#read 5, iclass 40, count 0 2006.246.07:31:11.33#ibcon#about to read 6, iclass 40, count 0 2006.246.07:31:11.33#ibcon#read 6, iclass 40, count 0 2006.246.07:31:11.33#ibcon#end of sib2, iclass 40, count 0 2006.246.07:31:11.33#ibcon#*after write, iclass 40, count 0 2006.246.07:31:11.33#ibcon#*before return 0, iclass 40, count 0 2006.246.07:31:11.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:11.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:31:11.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:31:11.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:31:11.33$vc4f8/vb=3,4 2006.246.07:31:11.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.07:31:11.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.07:31:11.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:11.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:11.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:11.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:11.39#ibcon#enter wrdev, iclass 4, count 2 2006.246.07:31:11.39#ibcon#first serial, iclass 4, count 2 2006.246.07:31:11.39#ibcon#enter sib2, iclass 4, count 2 2006.246.07:31:11.39#ibcon#flushed, iclass 4, count 2 2006.246.07:31:11.39#ibcon#about to write, iclass 4, count 2 2006.246.07:31:11.39#ibcon#wrote, iclass 4, count 2 2006.246.07:31:11.39#ibcon#about to read 3, iclass 4, count 2 2006.246.07:31:11.41#ibcon#read 3, iclass 4, count 2 2006.246.07:31:11.41#ibcon#about to read 4, iclass 4, count 2 2006.246.07:31:11.41#ibcon#read 4, iclass 4, count 2 2006.246.07:31:11.41#ibcon#about to read 5, iclass 4, count 2 2006.246.07:31:11.41#ibcon#read 5, iclass 4, count 2 2006.246.07:31:11.41#ibcon#about to read 6, iclass 4, count 2 2006.246.07:31:11.41#ibcon#read 6, iclass 4, count 2 2006.246.07:31:11.41#ibcon#end of sib2, iclass 4, count 2 2006.246.07:31:11.41#ibcon#*mode == 0, iclass 4, count 2 2006.246.07:31:11.41#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.07:31:11.41#ibcon#[27=AT03-04\r\n] 2006.246.07:31:11.41#ibcon#*before write, iclass 4, count 2 2006.246.07:31:11.41#ibcon#enter sib2, iclass 4, count 2 2006.246.07:31:11.41#ibcon#flushed, iclass 4, count 2 2006.246.07:31:11.41#ibcon#about to write, iclass 4, count 2 2006.246.07:31:11.41#ibcon#wrote, iclass 4, count 2 2006.246.07:31:11.41#ibcon#about to read 3, iclass 4, count 2 2006.246.07:31:11.44#ibcon#read 3, iclass 4, count 2 2006.246.07:31:11.44#ibcon#about to read 4, iclass 4, count 2 2006.246.07:31:11.44#ibcon#read 4, iclass 4, count 2 2006.246.07:31:11.44#ibcon#about to read 5, iclass 4, count 2 2006.246.07:31:11.44#ibcon#read 5, iclass 4, count 2 2006.246.07:31:11.44#ibcon#about to read 6, iclass 4, count 2 2006.246.07:31:11.44#ibcon#read 6, iclass 4, count 2 2006.246.07:31:11.44#ibcon#end of sib2, iclass 4, count 2 2006.246.07:31:11.44#ibcon#*after write, iclass 4, count 2 2006.246.07:31:11.44#ibcon#*before return 0, iclass 4, count 2 2006.246.07:31:11.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:11.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:31:11.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.07:31:11.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:11.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:11.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:11.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:11.56#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:31:11.56#ibcon#first serial, iclass 4, count 0 2006.246.07:31:11.56#ibcon#enter sib2, iclass 4, count 0 2006.246.07:31:11.56#ibcon#flushed, iclass 4, count 0 2006.246.07:31:11.56#ibcon#about to write, iclass 4, count 0 2006.246.07:31:11.56#ibcon#wrote, iclass 4, count 0 2006.246.07:31:11.56#ibcon#about to read 3, iclass 4, count 0 2006.246.07:31:11.58#ibcon#read 3, iclass 4, count 0 2006.246.07:31:11.58#ibcon#about to read 4, iclass 4, count 0 2006.246.07:31:11.58#ibcon#read 4, iclass 4, count 0 2006.246.07:31:11.58#ibcon#about to read 5, iclass 4, count 0 2006.246.07:31:11.58#ibcon#read 5, iclass 4, count 0 2006.246.07:31:11.58#ibcon#about to read 6, iclass 4, count 0 2006.246.07:31:11.58#ibcon#read 6, iclass 4, count 0 2006.246.07:31:11.58#ibcon#end of sib2, iclass 4, count 0 2006.246.07:31:11.58#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:31:11.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:31:11.58#ibcon#[27=USB\r\n] 2006.246.07:31:11.58#ibcon#*before write, iclass 4, count 0 2006.246.07:31:11.58#ibcon#enter sib2, iclass 4, count 0 2006.246.07:31:11.58#ibcon#flushed, iclass 4, count 0 2006.246.07:31:11.58#ibcon#about to write, iclass 4, count 0 2006.246.07:31:11.58#ibcon#wrote, iclass 4, count 0 2006.246.07:31:11.58#ibcon#about to read 3, iclass 4, count 0 2006.246.07:31:11.61#ibcon#read 3, iclass 4, count 0 2006.246.07:31:11.61#ibcon#about to read 4, iclass 4, count 0 2006.246.07:31:11.61#ibcon#read 4, iclass 4, count 0 2006.246.07:31:11.61#ibcon#about to read 5, iclass 4, count 0 2006.246.07:31:11.61#ibcon#read 5, iclass 4, count 0 2006.246.07:31:11.61#ibcon#about to read 6, iclass 4, count 0 2006.246.07:31:11.61#ibcon#read 6, iclass 4, count 0 2006.246.07:31:11.61#ibcon#end of sib2, iclass 4, count 0 2006.246.07:31:11.61#ibcon#*after write, iclass 4, count 0 2006.246.07:31:11.61#ibcon#*before return 0, iclass 4, count 0 2006.246.07:31:11.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:11.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:31:11.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:31:11.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:31:11.61$vc4f8/vblo=4,712.99 2006.246.07:31:11.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.07:31:11.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.07:31:11.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:11.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:11.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:11.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:11.61#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:31:11.61#ibcon#first serial, iclass 6, count 0 2006.246.07:31:11.61#ibcon#enter sib2, iclass 6, count 0 2006.246.07:31:11.61#ibcon#flushed, iclass 6, count 0 2006.246.07:31:11.61#ibcon#about to write, iclass 6, count 0 2006.246.07:31:11.61#ibcon#wrote, iclass 6, count 0 2006.246.07:31:11.61#ibcon#about to read 3, iclass 6, count 0 2006.246.07:31:11.63#ibcon#read 3, iclass 6, count 0 2006.246.07:31:11.63#ibcon#about to read 4, iclass 6, count 0 2006.246.07:31:11.63#ibcon#read 4, iclass 6, count 0 2006.246.07:31:11.63#ibcon#about to read 5, iclass 6, count 0 2006.246.07:31:11.63#ibcon#read 5, iclass 6, count 0 2006.246.07:31:11.63#ibcon#about to read 6, iclass 6, count 0 2006.246.07:31:11.63#ibcon#read 6, iclass 6, count 0 2006.246.07:31:11.63#ibcon#end of sib2, iclass 6, count 0 2006.246.07:31:11.63#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:31:11.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:31:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:31:11.63#ibcon#*before write, iclass 6, count 0 2006.246.07:31:11.63#ibcon#enter sib2, iclass 6, count 0 2006.246.07:31:11.63#ibcon#flushed, iclass 6, count 0 2006.246.07:31:11.63#ibcon#about to write, iclass 6, count 0 2006.246.07:31:11.63#ibcon#wrote, iclass 6, count 0 2006.246.07:31:11.63#ibcon#about to read 3, iclass 6, count 0 2006.246.07:31:11.67#ibcon#read 3, iclass 6, count 0 2006.246.07:31:11.67#ibcon#about to read 4, iclass 6, count 0 2006.246.07:31:11.67#ibcon#read 4, iclass 6, count 0 2006.246.07:31:11.67#ibcon#about to read 5, iclass 6, count 0 2006.246.07:31:11.67#ibcon#read 5, iclass 6, count 0 2006.246.07:31:11.67#ibcon#about to read 6, iclass 6, count 0 2006.246.07:31:11.67#ibcon#read 6, iclass 6, count 0 2006.246.07:31:11.67#ibcon#end of sib2, iclass 6, count 0 2006.246.07:31:11.67#ibcon#*after write, iclass 6, count 0 2006.246.07:31:11.67#ibcon#*before return 0, iclass 6, count 0 2006.246.07:31:11.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:11.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:31:11.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:31:11.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:31:11.67$vc4f8/vb=4,4 2006.246.07:31:11.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.07:31:11.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.07:31:11.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:11.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:11.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:11.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:11.73#ibcon#enter wrdev, iclass 10, count 2 2006.246.07:31:11.73#ibcon#first serial, iclass 10, count 2 2006.246.07:31:11.73#ibcon#enter sib2, iclass 10, count 2 2006.246.07:31:11.73#ibcon#flushed, iclass 10, count 2 2006.246.07:31:11.73#ibcon#about to write, iclass 10, count 2 2006.246.07:31:11.73#ibcon#wrote, iclass 10, count 2 2006.246.07:31:11.73#ibcon#about to read 3, iclass 10, count 2 2006.246.07:31:11.75#ibcon#read 3, iclass 10, count 2 2006.246.07:31:11.75#ibcon#about to read 4, iclass 10, count 2 2006.246.07:31:11.75#ibcon#read 4, iclass 10, count 2 2006.246.07:31:11.75#ibcon#about to read 5, iclass 10, count 2 2006.246.07:31:11.75#ibcon#read 5, iclass 10, count 2 2006.246.07:31:11.75#ibcon#about to read 6, iclass 10, count 2 2006.246.07:31:11.75#ibcon#read 6, iclass 10, count 2 2006.246.07:31:11.75#ibcon#end of sib2, iclass 10, count 2 2006.246.07:31:11.75#ibcon#*mode == 0, iclass 10, count 2 2006.246.07:31:11.75#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.07:31:11.75#ibcon#[27=AT04-04\r\n] 2006.246.07:31:11.75#ibcon#*before write, iclass 10, count 2 2006.246.07:31:11.75#ibcon#enter sib2, iclass 10, count 2 2006.246.07:31:11.75#ibcon#flushed, iclass 10, count 2 2006.246.07:31:11.75#ibcon#about to write, iclass 10, count 2 2006.246.07:31:11.75#ibcon#wrote, iclass 10, count 2 2006.246.07:31:11.75#ibcon#about to read 3, iclass 10, count 2 2006.246.07:31:11.78#ibcon#read 3, iclass 10, count 2 2006.246.07:31:11.78#ibcon#about to read 4, iclass 10, count 2 2006.246.07:31:11.78#ibcon#read 4, iclass 10, count 2 2006.246.07:31:11.78#ibcon#about to read 5, iclass 10, count 2 2006.246.07:31:11.78#ibcon#read 5, iclass 10, count 2 2006.246.07:31:11.78#ibcon#about to read 6, iclass 10, count 2 2006.246.07:31:11.78#ibcon#read 6, iclass 10, count 2 2006.246.07:31:11.78#ibcon#end of sib2, iclass 10, count 2 2006.246.07:31:11.78#ibcon#*after write, iclass 10, count 2 2006.246.07:31:11.78#ibcon#*before return 0, iclass 10, count 2 2006.246.07:31:11.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:11.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:31:11.78#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.07:31:11.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:11.78#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:11.90#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:11.90#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:11.90#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:31:11.90#ibcon#first serial, iclass 10, count 0 2006.246.07:31:11.90#ibcon#enter sib2, iclass 10, count 0 2006.246.07:31:11.90#ibcon#flushed, iclass 10, count 0 2006.246.07:31:11.90#ibcon#about to write, iclass 10, count 0 2006.246.07:31:11.90#ibcon#wrote, iclass 10, count 0 2006.246.07:31:11.90#ibcon#about to read 3, iclass 10, count 0 2006.246.07:31:11.92#ibcon#read 3, iclass 10, count 0 2006.246.07:31:11.92#ibcon#about to read 4, iclass 10, count 0 2006.246.07:31:11.92#ibcon#read 4, iclass 10, count 0 2006.246.07:31:11.92#ibcon#about to read 5, iclass 10, count 0 2006.246.07:31:11.92#ibcon#read 5, iclass 10, count 0 2006.246.07:31:11.92#ibcon#about to read 6, iclass 10, count 0 2006.246.07:31:11.92#ibcon#read 6, iclass 10, count 0 2006.246.07:31:11.92#ibcon#end of sib2, iclass 10, count 0 2006.246.07:31:11.92#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:31:11.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:31:11.92#ibcon#[27=USB\r\n] 2006.246.07:31:11.92#ibcon#*before write, iclass 10, count 0 2006.246.07:31:11.92#ibcon#enter sib2, iclass 10, count 0 2006.246.07:31:11.92#ibcon#flushed, iclass 10, count 0 2006.246.07:31:11.92#ibcon#about to write, iclass 10, count 0 2006.246.07:31:11.92#ibcon#wrote, iclass 10, count 0 2006.246.07:31:11.92#ibcon#about to read 3, iclass 10, count 0 2006.246.07:31:11.95#ibcon#read 3, iclass 10, count 0 2006.246.07:31:11.95#ibcon#about to read 4, iclass 10, count 0 2006.246.07:31:11.95#ibcon#read 4, iclass 10, count 0 2006.246.07:31:11.95#ibcon#about to read 5, iclass 10, count 0 2006.246.07:31:11.95#ibcon#read 5, iclass 10, count 0 2006.246.07:31:11.95#ibcon#about to read 6, iclass 10, count 0 2006.246.07:31:11.95#ibcon#read 6, iclass 10, count 0 2006.246.07:31:11.95#ibcon#end of sib2, iclass 10, count 0 2006.246.07:31:11.95#ibcon#*after write, iclass 10, count 0 2006.246.07:31:11.95#ibcon#*before return 0, iclass 10, count 0 2006.246.07:31:11.95#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:11.95#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:31:11.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:31:11.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:31:11.95$vc4f8/vblo=5,744.99 2006.246.07:31:11.95#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.07:31:11.95#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.07:31:11.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:11.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:11.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:11.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:11.95#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:31:11.95#ibcon#first serial, iclass 12, count 0 2006.246.07:31:11.95#ibcon#enter sib2, iclass 12, count 0 2006.246.07:31:11.95#ibcon#flushed, iclass 12, count 0 2006.246.07:31:11.95#ibcon#about to write, iclass 12, count 0 2006.246.07:31:11.95#ibcon#wrote, iclass 12, count 0 2006.246.07:31:11.95#ibcon#about to read 3, iclass 12, count 0 2006.246.07:31:11.97#ibcon#read 3, iclass 12, count 0 2006.246.07:31:11.97#ibcon#about to read 4, iclass 12, count 0 2006.246.07:31:11.97#ibcon#read 4, iclass 12, count 0 2006.246.07:31:11.97#ibcon#about to read 5, iclass 12, count 0 2006.246.07:31:11.97#ibcon#read 5, iclass 12, count 0 2006.246.07:31:11.97#ibcon#about to read 6, iclass 12, count 0 2006.246.07:31:11.97#ibcon#read 6, iclass 12, count 0 2006.246.07:31:11.97#ibcon#end of sib2, iclass 12, count 0 2006.246.07:31:11.97#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:31:11.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:31:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:31:11.97#ibcon#*before write, iclass 12, count 0 2006.246.07:31:11.97#ibcon#enter sib2, iclass 12, count 0 2006.246.07:31:11.97#ibcon#flushed, iclass 12, count 0 2006.246.07:31:11.97#ibcon#about to write, iclass 12, count 0 2006.246.07:31:11.97#ibcon#wrote, iclass 12, count 0 2006.246.07:31:11.97#ibcon#about to read 3, iclass 12, count 0 2006.246.07:31:12.01#ibcon#read 3, iclass 12, count 0 2006.246.07:31:12.01#ibcon#about to read 4, iclass 12, count 0 2006.246.07:31:12.01#ibcon#read 4, iclass 12, count 0 2006.246.07:31:12.01#ibcon#about to read 5, iclass 12, count 0 2006.246.07:31:12.01#ibcon#read 5, iclass 12, count 0 2006.246.07:31:12.01#ibcon#about to read 6, iclass 12, count 0 2006.246.07:31:12.01#ibcon#read 6, iclass 12, count 0 2006.246.07:31:12.01#ibcon#end of sib2, iclass 12, count 0 2006.246.07:31:12.01#ibcon#*after write, iclass 12, count 0 2006.246.07:31:12.01#ibcon#*before return 0, iclass 12, count 0 2006.246.07:31:12.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:12.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:31:12.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:31:12.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:31:12.01$vc4f8/vb=5,3 2006.246.07:31:12.01#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.07:31:12.01#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.07:31:12.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:12.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:12.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:12.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:12.07#ibcon#enter wrdev, iclass 14, count 2 2006.246.07:31:12.07#ibcon#first serial, iclass 14, count 2 2006.246.07:31:12.07#ibcon#enter sib2, iclass 14, count 2 2006.246.07:31:12.07#ibcon#flushed, iclass 14, count 2 2006.246.07:31:12.07#ibcon#about to write, iclass 14, count 2 2006.246.07:31:12.07#ibcon#wrote, iclass 14, count 2 2006.246.07:31:12.07#ibcon#about to read 3, iclass 14, count 2 2006.246.07:31:12.09#ibcon#read 3, iclass 14, count 2 2006.246.07:31:12.09#ibcon#about to read 4, iclass 14, count 2 2006.246.07:31:12.09#ibcon#read 4, iclass 14, count 2 2006.246.07:31:12.09#ibcon#about to read 5, iclass 14, count 2 2006.246.07:31:12.09#ibcon#read 5, iclass 14, count 2 2006.246.07:31:12.09#ibcon#about to read 6, iclass 14, count 2 2006.246.07:31:12.09#ibcon#read 6, iclass 14, count 2 2006.246.07:31:12.09#ibcon#end of sib2, iclass 14, count 2 2006.246.07:31:12.09#ibcon#*mode == 0, iclass 14, count 2 2006.246.07:31:12.09#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.07:31:12.09#ibcon#[27=AT05-03\r\n] 2006.246.07:31:12.09#ibcon#*before write, iclass 14, count 2 2006.246.07:31:12.09#ibcon#enter sib2, iclass 14, count 2 2006.246.07:31:12.09#ibcon#flushed, iclass 14, count 2 2006.246.07:31:12.09#ibcon#about to write, iclass 14, count 2 2006.246.07:31:12.09#ibcon#wrote, iclass 14, count 2 2006.246.07:31:12.09#ibcon#about to read 3, iclass 14, count 2 2006.246.07:31:12.12#ibcon#read 3, iclass 14, count 2 2006.246.07:31:12.12#ibcon#about to read 4, iclass 14, count 2 2006.246.07:31:12.12#ibcon#read 4, iclass 14, count 2 2006.246.07:31:12.12#ibcon#about to read 5, iclass 14, count 2 2006.246.07:31:12.12#ibcon#read 5, iclass 14, count 2 2006.246.07:31:12.12#ibcon#about to read 6, iclass 14, count 2 2006.246.07:31:12.12#ibcon#read 6, iclass 14, count 2 2006.246.07:31:12.12#ibcon#end of sib2, iclass 14, count 2 2006.246.07:31:12.12#ibcon#*after write, iclass 14, count 2 2006.246.07:31:12.12#ibcon#*before return 0, iclass 14, count 2 2006.246.07:31:12.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:12.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:31:12.12#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.07:31:12.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:12.12#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:12.24#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:12.24#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:12.24#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:31:12.24#ibcon#first serial, iclass 14, count 0 2006.246.07:31:12.24#ibcon#enter sib2, iclass 14, count 0 2006.246.07:31:12.24#ibcon#flushed, iclass 14, count 0 2006.246.07:31:12.24#ibcon#about to write, iclass 14, count 0 2006.246.07:31:12.24#ibcon#wrote, iclass 14, count 0 2006.246.07:31:12.24#ibcon#about to read 3, iclass 14, count 0 2006.246.07:31:12.26#ibcon#read 3, iclass 14, count 0 2006.246.07:31:12.26#ibcon#about to read 4, iclass 14, count 0 2006.246.07:31:12.26#ibcon#read 4, iclass 14, count 0 2006.246.07:31:12.26#ibcon#about to read 5, iclass 14, count 0 2006.246.07:31:12.26#ibcon#read 5, iclass 14, count 0 2006.246.07:31:12.26#ibcon#about to read 6, iclass 14, count 0 2006.246.07:31:12.26#ibcon#read 6, iclass 14, count 0 2006.246.07:31:12.26#ibcon#end of sib2, iclass 14, count 0 2006.246.07:31:12.26#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:31:12.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:31:12.26#ibcon#[27=USB\r\n] 2006.246.07:31:12.26#ibcon#*before write, iclass 14, count 0 2006.246.07:31:12.26#ibcon#enter sib2, iclass 14, count 0 2006.246.07:31:12.26#ibcon#flushed, iclass 14, count 0 2006.246.07:31:12.26#ibcon#about to write, iclass 14, count 0 2006.246.07:31:12.26#ibcon#wrote, iclass 14, count 0 2006.246.07:31:12.26#ibcon#about to read 3, iclass 14, count 0 2006.246.07:31:12.29#ibcon#read 3, iclass 14, count 0 2006.246.07:31:12.29#ibcon#about to read 4, iclass 14, count 0 2006.246.07:31:12.29#ibcon#read 4, iclass 14, count 0 2006.246.07:31:12.29#ibcon#about to read 5, iclass 14, count 0 2006.246.07:31:12.29#ibcon#read 5, iclass 14, count 0 2006.246.07:31:12.29#ibcon#about to read 6, iclass 14, count 0 2006.246.07:31:12.29#ibcon#read 6, iclass 14, count 0 2006.246.07:31:12.29#ibcon#end of sib2, iclass 14, count 0 2006.246.07:31:12.29#ibcon#*after write, iclass 14, count 0 2006.246.07:31:12.29#ibcon#*before return 0, iclass 14, count 0 2006.246.07:31:12.29#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:12.29#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:31:12.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:31:12.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:31:12.29$vc4f8/vblo=6,752.99 2006.246.07:31:12.29#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.07:31:12.29#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.07:31:12.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:31:12.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:12.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:12.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:12.29#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:31:12.29#ibcon#first serial, iclass 16, count 0 2006.246.07:31:12.29#ibcon#enter sib2, iclass 16, count 0 2006.246.07:31:12.29#ibcon#flushed, iclass 16, count 0 2006.246.07:31:12.29#ibcon#about to write, iclass 16, count 0 2006.246.07:31:12.29#ibcon#wrote, iclass 16, count 0 2006.246.07:31:12.29#ibcon#about to read 3, iclass 16, count 0 2006.246.07:31:12.31#ibcon#read 3, iclass 16, count 0 2006.246.07:31:12.31#ibcon#about to read 4, iclass 16, count 0 2006.246.07:31:12.31#ibcon#read 4, iclass 16, count 0 2006.246.07:31:12.31#ibcon#about to read 5, iclass 16, count 0 2006.246.07:31:12.31#ibcon#read 5, iclass 16, count 0 2006.246.07:31:12.31#ibcon#about to read 6, iclass 16, count 0 2006.246.07:31:12.31#ibcon#read 6, iclass 16, count 0 2006.246.07:31:12.31#ibcon#end of sib2, iclass 16, count 0 2006.246.07:31:12.31#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:31:12.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:31:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:31:12.31#ibcon#*before write, iclass 16, count 0 2006.246.07:31:12.31#ibcon#enter sib2, iclass 16, count 0 2006.246.07:31:12.31#ibcon#flushed, iclass 16, count 0 2006.246.07:31:12.31#ibcon#about to write, iclass 16, count 0 2006.246.07:31:12.31#ibcon#wrote, iclass 16, count 0 2006.246.07:31:12.31#ibcon#about to read 3, iclass 16, count 0 2006.246.07:31:12.35#ibcon#read 3, iclass 16, count 0 2006.246.07:31:12.35#ibcon#about to read 4, iclass 16, count 0 2006.246.07:31:12.35#ibcon#read 4, iclass 16, count 0 2006.246.07:31:12.35#ibcon#about to read 5, iclass 16, count 0 2006.246.07:31:12.35#ibcon#read 5, iclass 16, count 0 2006.246.07:31:12.35#ibcon#about to read 6, iclass 16, count 0 2006.246.07:31:12.35#ibcon#read 6, iclass 16, count 0 2006.246.07:31:12.35#ibcon#end of sib2, iclass 16, count 0 2006.246.07:31:12.35#ibcon#*after write, iclass 16, count 0 2006.246.07:31:12.35#ibcon#*before return 0, iclass 16, count 0 2006.246.07:31:12.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:12.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:31:12.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:31:12.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:31:12.35$vc4f8/vb=6,3 2006.246.07:31:12.35#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.07:31:12.35#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.07:31:12.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:31:12.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:12.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:12.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:12.41#ibcon#enter wrdev, iclass 18, count 2 2006.246.07:31:12.41#ibcon#first serial, iclass 18, count 2 2006.246.07:31:12.41#ibcon#enter sib2, iclass 18, count 2 2006.246.07:31:12.41#ibcon#flushed, iclass 18, count 2 2006.246.07:31:12.41#ibcon#about to write, iclass 18, count 2 2006.246.07:31:12.41#ibcon#wrote, iclass 18, count 2 2006.246.07:31:12.41#ibcon#about to read 3, iclass 18, count 2 2006.246.07:31:12.43#ibcon#read 3, iclass 18, count 2 2006.246.07:31:12.43#ibcon#about to read 4, iclass 18, count 2 2006.246.07:31:12.43#ibcon#read 4, iclass 18, count 2 2006.246.07:31:12.43#ibcon#about to read 5, iclass 18, count 2 2006.246.07:31:12.43#ibcon#read 5, iclass 18, count 2 2006.246.07:31:12.43#ibcon#about to read 6, iclass 18, count 2 2006.246.07:31:12.43#ibcon#read 6, iclass 18, count 2 2006.246.07:31:12.43#ibcon#end of sib2, iclass 18, count 2 2006.246.07:31:12.43#ibcon#*mode == 0, iclass 18, count 2 2006.246.07:31:12.43#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.07:31:12.43#ibcon#[27=AT06-03\r\n] 2006.246.07:31:12.43#ibcon#*before write, iclass 18, count 2 2006.246.07:31:12.43#ibcon#enter sib2, iclass 18, count 2 2006.246.07:31:12.43#ibcon#flushed, iclass 18, count 2 2006.246.07:31:12.43#ibcon#about to write, iclass 18, count 2 2006.246.07:31:12.43#ibcon#wrote, iclass 18, count 2 2006.246.07:31:12.43#ibcon#about to read 3, iclass 18, count 2 2006.246.07:31:12.46#ibcon#read 3, iclass 18, count 2 2006.246.07:31:12.46#ibcon#about to read 4, iclass 18, count 2 2006.246.07:31:12.46#ibcon#read 4, iclass 18, count 2 2006.246.07:31:12.46#ibcon#about to read 5, iclass 18, count 2 2006.246.07:31:12.46#ibcon#read 5, iclass 18, count 2 2006.246.07:31:12.46#ibcon#about to read 6, iclass 18, count 2 2006.246.07:31:12.46#ibcon#read 6, iclass 18, count 2 2006.246.07:31:12.46#ibcon#end of sib2, iclass 18, count 2 2006.246.07:31:12.46#ibcon#*after write, iclass 18, count 2 2006.246.07:31:12.46#ibcon#*before return 0, iclass 18, count 2 2006.246.07:31:12.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:12.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:31:12.46#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.07:31:12.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:31:12.46#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:12.58#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:12.58#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:12.58#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:31:12.58#ibcon#first serial, iclass 18, count 0 2006.246.07:31:12.58#ibcon#enter sib2, iclass 18, count 0 2006.246.07:31:12.58#ibcon#flushed, iclass 18, count 0 2006.246.07:31:12.58#ibcon#about to write, iclass 18, count 0 2006.246.07:31:12.58#ibcon#wrote, iclass 18, count 0 2006.246.07:31:12.58#ibcon#about to read 3, iclass 18, count 0 2006.246.07:31:12.60#ibcon#read 3, iclass 18, count 0 2006.246.07:31:12.60#ibcon#about to read 4, iclass 18, count 0 2006.246.07:31:12.60#ibcon#read 4, iclass 18, count 0 2006.246.07:31:12.60#ibcon#about to read 5, iclass 18, count 0 2006.246.07:31:12.60#ibcon#read 5, iclass 18, count 0 2006.246.07:31:12.60#ibcon#about to read 6, iclass 18, count 0 2006.246.07:31:12.60#ibcon#read 6, iclass 18, count 0 2006.246.07:31:12.60#ibcon#end of sib2, iclass 18, count 0 2006.246.07:31:12.60#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:31:12.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:31:12.60#ibcon#[27=USB\r\n] 2006.246.07:31:12.60#ibcon#*before write, iclass 18, count 0 2006.246.07:31:12.60#ibcon#enter sib2, iclass 18, count 0 2006.246.07:31:12.60#ibcon#flushed, iclass 18, count 0 2006.246.07:31:12.60#ibcon#about to write, iclass 18, count 0 2006.246.07:31:12.60#ibcon#wrote, iclass 18, count 0 2006.246.07:31:12.60#ibcon#about to read 3, iclass 18, count 0 2006.246.07:31:12.63#ibcon#read 3, iclass 18, count 0 2006.246.07:31:12.63#ibcon#about to read 4, iclass 18, count 0 2006.246.07:31:12.63#ibcon#read 4, iclass 18, count 0 2006.246.07:31:12.63#ibcon#about to read 5, iclass 18, count 0 2006.246.07:31:12.63#ibcon#read 5, iclass 18, count 0 2006.246.07:31:12.63#ibcon#about to read 6, iclass 18, count 0 2006.246.07:31:12.63#ibcon#read 6, iclass 18, count 0 2006.246.07:31:12.63#ibcon#end of sib2, iclass 18, count 0 2006.246.07:31:12.63#ibcon#*after write, iclass 18, count 0 2006.246.07:31:12.63#ibcon#*before return 0, iclass 18, count 0 2006.246.07:31:12.63#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:12.63#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:31:12.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:31:12.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:31:12.63$vc4f8/vabw=wide 2006.246.07:31:12.63#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.07:31:12.63#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.07:31:12.63#ibcon#ireg 8 cls_cnt 0 2006.246.07:31:12.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:12.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:12.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:12.63#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:31:12.63#ibcon#first serial, iclass 20, count 0 2006.246.07:31:12.63#ibcon#enter sib2, iclass 20, count 0 2006.246.07:31:12.63#ibcon#flushed, iclass 20, count 0 2006.246.07:31:12.63#ibcon#about to write, iclass 20, count 0 2006.246.07:31:12.63#ibcon#wrote, iclass 20, count 0 2006.246.07:31:12.63#ibcon#about to read 3, iclass 20, count 0 2006.246.07:31:12.65#ibcon#read 3, iclass 20, count 0 2006.246.07:31:12.65#ibcon#about to read 4, iclass 20, count 0 2006.246.07:31:12.65#ibcon#read 4, iclass 20, count 0 2006.246.07:31:12.65#ibcon#about to read 5, iclass 20, count 0 2006.246.07:31:12.65#ibcon#read 5, iclass 20, count 0 2006.246.07:31:12.65#ibcon#about to read 6, iclass 20, count 0 2006.246.07:31:12.65#ibcon#read 6, iclass 20, count 0 2006.246.07:31:12.65#ibcon#end of sib2, iclass 20, count 0 2006.246.07:31:12.65#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:31:12.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:31:12.65#ibcon#[25=BW32\r\n] 2006.246.07:31:12.65#ibcon#*before write, iclass 20, count 0 2006.246.07:31:12.65#ibcon#enter sib2, iclass 20, count 0 2006.246.07:31:12.65#ibcon#flushed, iclass 20, count 0 2006.246.07:31:12.65#ibcon#about to write, iclass 20, count 0 2006.246.07:31:12.65#ibcon#wrote, iclass 20, count 0 2006.246.07:31:12.65#ibcon#about to read 3, iclass 20, count 0 2006.246.07:31:12.68#ibcon#read 3, iclass 20, count 0 2006.246.07:31:12.68#ibcon#about to read 4, iclass 20, count 0 2006.246.07:31:12.68#ibcon#read 4, iclass 20, count 0 2006.246.07:31:12.68#ibcon#about to read 5, iclass 20, count 0 2006.246.07:31:12.68#ibcon#read 5, iclass 20, count 0 2006.246.07:31:12.68#ibcon#about to read 6, iclass 20, count 0 2006.246.07:31:12.68#ibcon#read 6, iclass 20, count 0 2006.246.07:31:12.68#ibcon#end of sib2, iclass 20, count 0 2006.246.07:31:12.68#ibcon#*after write, iclass 20, count 0 2006.246.07:31:12.68#ibcon#*before return 0, iclass 20, count 0 2006.246.07:31:12.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:12.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:31:12.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:31:12.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:31:12.68$vc4f8/vbbw=wide 2006.246.07:31:12.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:31:12.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:31:12.68#ibcon#ireg 8 cls_cnt 0 2006.246.07:31:12.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:31:12.75#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:31:12.75#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:31:12.75#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:31:12.75#ibcon#first serial, iclass 22, count 0 2006.246.07:31:12.75#ibcon#enter sib2, iclass 22, count 0 2006.246.07:31:12.75#ibcon#flushed, iclass 22, count 0 2006.246.07:31:12.75#ibcon#about to write, iclass 22, count 0 2006.246.07:31:12.75#ibcon#wrote, iclass 22, count 0 2006.246.07:31:12.75#ibcon#about to read 3, iclass 22, count 0 2006.246.07:31:12.77#ibcon#read 3, iclass 22, count 0 2006.246.07:31:12.77#ibcon#about to read 4, iclass 22, count 0 2006.246.07:31:12.77#ibcon#read 4, iclass 22, count 0 2006.246.07:31:12.77#ibcon#about to read 5, iclass 22, count 0 2006.246.07:31:12.77#ibcon#read 5, iclass 22, count 0 2006.246.07:31:12.77#ibcon#about to read 6, iclass 22, count 0 2006.246.07:31:12.77#ibcon#read 6, iclass 22, count 0 2006.246.07:31:12.77#ibcon#end of sib2, iclass 22, count 0 2006.246.07:31:12.77#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:31:12.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:31:12.77#ibcon#[27=BW32\r\n] 2006.246.07:31:12.77#ibcon#*before write, iclass 22, count 0 2006.246.07:31:12.77#ibcon#enter sib2, iclass 22, count 0 2006.246.07:31:12.77#ibcon#flushed, iclass 22, count 0 2006.246.07:31:12.77#ibcon#about to write, iclass 22, count 0 2006.246.07:31:12.77#ibcon#wrote, iclass 22, count 0 2006.246.07:31:12.77#ibcon#about to read 3, iclass 22, count 0 2006.246.07:31:12.80#ibcon#read 3, iclass 22, count 0 2006.246.07:31:12.80#ibcon#about to read 4, iclass 22, count 0 2006.246.07:31:12.80#ibcon#read 4, iclass 22, count 0 2006.246.07:31:12.80#ibcon#about to read 5, iclass 22, count 0 2006.246.07:31:12.80#ibcon#read 5, iclass 22, count 0 2006.246.07:31:12.80#ibcon#about to read 6, iclass 22, count 0 2006.246.07:31:12.80#ibcon#read 6, iclass 22, count 0 2006.246.07:31:12.80#ibcon#end of sib2, iclass 22, count 0 2006.246.07:31:12.80#ibcon#*after write, iclass 22, count 0 2006.246.07:31:12.80#ibcon#*before return 0, iclass 22, count 0 2006.246.07:31:12.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:31:12.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:31:12.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:31:12.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:31:12.80$4f8m12a/ifd4f 2006.246.07:31:12.80$ifd4f/lo= 2006.246.07:31:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:31:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:31:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:31:12.80$ifd4f/patch= 2006.246.07:31:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:31:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:31:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:31:12.80$4f8m12a/"form=m,16.000,1:2 2006.246.07:31:12.80$4f8m12a/"tpicd 2006.246.07:31:12.80$4f8m12a/echo=off 2006.246.07:31:12.80$4f8m12a/xlog=off 2006.246.07:31:12.80:!2006.246.07:33:20 2006.246.07:31:44.14#trakl#Source acquired 2006.246.07:31:46.14#flagr#flagr/antenna,acquired 2006.246.07:33:20.00:preob 2006.246.07:33:20.14/onsource/TRACKING 2006.246.07:33:20.14:!2006.246.07:33:30 2006.246.07:33:30.00:data_valid=on 2006.246.07:33:30.00:midob 2006.246.07:33:31.14/onsource/TRACKING 2006.246.07:33:31.14/wx/26.80,1005.6,74 2006.246.07:33:31.34/cable/+6.4121E-03 2006.246.07:33:32.43/va/01,08,usb,yes,33,35 2006.246.07:33:32.43/va/02,07,usb,yes,33,35 2006.246.07:33:32.43/va/03,06,usb,yes,35,35 2006.246.07:33:32.43/va/04,07,usb,yes,34,37 2006.246.07:33:32.43/va/05,07,usb,yes,36,38 2006.246.07:33:32.43/va/06,07,usb,yes,32,32 2006.246.07:33:32.43/va/07,07,usb,yes,32,32 2006.246.07:33:32.43/va/08,08,usb,yes,28,27 2006.246.07:33:32.66/valo/01,532.99,yes,locked 2006.246.07:33:32.66/valo/02,572.99,yes,locked 2006.246.07:33:32.66/valo/03,672.99,yes,locked 2006.246.07:33:32.66/valo/04,832.99,yes,locked 2006.246.07:33:32.66/valo/05,652.99,yes,locked 2006.246.07:33:32.66/valo/06,772.99,yes,locked 2006.246.07:33:32.66/valo/07,832.99,yes,locked 2006.246.07:33:32.66/valo/08,852.99,yes,locked 2006.246.07:33:33.75/vb/01,04,usb,yes,32,31 2006.246.07:33:33.75/vb/02,04,usb,yes,34,35 2006.246.07:33:33.75/vb/03,04,usb,yes,30,34 2006.246.07:33:33.75/vb/04,04,usb,yes,31,31 2006.246.07:33:33.75/vb/05,03,usb,yes,37,42 2006.246.07:33:33.75/vb/06,03,usb,yes,37,41 2006.246.07:33:33.75/vb/07,04,usb,yes,33,33 2006.246.07:33:33.75/vb/08,03,usb,yes,37,41 2006.246.07:33:33.98/vblo/01,632.99,yes,locked 2006.246.07:33:33.98/vblo/02,640.99,yes,locked 2006.246.07:33:33.98/vblo/03,656.99,yes,locked 2006.246.07:33:33.98/vblo/04,712.99,yes,locked 2006.246.07:33:33.98/vblo/05,744.99,yes,locked 2006.246.07:33:33.98/vblo/06,752.99,yes,locked 2006.246.07:33:33.98/vblo/07,734.99,yes,locked 2006.246.07:33:33.98/vblo/08,744.99,yes,locked 2006.246.07:33:34.13/vabw/8 2006.246.07:33:34.28/vbbw/8 2006.246.07:33:34.37/xfe/off,on,13.5 2006.246.07:33:34.75/ifatt/23,28,28,28 2006.246.07:33:35.08/fmout-gps/S +4.32E-07 2006.246.07:33:35.12:!2006.246.07:34:30 2006.246.07:34:30.00:data_valid=off 2006.246.07:34:30.00:postob 2006.246.07:34:30.13/cable/+6.4146E-03 2006.246.07:34:30.13/wx/26.80,1005.6,73 2006.246.07:34:31.08/fmout-gps/S +4.32E-07 2006.246.07:34:31.08:scan_name=246-0735,k06246,60 2006.246.07:34:31.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.246.07:34:31.14#flagr#flagr/antenna,new-source 2006.246.07:34:32.14:checkk5 2006.246.07:34:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:34:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:34:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:34:34.00/chk_obsdata//k5ts1/T2460733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:34:34.37/chk_obsdata//k5ts2/T2460733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:34:34.74/chk_obsdata//k5ts3/T2460733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:34:35.10/chk_obsdata//k5ts4/T2460733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:34:35.80/k5log//k5ts1_log_newline 2006.246.07:34:36.48/k5log//k5ts2_log_newline 2006.246.07:34:37.17/k5log//k5ts3_log_newline 2006.246.07:34:37.86/k5log//k5ts4_log_newline 2006.246.07:34:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:34:37.88:4f8m12a=1 2006.246.07:34:37.88$4f8m12a/echo=on 2006.246.07:34:37.88$4f8m12a/pcalon 2006.246.07:34:37.88$pcalon/"no phase cal control is implemented here 2006.246.07:34:37.88$4f8m12a/"tpicd=stop 2006.246.07:34:37.88$4f8m12a/vc4f8 2006.246.07:34:37.88$vc4f8/valo=1,532.99 2006.246.07:34:37.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.07:34:37.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.07:34:37.89#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:37.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:37.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:37.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:37.89#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:34:37.89#ibcon#first serial, iclass 37, count 0 2006.246.07:34:37.89#ibcon#enter sib2, iclass 37, count 0 2006.246.07:34:37.89#ibcon#flushed, iclass 37, count 0 2006.246.07:34:37.89#ibcon#about to write, iclass 37, count 0 2006.246.07:34:37.89#ibcon#wrote, iclass 37, count 0 2006.246.07:34:37.89#ibcon#about to read 3, iclass 37, count 0 2006.246.07:34:37.93#ibcon#read 3, iclass 37, count 0 2006.246.07:34:37.93#ibcon#about to read 4, iclass 37, count 0 2006.246.07:34:37.93#ibcon#read 4, iclass 37, count 0 2006.246.07:34:37.93#ibcon#about to read 5, iclass 37, count 0 2006.246.07:34:37.93#ibcon#read 5, iclass 37, count 0 2006.246.07:34:37.93#ibcon#about to read 6, iclass 37, count 0 2006.246.07:34:37.93#ibcon#read 6, iclass 37, count 0 2006.246.07:34:37.93#ibcon#end of sib2, iclass 37, count 0 2006.246.07:34:37.93#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:34:37.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:34:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:34:37.93#ibcon#*before write, iclass 37, count 0 2006.246.07:34:37.93#ibcon#enter sib2, iclass 37, count 0 2006.246.07:34:37.93#ibcon#flushed, iclass 37, count 0 2006.246.07:34:37.93#ibcon#about to write, iclass 37, count 0 2006.246.07:34:37.93#ibcon#wrote, iclass 37, count 0 2006.246.07:34:37.93#ibcon#about to read 3, iclass 37, count 0 2006.246.07:34:37.98#ibcon#read 3, iclass 37, count 0 2006.246.07:34:37.98#ibcon#about to read 4, iclass 37, count 0 2006.246.07:34:37.98#ibcon#read 4, iclass 37, count 0 2006.246.07:34:37.98#ibcon#about to read 5, iclass 37, count 0 2006.246.07:34:37.98#ibcon#read 5, iclass 37, count 0 2006.246.07:34:37.98#ibcon#about to read 6, iclass 37, count 0 2006.246.07:34:37.98#ibcon#read 6, iclass 37, count 0 2006.246.07:34:37.98#ibcon#end of sib2, iclass 37, count 0 2006.246.07:34:37.98#ibcon#*after write, iclass 37, count 0 2006.246.07:34:37.98#ibcon#*before return 0, iclass 37, count 0 2006.246.07:34:37.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:37.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:37.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:34:37.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:34:37.98$vc4f8/va=1,8 2006.246.07:34:37.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.07:34:37.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.07:34:37.98#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:37.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:37.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:37.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:37.98#ibcon#enter wrdev, iclass 39, count 2 2006.246.07:34:37.98#ibcon#first serial, iclass 39, count 2 2006.246.07:34:37.98#ibcon#enter sib2, iclass 39, count 2 2006.246.07:34:37.98#ibcon#flushed, iclass 39, count 2 2006.246.07:34:37.98#ibcon#about to write, iclass 39, count 2 2006.246.07:34:37.98#ibcon#wrote, iclass 39, count 2 2006.246.07:34:37.98#ibcon#about to read 3, iclass 39, count 2 2006.246.07:34:38.00#ibcon#read 3, iclass 39, count 2 2006.246.07:34:38.00#ibcon#about to read 4, iclass 39, count 2 2006.246.07:34:38.00#ibcon#read 4, iclass 39, count 2 2006.246.07:34:38.00#ibcon#about to read 5, iclass 39, count 2 2006.246.07:34:38.00#ibcon#read 5, iclass 39, count 2 2006.246.07:34:38.00#ibcon#about to read 6, iclass 39, count 2 2006.246.07:34:38.00#ibcon#read 6, iclass 39, count 2 2006.246.07:34:38.00#ibcon#end of sib2, iclass 39, count 2 2006.246.07:34:38.00#ibcon#*mode == 0, iclass 39, count 2 2006.246.07:34:38.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.07:34:38.00#ibcon#[25=AT01-08\r\n] 2006.246.07:34:38.00#ibcon#*before write, iclass 39, count 2 2006.246.07:34:38.00#ibcon#enter sib2, iclass 39, count 2 2006.246.07:34:38.00#ibcon#flushed, iclass 39, count 2 2006.246.07:34:38.00#ibcon#about to write, iclass 39, count 2 2006.246.07:34:38.00#ibcon#wrote, iclass 39, count 2 2006.246.07:34:38.00#ibcon#about to read 3, iclass 39, count 2 2006.246.07:34:38.03#ibcon#read 3, iclass 39, count 2 2006.246.07:34:38.03#ibcon#about to read 4, iclass 39, count 2 2006.246.07:34:38.03#ibcon#read 4, iclass 39, count 2 2006.246.07:34:38.03#ibcon#about to read 5, iclass 39, count 2 2006.246.07:34:38.03#ibcon#read 5, iclass 39, count 2 2006.246.07:34:38.03#ibcon#about to read 6, iclass 39, count 2 2006.246.07:34:38.03#ibcon#read 6, iclass 39, count 2 2006.246.07:34:38.03#ibcon#end of sib2, iclass 39, count 2 2006.246.07:34:38.03#ibcon#*after write, iclass 39, count 2 2006.246.07:34:38.03#ibcon#*before return 0, iclass 39, count 2 2006.246.07:34:38.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:38.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:38.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.07:34:38.03#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:38.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:38.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:38.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:38.15#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:34:38.15#ibcon#first serial, iclass 39, count 0 2006.246.07:34:38.15#ibcon#enter sib2, iclass 39, count 0 2006.246.07:34:38.15#ibcon#flushed, iclass 39, count 0 2006.246.07:34:38.15#ibcon#about to write, iclass 39, count 0 2006.246.07:34:38.15#ibcon#wrote, iclass 39, count 0 2006.246.07:34:38.15#ibcon#about to read 3, iclass 39, count 0 2006.246.07:34:38.17#ibcon#read 3, iclass 39, count 0 2006.246.07:34:38.17#ibcon#about to read 4, iclass 39, count 0 2006.246.07:34:38.17#ibcon#read 4, iclass 39, count 0 2006.246.07:34:38.17#ibcon#about to read 5, iclass 39, count 0 2006.246.07:34:38.17#ibcon#read 5, iclass 39, count 0 2006.246.07:34:38.17#ibcon#about to read 6, iclass 39, count 0 2006.246.07:34:38.17#ibcon#read 6, iclass 39, count 0 2006.246.07:34:38.17#ibcon#end of sib2, iclass 39, count 0 2006.246.07:34:38.17#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:34:38.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:34:38.17#ibcon#[25=USB\r\n] 2006.246.07:34:38.17#ibcon#*before write, iclass 39, count 0 2006.246.07:34:38.17#ibcon#enter sib2, iclass 39, count 0 2006.246.07:34:38.17#ibcon#flushed, iclass 39, count 0 2006.246.07:34:38.17#ibcon#about to write, iclass 39, count 0 2006.246.07:34:38.17#ibcon#wrote, iclass 39, count 0 2006.246.07:34:38.17#ibcon#about to read 3, iclass 39, count 0 2006.246.07:34:38.20#ibcon#read 3, iclass 39, count 0 2006.246.07:34:38.20#ibcon#about to read 4, iclass 39, count 0 2006.246.07:34:38.20#ibcon#read 4, iclass 39, count 0 2006.246.07:34:38.20#ibcon#about to read 5, iclass 39, count 0 2006.246.07:34:38.20#ibcon#read 5, iclass 39, count 0 2006.246.07:34:38.20#ibcon#about to read 6, iclass 39, count 0 2006.246.07:34:38.20#ibcon#read 6, iclass 39, count 0 2006.246.07:34:38.20#ibcon#end of sib2, iclass 39, count 0 2006.246.07:34:38.20#ibcon#*after write, iclass 39, count 0 2006.246.07:34:38.20#ibcon#*before return 0, iclass 39, count 0 2006.246.07:34:38.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:38.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:38.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:34:38.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:34:38.20$vc4f8/valo=2,572.99 2006.246.07:34:38.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.07:34:38.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.07:34:38.20#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:38.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:38.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:38.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:38.20#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:34:38.20#ibcon#first serial, iclass 3, count 0 2006.246.07:34:38.20#ibcon#enter sib2, iclass 3, count 0 2006.246.07:34:38.20#ibcon#flushed, iclass 3, count 0 2006.246.07:34:38.20#ibcon#about to write, iclass 3, count 0 2006.246.07:34:38.20#ibcon#wrote, iclass 3, count 0 2006.246.07:34:38.20#ibcon#about to read 3, iclass 3, count 0 2006.246.07:34:38.22#ibcon#read 3, iclass 3, count 0 2006.246.07:34:38.22#ibcon#about to read 4, iclass 3, count 0 2006.246.07:34:38.22#ibcon#read 4, iclass 3, count 0 2006.246.07:34:38.22#ibcon#about to read 5, iclass 3, count 0 2006.246.07:34:38.22#ibcon#read 5, iclass 3, count 0 2006.246.07:34:38.22#ibcon#about to read 6, iclass 3, count 0 2006.246.07:34:38.22#ibcon#read 6, iclass 3, count 0 2006.246.07:34:38.22#ibcon#end of sib2, iclass 3, count 0 2006.246.07:34:38.22#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:34:38.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:34:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:34:38.22#ibcon#*before write, iclass 3, count 0 2006.246.07:34:38.22#ibcon#enter sib2, iclass 3, count 0 2006.246.07:34:38.22#ibcon#flushed, iclass 3, count 0 2006.246.07:34:38.22#ibcon#about to write, iclass 3, count 0 2006.246.07:34:38.22#ibcon#wrote, iclass 3, count 0 2006.246.07:34:38.22#ibcon#about to read 3, iclass 3, count 0 2006.246.07:34:38.26#ibcon#read 3, iclass 3, count 0 2006.246.07:34:38.26#ibcon#about to read 4, iclass 3, count 0 2006.246.07:34:38.26#ibcon#read 4, iclass 3, count 0 2006.246.07:34:38.26#ibcon#about to read 5, iclass 3, count 0 2006.246.07:34:38.26#ibcon#read 5, iclass 3, count 0 2006.246.07:34:38.26#ibcon#about to read 6, iclass 3, count 0 2006.246.07:34:38.26#ibcon#read 6, iclass 3, count 0 2006.246.07:34:38.26#ibcon#end of sib2, iclass 3, count 0 2006.246.07:34:38.26#ibcon#*after write, iclass 3, count 0 2006.246.07:34:38.26#ibcon#*before return 0, iclass 3, count 0 2006.246.07:34:38.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:38.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:38.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:34:38.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:34:38.26$vc4f8/va=2,7 2006.246.07:34:38.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.07:34:38.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.07:34:38.26#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:38.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:38.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:38.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:38.32#ibcon#enter wrdev, iclass 5, count 2 2006.246.07:34:38.32#ibcon#first serial, iclass 5, count 2 2006.246.07:34:38.32#ibcon#enter sib2, iclass 5, count 2 2006.246.07:34:38.32#ibcon#flushed, iclass 5, count 2 2006.246.07:34:38.32#ibcon#about to write, iclass 5, count 2 2006.246.07:34:38.32#ibcon#wrote, iclass 5, count 2 2006.246.07:34:38.32#ibcon#about to read 3, iclass 5, count 2 2006.246.07:34:38.34#ibcon#read 3, iclass 5, count 2 2006.246.07:34:38.34#ibcon#about to read 4, iclass 5, count 2 2006.246.07:34:38.34#ibcon#read 4, iclass 5, count 2 2006.246.07:34:38.34#ibcon#about to read 5, iclass 5, count 2 2006.246.07:34:38.34#ibcon#read 5, iclass 5, count 2 2006.246.07:34:38.34#ibcon#about to read 6, iclass 5, count 2 2006.246.07:34:38.34#ibcon#read 6, iclass 5, count 2 2006.246.07:34:38.34#ibcon#end of sib2, iclass 5, count 2 2006.246.07:34:38.34#ibcon#*mode == 0, iclass 5, count 2 2006.246.07:34:38.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.07:34:38.34#ibcon#[25=AT02-07\r\n] 2006.246.07:34:38.34#ibcon#*before write, iclass 5, count 2 2006.246.07:34:38.34#ibcon#enter sib2, iclass 5, count 2 2006.246.07:34:38.34#ibcon#flushed, iclass 5, count 2 2006.246.07:34:38.34#ibcon#about to write, iclass 5, count 2 2006.246.07:34:38.34#ibcon#wrote, iclass 5, count 2 2006.246.07:34:38.34#ibcon#about to read 3, iclass 5, count 2 2006.246.07:34:38.37#ibcon#read 3, iclass 5, count 2 2006.246.07:34:38.37#ibcon#about to read 4, iclass 5, count 2 2006.246.07:34:38.37#ibcon#read 4, iclass 5, count 2 2006.246.07:34:38.37#ibcon#about to read 5, iclass 5, count 2 2006.246.07:34:38.37#ibcon#read 5, iclass 5, count 2 2006.246.07:34:38.37#ibcon#about to read 6, iclass 5, count 2 2006.246.07:34:38.37#ibcon#read 6, iclass 5, count 2 2006.246.07:34:38.37#ibcon#end of sib2, iclass 5, count 2 2006.246.07:34:38.37#ibcon#*after write, iclass 5, count 2 2006.246.07:34:38.37#ibcon#*before return 0, iclass 5, count 2 2006.246.07:34:38.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:38.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:38.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.07:34:38.37#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:38.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:38.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:38.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:38.49#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:34:38.49#ibcon#first serial, iclass 5, count 0 2006.246.07:34:38.49#ibcon#enter sib2, iclass 5, count 0 2006.246.07:34:38.49#ibcon#flushed, iclass 5, count 0 2006.246.07:34:38.49#ibcon#about to write, iclass 5, count 0 2006.246.07:34:38.49#ibcon#wrote, iclass 5, count 0 2006.246.07:34:38.49#ibcon#about to read 3, iclass 5, count 0 2006.246.07:34:38.51#ibcon#read 3, iclass 5, count 0 2006.246.07:34:38.51#ibcon#about to read 4, iclass 5, count 0 2006.246.07:34:38.51#ibcon#read 4, iclass 5, count 0 2006.246.07:34:38.51#ibcon#about to read 5, iclass 5, count 0 2006.246.07:34:38.51#ibcon#read 5, iclass 5, count 0 2006.246.07:34:38.51#ibcon#about to read 6, iclass 5, count 0 2006.246.07:34:38.51#ibcon#read 6, iclass 5, count 0 2006.246.07:34:38.51#ibcon#end of sib2, iclass 5, count 0 2006.246.07:34:38.51#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:34:38.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:34:38.51#ibcon#[25=USB\r\n] 2006.246.07:34:38.51#ibcon#*before write, iclass 5, count 0 2006.246.07:34:38.51#ibcon#enter sib2, iclass 5, count 0 2006.246.07:34:38.51#ibcon#flushed, iclass 5, count 0 2006.246.07:34:38.51#ibcon#about to write, iclass 5, count 0 2006.246.07:34:38.51#ibcon#wrote, iclass 5, count 0 2006.246.07:34:38.51#ibcon#about to read 3, iclass 5, count 0 2006.246.07:34:38.54#ibcon#read 3, iclass 5, count 0 2006.246.07:34:38.54#ibcon#about to read 4, iclass 5, count 0 2006.246.07:34:38.54#ibcon#read 4, iclass 5, count 0 2006.246.07:34:38.54#ibcon#about to read 5, iclass 5, count 0 2006.246.07:34:38.54#ibcon#read 5, iclass 5, count 0 2006.246.07:34:38.54#ibcon#about to read 6, iclass 5, count 0 2006.246.07:34:38.54#ibcon#read 6, iclass 5, count 0 2006.246.07:34:38.54#ibcon#end of sib2, iclass 5, count 0 2006.246.07:34:38.54#ibcon#*after write, iclass 5, count 0 2006.246.07:34:38.54#ibcon#*before return 0, iclass 5, count 0 2006.246.07:34:38.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:38.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:38.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:34:38.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:34:38.54$vc4f8/valo=3,672.99 2006.246.07:34:38.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.07:34:38.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.07:34:38.54#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:38.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:38.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:38.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:38.54#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:34:38.54#ibcon#first serial, iclass 7, count 0 2006.246.07:34:38.54#ibcon#enter sib2, iclass 7, count 0 2006.246.07:34:38.54#ibcon#flushed, iclass 7, count 0 2006.246.07:34:38.54#ibcon#about to write, iclass 7, count 0 2006.246.07:34:38.54#ibcon#wrote, iclass 7, count 0 2006.246.07:34:38.54#ibcon#about to read 3, iclass 7, count 0 2006.246.07:34:38.56#ibcon#read 3, iclass 7, count 0 2006.246.07:34:38.56#ibcon#about to read 4, iclass 7, count 0 2006.246.07:34:38.56#ibcon#read 4, iclass 7, count 0 2006.246.07:34:38.56#ibcon#about to read 5, iclass 7, count 0 2006.246.07:34:38.56#ibcon#read 5, iclass 7, count 0 2006.246.07:34:38.56#ibcon#about to read 6, iclass 7, count 0 2006.246.07:34:38.56#ibcon#read 6, iclass 7, count 0 2006.246.07:34:38.56#ibcon#end of sib2, iclass 7, count 0 2006.246.07:34:38.56#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:34:38.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:34:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:34:38.56#ibcon#*before write, iclass 7, count 0 2006.246.07:34:38.56#ibcon#enter sib2, iclass 7, count 0 2006.246.07:34:38.56#ibcon#flushed, iclass 7, count 0 2006.246.07:34:38.56#ibcon#about to write, iclass 7, count 0 2006.246.07:34:38.56#ibcon#wrote, iclass 7, count 0 2006.246.07:34:38.56#ibcon#about to read 3, iclass 7, count 0 2006.246.07:34:38.60#ibcon#read 3, iclass 7, count 0 2006.246.07:34:38.60#ibcon#about to read 4, iclass 7, count 0 2006.246.07:34:38.60#ibcon#read 4, iclass 7, count 0 2006.246.07:34:38.60#ibcon#about to read 5, iclass 7, count 0 2006.246.07:34:38.60#ibcon#read 5, iclass 7, count 0 2006.246.07:34:38.60#ibcon#about to read 6, iclass 7, count 0 2006.246.07:34:38.60#ibcon#read 6, iclass 7, count 0 2006.246.07:34:38.60#ibcon#end of sib2, iclass 7, count 0 2006.246.07:34:38.60#ibcon#*after write, iclass 7, count 0 2006.246.07:34:38.60#ibcon#*before return 0, iclass 7, count 0 2006.246.07:34:38.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:38.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:38.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:34:38.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:34:38.60$vc4f8/va=3,6 2006.246.07:34:38.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.07:34:38.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.07:34:38.60#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:38.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:38.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:38.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:38.66#ibcon#enter wrdev, iclass 11, count 2 2006.246.07:34:38.66#ibcon#first serial, iclass 11, count 2 2006.246.07:34:38.66#ibcon#enter sib2, iclass 11, count 2 2006.246.07:34:38.66#ibcon#flushed, iclass 11, count 2 2006.246.07:34:38.66#ibcon#about to write, iclass 11, count 2 2006.246.07:34:38.66#ibcon#wrote, iclass 11, count 2 2006.246.07:34:38.66#ibcon#about to read 3, iclass 11, count 2 2006.246.07:34:38.68#ibcon#read 3, iclass 11, count 2 2006.246.07:34:38.68#ibcon#about to read 4, iclass 11, count 2 2006.246.07:34:38.68#ibcon#read 4, iclass 11, count 2 2006.246.07:34:38.68#ibcon#about to read 5, iclass 11, count 2 2006.246.07:34:38.68#ibcon#read 5, iclass 11, count 2 2006.246.07:34:38.68#ibcon#about to read 6, iclass 11, count 2 2006.246.07:34:38.68#ibcon#read 6, iclass 11, count 2 2006.246.07:34:38.68#ibcon#end of sib2, iclass 11, count 2 2006.246.07:34:38.68#ibcon#*mode == 0, iclass 11, count 2 2006.246.07:34:38.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.07:34:38.68#ibcon#[25=AT03-06\r\n] 2006.246.07:34:38.68#ibcon#*before write, iclass 11, count 2 2006.246.07:34:38.68#ibcon#enter sib2, iclass 11, count 2 2006.246.07:34:38.68#ibcon#flushed, iclass 11, count 2 2006.246.07:34:38.68#ibcon#about to write, iclass 11, count 2 2006.246.07:34:38.68#ibcon#wrote, iclass 11, count 2 2006.246.07:34:38.68#ibcon#about to read 3, iclass 11, count 2 2006.246.07:34:38.71#ibcon#read 3, iclass 11, count 2 2006.246.07:34:38.71#ibcon#about to read 4, iclass 11, count 2 2006.246.07:34:38.71#ibcon#read 4, iclass 11, count 2 2006.246.07:34:38.71#ibcon#about to read 5, iclass 11, count 2 2006.246.07:34:38.71#ibcon#read 5, iclass 11, count 2 2006.246.07:34:38.71#ibcon#about to read 6, iclass 11, count 2 2006.246.07:34:38.71#ibcon#read 6, iclass 11, count 2 2006.246.07:34:38.71#ibcon#end of sib2, iclass 11, count 2 2006.246.07:34:38.71#ibcon#*after write, iclass 11, count 2 2006.246.07:34:38.71#ibcon#*before return 0, iclass 11, count 2 2006.246.07:34:38.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:38.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:38.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.07:34:38.71#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:38.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:38.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:38.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:38.83#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:34:38.83#ibcon#first serial, iclass 11, count 0 2006.246.07:34:38.83#ibcon#enter sib2, iclass 11, count 0 2006.246.07:34:38.83#ibcon#flushed, iclass 11, count 0 2006.246.07:34:38.83#ibcon#about to write, iclass 11, count 0 2006.246.07:34:38.83#ibcon#wrote, iclass 11, count 0 2006.246.07:34:38.83#ibcon#about to read 3, iclass 11, count 0 2006.246.07:34:38.85#ibcon#read 3, iclass 11, count 0 2006.246.07:34:38.85#ibcon#about to read 4, iclass 11, count 0 2006.246.07:34:38.85#ibcon#read 4, iclass 11, count 0 2006.246.07:34:38.85#ibcon#about to read 5, iclass 11, count 0 2006.246.07:34:38.85#ibcon#read 5, iclass 11, count 0 2006.246.07:34:38.85#ibcon#about to read 6, iclass 11, count 0 2006.246.07:34:38.85#ibcon#read 6, iclass 11, count 0 2006.246.07:34:38.85#ibcon#end of sib2, iclass 11, count 0 2006.246.07:34:38.85#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:34:38.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:34:38.85#ibcon#[25=USB\r\n] 2006.246.07:34:38.85#ibcon#*before write, iclass 11, count 0 2006.246.07:34:38.85#ibcon#enter sib2, iclass 11, count 0 2006.246.07:34:38.85#ibcon#flushed, iclass 11, count 0 2006.246.07:34:38.85#ibcon#about to write, iclass 11, count 0 2006.246.07:34:38.85#ibcon#wrote, iclass 11, count 0 2006.246.07:34:38.85#ibcon#about to read 3, iclass 11, count 0 2006.246.07:34:38.88#ibcon#read 3, iclass 11, count 0 2006.246.07:34:38.88#ibcon#about to read 4, iclass 11, count 0 2006.246.07:34:38.88#ibcon#read 4, iclass 11, count 0 2006.246.07:34:38.88#ibcon#about to read 5, iclass 11, count 0 2006.246.07:34:38.88#ibcon#read 5, iclass 11, count 0 2006.246.07:34:38.88#ibcon#about to read 6, iclass 11, count 0 2006.246.07:34:38.88#ibcon#read 6, iclass 11, count 0 2006.246.07:34:38.88#ibcon#end of sib2, iclass 11, count 0 2006.246.07:34:38.88#ibcon#*after write, iclass 11, count 0 2006.246.07:34:38.88#ibcon#*before return 0, iclass 11, count 0 2006.246.07:34:38.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:38.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:38.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:34:38.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:34:38.88$vc4f8/valo=4,832.99 2006.246.07:34:38.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.07:34:38.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.07:34:38.88#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:38.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:38.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:38.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:38.88#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:34:38.88#ibcon#first serial, iclass 13, count 0 2006.246.07:34:38.88#ibcon#enter sib2, iclass 13, count 0 2006.246.07:34:38.88#ibcon#flushed, iclass 13, count 0 2006.246.07:34:38.88#ibcon#about to write, iclass 13, count 0 2006.246.07:34:38.88#ibcon#wrote, iclass 13, count 0 2006.246.07:34:38.88#ibcon#about to read 3, iclass 13, count 0 2006.246.07:34:38.90#ibcon#read 3, iclass 13, count 0 2006.246.07:34:38.90#ibcon#about to read 4, iclass 13, count 0 2006.246.07:34:38.90#ibcon#read 4, iclass 13, count 0 2006.246.07:34:38.90#ibcon#about to read 5, iclass 13, count 0 2006.246.07:34:38.90#ibcon#read 5, iclass 13, count 0 2006.246.07:34:38.90#ibcon#about to read 6, iclass 13, count 0 2006.246.07:34:38.90#ibcon#read 6, iclass 13, count 0 2006.246.07:34:38.90#ibcon#end of sib2, iclass 13, count 0 2006.246.07:34:38.90#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:34:38.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:34:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:34:38.90#ibcon#*before write, iclass 13, count 0 2006.246.07:34:38.90#ibcon#enter sib2, iclass 13, count 0 2006.246.07:34:38.90#ibcon#flushed, iclass 13, count 0 2006.246.07:34:38.90#ibcon#about to write, iclass 13, count 0 2006.246.07:34:38.90#ibcon#wrote, iclass 13, count 0 2006.246.07:34:38.90#ibcon#about to read 3, iclass 13, count 0 2006.246.07:34:38.94#ibcon#read 3, iclass 13, count 0 2006.246.07:34:38.94#ibcon#about to read 4, iclass 13, count 0 2006.246.07:34:38.94#ibcon#read 4, iclass 13, count 0 2006.246.07:34:38.94#ibcon#about to read 5, iclass 13, count 0 2006.246.07:34:38.94#ibcon#read 5, iclass 13, count 0 2006.246.07:34:38.94#ibcon#about to read 6, iclass 13, count 0 2006.246.07:34:38.94#ibcon#read 6, iclass 13, count 0 2006.246.07:34:38.94#ibcon#end of sib2, iclass 13, count 0 2006.246.07:34:38.94#ibcon#*after write, iclass 13, count 0 2006.246.07:34:38.94#ibcon#*before return 0, iclass 13, count 0 2006.246.07:34:38.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:38.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:38.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:34:38.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:34:38.94$vc4f8/va=4,7 2006.246.07:34:38.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.07:34:38.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.07:34:38.94#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:38.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:39.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:39.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:39.00#ibcon#enter wrdev, iclass 15, count 2 2006.246.07:34:39.00#ibcon#first serial, iclass 15, count 2 2006.246.07:34:39.00#ibcon#enter sib2, iclass 15, count 2 2006.246.07:34:39.00#ibcon#flushed, iclass 15, count 2 2006.246.07:34:39.00#ibcon#about to write, iclass 15, count 2 2006.246.07:34:39.00#ibcon#wrote, iclass 15, count 2 2006.246.07:34:39.00#ibcon#about to read 3, iclass 15, count 2 2006.246.07:34:39.02#ibcon#read 3, iclass 15, count 2 2006.246.07:34:39.02#ibcon#about to read 4, iclass 15, count 2 2006.246.07:34:39.02#ibcon#read 4, iclass 15, count 2 2006.246.07:34:39.02#ibcon#about to read 5, iclass 15, count 2 2006.246.07:34:39.02#ibcon#read 5, iclass 15, count 2 2006.246.07:34:39.02#ibcon#about to read 6, iclass 15, count 2 2006.246.07:34:39.02#ibcon#read 6, iclass 15, count 2 2006.246.07:34:39.02#ibcon#end of sib2, iclass 15, count 2 2006.246.07:34:39.02#ibcon#*mode == 0, iclass 15, count 2 2006.246.07:34:39.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.07:34:39.02#ibcon#[25=AT04-07\r\n] 2006.246.07:34:39.02#ibcon#*before write, iclass 15, count 2 2006.246.07:34:39.02#ibcon#enter sib2, iclass 15, count 2 2006.246.07:34:39.02#ibcon#flushed, iclass 15, count 2 2006.246.07:34:39.02#ibcon#about to write, iclass 15, count 2 2006.246.07:34:39.02#ibcon#wrote, iclass 15, count 2 2006.246.07:34:39.02#ibcon#about to read 3, iclass 15, count 2 2006.246.07:34:39.05#ibcon#read 3, iclass 15, count 2 2006.246.07:34:39.05#ibcon#about to read 4, iclass 15, count 2 2006.246.07:34:39.05#ibcon#read 4, iclass 15, count 2 2006.246.07:34:39.05#ibcon#about to read 5, iclass 15, count 2 2006.246.07:34:39.05#ibcon#read 5, iclass 15, count 2 2006.246.07:34:39.05#ibcon#about to read 6, iclass 15, count 2 2006.246.07:34:39.05#ibcon#read 6, iclass 15, count 2 2006.246.07:34:39.05#ibcon#end of sib2, iclass 15, count 2 2006.246.07:34:39.05#ibcon#*after write, iclass 15, count 2 2006.246.07:34:39.05#ibcon#*before return 0, iclass 15, count 2 2006.246.07:34:39.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:39.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:39.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.07:34:39.05#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:39.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:39.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:39.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:39.17#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:34:39.17#ibcon#first serial, iclass 15, count 0 2006.246.07:34:39.17#ibcon#enter sib2, iclass 15, count 0 2006.246.07:34:39.17#ibcon#flushed, iclass 15, count 0 2006.246.07:34:39.17#ibcon#about to write, iclass 15, count 0 2006.246.07:34:39.17#ibcon#wrote, iclass 15, count 0 2006.246.07:34:39.17#ibcon#about to read 3, iclass 15, count 0 2006.246.07:34:39.19#ibcon#read 3, iclass 15, count 0 2006.246.07:34:39.19#ibcon#about to read 4, iclass 15, count 0 2006.246.07:34:39.19#ibcon#read 4, iclass 15, count 0 2006.246.07:34:39.19#ibcon#about to read 5, iclass 15, count 0 2006.246.07:34:39.19#ibcon#read 5, iclass 15, count 0 2006.246.07:34:39.19#ibcon#about to read 6, iclass 15, count 0 2006.246.07:34:39.19#ibcon#read 6, iclass 15, count 0 2006.246.07:34:39.19#ibcon#end of sib2, iclass 15, count 0 2006.246.07:34:39.19#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:34:39.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:34:39.19#ibcon#[25=USB\r\n] 2006.246.07:34:39.19#ibcon#*before write, iclass 15, count 0 2006.246.07:34:39.19#ibcon#enter sib2, iclass 15, count 0 2006.246.07:34:39.19#ibcon#flushed, iclass 15, count 0 2006.246.07:34:39.19#ibcon#about to write, iclass 15, count 0 2006.246.07:34:39.19#ibcon#wrote, iclass 15, count 0 2006.246.07:34:39.19#ibcon#about to read 3, iclass 15, count 0 2006.246.07:34:39.22#ibcon#read 3, iclass 15, count 0 2006.246.07:34:39.22#ibcon#about to read 4, iclass 15, count 0 2006.246.07:34:39.22#ibcon#read 4, iclass 15, count 0 2006.246.07:34:39.22#ibcon#about to read 5, iclass 15, count 0 2006.246.07:34:39.22#ibcon#read 5, iclass 15, count 0 2006.246.07:34:39.22#ibcon#about to read 6, iclass 15, count 0 2006.246.07:34:39.22#ibcon#read 6, iclass 15, count 0 2006.246.07:34:39.22#ibcon#end of sib2, iclass 15, count 0 2006.246.07:34:39.22#ibcon#*after write, iclass 15, count 0 2006.246.07:34:39.22#ibcon#*before return 0, iclass 15, count 0 2006.246.07:34:39.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:39.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:39.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:34:39.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:34:39.22$vc4f8/valo=5,652.99 2006.246.07:34:39.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:34:39.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:34:39.22#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:39.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:39.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:39.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:39.22#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:34:39.22#ibcon#first serial, iclass 17, count 0 2006.246.07:34:39.22#ibcon#enter sib2, iclass 17, count 0 2006.246.07:34:39.22#ibcon#flushed, iclass 17, count 0 2006.246.07:34:39.22#ibcon#about to write, iclass 17, count 0 2006.246.07:34:39.22#ibcon#wrote, iclass 17, count 0 2006.246.07:34:39.22#ibcon#about to read 3, iclass 17, count 0 2006.246.07:34:39.24#ibcon#read 3, iclass 17, count 0 2006.246.07:34:39.24#ibcon#about to read 4, iclass 17, count 0 2006.246.07:34:39.24#ibcon#read 4, iclass 17, count 0 2006.246.07:34:39.24#ibcon#about to read 5, iclass 17, count 0 2006.246.07:34:39.24#ibcon#read 5, iclass 17, count 0 2006.246.07:34:39.24#ibcon#about to read 6, iclass 17, count 0 2006.246.07:34:39.24#ibcon#read 6, iclass 17, count 0 2006.246.07:34:39.24#ibcon#end of sib2, iclass 17, count 0 2006.246.07:34:39.24#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:34:39.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:34:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:34:39.24#ibcon#*before write, iclass 17, count 0 2006.246.07:34:39.24#ibcon#enter sib2, iclass 17, count 0 2006.246.07:34:39.24#ibcon#flushed, iclass 17, count 0 2006.246.07:34:39.24#ibcon#about to write, iclass 17, count 0 2006.246.07:34:39.24#ibcon#wrote, iclass 17, count 0 2006.246.07:34:39.24#ibcon#about to read 3, iclass 17, count 0 2006.246.07:34:39.28#ibcon#read 3, iclass 17, count 0 2006.246.07:34:39.28#ibcon#about to read 4, iclass 17, count 0 2006.246.07:34:39.28#ibcon#read 4, iclass 17, count 0 2006.246.07:34:39.28#ibcon#about to read 5, iclass 17, count 0 2006.246.07:34:39.28#ibcon#read 5, iclass 17, count 0 2006.246.07:34:39.28#ibcon#about to read 6, iclass 17, count 0 2006.246.07:34:39.28#ibcon#read 6, iclass 17, count 0 2006.246.07:34:39.28#ibcon#end of sib2, iclass 17, count 0 2006.246.07:34:39.28#ibcon#*after write, iclass 17, count 0 2006.246.07:34:39.28#ibcon#*before return 0, iclass 17, count 0 2006.246.07:34:39.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:39.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:39.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:34:39.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:34:39.28$vc4f8/va=5,7 2006.246.07:34:39.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.07:34:39.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.07:34:39.28#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:39.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:39.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:39.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:39.34#ibcon#enter wrdev, iclass 19, count 2 2006.246.07:34:39.34#ibcon#first serial, iclass 19, count 2 2006.246.07:34:39.34#ibcon#enter sib2, iclass 19, count 2 2006.246.07:34:39.34#ibcon#flushed, iclass 19, count 2 2006.246.07:34:39.34#ibcon#about to write, iclass 19, count 2 2006.246.07:34:39.34#ibcon#wrote, iclass 19, count 2 2006.246.07:34:39.34#ibcon#about to read 3, iclass 19, count 2 2006.246.07:34:39.36#ibcon#read 3, iclass 19, count 2 2006.246.07:34:39.36#ibcon#about to read 4, iclass 19, count 2 2006.246.07:34:39.36#ibcon#read 4, iclass 19, count 2 2006.246.07:34:39.36#ibcon#about to read 5, iclass 19, count 2 2006.246.07:34:39.36#ibcon#read 5, iclass 19, count 2 2006.246.07:34:39.36#ibcon#about to read 6, iclass 19, count 2 2006.246.07:34:39.36#ibcon#read 6, iclass 19, count 2 2006.246.07:34:39.36#ibcon#end of sib2, iclass 19, count 2 2006.246.07:34:39.36#ibcon#*mode == 0, iclass 19, count 2 2006.246.07:34:39.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.07:34:39.36#ibcon#[25=AT05-07\r\n] 2006.246.07:34:39.36#ibcon#*before write, iclass 19, count 2 2006.246.07:34:39.36#ibcon#enter sib2, iclass 19, count 2 2006.246.07:34:39.36#ibcon#flushed, iclass 19, count 2 2006.246.07:34:39.36#ibcon#about to write, iclass 19, count 2 2006.246.07:34:39.36#ibcon#wrote, iclass 19, count 2 2006.246.07:34:39.36#ibcon#about to read 3, iclass 19, count 2 2006.246.07:34:39.39#ibcon#read 3, iclass 19, count 2 2006.246.07:34:39.39#ibcon#about to read 4, iclass 19, count 2 2006.246.07:34:39.39#ibcon#read 4, iclass 19, count 2 2006.246.07:34:39.39#ibcon#about to read 5, iclass 19, count 2 2006.246.07:34:39.39#ibcon#read 5, iclass 19, count 2 2006.246.07:34:39.39#ibcon#about to read 6, iclass 19, count 2 2006.246.07:34:39.39#ibcon#read 6, iclass 19, count 2 2006.246.07:34:39.39#ibcon#end of sib2, iclass 19, count 2 2006.246.07:34:39.39#ibcon#*after write, iclass 19, count 2 2006.246.07:34:39.39#ibcon#*before return 0, iclass 19, count 2 2006.246.07:34:39.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:39.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:39.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.07:34:39.39#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:39.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:39.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:39.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:39.51#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:34:39.51#ibcon#first serial, iclass 19, count 0 2006.246.07:34:39.51#ibcon#enter sib2, iclass 19, count 0 2006.246.07:34:39.51#ibcon#flushed, iclass 19, count 0 2006.246.07:34:39.51#ibcon#about to write, iclass 19, count 0 2006.246.07:34:39.51#ibcon#wrote, iclass 19, count 0 2006.246.07:34:39.51#ibcon#about to read 3, iclass 19, count 0 2006.246.07:34:39.53#ibcon#read 3, iclass 19, count 0 2006.246.07:34:39.53#ibcon#about to read 4, iclass 19, count 0 2006.246.07:34:39.53#ibcon#read 4, iclass 19, count 0 2006.246.07:34:39.53#ibcon#about to read 5, iclass 19, count 0 2006.246.07:34:39.53#ibcon#read 5, iclass 19, count 0 2006.246.07:34:39.53#ibcon#about to read 6, iclass 19, count 0 2006.246.07:34:39.53#ibcon#read 6, iclass 19, count 0 2006.246.07:34:39.53#ibcon#end of sib2, iclass 19, count 0 2006.246.07:34:39.53#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:34:39.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:34:39.53#ibcon#[25=USB\r\n] 2006.246.07:34:39.53#ibcon#*before write, iclass 19, count 0 2006.246.07:34:39.53#ibcon#enter sib2, iclass 19, count 0 2006.246.07:34:39.53#ibcon#flushed, iclass 19, count 0 2006.246.07:34:39.53#ibcon#about to write, iclass 19, count 0 2006.246.07:34:39.53#ibcon#wrote, iclass 19, count 0 2006.246.07:34:39.53#ibcon#about to read 3, iclass 19, count 0 2006.246.07:34:39.56#ibcon#read 3, iclass 19, count 0 2006.246.07:34:39.56#ibcon#about to read 4, iclass 19, count 0 2006.246.07:34:39.56#ibcon#read 4, iclass 19, count 0 2006.246.07:34:39.56#ibcon#about to read 5, iclass 19, count 0 2006.246.07:34:39.56#ibcon#read 5, iclass 19, count 0 2006.246.07:34:39.56#ibcon#about to read 6, iclass 19, count 0 2006.246.07:34:39.56#ibcon#read 6, iclass 19, count 0 2006.246.07:34:39.56#ibcon#end of sib2, iclass 19, count 0 2006.246.07:34:39.56#ibcon#*after write, iclass 19, count 0 2006.246.07:34:39.56#ibcon#*before return 0, iclass 19, count 0 2006.246.07:34:39.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:39.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:39.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:34:39.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:34:39.56$vc4f8/valo=6,772.99 2006.246.07:34:39.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.07:34:39.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.07:34:39.56#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:39.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:39.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:39.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:39.56#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:34:39.56#ibcon#first serial, iclass 21, count 0 2006.246.07:34:39.56#ibcon#enter sib2, iclass 21, count 0 2006.246.07:34:39.56#ibcon#flushed, iclass 21, count 0 2006.246.07:34:39.56#ibcon#about to write, iclass 21, count 0 2006.246.07:34:39.56#ibcon#wrote, iclass 21, count 0 2006.246.07:34:39.56#ibcon#about to read 3, iclass 21, count 0 2006.246.07:34:39.58#ibcon#read 3, iclass 21, count 0 2006.246.07:34:39.58#ibcon#about to read 4, iclass 21, count 0 2006.246.07:34:39.58#ibcon#read 4, iclass 21, count 0 2006.246.07:34:39.58#ibcon#about to read 5, iclass 21, count 0 2006.246.07:34:39.58#ibcon#read 5, iclass 21, count 0 2006.246.07:34:39.58#ibcon#about to read 6, iclass 21, count 0 2006.246.07:34:39.58#ibcon#read 6, iclass 21, count 0 2006.246.07:34:39.58#ibcon#end of sib2, iclass 21, count 0 2006.246.07:34:39.58#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:34:39.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:34:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:34:39.58#ibcon#*before write, iclass 21, count 0 2006.246.07:34:39.58#ibcon#enter sib2, iclass 21, count 0 2006.246.07:34:39.58#ibcon#flushed, iclass 21, count 0 2006.246.07:34:39.58#ibcon#about to write, iclass 21, count 0 2006.246.07:34:39.58#ibcon#wrote, iclass 21, count 0 2006.246.07:34:39.58#ibcon#about to read 3, iclass 21, count 0 2006.246.07:34:39.62#ibcon#read 3, iclass 21, count 0 2006.246.07:34:39.62#ibcon#about to read 4, iclass 21, count 0 2006.246.07:34:39.62#ibcon#read 4, iclass 21, count 0 2006.246.07:34:39.62#ibcon#about to read 5, iclass 21, count 0 2006.246.07:34:39.62#ibcon#read 5, iclass 21, count 0 2006.246.07:34:39.62#ibcon#about to read 6, iclass 21, count 0 2006.246.07:34:39.62#ibcon#read 6, iclass 21, count 0 2006.246.07:34:39.62#ibcon#end of sib2, iclass 21, count 0 2006.246.07:34:39.62#ibcon#*after write, iclass 21, count 0 2006.246.07:34:39.62#ibcon#*before return 0, iclass 21, count 0 2006.246.07:34:39.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:39.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:39.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:34:39.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:34:39.62$vc4f8/va=6,7 2006.246.07:34:39.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.07:34:39.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.07:34:39.62#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:39.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:34:39.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:34:39.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:34:39.68#ibcon#enter wrdev, iclass 23, count 2 2006.246.07:34:39.68#ibcon#first serial, iclass 23, count 2 2006.246.07:34:39.68#ibcon#enter sib2, iclass 23, count 2 2006.246.07:34:39.68#ibcon#flushed, iclass 23, count 2 2006.246.07:34:39.68#ibcon#about to write, iclass 23, count 2 2006.246.07:34:39.68#ibcon#wrote, iclass 23, count 2 2006.246.07:34:39.68#ibcon#about to read 3, iclass 23, count 2 2006.246.07:34:39.70#ibcon#read 3, iclass 23, count 2 2006.246.07:34:39.70#ibcon#about to read 4, iclass 23, count 2 2006.246.07:34:39.70#ibcon#read 4, iclass 23, count 2 2006.246.07:34:39.70#ibcon#about to read 5, iclass 23, count 2 2006.246.07:34:39.70#ibcon#read 5, iclass 23, count 2 2006.246.07:34:39.70#ibcon#about to read 6, iclass 23, count 2 2006.246.07:34:39.70#ibcon#read 6, iclass 23, count 2 2006.246.07:34:39.70#ibcon#end of sib2, iclass 23, count 2 2006.246.07:34:39.70#ibcon#*mode == 0, iclass 23, count 2 2006.246.07:34:39.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.07:34:39.70#ibcon#[25=AT06-07\r\n] 2006.246.07:34:39.70#ibcon#*before write, iclass 23, count 2 2006.246.07:34:39.70#ibcon#enter sib2, iclass 23, count 2 2006.246.07:34:39.70#ibcon#flushed, iclass 23, count 2 2006.246.07:34:39.70#ibcon#about to write, iclass 23, count 2 2006.246.07:34:39.70#ibcon#wrote, iclass 23, count 2 2006.246.07:34:39.70#ibcon#about to read 3, iclass 23, count 2 2006.246.07:34:39.73#ibcon#read 3, iclass 23, count 2 2006.246.07:34:39.73#ibcon#about to read 4, iclass 23, count 2 2006.246.07:34:39.73#ibcon#read 4, iclass 23, count 2 2006.246.07:34:39.73#ibcon#about to read 5, iclass 23, count 2 2006.246.07:34:39.73#ibcon#read 5, iclass 23, count 2 2006.246.07:34:39.73#ibcon#about to read 6, iclass 23, count 2 2006.246.07:34:39.73#ibcon#read 6, iclass 23, count 2 2006.246.07:34:39.73#ibcon#end of sib2, iclass 23, count 2 2006.246.07:34:39.73#ibcon#*after write, iclass 23, count 2 2006.246.07:34:39.73#ibcon#*before return 0, iclass 23, count 2 2006.246.07:34:39.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:34:39.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:34:39.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.07:34:39.73#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:39.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:34:39.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:34:39.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:34:39.85#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:34:39.85#ibcon#first serial, iclass 23, count 0 2006.246.07:34:39.85#ibcon#enter sib2, iclass 23, count 0 2006.246.07:34:39.85#ibcon#flushed, iclass 23, count 0 2006.246.07:34:39.85#ibcon#about to write, iclass 23, count 0 2006.246.07:34:39.85#ibcon#wrote, iclass 23, count 0 2006.246.07:34:39.85#ibcon#about to read 3, iclass 23, count 0 2006.246.07:34:39.87#ibcon#read 3, iclass 23, count 0 2006.246.07:34:39.87#ibcon#about to read 4, iclass 23, count 0 2006.246.07:34:39.87#ibcon#read 4, iclass 23, count 0 2006.246.07:34:39.87#ibcon#about to read 5, iclass 23, count 0 2006.246.07:34:39.87#ibcon#read 5, iclass 23, count 0 2006.246.07:34:39.87#ibcon#about to read 6, iclass 23, count 0 2006.246.07:34:39.87#ibcon#read 6, iclass 23, count 0 2006.246.07:34:39.87#ibcon#end of sib2, iclass 23, count 0 2006.246.07:34:39.87#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:34:39.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:34:39.87#ibcon#[25=USB\r\n] 2006.246.07:34:39.87#ibcon#*before write, iclass 23, count 0 2006.246.07:34:39.87#ibcon#enter sib2, iclass 23, count 0 2006.246.07:34:39.87#ibcon#flushed, iclass 23, count 0 2006.246.07:34:39.87#ibcon#about to write, iclass 23, count 0 2006.246.07:34:39.87#ibcon#wrote, iclass 23, count 0 2006.246.07:34:39.87#ibcon#about to read 3, iclass 23, count 0 2006.246.07:34:39.90#ibcon#read 3, iclass 23, count 0 2006.246.07:34:39.90#ibcon#about to read 4, iclass 23, count 0 2006.246.07:34:39.90#ibcon#read 4, iclass 23, count 0 2006.246.07:34:39.90#ibcon#about to read 5, iclass 23, count 0 2006.246.07:34:39.90#ibcon#read 5, iclass 23, count 0 2006.246.07:34:39.90#ibcon#about to read 6, iclass 23, count 0 2006.246.07:34:39.90#ibcon#read 6, iclass 23, count 0 2006.246.07:34:39.90#ibcon#end of sib2, iclass 23, count 0 2006.246.07:34:39.90#ibcon#*after write, iclass 23, count 0 2006.246.07:34:39.90#ibcon#*before return 0, iclass 23, count 0 2006.246.07:34:39.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:34:39.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:34:39.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:34:39.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:34:39.90$vc4f8/valo=7,832.99 2006.246.07:34:39.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.07:34:39.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.07:34:39.90#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:39.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:34:39.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:34:39.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:34:39.90#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:34:39.90#ibcon#first serial, iclass 25, count 0 2006.246.07:34:39.90#ibcon#enter sib2, iclass 25, count 0 2006.246.07:34:39.90#ibcon#flushed, iclass 25, count 0 2006.246.07:34:39.90#ibcon#about to write, iclass 25, count 0 2006.246.07:34:39.90#ibcon#wrote, iclass 25, count 0 2006.246.07:34:39.90#ibcon#about to read 3, iclass 25, count 0 2006.246.07:34:39.92#ibcon#read 3, iclass 25, count 0 2006.246.07:34:39.92#ibcon#about to read 4, iclass 25, count 0 2006.246.07:34:39.92#ibcon#read 4, iclass 25, count 0 2006.246.07:34:39.92#ibcon#about to read 5, iclass 25, count 0 2006.246.07:34:39.92#ibcon#read 5, iclass 25, count 0 2006.246.07:34:39.92#ibcon#about to read 6, iclass 25, count 0 2006.246.07:34:39.92#ibcon#read 6, iclass 25, count 0 2006.246.07:34:39.92#ibcon#end of sib2, iclass 25, count 0 2006.246.07:34:39.92#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:34:39.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:34:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:34:39.92#ibcon#*before write, iclass 25, count 0 2006.246.07:34:39.92#ibcon#enter sib2, iclass 25, count 0 2006.246.07:34:39.92#ibcon#flushed, iclass 25, count 0 2006.246.07:34:39.92#ibcon#about to write, iclass 25, count 0 2006.246.07:34:39.92#ibcon#wrote, iclass 25, count 0 2006.246.07:34:39.92#ibcon#about to read 3, iclass 25, count 0 2006.246.07:34:39.96#ibcon#read 3, iclass 25, count 0 2006.246.07:34:39.96#ibcon#about to read 4, iclass 25, count 0 2006.246.07:34:39.96#ibcon#read 4, iclass 25, count 0 2006.246.07:34:39.96#ibcon#about to read 5, iclass 25, count 0 2006.246.07:34:39.96#ibcon#read 5, iclass 25, count 0 2006.246.07:34:39.96#ibcon#about to read 6, iclass 25, count 0 2006.246.07:34:39.96#ibcon#read 6, iclass 25, count 0 2006.246.07:34:39.96#ibcon#end of sib2, iclass 25, count 0 2006.246.07:34:39.96#ibcon#*after write, iclass 25, count 0 2006.246.07:34:39.96#ibcon#*before return 0, iclass 25, count 0 2006.246.07:34:39.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:34:39.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:34:39.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:34:39.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:34:39.96$vc4f8/va=7,7 2006.246.07:34:39.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.07:34:39.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.07:34:39.96#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:39.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:34:40.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:34:40.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:34:40.02#ibcon#enter wrdev, iclass 27, count 2 2006.246.07:34:40.02#ibcon#first serial, iclass 27, count 2 2006.246.07:34:40.02#ibcon#enter sib2, iclass 27, count 2 2006.246.07:34:40.02#ibcon#flushed, iclass 27, count 2 2006.246.07:34:40.02#ibcon#about to write, iclass 27, count 2 2006.246.07:34:40.02#ibcon#wrote, iclass 27, count 2 2006.246.07:34:40.02#ibcon#about to read 3, iclass 27, count 2 2006.246.07:34:40.04#ibcon#read 3, iclass 27, count 2 2006.246.07:34:40.04#ibcon#about to read 4, iclass 27, count 2 2006.246.07:34:40.04#ibcon#read 4, iclass 27, count 2 2006.246.07:34:40.04#ibcon#about to read 5, iclass 27, count 2 2006.246.07:34:40.04#ibcon#read 5, iclass 27, count 2 2006.246.07:34:40.04#ibcon#about to read 6, iclass 27, count 2 2006.246.07:34:40.04#ibcon#read 6, iclass 27, count 2 2006.246.07:34:40.04#ibcon#end of sib2, iclass 27, count 2 2006.246.07:34:40.04#ibcon#*mode == 0, iclass 27, count 2 2006.246.07:34:40.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.07:34:40.04#ibcon#[25=AT07-07\r\n] 2006.246.07:34:40.04#ibcon#*before write, iclass 27, count 2 2006.246.07:34:40.04#ibcon#enter sib2, iclass 27, count 2 2006.246.07:34:40.04#ibcon#flushed, iclass 27, count 2 2006.246.07:34:40.04#ibcon#about to write, iclass 27, count 2 2006.246.07:34:40.04#ibcon#wrote, iclass 27, count 2 2006.246.07:34:40.04#ibcon#about to read 3, iclass 27, count 2 2006.246.07:34:40.07#ibcon#read 3, iclass 27, count 2 2006.246.07:34:40.07#ibcon#about to read 4, iclass 27, count 2 2006.246.07:34:40.07#ibcon#read 4, iclass 27, count 2 2006.246.07:34:40.07#ibcon#about to read 5, iclass 27, count 2 2006.246.07:34:40.07#ibcon#read 5, iclass 27, count 2 2006.246.07:34:40.07#ibcon#about to read 6, iclass 27, count 2 2006.246.07:34:40.07#ibcon#read 6, iclass 27, count 2 2006.246.07:34:40.07#ibcon#end of sib2, iclass 27, count 2 2006.246.07:34:40.07#ibcon#*after write, iclass 27, count 2 2006.246.07:34:40.07#ibcon#*before return 0, iclass 27, count 2 2006.246.07:34:40.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:34:40.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:34:40.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.07:34:40.07#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:40.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:34:40.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:34:40.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:34:40.19#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:34:40.19#ibcon#first serial, iclass 27, count 0 2006.246.07:34:40.19#ibcon#enter sib2, iclass 27, count 0 2006.246.07:34:40.19#ibcon#flushed, iclass 27, count 0 2006.246.07:34:40.19#ibcon#about to write, iclass 27, count 0 2006.246.07:34:40.19#ibcon#wrote, iclass 27, count 0 2006.246.07:34:40.19#ibcon#about to read 3, iclass 27, count 0 2006.246.07:34:40.21#ibcon#read 3, iclass 27, count 0 2006.246.07:34:40.21#ibcon#about to read 4, iclass 27, count 0 2006.246.07:34:40.21#ibcon#read 4, iclass 27, count 0 2006.246.07:34:40.21#ibcon#about to read 5, iclass 27, count 0 2006.246.07:34:40.21#ibcon#read 5, iclass 27, count 0 2006.246.07:34:40.21#ibcon#about to read 6, iclass 27, count 0 2006.246.07:34:40.21#ibcon#read 6, iclass 27, count 0 2006.246.07:34:40.21#ibcon#end of sib2, iclass 27, count 0 2006.246.07:34:40.21#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:34:40.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:34:40.21#ibcon#[25=USB\r\n] 2006.246.07:34:40.21#ibcon#*before write, iclass 27, count 0 2006.246.07:34:40.21#ibcon#enter sib2, iclass 27, count 0 2006.246.07:34:40.21#ibcon#flushed, iclass 27, count 0 2006.246.07:34:40.21#ibcon#about to write, iclass 27, count 0 2006.246.07:34:40.21#ibcon#wrote, iclass 27, count 0 2006.246.07:34:40.21#ibcon#about to read 3, iclass 27, count 0 2006.246.07:34:40.24#ibcon#read 3, iclass 27, count 0 2006.246.07:34:40.24#ibcon#about to read 4, iclass 27, count 0 2006.246.07:34:40.24#ibcon#read 4, iclass 27, count 0 2006.246.07:34:40.24#ibcon#about to read 5, iclass 27, count 0 2006.246.07:34:40.24#ibcon#read 5, iclass 27, count 0 2006.246.07:34:40.24#ibcon#about to read 6, iclass 27, count 0 2006.246.07:34:40.24#ibcon#read 6, iclass 27, count 0 2006.246.07:34:40.24#ibcon#end of sib2, iclass 27, count 0 2006.246.07:34:40.24#ibcon#*after write, iclass 27, count 0 2006.246.07:34:40.24#ibcon#*before return 0, iclass 27, count 0 2006.246.07:34:40.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:34:40.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:34:40.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:34:40.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:34:40.24$vc4f8/valo=8,852.99 2006.246.07:34:40.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:34:40.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:34:40.24#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:40.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:34:40.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:34:40.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:34:40.24#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:34:40.24#ibcon#first serial, iclass 29, count 0 2006.246.07:34:40.24#ibcon#enter sib2, iclass 29, count 0 2006.246.07:34:40.24#ibcon#flushed, iclass 29, count 0 2006.246.07:34:40.24#ibcon#about to write, iclass 29, count 0 2006.246.07:34:40.24#ibcon#wrote, iclass 29, count 0 2006.246.07:34:40.24#ibcon#about to read 3, iclass 29, count 0 2006.246.07:34:40.26#ibcon#read 3, iclass 29, count 0 2006.246.07:34:40.26#ibcon#about to read 4, iclass 29, count 0 2006.246.07:34:40.26#ibcon#read 4, iclass 29, count 0 2006.246.07:34:40.26#ibcon#about to read 5, iclass 29, count 0 2006.246.07:34:40.26#ibcon#read 5, iclass 29, count 0 2006.246.07:34:40.26#ibcon#about to read 6, iclass 29, count 0 2006.246.07:34:40.26#ibcon#read 6, iclass 29, count 0 2006.246.07:34:40.26#ibcon#end of sib2, iclass 29, count 0 2006.246.07:34:40.26#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:34:40.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:34:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:34:40.26#ibcon#*before write, iclass 29, count 0 2006.246.07:34:40.26#ibcon#enter sib2, iclass 29, count 0 2006.246.07:34:40.26#ibcon#flushed, iclass 29, count 0 2006.246.07:34:40.26#ibcon#about to write, iclass 29, count 0 2006.246.07:34:40.26#ibcon#wrote, iclass 29, count 0 2006.246.07:34:40.26#ibcon#about to read 3, iclass 29, count 0 2006.246.07:34:40.30#ibcon#read 3, iclass 29, count 0 2006.246.07:34:40.30#ibcon#about to read 4, iclass 29, count 0 2006.246.07:34:40.30#ibcon#read 4, iclass 29, count 0 2006.246.07:34:40.30#ibcon#about to read 5, iclass 29, count 0 2006.246.07:34:40.30#ibcon#read 5, iclass 29, count 0 2006.246.07:34:40.30#ibcon#about to read 6, iclass 29, count 0 2006.246.07:34:40.30#ibcon#read 6, iclass 29, count 0 2006.246.07:34:40.30#ibcon#end of sib2, iclass 29, count 0 2006.246.07:34:40.30#ibcon#*after write, iclass 29, count 0 2006.246.07:34:40.30#ibcon#*before return 0, iclass 29, count 0 2006.246.07:34:40.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:34:40.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:34:40.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:34:40.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:34:40.30$vc4f8/va=8,8 2006.246.07:34:40.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.07:34:40.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.07:34:40.30#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:40.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:34:40.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:34:40.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:34:40.36#ibcon#enter wrdev, iclass 31, count 2 2006.246.07:34:40.36#ibcon#first serial, iclass 31, count 2 2006.246.07:34:40.36#ibcon#enter sib2, iclass 31, count 2 2006.246.07:34:40.36#ibcon#flushed, iclass 31, count 2 2006.246.07:34:40.36#ibcon#about to write, iclass 31, count 2 2006.246.07:34:40.36#ibcon#wrote, iclass 31, count 2 2006.246.07:34:40.36#ibcon#about to read 3, iclass 31, count 2 2006.246.07:34:40.38#ibcon#read 3, iclass 31, count 2 2006.246.07:34:40.38#ibcon#about to read 4, iclass 31, count 2 2006.246.07:34:40.38#ibcon#read 4, iclass 31, count 2 2006.246.07:34:40.38#ibcon#about to read 5, iclass 31, count 2 2006.246.07:34:40.38#ibcon#read 5, iclass 31, count 2 2006.246.07:34:40.38#ibcon#about to read 6, iclass 31, count 2 2006.246.07:34:40.38#ibcon#read 6, iclass 31, count 2 2006.246.07:34:40.38#ibcon#end of sib2, iclass 31, count 2 2006.246.07:34:40.38#ibcon#*mode == 0, iclass 31, count 2 2006.246.07:34:40.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.07:34:40.38#ibcon#[25=AT08-08\r\n] 2006.246.07:34:40.38#ibcon#*before write, iclass 31, count 2 2006.246.07:34:40.38#ibcon#enter sib2, iclass 31, count 2 2006.246.07:34:40.38#ibcon#flushed, iclass 31, count 2 2006.246.07:34:40.38#ibcon#about to write, iclass 31, count 2 2006.246.07:34:40.38#ibcon#wrote, iclass 31, count 2 2006.246.07:34:40.38#ibcon#about to read 3, iclass 31, count 2 2006.246.07:34:40.41#ibcon#read 3, iclass 31, count 2 2006.246.07:34:40.41#ibcon#about to read 4, iclass 31, count 2 2006.246.07:34:40.41#ibcon#read 4, iclass 31, count 2 2006.246.07:34:40.41#ibcon#about to read 5, iclass 31, count 2 2006.246.07:34:40.41#ibcon#read 5, iclass 31, count 2 2006.246.07:34:40.41#ibcon#about to read 6, iclass 31, count 2 2006.246.07:34:40.41#ibcon#read 6, iclass 31, count 2 2006.246.07:34:40.41#ibcon#end of sib2, iclass 31, count 2 2006.246.07:34:40.41#ibcon#*after write, iclass 31, count 2 2006.246.07:34:40.41#ibcon#*before return 0, iclass 31, count 2 2006.246.07:34:40.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:34:40.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:34:40.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.07:34:40.41#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:40.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:34:40.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:34:40.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:34:40.53#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:34:40.53#ibcon#first serial, iclass 31, count 0 2006.246.07:34:40.53#ibcon#enter sib2, iclass 31, count 0 2006.246.07:34:40.53#ibcon#flushed, iclass 31, count 0 2006.246.07:34:40.53#ibcon#about to write, iclass 31, count 0 2006.246.07:34:40.53#ibcon#wrote, iclass 31, count 0 2006.246.07:34:40.53#ibcon#about to read 3, iclass 31, count 0 2006.246.07:34:40.55#ibcon#read 3, iclass 31, count 0 2006.246.07:34:40.55#ibcon#about to read 4, iclass 31, count 0 2006.246.07:34:40.55#ibcon#read 4, iclass 31, count 0 2006.246.07:34:40.55#ibcon#about to read 5, iclass 31, count 0 2006.246.07:34:40.55#ibcon#read 5, iclass 31, count 0 2006.246.07:34:40.55#ibcon#about to read 6, iclass 31, count 0 2006.246.07:34:40.55#ibcon#read 6, iclass 31, count 0 2006.246.07:34:40.55#ibcon#end of sib2, iclass 31, count 0 2006.246.07:34:40.55#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:34:40.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:34:40.55#ibcon#[25=USB\r\n] 2006.246.07:34:40.55#ibcon#*before write, iclass 31, count 0 2006.246.07:34:40.55#ibcon#enter sib2, iclass 31, count 0 2006.246.07:34:40.55#ibcon#flushed, iclass 31, count 0 2006.246.07:34:40.55#ibcon#about to write, iclass 31, count 0 2006.246.07:34:40.55#ibcon#wrote, iclass 31, count 0 2006.246.07:34:40.55#ibcon#about to read 3, iclass 31, count 0 2006.246.07:34:40.58#ibcon#read 3, iclass 31, count 0 2006.246.07:34:40.58#ibcon#about to read 4, iclass 31, count 0 2006.246.07:34:40.58#ibcon#read 4, iclass 31, count 0 2006.246.07:34:40.58#ibcon#about to read 5, iclass 31, count 0 2006.246.07:34:40.58#ibcon#read 5, iclass 31, count 0 2006.246.07:34:40.58#ibcon#about to read 6, iclass 31, count 0 2006.246.07:34:40.58#ibcon#read 6, iclass 31, count 0 2006.246.07:34:40.58#ibcon#end of sib2, iclass 31, count 0 2006.246.07:34:40.58#ibcon#*after write, iclass 31, count 0 2006.246.07:34:40.58#ibcon#*before return 0, iclass 31, count 0 2006.246.07:34:40.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:34:40.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:34:40.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:34:40.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:34:40.58$vc4f8/vblo=1,632.99 2006.246.07:34:40.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.07:34:40.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.07:34:40.58#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:40.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:34:40.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:34:40.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:34:40.58#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:34:40.58#ibcon#first serial, iclass 33, count 0 2006.246.07:34:40.58#ibcon#enter sib2, iclass 33, count 0 2006.246.07:34:40.58#ibcon#flushed, iclass 33, count 0 2006.246.07:34:40.58#ibcon#about to write, iclass 33, count 0 2006.246.07:34:40.58#ibcon#wrote, iclass 33, count 0 2006.246.07:34:40.58#ibcon#about to read 3, iclass 33, count 0 2006.246.07:34:40.60#ibcon#read 3, iclass 33, count 0 2006.246.07:34:40.60#ibcon#about to read 4, iclass 33, count 0 2006.246.07:34:40.60#ibcon#read 4, iclass 33, count 0 2006.246.07:34:40.60#ibcon#about to read 5, iclass 33, count 0 2006.246.07:34:40.60#ibcon#read 5, iclass 33, count 0 2006.246.07:34:40.60#ibcon#about to read 6, iclass 33, count 0 2006.246.07:34:40.60#ibcon#read 6, iclass 33, count 0 2006.246.07:34:40.60#ibcon#end of sib2, iclass 33, count 0 2006.246.07:34:40.60#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:34:40.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:34:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:34:40.60#ibcon#*before write, iclass 33, count 0 2006.246.07:34:40.60#ibcon#enter sib2, iclass 33, count 0 2006.246.07:34:40.60#ibcon#flushed, iclass 33, count 0 2006.246.07:34:40.60#ibcon#about to write, iclass 33, count 0 2006.246.07:34:40.60#ibcon#wrote, iclass 33, count 0 2006.246.07:34:40.60#ibcon#about to read 3, iclass 33, count 0 2006.246.07:34:40.64#ibcon#read 3, iclass 33, count 0 2006.246.07:34:40.64#ibcon#about to read 4, iclass 33, count 0 2006.246.07:34:40.64#ibcon#read 4, iclass 33, count 0 2006.246.07:34:40.64#ibcon#about to read 5, iclass 33, count 0 2006.246.07:34:40.64#ibcon#read 5, iclass 33, count 0 2006.246.07:34:40.64#ibcon#about to read 6, iclass 33, count 0 2006.246.07:34:40.64#ibcon#read 6, iclass 33, count 0 2006.246.07:34:40.64#ibcon#end of sib2, iclass 33, count 0 2006.246.07:34:40.64#ibcon#*after write, iclass 33, count 0 2006.246.07:34:40.64#ibcon#*before return 0, iclass 33, count 0 2006.246.07:34:40.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:34:40.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:34:40.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:34:40.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:34:40.64$vc4f8/vb=1,4 2006.246.07:34:40.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.07:34:40.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.07:34:40.64#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:40.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:34:40.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:34:40.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:34:40.64#ibcon#enter wrdev, iclass 35, count 2 2006.246.07:34:40.64#ibcon#first serial, iclass 35, count 2 2006.246.07:34:40.64#ibcon#enter sib2, iclass 35, count 2 2006.246.07:34:40.64#ibcon#flushed, iclass 35, count 2 2006.246.07:34:40.64#ibcon#about to write, iclass 35, count 2 2006.246.07:34:40.64#ibcon#wrote, iclass 35, count 2 2006.246.07:34:40.64#ibcon#about to read 3, iclass 35, count 2 2006.246.07:34:40.66#ibcon#read 3, iclass 35, count 2 2006.246.07:34:40.66#ibcon#about to read 4, iclass 35, count 2 2006.246.07:34:40.66#ibcon#read 4, iclass 35, count 2 2006.246.07:34:40.66#ibcon#about to read 5, iclass 35, count 2 2006.246.07:34:40.66#ibcon#read 5, iclass 35, count 2 2006.246.07:34:40.66#ibcon#about to read 6, iclass 35, count 2 2006.246.07:34:40.66#ibcon#read 6, iclass 35, count 2 2006.246.07:34:40.66#ibcon#end of sib2, iclass 35, count 2 2006.246.07:34:40.66#ibcon#*mode == 0, iclass 35, count 2 2006.246.07:34:40.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.07:34:40.66#ibcon#[27=AT01-04\r\n] 2006.246.07:34:40.66#ibcon#*before write, iclass 35, count 2 2006.246.07:34:40.66#ibcon#enter sib2, iclass 35, count 2 2006.246.07:34:40.66#ibcon#flushed, iclass 35, count 2 2006.246.07:34:40.66#ibcon#about to write, iclass 35, count 2 2006.246.07:34:40.66#ibcon#wrote, iclass 35, count 2 2006.246.07:34:40.66#ibcon#about to read 3, iclass 35, count 2 2006.246.07:34:40.69#ibcon#read 3, iclass 35, count 2 2006.246.07:34:40.69#ibcon#about to read 4, iclass 35, count 2 2006.246.07:34:40.69#ibcon#read 4, iclass 35, count 2 2006.246.07:34:40.69#ibcon#about to read 5, iclass 35, count 2 2006.246.07:34:40.69#ibcon#read 5, iclass 35, count 2 2006.246.07:34:40.69#ibcon#about to read 6, iclass 35, count 2 2006.246.07:34:40.69#ibcon#read 6, iclass 35, count 2 2006.246.07:34:40.69#ibcon#end of sib2, iclass 35, count 2 2006.246.07:34:40.69#ibcon#*after write, iclass 35, count 2 2006.246.07:34:40.69#ibcon#*before return 0, iclass 35, count 2 2006.246.07:34:40.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:34:40.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:34:40.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.07:34:40.69#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:40.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:34:40.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:34:40.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:34:40.81#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:34:40.81#ibcon#first serial, iclass 35, count 0 2006.246.07:34:40.81#ibcon#enter sib2, iclass 35, count 0 2006.246.07:34:40.81#ibcon#flushed, iclass 35, count 0 2006.246.07:34:40.81#ibcon#about to write, iclass 35, count 0 2006.246.07:34:40.81#ibcon#wrote, iclass 35, count 0 2006.246.07:34:40.81#ibcon#about to read 3, iclass 35, count 0 2006.246.07:34:40.83#ibcon#read 3, iclass 35, count 0 2006.246.07:34:40.83#ibcon#about to read 4, iclass 35, count 0 2006.246.07:34:40.83#ibcon#read 4, iclass 35, count 0 2006.246.07:34:40.83#ibcon#about to read 5, iclass 35, count 0 2006.246.07:34:40.83#ibcon#read 5, iclass 35, count 0 2006.246.07:34:40.83#ibcon#about to read 6, iclass 35, count 0 2006.246.07:34:40.83#ibcon#read 6, iclass 35, count 0 2006.246.07:34:40.83#ibcon#end of sib2, iclass 35, count 0 2006.246.07:34:40.83#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:34:40.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:34:40.83#ibcon#[27=USB\r\n] 2006.246.07:34:40.83#ibcon#*before write, iclass 35, count 0 2006.246.07:34:40.83#ibcon#enter sib2, iclass 35, count 0 2006.246.07:34:40.83#ibcon#flushed, iclass 35, count 0 2006.246.07:34:40.83#ibcon#about to write, iclass 35, count 0 2006.246.07:34:40.83#ibcon#wrote, iclass 35, count 0 2006.246.07:34:40.83#ibcon#about to read 3, iclass 35, count 0 2006.246.07:34:40.86#ibcon#read 3, iclass 35, count 0 2006.246.07:34:40.86#ibcon#about to read 4, iclass 35, count 0 2006.246.07:34:40.86#ibcon#read 4, iclass 35, count 0 2006.246.07:34:40.86#ibcon#about to read 5, iclass 35, count 0 2006.246.07:34:40.86#ibcon#read 5, iclass 35, count 0 2006.246.07:34:40.86#ibcon#about to read 6, iclass 35, count 0 2006.246.07:34:40.86#ibcon#read 6, iclass 35, count 0 2006.246.07:34:40.86#ibcon#end of sib2, iclass 35, count 0 2006.246.07:34:40.86#ibcon#*after write, iclass 35, count 0 2006.246.07:34:40.86#ibcon#*before return 0, iclass 35, count 0 2006.246.07:34:40.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:34:40.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:34:40.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:34:40.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:34:40.86$vc4f8/vblo=2,640.99 2006.246.07:34:40.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.07:34:40.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.07:34:40.86#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:40.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:40.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:40.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:40.86#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:34:40.86#ibcon#first serial, iclass 37, count 0 2006.246.07:34:40.86#ibcon#enter sib2, iclass 37, count 0 2006.246.07:34:40.86#ibcon#flushed, iclass 37, count 0 2006.246.07:34:40.86#ibcon#about to write, iclass 37, count 0 2006.246.07:34:40.86#ibcon#wrote, iclass 37, count 0 2006.246.07:34:40.86#ibcon#about to read 3, iclass 37, count 0 2006.246.07:34:40.88#ibcon#read 3, iclass 37, count 0 2006.246.07:34:40.88#ibcon#about to read 4, iclass 37, count 0 2006.246.07:34:40.88#ibcon#read 4, iclass 37, count 0 2006.246.07:34:40.88#ibcon#about to read 5, iclass 37, count 0 2006.246.07:34:40.88#ibcon#read 5, iclass 37, count 0 2006.246.07:34:40.88#ibcon#about to read 6, iclass 37, count 0 2006.246.07:34:40.88#ibcon#read 6, iclass 37, count 0 2006.246.07:34:40.88#ibcon#end of sib2, iclass 37, count 0 2006.246.07:34:40.88#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:34:40.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:34:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:34:40.88#ibcon#*before write, iclass 37, count 0 2006.246.07:34:40.88#ibcon#enter sib2, iclass 37, count 0 2006.246.07:34:40.88#ibcon#flushed, iclass 37, count 0 2006.246.07:34:40.88#ibcon#about to write, iclass 37, count 0 2006.246.07:34:40.88#ibcon#wrote, iclass 37, count 0 2006.246.07:34:40.88#ibcon#about to read 3, iclass 37, count 0 2006.246.07:34:40.92#ibcon#read 3, iclass 37, count 0 2006.246.07:34:40.92#ibcon#about to read 4, iclass 37, count 0 2006.246.07:34:40.92#ibcon#read 4, iclass 37, count 0 2006.246.07:34:40.92#ibcon#about to read 5, iclass 37, count 0 2006.246.07:34:40.92#ibcon#read 5, iclass 37, count 0 2006.246.07:34:40.92#ibcon#about to read 6, iclass 37, count 0 2006.246.07:34:40.92#ibcon#read 6, iclass 37, count 0 2006.246.07:34:40.92#ibcon#end of sib2, iclass 37, count 0 2006.246.07:34:40.92#ibcon#*after write, iclass 37, count 0 2006.246.07:34:40.92#ibcon#*before return 0, iclass 37, count 0 2006.246.07:34:40.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:40.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:34:40.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:34:40.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:34:40.92$vc4f8/vb=2,4 2006.246.07:34:40.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.07:34:40.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.07:34:40.92#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:40.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:40.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:40.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:40.98#ibcon#enter wrdev, iclass 39, count 2 2006.246.07:34:40.98#ibcon#first serial, iclass 39, count 2 2006.246.07:34:40.98#ibcon#enter sib2, iclass 39, count 2 2006.246.07:34:40.98#ibcon#flushed, iclass 39, count 2 2006.246.07:34:40.98#ibcon#about to write, iclass 39, count 2 2006.246.07:34:40.98#ibcon#wrote, iclass 39, count 2 2006.246.07:34:40.98#ibcon#about to read 3, iclass 39, count 2 2006.246.07:34:41.00#ibcon#read 3, iclass 39, count 2 2006.246.07:34:41.00#ibcon#about to read 4, iclass 39, count 2 2006.246.07:34:41.00#ibcon#read 4, iclass 39, count 2 2006.246.07:34:41.00#ibcon#about to read 5, iclass 39, count 2 2006.246.07:34:41.00#ibcon#read 5, iclass 39, count 2 2006.246.07:34:41.00#ibcon#about to read 6, iclass 39, count 2 2006.246.07:34:41.00#ibcon#read 6, iclass 39, count 2 2006.246.07:34:41.00#ibcon#end of sib2, iclass 39, count 2 2006.246.07:34:41.00#ibcon#*mode == 0, iclass 39, count 2 2006.246.07:34:41.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.07:34:41.00#ibcon#[27=AT02-04\r\n] 2006.246.07:34:41.00#ibcon#*before write, iclass 39, count 2 2006.246.07:34:41.00#ibcon#enter sib2, iclass 39, count 2 2006.246.07:34:41.00#ibcon#flushed, iclass 39, count 2 2006.246.07:34:41.00#ibcon#about to write, iclass 39, count 2 2006.246.07:34:41.00#ibcon#wrote, iclass 39, count 2 2006.246.07:34:41.00#ibcon#about to read 3, iclass 39, count 2 2006.246.07:34:41.03#ibcon#read 3, iclass 39, count 2 2006.246.07:34:41.03#ibcon#about to read 4, iclass 39, count 2 2006.246.07:34:41.03#ibcon#read 4, iclass 39, count 2 2006.246.07:34:41.03#ibcon#about to read 5, iclass 39, count 2 2006.246.07:34:41.03#ibcon#read 5, iclass 39, count 2 2006.246.07:34:41.03#ibcon#about to read 6, iclass 39, count 2 2006.246.07:34:41.03#ibcon#read 6, iclass 39, count 2 2006.246.07:34:41.03#ibcon#end of sib2, iclass 39, count 2 2006.246.07:34:41.03#ibcon#*after write, iclass 39, count 2 2006.246.07:34:41.03#ibcon#*before return 0, iclass 39, count 2 2006.246.07:34:41.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:41.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:34:41.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.07:34:41.03#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:41.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:41.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:41.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:41.15#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:34:41.15#ibcon#first serial, iclass 39, count 0 2006.246.07:34:41.15#ibcon#enter sib2, iclass 39, count 0 2006.246.07:34:41.15#ibcon#flushed, iclass 39, count 0 2006.246.07:34:41.15#ibcon#about to write, iclass 39, count 0 2006.246.07:34:41.15#ibcon#wrote, iclass 39, count 0 2006.246.07:34:41.15#ibcon#about to read 3, iclass 39, count 0 2006.246.07:34:41.17#ibcon#read 3, iclass 39, count 0 2006.246.07:34:41.17#ibcon#about to read 4, iclass 39, count 0 2006.246.07:34:41.17#ibcon#read 4, iclass 39, count 0 2006.246.07:34:41.17#ibcon#about to read 5, iclass 39, count 0 2006.246.07:34:41.17#ibcon#read 5, iclass 39, count 0 2006.246.07:34:41.17#ibcon#about to read 6, iclass 39, count 0 2006.246.07:34:41.17#ibcon#read 6, iclass 39, count 0 2006.246.07:34:41.17#ibcon#end of sib2, iclass 39, count 0 2006.246.07:34:41.17#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:34:41.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:34:41.17#ibcon#[27=USB\r\n] 2006.246.07:34:41.17#ibcon#*before write, iclass 39, count 0 2006.246.07:34:41.17#ibcon#enter sib2, iclass 39, count 0 2006.246.07:34:41.17#ibcon#flushed, iclass 39, count 0 2006.246.07:34:41.17#ibcon#about to write, iclass 39, count 0 2006.246.07:34:41.17#ibcon#wrote, iclass 39, count 0 2006.246.07:34:41.17#ibcon#about to read 3, iclass 39, count 0 2006.246.07:34:41.20#ibcon#read 3, iclass 39, count 0 2006.246.07:34:41.20#ibcon#about to read 4, iclass 39, count 0 2006.246.07:34:41.20#ibcon#read 4, iclass 39, count 0 2006.246.07:34:41.20#ibcon#about to read 5, iclass 39, count 0 2006.246.07:34:41.20#ibcon#read 5, iclass 39, count 0 2006.246.07:34:41.20#ibcon#about to read 6, iclass 39, count 0 2006.246.07:34:41.20#ibcon#read 6, iclass 39, count 0 2006.246.07:34:41.20#ibcon#end of sib2, iclass 39, count 0 2006.246.07:34:41.20#ibcon#*after write, iclass 39, count 0 2006.246.07:34:41.20#ibcon#*before return 0, iclass 39, count 0 2006.246.07:34:41.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:41.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:34:41.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:34:41.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:34:41.20$vc4f8/vblo=3,656.99 2006.246.07:34:41.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.07:34:41.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.07:34:41.20#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:41.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:41.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:41.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:41.20#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:34:41.20#ibcon#first serial, iclass 3, count 0 2006.246.07:34:41.20#ibcon#enter sib2, iclass 3, count 0 2006.246.07:34:41.20#ibcon#flushed, iclass 3, count 0 2006.246.07:34:41.20#ibcon#about to write, iclass 3, count 0 2006.246.07:34:41.20#ibcon#wrote, iclass 3, count 0 2006.246.07:34:41.20#ibcon#about to read 3, iclass 3, count 0 2006.246.07:34:41.22#ibcon#read 3, iclass 3, count 0 2006.246.07:34:41.22#ibcon#about to read 4, iclass 3, count 0 2006.246.07:34:41.22#ibcon#read 4, iclass 3, count 0 2006.246.07:34:41.22#ibcon#about to read 5, iclass 3, count 0 2006.246.07:34:41.22#ibcon#read 5, iclass 3, count 0 2006.246.07:34:41.22#ibcon#about to read 6, iclass 3, count 0 2006.246.07:34:41.22#ibcon#read 6, iclass 3, count 0 2006.246.07:34:41.22#ibcon#end of sib2, iclass 3, count 0 2006.246.07:34:41.22#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:34:41.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:34:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:34:41.22#ibcon#*before write, iclass 3, count 0 2006.246.07:34:41.22#ibcon#enter sib2, iclass 3, count 0 2006.246.07:34:41.22#ibcon#flushed, iclass 3, count 0 2006.246.07:34:41.22#ibcon#about to write, iclass 3, count 0 2006.246.07:34:41.22#ibcon#wrote, iclass 3, count 0 2006.246.07:34:41.22#ibcon#about to read 3, iclass 3, count 0 2006.246.07:34:41.26#ibcon#read 3, iclass 3, count 0 2006.246.07:34:41.26#ibcon#about to read 4, iclass 3, count 0 2006.246.07:34:41.26#ibcon#read 4, iclass 3, count 0 2006.246.07:34:41.26#ibcon#about to read 5, iclass 3, count 0 2006.246.07:34:41.26#ibcon#read 5, iclass 3, count 0 2006.246.07:34:41.26#ibcon#about to read 6, iclass 3, count 0 2006.246.07:34:41.26#ibcon#read 6, iclass 3, count 0 2006.246.07:34:41.26#ibcon#end of sib2, iclass 3, count 0 2006.246.07:34:41.26#ibcon#*after write, iclass 3, count 0 2006.246.07:34:41.26#ibcon#*before return 0, iclass 3, count 0 2006.246.07:34:41.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:41.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:34:41.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:34:41.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:34:41.26$vc4f8/vb=3,4 2006.246.07:34:41.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.07:34:41.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.07:34:41.26#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:41.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:41.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:41.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:41.32#ibcon#enter wrdev, iclass 5, count 2 2006.246.07:34:41.32#ibcon#first serial, iclass 5, count 2 2006.246.07:34:41.32#ibcon#enter sib2, iclass 5, count 2 2006.246.07:34:41.32#ibcon#flushed, iclass 5, count 2 2006.246.07:34:41.32#ibcon#about to write, iclass 5, count 2 2006.246.07:34:41.32#ibcon#wrote, iclass 5, count 2 2006.246.07:34:41.32#ibcon#about to read 3, iclass 5, count 2 2006.246.07:34:41.34#ibcon#read 3, iclass 5, count 2 2006.246.07:34:41.34#ibcon#about to read 4, iclass 5, count 2 2006.246.07:34:41.34#ibcon#read 4, iclass 5, count 2 2006.246.07:34:41.34#ibcon#about to read 5, iclass 5, count 2 2006.246.07:34:41.34#ibcon#read 5, iclass 5, count 2 2006.246.07:34:41.34#ibcon#about to read 6, iclass 5, count 2 2006.246.07:34:41.34#ibcon#read 6, iclass 5, count 2 2006.246.07:34:41.34#ibcon#end of sib2, iclass 5, count 2 2006.246.07:34:41.34#ibcon#*mode == 0, iclass 5, count 2 2006.246.07:34:41.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.07:34:41.34#ibcon#[27=AT03-04\r\n] 2006.246.07:34:41.34#ibcon#*before write, iclass 5, count 2 2006.246.07:34:41.34#ibcon#enter sib2, iclass 5, count 2 2006.246.07:34:41.34#ibcon#flushed, iclass 5, count 2 2006.246.07:34:41.34#ibcon#about to write, iclass 5, count 2 2006.246.07:34:41.34#ibcon#wrote, iclass 5, count 2 2006.246.07:34:41.34#ibcon#about to read 3, iclass 5, count 2 2006.246.07:34:41.37#ibcon#read 3, iclass 5, count 2 2006.246.07:34:41.37#ibcon#about to read 4, iclass 5, count 2 2006.246.07:34:41.37#ibcon#read 4, iclass 5, count 2 2006.246.07:34:41.37#ibcon#about to read 5, iclass 5, count 2 2006.246.07:34:41.37#ibcon#read 5, iclass 5, count 2 2006.246.07:34:41.37#ibcon#about to read 6, iclass 5, count 2 2006.246.07:34:41.37#ibcon#read 6, iclass 5, count 2 2006.246.07:34:41.37#ibcon#end of sib2, iclass 5, count 2 2006.246.07:34:41.37#ibcon#*after write, iclass 5, count 2 2006.246.07:34:41.37#ibcon#*before return 0, iclass 5, count 2 2006.246.07:34:41.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:41.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:34:41.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.07:34:41.37#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:41.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:41.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:41.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:41.49#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:34:41.49#ibcon#first serial, iclass 5, count 0 2006.246.07:34:41.49#ibcon#enter sib2, iclass 5, count 0 2006.246.07:34:41.49#ibcon#flushed, iclass 5, count 0 2006.246.07:34:41.49#ibcon#about to write, iclass 5, count 0 2006.246.07:34:41.49#ibcon#wrote, iclass 5, count 0 2006.246.07:34:41.49#ibcon#about to read 3, iclass 5, count 0 2006.246.07:34:41.51#ibcon#read 3, iclass 5, count 0 2006.246.07:34:41.51#ibcon#about to read 4, iclass 5, count 0 2006.246.07:34:41.51#ibcon#read 4, iclass 5, count 0 2006.246.07:34:41.51#ibcon#about to read 5, iclass 5, count 0 2006.246.07:34:41.51#ibcon#read 5, iclass 5, count 0 2006.246.07:34:41.51#ibcon#about to read 6, iclass 5, count 0 2006.246.07:34:41.51#ibcon#read 6, iclass 5, count 0 2006.246.07:34:41.51#ibcon#end of sib2, iclass 5, count 0 2006.246.07:34:41.51#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:34:41.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:34:41.51#ibcon#[27=USB\r\n] 2006.246.07:34:41.51#ibcon#*before write, iclass 5, count 0 2006.246.07:34:41.51#ibcon#enter sib2, iclass 5, count 0 2006.246.07:34:41.51#ibcon#flushed, iclass 5, count 0 2006.246.07:34:41.51#ibcon#about to write, iclass 5, count 0 2006.246.07:34:41.51#ibcon#wrote, iclass 5, count 0 2006.246.07:34:41.51#ibcon#about to read 3, iclass 5, count 0 2006.246.07:34:41.54#ibcon#read 3, iclass 5, count 0 2006.246.07:34:41.54#ibcon#about to read 4, iclass 5, count 0 2006.246.07:34:41.54#ibcon#read 4, iclass 5, count 0 2006.246.07:34:41.54#ibcon#about to read 5, iclass 5, count 0 2006.246.07:34:41.54#ibcon#read 5, iclass 5, count 0 2006.246.07:34:41.54#ibcon#about to read 6, iclass 5, count 0 2006.246.07:34:41.54#ibcon#read 6, iclass 5, count 0 2006.246.07:34:41.54#ibcon#end of sib2, iclass 5, count 0 2006.246.07:34:41.54#ibcon#*after write, iclass 5, count 0 2006.246.07:34:41.54#ibcon#*before return 0, iclass 5, count 0 2006.246.07:34:41.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:41.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:34:41.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:34:41.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:34:41.54$vc4f8/vblo=4,712.99 2006.246.07:34:41.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.07:34:41.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.07:34:41.54#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:41.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:41.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:41.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:41.54#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:34:41.54#ibcon#first serial, iclass 7, count 0 2006.246.07:34:41.54#ibcon#enter sib2, iclass 7, count 0 2006.246.07:34:41.54#ibcon#flushed, iclass 7, count 0 2006.246.07:34:41.54#ibcon#about to write, iclass 7, count 0 2006.246.07:34:41.54#ibcon#wrote, iclass 7, count 0 2006.246.07:34:41.54#ibcon#about to read 3, iclass 7, count 0 2006.246.07:34:41.56#ibcon#read 3, iclass 7, count 0 2006.246.07:34:41.56#ibcon#about to read 4, iclass 7, count 0 2006.246.07:34:41.56#ibcon#read 4, iclass 7, count 0 2006.246.07:34:41.56#ibcon#about to read 5, iclass 7, count 0 2006.246.07:34:41.56#ibcon#read 5, iclass 7, count 0 2006.246.07:34:41.56#ibcon#about to read 6, iclass 7, count 0 2006.246.07:34:41.56#ibcon#read 6, iclass 7, count 0 2006.246.07:34:41.56#ibcon#end of sib2, iclass 7, count 0 2006.246.07:34:41.56#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:34:41.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:34:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:34:41.56#ibcon#*before write, iclass 7, count 0 2006.246.07:34:41.56#ibcon#enter sib2, iclass 7, count 0 2006.246.07:34:41.56#ibcon#flushed, iclass 7, count 0 2006.246.07:34:41.56#ibcon#about to write, iclass 7, count 0 2006.246.07:34:41.56#ibcon#wrote, iclass 7, count 0 2006.246.07:34:41.56#ibcon#about to read 3, iclass 7, count 0 2006.246.07:34:41.60#ibcon#read 3, iclass 7, count 0 2006.246.07:34:41.60#ibcon#about to read 4, iclass 7, count 0 2006.246.07:34:41.60#ibcon#read 4, iclass 7, count 0 2006.246.07:34:41.60#ibcon#about to read 5, iclass 7, count 0 2006.246.07:34:41.60#ibcon#read 5, iclass 7, count 0 2006.246.07:34:41.60#ibcon#about to read 6, iclass 7, count 0 2006.246.07:34:41.60#ibcon#read 6, iclass 7, count 0 2006.246.07:34:41.60#ibcon#end of sib2, iclass 7, count 0 2006.246.07:34:41.60#ibcon#*after write, iclass 7, count 0 2006.246.07:34:41.60#ibcon#*before return 0, iclass 7, count 0 2006.246.07:34:41.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:41.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:34:41.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:34:41.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:34:41.60$vc4f8/vb=4,4 2006.246.07:34:41.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.07:34:41.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.07:34:41.60#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:41.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:41.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:41.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:41.66#ibcon#enter wrdev, iclass 11, count 2 2006.246.07:34:41.66#ibcon#first serial, iclass 11, count 2 2006.246.07:34:41.66#ibcon#enter sib2, iclass 11, count 2 2006.246.07:34:41.66#ibcon#flushed, iclass 11, count 2 2006.246.07:34:41.66#ibcon#about to write, iclass 11, count 2 2006.246.07:34:41.66#ibcon#wrote, iclass 11, count 2 2006.246.07:34:41.66#ibcon#about to read 3, iclass 11, count 2 2006.246.07:34:41.68#ibcon#read 3, iclass 11, count 2 2006.246.07:34:41.68#ibcon#about to read 4, iclass 11, count 2 2006.246.07:34:41.68#ibcon#read 4, iclass 11, count 2 2006.246.07:34:41.68#ibcon#about to read 5, iclass 11, count 2 2006.246.07:34:41.68#ibcon#read 5, iclass 11, count 2 2006.246.07:34:41.68#ibcon#about to read 6, iclass 11, count 2 2006.246.07:34:41.68#ibcon#read 6, iclass 11, count 2 2006.246.07:34:41.68#ibcon#end of sib2, iclass 11, count 2 2006.246.07:34:41.68#ibcon#*mode == 0, iclass 11, count 2 2006.246.07:34:41.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.07:34:41.68#ibcon#[27=AT04-04\r\n] 2006.246.07:34:41.68#ibcon#*before write, iclass 11, count 2 2006.246.07:34:41.68#ibcon#enter sib2, iclass 11, count 2 2006.246.07:34:41.68#ibcon#flushed, iclass 11, count 2 2006.246.07:34:41.68#ibcon#about to write, iclass 11, count 2 2006.246.07:34:41.68#ibcon#wrote, iclass 11, count 2 2006.246.07:34:41.68#ibcon#about to read 3, iclass 11, count 2 2006.246.07:34:41.71#ibcon#read 3, iclass 11, count 2 2006.246.07:34:41.71#ibcon#about to read 4, iclass 11, count 2 2006.246.07:34:41.71#ibcon#read 4, iclass 11, count 2 2006.246.07:34:41.71#ibcon#about to read 5, iclass 11, count 2 2006.246.07:34:41.71#ibcon#read 5, iclass 11, count 2 2006.246.07:34:41.71#ibcon#about to read 6, iclass 11, count 2 2006.246.07:34:41.71#ibcon#read 6, iclass 11, count 2 2006.246.07:34:41.71#ibcon#end of sib2, iclass 11, count 2 2006.246.07:34:41.71#ibcon#*after write, iclass 11, count 2 2006.246.07:34:41.71#ibcon#*before return 0, iclass 11, count 2 2006.246.07:34:41.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:41.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:34:41.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.07:34:41.71#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:41.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:41.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:41.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:41.83#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:34:41.83#ibcon#first serial, iclass 11, count 0 2006.246.07:34:41.83#ibcon#enter sib2, iclass 11, count 0 2006.246.07:34:41.83#ibcon#flushed, iclass 11, count 0 2006.246.07:34:41.83#ibcon#about to write, iclass 11, count 0 2006.246.07:34:41.83#ibcon#wrote, iclass 11, count 0 2006.246.07:34:41.83#ibcon#about to read 3, iclass 11, count 0 2006.246.07:34:41.85#ibcon#read 3, iclass 11, count 0 2006.246.07:34:41.85#ibcon#about to read 4, iclass 11, count 0 2006.246.07:34:41.85#ibcon#read 4, iclass 11, count 0 2006.246.07:34:41.85#ibcon#about to read 5, iclass 11, count 0 2006.246.07:34:41.85#ibcon#read 5, iclass 11, count 0 2006.246.07:34:41.85#ibcon#about to read 6, iclass 11, count 0 2006.246.07:34:41.85#ibcon#read 6, iclass 11, count 0 2006.246.07:34:41.85#ibcon#end of sib2, iclass 11, count 0 2006.246.07:34:41.85#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:34:41.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:34:41.85#ibcon#[27=USB\r\n] 2006.246.07:34:41.85#ibcon#*before write, iclass 11, count 0 2006.246.07:34:41.85#ibcon#enter sib2, iclass 11, count 0 2006.246.07:34:41.85#ibcon#flushed, iclass 11, count 0 2006.246.07:34:41.85#ibcon#about to write, iclass 11, count 0 2006.246.07:34:41.85#ibcon#wrote, iclass 11, count 0 2006.246.07:34:41.85#ibcon#about to read 3, iclass 11, count 0 2006.246.07:34:41.88#ibcon#read 3, iclass 11, count 0 2006.246.07:34:41.88#ibcon#about to read 4, iclass 11, count 0 2006.246.07:34:41.88#ibcon#read 4, iclass 11, count 0 2006.246.07:34:41.88#ibcon#about to read 5, iclass 11, count 0 2006.246.07:34:41.88#ibcon#read 5, iclass 11, count 0 2006.246.07:34:41.88#ibcon#about to read 6, iclass 11, count 0 2006.246.07:34:41.88#ibcon#read 6, iclass 11, count 0 2006.246.07:34:41.88#ibcon#end of sib2, iclass 11, count 0 2006.246.07:34:41.88#ibcon#*after write, iclass 11, count 0 2006.246.07:34:41.88#ibcon#*before return 0, iclass 11, count 0 2006.246.07:34:41.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:41.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:34:41.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:34:41.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:34:41.88$vc4f8/vblo=5,744.99 2006.246.07:34:41.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.07:34:41.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.07:34:41.88#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:41.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:41.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:41.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:41.88#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:34:41.88#ibcon#first serial, iclass 13, count 0 2006.246.07:34:41.88#ibcon#enter sib2, iclass 13, count 0 2006.246.07:34:41.88#ibcon#flushed, iclass 13, count 0 2006.246.07:34:41.88#ibcon#about to write, iclass 13, count 0 2006.246.07:34:41.88#ibcon#wrote, iclass 13, count 0 2006.246.07:34:41.88#ibcon#about to read 3, iclass 13, count 0 2006.246.07:34:41.90#ibcon#read 3, iclass 13, count 0 2006.246.07:34:41.90#ibcon#about to read 4, iclass 13, count 0 2006.246.07:34:41.90#ibcon#read 4, iclass 13, count 0 2006.246.07:34:41.90#ibcon#about to read 5, iclass 13, count 0 2006.246.07:34:41.90#ibcon#read 5, iclass 13, count 0 2006.246.07:34:41.90#ibcon#about to read 6, iclass 13, count 0 2006.246.07:34:41.90#ibcon#read 6, iclass 13, count 0 2006.246.07:34:41.90#ibcon#end of sib2, iclass 13, count 0 2006.246.07:34:41.90#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:34:41.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:34:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:34:41.90#ibcon#*before write, iclass 13, count 0 2006.246.07:34:41.90#ibcon#enter sib2, iclass 13, count 0 2006.246.07:34:41.90#ibcon#flushed, iclass 13, count 0 2006.246.07:34:41.90#ibcon#about to write, iclass 13, count 0 2006.246.07:34:41.90#ibcon#wrote, iclass 13, count 0 2006.246.07:34:41.90#ibcon#about to read 3, iclass 13, count 0 2006.246.07:34:41.94#ibcon#read 3, iclass 13, count 0 2006.246.07:34:41.94#ibcon#about to read 4, iclass 13, count 0 2006.246.07:34:41.94#ibcon#read 4, iclass 13, count 0 2006.246.07:34:41.94#ibcon#about to read 5, iclass 13, count 0 2006.246.07:34:41.94#ibcon#read 5, iclass 13, count 0 2006.246.07:34:41.94#ibcon#about to read 6, iclass 13, count 0 2006.246.07:34:41.94#ibcon#read 6, iclass 13, count 0 2006.246.07:34:41.94#ibcon#end of sib2, iclass 13, count 0 2006.246.07:34:41.94#ibcon#*after write, iclass 13, count 0 2006.246.07:34:41.94#ibcon#*before return 0, iclass 13, count 0 2006.246.07:34:41.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:41.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:34:41.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:34:41.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:34:41.94$vc4f8/vb=5,3 2006.246.07:34:41.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.07:34:41.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.07:34:41.94#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:41.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:42.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:42.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:42.00#ibcon#enter wrdev, iclass 15, count 2 2006.246.07:34:42.00#ibcon#first serial, iclass 15, count 2 2006.246.07:34:42.00#ibcon#enter sib2, iclass 15, count 2 2006.246.07:34:42.00#ibcon#flushed, iclass 15, count 2 2006.246.07:34:42.00#ibcon#about to write, iclass 15, count 2 2006.246.07:34:42.00#ibcon#wrote, iclass 15, count 2 2006.246.07:34:42.00#ibcon#about to read 3, iclass 15, count 2 2006.246.07:34:42.02#ibcon#read 3, iclass 15, count 2 2006.246.07:34:42.02#ibcon#about to read 4, iclass 15, count 2 2006.246.07:34:42.02#ibcon#read 4, iclass 15, count 2 2006.246.07:34:42.02#ibcon#about to read 5, iclass 15, count 2 2006.246.07:34:42.02#ibcon#read 5, iclass 15, count 2 2006.246.07:34:42.02#ibcon#about to read 6, iclass 15, count 2 2006.246.07:34:42.02#ibcon#read 6, iclass 15, count 2 2006.246.07:34:42.02#ibcon#end of sib2, iclass 15, count 2 2006.246.07:34:42.02#ibcon#*mode == 0, iclass 15, count 2 2006.246.07:34:42.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.07:34:42.02#ibcon#[27=AT05-03\r\n] 2006.246.07:34:42.02#ibcon#*before write, iclass 15, count 2 2006.246.07:34:42.02#ibcon#enter sib2, iclass 15, count 2 2006.246.07:34:42.02#ibcon#flushed, iclass 15, count 2 2006.246.07:34:42.02#ibcon#about to write, iclass 15, count 2 2006.246.07:34:42.02#ibcon#wrote, iclass 15, count 2 2006.246.07:34:42.02#ibcon#about to read 3, iclass 15, count 2 2006.246.07:34:42.05#ibcon#read 3, iclass 15, count 2 2006.246.07:34:42.05#ibcon#about to read 4, iclass 15, count 2 2006.246.07:34:42.05#ibcon#read 4, iclass 15, count 2 2006.246.07:34:42.05#ibcon#about to read 5, iclass 15, count 2 2006.246.07:34:42.05#ibcon#read 5, iclass 15, count 2 2006.246.07:34:42.05#ibcon#about to read 6, iclass 15, count 2 2006.246.07:34:42.05#ibcon#read 6, iclass 15, count 2 2006.246.07:34:42.05#ibcon#end of sib2, iclass 15, count 2 2006.246.07:34:42.05#ibcon#*after write, iclass 15, count 2 2006.246.07:34:42.05#ibcon#*before return 0, iclass 15, count 2 2006.246.07:34:42.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:42.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:34:42.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.07:34:42.05#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:42.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:42.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:42.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:42.17#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:34:42.17#ibcon#first serial, iclass 15, count 0 2006.246.07:34:42.17#ibcon#enter sib2, iclass 15, count 0 2006.246.07:34:42.17#ibcon#flushed, iclass 15, count 0 2006.246.07:34:42.17#ibcon#about to write, iclass 15, count 0 2006.246.07:34:42.17#ibcon#wrote, iclass 15, count 0 2006.246.07:34:42.17#ibcon#about to read 3, iclass 15, count 0 2006.246.07:34:42.20#ibcon#read 3, iclass 15, count 0 2006.246.07:34:42.20#ibcon#about to read 4, iclass 15, count 0 2006.246.07:34:42.20#ibcon#read 4, iclass 15, count 0 2006.246.07:34:42.20#ibcon#about to read 5, iclass 15, count 0 2006.246.07:34:42.20#ibcon#read 5, iclass 15, count 0 2006.246.07:34:42.20#ibcon#about to read 6, iclass 15, count 0 2006.246.07:34:42.20#ibcon#read 6, iclass 15, count 0 2006.246.07:34:42.20#ibcon#end of sib2, iclass 15, count 0 2006.246.07:34:42.20#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:34:42.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:34:42.20#ibcon#[27=USB\r\n] 2006.246.07:34:42.20#ibcon#*before write, iclass 15, count 0 2006.246.07:34:42.20#ibcon#enter sib2, iclass 15, count 0 2006.246.07:34:42.20#ibcon#flushed, iclass 15, count 0 2006.246.07:34:42.20#ibcon#about to write, iclass 15, count 0 2006.246.07:34:42.20#ibcon#wrote, iclass 15, count 0 2006.246.07:34:42.20#ibcon#about to read 3, iclass 15, count 0 2006.246.07:34:42.23#ibcon#read 3, iclass 15, count 0 2006.246.07:34:42.23#ibcon#about to read 4, iclass 15, count 0 2006.246.07:34:42.23#ibcon#read 4, iclass 15, count 0 2006.246.07:34:42.23#ibcon#about to read 5, iclass 15, count 0 2006.246.07:34:42.23#ibcon#read 5, iclass 15, count 0 2006.246.07:34:42.23#ibcon#about to read 6, iclass 15, count 0 2006.246.07:34:42.23#ibcon#read 6, iclass 15, count 0 2006.246.07:34:42.23#ibcon#end of sib2, iclass 15, count 0 2006.246.07:34:42.23#ibcon#*after write, iclass 15, count 0 2006.246.07:34:42.23#ibcon#*before return 0, iclass 15, count 0 2006.246.07:34:42.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:42.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:34:42.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:34:42.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:34:42.23$vc4f8/vblo=6,752.99 2006.246.07:34:42.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:34:42.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:34:42.23#ibcon#ireg 17 cls_cnt 0 2006.246.07:34:42.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:42.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:42.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:42.23#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:34:42.23#ibcon#first serial, iclass 17, count 0 2006.246.07:34:42.23#ibcon#enter sib2, iclass 17, count 0 2006.246.07:34:42.23#ibcon#flushed, iclass 17, count 0 2006.246.07:34:42.23#ibcon#about to write, iclass 17, count 0 2006.246.07:34:42.23#ibcon#wrote, iclass 17, count 0 2006.246.07:34:42.23#ibcon#about to read 3, iclass 17, count 0 2006.246.07:34:42.25#ibcon#read 3, iclass 17, count 0 2006.246.07:34:42.25#ibcon#about to read 4, iclass 17, count 0 2006.246.07:34:42.25#ibcon#read 4, iclass 17, count 0 2006.246.07:34:42.25#ibcon#about to read 5, iclass 17, count 0 2006.246.07:34:42.25#ibcon#read 5, iclass 17, count 0 2006.246.07:34:42.25#ibcon#about to read 6, iclass 17, count 0 2006.246.07:34:42.25#ibcon#read 6, iclass 17, count 0 2006.246.07:34:42.25#ibcon#end of sib2, iclass 17, count 0 2006.246.07:34:42.25#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:34:42.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:34:42.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:34:42.25#ibcon#*before write, iclass 17, count 0 2006.246.07:34:42.25#ibcon#enter sib2, iclass 17, count 0 2006.246.07:34:42.25#ibcon#flushed, iclass 17, count 0 2006.246.07:34:42.25#ibcon#about to write, iclass 17, count 0 2006.246.07:34:42.25#ibcon#wrote, iclass 17, count 0 2006.246.07:34:42.25#ibcon#about to read 3, iclass 17, count 0 2006.246.07:34:42.29#ibcon#read 3, iclass 17, count 0 2006.246.07:34:42.29#ibcon#about to read 4, iclass 17, count 0 2006.246.07:34:42.29#ibcon#read 4, iclass 17, count 0 2006.246.07:34:42.29#ibcon#about to read 5, iclass 17, count 0 2006.246.07:34:42.29#ibcon#read 5, iclass 17, count 0 2006.246.07:34:42.29#ibcon#about to read 6, iclass 17, count 0 2006.246.07:34:42.29#ibcon#read 6, iclass 17, count 0 2006.246.07:34:42.29#ibcon#end of sib2, iclass 17, count 0 2006.246.07:34:42.29#ibcon#*after write, iclass 17, count 0 2006.246.07:34:42.29#ibcon#*before return 0, iclass 17, count 0 2006.246.07:34:42.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:42.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:34:42.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:34:42.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:34:42.29$vc4f8/vb=6,3 2006.246.07:34:42.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.07:34:42.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.07:34:42.29#ibcon#ireg 11 cls_cnt 2 2006.246.07:34:42.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:42.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:42.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:42.35#ibcon#enter wrdev, iclass 19, count 2 2006.246.07:34:42.35#ibcon#first serial, iclass 19, count 2 2006.246.07:34:42.35#ibcon#enter sib2, iclass 19, count 2 2006.246.07:34:42.35#ibcon#flushed, iclass 19, count 2 2006.246.07:34:42.35#ibcon#about to write, iclass 19, count 2 2006.246.07:34:42.35#ibcon#wrote, iclass 19, count 2 2006.246.07:34:42.35#ibcon#about to read 3, iclass 19, count 2 2006.246.07:34:42.37#ibcon#read 3, iclass 19, count 2 2006.246.07:34:42.37#ibcon#about to read 4, iclass 19, count 2 2006.246.07:34:42.37#ibcon#read 4, iclass 19, count 2 2006.246.07:34:42.37#ibcon#about to read 5, iclass 19, count 2 2006.246.07:34:42.37#ibcon#read 5, iclass 19, count 2 2006.246.07:34:42.37#ibcon#about to read 6, iclass 19, count 2 2006.246.07:34:42.37#ibcon#read 6, iclass 19, count 2 2006.246.07:34:42.37#ibcon#end of sib2, iclass 19, count 2 2006.246.07:34:42.37#ibcon#*mode == 0, iclass 19, count 2 2006.246.07:34:42.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.07:34:42.37#ibcon#[27=AT06-03\r\n] 2006.246.07:34:42.37#ibcon#*before write, iclass 19, count 2 2006.246.07:34:42.37#ibcon#enter sib2, iclass 19, count 2 2006.246.07:34:42.37#ibcon#flushed, iclass 19, count 2 2006.246.07:34:42.37#ibcon#about to write, iclass 19, count 2 2006.246.07:34:42.37#ibcon#wrote, iclass 19, count 2 2006.246.07:34:42.37#ibcon#about to read 3, iclass 19, count 2 2006.246.07:34:42.40#ibcon#read 3, iclass 19, count 2 2006.246.07:34:42.40#ibcon#about to read 4, iclass 19, count 2 2006.246.07:34:42.40#ibcon#read 4, iclass 19, count 2 2006.246.07:34:42.40#ibcon#about to read 5, iclass 19, count 2 2006.246.07:34:42.40#ibcon#read 5, iclass 19, count 2 2006.246.07:34:42.40#ibcon#about to read 6, iclass 19, count 2 2006.246.07:34:42.40#ibcon#read 6, iclass 19, count 2 2006.246.07:34:42.40#ibcon#end of sib2, iclass 19, count 2 2006.246.07:34:42.40#ibcon#*after write, iclass 19, count 2 2006.246.07:34:42.40#ibcon#*before return 0, iclass 19, count 2 2006.246.07:34:42.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:42.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:34:42.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.07:34:42.40#ibcon#ireg 7 cls_cnt 0 2006.246.07:34:42.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:42.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:42.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:42.52#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:34:42.52#ibcon#first serial, iclass 19, count 0 2006.246.07:34:42.52#ibcon#enter sib2, iclass 19, count 0 2006.246.07:34:42.52#ibcon#flushed, iclass 19, count 0 2006.246.07:34:42.52#ibcon#about to write, iclass 19, count 0 2006.246.07:34:42.52#ibcon#wrote, iclass 19, count 0 2006.246.07:34:42.52#ibcon#about to read 3, iclass 19, count 0 2006.246.07:34:42.54#ibcon#read 3, iclass 19, count 0 2006.246.07:34:42.54#ibcon#about to read 4, iclass 19, count 0 2006.246.07:34:42.54#ibcon#read 4, iclass 19, count 0 2006.246.07:34:42.54#ibcon#about to read 5, iclass 19, count 0 2006.246.07:34:42.54#ibcon#read 5, iclass 19, count 0 2006.246.07:34:42.54#ibcon#about to read 6, iclass 19, count 0 2006.246.07:34:42.54#ibcon#read 6, iclass 19, count 0 2006.246.07:34:42.54#ibcon#end of sib2, iclass 19, count 0 2006.246.07:34:42.54#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:34:42.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:34:42.54#ibcon#[27=USB\r\n] 2006.246.07:34:42.54#ibcon#*before write, iclass 19, count 0 2006.246.07:34:42.54#ibcon#enter sib2, iclass 19, count 0 2006.246.07:34:42.54#ibcon#flushed, iclass 19, count 0 2006.246.07:34:42.54#ibcon#about to write, iclass 19, count 0 2006.246.07:34:42.54#ibcon#wrote, iclass 19, count 0 2006.246.07:34:42.54#ibcon#about to read 3, iclass 19, count 0 2006.246.07:34:42.57#ibcon#read 3, iclass 19, count 0 2006.246.07:34:42.57#ibcon#about to read 4, iclass 19, count 0 2006.246.07:34:42.57#ibcon#read 4, iclass 19, count 0 2006.246.07:34:42.57#ibcon#about to read 5, iclass 19, count 0 2006.246.07:34:42.57#ibcon#read 5, iclass 19, count 0 2006.246.07:34:42.57#ibcon#about to read 6, iclass 19, count 0 2006.246.07:34:42.57#ibcon#read 6, iclass 19, count 0 2006.246.07:34:42.57#ibcon#end of sib2, iclass 19, count 0 2006.246.07:34:42.57#ibcon#*after write, iclass 19, count 0 2006.246.07:34:42.57#ibcon#*before return 0, iclass 19, count 0 2006.246.07:34:42.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:42.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:34:42.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:34:42.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:34:42.57$vc4f8/vabw=wide 2006.246.07:34:42.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.07:34:42.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.07:34:42.57#ibcon#ireg 8 cls_cnt 0 2006.246.07:34:42.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:42.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:42.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:42.57#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:34:42.57#ibcon#first serial, iclass 21, count 0 2006.246.07:34:42.57#ibcon#enter sib2, iclass 21, count 0 2006.246.07:34:42.57#ibcon#flushed, iclass 21, count 0 2006.246.07:34:42.57#ibcon#about to write, iclass 21, count 0 2006.246.07:34:42.57#ibcon#wrote, iclass 21, count 0 2006.246.07:34:42.57#ibcon#about to read 3, iclass 21, count 0 2006.246.07:34:42.59#ibcon#read 3, iclass 21, count 0 2006.246.07:34:42.59#ibcon#about to read 4, iclass 21, count 0 2006.246.07:34:42.59#ibcon#read 4, iclass 21, count 0 2006.246.07:34:42.59#ibcon#about to read 5, iclass 21, count 0 2006.246.07:34:42.59#ibcon#read 5, iclass 21, count 0 2006.246.07:34:42.59#ibcon#about to read 6, iclass 21, count 0 2006.246.07:34:42.59#ibcon#read 6, iclass 21, count 0 2006.246.07:34:42.59#ibcon#end of sib2, iclass 21, count 0 2006.246.07:34:42.59#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:34:42.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:34:42.59#ibcon#[25=BW32\r\n] 2006.246.07:34:42.59#ibcon#*before write, iclass 21, count 0 2006.246.07:34:42.59#ibcon#enter sib2, iclass 21, count 0 2006.246.07:34:42.59#ibcon#flushed, iclass 21, count 0 2006.246.07:34:42.59#ibcon#about to write, iclass 21, count 0 2006.246.07:34:42.59#ibcon#wrote, iclass 21, count 0 2006.246.07:34:42.59#ibcon#about to read 3, iclass 21, count 0 2006.246.07:34:42.62#ibcon#read 3, iclass 21, count 0 2006.246.07:34:42.62#ibcon#about to read 4, iclass 21, count 0 2006.246.07:34:42.62#ibcon#read 4, iclass 21, count 0 2006.246.07:34:42.62#ibcon#about to read 5, iclass 21, count 0 2006.246.07:34:42.62#ibcon#read 5, iclass 21, count 0 2006.246.07:34:42.62#ibcon#about to read 6, iclass 21, count 0 2006.246.07:34:42.62#ibcon#read 6, iclass 21, count 0 2006.246.07:34:42.62#ibcon#end of sib2, iclass 21, count 0 2006.246.07:34:42.62#ibcon#*after write, iclass 21, count 0 2006.246.07:34:42.62#ibcon#*before return 0, iclass 21, count 0 2006.246.07:34:42.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:42.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:34:42.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:34:42.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:34:42.62$vc4f8/vbbw=wide 2006.246.07:34:42.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:34:42.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:34:42.62#ibcon#ireg 8 cls_cnt 0 2006.246.07:34:42.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:34:42.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:34:42.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:34:42.69#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:34:42.69#ibcon#first serial, iclass 23, count 0 2006.246.07:34:42.69#ibcon#enter sib2, iclass 23, count 0 2006.246.07:34:42.69#ibcon#flushed, iclass 23, count 0 2006.246.07:34:42.69#ibcon#about to write, iclass 23, count 0 2006.246.07:34:42.69#ibcon#wrote, iclass 23, count 0 2006.246.07:34:42.69#ibcon#about to read 3, iclass 23, count 0 2006.246.07:34:42.71#ibcon#read 3, iclass 23, count 0 2006.246.07:34:42.71#ibcon#about to read 4, iclass 23, count 0 2006.246.07:34:42.71#ibcon#read 4, iclass 23, count 0 2006.246.07:34:42.71#ibcon#about to read 5, iclass 23, count 0 2006.246.07:34:42.71#ibcon#read 5, iclass 23, count 0 2006.246.07:34:42.71#ibcon#about to read 6, iclass 23, count 0 2006.246.07:34:42.71#ibcon#read 6, iclass 23, count 0 2006.246.07:34:42.71#ibcon#end of sib2, iclass 23, count 0 2006.246.07:34:42.71#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:34:42.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:34:42.71#ibcon#[27=BW32\r\n] 2006.246.07:34:42.71#ibcon#*before write, iclass 23, count 0 2006.246.07:34:42.71#ibcon#enter sib2, iclass 23, count 0 2006.246.07:34:42.71#ibcon#flushed, iclass 23, count 0 2006.246.07:34:42.71#ibcon#about to write, iclass 23, count 0 2006.246.07:34:42.71#ibcon#wrote, iclass 23, count 0 2006.246.07:34:42.71#ibcon#about to read 3, iclass 23, count 0 2006.246.07:34:42.74#ibcon#read 3, iclass 23, count 0 2006.246.07:34:42.74#ibcon#about to read 4, iclass 23, count 0 2006.246.07:34:42.74#ibcon#read 4, iclass 23, count 0 2006.246.07:34:42.74#ibcon#about to read 5, iclass 23, count 0 2006.246.07:34:42.74#ibcon#read 5, iclass 23, count 0 2006.246.07:34:42.74#ibcon#about to read 6, iclass 23, count 0 2006.246.07:34:42.74#ibcon#read 6, iclass 23, count 0 2006.246.07:34:42.74#ibcon#end of sib2, iclass 23, count 0 2006.246.07:34:42.74#ibcon#*after write, iclass 23, count 0 2006.246.07:34:42.74#ibcon#*before return 0, iclass 23, count 0 2006.246.07:34:42.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:34:42.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:34:42.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:34:42.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:34:42.74$4f8m12a/ifd4f 2006.246.07:34:42.74$ifd4f/lo= 2006.246.07:34:42.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:34:42.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:34:42.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:34:42.74$ifd4f/patch= 2006.246.07:34:42.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:34:42.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:34:42.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:34:42.74$4f8m12a/"form=m,16.000,1:2 2006.246.07:34:42.74$4f8m12a/"tpicd 2006.246.07:34:42.74$4f8m12a/echo=off 2006.246.07:34:42.74$4f8m12a/xlog=off 2006.246.07:34:42.74:!2006.246.07:35:10 2006.246.07:34:55.14#trakl#Source acquired 2006.246.07:34:55.14#flagr#flagr/antenna,acquired 2006.246.07:35:10.00:preob 2006.246.07:35:11.14/onsource/TRACKING 2006.246.07:35:11.14:!2006.246.07:35:20 2006.246.07:35:20.00:data_valid=on 2006.246.07:35:20.00:midob 2006.246.07:35:20.14/onsource/TRACKING 2006.246.07:35:20.14/wx/26.79,1005.6,73 2006.246.07:35:20.27/cable/+6.4128E-03 2006.246.07:35:21.36/va/01,08,usb,yes,31,32 2006.246.07:35:21.36/va/02,07,usb,yes,31,32 2006.246.07:35:21.36/va/03,06,usb,yes,33,33 2006.246.07:35:21.36/va/04,07,usb,yes,32,34 2006.246.07:35:21.36/va/05,07,usb,yes,34,35 2006.246.07:35:21.36/va/06,07,usb,yes,29,29 2006.246.07:35:21.36/va/07,07,usb,yes,29,29 2006.246.07:35:21.36/va/08,08,usb,yes,25,25 2006.246.07:35:21.59/valo/01,532.99,yes,locked 2006.246.07:35:21.59/valo/02,572.99,yes,locked 2006.246.07:35:21.59/valo/03,672.99,yes,locked 2006.246.07:35:21.59/valo/04,832.99,yes,locked 2006.246.07:35:21.59/valo/05,652.99,yes,locked 2006.246.07:35:21.59/valo/06,772.99,yes,locked 2006.246.07:35:21.59/valo/07,832.99,yes,locked 2006.246.07:35:21.59/valo/08,852.99,yes,locked 2006.246.07:35:22.68/vb/01,04,usb,yes,30,29 2006.246.07:35:22.68/vb/02,04,usb,yes,32,33 2006.246.07:35:22.68/vb/03,04,usb,yes,28,32 2006.246.07:35:22.68/vb/04,04,usb,yes,29,29 2006.246.07:35:22.68/vb/05,03,usb,yes,34,39 2006.246.07:35:22.68/vb/06,03,usb,yes,35,39 2006.246.07:35:22.68/vb/07,04,usb,yes,31,31 2006.246.07:35:22.68/vb/08,03,usb,yes,35,39 2006.246.07:35:22.92/vblo/01,632.99,yes,locked 2006.246.07:35:22.92/vblo/02,640.99,yes,locked 2006.246.07:35:22.92/vblo/03,656.99,yes,locked 2006.246.07:35:22.92/vblo/04,712.99,yes,locked 2006.246.07:35:22.92/vblo/05,744.99,yes,locked 2006.246.07:35:22.92/vblo/06,752.99,yes,locked 2006.246.07:35:22.92/vblo/07,734.99,yes,locked 2006.246.07:35:22.92/vblo/08,744.99,yes,locked 2006.246.07:35:23.07/vabw/8 2006.246.07:35:23.22/vbbw/8 2006.246.07:35:23.31/xfe/off,on,13.2 2006.246.07:35:23.68/ifatt/23,28,28,28 2006.246.07:35:24.08/fmout-gps/S +4.32E-07 2006.246.07:35:24.12:!2006.246.07:36:20 2006.246.07:36:20.00:data_valid=off 2006.246.07:36:20.00:postob 2006.246.07:36:20.14/cable/+6.4143E-03 2006.246.07:36:20.14/wx/26.79,1005.6,74 2006.246.07:36:21.09/fmout-gps/S +4.31E-07 2006.246.07:36:21.09:scan_name=246-0737,k06246,60 2006.246.07:36:21.09:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.246.07:36:21.13#flagr#flagr/antenna,new-source 2006.246.07:36:22.13:checkk5 2006.246.07:36:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:36:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:36:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:36:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:36:23.99/chk_obsdata//k5ts1/T2460735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:36:24.36/chk_obsdata//k5ts2/T2460735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:36:24.69/chk_obsdata//k5ts3/T2460735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:36:25.06/chk_obsdata//k5ts4/T2460735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:36:25.72/k5log//k5ts1_log_newline 2006.246.07:36:26.41/k5log//k5ts2_log_newline 2006.246.07:36:27.10/k5log//k5ts3_log_newline 2006.246.07:36:27.78/k5log//k5ts4_log_newline 2006.246.07:36:27.80/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:36:27.80:4f8m12a=1 2006.246.07:36:27.80$4f8m12a/echo=on 2006.246.07:36:27.80$4f8m12a/pcalon 2006.246.07:36:27.80$pcalon/"no phase cal control is implemented here 2006.246.07:36:27.80$4f8m12a/"tpicd=stop 2006.246.07:36:27.80$4f8m12a/vc4f8 2006.246.07:36:27.80$vc4f8/valo=1,532.99 2006.246.07:36:27.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:36:27.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:36:27.81#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:27.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:27.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:27.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:27.81#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:36:27.81#ibcon#first serial, iclass 30, count 0 2006.246.07:36:27.81#ibcon#enter sib2, iclass 30, count 0 2006.246.07:36:27.81#ibcon#flushed, iclass 30, count 0 2006.246.07:36:27.81#ibcon#about to write, iclass 30, count 0 2006.246.07:36:27.81#ibcon#wrote, iclass 30, count 0 2006.246.07:36:27.81#ibcon#about to read 3, iclass 30, count 0 2006.246.07:36:27.85#ibcon#read 3, iclass 30, count 0 2006.246.07:36:27.85#ibcon#about to read 4, iclass 30, count 0 2006.246.07:36:27.85#ibcon#read 4, iclass 30, count 0 2006.246.07:36:27.85#ibcon#about to read 5, iclass 30, count 0 2006.246.07:36:27.85#ibcon#read 5, iclass 30, count 0 2006.246.07:36:27.85#ibcon#about to read 6, iclass 30, count 0 2006.246.07:36:27.85#ibcon#read 6, iclass 30, count 0 2006.246.07:36:27.85#ibcon#end of sib2, iclass 30, count 0 2006.246.07:36:27.85#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:36:27.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:36:27.85#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:36:27.85#ibcon#*before write, iclass 30, count 0 2006.246.07:36:27.85#ibcon#enter sib2, iclass 30, count 0 2006.246.07:36:27.85#ibcon#flushed, iclass 30, count 0 2006.246.07:36:27.85#ibcon#about to write, iclass 30, count 0 2006.246.07:36:27.85#ibcon#wrote, iclass 30, count 0 2006.246.07:36:27.85#ibcon#about to read 3, iclass 30, count 0 2006.246.07:36:27.90#ibcon#read 3, iclass 30, count 0 2006.246.07:36:27.90#ibcon#about to read 4, iclass 30, count 0 2006.246.07:36:27.90#ibcon#read 4, iclass 30, count 0 2006.246.07:36:27.90#ibcon#about to read 5, iclass 30, count 0 2006.246.07:36:27.90#ibcon#read 5, iclass 30, count 0 2006.246.07:36:27.90#ibcon#about to read 6, iclass 30, count 0 2006.246.07:36:27.90#ibcon#read 6, iclass 30, count 0 2006.246.07:36:27.90#ibcon#end of sib2, iclass 30, count 0 2006.246.07:36:27.90#ibcon#*after write, iclass 30, count 0 2006.246.07:36:27.90#ibcon#*before return 0, iclass 30, count 0 2006.246.07:36:27.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:27.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:27.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:36:27.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:36:27.90$vc4f8/va=1,8 2006.246.07:36:27.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:36:27.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:36:27.90#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:27.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:27.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:27.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:27.90#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:36:27.90#ibcon#first serial, iclass 32, count 2 2006.246.07:36:27.90#ibcon#enter sib2, iclass 32, count 2 2006.246.07:36:27.90#ibcon#flushed, iclass 32, count 2 2006.246.07:36:27.90#ibcon#about to write, iclass 32, count 2 2006.246.07:36:27.90#ibcon#wrote, iclass 32, count 2 2006.246.07:36:27.90#ibcon#about to read 3, iclass 32, count 2 2006.246.07:36:27.92#ibcon#read 3, iclass 32, count 2 2006.246.07:36:27.92#ibcon#about to read 4, iclass 32, count 2 2006.246.07:36:27.92#ibcon#read 4, iclass 32, count 2 2006.246.07:36:27.92#ibcon#about to read 5, iclass 32, count 2 2006.246.07:36:27.92#ibcon#read 5, iclass 32, count 2 2006.246.07:36:27.92#ibcon#about to read 6, iclass 32, count 2 2006.246.07:36:27.92#ibcon#read 6, iclass 32, count 2 2006.246.07:36:27.92#ibcon#end of sib2, iclass 32, count 2 2006.246.07:36:27.92#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:36:27.92#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:36:27.92#ibcon#[25=AT01-08\r\n] 2006.246.07:36:27.92#ibcon#*before write, iclass 32, count 2 2006.246.07:36:27.92#ibcon#enter sib2, iclass 32, count 2 2006.246.07:36:27.92#ibcon#flushed, iclass 32, count 2 2006.246.07:36:27.92#ibcon#about to write, iclass 32, count 2 2006.246.07:36:27.92#ibcon#wrote, iclass 32, count 2 2006.246.07:36:27.92#ibcon#about to read 3, iclass 32, count 2 2006.246.07:36:27.95#ibcon#read 3, iclass 32, count 2 2006.246.07:36:27.95#ibcon#about to read 4, iclass 32, count 2 2006.246.07:36:27.95#ibcon#read 4, iclass 32, count 2 2006.246.07:36:27.95#ibcon#about to read 5, iclass 32, count 2 2006.246.07:36:27.95#ibcon#read 5, iclass 32, count 2 2006.246.07:36:27.95#ibcon#about to read 6, iclass 32, count 2 2006.246.07:36:27.95#ibcon#read 6, iclass 32, count 2 2006.246.07:36:27.95#ibcon#end of sib2, iclass 32, count 2 2006.246.07:36:27.95#ibcon#*after write, iclass 32, count 2 2006.246.07:36:27.95#ibcon#*before return 0, iclass 32, count 2 2006.246.07:36:27.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:27.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:27.95#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:36:27.95#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:27.95#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:28.07#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:28.07#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:28.07#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:36:28.07#ibcon#first serial, iclass 32, count 0 2006.246.07:36:28.07#ibcon#enter sib2, iclass 32, count 0 2006.246.07:36:28.07#ibcon#flushed, iclass 32, count 0 2006.246.07:36:28.07#ibcon#about to write, iclass 32, count 0 2006.246.07:36:28.07#ibcon#wrote, iclass 32, count 0 2006.246.07:36:28.07#ibcon#about to read 3, iclass 32, count 0 2006.246.07:36:28.09#ibcon#read 3, iclass 32, count 0 2006.246.07:36:28.09#ibcon#about to read 4, iclass 32, count 0 2006.246.07:36:28.09#ibcon#read 4, iclass 32, count 0 2006.246.07:36:28.09#ibcon#about to read 5, iclass 32, count 0 2006.246.07:36:28.09#ibcon#read 5, iclass 32, count 0 2006.246.07:36:28.09#ibcon#about to read 6, iclass 32, count 0 2006.246.07:36:28.09#ibcon#read 6, iclass 32, count 0 2006.246.07:36:28.09#ibcon#end of sib2, iclass 32, count 0 2006.246.07:36:28.09#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:36:28.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:36:28.09#ibcon#[25=USB\r\n] 2006.246.07:36:28.09#ibcon#*before write, iclass 32, count 0 2006.246.07:36:28.09#ibcon#enter sib2, iclass 32, count 0 2006.246.07:36:28.09#ibcon#flushed, iclass 32, count 0 2006.246.07:36:28.09#ibcon#about to write, iclass 32, count 0 2006.246.07:36:28.09#ibcon#wrote, iclass 32, count 0 2006.246.07:36:28.09#ibcon#about to read 3, iclass 32, count 0 2006.246.07:36:28.12#ibcon#read 3, iclass 32, count 0 2006.246.07:36:28.12#ibcon#about to read 4, iclass 32, count 0 2006.246.07:36:28.12#ibcon#read 4, iclass 32, count 0 2006.246.07:36:28.12#ibcon#about to read 5, iclass 32, count 0 2006.246.07:36:28.12#ibcon#read 5, iclass 32, count 0 2006.246.07:36:28.12#ibcon#about to read 6, iclass 32, count 0 2006.246.07:36:28.12#ibcon#read 6, iclass 32, count 0 2006.246.07:36:28.12#ibcon#end of sib2, iclass 32, count 0 2006.246.07:36:28.12#ibcon#*after write, iclass 32, count 0 2006.246.07:36:28.12#ibcon#*before return 0, iclass 32, count 0 2006.246.07:36:28.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:28.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:28.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:36:28.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:36:28.12$vc4f8/valo=2,572.99 2006.246.07:36:28.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:36:28.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:36:28.12#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:28.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:28.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:28.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:28.12#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:36:28.12#ibcon#first serial, iclass 34, count 0 2006.246.07:36:28.12#ibcon#enter sib2, iclass 34, count 0 2006.246.07:36:28.12#ibcon#flushed, iclass 34, count 0 2006.246.07:36:28.12#ibcon#about to write, iclass 34, count 0 2006.246.07:36:28.12#ibcon#wrote, iclass 34, count 0 2006.246.07:36:28.12#ibcon#about to read 3, iclass 34, count 0 2006.246.07:36:28.14#ibcon#read 3, iclass 34, count 0 2006.246.07:36:28.14#ibcon#about to read 4, iclass 34, count 0 2006.246.07:36:28.14#ibcon#read 4, iclass 34, count 0 2006.246.07:36:28.14#ibcon#about to read 5, iclass 34, count 0 2006.246.07:36:28.14#ibcon#read 5, iclass 34, count 0 2006.246.07:36:28.14#ibcon#about to read 6, iclass 34, count 0 2006.246.07:36:28.14#ibcon#read 6, iclass 34, count 0 2006.246.07:36:28.14#ibcon#end of sib2, iclass 34, count 0 2006.246.07:36:28.14#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:36:28.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:36:28.14#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:36:28.14#ibcon#*before write, iclass 34, count 0 2006.246.07:36:28.14#ibcon#enter sib2, iclass 34, count 0 2006.246.07:36:28.14#ibcon#flushed, iclass 34, count 0 2006.246.07:36:28.14#ibcon#about to write, iclass 34, count 0 2006.246.07:36:28.14#ibcon#wrote, iclass 34, count 0 2006.246.07:36:28.14#ibcon#about to read 3, iclass 34, count 0 2006.246.07:36:28.18#ibcon#read 3, iclass 34, count 0 2006.246.07:36:28.18#ibcon#about to read 4, iclass 34, count 0 2006.246.07:36:28.18#ibcon#read 4, iclass 34, count 0 2006.246.07:36:28.18#ibcon#about to read 5, iclass 34, count 0 2006.246.07:36:28.18#ibcon#read 5, iclass 34, count 0 2006.246.07:36:28.18#ibcon#about to read 6, iclass 34, count 0 2006.246.07:36:28.18#ibcon#read 6, iclass 34, count 0 2006.246.07:36:28.18#ibcon#end of sib2, iclass 34, count 0 2006.246.07:36:28.18#ibcon#*after write, iclass 34, count 0 2006.246.07:36:28.18#ibcon#*before return 0, iclass 34, count 0 2006.246.07:36:28.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:28.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:28.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:36:28.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:36:28.18$vc4f8/va=2,7 2006.246.07:36:28.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:36:28.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:36:28.18#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:28.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:28.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:28.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:28.24#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:36:28.24#ibcon#first serial, iclass 36, count 2 2006.246.07:36:28.24#ibcon#enter sib2, iclass 36, count 2 2006.246.07:36:28.24#ibcon#flushed, iclass 36, count 2 2006.246.07:36:28.24#ibcon#about to write, iclass 36, count 2 2006.246.07:36:28.24#ibcon#wrote, iclass 36, count 2 2006.246.07:36:28.24#ibcon#about to read 3, iclass 36, count 2 2006.246.07:36:28.26#ibcon#read 3, iclass 36, count 2 2006.246.07:36:28.26#ibcon#about to read 4, iclass 36, count 2 2006.246.07:36:28.26#ibcon#read 4, iclass 36, count 2 2006.246.07:36:28.26#ibcon#about to read 5, iclass 36, count 2 2006.246.07:36:28.26#ibcon#read 5, iclass 36, count 2 2006.246.07:36:28.26#ibcon#about to read 6, iclass 36, count 2 2006.246.07:36:28.26#ibcon#read 6, iclass 36, count 2 2006.246.07:36:28.26#ibcon#end of sib2, iclass 36, count 2 2006.246.07:36:28.26#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:36:28.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:36:28.26#ibcon#[25=AT02-07\r\n] 2006.246.07:36:28.26#ibcon#*before write, iclass 36, count 2 2006.246.07:36:28.26#ibcon#enter sib2, iclass 36, count 2 2006.246.07:36:28.26#ibcon#flushed, iclass 36, count 2 2006.246.07:36:28.26#ibcon#about to write, iclass 36, count 2 2006.246.07:36:28.26#ibcon#wrote, iclass 36, count 2 2006.246.07:36:28.26#ibcon#about to read 3, iclass 36, count 2 2006.246.07:36:28.29#ibcon#read 3, iclass 36, count 2 2006.246.07:36:28.29#ibcon#about to read 4, iclass 36, count 2 2006.246.07:36:28.29#ibcon#read 4, iclass 36, count 2 2006.246.07:36:28.29#ibcon#about to read 5, iclass 36, count 2 2006.246.07:36:28.29#ibcon#read 5, iclass 36, count 2 2006.246.07:36:28.29#ibcon#about to read 6, iclass 36, count 2 2006.246.07:36:28.29#ibcon#read 6, iclass 36, count 2 2006.246.07:36:28.29#ibcon#end of sib2, iclass 36, count 2 2006.246.07:36:28.29#ibcon#*after write, iclass 36, count 2 2006.246.07:36:28.29#ibcon#*before return 0, iclass 36, count 2 2006.246.07:36:28.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:28.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:28.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:36:28.29#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:28.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:28.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:28.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:28.41#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:36:28.41#ibcon#first serial, iclass 36, count 0 2006.246.07:36:28.41#ibcon#enter sib2, iclass 36, count 0 2006.246.07:36:28.41#ibcon#flushed, iclass 36, count 0 2006.246.07:36:28.41#ibcon#about to write, iclass 36, count 0 2006.246.07:36:28.41#ibcon#wrote, iclass 36, count 0 2006.246.07:36:28.41#ibcon#about to read 3, iclass 36, count 0 2006.246.07:36:28.43#ibcon#read 3, iclass 36, count 0 2006.246.07:36:28.43#ibcon#about to read 4, iclass 36, count 0 2006.246.07:36:28.43#ibcon#read 4, iclass 36, count 0 2006.246.07:36:28.43#ibcon#about to read 5, iclass 36, count 0 2006.246.07:36:28.43#ibcon#read 5, iclass 36, count 0 2006.246.07:36:28.43#ibcon#about to read 6, iclass 36, count 0 2006.246.07:36:28.43#ibcon#read 6, iclass 36, count 0 2006.246.07:36:28.43#ibcon#end of sib2, iclass 36, count 0 2006.246.07:36:28.43#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:36:28.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:36:28.43#ibcon#[25=USB\r\n] 2006.246.07:36:28.43#ibcon#*before write, iclass 36, count 0 2006.246.07:36:28.43#ibcon#enter sib2, iclass 36, count 0 2006.246.07:36:28.43#ibcon#flushed, iclass 36, count 0 2006.246.07:36:28.43#ibcon#about to write, iclass 36, count 0 2006.246.07:36:28.43#ibcon#wrote, iclass 36, count 0 2006.246.07:36:28.43#ibcon#about to read 3, iclass 36, count 0 2006.246.07:36:28.46#ibcon#read 3, iclass 36, count 0 2006.246.07:36:28.46#ibcon#about to read 4, iclass 36, count 0 2006.246.07:36:28.46#ibcon#read 4, iclass 36, count 0 2006.246.07:36:28.46#ibcon#about to read 5, iclass 36, count 0 2006.246.07:36:28.46#ibcon#read 5, iclass 36, count 0 2006.246.07:36:28.46#ibcon#about to read 6, iclass 36, count 0 2006.246.07:36:28.46#ibcon#read 6, iclass 36, count 0 2006.246.07:36:28.46#ibcon#end of sib2, iclass 36, count 0 2006.246.07:36:28.46#ibcon#*after write, iclass 36, count 0 2006.246.07:36:28.46#ibcon#*before return 0, iclass 36, count 0 2006.246.07:36:28.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:28.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:28.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:36:28.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:36:28.46$vc4f8/valo=3,672.99 2006.246.07:36:28.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:36:28.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:36:28.46#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:28.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:28.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:28.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:28.46#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:36:28.46#ibcon#first serial, iclass 38, count 0 2006.246.07:36:28.46#ibcon#enter sib2, iclass 38, count 0 2006.246.07:36:28.46#ibcon#flushed, iclass 38, count 0 2006.246.07:36:28.46#ibcon#about to write, iclass 38, count 0 2006.246.07:36:28.46#ibcon#wrote, iclass 38, count 0 2006.246.07:36:28.46#ibcon#about to read 3, iclass 38, count 0 2006.246.07:36:28.48#ibcon#read 3, iclass 38, count 0 2006.246.07:36:28.48#ibcon#about to read 4, iclass 38, count 0 2006.246.07:36:28.48#ibcon#read 4, iclass 38, count 0 2006.246.07:36:28.48#ibcon#about to read 5, iclass 38, count 0 2006.246.07:36:28.48#ibcon#read 5, iclass 38, count 0 2006.246.07:36:28.48#ibcon#about to read 6, iclass 38, count 0 2006.246.07:36:28.48#ibcon#read 6, iclass 38, count 0 2006.246.07:36:28.48#ibcon#end of sib2, iclass 38, count 0 2006.246.07:36:28.48#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:36:28.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:36:28.48#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:36:28.48#ibcon#*before write, iclass 38, count 0 2006.246.07:36:28.48#ibcon#enter sib2, iclass 38, count 0 2006.246.07:36:28.48#ibcon#flushed, iclass 38, count 0 2006.246.07:36:28.48#ibcon#about to write, iclass 38, count 0 2006.246.07:36:28.48#ibcon#wrote, iclass 38, count 0 2006.246.07:36:28.48#ibcon#about to read 3, iclass 38, count 0 2006.246.07:36:28.52#ibcon#read 3, iclass 38, count 0 2006.246.07:36:28.52#ibcon#about to read 4, iclass 38, count 0 2006.246.07:36:28.52#ibcon#read 4, iclass 38, count 0 2006.246.07:36:28.52#ibcon#about to read 5, iclass 38, count 0 2006.246.07:36:28.52#ibcon#read 5, iclass 38, count 0 2006.246.07:36:28.52#ibcon#about to read 6, iclass 38, count 0 2006.246.07:36:28.52#ibcon#read 6, iclass 38, count 0 2006.246.07:36:28.52#ibcon#end of sib2, iclass 38, count 0 2006.246.07:36:28.52#ibcon#*after write, iclass 38, count 0 2006.246.07:36:28.52#ibcon#*before return 0, iclass 38, count 0 2006.246.07:36:28.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:28.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:28.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:36:28.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:36:28.52$vc4f8/va=3,6 2006.246.07:36:28.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.07:36:28.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.07:36:28.52#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:28.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:28.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:28.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:28.58#ibcon#enter wrdev, iclass 40, count 2 2006.246.07:36:28.58#ibcon#first serial, iclass 40, count 2 2006.246.07:36:28.58#ibcon#enter sib2, iclass 40, count 2 2006.246.07:36:28.58#ibcon#flushed, iclass 40, count 2 2006.246.07:36:28.58#ibcon#about to write, iclass 40, count 2 2006.246.07:36:28.58#ibcon#wrote, iclass 40, count 2 2006.246.07:36:28.58#ibcon#about to read 3, iclass 40, count 2 2006.246.07:36:28.60#ibcon#read 3, iclass 40, count 2 2006.246.07:36:28.60#ibcon#about to read 4, iclass 40, count 2 2006.246.07:36:28.60#ibcon#read 4, iclass 40, count 2 2006.246.07:36:28.60#ibcon#about to read 5, iclass 40, count 2 2006.246.07:36:28.60#ibcon#read 5, iclass 40, count 2 2006.246.07:36:28.60#ibcon#about to read 6, iclass 40, count 2 2006.246.07:36:28.60#ibcon#read 6, iclass 40, count 2 2006.246.07:36:28.60#ibcon#end of sib2, iclass 40, count 2 2006.246.07:36:28.60#ibcon#*mode == 0, iclass 40, count 2 2006.246.07:36:28.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.07:36:28.60#ibcon#[25=AT03-06\r\n] 2006.246.07:36:28.60#ibcon#*before write, iclass 40, count 2 2006.246.07:36:28.60#ibcon#enter sib2, iclass 40, count 2 2006.246.07:36:28.60#ibcon#flushed, iclass 40, count 2 2006.246.07:36:28.60#ibcon#about to write, iclass 40, count 2 2006.246.07:36:28.60#ibcon#wrote, iclass 40, count 2 2006.246.07:36:28.60#ibcon#about to read 3, iclass 40, count 2 2006.246.07:36:28.63#ibcon#read 3, iclass 40, count 2 2006.246.07:36:28.63#ibcon#about to read 4, iclass 40, count 2 2006.246.07:36:28.63#ibcon#read 4, iclass 40, count 2 2006.246.07:36:28.63#ibcon#about to read 5, iclass 40, count 2 2006.246.07:36:28.63#ibcon#read 5, iclass 40, count 2 2006.246.07:36:28.63#ibcon#about to read 6, iclass 40, count 2 2006.246.07:36:28.63#ibcon#read 6, iclass 40, count 2 2006.246.07:36:28.63#ibcon#end of sib2, iclass 40, count 2 2006.246.07:36:28.63#ibcon#*after write, iclass 40, count 2 2006.246.07:36:28.63#ibcon#*before return 0, iclass 40, count 2 2006.246.07:36:28.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:28.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:28.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.07:36:28.63#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:28.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:28.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:28.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:28.75#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:36:28.75#ibcon#first serial, iclass 40, count 0 2006.246.07:36:28.75#ibcon#enter sib2, iclass 40, count 0 2006.246.07:36:28.75#ibcon#flushed, iclass 40, count 0 2006.246.07:36:28.75#ibcon#about to write, iclass 40, count 0 2006.246.07:36:28.75#ibcon#wrote, iclass 40, count 0 2006.246.07:36:28.75#ibcon#about to read 3, iclass 40, count 0 2006.246.07:36:28.77#ibcon#read 3, iclass 40, count 0 2006.246.07:36:28.77#ibcon#about to read 4, iclass 40, count 0 2006.246.07:36:28.77#ibcon#read 4, iclass 40, count 0 2006.246.07:36:28.77#ibcon#about to read 5, iclass 40, count 0 2006.246.07:36:28.77#ibcon#read 5, iclass 40, count 0 2006.246.07:36:28.77#ibcon#about to read 6, iclass 40, count 0 2006.246.07:36:28.77#ibcon#read 6, iclass 40, count 0 2006.246.07:36:28.77#ibcon#end of sib2, iclass 40, count 0 2006.246.07:36:28.77#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:36:28.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:36:28.77#ibcon#[25=USB\r\n] 2006.246.07:36:28.77#ibcon#*before write, iclass 40, count 0 2006.246.07:36:28.77#ibcon#enter sib2, iclass 40, count 0 2006.246.07:36:28.77#ibcon#flushed, iclass 40, count 0 2006.246.07:36:28.77#ibcon#about to write, iclass 40, count 0 2006.246.07:36:28.77#ibcon#wrote, iclass 40, count 0 2006.246.07:36:28.77#ibcon#about to read 3, iclass 40, count 0 2006.246.07:36:28.80#ibcon#read 3, iclass 40, count 0 2006.246.07:36:28.80#ibcon#about to read 4, iclass 40, count 0 2006.246.07:36:28.80#ibcon#read 4, iclass 40, count 0 2006.246.07:36:28.80#ibcon#about to read 5, iclass 40, count 0 2006.246.07:36:28.80#ibcon#read 5, iclass 40, count 0 2006.246.07:36:28.80#ibcon#about to read 6, iclass 40, count 0 2006.246.07:36:28.80#ibcon#read 6, iclass 40, count 0 2006.246.07:36:28.80#ibcon#end of sib2, iclass 40, count 0 2006.246.07:36:28.80#ibcon#*after write, iclass 40, count 0 2006.246.07:36:28.80#ibcon#*before return 0, iclass 40, count 0 2006.246.07:36:28.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:28.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:28.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:36:28.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:36:28.80$vc4f8/valo=4,832.99 2006.246.07:36:28.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.07:36:28.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.07:36:28.80#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:28.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:28.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:28.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:28.80#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:36:28.80#ibcon#first serial, iclass 4, count 0 2006.246.07:36:28.80#ibcon#enter sib2, iclass 4, count 0 2006.246.07:36:28.80#ibcon#flushed, iclass 4, count 0 2006.246.07:36:28.80#ibcon#about to write, iclass 4, count 0 2006.246.07:36:28.80#ibcon#wrote, iclass 4, count 0 2006.246.07:36:28.80#ibcon#about to read 3, iclass 4, count 0 2006.246.07:36:28.82#ibcon#read 3, iclass 4, count 0 2006.246.07:36:28.82#ibcon#about to read 4, iclass 4, count 0 2006.246.07:36:28.82#ibcon#read 4, iclass 4, count 0 2006.246.07:36:28.82#ibcon#about to read 5, iclass 4, count 0 2006.246.07:36:28.82#ibcon#read 5, iclass 4, count 0 2006.246.07:36:28.82#ibcon#about to read 6, iclass 4, count 0 2006.246.07:36:28.82#ibcon#read 6, iclass 4, count 0 2006.246.07:36:28.82#ibcon#end of sib2, iclass 4, count 0 2006.246.07:36:28.82#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:36:28.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:36:28.82#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:36:28.82#ibcon#*before write, iclass 4, count 0 2006.246.07:36:28.82#ibcon#enter sib2, iclass 4, count 0 2006.246.07:36:28.82#ibcon#flushed, iclass 4, count 0 2006.246.07:36:28.82#ibcon#about to write, iclass 4, count 0 2006.246.07:36:28.82#ibcon#wrote, iclass 4, count 0 2006.246.07:36:28.82#ibcon#about to read 3, iclass 4, count 0 2006.246.07:36:28.86#ibcon#read 3, iclass 4, count 0 2006.246.07:36:28.86#ibcon#about to read 4, iclass 4, count 0 2006.246.07:36:28.86#ibcon#read 4, iclass 4, count 0 2006.246.07:36:28.86#ibcon#about to read 5, iclass 4, count 0 2006.246.07:36:28.86#ibcon#read 5, iclass 4, count 0 2006.246.07:36:28.86#ibcon#about to read 6, iclass 4, count 0 2006.246.07:36:28.86#ibcon#read 6, iclass 4, count 0 2006.246.07:36:28.86#ibcon#end of sib2, iclass 4, count 0 2006.246.07:36:28.86#ibcon#*after write, iclass 4, count 0 2006.246.07:36:28.86#ibcon#*before return 0, iclass 4, count 0 2006.246.07:36:28.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:28.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:28.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:36:28.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:36:28.86$vc4f8/va=4,7 2006.246.07:36:28.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.07:36:28.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.07:36:28.86#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:28.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:28.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:28.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:28.92#ibcon#enter wrdev, iclass 6, count 2 2006.246.07:36:28.92#ibcon#first serial, iclass 6, count 2 2006.246.07:36:28.92#ibcon#enter sib2, iclass 6, count 2 2006.246.07:36:28.92#ibcon#flushed, iclass 6, count 2 2006.246.07:36:28.92#ibcon#about to write, iclass 6, count 2 2006.246.07:36:28.92#ibcon#wrote, iclass 6, count 2 2006.246.07:36:28.92#ibcon#about to read 3, iclass 6, count 2 2006.246.07:36:28.94#ibcon#read 3, iclass 6, count 2 2006.246.07:36:28.94#ibcon#about to read 4, iclass 6, count 2 2006.246.07:36:28.94#ibcon#read 4, iclass 6, count 2 2006.246.07:36:28.94#ibcon#about to read 5, iclass 6, count 2 2006.246.07:36:28.94#ibcon#read 5, iclass 6, count 2 2006.246.07:36:28.94#ibcon#about to read 6, iclass 6, count 2 2006.246.07:36:28.94#ibcon#read 6, iclass 6, count 2 2006.246.07:36:28.94#ibcon#end of sib2, iclass 6, count 2 2006.246.07:36:28.94#ibcon#*mode == 0, iclass 6, count 2 2006.246.07:36:28.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.07:36:28.94#ibcon#[25=AT04-07\r\n] 2006.246.07:36:28.94#ibcon#*before write, iclass 6, count 2 2006.246.07:36:28.94#ibcon#enter sib2, iclass 6, count 2 2006.246.07:36:28.94#ibcon#flushed, iclass 6, count 2 2006.246.07:36:28.94#ibcon#about to write, iclass 6, count 2 2006.246.07:36:28.94#ibcon#wrote, iclass 6, count 2 2006.246.07:36:28.94#ibcon#about to read 3, iclass 6, count 2 2006.246.07:36:28.97#ibcon#read 3, iclass 6, count 2 2006.246.07:36:28.97#ibcon#about to read 4, iclass 6, count 2 2006.246.07:36:28.97#ibcon#read 4, iclass 6, count 2 2006.246.07:36:28.97#ibcon#about to read 5, iclass 6, count 2 2006.246.07:36:28.97#ibcon#read 5, iclass 6, count 2 2006.246.07:36:28.97#ibcon#about to read 6, iclass 6, count 2 2006.246.07:36:28.97#ibcon#read 6, iclass 6, count 2 2006.246.07:36:28.97#ibcon#end of sib2, iclass 6, count 2 2006.246.07:36:28.97#ibcon#*after write, iclass 6, count 2 2006.246.07:36:28.97#ibcon#*before return 0, iclass 6, count 2 2006.246.07:36:28.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:28.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:28.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.07:36:28.97#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:28.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:29.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:29.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:29.09#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:36:29.09#ibcon#first serial, iclass 6, count 0 2006.246.07:36:29.09#ibcon#enter sib2, iclass 6, count 0 2006.246.07:36:29.09#ibcon#flushed, iclass 6, count 0 2006.246.07:36:29.09#ibcon#about to write, iclass 6, count 0 2006.246.07:36:29.09#ibcon#wrote, iclass 6, count 0 2006.246.07:36:29.09#ibcon#about to read 3, iclass 6, count 0 2006.246.07:36:29.11#ibcon#read 3, iclass 6, count 0 2006.246.07:36:29.11#ibcon#about to read 4, iclass 6, count 0 2006.246.07:36:29.11#ibcon#read 4, iclass 6, count 0 2006.246.07:36:29.11#ibcon#about to read 5, iclass 6, count 0 2006.246.07:36:29.11#ibcon#read 5, iclass 6, count 0 2006.246.07:36:29.11#ibcon#about to read 6, iclass 6, count 0 2006.246.07:36:29.11#ibcon#read 6, iclass 6, count 0 2006.246.07:36:29.11#ibcon#end of sib2, iclass 6, count 0 2006.246.07:36:29.11#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:36:29.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:36:29.11#ibcon#[25=USB\r\n] 2006.246.07:36:29.11#ibcon#*before write, iclass 6, count 0 2006.246.07:36:29.11#ibcon#enter sib2, iclass 6, count 0 2006.246.07:36:29.11#ibcon#flushed, iclass 6, count 0 2006.246.07:36:29.11#ibcon#about to write, iclass 6, count 0 2006.246.07:36:29.11#ibcon#wrote, iclass 6, count 0 2006.246.07:36:29.11#ibcon#about to read 3, iclass 6, count 0 2006.246.07:36:29.14#ibcon#read 3, iclass 6, count 0 2006.246.07:36:29.14#ibcon#about to read 4, iclass 6, count 0 2006.246.07:36:29.14#ibcon#read 4, iclass 6, count 0 2006.246.07:36:29.14#ibcon#about to read 5, iclass 6, count 0 2006.246.07:36:29.14#ibcon#read 5, iclass 6, count 0 2006.246.07:36:29.14#ibcon#about to read 6, iclass 6, count 0 2006.246.07:36:29.14#ibcon#read 6, iclass 6, count 0 2006.246.07:36:29.14#ibcon#end of sib2, iclass 6, count 0 2006.246.07:36:29.14#ibcon#*after write, iclass 6, count 0 2006.246.07:36:29.14#ibcon#*before return 0, iclass 6, count 0 2006.246.07:36:29.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:29.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:29.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:36:29.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:36:29.14$vc4f8/valo=5,652.99 2006.246.07:36:29.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.07:36:29.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.07:36:29.14#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:29.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:29.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:29.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:29.14#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:36:29.14#ibcon#first serial, iclass 10, count 0 2006.246.07:36:29.14#ibcon#enter sib2, iclass 10, count 0 2006.246.07:36:29.14#ibcon#flushed, iclass 10, count 0 2006.246.07:36:29.14#ibcon#about to write, iclass 10, count 0 2006.246.07:36:29.14#ibcon#wrote, iclass 10, count 0 2006.246.07:36:29.14#ibcon#about to read 3, iclass 10, count 0 2006.246.07:36:29.16#ibcon#read 3, iclass 10, count 0 2006.246.07:36:29.16#ibcon#about to read 4, iclass 10, count 0 2006.246.07:36:29.16#ibcon#read 4, iclass 10, count 0 2006.246.07:36:29.16#ibcon#about to read 5, iclass 10, count 0 2006.246.07:36:29.16#ibcon#read 5, iclass 10, count 0 2006.246.07:36:29.16#ibcon#about to read 6, iclass 10, count 0 2006.246.07:36:29.16#ibcon#read 6, iclass 10, count 0 2006.246.07:36:29.16#ibcon#end of sib2, iclass 10, count 0 2006.246.07:36:29.16#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:36:29.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:36:29.16#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:36:29.16#ibcon#*before write, iclass 10, count 0 2006.246.07:36:29.16#ibcon#enter sib2, iclass 10, count 0 2006.246.07:36:29.16#ibcon#flushed, iclass 10, count 0 2006.246.07:36:29.16#ibcon#about to write, iclass 10, count 0 2006.246.07:36:29.16#ibcon#wrote, iclass 10, count 0 2006.246.07:36:29.16#ibcon#about to read 3, iclass 10, count 0 2006.246.07:36:29.20#ibcon#read 3, iclass 10, count 0 2006.246.07:36:29.20#ibcon#about to read 4, iclass 10, count 0 2006.246.07:36:29.20#ibcon#read 4, iclass 10, count 0 2006.246.07:36:29.20#ibcon#about to read 5, iclass 10, count 0 2006.246.07:36:29.20#ibcon#read 5, iclass 10, count 0 2006.246.07:36:29.20#ibcon#about to read 6, iclass 10, count 0 2006.246.07:36:29.20#ibcon#read 6, iclass 10, count 0 2006.246.07:36:29.20#ibcon#end of sib2, iclass 10, count 0 2006.246.07:36:29.20#ibcon#*after write, iclass 10, count 0 2006.246.07:36:29.20#ibcon#*before return 0, iclass 10, count 0 2006.246.07:36:29.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:29.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:29.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:36:29.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:36:29.20$vc4f8/va=5,7 2006.246.07:36:29.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.07:36:29.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.07:36:29.20#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:29.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:29.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:29.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:29.26#ibcon#enter wrdev, iclass 12, count 2 2006.246.07:36:29.26#ibcon#first serial, iclass 12, count 2 2006.246.07:36:29.26#ibcon#enter sib2, iclass 12, count 2 2006.246.07:36:29.26#ibcon#flushed, iclass 12, count 2 2006.246.07:36:29.26#ibcon#about to write, iclass 12, count 2 2006.246.07:36:29.26#ibcon#wrote, iclass 12, count 2 2006.246.07:36:29.26#ibcon#about to read 3, iclass 12, count 2 2006.246.07:36:29.28#ibcon#read 3, iclass 12, count 2 2006.246.07:36:29.28#ibcon#about to read 4, iclass 12, count 2 2006.246.07:36:29.28#ibcon#read 4, iclass 12, count 2 2006.246.07:36:29.28#ibcon#about to read 5, iclass 12, count 2 2006.246.07:36:29.28#ibcon#read 5, iclass 12, count 2 2006.246.07:36:29.28#ibcon#about to read 6, iclass 12, count 2 2006.246.07:36:29.28#ibcon#read 6, iclass 12, count 2 2006.246.07:36:29.28#ibcon#end of sib2, iclass 12, count 2 2006.246.07:36:29.28#ibcon#*mode == 0, iclass 12, count 2 2006.246.07:36:29.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.07:36:29.28#ibcon#[25=AT05-07\r\n] 2006.246.07:36:29.28#ibcon#*before write, iclass 12, count 2 2006.246.07:36:29.28#ibcon#enter sib2, iclass 12, count 2 2006.246.07:36:29.28#ibcon#flushed, iclass 12, count 2 2006.246.07:36:29.28#ibcon#about to write, iclass 12, count 2 2006.246.07:36:29.28#ibcon#wrote, iclass 12, count 2 2006.246.07:36:29.28#ibcon#about to read 3, iclass 12, count 2 2006.246.07:36:29.31#ibcon#read 3, iclass 12, count 2 2006.246.07:36:29.31#ibcon#about to read 4, iclass 12, count 2 2006.246.07:36:29.31#ibcon#read 4, iclass 12, count 2 2006.246.07:36:29.31#ibcon#about to read 5, iclass 12, count 2 2006.246.07:36:29.31#ibcon#read 5, iclass 12, count 2 2006.246.07:36:29.31#ibcon#about to read 6, iclass 12, count 2 2006.246.07:36:29.31#ibcon#read 6, iclass 12, count 2 2006.246.07:36:29.31#ibcon#end of sib2, iclass 12, count 2 2006.246.07:36:29.31#ibcon#*after write, iclass 12, count 2 2006.246.07:36:29.31#ibcon#*before return 0, iclass 12, count 2 2006.246.07:36:29.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:29.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:29.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.07:36:29.31#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:29.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:29.36#abcon#<5=/04 3.8 7.4 26.78 721005.6\r\n> 2006.246.07:36:29.38#abcon#{5=INTERFACE CLEAR} 2006.246.07:36:29.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:29.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:29.43#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:36:29.43#ibcon#first serial, iclass 12, count 0 2006.246.07:36:29.43#ibcon#enter sib2, iclass 12, count 0 2006.246.07:36:29.43#ibcon#flushed, iclass 12, count 0 2006.246.07:36:29.43#ibcon#about to write, iclass 12, count 0 2006.246.07:36:29.43#ibcon#wrote, iclass 12, count 0 2006.246.07:36:29.43#ibcon#about to read 3, iclass 12, count 0 2006.246.07:36:29.44#abcon#[5=S1D000X0/0*\r\n] 2006.246.07:36:29.45#ibcon#read 3, iclass 12, count 0 2006.246.07:36:29.45#ibcon#about to read 4, iclass 12, count 0 2006.246.07:36:29.45#ibcon#read 4, iclass 12, count 0 2006.246.07:36:29.45#ibcon#about to read 5, iclass 12, count 0 2006.246.07:36:29.45#ibcon#read 5, iclass 12, count 0 2006.246.07:36:29.45#ibcon#about to read 6, iclass 12, count 0 2006.246.07:36:29.45#ibcon#read 6, iclass 12, count 0 2006.246.07:36:29.45#ibcon#end of sib2, iclass 12, count 0 2006.246.07:36:29.45#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:36:29.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:36:29.45#ibcon#[25=USB\r\n] 2006.246.07:36:29.45#ibcon#*before write, iclass 12, count 0 2006.246.07:36:29.45#ibcon#enter sib2, iclass 12, count 0 2006.246.07:36:29.45#ibcon#flushed, iclass 12, count 0 2006.246.07:36:29.45#ibcon#about to write, iclass 12, count 0 2006.246.07:36:29.45#ibcon#wrote, iclass 12, count 0 2006.246.07:36:29.45#ibcon#about to read 3, iclass 12, count 0 2006.246.07:36:29.48#ibcon#read 3, iclass 12, count 0 2006.246.07:36:29.48#ibcon#about to read 4, iclass 12, count 0 2006.246.07:36:29.48#ibcon#read 4, iclass 12, count 0 2006.246.07:36:29.48#ibcon#about to read 5, iclass 12, count 0 2006.246.07:36:29.48#ibcon#read 5, iclass 12, count 0 2006.246.07:36:29.48#ibcon#about to read 6, iclass 12, count 0 2006.246.07:36:29.48#ibcon#read 6, iclass 12, count 0 2006.246.07:36:29.48#ibcon#end of sib2, iclass 12, count 0 2006.246.07:36:29.48#ibcon#*after write, iclass 12, count 0 2006.246.07:36:29.48#ibcon#*before return 0, iclass 12, count 0 2006.246.07:36:29.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:29.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:29.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:36:29.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:36:29.48$vc4f8/valo=6,772.99 2006.246.07:36:29.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:36:29.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:36:29.48#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:29.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:29.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:29.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:29.48#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:36:29.48#ibcon#first serial, iclass 18, count 0 2006.246.07:36:29.48#ibcon#enter sib2, iclass 18, count 0 2006.246.07:36:29.48#ibcon#flushed, iclass 18, count 0 2006.246.07:36:29.48#ibcon#about to write, iclass 18, count 0 2006.246.07:36:29.48#ibcon#wrote, iclass 18, count 0 2006.246.07:36:29.48#ibcon#about to read 3, iclass 18, count 0 2006.246.07:36:29.50#ibcon#read 3, iclass 18, count 0 2006.246.07:36:29.50#ibcon#about to read 4, iclass 18, count 0 2006.246.07:36:29.50#ibcon#read 4, iclass 18, count 0 2006.246.07:36:29.50#ibcon#about to read 5, iclass 18, count 0 2006.246.07:36:29.50#ibcon#read 5, iclass 18, count 0 2006.246.07:36:29.50#ibcon#about to read 6, iclass 18, count 0 2006.246.07:36:29.50#ibcon#read 6, iclass 18, count 0 2006.246.07:36:29.50#ibcon#end of sib2, iclass 18, count 0 2006.246.07:36:29.50#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:36:29.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:36:29.50#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:36:29.50#ibcon#*before write, iclass 18, count 0 2006.246.07:36:29.50#ibcon#enter sib2, iclass 18, count 0 2006.246.07:36:29.50#ibcon#flushed, iclass 18, count 0 2006.246.07:36:29.50#ibcon#about to write, iclass 18, count 0 2006.246.07:36:29.50#ibcon#wrote, iclass 18, count 0 2006.246.07:36:29.50#ibcon#about to read 3, iclass 18, count 0 2006.246.07:36:29.54#ibcon#read 3, iclass 18, count 0 2006.246.07:36:29.54#ibcon#about to read 4, iclass 18, count 0 2006.246.07:36:29.54#ibcon#read 4, iclass 18, count 0 2006.246.07:36:29.54#ibcon#about to read 5, iclass 18, count 0 2006.246.07:36:29.54#ibcon#read 5, iclass 18, count 0 2006.246.07:36:29.54#ibcon#about to read 6, iclass 18, count 0 2006.246.07:36:29.54#ibcon#read 6, iclass 18, count 0 2006.246.07:36:29.54#ibcon#end of sib2, iclass 18, count 0 2006.246.07:36:29.54#ibcon#*after write, iclass 18, count 0 2006.246.07:36:29.54#ibcon#*before return 0, iclass 18, count 0 2006.246.07:36:29.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:29.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:29.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:36:29.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:36:29.54$vc4f8/va=6,7 2006.246.07:36:29.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.07:36:29.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.07:36:29.54#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:29.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:36:29.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:36:29.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:36:29.60#ibcon#enter wrdev, iclass 20, count 2 2006.246.07:36:29.60#ibcon#first serial, iclass 20, count 2 2006.246.07:36:29.60#ibcon#enter sib2, iclass 20, count 2 2006.246.07:36:29.60#ibcon#flushed, iclass 20, count 2 2006.246.07:36:29.60#ibcon#about to write, iclass 20, count 2 2006.246.07:36:29.60#ibcon#wrote, iclass 20, count 2 2006.246.07:36:29.60#ibcon#about to read 3, iclass 20, count 2 2006.246.07:36:29.62#ibcon#read 3, iclass 20, count 2 2006.246.07:36:29.62#ibcon#about to read 4, iclass 20, count 2 2006.246.07:36:29.62#ibcon#read 4, iclass 20, count 2 2006.246.07:36:29.62#ibcon#about to read 5, iclass 20, count 2 2006.246.07:36:29.62#ibcon#read 5, iclass 20, count 2 2006.246.07:36:29.62#ibcon#about to read 6, iclass 20, count 2 2006.246.07:36:29.62#ibcon#read 6, iclass 20, count 2 2006.246.07:36:29.62#ibcon#end of sib2, iclass 20, count 2 2006.246.07:36:29.62#ibcon#*mode == 0, iclass 20, count 2 2006.246.07:36:29.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.07:36:29.62#ibcon#[25=AT06-07\r\n] 2006.246.07:36:29.62#ibcon#*before write, iclass 20, count 2 2006.246.07:36:29.62#ibcon#enter sib2, iclass 20, count 2 2006.246.07:36:29.62#ibcon#flushed, iclass 20, count 2 2006.246.07:36:29.62#ibcon#about to write, iclass 20, count 2 2006.246.07:36:29.62#ibcon#wrote, iclass 20, count 2 2006.246.07:36:29.62#ibcon#about to read 3, iclass 20, count 2 2006.246.07:36:29.65#ibcon#read 3, iclass 20, count 2 2006.246.07:36:29.65#ibcon#about to read 4, iclass 20, count 2 2006.246.07:36:29.65#ibcon#read 4, iclass 20, count 2 2006.246.07:36:29.65#ibcon#about to read 5, iclass 20, count 2 2006.246.07:36:29.65#ibcon#read 5, iclass 20, count 2 2006.246.07:36:29.65#ibcon#about to read 6, iclass 20, count 2 2006.246.07:36:29.65#ibcon#read 6, iclass 20, count 2 2006.246.07:36:29.65#ibcon#end of sib2, iclass 20, count 2 2006.246.07:36:29.65#ibcon#*after write, iclass 20, count 2 2006.246.07:36:29.65#ibcon#*before return 0, iclass 20, count 2 2006.246.07:36:29.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:36:29.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:36:29.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.07:36:29.65#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:29.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:36:29.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:36:29.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:36:29.77#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:36:29.77#ibcon#first serial, iclass 20, count 0 2006.246.07:36:29.77#ibcon#enter sib2, iclass 20, count 0 2006.246.07:36:29.77#ibcon#flushed, iclass 20, count 0 2006.246.07:36:29.77#ibcon#about to write, iclass 20, count 0 2006.246.07:36:29.77#ibcon#wrote, iclass 20, count 0 2006.246.07:36:29.77#ibcon#about to read 3, iclass 20, count 0 2006.246.07:36:29.79#ibcon#read 3, iclass 20, count 0 2006.246.07:36:29.79#ibcon#about to read 4, iclass 20, count 0 2006.246.07:36:29.79#ibcon#read 4, iclass 20, count 0 2006.246.07:36:29.79#ibcon#about to read 5, iclass 20, count 0 2006.246.07:36:29.79#ibcon#read 5, iclass 20, count 0 2006.246.07:36:29.79#ibcon#about to read 6, iclass 20, count 0 2006.246.07:36:29.79#ibcon#read 6, iclass 20, count 0 2006.246.07:36:29.79#ibcon#end of sib2, iclass 20, count 0 2006.246.07:36:29.79#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:36:29.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:36:29.79#ibcon#[25=USB\r\n] 2006.246.07:36:29.79#ibcon#*before write, iclass 20, count 0 2006.246.07:36:29.79#ibcon#enter sib2, iclass 20, count 0 2006.246.07:36:29.79#ibcon#flushed, iclass 20, count 0 2006.246.07:36:29.79#ibcon#about to write, iclass 20, count 0 2006.246.07:36:29.79#ibcon#wrote, iclass 20, count 0 2006.246.07:36:29.79#ibcon#about to read 3, iclass 20, count 0 2006.246.07:36:29.82#ibcon#read 3, iclass 20, count 0 2006.246.07:36:29.82#ibcon#about to read 4, iclass 20, count 0 2006.246.07:36:29.82#ibcon#read 4, iclass 20, count 0 2006.246.07:36:29.82#ibcon#about to read 5, iclass 20, count 0 2006.246.07:36:29.82#ibcon#read 5, iclass 20, count 0 2006.246.07:36:29.82#ibcon#about to read 6, iclass 20, count 0 2006.246.07:36:29.82#ibcon#read 6, iclass 20, count 0 2006.246.07:36:29.82#ibcon#end of sib2, iclass 20, count 0 2006.246.07:36:29.82#ibcon#*after write, iclass 20, count 0 2006.246.07:36:29.82#ibcon#*before return 0, iclass 20, count 0 2006.246.07:36:29.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:36:29.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:36:29.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:36:29.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:36:29.82$vc4f8/valo=7,832.99 2006.246.07:36:29.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:36:29.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:36:29.82#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:29.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:36:29.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:36:29.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:36:29.82#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:36:29.82#ibcon#first serial, iclass 22, count 0 2006.246.07:36:29.82#ibcon#enter sib2, iclass 22, count 0 2006.246.07:36:29.82#ibcon#flushed, iclass 22, count 0 2006.246.07:36:29.82#ibcon#about to write, iclass 22, count 0 2006.246.07:36:29.82#ibcon#wrote, iclass 22, count 0 2006.246.07:36:29.82#ibcon#about to read 3, iclass 22, count 0 2006.246.07:36:29.84#ibcon#read 3, iclass 22, count 0 2006.246.07:36:29.84#ibcon#about to read 4, iclass 22, count 0 2006.246.07:36:29.84#ibcon#read 4, iclass 22, count 0 2006.246.07:36:29.84#ibcon#about to read 5, iclass 22, count 0 2006.246.07:36:29.84#ibcon#read 5, iclass 22, count 0 2006.246.07:36:29.84#ibcon#about to read 6, iclass 22, count 0 2006.246.07:36:29.84#ibcon#read 6, iclass 22, count 0 2006.246.07:36:29.84#ibcon#end of sib2, iclass 22, count 0 2006.246.07:36:29.84#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:36:29.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:36:29.84#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:36:29.84#ibcon#*before write, iclass 22, count 0 2006.246.07:36:29.84#ibcon#enter sib2, iclass 22, count 0 2006.246.07:36:29.84#ibcon#flushed, iclass 22, count 0 2006.246.07:36:29.84#ibcon#about to write, iclass 22, count 0 2006.246.07:36:29.84#ibcon#wrote, iclass 22, count 0 2006.246.07:36:29.84#ibcon#about to read 3, iclass 22, count 0 2006.246.07:36:29.88#ibcon#read 3, iclass 22, count 0 2006.246.07:36:29.88#ibcon#about to read 4, iclass 22, count 0 2006.246.07:36:29.88#ibcon#read 4, iclass 22, count 0 2006.246.07:36:29.88#ibcon#about to read 5, iclass 22, count 0 2006.246.07:36:29.88#ibcon#read 5, iclass 22, count 0 2006.246.07:36:29.88#ibcon#about to read 6, iclass 22, count 0 2006.246.07:36:29.88#ibcon#read 6, iclass 22, count 0 2006.246.07:36:29.88#ibcon#end of sib2, iclass 22, count 0 2006.246.07:36:29.88#ibcon#*after write, iclass 22, count 0 2006.246.07:36:29.88#ibcon#*before return 0, iclass 22, count 0 2006.246.07:36:29.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:36:29.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:36:29.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:36:29.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:36:29.88$vc4f8/va=7,7 2006.246.07:36:29.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.07:36:29.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.07:36:29.88#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:29.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:36:29.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:36:29.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:36:29.94#ibcon#enter wrdev, iclass 24, count 2 2006.246.07:36:29.94#ibcon#first serial, iclass 24, count 2 2006.246.07:36:29.94#ibcon#enter sib2, iclass 24, count 2 2006.246.07:36:29.94#ibcon#flushed, iclass 24, count 2 2006.246.07:36:29.94#ibcon#about to write, iclass 24, count 2 2006.246.07:36:29.94#ibcon#wrote, iclass 24, count 2 2006.246.07:36:29.94#ibcon#about to read 3, iclass 24, count 2 2006.246.07:36:29.96#ibcon#read 3, iclass 24, count 2 2006.246.07:36:29.96#ibcon#about to read 4, iclass 24, count 2 2006.246.07:36:29.96#ibcon#read 4, iclass 24, count 2 2006.246.07:36:29.96#ibcon#about to read 5, iclass 24, count 2 2006.246.07:36:29.96#ibcon#read 5, iclass 24, count 2 2006.246.07:36:29.96#ibcon#about to read 6, iclass 24, count 2 2006.246.07:36:29.96#ibcon#read 6, iclass 24, count 2 2006.246.07:36:29.96#ibcon#end of sib2, iclass 24, count 2 2006.246.07:36:29.96#ibcon#*mode == 0, iclass 24, count 2 2006.246.07:36:29.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.07:36:29.96#ibcon#[25=AT07-07\r\n] 2006.246.07:36:29.96#ibcon#*before write, iclass 24, count 2 2006.246.07:36:29.96#ibcon#enter sib2, iclass 24, count 2 2006.246.07:36:29.96#ibcon#flushed, iclass 24, count 2 2006.246.07:36:29.96#ibcon#about to write, iclass 24, count 2 2006.246.07:36:29.96#ibcon#wrote, iclass 24, count 2 2006.246.07:36:29.96#ibcon#about to read 3, iclass 24, count 2 2006.246.07:36:29.99#ibcon#read 3, iclass 24, count 2 2006.246.07:36:29.99#ibcon#about to read 4, iclass 24, count 2 2006.246.07:36:29.99#ibcon#read 4, iclass 24, count 2 2006.246.07:36:29.99#ibcon#about to read 5, iclass 24, count 2 2006.246.07:36:29.99#ibcon#read 5, iclass 24, count 2 2006.246.07:36:29.99#ibcon#about to read 6, iclass 24, count 2 2006.246.07:36:29.99#ibcon#read 6, iclass 24, count 2 2006.246.07:36:29.99#ibcon#end of sib2, iclass 24, count 2 2006.246.07:36:29.99#ibcon#*after write, iclass 24, count 2 2006.246.07:36:29.99#ibcon#*before return 0, iclass 24, count 2 2006.246.07:36:29.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:36:29.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:36:29.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.07:36:29.99#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:29.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:36:30.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:36:30.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:36:30.11#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:36:30.11#ibcon#first serial, iclass 24, count 0 2006.246.07:36:30.11#ibcon#enter sib2, iclass 24, count 0 2006.246.07:36:30.11#ibcon#flushed, iclass 24, count 0 2006.246.07:36:30.11#ibcon#about to write, iclass 24, count 0 2006.246.07:36:30.11#ibcon#wrote, iclass 24, count 0 2006.246.07:36:30.11#ibcon#about to read 3, iclass 24, count 0 2006.246.07:36:30.13#ibcon#read 3, iclass 24, count 0 2006.246.07:36:30.13#ibcon#about to read 4, iclass 24, count 0 2006.246.07:36:30.13#ibcon#read 4, iclass 24, count 0 2006.246.07:36:30.13#ibcon#about to read 5, iclass 24, count 0 2006.246.07:36:30.13#ibcon#read 5, iclass 24, count 0 2006.246.07:36:30.13#ibcon#about to read 6, iclass 24, count 0 2006.246.07:36:30.13#ibcon#read 6, iclass 24, count 0 2006.246.07:36:30.13#ibcon#end of sib2, iclass 24, count 0 2006.246.07:36:30.13#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:36:30.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:36:30.13#ibcon#[25=USB\r\n] 2006.246.07:36:30.13#ibcon#*before write, iclass 24, count 0 2006.246.07:36:30.13#ibcon#enter sib2, iclass 24, count 0 2006.246.07:36:30.13#ibcon#flushed, iclass 24, count 0 2006.246.07:36:30.13#ibcon#about to write, iclass 24, count 0 2006.246.07:36:30.13#ibcon#wrote, iclass 24, count 0 2006.246.07:36:30.13#ibcon#about to read 3, iclass 24, count 0 2006.246.07:36:30.16#ibcon#read 3, iclass 24, count 0 2006.246.07:36:30.16#ibcon#about to read 4, iclass 24, count 0 2006.246.07:36:30.16#ibcon#read 4, iclass 24, count 0 2006.246.07:36:30.16#ibcon#about to read 5, iclass 24, count 0 2006.246.07:36:30.16#ibcon#read 5, iclass 24, count 0 2006.246.07:36:30.16#ibcon#about to read 6, iclass 24, count 0 2006.246.07:36:30.16#ibcon#read 6, iclass 24, count 0 2006.246.07:36:30.16#ibcon#end of sib2, iclass 24, count 0 2006.246.07:36:30.16#ibcon#*after write, iclass 24, count 0 2006.246.07:36:30.16#ibcon#*before return 0, iclass 24, count 0 2006.246.07:36:30.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:36:30.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:36:30.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:36:30.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:36:30.16$vc4f8/valo=8,852.99 2006.246.07:36:30.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:36:30.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:36:30.16#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:30.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:36:30.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:36:30.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:36:30.16#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:36:30.16#ibcon#first serial, iclass 26, count 0 2006.246.07:36:30.16#ibcon#enter sib2, iclass 26, count 0 2006.246.07:36:30.16#ibcon#flushed, iclass 26, count 0 2006.246.07:36:30.16#ibcon#about to write, iclass 26, count 0 2006.246.07:36:30.16#ibcon#wrote, iclass 26, count 0 2006.246.07:36:30.16#ibcon#about to read 3, iclass 26, count 0 2006.246.07:36:30.18#ibcon#read 3, iclass 26, count 0 2006.246.07:36:30.18#ibcon#about to read 4, iclass 26, count 0 2006.246.07:36:30.18#ibcon#read 4, iclass 26, count 0 2006.246.07:36:30.18#ibcon#about to read 5, iclass 26, count 0 2006.246.07:36:30.18#ibcon#read 5, iclass 26, count 0 2006.246.07:36:30.18#ibcon#about to read 6, iclass 26, count 0 2006.246.07:36:30.18#ibcon#read 6, iclass 26, count 0 2006.246.07:36:30.18#ibcon#end of sib2, iclass 26, count 0 2006.246.07:36:30.18#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:36:30.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:36:30.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:36:30.18#ibcon#*before write, iclass 26, count 0 2006.246.07:36:30.18#ibcon#enter sib2, iclass 26, count 0 2006.246.07:36:30.18#ibcon#flushed, iclass 26, count 0 2006.246.07:36:30.18#ibcon#about to write, iclass 26, count 0 2006.246.07:36:30.18#ibcon#wrote, iclass 26, count 0 2006.246.07:36:30.18#ibcon#about to read 3, iclass 26, count 0 2006.246.07:36:30.22#ibcon#read 3, iclass 26, count 0 2006.246.07:36:30.22#ibcon#about to read 4, iclass 26, count 0 2006.246.07:36:30.22#ibcon#read 4, iclass 26, count 0 2006.246.07:36:30.22#ibcon#about to read 5, iclass 26, count 0 2006.246.07:36:30.22#ibcon#read 5, iclass 26, count 0 2006.246.07:36:30.22#ibcon#about to read 6, iclass 26, count 0 2006.246.07:36:30.22#ibcon#read 6, iclass 26, count 0 2006.246.07:36:30.22#ibcon#end of sib2, iclass 26, count 0 2006.246.07:36:30.22#ibcon#*after write, iclass 26, count 0 2006.246.07:36:30.22#ibcon#*before return 0, iclass 26, count 0 2006.246.07:36:30.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:36:30.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:36:30.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:36:30.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:36:30.22$vc4f8/va=8,8 2006.246.07:36:30.22#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:36:30.22#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:36:30.22#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:30.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:36:30.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:36:30.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:36:30.28#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:36:30.28#ibcon#first serial, iclass 28, count 2 2006.246.07:36:30.28#ibcon#enter sib2, iclass 28, count 2 2006.246.07:36:30.28#ibcon#flushed, iclass 28, count 2 2006.246.07:36:30.28#ibcon#about to write, iclass 28, count 2 2006.246.07:36:30.28#ibcon#wrote, iclass 28, count 2 2006.246.07:36:30.28#ibcon#about to read 3, iclass 28, count 2 2006.246.07:36:30.30#ibcon#read 3, iclass 28, count 2 2006.246.07:36:30.30#ibcon#about to read 4, iclass 28, count 2 2006.246.07:36:30.30#ibcon#read 4, iclass 28, count 2 2006.246.07:36:30.30#ibcon#about to read 5, iclass 28, count 2 2006.246.07:36:30.30#ibcon#read 5, iclass 28, count 2 2006.246.07:36:30.30#ibcon#about to read 6, iclass 28, count 2 2006.246.07:36:30.30#ibcon#read 6, iclass 28, count 2 2006.246.07:36:30.30#ibcon#end of sib2, iclass 28, count 2 2006.246.07:36:30.30#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:36:30.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:36:30.30#ibcon#[25=AT08-08\r\n] 2006.246.07:36:30.30#ibcon#*before write, iclass 28, count 2 2006.246.07:36:30.30#ibcon#enter sib2, iclass 28, count 2 2006.246.07:36:30.30#ibcon#flushed, iclass 28, count 2 2006.246.07:36:30.30#ibcon#about to write, iclass 28, count 2 2006.246.07:36:30.30#ibcon#wrote, iclass 28, count 2 2006.246.07:36:30.30#ibcon#about to read 3, iclass 28, count 2 2006.246.07:36:30.33#ibcon#read 3, iclass 28, count 2 2006.246.07:36:30.33#ibcon#about to read 4, iclass 28, count 2 2006.246.07:36:30.33#ibcon#read 4, iclass 28, count 2 2006.246.07:36:30.33#ibcon#about to read 5, iclass 28, count 2 2006.246.07:36:30.33#ibcon#read 5, iclass 28, count 2 2006.246.07:36:30.33#ibcon#about to read 6, iclass 28, count 2 2006.246.07:36:30.33#ibcon#read 6, iclass 28, count 2 2006.246.07:36:30.33#ibcon#end of sib2, iclass 28, count 2 2006.246.07:36:30.33#ibcon#*after write, iclass 28, count 2 2006.246.07:36:30.33#ibcon#*before return 0, iclass 28, count 2 2006.246.07:36:30.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:36:30.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:36:30.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:36:30.33#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:30.33#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:36:30.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:36:30.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:36:30.45#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:36:30.45#ibcon#first serial, iclass 28, count 0 2006.246.07:36:30.45#ibcon#enter sib2, iclass 28, count 0 2006.246.07:36:30.45#ibcon#flushed, iclass 28, count 0 2006.246.07:36:30.45#ibcon#about to write, iclass 28, count 0 2006.246.07:36:30.45#ibcon#wrote, iclass 28, count 0 2006.246.07:36:30.45#ibcon#about to read 3, iclass 28, count 0 2006.246.07:36:30.47#ibcon#read 3, iclass 28, count 0 2006.246.07:36:30.47#ibcon#about to read 4, iclass 28, count 0 2006.246.07:36:30.47#ibcon#read 4, iclass 28, count 0 2006.246.07:36:30.47#ibcon#about to read 5, iclass 28, count 0 2006.246.07:36:30.47#ibcon#read 5, iclass 28, count 0 2006.246.07:36:30.47#ibcon#about to read 6, iclass 28, count 0 2006.246.07:36:30.47#ibcon#read 6, iclass 28, count 0 2006.246.07:36:30.47#ibcon#end of sib2, iclass 28, count 0 2006.246.07:36:30.47#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:36:30.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:36:30.47#ibcon#[25=USB\r\n] 2006.246.07:36:30.47#ibcon#*before write, iclass 28, count 0 2006.246.07:36:30.47#ibcon#enter sib2, iclass 28, count 0 2006.246.07:36:30.47#ibcon#flushed, iclass 28, count 0 2006.246.07:36:30.47#ibcon#about to write, iclass 28, count 0 2006.246.07:36:30.47#ibcon#wrote, iclass 28, count 0 2006.246.07:36:30.47#ibcon#about to read 3, iclass 28, count 0 2006.246.07:36:30.50#ibcon#read 3, iclass 28, count 0 2006.246.07:36:30.50#ibcon#about to read 4, iclass 28, count 0 2006.246.07:36:30.50#ibcon#read 4, iclass 28, count 0 2006.246.07:36:30.50#ibcon#about to read 5, iclass 28, count 0 2006.246.07:36:30.50#ibcon#read 5, iclass 28, count 0 2006.246.07:36:30.50#ibcon#about to read 6, iclass 28, count 0 2006.246.07:36:30.50#ibcon#read 6, iclass 28, count 0 2006.246.07:36:30.50#ibcon#end of sib2, iclass 28, count 0 2006.246.07:36:30.50#ibcon#*after write, iclass 28, count 0 2006.246.07:36:30.50#ibcon#*before return 0, iclass 28, count 0 2006.246.07:36:30.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:36:30.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:36:30.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:36:30.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:36:30.50$vc4f8/vblo=1,632.99 2006.246.07:36:30.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:36:30.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:36:30.50#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:30.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:30.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:30.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:30.50#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:36:30.50#ibcon#first serial, iclass 30, count 0 2006.246.07:36:30.50#ibcon#enter sib2, iclass 30, count 0 2006.246.07:36:30.50#ibcon#flushed, iclass 30, count 0 2006.246.07:36:30.50#ibcon#about to write, iclass 30, count 0 2006.246.07:36:30.50#ibcon#wrote, iclass 30, count 0 2006.246.07:36:30.50#ibcon#about to read 3, iclass 30, count 0 2006.246.07:36:30.52#ibcon#read 3, iclass 30, count 0 2006.246.07:36:30.52#ibcon#about to read 4, iclass 30, count 0 2006.246.07:36:30.52#ibcon#read 4, iclass 30, count 0 2006.246.07:36:30.52#ibcon#about to read 5, iclass 30, count 0 2006.246.07:36:30.52#ibcon#read 5, iclass 30, count 0 2006.246.07:36:30.52#ibcon#about to read 6, iclass 30, count 0 2006.246.07:36:30.52#ibcon#read 6, iclass 30, count 0 2006.246.07:36:30.52#ibcon#end of sib2, iclass 30, count 0 2006.246.07:36:30.52#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:36:30.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:36:30.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:36:30.52#ibcon#*before write, iclass 30, count 0 2006.246.07:36:30.52#ibcon#enter sib2, iclass 30, count 0 2006.246.07:36:30.52#ibcon#flushed, iclass 30, count 0 2006.246.07:36:30.52#ibcon#about to write, iclass 30, count 0 2006.246.07:36:30.52#ibcon#wrote, iclass 30, count 0 2006.246.07:36:30.52#ibcon#about to read 3, iclass 30, count 0 2006.246.07:36:30.56#ibcon#read 3, iclass 30, count 0 2006.246.07:36:30.56#ibcon#about to read 4, iclass 30, count 0 2006.246.07:36:30.56#ibcon#read 4, iclass 30, count 0 2006.246.07:36:30.56#ibcon#about to read 5, iclass 30, count 0 2006.246.07:36:30.56#ibcon#read 5, iclass 30, count 0 2006.246.07:36:30.56#ibcon#about to read 6, iclass 30, count 0 2006.246.07:36:30.56#ibcon#read 6, iclass 30, count 0 2006.246.07:36:30.56#ibcon#end of sib2, iclass 30, count 0 2006.246.07:36:30.56#ibcon#*after write, iclass 30, count 0 2006.246.07:36:30.56#ibcon#*before return 0, iclass 30, count 0 2006.246.07:36:30.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:30.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:36:30.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:36:30.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:36:30.56$vc4f8/vb=1,4 2006.246.07:36:30.56#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:36:30.56#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:36:30.56#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:30.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:30.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:30.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:30.56#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:36:30.56#ibcon#first serial, iclass 32, count 2 2006.246.07:36:30.56#ibcon#enter sib2, iclass 32, count 2 2006.246.07:36:30.56#ibcon#flushed, iclass 32, count 2 2006.246.07:36:30.56#ibcon#about to write, iclass 32, count 2 2006.246.07:36:30.56#ibcon#wrote, iclass 32, count 2 2006.246.07:36:30.56#ibcon#about to read 3, iclass 32, count 2 2006.246.07:36:30.58#ibcon#read 3, iclass 32, count 2 2006.246.07:36:30.58#ibcon#about to read 4, iclass 32, count 2 2006.246.07:36:30.58#ibcon#read 4, iclass 32, count 2 2006.246.07:36:30.58#ibcon#about to read 5, iclass 32, count 2 2006.246.07:36:30.58#ibcon#read 5, iclass 32, count 2 2006.246.07:36:30.58#ibcon#about to read 6, iclass 32, count 2 2006.246.07:36:30.58#ibcon#read 6, iclass 32, count 2 2006.246.07:36:30.58#ibcon#end of sib2, iclass 32, count 2 2006.246.07:36:30.58#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:36:30.58#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:36:30.58#ibcon#[27=AT01-04\r\n] 2006.246.07:36:30.58#ibcon#*before write, iclass 32, count 2 2006.246.07:36:30.58#ibcon#enter sib2, iclass 32, count 2 2006.246.07:36:30.58#ibcon#flushed, iclass 32, count 2 2006.246.07:36:30.58#ibcon#about to write, iclass 32, count 2 2006.246.07:36:30.58#ibcon#wrote, iclass 32, count 2 2006.246.07:36:30.58#ibcon#about to read 3, iclass 32, count 2 2006.246.07:36:30.61#ibcon#read 3, iclass 32, count 2 2006.246.07:36:30.61#ibcon#about to read 4, iclass 32, count 2 2006.246.07:36:30.61#ibcon#read 4, iclass 32, count 2 2006.246.07:36:30.61#ibcon#about to read 5, iclass 32, count 2 2006.246.07:36:30.61#ibcon#read 5, iclass 32, count 2 2006.246.07:36:30.61#ibcon#about to read 6, iclass 32, count 2 2006.246.07:36:30.61#ibcon#read 6, iclass 32, count 2 2006.246.07:36:30.61#ibcon#end of sib2, iclass 32, count 2 2006.246.07:36:30.61#ibcon#*after write, iclass 32, count 2 2006.246.07:36:30.61#ibcon#*before return 0, iclass 32, count 2 2006.246.07:36:30.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:30.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:36:30.61#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:36:30.61#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:30.61#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:30.73#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:30.73#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:30.73#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:36:30.73#ibcon#first serial, iclass 32, count 0 2006.246.07:36:30.73#ibcon#enter sib2, iclass 32, count 0 2006.246.07:36:30.73#ibcon#flushed, iclass 32, count 0 2006.246.07:36:30.73#ibcon#about to write, iclass 32, count 0 2006.246.07:36:30.73#ibcon#wrote, iclass 32, count 0 2006.246.07:36:30.73#ibcon#about to read 3, iclass 32, count 0 2006.246.07:36:30.75#ibcon#read 3, iclass 32, count 0 2006.246.07:36:30.75#ibcon#about to read 4, iclass 32, count 0 2006.246.07:36:30.75#ibcon#read 4, iclass 32, count 0 2006.246.07:36:30.75#ibcon#about to read 5, iclass 32, count 0 2006.246.07:36:30.75#ibcon#read 5, iclass 32, count 0 2006.246.07:36:30.75#ibcon#about to read 6, iclass 32, count 0 2006.246.07:36:30.75#ibcon#read 6, iclass 32, count 0 2006.246.07:36:30.75#ibcon#end of sib2, iclass 32, count 0 2006.246.07:36:30.75#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:36:30.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:36:30.75#ibcon#[27=USB\r\n] 2006.246.07:36:30.75#ibcon#*before write, iclass 32, count 0 2006.246.07:36:30.75#ibcon#enter sib2, iclass 32, count 0 2006.246.07:36:30.75#ibcon#flushed, iclass 32, count 0 2006.246.07:36:30.75#ibcon#about to write, iclass 32, count 0 2006.246.07:36:30.75#ibcon#wrote, iclass 32, count 0 2006.246.07:36:30.75#ibcon#about to read 3, iclass 32, count 0 2006.246.07:36:30.78#ibcon#read 3, iclass 32, count 0 2006.246.07:36:30.78#ibcon#about to read 4, iclass 32, count 0 2006.246.07:36:30.78#ibcon#read 4, iclass 32, count 0 2006.246.07:36:30.78#ibcon#about to read 5, iclass 32, count 0 2006.246.07:36:30.78#ibcon#read 5, iclass 32, count 0 2006.246.07:36:30.78#ibcon#about to read 6, iclass 32, count 0 2006.246.07:36:30.78#ibcon#read 6, iclass 32, count 0 2006.246.07:36:30.78#ibcon#end of sib2, iclass 32, count 0 2006.246.07:36:30.78#ibcon#*after write, iclass 32, count 0 2006.246.07:36:30.78#ibcon#*before return 0, iclass 32, count 0 2006.246.07:36:30.78#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:30.78#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:36:30.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:36:30.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:36:30.78$vc4f8/vblo=2,640.99 2006.246.07:36:30.78#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:36:30.78#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:36:30.78#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:30.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:30.78#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:30.78#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:30.78#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:36:30.78#ibcon#first serial, iclass 34, count 0 2006.246.07:36:30.78#ibcon#enter sib2, iclass 34, count 0 2006.246.07:36:30.78#ibcon#flushed, iclass 34, count 0 2006.246.07:36:30.78#ibcon#about to write, iclass 34, count 0 2006.246.07:36:30.78#ibcon#wrote, iclass 34, count 0 2006.246.07:36:30.78#ibcon#about to read 3, iclass 34, count 0 2006.246.07:36:30.80#ibcon#read 3, iclass 34, count 0 2006.246.07:36:30.80#ibcon#about to read 4, iclass 34, count 0 2006.246.07:36:30.80#ibcon#read 4, iclass 34, count 0 2006.246.07:36:30.80#ibcon#about to read 5, iclass 34, count 0 2006.246.07:36:30.80#ibcon#read 5, iclass 34, count 0 2006.246.07:36:30.80#ibcon#about to read 6, iclass 34, count 0 2006.246.07:36:30.80#ibcon#read 6, iclass 34, count 0 2006.246.07:36:30.80#ibcon#end of sib2, iclass 34, count 0 2006.246.07:36:30.80#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:36:30.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:36:30.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:36:30.80#ibcon#*before write, iclass 34, count 0 2006.246.07:36:30.80#ibcon#enter sib2, iclass 34, count 0 2006.246.07:36:30.80#ibcon#flushed, iclass 34, count 0 2006.246.07:36:30.80#ibcon#about to write, iclass 34, count 0 2006.246.07:36:30.80#ibcon#wrote, iclass 34, count 0 2006.246.07:36:30.80#ibcon#about to read 3, iclass 34, count 0 2006.246.07:36:30.84#ibcon#read 3, iclass 34, count 0 2006.246.07:36:30.84#ibcon#about to read 4, iclass 34, count 0 2006.246.07:36:30.84#ibcon#read 4, iclass 34, count 0 2006.246.07:36:30.84#ibcon#about to read 5, iclass 34, count 0 2006.246.07:36:30.84#ibcon#read 5, iclass 34, count 0 2006.246.07:36:30.84#ibcon#about to read 6, iclass 34, count 0 2006.246.07:36:30.84#ibcon#read 6, iclass 34, count 0 2006.246.07:36:30.84#ibcon#end of sib2, iclass 34, count 0 2006.246.07:36:30.84#ibcon#*after write, iclass 34, count 0 2006.246.07:36:30.84#ibcon#*before return 0, iclass 34, count 0 2006.246.07:36:30.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:30.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:36:30.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:36:30.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:36:30.84$vc4f8/vb=2,4 2006.246.07:36:30.84#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:36:30.84#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:36:30.84#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:30.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:30.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:30.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:30.90#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:36:30.90#ibcon#first serial, iclass 36, count 2 2006.246.07:36:30.90#ibcon#enter sib2, iclass 36, count 2 2006.246.07:36:30.90#ibcon#flushed, iclass 36, count 2 2006.246.07:36:30.90#ibcon#about to write, iclass 36, count 2 2006.246.07:36:30.90#ibcon#wrote, iclass 36, count 2 2006.246.07:36:30.90#ibcon#about to read 3, iclass 36, count 2 2006.246.07:36:30.92#ibcon#read 3, iclass 36, count 2 2006.246.07:36:30.92#ibcon#about to read 4, iclass 36, count 2 2006.246.07:36:30.92#ibcon#read 4, iclass 36, count 2 2006.246.07:36:30.92#ibcon#about to read 5, iclass 36, count 2 2006.246.07:36:30.92#ibcon#read 5, iclass 36, count 2 2006.246.07:36:30.92#ibcon#about to read 6, iclass 36, count 2 2006.246.07:36:30.92#ibcon#read 6, iclass 36, count 2 2006.246.07:36:30.92#ibcon#end of sib2, iclass 36, count 2 2006.246.07:36:30.92#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:36:30.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:36:30.92#ibcon#[27=AT02-04\r\n] 2006.246.07:36:30.92#ibcon#*before write, iclass 36, count 2 2006.246.07:36:30.92#ibcon#enter sib2, iclass 36, count 2 2006.246.07:36:30.92#ibcon#flushed, iclass 36, count 2 2006.246.07:36:30.92#ibcon#about to write, iclass 36, count 2 2006.246.07:36:30.92#ibcon#wrote, iclass 36, count 2 2006.246.07:36:30.92#ibcon#about to read 3, iclass 36, count 2 2006.246.07:36:30.95#ibcon#read 3, iclass 36, count 2 2006.246.07:36:30.95#ibcon#about to read 4, iclass 36, count 2 2006.246.07:36:30.95#ibcon#read 4, iclass 36, count 2 2006.246.07:36:30.95#ibcon#about to read 5, iclass 36, count 2 2006.246.07:36:30.95#ibcon#read 5, iclass 36, count 2 2006.246.07:36:30.95#ibcon#about to read 6, iclass 36, count 2 2006.246.07:36:30.95#ibcon#read 6, iclass 36, count 2 2006.246.07:36:30.95#ibcon#end of sib2, iclass 36, count 2 2006.246.07:36:30.95#ibcon#*after write, iclass 36, count 2 2006.246.07:36:30.95#ibcon#*before return 0, iclass 36, count 2 2006.246.07:36:30.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:30.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:36:30.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:36:30.95#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:30.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:31.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:31.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:31.07#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:36:31.07#ibcon#first serial, iclass 36, count 0 2006.246.07:36:31.07#ibcon#enter sib2, iclass 36, count 0 2006.246.07:36:31.07#ibcon#flushed, iclass 36, count 0 2006.246.07:36:31.07#ibcon#about to write, iclass 36, count 0 2006.246.07:36:31.07#ibcon#wrote, iclass 36, count 0 2006.246.07:36:31.07#ibcon#about to read 3, iclass 36, count 0 2006.246.07:36:31.09#ibcon#read 3, iclass 36, count 0 2006.246.07:36:31.09#ibcon#about to read 4, iclass 36, count 0 2006.246.07:36:31.09#ibcon#read 4, iclass 36, count 0 2006.246.07:36:31.09#ibcon#about to read 5, iclass 36, count 0 2006.246.07:36:31.09#ibcon#read 5, iclass 36, count 0 2006.246.07:36:31.09#ibcon#about to read 6, iclass 36, count 0 2006.246.07:36:31.09#ibcon#read 6, iclass 36, count 0 2006.246.07:36:31.09#ibcon#end of sib2, iclass 36, count 0 2006.246.07:36:31.09#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:36:31.09#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:36:31.09#ibcon#[27=USB\r\n] 2006.246.07:36:31.09#ibcon#*before write, iclass 36, count 0 2006.246.07:36:31.09#ibcon#enter sib2, iclass 36, count 0 2006.246.07:36:31.09#ibcon#flushed, iclass 36, count 0 2006.246.07:36:31.09#ibcon#about to write, iclass 36, count 0 2006.246.07:36:31.09#ibcon#wrote, iclass 36, count 0 2006.246.07:36:31.09#ibcon#about to read 3, iclass 36, count 0 2006.246.07:36:31.12#ibcon#read 3, iclass 36, count 0 2006.246.07:36:31.12#ibcon#about to read 4, iclass 36, count 0 2006.246.07:36:31.12#ibcon#read 4, iclass 36, count 0 2006.246.07:36:31.12#ibcon#about to read 5, iclass 36, count 0 2006.246.07:36:31.12#ibcon#read 5, iclass 36, count 0 2006.246.07:36:31.12#ibcon#about to read 6, iclass 36, count 0 2006.246.07:36:31.12#ibcon#read 6, iclass 36, count 0 2006.246.07:36:31.12#ibcon#end of sib2, iclass 36, count 0 2006.246.07:36:31.12#ibcon#*after write, iclass 36, count 0 2006.246.07:36:31.12#ibcon#*before return 0, iclass 36, count 0 2006.246.07:36:31.12#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:31.12#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:36:31.12#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:36:31.12#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:36:31.12$vc4f8/vblo=3,656.99 2006.246.07:36:31.12#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:36:31.12#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:36:31.12#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:31.12#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:31.12#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:31.12#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:31.12#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:36:31.12#ibcon#first serial, iclass 38, count 0 2006.246.07:36:31.12#ibcon#enter sib2, iclass 38, count 0 2006.246.07:36:31.12#ibcon#flushed, iclass 38, count 0 2006.246.07:36:31.12#ibcon#about to write, iclass 38, count 0 2006.246.07:36:31.12#ibcon#wrote, iclass 38, count 0 2006.246.07:36:31.12#ibcon#about to read 3, iclass 38, count 0 2006.246.07:36:31.14#ibcon#read 3, iclass 38, count 0 2006.246.07:36:31.14#ibcon#about to read 4, iclass 38, count 0 2006.246.07:36:31.14#ibcon#read 4, iclass 38, count 0 2006.246.07:36:31.14#ibcon#about to read 5, iclass 38, count 0 2006.246.07:36:31.14#ibcon#read 5, iclass 38, count 0 2006.246.07:36:31.14#ibcon#about to read 6, iclass 38, count 0 2006.246.07:36:31.14#ibcon#read 6, iclass 38, count 0 2006.246.07:36:31.14#ibcon#end of sib2, iclass 38, count 0 2006.246.07:36:31.14#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:36:31.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:36:31.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:36:31.14#ibcon#*before write, iclass 38, count 0 2006.246.07:36:31.14#ibcon#enter sib2, iclass 38, count 0 2006.246.07:36:31.14#ibcon#flushed, iclass 38, count 0 2006.246.07:36:31.14#ibcon#about to write, iclass 38, count 0 2006.246.07:36:31.14#ibcon#wrote, iclass 38, count 0 2006.246.07:36:31.14#ibcon#about to read 3, iclass 38, count 0 2006.246.07:36:31.18#ibcon#read 3, iclass 38, count 0 2006.246.07:36:31.18#ibcon#about to read 4, iclass 38, count 0 2006.246.07:36:31.18#ibcon#read 4, iclass 38, count 0 2006.246.07:36:31.18#ibcon#about to read 5, iclass 38, count 0 2006.246.07:36:31.18#ibcon#read 5, iclass 38, count 0 2006.246.07:36:31.18#ibcon#about to read 6, iclass 38, count 0 2006.246.07:36:31.18#ibcon#read 6, iclass 38, count 0 2006.246.07:36:31.18#ibcon#end of sib2, iclass 38, count 0 2006.246.07:36:31.18#ibcon#*after write, iclass 38, count 0 2006.246.07:36:31.18#ibcon#*before return 0, iclass 38, count 0 2006.246.07:36:31.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:31.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:36:31.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:36:31.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:36:31.18$vc4f8/vb=3,4 2006.246.07:36:31.18#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.07:36:31.18#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.07:36:31.18#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:31.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:31.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:31.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:31.24#ibcon#enter wrdev, iclass 40, count 2 2006.246.07:36:31.24#ibcon#first serial, iclass 40, count 2 2006.246.07:36:31.24#ibcon#enter sib2, iclass 40, count 2 2006.246.07:36:31.24#ibcon#flushed, iclass 40, count 2 2006.246.07:36:31.24#ibcon#about to write, iclass 40, count 2 2006.246.07:36:31.24#ibcon#wrote, iclass 40, count 2 2006.246.07:36:31.24#ibcon#about to read 3, iclass 40, count 2 2006.246.07:36:31.26#ibcon#read 3, iclass 40, count 2 2006.246.07:36:31.26#ibcon#about to read 4, iclass 40, count 2 2006.246.07:36:31.26#ibcon#read 4, iclass 40, count 2 2006.246.07:36:31.26#ibcon#about to read 5, iclass 40, count 2 2006.246.07:36:31.26#ibcon#read 5, iclass 40, count 2 2006.246.07:36:31.26#ibcon#about to read 6, iclass 40, count 2 2006.246.07:36:31.26#ibcon#read 6, iclass 40, count 2 2006.246.07:36:31.26#ibcon#end of sib2, iclass 40, count 2 2006.246.07:36:31.26#ibcon#*mode == 0, iclass 40, count 2 2006.246.07:36:31.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.07:36:31.26#ibcon#[27=AT03-04\r\n] 2006.246.07:36:31.26#ibcon#*before write, iclass 40, count 2 2006.246.07:36:31.26#ibcon#enter sib2, iclass 40, count 2 2006.246.07:36:31.26#ibcon#flushed, iclass 40, count 2 2006.246.07:36:31.26#ibcon#about to write, iclass 40, count 2 2006.246.07:36:31.26#ibcon#wrote, iclass 40, count 2 2006.246.07:36:31.26#ibcon#about to read 3, iclass 40, count 2 2006.246.07:36:31.29#ibcon#read 3, iclass 40, count 2 2006.246.07:36:31.29#ibcon#about to read 4, iclass 40, count 2 2006.246.07:36:31.29#ibcon#read 4, iclass 40, count 2 2006.246.07:36:31.29#ibcon#about to read 5, iclass 40, count 2 2006.246.07:36:31.29#ibcon#read 5, iclass 40, count 2 2006.246.07:36:31.29#ibcon#about to read 6, iclass 40, count 2 2006.246.07:36:31.29#ibcon#read 6, iclass 40, count 2 2006.246.07:36:31.29#ibcon#end of sib2, iclass 40, count 2 2006.246.07:36:31.29#ibcon#*after write, iclass 40, count 2 2006.246.07:36:31.29#ibcon#*before return 0, iclass 40, count 2 2006.246.07:36:31.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:31.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:36:31.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.07:36:31.29#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:31.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:31.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:31.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:31.41#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:36:31.41#ibcon#first serial, iclass 40, count 0 2006.246.07:36:31.41#ibcon#enter sib2, iclass 40, count 0 2006.246.07:36:31.41#ibcon#flushed, iclass 40, count 0 2006.246.07:36:31.41#ibcon#about to write, iclass 40, count 0 2006.246.07:36:31.41#ibcon#wrote, iclass 40, count 0 2006.246.07:36:31.41#ibcon#about to read 3, iclass 40, count 0 2006.246.07:36:31.43#ibcon#read 3, iclass 40, count 0 2006.246.07:36:31.43#ibcon#about to read 4, iclass 40, count 0 2006.246.07:36:31.43#ibcon#read 4, iclass 40, count 0 2006.246.07:36:31.43#ibcon#about to read 5, iclass 40, count 0 2006.246.07:36:31.43#ibcon#read 5, iclass 40, count 0 2006.246.07:36:31.43#ibcon#about to read 6, iclass 40, count 0 2006.246.07:36:31.43#ibcon#read 6, iclass 40, count 0 2006.246.07:36:31.43#ibcon#end of sib2, iclass 40, count 0 2006.246.07:36:31.43#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:36:31.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:36:31.43#ibcon#[27=USB\r\n] 2006.246.07:36:31.43#ibcon#*before write, iclass 40, count 0 2006.246.07:36:31.43#ibcon#enter sib2, iclass 40, count 0 2006.246.07:36:31.43#ibcon#flushed, iclass 40, count 0 2006.246.07:36:31.43#ibcon#about to write, iclass 40, count 0 2006.246.07:36:31.43#ibcon#wrote, iclass 40, count 0 2006.246.07:36:31.43#ibcon#about to read 3, iclass 40, count 0 2006.246.07:36:31.46#ibcon#read 3, iclass 40, count 0 2006.246.07:36:31.46#ibcon#about to read 4, iclass 40, count 0 2006.246.07:36:31.46#ibcon#read 4, iclass 40, count 0 2006.246.07:36:31.46#ibcon#about to read 5, iclass 40, count 0 2006.246.07:36:31.46#ibcon#read 5, iclass 40, count 0 2006.246.07:36:31.46#ibcon#about to read 6, iclass 40, count 0 2006.246.07:36:31.46#ibcon#read 6, iclass 40, count 0 2006.246.07:36:31.46#ibcon#end of sib2, iclass 40, count 0 2006.246.07:36:31.46#ibcon#*after write, iclass 40, count 0 2006.246.07:36:31.46#ibcon#*before return 0, iclass 40, count 0 2006.246.07:36:31.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:31.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:36:31.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:36:31.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:36:31.46$vc4f8/vblo=4,712.99 2006.246.07:36:31.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.07:36:31.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.07:36:31.46#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:31.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:31.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:31.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:31.46#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:36:31.46#ibcon#first serial, iclass 4, count 0 2006.246.07:36:31.46#ibcon#enter sib2, iclass 4, count 0 2006.246.07:36:31.46#ibcon#flushed, iclass 4, count 0 2006.246.07:36:31.46#ibcon#about to write, iclass 4, count 0 2006.246.07:36:31.46#ibcon#wrote, iclass 4, count 0 2006.246.07:36:31.46#ibcon#about to read 3, iclass 4, count 0 2006.246.07:36:31.48#ibcon#read 3, iclass 4, count 0 2006.246.07:36:31.48#ibcon#about to read 4, iclass 4, count 0 2006.246.07:36:31.48#ibcon#read 4, iclass 4, count 0 2006.246.07:36:31.48#ibcon#about to read 5, iclass 4, count 0 2006.246.07:36:31.48#ibcon#read 5, iclass 4, count 0 2006.246.07:36:31.48#ibcon#about to read 6, iclass 4, count 0 2006.246.07:36:31.48#ibcon#read 6, iclass 4, count 0 2006.246.07:36:31.48#ibcon#end of sib2, iclass 4, count 0 2006.246.07:36:31.48#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:36:31.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:36:31.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:36:31.48#ibcon#*before write, iclass 4, count 0 2006.246.07:36:31.48#ibcon#enter sib2, iclass 4, count 0 2006.246.07:36:31.48#ibcon#flushed, iclass 4, count 0 2006.246.07:36:31.48#ibcon#about to write, iclass 4, count 0 2006.246.07:36:31.48#ibcon#wrote, iclass 4, count 0 2006.246.07:36:31.48#ibcon#about to read 3, iclass 4, count 0 2006.246.07:36:31.52#ibcon#read 3, iclass 4, count 0 2006.246.07:36:31.52#ibcon#about to read 4, iclass 4, count 0 2006.246.07:36:31.52#ibcon#read 4, iclass 4, count 0 2006.246.07:36:31.52#ibcon#about to read 5, iclass 4, count 0 2006.246.07:36:31.52#ibcon#read 5, iclass 4, count 0 2006.246.07:36:31.52#ibcon#about to read 6, iclass 4, count 0 2006.246.07:36:31.52#ibcon#read 6, iclass 4, count 0 2006.246.07:36:31.52#ibcon#end of sib2, iclass 4, count 0 2006.246.07:36:31.52#ibcon#*after write, iclass 4, count 0 2006.246.07:36:31.52#ibcon#*before return 0, iclass 4, count 0 2006.246.07:36:31.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:31.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:36:31.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:36:31.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:36:31.52$vc4f8/vb=4,4 2006.246.07:36:31.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.07:36:31.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.07:36:31.52#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:31.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:31.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:31.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:31.58#ibcon#enter wrdev, iclass 6, count 2 2006.246.07:36:31.58#ibcon#first serial, iclass 6, count 2 2006.246.07:36:31.58#ibcon#enter sib2, iclass 6, count 2 2006.246.07:36:31.58#ibcon#flushed, iclass 6, count 2 2006.246.07:36:31.58#ibcon#about to write, iclass 6, count 2 2006.246.07:36:31.58#ibcon#wrote, iclass 6, count 2 2006.246.07:36:31.58#ibcon#about to read 3, iclass 6, count 2 2006.246.07:36:31.60#ibcon#read 3, iclass 6, count 2 2006.246.07:36:31.60#ibcon#about to read 4, iclass 6, count 2 2006.246.07:36:31.60#ibcon#read 4, iclass 6, count 2 2006.246.07:36:31.60#ibcon#about to read 5, iclass 6, count 2 2006.246.07:36:31.60#ibcon#read 5, iclass 6, count 2 2006.246.07:36:31.60#ibcon#about to read 6, iclass 6, count 2 2006.246.07:36:31.60#ibcon#read 6, iclass 6, count 2 2006.246.07:36:31.60#ibcon#end of sib2, iclass 6, count 2 2006.246.07:36:31.60#ibcon#*mode == 0, iclass 6, count 2 2006.246.07:36:31.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.07:36:31.60#ibcon#[27=AT04-04\r\n] 2006.246.07:36:31.60#ibcon#*before write, iclass 6, count 2 2006.246.07:36:31.60#ibcon#enter sib2, iclass 6, count 2 2006.246.07:36:31.60#ibcon#flushed, iclass 6, count 2 2006.246.07:36:31.60#ibcon#about to write, iclass 6, count 2 2006.246.07:36:31.60#ibcon#wrote, iclass 6, count 2 2006.246.07:36:31.60#ibcon#about to read 3, iclass 6, count 2 2006.246.07:36:31.63#ibcon#read 3, iclass 6, count 2 2006.246.07:36:31.63#ibcon#about to read 4, iclass 6, count 2 2006.246.07:36:31.63#ibcon#read 4, iclass 6, count 2 2006.246.07:36:31.63#ibcon#about to read 5, iclass 6, count 2 2006.246.07:36:31.63#ibcon#read 5, iclass 6, count 2 2006.246.07:36:31.63#ibcon#about to read 6, iclass 6, count 2 2006.246.07:36:31.63#ibcon#read 6, iclass 6, count 2 2006.246.07:36:31.63#ibcon#end of sib2, iclass 6, count 2 2006.246.07:36:31.63#ibcon#*after write, iclass 6, count 2 2006.246.07:36:31.63#ibcon#*before return 0, iclass 6, count 2 2006.246.07:36:31.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:31.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:36:31.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.07:36:31.63#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:31.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:31.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:31.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:31.75#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:36:31.75#ibcon#first serial, iclass 6, count 0 2006.246.07:36:31.75#ibcon#enter sib2, iclass 6, count 0 2006.246.07:36:31.75#ibcon#flushed, iclass 6, count 0 2006.246.07:36:31.75#ibcon#about to write, iclass 6, count 0 2006.246.07:36:31.75#ibcon#wrote, iclass 6, count 0 2006.246.07:36:31.75#ibcon#about to read 3, iclass 6, count 0 2006.246.07:36:31.77#ibcon#read 3, iclass 6, count 0 2006.246.07:36:31.77#ibcon#about to read 4, iclass 6, count 0 2006.246.07:36:31.77#ibcon#read 4, iclass 6, count 0 2006.246.07:36:31.77#ibcon#about to read 5, iclass 6, count 0 2006.246.07:36:31.77#ibcon#read 5, iclass 6, count 0 2006.246.07:36:31.77#ibcon#about to read 6, iclass 6, count 0 2006.246.07:36:31.77#ibcon#read 6, iclass 6, count 0 2006.246.07:36:31.77#ibcon#end of sib2, iclass 6, count 0 2006.246.07:36:31.77#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:36:31.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:36:31.77#ibcon#[27=USB\r\n] 2006.246.07:36:31.77#ibcon#*before write, iclass 6, count 0 2006.246.07:36:31.77#ibcon#enter sib2, iclass 6, count 0 2006.246.07:36:31.77#ibcon#flushed, iclass 6, count 0 2006.246.07:36:31.77#ibcon#about to write, iclass 6, count 0 2006.246.07:36:31.77#ibcon#wrote, iclass 6, count 0 2006.246.07:36:31.77#ibcon#about to read 3, iclass 6, count 0 2006.246.07:36:31.80#ibcon#read 3, iclass 6, count 0 2006.246.07:36:31.80#ibcon#about to read 4, iclass 6, count 0 2006.246.07:36:31.80#ibcon#read 4, iclass 6, count 0 2006.246.07:36:31.80#ibcon#about to read 5, iclass 6, count 0 2006.246.07:36:31.80#ibcon#read 5, iclass 6, count 0 2006.246.07:36:31.80#ibcon#about to read 6, iclass 6, count 0 2006.246.07:36:31.80#ibcon#read 6, iclass 6, count 0 2006.246.07:36:31.80#ibcon#end of sib2, iclass 6, count 0 2006.246.07:36:31.80#ibcon#*after write, iclass 6, count 0 2006.246.07:36:31.80#ibcon#*before return 0, iclass 6, count 0 2006.246.07:36:31.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:31.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:36:31.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:36:31.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:36:31.80$vc4f8/vblo=5,744.99 2006.246.07:36:31.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.07:36:31.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.07:36:31.80#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:31.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:31.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:31.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:31.80#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:36:31.80#ibcon#first serial, iclass 10, count 0 2006.246.07:36:31.80#ibcon#enter sib2, iclass 10, count 0 2006.246.07:36:31.80#ibcon#flushed, iclass 10, count 0 2006.246.07:36:31.80#ibcon#about to write, iclass 10, count 0 2006.246.07:36:31.80#ibcon#wrote, iclass 10, count 0 2006.246.07:36:31.80#ibcon#about to read 3, iclass 10, count 0 2006.246.07:36:31.82#ibcon#read 3, iclass 10, count 0 2006.246.07:36:31.82#ibcon#about to read 4, iclass 10, count 0 2006.246.07:36:31.82#ibcon#read 4, iclass 10, count 0 2006.246.07:36:31.82#ibcon#about to read 5, iclass 10, count 0 2006.246.07:36:31.82#ibcon#read 5, iclass 10, count 0 2006.246.07:36:31.82#ibcon#about to read 6, iclass 10, count 0 2006.246.07:36:31.82#ibcon#read 6, iclass 10, count 0 2006.246.07:36:31.82#ibcon#end of sib2, iclass 10, count 0 2006.246.07:36:31.82#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:36:31.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:36:31.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:36:31.82#ibcon#*before write, iclass 10, count 0 2006.246.07:36:31.82#ibcon#enter sib2, iclass 10, count 0 2006.246.07:36:31.82#ibcon#flushed, iclass 10, count 0 2006.246.07:36:31.82#ibcon#about to write, iclass 10, count 0 2006.246.07:36:31.82#ibcon#wrote, iclass 10, count 0 2006.246.07:36:31.82#ibcon#about to read 3, iclass 10, count 0 2006.246.07:36:31.86#ibcon#read 3, iclass 10, count 0 2006.246.07:36:31.86#ibcon#about to read 4, iclass 10, count 0 2006.246.07:36:31.86#ibcon#read 4, iclass 10, count 0 2006.246.07:36:31.86#ibcon#about to read 5, iclass 10, count 0 2006.246.07:36:31.86#ibcon#read 5, iclass 10, count 0 2006.246.07:36:31.86#ibcon#about to read 6, iclass 10, count 0 2006.246.07:36:31.86#ibcon#read 6, iclass 10, count 0 2006.246.07:36:31.86#ibcon#end of sib2, iclass 10, count 0 2006.246.07:36:31.86#ibcon#*after write, iclass 10, count 0 2006.246.07:36:31.86#ibcon#*before return 0, iclass 10, count 0 2006.246.07:36:31.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:31.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:36:31.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:36:31.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:36:31.86$vc4f8/vb=5,3 2006.246.07:36:31.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.07:36:31.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.07:36:31.86#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:31.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:31.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:31.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:31.92#ibcon#enter wrdev, iclass 12, count 2 2006.246.07:36:31.92#ibcon#first serial, iclass 12, count 2 2006.246.07:36:31.92#ibcon#enter sib2, iclass 12, count 2 2006.246.07:36:31.92#ibcon#flushed, iclass 12, count 2 2006.246.07:36:31.92#ibcon#about to write, iclass 12, count 2 2006.246.07:36:31.92#ibcon#wrote, iclass 12, count 2 2006.246.07:36:31.92#ibcon#about to read 3, iclass 12, count 2 2006.246.07:36:31.94#ibcon#read 3, iclass 12, count 2 2006.246.07:36:31.94#ibcon#about to read 4, iclass 12, count 2 2006.246.07:36:31.94#ibcon#read 4, iclass 12, count 2 2006.246.07:36:31.94#ibcon#about to read 5, iclass 12, count 2 2006.246.07:36:31.94#ibcon#read 5, iclass 12, count 2 2006.246.07:36:31.94#ibcon#about to read 6, iclass 12, count 2 2006.246.07:36:31.94#ibcon#read 6, iclass 12, count 2 2006.246.07:36:31.94#ibcon#end of sib2, iclass 12, count 2 2006.246.07:36:31.94#ibcon#*mode == 0, iclass 12, count 2 2006.246.07:36:31.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.07:36:31.94#ibcon#[27=AT05-03\r\n] 2006.246.07:36:31.94#ibcon#*before write, iclass 12, count 2 2006.246.07:36:31.94#ibcon#enter sib2, iclass 12, count 2 2006.246.07:36:31.94#ibcon#flushed, iclass 12, count 2 2006.246.07:36:31.94#ibcon#about to write, iclass 12, count 2 2006.246.07:36:31.94#ibcon#wrote, iclass 12, count 2 2006.246.07:36:31.94#ibcon#about to read 3, iclass 12, count 2 2006.246.07:36:31.97#ibcon#read 3, iclass 12, count 2 2006.246.07:36:31.97#ibcon#about to read 4, iclass 12, count 2 2006.246.07:36:31.97#ibcon#read 4, iclass 12, count 2 2006.246.07:36:31.97#ibcon#about to read 5, iclass 12, count 2 2006.246.07:36:31.97#ibcon#read 5, iclass 12, count 2 2006.246.07:36:31.97#ibcon#about to read 6, iclass 12, count 2 2006.246.07:36:31.97#ibcon#read 6, iclass 12, count 2 2006.246.07:36:31.97#ibcon#end of sib2, iclass 12, count 2 2006.246.07:36:31.97#ibcon#*after write, iclass 12, count 2 2006.246.07:36:31.97#ibcon#*before return 0, iclass 12, count 2 2006.246.07:36:31.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:31.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:36:31.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.07:36:31.97#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:31.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:32.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:32.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:32.09#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:36:32.09#ibcon#first serial, iclass 12, count 0 2006.246.07:36:32.09#ibcon#enter sib2, iclass 12, count 0 2006.246.07:36:32.09#ibcon#flushed, iclass 12, count 0 2006.246.07:36:32.09#ibcon#about to write, iclass 12, count 0 2006.246.07:36:32.09#ibcon#wrote, iclass 12, count 0 2006.246.07:36:32.09#ibcon#about to read 3, iclass 12, count 0 2006.246.07:36:32.12#ibcon#read 3, iclass 12, count 0 2006.246.07:36:32.12#ibcon#about to read 4, iclass 12, count 0 2006.246.07:36:32.12#ibcon#read 4, iclass 12, count 0 2006.246.07:36:32.12#ibcon#about to read 5, iclass 12, count 0 2006.246.07:36:32.12#ibcon#read 5, iclass 12, count 0 2006.246.07:36:32.12#ibcon#about to read 6, iclass 12, count 0 2006.246.07:36:32.12#ibcon#read 6, iclass 12, count 0 2006.246.07:36:32.12#ibcon#end of sib2, iclass 12, count 0 2006.246.07:36:32.12#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:36:32.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:36:32.12#ibcon#[27=USB\r\n] 2006.246.07:36:32.12#ibcon#*before write, iclass 12, count 0 2006.246.07:36:32.12#ibcon#enter sib2, iclass 12, count 0 2006.246.07:36:32.12#ibcon#flushed, iclass 12, count 0 2006.246.07:36:32.12#ibcon#about to write, iclass 12, count 0 2006.246.07:36:32.12#ibcon#wrote, iclass 12, count 0 2006.246.07:36:32.12#ibcon#about to read 3, iclass 12, count 0 2006.246.07:36:32.15#ibcon#read 3, iclass 12, count 0 2006.246.07:36:32.15#ibcon#about to read 4, iclass 12, count 0 2006.246.07:36:32.15#ibcon#read 4, iclass 12, count 0 2006.246.07:36:32.15#ibcon#about to read 5, iclass 12, count 0 2006.246.07:36:32.15#ibcon#read 5, iclass 12, count 0 2006.246.07:36:32.15#ibcon#about to read 6, iclass 12, count 0 2006.246.07:36:32.15#ibcon#read 6, iclass 12, count 0 2006.246.07:36:32.15#ibcon#end of sib2, iclass 12, count 0 2006.246.07:36:32.15#ibcon#*after write, iclass 12, count 0 2006.246.07:36:32.15#ibcon#*before return 0, iclass 12, count 0 2006.246.07:36:32.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:32.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:36:32.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:36:32.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:36:32.15$vc4f8/vblo=6,752.99 2006.246.07:36:32.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.07:36:32.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.07:36:32.15#ibcon#ireg 17 cls_cnt 0 2006.246.07:36:32.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:36:32.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:36:32.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:36:32.15#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:36:32.15#ibcon#first serial, iclass 14, count 0 2006.246.07:36:32.15#ibcon#enter sib2, iclass 14, count 0 2006.246.07:36:32.15#ibcon#flushed, iclass 14, count 0 2006.246.07:36:32.15#ibcon#about to write, iclass 14, count 0 2006.246.07:36:32.15#ibcon#wrote, iclass 14, count 0 2006.246.07:36:32.15#ibcon#about to read 3, iclass 14, count 0 2006.246.07:36:32.17#ibcon#read 3, iclass 14, count 0 2006.246.07:36:32.17#ibcon#about to read 4, iclass 14, count 0 2006.246.07:36:32.17#ibcon#read 4, iclass 14, count 0 2006.246.07:36:32.17#ibcon#about to read 5, iclass 14, count 0 2006.246.07:36:32.17#ibcon#read 5, iclass 14, count 0 2006.246.07:36:32.17#ibcon#about to read 6, iclass 14, count 0 2006.246.07:36:32.17#ibcon#read 6, iclass 14, count 0 2006.246.07:36:32.17#ibcon#end of sib2, iclass 14, count 0 2006.246.07:36:32.17#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:36:32.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:36:32.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:36:32.17#ibcon#*before write, iclass 14, count 0 2006.246.07:36:32.17#ibcon#enter sib2, iclass 14, count 0 2006.246.07:36:32.17#ibcon#flushed, iclass 14, count 0 2006.246.07:36:32.17#ibcon#about to write, iclass 14, count 0 2006.246.07:36:32.17#ibcon#wrote, iclass 14, count 0 2006.246.07:36:32.17#ibcon#about to read 3, iclass 14, count 0 2006.246.07:36:32.21#ibcon#read 3, iclass 14, count 0 2006.246.07:36:32.21#ibcon#about to read 4, iclass 14, count 0 2006.246.07:36:32.21#ibcon#read 4, iclass 14, count 0 2006.246.07:36:32.21#ibcon#about to read 5, iclass 14, count 0 2006.246.07:36:32.21#ibcon#read 5, iclass 14, count 0 2006.246.07:36:32.21#ibcon#about to read 6, iclass 14, count 0 2006.246.07:36:32.21#ibcon#read 6, iclass 14, count 0 2006.246.07:36:32.21#ibcon#end of sib2, iclass 14, count 0 2006.246.07:36:32.21#ibcon#*after write, iclass 14, count 0 2006.246.07:36:32.21#ibcon#*before return 0, iclass 14, count 0 2006.246.07:36:32.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:36:32.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:36:32.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:36:32.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:36:32.21$vc4f8/vb=6,3 2006.246.07:36:32.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.07:36:32.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.07:36:32.21#ibcon#ireg 11 cls_cnt 2 2006.246.07:36:32.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:36:32.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:36:32.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:36:32.27#ibcon#enter wrdev, iclass 16, count 2 2006.246.07:36:32.27#ibcon#first serial, iclass 16, count 2 2006.246.07:36:32.27#ibcon#enter sib2, iclass 16, count 2 2006.246.07:36:32.27#ibcon#flushed, iclass 16, count 2 2006.246.07:36:32.27#ibcon#about to write, iclass 16, count 2 2006.246.07:36:32.27#ibcon#wrote, iclass 16, count 2 2006.246.07:36:32.27#ibcon#about to read 3, iclass 16, count 2 2006.246.07:36:32.29#ibcon#read 3, iclass 16, count 2 2006.246.07:36:32.29#ibcon#about to read 4, iclass 16, count 2 2006.246.07:36:32.29#ibcon#read 4, iclass 16, count 2 2006.246.07:36:32.29#ibcon#about to read 5, iclass 16, count 2 2006.246.07:36:32.29#ibcon#read 5, iclass 16, count 2 2006.246.07:36:32.29#ibcon#about to read 6, iclass 16, count 2 2006.246.07:36:32.29#ibcon#read 6, iclass 16, count 2 2006.246.07:36:32.29#ibcon#end of sib2, iclass 16, count 2 2006.246.07:36:32.29#ibcon#*mode == 0, iclass 16, count 2 2006.246.07:36:32.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.07:36:32.29#ibcon#[27=AT06-03\r\n] 2006.246.07:36:32.29#ibcon#*before write, iclass 16, count 2 2006.246.07:36:32.29#ibcon#enter sib2, iclass 16, count 2 2006.246.07:36:32.29#ibcon#flushed, iclass 16, count 2 2006.246.07:36:32.29#ibcon#about to write, iclass 16, count 2 2006.246.07:36:32.29#ibcon#wrote, iclass 16, count 2 2006.246.07:36:32.29#ibcon#about to read 3, iclass 16, count 2 2006.246.07:36:32.32#ibcon#read 3, iclass 16, count 2 2006.246.07:36:32.32#ibcon#about to read 4, iclass 16, count 2 2006.246.07:36:32.32#ibcon#read 4, iclass 16, count 2 2006.246.07:36:32.32#ibcon#about to read 5, iclass 16, count 2 2006.246.07:36:32.32#ibcon#read 5, iclass 16, count 2 2006.246.07:36:32.32#ibcon#about to read 6, iclass 16, count 2 2006.246.07:36:32.32#ibcon#read 6, iclass 16, count 2 2006.246.07:36:32.32#ibcon#end of sib2, iclass 16, count 2 2006.246.07:36:32.32#ibcon#*after write, iclass 16, count 2 2006.246.07:36:32.32#ibcon#*before return 0, iclass 16, count 2 2006.246.07:36:32.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:36:32.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:36:32.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.07:36:32.32#ibcon#ireg 7 cls_cnt 0 2006.246.07:36:32.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:36:32.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:36:32.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:36:32.44#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:36:32.44#ibcon#first serial, iclass 16, count 0 2006.246.07:36:32.44#ibcon#enter sib2, iclass 16, count 0 2006.246.07:36:32.44#ibcon#flushed, iclass 16, count 0 2006.246.07:36:32.44#ibcon#about to write, iclass 16, count 0 2006.246.07:36:32.44#ibcon#wrote, iclass 16, count 0 2006.246.07:36:32.44#ibcon#about to read 3, iclass 16, count 0 2006.246.07:36:32.46#ibcon#read 3, iclass 16, count 0 2006.246.07:36:32.46#ibcon#about to read 4, iclass 16, count 0 2006.246.07:36:32.46#ibcon#read 4, iclass 16, count 0 2006.246.07:36:32.46#ibcon#about to read 5, iclass 16, count 0 2006.246.07:36:32.46#ibcon#read 5, iclass 16, count 0 2006.246.07:36:32.46#ibcon#about to read 6, iclass 16, count 0 2006.246.07:36:32.46#ibcon#read 6, iclass 16, count 0 2006.246.07:36:32.46#ibcon#end of sib2, iclass 16, count 0 2006.246.07:36:32.46#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:36:32.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:36:32.46#ibcon#[27=USB\r\n] 2006.246.07:36:32.46#ibcon#*before write, iclass 16, count 0 2006.246.07:36:32.46#ibcon#enter sib2, iclass 16, count 0 2006.246.07:36:32.46#ibcon#flushed, iclass 16, count 0 2006.246.07:36:32.46#ibcon#about to write, iclass 16, count 0 2006.246.07:36:32.46#ibcon#wrote, iclass 16, count 0 2006.246.07:36:32.46#ibcon#about to read 3, iclass 16, count 0 2006.246.07:36:32.49#ibcon#read 3, iclass 16, count 0 2006.246.07:36:32.49#ibcon#about to read 4, iclass 16, count 0 2006.246.07:36:32.49#ibcon#read 4, iclass 16, count 0 2006.246.07:36:32.49#ibcon#about to read 5, iclass 16, count 0 2006.246.07:36:32.49#ibcon#read 5, iclass 16, count 0 2006.246.07:36:32.49#ibcon#about to read 6, iclass 16, count 0 2006.246.07:36:32.49#ibcon#read 6, iclass 16, count 0 2006.246.07:36:32.49#ibcon#end of sib2, iclass 16, count 0 2006.246.07:36:32.49#ibcon#*after write, iclass 16, count 0 2006.246.07:36:32.49#ibcon#*before return 0, iclass 16, count 0 2006.246.07:36:32.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:36:32.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:36:32.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:36:32.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:36:32.49$vc4f8/vabw=wide 2006.246.07:36:32.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:36:32.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:36:32.49#ibcon#ireg 8 cls_cnt 0 2006.246.07:36:32.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:32.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:32.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:32.49#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:36:32.49#ibcon#first serial, iclass 18, count 0 2006.246.07:36:32.49#ibcon#enter sib2, iclass 18, count 0 2006.246.07:36:32.49#ibcon#flushed, iclass 18, count 0 2006.246.07:36:32.49#ibcon#about to write, iclass 18, count 0 2006.246.07:36:32.49#ibcon#wrote, iclass 18, count 0 2006.246.07:36:32.49#ibcon#about to read 3, iclass 18, count 0 2006.246.07:36:32.51#ibcon#read 3, iclass 18, count 0 2006.246.07:36:32.51#ibcon#about to read 4, iclass 18, count 0 2006.246.07:36:32.51#ibcon#read 4, iclass 18, count 0 2006.246.07:36:32.51#ibcon#about to read 5, iclass 18, count 0 2006.246.07:36:32.51#ibcon#read 5, iclass 18, count 0 2006.246.07:36:32.51#ibcon#about to read 6, iclass 18, count 0 2006.246.07:36:32.51#ibcon#read 6, iclass 18, count 0 2006.246.07:36:32.51#ibcon#end of sib2, iclass 18, count 0 2006.246.07:36:32.51#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:36:32.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:36:32.51#ibcon#[25=BW32\r\n] 2006.246.07:36:32.51#ibcon#*before write, iclass 18, count 0 2006.246.07:36:32.51#ibcon#enter sib2, iclass 18, count 0 2006.246.07:36:32.51#ibcon#flushed, iclass 18, count 0 2006.246.07:36:32.51#ibcon#about to write, iclass 18, count 0 2006.246.07:36:32.51#ibcon#wrote, iclass 18, count 0 2006.246.07:36:32.51#ibcon#about to read 3, iclass 18, count 0 2006.246.07:36:32.54#ibcon#read 3, iclass 18, count 0 2006.246.07:36:32.54#ibcon#about to read 4, iclass 18, count 0 2006.246.07:36:32.54#ibcon#read 4, iclass 18, count 0 2006.246.07:36:32.54#ibcon#about to read 5, iclass 18, count 0 2006.246.07:36:32.54#ibcon#read 5, iclass 18, count 0 2006.246.07:36:32.54#ibcon#about to read 6, iclass 18, count 0 2006.246.07:36:32.54#ibcon#read 6, iclass 18, count 0 2006.246.07:36:32.54#ibcon#end of sib2, iclass 18, count 0 2006.246.07:36:32.54#ibcon#*after write, iclass 18, count 0 2006.246.07:36:32.54#ibcon#*before return 0, iclass 18, count 0 2006.246.07:36:32.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:32.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:36:32.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:36:32.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:36:32.54$vc4f8/vbbw=wide 2006.246.07:36:32.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.07:36:32.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.07:36:32.54#ibcon#ireg 8 cls_cnt 0 2006.246.07:36:32.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:36:32.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:36:32.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:36:32.61#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:36:32.61#ibcon#first serial, iclass 20, count 0 2006.246.07:36:32.61#ibcon#enter sib2, iclass 20, count 0 2006.246.07:36:32.61#ibcon#flushed, iclass 20, count 0 2006.246.07:36:32.61#ibcon#about to write, iclass 20, count 0 2006.246.07:36:32.61#ibcon#wrote, iclass 20, count 0 2006.246.07:36:32.61#ibcon#about to read 3, iclass 20, count 0 2006.246.07:36:32.63#ibcon#read 3, iclass 20, count 0 2006.246.07:36:32.63#ibcon#about to read 4, iclass 20, count 0 2006.246.07:36:32.63#ibcon#read 4, iclass 20, count 0 2006.246.07:36:32.63#ibcon#about to read 5, iclass 20, count 0 2006.246.07:36:32.63#ibcon#read 5, iclass 20, count 0 2006.246.07:36:32.63#ibcon#about to read 6, iclass 20, count 0 2006.246.07:36:32.63#ibcon#read 6, iclass 20, count 0 2006.246.07:36:32.63#ibcon#end of sib2, iclass 20, count 0 2006.246.07:36:32.63#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:36:32.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:36:32.63#ibcon#[27=BW32\r\n] 2006.246.07:36:32.63#ibcon#*before write, iclass 20, count 0 2006.246.07:36:32.63#ibcon#enter sib2, iclass 20, count 0 2006.246.07:36:32.63#ibcon#flushed, iclass 20, count 0 2006.246.07:36:32.63#ibcon#about to write, iclass 20, count 0 2006.246.07:36:32.63#ibcon#wrote, iclass 20, count 0 2006.246.07:36:32.63#ibcon#about to read 3, iclass 20, count 0 2006.246.07:36:32.66#ibcon#read 3, iclass 20, count 0 2006.246.07:36:32.66#ibcon#about to read 4, iclass 20, count 0 2006.246.07:36:32.66#ibcon#read 4, iclass 20, count 0 2006.246.07:36:32.66#ibcon#about to read 5, iclass 20, count 0 2006.246.07:36:32.66#ibcon#read 5, iclass 20, count 0 2006.246.07:36:32.66#ibcon#about to read 6, iclass 20, count 0 2006.246.07:36:32.66#ibcon#read 6, iclass 20, count 0 2006.246.07:36:32.66#ibcon#end of sib2, iclass 20, count 0 2006.246.07:36:32.66#ibcon#*after write, iclass 20, count 0 2006.246.07:36:32.66#ibcon#*before return 0, iclass 20, count 0 2006.246.07:36:32.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:36:32.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:36:32.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:36:32.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:36:32.66$4f8m12a/ifd4f 2006.246.07:36:32.66$ifd4f/lo= 2006.246.07:36:32.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:36:32.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:36:32.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:36:32.66$ifd4f/patch= 2006.246.07:36:32.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:36:32.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:36:32.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:36:32.66$4f8m12a/"form=m,16.000,1:2 2006.246.07:36:32.66$4f8m12a/"tpicd 2006.246.07:36:32.66$4f8m12a/echo=off 2006.246.07:36:32.66$4f8m12a/xlog=off 2006.246.07:36:32.66:!2006.246.07:37:00 2006.246.07:36:41.13#trakl#Source acquired 2006.246.07:36:42.13#flagr#flagr/antenna,acquired 2006.246.07:37:00.02:preob 2006.246.07:37:01.13/onsource/TRACKING 2006.246.07:37:01.13:!2006.246.07:37:10 2006.246.07:37:10.02:data_valid=on 2006.246.07:37:10.02:midob 2006.246.07:37:11.13/onsource/TRACKING 2006.246.07:37:11.13/wx/26.78,1005.6,73 2006.246.07:37:11.34/cable/+6.4132E-03 2006.246.07:37:12.43/va/01,08,usb,yes,31,33 2006.246.07:37:12.43/va/02,07,usb,yes,31,32 2006.246.07:37:12.43/va/03,06,usb,yes,33,33 2006.246.07:37:12.43/va/04,07,usb,yes,32,35 2006.246.07:37:12.43/va/05,07,usb,yes,34,36 2006.246.07:37:12.43/va/06,07,usb,yes,30,30 2006.246.07:37:12.43/va/07,07,usb,yes,30,29 2006.246.07:37:12.43/va/08,08,usb,yes,26,25 2006.246.07:37:12.66/valo/01,532.99,yes,locked 2006.246.07:37:12.66/valo/02,572.99,yes,locked 2006.246.07:37:12.66/valo/03,672.99,yes,locked 2006.246.07:37:12.66/valo/04,832.99,yes,locked 2006.246.07:37:12.66/valo/05,652.99,yes,locked 2006.246.07:37:12.66/valo/06,772.99,yes,locked 2006.246.07:37:12.66/valo/07,832.99,yes,locked 2006.246.07:37:12.66/valo/08,852.99,yes,locked 2006.246.07:37:13.75/vb/01,04,usb,yes,31,29 2006.246.07:37:13.75/vb/02,04,usb,yes,33,34 2006.246.07:37:13.75/vb/03,04,usb,yes,29,33 2006.246.07:37:13.75/vb/04,04,usb,yes,30,30 2006.246.07:37:13.75/vb/05,03,usb,yes,35,40 2006.246.07:37:13.75/vb/06,03,usb,yes,36,39 2006.246.07:37:13.75/vb/07,04,usb,yes,31,31 2006.246.07:37:13.75/vb/08,03,usb,yes,36,40 2006.246.07:37:13.98/vblo/01,632.99,yes,locked 2006.246.07:37:13.98/vblo/02,640.99,yes,locked 2006.246.07:37:13.98/vblo/03,656.99,yes,locked 2006.246.07:37:13.98/vblo/04,712.99,yes,locked 2006.246.07:37:13.98/vblo/05,744.99,yes,locked 2006.246.07:37:13.98/vblo/06,752.99,yes,locked 2006.246.07:37:13.98/vblo/07,734.99,yes,locked 2006.246.07:37:13.98/vblo/08,744.99,yes,locked 2006.246.07:37:14.13/vabw/8 2006.246.07:37:14.28/vbbw/8 2006.246.07:37:14.37/xfe/off,on,13.2 2006.246.07:37:14.74/ifatt/23,28,28,28 2006.246.07:37:15.09/fmout-gps/S +4.31E-07 2006.246.07:37:15.16:!2006.246.07:38:10 2006.246.07:38:10.02:data_valid=off 2006.246.07:38:10.02:postob 2006.246.07:38:10.19/cable/+6.4149E-03 2006.246.07:38:10.19/wx/26.77,1005.6,73 2006.246.07:38:11.07/fmout-gps/S +4.32E-07 2006.246.07:38:11.08:scan_name=246-0739,k06246,60 2006.246.07:38:11.08:source=oq208,140700.39,282714.7,2000.0,ccw 2006.246.07:38:12.14#flagr#flagr/antenna,new-source 2006.246.07:38:12.14:checkk5 2006.246.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:38:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:38:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:38:13.99/chk_obsdata//k5ts1/T2460737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:38:14.37/chk_obsdata//k5ts2/T2460737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:38:14.74/chk_obsdata//k5ts3/T2460737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:38:15.10/chk_obsdata//k5ts4/T2460737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:38:15.81/k5log//k5ts1_log_newline 2006.246.07:38:16.49/k5log//k5ts2_log_newline 2006.246.07:38:17.18/k5log//k5ts3_log_newline 2006.246.07:38:17.87/k5log//k5ts4_log_newline 2006.246.07:38:17.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:38:17.89:4f8m12a=1 2006.246.07:38:17.90$4f8m12a/echo=on 2006.246.07:38:17.90$4f8m12a/pcalon 2006.246.07:38:17.90$pcalon/"no phase cal control is implemented here 2006.246.07:38:17.90$4f8m12a/"tpicd=stop 2006.246.07:38:17.90$4f8m12a/vc4f8 2006.246.07:38:17.90$vc4f8/valo=1,532.99 2006.246.07:38:17.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:38:17.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:38:17.90#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:17.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:17.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:17.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:17.90#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:38:17.90#ibcon#first serial, iclass 22, count 0 2006.246.07:38:17.90#ibcon#enter sib2, iclass 22, count 0 2006.246.07:38:17.90#ibcon#flushed, iclass 22, count 0 2006.246.07:38:17.90#ibcon#about to write, iclass 22, count 0 2006.246.07:38:17.90#ibcon#wrote, iclass 22, count 0 2006.246.07:38:17.90#ibcon#about to read 3, iclass 22, count 0 2006.246.07:38:17.94#ibcon#read 3, iclass 22, count 0 2006.246.07:38:17.94#ibcon#about to read 4, iclass 22, count 0 2006.246.07:38:17.94#ibcon#read 4, iclass 22, count 0 2006.246.07:38:17.94#ibcon#about to read 5, iclass 22, count 0 2006.246.07:38:17.94#ibcon#read 5, iclass 22, count 0 2006.246.07:38:17.94#ibcon#about to read 6, iclass 22, count 0 2006.246.07:38:17.94#ibcon#read 6, iclass 22, count 0 2006.246.07:38:17.94#ibcon#end of sib2, iclass 22, count 0 2006.246.07:38:17.94#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:38:17.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:38:17.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:38:17.94#ibcon#*before write, iclass 22, count 0 2006.246.07:38:17.94#ibcon#enter sib2, iclass 22, count 0 2006.246.07:38:17.94#ibcon#flushed, iclass 22, count 0 2006.246.07:38:17.94#ibcon#about to write, iclass 22, count 0 2006.246.07:38:17.94#ibcon#wrote, iclass 22, count 0 2006.246.07:38:17.94#ibcon#about to read 3, iclass 22, count 0 2006.246.07:38:17.98#ibcon#read 3, iclass 22, count 0 2006.246.07:38:17.98#ibcon#about to read 4, iclass 22, count 0 2006.246.07:38:17.98#ibcon#read 4, iclass 22, count 0 2006.246.07:38:17.98#ibcon#about to read 5, iclass 22, count 0 2006.246.07:38:17.98#ibcon#read 5, iclass 22, count 0 2006.246.07:38:17.98#ibcon#about to read 6, iclass 22, count 0 2006.246.07:38:17.98#ibcon#read 6, iclass 22, count 0 2006.246.07:38:17.98#ibcon#end of sib2, iclass 22, count 0 2006.246.07:38:17.98#ibcon#*after write, iclass 22, count 0 2006.246.07:38:17.98#ibcon#*before return 0, iclass 22, count 0 2006.246.07:38:17.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:17.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:17.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:38:17.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:38:17.99$vc4f8/va=1,8 2006.246.07:38:17.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.07:38:17.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.07:38:17.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:17.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:17.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:17.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:17.99#ibcon#enter wrdev, iclass 24, count 2 2006.246.07:38:17.99#ibcon#first serial, iclass 24, count 2 2006.246.07:38:17.99#ibcon#enter sib2, iclass 24, count 2 2006.246.07:38:17.99#ibcon#flushed, iclass 24, count 2 2006.246.07:38:17.99#ibcon#about to write, iclass 24, count 2 2006.246.07:38:17.99#ibcon#wrote, iclass 24, count 2 2006.246.07:38:17.99#ibcon#about to read 3, iclass 24, count 2 2006.246.07:38:18.00#ibcon#read 3, iclass 24, count 2 2006.246.07:38:18.00#ibcon#about to read 4, iclass 24, count 2 2006.246.07:38:18.00#ibcon#read 4, iclass 24, count 2 2006.246.07:38:18.00#ibcon#about to read 5, iclass 24, count 2 2006.246.07:38:18.00#ibcon#read 5, iclass 24, count 2 2006.246.07:38:18.00#ibcon#about to read 6, iclass 24, count 2 2006.246.07:38:18.00#ibcon#read 6, iclass 24, count 2 2006.246.07:38:18.00#ibcon#end of sib2, iclass 24, count 2 2006.246.07:38:18.00#ibcon#*mode == 0, iclass 24, count 2 2006.246.07:38:18.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.07:38:18.01#ibcon#[25=AT01-08\r\n] 2006.246.07:38:18.01#ibcon#*before write, iclass 24, count 2 2006.246.07:38:18.01#ibcon#enter sib2, iclass 24, count 2 2006.246.07:38:18.01#ibcon#flushed, iclass 24, count 2 2006.246.07:38:18.01#ibcon#about to write, iclass 24, count 2 2006.246.07:38:18.01#ibcon#wrote, iclass 24, count 2 2006.246.07:38:18.01#ibcon#about to read 3, iclass 24, count 2 2006.246.07:38:18.04#ibcon#read 3, iclass 24, count 2 2006.246.07:38:18.04#ibcon#about to read 4, iclass 24, count 2 2006.246.07:38:18.04#ibcon#read 4, iclass 24, count 2 2006.246.07:38:18.04#ibcon#about to read 5, iclass 24, count 2 2006.246.07:38:18.04#ibcon#read 5, iclass 24, count 2 2006.246.07:38:18.04#ibcon#about to read 6, iclass 24, count 2 2006.246.07:38:18.04#ibcon#read 6, iclass 24, count 2 2006.246.07:38:18.04#ibcon#end of sib2, iclass 24, count 2 2006.246.07:38:18.04#ibcon#*after write, iclass 24, count 2 2006.246.07:38:18.04#ibcon#*before return 0, iclass 24, count 2 2006.246.07:38:18.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:18.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:18.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.07:38:18.04#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:18.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:18.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:18.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:18.15#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:38:18.15#ibcon#first serial, iclass 24, count 0 2006.246.07:38:18.15#ibcon#enter sib2, iclass 24, count 0 2006.246.07:38:18.15#ibcon#flushed, iclass 24, count 0 2006.246.07:38:18.15#ibcon#about to write, iclass 24, count 0 2006.246.07:38:18.15#ibcon#wrote, iclass 24, count 0 2006.246.07:38:18.15#ibcon#about to read 3, iclass 24, count 0 2006.246.07:38:18.17#ibcon#read 3, iclass 24, count 0 2006.246.07:38:18.17#ibcon#about to read 4, iclass 24, count 0 2006.246.07:38:18.17#ibcon#read 4, iclass 24, count 0 2006.246.07:38:18.17#ibcon#about to read 5, iclass 24, count 0 2006.246.07:38:18.17#ibcon#read 5, iclass 24, count 0 2006.246.07:38:18.17#ibcon#about to read 6, iclass 24, count 0 2006.246.07:38:18.17#ibcon#read 6, iclass 24, count 0 2006.246.07:38:18.17#ibcon#end of sib2, iclass 24, count 0 2006.246.07:38:18.17#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:38:18.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:38:18.17#ibcon#[25=USB\r\n] 2006.246.07:38:18.17#ibcon#*before write, iclass 24, count 0 2006.246.07:38:18.17#ibcon#enter sib2, iclass 24, count 0 2006.246.07:38:18.17#ibcon#flushed, iclass 24, count 0 2006.246.07:38:18.17#ibcon#about to write, iclass 24, count 0 2006.246.07:38:18.17#ibcon#wrote, iclass 24, count 0 2006.246.07:38:18.17#ibcon#about to read 3, iclass 24, count 0 2006.246.07:38:18.21#ibcon#read 3, iclass 24, count 0 2006.246.07:38:18.21#ibcon#about to read 4, iclass 24, count 0 2006.246.07:38:18.21#ibcon#read 4, iclass 24, count 0 2006.246.07:38:18.21#ibcon#about to read 5, iclass 24, count 0 2006.246.07:38:18.21#ibcon#read 5, iclass 24, count 0 2006.246.07:38:18.21#ibcon#about to read 6, iclass 24, count 0 2006.246.07:38:18.21#ibcon#read 6, iclass 24, count 0 2006.246.07:38:18.21#ibcon#end of sib2, iclass 24, count 0 2006.246.07:38:18.21#ibcon#*after write, iclass 24, count 0 2006.246.07:38:18.21#ibcon#*before return 0, iclass 24, count 0 2006.246.07:38:18.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:18.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:18.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:38:18.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:38:18.21$vc4f8/valo=2,572.99 2006.246.07:38:18.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:38:18.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:38:18.21#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:18.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:18.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:18.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:18.21#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:38:18.21#ibcon#first serial, iclass 26, count 0 2006.246.07:38:18.21#ibcon#enter sib2, iclass 26, count 0 2006.246.07:38:18.21#ibcon#flushed, iclass 26, count 0 2006.246.07:38:18.21#ibcon#about to write, iclass 26, count 0 2006.246.07:38:18.21#ibcon#wrote, iclass 26, count 0 2006.246.07:38:18.21#ibcon#about to read 3, iclass 26, count 0 2006.246.07:38:18.23#ibcon#read 3, iclass 26, count 0 2006.246.07:38:18.23#ibcon#about to read 4, iclass 26, count 0 2006.246.07:38:18.23#ibcon#read 4, iclass 26, count 0 2006.246.07:38:18.23#ibcon#about to read 5, iclass 26, count 0 2006.246.07:38:18.23#ibcon#read 5, iclass 26, count 0 2006.246.07:38:18.23#ibcon#about to read 6, iclass 26, count 0 2006.246.07:38:18.23#ibcon#read 6, iclass 26, count 0 2006.246.07:38:18.23#ibcon#end of sib2, iclass 26, count 0 2006.246.07:38:18.23#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:38:18.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:38:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:38:18.23#ibcon#*before write, iclass 26, count 0 2006.246.07:38:18.23#ibcon#enter sib2, iclass 26, count 0 2006.246.07:38:18.23#ibcon#flushed, iclass 26, count 0 2006.246.07:38:18.23#ibcon#about to write, iclass 26, count 0 2006.246.07:38:18.23#ibcon#wrote, iclass 26, count 0 2006.246.07:38:18.23#ibcon#about to read 3, iclass 26, count 0 2006.246.07:38:18.26#ibcon#read 3, iclass 26, count 0 2006.246.07:38:18.26#ibcon#about to read 4, iclass 26, count 0 2006.246.07:38:18.26#ibcon#read 4, iclass 26, count 0 2006.246.07:38:18.26#ibcon#about to read 5, iclass 26, count 0 2006.246.07:38:18.26#ibcon#read 5, iclass 26, count 0 2006.246.07:38:18.26#ibcon#about to read 6, iclass 26, count 0 2006.246.07:38:18.26#ibcon#read 6, iclass 26, count 0 2006.246.07:38:18.26#ibcon#end of sib2, iclass 26, count 0 2006.246.07:38:18.26#ibcon#*after write, iclass 26, count 0 2006.246.07:38:18.26#ibcon#*before return 0, iclass 26, count 0 2006.246.07:38:18.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:18.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:18.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:38:18.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:38:18.27$vc4f8/va=2,7 2006.246.07:38:18.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:38:18.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:38:18.27#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:18.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:18.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:18.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:18.32#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:38:18.32#ibcon#first serial, iclass 28, count 2 2006.246.07:38:18.32#ibcon#enter sib2, iclass 28, count 2 2006.246.07:38:18.32#ibcon#flushed, iclass 28, count 2 2006.246.07:38:18.32#ibcon#about to write, iclass 28, count 2 2006.246.07:38:18.32#ibcon#wrote, iclass 28, count 2 2006.246.07:38:18.32#ibcon#about to read 3, iclass 28, count 2 2006.246.07:38:18.34#ibcon#read 3, iclass 28, count 2 2006.246.07:38:18.34#ibcon#about to read 4, iclass 28, count 2 2006.246.07:38:18.34#ibcon#read 4, iclass 28, count 2 2006.246.07:38:18.34#ibcon#about to read 5, iclass 28, count 2 2006.246.07:38:18.34#ibcon#read 5, iclass 28, count 2 2006.246.07:38:18.34#ibcon#about to read 6, iclass 28, count 2 2006.246.07:38:18.34#ibcon#read 6, iclass 28, count 2 2006.246.07:38:18.34#ibcon#end of sib2, iclass 28, count 2 2006.246.07:38:18.34#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:38:18.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:38:18.34#ibcon#[25=AT02-07\r\n] 2006.246.07:38:18.34#ibcon#*before write, iclass 28, count 2 2006.246.07:38:18.34#ibcon#enter sib2, iclass 28, count 2 2006.246.07:38:18.34#ibcon#flushed, iclass 28, count 2 2006.246.07:38:18.34#ibcon#about to write, iclass 28, count 2 2006.246.07:38:18.34#ibcon#wrote, iclass 28, count 2 2006.246.07:38:18.34#ibcon#about to read 3, iclass 28, count 2 2006.246.07:38:18.37#ibcon#read 3, iclass 28, count 2 2006.246.07:38:18.37#ibcon#about to read 4, iclass 28, count 2 2006.246.07:38:18.37#ibcon#read 4, iclass 28, count 2 2006.246.07:38:18.37#ibcon#about to read 5, iclass 28, count 2 2006.246.07:38:18.37#ibcon#read 5, iclass 28, count 2 2006.246.07:38:18.37#ibcon#about to read 6, iclass 28, count 2 2006.246.07:38:18.37#ibcon#read 6, iclass 28, count 2 2006.246.07:38:18.37#ibcon#end of sib2, iclass 28, count 2 2006.246.07:38:18.37#ibcon#*after write, iclass 28, count 2 2006.246.07:38:18.37#ibcon#*before return 0, iclass 28, count 2 2006.246.07:38:18.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:18.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:18.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:38:18.37#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:18.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:18.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:18.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:18.50#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:38:18.50#ibcon#first serial, iclass 28, count 0 2006.246.07:38:18.50#ibcon#enter sib2, iclass 28, count 0 2006.246.07:38:18.50#ibcon#flushed, iclass 28, count 0 2006.246.07:38:18.50#ibcon#about to write, iclass 28, count 0 2006.246.07:38:18.50#ibcon#wrote, iclass 28, count 0 2006.246.07:38:18.50#ibcon#about to read 3, iclass 28, count 0 2006.246.07:38:18.52#ibcon#read 3, iclass 28, count 0 2006.246.07:38:18.52#ibcon#about to read 4, iclass 28, count 0 2006.246.07:38:18.52#ibcon#read 4, iclass 28, count 0 2006.246.07:38:18.52#ibcon#about to read 5, iclass 28, count 0 2006.246.07:38:18.52#ibcon#read 5, iclass 28, count 0 2006.246.07:38:18.52#ibcon#about to read 6, iclass 28, count 0 2006.246.07:38:18.52#ibcon#read 6, iclass 28, count 0 2006.246.07:38:18.52#ibcon#end of sib2, iclass 28, count 0 2006.246.07:38:18.52#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:38:18.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:38:18.52#ibcon#[25=USB\r\n] 2006.246.07:38:18.52#ibcon#*before write, iclass 28, count 0 2006.246.07:38:18.52#ibcon#enter sib2, iclass 28, count 0 2006.246.07:38:18.52#ibcon#flushed, iclass 28, count 0 2006.246.07:38:18.52#ibcon#about to write, iclass 28, count 0 2006.246.07:38:18.52#ibcon#wrote, iclass 28, count 0 2006.246.07:38:18.52#ibcon#about to read 3, iclass 28, count 0 2006.246.07:38:18.54#ibcon#read 3, iclass 28, count 0 2006.246.07:38:18.54#ibcon#about to read 4, iclass 28, count 0 2006.246.07:38:18.54#ibcon#read 4, iclass 28, count 0 2006.246.07:38:18.54#ibcon#about to read 5, iclass 28, count 0 2006.246.07:38:18.54#ibcon#read 5, iclass 28, count 0 2006.246.07:38:18.54#ibcon#about to read 6, iclass 28, count 0 2006.246.07:38:18.54#ibcon#read 6, iclass 28, count 0 2006.246.07:38:18.54#ibcon#end of sib2, iclass 28, count 0 2006.246.07:38:18.54#ibcon#*after write, iclass 28, count 0 2006.246.07:38:18.54#ibcon#*before return 0, iclass 28, count 0 2006.246.07:38:18.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:18.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:18.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:38:18.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:38:18.55$vc4f8/valo=3,672.99 2006.246.07:38:18.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:38:18.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:38:18.55#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:18.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:18.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:18.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:18.55#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:38:18.55#ibcon#first serial, iclass 30, count 0 2006.246.07:38:18.55#ibcon#enter sib2, iclass 30, count 0 2006.246.07:38:18.55#ibcon#flushed, iclass 30, count 0 2006.246.07:38:18.55#ibcon#about to write, iclass 30, count 0 2006.246.07:38:18.55#ibcon#wrote, iclass 30, count 0 2006.246.07:38:18.55#ibcon#about to read 3, iclass 30, count 0 2006.246.07:38:18.57#ibcon#read 3, iclass 30, count 0 2006.246.07:38:18.57#ibcon#about to read 4, iclass 30, count 0 2006.246.07:38:18.57#ibcon#read 4, iclass 30, count 0 2006.246.07:38:18.57#ibcon#about to read 5, iclass 30, count 0 2006.246.07:38:18.57#ibcon#read 5, iclass 30, count 0 2006.246.07:38:18.57#ibcon#about to read 6, iclass 30, count 0 2006.246.07:38:18.57#ibcon#read 6, iclass 30, count 0 2006.246.07:38:18.57#ibcon#end of sib2, iclass 30, count 0 2006.246.07:38:18.57#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:38:18.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:38:18.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:38:18.57#ibcon#*before write, iclass 30, count 0 2006.246.07:38:18.57#ibcon#enter sib2, iclass 30, count 0 2006.246.07:38:18.57#ibcon#flushed, iclass 30, count 0 2006.246.07:38:18.57#ibcon#about to write, iclass 30, count 0 2006.246.07:38:18.57#ibcon#wrote, iclass 30, count 0 2006.246.07:38:18.57#ibcon#about to read 3, iclass 30, count 0 2006.246.07:38:18.60#ibcon#read 3, iclass 30, count 0 2006.246.07:38:18.60#ibcon#about to read 4, iclass 30, count 0 2006.246.07:38:18.60#ibcon#read 4, iclass 30, count 0 2006.246.07:38:18.60#ibcon#about to read 5, iclass 30, count 0 2006.246.07:38:18.60#ibcon#read 5, iclass 30, count 0 2006.246.07:38:18.60#ibcon#about to read 6, iclass 30, count 0 2006.246.07:38:18.60#ibcon#read 6, iclass 30, count 0 2006.246.07:38:18.60#ibcon#end of sib2, iclass 30, count 0 2006.246.07:38:18.60#ibcon#*after write, iclass 30, count 0 2006.246.07:38:18.60#ibcon#*before return 0, iclass 30, count 0 2006.246.07:38:18.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:18.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:18.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:38:18.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:38:18.61$vc4f8/va=3,6 2006.246.07:38:18.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:38:18.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:38:18.61#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:18.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:18.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:18.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:18.65#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:38:18.65#ibcon#first serial, iclass 32, count 2 2006.246.07:38:18.65#ibcon#enter sib2, iclass 32, count 2 2006.246.07:38:18.65#ibcon#flushed, iclass 32, count 2 2006.246.07:38:18.65#ibcon#about to write, iclass 32, count 2 2006.246.07:38:18.65#ibcon#wrote, iclass 32, count 2 2006.246.07:38:18.65#ibcon#about to read 3, iclass 32, count 2 2006.246.07:38:18.68#ibcon#read 3, iclass 32, count 2 2006.246.07:38:18.68#ibcon#about to read 4, iclass 32, count 2 2006.246.07:38:18.68#ibcon#read 4, iclass 32, count 2 2006.246.07:38:18.68#ibcon#about to read 5, iclass 32, count 2 2006.246.07:38:18.68#ibcon#read 5, iclass 32, count 2 2006.246.07:38:18.68#ibcon#about to read 6, iclass 32, count 2 2006.246.07:38:18.68#ibcon#read 6, iclass 32, count 2 2006.246.07:38:18.68#ibcon#end of sib2, iclass 32, count 2 2006.246.07:38:18.68#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:38:18.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:38:18.68#ibcon#[25=AT03-06\r\n] 2006.246.07:38:18.68#ibcon#*before write, iclass 32, count 2 2006.246.07:38:18.68#ibcon#enter sib2, iclass 32, count 2 2006.246.07:38:18.68#ibcon#flushed, iclass 32, count 2 2006.246.07:38:18.68#ibcon#about to write, iclass 32, count 2 2006.246.07:38:18.68#ibcon#wrote, iclass 32, count 2 2006.246.07:38:18.68#ibcon#about to read 3, iclass 32, count 2 2006.246.07:38:18.71#ibcon#read 3, iclass 32, count 2 2006.246.07:38:18.71#ibcon#about to read 4, iclass 32, count 2 2006.246.07:38:18.71#ibcon#read 4, iclass 32, count 2 2006.246.07:38:18.71#ibcon#about to read 5, iclass 32, count 2 2006.246.07:38:18.71#ibcon#read 5, iclass 32, count 2 2006.246.07:38:18.71#ibcon#about to read 6, iclass 32, count 2 2006.246.07:38:18.71#ibcon#read 6, iclass 32, count 2 2006.246.07:38:18.71#ibcon#end of sib2, iclass 32, count 2 2006.246.07:38:18.71#ibcon#*after write, iclass 32, count 2 2006.246.07:38:18.71#ibcon#*before return 0, iclass 32, count 2 2006.246.07:38:18.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:18.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:18.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:38:18.71#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:18.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:18.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:18.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:18.83#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:38:18.83#ibcon#first serial, iclass 32, count 0 2006.246.07:38:18.83#ibcon#enter sib2, iclass 32, count 0 2006.246.07:38:18.83#ibcon#flushed, iclass 32, count 0 2006.246.07:38:18.83#ibcon#about to write, iclass 32, count 0 2006.246.07:38:18.83#ibcon#wrote, iclass 32, count 0 2006.246.07:38:18.83#ibcon#about to read 3, iclass 32, count 0 2006.246.07:38:18.85#ibcon#read 3, iclass 32, count 0 2006.246.07:38:18.85#ibcon#about to read 4, iclass 32, count 0 2006.246.07:38:18.85#ibcon#read 4, iclass 32, count 0 2006.246.07:38:18.85#ibcon#about to read 5, iclass 32, count 0 2006.246.07:38:18.85#ibcon#read 5, iclass 32, count 0 2006.246.07:38:18.85#ibcon#about to read 6, iclass 32, count 0 2006.246.07:38:18.85#ibcon#read 6, iclass 32, count 0 2006.246.07:38:18.85#ibcon#end of sib2, iclass 32, count 0 2006.246.07:38:18.85#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:38:18.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:38:18.85#ibcon#[25=USB\r\n] 2006.246.07:38:18.85#ibcon#*before write, iclass 32, count 0 2006.246.07:38:18.85#ibcon#enter sib2, iclass 32, count 0 2006.246.07:38:18.85#ibcon#flushed, iclass 32, count 0 2006.246.07:38:18.85#ibcon#about to write, iclass 32, count 0 2006.246.07:38:18.85#ibcon#wrote, iclass 32, count 0 2006.246.07:38:18.85#ibcon#about to read 3, iclass 32, count 0 2006.246.07:38:18.88#ibcon#read 3, iclass 32, count 0 2006.246.07:38:18.88#ibcon#about to read 4, iclass 32, count 0 2006.246.07:38:18.88#ibcon#read 4, iclass 32, count 0 2006.246.07:38:18.88#ibcon#about to read 5, iclass 32, count 0 2006.246.07:38:18.88#ibcon#read 5, iclass 32, count 0 2006.246.07:38:18.88#ibcon#about to read 6, iclass 32, count 0 2006.246.07:38:18.88#ibcon#read 6, iclass 32, count 0 2006.246.07:38:18.88#ibcon#end of sib2, iclass 32, count 0 2006.246.07:38:18.88#ibcon#*after write, iclass 32, count 0 2006.246.07:38:18.88#ibcon#*before return 0, iclass 32, count 0 2006.246.07:38:18.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:18.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:18.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:38:18.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:38:18.89$vc4f8/valo=4,832.99 2006.246.07:38:18.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:38:18.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:38:18.89#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:18.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:18.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:18.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:18.89#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:38:18.89#ibcon#first serial, iclass 34, count 0 2006.246.07:38:18.89#ibcon#enter sib2, iclass 34, count 0 2006.246.07:38:18.89#ibcon#flushed, iclass 34, count 0 2006.246.07:38:18.89#ibcon#about to write, iclass 34, count 0 2006.246.07:38:18.89#ibcon#wrote, iclass 34, count 0 2006.246.07:38:18.89#ibcon#about to read 3, iclass 34, count 0 2006.246.07:38:18.90#ibcon#read 3, iclass 34, count 0 2006.246.07:38:18.90#ibcon#about to read 4, iclass 34, count 0 2006.246.07:38:18.90#ibcon#read 4, iclass 34, count 0 2006.246.07:38:18.90#ibcon#about to read 5, iclass 34, count 0 2006.246.07:38:18.90#ibcon#read 5, iclass 34, count 0 2006.246.07:38:18.90#ibcon#about to read 6, iclass 34, count 0 2006.246.07:38:18.90#ibcon#read 6, iclass 34, count 0 2006.246.07:38:18.90#ibcon#end of sib2, iclass 34, count 0 2006.246.07:38:18.90#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:38:18.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:38:18.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:38:18.90#ibcon#*before write, iclass 34, count 0 2006.246.07:38:18.90#ibcon#enter sib2, iclass 34, count 0 2006.246.07:38:18.90#ibcon#flushed, iclass 34, count 0 2006.246.07:38:18.90#ibcon#about to write, iclass 34, count 0 2006.246.07:38:18.90#ibcon#wrote, iclass 34, count 0 2006.246.07:38:18.90#ibcon#about to read 3, iclass 34, count 0 2006.246.07:38:18.94#ibcon#read 3, iclass 34, count 0 2006.246.07:38:18.94#ibcon#about to read 4, iclass 34, count 0 2006.246.07:38:18.94#ibcon#read 4, iclass 34, count 0 2006.246.07:38:18.94#ibcon#about to read 5, iclass 34, count 0 2006.246.07:38:18.94#ibcon#read 5, iclass 34, count 0 2006.246.07:38:18.94#ibcon#about to read 6, iclass 34, count 0 2006.246.07:38:18.94#ibcon#read 6, iclass 34, count 0 2006.246.07:38:18.94#ibcon#end of sib2, iclass 34, count 0 2006.246.07:38:18.94#ibcon#*after write, iclass 34, count 0 2006.246.07:38:18.94#ibcon#*before return 0, iclass 34, count 0 2006.246.07:38:18.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:18.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:18.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:38:18.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:38:18.95$vc4f8/va=4,7 2006.246.07:38:18.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:38:18.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:38:18.95#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:18.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:18.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:18.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:18.99#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:38:18.99#ibcon#first serial, iclass 36, count 2 2006.246.07:38:18.99#ibcon#enter sib2, iclass 36, count 2 2006.246.07:38:18.99#ibcon#flushed, iclass 36, count 2 2006.246.07:38:18.99#ibcon#about to write, iclass 36, count 2 2006.246.07:38:18.99#ibcon#wrote, iclass 36, count 2 2006.246.07:38:18.99#ibcon#about to read 3, iclass 36, count 2 2006.246.07:38:19.01#ibcon#read 3, iclass 36, count 2 2006.246.07:38:19.01#ibcon#about to read 4, iclass 36, count 2 2006.246.07:38:19.01#ibcon#read 4, iclass 36, count 2 2006.246.07:38:19.01#ibcon#about to read 5, iclass 36, count 2 2006.246.07:38:19.01#ibcon#read 5, iclass 36, count 2 2006.246.07:38:19.01#ibcon#about to read 6, iclass 36, count 2 2006.246.07:38:19.01#ibcon#read 6, iclass 36, count 2 2006.246.07:38:19.01#ibcon#end of sib2, iclass 36, count 2 2006.246.07:38:19.01#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:38:19.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:38:19.01#ibcon#[25=AT04-07\r\n] 2006.246.07:38:19.01#ibcon#*before write, iclass 36, count 2 2006.246.07:38:19.01#ibcon#enter sib2, iclass 36, count 2 2006.246.07:38:19.01#ibcon#flushed, iclass 36, count 2 2006.246.07:38:19.01#ibcon#about to write, iclass 36, count 2 2006.246.07:38:19.01#ibcon#wrote, iclass 36, count 2 2006.246.07:38:19.01#ibcon#about to read 3, iclass 36, count 2 2006.246.07:38:19.04#ibcon#read 3, iclass 36, count 2 2006.246.07:38:19.04#ibcon#about to read 4, iclass 36, count 2 2006.246.07:38:19.04#ibcon#read 4, iclass 36, count 2 2006.246.07:38:19.04#ibcon#about to read 5, iclass 36, count 2 2006.246.07:38:19.04#ibcon#read 5, iclass 36, count 2 2006.246.07:38:19.04#ibcon#about to read 6, iclass 36, count 2 2006.246.07:38:19.04#ibcon#read 6, iclass 36, count 2 2006.246.07:38:19.04#ibcon#end of sib2, iclass 36, count 2 2006.246.07:38:19.04#ibcon#*after write, iclass 36, count 2 2006.246.07:38:19.04#ibcon#*before return 0, iclass 36, count 2 2006.246.07:38:19.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:19.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:19.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:38:19.04#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:19.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:19.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:19.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:19.16#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:38:19.16#ibcon#first serial, iclass 36, count 0 2006.246.07:38:19.16#ibcon#enter sib2, iclass 36, count 0 2006.246.07:38:19.16#ibcon#flushed, iclass 36, count 0 2006.246.07:38:19.16#ibcon#about to write, iclass 36, count 0 2006.246.07:38:19.16#ibcon#wrote, iclass 36, count 0 2006.246.07:38:19.16#ibcon#about to read 3, iclass 36, count 0 2006.246.07:38:19.18#ibcon#read 3, iclass 36, count 0 2006.246.07:38:19.18#ibcon#about to read 4, iclass 36, count 0 2006.246.07:38:19.18#ibcon#read 4, iclass 36, count 0 2006.246.07:38:19.18#ibcon#about to read 5, iclass 36, count 0 2006.246.07:38:19.18#ibcon#read 5, iclass 36, count 0 2006.246.07:38:19.18#ibcon#about to read 6, iclass 36, count 0 2006.246.07:38:19.18#ibcon#read 6, iclass 36, count 0 2006.246.07:38:19.18#ibcon#end of sib2, iclass 36, count 0 2006.246.07:38:19.18#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:38:19.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:38:19.18#ibcon#[25=USB\r\n] 2006.246.07:38:19.18#ibcon#*before write, iclass 36, count 0 2006.246.07:38:19.18#ibcon#enter sib2, iclass 36, count 0 2006.246.07:38:19.18#ibcon#flushed, iclass 36, count 0 2006.246.07:38:19.18#ibcon#about to write, iclass 36, count 0 2006.246.07:38:19.18#ibcon#wrote, iclass 36, count 0 2006.246.07:38:19.18#ibcon#about to read 3, iclass 36, count 0 2006.246.07:38:19.21#ibcon#read 3, iclass 36, count 0 2006.246.07:38:19.21#ibcon#about to read 4, iclass 36, count 0 2006.246.07:38:19.21#ibcon#read 4, iclass 36, count 0 2006.246.07:38:19.21#ibcon#about to read 5, iclass 36, count 0 2006.246.07:38:19.21#ibcon#read 5, iclass 36, count 0 2006.246.07:38:19.21#ibcon#about to read 6, iclass 36, count 0 2006.246.07:38:19.21#ibcon#read 6, iclass 36, count 0 2006.246.07:38:19.21#ibcon#end of sib2, iclass 36, count 0 2006.246.07:38:19.21#ibcon#*after write, iclass 36, count 0 2006.246.07:38:19.21#ibcon#*before return 0, iclass 36, count 0 2006.246.07:38:19.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:19.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:19.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:38:19.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:38:19.22$vc4f8/valo=5,652.99 2006.246.07:38:19.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:38:19.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:38:19.22#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:19.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:19.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:19.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:19.22#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:38:19.22#ibcon#first serial, iclass 38, count 0 2006.246.07:38:19.22#ibcon#enter sib2, iclass 38, count 0 2006.246.07:38:19.22#ibcon#flushed, iclass 38, count 0 2006.246.07:38:19.22#ibcon#about to write, iclass 38, count 0 2006.246.07:38:19.22#ibcon#wrote, iclass 38, count 0 2006.246.07:38:19.22#ibcon#about to read 3, iclass 38, count 0 2006.246.07:38:19.23#ibcon#read 3, iclass 38, count 0 2006.246.07:38:19.23#ibcon#about to read 4, iclass 38, count 0 2006.246.07:38:19.23#ibcon#read 4, iclass 38, count 0 2006.246.07:38:19.23#ibcon#about to read 5, iclass 38, count 0 2006.246.07:38:19.23#ibcon#read 5, iclass 38, count 0 2006.246.07:38:19.23#ibcon#about to read 6, iclass 38, count 0 2006.246.07:38:19.23#ibcon#read 6, iclass 38, count 0 2006.246.07:38:19.23#ibcon#end of sib2, iclass 38, count 0 2006.246.07:38:19.23#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:38:19.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:38:19.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:38:19.23#ibcon#*before write, iclass 38, count 0 2006.246.07:38:19.23#ibcon#enter sib2, iclass 38, count 0 2006.246.07:38:19.23#ibcon#flushed, iclass 38, count 0 2006.246.07:38:19.23#ibcon#about to write, iclass 38, count 0 2006.246.07:38:19.23#ibcon#wrote, iclass 38, count 0 2006.246.07:38:19.23#ibcon#about to read 3, iclass 38, count 0 2006.246.07:38:19.27#ibcon#read 3, iclass 38, count 0 2006.246.07:38:19.27#ibcon#about to read 4, iclass 38, count 0 2006.246.07:38:19.27#ibcon#read 4, iclass 38, count 0 2006.246.07:38:19.27#ibcon#about to read 5, iclass 38, count 0 2006.246.07:38:19.27#ibcon#read 5, iclass 38, count 0 2006.246.07:38:19.27#ibcon#about to read 6, iclass 38, count 0 2006.246.07:38:19.27#ibcon#read 6, iclass 38, count 0 2006.246.07:38:19.27#ibcon#end of sib2, iclass 38, count 0 2006.246.07:38:19.27#ibcon#*after write, iclass 38, count 0 2006.246.07:38:19.27#ibcon#*before return 0, iclass 38, count 0 2006.246.07:38:19.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:19.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:19.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:38:19.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:38:19.28$vc4f8/va=5,7 2006.246.07:38:19.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.07:38:19.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.07:38:19.28#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:19.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:19.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:19.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:19.32#ibcon#enter wrdev, iclass 40, count 2 2006.246.07:38:19.32#ibcon#first serial, iclass 40, count 2 2006.246.07:38:19.32#ibcon#enter sib2, iclass 40, count 2 2006.246.07:38:19.32#ibcon#flushed, iclass 40, count 2 2006.246.07:38:19.32#ibcon#about to write, iclass 40, count 2 2006.246.07:38:19.32#ibcon#wrote, iclass 40, count 2 2006.246.07:38:19.32#ibcon#about to read 3, iclass 40, count 2 2006.246.07:38:19.34#ibcon#read 3, iclass 40, count 2 2006.246.07:38:19.34#ibcon#about to read 4, iclass 40, count 2 2006.246.07:38:19.34#ibcon#read 4, iclass 40, count 2 2006.246.07:38:19.34#ibcon#about to read 5, iclass 40, count 2 2006.246.07:38:19.34#ibcon#read 5, iclass 40, count 2 2006.246.07:38:19.34#ibcon#about to read 6, iclass 40, count 2 2006.246.07:38:19.34#ibcon#read 6, iclass 40, count 2 2006.246.07:38:19.34#ibcon#end of sib2, iclass 40, count 2 2006.246.07:38:19.34#ibcon#*mode == 0, iclass 40, count 2 2006.246.07:38:19.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.07:38:19.34#ibcon#[25=AT05-07\r\n] 2006.246.07:38:19.34#ibcon#*before write, iclass 40, count 2 2006.246.07:38:19.34#ibcon#enter sib2, iclass 40, count 2 2006.246.07:38:19.34#ibcon#flushed, iclass 40, count 2 2006.246.07:38:19.34#ibcon#about to write, iclass 40, count 2 2006.246.07:38:19.34#ibcon#wrote, iclass 40, count 2 2006.246.07:38:19.34#ibcon#about to read 3, iclass 40, count 2 2006.246.07:38:19.37#ibcon#read 3, iclass 40, count 2 2006.246.07:38:19.37#ibcon#about to read 4, iclass 40, count 2 2006.246.07:38:19.37#ibcon#read 4, iclass 40, count 2 2006.246.07:38:19.37#ibcon#about to read 5, iclass 40, count 2 2006.246.07:38:19.37#ibcon#read 5, iclass 40, count 2 2006.246.07:38:19.37#ibcon#about to read 6, iclass 40, count 2 2006.246.07:38:19.37#ibcon#read 6, iclass 40, count 2 2006.246.07:38:19.37#ibcon#end of sib2, iclass 40, count 2 2006.246.07:38:19.37#ibcon#*after write, iclass 40, count 2 2006.246.07:38:19.37#ibcon#*before return 0, iclass 40, count 2 2006.246.07:38:19.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:19.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:19.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.07:38:19.37#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:19.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:19.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:19.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:19.49#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:38:19.49#ibcon#first serial, iclass 40, count 0 2006.246.07:38:19.49#ibcon#enter sib2, iclass 40, count 0 2006.246.07:38:19.49#ibcon#flushed, iclass 40, count 0 2006.246.07:38:19.49#ibcon#about to write, iclass 40, count 0 2006.246.07:38:19.49#ibcon#wrote, iclass 40, count 0 2006.246.07:38:19.49#ibcon#about to read 3, iclass 40, count 0 2006.246.07:38:19.51#ibcon#read 3, iclass 40, count 0 2006.246.07:38:19.51#ibcon#about to read 4, iclass 40, count 0 2006.246.07:38:19.51#ibcon#read 4, iclass 40, count 0 2006.246.07:38:19.51#ibcon#about to read 5, iclass 40, count 0 2006.246.07:38:19.51#ibcon#read 5, iclass 40, count 0 2006.246.07:38:19.51#ibcon#about to read 6, iclass 40, count 0 2006.246.07:38:19.51#ibcon#read 6, iclass 40, count 0 2006.246.07:38:19.51#ibcon#end of sib2, iclass 40, count 0 2006.246.07:38:19.51#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:38:19.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:38:19.51#ibcon#[25=USB\r\n] 2006.246.07:38:19.51#ibcon#*before write, iclass 40, count 0 2006.246.07:38:19.51#ibcon#enter sib2, iclass 40, count 0 2006.246.07:38:19.51#ibcon#flushed, iclass 40, count 0 2006.246.07:38:19.51#ibcon#about to write, iclass 40, count 0 2006.246.07:38:19.51#ibcon#wrote, iclass 40, count 0 2006.246.07:38:19.51#ibcon#about to read 3, iclass 40, count 0 2006.246.07:38:19.54#ibcon#read 3, iclass 40, count 0 2006.246.07:38:19.54#ibcon#about to read 4, iclass 40, count 0 2006.246.07:38:19.54#ibcon#read 4, iclass 40, count 0 2006.246.07:38:19.54#ibcon#about to read 5, iclass 40, count 0 2006.246.07:38:19.54#ibcon#read 5, iclass 40, count 0 2006.246.07:38:19.54#ibcon#about to read 6, iclass 40, count 0 2006.246.07:38:19.54#ibcon#read 6, iclass 40, count 0 2006.246.07:38:19.54#ibcon#end of sib2, iclass 40, count 0 2006.246.07:38:19.54#ibcon#*after write, iclass 40, count 0 2006.246.07:38:19.54#ibcon#*before return 0, iclass 40, count 0 2006.246.07:38:19.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:19.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:19.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:38:19.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:38:19.55$vc4f8/valo=6,772.99 2006.246.07:38:19.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.07:38:19.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.07:38:19.55#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:19.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:19.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:19.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:19.55#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:38:19.55#ibcon#first serial, iclass 4, count 0 2006.246.07:38:19.55#ibcon#enter sib2, iclass 4, count 0 2006.246.07:38:19.55#ibcon#flushed, iclass 4, count 0 2006.246.07:38:19.55#ibcon#about to write, iclass 4, count 0 2006.246.07:38:19.55#ibcon#wrote, iclass 4, count 0 2006.246.07:38:19.55#ibcon#about to read 3, iclass 4, count 0 2006.246.07:38:19.57#ibcon#read 3, iclass 4, count 0 2006.246.07:38:19.57#ibcon#about to read 4, iclass 4, count 0 2006.246.07:38:19.57#ibcon#read 4, iclass 4, count 0 2006.246.07:38:19.57#ibcon#about to read 5, iclass 4, count 0 2006.246.07:38:19.57#ibcon#read 5, iclass 4, count 0 2006.246.07:38:19.57#ibcon#about to read 6, iclass 4, count 0 2006.246.07:38:19.57#ibcon#read 6, iclass 4, count 0 2006.246.07:38:19.57#ibcon#end of sib2, iclass 4, count 0 2006.246.07:38:19.57#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:38:19.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:38:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:38:19.57#ibcon#*before write, iclass 4, count 0 2006.246.07:38:19.57#ibcon#enter sib2, iclass 4, count 0 2006.246.07:38:19.57#ibcon#flushed, iclass 4, count 0 2006.246.07:38:19.57#ibcon#about to write, iclass 4, count 0 2006.246.07:38:19.57#ibcon#wrote, iclass 4, count 0 2006.246.07:38:19.57#ibcon#about to read 3, iclass 4, count 0 2006.246.07:38:19.60#ibcon#read 3, iclass 4, count 0 2006.246.07:38:19.60#ibcon#about to read 4, iclass 4, count 0 2006.246.07:38:19.60#ibcon#read 4, iclass 4, count 0 2006.246.07:38:19.60#ibcon#about to read 5, iclass 4, count 0 2006.246.07:38:19.60#ibcon#read 5, iclass 4, count 0 2006.246.07:38:19.60#ibcon#about to read 6, iclass 4, count 0 2006.246.07:38:19.60#ibcon#read 6, iclass 4, count 0 2006.246.07:38:19.60#ibcon#end of sib2, iclass 4, count 0 2006.246.07:38:19.60#ibcon#*after write, iclass 4, count 0 2006.246.07:38:19.60#ibcon#*before return 0, iclass 4, count 0 2006.246.07:38:19.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:19.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:19.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:38:19.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:38:19.61$vc4f8/va=6,7 2006.246.07:38:19.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.07:38:19.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.07:38:19.61#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:19.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:38:19.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:38:19.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:38:19.65#ibcon#enter wrdev, iclass 6, count 2 2006.246.07:38:19.65#ibcon#first serial, iclass 6, count 2 2006.246.07:38:19.65#ibcon#enter sib2, iclass 6, count 2 2006.246.07:38:19.65#ibcon#flushed, iclass 6, count 2 2006.246.07:38:19.65#ibcon#about to write, iclass 6, count 2 2006.246.07:38:19.65#ibcon#wrote, iclass 6, count 2 2006.246.07:38:19.65#ibcon#about to read 3, iclass 6, count 2 2006.246.07:38:19.67#ibcon#read 3, iclass 6, count 2 2006.246.07:38:19.67#ibcon#about to read 4, iclass 6, count 2 2006.246.07:38:19.67#ibcon#read 4, iclass 6, count 2 2006.246.07:38:19.67#ibcon#about to read 5, iclass 6, count 2 2006.246.07:38:19.67#ibcon#read 5, iclass 6, count 2 2006.246.07:38:19.67#ibcon#about to read 6, iclass 6, count 2 2006.246.07:38:19.67#ibcon#read 6, iclass 6, count 2 2006.246.07:38:19.67#ibcon#end of sib2, iclass 6, count 2 2006.246.07:38:19.67#ibcon#*mode == 0, iclass 6, count 2 2006.246.07:38:19.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.07:38:19.67#ibcon#[25=AT06-07\r\n] 2006.246.07:38:19.67#ibcon#*before write, iclass 6, count 2 2006.246.07:38:19.67#ibcon#enter sib2, iclass 6, count 2 2006.246.07:38:19.67#ibcon#flushed, iclass 6, count 2 2006.246.07:38:19.67#ibcon#about to write, iclass 6, count 2 2006.246.07:38:19.67#ibcon#wrote, iclass 6, count 2 2006.246.07:38:19.67#ibcon#about to read 3, iclass 6, count 2 2006.246.07:38:19.70#ibcon#read 3, iclass 6, count 2 2006.246.07:38:19.70#ibcon#about to read 4, iclass 6, count 2 2006.246.07:38:19.70#ibcon#read 4, iclass 6, count 2 2006.246.07:38:19.70#ibcon#about to read 5, iclass 6, count 2 2006.246.07:38:19.70#ibcon#read 5, iclass 6, count 2 2006.246.07:38:19.70#ibcon#about to read 6, iclass 6, count 2 2006.246.07:38:19.70#ibcon#read 6, iclass 6, count 2 2006.246.07:38:19.70#ibcon#end of sib2, iclass 6, count 2 2006.246.07:38:19.70#ibcon#*after write, iclass 6, count 2 2006.246.07:38:19.70#ibcon#*before return 0, iclass 6, count 2 2006.246.07:38:19.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:38:19.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:38:19.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.07:38:19.70#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:19.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:38:19.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:38:19.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:38:19.82#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:38:19.82#ibcon#first serial, iclass 6, count 0 2006.246.07:38:19.82#ibcon#enter sib2, iclass 6, count 0 2006.246.07:38:19.82#ibcon#flushed, iclass 6, count 0 2006.246.07:38:19.82#ibcon#about to write, iclass 6, count 0 2006.246.07:38:19.82#ibcon#wrote, iclass 6, count 0 2006.246.07:38:19.82#ibcon#about to read 3, iclass 6, count 0 2006.246.07:38:19.84#ibcon#read 3, iclass 6, count 0 2006.246.07:38:19.84#ibcon#about to read 4, iclass 6, count 0 2006.246.07:38:19.84#ibcon#read 4, iclass 6, count 0 2006.246.07:38:19.84#ibcon#about to read 5, iclass 6, count 0 2006.246.07:38:19.84#ibcon#read 5, iclass 6, count 0 2006.246.07:38:19.84#ibcon#about to read 6, iclass 6, count 0 2006.246.07:38:19.84#ibcon#read 6, iclass 6, count 0 2006.246.07:38:19.84#ibcon#end of sib2, iclass 6, count 0 2006.246.07:38:19.84#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:38:19.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:38:19.84#ibcon#[25=USB\r\n] 2006.246.07:38:19.84#ibcon#*before write, iclass 6, count 0 2006.246.07:38:19.84#ibcon#enter sib2, iclass 6, count 0 2006.246.07:38:19.84#ibcon#flushed, iclass 6, count 0 2006.246.07:38:19.84#ibcon#about to write, iclass 6, count 0 2006.246.07:38:19.84#ibcon#wrote, iclass 6, count 0 2006.246.07:38:19.84#ibcon#about to read 3, iclass 6, count 0 2006.246.07:38:19.87#ibcon#read 3, iclass 6, count 0 2006.246.07:38:19.87#ibcon#about to read 4, iclass 6, count 0 2006.246.07:38:19.87#ibcon#read 4, iclass 6, count 0 2006.246.07:38:19.87#ibcon#about to read 5, iclass 6, count 0 2006.246.07:38:19.87#ibcon#read 5, iclass 6, count 0 2006.246.07:38:19.87#ibcon#about to read 6, iclass 6, count 0 2006.246.07:38:19.87#ibcon#read 6, iclass 6, count 0 2006.246.07:38:19.87#ibcon#end of sib2, iclass 6, count 0 2006.246.07:38:19.87#ibcon#*after write, iclass 6, count 0 2006.246.07:38:19.87#ibcon#*before return 0, iclass 6, count 0 2006.246.07:38:19.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:38:19.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:38:19.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:38:19.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:38:19.88$vc4f8/valo=7,832.99 2006.246.07:38:19.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.07:38:19.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.07:38:19.88#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:19.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:38:19.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:38:19.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:38:19.88#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:38:19.88#ibcon#first serial, iclass 10, count 0 2006.246.07:38:19.88#ibcon#enter sib2, iclass 10, count 0 2006.246.07:38:19.88#ibcon#flushed, iclass 10, count 0 2006.246.07:38:19.88#ibcon#about to write, iclass 10, count 0 2006.246.07:38:19.88#ibcon#wrote, iclass 10, count 0 2006.246.07:38:19.88#ibcon#about to read 3, iclass 10, count 0 2006.246.07:38:19.89#ibcon#read 3, iclass 10, count 0 2006.246.07:38:19.89#ibcon#about to read 4, iclass 10, count 0 2006.246.07:38:19.89#ibcon#read 4, iclass 10, count 0 2006.246.07:38:19.89#ibcon#about to read 5, iclass 10, count 0 2006.246.07:38:19.89#ibcon#read 5, iclass 10, count 0 2006.246.07:38:19.89#ibcon#about to read 6, iclass 10, count 0 2006.246.07:38:19.89#ibcon#read 6, iclass 10, count 0 2006.246.07:38:19.89#ibcon#end of sib2, iclass 10, count 0 2006.246.07:38:19.89#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:38:19.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:38:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:38:19.89#ibcon#*before write, iclass 10, count 0 2006.246.07:38:19.89#ibcon#enter sib2, iclass 10, count 0 2006.246.07:38:19.89#ibcon#flushed, iclass 10, count 0 2006.246.07:38:19.89#ibcon#about to write, iclass 10, count 0 2006.246.07:38:19.89#ibcon#wrote, iclass 10, count 0 2006.246.07:38:19.89#ibcon#about to read 3, iclass 10, count 0 2006.246.07:38:19.93#ibcon#read 3, iclass 10, count 0 2006.246.07:38:19.93#ibcon#about to read 4, iclass 10, count 0 2006.246.07:38:19.93#ibcon#read 4, iclass 10, count 0 2006.246.07:38:19.93#ibcon#about to read 5, iclass 10, count 0 2006.246.07:38:19.93#ibcon#read 5, iclass 10, count 0 2006.246.07:38:19.93#ibcon#about to read 6, iclass 10, count 0 2006.246.07:38:19.93#ibcon#read 6, iclass 10, count 0 2006.246.07:38:19.93#ibcon#end of sib2, iclass 10, count 0 2006.246.07:38:19.93#ibcon#*after write, iclass 10, count 0 2006.246.07:38:19.93#ibcon#*before return 0, iclass 10, count 0 2006.246.07:38:19.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:38:19.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:38:19.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:38:19.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:38:19.94$vc4f8/va=7,7 2006.246.07:38:19.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.07:38:19.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.07:38:19.94#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:19.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:38:19.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:38:19.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:38:19.98#ibcon#enter wrdev, iclass 12, count 2 2006.246.07:38:19.98#ibcon#first serial, iclass 12, count 2 2006.246.07:38:19.98#ibcon#enter sib2, iclass 12, count 2 2006.246.07:38:19.98#ibcon#flushed, iclass 12, count 2 2006.246.07:38:19.98#ibcon#about to write, iclass 12, count 2 2006.246.07:38:19.98#ibcon#wrote, iclass 12, count 2 2006.246.07:38:19.98#ibcon#about to read 3, iclass 12, count 2 2006.246.07:38:20.00#ibcon#read 3, iclass 12, count 2 2006.246.07:38:20.00#ibcon#about to read 4, iclass 12, count 2 2006.246.07:38:20.00#ibcon#read 4, iclass 12, count 2 2006.246.07:38:20.00#ibcon#about to read 5, iclass 12, count 2 2006.246.07:38:20.00#ibcon#read 5, iclass 12, count 2 2006.246.07:38:20.00#ibcon#about to read 6, iclass 12, count 2 2006.246.07:38:20.00#ibcon#read 6, iclass 12, count 2 2006.246.07:38:20.00#ibcon#end of sib2, iclass 12, count 2 2006.246.07:38:20.00#ibcon#*mode == 0, iclass 12, count 2 2006.246.07:38:20.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.07:38:20.00#ibcon#[25=AT07-07\r\n] 2006.246.07:38:20.00#ibcon#*before write, iclass 12, count 2 2006.246.07:38:20.00#ibcon#enter sib2, iclass 12, count 2 2006.246.07:38:20.00#ibcon#flushed, iclass 12, count 2 2006.246.07:38:20.00#ibcon#about to write, iclass 12, count 2 2006.246.07:38:20.00#ibcon#wrote, iclass 12, count 2 2006.246.07:38:20.00#ibcon#about to read 3, iclass 12, count 2 2006.246.07:38:20.03#ibcon#read 3, iclass 12, count 2 2006.246.07:38:20.03#ibcon#about to read 4, iclass 12, count 2 2006.246.07:38:20.03#ibcon#read 4, iclass 12, count 2 2006.246.07:38:20.03#ibcon#about to read 5, iclass 12, count 2 2006.246.07:38:20.03#ibcon#read 5, iclass 12, count 2 2006.246.07:38:20.03#ibcon#about to read 6, iclass 12, count 2 2006.246.07:38:20.03#ibcon#read 6, iclass 12, count 2 2006.246.07:38:20.03#ibcon#end of sib2, iclass 12, count 2 2006.246.07:38:20.03#ibcon#*after write, iclass 12, count 2 2006.246.07:38:20.03#ibcon#*before return 0, iclass 12, count 2 2006.246.07:38:20.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:38:20.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:38:20.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.07:38:20.03#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:20.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:38:20.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:38:20.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:38:20.15#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:38:20.15#ibcon#first serial, iclass 12, count 0 2006.246.07:38:20.15#ibcon#enter sib2, iclass 12, count 0 2006.246.07:38:20.15#ibcon#flushed, iclass 12, count 0 2006.246.07:38:20.15#ibcon#about to write, iclass 12, count 0 2006.246.07:38:20.15#ibcon#wrote, iclass 12, count 0 2006.246.07:38:20.15#ibcon#about to read 3, iclass 12, count 0 2006.246.07:38:20.17#ibcon#read 3, iclass 12, count 0 2006.246.07:38:20.17#ibcon#about to read 4, iclass 12, count 0 2006.246.07:38:20.17#ibcon#read 4, iclass 12, count 0 2006.246.07:38:20.17#ibcon#about to read 5, iclass 12, count 0 2006.246.07:38:20.17#ibcon#read 5, iclass 12, count 0 2006.246.07:38:20.17#ibcon#about to read 6, iclass 12, count 0 2006.246.07:38:20.17#ibcon#read 6, iclass 12, count 0 2006.246.07:38:20.17#ibcon#end of sib2, iclass 12, count 0 2006.246.07:38:20.17#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:38:20.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:38:20.17#ibcon#[25=USB\r\n] 2006.246.07:38:20.17#ibcon#*before write, iclass 12, count 0 2006.246.07:38:20.17#ibcon#enter sib2, iclass 12, count 0 2006.246.07:38:20.17#ibcon#flushed, iclass 12, count 0 2006.246.07:38:20.17#ibcon#about to write, iclass 12, count 0 2006.246.07:38:20.17#ibcon#wrote, iclass 12, count 0 2006.246.07:38:20.17#ibcon#about to read 3, iclass 12, count 0 2006.246.07:38:20.20#ibcon#read 3, iclass 12, count 0 2006.246.07:38:20.20#ibcon#about to read 4, iclass 12, count 0 2006.246.07:38:20.20#ibcon#read 4, iclass 12, count 0 2006.246.07:38:20.20#ibcon#about to read 5, iclass 12, count 0 2006.246.07:38:20.20#ibcon#read 5, iclass 12, count 0 2006.246.07:38:20.20#ibcon#about to read 6, iclass 12, count 0 2006.246.07:38:20.20#ibcon#read 6, iclass 12, count 0 2006.246.07:38:20.20#ibcon#end of sib2, iclass 12, count 0 2006.246.07:38:20.20#ibcon#*after write, iclass 12, count 0 2006.246.07:38:20.20#ibcon#*before return 0, iclass 12, count 0 2006.246.07:38:20.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:38:20.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:38:20.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:38:20.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:38:20.21$vc4f8/valo=8,852.99 2006.246.07:38:20.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.07:38:20.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.07:38:20.21#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:20.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:38:20.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:38:20.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:38:20.21#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:38:20.21#ibcon#first serial, iclass 14, count 0 2006.246.07:38:20.21#ibcon#enter sib2, iclass 14, count 0 2006.246.07:38:20.21#ibcon#flushed, iclass 14, count 0 2006.246.07:38:20.21#ibcon#about to write, iclass 14, count 0 2006.246.07:38:20.21#ibcon#wrote, iclass 14, count 0 2006.246.07:38:20.21#ibcon#about to read 3, iclass 14, count 0 2006.246.07:38:20.22#ibcon#read 3, iclass 14, count 0 2006.246.07:38:20.22#ibcon#about to read 4, iclass 14, count 0 2006.246.07:38:20.22#ibcon#read 4, iclass 14, count 0 2006.246.07:38:20.22#ibcon#about to read 5, iclass 14, count 0 2006.246.07:38:20.22#ibcon#read 5, iclass 14, count 0 2006.246.07:38:20.22#ibcon#about to read 6, iclass 14, count 0 2006.246.07:38:20.22#ibcon#read 6, iclass 14, count 0 2006.246.07:38:20.22#ibcon#end of sib2, iclass 14, count 0 2006.246.07:38:20.22#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:38:20.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:38:20.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:38:20.22#ibcon#*before write, iclass 14, count 0 2006.246.07:38:20.22#ibcon#enter sib2, iclass 14, count 0 2006.246.07:38:20.22#ibcon#flushed, iclass 14, count 0 2006.246.07:38:20.22#ibcon#about to write, iclass 14, count 0 2006.246.07:38:20.22#ibcon#wrote, iclass 14, count 0 2006.246.07:38:20.22#ibcon#about to read 3, iclass 14, count 0 2006.246.07:38:20.26#ibcon#read 3, iclass 14, count 0 2006.246.07:38:20.26#ibcon#about to read 4, iclass 14, count 0 2006.246.07:38:20.26#ibcon#read 4, iclass 14, count 0 2006.246.07:38:20.26#ibcon#about to read 5, iclass 14, count 0 2006.246.07:38:20.26#ibcon#read 5, iclass 14, count 0 2006.246.07:38:20.26#ibcon#about to read 6, iclass 14, count 0 2006.246.07:38:20.26#ibcon#read 6, iclass 14, count 0 2006.246.07:38:20.26#ibcon#end of sib2, iclass 14, count 0 2006.246.07:38:20.26#ibcon#*after write, iclass 14, count 0 2006.246.07:38:20.26#ibcon#*before return 0, iclass 14, count 0 2006.246.07:38:20.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:38:20.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:38:20.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:38:20.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:38:20.27$vc4f8/va=8,8 2006.246.07:38:20.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.07:38:20.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.07:38:20.27#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:20.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:38:20.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:38:20.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:38:20.31#ibcon#enter wrdev, iclass 16, count 2 2006.246.07:38:20.31#ibcon#first serial, iclass 16, count 2 2006.246.07:38:20.31#ibcon#enter sib2, iclass 16, count 2 2006.246.07:38:20.31#ibcon#flushed, iclass 16, count 2 2006.246.07:38:20.31#ibcon#about to write, iclass 16, count 2 2006.246.07:38:20.31#ibcon#wrote, iclass 16, count 2 2006.246.07:38:20.31#ibcon#about to read 3, iclass 16, count 2 2006.246.07:38:20.33#ibcon#read 3, iclass 16, count 2 2006.246.07:38:20.33#ibcon#about to read 4, iclass 16, count 2 2006.246.07:38:20.33#ibcon#read 4, iclass 16, count 2 2006.246.07:38:20.33#ibcon#about to read 5, iclass 16, count 2 2006.246.07:38:20.33#ibcon#read 5, iclass 16, count 2 2006.246.07:38:20.33#ibcon#about to read 6, iclass 16, count 2 2006.246.07:38:20.33#ibcon#read 6, iclass 16, count 2 2006.246.07:38:20.33#ibcon#end of sib2, iclass 16, count 2 2006.246.07:38:20.33#ibcon#*mode == 0, iclass 16, count 2 2006.246.07:38:20.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.07:38:20.33#ibcon#[25=AT08-08\r\n] 2006.246.07:38:20.33#ibcon#*before write, iclass 16, count 2 2006.246.07:38:20.33#ibcon#enter sib2, iclass 16, count 2 2006.246.07:38:20.33#ibcon#flushed, iclass 16, count 2 2006.246.07:38:20.33#ibcon#about to write, iclass 16, count 2 2006.246.07:38:20.33#ibcon#wrote, iclass 16, count 2 2006.246.07:38:20.33#ibcon#about to read 3, iclass 16, count 2 2006.246.07:38:20.36#ibcon#read 3, iclass 16, count 2 2006.246.07:38:20.36#ibcon#about to read 4, iclass 16, count 2 2006.246.07:38:20.36#ibcon#read 4, iclass 16, count 2 2006.246.07:38:20.36#ibcon#about to read 5, iclass 16, count 2 2006.246.07:38:20.36#ibcon#read 5, iclass 16, count 2 2006.246.07:38:20.36#ibcon#about to read 6, iclass 16, count 2 2006.246.07:38:20.36#ibcon#read 6, iclass 16, count 2 2006.246.07:38:20.36#ibcon#end of sib2, iclass 16, count 2 2006.246.07:38:20.36#ibcon#*after write, iclass 16, count 2 2006.246.07:38:20.36#ibcon#*before return 0, iclass 16, count 2 2006.246.07:38:20.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:38:20.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:38:20.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.07:38:20.36#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:20.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:38:20.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:38:20.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:38:20.48#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:38:20.48#ibcon#first serial, iclass 16, count 0 2006.246.07:38:20.48#ibcon#enter sib2, iclass 16, count 0 2006.246.07:38:20.48#ibcon#flushed, iclass 16, count 0 2006.246.07:38:20.48#ibcon#about to write, iclass 16, count 0 2006.246.07:38:20.48#ibcon#wrote, iclass 16, count 0 2006.246.07:38:20.48#ibcon#about to read 3, iclass 16, count 0 2006.246.07:38:20.50#ibcon#read 3, iclass 16, count 0 2006.246.07:38:20.50#ibcon#about to read 4, iclass 16, count 0 2006.246.07:38:20.50#ibcon#read 4, iclass 16, count 0 2006.246.07:38:20.50#ibcon#about to read 5, iclass 16, count 0 2006.246.07:38:20.50#ibcon#read 5, iclass 16, count 0 2006.246.07:38:20.50#ibcon#about to read 6, iclass 16, count 0 2006.246.07:38:20.50#ibcon#read 6, iclass 16, count 0 2006.246.07:38:20.50#ibcon#end of sib2, iclass 16, count 0 2006.246.07:38:20.50#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:38:20.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:38:20.50#ibcon#[25=USB\r\n] 2006.246.07:38:20.50#ibcon#*before write, iclass 16, count 0 2006.246.07:38:20.50#ibcon#enter sib2, iclass 16, count 0 2006.246.07:38:20.50#ibcon#flushed, iclass 16, count 0 2006.246.07:38:20.50#ibcon#about to write, iclass 16, count 0 2006.246.07:38:20.50#ibcon#wrote, iclass 16, count 0 2006.246.07:38:20.50#ibcon#about to read 3, iclass 16, count 0 2006.246.07:38:20.53#ibcon#read 3, iclass 16, count 0 2006.246.07:38:20.53#ibcon#about to read 4, iclass 16, count 0 2006.246.07:38:20.53#ibcon#read 4, iclass 16, count 0 2006.246.07:38:20.53#ibcon#about to read 5, iclass 16, count 0 2006.246.07:38:20.53#ibcon#read 5, iclass 16, count 0 2006.246.07:38:20.53#ibcon#about to read 6, iclass 16, count 0 2006.246.07:38:20.53#ibcon#read 6, iclass 16, count 0 2006.246.07:38:20.53#ibcon#end of sib2, iclass 16, count 0 2006.246.07:38:20.53#ibcon#*after write, iclass 16, count 0 2006.246.07:38:20.53#ibcon#*before return 0, iclass 16, count 0 2006.246.07:38:20.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:38:20.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:38:20.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:38:20.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:38:20.54$vc4f8/vblo=1,632.99 2006.246.07:38:20.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:38:20.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:38:20.54#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:20.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:38:20.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:38:20.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:38:20.54#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:38:20.54#ibcon#first serial, iclass 18, count 0 2006.246.07:38:20.54#ibcon#enter sib2, iclass 18, count 0 2006.246.07:38:20.54#ibcon#flushed, iclass 18, count 0 2006.246.07:38:20.54#ibcon#about to write, iclass 18, count 0 2006.246.07:38:20.54#ibcon#wrote, iclass 18, count 0 2006.246.07:38:20.54#ibcon#about to read 3, iclass 18, count 0 2006.246.07:38:20.55#ibcon#read 3, iclass 18, count 0 2006.246.07:38:20.55#ibcon#about to read 4, iclass 18, count 0 2006.246.07:38:20.55#ibcon#read 4, iclass 18, count 0 2006.246.07:38:20.55#ibcon#about to read 5, iclass 18, count 0 2006.246.07:38:20.55#ibcon#read 5, iclass 18, count 0 2006.246.07:38:20.55#ibcon#about to read 6, iclass 18, count 0 2006.246.07:38:20.55#ibcon#read 6, iclass 18, count 0 2006.246.07:38:20.55#ibcon#end of sib2, iclass 18, count 0 2006.246.07:38:20.55#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:38:20.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:38:20.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:38:20.55#ibcon#*before write, iclass 18, count 0 2006.246.07:38:20.55#ibcon#enter sib2, iclass 18, count 0 2006.246.07:38:20.55#ibcon#flushed, iclass 18, count 0 2006.246.07:38:20.55#ibcon#about to write, iclass 18, count 0 2006.246.07:38:20.55#ibcon#wrote, iclass 18, count 0 2006.246.07:38:20.55#ibcon#about to read 3, iclass 18, count 0 2006.246.07:38:20.59#ibcon#read 3, iclass 18, count 0 2006.246.07:38:20.59#ibcon#about to read 4, iclass 18, count 0 2006.246.07:38:20.59#ibcon#read 4, iclass 18, count 0 2006.246.07:38:20.59#ibcon#about to read 5, iclass 18, count 0 2006.246.07:38:20.59#ibcon#read 5, iclass 18, count 0 2006.246.07:38:20.59#ibcon#about to read 6, iclass 18, count 0 2006.246.07:38:20.59#ibcon#read 6, iclass 18, count 0 2006.246.07:38:20.59#ibcon#end of sib2, iclass 18, count 0 2006.246.07:38:20.59#ibcon#*after write, iclass 18, count 0 2006.246.07:38:20.59#ibcon#*before return 0, iclass 18, count 0 2006.246.07:38:20.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:38:20.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:38:20.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:38:20.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:38:20.60$vc4f8/vb=1,4 2006.246.07:38:20.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.07:38:20.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.07:38:20.60#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:20.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:38:20.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:38:20.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:38:20.60#ibcon#enter wrdev, iclass 20, count 2 2006.246.07:38:20.60#ibcon#first serial, iclass 20, count 2 2006.246.07:38:20.60#ibcon#enter sib2, iclass 20, count 2 2006.246.07:38:20.60#ibcon#flushed, iclass 20, count 2 2006.246.07:38:20.60#ibcon#about to write, iclass 20, count 2 2006.246.07:38:20.60#ibcon#wrote, iclass 20, count 2 2006.246.07:38:20.60#ibcon#about to read 3, iclass 20, count 2 2006.246.07:38:20.61#ibcon#read 3, iclass 20, count 2 2006.246.07:38:20.61#ibcon#about to read 4, iclass 20, count 2 2006.246.07:38:20.61#ibcon#read 4, iclass 20, count 2 2006.246.07:38:20.61#ibcon#about to read 5, iclass 20, count 2 2006.246.07:38:20.61#ibcon#read 5, iclass 20, count 2 2006.246.07:38:20.61#ibcon#about to read 6, iclass 20, count 2 2006.246.07:38:20.61#ibcon#read 6, iclass 20, count 2 2006.246.07:38:20.61#ibcon#end of sib2, iclass 20, count 2 2006.246.07:38:20.61#ibcon#*mode == 0, iclass 20, count 2 2006.246.07:38:20.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.07:38:20.61#ibcon#[27=AT01-04\r\n] 2006.246.07:38:20.61#ibcon#*before write, iclass 20, count 2 2006.246.07:38:20.61#ibcon#enter sib2, iclass 20, count 2 2006.246.07:38:20.61#ibcon#flushed, iclass 20, count 2 2006.246.07:38:20.61#ibcon#about to write, iclass 20, count 2 2006.246.07:38:20.61#ibcon#wrote, iclass 20, count 2 2006.246.07:38:20.61#ibcon#about to read 3, iclass 20, count 2 2006.246.07:38:20.64#ibcon#read 3, iclass 20, count 2 2006.246.07:38:20.64#ibcon#about to read 4, iclass 20, count 2 2006.246.07:38:20.64#ibcon#read 4, iclass 20, count 2 2006.246.07:38:20.64#ibcon#about to read 5, iclass 20, count 2 2006.246.07:38:20.64#ibcon#read 5, iclass 20, count 2 2006.246.07:38:20.64#ibcon#about to read 6, iclass 20, count 2 2006.246.07:38:20.64#ibcon#read 6, iclass 20, count 2 2006.246.07:38:20.64#ibcon#end of sib2, iclass 20, count 2 2006.246.07:38:20.64#ibcon#*after write, iclass 20, count 2 2006.246.07:38:20.64#ibcon#*before return 0, iclass 20, count 2 2006.246.07:38:20.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:38:20.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:38:20.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.07:38:20.64#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:20.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:38:20.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:38:20.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:38:20.76#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:38:20.76#ibcon#first serial, iclass 20, count 0 2006.246.07:38:20.76#ibcon#enter sib2, iclass 20, count 0 2006.246.07:38:20.76#ibcon#flushed, iclass 20, count 0 2006.246.07:38:20.76#ibcon#about to write, iclass 20, count 0 2006.246.07:38:20.76#ibcon#wrote, iclass 20, count 0 2006.246.07:38:20.76#ibcon#about to read 3, iclass 20, count 0 2006.246.07:38:20.78#ibcon#read 3, iclass 20, count 0 2006.246.07:38:20.78#ibcon#about to read 4, iclass 20, count 0 2006.246.07:38:20.78#ibcon#read 4, iclass 20, count 0 2006.246.07:38:20.78#ibcon#about to read 5, iclass 20, count 0 2006.246.07:38:20.78#ibcon#read 5, iclass 20, count 0 2006.246.07:38:20.78#ibcon#about to read 6, iclass 20, count 0 2006.246.07:38:20.78#ibcon#read 6, iclass 20, count 0 2006.246.07:38:20.78#ibcon#end of sib2, iclass 20, count 0 2006.246.07:38:20.78#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:38:20.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:38:20.78#ibcon#[27=USB\r\n] 2006.246.07:38:20.78#ibcon#*before write, iclass 20, count 0 2006.246.07:38:20.78#ibcon#enter sib2, iclass 20, count 0 2006.246.07:38:20.78#ibcon#flushed, iclass 20, count 0 2006.246.07:38:20.78#ibcon#about to write, iclass 20, count 0 2006.246.07:38:20.78#ibcon#wrote, iclass 20, count 0 2006.246.07:38:20.78#ibcon#about to read 3, iclass 20, count 0 2006.246.07:38:20.81#ibcon#read 3, iclass 20, count 0 2006.246.07:38:20.81#ibcon#about to read 4, iclass 20, count 0 2006.246.07:38:20.81#ibcon#read 4, iclass 20, count 0 2006.246.07:38:20.81#ibcon#about to read 5, iclass 20, count 0 2006.246.07:38:20.81#ibcon#read 5, iclass 20, count 0 2006.246.07:38:20.81#ibcon#about to read 6, iclass 20, count 0 2006.246.07:38:20.81#ibcon#read 6, iclass 20, count 0 2006.246.07:38:20.81#ibcon#end of sib2, iclass 20, count 0 2006.246.07:38:20.81#ibcon#*after write, iclass 20, count 0 2006.246.07:38:20.81#ibcon#*before return 0, iclass 20, count 0 2006.246.07:38:20.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:38:20.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:38:20.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:38:20.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:38:20.82$vc4f8/vblo=2,640.99 2006.246.07:38:20.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:38:20.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:38:20.82#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:20.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:20.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:20.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:20.82#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:38:20.82#ibcon#first serial, iclass 22, count 0 2006.246.07:38:20.82#ibcon#enter sib2, iclass 22, count 0 2006.246.07:38:20.82#ibcon#flushed, iclass 22, count 0 2006.246.07:38:20.82#ibcon#about to write, iclass 22, count 0 2006.246.07:38:20.82#ibcon#wrote, iclass 22, count 0 2006.246.07:38:20.82#ibcon#about to read 3, iclass 22, count 0 2006.246.07:38:20.83#ibcon#read 3, iclass 22, count 0 2006.246.07:38:20.83#ibcon#about to read 4, iclass 22, count 0 2006.246.07:38:20.83#ibcon#read 4, iclass 22, count 0 2006.246.07:38:20.83#ibcon#about to read 5, iclass 22, count 0 2006.246.07:38:20.83#ibcon#read 5, iclass 22, count 0 2006.246.07:38:20.83#ibcon#about to read 6, iclass 22, count 0 2006.246.07:38:20.83#ibcon#read 6, iclass 22, count 0 2006.246.07:38:20.83#ibcon#end of sib2, iclass 22, count 0 2006.246.07:38:20.83#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:38:20.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:38:20.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:38:20.83#ibcon#*before write, iclass 22, count 0 2006.246.07:38:20.83#ibcon#enter sib2, iclass 22, count 0 2006.246.07:38:20.83#ibcon#flushed, iclass 22, count 0 2006.246.07:38:20.83#ibcon#about to write, iclass 22, count 0 2006.246.07:38:20.83#ibcon#wrote, iclass 22, count 0 2006.246.07:38:20.83#ibcon#about to read 3, iclass 22, count 0 2006.246.07:38:20.87#ibcon#read 3, iclass 22, count 0 2006.246.07:38:20.87#ibcon#about to read 4, iclass 22, count 0 2006.246.07:38:20.87#ibcon#read 4, iclass 22, count 0 2006.246.07:38:20.87#ibcon#about to read 5, iclass 22, count 0 2006.246.07:38:20.87#ibcon#read 5, iclass 22, count 0 2006.246.07:38:20.87#ibcon#about to read 6, iclass 22, count 0 2006.246.07:38:20.87#ibcon#read 6, iclass 22, count 0 2006.246.07:38:20.87#ibcon#end of sib2, iclass 22, count 0 2006.246.07:38:20.87#ibcon#*after write, iclass 22, count 0 2006.246.07:38:20.87#ibcon#*before return 0, iclass 22, count 0 2006.246.07:38:20.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:20.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:38:20.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:38:20.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:38:20.88$vc4f8/vb=2,4 2006.246.07:38:20.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.07:38:20.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.07:38:20.88#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:20.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:20.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:20.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:20.92#ibcon#enter wrdev, iclass 24, count 2 2006.246.07:38:20.92#ibcon#first serial, iclass 24, count 2 2006.246.07:38:20.92#ibcon#enter sib2, iclass 24, count 2 2006.246.07:38:20.92#ibcon#flushed, iclass 24, count 2 2006.246.07:38:20.92#ibcon#about to write, iclass 24, count 2 2006.246.07:38:20.92#ibcon#wrote, iclass 24, count 2 2006.246.07:38:20.92#ibcon#about to read 3, iclass 24, count 2 2006.246.07:38:20.94#ibcon#read 3, iclass 24, count 2 2006.246.07:38:20.94#ibcon#about to read 4, iclass 24, count 2 2006.246.07:38:20.94#ibcon#read 4, iclass 24, count 2 2006.246.07:38:20.94#ibcon#about to read 5, iclass 24, count 2 2006.246.07:38:20.94#ibcon#read 5, iclass 24, count 2 2006.246.07:38:20.94#ibcon#about to read 6, iclass 24, count 2 2006.246.07:38:20.94#ibcon#read 6, iclass 24, count 2 2006.246.07:38:20.94#ibcon#end of sib2, iclass 24, count 2 2006.246.07:38:20.94#ibcon#*mode == 0, iclass 24, count 2 2006.246.07:38:20.94#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.07:38:20.94#ibcon#[27=AT02-04\r\n] 2006.246.07:38:20.94#ibcon#*before write, iclass 24, count 2 2006.246.07:38:20.94#ibcon#enter sib2, iclass 24, count 2 2006.246.07:38:20.94#ibcon#flushed, iclass 24, count 2 2006.246.07:38:20.94#ibcon#about to write, iclass 24, count 2 2006.246.07:38:20.94#ibcon#wrote, iclass 24, count 2 2006.246.07:38:20.94#ibcon#about to read 3, iclass 24, count 2 2006.246.07:38:20.97#ibcon#read 3, iclass 24, count 2 2006.246.07:38:20.97#ibcon#about to read 4, iclass 24, count 2 2006.246.07:38:20.97#ibcon#read 4, iclass 24, count 2 2006.246.07:38:20.97#ibcon#about to read 5, iclass 24, count 2 2006.246.07:38:20.97#ibcon#read 5, iclass 24, count 2 2006.246.07:38:20.97#ibcon#about to read 6, iclass 24, count 2 2006.246.07:38:20.97#ibcon#read 6, iclass 24, count 2 2006.246.07:38:20.97#ibcon#end of sib2, iclass 24, count 2 2006.246.07:38:20.97#ibcon#*after write, iclass 24, count 2 2006.246.07:38:20.97#ibcon#*before return 0, iclass 24, count 2 2006.246.07:38:20.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:20.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:38:20.97#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.07:38:20.97#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:20.97#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:21.09#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:21.09#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:21.09#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:38:21.09#ibcon#first serial, iclass 24, count 0 2006.246.07:38:21.09#ibcon#enter sib2, iclass 24, count 0 2006.246.07:38:21.09#ibcon#flushed, iclass 24, count 0 2006.246.07:38:21.09#ibcon#about to write, iclass 24, count 0 2006.246.07:38:21.09#ibcon#wrote, iclass 24, count 0 2006.246.07:38:21.09#ibcon#about to read 3, iclass 24, count 0 2006.246.07:38:21.11#ibcon#read 3, iclass 24, count 0 2006.246.07:38:21.11#ibcon#about to read 4, iclass 24, count 0 2006.246.07:38:21.11#ibcon#read 4, iclass 24, count 0 2006.246.07:38:21.11#ibcon#about to read 5, iclass 24, count 0 2006.246.07:38:21.11#ibcon#read 5, iclass 24, count 0 2006.246.07:38:21.11#ibcon#about to read 6, iclass 24, count 0 2006.246.07:38:21.11#ibcon#read 6, iclass 24, count 0 2006.246.07:38:21.11#ibcon#end of sib2, iclass 24, count 0 2006.246.07:38:21.11#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:38:21.11#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:38:21.11#ibcon#[27=USB\r\n] 2006.246.07:38:21.11#ibcon#*before write, iclass 24, count 0 2006.246.07:38:21.11#ibcon#enter sib2, iclass 24, count 0 2006.246.07:38:21.11#ibcon#flushed, iclass 24, count 0 2006.246.07:38:21.11#ibcon#about to write, iclass 24, count 0 2006.246.07:38:21.11#ibcon#wrote, iclass 24, count 0 2006.246.07:38:21.11#ibcon#about to read 3, iclass 24, count 0 2006.246.07:38:21.14#ibcon#read 3, iclass 24, count 0 2006.246.07:38:21.14#ibcon#about to read 4, iclass 24, count 0 2006.246.07:38:21.14#ibcon#read 4, iclass 24, count 0 2006.246.07:38:21.14#ibcon#about to read 5, iclass 24, count 0 2006.246.07:38:21.14#ibcon#read 5, iclass 24, count 0 2006.246.07:38:21.14#ibcon#about to read 6, iclass 24, count 0 2006.246.07:38:21.14#ibcon#read 6, iclass 24, count 0 2006.246.07:38:21.14#ibcon#end of sib2, iclass 24, count 0 2006.246.07:38:21.14#ibcon#*after write, iclass 24, count 0 2006.246.07:38:21.14#ibcon#*before return 0, iclass 24, count 0 2006.246.07:38:21.14#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:21.14#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:38:21.14#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:38:21.14#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:38:21.15$vc4f8/vblo=3,656.99 2006.246.07:38:21.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:38:21.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:38:21.15#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:21.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:21.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:21.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:21.15#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:38:21.15#ibcon#first serial, iclass 26, count 0 2006.246.07:38:21.15#ibcon#enter sib2, iclass 26, count 0 2006.246.07:38:21.15#ibcon#flushed, iclass 26, count 0 2006.246.07:38:21.15#ibcon#about to write, iclass 26, count 0 2006.246.07:38:21.15#ibcon#wrote, iclass 26, count 0 2006.246.07:38:21.15#ibcon#about to read 3, iclass 26, count 0 2006.246.07:38:21.16#ibcon#read 3, iclass 26, count 0 2006.246.07:38:21.16#ibcon#about to read 4, iclass 26, count 0 2006.246.07:38:21.16#ibcon#read 4, iclass 26, count 0 2006.246.07:38:21.16#ibcon#about to read 5, iclass 26, count 0 2006.246.07:38:21.16#ibcon#read 5, iclass 26, count 0 2006.246.07:38:21.16#ibcon#about to read 6, iclass 26, count 0 2006.246.07:38:21.16#ibcon#read 6, iclass 26, count 0 2006.246.07:38:21.16#ibcon#end of sib2, iclass 26, count 0 2006.246.07:38:21.16#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:38:21.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:38:21.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:38:21.17#ibcon#*before write, iclass 26, count 0 2006.246.07:38:21.17#ibcon#enter sib2, iclass 26, count 0 2006.246.07:38:21.17#ibcon#flushed, iclass 26, count 0 2006.246.07:38:21.17#ibcon#about to write, iclass 26, count 0 2006.246.07:38:21.17#ibcon#wrote, iclass 26, count 0 2006.246.07:38:21.17#ibcon#about to read 3, iclass 26, count 0 2006.246.07:38:21.20#ibcon#read 3, iclass 26, count 0 2006.246.07:38:21.20#ibcon#about to read 4, iclass 26, count 0 2006.246.07:38:21.20#ibcon#read 4, iclass 26, count 0 2006.246.07:38:21.20#ibcon#about to read 5, iclass 26, count 0 2006.246.07:38:21.20#ibcon#read 5, iclass 26, count 0 2006.246.07:38:21.20#ibcon#about to read 6, iclass 26, count 0 2006.246.07:38:21.20#ibcon#read 6, iclass 26, count 0 2006.246.07:38:21.20#ibcon#end of sib2, iclass 26, count 0 2006.246.07:38:21.20#ibcon#*after write, iclass 26, count 0 2006.246.07:38:21.20#ibcon#*before return 0, iclass 26, count 0 2006.246.07:38:21.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:21.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:38:21.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:38:21.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:38:21.21$vc4f8/vb=3,4 2006.246.07:38:21.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:38:21.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:38:21.21#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:21.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:21.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:21.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:21.25#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:38:21.25#ibcon#first serial, iclass 28, count 2 2006.246.07:38:21.25#ibcon#enter sib2, iclass 28, count 2 2006.246.07:38:21.25#ibcon#flushed, iclass 28, count 2 2006.246.07:38:21.25#ibcon#about to write, iclass 28, count 2 2006.246.07:38:21.25#ibcon#wrote, iclass 28, count 2 2006.246.07:38:21.25#ibcon#about to read 3, iclass 28, count 2 2006.246.07:38:21.27#ibcon#read 3, iclass 28, count 2 2006.246.07:38:21.27#ibcon#about to read 4, iclass 28, count 2 2006.246.07:38:21.27#ibcon#read 4, iclass 28, count 2 2006.246.07:38:21.27#ibcon#about to read 5, iclass 28, count 2 2006.246.07:38:21.27#ibcon#read 5, iclass 28, count 2 2006.246.07:38:21.27#ibcon#about to read 6, iclass 28, count 2 2006.246.07:38:21.27#ibcon#read 6, iclass 28, count 2 2006.246.07:38:21.27#ibcon#end of sib2, iclass 28, count 2 2006.246.07:38:21.27#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:38:21.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:38:21.27#ibcon#[27=AT03-04\r\n] 2006.246.07:38:21.27#ibcon#*before write, iclass 28, count 2 2006.246.07:38:21.27#ibcon#enter sib2, iclass 28, count 2 2006.246.07:38:21.27#ibcon#flushed, iclass 28, count 2 2006.246.07:38:21.27#ibcon#about to write, iclass 28, count 2 2006.246.07:38:21.27#ibcon#wrote, iclass 28, count 2 2006.246.07:38:21.27#ibcon#about to read 3, iclass 28, count 2 2006.246.07:38:21.30#ibcon#read 3, iclass 28, count 2 2006.246.07:38:21.30#ibcon#about to read 4, iclass 28, count 2 2006.246.07:38:21.30#ibcon#read 4, iclass 28, count 2 2006.246.07:38:21.30#ibcon#about to read 5, iclass 28, count 2 2006.246.07:38:21.30#ibcon#read 5, iclass 28, count 2 2006.246.07:38:21.30#ibcon#about to read 6, iclass 28, count 2 2006.246.07:38:21.30#ibcon#read 6, iclass 28, count 2 2006.246.07:38:21.30#ibcon#end of sib2, iclass 28, count 2 2006.246.07:38:21.30#ibcon#*after write, iclass 28, count 2 2006.246.07:38:21.30#ibcon#*before return 0, iclass 28, count 2 2006.246.07:38:21.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:21.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:38:21.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:38:21.30#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:21.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:21.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:21.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:21.42#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:38:21.42#ibcon#first serial, iclass 28, count 0 2006.246.07:38:21.42#ibcon#enter sib2, iclass 28, count 0 2006.246.07:38:21.42#ibcon#flushed, iclass 28, count 0 2006.246.07:38:21.42#ibcon#about to write, iclass 28, count 0 2006.246.07:38:21.42#ibcon#wrote, iclass 28, count 0 2006.246.07:38:21.42#ibcon#about to read 3, iclass 28, count 0 2006.246.07:38:21.44#ibcon#read 3, iclass 28, count 0 2006.246.07:38:21.44#ibcon#about to read 4, iclass 28, count 0 2006.246.07:38:21.44#ibcon#read 4, iclass 28, count 0 2006.246.07:38:21.44#ibcon#about to read 5, iclass 28, count 0 2006.246.07:38:21.44#ibcon#read 5, iclass 28, count 0 2006.246.07:38:21.44#ibcon#about to read 6, iclass 28, count 0 2006.246.07:38:21.44#ibcon#read 6, iclass 28, count 0 2006.246.07:38:21.44#ibcon#end of sib2, iclass 28, count 0 2006.246.07:38:21.44#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:38:21.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:38:21.44#ibcon#[27=USB\r\n] 2006.246.07:38:21.44#ibcon#*before write, iclass 28, count 0 2006.246.07:38:21.44#ibcon#enter sib2, iclass 28, count 0 2006.246.07:38:21.44#ibcon#flushed, iclass 28, count 0 2006.246.07:38:21.44#ibcon#about to write, iclass 28, count 0 2006.246.07:38:21.44#ibcon#wrote, iclass 28, count 0 2006.246.07:38:21.44#ibcon#about to read 3, iclass 28, count 0 2006.246.07:38:21.47#ibcon#read 3, iclass 28, count 0 2006.246.07:38:21.47#ibcon#about to read 4, iclass 28, count 0 2006.246.07:38:21.47#ibcon#read 4, iclass 28, count 0 2006.246.07:38:21.47#ibcon#about to read 5, iclass 28, count 0 2006.246.07:38:21.47#ibcon#read 5, iclass 28, count 0 2006.246.07:38:21.47#ibcon#about to read 6, iclass 28, count 0 2006.246.07:38:21.47#ibcon#read 6, iclass 28, count 0 2006.246.07:38:21.47#ibcon#end of sib2, iclass 28, count 0 2006.246.07:38:21.47#ibcon#*after write, iclass 28, count 0 2006.246.07:38:21.47#ibcon#*before return 0, iclass 28, count 0 2006.246.07:38:21.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:21.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:38:21.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:38:21.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:38:21.48$vc4f8/vblo=4,712.99 2006.246.07:38:21.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:38:21.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:38:21.48#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:21.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:21.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:21.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:21.48#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:38:21.48#ibcon#first serial, iclass 30, count 0 2006.246.07:38:21.48#ibcon#enter sib2, iclass 30, count 0 2006.246.07:38:21.48#ibcon#flushed, iclass 30, count 0 2006.246.07:38:21.48#ibcon#about to write, iclass 30, count 0 2006.246.07:38:21.48#ibcon#wrote, iclass 30, count 0 2006.246.07:38:21.48#ibcon#about to read 3, iclass 30, count 0 2006.246.07:38:21.49#ibcon#read 3, iclass 30, count 0 2006.246.07:38:21.49#ibcon#about to read 4, iclass 30, count 0 2006.246.07:38:21.49#ibcon#read 4, iclass 30, count 0 2006.246.07:38:21.49#ibcon#about to read 5, iclass 30, count 0 2006.246.07:38:21.49#ibcon#read 5, iclass 30, count 0 2006.246.07:38:21.49#ibcon#about to read 6, iclass 30, count 0 2006.246.07:38:21.49#ibcon#read 6, iclass 30, count 0 2006.246.07:38:21.49#ibcon#end of sib2, iclass 30, count 0 2006.246.07:38:21.49#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:38:21.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:38:21.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:38:21.49#ibcon#*before write, iclass 30, count 0 2006.246.07:38:21.49#ibcon#enter sib2, iclass 30, count 0 2006.246.07:38:21.49#ibcon#flushed, iclass 30, count 0 2006.246.07:38:21.49#ibcon#about to write, iclass 30, count 0 2006.246.07:38:21.49#ibcon#wrote, iclass 30, count 0 2006.246.07:38:21.49#ibcon#about to read 3, iclass 30, count 0 2006.246.07:38:21.53#ibcon#read 3, iclass 30, count 0 2006.246.07:38:21.53#ibcon#about to read 4, iclass 30, count 0 2006.246.07:38:21.53#ibcon#read 4, iclass 30, count 0 2006.246.07:38:21.53#ibcon#about to read 5, iclass 30, count 0 2006.246.07:38:21.53#ibcon#read 5, iclass 30, count 0 2006.246.07:38:21.53#ibcon#about to read 6, iclass 30, count 0 2006.246.07:38:21.53#ibcon#read 6, iclass 30, count 0 2006.246.07:38:21.53#ibcon#end of sib2, iclass 30, count 0 2006.246.07:38:21.53#ibcon#*after write, iclass 30, count 0 2006.246.07:38:21.53#ibcon#*before return 0, iclass 30, count 0 2006.246.07:38:21.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:21.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:38:21.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:38:21.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:38:21.54$vc4f8/vb=4,4 2006.246.07:38:21.54#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:38:21.54#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:38:21.54#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:21.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:21.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:21.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:21.58#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:38:21.58#ibcon#first serial, iclass 32, count 2 2006.246.07:38:21.58#ibcon#enter sib2, iclass 32, count 2 2006.246.07:38:21.58#ibcon#flushed, iclass 32, count 2 2006.246.07:38:21.58#ibcon#about to write, iclass 32, count 2 2006.246.07:38:21.58#ibcon#wrote, iclass 32, count 2 2006.246.07:38:21.58#ibcon#about to read 3, iclass 32, count 2 2006.246.07:38:21.60#ibcon#read 3, iclass 32, count 2 2006.246.07:38:21.60#ibcon#about to read 4, iclass 32, count 2 2006.246.07:38:21.60#ibcon#read 4, iclass 32, count 2 2006.246.07:38:21.60#ibcon#about to read 5, iclass 32, count 2 2006.246.07:38:21.60#ibcon#read 5, iclass 32, count 2 2006.246.07:38:21.60#ibcon#about to read 6, iclass 32, count 2 2006.246.07:38:21.60#ibcon#read 6, iclass 32, count 2 2006.246.07:38:21.60#ibcon#end of sib2, iclass 32, count 2 2006.246.07:38:21.60#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:38:21.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:38:21.60#ibcon#[27=AT04-04\r\n] 2006.246.07:38:21.60#ibcon#*before write, iclass 32, count 2 2006.246.07:38:21.60#ibcon#enter sib2, iclass 32, count 2 2006.246.07:38:21.60#ibcon#flushed, iclass 32, count 2 2006.246.07:38:21.60#ibcon#about to write, iclass 32, count 2 2006.246.07:38:21.60#ibcon#wrote, iclass 32, count 2 2006.246.07:38:21.60#ibcon#about to read 3, iclass 32, count 2 2006.246.07:38:21.63#ibcon#read 3, iclass 32, count 2 2006.246.07:38:21.63#ibcon#about to read 4, iclass 32, count 2 2006.246.07:38:21.63#ibcon#read 4, iclass 32, count 2 2006.246.07:38:21.63#ibcon#about to read 5, iclass 32, count 2 2006.246.07:38:21.63#ibcon#read 5, iclass 32, count 2 2006.246.07:38:21.63#ibcon#about to read 6, iclass 32, count 2 2006.246.07:38:21.63#ibcon#read 6, iclass 32, count 2 2006.246.07:38:21.63#ibcon#end of sib2, iclass 32, count 2 2006.246.07:38:21.63#ibcon#*after write, iclass 32, count 2 2006.246.07:38:21.63#ibcon#*before return 0, iclass 32, count 2 2006.246.07:38:21.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:21.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:38:21.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:38:21.63#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:21.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:21.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:21.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:21.75#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:38:21.75#ibcon#first serial, iclass 32, count 0 2006.246.07:38:21.75#ibcon#enter sib2, iclass 32, count 0 2006.246.07:38:21.75#ibcon#flushed, iclass 32, count 0 2006.246.07:38:21.75#ibcon#about to write, iclass 32, count 0 2006.246.07:38:21.75#ibcon#wrote, iclass 32, count 0 2006.246.07:38:21.75#ibcon#about to read 3, iclass 32, count 0 2006.246.07:38:21.77#ibcon#read 3, iclass 32, count 0 2006.246.07:38:21.77#ibcon#about to read 4, iclass 32, count 0 2006.246.07:38:21.77#ibcon#read 4, iclass 32, count 0 2006.246.07:38:21.77#ibcon#about to read 5, iclass 32, count 0 2006.246.07:38:21.77#ibcon#read 5, iclass 32, count 0 2006.246.07:38:21.77#ibcon#about to read 6, iclass 32, count 0 2006.246.07:38:21.77#ibcon#read 6, iclass 32, count 0 2006.246.07:38:21.77#ibcon#end of sib2, iclass 32, count 0 2006.246.07:38:21.77#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:38:21.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:38:21.77#ibcon#[27=USB\r\n] 2006.246.07:38:21.77#ibcon#*before write, iclass 32, count 0 2006.246.07:38:21.77#ibcon#enter sib2, iclass 32, count 0 2006.246.07:38:21.77#ibcon#flushed, iclass 32, count 0 2006.246.07:38:21.77#ibcon#about to write, iclass 32, count 0 2006.246.07:38:21.77#ibcon#wrote, iclass 32, count 0 2006.246.07:38:21.77#ibcon#about to read 3, iclass 32, count 0 2006.246.07:38:21.80#ibcon#read 3, iclass 32, count 0 2006.246.07:38:21.80#ibcon#about to read 4, iclass 32, count 0 2006.246.07:38:21.80#ibcon#read 4, iclass 32, count 0 2006.246.07:38:21.80#ibcon#about to read 5, iclass 32, count 0 2006.246.07:38:21.80#ibcon#read 5, iclass 32, count 0 2006.246.07:38:21.80#ibcon#about to read 6, iclass 32, count 0 2006.246.07:38:21.80#ibcon#read 6, iclass 32, count 0 2006.246.07:38:21.80#ibcon#end of sib2, iclass 32, count 0 2006.246.07:38:21.80#ibcon#*after write, iclass 32, count 0 2006.246.07:38:21.80#ibcon#*before return 0, iclass 32, count 0 2006.246.07:38:21.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:21.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:38:21.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:38:21.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:38:21.81$vc4f8/vblo=5,744.99 2006.246.07:38:21.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:38:21.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:38:21.81#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:21.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:21.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:21.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:21.81#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:38:21.81#ibcon#first serial, iclass 34, count 0 2006.246.07:38:21.81#ibcon#enter sib2, iclass 34, count 0 2006.246.07:38:21.81#ibcon#flushed, iclass 34, count 0 2006.246.07:38:21.81#ibcon#about to write, iclass 34, count 0 2006.246.07:38:21.81#ibcon#wrote, iclass 34, count 0 2006.246.07:38:21.81#ibcon#about to read 3, iclass 34, count 0 2006.246.07:38:21.83#ibcon#read 3, iclass 34, count 0 2006.246.07:38:21.83#ibcon#about to read 4, iclass 34, count 0 2006.246.07:38:21.83#ibcon#read 4, iclass 34, count 0 2006.246.07:38:21.83#ibcon#about to read 5, iclass 34, count 0 2006.246.07:38:21.83#ibcon#read 5, iclass 34, count 0 2006.246.07:38:21.83#ibcon#about to read 6, iclass 34, count 0 2006.246.07:38:21.83#ibcon#read 6, iclass 34, count 0 2006.246.07:38:21.83#ibcon#end of sib2, iclass 34, count 0 2006.246.07:38:21.83#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:38:21.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:38:21.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:38:21.83#ibcon#*before write, iclass 34, count 0 2006.246.07:38:21.83#ibcon#enter sib2, iclass 34, count 0 2006.246.07:38:21.83#ibcon#flushed, iclass 34, count 0 2006.246.07:38:21.83#ibcon#about to write, iclass 34, count 0 2006.246.07:38:21.83#ibcon#wrote, iclass 34, count 0 2006.246.07:38:21.83#ibcon#about to read 3, iclass 34, count 0 2006.246.07:38:21.87#ibcon#read 3, iclass 34, count 0 2006.246.07:38:21.87#ibcon#about to read 4, iclass 34, count 0 2006.246.07:38:21.87#ibcon#read 4, iclass 34, count 0 2006.246.07:38:21.87#ibcon#about to read 5, iclass 34, count 0 2006.246.07:38:21.87#ibcon#read 5, iclass 34, count 0 2006.246.07:38:21.87#ibcon#about to read 6, iclass 34, count 0 2006.246.07:38:21.87#ibcon#read 6, iclass 34, count 0 2006.246.07:38:21.87#ibcon#end of sib2, iclass 34, count 0 2006.246.07:38:21.87#ibcon#*after write, iclass 34, count 0 2006.246.07:38:21.87#ibcon#*before return 0, iclass 34, count 0 2006.246.07:38:21.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:21.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:38:21.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:38:21.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:38:21.88$vc4f8/vb=5,3 2006.246.07:38:21.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:38:21.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:38:21.88#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:21.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:21.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:21.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:21.91#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:38:21.91#ibcon#first serial, iclass 36, count 2 2006.246.07:38:21.91#ibcon#enter sib2, iclass 36, count 2 2006.246.07:38:21.91#ibcon#flushed, iclass 36, count 2 2006.246.07:38:21.91#ibcon#about to write, iclass 36, count 2 2006.246.07:38:21.91#ibcon#wrote, iclass 36, count 2 2006.246.07:38:21.91#ibcon#about to read 3, iclass 36, count 2 2006.246.07:38:21.94#ibcon#read 3, iclass 36, count 2 2006.246.07:38:21.94#ibcon#about to read 4, iclass 36, count 2 2006.246.07:38:21.94#ibcon#read 4, iclass 36, count 2 2006.246.07:38:21.94#ibcon#about to read 5, iclass 36, count 2 2006.246.07:38:21.94#ibcon#read 5, iclass 36, count 2 2006.246.07:38:21.94#ibcon#about to read 6, iclass 36, count 2 2006.246.07:38:21.94#ibcon#read 6, iclass 36, count 2 2006.246.07:38:21.94#ibcon#end of sib2, iclass 36, count 2 2006.246.07:38:21.94#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:38:21.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:38:21.94#ibcon#[27=AT05-03\r\n] 2006.246.07:38:21.94#ibcon#*before write, iclass 36, count 2 2006.246.07:38:21.94#ibcon#enter sib2, iclass 36, count 2 2006.246.07:38:21.94#ibcon#flushed, iclass 36, count 2 2006.246.07:38:21.94#ibcon#about to write, iclass 36, count 2 2006.246.07:38:21.94#ibcon#wrote, iclass 36, count 2 2006.246.07:38:21.94#ibcon#about to read 3, iclass 36, count 2 2006.246.07:38:21.97#ibcon#read 3, iclass 36, count 2 2006.246.07:38:21.97#ibcon#about to read 4, iclass 36, count 2 2006.246.07:38:21.97#ibcon#read 4, iclass 36, count 2 2006.246.07:38:21.97#ibcon#about to read 5, iclass 36, count 2 2006.246.07:38:21.97#ibcon#read 5, iclass 36, count 2 2006.246.07:38:21.97#ibcon#about to read 6, iclass 36, count 2 2006.246.07:38:21.97#ibcon#read 6, iclass 36, count 2 2006.246.07:38:21.97#ibcon#end of sib2, iclass 36, count 2 2006.246.07:38:21.97#ibcon#*after write, iclass 36, count 2 2006.246.07:38:21.97#ibcon#*before return 0, iclass 36, count 2 2006.246.07:38:21.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:21.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:38:21.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:38:21.97#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:21.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:22.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:22.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:22.09#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:38:22.09#ibcon#first serial, iclass 36, count 0 2006.246.07:38:22.09#ibcon#enter sib2, iclass 36, count 0 2006.246.07:38:22.09#ibcon#flushed, iclass 36, count 0 2006.246.07:38:22.09#ibcon#about to write, iclass 36, count 0 2006.246.07:38:22.09#ibcon#wrote, iclass 36, count 0 2006.246.07:38:22.09#ibcon#about to read 3, iclass 36, count 0 2006.246.07:38:22.11#ibcon#read 3, iclass 36, count 0 2006.246.07:38:22.11#ibcon#about to read 4, iclass 36, count 0 2006.246.07:38:22.11#ibcon#read 4, iclass 36, count 0 2006.246.07:38:22.11#ibcon#about to read 5, iclass 36, count 0 2006.246.07:38:22.11#ibcon#read 5, iclass 36, count 0 2006.246.07:38:22.11#ibcon#about to read 6, iclass 36, count 0 2006.246.07:38:22.11#ibcon#read 6, iclass 36, count 0 2006.246.07:38:22.11#ibcon#end of sib2, iclass 36, count 0 2006.246.07:38:22.11#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:38:22.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:38:22.11#ibcon#[27=USB\r\n] 2006.246.07:38:22.11#ibcon#*before write, iclass 36, count 0 2006.246.07:38:22.11#ibcon#enter sib2, iclass 36, count 0 2006.246.07:38:22.11#ibcon#flushed, iclass 36, count 0 2006.246.07:38:22.11#ibcon#about to write, iclass 36, count 0 2006.246.07:38:22.11#ibcon#wrote, iclass 36, count 0 2006.246.07:38:22.11#ibcon#about to read 3, iclass 36, count 0 2006.246.07:38:22.14#ibcon#read 3, iclass 36, count 0 2006.246.07:38:22.14#ibcon#about to read 4, iclass 36, count 0 2006.246.07:38:22.14#ibcon#read 4, iclass 36, count 0 2006.246.07:38:22.14#ibcon#about to read 5, iclass 36, count 0 2006.246.07:38:22.14#ibcon#read 5, iclass 36, count 0 2006.246.07:38:22.14#ibcon#about to read 6, iclass 36, count 0 2006.246.07:38:22.14#ibcon#read 6, iclass 36, count 0 2006.246.07:38:22.14#ibcon#end of sib2, iclass 36, count 0 2006.246.07:38:22.14#ibcon#*after write, iclass 36, count 0 2006.246.07:38:22.14#ibcon#*before return 0, iclass 36, count 0 2006.246.07:38:22.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:22.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:38:22.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:38:22.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:38:22.15$vc4f8/vblo=6,752.99 2006.246.07:38:22.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:38:22.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:38:22.15#ibcon#ireg 17 cls_cnt 0 2006.246.07:38:22.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:22.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:22.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:22.15#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:38:22.15#ibcon#first serial, iclass 38, count 0 2006.246.07:38:22.15#ibcon#enter sib2, iclass 38, count 0 2006.246.07:38:22.15#ibcon#flushed, iclass 38, count 0 2006.246.07:38:22.15#ibcon#about to write, iclass 38, count 0 2006.246.07:38:22.15#ibcon#wrote, iclass 38, count 0 2006.246.07:38:22.15#ibcon#about to read 3, iclass 38, count 0 2006.246.07:38:22.16#ibcon#read 3, iclass 38, count 0 2006.246.07:38:22.16#ibcon#about to read 4, iclass 38, count 0 2006.246.07:38:22.16#ibcon#read 4, iclass 38, count 0 2006.246.07:38:22.16#ibcon#about to read 5, iclass 38, count 0 2006.246.07:38:22.16#ibcon#read 5, iclass 38, count 0 2006.246.07:38:22.16#ibcon#about to read 6, iclass 38, count 0 2006.246.07:38:22.16#ibcon#read 6, iclass 38, count 0 2006.246.07:38:22.16#ibcon#end of sib2, iclass 38, count 0 2006.246.07:38:22.16#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:38:22.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:38:22.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:38:22.16#ibcon#*before write, iclass 38, count 0 2006.246.07:38:22.16#ibcon#enter sib2, iclass 38, count 0 2006.246.07:38:22.16#ibcon#flushed, iclass 38, count 0 2006.246.07:38:22.16#ibcon#about to write, iclass 38, count 0 2006.246.07:38:22.16#ibcon#wrote, iclass 38, count 0 2006.246.07:38:22.16#ibcon#about to read 3, iclass 38, count 0 2006.246.07:38:22.20#ibcon#read 3, iclass 38, count 0 2006.246.07:38:22.20#ibcon#about to read 4, iclass 38, count 0 2006.246.07:38:22.20#ibcon#read 4, iclass 38, count 0 2006.246.07:38:22.20#ibcon#about to read 5, iclass 38, count 0 2006.246.07:38:22.20#ibcon#read 5, iclass 38, count 0 2006.246.07:38:22.20#ibcon#about to read 6, iclass 38, count 0 2006.246.07:38:22.20#ibcon#read 6, iclass 38, count 0 2006.246.07:38:22.20#ibcon#end of sib2, iclass 38, count 0 2006.246.07:38:22.20#ibcon#*after write, iclass 38, count 0 2006.246.07:38:22.20#ibcon#*before return 0, iclass 38, count 0 2006.246.07:38:22.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:22.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:38:22.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:38:22.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:38:22.21$vc4f8/vb=6,3 2006.246.07:38:22.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.07:38:22.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.07:38:22.21#ibcon#ireg 11 cls_cnt 2 2006.246.07:38:22.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:22.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:22.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:22.25#ibcon#enter wrdev, iclass 40, count 2 2006.246.07:38:22.25#ibcon#first serial, iclass 40, count 2 2006.246.07:38:22.25#ibcon#enter sib2, iclass 40, count 2 2006.246.07:38:22.25#ibcon#flushed, iclass 40, count 2 2006.246.07:38:22.25#ibcon#about to write, iclass 40, count 2 2006.246.07:38:22.25#ibcon#wrote, iclass 40, count 2 2006.246.07:38:22.25#ibcon#about to read 3, iclass 40, count 2 2006.246.07:38:22.27#ibcon#read 3, iclass 40, count 2 2006.246.07:38:22.27#ibcon#about to read 4, iclass 40, count 2 2006.246.07:38:22.27#ibcon#read 4, iclass 40, count 2 2006.246.07:38:22.27#ibcon#about to read 5, iclass 40, count 2 2006.246.07:38:22.27#ibcon#read 5, iclass 40, count 2 2006.246.07:38:22.27#ibcon#about to read 6, iclass 40, count 2 2006.246.07:38:22.27#ibcon#read 6, iclass 40, count 2 2006.246.07:38:22.27#ibcon#end of sib2, iclass 40, count 2 2006.246.07:38:22.27#ibcon#*mode == 0, iclass 40, count 2 2006.246.07:38:22.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.07:38:22.27#ibcon#[27=AT06-03\r\n] 2006.246.07:38:22.27#ibcon#*before write, iclass 40, count 2 2006.246.07:38:22.27#ibcon#enter sib2, iclass 40, count 2 2006.246.07:38:22.27#ibcon#flushed, iclass 40, count 2 2006.246.07:38:22.27#ibcon#about to write, iclass 40, count 2 2006.246.07:38:22.27#ibcon#wrote, iclass 40, count 2 2006.246.07:38:22.27#ibcon#about to read 3, iclass 40, count 2 2006.246.07:38:22.30#ibcon#read 3, iclass 40, count 2 2006.246.07:38:22.30#ibcon#about to read 4, iclass 40, count 2 2006.246.07:38:22.30#ibcon#read 4, iclass 40, count 2 2006.246.07:38:22.30#ibcon#about to read 5, iclass 40, count 2 2006.246.07:38:22.30#ibcon#read 5, iclass 40, count 2 2006.246.07:38:22.30#ibcon#about to read 6, iclass 40, count 2 2006.246.07:38:22.30#ibcon#read 6, iclass 40, count 2 2006.246.07:38:22.30#ibcon#end of sib2, iclass 40, count 2 2006.246.07:38:22.30#ibcon#*after write, iclass 40, count 2 2006.246.07:38:22.30#ibcon#*before return 0, iclass 40, count 2 2006.246.07:38:22.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:22.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:38:22.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.07:38:22.30#ibcon#ireg 7 cls_cnt 0 2006.246.07:38:22.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:22.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:22.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:22.42#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:38:22.42#ibcon#first serial, iclass 40, count 0 2006.246.07:38:22.42#ibcon#enter sib2, iclass 40, count 0 2006.246.07:38:22.42#ibcon#flushed, iclass 40, count 0 2006.246.07:38:22.42#ibcon#about to write, iclass 40, count 0 2006.246.07:38:22.42#ibcon#wrote, iclass 40, count 0 2006.246.07:38:22.42#ibcon#about to read 3, iclass 40, count 0 2006.246.07:38:22.44#ibcon#read 3, iclass 40, count 0 2006.246.07:38:22.44#ibcon#about to read 4, iclass 40, count 0 2006.246.07:38:22.44#ibcon#read 4, iclass 40, count 0 2006.246.07:38:22.44#ibcon#about to read 5, iclass 40, count 0 2006.246.07:38:22.44#ibcon#read 5, iclass 40, count 0 2006.246.07:38:22.44#ibcon#about to read 6, iclass 40, count 0 2006.246.07:38:22.44#ibcon#read 6, iclass 40, count 0 2006.246.07:38:22.44#ibcon#end of sib2, iclass 40, count 0 2006.246.07:38:22.44#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:38:22.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:38:22.44#ibcon#[27=USB\r\n] 2006.246.07:38:22.44#ibcon#*before write, iclass 40, count 0 2006.246.07:38:22.44#ibcon#enter sib2, iclass 40, count 0 2006.246.07:38:22.44#ibcon#flushed, iclass 40, count 0 2006.246.07:38:22.44#ibcon#about to write, iclass 40, count 0 2006.246.07:38:22.44#ibcon#wrote, iclass 40, count 0 2006.246.07:38:22.44#ibcon#about to read 3, iclass 40, count 0 2006.246.07:38:22.47#ibcon#read 3, iclass 40, count 0 2006.246.07:38:22.47#ibcon#about to read 4, iclass 40, count 0 2006.246.07:38:22.47#ibcon#read 4, iclass 40, count 0 2006.246.07:38:22.47#ibcon#about to read 5, iclass 40, count 0 2006.246.07:38:22.47#ibcon#read 5, iclass 40, count 0 2006.246.07:38:22.47#ibcon#about to read 6, iclass 40, count 0 2006.246.07:38:22.47#ibcon#read 6, iclass 40, count 0 2006.246.07:38:22.47#ibcon#end of sib2, iclass 40, count 0 2006.246.07:38:22.47#ibcon#*after write, iclass 40, count 0 2006.246.07:38:22.47#ibcon#*before return 0, iclass 40, count 0 2006.246.07:38:22.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:22.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:38:22.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:38:22.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:38:22.48$vc4f8/vabw=wide 2006.246.07:38:22.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.07:38:22.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.07:38:22.48#ibcon#ireg 8 cls_cnt 0 2006.246.07:38:22.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:22.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:22.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:22.48#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:38:22.48#ibcon#first serial, iclass 4, count 0 2006.246.07:38:22.48#ibcon#enter sib2, iclass 4, count 0 2006.246.07:38:22.48#ibcon#flushed, iclass 4, count 0 2006.246.07:38:22.48#ibcon#about to write, iclass 4, count 0 2006.246.07:38:22.48#ibcon#wrote, iclass 4, count 0 2006.246.07:38:22.48#ibcon#about to read 3, iclass 4, count 0 2006.246.07:38:22.49#ibcon#read 3, iclass 4, count 0 2006.246.07:38:22.49#ibcon#about to read 4, iclass 4, count 0 2006.246.07:38:22.49#ibcon#read 4, iclass 4, count 0 2006.246.07:38:22.49#ibcon#about to read 5, iclass 4, count 0 2006.246.07:38:22.49#ibcon#read 5, iclass 4, count 0 2006.246.07:38:22.49#ibcon#about to read 6, iclass 4, count 0 2006.246.07:38:22.49#ibcon#read 6, iclass 4, count 0 2006.246.07:38:22.49#ibcon#end of sib2, iclass 4, count 0 2006.246.07:38:22.49#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:38:22.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:38:22.49#ibcon#[25=BW32\r\n] 2006.246.07:38:22.49#ibcon#*before write, iclass 4, count 0 2006.246.07:38:22.49#ibcon#enter sib2, iclass 4, count 0 2006.246.07:38:22.49#ibcon#flushed, iclass 4, count 0 2006.246.07:38:22.49#ibcon#about to write, iclass 4, count 0 2006.246.07:38:22.49#ibcon#wrote, iclass 4, count 0 2006.246.07:38:22.49#ibcon#about to read 3, iclass 4, count 0 2006.246.07:38:22.52#ibcon#read 3, iclass 4, count 0 2006.246.07:38:22.52#ibcon#about to read 4, iclass 4, count 0 2006.246.07:38:22.52#ibcon#read 4, iclass 4, count 0 2006.246.07:38:22.52#ibcon#about to read 5, iclass 4, count 0 2006.246.07:38:22.52#ibcon#read 5, iclass 4, count 0 2006.246.07:38:22.52#ibcon#about to read 6, iclass 4, count 0 2006.246.07:38:22.52#ibcon#read 6, iclass 4, count 0 2006.246.07:38:22.52#ibcon#end of sib2, iclass 4, count 0 2006.246.07:38:22.52#ibcon#*after write, iclass 4, count 0 2006.246.07:38:22.52#ibcon#*before return 0, iclass 4, count 0 2006.246.07:38:22.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:22.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:38:22.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:38:22.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:38:22.53$vc4f8/vbbw=wide 2006.246.07:38:22.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.07:38:22.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.07:38:22.53#ibcon#ireg 8 cls_cnt 0 2006.246.07:38:22.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:38:22.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:38:22.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:38:22.58#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:38:22.58#ibcon#first serial, iclass 6, count 0 2006.246.07:38:22.58#ibcon#enter sib2, iclass 6, count 0 2006.246.07:38:22.58#ibcon#flushed, iclass 6, count 0 2006.246.07:38:22.58#ibcon#about to write, iclass 6, count 0 2006.246.07:38:22.58#ibcon#wrote, iclass 6, count 0 2006.246.07:38:22.58#ibcon#about to read 3, iclass 6, count 0 2006.246.07:38:22.60#ibcon#read 3, iclass 6, count 0 2006.246.07:38:22.60#ibcon#about to read 4, iclass 6, count 0 2006.246.07:38:22.60#ibcon#read 4, iclass 6, count 0 2006.246.07:38:22.60#ibcon#about to read 5, iclass 6, count 0 2006.246.07:38:22.60#ibcon#read 5, iclass 6, count 0 2006.246.07:38:22.60#ibcon#about to read 6, iclass 6, count 0 2006.246.07:38:22.60#ibcon#read 6, iclass 6, count 0 2006.246.07:38:22.60#ibcon#end of sib2, iclass 6, count 0 2006.246.07:38:22.60#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:38:22.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:38:22.60#ibcon#[27=BW32\r\n] 2006.246.07:38:22.60#ibcon#*before write, iclass 6, count 0 2006.246.07:38:22.60#ibcon#enter sib2, iclass 6, count 0 2006.246.07:38:22.60#ibcon#flushed, iclass 6, count 0 2006.246.07:38:22.60#ibcon#about to write, iclass 6, count 0 2006.246.07:38:22.60#ibcon#wrote, iclass 6, count 0 2006.246.07:38:22.60#ibcon#about to read 3, iclass 6, count 0 2006.246.07:38:22.63#ibcon#read 3, iclass 6, count 0 2006.246.07:38:22.63#ibcon#about to read 4, iclass 6, count 0 2006.246.07:38:22.63#ibcon#read 4, iclass 6, count 0 2006.246.07:38:22.63#ibcon#about to read 5, iclass 6, count 0 2006.246.07:38:22.63#ibcon#read 5, iclass 6, count 0 2006.246.07:38:22.63#ibcon#about to read 6, iclass 6, count 0 2006.246.07:38:22.63#ibcon#read 6, iclass 6, count 0 2006.246.07:38:22.63#ibcon#end of sib2, iclass 6, count 0 2006.246.07:38:22.63#ibcon#*after write, iclass 6, count 0 2006.246.07:38:22.63#ibcon#*before return 0, iclass 6, count 0 2006.246.07:38:22.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:38:22.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:38:22.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:38:22.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:38:22.64$4f8m12a/ifd4f 2006.246.07:38:22.64$ifd4f/lo= 2006.246.07:38:22.64$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:38:22.64$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:38:22.64$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:38:22.64$ifd4f/patch= 2006.246.07:38:22.64$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:38:22.64$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:38:22.64$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:38:22.64$4f8m12a/"form=m,16.000,1:2 2006.246.07:38:22.64$4f8m12a/"tpicd 2006.246.07:38:22.64$4f8m12a/echo=off 2006.246.07:38:22.64$4f8m12a/xlog=off 2006.246.07:38:22.64:!2006.246.07:38:50 2006.246.07:38:33.14#trakl#Source acquired 2006.246.07:38:35.15#flagr#flagr/antenna,acquired 2006.246.07:38:50.02:preob 2006.246.07:38:51.15/onsource/TRACKING 2006.246.07:38:51.15:!2006.246.07:39:00 2006.246.07:39:00.02:data_valid=on 2006.246.07:39:00.02:midob 2006.246.07:39:01.15/onsource/TRACKING 2006.246.07:39:01.15/wx/26.76,1005.6,74 2006.246.07:39:01.25/cable/+6.4154E-03 2006.246.07:39:02.34/va/01,08,usb,yes,31,32 2006.246.07:39:02.34/va/02,07,usb,yes,30,32 2006.246.07:39:02.34/va/03,06,usb,yes,32,33 2006.246.07:39:02.34/va/04,07,usb,yes,32,34 2006.246.07:39:02.34/va/05,07,usb,yes,33,35 2006.246.07:39:02.34/va/06,07,usb,yes,29,29 2006.246.07:39:02.34/va/07,07,usb,yes,29,29 2006.246.07:39:02.34/va/08,08,usb,yes,25,25 2006.246.07:39:02.57/valo/01,532.99,yes,locked 2006.246.07:39:02.57/valo/02,572.99,yes,locked 2006.246.07:39:02.57/valo/03,672.99,yes,locked 2006.246.07:39:02.57/valo/04,832.99,yes,locked 2006.246.07:39:02.57/valo/05,652.99,yes,locked 2006.246.07:39:02.57/valo/06,772.99,yes,locked 2006.246.07:39:02.57/valo/07,832.99,yes,locked 2006.246.07:39:02.57/valo/08,852.99,yes,locked 2006.246.07:39:03.66/vb/01,04,usb,yes,30,29 2006.246.07:39:03.66/vb/02,04,usb,yes,32,33 2006.246.07:39:03.66/vb/03,04,usb,yes,28,32 2006.246.07:39:03.66/vb/04,04,usb,yes,29,29 2006.246.07:39:03.66/vb/05,03,usb,yes,34,39 2006.246.07:39:03.66/vb/06,03,usb,yes,35,38 2006.246.07:39:03.66/vb/07,04,usb,yes,31,30 2006.246.07:39:03.66/vb/08,03,usb,yes,35,39 2006.246.07:39:03.90/vblo/01,632.99,yes,locked 2006.246.07:39:03.90/vblo/02,640.99,yes,locked 2006.246.07:39:03.90/vblo/03,656.99,yes,locked 2006.246.07:39:03.90/vblo/04,712.99,yes,locked 2006.246.07:39:03.90/vblo/05,744.99,yes,locked 2006.246.07:39:03.90/vblo/06,752.99,yes,locked 2006.246.07:39:03.90/vblo/07,734.99,yes,locked 2006.246.07:39:03.90/vblo/08,744.99,yes,locked 2006.246.07:39:04.05/vabw/8 2006.246.07:39:04.20/vbbw/8 2006.246.07:39:04.29/xfe/off,on,13.2 2006.246.07:39:04.66/ifatt/23,28,28,28 2006.246.07:39:05.07/fmout-gps/S +4.34E-07 2006.246.07:39:05.12:!2006.246.07:40:00 2006.246.07:40:00.00:data_valid=off 2006.246.07:40:00.01:postob 2006.246.07:40:00.15/cable/+6.4158E-03 2006.246.07:40:00.15/wx/26.75,1005.6,73 2006.246.07:40:01.07/fmout-gps/S +4.33E-07 2006.246.07:40:01.08:scan_name=246-0741,k06246,60 2006.246.07:40:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.246.07:40:02.14#flagr#flagr/antenna,new-source 2006.246.07:40:02.15:checkk5 2006.246.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:40:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:40:04.01/chk_obsdata//k5ts1/T2460739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:40:04.39/chk_obsdata//k5ts2/T2460739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:40:04.76/chk_obsdata//k5ts3/T2460739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:40:05.13/chk_obsdata//k5ts4/T2460739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:40:05.83/k5log//k5ts1_log_newline 2006.246.07:40:06.55/k5log//k5ts2_log_newline 2006.246.07:40:07.24/k5log//k5ts3_log_newline 2006.246.07:40:07.94/k5log//k5ts4_log_newline 2006.246.07:40:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:40:07.96:4f8m12a=1 2006.246.07:40:07.96$4f8m12a/echo=on 2006.246.07:40:07.96$4f8m12a/pcalon 2006.246.07:40:07.96$pcalon/"no phase cal control is implemented here 2006.246.07:40:07.97$4f8m12a/"tpicd=stop 2006.246.07:40:07.97$4f8m12a/vc4f8 2006.246.07:40:07.97$vc4f8/valo=1,532.99 2006.246.07:40:07.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:40:07.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:40:07.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:07.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:07.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:07.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:07.97#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:40:07.97#ibcon#first serial, iclass 19, count 0 2006.246.07:40:07.97#ibcon#enter sib2, iclass 19, count 0 2006.246.07:40:07.97#ibcon#flushed, iclass 19, count 0 2006.246.07:40:07.97#ibcon#about to write, iclass 19, count 0 2006.246.07:40:07.97#ibcon#wrote, iclass 19, count 0 2006.246.07:40:07.97#ibcon#about to read 3, iclass 19, count 0 2006.246.07:40:08.01#ibcon#read 3, iclass 19, count 0 2006.246.07:40:08.01#ibcon#about to read 4, iclass 19, count 0 2006.246.07:40:08.01#ibcon#read 4, iclass 19, count 0 2006.246.07:40:08.01#ibcon#about to read 5, iclass 19, count 0 2006.246.07:40:08.01#ibcon#read 5, iclass 19, count 0 2006.246.07:40:08.01#ibcon#about to read 6, iclass 19, count 0 2006.246.07:40:08.01#ibcon#read 6, iclass 19, count 0 2006.246.07:40:08.01#ibcon#end of sib2, iclass 19, count 0 2006.246.07:40:08.01#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:40:08.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:40:08.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:40:08.01#ibcon#*before write, iclass 19, count 0 2006.246.07:40:08.01#ibcon#enter sib2, iclass 19, count 0 2006.246.07:40:08.01#ibcon#flushed, iclass 19, count 0 2006.246.07:40:08.01#ibcon#about to write, iclass 19, count 0 2006.246.07:40:08.01#ibcon#wrote, iclass 19, count 0 2006.246.07:40:08.01#ibcon#about to read 3, iclass 19, count 0 2006.246.07:40:08.05#ibcon#read 3, iclass 19, count 0 2006.246.07:40:08.05#ibcon#about to read 4, iclass 19, count 0 2006.246.07:40:08.05#ibcon#read 4, iclass 19, count 0 2006.246.07:40:08.05#ibcon#about to read 5, iclass 19, count 0 2006.246.07:40:08.05#ibcon#read 5, iclass 19, count 0 2006.246.07:40:08.05#ibcon#about to read 6, iclass 19, count 0 2006.246.07:40:08.05#ibcon#read 6, iclass 19, count 0 2006.246.07:40:08.05#ibcon#end of sib2, iclass 19, count 0 2006.246.07:40:08.05#ibcon#*after write, iclass 19, count 0 2006.246.07:40:08.05#ibcon#*before return 0, iclass 19, count 0 2006.246.07:40:08.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:08.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:08.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:40:08.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:40:08.05$vc4f8/va=1,8 2006.246.07:40:08.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:40:08.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:40:08.05#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:08.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:08.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:08.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:08.05#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:40:08.05#ibcon#first serial, iclass 21, count 2 2006.246.07:40:08.05#ibcon#enter sib2, iclass 21, count 2 2006.246.07:40:08.05#ibcon#flushed, iclass 21, count 2 2006.246.07:40:08.05#ibcon#about to write, iclass 21, count 2 2006.246.07:40:08.05#ibcon#wrote, iclass 21, count 2 2006.246.07:40:08.05#ibcon#about to read 3, iclass 21, count 2 2006.246.07:40:08.07#ibcon#read 3, iclass 21, count 2 2006.246.07:40:08.07#ibcon#about to read 4, iclass 21, count 2 2006.246.07:40:08.07#ibcon#read 4, iclass 21, count 2 2006.246.07:40:08.07#ibcon#about to read 5, iclass 21, count 2 2006.246.07:40:08.07#ibcon#read 5, iclass 21, count 2 2006.246.07:40:08.07#ibcon#about to read 6, iclass 21, count 2 2006.246.07:40:08.07#ibcon#read 6, iclass 21, count 2 2006.246.07:40:08.07#ibcon#end of sib2, iclass 21, count 2 2006.246.07:40:08.07#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:40:08.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:40:08.07#ibcon#[25=AT01-08\r\n] 2006.246.07:40:08.07#ibcon#*before write, iclass 21, count 2 2006.246.07:40:08.07#ibcon#enter sib2, iclass 21, count 2 2006.246.07:40:08.07#ibcon#flushed, iclass 21, count 2 2006.246.07:40:08.07#ibcon#about to write, iclass 21, count 2 2006.246.07:40:08.07#ibcon#wrote, iclass 21, count 2 2006.246.07:40:08.07#ibcon#about to read 3, iclass 21, count 2 2006.246.07:40:08.11#ibcon#read 3, iclass 21, count 2 2006.246.07:40:08.11#ibcon#about to read 4, iclass 21, count 2 2006.246.07:40:08.11#ibcon#read 4, iclass 21, count 2 2006.246.07:40:08.11#ibcon#about to read 5, iclass 21, count 2 2006.246.07:40:08.11#ibcon#read 5, iclass 21, count 2 2006.246.07:40:08.11#ibcon#about to read 6, iclass 21, count 2 2006.246.07:40:08.11#ibcon#read 6, iclass 21, count 2 2006.246.07:40:08.11#ibcon#end of sib2, iclass 21, count 2 2006.246.07:40:08.11#ibcon#*after write, iclass 21, count 2 2006.246.07:40:08.11#ibcon#*before return 0, iclass 21, count 2 2006.246.07:40:08.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:08.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:08.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:40:08.11#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:08.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:08.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:08.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:08.22#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:40:08.22#ibcon#first serial, iclass 21, count 0 2006.246.07:40:08.22#ibcon#enter sib2, iclass 21, count 0 2006.246.07:40:08.22#ibcon#flushed, iclass 21, count 0 2006.246.07:40:08.22#ibcon#about to write, iclass 21, count 0 2006.246.07:40:08.22#ibcon#wrote, iclass 21, count 0 2006.246.07:40:08.22#ibcon#about to read 3, iclass 21, count 0 2006.246.07:40:08.24#ibcon#read 3, iclass 21, count 0 2006.246.07:40:08.24#ibcon#about to read 4, iclass 21, count 0 2006.246.07:40:08.24#ibcon#read 4, iclass 21, count 0 2006.246.07:40:08.24#ibcon#about to read 5, iclass 21, count 0 2006.246.07:40:08.24#ibcon#read 5, iclass 21, count 0 2006.246.07:40:08.24#ibcon#about to read 6, iclass 21, count 0 2006.246.07:40:08.24#ibcon#read 6, iclass 21, count 0 2006.246.07:40:08.24#ibcon#end of sib2, iclass 21, count 0 2006.246.07:40:08.24#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:40:08.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:40:08.24#ibcon#[25=USB\r\n] 2006.246.07:40:08.24#ibcon#*before write, iclass 21, count 0 2006.246.07:40:08.24#ibcon#enter sib2, iclass 21, count 0 2006.246.07:40:08.24#ibcon#flushed, iclass 21, count 0 2006.246.07:40:08.24#ibcon#about to write, iclass 21, count 0 2006.246.07:40:08.24#ibcon#wrote, iclass 21, count 0 2006.246.07:40:08.24#ibcon#about to read 3, iclass 21, count 0 2006.246.07:40:08.27#ibcon#read 3, iclass 21, count 0 2006.246.07:40:08.27#ibcon#about to read 4, iclass 21, count 0 2006.246.07:40:08.27#ibcon#read 4, iclass 21, count 0 2006.246.07:40:08.27#ibcon#about to read 5, iclass 21, count 0 2006.246.07:40:08.27#ibcon#read 5, iclass 21, count 0 2006.246.07:40:08.27#ibcon#about to read 6, iclass 21, count 0 2006.246.07:40:08.27#ibcon#read 6, iclass 21, count 0 2006.246.07:40:08.27#ibcon#end of sib2, iclass 21, count 0 2006.246.07:40:08.27#ibcon#*after write, iclass 21, count 0 2006.246.07:40:08.27#ibcon#*before return 0, iclass 21, count 0 2006.246.07:40:08.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:08.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:08.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:40:08.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:40:08.27$vc4f8/valo=2,572.99 2006.246.07:40:08.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:40:08.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:40:08.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:08.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:08.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:08.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:08.27#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:40:08.27#ibcon#first serial, iclass 23, count 0 2006.246.07:40:08.27#ibcon#enter sib2, iclass 23, count 0 2006.246.07:40:08.27#ibcon#flushed, iclass 23, count 0 2006.246.07:40:08.27#ibcon#about to write, iclass 23, count 0 2006.246.07:40:08.27#ibcon#wrote, iclass 23, count 0 2006.246.07:40:08.27#ibcon#about to read 3, iclass 23, count 0 2006.246.07:40:08.29#ibcon#read 3, iclass 23, count 0 2006.246.07:40:08.29#ibcon#about to read 4, iclass 23, count 0 2006.246.07:40:08.29#ibcon#read 4, iclass 23, count 0 2006.246.07:40:08.29#ibcon#about to read 5, iclass 23, count 0 2006.246.07:40:08.29#ibcon#read 5, iclass 23, count 0 2006.246.07:40:08.29#ibcon#about to read 6, iclass 23, count 0 2006.246.07:40:08.29#ibcon#read 6, iclass 23, count 0 2006.246.07:40:08.29#ibcon#end of sib2, iclass 23, count 0 2006.246.07:40:08.29#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:40:08.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:40:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:40:08.29#ibcon#*before write, iclass 23, count 0 2006.246.07:40:08.29#ibcon#enter sib2, iclass 23, count 0 2006.246.07:40:08.29#ibcon#flushed, iclass 23, count 0 2006.246.07:40:08.29#ibcon#about to write, iclass 23, count 0 2006.246.07:40:08.29#ibcon#wrote, iclass 23, count 0 2006.246.07:40:08.29#ibcon#about to read 3, iclass 23, count 0 2006.246.07:40:08.33#ibcon#read 3, iclass 23, count 0 2006.246.07:40:08.33#ibcon#about to read 4, iclass 23, count 0 2006.246.07:40:08.33#ibcon#read 4, iclass 23, count 0 2006.246.07:40:08.33#ibcon#about to read 5, iclass 23, count 0 2006.246.07:40:08.33#ibcon#read 5, iclass 23, count 0 2006.246.07:40:08.33#ibcon#about to read 6, iclass 23, count 0 2006.246.07:40:08.33#ibcon#read 6, iclass 23, count 0 2006.246.07:40:08.33#ibcon#end of sib2, iclass 23, count 0 2006.246.07:40:08.33#ibcon#*after write, iclass 23, count 0 2006.246.07:40:08.33#ibcon#*before return 0, iclass 23, count 0 2006.246.07:40:08.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:08.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:08.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:40:08.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:40:08.33$vc4f8/va=2,7 2006.246.07:40:08.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:40:08.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:40:08.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:08.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:08.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:08.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:08.40#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:40:08.40#ibcon#first serial, iclass 25, count 2 2006.246.07:40:08.40#ibcon#enter sib2, iclass 25, count 2 2006.246.07:40:08.40#ibcon#flushed, iclass 25, count 2 2006.246.07:40:08.40#ibcon#about to write, iclass 25, count 2 2006.246.07:40:08.40#ibcon#wrote, iclass 25, count 2 2006.246.07:40:08.40#ibcon#about to read 3, iclass 25, count 2 2006.246.07:40:08.42#ibcon#read 3, iclass 25, count 2 2006.246.07:40:08.42#ibcon#about to read 4, iclass 25, count 2 2006.246.07:40:08.42#ibcon#read 4, iclass 25, count 2 2006.246.07:40:08.42#ibcon#about to read 5, iclass 25, count 2 2006.246.07:40:08.42#ibcon#read 5, iclass 25, count 2 2006.246.07:40:08.42#ibcon#about to read 6, iclass 25, count 2 2006.246.07:40:08.42#ibcon#read 6, iclass 25, count 2 2006.246.07:40:08.42#ibcon#end of sib2, iclass 25, count 2 2006.246.07:40:08.42#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:40:08.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:40:08.42#ibcon#[25=AT02-07\r\n] 2006.246.07:40:08.42#ibcon#*before write, iclass 25, count 2 2006.246.07:40:08.42#ibcon#enter sib2, iclass 25, count 2 2006.246.07:40:08.42#ibcon#flushed, iclass 25, count 2 2006.246.07:40:08.42#ibcon#about to write, iclass 25, count 2 2006.246.07:40:08.42#ibcon#wrote, iclass 25, count 2 2006.246.07:40:08.42#ibcon#about to read 3, iclass 25, count 2 2006.246.07:40:08.44#ibcon#read 3, iclass 25, count 2 2006.246.07:40:08.44#ibcon#about to read 4, iclass 25, count 2 2006.246.07:40:08.44#ibcon#read 4, iclass 25, count 2 2006.246.07:40:08.44#ibcon#about to read 5, iclass 25, count 2 2006.246.07:40:08.44#ibcon#read 5, iclass 25, count 2 2006.246.07:40:08.44#ibcon#about to read 6, iclass 25, count 2 2006.246.07:40:08.44#ibcon#read 6, iclass 25, count 2 2006.246.07:40:08.44#ibcon#end of sib2, iclass 25, count 2 2006.246.07:40:08.44#ibcon#*after write, iclass 25, count 2 2006.246.07:40:08.44#ibcon#*before return 0, iclass 25, count 2 2006.246.07:40:08.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:08.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:08.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:40:08.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:08.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:08.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:08.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:08.56#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:40:08.56#ibcon#first serial, iclass 25, count 0 2006.246.07:40:08.56#ibcon#enter sib2, iclass 25, count 0 2006.246.07:40:08.56#ibcon#flushed, iclass 25, count 0 2006.246.07:40:08.56#ibcon#about to write, iclass 25, count 0 2006.246.07:40:08.56#ibcon#wrote, iclass 25, count 0 2006.246.07:40:08.56#ibcon#about to read 3, iclass 25, count 0 2006.246.07:40:08.58#ibcon#read 3, iclass 25, count 0 2006.246.07:40:08.58#ibcon#about to read 4, iclass 25, count 0 2006.246.07:40:08.58#ibcon#read 4, iclass 25, count 0 2006.246.07:40:08.58#ibcon#about to read 5, iclass 25, count 0 2006.246.07:40:08.58#ibcon#read 5, iclass 25, count 0 2006.246.07:40:08.58#ibcon#about to read 6, iclass 25, count 0 2006.246.07:40:08.58#ibcon#read 6, iclass 25, count 0 2006.246.07:40:08.58#ibcon#end of sib2, iclass 25, count 0 2006.246.07:40:08.58#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:40:08.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:40:08.58#ibcon#[25=USB\r\n] 2006.246.07:40:08.58#ibcon#*before write, iclass 25, count 0 2006.246.07:40:08.58#ibcon#enter sib2, iclass 25, count 0 2006.246.07:40:08.58#ibcon#flushed, iclass 25, count 0 2006.246.07:40:08.58#ibcon#about to write, iclass 25, count 0 2006.246.07:40:08.58#ibcon#wrote, iclass 25, count 0 2006.246.07:40:08.58#ibcon#about to read 3, iclass 25, count 0 2006.246.07:40:08.61#ibcon#read 3, iclass 25, count 0 2006.246.07:40:08.61#ibcon#about to read 4, iclass 25, count 0 2006.246.07:40:08.61#ibcon#read 4, iclass 25, count 0 2006.246.07:40:08.61#ibcon#about to read 5, iclass 25, count 0 2006.246.07:40:08.61#ibcon#read 5, iclass 25, count 0 2006.246.07:40:08.61#ibcon#about to read 6, iclass 25, count 0 2006.246.07:40:08.61#ibcon#read 6, iclass 25, count 0 2006.246.07:40:08.61#ibcon#end of sib2, iclass 25, count 0 2006.246.07:40:08.61#ibcon#*after write, iclass 25, count 0 2006.246.07:40:08.61#ibcon#*before return 0, iclass 25, count 0 2006.246.07:40:08.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:08.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:08.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:40:08.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:40:08.61$vc4f8/valo=3,672.99 2006.246.07:40:08.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:40:08.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:40:08.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:08.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:08.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:08.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:08.61#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:40:08.61#ibcon#first serial, iclass 27, count 0 2006.246.07:40:08.61#ibcon#enter sib2, iclass 27, count 0 2006.246.07:40:08.61#ibcon#flushed, iclass 27, count 0 2006.246.07:40:08.61#ibcon#about to write, iclass 27, count 0 2006.246.07:40:08.61#ibcon#wrote, iclass 27, count 0 2006.246.07:40:08.61#ibcon#about to read 3, iclass 27, count 0 2006.246.07:40:08.63#ibcon#read 3, iclass 27, count 0 2006.246.07:40:08.63#ibcon#about to read 4, iclass 27, count 0 2006.246.07:40:08.63#ibcon#read 4, iclass 27, count 0 2006.246.07:40:08.63#ibcon#about to read 5, iclass 27, count 0 2006.246.07:40:08.63#ibcon#read 5, iclass 27, count 0 2006.246.07:40:08.63#ibcon#about to read 6, iclass 27, count 0 2006.246.07:40:08.63#ibcon#read 6, iclass 27, count 0 2006.246.07:40:08.63#ibcon#end of sib2, iclass 27, count 0 2006.246.07:40:08.63#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:40:08.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:40:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:40:08.63#ibcon#*before write, iclass 27, count 0 2006.246.07:40:08.63#ibcon#enter sib2, iclass 27, count 0 2006.246.07:40:08.63#ibcon#flushed, iclass 27, count 0 2006.246.07:40:08.63#ibcon#about to write, iclass 27, count 0 2006.246.07:40:08.63#ibcon#wrote, iclass 27, count 0 2006.246.07:40:08.63#ibcon#about to read 3, iclass 27, count 0 2006.246.07:40:08.67#ibcon#read 3, iclass 27, count 0 2006.246.07:40:08.67#ibcon#about to read 4, iclass 27, count 0 2006.246.07:40:08.67#ibcon#read 4, iclass 27, count 0 2006.246.07:40:08.67#ibcon#about to read 5, iclass 27, count 0 2006.246.07:40:08.67#ibcon#read 5, iclass 27, count 0 2006.246.07:40:08.67#ibcon#about to read 6, iclass 27, count 0 2006.246.07:40:08.67#ibcon#read 6, iclass 27, count 0 2006.246.07:40:08.67#ibcon#end of sib2, iclass 27, count 0 2006.246.07:40:08.67#ibcon#*after write, iclass 27, count 0 2006.246.07:40:08.67#ibcon#*before return 0, iclass 27, count 0 2006.246.07:40:08.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:08.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:08.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:40:08.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:40:08.67$vc4f8/va=3,6 2006.246.07:40:08.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.07:40:08.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.07:40:08.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:08.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:08.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:08.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:08.74#ibcon#enter wrdev, iclass 29, count 2 2006.246.07:40:08.74#ibcon#first serial, iclass 29, count 2 2006.246.07:40:08.74#ibcon#enter sib2, iclass 29, count 2 2006.246.07:40:08.74#ibcon#flushed, iclass 29, count 2 2006.246.07:40:08.74#ibcon#about to write, iclass 29, count 2 2006.246.07:40:08.74#ibcon#wrote, iclass 29, count 2 2006.246.07:40:08.74#ibcon#about to read 3, iclass 29, count 2 2006.246.07:40:08.76#ibcon#read 3, iclass 29, count 2 2006.246.07:40:08.76#ibcon#about to read 4, iclass 29, count 2 2006.246.07:40:08.76#ibcon#read 4, iclass 29, count 2 2006.246.07:40:08.76#ibcon#about to read 5, iclass 29, count 2 2006.246.07:40:08.76#ibcon#read 5, iclass 29, count 2 2006.246.07:40:08.76#ibcon#about to read 6, iclass 29, count 2 2006.246.07:40:08.76#ibcon#read 6, iclass 29, count 2 2006.246.07:40:08.76#ibcon#end of sib2, iclass 29, count 2 2006.246.07:40:08.76#ibcon#*mode == 0, iclass 29, count 2 2006.246.07:40:08.76#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.07:40:08.76#ibcon#[25=AT03-06\r\n] 2006.246.07:40:08.76#ibcon#*before write, iclass 29, count 2 2006.246.07:40:08.76#ibcon#enter sib2, iclass 29, count 2 2006.246.07:40:08.76#ibcon#flushed, iclass 29, count 2 2006.246.07:40:08.76#ibcon#about to write, iclass 29, count 2 2006.246.07:40:08.76#ibcon#wrote, iclass 29, count 2 2006.246.07:40:08.76#ibcon#about to read 3, iclass 29, count 2 2006.246.07:40:08.78#ibcon#read 3, iclass 29, count 2 2006.246.07:40:08.78#ibcon#about to read 4, iclass 29, count 2 2006.246.07:40:08.78#ibcon#read 4, iclass 29, count 2 2006.246.07:40:08.78#ibcon#about to read 5, iclass 29, count 2 2006.246.07:40:08.78#ibcon#read 5, iclass 29, count 2 2006.246.07:40:08.78#ibcon#about to read 6, iclass 29, count 2 2006.246.07:40:08.78#ibcon#read 6, iclass 29, count 2 2006.246.07:40:08.78#ibcon#end of sib2, iclass 29, count 2 2006.246.07:40:08.78#ibcon#*after write, iclass 29, count 2 2006.246.07:40:08.78#ibcon#*before return 0, iclass 29, count 2 2006.246.07:40:08.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:08.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:08.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.07:40:08.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:08.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:08.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:08.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:08.90#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:40:08.90#ibcon#first serial, iclass 29, count 0 2006.246.07:40:08.90#ibcon#enter sib2, iclass 29, count 0 2006.246.07:40:08.90#ibcon#flushed, iclass 29, count 0 2006.246.07:40:08.90#ibcon#about to write, iclass 29, count 0 2006.246.07:40:08.90#ibcon#wrote, iclass 29, count 0 2006.246.07:40:08.90#ibcon#about to read 3, iclass 29, count 0 2006.246.07:40:08.92#ibcon#read 3, iclass 29, count 0 2006.246.07:40:08.92#ibcon#about to read 4, iclass 29, count 0 2006.246.07:40:08.92#ibcon#read 4, iclass 29, count 0 2006.246.07:40:08.92#ibcon#about to read 5, iclass 29, count 0 2006.246.07:40:08.92#ibcon#read 5, iclass 29, count 0 2006.246.07:40:08.92#ibcon#about to read 6, iclass 29, count 0 2006.246.07:40:08.92#ibcon#read 6, iclass 29, count 0 2006.246.07:40:08.92#ibcon#end of sib2, iclass 29, count 0 2006.246.07:40:08.92#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:40:08.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:40:08.92#ibcon#[25=USB\r\n] 2006.246.07:40:08.92#ibcon#*before write, iclass 29, count 0 2006.246.07:40:08.92#ibcon#enter sib2, iclass 29, count 0 2006.246.07:40:08.92#ibcon#flushed, iclass 29, count 0 2006.246.07:40:08.92#ibcon#about to write, iclass 29, count 0 2006.246.07:40:08.92#ibcon#wrote, iclass 29, count 0 2006.246.07:40:08.92#ibcon#about to read 3, iclass 29, count 0 2006.246.07:40:08.95#ibcon#read 3, iclass 29, count 0 2006.246.07:40:08.95#ibcon#about to read 4, iclass 29, count 0 2006.246.07:40:08.95#ibcon#read 4, iclass 29, count 0 2006.246.07:40:08.95#ibcon#about to read 5, iclass 29, count 0 2006.246.07:40:08.95#ibcon#read 5, iclass 29, count 0 2006.246.07:40:08.95#ibcon#about to read 6, iclass 29, count 0 2006.246.07:40:08.95#ibcon#read 6, iclass 29, count 0 2006.246.07:40:08.95#ibcon#end of sib2, iclass 29, count 0 2006.246.07:40:08.95#ibcon#*after write, iclass 29, count 0 2006.246.07:40:08.95#ibcon#*before return 0, iclass 29, count 0 2006.246.07:40:08.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:08.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:08.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:40:08.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:40:08.95$vc4f8/valo=4,832.99 2006.246.07:40:08.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.07:40:08.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.07:40:08.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:08.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:08.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:08.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:08.95#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:40:08.95#ibcon#first serial, iclass 31, count 0 2006.246.07:40:08.95#ibcon#enter sib2, iclass 31, count 0 2006.246.07:40:08.95#ibcon#flushed, iclass 31, count 0 2006.246.07:40:08.95#ibcon#about to write, iclass 31, count 0 2006.246.07:40:08.95#ibcon#wrote, iclass 31, count 0 2006.246.07:40:08.95#ibcon#about to read 3, iclass 31, count 0 2006.246.07:40:08.97#ibcon#read 3, iclass 31, count 0 2006.246.07:40:08.97#ibcon#about to read 4, iclass 31, count 0 2006.246.07:40:08.97#ibcon#read 4, iclass 31, count 0 2006.246.07:40:08.97#ibcon#about to read 5, iclass 31, count 0 2006.246.07:40:08.97#ibcon#read 5, iclass 31, count 0 2006.246.07:40:08.97#ibcon#about to read 6, iclass 31, count 0 2006.246.07:40:08.97#ibcon#read 6, iclass 31, count 0 2006.246.07:40:08.97#ibcon#end of sib2, iclass 31, count 0 2006.246.07:40:08.97#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:40:08.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:40:08.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:40:08.97#ibcon#*before write, iclass 31, count 0 2006.246.07:40:08.97#ibcon#enter sib2, iclass 31, count 0 2006.246.07:40:08.97#ibcon#flushed, iclass 31, count 0 2006.246.07:40:08.97#ibcon#about to write, iclass 31, count 0 2006.246.07:40:08.97#ibcon#wrote, iclass 31, count 0 2006.246.07:40:08.97#ibcon#about to read 3, iclass 31, count 0 2006.246.07:40:09.01#ibcon#read 3, iclass 31, count 0 2006.246.07:40:09.01#ibcon#about to read 4, iclass 31, count 0 2006.246.07:40:09.01#ibcon#read 4, iclass 31, count 0 2006.246.07:40:09.01#ibcon#about to read 5, iclass 31, count 0 2006.246.07:40:09.01#ibcon#read 5, iclass 31, count 0 2006.246.07:40:09.01#ibcon#about to read 6, iclass 31, count 0 2006.246.07:40:09.01#ibcon#read 6, iclass 31, count 0 2006.246.07:40:09.01#ibcon#end of sib2, iclass 31, count 0 2006.246.07:40:09.01#ibcon#*after write, iclass 31, count 0 2006.246.07:40:09.01#ibcon#*before return 0, iclass 31, count 0 2006.246.07:40:09.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:09.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:09.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:40:09.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:40:09.01$vc4f8/va=4,7 2006.246.07:40:09.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.07:40:09.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.07:40:09.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:09.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:09.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:09.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:09.07#ibcon#enter wrdev, iclass 33, count 2 2006.246.07:40:09.07#ibcon#first serial, iclass 33, count 2 2006.246.07:40:09.07#ibcon#enter sib2, iclass 33, count 2 2006.246.07:40:09.07#ibcon#flushed, iclass 33, count 2 2006.246.07:40:09.07#ibcon#about to write, iclass 33, count 2 2006.246.07:40:09.07#ibcon#wrote, iclass 33, count 2 2006.246.07:40:09.07#ibcon#about to read 3, iclass 33, count 2 2006.246.07:40:09.09#ibcon#read 3, iclass 33, count 2 2006.246.07:40:09.09#ibcon#about to read 4, iclass 33, count 2 2006.246.07:40:09.09#ibcon#read 4, iclass 33, count 2 2006.246.07:40:09.09#ibcon#about to read 5, iclass 33, count 2 2006.246.07:40:09.09#ibcon#read 5, iclass 33, count 2 2006.246.07:40:09.09#ibcon#about to read 6, iclass 33, count 2 2006.246.07:40:09.09#ibcon#read 6, iclass 33, count 2 2006.246.07:40:09.09#ibcon#end of sib2, iclass 33, count 2 2006.246.07:40:09.09#ibcon#*mode == 0, iclass 33, count 2 2006.246.07:40:09.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.07:40:09.09#ibcon#[25=AT04-07\r\n] 2006.246.07:40:09.09#ibcon#*before write, iclass 33, count 2 2006.246.07:40:09.09#ibcon#enter sib2, iclass 33, count 2 2006.246.07:40:09.09#ibcon#flushed, iclass 33, count 2 2006.246.07:40:09.09#ibcon#about to write, iclass 33, count 2 2006.246.07:40:09.09#ibcon#wrote, iclass 33, count 2 2006.246.07:40:09.09#ibcon#about to read 3, iclass 33, count 2 2006.246.07:40:09.12#ibcon#read 3, iclass 33, count 2 2006.246.07:40:09.12#ibcon#about to read 4, iclass 33, count 2 2006.246.07:40:09.12#ibcon#read 4, iclass 33, count 2 2006.246.07:40:09.12#ibcon#about to read 5, iclass 33, count 2 2006.246.07:40:09.12#ibcon#read 5, iclass 33, count 2 2006.246.07:40:09.12#ibcon#about to read 6, iclass 33, count 2 2006.246.07:40:09.12#ibcon#read 6, iclass 33, count 2 2006.246.07:40:09.12#ibcon#end of sib2, iclass 33, count 2 2006.246.07:40:09.12#ibcon#*after write, iclass 33, count 2 2006.246.07:40:09.12#ibcon#*before return 0, iclass 33, count 2 2006.246.07:40:09.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:09.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:09.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.07:40:09.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:09.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:09.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:09.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:09.24#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:40:09.24#ibcon#first serial, iclass 33, count 0 2006.246.07:40:09.24#ibcon#enter sib2, iclass 33, count 0 2006.246.07:40:09.24#ibcon#flushed, iclass 33, count 0 2006.246.07:40:09.24#ibcon#about to write, iclass 33, count 0 2006.246.07:40:09.24#ibcon#wrote, iclass 33, count 0 2006.246.07:40:09.24#ibcon#about to read 3, iclass 33, count 0 2006.246.07:40:09.26#ibcon#read 3, iclass 33, count 0 2006.246.07:40:09.26#ibcon#about to read 4, iclass 33, count 0 2006.246.07:40:09.26#ibcon#read 4, iclass 33, count 0 2006.246.07:40:09.26#ibcon#about to read 5, iclass 33, count 0 2006.246.07:40:09.26#ibcon#read 5, iclass 33, count 0 2006.246.07:40:09.26#ibcon#about to read 6, iclass 33, count 0 2006.246.07:40:09.26#ibcon#read 6, iclass 33, count 0 2006.246.07:40:09.26#ibcon#end of sib2, iclass 33, count 0 2006.246.07:40:09.26#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:40:09.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:40:09.26#ibcon#[25=USB\r\n] 2006.246.07:40:09.26#ibcon#*before write, iclass 33, count 0 2006.246.07:40:09.26#ibcon#enter sib2, iclass 33, count 0 2006.246.07:40:09.26#ibcon#flushed, iclass 33, count 0 2006.246.07:40:09.26#ibcon#about to write, iclass 33, count 0 2006.246.07:40:09.26#ibcon#wrote, iclass 33, count 0 2006.246.07:40:09.26#ibcon#about to read 3, iclass 33, count 0 2006.246.07:40:09.29#ibcon#read 3, iclass 33, count 0 2006.246.07:40:09.29#ibcon#about to read 4, iclass 33, count 0 2006.246.07:40:09.29#ibcon#read 4, iclass 33, count 0 2006.246.07:40:09.29#ibcon#about to read 5, iclass 33, count 0 2006.246.07:40:09.29#ibcon#read 5, iclass 33, count 0 2006.246.07:40:09.29#ibcon#about to read 6, iclass 33, count 0 2006.246.07:40:09.29#ibcon#read 6, iclass 33, count 0 2006.246.07:40:09.29#ibcon#end of sib2, iclass 33, count 0 2006.246.07:40:09.29#ibcon#*after write, iclass 33, count 0 2006.246.07:40:09.29#ibcon#*before return 0, iclass 33, count 0 2006.246.07:40:09.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:09.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:09.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:40:09.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:40:09.29$vc4f8/valo=5,652.99 2006.246.07:40:09.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.07:40:09.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.07:40:09.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:09.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:09.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:09.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:09.29#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:40:09.29#ibcon#first serial, iclass 35, count 0 2006.246.07:40:09.29#ibcon#enter sib2, iclass 35, count 0 2006.246.07:40:09.29#ibcon#flushed, iclass 35, count 0 2006.246.07:40:09.29#ibcon#about to write, iclass 35, count 0 2006.246.07:40:09.29#ibcon#wrote, iclass 35, count 0 2006.246.07:40:09.29#ibcon#about to read 3, iclass 35, count 0 2006.246.07:40:09.31#ibcon#read 3, iclass 35, count 0 2006.246.07:40:09.31#ibcon#about to read 4, iclass 35, count 0 2006.246.07:40:09.31#ibcon#read 4, iclass 35, count 0 2006.246.07:40:09.31#ibcon#about to read 5, iclass 35, count 0 2006.246.07:40:09.31#ibcon#read 5, iclass 35, count 0 2006.246.07:40:09.31#ibcon#about to read 6, iclass 35, count 0 2006.246.07:40:09.31#ibcon#read 6, iclass 35, count 0 2006.246.07:40:09.31#ibcon#end of sib2, iclass 35, count 0 2006.246.07:40:09.31#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:40:09.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:40:09.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:40:09.31#ibcon#*before write, iclass 35, count 0 2006.246.07:40:09.31#ibcon#enter sib2, iclass 35, count 0 2006.246.07:40:09.31#ibcon#flushed, iclass 35, count 0 2006.246.07:40:09.31#ibcon#about to write, iclass 35, count 0 2006.246.07:40:09.31#ibcon#wrote, iclass 35, count 0 2006.246.07:40:09.31#ibcon#about to read 3, iclass 35, count 0 2006.246.07:40:09.35#ibcon#read 3, iclass 35, count 0 2006.246.07:40:09.35#ibcon#about to read 4, iclass 35, count 0 2006.246.07:40:09.35#ibcon#read 4, iclass 35, count 0 2006.246.07:40:09.35#ibcon#about to read 5, iclass 35, count 0 2006.246.07:40:09.35#ibcon#read 5, iclass 35, count 0 2006.246.07:40:09.35#ibcon#about to read 6, iclass 35, count 0 2006.246.07:40:09.35#ibcon#read 6, iclass 35, count 0 2006.246.07:40:09.35#ibcon#end of sib2, iclass 35, count 0 2006.246.07:40:09.35#ibcon#*after write, iclass 35, count 0 2006.246.07:40:09.35#ibcon#*before return 0, iclass 35, count 0 2006.246.07:40:09.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:09.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:09.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:40:09.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:40:09.35$vc4f8/va=5,7 2006.246.07:40:09.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.07:40:09.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.07:40:09.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:09.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:09.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:09.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:09.41#ibcon#enter wrdev, iclass 37, count 2 2006.246.07:40:09.41#ibcon#first serial, iclass 37, count 2 2006.246.07:40:09.41#ibcon#enter sib2, iclass 37, count 2 2006.246.07:40:09.41#ibcon#flushed, iclass 37, count 2 2006.246.07:40:09.41#ibcon#about to write, iclass 37, count 2 2006.246.07:40:09.41#ibcon#wrote, iclass 37, count 2 2006.246.07:40:09.41#ibcon#about to read 3, iclass 37, count 2 2006.246.07:40:09.43#ibcon#read 3, iclass 37, count 2 2006.246.07:40:09.43#ibcon#about to read 4, iclass 37, count 2 2006.246.07:40:09.43#ibcon#read 4, iclass 37, count 2 2006.246.07:40:09.43#ibcon#about to read 5, iclass 37, count 2 2006.246.07:40:09.43#ibcon#read 5, iclass 37, count 2 2006.246.07:40:09.43#ibcon#about to read 6, iclass 37, count 2 2006.246.07:40:09.43#ibcon#read 6, iclass 37, count 2 2006.246.07:40:09.43#ibcon#end of sib2, iclass 37, count 2 2006.246.07:40:09.43#ibcon#*mode == 0, iclass 37, count 2 2006.246.07:40:09.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.07:40:09.43#ibcon#[25=AT05-07\r\n] 2006.246.07:40:09.43#ibcon#*before write, iclass 37, count 2 2006.246.07:40:09.43#ibcon#enter sib2, iclass 37, count 2 2006.246.07:40:09.43#ibcon#flushed, iclass 37, count 2 2006.246.07:40:09.43#ibcon#about to write, iclass 37, count 2 2006.246.07:40:09.43#ibcon#wrote, iclass 37, count 2 2006.246.07:40:09.43#ibcon#about to read 3, iclass 37, count 2 2006.246.07:40:09.46#ibcon#read 3, iclass 37, count 2 2006.246.07:40:09.46#ibcon#about to read 4, iclass 37, count 2 2006.246.07:40:09.46#ibcon#read 4, iclass 37, count 2 2006.246.07:40:09.46#ibcon#about to read 5, iclass 37, count 2 2006.246.07:40:09.46#ibcon#read 5, iclass 37, count 2 2006.246.07:40:09.46#ibcon#about to read 6, iclass 37, count 2 2006.246.07:40:09.46#ibcon#read 6, iclass 37, count 2 2006.246.07:40:09.46#ibcon#end of sib2, iclass 37, count 2 2006.246.07:40:09.46#ibcon#*after write, iclass 37, count 2 2006.246.07:40:09.46#ibcon#*before return 0, iclass 37, count 2 2006.246.07:40:09.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:09.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:09.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.07:40:09.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:09.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:09.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:09.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:09.58#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:40:09.58#ibcon#first serial, iclass 37, count 0 2006.246.07:40:09.58#ibcon#enter sib2, iclass 37, count 0 2006.246.07:40:09.58#ibcon#flushed, iclass 37, count 0 2006.246.07:40:09.58#ibcon#about to write, iclass 37, count 0 2006.246.07:40:09.58#ibcon#wrote, iclass 37, count 0 2006.246.07:40:09.58#ibcon#about to read 3, iclass 37, count 0 2006.246.07:40:09.60#ibcon#read 3, iclass 37, count 0 2006.246.07:40:09.60#ibcon#about to read 4, iclass 37, count 0 2006.246.07:40:09.60#ibcon#read 4, iclass 37, count 0 2006.246.07:40:09.60#ibcon#about to read 5, iclass 37, count 0 2006.246.07:40:09.60#ibcon#read 5, iclass 37, count 0 2006.246.07:40:09.60#ibcon#about to read 6, iclass 37, count 0 2006.246.07:40:09.60#ibcon#read 6, iclass 37, count 0 2006.246.07:40:09.60#ibcon#end of sib2, iclass 37, count 0 2006.246.07:40:09.60#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:40:09.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:40:09.60#ibcon#[25=USB\r\n] 2006.246.07:40:09.60#ibcon#*before write, iclass 37, count 0 2006.246.07:40:09.60#ibcon#enter sib2, iclass 37, count 0 2006.246.07:40:09.60#ibcon#flushed, iclass 37, count 0 2006.246.07:40:09.60#ibcon#about to write, iclass 37, count 0 2006.246.07:40:09.60#ibcon#wrote, iclass 37, count 0 2006.246.07:40:09.60#ibcon#about to read 3, iclass 37, count 0 2006.246.07:40:09.63#ibcon#read 3, iclass 37, count 0 2006.246.07:40:09.63#ibcon#about to read 4, iclass 37, count 0 2006.246.07:40:09.63#ibcon#read 4, iclass 37, count 0 2006.246.07:40:09.63#ibcon#about to read 5, iclass 37, count 0 2006.246.07:40:09.63#ibcon#read 5, iclass 37, count 0 2006.246.07:40:09.63#ibcon#about to read 6, iclass 37, count 0 2006.246.07:40:09.63#ibcon#read 6, iclass 37, count 0 2006.246.07:40:09.63#ibcon#end of sib2, iclass 37, count 0 2006.246.07:40:09.63#ibcon#*after write, iclass 37, count 0 2006.246.07:40:09.63#ibcon#*before return 0, iclass 37, count 0 2006.246.07:40:09.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:09.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:09.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:40:09.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:40:09.63$vc4f8/valo=6,772.99 2006.246.07:40:09.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:40:09.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:40:09.63#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:09.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:09.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:09.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:09.63#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:40:09.63#ibcon#first serial, iclass 39, count 0 2006.246.07:40:09.63#ibcon#enter sib2, iclass 39, count 0 2006.246.07:40:09.63#ibcon#flushed, iclass 39, count 0 2006.246.07:40:09.63#ibcon#about to write, iclass 39, count 0 2006.246.07:40:09.63#ibcon#wrote, iclass 39, count 0 2006.246.07:40:09.63#ibcon#about to read 3, iclass 39, count 0 2006.246.07:40:09.65#ibcon#read 3, iclass 39, count 0 2006.246.07:40:09.65#ibcon#about to read 4, iclass 39, count 0 2006.246.07:40:09.65#ibcon#read 4, iclass 39, count 0 2006.246.07:40:09.65#ibcon#about to read 5, iclass 39, count 0 2006.246.07:40:09.65#ibcon#read 5, iclass 39, count 0 2006.246.07:40:09.65#ibcon#about to read 6, iclass 39, count 0 2006.246.07:40:09.65#ibcon#read 6, iclass 39, count 0 2006.246.07:40:09.65#ibcon#end of sib2, iclass 39, count 0 2006.246.07:40:09.65#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:40:09.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:40:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:40:09.65#ibcon#*before write, iclass 39, count 0 2006.246.07:40:09.65#ibcon#enter sib2, iclass 39, count 0 2006.246.07:40:09.65#ibcon#flushed, iclass 39, count 0 2006.246.07:40:09.65#ibcon#about to write, iclass 39, count 0 2006.246.07:40:09.65#ibcon#wrote, iclass 39, count 0 2006.246.07:40:09.65#ibcon#about to read 3, iclass 39, count 0 2006.246.07:40:09.69#ibcon#read 3, iclass 39, count 0 2006.246.07:40:09.69#ibcon#about to read 4, iclass 39, count 0 2006.246.07:40:09.69#ibcon#read 4, iclass 39, count 0 2006.246.07:40:09.69#ibcon#about to read 5, iclass 39, count 0 2006.246.07:40:09.69#ibcon#read 5, iclass 39, count 0 2006.246.07:40:09.69#ibcon#about to read 6, iclass 39, count 0 2006.246.07:40:09.69#ibcon#read 6, iclass 39, count 0 2006.246.07:40:09.69#ibcon#end of sib2, iclass 39, count 0 2006.246.07:40:09.69#ibcon#*after write, iclass 39, count 0 2006.246.07:40:09.69#ibcon#*before return 0, iclass 39, count 0 2006.246.07:40:09.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:09.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:09.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:40:09.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:40:09.69$vc4f8/va=6,7 2006.246.07:40:09.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.07:40:09.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.07:40:09.69#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:09.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:40:09.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:40:09.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:40:09.76#ibcon#enter wrdev, iclass 3, count 2 2006.246.07:40:09.76#ibcon#first serial, iclass 3, count 2 2006.246.07:40:09.76#ibcon#enter sib2, iclass 3, count 2 2006.246.07:40:09.76#ibcon#flushed, iclass 3, count 2 2006.246.07:40:09.76#ibcon#about to write, iclass 3, count 2 2006.246.07:40:09.76#ibcon#wrote, iclass 3, count 2 2006.246.07:40:09.76#ibcon#about to read 3, iclass 3, count 2 2006.246.07:40:09.78#ibcon#read 3, iclass 3, count 2 2006.246.07:40:09.78#ibcon#about to read 4, iclass 3, count 2 2006.246.07:40:09.78#ibcon#read 4, iclass 3, count 2 2006.246.07:40:09.78#ibcon#about to read 5, iclass 3, count 2 2006.246.07:40:09.78#ibcon#read 5, iclass 3, count 2 2006.246.07:40:09.78#ibcon#about to read 6, iclass 3, count 2 2006.246.07:40:09.78#ibcon#read 6, iclass 3, count 2 2006.246.07:40:09.78#ibcon#end of sib2, iclass 3, count 2 2006.246.07:40:09.78#ibcon#*mode == 0, iclass 3, count 2 2006.246.07:40:09.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.07:40:09.78#ibcon#[25=AT06-07\r\n] 2006.246.07:40:09.78#ibcon#*before write, iclass 3, count 2 2006.246.07:40:09.78#ibcon#enter sib2, iclass 3, count 2 2006.246.07:40:09.78#ibcon#flushed, iclass 3, count 2 2006.246.07:40:09.78#ibcon#about to write, iclass 3, count 2 2006.246.07:40:09.78#ibcon#wrote, iclass 3, count 2 2006.246.07:40:09.78#ibcon#about to read 3, iclass 3, count 2 2006.246.07:40:09.80#ibcon#read 3, iclass 3, count 2 2006.246.07:40:09.80#ibcon#about to read 4, iclass 3, count 2 2006.246.07:40:09.80#ibcon#read 4, iclass 3, count 2 2006.246.07:40:09.80#ibcon#about to read 5, iclass 3, count 2 2006.246.07:40:09.80#ibcon#read 5, iclass 3, count 2 2006.246.07:40:09.80#ibcon#about to read 6, iclass 3, count 2 2006.246.07:40:09.80#ibcon#read 6, iclass 3, count 2 2006.246.07:40:09.80#ibcon#end of sib2, iclass 3, count 2 2006.246.07:40:09.80#ibcon#*after write, iclass 3, count 2 2006.246.07:40:09.80#ibcon#*before return 0, iclass 3, count 2 2006.246.07:40:09.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:40:09.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:40:09.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.07:40:09.80#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:09.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:40:09.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:40:09.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:40:09.92#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:40:09.92#ibcon#first serial, iclass 3, count 0 2006.246.07:40:09.92#ibcon#enter sib2, iclass 3, count 0 2006.246.07:40:09.92#ibcon#flushed, iclass 3, count 0 2006.246.07:40:09.92#ibcon#about to write, iclass 3, count 0 2006.246.07:40:09.92#ibcon#wrote, iclass 3, count 0 2006.246.07:40:09.92#ibcon#about to read 3, iclass 3, count 0 2006.246.07:40:09.94#ibcon#read 3, iclass 3, count 0 2006.246.07:40:09.94#ibcon#about to read 4, iclass 3, count 0 2006.246.07:40:09.94#ibcon#read 4, iclass 3, count 0 2006.246.07:40:09.94#ibcon#about to read 5, iclass 3, count 0 2006.246.07:40:09.94#ibcon#read 5, iclass 3, count 0 2006.246.07:40:09.94#ibcon#about to read 6, iclass 3, count 0 2006.246.07:40:09.94#ibcon#read 6, iclass 3, count 0 2006.246.07:40:09.94#ibcon#end of sib2, iclass 3, count 0 2006.246.07:40:09.94#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:40:09.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:40:09.94#ibcon#[25=USB\r\n] 2006.246.07:40:09.94#ibcon#*before write, iclass 3, count 0 2006.246.07:40:09.94#ibcon#enter sib2, iclass 3, count 0 2006.246.07:40:09.94#ibcon#flushed, iclass 3, count 0 2006.246.07:40:09.94#ibcon#about to write, iclass 3, count 0 2006.246.07:40:09.94#ibcon#wrote, iclass 3, count 0 2006.246.07:40:09.94#ibcon#about to read 3, iclass 3, count 0 2006.246.07:40:09.97#ibcon#read 3, iclass 3, count 0 2006.246.07:40:09.97#ibcon#about to read 4, iclass 3, count 0 2006.246.07:40:09.97#ibcon#read 4, iclass 3, count 0 2006.246.07:40:09.97#ibcon#about to read 5, iclass 3, count 0 2006.246.07:40:09.97#ibcon#read 5, iclass 3, count 0 2006.246.07:40:09.97#ibcon#about to read 6, iclass 3, count 0 2006.246.07:40:09.97#ibcon#read 6, iclass 3, count 0 2006.246.07:40:09.97#ibcon#end of sib2, iclass 3, count 0 2006.246.07:40:09.97#ibcon#*after write, iclass 3, count 0 2006.246.07:40:09.97#ibcon#*before return 0, iclass 3, count 0 2006.246.07:40:09.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:40:09.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:40:09.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:40:09.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:40:09.97$vc4f8/valo=7,832.99 2006.246.07:40:09.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:40:09.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:40:09.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:09.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:40:09.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:40:09.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:40:09.97#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:40:09.97#ibcon#first serial, iclass 5, count 0 2006.246.07:40:09.97#ibcon#enter sib2, iclass 5, count 0 2006.246.07:40:09.97#ibcon#flushed, iclass 5, count 0 2006.246.07:40:09.97#ibcon#about to write, iclass 5, count 0 2006.246.07:40:09.97#ibcon#wrote, iclass 5, count 0 2006.246.07:40:09.97#ibcon#about to read 3, iclass 5, count 0 2006.246.07:40:09.99#ibcon#read 3, iclass 5, count 0 2006.246.07:40:09.99#ibcon#about to read 4, iclass 5, count 0 2006.246.07:40:09.99#ibcon#read 4, iclass 5, count 0 2006.246.07:40:09.99#ibcon#about to read 5, iclass 5, count 0 2006.246.07:40:09.99#ibcon#read 5, iclass 5, count 0 2006.246.07:40:09.99#ibcon#about to read 6, iclass 5, count 0 2006.246.07:40:09.99#ibcon#read 6, iclass 5, count 0 2006.246.07:40:09.99#ibcon#end of sib2, iclass 5, count 0 2006.246.07:40:09.99#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:40:09.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:40:09.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:40:09.99#ibcon#*before write, iclass 5, count 0 2006.246.07:40:09.99#ibcon#enter sib2, iclass 5, count 0 2006.246.07:40:09.99#ibcon#flushed, iclass 5, count 0 2006.246.07:40:09.99#ibcon#about to write, iclass 5, count 0 2006.246.07:40:09.99#ibcon#wrote, iclass 5, count 0 2006.246.07:40:09.99#ibcon#about to read 3, iclass 5, count 0 2006.246.07:40:10.03#ibcon#read 3, iclass 5, count 0 2006.246.07:40:10.03#ibcon#about to read 4, iclass 5, count 0 2006.246.07:40:10.03#ibcon#read 4, iclass 5, count 0 2006.246.07:40:10.03#ibcon#about to read 5, iclass 5, count 0 2006.246.07:40:10.03#ibcon#read 5, iclass 5, count 0 2006.246.07:40:10.03#ibcon#about to read 6, iclass 5, count 0 2006.246.07:40:10.03#ibcon#read 6, iclass 5, count 0 2006.246.07:40:10.03#ibcon#end of sib2, iclass 5, count 0 2006.246.07:40:10.03#ibcon#*after write, iclass 5, count 0 2006.246.07:40:10.03#ibcon#*before return 0, iclass 5, count 0 2006.246.07:40:10.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:40:10.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:40:10.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:40:10.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:40:10.03$vc4f8/va=7,7 2006.246.07:40:10.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:40:10.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:40:10.03#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:10.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:40:10.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:40:10.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:40:10.09#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:40:10.09#ibcon#first serial, iclass 7, count 2 2006.246.07:40:10.09#ibcon#enter sib2, iclass 7, count 2 2006.246.07:40:10.09#ibcon#flushed, iclass 7, count 2 2006.246.07:40:10.09#ibcon#about to write, iclass 7, count 2 2006.246.07:40:10.09#ibcon#wrote, iclass 7, count 2 2006.246.07:40:10.09#ibcon#about to read 3, iclass 7, count 2 2006.246.07:40:10.11#ibcon#read 3, iclass 7, count 2 2006.246.07:40:10.11#ibcon#about to read 4, iclass 7, count 2 2006.246.07:40:10.11#ibcon#read 4, iclass 7, count 2 2006.246.07:40:10.11#ibcon#about to read 5, iclass 7, count 2 2006.246.07:40:10.11#ibcon#read 5, iclass 7, count 2 2006.246.07:40:10.11#ibcon#about to read 6, iclass 7, count 2 2006.246.07:40:10.11#ibcon#read 6, iclass 7, count 2 2006.246.07:40:10.11#ibcon#end of sib2, iclass 7, count 2 2006.246.07:40:10.11#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:40:10.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:40:10.11#ibcon#[25=AT07-07\r\n] 2006.246.07:40:10.11#ibcon#*before write, iclass 7, count 2 2006.246.07:40:10.11#ibcon#enter sib2, iclass 7, count 2 2006.246.07:40:10.11#ibcon#flushed, iclass 7, count 2 2006.246.07:40:10.11#ibcon#about to write, iclass 7, count 2 2006.246.07:40:10.11#ibcon#wrote, iclass 7, count 2 2006.246.07:40:10.11#ibcon#about to read 3, iclass 7, count 2 2006.246.07:40:10.14#ibcon#read 3, iclass 7, count 2 2006.246.07:40:10.14#ibcon#about to read 4, iclass 7, count 2 2006.246.07:40:10.14#ibcon#read 4, iclass 7, count 2 2006.246.07:40:10.14#ibcon#about to read 5, iclass 7, count 2 2006.246.07:40:10.14#ibcon#read 5, iclass 7, count 2 2006.246.07:40:10.15#ibcon#about to read 6, iclass 7, count 2 2006.246.07:40:10.15#ibcon#read 6, iclass 7, count 2 2006.246.07:40:10.15#ibcon#end of sib2, iclass 7, count 2 2006.246.07:40:10.15#ibcon#*after write, iclass 7, count 2 2006.246.07:40:10.15#ibcon#*before return 0, iclass 7, count 2 2006.246.07:40:10.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:40:10.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:40:10.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:40:10.15#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:10.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:40:10.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:40:10.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:40:10.26#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:40:10.26#ibcon#first serial, iclass 7, count 0 2006.246.07:40:10.26#ibcon#enter sib2, iclass 7, count 0 2006.246.07:40:10.26#ibcon#flushed, iclass 7, count 0 2006.246.07:40:10.26#ibcon#about to write, iclass 7, count 0 2006.246.07:40:10.26#ibcon#wrote, iclass 7, count 0 2006.246.07:40:10.26#ibcon#about to read 3, iclass 7, count 0 2006.246.07:40:10.28#ibcon#read 3, iclass 7, count 0 2006.246.07:40:10.28#ibcon#about to read 4, iclass 7, count 0 2006.246.07:40:10.28#ibcon#read 4, iclass 7, count 0 2006.246.07:40:10.28#ibcon#about to read 5, iclass 7, count 0 2006.246.07:40:10.28#ibcon#read 5, iclass 7, count 0 2006.246.07:40:10.28#ibcon#about to read 6, iclass 7, count 0 2006.246.07:40:10.28#ibcon#read 6, iclass 7, count 0 2006.246.07:40:10.28#ibcon#end of sib2, iclass 7, count 0 2006.246.07:40:10.28#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:40:10.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:40:10.28#ibcon#[25=USB\r\n] 2006.246.07:40:10.28#ibcon#*before write, iclass 7, count 0 2006.246.07:40:10.28#ibcon#enter sib2, iclass 7, count 0 2006.246.07:40:10.28#ibcon#flushed, iclass 7, count 0 2006.246.07:40:10.28#ibcon#about to write, iclass 7, count 0 2006.246.07:40:10.28#ibcon#wrote, iclass 7, count 0 2006.246.07:40:10.28#ibcon#about to read 3, iclass 7, count 0 2006.246.07:40:10.31#ibcon#read 3, iclass 7, count 0 2006.246.07:40:10.31#ibcon#about to read 4, iclass 7, count 0 2006.246.07:40:10.31#ibcon#read 4, iclass 7, count 0 2006.246.07:40:10.31#ibcon#about to read 5, iclass 7, count 0 2006.246.07:40:10.31#ibcon#read 5, iclass 7, count 0 2006.246.07:40:10.31#ibcon#about to read 6, iclass 7, count 0 2006.246.07:40:10.31#ibcon#read 6, iclass 7, count 0 2006.246.07:40:10.31#ibcon#end of sib2, iclass 7, count 0 2006.246.07:40:10.31#ibcon#*after write, iclass 7, count 0 2006.246.07:40:10.31#ibcon#*before return 0, iclass 7, count 0 2006.246.07:40:10.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:40:10.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:40:10.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:40:10.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:40:10.31$vc4f8/valo=8,852.99 2006.246.07:40:10.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:40:10.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:40:10.31#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:10.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:40:10.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:40:10.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:40:10.31#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:40:10.31#ibcon#first serial, iclass 11, count 0 2006.246.07:40:10.31#ibcon#enter sib2, iclass 11, count 0 2006.246.07:40:10.31#ibcon#flushed, iclass 11, count 0 2006.246.07:40:10.31#ibcon#about to write, iclass 11, count 0 2006.246.07:40:10.31#ibcon#wrote, iclass 11, count 0 2006.246.07:40:10.31#ibcon#about to read 3, iclass 11, count 0 2006.246.07:40:10.33#ibcon#read 3, iclass 11, count 0 2006.246.07:40:10.33#ibcon#about to read 4, iclass 11, count 0 2006.246.07:40:10.33#ibcon#read 4, iclass 11, count 0 2006.246.07:40:10.33#ibcon#about to read 5, iclass 11, count 0 2006.246.07:40:10.33#ibcon#read 5, iclass 11, count 0 2006.246.07:40:10.33#ibcon#about to read 6, iclass 11, count 0 2006.246.07:40:10.33#ibcon#read 6, iclass 11, count 0 2006.246.07:40:10.33#ibcon#end of sib2, iclass 11, count 0 2006.246.07:40:10.33#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:40:10.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:40:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:40:10.33#ibcon#*before write, iclass 11, count 0 2006.246.07:40:10.33#ibcon#enter sib2, iclass 11, count 0 2006.246.07:40:10.33#ibcon#flushed, iclass 11, count 0 2006.246.07:40:10.33#ibcon#about to write, iclass 11, count 0 2006.246.07:40:10.33#ibcon#wrote, iclass 11, count 0 2006.246.07:40:10.33#ibcon#about to read 3, iclass 11, count 0 2006.246.07:40:10.37#ibcon#read 3, iclass 11, count 0 2006.246.07:40:10.37#ibcon#about to read 4, iclass 11, count 0 2006.246.07:40:10.37#ibcon#read 4, iclass 11, count 0 2006.246.07:40:10.37#ibcon#about to read 5, iclass 11, count 0 2006.246.07:40:10.37#ibcon#read 5, iclass 11, count 0 2006.246.07:40:10.37#ibcon#about to read 6, iclass 11, count 0 2006.246.07:40:10.37#ibcon#read 6, iclass 11, count 0 2006.246.07:40:10.37#ibcon#end of sib2, iclass 11, count 0 2006.246.07:40:10.37#ibcon#*after write, iclass 11, count 0 2006.246.07:40:10.37#ibcon#*before return 0, iclass 11, count 0 2006.246.07:40:10.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:40:10.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:40:10.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:40:10.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:40:10.37$vc4f8/va=8,8 2006.246.07:40:10.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:40:10.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:40:10.37#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:10.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:40:10.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:40:10.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:40:10.44#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:40:10.44#ibcon#first serial, iclass 13, count 2 2006.246.07:40:10.44#ibcon#enter sib2, iclass 13, count 2 2006.246.07:40:10.44#ibcon#flushed, iclass 13, count 2 2006.246.07:40:10.44#ibcon#about to write, iclass 13, count 2 2006.246.07:40:10.44#ibcon#wrote, iclass 13, count 2 2006.246.07:40:10.44#ibcon#about to read 3, iclass 13, count 2 2006.246.07:40:10.46#ibcon#read 3, iclass 13, count 2 2006.246.07:40:10.46#ibcon#about to read 4, iclass 13, count 2 2006.246.07:40:10.46#ibcon#read 4, iclass 13, count 2 2006.246.07:40:10.46#ibcon#about to read 5, iclass 13, count 2 2006.246.07:40:10.46#ibcon#read 5, iclass 13, count 2 2006.246.07:40:10.46#ibcon#about to read 6, iclass 13, count 2 2006.246.07:40:10.46#ibcon#read 6, iclass 13, count 2 2006.246.07:40:10.46#ibcon#end of sib2, iclass 13, count 2 2006.246.07:40:10.46#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:40:10.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:40:10.46#ibcon#[25=AT08-08\r\n] 2006.246.07:40:10.46#ibcon#*before write, iclass 13, count 2 2006.246.07:40:10.46#ibcon#enter sib2, iclass 13, count 2 2006.246.07:40:10.46#ibcon#flushed, iclass 13, count 2 2006.246.07:40:10.46#ibcon#about to write, iclass 13, count 2 2006.246.07:40:10.46#ibcon#wrote, iclass 13, count 2 2006.246.07:40:10.46#ibcon#about to read 3, iclass 13, count 2 2006.246.07:40:10.48#ibcon#read 3, iclass 13, count 2 2006.246.07:40:10.48#ibcon#about to read 4, iclass 13, count 2 2006.246.07:40:10.48#ibcon#read 4, iclass 13, count 2 2006.246.07:40:10.48#ibcon#about to read 5, iclass 13, count 2 2006.246.07:40:10.48#ibcon#read 5, iclass 13, count 2 2006.246.07:40:10.48#ibcon#about to read 6, iclass 13, count 2 2006.246.07:40:10.48#ibcon#read 6, iclass 13, count 2 2006.246.07:40:10.48#ibcon#end of sib2, iclass 13, count 2 2006.246.07:40:10.48#ibcon#*after write, iclass 13, count 2 2006.246.07:40:10.48#ibcon#*before return 0, iclass 13, count 2 2006.246.07:40:10.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:40:10.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:40:10.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:40:10.48#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:10.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:40:10.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:40:10.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:40:10.60#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:40:10.60#ibcon#first serial, iclass 13, count 0 2006.246.07:40:10.60#ibcon#enter sib2, iclass 13, count 0 2006.246.07:40:10.60#ibcon#flushed, iclass 13, count 0 2006.246.07:40:10.60#ibcon#about to write, iclass 13, count 0 2006.246.07:40:10.60#ibcon#wrote, iclass 13, count 0 2006.246.07:40:10.60#ibcon#about to read 3, iclass 13, count 0 2006.246.07:40:10.62#ibcon#read 3, iclass 13, count 0 2006.246.07:40:10.62#ibcon#about to read 4, iclass 13, count 0 2006.246.07:40:10.62#ibcon#read 4, iclass 13, count 0 2006.246.07:40:10.62#ibcon#about to read 5, iclass 13, count 0 2006.246.07:40:10.62#ibcon#read 5, iclass 13, count 0 2006.246.07:40:10.62#ibcon#about to read 6, iclass 13, count 0 2006.246.07:40:10.62#ibcon#read 6, iclass 13, count 0 2006.246.07:40:10.62#ibcon#end of sib2, iclass 13, count 0 2006.246.07:40:10.62#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:40:10.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:40:10.62#ibcon#[25=USB\r\n] 2006.246.07:40:10.62#ibcon#*before write, iclass 13, count 0 2006.246.07:40:10.62#ibcon#enter sib2, iclass 13, count 0 2006.246.07:40:10.62#ibcon#flushed, iclass 13, count 0 2006.246.07:40:10.62#ibcon#about to write, iclass 13, count 0 2006.246.07:40:10.62#ibcon#wrote, iclass 13, count 0 2006.246.07:40:10.62#ibcon#about to read 3, iclass 13, count 0 2006.246.07:40:10.65#ibcon#read 3, iclass 13, count 0 2006.246.07:40:10.65#ibcon#about to read 4, iclass 13, count 0 2006.246.07:40:10.65#ibcon#read 4, iclass 13, count 0 2006.246.07:40:10.65#ibcon#about to read 5, iclass 13, count 0 2006.246.07:40:10.65#ibcon#read 5, iclass 13, count 0 2006.246.07:40:10.65#ibcon#about to read 6, iclass 13, count 0 2006.246.07:40:10.65#ibcon#read 6, iclass 13, count 0 2006.246.07:40:10.65#ibcon#end of sib2, iclass 13, count 0 2006.246.07:40:10.65#ibcon#*after write, iclass 13, count 0 2006.246.07:40:10.65#ibcon#*before return 0, iclass 13, count 0 2006.246.07:40:10.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:40:10.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:40:10.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:40:10.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:40:10.65$vc4f8/vblo=1,632.99 2006.246.07:40:10.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:40:10.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:40:10.65#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:10.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:40:10.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:40:10.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:40:10.65#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:40:10.65#ibcon#first serial, iclass 15, count 0 2006.246.07:40:10.65#ibcon#enter sib2, iclass 15, count 0 2006.246.07:40:10.65#ibcon#flushed, iclass 15, count 0 2006.246.07:40:10.65#ibcon#about to write, iclass 15, count 0 2006.246.07:40:10.65#ibcon#wrote, iclass 15, count 0 2006.246.07:40:10.65#ibcon#about to read 3, iclass 15, count 0 2006.246.07:40:10.67#ibcon#read 3, iclass 15, count 0 2006.246.07:40:10.67#ibcon#about to read 4, iclass 15, count 0 2006.246.07:40:10.67#ibcon#read 4, iclass 15, count 0 2006.246.07:40:10.67#ibcon#about to read 5, iclass 15, count 0 2006.246.07:40:10.67#ibcon#read 5, iclass 15, count 0 2006.246.07:40:10.67#ibcon#about to read 6, iclass 15, count 0 2006.246.07:40:10.67#ibcon#read 6, iclass 15, count 0 2006.246.07:40:10.67#ibcon#end of sib2, iclass 15, count 0 2006.246.07:40:10.67#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:40:10.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:40:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:40:10.67#ibcon#*before write, iclass 15, count 0 2006.246.07:40:10.67#ibcon#enter sib2, iclass 15, count 0 2006.246.07:40:10.67#ibcon#flushed, iclass 15, count 0 2006.246.07:40:10.67#ibcon#about to write, iclass 15, count 0 2006.246.07:40:10.67#ibcon#wrote, iclass 15, count 0 2006.246.07:40:10.67#ibcon#about to read 3, iclass 15, count 0 2006.246.07:40:10.71#ibcon#read 3, iclass 15, count 0 2006.246.07:40:10.71#ibcon#about to read 4, iclass 15, count 0 2006.246.07:40:10.71#ibcon#read 4, iclass 15, count 0 2006.246.07:40:10.71#ibcon#about to read 5, iclass 15, count 0 2006.246.07:40:10.71#ibcon#read 5, iclass 15, count 0 2006.246.07:40:10.71#ibcon#about to read 6, iclass 15, count 0 2006.246.07:40:10.71#ibcon#read 6, iclass 15, count 0 2006.246.07:40:10.71#ibcon#end of sib2, iclass 15, count 0 2006.246.07:40:10.71#ibcon#*after write, iclass 15, count 0 2006.246.07:40:10.71#ibcon#*before return 0, iclass 15, count 0 2006.246.07:40:10.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:40:10.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:40:10.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:40:10.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:40:10.71$vc4f8/vb=1,4 2006.246.07:40:10.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.07:40:10.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.07:40:10.71#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:10.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:40:10.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:40:10.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:40:10.71#ibcon#enter wrdev, iclass 17, count 2 2006.246.07:40:10.71#ibcon#first serial, iclass 17, count 2 2006.246.07:40:10.71#ibcon#enter sib2, iclass 17, count 2 2006.246.07:40:10.71#ibcon#flushed, iclass 17, count 2 2006.246.07:40:10.71#ibcon#about to write, iclass 17, count 2 2006.246.07:40:10.71#ibcon#wrote, iclass 17, count 2 2006.246.07:40:10.71#ibcon#about to read 3, iclass 17, count 2 2006.246.07:40:10.73#ibcon#read 3, iclass 17, count 2 2006.246.07:40:10.73#ibcon#about to read 4, iclass 17, count 2 2006.246.07:40:10.73#ibcon#read 4, iclass 17, count 2 2006.246.07:40:10.73#ibcon#about to read 5, iclass 17, count 2 2006.246.07:40:10.73#ibcon#read 5, iclass 17, count 2 2006.246.07:40:10.73#ibcon#about to read 6, iclass 17, count 2 2006.246.07:40:10.73#ibcon#read 6, iclass 17, count 2 2006.246.07:40:10.73#ibcon#end of sib2, iclass 17, count 2 2006.246.07:40:10.73#ibcon#*mode == 0, iclass 17, count 2 2006.246.07:40:10.73#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.07:40:10.73#ibcon#[27=AT01-04\r\n] 2006.246.07:40:10.73#ibcon#*before write, iclass 17, count 2 2006.246.07:40:10.73#ibcon#enter sib2, iclass 17, count 2 2006.246.07:40:10.73#ibcon#flushed, iclass 17, count 2 2006.246.07:40:10.73#ibcon#about to write, iclass 17, count 2 2006.246.07:40:10.73#ibcon#wrote, iclass 17, count 2 2006.246.07:40:10.73#ibcon#about to read 3, iclass 17, count 2 2006.246.07:40:10.76#ibcon#read 3, iclass 17, count 2 2006.246.07:40:10.76#ibcon#about to read 4, iclass 17, count 2 2006.246.07:40:10.76#ibcon#read 4, iclass 17, count 2 2006.246.07:40:10.76#ibcon#about to read 5, iclass 17, count 2 2006.246.07:40:10.76#ibcon#read 5, iclass 17, count 2 2006.246.07:40:10.76#ibcon#about to read 6, iclass 17, count 2 2006.246.07:40:10.76#ibcon#read 6, iclass 17, count 2 2006.246.07:40:10.76#ibcon#end of sib2, iclass 17, count 2 2006.246.07:40:10.76#ibcon#*after write, iclass 17, count 2 2006.246.07:40:10.76#ibcon#*before return 0, iclass 17, count 2 2006.246.07:40:10.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:40:10.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:40:10.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.07:40:10.76#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:10.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:40:10.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:40:10.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:40:10.88#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:40:10.88#ibcon#first serial, iclass 17, count 0 2006.246.07:40:10.88#ibcon#enter sib2, iclass 17, count 0 2006.246.07:40:10.88#ibcon#flushed, iclass 17, count 0 2006.246.07:40:10.88#ibcon#about to write, iclass 17, count 0 2006.246.07:40:10.88#ibcon#wrote, iclass 17, count 0 2006.246.07:40:10.88#ibcon#about to read 3, iclass 17, count 0 2006.246.07:40:10.90#ibcon#read 3, iclass 17, count 0 2006.246.07:40:10.90#ibcon#about to read 4, iclass 17, count 0 2006.246.07:40:10.90#ibcon#read 4, iclass 17, count 0 2006.246.07:40:10.90#ibcon#about to read 5, iclass 17, count 0 2006.246.07:40:10.90#ibcon#read 5, iclass 17, count 0 2006.246.07:40:10.90#ibcon#about to read 6, iclass 17, count 0 2006.246.07:40:10.90#ibcon#read 6, iclass 17, count 0 2006.246.07:40:10.90#ibcon#end of sib2, iclass 17, count 0 2006.246.07:40:10.90#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:40:10.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:40:10.90#ibcon#[27=USB\r\n] 2006.246.07:40:10.90#ibcon#*before write, iclass 17, count 0 2006.246.07:40:10.90#ibcon#enter sib2, iclass 17, count 0 2006.246.07:40:10.90#ibcon#flushed, iclass 17, count 0 2006.246.07:40:10.90#ibcon#about to write, iclass 17, count 0 2006.246.07:40:10.90#ibcon#wrote, iclass 17, count 0 2006.246.07:40:10.90#ibcon#about to read 3, iclass 17, count 0 2006.246.07:40:10.93#ibcon#read 3, iclass 17, count 0 2006.246.07:40:10.93#ibcon#about to read 4, iclass 17, count 0 2006.246.07:40:10.93#ibcon#read 4, iclass 17, count 0 2006.246.07:40:10.93#ibcon#about to read 5, iclass 17, count 0 2006.246.07:40:10.93#ibcon#read 5, iclass 17, count 0 2006.246.07:40:10.93#ibcon#about to read 6, iclass 17, count 0 2006.246.07:40:10.93#ibcon#read 6, iclass 17, count 0 2006.246.07:40:10.93#ibcon#end of sib2, iclass 17, count 0 2006.246.07:40:10.93#ibcon#*after write, iclass 17, count 0 2006.246.07:40:10.93#ibcon#*before return 0, iclass 17, count 0 2006.246.07:40:10.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:40:10.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:40:10.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:40:10.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:40:10.93$vc4f8/vblo=2,640.99 2006.246.07:40:10.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:40:10.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:40:10.93#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:10.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:10.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:10.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:10.93#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:40:10.93#ibcon#first serial, iclass 19, count 0 2006.246.07:40:10.93#ibcon#enter sib2, iclass 19, count 0 2006.246.07:40:10.93#ibcon#flushed, iclass 19, count 0 2006.246.07:40:10.93#ibcon#about to write, iclass 19, count 0 2006.246.07:40:10.93#ibcon#wrote, iclass 19, count 0 2006.246.07:40:10.93#ibcon#about to read 3, iclass 19, count 0 2006.246.07:40:10.95#ibcon#read 3, iclass 19, count 0 2006.246.07:40:10.95#ibcon#about to read 4, iclass 19, count 0 2006.246.07:40:10.95#ibcon#read 4, iclass 19, count 0 2006.246.07:40:10.95#ibcon#about to read 5, iclass 19, count 0 2006.246.07:40:10.95#ibcon#read 5, iclass 19, count 0 2006.246.07:40:10.95#ibcon#about to read 6, iclass 19, count 0 2006.246.07:40:10.95#ibcon#read 6, iclass 19, count 0 2006.246.07:40:10.95#ibcon#end of sib2, iclass 19, count 0 2006.246.07:40:10.95#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:40:10.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:40:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:40:10.95#ibcon#*before write, iclass 19, count 0 2006.246.07:40:10.95#ibcon#enter sib2, iclass 19, count 0 2006.246.07:40:10.95#ibcon#flushed, iclass 19, count 0 2006.246.07:40:10.95#ibcon#about to write, iclass 19, count 0 2006.246.07:40:10.95#ibcon#wrote, iclass 19, count 0 2006.246.07:40:10.95#ibcon#about to read 3, iclass 19, count 0 2006.246.07:40:10.99#ibcon#read 3, iclass 19, count 0 2006.246.07:40:10.99#ibcon#about to read 4, iclass 19, count 0 2006.246.07:40:10.99#ibcon#read 4, iclass 19, count 0 2006.246.07:40:10.99#ibcon#about to read 5, iclass 19, count 0 2006.246.07:40:10.99#ibcon#read 5, iclass 19, count 0 2006.246.07:40:10.99#ibcon#about to read 6, iclass 19, count 0 2006.246.07:40:10.99#ibcon#read 6, iclass 19, count 0 2006.246.07:40:10.99#ibcon#end of sib2, iclass 19, count 0 2006.246.07:40:10.99#ibcon#*after write, iclass 19, count 0 2006.246.07:40:10.99#ibcon#*before return 0, iclass 19, count 0 2006.246.07:40:10.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:10.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:40:10.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:40:10.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:40:10.99$vc4f8/vb=2,4 2006.246.07:40:10.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:40:10.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:40:10.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:10.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:11.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:11.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:11.05#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:40:11.05#ibcon#first serial, iclass 21, count 2 2006.246.07:40:11.05#ibcon#enter sib2, iclass 21, count 2 2006.246.07:40:11.05#ibcon#flushed, iclass 21, count 2 2006.246.07:40:11.05#ibcon#about to write, iclass 21, count 2 2006.246.07:40:11.05#ibcon#wrote, iclass 21, count 2 2006.246.07:40:11.05#ibcon#about to read 3, iclass 21, count 2 2006.246.07:40:11.07#ibcon#read 3, iclass 21, count 2 2006.246.07:40:11.07#ibcon#about to read 4, iclass 21, count 2 2006.246.07:40:11.07#ibcon#read 4, iclass 21, count 2 2006.246.07:40:11.07#ibcon#about to read 5, iclass 21, count 2 2006.246.07:40:11.07#ibcon#read 5, iclass 21, count 2 2006.246.07:40:11.07#ibcon#about to read 6, iclass 21, count 2 2006.246.07:40:11.07#ibcon#read 6, iclass 21, count 2 2006.246.07:40:11.07#ibcon#end of sib2, iclass 21, count 2 2006.246.07:40:11.07#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:40:11.07#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:40:11.07#ibcon#[27=AT02-04\r\n] 2006.246.07:40:11.07#ibcon#*before write, iclass 21, count 2 2006.246.07:40:11.07#ibcon#enter sib2, iclass 21, count 2 2006.246.07:40:11.07#ibcon#flushed, iclass 21, count 2 2006.246.07:40:11.07#ibcon#about to write, iclass 21, count 2 2006.246.07:40:11.07#ibcon#wrote, iclass 21, count 2 2006.246.07:40:11.07#ibcon#about to read 3, iclass 21, count 2 2006.246.07:40:11.10#ibcon#read 3, iclass 21, count 2 2006.246.07:40:11.10#ibcon#about to read 4, iclass 21, count 2 2006.246.07:40:11.10#ibcon#read 4, iclass 21, count 2 2006.246.07:40:11.10#ibcon#about to read 5, iclass 21, count 2 2006.246.07:40:11.10#ibcon#read 5, iclass 21, count 2 2006.246.07:40:11.10#ibcon#about to read 6, iclass 21, count 2 2006.246.07:40:11.10#ibcon#read 6, iclass 21, count 2 2006.246.07:40:11.10#ibcon#end of sib2, iclass 21, count 2 2006.246.07:40:11.10#ibcon#*after write, iclass 21, count 2 2006.246.07:40:11.10#ibcon#*before return 0, iclass 21, count 2 2006.246.07:40:11.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:11.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:40:11.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:40:11.10#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:11.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:11.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:11.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:11.22#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:40:11.22#ibcon#first serial, iclass 21, count 0 2006.246.07:40:11.22#ibcon#enter sib2, iclass 21, count 0 2006.246.07:40:11.22#ibcon#flushed, iclass 21, count 0 2006.246.07:40:11.22#ibcon#about to write, iclass 21, count 0 2006.246.07:40:11.22#ibcon#wrote, iclass 21, count 0 2006.246.07:40:11.22#ibcon#about to read 3, iclass 21, count 0 2006.246.07:40:11.24#ibcon#read 3, iclass 21, count 0 2006.246.07:40:11.24#ibcon#about to read 4, iclass 21, count 0 2006.246.07:40:11.24#ibcon#read 4, iclass 21, count 0 2006.246.07:40:11.24#ibcon#about to read 5, iclass 21, count 0 2006.246.07:40:11.24#ibcon#read 5, iclass 21, count 0 2006.246.07:40:11.24#ibcon#about to read 6, iclass 21, count 0 2006.246.07:40:11.24#ibcon#read 6, iclass 21, count 0 2006.246.07:40:11.24#ibcon#end of sib2, iclass 21, count 0 2006.246.07:40:11.24#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:40:11.24#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:40:11.24#ibcon#[27=USB\r\n] 2006.246.07:40:11.24#ibcon#*before write, iclass 21, count 0 2006.246.07:40:11.24#ibcon#enter sib2, iclass 21, count 0 2006.246.07:40:11.24#ibcon#flushed, iclass 21, count 0 2006.246.07:40:11.24#ibcon#about to write, iclass 21, count 0 2006.246.07:40:11.24#ibcon#wrote, iclass 21, count 0 2006.246.07:40:11.24#ibcon#about to read 3, iclass 21, count 0 2006.246.07:40:11.27#ibcon#read 3, iclass 21, count 0 2006.246.07:40:11.27#ibcon#about to read 4, iclass 21, count 0 2006.246.07:40:11.27#ibcon#read 4, iclass 21, count 0 2006.246.07:40:11.27#ibcon#about to read 5, iclass 21, count 0 2006.246.07:40:11.27#ibcon#read 5, iclass 21, count 0 2006.246.07:40:11.27#ibcon#about to read 6, iclass 21, count 0 2006.246.07:40:11.27#ibcon#read 6, iclass 21, count 0 2006.246.07:40:11.27#ibcon#end of sib2, iclass 21, count 0 2006.246.07:40:11.27#ibcon#*after write, iclass 21, count 0 2006.246.07:40:11.27#ibcon#*before return 0, iclass 21, count 0 2006.246.07:40:11.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:11.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:40:11.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:40:11.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:40:11.27$vc4f8/vblo=3,656.99 2006.246.07:40:11.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:40:11.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:40:11.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:11.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:11.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:11.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:11.27#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:40:11.27#ibcon#first serial, iclass 23, count 0 2006.246.07:40:11.27#ibcon#enter sib2, iclass 23, count 0 2006.246.07:40:11.27#ibcon#flushed, iclass 23, count 0 2006.246.07:40:11.27#ibcon#about to write, iclass 23, count 0 2006.246.07:40:11.28#ibcon#wrote, iclass 23, count 0 2006.246.07:40:11.28#ibcon#about to read 3, iclass 23, count 0 2006.246.07:40:11.29#ibcon#read 3, iclass 23, count 0 2006.246.07:40:11.29#ibcon#about to read 4, iclass 23, count 0 2006.246.07:40:11.29#ibcon#read 4, iclass 23, count 0 2006.246.07:40:11.29#ibcon#about to read 5, iclass 23, count 0 2006.246.07:40:11.29#ibcon#read 5, iclass 23, count 0 2006.246.07:40:11.29#ibcon#about to read 6, iclass 23, count 0 2006.246.07:40:11.29#ibcon#read 6, iclass 23, count 0 2006.246.07:40:11.29#ibcon#end of sib2, iclass 23, count 0 2006.246.07:40:11.29#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:40:11.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:40:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:40:11.29#ibcon#*before write, iclass 23, count 0 2006.246.07:40:11.29#ibcon#enter sib2, iclass 23, count 0 2006.246.07:40:11.29#ibcon#flushed, iclass 23, count 0 2006.246.07:40:11.29#ibcon#about to write, iclass 23, count 0 2006.246.07:40:11.29#ibcon#wrote, iclass 23, count 0 2006.246.07:40:11.29#ibcon#about to read 3, iclass 23, count 0 2006.246.07:40:11.33#ibcon#read 3, iclass 23, count 0 2006.246.07:40:11.33#ibcon#about to read 4, iclass 23, count 0 2006.246.07:40:11.33#ibcon#read 4, iclass 23, count 0 2006.246.07:40:11.33#ibcon#about to read 5, iclass 23, count 0 2006.246.07:40:11.33#ibcon#read 5, iclass 23, count 0 2006.246.07:40:11.33#ibcon#about to read 6, iclass 23, count 0 2006.246.07:40:11.33#ibcon#read 6, iclass 23, count 0 2006.246.07:40:11.33#ibcon#end of sib2, iclass 23, count 0 2006.246.07:40:11.33#ibcon#*after write, iclass 23, count 0 2006.246.07:40:11.33#ibcon#*before return 0, iclass 23, count 0 2006.246.07:40:11.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:11.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:40:11.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:40:11.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:40:11.33$vc4f8/vb=3,4 2006.246.07:40:11.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:40:11.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:40:11.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:11.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:11.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:11.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:11.39#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:40:11.39#ibcon#first serial, iclass 25, count 2 2006.246.07:40:11.39#ibcon#enter sib2, iclass 25, count 2 2006.246.07:40:11.39#ibcon#flushed, iclass 25, count 2 2006.246.07:40:11.39#ibcon#about to write, iclass 25, count 2 2006.246.07:40:11.39#ibcon#wrote, iclass 25, count 2 2006.246.07:40:11.39#ibcon#about to read 3, iclass 25, count 2 2006.246.07:40:11.41#ibcon#read 3, iclass 25, count 2 2006.246.07:40:11.41#ibcon#about to read 4, iclass 25, count 2 2006.246.07:40:11.41#ibcon#read 4, iclass 25, count 2 2006.246.07:40:11.41#ibcon#about to read 5, iclass 25, count 2 2006.246.07:40:11.42#ibcon#read 5, iclass 25, count 2 2006.246.07:40:11.42#ibcon#about to read 6, iclass 25, count 2 2006.246.07:40:11.42#ibcon#read 6, iclass 25, count 2 2006.246.07:40:11.42#ibcon#end of sib2, iclass 25, count 2 2006.246.07:40:11.42#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:40:11.42#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:40:11.42#ibcon#[27=AT03-04\r\n] 2006.246.07:40:11.42#ibcon#*before write, iclass 25, count 2 2006.246.07:40:11.42#ibcon#enter sib2, iclass 25, count 2 2006.246.07:40:11.42#ibcon#flushed, iclass 25, count 2 2006.246.07:40:11.42#ibcon#about to write, iclass 25, count 2 2006.246.07:40:11.42#ibcon#wrote, iclass 25, count 2 2006.246.07:40:11.42#ibcon#about to read 3, iclass 25, count 2 2006.246.07:40:11.44#ibcon#read 3, iclass 25, count 2 2006.246.07:40:11.44#ibcon#about to read 4, iclass 25, count 2 2006.246.07:40:11.44#ibcon#read 4, iclass 25, count 2 2006.246.07:40:11.44#ibcon#about to read 5, iclass 25, count 2 2006.246.07:40:11.44#ibcon#read 5, iclass 25, count 2 2006.246.07:40:11.44#ibcon#about to read 6, iclass 25, count 2 2006.246.07:40:11.44#ibcon#read 6, iclass 25, count 2 2006.246.07:40:11.44#ibcon#end of sib2, iclass 25, count 2 2006.246.07:40:11.44#ibcon#*after write, iclass 25, count 2 2006.246.07:40:11.44#ibcon#*before return 0, iclass 25, count 2 2006.246.07:40:11.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:11.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:40:11.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:40:11.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:11.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:11.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:11.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:11.56#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:40:11.56#ibcon#first serial, iclass 25, count 0 2006.246.07:40:11.56#ibcon#enter sib2, iclass 25, count 0 2006.246.07:40:11.56#ibcon#flushed, iclass 25, count 0 2006.246.07:40:11.56#ibcon#about to write, iclass 25, count 0 2006.246.07:40:11.56#ibcon#wrote, iclass 25, count 0 2006.246.07:40:11.56#ibcon#about to read 3, iclass 25, count 0 2006.246.07:40:11.58#ibcon#read 3, iclass 25, count 0 2006.246.07:40:11.58#ibcon#about to read 4, iclass 25, count 0 2006.246.07:40:11.58#ibcon#read 4, iclass 25, count 0 2006.246.07:40:11.58#ibcon#about to read 5, iclass 25, count 0 2006.246.07:40:11.58#ibcon#read 5, iclass 25, count 0 2006.246.07:40:11.58#ibcon#about to read 6, iclass 25, count 0 2006.246.07:40:11.58#ibcon#read 6, iclass 25, count 0 2006.246.07:40:11.58#ibcon#end of sib2, iclass 25, count 0 2006.246.07:40:11.58#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:40:11.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:40:11.58#ibcon#[27=USB\r\n] 2006.246.07:40:11.58#ibcon#*before write, iclass 25, count 0 2006.246.07:40:11.58#ibcon#enter sib2, iclass 25, count 0 2006.246.07:40:11.58#ibcon#flushed, iclass 25, count 0 2006.246.07:40:11.58#ibcon#about to write, iclass 25, count 0 2006.246.07:40:11.58#ibcon#wrote, iclass 25, count 0 2006.246.07:40:11.58#ibcon#about to read 3, iclass 25, count 0 2006.246.07:40:11.61#ibcon#read 3, iclass 25, count 0 2006.246.07:40:11.61#ibcon#about to read 4, iclass 25, count 0 2006.246.07:40:11.61#ibcon#read 4, iclass 25, count 0 2006.246.07:40:11.61#ibcon#about to read 5, iclass 25, count 0 2006.246.07:40:11.61#ibcon#read 5, iclass 25, count 0 2006.246.07:40:11.61#ibcon#about to read 6, iclass 25, count 0 2006.246.07:40:11.61#ibcon#read 6, iclass 25, count 0 2006.246.07:40:11.61#ibcon#end of sib2, iclass 25, count 0 2006.246.07:40:11.61#ibcon#*after write, iclass 25, count 0 2006.246.07:40:11.61#ibcon#*before return 0, iclass 25, count 0 2006.246.07:40:11.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:11.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:40:11.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:40:11.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:40:11.61$vc4f8/vblo=4,712.99 2006.246.07:40:11.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:40:11.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:40:11.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:11.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:11.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:11.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:11.61#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:40:11.61#ibcon#first serial, iclass 27, count 0 2006.246.07:40:11.61#ibcon#enter sib2, iclass 27, count 0 2006.246.07:40:11.61#ibcon#flushed, iclass 27, count 0 2006.246.07:40:11.61#ibcon#about to write, iclass 27, count 0 2006.246.07:40:11.61#ibcon#wrote, iclass 27, count 0 2006.246.07:40:11.61#ibcon#about to read 3, iclass 27, count 0 2006.246.07:40:11.63#ibcon#read 3, iclass 27, count 0 2006.246.07:40:11.63#ibcon#about to read 4, iclass 27, count 0 2006.246.07:40:11.63#ibcon#read 4, iclass 27, count 0 2006.246.07:40:11.63#ibcon#about to read 5, iclass 27, count 0 2006.246.07:40:11.63#ibcon#read 5, iclass 27, count 0 2006.246.07:40:11.63#ibcon#about to read 6, iclass 27, count 0 2006.246.07:40:11.63#ibcon#read 6, iclass 27, count 0 2006.246.07:40:11.63#ibcon#end of sib2, iclass 27, count 0 2006.246.07:40:11.63#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:40:11.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:40:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:40:11.63#ibcon#*before write, iclass 27, count 0 2006.246.07:40:11.63#ibcon#enter sib2, iclass 27, count 0 2006.246.07:40:11.63#ibcon#flushed, iclass 27, count 0 2006.246.07:40:11.63#ibcon#about to write, iclass 27, count 0 2006.246.07:40:11.63#ibcon#wrote, iclass 27, count 0 2006.246.07:40:11.63#ibcon#about to read 3, iclass 27, count 0 2006.246.07:40:11.67#ibcon#read 3, iclass 27, count 0 2006.246.07:40:11.67#ibcon#about to read 4, iclass 27, count 0 2006.246.07:40:11.67#ibcon#read 4, iclass 27, count 0 2006.246.07:40:11.67#ibcon#about to read 5, iclass 27, count 0 2006.246.07:40:11.67#ibcon#read 5, iclass 27, count 0 2006.246.07:40:11.67#ibcon#about to read 6, iclass 27, count 0 2006.246.07:40:11.67#ibcon#read 6, iclass 27, count 0 2006.246.07:40:11.67#ibcon#end of sib2, iclass 27, count 0 2006.246.07:40:11.67#ibcon#*after write, iclass 27, count 0 2006.246.07:40:11.67#ibcon#*before return 0, iclass 27, count 0 2006.246.07:40:11.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:11.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:40:11.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:40:11.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:40:11.67$vc4f8/vb=4,4 2006.246.07:40:11.67#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.07:40:11.67#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.07:40:11.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:11.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:11.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:11.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:11.73#ibcon#enter wrdev, iclass 29, count 2 2006.246.07:40:11.73#ibcon#first serial, iclass 29, count 2 2006.246.07:40:11.73#ibcon#enter sib2, iclass 29, count 2 2006.246.07:40:11.73#ibcon#flushed, iclass 29, count 2 2006.246.07:40:11.73#ibcon#about to write, iclass 29, count 2 2006.246.07:40:11.73#ibcon#wrote, iclass 29, count 2 2006.246.07:40:11.73#ibcon#about to read 3, iclass 29, count 2 2006.246.07:40:11.75#ibcon#read 3, iclass 29, count 2 2006.246.07:40:11.75#ibcon#about to read 4, iclass 29, count 2 2006.246.07:40:11.75#ibcon#read 4, iclass 29, count 2 2006.246.07:40:11.75#ibcon#about to read 5, iclass 29, count 2 2006.246.07:40:11.75#ibcon#read 5, iclass 29, count 2 2006.246.07:40:11.75#ibcon#about to read 6, iclass 29, count 2 2006.246.07:40:11.75#ibcon#read 6, iclass 29, count 2 2006.246.07:40:11.75#ibcon#end of sib2, iclass 29, count 2 2006.246.07:40:11.75#ibcon#*mode == 0, iclass 29, count 2 2006.246.07:40:11.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.07:40:11.75#ibcon#[27=AT04-04\r\n] 2006.246.07:40:11.75#ibcon#*before write, iclass 29, count 2 2006.246.07:40:11.75#ibcon#enter sib2, iclass 29, count 2 2006.246.07:40:11.75#ibcon#flushed, iclass 29, count 2 2006.246.07:40:11.75#ibcon#about to write, iclass 29, count 2 2006.246.07:40:11.75#ibcon#wrote, iclass 29, count 2 2006.246.07:40:11.75#ibcon#about to read 3, iclass 29, count 2 2006.246.07:40:11.78#ibcon#read 3, iclass 29, count 2 2006.246.07:40:11.78#ibcon#about to read 4, iclass 29, count 2 2006.246.07:40:11.78#ibcon#read 4, iclass 29, count 2 2006.246.07:40:11.78#ibcon#about to read 5, iclass 29, count 2 2006.246.07:40:11.78#ibcon#read 5, iclass 29, count 2 2006.246.07:40:11.78#ibcon#about to read 6, iclass 29, count 2 2006.246.07:40:11.78#ibcon#read 6, iclass 29, count 2 2006.246.07:40:11.78#ibcon#end of sib2, iclass 29, count 2 2006.246.07:40:11.78#ibcon#*after write, iclass 29, count 2 2006.246.07:40:11.78#ibcon#*before return 0, iclass 29, count 2 2006.246.07:40:11.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:11.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:40:11.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.07:40:11.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:11.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:11.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:11.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:11.90#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:40:11.90#ibcon#first serial, iclass 29, count 0 2006.246.07:40:11.90#ibcon#enter sib2, iclass 29, count 0 2006.246.07:40:11.90#ibcon#flushed, iclass 29, count 0 2006.246.07:40:11.90#ibcon#about to write, iclass 29, count 0 2006.246.07:40:11.90#ibcon#wrote, iclass 29, count 0 2006.246.07:40:11.90#ibcon#about to read 3, iclass 29, count 0 2006.246.07:40:11.92#ibcon#read 3, iclass 29, count 0 2006.246.07:40:11.92#ibcon#about to read 4, iclass 29, count 0 2006.246.07:40:11.92#ibcon#read 4, iclass 29, count 0 2006.246.07:40:11.92#ibcon#about to read 5, iclass 29, count 0 2006.246.07:40:11.92#ibcon#read 5, iclass 29, count 0 2006.246.07:40:11.92#ibcon#about to read 6, iclass 29, count 0 2006.246.07:40:11.92#ibcon#read 6, iclass 29, count 0 2006.246.07:40:11.92#ibcon#end of sib2, iclass 29, count 0 2006.246.07:40:11.92#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:40:11.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:40:11.92#ibcon#[27=USB\r\n] 2006.246.07:40:11.92#ibcon#*before write, iclass 29, count 0 2006.246.07:40:11.92#ibcon#enter sib2, iclass 29, count 0 2006.246.07:40:11.92#ibcon#flushed, iclass 29, count 0 2006.246.07:40:11.92#ibcon#about to write, iclass 29, count 0 2006.246.07:40:11.92#ibcon#wrote, iclass 29, count 0 2006.246.07:40:11.92#ibcon#about to read 3, iclass 29, count 0 2006.246.07:40:11.95#ibcon#read 3, iclass 29, count 0 2006.246.07:40:11.95#ibcon#about to read 4, iclass 29, count 0 2006.246.07:40:11.95#ibcon#read 4, iclass 29, count 0 2006.246.07:40:11.95#ibcon#about to read 5, iclass 29, count 0 2006.246.07:40:11.95#ibcon#read 5, iclass 29, count 0 2006.246.07:40:11.95#ibcon#about to read 6, iclass 29, count 0 2006.246.07:40:11.95#ibcon#read 6, iclass 29, count 0 2006.246.07:40:11.95#ibcon#end of sib2, iclass 29, count 0 2006.246.07:40:11.95#ibcon#*after write, iclass 29, count 0 2006.246.07:40:11.95#ibcon#*before return 0, iclass 29, count 0 2006.246.07:40:11.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:11.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:40:11.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:40:11.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:40:11.95$vc4f8/vblo=5,744.99 2006.246.07:40:11.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.07:40:11.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.07:40:11.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:11.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:11.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:11.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:11.95#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:40:11.95#ibcon#first serial, iclass 31, count 0 2006.246.07:40:11.95#ibcon#enter sib2, iclass 31, count 0 2006.246.07:40:11.95#ibcon#flushed, iclass 31, count 0 2006.246.07:40:11.95#ibcon#about to write, iclass 31, count 0 2006.246.07:40:11.95#ibcon#wrote, iclass 31, count 0 2006.246.07:40:11.95#ibcon#about to read 3, iclass 31, count 0 2006.246.07:40:11.97#ibcon#read 3, iclass 31, count 0 2006.246.07:40:11.97#ibcon#about to read 4, iclass 31, count 0 2006.246.07:40:11.97#ibcon#read 4, iclass 31, count 0 2006.246.07:40:11.97#ibcon#about to read 5, iclass 31, count 0 2006.246.07:40:11.97#ibcon#read 5, iclass 31, count 0 2006.246.07:40:11.97#ibcon#about to read 6, iclass 31, count 0 2006.246.07:40:11.97#ibcon#read 6, iclass 31, count 0 2006.246.07:40:11.97#ibcon#end of sib2, iclass 31, count 0 2006.246.07:40:11.97#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:40:11.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:40:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:40:11.97#ibcon#*before write, iclass 31, count 0 2006.246.07:40:11.97#ibcon#enter sib2, iclass 31, count 0 2006.246.07:40:11.97#ibcon#flushed, iclass 31, count 0 2006.246.07:40:11.97#ibcon#about to write, iclass 31, count 0 2006.246.07:40:11.97#ibcon#wrote, iclass 31, count 0 2006.246.07:40:11.97#ibcon#about to read 3, iclass 31, count 0 2006.246.07:40:12.01#ibcon#read 3, iclass 31, count 0 2006.246.07:40:12.01#ibcon#about to read 4, iclass 31, count 0 2006.246.07:40:12.01#ibcon#read 4, iclass 31, count 0 2006.246.07:40:12.01#ibcon#about to read 5, iclass 31, count 0 2006.246.07:40:12.01#ibcon#read 5, iclass 31, count 0 2006.246.07:40:12.01#ibcon#about to read 6, iclass 31, count 0 2006.246.07:40:12.01#ibcon#read 6, iclass 31, count 0 2006.246.07:40:12.01#ibcon#end of sib2, iclass 31, count 0 2006.246.07:40:12.01#ibcon#*after write, iclass 31, count 0 2006.246.07:40:12.01#ibcon#*before return 0, iclass 31, count 0 2006.246.07:40:12.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:12.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:40:12.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:40:12.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:40:12.01$vc4f8/vb=5,3 2006.246.07:40:12.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.07:40:12.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.07:40:12.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:12.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:12.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:12.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:12.07#ibcon#enter wrdev, iclass 33, count 2 2006.246.07:40:12.07#ibcon#first serial, iclass 33, count 2 2006.246.07:40:12.07#ibcon#enter sib2, iclass 33, count 2 2006.246.07:40:12.07#ibcon#flushed, iclass 33, count 2 2006.246.07:40:12.07#ibcon#about to write, iclass 33, count 2 2006.246.07:40:12.07#ibcon#wrote, iclass 33, count 2 2006.246.07:40:12.07#ibcon#about to read 3, iclass 33, count 2 2006.246.07:40:12.09#ibcon#read 3, iclass 33, count 2 2006.246.07:40:12.09#ibcon#about to read 4, iclass 33, count 2 2006.246.07:40:12.09#ibcon#read 4, iclass 33, count 2 2006.246.07:40:12.09#ibcon#about to read 5, iclass 33, count 2 2006.246.07:40:12.09#ibcon#read 5, iclass 33, count 2 2006.246.07:40:12.09#ibcon#about to read 6, iclass 33, count 2 2006.246.07:40:12.09#ibcon#read 6, iclass 33, count 2 2006.246.07:40:12.09#ibcon#end of sib2, iclass 33, count 2 2006.246.07:40:12.09#ibcon#*mode == 0, iclass 33, count 2 2006.246.07:40:12.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.07:40:12.09#ibcon#[27=AT05-03\r\n] 2006.246.07:40:12.09#ibcon#*before write, iclass 33, count 2 2006.246.07:40:12.09#ibcon#enter sib2, iclass 33, count 2 2006.246.07:40:12.09#ibcon#flushed, iclass 33, count 2 2006.246.07:40:12.09#ibcon#about to write, iclass 33, count 2 2006.246.07:40:12.09#ibcon#wrote, iclass 33, count 2 2006.246.07:40:12.09#ibcon#about to read 3, iclass 33, count 2 2006.246.07:40:12.12#ibcon#read 3, iclass 33, count 2 2006.246.07:40:12.12#ibcon#about to read 4, iclass 33, count 2 2006.246.07:40:12.12#ibcon#read 4, iclass 33, count 2 2006.246.07:40:12.12#ibcon#about to read 5, iclass 33, count 2 2006.246.07:40:12.12#ibcon#read 5, iclass 33, count 2 2006.246.07:40:12.12#ibcon#about to read 6, iclass 33, count 2 2006.246.07:40:12.12#ibcon#read 6, iclass 33, count 2 2006.246.07:40:12.12#ibcon#end of sib2, iclass 33, count 2 2006.246.07:40:12.12#ibcon#*after write, iclass 33, count 2 2006.246.07:40:12.12#ibcon#*before return 0, iclass 33, count 2 2006.246.07:40:12.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:12.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:40:12.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.07:40:12.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:12.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:12.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:12.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:12.24#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:40:12.24#ibcon#first serial, iclass 33, count 0 2006.246.07:40:12.24#ibcon#enter sib2, iclass 33, count 0 2006.246.07:40:12.24#ibcon#flushed, iclass 33, count 0 2006.246.07:40:12.24#ibcon#about to write, iclass 33, count 0 2006.246.07:40:12.24#ibcon#wrote, iclass 33, count 0 2006.246.07:40:12.24#ibcon#about to read 3, iclass 33, count 0 2006.246.07:40:12.26#ibcon#read 3, iclass 33, count 0 2006.246.07:40:12.26#ibcon#about to read 4, iclass 33, count 0 2006.246.07:40:12.26#ibcon#read 4, iclass 33, count 0 2006.246.07:40:12.26#ibcon#about to read 5, iclass 33, count 0 2006.246.07:40:12.26#ibcon#read 5, iclass 33, count 0 2006.246.07:40:12.26#ibcon#about to read 6, iclass 33, count 0 2006.246.07:40:12.26#ibcon#read 6, iclass 33, count 0 2006.246.07:40:12.26#ibcon#end of sib2, iclass 33, count 0 2006.246.07:40:12.26#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:40:12.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:40:12.26#ibcon#[27=USB\r\n] 2006.246.07:40:12.26#ibcon#*before write, iclass 33, count 0 2006.246.07:40:12.26#ibcon#enter sib2, iclass 33, count 0 2006.246.07:40:12.26#ibcon#flushed, iclass 33, count 0 2006.246.07:40:12.26#ibcon#about to write, iclass 33, count 0 2006.246.07:40:12.26#ibcon#wrote, iclass 33, count 0 2006.246.07:40:12.26#ibcon#about to read 3, iclass 33, count 0 2006.246.07:40:12.29#ibcon#read 3, iclass 33, count 0 2006.246.07:40:12.29#ibcon#about to read 4, iclass 33, count 0 2006.246.07:40:12.29#ibcon#read 4, iclass 33, count 0 2006.246.07:40:12.29#ibcon#about to read 5, iclass 33, count 0 2006.246.07:40:12.29#ibcon#read 5, iclass 33, count 0 2006.246.07:40:12.29#ibcon#about to read 6, iclass 33, count 0 2006.246.07:40:12.29#ibcon#read 6, iclass 33, count 0 2006.246.07:40:12.29#ibcon#end of sib2, iclass 33, count 0 2006.246.07:40:12.29#ibcon#*after write, iclass 33, count 0 2006.246.07:40:12.29#ibcon#*before return 0, iclass 33, count 0 2006.246.07:40:12.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:12.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:40:12.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:40:12.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:40:12.29$vc4f8/vblo=6,752.99 2006.246.07:40:12.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.07:40:12.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.07:40:12.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:40:12.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:12.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:12.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:12.29#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:40:12.29#ibcon#first serial, iclass 35, count 0 2006.246.07:40:12.29#ibcon#enter sib2, iclass 35, count 0 2006.246.07:40:12.29#ibcon#flushed, iclass 35, count 0 2006.246.07:40:12.29#ibcon#about to write, iclass 35, count 0 2006.246.07:40:12.29#ibcon#wrote, iclass 35, count 0 2006.246.07:40:12.29#ibcon#about to read 3, iclass 35, count 0 2006.246.07:40:12.31#ibcon#read 3, iclass 35, count 0 2006.246.07:40:12.31#ibcon#about to read 4, iclass 35, count 0 2006.246.07:40:12.31#ibcon#read 4, iclass 35, count 0 2006.246.07:40:12.31#ibcon#about to read 5, iclass 35, count 0 2006.246.07:40:12.31#ibcon#read 5, iclass 35, count 0 2006.246.07:40:12.31#ibcon#about to read 6, iclass 35, count 0 2006.246.07:40:12.31#ibcon#read 6, iclass 35, count 0 2006.246.07:40:12.31#ibcon#end of sib2, iclass 35, count 0 2006.246.07:40:12.31#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:40:12.31#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:40:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:40:12.31#ibcon#*before write, iclass 35, count 0 2006.246.07:40:12.31#ibcon#enter sib2, iclass 35, count 0 2006.246.07:40:12.31#ibcon#flushed, iclass 35, count 0 2006.246.07:40:12.31#ibcon#about to write, iclass 35, count 0 2006.246.07:40:12.31#ibcon#wrote, iclass 35, count 0 2006.246.07:40:12.31#ibcon#about to read 3, iclass 35, count 0 2006.246.07:40:12.35#ibcon#read 3, iclass 35, count 0 2006.246.07:40:12.35#ibcon#about to read 4, iclass 35, count 0 2006.246.07:40:12.35#ibcon#read 4, iclass 35, count 0 2006.246.07:40:12.35#ibcon#about to read 5, iclass 35, count 0 2006.246.07:40:12.35#ibcon#read 5, iclass 35, count 0 2006.246.07:40:12.35#ibcon#about to read 6, iclass 35, count 0 2006.246.07:40:12.35#ibcon#read 6, iclass 35, count 0 2006.246.07:40:12.35#ibcon#end of sib2, iclass 35, count 0 2006.246.07:40:12.35#ibcon#*after write, iclass 35, count 0 2006.246.07:40:12.35#ibcon#*before return 0, iclass 35, count 0 2006.246.07:40:12.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:12.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:40:12.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:40:12.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:40:12.35$vc4f8/vb=6,3 2006.246.07:40:12.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.07:40:12.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.07:40:12.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:40:12.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:12.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:12.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:12.41#ibcon#enter wrdev, iclass 37, count 2 2006.246.07:40:12.41#ibcon#first serial, iclass 37, count 2 2006.246.07:40:12.41#ibcon#enter sib2, iclass 37, count 2 2006.246.07:40:12.41#ibcon#flushed, iclass 37, count 2 2006.246.07:40:12.41#ibcon#about to write, iclass 37, count 2 2006.246.07:40:12.41#ibcon#wrote, iclass 37, count 2 2006.246.07:40:12.41#ibcon#about to read 3, iclass 37, count 2 2006.246.07:40:12.43#ibcon#read 3, iclass 37, count 2 2006.246.07:40:12.43#ibcon#about to read 4, iclass 37, count 2 2006.246.07:40:12.43#ibcon#read 4, iclass 37, count 2 2006.246.07:40:12.43#ibcon#about to read 5, iclass 37, count 2 2006.246.07:40:12.43#ibcon#read 5, iclass 37, count 2 2006.246.07:40:12.43#ibcon#about to read 6, iclass 37, count 2 2006.246.07:40:12.43#ibcon#read 6, iclass 37, count 2 2006.246.07:40:12.43#ibcon#end of sib2, iclass 37, count 2 2006.246.07:40:12.43#ibcon#*mode == 0, iclass 37, count 2 2006.246.07:40:12.43#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.07:40:12.43#ibcon#[27=AT06-03\r\n] 2006.246.07:40:12.43#ibcon#*before write, iclass 37, count 2 2006.246.07:40:12.43#ibcon#enter sib2, iclass 37, count 2 2006.246.07:40:12.43#ibcon#flushed, iclass 37, count 2 2006.246.07:40:12.43#ibcon#about to write, iclass 37, count 2 2006.246.07:40:12.43#ibcon#wrote, iclass 37, count 2 2006.246.07:40:12.43#ibcon#about to read 3, iclass 37, count 2 2006.246.07:40:12.46#ibcon#read 3, iclass 37, count 2 2006.246.07:40:12.46#ibcon#about to read 4, iclass 37, count 2 2006.246.07:40:12.46#ibcon#read 4, iclass 37, count 2 2006.246.07:40:12.46#ibcon#about to read 5, iclass 37, count 2 2006.246.07:40:12.46#ibcon#read 5, iclass 37, count 2 2006.246.07:40:12.46#ibcon#about to read 6, iclass 37, count 2 2006.246.07:40:12.46#ibcon#read 6, iclass 37, count 2 2006.246.07:40:12.46#ibcon#end of sib2, iclass 37, count 2 2006.246.07:40:12.46#ibcon#*after write, iclass 37, count 2 2006.246.07:40:12.46#ibcon#*before return 0, iclass 37, count 2 2006.246.07:40:12.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:12.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:40:12.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.07:40:12.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:40:12.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:12.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:12.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:12.58#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:40:12.58#ibcon#first serial, iclass 37, count 0 2006.246.07:40:12.58#ibcon#enter sib2, iclass 37, count 0 2006.246.07:40:12.58#ibcon#flushed, iclass 37, count 0 2006.246.07:40:12.58#ibcon#about to write, iclass 37, count 0 2006.246.07:40:12.58#ibcon#wrote, iclass 37, count 0 2006.246.07:40:12.58#ibcon#about to read 3, iclass 37, count 0 2006.246.07:40:12.60#ibcon#read 3, iclass 37, count 0 2006.246.07:40:12.60#ibcon#about to read 4, iclass 37, count 0 2006.246.07:40:12.60#ibcon#read 4, iclass 37, count 0 2006.246.07:40:12.60#ibcon#about to read 5, iclass 37, count 0 2006.246.07:40:12.60#ibcon#read 5, iclass 37, count 0 2006.246.07:40:12.60#ibcon#about to read 6, iclass 37, count 0 2006.246.07:40:12.60#ibcon#read 6, iclass 37, count 0 2006.246.07:40:12.60#ibcon#end of sib2, iclass 37, count 0 2006.246.07:40:12.60#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:40:12.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:40:12.60#ibcon#[27=USB\r\n] 2006.246.07:40:12.60#ibcon#*before write, iclass 37, count 0 2006.246.07:40:12.60#ibcon#enter sib2, iclass 37, count 0 2006.246.07:40:12.60#ibcon#flushed, iclass 37, count 0 2006.246.07:40:12.60#ibcon#about to write, iclass 37, count 0 2006.246.07:40:12.60#ibcon#wrote, iclass 37, count 0 2006.246.07:40:12.60#ibcon#about to read 3, iclass 37, count 0 2006.246.07:40:12.63#ibcon#read 3, iclass 37, count 0 2006.246.07:40:12.63#ibcon#about to read 4, iclass 37, count 0 2006.246.07:40:12.63#ibcon#read 4, iclass 37, count 0 2006.246.07:40:12.63#ibcon#about to read 5, iclass 37, count 0 2006.246.07:40:12.63#ibcon#read 5, iclass 37, count 0 2006.246.07:40:12.63#ibcon#about to read 6, iclass 37, count 0 2006.246.07:40:12.63#ibcon#read 6, iclass 37, count 0 2006.246.07:40:12.63#ibcon#end of sib2, iclass 37, count 0 2006.246.07:40:12.63#ibcon#*after write, iclass 37, count 0 2006.246.07:40:12.63#ibcon#*before return 0, iclass 37, count 0 2006.246.07:40:12.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:12.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:40:12.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:40:12.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:40:12.63$vc4f8/vabw=wide 2006.246.07:40:12.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:40:12.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:40:12.63#ibcon#ireg 8 cls_cnt 0 2006.246.07:40:12.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:12.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:12.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:12.63#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:40:12.63#ibcon#first serial, iclass 39, count 0 2006.246.07:40:12.63#ibcon#enter sib2, iclass 39, count 0 2006.246.07:40:12.63#ibcon#flushed, iclass 39, count 0 2006.246.07:40:12.63#ibcon#about to write, iclass 39, count 0 2006.246.07:40:12.63#ibcon#wrote, iclass 39, count 0 2006.246.07:40:12.63#ibcon#about to read 3, iclass 39, count 0 2006.246.07:40:12.65#ibcon#read 3, iclass 39, count 0 2006.246.07:40:12.65#ibcon#about to read 4, iclass 39, count 0 2006.246.07:40:12.65#ibcon#read 4, iclass 39, count 0 2006.246.07:40:12.65#ibcon#about to read 5, iclass 39, count 0 2006.246.07:40:12.65#ibcon#read 5, iclass 39, count 0 2006.246.07:40:12.65#ibcon#about to read 6, iclass 39, count 0 2006.246.07:40:12.65#ibcon#read 6, iclass 39, count 0 2006.246.07:40:12.65#ibcon#end of sib2, iclass 39, count 0 2006.246.07:40:12.65#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:40:12.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:40:12.65#ibcon#[25=BW32\r\n] 2006.246.07:40:12.65#ibcon#*before write, iclass 39, count 0 2006.246.07:40:12.65#ibcon#enter sib2, iclass 39, count 0 2006.246.07:40:12.65#ibcon#flushed, iclass 39, count 0 2006.246.07:40:12.65#ibcon#about to write, iclass 39, count 0 2006.246.07:40:12.65#ibcon#wrote, iclass 39, count 0 2006.246.07:40:12.65#ibcon#about to read 3, iclass 39, count 0 2006.246.07:40:12.68#ibcon#read 3, iclass 39, count 0 2006.246.07:40:12.68#ibcon#about to read 4, iclass 39, count 0 2006.246.07:40:12.68#ibcon#read 4, iclass 39, count 0 2006.246.07:40:12.68#ibcon#about to read 5, iclass 39, count 0 2006.246.07:40:12.68#ibcon#read 5, iclass 39, count 0 2006.246.07:40:12.68#ibcon#about to read 6, iclass 39, count 0 2006.246.07:40:12.68#ibcon#read 6, iclass 39, count 0 2006.246.07:40:12.68#ibcon#end of sib2, iclass 39, count 0 2006.246.07:40:12.68#ibcon#*after write, iclass 39, count 0 2006.246.07:40:12.68#ibcon#*before return 0, iclass 39, count 0 2006.246.07:40:12.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:12.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:40:12.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:40:12.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:40:12.68$vc4f8/vbbw=wide 2006.246.07:40:12.68#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.07:40:12.68#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.07:40:12.68#ibcon#ireg 8 cls_cnt 0 2006.246.07:40:12.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:40:12.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:40:12.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:40:12.75#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:40:12.75#ibcon#first serial, iclass 3, count 0 2006.246.07:40:12.75#ibcon#enter sib2, iclass 3, count 0 2006.246.07:40:12.75#ibcon#flushed, iclass 3, count 0 2006.246.07:40:12.75#ibcon#about to write, iclass 3, count 0 2006.246.07:40:12.75#ibcon#wrote, iclass 3, count 0 2006.246.07:40:12.75#ibcon#about to read 3, iclass 3, count 0 2006.246.07:40:12.77#ibcon#read 3, iclass 3, count 0 2006.246.07:40:12.77#ibcon#about to read 4, iclass 3, count 0 2006.246.07:40:12.77#ibcon#read 4, iclass 3, count 0 2006.246.07:40:12.77#ibcon#about to read 5, iclass 3, count 0 2006.246.07:40:12.77#ibcon#read 5, iclass 3, count 0 2006.246.07:40:12.77#ibcon#about to read 6, iclass 3, count 0 2006.246.07:40:12.77#ibcon#read 6, iclass 3, count 0 2006.246.07:40:12.77#ibcon#end of sib2, iclass 3, count 0 2006.246.07:40:12.77#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:40:12.77#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:40:12.77#ibcon#[27=BW32\r\n] 2006.246.07:40:12.77#ibcon#*before write, iclass 3, count 0 2006.246.07:40:12.77#ibcon#enter sib2, iclass 3, count 0 2006.246.07:40:12.77#ibcon#flushed, iclass 3, count 0 2006.246.07:40:12.77#ibcon#about to write, iclass 3, count 0 2006.246.07:40:12.77#ibcon#wrote, iclass 3, count 0 2006.246.07:40:12.77#ibcon#about to read 3, iclass 3, count 0 2006.246.07:40:12.80#ibcon#read 3, iclass 3, count 0 2006.246.07:40:12.80#ibcon#about to read 4, iclass 3, count 0 2006.246.07:40:12.80#ibcon#read 4, iclass 3, count 0 2006.246.07:40:12.80#ibcon#about to read 5, iclass 3, count 0 2006.246.07:40:12.80#ibcon#read 5, iclass 3, count 0 2006.246.07:40:12.80#ibcon#about to read 6, iclass 3, count 0 2006.246.07:40:12.80#ibcon#read 6, iclass 3, count 0 2006.246.07:40:12.80#ibcon#end of sib2, iclass 3, count 0 2006.246.07:40:12.80#ibcon#*after write, iclass 3, count 0 2006.246.07:40:12.80#ibcon#*before return 0, iclass 3, count 0 2006.246.07:40:12.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:40:12.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:40:12.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:40:12.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:40:12.80$4f8m12a/ifd4f 2006.246.07:40:12.80$ifd4f/lo= 2006.246.07:40:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:40:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:40:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:40:12.81$ifd4f/patch= 2006.246.07:40:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:40:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:40:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:40:12.81$4f8m12a/"form=m,16.000,1:2 2006.246.07:40:12.81$4f8m12a/"tpicd 2006.246.07:40:12.81$4f8m12a/echo=off 2006.246.07:40:12.81$4f8m12a/xlog=off 2006.246.07:40:12.81:!2006.246.07:40:50 2006.246.07:40:33.14#trakl#Source acquired 2006.246.07:40:34.14#flagr#flagr/antenna,acquired 2006.246.07:40:50.01:preob 2006.246.07:40:51.14/onsource/TRACKING 2006.246.07:40:51.14:!2006.246.07:41:00 2006.246.07:41:00.00:data_valid=on 2006.246.07:41:00.00:midob 2006.246.07:41:00.14/onsource/TRACKING 2006.246.07:41:00.15/wx/26.75,1005.6,73 2006.246.07:41:00.33/cable/+6.4145E-03 2006.246.07:41:01.42/va/01,08,usb,yes,31,32 2006.246.07:41:01.42/va/02,07,usb,yes,30,32 2006.246.07:41:01.42/va/03,06,usb,yes,32,33 2006.246.07:41:01.42/va/04,07,usb,yes,31,34 2006.246.07:41:01.42/va/05,07,usb,yes,34,36 2006.246.07:41:01.42/va/06,07,usb,yes,29,29 2006.246.07:41:01.42/va/07,07,usb,yes,29,29 2006.246.07:41:01.42/va/08,08,usb,yes,26,25 2006.246.07:41:01.65/valo/01,532.99,yes,locked 2006.246.07:41:01.65/valo/02,572.99,yes,locked 2006.246.07:41:01.65/valo/03,672.99,yes,locked 2006.246.07:41:01.65/valo/04,832.99,yes,locked 2006.246.07:41:01.65/valo/05,652.99,yes,locked 2006.246.07:41:01.65/valo/06,772.99,yes,locked 2006.246.07:41:01.65/valo/07,832.99,yes,locked 2006.246.07:41:01.65/valo/08,852.99,yes,locked 2006.246.07:41:02.74/vb/01,04,usb,yes,30,29 2006.246.07:41:02.74/vb/02,04,usb,yes,32,33 2006.246.07:41:02.74/vb/03,04,usb,yes,28,32 2006.246.07:41:02.74/vb/04,04,usb,yes,29,29 2006.246.07:41:02.74/vb/05,03,usb,yes,34,39 2006.246.07:41:02.74/vb/06,03,usb,yes,35,39 2006.246.07:41:02.74/vb/07,04,usb,yes,31,30 2006.246.07:41:02.74/vb/08,03,usb,yes,35,39 2006.246.07:41:02.98/vblo/01,632.99,yes,locked 2006.246.07:41:02.98/vblo/02,640.99,yes,locked 2006.246.07:41:02.98/vblo/03,656.99,yes,locked 2006.246.07:41:02.98/vblo/04,712.99,yes,locked 2006.246.07:41:02.98/vblo/05,744.99,yes,locked 2006.246.07:41:02.98/vblo/06,752.99,yes,locked 2006.246.07:41:02.98/vblo/07,734.99,yes,locked 2006.246.07:41:02.98/vblo/08,744.99,yes,locked 2006.246.07:41:03.13/vabw/8 2006.246.07:41:03.28/vbbw/8 2006.246.07:41:03.37/xfe/off,on,13.2 2006.246.07:41:03.74/ifatt/23,28,28,28 2006.246.07:41:04.07/fmout-gps/S +4.34E-07 2006.246.07:41:04.12:!2006.246.07:42:00 2006.246.07:42:00.00:data_valid=off 2006.246.07:42:00.01:postob 2006.246.07:42:00.14/cable/+6.4134E-03 2006.246.07:42:00.15/wx/26.74,1005.6,73 2006.246.07:42:01.07/fmout-gps/S +4.34E-07 2006.246.07:42:01.08:scan_name=246-0742,k06246,60 2006.246.07:42:01.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.246.07:42:02.14#flagr#flagr/antenna,new-source 2006.246.07:42:02.15:checkk5 2006.246.07:42:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:42:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:42:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:42:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:42:04.01/chk_obsdata//k5ts1/T2460741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:42:04.38/chk_obsdata//k5ts2/T2460741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:42:04.74/chk_obsdata//k5ts3/T2460741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:42:05.10/chk_obsdata//k5ts4/T2460741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:42:05.79/k5log//k5ts1_log_newline 2006.246.07:42:06.49/k5log//k5ts2_log_newline 2006.246.07:42:07.17/k5log//k5ts3_log_newline 2006.246.07:42:07.86/k5log//k5ts4_log_newline 2006.246.07:42:07.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:42:07.88:4f8m12a=1 2006.246.07:42:07.88$4f8m12a/echo=on 2006.246.07:42:07.88$4f8m12a/pcalon 2006.246.07:42:07.88$pcalon/"no phase cal control is implemented here 2006.246.07:42:07.88$4f8m12a/"tpicd=stop 2006.246.07:42:07.88$4f8m12a/vc4f8 2006.246.07:42:07.88$vc4f8/valo=1,532.99 2006.246.07:42:07.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:42:07.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:42:07.89#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:07.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:42:07.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:42:07.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:42:07.89#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:42:07.89#ibcon#first serial, iclass 17, count 0 2006.246.07:42:07.89#ibcon#enter sib2, iclass 17, count 0 2006.246.07:42:07.89#ibcon#flushed, iclass 17, count 0 2006.246.07:42:07.89#ibcon#about to write, iclass 17, count 0 2006.246.07:42:07.89#ibcon#wrote, iclass 17, count 0 2006.246.07:42:07.89#ibcon#about to read 3, iclass 17, count 0 2006.246.07:42:07.93#ibcon#read 3, iclass 17, count 0 2006.246.07:42:07.93#ibcon#about to read 4, iclass 17, count 0 2006.246.07:42:07.93#ibcon#read 4, iclass 17, count 0 2006.246.07:42:07.93#ibcon#about to read 5, iclass 17, count 0 2006.246.07:42:07.93#ibcon#read 5, iclass 17, count 0 2006.246.07:42:07.93#ibcon#about to read 6, iclass 17, count 0 2006.246.07:42:07.93#ibcon#read 6, iclass 17, count 0 2006.246.07:42:07.93#ibcon#end of sib2, iclass 17, count 0 2006.246.07:42:07.93#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:42:07.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:42:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:42:07.93#ibcon#*before write, iclass 17, count 0 2006.246.07:42:07.93#ibcon#enter sib2, iclass 17, count 0 2006.246.07:42:07.93#ibcon#flushed, iclass 17, count 0 2006.246.07:42:07.93#ibcon#about to write, iclass 17, count 0 2006.246.07:42:07.93#ibcon#wrote, iclass 17, count 0 2006.246.07:42:07.93#ibcon#about to read 3, iclass 17, count 0 2006.246.07:42:07.94#abcon#{5=INTERFACE CLEAR} 2006.246.07:42:07.97#ibcon#read 3, iclass 17, count 0 2006.246.07:42:07.97#ibcon#about to read 4, iclass 17, count 0 2006.246.07:42:07.97#ibcon#read 4, iclass 17, count 0 2006.246.07:42:07.97#ibcon#about to read 5, iclass 17, count 0 2006.246.07:42:07.97#ibcon#read 5, iclass 17, count 0 2006.246.07:42:07.97#ibcon#about to read 6, iclass 17, count 0 2006.246.07:42:07.97#ibcon#read 6, iclass 17, count 0 2006.246.07:42:07.97#ibcon#end of sib2, iclass 17, count 0 2006.246.07:42:07.97#ibcon#*after write, iclass 17, count 0 2006.246.07:42:07.97#ibcon#*before return 0, iclass 17, count 0 2006.246.07:42:07.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:42:07.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:42:07.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:42:07.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:42:07.97$vc4f8/va=1,8 2006.246.07:42:07.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:42:07.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:42:07.97#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:07.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:42:07.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:42:07.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:42:07.97#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:42:07.97#ibcon#first serial, iclass 21, count 2 2006.246.07:42:07.97#ibcon#enter sib2, iclass 21, count 2 2006.246.07:42:07.97#ibcon#flushed, iclass 21, count 2 2006.246.07:42:07.97#ibcon#about to write, iclass 21, count 2 2006.246.07:42:07.97#ibcon#wrote, iclass 21, count 2 2006.246.07:42:07.97#ibcon#about to read 3, iclass 21, count 2 2006.246.07:42:07.99#ibcon#read 3, iclass 21, count 2 2006.246.07:42:07.99#ibcon#about to read 4, iclass 21, count 2 2006.246.07:42:07.99#ibcon#read 4, iclass 21, count 2 2006.246.07:42:07.99#ibcon#about to read 5, iclass 21, count 2 2006.246.07:42:07.99#ibcon#read 5, iclass 21, count 2 2006.246.07:42:07.99#ibcon#about to read 6, iclass 21, count 2 2006.246.07:42:07.99#ibcon#read 6, iclass 21, count 2 2006.246.07:42:07.99#ibcon#end of sib2, iclass 21, count 2 2006.246.07:42:07.99#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:42:07.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:42:07.99#ibcon#[25=AT01-08\r\n] 2006.246.07:42:07.99#ibcon#*before write, iclass 21, count 2 2006.246.07:42:07.99#ibcon#enter sib2, iclass 21, count 2 2006.246.07:42:07.99#ibcon#flushed, iclass 21, count 2 2006.246.07:42:07.99#ibcon#about to write, iclass 21, count 2 2006.246.07:42:07.99#ibcon#wrote, iclass 21, count 2 2006.246.07:42:07.99#ibcon#about to read 3, iclass 21, count 2 2006.246.07:42:08.01#abcon#[5=S1D000X0/0*\r\n] 2006.246.07:42:08.02#ibcon#read 3, iclass 21, count 2 2006.246.07:42:08.02#ibcon#about to read 4, iclass 21, count 2 2006.246.07:42:08.02#ibcon#read 4, iclass 21, count 2 2006.246.07:42:08.02#ibcon#about to read 5, iclass 21, count 2 2006.246.07:42:08.02#ibcon#read 5, iclass 21, count 2 2006.246.07:42:08.02#ibcon#about to read 6, iclass 21, count 2 2006.246.07:42:08.02#ibcon#read 6, iclass 21, count 2 2006.246.07:42:08.02#ibcon#end of sib2, iclass 21, count 2 2006.246.07:42:08.02#ibcon#*after write, iclass 21, count 2 2006.246.07:42:08.02#ibcon#*before return 0, iclass 21, count 2 2006.246.07:42:08.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:42:08.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:42:08.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:42:08.02#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:08.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:42:08.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:42:08.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:42:08.14#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:42:08.14#ibcon#first serial, iclass 21, count 0 2006.246.07:42:08.14#ibcon#enter sib2, iclass 21, count 0 2006.246.07:42:08.14#ibcon#flushed, iclass 21, count 0 2006.246.07:42:08.14#ibcon#about to write, iclass 21, count 0 2006.246.07:42:08.14#ibcon#wrote, iclass 21, count 0 2006.246.07:42:08.14#ibcon#about to read 3, iclass 21, count 0 2006.246.07:42:08.16#ibcon#read 3, iclass 21, count 0 2006.246.07:42:08.16#ibcon#about to read 4, iclass 21, count 0 2006.246.07:42:08.16#ibcon#read 4, iclass 21, count 0 2006.246.07:42:08.16#ibcon#about to read 5, iclass 21, count 0 2006.246.07:42:08.16#ibcon#read 5, iclass 21, count 0 2006.246.07:42:08.16#ibcon#about to read 6, iclass 21, count 0 2006.246.07:42:08.16#ibcon#read 6, iclass 21, count 0 2006.246.07:42:08.16#ibcon#end of sib2, iclass 21, count 0 2006.246.07:42:08.16#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:42:08.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:42:08.16#ibcon#[25=USB\r\n] 2006.246.07:42:08.16#ibcon#*before write, iclass 21, count 0 2006.246.07:42:08.16#ibcon#enter sib2, iclass 21, count 0 2006.246.07:42:08.16#ibcon#flushed, iclass 21, count 0 2006.246.07:42:08.16#ibcon#about to write, iclass 21, count 0 2006.246.07:42:08.16#ibcon#wrote, iclass 21, count 0 2006.246.07:42:08.16#ibcon#about to read 3, iclass 21, count 0 2006.246.07:42:08.19#ibcon#read 3, iclass 21, count 0 2006.246.07:42:08.19#ibcon#about to read 4, iclass 21, count 0 2006.246.07:42:08.19#ibcon#read 4, iclass 21, count 0 2006.246.07:42:08.19#ibcon#about to read 5, iclass 21, count 0 2006.246.07:42:08.19#ibcon#read 5, iclass 21, count 0 2006.246.07:42:08.19#ibcon#about to read 6, iclass 21, count 0 2006.246.07:42:08.19#ibcon#read 6, iclass 21, count 0 2006.246.07:42:08.19#ibcon#end of sib2, iclass 21, count 0 2006.246.07:42:08.19#ibcon#*after write, iclass 21, count 0 2006.246.07:42:08.19#ibcon#*before return 0, iclass 21, count 0 2006.246.07:42:08.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:42:08.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:42:08.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:42:08.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:42:08.19$vc4f8/valo=2,572.99 2006.246.07:42:08.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.07:42:08.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.07:42:08.19#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:08.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:08.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:08.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:08.19#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:42:08.19#ibcon#first serial, iclass 24, count 0 2006.246.07:42:08.19#ibcon#enter sib2, iclass 24, count 0 2006.246.07:42:08.19#ibcon#flushed, iclass 24, count 0 2006.246.07:42:08.19#ibcon#about to write, iclass 24, count 0 2006.246.07:42:08.19#ibcon#wrote, iclass 24, count 0 2006.246.07:42:08.19#ibcon#about to read 3, iclass 24, count 0 2006.246.07:42:08.22#ibcon#read 3, iclass 24, count 0 2006.246.07:42:08.22#ibcon#about to read 4, iclass 24, count 0 2006.246.07:42:08.22#ibcon#read 4, iclass 24, count 0 2006.246.07:42:08.22#ibcon#about to read 5, iclass 24, count 0 2006.246.07:42:08.22#ibcon#read 5, iclass 24, count 0 2006.246.07:42:08.22#ibcon#about to read 6, iclass 24, count 0 2006.246.07:42:08.22#ibcon#read 6, iclass 24, count 0 2006.246.07:42:08.22#ibcon#end of sib2, iclass 24, count 0 2006.246.07:42:08.22#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:42:08.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:42:08.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:42:08.22#ibcon#*before write, iclass 24, count 0 2006.246.07:42:08.22#ibcon#enter sib2, iclass 24, count 0 2006.246.07:42:08.22#ibcon#flushed, iclass 24, count 0 2006.246.07:42:08.22#ibcon#about to write, iclass 24, count 0 2006.246.07:42:08.22#ibcon#wrote, iclass 24, count 0 2006.246.07:42:08.22#ibcon#about to read 3, iclass 24, count 0 2006.246.07:42:08.26#ibcon#read 3, iclass 24, count 0 2006.246.07:42:08.26#ibcon#about to read 4, iclass 24, count 0 2006.246.07:42:08.26#ibcon#read 4, iclass 24, count 0 2006.246.07:42:08.26#ibcon#about to read 5, iclass 24, count 0 2006.246.07:42:08.26#ibcon#read 5, iclass 24, count 0 2006.246.07:42:08.26#ibcon#about to read 6, iclass 24, count 0 2006.246.07:42:08.26#ibcon#read 6, iclass 24, count 0 2006.246.07:42:08.26#ibcon#end of sib2, iclass 24, count 0 2006.246.07:42:08.26#ibcon#*after write, iclass 24, count 0 2006.246.07:42:08.26#ibcon#*before return 0, iclass 24, count 0 2006.246.07:42:08.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:08.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:08.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:42:08.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:42:08.26$vc4f8/va=2,7 2006.246.07:42:08.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.07:42:08.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.07:42:08.26#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:08.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:08.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:08.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:08.32#ibcon#enter wrdev, iclass 26, count 2 2006.246.07:42:08.32#ibcon#first serial, iclass 26, count 2 2006.246.07:42:08.32#ibcon#enter sib2, iclass 26, count 2 2006.246.07:42:08.32#ibcon#flushed, iclass 26, count 2 2006.246.07:42:08.32#ibcon#about to write, iclass 26, count 2 2006.246.07:42:08.32#ibcon#wrote, iclass 26, count 2 2006.246.07:42:08.32#ibcon#about to read 3, iclass 26, count 2 2006.246.07:42:08.33#ibcon#read 3, iclass 26, count 2 2006.246.07:42:08.33#ibcon#about to read 4, iclass 26, count 2 2006.246.07:42:08.33#ibcon#read 4, iclass 26, count 2 2006.246.07:42:08.33#ibcon#about to read 5, iclass 26, count 2 2006.246.07:42:08.33#ibcon#read 5, iclass 26, count 2 2006.246.07:42:08.33#ibcon#about to read 6, iclass 26, count 2 2006.246.07:42:08.33#ibcon#read 6, iclass 26, count 2 2006.246.07:42:08.33#ibcon#end of sib2, iclass 26, count 2 2006.246.07:42:08.33#ibcon#*mode == 0, iclass 26, count 2 2006.246.07:42:08.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.07:42:08.33#ibcon#[25=AT02-07\r\n] 2006.246.07:42:08.33#ibcon#*before write, iclass 26, count 2 2006.246.07:42:08.33#ibcon#enter sib2, iclass 26, count 2 2006.246.07:42:08.33#ibcon#flushed, iclass 26, count 2 2006.246.07:42:08.33#ibcon#about to write, iclass 26, count 2 2006.246.07:42:08.33#ibcon#wrote, iclass 26, count 2 2006.246.07:42:08.33#ibcon#about to read 3, iclass 26, count 2 2006.246.07:42:08.36#ibcon#read 3, iclass 26, count 2 2006.246.07:42:08.36#ibcon#about to read 4, iclass 26, count 2 2006.246.07:42:08.36#ibcon#read 4, iclass 26, count 2 2006.246.07:42:08.36#ibcon#about to read 5, iclass 26, count 2 2006.246.07:42:08.36#ibcon#read 5, iclass 26, count 2 2006.246.07:42:08.36#ibcon#about to read 6, iclass 26, count 2 2006.246.07:42:08.36#ibcon#read 6, iclass 26, count 2 2006.246.07:42:08.36#ibcon#end of sib2, iclass 26, count 2 2006.246.07:42:08.36#ibcon#*after write, iclass 26, count 2 2006.246.07:42:08.36#ibcon#*before return 0, iclass 26, count 2 2006.246.07:42:08.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:08.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:08.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.07:42:08.36#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:08.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:08.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:08.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:08.48#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:42:08.48#ibcon#first serial, iclass 26, count 0 2006.246.07:42:08.48#ibcon#enter sib2, iclass 26, count 0 2006.246.07:42:08.48#ibcon#flushed, iclass 26, count 0 2006.246.07:42:08.48#ibcon#about to write, iclass 26, count 0 2006.246.07:42:08.48#ibcon#wrote, iclass 26, count 0 2006.246.07:42:08.48#ibcon#about to read 3, iclass 26, count 0 2006.246.07:42:08.50#ibcon#read 3, iclass 26, count 0 2006.246.07:42:08.50#ibcon#about to read 4, iclass 26, count 0 2006.246.07:42:08.50#ibcon#read 4, iclass 26, count 0 2006.246.07:42:08.50#ibcon#about to read 5, iclass 26, count 0 2006.246.07:42:08.50#ibcon#read 5, iclass 26, count 0 2006.246.07:42:08.50#ibcon#about to read 6, iclass 26, count 0 2006.246.07:42:08.50#ibcon#read 6, iclass 26, count 0 2006.246.07:42:08.50#ibcon#end of sib2, iclass 26, count 0 2006.246.07:42:08.50#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:42:08.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:42:08.50#ibcon#[25=USB\r\n] 2006.246.07:42:08.50#ibcon#*before write, iclass 26, count 0 2006.246.07:42:08.50#ibcon#enter sib2, iclass 26, count 0 2006.246.07:42:08.50#ibcon#flushed, iclass 26, count 0 2006.246.07:42:08.50#ibcon#about to write, iclass 26, count 0 2006.246.07:42:08.50#ibcon#wrote, iclass 26, count 0 2006.246.07:42:08.50#ibcon#about to read 3, iclass 26, count 0 2006.246.07:42:08.53#ibcon#read 3, iclass 26, count 0 2006.246.07:42:08.53#ibcon#about to read 4, iclass 26, count 0 2006.246.07:42:08.53#ibcon#read 4, iclass 26, count 0 2006.246.07:42:08.53#ibcon#about to read 5, iclass 26, count 0 2006.246.07:42:08.53#ibcon#read 5, iclass 26, count 0 2006.246.07:42:08.53#ibcon#about to read 6, iclass 26, count 0 2006.246.07:42:08.53#ibcon#read 6, iclass 26, count 0 2006.246.07:42:08.53#ibcon#end of sib2, iclass 26, count 0 2006.246.07:42:08.53#ibcon#*after write, iclass 26, count 0 2006.246.07:42:08.53#ibcon#*before return 0, iclass 26, count 0 2006.246.07:42:08.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:08.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:08.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:42:08.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:42:08.53$vc4f8/valo=3,672.99 2006.246.07:42:08.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.07:42:08.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.07:42:08.53#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:08.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:08.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:08.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:08.53#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:42:08.53#ibcon#first serial, iclass 28, count 0 2006.246.07:42:08.53#ibcon#enter sib2, iclass 28, count 0 2006.246.07:42:08.53#ibcon#flushed, iclass 28, count 0 2006.246.07:42:08.53#ibcon#about to write, iclass 28, count 0 2006.246.07:42:08.53#ibcon#wrote, iclass 28, count 0 2006.246.07:42:08.53#ibcon#about to read 3, iclass 28, count 0 2006.246.07:42:08.56#ibcon#read 3, iclass 28, count 0 2006.246.07:42:08.56#ibcon#about to read 4, iclass 28, count 0 2006.246.07:42:08.56#ibcon#read 4, iclass 28, count 0 2006.246.07:42:08.56#ibcon#about to read 5, iclass 28, count 0 2006.246.07:42:08.56#ibcon#read 5, iclass 28, count 0 2006.246.07:42:08.56#ibcon#about to read 6, iclass 28, count 0 2006.246.07:42:08.56#ibcon#read 6, iclass 28, count 0 2006.246.07:42:08.56#ibcon#end of sib2, iclass 28, count 0 2006.246.07:42:08.56#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:42:08.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:42:08.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:42:08.56#ibcon#*before write, iclass 28, count 0 2006.246.07:42:08.56#ibcon#enter sib2, iclass 28, count 0 2006.246.07:42:08.56#ibcon#flushed, iclass 28, count 0 2006.246.07:42:08.56#ibcon#about to write, iclass 28, count 0 2006.246.07:42:08.56#ibcon#wrote, iclass 28, count 0 2006.246.07:42:08.56#ibcon#about to read 3, iclass 28, count 0 2006.246.07:42:08.60#ibcon#read 3, iclass 28, count 0 2006.246.07:42:08.60#ibcon#about to read 4, iclass 28, count 0 2006.246.07:42:08.60#ibcon#read 4, iclass 28, count 0 2006.246.07:42:08.60#ibcon#about to read 5, iclass 28, count 0 2006.246.07:42:08.60#ibcon#read 5, iclass 28, count 0 2006.246.07:42:08.60#ibcon#about to read 6, iclass 28, count 0 2006.246.07:42:08.60#ibcon#read 6, iclass 28, count 0 2006.246.07:42:08.60#ibcon#end of sib2, iclass 28, count 0 2006.246.07:42:08.60#ibcon#*after write, iclass 28, count 0 2006.246.07:42:08.60#ibcon#*before return 0, iclass 28, count 0 2006.246.07:42:08.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:08.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:08.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:42:08.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:42:08.60$vc4f8/va=3,6 2006.246.07:42:08.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.07:42:08.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.07:42:08.60#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:08.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:08.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:08.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:08.66#ibcon#enter wrdev, iclass 30, count 2 2006.246.07:42:08.66#ibcon#first serial, iclass 30, count 2 2006.246.07:42:08.66#ibcon#enter sib2, iclass 30, count 2 2006.246.07:42:08.66#ibcon#flushed, iclass 30, count 2 2006.246.07:42:08.66#ibcon#about to write, iclass 30, count 2 2006.246.07:42:08.66#ibcon#wrote, iclass 30, count 2 2006.246.07:42:08.66#ibcon#about to read 3, iclass 30, count 2 2006.246.07:42:08.67#ibcon#read 3, iclass 30, count 2 2006.246.07:42:08.67#ibcon#about to read 4, iclass 30, count 2 2006.246.07:42:08.67#ibcon#read 4, iclass 30, count 2 2006.246.07:42:08.67#ibcon#about to read 5, iclass 30, count 2 2006.246.07:42:08.67#ibcon#read 5, iclass 30, count 2 2006.246.07:42:08.67#ibcon#about to read 6, iclass 30, count 2 2006.246.07:42:08.67#ibcon#read 6, iclass 30, count 2 2006.246.07:42:08.67#ibcon#end of sib2, iclass 30, count 2 2006.246.07:42:08.67#ibcon#*mode == 0, iclass 30, count 2 2006.246.07:42:08.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.07:42:08.67#ibcon#[25=AT03-06\r\n] 2006.246.07:42:08.67#ibcon#*before write, iclass 30, count 2 2006.246.07:42:08.67#ibcon#enter sib2, iclass 30, count 2 2006.246.07:42:08.67#ibcon#flushed, iclass 30, count 2 2006.246.07:42:08.67#ibcon#about to write, iclass 30, count 2 2006.246.07:42:08.67#ibcon#wrote, iclass 30, count 2 2006.246.07:42:08.67#ibcon#about to read 3, iclass 30, count 2 2006.246.07:42:08.70#ibcon#read 3, iclass 30, count 2 2006.246.07:42:08.70#ibcon#about to read 4, iclass 30, count 2 2006.246.07:42:08.70#ibcon#read 4, iclass 30, count 2 2006.246.07:42:08.70#ibcon#about to read 5, iclass 30, count 2 2006.246.07:42:08.70#ibcon#read 5, iclass 30, count 2 2006.246.07:42:08.70#ibcon#about to read 6, iclass 30, count 2 2006.246.07:42:08.70#ibcon#read 6, iclass 30, count 2 2006.246.07:42:08.70#ibcon#end of sib2, iclass 30, count 2 2006.246.07:42:08.70#ibcon#*after write, iclass 30, count 2 2006.246.07:42:08.70#ibcon#*before return 0, iclass 30, count 2 2006.246.07:42:08.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:08.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:08.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.07:42:08.70#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:08.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:08.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:08.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:08.82#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:42:08.82#ibcon#first serial, iclass 30, count 0 2006.246.07:42:08.82#ibcon#enter sib2, iclass 30, count 0 2006.246.07:42:08.82#ibcon#flushed, iclass 30, count 0 2006.246.07:42:08.82#ibcon#about to write, iclass 30, count 0 2006.246.07:42:08.82#ibcon#wrote, iclass 30, count 0 2006.246.07:42:08.82#ibcon#about to read 3, iclass 30, count 0 2006.246.07:42:08.84#ibcon#read 3, iclass 30, count 0 2006.246.07:42:08.84#ibcon#about to read 4, iclass 30, count 0 2006.246.07:42:08.84#ibcon#read 4, iclass 30, count 0 2006.246.07:42:08.84#ibcon#about to read 5, iclass 30, count 0 2006.246.07:42:08.84#ibcon#read 5, iclass 30, count 0 2006.246.07:42:08.84#ibcon#about to read 6, iclass 30, count 0 2006.246.07:42:08.84#ibcon#read 6, iclass 30, count 0 2006.246.07:42:08.84#ibcon#end of sib2, iclass 30, count 0 2006.246.07:42:08.84#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:42:08.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:42:08.84#ibcon#[25=USB\r\n] 2006.246.07:42:08.84#ibcon#*before write, iclass 30, count 0 2006.246.07:42:08.84#ibcon#enter sib2, iclass 30, count 0 2006.246.07:42:08.84#ibcon#flushed, iclass 30, count 0 2006.246.07:42:08.84#ibcon#about to write, iclass 30, count 0 2006.246.07:42:08.84#ibcon#wrote, iclass 30, count 0 2006.246.07:42:08.84#ibcon#about to read 3, iclass 30, count 0 2006.246.07:42:08.87#ibcon#read 3, iclass 30, count 0 2006.246.07:42:08.87#ibcon#about to read 4, iclass 30, count 0 2006.246.07:42:08.87#ibcon#read 4, iclass 30, count 0 2006.246.07:42:08.87#ibcon#about to read 5, iclass 30, count 0 2006.246.07:42:08.87#ibcon#read 5, iclass 30, count 0 2006.246.07:42:08.87#ibcon#about to read 6, iclass 30, count 0 2006.246.07:42:08.87#ibcon#read 6, iclass 30, count 0 2006.246.07:42:08.87#ibcon#end of sib2, iclass 30, count 0 2006.246.07:42:08.87#ibcon#*after write, iclass 30, count 0 2006.246.07:42:08.87#ibcon#*before return 0, iclass 30, count 0 2006.246.07:42:08.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:08.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:08.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:42:08.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:42:08.87$vc4f8/valo=4,832.99 2006.246.07:42:08.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.07:42:08.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.07:42:08.87#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:08.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:08.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:08.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:08.87#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:42:08.87#ibcon#first serial, iclass 32, count 0 2006.246.07:42:08.87#ibcon#enter sib2, iclass 32, count 0 2006.246.07:42:08.87#ibcon#flushed, iclass 32, count 0 2006.246.07:42:08.87#ibcon#about to write, iclass 32, count 0 2006.246.07:42:08.87#ibcon#wrote, iclass 32, count 0 2006.246.07:42:08.87#ibcon#about to read 3, iclass 32, count 0 2006.246.07:42:08.89#ibcon#read 3, iclass 32, count 0 2006.246.07:42:08.89#ibcon#about to read 4, iclass 32, count 0 2006.246.07:42:08.89#ibcon#read 4, iclass 32, count 0 2006.246.07:42:08.89#ibcon#about to read 5, iclass 32, count 0 2006.246.07:42:08.89#ibcon#read 5, iclass 32, count 0 2006.246.07:42:08.89#ibcon#about to read 6, iclass 32, count 0 2006.246.07:42:08.89#ibcon#read 6, iclass 32, count 0 2006.246.07:42:08.89#ibcon#end of sib2, iclass 32, count 0 2006.246.07:42:08.89#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:42:08.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:42:08.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:42:08.89#ibcon#*before write, iclass 32, count 0 2006.246.07:42:08.89#ibcon#enter sib2, iclass 32, count 0 2006.246.07:42:08.89#ibcon#flushed, iclass 32, count 0 2006.246.07:42:08.89#ibcon#about to write, iclass 32, count 0 2006.246.07:42:08.89#ibcon#wrote, iclass 32, count 0 2006.246.07:42:08.89#ibcon#about to read 3, iclass 32, count 0 2006.246.07:42:08.93#ibcon#read 3, iclass 32, count 0 2006.246.07:42:08.93#ibcon#about to read 4, iclass 32, count 0 2006.246.07:42:08.93#ibcon#read 4, iclass 32, count 0 2006.246.07:42:08.93#ibcon#about to read 5, iclass 32, count 0 2006.246.07:42:08.93#ibcon#read 5, iclass 32, count 0 2006.246.07:42:08.93#ibcon#about to read 6, iclass 32, count 0 2006.246.07:42:08.93#ibcon#read 6, iclass 32, count 0 2006.246.07:42:08.93#ibcon#end of sib2, iclass 32, count 0 2006.246.07:42:08.93#ibcon#*after write, iclass 32, count 0 2006.246.07:42:08.93#ibcon#*before return 0, iclass 32, count 0 2006.246.07:42:08.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:08.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:08.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:42:08.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:42:08.93$vc4f8/va=4,7 2006.246.07:42:08.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.07:42:08.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.07:42:08.93#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:08.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:08.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:08.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:08.99#ibcon#enter wrdev, iclass 34, count 2 2006.246.07:42:08.99#ibcon#first serial, iclass 34, count 2 2006.246.07:42:08.99#ibcon#enter sib2, iclass 34, count 2 2006.246.07:42:08.99#ibcon#flushed, iclass 34, count 2 2006.246.07:42:08.99#ibcon#about to write, iclass 34, count 2 2006.246.07:42:08.99#ibcon#wrote, iclass 34, count 2 2006.246.07:42:08.99#ibcon#about to read 3, iclass 34, count 2 2006.246.07:42:09.01#ibcon#read 3, iclass 34, count 2 2006.246.07:42:09.01#ibcon#about to read 4, iclass 34, count 2 2006.246.07:42:09.01#ibcon#read 4, iclass 34, count 2 2006.246.07:42:09.01#ibcon#about to read 5, iclass 34, count 2 2006.246.07:42:09.01#ibcon#read 5, iclass 34, count 2 2006.246.07:42:09.01#ibcon#about to read 6, iclass 34, count 2 2006.246.07:42:09.01#ibcon#read 6, iclass 34, count 2 2006.246.07:42:09.01#ibcon#end of sib2, iclass 34, count 2 2006.246.07:42:09.01#ibcon#*mode == 0, iclass 34, count 2 2006.246.07:42:09.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.07:42:09.01#ibcon#[25=AT04-07\r\n] 2006.246.07:42:09.01#ibcon#*before write, iclass 34, count 2 2006.246.07:42:09.01#ibcon#enter sib2, iclass 34, count 2 2006.246.07:42:09.01#ibcon#flushed, iclass 34, count 2 2006.246.07:42:09.01#ibcon#about to write, iclass 34, count 2 2006.246.07:42:09.01#ibcon#wrote, iclass 34, count 2 2006.246.07:42:09.01#ibcon#about to read 3, iclass 34, count 2 2006.246.07:42:09.04#ibcon#read 3, iclass 34, count 2 2006.246.07:42:09.04#ibcon#about to read 4, iclass 34, count 2 2006.246.07:42:09.04#ibcon#read 4, iclass 34, count 2 2006.246.07:42:09.04#ibcon#about to read 5, iclass 34, count 2 2006.246.07:42:09.04#ibcon#read 5, iclass 34, count 2 2006.246.07:42:09.04#ibcon#about to read 6, iclass 34, count 2 2006.246.07:42:09.04#ibcon#read 6, iclass 34, count 2 2006.246.07:42:09.04#ibcon#end of sib2, iclass 34, count 2 2006.246.07:42:09.04#ibcon#*after write, iclass 34, count 2 2006.246.07:42:09.04#ibcon#*before return 0, iclass 34, count 2 2006.246.07:42:09.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:09.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:09.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.07:42:09.04#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:09.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:09.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:09.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:09.16#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:42:09.16#ibcon#first serial, iclass 34, count 0 2006.246.07:42:09.16#ibcon#enter sib2, iclass 34, count 0 2006.246.07:42:09.16#ibcon#flushed, iclass 34, count 0 2006.246.07:42:09.16#ibcon#about to write, iclass 34, count 0 2006.246.07:42:09.16#ibcon#wrote, iclass 34, count 0 2006.246.07:42:09.16#ibcon#about to read 3, iclass 34, count 0 2006.246.07:42:09.18#ibcon#read 3, iclass 34, count 0 2006.246.07:42:09.18#ibcon#about to read 4, iclass 34, count 0 2006.246.07:42:09.18#ibcon#read 4, iclass 34, count 0 2006.246.07:42:09.18#ibcon#about to read 5, iclass 34, count 0 2006.246.07:42:09.18#ibcon#read 5, iclass 34, count 0 2006.246.07:42:09.18#ibcon#about to read 6, iclass 34, count 0 2006.246.07:42:09.18#ibcon#read 6, iclass 34, count 0 2006.246.07:42:09.18#ibcon#end of sib2, iclass 34, count 0 2006.246.07:42:09.18#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:42:09.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:42:09.18#ibcon#[25=USB\r\n] 2006.246.07:42:09.18#ibcon#*before write, iclass 34, count 0 2006.246.07:42:09.18#ibcon#enter sib2, iclass 34, count 0 2006.246.07:42:09.18#ibcon#flushed, iclass 34, count 0 2006.246.07:42:09.18#ibcon#about to write, iclass 34, count 0 2006.246.07:42:09.18#ibcon#wrote, iclass 34, count 0 2006.246.07:42:09.18#ibcon#about to read 3, iclass 34, count 0 2006.246.07:42:09.21#ibcon#read 3, iclass 34, count 0 2006.246.07:42:09.21#ibcon#about to read 4, iclass 34, count 0 2006.246.07:42:09.21#ibcon#read 4, iclass 34, count 0 2006.246.07:42:09.21#ibcon#about to read 5, iclass 34, count 0 2006.246.07:42:09.21#ibcon#read 5, iclass 34, count 0 2006.246.07:42:09.21#ibcon#about to read 6, iclass 34, count 0 2006.246.07:42:09.21#ibcon#read 6, iclass 34, count 0 2006.246.07:42:09.21#ibcon#end of sib2, iclass 34, count 0 2006.246.07:42:09.21#ibcon#*after write, iclass 34, count 0 2006.246.07:42:09.21#ibcon#*before return 0, iclass 34, count 0 2006.246.07:42:09.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:09.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:09.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:42:09.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:42:09.21$vc4f8/valo=5,652.99 2006.246.07:42:09.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.07:42:09.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.07:42:09.21#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:09.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:09.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:09.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:09.21#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:42:09.21#ibcon#first serial, iclass 36, count 0 2006.246.07:42:09.21#ibcon#enter sib2, iclass 36, count 0 2006.246.07:42:09.21#ibcon#flushed, iclass 36, count 0 2006.246.07:42:09.21#ibcon#about to write, iclass 36, count 0 2006.246.07:42:09.21#ibcon#wrote, iclass 36, count 0 2006.246.07:42:09.21#ibcon#about to read 3, iclass 36, count 0 2006.246.07:42:09.23#ibcon#read 3, iclass 36, count 0 2006.246.07:42:09.23#ibcon#about to read 4, iclass 36, count 0 2006.246.07:42:09.23#ibcon#read 4, iclass 36, count 0 2006.246.07:42:09.23#ibcon#about to read 5, iclass 36, count 0 2006.246.07:42:09.23#ibcon#read 5, iclass 36, count 0 2006.246.07:42:09.23#ibcon#about to read 6, iclass 36, count 0 2006.246.07:42:09.23#ibcon#read 6, iclass 36, count 0 2006.246.07:42:09.23#ibcon#end of sib2, iclass 36, count 0 2006.246.07:42:09.23#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:42:09.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:42:09.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:42:09.23#ibcon#*before write, iclass 36, count 0 2006.246.07:42:09.23#ibcon#enter sib2, iclass 36, count 0 2006.246.07:42:09.23#ibcon#flushed, iclass 36, count 0 2006.246.07:42:09.23#ibcon#about to write, iclass 36, count 0 2006.246.07:42:09.23#ibcon#wrote, iclass 36, count 0 2006.246.07:42:09.23#ibcon#about to read 3, iclass 36, count 0 2006.246.07:42:09.27#ibcon#read 3, iclass 36, count 0 2006.246.07:42:09.27#ibcon#about to read 4, iclass 36, count 0 2006.246.07:42:09.27#ibcon#read 4, iclass 36, count 0 2006.246.07:42:09.27#ibcon#about to read 5, iclass 36, count 0 2006.246.07:42:09.27#ibcon#read 5, iclass 36, count 0 2006.246.07:42:09.27#ibcon#about to read 6, iclass 36, count 0 2006.246.07:42:09.27#ibcon#read 6, iclass 36, count 0 2006.246.07:42:09.27#ibcon#end of sib2, iclass 36, count 0 2006.246.07:42:09.27#ibcon#*after write, iclass 36, count 0 2006.246.07:42:09.27#ibcon#*before return 0, iclass 36, count 0 2006.246.07:42:09.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:09.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:09.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:42:09.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:42:09.27$vc4f8/va=5,7 2006.246.07:42:09.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.07:42:09.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.07:42:09.27#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:09.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:09.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:09.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:09.33#ibcon#enter wrdev, iclass 38, count 2 2006.246.07:42:09.33#ibcon#first serial, iclass 38, count 2 2006.246.07:42:09.33#ibcon#enter sib2, iclass 38, count 2 2006.246.07:42:09.33#ibcon#flushed, iclass 38, count 2 2006.246.07:42:09.33#ibcon#about to write, iclass 38, count 2 2006.246.07:42:09.33#ibcon#wrote, iclass 38, count 2 2006.246.07:42:09.33#ibcon#about to read 3, iclass 38, count 2 2006.246.07:42:09.35#ibcon#read 3, iclass 38, count 2 2006.246.07:42:09.35#ibcon#about to read 4, iclass 38, count 2 2006.246.07:42:09.35#ibcon#read 4, iclass 38, count 2 2006.246.07:42:09.35#ibcon#about to read 5, iclass 38, count 2 2006.246.07:42:09.35#ibcon#read 5, iclass 38, count 2 2006.246.07:42:09.35#ibcon#about to read 6, iclass 38, count 2 2006.246.07:42:09.35#ibcon#read 6, iclass 38, count 2 2006.246.07:42:09.35#ibcon#end of sib2, iclass 38, count 2 2006.246.07:42:09.35#ibcon#*mode == 0, iclass 38, count 2 2006.246.07:42:09.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.07:42:09.35#ibcon#[25=AT05-07\r\n] 2006.246.07:42:09.35#ibcon#*before write, iclass 38, count 2 2006.246.07:42:09.35#ibcon#enter sib2, iclass 38, count 2 2006.246.07:42:09.35#ibcon#flushed, iclass 38, count 2 2006.246.07:42:09.35#ibcon#about to write, iclass 38, count 2 2006.246.07:42:09.35#ibcon#wrote, iclass 38, count 2 2006.246.07:42:09.35#ibcon#about to read 3, iclass 38, count 2 2006.246.07:42:09.38#ibcon#read 3, iclass 38, count 2 2006.246.07:42:09.38#ibcon#about to read 4, iclass 38, count 2 2006.246.07:42:09.38#ibcon#read 4, iclass 38, count 2 2006.246.07:42:09.38#ibcon#about to read 5, iclass 38, count 2 2006.246.07:42:09.38#ibcon#read 5, iclass 38, count 2 2006.246.07:42:09.38#ibcon#about to read 6, iclass 38, count 2 2006.246.07:42:09.38#ibcon#read 6, iclass 38, count 2 2006.246.07:42:09.38#ibcon#end of sib2, iclass 38, count 2 2006.246.07:42:09.38#ibcon#*after write, iclass 38, count 2 2006.246.07:42:09.38#ibcon#*before return 0, iclass 38, count 2 2006.246.07:42:09.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:09.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:09.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.07:42:09.38#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:09.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:09.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:09.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:09.50#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:42:09.50#ibcon#first serial, iclass 38, count 0 2006.246.07:42:09.50#ibcon#enter sib2, iclass 38, count 0 2006.246.07:42:09.50#ibcon#flushed, iclass 38, count 0 2006.246.07:42:09.50#ibcon#about to write, iclass 38, count 0 2006.246.07:42:09.50#ibcon#wrote, iclass 38, count 0 2006.246.07:42:09.50#ibcon#about to read 3, iclass 38, count 0 2006.246.07:42:09.52#ibcon#read 3, iclass 38, count 0 2006.246.07:42:09.52#ibcon#about to read 4, iclass 38, count 0 2006.246.07:42:09.52#ibcon#read 4, iclass 38, count 0 2006.246.07:42:09.52#ibcon#about to read 5, iclass 38, count 0 2006.246.07:42:09.52#ibcon#read 5, iclass 38, count 0 2006.246.07:42:09.52#ibcon#about to read 6, iclass 38, count 0 2006.246.07:42:09.52#ibcon#read 6, iclass 38, count 0 2006.246.07:42:09.52#ibcon#end of sib2, iclass 38, count 0 2006.246.07:42:09.52#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:42:09.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:42:09.52#ibcon#[25=USB\r\n] 2006.246.07:42:09.52#ibcon#*before write, iclass 38, count 0 2006.246.07:42:09.52#ibcon#enter sib2, iclass 38, count 0 2006.246.07:42:09.52#ibcon#flushed, iclass 38, count 0 2006.246.07:42:09.52#ibcon#about to write, iclass 38, count 0 2006.246.07:42:09.52#ibcon#wrote, iclass 38, count 0 2006.246.07:42:09.52#ibcon#about to read 3, iclass 38, count 0 2006.246.07:42:09.55#ibcon#read 3, iclass 38, count 0 2006.246.07:42:09.55#ibcon#about to read 4, iclass 38, count 0 2006.246.07:42:09.55#ibcon#read 4, iclass 38, count 0 2006.246.07:42:09.55#ibcon#about to read 5, iclass 38, count 0 2006.246.07:42:09.55#ibcon#read 5, iclass 38, count 0 2006.246.07:42:09.55#ibcon#about to read 6, iclass 38, count 0 2006.246.07:42:09.55#ibcon#read 6, iclass 38, count 0 2006.246.07:42:09.55#ibcon#end of sib2, iclass 38, count 0 2006.246.07:42:09.55#ibcon#*after write, iclass 38, count 0 2006.246.07:42:09.55#ibcon#*before return 0, iclass 38, count 0 2006.246.07:42:09.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:09.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:09.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:42:09.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:42:09.55$vc4f8/valo=6,772.99 2006.246.07:42:09.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:42:09.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:42:09.55#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:09.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:09.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:09.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:09.55#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:42:09.55#ibcon#first serial, iclass 40, count 0 2006.246.07:42:09.55#ibcon#enter sib2, iclass 40, count 0 2006.246.07:42:09.55#ibcon#flushed, iclass 40, count 0 2006.246.07:42:09.55#ibcon#about to write, iclass 40, count 0 2006.246.07:42:09.55#ibcon#wrote, iclass 40, count 0 2006.246.07:42:09.55#ibcon#about to read 3, iclass 40, count 0 2006.246.07:42:09.58#ibcon#read 3, iclass 40, count 0 2006.246.07:42:09.58#ibcon#about to read 4, iclass 40, count 0 2006.246.07:42:09.58#ibcon#read 4, iclass 40, count 0 2006.246.07:42:09.58#ibcon#about to read 5, iclass 40, count 0 2006.246.07:42:09.58#ibcon#read 5, iclass 40, count 0 2006.246.07:42:09.58#ibcon#about to read 6, iclass 40, count 0 2006.246.07:42:09.58#ibcon#read 6, iclass 40, count 0 2006.246.07:42:09.58#ibcon#end of sib2, iclass 40, count 0 2006.246.07:42:09.58#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:42:09.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:42:09.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:42:09.58#ibcon#*before write, iclass 40, count 0 2006.246.07:42:09.58#ibcon#enter sib2, iclass 40, count 0 2006.246.07:42:09.58#ibcon#flushed, iclass 40, count 0 2006.246.07:42:09.58#ibcon#about to write, iclass 40, count 0 2006.246.07:42:09.58#ibcon#wrote, iclass 40, count 0 2006.246.07:42:09.58#ibcon#about to read 3, iclass 40, count 0 2006.246.07:42:09.62#ibcon#read 3, iclass 40, count 0 2006.246.07:42:09.62#ibcon#about to read 4, iclass 40, count 0 2006.246.07:42:09.62#ibcon#read 4, iclass 40, count 0 2006.246.07:42:09.62#ibcon#about to read 5, iclass 40, count 0 2006.246.07:42:09.62#ibcon#read 5, iclass 40, count 0 2006.246.07:42:09.62#ibcon#about to read 6, iclass 40, count 0 2006.246.07:42:09.62#ibcon#read 6, iclass 40, count 0 2006.246.07:42:09.62#ibcon#end of sib2, iclass 40, count 0 2006.246.07:42:09.62#ibcon#*after write, iclass 40, count 0 2006.246.07:42:09.62#ibcon#*before return 0, iclass 40, count 0 2006.246.07:42:09.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:09.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:09.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:42:09.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:42:09.62$vc4f8/va=6,7 2006.246.07:42:09.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.07:42:09.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.07:42:09.62#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:09.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:42:09.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:42:09.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:42:09.68#ibcon#enter wrdev, iclass 4, count 2 2006.246.07:42:09.68#ibcon#first serial, iclass 4, count 2 2006.246.07:42:09.68#ibcon#enter sib2, iclass 4, count 2 2006.246.07:42:09.68#ibcon#flushed, iclass 4, count 2 2006.246.07:42:09.68#ibcon#about to write, iclass 4, count 2 2006.246.07:42:09.68#ibcon#wrote, iclass 4, count 2 2006.246.07:42:09.68#ibcon#about to read 3, iclass 4, count 2 2006.246.07:42:09.69#ibcon#read 3, iclass 4, count 2 2006.246.07:42:09.69#ibcon#about to read 4, iclass 4, count 2 2006.246.07:42:09.69#ibcon#read 4, iclass 4, count 2 2006.246.07:42:09.69#ibcon#about to read 5, iclass 4, count 2 2006.246.07:42:09.69#ibcon#read 5, iclass 4, count 2 2006.246.07:42:09.69#ibcon#about to read 6, iclass 4, count 2 2006.246.07:42:09.69#ibcon#read 6, iclass 4, count 2 2006.246.07:42:09.69#ibcon#end of sib2, iclass 4, count 2 2006.246.07:42:09.69#ibcon#*mode == 0, iclass 4, count 2 2006.246.07:42:09.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.07:42:09.69#ibcon#[25=AT06-07\r\n] 2006.246.07:42:09.69#ibcon#*before write, iclass 4, count 2 2006.246.07:42:09.69#ibcon#enter sib2, iclass 4, count 2 2006.246.07:42:09.69#ibcon#flushed, iclass 4, count 2 2006.246.07:42:09.69#ibcon#about to write, iclass 4, count 2 2006.246.07:42:09.69#ibcon#wrote, iclass 4, count 2 2006.246.07:42:09.69#ibcon#about to read 3, iclass 4, count 2 2006.246.07:42:09.72#ibcon#read 3, iclass 4, count 2 2006.246.07:42:09.72#ibcon#about to read 4, iclass 4, count 2 2006.246.07:42:09.72#ibcon#read 4, iclass 4, count 2 2006.246.07:42:09.72#ibcon#about to read 5, iclass 4, count 2 2006.246.07:42:09.72#ibcon#read 5, iclass 4, count 2 2006.246.07:42:09.72#ibcon#about to read 6, iclass 4, count 2 2006.246.07:42:09.72#ibcon#read 6, iclass 4, count 2 2006.246.07:42:09.72#ibcon#end of sib2, iclass 4, count 2 2006.246.07:42:09.72#ibcon#*after write, iclass 4, count 2 2006.246.07:42:09.72#ibcon#*before return 0, iclass 4, count 2 2006.246.07:42:09.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:42:09.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:42:09.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.07:42:09.72#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:09.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:42:09.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:42:09.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:42:09.84#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:42:09.84#ibcon#first serial, iclass 4, count 0 2006.246.07:42:09.84#ibcon#enter sib2, iclass 4, count 0 2006.246.07:42:09.84#ibcon#flushed, iclass 4, count 0 2006.246.07:42:09.84#ibcon#about to write, iclass 4, count 0 2006.246.07:42:09.84#ibcon#wrote, iclass 4, count 0 2006.246.07:42:09.84#ibcon#about to read 3, iclass 4, count 0 2006.246.07:42:09.86#ibcon#read 3, iclass 4, count 0 2006.246.07:42:09.86#ibcon#about to read 4, iclass 4, count 0 2006.246.07:42:09.86#ibcon#read 4, iclass 4, count 0 2006.246.07:42:09.86#ibcon#about to read 5, iclass 4, count 0 2006.246.07:42:09.86#ibcon#read 5, iclass 4, count 0 2006.246.07:42:09.86#ibcon#about to read 6, iclass 4, count 0 2006.246.07:42:09.86#ibcon#read 6, iclass 4, count 0 2006.246.07:42:09.86#ibcon#end of sib2, iclass 4, count 0 2006.246.07:42:09.86#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:42:09.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:42:09.86#ibcon#[25=USB\r\n] 2006.246.07:42:09.86#ibcon#*before write, iclass 4, count 0 2006.246.07:42:09.86#ibcon#enter sib2, iclass 4, count 0 2006.246.07:42:09.86#ibcon#flushed, iclass 4, count 0 2006.246.07:42:09.86#ibcon#about to write, iclass 4, count 0 2006.246.07:42:09.86#ibcon#wrote, iclass 4, count 0 2006.246.07:42:09.86#ibcon#about to read 3, iclass 4, count 0 2006.246.07:42:09.89#ibcon#read 3, iclass 4, count 0 2006.246.07:42:09.89#ibcon#about to read 4, iclass 4, count 0 2006.246.07:42:09.89#ibcon#read 4, iclass 4, count 0 2006.246.07:42:09.89#ibcon#about to read 5, iclass 4, count 0 2006.246.07:42:09.89#ibcon#read 5, iclass 4, count 0 2006.246.07:42:09.89#ibcon#about to read 6, iclass 4, count 0 2006.246.07:42:09.89#ibcon#read 6, iclass 4, count 0 2006.246.07:42:09.89#ibcon#end of sib2, iclass 4, count 0 2006.246.07:42:09.89#ibcon#*after write, iclass 4, count 0 2006.246.07:42:09.89#ibcon#*before return 0, iclass 4, count 0 2006.246.07:42:09.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:42:09.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:42:09.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:42:09.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:42:09.89$vc4f8/valo=7,832.99 2006.246.07:42:09.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.07:42:09.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.07:42:09.89#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:09.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:42:09.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:42:09.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:42:09.89#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:42:09.89#ibcon#first serial, iclass 6, count 0 2006.246.07:42:09.89#ibcon#enter sib2, iclass 6, count 0 2006.246.07:42:09.89#ibcon#flushed, iclass 6, count 0 2006.246.07:42:09.89#ibcon#about to write, iclass 6, count 0 2006.246.07:42:09.89#ibcon#wrote, iclass 6, count 0 2006.246.07:42:09.89#ibcon#about to read 3, iclass 6, count 0 2006.246.07:42:09.91#ibcon#read 3, iclass 6, count 0 2006.246.07:42:09.91#ibcon#about to read 4, iclass 6, count 0 2006.246.07:42:09.91#ibcon#read 4, iclass 6, count 0 2006.246.07:42:09.91#ibcon#about to read 5, iclass 6, count 0 2006.246.07:42:09.91#ibcon#read 5, iclass 6, count 0 2006.246.07:42:09.91#ibcon#about to read 6, iclass 6, count 0 2006.246.07:42:09.91#ibcon#read 6, iclass 6, count 0 2006.246.07:42:09.91#ibcon#end of sib2, iclass 6, count 0 2006.246.07:42:09.91#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:42:09.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:42:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:42:09.91#ibcon#*before write, iclass 6, count 0 2006.246.07:42:09.91#ibcon#enter sib2, iclass 6, count 0 2006.246.07:42:09.91#ibcon#flushed, iclass 6, count 0 2006.246.07:42:09.91#ibcon#about to write, iclass 6, count 0 2006.246.07:42:09.91#ibcon#wrote, iclass 6, count 0 2006.246.07:42:09.91#ibcon#about to read 3, iclass 6, count 0 2006.246.07:42:09.95#ibcon#read 3, iclass 6, count 0 2006.246.07:42:09.95#ibcon#about to read 4, iclass 6, count 0 2006.246.07:42:09.95#ibcon#read 4, iclass 6, count 0 2006.246.07:42:09.95#ibcon#about to read 5, iclass 6, count 0 2006.246.07:42:09.95#ibcon#read 5, iclass 6, count 0 2006.246.07:42:09.95#ibcon#about to read 6, iclass 6, count 0 2006.246.07:42:09.95#ibcon#read 6, iclass 6, count 0 2006.246.07:42:09.95#ibcon#end of sib2, iclass 6, count 0 2006.246.07:42:09.95#ibcon#*after write, iclass 6, count 0 2006.246.07:42:09.95#ibcon#*before return 0, iclass 6, count 0 2006.246.07:42:09.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:42:09.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:42:09.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:42:09.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:42:09.95$vc4f8/va=7,7 2006.246.07:42:09.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.07:42:09.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.07:42:09.95#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:09.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:42:10.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:42:10.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:42:10.01#ibcon#enter wrdev, iclass 10, count 2 2006.246.07:42:10.01#ibcon#first serial, iclass 10, count 2 2006.246.07:42:10.01#ibcon#enter sib2, iclass 10, count 2 2006.246.07:42:10.01#ibcon#flushed, iclass 10, count 2 2006.246.07:42:10.01#ibcon#about to write, iclass 10, count 2 2006.246.07:42:10.01#ibcon#wrote, iclass 10, count 2 2006.246.07:42:10.01#ibcon#about to read 3, iclass 10, count 2 2006.246.07:42:10.03#ibcon#read 3, iclass 10, count 2 2006.246.07:42:10.03#ibcon#about to read 4, iclass 10, count 2 2006.246.07:42:10.03#ibcon#read 4, iclass 10, count 2 2006.246.07:42:10.03#ibcon#about to read 5, iclass 10, count 2 2006.246.07:42:10.03#ibcon#read 5, iclass 10, count 2 2006.246.07:42:10.03#ibcon#about to read 6, iclass 10, count 2 2006.246.07:42:10.03#ibcon#read 6, iclass 10, count 2 2006.246.07:42:10.03#ibcon#end of sib2, iclass 10, count 2 2006.246.07:42:10.03#ibcon#*mode == 0, iclass 10, count 2 2006.246.07:42:10.03#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.07:42:10.03#ibcon#[25=AT07-07\r\n] 2006.246.07:42:10.03#ibcon#*before write, iclass 10, count 2 2006.246.07:42:10.03#ibcon#enter sib2, iclass 10, count 2 2006.246.07:42:10.03#ibcon#flushed, iclass 10, count 2 2006.246.07:42:10.03#ibcon#about to write, iclass 10, count 2 2006.246.07:42:10.03#ibcon#wrote, iclass 10, count 2 2006.246.07:42:10.03#ibcon#about to read 3, iclass 10, count 2 2006.246.07:42:10.06#ibcon#read 3, iclass 10, count 2 2006.246.07:42:10.06#ibcon#about to read 4, iclass 10, count 2 2006.246.07:42:10.06#ibcon#read 4, iclass 10, count 2 2006.246.07:42:10.06#ibcon#about to read 5, iclass 10, count 2 2006.246.07:42:10.06#ibcon#read 5, iclass 10, count 2 2006.246.07:42:10.06#ibcon#about to read 6, iclass 10, count 2 2006.246.07:42:10.06#ibcon#read 6, iclass 10, count 2 2006.246.07:42:10.06#ibcon#end of sib2, iclass 10, count 2 2006.246.07:42:10.06#ibcon#*after write, iclass 10, count 2 2006.246.07:42:10.06#ibcon#*before return 0, iclass 10, count 2 2006.246.07:42:10.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:42:10.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:42:10.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.07:42:10.06#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:10.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:42:10.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:42:10.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:42:10.18#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:42:10.18#ibcon#first serial, iclass 10, count 0 2006.246.07:42:10.18#ibcon#enter sib2, iclass 10, count 0 2006.246.07:42:10.18#ibcon#flushed, iclass 10, count 0 2006.246.07:42:10.18#ibcon#about to write, iclass 10, count 0 2006.246.07:42:10.18#ibcon#wrote, iclass 10, count 0 2006.246.07:42:10.18#ibcon#about to read 3, iclass 10, count 0 2006.246.07:42:10.20#ibcon#read 3, iclass 10, count 0 2006.246.07:42:10.20#ibcon#about to read 4, iclass 10, count 0 2006.246.07:42:10.20#ibcon#read 4, iclass 10, count 0 2006.246.07:42:10.20#ibcon#about to read 5, iclass 10, count 0 2006.246.07:42:10.20#ibcon#read 5, iclass 10, count 0 2006.246.07:42:10.20#ibcon#about to read 6, iclass 10, count 0 2006.246.07:42:10.20#ibcon#read 6, iclass 10, count 0 2006.246.07:42:10.20#ibcon#end of sib2, iclass 10, count 0 2006.246.07:42:10.20#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:42:10.20#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:42:10.20#ibcon#[25=USB\r\n] 2006.246.07:42:10.20#ibcon#*before write, iclass 10, count 0 2006.246.07:42:10.20#ibcon#enter sib2, iclass 10, count 0 2006.246.07:42:10.20#ibcon#flushed, iclass 10, count 0 2006.246.07:42:10.20#ibcon#about to write, iclass 10, count 0 2006.246.07:42:10.20#ibcon#wrote, iclass 10, count 0 2006.246.07:42:10.20#ibcon#about to read 3, iclass 10, count 0 2006.246.07:42:10.23#ibcon#read 3, iclass 10, count 0 2006.246.07:42:10.23#ibcon#about to read 4, iclass 10, count 0 2006.246.07:42:10.23#ibcon#read 4, iclass 10, count 0 2006.246.07:42:10.23#ibcon#about to read 5, iclass 10, count 0 2006.246.07:42:10.23#ibcon#read 5, iclass 10, count 0 2006.246.07:42:10.23#ibcon#about to read 6, iclass 10, count 0 2006.246.07:42:10.23#ibcon#read 6, iclass 10, count 0 2006.246.07:42:10.23#ibcon#end of sib2, iclass 10, count 0 2006.246.07:42:10.23#ibcon#*after write, iclass 10, count 0 2006.246.07:42:10.23#ibcon#*before return 0, iclass 10, count 0 2006.246.07:42:10.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:42:10.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:42:10.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:42:10.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:42:10.23$vc4f8/valo=8,852.99 2006.246.07:42:10.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.07:42:10.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.07:42:10.23#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:10.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:42:10.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:42:10.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:42:10.23#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:42:10.23#ibcon#first serial, iclass 12, count 0 2006.246.07:42:10.23#ibcon#enter sib2, iclass 12, count 0 2006.246.07:42:10.23#ibcon#flushed, iclass 12, count 0 2006.246.07:42:10.23#ibcon#about to write, iclass 12, count 0 2006.246.07:42:10.23#ibcon#wrote, iclass 12, count 0 2006.246.07:42:10.23#ibcon#about to read 3, iclass 12, count 0 2006.246.07:42:10.25#ibcon#read 3, iclass 12, count 0 2006.246.07:42:10.25#ibcon#about to read 4, iclass 12, count 0 2006.246.07:42:10.25#ibcon#read 4, iclass 12, count 0 2006.246.07:42:10.25#ibcon#about to read 5, iclass 12, count 0 2006.246.07:42:10.25#ibcon#read 5, iclass 12, count 0 2006.246.07:42:10.25#ibcon#about to read 6, iclass 12, count 0 2006.246.07:42:10.25#ibcon#read 6, iclass 12, count 0 2006.246.07:42:10.25#ibcon#end of sib2, iclass 12, count 0 2006.246.07:42:10.25#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:42:10.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:42:10.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:42:10.25#ibcon#*before write, iclass 12, count 0 2006.246.07:42:10.25#ibcon#enter sib2, iclass 12, count 0 2006.246.07:42:10.25#ibcon#flushed, iclass 12, count 0 2006.246.07:42:10.25#ibcon#about to write, iclass 12, count 0 2006.246.07:42:10.25#ibcon#wrote, iclass 12, count 0 2006.246.07:42:10.25#ibcon#about to read 3, iclass 12, count 0 2006.246.07:42:10.29#ibcon#read 3, iclass 12, count 0 2006.246.07:42:10.29#ibcon#about to read 4, iclass 12, count 0 2006.246.07:42:10.29#ibcon#read 4, iclass 12, count 0 2006.246.07:42:10.29#ibcon#about to read 5, iclass 12, count 0 2006.246.07:42:10.29#ibcon#read 5, iclass 12, count 0 2006.246.07:42:10.29#ibcon#about to read 6, iclass 12, count 0 2006.246.07:42:10.29#ibcon#read 6, iclass 12, count 0 2006.246.07:42:10.29#ibcon#end of sib2, iclass 12, count 0 2006.246.07:42:10.29#ibcon#*after write, iclass 12, count 0 2006.246.07:42:10.29#ibcon#*before return 0, iclass 12, count 0 2006.246.07:42:10.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:42:10.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:42:10.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:42:10.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:42:10.29$vc4f8/va=8,8 2006.246.07:42:10.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.07:42:10.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.07:42:10.29#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:10.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:42:10.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:42:10.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:42:10.35#ibcon#enter wrdev, iclass 14, count 2 2006.246.07:42:10.35#ibcon#first serial, iclass 14, count 2 2006.246.07:42:10.35#ibcon#enter sib2, iclass 14, count 2 2006.246.07:42:10.35#ibcon#flushed, iclass 14, count 2 2006.246.07:42:10.35#ibcon#about to write, iclass 14, count 2 2006.246.07:42:10.35#ibcon#wrote, iclass 14, count 2 2006.246.07:42:10.35#ibcon#about to read 3, iclass 14, count 2 2006.246.07:42:10.37#ibcon#read 3, iclass 14, count 2 2006.246.07:42:10.37#ibcon#about to read 4, iclass 14, count 2 2006.246.07:42:10.37#ibcon#read 4, iclass 14, count 2 2006.246.07:42:10.37#ibcon#about to read 5, iclass 14, count 2 2006.246.07:42:10.37#ibcon#read 5, iclass 14, count 2 2006.246.07:42:10.37#ibcon#about to read 6, iclass 14, count 2 2006.246.07:42:10.37#ibcon#read 6, iclass 14, count 2 2006.246.07:42:10.37#ibcon#end of sib2, iclass 14, count 2 2006.246.07:42:10.37#ibcon#*mode == 0, iclass 14, count 2 2006.246.07:42:10.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.07:42:10.37#ibcon#[25=AT08-08\r\n] 2006.246.07:42:10.37#ibcon#*before write, iclass 14, count 2 2006.246.07:42:10.37#ibcon#enter sib2, iclass 14, count 2 2006.246.07:42:10.37#ibcon#flushed, iclass 14, count 2 2006.246.07:42:10.37#ibcon#about to write, iclass 14, count 2 2006.246.07:42:10.37#ibcon#wrote, iclass 14, count 2 2006.246.07:42:10.37#ibcon#about to read 3, iclass 14, count 2 2006.246.07:42:10.40#ibcon#read 3, iclass 14, count 2 2006.246.07:42:10.40#ibcon#about to read 4, iclass 14, count 2 2006.246.07:42:10.40#ibcon#read 4, iclass 14, count 2 2006.246.07:42:10.40#ibcon#about to read 5, iclass 14, count 2 2006.246.07:42:10.40#ibcon#read 5, iclass 14, count 2 2006.246.07:42:10.40#ibcon#about to read 6, iclass 14, count 2 2006.246.07:42:10.40#ibcon#read 6, iclass 14, count 2 2006.246.07:42:10.40#ibcon#end of sib2, iclass 14, count 2 2006.246.07:42:10.40#ibcon#*after write, iclass 14, count 2 2006.246.07:42:10.40#ibcon#*before return 0, iclass 14, count 2 2006.246.07:42:10.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:42:10.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:42:10.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.07:42:10.40#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:10.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:42:10.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:42:10.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:42:10.52#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:42:10.52#ibcon#first serial, iclass 14, count 0 2006.246.07:42:10.52#ibcon#enter sib2, iclass 14, count 0 2006.246.07:42:10.52#ibcon#flushed, iclass 14, count 0 2006.246.07:42:10.52#ibcon#about to write, iclass 14, count 0 2006.246.07:42:10.52#ibcon#wrote, iclass 14, count 0 2006.246.07:42:10.52#ibcon#about to read 3, iclass 14, count 0 2006.246.07:42:10.54#ibcon#read 3, iclass 14, count 0 2006.246.07:42:10.54#ibcon#about to read 4, iclass 14, count 0 2006.246.07:42:10.54#ibcon#read 4, iclass 14, count 0 2006.246.07:42:10.54#ibcon#about to read 5, iclass 14, count 0 2006.246.07:42:10.54#ibcon#read 5, iclass 14, count 0 2006.246.07:42:10.54#ibcon#about to read 6, iclass 14, count 0 2006.246.07:42:10.54#ibcon#read 6, iclass 14, count 0 2006.246.07:42:10.54#ibcon#end of sib2, iclass 14, count 0 2006.246.07:42:10.54#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:42:10.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:42:10.54#ibcon#[25=USB\r\n] 2006.246.07:42:10.54#ibcon#*before write, iclass 14, count 0 2006.246.07:42:10.54#ibcon#enter sib2, iclass 14, count 0 2006.246.07:42:10.54#ibcon#flushed, iclass 14, count 0 2006.246.07:42:10.54#ibcon#about to write, iclass 14, count 0 2006.246.07:42:10.54#ibcon#wrote, iclass 14, count 0 2006.246.07:42:10.54#ibcon#about to read 3, iclass 14, count 0 2006.246.07:42:10.57#ibcon#read 3, iclass 14, count 0 2006.246.07:42:10.57#ibcon#about to read 4, iclass 14, count 0 2006.246.07:42:10.57#ibcon#read 4, iclass 14, count 0 2006.246.07:42:10.57#ibcon#about to read 5, iclass 14, count 0 2006.246.07:42:10.57#ibcon#read 5, iclass 14, count 0 2006.246.07:42:10.57#ibcon#about to read 6, iclass 14, count 0 2006.246.07:42:10.57#ibcon#read 6, iclass 14, count 0 2006.246.07:42:10.57#ibcon#end of sib2, iclass 14, count 0 2006.246.07:42:10.57#ibcon#*after write, iclass 14, count 0 2006.246.07:42:10.57#ibcon#*before return 0, iclass 14, count 0 2006.246.07:42:10.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:42:10.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:42:10.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:42:10.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:42:10.57$vc4f8/vblo=1,632.99 2006.246.07:42:10.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.07:42:10.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.07:42:10.57#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:10.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:42:10.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:42:10.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:42:10.57#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:42:10.57#ibcon#first serial, iclass 16, count 0 2006.246.07:42:10.57#ibcon#enter sib2, iclass 16, count 0 2006.246.07:42:10.57#ibcon#flushed, iclass 16, count 0 2006.246.07:42:10.57#ibcon#about to write, iclass 16, count 0 2006.246.07:42:10.57#ibcon#wrote, iclass 16, count 0 2006.246.07:42:10.57#ibcon#about to read 3, iclass 16, count 0 2006.246.07:42:10.59#ibcon#read 3, iclass 16, count 0 2006.246.07:42:10.59#ibcon#about to read 4, iclass 16, count 0 2006.246.07:42:10.59#ibcon#read 4, iclass 16, count 0 2006.246.07:42:10.59#ibcon#about to read 5, iclass 16, count 0 2006.246.07:42:10.59#ibcon#read 5, iclass 16, count 0 2006.246.07:42:10.59#ibcon#about to read 6, iclass 16, count 0 2006.246.07:42:10.59#ibcon#read 6, iclass 16, count 0 2006.246.07:42:10.59#ibcon#end of sib2, iclass 16, count 0 2006.246.07:42:10.59#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:42:10.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:42:10.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:42:10.59#ibcon#*before write, iclass 16, count 0 2006.246.07:42:10.59#ibcon#enter sib2, iclass 16, count 0 2006.246.07:42:10.59#ibcon#flushed, iclass 16, count 0 2006.246.07:42:10.59#ibcon#about to write, iclass 16, count 0 2006.246.07:42:10.59#ibcon#wrote, iclass 16, count 0 2006.246.07:42:10.59#ibcon#about to read 3, iclass 16, count 0 2006.246.07:42:10.63#ibcon#read 3, iclass 16, count 0 2006.246.07:42:10.63#ibcon#about to read 4, iclass 16, count 0 2006.246.07:42:10.63#ibcon#read 4, iclass 16, count 0 2006.246.07:42:10.63#ibcon#about to read 5, iclass 16, count 0 2006.246.07:42:10.63#ibcon#read 5, iclass 16, count 0 2006.246.07:42:10.63#ibcon#about to read 6, iclass 16, count 0 2006.246.07:42:10.63#ibcon#read 6, iclass 16, count 0 2006.246.07:42:10.63#ibcon#end of sib2, iclass 16, count 0 2006.246.07:42:10.63#ibcon#*after write, iclass 16, count 0 2006.246.07:42:10.63#ibcon#*before return 0, iclass 16, count 0 2006.246.07:42:10.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:42:10.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:42:10.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:42:10.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:42:10.63$vc4f8/vb=1,4 2006.246.07:42:10.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.07:42:10.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.07:42:10.63#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:10.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:42:10.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:42:10.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:42:10.63#ibcon#enter wrdev, iclass 18, count 2 2006.246.07:42:10.63#ibcon#first serial, iclass 18, count 2 2006.246.07:42:10.63#ibcon#enter sib2, iclass 18, count 2 2006.246.07:42:10.63#ibcon#flushed, iclass 18, count 2 2006.246.07:42:10.63#ibcon#about to write, iclass 18, count 2 2006.246.07:42:10.63#ibcon#wrote, iclass 18, count 2 2006.246.07:42:10.63#ibcon#about to read 3, iclass 18, count 2 2006.246.07:42:10.65#ibcon#read 3, iclass 18, count 2 2006.246.07:42:10.65#ibcon#about to read 4, iclass 18, count 2 2006.246.07:42:10.65#ibcon#read 4, iclass 18, count 2 2006.246.07:42:10.65#ibcon#about to read 5, iclass 18, count 2 2006.246.07:42:10.65#ibcon#read 5, iclass 18, count 2 2006.246.07:42:10.65#ibcon#about to read 6, iclass 18, count 2 2006.246.07:42:10.65#ibcon#read 6, iclass 18, count 2 2006.246.07:42:10.65#ibcon#end of sib2, iclass 18, count 2 2006.246.07:42:10.65#ibcon#*mode == 0, iclass 18, count 2 2006.246.07:42:10.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.07:42:10.65#ibcon#[27=AT01-04\r\n] 2006.246.07:42:10.65#ibcon#*before write, iclass 18, count 2 2006.246.07:42:10.65#ibcon#enter sib2, iclass 18, count 2 2006.246.07:42:10.65#ibcon#flushed, iclass 18, count 2 2006.246.07:42:10.65#ibcon#about to write, iclass 18, count 2 2006.246.07:42:10.65#ibcon#wrote, iclass 18, count 2 2006.246.07:42:10.65#ibcon#about to read 3, iclass 18, count 2 2006.246.07:42:10.68#ibcon#read 3, iclass 18, count 2 2006.246.07:42:10.68#ibcon#about to read 4, iclass 18, count 2 2006.246.07:42:10.68#ibcon#read 4, iclass 18, count 2 2006.246.07:42:10.68#ibcon#about to read 5, iclass 18, count 2 2006.246.07:42:10.68#ibcon#read 5, iclass 18, count 2 2006.246.07:42:10.68#ibcon#about to read 6, iclass 18, count 2 2006.246.07:42:10.68#ibcon#read 6, iclass 18, count 2 2006.246.07:42:10.68#ibcon#end of sib2, iclass 18, count 2 2006.246.07:42:10.68#ibcon#*after write, iclass 18, count 2 2006.246.07:42:10.68#ibcon#*before return 0, iclass 18, count 2 2006.246.07:42:10.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:42:10.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:42:10.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.07:42:10.68#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:10.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:42:10.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:42:10.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:42:10.80#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:42:10.80#ibcon#first serial, iclass 18, count 0 2006.246.07:42:10.80#ibcon#enter sib2, iclass 18, count 0 2006.246.07:42:10.80#ibcon#flushed, iclass 18, count 0 2006.246.07:42:10.80#ibcon#about to write, iclass 18, count 0 2006.246.07:42:10.80#ibcon#wrote, iclass 18, count 0 2006.246.07:42:10.80#ibcon#about to read 3, iclass 18, count 0 2006.246.07:42:10.82#ibcon#read 3, iclass 18, count 0 2006.246.07:42:10.82#ibcon#about to read 4, iclass 18, count 0 2006.246.07:42:10.82#ibcon#read 4, iclass 18, count 0 2006.246.07:42:10.82#ibcon#about to read 5, iclass 18, count 0 2006.246.07:42:10.82#ibcon#read 5, iclass 18, count 0 2006.246.07:42:10.82#ibcon#about to read 6, iclass 18, count 0 2006.246.07:42:10.82#ibcon#read 6, iclass 18, count 0 2006.246.07:42:10.82#ibcon#end of sib2, iclass 18, count 0 2006.246.07:42:10.82#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:42:10.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:42:10.82#ibcon#[27=USB\r\n] 2006.246.07:42:10.82#ibcon#*before write, iclass 18, count 0 2006.246.07:42:10.82#ibcon#enter sib2, iclass 18, count 0 2006.246.07:42:10.82#ibcon#flushed, iclass 18, count 0 2006.246.07:42:10.82#ibcon#about to write, iclass 18, count 0 2006.246.07:42:10.82#ibcon#wrote, iclass 18, count 0 2006.246.07:42:10.82#ibcon#about to read 3, iclass 18, count 0 2006.246.07:42:10.85#ibcon#read 3, iclass 18, count 0 2006.246.07:42:10.85#ibcon#about to read 4, iclass 18, count 0 2006.246.07:42:10.85#ibcon#read 4, iclass 18, count 0 2006.246.07:42:10.85#ibcon#about to read 5, iclass 18, count 0 2006.246.07:42:10.85#ibcon#read 5, iclass 18, count 0 2006.246.07:42:10.85#ibcon#about to read 6, iclass 18, count 0 2006.246.07:42:10.85#ibcon#read 6, iclass 18, count 0 2006.246.07:42:10.85#ibcon#end of sib2, iclass 18, count 0 2006.246.07:42:10.85#ibcon#*after write, iclass 18, count 0 2006.246.07:42:10.85#ibcon#*before return 0, iclass 18, count 0 2006.246.07:42:10.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:42:10.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:42:10.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:42:10.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:42:10.85$vc4f8/vblo=2,640.99 2006.246.07:42:10.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.07:42:10.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.07:42:10.85#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:10.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:42:10.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:42:10.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:42:10.85#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:42:10.85#ibcon#first serial, iclass 20, count 0 2006.246.07:42:10.85#ibcon#enter sib2, iclass 20, count 0 2006.246.07:42:10.85#ibcon#flushed, iclass 20, count 0 2006.246.07:42:10.85#ibcon#about to write, iclass 20, count 0 2006.246.07:42:10.85#ibcon#wrote, iclass 20, count 0 2006.246.07:42:10.85#ibcon#about to read 3, iclass 20, count 0 2006.246.07:42:10.87#ibcon#read 3, iclass 20, count 0 2006.246.07:42:10.87#ibcon#about to read 4, iclass 20, count 0 2006.246.07:42:10.87#ibcon#read 4, iclass 20, count 0 2006.246.07:42:10.87#ibcon#about to read 5, iclass 20, count 0 2006.246.07:42:10.87#ibcon#read 5, iclass 20, count 0 2006.246.07:42:10.87#ibcon#about to read 6, iclass 20, count 0 2006.246.07:42:10.87#ibcon#read 6, iclass 20, count 0 2006.246.07:42:10.87#ibcon#end of sib2, iclass 20, count 0 2006.246.07:42:10.87#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:42:10.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:42:10.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:42:10.87#ibcon#*before write, iclass 20, count 0 2006.246.07:42:10.87#ibcon#enter sib2, iclass 20, count 0 2006.246.07:42:10.87#ibcon#flushed, iclass 20, count 0 2006.246.07:42:10.87#ibcon#about to write, iclass 20, count 0 2006.246.07:42:10.87#ibcon#wrote, iclass 20, count 0 2006.246.07:42:10.87#ibcon#about to read 3, iclass 20, count 0 2006.246.07:42:10.91#ibcon#read 3, iclass 20, count 0 2006.246.07:42:10.91#ibcon#about to read 4, iclass 20, count 0 2006.246.07:42:10.91#ibcon#read 4, iclass 20, count 0 2006.246.07:42:10.91#ibcon#about to read 5, iclass 20, count 0 2006.246.07:42:10.91#ibcon#read 5, iclass 20, count 0 2006.246.07:42:10.91#ibcon#about to read 6, iclass 20, count 0 2006.246.07:42:10.91#ibcon#read 6, iclass 20, count 0 2006.246.07:42:10.91#ibcon#end of sib2, iclass 20, count 0 2006.246.07:42:10.91#ibcon#*after write, iclass 20, count 0 2006.246.07:42:10.91#ibcon#*before return 0, iclass 20, count 0 2006.246.07:42:10.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:42:10.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:42:10.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:42:10.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:42:10.91$vc4f8/vb=2,4 2006.246.07:42:10.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.07:42:10.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.07:42:10.91#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:10.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:42:10.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:42:10.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:42:10.97#ibcon#enter wrdev, iclass 22, count 2 2006.246.07:42:10.97#ibcon#first serial, iclass 22, count 2 2006.246.07:42:10.97#ibcon#enter sib2, iclass 22, count 2 2006.246.07:42:10.97#ibcon#flushed, iclass 22, count 2 2006.246.07:42:10.97#ibcon#about to write, iclass 22, count 2 2006.246.07:42:10.97#ibcon#wrote, iclass 22, count 2 2006.246.07:42:10.97#ibcon#about to read 3, iclass 22, count 2 2006.246.07:42:10.99#ibcon#read 3, iclass 22, count 2 2006.246.07:42:10.99#ibcon#about to read 4, iclass 22, count 2 2006.246.07:42:10.99#ibcon#read 4, iclass 22, count 2 2006.246.07:42:10.99#ibcon#about to read 5, iclass 22, count 2 2006.246.07:42:10.99#ibcon#read 5, iclass 22, count 2 2006.246.07:42:10.99#ibcon#about to read 6, iclass 22, count 2 2006.246.07:42:10.99#ibcon#read 6, iclass 22, count 2 2006.246.07:42:10.99#ibcon#end of sib2, iclass 22, count 2 2006.246.07:42:10.99#ibcon#*mode == 0, iclass 22, count 2 2006.246.07:42:10.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.07:42:10.99#ibcon#[27=AT02-04\r\n] 2006.246.07:42:10.99#ibcon#*before write, iclass 22, count 2 2006.246.07:42:10.99#ibcon#enter sib2, iclass 22, count 2 2006.246.07:42:10.99#ibcon#flushed, iclass 22, count 2 2006.246.07:42:10.99#ibcon#about to write, iclass 22, count 2 2006.246.07:42:10.99#ibcon#wrote, iclass 22, count 2 2006.246.07:42:10.99#ibcon#about to read 3, iclass 22, count 2 2006.246.07:42:11.02#ibcon#read 3, iclass 22, count 2 2006.246.07:42:11.02#ibcon#about to read 4, iclass 22, count 2 2006.246.07:42:11.02#ibcon#read 4, iclass 22, count 2 2006.246.07:42:11.02#ibcon#about to read 5, iclass 22, count 2 2006.246.07:42:11.02#ibcon#read 5, iclass 22, count 2 2006.246.07:42:11.02#ibcon#about to read 6, iclass 22, count 2 2006.246.07:42:11.02#ibcon#read 6, iclass 22, count 2 2006.246.07:42:11.02#ibcon#end of sib2, iclass 22, count 2 2006.246.07:42:11.02#ibcon#*after write, iclass 22, count 2 2006.246.07:42:11.02#ibcon#*before return 0, iclass 22, count 2 2006.246.07:42:11.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:42:11.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:42:11.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.07:42:11.02#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:11.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:42:11.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:42:11.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:42:11.14#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:42:11.14#ibcon#first serial, iclass 22, count 0 2006.246.07:42:11.14#ibcon#enter sib2, iclass 22, count 0 2006.246.07:42:11.14#ibcon#flushed, iclass 22, count 0 2006.246.07:42:11.14#ibcon#about to write, iclass 22, count 0 2006.246.07:42:11.14#ibcon#wrote, iclass 22, count 0 2006.246.07:42:11.14#ibcon#about to read 3, iclass 22, count 0 2006.246.07:42:11.16#ibcon#read 3, iclass 22, count 0 2006.246.07:42:11.16#ibcon#about to read 4, iclass 22, count 0 2006.246.07:42:11.16#ibcon#read 4, iclass 22, count 0 2006.246.07:42:11.16#ibcon#about to read 5, iclass 22, count 0 2006.246.07:42:11.16#ibcon#read 5, iclass 22, count 0 2006.246.07:42:11.16#ibcon#about to read 6, iclass 22, count 0 2006.246.07:42:11.16#ibcon#read 6, iclass 22, count 0 2006.246.07:42:11.16#ibcon#end of sib2, iclass 22, count 0 2006.246.07:42:11.16#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:42:11.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:42:11.16#ibcon#[27=USB\r\n] 2006.246.07:42:11.16#ibcon#*before write, iclass 22, count 0 2006.246.07:42:11.16#ibcon#enter sib2, iclass 22, count 0 2006.246.07:42:11.16#ibcon#flushed, iclass 22, count 0 2006.246.07:42:11.16#ibcon#about to write, iclass 22, count 0 2006.246.07:42:11.16#ibcon#wrote, iclass 22, count 0 2006.246.07:42:11.16#ibcon#about to read 3, iclass 22, count 0 2006.246.07:42:11.19#ibcon#read 3, iclass 22, count 0 2006.246.07:42:11.19#ibcon#about to read 4, iclass 22, count 0 2006.246.07:42:11.19#ibcon#read 4, iclass 22, count 0 2006.246.07:42:11.19#ibcon#about to read 5, iclass 22, count 0 2006.246.07:42:11.19#ibcon#read 5, iclass 22, count 0 2006.246.07:42:11.19#ibcon#about to read 6, iclass 22, count 0 2006.246.07:42:11.19#ibcon#read 6, iclass 22, count 0 2006.246.07:42:11.19#ibcon#end of sib2, iclass 22, count 0 2006.246.07:42:11.19#ibcon#*after write, iclass 22, count 0 2006.246.07:42:11.19#ibcon#*before return 0, iclass 22, count 0 2006.246.07:42:11.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:42:11.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:42:11.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:42:11.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:42:11.19$vc4f8/vblo=3,656.99 2006.246.07:42:11.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.07:42:11.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.07:42:11.19#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:11.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:11.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:11.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:11.19#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:42:11.19#ibcon#first serial, iclass 24, count 0 2006.246.07:42:11.19#ibcon#enter sib2, iclass 24, count 0 2006.246.07:42:11.19#ibcon#flushed, iclass 24, count 0 2006.246.07:42:11.19#ibcon#about to write, iclass 24, count 0 2006.246.07:42:11.19#ibcon#wrote, iclass 24, count 0 2006.246.07:42:11.19#ibcon#about to read 3, iclass 24, count 0 2006.246.07:42:11.21#ibcon#read 3, iclass 24, count 0 2006.246.07:42:11.21#ibcon#about to read 4, iclass 24, count 0 2006.246.07:42:11.21#ibcon#read 4, iclass 24, count 0 2006.246.07:42:11.21#ibcon#about to read 5, iclass 24, count 0 2006.246.07:42:11.21#ibcon#read 5, iclass 24, count 0 2006.246.07:42:11.21#ibcon#about to read 6, iclass 24, count 0 2006.246.07:42:11.21#ibcon#read 6, iclass 24, count 0 2006.246.07:42:11.21#ibcon#end of sib2, iclass 24, count 0 2006.246.07:42:11.21#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:42:11.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:42:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:42:11.21#ibcon#*before write, iclass 24, count 0 2006.246.07:42:11.21#ibcon#enter sib2, iclass 24, count 0 2006.246.07:42:11.21#ibcon#flushed, iclass 24, count 0 2006.246.07:42:11.21#ibcon#about to write, iclass 24, count 0 2006.246.07:42:11.21#ibcon#wrote, iclass 24, count 0 2006.246.07:42:11.21#ibcon#about to read 3, iclass 24, count 0 2006.246.07:42:11.25#ibcon#read 3, iclass 24, count 0 2006.246.07:42:11.25#ibcon#about to read 4, iclass 24, count 0 2006.246.07:42:11.25#ibcon#read 4, iclass 24, count 0 2006.246.07:42:11.25#ibcon#about to read 5, iclass 24, count 0 2006.246.07:42:11.25#ibcon#read 5, iclass 24, count 0 2006.246.07:42:11.25#ibcon#about to read 6, iclass 24, count 0 2006.246.07:42:11.25#ibcon#read 6, iclass 24, count 0 2006.246.07:42:11.25#ibcon#end of sib2, iclass 24, count 0 2006.246.07:42:11.25#ibcon#*after write, iclass 24, count 0 2006.246.07:42:11.25#ibcon#*before return 0, iclass 24, count 0 2006.246.07:42:11.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:11.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:42:11.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:42:11.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:42:11.25$vc4f8/vb=3,4 2006.246.07:42:11.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.07:42:11.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.07:42:11.25#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:11.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:11.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:11.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:11.32#ibcon#enter wrdev, iclass 26, count 2 2006.246.07:42:11.32#ibcon#first serial, iclass 26, count 2 2006.246.07:42:11.32#ibcon#enter sib2, iclass 26, count 2 2006.246.07:42:11.32#ibcon#flushed, iclass 26, count 2 2006.246.07:42:11.32#ibcon#about to write, iclass 26, count 2 2006.246.07:42:11.32#ibcon#wrote, iclass 26, count 2 2006.246.07:42:11.32#ibcon#about to read 3, iclass 26, count 2 2006.246.07:42:11.33#ibcon#read 3, iclass 26, count 2 2006.246.07:42:11.33#ibcon#about to read 4, iclass 26, count 2 2006.246.07:42:11.33#ibcon#read 4, iclass 26, count 2 2006.246.07:42:11.33#ibcon#about to read 5, iclass 26, count 2 2006.246.07:42:11.33#ibcon#read 5, iclass 26, count 2 2006.246.07:42:11.33#ibcon#about to read 6, iclass 26, count 2 2006.246.07:42:11.33#ibcon#read 6, iclass 26, count 2 2006.246.07:42:11.33#ibcon#end of sib2, iclass 26, count 2 2006.246.07:42:11.33#ibcon#*mode == 0, iclass 26, count 2 2006.246.07:42:11.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.07:42:11.33#ibcon#[27=AT03-04\r\n] 2006.246.07:42:11.33#ibcon#*before write, iclass 26, count 2 2006.246.07:42:11.33#ibcon#enter sib2, iclass 26, count 2 2006.246.07:42:11.33#ibcon#flushed, iclass 26, count 2 2006.246.07:42:11.33#ibcon#about to write, iclass 26, count 2 2006.246.07:42:11.33#ibcon#wrote, iclass 26, count 2 2006.246.07:42:11.33#ibcon#about to read 3, iclass 26, count 2 2006.246.07:42:11.36#ibcon#read 3, iclass 26, count 2 2006.246.07:42:11.36#ibcon#about to read 4, iclass 26, count 2 2006.246.07:42:11.36#ibcon#read 4, iclass 26, count 2 2006.246.07:42:11.36#ibcon#about to read 5, iclass 26, count 2 2006.246.07:42:11.36#ibcon#read 5, iclass 26, count 2 2006.246.07:42:11.36#ibcon#about to read 6, iclass 26, count 2 2006.246.07:42:11.36#ibcon#read 6, iclass 26, count 2 2006.246.07:42:11.36#ibcon#end of sib2, iclass 26, count 2 2006.246.07:42:11.36#ibcon#*after write, iclass 26, count 2 2006.246.07:42:11.36#ibcon#*before return 0, iclass 26, count 2 2006.246.07:42:11.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:11.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:42:11.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.07:42:11.36#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:11.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:11.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:11.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:11.48#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:42:11.48#ibcon#first serial, iclass 26, count 0 2006.246.07:42:11.48#ibcon#enter sib2, iclass 26, count 0 2006.246.07:42:11.48#ibcon#flushed, iclass 26, count 0 2006.246.07:42:11.48#ibcon#about to write, iclass 26, count 0 2006.246.07:42:11.48#ibcon#wrote, iclass 26, count 0 2006.246.07:42:11.48#ibcon#about to read 3, iclass 26, count 0 2006.246.07:42:11.50#ibcon#read 3, iclass 26, count 0 2006.246.07:42:11.50#ibcon#about to read 4, iclass 26, count 0 2006.246.07:42:11.50#ibcon#read 4, iclass 26, count 0 2006.246.07:42:11.50#ibcon#about to read 5, iclass 26, count 0 2006.246.07:42:11.50#ibcon#read 5, iclass 26, count 0 2006.246.07:42:11.50#ibcon#about to read 6, iclass 26, count 0 2006.246.07:42:11.50#ibcon#read 6, iclass 26, count 0 2006.246.07:42:11.50#ibcon#end of sib2, iclass 26, count 0 2006.246.07:42:11.50#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:42:11.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:42:11.50#ibcon#[27=USB\r\n] 2006.246.07:42:11.50#ibcon#*before write, iclass 26, count 0 2006.246.07:42:11.50#ibcon#enter sib2, iclass 26, count 0 2006.246.07:42:11.50#ibcon#flushed, iclass 26, count 0 2006.246.07:42:11.50#ibcon#about to write, iclass 26, count 0 2006.246.07:42:11.50#ibcon#wrote, iclass 26, count 0 2006.246.07:42:11.50#ibcon#about to read 3, iclass 26, count 0 2006.246.07:42:11.53#ibcon#read 3, iclass 26, count 0 2006.246.07:42:11.53#ibcon#about to read 4, iclass 26, count 0 2006.246.07:42:11.53#ibcon#read 4, iclass 26, count 0 2006.246.07:42:11.53#ibcon#about to read 5, iclass 26, count 0 2006.246.07:42:11.53#ibcon#read 5, iclass 26, count 0 2006.246.07:42:11.53#ibcon#about to read 6, iclass 26, count 0 2006.246.07:42:11.53#ibcon#read 6, iclass 26, count 0 2006.246.07:42:11.53#ibcon#end of sib2, iclass 26, count 0 2006.246.07:42:11.53#ibcon#*after write, iclass 26, count 0 2006.246.07:42:11.53#ibcon#*before return 0, iclass 26, count 0 2006.246.07:42:11.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:11.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:42:11.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:42:11.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:42:11.53$vc4f8/vblo=4,712.99 2006.246.07:42:11.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.07:42:11.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.07:42:11.53#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:11.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:11.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:11.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:11.53#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:42:11.53#ibcon#first serial, iclass 28, count 0 2006.246.07:42:11.53#ibcon#enter sib2, iclass 28, count 0 2006.246.07:42:11.53#ibcon#flushed, iclass 28, count 0 2006.246.07:42:11.53#ibcon#about to write, iclass 28, count 0 2006.246.07:42:11.53#ibcon#wrote, iclass 28, count 0 2006.246.07:42:11.53#ibcon#about to read 3, iclass 28, count 0 2006.246.07:42:11.55#ibcon#read 3, iclass 28, count 0 2006.246.07:42:11.55#ibcon#about to read 4, iclass 28, count 0 2006.246.07:42:11.55#ibcon#read 4, iclass 28, count 0 2006.246.07:42:11.55#ibcon#about to read 5, iclass 28, count 0 2006.246.07:42:11.55#ibcon#read 5, iclass 28, count 0 2006.246.07:42:11.55#ibcon#about to read 6, iclass 28, count 0 2006.246.07:42:11.55#ibcon#read 6, iclass 28, count 0 2006.246.07:42:11.55#ibcon#end of sib2, iclass 28, count 0 2006.246.07:42:11.55#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:42:11.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:42:11.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:42:11.55#ibcon#*before write, iclass 28, count 0 2006.246.07:42:11.55#ibcon#enter sib2, iclass 28, count 0 2006.246.07:42:11.55#ibcon#flushed, iclass 28, count 0 2006.246.07:42:11.55#ibcon#about to write, iclass 28, count 0 2006.246.07:42:11.55#ibcon#wrote, iclass 28, count 0 2006.246.07:42:11.55#ibcon#about to read 3, iclass 28, count 0 2006.246.07:42:11.59#ibcon#read 3, iclass 28, count 0 2006.246.07:42:11.59#ibcon#about to read 4, iclass 28, count 0 2006.246.07:42:11.59#ibcon#read 4, iclass 28, count 0 2006.246.07:42:11.59#ibcon#about to read 5, iclass 28, count 0 2006.246.07:42:11.59#ibcon#read 5, iclass 28, count 0 2006.246.07:42:11.59#ibcon#about to read 6, iclass 28, count 0 2006.246.07:42:11.59#ibcon#read 6, iclass 28, count 0 2006.246.07:42:11.59#ibcon#end of sib2, iclass 28, count 0 2006.246.07:42:11.59#ibcon#*after write, iclass 28, count 0 2006.246.07:42:11.59#ibcon#*before return 0, iclass 28, count 0 2006.246.07:42:11.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:11.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:42:11.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:42:11.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:42:11.59$vc4f8/vb=4,4 2006.246.07:42:11.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.07:42:11.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.07:42:11.59#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:11.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:11.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:11.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:11.65#ibcon#enter wrdev, iclass 30, count 2 2006.246.07:42:11.65#ibcon#first serial, iclass 30, count 2 2006.246.07:42:11.65#ibcon#enter sib2, iclass 30, count 2 2006.246.07:42:11.65#ibcon#flushed, iclass 30, count 2 2006.246.07:42:11.65#ibcon#about to write, iclass 30, count 2 2006.246.07:42:11.65#ibcon#wrote, iclass 30, count 2 2006.246.07:42:11.65#ibcon#about to read 3, iclass 30, count 2 2006.246.07:42:11.67#ibcon#read 3, iclass 30, count 2 2006.246.07:42:11.67#ibcon#about to read 4, iclass 30, count 2 2006.246.07:42:11.67#ibcon#read 4, iclass 30, count 2 2006.246.07:42:11.67#ibcon#about to read 5, iclass 30, count 2 2006.246.07:42:11.67#ibcon#read 5, iclass 30, count 2 2006.246.07:42:11.67#ibcon#about to read 6, iclass 30, count 2 2006.246.07:42:11.67#ibcon#read 6, iclass 30, count 2 2006.246.07:42:11.67#ibcon#end of sib2, iclass 30, count 2 2006.246.07:42:11.67#ibcon#*mode == 0, iclass 30, count 2 2006.246.07:42:11.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.07:42:11.67#ibcon#[27=AT04-04\r\n] 2006.246.07:42:11.67#ibcon#*before write, iclass 30, count 2 2006.246.07:42:11.67#ibcon#enter sib2, iclass 30, count 2 2006.246.07:42:11.67#ibcon#flushed, iclass 30, count 2 2006.246.07:42:11.67#ibcon#about to write, iclass 30, count 2 2006.246.07:42:11.67#ibcon#wrote, iclass 30, count 2 2006.246.07:42:11.67#ibcon#about to read 3, iclass 30, count 2 2006.246.07:42:11.70#ibcon#read 3, iclass 30, count 2 2006.246.07:42:11.70#ibcon#about to read 4, iclass 30, count 2 2006.246.07:42:11.70#ibcon#read 4, iclass 30, count 2 2006.246.07:42:11.70#ibcon#about to read 5, iclass 30, count 2 2006.246.07:42:11.70#ibcon#read 5, iclass 30, count 2 2006.246.07:42:11.70#ibcon#about to read 6, iclass 30, count 2 2006.246.07:42:11.70#ibcon#read 6, iclass 30, count 2 2006.246.07:42:11.70#ibcon#end of sib2, iclass 30, count 2 2006.246.07:42:11.70#ibcon#*after write, iclass 30, count 2 2006.246.07:42:11.70#ibcon#*before return 0, iclass 30, count 2 2006.246.07:42:11.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:11.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:42:11.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.07:42:11.70#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:11.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:11.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:11.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:11.82#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:42:11.82#ibcon#first serial, iclass 30, count 0 2006.246.07:42:11.82#ibcon#enter sib2, iclass 30, count 0 2006.246.07:42:11.82#ibcon#flushed, iclass 30, count 0 2006.246.07:42:11.82#ibcon#about to write, iclass 30, count 0 2006.246.07:42:11.82#ibcon#wrote, iclass 30, count 0 2006.246.07:42:11.82#ibcon#about to read 3, iclass 30, count 0 2006.246.07:42:11.84#ibcon#read 3, iclass 30, count 0 2006.246.07:42:11.84#ibcon#about to read 4, iclass 30, count 0 2006.246.07:42:11.84#ibcon#read 4, iclass 30, count 0 2006.246.07:42:11.84#ibcon#about to read 5, iclass 30, count 0 2006.246.07:42:11.84#ibcon#read 5, iclass 30, count 0 2006.246.07:42:11.84#ibcon#about to read 6, iclass 30, count 0 2006.246.07:42:11.84#ibcon#read 6, iclass 30, count 0 2006.246.07:42:11.84#ibcon#end of sib2, iclass 30, count 0 2006.246.07:42:11.84#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:42:11.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:42:11.84#ibcon#[27=USB\r\n] 2006.246.07:42:11.84#ibcon#*before write, iclass 30, count 0 2006.246.07:42:11.84#ibcon#enter sib2, iclass 30, count 0 2006.246.07:42:11.84#ibcon#flushed, iclass 30, count 0 2006.246.07:42:11.84#ibcon#about to write, iclass 30, count 0 2006.246.07:42:11.84#ibcon#wrote, iclass 30, count 0 2006.246.07:42:11.84#ibcon#about to read 3, iclass 30, count 0 2006.246.07:42:11.87#ibcon#read 3, iclass 30, count 0 2006.246.07:42:11.87#ibcon#about to read 4, iclass 30, count 0 2006.246.07:42:11.87#ibcon#read 4, iclass 30, count 0 2006.246.07:42:11.87#ibcon#about to read 5, iclass 30, count 0 2006.246.07:42:11.87#ibcon#read 5, iclass 30, count 0 2006.246.07:42:11.87#ibcon#about to read 6, iclass 30, count 0 2006.246.07:42:11.87#ibcon#read 6, iclass 30, count 0 2006.246.07:42:11.87#ibcon#end of sib2, iclass 30, count 0 2006.246.07:42:11.87#ibcon#*after write, iclass 30, count 0 2006.246.07:42:11.87#ibcon#*before return 0, iclass 30, count 0 2006.246.07:42:11.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:11.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:42:11.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:42:11.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:42:11.87$vc4f8/vblo=5,744.99 2006.246.07:42:11.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.07:42:11.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.07:42:11.87#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:11.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:11.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:11.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:11.87#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:42:11.87#ibcon#first serial, iclass 32, count 0 2006.246.07:42:11.87#ibcon#enter sib2, iclass 32, count 0 2006.246.07:42:11.87#ibcon#flushed, iclass 32, count 0 2006.246.07:42:11.87#ibcon#about to write, iclass 32, count 0 2006.246.07:42:11.87#ibcon#wrote, iclass 32, count 0 2006.246.07:42:11.87#ibcon#about to read 3, iclass 32, count 0 2006.246.07:42:11.89#ibcon#read 3, iclass 32, count 0 2006.246.07:42:11.89#ibcon#about to read 4, iclass 32, count 0 2006.246.07:42:11.89#ibcon#read 4, iclass 32, count 0 2006.246.07:42:11.89#ibcon#about to read 5, iclass 32, count 0 2006.246.07:42:11.89#ibcon#read 5, iclass 32, count 0 2006.246.07:42:11.89#ibcon#about to read 6, iclass 32, count 0 2006.246.07:42:11.89#ibcon#read 6, iclass 32, count 0 2006.246.07:42:11.89#ibcon#end of sib2, iclass 32, count 0 2006.246.07:42:11.89#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:42:11.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:42:11.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:42:11.89#ibcon#*before write, iclass 32, count 0 2006.246.07:42:11.89#ibcon#enter sib2, iclass 32, count 0 2006.246.07:42:11.89#ibcon#flushed, iclass 32, count 0 2006.246.07:42:11.89#ibcon#about to write, iclass 32, count 0 2006.246.07:42:11.89#ibcon#wrote, iclass 32, count 0 2006.246.07:42:11.89#ibcon#about to read 3, iclass 32, count 0 2006.246.07:42:11.93#ibcon#read 3, iclass 32, count 0 2006.246.07:42:11.93#ibcon#about to read 4, iclass 32, count 0 2006.246.07:42:11.93#ibcon#read 4, iclass 32, count 0 2006.246.07:42:11.93#ibcon#about to read 5, iclass 32, count 0 2006.246.07:42:11.93#ibcon#read 5, iclass 32, count 0 2006.246.07:42:11.93#ibcon#about to read 6, iclass 32, count 0 2006.246.07:42:11.93#ibcon#read 6, iclass 32, count 0 2006.246.07:42:11.93#ibcon#end of sib2, iclass 32, count 0 2006.246.07:42:11.93#ibcon#*after write, iclass 32, count 0 2006.246.07:42:11.93#ibcon#*before return 0, iclass 32, count 0 2006.246.07:42:11.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:11.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:42:11.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:42:11.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:42:11.93$vc4f8/vb=5,3 2006.246.07:42:11.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.07:42:11.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.07:42:11.93#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:11.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:11.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:11.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:11.99#ibcon#enter wrdev, iclass 34, count 2 2006.246.07:42:11.99#ibcon#first serial, iclass 34, count 2 2006.246.07:42:11.99#ibcon#enter sib2, iclass 34, count 2 2006.246.07:42:11.99#ibcon#flushed, iclass 34, count 2 2006.246.07:42:11.99#ibcon#about to write, iclass 34, count 2 2006.246.07:42:11.99#ibcon#wrote, iclass 34, count 2 2006.246.07:42:11.99#ibcon#about to read 3, iclass 34, count 2 2006.246.07:42:12.01#ibcon#read 3, iclass 34, count 2 2006.246.07:42:12.01#ibcon#about to read 4, iclass 34, count 2 2006.246.07:42:12.01#ibcon#read 4, iclass 34, count 2 2006.246.07:42:12.01#ibcon#about to read 5, iclass 34, count 2 2006.246.07:42:12.01#ibcon#read 5, iclass 34, count 2 2006.246.07:42:12.01#ibcon#about to read 6, iclass 34, count 2 2006.246.07:42:12.01#ibcon#read 6, iclass 34, count 2 2006.246.07:42:12.01#ibcon#end of sib2, iclass 34, count 2 2006.246.07:42:12.01#ibcon#*mode == 0, iclass 34, count 2 2006.246.07:42:12.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.07:42:12.01#ibcon#[27=AT05-03\r\n] 2006.246.07:42:12.01#ibcon#*before write, iclass 34, count 2 2006.246.07:42:12.01#ibcon#enter sib2, iclass 34, count 2 2006.246.07:42:12.01#ibcon#flushed, iclass 34, count 2 2006.246.07:42:12.01#ibcon#about to write, iclass 34, count 2 2006.246.07:42:12.01#ibcon#wrote, iclass 34, count 2 2006.246.07:42:12.01#ibcon#about to read 3, iclass 34, count 2 2006.246.07:42:12.04#ibcon#read 3, iclass 34, count 2 2006.246.07:42:12.04#ibcon#about to read 4, iclass 34, count 2 2006.246.07:42:12.04#ibcon#read 4, iclass 34, count 2 2006.246.07:42:12.04#ibcon#about to read 5, iclass 34, count 2 2006.246.07:42:12.04#ibcon#read 5, iclass 34, count 2 2006.246.07:42:12.04#ibcon#about to read 6, iclass 34, count 2 2006.246.07:42:12.04#ibcon#read 6, iclass 34, count 2 2006.246.07:42:12.04#ibcon#end of sib2, iclass 34, count 2 2006.246.07:42:12.04#ibcon#*after write, iclass 34, count 2 2006.246.07:42:12.04#ibcon#*before return 0, iclass 34, count 2 2006.246.07:42:12.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:12.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:42:12.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.07:42:12.04#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:12.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:12.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:12.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:12.16#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:42:12.16#ibcon#first serial, iclass 34, count 0 2006.246.07:42:12.16#ibcon#enter sib2, iclass 34, count 0 2006.246.07:42:12.16#ibcon#flushed, iclass 34, count 0 2006.246.07:42:12.16#ibcon#about to write, iclass 34, count 0 2006.246.07:42:12.16#ibcon#wrote, iclass 34, count 0 2006.246.07:42:12.16#ibcon#about to read 3, iclass 34, count 0 2006.246.07:42:12.18#ibcon#read 3, iclass 34, count 0 2006.246.07:42:12.18#ibcon#about to read 4, iclass 34, count 0 2006.246.07:42:12.18#ibcon#read 4, iclass 34, count 0 2006.246.07:42:12.18#ibcon#about to read 5, iclass 34, count 0 2006.246.07:42:12.18#ibcon#read 5, iclass 34, count 0 2006.246.07:42:12.18#ibcon#about to read 6, iclass 34, count 0 2006.246.07:42:12.18#ibcon#read 6, iclass 34, count 0 2006.246.07:42:12.18#ibcon#end of sib2, iclass 34, count 0 2006.246.07:42:12.18#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:42:12.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:42:12.18#ibcon#[27=USB\r\n] 2006.246.07:42:12.18#ibcon#*before write, iclass 34, count 0 2006.246.07:42:12.18#ibcon#enter sib2, iclass 34, count 0 2006.246.07:42:12.18#ibcon#flushed, iclass 34, count 0 2006.246.07:42:12.18#ibcon#about to write, iclass 34, count 0 2006.246.07:42:12.18#ibcon#wrote, iclass 34, count 0 2006.246.07:42:12.18#ibcon#about to read 3, iclass 34, count 0 2006.246.07:42:12.21#ibcon#read 3, iclass 34, count 0 2006.246.07:42:12.21#ibcon#about to read 4, iclass 34, count 0 2006.246.07:42:12.21#ibcon#read 4, iclass 34, count 0 2006.246.07:42:12.21#ibcon#about to read 5, iclass 34, count 0 2006.246.07:42:12.21#ibcon#read 5, iclass 34, count 0 2006.246.07:42:12.21#ibcon#about to read 6, iclass 34, count 0 2006.246.07:42:12.21#ibcon#read 6, iclass 34, count 0 2006.246.07:42:12.21#ibcon#end of sib2, iclass 34, count 0 2006.246.07:42:12.21#ibcon#*after write, iclass 34, count 0 2006.246.07:42:12.21#ibcon#*before return 0, iclass 34, count 0 2006.246.07:42:12.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:12.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:42:12.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:42:12.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:42:12.21$vc4f8/vblo=6,752.99 2006.246.07:42:12.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.07:42:12.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.07:42:12.21#ibcon#ireg 17 cls_cnt 0 2006.246.07:42:12.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:12.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:12.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:12.21#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:42:12.21#ibcon#first serial, iclass 36, count 0 2006.246.07:42:12.21#ibcon#enter sib2, iclass 36, count 0 2006.246.07:42:12.21#ibcon#flushed, iclass 36, count 0 2006.246.07:42:12.21#ibcon#about to write, iclass 36, count 0 2006.246.07:42:12.21#ibcon#wrote, iclass 36, count 0 2006.246.07:42:12.21#ibcon#about to read 3, iclass 36, count 0 2006.246.07:42:12.23#ibcon#read 3, iclass 36, count 0 2006.246.07:42:12.23#ibcon#about to read 4, iclass 36, count 0 2006.246.07:42:12.23#ibcon#read 4, iclass 36, count 0 2006.246.07:42:12.23#ibcon#about to read 5, iclass 36, count 0 2006.246.07:42:12.23#ibcon#read 5, iclass 36, count 0 2006.246.07:42:12.23#ibcon#about to read 6, iclass 36, count 0 2006.246.07:42:12.23#ibcon#read 6, iclass 36, count 0 2006.246.07:42:12.23#ibcon#end of sib2, iclass 36, count 0 2006.246.07:42:12.23#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:42:12.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:42:12.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:42:12.23#ibcon#*before write, iclass 36, count 0 2006.246.07:42:12.23#ibcon#enter sib2, iclass 36, count 0 2006.246.07:42:12.23#ibcon#flushed, iclass 36, count 0 2006.246.07:42:12.23#ibcon#about to write, iclass 36, count 0 2006.246.07:42:12.23#ibcon#wrote, iclass 36, count 0 2006.246.07:42:12.23#ibcon#about to read 3, iclass 36, count 0 2006.246.07:42:12.27#ibcon#read 3, iclass 36, count 0 2006.246.07:42:12.27#ibcon#about to read 4, iclass 36, count 0 2006.246.07:42:12.27#ibcon#read 4, iclass 36, count 0 2006.246.07:42:12.27#ibcon#about to read 5, iclass 36, count 0 2006.246.07:42:12.27#ibcon#read 5, iclass 36, count 0 2006.246.07:42:12.27#ibcon#about to read 6, iclass 36, count 0 2006.246.07:42:12.27#ibcon#read 6, iclass 36, count 0 2006.246.07:42:12.27#ibcon#end of sib2, iclass 36, count 0 2006.246.07:42:12.27#ibcon#*after write, iclass 36, count 0 2006.246.07:42:12.27#ibcon#*before return 0, iclass 36, count 0 2006.246.07:42:12.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:12.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:42:12.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:42:12.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:42:12.27$vc4f8/vb=6,3 2006.246.07:42:12.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.07:42:12.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.07:42:12.27#ibcon#ireg 11 cls_cnt 2 2006.246.07:42:12.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:12.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:12.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:12.33#ibcon#enter wrdev, iclass 38, count 2 2006.246.07:42:12.33#ibcon#first serial, iclass 38, count 2 2006.246.07:42:12.33#ibcon#enter sib2, iclass 38, count 2 2006.246.07:42:12.33#ibcon#flushed, iclass 38, count 2 2006.246.07:42:12.33#ibcon#about to write, iclass 38, count 2 2006.246.07:42:12.33#ibcon#wrote, iclass 38, count 2 2006.246.07:42:12.33#ibcon#about to read 3, iclass 38, count 2 2006.246.07:42:12.35#ibcon#read 3, iclass 38, count 2 2006.246.07:42:12.35#ibcon#about to read 4, iclass 38, count 2 2006.246.07:42:12.35#ibcon#read 4, iclass 38, count 2 2006.246.07:42:12.35#ibcon#about to read 5, iclass 38, count 2 2006.246.07:42:12.35#ibcon#read 5, iclass 38, count 2 2006.246.07:42:12.35#ibcon#about to read 6, iclass 38, count 2 2006.246.07:42:12.35#ibcon#read 6, iclass 38, count 2 2006.246.07:42:12.35#ibcon#end of sib2, iclass 38, count 2 2006.246.07:42:12.35#ibcon#*mode == 0, iclass 38, count 2 2006.246.07:42:12.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.07:42:12.35#ibcon#[27=AT06-03\r\n] 2006.246.07:42:12.35#ibcon#*before write, iclass 38, count 2 2006.246.07:42:12.35#ibcon#enter sib2, iclass 38, count 2 2006.246.07:42:12.35#ibcon#flushed, iclass 38, count 2 2006.246.07:42:12.35#ibcon#about to write, iclass 38, count 2 2006.246.07:42:12.35#ibcon#wrote, iclass 38, count 2 2006.246.07:42:12.35#ibcon#about to read 3, iclass 38, count 2 2006.246.07:42:12.38#ibcon#read 3, iclass 38, count 2 2006.246.07:42:12.38#ibcon#about to read 4, iclass 38, count 2 2006.246.07:42:12.38#ibcon#read 4, iclass 38, count 2 2006.246.07:42:12.38#ibcon#about to read 5, iclass 38, count 2 2006.246.07:42:12.38#ibcon#read 5, iclass 38, count 2 2006.246.07:42:12.38#ibcon#about to read 6, iclass 38, count 2 2006.246.07:42:12.38#ibcon#read 6, iclass 38, count 2 2006.246.07:42:12.38#ibcon#end of sib2, iclass 38, count 2 2006.246.07:42:12.38#ibcon#*after write, iclass 38, count 2 2006.246.07:42:12.38#ibcon#*before return 0, iclass 38, count 2 2006.246.07:42:12.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:12.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:42:12.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.07:42:12.38#ibcon#ireg 7 cls_cnt 0 2006.246.07:42:12.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:12.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:12.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:12.50#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:42:12.50#ibcon#first serial, iclass 38, count 0 2006.246.07:42:12.50#ibcon#enter sib2, iclass 38, count 0 2006.246.07:42:12.50#ibcon#flushed, iclass 38, count 0 2006.246.07:42:12.50#ibcon#about to write, iclass 38, count 0 2006.246.07:42:12.50#ibcon#wrote, iclass 38, count 0 2006.246.07:42:12.50#ibcon#about to read 3, iclass 38, count 0 2006.246.07:42:12.52#ibcon#read 3, iclass 38, count 0 2006.246.07:42:12.52#ibcon#about to read 4, iclass 38, count 0 2006.246.07:42:12.52#ibcon#read 4, iclass 38, count 0 2006.246.07:42:12.52#ibcon#about to read 5, iclass 38, count 0 2006.246.07:42:12.52#ibcon#read 5, iclass 38, count 0 2006.246.07:42:12.52#ibcon#about to read 6, iclass 38, count 0 2006.246.07:42:12.52#ibcon#read 6, iclass 38, count 0 2006.246.07:42:12.52#ibcon#end of sib2, iclass 38, count 0 2006.246.07:42:12.52#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:42:12.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:42:12.52#ibcon#[27=USB\r\n] 2006.246.07:42:12.52#ibcon#*before write, iclass 38, count 0 2006.246.07:42:12.52#ibcon#enter sib2, iclass 38, count 0 2006.246.07:42:12.52#ibcon#flushed, iclass 38, count 0 2006.246.07:42:12.52#ibcon#about to write, iclass 38, count 0 2006.246.07:42:12.52#ibcon#wrote, iclass 38, count 0 2006.246.07:42:12.52#ibcon#about to read 3, iclass 38, count 0 2006.246.07:42:12.55#ibcon#read 3, iclass 38, count 0 2006.246.07:42:12.55#ibcon#about to read 4, iclass 38, count 0 2006.246.07:42:12.55#ibcon#read 4, iclass 38, count 0 2006.246.07:42:12.55#ibcon#about to read 5, iclass 38, count 0 2006.246.07:42:12.55#ibcon#read 5, iclass 38, count 0 2006.246.07:42:12.55#ibcon#about to read 6, iclass 38, count 0 2006.246.07:42:12.55#ibcon#read 6, iclass 38, count 0 2006.246.07:42:12.55#ibcon#end of sib2, iclass 38, count 0 2006.246.07:42:12.55#ibcon#*after write, iclass 38, count 0 2006.246.07:42:12.55#ibcon#*before return 0, iclass 38, count 0 2006.246.07:42:12.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:12.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:42:12.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:42:12.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:42:12.55$vc4f8/vabw=wide 2006.246.07:42:12.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:42:12.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:42:12.55#ibcon#ireg 8 cls_cnt 0 2006.246.07:42:12.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:12.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:12.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:12.55#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:42:12.55#ibcon#first serial, iclass 40, count 0 2006.246.07:42:12.55#ibcon#enter sib2, iclass 40, count 0 2006.246.07:42:12.55#ibcon#flushed, iclass 40, count 0 2006.246.07:42:12.55#ibcon#about to write, iclass 40, count 0 2006.246.07:42:12.55#ibcon#wrote, iclass 40, count 0 2006.246.07:42:12.55#ibcon#about to read 3, iclass 40, count 0 2006.246.07:42:12.57#ibcon#read 3, iclass 40, count 0 2006.246.07:42:12.57#ibcon#about to read 4, iclass 40, count 0 2006.246.07:42:12.57#ibcon#read 4, iclass 40, count 0 2006.246.07:42:12.57#ibcon#about to read 5, iclass 40, count 0 2006.246.07:42:12.57#ibcon#read 5, iclass 40, count 0 2006.246.07:42:12.57#ibcon#about to read 6, iclass 40, count 0 2006.246.07:42:12.57#ibcon#read 6, iclass 40, count 0 2006.246.07:42:12.57#ibcon#end of sib2, iclass 40, count 0 2006.246.07:42:12.57#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:42:12.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:42:12.57#ibcon#[25=BW32\r\n] 2006.246.07:42:12.57#ibcon#*before write, iclass 40, count 0 2006.246.07:42:12.57#ibcon#enter sib2, iclass 40, count 0 2006.246.07:42:12.57#ibcon#flushed, iclass 40, count 0 2006.246.07:42:12.57#ibcon#about to write, iclass 40, count 0 2006.246.07:42:12.57#ibcon#wrote, iclass 40, count 0 2006.246.07:42:12.57#ibcon#about to read 3, iclass 40, count 0 2006.246.07:42:12.60#ibcon#read 3, iclass 40, count 0 2006.246.07:42:12.60#ibcon#about to read 4, iclass 40, count 0 2006.246.07:42:12.60#ibcon#read 4, iclass 40, count 0 2006.246.07:42:12.60#ibcon#about to read 5, iclass 40, count 0 2006.246.07:42:12.60#ibcon#read 5, iclass 40, count 0 2006.246.07:42:12.60#ibcon#about to read 6, iclass 40, count 0 2006.246.07:42:12.60#ibcon#read 6, iclass 40, count 0 2006.246.07:42:12.60#ibcon#end of sib2, iclass 40, count 0 2006.246.07:42:12.60#ibcon#*after write, iclass 40, count 0 2006.246.07:42:12.60#ibcon#*before return 0, iclass 40, count 0 2006.246.07:42:12.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:12.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:42:12.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:42:12.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:42:12.60$vc4f8/vbbw=wide 2006.246.07:42:12.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.07:42:12.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.07:42:12.60#ibcon#ireg 8 cls_cnt 0 2006.246.07:42:12.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:42:12.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:42:12.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:42:12.67#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:42:12.67#ibcon#first serial, iclass 4, count 0 2006.246.07:42:12.67#ibcon#enter sib2, iclass 4, count 0 2006.246.07:42:12.67#ibcon#flushed, iclass 4, count 0 2006.246.07:42:12.67#ibcon#about to write, iclass 4, count 0 2006.246.07:42:12.67#ibcon#wrote, iclass 4, count 0 2006.246.07:42:12.67#ibcon#about to read 3, iclass 4, count 0 2006.246.07:42:12.69#ibcon#read 3, iclass 4, count 0 2006.246.07:42:12.69#ibcon#about to read 4, iclass 4, count 0 2006.246.07:42:12.69#ibcon#read 4, iclass 4, count 0 2006.246.07:42:12.69#ibcon#about to read 5, iclass 4, count 0 2006.246.07:42:12.69#ibcon#read 5, iclass 4, count 0 2006.246.07:42:12.69#ibcon#about to read 6, iclass 4, count 0 2006.246.07:42:12.69#ibcon#read 6, iclass 4, count 0 2006.246.07:42:12.69#ibcon#end of sib2, iclass 4, count 0 2006.246.07:42:12.69#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:42:12.69#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:42:12.69#ibcon#[27=BW32\r\n] 2006.246.07:42:12.69#ibcon#*before write, iclass 4, count 0 2006.246.07:42:12.69#ibcon#enter sib2, iclass 4, count 0 2006.246.07:42:12.69#ibcon#flushed, iclass 4, count 0 2006.246.07:42:12.69#ibcon#about to write, iclass 4, count 0 2006.246.07:42:12.69#ibcon#wrote, iclass 4, count 0 2006.246.07:42:12.69#ibcon#about to read 3, iclass 4, count 0 2006.246.07:42:12.72#ibcon#read 3, iclass 4, count 0 2006.246.07:42:12.72#ibcon#about to read 4, iclass 4, count 0 2006.246.07:42:12.72#ibcon#read 4, iclass 4, count 0 2006.246.07:42:12.72#ibcon#about to read 5, iclass 4, count 0 2006.246.07:42:12.72#ibcon#read 5, iclass 4, count 0 2006.246.07:42:12.72#ibcon#about to read 6, iclass 4, count 0 2006.246.07:42:12.72#ibcon#read 6, iclass 4, count 0 2006.246.07:42:12.72#ibcon#end of sib2, iclass 4, count 0 2006.246.07:42:12.72#ibcon#*after write, iclass 4, count 0 2006.246.07:42:12.72#ibcon#*before return 0, iclass 4, count 0 2006.246.07:42:12.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:42:12.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:42:12.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:42:12.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:42:12.72$4f8m12a/ifd4f 2006.246.07:42:12.72$ifd4f/lo= 2006.246.07:42:12.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:42:12.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:42:12.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:42:12.72$ifd4f/patch= 2006.246.07:42:12.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:42:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:42:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:42:12.73$4f8m12a/"form=m,16.000,1:2 2006.246.07:42:12.73$4f8m12a/"tpicd 2006.246.07:42:12.73$4f8m12a/echo=off 2006.246.07:42:12.73$4f8m12a/xlog=off 2006.246.07:42:12.73:!2006.246.07:42:40 2006.246.07:42:21.14#trakl#Source acquired 2006.246.07:42:21.14#flagr#flagr/antenna,acquired 2006.246.07:42:40.01:preob 2006.246.07:42:41.14/onsource/TRACKING 2006.246.07:42:41.14:!2006.246.07:42:50 2006.246.07:42:50.00:data_valid=on 2006.246.07:42:50.00:midob 2006.246.07:42:50.14/onsource/TRACKING 2006.246.07:42:50.14/wx/26.73,1005.6,73 2006.246.07:42:50.25/cable/+6.4147E-03 2006.246.07:42:51.34/va/01,08,usb,yes,31,33 2006.246.07:42:51.34/va/02,07,usb,yes,31,33 2006.246.07:42:51.34/va/03,06,usb,yes,33,33 2006.246.07:42:51.34/va/04,07,usb,yes,32,35 2006.246.07:42:51.34/va/05,07,usb,yes,34,36 2006.246.07:42:51.34/va/06,07,usb,yes,30,30 2006.246.07:42:51.34/va/07,07,usb,yes,30,30 2006.246.07:42:51.34/va/08,08,usb,yes,26,26 2006.246.07:42:51.57/valo/01,532.99,yes,locked 2006.246.07:42:51.57/valo/02,572.99,yes,locked 2006.246.07:42:51.57/valo/03,672.99,yes,locked 2006.246.07:42:51.57/valo/04,832.99,yes,locked 2006.246.07:42:51.57/valo/05,652.99,yes,locked 2006.246.07:42:51.57/valo/06,772.99,yes,locked 2006.246.07:42:51.57/valo/07,832.99,yes,locked 2006.246.07:42:51.57/valo/08,852.99,yes,locked 2006.246.07:42:52.66/vb/01,04,usb,yes,31,29 2006.246.07:42:52.66/vb/02,04,usb,yes,32,34 2006.246.07:42:52.66/vb/03,04,usb,yes,29,32 2006.246.07:42:52.66/vb/04,04,usb,yes,29,30 2006.246.07:42:52.66/vb/05,03,usb,yes,35,40 2006.246.07:42:52.66/vb/06,03,usb,yes,36,39 2006.246.07:42:52.66/vb/07,04,usb,yes,31,31 2006.246.07:42:52.66/vb/08,03,usb,yes,36,39 2006.246.07:42:52.90/vblo/01,632.99,yes,locked 2006.246.07:42:52.90/vblo/02,640.99,yes,locked 2006.246.07:42:52.90/vblo/03,656.99,yes,locked 2006.246.07:42:52.90/vblo/04,712.99,yes,locked 2006.246.07:42:52.90/vblo/05,744.99,yes,locked 2006.246.07:42:52.90/vblo/06,752.99,yes,locked 2006.246.07:42:52.90/vblo/07,734.99,yes,locked 2006.246.07:42:52.90/vblo/08,744.99,yes,locked 2006.246.07:42:53.05/vabw/8 2006.246.07:42:53.20/vbbw/8 2006.246.07:42:53.37/xfe/off,on,13.2 2006.246.07:42:53.74/ifatt/23,28,28,28 2006.246.07:42:54.07/fmout-gps/S +4.36E-07 2006.246.07:42:54.12:!2006.246.07:43:50 2006.246.07:43:50.00:data_valid=off 2006.246.07:43:50.01:postob 2006.246.07:43:50.18/cable/+6.4127E-03 2006.246.07:43:50.19/wx/26.73,1005.6,74 2006.246.07:43:51.07/fmout-gps/S +4.35E-07 2006.246.07:43:51.08:scan_name=246-0744,k06246,60 2006.246.07:43:51.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.246.07:43:52.14#flagr#flagr/antenna,new-source 2006.246.07:43:52.15:checkk5 2006.246.07:43:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:43:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:43:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:43:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:43:54.01/chk_obsdata//k5ts1/T2460742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:43:54.38/chk_obsdata//k5ts2/T2460742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:43:54.74/chk_obsdata//k5ts3/T2460742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:43:55.11/chk_obsdata//k5ts4/T2460742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:43:55.85/k5log//k5ts1_log_newline 2006.246.07:43:56.55/k5log//k5ts2_log_newline 2006.246.07:43:57.24/k5log//k5ts3_log_newline 2006.246.07:43:57.94/k5log//k5ts4_log_newline 2006.246.07:43:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:43:57.97:4f8m12a=1 2006.246.07:43:57.97$4f8m12a/echo=on 2006.246.07:43:57.97$4f8m12a/pcalon 2006.246.07:43:57.97$pcalon/"no phase cal control is implemented here 2006.246.07:43:57.97$4f8m12a/"tpicd=stop 2006.246.07:43:57.97$4f8m12a/vc4f8 2006.246.07:43:57.97$vc4f8/valo=1,532.99 2006.246.07:43:57.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.07:43:57.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.07:43:57.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:57.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:43:57.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:43:57.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:43:57.97#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:43:57.97#ibcon#first serial, iclass 13, count 0 2006.246.07:43:57.97#ibcon#enter sib2, iclass 13, count 0 2006.246.07:43:57.97#ibcon#flushed, iclass 13, count 0 2006.246.07:43:57.97#ibcon#about to write, iclass 13, count 0 2006.246.07:43:57.97#ibcon#wrote, iclass 13, count 0 2006.246.07:43:57.97#ibcon#about to read 3, iclass 13, count 0 2006.246.07:43:57.98#ibcon#read 3, iclass 13, count 0 2006.246.07:43:57.98#ibcon#about to read 4, iclass 13, count 0 2006.246.07:43:57.98#ibcon#read 4, iclass 13, count 0 2006.246.07:43:57.98#ibcon#about to read 5, iclass 13, count 0 2006.246.07:43:57.98#ibcon#read 5, iclass 13, count 0 2006.246.07:43:57.98#ibcon#about to read 6, iclass 13, count 0 2006.246.07:43:57.98#ibcon#read 6, iclass 13, count 0 2006.246.07:43:57.98#ibcon#end of sib2, iclass 13, count 0 2006.246.07:43:57.98#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:43:57.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:43:57.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:43:57.98#ibcon#*before write, iclass 13, count 0 2006.246.07:43:57.98#ibcon#enter sib2, iclass 13, count 0 2006.246.07:43:57.98#ibcon#flushed, iclass 13, count 0 2006.246.07:43:57.98#ibcon#about to write, iclass 13, count 0 2006.246.07:43:57.98#ibcon#wrote, iclass 13, count 0 2006.246.07:43:57.98#ibcon#about to read 3, iclass 13, count 0 2006.246.07:43:58.03#ibcon#read 3, iclass 13, count 0 2006.246.07:43:58.03#ibcon#about to read 4, iclass 13, count 0 2006.246.07:43:58.03#ibcon#read 4, iclass 13, count 0 2006.246.07:43:58.03#ibcon#about to read 5, iclass 13, count 0 2006.246.07:43:58.03#ibcon#read 5, iclass 13, count 0 2006.246.07:43:58.03#ibcon#about to read 6, iclass 13, count 0 2006.246.07:43:58.03#ibcon#read 6, iclass 13, count 0 2006.246.07:43:58.03#ibcon#end of sib2, iclass 13, count 0 2006.246.07:43:58.03#ibcon#*after write, iclass 13, count 0 2006.246.07:43:58.03#ibcon#*before return 0, iclass 13, count 0 2006.246.07:43:58.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:43:58.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:43:58.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:43:58.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:43:58.03$vc4f8/va=1,8 2006.246.07:43:58.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.07:43:58.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.07:43:58.03#ibcon#ireg 11 cls_cnt 2 2006.246.07:43:58.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:43:58.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:43:58.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:43:58.03#ibcon#enter wrdev, iclass 15, count 2 2006.246.07:43:58.03#ibcon#first serial, iclass 15, count 2 2006.246.07:43:58.03#ibcon#enter sib2, iclass 15, count 2 2006.246.07:43:58.03#ibcon#flushed, iclass 15, count 2 2006.246.07:43:58.03#ibcon#about to write, iclass 15, count 2 2006.246.07:43:58.03#ibcon#wrote, iclass 15, count 2 2006.246.07:43:58.03#ibcon#about to read 3, iclass 15, count 2 2006.246.07:43:58.05#ibcon#read 3, iclass 15, count 2 2006.246.07:43:58.05#ibcon#about to read 4, iclass 15, count 2 2006.246.07:43:58.05#ibcon#read 4, iclass 15, count 2 2006.246.07:43:58.05#ibcon#about to read 5, iclass 15, count 2 2006.246.07:43:58.05#ibcon#read 5, iclass 15, count 2 2006.246.07:43:58.05#ibcon#about to read 6, iclass 15, count 2 2006.246.07:43:58.05#ibcon#read 6, iclass 15, count 2 2006.246.07:43:58.05#ibcon#end of sib2, iclass 15, count 2 2006.246.07:43:58.05#ibcon#*mode == 0, iclass 15, count 2 2006.246.07:43:58.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.07:43:58.05#ibcon#[25=AT01-08\r\n] 2006.246.07:43:58.05#ibcon#*before write, iclass 15, count 2 2006.246.07:43:58.05#ibcon#enter sib2, iclass 15, count 2 2006.246.07:43:58.05#ibcon#flushed, iclass 15, count 2 2006.246.07:43:58.05#ibcon#about to write, iclass 15, count 2 2006.246.07:43:58.05#ibcon#wrote, iclass 15, count 2 2006.246.07:43:58.05#ibcon#about to read 3, iclass 15, count 2 2006.246.07:43:58.09#ibcon#read 3, iclass 15, count 2 2006.246.07:43:58.09#ibcon#about to read 4, iclass 15, count 2 2006.246.07:43:58.09#ibcon#read 4, iclass 15, count 2 2006.246.07:43:58.09#ibcon#about to read 5, iclass 15, count 2 2006.246.07:43:58.09#ibcon#read 5, iclass 15, count 2 2006.246.07:43:58.09#ibcon#about to read 6, iclass 15, count 2 2006.246.07:43:58.09#ibcon#read 6, iclass 15, count 2 2006.246.07:43:58.09#ibcon#end of sib2, iclass 15, count 2 2006.246.07:43:58.09#ibcon#*after write, iclass 15, count 2 2006.246.07:43:58.09#ibcon#*before return 0, iclass 15, count 2 2006.246.07:43:58.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:43:58.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:43:58.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.07:43:58.09#ibcon#ireg 7 cls_cnt 0 2006.246.07:43:58.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:43:58.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:43:58.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:43:58.20#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:43:58.20#ibcon#first serial, iclass 15, count 0 2006.246.07:43:58.20#ibcon#enter sib2, iclass 15, count 0 2006.246.07:43:58.20#ibcon#flushed, iclass 15, count 0 2006.246.07:43:58.20#ibcon#about to write, iclass 15, count 0 2006.246.07:43:58.20#ibcon#wrote, iclass 15, count 0 2006.246.07:43:58.20#ibcon#about to read 3, iclass 15, count 0 2006.246.07:43:58.22#ibcon#read 3, iclass 15, count 0 2006.246.07:43:58.22#ibcon#about to read 4, iclass 15, count 0 2006.246.07:43:58.22#ibcon#read 4, iclass 15, count 0 2006.246.07:43:58.22#ibcon#about to read 5, iclass 15, count 0 2006.246.07:43:58.22#ibcon#read 5, iclass 15, count 0 2006.246.07:43:58.22#ibcon#about to read 6, iclass 15, count 0 2006.246.07:43:58.22#ibcon#read 6, iclass 15, count 0 2006.246.07:43:58.22#ibcon#end of sib2, iclass 15, count 0 2006.246.07:43:58.22#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:43:58.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:43:58.22#ibcon#[25=USB\r\n] 2006.246.07:43:58.22#ibcon#*before write, iclass 15, count 0 2006.246.07:43:58.22#ibcon#enter sib2, iclass 15, count 0 2006.246.07:43:58.22#ibcon#flushed, iclass 15, count 0 2006.246.07:43:58.22#ibcon#about to write, iclass 15, count 0 2006.246.07:43:58.22#ibcon#wrote, iclass 15, count 0 2006.246.07:43:58.22#ibcon#about to read 3, iclass 15, count 0 2006.246.07:43:58.26#ibcon#read 3, iclass 15, count 0 2006.246.07:43:58.26#ibcon#about to read 4, iclass 15, count 0 2006.246.07:43:58.26#ibcon#read 4, iclass 15, count 0 2006.246.07:43:58.26#ibcon#about to read 5, iclass 15, count 0 2006.246.07:43:58.26#ibcon#read 5, iclass 15, count 0 2006.246.07:43:58.26#ibcon#about to read 6, iclass 15, count 0 2006.246.07:43:58.26#ibcon#read 6, iclass 15, count 0 2006.246.07:43:58.26#ibcon#end of sib2, iclass 15, count 0 2006.246.07:43:58.26#ibcon#*after write, iclass 15, count 0 2006.246.07:43:58.26#ibcon#*before return 0, iclass 15, count 0 2006.246.07:43:58.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:43:58.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:43:58.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:43:58.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:43:58.26$vc4f8/valo=2,572.99 2006.246.07:43:58.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:43:58.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:43:58.26#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:58.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:43:58.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:43:58.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:43:58.26#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:43:58.26#ibcon#first serial, iclass 17, count 0 2006.246.07:43:58.26#ibcon#enter sib2, iclass 17, count 0 2006.246.07:43:58.26#ibcon#flushed, iclass 17, count 0 2006.246.07:43:58.26#ibcon#about to write, iclass 17, count 0 2006.246.07:43:58.26#ibcon#wrote, iclass 17, count 0 2006.246.07:43:58.26#ibcon#about to read 3, iclass 17, count 0 2006.246.07:43:58.27#ibcon#read 3, iclass 17, count 0 2006.246.07:43:58.27#ibcon#about to read 4, iclass 17, count 0 2006.246.07:43:58.27#ibcon#read 4, iclass 17, count 0 2006.246.07:43:58.27#ibcon#about to read 5, iclass 17, count 0 2006.246.07:43:58.27#ibcon#read 5, iclass 17, count 0 2006.246.07:43:58.27#ibcon#about to read 6, iclass 17, count 0 2006.246.07:43:58.27#ibcon#read 6, iclass 17, count 0 2006.246.07:43:58.27#ibcon#end of sib2, iclass 17, count 0 2006.246.07:43:58.27#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:43:58.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:43:58.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:43:58.27#ibcon#*before write, iclass 17, count 0 2006.246.07:43:58.27#ibcon#enter sib2, iclass 17, count 0 2006.246.07:43:58.27#ibcon#flushed, iclass 17, count 0 2006.246.07:43:58.27#ibcon#about to write, iclass 17, count 0 2006.246.07:43:58.27#ibcon#wrote, iclass 17, count 0 2006.246.07:43:58.27#ibcon#about to read 3, iclass 17, count 0 2006.246.07:43:58.31#ibcon#read 3, iclass 17, count 0 2006.246.07:43:58.31#ibcon#about to read 4, iclass 17, count 0 2006.246.07:43:58.31#ibcon#read 4, iclass 17, count 0 2006.246.07:43:58.31#ibcon#about to read 5, iclass 17, count 0 2006.246.07:43:58.31#ibcon#read 5, iclass 17, count 0 2006.246.07:43:58.31#ibcon#about to read 6, iclass 17, count 0 2006.246.07:43:58.31#ibcon#read 6, iclass 17, count 0 2006.246.07:43:58.31#ibcon#end of sib2, iclass 17, count 0 2006.246.07:43:58.31#ibcon#*after write, iclass 17, count 0 2006.246.07:43:58.31#ibcon#*before return 0, iclass 17, count 0 2006.246.07:43:58.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:43:58.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:43:58.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:43:58.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:43:58.31$vc4f8/va=2,7 2006.246.07:43:58.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.07:43:58.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.07:43:58.31#ibcon#ireg 11 cls_cnt 2 2006.246.07:43:58.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:43:58.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:43:58.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:43:58.38#ibcon#enter wrdev, iclass 19, count 2 2006.246.07:43:58.38#ibcon#first serial, iclass 19, count 2 2006.246.07:43:58.38#ibcon#enter sib2, iclass 19, count 2 2006.246.07:43:58.38#ibcon#flushed, iclass 19, count 2 2006.246.07:43:58.38#ibcon#about to write, iclass 19, count 2 2006.246.07:43:58.38#ibcon#wrote, iclass 19, count 2 2006.246.07:43:58.38#ibcon#about to read 3, iclass 19, count 2 2006.246.07:43:58.40#ibcon#read 3, iclass 19, count 2 2006.246.07:43:58.40#ibcon#about to read 4, iclass 19, count 2 2006.246.07:43:58.40#ibcon#read 4, iclass 19, count 2 2006.246.07:43:58.40#ibcon#about to read 5, iclass 19, count 2 2006.246.07:43:58.40#ibcon#read 5, iclass 19, count 2 2006.246.07:43:58.40#ibcon#about to read 6, iclass 19, count 2 2006.246.07:43:58.40#ibcon#read 6, iclass 19, count 2 2006.246.07:43:58.40#ibcon#end of sib2, iclass 19, count 2 2006.246.07:43:58.40#ibcon#*mode == 0, iclass 19, count 2 2006.246.07:43:58.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.07:43:58.40#ibcon#[25=AT02-07\r\n] 2006.246.07:43:58.40#ibcon#*before write, iclass 19, count 2 2006.246.07:43:58.40#ibcon#enter sib2, iclass 19, count 2 2006.246.07:43:58.40#ibcon#flushed, iclass 19, count 2 2006.246.07:43:58.40#ibcon#about to write, iclass 19, count 2 2006.246.07:43:58.40#ibcon#wrote, iclass 19, count 2 2006.246.07:43:58.40#ibcon#about to read 3, iclass 19, count 2 2006.246.07:43:58.43#ibcon#read 3, iclass 19, count 2 2006.246.07:43:58.43#ibcon#about to read 4, iclass 19, count 2 2006.246.07:43:58.43#ibcon#read 4, iclass 19, count 2 2006.246.07:43:58.43#ibcon#about to read 5, iclass 19, count 2 2006.246.07:43:58.43#ibcon#read 5, iclass 19, count 2 2006.246.07:43:58.43#ibcon#about to read 6, iclass 19, count 2 2006.246.07:43:58.43#ibcon#read 6, iclass 19, count 2 2006.246.07:43:58.43#ibcon#end of sib2, iclass 19, count 2 2006.246.07:43:58.43#ibcon#*after write, iclass 19, count 2 2006.246.07:43:58.43#ibcon#*before return 0, iclass 19, count 2 2006.246.07:43:58.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:43:58.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:43:58.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.07:43:58.43#ibcon#ireg 7 cls_cnt 0 2006.246.07:43:58.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:43:58.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:43:58.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:43:58.56#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:43:58.56#ibcon#first serial, iclass 19, count 0 2006.246.07:43:58.56#ibcon#enter sib2, iclass 19, count 0 2006.246.07:43:58.56#ibcon#flushed, iclass 19, count 0 2006.246.07:43:58.56#ibcon#about to write, iclass 19, count 0 2006.246.07:43:58.56#ibcon#wrote, iclass 19, count 0 2006.246.07:43:58.56#ibcon#about to read 3, iclass 19, count 0 2006.246.07:43:58.58#ibcon#read 3, iclass 19, count 0 2006.246.07:43:58.58#ibcon#about to read 4, iclass 19, count 0 2006.246.07:43:58.58#ibcon#read 4, iclass 19, count 0 2006.246.07:43:58.58#ibcon#about to read 5, iclass 19, count 0 2006.246.07:43:58.58#ibcon#read 5, iclass 19, count 0 2006.246.07:43:58.58#ibcon#about to read 6, iclass 19, count 0 2006.246.07:43:58.58#ibcon#read 6, iclass 19, count 0 2006.246.07:43:58.58#ibcon#end of sib2, iclass 19, count 0 2006.246.07:43:58.58#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:43:58.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:43:58.58#ibcon#[25=USB\r\n] 2006.246.07:43:58.58#ibcon#*before write, iclass 19, count 0 2006.246.07:43:58.58#ibcon#enter sib2, iclass 19, count 0 2006.246.07:43:58.58#ibcon#flushed, iclass 19, count 0 2006.246.07:43:58.58#ibcon#about to write, iclass 19, count 0 2006.246.07:43:58.58#ibcon#wrote, iclass 19, count 0 2006.246.07:43:58.58#ibcon#about to read 3, iclass 19, count 0 2006.246.07:43:58.60#ibcon#read 3, iclass 19, count 0 2006.246.07:43:58.60#ibcon#about to read 4, iclass 19, count 0 2006.246.07:43:58.60#ibcon#read 4, iclass 19, count 0 2006.246.07:43:58.60#ibcon#about to read 5, iclass 19, count 0 2006.246.07:43:58.60#ibcon#read 5, iclass 19, count 0 2006.246.07:43:58.60#ibcon#about to read 6, iclass 19, count 0 2006.246.07:43:58.60#ibcon#read 6, iclass 19, count 0 2006.246.07:43:58.60#ibcon#end of sib2, iclass 19, count 0 2006.246.07:43:58.60#ibcon#*after write, iclass 19, count 0 2006.246.07:43:58.60#ibcon#*before return 0, iclass 19, count 0 2006.246.07:43:58.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:43:58.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:43:58.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:43:58.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:43:58.60$vc4f8/valo=3,672.99 2006.246.07:43:58.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.07:43:58.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.07:43:58.60#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:58.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:43:58.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:43:58.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:43:58.60#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:43:58.60#ibcon#first serial, iclass 21, count 0 2006.246.07:43:58.60#ibcon#enter sib2, iclass 21, count 0 2006.246.07:43:58.60#ibcon#flushed, iclass 21, count 0 2006.246.07:43:58.60#ibcon#about to write, iclass 21, count 0 2006.246.07:43:58.60#ibcon#wrote, iclass 21, count 0 2006.246.07:43:58.60#ibcon#about to read 3, iclass 21, count 0 2006.246.07:43:58.63#ibcon#read 3, iclass 21, count 0 2006.246.07:43:58.63#ibcon#about to read 4, iclass 21, count 0 2006.246.07:43:58.63#ibcon#read 4, iclass 21, count 0 2006.246.07:43:58.63#ibcon#about to read 5, iclass 21, count 0 2006.246.07:43:58.63#ibcon#read 5, iclass 21, count 0 2006.246.07:43:58.63#ibcon#about to read 6, iclass 21, count 0 2006.246.07:43:58.63#ibcon#read 6, iclass 21, count 0 2006.246.07:43:58.63#ibcon#end of sib2, iclass 21, count 0 2006.246.07:43:58.63#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:43:58.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:43:58.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:43:58.63#ibcon#*before write, iclass 21, count 0 2006.246.07:43:58.63#ibcon#enter sib2, iclass 21, count 0 2006.246.07:43:58.63#ibcon#flushed, iclass 21, count 0 2006.246.07:43:58.63#ibcon#about to write, iclass 21, count 0 2006.246.07:43:58.63#ibcon#wrote, iclass 21, count 0 2006.246.07:43:58.63#ibcon#about to read 3, iclass 21, count 0 2006.246.07:43:58.66#ibcon#read 3, iclass 21, count 0 2006.246.07:43:58.66#ibcon#about to read 4, iclass 21, count 0 2006.246.07:43:58.66#ibcon#read 4, iclass 21, count 0 2006.246.07:43:58.66#ibcon#about to read 5, iclass 21, count 0 2006.246.07:43:58.66#ibcon#read 5, iclass 21, count 0 2006.246.07:43:58.66#ibcon#about to read 6, iclass 21, count 0 2006.246.07:43:58.66#ibcon#read 6, iclass 21, count 0 2006.246.07:43:58.66#ibcon#end of sib2, iclass 21, count 0 2006.246.07:43:58.66#ibcon#*after write, iclass 21, count 0 2006.246.07:43:58.66#ibcon#*before return 0, iclass 21, count 0 2006.246.07:43:58.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:43:58.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:43:58.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:43:58.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:43:58.66$vc4f8/va=3,6 2006.246.07:43:58.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.07:43:58.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.07:43:58.66#ibcon#ireg 11 cls_cnt 2 2006.246.07:43:58.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:43:58.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:43:58.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:43:58.72#ibcon#enter wrdev, iclass 23, count 2 2006.246.07:43:58.72#ibcon#first serial, iclass 23, count 2 2006.246.07:43:58.72#ibcon#enter sib2, iclass 23, count 2 2006.246.07:43:58.72#ibcon#flushed, iclass 23, count 2 2006.246.07:43:58.72#ibcon#about to write, iclass 23, count 2 2006.246.07:43:58.72#ibcon#wrote, iclass 23, count 2 2006.246.07:43:58.72#ibcon#about to read 3, iclass 23, count 2 2006.246.07:43:58.75#ibcon#read 3, iclass 23, count 2 2006.246.07:43:58.75#ibcon#about to read 4, iclass 23, count 2 2006.246.07:43:58.75#ibcon#read 4, iclass 23, count 2 2006.246.07:43:58.75#ibcon#about to read 5, iclass 23, count 2 2006.246.07:43:58.75#ibcon#read 5, iclass 23, count 2 2006.246.07:43:58.75#ibcon#about to read 6, iclass 23, count 2 2006.246.07:43:58.75#ibcon#read 6, iclass 23, count 2 2006.246.07:43:58.75#ibcon#end of sib2, iclass 23, count 2 2006.246.07:43:58.75#ibcon#*mode == 0, iclass 23, count 2 2006.246.07:43:58.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.07:43:58.75#ibcon#[25=AT03-06\r\n] 2006.246.07:43:58.75#ibcon#*before write, iclass 23, count 2 2006.246.07:43:58.75#ibcon#enter sib2, iclass 23, count 2 2006.246.07:43:58.75#ibcon#flushed, iclass 23, count 2 2006.246.07:43:58.75#ibcon#about to write, iclass 23, count 2 2006.246.07:43:58.75#ibcon#wrote, iclass 23, count 2 2006.246.07:43:58.75#ibcon#about to read 3, iclass 23, count 2 2006.246.07:43:58.78#ibcon#read 3, iclass 23, count 2 2006.246.07:43:58.78#ibcon#about to read 4, iclass 23, count 2 2006.246.07:43:58.78#ibcon#read 4, iclass 23, count 2 2006.246.07:43:58.78#ibcon#about to read 5, iclass 23, count 2 2006.246.07:43:58.78#ibcon#read 5, iclass 23, count 2 2006.246.07:43:58.78#ibcon#about to read 6, iclass 23, count 2 2006.246.07:43:58.78#ibcon#read 6, iclass 23, count 2 2006.246.07:43:58.78#ibcon#end of sib2, iclass 23, count 2 2006.246.07:43:58.78#ibcon#*after write, iclass 23, count 2 2006.246.07:43:58.78#ibcon#*before return 0, iclass 23, count 2 2006.246.07:43:58.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:43:58.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:43:58.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.07:43:58.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:43:58.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:43:58.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:43:58.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:43:58.90#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:43:58.90#ibcon#first serial, iclass 23, count 0 2006.246.07:43:58.90#ibcon#enter sib2, iclass 23, count 0 2006.246.07:43:58.90#ibcon#flushed, iclass 23, count 0 2006.246.07:43:58.90#ibcon#about to write, iclass 23, count 0 2006.246.07:43:58.90#ibcon#wrote, iclass 23, count 0 2006.246.07:43:58.90#ibcon#about to read 3, iclass 23, count 0 2006.246.07:43:58.92#ibcon#read 3, iclass 23, count 0 2006.246.07:43:58.92#ibcon#about to read 4, iclass 23, count 0 2006.246.07:43:58.92#ibcon#read 4, iclass 23, count 0 2006.246.07:43:58.92#ibcon#about to read 5, iclass 23, count 0 2006.246.07:43:58.92#ibcon#read 5, iclass 23, count 0 2006.246.07:43:58.92#ibcon#about to read 6, iclass 23, count 0 2006.246.07:43:58.92#ibcon#read 6, iclass 23, count 0 2006.246.07:43:58.92#ibcon#end of sib2, iclass 23, count 0 2006.246.07:43:58.92#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:43:58.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:43:58.92#ibcon#[25=USB\r\n] 2006.246.07:43:58.92#ibcon#*before write, iclass 23, count 0 2006.246.07:43:58.92#ibcon#enter sib2, iclass 23, count 0 2006.246.07:43:58.92#ibcon#flushed, iclass 23, count 0 2006.246.07:43:58.92#ibcon#about to write, iclass 23, count 0 2006.246.07:43:58.92#ibcon#wrote, iclass 23, count 0 2006.246.07:43:58.92#ibcon#about to read 3, iclass 23, count 0 2006.246.07:43:58.95#ibcon#read 3, iclass 23, count 0 2006.246.07:43:58.95#ibcon#about to read 4, iclass 23, count 0 2006.246.07:43:58.95#ibcon#read 4, iclass 23, count 0 2006.246.07:43:58.95#ibcon#about to read 5, iclass 23, count 0 2006.246.07:43:58.95#ibcon#read 5, iclass 23, count 0 2006.246.07:43:58.95#ibcon#about to read 6, iclass 23, count 0 2006.246.07:43:58.95#ibcon#read 6, iclass 23, count 0 2006.246.07:43:58.95#ibcon#end of sib2, iclass 23, count 0 2006.246.07:43:58.95#ibcon#*after write, iclass 23, count 0 2006.246.07:43:58.95#ibcon#*before return 0, iclass 23, count 0 2006.246.07:43:58.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:43:58.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:43:58.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:43:58.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:43:58.95$vc4f8/valo=4,832.99 2006.246.07:43:58.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.07:43:58.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.07:43:58.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:58.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:43:58.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:43:58.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:43:58.95#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:43:58.95#ibcon#first serial, iclass 25, count 0 2006.246.07:43:58.95#ibcon#enter sib2, iclass 25, count 0 2006.246.07:43:58.95#ibcon#flushed, iclass 25, count 0 2006.246.07:43:58.95#ibcon#about to write, iclass 25, count 0 2006.246.07:43:58.95#ibcon#wrote, iclass 25, count 0 2006.246.07:43:58.95#ibcon#about to read 3, iclass 25, count 0 2006.246.07:43:58.97#ibcon#read 3, iclass 25, count 0 2006.246.07:43:58.97#ibcon#about to read 4, iclass 25, count 0 2006.246.07:43:58.97#ibcon#read 4, iclass 25, count 0 2006.246.07:43:58.97#ibcon#about to read 5, iclass 25, count 0 2006.246.07:43:58.97#ibcon#read 5, iclass 25, count 0 2006.246.07:43:58.97#ibcon#about to read 6, iclass 25, count 0 2006.246.07:43:58.97#ibcon#read 6, iclass 25, count 0 2006.246.07:43:58.97#ibcon#end of sib2, iclass 25, count 0 2006.246.07:43:58.97#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:43:58.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:43:58.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:43:58.97#ibcon#*before write, iclass 25, count 0 2006.246.07:43:58.97#ibcon#enter sib2, iclass 25, count 0 2006.246.07:43:58.97#ibcon#flushed, iclass 25, count 0 2006.246.07:43:58.97#ibcon#about to write, iclass 25, count 0 2006.246.07:43:58.97#ibcon#wrote, iclass 25, count 0 2006.246.07:43:58.97#ibcon#about to read 3, iclass 25, count 0 2006.246.07:43:59.01#ibcon#read 3, iclass 25, count 0 2006.246.07:43:59.01#ibcon#about to read 4, iclass 25, count 0 2006.246.07:43:59.01#ibcon#read 4, iclass 25, count 0 2006.246.07:43:59.01#ibcon#about to read 5, iclass 25, count 0 2006.246.07:43:59.01#ibcon#read 5, iclass 25, count 0 2006.246.07:43:59.01#ibcon#about to read 6, iclass 25, count 0 2006.246.07:43:59.01#ibcon#read 6, iclass 25, count 0 2006.246.07:43:59.01#ibcon#end of sib2, iclass 25, count 0 2006.246.07:43:59.01#ibcon#*after write, iclass 25, count 0 2006.246.07:43:59.01#ibcon#*before return 0, iclass 25, count 0 2006.246.07:43:59.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:43:59.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:43:59.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:43:59.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:43:59.01$vc4f8/va=4,7 2006.246.07:43:59.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.07:43:59.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.07:43:59.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:43:59.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:43:59.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:43:59.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:43:59.07#ibcon#enter wrdev, iclass 27, count 2 2006.246.07:43:59.07#ibcon#first serial, iclass 27, count 2 2006.246.07:43:59.07#ibcon#enter sib2, iclass 27, count 2 2006.246.07:43:59.07#ibcon#flushed, iclass 27, count 2 2006.246.07:43:59.07#ibcon#about to write, iclass 27, count 2 2006.246.07:43:59.07#ibcon#wrote, iclass 27, count 2 2006.246.07:43:59.07#ibcon#about to read 3, iclass 27, count 2 2006.246.07:43:59.09#ibcon#read 3, iclass 27, count 2 2006.246.07:43:59.09#ibcon#about to read 4, iclass 27, count 2 2006.246.07:43:59.09#ibcon#read 4, iclass 27, count 2 2006.246.07:43:59.09#ibcon#about to read 5, iclass 27, count 2 2006.246.07:43:59.09#ibcon#read 5, iclass 27, count 2 2006.246.07:43:59.09#ibcon#about to read 6, iclass 27, count 2 2006.246.07:43:59.09#ibcon#read 6, iclass 27, count 2 2006.246.07:43:59.09#ibcon#end of sib2, iclass 27, count 2 2006.246.07:43:59.09#ibcon#*mode == 0, iclass 27, count 2 2006.246.07:43:59.09#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.07:43:59.09#ibcon#[25=AT04-07\r\n] 2006.246.07:43:59.09#ibcon#*before write, iclass 27, count 2 2006.246.07:43:59.09#ibcon#enter sib2, iclass 27, count 2 2006.246.07:43:59.09#ibcon#flushed, iclass 27, count 2 2006.246.07:43:59.09#ibcon#about to write, iclass 27, count 2 2006.246.07:43:59.09#ibcon#wrote, iclass 27, count 2 2006.246.07:43:59.09#ibcon#about to read 3, iclass 27, count 2 2006.246.07:43:59.12#ibcon#read 3, iclass 27, count 2 2006.246.07:43:59.12#ibcon#about to read 4, iclass 27, count 2 2006.246.07:43:59.12#ibcon#read 4, iclass 27, count 2 2006.246.07:43:59.12#ibcon#about to read 5, iclass 27, count 2 2006.246.07:43:59.12#ibcon#read 5, iclass 27, count 2 2006.246.07:43:59.12#ibcon#about to read 6, iclass 27, count 2 2006.246.07:43:59.12#ibcon#read 6, iclass 27, count 2 2006.246.07:43:59.12#ibcon#end of sib2, iclass 27, count 2 2006.246.07:43:59.12#ibcon#*after write, iclass 27, count 2 2006.246.07:43:59.12#ibcon#*before return 0, iclass 27, count 2 2006.246.07:43:59.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:43:59.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:43:59.12#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.07:43:59.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:43:59.12#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:43:59.24#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:43:59.24#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:43:59.24#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:43:59.24#ibcon#first serial, iclass 27, count 0 2006.246.07:43:59.24#ibcon#enter sib2, iclass 27, count 0 2006.246.07:43:59.24#ibcon#flushed, iclass 27, count 0 2006.246.07:43:59.24#ibcon#about to write, iclass 27, count 0 2006.246.07:43:59.24#ibcon#wrote, iclass 27, count 0 2006.246.07:43:59.24#ibcon#about to read 3, iclass 27, count 0 2006.246.07:43:59.26#ibcon#read 3, iclass 27, count 0 2006.246.07:43:59.26#ibcon#about to read 4, iclass 27, count 0 2006.246.07:43:59.26#ibcon#read 4, iclass 27, count 0 2006.246.07:43:59.26#ibcon#about to read 5, iclass 27, count 0 2006.246.07:43:59.26#ibcon#read 5, iclass 27, count 0 2006.246.07:43:59.26#ibcon#about to read 6, iclass 27, count 0 2006.246.07:43:59.26#ibcon#read 6, iclass 27, count 0 2006.246.07:43:59.26#ibcon#end of sib2, iclass 27, count 0 2006.246.07:43:59.26#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:43:59.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:43:59.26#ibcon#[25=USB\r\n] 2006.246.07:43:59.26#ibcon#*before write, iclass 27, count 0 2006.246.07:43:59.26#ibcon#enter sib2, iclass 27, count 0 2006.246.07:43:59.26#ibcon#flushed, iclass 27, count 0 2006.246.07:43:59.26#ibcon#about to write, iclass 27, count 0 2006.246.07:43:59.26#ibcon#wrote, iclass 27, count 0 2006.246.07:43:59.26#ibcon#about to read 3, iclass 27, count 0 2006.246.07:43:59.29#ibcon#read 3, iclass 27, count 0 2006.246.07:43:59.29#ibcon#about to read 4, iclass 27, count 0 2006.246.07:43:59.29#ibcon#read 4, iclass 27, count 0 2006.246.07:43:59.29#ibcon#about to read 5, iclass 27, count 0 2006.246.07:43:59.29#ibcon#read 5, iclass 27, count 0 2006.246.07:43:59.29#ibcon#about to read 6, iclass 27, count 0 2006.246.07:43:59.29#ibcon#read 6, iclass 27, count 0 2006.246.07:43:59.29#ibcon#end of sib2, iclass 27, count 0 2006.246.07:43:59.29#ibcon#*after write, iclass 27, count 0 2006.246.07:43:59.29#ibcon#*before return 0, iclass 27, count 0 2006.246.07:43:59.29#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:43:59.29#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:43:59.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:43:59.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:43:59.29$vc4f8/valo=5,652.99 2006.246.07:43:59.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:43:59.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:43:59.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:59.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:43:59.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:43:59.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:43:59.29#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:43:59.29#ibcon#first serial, iclass 29, count 0 2006.246.07:43:59.29#ibcon#enter sib2, iclass 29, count 0 2006.246.07:43:59.29#ibcon#flushed, iclass 29, count 0 2006.246.07:43:59.29#ibcon#about to write, iclass 29, count 0 2006.246.07:43:59.29#ibcon#wrote, iclass 29, count 0 2006.246.07:43:59.29#ibcon#about to read 3, iclass 29, count 0 2006.246.07:43:59.31#ibcon#read 3, iclass 29, count 0 2006.246.07:43:59.31#ibcon#about to read 4, iclass 29, count 0 2006.246.07:43:59.31#ibcon#read 4, iclass 29, count 0 2006.246.07:43:59.31#ibcon#about to read 5, iclass 29, count 0 2006.246.07:43:59.31#ibcon#read 5, iclass 29, count 0 2006.246.07:43:59.31#ibcon#about to read 6, iclass 29, count 0 2006.246.07:43:59.31#ibcon#read 6, iclass 29, count 0 2006.246.07:43:59.31#ibcon#end of sib2, iclass 29, count 0 2006.246.07:43:59.31#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:43:59.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:43:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:43:59.31#ibcon#*before write, iclass 29, count 0 2006.246.07:43:59.31#ibcon#enter sib2, iclass 29, count 0 2006.246.07:43:59.31#ibcon#flushed, iclass 29, count 0 2006.246.07:43:59.31#ibcon#about to write, iclass 29, count 0 2006.246.07:43:59.31#ibcon#wrote, iclass 29, count 0 2006.246.07:43:59.31#ibcon#about to read 3, iclass 29, count 0 2006.246.07:43:59.35#ibcon#read 3, iclass 29, count 0 2006.246.07:43:59.35#ibcon#about to read 4, iclass 29, count 0 2006.246.07:43:59.35#ibcon#read 4, iclass 29, count 0 2006.246.07:43:59.35#ibcon#about to read 5, iclass 29, count 0 2006.246.07:43:59.35#ibcon#read 5, iclass 29, count 0 2006.246.07:43:59.35#ibcon#about to read 6, iclass 29, count 0 2006.246.07:43:59.35#ibcon#read 6, iclass 29, count 0 2006.246.07:43:59.35#ibcon#end of sib2, iclass 29, count 0 2006.246.07:43:59.35#ibcon#*after write, iclass 29, count 0 2006.246.07:43:59.35#ibcon#*before return 0, iclass 29, count 0 2006.246.07:43:59.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:43:59.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:43:59.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:43:59.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:43:59.35$vc4f8/va=5,7 2006.246.07:43:59.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.07:43:59.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.07:43:59.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:43:59.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:43:59.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:43:59.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:43:59.41#ibcon#enter wrdev, iclass 31, count 2 2006.246.07:43:59.41#ibcon#first serial, iclass 31, count 2 2006.246.07:43:59.41#ibcon#enter sib2, iclass 31, count 2 2006.246.07:43:59.41#ibcon#flushed, iclass 31, count 2 2006.246.07:43:59.41#ibcon#about to write, iclass 31, count 2 2006.246.07:43:59.41#ibcon#wrote, iclass 31, count 2 2006.246.07:43:59.41#ibcon#about to read 3, iclass 31, count 2 2006.246.07:43:59.43#ibcon#read 3, iclass 31, count 2 2006.246.07:43:59.43#ibcon#about to read 4, iclass 31, count 2 2006.246.07:43:59.43#ibcon#read 4, iclass 31, count 2 2006.246.07:43:59.43#ibcon#about to read 5, iclass 31, count 2 2006.246.07:43:59.43#ibcon#read 5, iclass 31, count 2 2006.246.07:43:59.43#ibcon#about to read 6, iclass 31, count 2 2006.246.07:43:59.43#ibcon#read 6, iclass 31, count 2 2006.246.07:43:59.43#ibcon#end of sib2, iclass 31, count 2 2006.246.07:43:59.43#ibcon#*mode == 0, iclass 31, count 2 2006.246.07:43:59.43#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.07:43:59.43#ibcon#[25=AT05-07\r\n] 2006.246.07:43:59.43#ibcon#*before write, iclass 31, count 2 2006.246.07:43:59.43#ibcon#enter sib2, iclass 31, count 2 2006.246.07:43:59.43#ibcon#flushed, iclass 31, count 2 2006.246.07:43:59.43#ibcon#about to write, iclass 31, count 2 2006.246.07:43:59.43#ibcon#wrote, iclass 31, count 2 2006.246.07:43:59.43#ibcon#about to read 3, iclass 31, count 2 2006.246.07:43:59.46#ibcon#read 3, iclass 31, count 2 2006.246.07:43:59.46#ibcon#about to read 4, iclass 31, count 2 2006.246.07:43:59.46#ibcon#read 4, iclass 31, count 2 2006.246.07:43:59.46#ibcon#about to read 5, iclass 31, count 2 2006.246.07:43:59.46#ibcon#read 5, iclass 31, count 2 2006.246.07:43:59.46#ibcon#about to read 6, iclass 31, count 2 2006.246.07:43:59.46#ibcon#read 6, iclass 31, count 2 2006.246.07:43:59.46#ibcon#end of sib2, iclass 31, count 2 2006.246.07:43:59.46#ibcon#*after write, iclass 31, count 2 2006.246.07:43:59.46#ibcon#*before return 0, iclass 31, count 2 2006.246.07:43:59.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:43:59.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:43:59.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.07:43:59.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:43:59.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:43:59.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:43:59.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:43:59.58#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:43:59.58#ibcon#first serial, iclass 31, count 0 2006.246.07:43:59.58#ibcon#enter sib2, iclass 31, count 0 2006.246.07:43:59.58#ibcon#flushed, iclass 31, count 0 2006.246.07:43:59.58#ibcon#about to write, iclass 31, count 0 2006.246.07:43:59.58#ibcon#wrote, iclass 31, count 0 2006.246.07:43:59.58#ibcon#about to read 3, iclass 31, count 0 2006.246.07:43:59.60#ibcon#read 3, iclass 31, count 0 2006.246.07:43:59.60#ibcon#about to read 4, iclass 31, count 0 2006.246.07:43:59.60#ibcon#read 4, iclass 31, count 0 2006.246.07:43:59.60#ibcon#about to read 5, iclass 31, count 0 2006.246.07:43:59.60#ibcon#read 5, iclass 31, count 0 2006.246.07:43:59.60#ibcon#about to read 6, iclass 31, count 0 2006.246.07:43:59.60#ibcon#read 6, iclass 31, count 0 2006.246.07:43:59.60#ibcon#end of sib2, iclass 31, count 0 2006.246.07:43:59.60#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:43:59.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:43:59.60#ibcon#[25=USB\r\n] 2006.246.07:43:59.60#ibcon#*before write, iclass 31, count 0 2006.246.07:43:59.60#ibcon#enter sib2, iclass 31, count 0 2006.246.07:43:59.60#ibcon#flushed, iclass 31, count 0 2006.246.07:43:59.60#ibcon#about to write, iclass 31, count 0 2006.246.07:43:59.60#ibcon#wrote, iclass 31, count 0 2006.246.07:43:59.60#ibcon#about to read 3, iclass 31, count 0 2006.246.07:43:59.63#ibcon#read 3, iclass 31, count 0 2006.246.07:43:59.63#ibcon#about to read 4, iclass 31, count 0 2006.246.07:43:59.63#ibcon#read 4, iclass 31, count 0 2006.246.07:43:59.63#ibcon#about to read 5, iclass 31, count 0 2006.246.07:43:59.63#ibcon#read 5, iclass 31, count 0 2006.246.07:43:59.63#ibcon#about to read 6, iclass 31, count 0 2006.246.07:43:59.63#ibcon#read 6, iclass 31, count 0 2006.246.07:43:59.63#ibcon#end of sib2, iclass 31, count 0 2006.246.07:43:59.63#ibcon#*after write, iclass 31, count 0 2006.246.07:43:59.63#ibcon#*before return 0, iclass 31, count 0 2006.246.07:43:59.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:43:59.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:43:59.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:43:59.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:43:59.63$vc4f8/valo=6,772.99 2006.246.07:43:59.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.07:43:59.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.07:43:59.63#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:59.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:43:59.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:43:59.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:43:59.63#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:43:59.63#ibcon#first serial, iclass 33, count 0 2006.246.07:43:59.63#ibcon#enter sib2, iclass 33, count 0 2006.246.07:43:59.63#ibcon#flushed, iclass 33, count 0 2006.246.07:43:59.63#ibcon#about to write, iclass 33, count 0 2006.246.07:43:59.63#ibcon#wrote, iclass 33, count 0 2006.246.07:43:59.63#ibcon#about to read 3, iclass 33, count 0 2006.246.07:43:59.65#ibcon#read 3, iclass 33, count 0 2006.246.07:43:59.65#ibcon#about to read 4, iclass 33, count 0 2006.246.07:43:59.65#ibcon#read 4, iclass 33, count 0 2006.246.07:43:59.65#ibcon#about to read 5, iclass 33, count 0 2006.246.07:43:59.65#ibcon#read 5, iclass 33, count 0 2006.246.07:43:59.65#ibcon#about to read 6, iclass 33, count 0 2006.246.07:43:59.65#ibcon#read 6, iclass 33, count 0 2006.246.07:43:59.65#ibcon#end of sib2, iclass 33, count 0 2006.246.07:43:59.65#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:43:59.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:43:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:43:59.65#ibcon#*before write, iclass 33, count 0 2006.246.07:43:59.65#ibcon#enter sib2, iclass 33, count 0 2006.246.07:43:59.65#ibcon#flushed, iclass 33, count 0 2006.246.07:43:59.65#ibcon#about to write, iclass 33, count 0 2006.246.07:43:59.65#ibcon#wrote, iclass 33, count 0 2006.246.07:43:59.65#ibcon#about to read 3, iclass 33, count 0 2006.246.07:43:59.69#ibcon#read 3, iclass 33, count 0 2006.246.07:43:59.69#ibcon#about to read 4, iclass 33, count 0 2006.246.07:43:59.69#ibcon#read 4, iclass 33, count 0 2006.246.07:43:59.69#ibcon#about to read 5, iclass 33, count 0 2006.246.07:43:59.69#ibcon#read 5, iclass 33, count 0 2006.246.07:43:59.69#ibcon#about to read 6, iclass 33, count 0 2006.246.07:43:59.69#ibcon#read 6, iclass 33, count 0 2006.246.07:43:59.69#ibcon#end of sib2, iclass 33, count 0 2006.246.07:43:59.69#ibcon#*after write, iclass 33, count 0 2006.246.07:43:59.69#ibcon#*before return 0, iclass 33, count 0 2006.246.07:43:59.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:43:59.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:43:59.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:43:59.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:43:59.69$vc4f8/va=6,7 2006.246.07:43:59.69#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.07:43:59.69#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.07:43:59.69#ibcon#ireg 11 cls_cnt 2 2006.246.07:43:59.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:43:59.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:43:59.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:43:59.75#ibcon#enter wrdev, iclass 35, count 2 2006.246.07:43:59.75#ibcon#first serial, iclass 35, count 2 2006.246.07:43:59.75#ibcon#enter sib2, iclass 35, count 2 2006.246.07:43:59.75#ibcon#flushed, iclass 35, count 2 2006.246.07:43:59.75#ibcon#about to write, iclass 35, count 2 2006.246.07:43:59.75#ibcon#wrote, iclass 35, count 2 2006.246.07:43:59.75#ibcon#about to read 3, iclass 35, count 2 2006.246.07:43:59.77#ibcon#read 3, iclass 35, count 2 2006.246.07:43:59.77#ibcon#about to read 4, iclass 35, count 2 2006.246.07:43:59.77#ibcon#read 4, iclass 35, count 2 2006.246.07:43:59.77#ibcon#about to read 5, iclass 35, count 2 2006.246.07:43:59.77#ibcon#read 5, iclass 35, count 2 2006.246.07:43:59.77#ibcon#about to read 6, iclass 35, count 2 2006.246.07:43:59.77#ibcon#read 6, iclass 35, count 2 2006.246.07:43:59.77#ibcon#end of sib2, iclass 35, count 2 2006.246.07:43:59.77#ibcon#*mode == 0, iclass 35, count 2 2006.246.07:43:59.77#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.07:43:59.77#ibcon#[25=AT06-07\r\n] 2006.246.07:43:59.77#ibcon#*before write, iclass 35, count 2 2006.246.07:43:59.77#ibcon#enter sib2, iclass 35, count 2 2006.246.07:43:59.77#ibcon#flushed, iclass 35, count 2 2006.246.07:43:59.77#ibcon#about to write, iclass 35, count 2 2006.246.07:43:59.77#ibcon#wrote, iclass 35, count 2 2006.246.07:43:59.77#ibcon#about to read 3, iclass 35, count 2 2006.246.07:43:59.80#abcon#<5=/04 3.7 7.4 26.73 751005.6\r\n> 2006.246.07:43:59.80#ibcon#read 3, iclass 35, count 2 2006.246.07:43:59.80#ibcon#about to read 4, iclass 35, count 2 2006.246.07:43:59.80#ibcon#read 4, iclass 35, count 2 2006.246.07:43:59.80#ibcon#about to read 5, iclass 35, count 2 2006.246.07:43:59.80#ibcon#read 5, iclass 35, count 2 2006.246.07:43:59.80#ibcon#about to read 6, iclass 35, count 2 2006.246.07:43:59.80#ibcon#read 6, iclass 35, count 2 2006.246.07:43:59.80#ibcon#end of sib2, iclass 35, count 2 2006.246.07:43:59.80#ibcon#*after write, iclass 35, count 2 2006.246.07:43:59.80#ibcon#*before return 0, iclass 35, count 2 2006.246.07:43:59.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:43:59.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:43:59.80#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.07:43:59.80#ibcon#ireg 7 cls_cnt 0 2006.246.07:43:59.80#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:43:59.82#abcon#{5=INTERFACE CLEAR} 2006.246.07:43:59.88#abcon#[5=S1D000X0/0*\r\n] 2006.246.07:43:59.92#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:43:59.92#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:43:59.92#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:43:59.92#ibcon#first serial, iclass 35, count 0 2006.246.07:43:59.92#ibcon#enter sib2, iclass 35, count 0 2006.246.07:43:59.92#ibcon#flushed, iclass 35, count 0 2006.246.07:43:59.92#ibcon#about to write, iclass 35, count 0 2006.246.07:43:59.92#ibcon#wrote, iclass 35, count 0 2006.246.07:43:59.92#ibcon#about to read 3, iclass 35, count 0 2006.246.07:43:59.94#ibcon#read 3, iclass 35, count 0 2006.246.07:43:59.94#ibcon#about to read 4, iclass 35, count 0 2006.246.07:43:59.94#ibcon#read 4, iclass 35, count 0 2006.246.07:43:59.94#ibcon#about to read 5, iclass 35, count 0 2006.246.07:43:59.94#ibcon#read 5, iclass 35, count 0 2006.246.07:43:59.94#ibcon#about to read 6, iclass 35, count 0 2006.246.07:43:59.94#ibcon#read 6, iclass 35, count 0 2006.246.07:43:59.94#ibcon#end of sib2, iclass 35, count 0 2006.246.07:43:59.94#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:43:59.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:43:59.94#ibcon#[25=USB\r\n] 2006.246.07:43:59.94#ibcon#*before write, iclass 35, count 0 2006.246.07:43:59.94#ibcon#enter sib2, iclass 35, count 0 2006.246.07:43:59.94#ibcon#flushed, iclass 35, count 0 2006.246.07:43:59.94#ibcon#about to write, iclass 35, count 0 2006.246.07:43:59.94#ibcon#wrote, iclass 35, count 0 2006.246.07:43:59.94#ibcon#about to read 3, iclass 35, count 0 2006.246.07:43:59.97#ibcon#read 3, iclass 35, count 0 2006.246.07:43:59.97#ibcon#about to read 4, iclass 35, count 0 2006.246.07:43:59.97#ibcon#read 4, iclass 35, count 0 2006.246.07:43:59.97#ibcon#about to read 5, iclass 35, count 0 2006.246.07:43:59.97#ibcon#read 5, iclass 35, count 0 2006.246.07:43:59.97#ibcon#about to read 6, iclass 35, count 0 2006.246.07:43:59.97#ibcon#read 6, iclass 35, count 0 2006.246.07:43:59.97#ibcon#end of sib2, iclass 35, count 0 2006.246.07:43:59.97#ibcon#*after write, iclass 35, count 0 2006.246.07:43:59.97#ibcon#*before return 0, iclass 35, count 0 2006.246.07:43:59.97#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:43:59.97#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:43:59.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:43:59.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:43:59.97$vc4f8/valo=7,832.99 2006.246.07:43:59.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.07:43:59.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.07:43:59.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:43:59.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:43:59.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:43:59.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:43:59.97#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:43:59.97#ibcon#first serial, iclass 3, count 0 2006.246.07:43:59.97#ibcon#enter sib2, iclass 3, count 0 2006.246.07:43:59.97#ibcon#flushed, iclass 3, count 0 2006.246.07:43:59.97#ibcon#about to write, iclass 3, count 0 2006.246.07:43:59.97#ibcon#wrote, iclass 3, count 0 2006.246.07:43:59.97#ibcon#about to read 3, iclass 3, count 0 2006.246.07:43:59.99#ibcon#read 3, iclass 3, count 0 2006.246.07:43:59.99#ibcon#about to read 4, iclass 3, count 0 2006.246.07:43:59.99#ibcon#read 4, iclass 3, count 0 2006.246.07:43:59.99#ibcon#about to read 5, iclass 3, count 0 2006.246.07:43:59.99#ibcon#read 5, iclass 3, count 0 2006.246.07:43:59.99#ibcon#about to read 6, iclass 3, count 0 2006.246.07:43:59.99#ibcon#read 6, iclass 3, count 0 2006.246.07:43:59.99#ibcon#end of sib2, iclass 3, count 0 2006.246.07:43:59.99#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:43:59.99#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:43:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:43:59.99#ibcon#*before write, iclass 3, count 0 2006.246.07:43:59.99#ibcon#enter sib2, iclass 3, count 0 2006.246.07:43:59.99#ibcon#flushed, iclass 3, count 0 2006.246.07:43:59.99#ibcon#about to write, iclass 3, count 0 2006.246.07:43:59.99#ibcon#wrote, iclass 3, count 0 2006.246.07:43:59.99#ibcon#about to read 3, iclass 3, count 0 2006.246.07:44:00.03#ibcon#read 3, iclass 3, count 0 2006.246.07:44:00.03#ibcon#about to read 4, iclass 3, count 0 2006.246.07:44:00.03#ibcon#read 4, iclass 3, count 0 2006.246.07:44:00.03#ibcon#about to read 5, iclass 3, count 0 2006.246.07:44:00.03#ibcon#read 5, iclass 3, count 0 2006.246.07:44:00.03#ibcon#about to read 6, iclass 3, count 0 2006.246.07:44:00.03#ibcon#read 6, iclass 3, count 0 2006.246.07:44:00.03#ibcon#end of sib2, iclass 3, count 0 2006.246.07:44:00.03#ibcon#*after write, iclass 3, count 0 2006.246.07:44:00.03#ibcon#*before return 0, iclass 3, count 0 2006.246.07:44:00.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:44:00.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:44:00.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:44:00.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:44:00.03$vc4f8/va=7,7 2006.246.07:44:00.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.07:44:00.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.07:44:00.03#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:00.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:44:00.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:44:00.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:44:00.09#ibcon#enter wrdev, iclass 5, count 2 2006.246.07:44:00.09#ibcon#first serial, iclass 5, count 2 2006.246.07:44:00.09#ibcon#enter sib2, iclass 5, count 2 2006.246.07:44:00.09#ibcon#flushed, iclass 5, count 2 2006.246.07:44:00.09#ibcon#about to write, iclass 5, count 2 2006.246.07:44:00.09#ibcon#wrote, iclass 5, count 2 2006.246.07:44:00.09#ibcon#about to read 3, iclass 5, count 2 2006.246.07:44:00.11#ibcon#read 3, iclass 5, count 2 2006.246.07:44:00.11#ibcon#about to read 4, iclass 5, count 2 2006.246.07:44:00.11#ibcon#read 4, iclass 5, count 2 2006.246.07:44:00.11#ibcon#about to read 5, iclass 5, count 2 2006.246.07:44:00.11#ibcon#read 5, iclass 5, count 2 2006.246.07:44:00.11#ibcon#about to read 6, iclass 5, count 2 2006.246.07:44:00.11#ibcon#read 6, iclass 5, count 2 2006.246.07:44:00.11#ibcon#end of sib2, iclass 5, count 2 2006.246.07:44:00.11#ibcon#*mode == 0, iclass 5, count 2 2006.246.07:44:00.11#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.07:44:00.11#ibcon#[25=AT07-07\r\n] 2006.246.07:44:00.11#ibcon#*before write, iclass 5, count 2 2006.246.07:44:00.11#ibcon#enter sib2, iclass 5, count 2 2006.246.07:44:00.11#ibcon#flushed, iclass 5, count 2 2006.246.07:44:00.11#ibcon#about to write, iclass 5, count 2 2006.246.07:44:00.11#ibcon#wrote, iclass 5, count 2 2006.246.07:44:00.11#ibcon#about to read 3, iclass 5, count 2 2006.246.07:44:00.14#ibcon#read 3, iclass 5, count 2 2006.246.07:44:00.14#ibcon#about to read 4, iclass 5, count 2 2006.246.07:44:00.14#ibcon#read 4, iclass 5, count 2 2006.246.07:44:00.14#ibcon#about to read 5, iclass 5, count 2 2006.246.07:44:00.14#ibcon#read 5, iclass 5, count 2 2006.246.07:44:00.14#ibcon#about to read 6, iclass 5, count 2 2006.246.07:44:00.14#ibcon#read 6, iclass 5, count 2 2006.246.07:44:00.14#ibcon#end of sib2, iclass 5, count 2 2006.246.07:44:00.14#ibcon#*after write, iclass 5, count 2 2006.246.07:44:00.14#ibcon#*before return 0, iclass 5, count 2 2006.246.07:44:00.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:44:00.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:44:00.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.07:44:00.14#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:00.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:44:00.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:44:00.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:44:00.26#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:44:00.26#ibcon#first serial, iclass 5, count 0 2006.246.07:44:00.26#ibcon#enter sib2, iclass 5, count 0 2006.246.07:44:00.26#ibcon#flushed, iclass 5, count 0 2006.246.07:44:00.26#ibcon#about to write, iclass 5, count 0 2006.246.07:44:00.26#ibcon#wrote, iclass 5, count 0 2006.246.07:44:00.26#ibcon#about to read 3, iclass 5, count 0 2006.246.07:44:00.28#ibcon#read 3, iclass 5, count 0 2006.246.07:44:00.28#ibcon#about to read 4, iclass 5, count 0 2006.246.07:44:00.28#ibcon#read 4, iclass 5, count 0 2006.246.07:44:00.28#ibcon#about to read 5, iclass 5, count 0 2006.246.07:44:00.28#ibcon#read 5, iclass 5, count 0 2006.246.07:44:00.28#ibcon#about to read 6, iclass 5, count 0 2006.246.07:44:00.28#ibcon#read 6, iclass 5, count 0 2006.246.07:44:00.28#ibcon#end of sib2, iclass 5, count 0 2006.246.07:44:00.28#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:44:00.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:44:00.28#ibcon#[25=USB\r\n] 2006.246.07:44:00.28#ibcon#*before write, iclass 5, count 0 2006.246.07:44:00.28#ibcon#enter sib2, iclass 5, count 0 2006.246.07:44:00.28#ibcon#flushed, iclass 5, count 0 2006.246.07:44:00.28#ibcon#about to write, iclass 5, count 0 2006.246.07:44:00.28#ibcon#wrote, iclass 5, count 0 2006.246.07:44:00.28#ibcon#about to read 3, iclass 5, count 0 2006.246.07:44:00.31#ibcon#read 3, iclass 5, count 0 2006.246.07:44:00.31#ibcon#about to read 4, iclass 5, count 0 2006.246.07:44:00.31#ibcon#read 4, iclass 5, count 0 2006.246.07:44:00.31#ibcon#about to read 5, iclass 5, count 0 2006.246.07:44:00.31#ibcon#read 5, iclass 5, count 0 2006.246.07:44:00.31#ibcon#about to read 6, iclass 5, count 0 2006.246.07:44:00.31#ibcon#read 6, iclass 5, count 0 2006.246.07:44:00.31#ibcon#end of sib2, iclass 5, count 0 2006.246.07:44:00.31#ibcon#*after write, iclass 5, count 0 2006.246.07:44:00.31#ibcon#*before return 0, iclass 5, count 0 2006.246.07:44:00.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:44:00.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:44:00.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:44:00.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:44:00.31$vc4f8/valo=8,852.99 2006.246.07:44:00.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.07:44:00.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.07:44:00.31#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:00.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:44:00.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:44:00.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:44:00.31#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:44:00.31#ibcon#first serial, iclass 7, count 0 2006.246.07:44:00.31#ibcon#enter sib2, iclass 7, count 0 2006.246.07:44:00.31#ibcon#flushed, iclass 7, count 0 2006.246.07:44:00.31#ibcon#about to write, iclass 7, count 0 2006.246.07:44:00.31#ibcon#wrote, iclass 7, count 0 2006.246.07:44:00.31#ibcon#about to read 3, iclass 7, count 0 2006.246.07:44:00.34#ibcon#read 3, iclass 7, count 0 2006.246.07:44:00.34#ibcon#about to read 4, iclass 7, count 0 2006.246.07:44:00.34#ibcon#read 4, iclass 7, count 0 2006.246.07:44:00.34#ibcon#about to read 5, iclass 7, count 0 2006.246.07:44:00.34#ibcon#read 5, iclass 7, count 0 2006.246.07:44:00.34#ibcon#about to read 6, iclass 7, count 0 2006.246.07:44:00.34#ibcon#read 6, iclass 7, count 0 2006.246.07:44:00.34#ibcon#end of sib2, iclass 7, count 0 2006.246.07:44:00.34#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:44:00.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:44:00.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:44:00.34#ibcon#*before write, iclass 7, count 0 2006.246.07:44:00.34#ibcon#enter sib2, iclass 7, count 0 2006.246.07:44:00.34#ibcon#flushed, iclass 7, count 0 2006.246.07:44:00.34#ibcon#about to write, iclass 7, count 0 2006.246.07:44:00.34#ibcon#wrote, iclass 7, count 0 2006.246.07:44:00.34#ibcon#about to read 3, iclass 7, count 0 2006.246.07:44:00.38#ibcon#read 3, iclass 7, count 0 2006.246.07:44:00.38#ibcon#about to read 4, iclass 7, count 0 2006.246.07:44:00.38#ibcon#read 4, iclass 7, count 0 2006.246.07:44:00.38#ibcon#about to read 5, iclass 7, count 0 2006.246.07:44:00.38#ibcon#read 5, iclass 7, count 0 2006.246.07:44:00.38#ibcon#about to read 6, iclass 7, count 0 2006.246.07:44:00.38#ibcon#read 6, iclass 7, count 0 2006.246.07:44:00.38#ibcon#end of sib2, iclass 7, count 0 2006.246.07:44:00.38#ibcon#*after write, iclass 7, count 0 2006.246.07:44:00.38#ibcon#*before return 0, iclass 7, count 0 2006.246.07:44:00.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:44:00.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:44:00.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:44:00.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:44:00.38$vc4f8/va=8,8 2006.246.07:44:00.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.07:44:00.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.07:44:00.38#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:00.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:44:00.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:44:00.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:44:00.43#ibcon#enter wrdev, iclass 11, count 2 2006.246.07:44:00.43#ibcon#first serial, iclass 11, count 2 2006.246.07:44:00.43#ibcon#enter sib2, iclass 11, count 2 2006.246.07:44:00.43#ibcon#flushed, iclass 11, count 2 2006.246.07:44:00.43#ibcon#about to write, iclass 11, count 2 2006.246.07:44:00.43#ibcon#wrote, iclass 11, count 2 2006.246.07:44:00.43#ibcon#about to read 3, iclass 11, count 2 2006.246.07:44:00.45#ibcon#read 3, iclass 11, count 2 2006.246.07:44:00.45#ibcon#about to read 4, iclass 11, count 2 2006.246.07:44:00.45#ibcon#read 4, iclass 11, count 2 2006.246.07:44:00.45#ibcon#about to read 5, iclass 11, count 2 2006.246.07:44:00.45#ibcon#read 5, iclass 11, count 2 2006.246.07:44:00.45#ibcon#about to read 6, iclass 11, count 2 2006.246.07:44:00.45#ibcon#read 6, iclass 11, count 2 2006.246.07:44:00.45#ibcon#end of sib2, iclass 11, count 2 2006.246.07:44:00.45#ibcon#*mode == 0, iclass 11, count 2 2006.246.07:44:00.45#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.07:44:00.45#ibcon#[25=AT08-08\r\n] 2006.246.07:44:00.45#ibcon#*before write, iclass 11, count 2 2006.246.07:44:00.45#ibcon#enter sib2, iclass 11, count 2 2006.246.07:44:00.45#ibcon#flushed, iclass 11, count 2 2006.246.07:44:00.45#ibcon#about to write, iclass 11, count 2 2006.246.07:44:00.45#ibcon#wrote, iclass 11, count 2 2006.246.07:44:00.45#ibcon#about to read 3, iclass 11, count 2 2006.246.07:44:00.48#ibcon#read 3, iclass 11, count 2 2006.246.07:44:00.48#ibcon#about to read 4, iclass 11, count 2 2006.246.07:44:00.48#ibcon#read 4, iclass 11, count 2 2006.246.07:44:00.48#ibcon#about to read 5, iclass 11, count 2 2006.246.07:44:00.48#ibcon#read 5, iclass 11, count 2 2006.246.07:44:00.48#ibcon#about to read 6, iclass 11, count 2 2006.246.07:44:00.48#ibcon#read 6, iclass 11, count 2 2006.246.07:44:00.48#ibcon#end of sib2, iclass 11, count 2 2006.246.07:44:00.48#ibcon#*after write, iclass 11, count 2 2006.246.07:44:00.48#ibcon#*before return 0, iclass 11, count 2 2006.246.07:44:00.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:44:00.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:44:00.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.07:44:00.48#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:00.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:44:00.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:44:00.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:44:00.60#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:44:00.60#ibcon#first serial, iclass 11, count 0 2006.246.07:44:00.60#ibcon#enter sib2, iclass 11, count 0 2006.246.07:44:00.60#ibcon#flushed, iclass 11, count 0 2006.246.07:44:00.60#ibcon#about to write, iclass 11, count 0 2006.246.07:44:00.60#ibcon#wrote, iclass 11, count 0 2006.246.07:44:00.60#ibcon#about to read 3, iclass 11, count 0 2006.246.07:44:00.62#ibcon#read 3, iclass 11, count 0 2006.246.07:44:00.62#ibcon#about to read 4, iclass 11, count 0 2006.246.07:44:00.62#ibcon#read 4, iclass 11, count 0 2006.246.07:44:00.62#ibcon#about to read 5, iclass 11, count 0 2006.246.07:44:00.62#ibcon#read 5, iclass 11, count 0 2006.246.07:44:00.62#ibcon#about to read 6, iclass 11, count 0 2006.246.07:44:00.62#ibcon#read 6, iclass 11, count 0 2006.246.07:44:00.62#ibcon#end of sib2, iclass 11, count 0 2006.246.07:44:00.62#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:44:00.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:44:00.62#ibcon#[25=USB\r\n] 2006.246.07:44:00.62#ibcon#*before write, iclass 11, count 0 2006.246.07:44:00.62#ibcon#enter sib2, iclass 11, count 0 2006.246.07:44:00.62#ibcon#flushed, iclass 11, count 0 2006.246.07:44:00.62#ibcon#about to write, iclass 11, count 0 2006.246.07:44:00.62#ibcon#wrote, iclass 11, count 0 2006.246.07:44:00.62#ibcon#about to read 3, iclass 11, count 0 2006.246.07:44:00.65#ibcon#read 3, iclass 11, count 0 2006.246.07:44:00.65#ibcon#about to read 4, iclass 11, count 0 2006.246.07:44:00.65#ibcon#read 4, iclass 11, count 0 2006.246.07:44:00.65#ibcon#about to read 5, iclass 11, count 0 2006.246.07:44:00.65#ibcon#read 5, iclass 11, count 0 2006.246.07:44:00.65#ibcon#about to read 6, iclass 11, count 0 2006.246.07:44:00.65#ibcon#read 6, iclass 11, count 0 2006.246.07:44:00.65#ibcon#end of sib2, iclass 11, count 0 2006.246.07:44:00.65#ibcon#*after write, iclass 11, count 0 2006.246.07:44:00.65#ibcon#*before return 0, iclass 11, count 0 2006.246.07:44:00.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:44:00.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:44:00.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:44:00.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:44:00.65$vc4f8/vblo=1,632.99 2006.246.07:44:00.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.07:44:00.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.07:44:00.65#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:00.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:44:00.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:44:00.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:44:00.65#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:44:00.65#ibcon#first serial, iclass 13, count 0 2006.246.07:44:00.65#ibcon#enter sib2, iclass 13, count 0 2006.246.07:44:00.65#ibcon#flushed, iclass 13, count 0 2006.246.07:44:00.65#ibcon#about to write, iclass 13, count 0 2006.246.07:44:00.65#ibcon#wrote, iclass 13, count 0 2006.246.07:44:00.65#ibcon#about to read 3, iclass 13, count 0 2006.246.07:44:00.67#ibcon#read 3, iclass 13, count 0 2006.246.07:44:00.67#ibcon#about to read 4, iclass 13, count 0 2006.246.07:44:00.67#ibcon#read 4, iclass 13, count 0 2006.246.07:44:00.67#ibcon#about to read 5, iclass 13, count 0 2006.246.07:44:00.67#ibcon#read 5, iclass 13, count 0 2006.246.07:44:00.67#ibcon#about to read 6, iclass 13, count 0 2006.246.07:44:00.67#ibcon#read 6, iclass 13, count 0 2006.246.07:44:00.67#ibcon#end of sib2, iclass 13, count 0 2006.246.07:44:00.67#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:44:00.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:44:00.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:44:00.67#ibcon#*before write, iclass 13, count 0 2006.246.07:44:00.67#ibcon#enter sib2, iclass 13, count 0 2006.246.07:44:00.67#ibcon#flushed, iclass 13, count 0 2006.246.07:44:00.67#ibcon#about to write, iclass 13, count 0 2006.246.07:44:00.67#ibcon#wrote, iclass 13, count 0 2006.246.07:44:00.67#ibcon#about to read 3, iclass 13, count 0 2006.246.07:44:00.71#ibcon#read 3, iclass 13, count 0 2006.246.07:44:00.71#ibcon#about to read 4, iclass 13, count 0 2006.246.07:44:00.71#ibcon#read 4, iclass 13, count 0 2006.246.07:44:00.71#ibcon#about to read 5, iclass 13, count 0 2006.246.07:44:00.71#ibcon#read 5, iclass 13, count 0 2006.246.07:44:00.71#ibcon#about to read 6, iclass 13, count 0 2006.246.07:44:00.71#ibcon#read 6, iclass 13, count 0 2006.246.07:44:00.71#ibcon#end of sib2, iclass 13, count 0 2006.246.07:44:00.71#ibcon#*after write, iclass 13, count 0 2006.246.07:44:00.71#ibcon#*before return 0, iclass 13, count 0 2006.246.07:44:00.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:44:00.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:44:00.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:44:00.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:44:00.71$vc4f8/vb=1,4 2006.246.07:44:00.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.07:44:00.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.07:44:00.71#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:00.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:44:00.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:44:00.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:44:00.71#ibcon#enter wrdev, iclass 15, count 2 2006.246.07:44:00.71#ibcon#first serial, iclass 15, count 2 2006.246.07:44:00.71#ibcon#enter sib2, iclass 15, count 2 2006.246.07:44:00.71#ibcon#flushed, iclass 15, count 2 2006.246.07:44:00.71#ibcon#about to write, iclass 15, count 2 2006.246.07:44:00.71#ibcon#wrote, iclass 15, count 2 2006.246.07:44:00.71#ibcon#about to read 3, iclass 15, count 2 2006.246.07:44:00.73#ibcon#read 3, iclass 15, count 2 2006.246.07:44:00.73#ibcon#about to read 4, iclass 15, count 2 2006.246.07:44:00.73#ibcon#read 4, iclass 15, count 2 2006.246.07:44:00.73#ibcon#about to read 5, iclass 15, count 2 2006.246.07:44:00.73#ibcon#read 5, iclass 15, count 2 2006.246.07:44:00.73#ibcon#about to read 6, iclass 15, count 2 2006.246.07:44:00.73#ibcon#read 6, iclass 15, count 2 2006.246.07:44:00.73#ibcon#end of sib2, iclass 15, count 2 2006.246.07:44:00.73#ibcon#*mode == 0, iclass 15, count 2 2006.246.07:44:00.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.07:44:00.73#ibcon#[27=AT01-04\r\n] 2006.246.07:44:00.73#ibcon#*before write, iclass 15, count 2 2006.246.07:44:00.73#ibcon#enter sib2, iclass 15, count 2 2006.246.07:44:00.73#ibcon#flushed, iclass 15, count 2 2006.246.07:44:00.73#ibcon#about to write, iclass 15, count 2 2006.246.07:44:00.73#ibcon#wrote, iclass 15, count 2 2006.246.07:44:00.73#ibcon#about to read 3, iclass 15, count 2 2006.246.07:44:00.76#ibcon#read 3, iclass 15, count 2 2006.246.07:44:00.76#ibcon#about to read 4, iclass 15, count 2 2006.246.07:44:00.76#ibcon#read 4, iclass 15, count 2 2006.246.07:44:00.76#ibcon#about to read 5, iclass 15, count 2 2006.246.07:44:00.76#ibcon#read 5, iclass 15, count 2 2006.246.07:44:00.76#ibcon#about to read 6, iclass 15, count 2 2006.246.07:44:00.76#ibcon#read 6, iclass 15, count 2 2006.246.07:44:00.76#ibcon#end of sib2, iclass 15, count 2 2006.246.07:44:00.76#ibcon#*after write, iclass 15, count 2 2006.246.07:44:00.76#ibcon#*before return 0, iclass 15, count 2 2006.246.07:44:00.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:44:00.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:44:00.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.07:44:00.76#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:00.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:44:00.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:44:00.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:44:00.88#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:44:00.88#ibcon#first serial, iclass 15, count 0 2006.246.07:44:00.88#ibcon#enter sib2, iclass 15, count 0 2006.246.07:44:00.88#ibcon#flushed, iclass 15, count 0 2006.246.07:44:00.88#ibcon#about to write, iclass 15, count 0 2006.246.07:44:00.88#ibcon#wrote, iclass 15, count 0 2006.246.07:44:00.88#ibcon#about to read 3, iclass 15, count 0 2006.246.07:44:00.90#ibcon#read 3, iclass 15, count 0 2006.246.07:44:00.90#ibcon#about to read 4, iclass 15, count 0 2006.246.07:44:00.90#ibcon#read 4, iclass 15, count 0 2006.246.07:44:00.90#ibcon#about to read 5, iclass 15, count 0 2006.246.07:44:00.90#ibcon#read 5, iclass 15, count 0 2006.246.07:44:00.90#ibcon#about to read 6, iclass 15, count 0 2006.246.07:44:00.90#ibcon#read 6, iclass 15, count 0 2006.246.07:44:00.90#ibcon#end of sib2, iclass 15, count 0 2006.246.07:44:00.90#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:44:00.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:44:00.90#ibcon#[27=USB\r\n] 2006.246.07:44:00.90#ibcon#*before write, iclass 15, count 0 2006.246.07:44:00.90#ibcon#enter sib2, iclass 15, count 0 2006.246.07:44:00.90#ibcon#flushed, iclass 15, count 0 2006.246.07:44:00.90#ibcon#about to write, iclass 15, count 0 2006.246.07:44:00.90#ibcon#wrote, iclass 15, count 0 2006.246.07:44:00.90#ibcon#about to read 3, iclass 15, count 0 2006.246.07:44:00.93#ibcon#read 3, iclass 15, count 0 2006.246.07:44:00.93#ibcon#about to read 4, iclass 15, count 0 2006.246.07:44:00.93#ibcon#read 4, iclass 15, count 0 2006.246.07:44:00.93#ibcon#about to read 5, iclass 15, count 0 2006.246.07:44:00.93#ibcon#read 5, iclass 15, count 0 2006.246.07:44:00.93#ibcon#about to read 6, iclass 15, count 0 2006.246.07:44:00.93#ibcon#read 6, iclass 15, count 0 2006.246.07:44:00.93#ibcon#end of sib2, iclass 15, count 0 2006.246.07:44:00.93#ibcon#*after write, iclass 15, count 0 2006.246.07:44:00.93#ibcon#*before return 0, iclass 15, count 0 2006.246.07:44:00.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:44:00.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:44:00.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:44:00.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:44:00.93$vc4f8/vblo=2,640.99 2006.246.07:44:00.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:44:00.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:44:00.93#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:00.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:44:00.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:44:00.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:44:00.93#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:44:00.93#ibcon#first serial, iclass 17, count 0 2006.246.07:44:00.93#ibcon#enter sib2, iclass 17, count 0 2006.246.07:44:00.93#ibcon#flushed, iclass 17, count 0 2006.246.07:44:00.93#ibcon#about to write, iclass 17, count 0 2006.246.07:44:00.93#ibcon#wrote, iclass 17, count 0 2006.246.07:44:00.93#ibcon#about to read 3, iclass 17, count 0 2006.246.07:44:00.95#ibcon#read 3, iclass 17, count 0 2006.246.07:44:00.95#ibcon#about to read 4, iclass 17, count 0 2006.246.07:44:00.95#ibcon#read 4, iclass 17, count 0 2006.246.07:44:00.95#ibcon#about to read 5, iclass 17, count 0 2006.246.07:44:00.95#ibcon#read 5, iclass 17, count 0 2006.246.07:44:00.95#ibcon#about to read 6, iclass 17, count 0 2006.246.07:44:00.95#ibcon#read 6, iclass 17, count 0 2006.246.07:44:00.95#ibcon#end of sib2, iclass 17, count 0 2006.246.07:44:00.95#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:44:00.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:44:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:44:00.95#ibcon#*before write, iclass 17, count 0 2006.246.07:44:00.95#ibcon#enter sib2, iclass 17, count 0 2006.246.07:44:00.95#ibcon#flushed, iclass 17, count 0 2006.246.07:44:00.95#ibcon#about to write, iclass 17, count 0 2006.246.07:44:00.95#ibcon#wrote, iclass 17, count 0 2006.246.07:44:00.95#ibcon#about to read 3, iclass 17, count 0 2006.246.07:44:00.99#ibcon#read 3, iclass 17, count 0 2006.246.07:44:00.99#ibcon#about to read 4, iclass 17, count 0 2006.246.07:44:00.99#ibcon#read 4, iclass 17, count 0 2006.246.07:44:00.99#ibcon#about to read 5, iclass 17, count 0 2006.246.07:44:00.99#ibcon#read 5, iclass 17, count 0 2006.246.07:44:00.99#ibcon#about to read 6, iclass 17, count 0 2006.246.07:44:00.99#ibcon#read 6, iclass 17, count 0 2006.246.07:44:00.99#ibcon#end of sib2, iclass 17, count 0 2006.246.07:44:00.99#ibcon#*after write, iclass 17, count 0 2006.246.07:44:00.99#ibcon#*before return 0, iclass 17, count 0 2006.246.07:44:00.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:44:00.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:44:00.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:44:00.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:44:00.99$vc4f8/vb=2,4 2006.246.07:44:00.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.07:44:00.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.07:44:00.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:00.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:44:01.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:44:01.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:44:01.05#ibcon#enter wrdev, iclass 19, count 2 2006.246.07:44:01.05#ibcon#first serial, iclass 19, count 2 2006.246.07:44:01.06#ibcon#enter sib2, iclass 19, count 2 2006.246.07:44:01.06#ibcon#flushed, iclass 19, count 2 2006.246.07:44:01.06#ibcon#about to write, iclass 19, count 2 2006.246.07:44:01.06#ibcon#wrote, iclass 19, count 2 2006.246.07:44:01.06#ibcon#about to read 3, iclass 19, count 2 2006.246.07:44:01.07#ibcon#read 3, iclass 19, count 2 2006.246.07:44:01.07#ibcon#about to read 4, iclass 19, count 2 2006.246.07:44:01.07#ibcon#read 4, iclass 19, count 2 2006.246.07:44:01.07#ibcon#about to read 5, iclass 19, count 2 2006.246.07:44:01.07#ibcon#read 5, iclass 19, count 2 2006.246.07:44:01.07#ibcon#about to read 6, iclass 19, count 2 2006.246.07:44:01.07#ibcon#read 6, iclass 19, count 2 2006.246.07:44:01.07#ibcon#end of sib2, iclass 19, count 2 2006.246.07:44:01.07#ibcon#*mode == 0, iclass 19, count 2 2006.246.07:44:01.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.07:44:01.07#ibcon#[27=AT02-04\r\n] 2006.246.07:44:01.07#ibcon#*before write, iclass 19, count 2 2006.246.07:44:01.07#ibcon#enter sib2, iclass 19, count 2 2006.246.07:44:01.07#ibcon#flushed, iclass 19, count 2 2006.246.07:44:01.07#ibcon#about to write, iclass 19, count 2 2006.246.07:44:01.07#ibcon#wrote, iclass 19, count 2 2006.246.07:44:01.07#ibcon#about to read 3, iclass 19, count 2 2006.246.07:44:01.10#ibcon#read 3, iclass 19, count 2 2006.246.07:44:01.10#ibcon#about to read 4, iclass 19, count 2 2006.246.07:44:01.10#ibcon#read 4, iclass 19, count 2 2006.246.07:44:01.10#ibcon#about to read 5, iclass 19, count 2 2006.246.07:44:01.10#ibcon#read 5, iclass 19, count 2 2006.246.07:44:01.10#ibcon#about to read 6, iclass 19, count 2 2006.246.07:44:01.10#ibcon#read 6, iclass 19, count 2 2006.246.07:44:01.10#ibcon#end of sib2, iclass 19, count 2 2006.246.07:44:01.10#ibcon#*after write, iclass 19, count 2 2006.246.07:44:01.10#ibcon#*before return 0, iclass 19, count 2 2006.246.07:44:01.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:44:01.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:44:01.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.07:44:01.10#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:01.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:44:01.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:44:01.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:44:01.22#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:44:01.22#ibcon#first serial, iclass 19, count 0 2006.246.07:44:01.22#ibcon#enter sib2, iclass 19, count 0 2006.246.07:44:01.22#ibcon#flushed, iclass 19, count 0 2006.246.07:44:01.22#ibcon#about to write, iclass 19, count 0 2006.246.07:44:01.22#ibcon#wrote, iclass 19, count 0 2006.246.07:44:01.22#ibcon#about to read 3, iclass 19, count 0 2006.246.07:44:01.24#ibcon#read 3, iclass 19, count 0 2006.246.07:44:01.24#ibcon#about to read 4, iclass 19, count 0 2006.246.07:44:01.24#ibcon#read 4, iclass 19, count 0 2006.246.07:44:01.24#ibcon#about to read 5, iclass 19, count 0 2006.246.07:44:01.24#ibcon#read 5, iclass 19, count 0 2006.246.07:44:01.24#ibcon#about to read 6, iclass 19, count 0 2006.246.07:44:01.24#ibcon#read 6, iclass 19, count 0 2006.246.07:44:01.24#ibcon#end of sib2, iclass 19, count 0 2006.246.07:44:01.24#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:44:01.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:44:01.24#ibcon#[27=USB\r\n] 2006.246.07:44:01.24#ibcon#*before write, iclass 19, count 0 2006.246.07:44:01.24#ibcon#enter sib2, iclass 19, count 0 2006.246.07:44:01.24#ibcon#flushed, iclass 19, count 0 2006.246.07:44:01.24#ibcon#about to write, iclass 19, count 0 2006.246.07:44:01.24#ibcon#wrote, iclass 19, count 0 2006.246.07:44:01.24#ibcon#about to read 3, iclass 19, count 0 2006.246.07:44:01.27#ibcon#read 3, iclass 19, count 0 2006.246.07:44:01.27#ibcon#about to read 4, iclass 19, count 0 2006.246.07:44:01.27#ibcon#read 4, iclass 19, count 0 2006.246.07:44:01.27#ibcon#about to read 5, iclass 19, count 0 2006.246.07:44:01.27#ibcon#read 5, iclass 19, count 0 2006.246.07:44:01.27#ibcon#about to read 6, iclass 19, count 0 2006.246.07:44:01.27#ibcon#read 6, iclass 19, count 0 2006.246.07:44:01.27#ibcon#end of sib2, iclass 19, count 0 2006.246.07:44:01.27#ibcon#*after write, iclass 19, count 0 2006.246.07:44:01.27#ibcon#*before return 0, iclass 19, count 0 2006.246.07:44:01.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:44:01.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:44:01.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:44:01.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:44:01.27$vc4f8/vblo=3,656.99 2006.246.07:44:01.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.07:44:01.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.07:44:01.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:01.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:44:01.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:44:01.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:44:01.27#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:44:01.27#ibcon#first serial, iclass 21, count 0 2006.246.07:44:01.27#ibcon#enter sib2, iclass 21, count 0 2006.246.07:44:01.27#ibcon#flushed, iclass 21, count 0 2006.246.07:44:01.27#ibcon#about to write, iclass 21, count 0 2006.246.07:44:01.27#ibcon#wrote, iclass 21, count 0 2006.246.07:44:01.27#ibcon#about to read 3, iclass 21, count 0 2006.246.07:44:01.29#ibcon#read 3, iclass 21, count 0 2006.246.07:44:01.29#ibcon#about to read 4, iclass 21, count 0 2006.246.07:44:01.29#ibcon#read 4, iclass 21, count 0 2006.246.07:44:01.29#ibcon#about to read 5, iclass 21, count 0 2006.246.07:44:01.29#ibcon#read 5, iclass 21, count 0 2006.246.07:44:01.29#ibcon#about to read 6, iclass 21, count 0 2006.246.07:44:01.29#ibcon#read 6, iclass 21, count 0 2006.246.07:44:01.29#ibcon#end of sib2, iclass 21, count 0 2006.246.07:44:01.29#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:44:01.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:44:01.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:44:01.29#ibcon#*before write, iclass 21, count 0 2006.246.07:44:01.29#ibcon#enter sib2, iclass 21, count 0 2006.246.07:44:01.29#ibcon#flushed, iclass 21, count 0 2006.246.07:44:01.29#ibcon#about to write, iclass 21, count 0 2006.246.07:44:01.29#ibcon#wrote, iclass 21, count 0 2006.246.07:44:01.29#ibcon#about to read 3, iclass 21, count 0 2006.246.07:44:01.33#ibcon#read 3, iclass 21, count 0 2006.246.07:44:01.33#ibcon#about to read 4, iclass 21, count 0 2006.246.07:44:01.33#ibcon#read 4, iclass 21, count 0 2006.246.07:44:01.33#ibcon#about to read 5, iclass 21, count 0 2006.246.07:44:01.33#ibcon#read 5, iclass 21, count 0 2006.246.07:44:01.33#ibcon#about to read 6, iclass 21, count 0 2006.246.07:44:01.33#ibcon#read 6, iclass 21, count 0 2006.246.07:44:01.33#ibcon#end of sib2, iclass 21, count 0 2006.246.07:44:01.33#ibcon#*after write, iclass 21, count 0 2006.246.07:44:01.33#ibcon#*before return 0, iclass 21, count 0 2006.246.07:44:01.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:44:01.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:44:01.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:44:01.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:44:01.33$vc4f8/vb=3,4 2006.246.07:44:01.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.07:44:01.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.07:44:01.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:01.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:44:01.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:44:01.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:44:01.39#ibcon#enter wrdev, iclass 23, count 2 2006.246.07:44:01.39#ibcon#first serial, iclass 23, count 2 2006.246.07:44:01.39#ibcon#enter sib2, iclass 23, count 2 2006.246.07:44:01.39#ibcon#flushed, iclass 23, count 2 2006.246.07:44:01.39#ibcon#about to write, iclass 23, count 2 2006.246.07:44:01.39#ibcon#wrote, iclass 23, count 2 2006.246.07:44:01.39#ibcon#about to read 3, iclass 23, count 2 2006.246.07:44:01.41#ibcon#read 3, iclass 23, count 2 2006.246.07:44:01.41#ibcon#about to read 4, iclass 23, count 2 2006.246.07:44:01.41#ibcon#read 4, iclass 23, count 2 2006.246.07:44:01.41#ibcon#about to read 5, iclass 23, count 2 2006.246.07:44:01.41#ibcon#read 5, iclass 23, count 2 2006.246.07:44:01.41#ibcon#about to read 6, iclass 23, count 2 2006.246.07:44:01.41#ibcon#read 6, iclass 23, count 2 2006.246.07:44:01.41#ibcon#end of sib2, iclass 23, count 2 2006.246.07:44:01.41#ibcon#*mode == 0, iclass 23, count 2 2006.246.07:44:01.41#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.07:44:01.41#ibcon#[27=AT03-04\r\n] 2006.246.07:44:01.41#ibcon#*before write, iclass 23, count 2 2006.246.07:44:01.41#ibcon#enter sib2, iclass 23, count 2 2006.246.07:44:01.41#ibcon#flushed, iclass 23, count 2 2006.246.07:44:01.41#ibcon#about to write, iclass 23, count 2 2006.246.07:44:01.41#ibcon#wrote, iclass 23, count 2 2006.246.07:44:01.41#ibcon#about to read 3, iclass 23, count 2 2006.246.07:44:01.44#ibcon#read 3, iclass 23, count 2 2006.246.07:44:01.44#ibcon#about to read 4, iclass 23, count 2 2006.246.07:44:01.44#ibcon#read 4, iclass 23, count 2 2006.246.07:44:01.44#ibcon#about to read 5, iclass 23, count 2 2006.246.07:44:01.44#ibcon#read 5, iclass 23, count 2 2006.246.07:44:01.44#ibcon#about to read 6, iclass 23, count 2 2006.246.07:44:01.44#ibcon#read 6, iclass 23, count 2 2006.246.07:44:01.44#ibcon#end of sib2, iclass 23, count 2 2006.246.07:44:01.44#ibcon#*after write, iclass 23, count 2 2006.246.07:44:01.44#ibcon#*before return 0, iclass 23, count 2 2006.246.07:44:01.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:44:01.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:44:01.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.07:44:01.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:01.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:44:01.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:44:01.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:44:01.56#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:44:01.56#ibcon#first serial, iclass 23, count 0 2006.246.07:44:01.56#ibcon#enter sib2, iclass 23, count 0 2006.246.07:44:01.56#ibcon#flushed, iclass 23, count 0 2006.246.07:44:01.56#ibcon#about to write, iclass 23, count 0 2006.246.07:44:01.56#ibcon#wrote, iclass 23, count 0 2006.246.07:44:01.56#ibcon#about to read 3, iclass 23, count 0 2006.246.07:44:01.58#ibcon#read 3, iclass 23, count 0 2006.246.07:44:01.58#ibcon#about to read 4, iclass 23, count 0 2006.246.07:44:01.58#ibcon#read 4, iclass 23, count 0 2006.246.07:44:01.58#ibcon#about to read 5, iclass 23, count 0 2006.246.07:44:01.58#ibcon#read 5, iclass 23, count 0 2006.246.07:44:01.58#ibcon#about to read 6, iclass 23, count 0 2006.246.07:44:01.58#ibcon#read 6, iclass 23, count 0 2006.246.07:44:01.58#ibcon#end of sib2, iclass 23, count 0 2006.246.07:44:01.58#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:44:01.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:44:01.58#ibcon#[27=USB\r\n] 2006.246.07:44:01.58#ibcon#*before write, iclass 23, count 0 2006.246.07:44:01.58#ibcon#enter sib2, iclass 23, count 0 2006.246.07:44:01.58#ibcon#flushed, iclass 23, count 0 2006.246.07:44:01.58#ibcon#about to write, iclass 23, count 0 2006.246.07:44:01.58#ibcon#wrote, iclass 23, count 0 2006.246.07:44:01.58#ibcon#about to read 3, iclass 23, count 0 2006.246.07:44:01.61#ibcon#read 3, iclass 23, count 0 2006.246.07:44:01.61#ibcon#about to read 4, iclass 23, count 0 2006.246.07:44:01.61#ibcon#read 4, iclass 23, count 0 2006.246.07:44:01.61#ibcon#about to read 5, iclass 23, count 0 2006.246.07:44:01.61#ibcon#read 5, iclass 23, count 0 2006.246.07:44:01.61#ibcon#about to read 6, iclass 23, count 0 2006.246.07:44:01.61#ibcon#read 6, iclass 23, count 0 2006.246.07:44:01.61#ibcon#end of sib2, iclass 23, count 0 2006.246.07:44:01.61#ibcon#*after write, iclass 23, count 0 2006.246.07:44:01.61#ibcon#*before return 0, iclass 23, count 0 2006.246.07:44:01.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:44:01.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:44:01.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:44:01.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:44:01.61$vc4f8/vblo=4,712.99 2006.246.07:44:01.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.07:44:01.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.07:44:01.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:01.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:44:01.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:44:01.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:44:01.61#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:44:01.61#ibcon#first serial, iclass 25, count 0 2006.246.07:44:01.61#ibcon#enter sib2, iclass 25, count 0 2006.246.07:44:01.61#ibcon#flushed, iclass 25, count 0 2006.246.07:44:01.61#ibcon#about to write, iclass 25, count 0 2006.246.07:44:01.61#ibcon#wrote, iclass 25, count 0 2006.246.07:44:01.61#ibcon#about to read 3, iclass 25, count 0 2006.246.07:44:01.63#ibcon#read 3, iclass 25, count 0 2006.246.07:44:01.63#ibcon#about to read 4, iclass 25, count 0 2006.246.07:44:01.63#ibcon#read 4, iclass 25, count 0 2006.246.07:44:01.63#ibcon#about to read 5, iclass 25, count 0 2006.246.07:44:01.63#ibcon#read 5, iclass 25, count 0 2006.246.07:44:01.63#ibcon#about to read 6, iclass 25, count 0 2006.246.07:44:01.63#ibcon#read 6, iclass 25, count 0 2006.246.07:44:01.63#ibcon#end of sib2, iclass 25, count 0 2006.246.07:44:01.63#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:44:01.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:44:01.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:44:01.63#ibcon#*before write, iclass 25, count 0 2006.246.07:44:01.63#ibcon#enter sib2, iclass 25, count 0 2006.246.07:44:01.63#ibcon#flushed, iclass 25, count 0 2006.246.07:44:01.63#ibcon#about to write, iclass 25, count 0 2006.246.07:44:01.63#ibcon#wrote, iclass 25, count 0 2006.246.07:44:01.63#ibcon#about to read 3, iclass 25, count 0 2006.246.07:44:01.67#ibcon#read 3, iclass 25, count 0 2006.246.07:44:01.67#ibcon#about to read 4, iclass 25, count 0 2006.246.07:44:01.67#ibcon#read 4, iclass 25, count 0 2006.246.07:44:01.67#ibcon#about to read 5, iclass 25, count 0 2006.246.07:44:01.67#ibcon#read 5, iclass 25, count 0 2006.246.07:44:01.67#ibcon#about to read 6, iclass 25, count 0 2006.246.07:44:01.67#ibcon#read 6, iclass 25, count 0 2006.246.07:44:01.67#ibcon#end of sib2, iclass 25, count 0 2006.246.07:44:01.67#ibcon#*after write, iclass 25, count 0 2006.246.07:44:01.67#ibcon#*before return 0, iclass 25, count 0 2006.246.07:44:01.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:44:01.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:44:01.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:44:01.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:44:01.67$vc4f8/vb=4,4 2006.246.07:44:01.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.07:44:01.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.07:44:01.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:01.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:44:01.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:44:01.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:44:01.73#ibcon#enter wrdev, iclass 27, count 2 2006.246.07:44:01.73#ibcon#first serial, iclass 27, count 2 2006.246.07:44:01.73#ibcon#enter sib2, iclass 27, count 2 2006.246.07:44:01.73#ibcon#flushed, iclass 27, count 2 2006.246.07:44:01.73#ibcon#about to write, iclass 27, count 2 2006.246.07:44:01.73#ibcon#wrote, iclass 27, count 2 2006.246.07:44:01.73#ibcon#about to read 3, iclass 27, count 2 2006.246.07:44:01.75#ibcon#read 3, iclass 27, count 2 2006.246.07:44:01.75#ibcon#about to read 4, iclass 27, count 2 2006.246.07:44:01.75#ibcon#read 4, iclass 27, count 2 2006.246.07:44:01.75#ibcon#about to read 5, iclass 27, count 2 2006.246.07:44:01.75#ibcon#read 5, iclass 27, count 2 2006.246.07:44:01.75#ibcon#about to read 6, iclass 27, count 2 2006.246.07:44:01.75#ibcon#read 6, iclass 27, count 2 2006.246.07:44:01.75#ibcon#end of sib2, iclass 27, count 2 2006.246.07:44:01.75#ibcon#*mode == 0, iclass 27, count 2 2006.246.07:44:01.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.07:44:01.75#ibcon#[27=AT04-04\r\n] 2006.246.07:44:01.75#ibcon#*before write, iclass 27, count 2 2006.246.07:44:01.75#ibcon#enter sib2, iclass 27, count 2 2006.246.07:44:01.75#ibcon#flushed, iclass 27, count 2 2006.246.07:44:01.75#ibcon#about to write, iclass 27, count 2 2006.246.07:44:01.75#ibcon#wrote, iclass 27, count 2 2006.246.07:44:01.75#ibcon#about to read 3, iclass 27, count 2 2006.246.07:44:01.78#ibcon#read 3, iclass 27, count 2 2006.246.07:44:01.78#ibcon#about to read 4, iclass 27, count 2 2006.246.07:44:01.78#ibcon#read 4, iclass 27, count 2 2006.246.07:44:01.78#ibcon#about to read 5, iclass 27, count 2 2006.246.07:44:01.78#ibcon#read 5, iclass 27, count 2 2006.246.07:44:01.78#ibcon#about to read 6, iclass 27, count 2 2006.246.07:44:01.78#ibcon#read 6, iclass 27, count 2 2006.246.07:44:01.78#ibcon#end of sib2, iclass 27, count 2 2006.246.07:44:01.78#ibcon#*after write, iclass 27, count 2 2006.246.07:44:01.78#ibcon#*before return 0, iclass 27, count 2 2006.246.07:44:01.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:44:01.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:44:01.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.07:44:01.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:01.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:44:01.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:44:01.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:44:01.90#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:44:01.90#ibcon#first serial, iclass 27, count 0 2006.246.07:44:01.90#ibcon#enter sib2, iclass 27, count 0 2006.246.07:44:01.90#ibcon#flushed, iclass 27, count 0 2006.246.07:44:01.90#ibcon#about to write, iclass 27, count 0 2006.246.07:44:01.90#ibcon#wrote, iclass 27, count 0 2006.246.07:44:01.90#ibcon#about to read 3, iclass 27, count 0 2006.246.07:44:01.92#ibcon#read 3, iclass 27, count 0 2006.246.07:44:01.92#ibcon#about to read 4, iclass 27, count 0 2006.246.07:44:01.92#ibcon#read 4, iclass 27, count 0 2006.246.07:44:01.92#ibcon#about to read 5, iclass 27, count 0 2006.246.07:44:01.92#ibcon#read 5, iclass 27, count 0 2006.246.07:44:01.92#ibcon#about to read 6, iclass 27, count 0 2006.246.07:44:01.92#ibcon#read 6, iclass 27, count 0 2006.246.07:44:01.92#ibcon#end of sib2, iclass 27, count 0 2006.246.07:44:01.92#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:44:01.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:44:01.92#ibcon#[27=USB\r\n] 2006.246.07:44:01.92#ibcon#*before write, iclass 27, count 0 2006.246.07:44:01.92#ibcon#enter sib2, iclass 27, count 0 2006.246.07:44:01.92#ibcon#flushed, iclass 27, count 0 2006.246.07:44:01.92#ibcon#about to write, iclass 27, count 0 2006.246.07:44:01.92#ibcon#wrote, iclass 27, count 0 2006.246.07:44:01.92#ibcon#about to read 3, iclass 27, count 0 2006.246.07:44:01.95#ibcon#read 3, iclass 27, count 0 2006.246.07:44:01.95#ibcon#about to read 4, iclass 27, count 0 2006.246.07:44:01.95#ibcon#read 4, iclass 27, count 0 2006.246.07:44:01.95#ibcon#about to read 5, iclass 27, count 0 2006.246.07:44:01.95#ibcon#read 5, iclass 27, count 0 2006.246.07:44:01.95#ibcon#about to read 6, iclass 27, count 0 2006.246.07:44:01.95#ibcon#read 6, iclass 27, count 0 2006.246.07:44:01.95#ibcon#end of sib2, iclass 27, count 0 2006.246.07:44:01.95#ibcon#*after write, iclass 27, count 0 2006.246.07:44:01.95#ibcon#*before return 0, iclass 27, count 0 2006.246.07:44:01.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:44:01.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:44:01.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:44:01.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:44:01.95$vc4f8/vblo=5,744.99 2006.246.07:44:01.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:44:01.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:44:01.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:01.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:44:01.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:44:01.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:44:01.95#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:44:01.95#ibcon#first serial, iclass 29, count 0 2006.246.07:44:01.95#ibcon#enter sib2, iclass 29, count 0 2006.246.07:44:01.95#ibcon#flushed, iclass 29, count 0 2006.246.07:44:01.95#ibcon#about to write, iclass 29, count 0 2006.246.07:44:01.95#ibcon#wrote, iclass 29, count 0 2006.246.07:44:01.95#ibcon#about to read 3, iclass 29, count 0 2006.246.07:44:01.97#ibcon#read 3, iclass 29, count 0 2006.246.07:44:01.97#ibcon#about to read 4, iclass 29, count 0 2006.246.07:44:01.97#ibcon#read 4, iclass 29, count 0 2006.246.07:44:01.97#ibcon#about to read 5, iclass 29, count 0 2006.246.07:44:01.97#ibcon#read 5, iclass 29, count 0 2006.246.07:44:01.97#ibcon#about to read 6, iclass 29, count 0 2006.246.07:44:01.97#ibcon#read 6, iclass 29, count 0 2006.246.07:44:01.97#ibcon#end of sib2, iclass 29, count 0 2006.246.07:44:01.97#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:44:01.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:44:01.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:44:01.97#ibcon#*before write, iclass 29, count 0 2006.246.07:44:01.97#ibcon#enter sib2, iclass 29, count 0 2006.246.07:44:01.97#ibcon#flushed, iclass 29, count 0 2006.246.07:44:01.97#ibcon#about to write, iclass 29, count 0 2006.246.07:44:01.97#ibcon#wrote, iclass 29, count 0 2006.246.07:44:01.97#ibcon#about to read 3, iclass 29, count 0 2006.246.07:44:02.01#ibcon#read 3, iclass 29, count 0 2006.246.07:44:02.01#ibcon#about to read 4, iclass 29, count 0 2006.246.07:44:02.01#ibcon#read 4, iclass 29, count 0 2006.246.07:44:02.01#ibcon#about to read 5, iclass 29, count 0 2006.246.07:44:02.01#ibcon#read 5, iclass 29, count 0 2006.246.07:44:02.01#ibcon#about to read 6, iclass 29, count 0 2006.246.07:44:02.01#ibcon#read 6, iclass 29, count 0 2006.246.07:44:02.01#ibcon#end of sib2, iclass 29, count 0 2006.246.07:44:02.01#ibcon#*after write, iclass 29, count 0 2006.246.07:44:02.01#ibcon#*before return 0, iclass 29, count 0 2006.246.07:44:02.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:44:02.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:44:02.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:44:02.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:44:02.01$vc4f8/vb=5,3 2006.246.07:44:02.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.07:44:02.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.07:44:02.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:02.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:44:02.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:44:02.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:44:02.07#ibcon#enter wrdev, iclass 31, count 2 2006.246.07:44:02.07#ibcon#first serial, iclass 31, count 2 2006.246.07:44:02.07#ibcon#enter sib2, iclass 31, count 2 2006.246.07:44:02.07#ibcon#flushed, iclass 31, count 2 2006.246.07:44:02.07#ibcon#about to write, iclass 31, count 2 2006.246.07:44:02.07#ibcon#wrote, iclass 31, count 2 2006.246.07:44:02.07#ibcon#about to read 3, iclass 31, count 2 2006.246.07:44:02.09#ibcon#read 3, iclass 31, count 2 2006.246.07:44:02.09#ibcon#about to read 4, iclass 31, count 2 2006.246.07:44:02.09#ibcon#read 4, iclass 31, count 2 2006.246.07:44:02.09#ibcon#about to read 5, iclass 31, count 2 2006.246.07:44:02.09#ibcon#read 5, iclass 31, count 2 2006.246.07:44:02.09#ibcon#about to read 6, iclass 31, count 2 2006.246.07:44:02.09#ibcon#read 6, iclass 31, count 2 2006.246.07:44:02.09#ibcon#end of sib2, iclass 31, count 2 2006.246.07:44:02.09#ibcon#*mode == 0, iclass 31, count 2 2006.246.07:44:02.09#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.07:44:02.09#ibcon#[27=AT05-03\r\n] 2006.246.07:44:02.09#ibcon#*before write, iclass 31, count 2 2006.246.07:44:02.09#ibcon#enter sib2, iclass 31, count 2 2006.246.07:44:02.09#ibcon#flushed, iclass 31, count 2 2006.246.07:44:02.09#ibcon#about to write, iclass 31, count 2 2006.246.07:44:02.09#ibcon#wrote, iclass 31, count 2 2006.246.07:44:02.09#ibcon#about to read 3, iclass 31, count 2 2006.246.07:44:02.12#ibcon#read 3, iclass 31, count 2 2006.246.07:44:02.12#ibcon#about to read 4, iclass 31, count 2 2006.246.07:44:02.12#ibcon#read 4, iclass 31, count 2 2006.246.07:44:02.12#ibcon#about to read 5, iclass 31, count 2 2006.246.07:44:02.12#ibcon#read 5, iclass 31, count 2 2006.246.07:44:02.12#ibcon#about to read 6, iclass 31, count 2 2006.246.07:44:02.12#ibcon#read 6, iclass 31, count 2 2006.246.07:44:02.12#ibcon#end of sib2, iclass 31, count 2 2006.246.07:44:02.12#ibcon#*after write, iclass 31, count 2 2006.246.07:44:02.12#ibcon#*before return 0, iclass 31, count 2 2006.246.07:44:02.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:44:02.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:44:02.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.07:44:02.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:02.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:44:02.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:44:02.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:44:02.24#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:44:02.24#ibcon#first serial, iclass 31, count 0 2006.246.07:44:02.24#ibcon#enter sib2, iclass 31, count 0 2006.246.07:44:02.24#ibcon#flushed, iclass 31, count 0 2006.246.07:44:02.24#ibcon#about to write, iclass 31, count 0 2006.246.07:44:02.24#ibcon#wrote, iclass 31, count 0 2006.246.07:44:02.24#ibcon#about to read 3, iclass 31, count 0 2006.246.07:44:02.26#ibcon#read 3, iclass 31, count 0 2006.246.07:44:02.26#ibcon#about to read 4, iclass 31, count 0 2006.246.07:44:02.26#ibcon#read 4, iclass 31, count 0 2006.246.07:44:02.26#ibcon#about to read 5, iclass 31, count 0 2006.246.07:44:02.26#ibcon#read 5, iclass 31, count 0 2006.246.07:44:02.26#ibcon#about to read 6, iclass 31, count 0 2006.246.07:44:02.26#ibcon#read 6, iclass 31, count 0 2006.246.07:44:02.26#ibcon#end of sib2, iclass 31, count 0 2006.246.07:44:02.26#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:44:02.26#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:44:02.26#ibcon#[27=USB\r\n] 2006.246.07:44:02.26#ibcon#*before write, iclass 31, count 0 2006.246.07:44:02.26#ibcon#enter sib2, iclass 31, count 0 2006.246.07:44:02.26#ibcon#flushed, iclass 31, count 0 2006.246.07:44:02.26#ibcon#about to write, iclass 31, count 0 2006.246.07:44:02.26#ibcon#wrote, iclass 31, count 0 2006.246.07:44:02.26#ibcon#about to read 3, iclass 31, count 0 2006.246.07:44:02.29#ibcon#read 3, iclass 31, count 0 2006.246.07:44:02.29#ibcon#about to read 4, iclass 31, count 0 2006.246.07:44:02.29#ibcon#read 4, iclass 31, count 0 2006.246.07:44:02.29#ibcon#about to read 5, iclass 31, count 0 2006.246.07:44:02.29#ibcon#read 5, iclass 31, count 0 2006.246.07:44:02.29#ibcon#about to read 6, iclass 31, count 0 2006.246.07:44:02.29#ibcon#read 6, iclass 31, count 0 2006.246.07:44:02.29#ibcon#end of sib2, iclass 31, count 0 2006.246.07:44:02.29#ibcon#*after write, iclass 31, count 0 2006.246.07:44:02.29#ibcon#*before return 0, iclass 31, count 0 2006.246.07:44:02.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:44:02.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:44:02.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:44:02.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:44:02.29$vc4f8/vblo=6,752.99 2006.246.07:44:02.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.07:44:02.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.07:44:02.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:44:02.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:44:02.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:44:02.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:44:02.29#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:44:02.29#ibcon#first serial, iclass 33, count 0 2006.246.07:44:02.29#ibcon#enter sib2, iclass 33, count 0 2006.246.07:44:02.29#ibcon#flushed, iclass 33, count 0 2006.246.07:44:02.29#ibcon#about to write, iclass 33, count 0 2006.246.07:44:02.29#ibcon#wrote, iclass 33, count 0 2006.246.07:44:02.29#ibcon#about to read 3, iclass 33, count 0 2006.246.07:44:02.31#ibcon#read 3, iclass 33, count 0 2006.246.07:44:02.31#ibcon#about to read 4, iclass 33, count 0 2006.246.07:44:02.31#ibcon#read 4, iclass 33, count 0 2006.246.07:44:02.31#ibcon#about to read 5, iclass 33, count 0 2006.246.07:44:02.31#ibcon#read 5, iclass 33, count 0 2006.246.07:44:02.31#ibcon#about to read 6, iclass 33, count 0 2006.246.07:44:02.31#ibcon#read 6, iclass 33, count 0 2006.246.07:44:02.31#ibcon#end of sib2, iclass 33, count 0 2006.246.07:44:02.31#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:44:02.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:44:02.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:44:02.31#ibcon#*before write, iclass 33, count 0 2006.246.07:44:02.31#ibcon#enter sib2, iclass 33, count 0 2006.246.07:44:02.31#ibcon#flushed, iclass 33, count 0 2006.246.07:44:02.31#ibcon#about to write, iclass 33, count 0 2006.246.07:44:02.31#ibcon#wrote, iclass 33, count 0 2006.246.07:44:02.31#ibcon#about to read 3, iclass 33, count 0 2006.246.07:44:02.35#ibcon#read 3, iclass 33, count 0 2006.246.07:44:02.35#ibcon#about to read 4, iclass 33, count 0 2006.246.07:44:02.35#ibcon#read 4, iclass 33, count 0 2006.246.07:44:02.35#ibcon#about to read 5, iclass 33, count 0 2006.246.07:44:02.35#ibcon#read 5, iclass 33, count 0 2006.246.07:44:02.35#ibcon#about to read 6, iclass 33, count 0 2006.246.07:44:02.35#ibcon#read 6, iclass 33, count 0 2006.246.07:44:02.35#ibcon#end of sib2, iclass 33, count 0 2006.246.07:44:02.35#ibcon#*after write, iclass 33, count 0 2006.246.07:44:02.35#ibcon#*before return 0, iclass 33, count 0 2006.246.07:44:02.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:44:02.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:44:02.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:44:02.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:44:02.35$vc4f8/vb=6,3 2006.246.07:44:02.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.07:44:02.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.07:44:02.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:44:02.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:44:02.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:44:02.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:44:02.41#ibcon#enter wrdev, iclass 35, count 2 2006.246.07:44:02.41#ibcon#first serial, iclass 35, count 2 2006.246.07:44:02.41#ibcon#enter sib2, iclass 35, count 2 2006.246.07:44:02.41#ibcon#flushed, iclass 35, count 2 2006.246.07:44:02.41#ibcon#about to write, iclass 35, count 2 2006.246.07:44:02.41#ibcon#wrote, iclass 35, count 2 2006.246.07:44:02.41#ibcon#about to read 3, iclass 35, count 2 2006.246.07:44:02.43#ibcon#read 3, iclass 35, count 2 2006.246.07:44:02.43#ibcon#about to read 4, iclass 35, count 2 2006.246.07:44:02.43#ibcon#read 4, iclass 35, count 2 2006.246.07:44:02.43#ibcon#about to read 5, iclass 35, count 2 2006.246.07:44:02.43#ibcon#read 5, iclass 35, count 2 2006.246.07:44:02.43#ibcon#about to read 6, iclass 35, count 2 2006.246.07:44:02.43#ibcon#read 6, iclass 35, count 2 2006.246.07:44:02.43#ibcon#end of sib2, iclass 35, count 2 2006.246.07:44:02.43#ibcon#*mode == 0, iclass 35, count 2 2006.246.07:44:02.43#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.07:44:02.43#ibcon#[27=AT06-03\r\n] 2006.246.07:44:02.43#ibcon#*before write, iclass 35, count 2 2006.246.07:44:02.43#ibcon#enter sib2, iclass 35, count 2 2006.246.07:44:02.43#ibcon#flushed, iclass 35, count 2 2006.246.07:44:02.43#ibcon#about to write, iclass 35, count 2 2006.246.07:44:02.43#ibcon#wrote, iclass 35, count 2 2006.246.07:44:02.43#ibcon#about to read 3, iclass 35, count 2 2006.246.07:44:02.46#ibcon#read 3, iclass 35, count 2 2006.246.07:44:02.46#ibcon#about to read 4, iclass 35, count 2 2006.246.07:44:02.46#ibcon#read 4, iclass 35, count 2 2006.246.07:44:02.46#ibcon#about to read 5, iclass 35, count 2 2006.246.07:44:02.46#ibcon#read 5, iclass 35, count 2 2006.246.07:44:02.46#ibcon#about to read 6, iclass 35, count 2 2006.246.07:44:02.46#ibcon#read 6, iclass 35, count 2 2006.246.07:44:02.46#ibcon#end of sib2, iclass 35, count 2 2006.246.07:44:02.46#ibcon#*after write, iclass 35, count 2 2006.246.07:44:02.46#ibcon#*before return 0, iclass 35, count 2 2006.246.07:44:02.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:44:02.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:44:02.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.07:44:02.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:44:02.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:44:02.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:44:02.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:44:02.58#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:44:02.58#ibcon#first serial, iclass 35, count 0 2006.246.07:44:02.58#ibcon#enter sib2, iclass 35, count 0 2006.246.07:44:02.58#ibcon#flushed, iclass 35, count 0 2006.246.07:44:02.58#ibcon#about to write, iclass 35, count 0 2006.246.07:44:02.58#ibcon#wrote, iclass 35, count 0 2006.246.07:44:02.58#ibcon#about to read 3, iclass 35, count 0 2006.246.07:44:02.60#ibcon#read 3, iclass 35, count 0 2006.246.07:44:02.60#ibcon#about to read 4, iclass 35, count 0 2006.246.07:44:02.60#ibcon#read 4, iclass 35, count 0 2006.246.07:44:02.60#ibcon#about to read 5, iclass 35, count 0 2006.246.07:44:02.60#ibcon#read 5, iclass 35, count 0 2006.246.07:44:02.60#ibcon#about to read 6, iclass 35, count 0 2006.246.07:44:02.60#ibcon#read 6, iclass 35, count 0 2006.246.07:44:02.60#ibcon#end of sib2, iclass 35, count 0 2006.246.07:44:02.60#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:44:02.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:44:02.60#ibcon#[27=USB\r\n] 2006.246.07:44:02.60#ibcon#*before write, iclass 35, count 0 2006.246.07:44:02.60#ibcon#enter sib2, iclass 35, count 0 2006.246.07:44:02.60#ibcon#flushed, iclass 35, count 0 2006.246.07:44:02.60#ibcon#about to write, iclass 35, count 0 2006.246.07:44:02.60#ibcon#wrote, iclass 35, count 0 2006.246.07:44:02.60#ibcon#about to read 3, iclass 35, count 0 2006.246.07:44:02.63#ibcon#read 3, iclass 35, count 0 2006.246.07:44:02.63#ibcon#about to read 4, iclass 35, count 0 2006.246.07:44:02.63#ibcon#read 4, iclass 35, count 0 2006.246.07:44:02.63#ibcon#about to read 5, iclass 35, count 0 2006.246.07:44:02.63#ibcon#read 5, iclass 35, count 0 2006.246.07:44:02.63#ibcon#about to read 6, iclass 35, count 0 2006.246.07:44:02.63#ibcon#read 6, iclass 35, count 0 2006.246.07:44:02.63#ibcon#end of sib2, iclass 35, count 0 2006.246.07:44:02.63#ibcon#*after write, iclass 35, count 0 2006.246.07:44:02.63#ibcon#*before return 0, iclass 35, count 0 2006.246.07:44:02.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:44:02.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:44:02.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:44:02.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:44:02.63$vc4f8/vabw=wide 2006.246.07:44:02.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.07:44:02.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.07:44:02.63#ibcon#ireg 8 cls_cnt 0 2006.246.07:44:02.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:44:02.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:44:02.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:44:02.63#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:44:02.63#ibcon#first serial, iclass 37, count 0 2006.246.07:44:02.63#ibcon#enter sib2, iclass 37, count 0 2006.246.07:44:02.63#ibcon#flushed, iclass 37, count 0 2006.246.07:44:02.63#ibcon#about to write, iclass 37, count 0 2006.246.07:44:02.63#ibcon#wrote, iclass 37, count 0 2006.246.07:44:02.63#ibcon#about to read 3, iclass 37, count 0 2006.246.07:44:02.65#ibcon#read 3, iclass 37, count 0 2006.246.07:44:02.65#ibcon#about to read 4, iclass 37, count 0 2006.246.07:44:02.65#ibcon#read 4, iclass 37, count 0 2006.246.07:44:02.65#ibcon#about to read 5, iclass 37, count 0 2006.246.07:44:02.65#ibcon#read 5, iclass 37, count 0 2006.246.07:44:02.65#ibcon#about to read 6, iclass 37, count 0 2006.246.07:44:02.65#ibcon#read 6, iclass 37, count 0 2006.246.07:44:02.65#ibcon#end of sib2, iclass 37, count 0 2006.246.07:44:02.65#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:44:02.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:44:02.65#ibcon#[25=BW32\r\n] 2006.246.07:44:02.65#ibcon#*before write, iclass 37, count 0 2006.246.07:44:02.65#ibcon#enter sib2, iclass 37, count 0 2006.246.07:44:02.65#ibcon#flushed, iclass 37, count 0 2006.246.07:44:02.65#ibcon#about to write, iclass 37, count 0 2006.246.07:44:02.65#ibcon#wrote, iclass 37, count 0 2006.246.07:44:02.65#ibcon#about to read 3, iclass 37, count 0 2006.246.07:44:02.68#ibcon#read 3, iclass 37, count 0 2006.246.07:44:02.68#ibcon#about to read 4, iclass 37, count 0 2006.246.07:44:02.68#ibcon#read 4, iclass 37, count 0 2006.246.07:44:02.68#ibcon#about to read 5, iclass 37, count 0 2006.246.07:44:02.68#ibcon#read 5, iclass 37, count 0 2006.246.07:44:02.68#ibcon#about to read 6, iclass 37, count 0 2006.246.07:44:02.68#ibcon#read 6, iclass 37, count 0 2006.246.07:44:02.68#ibcon#end of sib2, iclass 37, count 0 2006.246.07:44:02.68#ibcon#*after write, iclass 37, count 0 2006.246.07:44:02.68#ibcon#*before return 0, iclass 37, count 0 2006.246.07:44:02.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:44:02.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:44:02.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:44:02.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:44:02.68$vc4f8/vbbw=wide 2006.246.07:44:02.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:44:02.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:44:02.68#ibcon#ireg 8 cls_cnt 0 2006.246.07:44:02.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:44:02.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:44:02.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:44:02.76#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:44:02.76#ibcon#first serial, iclass 39, count 0 2006.246.07:44:02.76#ibcon#enter sib2, iclass 39, count 0 2006.246.07:44:02.76#ibcon#flushed, iclass 39, count 0 2006.246.07:44:02.76#ibcon#about to write, iclass 39, count 0 2006.246.07:44:02.76#ibcon#wrote, iclass 39, count 0 2006.246.07:44:02.76#ibcon#about to read 3, iclass 39, count 0 2006.246.07:44:02.77#ibcon#read 3, iclass 39, count 0 2006.246.07:44:02.77#ibcon#about to read 4, iclass 39, count 0 2006.246.07:44:02.77#ibcon#read 4, iclass 39, count 0 2006.246.07:44:02.77#ibcon#about to read 5, iclass 39, count 0 2006.246.07:44:02.77#ibcon#read 5, iclass 39, count 0 2006.246.07:44:02.77#ibcon#about to read 6, iclass 39, count 0 2006.246.07:44:02.77#ibcon#read 6, iclass 39, count 0 2006.246.07:44:02.77#ibcon#end of sib2, iclass 39, count 0 2006.246.07:44:02.77#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:44:02.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:44:02.77#ibcon#[27=BW32\r\n] 2006.246.07:44:02.77#ibcon#*before write, iclass 39, count 0 2006.246.07:44:02.77#ibcon#enter sib2, iclass 39, count 0 2006.246.07:44:02.77#ibcon#flushed, iclass 39, count 0 2006.246.07:44:02.78#ibcon#about to write, iclass 39, count 0 2006.246.07:44:02.78#ibcon#wrote, iclass 39, count 0 2006.246.07:44:02.78#ibcon#about to read 3, iclass 39, count 0 2006.246.07:44:02.80#ibcon#read 3, iclass 39, count 0 2006.246.07:44:02.80#ibcon#about to read 4, iclass 39, count 0 2006.246.07:44:02.80#ibcon#read 4, iclass 39, count 0 2006.246.07:44:02.80#ibcon#about to read 5, iclass 39, count 0 2006.246.07:44:02.80#ibcon#read 5, iclass 39, count 0 2006.246.07:44:02.80#ibcon#about to read 6, iclass 39, count 0 2006.246.07:44:02.80#ibcon#read 6, iclass 39, count 0 2006.246.07:44:02.80#ibcon#end of sib2, iclass 39, count 0 2006.246.07:44:02.80#ibcon#*after write, iclass 39, count 0 2006.246.07:44:02.80#ibcon#*before return 0, iclass 39, count 0 2006.246.07:44:02.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:44:02.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:44:02.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:44:02.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:44:02.80$4f8m12a/ifd4f 2006.246.07:44:02.80$ifd4f/lo= 2006.246.07:44:02.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:44:02.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:44:02.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:44:02.80$ifd4f/patch= 2006.246.07:44:02.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:44:02.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:44:02.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:44:02.81$4f8m12a/"form=m,16.000,1:2 2006.246.07:44:02.81$4f8m12a/"tpicd 2006.246.07:44:02.81$4f8m12a/echo=off 2006.246.07:44:02.81$4f8m12a/xlog=off 2006.246.07:44:02.81:!2006.246.07:44:30 2006.246.07:44:14.14#trakl#Source acquired 2006.246.07:44:14.14#flagr#flagr/antenna,acquired 2006.246.07:44:30.01:preob 2006.246.07:44:31.13/onsource/TRACKING 2006.246.07:44:31.13:!2006.246.07:44:40 2006.246.07:44:40.00:data_valid=on 2006.246.07:44:40.00:midob 2006.246.07:44:40.13/onsource/TRACKING 2006.246.07:44:40.13/wx/26.73,1005.7,75 2006.246.07:44:40.21/cable/+6.4114E-03 2006.246.07:44:41.30/va/01,08,usb,yes,31,32 2006.246.07:44:41.30/va/02,07,usb,yes,31,32 2006.246.07:44:41.30/va/03,06,usb,yes,33,33 2006.246.07:44:41.30/va/04,07,usb,yes,32,34 2006.246.07:44:41.30/va/05,07,usb,yes,34,36 2006.246.07:44:41.30/va/06,07,usb,yes,29,29 2006.246.07:44:41.30/va/07,07,usb,yes,29,29 2006.246.07:44:41.30/va/08,08,usb,yes,26,25 2006.246.07:44:41.53/valo/01,532.99,yes,locked 2006.246.07:44:41.53/valo/02,572.99,yes,locked 2006.246.07:44:41.53/valo/03,672.99,yes,locked 2006.246.07:44:41.53/valo/04,832.99,yes,locked 2006.246.07:44:41.53/valo/05,652.99,yes,locked 2006.246.07:44:41.53/valo/06,772.99,yes,locked 2006.246.07:44:41.53/valo/07,832.99,yes,locked 2006.246.07:44:41.53/valo/08,852.99,yes,locked 2006.246.07:44:42.62/vb/01,04,usb,yes,30,29 2006.246.07:44:42.62/vb/02,04,usb,yes,32,33 2006.246.07:44:42.62/vb/03,04,usb,yes,28,32 2006.246.07:44:42.62/vb/04,04,usb,yes,29,29 2006.246.07:44:42.62/vb/05,03,usb,yes,34,39 2006.246.07:44:42.62/vb/06,03,usb,yes,35,39 2006.246.07:44:42.62/vb/07,04,usb,yes,31,31 2006.246.07:44:42.62/vb/08,03,usb,yes,35,39 2006.246.07:44:42.85/vblo/01,632.99,yes,locked 2006.246.07:44:42.85/vblo/02,640.99,yes,locked 2006.246.07:44:42.85/vblo/03,656.99,yes,locked 2006.246.07:44:42.85/vblo/04,712.99,yes,locked 2006.246.07:44:42.85/vblo/05,744.99,yes,locked 2006.246.07:44:42.85/vblo/06,752.99,yes,locked 2006.246.07:44:42.85/vblo/07,734.99,yes,locked 2006.246.07:44:42.85/vblo/08,744.99,yes,locked 2006.246.07:44:43.00/vabw/8 2006.246.07:44:43.15/vbbw/8 2006.246.07:44:43.24/xfe/off,on,13.2 2006.246.07:44:43.62/ifatt/23,28,28,28 2006.246.07:44:44.07/fmout-gps/S +4.36E-07 2006.246.07:44:44.11:!2006.246.07:45:40 2006.246.07:45:40.00:data_valid=off 2006.246.07:45:40.01:postob 2006.246.07:45:40.22/cable/+6.4125E-03 2006.246.07:45:40.23/wx/26.73,1005.7,75 2006.246.07:45:41.07/fmout-gps/S +4.37E-07 2006.246.07:45:41.08:scan_name=246-0746,k06246,60 2006.246.07:45:41.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.246.07:45:41.13#flagr#flagr/antenna,new-source 2006.246.07:45:42.13:checkk5 2006.246.07:45:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:45:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:45:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:45:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:45:44.01/chk_obsdata//k5ts1/T2460744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:45:44.38/chk_obsdata//k5ts2/T2460744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:45:44.74/chk_obsdata//k5ts3/T2460744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:45:45.11/chk_obsdata//k5ts4/T2460744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:45:45.81/k5log//k5ts1_log_newline 2006.246.07:45:46.50/k5log//k5ts2_log_newline 2006.246.07:45:47.18/k5log//k5ts3_log_newline 2006.246.07:45:47.87/k5log//k5ts4_log_newline 2006.246.07:45:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:45:47.89:4f8m12a=1 2006.246.07:45:47.89$4f8m12a/echo=on 2006.246.07:45:47.89$4f8m12a/pcalon 2006.246.07:45:47.89$pcalon/"no phase cal control is implemented here 2006.246.07:45:47.89$4f8m12a/"tpicd=stop 2006.246.07:45:47.89$4f8m12a/vc4f8 2006.246.07:45:47.89$vc4f8/valo=1,532.99 2006.246.07:45:47.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.07:45:47.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.07:45:47.90#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:47.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:47.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:47.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:47.90#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:45:47.90#ibcon#first serial, iclass 10, count 0 2006.246.07:45:47.90#ibcon#enter sib2, iclass 10, count 0 2006.246.07:45:47.90#ibcon#flushed, iclass 10, count 0 2006.246.07:45:47.90#ibcon#about to write, iclass 10, count 0 2006.246.07:45:47.90#ibcon#wrote, iclass 10, count 0 2006.246.07:45:47.90#ibcon#about to read 3, iclass 10, count 0 2006.246.07:45:47.91#ibcon#read 3, iclass 10, count 0 2006.246.07:45:47.91#ibcon#about to read 4, iclass 10, count 0 2006.246.07:45:47.91#ibcon#read 4, iclass 10, count 0 2006.246.07:45:47.91#ibcon#about to read 5, iclass 10, count 0 2006.246.07:45:47.91#ibcon#read 5, iclass 10, count 0 2006.246.07:45:47.91#ibcon#about to read 6, iclass 10, count 0 2006.246.07:45:47.91#ibcon#read 6, iclass 10, count 0 2006.246.07:45:47.91#ibcon#end of sib2, iclass 10, count 0 2006.246.07:45:47.91#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:45:47.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:45:47.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:45:47.91#ibcon#*before write, iclass 10, count 0 2006.246.07:45:47.91#ibcon#enter sib2, iclass 10, count 0 2006.246.07:45:47.91#ibcon#flushed, iclass 10, count 0 2006.246.07:45:47.91#ibcon#about to write, iclass 10, count 0 2006.246.07:45:47.91#ibcon#wrote, iclass 10, count 0 2006.246.07:45:47.91#ibcon#about to read 3, iclass 10, count 0 2006.246.07:45:47.96#ibcon#read 3, iclass 10, count 0 2006.246.07:45:47.96#ibcon#about to read 4, iclass 10, count 0 2006.246.07:45:47.96#ibcon#read 4, iclass 10, count 0 2006.246.07:45:47.96#ibcon#about to read 5, iclass 10, count 0 2006.246.07:45:47.96#ibcon#read 5, iclass 10, count 0 2006.246.07:45:47.96#ibcon#about to read 6, iclass 10, count 0 2006.246.07:45:47.96#ibcon#read 6, iclass 10, count 0 2006.246.07:45:47.96#ibcon#end of sib2, iclass 10, count 0 2006.246.07:45:47.96#ibcon#*after write, iclass 10, count 0 2006.246.07:45:47.96#ibcon#*before return 0, iclass 10, count 0 2006.246.07:45:47.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:47.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:47.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:45:47.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:45:47.96$vc4f8/va=1,8 2006.246.07:45:47.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.07:45:47.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.07:45:47.96#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:47.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:47.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:47.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:47.96#ibcon#enter wrdev, iclass 12, count 2 2006.246.07:45:47.96#ibcon#first serial, iclass 12, count 2 2006.246.07:45:47.96#ibcon#enter sib2, iclass 12, count 2 2006.246.07:45:47.96#ibcon#flushed, iclass 12, count 2 2006.246.07:45:47.96#ibcon#about to write, iclass 12, count 2 2006.246.07:45:47.96#ibcon#wrote, iclass 12, count 2 2006.246.07:45:47.96#ibcon#about to read 3, iclass 12, count 2 2006.246.07:45:47.98#ibcon#read 3, iclass 12, count 2 2006.246.07:45:47.98#ibcon#about to read 4, iclass 12, count 2 2006.246.07:45:47.98#ibcon#read 4, iclass 12, count 2 2006.246.07:45:47.98#ibcon#about to read 5, iclass 12, count 2 2006.246.07:45:47.98#ibcon#read 5, iclass 12, count 2 2006.246.07:45:47.98#ibcon#about to read 6, iclass 12, count 2 2006.246.07:45:47.98#ibcon#read 6, iclass 12, count 2 2006.246.07:45:47.98#ibcon#end of sib2, iclass 12, count 2 2006.246.07:45:47.98#ibcon#*mode == 0, iclass 12, count 2 2006.246.07:45:47.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.07:45:47.98#ibcon#[25=AT01-08\r\n] 2006.246.07:45:47.98#ibcon#*before write, iclass 12, count 2 2006.246.07:45:47.98#ibcon#enter sib2, iclass 12, count 2 2006.246.07:45:47.98#ibcon#flushed, iclass 12, count 2 2006.246.07:45:47.98#ibcon#about to write, iclass 12, count 2 2006.246.07:45:47.98#ibcon#wrote, iclass 12, count 2 2006.246.07:45:47.98#ibcon#about to read 3, iclass 12, count 2 2006.246.07:45:48.02#ibcon#read 3, iclass 12, count 2 2006.246.07:45:48.02#ibcon#about to read 4, iclass 12, count 2 2006.246.07:45:48.02#ibcon#read 4, iclass 12, count 2 2006.246.07:45:48.02#ibcon#about to read 5, iclass 12, count 2 2006.246.07:45:48.02#ibcon#read 5, iclass 12, count 2 2006.246.07:45:48.02#ibcon#about to read 6, iclass 12, count 2 2006.246.07:45:48.02#ibcon#read 6, iclass 12, count 2 2006.246.07:45:48.02#ibcon#end of sib2, iclass 12, count 2 2006.246.07:45:48.02#ibcon#*after write, iclass 12, count 2 2006.246.07:45:48.02#ibcon#*before return 0, iclass 12, count 2 2006.246.07:45:48.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:48.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:48.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.07:45:48.02#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:48.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:48.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:48.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:48.13#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:45:48.13#ibcon#first serial, iclass 12, count 0 2006.246.07:45:48.13#ibcon#enter sib2, iclass 12, count 0 2006.246.07:45:48.13#ibcon#flushed, iclass 12, count 0 2006.246.07:45:48.13#ibcon#about to write, iclass 12, count 0 2006.246.07:45:48.13#ibcon#wrote, iclass 12, count 0 2006.246.07:45:48.14#ibcon#about to read 3, iclass 12, count 0 2006.246.07:45:48.15#ibcon#read 3, iclass 12, count 0 2006.246.07:45:48.15#ibcon#about to read 4, iclass 12, count 0 2006.246.07:45:48.15#ibcon#read 4, iclass 12, count 0 2006.246.07:45:48.15#ibcon#about to read 5, iclass 12, count 0 2006.246.07:45:48.15#ibcon#read 5, iclass 12, count 0 2006.246.07:45:48.15#ibcon#about to read 6, iclass 12, count 0 2006.246.07:45:48.15#ibcon#read 6, iclass 12, count 0 2006.246.07:45:48.15#ibcon#end of sib2, iclass 12, count 0 2006.246.07:45:48.15#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:45:48.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:45:48.15#ibcon#[25=USB\r\n] 2006.246.07:45:48.15#ibcon#*before write, iclass 12, count 0 2006.246.07:45:48.15#ibcon#enter sib2, iclass 12, count 0 2006.246.07:45:48.15#ibcon#flushed, iclass 12, count 0 2006.246.07:45:48.15#ibcon#about to write, iclass 12, count 0 2006.246.07:45:48.15#ibcon#wrote, iclass 12, count 0 2006.246.07:45:48.15#ibcon#about to read 3, iclass 12, count 0 2006.246.07:45:48.18#ibcon#read 3, iclass 12, count 0 2006.246.07:45:48.18#ibcon#about to read 4, iclass 12, count 0 2006.246.07:45:48.18#ibcon#read 4, iclass 12, count 0 2006.246.07:45:48.18#ibcon#about to read 5, iclass 12, count 0 2006.246.07:45:48.18#ibcon#read 5, iclass 12, count 0 2006.246.07:45:48.18#ibcon#about to read 6, iclass 12, count 0 2006.246.07:45:48.18#ibcon#read 6, iclass 12, count 0 2006.246.07:45:48.18#ibcon#end of sib2, iclass 12, count 0 2006.246.07:45:48.18#ibcon#*after write, iclass 12, count 0 2006.246.07:45:48.18#ibcon#*before return 0, iclass 12, count 0 2006.246.07:45:48.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:48.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:48.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:45:48.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:45:48.18$vc4f8/valo=2,572.99 2006.246.07:45:48.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.07:45:48.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.07:45:48.18#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:48.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:48.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:48.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:48.18#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:45:48.18#ibcon#first serial, iclass 14, count 0 2006.246.07:45:48.18#ibcon#enter sib2, iclass 14, count 0 2006.246.07:45:48.18#ibcon#flushed, iclass 14, count 0 2006.246.07:45:48.18#ibcon#about to write, iclass 14, count 0 2006.246.07:45:48.18#ibcon#wrote, iclass 14, count 0 2006.246.07:45:48.18#ibcon#about to read 3, iclass 14, count 0 2006.246.07:45:48.21#ibcon#read 3, iclass 14, count 0 2006.246.07:45:48.21#ibcon#about to read 4, iclass 14, count 0 2006.246.07:45:48.21#ibcon#read 4, iclass 14, count 0 2006.246.07:45:48.21#ibcon#about to read 5, iclass 14, count 0 2006.246.07:45:48.21#ibcon#read 5, iclass 14, count 0 2006.246.07:45:48.21#ibcon#about to read 6, iclass 14, count 0 2006.246.07:45:48.21#ibcon#read 6, iclass 14, count 0 2006.246.07:45:48.21#ibcon#end of sib2, iclass 14, count 0 2006.246.07:45:48.21#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:45:48.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:45:48.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:45:48.21#ibcon#*before write, iclass 14, count 0 2006.246.07:45:48.21#ibcon#enter sib2, iclass 14, count 0 2006.246.07:45:48.21#ibcon#flushed, iclass 14, count 0 2006.246.07:45:48.21#ibcon#about to write, iclass 14, count 0 2006.246.07:45:48.21#ibcon#wrote, iclass 14, count 0 2006.246.07:45:48.21#ibcon#about to read 3, iclass 14, count 0 2006.246.07:45:48.25#ibcon#read 3, iclass 14, count 0 2006.246.07:45:48.25#ibcon#about to read 4, iclass 14, count 0 2006.246.07:45:48.25#ibcon#read 4, iclass 14, count 0 2006.246.07:45:48.25#ibcon#about to read 5, iclass 14, count 0 2006.246.07:45:48.25#ibcon#read 5, iclass 14, count 0 2006.246.07:45:48.25#ibcon#about to read 6, iclass 14, count 0 2006.246.07:45:48.25#ibcon#read 6, iclass 14, count 0 2006.246.07:45:48.25#ibcon#end of sib2, iclass 14, count 0 2006.246.07:45:48.25#ibcon#*after write, iclass 14, count 0 2006.246.07:45:48.25#ibcon#*before return 0, iclass 14, count 0 2006.246.07:45:48.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:48.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:48.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:45:48.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:45:48.25$vc4f8/va=2,7 2006.246.07:45:48.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.07:45:48.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.07:45:48.25#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:48.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:48.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:48.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:48.30#ibcon#enter wrdev, iclass 16, count 2 2006.246.07:45:48.30#ibcon#first serial, iclass 16, count 2 2006.246.07:45:48.30#ibcon#enter sib2, iclass 16, count 2 2006.246.07:45:48.30#ibcon#flushed, iclass 16, count 2 2006.246.07:45:48.30#ibcon#about to write, iclass 16, count 2 2006.246.07:45:48.30#ibcon#wrote, iclass 16, count 2 2006.246.07:45:48.30#ibcon#about to read 3, iclass 16, count 2 2006.246.07:45:48.32#ibcon#read 3, iclass 16, count 2 2006.246.07:45:48.32#ibcon#about to read 4, iclass 16, count 2 2006.246.07:45:48.32#ibcon#read 4, iclass 16, count 2 2006.246.07:45:48.32#ibcon#about to read 5, iclass 16, count 2 2006.246.07:45:48.32#ibcon#read 5, iclass 16, count 2 2006.246.07:45:48.32#ibcon#about to read 6, iclass 16, count 2 2006.246.07:45:48.32#ibcon#read 6, iclass 16, count 2 2006.246.07:45:48.32#ibcon#end of sib2, iclass 16, count 2 2006.246.07:45:48.32#ibcon#*mode == 0, iclass 16, count 2 2006.246.07:45:48.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.07:45:48.32#ibcon#[25=AT02-07\r\n] 2006.246.07:45:48.32#ibcon#*before write, iclass 16, count 2 2006.246.07:45:48.32#ibcon#enter sib2, iclass 16, count 2 2006.246.07:45:48.32#ibcon#flushed, iclass 16, count 2 2006.246.07:45:48.32#ibcon#about to write, iclass 16, count 2 2006.246.07:45:48.32#ibcon#wrote, iclass 16, count 2 2006.246.07:45:48.32#ibcon#about to read 3, iclass 16, count 2 2006.246.07:45:48.35#ibcon#read 3, iclass 16, count 2 2006.246.07:45:48.35#ibcon#about to read 4, iclass 16, count 2 2006.246.07:45:48.35#ibcon#read 4, iclass 16, count 2 2006.246.07:45:48.35#ibcon#about to read 5, iclass 16, count 2 2006.246.07:45:48.35#ibcon#read 5, iclass 16, count 2 2006.246.07:45:48.35#ibcon#about to read 6, iclass 16, count 2 2006.246.07:45:48.35#ibcon#read 6, iclass 16, count 2 2006.246.07:45:48.35#ibcon#end of sib2, iclass 16, count 2 2006.246.07:45:48.35#ibcon#*after write, iclass 16, count 2 2006.246.07:45:48.35#ibcon#*before return 0, iclass 16, count 2 2006.246.07:45:48.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:48.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:48.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.07:45:48.35#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:48.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:48.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:48.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:48.47#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:45:48.47#ibcon#first serial, iclass 16, count 0 2006.246.07:45:48.47#ibcon#enter sib2, iclass 16, count 0 2006.246.07:45:48.47#ibcon#flushed, iclass 16, count 0 2006.246.07:45:48.47#ibcon#about to write, iclass 16, count 0 2006.246.07:45:48.47#ibcon#wrote, iclass 16, count 0 2006.246.07:45:48.47#ibcon#about to read 3, iclass 16, count 0 2006.246.07:45:48.49#ibcon#read 3, iclass 16, count 0 2006.246.07:45:48.49#ibcon#about to read 4, iclass 16, count 0 2006.246.07:45:48.49#ibcon#read 4, iclass 16, count 0 2006.246.07:45:48.49#ibcon#about to read 5, iclass 16, count 0 2006.246.07:45:48.49#ibcon#read 5, iclass 16, count 0 2006.246.07:45:48.49#ibcon#about to read 6, iclass 16, count 0 2006.246.07:45:48.49#ibcon#read 6, iclass 16, count 0 2006.246.07:45:48.49#ibcon#end of sib2, iclass 16, count 0 2006.246.07:45:48.49#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:45:48.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:45:48.49#ibcon#[25=USB\r\n] 2006.246.07:45:48.49#ibcon#*before write, iclass 16, count 0 2006.246.07:45:48.49#ibcon#enter sib2, iclass 16, count 0 2006.246.07:45:48.49#ibcon#flushed, iclass 16, count 0 2006.246.07:45:48.49#ibcon#about to write, iclass 16, count 0 2006.246.07:45:48.49#ibcon#wrote, iclass 16, count 0 2006.246.07:45:48.49#ibcon#about to read 3, iclass 16, count 0 2006.246.07:45:48.52#ibcon#read 3, iclass 16, count 0 2006.246.07:45:48.52#ibcon#about to read 4, iclass 16, count 0 2006.246.07:45:48.52#ibcon#read 4, iclass 16, count 0 2006.246.07:45:48.52#ibcon#about to read 5, iclass 16, count 0 2006.246.07:45:48.52#ibcon#read 5, iclass 16, count 0 2006.246.07:45:48.52#ibcon#about to read 6, iclass 16, count 0 2006.246.07:45:48.52#ibcon#read 6, iclass 16, count 0 2006.246.07:45:48.52#ibcon#end of sib2, iclass 16, count 0 2006.246.07:45:48.52#ibcon#*after write, iclass 16, count 0 2006.246.07:45:48.52#ibcon#*before return 0, iclass 16, count 0 2006.246.07:45:48.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:48.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:48.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:45:48.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:45:48.52$vc4f8/valo=3,672.99 2006.246.07:45:48.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:45:48.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:45:48.52#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:48.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:48.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:48.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:48.52#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:45:48.52#ibcon#first serial, iclass 18, count 0 2006.246.07:45:48.52#ibcon#enter sib2, iclass 18, count 0 2006.246.07:45:48.52#ibcon#flushed, iclass 18, count 0 2006.246.07:45:48.52#ibcon#about to write, iclass 18, count 0 2006.246.07:45:48.52#ibcon#wrote, iclass 18, count 0 2006.246.07:45:48.52#ibcon#about to read 3, iclass 18, count 0 2006.246.07:45:48.55#ibcon#read 3, iclass 18, count 0 2006.246.07:45:48.55#ibcon#about to read 4, iclass 18, count 0 2006.246.07:45:48.55#ibcon#read 4, iclass 18, count 0 2006.246.07:45:48.55#ibcon#about to read 5, iclass 18, count 0 2006.246.07:45:48.55#ibcon#read 5, iclass 18, count 0 2006.246.07:45:48.55#ibcon#about to read 6, iclass 18, count 0 2006.246.07:45:48.55#ibcon#read 6, iclass 18, count 0 2006.246.07:45:48.55#ibcon#end of sib2, iclass 18, count 0 2006.246.07:45:48.55#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:45:48.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:45:48.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:45:48.55#ibcon#*before write, iclass 18, count 0 2006.246.07:45:48.55#ibcon#enter sib2, iclass 18, count 0 2006.246.07:45:48.55#ibcon#flushed, iclass 18, count 0 2006.246.07:45:48.55#ibcon#about to write, iclass 18, count 0 2006.246.07:45:48.55#ibcon#wrote, iclass 18, count 0 2006.246.07:45:48.55#ibcon#about to read 3, iclass 18, count 0 2006.246.07:45:48.59#ibcon#read 3, iclass 18, count 0 2006.246.07:45:48.59#ibcon#about to read 4, iclass 18, count 0 2006.246.07:45:48.59#ibcon#read 4, iclass 18, count 0 2006.246.07:45:48.59#ibcon#about to read 5, iclass 18, count 0 2006.246.07:45:48.59#ibcon#read 5, iclass 18, count 0 2006.246.07:45:48.59#ibcon#about to read 6, iclass 18, count 0 2006.246.07:45:48.59#ibcon#read 6, iclass 18, count 0 2006.246.07:45:48.59#ibcon#end of sib2, iclass 18, count 0 2006.246.07:45:48.59#ibcon#*after write, iclass 18, count 0 2006.246.07:45:48.59#ibcon#*before return 0, iclass 18, count 0 2006.246.07:45:48.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:48.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:48.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:45:48.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:45:48.59$vc4f8/va=3,6 2006.246.07:45:48.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.07:45:48.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.07:45:48.59#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:48.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:48.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:48.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:48.64#ibcon#enter wrdev, iclass 20, count 2 2006.246.07:45:48.64#ibcon#first serial, iclass 20, count 2 2006.246.07:45:48.64#ibcon#enter sib2, iclass 20, count 2 2006.246.07:45:48.64#ibcon#flushed, iclass 20, count 2 2006.246.07:45:48.64#ibcon#about to write, iclass 20, count 2 2006.246.07:45:48.64#ibcon#wrote, iclass 20, count 2 2006.246.07:45:48.64#ibcon#about to read 3, iclass 20, count 2 2006.246.07:45:48.66#ibcon#read 3, iclass 20, count 2 2006.246.07:45:48.66#ibcon#about to read 4, iclass 20, count 2 2006.246.07:45:48.66#ibcon#read 4, iclass 20, count 2 2006.246.07:45:48.66#ibcon#about to read 5, iclass 20, count 2 2006.246.07:45:48.66#ibcon#read 5, iclass 20, count 2 2006.246.07:45:48.66#ibcon#about to read 6, iclass 20, count 2 2006.246.07:45:48.66#ibcon#read 6, iclass 20, count 2 2006.246.07:45:48.66#ibcon#end of sib2, iclass 20, count 2 2006.246.07:45:48.66#ibcon#*mode == 0, iclass 20, count 2 2006.246.07:45:48.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.07:45:48.66#ibcon#[25=AT03-06\r\n] 2006.246.07:45:48.66#ibcon#*before write, iclass 20, count 2 2006.246.07:45:48.66#ibcon#enter sib2, iclass 20, count 2 2006.246.07:45:48.66#ibcon#flushed, iclass 20, count 2 2006.246.07:45:48.66#ibcon#about to write, iclass 20, count 2 2006.246.07:45:48.66#ibcon#wrote, iclass 20, count 2 2006.246.07:45:48.66#ibcon#about to read 3, iclass 20, count 2 2006.246.07:45:48.69#ibcon#read 3, iclass 20, count 2 2006.246.07:45:48.69#ibcon#about to read 4, iclass 20, count 2 2006.246.07:45:48.69#ibcon#read 4, iclass 20, count 2 2006.246.07:45:48.69#ibcon#about to read 5, iclass 20, count 2 2006.246.07:45:48.69#ibcon#read 5, iclass 20, count 2 2006.246.07:45:48.69#ibcon#about to read 6, iclass 20, count 2 2006.246.07:45:48.69#ibcon#read 6, iclass 20, count 2 2006.246.07:45:48.69#ibcon#end of sib2, iclass 20, count 2 2006.246.07:45:48.69#ibcon#*after write, iclass 20, count 2 2006.246.07:45:48.69#ibcon#*before return 0, iclass 20, count 2 2006.246.07:45:48.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:48.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:48.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.07:45:48.69#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:48.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:48.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:48.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:48.81#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:45:48.81#ibcon#first serial, iclass 20, count 0 2006.246.07:45:48.81#ibcon#enter sib2, iclass 20, count 0 2006.246.07:45:48.81#ibcon#flushed, iclass 20, count 0 2006.246.07:45:48.81#ibcon#about to write, iclass 20, count 0 2006.246.07:45:48.81#ibcon#wrote, iclass 20, count 0 2006.246.07:45:48.81#ibcon#about to read 3, iclass 20, count 0 2006.246.07:45:48.83#ibcon#read 3, iclass 20, count 0 2006.246.07:45:48.83#ibcon#about to read 4, iclass 20, count 0 2006.246.07:45:48.83#ibcon#read 4, iclass 20, count 0 2006.246.07:45:48.83#ibcon#about to read 5, iclass 20, count 0 2006.246.07:45:48.83#ibcon#read 5, iclass 20, count 0 2006.246.07:45:48.83#ibcon#about to read 6, iclass 20, count 0 2006.246.07:45:48.83#ibcon#read 6, iclass 20, count 0 2006.246.07:45:48.83#ibcon#end of sib2, iclass 20, count 0 2006.246.07:45:48.83#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:45:48.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:45:48.83#ibcon#[25=USB\r\n] 2006.246.07:45:48.83#ibcon#*before write, iclass 20, count 0 2006.246.07:45:48.83#ibcon#enter sib2, iclass 20, count 0 2006.246.07:45:48.83#ibcon#flushed, iclass 20, count 0 2006.246.07:45:48.83#ibcon#about to write, iclass 20, count 0 2006.246.07:45:48.83#ibcon#wrote, iclass 20, count 0 2006.246.07:45:48.83#ibcon#about to read 3, iclass 20, count 0 2006.246.07:45:48.86#ibcon#read 3, iclass 20, count 0 2006.246.07:45:48.86#ibcon#about to read 4, iclass 20, count 0 2006.246.07:45:48.86#ibcon#read 4, iclass 20, count 0 2006.246.07:45:48.86#ibcon#about to read 5, iclass 20, count 0 2006.246.07:45:48.86#ibcon#read 5, iclass 20, count 0 2006.246.07:45:48.86#ibcon#about to read 6, iclass 20, count 0 2006.246.07:45:48.86#ibcon#read 6, iclass 20, count 0 2006.246.07:45:48.86#ibcon#end of sib2, iclass 20, count 0 2006.246.07:45:48.86#ibcon#*after write, iclass 20, count 0 2006.246.07:45:48.86#ibcon#*before return 0, iclass 20, count 0 2006.246.07:45:48.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:48.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:48.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:45:48.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:45:48.86$vc4f8/valo=4,832.99 2006.246.07:45:48.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:45:48.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:45:48.86#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:48.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:45:48.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:45:48.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:45:48.86#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:45:48.86#ibcon#first serial, iclass 22, count 0 2006.246.07:45:48.86#ibcon#enter sib2, iclass 22, count 0 2006.246.07:45:48.86#ibcon#flushed, iclass 22, count 0 2006.246.07:45:48.86#ibcon#about to write, iclass 22, count 0 2006.246.07:45:48.86#ibcon#wrote, iclass 22, count 0 2006.246.07:45:48.86#ibcon#about to read 3, iclass 22, count 0 2006.246.07:45:48.88#ibcon#read 3, iclass 22, count 0 2006.246.07:45:48.88#ibcon#about to read 4, iclass 22, count 0 2006.246.07:45:48.88#ibcon#read 4, iclass 22, count 0 2006.246.07:45:48.88#ibcon#about to read 5, iclass 22, count 0 2006.246.07:45:48.88#ibcon#read 5, iclass 22, count 0 2006.246.07:45:48.88#ibcon#about to read 6, iclass 22, count 0 2006.246.07:45:48.88#ibcon#read 6, iclass 22, count 0 2006.246.07:45:48.88#ibcon#end of sib2, iclass 22, count 0 2006.246.07:45:48.88#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:45:48.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:45:48.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:45:48.88#ibcon#*before write, iclass 22, count 0 2006.246.07:45:48.88#ibcon#enter sib2, iclass 22, count 0 2006.246.07:45:48.88#ibcon#flushed, iclass 22, count 0 2006.246.07:45:48.88#ibcon#about to write, iclass 22, count 0 2006.246.07:45:48.88#ibcon#wrote, iclass 22, count 0 2006.246.07:45:48.88#ibcon#about to read 3, iclass 22, count 0 2006.246.07:45:48.92#ibcon#read 3, iclass 22, count 0 2006.246.07:45:48.92#ibcon#about to read 4, iclass 22, count 0 2006.246.07:45:48.92#ibcon#read 4, iclass 22, count 0 2006.246.07:45:48.92#ibcon#about to read 5, iclass 22, count 0 2006.246.07:45:48.92#ibcon#read 5, iclass 22, count 0 2006.246.07:45:48.92#ibcon#about to read 6, iclass 22, count 0 2006.246.07:45:48.92#ibcon#read 6, iclass 22, count 0 2006.246.07:45:48.92#ibcon#end of sib2, iclass 22, count 0 2006.246.07:45:48.92#ibcon#*after write, iclass 22, count 0 2006.246.07:45:48.92#ibcon#*before return 0, iclass 22, count 0 2006.246.07:45:48.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:45:48.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:45:48.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:45:48.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:45:48.92$vc4f8/va=4,7 2006.246.07:45:48.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.07:45:48.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.07:45:48.92#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:48.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:45:48.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:45:48.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:45:48.98#ibcon#enter wrdev, iclass 24, count 2 2006.246.07:45:48.98#ibcon#first serial, iclass 24, count 2 2006.246.07:45:48.98#ibcon#enter sib2, iclass 24, count 2 2006.246.07:45:48.98#ibcon#flushed, iclass 24, count 2 2006.246.07:45:48.98#ibcon#about to write, iclass 24, count 2 2006.246.07:45:48.98#ibcon#wrote, iclass 24, count 2 2006.246.07:45:48.98#ibcon#about to read 3, iclass 24, count 2 2006.246.07:45:49.00#ibcon#read 3, iclass 24, count 2 2006.246.07:45:49.00#ibcon#about to read 4, iclass 24, count 2 2006.246.07:45:49.00#ibcon#read 4, iclass 24, count 2 2006.246.07:45:49.00#ibcon#about to read 5, iclass 24, count 2 2006.246.07:45:49.00#ibcon#read 5, iclass 24, count 2 2006.246.07:45:49.00#ibcon#about to read 6, iclass 24, count 2 2006.246.07:45:49.00#ibcon#read 6, iclass 24, count 2 2006.246.07:45:49.00#ibcon#end of sib2, iclass 24, count 2 2006.246.07:45:49.00#ibcon#*mode == 0, iclass 24, count 2 2006.246.07:45:49.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.07:45:49.00#ibcon#[25=AT04-07\r\n] 2006.246.07:45:49.00#ibcon#*before write, iclass 24, count 2 2006.246.07:45:49.00#ibcon#enter sib2, iclass 24, count 2 2006.246.07:45:49.00#ibcon#flushed, iclass 24, count 2 2006.246.07:45:49.00#ibcon#about to write, iclass 24, count 2 2006.246.07:45:49.00#ibcon#wrote, iclass 24, count 2 2006.246.07:45:49.00#ibcon#about to read 3, iclass 24, count 2 2006.246.07:45:49.03#ibcon#read 3, iclass 24, count 2 2006.246.07:45:49.03#ibcon#about to read 4, iclass 24, count 2 2006.246.07:45:49.03#ibcon#read 4, iclass 24, count 2 2006.246.07:45:49.03#ibcon#about to read 5, iclass 24, count 2 2006.246.07:45:49.03#ibcon#read 5, iclass 24, count 2 2006.246.07:45:49.03#ibcon#about to read 6, iclass 24, count 2 2006.246.07:45:49.03#ibcon#read 6, iclass 24, count 2 2006.246.07:45:49.03#ibcon#end of sib2, iclass 24, count 2 2006.246.07:45:49.03#ibcon#*after write, iclass 24, count 2 2006.246.07:45:49.03#ibcon#*before return 0, iclass 24, count 2 2006.246.07:45:49.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:45:49.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:45:49.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.07:45:49.03#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:49.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:45:49.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:45:49.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:45:49.15#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:45:49.15#ibcon#first serial, iclass 24, count 0 2006.246.07:45:49.15#ibcon#enter sib2, iclass 24, count 0 2006.246.07:45:49.15#ibcon#flushed, iclass 24, count 0 2006.246.07:45:49.15#ibcon#about to write, iclass 24, count 0 2006.246.07:45:49.15#ibcon#wrote, iclass 24, count 0 2006.246.07:45:49.15#ibcon#about to read 3, iclass 24, count 0 2006.246.07:45:49.17#ibcon#read 3, iclass 24, count 0 2006.246.07:45:49.17#ibcon#about to read 4, iclass 24, count 0 2006.246.07:45:49.17#ibcon#read 4, iclass 24, count 0 2006.246.07:45:49.17#ibcon#about to read 5, iclass 24, count 0 2006.246.07:45:49.17#ibcon#read 5, iclass 24, count 0 2006.246.07:45:49.17#ibcon#about to read 6, iclass 24, count 0 2006.246.07:45:49.17#ibcon#read 6, iclass 24, count 0 2006.246.07:45:49.17#ibcon#end of sib2, iclass 24, count 0 2006.246.07:45:49.17#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:45:49.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:45:49.17#ibcon#[25=USB\r\n] 2006.246.07:45:49.17#ibcon#*before write, iclass 24, count 0 2006.246.07:45:49.17#ibcon#enter sib2, iclass 24, count 0 2006.246.07:45:49.17#ibcon#flushed, iclass 24, count 0 2006.246.07:45:49.17#ibcon#about to write, iclass 24, count 0 2006.246.07:45:49.17#ibcon#wrote, iclass 24, count 0 2006.246.07:45:49.17#ibcon#about to read 3, iclass 24, count 0 2006.246.07:45:49.20#ibcon#read 3, iclass 24, count 0 2006.246.07:45:49.20#ibcon#about to read 4, iclass 24, count 0 2006.246.07:45:49.20#ibcon#read 4, iclass 24, count 0 2006.246.07:45:49.20#ibcon#about to read 5, iclass 24, count 0 2006.246.07:45:49.20#ibcon#read 5, iclass 24, count 0 2006.246.07:45:49.20#ibcon#about to read 6, iclass 24, count 0 2006.246.07:45:49.20#ibcon#read 6, iclass 24, count 0 2006.246.07:45:49.20#ibcon#end of sib2, iclass 24, count 0 2006.246.07:45:49.20#ibcon#*after write, iclass 24, count 0 2006.246.07:45:49.20#ibcon#*before return 0, iclass 24, count 0 2006.246.07:45:49.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:45:49.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:45:49.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:45:49.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:45:49.20$vc4f8/valo=5,652.99 2006.246.07:45:49.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:45:49.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:45:49.20#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:49.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:45:49.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:45:49.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:45:49.20#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:45:49.20#ibcon#first serial, iclass 26, count 0 2006.246.07:45:49.20#ibcon#enter sib2, iclass 26, count 0 2006.246.07:45:49.20#ibcon#flushed, iclass 26, count 0 2006.246.07:45:49.20#ibcon#about to write, iclass 26, count 0 2006.246.07:45:49.20#ibcon#wrote, iclass 26, count 0 2006.246.07:45:49.20#ibcon#about to read 3, iclass 26, count 0 2006.246.07:45:49.22#ibcon#read 3, iclass 26, count 0 2006.246.07:45:49.22#ibcon#about to read 4, iclass 26, count 0 2006.246.07:45:49.22#ibcon#read 4, iclass 26, count 0 2006.246.07:45:49.22#ibcon#about to read 5, iclass 26, count 0 2006.246.07:45:49.22#ibcon#read 5, iclass 26, count 0 2006.246.07:45:49.22#ibcon#about to read 6, iclass 26, count 0 2006.246.07:45:49.22#ibcon#read 6, iclass 26, count 0 2006.246.07:45:49.22#ibcon#end of sib2, iclass 26, count 0 2006.246.07:45:49.22#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:45:49.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:45:49.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:45:49.22#ibcon#*before write, iclass 26, count 0 2006.246.07:45:49.22#ibcon#enter sib2, iclass 26, count 0 2006.246.07:45:49.22#ibcon#flushed, iclass 26, count 0 2006.246.07:45:49.22#ibcon#about to write, iclass 26, count 0 2006.246.07:45:49.22#ibcon#wrote, iclass 26, count 0 2006.246.07:45:49.22#ibcon#about to read 3, iclass 26, count 0 2006.246.07:45:49.26#ibcon#read 3, iclass 26, count 0 2006.246.07:45:49.26#ibcon#about to read 4, iclass 26, count 0 2006.246.07:45:49.26#ibcon#read 4, iclass 26, count 0 2006.246.07:45:49.26#ibcon#about to read 5, iclass 26, count 0 2006.246.07:45:49.26#ibcon#read 5, iclass 26, count 0 2006.246.07:45:49.26#ibcon#about to read 6, iclass 26, count 0 2006.246.07:45:49.26#ibcon#read 6, iclass 26, count 0 2006.246.07:45:49.26#ibcon#end of sib2, iclass 26, count 0 2006.246.07:45:49.26#ibcon#*after write, iclass 26, count 0 2006.246.07:45:49.26#ibcon#*before return 0, iclass 26, count 0 2006.246.07:45:49.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:45:49.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:45:49.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:45:49.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:45:49.26$vc4f8/va=5,7 2006.246.07:45:49.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:45:49.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:45:49.26#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:49.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:49.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:49.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:49.32#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:45:49.32#ibcon#first serial, iclass 28, count 2 2006.246.07:45:49.32#ibcon#enter sib2, iclass 28, count 2 2006.246.07:45:49.32#ibcon#flushed, iclass 28, count 2 2006.246.07:45:49.32#ibcon#about to write, iclass 28, count 2 2006.246.07:45:49.32#ibcon#wrote, iclass 28, count 2 2006.246.07:45:49.32#ibcon#about to read 3, iclass 28, count 2 2006.246.07:45:49.34#ibcon#read 3, iclass 28, count 2 2006.246.07:45:49.34#ibcon#about to read 4, iclass 28, count 2 2006.246.07:45:49.34#ibcon#read 4, iclass 28, count 2 2006.246.07:45:49.34#ibcon#about to read 5, iclass 28, count 2 2006.246.07:45:49.34#ibcon#read 5, iclass 28, count 2 2006.246.07:45:49.34#ibcon#about to read 6, iclass 28, count 2 2006.246.07:45:49.34#ibcon#read 6, iclass 28, count 2 2006.246.07:45:49.34#ibcon#end of sib2, iclass 28, count 2 2006.246.07:45:49.34#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:45:49.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:45:49.34#ibcon#[25=AT05-07\r\n] 2006.246.07:45:49.34#ibcon#*before write, iclass 28, count 2 2006.246.07:45:49.34#ibcon#enter sib2, iclass 28, count 2 2006.246.07:45:49.34#ibcon#flushed, iclass 28, count 2 2006.246.07:45:49.34#ibcon#about to write, iclass 28, count 2 2006.246.07:45:49.34#ibcon#wrote, iclass 28, count 2 2006.246.07:45:49.34#ibcon#about to read 3, iclass 28, count 2 2006.246.07:45:49.37#ibcon#read 3, iclass 28, count 2 2006.246.07:45:49.37#ibcon#about to read 4, iclass 28, count 2 2006.246.07:45:49.37#ibcon#read 4, iclass 28, count 2 2006.246.07:45:49.37#ibcon#about to read 5, iclass 28, count 2 2006.246.07:45:49.37#ibcon#read 5, iclass 28, count 2 2006.246.07:45:49.37#ibcon#about to read 6, iclass 28, count 2 2006.246.07:45:49.37#ibcon#read 6, iclass 28, count 2 2006.246.07:45:49.37#ibcon#end of sib2, iclass 28, count 2 2006.246.07:45:49.37#ibcon#*after write, iclass 28, count 2 2006.246.07:45:49.37#ibcon#*before return 0, iclass 28, count 2 2006.246.07:45:49.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:49.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:49.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:45:49.37#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:49.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:49.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:49.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:49.50#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:45:49.50#ibcon#first serial, iclass 28, count 0 2006.246.07:45:49.50#ibcon#enter sib2, iclass 28, count 0 2006.246.07:45:49.50#ibcon#flushed, iclass 28, count 0 2006.246.07:45:49.50#ibcon#about to write, iclass 28, count 0 2006.246.07:45:49.50#ibcon#wrote, iclass 28, count 0 2006.246.07:45:49.50#ibcon#about to read 3, iclass 28, count 0 2006.246.07:45:49.51#ibcon#read 3, iclass 28, count 0 2006.246.07:45:49.51#ibcon#about to read 4, iclass 28, count 0 2006.246.07:45:49.51#ibcon#read 4, iclass 28, count 0 2006.246.07:45:49.51#ibcon#about to read 5, iclass 28, count 0 2006.246.07:45:49.51#ibcon#read 5, iclass 28, count 0 2006.246.07:45:49.51#ibcon#about to read 6, iclass 28, count 0 2006.246.07:45:49.51#ibcon#read 6, iclass 28, count 0 2006.246.07:45:49.51#ibcon#end of sib2, iclass 28, count 0 2006.246.07:45:49.51#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:45:49.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:45:49.51#ibcon#[25=USB\r\n] 2006.246.07:45:49.51#ibcon#*before write, iclass 28, count 0 2006.246.07:45:49.51#ibcon#enter sib2, iclass 28, count 0 2006.246.07:45:49.51#ibcon#flushed, iclass 28, count 0 2006.246.07:45:49.51#ibcon#about to write, iclass 28, count 0 2006.246.07:45:49.51#ibcon#wrote, iclass 28, count 0 2006.246.07:45:49.51#ibcon#about to read 3, iclass 28, count 0 2006.246.07:45:49.54#ibcon#read 3, iclass 28, count 0 2006.246.07:45:49.54#ibcon#about to read 4, iclass 28, count 0 2006.246.07:45:49.54#ibcon#read 4, iclass 28, count 0 2006.246.07:45:49.54#ibcon#about to read 5, iclass 28, count 0 2006.246.07:45:49.54#ibcon#read 5, iclass 28, count 0 2006.246.07:45:49.54#ibcon#about to read 6, iclass 28, count 0 2006.246.07:45:49.54#ibcon#read 6, iclass 28, count 0 2006.246.07:45:49.54#ibcon#end of sib2, iclass 28, count 0 2006.246.07:45:49.54#ibcon#*after write, iclass 28, count 0 2006.246.07:45:49.54#ibcon#*before return 0, iclass 28, count 0 2006.246.07:45:49.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:49.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:49.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:45:49.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:45:49.54$vc4f8/valo=6,772.99 2006.246.07:45:49.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:45:49.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:45:49.54#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:49.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:49.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:49.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:49.54#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:45:49.54#ibcon#first serial, iclass 30, count 0 2006.246.07:45:49.54#ibcon#enter sib2, iclass 30, count 0 2006.246.07:45:49.54#ibcon#flushed, iclass 30, count 0 2006.246.07:45:49.54#ibcon#about to write, iclass 30, count 0 2006.246.07:45:49.54#ibcon#wrote, iclass 30, count 0 2006.246.07:45:49.54#ibcon#about to read 3, iclass 30, count 0 2006.246.07:45:49.56#ibcon#read 3, iclass 30, count 0 2006.246.07:45:49.56#ibcon#about to read 4, iclass 30, count 0 2006.246.07:45:49.56#ibcon#read 4, iclass 30, count 0 2006.246.07:45:49.56#ibcon#about to read 5, iclass 30, count 0 2006.246.07:45:49.56#ibcon#read 5, iclass 30, count 0 2006.246.07:45:49.56#ibcon#about to read 6, iclass 30, count 0 2006.246.07:45:49.56#ibcon#read 6, iclass 30, count 0 2006.246.07:45:49.56#ibcon#end of sib2, iclass 30, count 0 2006.246.07:45:49.56#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:45:49.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:45:49.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:45:49.56#ibcon#*before write, iclass 30, count 0 2006.246.07:45:49.56#ibcon#enter sib2, iclass 30, count 0 2006.246.07:45:49.56#ibcon#flushed, iclass 30, count 0 2006.246.07:45:49.56#ibcon#about to write, iclass 30, count 0 2006.246.07:45:49.56#ibcon#wrote, iclass 30, count 0 2006.246.07:45:49.56#ibcon#about to read 3, iclass 30, count 0 2006.246.07:45:49.60#ibcon#read 3, iclass 30, count 0 2006.246.07:45:49.60#ibcon#about to read 4, iclass 30, count 0 2006.246.07:45:49.60#ibcon#read 4, iclass 30, count 0 2006.246.07:45:49.60#ibcon#about to read 5, iclass 30, count 0 2006.246.07:45:49.60#ibcon#read 5, iclass 30, count 0 2006.246.07:45:49.60#ibcon#about to read 6, iclass 30, count 0 2006.246.07:45:49.60#ibcon#read 6, iclass 30, count 0 2006.246.07:45:49.60#ibcon#end of sib2, iclass 30, count 0 2006.246.07:45:49.60#ibcon#*after write, iclass 30, count 0 2006.246.07:45:49.60#ibcon#*before return 0, iclass 30, count 0 2006.246.07:45:49.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:49.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:49.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:45:49.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:45:49.60$vc4f8/va=6,7 2006.246.07:45:49.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:45:49.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:45:49.60#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:49.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:49.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:49.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:49.66#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:45:49.66#ibcon#first serial, iclass 32, count 2 2006.246.07:45:49.66#ibcon#enter sib2, iclass 32, count 2 2006.246.07:45:49.66#ibcon#flushed, iclass 32, count 2 2006.246.07:45:49.66#ibcon#about to write, iclass 32, count 2 2006.246.07:45:49.66#ibcon#wrote, iclass 32, count 2 2006.246.07:45:49.66#ibcon#about to read 3, iclass 32, count 2 2006.246.07:45:49.68#ibcon#read 3, iclass 32, count 2 2006.246.07:45:49.68#ibcon#about to read 4, iclass 32, count 2 2006.246.07:45:49.68#ibcon#read 4, iclass 32, count 2 2006.246.07:45:49.68#ibcon#about to read 5, iclass 32, count 2 2006.246.07:45:49.68#ibcon#read 5, iclass 32, count 2 2006.246.07:45:49.68#ibcon#about to read 6, iclass 32, count 2 2006.246.07:45:49.68#ibcon#read 6, iclass 32, count 2 2006.246.07:45:49.68#ibcon#end of sib2, iclass 32, count 2 2006.246.07:45:49.68#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:45:49.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:45:49.68#ibcon#[25=AT06-07\r\n] 2006.246.07:45:49.68#ibcon#*before write, iclass 32, count 2 2006.246.07:45:49.68#ibcon#enter sib2, iclass 32, count 2 2006.246.07:45:49.68#ibcon#flushed, iclass 32, count 2 2006.246.07:45:49.68#ibcon#about to write, iclass 32, count 2 2006.246.07:45:49.68#ibcon#wrote, iclass 32, count 2 2006.246.07:45:49.68#ibcon#about to read 3, iclass 32, count 2 2006.246.07:45:49.71#ibcon#read 3, iclass 32, count 2 2006.246.07:45:49.71#ibcon#about to read 4, iclass 32, count 2 2006.246.07:45:49.71#ibcon#read 4, iclass 32, count 2 2006.246.07:45:49.71#ibcon#about to read 5, iclass 32, count 2 2006.246.07:45:49.71#ibcon#read 5, iclass 32, count 2 2006.246.07:45:49.71#ibcon#about to read 6, iclass 32, count 2 2006.246.07:45:49.71#ibcon#read 6, iclass 32, count 2 2006.246.07:45:49.71#ibcon#end of sib2, iclass 32, count 2 2006.246.07:45:49.71#ibcon#*after write, iclass 32, count 2 2006.246.07:45:49.71#ibcon#*before return 0, iclass 32, count 2 2006.246.07:45:49.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:49.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:49.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:45:49.71#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:49.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:49.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:49.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:49.83#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:45:49.83#ibcon#first serial, iclass 32, count 0 2006.246.07:45:49.83#ibcon#enter sib2, iclass 32, count 0 2006.246.07:45:49.83#ibcon#flushed, iclass 32, count 0 2006.246.07:45:49.83#ibcon#about to write, iclass 32, count 0 2006.246.07:45:49.83#ibcon#wrote, iclass 32, count 0 2006.246.07:45:49.83#ibcon#about to read 3, iclass 32, count 0 2006.246.07:45:49.85#ibcon#read 3, iclass 32, count 0 2006.246.07:45:49.85#ibcon#about to read 4, iclass 32, count 0 2006.246.07:45:49.85#ibcon#read 4, iclass 32, count 0 2006.246.07:45:49.85#ibcon#about to read 5, iclass 32, count 0 2006.246.07:45:49.85#ibcon#read 5, iclass 32, count 0 2006.246.07:45:49.85#ibcon#about to read 6, iclass 32, count 0 2006.246.07:45:49.85#ibcon#read 6, iclass 32, count 0 2006.246.07:45:49.85#ibcon#end of sib2, iclass 32, count 0 2006.246.07:45:49.85#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:45:49.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:45:49.85#ibcon#[25=USB\r\n] 2006.246.07:45:49.85#ibcon#*before write, iclass 32, count 0 2006.246.07:45:49.85#ibcon#enter sib2, iclass 32, count 0 2006.246.07:45:49.85#ibcon#flushed, iclass 32, count 0 2006.246.07:45:49.85#ibcon#about to write, iclass 32, count 0 2006.246.07:45:49.85#ibcon#wrote, iclass 32, count 0 2006.246.07:45:49.85#ibcon#about to read 3, iclass 32, count 0 2006.246.07:45:49.88#ibcon#read 3, iclass 32, count 0 2006.246.07:45:49.88#ibcon#about to read 4, iclass 32, count 0 2006.246.07:45:49.88#ibcon#read 4, iclass 32, count 0 2006.246.07:45:49.88#ibcon#about to read 5, iclass 32, count 0 2006.246.07:45:49.88#ibcon#read 5, iclass 32, count 0 2006.246.07:45:49.88#ibcon#about to read 6, iclass 32, count 0 2006.246.07:45:49.88#ibcon#read 6, iclass 32, count 0 2006.246.07:45:49.88#ibcon#end of sib2, iclass 32, count 0 2006.246.07:45:49.88#ibcon#*after write, iclass 32, count 0 2006.246.07:45:49.88#ibcon#*before return 0, iclass 32, count 0 2006.246.07:45:49.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:49.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:49.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:45:49.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:45:49.88$vc4f8/valo=7,832.99 2006.246.07:45:49.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:45:49.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:45:49.88#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:49.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:49.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:49.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:49.88#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:45:49.88#ibcon#first serial, iclass 34, count 0 2006.246.07:45:49.88#ibcon#enter sib2, iclass 34, count 0 2006.246.07:45:49.88#ibcon#flushed, iclass 34, count 0 2006.246.07:45:49.88#ibcon#about to write, iclass 34, count 0 2006.246.07:45:49.88#ibcon#wrote, iclass 34, count 0 2006.246.07:45:49.88#ibcon#about to read 3, iclass 34, count 0 2006.246.07:45:49.90#ibcon#read 3, iclass 34, count 0 2006.246.07:45:49.90#ibcon#about to read 4, iclass 34, count 0 2006.246.07:45:49.90#ibcon#read 4, iclass 34, count 0 2006.246.07:45:49.90#ibcon#about to read 5, iclass 34, count 0 2006.246.07:45:49.90#ibcon#read 5, iclass 34, count 0 2006.246.07:45:49.90#ibcon#about to read 6, iclass 34, count 0 2006.246.07:45:49.90#ibcon#read 6, iclass 34, count 0 2006.246.07:45:49.90#ibcon#end of sib2, iclass 34, count 0 2006.246.07:45:49.90#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:45:49.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:45:49.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:45:49.90#ibcon#*before write, iclass 34, count 0 2006.246.07:45:49.90#ibcon#enter sib2, iclass 34, count 0 2006.246.07:45:49.90#ibcon#flushed, iclass 34, count 0 2006.246.07:45:49.90#ibcon#about to write, iclass 34, count 0 2006.246.07:45:49.90#ibcon#wrote, iclass 34, count 0 2006.246.07:45:49.90#ibcon#about to read 3, iclass 34, count 0 2006.246.07:45:49.94#ibcon#read 3, iclass 34, count 0 2006.246.07:45:49.94#ibcon#about to read 4, iclass 34, count 0 2006.246.07:45:49.94#ibcon#read 4, iclass 34, count 0 2006.246.07:45:49.94#ibcon#about to read 5, iclass 34, count 0 2006.246.07:45:49.94#ibcon#read 5, iclass 34, count 0 2006.246.07:45:49.94#ibcon#about to read 6, iclass 34, count 0 2006.246.07:45:49.94#ibcon#read 6, iclass 34, count 0 2006.246.07:45:49.94#ibcon#end of sib2, iclass 34, count 0 2006.246.07:45:49.94#ibcon#*after write, iclass 34, count 0 2006.246.07:45:49.94#ibcon#*before return 0, iclass 34, count 0 2006.246.07:45:49.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:49.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:49.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:45:49.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:45:49.94$vc4f8/va=7,7 2006.246.07:45:49.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:45:49.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:45:49.94#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:49.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:45:50.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:45:50.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:45:50.00#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:45:50.00#ibcon#first serial, iclass 36, count 2 2006.246.07:45:50.00#ibcon#enter sib2, iclass 36, count 2 2006.246.07:45:50.00#ibcon#flushed, iclass 36, count 2 2006.246.07:45:50.00#ibcon#about to write, iclass 36, count 2 2006.246.07:45:50.00#ibcon#wrote, iclass 36, count 2 2006.246.07:45:50.00#ibcon#about to read 3, iclass 36, count 2 2006.246.07:45:50.02#ibcon#read 3, iclass 36, count 2 2006.246.07:45:50.02#ibcon#about to read 4, iclass 36, count 2 2006.246.07:45:50.02#ibcon#read 4, iclass 36, count 2 2006.246.07:45:50.02#ibcon#about to read 5, iclass 36, count 2 2006.246.07:45:50.02#ibcon#read 5, iclass 36, count 2 2006.246.07:45:50.02#ibcon#about to read 6, iclass 36, count 2 2006.246.07:45:50.02#ibcon#read 6, iclass 36, count 2 2006.246.07:45:50.02#ibcon#end of sib2, iclass 36, count 2 2006.246.07:45:50.02#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:45:50.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:45:50.02#ibcon#[25=AT07-07\r\n] 2006.246.07:45:50.02#ibcon#*before write, iclass 36, count 2 2006.246.07:45:50.02#ibcon#enter sib2, iclass 36, count 2 2006.246.07:45:50.02#ibcon#flushed, iclass 36, count 2 2006.246.07:45:50.02#ibcon#about to write, iclass 36, count 2 2006.246.07:45:50.02#ibcon#wrote, iclass 36, count 2 2006.246.07:45:50.02#ibcon#about to read 3, iclass 36, count 2 2006.246.07:45:50.05#ibcon#read 3, iclass 36, count 2 2006.246.07:45:50.05#ibcon#about to read 4, iclass 36, count 2 2006.246.07:45:50.05#ibcon#read 4, iclass 36, count 2 2006.246.07:45:50.05#ibcon#about to read 5, iclass 36, count 2 2006.246.07:45:50.05#ibcon#read 5, iclass 36, count 2 2006.246.07:45:50.05#ibcon#about to read 6, iclass 36, count 2 2006.246.07:45:50.05#ibcon#read 6, iclass 36, count 2 2006.246.07:45:50.05#ibcon#end of sib2, iclass 36, count 2 2006.246.07:45:50.05#ibcon#*after write, iclass 36, count 2 2006.246.07:45:50.05#ibcon#*before return 0, iclass 36, count 2 2006.246.07:45:50.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:45:50.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:45:50.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:45:50.05#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:50.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:45:50.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:45:50.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:45:50.17#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:45:50.17#ibcon#first serial, iclass 36, count 0 2006.246.07:45:50.17#ibcon#enter sib2, iclass 36, count 0 2006.246.07:45:50.17#ibcon#flushed, iclass 36, count 0 2006.246.07:45:50.17#ibcon#about to write, iclass 36, count 0 2006.246.07:45:50.17#ibcon#wrote, iclass 36, count 0 2006.246.07:45:50.17#ibcon#about to read 3, iclass 36, count 0 2006.246.07:45:50.21#ibcon#read 3, iclass 36, count 0 2006.246.07:45:50.21#ibcon#about to read 4, iclass 36, count 0 2006.246.07:45:50.21#ibcon#read 4, iclass 36, count 0 2006.246.07:45:50.21#ibcon#about to read 5, iclass 36, count 0 2006.246.07:45:50.21#ibcon#read 5, iclass 36, count 0 2006.246.07:45:50.21#ibcon#about to read 6, iclass 36, count 0 2006.246.07:45:50.21#ibcon#read 6, iclass 36, count 0 2006.246.07:45:50.21#ibcon#end of sib2, iclass 36, count 0 2006.246.07:45:50.21#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:45:50.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:45:50.21#ibcon#[25=USB\r\n] 2006.246.07:45:50.21#ibcon#*before write, iclass 36, count 0 2006.246.07:45:50.21#ibcon#enter sib2, iclass 36, count 0 2006.246.07:45:50.21#ibcon#flushed, iclass 36, count 0 2006.246.07:45:50.21#ibcon#about to write, iclass 36, count 0 2006.246.07:45:50.21#ibcon#wrote, iclass 36, count 0 2006.246.07:45:50.21#ibcon#about to read 3, iclass 36, count 0 2006.246.07:45:50.23#ibcon#read 3, iclass 36, count 0 2006.246.07:45:50.23#ibcon#about to read 4, iclass 36, count 0 2006.246.07:45:50.23#ibcon#read 4, iclass 36, count 0 2006.246.07:45:50.23#ibcon#about to read 5, iclass 36, count 0 2006.246.07:45:50.23#ibcon#read 5, iclass 36, count 0 2006.246.07:45:50.23#ibcon#about to read 6, iclass 36, count 0 2006.246.07:45:50.23#ibcon#read 6, iclass 36, count 0 2006.246.07:45:50.23#ibcon#end of sib2, iclass 36, count 0 2006.246.07:45:50.23#ibcon#*after write, iclass 36, count 0 2006.246.07:45:50.23#ibcon#*before return 0, iclass 36, count 0 2006.246.07:45:50.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:45:50.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:45:50.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:45:50.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:45:50.23$vc4f8/valo=8,852.99 2006.246.07:45:50.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:45:50.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:45:50.23#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:50.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:45:50.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:45:50.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:45:50.23#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:45:50.23#ibcon#first serial, iclass 38, count 0 2006.246.07:45:50.23#ibcon#enter sib2, iclass 38, count 0 2006.246.07:45:50.23#ibcon#flushed, iclass 38, count 0 2006.246.07:45:50.23#ibcon#about to write, iclass 38, count 0 2006.246.07:45:50.23#ibcon#wrote, iclass 38, count 0 2006.246.07:45:50.23#ibcon#about to read 3, iclass 38, count 0 2006.246.07:45:50.25#ibcon#read 3, iclass 38, count 0 2006.246.07:45:50.25#ibcon#about to read 4, iclass 38, count 0 2006.246.07:45:50.25#ibcon#read 4, iclass 38, count 0 2006.246.07:45:50.25#ibcon#about to read 5, iclass 38, count 0 2006.246.07:45:50.25#ibcon#read 5, iclass 38, count 0 2006.246.07:45:50.25#ibcon#about to read 6, iclass 38, count 0 2006.246.07:45:50.25#ibcon#read 6, iclass 38, count 0 2006.246.07:45:50.25#ibcon#end of sib2, iclass 38, count 0 2006.246.07:45:50.25#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:45:50.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:45:50.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:45:50.25#ibcon#*before write, iclass 38, count 0 2006.246.07:45:50.25#ibcon#enter sib2, iclass 38, count 0 2006.246.07:45:50.25#ibcon#flushed, iclass 38, count 0 2006.246.07:45:50.25#ibcon#about to write, iclass 38, count 0 2006.246.07:45:50.25#ibcon#wrote, iclass 38, count 0 2006.246.07:45:50.25#ibcon#about to read 3, iclass 38, count 0 2006.246.07:45:50.29#ibcon#read 3, iclass 38, count 0 2006.246.07:45:50.29#ibcon#about to read 4, iclass 38, count 0 2006.246.07:45:50.29#ibcon#read 4, iclass 38, count 0 2006.246.07:45:50.29#ibcon#about to read 5, iclass 38, count 0 2006.246.07:45:50.29#ibcon#read 5, iclass 38, count 0 2006.246.07:45:50.29#ibcon#about to read 6, iclass 38, count 0 2006.246.07:45:50.29#ibcon#read 6, iclass 38, count 0 2006.246.07:45:50.29#ibcon#end of sib2, iclass 38, count 0 2006.246.07:45:50.29#ibcon#*after write, iclass 38, count 0 2006.246.07:45:50.29#ibcon#*before return 0, iclass 38, count 0 2006.246.07:45:50.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:45:50.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:45:50.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:45:50.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:45:50.29$vc4f8/va=8,8 2006.246.07:45:50.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.07:45:50.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.07:45:50.29#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:50.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:45:50.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:45:50.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:45:50.35#ibcon#enter wrdev, iclass 40, count 2 2006.246.07:45:50.35#ibcon#first serial, iclass 40, count 2 2006.246.07:45:50.35#ibcon#enter sib2, iclass 40, count 2 2006.246.07:45:50.35#ibcon#flushed, iclass 40, count 2 2006.246.07:45:50.35#ibcon#about to write, iclass 40, count 2 2006.246.07:45:50.35#ibcon#wrote, iclass 40, count 2 2006.246.07:45:50.35#ibcon#about to read 3, iclass 40, count 2 2006.246.07:45:50.37#ibcon#read 3, iclass 40, count 2 2006.246.07:45:50.37#ibcon#about to read 4, iclass 40, count 2 2006.246.07:45:50.37#ibcon#read 4, iclass 40, count 2 2006.246.07:45:50.37#ibcon#about to read 5, iclass 40, count 2 2006.246.07:45:50.37#ibcon#read 5, iclass 40, count 2 2006.246.07:45:50.37#ibcon#about to read 6, iclass 40, count 2 2006.246.07:45:50.37#ibcon#read 6, iclass 40, count 2 2006.246.07:45:50.37#ibcon#end of sib2, iclass 40, count 2 2006.246.07:45:50.37#ibcon#*mode == 0, iclass 40, count 2 2006.246.07:45:50.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.07:45:50.37#ibcon#[25=AT08-08\r\n] 2006.246.07:45:50.37#ibcon#*before write, iclass 40, count 2 2006.246.07:45:50.37#ibcon#enter sib2, iclass 40, count 2 2006.246.07:45:50.37#ibcon#flushed, iclass 40, count 2 2006.246.07:45:50.37#ibcon#about to write, iclass 40, count 2 2006.246.07:45:50.37#ibcon#wrote, iclass 40, count 2 2006.246.07:45:50.37#ibcon#about to read 3, iclass 40, count 2 2006.246.07:45:50.40#ibcon#read 3, iclass 40, count 2 2006.246.07:45:50.40#ibcon#about to read 4, iclass 40, count 2 2006.246.07:45:50.40#ibcon#read 4, iclass 40, count 2 2006.246.07:45:50.40#ibcon#about to read 5, iclass 40, count 2 2006.246.07:45:50.40#ibcon#read 5, iclass 40, count 2 2006.246.07:45:50.40#ibcon#about to read 6, iclass 40, count 2 2006.246.07:45:50.40#ibcon#read 6, iclass 40, count 2 2006.246.07:45:50.40#ibcon#end of sib2, iclass 40, count 2 2006.246.07:45:50.40#ibcon#*after write, iclass 40, count 2 2006.246.07:45:50.40#ibcon#*before return 0, iclass 40, count 2 2006.246.07:45:50.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:45:50.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.07:45:50.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.07:45:50.40#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:50.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:45:50.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:45:50.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:45:50.52#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:45:50.52#ibcon#first serial, iclass 40, count 0 2006.246.07:45:50.52#ibcon#enter sib2, iclass 40, count 0 2006.246.07:45:50.52#ibcon#flushed, iclass 40, count 0 2006.246.07:45:50.52#ibcon#about to write, iclass 40, count 0 2006.246.07:45:50.52#ibcon#wrote, iclass 40, count 0 2006.246.07:45:50.52#ibcon#about to read 3, iclass 40, count 0 2006.246.07:45:50.54#ibcon#read 3, iclass 40, count 0 2006.246.07:45:50.54#ibcon#about to read 4, iclass 40, count 0 2006.246.07:45:50.54#ibcon#read 4, iclass 40, count 0 2006.246.07:45:50.54#ibcon#about to read 5, iclass 40, count 0 2006.246.07:45:50.54#ibcon#read 5, iclass 40, count 0 2006.246.07:45:50.54#ibcon#about to read 6, iclass 40, count 0 2006.246.07:45:50.54#ibcon#read 6, iclass 40, count 0 2006.246.07:45:50.54#ibcon#end of sib2, iclass 40, count 0 2006.246.07:45:50.54#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:45:50.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:45:50.54#ibcon#[25=USB\r\n] 2006.246.07:45:50.54#ibcon#*before write, iclass 40, count 0 2006.246.07:45:50.54#ibcon#enter sib2, iclass 40, count 0 2006.246.07:45:50.54#ibcon#flushed, iclass 40, count 0 2006.246.07:45:50.54#ibcon#about to write, iclass 40, count 0 2006.246.07:45:50.54#ibcon#wrote, iclass 40, count 0 2006.246.07:45:50.54#ibcon#about to read 3, iclass 40, count 0 2006.246.07:45:50.57#ibcon#read 3, iclass 40, count 0 2006.246.07:45:50.57#ibcon#about to read 4, iclass 40, count 0 2006.246.07:45:50.57#ibcon#read 4, iclass 40, count 0 2006.246.07:45:50.57#ibcon#about to read 5, iclass 40, count 0 2006.246.07:45:50.57#ibcon#read 5, iclass 40, count 0 2006.246.07:45:50.57#ibcon#about to read 6, iclass 40, count 0 2006.246.07:45:50.57#ibcon#read 6, iclass 40, count 0 2006.246.07:45:50.57#ibcon#end of sib2, iclass 40, count 0 2006.246.07:45:50.57#ibcon#*after write, iclass 40, count 0 2006.246.07:45:50.57#ibcon#*before return 0, iclass 40, count 0 2006.246.07:45:50.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:45:50.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.07:45:50.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:45:50.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:45:50.57$vc4f8/vblo=1,632.99 2006.246.07:45:50.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.07:45:50.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.07:45:50.57#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:50.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:45:50.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:45:50.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:45:50.57#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:45:50.57#ibcon#first serial, iclass 4, count 0 2006.246.07:45:50.57#ibcon#enter sib2, iclass 4, count 0 2006.246.07:45:50.57#ibcon#flushed, iclass 4, count 0 2006.246.07:45:50.57#ibcon#about to write, iclass 4, count 0 2006.246.07:45:50.57#ibcon#wrote, iclass 4, count 0 2006.246.07:45:50.57#ibcon#about to read 3, iclass 4, count 0 2006.246.07:45:50.59#ibcon#read 3, iclass 4, count 0 2006.246.07:45:50.59#ibcon#about to read 4, iclass 4, count 0 2006.246.07:45:50.59#ibcon#read 4, iclass 4, count 0 2006.246.07:45:50.59#ibcon#about to read 5, iclass 4, count 0 2006.246.07:45:50.59#ibcon#read 5, iclass 4, count 0 2006.246.07:45:50.59#ibcon#about to read 6, iclass 4, count 0 2006.246.07:45:50.59#ibcon#read 6, iclass 4, count 0 2006.246.07:45:50.59#ibcon#end of sib2, iclass 4, count 0 2006.246.07:45:50.59#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:45:50.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:45:50.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:45:50.59#ibcon#*before write, iclass 4, count 0 2006.246.07:45:50.59#ibcon#enter sib2, iclass 4, count 0 2006.246.07:45:50.59#ibcon#flushed, iclass 4, count 0 2006.246.07:45:50.59#ibcon#about to write, iclass 4, count 0 2006.246.07:45:50.59#ibcon#wrote, iclass 4, count 0 2006.246.07:45:50.59#ibcon#about to read 3, iclass 4, count 0 2006.246.07:45:50.63#ibcon#read 3, iclass 4, count 0 2006.246.07:45:50.63#ibcon#about to read 4, iclass 4, count 0 2006.246.07:45:50.63#ibcon#read 4, iclass 4, count 0 2006.246.07:45:50.63#ibcon#about to read 5, iclass 4, count 0 2006.246.07:45:50.63#ibcon#read 5, iclass 4, count 0 2006.246.07:45:50.63#ibcon#about to read 6, iclass 4, count 0 2006.246.07:45:50.63#ibcon#read 6, iclass 4, count 0 2006.246.07:45:50.63#ibcon#end of sib2, iclass 4, count 0 2006.246.07:45:50.63#ibcon#*after write, iclass 4, count 0 2006.246.07:45:50.63#ibcon#*before return 0, iclass 4, count 0 2006.246.07:45:50.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:45:50.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.07:45:50.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:45:50.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:45:50.63$vc4f8/vb=1,4 2006.246.07:45:50.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.07:45:50.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.07:45:50.63#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:50.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:45:50.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:45:50.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:45:50.63#ibcon#enter wrdev, iclass 6, count 2 2006.246.07:45:50.63#ibcon#first serial, iclass 6, count 2 2006.246.07:45:50.63#ibcon#enter sib2, iclass 6, count 2 2006.246.07:45:50.63#ibcon#flushed, iclass 6, count 2 2006.246.07:45:50.63#ibcon#about to write, iclass 6, count 2 2006.246.07:45:50.63#ibcon#wrote, iclass 6, count 2 2006.246.07:45:50.63#ibcon#about to read 3, iclass 6, count 2 2006.246.07:45:50.65#ibcon#read 3, iclass 6, count 2 2006.246.07:45:50.65#ibcon#about to read 4, iclass 6, count 2 2006.246.07:45:50.65#ibcon#read 4, iclass 6, count 2 2006.246.07:45:50.65#ibcon#about to read 5, iclass 6, count 2 2006.246.07:45:50.65#ibcon#read 5, iclass 6, count 2 2006.246.07:45:50.65#ibcon#about to read 6, iclass 6, count 2 2006.246.07:45:50.65#ibcon#read 6, iclass 6, count 2 2006.246.07:45:50.65#ibcon#end of sib2, iclass 6, count 2 2006.246.07:45:50.65#ibcon#*mode == 0, iclass 6, count 2 2006.246.07:45:50.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.07:45:50.65#ibcon#[27=AT01-04\r\n] 2006.246.07:45:50.65#ibcon#*before write, iclass 6, count 2 2006.246.07:45:50.65#ibcon#enter sib2, iclass 6, count 2 2006.246.07:45:50.65#ibcon#flushed, iclass 6, count 2 2006.246.07:45:50.65#ibcon#about to write, iclass 6, count 2 2006.246.07:45:50.65#ibcon#wrote, iclass 6, count 2 2006.246.07:45:50.65#ibcon#about to read 3, iclass 6, count 2 2006.246.07:45:50.68#ibcon#read 3, iclass 6, count 2 2006.246.07:45:50.68#ibcon#about to read 4, iclass 6, count 2 2006.246.07:45:50.68#ibcon#read 4, iclass 6, count 2 2006.246.07:45:50.68#ibcon#about to read 5, iclass 6, count 2 2006.246.07:45:50.68#ibcon#read 5, iclass 6, count 2 2006.246.07:45:50.68#ibcon#about to read 6, iclass 6, count 2 2006.246.07:45:50.68#ibcon#read 6, iclass 6, count 2 2006.246.07:45:50.68#ibcon#end of sib2, iclass 6, count 2 2006.246.07:45:50.68#ibcon#*after write, iclass 6, count 2 2006.246.07:45:50.68#ibcon#*before return 0, iclass 6, count 2 2006.246.07:45:50.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:45:50.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.07:45:50.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.07:45:50.68#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:50.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:45:50.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:45:50.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:45:50.80#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:45:50.80#ibcon#first serial, iclass 6, count 0 2006.246.07:45:50.80#ibcon#enter sib2, iclass 6, count 0 2006.246.07:45:50.80#ibcon#flushed, iclass 6, count 0 2006.246.07:45:50.80#ibcon#about to write, iclass 6, count 0 2006.246.07:45:50.80#ibcon#wrote, iclass 6, count 0 2006.246.07:45:50.80#ibcon#about to read 3, iclass 6, count 0 2006.246.07:45:50.82#ibcon#read 3, iclass 6, count 0 2006.246.07:45:50.82#ibcon#about to read 4, iclass 6, count 0 2006.246.07:45:50.82#ibcon#read 4, iclass 6, count 0 2006.246.07:45:50.82#ibcon#about to read 5, iclass 6, count 0 2006.246.07:45:50.82#ibcon#read 5, iclass 6, count 0 2006.246.07:45:50.82#ibcon#about to read 6, iclass 6, count 0 2006.246.07:45:50.82#ibcon#read 6, iclass 6, count 0 2006.246.07:45:50.82#ibcon#end of sib2, iclass 6, count 0 2006.246.07:45:50.82#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:45:50.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:45:50.82#ibcon#[27=USB\r\n] 2006.246.07:45:50.82#ibcon#*before write, iclass 6, count 0 2006.246.07:45:50.82#ibcon#enter sib2, iclass 6, count 0 2006.246.07:45:50.82#ibcon#flushed, iclass 6, count 0 2006.246.07:45:50.82#ibcon#about to write, iclass 6, count 0 2006.246.07:45:50.82#ibcon#wrote, iclass 6, count 0 2006.246.07:45:50.82#ibcon#about to read 3, iclass 6, count 0 2006.246.07:45:50.85#ibcon#read 3, iclass 6, count 0 2006.246.07:45:50.85#ibcon#about to read 4, iclass 6, count 0 2006.246.07:45:50.85#ibcon#read 4, iclass 6, count 0 2006.246.07:45:50.85#ibcon#about to read 5, iclass 6, count 0 2006.246.07:45:50.85#ibcon#read 5, iclass 6, count 0 2006.246.07:45:50.85#ibcon#about to read 6, iclass 6, count 0 2006.246.07:45:50.85#ibcon#read 6, iclass 6, count 0 2006.246.07:45:50.85#ibcon#end of sib2, iclass 6, count 0 2006.246.07:45:50.85#ibcon#*after write, iclass 6, count 0 2006.246.07:45:50.85#ibcon#*before return 0, iclass 6, count 0 2006.246.07:45:50.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:45:50.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.07:45:50.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:45:50.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:45:50.85$vc4f8/vblo=2,640.99 2006.246.07:45:50.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.07:45:50.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.07:45:50.85#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:50.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:50.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:50.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:50.85#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:45:50.85#ibcon#first serial, iclass 10, count 0 2006.246.07:45:50.85#ibcon#enter sib2, iclass 10, count 0 2006.246.07:45:50.85#ibcon#flushed, iclass 10, count 0 2006.246.07:45:50.85#ibcon#about to write, iclass 10, count 0 2006.246.07:45:50.85#ibcon#wrote, iclass 10, count 0 2006.246.07:45:50.85#ibcon#about to read 3, iclass 10, count 0 2006.246.07:45:50.87#ibcon#read 3, iclass 10, count 0 2006.246.07:45:50.87#ibcon#about to read 4, iclass 10, count 0 2006.246.07:45:50.87#ibcon#read 4, iclass 10, count 0 2006.246.07:45:50.87#ibcon#about to read 5, iclass 10, count 0 2006.246.07:45:50.87#ibcon#read 5, iclass 10, count 0 2006.246.07:45:50.87#ibcon#about to read 6, iclass 10, count 0 2006.246.07:45:50.87#ibcon#read 6, iclass 10, count 0 2006.246.07:45:50.87#ibcon#end of sib2, iclass 10, count 0 2006.246.07:45:50.87#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:45:50.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:45:50.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:45:50.87#ibcon#*before write, iclass 10, count 0 2006.246.07:45:50.87#ibcon#enter sib2, iclass 10, count 0 2006.246.07:45:50.87#ibcon#flushed, iclass 10, count 0 2006.246.07:45:50.87#ibcon#about to write, iclass 10, count 0 2006.246.07:45:50.87#ibcon#wrote, iclass 10, count 0 2006.246.07:45:50.87#ibcon#about to read 3, iclass 10, count 0 2006.246.07:45:50.91#ibcon#read 3, iclass 10, count 0 2006.246.07:45:50.91#ibcon#about to read 4, iclass 10, count 0 2006.246.07:45:50.91#ibcon#read 4, iclass 10, count 0 2006.246.07:45:50.91#ibcon#about to read 5, iclass 10, count 0 2006.246.07:45:50.91#ibcon#read 5, iclass 10, count 0 2006.246.07:45:50.91#ibcon#about to read 6, iclass 10, count 0 2006.246.07:45:50.91#ibcon#read 6, iclass 10, count 0 2006.246.07:45:50.91#ibcon#end of sib2, iclass 10, count 0 2006.246.07:45:50.91#ibcon#*after write, iclass 10, count 0 2006.246.07:45:50.91#ibcon#*before return 0, iclass 10, count 0 2006.246.07:45:50.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:50.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:45:50.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:45:50.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:45:50.91$vc4f8/vb=2,4 2006.246.07:45:50.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.07:45:50.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.07:45:50.91#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:50.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:50.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:50.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:50.97#ibcon#enter wrdev, iclass 12, count 2 2006.246.07:45:50.97#ibcon#first serial, iclass 12, count 2 2006.246.07:45:50.97#ibcon#enter sib2, iclass 12, count 2 2006.246.07:45:50.97#ibcon#flushed, iclass 12, count 2 2006.246.07:45:50.97#ibcon#about to write, iclass 12, count 2 2006.246.07:45:50.97#ibcon#wrote, iclass 12, count 2 2006.246.07:45:50.97#ibcon#about to read 3, iclass 12, count 2 2006.246.07:45:50.99#ibcon#read 3, iclass 12, count 2 2006.246.07:45:50.99#ibcon#about to read 4, iclass 12, count 2 2006.246.07:45:50.99#ibcon#read 4, iclass 12, count 2 2006.246.07:45:50.99#ibcon#about to read 5, iclass 12, count 2 2006.246.07:45:50.99#ibcon#read 5, iclass 12, count 2 2006.246.07:45:50.99#ibcon#about to read 6, iclass 12, count 2 2006.246.07:45:50.99#ibcon#read 6, iclass 12, count 2 2006.246.07:45:50.99#ibcon#end of sib2, iclass 12, count 2 2006.246.07:45:50.99#ibcon#*mode == 0, iclass 12, count 2 2006.246.07:45:50.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.07:45:50.99#ibcon#[27=AT02-04\r\n] 2006.246.07:45:50.99#ibcon#*before write, iclass 12, count 2 2006.246.07:45:50.99#ibcon#enter sib2, iclass 12, count 2 2006.246.07:45:50.99#ibcon#flushed, iclass 12, count 2 2006.246.07:45:50.99#ibcon#about to write, iclass 12, count 2 2006.246.07:45:50.99#ibcon#wrote, iclass 12, count 2 2006.246.07:45:50.99#ibcon#about to read 3, iclass 12, count 2 2006.246.07:45:51.02#ibcon#read 3, iclass 12, count 2 2006.246.07:45:51.02#ibcon#about to read 4, iclass 12, count 2 2006.246.07:45:51.02#ibcon#read 4, iclass 12, count 2 2006.246.07:45:51.02#ibcon#about to read 5, iclass 12, count 2 2006.246.07:45:51.02#ibcon#read 5, iclass 12, count 2 2006.246.07:45:51.02#ibcon#about to read 6, iclass 12, count 2 2006.246.07:45:51.02#ibcon#read 6, iclass 12, count 2 2006.246.07:45:51.02#ibcon#end of sib2, iclass 12, count 2 2006.246.07:45:51.02#ibcon#*after write, iclass 12, count 2 2006.246.07:45:51.02#ibcon#*before return 0, iclass 12, count 2 2006.246.07:45:51.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:51.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:45:51.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.07:45:51.02#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:51.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:51.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:51.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:51.14#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:45:51.14#ibcon#first serial, iclass 12, count 0 2006.246.07:45:51.14#ibcon#enter sib2, iclass 12, count 0 2006.246.07:45:51.14#ibcon#flushed, iclass 12, count 0 2006.246.07:45:51.14#ibcon#about to write, iclass 12, count 0 2006.246.07:45:51.14#ibcon#wrote, iclass 12, count 0 2006.246.07:45:51.14#ibcon#about to read 3, iclass 12, count 0 2006.246.07:45:51.16#ibcon#read 3, iclass 12, count 0 2006.246.07:45:51.16#ibcon#about to read 4, iclass 12, count 0 2006.246.07:45:51.16#ibcon#read 4, iclass 12, count 0 2006.246.07:45:51.16#ibcon#about to read 5, iclass 12, count 0 2006.246.07:45:51.16#ibcon#read 5, iclass 12, count 0 2006.246.07:45:51.16#ibcon#about to read 6, iclass 12, count 0 2006.246.07:45:51.16#ibcon#read 6, iclass 12, count 0 2006.246.07:45:51.16#ibcon#end of sib2, iclass 12, count 0 2006.246.07:45:51.16#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:45:51.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:45:51.16#ibcon#[27=USB\r\n] 2006.246.07:45:51.16#ibcon#*before write, iclass 12, count 0 2006.246.07:45:51.16#ibcon#enter sib2, iclass 12, count 0 2006.246.07:45:51.16#ibcon#flushed, iclass 12, count 0 2006.246.07:45:51.16#ibcon#about to write, iclass 12, count 0 2006.246.07:45:51.16#ibcon#wrote, iclass 12, count 0 2006.246.07:45:51.16#ibcon#about to read 3, iclass 12, count 0 2006.246.07:45:51.19#ibcon#read 3, iclass 12, count 0 2006.246.07:45:51.19#ibcon#about to read 4, iclass 12, count 0 2006.246.07:45:51.19#ibcon#read 4, iclass 12, count 0 2006.246.07:45:51.19#ibcon#about to read 5, iclass 12, count 0 2006.246.07:45:51.19#ibcon#read 5, iclass 12, count 0 2006.246.07:45:51.19#ibcon#about to read 6, iclass 12, count 0 2006.246.07:45:51.19#ibcon#read 6, iclass 12, count 0 2006.246.07:45:51.19#ibcon#end of sib2, iclass 12, count 0 2006.246.07:45:51.19#ibcon#*after write, iclass 12, count 0 2006.246.07:45:51.19#ibcon#*before return 0, iclass 12, count 0 2006.246.07:45:51.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:51.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:45:51.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:45:51.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:45:51.19$vc4f8/vblo=3,656.99 2006.246.07:45:51.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.07:45:51.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.07:45:51.19#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:51.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:51.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:51.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:51.19#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:45:51.19#ibcon#first serial, iclass 14, count 0 2006.246.07:45:51.19#ibcon#enter sib2, iclass 14, count 0 2006.246.07:45:51.19#ibcon#flushed, iclass 14, count 0 2006.246.07:45:51.19#ibcon#about to write, iclass 14, count 0 2006.246.07:45:51.19#ibcon#wrote, iclass 14, count 0 2006.246.07:45:51.19#ibcon#about to read 3, iclass 14, count 0 2006.246.07:45:51.21#ibcon#read 3, iclass 14, count 0 2006.246.07:45:51.21#ibcon#about to read 4, iclass 14, count 0 2006.246.07:45:51.21#ibcon#read 4, iclass 14, count 0 2006.246.07:45:51.21#ibcon#about to read 5, iclass 14, count 0 2006.246.07:45:51.21#ibcon#read 5, iclass 14, count 0 2006.246.07:45:51.21#ibcon#about to read 6, iclass 14, count 0 2006.246.07:45:51.21#ibcon#read 6, iclass 14, count 0 2006.246.07:45:51.21#ibcon#end of sib2, iclass 14, count 0 2006.246.07:45:51.21#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:45:51.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:45:51.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:45:51.21#ibcon#*before write, iclass 14, count 0 2006.246.07:45:51.21#ibcon#enter sib2, iclass 14, count 0 2006.246.07:45:51.21#ibcon#flushed, iclass 14, count 0 2006.246.07:45:51.21#ibcon#about to write, iclass 14, count 0 2006.246.07:45:51.21#ibcon#wrote, iclass 14, count 0 2006.246.07:45:51.21#ibcon#about to read 3, iclass 14, count 0 2006.246.07:45:51.25#ibcon#read 3, iclass 14, count 0 2006.246.07:45:51.25#ibcon#about to read 4, iclass 14, count 0 2006.246.07:45:51.25#ibcon#read 4, iclass 14, count 0 2006.246.07:45:51.25#ibcon#about to read 5, iclass 14, count 0 2006.246.07:45:51.25#ibcon#read 5, iclass 14, count 0 2006.246.07:45:51.25#ibcon#about to read 6, iclass 14, count 0 2006.246.07:45:51.25#ibcon#read 6, iclass 14, count 0 2006.246.07:45:51.25#ibcon#end of sib2, iclass 14, count 0 2006.246.07:45:51.25#ibcon#*after write, iclass 14, count 0 2006.246.07:45:51.25#ibcon#*before return 0, iclass 14, count 0 2006.246.07:45:51.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:51.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:45:51.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:45:51.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:45:51.25$vc4f8/vb=3,4 2006.246.07:45:51.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.07:45:51.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.07:45:51.25#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:51.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:51.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:51.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:51.31#ibcon#enter wrdev, iclass 16, count 2 2006.246.07:45:51.31#ibcon#first serial, iclass 16, count 2 2006.246.07:45:51.31#ibcon#enter sib2, iclass 16, count 2 2006.246.07:45:51.31#ibcon#flushed, iclass 16, count 2 2006.246.07:45:51.31#ibcon#about to write, iclass 16, count 2 2006.246.07:45:51.31#ibcon#wrote, iclass 16, count 2 2006.246.07:45:51.31#ibcon#about to read 3, iclass 16, count 2 2006.246.07:45:51.33#ibcon#read 3, iclass 16, count 2 2006.246.07:45:51.33#ibcon#about to read 4, iclass 16, count 2 2006.246.07:45:51.33#ibcon#read 4, iclass 16, count 2 2006.246.07:45:51.33#ibcon#about to read 5, iclass 16, count 2 2006.246.07:45:51.33#ibcon#read 5, iclass 16, count 2 2006.246.07:45:51.33#ibcon#about to read 6, iclass 16, count 2 2006.246.07:45:51.33#ibcon#read 6, iclass 16, count 2 2006.246.07:45:51.33#ibcon#end of sib2, iclass 16, count 2 2006.246.07:45:51.33#ibcon#*mode == 0, iclass 16, count 2 2006.246.07:45:51.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.07:45:51.33#ibcon#[27=AT03-04\r\n] 2006.246.07:45:51.33#ibcon#*before write, iclass 16, count 2 2006.246.07:45:51.33#ibcon#enter sib2, iclass 16, count 2 2006.246.07:45:51.33#ibcon#flushed, iclass 16, count 2 2006.246.07:45:51.33#ibcon#about to write, iclass 16, count 2 2006.246.07:45:51.33#ibcon#wrote, iclass 16, count 2 2006.246.07:45:51.33#ibcon#about to read 3, iclass 16, count 2 2006.246.07:45:51.36#ibcon#read 3, iclass 16, count 2 2006.246.07:45:51.36#ibcon#about to read 4, iclass 16, count 2 2006.246.07:45:51.36#ibcon#read 4, iclass 16, count 2 2006.246.07:45:51.36#ibcon#about to read 5, iclass 16, count 2 2006.246.07:45:51.36#ibcon#read 5, iclass 16, count 2 2006.246.07:45:51.36#ibcon#about to read 6, iclass 16, count 2 2006.246.07:45:51.36#ibcon#read 6, iclass 16, count 2 2006.246.07:45:51.36#ibcon#end of sib2, iclass 16, count 2 2006.246.07:45:51.36#ibcon#*after write, iclass 16, count 2 2006.246.07:45:51.36#ibcon#*before return 0, iclass 16, count 2 2006.246.07:45:51.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:51.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:45:51.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.07:45:51.36#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:51.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:51.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:51.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:51.48#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:45:51.48#ibcon#first serial, iclass 16, count 0 2006.246.07:45:51.48#ibcon#enter sib2, iclass 16, count 0 2006.246.07:45:51.48#ibcon#flushed, iclass 16, count 0 2006.246.07:45:51.48#ibcon#about to write, iclass 16, count 0 2006.246.07:45:51.48#ibcon#wrote, iclass 16, count 0 2006.246.07:45:51.48#ibcon#about to read 3, iclass 16, count 0 2006.246.07:45:51.50#ibcon#read 3, iclass 16, count 0 2006.246.07:45:51.50#ibcon#about to read 4, iclass 16, count 0 2006.246.07:45:51.50#ibcon#read 4, iclass 16, count 0 2006.246.07:45:51.50#ibcon#about to read 5, iclass 16, count 0 2006.246.07:45:51.50#ibcon#read 5, iclass 16, count 0 2006.246.07:45:51.50#ibcon#about to read 6, iclass 16, count 0 2006.246.07:45:51.50#ibcon#read 6, iclass 16, count 0 2006.246.07:45:51.50#ibcon#end of sib2, iclass 16, count 0 2006.246.07:45:51.50#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:45:51.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:45:51.50#ibcon#[27=USB\r\n] 2006.246.07:45:51.50#ibcon#*before write, iclass 16, count 0 2006.246.07:45:51.50#ibcon#enter sib2, iclass 16, count 0 2006.246.07:45:51.50#ibcon#flushed, iclass 16, count 0 2006.246.07:45:51.50#ibcon#about to write, iclass 16, count 0 2006.246.07:45:51.50#ibcon#wrote, iclass 16, count 0 2006.246.07:45:51.50#ibcon#about to read 3, iclass 16, count 0 2006.246.07:45:51.53#ibcon#read 3, iclass 16, count 0 2006.246.07:45:51.53#ibcon#about to read 4, iclass 16, count 0 2006.246.07:45:51.53#ibcon#read 4, iclass 16, count 0 2006.246.07:45:51.53#ibcon#about to read 5, iclass 16, count 0 2006.246.07:45:51.53#ibcon#read 5, iclass 16, count 0 2006.246.07:45:51.53#ibcon#about to read 6, iclass 16, count 0 2006.246.07:45:51.53#ibcon#read 6, iclass 16, count 0 2006.246.07:45:51.53#ibcon#end of sib2, iclass 16, count 0 2006.246.07:45:51.53#ibcon#*after write, iclass 16, count 0 2006.246.07:45:51.53#ibcon#*before return 0, iclass 16, count 0 2006.246.07:45:51.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:51.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:45:51.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:45:51.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:45:51.53$vc4f8/vblo=4,712.99 2006.246.07:45:51.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:45:51.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:45:51.53#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:51.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:51.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:51.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:51.53#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:45:51.53#ibcon#first serial, iclass 18, count 0 2006.246.07:45:51.53#ibcon#enter sib2, iclass 18, count 0 2006.246.07:45:51.53#ibcon#flushed, iclass 18, count 0 2006.246.07:45:51.53#ibcon#about to write, iclass 18, count 0 2006.246.07:45:51.53#ibcon#wrote, iclass 18, count 0 2006.246.07:45:51.53#ibcon#about to read 3, iclass 18, count 0 2006.246.07:45:51.55#ibcon#read 3, iclass 18, count 0 2006.246.07:45:51.55#ibcon#about to read 4, iclass 18, count 0 2006.246.07:45:51.55#ibcon#read 4, iclass 18, count 0 2006.246.07:45:51.55#ibcon#about to read 5, iclass 18, count 0 2006.246.07:45:51.55#ibcon#read 5, iclass 18, count 0 2006.246.07:45:51.55#ibcon#about to read 6, iclass 18, count 0 2006.246.07:45:51.55#ibcon#read 6, iclass 18, count 0 2006.246.07:45:51.55#ibcon#end of sib2, iclass 18, count 0 2006.246.07:45:51.55#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:45:51.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:45:51.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:45:51.55#ibcon#*before write, iclass 18, count 0 2006.246.07:45:51.55#ibcon#enter sib2, iclass 18, count 0 2006.246.07:45:51.55#ibcon#flushed, iclass 18, count 0 2006.246.07:45:51.55#ibcon#about to write, iclass 18, count 0 2006.246.07:45:51.55#ibcon#wrote, iclass 18, count 0 2006.246.07:45:51.55#ibcon#about to read 3, iclass 18, count 0 2006.246.07:45:51.59#ibcon#read 3, iclass 18, count 0 2006.246.07:45:51.59#ibcon#about to read 4, iclass 18, count 0 2006.246.07:45:51.59#ibcon#read 4, iclass 18, count 0 2006.246.07:45:51.59#ibcon#about to read 5, iclass 18, count 0 2006.246.07:45:51.59#ibcon#read 5, iclass 18, count 0 2006.246.07:45:51.59#ibcon#about to read 6, iclass 18, count 0 2006.246.07:45:51.59#ibcon#read 6, iclass 18, count 0 2006.246.07:45:51.59#ibcon#end of sib2, iclass 18, count 0 2006.246.07:45:51.59#ibcon#*after write, iclass 18, count 0 2006.246.07:45:51.59#ibcon#*before return 0, iclass 18, count 0 2006.246.07:45:51.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:51.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:45:51.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:45:51.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:45:51.59$vc4f8/vb=4,4 2006.246.07:45:51.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.07:45:51.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.07:45:51.59#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:51.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:51.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:51.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:51.65#ibcon#enter wrdev, iclass 20, count 2 2006.246.07:45:51.65#ibcon#first serial, iclass 20, count 2 2006.246.07:45:51.65#ibcon#enter sib2, iclass 20, count 2 2006.246.07:45:51.65#ibcon#flushed, iclass 20, count 2 2006.246.07:45:51.65#ibcon#about to write, iclass 20, count 2 2006.246.07:45:51.65#ibcon#wrote, iclass 20, count 2 2006.246.07:45:51.65#ibcon#about to read 3, iclass 20, count 2 2006.246.07:45:51.67#ibcon#read 3, iclass 20, count 2 2006.246.07:45:51.67#ibcon#about to read 4, iclass 20, count 2 2006.246.07:45:51.67#ibcon#read 4, iclass 20, count 2 2006.246.07:45:51.67#ibcon#about to read 5, iclass 20, count 2 2006.246.07:45:51.67#ibcon#read 5, iclass 20, count 2 2006.246.07:45:51.67#ibcon#about to read 6, iclass 20, count 2 2006.246.07:45:51.67#ibcon#read 6, iclass 20, count 2 2006.246.07:45:51.67#ibcon#end of sib2, iclass 20, count 2 2006.246.07:45:51.67#ibcon#*mode == 0, iclass 20, count 2 2006.246.07:45:51.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.07:45:51.67#ibcon#[27=AT04-04\r\n] 2006.246.07:45:51.67#ibcon#*before write, iclass 20, count 2 2006.246.07:45:51.67#ibcon#enter sib2, iclass 20, count 2 2006.246.07:45:51.67#ibcon#flushed, iclass 20, count 2 2006.246.07:45:51.67#ibcon#about to write, iclass 20, count 2 2006.246.07:45:51.67#ibcon#wrote, iclass 20, count 2 2006.246.07:45:51.67#ibcon#about to read 3, iclass 20, count 2 2006.246.07:45:51.70#ibcon#read 3, iclass 20, count 2 2006.246.07:45:51.70#ibcon#about to read 4, iclass 20, count 2 2006.246.07:45:51.70#ibcon#read 4, iclass 20, count 2 2006.246.07:45:51.70#ibcon#about to read 5, iclass 20, count 2 2006.246.07:45:51.70#ibcon#read 5, iclass 20, count 2 2006.246.07:45:51.70#ibcon#about to read 6, iclass 20, count 2 2006.246.07:45:51.70#ibcon#read 6, iclass 20, count 2 2006.246.07:45:51.70#ibcon#end of sib2, iclass 20, count 2 2006.246.07:45:51.70#ibcon#*after write, iclass 20, count 2 2006.246.07:45:51.70#ibcon#*before return 0, iclass 20, count 2 2006.246.07:45:51.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:51.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:45:51.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.07:45:51.70#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:51.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:51.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:51.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:51.82#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:45:51.82#ibcon#first serial, iclass 20, count 0 2006.246.07:45:51.82#ibcon#enter sib2, iclass 20, count 0 2006.246.07:45:51.82#ibcon#flushed, iclass 20, count 0 2006.246.07:45:51.82#ibcon#about to write, iclass 20, count 0 2006.246.07:45:51.82#ibcon#wrote, iclass 20, count 0 2006.246.07:45:51.82#ibcon#about to read 3, iclass 20, count 0 2006.246.07:45:51.84#ibcon#read 3, iclass 20, count 0 2006.246.07:45:51.84#ibcon#about to read 4, iclass 20, count 0 2006.246.07:45:51.84#ibcon#read 4, iclass 20, count 0 2006.246.07:45:51.84#ibcon#about to read 5, iclass 20, count 0 2006.246.07:45:51.84#ibcon#read 5, iclass 20, count 0 2006.246.07:45:51.84#ibcon#about to read 6, iclass 20, count 0 2006.246.07:45:51.84#ibcon#read 6, iclass 20, count 0 2006.246.07:45:51.84#ibcon#end of sib2, iclass 20, count 0 2006.246.07:45:51.84#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:45:51.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:45:51.84#ibcon#[27=USB\r\n] 2006.246.07:45:51.84#ibcon#*before write, iclass 20, count 0 2006.246.07:45:51.84#ibcon#enter sib2, iclass 20, count 0 2006.246.07:45:51.84#ibcon#flushed, iclass 20, count 0 2006.246.07:45:51.84#ibcon#about to write, iclass 20, count 0 2006.246.07:45:51.84#ibcon#wrote, iclass 20, count 0 2006.246.07:45:51.84#ibcon#about to read 3, iclass 20, count 0 2006.246.07:45:51.87#abcon#<5=/04 3.4 7.1 26.73 751005.7\r\n> 2006.246.07:45:51.87#ibcon#read 3, iclass 20, count 0 2006.246.07:45:51.87#ibcon#about to read 4, iclass 20, count 0 2006.246.07:45:51.87#ibcon#read 4, iclass 20, count 0 2006.246.07:45:51.87#ibcon#about to read 5, iclass 20, count 0 2006.246.07:45:51.87#ibcon#read 5, iclass 20, count 0 2006.246.07:45:51.87#ibcon#about to read 6, iclass 20, count 0 2006.246.07:45:51.87#ibcon#read 6, iclass 20, count 0 2006.246.07:45:51.87#ibcon#end of sib2, iclass 20, count 0 2006.246.07:45:51.87#ibcon#*after write, iclass 20, count 0 2006.246.07:45:51.87#ibcon#*before return 0, iclass 20, count 0 2006.246.07:45:51.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:51.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:45:51.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:45:51.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:45:51.87$vc4f8/vblo=5,744.99 2006.246.07:45:51.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.07:45:51.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.07:45:51.87#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:51.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:45:51.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:45:51.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:45:51.87#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:45:51.87#ibcon#first serial, iclass 25, count 0 2006.246.07:45:51.87#ibcon#enter sib2, iclass 25, count 0 2006.246.07:45:51.87#ibcon#flushed, iclass 25, count 0 2006.246.07:45:51.87#ibcon#about to write, iclass 25, count 0 2006.246.07:45:51.87#ibcon#wrote, iclass 25, count 0 2006.246.07:45:51.87#ibcon#about to read 3, iclass 25, count 0 2006.246.07:45:51.90#abcon#{5=INTERFACE CLEAR} 2006.246.07:45:51.90#ibcon#read 3, iclass 25, count 0 2006.246.07:45:51.90#ibcon#about to read 4, iclass 25, count 0 2006.246.07:45:51.90#ibcon#read 4, iclass 25, count 0 2006.246.07:45:51.90#ibcon#about to read 5, iclass 25, count 0 2006.246.07:45:51.90#ibcon#read 5, iclass 25, count 0 2006.246.07:45:51.90#ibcon#about to read 6, iclass 25, count 0 2006.246.07:45:51.90#ibcon#read 6, iclass 25, count 0 2006.246.07:45:51.90#ibcon#end of sib2, iclass 25, count 0 2006.246.07:45:51.90#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:45:51.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:45:51.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:45:51.90#ibcon#*before write, iclass 25, count 0 2006.246.07:45:51.90#ibcon#enter sib2, iclass 25, count 0 2006.246.07:45:51.90#ibcon#flushed, iclass 25, count 0 2006.246.07:45:51.90#ibcon#about to write, iclass 25, count 0 2006.246.07:45:51.90#ibcon#wrote, iclass 25, count 0 2006.246.07:45:51.90#ibcon#about to read 3, iclass 25, count 0 2006.246.07:45:51.94#ibcon#read 3, iclass 25, count 0 2006.246.07:45:51.94#ibcon#about to read 4, iclass 25, count 0 2006.246.07:45:51.94#ibcon#read 4, iclass 25, count 0 2006.246.07:45:51.94#ibcon#about to read 5, iclass 25, count 0 2006.246.07:45:51.94#ibcon#read 5, iclass 25, count 0 2006.246.07:45:51.94#ibcon#about to read 6, iclass 25, count 0 2006.246.07:45:51.94#ibcon#read 6, iclass 25, count 0 2006.246.07:45:51.94#ibcon#end of sib2, iclass 25, count 0 2006.246.07:45:51.94#ibcon#*after write, iclass 25, count 0 2006.246.07:45:51.94#ibcon#*before return 0, iclass 25, count 0 2006.246.07:45:51.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:45:51.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:45:51.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:45:51.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:45:51.94$vc4f8/vb=5,3 2006.246.07:45:51.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:45:51.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:45:51.94#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:51.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:51.95#abcon#[5=S1D000X0/0*\r\n] 2006.246.07:45:51.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:51.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:51.99#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:45:51.99#ibcon#first serial, iclass 28, count 2 2006.246.07:45:51.99#ibcon#enter sib2, iclass 28, count 2 2006.246.07:45:51.99#ibcon#flushed, iclass 28, count 2 2006.246.07:45:51.99#ibcon#about to write, iclass 28, count 2 2006.246.07:45:51.99#ibcon#wrote, iclass 28, count 2 2006.246.07:45:51.99#ibcon#about to read 3, iclass 28, count 2 2006.246.07:45:52.01#ibcon#read 3, iclass 28, count 2 2006.246.07:45:52.01#ibcon#about to read 4, iclass 28, count 2 2006.246.07:45:52.01#ibcon#read 4, iclass 28, count 2 2006.246.07:45:52.01#ibcon#about to read 5, iclass 28, count 2 2006.246.07:45:52.01#ibcon#read 5, iclass 28, count 2 2006.246.07:45:52.01#ibcon#about to read 6, iclass 28, count 2 2006.246.07:45:52.01#ibcon#read 6, iclass 28, count 2 2006.246.07:45:52.01#ibcon#end of sib2, iclass 28, count 2 2006.246.07:45:52.01#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:45:52.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:45:52.01#ibcon#[27=AT05-03\r\n] 2006.246.07:45:52.01#ibcon#*before write, iclass 28, count 2 2006.246.07:45:52.01#ibcon#enter sib2, iclass 28, count 2 2006.246.07:45:52.01#ibcon#flushed, iclass 28, count 2 2006.246.07:45:52.01#ibcon#about to write, iclass 28, count 2 2006.246.07:45:52.01#ibcon#wrote, iclass 28, count 2 2006.246.07:45:52.01#ibcon#about to read 3, iclass 28, count 2 2006.246.07:45:52.04#ibcon#read 3, iclass 28, count 2 2006.246.07:45:52.04#ibcon#about to read 4, iclass 28, count 2 2006.246.07:45:52.04#ibcon#read 4, iclass 28, count 2 2006.246.07:45:52.04#ibcon#about to read 5, iclass 28, count 2 2006.246.07:45:52.04#ibcon#read 5, iclass 28, count 2 2006.246.07:45:52.04#ibcon#about to read 6, iclass 28, count 2 2006.246.07:45:52.04#ibcon#read 6, iclass 28, count 2 2006.246.07:45:52.04#ibcon#end of sib2, iclass 28, count 2 2006.246.07:45:52.04#ibcon#*after write, iclass 28, count 2 2006.246.07:45:52.04#ibcon#*before return 0, iclass 28, count 2 2006.246.07:45:52.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:52.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:45:52.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:45:52.04#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:52.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:52.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:52.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:52.16#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:45:52.16#ibcon#first serial, iclass 28, count 0 2006.246.07:45:52.16#ibcon#enter sib2, iclass 28, count 0 2006.246.07:45:52.16#ibcon#flushed, iclass 28, count 0 2006.246.07:45:52.16#ibcon#about to write, iclass 28, count 0 2006.246.07:45:52.16#ibcon#wrote, iclass 28, count 0 2006.246.07:45:52.16#ibcon#about to read 3, iclass 28, count 0 2006.246.07:45:52.18#ibcon#read 3, iclass 28, count 0 2006.246.07:45:52.18#ibcon#about to read 4, iclass 28, count 0 2006.246.07:45:52.18#ibcon#read 4, iclass 28, count 0 2006.246.07:45:52.18#ibcon#about to read 5, iclass 28, count 0 2006.246.07:45:52.18#ibcon#read 5, iclass 28, count 0 2006.246.07:45:52.18#ibcon#about to read 6, iclass 28, count 0 2006.246.07:45:52.18#ibcon#read 6, iclass 28, count 0 2006.246.07:45:52.18#ibcon#end of sib2, iclass 28, count 0 2006.246.07:45:52.18#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:45:52.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:45:52.18#ibcon#[27=USB\r\n] 2006.246.07:45:52.18#ibcon#*before write, iclass 28, count 0 2006.246.07:45:52.18#ibcon#enter sib2, iclass 28, count 0 2006.246.07:45:52.18#ibcon#flushed, iclass 28, count 0 2006.246.07:45:52.18#ibcon#about to write, iclass 28, count 0 2006.246.07:45:52.18#ibcon#wrote, iclass 28, count 0 2006.246.07:45:52.18#ibcon#about to read 3, iclass 28, count 0 2006.246.07:45:52.21#ibcon#read 3, iclass 28, count 0 2006.246.07:45:52.21#ibcon#about to read 4, iclass 28, count 0 2006.246.07:45:52.21#ibcon#read 4, iclass 28, count 0 2006.246.07:45:52.21#ibcon#about to read 5, iclass 28, count 0 2006.246.07:45:52.21#ibcon#read 5, iclass 28, count 0 2006.246.07:45:52.21#ibcon#about to read 6, iclass 28, count 0 2006.246.07:45:52.21#ibcon#read 6, iclass 28, count 0 2006.246.07:45:52.21#ibcon#end of sib2, iclass 28, count 0 2006.246.07:45:52.21#ibcon#*after write, iclass 28, count 0 2006.246.07:45:52.21#ibcon#*before return 0, iclass 28, count 0 2006.246.07:45:52.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:52.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:45:52.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:45:52.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:45:52.21$vc4f8/vblo=6,752.99 2006.246.07:45:52.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:45:52.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:45:52.21#ibcon#ireg 17 cls_cnt 0 2006.246.07:45:52.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:52.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:52.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:52.21#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:45:52.21#ibcon#first serial, iclass 30, count 0 2006.246.07:45:52.21#ibcon#enter sib2, iclass 30, count 0 2006.246.07:45:52.21#ibcon#flushed, iclass 30, count 0 2006.246.07:45:52.21#ibcon#about to write, iclass 30, count 0 2006.246.07:45:52.21#ibcon#wrote, iclass 30, count 0 2006.246.07:45:52.21#ibcon#about to read 3, iclass 30, count 0 2006.246.07:45:52.23#ibcon#read 3, iclass 30, count 0 2006.246.07:45:52.23#ibcon#about to read 4, iclass 30, count 0 2006.246.07:45:52.23#ibcon#read 4, iclass 30, count 0 2006.246.07:45:52.23#ibcon#about to read 5, iclass 30, count 0 2006.246.07:45:52.23#ibcon#read 5, iclass 30, count 0 2006.246.07:45:52.23#ibcon#about to read 6, iclass 30, count 0 2006.246.07:45:52.23#ibcon#read 6, iclass 30, count 0 2006.246.07:45:52.23#ibcon#end of sib2, iclass 30, count 0 2006.246.07:45:52.23#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:45:52.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:45:52.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:45:52.23#ibcon#*before write, iclass 30, count 0 2006.246.07:45:52.23#ibcon#enter sib2, iclass 30, count 0 2006.246.07:45:52.23#ibcon#flushed, iclass 30, count 0 2006.246.07:45:52.23#ibcon#about to write, iclass 30, count 0 2006.246.07:45:52.23#ibcon#wrote, iclass 30, count 0 2006.246.07:45:52.23#ibcon#about to read 3, iclass 30, count 0 2006.246.07:45:52.27#ibcon#read 3, iclass 30, count 0 2006.246.07:45:52.27#ibcon#about to read 4, iclass 30, count 0 2006.246.07:45:52.27#ibcon#read 4, iclass 30, count 0 2006.246.07:45:52.27#ibcon#about to read 5, iclass 30, count 0 2006.246.07:45:52.27#ibcon#read 5, iclass 30, count 0 2006.246.07:45:52.27#ibcon#about to read 6, iclass 30, count 0 2006.246.07:45:52.27#ibcon#read 6, iclass 30, count 0 2006.246.07:45:52.27#ibcon#end of sib2, iclass 30, count 0 2006.246.07:45:52.27#ibcon#*after write, iclass 30, count 0 2006.246.07:45:52.27#ibcon#*before return 0, iclass 30, count 0 2006.246.07:45:52.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:52.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:45:52.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:45:52.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:45:52.27$vc4f8/vb=6,3 2006.246.07:45:52.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:45:52.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:45:52.27#ibcon#ireg 11 cls_cnt 2 2006.246.07:45:52.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:52.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:52.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:52.33#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:45:52.33#ibcon#first serial, iclass 32, count 2 2006.246.07:45:52.33#ibcon#enter sib2, iclass 32, count 2 2006.246.07:45:52.33#ibcon#flushed, iclass 32, count 2 2006.246.07:45:52.33#ibcon#about to write, iclass 32, count 2 2006.246.07:45:52.33#ibcon#wrote, iclass 32, count 2 2006.246.07:45:52.33#ibcon#about to read 3, iclass 32, count 2 2006.246.07:45:52.35#ibcon#read 3, iclass 32, count 2 2006.246.07:45:52.35#ibcon#about to read 4, iclass 32, count 2 2006.246.07:45:52.35#ibcon#read 4, iclass 32, count 2 2006.246.07:45:52.35#ibcon#about to read 5, iclass 32, count 2 2006.246.07:45:52.35#ibcon#read 5, iclass 32, count 2 2006.246.07:45:52.35#ibcon#about to read 6, iclass 32, count 2 2006.246.07:45:52.35#ibcon#read 6, iclass 32, count 2 2006.246.07:45:52.35#ibcon#end of sib2, iclass 32, count 2 2006.246.07:45:52.35#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:45:52.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:45:52.35#ibcon#[27=AT06-03\r\n] 2006.246.07:45:52.35#ibcon#*before write, iclass 32, count 2 2006.246.07:45:52.35#ibcon#enter sib2, iclass 32, count 2 2006.246.07:45:52.35#ibcon#flushed, iclass 32, count 2 2006.246.07:45:52.35#ibcon#about to write, iclass 32, count 2 2006.246.07:45:52.35#ibcon#wrote, iclass 32, count 2 2006.246.07:45:52.35#ibcon#about to read 3, iclass 32, count 2 2006.246.07:45:52.38#ibcon#read 3, iclass 32, count 2 2006.246.07:45:52.38#ibcon#about to read 4, iclass 32, count 2 2006.246.07:45:52.38#ibcon#read 4, iclass 32, count 2 2006.246.07:45:52.38#ibcon#about to read 5, iclass 32, count 2 2006.246.07:45:52.38#ibcon#read 5, iclass 32, count 2 2006.246.07:45:52.38#ibcon#about to read 6, iclass 32, count 2 2006.246.07:45:52.38#ibcon#read 6, iclass 32, count 2 2006.246.07:45:52.38#ibcon#end of sib2, iclass 32, count 2 2006.246.07:45:52.38#ibcon#*after write, iclass 32, count 2 2006.246.07:45:52.38#ibcon#*before return 0, iclass 32, count 2 2006.246.07:45:52.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:52.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:45:52.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:45:52.38#ibcon#ireg 7 cls_cnt 0 2006.246.07:45:52.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:52.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:52.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:52.50#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:45:52.50#ibcon#first serial, iclass 32, count 0 2006.246.07:45:52.50#ibcon#enter sib2, iclass 32, count 0 2006.246.07:45:52.50#ibcon#flushed, iclass 32, count 0 2006.246.07:45:52.50#ibcon#about to write, iclass 32, count 0 2006.246.07:45:52.50#ibcon#wrote, iclass 32, count 0 2006.246.07:45:52.50#ibcon#about to read 3, iclass 32, count 0 2006.246.07:45:52.52#ibcon#read 3, iclass 32, count 0 2006.246.07:45:52.52#ibcon#about to read 4, iclass 32, count 0 2006.246.07:45:52.52#ibcon#read 4, iclass 32, count 0 2006.246.07:45:52.52#ibcon#about to read 5, iclass 32, count 0 2006.246.07:45:52.52#ibcon#read 5, iclass 32, count 0 2006.246.07:45:52.52#ibcon#about to read 6, iclass 32, count 0 2006.246.07:45:52.52#ibcon#read 6, iclass 32, count 0 2006.246.07:45:52.52#ibcon#end of sib2, iclass 32, count 0 2006.246.07:45:52.52#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:45:52.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:45:52.52#ibcon#[27=USB\r\n] 2006.246.07:45:52.52#ibcon#*before write, iclass 32, count 0 2006.246.07:45:52.52#ibcon#enter sib2, iclass 32, count 0 2006.246.07:45:52.52#ibcon#flushed, iclass 32, count 0 2006.246.07:45:52.52#ibcon#about to write, iclass 32, count 0 2006.246.07:45:52.52#ibcon#wrote, iclass 32, count 0 2006.246.07:45:52.52#ibcon#about to read 3, iclass 32, count 0 2006.246.07:45:52.55#ibcon#read 3, iclass 32, count 0 2006.246.07:45:52.55#ibcon#about to read 4, iclass 32, count 0 2006.246.07:45:52.55#ibcon#read 4, iclass 32, count 0 2006.246.07:45:52.55#ibcon#about to read 5, iclass 32, count 0 2006.246.07:45:52.55#ibcon#read 5, iclass 32, count 0 2006.246.07:45:52.55#ibcon#about to read 6, iclass 32, count 0 2006.246.07:45:52.55#ibcon#read 6, iclass 32, count 0 2006.246.07:45:52.55#ibcon#end of sib2, iclass 32, count 0 2006.246.07:45:52.55#ibcon#*after write, iclass 32, count 0 2006.246.07:45:52.55#ibcon#*before return 0, iclass 32, count 0 2006.246.07:45:52.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:52.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:45:52.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:45:52.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:45:52.55$vc4f8/vabw=wide 2006.246.07:45:52.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:45:52.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:45:52.55#ibcon#ireg 8 cls_cnt 0 2006.246.07:45:52.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:52.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:52.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:52.55#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:45:52.55#ibcon#first serial, iclass 34, count 0 2006.246.07:45:52.55#ibcon#enter sib2, iclass 34, count 0 2006.246.07:45:52.55#ibcon#flushed, iclass 34, count 0 2006.246.07:45:52.55#ibcon#about to write, iclass 34, count 0 2006.246.07:45:52.55#ibcon#wrote, iclass 34, count 0 2006.246.07:45:52.55#ibcon#about to read 3, iclass 34, count 0 2006.246.07:45:52.57#ibcon#read 3, iclass 34, count 0 2006.246.07:45:52.57#ibcon#about to read 4, iclass 34, count 0 2006.246.07:45:52.57#ibcon#read 4, iclass 34, count 0 2006.246.07:45:52.57#ibcon#about to read 5, iclass 34, count 0 2006.246.07:45:52.57#ibcon#read 5, iclass 34, count 0 2006.246.07:45:52.57#ibcon#about to read 6, iclass 34, count 0 2006.246.07:45:52.57#ibcon#read 6, iclass 34, count 0 2006.246.07:45:52.57#ibcon#end of sib2, iclass 34, count 0 2006.246.07:45:52.57#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:45:52.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:45:52.57#ibcon#[25=BW32\r\n] 2006.246.07:45:52.57#ibcon#*before write, iclass 34, count 0 2006.246.07:45:52.57#ibcon#enter sib2, iclass 34, count 0 2006.246.07:45:52.57#ibcon#flushed, iclass 34, count 0 2006.246.07:45:52.57#ibcon#about to write, iclass 34, count 0 2006.246.07:45:52.57#ibcon#wrote, iclass 34, count 0 2006.246.07:45:52.57#ibcon#about to read 3, iclass 34, count 0 2006.246.07:45:52.60#ibcon#read 3, iclass 34, count 0 2006.246.07:45:52.60#ibcon#about to read 4, iclass 34, count 0 2006.246.07:45:52.60#ibcon#read 4, iclass 34, count 0 2006.246.07:45:52.60#ibcon#about to read 5, iclass 34, count 0 2006.246.07:45:52.60#ibcon#read 5, iclass 34, count 0 2006.246.07:45:52.60#ibcon#about to read 6, iclass 34, count 0 2006.246.07:45:52.60#ibcon#read 6, iclass 34, count 0 2006.246.07:45:52.60#ibcon#end of sib2, iclass 34, count 0 2006.246.07:45:52.60#ibcon#*after write, iclass 34, count 0 2006.246.07:45:52.60#ibcon#*before return 0, iclass 34, count 0 2006.246.07:45:52.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:52.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:45:52.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:45:52.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:45:52.60$vc4f8/vbbw=wide 2006.246.07:45:52.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.07:45:52.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.07:45:52.60#ibcon#ireg 8 cls_cnt 0 2006.246.07:45:52.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:45:52.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:45:52.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:45:52.67#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:45:52.67#ibcon#first serial, iclass 36, count 0 2006.246.07:45:52.67#ibcon#enter sib2, iclass 36, count 0 2006.246.07:45:52.67#ibcon#flushed, iclass 36, count 0 2006.246.07:45:52.67#ibcon#about to write, iclass 36, count 0 2006.246.07:45:52.67#ibcon#wrote, iclass 36, count 0 2006.246.07:45:52.67#ibcon#about to read 3, iclass 36, count 0 2006.246.07:45:52.69#ibcon#read 3, iclass 36, count 0 2006.246.07:45:52.69#ibcon#about to read 4, iclass 36, count 0 2006.246.07:45:52.69#ibcon#read 4, iclass 36, count 0 2006.246.07:45:52.69#ibcon#about to read 5, iclass 36, count 0 2006.246.07:45:52.69#ibcon#read 5, iclass 36, count 0 2006.246.07:45:52.69#ibcon#about to read 6, iclass 36, count 0 2006.246.07:45:52.69#ibcon#read 6, iclass 36, count 0 2006.246.07:45:52.69#ibcon#end of sib2, iclass 36, count 0 2006.246.07:45:52.69#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:45:52.69#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:45:52.69#ibcon#[27=BW32\r\n] 2006.246.07:45:52.69#ibcon#*before write, iclass 36, count 0 2006.246.07:45:52.69#ibcon#enter sib2, iclass 36, count 0 2006.246.07:45:52.69#ibcon#flushed, iclass 36, count 0 2006.246.07:45:52.69#ibcon#about to write, iclass 36, count 0 2006.246.07:45:52.69#ibcon#wrote, iclass 36, count 0 2006.246.07:45:52.69#ibcon#about to read 3, iclass 36, count 0 2006.246.07:45:52.72#ibcon#read 3, iclass 36, count 0 2006.246.07:45:52.72#ibcon#about to read 4, iclass 36, count 0 2006.246.07:45:52.72#ibcon#read 4, iclass 36, count 0 2006.246.07:45:52.72#ibcon#about to read 5, iclass 36, count 0 2006.246.07:45:52.72#ibcon#read 5, iclass 36, count 0 2006.246.07:45:52.72#ibcon#about to read 6, iclass 36, count 0 2006.246.07:45:52.72#ibcon#read 6, iclass 36, count 0 2006.246.07:45:52.72#ibcon#end of sib2, iclass 36, count 0 2006.246.07:45:52.72#ibcon#*after write, iclass 36, count 0 2006.246.07:45:52.72#ibcon#*before return 0, iclass 36, count 0 2006.246.07:45:52.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:45:52.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:45:52.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:45:52.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:45:52.72$4f8m12a/ifd4f 2006.246.07:45:52.72$ifd4f/lo= 2006.246.07:45:52.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:45:52.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:45:52.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:45:52.72$ifd4f/patch= 2006.246.07:45:52.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:45:52.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:45:52.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:45:52.72$4f8m12a/"form=m,16.000,1:2 2006.246.07:45:52.72$4f8m12a/"tpicd 2006.246.07:45:52.72$4f8m12a/echo=off 2006.246.07:45:52.72$4f8m12a/xlog=off 2006.246.07:45:52.73:!2006.246.07:46:20 2006.246.07:46:07.13#trakl#Source acquired 2006.246.07:46:08.13#flagr#flagr/antenna,acquired 2006.246.07:46:20.01:preob 2006.246.07:46:21.13/onsource/TRACKING 2006.246.07:46:21.13:!2006.246.07:46:30 2006.246.07:46:30.00:data_valid=on 2006.246.07:46:30.00:midob 2006.246.07:46:30.13/onsource/TRACKING 2006.246.07:46:30.13/wx/26.73,1005.7,75 2006.246.07:46:30.22/cable/+6.4129E-03 2006.246.07:46:31.31/va/01,08,usb,yes,35,37 2006.246.07:46:31.31/va/02,07,usb,yes,35,36 2006.246.07:46:31.31/va/03,06,usb,yes,37,37 2006.246.07:46:31.31/va/04,07,usb,yes,36,39 2006.246.07:46:31.31/va/05,07,usb,yes,39,41 2006.246.07:46:31.31/va/06,07,usb,yes,34,34 2006.246.07:46:31.31/va/07,07,usb,yes,34,33 2006.246.07:46:31.31/va/08,08,usb,yes,29,29 2006.246.07:46:31.54/valo/01,532.99,yes,locked 2006.246.07:46:31.54/valo/02,572.99,yes,locked 2006.246.07:46:31.54/valo/03,672.99,yes,locked 2006.246.07:46:31.54/valo/04,832.99,yes,locked 2006.246.07:46:31.54/valo/05,652.99,yes,locked 2006.246.07:46:31.54/valo/06,772.99,yes,locked 2006.246.07:46:31.54/valo/07,832.99,yes,locked 2006.246.07:46:31.54/valo/08,852.99,yes,locked 2006.246.07:46:32.63/vb/01,04,usb,yes,33,32 2006.246.07:46:32.63/vb/02,04,usb,yes,35,37 2006.246.07:46:32.63/vb/03,04,usb,yes,31,35 2006.246.07:46:32.63/vb/04,04,usb,yes,33,33 2006.246.07:46:32.63/vb/05,03,usb,yes,38,44 2006.246.07:46:32.63/vb/06,03,usb,yes,39,43 2006.246.07:46:32.63/vb/07,04,usb,yes,34,35 2006.246.07:46:32.63/vb/08,03,usb,yes,39,44 2006.246.07:46:32.86/vblo/01,632.99,yes,locked 2006.246.07:46:32.86/vblo/02,640.99,yes,locked 2006.246.07:46:32.86/vblo/03,656.99,yes,locked 2006.246.07:46:32.86/vblo/04,712.99,yes,locked 2006.246.07:46:32.86/vblo/05,744.99,yes,locked 2006.246.07:46:32.86/vblo/06,752.99,yes,locked 2006.246.07:46:32.86/vblo/07,734.99,yes,locked 2006.246.07:46:32.86/vblo/08,744.99,yes,locked 2006.246.07:46:33.01/vabw/8 2006.246.07:46:33.16/vbbw/8 2006.246.07:46:33.25/xfe/off,on,13.2 2006.246.07:46:33.63/ifatt/23,28,28,28 2006.246.07:46:34.07/fmout-gps/S +4.36E-07 2006.246.07:46:34.11:!2006.246.07:47:30 2006.246.07:47:30.00:data_valid=off 2006.246.07:47:30.01:postob 2006.246.07:47:30.14/cable/+6.4128E-03 2006.246.07:47:30.15/wx/26.74,1005.7,74 2006.246.07:47:31.08/fmout-gps/S +4.35E-07 2006.246.07:47:31.09:scan_name=246-0748,k06246,60 2006.246.07:47:31.09:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.246.07:47:31.14#flagr#flagr/antenna,new-source 2006.246.07:47:32.14:checkk5 2006.246.07:47:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:47:32.96/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:47:33.34/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:47:33.72/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:47:34.09/chk_obsdata//k5ts1/T2460746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:47:34.46/chk_obsdata//k5ts2/T2460746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:47:34.82/chk_obsdata//k5ts3/T2460746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:47:35.19/chk_obsdata//k5ts4/T2460746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:47:35.88/k5log//k5ts1_log_newline 2006.246.07:47:36.56/k5log//k5ts2_log_newline 2006.246.07:47:37.26/k5log//k5ts3_log_newline 2006.246.07:47:37.96/k5log//k5ts4_log_newline 2006.246.07:47:37.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:47:37.99:4f8m12a=1 2006.246.07:47:37.99$4f8m12a/echo=on 2006.246.07:47:37.99$4f8m12a/pcalon 2006.246.07:47:37.99$pcalon/"no phase cal control is implemented here 2006.246.07:47:37.99$4f8m12a/"tpicd=stop 2006.246.07:47:37.99$4f8m12a/vc4f8 2006.246.07:47:37.99$vc4f8/valo=1,532.99 2006.246.07:47:37.99#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:47:37.99#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:47:37.99#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:37.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:37.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:37.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:37.99#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:47:37.99#ibcon#first serial, iclass 5, count 0 2006.246.07:47:37.99#ibcon#enter sib2, iclass 5, count 0 2006.246.07:47:37.99#ibcon#flushed, iclass 5, count 0 2006.246.07:47:37.99#ibcon#about to write, iclass 5, count 0 2006.246.07:47:37.99#ibcon#wrote, iclass 5, count 0 2006.246.07:47:37.99#ibcon#about to read 3, iclass 5, count 0 2006.246.07:47:38.03#ibcon#read 3, iclass 5, count 0 2006.246.07:47:38.03#ibcon#about to read 4, iclass 5, count 0 2006.246.07:47:38.03#ibcon#read 4, iclass 5, count 0 2006.246.07:47:38.03#ibcon#about to read 5, iclass 5, count 0 2006.246.07:47:38.03#ibcon#read 5, iclass 5, count 0 2006.246.07:47:38.03#ibcon#about to read 6, iclass 5, count 0 2006.246.07:47:38.03#ibcon#read 6, iclass 5, count 0 2006.246.07:47:38.03#ibcon#end of sib2, iclass 5, count 0 2006.246.07:47:38.03#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:47:38.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:47:38.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:47:38.03#ibcon#*before write, iclass 5, count 0 2006.246.07:47:38.03#ibcon#enter sib2, iclass 5, count 0 2006.246.07:47:38.03#ibcon#flushed, iclass 5, count 0 2006.246.07:47:38.03#ibcon#about to write, iclass 5, count 0 2006.246.07:47:38.03#ibcon#wrote, iclass 5, count 0 2006.246.07:47:38.03#ibcon#about to read 3, iclass 5, count 0 2006.246.07:47:38.07#ibcon#read 3, iclass 5, count 0 2006.246.07:47:38.07#ibcon#about to read 4, iclass 5, count 0 2006.246.07:47:38.07#ibcon#read 4, iclass 5, count 0 2006.246.07:47:38.07#ibcon#about to read 5, iclass 5, count 0 2006.246.07:47:38.07#ibcon#read 5, iclass 5, count 0 2006.246.07:47:38.07#ibcon#about to read 6, iclass 5, count 0 2006.246.07:47:38.07#ibcon#read 6, iclass 5, count 0 2006.246.07:47:38.07#ibcon#end of sib2, iclass 5, count 0 2006.246.07:47:38.07#ibcon#*after write, iclass 5, count 0 2006.246.07:47:38.07#ibcon#*before return 0, iclass 5, count 0 2006.246.07:47:38.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:38.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:38.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:47:38.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:47:38.07$vc4f8/va=1,8 2006.246.07:47:38.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:47:38.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:47:38.07#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:38.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:38.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:38.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:38.07#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:47:38.07#ibcon#first serial, iclass 7, count 2 2006.246.07:47:38.07#ibcon#enter sib2, iclass 7, count 2 2006.246.07:47:38.07#ibcon#flushed, iclass 7, count 2 2006.246.07:47:38.07#ibcon#about to write, iclass 7, count 2 2006.246.07:47:38.07#ibcon#wrote, iclass 7, count 2 2006.246.07:47:38.07#ibcon#about to read 3, iclass 7, count 2 2006.246.07:47:38.09#ibcon#read 3, iclass 7, count 2 2006.246.07:47:38.09#ibcon#about to read 4, iclass 7, count 2 2006.246.07:47:38.09#ibcon#read 4, iclass 7, count 2 2006.246.07:47:38.09#ibcon#about to read 5, iclass 7, count 2 2006.246.07:47:38.09#ibcon#read 5, iclass 7, count 2 2006.246.07:47:38.09#ibcon#about to read 6, iclass 7, count 2 2006.246.07:47:38.09#ibcon#read 6, iclass 7, count 2 2006.246.07:47:38.09#ibcon#end of sib2, iclass 7, count 2 2006.246.07:47:38.09#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:47:38.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:47:38.09#ibcon#[25=AT01-08\r\n] 2006.246.07:47:38.09#ibcon#*before write, iclass 7, count 2 2006.246.07:47:38.09#ibcon#enter sib2, iclass 7, count 2 2006.246.07:47:38.09#ibcon#flushed, iclass 7, count 2 2006.246.07:47:38.09#ibcon#about to write, iclass 7, count 2 2006.246.07:47:38.09#ibcon#wrote, iclass 7, count 2 2006.246.07:47:38.09#ibcon#about to read 3, iclass 7, count 2 2006.246.07:47:38.13#ibcon#read 3, iclass 7, count 2 2006.246.07:47:38.13#ibcon#about to read 4, iclass 7, count 2 2006.246.07:47:38.13#ibcon#read 4, iclass 7, count 2 2006.246.07:47:38.13#ibcon#about to read 5, iclass 7, count 2 2006.246.07:47:38.13#ibcon#read 5, iclass 7, count 2 2006.246.07:47:38.13#ibcon#about to read 6, iclass 7, count 2 2006.246.07:47:38.13#ibcon#read 6, iclass 7, count 2 2006.246.07:47:38.13#ibcon#end of sib2, iclass 7, count 2 2006.246.07:47:38.13#ibcon#*after write, iclass 7, count 2 2006.246.07:47:38.13#ibcon#*before return 0, iclass 7, count 2 2006.246.07:47:38.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:38.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:38.13#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:47:38.13#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:38.13#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:38.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:38.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:38.24#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:47:38.24#ibcon#first serial, iclass 7, count 0 2006.246.07:47:38.24#ibcon#enter sib2, iclass 7, count 0 2006.246.07:47:38.24#ibcon#flushed, iclass 7, count 0 2006.246.07:47:38.24#ibcon#about to write, iclass 7, count 0 2006.246.07:47:38.24#ibcon#wrote, iclass 7, count 0 2006.246.07:47:38.24#ibcon#about to read 3, iclass 7, count 0 2006.246.07:47:38.26#ibcon#read 3, iclass 7, count 0 2006.246.07:47:38.26#ibcon#about to read 4, iclass 7, count 0 2006.246.07:47:38.26#ibcon#read 4, iclass 7, count 0 2006.246.07:47:38.26#ibcon#about to read 5, iclass 7, count 0 2006.246.07:47:38.26#ibcon#read 5, iclass 7, count 0 2006.246.07:47:38.26#ibcon#about to read 6, iclass 7, count 0 2006.246.07:47:38.26#ibcon#read 6, iclass 7, count 0 2006.246.07:47:38.26#ibcon#end of sib2, iclass 7, count 0 2006.246.07:47:38.26#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:47:38.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:47:38.26#ibcon#[25=USB\r\n] 2006.246.07:47:38.26#ibcon#*before write, iclass 7, count 0 2006.246.07:47:38.26#ibcon#enter sib2, iclass 7, count 0 2006.246.07:47:38.26#ibcon#flushed, iclass 7, count 0 2006.246.07:47:38.26#ibcon#about to write, iclass 7, count 0 2006.246.07:47:38.26#ibcon#wrote, iclass 7, count 0 2006.246.07:47:38.26#ibcon#about to read 3, iclass 7, count 0 2006.246.07:47:38.29#ibcon#read 3, iclass 7, count 0 2006.246.07:47:38.29#ibcon#about to read 4, iclass 7, count 0 2006.246.07:47:38.29#ibcon#read 4, iclass 7, count 0 2006.246.07:47:38.29#ibcon#about to read 5, iclass 7, count 0 2006.246.07:47:38.29#ibcon#read 5, iclass 7, count 0 2006.246.07:47:38.29#ibcon#about to read 6, iclass 7, count 0 2006.246.07:47:38.29#ibcon#read 6, iclass 7, count 0 2006.246.07:47:38.29#ibcon#end of sib2, iclass 7, count 0 2006.246.07:47:38.29#ibcon#*after write, iclass 7, count 0 2006.246.07:47:38.29#ibcon#*before return 0, iclass 7, count 0 2006.246.07:47:38.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:38.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:38.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:47:38.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:47:38.29$vc4f8/valo=2,572.99 2006.246.07:47:38.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:47:38.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:47:38.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:38.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:38.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:38.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:38.29#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:47:38.29#ibcon#first serial, iclass 11, count 0 2006.246.07:47:38.29#ibcon#enter sib2, iclass 11, count 0 2006.246.07:47:38.29#ibcon#flushed, iclass 11, count 0 2006.246.07:47:38.29#ibcon#about to write, iclass 11, count 0 2006.246.07:47:38.29#ibcon#wrote, iclass 11, count 0 2006.246.07:47:38.29#ibcon#about to read 3, iclass 11, count 0 2006.246.07:47:38.32#ibcon#read 3, iclass 11, count 0 2006.246.07:47:38.32#ibcon#about to read 4, iclass 11, count 0 2006.246.07:47:38.32#ibcon#read 4, iclass 11, count 0 2006.246.07:47:38.32#ibcon#about to read 5, iclass 11, count 0 2006.246.07:47:38.32#ibcon#read 5, iclass 11, count 0 2006.246.07:47:38.32#ibcon#about to read 6, iclass 11, count 0 2006.246.07:47:38.32#ibcon#read 6, iclass 11, count 0 2006.246.07:47:38.32#ibcon#end of sib2, iclass 11, count 0 2006.246.07:47:38.32#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:47:38.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:47:38.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:47:38.32#ibcon#*before write, iclass 11, count 0 2006.246.07:47:38.32#ibcon#enter sib2, iclass 11, count 0 2006.246.07:47:38.32#ibcon#flushed, iclass 11, count 0 2006.246.07:47:38.32#ibcon#about to write, iclass 11, count 0 2006.246.07:47:38.32#ibcon#wrote, iclass 11, count 0 2006.246.07:47:38.32#ibcon#about to read 3, iclass 11, count 0 2006.246.07:47:38.36#ibcon#read 3, iclass 11, count 0 2006.246.07:47:38.36#ibcon#about to read 4, iclass 11, count 0 2006.246.07:47:38.36#ibcon#read 4, iclass 11, count 0 2006.246.07:47:38.36#ibcon#about to read 5, iclass 11, count 0 2006.246.07:47:38.36#ibcon#read 5, iclass 11, count 0 2006.246.07:47:38.36#ibcon#about to read 6, iclass 11, count 0 2006.246.07:47:38.36#ibcon#read 6, iclass 11, count 0 2006.246.07:47:38.36#ibcon#end of sib2, iclass 11, count 0 2006.246.07:47:38.36#ibcon#*after write, iclass 11, count 0 2006.246.07:47:38.36#ibcon#*before return 0, iclass 11, count 0 2006.246.07:47:38.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:38.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:38.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:47:38.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:47:38.36$vc4f8/va=2,7 2006.246.07:47:38.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:47:38.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:47:38.36#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:38.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:38.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:38.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:38.41#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:47:38.41#ibcon#first serial, iclass 13, count 2 2006.246.07:47:38.41#ibcon#enter sib2, iclass 13, count 2 2006.246.07:47:38.41#ibcon#flushed, iclass 13, count 2 2006.246.07:47:38.41#ibcon#about to write, iclass 13, count 2 2006.246.07:47:38.41#ibcon#wrote, iclass 13, count 2 2006.246.07:47:38.41#ibcon#about to read 3, iclass 13, count 2 2006.246.07:47:38.43#ibcon#read 3, iclass 13, count 2 2006.246.07:47:38.43#ibcon#about to read 4, iclass 13, count 2 2006.246.07:47:38.43#ibcon#read 4, iclass 13, count 2 2006.246.07:47:38.43#ibcon#about to read 5, iclass 13, count 2 2006.246.07:47:38.43#ibcon#read 5, iclass 13, count 2 2006.246.07:47:38.43#ibcon#about to read 6, iclass 13, count 2 2006.246.07:47:38.43#ibcon#read 6, iclass 13, count 2 2006.246.07:47:38.43#ibcon#end of sib2, iclass 13, count 2 2006.246.07:47:38.43#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:47:38.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:47:38.43#ibcon#[25=AT02-07\r\n] 2006.246.07:47:38.43#ibcon#*before write, iclass 13, count 2 2006.246.07:47:38.43#ibcon#enter sib2, iclass 13, count 2 2006.246.07:47:38.43#ibcon#flushed, iclass 13, count 2 2006.246.07:47:38.43#ibcon#about to write, iclass 13, count 2 2006.246.07:47:38.43#ibcon#wrote, iclass 13, count 2 2006.246.07:47:38.43#ibcon#about to read 3, iclass 13, count 2 2006.246.07:47:38.46#ibcon#read 3, iclass 13, count 2 2006.246.07:47:38.46#ibcon#about to read 4, iclass 13, count 2 2006.246.07:47:38.46#ibcon#read 4, iclass 13, count 2 2006.246.07:47:38.46#ibcon#about to read 5, iclass 13, count 2 2006.246.07:47:38.46#ibcon#read 5, iclass 13, count 2 2006.246.07:47:38.46#ibcon#about to read 6, iclass 13, count 2 2006.246.07:47:38.46#ibcon#read 6, iclass 13, count 2 2006.246.07:47:38.46#ibcon#end of sib2, iclass 13, count 2 2006.246.07:47:38.46#ibcon#*after write, iclass 13, count 2 2006.246.07:47:38.46#ibcon#*before return 0, iclass 13, count 2 2006.246.07:47:38.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:38.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:38.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:47:38.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:38.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:38.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:38.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:38.58#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:47:38.58#ibcon#first serial, iclass 13, count 0 2006.246.07:47:38.58#ibcon#enter sib2, iclass 13, count 0 2006.246.07:47:38.58#ibcon#flushed, iclass 13, count 0 2006.246.07:47:38.58#ibcon#about to write, iclass 13, count 0 2006.246.07:47:38.58#ibcon#wrote, iclass 13, count 0 2006.246.07:47:38.58#ibcon#about to read 3, iclass 13, count 0 2006.246.07:47:38.60#ibcon#read 3, iclass 13, count 0 2006.246.07:47:38.60#ibcon#about to read 4, iclass 13, count 0 2006.246.07:47:38.60#ibcon#read 4, iclass 13, count 0 2006.246.07:47:38.60#ibcon#about to read 5, iclass 13, count 0 2006.246.07:47:38.60#ibcon#read 5, iclass 13, count 0 2006.246.07:47:38.60#ibcon#about to read 6, iclass 13, count 0 2006.246.07:47:38.60#ibcon#read 6, iclass 13, count 0 2006.246.07:47:38.60#ibcon#end of sib2, iclass 13, count 0 2006.246.07:47:38.60#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:47:38.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:47:38.60#ibcon#[25=USB\r\n] 2006.246.07:47:38.60#ibcon#*before write, iclass 13, count 0 2006.246.07:47:38.60#ibcon#enter sib2, iclass 13, count 0 2006.246.07:47:38.60#ibcon#flushed, iclass 13, count 0 2006.246.07:47:38.60#ibcon#about to write, iclass 13, count 0 2006.246.07:47:38.60#ibcon#wrote, iclass 13, count 0 2006.246.07:47:38.60#ibcon#about to read 3, iclass 13, count 0 2006.246.07:47:38.63#ibcon#read 3, iclass 13, count 0 2006.246.07:47:38.63#ibcon#about to read 4, iclass 13, count 0 2006.246.07:47:38.63#ibcon#read 4, iclass 13, count 0 2006.246.07:47:38.63#ibcon#about to read 5, iclass 13, count 0 2006.246.07:47:38.63#ibcon#read 5, iclass 13, count 0 2006.246.07:47:38.63#ibcon#about to read 6, iclass 13, count 0 2006.246.07:47:38.63#ibcon#read 6, iclass 13, count 0 2006.246.07:47:38.63#ibcon#end of sib2, iclass 13, count 0 2006.246.07:47:38.63#ibcon#*after write, iclass 13, count 0 2006.246.07:47:38.63#ibcon#*before return 0, iclass 13, count 0 2006.246.07:47:38.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:38.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:38.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:47:38.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:47:38.63$vc4f8/valo=3,672.99 2006.246.07:47:38.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:47:38.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:47:38.63#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:38.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:38.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:38.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:38.63#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:47:38.63#ibcon#first serial, iclass 15, count 0 2006.246.07:47:38.63#ibcon#enter sib2, iclass 15, count 0 2006.246.07:47:38.63#ibcon#flushed, iclass 15, count 0 2006.246.07:47:38.63#ibcon#about to write, iclass 15, count 0 2006.246.07:47:38.63#ibcon#wrote, iclass 15, count 0 2006.246.07:47:38.63#ibcon#about to read 3, iclass 15, count 0 2006.246.07:47:38.66#ibcon#read 3, iclass 15, count 0 2006.246.07:47:38.66#ibcon#about to read 4, iclass 15, count 0 2006.246.07:47:38.66#ibcon#read 4, iclass 15, count 0 2006.246.07:47:38.66#ibcon#about to read 5, iclass 15, count 0 2006.246.07:47:38.66#ibcon#read 5, iclass 15, count 0 2006.246.07:47:38.66#ibcon#about to read 6, iclass 15, count 0 2006.246.07:47:38.66#ibcon#read 6, iclass 15, count 0 2006.246.07:47:38.66#ibcon#end of sib2, iclass 15, count 0 2006.246.07:47:38.66#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:47:38.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:47:38.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:47:38.66#ibcon#*before write, iclass 15, count 0 2006.246.07:47:38.66#ibcon#enter sib2, iclass 15, count 0 2006.246.07:47:38.66#ibcon#flushed, iclass 15, count 0 2006.246.07:47:38.66#ibcon#about to write, iclass 15, count 0 2006.246.07:47:38.66#ibcon#wrote, iclass 15, count 0 2006.246.07:47:38.66#ibcon#about to read 3, iclass 15, count 0 2006.246.07:47:38.70#ibcon#read 3, iclass 15, count 0 2006.246.07:47:38.70#ibcon#about to read 4, iclass 15, count 0 2006.246.07:47:38.70#ibcon#read 4, iclass 15, count 0 2006.246.07:47:38.70#ibcon#about to read 5, iclass 15, count 0 2006.246.07:47:38.70#ibcon#read 5, iclass 15, count 0 2006.246.07:47:38.70#ibcon#about to read 6, iclass 15, count 0 2006.246.07:47:38.70#ibcon#read 6, iclass 15, count 0 2006.246.07:47:38.70#ibcon#end of sib2, iclass 15, count 0 2006.246.07:47:38.70#ibcon#*after write, iclass 15, count 0 2006.246.07:47:38.70#ibcon#*before return 0, iclass 15, count 0 2006.246.07:47:38.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:38.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:38.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:47:38.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:47:38.70$vc4f8/va=3,6 2006.246.07:47:38.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.07:47:38.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.07:47:38.70#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:38.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:38.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:38.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:38.75#ibcon#enter wrdev, iclass 17, count 2 2006.246.07:47:38.75#ibcon#first serial, iclass 17, count 2 2006.246.07:47:38.75#ibcon#enter sib2, iclass 17, count 2 2006.246.07:47:38.75#ibcon#flushed, iclass 17, count 2 2006.246.07:47:38.75#ibcon#about to write, iclass 17, count 2 2006.246.07:47:38.75#ibcon#wrote, iclass 17, count 2 2006.246.07:47:38.75#ibcon#about to read 3, iclass 17, count 2 2006.246.07:47:38.77#ibcon#read 3, iclass 17, count 2 2006.246.07:47:38.77#ibcon#about to read 4, iclass 17, count 2 2006.246.07:47:38.77#ibcon#read 4, iclass 17, count 2 2006.246.07:47:38.77#ibcon#about to read 5, iclass 17, count 2 2006.246.07:47:38.77#ibcon#read 5, iclass 17, count 2 2006.246.07:47:38.77#ibcon#about to read 6, iclass 17, count 2 2006.246.07:47:38.77#ibcon#read 6, iclass 17, count 2 2006.246.07:47:38.77#ibcon#end of sib2, iclass 17, count 2 2006.246.07:47:38.77#ibcon#*mode == 0, iclass 17, count 2 2006.246.07:47:38.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.07:47:38.77#ibcon#[25=AT03-06\r\n] 2006.246.07:47:38.77#ibcon#*before write, iclass 17, count 2 2006.246.07:47:38.77#ibcon#enter sib2, iclass 17, count 2 2006.246.07:47:38.77#ibcon#flushed, iclass 17, count 2 2006.246.07:47:38.77#ibcon#about to write, iclass 17, count 2 2006.246.07:47:38.77#ibcon#wrote, iclass 17, count 2 2006.246.07:47:38.77#ibcon#about to read 3, iclass 17, count 2 2006.246.07:47:38.80#ibcon#read 3, iclass 17, count 2 2006.246.07:47:38.80#ibcon#about to read 4, iclass 17, count 2 2006.246.07:47:38.80#ibcon#read 4, iclass 17, count 2 2006.246.07:47:38.80#ibcon#about to read 5, iclass 17, count 2 2006.246.07:47:38.80#ibcon#read 5, iclass 17, count 2 2006.246.07:47:38.80#ibcon#about to read 6, iclass 17, count 2 2006.246.07:47:38.80#ibcon#read 6, iclass 17, count 2 2006.246.07:47:38.80#ibcon#end of sib2, iclass 17, count 2 2006.246.07:47:38.80#ibcon#*after write, iclass 17, count 2 2006.246.07:47:38.80#ibcon#*before return 0, iclass 17, count 2 2006.246.07:47:38.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:38.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:38.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.07:47:38.80#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:38.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:38.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:38.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:38.92#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:47:38.92#ibcon#first serial, iclass 17, count 0 2006.246.07:47:38.92#ibcon#enter sib2, iclass 17, count 0 2006.246.07:47:38.92#ibcon#flushed, iclass 17, count 0 2006.246.07:47:38.92#ibcon#about to write, iclass 17, count 0 2006.246.07:47:38.92#ibcon#wrote, iclass 17, count 0 2006.246.07:47:38.92#ibcon#about to read 3, iclass 17, count 0 2006.246.07:47:38.94#ibcon#read 3, iclass 17, count 0 2006.246.07:47:38.94#ibcon#about to read 4, iclass 17, count 0 2006.246.07:47:38.94#ibcon#read 4, iclass 17, count 0 2006.246.07:47:38.94#ibcon#about to read 5, iclass 17, count 0 2006.246.07:47:38.94#ibcon#read 5, iclass 17, count 0 2006.246.07:47:38.94#ibcon#about to read 6, iclass 17, count 0 2006.246.07:47:38.94#ibcon#read 6, iclass 17, count 0 2006.246.07:47:38.94#ibcon#end of sib2, iclass 17, count 0 2006.246.07:47:38.94#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:47:38.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:47:38.94#ibcon#[25=USB\r\n] 2006.246.07:47:38.94#ibcon#*before write, iclass 17, count 0 2006.246.07:47:38.94#ibcon#enter sib2, iclass 17, count 0 2006.246.07:47:38.94#ibcon#flushed, iclass 17, count 0 2006.246.07:47:38.94#ibcon#about to write, iclass 17, count 0 2006.246.07:47:38.94#ibcon#wrote, iclass 17, count 0 2006.246.07:47:38.94#ibcon#about to read 3, iclass 17, count 0 2006.246.07:47:38.97#ibcon#read 3, iclass 17, count 0 2006.246.07:47:38.97#ibcon#about to read 4, iclass 17, count 0 2006.246.07:47:38.97#ibcon#read 4, iclass 17, count 0 2006.246.07:47:38.97#ibcon#about to read 5, iclass 17, count 0 2006.246.07:47:38.97#ibcon#read 5, iclass 17, count 0 2006.246.07:47:38.97#ibcon#about to read 6, iclass 17, count 0 2006.246.07:47:38.97#ibcon#read 6, iclass 17, count 0 2006.246.07:47:38.97#ibcon#end of sib2, iclass 17, count 0 2006.246.07:47:38.97#ibcon#*after write, iclass 17, count 0 2006.246.07:47:38.97#ibcon#*before return 0, iclass 17, count 0 2006.246.07:47:38.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:38.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:38.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:47:38.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:47:38.97$vc4f8/valo=4,832.99 2006.246.07:47:38.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:47:38.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:47:38.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:38.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:38.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:38.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:38.97#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:47:38.97#ibcon#first serial, iclass 19, count 0 2006.246.07:47:38.97#ibcon#enter sib2, iclass 19, count 0 2006.246.07:47:38.97#ibcon#flushed, iclass 19, count 0 2006.246.07:47:38.97#ibcon#about to write, iclass 19, count 0 2006.246.07:47:38.97#ibcon#wrote, iclass 19, count 0 2006.246.07:47:38.97#ibcon#about to read 3, iclass 19, count 0 2006.246.07:47:38.99#ibcon#read 3, iclass 19, count 0 2006.246.07:47:38.99#ibcon#about to read 4, iclass 19, count 0 2006.246.07:47:38.99#ibcon#read 4, iclass 19, count 0 2006.246.07:47:38.99#ibcon#about to read 5, iclass 19, count 0 2006.246.07:47:38.99#ibcon#read 5, iclass 19, count 0 2006.246.07:47:38.99#ibcon#about to read 6, iclass 19, count 0 2006.246.07:47:38.99#ibcon#read 6, iclass 19, count 0 2006.246.07:47:38.99#ibcon#end of sib2, iclass 19, count 0 2006.246.07:47:38.99#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:47:38.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:47:38.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:47:38.99#ibcon#*before write, iclass 19, count 0 2006.246.07:47:38.99#ibcon#enter sib2, iclass 19, count 0 2006.246.07:47:38.99#ibcon#flushed, iclass 19, count 0 2006.246.07:47:38.99#ibcon#about to write, iclass 19, count 0 2006.246.07:47:38.99#ibcon#wrote, iclass 19, count 0 2006.246.07:47:38.99#ibcon#about to read 3, iclass 19, count 0 2006.246.07:47:39.03#ibcon#read 3, iclass 19, count 0 2006.246.07:47:39.03#ibcon#about to read 4, iclass 19, count 0 2006.246.07:47:39.03#ibcon#read 4, iclass 19, count 0 2006.246.07:47:39.03#ibcon#about to read 5, iclass 19, count 0 2006.246.07:47:39.03#ibcon#read 5, iclass 19, count 0 2006.246.07:47:39.03#ibcon#about to read 6, iclass 19, count 0 2006.246.07:47:39.03#ibcon#read 6, iclass 19, count 0 2006.246.07:47:39.03#ibcon#end of sib2, iclass 19, count 0 2006.246.07:47:39.03#ibcon#*after write, iclass 19, count 0 2006.246.07:47:39.03#ibcon#*before return 0, iclass 19, count 0 2006.246.07:47:39.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:39.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:39.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:47:39.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:47:39.03$vc4f8/va=4,7 2006.246.07:47:39.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:47:39.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:47:39.03#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:39.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:39.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:39.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:39.09#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:47:39.09#ibcon#first serial, iclass 21, count 2 2006.246.07:47:39.09#ibcon#enter sib2, iclass 21, count 2 2006.246.07:47:39.09#ibcon#flushed, iclass 21, count 2 2006.246.07:47:39.09#ibcon#about to write, iclass 21, count 2 2006.246.07:47:39.09#ibcon#wrote, iclass 21, count 2 2006.246.07:47:39.09#ibcon#about to read 3, iclass 21, count 2 2006.246.07:47:39.11#ibcon#read 3, iclass 21, count 2 2006.246.07:47:39.11#ibcon#about to read 4, iclass 21, count 2 2006.246.07:47:39.11#ibcon#read 4, iclass 21, count 2 2006.246.07:47:39.11#ibcon#about to read 5, iclass 21, count 2 2006.246.07:47:39.11#ibcon#read 5, iclass 21, count 2 2006.246.07:47:39.11#ibcon#about to read 6, iclass 21, count 2 2006.246.07:47:39.11#ibcon#read 6, iclass 21, count 2 2006.246.07:47:39.11#ibcon#end of sib2, iclass 21, count 2 2006.246.07:47:39.11#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:47:39.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:47:39.11#ibcon#[25=AT04-07\r\n] 2006.246.07:47:39.11#ibcon#*before write, iclass 21, count 2 2006.246.07:47:39.11#ibcon#enter sib2, iclass 21, count 2 2006.246.07:47:39.11#ibcon#flushed, iclass 21, count 2 2006.246.07:47:39.11#ibcon#about to write, iclass 21, count 2 2006.246.07:47:39.11#ibcon#wrote, iclass 21, count 2 2006.246.07:47:39.11#ibcon#about to read 3, iclass 21, count 2 2006.246.07:47:39.14#ibcon#read 3, iclass 21, count 2 2006.246.07:47:39.14#ibcon#about to read 4, iclass 21, count 2 2006.246.07:47:39.14#ibcon#read 4, iclass 21, count 2 2006.246.07:47:39.14#ibcon#about to read 5, iclass 21, count 2 2006.246.07:47:39.14#ibcon#read 5, iclass 21, count 2 2006.246.07:47:39.14#ibcon#about to read 6, iclass 21, count 2 2006.246.07:47:39.14#ibcon#read 6, iclass 21, count 2 2006.246.07:47:39.14#ibcon#end of sib2, iclass 21, count 2 2006.246.07:47:39.14#ibcon#*after write, iclass 21, count 2 2006.246.07:47:39.14#ibcon#*before return 0, iclass 21, count 2 2006.246.07:47:39.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:39.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:39.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:47:39.14#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:39.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:39.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:39.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:39.26#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:47:39.26#ibcon#first serial, iclass 21, count 0 2006.246.07:47:39.26#ibcon#enter sib2, iclass 21, count 0 2006.246.07:47:39.26#ibcon#flushed, iclass 21, count 0 2006.246.07:47:39.26#ibcon#about to write, iclass 21, count 0 2006.246.07:47:39.26#ibcon#wrote, iclass 21, count 0 2006.246.07:47:39.26#ibcon#about to read 3, iclass 21, count 0 2006.246.07:47:39.28#ibcon#read 3, iclass 21, count 0 2006.246.07:47:39.28#ibcon#about to read 4, iclass 21, count 0 2006.246.07:47:39.28#ibcon#read 4, iclass 21, count 0 2006.246.07:47:39.28#ibcon#about to read 5, iclass 21, count 0 2006.246.07:47:39.28#ibcon#read 5, iclass 21, count 0 2006.246.07:47:39.28#ibcon#about to read 6, iclass 21, count 0 2006.246.07:47:39.28#ibcon#read 6, iclass 21, count 0 2006.246.07:47:39.28#ibcon#end of sib2, iclass 21, count 0 2006.246.07:47:39.28#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:47:39.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:47:39.28#ibcon#[25=USB\r\n] 2006.246.07:47:39.28#ibcon#*before write, iclass 21, count 0 2006.246.07:47:39.28#ibcon#enter sib2, iclass 21, count 0 2006.246.07:47:39.28#ibcon#flushed, iclass 21, count 0 2006.246.07:47:39.28#ibcon#about to write, iclass 21, count 0 2006.246.07:47:39.28#ibcon#wrote, iclass 21, count 0 2006.246.07:47:39.28#ibcon#about to read 3, iclass 21, count 0 2006.246.07:47:39.31#ibcon#read 3, iclass 21, count 0 2006.246.07:47:39.31#ibcon#about to read 4, iclass 21, count 0 2006.246.07:47:39.31#ibcon#read 4, iclass 21, count 0 2006.246.07:47:39.31#ibcon#about to read 5, iclass 21, count 0 2006.246.07:47:39.31#ibcon#read 5, iclass 21, count 0 2006.246.07:47:39.31#ibcon#about to read 6, iclass 21, count 0 2006.246.07:47:39.31#ibcon#read 6, iclass 21, count 0 2006.246.07:47:39.31#ibcon#end of sib2, iclass 21, count 0 2006.246.07:47:39.31#ibcon#*after write, iclass 21, count 0 2006.246.07:47:39.31#ibcon#*before return 0, iclass 21, count 0 2006.246.07:47:39.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:39.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:39.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:47:39.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:47:39.31$vc4f8/valo=5,652.99 2006.246.07:47:39.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:47:39.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:47:39.31#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:39.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:39.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:39.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:39.31#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:47:39.31#ibcon#first serial, iclass 23, count 0 2006.246.07:47:39.31#ibcon#enter sib2, iclass 23, count 0 2006.246.07:47:39.31#ibcon#flushed, iclass 23, count 0 2006.246.07:47:39.31#ibcon#about to write, iclass 23, count 0 2006.246.07:47:39.31#ibcon#wrote, iclass 23, count 0 2006.246.07:47:39.31#ibcon#about to read 3, iclass 23, count 0 2006.246.07:47:39.33#ibcon#read 3, iclass 23, count 0 2006.246.07:47:39.33#ibcon#about to read 4, iclass 23, count 0 2006.246.07:47:39.33#ibcon#read 4, iclass 23, count 0 2006.246.07:47:39.33#ibcon#about to read 5, iclass 23, count 0 2006.246.07:47:39.33#ibcon#read 5, iclass 23, count 0 2006.246.07:47:39.33#ibcon#about to read 6, iclass 23, count 0 2006.246.07:47:39.33#ibcon#read 6, iclass 23, count 0 2006.246.07:47:39.33#ibcon#end of sib2, iclass 23, count 0 2006.246.07:47:39.33#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:47:39.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:47:39.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:47:39.33#ibcon#*before write, iclass 23, count 0 2006.246.07:47:39.33#ibcon#enter sib2, iclass 23, count 0 2006.246.07:47:39.33#ibcon#flushed, iclass 23, count 0 2006.246.07:47:39.33#ibcon#about to write, iclass 23, count 0 2006.246.07:47:39.33#ibcon#wrote, iclass 23, count 0 2006.246.07:47:39.33#ibcon#about to read 3, iclass 23, count 0 2006.246.07:47:39.37#ibcon#read 3, iclass 23, count 0 2006.246.07:47:39.37#ibcon#about to read 4, iclass 23, count 0 2006.246.07:47:39.37#ibcon#read 4, iclass 23, count 0 2006.246.07:47:39.37#ibcon#about to read 5, iclass 23, count 0 2006.246.07:47:39.37#ibcon#read 5, iclass 23, count 0 2006.246.07:47:39.37#ibcon#about to read 6, iclass 23, count 0 2006.246.07:47:39.37#ibcon#read 6, iclass 23, count 0 2006.246.07:47:39.37#ibcon#end of sib2, iclass 23, count 0 2006.246.07:47:39.37#ibcon#*after write, iclass 23, count 0 2006.246.07:47:39.37#ibcon#*before return 0, iclass 23, count 0 2006.246.07:47:39.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:39.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:39.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:47:39.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:47:39.37$vc4f8/va=5,7 2006.246.07:47:39.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:47:39.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:47:39.37#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:39.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:39.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:39.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:39.43#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:47:39.43#ibcon#first serial, iclass 25, count 2 2006.246.07:47:39.43#ibcon#enter sib2, iclass 25, count 2 2006.246.07:47:39.43#ibcon#flushed, iclass 25, count 2 2006.246.07:47:39.43#ibcon#about to write, iclass 25, count 2 2006.246.07:47:39.43#ibcon#wrote, iclass 25, count 2 2006.246.07:47:39.43#ibcon#about to read 3, iclass 25, count 2 2006.246.07:47:39.45#ibcon#read 3, iclass 25, count 2 2006.246.07:47:39.45#ibcon#about to read 4, iclass 25, count 2 2006.246.07:47:39.45#ibcon#read 4, iclass 25, count 2 2006.246.07:47:39.45#ibcon#about to read 5, iclass 25, count 2 2006.246.07:47:39.45#ibcon#read 5, iclass 25, count 2 2006.246.07:47:39.45#ibcon#about to read 6, iclass 25, count 2 2006.246.07:47:39.45#ibcon#read 6, iclass 25, count 2 2006.246.07:47:39.45#ibcon#end of sib2, iclass 25, count 2 2006.246.07:47:39.45#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:47:39.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:47:39.45#ibcon#[25=AT05-07\r\n] 2006.246.07:47:39.45#ibcon#*before write, iclass 25, count 2 2006.246.07:47:39.45#ibcon#enter sib2, iclass 25, count 2 2006.246.07:47:39.45#ibcon#flushed, iclass 25, count 2 2006.246.07:47:39.45#ibcon#about to write, iclass 25, count 2 2006.246.07:47:39.45#ibcon#wrote, iclass 25, count 2 2006.246.07:47:39.45#ibcon#about to read 3, iclass 25, count 2 2006.246.07:47:39.48#ibcon#read 3, iclass 25, count 2 2006.246.07:47:39.48#ibcon#about to read 4, iclass 25, count 2 2006.246.07:47:39.48#ibcon#read 4, iclass 25, count 2 2006.246.07:47:39.48#ibcon#about to read 5, iclass 25, count 2 2006.246.07:47:39.48#ibcon#read 5, iclass 25, count 2 2006.246.07:47:39.48#ibcon#about to read 6, iclass 25, count 2 2006.246.07:47:39.48#ibcon#read 6, iclass 25, count 2 2006.246.07:47:39.48#ibcon#end of sib2, iclass 25, count 2 2006.246.07:47:39.48#ibcon#*after write, iclass 25, count 2 2006.246.07:47:39.48#ibcon#*before return 0, iclass 25, count 2 2006.246.07:47:39.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:39.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:39.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:47:39.48#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:39.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:39.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:39.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:39.60#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:47:39.60#ibcon#first serial, iclass 25, count 0 2006.246.07:47:39.60#ibcon#enter sib2, iclass 25, count 0 2006.246.07:47:39.60#ibcon#flushed, iclass 25, count 0 2006.246.07:47:39.60#ibcon#about to write, iclass 25, count 0 2006.246.07:47:39.60#ibcon#wrote, iclass 25, count 0 2006.246.07:47:39.60#ibcon#about to read 3, iclass 25, count 0 2006.246.07:47:39.62#ibcon#read 3, iclass 25, count 0 2006.246.07:47:39.62#ibcon#about to read 4, iclass 25, count 0 2006.246.07:47:39.62#ibcon#read 4, iclass 25, count 0 2006.246.07:47:39.62#ibcon#about to read 5, iclass 25, count 0 2006.246.07:47:39.62#ibcon#read 5, iclass 25, count 0 2006.246.07:47:39.62#ibcon#about to read 6, iclass 25, count 0 2006.246.07:47:39.62#ibcon#read 6, iclass 25, count 0 2006.246.07:47:39.62#ibcon#end of sib2, iclass 25, count 0 2006.246.07:47:39.62#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:47:39.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:47:39.62#ibcon#[25=USB\r\n] 2006.246.07:47:39.62#ibcon#*before write, iclass 25, count 0 2006.246.07:47:39.62#ibcon#enter sib2, iclass 25, count 0 2006.246.07:47:39.62#ibcon#flushed, iclass 25, count 0 2006.246.07:47:39.62#ibcon#about to write, iclass 25, count 0 2006.246.07:47:39.62#ibcon#wrote, iclass 25, count 0 2006.246.07:47:39.62#ibcon#about to read 3, iclass 25, count 0 2006.246.07:47:39.65#ibcon#read 3, iclass 25, count 0 2006.246.07:47:39.65#ibcon#about to read 4, iclass 25, count 0 2006.246.07:47:39.65#ibcon#read 4, iclass 25, count 0 2006.246.07:47:39.65#ibcon#about to read 5, iclass 25, count 0 2006.246.07:47:39.65#ibcon#read 5, iclass 25, count 0 2006.246.07:47:39.65#ibcon#about to read 6, iclass 25, count 0 2006.246.07:47:39.65#ibcon#read 6, iclass 25, count 0 2006.246.07:47:39.65#ibcon#end of sib2, iclass 25, count 0 2006.246.07:47:39.65#ibcon#*after write, iclass 25, count 0 2006.246.07:47:39.65#ibcon#*before return 0, iclass 25, count 0 2006.246.07:47:39.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:39.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:39.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:47:39.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:47:39.65$vc4f8/valo=6,772.99 2006.246.07:47:39.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:47:39.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:47:39.65#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:39.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:39.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:39.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:39.65#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:47:39.65#ibcon#first serial, iclass 27, count 0 2006.246.07:47:39.65#ibcon#enter sib2, iclass 27, count 0 2006.246.07:47:39.65#ibcon#flushed, iclass 27, count 0 2006.246.07:47:39.65#ibcon#about to write, iclass 27, count 0 2006.246.07:47:39.65#ibcon#wrote, iclass 27, count 0 2006.246.07:47:39.65#ibcon#about to read 3, iclass 27, count 0 2006.246.07:47:39.68#ibcon#read 3, iclass 27, count 0 2006.246.07:47:39.68#ibcon#about to read 4, iclass 27, count 0 2006.246.07:47:39.68#ibcon#read 4, iclass 27, count 0 2006.246.07:47:39.68#ibcon#about to read 5, iclass 27, count 0 2006.246.07:47:39.68#ibcon#read 5, iclass 27, count 0 2006.246.07:47:39.68#ibcon#about to read 6, iclass 27, count 0 2006.246.07:47:39.68#ibcon#read 6, iclass 27, count 0 2006.246.07:47:39.68#ibcon#end of sib2, iclass 27, count 0 2006.246.07:47:39.68#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:47:39.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:47:39.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:47:39.68#ibcon#*before write, iclass 27, count 0 2006.246.07:47:39.68#ibcon#enter sib2, iclass 27, count 0 2006.246.07:47:39.68#ibcon#flushed, iclass 27, count 0 2006.246.07:47:39.68#ibcon#about to write, iclass 27, count 0 2006.246.07:47:39.68#ibcon#wrote, iclass 27, count 0 2006.246.07:47:39.68#ibcon#about to read 3, iclass 27, count 0 2006.246.07:47:39.72#ibcon#read 3, iclass 27, count 0 2006.246.07:47:39.72#ibcon#about to read 4, iclass 27, count 0 2006.246.07:47:39.72#ibcon#read 4, iclass 27, count 0 2006.246.07:47:39.72#ibcon#about to read 5, iclass 27, count 0 2006.246.07:47:39.72#ibcon#read 5, iclass 27, count 0 2006.246.07:47:39.72#ibcon#about to read 6, iclass 27, count 0 2006.246.07:47:39.72#ibcon#read 6, iclass 27, count 0 2006.246.07:47:39.72#ibcon#end of sib2, iclass 27, count 0 2006.246.07:47:39.72#ibcon#*after write, iclass 27, count 0 2006.246.07:47:39.72#ibcon#*before return 0, iclass 27, count 0 2006.246.07:47:39.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:39.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:39.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:47:39.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:47:39.72$vc4f8/va=6,7 2006.246.07:47:39.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.07:47:39.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.07:47:39.72#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:39.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:47:39.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:47:39.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:47:39.77#ibcon#enter wrdev, iclass 29, count 2 2006.246.07:47:39.77#ibcon#first serial, iclass 29, count 2 2006.246.07:47:39.77#ibcon#enter sib2, iclass 29, count 2 2006.246.07:47:39.77#ibcon#flushed, iclass 29, count 2 2006.246.07:47:39.77#ibcon#about to write, iclass 29, count 2 2006.246.07:47:39.77#ibcon#wrote, iclass 29, count 2 2006.246.07:47:39.77#ibcon#about to read 3, iclass 29, count 2 2006.246.07:47:39.79#ibcon#read 3, iclass 29, count 2 2006.246.07:47:39.79#ibcon#about to read 4, iclass 29, count 2 2006.246.07:47:39.79#ibcon#read 4, iclass 29, count 2 2006.246.07:47:39.79#ibcon#about to read 5, iclass 29, count 2 2006.246.07:47:39.79#ibcon#read 5, iclass 29, count 2 2006.246.07:47:39.79#ibcon#about to read 6, iclass 29, count 2 2006.246.07:47:39.79#ibcon#read 6, iclass 29, count 2 2006.246.07:47:39.79#ibcon#end of sib2, iclass 29, count 2 2006.246.07:47:39.79#ibcon#*mode == 0, iclass 29, count 2 2006.246.07:47:39.79#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.07:47:39.79#ibcon#[25=AT06-07\r\n] 2006.246.07:47:39.79#ibcon#*before write, iclass 29, count 2 2006.246.07:47:39.79#ibcon#enter sib2, iclass 29, count 2 2006.246.07:47:39.79#ibcon#flushed, iclass 29, count 2 2006.246.07:47:39.79#ibcon#about to write, iclass 29, count 2 2006.246.07:47:39.79#ibcon#wrote, iclass 29, count 2 2006.246.07:47:39.79#ibcon#about to read 3, iclass 29, count 2 2006.246.07:47:39.82#ibcon#read 3, iclass 29, count 2 2006.246.07:47:39.82#ibcon#about to read 4, iclass 29, count 2 2006.246.07:47:39.82#ibcon#read 4, iclass 29, count 2 2006.246.07:47:39.82#ibcon#about to read 5, iclass 29, count 2 2006.246.07:47:39.82#ibcon#read 5, iclass 29, count 2 2006.246.07:47:39.82#ibcon#about to read 6, iclass 29, count 2 2006.246.07:47:39.82#ibcon#read 6, iclass 29, count 2 2006.246.07:47:39.82#ibcon#end of sib2, iclass 29, count 2 2006.246.07:47:39.82#ibcon#*after write, iclass 29, count 2 2006.246.07:47:39.82#ibcon#*before return 0, iclass 29, count 2 2006.246.07:47:39.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:47:39.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:47:39.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.07:47:39.82#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:39.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:47:39.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:47:39.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:47:39.94#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:47:39.94#ibcon#first serial, iclass 29, count 0 2006.246.07:47:39.94#ibcon#enter sib2, iclass 29, count 0 2006.246.07:47:39.94#ibcon#flushed, iclass 29, count 0 2006.246.07:47:39.94#ibcon#about to write, iclass 29, count 0 2006.246.07:47:39.94#ibcon#wrote, iclass 29, count 0 2006.246.07:47:39.94#ibcon#about to read 3, iclass 29, count 0 2006.246.07:47:39.96#ibcon#read 3, iclass 29, count 0 2006.246.07:47:39.96#ibcon#about to read 4, iclass 29, count 0 2006.246.07:47:39.96#ibcon#read 4, iclass 29, count 0 2006.246.07:47:39.96#ibcon#about to read 5, iclass 29, count 0 2006.246.07:47:39.96#ibcon#read 5, iclass 29, count 0 2006.246.07:47:39.96#ibcon#about to read 6, iclass 29, count 0 2006.246.07:47:39.96#ibcon#read 6, iclass 29, count 0 2006.246.07:47:39.96#ibcon#end of sib2, iclass 29, count 0 2006.246.07:47:39.96#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:47:39.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:47:39.96#ibcon#[25=USB\r\n] 2006.246.07:47:39.96#ibcon#*before write, iclass 29, count 0 2006.246.07:47:39.96#ibcon#enter sib2, iclass 29, count 0 2006.246.07:47:39.96#ibcon#flushed, iclass 29, count 0 2006.246.07:47:39.96#ibcon#about to write, iclass 29, count 0 2006.246.07:47:39.96#ibcon#wrote, iclass 29, count 0 2006.246.07:47:39.96#ibcon#about to read 3, iclass 29, count 0 2006.246.07:47:39.99#ibcon#read 3, iclass 29, count 0 2006.246.07:47:39.99#ibcon#about to read 4, iclass 29, count 0 2006.246.07:47:39.99#ibcon#read 4, iclass 29, count 0 2006.246.07:47:39.99#ibcon#about to read 5, iclass 29, count 0 2006.246.07:47:39.99#ibcon#read 5, iclass 29, count 0 2006.246.07:47:39.99#ibcon#about to read 6, iclass 29, count 0 2006.246.07:47:39.99#ibcon#read 6, iclass 29, count 0 2006.246.07:47:39.99#ibcon#end of sib2, iclass 29, count 0 2006.246.07:47:39.99#ibcon#*after write, iclass 29, count 0 2006.246.07:47:39.99#ibcon#*before return 0, iclass 29, count 0 2006.246.07:47:39.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:47:39.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:47:39.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:47:39.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:47:39.99$vc4f8/valo=7,832.99 2006.246.07:47:39.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.07:47:39.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.07:47:39.99#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:39.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:47:39.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:47:39.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:47:39.99#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:47:39.99#ibcon#first serial, iclass 31, count 0 2006.246.07:47:39.99#ibcon#enter sib2, iclass 31, count 0 2006.246.07:47:39.99#ibcon#flushed, iclass 31, count 0 2006.246.07:47:39.99#ibcon#about to write, iclass 31, count 0 2006.246.07:47:39.99#ibcon#wrote, iclass 31, count 0 2006.246.07:47:39.99#ibcon#about to read 3, iclass 31, count 0 2006.246.07:47:40.01#ibcon#read 3, iclass 31, count 0 2006.246.07:47:40.01#ibcon#about to read 4, iclass 31, count 0 2006.246.07:47:40.01#ibcon#read 4, iclass 31, count 0 2006.246.07:47:40.01#ibcon#about to read 5, iclass 31, count 0 2006.246.07:47:40.01#ibcon#read 5, iclass 31, count 0 2006.246.07:47:40.01#ibcon#about to read 6, iclass 31, count 0 2006.246.07:47:40.01#ibcon#read 6, iclass 31, count 0 2006.246.07:47:40.01#ibcon#end of sib2, iclass 31, count 0 2006.246.07:47:40.01#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:47:40.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:47:40.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:47:40.01#ibcon#*before write, iclass 31, count 0 2006.246.07:47:40.01#ibcon#enter sib2, iclass 31, count 0 2006.246.07:47:40.01#ibcon#flushed, iclass 31, count 0 2006.246.07:47:40.01#ibcon#about to write, iclass 31, count 0 2006.246.07:47:40.01#ibcon#wrote, iclass 31, count 0 2006.246.07:47:40.01#ibcon#about to read 3, iclass 31, count 0 2006.246.07:47:40.05#ibcon#read 3, iclass 31, count 0 2006.246.07:47:40.05#ibcon#about to read 4, iclass 31, count 0 2006.246.07:47:40.05#ibcon#read 4, iclass 31, count 0 2006.246.07:47:40.05#ibcon#about to read 5, iclass 31, count 0 2006.246.07:47:40.05#ibcon#read 5, iclass 31, count 0 2006.246.07:47:40.05#ibcon#about to read 6, iclass 31, count 0 2006.246.07:47:40.05#ibcon#read 6, iclass 31, count 0 2006.246.07:47:40.05#ibcon#end of sib2, iclass 31, count 0 2006.246.07:47:40.05#ibcon#*after write, iclass 31, count 0 2006.246.07:47:40.05#ibcon#*before return 0, iclass 31, count 0 2006.246.07:47:40.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:47:40.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:47:40.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:47:40.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:47:40.05$vc4f8/va=7,7 2006.246.07:47:40.05#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.07:47:40.05#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.07:47:40.05#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:40.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:47:40.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:47:40.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:47:40.11#ibcon#enter wrdev, iclass 33, count 2 2006.246.07:47:40.11#ibcon#first serial, iclass 33, count 2 2006.246.07:47:40.11#ibcon#enter sib2, iclass 33, count 2 2006.246.07:47:40.11#ibcon#flushed, iclass 33, count 2 2006.246.07:47:40.11#ibcon#about to write, iclass 33, count 2 2006.246.07:47:40.11#ibcon#wrote, iclass 33, count 2 2006.246.07:47:40.11#ibcon#about to read 3, iclass 33, count 2 2006.246.07:47:40.13#ibcon#read 3, iclass 33, count 2 2006.246.07:47:40.13#ibcon#about to read 4, iclass 33, count 2 2006.246.07:47:40.13#ibcon#read 4, iclass 33, count 2 2006.246.07:47:40.13#ibcon#about to read 5, iclass 33, count 2 2006.246.07:47:40.13#ibcon#read 5, iclass 33, count 2 2006.246.07:47:40.13#ibcon#about to read 6, iclass 33, count 2 2006.246.07:47:40.13#ibcon#read 6, iclass 33, count 2 2006.246.07:47:40.13#ibcon#end of sib2, iclass 33, count 2 2006.246.07:47:40.13#ibcon#*mode == 0, iclass 33, count 2 2006.246.07:47:40.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.07:47:40.13#ibcon#[25=AT07-07\r\n] 2006.246.07:47:40.13#ibcon#*before write, iclass 33, count 2 2006.246.07:47:40.13#ibcon#enter sib2, iclass 33, count 2 2006.246.07:47:40.13#ibcon#flushed, iclass 33, count 2 2006.246.07:47:40.13#ibcon#about to write, iclass 33, count 2 2006.246.07:47:40.13#ibcon#wrote, iclass 33, count 2 2006.246.07:47:40.13#ibcon#about to read 3, iclass 33, count 2 2006.246.07:47:40.16#ibcon#read 3, iclass 33, count 2 2006.246.07:47:40.16#ibcon#about to read 4, iclass 33, count 2 2006.246.07:47:40.16#ibcon#read 4, iclass 33, count 2 2006.246.07:47:40.16#ibcon#about to read 5, iclass 33, count 2 2006.246.07:47:40.16#ibcon#read 5, iclass 33, count 2 2006.246.07:47:40.16#ibcon#about to read 6, iclass 33, count 2 2006.246.07:47:40.16#ibcon#read 6, iclass 33, count 2 2006.246.07:47:40.16#ibcon#end of sib2, iclass 33, count 2 2006.246.07:47:40.16#ibcon#*after write, iclass 33, count 2 2006.246.07:47:40.16#ibcon#*before return 0, iclass 33, count 2 2006.246.07:47:40.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:47:40.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:47:40.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.07:47:40.16#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:40.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:47:40.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:47:40.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:47:40.28#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:47:40.28#ibcon#first serial, iclass 33, count 0 2006.246.07:47:40.28#ibcon#enter sib2, iclass 33, count 0 2006.246.07:47:40.28#ibcon#flushed, iclass 33, count 0 2006.246.07:47:40.28#ibcon#about to write, iclass 33, count 0 2006.246.07:47:40.28#ibcon#wrote, iclass 33, count 0 2006.246.07:47:40.28#ibcon#about to read 3, iclass 33, count 0 2006.246.07:47:40.30#ibcon#read 3, iclass 33, count 0 2006.246.07:47:40.30#ibcon#about to read 4, iclass 33, count 0 2006.246.07:47:40.30#ibcon#read 4, iclass 33, count 0 2006.246.07:47:40.30#ibcon#about to read 5, iclass 33, count 0 2006.246.07:47:40.30#ibcon#read 5, iclass 33, count 0 2006.246.07:47:40.30#ibcon#about to read 6, iclass 33, count 0 2006.246.07:47:40.30#ibcon#read 6, iclass 33, count 0 2006.246.07:47:40.30#ibcon#end of sib2, iclass 33, count 0 2006.246.07:47:40.30#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:47:40.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:47:40.30#ibcon#[25=USB\r\n] 2006.246.07:47:40.30#ibcon#*before write, iclass 33, count 0 2006.246.07:47:40.30#ibcon#enter sib2, iclass 33, count 0 2006.246.07:47:40.30#ibcon#flushed, iclass 33, count 0 2006.246.07:47:40.30#ibcon#about to write, iclass 33, count 0 2006.246.07:47:40.30#ibcon#wrote, iclass 33, count 0 2006.246.07:47:40.30#ibcon#about to read 3, iclass 33, count 0 2006.246.07:47:40.33#ibcon#read 3, iclass 33, count 0 2006.246.07:47:40.33#ibcon#about to read 4, iclass 33, count 0 2006.246.07:47:40.33#ibcon#read 4, iclass 33, count 0 2006.246.07:47:40.33#ibcon#about to read 5, iclass 33, count 0 2006.246.07:47:40.33#ibcon#read 5, iclass 33, count 0 2006.246.07:47:40.33#ibcon#about to read 6, iclass 33, count 0 2006.246.07:47:40.33#ibcon#read 6, iclass 33, count 0 2006.246.07:47:40.33#ibcon#end of sib2, iclass 33, count 0 2006.246.07:47:40.33#ibcon#*after write, iclass 33, count 0 2006.246.07:47:40.33#ibcon#*before return 0, iclass 33, count 0 2006.246.07:47:40.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:47:40.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:47:40.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:47:40.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:47:40.33$vc4f8/valo=8,852.99 2006.246.07:47:40.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.07:47:40.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.07:47:40.33#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:40.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:47:40.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:47:40.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:47:40.33#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:47:40.33#ibcon#first serial, iclass 35, count 0 2006.246.07:47:40.33#ibcon#enter sib2, iclass 35, count 0 2006.246.07:47:40.33#ibcon#flushed, iclass 35, count 0 2006.246.07:47:40.33#ibcon#about to write, iclass 35, count 0 2006.246.07:47:40.33#ibcon#wrote, iclass 35, count 0 2006.246.07:47:40.33#ibcon#about to read 3, iclass 35, count 0 2006.246.07:47:40.36#ibcon#read 3, iclass 35, count 0 2006.246.07:47:40.36#ibcon#about to read 4, iclass 35, count 0 2006.246.07:47:40.36#ibcon#read 4, iclass 35, count 0 2006.246.07:47:40.36#ibcon#about to read 5, iclass 35, count 0 2006.246.07:47:40.36#ibcon#read 5, iclass 35, count 0 2006.246.07:47:40.36#ibcon#about to read 6, iclass 35, count 0 2006.246.07:47:40.36#ibcon#read 6, iclass 35, count 0 2006.246.07:47:40.36#ibcon#end of sib2, iclass 35, count 0 2006.246.07:47:40.36#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:47:40.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:47:40.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:47:40.36#ibcon#*before write, iclass 35, count 0 2006.246.07:47:40.36#ibcon#enter sib2, iclass 35, count 0 2006.246.07:47:40.36#ibcon#flushed, iclass 35, count 0 2006.246.07:47:40.36#ibcon#about to write, iclass 35, count 0 2006.246.07:47:40.36#ibcon#wrote, iclass 35, count 0 2006.246.07:47:40.36#ibcon#about to read 3, iclass 35, count 0 2006.246.07:47:40.40#ibcon#read 3, iclass 35, count 0 2006.246.07:47:40.40#ibcon#about to read 4, iclass 35, count 0 2006.246.07:47:40.40#ibcon#read 4, iclass 35, count 0 2006.246.07:47:40.40#ibcon#about to read 5, iclass 35, count 0 2006.246.07:47:40.40#ibcon#read 5, iclass 35, count 0 2006.246.07:47:40.40#ibcon#about to read 6, iclass 35, count 0 2006.246.07:47:40.40#ibcon#read 6, iclass 35, count 0 2006.246.07:47:40.40#ibcon#end of sib2, iclass 35, count 0 2006.246.07:47:40.40#ibcon#*after write, iclass 35, count 0 2006.246.07:47:40.40#ibcon#*before return 0, iclass 35, count 0 2006.246.07:47:40.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:47:40.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:47:40.40#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:47:40.40#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:47:40.40$vc4f8/va=8,8 2006.246.07:47:40.40#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.07:47:40.40#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.07:47:40.40#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:40.40#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:47:40.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:47:40.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:47:40.45#ibcon#enter wrdev, iclass 37, count 2 2006.246.07:47:40.45#ibcon#first serial, iclass 37, count 2 2006.246.07:47:40.45#ibcon#enter sib2, iclass 37, count 2 2006.246.07:47:40.45#ibcon#flushed, iclass 37, count 2 2006.246.07:47:40.45#ibcon#about to write, iclass 37, count 2 2006.246.07:47:40.45#ibcon#wrote, iclass 37, count 2 2006.246.07:47:40.45#ibcon#about to read 3, iclass 37, count 2 2006.246.07:47:40.47#ibcon#read 3, iclass 37, count 2 2006.246.07:47:40.47#ibcon#about to read 4, iclass 37, count 2 2006.246.07:47:40.47#ibcon#read 4, iclass 37, count 2 2006.246.07:47:40.47#ibcon#about to read 5, iclass 37, count 2 2006.246.07:47:40.47#ibcon#read 5, iclass 37, count 2 2006.246.07:47:40.47#ibcon#about to read 6, iclass 37, count 2 2006.246.07:47:40.47#ibcon#read 6, iclass 37, count 2 2006.246.07:47:40.47#ibcon#end of sib2, iclass 37, count 2 2006.246.07:47:40.47#ibcon#*mode == 0, iclass 37, count 2 2006.246.07:47:40.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.07:47:40.47#ibcon#[25=AT08-08\r\n] 2006.246.07:47:40.47#ibcon#*before write, iclass 37, count 2 2006.246.07:47:40.47#ibcon#enter sib2, iclass 37, count 2 2006.246.07:47:40.47#ibcon#flushed, iclass 37, count 2 2006.246.07:47:40.47#ibcon#about to write, iclass 37, count 2 2006.246.07:47:40.47#ibcon#wrote, iclass 37, count 2 2006.246.07:47:40.47#ibcon#about to read 3, iclass 37, count 2 2006.246.07:47:40.50#ibcon#read 3, iclass 37, count 2 2006.246.07:47:40.50#ibcon#about to read 4, iclass 37, count 2 2006.246.07:47:40.50#ibcon#read 4, iclass 37, count 2 2006.246.07:47:40.50#ibcon#about to read 5, iclass 37, count 2 2006.246.07:47:40.50#ibcon#read 5, iclass 37, count 2 2006.246.07:47:40.50#ibcon#about to read 6, iclass 37, count 2 2006.246.07:47:40.50#ibcon#read 6, iclass 37, count 2 2006.246.07:47:40.50#ibcon#end of sib2, iclass 37, count 2 2006.246.07:47:40.50#ibcon#*after write, iclass 37, count 2 2006.246.07:47:40.50#ibcon#*before return 0, iclass 37, count 2 2006.246.07:47:40.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:47:40.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:47:40.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.07:47:40.50#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:40.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:47:40.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:47:40.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:47:40.62#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:47:40.62#ibcon#first serial, iclass 37, count 0 2006.246.07:47:40.62#ibcon#enter sib2, iclass 37, count 0 2006.246.07:47:40.62#ibcon#flushed, iclass 37, count 0 2006.246.07:47:40.62#ibcon#about to write, iclass 37, count 0 2006.246.07:47:40.62#ibcon#wrote, iclass 37, count 0 2006.246.07:47:40.62#ibcon#about to read 3, iclass 37, count 0 2006.246.07:47:40.64#ibcon#read 3, iclass 37, count 0 2006.246.07:47:40.64#ibcon#about to read 4, iclass 37, count 0 2006.246.07:47:40.64#ibcon#read 4, iclass 37, count 0 2006.246.07:47:40.64#ibcon#about to read 5, iclass 37, count 0 2006.246.07:47:40.64#ibcon#read 5, iclass 37, count 0 2006.246.07:47:40.64#ibcon#about to read 6, iclass 37, count 0 2006.246.07:47:40.64#ibcon#read 6, iclass 37, count 0 2006.246.07:47:40.64#ibcon#end of sib2, iclass 37, count 0 2006.246.07:47:40.64#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:47:40.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:47:40.64#ibcon#[25=USB\r\n] 2006.246.07:47:40.64#ibcon#*before write, iclass 37, count 0 2006.246.07:47:40.64#ibcon#enter sib2, iclass 37, count 0 2006.246.07:47:40.64#ibcon#flushed, iclass 37, count 0 2006.246.07:47:40.64#ibcon#about to write, iclass 37, count 0 2006.246.07:47:40.64#ibcon#wrote, iclass 37, count 0 2006.246.07:47:40.64#ibcon#about to read 3, iclass 37, count 0 2006.246.07:47:40.67#ibcon#read 3, iclass 37, count 0 2006.246.07:47:40.67#ibcon#about to read 4, iclass 37, count 0 2006.246.07:47:40.67#ibcon#read 4, iclass 37, count 0 2006.246.07:47:40.67#ibcon#about to read 5, iclass 37, count 0 2006.246.07:47:40.67#ibcon#read 5, iclass 37, count 0 2006.246.07:47:40.67#ibcon#about to read 6, iclass 37, count 0 2006.246.07:47:40.67#ibcon#read 6, iclass 37, count 0 2006.246.07:47:40.67#ibcon#end of sib2, iclass 37, count 0 2006.246.07:47:40.67#ibcon#*after write, iclass 37, count 0 2006.246.07:47:40.67#ibcon#*before return 0, iclass 37, count 0 2006.246.07:47:40.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:47:40.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:47:40.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:47:40.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:47:40.67$vc4f8/vblo=1,632.99 2006.246.07:47:40.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:47:40.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:47:40.67#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:40.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:47:40.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:47:40.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:47:40.67#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:47:40.67#ibcon#first serial, iclass 39, count 0 2006.246.07:47:40.67#ibcon#enter sib2, iclass 39, count 0 2006.246.07:47:40.67#ibcon#flushed, iclass 39, count 0 2006.246.07:47:40.67#ibcon#about to write, iclass 39, count 0 2006.246.07:47:40.67#ibcon#wrote, iclass 39, count 0 2006.246.07:47:40.67#ibcon#about to read 3, iclass 39, count 0 2006.246.07:47:40.69#ibcon#read 3, iclass 39, count 0 2006.246.07:47:40.69#ibcon#about to read 4, iclass 39, count 0 2006.246.07:47:40.69#ibcon#read 4, iclass 39, count 0 2006.246.07:47:40.69#ibcon#about to read 5, iclass 39, count 0 2006.246.07:47:40.69#ibcon#read 5, iclass 39, count 0 2006.246.07:47:40.69#ibcon#about to read 6, iclass 39, count 0 2006.246.07:47:40.69#ibcon#read 6, iclass 39, count 0 2006.246.07:47:40.69#ibcon#end of sib2, iclass 39, count 0 2006.246.07:47:40.69#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:47:40.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:47:40.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:47:40.69#ibcon#*before write, iclass 39, count 0 2006.246.07:47:40.69#ibcon#enter sib2, iclass 39, count 0 2006.246.07:47:40.69#ibcon#flushed, iclass 39, count 0 2006.246.07:47:40.69#ibcon#about to write, iclass 39, count 0 2006.246.07:47:40.69#ibcon#wrote, iclass 39, count 0 2006.246.07:47:40.69#ibcon#about to read 3, iclass 39, count 0 2006.246.07:47:40.73#ibcon#read 3, iclass 39, count 0 2006.246.07:47:40.73#ibcon#about to read 4, iclass 39, count 0 2006.246.07:47:40.73#ibcon#read 4, iclass 39, count 0 2006.246.07:47:40.73#ibcon#about to read 5, iclass 39, count 0 2006.246.07:47:40.73#ibcon#read 5, iclass 39, count 0 2006.246.07:47:40.73#ibcon#about to read 6, iclass 39, count 0 2006.246.07:47:40.73#ibcon#read 6, iclass 39, count 0 2006.246.07:47:40.73#ibcon#end of sib2, iclass 39, count 0 2006.246.07:47:40.73#ibcon#*after write, iclass 39, count 0 2006.246.07:47:40.73#ibcon#*before return 0, iclass 39, count 0 2006.246.07:47:40.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:47:40.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:47:40.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:47:40.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:47:40.73$vc4f8/vb=1,4 2006.246.07:47:40.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.07:47:40.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.07:47:40.73#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:40.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:47:40.73#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:47:40.73#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:47:40.73#ibcon#enter wrdev, iclass 3, count 2 2006.246.07:47:40.73#ibcon#first serial, iclass 3, count 2 2006.246.07:47:40.73#ibcon#enter sib2, iclass 3, count 2 2006.246.07:47:40.73#ibcon#flushed, iclass 3, count 2 2006.246.07:47:40.73#ibcon#about to write, iclass 3, count 2 2006.246.07:47:40.73#ibcon#wrote, iclass 3, count 2 2006.246.07:47:40.73#ibcon#about to read 3, iclass 3, count 2 2006.246.07:47:40.75#ibcon#read 3, iclass 3, count 2 2006.246.07:47:40.75#ibcon#about to read 4, iclass 3, count 2 2006.246.07:47:40.75#ibcon#read 4, iclass 3, count 2 2006.246.07:47:40.75#ibcon#about to read 5, iclass 3, count 2 2006.246.07:47:40.75#ibcon#read 5, iclass 3, count 2 2006.246.07:47:40.75#ibcon#about to read 6, iclass 3, count 2 2006.246.07:47:40.75#ibcon#read 6, iclass 3, count 2 2006.246.07:47:40.75#ibcon#end of sib2, iclass 3, count 2 2006.246.07:47:40.75#ibcon#*mode == 0, iclass 3, count 2 2006.246.07:47:40.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.07:47:40.75#ibcon#[27=AT01-04\r\n] 2006.246.07:47:40.75#ibcon#*before write, iclass 3, count 2 2006.246.07:47:40.75#ibcon#enter sib2, iclass 3, count 2 2006.246.07:47:40.75#ibcon#flushed, iclass 3, count 2 2006.246.07:47:40.75#ibcon#about to write, iclass 3, count 2 2006.246.07:47:40.75#ibcon#wrote, iclass 3, count 2 2006.246.07:47:40.75#ibcon#about to read 3, iclass 3, count 2 2006.246.07:47:40.78#ibcon#read 3, iclass 3, count 2 2006.246.07:47:40.78#ibcon#about to read 4, iclass 3, count 2 2006.246.07:47:40.78#ibcon#read 4, iclass 3, count 2 2006.246.07:47:40.78#ibcon#about to read 5, iclass 3, count 2 2006.246.07:47:40.78#ibcon#read 5, iclass 3, count 2 2006.246.07:47:40.78#ibcon#about to read 6, iclass 3, count 2 2006.246.07:47:40.78#ibcon#read 6, iclass 3, count 2 2006.246.07:47:40.78#ibcon#end of sib2, iclass 3, count 2 2006.246.07:47:40.78#ibcon#*after write, iclass 3, count 2 2006.246.07:47:40.78#ibcon#*before return 0, iclass 3, count 2 2006.246.07:47:40.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:47:40.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:47:40.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.07:47:40.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:40.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:47:40.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:47:40.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:47:40.90#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:47:40.90#ibcon#first serial, iclass 3, count 0 2006.246.07:47:40.90#ibcon#enter sib2, iclass 3, count 0 2006.246.07:47:40.90#ibcon#flushed, iclass 3, count 0 2006.246.07:47:40.90#ibcon#about to write, iclass 3, count 0 2006.246.07:47:40.90#ibcon#wrote, iclass 3, count 0 2006.246.07:47:40.90#ibcon#about to read 3, iclass 3, count 0 2006.246.07:47:40.92#ibcon#read 3, iclass 3, count 0 2006.246.07:47:40.92#ibcon#about to read 4, iclass 3, count 0 2006.246.07:47:40.92#ibcon#read 4, iclass 3, count 0 2006.246.07:47:40.92#ibcon#about to read 5, iclass 3, count 0 2006.246.07:47:40.92#ibcon#read 5, iclass 3, count 0 2006.246.07:47:40.92#ibcon#about to read 6, iclass 3, count 0 2006.246.07:47:40.92#ibcon#read 6, iclass 3, count 0 2006.246.07:47:40.92#ibcon#end of sib2, iclass 3, count 0 2006.246.07:47:40.92#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:47:40.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:47:40.92#ibcon#[27=USB\r\n] 2006.246.07:47:40.92#ibcon#*before write, iclass 3, count 0 2006.246.07:47:40.92#ibcon#enter sib2, iclass 3, count 0 2006.246.07:47:40.92#ibcon#flushed, iclass 3, count 0 2006.246.07:47:40.92#ibcon#about to write, iclass 3, count 0 2006.246.07:47:40.92#ibcon#wrote, iclass 3, count 0 2006.246.07:47:40.92#ibcon#about to read 3, iclass 3, count 0 2006.246.07:47:40.95#ibcon#read 3, iclass 3, count 0 2006.246.07:47:40.95#ibcon#about to read 4, iclass 3, count 0 2006.246.07:47:40.95#ibcon#read 4, iclass 3, count 0 2006.246.07:47:40.95#ibcon#about to read 5, iclass 3, count 0 2006.246.07:47:40.95#ibcon#read 5, iclass 3, count 0 2006.246.07:47:40.95#ibcon#about to read 6, iclass 3, count 0 2006.246.07:47:40.95#ibcon#read 6, iclass 3, count 0 2006.246.07:47:40.95#ibcon#end of sib2, iclass 3, count 0 2006.246.07:47:40.95#ibcon#*after write, iclass 3, count 0 2006.246.07:47:40.95#ibcon#*before return 0, iclass 3, count 0 2006.246.07:47:40.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:47:40.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:47:40.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:47:40.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:47:40.95$vc4f8/vblo=2,640.99 2006.246.07:47:40.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:47:40.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:47:40.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:40.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:40.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:40.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:40.95#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:47:40.95#ibcon#first serial, iclass 5, count 0 2006.246.07:47:40.95#ibcon#enter sib2, iclass 5, count 0 2006.246.07:47:40.95#ibcon#flushed, iclass 5, count 0 2006.246.07:47:40.95#ibcon#about to write, iclass 5, count 0 2006.246.07:47:40.95#ibcon#wrote, iclass 5, count 0 2006.246.07:47:40.95#ibcon#about to read 3, iclass 5, count 0 2006.246.07:47:40.97#ibcon#read 3, iclass 5, count 0 2006.246.07:47:40.97#ibcon#about to read 4, iclass 5, count 0 2006.246.07:47:40.97#ibcon#read 4, iclass 5, count 0 2006.246.07:47:40.97#ibcon#about to read 5, iclass 5, count 0 2006.246.07:47:40.97#ibcon#read 5, iclass 5, count 0 2006.246.07:47:40.97#ibcon#about to read 6, iclass 5, count 0 2006.246.07:47:40.97#ibcon#read 6, iclass 5, count 0 2006.246.07:47:40.97#ibcon#end of sib2, iclass 5, count 0 2006.246.07:47:40.97#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:47:40.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:47:40.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:47:40.97#ibcon#*before write, iclass 5, count 0 2006.246.07:47:40.97#ibcon#enter sib2, iclass 5, count 0 2006.246.07:47:40.97#ibcon#flushed, iclass 5, count 0 2006.246.07:47:40.97#ibcon#about to write, iclass 5, count 0 2006.246.07:47:40.97#ibcon#wrote, iclass 5, count 0 2006.246.07:47:40.97#ibcon#about to read 3, iclass 5, count 0 2006.246.07:47:41.01#ibcon#read 3, iclass 5, count 0 2006.246.07:47:41.01#ibcon#about to read 4, iclass 5, count 0 2006.246.07:47:41.01#ibcon#read 4, iclass 5, count 0 2006.246.07:47:41.01#ibcon#about to read 5, iclass 5, count 0 2006.246.07:47:41.01#ibcon#read 5, iclass 5, count 0 2006.246.07:47:41.01#ibcon#about to read 6, iclass 5, count 0 2006.246.07:47:41.01#ibcon#read 6, iclass 5, count 0 2006.246.07:47:41.01#ibcon#end of sib2, iclass 5, count 0 2006.246.07:47:41.01#ibcon#*after write, iclass 5, count 0 2006.246.07:47:41.01#ibcon#*before return 0, iclass 5, count 0 2006.246.07:47:41.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:41.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:47:41.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:47:41.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:47:41.01$vc4f8/vb=2,4 2006.246.07:47:41.01#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:47:41.01#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:47:41.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:41.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:41.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:41.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:41.07#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:47:41.07#ibcon#first serial, iclass 7, count 2 2006.246.07:47:41.07#ibcon#enter sib2, iclass 7, count 2 2006.246.07:47:41.07#ibcon#flushed, iclass 7, count 2 2006.246.07:47:41.07#ibcon#about to write, iclass 7, count 2 2006.246.07:47:41.07#ibcon#wrote, iclass 7, count 2 2006.246.07:47:41.07#ibcon#about to read 3, iclass 7, count 2 2006.246.07:47:41.09#ibcon#read 3, iclass 7, count 2 2006.246.07:47:41.09#ibcon#about to read 4, iclass 7, count 2 2006.246.07:47:41.09#ibcon#read 4, iclass 7, count 2 2006.246.07:47:41.09#ibcon#about to read 5, iclass 7, count 2 2006.246.07:47:41.09#ibcon#read 5, iclass 7, count 2 2006.246.07:47:41.09#ibcon#about to read 6, iclass 7, count 2 2006.246.07:47:41.09#ibcon#read 6, iclass 7, count 2 2006.246.07:47:41.09#ibcon#end of sib2, iclass 7, count 2 2006.246.07:47:41.09#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:47:41.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:47:41.09#ibcon#[27=AT02-04\r\n] 2006.246.07:47:41.09#ibcon#*before write, iclass 7, count 2 2006.246.07:47:41.09#ibcon#enter sib2, iclass 7, count 2 2006.246.07:47:41.09#ibcon#flushed, iclass 7, count 2 2006.246.07:47:41.09#ibcon#about to write, iclass 7, count 2 2006.246.07:47:41.09#ibcon#wrote, iclass 7, count 2 2006.246.07:47:41.09#ibcon#about to read 3, iclass 7, count 2 2006.246.07:47:41.12#ibcon#read 3, iclass 7, count 2 2006.246.07:47:41.12#ibcon#about to read 4, iclass 7, count 2 2006.246.07:47:41.12#ibcon#read 4, iclass 7, count 2 2006.246.07:47:41.12#ibcon#about to read 5, iclass 7, count 2 2006.246.07:47:41.12#ibcon#read 5, iclass 7, count 2 2006.246.07:47:41.12#ibcon#about to read 6, iclass 7, count 2 2006.246.07:47:41.12#ibcon#read 6, iclass 7, count 2 2006.246.07:47:41.12#ibcon#end of sib2, iclass 7, count 2 2006.246.07:47:41.12#ibcon#*after write, iclass 7, count 2 2006.246.07:47:41.12#ibcon#*before return 0, iclass 7, count 2 2006.246.07:47:41.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:41.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:47:41.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:47:41.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:41.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:41.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:41.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:41.24#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:47:41.24#ibcon#first serial, iclass 7, count 0 2006.246.07:47:41.24#ibcon#enter sib2, iclass 7, count 0 2006.246.07:47:41.24#ibcon#flushed, iclass 7, count 0 2006.246.07:47:41.24#ibcon#about to write, iclass 7, count 0 2006.246.07:47:41.24#ibcon#wrote, iclass 7, count 0 2006.246.07:47:41.24#ibcon#about to read 3, iclass 7, count 0 2006.246.07:47:41.26#ibcon#read 3, iclass 7, count 0 2006.246.07:47:41.26#ibcon#about to read 4, iclass 7, count 0 2006.246.07:47:41.26#ibcon#read 4, iclass 7, count 0 2006.246.07:47:41.26#ibcon#about to read 5, iclass 7, count 0 2006.246.07:47:41.26#ibcon#read 5, iclass 7, count 0 2006.246.07:47:41.26#ibcon#about to read 6, iclass 7, count 0 2006.246.07:47:41.26#ibcon#read 6, iclass 7, count 0 2006.246.07:47:41.26#ibcon#end of sib2, iclass 7, count 0 2006.246.07:47:41.26#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:47:41.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:47:41.26#ibcon#[27=USB\r\n] 2006.246.07:47:41.26#ibcon#*before write, iclass 7, count 0 2006.246.07:47:41.26#ibcon#enter sib2, iclass 7, count 0 2006.246.07:47:41.26#ibcon#flushed, iclass 7, count 0 2006.246.07:47:41.26#ibcon#about to write, iclass 7, count 0 2006.246.07:47:41.26#ibcon#wrote, iclass 7, count 0 2006.246.07:47:41.26#ibcon#about to read 3, iclass 7, count 0 2006.246.07:47:41.29#ibcon#read 3, iclass 7, count 0 2006.246.07:47:41.29#ibcon#about to read 4, iclass 7, count 0 2006.246.07:47:41.29#ibcon#read 4, iclass 7, count 0 2006.246.07:47:41.29#ibcon#about to read 5, iclass 7, count 0 2006.246.07:47:41.29#ibcon#read 5, iclass 7, count 0 2006.246.07:47:41.29#ibcon#about to read 6, iclass 7, count 0 2006.246.07:47:41.29#ibcon#read 6, iclass 7, count 0 2006.246.07:47:41.29#ibcon#end of sib2, iclass 7, count 0 2006.246.07:47:41.29#ibcon#*after write, iclass 7, count 0 2006.246.07:47:41.29#ibcon#*before return 0, iclass 7, count 0 2006.246.07:47:41.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:41.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:47:41.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:47:41.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:47:41.29$vc4f8/vblo=3,656.99 2006.246.07:47:41.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:47:41.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:47:41.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:41.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:41.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:41.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:41.29#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:47:41.29#ibcon#first serial, iclass 11, count 0 2006.246.07:47:41.29#ibcon#enter sib2, iclass 11, count 0 2006.246.07:47:41.29#ibcon#flushed, iclass 11, count 0 2006.246.07:47:41.29#ibcon#about to write, iclass 11, count 0 2006.246.07:47:41.29#ibcon#wrote, iclass 11, count 0 2006.246.07:47:41.29#ibcon#about to read 3, iclass 11, count 0 2006.246.07:47:41.32#ibcon#read 3, iclass 11, count 0 2006.246.07:47:41.32#ibcon#about to read 4, iclass 11, count 0 2006.246.07:47:41.32#ibcon#read 4, iclass 11, count 0 2006.246.07:47:41.32#ibcon#about to read 5, iclass 11, count 0 2006.246.07:47:41.32#ibcon#read 5, iclass 11, count 0 2006.246.07:47:41.32#ibcon#about to read 6, iclass 11, count 0 2006.246.07:47:41.32#ibcon#read 6, iclass 11, count 0 2006.246.07:47:41.32#ibcon#end of sib2, iclass 11, count 0 2006.246.07:47:41.32#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:47:41.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:47:41.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:47:41.32#ibcon#*before write, iclass 11, count 0 2006.246.07:47:41.32#ibcon#enter sib2, iclass 11, count 0 2006.246.07:47:41.32#ibcon#flushed, iclass 11, count 0 2006.246.07:47:41.32#ibcon#about to write, iclass 11, count 0 2006.246.07:47:41.32#ibcon#wrote, iclass 11, count 0 2006.246.07:47:41.32#ibcon#about to read 3, iclass 11, count 0 2006.246.07:47:41.36#ibcon#read 3, iclass 11, count 0 2006.246.07:47:41.36#ibcon#about to read 4, iclass 11, count 0 2006.246.07:47:41.36#ibcon#read 4, iclass 11, count 0 2006.246.07:47:41.36#ibcon#about to read 5, iclass 11, count 0 2006.246.07:47:41.36#ibcon#read 5, iclass 11, count 0 2006.246.07:47:41.36#ibcon#about to read 6, iclass 11, count 0 2006.246.07:47:41.36#ibcon#read 6, iclass 11, count 0 2006.246.07:47:41.36#ibcon#end of sib2, iclass 11, count 0 2006.246.07:47:41.36#ibcon#*after write, iclass 11, count 0 2006.246.07:47:41.36#ibcon#*before return 0, iclass 11, count 0 2006.246.07:47:41.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:41.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:47:41.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:47:41.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:47:41.36$vc4f8/vb=3,4 2006.246.07:47:41.36#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:47:41.36#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:47:41.36#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:41.36#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:41.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:41.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:41.41#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:47:41.41#ibcon#first serial, iclass 13, count 2 2006.246.07:47:41.41#ibcon#enter sib2, iclass 13, count 2 2006.246.07:47:41.41#ibcon#flushed, iclass 13, count 2 2006.246.07:47:41.41#ibcon#about to write, iclass 13, count 2 2006.246.07:47:41.41#ibcon#wrote, iclass 13, count 2 2006.246.07:47:41.41#ibcon#about to read 3, iclass 13, count 2 2006.246.07:47:41.43#ibcon#read 3, iclass 13, count 2 2006.246.07:47:41.43#ibcon#about to read 4, iclass 13, count 2 2006.246.07:47:41.43#ibcon#read 4, iclass 13, count 2 2006.246.07:47:41.43#ibcon#about to read 5, iclass 13, count 2 2006.246.07:47:41.43#ibcon#read 5, iclass 13, count 2 2006.246.07:47:41.43#ibcon#about to read 6, iclass 13, count 2 2006.246.07:47:41.43#ibcon#read 6, iclass 13, count 2 2006.246.07:47:41.43#ibcon#end of sib2, iclass 13, count 2 2006.246.07:47:41.43#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:47:41.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:47:41.43#ibcon#[27=AT03-04\r\n] 2006.246.07:47:41.43#ibcon#*before write, iclass 13, count 2 2006.246.07:47:41.43#ibcon#enter sib2, iclass 13, count 2 2006.246.07:47:41.43#ibcon#flushed, iclass 13, count 2 2006.246.07:47:41.43#ibcon#about to write, iclass 13, count 2 2006.246.07:47:41.43#ibcon#wrote, iclass 13, count 2 2006.246.07:47:41.43#ibcon#about to read 3, iclass 13, count 2 2006.246.07:47:41.46#ibcon#read 3, iclass 13, count 2 2006.246.07:47:41.46#ibcon#about to read 4, iclass 13, count 2 2006.246.07:47:41.46#ibcon#read 4, iclass 13, count 2 2006.246.07:47:41.46#ibcon#about to read 5, iclass 13, count 2 2006.246.07:47:41.46#ibcon#read 5, iclass 13, count 2 2006.246.07:47:41.46#ibcon#about to read 6, iclass 13, count 2 2006.246.07:47:41.46#ibcon#read 6, iclass 13, count 2 2006.246.07:47:41.46#ibcon#end of sib2, iclass 13, count 2 2006.246.07:47:41.46#ibcon#*after write, iclass 13, count 2 2006.246.07:47:41.46#ibcon#*before return 0, iclass 13, count 2 2006.246.07:47:41.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:41.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:47:41.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:47:41.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:41.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:41.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:41.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:41.58#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:47:41.58#ibcon#first serial, iclass 13, count 0 2006.246.07:47:41.58#ibcon#enter sib2, iclass 13, count 0 2006.246.07:47:41.58#ibcon#flushed, iclass 13, count 0 2006.246.07:47:41.58#ibcon#about to write, iclass 13, count 0 2006.246.07:47:41.58#ibcon#wrote, iclass 13, count 0 2006.246.07:47:41.58#ibcon#about to read 3, iclass 13, count 0 2006.246.07:47:41.60#ibcon#read 3, iclass 13, count 0 2006.246.07:47:41.60#ibcon#about to read 4, iclass 13, count 0 2006.246.07:47:41.60#ibcon#read 4, iclass 13, count 0 2006.246.07:47:41.60#ibcon#about to read 5, iclass 13, count 0 2006.246.07:47:41.60#ibcon#read 5, iclass 13, count 0 2006.246.07:47:41.60#ibcon#about to read 6, iclass 13, count 0 2006.246.07:47:41.60#ibcon#read 6, iclass 13, count 0 2006.246.07:47:41.60#ibcon#end of sib2, iclass 13, count 0 2006.246.07:47:41.60#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:47:41.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:47:41.60#ibcon#[27=USB\r\n] 2006.246.07:47:41.60#ibcon#*before write, iclass 13, count 0 2006.246.07:47:41.60#ibcon#enter sib2, iclass 13, count 0 2006.246.07:47:41.60#ibcon#flushed, iclass 13, count 0 2006.246.07:47:41.60#ibcon#about to write, iclass 13, count 0 2006.246.07:47:41.60#ibcon#wrote, iclass 13, count 0 2006.246.07:47:41.60#ibcon#about to read 3, iclass 13, count 0 2006.246.07:47:41.63#ibcon#read 3, iclass 13, count 0 2006.246.07:47:41.63#ibcon#about to read 4, iclass 13, count 0 2006.246.07:47:41.63#ibcon#read 4, iclass 13, count 0 2006.246.07:47:41.63#ibcon#about to read 5, iclass 13, count 0 2006.246.07:47:41.63#ibcon#read 5, iclass 13, count 0 2006.246.07:47:41.63#ibcon#about to read 6, iclass 13, count 0 2006.246.07:47:41.63#ibcon#read 6, iclass 13, count 0 2006.246.07:47:41.63#ibcon#end of sib2, iclass 13, count 0 2006.246.07:47:41.63#ibcon#*after write, iclass 13, count 0 2006.246.07:47:41.63#ibcon#*before return 0, iclass 13, count 0 2006.246.07:47:41.63#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:41.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:47:41.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:47:41.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:47:41.63$vc4f8/vblo=4,712.99 2006.246.07:47:41.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:47:41.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:47:41.63#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:41.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:41.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:41.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:41.63#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:47:41.63#ibcon#first serial, iclass 15, count 0 2006.246.07:47:41.63#ibcon#enter sib2, iclass 15, count 0 2006.246.07:47:41.63#ibcon#flushed, iclass 15, count 0 2006.246.07:47:41.63#ibcon#about to write, iclass 15, count 0 2006.246.07:47:41.63#ibcon#wrote, iclass 15, count 0 2006.246.07:47:41.63#ibcon#about to read 3, iclass 15, count 0 2006.246.07:47:41.65#ibcon#read 3, iclass 15, count 0 2006.246.07:47:41.65#ibcon#about to read 4, iclass 15, count 0 2006.246.07:47:41.65#ibcon#read 4, iclass 15, count 0 2006.246.07:47:41.65#ibcon#about to read 5, iclass 15, count 0 2006.246.07:47:41.65#ibcon#read 5, iclass 15, count 0 2006.246.07:47:41.65#ibcon#about to read 6, iclass 15, count 0 2006.246.07:47:41.65#ibcon#read 6, iclass 15, count 0 2006.246.07:47:41.65#ibcon#end of sib2, iclass 15, count 0 2006.246.07:47:41.65#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:47:41.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:47:41.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:47:41.65#ibcon#*before write, iclass 15, count 0 2006.246.07:47:41.65#ibcon#enter sib2, iclass 15, count 0 2006.246.07:47:41.65#ibcon#flushed, iclass 15, count 0 2006.246.07:47:41.65#ibcon#about to write, iclass 15, count 0 2006.246.07:47:41.65#ibcon#wrote, iclass 15, count 0 2006.246.07:47:41.65#ibcon#about to read 3, iclass 15, count 0 2006.246.07:47:41.69#ibcon#read 3, iclass 15, count 0 2006.246.07:47:41.69#ibcon#about to read 4, iclass 15, count 0 2006.246.07:47:41.69#ibcon#read 4, iclass 15, count 0 2006.246.07:47:41.69#ibcon#about to read 5, iclass 15, count 0 2006.246.07:47:41.69#ibcon#read 5, iclass 15, count 0 2006.246.07:47:41.69#ibcon#about to read 6, iclass 15, count 0 2006.246.07:47:41.69#ibcon#read 6, iclass 15, count 0 2006.246.07:47:41.69#ibcon#end of sib2, iclass 15, count 0 2006.246.07:47:41.69#ibcon#*after write, iclass 15, count 0 2006.246.07:47:41.69#ibcon#*before return 0, iclass 15, count 0 2006.246.07:47:41.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:41.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:47:41.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:47:41.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:47:41.69$vc4f8/vb=4,4 2006.246.07:47:41.69#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.07:47:41.69#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.07:47:41.69#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:41.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:41.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:41.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:41.75#ibcon#enter wrdev, iclass 17, count 2 2006.246.07:47:41.75#ibcon#first serial, iclass 17, count 2 2006.246.07:47:41.75#ibcon#enter sib2, iclass 17, count 2 2006.246.07:47:41.75#ibcon#flushed, iclass 17, count 2 2006.246.07:47:41.75#ibcon#about to write, iclass 17, count 2 2006.246.07:47:41.75#ibcon#wrote, iclass 17, count 2 2006.246.07:47:41.75#ibcon#about to read 3, iclass 17, count 2 2006.246.07:47:41.77#ibcon#read 3, iclass 17, count 2 2006.246.07:47:41.77#ibcon#about to read 4, iclass 17, count 2 2006.246.07:47:41.77#ibcon#read 4, iclass 17, count 2 2006.246.07:47:41.77#ibcon#about to read 5, iclass 17, count 2 2006.246.07:47:41.77#ibcon#read 5, iclass 17, count 2 2006.246.07:47:41.77#ibcon#about to read 6, iclass 17, count 2 2006.246.07:47:41.77#ibcon#read 6, iclass 17, count 2 2006.246.07:47:41.77#ibcon#end of sib2, iclass 17, count 2 2006.246.07:47:41.77#ibcon#*mode == 0, iclass 17, count 2 2006.246.07:47:41.77#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.07:47:41.77#ibcon#[27=AT04-04\r\n] 2006.246.07:47:41.77#ibcon#*before write, iclass 17, count 2 2006.246.07:47:41.77#ibcon#enter sib2, iclass 17, count 2 2006.246.07:47:41.77#ibcon#flushed, iclass 17, count 2 2006.246.07:47:41.77#ibcon#about to write, iclass 17, count 2 2006.246.07:47:41.77#ibcon#wrote, iclass 17, count 2 2006.246.07:47:41.77#ibcon#about to read 3, iclass 17, count 2 2006.246.07:47:41.80#ibcon#read 3, iclass 17, count 2 2006.246.07:47:41.80#ibcon#about to read 4, iclass 17, count 2 2006.246.07:47:41.80#ibcon#read 4, iclass 17, count 2 2006.246.07:47:41.80#ibcon#about to read 5, iclass 17, count 2 2006.246.07:47:41.80#ibcon#read 5, iclass 17, count 2 2006.246.07:47:41.80#ibcon#about to read 6, iclass 17, count 2 2006.246.07:47:41.80#ibcon#read 6, iclass 17, count 2 2006.246.07:47:41.80#ibcon#end of sib2, iclass 17, count 2 2006.246.07:47:41.80#ibcon#*after write, iclass 17, count 2 2006.246.07:47:41.80#ibcon#*before return 0, iclass 17, count 2 2006.246.07:47:41.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:41.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:47:41.80#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.07:47:41.80#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:41.80#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:41.92#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:41.92#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:41.92#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:47:41.92#ibcon#first serial, iclass 17, count 0 2006.246.07:47:41.92#ibcon#enter sib2, iclass 17, count 0 2006.246.07:47:41.92#ibcon#flushed, iclass 17, count 0 2006.246.07:47:41.92#ibcon#about to write, iclass 17, count 0 2006.246.07:47:41.92#ibcon#wrote, iclass 17, count 0 2006.246.07:47:41.92#ibcon#about to read 3, iclass 17, count 0 2006.246.07:47:41.94#ibcon#read 3, iclass 17, count 0 2006.246.07:47:41.94#ibcon#about to read 4, iclass 17, count 0 2006.246.07:47:41.94#ibcon#read 4, iclass 17, count 0 2006.246.07:47:41.94#ibcon#about to read 5, iclass 17, count 0 2006.246.07:47:41.94#ibcon#read 5, iclass 17, count 0 2006.246.07:47:41.94#ibcon#about to read 6, iclass 17, count 0 2006.246.07:47:41.94#ibcon#read 6, iclass 17, count 0 2006.246.07:47:41.94#ibcon#end of sib2, iclass 17, count 0 2006.246.07:47:41.94#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:47:41.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:47:41.94#ibcon#[27=USB\r\n] 2006.246.07:47:41.94#ibcon#*before write, iclass 17, count 0 2006.246.07:47:41.94#ibcon#enter sib2, iclass 17, count 0 2006.246.07:47:41.94#ibcon#flushed, iclass 17, count 0 2006.246.07:47:41.94#ibcon#about to write, iclass 17, count 0 2006.246.07:47:41.94#ibcon#wrote, iclass 17, count 0 2006.246.07:47:41.94#ibcon#about to read 3, iclass 17, count 0 2006.246.07:47:41.97#ibcon#read 3, iclass 17, count 0 2006.246.07:47:41.97#ibcon#about to read 4, iclass 17, count 0 2006.246.07:47:41.97#ibcon#read 4, iclass 17, count 0 2006.246.07:47:41.97#ibcon#about to read 5, iclass 17, count 0 2006.246.07:47:41.97#ibcon#read 5, iclass 17, count 0 2006.246.07:47:41.97#ibcon#about to read 6, iclass 17, count 0 2006.246.07:47:41.97#ibcon#read 6, iclass 17, count 0 2006.246.07:47:41.97#ibcon#end of sib2, iclass 17, count 0 2006.246.07:47:41.97#ibcon#*after write, iclass 17, count 0 2006.246.07:47:41.97#ibcon#*before return 0, iclass 17, count 0 2006.246.07:47:41.97#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:41.97#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:47:41.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:47:41.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:47:41.97$vc4f8/vblo=5,744.99 2006.246.07:47:41.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:47:41.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:47:41.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:41.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:41.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:41.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:41.97#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:47:41.97#ibcon#first serial, iclass 19, count 0 2006.246.07:47:41.97#ibcon#enter sib2, iclass 19, count 0 2006.246.07:47:41.97#ibcon#flushed, iclass 19, count 0 2006.246.07:47:41.97#ibcon#about to write, iclass 19, count 0 2006.246.07:47:41.97#ibcon#wrote, iclass 19, count 0 2006.246.07:47:41.97#ibcon#about to read 3, iclass 19, count 0 2006.246.07:47:42.00#ibcon#read 3, iclass 19, count 0 2006.246.07:47:42.00#ibcon#about to read 4, iclass 19, count 0 2006.246.07:47:42.00#ibcon#read 4, iclass 19, count 0 2006.246.07:47:42.00#ibcon#about to read 5, iclass 19, count 0 2006.246.07:47:42.00#ibcon#read 5, iclass 19, count 0 2006.246.07:47:42.00#ibcon#about to read 6, iclass 19, count 0 2006.246.07:47:42.00#ibcon#read 6, iclass 19, count 0 2006.246.07:47:42.00#ibcon#end of sib2, iclass 19, count 0 2006.246.07:47:42.00#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:47:42.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:47:42.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:47:42.00#ibcon#*before write, iclass 19, count 0 2006.246.07:47:42.00#ibcon#enter sib2, iclass 19, count 0 2006.246.07:47:42.00#ibcon#flushed, iclass 19, count 0 2006.246.07:47:42.00#ibcon#about to write, iclass 19, count 0 2006.246.07:47:42.00#ibcon#wrote, iclass 19, count 0 2006.246.07:47:42.00#ibcon#about to read 3, iclass 19, count 0 2006.246.07:47:42.04#ibcon#read 3, iclass 19, count 0 2006.246.07:47:42.04#ibcon#about to read 4, iclass 19, count 0 2006.246.07:47:42.04#ibcon#read 4, iclass 19, count 0 2006.246.07:47:42.04#ibcon#about to read 5, iclass 19, count 0 2006.246.07:47:42.04#ibcon#read 5, iclass 19, count 0 2006.246.07:47:42.04#ibcon#about to read 6, iclass 19, count 0 2006.246.07:47:42.04#ibcon#read 6, iclass 19, count 0 2006.246.07:47:42.04#ibcon#end of sib2, iclass 19, count 0 2006.246.07:47:42.04#ibcon#*after write, iclass 19, count 0 2006.246.07:47:42.04#ibcon#*before return 0, iclass 19, count 0 2006.246.07:47:42.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:42.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:47:42.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:47:42.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:47:42.04$vc4f8/vb=5,3 2006.246.07:47:42.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:47:42.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:47:42.04#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:42.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:42.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:42.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:42.09#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:47:42.09#ibcon#first serial, iclass 21, count 2 2006.246.07:47:42.09#ibcon#enter sib2, iclass 21, count 2 2006.246.07:47:42.09#ibcon#flushed, iclass 21, count 2 2006.246.07:47:42.09#ibcon#about to write, iclass 21, count 2 2006.246.07:47:42.09#ibcon#wrote, iclass 21, count 2 2006.246.07:47:42.09#ibcon#about to read 3, iclass 21, count 2 2006.246.07:47:42.11#ibcon#read 3, iclass 21, count 2 2006.246.07:47:42.11#ibcon#about to read 4, iclass 21, count 2 2006.246.07:47:42.11#ibcon#read 4, iclass 21, count 2 2006.246.07:47:42.11#ibcon#about to read 5, iclass 21, count 2 2006.246.07:47:42.11#ibcon#read 5, iclass 21, count 2 2006.246.07:47:42.11#ibcon#about to read 6, iclass 21, count 2 2006.246.07:47:42.11#ibcon#read 6, iclass 21, count 2 2006.246.07:47:42.11#ibcon#end of sib2, iclass 21, count 2 2006.246.07:47:42.11#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:47:42.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:47:42.11#ibcon#[27=AT05-03\r\n] 2006.246.07:47:42.11#ibcon#*before write, iclass 21, count 2 2006.246.07:47:42.11#ibcon#enter sib2, iclass 21, count 2 2006.246.07:47:42.11#ibcon#flushed, iclass 21, count 2 2006.246.07:47:42.11#ibcon#about to write, iclass 21, count 2 2006.246.07:47:42.11#ibcon#wrote, iclass 21, count 2 2006.246.07:47:42.11#ibcon#about to read 3, iclass 21, count 2 2006.246.07:47:42.14#ibcon#read 3, iclass 21, count 2 2006.246.07:47:42.14#ibcon#about to read 4, iclass 21, count 2 2006.246.07:47:42.14#ibcon#read 4, iclass 21, count 2 2006.246.07:47:42.14#ibcon#about to read 5, iclass 21, count 2 2006.246.07:47:42.14#ibcon#read 5, iclass 21, count 2 2006.246.07:47:42.14#ibcon#about to read 6, iclass 21, count 2 2006.246.07:47:42.14#ibcon#read 6, iclass 21, count 2 2006.246.07:47:42.14#ibcon#end of sib2, iclass 21, count 2 2006.246.07:47:42.14#ibcon#*after write, iclass 21, count 2 2006.246.07:47:42.14#ibcon#*before return 0, iclass 21, count 2 2006.246.07:47:42.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:42.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:47:42.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:47:42.14#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:42.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:42.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:42.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:42.26#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:47:42.26#ibcon#first serial, iclass 21, count 0 2006.246.07:47:42.26#ibcon#enter sib2, iclass 21, count 0 2006.246.07:47:42.26#ibcon#flushed, iclass 21, count 0 2006.246.07:47:42.26#ibcon#about to write, iclass 21, count 0 2006.246.07:47:42.26#ibcon#wrote, iclass 21, count 0 2006.246.07:47:42.26#ibcon#about to read 3, iclass 21, count 0 2006.246.07:47:42.28#ibcon#read 3, iclass 21, count 0 2006.246.07:47:42.28#ibcon#about to read 4, iclass 21, count 0 2006.246.07:47:42.28#ibcon#read 4, iclass 21, count 0 2006.246.07:47:42.28#ibcon#about to read 5, iclass 21, count 0 2006.246.07:47:42.28#ibcon#read 5, iclass 21, count 0 2006.246.07:47:42.28#ibcon#about to read 6, iclass 21, count 0 2006.246.07:47:42.28#ibcon#read 6, iclass 21, count 0 2006.246.07:47:42.28#ibcon#end of sib2, iclass 21, count 0 2006.246.07:47:42.28#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:47:42.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:47:42.28#ibcon#[27=USB\r\n] 2006.246.07:47:42.28#ibcon#*before write, iclass 21, count 0 2006.246.07:47:42.28#ibcon#enter sib2, iclass 21, count 0 2006.246.07:47:42.28#ibcon#flushed, iclass 21, count 0 2006.246.07:47:42.28#ibcon#about to write, iclass 21, count 0 2006.246.07:47:42.28#ibcon#wrote, iclass 21, count 0 2006.246.07:47:42.28#ibcon#about to read 3, iclass 21, count 0 2006.246.07:47:42.31#ibcon#read 3, iclass 21, count 0 2006.246.07:47:42.31#ibcon#about to read 4, iclass 21, count 0 2006.246.07:47:42.31#ibcon#read 4, iclass 21, count 0 2006.246.07:47:42.31#ibcon#about to read 5, iclass 21, count 0 2006.246.07:47:42.31#ibcon#read 5, iclass 21, count 0 2006.246.07:47:42.31#ibcon#about to read 6, iclass 21, count 0 2006.246.07:47:42.31#ibcon#read 6, iclass 21, count 0 2006.246.07:47:42.31#ibcon#end of sib2, iclass 21, count 0 2006.246.07:47:42.31#ibcon#*after write, iclass 21, count 0 2006.246.07:47:42.31#ibcon#*before return 0, iclass 21, count 0 2006.246.07:47:42.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:42.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:47:42.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:47:42.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:47:42.31$vc4f8/vblo=6,752.99 2006.246.07:47:42.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:47:42.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:47:42.31#ibcon#ireg 17 cls_cnt 0 2006.246.07:47:42.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:42.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:42.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:42.31#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:47:42.31#ibcon#first serial, iclass 23, count 0 2006.246.07:47:42.31#ibcon#enter sib2, iclass 23, count 0 2006.246.07:47:42.31#ibcon#flushed, iclass 23, count 0 2006.246.07:47:42.31#ibcon#about to write, iclass 23, count 0 2006.246.07:47:42.31#ibcon#wrote, iclass 23, count 0 2006.246.07:47:42.31#ibcon#about to read 3, iclass 23, count 0 2006.246.07:47:42.33#ibcon#read 3, iclass 23, count 0 2006.246.07:47:42.33#ibcon#about to read 4, iclass 23, count 0 2006.246.07:47:42.33#ibcon#read 4, iclass 23, count 0 2006.246.07:47:42.33#ibcon#about to read 5, iclass 23, count 0 2006.246.07:47:42.33#ibcon#read 5, iclass 23, count 0 2006.246.07:47:42.33#ibcon#about to read 6, iclass 23, count 0 2006.246.07:47:42.33#ibcon#read 6, iclass 23, count 0 2006.246.07:47:42.33#ibcon#end of sib2, iclass 23, count 0 2006.246.07:47:42.33#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:47:42.33#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:47:42.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:47:42.33#ibcon#*before write, iclass 23, count 0 2006.246.07:47:42.33#ibcon#enter sib2, iclass 23, count 0 2006.246.07:47:42.33#ibcon#flushed, iclass 23, count 0 2006.246.07:47:42.33#ibcon#about to write, iclass 23, count 0 2006.246.07:47:42.33#ibcon#wrote, iclass 23, count 0 2006.246.07:47:42.33#ibcon#about to read 3, iclass 23, count 0 2006.246.07:47:42.37#ibcon#read 3, iclass 23, count 0 2006.246.07:47:42.37#ibcon#about to read 4, iclass 23, count 0 2006.246.07:47:42.37#ibcon#read 4, iclass 23, count 0 2006.246.07:47:42.37#ibcon#about to read 5, iclass 23, count 0 2006.246.07:47:42.37#ibcon#read 5, iclass 23, count 0 2006.246.07:47:42.37#ibcon#about to read 6, iclass 23, count 0 2006.246.07:47:42.37#ibcon#read 6, iclass 23, count 0 2006.246.07:47:42.37#ibcon#end of sib2, iclass 23, count 0 2006.246.07:47:42.37#ibcon#*after write, iclass 23, count 0 2006.246.07:47:42.37#ibcon#*before return 0, iclass 23, count 0 2006.246.07:47:42.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:42.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:47:42.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:47:42.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:47:42.37$vc4f8/vb=6,3 2006.246.07:47:42.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:47:42.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:47:42.37#ibcon#ireg 11 cls_cnt 2 2006.246.07:47:42.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:42.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:42.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:42.43#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:47:42.43#ibcon#first serial, iclass 25, count 2 2006.246.07:47:42.43#ibcon#enter sib2, iclass 25, count 2 2006.246.07:47:42.43#ibcon#flushed, iclass 25, count 2 2006.246.07:47:42.43#ibcon#about to write, iclass 25, count 2 2006.246.07:47:42.43#ibcon#wrote, iclass 25, count 2 2006.246.07:47:42.43#ibcon#about to read 3, iclass 25, count 2 2006.246.07:47:42.45#ibcon#read 3, iclass 25, count 2 2006.246.07:47:42.45#ibcon#about to read 4, iclass 25, count 2 2006.246.07:47:42.45#ibcon#read 4, iclass 25, count 2 2006.246.07:47:42.45#ibcon#about to read 5, iclass 25, count 2 2006.246.07:47:42.45#ibcon#read 5, iclass 25, count 2 2006.246.07:47:42.45#ibcon#about to read 6, iclass 25, count 2 2006.246.07:47:42.45#ibcon#read 6, iclass 25, count 2 2006.246.07:47:42.45#ibcon#end of sib2, iclass 25, count 2 2006.246.07:47:42.45#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:47:42.45#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:47:42.45#ibcon#[27=AT06-03\r\n] 2006.246.07:47:42.45#ibcon#*before write, iclass 25, count 2 2006.246.07:47:42.45#ibcon#enter sib2, iclass 25, count 2 2006.246.07:47:42.45#ibcon#flushed, iclass 25, count 2 2006.246.07:47:42.45#ibcon#about to write, iclass 25, count 2 2006.246.07:47:42.45#ibcon#wrote, iclass 25, count 2 2006.246.07:47:42.45#ibcon#about to read 3, iclass 25, count 2 2006.246.07:47:42.48#ibcon#read 3, iclass 25, count 2 2006.246.07:47:42.48#ibcon#about to read 4, iclass 25, count 2 2006.246.07:47:42.48#ibcon#read 4, iclass 25, count 2 2006.246.07:47:42.48#ibcon#about to read 5, iclass 25, count 2 2006.246.07:47:42.48#ibcon#read 5, iclass 25, count 2 2006.246.07:47:42.48#ibcon#about to read 6, iclass 25, count 2 2006.246.07:47:42.48#ibcon#read 6, iclass 25, count 2 2006.246.07:47:42.48#ibcon#end of sib2, iclass 25, count 2 2006.246.07:47:42.48#ibcon#*after write, iclass 25, count 2 2006.246.07:47:42.48#ibcon#*before return 0, iclass 25, count 2 2006.246.07:47:42.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:42.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:47:42.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:47:42.48#ibcon#ireg 7 cls_cnt 0 2006.246.07:47:42.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:42.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:42.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:42.60#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:47:42.60#ibcon#first serial, iclass 25, count 0 2006.246.07:47:42.60#ibcon#enter sib2, iclass 25, count 0 2006.246.07:47:42.60#ibcon#flushed, iclass 25, count 0 2006.246.07:47:42.60#ibcon#about to write, iclass 25, count 0 2006.246.07:47:42.60#ibcon#wrote, iclass 25, count 0 2006.246.07:47:42.60#ibcon#about to read 3, iclass 25, count 0 2006.246.07:47:42.62#ibcon#read 3, iclass 25, count 0 2006.246.07:47:42.62#ibcon#about to read 4, iclass 25, count 0 2006.246.07:47:42.62#ibcon#read 4, iclass 25, count 0 2006.246.07:47:42.62#ibcon#about to read 5, iclass 25, count 0 2006.246.07:47:42.62#ibcon#read 5, iclass 25, count 0 2006.246.07:47:42.62#ibcon#about to read 6, iclass 25, count 0 2006.246.07:47:42.62#ibcon#read 6, iclass 25, count 0 2006.246.07:47:42.62#ibcon#end of sib2, iclass 25, count 0 2006.246.07:47:42.62#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:47:42.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:47:42.62#ibcon#[27=USB\r\n] 2006.246.07:47:42.62#ibcon#*before write, iclass 25, count 0 2006.246.07:47:42.62#ibcon#enter sib2, iclass 25, count 0 2006.246.07:47:42.62#ibcon#flushed, iclass 25, count 0 2006.246.07:47:42.62#ibcon#about to write, iclass 25, count 0 2006.246.07:47:42.62#ibcon#wrote, iclass 25, count 0 2006.246.07:47:42.62#ibcon#about to read 3, iclass 25, count 0 2006.246.07:47:42.65#ibcon#read 3, iclass 25, count 0 2006.246.07:47:42.65#ibcon#about to read 4, iclass 25, count 0 2006.246.07:47:42.65#ibcon#read 4, iclass 25, count 0 2006.246.07:47:42.65#ibcon#about to read 5, iclass 25, count 0 2006.246.07:47:42.65#ibcon#read 5, iclass 25, count 0 2006.246.07:47:42.65#ibcon#about to read 6, iclass 25, count 0 2006.246.07:47:42.65#ibcon#read 6, iclass 25, count 0 2006.246.07:47:42.65#ibcon#end of sib2, iclass 25, count 0 2006.246.07:47:42.65#ibcon#*after write, iclass 25, count 0 2006.246.07:47:42.65#ibcon#*before return 0, iclass 25, count 0 2006.246.07:47:42.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:42.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:47:42.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:47:42.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:47:42.65$vc4f8/vabw=wide 2006.246.07:47:42.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:47:42.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:47:42.65#ibcon#ireg 8 cls_cnt 0 2006.246.07:47:42.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:42.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:42.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:42.65#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:47:42.65#ibcon#first serial, iclass 27, count 0 2006.246.07:47:42.65#ibcon#enter sib2, iclass 27, count 0 2006.246.07:47:42.65#ibcon#flushed, iclass 27, count 0 2006.246.07:47:42.65#ibcon#about to write, iclass 27, count 0 2006.246.07:47:42.65#ibcon#wrote, iclass 27, count 0 2006.246.07:47:42.65#ibcon#about to read 3, iclass 27, count 0 2006.246.07:47:42.68#ibcon#read 3, iclass 27, count 0 2006.246.07:47:42.68#ibcon#about to read 4, iclass 27, count 0 2006.246.07:47:42.68#ibcon#read 4, iclass 27, count 0 2006.246.07:47:42.68#ibcon#about to read 5, iclass 27, count 0 2006.246.07:47:42.68#ibcon#read 5, iclass 27, count 0 2006.246.07:47:42.68#ibcon#about to read 6, iclass 27, count 0 2006.246.07:47:42.68#ibcon#read 6, iclass 27, count 0 2006.246.07:47:42.68#ibcon#end of sib2, iclass 27, count 0 2006.246.07:47:42.68#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:47:42.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:47:42.68#ibcon#[25=BW32\r\n] 2006.246.07:47:42.68#ibcon#*before write, iclass 27, count 0 2006.246.07:47:42.68#ibcon#enter sib2, iclass 27, count 0 2006.246.07:47:42.68#ibcon#flushed, iclass 27, count 0 2006.246.07:47:42.68#ibcon#about to write, iclass 27, count 0 2006.246.07:47:42.68#ibcon#wrote, iclass 27, count 0 2006.246.07:47:42.68#ibcon#about to read 3, iclass 27, count 0 2006.246.07:47:42.71#ibcon#read 3, iclass 27, count 0 2006.246.07:47:42.71#ibcon#about to read 4, iclass 27, count 0 2006.246.07:47:42.71#ibcon#read 4, iclass 27, count 0 2006.246.07:47:42.71#ibcon#about to read 5, iclass 27, count 0 2006.246.07:47:42.71#ibcon#read 5, iclass 27, count 0 2006.246.07:47:42.71#ibcon#about to read 6, iclass 27, count 0 2006.246.07:47:42.71#ibcon#read 6, iclass 27, count 0 2006.246.07:47:42.71#ibcon#end of sib2, iclass 27, count 0 2006.246.07:47:42.71#ibcon#*after write, iclass 27, count 0 2006.246.07:47:42.71#ibcon#*before return 0, iclass 27, count 0 2006.246.07:47:42.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:42.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:47:42.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:47:42.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:47:42.71$vc4f8/vbbw=wide 2006.246.07:47:42.71#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:47:42.71#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:47:42.71#ibcon#ireg 8 cls_cnt 0 2006.246.07:47:42.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:47:42.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:47:42.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:47:42.77#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:47:42.77#ibcon#first serial, iclass 29, count 0 2006.246.07:47:42.77#ibcon#enter sib2, iclass 29, count 0 2006.246.07:47:42.77#ibcon#flushed, iclass 29, count 0 2006.246.07:47:42.77#ibcon#about to write, iclass 29, count 0 2006.246.07:47:42.77#ibcon#wrote, iclass 29, count 0 2006.246.07:47:42.77#ibcon#about to read 3, iclass 29, count 0 2006.246.07:47:42.79#ibcon#read 3, iclass 29, count 0 2006.246.07:47:42.79#ibcon#about to read 4, iclass 29, count 0 2006.246.07:47:42.79#ibcon#read 4, iclass 29, count 0 2006.246.07:47:42.79#ibcon#about to read 5, iclass 29, count 0 2006.246.07:47:42.79#ibcon#read 5, iclass 29, count 0 2006.246.07:47:42.79#ibcon#about to read 6, iclass 29, count 0 2006.246.07:47:42.79#ibcon#read 6, iclass 29, count 0 2006.246.07:47:42.79#ibcon#end of sib2, iclass 29, count 0 2006.246.07:47:42.79#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:47:42.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:47:42.79#ibcon#[27=BW32\r\n] 2006.246.07:47:42.79#ibcon#*before write, iclass 29, count 0 2006.246.07:47:42.79#ibcon#enter sib2, iclass 29, count 0 2006.246.07:47:42.79#ibcon#flushed, iclass 29, count 0 2006.246.07:47:42.79#ibcon#about to write, iclass 29, count 0 2006.246.07:47:42.79#ibcon#wrote, iclass 29, count 0 2006.246.07:47:42.79#ibcon#about to read 3, iclass 29, count 0 2006.246.07:47:42.82#ibcon#read 3, iclass 29, count 0 2006.246.07:47:42.82#ibcon#about to read 4, iclass 29, count 0 2006.246.07:47:42.82#ibcon#read 4, iclass 29, count 0 2006.246.07:47:42.82#ibcon#about to read 5, iclass 29, count 0 2006.246.07:47:42.82#ibcon#read 5, iclass 29, count 0 2006.246.07:47:42.82#ibcon#about to read 6, iclass 29, count 0 2006.246.07:47:42.82#ibcon#read 6, iclass 29, count 0 2006.246.07:47:42.82#ibcon#end of sib2, iclass 29, count 0 2006.246.07:47:42.82#ibcon#*after write, iclass 29, count 0 2006.246.07:47:42.82#ibcon#*before return 0, iclass 29, count 0 2006.246.07:47:42.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:47:42.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:47:42.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:47:42.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:47:42.82$4f8m12a/ifd4f 2006.246.07:47:42.82$ifd4f/lo= 2006.246.07:47:42.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:47:42.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:47:42.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:47:42.82$ifd4f/patch= 2006.246.07:47:42.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:47:42.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:47:42.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:47:42.82$4f8m12a/"form=m,16.000,1:2 2006.246.07:47:42.82$4f8m12a/"tpicd 2006.246.07:47:42.82$4f8m12a/echo=off 2006.246.07:47:42.82$4f8m12a/xlog=off 2006.246.07:47:42.82:!2006.246.07:48:10 2006.246.07:47:54.14#trakl#Source acquired 2006.246.07:47:55.14#flagr#flagr/antenna,acquired 2006.246.07:48:10.00:preob 2006.246.07:48:11.14/onsource/TRACKING 2006.246.07:48:11.14:!2006.246.07:48:20 2006.246.07:48:20.00:data_valid=on 2006.246.07:48:20.00:midob 2006.246.07:48:20.14/onsource/TRACKING 2006.246.07:48:20.14/wx/26.74,1005.7,75 2006.246.07:48:20.26/cable/+6.4141E-03 2006.246.07:48:21.35/va/01,08,usb,yes,31,33 2006.246.07:48:21.35/va/02,07,usb,yes,31,32 2006.246.07:48:21.35/va/03,06,usb,yes,33,33 2006.246.07:48:21.35/va/04,07,usb,yes,32,34 2006.246.07:48:21.35/va/05,07,usb,yes,34,35 2006.246.07:48:21.35/va/06,07,usb,yes,29,29 2006.246.07:48:21.35/va/07,07,usb,yes,29,29 2006.246.07:48:21.35/va/08,08,usb,yes,25,25 2006.246.07:48:21.58/valo/01,532.99,yes,locked 2006.246.07:48:21.58/valo/02,572.99,yes,locked 2006.246.07:48:21.58/valo/03,672.99,yes,locked 2006.246.07:48:21.58/valo/04,832.99,yes,locked 2006.246.07:48:21.58/valo/05,652.99,yes,locked 2006.246.07:48:21.58/valo/06,772.99,yes,locked 2006.246.07:48:21.58/valo/07,832.99,yes,locked 2006.246.07:48:21.58/valo/08,852.99,yes,locked 2006.246.07:48:22.67/vb/01,04,usb,yes,30,29 2006.246.07:48:22.67/vb/02,04,usb,yes,32,34 2006.246.07:48:22.67/vb/03,04,usb,yes,28,32 2006.246.07:48:22.67/vb/04,04,usb,yes,29,29 2006.246.07:48:22.67/vb/05,03,usb,yes,35,39 2006.246.07:48:22.67/vb/06,03,usb,yes,35,39 2006.246.07:48:22.67/vb/07,04,usb,yes,31,31 2006.246.07:48:22.67/vb/08,03,usb,yes,35,39 2006.246.07:48:22.91/vblo/01,632.99,yes,locked 2006.246.07:48:22.91/vblo/02,640.99,yes,locked 2006.246.07:48:22.91/vblo/03,656.99,yes,locked 2006.246.07:48:22.91/vblo/04,712.99,yes,locked 2006.246.07:48:22.91/vblo/05,744.99,yes,locked 2006.246.07:48:22.91/vblo/06,752.99,yes,locked 2006.246.07:48:22.91/vblo/07,734.99,yes,locked 2006.246.07:48:22.91/vblo/08,744.99,yes,locked 2006.246.07:48:23.06/vabw/8 2006.246.07:48:23.21/vbbw/8 2006.246.07:48:23.34/xfe/off,on,13.2 2006.246.07:48:23.71/ifatt/23,28,28,28 2006.246.07:48:24.07/fmout-gps/S +4.36E-07 2006.246.07:48:24.11:!2006.246.07:49:20 2006.246.07:49:20.00:data_valid=off 2006.246.07:49:20.01:postob 2006.246.07:49:20.22/cable/+6.4132E-03 2006.246.07:49:20.23/wx/26.74,1005.7,75 2006.246.07:49:21.07/fmout-gps/S +4.37E-07 2006.246.07:49:21.08:scan_name=246-0750,k06246,80 2006.246.07:49:21.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.246.07:49:21.14#flagr#flagr/antenna,new-source 2006.246.07:49:22.14:checkk5 2006.246.07:49:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:49:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:49:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:49:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:49:24.03/chk_obsdata//k5ts1/T2460748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:49:24.39/chk_obsdata//k5ts2/T2460748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:49:24.75/chk_obsdata//k5ts3/T2460748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:49:25.12/chk_obsdata//k5ts4/T2460748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:49:25.82/k5log//k5ts1_log_newline 2006.246.07:49:26.52/k5log//k5ts2_log_newline 2006.246.07:49:27.20/k5log//k5ts3_log_newline 2006.246.07:49:27.89/k5log//k5ts4_log_newline 2006.246.07:49:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:49:27.92:4f8m12a=1 2006.246.07:49:27.92$4f8m12a/echo=on 2006.246.07:49:27.92$4f8m12a/pcalon 2006.246.07:49:27.92$pcalon/"no phase cal control is implemented here 2006.246.07:49:27.92$4f8m12a/"tpicd=stop 2006.246.07:49:27.92$4f8m12a/vc4f8 2006.246.07:49:27.92$vc4f8/valo=1,532.99 2006.246.07:49:27.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:49:27.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:49:27.92#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:27.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:27.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:27.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:27.92#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:49:27.92#ibcon#first serial, iclass 40, count 0 2006.246.07:49:27.92#ibcon#enter sib2, iclass 40, count 0 2006.246.07:49:27.92#ibcon#flushed, iclass 40, count 0 2006.246.07:49:27.92#ibcon#about to write, iclass 40, count 0 2006.246.07:49:27.92#ibcon#wrote, iclass 40, count 0 2006.246.07:49:27.92#ibcon#about to read 3, iclass 40, count 0 2006.246.07:49:27.96#ibcon#read 3, iclass 40, count 0 2006.246.07:49:27.96#ibcon#about to read 4, iclass 40, count 0 2006.246.07:49:27.96#ibcon#read 4, iclass 40, count 0 2006.246.07:49:27.96#ibcon#about to read 5, iclass 40, count 0 2006.246.07:49:27.96#ibcon#read 5, iclass 40, count 0 2006.246.07:49:27.96#ibcon#about to read 6, iclass 40, count 0 2006.246.07:49:27.96#ibcon#read 6, iclass 40, count 0 2006.246.07:49:27.96#ibcon#end of sib2, iclass 40, count 0 2006.246.07:49:27.96#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:49:27.96#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:49:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:49:27.96#ibcon#*before write, iclass 40, count 0 2006.246.07:49:27.96#ibcon#enter sib2, iclass 40, count 0 2006.246.07:49:27.96#ibcon#flushed, iclass 40, count 0 2006.246.07:49:27.96#ibcon#about to write, iclass 40, count 0 2006.246.07:49:27.96#ibcon#wrote, iclass 40, count 0 2006.246.07:49:27.96#ibcon#about to read 3, iclass 40, count 0 2006.246.07:49:28.01#ibcon#read 3, iclass 40, count 0 2006.246.07:49:28.01#ibcon#about to read 4, iclass 40, count 0 2006.246.07:49:28.01#ibcon#read 4, iclass 40, count 0 2006.246.07:49:28.01#ibcon#about to read 5, iclass 40, count 0 2006.246.07:49:28.01#ibcon#read 5, iclass 40, count 0 2006.246.07:49:28.01#ibcon#about to read 6, iclass 40, count 0 2006.246.07:49:28.01#ibcon#read 6, iclass 40, count 0 2006.246.07:49:28.01#ibcon#end of sib2, iclass 40, count 0 2006.246.07:49:28.01#ibcon#*after write, iclass 40, count 0 2006.246.07:49:28.01#ibcon#*before return 0, iclass 40, count 0 2006.246.07:49:28.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:28.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:28.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:49:28.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:49:28.01$vc4f8/va=1,8 2006.246.07:49:28.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.07:49:28.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.07:49:28.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:28.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:28.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:28.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:28.01#ibcon#enter wrdev, iclass 4, count 2 2006.246.07:49:28.01#ibcon#first serial, iclass 4, count 2 2006.246.07:49:28.01#ibcon#enter sib2, iclass 4, count 2 2006.246.07:49:28.01#ibcon#flushed, iclass 4, count 2 2006.246.07:49:28.01#ibcon#about to write, iclass 4, count 2 2006.246.07:49:28.01#ibcon#wrote, iclass 4, count 2 2006.246.07:49:28.01#ibcon#about to read 3, iclass 4, count 2 2006.246.07:49:28.04#ibcon#read 3, iclass 4, count 2 2006.246.07:49:28.04#ibcon#about to read 4, iclass 4, count 2 2006.246.07:49:28.04#ibcon#read 4, iclass 4, count 2 2006.246.07:49:28.04#ibcon#about to read 5, iclass 4, count 2 2006.246.07:49:28.04#ibcon#read 5, iclass 4, count 2 2006.246.07:49:28.04#ibcon#about to read 6, iclass 4, count 2 2006.246.07:49:28.04#ibcon#read 6, iclass 4, count 2 2006.246.07:49:28.04#ibcon#end of sib2, iclass 4, count 2 2006.246.07:49:28.04#ibcon#*mode == 0, iclass 4, count 2 2006.246.07:49:28.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.07:49:28.04#ibcon#[25=AT01-08\r\n] 2006.246.07:49:28.04#ibcon#*before write, iclass 4, count 2 2006.246.07:49:28.04#ibcon#enter sib2, iclass 4, count 2 2006.246.07:49:28.04#ibcon#flushed, iclass 4, count 2 2006.246.07:49:28.04#ibcon#about to write, iclass 4, count 2 2006.246.07:49:28.04#ibcon#wrote, iclass 4, count 2 2006.246.07:49:28.04#ibcon#about to read 3, iclass 4, count 2 2006.246.07:49:28.07#ibcon#read 3, iclass 4, count 2 2006.246.07:49:28.07#ibcon#about to read 4, iclass 4, count 2 2006.246.07:49:28.07#ibcon#read 4, iclass 4, count 2 2006.246.07:49:28.07#ibcon#about to read 5, iclass 4, count 2 2006.246.07:49:28.07#ibcon#read 5, iclass 4, count 2 2006.246.07:49:28.07#ibcon#about to read 6, iclass 4, count 2 2006.246.07:49:28.07#ibcon#read 6, iclass 4, count 2 2006.246.07:49:28.07#ibcon#end of sib2, iclass 4, count 2 2006.246.07:49:28.07#ibcon#*after write, iclass 4, count 2 2006.246.07:49:28.07#ibcon#*before return 0, iclass 4, count 2 2006.246.07:49:28.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:28.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:28.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.07:49:28.07#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:28.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:28.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:28.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:28.19#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:49:28.19#ibcon#first serial, iclass 4, count 0 2006.246.07:49:28.19#ibcon#enter sib2, iclass 4, count 0 2006.246.07:49:28.19#ibcon#flushed, iclass 4, count 0 2006.246.07:49:28.19#ibcon#about to write, iclass 4, count 0 2006.246.07:49:28.19#ibcon#wrote, iclass 4, count 0 2006.246.07:49:28.19#ibcon#about to read 3, iclass 4, count 0 2006.246.07:49:28.21#ibcon#read 3, iclass 4, count 0 2006.246.07:49:28.21#ibcon#about to read 4, iclass 4, count 0 2006.246.07:49:28.21#ibcon#read 4, iclass 4, count 0 2006.246.07:49:28.21#ibcon#about to read 5, iclass 4, count 0 2006.246.07:49:28.21#ibcon#read 5, iclass 4, count 0 2006.246.07:49:28.21#ibcon#about to read 6, iclass 4, count 0 2006.246.07:49:28.21#ibcon#read 6, iclass 4, count 0 2006.246.07:49:28.21#ibcon#end of sib2, iclass 4, count 0 2006.246.07:49:28.21#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:49:28.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:49:28.21#ibcon#[25=USB\r\n] 2006.246.07:49:28.21#ibcon#*before write, iclass 4, count 0 2006.246.07:49:28.21#ibcon#enter sib2, iclass 4, count 0 2006.246.07:49:28.21#ibcon#flushed, iclass 4, count 0 2006.246.07:49:28.21#ibcon#about to write, iclass 4, count 0 2006.246.07:49:28.21#ibcon#wrote, iclass 4, count 0 2006.246.07:49:28.21#ibcon#about to read 3, iclass 4, count 0 2006.246.07:49:28.24#ibcon#read 3, iclass 4, count 0 2006.246.07:49:28.24#ibcon#about to read 4, iclass 4, count 0 2006.246.07:49:28.24#ibcon#read 4, iclass 4, count 0 2006.246.07:49:28.24#ibcon#about to read 5, iclass 4, count 0 2006.246.07:49:28.24#ibcon#read 5, iclass 4, count 0 2006.246.07:49:28.24#ibcon#about to read 6, iclass 4, count 0 2006.246.07:49:28.24#ibcon#read 6, iclass 4, count 0 2006.246.07:49:28.24#ibcon#end of sib2, iclass 4, count 0 2006.246.07:49:28.24#ibcon#*after write, iclass 4, count 0 2006.246.07:49:28.24#ibcon#*before return 0, iclass 4, count 0 2006.246.07:49:28.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:28.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:28.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:49:28.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:49:28.24$vc4f8/valo=2,572.99 2006.246.07:49:28.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.07:49:28.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.07:49:28.24#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:28.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:28.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:28.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:28.24#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:49:28.24#ibcon#first serial, iclass 6, count 0 2006.246.07:49:28.24#ibcon#enter sib2, iclass 6, count 0 2006.246.07:49:28.24#ibcon#flushed, iclass 6, count 0 2006.246.07:49:28.24#ibcon#about to write, iclass 6, count 0 2006.246.07:49:28.24#ibcon#wrote, iclass 6, count 0 2006.246.07:49:28.24#ibcon#about to read 3, iclass 6, count 0 2006.246.07:49:28.26#ibcon#read 3, iclass 6, count 0 2006.246.07:49:28.26#ibcon#about to read 4, iclass 6, count 0 2006.246.07:49:28.26#ibcon#read 4, iclass 6, count 0 2006.246.07:49:28.26#ibcon#about to read 5, iclass 6, count 0 2006.246.07:49:28.26#ibcon#read 5, iclass 6, count 0 2006.246.07:49:28.26#ibcon#about to read 6, iclass 6, count 0 2006.246.07:49:28.26#ibcon#read 6, iclass 6, count 0 2006.246.07:49:28.26#ibcon#end of sib2, iclass 6, count 0 2006.246.07:49:28.26#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:49:28.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:49:28.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:49:28.26#ibcon#*before write, iclass 6, count 0 2006.246.07:49:28.26#ibcon#enter sib2, iclass 6, count 0 2006.246.07:49:28.26#ibcon#flushed, iclass 6, count 0 2006.246.07:49:28.26#ibcon#about to write, iclass 6, count 0 2006.246.07:49:28.26#ibcon#wrote, iclass 6, count 0 2006.246.07:49:28.26#ibcon#about to read 3, iclass 6, count 0 2006.246.07:49:28.30#ibcon#read 3, iclass 6, count 0 2006.246.07:49:28.30#ibcon#about to read 4, iclass 6, count 0 2006.246.07:49:28.30#ibcon#read 4, iclass 6, count 0 2006.246.07:49:28.30#ibcon#about to read 5, iclass 6, count 0 2006.246.07:49:28.30#ibcon#read 5, iclass 6, count 0 2006.246.07:49:28.30#ibcon#about to read 6, iclass 6, count 0 2006.246.07:49:28.30#ibcon#read 6, iclass 6, count 0 2006.246.07:49:28.30#ibcon#end of sib2, iclass 6, count 0 2006.246.07:49:28.30#ibcon#*after write, iclass 6, count 0 2006.246.07:49:28.30#ibcon#*before return 0, iclass 6, count 0 2006.246.07:49:28.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:28.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:28.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:49:28.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:49:28.30$vc4f8/va=2,7 2006.246.07:49:28.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.07:49:28.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.07:49:28.30#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:28.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:28.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:28.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:28.36#ibcon#enter wrdev, iclass 10, count 2 2006.246.07:49:28.36#ibcon#first serial, iclass 10, count 2 2006.246.07:49:28.36#ibcon#enter sib2, iclass 10, count 2 2006.246.07:49:28.36#ibcon#flushed, iclass 10, count 2 2006.246.07:49:28.36#ibcon#about to write, iclass 10, count 2 2006.246.07:49:28.36#ibcon#wrote, iclass 10, count 2 2006.246.07:49:28.36#ibcon#about to read 3, iclass 10, count 2 2006.246.07:49:28.38#ibcon#read 3, iclass 10, count 2 2006.246.07:49:28.38#ibcon#about to read 4, iclass 10, count 2 2006.246.07:49:28.38#ibcon#read 4, iclass 10, count 2 2006.246.07:49:28.38#ibcon#about to read 5, iclass 10, count 2 2006.246.07:49:28.38#ibcon#read 5, iclass 10, count 2 2006.246.07:49:28.38#ibcon#about to read 6, iclass 10, count 2 2006.246.07:49:28.38#ibcon#read 6, iclass 10, count 2 2006.246.07:49:28.38#ibcon#end of sib2, iclass 10, count 2 2006.246.07:49:28.38#ibcon#*mode == 0, iclass 10, count 2 2006.246.07:49:28.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.07:49:28.38#ibcon#[25=AT02-07\r\n] 2006.246.07:49:28.38#ibcon#*before write, iclass 10, count 2 2006.246.07:49:28.38#ibcon#enter sib2, iclass 10, count 2 2006.246.07:49:28.38#ibcon#flushed, iclass 10, count 2 2006.246.07:49:28.38#ibcon#about to write, iclass 10, count 2 2006.246.07:49:28.38#ibcon#wrote, iclass 10, count 2 2006.246.07:49:28.38#ibcon#about to read 3, iclass 10, count 2 2006.246.07:49:28.41#ibcon#read 3, iclass 10, count 2 2006.246.07:49:28.41#ibcon#about to read 4, iclass 10, count 2 2006.246.07:49:28.41#ibcon#read 4, iclass 10, count 2 2006.246.07:49:28.41#ibcon#about to read 5, iclass 10, count 2 2006.246.07:49:28.41#ibcon#read 5, iclass 10, count 2 2006.246.07:49:28.41#ibcon#about to read 6, iclass 10, count 2 2006.246.07:49:28.41#ibcon#read 6, iclass 10, count 2 2006.246.07:49:28.41#ibcon#end of sib2, iclass 10, count 2 2006.246.07:49:28.41#ibcon#*after write, iclass 10, count 2 2006.246.07:49:28.41#ibcon#*before return 0, iclass 10, count 2 2006.246.07:49:28.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:28.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:28.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.07:49:28.41#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:28.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:28.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:28.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:28.54#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:49:28.54#ibcon#first serial, iclass 10, count 0 2006.246.07:49:28.54#ibcon#enter sib2, iclass 10, count 0 2006.246.07:49:28.54#ibcon#flushed, iclass 10, count 0 2006.246.07:49:28.54#ibcon#about to write, iclass 10, count 0 2006.246.07:49:28.54#ibcon#wrote, iclass 10, count 0 2006.246.07:49:28.54#ibcon#about to read 3, iclass 10, count 0 2006.246.07:49:28.55#ibcon#read 3, iclass 10, count 0 2006.246.07:49:28.55#ibcon#about to read 4, iclass 10, count 0 2006.246.07:49:28.55#ibcon#read 4, iclass 10, count 0 2006.246.07:49:28.55#ibcon#about to read 5, iclass 10, count 0 2006.246.07:49:28.55#ibcon#read 5, iclass 10, count 0 2006.246.07:49:28.55#ibcon#about to read 6, iclass 10, count 0 2006.246.07:49:28.55#ibcon#read 6, iclass 10, count 0 2006.246.07:49:28.55#ibcon#end of sib2, iclass 10, count 0 2006.246.07:49:28.55#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:49:28.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:49:28.55#ibcon#[25=USB\r\n] 2006.246.07:49:28.55#ibcon#*before write, iclass 10, count 0 2006.246.07:49:28.55#ibcon#enter sib2, iclass 10, count 0 2006.246.07:49:28.55#ibcon#flushed, iclass 10, count 0 2006.246.07:49:28.55#ibcon#about to write, iclass 10, count 0 2006.246.07:49:28.55#ibcon#wrote, iclass 10, count 0 2006.246.07:49:28.55#ibcon#about to read 3, iclass 10, count 0 2006.246.07:49:28.58#ibcon#read 3, iclass 10, count 0 2006.246.07:49:28.58#ibcon#about to read 4, iclass 10, count 0 2006.246.07:49:28.58#ibcon#read 4, iclass 10, count 0 2006.246.07:49:28.58#ibcon#about to read 5, iclass 10, count 0 2006.246.07:49:28.58#ibcon#read 5, iclass 10, count 0 2006.246.07:49:28.58#ibcon#about to read 6, iclass 10, count 0 2006.246.07:49:28.58#ibcon#read 6, iclass 10, count 0 2006.246.07:49:28.58#ibcon#end of sib2, iclass 10, count 0 2006.246.07:49:28.58#ibcon#*after write, iclass 10, count 0 2006.246.07:49:28.58#ibcon#*before return 0, iclass 10, count 0 2006.246.07:49:28.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:28.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:28.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:49:28.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:49:28.58$vc4f8/valo=3,672.99 2006.246.07:49:28.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.07:49:28.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.07:49:28.58#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:28.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:28.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:28.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:28.58#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:49:28.58#ibcon#first serial, iclass 12, count 0 2006.246.07:49:28.58#ibcon#enter sib2, iclass 12, count 0 2006.246.07:49:28.58#ibcon#flushed, iclass 12, count 0 2006.246.07:49:28.58#ibcon#about to write, iclass 12, count 0 2006.246.07:49:28.58#ibcon#wrote, iclass 12, count 0 2006.246.07:49:28.58#ibcon#about to read 3, iclass 12, count 0 2006.246.07:49:28.61#ibcon#read 3, iclass 12, count 0 2006.246.07:49:28.61#ibcon#about to read 4, iclass 12, count 0 2006.246.07:49:28.61#ibcon#read 4, iclass 12, count 0 2006.246.07:49:28.61#ibcon#about to read 5, iclass 12, count 0 2006.246.07:49:28.61#ibcon#read 5, iclass 12, count 0 2006.246.07:49:28.61#ibcon#about to read 6, iclass 12, count 0 2006.246.07:49:28.61#ibcon#read 6, iclass 12, count 0 2006.246.07:49:28.61#ibcon#end of sib2, iclass 12, count 0 2006.246.07:49:28.61#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:49:28.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:49:28.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:49:28.61#ibcon#*before write, iclass 12, count 0 2006.246.07:49:28.61#ibcon#enter sib2, iclass 12, count 0 2006.246.07:49:28.61#ibcon#flushed, iclass 12, count 0 2006.246.07:49:28.61#ibcon#about to write, iclass 12, count 0 2006.246.07:49:28.61#ibcon#wrote, iclass 12, count 0 2006.246.07:49:28.61#ibcon#about to read 3, iclass 12, count 0 2006.246.07:49:28.65#ibcon#read 3, iclass 12, count 0 2006.246.07:49:28.65#ibcon#about to read 4, iclass 12, count 0 2006.246.07:49:28.65#ibcon#read 4, iclass 12, count 0 2006.246.07:49:28.65#ibcon#about to read 5, iclass 12, count 0 2006.246.07:49:28.65#ibcon#read 5, iclass 12, count 0 2006.246.07:49:28.65#ibcon#about to read 6, iclass 12, count 0 2006.246.07:49:28.65#ibcon#read 6, iclass 12, count 0 2006.246.07:49:28.65#ibcon#end of sib2, iclass 12, count 0 2006.246.07:49:28.65#ibcon#*after write, iclass 12, count 0 2006.246.07:49:28.65#ibcon#*before return 0, iclass 12, count 0 2006.246.07:49:28.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:28.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:28.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:49:28.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:49:28.65$vc4f8/va=3,6 2006.246.07:49:28.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.07:49:28.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.07:49:28.65#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:28.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:28.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:28.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:28.70#ibcon#enter wrdev, iclass 14, count 2 2006.246.07:49:28.70#ibcon#first serial, iclass 14, count 2 2006.246.07:49:28.70#ibcon#enter sib2, iclass 14, count 2 2006.246.07:49:28.70#ibcon#flushed, iclass 14, count 2 2006.246.07:49:28.70#ibcon#about to write, iclass 14, count 2 2006.246.07:49:28.70#ibcon#wrote, iclass 14, count 2 2006.246.07:49:28.70#ibcon#about to read 3, iclass 14, count 2 2006.246.07:49:28.72#ibcon#read 3, iclass 14, count 2 2006.246.07:49:28.72#ibcon#about to read 4, iclass 14, count 2 2006.246.07:49:28.72#ibcon#read 4, iclass 14, count 2 2006.246.07:49:28.72#ibcon#about to read 5, iclass 14, count 2 2006.246.07:49:28.72#ibcon#read 5, iclass 14, count 2 2006.246.07:49:28.72#ibcon#about to read 6, iclass 14, count 2 2006.246.07:49:28.72#ibcon#read 6, iclass 14, count 2 2006.246.07:49:28.72#ibcon#end of sib2, iclass 14, count 2 2006.246.07:49:28.72#ibcon#*mode == 0, iclass 14, count 2 2006.246.07:49:28.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.07:49:28.72#ibcon#[25=AT03-06\r\n] 2006.246.07:49:28.72#ibcon#*before write, iclass 14, count 2 2006.246.07:49:28.72#ibcon#enter sib2, iclass 14, count 2 2006.246.07:49:28.72#ibcon#flushed, iclass 14, count 2 2006.246.07:49:28.72#ibcon#about to write, iclass 14, count 2 2006.246.07:49:28.72#ibcon#wrote, iclass 14, count 2 2006.246.07:49:28.72#ibcon#about to read 3, iclass 14, count 2 2006.246.07:49:28.75#ibcon#read 3, iclass 14, count 2 2006.246.07:49:28.75#ibcon#about to read 4, iclass 14, count 2 2006.246.07:49:28.75#ibcon#read 4, iclass 14, count 2 2006.246.07:49:28.75#ibcon#about to read 5, iclass 14, count 2 2006.246.07:49:28.75#ibcon#read 5, iclass 14, count 2 2006.246.07:49:28.75#ibcon#about to read 6, iclass 14, count 2 2006.246.07:49:28.75#ibcon#read 6, iclass 14, count 2 2006.246.07:49:28.75#ibcon#end of sib2, iclass 14, count 2 2006.246.07:49:28.75#ibcon#*after write, iclass 14, count 2 2006.246.07:49:28.75#ibcon#*before return 0, iclass 14, count 2 2006.246.07:49:28.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:28.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:28.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.07:49:28.75#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:28.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:28.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:28.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:28.87#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:49:28.87#ibcon#first serial, iclass 14, count 0 2006.246.07:49:28.87#ibcon#enter sib2, iclass 14, count 0 2006.246.07:49:28.87#ibcon#flushed, iclass 14, count 0 2006.246.07:49:28.87#ibcon#about to write, iclass 14, count 0 2006.246.07:49:28.87#ibcon#wrote, iclass 14, count 0 2006.246.07:49:28.87#ibcon#about to read 3, iclass 14, count 0 2006.246.07:49:28.89#ibcon#read 3, iclass 14, count 0 2006.246.07:49:28.89#ibcon#about to read 4, iclass 14, count 0 2006.246.07:49:28.89#ibcon#read 4, iclass 14, count 0 2006.246.07:49:28.89#ibcon#about to read 5, iclass 14, count 0 2006.246.07:49:28.89#ibcon#read 5, iclass 14, count 0 2006.246.07:49:28.89#ibcon#about to read 6, iclass 14, count 0 2006.246.07:49:28.89#ibcon#read 6, iclass 14, count 0 2006.246.07:49:28.89#ibcon#end of sib2, iclass 14, count 0 2006.246.07:49:28.89#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:49:28.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:49:28.89#ibcon#[25=USB\r\n] 2006.246.07:49:28.89#ibcon#*before write, iclass 14, count 0 2006.246.07:49:28.89#ibcon#enter sib2, iclass 14, count 0 2006.246.07:49:28.89#ibcon#flushed, iclass 14, count 0 2006.246.07:49:28.89#ibcon#about to write, iclass 14, count 0 2006.246.07:49:28.89#ibcon#wrote, iclass 14, count 0 2006.246.07:49:28.89#ibcon#about to read 3, iclass 14, count 0 2006.246.07:49:28.92#ibcon#read 3, iclass 14, count 0 2006.246.07:49:28.92#ibcon#about to read 4, iclass 14, count 0 2006.246.07:49:28.92#ibcon#read 4, iclass 14, count 0 2006.246.07:49:28.92#ibcon#about to read 5, iclass 14, count 0 2006.246.07:49:28.92#ibcon#read 5, iclass 14, count 0 2006.246.07:49:28.92#ibcon#about to read 6, iclass 14, count 0 2006.246.07:49:28.92#ibcon#read 6, iclass 14, count 0 2006.246.07:49:28.92#ibcon#end of sib2, iclass 14, count 0 2006.246.07:49:28.92#ibcon#*after write, iclass 14, count 0 2006.246.07:49:28.92#ibcon#*before return 0, iclass 14, count 0 2006.246.07:49:28.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:28.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:28.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:49:28.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:49:28.92$vc4f8/valo=4,832.99 2006.246.07:49:28.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.07:49:28.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.07:49:28.92#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:28.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:28.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:28.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:28.92#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:49:28.92#ibcon#first serial, iclass 16, count 0 2006.246.07:49:28.92#ibcon#enter sib2, iclass 16, count 0 2006.246.07:49:28.92#ibcon#flushed, iclass 16, count 0 2006.246.07:49:28.92#ibcon#about to write, iclass 16, count 0 2006.246.07:49:28.92#ibcon#wrote, iclass 16, count 0 2006.246.07:49:28.92#ibcon#about to read 3, iclass 16, count 0 2006.246.07:49:28.94#ibcon#read 3, iclass 16, count 0 2006.246.07:49:28.94#ibcon#about to read 4, iclass 16, count 0 2006.246.07:49:28.94#ibcon#read 4, iclass 16, count 0 2006.246.07:49:28.94#ibcon#about to read 5, iclass 16, count 0 2006.246.07:49:28.94#ibcon#read 5, iclass 16, count 0 2006.246.07:49:28.94#ibcon#about to read 6, iclass 16, count 0 2006.246.07:49:28.94#ibcon#read 6, iclass 16, count 0 2006.246.07:49:28.94#ibcon#end of sib2, iclass 16, count 0 2006.246.07:49:28.94#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:49:28.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:49:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:49:28.94#ibcon#*before write, iclass 16, count 0 2006.246.07:49:28.94#ibcon#enter sib2, iclass 16, count 0 2006.246.07:49:28.94#ibcon#flushed, iclass 16, count 0 2006.246.07:49:28.94#ibcon#about to write, iclass 16, count 0 2006.246.07:49:28.94#ibcon#wrote, iclass 16, count 0 2006.246.07:49:28.94#ibcon#about to read 3, iclass 16, count 0 2006.246.07:49:28.98#ibcon#read 3, iclass 16, count 0 2006.246.07:49:28.98#ibcon#about to read 4, iclass 16, count 0 2006.246.07:49:28.98#ibcon#read 4, iclass 16, count 0 2006.246.07:49:28.98#ibcon#about to read 5, iclass 16, count 0 2006.246.07:49:28.98#ibcon#read 5, iclass 16, count 0 2006.246.07:49:28.98#ibcon#about to read 6, iclass 16, count 0 2006.246.07:49:28.98#ibcon#read 6, iclass 16, count 0 2006.246.07:49:28.98#ibcon#end of sib2, iclass 16, count 0 2006.246.07:49:28.98#ibcon#*after write, iclass 16, count 0 2006.246.07:49:28.98#ibcon#*before return 0, iclass 16, count 0 2006.246.07:49:28.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:28.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:28.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:49:28.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:49:28.98$vc4f8/va=4,7 2006.246.07:49:28.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.07:49:28.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.07:49:28.98#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:28.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:29.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:29.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:29.04#ibcon#enter wrdev, iclass 18, count 2 2006.246.07:49:29.04#ibcon#first serial, iclass 18, count 2 2006.246.07:49:29.04#ibcon#enter sib2, iclass 18, count 2 2006.246.07:49:29.04#ibcon#flushed, iclass 18, count 2 2006.246.07:49:29.04#ibcon#about to write, iclass 18, count 2 2006.246.07:49:29.04#ibcon#wrote, iclass 18, count 2 2006.246.07:49:29.04#ibcon#about to read 3, iclass 18, count 2 2006.246.07:49:29.06#ibcon#read 3, iclass 18, count 2 2006.246.07:49:29.06#ibcon#about to read 4, iclass 18, count 2 2006.246.07:49:29.06#ibcon#read 4, iclass 18, count 2 2006.246.07:49:29.06#ibcon#about to read 5, iclass 18, count 2 2006.246.07:49:29.06#ibcon#read 5, iclass 18, count 2 2006.246.07:49:29.06#ibcon#about to read 6, iclass 18, count 2 2006.246.07:49:29.06#ibcon#read 6, iclass 18, count 2 2006.246.07:49:29.06#ibcon#end of sib2, iclass 18, count 2 2006.246.07:49:29.06#ibcon#*mode == 0, iclass 18, count 2 2006.246.07:49:29.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.07:49:29.06#ibcon#[25=AT04-07\r\n] 2006.246.07:49:29.06#ibcon#*before write, iclass 18, count 2 2006.246.07:49:29.06#ibcon#enter sib2, iclass 18, count 2 2006.246.07:49:29.06#ibcon#flushed, iclass 18, count 2 2006.246.07:49:29.06#ibcon#about to write, iclass 18, count 2 2006.246.07:49:29.06#ibcon#wrote, iclass 18, count 2 2006.246.07:49:29.06#ibcon#about to read 3, iclass 18, count 2 2006.246.07:49:29.09#ibcon#read 3, iclass 18, count 2 2006.246.07:49:29.09#ibcon#about to read 4, iclass 18, count 2 2006.246.07:49:29.09#ibcon#read 4, iclass 18, count 2 2006.246.07:49:29.09#ibcon#about to read 5, iclass 18, count 2 2006.246.07:49:29.09#ibcon#read 5, iclass 18, count 2 2006.246.07:49:29.09#ibcon#about to read 6, iclass 18, count 2 2006.246.07:49:29.09#ibcon#read 6, iclass 18, count 2 2006.246.07:49:29.09#ibcon#end of sib2, iclass 18, count 2 2006.246.07:49:29.09#ibcon#*after write, iclass 18, count 2 2006.246.07:49:29.09#ibcon#*before return 0, iclass 18, count 2 2006.246.07:49:29.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:29.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:29.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.07:49:29.09#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:29.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:29.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:29.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:29.21#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:49:29.21#ibcon#first serial, iclass 18, count 0 2006.246.07:49:29.21#ibcon#enter sib2, iclass 18, count 0 2006.246.07:49:29.21#ibcon#flushed, iclass 18, count 0 2006.246.07:49:29.21#ibcon#about to write, iclass 18, count 0 2006.246.07:49:29.21#ibcon#wrote, iclass 18, count 0 2006.246.07:49:29.21#ibcon#about to read 3, iclass 18, count 0 2006.246.07:49:29.23#ibcon#read 3, iclass 18, count 0 2006.246.07:49:29.23#ibcon#about to read 4, iclass 18, count 0 2006.246.07:49:29.23#ibcon#read 4, iclass 18, count 0 2006.246.07:49:29.23#ibcon#about to read 5, iclass 18, count 0 2006.246.07:49:29.23#ibcon#read 5, iclass 18, count 0 2006.246.07:49:29.23#ibcon#about to read 6, iclass 18, count 0 2006.246.07:49:29.23#ibcon#read 6, iclass 18, count 0 2006.246.07:49:29.23#ibcon#end of sib2, iclass 18, count 0 2006.246.07:49:29.23#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:49:29.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:49:29.23#ibcon#[25=USB\r\n] 2006.246.07:49:29.23#ibcon#*before write, iclass 18, count 0 2006.246.07:49:29.23#ibcon#enter sib2, iclass 18, count 0 2006.246.07:49:29.23#ibcon#flushed, iclass 18, count 0 2006.246.07:49:29.23#ibcon#about to write, iclass 18, count 0 2006.246.07:49:29.23#ibcon#wrote, iclass 18, count 0 2006.246.07:49:29.23#ibcon#about to read 3, iclass 18, count 0 2006.246.07:49:29.26#ibcon#read 3, iclass 18, count 0 2006.246.07:49:29.26#ibcon#about to read 4, iclass 18, count 0 2006.246.07:49:29.26#ibcon#read 4, iclass 18, count 0 2006.246.07:49:29.26#ibcon#about to read 5, iclass 18, count 0 2006.246.07:49:29.26#ibcon#read 5, iclass 18, count 0 2006.246.07:49:29.26#ibcon#about to read 6, iclass 18, count 0 2006.246.07:49:29.26#ibcon#read 6, iclass 18, count 0 2006.246.07:49:29.26#ibcon#end of sib2, iclass 18, count 0 2006.246.07:49:29.26#ibcon#*after write, iclass 18, count 0 2006.246.07:49:29.26#ibcon#*before return 0, iclass 18, count 0 2006.246.07:49:29.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:29.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:29.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:49:29.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:49:29.26$vc4f8/valo=5,652.99 2006.246.07:49:29.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.07:49:29.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.07:49:29.26#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:29.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:29.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:29.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:29.26#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:49:29.26#ibcon#first serial, iclass 20, count 0 2006.246.07:49:29.26#ibcon#enter sib2, iclass 20, count 0 2006.246.07:49:29.26#ibcon#flushed, iclass 20, count 0 2006.246.07:49:29.26#ibcon#about to write, iclass 20, count 0 2006.246.07:49:29.26#ibcon#wrote, iclass 20, count 0 2006.246.07:49:29.26#ibcon#about to read 3, iclass 20, count 0 2006.246.07:49:29.28#ibcon#read 3, iclass 20, count 0 2006.246.07:49:29.28#ibcon#about to read 4, iclass 20, count 0 2006.246.07:49:29.28#ibcon#read 4, iclass 20, count 0 2006.246.07:49:29.28#ibcon#about to read 5, iclass 20, count 0 2006.246.07:49:29.28#ibcon#read 5, iclass 20, count 0 2006.246.07:49:29.28#ibcon#about to read 6, iclass 20, count 0 2006.246.07:49:29.28#ibcon#read 6, iclass 20, count 0 2006.246.07:49:29.28#ibcon#end of sib2, iclass 20, count 0 2006.246.07:49:29.28#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:49:29.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:49:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:49:29.28#ibcon#*before write, iclass 20, count 0 2006.246.07:49:29.28#ibcon#enter sib2, iclass 20, count 0 2006.246.07:49:29.28#ibcon#flushed, iclass 20, count 0 2006.246.07:49:29.28#ibcon#about to write, iclass 20, count 0 2006.246.07:49:29.28#ibcon#wrote, iclass 20, count 0 2006.246.07:49:29.28#ibcon#about to read 3, iclass 20, count 0 2006.246.07:49:29.32#ibcon#read 3, iclass 20, count 0 2006.246.07:49:29.32#ibcon#about to read 4, iclass 20, count 0 2006.246.07:49:29.32#ibcon#read 4, iclass 20, count 0 2006.246.07:49:29.32#ibcon#about to read 5, iclass 20, count 0 2006.246.07:49:29.32#ibcon#read 5, iclass 20, count 0 2006.246.07:49:29.32#ibcon#about to read 6, iclass 20, count 0 2006.246.07:49:29.32#ibcon#read 6, iclass 20, count 0 2006.246.07:49:29.32#ibcon#end of sib2, iclass 20, count 0 2006.246.07:49:29.32#ibcon#*after write, iclass 20, count 0 2006.246.07:49:29.32#ibcon#*before return 0, iclass 20, count 0 2006.246.07:49:29.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:29.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:29.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:49:29.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:49:29.32$vc4f8/va=5,7 2006.246.07:49:29.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.07:49:29.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.07:49:29.32#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:29.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:29.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:29.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:29.38#ibcon#enter wrdev, iclass 22, count 2 2006.246.07:49:29.38#ibcon#first serial, iclass 22, count 2 2006.246.07:49:29.38#ibcon#enter sib2, iclass 22, count 2 2006.246.07:49:29.38#ibcon#flushed, iclass 22, count 2 2006.246.07:49:29.38#ibcon#about to write, iclass 22, count 2 2006.246.07:49:29.38#ibcon#wrote, iclass 22, count 2 2006.246.07:49:29.38#ibcon#about to read 3, iclass 22, count 2 2006.246.07:49:29.40#ibcon#read 3, iclass 22, count 2 2006.246.07:49:29.40#ibcon#about to read 4, iclass 22, count 2 2006.246.07:49:29.40#ibcon#read 4, iclass 22, count 2 2006.246.07:49:29.40#ibcon#about to read 5, iclass 22, count 2 2006.246.07:49:29.40#ibcon#read 5, iclass 22, count 2 2006.246.07:49:29.40#ibcon#about to read 6, iclass 22, count 2 2006.246.07:49:29.40#ibcon#read 6, iclass 22, count 2 2006.246.07:49:29.40#ibcon#end of sib2, iclass 22, count 2 2006.246.07:49:29.40#ibcon#*mode == 0, iclass 22, count 2 2006.246.07:49:29.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.07:49:29.40#ibcon#[25=AT05-07\r\n] 2006.246.07:49:29.40#ibcon#*before write, iclass 22, count 2 2006.246.07:49:29.40#ibcon#enter sib2, iclass 22, count 2 2006.246.07:49:29.40#ibcon#flushed, iclass 22, count 2 2006.246.07:49:29.40#ibcon#about to write, iclass 22, count 2 2006.246.07:49:29.40#ibcon#wrote, iclass 22, count 2 2006.246.07:49:29.40#ibcon#about to read 3, iclass 22, count 2 2006.246.07:49:29.43#ibcon#read 3, iclass 22, count 2 2006.246.07:49:29.43#ibcon#about to read 4, iclass 22, count 2 2006.246.07:49:29.43#ibcon#read 4, iclass 22, count 2 2006.246.07:49:29.43#ibcon#about to read 5, iclass 22, count 2 2006.246.07:49:29.43#ibcon#read 5, iclass 22, count 2 2006.246.07:49:29.43#ibcon#about to read 6, iclass 22, count 2 2006.246.07:49:29.43#ibcon#read 6, iclass 22, count 2 2006.246.07:49:29.43#ibcon#end of sib2, iclass 22, count 2 2006.246.07:49:29.43#ibcon#*after write, iclass 22, count 2 2006.246.07:49:29.43#ibcon#*before return 0, iclass 22, count 2 2006.246.07:49:29.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:29.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:29.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.07:49:29.43#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:29.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:29.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:29.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:29.55#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:49:29.55#ibcon#first serial, iclass 22, count 0 2006.246.07:49:29.55#ibcon#enter sib2, iclass 22, count 0 2006.246.07:49:29.55#ibcon#flushed, iclass 22, count 0 2006.246.07:49:29.55#ibcon#about to write, iclass 22, count 0 2006.246.07:49:29.55#ibcon#wrote, iclass 22, count 0 2006.246.07:49:29.55#ibcon#about to read 3, iclass 22, count 0 2006.246.07:49:29.57#ibcon#read 3, iclass 22, count 0 2006.246.07:49:29.57#ibcon#about to read 4, iclass 22, count 0 2006.246.07:49:29.57#ibcon#read 4, iclass 22, count 0 2006.246.07:49:29.57#ibcon#about to read 5, iclass 22, count 0 2006.246.07:49:29.57#ibcon#read 5, iclass 22, count 0 2006.246.07:49:29.57#ibcon#about to read 6, iclass 22, count 0 2006.246.07:49:29.57#ibcon#read 6, iclass 22, count 0 2006.246.07:49:29.57#ibcon#end of sib2, iclass 22, count 0 2006.246.07:49:29.57#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:49:29.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:49:29.57#ibcon#[25=USB\r\n] 2006.246.07:49:29.57#ibcon#*before write, iclass 22, count 0 2006.246.07:49:29.57#ibcon#enter sib2, iclass 22, count 0 2006.246.07:49:29.57#ibcon#flushed, iclass 22, count 0 2006.246.07:49:29.57#ibcon#about to write, iclass 22, count 0 2006.246.07:49:29.57#ibcon#wrote, iclass 22, count 0 2006.246.07:49:29.57#ibcon#about to read 3, iclass 22, count 0 2006.246.07:49:29.60#ibcon#read 3, iclass 22, count 0 2006.246.07:49:29.60#ibcon#about to read 4, iclass 22, count 0 2006.246.07:49:29.60#ibcon#read 4, iclass 22, count 0 2006.246.07:49:29.60#ibcon#about to read 5, iclass 22, count 0 2006.246.07:49:29.60#ibcon#read 5, iclass 22, count 0 2006.246.07:49:29.60#ibcon#about to read 6, iclass 22, count 0 2006.246.07:49:29.60#ibcon#read 6, iclass 22, count 0 2006.246.07:49:29.60#ibcon#end of sib2, iclass 22, count 0 2006.246.07:49:29.60#ibcon#*after write, iclass 22, count 0 2006.246.07:49:29.60#ibcon#*before return 0, iclass 22, count 0 2006.246.07:49:29.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:29.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:29.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:49:29.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:49:29.60$vc4f8/valo=6,772.99 2006.246.07:49:29.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.07:49:29.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.07:49:29.60#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:29.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:29.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:29.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:29.60#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:49:29.60#ibcon#first serial, iclass 24, count 0 2006.246.07:49:29.60#ibcon#enter sib2, iclass 24, count 0 2006.246.07:49:29.60#ibcon#flushed, iclass 24, count 0 2006.246.07:49:29.60#ibcon#about to write, iclass 24, count 0 2006.246.07:49:29.60#ibcon#wrote, iclass 24, count 0 2006.246.07:49:29.60#ibcon#about to read 3, iclass 24, count 0 2006.246.07:49:29.62#ibcon#read 3, iclass 24, count 0 2006.246.07:49:29.62#ibcon#about to read 4, iclass 24, count 0 2006.246.07:49:29.62#ibcon#read 4, iclass 24, count 0 2006.246.07:49:29.62#ibcon#about to read 5, iclass 24, count 0 2006.246.07:49:29.62#ibcon#read 5, iclass 24, count 0 2006.246.07:49:29.62#ibcon#about to read 6, iclass 24, count 0 2006.246.07:49:29.62#ibcon#read 6, iclass 24, count 0 2006.246.07:49:29.62#ibcon#end of sib2, iclass 24, count 0 2006.246.07:49:29.62#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:49:29.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:49:29.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:49:29.62#ibcon#*before write, iclass 24, count 0 2006.246.07:49:29.62#ibcon#enter sib2, iclass 24, count 0 2006.246.07:49:29.62#ibcon#flushed, iclass 24, count 0 2006.246.07:49:29.62#ibcon#about to write, iclass 24, count 0 2006.246.07:49:29.62#ibcon#wrote, iclass 24, count 0 2006.246.07:49:29.62#ibcon#about to read 3, iclass 24, count 0 2006.246.07:49:29.66#ibcon#read 3, iclass 24, count 0 2006.246.07:49:29.66#ibcon#about to read 4, iclass 24, count 0 2006.246.07:49:29.66#ibcon#read 4, iclass 24, count 0 2006.246.07:49:29.66#ibcon#about to read 5, iclass 24, count 0 2006.246.07:49:29.66#ibcon#read 5, iclass 24, count 0 2006.246.07:49:29.66#ibcon#about to read 6, iclass 24, count 0 2006.246.07:49:29.66#ibcon#read 6, iclass 24, count 0 2006.246.07:49:29.66#ibcon#end of sib2, iclass 24, count 0 2006.246.07:49:29.66#ibcon#*after write, iclass 24, count 0 2006.246.07:49:29.66#ibcon#*before return 0, iclass 24, count 0 2006.246.07:49:29.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:29.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:29.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:49:29.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:49:29.66$vc4f8/va=6,7 2006.246.07:49:29.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.07:49:29.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.07:49:29.66#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:29.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:49:29.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:49:29.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:49:29.72#ibcon#enter wrdev, iclass 26, count 2 2006.246.07:49:29.72#ibcon#first serial, iclass 26, count 2 2006.246.07:49:29.72#ibcon#enter sib2, iclass 26, count 2 2006.246.07:49:29.72#ibcon#flushed, iclass 26, count 2 2006.246.07:49:29.72#ibcon#about to write, iclass 26, count 2 2006.246.07:49:29.72#ibcon#wrote, iclass 26, count 2 2006.246.07:49:29.72#ibcon#about to read 3, iclass 26, count 2 2006.246.07:49:29.74#ibcon#read 3, iclass 26, count 2 2006.246.07:49:29.74#ibcon#about to read 4, iclass 26, count 2 2006.246.07:49:29.74#ibcon#read 4, iclass 26, count 2 2006.246.07:49:29.74#ibcon#about to read 5, iclass 26, count 2 2006.246.07:49:29.74#ibcon#read 5, iclass 26, count 2 2006.246.07:49:29.74#ibcon#about to read 6, iclass 26, count 2 2006.246.07:49:29.74#ibcon#read 6, iclass 26, count 2 2006.246.07:49:29.74#ibcon#end of sib2, iclass 26, count 2 2006.246.07:49:29.74#ibcon#*mode == 0, iclass 26, count 2 2006.246.07:49:29.74#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.07:49:29.74#ibcon#[25=AT06-07\r\n] 2006.246.07:49:29.74#ibcon#*before write, iclass 26, count 2 2006.246.07:49:29.74#ibcon#enter sib2, iclass 26, count 2 2006.246.07:49:29.74#ibcon#flushed, iclass 26, count 2 2006.246.07:49:29.74#ibcon#about to write, iclass 26, count 2 2006.246.07:49:29.74#ibcon#wrote, iclass 26, count 2 2006.246.07:49:29.74#ibcon#about to read 3, iclass 26, count 2 2006.246.07:49:29.77#ibcon#read 3, iclass 26, count 2 2006.246.07:49:29.77#ibcon#about to read 4, iclass 26, count 2 2006.246.07:49:29.77#ibcon#read 4, iclass 26, count 2 2006.246.07:49:29.77#ibcon#about to read 5, iclass 26, count 2 2006.246.07:49:29.77#ibcon#read 5, iclass 26, count 2 2006.246.07:49:29.77#ibcon#about to read 6, iclass 26, count 2 2006.246.07:49:29.77#ibcon#read 6, iclass 26, count 2 2006.246.07:49:29.77#ibcon#end of sib2, iclass 26, count 2 2006.246.07:49:29.77#ibcon#*after write, iclass 26, count 2 2006.246.07:49:29.77#ibcon#*before return 0, iclass 26, count 2 2006.246.07:49:29.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:49:29.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.07:49:29.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.07:49:29.77#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:29.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:49:29.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:49:29.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:49:29.89#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:49:29.89#ibcon#first serial, iclass 26, count 0 2006.246.07:49:29.89#ibcon#enter sib2, iclass 26, count 0 2006.246.07:49:29.89#ibcon#flushed, iclass 26, count 0 2006.246.07:49:29.89#ibcon#about to write, iclass 26, count 0 2006.246.07:49:29.89#ibcon#wrote, iclass 26, count 0 2006.246.07:49:29.89#ibcon#about to read 3, iclass 26, count 0 2006.246.07:49:29.91#ibcon#read 3, iclass 26, count 0 2006.246.07:49:29.91#ibcon#about to read 4, iclass 26, count 0 2006.246.07:49:29.91#ibcon#read 4, iclass 26, count 0 2006.246.07:49:29.91#ibcon#about to read 5, iclass 26, count 0 2006.246.07:49:29.91#ibcon#read 5, iclass 26, count 0 2006.246.07:49:29.91#ibcon#about to read 6, iclass 26, count 0 2006.246.07:49:29.91#ibcon#read 6, iclass 26, count 0 2006.246.07:49:29.91#ibcon#end of sib2, iclass 26, count 0 2006.246.07:49:29.91#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:49:29.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:49:29.91#ibcon#[25=USB\r\n] 2006.246.07:49:29.91#ibcon#*before write, iclass 26, count 0 2006.246.07:49:29.91#ibcon#enter sib2, iclass 26, count 0 2006.246.07:49:29.91#ibcon#flushed, iclass 26, count 0 2006.246.07:49:29.91#ibcon#about to write, iclass 26, count 0 2006.246.07:49:29.91#ibcon#wrote, iclass 26, count 0 2006.246.07:49:29.91#ibcon#about to read 3, iclass 26, count 0 2006.246.07:49:29.94#ibcon#read 3, iclass 26, count 0 2006.246.07:49:29.94#ibcon#about to read 4, iclass 26, count 0 2006.246.07:49:29.94#ibcon#read 4, iclass 26, count 0 2006.246.07:49:29.94#ibcon#about to read 5, iclass 26, count 0 2006.246.07:49:29.94#ibcon#read 5, iclass 26, count 0 2006.246.07:49:29.94#ibcon#about to read 6, iclass 26, count 0 2006.246.07:49:29.94#ibcon#read 6, iclass 26, count 0 2006.246.07:49:29.94#ibcon#end of sib2, iclass 26, count 0 2006.246.07:49:29.94#ibcon#*after write, iclass 26, count 0 2006.246.07:49:29.94#ibcon#*before return 0, iclass 26, count 0 2006.246.07:49:29.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:49:29.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.07:49:29.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:49:29.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:49:29.94$vc4f8/valo=7,832.99 2006.246.07:49:29.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.07:49:29.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.07:49:29.94#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:29.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:49:29.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:49:29.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:49:29.94#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:49:29.94#ibcon#first serial, iclass 28, count 0 2006.246.07:49:29.94#ibcon#enter sib2, iclass 28, count 0 2006.246.07:49:29.94#ibcon#flushed, iclass 28, count 0 2006.246.07:49:29.94#ibcon#about to write, iclass 28, count 0 2006.246.07:49:29.94#ibcon#wrote, iclass 28, count 0 2006.246.07:49:29.94#ibcon#about to read 3, iclass 28, count 0 2006.246.07:49:29.96#ibcon#read 3, iclass 28, count 0 2006.246.07:49:29.96#ibcon#about to read 4, iclass 28, count 0 2006.246.07:49:29.96#ibcon#read 4, iclass 28, count 0 2006.246.07:49:29.96#ibcon#about to read 5, iclass 28, count 0 2006.246.07:49:29.96#ibcon#read 5, iclass 28, count 0 2006.246.07:49:29.96#ibcon#about to read 6, iclass 28, count 0 2006.246.07:49:29.96#ibcon#read 6, iclass 28, count 0 2006.246.07:49:29.96#ibcon#end of sib2, iclass 28, count 0 2006.246.07:49:29.96#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:49:29.96#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:49:29.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:49:29.96#ibcon#*before write, iclass 28, count 0 2006.246.07:49:29.96#ibcon#enter sib2, iclass 28, count 0 2006.246.07:49:29.96#ibcon#flushed, iclass 28, count 0 2006.246.07:49:29.96#ibcon#about to write, iclass 28, count 0 2006.246.07:49:29.96#ibcon#wrote, iclass 28, count 0 2006.246.07:49:29.96#ibcon#about to read 3, iclass 28, count 0 2006.246.07:49:30.00#ibcon#read 3, iclass 28, count 0 2006.246.07:49:30.00#ibcon#about to read 4, iclass 28, count 0 2006.246.07:49:30.00#ibcon#read 4, iclass 28, count 0 2006.246.07:49:30.00#ibcon#about to read 5, iclass 28, count 0 2006.246.07:49:30.00#ibcon#read 5, iclass 28, count 0 2006.246.07:49:30.00#ibcon#about to read 6, iclass 28, count 0 2006.246.07:49:30.00#ibcon#read 6, iclass 28, count 0 2006.246.07:49:30.00#ibcon#end of sib2, iclass 28, count 0 2006.246.07:49:30.00#ibcon#*after write, iclass 28, count 0 2006.246.07:49:30.00#ibcon#*before return 0, iclass 28, count 0 2006.246.07:49:30.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:49:30.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.07:49:30.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:49:30.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:49:30.00$vc4f8/va=7,7 2006.246.07:49:30.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.07:49:30.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.07:49:30.00#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:30.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:49:30.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:49:30.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:49:30.06#ibcon#enter wrdev, iclass 30, count 2 2006.246.07:49:30.06#ibcon#first serial, iclass 30, count 2 2006.246.07:49:30.06#ibcon#enter sib2, iclass 30, count 2 2006.246.07:49:30.06#ibcon#flushed, iclass 30, count 2 2006.246.07:49:30.06#ibcon#about to write, iclass 30, count 2 2006.246.07:49:30.06#ibcon#wrote, iclass 30, count 2 2006.246.07:49:30.06#ibcon#about to read 3, iclass 30, count 2 2006.246.07:49:30.08#ibcon#read 3, iclass 30, count 2 2006.246.07:49:30.08#ibcon#about to read 4, iclass 30, count 2 2006.246.07:49:30.08#ibcon#read 4, iclass 30, count 2 2006.246.07:49:30.08#ibcon#about to read 5, iclass 30, count 2 2006.246.07:49:30.08#ibcon#read 5, iclass 30, count 2 2006.246.07:49:30.08#ibcon#about to read 6, iclass 30, count 2 2006.246.07:49:30.08#ibcon#read 6, iclass 30, count 2 2006.246.07:49:30.08#ibcon#end of sib2, iclass 30, count 2 2006.246.07:49:30.08#ibcon#*mode == 0, iclass 30, count 2 2006.246.07:49:30.08#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.07:49:30.08#ibcon#[25=AT07-07\r\n] 2006.246.07:49:30.08#ibcon#*before write, iclass 30, count 2 2006.246.07:49:30.08#ibcon#enter sib2, iclass 30, count 2 2006.246.07:49:30.08#ibcon#flushed, iclass 30, count 2 2006.246.07:49:30.08#ibcon#about to write, iclass 30, count 2 2006.246.07:49:30.08#ibcon#wrote, iclass 30, count 2 2006.246.07:49:30.08#ibcon#about to read 3, iclass 30, count 2 2006.246.07:49:30.11#ibcon#read 3, iclass 30, count 2 2006.246.07:49:30.11#ibcon#about to read 4, iclass 30, count 2 2006.246.07:49:30.11#ibcon#read 4, iclass 30, count 2 2006.246.07:49:30.11#ibcon#about to read 5, iclass 30, count 2 2006.246.07:49:30.11#ibcon#read 5, iclass 30, count 2 2006.246.07:49:30.11#ibcon#about to read 6, iclass 30, count 2 2006.246.07:49:30.11#ibcon#read 6, iclass 30, count 2 2006.246.07:49:30.11#ibcon#end of sib2, iclass 30, count 2 2006.246.07:49:30.11#ibcon#*after write, iclass 30, count 2 2006.246.07:49:30.11#ibcon#*before return 0, iclass 30, count 2 2006.246.07:49:30.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:49:30.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.07:49:30.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.07:49:30.11#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:30.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:49:30.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:49:30.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:49:30.23#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:49:30.23#ibcon#first serial, iclass 30, count 0 2006.246.07:49:30.23#ibcon#enter sib2, iclass 30, count 0 2006.246.07:49:30.23#ibcon#flushed, iclass 30, count 0 2006.246.07:49:30.23#ibcon#about to write, iclass 30, count 0 2006.246.07:49:30.23#ibcon#wrote, iclass 30, count 0 2006.246.07:49:30.23#ibcon#about to read 3, iclass 30, count 0 2006.246.07:49:30.25#ibcon#read 3, iclass 30, count 0 2006.246.07:49:30.25#ibcon#about to read 4, iclass 30, count 0 2006.246.07:49:30.25#ibcon#read 4, iclass 30, count 0 2006.246.07:49:30.25#ibcon#about to read 5, iclass 30, count 0 2006.246.07:49:30.25#ibcon#read 5, iclass 30, count 0 2006.246.07:49:30.25#ibcon#about to read 6, iclass 30, count 0 2006.246.07:49:30.25#ibcon#read 6, iclass 30, count 0 2006.246.07:49:30.25#ibcon#end of sib2, iclass 30, count 0 2006.246.07:49:30.25#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:49:30.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:49:30.25#ibcon#[25=USB\r\n] 2006.246.07:49:30.25#ibcon#*before write, iclass 30, count 0 2006.246.07:49:30.25#ibcon#enter sib2, iclass 30, count 0 2006.246.07:49:30.25#ibcon#flushed, iclass 30, count 0 2006.246.07:49:30.25#ibcon#about to write, iclass 30, count 0 2006.246.07:49:30.25#ibcon#wrote, iclass 30, count 0 2006.246.07:49:30.25#ibcon#about to read 3, iclass 30, count 0 2006.246.07:49:30.28#ibcon#read 3, iclass 30, count 0 2006.246.07:49:30.28#ibcon#about to read 4, iclass 30, count 0 2006.246.07:49:30.28#ibcon#read 4, iclass 30, count 0 2006.246.07:49:30.28#ibcon#about to read 5, iclass 30, count 0 2006.246.07:49:30.28#ibcon#read 5, iclass 30, count 0 2006.246.07:49:30.28#ibcon#about to read 6, iclass 30, count 0 2006.246.07:49:30.28#ibcon#read 6, iclass 30, count 0 2006.246.07:49:30.28#ibcon#end of sib2, iclass 30, count 0 2006.246.07:49:30.28#ibcon#*after write, iclass 30, count 0 2006.246.07:49:30.28#ibcon#*before return 0, iclass 30, count 0 2006.246.07:49:30.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:49:30.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.07:49:30.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:49:30.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:49:30.28$vc4f8/valo=8,852.99 2006.246.07:49:30.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.07:49:30.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.07:49:30.28#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:30.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:49:30.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:49:30.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:49:30.28#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:49:30.28#ibcon#first serial, iclass 32, count 0 2006.246.07:49:30.28#ibcon#enter sib2, iclass 32, count 0 2006.246.07:49:30.28#ibcon#flushed, iclass 32, count 0 2006.246.07:49:30.28#ibcon#about to write, iclass 32, count 0 2006.246.07:49:30.28#ibcon#wrote, iclass 32, count 0 2006.246.07:49:30.28#ibcon#about to read 3, iclass 32, count 0 2006.246.07:49:30.31#ibcon#read 3, iclass 32, count 0 2006.246.07:49:30.31#ibcon#about to read 4, iclass 32, count 0 2006.246.07:49:30.31#ibcon#read 4, iclass 32, count 0 2006.246.07:49:30.31#ibcon#about to read 5, iclass 32, count 0 2006.246.07:49:30.31#ibcon#read 5, iclass 32, count 0 2006.246.07:49:30.31#ibcon#about to read 6, iclass 32, count 0 2006.246.07:49:30.31#ibcon#read 6, iclass 32, count 0 2006.246.07:49:30.31#ibcon#end of sib2, iclass 32, count 0 2006.246.07:49:30.31#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:49:30.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:49:30.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:49:30.31#ibcon#*before write, iclass 32, count 0 2006.246.07:49:30.31#ibcon#enter sib2, iclass 32, count 0 2006.246.07:49:30.31#ibcon#flushed, iclass 32, count 0 2006.246.07:49:30.31#ibcon#about to write, iclass 32, count 0 2006.246.07:49:30.31#ibcon#wrote, iclass 32, count 0 2006.246.07:49:30.31#ibcon#about to read 3, iclass 32, count 0 2006.246.07:49:30.35#ibcon#read 3, iclass 32, count 0 2006.246.07:49:30.35#ibcon#about to read 4, iclass 32, count 0 2006.246.07:49:30.35#ibcon#read 4, iclass 32, count 0 2006.246.07:49:30.35#ibcon#about to read 5, iclass 32, count 0 2006.246.07:49:30.35#ibcon#read 5, iclass 32, count 0 2006.246.07:49:30.35#ibcon#about to read 6, iclass 32, count 0 2006.246.07:49:30.35#ibcon#read 6, iclass 32, count 0 2006.246.07:49:30.35#ibcon#end of sib2, iclass 32, count 0 2006.246.07:49:30.35#ibcon#*after write, iclass 32, count 0 2006.246.07:49:30.35#ibcon#*before return 0, iclass 32, count 0 2006.246.07:49:30.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:49:30.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.07:49:30.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:49:30.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:49:30.35$vc4f8/va=8,8 2006.246.07:49:30.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.07:49:30.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.07:49:30.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:30.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:49:30.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:49:30.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:49:30.40#ibcon#enter wrdev, iclass 34, count 2 2006.246.07:49:30.40#ibcon#first serial, iclass 34, count 2 2006.246.07:49:30.40#ibcon#enter sib2, iclass 34, count 2 2006.246.07:49:30.40#ibcon#flushed, iclass 34, count 2 2006.246.07:49:30.40#ibcon#about to write, iclass 34, count 2 2006.246.07:49:30.40#ibcon#wrote, iclass 34, count 2 2006.246.07:49:30.40#ibcon#about to read 3, iclass 34, count 2 2006.246.07:49:30.42#ibcon#read 3, iclass 34, count 2 2006.246.07:49:30.42#ibcon#about to read 4, iclass 34, count 2 2006.246.07:49:30.42#ibcon#read 4, iclass 34, count 2 2006.246.07:49:30.42#ibcon#about to read 5, iclass 34, count 2 2006.246.07:49:30.42#ibcon#read 5, iclass 34, count 2 2006.246.07:49:30.42#ibcon#about to read 6, iclass 34, count 2 2006.246.07:49:30.42#ibcon#read 6, iclass 34, count 2 2006.246.07:49:30.42#ibcon#end of sib2, iclass 34, count 2 2006.246.07:49:30.42#ibcon#*mode == 0, iclass 34, count 2 2006.246.07:49:30.42#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.07:49:30.42#ibcon#[25=AT08-08\r\n] 2006.246.07:49:30.42#ibcon#*before write, iclass 34, count 2 2006.246.07:49:30.42#ibcon#enter sib2, iclass 34, count 2 2006.246.07:49:30.42#ibcon#flushed, iclass 34, count 2 2006.246.07:49:30.42#ibcon#about to write, iclass 34, count 2 2006.246.07:49:30.42#ibcon#wrote, iclass 34, count 2 2006.246.07:49:30.42#ibcon#about to read 3, iclass 34, count 2 2006.246.07:49:30.45#ibcon#read 3, iclass 34, count 2 2006.246.07:49:30.45#ibcon#about to read 4, iclass 34, count 2 2006.246.07:49:30.45#ibcon#read 4, iclass 34, count 2 2006.246.07:49:30.45#ibcon#about to read 5, iclass 34, count 2 2006.246.07:49:30.45#ibcon#read 5, iclass 34, count 2 2006.246.07:49:30.45#ibcon#about to read 6, iclass 34, count 2 2006.246.07:49:30.45#ibcon#read 6, iclass 34, count 2 2006.246.07:49:30.45#ibcon#end of sib2, iclass 34, count 2 2006.246.07:49:30.45#ibcon#*after write, iclass 34, count 2 2006.246.07:49:30.45#ibcon#*before return 0, iclass 34, count 2 2006.246.07:49:30.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:49:30.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.07:49:30.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.07:49:30.45#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:30.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:49:30.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:49:30.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:49:30.57#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:49:30.57#ibcon#first serial, iclass 34, count 0 2006.246.07:49:30.57#ibcon#enter sib2, iclass 34, count 0 2006.246.07:49:30.57#ibcon#flushed, iclass 34, count 0 2006.246.07:49:30.57#ibcon#about to write, iclass 34, count 0 2006.246.07:49:30.57#ibcon#wrote, iclass 34, count 0 2006.246.07:49:30.57#ibcon#about to read 3, iclass 34, count 0 2006.246.07:49:30.59#ibcon#read 3, iclass 34, count 0 2006.246.07:49:30.59#ibcon#about to read 4, iclass 34, count 0 2006.246.07:49:30.59#ibcon#read 4, iclass 34, count 0 2006.246.07:49:30.59#ibcon#about to read 5, iclass 34, count 0 2006.246.07:49:30.59#ibcon#read 5, iclass 34, count 0 2006.246.07:49:30.59#ibcon#about to read 6, iclass 34, count 0 2006.246.07:49:30.59#ibcon#read 6, iclass 34, count 0 2006.246.07:49:30.59#ibcon#end of sib2, iclass 34, count 0 2006.246.07:49:30.59#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:49:30.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:49:30.59#ibcon#[25=USB\r\n] 2006.246.07:49:30.59#ibcon#*before write, iclass 34, count 0 2006.246.07:49:30.59#ibcon#enter sib2, iclass 34, count 0 2006.246.07:49:30.59#ibcon#flushed, iclass 34, count 0 2006.246.07:49:30.59#ibcon#about to write, iclass 34, count 0 2006.246.07:49:30.59#ibcon#wrote, iclass 34, count 0 2006.246.07:49:30.59#ibcon#about to read 3, iclass 34, count 0 2006.246.07:49:30.62#ibcon#read 3, iclass 34, count 0 2006.246.07:49:30.62#ibcon#about to read 4, iclass 34, count 0 2006.246.07:49:30.62#ibcon#read 4, iclass 34, count 0 2006.246.07:49:30.62#ibcon#about to read 5, iclass 34, count 0 2006.246.07:49:30.62#ibcon#read 5, iclass 34, count 0 2006.246.07:49:30.62#ibcon#about to read 6, iclass 34, count 0 2006.246.07:49:30.62#ibcon#read 6, iclass 34, count 0 2006.246.07:49:30.62#ibcon#end of sib2, iclass 34, count 0 2006.246.07:49:30.62#ibcon#*after write, iclass 34, count 0 2006.246.07:49:30.62#ibcon#*before return 0, iclass 34, count 0 2006.246.07:49:30.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:49:30.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.07:49:30.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:49:30.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:49:30.62$vc4f8/vblo=1,632.99 2006.246.07:49:30.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.07:49:30.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.07:49:30.62#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:30.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:49:30.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:49:30.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:49:30.62#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:49:30.62#ibcon#first serial, iclass 36, count 0 2006.246.07:49:30.62#ibcon#enter sib2, iclass 36, count 0 2006.246.07:49:30.62#ibcon#flushed, iclass 36, count 0 2006.246.07:49:30.62#ibcon#about to write, iclass 36, count 0 2006.246.07:49:30.62#ibcon#wrote, iclass 36, count 0 2006.246.07:49:30.62#ibcon#about to read 3, iclass 36, count 0 2006.246.07:49:30.64#ibcon#read 3, iclass 36, count 0 2006.246.07:49:30.64#ibcon#about to read 4, iclass 36, count 0 2006.246.07:49:30.64#ibcon#read 4, iclass 36, count 0 2006.246.07:49:30.64#ibcon#about to read 5, iclass 36, count 0 2006.246.07:49:30.64#ibcon#read 5, iclass 36, count 0 2006.246.07:49:30.64#ibcon#about to read 6, iclass 36, count 0 2006.246.07:49:30.64#ibcon#read 6, iclass 36, count 0 2006.246.07:49:30.64#ibcon#end of sib2, iclass 36, count 0 2006.246.07:49:30.64#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:49:30.64#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:49:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:49:30.64#ibcon#*before write, iclass 36, count 0 2006.246.07:49:30.64#ibcon#enter sib2, iclass 36, count 0 2006.246.07:49:30.64#ibcon#flushed, iclass 36, count 0 2006.246.07:49:30.64#ibcon#about to write, iclass 36, count 0 2006.246.07:49:30.64#ibcon#wrote, iclass 36, count 0 2006.246.07:49:30.64#ibcon#about to read 3, iclass 36, count 0 2006.246.07:49:30.68#ibcon#read 3, iclass 36, count 0 2006.246.07:49:30.68#ibcon#about to read 4, iclass 36, count 0 2006.246.07:49:30.68#ibcon#read 4, iclass 36, count 0 2006.246.07:49:30.68#ibcon#about to read 5, iclass 36, count 0 2006.246.07:49:30.68#ibcon#read 5, iclass 36, count 0 2006.246.07:49:30.68#ibcon#about to read 6, iclass 36, count 0 2006.246.07:49:30.68#ibcon#read 6, iclass 36, count 0 2006.246.07:49:30.68#ibcon#end of sib2, iclass 36, count 0 2006.246.07:49:30.68#ibcon#*after write, iclass 36, count 0 2006.246.07:49:30.68#ibcon#*before return 0, iclass 36, count 0 2006.246.07:49:30.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:49:30.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.07:49:30.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:49:30.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:49:30.68$vc4f8/vb=1,4 2006.246.07:49:30.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.07:49:30.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.07:49:30.68#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:30.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:49:30.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:49:30.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:49:30.68#ibcon#enter wrdev, iclass 38, count 2 2006.246.07:49:30.68#ibcon#first serial, iclass 38, count 2 2006.246.07:49:30.68#ibcon#enter sib2, iclass 38, count 2 2006.246.07:49:30.68#ibcon#flushed, iclass 38, count 2 2006.246.07:49:30.68#ibcon#about to write, iclass 38, count 2 2006.246.07:49:30.68#ibcon#wrote, iclass 38, count 2 2006.246.07:49:30.68#ibcon#about to read 3, iclass 38, count 2 2006.246.07:49:30.70#ibcon#read 3, iclass 38, count 2 2006.246.07:49:30.70#ibcon#about to read 4, iclass 38, count 2 2006.246.07:49:30.70#ibcon#read 4, iclass 38, count 2 2006.246.07:49:30.70#ibcon#about to read 5, iclass 38, count 2 2006.246.07:49:30.70#ibcon#read 5, iclass 38, count 2 2006.246.07:49:30.70#ibcon#about to read 6, iclass 38, count 2 2006.246.07:49:30.70#ibcon#read 6, iclass 38, count 2 2006.246.07:49:30.70#ibcon#end of sib2, iclass 38, count 2 2006.246.07:49:30.70#ibcon#*mode == 0, iclass 38, count 2 2006.246.07:49:30.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.07:49:30.70#ibcon#[27=AT01-04\r\n] 2006.246.07:49:30.70#ibcon#*before write, iclass 38, count 2 2006.246.07:49:30.70#ibcon#enter sib2, iclass 38, count 2 2006.246.07:49:30.70#ibcon#flushed, iclass 38, count 2 2006.246.07:49:30.70#ibcon#about to write, iclass 38, count 2 2006.246.07:49:30.70#ibcon#wrote, iclass 38, count 2 2006.246.07:49:30.70#ibcon#about to read 3, iclass 38, count 2 2006.246.07:49:30.73#ibcon#read 3, iclass 38, count 2 2006.246.07:49:30.73#ibcon#about to read 4, iclass 38, count 2 2006.246.07:49:30.73#ibcon#read 4, iclass 38, count 2 2006.246.07:49:30.73#ibcon#about to read 5, iclass 38, count 2 2006.246.07:49:30.73#ibcon#read 5, iclass 38, count 2 2006.246.07:49:30.73#ibcon#about to read 6, iclass 38, count 2 2006.246.07:49:30.73#ibcon#read 6, iclass 38, count 2 2006.246.07:49:30.73#ibcon#end of sib2, iclass 38, count 2 2006.246.07:49:30.73#ibcon#*after write, iclass 38, count 2 2006.246.07:49:30.73#ibcon#*before return 0, iclass 38, count 2 2006.246.07:49:30.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:49:30.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.07:49:30.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.07:49:30.73#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:30.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:49:30.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:49:30.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:49:30.85#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:49:30.85#ibcon#first serial, iclass 38, count 0 2006.246.07:49:30.85#ibcon#enter sib2, iclass 38, count 0 2006.246.07:49:30.85#ibcon#flushed, iclass 38, count 0 2006.246.07:49:30.85#ibcon#about to write, iclass 38, count 0 2006.246.07:49:30.85#ibcon#wrote, iclass 38, count 0 2006.246.07:49:30.85#ibcon#about to read 3, iclass 38, count 0 2006.246.07:49:30.87#ibcon#read 3, iclass 38, count 0 2006.246.07:49:30.87#ibcon#about to read 4, iclass 38, count 0 2006.246.07:49:30.87#ibcon#read 4, iclass 38, count 0 2006.246.07:49:30.87#ibcon#about to read 5, iclass 38, count 0 2006.246.07:49:30.87#ibcon#read 5, iclass 38, count 0 2006.246.07:49:30.87#ibcon#about to read 6, iclass 38, count 0 2006.246.07:49:30.87#ibcon#read 6, iclass 38, count 0 2006.246.07:49:30.87#ibcon#end of sib2, iclass 38, count 0 2006.246.07:49:30.87#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:49:30.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:49:30.87#ibcon#[27=USB\r\n] 2006.246.07:49:30.87#ibcon#*before write, iclass 38, count 0 2006.246.07:49:30.87#ibcon#enter sib2, iclass 38, count 0 2006.246.07:49:30.87#ibcon#flushed, iclass 38, count 0 2006.246.07:49:30.87#ibcon#about to write, iclass 38, count 0 2006.246.07:49:30.87#ibcon#wrote, iclass 38, count 0 2006.246.07:49:30.87#ibcon#about to read 3, iclass 38, count 0 2006.246.07:49:30.90#ibcon#read 3, iclass 38, count 0 2006.246.07:49:30.90#ibcon#about to read 4, iclass 38, count 0 2006.246.07:49:30.90#ibcon#read 4, iclass 38, count 0 2006.246.07:49:30.90#ibcon#about to read 5, iclass 38, count 0 2006.246.07:49:30.90#ibcon#read 5, iclass 38, count 0 2006.246.07:49:30.90#ibcon#about to read 6, iclass 38, count 0 2006.246.07:49:30.90#ibcon#read 6, iclass 38, count 0 2006.246.07:49:30.90#ibcon#end of sib2, iclass 38, count 0 2006.246.07:49:30.90#ibcon#*after write, iclass 38, count 0 2006.246.07:49:30.90#ibcon#*before return 0, iclass 38, count 0 2006.246.07:49:30.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:49:30.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.07:49:30.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:49:30.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:49:30.90$vc4f8/vblo=2,640.99 2006.246.07:49:30.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:49:30.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:49:30.90#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:30.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:30.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:30.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:30.90#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:49:30.90#ibcon#first serial, iclass 40, count 0 2006.246.07:49:30.90#ibcon#enter sib2, iclass 40, count 0 2006.246.07:49:30.90#ibcon#flushed, iclass 40, count 0 2006.246.07:49:30.90#ibcon#about to write, iclass 40, count 0 2006.246.07:49:30.90#ibcon#wrote, iclass 40, count 0 2006.246.07:49:30.90#ibcon#about to read 3, iclass 40, count 0 2006.246.07:49:30.92#ibcon#read 3, iclass 40, count 0 2006.246.07:49:30.92#ibcon#about to read 4, iclass 40, count 0 2006.246.07:49:30.92#ibcon#read 4, iclass 40, count 0 2006.246.07:49:30.92#ibcon#about to read 5, iclass 40, count 0 2006.246.07:49:30.92#ibcon#read 5, iclass 40, count 0 2006.246.07:49:30.92#ibcon#about to read 6, iclass 40, count 0 2006.246.07:49:30.92#ibcon#read 6, iclass 40, count 0 2006.246.07:49:30.92#ibcon#end of sib2, iclass 40, count 0 2006.246.07:49:30.92#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:49:30.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:49:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:49:30.92#ibcon#*before write, iclass 40, count 0 2006.246.07:49:30.92#ibcon#enter sib2, iclass 40, count 0 2006.246.07:49:30.92#ibcon#flushed, iclass 40, count 0 2006.246.07:49:30.92#ibcon#about to write, iclass 40, count 0 2006.246.07:49:30.92#ibcon#wrote, iclass 40, count 0 2006.246.07:49:30.92#ibcon#about to read 3, iclass 40, count 0 2006.246.07:49:30.96#ibcon#read 3, iclass 40, count 0 2006.246.07:49:30.96#ibcon#about to read 4, iclass 40, count 0 2006.246.07:49:30.96#ibcon#read 4, iclass 40, count 0 2006.246.07:49:30.96#ibcon#about to read 5, iclass 40, count 0 2006.246.07:49:30.96#ibcon#read 5, iclass 40, count 0 2006.246.07:49:30.96#ibcon#about to read 6, iclass 40, count 0 2006.246.07:49:30.96#ibcon#read 6, iclass 40, count 0 2006.246.07:49:30.96#ibcon#end of sib2, iclass 40, count 0 2006.246.07:49:30.96#ibcon#*after write, iclass 40, count 0 2006.246.07:49:30.96#ibcon#*before return 0, iclass 40, count 0 2006.246.07:49:30.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:30.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:49:30.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:49:30.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:49:30.96$vc4f8/vb=2,4 2006.246.07:49:30.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.07:49:30.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.07:49:30.96#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:30.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:31.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:31.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:31.02#ibcon#enter wrdev, iclass 4, count 2 2006.246.07:49:31.02#ibcon#first serial, iclass 4, count 2 2006.246.07:49:31.02#ibcon#enter sib2, iclass 4, count 2 2006.246.07:49:31.02#ibcon#flushed, iclass 4, count 2 2006.246.07:49:31.02#ibcon#about to write, iclass 4, count 2 2006.246.07:49:31.02#ibcon#wrote, iclass 4, count 2 2006.246.07:49:31.02#ibcon#about to read 3, iclass 4, count 2 2006.246.07:49:31.04#ibcon#read 3, iclass 4, count 2 2006.246.07:49:31.04#ibcon#about to read 4, iclass 4, count 2 2006.246.07:49:31.04#ibcon#read 4, iclass 4, count 2 2006.246.07:49:31.04#ibcon#about to read 5, iclass 4, count 2 2006.246.07:49:31.04#ibcon#read 5, iclass 4, count 2 2006.246.07:49:31.04#ibcon#about to read 6, iclass 4, count 2 2006.246.07:49:31.04#ibcon#read 6, iclass 4, count 2 2006.246.07:49:31.04#ibcon#end of sib2, iclass 4, count 2 2006.246.07:49:31.04#ibcon#*mode == 0, iclass 4, count 2 2006.246.07:49:31.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.07:49:31.04#ibcon#[27=AT02-04\r\n] 2006.246.07:49:31.04#ibcon#*before write, iclass 4, count 2 2006.246.07:49:31.04#ibcon#enter sib2, iclass 4, count 2 2006.246.07:49:31.04#ibcon#flushed, iclass 4, count 2 2006.246.07:49:31.04#ibcon#about to write, iclass 4, count 2 2006.246.07:49:31.04#ibcon#wrote, iclass 4, count 2 2006.246.07:49:31.04#ibcon#about to read 3, iclass 4, count 2 2006.246.07:49:31.07#ibcon#read 3, iclass 4, count 2 2006.246.07:49:31.07#ibcon#about to read 4, iclass 4, count 2 2006.246.07:49:31.07#ibcon#read 4, iclass 4, count 2 2006.246.07:49:31.07#ibcon#about to read 5, iclass 4, count 2 2006.246.07:49:31.07#ibcon#read 5, iclass 4, count 2 2006.246.07:49:31.07#ibcon#about to read 6, iclass 4, count 2 2006.246.07:49:31.07#ibcon#read 6, iclass 4, count 2 2006.246.07:49:31.07#ibcon#end of sib2, iclass 4, count 2 2006.246.07:49:31.07#ibcon#*after write, iclass 4, count 2 2006.246.07:49:31.07#ibcon#*before return 0, iclass 4, count 2 2006.246.07:49:31.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:31.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.07:49:31.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.07:49:31.07#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:31.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:31.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:31.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:31.19#ibcon#enter wrdev, iclass 4, count 0 2006.246.07:49:31.19#ibcon#first serial, iclass 4, count 0 2006.246.07:49:31.19#ibcon#enter sib2, iclass 4, count 0 2006.246.07:49:31.19#ibcon#flushed, iclass 4, count 0 2006.246.07:49:31.19#ibcon#about to write, iclass 4, count 0 2006.246.07:49:31.19#ibcon#wrote, iclass 4, count 0 2006.246.07:49:31.19#ibcon#about to read 3, iclass 4, count 0 2006.246.07:49:31.21#ibcon#read 3, iclass 4, count 0 2006.246.07:49:31.21#ibcon#about to read 4, iclass 4, count 0 2006.246.07:49:31.21#ibcon#read 4, iclass 4, count 0 2006.246.07:49:31.21#ibcon#about to read 5, iclass 4, count 0 2006.246.07:49:31.21#ibcon#read 5, iclass 4, count 0 2006.246.07:49:31.21#ibcon#about to read 6, iclass 4, count 0 2006.246.07:49:31.21#ibcon#read 6, iclass 4, count 0 2006.246.07:49:31.21#ibcon#end of sib2, iclass 4, count 0 2006.246.07:49:31.21#ibcon#*mode == 0, iclass 4, count 0 2006.246.07:49:31.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.07:49:31.21#ibcon#[27=USB\r\n] 2006.246.07:49:31.21#ibcon#*before write, iclass 4, count 0 2006.246.07:49:31.21#ibcon#enter sib2, iclass 4, count 0 2006.246.07:49:31.21#ibcon#flushed, iclass 4, count 0 2006.246.07:49:31.21#ibcon#about to write, iclass 4, count 0 2006.246.07:49:31.21#ibcon#wrote, iclass 4, count 0 2006.246.07:49:31.21#ibcon#about to read 3, iclass 4, count 0 2006.246.07:49:31.24#ibcon#read 3, iclass 4, count 0 2006.246.07:49:31.24#ibcon#about to read 4, iclass 4, count 0 2006.246.07:49:31.24#ibcon#read 4, iclass 4, count 0 2006.246.07:49:31.24#ibcon#about to read 5, iclass 4, count 0 2006.246.07:49:31.24#ibcon#read 5, iclass 4, count 0 2006.246.07:49:31.24#ibcon#about to read 6, iclass 4, count 0 2006.246.07:49:31.24#ibcon#read 6, iclass 4, count 0 2006.246.07:49:31.24#ibcon#end of sib2, iclass 4, count 0 2006.246.07:49:31.24#ibcon#*after write, iclass 4, count 0 2006.246.07:49:31.24#ibcon#*before return 0, iclass 4, count 0 2006.246.07:49:31.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:31.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.07:49:31.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.07:49:31.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.07:49:31.24$vc4f8/vblo=3,656.99 2006.246.07:49:31.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.07:49:31.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.07:49:31.24#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:31.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:31.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:31.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:31.24#ibcon#enter wrdev, iclass 6, count 0 2006.246.07:49:31.24#ibcon#first serial, iclass 6, count 0 2006.246.07:49:31.24#ibcon#enter sib2, iclass 6, count 0 2006.246.07:49:31.24#ibcon#flushed, iclass 6, count 0 2006.246.07:49:31.24#ibcon#about to write, iclass 6, count 0 2006.246.07:49:31.24#ibcon#wrote, iclass 6, count 0 2006.246.07:49:31.24#ibcon#about to read 3, iclass 6, count 0 2006.246.07:49:31.26#ibcon#read 3, iclass 6, count 0 2006.246.07:49:31.26#ibcon#about to read 4, iclass 6, count 0 2006.246.07:49:31.26#ibcon#read 4, iclass 6, count 0 2006.246.07:49:31.26#ibcon#about to read 5, iclass 6, count 0 2006.246.07:49:31.26#ibcon#read 5, iclass 6, count 0 2006.246.07:49:31.26#ibcon#about to read 6, iclass 6, count 0 2006.246.07:49:31.26#ibcon#read 6, iclass 6, count 0 2006.246.07:49:31.26#ibcon#end of sib2, iclass 6, count 0 2006.246.07:49:31.26#ibcon#*mode == 0, iclass 6, count 0 2006.246.07:49:31.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.07:49:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:49:31.26#ibcon#*before write, iclass 6, count 0 2006.246.07:49:31.26#ibcon#enter sib2, iclass 6, count 0 2006.246.07:49:31.26#ibcon#flushed, iclass 6, count 0 2006.246.07:49:31.26#ibcon#about to write, iclass 6, count 0 2006.246.07:49:31.26#ibcon#wrote, iclass 6, count 0 2006.246.07:49:31.26#ibcon#about to read 3, iclass 6, count 0 2006.246.07:49:31.30#ibcon#read 3, iclass 6, count 0 2006.246.07:49:31.30#ibcon#about to read 4, iclass 6, count 0 2006.246.07:49:31.30#ibcon#read 4, iclass 6, count 0 2006.246.07:49:31.30#ibcon#about to read 5, iclass 6, count 0 2006.246.07:49:31.30#ibcon#read 5, iclass 6, count 0 2006.246.07:49:31.30#ibcon#about to read 6, iclass 6, count 0 2006.246.07:49:31.30#ibcon#read 6, iclass 6, count 0 2006.246.07:49:31.30#ibcon#end of sib2, iclass 6, count 0 2006.246.07:49:31.30#ibcon#*after write, iclass 6, count 0 2006.246.07:49:31.30#ibcon#*before return 0, iclass 6, count 0 2006.246.07:49:31.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:31.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.07:49:31.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.07:49:31.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.07:49:31.30$vc4f8/vb=3,4 2006.246.07:49:31.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.07:49:31.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.07:49:31.30#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:31.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:31.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:31.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:31.36#ibcon#enter wrdev, iclass 10, count 2 2006.246.07:49:31.36#ibcon#first serial, iclass 10, count 2 2006.246.07:49:31.36#ibcon#enter sib2, iclass 10, count 2 2006.246.07:49:31.36#ibcon#flushed, iclass 10, count 2 2006.246.07:49:31.36#ibcon#about to write, iclass 10, count 2 2006.246.07:49:31.36#ibcon#wrote, iclass 10, count 2 2006.246.07:49:31.36#ibcon#about to read 3, iclass 10, count 2 2006.246.07:49:31.38#ibcon#read 3, iclass 10, count 2 2006.246.07:49:31.38#ibcon#about to read 4, iclass 10, count 2 2006.246.07:49:31.38#ibcon#read 4, iclass 10, count 2 2006.246.07:49:31.38#ibcon#about to read 5, iclass 10, count 2 2006.246.07:49:31.38#ibcon#read 5, iclass 10, count 2 2006.246.07:49:31.38#ibcon#about to read 6, iclass 10, count 2 2006.246.07:49:31.38#ibcon#read 6, iclass 10, count 2 2006.246.07:49:31.38#ibcon#end of sib2, iclass 10, count 2 2006.246.07:49:31.38#ibcon#*mode == 0, iclass 10, count 2 2006.246.07:49:31.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.07:49:31.38#ibcon#[27=AT03-04\r\n] 2006.246.07:49:31.38#ibcon#*before write, iclass 10, count 2 2006.246.07:49:31.38#ibcon#enter sib2, iclass 10, count 2 2006.246.07:49:31.38#ibcon#flushed, iclass 10, count 2 2006.246.07:49:31.38#ibcon#about to write, iclass 10, count 2 2006.246.07:49:31.38#ibcon#wrote, iclass 10, count 2 2006.246.07:49:31.38#ibcon#about to read 3, iclass 10, count 2 2006.246.07:49:31.41#ibcon#read 3, iclass 10, count 2 2006.246.07:49:31.41#ibcon#about to read 4, iclass 10, count 2 2006.246.07:49:31.41#ibcon#read 4, iclass 10, count 2 2006.246.07:49:31.41#ibcon#about to read 5, iclass 10, count 2 2006.246.07:49:31.41#ibcon#read 5, iclass 10, count 2 2006.246.07:49:31.41#ibcon#about to read 6, iclass 10, count 2 2006.246.07:49:31.41#ibcon#read 6, iclass 10, count 2 2006.246.07:49:31.41#ibcon#end of sib2, iclass 10, count 2 2006.246.07:49:31.41#ibcon#*after write, iclass 10, count 2 2006.246.07:49:31.41#ibcon#*before return 0, iclass 10, count 2 2006.246.07:49:31.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:31.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.07:49:31.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.07:49:31.41#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:31.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:31.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:31.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:31.53#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:49:31.53#ibcon#first serial, iclass 10, count 0 2006.246.07:49:31.53#ibcon#enter sib2, iclass 10, count 0 2006.246.07:49:31.53#ibcon#flushed, iclass 10, count 0 2006.246.07:49:31.53#ibcon#about to write, iclass 10, count 0 2006.246.07:49:31.53#ibcon#wrote, iclass 10, count 0 2006.246.07:49:31.53#ibcon#about to read 3, iclass 10, count 0 2006.246.07:49:31.55#ibcon#read 3, iclass 10, count 0 2006.246.07:49:31.55#ibcon#about to read 4, iclass 10, count 0 2006.246.07:49:31.55#ibcon#read 4, iclass 10, count 0 2006.246.07:49:31.55#ibcon#about to read 5, iclass 10, count 0 2006.246.07:49:31.55#ibcon#read 5, iclass 10, count 0 2006.246.07:49:31.55#ibcon#about to read 6, iclass 10, count 0 2006.246.07:49:31.55#ibcon#read 6, iclass 10, count 0 2006.246.07:49:31.55#ibcon#end of sib2, iclass 10, count 0 2006.246.07:49:31.55#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:49:31.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:49:31.55#ibcon#[27=USB\r\n] 2006.246.07:49:31.55#ibcon#*before write, iclass 10, count 0 2006.246.07:49:31.55#ibcon#enter sib2, iclass 10, count 0 2006.246.07:49:31.55#ibcon#flushed, iclass 10, count 0 2006.246.07:49:31.55#ibcon#about to write, iclass 10, count 0 2006.246.07:49:31.55#ibcon#wrote, iclass 10, count 0 2006.246.07:49:31.55#ibcon#about to read 3, iclass 10, count 0 2006.246.07:49:31.58#ibcon#read 3, iclass 10, count 0 2006.246.07:49:31.58#ibcon#about to read 4, iclass 10, count 0 2006.246.07:49:31.58#ibcon#read 4, iclass 10, count 0 2006.246.07:49:31.58#ibcon#about to read 5, iclass 10, count 0 2006.246.07:49:31.58#ibcon#read 5, iclass 10, count 0 2006.246.07:49:31.58#ibcon#about to read 6, iclass 10, count 0 2006.246.07:49:31.58#ibcon#read 6, iclass 10, count 0 2006.246.07:49:31.58#ibcon#end of sib2, iclass 10, count 0 2006.246.07:49:31.58#ibcon#*after write, iclass 10, count 0 2006.246.07:49:31.58#ibcon#*before return 0, iclass 10, count 0 2006.246.07:49:31.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:31.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.07:49:31.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:49:31.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:49:31.58$vc4f8/vblo=4,712.99 2006.246.07:49:31.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.07:49:31.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.07:49:31.58#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:31.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:31.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:31.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:31.58#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:49:31.58#ibcon#first serial, iclass 12, count 0 2006.246.07:49:31.58#ibcon#enter sib2, iclass 12, count 0 2006.246.07:49:31.58#ibcon#flushed, iclass 12, count 0 2006.246.07:49:31.58#ibcon#about to write, iclass 12, count 0 2006.246.07:49:31.58#ibcon#wrote, iclass 12, count 0 2006.246.07:49:31.58#ibcon#about to read 3, iclass 12, count 0 2006.246.07:49:31.60#ibcon#read 3, iclass 12, count 0 2006.246.07:49:31.60#ibcon#about to read 4, iclass 12, count 0 2006.246.07:49:31.60#ibcon#read 4, iclass 12, count 0 2006.246.07:49:31.60#ibcon#about to read 5, iclass 12, count 0 2006.246.07:49:31.60#ibcon#read 5, iclass 12, count 0 2006.246.07:49:31.60#ibcon#about to read 6, iclass 12, count 0 2006.246.07:49:31.60#ibcon#read 6, iclass 12, count 0 2006.246.07:49:31.60#ibcon#end of sib2, iclass 12, count 0 2006.246.07:49:31.60#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:49:31.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:49:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:49:31.60#ibcon#*before write, iclass 12, count 0 2006.246.07:49:31.60#ibcon#enter sib2, iclass 12, count 0 2006.246.07:49:31.60#ibcon#flushed, iclass 12, count 0 2006.246.07:49:31.60#ibcon#about to write, iclass 12, count 0 2006.246.07:49:31.60#ibcon#wrote, iclass 12, count 0 2006.246.07:49:31.60#ibcon#about to read 3, iclass 12, count 0 2006.246.07:49:31.64#ibcon#read 3, iclass 12, count 0 2006.246.07:49:31.64#ibcon#about to read 4, iclass 12, count 0 2006.246.07:49:31.64#ibcon#read 4, iclass 12, count 0 2006.246.07:49:31.64#ibcon#about to read 5, iclass 12, count 0 2006.246.07:49:31.64#ibcon#read 5, iclass 12, count 0 2006.246.07:49:31.64#ibcon#about to read 6, iclass 12, count 0 2006.246.07:49:31.64#ibcon#read 6, iclass 12, count 0 2006.246.07:49:31.64#ibcon#end of sib2, iclass 12, count 0 2006.246.07:49:31.64#ibcon#*after write, iclass 12, count 0 2006.246.07:49:31.64#ibcon#*before return 0, iclass 12, count 0 2006.246.07:49:31.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:31.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.07:49:31.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:49:31.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:49:31.64$vc4f8/vb=4,4 2006.246.07:49:31.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.07:49:31.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.07:49:31.64#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:31.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:31.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:31.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:31.70#ibcon#enter wrdev, iclass 14, count 2 2006.246.07:49:31.70#ibcon#first serial, iclass 14, count 2 2006.246.07:49:31.70#ibcon#enter sib2, iclass 14, count 2 2006.246.07:49:31.70#ibcon#flushed, iclass 14, count 2 2006.246.07:49:31.70#ibcon#about to write, iclass 14, count 2 2006.246.07:49:31.70#ibcon#wrote, iclass 14, count 2 2006.246.07:49:31.70#ibcon#about to read 3, iclass 14, count 2 2006.246.07:49:31.72#ibcon#read 3, iclass 14, count 2 2006.246.07:49:31.72#ibcon#about to read 4, iclass 14, count 2 2006.246.07:49:31.72#ibcon#read 4, iclass 14, count 2 2006.246.07:49:31.72#ibcon#about to read 5, iclass 14, count 2 2006.246.07:49:31.72#ibcon#read 5, iclass 14, count 2 2006.246.07:49:31.72#ibcon#about to read 6, iclass 14, count 2 2006.246.07:49:31.72#ibcon#read 6, iclass 14, count 2 2006.246.07:49:31.72#ibcon#end of sib2, iclass 14, count 2 2006.246.07:49:31.72#ibcon#*mode == 0, iclass 14, count 2 2006.246.07:49:31.72#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.07:49:31.72#ibcon#[27=AT04-04\r\n] 2006.246.07:49:31.72#ibcon#*before write, iclass 14, count 2 2006.246.07:49:31.72#ibcon#enter sib2, iclass 14, count 2 2006.246.07:49:31.72#ibcon#flushed, iclass 14, count 2 2006.246.07:49:31.72#ibcon#about to write, iclass 14, count 2 2006.246.07:49:31.72#ibcon#wrote, iclass 14, count 2 2006.246.07:49:31.72#ibcon#about to read 3, iclass 14, count 2 2006.246.07:49:31.75#ibcon#read 3, iclass 14, count 2 2006.246.07:49:31.75#ibcon#about to read 4, iclass 14, count 2 2006.246.07:49:31.75#ibcon#read 4, iclass 14, count 2 2006.246.07:49:31.75#ibcon#about to read 5, iclass 14, count 2 2006.246.07:49:31.75#ibcon#read 5, iclass 14, count 2 2006.246.07:49:31.75#ibcon#about to read 6, iclass 14, count 2 2006.246.07:49:31.75#ibcon#read 6, iclass 14, count 2 2006.246.07:49:31.75#ibcon#end of sib2, iclass 14, count 2 2006.246.07:49:31.75#ibcon#*after write, iclass 14, count 2 2006.246.07:49:31.75#ibcon#*before return 0, iclass 14, count 2 2006.246.07:49:31.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:31.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.07:49:31.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.07:49:31.75#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:31.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:31.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:31.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:31.87#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:49:31.87#ibcon#first serial, iclass 14, count 0 2006.246.07:49:31.87#ibcon#enter sib2, iclass 14, count 0 2006.246.07:49:31.87#ibcon#flushed, iclass 14, count 0 2006.246.07:49:31.87#ibcon#about to write, iclass 14, count 0 2006.246.07:49:31.87#ibcon#wrote, iclass 14, count 0 2006.246.07:49:31.87#ibcon#about to read 3, iclass 14, count 0 2006.246.07:49:31.89#ibcon#read 3, iclass 14, count 0 2006.246.07:49:31.89#ibcon#about to read 4, iclass 14, count 0 2006.246.07:49:31.89#ibcon#read 4, iclass 14, count 0 2006.246.07:49:31.89#ibcon#about to read 5, iclass 14, count 0 2006.246.07:49:31.89#ibcon#read 5, iclass 14, count 0 2006.246.07:49:31.89#ibcon#about to read 6, iclass 14, count 0 2006.246.07:49:31.89#ibcon#read 6, iclass 14, count 0 2006.246.07:49:31.89#ibcon#end of sib2, iclass 14, count 0 2006.246.07:49:31.89#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:49:31.89#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:49:31.89#ibcon#[27=USB\r\n] 2006.246.07:49:31.89#ibcon#*before write, iclass 14, count 0 2006.246.07:49:31.89#ibcon#enter sib2, iclass 14, count 0 2006.246.07:49:31.89#ibcon#flushed, iclass 14, count 0 2006.246.07:49:31.89#ibcon#about to write, iclass 14, count 0 2006.246.07:49:31.89#ibcon#wrote, iclass 14, count 0 2006.246.07:49:31.89#ibcon#about to read 3, iclass 14, count 0 2006.246.07:49:31.92#ibcon#read 3, iclass 14, count 0 2006.246.07:49:31.92#ibcon#about to read 4, iclass 14, count 0 2006.246.07:49:31.92#ibcon#read 4, iclass 14, count 0 2006.246.07:49:31.92#ibcon#about to read 5, iclass 14, count 0 2006.246.07:49:31.92#ibcon#read 5, iclass 14, count 0 2006.246.07:49:31.92#ibcon#about to read 6, iclass 14, count 0 2006.246.07:49:31.92#ibcon#read 6, iclass 14, count 0 2006.246.07:49:31.92#ibcon#end of sib2, iclass 14, count 0 2006.246.07:49:31.92#ibcon#*after write, iclass 14, count 0 2006.246.07:49:31.92#ibcon#*before return 0, iclass 14, count 0 2006.246.07:49:31.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:31.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.07:49:31.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:49:31.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:49:31.92$vc4f8/vblo=5,744.99 2006.246.07:49:31.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.07:49:31.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.07:49:31.92#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:31.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:31.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:31.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:31.92#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:49:31.92#ibcon#first serial, iclass 16, count 0 2006.246.07:49:31.92#ibcon#enter sib2, iclass 16, count 0 2006.246.07:49:31.92#ibcon#flushed, iclass 16, count 0 2006.246.07:49:31.92#ibcon#about to write, iclass 16, count 0 2006.246.07:49:31.92#ibcon#wrote, iclass 16, count 0 2006.246.07:49:31.92#ibcon#about to read 3, iclass 16, count 0 2006.246.07:49:31.95#ibcon#read 3, iclass 16, count 0 2006.246.07:49:31.95#ibcon#about to read 4, iclass 16, count 0 2006.246.07:49:31.95#ibcon#read 4, iclass 16, count 0 2006.246.07:49:31.95#ibcon#about to read 5, iclass 16, count 0 2006.246.07:49:31.95#ibcon#read 5, iclass 16, count 0 2006.246.07:49:31.95#ibcon#about to read 6, iclass 16, count 0 2006.246.07:49:31.95#ibcon#read 6, iclass 16, count 0 2006.246.07:49:31.95#ibcon#end of sib2, iclass 16, count 0 2006.246.07:49:31.95#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:49:31.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:49:31.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:49:31.95#ibcon#*before write, iclass 16, count 0 2006.246.07:49:31.95#ibcon#enter sib2, iclass 16, count 0 2006.246.07:49:31.95#ibcon#flushed, iclass 16, count 0 2006.246.07:49:31.95#ibcon#about to write, iclass 16, count 0 2006.246.07:49:31.95#ibcon#wrote, iclass 16, count 0 2006.246.07:49:31.95#ibcon#about to read 3, iclass 16, count 0 2006.246.07:49:31.99#ibcon#read 3, iclass 16, count 0 2006.246.07:49:31.99#ibcon#about to read 4, iclass 16, count 0 2006.246.07:49:31.99#ibcon#read 4, iclass 16, count 0 2006.246.07:49:31.99#ibcon#about to read 5, iclass 16, count 0 2006.246.07:49:31.99#ibcon#read 5, iclass 16, count 0 2006.246.07:49:31.99#ibcon#about to read 6, iclass 16, count 0 2006.246.07:49:31.99#ibcon#read 6, iclass 16, count 0 2006.246.07:49:31.99#ibcon#end of sib2, iclass 16, count 0 2006.246.07:49:31.99#ibcon#*after write, iclass 16, count 0 2006.246.07:49:31.99#ibcon#*before return 0, iclass 16, count 0 2006.246.07:49:31.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:31.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.07:49:31.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:49:31.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:49:31.99$vc4f8/vb=5,3 2006.246.07:49:31.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.07:49:31.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.07:49:31.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:31.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:32.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:32.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:32.04#ibcon#enter wrdev, iclass 18, count 2 2006.246.07:49:32.04#ibcon#first serial, iclass 18, count 2 2006.246.07:49:32.04#ibcon#enter sib2, iclass 18, count 2 2006.246.07:49:32.04#ibcon#flushed, iclass 18, count 2 2006.246.07:49:32.04#ibcon#about to write, iclass 18, count 2 2006.246.07:49:32.04#ibcon#wrote, iclass 18, count 2 2006.246.07:49:32.04#ibcon#about to read 3, iclass 18, count 2 2006.246.07:49:32.06#ibcon#read 3, iclass 18, count 2 2006.246.07:49:32.06#ibcon#about to read 4, iclass 18, count 2 2006.246.07:49:32.06#ibcon#read 4, iclass 18, count 2 2006.246.07:49:32.06#ibcon#about to read 5, iclass 18, count 2 2006.246.07:49:32.06#ibcon#read 5, iclass 18, count 2 2006.246.07:49:32.06#ibcon#about to read 6, iclass 18, count 2 2006.246.07:49:32.06#ibcon#read 6, iclass 18, count 2 2006.246.07:49:32.06#ibcon#end of sib2, iclass 18, count 2 2006.246.07:49:32.06#ibcon#*mode == 0, iclass 18, count 2 2006.246.07:49:32.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.07:49:32.06#ibcon#[27=AT05-03\r\n] 2006.246.07:49:32.06#ibcon#*before write, iclass 18, count 2 2006.246.07:49:32.06#ibcon#enter sib2, iclass 18, count 2 2006.246.07:49:32.06#ibcon#flushed, iclass 18, count 2 2006.246.07:49:32.06#ibcon#about to write, iclass 18, count 2 2006.246.07:49:32.06#ibcon#wrote, iclass 18, count 2 2006.246.07:49:32.06#ibcon#about to read 3, iclass 18, count 2 2006.246.07:49:32.09#ibcon#read 3, iclass 18, count 2 2006.246.07:49:32.09#ibcon#about to read 4, iclass 18, count 2 2006.246.07:49:32.09#ibcon#read 4, iclass 18, count 2 2006.246.07:49:32.09#ibcon#about to read 5, iclass 18, count 2 2006.246.07:49:32.09#ibcon#read 5, iclass 18, count 2 2006.246.07:49:32.09#ibcon#about to read 6, iclass 18, count 2 2006.246.07:49:32.09#ibcon#read 6, iclass 18, count 2 2006.246.07:49:32.09#ibcon#end of sib2, iclass 18, count 2 2006.246.07:49:32.09#ibcon#*after write, iclass 18, count 2 2006.246.07:49:32.09#ibcon#*before return 0, iclass 18, count 2 2006.246.07:49:32.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:32.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:49:32.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.07:49:32.09#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:32.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:32.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:32.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:32.21#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:49:32.21#ibcon#first serial, iclass 18, count 0 2006.246.07:49:32.21#ibcon#enter sib2, iclass 18, count 0 2006.246.07:49:32.21#ibcon#flushed, iclass 18, count 0 2006.246.07:49:32.21#ibcon#about to write, iclass 18, count 0 2006.246.07:49:32.21#ibcon#wrote, iclass 18, count 0 2006.246.07:49:32.21#ibcon#about to read 3, iclass 18, count 0 2006.246.07:49:32.23#ibcon#read 3, iclass 18, count 0 2006.246.07:49:32.23#ibcon#about to read 4, iclass 18, count 0 2006.246.07:49:32.23#ibcon#read 4, iclass 18, count 0 2006.246.07:49:32.23#ibcon#about to read 5, iclass 18, count 0 2006.246.07:49:32.23#ibcon#read 5, iclass 18, count 0 2006.246.07:49:32.23#ibcon#about to read 6, iclass 18, count 0 2006.246.07:49:32.23#ibcon#read 6, iclass 18, count 0 2006.246.07:49:32.23#ibcon#end of sib2, iclass 18, count 0 2006.246.07:49:32.23#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:49:32.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:49:32.23#ibcon#[27=USB\r\n] 2006.246.07:49:32.23#ibcon#*before write, iclass 18, count 0 2006.246.07:49:32.23#ibcon#enter sib2, iclass 18, count 0 2006.246.07:49:32.23#ibcon#flushed, iclass 18, count 0 2006.246.07:49:32.23#ibcon#about to write, iclass 18, count 0 2006.246.07:49:32.23#ibcon#wrote, iclass 18, count 0 2006.246.07:49:32.23#ibcon#about to read 3, iclass 18, count 0 2006.246.07:49:32.26#ibcon#read 3, iclass 18, count 0 2006.246.07:49:32.26#ibcon#about to read 4, iclass 18, count 0 2006.246.07:49:32.26#ibcon#read 4, iclass 18, count 0 2006.246.07:49:32.26#ibcon#about to read 5, iclass 18, count 0 2006.246.07:49:32.26#ibcon#read 5, iclass 18, count 0 2006.246.07:49:32.26#ibcon#about to read 6, iclass 18, count 0 2006.246.07:49:32.26#ibcon#read 6, iclass 18, count 0 2006.246.07:49:32.26#ibcon#end of sib2, iclass 18, count 0 2006.246.07:49:32.26#ibcon#*after write, iclass 18, count 0 2006.246.07:49:32.26#ibcon#*before return 0, iclass 18, count 0 2006.246.07:49:32.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:32.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:49:32.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:49:32.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:49:32.26$vc4f8/vblo=6,752.99 2006.246.07:49:32.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.07:49:32.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.07:49:32.26#ibcon#ireg 17 cls_cnt 0 2006.246.07:49:32.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:32.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:32.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:32.26#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:49:32.26#ibcon#first serial, iclass 20, count 0 2006.246.07:49:32.26#ibcon#enter sib2, iclass 20, count 0 2006.246.07:49:32.26#ibcon#flushed, iclass 20, count 0 2006.246.07:49:32.26#ibcon#about to write, iclass 20, count 0 2006.246.07:49:32.26#ibcon#wrote, iclass 20, count 0 2006.246.07:49:32.26#ibcon#about to read 3, iclass 20, count 0 2006.246.07:49:32.28#ibcon#read 3, iclass 20, count 0 2006.246.07:49:32.28#ibcon#about to read 4, iclass 20, count 0 2006.246.07:49:32.28#ibcon#read 4, iclass 20, count 0 2006.246.07:49:32.28#ibcon#about to read 5, iclass 20, count 0 2006.246.07:49:32.28#ibcon#read 5, iclass 20, count 0 2006.246.07:49:32.28#ibcon#about to read 6, iclass 20, count 0 2006.246.07:49:32.28#ibcon#read 6, iclass 20, count 0 2006.246.07:49:32.28#ibcon#end of sib2, iclass 20, count 0 2006.246.07:49:32.28#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:49:32.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:49:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:49:32.28#ibcon#*before write, iclass 20, count 0 2006.246.07:49:32.28#ibcon#enter sib2, iclass 20, count 0 2006.246.07:49:32.28#ibcon#flushed, iclass 20, count 0 2006.246.07:49:32.28#ibcon#about to write, iclass 20, count 0 2006.246.07:49:32.28#ibcon#wrote, iclass 20, count 0 2006.246.07:49:32.28#ibcon#about to read 3, iclass 20, count 0 2006.246.07:49:32.32#ibcon#read 3, iclass 20, count 0 2006.246.07:49:32.32#ibcon#about to read 4, iclass 20, count 0 2006.246.07:49:32.32#ibcon#read 4, iclass 20, count 0 2006.246.07:49:32.32#ibcon#about to read 5, iclass 20, count 0 2006.246.07:49:32.32#ibcon#read 5, iclass 20, count 0 2006.246.07:49:32.32#ibcon#about to read 6, iclass 20, count 0 2006.246.07:49:32.32#ibcon#read 6, iclass 20, count 0 2006.246.07:49:32.32#ibcon#end of sib2, iclass 20, count 0 2006.246.07:49:32.32#ibcon#*after write, iclass 20, count 0 2006.246.07:49:32.32#ibcon#*before return 0, iclass 20, count 0 2006.246.07:49:32.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:32.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.07:49:32.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:49:32.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:49:32.32$vc4f8/vb=6,3 2006.246.07:49:32.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.07:49:32.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.07:49:32.32#ibcon#ireg 11 cls_cnt 2 2006.246.07:49:32.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:32.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:32.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:32.38#ibcon#enter wrdev, iclass 22, count 2 2006.246.07:49:32.38#ibcon#first serial, iclass 22, count 2 2006.246.07:49:32.38#ibcon#enter sib2, iclass 22, count 2 2006.246.07:49:32.38#ibcon#flushed, iclass 22, count 2 2006.246.07:49:32.38#ibcon#about to write, iclass 22, count 2 2006.246.07:49:32.38#ibcon#wrote, iclass 22, count 2 2006.246.07:49:32.38#ibcon#about to read 3, iclass 22, count 2 2006.246.07:49:32.40#ibcon#read 3, iclass 22, count 2 2006.246.07:49:32.40#ibcon#about to read 4, iclass 22, count 2 2006.246.07:49:32.40#ibcon#read 4, iclass 22, count 2 2006.246.07:49:32.40#ibcon#about to read 5, iclass 22, count 2 2006.246.07:49:32.40#ibcon#read 5, iclass 22, count 2 2006.246.07:49:32.40#ibcon#about to read 6, iclass 22, count 2 2006.246.07:49:32.40#ibcon#read 6, iclass 22, count 2 2006.246.07:49:32.40#ibcon#end of sib2, iclass 22, count 2 2006.246.07:49:32.40#ibcon#*mode == 0, iclass 22, count 2 2006.246.07:49:32.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.07:49:32.40#ibcon#[27=AT06-03\r\n] 2006.246.07:49:32.40#ibcon#*before write, iclass 22, count 2 2006.246.07:49:32.40#ibcon#enter sib2, iclass 22, count 2 2006.246.07:49:32.40#ibcon#flushed, iclass 22, count 2 2006.246.07:49:32.40#ibcon#about to write, iclass 22, count 2 2006.246.07:49:32.40#ibcon#wrote, iclass 22, count 2 2006.246.07:49:32.40#ibcon#about to read 3, iclass 22, count 2 2006.246.07:49:32.43#ibcon#read 3, iclass 22, count 2 2006.246.07:49:32.43#ibcon#about to read 4, iclass 22, count 2 2006.246.07:49:32.43#ibcon#read 4, iclass 22, count 2 2006.246.07:49:32.43#ibcon#about to read 5, iclass 22, count 2 2006.246.07:49:32.43#ibcon#read 5, iclass 22, count 2 2006.246.07:49:32.43#ibcon#about to read 6, iclass 22, count 2 2006.246.07:49:32.43#ibcon#read 6, iclass 22, count 2 2006.246.07:49:32.43#ibcon#end of sib2, iclass 22, count 2 2006.246.07:49:32.43#ibcon#*after write, iclass 22, count 2 2006.246.07:49:32.43#ibcon#*before return 0, iclass 22, count 2 2006.246.07:49:32.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:32.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.07:49:32.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.07:49:32.43#ibcon#ireg 7 cls_cnt 0 2006.246.07:49:32.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:32.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:32.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:32.55#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:49:32.55#ibcon#first serial, iclass 22, count 0 2006.246.07:49:32.55#ibcon#enter sib2, iclass 22, count 0 2006.246.07:49:32.55#ibcon#flushed, iclass 22, count 0 2006.246.07:49:32.55#ibcon#about to write, iclass 22, count 0 2006.246.07:49:32.55#ibcon#wrote, iclass 22, count 0 2006.246.07:49:32.55#ibcon#about to read 3, iclass 22, count 0 2006.246.07:49:32.57#ibcon#read 3, iclass 22, count 0 2006.246.07:49:32.57#ibcon#about to read 4, iclass 22, count 0 2006.246.07:49:32.57#ibcon#read 4, iclass 22, count 0 2006.246.07:49:32.57#ibcon#about to read 5, iclass 22, count 0 2006.246.07:49:32.57#ibcon#read 5, iclass 22, count 0 2006.246.07:49:32.57#ibcon#about to read 6, iclass 22, count 0 2006.246.07:49:32.57#ibcon#read 6, iclass 22, count 0 2006.246.07:49:32.57#ibcon#end of sib2, iclass 22, count 0 2006.246.07:49:32.57#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:49:32.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:49:32.57#ibcon#[27=USB\r\n] 2006.246.07:49:32.57#ibcon#*before write, iclass 22, count 0 2006.246.07:49:32.57#ibcon#enter sib2, iclass 22, count 0 2006.246.07:49:32.57#ibcon#flushed, iclass 22, count 0 2006.246.07:49:32.57#ibcon#about to write, iclass 22, count 0 2006.246.07:49:32.57#ibcon#wrote, iclass 22, count 0 2006.246.07:49:32.57#ibcon#about to read 3, iclass 22, count 0 2006.246.07:49:32.60#ibcon#read 3, iclass 22, count 0 2006.246.07:49:32.60#ibcon#about to read 4, iclass 22, count 0 2006.246.07:49:32.60#ibcon#read 4, iclass 22, count 0 2006.246.07:49:32.60#ibcon#about to read 5, iclass 22, count 0 2006.246.07:49:32.60#ibcon#read 5, iclass 22, count 0 2006.246.07:49:32.60#ibcon#about to read 6, iclass 22, count 0 2006.246.07:49:32.60#ibcon#read 6, iclass 22, count 0 2006.246.07:49:32.60#ibcon#end of sib2, iclass 22, count 0 2006.246.07:49:32.60#ibcon#*after write, iclass 22, count 0 2006.246.07:49:32.60#ibcon#*before return 0, iclass 22, count 0 2006.246.07:49:32.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:32.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.07:49:32.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:49:32.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:49:32.60$vc4f8/vabw=wide 2006.246.07:49:32.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.07:49:32.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.07:49:32.60#ibcon#ireg 8 cls_cnt 0 2006.246.07:49:32.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:32.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:32.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:32.60#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:49:32.60#ibcon#first serial, iclass 24, count 0 2006.246.07:49:32.60#ibcon#enter sib2, iclass 24, count 0 2006.246.07:49:32.60#ibcon#flushed, iclass 24, count 0 2006.246.07:49:32.60#ibcon#about to write, iclass 24, count 0 2006.246.07:49:32.60#ibcon#wrote, iclass 24, count 0 2006.246.07:49:32.60#ibcon#about to read 3, iclass 24, count 0 2006.246.07:49:32.62#ibcon#read 3, iclass 24, count 0 2006.246.07:49:32.62#ibcon#about to read 4, iclass 24, count 0 2006.246.07:49:32.62#ibcon#read 4, iclass 24, count 0 2006.246.07:49:32.62#ibcon#about to read 5, iclass 24, count 0 2006.246.07:49:32.62#ibcon#read 5, iclass 24, count 0 2006.246.07:49:32.62#ibcon#about to read 6, iclass 24, count 0 2006.246.07:49:32.62#ibcon#read 6, iclass 24, count 0 2006.246.07:49:32.62#ibcon#end of sib2, iclass 24, count 0 2006.246.07:49:32.62#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:49:32.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:49:32.62#ibcon#[25=BW32\r\n] 2006.246.07:49:32.62#ibcon#*before write, iclass 24, count 0 2006.246.07:49:32.62#ibcon#enter sib2, iclass 24, count 0 2006.246.07:49:32.62#ibcon#flushed, iclass 24, count 0 2006.246.07:49:32.62#ibcon#about to write, iclass 24, count 0 2006.246.07:49:32.62#ibcon#wrote, iclass 24, count 0 2006.246.07:49:32.62#ibcon#about to read 3, iclass 24, count 0 2006.246.07:49:32.65#ibcon#read 3, iclass 24, count 0 2006.246.07:49:32.65#ibcon#about to read 4, iclass 24, count 0 2006.246.07:49:32.65#ibcon#read 4, iclass 24, count 0 2006.246.07:49:32.65#ibcon#about to read 5, iclass 24, count 0 2006.246.07:49:32.65#ibcon#read 5, iclass 24, count 0 2006.246.07:49:32.65#ibcon#about to read 6, iclass 24, count 0 2006.246.07:49:32.65#ibcon#read 6, iclass 24, count 0 2006.246.07:49:32.65#ibcon#end of sib2, iclass 24, count 0 2006.246.07:49:32.65#ibcon#*after write, iclass 24, count 0 2006.246.07:49:32.65#ibcon#*before return 0, iclass 24, count 0 2006.246.07:49:32.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:32.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.07:49:32.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:49:32.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:49:32.65$vc4f8/vbbw=wide 2006.246.07:49:32.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:49:32.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:49:32.65#ibcon#ireg 8 cls_cnt 0 2006.246.07:49:32.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:49:32.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:49:32.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:49:32.72#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:49:32.72#ibcon#first serial, iclass 26, count 0 2006.246.07:49:32.72#ibcon#enter sib2, iclass 26, count 0 2006.246.07:49:32.72#ibcon#flushed, iclass 26, count 0 2006.246.07:49:32.72#ibcon#about to write, iclass 26, count 0 2006.246.07:49:32.72#ibcon#wrote, iclass 26, count 0 2006.246.07:49:32.72#ibcon#about to read 3, iclass 26, count 0 2006.246.07:49:32.74#ibcon#read 3, iclass 26, count 0 2006.246.07:49:32.74#ibcon#about to read 4, iclass 26, count 0 2006.246.07:49:32.74#ibcon#read 4, iclass 26, count 0 2006.246.07:49:32.74#ibcon#about to read 5, iclass 26, count 0 2006.246.07:49:32.74#ibcon#read 5, iclass 26, count 0 2006.246.07:49:32.74#ibcon#about to read 6, iclass 26, count 0 2006.246.07:49:32.74#ibcon#read 6, iclass 26, count 0 2006.246.07:49:32.74#ibcon#end of sib2, iclass 26, count 0 2006.246.07:49:32.74#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:49:32.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:49:32.74#ibcon#[27=BW32\r\n] 2006.246.07:49:32.74#ibcon#*before write, iclass 26, count 0 2006.246.07:49:32.74#ibcon#enter sib2, iclass 26, count 0 2006.246.07:49:32.74#ibcon#flushed, iclass 26, count 0 2006.246.07:49:32.74#ibcon#about to write, iclass 26, count 0 2006.246.07:49:32.74#ibcon#wrote, iclass 26, count 0 2006.246.07:49:32.74#ibcon#about to read 3, iclass 26, count 0 2006.246.07:49:32.77#ibcon#read 3, iclass 26, count 0 2006.246.07:49:32.77#ibcon#about to read 4, iclass 26, count 0 2006.246.07:49:32.77#ibcon#read 4, iclass 26, count 0 2006.246.07:49:32.77#ibcon#about to read 5, iclass 26, count 0 2006.246.07:49:32.77#ibcon#read 5, iclass 26, count 0 2006.246.07:49:32.77#ibcon#about to read 6, iclass 26, count 0 2006.246.07:49:32.77#ibcon#read 6, iclass 26, count 0 2006.246.07:49:32.77#ibcon#end of sib2, iclass 26, count 0 2006.246.07:49:32.77#ibcon#*after write, iclass 26, count 0 2006.246.07:49:32.77#ibcon#*before return 0, iclass 26, count 0 2006.246.07:49:32.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:49:32.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:49:32.77#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:49:32.77#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:49:32.77$4f8m12a/ifd4f 2006.246.07:49:32.77$ifd4f/lo= 2006.246.07:49:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:49:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:49:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:49:32.77$ifd4f/patch= 2006.246.07:49:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:49:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:49:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:49:32.77$4f8m12a/"form=m,16.000,1:2 2006.246.07:49:32.77$4f8m12a/"tpicd 2006.246.07:49:32.77$4f8m12a/echo=off 2006.246.07:49:32.77$4f8m12a/xlog=off 2006.246.07:49:32.77:!2006.246.07:50:20 2006.246.07:50:02.14#trakl#Source acquired 2006.246.07:50:03.14#flagr#flagr/antenna,acquired 2006.246.07:50:20.00:preob 2006.246.07:50:20.14/onsource/TRACKING 2006.246.07:50:20.14:!2006.246.07:50:30 2006.246.07:50:30.00:data_valid=on 2006.246.07:50:30.00:midob 2006.246.07:50:30.14/onsource/TRACKING 2006.246.07:50:30.14/wx/26.74,1005.7,75 2006.246.07:50:30.34/cable/+6.4145E-03 2006.246.07:50:31.43/va/01,08,usb,yes,32,33 2006.246.07:50:31.43/va/02,07,usb,yes,31,33 2006.246.07:50:31.43/va/03,06,usb,yes,33,34 2006.246.07:50:31.43/va/04,07,usb,yes,32,35 2006.246.07:50:31.43/va/05,07,usb,yes,34,36 2006.246.07:50:31.43/va/06,07,usb,yes,30,30 2006.246.07:50:31.43/va/07,07,usb,yes,30,30 2006.246.07:50:31.43/va/08,08,usb,yes,26,25 2006.246.07:50:31.66/valo/01,532.99,yes,locked 2006.246.07:50:31.66/valo/02,572.99,yes,locked 2006.246.07:50:31.66/valo/03,672.99,yes,locked 2006.246.07:50:31.66/valo/04,832.99,yes,locked 2006.246.07:50:31.66/valo/05,652.99,yes,locked 2006.246.07:50:31.66/valo/06,772.99,yes,locked 2006.246.07:50:31.66/valo/07,832.99,yes,locked 2006.246.07:50:31.66/valo/08,852.99,yes,locked 2006.246.07:50:32.75/vb/01,04,usb,yes,31,30 2006.246.07:50:32.75/vb/02,04,usb,yes,33,34 2006.246.07:50:32.75/vb/03,04,usb,yes,29,33 2006.246.07:50:32.75/vb/04,04,usb,yes,30,30 2006.246.07:50:32.75/vb/05,03,usb,yes,35,40 2006.246.07:50:32.75/vb/06,03,usb,yes,36,39 2006.246.07:50:32.75/vb/07,04,usb,yes,31,31 2006.246.07:50:32.75/vb/08,03,usb,yes,36,40 2006.246.07:50:32.99/vblo/01,632.99,yes,locked 2006.246.07:50:32.99/vblo/02,640.99,yes,locked 2006.246.07:50:32.99/vblo/03,656.99,yes,locked 2006.246.07:50:32.99/vblo/04,712.99,yes,locked 2006.246.07:50:32.99/vblo/05,744.99,yes,locked 2006.246.07:50:32.99/vblo/06,752.99,yes,locked 2006.246.07:50:32.99/vblo/07,734.99,yes,locked 2006.246.07:50:32.99/vblo/08,744.99,yes,locked 2006.246.07:50:33.14/vabw/8 2006.246.07:50:33.29/vbbw/8 2006.246.07:50:33.38/xfe/off,on,13.2 2006.246.07:50:33.75/ifatt/23,28,28,28 2006.246.07:50:34.08/fmout-gps/S +4.37E-07 2006.246.07:50:34.12:!2006.246.07:51:50 2006.246.07:51:50.00:data_valid=off 2006.246.07:51:50.00:postob 2006.246.07:51:50.18/cable/+6.4149E-03 2006.246.07:51:50.19/wx/26.74,1005.7,73 2006.246.07:51:51.07/fmout-gps/S +4.36E-07 2006.246.07:51:51.07:scan_name=246-0752,k06246,60 2006.246.07:51:51.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.246.07:51:52.14#flagr#flagr/antenna,new-source 2006.246.07:51:52.15:checkk5 2006.246.07:51:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:51:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:51:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:51:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:51:54.02/chk_obsdata//k5ts1/T2460750??a.dat file size is correct (nominal:640MB, actual:632MB). 2006.246.07:51:54.38/chk_obsdata//k5ts2/T2460750??b.dat file size is correct (nominal:640MB, actual:632MB). 2006.246.07:51:54.75/chk_obsdata//k5ts3/T2460750??c.dat file size is correct (nominal:640MB, actual:632MB). 2006.246.07:51:55.11/chk_obsdata//k5ts4/T2460750??d.dat file size is correct (nominal:640MB, actual:632MB). 2006.246.07:51:55.81/k5log//k5ts1_log_newline 2006.246.07:51:56.52/k5log//k5ts2_log_newline 2006.246.07:51:57.21/k5log//k5ts3_log_newline 2006.246.07:51:57.89/k5log//k5ts4_log_newline 2006.246.07:51:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:51:57.92:4f8m12a=1 2006.246.07:51:57.92$4f8m12a/echo=on 2006.246.07:51:57.92$4f8m12a/pcalon 2006.246.07:51:57.92$pcalon/"no phase cal control is implemented here 2006.246.07:51:57.92$4f8m12a/"tpicd=stop 2006.246.07:51:57.92$4f8m12a/vc4f8 2006.246.07:51:57.92$vc4f8/valo=1,532.99 2006.246.07:51:57.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.07:51:57.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.07:51:57.92#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:57.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:51:57.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:51:57.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:51:57.92#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:51:57.92#ibcon#first serial, iclass 13, count 0 2006.246.07:51:57.92#ibcon#enter sib2, iclass 13, count 0 2006.246.07:51:57.92#ibcon#flushed, iclass 13, count 0 2006.246.07:51:57.92#ibcon#about to write, iclass 13, count 0 2006.246.07:51:57.92#ibcon#wrote, iclass 13, count 0 2006.246.07:51:57.92#ibcon#about to read 3, iclass 13, count 0 2006.246.07:51:57.96#ibcon#read 3, iclass 13, count 0 2006.246.07:51:57.96#ibcon#about to read 4, iclass 13, count 0 2006.246.07:51:57.96#ibcon#read 4, iclass 13, count 0 2006.246.07:51:57.96#ibcon#about to read 5, iclass 13, count 0 2006.246.07:51:57.96#ibcon#read 5, iclass 13, count 0 2006.246.07:51:57.96#ibcon#about to read 6, iclass 13, count 0 2006.246.07:51:57.96#ibcon#read 6, iclass 13, count 0 2006.246.07:51:57.96#ibcon#end of sib2, iclass 13, count 0 2006.246.07:51:57.96#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:51:57.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:51:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:51:57.96#ibcon#*before write, iclass 13, count 0 2006.246.07:51:57.96#ibcon#enter sib2, iclass 13, count 0 2006.246.07:51:57.96#ibcon#flushed, iclass 13, count 0 2006.246.07:51:57.96#ibcon#about to write, iclass 13, count 0 2006.246.07:51:57.96#ibcon#wrote, iclass 13, count 0 2006.246.07:51:57.96#ibcon#about to read 3, iclass 13, count 0 2006.246.07:51:58.00#abcon#<5=/04 3.1 6.3 26.73 741005.7\r\n> 2006.246.07:51:58.01#ibcon#read 3, iclass 13, count 0 2006.246.07:51:58.01#ibcon#about to read 4, iclass 13, count 0 2006.246.07:51:58.01#ibcon#read 4, iclass 13, count 0 2006.246.07:51:58.01#ibcon#about to read 5, iclass 13, count 0 2006.246.07:51:58.01#ibcon#read 5, iclass 13, count 0 2006.246.07:51:58.01#ibcon#about to read 6, iclass 13, count 0 2006.246.07:51:58.01#ibcon#read 6, iclass 13, count 0 2006.246.07:51:58.01#ibcon#end of sib2, iclass 13, count 0 2006.246.07:51:58.01#ibcon#*after write, iclass 13, count 0 2006.246.07:51:58.01#ibcon#*before return 0, iclass 13, count 0 2006.246.07:51:58.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:51:58.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:51:58.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:51:58.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:51:58.01$vc4f8/va=1,8 2006.246.07:51:58.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.07:51:58.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.07:51:58.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:51:58.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:51:58.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:51:58.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:51:58.01#ibcon#enter wrdev, iclass 18, count 2 2006.246.07:51:58.01#ibcon#first serial, iclass 18, count 2 2006.246.07:51:58.01#ibcon#enter sib2, iclass 18, count 2 2006.246.07:51:58.01#ibcon#flushed, iclass 18, count 2 2006.246.07:51:58.01#ibcon#about to write, iclass 18, count 2 2006.246.07:51:58.01#ibcon#wrote, iclass 18, count 2 2006.246.07:51:58.01#ibcon#about to read 3, iclass 18, count 2 2006.246.07:51:58.02#abcon#{5=INTERFACE CLEAR} 2006.246.07:51:58.04#ibcon#read 3, iclass 18, count 2 2006.246.07:51:58.04#ibcon#about to read 4, iclass 18, count 2 2006.246.07:51:58.04#ibcon#read 4, iclass 18, count 2 2006.246.07:51:58.04#ibcon#about to read 5, iclass 18, count 2 2006.246.07:51:58.04#ibcon#read 5, iclass 18, count 2 2006.246.07:51:58.04#ibcon#about to read 6, iclass 18, count 2 2006.246.07:51:58.04#ibcon#read 6, iclass 18, count 2 2006.246.07:51:58.04#ibcon#end of sib2, iclass 18, count 2 2006.246.07:51:58.04#ibcon#*mode == 0, iclass 18, count 2 2006.246.07:51:58.04#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.07:51:58.04#ibcon#[25=AT01-08\r\n] 2006.246.07:51:58.04#ibcon#*before write, iclass 18, count 2 2006.246.07:51:58.04#ibcon#enter sib2, iclass 18, count 2 2006.246.07:51:58.04#ibcon#flushed, iclass 18, count 2 2006.246.07:51:58.04#ibcon#about to write, iclass 18, count 2 2006.246.07:51:58.04#ibcon#wrote, iclass 18, count 2 2006.246.07:51:58.04#ibcon#about to read 3, iclass 18, count 2 2006.246.07:51:58.07#ibcon#read 3, iclass 18, count 2 2006.246.07:51:58.07#ibcon#about to read 4, iclass 18, count 2 2006.246.07:51:58.07#ibcon#read 4, iclass 18, count 2 2006.246.07:51:58.07#ibcon#about to read 5, iclass 18, count 2 2006.246.07:51:58.07#ibcon#read 5, iclass 18, count 2 2006.246.07:51:58.07#ibcon#about to read 6, iclass 18, count 2 2006.246.07:51:58.07#ibcon#read 6, iclass 18, count 2 2006.246.07:51:58.07#ibcon#end of sib2, iclass 18, count 2 2006.246.07:51:58.07#ibcon#*after write, iclass 18, count 2 2006.246.07:51:58.07#ibcon#*before return 0, iclass 18, count 2 2006.246.07:51:58.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:51:58.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.07:51:58.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.07:51:58.07#ibcon#ireg 7 cls_cnt 0 2006.246.07:51:58.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:51:58.08#abcon#[5=S1D000X0/0*\r\n] 2006.246.07:51:58.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:51:58.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:51:58.19#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:51:58.19#ibcon#first serial, iclass 18, count 0 2006.246.07:51:58.19#ibcon#enter sib2, iclass 18, count 0 2006.246.07:51:58.19#ibcon#flushed, iclass 18, count 0 2006.246.07:51:58.19#ibcon#about to write, iclass 18, count 0 2006.246.07:51:58.19#ibcon#wrote, iclass 18, count 0 2006.246.07:51:58.19#ibcon#about to read 3, iclass 18, count 0 2006.246.07:51:58.23#ibcon#read 3, iclass 18, count 0 2006.246.07:51:58.23#ibcon#about to read 4, iclass 18, count 0 2006.246.07:51:58.23#ibcon#read 4, iclass 18, count 0 2006.246.07:51:58.23#ibcon#about to read 5, iclass 18, count 0 2006.246.07:51:58.23#ibcon#read 5, iclass 18, count 0 2006.246.07:51:58.23#ibcon#about to read 6, iclass 18, count 0 2006.246.07:51:58.23#ibcon#read 6, iclass 18, count 0 2006.246.07:51:58.23#ibcon#end of sib2, iclass 18, count 0 2006.246.07:51:58.23#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:51:58.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:51:58.23#ibcon#[25=USB\r\n] 2006.246.07:51:58.23#ibcon#*before write, iclass 18, count 0 2006.246.07:51:58.23#ibcon#enter sib2, iclass 18, count 0 2006.246.07:51:58.23#ibcon#flushed, iclass 18, count 0 2006.246.07:51:58.23#ibcon#about to write, iclass 18, count 0 2006.246.07:51:58.23#ibcon#wrote, iclass 18, count 0 2006.246.07:51:58.23#ibcon#about to read 3, iclass 18, count 0 2006.246.07:51:58.25#ibcon#read 3, iclass 18, count 0 2006.246.07:51:58.25#ibcon#about to read 4, iclass 18, count 0 2006.246.07:51:58.25#ibcon#read 4, iclass 18, count 0 2006.246.07:51:58.25#ibcon#about to read 5, iclass 18, count 0 2006.246.07:51:58.25#ibcon#read 5, iclass 18, count 0 2006.246.07:51:58.25#ibcon#about to read 6, iclass 18, count 0 2006.246.07:51:58.25#ibcon#read 6, iclass 18, count 0 2006.246.07:51:58.25#ibcon#end of sib2, iclass 18, count 0 2006.246.07:51:58.25#ibcon#*after write, iclass 18, count 0 2006.246.07:51:58.25#ibcon#*before return 0, iclass 18, count 0 2006.246.07:51:58.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:51:58.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.07:51:58.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:51:58.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:51:58.25$vc4f8/valo=2,572.99 2006.246.07:51:58.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.07:51:58.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.07:51:58.25#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:58.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:51:58.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:51:58.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:51:58.25#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:51:58.25#ibcon#first serial, iclass 21, count 0 2006.246.07:51:58.25#ibcon#enter sib2, iclass 21, count 0 2006.246.07:51:58.25#ibcon#flushed, iclass 21, count 0 2006.246.07:51:58.25#ibcon#about to write, iclass 21, count 0 2006.246.07:51:58.25#ibcon#wrote, iclass 21, count 0 2006.246.07:51:58.25#ibcon#about to read 3, iclass 21, count 0 2006.246.07:51:58.27#ibcon#read 3, iclass 21, count 0 2006.246.07:51:58.27#ibcon#about to read 4, iclass 21, count 0 2006.246.07:51:58.27#ibcon#read 4, iclass 21, count 0 2006.246.07:51:58.27#ibcon#about to read 5, iclass 21, count 0 2006.246.07:51:58.27#ibcon#read 5, iclass 21, count 0 2006.246.07:51:58.27#ibcon#about to read 6, iclass 21, count 0 2006.246.07:51:58.27#ibcon#read 6, iclass 21, count 0 2006.246.07:51:58.27#ibcon#end of sib2, iclass 21, count 0 2006.246.07:51:58.27#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:51:58.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:51:58.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:51:58.27#ibcon#*before write, iclass 21, count 0 2006.246.07:51:58.27#ibcon#enter sib2, iclass 21, count 0 2006.246.07:51:58.27#ibcon#flushed, iclass 21, count 0 2006.246.07:51:58.27#ibcon#about to write, iclass 21, count 0 2006.246.07:51:58.27#ibcon#wrote, iclass 21, count 0 2006.246.07:51:58.27#ibcon#about to read 3, iclass 21, count 0 2006.246.07:51:58.31#ibcon#read 3, iclass 21, count 0 2006.246.07:51:58.31#ibcon#about to read 4, iclass 21, count 0 2006.246.07:51:58.31#ibcon#read 4, iclass 21, count 0 2006.246.07:51:58.31#ibcon#about to read 5, iclass 21, count 0 2006.246.07:51:58.31#ibcon#read 5, iclass 21, count 0 2006.246.07:51:58.31#ibcon#about to read 6, iclass 21, count 0 2006.246.07:51:58.31#ibcon#read 6, iclass 21, count 0 2006.246.07:51:58.31#ibcon#end of sib2, iclass 21, count 0 2006.246.07:51:58.31#ibcon#*after write, iclass 21, count 0 2006.246.07:51:58.31#ibcon#*before return 0, iclass 21, count 0 2006.246.07:51:58.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:51:58.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:51:58.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:51:58.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:51:58.31$vc4f8/va=2,7 2006.246.07:51:58.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.07:51:58.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.07:51:58.31#ibcon#ireg 11 cls_cnt 2 2006.246.07:51:58.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:51:58.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:51:58.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:51:58.37#ibcon#enter wrdev, iclass 23, count 2 2006.246.07:51:58.37#ibcon#first serial, iclass 23, count 2 2006.246.07:51:58.37#ibcon#enter sib2, iclass 23, count 2 2006.246.07:51:58.37#ibcon#flushed, iclass 23, count 2 2006.246.07:51:58.37#ibcon#about to write, iclass 23, count 2 2006.246.07:51:58.37#ibcon#wrote, iclass 23, count 2 2006.246.07:51:58.37#ibcon#about to read 3, iclass 23, count 2 2006.246.07:51:58.39#ibcon#read 3, iclass 23, count 2 2006.246.07:51:58.39#ibcon#about to read 4, iclass 23, count 2 2006.246.07:51:58.39#ibcon#read 4, iclass 23, count 2 2006.246.07:51:58.39#ibcon#about to read 5, iclass 23, count 2 2006.246.07:51:58.39#ibcon#read 5, iclass 23, count 2 2006.246.07:51:58.39#ibcon#about to read 6, iclass 23, count 2 2006.246.07:51:58.39#ibcon#read 6, iclass 23, count 2 2006.246.07:51:58.39#ibcon#end of sib2, iclass 23, count 2 2006.246.07:51:58.39#ibcon#*mode == 0, iclass 23, count 2 2006.246.07:51:58.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.07:51:58.39#ibcon#[25=AT02-07\r\n] 2006.246.07:51:58.39#ibcon#*before write, iclass 23, count 2 2006.246.07:51:58.39#ibcon#enter sib2, iclass 23, count 2 2006.246.07:51:58.39#ibcon#flushed, iclass 23, count 2 2006.246.07:51:58.39#ibcon#about to write, iclass 23, count 2 2006.246.07:51:58.39#ibcon#wrote, iclass 23, count 2 2006.246.07:51:58.39#ibcon#about to read 3, iclass 23, count 2 2006.246.07:51:58.42#ibcon#read 3, iclass 23, count 2 2006.246.07:51:58.42#ibcon#about to read 4, iclass 23, count 2 2006.246.07:51:58.42#ibcon#read 4, iclass 23, count 2 2006.246.07:51:58.42#ibcon#about to read 5, iclass 23, count 2 2006.246.07:51:58.42#ibcon#read 5, iclass 23, count 2 2006.246.07:51:58.42#ibcon#about to read 6, iclass 23, count 2 2006.246.07:51:58.42#ibcon#read 6, iclass 23, count 2 2006.246.07:51:58.42#ibcon#end of sib2, iclass 23, count 2 2006.246.07:51:58.42#ibcon#*after write, iclass 23, count 2 2006.246.07:51:58.42#ibcon#*before return 0, iclass 23, count 2 2006.246.07:51:58.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:51:58.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:51:58.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.07:51:58.42#ibcon#ireg 7 cls_cnt 0 2006.246.07:51:58.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:51:58.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:51:58.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:51:58.54#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:51:58.54#ibcon#first serial, iclass 23, count 0 2006.246.07:51:58.54#ibcon#enter sib2, iclass 23, count 0 2006.246.07:51:58.54#ibcon#flushed, iclass 23, count 0 2006.246.07:51:58.54#ibcon#about to write, iclass 23, count 0 2006.246.07:51:58.54#ibcon#wrote, iclass 23, count 0 2006.246.07:51:58.54#ibcon#about to read 3, iclass 23, count 0 2006.246.07:51:58.56#ibcon#read 3, iclass 23, count 0 2006.246.07:51:58.56#ibcon#about to read 4, iclass 23, count 0 2006.246.07:51:58.56#ibcon#read 4, iclass 23, count 0 2006.246.07:51:58.56#ibcon#about to read 5, iclass 23, count 0 2006.246.07:51:58.56#ibcon#read 5, iclass 23, count 0 2006.246.07:51:58.56#ibcon#about to read 6, iclass 23, count 0 2006.246.07:51:58.56#ibcon#read 6, iclass 23, count 0 2006.246.07:51:58.56#ibcon#end of sib2, iclass 23, count 0 2006.246.07:51:58.56#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:51:58.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:51:58.56#ibcon#[25=USB\r\n] 2006.246.07:51:58.56#ibcon#*before write, iclass 23, count 0 2006.246.07:51:58.56#ibcon#enter sib2, iclass 23, count 0 2006.246.07:51:58.56#ibcon#flushed, iclass 23, count 0 2006.246.07:51:58.56#ibcon#about to write, iclass 23, count 0 2006.246.07:51:58.56#ibcon#wrote, iclass 23, count 0 2006.246.07:51:58.56#ibcon#about to read 3, iclass 23, count 0 2006.246.07:51:58.59#ibcon#read 3, iclass 23, count 0 2006.246.07:51:58.59#ibcon#about to read 4, iclass 23, count 0 2006.246.07:51:58.59#ibcon#read 4, iclass 23, count 0 2006.246.07:51:58.59#ibcon#about to read 5, iclass 23, count 0 2006.246.07:51:58.59#ibcon#read 5, iclass 23, count 0 2006.246.07:51:58.59#ibcon#about to read 6, iclass 23, count 0 2006.246.07:51:58.59#ibcon#read 6, iclass 23, count 0 2006.246.07:51:58.59#ibcon#end of sib2, iclass 23, count 0 2006.246.07:51:58.59#ibcon#*after write, iclass 23, count 0 2006.246.07:51:58.59#ibcon#*before return 0, iclass 23, count 0 2006.246.07:51:58.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:51:58.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:51:58.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:51:58.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:51:58.59$vc4f8/valo=3,672.99 2006.246.07:51:58.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.07:51:58.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.07:51:58.59#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:58.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:51:58.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:51:58.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:51:58.59#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:51:58.59#ibcon#first serial, iclass 25, count 0 2006.246.07:51:58.59#ibcon#enter sib2, iclass 25, count 0 2006.246.07:51:58.59#ibcon#flushed, iclass 25, count 0 2006.246.07:51:58.59#ibcon#about to write, iclass 25, count 0 2006.246.07:51:58.59#ibcon#wrote, iclass 25, count 0 2006.246.07:51:58.59#ibcon#about to read 3, iclass 25, count 0 2006.246.07:51:58.62#ibcon#read 3, iclass 25, count 0 2006.246.07:51:58.62#ibcon#about to read 4, iclass 25, count 0 2006.246.07:51:58.62#ibcon#read 4, iclass 25, count 0 2006.246.07:51:58.62#ibcon#about to read 5, iclass 25, count 0 2006.246.07:51:58.62#ibcon#read 5, iclass 25, count 0 2006.246.07:51:58.62#ibcon#about to read 6, iclass 25, count 0 2006.246.07:51:58.62#ibcon#read 6, iclass 25, count 0 2006.246.07:51:58.62#ibcon#end of sib2, iclass 25, count 0 2006.246.07:51:58.62#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:51:58.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:51:58.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:51:58.62#ibcon#*before write, iclass 25, count 0 2006.246.07:51:58.62#ibcon#enter sib2, iclass 25, count 0 2006.246.07:51:58.62#ibcon#flushed, iclass 25, count 0 2006.246.07:51:58.62#ibcon#about to write, iclass 25, count 0 2006.246.07:51:58.62#ibcon#wrote, iclass 25, count 0 2006.246.07:51:58.62#ibcon#about to read 3, iclass 25, count 0 2006.246.07:51:58.66#ibcon#read 3, iclass 25, count 0 2006.246.07:51:58.66#ibcon#about to read 4, iclass 25, count 0 2006.246.07:51:58.66#ibcon#read 4, iclass 25, count 0 2006.246.07:51:58.66#ibcon#about to read 5, iclass 25, count 0 2006.246.07:51:58.66#ibcon#read 5, iclass 25, count 0 2006.246.07:51:58.66#ibcon#about to read 6, iclass 25, count 0 2006.246.07:51:58.66#ibcon#read 6, iclass 25, count 0 2006.246.07:51:58.66#ibcon#end of sib2, iclass 25, count 0 2006.246.07:51:58.66#ibcon#*after write, iclass 25, count 0 2006.246.07:51:58.66#ibcon#*before return 0, iclass 25, count 0 2006.246.07:51:58.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:51:58.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:51:58.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:51:58.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:51:58.66$vc4f8/va=3,6 2006.246.07:51:58.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.07:51:58.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.07:51:58.66#ibcon#ireg 11 cls_cnt 2 2006.246.07:51:58.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:51:58.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:51:58.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:51:58.71#ibcon#enter wrdev, iclass 27, count 2 2006.246.07:51:58.71#ibcon#first serial, iclass 27, count 2 2006.246.07:51:58.71#ibcon#enter sib2, iclass 27, count 2 2006.246.07:51:58.71#ibcon#flushed, iclass 27, count 2 2006.246.07:51:58.71#ibcon#about to write, iclass 27, count 2 2006.246.07:51:58.71#ibcon#wrote, iclass 27, count 2 2006.246.07:51:58.71#ibcon#about to read 3, iclass 27, count 2 2006.246.07:51:58.73#ibcon#read 3, iclass 27, count 2 2006.246.07:51:58.73#ibcon#about to read 4, iclass 27, count 2 2006.246.07:51:58.73#ibcon#read 4, iclass 27, count 2 2006.246.07:51:58.73#ibcon#about to read 5, iclass 27, count 2 2006.246.07:51:58.73#ibcon#read 5, iclass 27, count 2 2006.246.07:51:58.73#ibcon#about to read 6, iclass 27, count 2 2006.246.07:51:58.73#ibcon#read 6, iclass 27, count 2 2006.246.07:51:58.73#ibcon#end of sib2, iclass 27, count 2 2006.246.07:51:58.73#ibcon#*mode == 0, iclass 27, count 2 2006.246.07:51:58.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.07:51:58.73#ibcon#[25=AT03-06\r\n] 2006.246.07:51:58.73#ibcon#*before write, iclass 27, count 2 2006.246.07:51:58.73#ibcon#enter sib2, iclass 27, count 2 2006.246.07:51:58.73#ibcon#flushed, iclass 27, count 2 2006.246.07:51:58.73#ibcon#about to write, iclass 27, count 2 2006.246.07:51:58.73#ibcon#wrote, iclass 27, count 2 2006.246.07:51:58.73#ibcon#about to read 3, iclass 27, count 2 2006.246.07:51:58.76#ibcon#read 3, iclass 27, count 2 2006.246.07:51:58.76#ibcon#about to read 4, iclass 27, count 2 2006.246.07:51:58.76#ibcon#read 4, iclass 27, count 2 2006.246.07:51:58.76#ibcon#about to read 5, iclass 27, count 2 2006.246.07:51:58.76#ibcon#read 5, iclass 27, count 2 2006.246.07:51:58.76#ibcon#about to read 6, iclass 27, count 2 2006.246.07:51:58.76#ibcon#read 6, iclass 27, count 2 2006.246.07:51:58.76#ibcon#end of sib2, iclass 27, count 2 2006.246.07:51:58.76#ibcon#*after write, iclass 27, count 2 2006.246.07:51:58.76#ibcon#*before return 0, iclass 27, count 2 2006.246.07:51:58.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:51:58.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:51:58.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.07:51:58.76#ibcon#ireg 7 cls_cnt 0 2006.246.07:51:58.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:51:58.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:51:58.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:51:58.88#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:51:58.88#ibcon#first serial, iclass 27, count 0 2006.246.07:51:58.88#ibcon#enter sib2, iclass 27, count 0 2006.246.07:51:58.88#ibcon#flushed, iclass 27, count 0 2006.246.07:51:58.88#ibcon#about to write, iclass 27, count 0 2006.246.07:51:58.88#ibcon#wrote, iclass 27, count 0 2006.246.07:51:58.88#ibcon#about to read 3, iclass 27, count 0 2006.246.07:51:58.90#ibcon#read 3, iclass 27, count 0 2006.246.07:51:58.90#ibcon#about to read 4, iclass 27, count 0 2006.246.07:51:58.90#ibcon#read 4, iclass 27, count 0 2006.246.07:51:58.90#ibcon#about to read 5, iclass 27, count 0 2006.246.07:51:58.90#ibcon#read 5, iclass 27, count 0 2006.246.07:51:58.90#ibcon#about to read 6, iclass 27, count 0 2006.246.07:51:58.90#ibcon#read 6, iclass 27, count 0 2006.246.07:51:58.90#ibcon#end of sib2, iclass 27, count 0 2006.246.07:51:58.90#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:51:58.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:51:58.90#ibcon#[25=USB\r\n] 2006.246.07:51:58.90#ibcon#*before write, iclass 27, count 0 2006.246.07:51:58.90#ibcon#enter sib2, iclass 27, count 0 2006.246.07:51:58.90#ibcon#flushed, iclass 27, count 0 2006.246.07:51:58.90#ibcon#about to write, iclass 27, count 0 2006.246.07:51:58.90#ibcon#wrote, iclass 27, count 0 2006.246.07:51:58.90#ibcon#about to read 3, iclass 27, count 0 2006.246.07:51:58.93#ibcon#read 3, iclass 27, count 0 2006.246.07:51:58.93#ibcon#about to read 4, iclass 27, count 0 2006.246.07:51:58.93#ibcon#read 4, iclass 27, count 0 2006.246.07:51:58.93#ibcon#about to read 5, iclass 27, count 0 2006.246.07:51:58.93#ibcon#read 5, iclass 27, count 0 2006.246.07:51:58.93#ibcon#about to read 6, iclass 27, count 0 2006.246.07:51:58.93#ibcon#read 6, iclass 27, count 0 2006.246.07:51:58.93#ibcon#end of sib2, iclass 27, count 0 2006.246.07:51:58.93#ibcon#*after write, iclass 27, count 0 2006.246.07:51:58.93#ibcon#*before return 0, iclass 27, count 0 2006.246.07:51:58.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:51:58.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:51:58.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:51:58.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:51:58.93$vc4f8/valo=4,832.99 2006.246.07:51:58.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:51:58.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:51:58.93#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:58.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:51:58.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:51:58.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:51:58.93#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:51:58.93#ibcon#first serial, iclass 29, count 0 2006.246.07:51:58.93#ibcon#enter sib2, iclass 29, count 0 2006.246.07:51:58.93#ibcon#flushed, iclass 29, count 0 2006.246.07:51:58.93#ibcon#about to write, iclass 29, count 0 2006.246.07:51:58.93#ibcon#wrote, iclass 29, count 0 2006.246.07:51:58.93#ibcon#about to read 3, iclass 29, count 0 2006.246.07:51:58.95#ibcon#read 3, iclass 29, count 0 2006.246.07:51:58.95#ibcon#about to read 4, iclass 29, count 0 2006.246.07:51:58.95#ibcon#read 4, iclass 29, count 0 2006.246.07:51:58.95#ibcon#about to read 5, iclass 29, count 0 2006.246.07:51:58.95#ibcon#read 5, iclass 29, count 0 2006.246.07:51:58.95#ibcon#about to read 6, iclass 29, count 0 2006.246.07:51:58.95#ibcon#read 6, iclass 29, count 0 2006.246.07:51:58.95#ibcon#end of sib2, iclass 29, count 0 2006.246.07:51:58.95#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:51:58.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:51:58.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:51:58.95#ibcon#*before write, iclass 29, count 0 2006.246.07:51:58.95#ibcon#enter sib2, iclass 29, count 0 2006.246.07:51:58.95#ibcon#flushed, iclass 29, count 0 2006.246.07:51:58.95#ibcon#about to write, iclass 29, count 0 2006.246.07:51:58.95#ibcon#wrote, iclass 29, count 0 2006.246.07:51:58.95#ibcon#about to read 3, iclass 29, count 0 2006.246.07:51:58.99#ibcon#read 3, iclass 29, count 0 2006.246.07:51:58.99#ibcon#about to read 4, iclass 29, count 0 2006.246.07:51:58.99#ibcon#read 4, iclass 29, count 0 2006.246.07:51:58.99#ibcon#about to read 5, iclass 29, count 0 2006.246.07:51:58.99#ibcon#read 5, iclass 29, count 0 2006.246.07:51:58.99#ibcon#about to read 6, iclass 29, count 0 2006.246.07:51:58.99#ibcon#read 6, iclass 29, count 0 2006.246.07:51:58.99#ibcon#end of sib2, iclass 29, count 0 2006.246.07:51:58.99#ibcon#*after write, iclass 29, count 0 2006.246.07:51:58.99#ibcon#*before return 0, iclass 29, count 0 2006.246.07:51:58.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:51:58.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:51:58.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:51:58.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:51:58.99$vc4f8/va=4,7 2006.246.07:51:58.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.07:51:58.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.07:51:58.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:51:58.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:51:59.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:51:59.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:51:59.05#ibcon#enter wrdev, iclass 31, count 2 2006.246.07:51:59.05#ibcon#first serial, iclass 31, count 2 2006.246.07:51:59.05#ibcon#enter sib2, iclass 31, count 2 2006.246.07:51:59.05#ibcon#flushed, iclass 31, count 2 2006.246.07:51:59.05#ibcon#about to write, iclass 31, count 2 2006.246.07:51:59.05#ibcon#wrote, iclass 31, count 2 2006.246.07:51:59.05#ibcon#about to read 3, iclass 31, count 2 2006.246.07:51:59.07#ibcon#read 3, iclass 31, count 2 2006.246.07:51:59.07#ibcon#about to read 4, iclass 31, count 2 2006.246.07:51:59.07#ibcon#read 4, iclass 31, count 2 2006.246.07:51:59.07#ibcon#about to read 5, iclass 31, count 2 2006.246.07:51:59.07#ibcon#read 5, iclass 31, count 2 2006.246.07:51:59.07#ibcon#about to read 6, iclass 31, count 2 2006.246.07:51:59.07#ibcon#read 6, iclass 31, count 2 2006.246.07:51:59.07#ibcon#end of sib2, iclass 31, count 2 2006.246.07:51:59.07#ibcon#*mode == 0, iclass 31, count 2 2006.246.07:51:59.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.07:51:59.07#ibcon#[25=AT04-07\r\n] 2006.246.07:51:59.07#ibcon#*before write, iclass 31, count 2 2006.246.07:51:59.07#ibcon#enter sib2, iclass 31, count 2 2006.246.07:51:59.07#ibcon#flushed, iclass 31, count 2 2006.246.07:51:59.07#ibcon#about to write, iclass 31, count 2 2006.246.07:51:59.07#ibcon#wrote, iclass 31, count 2 2006.246.07:51:59.07#ibcon#about to read 3, iclass 31, count 2 2006.246.07:51:59.10#ibcon#read 3, iclass 31, count 2 2006.246.07:51:59.10#ibcon#about to read 4, iclass 31, count 2 2006.246.07:51:59.10#ibcon#read 4, iclass 31, count 2 2006.246.07:51:59.10#ibcon#about to read 5, iclass 31, count 2 2006.246.07:51:59.10#ibcon#read 5, iclass 31, count 2 2006.246.07:51:59.10#ibcon#about to read 6, iclass 31, count 2 2006.246.07:51:59.10#ibcon#read 6, iclass 31, count 2 2006.246.07:51:59.10#ibcon#end of sib2, iclass 31, count 2 2006.246.07:51:59.10#ibcon#*after write, iclass 31, count 2 2006.246.07:51:59.10#ibcon#*before return 0, iclass 31, count 2 2006.246.07:51:59.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:51:59.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:51:59.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.07:51:59.10#ibcon#ireg 7 cls_cnt 0 2006.246.07:51:59.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:51:59.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:51:59.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:51:59.22#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:51:59.22#ibcon#first serial, iclass 31, count 0 2006.246.07:51:59.22#ibcon#enter sib2, iclass 31, count 0 2006.246.07:51:59.22#ibcon#flushed, iclass 31, count 0 2006.246.07:51:59.22#ibcon#about to write, iclass 31, count 0 2006.246.07:51:59.22#ibcon#wrote, iclass 31, count 0 2006.246.07:51:59.22#ibcon#about to read 3, iclass 31, count 0 2006.246.07:51:59.24#ibcon#read 3, iclass 31, count 0 2006.246.07:51:59.24#ibcon#about to read 4, iclass 31, count 0 2006.246.07:51:59.24#ibcon#read 4, iclass 31, count 0 2006.246.07:51:59.24#ibcon#about to read 5, iclass 31, count 0 2006.246.07:51:59.24#ibcon#read 5, iclass 31, count 0 2006.246.07:51:59.24#ibcon#about to read 6, iclass 31, count 0 2006.246.07:51:59.24#ibcon#read 6, iclass 31, count 0 2006.246.07:51:59.24#ibcon#end of sib2, iclass 31, count 0 2006.246.07:51:59.24#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:51:59.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:51:59.24#ibcon#[25=USB\r\n] 2006.246.07:51:59.24#ibcon#*before write, iclass 31, count 0 2006.246.07:51:59.24#ibcon#enter sib2, iclass 31, count 0 2006.246.07:51:59.24#ibcon#flushed, iclass 31, count 0 2006.246.07:51:59.24#ibcon#about to write, iclass 31, count 0 2006.246.07:51:59.24#ibcon#wrote, iclass 31, count 0 2006.246.07:51:59.24#ibcon#about to read 3, iclass 31, count 0 2006.246.07:51:59.27#ibcon#read 3, iclass 31, count 0 2006.246.07:51:59.27#ibcon#about to read 4, iclass 31, count 0 2006.246.07:51:59.27#ibcon#read 4, iclass 31, count 0 2006.246.07:51:59.27#ibcon#about to read 5, iclass 31, count 0 2006.246.07:51:59.27#ibcon#read 5, iclass 31, count 0 2006.246.07:51:59.27#ibcon#about to read 6, iclass 31, count 0 2006.246.07:51:59.27#ibcon#read 6, iclass 31, count 0 2006.246.07:51:59.27#ibcon#end of sib2, iclass 31, count 0 2006.246.07:51:59.27#ibcon#*after write, iclass 31, count 0 2006.246.07:51:59.27#ibcon#*before return 0, iclass 31, count 0 2006.246.07:51:59.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:51:59.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:51:59.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:51:59.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:51:59.27$vc4f8/valo=5,652.99 2006.246.07:51:59.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.07:51:59.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.07:51:59.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:59.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:51:59.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:51:59.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:51:59.27#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:51:59.27#ibcon#first serial, iclass 33, count 0 2006.246.07:51:59.27#ibcon#enter sib2, iclass 33, count 0 2006.246.07:51:59.27#ibcon#flushed, iclass 33, count 0 2006.246.07:51:59.27#ibcon#about to write, iclass 33, count 0 2006.246.07:51:59.27#ibcon#wrote, iclass 33, count 0 2006.246.07:51:59.27#ibcon#about to read 3, iclass 33, count 0 2006.246.07:51:59.29#ibcon#read 3, iclass 33, count 0 2006.246.07:51:59.29#ibcon#about to read 4, iclass 33, count 0 2006.246.07:51:59.29#ibcon#read 4, iclass 33, count 0 2006.246.07:51:59.29#ibcon#about to read 5, iclass 33, count 0 2006.246.07:51:59.29#ibcon#read 5, iclass 33, count 0 2006.246.07:51:59.29#ibcon#about to read 6, iclass 33, count 0 2006.246.07:51:59.29#ibcon#read 6, iclass 33, count 0 2006.246.07:51:59.29#ibcon#end of sib2, iclass 33, count 0 2006.246.07:51:59.29#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:51:59.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:51:59.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:51:59.29#ibcon#*before write, iclass 33, count 0 2006.246.07:51:59.29#ibcon#enter sib2, iclass 33, count 0 2006.246.07:51:59.29#ibcon#flushed, iclass 33, count 0 2006.246.07:51:59.29#ibcon#about to write, iclass 33, count 0 2006.246.07:51:59.29#ibcon#wrote, iclass 33, count 0 2006.246.07:51:59.29#ibcon#about to read 3, iclass 33, count 0 2006.246.07:51:59.33#ibcon#read 3, iclass 33, count 0 2006.246.07:51:59.33#ibcon#about to read 4, iclass 33, count 0 2006.246.07:51:59.33#ibcon#read 4, iclass 33, count 0 2006.246.07:51:59.33#ibcon#about to read 5, iclass 33, count 0 2006.246.07:51:59.33#ibcon#read 5, iclass 33, count 0 2006.246.07:51:59.33#ibcon#about to read 6, iclass 33, count 0 2006.246.07:51:59.33#ibcon#read 6, iclass 33, count 0 2006.246.07:51:59.33#ibcon#end of sib2, iclass 33, count 0 2006.246.07:51:59.33#ibcon#*after write, iclass 33, count 0 2006.246.07:51:59.33#ibcon#*before return 0, iclass 33, count 0 2006.246.07:51:59.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:51:59.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:51:59.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:51:59.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:51:59.33$vc4f8/va=5,7 2006.246.07:51:59.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.07:51:59.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.07:51:59.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:51:59.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:51:59.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:51:59.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:51:59.39#ibcon#enter wrdev, iclass 35, count 2 2006.246.07:51:59.39#ibcon#first serial, iclass 35, count 2 2006.246.07:51:59.39#ibcon#enter sib2, iclass 35, count 2 2006.246.07:51:59.39#ibcon#flushed, iclass 35, count 2 2006.246.07:51:59.39#ibcon#about to write, iclass 35, count 2 2006.246.07:51:59.39#ibcon#wrote, iclass 35, count 2 2006.246.07:51:59.39#ibcon#about to read 3, iclass 35, count 2 2006.246.07:51:59.41#ibcon#read 3, iclass 35, count 2 2006.246.07:51:59.41#ibcon#about to read 4, iclass 35, count 2 2006.246.07:51:59.41#ibcon#read 4, iclass 35, count 2 2006.246.07:51:59.41#ibcon#about to read 5, iclass 35, count 2 2006.246.07:51:59.41#ibcon#read 5, iclass 35, count 2 2006.246.07:51:59.41#ibcon#about to read 6, iclass 35, count 2 2006.246.07:51:59.41#ibcon#read 6, iclass 35, count 2 2006.246.07:51:59.41#ibcon#end of sib2, iclass 35, count 2 2006.246.07:51:59.41#ibcon#*mode == 0, iclass 35, count 2 2006.246.07:51:59.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.07:51:59.41#ibcon#[25=AT05-07\r\n] 2006.246.07:51:59.41#ibcon#*before write, iclass 35, count 2 2006.246.07:51:59.41#ibcon#enter sib2, iclass 35, count 2 2006.246.07:51:59.41#ibcon#flushed, iclass 35, count 2 2006.246.07:51:59.41#ibcon#about to write, iclass 35, count 2 2006.246.07:51:59.41#ibcon#wrote, iclass 35, count 2 2006.246.07:51:59.41#ibcon#about to read 3, iclass 35, count 2 2006.246.07:51:59.44#ibcon#read 3, iclass 35, count 2 2006.246.07:51:59.44#ibcon#about to read 4, iclass 35, count 2 2006.246.07:51:59.44#ibcon#read 4, iclass 35, count 2 2006.246.07:51:59.44#ibcon#about to read 5, iclass 35, count 2 2006.246.07:51:59.44#ibcon#read 5, iclass 35, count 2 2006.246.07:51:59.44#ibcon#about to read 6, iclass 35, count 2 2006.246.07:51:59.44#ibcon#read 6, iclass 35, count 2 2006.246.07:51:59.44#ibcon#end of sib2, iclass 35, count 2 2006.246.07:51:59.44#ibcon#*after write, iclass 35, count 2 2006.246.07:51:59.44#ibcon#*before return 0, iclass 35, count 2 2006.246.07:51:59.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:51:59.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:51:59.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.07:51:59.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:51:59.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:51:59.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:51:59.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:51:59.56#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:51:59.56#ibcon#first serial, iclass 35, count 0 2006.246.07:51:59.56#ibcon#enter sib2, iclass 35, count 0 2006.246.07:51:59.56#ibcon#flushed, iclass 35, count 0 2006.246.07:51:59.56#ibcon#about to write, iclass 35, count 0 2006.246.07:51:59.56#ibcon#wrote, iclass 35, count 0 2006.246.07:51:59.56#ibcon#about to read 3, iclass 35, count 0 2006.246.07:51:59.58#ibcon#read 3, iclass 35, count 0 2006.246.07:51:59.58#ibcon#about to read 4, iclass 35, count 0 2006.246.07:51:59.58#ibcon#read 4, iclass 35, count 0 2006.246.07:51:59.58#ibcon#about to read 5, iclass 35, count 0 2006.246.07:51:59.58#ibcon#read 5, iclass 35, count 0 2006.246.07:51:59.58#ibcon#about to read 6, iclass 35, count 0 2006.246.07:51:59.58#ibcon#read 6, iclass 35, count 0 2006.246.07:51:59.58#ibcon#end of sib2, iclass 35, count 0 2006.246.07:51:59.58#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:51:59.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:51:59.58#ibcon#[25=USB\r\n] 2006.246.07:51:59.58#ibcon#*before write, iclass 35, count 0 2006.246.07:51:59.58#ibcon#enter sib2, iclass 35, count 0 2006.246.07:51:59.58#ibcon#flushed, iclass 35, count 0 2006.246.07:51:59.58#ibcon#about to write, iclass 35, count 0 2006.246.07:51:59.58#ibcon#wrote, iclass 35, count 0 2006.246.07:51:59.58#ibcon#about to read 3, iclass 35, count 0 2006.246.07:51:59.61#ibcon#read 3, iclass 35, count 0 2006.246.07:51:59.61#ibcon#about to read 4, iclass 35, count 0 2006.246.07:51:59.61#ibcon#read 4, iclass 35, count 0 2006.246.07:51:59.61#ibcon#about to read 5, iclass 35, count 0 2006.246.07:51:59.61#ibcon#read 5, iclass 35, count 0 2006.246.07:51:59.61#ibcon#about to read 6, iclass 35, count 0 2006.246.07:51:59.61#ibcon#read 6, iclass 35, count 0 2006.246.07:51:59.61#ibcon#end of sib2, iclass 35, count 0 2006.246.07:51:59.61#ibcon#*after write, iclass 35, count 0 2006.246.07:51:59.61#ibcon#*before return 0, iclass 35, count 0 2006.246.07:51:59.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:51:59.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:51:59.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:51:59.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:51:59.61$vc4f8/valo=6,772.99 2006.246.07:51:59.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.07:51:59.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.07:51:59.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:59.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:51:59.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:51:59.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:51:59.61#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:51:59.61#ibcon#first serial, iclass 37, count 0 2006.246.07:51:59.61#ibcon#enter sib2, iclass 37, count 0 2006.246.07:51:59.61#ibcon#flushed, iclass 37, count 0 2006.246.07:51:59.61#ibcon#about to write, iclass 37, count 0 2006.246.07:51:59.61#ibcon#wrote, iclass 37, count 0 2006.246.07:51:59.61#ibcon#about to read 3, iclass 37, count 0 2006.246.07:51:59.64#ibcon#read 3, iclass 37, count 0 2006.246.07:51:59.64#ibcon#about to read 4, iclass 37, count 0 2006.246.07:51:59.64#ibcon#read 4, iclass 37, count 0 2006.246.07:51:59.64#ibcon#about to read 5, iclass 37, count 0 2006.246.07:51:59.64#ibcon#read 5, iclass 37, count 0 2006.246.07:51:59.64#ibcon#about to read 6, iclass 37, count 0 2006.246.07:51:59.64#ibcon#read 6, iclass 37, count 0 2006.246.07:51:59.64#ibcon#end of sib2, iclass 37, count 0 2006.246.07:51:59.64#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:51:59.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:51:59.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:51:59.64#ibcon#*before write, iclass 37, count 0 2006.246.07:51:59.64#ibcon#enter sib2, iclass 37, count 0 2006.246.07:51:59.64#ibcon#flushed, iclass 37, count 0 2006.246.07:51:59.64#ibcon#about to write, iclass 37, count 0 2006.246.07:51:59.64#ibcon#wrote, iclass 37, count 0 2006.246.07:51:59.64#ibcon#about to read 3, iclass 37, count 0 2006.246.07:51:59.68#ibcon#read 3, iclass 37, count 0 2006.246.07:51:59.68#ibcon#about to read 4, iclass 37, count 0 2006.246.07:51:59.68#ibcon#read 4, iclass 37, count 0 2006.246.07:51:59.68#ibcon#about to read 5, iclass 37, count 0 2006.246.07:51:59.68#ibcon#read 5, iclass 37, count 0 2006.246.07:51:59.68#ibcon#about to read 6, iclass 37, count 0 2006.246.07:51:59.68#ibcon#read 6, iclass 37, count 0 2006.246.07:51:59.68#ibcon#end of sib2, iclass 37, count 0 2006.246.07:51:59.68#ibcon#*after write, iclass 37, count 0 2006.246.07:51:59.68#ibcon#*before return 0, iclass 37, count 0 2006.246.07:51:59.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:51:59.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:51:59.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:51:59.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:51:59.68$vc4f8/va=6,7 2006.246.07:51:59.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.07:51:59.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.07:51:59.68#ibcon#ireg 11 cls_cnt 2 2006.246.07:51:59.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:51:59.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:51:59.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:51:59.73#ibcon#enter wrdev, iclass 39, count 2 2006.246.07:51:59.73#ibcon#first serial, iclass 39, count 2 2006.246.07:51:59.73#ibcon#enter sib2, iclass 39, count 2 2006.246.07:51:59.73#ibcon#flushed, iclass 39, count 2 2006.246.07:51:59.73#ibcon#about to write, iclass 39, count 2 2006.246.07:51:59.73#ibcon#wrote, iclass 39, count 2 2006.246.07:51:59.73#ibcon#about to read 3, iclass 39, count 2 2006.246.07:51:59.75#ibcon#read 3, iclass 39, count 2 2006.246.07:51:59.75#ibcon#about to read 4, iclass 39, count 2 2006.246.07:51:59.75#ibcon#read 4, iclass 39, count 2 2006.246.07:51:59.75#ibcon#about to read 5, iclass 39, count 2 2006.246.07:51:59.75#ibcon#read 5, iclass 39, count 2 2006.246.07:51:59.75#ibcon#about to read 6, iclass 39, count 2 2006.246.07:51:59.75#ibcon#read 6, iclass 39, count 2 2006.246.07:51:59.75#ibcon#end of sib2, iclass 39, count 2 2006.246.07:51:59.75#ibcon#*mode == 0, iclass 39, count 2 2006.246.07:51:59.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.07:51:59.75#ibcon#[25=AT06-07\r\n] 2006.246.07:51:59.75#ibcon#*before write, iclass 39, count 2 2006.246.07:51:59.75#ibcon#enter sib2, iclass 39, count 2 2006.246.07:51:59.75#ibcon#flushed, iclass 39, count 2 2006.246.07:51:59.75#ibcon#about to write, iclass 39, count 2 2006.246.07:51:59.75#ibcon#wrote, iclass 39, count 2 2006.246.07:51:59.75#ibcon#about to read 3, iclass 39, count 2 2006.246.07:51:59.78#ibcon#read 3, iclass 39, count 2 2006.246.07:51:59.78#ibcon#about to read 4, iclass 39, count 2 2006.246.07:51:59.78#ibcon#read 4, iclass 39, count 2 2006.246.07:51:59.78#ibcon#about to read 5, iclass 39, count 2 2006.246.07:51:59.78#ibcon#read 5, iclass 39, count 2 2006.246.07:51:59.78#ibcon#about to read 6, iclass 39, count 2 2006.246.07:51:59.78#ibcon#read 6, iclass 39, count 2 2006.246.07:51:59.78#ibcon#end of sib2, iclass 39, count 2 2006.246.07:51:59.78#ibcon#*after write, iclass 39, count 2 2006.246.07:51:59.78#ibcon#*before return 0, iclass 39, count 2 2006.246.07:51:59.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:51:59.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.07:51:59.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.07:51:59.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:51:59.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:51:59.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:51:59.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:51:59.90#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:51:59.90#ibcon#first serial, iclass 39, count 0 2006.246.07:51:59.90#ibcon#enter sib2, iclass 39, count 0 2006.246.07:51:59.90#ibcon#flushed, iclass 39, count 0 2006.246.07:51:59.90#ibcon#about to write, iclass 39, count 0 2006.246.07:51:59.90#ibcon#wrote, iclass 39, count 0 2006.246.07:51:59.90#ibcon#about to read 3, iclass 39, count 0 2006.246.07:51:59.92#ibcon#read 3, iclass 39, count 0 2006.246.07:51:59.92#ibcon#about to read 4, iclass 39, count 0 2006.246.07:51:59.92#ibcon#read 4, iclass 39, count 0 2006.246.07:51:59.92#ibcon#about to read 5, iclass 39, count 0 2006.246.07:51:59.92#ibcon#read 5, iclass 39, count 0 2006.246.07:51:59.92#ibcon#about to read 6, iclass 39, count 0 2006.246.07:51:59.92#ibcon#read 6, iclass 39, count 0 2006.246.07:51:59.92#ibcon#end of sib2, iclass 39, count 0 2006.246.07:51:59.92#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:51:59.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:51:59.92#ibcon#[25=USB\r\n] 2006.246.07:51:59.92#ibcon#*before write, iclass 39, count 0 2006.246.07:51:59.92#ibcon#enter sib2, iclass 39, count 0 2006.246.07:51:59.92#ibcon#flushed, iclass 39, count 0 2006.246.07:51:59.92#ibcon#about to write, iclass 39, count 0 2006.246.07:51:59.92#ibcon#wrote, iclass 39, count 0 2006.246.07:51:59.92#ibcon#about to read 3, iclass 39, count 0 2006.246.07:51:59.95#ibcon#read 3, iclass 39, count 0 2006.246.07:51:59.95#ibcon#about to read 4, iclass 39, count 0 2006.246.07:51:59.95#ibcon#read 4, iclass 39, count 0 2006.246.07:51:59.95#ibcon#about to read 5, iclass 39, count 0 2006.246.07:51:59.95#ibcon#read 5, iclass 39, count 0 2006.246.07:51:59.95#ibcon#about to read 6, iclass 39, count 0 2006.246.07:51:59.95#ibcon#read 6, iclass 39, count 0 2006.246.07:51:59.95#ibcon#end of sib2, iclass 39, count 0 2006.246.07:51:59.95#ibcon#*after write, iclass 39, count 0 2006.246.07:51:59.95#ibcon#*before return 0, iclass 39, count 0 2006.246.07:51:59.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:51:59.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.07:51:59.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:51:59.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:51:59.95$vc4f8/valo=7,832.99 2006.246.07:51:59.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.07:51:59.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.07:51:59.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:51:59.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:51:59.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:51:59.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:51:59.95#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:51:59.95#ibcon#first serial, iclass 3, count 0 2006.246.07:51:59.95#ibcon#enter sib2, iclass 3, count 0 2006.246.07:51:59.95#ibcon#flushed, iclass 3, count 0 2006.246.07:51:59.95#ibcon#about to write, iclass 3, count 0 2006.246.07:51:59.95#ibcon#wrote, iclass 3, count 0 2006.246.07:51:59.95#ibcon#about to read 3, iclass 3, count 0 2006.246.07:51:59.97#ibcon#read 3, iclass 3, count 0 2006.246.07:51:59.97#ibcon#about to read 4, iclass 3, count 0 2006.246.07:51:59.97#ibcon#read 4, iclass 3, count 0 2006.246.07:51:59.97#ibcon#about to read 5, iclass 3, count 0 2006.246.07:51:59.97#ibcon#read 5, iclass 3, count 0 2006.246.07:51:59.97#ibcon#about to read 6, iclass 3, count 0 2006.246.07:51:59.97#ibcon#read 6, iclass 3, count 0 2006.246.07:51:59.97#ibcon#end of sib2, iclass 3, count 0 2006.246.07:51:59.97#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:51:59.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:51:59.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:51:59.97#ibcon#*before write, iclass 3, count 0 2006.246.07:51:59.97#ibcon#enter sib2, iclass 3, count 0 2006.246.07:51:59.97#ibcon#flushed, iclass 3, count 0 2006.246.07:51:59.97#ibcon#about to write, iclass 3, count 0 2006.246.07:51:59.97#ibcon#wrote, iclass 3, count 0 2006.246.07:51:59.97#ibcon#about to read 3, iclass 3, count 0 2006.246.07:52:00.01#ibcon#read 3, iclass 3, count 0 2006.246.07:52:00.01#ibcon#about to read 4, iclass 3, count 0 2006.246.07:52:00.01#ibcon#read 4, iclass 3, count 0 2006.246.07:52:00.01#ibcon#about to read 5, iclass 3, count 0 2006.246.07:52:00.01#ibcon#read 5, iclass 3, count 0 2006.246.07:52:00.01#ibcon#about to read 6, iclass 3, count 0 2006.246.07:52:00.01#ibcon#read 6, iclass 3, count 0 2006.246.07:52:00.01#ibcon#end of sib2, iclass 3, count 0 2006.246.07:52:00.01#ibcon#*after write, iclass 3, count 0 2006.246.07:52:00.01#ibcon#*before return 0, iclass 3, count 0 2006.246.07:52:00.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:52:00.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.07:52:00.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:52:00.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:52:00.01$vc4f8/va=7,7 2006.246.07:52:00.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.07:52:00.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.07:52:00.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:00.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:52:00.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:52:00.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:52:00.07#ibcon#enter wrdev, iclass 5, count 2 2006.246.07:52:00.07#ibcon#first serial, iclass 5, count 2 2006.246.07:52:00.07#ibcon#enter sib2, iclass 5, count 2 2006.246.07:52:00.07#ibcon#flushed, iclass 5, count 2 2006.246.07:52:00.07#ibcon#about to write, iclass 5, count 2 2006.246.07:52:00.07#ibcon#wrote, iclass 5, count 2 2006.246.07:52:00.07#ibcon#about to read 3, iclass 5, count 2 2006.246.07:52:00.09#ibcon#read 3, iclass 5, count 2 2006.246.07:52:00.09#ibcon#about to read 4, iclass 5, count 2 2006.246.07:52:00.09#ibcon#read 4, iclass 5, count 2 2006.246.07:52:00.09#ibcon#about to read 5, iclass 5, count 2 2006.246.07:52:00.09#ibcon#read 5, iclass 5, count 2 2006.246.07:52:00.09#ibcon#about to read 6, iclass 5, count 2 2006.246.07:52:00.09#ibcon#read 6, iclass 5, count 2 2006.246.07:52:00.09#ibcon#end of sib2, iclass 5, count 2 2006.246.07:52:00.09#ibcon#*mode == 0, iclass 5, count 2 2006.246.07:52:00.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.07:52:00.09#ibcon#[25=AT07-07\r\n] 2006.246.07:52:00.09#ibcon#*before write, iclass 5, count 2 2006.246.07:52:00.09#ibcon#enter sib2, iclass 5, count 2 2006.246.07:52:00.09#ibcon#flushed, iclass 5, count 2 2006.246.07:52:00.09#ibcon#about to write, iclass 5, count 2 2006.246.07:52:00.09#ibcon#wrote, iclass 5, count 2 2006.246.07:52:00.09#ibcon#about to read 3, iclass 5, count 2 2006.246.07:52:00.12#ibcon#read 3, iclass 5, count 2 2006.246.07:52:00.12#ibcon#about to read 4, iclass 5, count 2 2006.246.07:52:00.12#ibcon#read 4, iclass 5, count 2 2006.246.07:52:00.12#ibcon#about to read 5, iclass 5, count 2 2006.246.07:52:00.12#ibcon#read 5, iclass 5, count 2 2006.246.07:52:00.12#ibcon#about to read 6, iclass 5, count 2 2006.246.07:52:00.12#ibcon#read 6, iclass 5, count 2 2006.246.07:52:00.12#ibcon#end of sib2, iclass 5, count 2 2006.246.07:52:00.12#ibcon#*after write, iclass 5, count 2 2006.246.07:52:00.12#ibcon#*before return 0, iclass 5, count 2 2006.246.07:52:00.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:52:00.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.07:52:00.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.07:52:00.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:00.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:52:00.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:52:00.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:52:00.24#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:52:00.24#ibcon#first serial, iclass 5, count 0 2006.246.07:52:00.24#ibcon#enter sib2, iclass 5, count 0 2006.246.07:52:00.24#ibcon#flushed, iclass 5, count 0 2006.246.07:52:00.24#ibcon#about to write, iclass 5, count 0 2006.246.07:52:00.24#ibcon#wrote, iclass 5, count 0 2006.246.07:52:00.24#ibcon#about to read 3, iclass 5, count 0 2006.246.07:52:00.26#ibcon#read 3, iclass 5, count 0 2006.246.07:52:00.26#ibcon#about to read 4, iclass 5, count 0 2006.246.07:52:00.26#ibcon#read 4, iclass 5, count 0 2006.246.07:52:00.26#ibcon#about to read 5, iclass 5, count 0 2006.246.07:52:00.26#ibcon#read 5, iclass 5, count 0 2006.246.07:52:00.26#ibcon#about to read 6, iclass 5, count 0 2006.246.07:52:00.26#ibcon#read 6, iclass 5, count 0 2006.246.07:52:00.26#ibcon#end of sib2, iclass 5, count 0 2006.246.07:52:00.26#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:52:00.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:52:00.26#ibcon#[25=USB\r\n] 2006.246.07:52:00.26#ibcon#*before write, iclass 5, count 0 2006.246.07:52:00.26#ibcon#enter sib2, iclass 5, count 0 2006.246.07:52:00.26#ibcon#flushed, iclass 5, count 0 2006.246.07:52:00.26#ibcon#about to write, iclass 5, count 0 2006.246.07:52:00.26#ibcon#wrote, iclass 5, count 0 2006.246.07:52:00.26#ibcon#about to read 3, iclass 5, count 0 2006.246.07:52:00.29#ibcon#read 3, iclass 5, count 0 2006.246.07:52:00.29#ibcon#about to read 4, iclass 5, count 0 2006.246.07:52:00.29#ibcon#read 4, iclass 5, count 0 2006.246.07:52:00.29#ibcon#about to read 5, iclass 5, count 0 2006.246.07:52:00.29#ibcon#read 5, iclass 5, count 0 2006.246.07:52:00.29#ibcon#about to read 6, iclass 5, count 0 2006.246.07:52:00.29#ibcon#read 6, iclass 5, count 0 2006.246.07:52:00.29#ibcon#end of sib2, iclass 5, count 0 2006.246.07:52:00.29#ibcon#*after write, iclass 5, count 0 2006.246.07:52:00.29#ibcon#*before return 0, iclass 5, count 0 2006.246.07:52:00.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:52:00.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.07:52:00.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:52:00.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:52:00.29$vc4f8/valo=8,852.99 2006.246.07:52:00.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.07:52:00.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.07:52:00.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:00.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:52:00.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:52:00.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:52:00.29#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:52:00.29#ibcon#first serial, iclass 7, count 0 2006.246.07:52:00.29#ibcon#enter sib2, iclass 7, count 0 2006.246.07:52:00.29#ibcon#flushed, iclass 7, count 0 2006.246.07:52:00.29#ibcon#about to write, iclass 7, count 0 2006.246.07:52:00.29#ibcon#wrote, iclass 7, count 0 2006.246.07:52:00.29#ibcon#about to read 3, iclass 7, count 0 2006.246.07:52:00.32#ibcon#read 3, iclass 7, count 0 2006.246.07:52:00.32#ibcon#about to read 4, iclass 7, count 0 2006.246.07:52:00.32#ibcon#read 4, iclass 7, count 0 2006.246.07:52:00.32#ibcon#about to read 5, iclass 7, count 0 2006.246.07:52:00.32#ibcon#read 5, iclass 7, count 0 2006.246.07:52:00.32#ibcon#about to read 6, iclass 7, count 0 2006.246.07:52:00.32#ibcon#read 6, iclass 7, count 0 2006.246.07:52:00.32#ibcon#end of sib2, iclass 7, count 0 2006.246.07:52:00.32#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:52:00.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:52:00.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:52:00.32#ibcon#*before write, iclass 7, count 0 2006.246.07:52:00.32#ibcon#enter sib2, iclass 7, count 0 2006.246.07:52:00.32#ibcon#flushed, iclass 7, count 0 2006.246.07:52:00.32#ibcon#about to write, iclass 7, count 0 2006.246.07:52:00.32#ibcon#wrote, iclass 7, count 0 2006.246.07:52:00.32#ibcon#about to read 3, iclass 7, count 0 2006.246.07:52:00.36#ibcon#read 3, iclass 7, count 0 2006.246.07:52:00.36#ibcon#about to read 4, iclass 7, count 0 2006.246.07:52:00.36#ibcon#read 4, iclass 7, count 0 2006.246.07:52:00.36#ibcon#about to read 5, iclass 7, count 0 2006.246.07:52:00.36#ibcon#read 5, iclass 7, count 0 2006.246.07:52:00.36#ibcon#about to read 6, iclass 7, count 0 2006.246.07:52:00.36#ibcon#read 6, iclass 7, count 0 2006.246.07:52:00.36#ibcon#end of sib2, iclass 7, count 0 2006.246.07:52:00.36#ibcon#*after write, iclass 7, count 0 2006.246.07:52:00.36#ibcon#*before return 0, iclass 7, count 0 2006.246.07:52:00.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:52:00.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.07:52:00.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:52:00.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:52:00.36$vc4f8/va=8,8 2006.246.07:52:00.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.07:52:00.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.07:52:00.36#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:00.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:52:00.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:52:00.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:52:00.41#ibcon#enter wrdev, iclass 11, count 2 2006.246.07:52:00.41#ibcon#first serial, iclass 11, count 2 2006.246.07:52:00.41#ibcon#enter sib2, iclass 11, count 2 2006.246.07:52:00.41#ibcon#flushed, iclass 11, count 2 2006.246.07:52:00.41#ibcon#about to write, iclass 11, count 2 2006.246.07:52:00.41#ibcon#wrote, iclass 11, count 2 2006.246.07:52:00.41#ibcon#about to read 3, iclass 11, count 2 2006.246.07:52:00.43#ibcon#read 3, iclass 11, count 2 2006.246.07:52:00.43#ibcon#about to read 4, iclass 11, count 2 2006.246.07:52:00.43#ibcon#read 4, iclass 11, count 2 2006.246.07:52:00.43#ibcon#about to read 5, iclass 11, count 2 2006.246.07:52:00.43#ibcon#read 5, iclass 11, count 2 2006.246.07:52:00.43#ibcon#about to read 6, iclass 11, count 2 2006.246.07:52:00.43#ibcon#read 6, iclass 11, count 2 2006.246.07:52:00.43#ibcon#end of sib2, iclass 11, count 2 2006.246.07:52:00.43#ibcon#*mode == 0, iclass 11, count 2 2006.246.07:52:00.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.07:52:00.43#ibcon#[25=AT08-08\r\n] 2006.246.07:52:00.43#ibcon#*before write, iclass 11, count 2 2006.246.07:52:00.43#ibcon#enter sib2, iclass 11, count 2 2006.246.07:52:00.43#ibcon#flushed, iclass 11, count 2 2006.246.07:52:00.43#ibcon#about to write, iclass 11, count 2 2006.246.07:52:00.43#ibcon#wrote, iclass 11, count 2 2006.246.07:52:00.43#ibcon#about to read 3, iclass 11, count 2 2006.246.07:52:00.46#ibcon#read 3, iclass 11, count 2 2006.246.07:52:00.46#ibcon#about to read 4, iclass 11, count 2 2006.246.07:52:00.46#ibcon#read 4, iclass 11, count 2 2006.246.07:52:00.46#ibcon#about to read 5, iclass 11, count 2 2006.246.07:52:00.46#ibcon#read 5, iclass 11, count 2 2006.246.07:52:00.46#ibcon#about to read 6, iclass 11, count 2 2006.246.07:52:00.46#ibcon#read 6, iclass 11, count 2 2006.246.07:52:00.46#ibcon#end of sib2, iclass 11, count 2 2006.246.07:52:00.46#ibcon#*after write, iclass 11, count 2 2006.246.07:52:00.46#ibcon#*before return 0, iclass 11, count 2 2006.246.07:52:00.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:52:00.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.07:52:00.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.07:52:00.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:00.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:52:00.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:52:00.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:52:00.58#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:52:00.58#ibcon#first serial, iclass 11, count 0 2006.246.07:52:00.58#ibcon#enter sib2, iclass 11, count 0 2006.246.07:52:00.58#ibcon#flushed, iclass 11, count 0 2006.246.07:52:00.58#ibcon#about to write, iclass 11, count 0 2006.246.07:52:00.58#ibcon#wrote, iclass 11, count 0 2006.246.07:52:00.58#ibcon#about to read 3, iclass 11, count 0 2006.246.07:52:00.60#ibcon#read 3, iclass 11, count 0 2006.246.07:52:00.60#ibcon#about to read 4, iclass 11, count 0 2006.246.07:52:00.60#ibcon#read 4, iclass 11, count 0 2006.246.07:52:00.60#ibcon#about to read 5, iclass 11, count 0 2006.246.07:52:00.60#ibcon#read 5, iclass 11, count 0 2006.246.07:52:00.60#ibcon#about to read 6, iclass 11, count 0 2006.246.07:52:00.60#ibcon#read 6, iclass 11, count 0 2006.246.07:52:00.60#ibcon#end of sib2, iclass 11, count 0 2006.246.07:52:00.60#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:52:00.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:52:00.60#ibcon#[25=USB\r\n] 2006.246.07:52:00.60#ibcon#*before write, iclass 11, count 0 2006.246.07:52:00.60#ibcon#enter sib2, iclass 11, count 0 2006.246.07:52:00.60#ibcon#flushed, iclass 11, count 0 2006.246.07:52:00.60#ibcon#about to write, iclass 11, count 0 2006.246.07:52:00.60#ibcon#wrote, iclass 11, count 0 2006.246.07:52:00.60#ibcon#about to read 3, iclass 11, count 0 2006.246.07:52:00.63#ibcon#read 3, iclass 11, count 0 2006.246.07:52:00.63#ibcon#about to read 4, iclass 11, count 0 2006.246.07:52:00.63#ibcon#read 4, iclass 11, count 0 2006.246.07:52:00.63#ibcon#about to read 5, iclass 11, count 0 2006.246.07:52:00.63#ibcon#read 5, iclass 11, count 0 2006.246.07:52:00.63#ibcon#about to read 6, iclass 11, count 0 2006.246.07:52:00.63#ibcon#read 6, iclass 11, count 0 2006.246.07:52:00.63#ibcon#end of sib2, iclass 11, count 0 2006.246.07:52:00.63#ibcon#*after write, iclass 11, count 0 2006.246.07:52:00.63#ibcon#*before return 0, iclass 11, count 0 2006.246.07:52:00.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:52:00.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.07:52:00.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:52:00.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:52:00.63$vc4f8/vblo=1,632.99 2006.246.07:52:00.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.07:52:00.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.07:52:00.63#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:00.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:52:00.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:52:00.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:52:00.63#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:52:00.63#ibcon#first serial, iclass 13, count 0 2006.246.07:52:00.63#ibcon#enter sib2, iclass 13, count 0 2006.246.07:52:00.63#ibcon#flushed, iclass 13, count 0 2006.246.07:52:00.63#ibcon#about to write, iclass 13, count 0 2006.246.07:52:00.63#ibcon#wrote, iclass 13, count 0 2006.246.07:52:00.63#ibcon#about to read 3, iclass 13, count 0 2006.246.07:52:00.65#ibcon#read 3, iclass 13, count 0 2006.246.07:52:00.65#ibcon#about to read 4, iclass 13, count 0 2006.246.07:52:00.65#ibcon#read 4, iclass 13, count 0 2006.246.07:52:00.65#ibcon#about to read 5, iclass 13, count 0 2006.246.07:52:00.65#ibcon#read 5, iclass 13, count 0 2006.246.07:52:00.65#ibcon#about to read 6, iclass 13, count 0 2006.246.07:52:00.65#ibcon#read 6, iclass 13, count 0 2006.246.07:52:00.65#ibcon#end of sib2, iclass 13, count 0 2006.246.07:52:00.65#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:52:00.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:52:00.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:52:00.65#ibcon#*before write, iclass 13, count 0 2006.246.07:52:00.65#ibcon#enter sib2, iclass 13, count 0 2006.246.07:52:00.65#ibcon#flushed, iclass 13, count 0 2006.246.07:52:00.65#ibcon#about to write, iclass 13, count 0 2006.246.07:52:00.65#ibcon#wrote, iclass 13, count 0 2006.246.07:52:00.65#ibcon#about to read 3, iclass 13, count 0 2006.246.07:52:00.69#ibcon#read 3, iclass 13, count 0 2006.246.07:52:00.69#ibcon#about to read 4, iclass 13, count 0 2006.246.07:52:00.69#ibcon#read 4, iclass 13, count 0 2006.246.07:52:00.69#ibcon#about to read 5, iclass 13, count 0 2006.246.07:52:00.69#ibcon#read 5, iclass 13, count 0 2006.246.07:52:00.69#ibcon#about to read 6, iclass 13, count 0 2006.246.07:52:00.69#ibcon#read 6, iclass 13, count 0 2006.246.07:52:00.69#ibcon#end of sib2, iclass 13, count 0 2006.246.07:52:00.69#ibcon#*after write, iclass 13, count 0 2006.246.07:52:00.69#ibcon#*before return 0, iclass 13, count 0 2006.246.07:52:00.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:52:00.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.07:52:00.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:52:00.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:52:00.69$vc4f8/vb=1,4 2006.246.07:52:00.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.07:52:00.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.07:52:00.69#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:00.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:52:00.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:52:00.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:52:00.69#ibcon#enter wrdev, iclass 15, count 2 2006.246.07:52:00.69#ibcon#first serial, iclass 15, count 2 2006.246.07:52:00.69#ibcon#enter sib2, iclass 15, count 2 2006.246.07:52:00.69#ibcon#flushed, iclass 15, count 2 2006.246.07:52:00.69#ibcon#about to write, iclass 15, count 2 2006.246.07:52:00.69#ibcon#wrote, iclass 15, count 2 2006.246.07:52:00.69#ibcon#about to read 3, iclass 15, count 2 2006.246.07:52:00.71#ibcon#read 3, iclass 15, count 2 2006.246.07:52:00.71#ibcon#about to read 4, iclass 15, count 2 2006.246.07:52:00.71#ibcon#read 4, iclass 15, count 2 2006.246.07:52:00.71#ibcon#about to read 5, iclass 15, count 2 2006.246.07:52:00.71#ibcon#read 5, iclass 15, count 2 2006.246.07:52:00.71#ibcon#about to read 6, iclass 15, count 2 2006.246.07:52:00.71#ibcon#read 6, iclass 15, count 2 2006.246.07:52:00.71#ibcon#end of sib2, iclass 15, count 2 2006.246.07:52:00.71#ibcon#*mode == 0, iclass 15, count 2 2006.246.07:52:00.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.07:52:00.71#ibcon#[27=AT01-04\r\n] 2006.246.07:52:00.71#ibcon#*before write, iclass 15, count 2 2006.246.07:52:00.71#ibcon#enter sib2, iclass 15, count 2 2006.246.07:52:00.71#ibcon#flushed, iclass 15, count 2 2006.246.07:52:00.71#ibcon#about to write, iclass 15, count 2 2006.246.07:52:00.71#ibcon#wrote, iclass 15, count 2 2006.246.07:52:00.71#ibcon#about to read 3, iclass 15, count 2 2006.246.07:52:00.74#ibcon#read 3, iclass 15, count 2 2006.246.07:52:00.74#ibcon#about to read 4, iclass 15, count 2 2006.246.07:52:00.74#ibcon#read 4, iclass 15, count 2 2006.246.07:52:00.74#ibcon#about to read 5, iclass 15, count 2 2006.246.07:52:00.74#ibcon#read 5, iclass 15, count 2 2006.246.07:52:00.74#ibcon#about to read 6, iclass 15, count 2 2006.246.07:52:00.74#ibcon#read 6, iclass 15, count 2 2006.246.07:52:00.74#ibcon#end of sib2, iclass 15, count 2 2006.246.07:52:00.74#ibcon#*after write, iclass 15, count 2 2006.246.07:52:00.74#ibcon#*before return 0, iclass 15, count 2 2006.246.07:52:00.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:52:00.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.07:52:00.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.07:52:00.74#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:00.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:52:00.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:52:00.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:52:00.86#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:52:00.86#ibcon#first serial, iclass 15, count 0 2006.246.07:52:00.86#ibcon#enter sib2, iclass 15, count 0 2006.246.07:52:00.86#ibcon#flushed, iclass 15, count 0 2006.246.07:52:00.86#ibcon#about to write, iclass 15, count 0 2006.246.07:52:00.86#ibcon#wrote, iclass 15, count 0 2006.246.07:52:00.86#ibcon#about to read 3, iclass 15, count 0 2006.246.07:52:00.88#ibcon#read 3, iclass 15, count 0 2006.246.07:52:00.88#ibcon#about to read 4, iclass 15, count 0 2006.246.07:52:00.88#ibcon#read 4, iclass 15, count 0 2006.246.07:52:00.88#ibcon#about to read 5, iclass 15, count 0 2006.246.07:52:00.88#ibcon#read 5, iclass 15, count 0 2006.246.07:52:00.88#ibcon#about to read 6, iclass 15, count 0 2006.246.07:52:00.88#ibcon#read 6, iclass 15, count 0 2006.246.07:52:00.88#ibcon#end of sib2, iclass 15, count 0 2006.246.07:52:00.88#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:52:00.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:52:00.88#ibcon#[27=USB\r\n] 2006.246.07:52:00.88#ibcon#*before write, iclass 15, count 0 2006.246.07:52:00.88#ibcon#enter sib2, iclass 15, count 0 2006.246.07:52:00.88#ibcon#flushed, iclass 15, count 0 2006.246.07:52:00.88#ibcon#about to write, iclass 15, count 0 2006.246.07:52:00.88#ibcon#wrote, iclass 15, count 0 2006.246.07:52:00.88#ibcon#about to read 3, iclass 15, count 0 2006.246.07:52:00.91#ibcon#read 3, iclass 15, count 0 2006.246.07:52:00.91#ibcon#about to read 4, iclass 15, count 0 2006.246.07:52:00.91#ibcon#read 4, iclass 15, count 0 2006.246.07:52:00.91#ibcon#about to read 5, iclass 15, count 0 2006.246.07:52:00.91#ibcon#read 5, iclass 15, count 0 2006.246.07:52:00.91#ibcon#about to read 6, iclass 15, count 0 2006.246.07:52:00.91#ibcon#read 6, iclass 15, count 0 2006.246.07:52:00.91#ibcon#end of sib2, iclass 15, count 0 2006.246.07:52:00.91#ibcon#*after write, iclass 15, count 0 2006.246.07:52:00.91#ibcon#*before return 0, iclass 15, count 0 2006.246.07:52:00.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:52:00.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.07:52:00.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:52:00.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:52:00.91$vc4f8/vblo=2,640.99 2006.246.07:52:00.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:52:00.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:52:00.91#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:00.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:52:00.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:52:00.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:52:00.91#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:52:00.91#ibcon#first serial, iclass 17, count 0 2006.246.07:52:00.91#ibcon#enter sib2, iclass 17, count 0 2006.246.07:52:00.91#ibcon#flushed, iclass 17, count 0 2006.246.07:52:00.91#ibcon#about to write, iclass 17, count 0 2006.246.07:52:00.91#ibcon#wrote, iclass 17, count 0 2006.246.07:52:00.91#ibcon#about to read 3, iclass 17, count 0 2006.246.07:52:00.93#ibcon#read 3, iclass 17, count 0 2006.246.07:52:00.93#ibcon#about to read 4, iclass 17, count 0 2006.246.07:52:00.93#ibcon#read 4, iclass 17, count 0 2006.246.07:52:00.93#ibcon#about to read 5, iclass 17, count 0 2006.246.07:52:00.93#ibcon#read 5, iclass 17, count 0 2006.246.07:52:00.93#ibcon#about to read 6, iclass 17, count 0 2006.246.07:52:00.93#ibcon#read 6, iclass 17, count 0 2006.246.07:52:00.93#ibcon#end of sib2, iclass 17, count 0 2006.246.07:52:00.93#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:52:00.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:52:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:52:00.93#ibcon#*before write, iclass 17, count 0 2006.246.07:52:00.93#ibcon#enter sib2, iclass 17, count 0 2006.246.07:52:00.93#ibcon#flushed, iclass 17, count 0 2006.246.07:52:00.93#ibcon#about to write, iclass 17, count 0 2006.246.07:52:00.93#ibcon#wrote, iclass 17, count 0 2006.246.07:52:00.93#ibcon#about to read 3, iclass 17, count 0 2006.246.07:52:00.97#ibcon#read 3, iclass 17, count 0 2006.246.07:52:00.97#ibcon#about to read 4, iclass 17, count 0 2006.246.07:52:00.97#ibcon#read 4, iclass 17, count 0 2006.246.07:52:00.97#ibcon#about to read 5, iclass 17, count 0 2006.246.07:52:00.97#ibcon#read 5, iclass 17, count 0 2006.246.07:52:00.97#ibcon#about to read 6, iclass 17, count 0 2006.246.07:52:00.97#ibcon#read 6, iclass 17, count 0 2006.246.07:52:00.97#ibcon#end of sib2, iclass 17, count 0 2006.246.07:52:00.97#ibcon#*after write, iclass 17, count 0 2006.246.07:52:00.97#ibcon#*before return 0, iclass 17, count 0 2006.246.07:52:00.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:52:00.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:52:00.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:52:00.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:52:00.97$vc4f8/vb=2,4 2006.246.07:52:00.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.07:52:00.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.07:52:00.97#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:00.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:52:01.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:52:01.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:52:01.03#ibcon#enter wrdev, iclass 19, count 2 2006.246.07:52:01.03#ibcon#first serial, iclass 19, count 2 2006.246.07:52:01.03#ibcon#enter sib2, iclass 19, count 2 2006.246.07:52:01.03#ibcon#flushed, iclass 19, count 2 2006.246.07:52:01.03#ibcon#about to write, iclass 19, count 2 2006.246.07:52:01.03#ibcon#wrote, iclass 19, count 2 2006.246.07:52:01.03#ibcon#about to read 3, iclass 19, count 2 2006.246.07:52:01.05#ibcon#read 3, iclass 19, count 2 2006.246.07:52:01.05#ibcon#about to read 4, iclass 19, count 2 2006.246.07:52:01.05#ibcon#read 4, iclass 19, count 2 2006.246.07:52:01.05#ibcon#about to read 5, iclass 19, count 2 2006.246.07:52:01.05#ibcon#read 5, iclass 19, count 2 2006.246.07:52:01.05#ibcon#about to read 6, iclass 19, count 2 2006.246.07:52:01.05#ibcon#read 6, iclass 19, count 2 2006.246.07:52:01.05#ibcon#end of sib2, iclass 19, count 2 2006.246.07:52:01.05#ibcon#*mode == 0, iclass 19, count 2 2006.246.07:52:01.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.07:52:01.05#ibcon#[27=AT02-04\r\n] 2006.246.07:52:01.05#ibcon#*before write, iclass 19, count 2 2006.246.07:52:01.05#ibcon#enter sib2, iclass 19, count 2 2006.246.07:52:01.05#ibcon#flushed, iclass 19, count 2 2006.246.07:52:01.05#ibcon#about to write, iclass 19, count 2 2006.246.07:52:01.05#ibcon#wrote, iclass 19, count 2 2006.246.07:52:01.05#ibcon#about to read 3, iclass 19, count 2 2006.246.07:52:01.08#ibcon#read 3, iclass 19, count 2 2006.246.07:52:01.08#ibcon#about to read 4, iclass 19, count 2 2006.246.07:52:01.08#ibcon#read 4, iclass 19, count 2 2006.246.07:52:01.08#ibcon#about to read 5, iclass 19, count 2 2006.246.07:52:01.08#ibcon#read 5, iclass 19, count 2 2006.246.07:52:01.08#ibcon#about to read 6, iclass 19, count 2 2006.246.07:52:01.08#ibcon#read 6, iclass 19, count 2 2006.246.07:52:01.08#ibcon#end of sib2, iclass 19, count 2 2006.246.07:52:01.08#ibcon#*after write, iclass 19, count 2 2006.246.07:52:01.08#ibcon#*before return 0, iclass 19, count 2 2006.246.07:52:01.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:52:01.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.07:52:01.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.07:52:01.08#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:01.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:52:01.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:52:01.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:52:01.20#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:52:01.20#ibcon#first serial, iclass 19, count 0 2006.246.07:52:01.20#ibcon#enter sib2, iclass 19, count 0 2006.246.07:52:01.20#ibcon#flushed, iclass 19, count 0 2006.246.07:52:01.20#ibcon#about to write, iclass 19, count 0 2006.246.07:52:01.20#ibcon#wrote, iclass 19, count 0 2006.246.07:52:01.20#ibcon#about to read 3, iclass 19, count 0 2006.246.07:52:01.24#ibcon#read 3, iclass 19, count 0 2006.246.07:52:01.24#ibcon#about to read 4, iclass 19, count 0 2006.246.07:52:01.24#ibcon#read 4, iclass 19, count 0 2006.246.07:52:01.24#ibcon#about to read 5, iclass 19, count 0 2006.246.07:52:01.24#ibcon#read 5, iclass 19, count 0 2006.246.07:52:01.24#ibcon#about to read 6, iclass 19, count 0 2006.246.07:52:01.24#ibcon#read 6, iclass 19, count 0 2006.246.07:52:01.24#ibcon#end of sib2, iclass 19, count 0 2006.246.07:52:01.24#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:52:01.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:52:01.24#ibcon#[27=USB\r\n] 2006.246.07:52:01.24#ibcon#*before write, iclass 19, count 0 2006.246.07:52:01.24#ibcon#enter sib2, iclass 19, count 0 2006.246.07:52:01.24#ibcon#flushed, iclass 19, count 0 2006.246.07:52:01.24#ibcon#about to write, iclass 19, count 0 2006.246.07:52:01.24#ibcon#wrote, iclass 19, count 0 2006.246.07:52:01.24#ibcon#about to read 3, iclass 19, count 0 2006.246.07:52:01.26#ibcon#read 3, iclass 19, count 0 2006.246.07:52:01.26#ibcon#about to read 4, iclass 19, count 0 2006.246.07:52:01.26#ibcon#read 4, iclass 19, count 0 2006.246.07:52:01.26#ibcon#about to read 5, iclass 19, count 0 2006.246.07:52:01.26#ibcon#read 5, iclass 19, count 0 2006.246.07:52:01.26#ibcon#about to read 6, iclass 19, count 0 2006.246.07:52:01.26#ibcon#read 6, iclass 19, count 0 2006.246.07:52:01.26#ibcon#end of sib2, iclass 19, count 0 2006.246.07:52:01.26#ibcon#*after write, iclass 19, count 0 2006.246.07:52:01.26#ibcon#*before return 0, iclass 19, count 0 2006.246.07:52:01.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:52:01.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.07:52:01.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:52:01.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:52:01.26$vc4f8/vblo=3,656.99 2006.246.07:52:01.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.07:52:01.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.07:52:01.26#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:01.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:52:01.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:52:01.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:52:01.26#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:52:01.26#ibcon#first serial, iclass 21, count 0 2006.246.07:52:01.26#ibcon#enter sib2, iclass 21, count 0 2006.246.07:52:01.26#ibcon#flushed, iclass 21, count 0 2006.246.07:52:01.26#ibcon#about to write, iclass 21, count 0 2006.246.07:52:01.26#ibcon#wrote, iclass 21, count 0 2006.246.07:52:01.26#ibcon#about to read 3, iclass 21, count 0 2006.246.07:52:01.28#ibcon#read 3, iclass 21, count 0 2006.246.07:52:01.28#ibcon#about to read 4, iclass 21, count 0 2006.246.07:52:01.28#ibcon#read 4, iclass 21, count 0 2006.246.07:52:01.28#ibcon#about to read 5, iclass 21, count 0 2006.246.07:52:01.28#ibcon#read 5, iclass 21, count 0 2006.246.07:52:01.28#ibcon#about to read 6, iclass 21, count 0 2006.246.07:52:01.28#ibcon#read 6, iclass 21, count 0 2006.246.07:52:01.28#ibcon#end of sib2, iclass 21, count 0 2006.246.07:52:01.28#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:52:01.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:52:01.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:52:01.28#ibcon#*before write, iclass 21, count 0 2006.246.07:52:01.28#ibcon#enter sib2, iclass 21, count 0 2006.246.07:52:01.28#ibcon#flushed, iclass 21, count 0 2006.246.07:52:01.28#ibcon#about to write, iclass 21, count 0 2006.246.07:52:01.28#ibcon#wrote, iclass 21, count 0 2006.246.07:52:01.28#ibcon#about to read 3, iclass 21, count 0 2006.246.07:52:01.32#ibcon#read 3, iclass 21, count 0 2006.246.07:52:01.32#ibcon#about to read 4, iclass 21, count 0 2006.246.07:52:01.32#ibcon#read 4, iclass 21, count 0 2006.246.07:52:01.32#ibcon#about to read 5, iclass 21, count 0 2006.246.07:52:01.32#ibcon#read 5, iclass 21, count 0 2006.246.07:52:01.32#ibcon#about to read 6, iclass 21, count 0 2006.246.07:52:01.32#ibcon#read 6, iclass 21, count 0 2006.246.07:52:01.32#ibcon#end of sib2, iclass 21, count 0 2006.246.07:52:01.32#ibcon#*after write, iclass 21, count 0 2006.246.07:52:01.32#ibcon#*before return 0, iclass 21, count 0 2006.246.07:52:01.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:52:01.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.07:52:01.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:52:01.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:52:01.32$vc4f8/vb=3,4 2006.246.07:52:01.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.07:52:01.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.07:52:01.32#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:01.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:52:01.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:52:01.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:52:01.38#ibcon#enter wrdev, iclass 23, count 2 2006.246.07:52:01.38#ibcon#first serial, iclass 23, count 2 2006.246.07:52:01.38#ibcon#enter sib2, iclass 23, count 2 2006.246.07:52:01.38#ibcon#flushed, iclass 23, count 2 2006.246.07:52:01.38#ibcon#about to write, iclass 23, count 2 2006.246.07:52:01.38#ibcon#wrote, iclass 23, count 2 2006.246.07:52:01.38#ibcon#about to read 3, iclass 23, count 2 2006.246.07:52:01.40#ibcon#read 3, iclass 23, count 2 2006.246.07:52:01.40#ibcon#about to read 4, iclass 23, count 2 2006.246.07:52:01.40#ibcon#read 4, iclass 23, count 2 2006.246.07:52:01.40#ibcon#about to read 5, iclass 23, count 2 2006.246.07:52:01.40#ibcon#read 5, iclass 23, count 2 2006.246.07:52:01.40#ibcon#about to read 6, iclass 23, count 2 2006.246.07:52:01.40#ibcon#read 6, iclass 23, count 2 2006.246.07:52:01.40#ibcon#end of sib2, iclass 23, count 2 2006.246.07:52:01.40#ibcon#*mode == 0, iclass 23, count 2 2006.246.07:52:01.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.07:52:01.40#ibcon#[27=AT03-04\r\n] 2006.246.07:52:01.40#ibcon#*before write, iclass 23, count 2 2006.246.07:52:01.40#ibcon#enter sib2, iclass 23, count 2 2006.246.07:52:01.40#ibcon#flushed, iclass 23, count 2 2006.246.07:52:01.40#ibcon#about to write, iclass 23, count 2 2006.246.07:52:01.40#ibcon#wrote, iclass 23, count 2 2006.246.07:52:01.40#ibcon#about to read 3, iclass 23, count 2 2006.246.07:52:01.43#ibcon#read 3, iclass 23, count 2 2006.246.07:52:01.43#ibcon#about to read 4, iclass 23, count 2 2006.246.07:52:01.43#ibcon#read 4, iclass 23, count 2 2006.246.07:52:01.43#ibcon#about to read 5, iclass 23, count 2 2006.246.07:52:01.43#ibcon#read 5, iclass 23, count 2 2006.246.07:52:01.43#ibcon#about to read 6, iclass 23, count 2 2006.246.07:52:01.43#ibcon#read 6, iclass 23, count 2 2006.246.07:52:01.43#ibcon#end of sib2, iclass 23, count 2 2006.246.07:52:01.43#ibcon#*after write, iclass 23, count 2 2006.246.07:52:01.43#ibcon#*before return 0, iclass 23, count 2 2006.246.07:52:01.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:52:01.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.07:52:01.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.07:52:01.43#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:01.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:52:01.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:52:01.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:52:01.55#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:52:01.55#ibcon#first serial, iclass 23, count 0 2006.246.07:52:01.55#ibcon#enter sib2, iclass 23, count 0 2006.246.07:52:01.55#ibcon#flushed, iclass 23, count 0 2006.246.07:52:01.55#ibcon#about to write, iclass 23, count 0 2006.246.07:52:01.55#ibcon#wrote, iclass 23, count 0 2006.246.07:52:01.55#ibcon#about to read 3, iclass 23, count 0 2006.246.07:52:01.57#ibcon#read 3, iclass 23, count 0 2006.246.07:52:01.57#ibcon#about to read 4, iclass 23, count 0 2006.246.07:52:01.57#ibcon#read 4, iclass 23, count 0 2006.246.07:52:01.57#ibcon#about to read 5, iclass 23, count 0 2006.246.07:52:01.57#ibcon#read 5, iclass 23, count 0 2006.246.07:52:01.57#ibcon#about to read 6, iclass 23, count 0 2006.246.07:52:01.57#ibcon#read 6, iclass 23, count 0 2006.246.07:52:01.57#ibcon#end of sib2, iclass 23, count 0 2006.246.07:52:01.57#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:52:01.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:52:01.57#ibcon#[27=USB\r\n] 2006.246.07:52:01.57#ibcon#*before write, iclass 23, count 0 2006.246.07:52:01.57#ibcon#enter sib2, iclass 23, count 0 2006.246.07:52:01.57#ibcon#flushed, iclass 23, count 0 2006.246.07:52:01.57#ibcon#about to write, iclass 23, count 0 2006.246.07:52:01.57#ibcon#wrote, iclass 23, count 0 2006.246.07:52:01.57#ibcon#about to read 3, iclass 23, count 0 2006.246.07:52:01.60#ibcon#read 3, iclass 23, count 0 2006.246.07:52:01.60#ibcon#about to read 4, iclass 23, count 0 2006.246.07:52:01.60#ibcon#read 4, iclass 23, count 0 2006.246.07:52:01.60#ibcon#about to read 5, iclass 23, count 0 2006.246.07:52:01.60#ibcon#read 5, iclass 23, count 0 2006.246.07:52:01.60#ibcon#about to read 6, iclass 23, count 0 2006.246.07:52:01.60#ibcon#read 6, iclass 23, count 0 2006.246.07:52:01.60#ibcon#end of sib2, iclass 23, count 0 2006.246.07:52:01.60#ibcon#*after write, iclass 23, count 0 2006.246.07:52:01.60#ibcon#*before return 0, iclass 23, count 0 2006.246.07:52:01.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:52:01.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.07:52:01.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:52:01.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:52:01.60$vc4f8/vblo=4,712.99 2006.246.07:52:01.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.07:52:01.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.07:52:01.60#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:01.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:52:01.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:52:01.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:52:01.60#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:52:01.60#ibcon#first serial, iclass 25, count 0 2006.246.07:52:01.60#ibcon#enter sib2, iclass 25, count 0 2006.246.07:52:01.60#ibcon#flushed, iclass 25, count 0 2006.246.07:52:01.60#ibcon#about to write, iclass 25, count 0 2006.246.07:52:01.60#ibcon#wrote, iclass 25, count 0 2006.246.07:52:01.60#ibcon#about to read 3, iclass 25, count 0 2006.246.07:52:01.62#ibcon#read 3, iclass 25, count 0 2006.246.07:52:01.62#ibcon#about to read 4, iclass 25, count 0 2006.246.07:52:01.62#ibcon#read 4, iclass 25, count 0 2006.246.07:52:01.62#ibcon#about to read 5, iclass 25, count 0 2006.246.07:52:01.62#ibcon#read 5, iclass 25, count 0 2006.246.07:52:01.62#ibcon#about to read 6, iclass 25, count 0 2006.246.07:52:01.62#ibcon#read 6, iclass 25, count 0 2006.246.07:52:01.62#ibcon#end of sib2, iclass 25, count 0 2006.246.07:52:01.62#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:52:01.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:52:01.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:52:01.62#ibcon#*before write, iclass 25, count 0 2006.246.07:52:01.62#ibcon#enter sib2, iclass 25, count 0 2006.246.07:52:01.62#ibcon#flushed, iclass 25, count 0 2006.246.07:52:01.62#ibcon#about to write, iclass 25, count 0 2006.246.07:52:01.62#ibcon#wrote, iclass 25, count 0 2006.246.07:52:01.62#ibcon#about to read 3, iclass 25, count 0 2006.246.07:52:01.66#ibcon#read 3, iclass 25, count 0 2006.246.07:52:01.66#ibcon#about to read 4, iclass 25, count 0 2006.246.07:52:01.66#ibcon#read 4, iclass 25, count 0 2006.246.07:52:01.66#ibcon#about to read 5, iclass 25, count 0 2006.246.07:52:01.66#ibcon#read 5, iclass 25, count 0 2006.246.07:52:01.66#ibcon#about to read 6, iclass 25, count 0 2006.246.07:52:01.66#ibcon#read 6, iclass 25, count 0 2006.246.07:52:01.66#ibcon#end of sib2, iclass 25, count 0 2006.246.07:52:01.66#ibcon#*after write, iclass 25, count 0 2006.246.07:52:01.66#ibcon#*before return 0, iclass 25, count 0 2006.246.07:52:01.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:52:01.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.07:52:01.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:52:01.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:52:01.66$vc4f8/vb=4,4 2006.246.07:52:01.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.07:52:01.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.07:52:01.66#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:01.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:52:01.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:52:01.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:52:01.72#ibcon#enter wrdev, iclass 27, count 2 2006.246.07:52:01.72#ibcon#first serial, iclass 27, count 2 2006.246.07:52:01.72#ibcon#enter sib2, iclass 27, count 2 2006.246.07:52:01.72#ibcon#flushed, iclass 27, count 2 2006.246.07:52:01.72#ibcon#about to write, iclass 27, count 2 2006.246.07:52:01.72#ibcon#wrote, iclass 27, count 2 2006.246.07:52:01.72#ibcon#about to read 3, iclass 27, count 2 2006.246.07:52:01.74#ibcon#read 3, iclass 27, count 2 2006.246.07:52:01.74#ibcon#about to read 4, iclass 27, count 2 2006.246.07:52:01.74#ibcon#read 4, iclass 27, count 2 2006.246.07:52:01.74#ibcon#about to read 5, iclass 27, count 2 2006.246.07:52:01.74#ibcon#read 5, iclass 27, count 2 2006.246.07:52:01.74#ibcon#about to read 6, iclass 27, count 2 2006.246.07:52:01.74#ibcon#read 6, iclass 27, count 2 2006.246.07:52:01.74#ibcon#end of sib2, iclass 27, count 2 2006.246.07:52:01.74#ibcon#*mode == 0, iclass 27, count 2 2006.246.07:52:01.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.07:52:01.74#ibcon#[27=AT04-04\r\n] 2006.246.07:52:01.74#ibcon#*before write, iclass 27, count 2 2006.246.07:52:01.74#ibcon#enter sib2, iclass 27, count 2 2006.246.07:52:01.74#ibcon#flushed, iclass 27, count 2 2006.246.07:52:01.74#ibcon#about to write, iclass 27, count 2 2006.246.07:52:01.74#ibcon#wrote, iclass 27, count 2 2006.246.07:52:01.74#ibcon#about to read 3, iclass 27, count 2 2006.246.07:52:01.77#ibcon#read 3, iclass 27, count 2 2006.246.07:52:01.77#ibcon#about to read 4, iclass 27, count 2 2006.246.07:52:01.77#ibcon#read 4, iclass 27, count 2 2006.246.07:52:01.77#ibcon#about to read 5, iclass 27, count 2 2006.246.07:52:01.77#ibcon#read 5, iclass 27, count 2 2006.246.07:52:01.77#ibcon#about to read 6, iclass 27, count 2 2006.246.07:52:01.77#ibcon#read 6, iclass 27, count 2 2006.246.07:52:01.77#ibcon#end of sib2, iclass 27, count 2 2006.246.07:52:01.77#ibcon#*after write, iclass 27, count 2 2006.246.07:52:01.77#ibcon#*before return 0, iclass 27, count 2 2006.246.07:52:01.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:52:01.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.07:52:01.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.07:52:01.77#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:01.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:52:01.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:52:01.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:52:01.89#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:52:01.89#ibcon#first serial, iclass 27, count 0 2006.246.07:52:01.89#ibcon#enter sib2, iclass 27, count 0 2006.246.07:52:01.89#ibcon#flushed, iclass 27, count 0 2006.246.07:52:01.89#ibcon#about to write, iclass 27, count 0 2006.246.07:52:01.89#ibcon#wrote, iclass 27, count 0 2006.246.07:52:01.89#ibcon#about to read 3, iclass 27, count 0 2006.246.07:52:01.91#ibcon#read 3, iclass 27, count 0 2006.246.07:52:01.91#ibcon#about to read 4, iclass 27, count 0 2006.246.07:52:01.91#ibcon#read 4, iclass 27, count 0 2006.246.07:52:01.91#ibcon#about to read 5, iclass 27, count 0 2006.246.07:52:01.91#ibcon#read 5, iclass 27, count 0 2006.246.07:52:01.91#ibcon#about to read 6, iclass 27, count 0 2006.246.07:52:01.91#ibcon#read 6, iclass 27, count 0 2006.246.07:52:01.91#ibcon#end of sib2, iclass 27, count 0 2006.246.07:52:01.91#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:52:01.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:52:01.91#ibcon#[27=USB\r\n] 2006.246.07:52:01.91#ibcon#*before write, iclass 27, count 0 2006.246.07:52:01.91#ibcon#enter sib2, iclass 27, count 0 2006.246.07:52:01.91#ibcon#flushed, iclass 27, count 0 2006.246.07:52:01.91#ibcon#about to write, iclass 27, count 0 2006.246.07:52:01.91#ibcon#wrote, iclass 27, count 0 2006.246.07:52:01.91#ibcon#about to read 3, iclass 27, count 0 2006.246.07:52:01.94#ibcon#read 3, iclass 27, count 0 2006.246.07:52:01.94#ibcon#about to read 4, iclass 27, count 0 2006.246.07:52:01.94#ibcon#read 4, iclass 27, count 0 2006.246.07:52:01.94#ibcon#about to read 5, iclass 27, count 0 2006.246.07:52:01.94#ibcon#read 5, iclass 27, count 0 2006.246.07:52:01.94#ibcon#about to read 6, iclass 27, count 0 2006.246.07:52:01.94#ibcon#read 6, iclass 27, count 0 2006.246.07:52:01.94#ibcon#end of sib2, iclass 27, count 0 2006.246.07:52:01.94#ibcon#*after write, iclass 27, count 0 2006.246.07:52:01.94#ibcon#*before return 0, iclass 27, count 0 2006.246.07:52:01.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:52:01.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.07:52:01.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:52:01.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:52:01.94$vc4f8/vblo=5,744.99 2006.246.07:52:01.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.07:52:01.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.07:52:01.94#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:01.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:52:01.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:52:01.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:52:01.94#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:52:01.94#ibcon#first serial, iclass 29, count 0 2006.246.07:52:01.94#ibcon#enter sib2, iclass 29, count 0 2006.246.07:52:01.94#ibcon#flushed, iclass 29, count 0 2006.246.07:52:01.94#ibcon#about to write, iclass 29, count 0 2006.246.07:52:01.94#ibcon#wrote, iclass 29, count 0 2006.246.07:52:01.94#ibcon#about to read 3, iclass 29, count 0 2006.246.07:52:01.96#ibcon#read 3, iclass 29, count 0 2006.246.07:52:01.96#ibcon#about to read 4, iclass 29, count 0 2006.246.07:52:01.96#ibcon#read 4, iclass 29, count 0 2006.246.07:52:01.96#ibcon#about to read 5, iclass 29, count 0 2006.246.07:52:01.96#ibcon#read 5, iclass 29, count 0 2006.246.07:52:01.96#ibcon#about to read 6, iclass 29, count 0 2006.246.07:52:01.96#ibcon#read 6, iclass 29, count 0 2006.246.07:52:01.96#ibcon#end of sib2, iclass 29, count 0 2006.246.07:52:01.96#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:52:01.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:52:01.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:52:01.96#ibcon#*before write, iclass 29, count 0 2006.246.07:52:01.96#ibcon#enter sib2, iclass 29, count 0 2006.246.07:52:01.96#ibcon#flushed, iclass 29, count 0 2006.246.07:52:01.96#ibcon#about to write, iclass 29, count 0 2006.246.07:52:01.96#ibcon#wrote, iclass 29, count 0 2006.246.07:52:01.96#ibcon#about to read 3, iclass 29, count 0 2006.246.07:52:02.00#ibcon#read 3, iclass 29, count 0 2006.246.07:52:02.00#ibcon#about to read 4, iclass 29, count 0 2006.246.07:52:02.00#ibcon#read 4, iclass 29, count 0 2006.246.07:52:02.00#ibcon#about to read 5, iclass 29, count 0 2006.246.07:52:02.00#ibcon#read 5, iclass 29, count 0 2006.246.07:52:02.00#ibcon#about to read 6, iclass 29, count 0 2006.246.07:52:02.00#ibcon#read 6, iclass 29, count 0 2006.246.07:52:02.00#ibcon#end of sib2, iclass 29, count 0 2006.246.07:52:02.00#ibcon#*after write, iclass 29, count 0 2006.246.07:52:02.00#ibcon#*before return 0, iclass 29, count 0 2006.246.07:52:02.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:52:02.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.07:52:02.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:52:02.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:52:02.00$vc4f8/vb=5,3 2006.246.07:52:02.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.07:52:02.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.07:52:02.00#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:02.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:52:02.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:52:02.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:52:02.06#ibcon#enter wrdev, iclass 31, count 2 2006.246.07:52:02.06#ibcon#first serial, iclass 31, count 2 2006.246.07:52:02.06#ibcon#enter sib2, iclass 31, count 2 2006.246.07:52:02.06#ibcon#flushed, iclass 31, count 2 2006.246.07:52:02.06#ibcon#about to write, iclass 31, count 2 2006.246.07:52:02.06#ibcon#wrote, iclass 31, count 2 2006.246.07:52:02.06#ibcon#about to read 3, iclass 31, count 2 2006.246.07:52:02.08#ibcon#read 3, iclass 31, count 2 2006.246.07:52:02.08#ibcon#about to read 4, iclass 31, count 2 2006.246.07:52:02.08#ibcon#read 4, iclass 31, count 2 2006.246.07:52:02.08#ibcon#about to read 5, iclass 31, count 2 2006.246.07:52:02.08#ibcon#read 5, iclass 31, count 2 2006.246.07:52:02.08#ibcon#about to read 6, iclass 31, count 2 2006.246.07:52:02.08#ibcon#read 6, iclass 31, count 2 2006.246.07:52:02.08#ibcon#end of sib2, iclass 31, count 2 2006.246.07:52:02.08#ibcon#*mode == 0, iclass 31, count 2 2006.246.07:52:02.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.07:52:02.08#ibcon#[27=AT05-03\r\n] 2006.246.07:52:02.08#ibcon#*before write, iclass 31, count 2 2006.246.07:52:02.08#ibcon#enter sib2, iclass 31, count 2 2006.246.07:52:02.08#ibcon#flushed, iclass 31, count 2 2006.246.07:52:02.08#ibcon#about to write, iclass 31, count 2 2006.246.07:52:02.08#ibcon#wrote, iclass 31, count 2 2006.246.07:52:02.08#ibcon#about to read 3, iclass 31, count 2 2006.246.07:52:02.11#ibcon#read 3, iclass 31, count 2 2006.246.07:52:02.11#ibcon#about to read 4, iclass 31, count 2 2006.246.07:52:02.11#ibcon#read 4, iclass 31, count 2 2006.246.07:52:02.11#ibcon#about to read 5, iclass 31, count 2 2006.246.07:52:02.11#ibcon#read 5, iclass 31, count 2 2006.246.07:52:02.11#ibcon#about to read 6, iclass 31, count 2 2006.246.07:52:02.11#ibcon#read 6, iclass 31, count 2 2006.246.07:52:02.11#ibcon#end of sib2, iclass 31, count 2 2006.246.07:52:02.11#ibcon#*after write, iclass 31, count 2 2006.246.07:52:02.11#ibcon#*before return 0, iclass 31, count 2 2006.246.07:52:02.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:52:02.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.07:52:02.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.07:52:02.11#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:02.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:52:02.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:52:02.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:52:02.23#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:52:02.23#ibcon#first serial, iclass 31, count 0 2006.246.07:52:02.23#ibcon#enter sib2, iclass 31, count 0 2006.246.07:52:02.23#ibcon#flushed, iclass 31, count 0 2006.246.07:52:02.23#ibcon#about to write, iclass 31, count 0 2006.246.07:52:02.23#ibcon#wrote, iclass 31, count 0 2006.246.07:52:02.23#ibcon#about to read 3, iclass 31, count 0 2006.246.07:52:02.25#ibcon#read 3, iclass 31, count 0 2006.246.07:52:02.25#ibcon#about to read 4, iclass 31, count 0 2006.246.07:52:02.25#ibcon#read 4, iclass 31, count 0 2006.246.07:52:02.25#ibcon#about to read 5, iclass 31, count 0 2006.246.07:52:02.25#ibcon#read 5, iclass 31, count 0 2006.246.07:52:02.25#ibcon#about to read 6, iclass 31, count 0 2006.246.07:52:02.25#ibcon#read 6, iclass 31, count 0 2006.246.07:52:02.25#ibcon#end of sib2, iclass 31, count 0 2006.246.07:52:02.25#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:52:02.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:52:02.25#ibcon#[27=USB\r\n] 2006.246.07:52:02.25#ibcon#*before write, iclass 31, count 0 2006.246.07:52:02.25#ibcon#enter sib2, iclass 31, count 0 2006.246.07:52:02.25#ibcon#flushed, iclass 31, count 0 2006.246.07:52:02.25#ibcon#about to write, iclass 31, count 0 2006.246.07:52:02.25#ibcon#wrote, iclass 31, count 0 2006.246.07:52:02.25#ibcon#about to read 3, iclass 31, count 0 2006.246.07:52:02.28#ibcon#read 3, iclass 31, count 0 2006.246.07:52:02.28#ibcon#about to read 4, iclass 31, count 0 2006.246.07:52:02.28#ibcon#read 4, iclass 31, count 0 2006.246.07:52:02.28#ibcon#about to read 5, iclass 31, count 0 2006.246.07:52:02.28#ibcon#read 5, iclass 31, count 0 2006.246.07:52:02.28#ibcon#about to read 6, iclass 31, count 0 2006.246.07:52:02.28#ibcon#read 6, iclass 31, count 0 2006.246.07:52:02.28#ibcon#end of sib2, iclass 31, count 0 2006.246.07:52:02.28#ibcon#*after write, iclass 31, count 0 2006.246.07:52:02.28#ibcon#*before return 0, iclass 31, count 0 2006.246.07:52:02.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:52:02.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.07:52:02.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:52:02.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:52:02.28$vc4f8/vblo=6,752.99 2006.246.07:52:02.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.07:52:02.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.07:52:02.28#ibcon#ireg 17 cls_cnt 0 2006.246.07:52:02.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:52:02.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:52:02.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:52:02.28#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:52:02.28#ibcon#first serial, iclass 33, count 0 2006.246.07:52:02.28#ibcon#enter sib2, iclass 33, count 0 2006.246.07:52:02.28#ibcon#flushed, iclass 33, count 0 2006.246.07:52:02.28#ibcon#about to write, iclass 33, count 0 2006.246.07:52:02.28#ibcon#wrote, iclass 33, count 0 2006.246.07:52:02.28#ibcon#about to read 3, iclass 33, count 0 2006.246.07:52:02.30#ibcon#read 3, iclass 33, count 0 2006.246.07:52:02.30#ibcon#about to read 4, iclass 33, count 0 2006.246.07:52:02.30#ibcon#read 4, iclass 33, count 0 2006.246.07:52:02.30#ibcon#about to read 5, iclass 33, count 0 2006.246.07:52:02.30#ibcon#read 5, iclass 33, count 0 2006.246.07:52:02.30#ibcon#about to read 6, iclass 33, count 0 2006.246.07:52:02.30#ibcon#read 6, iclass 33, count 0 2006.246.07:52:02.30#ibcon#end of sib2, iclass 33, count 0 2006.246.07:52:02.30#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:52:02.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:52:02.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:52:02.30#ibcon#*before write, iclass 33, count 0 2006.246.07:52:02.30#ibcon#enter sib2, iclass 33, count 0 2006.246.07:52:02.30#ibcon#flushed, iclass 33, count 0 2006.246.07:52:02.30#ibcon#about to write, iclass 33, count 0 2006.246.07:52:02.30#ibcon#wrote, iclass 33, count 0 2006.246.07:52:02.30#ibcon#about to read 3, iclass 33, count 0 2006.246.07:52:02.34#ibcon#read 3, iclass 33, count 0 2006.246.07:52:02.34#ibcon#about to read 4, iclass 33, count 0 2006.246.07:52:02.34#ibcon#read 4, iclass 33, count 0 2006.246.07:52:02.34#ibcon#about to read 5, iclass 33, count 0 2006.246.07:52:02.34#ibcon#read 5, iclass 33, count 0 2006.246.07:52:02.34#ibcon#about to read 6, iclass 33, count 0 2006.246.07:52:02.34#ibcon#read 6, iclass 33, count 0 2006.246.07:52:02.34#ibcon#end of sib2, iclass 33, count 0 2006.246.07:52:02.34#ibcon#*after write, iclass 33, count 0 2006.246.07:52:02.34#ibcon#*before return 0, iclass 33, count 0 2006.246.07:52:02.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:52:02.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.07:52:02.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:52:02.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:52:02.34$vc4f8/vb=6,3 2006.246.07:52:02.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.07:52:02.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.07:52:02.34#ibcon#ireg 11 cls_cnt 2 2006.246.07:52:02.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:52:02.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:52:02.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:52:02.40#ibcon#enter wrdev, iclass 35, count 2 2006.246.07:52:02.40#ibcon#first serial, iclass 35, count 2 2006.246.07:52:02.40#ibcon#enter sib2, iclass 35, count 2 2006.246.07:52:02.40#ibcon#flushed, iclass 35, count 2 2006.246.07:52:02.40#ibcon#about to write, iclass 35, count 2 2006.246.07:52:02.40#ibcon#wrote, iclass 35, count 2 2006.246.07:52:02.40#ibcon#about to read 3, iclass 35, count 2 2006.246.07:52:02.42#ibcon#read 3, iclass 35, count 2 2006.246.07:52:02.42#ibcon#about to read 4, iclass 35, count 2 2006.246.07:52:02.42#ibcon#read 4, iclass 35, count 2 2006.246.07:52:02.42#ibcon#about to read 5, iclass 35, count 2 2006.246.07:52:02.42#ibcon#read 5, iclass 35, count 2 2006.246.07:52:02.42#ibcon#about to read 6, iclass 35, count 2 2006.246.07:52:02.42#ibcon#read 6, iclass 35, count 2 2006.246.07:52:02.42#ibcon#end of sib2, iclass 35, count 2 2006.246.07:52:02.42#ibcon#*mode == 0, iclass 35, count 2 2006.246.07:52:02.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.07:52:02.42#ibcon#[27=AT06-03\r\n] 2006.246.07:52:02.42#ibcon#*before write, iclass 35, count 2 2006.246.07:52:02.42#ibcon#enter sib2, iclass 35, count 2 2006.246.07:52:02.42#ibcon#flushed, iclass 35, count 2 2006.246.07:52:02.42#ibcon#about to write, iclass 35, count 2 2006.246.07:52:02.42#ibcon#wrote, iclass 35, count 2 2006.246.07:52:02.42#ibcon#about to read 3, iclass 35, count 2 2006.246.07:52:02.45#ibcon#read 3, iclass 35, count 2 2006.246.07:52:02.45#ibcon#about to read 4, iclass 35, count 2 2006.246.07:52:02.45#ibcon#read 4, iclass 35, count 2 2006.246.07:52:02.45#ibcon#about to read 5, iclass 35, count 2 2006.246.07:52:02.45#ibcon#read 5, iclass 35, count 2 2006.246.07:52:02.45#ibcon#about to read 6, iclass 35, count 2 2006.246.07:52:02.45#ibcon#read 6, iclass 35, count 2 2006.246.07:52:02.45#ibcon#end of sib2, iclass 35, count 2 2006.246.07:52:02.45#ibcon#*after write, iclass 35, count 2 2006.246.07:52:02.45#ibcon#*before return 0, iclass 35, count 2 2006.246.07:52:02.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:52:02.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.07:52:02.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.07:52:02.45#ibcon#ireg 7 cls_cnt 0 2006.246.07:52:02.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:52:02.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:52:02.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:52:02.57#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:52:02.57#ibcon#first serial, iclass 35, count 0 2006.246.07:52:02.57#ibcon#enter sib2, iclass 35, count 0 2006.246.07:52:02.57#ibcon#flushed, iclass 35, count 0 2006.246.07:52:02.57#ibcon#about to write, iclass 35, count 0 2006.246.07:52:02.57#ibcon#wrote, iclass 35, count 0 2006.246.07:52:02.57#ibcon#about to read 3, iclass 35, count 0 2006.246.07:52:02.59#ibcon#read 3, iclass 35, count 0 2006.246.07:52:02.59#ibcon#about to read 4, iclass 35, count 0 2006.246.07:52:02.59#ibcon#read 4, iclass 35, count 0 2006.246.07:52:02.59#ibcon#about to read 5, iclass 35, count 0 2006.246.07:52:02.59#ibcon#read 5, iclass 35, count 0 2006.246.07:52:02.59#ibcon#about to read 6, iclass 35, count 0 2006.246.07:52:02.59#ibcon#read 6, iclass 35, count 0 2006.246.07:52:02.59#ibcon#end of sib2, iclass 35, count 0 2006.246.07:52:02.59#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:52:02.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:52:02.59#ibcon#[27=USB\r\n] 2006.246.07:52:02.59#ibcon#*before write, iclass 35, count 0 2006.246.07:52:02.59#ibcon#enter sib2, iclass 35, count 0 2006.246.07:52:02.59#ibcon#flushed, iclass 35, count 0 2006.246.07:52:02.59#ibcon#about to write, iclass 35, count 0 2006.246.07:52:02.59#ibcon#wrote, iclass 35, count 0 2006.246.07:52:02.59#ibcon#about to read 3, iclass 35, count 0 2006.246.07:52:02.62#ibcon#read 3, iclass 35, count 0 2006.246.07:52:02.62#ibcon#about to read 4, iclass 35, count 0 2006.246.07:52:02.62#ibcon#read 4, iclass 35, count 0 2006.246.07:52:02.62#ibcon#about to read 5, iclass 35, count 0 2006.246.07:52:02.62#ibcon#read 5, iclass 35, count 0 2006.246.07:52:02.62#ibcon#about to read 6, iclass 35, count 0 2006.246.07:52:02.62#ibcon#read 6, iclass 35, count 0 2006.246.07:52:02.62#ibcon#end of sib2, iclass 35, count 0 2006.246.07:52:02.62#ibcon#*after write, iclass 35, count 0 2006.246.07:52:02.62#ibcon#*before return 0, iclass 35, count 0 2006.246.07:52:02.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:52:02.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.07:52:02.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:52:02.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:52:02.62$vc4f8/vabw=wide 2006.246.07:52:02.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.07:52:02.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.07:52:02.62#ibcon#ireg 8 cls_cnt 0 2006.246.07:52:02.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:52:02.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:52:02.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:52:02.62#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:52:02.62#ibcon#first serial, iclass 37, count 0 2006.246.07:52:02.62#ibcon#enter sib2, iclass 37, count 0 2006.246.07:52:02.62#ibcon#flushed, iclass 37, count 0 2006.246.07:52:02.62#ibcon#about to write, iclass 37, count 0 2006.246.07:52:02.62#ibcon#wrote, iclass 37, count 0 2006.246.07:52:02.62#ibcon#about to read 3, iclass 37, count 0 2006.246.07:52:02.64#ibcon#read 3, iclass 37, count 0 2006.246.07:52:02.64#ibcon#about to read 4, iclass 37, count 0 2006.246.07:52:02.64#ibcon#read 4, iclass 37, count 0 2006.246.07:52:02.64#ibcon#about to read 5, iclass 37, count 0 2006.246.07:52:02.64#ibcon#read 5, iclass 37, count 0 2006.246.07:52:02.64#ibcon#about to read 6, iclass 37, count 0 2006.246.07:52:02.64#ibcon#read 6, iclass 37, count 0 2006.246.07:52:02.64#ibcon#end of sib2, iclass 37, count 0 2006.246.07:52:02.64#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:52:02.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:52:02.64#ibcon#[25=BW32\r\n] 2006.246.07:52:02.64#ibcon#*before write, iclass 37, count 0 2006.246.07:52:02.64#ibcon#enter sib2, iclass 37, count 0 2006.246.07:52:02.64#ibcon#flushed, iclass 37, count 0 2006.246.07:52:02.64#ibcon#about to write, iclass 37, count 0 2006.246.07:52:02.64#ibcon#wrote, iclass 37, count 0 2006.246.07:52:02.64#ibcon#about to read 3, iclass 37, count 0 2006.246.07:52:02.67#ibcon#read 3, iclass 37, count 0 2006.246.07:52:02.67#ibcon#about to read 4, iclass 37, count 0 2006.246.07:52:02.67#ibcon#read 4, iclass 37, count 0 2006.246.07:52:02.67#ibcon#about to read 5, iclass 37, count 0 2006.246.07:52:02.67#ibcon#read 5, iclass 37, count 0 2006.246.07:52:02.67#ibcon#about to read 6, iclass 37, count 0 2006.246.07:52:02.67#ibcon#read 6, iclass 37, count 0 2006.246.07:52:02.67#ibcon#end of sib2, iclass 37, count 0 2006.246.07:52:02.67#ibcon#*after write, iclass 37, count 0 2006.246.07:52:02.67#ibcon#*before return 0, iclass 37, count 0 2006.246.07:52:02.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:52:02.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.07:52:02.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:52:02.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:52:02.67$vc4f8/vbbw=wide 2006.246.07:52:02.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:52:02.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:52:02.67#ibcon#ireg 8 cls_cnt 0 2006.246.07:52:02.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:52:02.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:52:02.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:52:02.74#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:52:02.74#ibcon#first serial, iclass 39, count 0 2006.246.07:52:02.74#ibcon#enter sib2, iclass 39, count 0 2006.246.07:52:02.74#ibcon#flushed, iclass 39, count 0 2006.246.07:52:02.74#ibcon#about to write, iclass 39, count 0 2006.246.07:52:02.74#ibcon#wrote, iclass 39, count 0 2006.246.07:52:02.74#ibcon#about to read 3, iclass 39, count 0 2006.246.07:52:02.76#ibcon#read 3, iclass 39, count 0 2006.246.07:52:02.76#ibcon#about to read 4, iclass 39, count 0 2006.246.07:52:02.76#ibcon#read 4, iclass 39, count 0 2006.246.07:52:02.76#ibcon#about to read 5, iclass 39, count 0 2006.246.07:52:02.76#ibcon#read 5, iclass 39, count 0 2006.246.07:52:02.76#ibcon#about to read 6, iclass 39, count 0 2006.246.07:52:02.76#ibcon#read 6, iclass 39, count 0 2006.246.07:52:02.76#ibcon#end of sib2, iclass 39, count 0 2006.246.07:52:02.76#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:52:02.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:52:02.76#ibcon#[27=BW32\r\n] 2006.246.07:52:02.76#ibcon#*before write, iclass 39, count 0 2006.246.07:52:02.76#ibcon#enter sib2, iclass 39, count 0 2006.246.07:52:02.76#ibcon#flushed, iclass 39, count 0 2006.246.07:52:02.76#ibcon#about to write, iclass 39, count 0 2006.246.07:52:02.76#ibcon#wrote, iclass 39, count 0 2006.246.07:52:02.76#ibcon#about to read 3, iclass 39, count 0 2006.246.07:52:02.79#ibcon#read 3, iclass 39, count 0 2006.246.07:52:02.79#ibcon#about to read 4, iclass 39, count 0 2006.246.07:52:02.79#ibcon#read 4, iclass 39, count 0 2006.246.07:52:02.79#ibcon#about to read 5, iclass 39, count 0 2006.246.07:52:02.79#ibcon#read 5, iclass 39, count 0 2006.246.07:52:02.79#ibcon#about to read 6, iclass 39, count 0 2006.246.07:52:02.79#ibcon#read 6, iclass 39, count 0 2006.246.07:52:02.79#ibcon#end of sib2, iclass 39, count 0 2006.246.07:52:02.79#ibcon#*after write, iclass 39, count 0 2006.246.07:52:02.79#ibcon#*before return 0, iclass 39, count 0 2006.246.07:52:02.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:52:02.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:52:02.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:52:02.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:52:02.79$4f8m12a/ifd4f 2006.246.07:52:02.79$ifd4f/lo= 2006.246.07:52:02.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:52:02.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:52:02.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:52:02.79$ifd4f/patch= 2006.246.07:52:02.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:52:02.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:52:02.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:52:02.79$4f8m12a/"form=m,16.000,1:2 2006.246.07:52:02.79$4f8m12a/"tpicd 2006.246.07:52:02.79$4f8m12a/echo=off 2006.246.07:52:02.79$4f8m12a/xlog=off 2006.246.07:52:02.79:!2006.246.07:52:40 2006.246.07:52:20.14#trakl#Source acquired 2006.246.07:52:21.14#flagr#flagr/antenna,acquired 2006.246.07:52:40.00:preob 2006.246.07:52:40.14/onsource/TRACKING 2006.246.07:52:40.14:!2006.246.07:52:50 2006.246.07:52:50.00:data_valid=on 2006.246.07:52:50.00:midob 2006.246.07:52:51.14/onsource/TRACKING 2006.246.07:52:51.14/wx/26.72,1005.7,73 2006.246.07:52:51.34/cable/+6.4142E-03 2006.246.07:52:52.43/va/01,08,usb,yes,37,39 2006.246.07:52:52.43/va/02,07,usb,yes,36,38 2006.246.07:52:52.43/va/03,06,usb,yes,38,39 2006.246.07:52:52.43/va/04,07,usb,yes,37,40 2006.246.07:52:52.43/va/05,07,usb,yes,40,42 2006.246.07:52:52.43/va/06,07,usb,yes,35,35 2006.246.07:52:52.43/va/07,07,usb,yes,35,35 2006.246.07:52:52.43/va/08,08,usb,yes,30,30 2006.246.07:52:52.66/valo/01,532.99,yes,locked 2006.246.07:52:52.66/valo/02,572.99,yes,locked 2006.246.07:52:52.66/valo/03,672.99,yes,locked 2006.246.07:52:52.66/valo/04,832.99,yes,locked 2006.246.07:52:52.66/valo/05,652.99,yes,locked 2006.246.07:52:52.66/valo/06,772.99,yes,locked 2006.246.07:52:52.66/valo/07,832.99,yes,locked 2006.246.07:52:52.66/valo/08,852.99,yes,locked 2006.246.07:52:53.75/vb/01,04,usb,yes,34,32 2006.246.07:52:53.75/vb/02,04,usb,yes,36,37 2006.246.07:52:53.75/vb/03,04,usb,yes,32,36 2006.246.07:52:53.75/vb/04,04,usb,yes,33,33 2006.246.07:52:53.75/vb/05,03,usb,yes,38,44 2006.246.07:52:53.75/vb/06,03,usb,yes,39,43 2006.246.07:52:53.75/vb/07,04,usb,yes,34,34 2006.246.07:52:53.75/vb/08,03,usb,yes,39,43 2006.246.07:52:53.98/vblo/01,632.99,yes,locked 2006.246.07:52:53.98/vblo/02,640.99,yes,locked 2006.246.07:52:53.98/vblo/03,656.99,yes,locked 2006.246.07:52:53.98/vblo/04,712.99,yes,locked 2006.246.07:52:53.98/vblo/05,744.99,yes,locked 2006.246.07:52:53.98/vblo/06,752.99,yes,locked 2006.246.07:52:53.98/vblo/07,734.99,yes,locked 2006.246.07:52:53.98/vblo/08,744.99,yes,locked 2006.246.07:52:54.13/vabw/8 2006.246.07:52:54.28/vbbw/8 2006.246.07:52:54.40/xfe/off,on,13.2 2006.246.07:52:54.78/ifatt/23,28,28,28 2006.246.07:52:55.07/fmout-gps/S +4.36E-07 2006.246.07:52:55.11:!2006.246.07:53:50 2006.246.07:53:50.00:data_valid=off 2006.246.07:53:50.00:postob 2006.246.07:53:50.22/cable/+6.4138E-03 2006.246.07:53:50.22/wx/26.70,1005.7,73 2006.246.07:53:51.07/fmout-gps/S +4.37E-07 2006.246.07:53:51.07:scan_name=246-0755,k06246,60 2006.246.07:53:51.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.246.07:53:51.14#flagr#flagr/antenna,new-source 2006.246.07:53:52.12:checkk5 2006.246.07:53:52.49/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:53:52.87/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:53:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:53:53.69/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:53:54.05/chk_obsdata//k5ts1/T2460752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:53:54.43/chk_obsdata//k5ts2/T2460752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:53:54.80/chk_obsdata//k5ts3/T2460752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:53:55.16/chk_obsdata//k5ts4/T2460752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:53:55.86/k5log//k5ts1_log_newline 2006.246.07:53:56.56/k5log//k5ts2_log_newline 2006.246.07:53:57.25/k5log//k5ts3_log_newline 2006.246.07:53:57.93/k5log//k5ts4_log_newline 2006.246.07:53:57.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:53:57.96:4f8m12a=2 2006.246.07:53:57.96$4f8m12a/echo=on 2006.246.07:53:57.96$4f8m12a/pcalon 2006.246.07:53:57.96$pcalon/"no phase cal control is implemented here 2006.246.07:53:57.96$4f8m12a/"tpicd=stop 2006.246.07:53:57.96$4f8m12a/vc4f8 2006.246.07:53:57.96$vc4f8/valo=1,532.99 2006.246.07:53:57.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.07:53:57.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.07:53:57.96#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:57.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:53:57.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:53:57.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:53:57.96#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:53:57.96#ibcon#first serial, iclass 14, count 0 2006.246.07:53:57.96#ibcon#enter sib2, iclass 14, count 0 2006.246.07:53:57.96#ibcon#flushed, iclass 14, count 0 2006.246.07:53:57.96#ibcon#about to write, iclass 14, count 0 2006.246.07:53:57.96#ibcon#wrote, iclass 14, count 0 2006.246.07:53:57.96#ibcon#about to read 3, iclass 14, count 0 2006.246.07:53:58.00#ibcon#read 3, iclass 14, count 0 2006.246.07:53:58.00#ibcon#about to read 4, iclass 14, count 0 2006.246.07:53:58.00#ibcon#read 4, iclass 14, count 0 2006.246.07:53:58.00#ibcon#about to read 5, iclass 14, count 0 2006.246.07:53:58.00#ibcon#read 5, iclass 14, count 0 2006.246.07:53:58.00#ibcon#about to read 6, iclass 14, count 0 2006.246.07:53:58.00#ibcon#read 6, iclass 14, count 0 2006.246.07:53:58.00#ibcon#end of sib2, iclass 14, count 0 2006.246.07:53:58.00#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:53:58.00#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:53:58.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:53:58.00#ibcon#*before write, iclass 14, count 0 2006.246.07:53:58.00#ibcon#enter sib2, iclass 14, count 0 2006.246.07:53:58.00#ibcon#flushed, iclass 14, count 0 2006.246.07:53:58.00#ibcon#about to write, iclass 14, count 0 2006.246.07:53:58.00#ibcon#wrote, iclass 14, count 0 2006.246.07:53:58.00#ibcon#about to read 3, iclass 14, count 0 2006.246.07:53:58.05#ibcon#read 3, iclass 14, count 0 2006.246.07:53:58.05#ibcon#about to read 4, iclass 14, count 0 2006.246.07:53:58.05#ibcon#read 4, iclass 14, count 0 2006.246.07:53:58.05#ibcon#about to read 5, iclass 14, count 0 2006.246.07:53:58.05#ibcon#read 5, iclass 14, count 0 2006.246.07:53:58.05#ibcon#about to read 6, iclass 14, count 0 2006.246.07:53:58.05#ibcon#read 6, iclass 14, count 0 2006.246.07:53:58.05#ibcon#end of sib2, iclass 14, count 0 2006.246.07:53:58.05#ibcon#*after write, iclass 14, count 0 2006.246.07:53:58.05#ibcon#*before return 0, iclass 14, count 0 2006.246.07:53:58.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:53:58.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:53:58.05#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:53:58.05#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:53:58.05$vc4f8/va=1,8 2006.246.07:53:58.05#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.07:53:58.05#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.07:53:58.05#ibcon#ireg 11 cls_cnt 2 2006.246.07:53:58.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:53:58.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:53:58.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:53:58.05#ibcon#enter wrdev, iclass 16, count 2 2006.246.07:53:58.05#ibcon#first serial, iclass 16, count 2 2006.246.07:53:58.05#ibcon#enter sib2, iclass 16, count 2 2006.246.07:53:58.05#ibcon#flushed, iclass 16, count 2 2006.246.07:53:58.05#ibcon#about to write, iclass 16, count 2 2006.246.07:53:58.05#ibcon#wrote, iclass 16, count 2 2006.246.07:53:58.05#ibcon#about to read 3, iclass 16, count 2 2006.246.07:53:58.07#ibcon#read 3, iclass 16, count 2 2006.246.07:53:58.07#ibcon#about to read 4, iclass 16, count 2 2006.246.07:53:58.07#ibcon#read 4, iclass 16, count 2 2006.246.07:53:58.07#ibcon#about to read 5, iclass 16, count 2 2006.246.07:53:58.07#ibcon#read 5, iclass 16, count 2 2006.246.07:53:58.07#ibcon#about to read 6, iclass 16, count 2 2006.246.07:53:58.07#ibcon#read 6, iclass 16, count 2 2006.246.07:53:58.07#ibcon#end of sib2, iclass 16, count 2 2006.246.07:53:58.07#ibcon#*mode == 0, iclass 16, count 2 2006.246.07:53:58.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.07:53:58.07#ibcon#[25=AT01-08\r\n] 2006.246.07:53:58.07#ibcon#*before write, iclass 16, count 2 2006.246.07:53:58.07#ibcon#enter sib2, iclass 16, count 2 2006.246.07:53:58.07#ibcon#flushed, iclass 16, count 2 2006.246.07:53:58.07#ibcon#about to write, iclass 16, count 2 2006.246.07:53:58.07#ibcon#wrote, iclass 16, count 2 2006.246.07:53:58.07#ibcon#about to read 3, iclass 16, count 2 2006.246.07:53:58.10#ibcon#read 3, iclass 16, count 2 2006.246.07:53:58.10#ibcon#about to read 4, iclass 16, count 2 2006.246.07:53:58.10#ibcon#read 4, iclass 16, count 2 2006.246.07:53:58.10#ibcon#about to read 5, iclass 16, count 2 2006.246.07:53:58.10#ibcon#read 5, iclass 16, count 2 2006.246.07:53:58.10#ibcon#about to read 6, iclass 16, count 2 2006.246.07:53:58.10#ibcon#read 6, iclass 16, count 2 2006.246.07:53:58.10#ibcon#end of sib2, iclass 16, count 2 2006.246.07:53:58.10#ibcon#*after write, iclass 16, count 2 2006.246.07:53:58.10#ibcon#*before return 0, iclass 16, count 2 2006.246.07:53:58.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:53:58.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:53:58.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.07:53:58.10#ibcon#ireg 7 cls_cnt 0 2006.246.07:53:58.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:53:58.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:53:58.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:53:58.22#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:53:58.22#ibcon#first serial, iclass 16, count 0 2006.246.07:53:58.22#ibcon#enter sib2, iclass 16, count 0 2006.246.07:53:58.22#ibcon#flushed, iclass 16, count 0 2006.246.07:53:58.22#ibcon#about to write, iclass 16, count 0 2006.246.07:53:58.22#ibcon#wrote, iclass 16, count 0 2006.246.07:53:58.22#ibcon#about to read 3, iclass 16, count 0 2006.246.07:53:58.24#ibcon#read 3, iclass 16, count 0 2006.246.07:53:58.24#ibcon#about to read 4, iclass 16, count 0 2006.246.07:53:58.24#ibcon#read 4, iclass 16, count 0 2006.246.07:53:58.24#ibcon#about to read 5, iclass 16, count 0 2006.246.07:53:58.24#ibcon#read 5, iclass 16, count 0 2006.246.07:53:58.24#ibcon#about to read 6, iclass 16, count 0 2006.246.07:53:58.24#ibcon#read 6, iclass 16, count 0 2006.246.07:53:58.24#ibcon#end of sib2, iclass 16, count 0 2006.246.07:53:58.24#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:53:58.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:53:58.24#ibcon#[25=USB\r\n] 2006.246.07:53:58.24#ibcon#*before write, iclass 16, count 0 2006.246.07:53:58.24#ibcon#enter sib2, iclass 16, count 0 2006.246.07:53:58.24#ibcon#flushed, iclass 16, count 0 2006.246.07:53:58.24#ibcon#about to write, iclass 16, count 0 2006.246.07:53:58.24#ibcon#wrote, iclass 16, count 0 2006.246.07:53:58.24#ibcon#about to read 3, iclass 16, count 0 2006.246.07:53:58.27#ibcon#read 3, iclass 16, count 0 2006.246.07:53:58.27#ibcon#about to read 4, iclass 16, count 0 2006.246.07:53:58.27#ibcon#read 4, iclass 16, count 0 2006.246.07:53:58.27#ibcon#about to read 5, iclass 16, count 0 2006.246.07:53:58.27#ibcon#read 5, iclass 16, count 0 2006.246.07:53:58.27#ibcon#about to read 6, iclass 16, count 0 2006.246.07:53:58.27#ibcon#read 6, iclass 16, count 0 2006.246.07:53:58.27#ibcon#end of sib2, iclass 16, count 0 2006.246.07:53:58.27#ibcon#*after write, iclass 16, count 0 2006.246.07:53:58.27#ibcon#*before return 0, iclass 16, count 0 2006.246.07:53:58.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:53:58.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:53:58.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:53:58.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:53:58.27$vc4f8/valo=2,572.99 2006.246.07:53:58.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:53:58.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:53:58.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:58.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:53:58.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:53:58.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:53:58.27#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:53:58.27#ibcon#first serial, iclass 18, count 0 2006.246.07:53:58.27#ibcon#enter sib2, iclass 18, count 0 2006.246.07:53:58.27#ibcon#flushed, iclass 18, count 0 2006.246.07:53:58.27#ibcon#about to write, iclass 18, count 0 2006.246.07:53:58.27#ibcon#wrote, iclass 18, count 0 2006.246.07:53:58.27#ibcon#about to read 3, iclass 18, count 0 2006.246.07:53:58.29#ibcon#read 3, iclass 18, count 0 2006.246.07:53:58.29#ibcon#about to read 4, iclass 18, count 0 2006.246.07:53:58.29#ibcon#read 4, iclass 18, count 0 2006.246.07:53:58.29#ibcon#about to read 5, iclass 18, count 0 2006.246.07:53:58.29#ibcon#read 5, iclass 18, count 0 2006.246.07:53:58.29#ibcon#about to read 6, iclass 18, count 0 2006.246.07:53:58.29#ibcon#read 6, iclass 18, count 0 2006.246.07:53:58.29#ibcon#end of sib2, iclass 18, count 0 2006.246.07:53:58.29#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:53:58.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:53:58.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:53:58.29#ibcon#*before write, iclass 18, count 0 2006.246.07:53:58.29#ibcon#enter sib2, iclass 18, count 0 2006.246.07:53:58.29#ibcon#flushed, iclass 18, count 0 2006.246.07:53:58.29#ibcon#about to write, iclass 18, count 0 2006.246.07:53:58.29#ibcon#wrote, iclass 18, count 0 2006.246.07:53:58.29#ibcon#about to read 3, iclass 18, count 0 2006.246.07:53:58.33#ibcon#read 3, iclass 18, count 0 2006.246.07:53:58.33#ibcon#about to read 4, iclass 18, count 0 2006.246.07:53:58.33#ibcon#read 4, iclass 18, count 0 2006.246.07:53:58.33#ibcon#about to read 5, iclass 18, count 0 2006.246.07:53:58.33#ibcon#read 5, iclass 18, count 0 2006.246.07:53:58.33#ibcon#about to read 6, iclass 18, count 0 2006.246.07:53:58.33#ibcon#read 6, iclass 18, count 0 2006.246.07:53:58.33#ibcon#end of sib2, iclass 18, count 0 2006.246.07:53:58.33#ibcon#*after write, iclass 18, count 0 2006.246.07:53:58.33#ibcon#*before return 0, iclass 18, count 0 2006.246.07:53:58.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:53:58.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:53:58.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:53:58.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:53:58.33$vc4f8/va=2,7 2006.246.07:53:58.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.07:53:58.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.07:53:58.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:53:58.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:53:58.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:53:58.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:53:58.40#ibcon#enter wrdev, iclass 20, count 2 2006.246.07:53:58.40#ibcon#first serial, iclass 20, count 2 2006.246.07:53:58.40#ibcon#enter sib2, iclass 20, count 2 2006.246.07:53:58.40#ibcon#flushed, iclass 20, count 2 2006.246.07:53:58.40#ibcon#about to write, iclass 20, count 2 2006.246.07:53:58.40#ibcon#wrote, iclass 20, count 2 2006.246.07:53:58.40#ibcon#about to read 3, iclass 20, count 2 2006.246.07:53:58.41#ibcon#read 3, iclass 20, count 2 2006.246.07:53:58.41#ibcon#about to read 4, iclass 20, count 2 2006.246.07:53:58.41#ibcon#read 4, iclass 20, count 2 2006.246.07:53:58.41#ibcon#about to read 5, iclass 20, count 2 2006.246.07:53:58.41#ibcon#read 5, iclass 20, count 2 2006.246.07:53:58.41#ibcon#about to read 6, iclass 20, count 2 2006.246.07:53:58.41#ibcon#read 6, iclass 20, count 2 2006.246.07:53:58.41#ibcon#end of sib2, iclass 20, count 2 2006.246.07:53:58.41#ibcon#*mode == 0, iclass 20, count 2 2006.246.07:53:58.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.07:53:58.41#ibcon#[25=AT02-07\r\n] 2006.246.07:53:58.41#ibcon#*before write, iclass 20, count 2 2006.246.07:53:58.41#ibcon#enter sib2, iclass 20, count 2 2006.246.07:53:58.41#ibcon#flushed, iclass 20, count 2 2006.246.07:53:58.41#ibcon#about to write, iclass 20, count 2 2006.246.07:53:58.41#ibcon#wrote, iclass 20, count 2 2006.246.07:53:58.41#ibcon#about to read 3, iclass 20, count 2 2006.246.07:53:58.44#ibcon#read 3, iclass 20, count 2 2006.246.07:53:58.44#ibcon#about to read 4, iclass 20, count 2 2006.246.07:53:58.44#ibcon#read 4, iclass 20, count 2 2006.246.07:53:58.44#ibcon#about to read 5, iclass 20, count 2 2006.246.07:53:58.44#ibcon#read 5, iclass 20, count 2 2006.246.07:53:58.44#ibcon#about to read 6, iclass 20, count 2 2006.246.07:53:58.44#ibcon#read 6, iclass 20, count 2 2006.246.07:53:58.44#ibcon#end of sib2, iclass 20, count 2 2006.246.07:53:58.44#ibcon#*after write, iclass 20, count 2 2006.246.07:53:58.44#ibcon#*before return 0, iclass 20, count 2 2006.246.07:53:58.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:53:58.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:53:58.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.07:53:58.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:53:58.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:53:58.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:53:58.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:53:58.56#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:53:58.56#ibcon#first serial, iclass 20, count 0 2006.246.07:53:58.56#ibcon#enter sib2, iclass 20, count 0 2006.246.07:53:58.56#ibcon#flushed, iclass 20, count 0 2006.246.07:53:58.56#ibcon#about to write, iclass 20, count 0 2006.246.07:53:58.56#ibcon#wrote, iclass 20, count 0 2006.246.07:53:58.56#ibcon#about to read 3, iclass 20, count 0 2006.246.07:53:58.58#ibcon#read 3, iclass 20, count 0 2006.246.07:53:58.58#ibcon#about to read 4, iclass 20, count 0 2006.246.07:53:58.58#ibcon#read 4, iclass 20, count 0 2006.246.07:53:58.58#ibcon#about to read 5, iclass 20, count 0 2006.246.07:53:58.58#ibcon#read 5, iclass 20, count 0 2006.246.07:53:58.58#ibcon#about to read 6, iclass 20, count 0 2006.246.07:53:58.58#ibcon#read 6, iclass 20, count 0 2006.246.07:53:58.58#ibcon#end of sib2, iclass 20, count 0 2006.246.07:53:58.58#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:53:58.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:53:58.58#ibcon#[25=USB\r\n] 2006.246.07:53:58.58#ibcon#*before write, iclass 20, count 0 2006.246.07:53:58.58#ibcon#enter sib2, iclass 20, count 0 2006.246.07:53:58.58#ibcon#flushed, iclass 20, count 0 2006.246.07:53:58.58#ibcon#about to write, iclass 20, count 0 2006.246.07:53:58.58#ibcon#wrote, iclass 20, count 0 2006.246.07:53:58.58#ibcon#about to read 3, iclass 20, count 0 2006.246.07:53:58.61#ibcon#read 3, iclass 20, count 0 2006.246.07:53:58.61#ibcon#about to read 4, iclass 20, count 0 2006.246.07:53:58.61#ibcon#read 4, iclass 20, count 0 2006.246.07:53:58.61#ibcon#about to read 5, iclass 20, count 0 2006.246.07:53:58.61#ibcon#read 5, iclass 20, count 0 2006.246.07:53:58.61#ibcon#about to read 6, iclass 20, count 0 2006.246.07:53:58.61#ibcon#read 6, iclass 20, count 0 2006.246.07:53:58.61#ibcon#end of sib2, iclass 20, count 0 2006.246.07:53:58.61#ibcon#*after write, iclass 20, count 0 2006.246.07:53:58.61#ibcon#*before return 0, iclass 20, count 0 2006.246.07:53:58.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:53:58.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:53:58.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:53:58.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:53:58.61$vc4f8/valo=3,672.99 2006.246.07:53:58.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:53:58.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:53:58.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:58.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:53:58.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:53:58.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:53:58.61#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:53:58.61#ibcon#first serial, iclass 22, count 0 2006.246.07:53:58.61#ibcon#enter sib2, iclass 22, count 0 2006.246.07:53:58.61#ibcon#flushed, iclass 22, count 0 2006.246.07:53:58.61#ibcon#about to write, iclass 22, count 0 2006.246.07:53:58.61#ibcon#wrote, iclass 22, count 0 2006.246.07:53:58.61#ibcon#about to read 3, iclass 22, count 0 2006.246.07:53:58.63#ibcon#read 3, iclass 22, count 0 2006.246.07:53:58.63#ibcon#about to read 4, iclass 22, count 0 2006.246.07:53:58.63#ibcon#read 4, iclass 22, count 0 2006.246.07:53:58.63#ibcon#about to read 5, iclass 22, count 0 2006.246.07:53:58.63#ibcon#read 5, iclass 22, count 0 2006.246.07:53:58.63#ibcon#about to read 6, iclass 22, count 0 2006.246.07:53:58.63#ibcon#read 6, iclass 22, count 0 2006.246.07:53:58.63#ibcon#end of sib2, iclass 22, count 0 2006.246.07:53:58.63#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:53:58.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:53:58.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:53:58.63#ibcon#*before write, iclass 22, count 0 2006.246.07:53:58.63#ibcon#enter sib2, iclass 22, count 0 2006.246.07:53:58.63#ibcon#flushed, iclass 22, count 0 2006.246.07:53:58.63#ibcon#about to write, iclass 22, count 0 2006.246.07:53:58.63#ibcon#wrote, iclass 22, count 0 2006.246.07:53:58.63#ibcon#about to read 3, iclass 22, count 0 2006.246.07:53:58.67#ibcon#read 3, iclass 22, count 0 2006.246.07:53:58.67#ibcon#about to read 4, iclass 22, count 0 2006.246.07:53:58.67#ibcon#read 4, iclass 22, count 0 2006.246.07:53:58.67#ibcon#about to read 5, iclass 22, count 0 2006.246.07:53:58.67#ibcon#read 5, iclass 22, count 0 2006.246.07:53:58.67#ibcon#about to read 6, iclass 22, count 0 2006.246.07:53:58.67#ibcon#read 6, iclass 22, count 0 2006.246.07:53:58.67#ibcon#end of sib2, iclass 22, count 0 2006.246.07:53:58.67#ibcon#*after write, iclass 22, count 0 2006.246.07:53:58.67#ibcon#*before return 0, iclass 22, count 0 2006.246.07:53:58.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:53:58.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:53:58.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:53:58.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:53:58.67$vc4f8/va=3,6 2006.246.07:53:58.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.07:53:58.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.07:53:58.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:53:58.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:53:58.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:53:58.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:53:58.74#ibcon#enter wrdev, iclass 24, count 2 2006.246.07:53:58.74#ibcon#first serial, iclass 24, count 2 2006.246.07:53:58.74#ibcon#enter sib2, iclass 24, count 2 2006.246.07:53:58.74#ibcon#flushed, iclass 24, count 2 2006.246.07:53:58.74#ibcon#about to write, iclass 24, count 2 2006.246.07:53:58.74#ibcon#wrote, iclass 24, count 2 2006.246.07:53:58.74#ibcon#about to read 3, iclass 24, count 2 2006.246.07:53:58.75#ibcon#read 3, iclass 24, count 2 2006.246.07:53:58.75#ibcon#about to read 4, iclass 24, count 2 2006.246.07:53:58.75#ibcon#read 4, iclass 24, count 2 2006.246.07:53:58.75#ibcon#about to read 5, iclass 24, count 2 2006.246.07:53:58.75#ibcon#read 5, iclass 24, count 2 2006.246.07:53:58.75#ibcon#about to read 6, iclass 24, count 2 2006.246.07:53:58.75#ibcon#read 6, iclass 24, count 2 2006.246.07:53:58.75#ibcon#end of sib2, iclass 24, count 2 2006.246.07:53:58.75#ibcon#*mode == 0, iclass 24, count 2 2006.246.07:53:58.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.07:53:58.75#ibcon#[25=AT03-06\r\n] 2006.246.07:53:58.75#ibcon#*before write, iclass 24, count 2 2006.246.07:53:58.75#ibcon#enter sib2, iclass 24, count 2 2006.246.07:53:58.75#ibcon#flushed, iclass 24, count 2 2006.246.07:53:58.75#ibcon#about to write, iclass 24, count 2 2006.246.07:53:58.75#ibcon#wrote, iclass 24, count 2 2006.246.07:53:58.75#ibcon#about to read 3, iclass 24, count 2 2006.246.07:53:58.78#ibcon#read 3, iclass 24, count 2 2006.246.07:53:58.78#ibcon#about to read 4, iclass 24, count 2 2006.246.07:53:58.78#ibcon#read 4, iclass 24, count 2 2006.246.07:53:58.78#ibcon#about to read 5, iclass 24, count 2 2006.246.07:53:58.78#ibcon#read 5, iclass 24, count 2 2006.246.07:53:58.78#ibcon#about to read 6, iclass 24, count 2 2006.246.07:53:58.78#ibcon#read 6, iclass 24, count 2 2006.246.07:53:58.78#ibcon#end of sib2, iclass 24, count 2 2006.246.07:53:58.78#ibcon#*after write, iclass 24, count 2 2006.246.07:53:58.78#ibcon#*before return 0, iclass 24, count 2 2006.246.07:53:58.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:53:58.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:53:58.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.07:53:58.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:53:58.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:53:58.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:53:58.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:53:58.90#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:53:58.90#ibcon#first serial, iclass 24, count 0 2006.246.07:53:58.90#ibcon#enter sib2, iclass 24, count 0 2006.246.07:53:58.90#ibcon#flushed, iclass 24, count 0 2006.246.07:53:58.90#ibcon#about to write, iclass 24, count 0 2006.246.07:53:58.90#ibcon#wrote, iclass 24, count 0 2006.246.07:53:58.90#ibcon#about to read 3, iclass 24, count 0 2006.246.07:53:58.92#ibcon#read 3, iclass 24, count 0 2006.246.07:53:58.92#ibcon#about to read 4, iclass 24, count 0 2006.246.07:53:58.92#ibcon#read 4, iclass 24, count 0 2006.246.07:53:58.92#ibcon#about to read 5, iclass 24, count 0 2006.246.07:53:58.92#ibcon#read 5, iclass 24, count 0 2006.246.07:53:58.92#ibcon#about to read 6, iclass 24, count 0 2006.246.07:53:58.92#ibcon#read 6, iclass 24, count 0 2006.246.07:53:58.92#ibcon#end of sib2, iclass 24, count 0 2006.246.07:53:58.92#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:53:58.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:53:58.92#ibcon#[25=USB\r\n] 2006.246.07:53:58.92#ibcon#*before write, iclass 24, count 0 2006.246.07:53:58.92#ibcon#enter sib2, iclass 24, count 0 2006.246.07:53:58.92#ibcon#flushed, iclass 24, count 0 2006.246.07:53:58.92#ibcon#about to write, iclass 24, count 0 2006.246.07:53:58.92#ibcon#wrote, iclass 24, count 0 2006.246.07:53:58.92#ibcon#about to read 3, iclass 24, count 0 2006.246.07:53:58.95#ibcon#read 3, iclass 24, count 0 2006.246.07:53:58.95#ibcon#about to read 4, iclass 24, count 0 2006.246.07:53:58.95#ibcon#read 4, iclass 24, count 0 2006.246.07:53:58.95#ibcon#about to read 5, iclass 24, count 0 2006.246.07:53:58.95#ibcon#read 5, iclass 24, count 0 2006.246.07:53:58.95#ibcon#about to read 6, iclass 24, count 0 2006.246.07:53:58.95#ibcon#read 6, iclass 24, count 0 2006.246.07:53:58.95#ibcon#end of sib2, iclass 24, count 0 2006.246.07:53:58.95#ibcon#*after write, iclass 24, count 0 2006.246.07:53:58.95#ibcon#*before return 0, iclass 24, count 0 2006.246.07:53:58.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:53:58.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:53:58.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:53:58.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:53:58.95$vc4f8/valo=4,832.99 2006.246.07:53:58.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:53:58.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:53:58.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:58.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:53:58.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:53:58.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:53:58.95#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:53:58.95#ibcon#first serial, iclass 26, count 0 2006.246.07:53:58.95#ibcon#enter sib2, iclass 26, count 0 2006.246.07:53:58.95#ibcon#flushed, iclass 26, count 0 2006.246.07:53:58.95#ibcon#about to write, iclass 26, count 0 2006.246.07:53:58.95#ibcon#wrote, iclass 26, count 0 2006.246.07:53:58.95#ibcon#about to read 3, iclass 26, count 0 2006.246.07:53:58.97#ibcon#read 3, iclass 26, count 0 2006.246.07:53:58.97#ibcon#about to read 4, iclass 26, count 0 2006.246.07:53:58.97#ibcon#read 4, iclass 26, count 0 2006.246.07:53:58.97#ibcon#about to read 5, iclass 26, count 0 2006.246.07:53:58.97#ibcon#read 5, iclass 26, count 0 2006.246.07:53:58.97#ibcon#about to read 6, iclass 26, count 0 2006.246.07:53:58.97#ibcon#read 6, iclass 26, count 0 2006.246.07:53:58.97#ibcon#end of sib2, iclass 26, count 0 2006.246.07:53:58.97#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:53:58.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:53:58.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:53:58.97#ibcon#*before write, iclass 26, count 0 2006.246.07:53:58.97#ibcon#enter sib2, iclass 26, count 0 2006.246.07:53:58.97#ibcon#flushed, iclass 26, count 0 2006.246.07:53:58.97#ibcon#about to write, iclass 26, count 0 2006.246.07:53:58.97#ibcon#wrote, iclass 26, count 0 2006.246.07:53:58.97#ibcon#about to read 3, iclass 26, count 0 2006.246.07:53:59.01#ibcon#read 3, iclass 26, count 0 2006.246.07:53:59.01#ibcon#about to read 4, iclass 26, count 0 2006.246.07:53:59.01#ibcon#read 4, iclass 26, count 0 2006.246.07:53:59.01#ibcon#about to read 5, iclass 26, count 0 2006.246.07:53:59.01#ibcon#read 5, iclass 26, count 0 2006.246.07:53:59.01#ibcon#about to read 6, iclass 26, count 0 2006.246.07:53:59.01#ibcon#read 6, iclass 26, count 0 2006.246.07:53:59.01#ibcon#end of sib2, iclass 26, count 0 2006.246.07:53:59.01#ibcon#*after write, iclass 26, count 0 2006.246.07:53:59.01#ibcon#*before return 0, iclass 26, count 0 2006.246.07:53:59.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:53:59.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:53:59.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:53:59.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:53:59.01$vc4f8/va=4,7 2006.246.07:53:59.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:53:59.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:53:59.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:53:59.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:53:59.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:53:59.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:53:59.07#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:53:59.07#ibcon#first serial, iclass 28, count 2 2006.246.07:53:59.07#ibcon#enter sib2, iclass 28, count 2 2006.246.07:53:59.07#ibcon#flushed, iclass 28, count 2 2006.246.07:53:59.07#ibcon#about to write, iclass 28, count 2 2006.246.07:53:59.07#ibcon#wrote, iclass 28, count 2 2006.246.07:53:59.07#ibcon#about to read 3, iclass 28, count 2 2006.246.07:53:59.09#ibcon#read 3, iclass 28, count 2 2006.246.07:53:59.09#ibcon#about to read 4, iclass 28, count 2 2006.246.07:53:59.09#ibcon#read 4, iclass 28, count 2 2006.246.07:53:59.09#ibcon#about to read 5, iclass 28, count 2 2006.246.07:53:59.09#ibcon#read 5, iclass 28, count 2 2006.246.07:53:59.09#ibcon#about to read 6, iclass 28, count 2 2006.246.07:53:59.09#ibcon#read 6, iclass 28, count 2 2006.246.07:53:59.09#ibcon#end of sib2, iclass 28, count 2 2006.246.07:53:59.09#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:53:59.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:53:59.09#ibcon#[25=AT04-07\r\n] 2006.246.07:53:59.09#ibcon#*before write, iclass 28, count 2 2006.246.07:53:59.09#ibcon#enter sib2, iclass 28, count 2 2006.246.07:53:59.09#ibcon#flushed, iclass 28, count 2 2006.246.07:53:59.09#ibcon#about to write, iclass 28, count 2 2006.246.07:53:59.09#ibcon#wrote, iclass 28, count 2 2006.246.07:53:59.09#ibcon#about to read 3, iclass 28, count 2 2006.246.07:53:59.12#ibcon#read 3, iclass 28, count 2 2006.246.07:53:59.12#ibcon#about to read 4, iclass 28, count 2 2006.246.07:53:59.12#ibcon#read 4, iclass 28, count 2 2006.246.07:53:59.12#ibcon#about to read 5, iclass 28, count 2 2006.246.07:53:59.12#ibcon#read 5, iclass 28, count 2 2006.246.07:53:59.12#ibcon#about to read 6, iclass 28, count 2 2006.246.07:53:59.12#ibcon#read 6, iclass 28, count 2 2006.246.07:53:59.12#ibcon#end of sib2, iclass 28, count 2 2006.246.07:53:59.12#ibcon#*after write, iclass 28, count 2 2006.246.07:53:59.12#ibcon#*before return 0, iclass 28, count 2 2006.246.07:53:59.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:53:59.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:53:59.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:53:59.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:53:59.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:53:59.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:53:59.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:53:59.24#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:53:59.24#ibcon#first serial, iclass 28, count 0 2006.246.07:53:59.24#ibcon#enter sib2, iclass 28, count 0 2006.246.07:53:59.24#ibcon#flushed, iclass 28, count 0 2006.246.07:53:59.24#ibcon#about to write, iclass 28, count 0 2006.246.07:53:59.24#ibcon#wrote, iclass 28, count 0 2006.246.07:53:59.24#ibcon#about to read 3, iclass 28, count 0 2006.246.07:53:59.26#ibcon#read 3, iclass 28, count 0 2006.246.07:53:59.26#ibcon#about to read 4, iclass 28, count 0 2006.246.07:53:59.26#ibcon#read 4, iclass 28, count 0 2006.246.07:53:59.26#ibcon#about to read 5, iclass 28, count 0 2006.246.07:53:59.26#ibcon#read 5, iclass 28, count 0 2006.246.07:53:59.26#ibcon#about to read 6, iclass 28, count 0 2006.246.07:53:59.26#ibcon#read 6, iclass 28, count 0 2006.246.07:53:59.26#ibcon#end of sib2, iclass 28, count 0 2006.246.07:53:59.26#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:53:59.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:53:59.26#ibcon#[25=USB\r\n] 2006.246.07:53:59.26#ibcon#*before write, iclass 28, count 0 2006.246.07:53:59.26#ibcon#enter sib2, iclass 28, count 0 2006.246.07:53:59.26#ibcon#flushed, iclass 28, count 0 2006.246.07:53:59.26#ibcon#about to write, iclass 28, count 0 2006.246.07:53:59.26#ibcon#wrote, iclass 28, count 0 2006.246.07:53:59.26#ibcon#about to read 3, iclass 28, count 0 2006.246.07:53:59.29#ibcon#read 3, iclass 28, count 0 2006.246.07:53:59.29#ibcon#about to read 4, iclass 28, count 0 2006.246.07:53:59.29#ibcon#read 4, iclass 28, count 0 2006.246.07:53:59.29#ibcon#about to read 5, iclass 28, count 0 2006.246.07:53:59.29#ibcon#read 5, iclass 28, count 0 2006.246.07:53:59.29#ibcon#about to read 6, iclass 28, count 0 2006.246.07:53:59.29#ibcon#read 6, iclass 28, count 0 2006.246.07:53:59.29#ibcon#end of sib2, iclass 28, count 0 2006.246.07:53:59.29#ibcon#*after write, iclass 28, count 0 2006.246.07:53:59.29#ibcon#*before return 0, iclass 28, count 0 2006.246.07:53:59.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:53:59.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:53:59.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:53:59.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:53:59.29$vc4f8/valo=5,652.99 2006.246.07:53:59.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:53:59.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:53:59.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:59.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:53:59.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:53:59.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:53:59.29#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:53:59.29#ibcon#first serial, iclass 30, count 0 2006.246.07:53:59.29#ibcon#enter sib2, iclass 30, count 0 2006.246.07:53:59.29#ibcon#flushed, iclass 30, count 0 2006.246.07:53:59.29#ibcon#about to write, iclass 30, count 0 2006.246.07:53:59.29#ibcon#wrote, iclass 30, count 0 2006.246.07:53:59.29#ibcon#about to read 3, iclass 30, count 0 2006.246.07:53:59.31#ibcon#read 3, iclass 30, count 0 2006.246.07:53:59.31#ibcon#about to read 4, iclass 30, count 0 2006.246.07:53:59.31#ibcon#read 4, iclass 30, count 0 2006.246.07:53:59.31#ibcon#about to read 5, iclass 30, count 0 2006.246.07:53:59.31#ibcon#read 5, iclass 30, count 0 2006.246.07:53:59.31#ibcon#about to read 6, iclass 30, count 0 2006.246.07:53:59.31#ibcon#read 6, iclass 30, count 0 2006.246.07:53:59.31#ibcon#end of sib2, iclass 30, count 0 2006.246.07:53:59.31#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:53:59.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:53:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:53:59.31#ibcon#*before write, iclass 30, count 0 2006.246.07:53:59.31#ibcon#enter sib2, iclass 30, count 0 2006.246.07:53:59.31#ibcon#flushed, iclass 30, count 0 2006.246.07:53:59.31#ibcon#about to write, iclass 30, count 0 2006.246.07:53:59.31#ibcon#wrote, iclass 30, count 0 2006.246.07:53:59.31#ibcon#about to read 3, iclass 30, count 0 2006.246.07:53:59.35#ibcon#read 3, iclass 30, count 0 2006.246.07:53:59.35#ibcon#about to read 4, iclass 30, count 0 2006.246.07:53:59.35#ibcon#read 4, iclass 30, count 0 2006.246.07:53:59.35#ibcon#about to read 5, iclass 30, count 0 2006.246.07:53:59.35#ibcon#read 5, iclass 30, count 0 2006.246.07:53:59.35#ibcon#about to read 6, iclass 30, count 0 2006.246.07:53:59.35#ibcon#read 6, iclass 30, count 0 2006.246.07:53:59.35#ibcon#end of sib2, iclass 30, count 0 2006.246.07:53:59.35#ibcon#*after write, iclass 30, count 0 2006.246.07:53:59.35#ibcon#*before return 0, iclass 30, count 0 2006.246.07:53:59.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:53:59.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:53:59.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:53:59.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:53:59.35$vc4f8/va=5,7 2006.246.07:53:59.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:53:59.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:53:59.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:53:59.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:53:59.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:53:59.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:53:59.41#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:53:59.41#ibcon#first serial, iclass 32, count 2 2006.246.07:53:59.41#ibcon#enter sib2, iclass 32, count 2 2006.246.07:53:59.41#ibcon#flushed, iclass 32, count 2 2006.246.07:53:59.41#ibcon#about to write, iclass 32, count 2 2006.246.07:53:59.41#ibcon#wrote, iclass 32, count 2 2006.246.07:53:59.41#ibcon#about to read 3, iclass 32, count 2 2006.246.07:53:59.43#ibcon#read 3, iclass 32, count 2 2006.246.07:53:59.43#ibcon#about to read 4, iclass 32, count 2 2006.246.07:53:59.43#ibcon#read 4, iclass 32, count 2 2006.246.07:53:59.43#ibcon#about to read 5, iclass 32, count 2 2006.246.07:53:59.43#ibcon#read 5, iclass 32, count 2 2006.246.07:53:59.43#ibcon#about to read 6, iclass 32, count 2 2006.246.07:53:59.43#ibcon#read 6, iclass 32, count 2 2006.246.07:53:59.43#ibcon#end of sib2, iclass 32, count 2 2006.246.07:53:59.43#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:53:59.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:53:59.43#ibcon#[25=AT05-07\r\n] 2006.246.07:53:59.43#ibcon#*before write, iclass 32, count 2 2006.246.07:53:59.43#ibcon#enter sib2, iclass 32, count 2 2006.246.07:53:59.43#ibcon#flushed, iclass 32, count 2 2006.246.07:53:59.43#ibcon#about to write, iclass 32, count 2 2006.246.07:53:59.43#ibcon#wrote, iclass 32, count 2 2006.246.07:53:59.43#ibcon#about to read 3, iclass 32, count 2 2006.246.07:53:59.46#ibcon#read 3, iclass 32, count 2 2006.246.07:53:59.46#ibcon#about to read 4, iclass 32, count 2 2006.246.07:53:59.46#ibcon#read 4, iclass 32, count 2 2006.246.07:53:59.46#ibcon#about to read 5, iclass 32, count 2 2006.246.07:53:59.46#ibcon#read 5, iclass 32, count 2 2006.246.07:53:59.46#ibcon#about to read 6, iclass 32, count 2 2006.246.07:53:59.46#ibcon#read 6, iclass 32, count 2 2006.246.07:53:59.46#ibcon#end of sib2, iclass 32, count 2 2006.246.07:53:59.46#ibcon#*after write, iclass 32, count 2 2006.246.07:53:59.46#ibcon#*before return 0, iclass 32, count 2 2006.246.07:53:59.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:53:59.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:53:59.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:53:59.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:53:59.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:53:59.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:53:59.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:53:59.58#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:53:59.58#ibcon#first serial, iclass 32, count 0 2006.246.07:53:59.58#ibcon#enter sib2, iclass 32, count 0 2006.246.07:53:59.58#ibcon#flushed, iclass 32, count 0 2006.246.07:53:59.58#ibcon#about to write, iclass 32, count 0 2006.246.07:53:59.58#ibcon#wrote, iclass 32, count 0 2006.246.07:53:59.58#ibcon#about to read 3, iclass 32, count 0 2006.246.07:53:59.60#ibcon#read 3, iclass 32, count 0 2006.246.07:53:59.60#ibcon#about to read 4, iclass 32, count 0 2006.246.07:53:59.60#ibcon#read 4, iclass 32, count 0 2006.246.07:53:59.60#ibcon#about to read 5, iclass 32, count 0 2006.246.07:53:59.60#ibcon#read 5, iclass 32, count 0 2006.246.07:53:59.60#ibcon#about to read 6, iclass 32, count 0 2006.246.07:53:59.60#ibcon#read 6, iclass 32, count 0 2006.246.07:53:59.60#ibcon#end of sib2, iclass 32, count 0 2006.246.07:53:59.60#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:53:59.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:53:59.60#ibcon#[25=USB\r\n] 2006.246.07:53:59.60#ibcon#*before write, iclass 32, count 0 2006.246.07:53:59.60#ibcon#enter sib2, iclass 32, count 0 2006.246.07:53:59.60#ibcon#flushed, iclass 32, count 0 2006.246.07:53:59.60#ibcon#about to write, iclass 32, count 0 2006.246.07:53:59.60#ibcon#wrote, iclass 32, count 0 2006.246.07:53:59.60#ibcon#about to read 3, iclass 32, count 0 2006.246.07:53:59.63#ibcon#read 3, iclass 32, count 0 2006.246.07:53:59.63#ibcon#about to read 4, iclass 32, count 0 2006.246.07:53:59.63#ibcon#read 4, iclass 32, count 0 2006.246.07:53:59.63#ibcon#about to read 5, iclass 32, count 0 2006.246.07:53:59.63#ibcon#read 5, iclass 32, count 0 2006.246.07:53:59.63#ibcon#about to read 6, iclass 32, count 0 2006.246.07:53:59.63#ibcon#read 6, iclass 32, count 0 2006.246.07:53:59.63#ibcon#end of sib2, iclass 32, count 0 2006.246.07:53:59.63#ibcon#*after write, iclass 32, count 0 2006.246.07:53:59.63#ibcon#*before return 0, iclass 32, count 0 2006.246.07:53:59.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:53:59.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:53:59.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:53:59.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:53:59.63$vc4f8/valo=6,772.99 2006.246.07:53:59.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:53:59.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:53:59.63#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:59.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:53:59.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:53:59.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:53:59.63#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:53:59.63#ibcon#first serial, iclass 34, count 0 2006.246.07:53:59.63#ibcon#enter sib2, iclass 34, count 0 2006.246.07:53:59.63#ibcon#flushed, iclass 34, count 0 2006.246.07:53:59.63#ibcon#about to write, iclass 34, count 0 2006.246.07:53:59.63#ibcon#wrote, iclass 34, count 0 2006.246.07:53:59.63#ibcon#about to read 3, iclass 34, count 0 2006.246.07:53:59.65#ibcon#read 3, iclass 34, count 0 2006.246.07:53:59.65#ibcon#about to read 4, iclass 34, count 0 2006.246.07:53:59.65#ibcon#read 4, iclass 34, count 0 2006.246.07:53:59.65#ibcon#about to read 5, iclass 34, count 0 2006.246.07:53:59.65#ibcon#read 5, iclass 34, count 0 2006.246.07:53:59.65#ibcon#about to read 6, iclass 34, count 0 2006.246.07:53:59.65#ibcon#read 6, iclass 34, count 0 2006.246.07:53:59.65#ibcon#end of sib2, iclass 34, count 0 2006.246.07:53:59.65#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:53:59.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:53:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:53:59.65#ibcon#*before write, iclass 34, count 0 2006.246.07:53:59.65#ibcon#enter sib2, iclass 34, count 0 2006.246.07:53:59.65#ibcon#flushed, iclass 34, count 0 2006.246.07:53:59.65#ibcon#about to write, iclass 34, count 0 2006.246.07:53:59.65#ibcon#wrote, iclass 34, count 0 2006.246.07:53:59.65#ibcon#about to read 3, iclass 34, count 0 2006.246.07:53:59.69#ibcon#read 3, iclass 34, count 0 2006.246.07:53:59.69#ibcon#about to read 4, iclass 34, count 0 2006.246.07:53:59.69#ibcon#read 4, iclass 34, count 0 2006.246.07:53:59.69#ibcon#about to read 5, iclass 34, count 0 2006.246.07:53:59.69#ibcon#read 5, iclass 34, count 0 2006.246.07:53:59.69#ibcon#about to read 6, iclass 34, count 0 2006.246.07:53:59.69#ibcon#read 6, iclass 34, count 0 2006.246.07:53:59.69#ibcon#end of sib2, iclass 34, count 0 2006.246.07:53:59.69#ibcon#*after write, iclass 34, count 0 2006.246.07:53:59.69#ibcon#*before return 0, iclass 34, count 0 2006.246.07:53:59.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:53:59.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:53:59.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:53:59.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:53:59.69$vc4f8/va=6,7 2006.246.07:53:59.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:53:59.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:53:59.69#ibcon#ireg 11 cls_cnt 2 2006.246.07:53:59.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:53:59.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:53:59.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:53:59.75#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:53:59.75#ibcon#first serial, iclass 36, count 2 2006.246.07:53:59.75#ibcon#enter sib2, iclass 36, count 2 2006.246.07:53:59.75#ibcon#flushed, iclass 36, count 2 2006.246.07:53:59.75#ibcon#about to write, iclass 36, count 2 2006.246.07:53:59.75#ibcon#wrote, iclass 36, count 2 2006.246.07:53:59.75#ibcon#about to read 3, iclass 36, count 2 2006.246.07:53:59.77#ibcon#read 3, iclass 36, count 2 2006.246.07:53:59.77#ibcon#about to read 4, iclass 36, count 2 2006.246.07:53:59.77#ibcon#read 4, iclass 36, count 2 2006.246.07:53:59.77#ibcon#about to read 5, iclass 36, count 2 2006.246.07:53:59.77#ibcon#read 5, iclass 36, count 2 2006.246.07:53:59.77#ibcon#about to read 6, iclass 36, count 2 2006.246.07:53:59.77#ibcon#read 6, iclass 36, count 2 2006.246.07:53:59.77#ibcon#end of sib2, iclass 36, count 2 2006.246.07:53:59.77#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:53:59.77#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:53:59.77#ibcon#[25=AT06-07\r\n] 2006.246.07:53:59.77#ibcon#*before write, iclass 36, count 2 2006.246.07:53:59.77#ibcon#enter sib2, iclass 36, count 2 2006.246.07:53:59.77#ibcon#flushed, iclass 36, count 2 2006.246.07:53:59.77#ibcon#about to write, iclass 36, count 2 2006.246.07:53:59.77#ibcon#wrote, iclass 36, count 2 2006.246.07:53:59.77#ibcon#about to read 3, iclass 36, count 2 2006.246.07:53:59.80#ibcon#read 3, iclass 36, count 2 2006.246.07:53:59.80#ibcon#about to read 4, iclass 36, count 2 2006.246.07:53:59.80#ibcon#read 4, iclass 36, count 2 2006.246.07:53:59.80#ibcon#about to read 5, iclass 36, count 2 2006.246.07:53:59.80#ibcon#read 5, iclass 36, count 2 2006.246.07:53:59.80#ibcon#about to read 6, iclass 36, count 2 2006.246.07:53:59.80#ibcon#read 6, iclass 36, count 2 2006.246.07:53:59.80#ibcon#end of sib2, iclass 36, count 2 2006.246.07:53:59.80#ibcon#*after write, iclass 36, count 2 2006.246.07:53:59.80#ibcon#*before return 0, iclass 36, count 2 2006.246.07:53:59.80#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:53:59.80#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:53:59.80#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:53:59.80#ibcon#ireg 7 cls_cnt 0 2006.246.07:53:59.80#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:53:59.92#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:53:59.92#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:53:59.92#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:53:59.92#ibcon#first serial, iclass 36, count 0 2006.246.07:53:59.92#ibcon#enter sib2, iclass 36, count 0 2006.246.07:53:59.92#ibcon#flushed, iclass 36, count 0 2006.246.07:53:59.92#ibcon#about to write, iclass 36, count 0 2006.246.07:53:59.92#ibcon#wrote, iclass 36, count 0 2006.246.07:53:59.92#ibcon#about to read 3, iclass 36, count 0 2006.246.07:53:59.94#ibcon#read 3, iclass 36, count 0 2006.246.07:53:59.94#ibcon#about to read 4, iclass 36, count 0 2006.246.07:53:59.94#ibcon#read 4, iclass 36, count 0 2006.246.07:53:59.94#ibcon#about to read 5, iclass 36, count 0 2006.246.07:53:59.94#ibcon#read 5, iclass 36, count 0 2006.246.07:53:59.94#ibcon#about to read 6, iclass 36, count 0 2006.246.07:53:59.94#ibcon#read 6, iclass 36, count 0 2006.246.07:53:59.94#ibcon#end of sib2, iclass 36, count 0 2006.246.07:53:59.94#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:53:59.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:53:59.94#ibcon#[25=USB\r\n] 2006.246.07:53:59.94#ibcon#*before write, iclass 36, count 0 2006.246.07:53:59.94#ibcon#enter sib2, iclass 36, count 0 2006.246.07:53:59.94#ibcon#flushed, iclass 36, count 0 2006.246.07:53:59.94#ibcon#about to write, iclass 36, count 0 2006.246.07:53:59.94#ibcon#wrote, iclass 36, count 0 2006.246.07:53:59.94#ibcon#about to read 3, iclass 36, count 0 2006.246.07:53:59.97#ibcon#read 3, iclass 36, count 0 2006.246.07:53:59.97#ibcon#about to read 4, iclass 36, count 0 2006.246.07:53:59.97#ibcon#read 4, iclass 36, count 0 2006.246.07:53:59.97#ibcon#about to read 5, iclass 36, count 0 2006.246.07:53:59.97#ibcon#read 5, iclass 36, count 0 2006.246.07:53:59.97#ibcon#about to read 6, iclass 36, count 0 2006.246.07:53:59.97#ibcon#read 6, iclass 36, count 0 2006.246.07:53:59.97#ibcon#end of sib2, iclass 36, count 0 2006.246.07:53:59.97#ibcon#*after write, iclass 36, count 0 2006.246.07:53:59.97#ibcon#*before return 0, iclass 36, count 0 2006.246.07:53:59.97#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:53:59.97#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:53:59.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:53:59.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:53:59.97$vc4f8/valo=7,832.99 2006.246.07:53:59.97#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:53:59.97#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:53:59.97#ibcon#ireg 17 cls_cnt 0 2006.246.07:53:59.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:53:59.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:53:59.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:53:59.97#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:53:59.97#ibcon#first serial, iclass 38, count 0 2006.246.07:53:59.97#ibcon#enter sib2, iclass 38, count 0 2006.246.07:53:59.97#ibcon#flushed, iclass 38, count 0 2006.246.07:53:59.97#ibcon#about to write, iclass 38, count 0 2006.246.07:53:59.97#ibcon#wrote, iclass 38, count 0 2006.246.07:53:59.97#ibcon#about to read 3, iclass 38, count 0 2006.246.07:53:59.99#ibcon#read 3, iclass 38, count 0 2006.246.07:53:59.99#ibcon#about to read 4, iclass 38, count 0 2006.246.07:53:59.99#ibcon#read 4, iclass 38, count 0 2006.246.07:53:59.99#ibcon#about to read 5, iclass 38, count 0 2006.246.07:53:59.99#ibcon#read 5, iclass 38, count 0 2006.246.07:53:59.99#ibcon#about to read 6, iclass 38, count 0 2006.246.07:53:59.99#ibcon#read 6, iclass 38, count 0 2006.246.07:53:59.99#ibcon#end of sib2, iclass 38, count 0 2006.246.07:53:59.99#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:53:59.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:53:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:53:59.99#ibcon#*before write, iclass 38, count 0 2006.246.07:53:59.99#ibcon#enter sib2, iclass 38, count 0 2006.246.07:53:59.99#ibcon#flushed, iclass 38, count 0 2006.246.07:53:59.99#ibcon#about to write, iclass 38, count 0 2006.246.07:53:59.99#ibcon#wrote, iclass 38, count 0 2006.246.07:53:59.99#ibcon#about to read 3, iclass 38, count 0 2006.246.07:54:00.03#ibcon#read 3, iclass 38, count 0 2006.246.07:54:00.03#ibcon#about to read 4, iclass 38, count 0 2006.246.07:54:00.03#ibcon#read 4, iclass 38, count 0 2006.246.07:54:00.03#ibcon#about to read 5, iclass 38, count 0 2006.246.07:54:00.03#ibcon#read 5, iclass 38, count 0 2006.246.07:54:00.03#ibcon#about to read 6, iclass 38, count 0 2006.246.07:54:00.03#ibcon#read 6, iclass 38, count 0 2006.246.07:54:00.03#ibcon#end of sib2, iclass 38, count 0 2006.246.07:54:00.03#ibcon#*after write, iclass 38, count 0 2006.246.07:54:00.03#ibcon#*before return 0, iclass 38, count 0 2006.246.07:54:00.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:00.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:00.03#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:54:00.03#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:54:00.03$vc4f8/va=7,7 2006.246.07:54:00.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.07:54:00.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.07:54:00.03#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:00.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:54:00.04#abcon#<5=/04 3.2 6.9 26.70 731005.7\r\n> 2006.246.07:54:00.06#abcon#{5=INTERFACE CLEAR} 2006.246.07:54:00.09#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:54:00.09#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:54:00.09#ibcon#enter wrdev, iclass 3, count 2 2006.246.07:54:00.09#ibcon#first serial, iclass 3, count 2 2006.246.07:54:00.09#ibcon#enter sib2, iclass 3, count 2 2006.246.07:54:00.09#ibcon#flushed, iclass 3, count 2 2006.246.07:54:00.09#ibcon#about to write, iclass 3, count 2 2006.246.07:54:00.09#ibcon#wrote, iclass 3, count 2 2006.246.07:54:00.09#ibcon#about to read 3, iclass 3, count 2 2006.246.07:54:00.11#ibcon#read 3, iclass 3, count 2 2006.246.07:54:00.11#ibcon#about to read 4, iclass 3, count 2 2006.246.07:54:00.11#ibcon#read 4, iclass 3, count 2 2006.246.07:54:00.11#ibcon#about to read 5, iclass 3, count 2 2006.246.07:54:00.11#ibcon#read 5, iclass 3, count 2 2006.246.07:54:00.11#ibcon#about to read 6, iclass 3, count 2 2006.246.07:54:00.11#ibcon#read 6, iclass 3, count 2 2006.246.07:54:00.11#ibcon#end of sib2, iclass 3, count 2 2006.246.07:54:00.11#ibcon#*mode == 0, iclass 3, count 2 2006.246.07:54:00.11#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.07:54:00.11#ibcon#[25=AT07-07\r\n] 2006.246.07:54:00.11#ibcon#*before write, iclass 3, count 2 2006.246.07:54:00.11#ibcon#enter sib2, iclass 3, count 2 2006.246.07:54:00.11#ibcon#flushed, iclass 3, count 2 2006.246.07:54:00.11#ibcon#about to write, iclass 3, count 2 2006.246.07:54:00.11#ibcon#wrote, iclass 3, count 2 2006.246.07:54:00.11#ibcon#about to read 3, iclass 3, count 2 2006.246.07:54:00.12#abcon#[5=S1D000X0/0*\r\n] 2006.246.07:54:00.14#ibcon#read 3, iclass 3, count 2 2006.246.07:54:00.14#ibcon#about to read 4, iclass 3, count 2 2006.246.07:54:00.14#ibcon#read 4, iclass 3, count 2 2006.246.07:54:00.14#ibcon#about to read 5, iclass 3, count 2 2006.246.07:54:00.14#ibcon#read 5, iclass 3, count 2 2006.246.07:54:00.14#ibcon#about to read 6, iclass 3, count 2 2006.246.07:54:00.14#ibcon#read 6, iclass 3, count 2 2006.246.07:54:00.14#ibcon#end of sib2, iclass 3, count 2 2006.246.07:54:00.14#ibcon#*after write, iclass 3, count 2 2006.246.07:54:00.14#ibcon#*before return 0, iclass 3, count 2 2006.246.07:54:00.14#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:54:00.14#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:54:00.14#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.07:54:00.14#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:00.14#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:54:00.26#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:54:00.26#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:54:00.26#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:54:00.26#ibcon#first serial, iclass 3, count 0 2006.246.07:54:00.26#ibcon#enter sib2, iclass 3, count 0 2006.246.07:54:00.26#ibcon#flushed, iclass 3, count 0 2006.246.07:54:00.26#ibcon#about to write, iclass 3, count 0 2006.246.07:54:00.26#ibcon#wrote, iclass 3, count 0 2006.246.07:54:00.26#ibcon#about to read 3, iclass 3, count 0 2006.246.07:54:00.28#ibcon#read 3, iclass 3, count 0 2006.246.07:54:00.28#ibcon#about to read 4, iclass 3, count 0 2006.246.07:54:00.28#ibcon#read 4, iclass 3, count 0 2006.246.07:54:00.28#ibcon#about to read 5, iclass 3, count 0 2006.246.07:54:00.28#ibcon#read 5, iclass 3, count 0 2006.246.07:54:00.28#ibcon#about to read 6, iclass 3, count 0 2006.246.07:54:00.28#ibcon#read 6, iclass 3, count 0 2006.246.07:54:00.28#ibcon#end of sib2, iclass 3, count 0 2006.246.07:54:00.28#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:54:00.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:54:00.28#ibcon#[25=USB\r\n] 2006.246.07:54:00.28#ibcon#*before write, iclass 3, count 0 2006.246.07:54:00.28#ibcon#enter sib2, iclass 3, count 0 2006.246.07:54:00.28#ibcon#flushed, iclass 3, count 0 2006.246.07:54:00.28#ibcon#about to write, iclass 3, count 0 2006.246.07:54:00.28#ibcon#wrote, iclass 3, count 0 2006.246.07:54:00.28#ibcon#about to read 3, iclass 3, count 0 2006.246.07:54:00.31#ibcon#read 3, iclass 3, count 0 2006.246.07:54:00.31#ibcon#about to read 4, iclass 3, count 0 2006.246.07:54:00.31#ibcon#read 4, iclass 3, count 0 2006.246.07:54:00.31#ibcon#about to read 5, iclass 3, count 0 2006.246.07:54:00.31#ibcon#read 5, iclass 3, count 0 2006.246.07:54:00.31#ibcon#about to read 6, iclass 3, count 0 2006.246.07:54:00.31#ibcon#read 6, iclass 3, count 0 2006.246.07:54:00.31#ibcon#end of sib2, iclass 3, count 0 2006.246.07:54:00.31#ibcon#*after write, iclass 3, count 0 2006.246.07:54:00.31#ibcon#*before return 0, iclass 3, count 0 2006.246.07:54:00.31#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:54:00.31#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:54:00.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:54:00.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:54:00.31$vc4f8/valo=8,852.99 2006.246.07:54:00.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.07:54:00.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.07:54:00.31#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:00.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:54:00.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:54:00.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:54:00.31#ibcon#enter wrdev, iclass 10, count 0 2006.246.07:54:00.31#ibcon#first serial, iclass 10, count 0 2006.246.07:54:00.31#ibcon#enter sib2, iclass 10, count 0 2006.246.07:54:00.31#ibcon#flushed, iclass 10, count 0 2006.246.07:54:00.31#ibcon#about to write, iclass 10, count 0 2006.246.07:54:00.31#ibcon#wrote, iclass 10, count 0 2006.246.07:54:00.31#ibcon#about to read 3, iclass 10, count 0 2006.246.07:54:00.33#ibcon#read 3, iclass 10, count 0 2006.246.07:54:00.33#ibcon#about to read 4, iclass 10, count 0 2006.246.07:54:00.33#ibcon#read 4, iclass 10, count 0 2006.246.07:54:00.33#ibcon#about to read 5, iclass 10, count 0 2006.246.07:54:00.33#ibcon#read 5, iclass 10, count 0 2006.246.07:54:00.33#ibcon#about to read 6, iclass 10, count 0 2006.246.07:54:00.33#ibcon#read 6, iclass 10, count 0 2006.246.07:54:00.33#ibcon#end of sib2, iclass 10, count 0 2006.246.07:54:00.33#ibcon#*mode == 0, iclass 10, count 0 2006.246.07:54:00.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.07:54:00.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:54:00.33#ibcon#*before write, iclass 10, count 0 2006.246.07:54:00.33#ibcon#enter sib2, iclass 10, count 0 2006.246.07:54:00.33#ibcon#flushed, iclass 10, count 0 2006.246.07:54:00.33#ibcon#about to write, iclass 10, count 0 2006.246.07:54:00.33#ibcon#wrote, iclass 10, count 0 2006.246.07:54:00.33#ibcon#about to read 3, iclass 10, count 0 2006.246.07:54:00.37#ibcon#read 3, iclass 10, count 0 2006.246.07:54:00.37#ibcon#about to read 4, iclass 10, count 0 2006.246.07:54:00.37#ibcon#read 4, iclass 10, count 0 2006.246.07:54:00.37#ibcon#about to read 5, iclass 10, count 0 2006.246.07:54:00.37#ibcon#read 5, iclass 10, count 0 2006.246.07:54:00.37#ibcon#about to read 6, iclass 10, count 0 2006.246.07:54:00.37#ibcon#read 6, iclass 10, count 0 2006.246.07:54:00.37#ibcon#end of sib2, iclass 10, count 0 2006.246.07:54:00.37#ibcon#*after write, iclass 10, count 0 2006.246.07:54:00.37#ibcon#*before return 0, iclass 10, count 0 2006.246.07:54:00.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:54:00.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.07:54:00.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.07:54:00.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.07:54:00.37$vc4f8/va=8,8 2006.246.07:54:00.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.07:54:00.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.07:54:00.37#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:00.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:54:00.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:54:00.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:54:00.44#ibcon#enter wrdev, iclass 12, count 2 2006.246.07:54:00.44#ibcon#first serial, iclass 12, count 2 2006.246.07:54:00.44#ibcon#enter sib2, iclass 12, count 2 2006.246.07:54:00.44#ibcon#flushed, iclass 12, count 2 2006.246.07:54:00.44#ibcon#about to write, iclass 12, count 2 2006.246.07:54:00.44#ibcon#wrote, iclass 12, count 2 2006.246.07:54:00.44#ibcon#about to read 3, iclass 12, count 2 2006.246.07:54:00.45#ibcon#read 3, iclass 12, count 2 2006.246.07:54:00.45#ibcon#about to read 4, iclass 12, count 2 2006.246.07:54:00.45#ibcon#read 4, iclass 12, count 2 2006.246.07:54:00.45#ibcon#about to read 5, iclass 12, count 2 2006.246.07:54:00.45#ibcon#read 5, iclass 12, count 2 2006.246.07:54:00.45#ibcon#about to read 6, iclass 12, count 2 2006.246.07:54:00.45#ibcon#read 6, iclass 12, count 2 2006.246.07:54:00.45#ibcon#end of sib2, iclass 12, count 2 2006.246.07:54:00.45#ibcon#*mode == 0, iclass 12, count 2 2006.246.07:54:00.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.07:54:00.45#ibcon#[25=AT08-08\r\n] 2006.246.07:54:00.45#ibcon#*before write, iclass 12, count 2 2006.246.07:54:00.45#ibcon#enter sib2, iclass 12, count 2 2006.246.07:54:00.45#ibcon#flushed, iclass 12, count 2 2006.246.07:54:00.45#ibcon#about to write, iclass 12, count 2 2006.246.07:54:00.45#ibcon#wrote, iclass 12, count 2 2006.246.07:54:00.45#ibcon#about to read 3, iclass 12, count 2 2006.246.07:54:00.48#ibcon#read 3, iclass 12, count 2 2006.246.07:54:00.48#ibcon#about to read 4, iclass 12, count 2 2006.246.07:54:00.48#ibcon#read 4, iclass 12, count 2 2006.246.07:54:00.48#ibcon#about to read 5, iclass 12, count 2 2006.246.07:54:00.48#ibcon#read 5, iclass 12, count 2 2006.246.07:54:00.48#ibcon#about to read 6, iclass 12, count 2 2006.246.07:54:00.48#ibcon#read 6, iclass 12, count 2 2006.246.07:54:00.48#ibcon#end of sib2, iclass 12, count 2 2006.246.07:54:00.48#ibcon#*after write, iclass 12, count 2 2006.246.07:54:00.48#ibcon#*before return 0, iclass 12, count 2 2006.246.07:54:00.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:54:00.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.07:54:00.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.07:54:00.48#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:00.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:54:00.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:54:00.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:54:00.60#ibcon#enter wrdev, iclass 12, count 0 2006.246.07:54:00.60#ibcon#first serial, iclass 12, count 0 2006.246.07:54:00.60#ibcon#enter sib2, iclass 12, count 0 2006.246.07:54:00.60#ibcon#flushed, iclass 12, count 0 2006.246.07:54:00.60#ibcon#about to write, iclass 12, count 0 2006.246.07:54:00.60#ibcon#wrote, iclass 12, count 0 2006.246.07:54:00.60#ibcon#about to read 3, iclass 12, count 0 2006.246.07:54:00.62#ibcon#read 3, iclass 12, count 0 2006.246.07:54:00.62#ibcon#about to read 4, iclass 12, count 0 2006.246.07:54:00.62#ibcon#read 4, iclass 12, count 0 2006.246.07:54:00.62#ibcon#about to read 5, iclass 12, count 0 2006.246.07:54:00.62#ibcon#read 5, iclass 12, count 0 2006.246.07:54:00.62#ibcon#about to read 6, iclass 12, count 0 2006.246.07:54:00.62#ibcon#read 6, iclass 12, count 0 2006.246.07:54:00.62#ibcon#end of sib2, iclass 12, count 0 2006.246.07:54:00.62#ibcon#*mode == 0, iclass 12, count 0 2006.246.07:54:00.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.07:54:00.62#ibcon#[25=USB\r\n] 2006.246.07:54:00.62#ibcon#*before write, iclass 12, count 0 2006.246.07:54:00.62#ibcon#enter sib2, iclass 12, count 0 2006.246.07:54:00.62#ibcon#flushed, iclass 12, count 0 2006.246.07:54:00.62#ibcon#about to write, iclass 12, count 0 2006.246.07:54:00.62#ibcon#wrote, iclass 12, count 0 2006.246.07:54:00.62#ibcon#about to read 3, iclass 12, count 0 2006.246.07:54:00.65#ibcon#read 3, iclass 12, count 0 2006.246.07:54:00.65#ibcon#about to read 4, iclass 12, count 0 2006.246.07:54:00.65#ibcon#read 4, iclass 12, count 0 2006.246.07:54:00.65#ibcon#about to read 5, iclass 12, count 0 2006.246.07:54:00.65#ibcon#read 5, iclass 12, count 0 2006.246.07:54:00.65#ibcon#about to read 6, iclass 12, count 0 2006.246.07:54:00.65#ibcon#read 6, iclass 12, count 0 2006.246.07:54:00.65#ibcon#end of sib2, iclass 12, count 0 2006.246.07:54:00.65#ibcon#*after write, iclass 12, count 0 2006.246.07:54:00.65#ibcon#*before return 0, iclass 12, count 0 2006.246.07:54:00.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:54:00.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.07:54:00.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.07:54:00.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.07:54:00.65$vc4f8/vblo=1,632.99 2006.246.07:54:00.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.07:54:00.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.07:54:00.65#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:00.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:54:00.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:54:00.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:54:00.65#ibcon#enter wrdev, iclass 14, count 0 2006.246.07:54:00.65#ibcon#first serial, iclass 14, count 0 2006.246.07:54:00.65#ibcon#enter sib2, iclass 14, count 0 2006.246.07:54:00.65#ibcon#flushed, iclass 14, count 0 2006.246.07:54:00.65#ibcon#about to write, iclass 14, count 0 2006.246.07:54:00.65#ibcon#wrote, iclass 14, count 0 2006.246.07:54:00.65#ibcon#about to read 3, iclass 14, count 0 2006.246.07:54:00.67#ibcon#read 3, iclass 14, count 0 2006.246.07:54:00.67#ibcon#about to read 4, iclass 14, count 0 2006.246.07:54:00.67#ibcon#read 4, iclass 14, count 0 2006.246.07:54:00.67#ibcon#about to read 5, iclass 14, count 0 2006.246.07:54:00.67#ibcon#read 5, iclass 14, count 0 2006.246.07:54:00.67#ibcon#about to read 6, iclass 14, count 0 2006.246.07:54:00.67#ibcon#read 6, iclass 14, count 0 2006.246.07:54:00.67#ibcon#end of sib2, iclass 14, count 0 2006.246.07:54:00.67#ibcon#*mode == 0, iclass 14, count 0 2006.246.07:54:00.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.07:54:00.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:54:00.67#ibcon#*before write, iclass 14, count 0 2006.246.07:54:00.67#ibcon#enter sib2, iclass 14, count 0 2006.246.07:54:00.67#ibcon#flushed, iclass 14, count 0 2006.246.07:54:00.67#ibcon#about to write, iclass 14, count 0 2006.246.07:54:00.67#ibcon#wrote, iclass 14, count 0 2006.246.07:54:00.67#ibcon#about to read 3, iclass 14, count 0 2006.246.07:54:00.71#ibcon#read 3, iclass 14, count 0 2006.246.07:54:00.71#ibcon#about to read 4, iclass 14, count 0 2006.246.07:54:00.71#ibcon#read 4, iclass 14, count 0 2006.246.07:54:00.71#ibcon#about to read 5, iclass 14, count 0 2006.246.07:54:00.71#ibcon#read 5, iclass 14, count 0 2006.246.07:54:00.71#ibcon#about to read 6, iclass 14, count 0 2006.246.07:54:00.71#ibcon#read 6, iclass 14, count 0 2006.246.07:54:00.71#ibcon#end of sib2, iclass 14, count 0 2006.246.07:54:00.71#ibcon#*after write, iclass 14, count 0 2006.246.07:54:00.71#ibcon#*before return 0, iclass 14, count 0 2006.246.07:54:00.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:54:00.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.07:54:00.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.07:54:00.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.07:54:00.71$vc4f8/vb=1,4 2006.246.07:54:00.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.07:54:00.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.07:54:00.71#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:00.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:54:00.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:54:00.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:54:00.71#ibcon#enter wrdev, iclass 16, count 2 2006.246.07:54:00.71#ibcon#first serial, iclass 16, count 2 2006.246.07:54:00.71#ibcon#enter sib2, iclass 16, count 2 2006.246.07:54:00.71#ibcon#flushed, iclass 16, count 2 2006.246.07:54:00.71#ibcon#about to write, iclass 16, count 2 2006.246.07:54:00.71#ibcon#wrote, iclass 16, count 2 2006.246.07:54:00.71#ibcon#about to read 3, iclass 16, count 2 2006.246.07:54:00.73#ibcon#read 3, iclass 16, count 2 2006.246.07:54:00.73#ibcon#about to read 4, iclass 16, count 2 2006.246.07:54:00.73#ibcon#read 4, iclass 16, count 2 2006.246.07:54:00.73#ibcon#about to read 5, iclass 16, count 2 2006.246.07:54:00.73#ibcon#read 5, iclass 16, count 2 2006.246.07:54:00.73#ibcon#about to read 6, iclass 16, count 2 2006.246.07:54:00.73#ibcon#read 6, iclass 16, count 2 2006.246.07:54:00.73#ibcon#end of sib2, iclass 16, count 2 2006.246.07:54:00.73#ibcon#*mode == 0, iclass 16, count 2 2006.246.07:54:00.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.07:54:00.73#ibcon#[27=AT01-04\r\n] 2006.246.07:54:00.73#ibcon#*before write, iclass 16, count 2 2006.246.07:54:00.73#ibcon#enter sib2, iclass 16, count 2 2006.246.07:54:00.73#ibcon#flushed, iclass 16, count 2 2006.246.07:54:00.73#ibcon#about to write, iclass 16, count 2 2006.246.07:54:00.73#ibcon#wrote, iclass 16, count 2 2006.246.07:54:00.73#ibcon#about to read 3, iclass 16, count 2 2006.246.07:54:00.76#ibcon#read 3, iclass 16, count 2 2006.246.07:54:00.76#ibcon#about to read 4, iclass 16, count 2 2006.246.07:54:00.76#ibcon#read 4, iclass 16, count 2 2006.246.07:54:00.76#ibcon#about to read 5, iclass 16, count 2 2006.246.07:54:00.76#ibcon#read 5, iclass 16, count 2 2006.246.07:54:00.76#ibcon#about to read 6, iclass 16, count 2 2006.246.07:54:00.76#ibcon#read 6, iclass 16, count 2 2006.246.07:54:00.76#ibcon#end of sib2, iclass 16, count 2 2006.246.07:54:00.76#ibcon#*after write, iclass 16, count 2 2006.246.07:54:00.76#ibcon#*before return 0, iclass 16, count 2 2006.246.07:54:00.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:54:00.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.07:54:00.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.07:54:00.76#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:00.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:54:00.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:54:00.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:54:00.88#ibcon#enter wrdev, iclass 16, count 0 2006.246.07:54:00.88#ibcon#first serial, iclass 16, count 0 2006.246.07:54:00.88#ibcon#enter sib2, iclass 16, count 0 2006.246.07:54:00.88#ibcon#flushed, iclass 16, count 0 2006.246.07:54:00.88#ibcon#about to write, iclass 16, count 0 2006.246.07:54:00.88#ibcon#wrote, iclass 16, count 0 2006.246.07:54:00.88#ibcon#about to read 3, iclass 16, count 0 2006.246.07:54:00.90#ibcon#read 3, iclass 16, count 0 2006.246.07:54:00.90#ibcon#about to read 4, iclass 16, count 0 2006.246.07:54:00.90#ibcon#read 4, iclass 16, count 0 2006.246.07:54:00.90#ibcon#about to read 5, iclass 16, count 0 2006.246.07:54:00.90#ibcon#read 5, iclass 16, count 0 2006.246.07:54:00.90#ibcon#about to read 6, iclass 16, count 0 2006.246.07:54:00.90#ibcon#read 6, iclass 16, count 0 2006.246.07:54:00.90#ibcon#end of sib2, iclass 16, count 0 2006.246.07:54:00.90#ibcon#*mode == 0, iclass 16, count 0 2006.246.07:54:00.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.07:54:00.90#ibcon#[27=USB\r\n] 2006.246.07:54:00.90#ibcon#*before write, iclass 16, count 0 2006.246.07:54:00.90#ibcon#enter sib2, iclass 16, count 0 2006.246.07:54:00.90#ibcon#flushed, iclass 16, count 0 2006.246.07:54:00.90#ibcon#about to write, iclass 16, count 0 2006.246.07:54:00.90#ibcon#wrote, iclass 16, count 0 2006.246.07:54:00.90#ibcon#about to read 3, iclass 16, count 0 2006.246.07:54:00.93#ibcon#read 3, iclass 16, count 0 2006.246.07:54:00.93#ibcon#about to read 4, iclass 16, count 0 2006.246.07:54:00.93#ibcon#read 4, iclass 16, count 0 2006.246.07:54:00.93#ibcon#about to read 5, iclass 16, count 0 2006.246.07:54:00.93#ibcon#read 5, iclass 16, count 0 2006.246.07:54:00.93#ibcon#about to read 6, iclass 16, count 0 2006.246.07:54:00.93#ibcon#read 6, iclass 16, count 0 2006.246.07:54:00.93#ibcon#end of sib2, iclass 16, count 0 2006.246.07:54:00.93#ibcon#*after write, iclass 16, count 0 2006.246.07:54:00.93#ibcon#*before return 0, iclass 16, count 0 2006.246.07:54:00.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:54:00.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.07:54:00.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.07:54:00.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.07:54:00.93$vc4f8/vblo=2,640.99 2006.246.07:54:00.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.07:54:00.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.07:54:00.93#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:00.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:54:00.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:54:00.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:54:00.93#ibcon#enter wrdev, iclass 18, count 0 2006.246.07:54:00.93#ibcon#first serial, iclass 18, count 0 2006.246.07:54:00.93#ibcon#enter sib2, iclass 18, count 0 2006.246.07:54:00.93#ibcon#flushed, iclass 18, count 0 2006.246.07:54:00.93#ibcon#about to write, iclass 18, count 0 2006.246.07:54:00.93#ibcon#wrote, iclass 18, count 0 2006.246.07:54:00.93#ibcon#about to read 3, iclass 18, count 0 2006.246.07:54:00.95#ibcon#read 3, iclass 18, count 0 2006.246.07:54:00.95#ibcon#about to read 4, iclass 18, count 0 2006.246.07:54:00.95#ibcon#read 4, iclass 18, count 0 2006.246.07:54:00.95#ibcon#about to read 5, iclass 18, count 0 2006.246.07:54:00.95#ibcon#read 5, iclass 18, count 0 2006.246.07:54:00.95#ibcon#about to read 6, iclass 18, count 0 2006.246.07:54:00.95#ibcon#read 6, iclass 18, count 0 2006.246.07:54:00.95#ibcon#end of sib2, iclass 18, count 0 2006.246.07:54:00.95#ibcon#*mode == 0, iclass 18, count 0 2006.246.07:54:00.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.07:54:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:54:00.95#ibcon#*before write, iclass 18, count 0 2006.246.07:54:00.95#ibcon#enter sib2, iclass 18, count 0 2006.246.07:54:00.95#ibcon#flushed, iclass 18, count 0 2006.246.07:54:00.95#ibcon#about to write, iclass 18, count 0 2006.246.07:54:00.95#ibcon#wrote, iclass 18, count 0 2006.246.07:54:00.95#ibcon#about to read 3, iclass 18, count 0 2006.246.07:54:00.99#ibcon#read 3, iclass 18, count 0 2006.246.07:54:00.99#ibcon#about to read 4, iclass 18, count 0 2006.246.07:54:00.99#ibcon#read 4, iclass 18, count 0 2006.246.07:54:00.99#ibcon#about to read 5, iclass 18, count 0 2006.246.07:54:00.99#ibcon#read 5, iclass 18, count 0 2006.246.07:54:00.99#ibcon#about to read 6, iclass 18, count 0 2006.246.07:54:00.99#ibcon#read 6, iclass 18, count 0 2006.246.07:54:00.99#ibcon#end of sib2, iclass 18, count 0 2006.246.07:54:00.99#ibcon#*after write, iclass 18, count 0 2006.246.07:54:00.99#ibcon#*before return 0, iclass 18, count 0 2006.246.07:54:00.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:54:00.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.07:54:00.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.07:54:00.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.07:54:00.99$vc4f8/vb=2,4 2006.246.07:54:00.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.07:54:00.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.07:54:00.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:00.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:54:01.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:54:01.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:54:01.05#ibcon#enter wrdev, iclass 20, count 2 2006.246.07:54:01.05#ibcon#first serial, iclass 20, count 2 2006.246.07:54:01.05#ibcon#enter sib2, iclass 20, count 2 2006.246.07:54:01.05#ibcon#flushed, iclass 20, count 2 2006.246.07:54:01.05#ibcon#about to write, iclass 20, count 2 2006.246.07:54:01.05#ibcon#wrote, iclass 20, count 2 2006.246.07:54:01.05#ibcon#about to read 3, iclass 20, count 2 2006.246.07:54:01.07#ibcon#read 3, iclass 20, count 2 2006.246.07:54:01.07#ibcon#about to read 4, iclass 20, count 2 2006.246.07:54:01.07#ibcon#read 4, iclass 20, count 2 2006.246.07:54:01.07#ibcon#about to read 5, iclass 20, count 2 2006.246.07:54:01.07#ibcon#read 5, iclass 20, count 2 2006.246.07:54:01.07#ibcon#about to read 6, iclass 20, count 2 2006.246.07:54:01.07#ibcon#read 6, iclass 20, count 2 2006.246.07:54:01.07#ibcon#end of sib2, iclass 20, count 2 2006.246.07:54:01.07#ibcon#*mode == 0, iclass 20, count 2 2006.246.07:54:01.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.07:54:01.07#ibcon#[27=AT02-04\r\n] 2006.246.07:54:01.07#ibcon#*before write, iclass 20, count 2 2006.246.07:54:01.07#ibcon#enter sib2, iclass 20, count 2 2006.246.07:54:01.07#ibcon#flushed, iclass 20, count 2 2006.246.07:54:01.07#ibcon#about to write, iclass 20, count 2 2006.246.07:54:01.07#ibcon#wrote, iclass 20, count 2 2006.246.07:54:01.07#ibcon#about to read 3, iclass 20, count 2 2006.246.07:54:01.10#ibcon#read 3, iclass 20, count 2 2006.246.07:54:01.10#ibcon#about to read 4, iclass 20, count 2 2006.246.07:54:01.10#ibcon#read 4, iclass 20, count 2 2006.246.07:54:01.10#ibcon#about to read 5, iclass 20, count 2 2006.246.07:54:01.10#ibcon#read 5, iclass 20, count 2 2006.246.07:54:01.10#ibcon#about to read 6, iclass 20, count 2 2006.246.07:54:01.10#ibcon#read 6, iclass 20, count 2 2006.246.07:54:01.10#ibcon#end of sib2, iclass 20, count 2 2006.246.07:54:01.10#ibcon#*after write, iclass 20, count 2 2006.246.07:54:01.10#ibcon#*before return 0, iclass 20, count 2 2006.246.07:54:01.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:54:01.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.07:54:01.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.07:54:01.10#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:01.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:54:01.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:54:01.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:54:01.22#ibcon#enter wrdev, iclass 20, count 0 2006.246.07:54:01.22#ibcon#first serial, iclass 20, count 0 2006.246.07:54:01.22#ibcon#enter sib2, iclass 20, count 0 2006.246.07:54:01.22#ibcon#flushed, iclass 20, count 0 2006.246.07:54:01.22#ibcon#about to write, iclass 20, count 0 2006.246.07:54:01.22#ibcon#wrote, iclass 20, count 0 2006.246.07:54:01.22#ibcon#about to read 3, iclass 20, count 0 2006.246.07:54:01.24#ibcon#read 3, iclass 20, count 0 2006.246.07:54:01.24#ibcon#about to read 4, iclass 20, count 0 2006.246.07:54:01.24#ibcon#read 4, iclass 20, count 0 2006.246.07:54:01.24#ibcon#about to read 5, iclass 20, count 0 2006.246.07:54:01.24#ibcon#read 5, iclass 20, count 0 2006.246.07:54:01.24#ibcon#about to read 6, iclass 20, count 0 2006.246.07:54:01.24#ibcon#read 6, iclass 20, count 0 2006.246.07:54:01.24#ibcon#end of sib2, iclass 20, count 0 2006.246.07:54:01.24#ibcon#*mode == 0, iclass 20, count 0 2006.246.07:54:01.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.07:54:01.24#ibcon#[27=USB\r\n] 2006.246.07:54:01.24#ibcon#*before write, iclass 20, count 0 2006.246.07:54:01.24#ibcon#enter sib2, iclass 20, count 0 2006.246.07:54:01.24#ibcon#flushed, iclass 20, count 0 2006.246.07:54:01.24#ibcon#about to write, iclass 20, count 0 2006.246.07:54:01.24#ibcon#wrote, iclass 20, count 0 2006.246.07:54:01.24#ibcon#about to read 3, iclass 20, count 0 2006.246.07:54:01.27#ibcon#read 3, iclass 20, count 0 2006.246.07:54:01.27#ibcon#about to read 4, iclass 20, count 0 2006.246.07:54:01.27#ibcon#read 4, iclass 20, count 0 2006.246.07:54:01.27#ibcon#about to read 5, iclass 20, count 0 2006.246.07:54:01.27#ibcon#read 5, iclass 20, count 0 2006.246.07:54:01.27#ibcon#about to read 6, iclass 20, count 0 2006.246.07:54:01.27#ibcon#read 6, iclass 20, count 0 2006.246.07:54:01.27#ibcon#end of sib2, iclass 20, count 0 2006.246.07:54:01.27#ibcon#*after write, iclass 20, count 0 2006.246.07:54:01.27#ibcon#*before return 0, iclass 20, count 0 2006.246.07:54:01.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:54:01.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.07:54:01.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.07:54:01.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.07:54:01.27$vc4f8/vblo=3,656.99 2006.246.07:54:01.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.07:54:01.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.07:54:01.27#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:01.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:54:01.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:54:01.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:54:01.27#ibcon#enter wrdev, iclass 22, count 0 2006.246.07:54:01.27#ibcon#first serial, iclass 22, count 0 2006.246.07:54:01.27#ibcon#enter sib2, iclass 22, count 0 2006.246.07:54:01.27#ibcon#flushed, iclass 22, count 0 2006.246.07:54:01.27#ibcon#about to write, iclass 22, count 0 2006.246.07:54:01.27#ibcon#wrote, iclass 22, count 0 2006.246.07:54:01.27#ibcon#about to read 3, iclass 22, count 0 2006.246.07:54:01.29#ibcon#read 3, iclass 22, count 0 2006.246.07:54:01.29#ibcon#about to read 4, iclass 22, count 0 2006.246.07:54:01.29#ibcon#read 4, iclass 22, count 0 2006.246.07:54:01.29#ibcon#about to read 5, iclass 22, count 0 2006.246.07:54:01.29#ibcon#read 5, iclass 22, count 0 2006.246.07:54:01.29#ibcon#about to read 6, iclass 22, count 0 2006.246.07:54:01.29#ibcon#read 6, iclass 22, count 0 2006.246.07:54:01.29#ibcon#end of sib2, iclass 22, count 0 2006.246.07:54:01.29#ibcon#*mode == 0, iclass 22, count 0 2006.246.07:54:01.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.07:54:01.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:54:01.29#ibcon#*before write, iclass 22, count 0 2006.246.07:54:01.29#ibcon#enter sib2, iclass 22, count 0 2006.246.07:54:01.29#ibcon#flushed, iclass 22, count 0 2006.246.07:54:01.29#ibcon#about to write, iclass 22, count 0 2006.246.07:54:01.29#ibcon#wrote, iclass 22, count 0 2006.246.07:54:01.29#ibcon#about to read 3, iclass 22, count 0 2006.246.07:54:01.33#ibcon#read 3, iclass 22, count 0 2006.246.07:54:01.33#ibcon#about to read 4, iclass 22, count 0 2006.246.07:54:01.33#ibcon#read 4, iclass 22, count 0 2006.246.07:54:01.33#ibcon#about to read 5, iclass 22, count 0 2006.246.07:54:01.33#ibcon#read 5, iclass 22, count 0 2006.246.07:54:01.33#ibcon#about to read 6, iclass 22, count 0 2006.246.07:54:01.33#ibcon#read 6, iclass 22, count 0 2006.246.07:54:01.33#ibcon#end of sib2, iclass 22, count 0 2006.246.07:54:01.33#ibcon#*after write, iclass 22, count 0 2006.246.07:54:01.33#ibcon#*before return 0, iclass 22, count 0 2006.246.07:54:01.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:54:01.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.07:54:01.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.07:54:01.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.07:54:01.33$vc4f8/vb=3,4 2006.246.07:54:01.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.07:54:01.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.07:54:01.33#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:01.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:54:01.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:54:01.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:54:01.39#ibcon#enter wrdev, iclass 24, count 2 2006.246.07:54:01.39#ibcon#first serial, iclass 24, count 2 2006.246.07:54:01.39#ibcon#enter sib2, iclass 24, count 2 2006.246.07:54:01.39#ibcon#flushed, iclass 24, count 2 2006.246.07:54:01.39#ibcon#about to write, iclass 24, count 2 2006.246.07:54:01.39#ibcon#wrote, iclass 24, count 2 2006.246.07:54:01.39#ibcon#about to read 3, iclass 24, count 2 2006.246.07:54:01.41#ibcon#read 3, iclass 24, count 2 2006.246.07:54:01.41#ibcon#about to read 4, iclass 24, count 2 2006.246.07:54:01.41#ibcon#read 4, iclass 24, count 2 2006.246.07:54:01.41#ibcon#about to read 5, iclass 24, count 2 2006.246.07:54:01.41#ibcon#read 5, iclass 24, count 2 2006.246.07:54:01.41#ibcon#about to read 6, iclass 24, count 2 2006.246.07:54:01.41#ibcon#read 6, iclass 24, count 2 2006.246.07:54:01.41#ibcon#end of sib2, iclass 24, count 2 2006.246.07:54:01.41#ibcon#*mode == 0, iclass 24, count 2 2006.246.07:54:01.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.07:54:01.41#ibcon#[27=AT03-04\r\n] 2006.246.07:54:01.41#ibcon#*before write, iclass 24, count 2 2006.246.07:54:01.41#ibcon#enter sib2, iclass 24, count 2 2006.246.07:54:01.41#ibcon#flushed, iclass 24, count 2 2006.246.07:54:01.41#ibcon#about to write, iclass 24, count 2 2006.246.07:54:01.41#ibcon#wrote, iclass 24, count 2 2006.246.07:54:01.41#ibcon#about to read 3, iclass 24, count 2 2006.246.07:54:01.44#ibcon#read 3, iclass 24, count 2 2006.246.07:54:01.44#ibcon#about to read 4, iclass 24, count 2 2006.246.07:54:01.44#ibcon#read 4, iclass 24, count 2 2006.246.07:54:01.44#ibcon#about to read 5, iclass 24, count 2 2006.246.07:54:01.44#ibcon#read 5, iclass 24, count 2 2006.246.07:54:01.44#ibcon#about to read 6, iclass 24, count 2 2006.246.07:54:01.44#ibcon#read 6, iclass 24, count 2 2006.246.07:54:01.44#ibcon#end of sib2, iclass 24, count 2 2006.246.07:54:01.44#ibcon#*after write, iclass 24, count 2 2006.246.07:54:01.44#ibcon#*before return 0, iclass 24, count 2 2006.246.07:54:01.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:54:01.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.07:54:01.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.07:54:01.44#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:01.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:54:01.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:54:01.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:54:01.56#ibcon#enter wrdev, iclass 24, count 0 2006.246.07:54:01.56#ibcon#first serial, iclass 24, count 0 2006.246.07:54:01.56#ibcon#enter sib2, iclass 24, count 0 2006.246.07:54:01.56#ibcon#flushed, iclass 24, count 0 2006.246.07:54:01.56#ibcon#about to write, iclass 24, count 0 2006.246.07:54:01.56#ibcon#wrote, iclass 24, count 0 2006.246.07:54:01.56#ibcon#about to read 3, iclass 24, count 0 2006.246.07:54:01.58#ibcon#read 3, iclass 24, count 0 2006.246.07:54:01.58#ibcon#about to read 4, iclass 24, count 0 2006.246.07:54:01.58#ibcon#read 4, iclass 24, count 0 2006.246.07:54:01.58#ibcon#about to read 5, iclass 24, count 0 2006.246.07:54:01.58#ibcon#read 5, iclass 24, count 0 2006.246.07:54:01.58#ibcon#about to read 6, iclass 24, count 0 2006.246.07:54:01.58#ibcon#read 6, iclass 24, count 0 2006.246.07:54:01.58#ibcon#end of sib2, iclass 24, count 0 2006.246.07:54:01.58#ibcon#*mode == 0, iclass 24, count 0 2006.246.07:54:01.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.07:54:01.58#ibcon#[27=USB\r\n] 2006.246.07:54:01.58#ibcon#*before write, iclass 24, count 0 2006.246.07:54:01.58#ibcon#enter sib2, iclass 24, count 0 2006.246.07:54:01.58#ibcon#flushed, iclass 24, count 0 2006.246.07:54:01.58#ibcon#about to write, iclass 24, count 0 2006.246.07:54:01.58#ibcon#wrote, iclass 24, count 0 2006.246.07:54:01.58#ibcon#about to read 3, iclass 24, count 0 2006.246.07:54:01.61#ibcon#read 3, iclass 24, count 0 2006.246.07:54:01.61#ibcon#about to read 4, iclass 24, count 0 2006.246.07:54:01.61#ibcon#read 4, iclass 24, count 0 2006.246.07:54:01.61#ibcon#about to read 5, iclass 24, count 0 2006.246.07:54:01.61#ibcon#read 5, iclass 24, count 0 2006.246.07:54:01.61#ibcon#about to read 6, iclass 24, count 0 2006.246.07:54:01.61#ibcon#read 6, iclass 24, count 0 2006.246.07:54:01.61#ibcon#end of sib2, iclass 24, count 0 2006.246.07:54:01.61#ibcon#*after write, iclass 24, count 0 2006.246.07:54:01.61#ibcon#*before return 0, iclass 24, count 0 2006.246.07:54:01.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:54:01.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.07:54:01.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.07:54:01.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.07:54:01.61$vc4f8/vblo=4,712.99 2006.246.07:54:01.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.07:54:01.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.07:54:01.61#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:01.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:54:01.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:54:01.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:54:01.61#ibcon#enter wrdev, iclass 26, count 0 2006.246.07:54:01.61#ibcon#first serial, iclass 26, count 0 2006.246.07:54:01.61#ibcon#enter sib2, iclass 26, count 0 2006.246.07:54:01.61#ibcon#flushed, iclass 26, count 0 2006.246.07:54:01.61#ibcon#about to write, iclass 26, count 0 2006.246.07:54:01.61#ibcon#wrote, iclass 26, count 0 2006.246.07:54:01.61#ibcon#about to read 3, iclass 26, count 0 2006.246.07:54:01.63#ibcon#read 3, iclass 26, count 0 2006.246.07:54:01.63#ibcon#about to read 4, iclass 26, count 0 2006.246.07:54:01.63#ibcon#read 4, iclass 26, count 0 2006.246.07:54:01.63#ibcon#about to read 5, iclass 26, count 0 2006.246.07:54:01.63#ibcon#read 5, iclass 26, count 0 2006.246.07:54:01.63#ibcon#about to read 6, iclass 26, count 0 2006.246.07:54:01.63#ibcon#read 6, iclass 26, count 0 2006.246.07:54:01.63#ibcon#end of sib2, iclass 26, count 0 2006.246.07:54:01.63#ibcon#*mode == 0, iclass 26, count 0 2006.246.07:54:01.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.07:54:01.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:54:01.63#ibcon#*before write, iclass 26, count 0 2006.246.07:54:01.63#ibcon#enter sib2, iclass 26, count 0 2006.246.07:54:01.63#ibcon#flushed, iclass 26, count 0 2006.246.07:54:01.63#ibcon#about to write, iclass 26, count 0 2006.246.07:54:01.63#ibcon#wrote, iclass 26, count 0 2006.246.07:54:01.63#ibcon#about to read 3, iclass 26, count 0 2006.246.07:54:01.67#ibcon#read 3, iclass 26, count 0 2006.246.07:54:01.67#ibcon#about to read 4, iclass 26, count 0 2006.246.07:54:01.67#ibcon#read 4, iclass 26, count 0 2006.246.07:54:01.67#ibcon#about to read 5, iclass 26, count 0 2006.246.07:54:01.67#ibcon#read 5, iclass 26, count 0 2006.246.07:54:01.67#ibcon#about to read 6, iclass 26, count 0 2006.246.07:54:01.67#ibcon#read 6, iclass 26, count 0 2006.246.07:54:01.67#ibcon#end of sib2, iclass 26, count 0 2006.246.07:54:01.67#ibcon#*after write, iclass 26, count 0 2006.246.07:54:01.67#ibcon#*before return 0, iclass 26, count 0 2006.246.07:54:01.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:54:01.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.07:54:01.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.07:54:01.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.07:54:01.67$vc4f8/vb=4,4 2006.246.07:54:01.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.07:54:01.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.07:54:01.67#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:01.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:54:01.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:54:01.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:54:01.73#ibcon#enter wrdev, iclass 28, count 2 2006.246.07:54:01.73#ibcon#first serial, iclass 28, count 2 2006.246.07:54:01.73#ibcon#enter sib2, iclass 28, count 2 2006.246.07:54:01.73#ibcon#flushed, iclass 28, count 2 2006.246.07:54:01.73#ibcon#about to write, iclass 28, count 2 2006.246.07:54:01.73#ibcon#wrote, iclass 28, count 2 2006.246.07:54:01.73#ibcon#about to read 3, iclass 28, count 2 2006.246.07:54:01.75#ibcon#read 3, iclass 28, count 2 2006.246.07:54:01.75#ibcon#about to read 4, iclass 28, count 2 2006.246.07:54:01.75#ibcon#read 4, iclass 28, count 2 2006.246.07:54:01.75#ibcon#about to read 5, iclass 28, count 2 2006.246.07:54:01.75#ibcon#read 5, iclass 28, count 2 2006.246.07:54:01.75#ibcon#about to read 6, iclass 28, count 2 2006.246.07:54:01.75#ibcon#read 6, iclass 28, count 2 2006.246.07:54:01.75#ibcon#end of sib2, iclass 28, count 2 2006.246.07:54:01.75#ibcon#*mode == 0, iclass 28, count 2 2006.246.07:54:01.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.07:54:01.75#ibcon#[27=AT04-04\r\n] 2006.246.07:54:01.75#ibcon#*before write, iclass 28, count 2 2006.246.07:54:01.75#ibcon#enter sib2, iclass 28, count 2 2006.246.07:54:01.75#ibcon#flushed, iclass 28, count 2 2006.246.07:54:01.75#ibcon#about to write, iclass 28, count 2 2006.246.07:54:01.75#ibcon#wrote, iclass 28, count 2 2006.246.07:54:01.75#ibcon#about to read 3, iclass 28, count 2 2006.246.07:54:01.78#ibcon#read 3, iclass 28, count 2 2006.246.07:54:01.78#ibcon#about to read 4, iclass 28, count 2 2006.246.07:54:01.78#ibcon#read 4, iclass 28, count 2 2006.246.07:54:01.78#ibcon#about to read 5, iclass 28, count 2 2006.246.07:54:01.78#ibcon#read 5, iclass 28, count 2 2006.246.07:54:01.78#ibcon#about to read 6, iclass 28, count 2 2006.246.07:54:01.78#ibcon#read 6, iclass 28, count 2 2006.246.07:54:01.78#ibcon#end of sib2, iclass 28, count 2 2006.246.07:54:01.78#ibcon#*after write, iclass 28, count 2 2006.246.07:54:01.78#ibcon#*before return 0, iclass 28, count 2 2006.246.07:54:01.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:54:01.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.07:54:01.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.07:54:01.78#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:01.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:54:01.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:54:01.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:54:01.90#ibcon#enter wrdev, iclass 28, count 0 2006.246.07:54:01.90#ibcon#first serial, iclass 28, count 0 2006.246.07:54:01.90#ibcon#enter sib2, iclass 28, count 0 2006.246.07:54:01.90#ibcon#flushed, iclass 28, count 0 2006.246.07:54:01.90#ibcon#about to write, iclass 28, count 0 2006.246.07:54:01.90#ibcon#wrote, iclass 28, count 0 2006.246.07:54:01.90#ibcon#about to read 3, iclass 28, count 0 2006.246.07:54:01.92#ibcon#read 3, iclass 28, count 0 2006.246.07:54:01.92#ibcon#about to read 4, iclass 28, count 0 2006.246.07:54:01.92#ibcon#read 4, iclass 28, count 0 2006.246.07:54:01.92#ibcon#about to read 5, iclass 28, count 0 2006.246.07:54:01.92#ibcon#read 5, iclass 28, count 0 2006.246.07:54:01.92#ibcon#about to read 6, iclass 28, count 0 2006.246.07:54:01.92#ibcon#read 6, iclass 28, count 0 2006.246.07:54:01.92#ibcon#end of sib2, iclass 28, count 0 2006.246.07:54:01.92#ibcon#*mode == 0, iclass 28, count 0 2006.246.07:54:01.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.07:54:01.92#ibcon#[27=USB\r\n] 2006.246.07:54:01.92#ibcon#*before write, iclass 28, count 0 2006.246.07:54:01.92#ibcon#enter sib2, iclass 28, count 0 2006.246.07:54:01.92#ibcon#flushed, iclass 28, count 0 2006.246.07:54:01.92#ibcon#about to write, iclass 28, count 0 2006.246.07:54:01.92#ibcon#wrote, iclass 28, count 0 2006.246.07:54:01.92#ibcon#about to read 3, iclass 28, count 0 2006.246.07:54:01.95#ibcon#read 3, iclass 28, count 0 2006.246.07:54:01.95#ibcon#about to read 4, iclass 28, count 0 2006.246.07:54:01.95#ibcon#read 4, iclass 28, count 0 2006.246.07:54:01.95#ibcon#about to read 5, iclass 28, count 0 2006.246.07:54:01.95#ibcon#read 5, iclass 28, count 0 2006.246.07:54:01.95#ibcon#about to read 6, iclass 28, count 0 2006.246.07:54:01.95#ibcon#read 6, iclass 28, count 0 2006.246.07:54:01.95#ibcon#end of sib2, iclass 28, count 0 2006.246.07:54:01.95#ibcon#*after write, iclass 28, count 0 2006.246.07:54:01.95#ibcon#*before return 0, iclass 28, count 0 2006.246.07:54:01.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:54:01.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.07:54:01.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.07:54:01.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.07:54:01.95$vc4f8/vblo=5,744.99 2006.246.07:54:01.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.07:54:01.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.07:54:01.95#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:01.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:54:01.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:54:01.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:54:01.95#ibcon#enter wrdev, iclass 30, count 0 2006.246.07:54:01.95#ibcon#first serial, iclass 30, count 0 2006.246.07:54:01.95#ibcon#enter sib2, iclass 30, count 0 2006.246.07:54:01.95#ibcon#flushed, iclass 30, count 0 2006.246.07:54:01.95#ibcon#about to write, iclass 30, count 0 2006.246.07:54:01.95#ibcon#wrote, iclass 30, count 0 2006.246.07:54:01.95#ibcon#about to read 3, iclass 30, count 0 2006.246.07:54:01.97#ibcon#read 3, iclass 30, count 0 2006.246.07:54:01.97#ibcon#about to read 4, iclass 30, count 0 2006.246.07:54:01.97#ibcon#read 4, iclass 30, count 0 2006.246.07:54:01.97#ibcon#about to read 5, iclass 30, count 0 2006.246.07:54:01.97#ibcon#read 5, iclass 30, count 0 2006.246.07:54:01.97#ibcon#about to read 6, iclass 30, count 0 2006.246.07:54:01.97#ibcon#read 6, iclass 30, count 0 2006.246.07:54:01.97#ibcon#end of sib2, iclass 30, count 0 2006.246.07:54:01.97#ibcon#*mode == 0, iclass 30, count 0 2006.246.07:54:01.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.07:54:01.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:54:01.97#ibcon#*before write, iclass 30, count 0 2006.246.07:54:01.97#ibcon#enter sib2, iclass 30, count 0 2006.246.07:54:01.97#ibcon#flushed, iclass 30, count 0 2006.246.07:54:01.97#ibcon#about to write, iclass 30, count 0 2006.246.07:54:01.97#ibcon#wrote, iclass 30, count 0 2006.246.07:54:01.97#ibcon#about to read 3, iclass 30, count 0 2006.246.07:54:02.01#ibcon#read 3, iclass 30, count 0 2006.246.07:54:02.01#ibcon#about to read 4, iclass 30, count 0 2006.246.07:54:02.01#ibcon#read 4, iclass 30, count 0 2006.246.07:54:02.01#ibcon#about to read 5, iclass 30, count 0 2006.246.07:54:02.01#ibcon#read 5, iclass 30, count 0 2006.246.07:54:02.01#ibcon#about to read 6, iclass 30, count 0 2006.246.07:54:02.01#ibcon#read 6, iclass 30, count 0 2006.246.07:54:02.01#ibcon#end of sib2, iclass 30, count 0 2006.246.07:54:02.01#ibcon#*after write, iclass 30, count 0 2006.246.07:54:02.01#ibcon#*before return 0, iclass 30, count 0 2006.246.07:54:02.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:54:02.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.07:54:02.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.07:54:02.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.07:54:02.01$vc4f8/vb=5,3 2006.246.07:54:02.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.07:54:02.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.07:54:02.01#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:02.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:54:02.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:54:02.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:54:02.08#ibcon#enter wrdev, iclass 32, count 2 2006.246.07:54:02.08#ibcon#first serial, iclass 32, count 2 2006.246.07:54:02.08#ibcon#enter sib2, iclass 32, count 2 2006.246.07:54:02.08#ibcon#flushed, iclass 32, count 2 2006.246.07:54:02.08#ibcon#about to write, iclass 32, count 2 2006.246.07:54:02.08#ibcon#wrote, iclass 32, count 2 2006.246.07:54:02.08#ibcon#about to read 3, iclass 32, count 2 2006.246.07:54:02.09#ibcon#read 3, iclass 32, count 2 2006.246.07:54:02.09#ibcon#about to read 4, iclass 32, count 2 2006.246.07:54:02.09#ibcon#read 4, iclass 32, count 2 2006.246.07:54:02.09#ibcon#about to read 5, iclass 32, count 2 2006.246.07:54:02.09#ibcon#read 5, iclass 32, count 2 2006.246.07:54:02.09#ibcon#about to read 6, iclass 32, count 2 2006.246.07:54:02.09#ibcon#read 6, iclass 32, count 2 2006.246.07:54:02.09#ibcon#end of sib2, iclass 32, count 2 2006.246.07:54:02.09#ibcon#*mode == 0, iclass 32, count 2 2006.246.07:54:02.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.07:54:02.09#ibcon#[27=AT05-03\r\n] 2006.246.07:54:02.09#ibcon#*before write, iclass 32, count 2 2006.246.07:54:02.09#ibcon#enter sib2, iclass 32, count 2 2006.246.07:54:02.09#ibcon#flushed, iclass 32, count 2 2006.246.07:54:02.09#ibcon#about to write, iclass 32, count 2 2006.246.07:54:02.09#ibcon#wrote, iclass 32, count 2 2006.246.07:54:02.09#ibcon#about to read 3, iclass 32, count 2 2006.246.07:54:02.12#ibcon#read 3, iclass 32, count 2 2006.246.07:54:02.12#ibcon#about to read 4, iclass 32, count 2 2006.246.07:54:02.12#ibcon#read 4, iclass 32, count 2 2006.246.07:54:02.12#ibcon#about to read 5, iclass 32, count 2 2006.246.07:54:02.12#ibcon#read 5, iclass 32, count 2 2006.246.07:54:02.12#ibcon#about to read 6, iclass 32, count 2 2006.246.07:54:02.12#ibcon#read 6, iclass 32, count 2 2006.246.07:54:02.12#ibcon#end of sib2, iclass 32, count 2 2006.246.07:54:02.12#ibcon#*after write, iclass 32, count 2 2006.246.07:54:02.12#ibcon#*before return 0, iclass 32, count 2 2006.246.07:54:02.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:54:02.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.07:54:02.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.07:54:02.12#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:02.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:54:02.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:54:02.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:54:02.24#ibcon#enter wrdev, iclass 32, count 0 2006.246.07:54:02.24#ibcon#first serial, iclass 32, count 0 2006.246.07:54:02.24#ibcon#enter sib2, iclass 32, count 0 2006.246.07:54:02.24#ibcon#flushed, iclass 32, count 0 2006.246.07:54:02.24#ibcon#about to write, iclass 32, count 0 2006.246.07:54:02.24#ibcon#wrote, iclass 32, count 0 2006.246.07:54:02.24#ibcon#about to read 3, iclass 32, count 0 2006.246.07:54:02.26#ibcon#read 3, iclass 32, count 0 2006.246.07:54:02.26#ibcon#about to read 4, iclass 32, count 0 2006.246.07:54:02.26#ibcon#read 4, iclass 32, count 0 2006.246.07:54:02.26#ibcon#about to read 5, iclass 32, count 0 2006.246.07:54:02.26#ibcon#read 5, iclass 32, count 0 2006.246.07:54:02.26#ibcon#about to read 6, iclass 32, count 0 2006.246.07:54:02.26#ibcon#read 6, iclass 32, count 0 2006.246.07:54:02.26#ibcon#end of sib2, iclass 32, count 0 2006.246.07:54:02.26#ibcon#*mode == 0, iclass 32, count 0 2006.246.07:54:02.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.07:54:02.26#ibcon#[27=USB\r\n] 2006.246.07:54:02.26#ibcon#*before write, iclass 32, count 0 2006.246.07:54:02.26#ibcon#enter sib2, iclass 32, count 0 2006.246.07:54:02.26#ibcon#flushed, iclass 32, count 0 2006.246.07:54:02.26#ibcon#about to write, iclass 32, count 0 2006.246.07:54:02.26#ibcon#wrote, iclass 32, count 0 2006.246.07:54:02.26#ibcon#about to read 3, iclass 32, count 0 2006.246.07:54:02.29#ibcon#read 3, iclass 32, count 0 2006.246.07:54:02.29#ibcon#about to read 4, iclass 32, count 0 2006.246.07:54:02.29#ibcon#read 4, iclass 32, count 0 2006.246.07:54:02.29#ibcon#about to read 5, iclass 32, count 0 2006.246.07:54:02.29#ibcon#read 5, iclass 32, count 0 2006.246.07:54:02.29#ibcon#about to read 6, iclass 32, count 0 2006.246.07:54:02.29#ibcon#read 6, iclass 32, count 0 2006.246.07:54:02.29#ibcon#end of sib2, iclass 32, count 0 2006.246.07:54:02.29#ibcon#*after write, iclass 32, count 0 2006.246.07:54:02.29#ibcon#*before return 0, iclass 32, count 0 2006.246.07:54:02.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:54:02.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.07:54:02.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.07:54:02.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.07:54:02.29$vc4f8/vblo=6,752.99 2006.246.07:54:02.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.07:54:02.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.07:54:02.29#ibcon#ireg 17 cls_cnt 0 2006.246.07:54:02.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:54:02.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:54:02.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:54:02.29#ibcon#enter wrdev, iclass 34, count 0 2006.246.07:54:02.29#ibcon#first serial, iclass 34, count 0 2006.246.07:54:02.29#ibcon#enter sib2, iclass 34, count 0 2006.246.07:54:02.29#ibcon#flushed, iclass 34, count 0 2006.246.07:54:02.29#ibcon#about to write, iclass 34, count 0 2006.246.07:54:02.29#ibcon#wrote, iclass 34, count 0 2006.246.07:54:02.29#ibcon#about to read 3, iclass 34, count 0 2006.246.07:54:02.31#ibcon#read 3, iclass 34, count 0 2006.246.07:54:02.31#ibcon#about to read 4, iclass 34, count 0 2006.246.07:54:02.31#ibcon#read 4, iclass 34, count 0 2006.246.07:54:02.31#ibcon#about to read 5, iclass 34, count 0 2006.246.07:54:02.31#ibcon#read 5, iclass 34, count 0 2006.246.07:54:02.31#ibcon#about to read 6, iclass 34, count 0 2006.246.07:54:02.31#ibcon#read 6, iclass 34, count 0 2006.246.07:54:02.31#ibcon#end of sib2, iclass 34, count 0 2006.246.07:54:02.31#ibcon#*mode == 0, iclass 34, count 0 2006.246.07:54:02.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.07:54:02.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:54:02.31#ibcon#*before write, iclass 34, count 0 2006.246.07:54:02.31#ibcon#enter sib2, iclass 34, count 0 2006.246.07:54:02.31#ibcon#flushed, iclass 34, count 0 2006.246.07:54:02.31#ibcon#about to write, iclass 34, count 0 2006.246.07:54:02.31#ibcon#wrote, iclass 34, count 0 2006.246.07:54:02.31#ibcon#about to read 3, iclass 34, count 0 2006.246.07:54:02.35#ibcon#read 3, iclass 34, count 0 2006.246.07:54:02.35#ibcon#about to read 4, iclass 34, count 0 2006.246.07:54:02.35#ibcon#read 4, iclass 34, count 0 2006.246.07:54:02.35#ibcon#about to read 5, iclass 34, count 0 2006.246.07:54:02.35#ibcon#read 5, iclass 34, count 0 2006.246.07:54:02.35#ibcon#about to read 6, iclass 34, count 0 2006.246.07:54:02.35#ibcon#read 6, iclass 34, count 0 2006.246.07:54:02.35#ibcon#end of sib2, iclass 34, count 0 2006.246.07:54:02.35#ibcon#*after write, iclass 34, count 0 2006.246.07:54:02.35#ibcon#*before return 0, iclass 34, count 0 2006.246.07:54:02.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:54:02.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.07:54:02.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.07:54:02.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.07:54:02.35$vc4f8/vb=6,3 2006.246.07:54:02.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.07:54:02.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.07:54:02.35#ibcon#ireg 11 cls_cnt 2 2006.246.07:54:02.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:54:02.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:54:02.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:54:02.41#ibcon#enter wrdev, iclass 36, count 2 2006.246.07:54:02.41#ibcon#first serial, iclass 36, count 2 2006.246.07:54:02.41#ibcon#enter sib2, iclass 36, count 2 2006.246.07:54:02.41#ibcon#flushed, iclass 36, count 2 2006.246.07:54:02.41#ibcon#about to write, iclass 36, count 2 2006.246.07:54:02.41#ibcon#wrote, iclass 36, count 2 2006.246.07:54:02.41#ibcon#about to read 3, iclass 36, count 2 2006.246.07:54:02.43#ibcon#read 3, iclass 36, count 2 2006.246.07:54:02.43#ibcon#about to read 4, iclass 36, count 2 2006.246.07:54:02.43#ibcon#read 4, iclass 36, count 2 2006.246.07:54:02.43#ibcon#about to read 5, iclass 36, count 2 2006.246.07:54:02.43#ibcon#read 5, iclass 36, count 2 2006.246.07:54:02.43#ibcon#about to read 6, iclass 36, count 2 2006.246.07:54:02.43#ibcon#read 6, iclass 36, count 2 2006.246.07:54:02.43#ibcon#end of sib2, iclass 36, count 2 2006.246.07:54:02.43#ibcon#*mode == 0, iclass 36, count 2 2006.246.07:54:02.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.07:54:02.43#ibcon#[27=AT06-03\r\n] 2006.246.07:54:02.43#ibcon#*before write, iclass 36, count 2 2006.246.07:54:02.43#ibcon#enter sib2, iclass 36, count 2 2006.246.07:54:02.43#ibcon#flushed, iclass 36, count 2 2006.246.07:54:02.43#ibcon#about to write, iclass 36, count 2 2006.246.07:54:02.43#ibcon#wrote, iclass 36, count 2 2006.246.07:54:02.43#ibcon#about to read 3, iclass 36, count 2 2006.246.07:54:02.46#ibcon#read 3, iclass 36, count 2 2006.246.07:54:02.46#ibcon#about to read 4, iclass 36, count 2 2006.246.07:54:02.46#ibcon#read 4, iclass 36, count 2 2006.246.07:54:02.46#ibcon#about to read 5, iclass 36, count 2 2006.246.07:54:02.46#ibcon#read 5, iclass 36, count 2 2006.246.07:54:02.46#ibcon#about to read 6, iclass 36, count 2 2006.246.07:54:02.46#ibcon#read 6, iclass 36, count 2 2006.246.07:54:02.46#ibcon#end of sib2, iclass 36, count 2 2006.246.07:54:02.46#ibcon#*after write, iclass 36, count 2 2006.246.07:54:02.46#ibcon#*before return 0, iclass 36, count 2 2006.246.07:54:02.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:54:02.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.07:54:02.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.07:54:02.46#ibcon#ireg 7 cls_cnt 0 2006.246.07:54:02.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:54:02.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:54:02.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:54:02.58#ibcon#enter wrdev, iclass 36, count 0 2006.246.07:54:02.58#ibcon#first serial, iclass 36, count 0 2006.246.07:54:02.58#ibcon#enter sib2, iclass 36, count 0 2006.246.07:54:02.58#ibcon#flushed, iclass 36, count 0 2006.246.07:54:02.58#ibcon#about to write, iclass 36, count 0 2006.246.07:54:02.58#ibcon#wrote, iclass 36, count 0 2006.246.07:54:02.58#ibcon#about to read 3, iclass 36, count 0 2006.246.07:54:02.60#ibcon#read 3, iclass 36, count 0 2006.246.07:54:02.60#ibcon#about to read 4, iclass 36, count 0 2006.246.07:54:02.60#ibcon#read 4, iclass 36, count 0 2006.246.07:54:02.60#ibcon#about to read 5, iclass 36, count 0 2006.246.07:54:02.60#ibcon#read 5, iclass 36, count 0 2006.246.07:54:02.60#ibcon#about to read 6, iclass 36, count 0 2006.246.07:54:02.60#ibcon#read 6, iclass 36, count 0 2006.246.07:54:02.60#ibcon#end of sib2, iclass 36, count 0 2006.246.07:54:02.60#ibcon#*mode == 0, iclass 36, count 0 2006.246.07:54:02.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.07:54:02.60#ibcon#[27=USB\r\n] 2006.246.07:54:02.60#ibcon#*before write, iclass 36, count 0 2006.246.07:54:02.60#ibcon#enter sib2, iclass 36, count 0 2006.246.07:54:02.60#ibcon#flushed, iclass 36, count 0 2006.246.07:54:02.60#ibcon#about to write, iclass 36, count 0 2006.246.07:54:02.60#ibcon#wrote, iclass 36, count 0 2006.246.07:54:02.60#ibcon#about to read 3, iclass 36, count 0 2006.246.07:54:02.63#ibcon#read 3, iclass 36, count 0 2006.246.07:54:02.63#ibcon#about to read 4, iclass 36, count 0 2006.246.07:54:02.63#ibcon#read 4, iclass 36, count 0 2006.246.07:54:02.63#ibcon#about to read 5, iclass 36, count 0 2006.246.07:54:02.63#ibcon#read 5, iclass 36, count 0 2006.246.07:54:02.63#ibcon#about to read 6, iclass 36, count 0 2006.246.07:54:02.63#ibcon#read 6, iclass 36, count 0 2006.246.07:54:02.63#ibcon#end of sib2, iclass 36, count 0 2006.246.07:54:02.63#ibcon#*after write, iclass 36, count 0 2006.246.07:54:02.63#ibcon#*before return 0, iclass 36, count 0 2006.246.07:54:02.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:54:02.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.07:54:02.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.07:54:02.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.07:54:02.63$vc4f8/vabw=wide 2006.246.07:54:02.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.07:54:02.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.07:54:02.63#ibcon#ireg 8 cls_cnt 0 2006.246.07:54:02.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:02.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:02.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:02.63#ibcon#enter wrdev, iclass 38, count 0 2006.246.07:54:02.63#ibcon#first serial, iclass 38, count 0 2006.246.07:54:02.63#ibcon#enter sib2, iclass 38, count 0 2006.246.07:54:02.63#ibcon#flushed, iclass 38, count 0 2006.246.07:54:02.63#ibcon#about to write, iclass 38, count 0 2006.246.07:54:02.63#ibcon#wrote, iclass 38, count 0 2006.246.07:54:02.63#ibcon#about to read 3, iclass 38, count 0 2006.246.07:54:02.65#ibcon#read 3, iclass 38, count 0 2006.246.07:54:02.65#ibcon#about to read 4, iclass 38, count 0 2006.246.07:54:02.65#ibcon#read 4, iclass 38, count 0 2006.246.07:54:02.65#ibcon#about to read 5, iclass 38, count 0 2006.246.07:54:02.65#ibcon#read 5, iclass 38, count 0 2006.246.07:54:02.65#ibcon#about to read 6, iclass 38, count 0 2006.246.07:54:02.65#ibcon#read 6, iclass 38, count 0 2006.246.07:54:02.65#ibcon#end of sib2, iclass 38, count 0 2006.246.07:54:02.65#ibcon#*mode == 0, iclass 38, count 0 2006.246.07:54:02.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.07:54:02.65#ibcon#[25=BW32\r\n] 2006.246.07:54:02.65#ibcon#*before write, iclass 38, count 0 2006.246.07:54:02.65#ibcon#enter sib2, iclass 38, count 0 2006.246.07:54:02.65#ibcon#flushed, iclass 38, count 0 2006.246.07:54:02.65#ibcon#about to write, iclass 38, count 0 2006.246.07:54:02.65#ibcon#wrote, iclass 38, count 0 2006.246.07:54:02.65#ibcon#about to read 3, iclass 38, count 0 2006.246.07:54:02.68#ibcon#read 3, iclass 38, count 0 2006.246.07:54:02.68#ibcon#about to read 4, iclass 38, count 0 2006.246.07:54:02.68#ibcon#read 4, iclass 38, count 0 2006.246.07:54:02.68#ibcon#about to read 5, iclass 38, count 0 2006.246.07:54:02.68#ibcon#read 5, iclass 38, count 0 2006.246.07:54:02.68#ibcon#about to read 6, iclass 38, count 0 2006.246.07:54:02.68#ibcon#read 6, iclass 38, count 0 2006.246.07:54:02.68#ibcon#end of sib2, iclass 38, count 0 2006.246.07:54:02.68#ibcon#*after write, iclass 38, count 0 2006.246.07:54:02.68#ibcon#*before return 0, iclass 38, count 0 2006.246.07:54:02.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:02.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.07:54:02.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.07:54:02.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.07:54:02.68$vc4f8/vbbw=wide 2006.246.07:54:02.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.07:54:02.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.07:54:02.68#ibcon#ireg 8 cls_cnt 0 2006.246.07:54:02.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:54:02.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:54:02.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:54:02.75#ibcon#enter wrdev, iclass 40, count 0 2006.246.07:54:02.75#ibcon#first serial, iclass 40, count 0 2006.246.07:54:02.75#ibcon#enter sib2, iclass 40, count 0 2006.246.07:54:02.75#ibcon#flushed, iclass 40, count 0 2006.246.07:54:02.75#ibcon#about to write, iclass 40, count 0 2006.246.07:54:02.75#ibcon#wrote, iclass 40, count 0 2006.246.07:54:02.75#ibcon#about to read 3, iclass 40, count 0 2006.246.07:54:02.77#ibcon#read 3, iclass 40, count 0 2006.246.07:54:02.77#ibcon#about to read 4, iclass 40, count 0 2006.246.07:54:02.77#ibcon#read 4, iclass 40, count 0 2006.246.07:54:02.77#ibcon#about to read 5, iclass 40, count 0 2006.246.07:54:02.77#ibcon#read 5, iclass 40, count 0 2006.246.07:54:02.77#ibcon#about to read 6, iclass 40, count 0 2006.246.07:54:02.77#ibcon#read 6, iclass 40, count 0 2006.246.07:54:02.77#ibcon#end of sib2, iclass 40, count 0 2006.246.07:54:02.77#ibcon#*mode == 0, iclass 40, count 0 2006.246.07:54:02.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.07:54:02.77#ibcon#[27=BW32\r\n] 2006.246.07:54:02.77#ibcon#*before write, iclass 40, count 0 2006.246.07:54:02.77#ibcon#enter sib2, iclass 40, count 0 2006.246.07:54:02.77#ibcon#flushed, iclass 40, count 0 2006.246.07:54:02.77#ibcon#about to write, iclass 40, count 0 2006.246.07:54:02.77#ibcon#wrote, iclass 40, count 0 2006.246.07:54:02.77#ibcon#about to read 3, iclass 40, count 0 2006.246.07:54:02.80#ibcon#read 3, iclass 40, count 0 2006.246.07:54:02.80#ibcon#about to read 4, iclass 40, count 0 2006.246.07:54:02.80#ibcon#read 4, iclass 40, count 0 2006.246.07:54:02.80#ibcon#about to read 5, iclass 40, count 0 2006.246.07:54:02.80#ibcon#read 5, iclass 40, count 0 2006.246.07:54:02.80#ibcon#about to read 6, iclass 40, count 0 2006.246.07:54:02.80#ibcon#read 6, iclass 40, count 0 2006.246.07:54:02.80#ibcon#end of sib2, iclass 40, count 0 2006.246.07:54:02.80#ibcon#*after write, iclass 40, count 0 2006.246.07:54:02.80#ibcon#*before return 0, iclass 40, count 0 2006.246.07:54:02.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:54:02.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.07:54:02.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.07:54:02.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.07:54:02.80$4f8m12a/ifd4f 2006.246.07:54:02.80$ifd4f/lo= 2006.246.07:54:02.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:54:02.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:54:02.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:54:02.80$ifd4f/patch= 2006.246.07:54:02.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:54:02.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:54:02.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:54:02.80$4f8m12a/"form=m,16.000,1:2 2006.246.07:54:02.80$4f8m12a/"tpicd 2006.246.07:54:02.80$4f8m12a/echo=off 2006.246.07:54:02.80$4f8m12a/xlog=off 2006.246.07:54:02.80:!2006.246.07:55:20 2006.246.07:54:20.13#trakl#Source acquired 2006.246.07:54:21.13#flagr#flagr/antenna,acquired 2006.246.07:55:20.00:preob 2006.246.07:55:20.14/onsource/TRACKING 2006.246.07:55:20.14:!2006.246.07:55:30 2006.246.07:55:30.00:data_valid=on 2006.246.07:55:30.00:midob 2006.246.07:55:30.14/onsource/TRACKING 2006.246.07:55:30.14/wx/26.67,1005.7,74 2006.246.07:55:30.26/cable/+6.4136E-03 2006.246.07:55:31.35/va/01,08,usb,yes,31,33 2006.246.07:55:31.35/va/02,07,usb,yes,31,32 2006.246.07:55:31.35/va/03,06,usb,yes,33,33 2006.246.07:55:31.35/va/04,07,usb,yes,32,34 2006.246.07:55:31.35/va/05,07,usb,yes,34,35 2006.246.07:55:31.35/va/06,07,usb,yes,29,29 2006.246.07:55:31.35/va/07,07,usb,yes,29,29 2006.246.07:55:31.35/va/08,08,usb,yes,25,25 2006.246.07:55:31.58/valo/01,532.99,yes,locked 2006.246.07:55:31.58/valo/02,572.99,yes,locked 2006.246.07:55:31.58/valo/03,672.99,yes,locked 2006.246.07:55:31.58/valo/04,832.99,yes,locked 2006.246.07:55:31.58/valo/05,652.99,yes,locked 2006.246.07:55:31.58/valo/06,772.99,yes,locked 2006.246.07:55:31.58/valo/07,832.99,yes,locked 2006.246.07:55:31.58/valo/08,852.99,yes,locked 2006.246.07:55:32.67/vb/01,04,usb,yes,30,29 2006.246.07:55:32.67/vb/02,04,usb,yes,32,34 2006.246.07:55:32.67/vb/03,04,usb,yes,29,32 2006.246.07:55:32.67/vb/04,04,usb,yes,29,30 2006.246.07:55:32.67/vb/05,03,usb,yes,35,39 2006.246.07:55:32.67/vb/06,03,usb,yes,35,39 2006.246.07:55:32.67/vb/07,04,usb,yes,31,31 2006.246.07:55:32.67/vb/08,03,usb,yes,35,39 2006.246.07:55:32.90/vblo/01,632.99,yes,locked 2006.246.07:55:32.90/vblo/02,640.99,yes,locked 2006.246.07:55:32.90/vblo/03,656.99,yes,locked 2006.246.07:55:32.90/vblo/04,712.99,yes,locked 2006.246.07:55:32.90/vblo/05,744.99,yes,locked 2006.246.07:55:32.90/vblo/06,752.99,yes,locked 2006.246.07:55:32.90/vblo/07,734.99,yes,locked 2006.246.07:55:32.90/vblo/08,744.99,yes,locked 2006.246.07:55:33.05/vabw/8 2006.246.07:55:33.21/vbbw/8 2006.246.07:55:33.30/xfe/off,on,13.2 2006.246.07:55:33.67/ifatt/23,28,28,28 2006.246.07:55:34.08/fmout-gps/S +4.38E-07 2006.246.07:55:34.12:!2006.246.07:56:30 2006.246.07:56:30.00:data_valid=off 2006.246.07:56:30.00:postob 2006.246.07:56:30.18/cable/+6.4141E-03 2006.246.07:56:30.22/wx/26.66,1005.7,74 2006.246.07:56:31.08/fmout-gps/S +4.37E-07 2006.246.07:56:31.08:scan_name=246-0759,k06246,60 2006.246.07:56:31.09:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.246.07:56:31.14#flagr#flagr/antenna,new-source 2006.246.07:56:32.14:checkk5 2006.246.07:56:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.07:56:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.07:56:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.07:56:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.07:56:34.01/chk_obsdata//k5ts1/T2460755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:56:34.37/chk_obsdata//k5ts2/T2460755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:56:34.74/chk_obsdata//k5ts3/T2460755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:56:35.11/chk_obsdata//k5ts4/T2460755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.07:56:35.81/k5log//k5ts1_log_newline 2006.246.07:56:36.49/k5log//k5ts2_log_newline 2006.246.07:56:37.18/k5log//k5ts3_log_newline 2006.246.07:56:37.87/k5log//k5ts4_log_newline 2006.246.07:56:37.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.07:56:37.90:4f8m12a=2 2006.246.07:56:37.90$4f8m12a/echo=on 2006.246.07:56:37.90$4f8m12a/pcalon 2006.246.07:56:37.90$pcalon/"no phase cal control is implemented here 2006.246.07:56:37.90$4f8m12a/"tpicd=stop 2006.246.07:56:37.90$4f8m12a/vc4f8 2006.246.07:56:37.90$vc4f8/valo=1,532.99 2006.246.07:56:37.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.07:56:37.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.07:56:37.90#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:37.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:37.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:37.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:37.90#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:56:37.90#ibcon#first serial, iclass 31, count 0 2006.246.07:56:37.90#ibcon#enter sib2, iclass 31, count 0 2006.246.07:56:37.90#ibcon#flushed, iclass 31, count 0 2006.246.07:56:37.90#ibcon#about to write, iclass 31, count 0 2006.246.07:56:37.90#ibcon#wrote, iclass 31, count 0 2006.246.07:56:37.90#ibcon#about to read 3, iclass 31, count 0 2006.246.07:56:37.94#ibcon#read 3, iclass 31, count 0 2006.246.07:56:37.94#ibcon#about to read 4, iclass 31, count 0 2006.246.07:56:37.94#ibcon#read 4, iclass 31, count 0 2006.246.07:56:37.94#ibcon#about to read 5, iclass 31, count 0 2006.246.07:56:37.94#ibcon#read 5, iclass 31, count 0 2006.246.07:56:37.94#ibcon#about to read 6, iclass 31, count 0 2006.246.07:56:37.94#ibcon#read 6, iclass 31, count 0 2006.246.07:56:37.94#ibcon#end of sib2, iclass 31, count 0 2006.246.07:56:37.94#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:56:37.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:56:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.07:56:37.94#ibcon#*before write, iclass 31, count 0 2006.246.07:56:37.94#ibcon#enter sib2, iclass 31, count 0 2006.246.07:56:37.94#ibcon#flushed, iclass 31, count 0 2006.246.07:56:37.94#ibcon#about to write, iclass 31, count 0 2006.246.07:56:37.94#ibcon#wrote, iclass 31, count 0 2006.246.07:56:37.94#ibcon#about to read 3, iclass 31, count 0 2006.246.07:56:37.99#ibcon#read 3, iclass 31, count 0 2006.246.07:56:37.99#ibcon#about to read 4, iclass 31, count 0 2006.246.07:56:37.99#ibcon#read 4, iclass 31, count 0 2006.246.07:56:37.99#ibcon#about to read 5, iclass 31, count 0 2006.246.07:56:37.99#ibcon#read 5, iclass 31, count 0 2006.246.07:56:37.99#ibcon#about to read 6, iclass 31, count 0 2006.246.07:56:37.99#ibcon#read 6, iclass 31, count 0 2006.246.07:56:37.99#ibcon#end of sib2, iclass 31, count 0 2006.246.07:56:37.99#ibcon#*after write, iclass 31, count 0 2006.246.07:56:37.99#ibcon#*before return 0, iclass 31, count 0 2006.246.07:56:37.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:37.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:37.99#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:56:37.99#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:56:37.99$vc4f8/va=1,8 2006.246.07:56:37.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.07:56:37.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.07:56:37.99#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:37.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:37.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:37.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:37.99#ibcon#enter wrdev, iclass 33, count 2 2006.246.07:56:37.99#ibcon#first serial, iclass 33, count 2 2006.246.07:56:37.99#ibcon#enter sib2, iclass 33, count 2 2006.246.07:56:37.99#ibcon#flushed, iclass 33, count 2 2006.246.07:56:37.99#ibcon#about to write, iclass 33, count 2 2006.246.07:56:37.99#ibcon#wrote, iclass 33, count 2 2006.246.07:56:37.99#ibcon#about to read 3, iclass 33, count 2 2006.246.07:56:38.01#ibcon#read 3, iclass 33, count 2 2006.246.07:56:38.01#ibcon#about to read 4, iclass 33, count 2 2006.246.07:56:38.01#ibcon#read 4, iclass 33, count 2 2006.246.07:56:38.01#ibcon#about to read 5, iclass 33, count 2 2006.246.07:56:38.01#ibcon#read 5, iclass 33, count 2 2006.246.07:56:38.01#ibcon#about to read 6, iclass 33, count 2 2006.246.07:56:38.01#ibcon#read 6, iclass 33, count 2 2006.246.07:56:38.01#ibcon#end of sib2, iclass 33, count 2 2006.246.07:56:38.01#ibcon#*mode == 0, iclass 33, count 2 2006.246.07:56:38.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.07:56:38.01#ibcon#[25=AT01-08\r\n] 2006.246.07:56:38.01#ibcon#*before write, iclass 33, count 2 2006.246.07:56:38.01#ibcon#enter sib2, iclass 33, count 2 2006.246.07:56:38.01#ibcon#flushed, iclass 33, count 2 2006.246.07:56:38.01#ibcon#about to write, iclass 33, count 2 2006.246.07:56:38.01#ibcon#wrote, iclass 33, count 2 2006.246.07:56:38.01#ibcon#about to read 3, iclass 33, count 2 2006.246.07:56:38.04#ibcon#read 3, iclass 33, count 2 2006.246.07:56:38.04#ibcon#about to read 4, iclass 33, count 2 2006.246.07:56:38.04#ibcon#read 4, iclass 33, count 2 2006.246.07:56:38.04#ibcon#about to read 5, iclass 33, count 2 2006.246.07:56:38.04#ibcon#read 5, iclass 33, count 2 2006.246.07:56:38.04#ibcon#about to read 6, iclass 33, count 2 2006.246.07:56:38.04#ibcon#read 6, iclass 33, count 2 2006.246.07:56:38.04#ibcon#end of sib2, iclass 33, count 2 2006.246.07:56:38.04#ibcon#*after write, iclass 33, count 2 2006.246.07:56:38.04#ibcon#*before return 0, iclass 33, count 2 2006.246.07:56:38.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:38.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:38.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.07:56:38.04#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:38.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:38.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:38.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:38.16#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:56:38.16#ibcon#first serial, iclass 33, count 0 2006.246.07:56:38.16#ibcon#enter sib2, iclass 33, count 0 2006.246.07:56:38.16#ibcon#flushed, iclass 33, count 0 2006.246.07:56:38.16#ibcon#about to write, iclass 33, count 0 2006.246.07:56:38.16#ibcon#wrote, iclass 33, count 0 2006.246.07:56:38.16#ibcon#about to read 3, iclass 33, count 0 2006.246.07:56:38.18#ibcon#read 3, iclass 33, count 0 2006.246.07:56:38.18#ibcon#about to read 4, iclass 33, count 0 2006.246.07:56:38.18#ibcon#read 4, iclass 33, count 0 2006.246.07:56:38.18#ibcon#about to read 5, iclass 33, count 0 2006.246.07:56:38.18#ibcon#read 5, iclass 33, count 0 2006.246.07:56:38.18#ibcon#about to read 6, iclass 33, count 0 2006.246.07:56:38.18#ibcon#read 6, iclass 33, count 0 2006.246.07:56:38.18#ibcon#end of sib2, iclass 33, count 0 2006.246.07:56:38.18#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:56:38.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:56:38.18#ibcon#[25=USB\r\n] 2006.246.07:56:38.18#ibcon#*before write, iclass 33, count 0 2006.246.07:56:38.18#ibcon#enter sib2, iclass 33, count 0 2006.246.07:56:38.18#ibcon#flushed, iclass 33, count 0 2006.246.07:56:38.18#ibcon#about to write, iclass 33, count 0 2006.246.07:56:38.18#ibcon#wrote, iclass 33, count 0 2006.246.07:56:38.18#ibcon#about to read 3, iclass 33, count 0 2006.246.07:56:38.21#ibcon#read 3, iclass 33, count 0 2006.246.07:56:38.21#ibcon#about to read 4, iclass 33, count 0 2006.246.07:56:38.21#ibcon#read 4, iclass 33, count 0 2006.246.07:56:38.21#ibcon#about to read 5, iclass 33, count 0 2006.246.07:56:38.21#ibcon#read 5, iclass 33, count 0 2006.246.07:56:38.21#ibcon#about to read 6, iclass 33, count 0 2006.246.07:56:38.21#ibcon#read 6, iclass 33, count 0 2006.246.07:56:38.21#ibcon#end of sib2, iclass 33, count 0 2006.246.07:56:38.21#ibcon#*after write, iclass 33, count 0 2006.246.07:56:38.21#ibcon#*before return 0, iclass 33, count 0 2006.246.07:56:38.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:38.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:38.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:56:38.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:56:38.21$vc4f8/valo=2,572.99 2006.246.07:56:38.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.07:56:38.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.07:56:38.21#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:38.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:38.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:38.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:38.21#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:56:38.21#ibcon#first serial, iclass 35, count 0 2006.246.07:56:38.21#ibcon#enter sib2, iclass 35, count 0 2006.246.07:56:38.21#ibcon#flushed, iclass 35, count 0 2006.246.07:56:38.21#ibcon#about to write, iclass 35, count 0 2006.246.07:56:38.21#ibcon#wrote, iclass 35, count 0 2006.246.07:56:38.21#ibcon#about to read 3, iclass 35, count 0 2006.246.07:56:38.23#ibcon#read 3, iclass 35, count 0 2006.246.07:56:38.23#ibcon#about to read 4, iclass 35, count 0 2006.246.07:56:38.23#ibcon#read 4, iclass 35, count 0 2006.246.07:56:38.23#ibcon#about to read 5, iclass 35, count 0 2006.246.07:56:38.23#ibcon#read 5, iclass 35, count 0 2006.246.07:56:38.23#ibcon#about to read 6, iclass 35, count 0 2006.246.07:56:38.23#ibcon#read 6, iclass 35, count 0 2006.246.07:56:38.23#ibcon#end of sib2, iclass 35, count 0 2006.246.07:56:38.23#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:56:38.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:56:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.07:56:38.23#ibcon#*before write, iclass 35, count 0 2006.246.07:56:38.23#ibcon#enter sib2, iclass 35, count 0 2006.246.07:56:38.23#ibcon#flushed, iclass 35, count 0 2006.246.07:56:38.23#ibcon#about to write, iclass 35, count 0 2006.246.07:56:38.23#ibcon#wrote, iclass 35, count 0 2006.246.07:56:38.23#ibcon#about to read 3, iclass 35, count 0 2006.246.07:56:38.27#ibcon#read 3, iclass 35, count 0 2006.246.07:56:38.27#ibcon#about to read 4, iclass 35, count 0 2006.246.07:56:38.27#ibcon#read 4, iclass 35, count 0 2006.246.07:56:38.27#ibcon#about to read 5, iclass 35, count 0 2006.246.07:56:38.27#ibcon#read 5, iclass 35, count 0 2006.246.07:56:38.27#ibcon#about to read 6, iclass 35, count 0 2006.246.07:56:38.27#ibcon#read 6, iclass 35, count 0 2006.246.07:56:38.27#ibcon#end of sib2, iclass 35, count 0 2006.246.07:56:38.27#ibcon#*after write, iclass 35, count 0 2006.246.07:56:38.27#ibcon#*before return 0, iclass 35, count 0 2006.246.07:56:38.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:38.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:38.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:56:38.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:56:38.27$vc4f8/va=2,7 2006.246.07:56:38.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.07:56:38.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.07:56:38.27#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:38.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:38.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:38.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:38.33#ibcon#enter wrdev, iclass 37, count 2 2006.246.07:56:38.33#ibcon#first serial, iclass 37, count 2 2006.246.07:56:38.33#ibcon#enter sib2, iclass 37, count 2 2006.246.07:56:38.33#ibcon#flushed, iclass 37, count 2 2006.246.07:56:38.33#ibcon#about to write, iclass 37, count 2 2006.246.07:56:38.33#ibcon#wrote, iclass 37, count 2 2006.246.07:56:38.33#ibcon#about to read 3, iclass 37, count 2 2006.246.07:56:38.35#ibcon#read 3, iclass 37, count 2 2006.246.07:56:38.35#ibcon#about to read 4, iclass 37, count 2 2006.246.07:56:38.35#ibcon#read 4, iclass 37, count 2 2006.246.07:56:38.35#ibcon#about to read 5, iclass 37, count 2 2006.246.07:56:38.35#ibcon#read 5, iclass 37, count 2 2006.246.07:56:38.35#ibcon#about to read 6, iclass 37, count 2 2006.246.07:56:38.35#ibcon#read 6, iclass 37, count 2 2006.246.07:56:38.35#ibcon#end of sib2, iclass 37, count 2 2006.246.07:56:38.35#ibcon#*mode == 0, iclass 37, count 2 2006.246.07:56:38.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.07:56:38.35#ibcon#[25=AT02-07\r\n] 2006.246.07:56:38.35#ibcon#*before write, iclass 37, count 2 2006.246.07:56:38.35#ibcon#enter sib2, iclass 37, count 2 2006.246.07:56:38.35#ibcon#flushed, iclass 37, count 2 2006.246.07:56:38.35#ibcon#about to write, iclass 37, count 2 2006.246.07:56:38.35#ibcon#wrote, iclass 37, count 2 2006.246.07:56:38.35#ibcon#about to read 3, iclass 37, count 2 2006.246.07:56:38.38#ibcon#read 3, iclass 37, count 2 2006.246.07:56:38.38#ibcon#about to read 4, iclass 37, count 2 2006.246.07:56:38.38#ibcon#read 4, iclass 37, count 2 2006.246.07:56:38.38#ibcon#about to read 5, iclass 37, count 2 2006.246.07:56:38.38#ibcon#read 5, iclass 37, count 2 2006.246.07:56:38.38#ibcon#about to read 6, iclass 37, count 2 2006.246.07:56:38.38#ibcon#read 6, iclass 37, count 2 2006.246.07:56:38.38#ibcon#end of sib2, iclass 37, count 2 2006.246.07:56:38.38#ibcon#*after write, iclass 37, count 2 2006.246.07:56:38.38#ibcon#*before return 0, iclass 37, count 2 2006.246.07:56:38.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:38.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:38.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.07:56:38.38#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:38.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:38.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:38.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:38.50#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:56:38.50#ibcon#first serial, iclass 37, count 0 2006.246.07:56:38.50#ibcon#enter sib2, iclass 37, count 0 2006.246.07:56:38.50#ibcon#flushed, iclass 37, count 0 2006.246.07:56:38.50#ibcon#about to write, iclass 37, count 0 2006.246.07:56:38.50#ibcon#wrote, iclass 37, count 0 2006.246.07:56:38.50#ibcon#about to read 3, iclass 37, count 0 2006.246.07:56:38.52#ibcon#read 3, iclass 37, count 0 2006.246.07:56:38.52#ibcon#about to read 4, iclass 37, count 0 2006.246.07:56:38.52#ibcon#read 4, iclass 37, count 0 2006.246.07:56:38.52#ibcon#about to read 5, iclass 37, count 0 2006.246.07:56:38.52#ibcon#read 5, iclass 37, count 0 2006.246.07:56:38.52#ibcon#about to read 6, iclass 37, count 0 2006.246.07:56:38.52#ibcon#read 6, iclass 37, count 0 2006.246.07:56:38.52#ibcon#end of sib2, iclass 37, count 0 2006.246.07:56:38.52#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:56:38.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:56:38.52#ibcon#[25=USB\r\n] 2006.246.07:56:38.52#ibcon#*before write, iclass 37, count 0 2006.246.07:56:38.52#ibcon#enter sib2, iclass 37, count 0 2006.246.07:56:38.52#ibcon#flushed, iclass 37, count 0 2006.246.07:56:38.52#ibcon#about to write, iclass 37, count 0 2006.246.07:56:38.52#ibcon#wrote, iclass 37, count 0 2006.246.07:56:38.52#ibcon#about to read 3, iclass 37, count 0 2006.246.07:56:38.55#ibcon#read 3, iclass 37, count 0 2006.246.07:56:38.55#ibcon#about to read 4, iclass 37, count 0 2006.246.07:56:38.55#ibcon#read 4, iclass 37, count 0 2006.246.07:56:38.55#ibcon#about to read 5, iclass 37, count 0 2006.246.07:56:38.55#ibcon#read 5, iclass 37, count 0 2006.246.07:56:38.55#ibcon#about to read 6, iclass 37, count 0 2006.246.07:56:38.55#ibcon#read 6, iclass 37, count 0 2006.246.07:56:38.55#ibcon#end of sib2, iclass 37, count 0 2006.246.07:56:38.55#ibcon#*after write, iclass 37, count 0 2006.246.07:56:38.55#ibcon#*before return 0, iclass 37, count 0 2006.246.07:56:38.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:38.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:38.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:56:38.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:56:38.55$vc4f8/valo=3,672.99 2006.246.07:56:38.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:56:38.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:56:38.55#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:38.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:38.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:38.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:38.55#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:56:38.55#ibcon#first serial, iclass 39, count 0 2006.246.07:56:38.55#ibcon#enter sib2, iclass 39, count 0 2006.246.07:56:38.55#ibcon#flushed, iclass 39, count 0 2006.246.07:56:38.55#ibcon#about to write, iclass 39, count 0 2006.246.07:56:38.55#ibcon#wrote, iclass 39, count 0 2006.246.07:56:38.55#ibcon#about to read 3, iclass 39, count 0 2006.246.07:56:38.57#ibcon#read 3, iclass 39, count 0 2006.246.07:56:38.57#ibcon#about to read 4, iclass 39, count 0 2006.246.07:56:38.57#ibcon#read 4, iclass 39, count 0 2006.246.07:56:38.57#ibcon#about to read 5, iclass 39, count 0 2006.246.07:56:38.57#ibcon#read 5, iclass 39, count 0 2006.246.07:56:38.57#ibcon#about to read 6, iclass 39, count 0 2006.246.07:56:38.57#ibcon#read 6, iclass 39, count 0 2006.246.07:56:38.57#ibcon#end of sib2, iclass 39, count 0 2006.246.07:56:38.57#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:56:38.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:56:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.07:56:38.57#ibcon#*before write, iclass 39, count 0 2006.246.07:56:38.57#ibcon#enter sib2, iclass 39, count 0 2006.246.07:56:38.57#ibcon#flushed, iclass 39, count 0 2006.246.07:56:38.57#ibcon#about to write, iclass 39, count 0 2006.246.07:56:38.57#ibcon#wrote, iclass 39, count 0 2006.246.07:56:38.57#ibcon#about to read 3, iclass 39, count 0 2006.246.07:56:38.61#ibcon#read 3, iclass 39, count 0 2006.246.07:56:38.61#ibcon#about to read 4, iclass 39, count 0 2006.246.07:56:38.61#ibcon#read 4, iclass 39, count 0 2006.246.07:56:38.61#ibcon#about to read 5, iclass 39, count 0 2006.246.07:56:38.61#ibcon#read 5, iclass 39, count 0 2006.246.07:56:38.61#ibcon#about to read 6, iclass 39, count 0 2006.246.07:56:38.61#ibcon#read 6, iclass 39, count 0 2006.246.07:56:38.61#ibcon#end of sib2, iclass 39, count 0 2006.246.07:56:38.61#ibcon#*after write, iclass 39, count 0 2006.246.07:56:38.61#ibcon#*before return 0, iclass 39, count 0 2006.246.07:56:38.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:38.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:38.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:56:38.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:56:38.61$vc4f8/va=3,6 2006.246.07:56:38.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.07:56:38.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.07:56:38.61#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:38.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:38.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:38.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:38.67#ibcon#enter wrdev, iclass 3, count 2 2006.246.07:56:38.67#ibcon#first serial, iclass 3, count 2 2006.246.07:56:38.67#ibcon#enter sib2, iclass 3, count 2 2006.246.07:56:38.67#ibcon#flushed, iclass 3, count 2 2006.246.07:56:38.67#ibcon#about to write, iclass 3, count 2 2006.246.07:56:38.67#ibcon#wrote, iclass 3, count 2 2006.246.07:56:38.67#ibcon#about to read 3, iclass 3, count 2 2006.246.07:56:38.70#ibcon#read 3, iclass 3, count 2 2006.246.07:56:38.70#ibcon#about to read 4, iclass 3, count 2 2006.246.07:56:38.70#ibcon#read 4, iclass 3, count 2 2006.246.07:56:38.70#ibcon#about to read 5, iclass 3, count 2 2006.246.07:56:38.70#ibcon#read 5, iclass 3, count 2 2006.246.07:56:38.70#ibcon#about to read 6, iclass 3, count 2 2006.246.07:56:38.70#ibcon#read 6, iclass 3, count 2 2006.246.07:56:38.70#ibcon#end of sib2, iclass 3, count 2 2006.246.07:56:38.70#ibcon#*mode == 0, iclass 3, count 2 2006.246.07:56:38.70#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.07:56:38.70#ibcon#[25=AT03-06\r\n] 2006.246.07:56:38.70#ibcon#*before write, iclass 3, count 2 2006.246.07:56:38.70#ibcon#enter sib2, iclass 3, count 2 2006.246.07:56:38.70#ibcon#flushed, iclass 3, count 2 2006.246.07:56:38.70#ibcon#about to write, iclass 3, count 2 2006.246.07:56:38.70#ibcon#wrote, iclass 3, count 2 2006.246.07:56:38.70#ibcon#about to read 3, iclass 3, count 2 2006.246.07:56:38.73#ibcon#read 3, iclass 3, count 2 2006.246.07:56:38.73#ibcon#about to read 4, iclass 3, count 2 2006.246.07:56:38.73#ibcon#read 4, iclass 3, count 2 2006.246.07:56:38.73#ibcon#about to read 5, iclass 3, count 2 2006.246.07:56:38.73#ibcon#read 5, iclass 3, count 2 2006.246.07:56:38.73#ibcon#about to read 6, iclass 3, count 2 2006.246.07:56:38.73#ibcon#read 6, iclass 3, count 2 2006.246.07:56:38.73#ibcon#end of sib2, iclass 3, count 2 2006.246.07:56:38.73#ibcon#*after write, iclass 3, count 2 2006.246.07:56:38.73#ibcon#*before return 0, iclass 3, count 2 2006.246.07:56:38.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:38.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:38.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.07:56:38.73#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:38.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:38.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:38.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:38.85#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:56:38.85#ibcon#first serial, iclass 3, count 0 2006.246.07:56:38.85#ibcon#enter sib2, iclass 3, count 0 2006.246.07:56:38.85#ibcon#flushed, iclass 3, count 0 2006.246.07:56:38.85#ibcon#about to write, iclass 3, count 0 2006.246.07:56:38.85#ibcon#wrote, iclass 3, count 0 2006.246.07:56:38.85#ibcon#about to read 3, iclass 3, count 0 2006.246.07:56:38.87#ibcon#read 3, iclass 3, count 0 2006.246.07:56:38.87#ibcon#about to read 4, iclass 3, count 0 2006.246.07:56:38.87#ibcon#read 4, iclass 3, count 0 2006.246.07:56:38.87#ibcon#about to read 5, iclass 3, count 0 2006.246.07:56:38.87#ibcon#read 5, iclass 3, count 0 2006.246.07:56:38.87#ibcon#about to read 6, iclass 3, count 0 2006.246.07:56:38.87#ibcon#read 6, iclass 3, count 0 2006.246.07:56:38.87#ibcon#end of sib2, iclass 3, count 0 2006.246.07:56:38.87#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:56:38.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:56:38.87#ibcon#[25=USB\r\n] 2006.246.07:56:38.87#ibcon#*before write, iclass 3, count 0 2006.246.07:56:38.87#ibcon#enter sib2, iclass 3, count 0 2006.246.07:56:38.87#ibcon#flushed, iclass 3, count 0 2006.246.07:56:38.87#ibcon#about to write, iclass 3, count 0 2006.246.07:56:38.87#ibcon#wrote, iclass 3, count 0 2006.246.07:56:38.87#ibcon#about to read 3, iclass 3, count 0 2006.246.07:56:38.90#ibcon#read 3, iclass 3, count 0 2006.246.07:56:38.90#ibcon#about to read 4, iclass 3, count 0 2006.246.07:56:38.90#ibcon#read 4, iclass 3, count 0 2006.246.07:56:38.90#ibcon#about to read 5, iclass 3, count 0 2006.246.07:56:38.90#ibcon#read 5, iclass 3, count 0 2006.246.07:56:38.90#ibcon#about to read 6, iclass 3, count 0 2006.246.07:56:38.90#ibcon#read 6, iclass 3, count 0 2006.246.07:56:38.90#ibcon#end of sib2, iclass 3, count 0 2006.246.07:56:38.90#ibcon#*after write, iclass 3, count 0 2006.246.07:56:38.90#ibcon#*before return 0, iclass 3, count 0 2006.246.07:56:38.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:38.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:38.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:56:38.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:56:38.90$vc4f8/valo=4,832.99 2006.246.07:56:38.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:56:38.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:56:38.90#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:38.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:38.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:38.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:38.90#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:56:38.90#ibcon#first serial, iclass 5, count 0 2006.246.07:56:38.90#ibcon#enter sib2, iclass 5, count 0 2006.246.07:56:38.90#ibcon#flushed, iclass 5, count 0 2006.246.07:56:38.90#ibcon#about to write, iclass 5, count 0 2006.246.07:56:38.90#ibcon#wrote, iclass 5, count 0 2006.246.07:56:38.90#ibcon#about to read 3, iclass 5, count 0 2006.246.07:56:38.92#ibcon#read 3, iclass 5, count 0 2006.246.07:56:38.92#ibcon#about to read 4, iclass 5, count 0 2006.246.07:56:38.92#ibcon#read 4, iclass 5, count 0 2006.246.07:56:38.92#ibcon#about to read 5, iclass 5, count 0 2006.246.07:56:38.92#ibcon#read 5, iclass 5, count 0 2006.246.07:56:38.92#ibcon#about to read 6, iclass 5, count 0 2006.246.07:56:38.92#ibcon#read 6, iclass 5, count 0 2006.246.07:56:38.92#ibcon#end of sib2, iclass 5, count 0 2006.246.07:56:38.92#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:56:38.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:56:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.07:56:38.92#ibcon#*before write, iclass 5, count 0 2006.246.07:56:38.92#ibcon#enter sib2, iclass 5, count 0 2006.246.07:56:38.92#ibcon#flushed, iclass 5, count 0 2006.246.07:56:38.92#ibcon#about to write, iclass 5, count 0 2006.246.07:56:38.92#ibcon#wrote, iclass 5, count 0 2006.246.07:56:38.92#ibcon#about to read 3, iclass 5, count 0 2006.246.07:56:38.96#ibcon#read 3, iclass 5, count 0 2006.246.07:56:38.96#ibcon#about to read 4, iclass 5, count 0 2006.246.07:56:38.96#ibcon#read 4, iclass 5, count 0 2006.246.07:56:38.96#ibcon#about to read 5, iclass 5, count 0 2006.246.07:56:38.96#ibcon#read 5, iclass 5, count 0 2006.246.07:56:38.96#ibcon#about to read 6, iclass 5, count 0 2006.246.07:56:38.96#ibcon#read 6, iclass 5, count 0 2006.246.07:56:38.96#ibcon#end of sib2, iclass 5, count 0 2006.246.07:56:38.96#ibcon#*after write, iclass 5, count 0 2006.246.07:56:38.96#ibcon#*before return 0, iclass 5, count 0 2006.246.07:56:38.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:38.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:38.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:56:38.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:56:38.96$vc4f8/va=4,7 2006.246.07:56:38.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:56:38.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:56:38.96#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:38.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:39.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:39.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:39.02#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:56:39.02#ibcon#first serial, iclass 7, count 2 2006.246.07:56:39.02#ibcon#enter sib2, iclass 7, count 2 2006.246.07:56:39.02#ibcon#flushed, iclass 7, count 2 2006.246.07:56:39.02#ibcon#about to write, iclass 7, count 2 2006.246.07:56:39.02#ibcon#wrote, iclass 7, count 2 2006.246.07:56:39.02#ibcon#about to read 3, iclass 7, count 2 2006.246.07:56:39.04#ibcon#read 3, iclass 7, count 2 2006.246.07:56:39.04#ibcon#about to read 4, iclass 7, count 2 2006.246.07:56:39.04#ibcon#read 4, iclass 7, count 2 2006.246.07:56:39.04#ibcon#about to read 5, iclass 7, count 2 2006.246.07:56:39.04#ibcon#read 5, iclass 7, count 2 2006.246.07:56:39.04#ibcon#about to read 6, iclass 7, count 2 2006.246.07:56:39.04#ibcon#read 6, iclass 7, count 2 2006.246.07:56:39.04#ibcon#end of sib2, iclass 7, count 2 2006.246.07:56:39.04#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:56:39.04#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:56:39.04#ibcon#[25=AT04-07\r\n] 2006.246.07:56:39.04#ibcon#*before write, iclass 7, count 2 2006.246.07:56:39.04#ibcon#enter sib2, iclass 7, count 2 2006.246.07:56:39.04#ibcon#flushed, iclass 7, count 2 2006.246.07:56:39.04#ibcon#about to write, iclass 7, count 2 2006.246.07:56:39.04#ibcon#wrote, iclass 7, count 2 2006.246.07:56:39.04#ibcon#about to read 3, iclass 7, count 2 2006.246.07:56:39.07#ibcon#read 3, iclass 7, count 2 2006.246.07:56:39.07#ibcon#about to read 4, iclass 7, count 2 2006.246.07:56:39.07#ibcon#read 4, iclass 7, count 2 2006.246.07:56:39.07#ibcon#about to read 5, iclass 7, count 2 2006.246.07:56:39.07#ibcon#read 5, iclass 7, count 2 2006.246.07:56:39.07#ibcon#about to read 6, iclass 7, count 2 2006.246.07:56:39.07#ibcon#read 6, iclass 7, count 2 2006.246.07:56:39.07#ibcon#end of sib2, iclass 7, count 2 2006.246.07:56:39.07#ibcon#*after write, iclass 7, count 2 2006.246.07:56:39.07#ibcon#*before return 0, iclass 7, count 2 2006.246.07:56:39.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:39.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:39.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:56:39.07#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:39.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:39.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:39.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:39.19#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:56:39.19#ibcon#first serial, iclass 7, count 0 2006.246.07:56:39.19#ibcon#enter sib2, iclass 7, count 0 2006.246.07:56:39.19#ibcon#flushed, iclass 7, count 0 2006.246.07:56:39.19#ibcon#about to write, iclass 7, count 0 2006.246.07:56:39.19#ibcon#wrote, iclass 7, count 0 2006.246.07:56:39.19#ibcon#about to read 3, iclass 7, count 0 2006.246.07:56:39.21#ibcon#read 3, iclass 7, count 0 2006.246.07:56:39.21#ibcon#about to read 4, iclass 7, count 0 2006.246.07:56:39.21#ibcon#read 4, iclass 7, count 0 2006.246.07:56:39.21#ibcon#about to read 5, iclass 7, count 0 2006.246.07:56:39.21#ibcon#read 5, iclass 7, count 0 2006.246.07:56:39.21#ibcon#about to read 6, iclass 7, count 0 2006.246.07:56:39.21#ibcon#read 6, iclass 7, count 0 2006.246.07:56:39.21#ibcon#end of sib2, iclass 7, count 0 2006.246.07:56:39.21#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:56:39.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:56:39.21#ibcon#[25=USB\r\n] 2006.246.07:56:39.21#ibcon#*before write, iclass 7, count 0 2006.246.07:56:39.21#ibcon#enter sib2, iclass 7, count 0 2006.246.07:56:39.21#ibcon#flushed, iclass 7, count 0 2006.246.07:56:39.21#ibcon#about to write, iclass 7, count 0 2006.246.07:56:39.21#ibcon#wrote, iclass 7, count 0 2006.246.07:56:39.21#ibcon#about to read 3, iclass 7, count 0 2006.246.07:56:39.24#ibcon#read 3, iclass 7, count 0 2006.246.07:56:39.24#ibcon#about to read 4, iclass 7, count 0 2006.246.07:56:39.24#ibcon#read 4, iclass 7, count 0 2006.246.07:56:39.24#ibcon#about to read 5, iclass 7, count 0 2006.246.07:56:39.24#ibcon#read 5, iclass 7, count 0 2006.246.07:56:39.24#ibcon#about to read 6, iclass 7, count 0 2006.246.07:56:39.24#ibcon#read 6, iclass 7, count 0 2006.246.07:56:39.24#ibcon#end of sib2, iclass 7, count 0 2006.246.07:56:39.24#ibcon#*after write, iclass 7, count 0 2006.246.07:56:39.24#ibcon#*before return 0, iclass 7, count 0 2006.246.07:56:39.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:39.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:39.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:56:39.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:56:39.24$vc4f8/valo=5,652.99 2006.246.07:56:39.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:56:39.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:56:39.24#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:39.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:39.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:39.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:39.24#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:56:39.24#ibcon#first serial, iclass 11, count 0 2006.246.07:56:39.24#ibcon#enter sib2, iclass 11, count 0 2006.246.07:56:39.24#ibcon#flushed, iclass 11, count 0 2006.246.07:56:39.24#ibcon#about to write, iclass 11, count 0 2006.246.07:56:39.24#ibcon#wrote, iclass 11, count 0 2006.246.07:56:39.24#ibcon#about to read 3, iclass 11, count 0 2006.246.07:56:39.26#ibcon#read 3, iclass 11, count 0 2006.246.07:56:39.26#ibcon#about to read 4, iclass 11, count 0 2006.246.07:56:39.26#ibcon#read 4, iclass 11, count 0 2006.246.07:56:39.26#ibcon#about to read 5, iclass 11, count 0 2006.246.07:56:39.26#ibcon#read 5, iclass 11, count 0 2006.246.07:56:39.26#ibcon#about to read 6, iclass 11, count 0 2006.246.07:56:39.26#ibcon#read 6, iclass 11, count 0 2006.246.07:56:39.26#ibcon#end of sib2, iclass 11, count 0 2006.246.07:56:39.26#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:56:39.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:56:39.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.07:56:39.26#ibcon#*before write, iclass 11, count 0 2006.246.07:56:39.26#ibcon#enter sib2, iclass 11, count 0 2006.246.07:56:39.26#ibcon#flushed, iclass 11, count 0 2006.246.07:56:39.26#ibcon#about to write, iclass 11, count 0 2006.246.07:56:39.26#ibcon#wrote, iclass 11, count 0 2006.246.07:56:39.26#ibcon#about to read 3, iclass 11, count 0 2006.246.07:56:39.30#ibcon#read 3, iclass 11, count 0 2006.246.07:56:39.30#ibcon#about to read 4, iclass 11, count 0 2006.246.07:56:39.30#ibcon#read 4, iclass 11, count 0 2006.246.07:56:39.30#ibcon#about to read 5, iclass 11, count 0 2006.246.07:56:39.30#ibcon#read 5, iclass 11, count 0 2006.246.07:56:39.30#ibcon#about to read 6, iclass 11, count 0 2006.246.07:56:39.30#ibcon#read 6, iclass 11, count 0 2006.246.07:56:39.30#ibcon#end of sib2, iclass 11, count 0 2006.246.07:56:39.30#ibcon#*after write, iclass 11, count 0 2006.246.07:56:39.30#ibcon#*before return 0, iclass 11, count 0 2006.246.07:56:39.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:39.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:39.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:56:39.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:56:39.30$vc4f8/va=5,7 2006.246.07:56:39.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:56:39.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:56:39.30#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:39.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:39.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:39.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:39.36#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:56:39.36#ibcon#first serial, iclass 13, count 2 2006.246.07:56:39.36#ibcon#enter sib2, iclass 13, count 2 2006.246.07:56:39.36#ibcon#flushed, iclass 13, count 2 2006.246.07:56:39.36#ibcon#about to write, iclass 13, count 2 2006.246.07:56:39.36#ibcon#wrote, iclass 13, count 2 2006.246.07:56:39.36#ibcon#about to read 3, iclass 13, count 2 2006.246.07:56:39.38#ibcon#read 3, iclass 13, count 2 2006.246.07:56:39.38#ibcon#about to read 4, iclass 13, count 2 2006.246.07:56:39.38#ibcon#read 4, iclass 13, count 2 2006.246.07:56:39.38#ibcon#about to read 5, iclass 13, count 2 2006.246.07:56:39.38#ibcon#read 5, iclass 13, count 2 2006.246.07:56:39.38#ibcon#about to read 6, iclass 13, count 2 2006.246.07:56:39.38#ibcon#read 6, iclass 13, count 2 2006.246.07:56:39.38#ibcon#end of sib2, iclass 13, count 2 2006.246.07:56:39.38#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:56:39.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:56:39.38#ibcon#[25=AT05-07\r\n] 2006.246.07:56:39.38#ibcon#*before write, iclass 13, count 2 2006.246.07:56:39.38#ibcon#enter sib2, iclass 13, count 2 2006.246.07:56:39.38#ibcon#flushed, iclass 13, count 2 2006.246.07:56:39.38#ibcon#about to write, iclass 13, count 2 2006.246.07:56:39.38#ibcon#wrote, iclass 13, count 2 2006.246.07:56:39.38#ibcon#about to read 3, iclass 13, count 2 2006.246.07:56:39.41#ibcon#read 3, iclass 13, count 2 2006.246.07:56:39.41#ibcon#about to read 4, iclass 13, count 2 2006.246.07:56:39.41#ibcon#read 4, iclass 13, count 2 2006.246.07:56:39.41#ibcon#about to read 5, iclass 13, count 2 2006.246.07:56:39.41#ibcon#read 5, iclass 13, count 2 2006.246.07:56:39.41#ibcon#about to read 6, iclass 13, count 2 2006.246.07:56:39.41#ibcon#read 6, iclass 13, count 2 2006.246.07:56:39.41#ibcon#end of sib2, iclass 13, count 2 2006.246.07:56:39.41#ibcon#*after write, iclass 13, count 2 2006.246.07:56:39.41#ibcon#*before return 0, iclass 13, count 2 2006.246.07:56:39.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:39.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:39.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:56:39.41#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:39.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:39.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:39.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:39.53#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:56:39.53#ibcon#first serial, iclass 13, count 0 2006.246.07:56:39.53#ibcon#enter sib2, iclass 13, count 0 2006.246.07:56:39.53#ibcon#flushed, iclass 13, count 0 2006.246.07:56:39.53#ibcon#about to write, iclass 13, count 0 2006.246.07:56:39.53#ibcon#wrote, iclass 13, count 0 2006.246.07:56:39.53#ibcon#about to read 3, iclass 13, count 0 2006.246.07:56:39.55#ibcon#read 3, iclass 13, count 0 2006.246.07:56:39.55#ibcon#about to read 4, iclass 13, count 0 2006.246.07:56:39.55#ibcon#read 4, iclass 13, count 0 2006.246.07:56:39.55#ibcon#about to read 5, iclass 13, count 0 2006.246.07:56:39.55#ibcon#read 5, iclass 13, count 0 2006.246.07:56:39.55#ibcon#about to read 6, iclass 13, count 0 2006.246.07:56:39.55#ibcon#read 6, iclass 13, count 0 2006.246.07:56:39.55#ibcon#end of sib2, iclass 13, count 0 2006.246.07:56:39.55#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:56:39.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:56:39.55#ibcon#[25=USB\r\n] 2006.246.07:56:39.55#ibcon#*before write, iclass 13, count 0 2006.246.07:56:39.55#ibcon#enter sib2, iclass 13, count 0 2006.246.07:56:39.55#ibcon#flushed, iclass 13, count 0 2006.246.07:56:39.55#ibcon#about to write, iclass 13, count 0 2006.246.07:56:39.55#ibcon#wrote, iclass 13, count 0 2006.246.07:56:39.55#ibcon#about to read 3, iclass 13, count 0 2006.246.07:56:39.58#ibcon#read 3, iclass 13, count 0 2006.246.07:56:39.58#ibcon#about to read 4, iclass 13, count 0 2006.246.07:56:39.58#ibcon#read 4, iclass 13, count 0 2006.246.07:56:39.58#ibcon#about to read 5, iclass 13, count 0 2006.246.07:56:39.58#ibcon#read 5, iclass 13, count 0 2006.246.07:56:39.58#ibcon#about to read 6, iclass 13, count 0 2006.246.07:56:39.58#ibcon#read 6, iclass 13, count 0 2006.246.07:56:39.58#ibcon#end of sib2, iclass 13, count 0 2006.246.07:56:39.58#ibcon#*after write, iclass 13, count 0 2006.246.07:56:39.58#ibcon#*before return 0, iclass 13, count 0 2006.246.07:56:39.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:39.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:39.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:56:39.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:56:39.58$vc4f8/valo=6,772.99 2006.246.07:56:39.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:56:39.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:56:39.58#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:39.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:39.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:39.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:39.58#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:56:39.58#ibcon#first serial, iclass 15, count 0 2006.246.07:56:39.58#ibcon#enter sib2, iclass 15, count 0 2006.246.07:56:39.58#ibcon#flushed, iclass 15, count 0 2006.246.07:56:39.58#ibcon#about to write, iclass 15, count 0 2006.246.07:56:39.58#ibcon#wrote, iclass 15, count 0 2006.246.07:56:39.58#ibcon#about to read 3, iclass 15, count 0 2006.246.07:56:39.61#ibcon#read 3, iclass 15, count 0 2006.246.07:56:39.61#ibcon#about to read 4, iclass 15, count 0 2006.246.07:56:39.61#ibcon#read 4, iclass 15, count 0 2006.246.07:56:39.61#ibcon#about to read 5, iclass 15, count 0 2006.246.07:56:39.61#ibcon#read 5, iclass 15, count 0 2006.246.07:56:39.61#ibcon#about to read 6, iclass 15, count 0 2006.246.07:56:39.61#ibcon#read 6, iclass 15, count 0 2006.246.07:56:39.61#ibcon#end of sib2, iclass 15, count 0 2006.246.07:56:39.61#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:56:39.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:56:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.07:56:39.61#ibcon#*before write, iclass 15, count 0 2006.246.07:56:39.61#ibcon#enter sib2, iclass 15, count 0 2006.246.07:56:39.61#ibcon#flushed, iclass 15, count 0 2006.246.07:56:39.61#ibcon#about to write, iclass 15, count 0 2006.246.07:56:39.61#ibcon#wrote, iclass 15, count 0 2006.246.07:56:39.61#ibcon#about to read 3, iclass 15, count 0 2006.246.07:56:39.65#ibcon#read 3, iclass 15, count 0 2006.246.07:56:39.65#ibcon#about to read 4, iclass 15, count 0 2006.246.07:56:39.65#ibcon#read 4, iclass 15, count 0 2006.246.07:56:39.65#ibcon#about to read 5, iclass 15, count 0 2006.246.07:56:39.65#ibcon#read 5, iclass 15, count 0 2006.246.07:56:39.65#ibcon#about to read 6, iclass 15, count 0 2006.246.07:56:39.65#ibcon#read 6, iclass 15, count 0 2006.246.07:56:39.65#ibcon#end of sib2, iclass 15, count 0 2006.246.07:56:39.65#ibcon#*after write, iclass 15, count 0 2006.246.07:56:39.65#ibcon#*before return 0, iclass 15, count 0 2006.246.07:56:39.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:39.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:39.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:56:39.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:56:39.65$vc4f8/va=6,7 2006.246.07:56:39.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.07:56:39.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.07:56:39.65#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:39.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:56:39.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:56:39.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:56:39.70#ibcon#enter wrdev, iclass 17, count 2 2006.246.07:56:39.70#ibcon#first serial, iclass 17, count 2 2006.246.07:56:39.70#ibcon#enter sib2, iclass 17, count 2 2006.246.07:56:39.70#ibcon#flushed, iclass 17, count 2 2006.246.07:56:39.70#ibcon#about to write, iclass 17, count 2 2006.246.07:56:39.70#ibcon#wrote, iclass 17, count 2 2006.246.07:56:39.70#ibcon#about to read 3, iclass 17, count 2 2006.246.07:56:39.72#ibcon#read 3, iclass 17, count 2 2006.246.07:56:39.72#ibcon#about to read 4, iclass 17, count 2 2006.246.07:56:39.72#ibcon#read 4, iclass 17, count 2 2006.246.07:56:39.72#ibcon#about to read 5, iclass 17, count 2 2006.246.07:56:39.72#ibcon#read 5, iclass 17, count 2 2006.246.07:56:39.72#ibcon#about to read 6, iclass 17, count 2 2006.246.07:56:39.72#ibcon#read 6, iclass 17, count 2 2006.246.07:56:39.72#ibcon#end of sib2, iclass 17, count 2 2006.246.07:56:39.72#ibcon#*mode == 0, iclass 17, count 2 2006.246.07:56:39.72#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.07:56:39.72#ibcon#[25=AT06-07\r\n] 2006.246.07:56:39.72#ibcon#*before write, iclass 17, count 2 2006.246.07:56:39.72#ibcon#enter sib2, iclass 17, count 2 2006.246.07:56:39.72#ibcon#flushed, iclass 17, count 2 2006.246.07:56:39.72#ibcon#about to write, iclass 17, count 2 2006.246.07:56:39.72#ibcon#wrote, iclass 17, count 2 2006.246.07:56:39.72#ibcon#about to read 3, iclass 17, count 2 2006.246.07:56:39.75#ibcon#read 3, iclass 17, count 2 2006.246.07:56:39.75#ibcon#about to read 4, iclass 17, count 2 2006.246.07:56:39.75#ibcon#read 4, iclass 17, count 2 2006.246.07:56:39.75#ibcon#about to read 5, iclass 17, count 2 2006.246.07:56:39.75#ibcon#read 5, iclass 17, count 2 2006.246.07:56:39.75#ibcon#about to read 6, iclass 17, count 2 2006.246.07:56:39.75#ibcon#read 6, iclass 17, count 2 2006.246.07:56:39.75#ibcon#end of sib2, iclass 17, count 2 2006.246.07:56:39.75#ibcon#*after write, iclass 17, count 2 2006.246.07:56:39.75#ibcon#*before return 0, iclass 17, count 2 2006.246.07:56:39.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:56:39.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.07:56:39.75#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.07:56:39.75#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:39.75#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:56:39.87#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:56:39.87#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:56:39.87#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:56:39.87#ibcon#first serial, iclass 17, count 0 2006.246.07:56:39.87#ibcon#enter sib2, iclass 17, count 0 2006.246.07:56:39.87#ibcon#flushed, iclass 17, count 0 2006.246.07:56:39.87#ibcon#about to write, iclass 17, count 0 2006.246.07:56:39.87#ibcon#wrote, iclass 17, count 0 2006.246.07:56:39.87#ibcon#about to read 3, iclass 17, count 0 2006.246.07:56:39.89#ibcon#read 3, iclass 17, count 0 2006.246.07:56:39.89#ibcon#about to read 4, iclass 17, count 0 2006.246.07:56:39.89#ibcon#read 4, iclass 17, count 0 2006.246.07:56:39.89#ibcon#about to read 5, iclass 17, count 0 2006.246.07:56:39.89#ibcon#read 5, iclass 17, count 0 2006.246.07:56:39.89#ibcon#about to read 6, iclass 17, count 0 2006.246.07:56:39.89#ibcon#read 6, iclass 17, count 0 2006.246.07:56:39.89#ibcon#end of sib2, iclass 17, count 0 2006.246.07:56:39.89#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:56:39.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:56:39.89#ibcon#[25=USB\r\n] 2006.246.07:56:39.89#ibcon#*before write, iclass 17, count 0 2006.246.07:56:39.89#ibcon#enter sib2, iclass 17, count 0 2006.246.07:56:39.89#ibcon#flushed, iclass 17, count 0 2006.246.07:56:39.89#ibcon#about to write, iclass 17, count 0 2006.246.07:56:39.89#ibcon#wrote, iclass 17, count 0 2006.246.07:56:39.89#ibcon#about to read 3, iclass 17, count 0 2006.246.07:56:39.92#ibcon#read 3, iclass 17, count 0 2006.246.07:56:39.92#ibcon#about to read 4, iclass 17, count 0 2006.246.07:56:39.92#ibcon#read 4, iclass 17, count 0 2006.246.07:56:39.92#ibcon#about to read 5, iclass 17, count 0 2006.246.07:56:39.92#ibcon#read 5, iclass 17, count 0 2006.246.07:56:39.92#ibcon#about to read 6, iclass 17, count 0 2006.246.07:56:39.92#ibcon#read 6, iclass 17, count 0 2006.246.07:56:39.92#ibcon#end of sib2, iclass 17, count 0 2006.246.07:56:39.92#ibcon#*after write, iclass 17, count 0 2006.246.07:56:39.92#ibcon#*before return 0, iclass 17, count 0 2006.246.07:56:39.92#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:56:39.92#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.07:56:39.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:56:39.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:56:39.92$vc4f8/valo=7,832.99 2006.246.07:56:39.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.07:56:39.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.07:56:39.92#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:39.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:56:39.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:56:39.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:56:39.92#ibcon#enter wrdev, iclass 19, count 0 2006.246.07:56:39.92#ibcon#first serial, iclass 19, count 0 2006.246.07:56:39.92#ibcon#enter sib2, iclass 19, count 0 2006.246.07:56:39.92#ibcon#flushed, iclass 19, count 0 2006.246.07:56:39.92#ibcon#about to write, iclass 19, count 0 2006.246.07:56:39.92#ibcon#wrote, iclass 19, count 0 2006.246.07:56:39.92#ibcon#about to read 3, iclass 19, count 0 2006.246.07:56:39.94#ibcon#read 3, iclass 19, count 0 2006.246.07:56:39.94#ibcon#about to read 4, iclass 19, count 0 2006.246.07:56:39.94#ibcon#read 4, iclass 19, count 0 2006.246.07:56:39.94#ibcon#about to read 5, iclass 19, count 0 2006.246.07:56:39.94#ibcon#read 5, iclass 19, count 0 2006.246.07:56:39.94#ibcon#about to read 6, iclass 19, count 0 2006.246.07:56:39.94#ibcon#read 6, iclass 19, count 0 2006.246.07:56:39.94#ibcon#end of sib2, iclass 19, count 0 2006.246.07:56:39.94#ibcon#*mode == 0, iclass 19, count 0 2006.246.07:56:39.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.07:56:39.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.07:56:39.94#ibcon#*before write, iclass 19, count 0 2006.246.07:56:39.94#ibcon#enter sib2, iclass 19, count 0 2006.246.07:56:39.94#ibcon#flushed, iclass 19, count 0 2006.246.07:56:39.94#ibcon#about to write, iclass 19, count 0 2006.246.07:56:39.94#ibcon#wrote, iclass 19, count 0 2006.246.07:56:39.94#ibcon#about to read 3, iclass 19, count 0 2006.246.07:56:39.98#ibcon#read 3, iclass 19, count 0 2006.246.07:56:39.98#ibcon#about to read 4, iclass 19, count 0 2006.246.07:56:39.98#ibcon#read 4, iclass 19, count 0 2006.246.07:56:39.98#ibcon#about to read 5, iclass 19, count 0 2006.246.07:56:39.98#ibcon#read 5, iclass 19, count 0 2006.246.07:56:39.98#ibcon#about to read 6, iclass 19, count 0 2006.246.07:56:39.98#ibcon#read 6, iclass 19, count 0 2006.246.07:56:39.98#ibcon#end of sib2, iclass 19, count 0 2006.246.07:56:39.98#ibcon#*after write, iclass 19, count 0 2006.246.07:56:39.98#ibcon#*before return 0, iclass 19, count 0 2006.246.07:56:39.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:56:39.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.07:56:39.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.07:56:39.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.07:56:39.98$vc4f8/va=7,7 2006.246.07:56:39.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.07:56:39.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.07:56:39.98#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:39.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:56:40.04#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:56:40.04#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:56:40.04#ibcon#enter wrdev, iclass 21, count 2 2006.246.07:56:40.04#ibcon#first serial, iclass 21, count 2 2006.246.07:56:40.04#ibcon#enter sib2, iclass 21, count 2 2006.246.07:56:40.04#ibcon#flushed, iclass 21, count 2 2006.246.07:56:40.04#ibcon#about to write, iclass 21, count 2 2006.246.07:56:40.04#ibcon#wrote, iclass 21, count 2 2006.246.07:56:40.04#ibcon#about to read 3, iclass 21, count 2 2006.246.07:56:40.06#ibcon#read 3, iclass 21, count 2 2006.246.07:56:40.06#ibcon#about to read 4, iclass 21, count 2 2006.246.07:56:40.06#ibcon#read 4, iclass 21, count 2 2006.246.07:56:40.06#ibcon#about to read 5, iclass 21, count 2 2006.246.07:56:40.06#ibcon#read 5, iclass 21, count 2 2006.246.07:56:40.06#ibcon#about to read 6, iclass 21, count 2 2006.246.07:56:40.06#ibcon#read 6, iclass 21, count 2 2006.246.07:56:40.06#ibcon#end of sib2, iclass 21, count 2 2006.246.07:56:40.06#ibcon#*mode == 0, iclass 21, count 2 2006.246.07:56:40.06#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.07:56:40.06#ibcon#[25=AT07-07\r\n] 2006.246.07:56:40.06#ibcon#*before write, iclass 21, count 2 2006.246.07:56:40.06#ibcon#enter sib2, iclass 21, count 2 2006.246.07:56:40.06#ibcon#flushed, iclass 21, count 2 2006.246.07:56:40.06#ibcon#about to write, iclass 21, count 2 2006.246.07:56:40.06#ibcon#wrote, iclass 21, count 2 2006.246.07:56:40.06#ibcon#about to read 3, iclass 21, count 2 2006.246.07:56:40.09#ibcon#read 3, iclass 21, count 2 2006.246.07:56:40.09#ibcon#about to read 4, iclass 21, count 2 2006.246.07:56:40.09#ibcon#read 4, iclass 21, count 2 2006.246.07:56:40.09#ibcon#about to read 5, iclass 21, count 2 2006.246.07:56:40.09#ibcon#read 5, iclass 21, count 2 2006.246.07:56:40.09#ibcon#about to read 6, iclass 21, count 2 2006.246.07:56:40.09#ibcon#read 6, iclass 21, count 2 2006.246.07:56:40.09#ibcon#end of sib2, iclass 21, count 2 2006.246.07:56:40.09#ibcon#*after write, iclass 21, count 2 2006.246.07:56:40.09#ibcon#*before return 0, iclass 21, count 2 2006.246.07:56:40.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:56:40.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.07:56:40.09#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.07:56:40.09#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:40.09#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:56:40.21#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:56:40.21#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:56:40.21#ibcon#enter wrdev, iclass 21, count 0 2006.246.07:56:40.21#ibcon#first serial, iclass 21, count 0 2006.246.07:56:40.21#ibcon#enter sib2, iclass 21, count 0 2006.246.07:56:40.21#ibcon#flushed, iclass 21, count 0 2006.246.07:56:40.21#ibcon#about to write, iclass 21, count 0 2006.246.07:56:40.21#ibcon#wrote, iclass 21, count 0 2006.246.07:56:40.21#ibcon#about to read 3, iclass 21, count 0 2006.246.07:56:40.23#ibcon#read 3, iclass 21, count 0 2006.246.07:56:40.23#ibcon#about to read 4, iclass 21, count 0 2006.246.07:56:40.23#ibcon#read 4, iclass 21, count 0 2006.246.07:56:40.23#ibcon#about to read 5, iclass 21, count 0 2006.246.07:56:40.23#ibcon#read 5, iclass 21, count 0 2006.246.07:56:40.23#ibcon#about to read 6, iclass 21, count 0 2006.246.07:56:40.23#ibcon#read 6, iclass 21, count 0 2006.246.07:56:40.23#ibcon#end of sib2, iclass 21, count 0 2006.246.07:56:40.23#ibcon#*mode == 0, iclass 21, count 0 2006.246.07:56:40.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.07:56:40.23#ibcon#[25=USB\r\n] 2006.246.07:56:40.23#ibcon#*before write, iclass 21, count 0 2006.246.07:56:40.23#ibcon#enter sib2, iclass 21, count 0 2006.246.07:56:40.23#ibcon#flushed, iclass 21, count 0 2006.246.07:56:40.23#ibcon#about to write, iclass 21, count 0 2006.246.07:56:40.23#ibcon#wrote, iclass 21, count 0 2006.246.07:56:40.23#ibcon#about to read 3, iclass 21, count 0 2006.246.07:56:40.26#ibcon#read 3, iclass 21, count 0 2006.246.07:56:40.26#ibcon#about to read 4, iclass 21, count 0 2006.246.07:56:40.26#ibcon#read 4, iclass 21, count 0 2006.246.07:56:40.26#ibcon#about to read 5, iclass 21, count 0 2006.246.07:56:40.26#ibcon#read 5, iclass 21, count 0 2006.246.07:56:40.26#ibcon#about to read 6, iclass 21, count 0 2006.246.07:56:40.26#ibcon#read 6, iclass 21, count 0 2006.246.07:56:40.26#ibcon#end of sib2, iclass 21, count 0 2006.246.07:56:40.26#ibcon#*after write, iclass 21, count 0 2006.246.07:56:40.26#ibcon#*before return 0, iclass 21, count 0 2006.246.07:56:40.26#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:56:40.26#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.07:56:40.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.07:56:40.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.07:56:40.26$vc4f8/valo=8,852.99 2006.246.07:56:40.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.07:56:40.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.07:56:40.26#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:40.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:56:40.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:56:40.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:56:40.26#ibcon#enter wrdev, iclass 23, count 0 2006.246.07:56:40.26#ibcon#first serial, iclass 23, count 0 2006.246.07:56:40.26#ibcon#enter sib2, iclass 23, count 0 2006.246.07:56:40.26#ibcon#flushed, iclass 23, count 0 2006.246.07:56:40.26#ibcon#about to write, iclass 23, count 0 2006.246.07:56:40.26#ibcon#wrote, iclass 23, count 0 2006.246.07:56:40.26#ibcon#about to read 3, iclass 23, count 0 2006.246.07:56:40.28#ibcon#read 3, iclass 23, count 0 2006.246.07:56:40.28#ibcon#about to read 4, iclass 23, count 0 2006.246.07:56:40.28#ibcon#read 4, iclass 23, count 0 2006.246.07:56:40.28#ibcon#about to read 5, iclass 23, count 0 2006.246.07:56:40.28#ibcon#read 5, iclass 23, count 0 2006.246.07:56:40.28#ibcon#about to read 6, iclass 23, count 0 2006.246.07:56:40.28#ibcon#read 6, iclass 23, count 0 2006.246.07:56:40.28#ibcon#end of sib2, iclass 23, count 0 2006.246.07:56:40.28#ibcon#*mode == 0, iclass 23, count 0 2006.246.07:56:40.28#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.07:56:40.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.07:56:40.28#ibcon#*before write, iclass 23, count 0 2006.246.07:56:40.28#ibcon#enter sib2, iclass 23, count 0 2006.246.07:56:40.28#ibcon#flushed, iclass 23, count 0 2006.246.07:56:40.28#ibcon#about to write, iclass 23, count 0 2006.246.07:56:40.28#ibcon#wrote, iclass 23, count 0 2006.246.07:56:40.28#ibcon#about to read 3, iclass 23, count 0 2006.246.07:56:40.32#ibcon#read 3, iclass 23, count 0 2006.246.07:56:40.32#ibcon#about to read 4, iclass 23, count 0 2006.246.07:56:40.32#ibcon#read 4, iclass 23, count 0 2006.246.07:56:40.32#ibcon#about to read 5, iclass 23, count 0 2006.246.07:56:40.32#ibcon#read 5, iclass 23, count 0 2006.246.07:56:40.32#ibcon#about to read 6, iclass 23, count 0 2006.246.07:56:40.32#ibcon#read 6, iclass 23, count 0 2006.246.07:56:40.32#ibcon#end of sib2, iclass 23, count 0 2006.246.07:56:40.32#ibcon#*after write, iclass 23, count 0 2006.246.07:56:40.32#ibcon#*before return 0, iclass 23, count 0 2006.246.07:56:40.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:56:40.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.07:56:40.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.07:56:40.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.07:56:40.32$vc4f8/va=8,8 2006.246.07:56:40.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.07:56:40.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.07:56:40.32#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:40.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:56:40.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:56:40.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:56:40.38#ibcon#enter wrdev, iclass 25, count 2 2006.246.07:56:40.38#ibcon#first serial, iclass 25, count 2 2006.246.07:56:40.38#ibcon#enter sib2, iclass 25, count 2 2006.246.07:56:40.38#ibcon#flushed, iclass 25, count 2 2006.246.07:56:40.38#ibcon#about to write, iclass 25, count 2 2006.246.07:56:40.38#ibcon#wrote, iclass 25, count 2 2006.246.07:56:40.38#ibcon#about to read 3, iclass 25, count 2 2006.246.07:56:40.40#ibcon#read 3, iclass 25, count 2 2006.246.07:56:40.40#ibcon#about to read 4, iclass 25, count 2 2006.246.07:56:40.40#ibcon#read 4, iclass 25, count 2 2006.246.07:56:40.40#ibcon#about to read 5, iclass 25, count 2 2006.246.07:56:40.40#ibcon#read 5, iclass 25, count 2 2006.246.07:56:40.40#ibcon#about to read 6, iclass 25, count 2 2006.246.07:56:40.40#ibcon#read 6, iclass 25, count 2 2006.246.07:56:40.40#ibcon#end of sib2, iclass 25, count 2 2006.246.07:56:40.40#ibcon#*mode == 0, iclass 25, count 2 2006.246.07:56:40.40#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.07:56:40.40#ibcon#[25=AT08-08\r\n] 2006.246.07:56:40.40#ibcon#*before write, iclass 25, count 2 2006.246.07:56:40.40#ibcon#enter sib2, iclass 25, count 2 2006.246.07:56:40.40#ibcon#flushed, iclass 25, count 2 2006.246.07:56:40.40#ibcon#about to write, iclass 25, count 2 2006.246.07:56:40.40#ibcon#wrote, iclass 25, count 2 2006.246.07:56:40.40#ibcon#about to read 3, iclass 25, count 2 2006.246.07:56:40.43#ibcon#read 3, iclass 25, count 2 2006.246.07:56:40.43#ibcon#about to read 4, iclass 25, count 2 2006.246.07:56:40.43#ibcon#read 4, iclass 25, count 2 2006.246.07:56:40.43#ibcon#about to read 5, iclass 25, count 2 2006.246.07:56:40.43#ibcon#read 5, iclass 25, count 2 2006.246.07:56:40.43#ibcon#about to read 6, iclass 25, count 2 2006.246.07:56:40.43#ibcon#read 6, iclass 25, count 2 2006.246.07:56:40.43#ibcon#end of sib2, iclass 25, count 2 2006.246.07:56:40.43#ibcon#*after write, iclass 25, count 2 2006.246.07:56:40.43#ibcon#*before return 0, iclass 25, count 2 2006.246.07:56:40.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:56:40.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.07:56:40.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.07:56:40.43#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:40.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:56:40.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:56:40.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:56:40.55#ibcon#enter wrdev, iclass 25, count 0 2006.246.07:56:40.55#ibcon#first serial, iclass 25, count 0 2006.246.07:56:40.55#ibcon#enter sib2, iclass 25, count 0 2006.246.07:56:40.55#ibcon#flushed, iclass 25, count 0 2006.246.07:56:40.55#ibcon#about to write, iclass 25, count 0 2006.246.07:56:40.55#ibcon#wrote, iclass 25, count 0 2006.246.07:56:40.55#ibcon#about to read 3, iclass 25, count 0 2006.246.07:56:40.57#ibcon#read 3, iclass 25, count 0 2006.246.07:56:40.57#ibcon#about to read 4, iclass 25, count 0 2006.246.07:56:40.57#ibcon#read 4, iclass 25, count 0 2006.246.07:56:40.57#ibcon#about to read 5, iclass 25, count 0 2006.246.07:56:40.57#ibcon#read 5, iclass 25, count 0 2006.246.07:56:40.57#ibcon#about to read 6, iclass 25, count 0 2006.246.07:56:40.57#ibcon#read 6, iclass 25, count 0 2006.246.07:56:40.57#ibcon#end of sib2, iclass 25, count 0 2006.246.07:56:40.57#ibcon#*mode == 0, iclass 25, count 0 2006.246.07:56:40.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.07:56:40.57#ibcon#[25=USB\r\n] 2006.246.07:56:40.57#ibcon#*before write, iclass 25, count 0 2006.246.07:56:40.57#ibcon#enter sib2, iclass 25, count 0 2006.246.07:56:40.57#ibcon#flushed, iclass 25, count 0 2006.246.07:56:40.57#ibcon#about to write, iclass 25, count 0 2006.246.07:56:40.57#ibcon#wrote, iclass 25, count 0 2006.246.07:56:40.57#ibcon#about to read 3, iclass 25, count 0 2006.246.07:56:40.60#ibcon#read 3, iclass 25, count 0 2006.246.07:56:40.60#ibcon#about to read 4, iclass 25, count 0 2006.246.07:56:40.60#ibcon#read 4, iclass 25, count 0 2006.246.07:56:40.60#ibcon#about to read 5, iclass 25, count 0 2006.246.07:56:40.60#ibcon#read 5, iclass 25, count 0 2006.246.07:56:40.60#ibcon#about to read 6, iclass 25, count 0 2006.246.07:56:40.60#ibcon#read 6, iclass 25, count 0 2006.246.07:56:40.60#ibcon#end of sib2, iclass 25, count 0 2006.246.07:56:40.60#ibcon#*after write, iclass 25, count 0 2006.246.07:56:40.60#ibcon#*before return 0, iclass 25, count 0 2006.246.07:56:40.60#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:56:40.60#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.07:56:40.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.07:56:40.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.07:56:40.60$vc4f8/vblo=1,632.99 2006.246.07:56:40.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.07:56:40.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.07:56:40.60#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:40.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:56:40.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:56:40.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:56:40.60#ibcon#enter wrdev, iclass 27, count 0 2006.246.07:56:40.60#ibcon#first serial, iclass 27, count 0 2006.246.07:56:40.60#ibcon#enter sib2, iclass 27, count 0 2006.246.07:56:40.60#ibcon#flushed, iclass 27, count 0 2006.246.07:56:40.60#ibcon#about to write, iclass 27, count 0 2006.246.07:56:40.60#ibcon#wrote, iclass 27, count 0 2006.246.07:56:40.60#ibcon#about to read 3, iclass 27, count 0 2006.246.07:56:40.62#ibcon#read 3, iclass 27, count 0 2006.246.07:56:40.62#ibcon#about to read 4, iclass 27, count 0 2006.246.07:56:40.62#ibcon#read 4, iclass 27, count 0 2006.246.07:56:40.62#ibcon#about to read 5, iclass 27, count 0 2006.246.07:56:40.62#ibcon#read 5, iclass 27, count 0 2006.246.07:56:40.62#ibcon#about to read 6, iclass 27, count 0 2006.246.07:56:40.62#ibcon#read 6, iclass 27, count 0 2006.246.07:56:40.62#ibcon#end of sib2, iclass 27, count 0 2006.246.07:56:40.62#ibcon#*mode == 0, iclass 27, count 0 2006.246.07:56:40.62#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.07:56:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.07:56:40.62#ibcon#*before write, iclass 27, count 0 2006.246.07:56:40.62#ibcon#enter sib2, iclass 27, count 0 2006.246.07:56:40.62#ibcon#flushed, iclass 27, count 0 2006.246.07:56:40.62#ibcon#about to write, iclass 27, count 0 2006.246.07:56:40.62#ibcon#wrote, iclass 27, count 0 2006.246.07:56:40.62#ibcon#about to read 3, iclass 27, count 0 2006.246.07:56:40.66#ibcon#read 3, iclass 27, count 0 2006.246.07:56:40.66#ibcon#about to read 4, iclass 27, count 0 2006.246.07:56:40.66#ibcon#read 4, iclass 27, count 0 2006.246.07:56:40.66#ibcon#about to read 5, iclass 27, count 0 2006.246.07:56:40.66#ibcon#read 5, iclass 27, count 0 2006.246.07:56:40.66#ibcon#about to read 6, iclass 27, count 0 2006.246.07:56:40.66#ibcon#read 6, iclass 27, count 0 2006.246.07:56:40.66#ibcon#end of sib2, iclass 27, count 0 2006.246.07:56:40.66#ibcon#*after write, iclass 27, count 0 2006.246.07:56:40.66#ibcon#*before return 0, iclass 27, count 0 2006.246.07:56:40.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:56:40.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.07:56:40.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.07:56:40.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.07:56:40.66$vc4f8/vb=1,4 2006.246.07:56:40.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.07:56:40.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.07:56:40.66#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:40.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:56:40.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:56:40.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:56:40.66#ibcon#enter wrdev, iclass 29, count 2 2006.246.07:56:40.66#ibcon#first serial, iclass 29, count 2 2006.246.07:56:40.66#ibcon#enter sib2, iclass 29, count 2 2006.246.07:56:40.66#ibcon#flushed, iclass 29, count 2 2006.246.07:56:40.66#ibcon#about to write, iclass 29, count 2 2006.246.07:56:40.66#ibcon#wrote, iclass 29, count 2 2006.246.07:56:40.66#ibcon#about to read 3, iclass 29, count 2 2006.246.07:56:40.68#ibcon#read 3, iclass 29, count 2 2006.246.07:56:40.68#ibcon#about to read 4, iclass 29, count 2 2006.246.07:56:40.68#ibcon#read 4, iclass 29, count 2 2006.246.07:56:40.68#ibcon#about to read 5, iclass 29, count 2 2006.246.07:56:40.68#ibcon#read 5, iclass 29, count 2 2006.246.07:56:40.68#ibcon#about to read 6, iclass 29, count 2 2006.246.07:56:40.68#ibcon#read 6, iclass 29, count 2 2006.246.07:56:40.68#ibcon#end of sib2, iclass 29, count 2 2006.246.07:56:40.68#ibcon#*mode == 0, iclass 29, count 2 2006.246.07:56:40.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.07:56:40.68#ibcon#[27=AT01-04\r\n] 2006.246.07:56:40.68#ibcon#*before write, iclass 29, count 2 2006.246.07:56:40.68#ibcon#enter sib2, iclass 29, count 2 2006.246.07:56:40.68#ibcon#flushed, iclass 29, count 2 2006.246.07:56:40.68#ibcon#about to write, iclass 29, count 2 2006.246.07:56:40.68#ibcon#wrote, iclass 29, count 2 2006.246.07:56:40.68#ibcon#about to read 3, iclass 29, count 2 2006.246.07:56:40.71#ibcon#read 3, iclass 29, count 2 2006.246.07:56:40.71#ibcon#about to read 4, iclass 29, count 2 2006.246.07:56:40.71#ibcon#read 4, iclass 29, count 2 2006.246.07:56:40.71#ibcon#about to read 5, iclass 29, count 2 2006.246.07:56:40.71#ibcon#read 5, iclass 29, count 2 2006.246.07:56:40.71#ibcon#about to read 6, iclass 29, count 2 2006.246.07:56:40.71#ibcon#read 6, iclass 29, count 2 2006.246.07:56:40.71#ibcon#end of sib2, iclass 29, count 2 2006.246.07:56:40.71#ibcon#*after write, iclass 29, count 2 2006.246.07:56:40.71#ibcon#*before return 0, iclass 29, count 2 2006.246.07:56:40.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:56:40.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.07:56:40.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.07:56:40.71#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:40.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:56:40.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:56:40.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:56:40.83#ibcon#enter wrdev, iclass 29, count 0 2006.246.07:56:40.83#ibcon#first serial, iclass 29, count 0 2006.246.07:56:40.83#ibcon#enter sib2, iclass 29, count 0 2006.246.07:56:40.83#ibcon#flushed, iclass 29, count 0 2006.246.07:56:40.83#ibcon#about to write, iclass 29, count 0 2006.246.07:56:40.83#ibcon#wrote, iclass 29, count 0 2006.246.07:56:40.83#ibcon#about to read 3, iclass 29, count 0 2006.246.07:56:40.85#ibcon#read 3, iclass 29, count 0 2006.246.07:56:40.85#ibcon#about to read 4, iclass 29, count 0 2006.246.07:56:40.85#ibcon#read 4, iclass 29, count 0 2006.246.07:56:40.85#ibcon#about to read 5, iclass 29, count 0 2006.246.07:56:40.85#ibcon#read 5, iclass 29, count 0 2006.246.07:56:40.85#ibcon#about to read 6, iclass 29, count 0 2006.246.07:56:40.85#ibcon#read 6, iclass 29, count 0 2006.246.07:56:40.85#ibcon#end of sib2, iclass 29, count 0 2006.246.07:56:40.85#ibcon#*mode == 0, iclass 29, count 0 2006.246.07:56:40.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.07:56:40.85#ibcon#[27=USB\r\n] 2006.246.07:56:40.85#ibcon#*before write, iclass 29, count 0 2006.246.07:56:40.85#ibcon#enter sib2, iclass 29, count 0 2006.246.07:56:40.85#ibcon#flushed, iclass 29, count 0 2006.246.07:56:40.85#ibcon#about to write, iclass 29, count 0 2006.246.07:56:40.85#ibcon#wrote, iclass 29, count 0 2006.246.07:56:40.85#ibcon#about to read 3, iclass 29, count 0 2006.246.07:56:40.88#ibcon#read 3, iclass 29, count 0 2006.246.07:56:40.88#ibcon#about to read 4, iclass 29, count 0 2006.246.07:56:40.88#ibcon#read 4, iclass 29, count 0 2006.246.07:56:40.88#ibcon#about to read 5, iclass 29, count 0 2006.246.07:56:40.88#ibcon#read 5, iclass 29, count 0 2006.246.07:56:40.88#ibcon#about to read 6, iclass 29, count 0 2006.246.07:56:40.88#ibcon#read 6, iclass 29, count 0 2006.246.07:56:40.88#ibcon#end of sib2, iclass 29, count 0 2006.246.07:56:40.88#ibcon#*after write, iclass 29, count 0 2006.246.07:56:40.88#ibcon#*before return 0, iclass 29, count 0 2006.246.07:56:40.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:56:40.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.07:56:40.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.07:56:40.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.07:56:40.88$vc4f8/vblo=2,640.99 2006.246.07:56:40.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.07:56:40.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.07:56:40.88#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:40.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:40.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:40.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:40.88#ibcon#enter wrdev, iclass 31, count 0 2006.246.07:56:40.88#ibcon#first serial, iclass 31, count 0 2006.246.07:56:40.88#ibcon#enter sib2, iclass 31, count 0 2006.246.07:56:40.88#ibcon#flushed, iclass 31, count 0 2006.246.07:56:40.88#ibcon#about to write, iclass 31, count 0 2006.246.07:56:40.88#ibcon#wrote, iclass 31, count 0 2006.246.07:56:40.88#ibcon#about to read 3, iclass 31, count 0 2006.246.07:56:40.90#ibcon#read 3, iclass 31, count 0 2006.246.07:56:40.90#ibcon#about to read 4, iclass 31, count 0 2006.246.07:56:40.90#ibcon#read 4, iclass 31, count 0 2006.246.07:56:40.90#ibcon#about to read 5, iclass 31, count 0 2006.246.07:56:40.90#ibcon#read 5, iclass 31, count 0 2006.246.07:56:40.90#ibcon#about to read 6, iclass 31, count 0 2006.246.07:56:40.90#ibcon#read 6, iclass 31, count 0 2006.246.07:56:40.90#ibcon#end of sib2, iclass 31, count 0 2006.246.07:56:40.90#ibcon#*mode == 0, iclass 31, count 0 2006.246.07:56:40.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.07:56:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.07:56:40.90#ibcon#*before write, iclass 31, count 0 2006.246.07:56:40.90#ibcon#enter sib2, iclass 31, count 0 2006.246.07:56:40.90#ibcon#flushed, iclass 31, count 0 2006.246.07:56:40.90#ibcon#about to write, iclass 31, count 0 2006.246.07:56:40.90#ibcon#wrote, iclass 31, count 0 2006.246.07:56:40.90#ibcon#about to read 3, iclass 31, count 0 2006.246.07:56:40.94#ibcon#read 3, iclass 31, count 0 2006.246.07:56:40.94#ibcon#about to read 4, iclass 31, count 0 2006.246.07:56:40.94#ibcon#read 4, iclass 31, count 0 2006.246.07:56:40.94#ibcon#about to read 5, iclass 31, count 0 2006.246.07:56:40.94#ibcon#read 5, iclass 31, count 0 2006.246.07:56:40.94#ibcon#about to read 6, iclass 31, count 0 2006.246.07:56:40.94#ibcon#read 6, iclass 31, count 0 2006.246.07:56:40.94#ibcon#end of sib2, iclass 31, count 0 2006.246.07:56:40.94#ibcon#*after write, iclass 31, count 0 2006.246.07:56:40.94#ibcon#*before return 0, iclass 31, count 0 2006.246.07:56:40.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:40.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.07:56:40.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.07:56:40.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.07:56:40.94$vc4f8/vb=2,4 2006.246.07:56:40.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.07:56:40.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.07:56:40.94#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:40.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:41.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:41.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:41.00#ibcon#enter wrdev, iclass 33, count 2 2006.246.07:56:41.00#ibcon#first serial, iclass 33, count 2 2006.246.07:56:41.00#ibcon#enter sib2, iclass 33, count 2 2006.246.07:56:41.00#ibcon#flushed, iclass 33, count 2 2006.246.07:56:41.00#ibcon#about to write, iclass 33, count 2 2006.246.07:56:41.00#ibcon#wrote, iclass 33, count 2 2006.246.07:56:41.00#ibcon#about to read 3, iclass 33, count 2 2006.246.07:56:41.02#ibcon#read 3, iclass 33, count 2 2006.246.07:56:41.02#ibcon#about to read 4, iclass 33, count 2 2006.246.07:56:41.02#ibcon#read 4, iclass 33, count 2 2006.246.07:56:41.02#ibcon#about to read 5, iclass 33, count 2 2006.246.07:56:41.02#ibcon#read 5, iclass 33, count 2 2006.246.07:56:41.02#ibcon#about to read 6, iclass 33, count 2 2006.246.07:56:41.02#ibcon#read 6, iclass 33, count 2 2006.246.07:56:41.02#ibcon#end of sib2, iclass 33, count 2 2006.246.07:56:41.02#ibcon#*mode == 0, iclass 33, count 2 2006.246.07:56:41.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.07:56:41.02#ibcon#[27=AT02-04\r\n] 2006.246.07:56:41.02#ibcon#*before write, iclass 33, count 2 2006.246.07:56:41.02#ibcon#enter sib2, iclass 33, count 2 2006.246.07:56:41.02#ibcon#flushed, iclass 33, count 2 2006.246.07:56:41.02#ibcon#about to write, iclass 33, count 2 2006.246.07:56:41.02#ibcon#wrote, iclass 33, count 2 2006.246.07:56:41.02#ibcon#about to read 3, iclass 33, count 2 2006.246.07:56:41.05#ibcon#read 3, iclass 33, count 2 2006.246.07:56:41.05#ibcon#about to read 4, iclass 33, count 2 2006.246.07:56:41.05#ibcon#read 4, iclass 33, count 2 2006.246.07:56:41.05#ibcon#about to read 5, iclass 33, count 2 2006.246.07:56:41.05#ibcon#read 5, iclass 33, count 2 2006.246.07:56:41.05#ibcon#about to read 6, iclass 33, count 2 2006.246.07:56:41.05#ibcon#read 6, iclass 33, count 2 2006.246.07:56:41.05#ibcon#end of sib2, iclass 33, count 2 2006.246.07:56:41.05#ibcon#*after write, iclass 33, count 2 2006.246.07:56:41.05#ibcon#*before return 0, iclass 33, count 2 2006.246.07:56:41.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:41.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.07:56:41.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.07:56:41.05#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:41.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:41.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:41.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:41.17#ibcon#enter wrdev, iclass 33, count 0 2006.246.07:56:41.17#ibcon#first serial, iclass 33, count 0 2006.246.07:56:41.17#ibcon#enter sib2, iclass 33, count 0 2006.246.07:56:41.17#ibcon#flushed, iclass 33, count 0 2006.246.07:56:41.17#ibcon#about to write, iclass 33, count 0 2006.246.07:56:41.17#ibcon#wrote, iclass 33, count 0 2006.246.07:56:41.17#ibcon#about to read 3, iclass 33, count 0 2006.246.07:56:41.20#ibcon#read 3, iclass 33, count 0 2006.246.07:56:41.20#ibcon#about to read 4, iclass 33, count 0 2006.246.07:56:41.20#ibcon#read 4, iclass 33, count 0 2006.246.07:56:41.20#ibcon#about to read 5, iclass 33, count 0 2006.246.07:56:41.20#ibcon#read 5, iclass 33, count 0 2006.246.07:56:41.20#ibcon#about to read 6, iclass 33, count 0 2006.246.07:56:41.20#ibcon#read 6, iclass 33, count 0 2006.246.07:56:41.20#ibcon#end of sib2, iclass 33, count 0 2006.246.07:56:41.20#ibcon#*mode == 0, iclass 33, count 0 2006.246.07:56:41.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.07:56:41.20#ibcon#[27=USB\r\n] 2006.246.07:56:41.20#ibcon#*before write, iclass 33, count 0 2006.246.07:56:41.20#ibcon#enter sib2, iclass 33, count 0 2006.246.07:56:41.20#ibcon#flushed, iclass 33, count 0 2006.246.07:56:41.20#ibcon#about to write, iclass 33, count 0 2006.246.07:56:41.20#ibcon#wrote, iclass 33, count 0 2006.246.07:56:41.20#ibcon#about to read 3, iclass 33, count 0 2006.246.07:56:41.23#ibcon#read 3, iclass 33, count 0 2006.246.07:56:41.23#ibcon#about to read 4, iclass 33, count 0 2006.246.07:56:41.23#ibcon#read 4, iclass 33, count 0 2006.246.07:56:41.23#ibcon#about to read 5, iclass 33, count 0 2006.246.07:56:41.23#ibcon#read 5, iclass 33, count 0 2006.246.07:56:41.23#ibcon#about to read 6, iclass 33, count 0 2006.246.07:56:41.23#ibcon#read 6, iclass 33, count 0 2006.246.07:56:41.23#ibcon#end of sib2, iclass 33, count 0 2006.246.07:56:41.23#ibcon#*after write, iclass 33, count 0 2006.246.07:56:41.23#ibcon#*before return 0, iclass 33, count 0 2006.246.07:56:41.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:41.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.07:56:41.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.07:56:41.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.07:56:41.23$vc4f8/vblo=3,656.99 2006.246.07:56:41.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.07:56:41.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.07:56:41.23#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:41.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:41.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:41.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:41.23#ibcon#enter wrdev, iclass 35, count 0 2006.246.07:56:41.23#ibcon#first serial, iclass 35, count 0 2006.246.07:56:41.23#ibcon#enter sib2, iclass 35, count 0 2006.246.07:56:41.23#ibcon#flushed, iclass 35, count 0 2006.246.07:56:41.23#ibcon#about to write, iclass 35, count 0 2006.246.07:56:41.23#ibcon#wrote, iclass 35, count 0 2006.246.07:56:41.23#ibcon#about to read 3, iclass 35, count 0 2006.246.07:56:41.25#ibcon#read 3, iclass 35, count 0 2006.246.07:56:41.25#ibcon#about to read 4, iclass 35, count 0 2006.246.07:56:41.25#ibcon#read 4, iclass 35, count 0 2006.246.07:56:41.25#ibcon#about to read 5, iclass 35, count 0 2006.246.07:56:41.25#ibcon#read 5, iclass 35, count 0 2006.246.07:56:41.25#ibcon#about to read 6, iclass 35, count 0 2006.246.07:56:41.25#ibcon#read 6, iclass 35, count 0 2006.246.07:56:41.25#ibcon#end of sib2, iclass 35, count 0 2006.246.07:56:41.25#ibcon#*mode == 0, iclass 35, count 0 2006.246.07:56:41.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.07:56:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.07:56:41.25#ibcon#*before write, iclass 35, count 0 2006.246.07:56:41.25#ibcon#enter sib2, iclass 35, count 0 2006.246.07:56:41.25#ibcon#flushed, iclass 35, count 0 2006.246.07:56:41.25#ibcon#about to write, iclass 35, count 0 2006.246.07:56:41.25#ibcon#wrote, iclass 35, count 0 2006.246.07:56:41.25#ibcon#about to read 3, iclass 35, count 0 2006.246.07:56:41.29#ibcon#read 3, iclass 35, count 0 2006.246.07:56:41.29#ibcon#about to read 4, iclass 35, count 0 2006.246.07:56:41.29#ibcon#read 4, iclass 35, count 0 2006.246.07:56:41.29#ibcon#about to read 5, iclass 35, count 0 2006.246.07:56:41.29#ibcon#read 5, iclass 35, count 0 2006.246.07:56:41.29#ibcon#about to read 6, iclass 35, count 0 2006.246.07:56:41.29#ibcon#read 6, iclass 35, count 0 2006.246.07:56:41.29#ibcon#end of sib2, iclass 35, count 0 2006.246.07:56:41.29#ibcon#*after write, iclass 35, count 0 2006.246.07:56:41.29#ibcon#*before return 0, iclass 35, count 0 2006.246.07:56:41.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:41.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.07:56:41.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.07:56:41.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.07:56:41.29$vc4f8/vb=3,4 2006.246.07:56:41.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.07:56:41.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.07:56:41.29#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:41.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:41.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:41.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:41.35#ibcon#enter wrdev, iclass 37, count 2 2006.246.07:56:41.35#ibcon#first serial, iclass 37, count 2 2006.246.07:56:41.35#ibcon#enter sib2, iclass 37, count 2 2006.246.07:56:41.35#ibcon#flushed, iclass 37, count 2 2006.246.07:56:41.35#ibcon#about to write, iclass 37, count 2 2006.246.07:56:41.35#ibcon#wrote, iclass 37, count 2 2006.246.07:56:41.35#ibcon#about to read 3, iclass 37, count 2 2006.246.07:56:41.37#ibcon#read 3, iclass 37, count 2 2006.246.07:56:41.37#ibcon#about to read 4, iclass 37, count 2 2006.246.07:56:41.37#ibcon#read 4, iclass 37, count 2 2006.246.07:56:41.37#ibcon#about to read 5, iclass 37, count 2 2006.246.07:56:41.37#ibcon#read 5, iclass 37, count 2 2006.246.07:56:41.37#ibcon#about to read 6, iclass 37, count 2 2006.246.07:56:41.37#ibcon#read 6, iclass 37, count 2 2006.246.07:56:41.37#ibcon#end of sib2, iclass 37, count 2 2006.246.07:56:41.37#ibcon#*mode == 0, iclass 37, count 2 2006.246.07:56:41.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.07:56:41.37#ibcon#[27=AT03-04\r\n] 2006.246.07:56:41.37#ibcon#*before write, iclass 37, count 2 2006.246.07:56:41.37#ibcon#enter sib2, iclass 37, count 2 2006.246.07:56:41.37#ibcon#flushed, iclass 37, count 2 2006.246.07:56:41.37#ibcon#about to write, iclass 37, count 2 2006.246.07:56:41.37#ibcon#wrote, iclass 37, count 2 2006.246.07:56:41.37#ibcon#about to read 3, iclass 37, count 2 2006.246.07:56:41.40#ibcon#read 3, iclass 37, count 2 2006.246.07:56:41.40#ibcon#about to read 4, iclass 37, count 2 2006.246.07:56:41.40#ibcon#read 4, iclass 37, count 2 2006.246.07:56:41.40#ibcon#about to read 5, iclass 37, count 2 2006.246.07:56:41.40#ibcon#read 5, iclass 37, count 2 2006.246.07:56:41.40#ibcon#about to read 6, iclass 37, count 2 2006.246.07:56:41.40#ibcon#read 6, iclass 37, count 2 2006.246.07:56:41.40#ibcon#end of sib2, iclass 37, count 2 2006.246.07:56:41.40#ibcon#*after write, iclass 37, count 2 2006.246.07:56:41.40#ibcon#*before return 0, iclass 37, count 2 2006.246.07:56:41.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:41.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.07:56:41.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.07:56:41.40#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:41.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:41.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:41.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:41.52#ibcon#enter wrdev, iclass 37, count 0 2006.246.07:56:41.52#ibcon#first serial, iclass 37, count 0 2006.246.07:56:41.52#ibcon#enter sib2, iclass 37, count 0 2006.246.07:56:41.52#ibcon#flushed, iclass 37, count 0 2006.246.07:56:41.52#ibcon#about to write, iclass 37, count 0 2006.246.07:56:41.52#ibcon#wrote, iclass 37, count 0 2006.246.07:56:41.52#ibcon#about to read 3, iclass 37, count 0 2006.246.07:56:41.54#ibcon#read 3, iclass 37, count 0 2006.246.07:56:41.54#ibcon#about to read 4, iclass 37, count 0 2006.246.07:56:41.54#ibcon#read 4, iclass 37, count 0 2006.246.07:56:41.54#ibcon#about to read 5, iclass 37, count 0 2006.246.07:56:41.54#ibcon#read 5, iclass 37, count 0 2006.246.07:56:41.54#ibcon#about to read 6, iclass 37, count 0 2006.246.07:56:41.54#ibcon#read 6, iclass 37, count 0 2006.246.07:56:41.54#ibcon#end of sib2, iclass 37, count 0 2006.246.07:56:41.54#ibcon#*mode == 0, iclass 37, count 0 2006.246.07:56:41.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.07:56:41.54#ibcon#[27=USB\r\n] 2006.246.07:56:41.54#ibcon#*before write, iclass 37, count 0 2006.246.07:56:41.54#ibcon#enter sib2, iclass 37, count 0 2006.246.07:56:41.54#ibcon#flushed, iclass 37, count 0 2006.246.07:56:41.54#ibcon#about to write, iclass 37, count 0 2006.246.07:56:41.54#ibcon#wrote, iclass 37, count 0 2006.246.07:56:41.54#ibcon#about to read 3, iclass 37, count 0 2006.246.07:56:41.57#ibcon#read 3, iclass 37, count 0 2006.246.07:56:41.57#ibcon#about to read 4, iclass 37, count 0 2006.246.07:56:41.57#ibcon#read 4, iclass 37, count 0 2006.246.07:56:41.57#ibcon#about to read 5, iclass 37, count 0 2006.246.07:56:41.57#ibcon#read 5, iclass 37, count 0 2006.246.07:56:41.57#ibcon#about to read 6, iclass 37, count 0 2006.246.07:56:41.57#ibcon#read 6, iclass 37, count 0 2006.246.07:56:41.57#ibcon#end of sib2, iclass 37, count 0 2006.246.07:56:41.57#ibcon#*after write, iclass 37, count 0 2006.246.07:56:41.57#ibcon#*before return 0, iclass 37, count 0 2006.246.07:56:41.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:41.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.07:56:41.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.07:56:41.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.07:56:41.57$vc4f8/vblo=4,712.99 2006.246.07:56:41.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.07:56:41.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.07:56:41.57#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:41.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:41.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:41.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:41.57#ibcon#enter wrdev, iclass 39, count 0 2006.246.07:56:41.57#ibcon#first serial, iclass 39, count 0 2006.246.07:56:41.57#ibcon#enter sib2, iclass 39, count 0 2006.246.07:56:41.57#ibcon#flushed, iclass 39, count 0 2006.246.07:56:41.57#ibcon#about to write, iclass 39, count 0 2006.246.07:56:41.57#ibcon#wrote, iclass 39, count 0 2006.246.07:56:41.57#ibcon#about to read 3, iclass 39, count 0 2006.246.07:56:41.59#ibcon#read 3, iclass 39, count 0 2006.246.07:56:41.59#ibcon#about to read 4, iclass 39, count 0 2006.246.07:56:41.59#ibcon#read 4, iclass 39, count 0 2006.246.07:56:41.59#ibcon#about to read 5, iclass 39, count 0 2006.246.07:56:41.59#ibcon#read 5, iclass 39, count 0 2006.246.07:56:41.59#ibcon#about to read 6, iclass 39, count 0 2006.246.07:56:41.59#ibcon#read 6, iclass 39, count 0 2006.246.07:56:41.59#ibcon#end of sib2, iclass 39, count 0 2006.246.07:56:41.59#ibcon#*mode == 0, iclass 39, count 0 2006.246.07:56:41.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.07:56:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.07:56:41.59#ibcon#*before write, iclass 39, count 0 2006.246.07:56:41.59#ibcon#enter sib2, iclass 39, count 0 2006.246.07:56:41.59#ibcon#flushed, iclass 39, count 0 2006.246.07:56:41.59#ibcon#about to write, iclass 39, count 0 2006.246.07:56:41.59#ibcon#wrote, iclass 39, count 0 2006.246.07:56:41.59#ibcon#about to read 3, iclass 39, count 0 2006.246.07:56:41.63#ibcon#read 3, iclass 39, count 0 2006.246.07:56:41.63#ibcon#about to read 4, iclass 39, count 0 2006.246.07:56:41.63#ibcon#read 4, iclass 39, count 0 2006.246.07:56:41.63#ibcon#about to read 5, iclass 39, count 0 2006.246.07:56:41.63#ibcon#read 5, iclass 39, count 0 2006.246.07:56:41.63#ibcon#about to read 6, iclass 39, count 0 2006.246.07:56:41.63#ibcon#read 6, iclass 39, count 0 2006.246.07:56:41.63#ibcon#end of sib2, iclass 39, count 0 2006.246.07:56:41.63#ibcon#*after write, iclass 39, count 0 2006.246.07:56:41.63#ibcon#*before return 0, iclass 39, count 0 2006.246.07:56:41.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:41.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.07:56:41.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.07:56:41.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.07:56:41.63$vc4f8/vb=4,4 2006.246.07:56:41.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.07:56:41.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.07:56:41.63#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:41.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:41.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:41.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:41.69#ibcon#enter wrdev, iclass 3, count 2 2006.246.07:56:41.69#ibcon#first serial, iclass 3, count 2 2006.246.07:56:41.69#ibcon#enter sib2, iclass 3, count 2 2006.246.07:56:41.69#ibcon#flushed, iclass 3, count 2 2006.246.07:56:41.69#ibcon#about to write, iclass 3, count 2 2006.246.07:56:41.69#ibcon#wrote, iclass 3, count 2 2006.246.07:56:41.69#ibcon#about to read 3, iclass 3, count 2 2006.246.07:56:41.71#ibcon#read 3, iclass 3, count 2 2006.246.07:56:41.71#ibcon#about to read 4, iclass 3, count 2 2006.246.07:56:41.71#ibcon#read 4, iclass 3, count 2 2006.246.07:56:41.71#ibcon#about to read 5, iclass 3, count 2 2006.246.07:56:41.71#ibcon#read 5, iclass 3, count 2 2006.246.07:56:41.71#ibcon#about to read 6, iclass 3, count 2 2006.246.07:56:41.71#ibcon#read 6, iclass 3, count 2 2006.246.07:56:41.71#ibcon#end of sib2, iclass 3, count 2 2006.246.07:56:41.71#ibcon#*mode == 0, iclass 3, count 2 2006.246.07:56:41.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.07:56:41.71#ibcon#[27=AT04-04\r\n] 2006.246.07:56:41.71#ibcon#*before write, iclass 3, count 2 2006.246.07:56:41.71#ibcon#enter sib2, iclass 3, count 2 2006.246.07:56:41.71#ibcon#flushed, iclass 3, count 2 2006.246.07:56:41.71#ibcon#about to write, iclass 3, count 2 2006.246.07:56:41.71#ibcon#wrote, iclass 3, count 2 2006.246.07:56:41.71#ibcon#about to read 3, iclass 3, count 2 2006.246.07:56:41.74#ibcon#read 3, iclass 3, count 2 2006.246.07:56:41.74#ibcon#about to read 4, iclass 3, count 2 2006.246.07:56:41.74#ibcon#read 4, iclass 3, count 2 2006.246.07:56:41.74#ibcon#about to read 5, iclass 3, count 2 2006.246.07:56:41.74#ibcon#read 5, iclass 3, count 2 2006.246.07:56:41.74#ibcon#about to read 6, iclass 3, count 2 2006.246.07:56:41.74#ibcon#read 6, iclass 3, count 2 2006.246.07:56:41.74#ibcon#end of sib2, iclass 3, count 2 2006.246.07:56:41.74#ibcon#*after write, iclass 3, count 2 2006.246.07:56:41.74#ibcon#*before return 0, iclass 3, count 2 2006.246.07:56:41.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:41.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.07:56:41.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.07:56:41.74#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:41.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:41.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:41.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:41.86#ibcon#enter wrdev, iclass 3, count 0 2006.246.07:56:41.86#ibcon#first serial, iclass 3, count 0 2006.246.07:56:41.86#ibcon#enter sib2, iclass 3, count 0 2006.246.07:56:41.86#ibcon#flushed, iclass 3, count 0 2006.246.07:56:41.86#ibcon#about to write, iclass 3, count 0 2006.246.07:56:41.86#ibcon#wrote, iclass 3, count 0 2006.246.07:56:41.86#ibcon#about to read 3, iclass 3, count 0 2006.246.07:56:41.88#ibcon#read 3, iclass 3, count 0 2006.246.07:56:41.88#ibcon#about to read 4, iclass 3, count 0 2006.246.07:56:41.88#ibcon#read 4, iclass 3, count 0 2006.246.07:56:41.88#ibcon#about to read 5, iclass 3, count 0 2006.246.07:56:41.88#ibcon#read 5, iclass 3, count 0 2006.246.07:56:41.88#ibcon#about to read 6, iclass 3, count 0 2006.246.07:56:41.88#ibcon#read 6, iclass 3, count 0 2006.246.07:56:41.88#ibcon#end of sib2, iclass 3, count 0 2006.246.07:56:41.88#ibcon#*mode == 0, iclass 3, count 0 2006.246.07:56:41.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.07:56:41.88#ibcon#[27=USB\r\n] 2006.246.07:56:41.88#ibcon#*before write, iclass 3, count 0 2006.246.07:56:41.88#ibcon#enter sib2, iclass 3, count 0 2006.246.07:56:41.88#ibcon#flushed, iclass 3, count 0 2006.246.07:56:41.88#ibcon#about to write, iclass 3, count 0 2006.246.07:56:41.88#ibcon#wrote, iclass 3, count 0 2006.246.07:56:41.88#ibcon#about to read 3, iclass 3, count 0 2006.246.07:56:41.91#ibcon#read 3, iclass 3, count 0 2006.246.07:56:41.91#ibcon#about to read 4, iclass 3, count 0 2006.246.07:56:41.91#ibcon#read 4, iclass 3, count 0 2006.246.07:56:41.91#ibcon#about to read 5, iclass 3, count 0 2006.246.07:56:41.91#ibcon#read 5, iclass 3, count 0 2006.246.07:56:41.91#ibcon#about to read 6, iclass 3, count 0 2006.246.07:56:41.91#ibcon#read 6, iclass 3, count 0 2006.246.07:56:41.91#ibcon#end of sib2, iclass 3, count 0 2006.246.07:56:41.91#ibcon#*after write, iclass 3, count 0 2006.246.07:56:41.91#ibcon#*before return 0, iclass 3, count 0 2006.246.07:56:41.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:41.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.07:56:41.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.07:56:41.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.07:56:41.91$vc4f8/vblo=5,744.99 2006.246.07:56:41.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.07:56:41.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.07:56:41.91#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:41.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:41.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:41.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:41.91#ibcon#enter wrdev, iclass 5, count 0 2006.246.07:56:41.91#ibcon#first serial, iclass 5, count 0 2006.246.07:56:41.91#ibcon#enter sib2, iclass 5, count 0 2006.246.07:56:41.91#ibcon#flushed, iclass 5, count 0 2006.246.07:56:41.91#ibcon#about to write, iclass 5, count 0 2006.246.07:56:41.91#ibcon#wrote, iclass 5, count 0 2006.246.07:56:41.91#ibcon#about to read 3, iclass 5, count 0 2006.246.07:56:41.93#ibcon#read 3, iclass 5, count 0 2006.246.07:56:41.93#ibcon#about to read 4, iclass 5, count 0 2006.246.07:56:41.93#ibcon#read 4, iclass 5, count 0 2006.246.07:56:41.93#ibcon#about to read 5, iclass 5, count 0 2006.246.07:56:41.93#ibcon#read 5, iclass 5, count 0 2006.246.07:56:41.93#ibcon#about to read 6, iclass 5, count 0 2006.246.07:56:41.93#ibcon#read 6, iclass 5, count 0 2006.246.07:56:41.93#ibcon#end of sib2, iclass 5, count 0 2006.246.07:56:41.93#ibcon#*mode == 0, iclass 5, count 0 2006.246.07:56:41.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.07:56:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.07:56:41.93#ibcon#*before write, iclass 5, count 0 2006.246.07:56:41.93#ibcon#enter sib2, iclass 5, count 0 2006.246.07:56:41.93#ibcon#flushed, iclass 5, count 0 2006.246.07:56:41.93#ibcon#about to write, iclass 5, count 0 2006.246.07:56:41.93#ibcon#wrote, iclass 5, count 0 2006.246.07:56:41.93#ibcon#about to read 3, iclass 5, count 0 2006.246.07:56:41.97#ibcon#read 3, iclass 5, count 0 2006.246.07:56:41.97#ibcon#about to read 4, iclass 5, count 0 2006.246.07:56:41.97#ibcon#read 4, iclass 5, count 0 2006.246.07:56:41.97#ibcon#about to read 5, iclass 5, count 0 2006.246.07:56:41.97#ibcon#read 5, iclass 5, count 0 2006.246.07:56:41.97#ibcon#about to read 6, iclass 5, count 0 2006.246.07:56:41.97#ibcon#read 6, iclass 5, count 0 2006.246.07:56:41.97#ibcon#end of sib2, iclass 5, count 0 2006.246.07:56:41.97#ibcon#*after write, iclass 5, count 0 2006.246.07:56:41.97#ibcon#*before return 0, iclass 5, count 0 2006.246.07:56:41.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:41.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.07:56:41.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.07:56:41.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.07:56:41.97$vc4f8/vb=5,3 2006.246.07:56:41.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.07:56:41.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.07:56:41.97#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:41.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:42.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:42.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:42.03#ibcon#enter wrdev, iclass 7, count 2 2006.246.07:56:42.03#ibcon#first serial, iclass 7, count 2 2006.246.07:56:42.03#ibcon#enter sib2, iclass 7, count 2 2006.246.07:56:42.03#ibcon#flushed, iclass 7, count 2 2006.246.07:56:42.03#ibcon#about to write, iclass 7, count 2 2006.246.07:56:42.03#ibcon#wrote, iclass 7, count 2 2006.246.07:56:42.03#ibcon#about to read 3, iclass 7, count 2 2006.246.07:56:42.05#ibcon#read 3, iclass 7, count 2 2006.246.07:56:42.05#ibcon#about to read 4, iclass 7, count 2 2006.246.07:56:42.05#ibcon#read 4, iclass 7, count 2 2006.246.07:56:42.05#ibcon#about to read 5, iclass 7, count 2 2006.246.07:56:42.05#ibcon#read 5, iclass 7, count 2 2006.246.07:56:42.05#ibcon#about to read 6, iclass 7, count 2 2006.246.07:56:42.05#ibcon#read 6, iclass 7, count 2 2006.246.07:56:42.05#ibcon#end of sib2, iclass 7, count 2 2006.246.07:56:42.05#ibcon#*mode == 0, iclass 7, count 2 2006.246.07:56:42.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.07:56:42.05#ibcon#[27=AT05-03\r\n] 2006.246.07:56:42.05#ibcon#*before write, iclass 7, count 2 2006.246.07:56:42.05#ibcon#enter sib2, iclass 7, count 2 2006.246.07:56:42.05#ibcon#flushed, iclass 7, count 2 2006.246.07:56:42.05#ibcon#about to write, iclass 7, count 2 2006.246.07:56:42.05#ibcon#wrote, iclass 7, count 2 2006.246.07:56:42.05#ibcon#about to read 3, iclass 7, count 2 2006.246.07:56:42.08#ibcon#read 3, iclass 7, count 2 2006.246.07:56:42.08#ibcon#about to read 4, iclass 7, count 2 2006.246.07:56:42.08#ibcon#read 4, iclass 7, count 2 2006.246.07:56:42.08#ibcon#about to read 5, iclass 7, count 2 2006.246.07:56:42.08#ibcon#read 5, iclass 7, count 2 2006.246.07:56:42.08#ibcon#about to read 6, iclass 7, count 2 2006.246.07:56:42.08#ibcon#read 6, iclass 7, count 2 2006.246.07:56:42.08#ibcon#end of sib2, iclass 7, count 2 2006.246.07:56:42.08#ibcon#*after write, iclass 7, count 2 2006.246.07:56:42.08#ibcon#*before return 0, iclass 7, count 2 2006.246.07:56:42.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:42.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.07:56:42.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.07:56:42.08#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:42.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:42.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:42.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:42.20#ibcon#enter wrdev, iclass 7, count 0 2006.246.07:56:42.20#ibcon#first serial, iclass 7, count 0 2006.246.07:56:42.20#ibcon#enter sib2, iclass 7, count 0 2006.246.07:56:42.20#ibcon#flushed, iclass 7, count 0 2006.246.07:56:42.20#ibcon#about to write, iclass 7, count 0 2006.246.07:56:42.20#ibcon#wrote, iclass 7, count 0 2006.246.07:56:42.20#ibcon#about to read 3, iclass 7, count 0 2006.246.07:56:42.22#ibcon#read 3, iclass 7, count 0 2006.246.07:56:42.22#ibcon#about to read 4, iclass 7, count 0 2006.246.07:56:42.22#ibcon#read 4, iclass 7, count 0 2006.246.07:56:42.22#ibcon#about to read 5, iclass 7, count 0 2006.246.07:56:42.22#ibcon#read 5, iclass 7, count 0 2006.246.07:56:42.22#ibcon#about to read 6, iclass 7, count 0 2006.246.07:56:42.22#ibcon#read 6, iclass 7, count 0 2006.246.07:56:42.22#ibcon#end of sib2, iclass 7, count 0 2006.246.07:56:42.22#ibcon#*mode == 0, iclass 7, count 0 2006.246.07:56:42.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.07:56:42.22#ibcon#[27=USB\r\n] 2006.246.07:56:42.22#ibcon#*before write, iclass 7, count 0 2006.246.07:56:42.22#ibcon#enter sib2, iclass 7, count 0 2006.246.07:56:42.22#ibcon#flushed, iclass 7, count 0 2006.246.07:56:42.22#ibcon#about to write, iclass 7, count 0 2006.246.07:56:42.22#ibcon#wrote, iclass 7, count 0 2006.246.07:56:42.22#ibcon#about to read 3, iclass 7, count 0 2006.246.07:56:42.25#ibcon#read 3, iclass 7, count 0 2006.246.07:56:42.25#ibcon#about to read 4, iclass 7, count 0 2006.246.07:56:42.25#ibcon#read 4, iclass 7, count 0 2006.246.07:56:42.25#ibcon#about to read 5, iclass 7, count 0 2006.246.07:56:42.25#ibcon#read 5, iclass 7, count 0 2006.246.07:56:42.25#ibcon#about to read 6, iclass 7, count 0 2006.246.07:56:42.25#ibcon#read 6, iclass 7, count 0 2006.246.07:56:42.25#ibcon#end of sib2, iclass 7, count 0 2006.246.07:56:42.25#ibcon#*after write, iclass 7, count 0 2006.246.07:56:42.25#ibcon#*before return 0, iclass 7, count 0 2006.246.07:56:42.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:42.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.07:56:42.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.07:56:42.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.07:56:42.25$vc4f8/vblo=6,752.99 2006.246.07:56:42.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.07:56:42.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.07:56:42.25#ibcon#ireg 17 cls_cnt 0 2006.246.07:56:42.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:42.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:42.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:42.25#ibcon#enter wrdev, iclass 11, count 0 2006.246.07:56:42.25#ibcon#first serial, iclass 11, count 0 2006.246.07:56:42.25#ibcon#enter sib2, iclass 11, count 0 2006.246.07:56:42.25#ibcon#flushed, iclass 11, count 0 2006.246.07:56:42.25#ibcon#about to write, iclass 11, count 0 2006.246.07:56:42.25#ibcon#wrote, iclass 11, count 0 2006.246.07:56:42.25#ibcon#about to read 3, iclass 11, count 0 2006.246.07:56:42.27#ibcon#read 3, iclass 11, count 0 2006.246.07:56:42.27#ibcon#about to read 4, iclass 11, count 0 2006.246.07:56:42.27#ibcon#read 4, iclass 11, count 0 2006.246.07:56:42.27#ibcon#about to read 5, iclass 11, count 0 2006.246.07:56:42.27#ibcon#read 5, iclass 11, count 0 2006.246.07:56:42.27#ibcon#about to read 6, iclass 11, count 0 2006.246.07:56:42.27#ibcon#read 6, iclass 11, count 0 2006.246.07:56:42.27#ibcon#end of sib2, iclass 11, count 0 2006.246.07:56:42.27#ibcon#*mode == 0, iclass 11, count 0 2006.246.07:56:42.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.07:56:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.07:56:42.27#ibcon#*before write, iclass 11, count 0 2006.246.07:56:42.27#ibcon#enter sib2, iclass 11, count 0 2006.246.07:56:42.27#ibcon#flushed, iclass 11, count 0 2006.246.07:56:42.27#ibcon#about to write, iclass 11, count 0 2006.246.07:56:42.27#ibcon#wrote, iclass 11, count 0 2006.246.07:56:42.27#ibcon#about to read 3, iclass 11, count 0 2006.246.07:56:42.31#ibcon#read 3, iclass 11, count 0 2006.246.07:56:42.31#ibcon#about to read 4, iclass 11, count 0 2006.246.07:56:42.31#ibcon#read 4, iclass 11, count 0 2006.246.07:56:42.31#ibcon#about to read 5, iclass 11, count 0 2006.246.07:56:42.31#ibcon#read 5, iclass 11, count 0 2006.246.07:56:42.31#ibcon#about to read 6, iclass 11, count 0 2006.246.07:56:42.31#ibcon#read 6, iclass 11, count 0 2006.246.07:56:42.31#ibcon#end of sib2, iclass 11, count 0 2006.246.07:56:42.31#ibcon#*after write, iclass 11, count 0 2006.246.07:56:42.31#ibcon#*before return 0, iclass 11, count 0 2006.246.07:56:42.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:42.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.07:56:42.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.07:56:42.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.07:56:42.31$vc4f8/vb=6,3 2006.246.07:56:42.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.07:56:42.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.07:56:42.31#ibcon#ireg 11 cls_cnt 2 2006.246.07:56:42.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:42.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:42.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:42.37#ibcon#enter wrdev, iclass 13, count 2 2006.246.07:56:42.37#ibcon#first serial, iclass 13, count 2 2006.246.07:56:42.37#ibcon#enter sib2, iclass 13, count 2 2006.246.07:56:42.37#ibcon#flushed, iclass 13, count 2 2006.246.07:56:42.37#ibcon#about to write, iclass 13, count 2 2006.246.07:56:42.37#ibcon#wrote, iclass 13, count 2 2006.246.07:56:42.37#ibcon#about to read 3, iclass 13, count 2 2006.246.07:56:42.39#ibcon#read 3, iclass 13, count 2 2006.246.07:56:42.39#ibcon#about to read 4, iclass 13, count 2 2006.246.07:56:42.39#ibcon#read 4, iclass 13, count 2 2006.246.07:56:42.39#ibcon#about to read 5, iclass 13, count 2 2006.246.07:56:42.39#ibcon#read 5, iclass 13, count 2 2006.246.07:56:42.39#ibcon#about to read 6, iclass 13, count 2 2006.246.07:56:42.39#ibcon#read 6, iclass 13, count 2 2006.246.07:56:42.39#ibcon#end of sib2, iclass 13, count 2 2006.246.07:56:42.39#ibcon#*mode == 0, iclass 13, count 2 2006.246.07:56:42.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.07:56:42.39#ibcon#[27=AT06-03\r\n] 2006.246.07:56:42.39#ibcon#*before write, iclass 13, count 2 2006.246.07:56:42.39#ibcon#enter sib2, iclass 13, count 2 2006.246.07:56:42.39#ibcon#flushed, iclass 13, count 2 2006.246.07:56:42.39#ibcon#about to write, iclass 13, count 2 2006.246.07:56:42.39#ibcon#wrote, iclass 13, count 2 2006.246.07:56:42.39#ibcon#about to read 3, iclass 13, count 2 2006.246.07:56:42.42#ibcon#read 3, iclass 13, count 2 2006.246.07:56:42.42#ibcon#about to read 4, iclass 13, count 2 2006.246.07:56:42.42#ibcon#read 4, iclass 13, count 2 2006.246.07:56:42.42#ibcon#about to read 5, iclass 13, count 2 2006.246.07:56:42.42#ibcon#read 5, iclass 13, count 2 2006.246.07:56:42.42#ibcon#about to read 6, iclass 13, count 2 2006.246.07:56:42.42#ibcon#read 6, iclass 13, count 2 2006.246.07:56:42.42#ibcon#end of sib2, iclass 13, count 2 2006.246.07:56:42.42#ibcon#*after write, iclass 13, count 2 2006.246.07:56:42.42#ibcon#*before return 0, iclass 13, count 2 2006.246.07:56:42.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:42.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.07:56:42.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.07:56:42.42#ibcon#ireg 7 cls_cnt 0 2006.246.07:56:42.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:42.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:42.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:42.54#ibcon#enter wrdev, iclass 13, count 0 2006.246.07:56:42.54#ibcon#first serial, iclass 13, count 0 2006.246.07:56:42.54#ibcon#enter sib2, iclass 13, count 0 2006.246.07:56:42.54#ibcon#flushed, iclass 13, count 0 2006.246.07:56:42.54#ibcon#about to write, iclass 13, count 0 2006.246.07:56:42.54#ibcon#wrote, iclass 13, count 0 2006.246.07:56:42.54#ibcon#about to read 3, iclass 13, count 0 2006.246.07:56:42.56#ibcon#read 3, iclass 13, count 0 2006.246.07:56:42.56#ibcon#about to read 4, iclass 13, count 0 2006.246.07:56:42.56#ibcon#read 4, iclass 13, count 0 2006.246.07:56:42.56#ibcon#about to read 5, iclass 13, count 0 2006.246.07:56:42.56#ibcon#read 5, iclass 13, count 0 2006.246.07:56:42.56#ibcon#about to read 6, iclass 13, count 0 2006.246.07:56:42.56#ibcon#read 6, iclass 13, count 0 2006.246.07:56:42.56#ibcon#end of sib2, iclass 13, count 0 2006.246.07:56:42.56#ibcon#*mode == 0, iclass 13, count 0 2006.246.07:56:42.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.07:56:42.56#ibcon#[27=USB\r\n] 2006.246.07:56:42.56#ibcon#*before write, iclass 13, count 0 2006.246.07:56:42.56#ibcon#enter sib2, iclass 13, count 0 2006.246.07:56:42.56#ibcon#flushed, iclass 13, count 0 2006.246.07:56:42.56#ibcon#about to write, iclass 13, count 0 2006.246.07:56:42.56#ibcon#wrote, iclass 13, count 0 2006.246.07:56:42.56#ibcon#about to read 3, iclass 13, count 0 2006.246.07:56:42.59#ibcon#read 3, iclass 13, count 0 2006.246.07:56:42.59#ibcon#about to read 4, iclass 13, count 0 2006.246.07:56:42.59#ibcon#read 4, iclass 13, count 0 2006.246.07:56:42.59#ibcon#about to read 5, iclass 13, count 0 2006.246.07:56:42.59#ibcon#read 5, iclass 13, count 0 2006.246.07:56:42.59#ibcon#about to read 6, iclass 13, count 0 2006.246.07:56:42.59#ibcon#read 6, iclass 13, count 0 2006.246.07:56:42.59#ibcon#end of sib2, iclass 13, count 0 2006.246.07:56:42.59#ibcon#*after write, iclass 13, count 0 2006.246.07:56:42.59#ibcon#*before return 0, iclass 13, count 0 2006.246.07:56:42.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:42.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.07:56:42.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.07:56:42.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.07:56:42.59$vc4f8/vabw=wide 2006.246.07:56:42.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.07:56:42.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.07:56:42.59#ibcon#ireg 8 cls_cnt 0 2006.246.07:56:42.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:42.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:42.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:42.59#ibcon#enter wrdev, iclass 15, count 0 2006.246.07:56:42.59#ibcon#first serial, iclass 15, count 0 2006.246.07:56:42.59#ibcon#enter sib2, iclass 15, count 0 2006.246.07:56:42.59#ibcon#flushed, iclass 15, count 0 2006.246.07:56:42.59#ibcon#about to write, iclass 15, count 0 2006.246.07:56:42.59#ibcon#wrote, iclass 15, count 0 2006.246.07:56:42.59#ibcon#about to read 3, iclass 15, count 0 2006.246.07:56:42.61#ibcon#read 3, iclass 15, count 0 2006.246.07:56:42.61#ibcon#about to read 4, iclass 15, count 0 2006.246.07:56:42.61#ibcon#read 4, iclass 15, count 0 2006.246.07:56:42.61#ibcon#about to read 5, iclass 15, count 0 2006.246.07:56:42.61#ibcon#read 5, iclass 15, count 0 2006.246.07:56:42.61#ibcon#about to read 6, iclass 15, count 0 2006.246.07:56:42.61#ibcon#read 6, iclass 15, count 0 2006.246.07:56:42.61#ibcon#end of sib2, iclass 15, count 0 2006.246.07:56:42.61#ibcon#*mode == 0, iclass 15, count 0 2006.246.07:56:42.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.07:56:42.61#ibcon#[25=BW32\r\n] 2006.246.07:56:42.61#ibcon#*before write, iclass 15, count 0 2006.246.07:56:42.61#ibcon#enter sib2, iclass 15, count 0 2006.246.07:56:42.61#ibcon#flushed, iclass 15, count 0 2006.246.07:56:42.61#ibcon#about to write, iclass 15, count 0 2006.246.07:56:42.61#ibcon#wrote, iclass 15, count 0 2006.246.07:56:42.61#ibcon#about to read 3, iclass 15, count 0 2006.246.07:56:42.64#ibcon#read 3, iclass 15, count 0 2006.246.07:56:42.64#ibcon#about to read 4, iclass 15, count 0 2006.246.07:56:42.64#ibcon#read 4, iclass 15, count 0 2006.246.07:56:42.64#ibcon#about to read 5, iclass 15, count 0 2006.246.07:56:42.64#ibcon#read 5, iclass 15, count 0 2006.246.07:56:42.64#ibcon#about to read 6, iclass 15, count 0 2006.246.07:56:42.64#ibcon#read 6, iclass 15, count 0 2006.246.07:56:42.64#ibcon#end of sib2, iclass 15, count 0 2006.246.07:56:42.64#ibcon#*after write, iclass 15, count 0 2006.246.07:56:42.64#ibcon#*before return 0, iclass 15, count 0 2006.246.07:56:42.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:42.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.07:56:42.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.07:56:42.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.07:56:42.64$vc4f8/vbbw=wide 2006.246.07:56:42.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.07:56:42.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.07:56:42.64#ibcon#ireg 8 cls_cnt 0 2006.246.07:56:42.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:56:42.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:56:42.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:56:42.71#ibcon#enter wrdev, iclass 17, count 0 2006.246.07:56:42.71#ibcon#first serial, iclass 17, count 0 2006.246.07:56:42.71#ibcon#enter sib2, iclass 17, count 0 2006.246.07:56:42.71#ibcon#flushed, iclass 17, count 0 2006.246.07:56:42.71#ibcon#about to write, iclass 17, count 0 2006.246.07:56:42.71#ibcon#wrote, iclass 17, count 0 2006.246.07:56:42.71#ibcon#about to read 3, iclass 17, count 0 2006.246.07:56:42.73#ibcon#read 3, iclass 17, count 0 2006.246.07:56:42.73#ibcon#about to read 4, iclass 17, count 0 2006.246.07:56:42.73#ibcon#read 4, iclass 17, count 0 2006.246.07:56:42.73#ibcon#about to read 5, iclass 17, count 0 2006.246.07:56:42.73#ibcon#read 5, iclass 17, count 0 2006.246.07:56:42.73#ibcon#about to read 6, iclass 17, count 0 2006.246.07:56:42.73#ibcon#read 6, iclass 17, count 0 2006.246.07:56:42.73#ibcon#end of sib2, iclass 17, count 0 2006.246.07:56:42.73#ibcon#*mode == 0, iclass 17, count 0 2006.246.07:56:42.73#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.07:56:42.73#ibcon#[27=BW32\r\n] 2006.246.07:56:42.73#ibcon#*before write, iclass 17, count 0 2006.246.07:56:42.73#ibcon#enter sib2, iclass 17, count 0 2006.246.07:56:42.73#ibcon#flushed, iclass 17, count 0 2006.246.07:56:42.73#ibcon#about to write, iclass 17, count 0 2006.246.07:56:42.73#ibcon#wrote, iclass 17, count 0 2006.246.07:56:42.73#ibcon#about to read 3, iclass 17, count 0 2006.246.07:56:42.76#ibcon#read 3, iclass 17, count 0 2006.246.07:56:42.76#ibcon#about to read 4, iclass 17, count 0 2006.246.07:56:42.76#ibcon#read 4, iclass 17, count 0 2006.246.07:56:42.76#ibcon#about to read 5, iclass 17, count 0 2006.246.07:56:42.76#ibcon#read 5, iclass 17, count 0 2006.246.07:56:42.76#ibcon#about to read 6, iclass 17, count 0 2006.246.07:56:42.76#ibcon#read 6, iclass 17, count 0 2006.246.07:56:42.76#ibcon#end of sib2, iclass 17, count 0 2006.246.07:56:42.76#ibcon#*after write, iclass 17, count 0 2006.246.07:56:42.76#ibcon#*before return 0, iclass 17, count 0 2006.246.07:56:42.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:56:42.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.07:56:42.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.07:56:42.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.07:56:42.76$4f8m12a/ifd4f 2006.246.07:56:42.76$ifd4f/lo= 2006.246.07:56:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.07:56:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.07:56:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.07:56:42.76$ifd4f/patch= 2006.246.07:56:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.07:56:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.07:56:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.07:56:42.76$4f8m12a/"form=m,16.000,1:2 2006.246.07:56:42.76$4f8m12a/"tpicd 2006.246.07:56:42.76$4f8m12a/echo=off 2006.246.07:56:42.76$4f8m12a/xlog=off 2006.246.07:56:42.76:!2006.246.07:58:50 2006.246.07:57:07.14#trakl#Source acquired 2006.246.07:57:07.14#flagr#flagr/antenna,acquired 2006.246.07:58:50.00:preob 2006.246.07:58:50.14/onsource/TRACKING 2006.246.07:58:50.14:!2006.246.07:59:00 2006.246.07:59:00.00:data_valid=on 2006.246.07:59:00.00:midob 2006.246.07:59:01.14/onsource/TRACKING 2006.246.07:59:01.14/wx/26.63,1005.7,75 2006.246.07:59:01.26/cable/+6.4141E-03 2006.246.07:59:02.35/va/01,08,usb,yes,31,32 2006.246.07:59:02.35/va/02,07,usb,yes,30,32 2006.246.07:59:02.35/va/03,06,usb,yes,32,33 2006.246.07:59:02.35/va/04,07,usb,yes,31,34 2006.246.07:59:02.35/va/05,07,usb,yes,33,35 2006.246.07:59:02.35/va/06,07,usb,yes,29,29 2006.246.07:59:02.35/va/07,07,usb,yes,29,29 2006.246.07:59:02.35/va/08,08,usb,yes,25,25 2006.246.07:59:02.58/valo/01,532.99,yes,locked 2006.246.07:59:02.58/valo/02,572.99,yes,locked 2006.246.07:59:02.58/valo/03,672.99,yes,locked 2006.246.07:59:02.58/valo/04,832.99,yes,locked 2006.246.07:59:02.58/valo/05,652.99,yes,locked 2006.246.07:59:02.58/valo/06,772.99,yes,locked 2006.246.07:59:02.58/valo/07,832.99,yes,locked 2006.246.07:59:02.58/valo/08,852.99,yes,locked 2006.246.07:59:03.67/vb/01,04,usb,yes,30,29 2006.246.07:59:03.67/vb/02,04,usb,yes,32,33 2006.246.07:59:03.67/vb/03,04,usb,yes,28,32 2006.246.07:59:03.67/vb/04,04,usb,yes,29,29 2006.246.07:59:03.67/vb/05,03,usb,yes,34,39 2006.246.07:59:03.67/vb/06,03,usb,yes,35,39 2006.246.07:59:03.67/vb/07,04,usb,yes,31,31 2006.246.07:59:03.67/vb/08,03,usb,yes,35,39 2006.246.07:59:03.91/vblo/01,632.99,yes,locked 2006.246.07:59:03.91/vblo/02,640.99,yes,locked 2006.246.07:59:03.91/vblo/03,656.99,yes,locked 2006.246.07:59:03.91/vblo/04,712.99,yes,locked 2006.246.07:59:03.91/vblo/05,744.99,yes,locked 2006.246.07:59:03.91/vblo/06,752.99,yes,locked 2006.246.07:59:03.91/vblo/07,734.99,yes,locked 2006.246.07:59:03.91/vblo/08,744.99,yes,locked 2006.246.07:59:04.06/vabw/8 2006.246.07:59:04.21/vbbw/8 2006.246.07:59:04.32/xfe/off,on,13.2 2006.246.07:59:04.69/ifatt/23,28,28,28 2006.246.07:59:05.08/fmout-gps/S +4.39E-07 2006.246.07:59:05.12:!2006.246.08:00:00 2006.246.08:00:00.00:data_valid=off 2006.246.08:00:00.00:postob 2006.246.08:00:00.11/cable/+6.4146E-03 2006.246.08:00:00.11/wx/26.62,1005.7,75 2006.246.08:00:01.08/fmout-gps/S +4.39E-07 2006.246.08:00:01.08:scan_name=246-0800,k06246,60 2006.246.08:00:01.09:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.246.08:00:01.14#flagr#flagr/antenna,new-source 2006.246.08:00:02.14:checkk5 2006.246.08:00:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:00:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:00:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:00:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:00:04.01/chk_obsdata//k5ts1/T2460759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:00:04.38/chk_obsdata//k5ts2/T2460759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:00:04.74/chk_obsdata//k5ts3/T2460759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:00:05.12/chk_obsdata//k5ts4/T2460759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:00:05.82/k5log//k5ts1_log_newline 2006.246.08:00:06.52/k5log//k5ts2_log_newline 2006.246.08:00:07.20/k5log//k5ts3_log_newline 2006.246.08:00:07.88/k5log//k5ts4_log_newline 2006.246.08:00:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:00:07.91:4f8m12a=2 2006.246.08:00:07.91$4f8m12a/echo=on 2006.246.08:00:07.91$4f8m12a/pcalon 2006.246.08:00:07.91$pcalon/"no phase cal control is implemented here 2006.246.08:00:07.91$4f8m12a/"tpicd=stop 2006.246.08:00:07.91$4f8m12a/vc4f8 2006.246.08:00:07.91$vc4f8/valo=1,532.99 2006.246.08:00:07.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:00:07.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:00:07.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:07.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:07.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:07.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:07.91#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:00:07.91#ibcon#first serial, iclass 32, count 0 2006.246.08:00:07.91#ibcon#enter sib2, iclass 32, count 0 2006.246.08:00:07.91#ibcon#flushed, iclass 32, count 0 2006.246.08:00:07.91#ibcon#about to write, iclass 32, count 0 2006.246.08:00:07.91#ibcon#wrote, iclass 32, count 0 2006.246.08:00:07.91#ibcon#about to read 3, iclass 32, count 0 2006.246.08:00:07.95#ibcon#read 3, iclass 32, count 0 2006.246.08:00:07.95#ibcon#about to read 4, iclass 32, count 0 2006.246.08:00:07.95#ibcon#read 4, iclass 32, count 0 2006.246.08:00:07.95#ibcon#about to read 5, iclass 32, count 0 2006.246.08:00:07.95#ibcon#read 5, iclass 32, count 0 2006.246.08:00:07.95#ibcon#about to read 6, iclass 32, count 0 2006.246.08:00:07.95#ibcon#read 6, iclass 32, count 0 2006.246.08:00:07.95#ibcon#end of sib2, iclass 32, count 0 2006.246.08:00:07.95#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:00:07.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:00:07.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:00:07.95#ibcon#*before write, iclass 32, count 0 2006.246.08:00:07.95#ibcon#enter sib2, iclass 32, count 0 2006.246.08:00:07.95#ibcon#flushed, iclass 32, count 0 2006.246.08:00:07.95#ibcon#about to write, iclass 32, count 0 2006.246.08:00:07.95#ibcon#wrote, iclass 32, count 0 2006.246.08:00:07.95#ibcon#about to read 3, iclass 32, count 0 2006.246.08:00:08.00#ibcon#read 3, iclass 32, count 0 2006.246.08:00:08.00#ibcon#about to read 4, iclass 32, count 0 2006.246.08:00:08.00#ibcon#read 4, iclass 32, count 0 2006.246.08:00:08.00#ibcon#about to read 5, iclass 32, count 0 2006.246.08:00:08.00#ibcon#read 5, iclass 32, count 0 2006.246.08:00:08.00#ibcon#about to read 6, iclass 32, count 0 2006.246.08:00:08.00#ibcon#read 6, iclass 32, count 0 2006.246.08:00:08.00#ibcon#end of sib2, iclass 32, count 0 2006.246.08:00:08.00#ibcon#*after write, iclass 32, count 0 2006.246.08:00:08.00#ibcon#*before return 0, iclass 32, count 0 2006.246.08:00:08.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:08.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:08.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:00:08.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:00:08.00$vc4f8/va=1,8 2006.246.08:00:08.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.08:00:08.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.08:00:08.00#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:08.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:08.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:08.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:08.00#ibcon#enter wrdev, iclass 34, count 2 2006.246.08:00:08.00#ibcon#first serial, iclass 34, count 2 2006.246.08:00:08.00#ibcon#enter sib2, iclass 34, count 2 2006.246.08:00:08.00#ibcon#flushed, iclass 34, count 2 2006.246.08:00:08.00#ibcon#about to write, iclass 34, count 2 2006.246.08:00:08.00#ibcon#wrote, iclass 34, count 2 2006.246.08:00:08.00#ibcon#about to read 3, iclass 34, count 2 2006.246.08:00:08.02#ibcon#read 3, iclass 34, count 2 2006.246.08:00:08.02#ibcon#about to read 4, iclass 34, count 2 2006.246.08:00:08.02#ibcon#read 4, iclass 34, count 2 2006.246.08:00:08.02#ibcon#about to read 5, iclass 34, count 2 2006.246.08:00:08.02#ibcon#read 5, iclass 34, count 2 2006.246.08:00:08.02#ibcon#about to read 6, iclass 34, count 2 2006.246.08:00:08.02#ibcon#read 6, iclass 34, count 2 2006.246.08:00:08.02#ibcon#end of sib2, iclass 34, count 2 2006.246.08:00:08.02#ibcon#*mode == 0, iclass 34, count 2 2006.246.08:00:08.02#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.08:00:08.02#ibcon#[25=AT01-08\r\n] 2006.246.08:00:08.02#ibcon#*before write, iclass 34, count 2 2006.246.08:00:08.02#ibcon#enter sib2, iclass 34, count 2 2006.246.08:00:08.02#ibcon#flushed, iclass 34, count 2 2006.246.08:00:08.02#ibcon#about to write, iclass 34, count 2 2006.246.08:00:08.02#ibcon#wrote, iclass 34, count 2 2006.246.08:00:08.02#ibcon#about to read 3, iclass 34, count 2 2006.246.08:00:08.05#ibcon#read 3, iclass 34, count 2 2006.246.08:00:08.05#ibcon#about to read 4, iclass 34, count 2 2006.246.08:00:08.05#ibcon#read 4, iclass 34, count 2 2006.246.08:00:08.05#ibcon#about to read 5, iclass 34, count 2 2006.246.08:00:08.05#ibcon#read 5, iclass 34, count 2 2006.246.08:00:08.05#ibcon#about to read 6, iclass 34, count 2 2006.246.08:00:08.05#ibcon#read 6, iclass 34, count 2 2006.246.08:00:08.05#ibcon#end of sib2, iclass 34, count 2 2006.246.08:00:08.05#ibcon#*after write, iclass 34, count 2 2006.246.08:00:08.05#ibcon#*before return 0, iclass 34, count 2 2006.246.08:00:08.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:08.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:08.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.08:00:08.05#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:08.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:08.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:08.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:08.17#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:00:08.17#ibcon#first serial, iclass 34, count 0 2006.246.08:00:08.17#ibcon#enter sib2, iclass 34, count 0 2006.246.08:00:08.17#ibcon#flushed, iclass 34, count 0 2006.246.08:00:08.17#ibcon#about to write, iclass 34, count 0 2006.246.08:00:08.17#ibcon#wrote, iclass 34, count 0 2006.246.08:00:08.17#ibcon#about to read 3, iclass 34, count 0 2006.246.08:00:08.19#ibcon#read 3, iclass 34, count 0 2006.246.08:00:08.19#ibcon#about to read 4, iclass 34, count 0 2006.246.08:00:08.19#ibcon#read 4, iclass 34, count 0 2006.246.08:00:08.19#ibcon#about to read 5, iclass 34, count 0 2006.246.08:00:08.19#ibcon#read 5, iclass 34, count 0 2006.246.08:00:08.19#ibcon#about to read 6, iclass 34, count 0 2006.246.08:00:08.19#ibcon#read 6, iclass 34, count 0 2006.246.08:00:08.19#ibcon#end of sib2, iclass 34, count 0 2006.246.08:00:08.19#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:00:08.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:00:08.19#ibcon#[25=USB\r\n] 2006.246.08:00:08.19#ibcon#*before write, iclass 34, count 0 2006.246.08:00:08.19#ibcon#enter sib2, iclass 34, count 0 2006.246.08:00:08.19#ibcon#flushed, iclass 34, count 0 2006.246.08:00:08.19#ibcon#about to write, iclass 34, count 0 2006.246.08:00:08.19#ibcon#wrote, iclass 34, count 0 2006.246.08:00:08.19#ibcon#about to read 3, iclass 34, count 0 2006.246.08:00:08.22#ibcon#read 3, iclass 34, count 0 2006.246.08:00:08.22#ibcon#about to read 4, iclass 34, count 0 2006.246.08:00:08.22#ibcon#read 4, iclass 34, count 0 2006.246.08:00:08.22#ibcon#about to read 5, iclass 34, count 0 2006.246.08:00:08.22#ibcon#read 5, iclass 34, count 0 2006.246.08:00:08.22#ibcon#about to read 6, iclass 34, count 0 2006.246.08:00:08.22#ibcon#read 6, iclass 34, count 0 2006.246.08:00:08.22#ibcon#end of sib2, iclass 34, count 0 2006.246.08:00:08.22#ibcon#*after write, iclass 34, count 0 2006.246.08:00:08.22#ibcon#*before return 0, iclass 34, count 0 2006.246.08:00:08.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:08.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:08.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:00:08.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:00:08.22$vc4f8/valo=2,572.99 2006.246.08:00:08.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.08:00:08.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.08:00:08.22#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:08.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:08.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:08.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:08.22#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:00:08.22#ibcon#first serial, iclass 36, count 0 2006.246.08:00:08.22#ibcon#enter sib2, iclass 36, count 0 2006.246.08:00:08.22#ibcon#flushed, iclass 36, count 0 2006.246.08:00:08.22#ibcon#about to write, iclass 36, count 0 2006.246.08:00:08.22#ibcon#wrote, iclass 36, count 0 2006.246.08:00:08.22#ibcon#about to read 3, iclass 36, count 0 2006.246.08:00:08.24#ibcon#read 3, iclass 36, count 0 2006.246.08:00:08.24#ibcon#about to read 4, iclass 36, count 0 2006.246.08:00:08.24#ibcon#read 4, iclass 36, count 0 2006.246.08:00:08.24#ibcon#about to read 5, iclass 36, count 0 2006.246.08:00:08.24#ibcon#read 5, iclass 36, count 0 2006.246.08:00:08.24#ibcon#about to read 6, iclass 36, count 0 2006.246.08:00:08.24#ibcon#read 6, iclass 36, count 0 2006.246.08:00:08.24#ibcon#end of sib2, iclass 36, count 0 2006.246.08:00:08.24#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:00:08.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:00:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:00:08.24#ibcon#*before write, iclass 36, count 0 2006.246.08:00:08.24#ibcon#enter sib2, iclass 36, count 0 2006.246.08:00:08.24#ibcon#flushed, iclass 36, count 0 2006.246.08:00:08.24#ibcon#about to write, iclass 36, count 0 2006.246.08:00:08.24#ibcon#wrote, iclass 36, count 0 2006.246.08:00:08.24#ibcon#about to read 3, iclass 36, count 0 2006.246.08:00:08.28#ibcon#read 3, iclass 36, count 0 2006.246.08:00:08.28#ibcon#about to read 4, iclass 36, count 0 2006.246.08:00:08.28#ibcon#read 4, iclass 36, count 0 2006.246.08:00:08.28#ibcon#about to read 5, iclass 36, count 0 2006.246.08:00:08.28#ibcon#read 5, iclass 36, count 0 2006.246.08:00:08.28#ibcon#about to read 6, iclass 36, count 0 2006.246.08:00:08.28#ibcon#read 6, iclass 36, count 0 2006.246.08:00:08.28#ibcon#end of sib2, iclass 36, count 0 2006.246.08:00:08.28#ibcon#*after write, iclass 36, count 0 2006.246.08:00:08.28#ibcon#*before return 0, iclass 36, count 0 2006.246.08:00:08.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:08.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:08.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:00:08.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:00:08.28$vc4f8/va=2,7 2006.246.08:00:08.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.08:00:08.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.08:00:08.28#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:08.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:08.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:08.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:08.34#ibcon#enter wrdev, iclass 38, count 2 2006.246.08:00:08.34#ibcon#first serial, iclass 38, count 2 2006.246.08:00:08.34#ibcon#enter sib2, iclass 38, count 2 2006.246.08:00:08.34#ibcon#flushed, iclass 38, count 2 2006.246.08:00:08.34#ibcon#about to write, iclass 38, count 2 2006.246.08:00:08.34#ibcon#wrote, iclass 38, count 2 2006.246.08:00:08.34#ibcon#about to read 3, iclass 38, count 2 2006.246.08:00:08.36#ibcon#read 3, iclass 38, count 2 2006.246.08:00:08.36#ibcon#about to read 4, iclass 38, count 2 2006.246.08:00:08.36#ibcon#read 4, iclass 38, count 2 2006.246.08:00:08.36#ibcon#about to read 5, iclass 38, count 2 2006.246.08:00:08.36#ibcon#read 5, iclass 38, count 2 2006.246.08:00:08.36#ibcon#about to read 6, iclass 38, count 2 2006.246.08:00:08.36#ibcon#read 6, iclass 38, count 2 2006.246.08:00:08.36#ibcon#end of sib2, iclass 38, count 2 2006.246.08:00:08.36#ibcon#*mode == 0, iclass 38, count 2 2006.246.08:00:08.36#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.08:00:08.36#ibcon#[25=AT02-07\r\n] 2006.246.08:00:08.36#ibcon#*before write, iclass 38, count 2 2006.246.08:00:08.36#ibcon#enter sib2, iclass 38, count 2 2006.246.08:00:08.36#ibcon#flushed, iclass 38, count 2 2006.246.08:00:08.36#ibcon#about to write, iclass 38, count 2 2006.246.08:00:08.36#ibcon#wrote, iclass 38, count 2 2006.246.08:00:08.36#ibcon#about to read 3, iclass 38, count 2 2006.246.08:00:08.39#ibcon#read 3, iclass 38, count 2 2006.246.08:00:08.39#ibcon#about to read 4, iclass 38, count 2 2006.246.08:00:08.39#ibcon#read 4, iclass 38, count 2 2006.246.08:00:08.39#ibcon#about to read 5, iclass 38, count 2 2006.246.08:00:08.39#ibcon#read 5, iclass 38, count 2 2006.246.08:00:08.39#ibcon#about to read 6, iclass 38, count 2 2006.246.08:00:08.39#ibcon#read 6, iclass 38, count 2 2006.246.08:00:08.39#ibcon#end of sib2, iclass 38, count 2 2006.246.08:00:08.39#ibcon#*after write, iclass 38, count 2 2006.246.08:00:08.39#ibcon#*before return 0, iclass 38, count 2 2006.246.08:00:08.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:08.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:08.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.08:00:08.39#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:08.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:08.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:08.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:08.51#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:00:08.51#ibcon#first serial, iclass 38, count 0 2006.246.08:00:08.51#ibcon#enter sib2, iclass 38, count 0 2006.246.08:00:08.51#ibcon#flushed, iclass 38, count 0 2006.246.08:00:08.51#ibcon#about to write, iclass 38, count 0 2006.246.08:00:08.51#ibcon#wrote, iclass 38, count 0 2006.246.08:00:08.51#ibcon#about to read 3, iclass 38, count 0 2006.246.08:00:08.53#ibcon#read 3, iclass 38, count 0 2006.246.08:00:08.53#ibcon#about to read 4, iclass 38, count 0 2006.246.08:00:08.53#ibcon#read 4, iclass 38, count 0 2006.246.08:00:08.53#ibcon#about to read 5, iclass 38, count 0 2006.246.08:00:08.53#ibcon#read 5, iclass 38, count 0 2006.246.08:00:08.53#ibcon#about to read 6, iclass 38, count 0 2006.246.08:00:08.53#ibcon#read 6, iclass 38, count 0 2006.246.08:00:08.53#ibcon#end of sib2, iclass 38, count 0 2006.246.08:00:08.53#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:00:08.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:00:08.53#ibcon#[25=USB\r\n] 2006.246.08:00:08.53#ibcon#*before write, iclass 38, count 0 2006.246.08:00:08.53#ibcon#enter sib2, iclass 38, count 0 2006.246.08:00:08.53#ibcon#flushed, iclass 38, count 0 2006.246.08:00:08.53#ibcon#about to write, iclass 38, count 0 2006.246.08:00:08.53#ibcon#wrote, iclass 38, count 0 2006.246.08:00:08.53#ibcon#about to read 3, iclass 38, count 0 2006.246.08:00:08.56#ibcon#read 3, iclass 38, count 0 2006.246.08:00:08.56#ibcon#about to read 4, iclass 38, count 0 2006.246.08:00:08.56#ibcon#read 4, iclass 38, count 0 2006.246.08:00:08.56#ibcon#about to read 5, iclass 38, count 0 2006.246.08:00:08.56#ibcon#read 5, iclass 38, count 0 2006.246.08:00:08.56#ibcon#about to read 6, iclass 38, count 0 2006.246.08:00:08.56#ibcon#read 6, iclass 38, count 0 2006.246.08:00:08.56#ibcon#end of sib2, iclass 38, count 0 2006.246.08:00:08.56#ibcon#*after write, iclass 38, count 0 2006.246.08:00:08.56#ibcon#*before return 0, iclass 38, count 0 2006.246.08:00:08.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:08.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:08.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:00:08.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:00:08.56$vc4f8/valo=3,672.99 2006.246.08:00:08.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.08:00:08.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.08:00:08.56#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:08.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:08.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:08.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:08.56#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:00:08.56#ibcon#first serial, iclass 40, count 0 2006.246.08:00:08.56#ibcon#enter sib2, iclass 40, count 0 2006.246.08:00:08.56#ibcon#flushed, iclass 40, count 0 2006.246.08:00:08.56#ibcon#about to write, iclass 40, count 0 2006.246.08:00:08.56#ibcon#wrote, iclass 40, count 0 2006.246.08:00:08.56#ibcon#about to read 3, iclass 40, count 0 2006.246.08:00:08.58#ibcon#read 3, iclass 40, count 0 2006.246.08:00:08.58#ibcon#about to read 4, iclass 40, count 0 2006.246.08:00:08.58#ibcon#read 4, iclass 40, count 0 2006.246.08:00:08.58#ibcon#about to read 5, iclass 40, count 0 2006.246.08:00:08.58#ibcon#read 5, iclass 40, count 0 2006.246.08:00:08.58#ibcon#about to read 6, iclass 40, count 0 2006.246.08:00:08.58#ibcon#read 6, iclass 40, count 0 2006.246.08:00:08.58#ibcon#end of sib2, iclass 40, count 0 2006.246.08:00:08.58#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:00:08.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:00:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:00:08.58#ibcon#*before write, iclass 40, count 0 2006.246.08:00:08.58#ibcon#enter sib2, iclass 40, count 0 2006.246.08:00:08.58#ibcon#flushed, iclass 40, count 0 2006.246.08:00:08.58#ibcon#about to write, iclass 40, count 0 2006.246.08:00:08.58#ibcon#wrote, iclass 40, count 0 2006.246.08:00:08.58#ibcon#about to read 3, iclass 40, count 0 2006.246.08:00:08.62#ibcon#read 3, iclass 40, count 0 2006.246.08:00:08.62#ibcon#about to read 4, iclass 40, count 0 2006.246.08:00:08.62#ibcon#read 4, iclass 40, count 0 2006.246.08:00:08.62#ibcon#about to read 5, iclass 40, count 0 2006.246.08:00:08.62#ibcon#read 5, iclass 40, count 0 2006.246.08:00:08.62#ibcon#about to read 6, iclass 40, count 0 2006.246.08:00:08.62#ibcon#read 6, iclass 40, count 0 2006.246.08:00:08.62#ibcon#end of sib2, iclass 40, count 0 2006.246.08:00:08.62#ibcon#*after write, iclass 40, count 0 2006.246.08:00:08.62#ibcon#*before return 0, iclass 40, count 0 2006.246.08:00:08.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:08.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:08.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:00:08.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:00:08.62$vc4f8/va=3,6 2006.246.08:00:08.62#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.08:00:08.62#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.08:00:08.62#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:08.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:08.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:08.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:08.68#ibcon#enter wrdev, iclass 4, count 2 2006.246.08:00:08.68#ibcon#first serial, iclass 4, count 2 2006.246.08:00:08.68#ibcon#enter sib2, iclass 4, count 2 2006.246.08:00:08.68#ibcon#flushed, iclass 4, count 2 2006.246.08:00:08.68#ibcon#about to write, iclass 4, count 2 2006.246.08:00:08.68#ibcon#wrote, iclass 4, count 2 2006.246.08:00:08.68#ibcon#about to read 3, iclass 4, count 2 2006.246.08:00:08.71#ibcon#read 3, iclass 4, count 2 2006.246.08:00:08.71#ibcon#about to read 4, iclass 4, count 2 2006.246.08:00:08.71#ibcon#read 4, iclass 4, count 2 2006.246.08:00:08.71#ibcon#about to read 5, iclass 4, count 2 2006.246.08:00:08.71#ibcon#read 5, iclass 4, count 2 2006.246.08:00:08.71#ibcon#about to read 6, iclass 4, count 2 2006.246.08:00:08.71#ibcon#read 6, iclass 4, count 2 2006.246.08:00:08.71#ibcon#end of sib2, iclass 4, count 2 2006.246.08:00:08.71#ibcon#*mode == 0, iclass 4, count 2 2006.246.08:00:08.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.08:00:08.71#ibcon#[25=AT03-06\r\n] 2006.246.08:00:08.71#ibcon#*before write, iclass 4, count 2 2006.246.08:00:08.71#ibcon#enter sib2, iclass 4, count 2 2006.246.08:00:08.71#ibcon#flushed, iclass 4, count 2 2006.246.08:00:08.71#ibcon#about to write, iclass 4, count 2 2006.246.08:00:08.71#ibcon#wrote, iclass 4, count 2 2006.246.08:00:08.71#ibcon#about to read 3, iclass 4, count 2 2006.246.08:00:08.74#ibcon#read 3, iclass 4, count 2 2006.246.08:00:08.74#ibcon#about to read 4, iclass 4, count 2 2006.246.08:00:08.74#ibcon#read 4, iclass 4, count 2 2006.246.08:00:08.74#ibcon#about to read 5, iclass 4, count 2 2006.246.08:00:08.74#ibcon#read 5, iclass 4, count 2 2006.246.08:00:08.74#ibcon#about to read 6, iclass 4, count 2 2006.246.08:00:08.74#ibcon#read 6, iclass 4, count 2 2006.246.08:00:08.74#ibcon#end of sib2, iclass 4, count 2 2006.246.08:00:08.74#ibcon#*after write, iclass 4, count 2 2006.246.08:00:08.74#ibcon#*before return 0, iclass 4, count 2 2006.246.08:00:08.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:08.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:08.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.08:00:08.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:08.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:08.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:08.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:08.86#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:00:08.86#ibcon#first serial, iclass 4, count 0 2006.246.08:00:08.86#ibcon#enter sib2, iclass 4, count 0 2006.246.08:00:08.86#ibcon#flushed, iclass 4, count 0 2006.246.08:00:08.86#ibcon#about to write, iclass 4, count 0 2006.246.08:00:08.86#ibcon#wrote, iclass 4, count 0 2006.246.08:00:08.86#ibcon#about to read 3, iclass 4, count 0 2006.246.08:00:08.88#ibcon#read 3, iclass 4, count 0 2006.246.08:00:08.88#ibcon#about to read 4, iclass 4, count 0 2006.246.08:00:08.88#ibcon#read 4, iclass 4, count 0 2006.246.08:00:08.88#ibcon#about to read 5, iclass 4, count 0 2006.246.08:00:08.88#ibcon#read 5, iclass 4, count 0 2006.246.08:00:08.88#ibcon#about to read 6, iclass 4, count 0 2006.246.08:00:08.88#ibcon#read 6, iclass 4, count 0 2006.246.08:00:08.88#ibcon#end of sib2, iclass 4, count 0 2006.246.08:00:08.88#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:00:08.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:00:08.88#ibcon#[25=USB\r\n] 2006.246.08:00:08.88#ibcon#*before write, iclass 4, count 0 2006.246.08:00:08.88#ibcon#enter sib2, iclass 4, count 0 2006.246.08:00:08.88#ibcon#flushed, iclass 4, count 0 2006.246.08:00:08.88#ibcon#about to write, iclass 4, count 0 2006.246.08:00:08.88#ibcon#wrote, iclass 4, count 0 2006.246.08:00:08.88#ibcon#about to read 3, iclass 4, count 0 2006.246.08:00:08.91#ibcon#read 3, iclass 4, count 0 2006.246.08:00:08.91#ibcon#about to read 4, iclass 4, count 0 2006.246.08:00:08.91#ibcon#read 4, iclass 4, count 0 2006.246.08:00:08.91#ibcon#about to read 5, iclass 4, count 0 2006.246.08:00:08.91#ibcon#read 5, iclass 4, count 0 2006.246.08:00:08.91#ibcon#about to read 6, iclass 4, count 0 2006.246.08:00:08.91#ibcon#read 6, iclass 4, count 0 2006.246.08:00:08.91#ibcon#end of sib2, iclass 4, count 0 2006.246.08:00:08.91#ibcon#*after write, iclass 4, count 0 2006.246.08:00:08.91#ibcon#*before return 0, iclass 4, count 0 2006.246.08:00:08.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:08.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:08.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:00:08.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:00:08.91$vc4f8/valo=4,832.99 2006.246.08:00:08.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.08:00:08.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.08:00:08.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:08.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:08.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:08.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:08.91#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:00:08.91#ibcon#first serial, iclass 6, count 0 2006.246.08:00:08.91#ibcon#enter sib2, iclass 6, count 0 2006.246.08:00:08.91#ibcon#flushed, iclass 6, count 0 2006.246.08:00:08.91#ibcon#about to write, iclass 6, count 0 2006.246.08:00:08.91#ibcon#wrote, iclass 6, count 0 2006.246.08:00:08.91#ibcon#about to read 3, iclass 6, count 0 2006.246.08:00:08.93#ibcon#read 3, iclass 6, count 0 2006.246.08:00:08.93#ibcon#about to read 4, iclass 6, count 0 2006.246.08:00:08.93#ibcon#read 4, iclass 6, count 0 2006.246.08:00:08.93#ibcon#about to read 5, iclass 6, count 0 2006.246.08:00:08.93#ibcon#read 5, iclass 6, count 0 2006.246.08:00:08.93#ibcon#about to read 6, iclass 6, count 0 2006.246.08:00:08.93#ibcon#read 6, iclass 6, count 0 2006.246.08:00:08.93#ibcon#end of sib2, iclass 6, count 0 2006.246.08:00:08.93#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:00:08.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:00:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:00:08.93#ibcon#*before write, iclass 6, count 0 2006.246.08:00:08.93#ibcon#enter sib2, iclass 6, count 0 2006.246.08:00:08.93#ibcon#flushed, iclass 6, count 0 2006.246.08:00:08.93#ibcon#about to write, iclass 6, count 0 2006.246.08:00:08.93#ibcon#wrote, iclass 6, count 0 2006.246.08:00:08.93#ibcon#about to read 3, iclass 6, count 0 2006.246.08:00:08.97#ibcon#read 3, iclass 6, count 0 2006.246.08:00:08.97#ibcon#about to read 4, iclass 6, count 0 2006.246.08:00:08.97#ibcon#read 4, iclass 6, count 0 2006.246.08:00:08.97#ibcon#about to read 5, iclass 6, count 0 2006.246.08:00:08.97#ibcon#read 5, iclass 6, count 0 2006.246.08:00:08.97#ibcon#about to read 6, iclass 6, count 0 2006.246.08:00:08.97#ibcon#read 6, iclass 6, count 0 2006.246.08:00:08.97#ibcon#end of sib2, iclass 6, count 0 2006.246.08:00:08.97#ibcon#*after write, iclass 6, count 0 2006.246.08:00:08.97#ibcon#*before return 0, iclass 6, count 0 2006.246.08:00:08.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:08.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:08.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:00:08.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:00:08.97$vc4f8/va=4,7 2006.246.08:00:08.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.08:00:08.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.08:00:08.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:08.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:09.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:09.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:09.03#ibcon#enter wrdev, iclass 10, count 2 2006.246.08:00:09.03#ibcon#first serial, iclass 10, count 2 2006.246.08:00:09.03#ibcon#enter sib2, iclass 10, count 2 2006.246.08:00:09.03#ibcon#flushed, iclass 10, count 2 2006.246.08:00:09.03#ibcon#about to write, iclass 10, count 2 2006.246.08:00:09.03#ibcon#wrote, iclass 10, count 2 2006.246.08:00:09.03#ibcon#about to read 3, iclass 10, count 2 2006.246.08:00:09.05#ibcon#read 3, iclass 10, count 2 2006.246.08:00:09.05#ibcon#about to read 4, iclass 10, count 2 2006.246.08:00:09.05#ibcon#read 4, iclass 10, count 2 2006.246.08:00:09.05#ibcon#about to read 5, iclass 10, count 2 2006.246.08:00:09.05#ibcon#read 5, iclass 10, count 2 2006.246.08:00:09.05#ibcon#about to read 6, iclass 10, count 2 2006.246.08:00:09.05#ibcon#read 6, iclass 10, count 2 2006.246.08:00:09.05#ibcon#end of sib2, iclass 10, count 2 2006.246.08:00:09.05#ibcon#*mode == 0, iclass 10, count 2 2006.246.08:00:09.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.08:00:09.05#ibcon#[25=AT04-07\r\n] 2006.246.08:00:09.05#ibcon#*before write, iclass 10, count 2 2006.246.08:00:09.05#ibcon#enter sib2, iclass 10, count 2 2006.246.08:00:09.05#ibcon#flushed, iclass 10, count 2 2006.246.08:00:09.05#ibcon#about to write, iclass 10, count 2 2006.246.08:00:09.05#ibcon#wrote, iclass 10, count 2 2006.246.08:00:09.05#ibcon#about to read 3, iclass 10, count 2 2006.246.08:00:09.08#ibcon#read 3, iclass 10, count 2 2006.246.08:00:09.08#ibcon#about to read 4, iclass 10, count 2 2006.246.08:00:09.08#ibcon#read 4, iclass 10, count 2 2006.246.08:00:09.08#ibcon#about to read 5, iclass 10, count 2 2006.246.08:00:09.08#ibcon#read 5, iclass 10, count 2 2006.246.08:00:09.08#ibcon#about to read 6, iclass 10, count 2 2006.246.08:00:09.08#ibcon#read 6, iclass 10, count 2 2006.246.08:00:09.08#ibcon#end of sib2, iclass 10, count 2 2006.246.08:00:09.08#ibcon#*after write, iclass 10, count 2 2006.246.08:00:09.08#ibcon#*before return 0, iclass 10, count 2 2006.246.08:00:09.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:09.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:09.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.08:00:09.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:09.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:09.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:09.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:09.20#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:00:09.20#ibcon#first serial, iclass 10, count 0 2006.246.08:00:09.20#ibcon#enter sib2, iclass 10, count 0 2006.246.08:00:09.20#ibcon#flushed, iclass 10, count 0 2006.246.08:00:09.20#ibcon#about to write, iclass 10, count 0 2006.246.08:00:09.20#ibcon#wrote, iclass 10, count 0 2006.246.08:00:09.20#ibcon#about to read 3, iclass 10, count 0 2006.246.08:00:09.22#ibcon#read 3, iclass 10, count 0 2006.246.08:00:09.22#ibcon#about to read 4, iclass 10, count 0 2006.246.08:00:09.22#ibcon#read 4, iclass 10, count 0 2006.246.08:00:09.22#ibcon#about to read 5, iclass 10, count 0 2006.246.08:00:09.22#ibcon#read 5, iclass 10, count 0 2006.246.08:00:09.22#ibcon#about to read 6, iclass 10, count 0 2006.246.08:00:09.22#ibcon#read 6, iclass 10, count 0 2006.246.08:00:09.22#ibcon#end of sib2, iclass 10, count 0 2006.246.08:00:09.22#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:00:09.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:00:09.22#ibcon#[25=USB\r\n] 2006.246.08:00:09.22#ibcon#*before write, iclass 10, count 0 2006.246.08:00:09.22#ibcon#enter sib2, iclass 10, count 0 2006.246.08:00:09.22#ibcon#flushed, iclass 10, count 0 2006.246.08:00:09.22#ibcon#about to write, iclass 10, count 0 2006.246.08:00:09.22#ibcon#wrote, iclass 10, count 0 2006.246.08:00:09.22#ibcon#about to read 3, iclass 10, count 0 2006.246.08:00:09.25#ibcon#read 3, iclass 10, count 0 2006.246.08:00:09.25#ibcon#about to read 4, iclass 10, count 0 2006.246.08:00:09.25#ibcon#read 4, iclass 10, count 0 2006.246.08:00:09.25#ibcon#about to read 5, iclass 10, count 0 2006.246.08:00:09.25#ibcon#read 5, iclass 10, count 0 2006.246.08:00:09.25#ibcon#about to read 6, iclass 10, count 0 2006.246.08:00:09.25#ibcon#read 6, iclass 10, count 0 2006.246.08:00:09.25#ibcon#end of sib2, iclass 10, count 0 2006.246.08:00:09.25#ibcon#*after write, iclass 10, count 0 2006.246.08:00:09.25#ibcon#*before return 0, iclass 10, count 0 2006.246.08:00:09.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:09.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:09.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:00:09.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:00:09.25$vc4f8/valo=5,652.99 2006.246.08:00:09.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.08:00:09.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.08:00:09.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:09.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:09.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:09.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:09.25#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:00:09.25#ibcon#first serial, iclass 12, count 0 2006.246.08:00:09.25#ibcon#enter sib2, iclass 12, count 0 2006.246.08:00:09.25#ibcon#flushed, iclass 12, count 0 2006.246.08:00:09.25#ibcon#about to write, iclass 12, count 0 2006.246.08:00:09.25#ibcon#wrote, iclass 12, count 0 2006.246.08:00:09.25#ibcon#about to read 3, iclass 12, count 0 2006.246.08:00:09.27#ibcon#read 3, iclass 12, count 0 2006.246.08:00:09.27#ibcon#about to read 4, iclass 12, count 0 2006.246.08:00:09.27#ibcon#read 4, iclass 12, count 0 2006.246.08:00:09.27#ibcon#about to read 5, iclass 12, count 0 2006.246.08:00:09.27#ibcon#read 5, iclass 12, count 0 2006.246.08:00:09.27#ibcon#about to read 6, iclass 12, count 0 2006.246.08:00:09.27#ibcon#read 6, iclass 12, count 0 2006.246.08:00:09.27#ibcon#end of sib2, iclass 12, count 0 2006.246.08:00:09.27#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:00:09.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:00:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:00:09.27#ibcon#*before write, iclass 12, count 0 2006.246.08:00:09.27#ibcon#enter sib2, iclass 12, count 0 2006.246.08:00:09.27#ibcon#flushed, iclass 12, count 0 2006.246.08:00:09.27#ibcon#about to write, iclass 12, count 0 2006.246.08:00:09.27#ibcon#wrote, iclass 12, count 0 2006.246.08:00:09.27#ibcon#about to read 3, iclass 12, count 0 2006.246.08:00:09.31#ibcon#read 3, iclass 12, count 0 2006.246.08:00:09.31#ibcon#about to read 4, iclass 12, count 0 2006.246.08:00:09.31#ibcon#read 4, iclass 12, count 0 2006.246.08:00:09.31#ibcon#about to read 5, iclass 12, count 0 2006.246.08:00:09.31#ibcon#read 5, iclass 12, count 0 2006.246.08:00:09.31#ibcon#about to read 6, iclass 12, count 0 2006.246.08:00:09.31#ibcon#read 6, iclass 12, count 0 2006.246.08:00:09.31#ibcon#end of sib2, iclass 12, count 0 2006.246.08:00:09.31#ibcon#*after write, iclass 12, count 0 2006.246.08:00:09.31#ibcon#*before return 0, iclass 12, count 0 2006.246.08:00:09.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:09.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:09.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:00:09.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:00:09.31$vc4f8/va=5,7 2006.246.08:00:09.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.08:00:09.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.08:00:09.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:09.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:09.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:09.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:09.37#ibcon#enter wrdev, iclass 14, count 2 2006.246.08:00:09.37#ibcon#first serial, iclass 14, count 2 2006.246.08:00:09.37#ibcon#enter sib2, iclass 14, count 2 2006.246.08:00:09.37#ibcon#flushed, iclass 14, count 2 2006.246.08:00:09.37#ibcon#about to write, iclass 14, count 2 2006.246.08:00:09.37#ibcon#wrote, iclass 14, count 2 2006.246.08:00:09.37#ibcon#about to read 3, iclass 14, count 2 2006.246.08:00:09.39#ibcon#read 3, iclass 14, count 2 2006.246.08:00:09.39#ibcon#about to read 4, iclass 14, count 2 2006.246.08:00:09.39#ibcon#read 4, iclass 14, count 2 2006.246.08:00:09.39#ibcon#about to read 5, iclass 14, count 2 2006.246.08:00:09.39#ibcon#read 5, iclass 14, count 2 2006.246.08:00:09.39#ibcon#about to read 6, iclass 14, count 2 2006.246.08:00:09.39#ibcon#read 6, iclass 14, count 2 2006.246.08:00:09.39#ibcon#end of sib2, iclass 14, count 2 2006.246.08:00:09.39#ibcon#*mode == 0, iclass 14, count 2 2006.246.08:00:09.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.08:00:09.39#ibcon#[25=AT05-07\r\n] 2006.246.08:00:09.39#ibcon#*before write, iclass 14, count 2 2006.246.08:00:09.39#ibcon#enter sib2, iclass 14, count 2 2006.246.08:00:09.39#ibcon#flushed, iclass 14, count 2 2006.246.08:00:09.39#ibcon#about to write, iclass 14, count 2 2006.246.08:00:09.39#ibcon#wrote, iclass 14, count 2 2006.246.08:00:09.39#ibcon#about to read 3, iclass 14, count 2 2006.246.08:00:09.42#ibcon#read 3, iclass 14, count 2 2006.246.08:00:09.42#ibcon#about to read 4, iclass 14, count 2 2006.246.08:00:09.42#ibcon#read 4, iclass 14, count 2 2006.246.08:00:09.42#ibcon#about to read 5, iclass 14, count 2 2006.246.08:00:09.42#ibcon#read 5, iclass 14, count 2 2006.246.08:00:09.42#ibcon#about to read 6, iclass 14, count 2 2006.246.08:00:09.42#ibcon#read 6, iclass 14, count 2 2006.246.08:00:09.42#ibcon#end of sib2, iclass 14, count 2 2006.246.08:00:09.42#ibcon#*after write, iclass 14, count 2 2006.246.08:00:09.42#ibcon#*before return 0, iclass 14, count 2 2006.246.08:00:09.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:09.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:09.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.08:00:09.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:09.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:09.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:09.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:09.54#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:00:09.54#ibcon#first serial, iclass 14, count 0 2006.246.08:00:09.54#ibcon#enter sib2, iclass 14, count 0 2006.246.08:00:09.54#ibcon#flushed, iclass 14, count 0 2006.246.08:00:09.54#ibcon#about to write, iclass 14, count 0 2006.246.08:00:09.54#ibcon#wrote, iclass 14, count 0 2006.246.08:00:09.54#ibcon#about to read 3, iclass 14, count 0 2006.246.08:00:09.56#ibcon#read 3, iclass 14, count 0 2006.246.08:00:09.56#ibcon#about to read 4, iclass 14, count 0 2006.246.08:00:09.56#ibcon#read 4, iclass 14, count 0 2006.246.08:00:09.56#ibcon#about to read 5, iclass 14, count 0 2006.246.08:00:09.56#ibcon#read 5, iclass 14, count 0 2006.246.08:00:09.56#ibcon#about to read 6, iclass 14, count 0 2006.246.08:00:09.56#ibcon#read 6, iclass 14, count 0 2006.246.08:00:09.56#ibcon#end of sib2, iclass 14, count 0 2006.246.08:00:09.56#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:00:09.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:00:09.56#ibcon#[25=USB\r\n] 2006.246.08:00:09.56#ibcon#*before write, iclass 14, count 0 2006.246.08:00:09.56#ibcon#enter sib2, iclass 14, count 0 2006.246.08:00:09.56#ibcon#flushed, iclass 14, count 0 2006.246.08:00:09.56#ibcon#about to write, iclass 14, count 0 2006.246.08:00:09.56#ibcon#wrote, iclass 14, count 0 2006.246.08:00:09.56#ibcon#about to read 3, iclass 14, count 0 2006.246.08:00:09.59#ibcon#read 3, iclass 14, count 0 2006.246.08:00:09.59#ibcon#about to read 4, iclass 14, count 0 2006.246.08:00:09.59#ibcon#read 4, iclass 14, count 0 2006.246.08:00:09.59#ibcon#about to read 5, iclass 14, count 0 2006.246.08:00:09.59#ibcon#read 5, iclass 14, count 0 2006.246.08:00:09.59#ibcon#about to read 6, iclass 14, count 0 2006.246.08:00:09.59#ibcon#read 6, iclass 14, count 0 2006.246.08:00:09.59#ibcon#end of sib2, iclass 14, count 0 2006.246.08:00:09.59#ibcon#*after write, iclass 14, count 0 2006.246.08:00:09.59#ibcon#*before return 0, iclass 14, count 0 2006.246.08:00:09.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:09.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:09.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:00:09.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:00:09.59$vc4f8/valo=6,772.99 2006.246.08:00:09.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.08:00:09.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.08:00:09.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:09.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:09.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:09.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:09.59#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:00:09.59#ibcon#first serial, iclass 16, count 0 2006.246.08:00:09.59#ibcon#enter sib2, iclass 16, count 0 2006.246.08:00:09.59#ibcon#flushed, iclass 16, count 0 2006.246.08:00:09.59#ibcon#about to write, iclass 16, count 0 2006.246.08:00:09.59#ibcon#wrote, iclass 16, count 0 2006.246.08:00:09.59#ibcon#about to read 3, iclass 16, count 0 2006.246.08:00:09.61#ibcon#read 3, iclass 16, count 0 2006.246.08:00:09.61#ibcon#about to read 4, iclass 16, count 0 2006.246.08:00:09.61#ibcon#read 4, iclass 16, count 0 2006.246.08:00:09.61#ibcon#about to read 5, iclass 16, count 0 2006.246.08:00:09.61#ibcon#read 5, iclass 16, count 0 2006.246.08:00:09.61#ibcon#about to read 6, iclass 16, count 0 2006.246.08:00:09.62#ibcon#read 6, iclass 16, count 0 2006.246.08:00:09.62#ibcon#end of sib2, iclass 16, count 0 2006.246.08:00:09.62#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:00:09.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:00:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:00:09.62#ibcon#*before write, iclass 16, count 0 2006.246.08:00:09.62#ibcon#enter sib2, iclass 16, count 0 2006.246.08:00:09.62#ibcon#flushed, iclass 16, count 0 2006.246.08:00:09.62#ibcon#about to write, iclass 16, count 0 2006.246.08:00:09.62#ibcon#wrote, iclass 16, count 0 2006.246.08:00:09.62#ibcon#about to read 3, iclass 16, count 0 2006.246.08:00:09.66#ibcon#read 3, iclass 16, count 0 2006.246.08:00:09.66#ibcon#about to read 4, iclass 16, count 0 2006.246.08:00:09.66#ibcon#read 4, iclass 16, count 0 2006.246.08:00:09.66#ibcon#about to read 5, iclass 16, count 0 2006.246.08:00:09.66#ibcon#read 5, iclass 16, count 0 2006.246.08:00:09.66#ibcon#about to read 6, iclass 16, count 0 2006.246.08:00:09.66#ibcon#read 6, iclass 16, count 0 2006.246.08:00:09.66#ibcon#end of sib2, iclass 16, count 0 2006.246.08:00:09.66#ibcon#*after write, iclass 16, count 0 2006.246.08:00:09.66#ibcon#*before return 0, iclass 16, count 0 2006.246.08:00:09.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:09.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:09.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:00:09.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:00:09.66$vc4f8/va=6,7 2006.246.08:00:09.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.08:00:09.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.08:00:09.66#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:09.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:00:09.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:00:09.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:00:09.71#ibcon#enter wrdev, iclass 18, count 2 2006.246.08:00:09.71#ibcon#first serial, iclass 18, count 2 2006.246.08:00:09.71#ibcon#enter sib2, iclass 18, count 2 2006.246.08:00:09.71#ibcon#flushed, iclass 18, count 2 2006.246.08:00:09.71#ibcon#about to write, iclass 18, count 2 2006.246.08:00:09.71#ibcon#wrote, iclass 18, count 2 2006.246.08:00:09.71#ibcon#about to read 3, iclass 18, count 2 2006.246.08:00:09.73#ibcon#read 3, iclass 18, count 2 2006.246.08:00:09.73#ibcon#about to read 4, iclass 18, count 2 2006.246.08:00:09.73#ibcon#read 4, iclass 18, count 2 2006.246.08:00:09.73#ibcon#about to read 5, iclass 18, count 2 2006.246.08:00:09.73#ibcon#read 5, iclass 18, count 2 2006.246.08:00:09.73#ibcon#about to read 6, iclass 18, count 2 2006.246.08:00:09.73#ibcon#read 6, iclass 18, count 2 2006.246.08:00:09.73#ibcon#end of sib2, iclass 18, count 2 2006.246.08:00:09.73#ibcon#*mode == 0, iclass 18, count 2 2006.246.08:00:09.73#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.08:00:09.73#ibcon#[25=AT06-07\r\n] 2006.246.08:00:09.73#ibcon#*before write, iclass 18, count 2 2006.246.08:00:09.73#ibcon#enter sib2, iclass 18, count 2 2006.246.08:00:09.73#ibcon#flushed, iclass 18, count 2 2006.246.08:00:09.73#ibcon#about to write, iclass 18, count 2 2006.246.08:00:09.73#ibcon#wrote, iclass 18, count 2 2006.246.08:00:09.73#ibcon#about to read 3, iclass 18, count 2 2006.246.08:00:09.76#ibcon#read 3, iclass 18, count 2 2006.246.08:00:09.76#ibcon#about to read 4, iclass 18, count 2 2006.246.08:00:09.76#ibcon#read 4, iclass 18, count 2 2006.246.08:00:09.76#ibcon#about to read 5, iclass 18, count 2 2006.246.08:00:09.76#ibcon#read 5, iclass 18, count 2 2006.246.08:00:09.76#ibcon#about to read 6, iclass 18, count 2 2006.246.08:00:09.76#ibcon#read 6, iclass 18, count 2 2006.246.08:00:09.76#ibcon#end of sib2, iclass 18, count 2 2006.246.08:00:09.76#ibcon#*after write, iclass 18, count 2 2006.246.08:00:09.76#ibcon#*before return 0, iclass 18, count 2 2006.246.08:00:09.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:00:09.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:00:09.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.08:00:09.76#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:09.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:00:09.88#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:00:09.88#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:00:09.88#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:00:09.88#ibcon#first serial, iclass 18, count 0 2006.246.08:00:09.88#ibcon#enter sib2, iclass 18, count 0 2006.246.08:00:09.88#ibcon#flushed, iclass 18, count 0 2006.246.08:00:09.88#ibcon#about to write, iclass 18, count 0 2006.246.08:00:09.88#ibcon#wrote, iclass 18, count 0 2006.246.08:00:09.88#ibcon#about to read 3, iclass 18, count 0 2006.246.08:00:09.90#ibcon#read 3, iclass 18, count 0 2006.246.08:00:09.90#ibcon#about to read 4, iclass 18, count 0 2006.246.08:00:09.90#ibcon#read 4, iclass 18, count 0 2006.246.08:00:09.90#ibcon#about to read 5, iclass 18, count 0 2006.246.08:00:09.90#ibcon#read 5, iclass 18, count 0 2006.246.08:00:09.90#ibcon#about to read 6, iclass 18, count 0 2006.246.08:00:09.90#ibcon#read 6, iclass 18, count 0 2006.246.08:00:09.90#ibcon#end of sib2, iclass 18, count 0 2006.246.08:00:09.90#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:00:09.90#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:00:09.90#ibcon#[25=USB\r\n] 2006.246.08:00:09.90#ibcon#*before write, iclass 18, count 0 2006.246.08:00:09.90#ibcon#enter sib2, iclass 18, count 0 2006.246.08:00:09.90#ibcon#flushed, iclass 18, count 0 2006.246.08:00:09.90#ibcon#about to write, iclass 18, count 0 2006.246.08:00:09.90#ibcon#wrote, iclass 18, count 0 2006.246.08:00:09.90#ibcon#about to read 3, iclass 18, count 0 2006.246.08:00:09.93#ibcon#read 3, iclass 18, count 0 2006.246.08:00:09.93#ibcon#about to read 4, iclass 18, count 0 2006.246.08:00:09.93#ibcon#read 4, iclass 18, count 0 2006.246.08:00:09.93#ibcon#about to read 5, iclass 18, count 0 2006.246.08:00:09.93#ibcon#read 5, iclass 18, count 0 2006.246.08:00:09.93#ibcon#about to read 6, iclass 18, count 0 2006.246.08:00:09.93#ibcon#read 6, iclass 18, count 0 2006.246.08:00:09.93#ibcon#end of sib2, iclass 18, count 0 2006.246.08:00:09.93#ibcon#*after write, iclass 18, count 0 2006.246.08:00:09.93#ibcon#*before return 0, iclass 18, count 0 2006.246.08:00:09.93#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:00:09.93#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:00:09.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:00:09.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:00:09.93$vc4f8/valo=7,832.99 2006.246.08:00:09.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.08:00:09.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.08:00:09.93#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:09.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:00:09.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:00:09.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:00:09.93#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:00:09.93#ibcon#first serial, iclass 20, count 0 2006.246.08:00:09.93#ibcon#enter sib2, iclass 20, count 0 2006.246.08:00:09.93#ibcon#flushed, iclass 20, count 0 2006.246.08:00:09.93#ibcon#about to write, iclass 20, count 0 2006.246.08:00:09.93#ibcon#wrote, iclass 20, count 0 2006.246.08:00:09.93#ibcon#about to read 3, iclass 20, count 0 2006.246.08:00:09.95#ibcon#read 3, iclass 20, count 0 2006.246.08:00:09.95#ibcon#about to read 4, iclass 20, count 0 2006.246.08:00:09.95#ibcon#read 4, iclass 20, count 0 2006.246.08:00:09.95#ibcon#about to read 5, iclass 20, count 0 2006.246.08:00:09.95#ibcon#read 5, iclass 20, count 0 2006.246.08:00:09.95#ibcon#about to read 6, iclass 20, count 0 2006.246.08:00:09.95#ibcon#read 6, iclass 20, count 0 2006.246.08:00:09.95#ibcon#end of sib2, iclass 20, count 0 2006.246.08:00:09.95#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:00:09.95#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:00:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:00:09.95#ibcon#*before write, iclass 20, count 0 2006.246.08:00:09.95#ibcon#enter sib2, iclass 20, count 0 2006.246.08:00:09.95#ibcon#flushed, iclass 20, count 0 2006.246.08:00:09.95#ibcon#about to write, iclass 20, count 0 2006.246.08:00:09.95#ibcon#wrote, iclass 20, count 0 2006.246.08:00:09.95#ibcon#about to read 3, iclass 20, count 0 2006.246.08:00:09.99#ibcon#read 3, iclass 20, count 0 2006.246.08:00:09.99#ibcon#about to read 4, iclass 20, count 0 2006.246.08:00:09.99#ibcon#read 4, iclass 20, count 0 2006.246.08:00:09.99#ibcon#about to read 5, iclass 20, count 0 2006.246.08:00:09.99#ibcon#read 5, iclass 20, count 0 2006.246.08:00:09.99#ibcon#about to read 6, iclass 20, count 0 2006.246.08:00:09.99#ibcon#read 6, iclass 20, count 0 2006.246.08:00:09.99#ibcon#end of sib2, iclass 20, count 0 2006.246.08:00:09.99#ibcon#*after write, iclass 20, count 0 2006.246.08:00:09.99#ibcon#*before return 0, iclass 20, count 0 2006.246.08:00:09.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:00:09.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:00:09.99#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:00:09.99#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:00:09.99$vc4f8/va=7,7 2006.246.08:00:09.99#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.08:00:09.99#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.08:00:09.99#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:09.99#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:00:10.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:00:10.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:00:10.05#ibcon#enter wrdev, iclass 22, count 2 2006.246.08:00:10.05#ibcon#first serial, iclass 22, count 2 2006.246.08:00:10.05#ibcon#enter sib2, iclass 22, count 2 2006.246.08:00:10.05#ibcon#flushed, iclass 22, count 2 2006.246.08:00:10.05#ibcon#about to write, iclass 22, count 2 2006.246.08:00:10.05#ibcon#wrote, iclass 22, count 2 2006.246.08:00:10.05#ibcon#about to read 3, iclass 22, count 2 2006.246.08:00:10.07#ibcon#read 3, iclass 22, count 2 2006.246.08:00:10.07#ibcon#about to read 4, iclass 22, count 2 2006.246.08:00:10.07#ibcon#read 4, iclass 22, count 2 2006.246.08:00:10.07#ibcon#about to read 5, iclass 22, count 2 2006.246.08:00:10.07#ibcon#read 5, iclass 22, count 2 2006.246.08:00:10.07#ibcon#about to read 6, iclass 22, count 2 2006.246.08:00:10.07#ibcon#read 6, iclass 22, count 2 2006.246.08:00:10.07#ibcon#end of sib2, iclass 22, count 2 2006.246.08:00:10.07#ibcon#*mode == 0, iclass 22, count 2 2006.246.08:00:10.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.08:00:10.07#ibcon#[25=AT07-07\r\n] 2006.246.08:00:10.07#ibcon#*before write, iclass 22, count 2 2006.246.08:00:10.07#ibcon#enter sib2, iclass 22, count 2 2006.246.08:00:10.07#ibcon#flushed, iclass 22, count 2 2006.246.08:00:10.07#ibcon#about to write, iclass 22, count 2 2006.246.08:00:10.07#ibcon#wrote, iclass 22, count 2 2006.246.08:00:10.07#ibcon#about to read 3, iclass 22, count 2 2006.246.08:00:10.10#ibcon#read 3, iclass 22, count 2 2006.246.08:00:10.10#ibcon#about to read 4, iclass 22, count 2 2006.246.08:00:10.10#ibcon#read 4, iclass 22, count 2 2006.246.08:00:10.10#ibcon#about to read 5, iclass 22, count 2 2006.246.08:00:10.10#ibcon#read 5, iclass 22, count 2 2006.246.08:00:10.10#ibcon#about to read 6, iclass 22, count 2 2006.246.08:00:10.10#ibcon#read 6, iclass 22, count 2 2006.246.08:00:10.10#ibcon#end of sib2, iclass 22, count 2 2006.246.08:00:10.10#ibcon#*after write, iclass 22, count 2 2006.246.08:00:10.10#ibcon#*before return 0, iclass 22, count 2 2006.246.08:00:10.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:00:10.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:00:10.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.08:00:10.10#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:10.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:00:10.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:00:10.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:00:10.22#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:00:10.22#ibcon#first serial, iclass 22, count 0 2006.246.08:00:10.22#ibcon#enter sib2, iclass 22, count 0 2006.246.08:00:10.22#ibcon#flushed, iclass 22, count 0 2006.246.08:00:10.22#ibcon#about to write, iclass 22, count 0 2006.246.08:00:10.22#ibcon#wrote, iclass 22, count 0 2006.246.08:00:10.22#ibcon#about to read 3, iclass 22, count 0 2006.246.08:00:10.24#ibcon#read 3, iclass 22, count 0 2006.246.08:00:10.24#ibcon#about to read 4, iclass 22, count 0 2006.246.08:00:10.24#ibcon#read 4, iclass 22, count 0 2006.246.08:00:10.24#ibcon#about to read 5, iclass 22, count 0 2006.246.08:00:10.24#ibcon#read 5, iclass 22, count 0 2006.246.08:00:10.24#ibcon#about to read 6, iclass 22, count 0 2006.246.08:00:10.24#ibcon#read 6, iclass 22, count 0 2006.246.08:00:10.24#ibcon#end of sib2, iclass 22, count 0 2006.246.08:00:10.24#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:00:10.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:00:10.24#ibcon#[25=USB\r\n] 2006.246.08:00:10.24#ibcon#*before write, iclass 22, count 0 2006.246.08:00:10.24#ibcon#enter sib2, iclass 22, count 0 2006.246.08:00:10.24#ibcon#flushed, iclass 22, count 0 2006.246.08:00:10.24#ibcon#about to write, iclass 22, count 0 2006.246.08:00:10.24#ibcon#wrote, iclass 22, count 0 2006.246.08:00:10.24#ibcon#about to read 3, iclass 22, count 0 2006.246.08:00:10.27#ibcon#read 3, iclass 22, count 0 2006.246.08:00:10.27#ibcon#about to read 4, iclass 22, count 0 2006.246.08:00:10.27#ibcon#read 4, iclass 22, count 0 2006.246.08:00:10.27#ibcon#about to read 5, iclass 22, count 0 2006.246.08:00:10.27#ibcon#read 5, iclass 22, count 0 2006.246.08:00:10.27#ibcon#about to read 6, iclass 22, count 0 2006.246.08:00:10.27#ibcon#read 6, iclass 22, count 0 2006.246.08:00:10.27#ibcon#end of sib2, iclass 22, count 0 2006.246.08:00:10.27#ibcon#*after write, iclass 22, count 0 2006.246.08:00:10.27#ibcon#*before return 0, iclass 22, count 0 2006.246.08:00:10.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:00:10.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:00:10.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:00:10.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:00:10.27$vc4f8/valo=8,852.99 2006.246.08:00:10.27#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.08:00:10.27#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.08:00:10.27#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:10.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:00:10.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:00:10.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:00:10.27#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:00:10.27#ibcon#first serial, iclass 24, count 0 2006.246.08:00:10.27#ibcon#enter sib2, iclass 24, count 0 2006.246.08:00:10.27#ibcon#flushed, iclass 24, count 0 2006.246.08:00:10.27#ibcon#about to write, iclass 24, count 0 2006.246.08:00:10.27#ibcon#wrote, iclass 24, count 0 2006.246.08:00:10.27#ibcon#about to read 3, iclass 24, count 0 2006.246.08:00:10.29#ibcon#read 3, iclass 24, count 0 2006.246.08:00:10.29#ibcon#about to read 4, iclass 24, count 0 2006.246.08:00:10.29#ibcon#read 4, iclass 24, count 0 2006.246.08:00:10.29#ibcon#about to read 5, iclass 24, count 0 2006.246.08:00:10.29#ibcon#read 5, iclass 24, count 0 2006.246.08:00:10.29#ibcon#about to read 6, iclass 24, count 0 2006.246.08:00:10.29#ibcon#read 6, iclass 24, count 0 2006.246.08:00:10.29#ibcon#end of sib2, iclass 24, count 0 2006.246.08:00:10.29#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:00:10.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:00:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:00:10.29#ibcon#*before write, iclass 24, count 0 2006.246.08:00:10.29#ibcon#enter sib2, iclass 24, count 0 2006.246.08:00:10.29#ibcon#flushed, iclass 24, count 0 2006.246.08:00:10.29#ibcon#about to write, iclass 24, count 0 2006.246.08:00:10.29#ibcon#wrote, iclass 24, count 0 2006.246.08:00:10.29#ibcon#about to read 3, iclass 24, count 0 2006.246.08:00:10.33#ibcon#read 3, iclass 24, count 0 2006.246.08:00:10.33#ibcon#about to read 4, iclass 24, count 0 2006.246.08:00:10.33#ibcon#read 4, iclass 24, count 0 2006.246.08:00:10.33#ibcon#about to read 5, iclass 24, count 0 2006.246.08:00:10.33#ibcon#read 5, iclass 24, count 0 2006.246.08:00:10.33#ibcon#about to read 6, iclass 24, count 0 2006.246.08:00:10.33#ibcon#read 6, iclass 24, count 0 2006.246.08:00:10.33#ibcon#end of sib2, iclass 24, count 0 2006.246.08:00:10.33#ibcon#*after write, iclass 24, count 0 2006.246.08:00:10.33#ibcon#*before return 0, iclass 24, count 0 2006.246.08:00:10.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:00:10.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:00:10.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:00:10.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:00:10.33$vc4f8/va=8,8 2006.246.08:00:10.33#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.08:00:10.33#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.08:00:10.33#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:10.33#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:00:10.39#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:00:10.39#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:00:10.39#ibcon#enter wrdev, iclass 26, count 2 2006.246.08:00:10.39#ibcon#first serial, iclass 26, count 2 2006.246.08:00:10.39#ibcon#enter sib2, iclass 26, count 2 2006.246.08:00:10.39#ibcon#flushed, iclass 26, count 2 2006.246.08:00:10.39#ibcon#about to write, iclass 26, count 2 2006.246.08:00:10.39#ibcon#wrote, iclass 26, count 2 2006.246.08:00:10.39#ibcon#about to read 3, iclass 26, count 2 2006.246.08:00:10.41#ibcon#read 3, iclass 26, count 2 2006.246.08:00:10.41#ibcon#about to read 4, iclass 26, count 2 2006.246.08:00:10.41#ibcon#read 4, iclass 26, count 2 2006.246.08:00:10.41#ibcon#about to read 5, iclass 26, count 2 2006.246.08:00:10.41#ibcon#read 5, iclass 26, count 2 2006.246.08:00:10.41#ibcon#about to read 6, iclass 26, count 2 2006.246.08:00:10.41#ibcon#read 6, iclass 26, count 2 2006.246.08:00:10.41#ibcon#end of sib2, iclass 26, count 2 2006.246.08:00:10.41#ibcon#*mode == 0, iclass 26, count 2 2006.246.08:00:10.41#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.08:00:10.41#ibcon#[25=AT08-08\r\n] 2006.246.08:00:10.41#ibcon#*before write, iclass 26, count 2 2006.246.08:00:10.41#ibcon#enter sib2, iclass 26, count 2 2006.246.08:00:10.41#ibcon#flushed, iclass 26, count 2 2006.246.08:00:10.41#ibcon#about to write, iclass 26, count 2 2006.246.08:00:10.41#ibcon#wrote, iclass 26, count 2 2006.246.08:00:10.41#ibcon#about to read 3, iclass 26, count 2 2006.246.08:00:10.44#ibcon#read 3, iclass 26, count 2 2006.246.08:00:10.44#ibcon#about to read 4, iclass 26, count 2 2006.246.08:00:10.44#ibcon#read 4, iclass 26, count 2 2006.246.08:00:10.44#ibcon#about to read 5, iclass 26, count 2 2006.246.08:00:10.44#ibcon#read 5, iclass 26, count 2 2006.246.08:00:10.44#ibcon#about to read 6, iclass 26, count 2 2006.246.08:00:10.44#ibcon#read 6, iclass 26, count 2 2006.246.08:00:10.44#ibcon#end of sib2, iclass 26, count 2 2006.246.08:00:10.44#ibcon#*after write, iclass 26, count 2 2006.246.08:00:10.44#ibcon#*before return 0, iclass 26, count 2 2006.246.08:00:10.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:00:10.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:00:10.44#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.08:00:10.44#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:10.44#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:00:10.56#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:00:10.56#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:00:10.56#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:00:10.56#ibcon#first serial, iclass 26, count 0 2006.246.08:00:10.56#ibcon#enter sib2, iclass 26, count 0 2006.246.08:00:10.56#ibcon#flushed, iclass 26, count 0 2006.246.08:00:10.56#ibcon#about to write, iclass 26, count 0 2006.246.08:00:10.56#ibcon#wrote, iclass 26, count 0 2006.246.08:00:10.56#ibcon#about to read 3, iclass 26, count 0 2006.246.08:00:10.58#ibcon#read 3, iclass 26, count 0 2006.246.08:00:10.58#ibcon#about to read 4, iclass 26, count 0 2006.246.08:00:10.58#ibcon#read 4, iclass 26, count 0 2006.246.08:00:10.58#ibcon#about to read 5, iclass 26, count 0 2006.246.08:00:10.58#ibcon#read 5, iclass 26, count 0 2006.246.08:00:10.58#ibcon#about to read 6, iclass 26, count 0 2006.246.08:00:10.58#ibcon#read 6, iclass 26, count 0 2006.246.08:00:10.58#ibcon#end of sib2, iclass 26, count 0 2006.246.08:00:10.58#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:00:10.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:00:10.58#ibcon#[25=USB\r\n] 2006.246.08:00:10.58#ibcon#*before write, iclass 26, count 0 2006.246.08:00:10.58#ibcon#enter sib2, iclass 26, count 0 2006.246.08:00:10.58#ibcon#flushed, iclass 26, count 0 2006.246.08:00:10.58#ibcon#about to write, iclass 26, count 0 2006.246.08:00:10.58#ibcon#wrote, iclass 26, count 0 2006.246.08:00:10.58#ibcon#about to read 3, iclass 26, count 0 2006.246.08:00:10.61#ibcon#read 3, iclass 26, count 0 2006.246.08:00:10.61#ibcon#about to read 4, iclass 26, count 0 2006.246.08:00:10.61#ibcon#read 4, iclass 26, count 0 2006.246.08:00:10.61#ibcon#about to read 5, iclass 26, count 0 2006.246.08:00:10.61#ibcon#read 5, iclass 26, count 0 2006.246.08:00:10.61#ibcon#about to read 6, iclass 26, count 0 2006.246.08:00:10.61#ibcon#read 6, iclass 26, count 0 2006.246.08:00:10.61#ibcon#end of sib2, iclass 26, count 0 2006.246.08:00:10.61#ibcon#*after write, iclass 26, count 0 2006.246.08:00:10.61#ibcon#*before return 0, iclass 26, count 0 2006.246.08:00:10.61#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:00:10.61#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:00:10.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:00:10.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:00:10.61$vc4f8/vblo=1,632.99 2006.246.08:00:10.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.08:00:10.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.08:00:10.61#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:10.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:00:10.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:00:10.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:00:10.61#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:00:10.61#ibcon#first serial, iclass 28, count 0 2006.246.08:00:10.61#ibcon#enter sib2, iclass 28, count 0 2006.246.08:00:10.61#ibcon#flushed, iclass 28, count 0 2006.246.08:00:10.61#ibcon#about to write, iclass 28, count 0 2006.246.08:00:10.61#ibcon#wrote, iclass 28, count 0 2006.246.08:00:10.61#ibcon#about to read 3, iclass 28, count 0 2006.246.08:00:10.63#ibcon#read 3, iclass 28, count 0 2006.246.08:00:10.63#ibcon#about to read 4, iclass 28, count 0 2006.246.08:00:10.63#ibcon#read 4, iclass 28, count 0 2006.246.08:00:10.63#ibcon#about to read 5, iclass 28, count 0 2006.246.08:00:10.63#ibcon#read 5, iclass 28, count 0 2006.246.08:00:10.63#ibcon#about to read 6, iclass 28, count 0 2006.246.08:00:10.63#ibcon#read 6, iclass 28, count 0 2006.246.08:00:10.63#ibcon#end of sib2, iclass 28, count 0 2006.246.08:00:10.63#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:00:10.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:00:10.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:00:10.63#ibcon#*before write, iclass 28, count 0 2006.246.08:00:10.63#ibcon#enter sib2, iclass 28, count 0 2006.246.08:00:10.63#ibcon#flushed, iclass 28, count 0 2006.246.08:00:10.63#ibcon#about to write, iclass 28, count 0 2006.246.08:00:10.63#ibcon#wrote, iclass 28, count 0 2006.246.08:00:10.63#ibcon#about to read 3, iclass 28, count 0 2006.246.08:00:10.67#ibcon#read 3, iclass 28, count 0 2006.246.08:00:10.67#ibcon#about to read 4, iclass 28, count 0 2006.246.08:00:10.67#ibcon#read 4, iclass 28, count 0 2006.246.08:00:10.67#ibcon#about to read 5, iclass 28, count 0 2006.246.08:00:10.67#ibcon#read 5, iclass 28, count 0 2006.246.08:00:10.67#ibcon#about to read 6, iclass 28, count 0 2006.246.08:00:10.67#ibcon#read 6, iclass 28, count 0 2006.246.08:00:10.67#ibcon#end of sib2, iclass 28, count 0 2006.246.08:00:10.67#ibcon#*after write, iclass 28, count 0 2006.246.08:00:10.67#ibcon#*before return 0, iclass 28, count 0 2006.246.08:00:10.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:00:10.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:00:10.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:00:10.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:00:10.67$vc4f8/vb=1,4 2006.246.08:00:10.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.08:00:10.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.08:00:10.67#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:10.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:00:10.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:00:10.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:00:10.67#ibcon#enter wrdev, iclass 30, count 2 2006.246.08:00:10.67#ibcon#first serial, iclass 30, count 2 2006.246.08:00:10.67#ibcon#enter sib2, iclass 30, count 2 2006.246.08:00:10.67#ibcon#flushed, iclass 30, count 2 2006.246.08:00:10.67#ibcon#about to write, iclass 30, count 2 2006.246.08:00:10.67#ibcon#wrote, iclass 30, count 2 2006.246.08:00:10.67#ibcon#about to read 3, iclass 30, count 2 2006.246.08:00:10.69#ibcon#read 3, iclass 30, count 2 2006.246.08:00:10.69#ibcon#about to read 4, iclass 30, count 2 2006.246.08:00:10.69#ibcon#read 4, iclass 30, count 2 2006.246.08:00:10.69#ibcon#about to read 5, iclass 30, count 2 2006.246.08:00:10.69#ibcon#read 5, iclass 30, count 2 2006.246.08:00:10.69#ibcon#about to read 6, iclass 30, count 2 2006.246.08:00:10.69#ibcon#read 6, iclass 30, count 2 2006.246.08:00:10.69#ibcon#end of sib2, iclass 30, count 2 2006.246.08:00:10.69#ibcon#*mode == 0, iclass 30, count 2 2006.246.08:00:10.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.08:00:10.69#ibcon#[27=AT01-04\r\n] 2006.246.08:00:10.69#ibcon#*before write, iclass 30, count 2 2006.246.08:00:10.69#ibcon#enter sib2, iclass 30, count 2 2006.246.08:00:10.69#ibcon#flushed, iclass 30, count 2 2006.246.08:00:10.69#ibcon#about to write, iclass 30, count 2 2006.246.08:00:10.69#ibcon#wrote, iclass 30, count 2 2006.246.08:00:10.69#ibcon#about to read 3, iclass 30, count 2 2006.246.08:00:10.72#ibcon#read 3, iclass 30, count 2 2006.246.08:00:10.72#ibcon#about to read 4, iclass 30, count 2 2006.246.08:00:10.72#ibcon#read 4, iclass 30, count 2 2006.246.08:00:10.72#ibcon#about to read 5, iclass 30, count 2 2006.246.08:00:10.72#ibcon#read 5, iclass 30, count 2 2006.246.08:00:10.72#ibcon#about to read 6, iclass 30, count 2 2006.246.08:00:10.72#ibcon#read 6, iclass 30, count 2 2006.246.08:00:10.72#ibcon#end of sib2, iclass 30, count 2 2006.246.08:00:10.72#ibcon#*after write, iclass 30, count 2 2006.246.08:00:10.72#ibcon#*before return 0, iclass 30, count 2 2006.246.08:00:10.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:00:10.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:00:10.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.08:00:10.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:10.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:00:10.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:00:10.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:00:10.84#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:00:10.84#ibcon#first serial, iclass 30, count 0 2006.246.08:00:10.84#ibcon#enter sib2, iclass 30, count 0 2006.246.08:00:10.84#ibcon#flushed, iclass 30, count 0 2006.246.08:00:10.84#ibcon#about to write, iclass 30, count 0 2006.246.08:00:10.84#ibcon#wrote, iclass 30, count 0 2006.246.08:00:10.84#ibcon#about to read 3, iclass 30, count 0 2006.246.08:00:10.86#ibcon#read 3, iclass 30, count 0 2006.246.08:00:10.86#ibcon#about to read 4, iclass 30, count 0 2006.246.08:00:10.86#ibcon#read 4, iclass 30, count 0 2006.246.08:00:10.86#ibcon#about to read 5, iclass 30, count 0 2006.246.08:00:10.86#ibcon#read 5, iclass 30, count 0 2006.246.08:00:10.86#ibcon#about to read 6, iclass 30, count 0 2006.246.08:00:10.86#ibcon#read 6, iclass 30, count 0 2006.246.08:00:10.86#ibcon#end of sib2, iclass 30, count 0 2006.246.08:00:10.86#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:00:10.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:00:10.86#ibcon#[27=USB\r\n] 2006.246.08:00:10.86#ibcon#*before write, iclass 30, count 0 2006.246.08:00:10.86#ibcon#enter sib2, iclass 30, count 0 2006.246.08:00:10.86#ibcon#flushed, iclass 30, count 0 2006.246.08:00:10.86#ibcon#about to write, iclass 30, count 0 2006.246.08:00:10.86#ibcon#wrote, iclass 30, count 0 2006.246.08:00:10.86#ibcon#about to read 3, iclass 30, count 0 2006.246.08:00:10.89#ibcon#read 3, iclass 30, count 0 2006.246.08:00:10.89#ibcon#about to read 4, iclass 30, count 0 2006.246.08:00:10.89#ibcon#read 4, iclass 30, count 0 2006.246.08:00:10.89#ibcon#about to read 5, iclass 30, count 0 2006.246.08:00:10.89#ibcon#read 5, iclass 30, count 0 2006.246.08:00:10.89#ibcon#about to read 6, iclass 30, count 0 2006.246.08:00:10.89#ibcon#read 6, iclass 30, count 0 2006.246.08:00:10.89#ibcon#end of sib2, iclass 30, count 0 2006.246.08:00:10.89#ibcon#*after write, iclass 30, count 0 2006.246.08:00:10.89#ibcon#*before return 0, iclass 30, count 0 2006.246.08:00:10.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:00:10.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:00:10.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:00:10.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:00:10.89$vc4f8/vblo=2,640.99 2006.246.08:00:10.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:00:10.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:00:10.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:10.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:10.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:10.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:10.89#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:00:10.89#ibcon#first serial, iclass 32, count 0 2006.246.08:00:10.89#ibcon#enter sib2, iclass 32, count 0 2006.246.08:00:10.89#ibcon#flushed, iclass 32, count 0 2006.246.08:00:10.89#ibcon#about to write, iclass 32, count 0 2006.246.08:00:10.89#ibcon#wrote, iclass 32, count 0 2006.246.08:00:10.89#ibcon#about to read 3, iclass 32, count 0 2006.246.08:00:10.91#ibcon#read 3, iclass 32, count 0 2006.246.08:00:10.91#ibcon#about to read 4, iclass 32, count 0 2006.246.08:00:10.91#ibcon#read 4, iclass 32, count 0 2006.246.08:00:10.91#ibcon#about to read 5, iclass 32, count 0 2006.246.08:00:10.91#ibcon#read 5, iclass 32, count 0 2006.246.08:00:10.91#ibcon#about to read 6, iclass 32, count 0 2006.246.08:00:10.91#ibcon#read 6, iclass 32, count 0 2006.246.08:00:10.91#ibcon#end of sib2, iclass 32, count 0 2006.246.08:00:10.91#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:00:10.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:00:10.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:00:10.91#ibcon#*before write, iclass 32, count 0 2006.246.08:00:10.91#ibcon#enter sib2, iclass 32, count 0 2006.246.08:00:10.91#ibcon#flushed, iclass 32, count 0 2006.246.08:00:10.91#ibcon#about to write, iclass 32, count 0 2006.246.08:00:10.91#ibcon#wrote, iclass 32, count 0 2006.246.08:00:10.91#ibcon#about to read 3, iclass 32, count 0 2006.246.08:00:10.95#ibcon#read 3, iclass 32, count 0 2006.246.08:00:10.95#ibcon#about to read 4, iclass 32, count 0 2006.246.08:00:10.95#ibcon#read 4, iclass 32, count 0 2006.246.08:00:10.95#ibcon#about to read 5, iclass 32, count 0 2006.246.08:00:10.95#ibcon#read 5, iclass 32, count 0 2006.246.08:00:10.95#ibcon#about to read 6, iclass 32, count 0 2006.246.08:00:10.95#ibcon#read 6, iclass 32, count 0 2006.246.08:00:10.95#ibcon#end of sib2, iclass 32, count 0 2006.246.08:00:10.95#ibcon#*after write, iclass 32, count 0 2006.246.08:00:10.95#ibcon#*before return 0, iclass 32, count 0 2006.246.08:00:10.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:10.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:00:10.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:00:10.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:00:10.95$vc4f8/vb=2,4 2006.246.08:00:10.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.08:00:10.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.08:00:10.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:10.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:11.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:11.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:11.01#ibcon#enter wrdev, iclass 34, count 2 2006.246.08:00:11.01#ibcon#first serial, iclass 34, count 2 2006.246.08:00:11.01#ibcon#enter sib2, iclass 34, count 2 2006.246.08:00:11.01#ibcon#flushed, iclass 34, count 2 2006.246.08:00:11.01#ibcon#about to write, iclass 34, count 2 2006.246.08:00:11.01#ibcon#wrote, iclass 34, count 2 2006.246.08:00:11.01#ibcon#about to read 3, iclass 34, count 2 2006.246.08:00:11.03#ibcon#read 3, iclass 34, count 2 2006.246.08:00:11.03#ibcon#about to read 4, iclass 34, count 2 2006.246.08:00:11.03#ibcon#read 4, iclass 34, count 2 2006.246.08:00:11.03#ibcon#about to read 5, iclass 34, count 2 2006.246.08:00:11.03#ibcon#read 5, iclass 34, count 2 2006.246.08:00:11.03#ibcon#about to read 6, iclass 34, count 2 2006.246.08:00:11.03#ibcon#read 6, iclass 34, count 2 2006.246.08:00:11.03#ibcon#end of sib2, iclass 34, count 2 2006.246.08:00:11.03#ibcon#*mode == 0, iclass 34, count 2 2006.246.08:00:11.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.08:00:11.03#ibcon#[27=AT02-04\r\n] 2006.246.08:00:11.03#ibcon#*before write, iclass 34, count 2 2006.246.08:00:11.03#ibcon#enter sib2, iclass 34, count 2 2006.246.08:00:11.03#ibcon#flushed, iclass 34, count 2 2006.246.08:00:11.03#ibcon#about to write, iclass 34, count 2 2006.246.08:00:11.03#ibcon#wrote, iclass 34, count 2 2006.246.08:00:11.03#ibcon#about to read 3, iclass 34, count 2 2006.246.08:00:11.06#ibcon#read 3, iclass 34, count 2 2006.246.08:00:11.06#ibcon#about to read 4, iclass 34, count 2 2006.246.08:00:11.06#ibcon#read 4, iclass 34, count 2 2006.246.08:00:11.06#ibcon#about to read 5, iclass 34, count 2 2006.246.08:00:11.06#ibcon#read 5, iclass 34, count 2 2006.246.08:00:11.06#ibcon#about to read 6, iclass 34, count 2 2006.246.08:00:11.06#ibcon#read 6, iclass 34, count 2 2006.246.08:00:11.06#ibcon#end of sib2, iclass 34, count 2 2006.246.08:00:11.06#ibcon#*after write, iclass 34, count 2 2006.246.08:00:11.06#ibcon#*before return 0, iclass 34, count 2 2006.246.08:00:11.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:11.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:00:11.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.08:00:11.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:11.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:11.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:11.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:11.18#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:00:11.18#ibcon#first serial, iclass 34, count 0 2006.246.08:00:11.18#ibcon#enter sib2, iclass 34, count 0 2006.246.08:00:11.18#ibcon#flushed, iclass 34, count 0 2006.246.08:00:11.18#ibcon#about to write, iclass 34, count 0 2006.246.08:00:11.18#ibcon#wrote, iclass 34, count 0 2006.246.08:00:11.18#ibcon#about to read 3, iclass 34, count 0 2006.246.08:00:11.20#ibcon#read 3, iclass 34, count 0 2006.246.08:00:11.20#ibcon#about to read 4, iclass 34, count 0 2006.246.08:00:11.20#ibcon#read 4, iclass 34, count 0 2006.246.08:00:11.20#ibcon#about to read 5, iclass 34, count 0 2006.246.08:00:11.20#ibcon#read 5, iclass 34, count 0 2006.246.08:00:11.20#ibcon#about to read 6, iclass 34, count 0 2006.246.08:00:11.20#ibcon#read 6, iclass 34, count 0 2006.246.08:00:11.20#ibcon#end of sib2, iclass 34, count 0 2006.246.08:00:11.20#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:00:11.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:00:11.20#ibcon#[27=USB\r\n] 2006.246.08:00:11.20#ibcon#*before write, iclass 34, count 0 2006.246.08:00:11.20#ibcon#enter sib2, iclass 34, count 0 2006.246.08:00:11.20#ibcon#flushed, iclass 34, count 0 2006.246.08:00:11.20#ibcon#about to write, iclass 34, count 0 2006.246.08:00:11.20#ibcon#wrote, iclass 34, count 0 2006.246.08:00:11.20#ibcon#about to read 3, iclass 34, count 0 2006.246.08:00:11.23#ibcon#read 3, iclass 34, count 0 2006.246.08:00:11.23#ibcon#about to read 4, iclass 34, count 0 2006.246.08:00:11.23#ibcon#read 4, iclass 34, count 0 2006.246.08:00:11.23#ibcon#about to read 5, iclass 34, count 0 2006.246.08:00:11.23#ibcon#read 5, iclass 34, count 0 2006.246.08:00:11.23#ibcon#about to read 6, iclass 34, count 0 2006.246.08:00:11.23#ibcon#read 6, iclass 34, count 0 2006.246.08:00:11.23#ibcon#end of sib2, iclass 34, count 0 2006.246.08:00:11.23#ibcon#*after write, iclass 34, count 0 2006.246.08:00:11.23#ibcon#*before return 0, iclass 34, count 0 2006.246.08:00:11.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:11.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:00:11.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:00:11.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:00:11.23$vc4f8/vblo=3,656.99 2006.246.08:00:11.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.08:00:11.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.08:00:11.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:11.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:11.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:11.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:11.23#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:00:11.23#ibcon#first serial, iclass 36, count 0 2006.246.08:00:11.23#ibcon#enter sib2, iclass 36, count 0 2006.246.08:00:11.23#ibcon#flushed, iclass 36, count 0 2006.246.08:00:11.23#ibcon#about to write, iclass 36, count 0 2006.246.08:00:11.23#ibcon#wrote, iclass 36, count 0 2006.246.08:00:11.23#ibcon#about to read 3, iclass 36, count 0 2006.246.08:00:11.25#ibcon#read 3, iclass 36, count 0 2006.246.08:00:11.25#ibcon#about to read 4, iclass 36, count 0 2006.246.08:00:11.25#ibcon#read 4, iclass 36, count 0 2006.246.08:00:11.25#ibcon#about to read 5, iclass 36, count 0 2006.246.08:00:11.25#ibcon#read 5, iclass 36, count 0 2006.246.08:00:11.25#ibcon#about to read 6, iclass 36, count 0 2006.246.08:00:11.25#ibcon#read 6, iclass 36, count 0 2006.246.08:00:11.25#ibcon#end of sib2, iclass 36, count 0 2006.246.08:00:11.25#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:00:11.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:00:11.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:00:11.25#ibcon#*before write, iclass 36, count 0 2006.246.08:00:11.25#ibcon#enter sib2, iclass 36, count 0 2006.246.08:00:11.25#ibcon#flushed, iclass 36, count 0 2006.246.08:00:11.25#ibcon#about to write, iclass 36, count 0 2006.246.08:00:11.25#ibcon#wrote, iclass 36, count 0 2006.246.08:00:11.25#ibcon#about to read 3, iclass 36, count 0 2006.246.08:00:11.29#ibcon#read 3, iclass 36, count 0 2006.246.08:00:11.29#ibcon#about to read 4, iclass 36, count 0 2006.246.08:00:11.29#ibcon#read 4, iclass 36, count 0 2006.246.08:00:11.29#ibcon#about to read 5, iclass 36, count 0 2006.246.08:00:11.29#ibcon#read 5, iclass 36, count 0 2006.246.08:00:11.29#ibcon#about to read 6, iclass 36, count 0 2006.246.08:00:11.29#ibcon#read 6, iclass 36, count 0 2006.246.08:00:11.29#ibcon#end of sib2, iclass 36, count 0 2006.246.08:00:11.29#ibcon#*after write, iclass 36, count 0 2006.246.08:00:11.29#ibcon#*before return 0, iclass 36, count 0 2006.246.08:00:11.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:11.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:00:11.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:00:11.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:00:11.29$vc4f8/vb=3,4 2006.246.08:00:11.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.08:00:11.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.08:00:11.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:11.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:11.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:11.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:11.35#ibcon#enter wrdev, iclass 38, count 2 2006.246.08:00:11.35#ibcon#first serial, iclass 38, count 2 2006.246.08:00:11.35#ibcon#enter sib2, iclass 38, count 2 2006.246.08:00:11.35#ibcon#flushed, iclass 38, count 2 2006.246.08:00:11.35#ibcon#about to write, iclass 38, count 2 2006.246.08:00:11.35#ibcon#wrote, iclass 38, count 2 2006.246.08:00:11.35#ibcon#about to read 3, iclass 38, count 2 2006.246.08:00:11.37#ibcon#read 3, iclass 38, count 2 2006.246.08:00:11.37#ibcon#about to read 4, iclass 38, count 2 2006.246.08:00:11.37#ibcon#read 4, iclass 38, count 2 2006.246.08:00:11.37#ibcon#about to read 5, iclass 38, count 2 2006.246.08:00:11.37#ibcon#read 5, iclass 38, count 2 2006.246.08:00:11.37#ibcon#about to read 6, iclass 38, count 2 2006.246.08:00:11.37#ibcon#read 6, iclass 38, count 2 2006.246.08:00:11.37#ibcon#end of sib2, iclass 38, count 2 2006.246.08:00:11.37#ibcon#*mode == 0, iclass 38, count 2 2006.246.08:00:11.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.08:00:11.37#ibcon#[27=AT03-04\r\n] 2006.246.08:00:11.37#ibcon#*before write, iclass 38, count 2 2006.246.08:00:11.37#ibcon#enter sib2, iclass 38, count 2 2006.246.08:00:11.37#ibcon#flushed, iclass 38, count 2 2006.246.08:00:11.37#ibcon#about to write, iclass 38, count 2 2006.246.08:00:11.37#ibcon#wrote, iclass 38, count 2 2006.246.08:00:11.37#ibcon#about to read 3, iclass 38, count 2 2006.246.08:00:11.40#ibcon#read 3, iclass 38, count 2 2006.246.08:00:11.40#ibcon#about to read 4, iclass 38, count 2 2006.246.08:00:11.40#ibcon#read 4, iclass 38, count 2 2006.246.08:00:11.40#ibcon#about to read 5, iclass 38, count 2 2006.246.08:00:11.40#ibcon#read 5, iclass 38, count 2 2006.246.08:00:11.40#ibcon#about to read 6, iclass 38, count 2 2006.246.08:00:11.40#ibcon#read 6, iclass 38, count 2 2006.246.08:00:11.40#ibcon#end of sib2, iclass 38, count 2 2006.246.08:00:11.40#ibcon#*after write, iclass 38, count 2 2006.246.08:00:11.40#ibcon#*before return 0, iclass 38, count 2 2006.246.08:00:11.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:11.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:00:11.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.08:00:11.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:11.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:11.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:11.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:11.52#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:00:11.52#ibcon#first serial, iclass 38, count 0 2006.246.08:00:11.52#ibcon#enter sib2, iclass 38, count 0 2006.246.08:00:11.52#ibcon#flushed, iclass 38, count 0 2006.246.08:00:11.52#ibcon#about to write, iclass 38, count 0 2006.246.08:00:11.52#ibcon#wrote, iclass 38, count 0 2006.246.08:00:11.52#ibcon#about to read 3, iclass 38, count 0 2006.246.08:00:11.54#ibcon#read 3, iclass 38, count 0 2006.246.08:00:11.54#ibcon#about to read 4, iclass 38, count 0 2006.246.08:00:11.54#ibcon#read 4, iclass 38, count 0 2006.246.08:00:11.54#ibcon#about to read 5, iclass 38, count 0 2006.246.08:00:11.54#ibcon#read 5, iclass 38, count 0 2006.246.08:00:11.54#ibcon#about to read 6, iclass 38, count 0 2006.246.08:00:11.54#ibcon#read 6, iclass 38, count 0 2006.246.08:00:11.54#ibcon#end of sib2, iclass 38, count 0 2006.246.08:00:11.54#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:00:11.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:00:11.54#ibcon#[27=USB\r\n] 2006.246.08:00:11.54#ibcon#*before write, iclass 38, count 0 2006.246.08:00:11.54#ibcon#enter sib2, iclass 38, count 0 2006.246.08:00:11.54#ibcon#flushed, iclass 38, count 0 2006.246.08:00:11.54#ibcon#about to write, iclass 38, count 0 2006.246.08:00:11.54#ibcon#wrote, iclass 38, count 0 2006.246.08:00:11.54#ibcon#about to read 3, iclass 38, count 0 2006.246.08:00:11.57#ibcon#read 3, iclass 38, count 0 2006.246.08:00:11.57#ibcon#about to read 4, iclass 38, count 0 2006.246.08:00:11.57#ibcon#read 4, iclass 38, count 0 2006.246.08:00:11.57#ibcon#about to read 5, iclass 38, count 0 2006.246.08:00:11.57#ibcon#read 5, iclass 38, count 0 2006.246.08:00:11.57#ibcon#about to read 6, iclass 38, count 0 2006.246.08:00:11.57#ibcon#read 6, iclass 38, count 0 2006.246.08:00:11.57#ibcon#end of sib2, iclass 38, count 0 2006.246.08:00:11.57#ibcon#*after write, iclass 38, count 0 2006.246.08:00:11.57#ibcon#*before return 0, iclass 38, count 0 2006.246.08:00:11.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:11.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:00:11.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:00:11.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:00:11.57$vc4f8/vblo=4,712.99 2006.246.08:00:11.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.08:00:11.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.08:00:11.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:11.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:11.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:11.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:11.57#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:00:11.57#ibcon#first serial, iclass 40, count 0 2006.246.08:00:11.57#ibcon#enter sib2, iclass 40, count 0 2006.246.08:00:11.57#ibcon#flushed, iclass 40, count 0 2006.246.08:00:11.57#ibcon#about to write, iclass 40, count 0 2006.246.08:00:11.57#ibcon#wrote, iclass 40, count 0 2006.246.08:00:11.57#ibcon#about to read 3, iclass 40, count 0 2006.246.08:00:11.59#ibcon#read 3, iclass 40, count 0 2006.246.08:00:11.59#ibcon#about to read 4, iclass 40, count 0 2006.246.08:00:11.59#ibcon#read 4, iclass 40, count 0 2006.246.08:00:11.59#ibcon#about to read 5, iclass 40, count 0 2006.246.08:00:11.59#ibcon#read 5, iclass 40, count 0 2006.246.08:00:11.59#ibcon#about to read 6, iclass 40, count 0 2006.246.08:00:11.59#ibcon#read 6, iclass 40, count 0 2006.246.08:00:11.59#ibcon#end of sib2, iclass 40, count 0 2006.246.08:00:11.59#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:00:11.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:00:11.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:00:11.59#ibcon#*before write, iclass 40, count 0 2006.246.08:00:11.59#ibcon#enter sib2, iclass 40, count 0 2006.246.08:00:11.59#ibcon#flushed, iclass 40, count 0 2006.246.08:00:11.59#ibcon#about to write, iclass 40, count 0 2006.246.08:00:11.59#ibcon#wrote, iclass 40, count 0 2006.246.08:00:11.59#ibcon#about to read 3, iclass 40, count 0 2006.246.08:00:11.63#ibcon#read 3, iclass 40, count 0 2006.246.08:00:11.63#ibcon#about to read 4, iclass 40, count 0 2006.246.08:00:11.63#ibcon#read 4, iclass 40, count 0 2006.246.08:00:11.63#ibcon#about to read 5, iclass 40, count 0 2006.246.08:00:11.63#ibcon#read 5, iclass 40, count 0 2006.246.08:00:11.63#ibcon#about to read 6, iclass 40, count 0 2006.246.08:00:11.63#ibcon#read 6, iclass 40, count 0 2006.246.08:00:11.63#ibcon#end of sib2, iclass 40, count 0 2006.246.08:00:11.63#ibcon#*after write, iclass 40, count 0 2006.246.08:00:11.63#ibcon#*before return 0, iclass 40, count 0 2006.246.08:00:11.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:11.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:00:11.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:00:11.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:00:11.63$vc4f8/vb=4,4 2006.246.08:00:11.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.08:00:11.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.08:00:11.63#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:11.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:11.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:11.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:11.69#ibcon#enter wrdev, iclass 4, count 2 2006.246.08:00:11.69#ibcon#first serial, iclass 4, count 2 2006.246.08:00:11.69#ibcon#enter sib2, iclass 4, count 2 2006.246.08:00:11.69#ibcon#flushed, iclass 4, count 2 2006.246.08:00:11.69#ibcon#about to write, iclass 4, count 2 2006.246.08:00:11.69#ibcon#wrote, iclass 4, count 2 2006.246.08:00:11.69#ibcon#about to read 3, iclass 4, count 2 2006.246.08:00:11.71#ibcon#read 3, iclass 4, count 2 2006.246.08:00:11.71#ibcon#about to read 4, iclass 4, count 2 2006.246.08:00:11.71#ibcon#read 4, iclass 4, count 2 2006.246.08:00:11.71#ibcon#about to read 5, iclass 4, count 2 2006.246.08:00:11.71#ibcon#read 5, iclass 4, count 2 2006.246.08:00:11.71#ibcon#about to read 6, iclass 4, count 2 2006.246.08:00:11.71#ibcon#read 6, iclass 4, count 2 2006.246.08:00:11.71#ibcon#end of sib2, iclass 4, count 2 2006.246.08:00:11.71#ibcon#*mode == 0, iclass 4, count 2 2006.246.08:00:11.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.08:00:11.71#ibcon#[27=AT04-04\r\n] 2006.246.08:00:11.71#ibcon#*before write, iclass 4, count 2 2006.246.08:00:11.71#ibcon#enter sib2, iclass 4, count 2 2006.246.08:00:11.71#ibcon#flushed, iclass 4, count 2 2006.246.08:00:11.71#ibcon#about to write, iclass 4, count 2 2006.246.08:00:11.71#ibcon#wrote, iclass 4, count 2 2006.246.08:00:11.71#ibcon#about to read 3, iclass 4, count 2 2006.246.08:00:11.74#ibcon#read 3, iclass 4, count 2 2006.246.08:00:11.74#ibcon#about to read 4, iclass 4, count 2 2006.246.08:00:11.74#ibcon#read 4, iclass 4, count 2 2006.246.08:00:11.74#ibcon#about to read 5, iclass 4, count 2 2006.246.08:00:11.74#ibcon#read 5, iclass 4, count 2 2006.246.08:00:11.74#ibcon#about to read 6, iclass 4, count 2 2006.246.08:00:11.74#ibcon#read 6, iclass 4, count 2 2006.246.08:00:11.74#ibcon#end of sib2, iclass 4, count 2 2006.246.08:00:11.74#ibcon#*after write, iclass 4, count 2 2006.246.08:00:11.74#ibcon#*before return 0, iclass 4, count 2 2006.246.08:00:11.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:11.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:00:11.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.08:00:11.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:11.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:11.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:11.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:11.86#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:00:11.86#ibcon#first serial, iclass 4, count 0 2006.246.08:00:11.86#ibcon#enter sib2, iclass 4, count 0 2006.246.08:00:11.86#ibcon#flushed, iclass 4, count 0 2006.246.08:00:11.86#ibcon#about to write, iclass 4, count 0 2006.246.08:00:11.86#ibcon#wrote, iclass 4, count 0 2006.246.08:00:11.86#ibcon#about to read 3, iclass 4, count 0 2006.246.08:00:11.88#ibcon#read 3, iclass 4, count 0 2006.246.08:00:11.88#ibcon#about to read 4, iclass 4, count 0 2006.246.08:00:11.88#ibcon#read 4, iclass 4, count 0 2006.246.08:00:11.88#ibcon#about to read 5, iclass 4, count 0 2006.246.08:00:11.88#ibcon#read 5, iclass 4, count 0 2006.246.08:00:11.88#ibcon#about to read 6, iclass 4, count 0 2006.246.08:00:11.88#ibcon#read 6, iclass 4, count 0 2006.246.08:00:11.88#ibcon#end of sib2, iclass 4, count 0 2006.246.08:00:11.88#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:00:11.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:00:11.88#ibcon#[27=USB\r\n] 2006.246.08:00:11.88#ibcon#*before write, iclass 4, count 0 2006.246.08:00:11.88#ibcon#enter sib2, iclass 4, count 0 2006.246.08:00:11.88#ibcon#flushed, iclass 4, count 0 2006.246.08:00:11.88#ibcon#about to write, iclass 4, count 0 2006.246.08:00:11.88#ibcon#wrote, iclass 4, count 0 2006.246.08:00:11.88#ibcon#about to read 3, iclass 4, count 0 2006.246.08:00:11.91#ibcon#read 3, iclass 4, count 0 2006.246.08:00:11.91#ibcon#about to read 4, iclass 4, count 0 2006.246.08:00:11.91#ibcon#read 4, iclass 4, count 0 2006.246.08:00:11.91#ibcon#about to read 5, iclass 4, count 0 2006.246.08:00:11.91#ibcon#read 5, iclass 4, count 0 2006.246.08:00:11.91#ibcon#about to read 6, iclass 4, count 0 2006.246.08:00:11.91#ibcon#read 6, iclass 4, count 0 2006.246.08:00:11.91#ibcon#end of sib2, iclass 4, count 0 2006.246.08:00:11.91#ibcon#*after write, iclass 4, count 0 2006.246.08:00:11.91#ibcon#*before return 0, iclass 4, count 0 2006.246.08:00:11.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:11.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:00:11.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:00:11.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:00:11.91$vc4f8/vblo=5,744.99 2006.246.08:00:11.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.08:00:11.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.08:00:11.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:11.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:11.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:11.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:11.91#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:00:11.91#ibcon#first serial, iclass 6, count 0 2006.246.08:00:11.91#ibcon#enter sib2, iclass 6, count 0 2006.246.08:00:11.91#ibcon#flushed, iclass 6, count 0 2006.246.08:00:11.91#ibcon#about to write, iclass 6, count 0 2006.246.08:00:11.91#ibcon#wrote, iclass 6, count 0 2006.246.08:00:11.91#ibcon#about to read 3, iclass 6, count 0 2006.246.08:00:11.93#ibcon#read 3, iclass 6, count 0 2006.246.08:00:11.93#ibcon#about to read 4, iclass 6, count 0 2006.246.08:00:11.93#ibcon#read 4, iclass 6, count 0 2006.246.08:00:11.93#ibcon#about to read 5, iclass 6, count 0 2006.246.08:00:11.93#ibcon#read 5, iclass 6, count 0 2006.246.08:00:11.93#ibcon#about to read 6, iclass 6, count 0 2006.246.08:00:11.93#ibcon#read 6, iclass 6, count 0 2006.246.08:00:11.93#ibcon#end of sib2, iclass 6, count 0 2006.246.08:00:11.93#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:00:11.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:00:11.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:00:11.93#ibcon#*before write, iclass 6, count 0 2006.246.08:00:11.93#ibcon#enter sib2, iclass 6, count 0 2006.246.08:00:11.93#ibcon#flushed, iclass 6, count 0 2006.246.08:00:11.93#ibcon#about to write, iclass 6, count 0 2006.246.08:00:11.93#ibcon#wrote, iclass 6, count 0 2006.246.08:00:11.93#ibcon#about to read 3, iclass 6, count 0 2006.246.08:00:11.97#ibcon#read 3, iclass 6, count 0 2006.246.08:00:11.97#ibcon#about to read 4, iclass 6, count 0 2006.246.08:00:11.97#ibcon#read 4, iclass 6, count 0 2006.246.08:00:11.97#ibcon#about to read 5, iclass 6, count 0 2006.246.08:00:11.97#ibcon#read 5, iclass 6, count 0 2006.246.08:00:11.97#ibcon#about to read 6, iclass 6, count 0 2006.246.08:00:11.97#ibcon#read 6, iclass 6, count 0 2006.246.08:00:11.97#ibcon#end of sib2, iclass 6, count 0 2006.246.08:00:11.97#ibcon#*after write, iclass 6, count 0 2006.246.08:00:11.97#ibcon#*before return 0, iclass 6, count 0 2006.246.08:00:11.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:11.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:00:11.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:00:11.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:00:11.97$vc4f8/vb=5,3 2006.246.08:00:11.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.08:00:11.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.08:00:11.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:11.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:12.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:12.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:12.03#ibcon#enter wrdev, iclass 10, count 2 2006.246.08:00:12.03#ibcon#first serial, iclass 10, count 2 2006.246.08:00:12.03#ibcon#enter sib2, iclass 10, count 2 2006.246.08:00:12.03#ibcon#flushed, iclass 10, count 2 2006.246.08:00:12.03#ibcon#about to write, iclass 10, count 2 2006.246.08:00:12.03#ibcon#wrote, iclass 10, count 2 2006.246.08:00:12.03#ibcon#about to read 3, iclass 10, count 2 2006.246.08:00:12.05#ibcon#read 3, iclass 10, count 2 2006.246.08:00:12.05#ibcon#about to read 4, iclass 10, count 2 2006.246.08:00:12.05#ibcon#read 4, iclass 10, count 2 2006.246.08:00:12.05#ibcon#about to read 5, iclass 10, count 2 2006.246.08:00:12.05#ibcon#read 5, iclass 10, count 2 2006.246.08:00:12.05#ibcon#about to read 6, iclass 10, count 2 2006.246.08:00:12.05#ibcon#read 6, iclass 10, count 2 2006.246.08:00:12.05#ibcon#end of sib2, iclass 10, count 2 2006.246.08:00:12.05#ibcon#*mode == 0, iclass 10, count 2 2006.246.08:00:12.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.08:00:12.05#ibcon#[27=AT05-03\r\n] 2006.246.08:00:12.05#ibcon#*before write, iclass 10, count 2 2006.246.08:00:12.05#ibcon#enter sib2, iclass 10, count 2 2006.246.08:00:12.05#ibcon#flushed, iclass 10, count 2 2006.246.08:00:12.05#ibcon#about to write, iclass 10, count 2 2006.246.08:00:12.05#ibcon#wrote, iclass 10, count 2 2006.246.08:00:12.05#ibcon#about to read 3, iclass 10, count 2 2006.246.08:00:12.08#ibcon#read 3, iclass 10, count 2 2006.246.08:00:12.08#ibcon#about to read 4, iclass 10, count 2 2006.246.08:00:12.08#ibcon#read 4, iclass 10, count 2 2006.246.08:00:12.08#ibcon#about to read 5, iclass 10, count 2 2006.246.08:00:12.08#ibcon#read 5, iclass 10, count 2 2006.246.08:00:12.08#ibcon#about to read 6, iclass 10, count 2 2006.246.08:00:12.08#ibcon#read 6, iclass 10, count 2 2006.246.08:00:12.08#ibcon#end of sib2, iclass 10, count 2 2006.246.08:00:12.08#ibcon#*after write, iclass 10, count 2 2006.246.08:00:12.08#ibcon#*before return 0, iclass 10, count 2 2006.246.08:00:12.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:12.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:00:12.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.08:00:12.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:12.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:12.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:12.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:12.20#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:00:12.20#ibcon#first serial, iclass 10, count 0 2006.246.08:00:12.20#ibcon#enter sib2, iclass 10, count 0 2006.246.08:00:12.20#ibcon#flushed, iclass 10, count 0 2006.246.08:00:12.20#ibcon#about to write, iclass 10, count 0 2006.246.08:00:12.20#ibcon#wrote, iclass 10, count 0 2006.246.08:00:12.20#ibcon#about to read 3, iclass 10, count 0 2006.246.08:00:12.22#ibcon#read 3, iclass 10, count 0 2006.246.08:00:12.22#ibcon#about to read 4, iclass 10, count 0 2006.246.08:00:12.22#ibcon#read 4, iclass 10, count 0 2006.246.08:00:12.22#ibcon#about to read 5, iclass 10, count 0 2006.246.08:00:12.22#ibcon#read 5, iclass 10, count 0 2006.246.08:00:12.22#ibcon#about to read 6, iclass 10, count 0 2006.246.08:00:12.22#ibcon#read 6, iclass 10, count 0 2006.246.08:00:12.22#ibcon#end of sib2, iclass 10, count 0 2006.246.08:00:12.22#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:00:12.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:00:12.22#ibcon#[27=USB\r\n] 2006.246.08:00:12.22#ibcon#*before write, iclass 10, count 0 2006.246.08:00:12.22#ibcon#enter sib2, iclass 10, count 0 2006.246.08:00:12.22#ibcon#flushed, iclass 10, count 0 2006.246.08:00:12.22#ibcon#about to write, iclass 10, count 0 2006.246.08:00:12.22#ibcon#wrote, iclass 10, count 0 2006.246.08:00:12.22#ibcon#about to read 3, iclass 10, count 0 2006.246.08:00:12.25#ibcon#read 3, iclass 10, count 0 2006.246.08:00:12.25#ibcon#about to read 4, iclass 10, count 0 2006.246.08:00:12.25#ibcon#read 4, iclass 10, count 0 2006.246.08:00:12.25#ibcon#about to read 5, iclass 10, count 0 2006.246.08:00:12.25#ibcon#read 5, iclass 10, count 0 2006.246.08:00:12.25#ibcon#about to read 6, iclass 10, count 0 2006.246.08:00:12.25#ibcon#read 6, iclass 10, count 0 2006.246.08:00:12.25#ibcon#end of sib2, iclass 10, count 0 2006.246.08:00:12.25#ibcon#*after write, iclass 10, count 0 2006.246.08:00:12.25#ibcon#*before return 0, iclass 10, count 0 2006.246.08:00:12.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:12.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:00:12.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:00:12.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:00:12.25$vc4f8/vblo=6,752.99 2006.246.08:00:12.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.08:00:12.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.08:00:12.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:00:12.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:12.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:12.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:12.25#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:00:12.25#ibcon#first serial, iclass 12, count 0 2006.246.08:00:12.25#ibcon#enter sib2, iclass 12, count 0 2006.246.08:00:12.25#ibcon#flushed, iclass 12, count 0 2006.246.08:00:12.25#ibcon#about to write, iclass 12, count 0 2006.246.08:00:12.25#ibcon#wrote, iclass 12, count 0 2006.246.08:00:12.25#ibcon#about to read 3, iclass 12, count 0 2006.246.08:00:12.27#ibcon#read 3, iclass 12, count 0 2006.246.08:00:12.27#ibcon#about to read 4, iclass 12, count 0 2006.246.08:00:12.27#ibcon#read 4, iclass 12, count 0 2006.246.08:00:12.27#ibcon#about to read 5, iclass 12, count 0 2006.246.08:00:12.27#ibcon#read 5, iclass 12, count 0 2006.246.08:00:12.27#ibcon#about to read 6, iclass 12, count 0 2006.246.08:00:12.27#ibcon#read 6, iclass 12, count 0 2006.246.08:00:12.27#ibcon#end of sib2, iclass 12, count 0 2006.246.08:00:12.27#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:00:12.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:00:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:00:12.27#ibcon#*before write, iclass 12, count 0 2006.246.08:00:12.27#ibcon#enter sib2, iclass 12, count 0 2006.246.08:00:12.27#ibcon#flushed, iclass 12, count 0 2006.246.08:00:12.27#ibcon#about to write, iclass 12, count 0 2006.246.08:00:12.27#ibcon#wrote, iclass 12, count 0 2006.246.08:00:12.27#ibcon#about to read 3, iclass 12, count 0 2006.246.08:00:12.31#ibcon#read 3, iclass 12, count 0 2006.246.08:00:12.31#ibcon#about to read 4, iclass 12, count 0 2006.246.08:00:12.31#ibcon#read 4, iclass 12, count 0 2006.246.08:00:12.31#ibcon#about to read 5, iclass 12, count 0 2006.246.08:00:12.31#ibcon#read 5, iclass 12, count 0 2006.246.08:00:12.31#ibcon#about to read 6, iclass 12, count 0 2006.246.08:00:12.31#ibcon#read 6, iclass 12, count 0 2006.246.08:00:12.31#ibcon#end of sib2, iclass 12, count 0 2006.246.08:00:12.31#ibcon#*after write, iclass 12, count 0 2006.246.08:00:12.31#ibcon#*before return 0, iclass 12, count 0 2006.246.08:00:12.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:12.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:00:12.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:00:12.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:00:12.31$vc4f8/vb=6,3 2006.246.08:00:12.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.08:00:12.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.08:00:12.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:00:12.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:12.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:12.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:12.37#ibcon#enter wrdev, iclass 14, count 2 2006.246.08:00:12.37#ibcon#first serial, iclass 14, count 2 2006.246.08:00:12.37#ibcon#enter sib2, iclass 14, count 2 2006.246.08:00:12.37#ibcon#flushed, iclass 14, count 2 2006.246.08:00:12.37#ibcon#about to write, iclass 14, count 2 2006.246.08:00:12.37#ibcon#wrote, iclass 14, count 2 2006.246.08:00:12.37#ibcon#about to read 3, iclass 14, count 2 2006.246.08:00:12.39#ibcon#read 3, iclass 14, count 2 2006.246.08:00:12.39#ibcon#about to read 4, iclass 14, count 2 2006.246.08:00:12.39#ibcon#read 4, iclass 14, count 2 2006.246.08:00:12.39#ibcon#about to read 5, iclass 14, count 2 2006.246.08:00:12.39#ibcon#read 5, iclass 14, count 2 2006.246.08:00:12.39#ibcon#about to read 6, iclass 14, count 2 2006.246.08:00:12.39#ibcon#read 6, iclass 14, count 2 2006.246.08:00:12.39#ibcon#end of sib2, iclass 14, count 2 2006.246.08:00:12.39#ibcon#*mode == 0, iclass 14, count 2 2006.246.08:00:12.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.08:00:12.39#ibcon#[27=AT06-03\r\n] 2006.246.08:00:12.39#ibcon#*before write, iclass 14, count 2 2006.246.08:00:12.39#ibcon#enter sib2, iclass 14, count 2 2006.246.08:00:12.39#ibcon#flushed, iclass 14, count 2 2006.246.08:00:12.39#ibcon#about to write, iclass 14, count 2 2006.246.08:00:12.39#ibcon#wrote, iclass 14, count 2 2006.246.08:00:12.39#ibcon#about to read 3, iclass 14, count 2 2006.246.08:00:12.42#ibcon#read 3, iclass 14, count 2 2006.246.08:00:12.42#ibcon#about to read 4, iclass 14, count 2 2006.246.08:00:12.42#ibcon#read 4, iclass 14, count 2 2006.246.08:00:12.42#ibcon#about to read 5, iclass 14, count 2 2006.246.08:00:12.42#ibcon#read 5, iclass 14, count 2 2006.246.08:00:12.42#ibcon#about to read 6, iclass 14, count 2 2006.246.08:00:12.42#ibcon#read 6, iclass 14, count 2 2006.246.08:00:12.42#ibcon#end of sib2, iclass 14, count 2 2006.246.08:00:12.42#ibcon#*after write, iclass 14, count 2 2006.246.08:00:12.42#ibcon#*before return 0, iclass 14, count 2 2006.246.08:00:12.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:12.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:00:12.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.08:00:12.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:00:12.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:12.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:12.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:12.54#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:00:12.54#ibcon#first serial, iclass 14, count 0 2006.246.08:00:12.54#ibcon#enter sib2, iclass 14, count 0 2006.246.08:00:12.54#ibcon#flushed, iclass 14, count 0 2006.246.08:00:12.54#ibcon#about to write, iclass 14, count 0 2006.246.08:00:12.54#ibcon#wrote, iclass 14, count 0 2006.246.08:00:12.54#ibcon#about to read 3, iclass 14, count 0 2006.246.08:00:12.56#ibcon#read 3, iclass 14, count 0 2006.246.08:00:12.56#ibcon#about to read 4, iclass 14, count 0 2006.246.08:00:12.56#ibcon#read 4, iclass 14, count 0 2006.246.08:00:12.56#ibcon#about to read 5, iclass 14, count 0 2006.246.08:00:12.56#ibcon#read 5, iclass 14, count 0 2006.246.08:00:12.56#ibcon#about to read 6, iclass 14, count 0 2006.246.08:00:12.56#ibcon#read 6, iclass 14, count 0 2006.246.08:00:12.56#ibcon#end of sib2, iclass 14, count 0 2006.246.08:00:12.56#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:00:12.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:00:12.56#ibcon#[27=USB\r\n] 2006.246.08:00:12.56#ibcon#*before write, iclass 14, count 0 2006.246.08:00:12.56#ibcon#enter sib2, iclass 14, count 0 2006.246.08:00:12.56#ibcon#flushed, iclass 14, count 0 2006.246.08:00:12.56#ibcon#about to write, iclass 14, count 0 2006.246.08:00:12.56#ibcon#wrote, iclass 14, count 0 2006.246.08:00:12.56#ibcon#about to read 3, iclass 14, count 0 2006.246.08:00:12.59#ibcon#read 3, iclass 14, count 0 2006.246.08:00:12.59#ibcon#about to read 4, iclass 14, count 0 2006.246.08:00:12.59#ibcon#read 4, iclass 14, count 0 2006.246.08:00:12.59#ibcon#about to read 5, iclass 14, count 0 2006.246.08:00:12.59#ibcon#read 5, iclass 14, count 0 2006.246.08:00:12.59#ibcon#about to read 6, iclass 14, count 0 2006.246.08:00:12.59#ibcon#read 6, iclass 14, count 0 2006.246.08:00:12.59#ibcon#end of sib2, iclass 14, count 0 2006.246.08:00:12.59#ibcon#*after write, iclass 14, count 0 2006.246.08:00:12.59#ibcon#*before return 0, iclass 14, count 0 2006.246.08:00:12.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:12.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:00:12.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:00:12.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:00:12.59$vc4f8/vabw=wide 2006.246.08:00:12.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.08:00:12.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.08:00:12.59#ibcon#ireg 8 cls_cnt 0 2006.246.08:00:12.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:12.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:12.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:12.59#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:00:12.59#ibcon#first serial, iclass 16, count 0 2006.246.08:00:12.59#ibcon#enter sib2, iclass 16, count 0 2006.246.08:00:12.59#ibcon#flushed, iclass 16, count 0 2006.246.08:00:12.59#ibcon#about to write, iclass 16, count 0 2006.246.08:00:12.59#ibcon#wrote, iclass 16, count 0 2006.246.08:00:12.59#ibcon#about to read 3, iclass 16, count 0 2006.246.08:00:12.61#ibcon#read 3, iclass 16, count 0 2006.246.08:00:12.61#ibcon#about to read 4, iclass 16, count 0 2006.246.08:00:12.61#ibcon#read 4, iclass 16, count 0 2006.246.08:00:12.61#ibcon#about to read 5, iclass 16, count 0 2006.246.08:00:12.61#ibcon#read 5, iclass 16, count 0 2006.246.08:00:12.61#ibcon#about to read 6, iclass 16, count 0 2006.246.08:00:12.61#ibcon#read 6, iclass 16, count 0 2006.246.08:00:12.61#ibcon#end of sib2, iclass 16, count 0 2006.246.08:00:12.61#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:00:12.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:00:12.61#ibcon#[25=BW32\r\n] 2006.246.08:00:12.61#ibcon#*before write, iclass 16, count 0 2006.246.08:00:12.61#ibcon#enter sib2, iclass 16, count 0 2006.246.08:00:12.61#ibcon#flushed, iclass 16, count 0 2006.246.08:00:12.61#ibcon#about to write, iclass 16, count 0 2006.246.08:00:12.61#ibcon#wrote, iclass 16, count 0 2006.246.08:00:12.61#ibcon#about to read 3, iclass 16, count 0 2006.246.08:00:12.64#ibcon#read 3, iclass 16, count 0 2006.246.08:00:12.64#ibcon#about to read 4, iclass 16, count 0 2006.246.08:00:12.64#ibcon#read 4, iclass 16, count 0 2006.246.08:00:12.64#ibcon#about to read 5, iclass 16, count 0 2006.246.08:00:12.64#ibcon#read 5, iclass 16, count 0 2006.246.08:00:12.64#ibcon#about to read 6, iclass 16, count 0 2006.246.08:00:12.64#ibcon#read 6, iclass 16, count 0 2006.246.08:00:12.64#ibcon#end of sib2, iclass 16, count 0 2006.246.08:00:12.64#ibcon#*after write, iclass 16, count 0 2006.246.08:00:12.64#ibcon#*before return 0, iclass 16, count 0 2006.246.08:00:12.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:12.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:00:12.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:00:12.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:00:12.64$vc4f8/vbbw=wide 2006.246.08:00:12.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.08:00:12.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.08:00:12.64#ibcon#ireg 8 cls_cnt 0 2006.246.08:00:12.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:00:12.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:00:12.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:00:12.71#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:00:12.71#ibcon#first serial, iclass 18, count 0 2006.246.08:00:12.71#ibcon#enter sib2, iclass 18, count 0 2006.246.08:00:12.71#ibcon#flushed, iclass 18, count 0 2006.246.08:00:12.71#ibcon#about to write, iclass 18, count 0 2006.246.08:00:12.71#ibcon#wrote, iclass 18, count 0 2006.246.08:00:12.71#ibcon#about to read 3, iclass 18, count 0 2006.246.08:00:12.73#ibcon#read 3, iclass 18, count 0 2006.246.08:00:12.73#ibcon#about to read 4, iclass 18, count 0 2006.246.08:00:12.73#ibcon#read 4, iclass 18, count 0 2006.246.08:00:12.73#ibcon#about to read 5, iclass 18, count 0 2006.246.08:00:12.73#ibcon#read 5, iclass 18, count 0 2006.246.08:00:12.73#ibcon#about to read 6, iclass 18, count 0 2006.246.08:00:12.73#ibcon#read 6, iclass 18, count 0 2006.246.08:00:12.73#ibcon#end of sib2, iclass 18, count 0 2006.246.08:00:12.73#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:00:12.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:00:12.73#ibcon#[27=BW32\r\n] 2006.246.08:00:12.73#ibcon#*before write, iclass 18, count 0 2006.246.08:00:12.73#ibcon#enter sib2, iclass 18, count 0 2006.246.08:00:12.73#ibcon#flushed, iclass 18, count 0 2006.246.08:00:12.73#ibcon#about to write, iclass 18, count 0 2006.246.08:00:12.73#ibcon#wrote, iclass 18, count 0 2006.246.08:00:12.73#ibcon#about to read 3, iclass 18, count 0 2006.246.08:00:12.76#ibcon#read 3, iclass 18, count 0 2006.246.08:00:12.76#ibcon#about to read 4, iclass 18, count 0 2006.246.08:00:12.76#ibcon#read 4, iclass 18, count 0 2006.246.08:00:12.76#ibcon#about to read 5, iclass 18, count 0 2006.246.08:00:12.76#ibcon#read 5, iclass 18, count 0 2006.246.08:00:12.76#ibcon#about to read 6, iclass 18, count 0 2006.246.08:00:12.76#ibcon#read 6, iclass 18, count 0 2006.246.08:00:12.76#ibcon#end of sib2, iclass 18, count 0 2006.246.08:00:12.76#ibcon#*after write, iclass 18, count 0 2006.246.08:00:12.76#ibcon#*before return 0, iclass 18, count 0 2006.246.08:00:12.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:00:12.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:00:12.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:00:12.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:00:12.76$4f8m12a/ifd4f 2006.246.08:00:12.76$ifd4f/lo= 2006.246.08:00:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:00:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:00:12.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:00:12.76$ifd4f/patch= 2006.246.08:00:12.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:00:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:00:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:00:12.76$4f8m12a/"form=m,16.000,1:2 2006.246.08:00:12.76$4f8m12a/"tpicd 2006.246.08:00:12.76$4f8m12a/echo=off 2006.246.08:00:12.76$4f8m12a/xlog=off 2006.246.08:00:12.76:!2006.246.08:00:40 2006.246.08:00:25.14#trakl#Source acquired 2006.246.08:00:25.14#flagr#flagr/antenna,acquired 2006.246.08:00:40.00:preob 2006.246.08:00:41.14/onsource/TRACKING 2006.246.08:00:41.14:!2006.246.08:00:50 2006.246.08:00:50.00:data_valid=on 2006.246.08:00:50.00:midob 2006.246.08:00:50.14/onsource/TRACKING 2006.246.08:00:50.14/wx/26.60,1005.7,74 2006.246.08:00:50.29/cable/+6.4137E-03 2006.246.08:00:51.38/va/01,08,usb,yes,31,33 2006.246.08:00:51.38/va/02,07,usb,yes,31,32 2006.246.08:00:51.38/va/03,06,usb,yes,33,33 2006.246.08:00:51.38/va/04,07,usb,yes,32,35 2006.246.08:00:51.38/va/05,07,usb,yes,34,36 2006.246.08:00:51.38/va/06,07,usb,yes,30,30 2006.246.08:00:51.38/va/07,07,usb,yes,30,30 2006.246.08:00:51.38/va/08,08,usb,yes,26,26 2006.246.08:00:51.61/valo/01,532.99,yes,locked 2006.246.08:00:51.61/valo/02,572.99,yes,locked 2006.246.08:00:51.61/valo/03,672.99,yes,locked 2006.246.08:00:51.61/valo/04,832.99,yes,locked 2006.246.08:00:51.61/valo/05,652.99,yes,locked 2006.246.08:00:51.61/valo/06,772.99,yes,locked 2006.246.08:00:51.61/valo/07,832.99,yes,locked 2006.246.08:00:51.61/valo/08,852.99,yes,locked 2006.246.08:00:52.70/vb/01,04,usb,yes,31,29 2006.246.08:00:52.70/vb/02,04,usb,yes,33,34 2006.246.08:00:52.70/vb/03,04,usb,yes,29,33 2006.246.08:00:52.70/vb/04,04,usb,yes,30,30 2006.246.08:00:52.70/vb/05,03,usb,yes,35,40 2006.246.08:00:52.70/vb/06,03,usb,yes,36,39 2006.246.08:00:52.70/vb/07,04,usb,yes,31,31 2006.246.08:00:52.70/vb/08,03,usb,yes,36,40 2006.246.08:00:52.94/vblo/01,632.99,yes,locked 2006.246.08:00:52.94/vblo/02,640.99,yes,locked 2006.246.08:00:52.94/vblo/03,656.99,yes,locked 2006.246.08:00:52.94/vblo/04,712.99,yes,locked 2006.246.08:00:52.94/vblo/05,744.99,yes,locked 2006.246.08:00:52.94/vblo/06,752.99,yes,locked 2006.246.08:00:52.94/vblo/07,734.99,yes,locked 2006.246.08:00:52.94/vblo/08,744.99,yes,locked 2006.246.08:00:53.09/vabw/8 2006.246.08:00:53.24/vbbw/8 2006.246.08:00:53.33/xfe/off,on,13.2 2006.246.08:00:53.71/ifatt/23,28,28,28 2006.246.08:00:54.07/fmout-gps/S +4.39E-07 2006.246.08:00:54.11:!2006.246.08:01:50 2006.246.08:01:50.00:data_valid=off 2006.246.08:01:50.00:postob 2006.246.08:01:50.21/cable/+6.4140E-03 2006.246.08:01:50.21/wx/26.59,1005.7,74 2006.246.08:01:51.08/fmout-gps/S +4.40E-07 2006.246.08:01:51.08:scan_name=246-0802,k06246,60 2006.246.08:01:51.09:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.246.08:01:51.13#flagr#flagr/antenna,new-source 2006.246.08:01:52.13:checkk5 2006.246.08:01:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:01:52.87/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:01:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:01:53.62/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:01:53.99/chk_obsdata//k5ts1/T2460800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:01:54.36/chk_obsdata//k5ts2/T2460800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:01:54.72/chk_obsdata//k5ts3/T2460800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:01:55.09/chk_obsdata//k5ts4/T2460800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:01:55.79/k5log//k5ts1_log_newline 2006.246.08:01:56.49/k5log//k5ts2_log_newline 2006.246.08:01:57.17/k5log//k5ts3_log_newline 2006.246.08:01:57.86/k5log//k5ts4_log_newline 2006.246.08:01:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:01:57.89:4f8m12a=2 2006.246.08:01:57.89$4f8m12a/echo=on 2006.246.08:01:57.89$4f8m12a/pcalon 2006.246.08:01:57.89$pcalon/"no phase cal control is implemented here 2006.246.08:01:57.89$4f8m12a/"tpicd=stop 2006.246.08:01:57.89$4f8m12a/vc4f8 2006.246.08:01:57.89$vc4f8/valo=1,532.99 2006.246.08:01:57.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.08:01:57.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.08:01:57.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:57.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:01:57.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:01:57.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:01:57.89#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:01:57.89#ibcon#first serial, iclass 25, count 0 2006.246.08:01:57.89#ibcon#enter sib2, iclass 25, count 0 2006.246.08:01:57.89#ibcon#flushed, iclass 25, count 0 2006.246.08:01:57.89#ibcon#about to write, iclass 25, count 0 2006.246.08:01:57.89#ibcon#wrote, iclass 25, count 0 2006.246.08:01:57.89#ibcon#about to read 3, iclass 25, count 0 2006.246.08:01:57.93#ibcon#read 3, iclass 25, count 0 2006.246.08:01:57.93#ibcon#about to read 4, iclass 25, count 0 2006.246.08:01:57.93#ibcon#read 4, iclass 25, count 0 2006.246.08:01:57.93#ibcon#about to read 5, iclass 25, count 0 2006.246.08:01:57.93#ibcon#read 5, iclass 25, count 0 2006.246.08:01:57.93#ibcon#about to read 6, iclass 25, count 0 2006.246.08:01:57.93#ibcon#read 6, iclass 25, count 0 2006.246.08:01:57.93#ibcon#end of sib2, iclass 25, count 0 2006.246.08:01:57.93#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:01:57.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:01:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:01:57.93#ibcon#*before write, iclass 25, count 0 2006.246.08:01:57.93#ibcon#enter sib2, iclass 25, count 0 2006.246.08:01:57.93#ibcon#flushed, iclass 25, count 0 2006.246.08:01:57.93#ibcon#about to write, iclass 25, count 0 2006.246.08:01:57.93#ibcon#wrote, iclass 25, count 0 2006.246.08:01:57.93#ibcon#about to read 3, iclass 25, count 0 2006.246.08:01:57.98#ibcon#read 3, iclass 25, count 0 2006.246.08:01:57.98#ibcon#about to read 4, iclass 25, count 0 2006.246.08:01:57.98#ibcon#read 4, iclass 25, count 0 2006.246.08:01:57.98#ibcon#about to read 5, iclass 25, count 0 2006.246.08:01:57.98#ibcon#read 5, iclass 25, count 0 2006.246.08:01:57.98#ibcon#about to read 6, iclass 25, count 0 2006.246.08:01:57.98#ibcon#read 6, iclass 25, count 0 2006.246.08:01:57.98#ibcon#end of sib2, iclass 25, count 0 2006.246.08:01:57.98#ibcon#*after write, iclass 25, count 0 2006.246.08:01:57.98#ibcon#*before return 0, iclass 25, count 0 2006.246.08:01:57.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:01:57.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:01:57.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:01:57.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:01:57.98$vc4f8/va=1,8 2006.246.08:01:57.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.08:01:57.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.08:01:57.98#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:57.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:01:57.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:01:57.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:01:57.98#ibcon#enter wrdev, iclass 27, count 2 2006.246.08:01:57.98#ibcon#first serial, iclass 27, count 2 2006.246.08:01:57.98#ibcon#enter sib2, iclass 27, count 2 2006.246.08:01:57.98#ibcon#flushed, iclass 27, count 2 2006.246.08:01:57.98#ibcon#about to write, iclass 27, count 2 2006.246.08:01:57.98#ibcon#wrote, iclass 27, count 2 2006.246.08:01:57.98#ibcon#about to read 3, iclass 27, count 2 2006.246.08:01:58.00#ibcon#read 3, iclass 27, count 2 2006.246.08:01:58.00#ibcon#about to read 4, iclass 27, count 2 2006.246.08:01:58.00#ibcon#read 4, iclass 27, count 2 2006.246.08:01:58.00#ibcon#about to read 5, iclass 27, count 2 2006.246.08:01:58.00#ibcon#read 5, iclass 27, count 2 2006.246.08:01:58.00#ibcon#about to read 6, iclass 27, count 2 2006.246.08:01:58.00#ibcon#read 6, iclass 27, count 2 2006.246.08:01:58.00#ibcon#end of sib2, iclass 27, count 2 2006.246.08:01:58.00#ibcon#*mode == 0, iclass 27, count 2 2006.246.08:01:58.00#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.08:01:58.00#ibcon#[25=AT01-08\r\n] 2006.246.08:01:58.00#ibcon#*before write, iclass 27, count 2 2006.246.08:01:58.00#ibcon#enter sib2, iclass 27, count 2 2006.246.08:01:58.00#ibcon#flushed, iclass 27, count 2 2006.246.08:01:58.00#ibcon#about to write, iclass 27, count 2 2006.246.08:01:58.00#ibcon#wrote, iclass 27, count 2 2006.246.08:01:58.00#ibcon#about to read 3, iclass 27, count 2 2006.246.08:01:58.03#ibcon#read 3, iclass 27, count 2 2006.246.08:01:58.03#ibcon#about to read 4, iclass 27, count 2 2006.246.08:01:58.03#ibcon#read 4, iclass 27, count 2 2006.246.08:01:58.03#ibcon#about to read 5, iclass 27, count 2 2006.246.08:01:58.03#ibcon#read 5, iclass 27, count 2 2006.246.08:01:58.03#ibcon#about to read 6, iclass 27, count 2 2006.246.08:01:58.03#ibcon#read 6, iclass 27, count 2 2006.246.08:01:58.03#ibcon#end of sib2, iclass 27, count 2 2006.246.08:01:58.03#ibcon#*after write, iclass 27, count 2 2006.246.08:01:58.03#ibcon#*before return 0, iclass 27, count 2 2006.246.08:01:58.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:01:58.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:01:58.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.08:01:58.03#ibcon#ireg 7 cls_cnt 0 2006.246.08:01:58.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:01:58.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:01:58.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:01:58.15#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:01:58.15#ibcon#first serial, iclass 27, count 0 2006.246.08:01:58.15#ibcon#enter sib2, iclass 27, count 0 2006.246.08:01:58.15#ibcon#flushed, iclass 27, count 0 2006.246.08:01:58.15#ibcon#about to write, iclass 27, count 0 2006.246.08:01:58.15#ibcon#wrote, iclass 27, count 0 2006.246.08:01:58.15#ibcon#about to read 3, iclass 27, count 0 2006.246.08:01:58.17#ibcon#read 3, iclass 27, count 0 2006.246.08:01:58.17#ibcon#about to read 4, iclass 27, count 0 2006.246.08:01:58.17#ibcon#read 4, iclass 27, count 0 2006.246.08:01:58.17#ibcon#about to read 5, iclass 27, count 0 2006.246.08:01:58.17#ibcon#read 5, iclass 27, count 0 2006.246.08:01:58.17#ibcon#about to read 6, iclass 27, count 0 2006.246.08:01:58.17#ibcon#read 6, iclass 27, count 0 2006.246.08:01:58.17#ibcon#end of sib2, iclass 27, count 0 2006.246.08:01:58.17#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:01:58.17#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:01:58.17#ibcon#[25=USB\r\n] 2006.246.08:01:58.17#ibcon#*before write, iclass 27, count 0 2006.246.08:01:58.17#ibcon#enter sib2, iclass 27, count 0 2006.246.08:01:58.17#ibcon#flushed, iclass 27, count 0 2006.246.08:01:58.17#ibcon#about to write, iclass 27, count 0 2006.246.08:01:58.17#ibcon#wrote, iclass 27, count 0 2006.246.08:01:58.17#ibcon#about to read 3, iclass 27, count 0 2006.246.08:01:58.18#abcon#<5=/05 3.8 6.9 26.58 741005.7\r\n> 2006.246.08:01:58.20#abcon#{5=INTERFACE CLEAR} 2006.246.08:01:58.20#ibcon#read 3, iclass 27, count 0 2006.246.08:01:58.20#ibcon#about to read 4, iclass 27, count 0 2006.246.08:01:58.20#ibcon#read 4, iclass 27, count 0 2006.246.08:01:58.20#ibcon#about to read 5, iclass 27, count 0 2006.246.08:01:58.20#ibcon#read 5, iclass 27, count 0 2006.246.08:01:58.20#ibcon#about to read 6, iclass 27, count 0 2006.246.08:01:58.20#ibcon#read 6, iclass 27, count 0 2006.246.08:01:58.20#ibcon#end of sib2, iclass 27, count 0 2006.246.08:01:58.20#ibcon#*after write, iclass 27, count 0 2006.246.08:01:58.20#ibcon#*before return 0, iclass 27, count 0 2006.246.08:01:58.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:01:58.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:01:58.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:01:58.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:01:58.20$vc4f8/valo=2,572.99 2006.246.08:01:58.20#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:01:58.20#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:01:58.20#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:58.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:01:58.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:01:58.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:01:58.20#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:01:58.20#ibcon#first serial, iclass 32, count 0 2006.246.08:01:58.20#ibcon#enter sib2, iclass 32, count 0 2006.246.08:01:58.20#ibcon#flushed, iclass 32, count 0 2006.246.08:01:58.20#ibcon#about to write, iclass 32, count 0 2006.246.08:01:58.20#ibcon#wrote, iclass 32, count 0 2006.246.08:01:58.20#ibcon#about to read 3, iclass 32, count 0 2006.246.08:01:58.22#ibcon#read 3, iclass 32, count 0 2006.246.08:01:58.22#ibcon#about to read 4, iclass 32, count 0 2006.246.08:01:58.22#ibcon#read 4, iclass 32, count 0 2006.246.08:01:58.22#ibcon#about to read 5, iclass 32, count 0 2006.246.08:01:58.22#ibcon#read 5, iclass 32, count 0 2006.246.08:01:58.22#ibcon#about to read 6, iclass 32, count 0 2006.246.08:01:58.22#ibcon#read 6, iclass 32, count 0 2006.246.08:01:58.22#ibcon#end of sib2, iclass 32, count 0 2006.246.08:01:58.22#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:01:58.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:01:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:01:58.22#ibcon#*before write, iclass 32, count 0 2006.246.08:01:58.22#ibcon#enter sib2, iclass 32, count 0 2006.246.08:01:58.22#ibcon#flushed, iclass 32, count 0 2006.246.08:01:58.22#ibcon#about to write, iclass 32, count 0 2006.246.08:01:58.22#ibcon#wrote, iclass 32, count 0 2006.246.08:01:58.22#ibcon#about to read 3, iclass 32, count 0 2006.246.08:01:58.26#abcon#[5=S1D000X0/0*\r\n] 2006.246.08:01:58.26#ibcon#read 3, iclass 32, count 0 2006.246.08:01:58.26#ibcon#about to read 4, iclass 32, count 0 2006.246.08:01:58.26#ibcon#read 4, iclass 32, count 0 2006.246.08:01:58.26#ibcon#about to read 5, iclass 32, count 0 2006.246.08:01:58.26#ibcon#read 5, iclass 32, count 0 2006.246.08:01:58.26#ibcon#about to read 6, iclass 32, count 0 2006.246.08:01:58.26#ibcon#read 6, iclass 32, count 0 2006.246.08:01:58.26#ibcon#end of sib2, iclass 32, count 0 2006.246.08:01:58.26#ibcon#*after write, iclass 32, count 0 2006.246.08:01:58.26#ibcon#*before return 0, iclass 32, count 0 2006.246.08:01:58.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:01:58.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:01:58.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:01:58.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:01:58.26$vc4f8/va=2,7 2006.246.08:01:58.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.08:01:58.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.08:01:58.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:58.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:01:58.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:01:58.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:01:58.32#ibcon#enter wrdev, iclass 35, count 2 2006.246.08:01:58.32#ibcon#first serial, iclass 35, count 2 2006.246.08:01:58.32#ibcon#enter sib2, iclass 35, count 2 2006.246.08:01:58.32#ibcon#flushed, iclass 35, count 2 2006.246.08:01:58.32#ibcon#about to write, iclass 35, count 2 2006.246.08:01:58.32#ibcon#wrote, iclass 35, count 2 2006.246.08:01:58.32#ibcon#about to read 3, iclass 35, count 2 2006.246.08:01:58.34#ibcon#read 3, iclass 35, count 2 2006.246.08:01:58.34#ibcon#about to read 4, iclass 35, count 2 2006.246.08:01:58.34#ibcon#read 4, iclass 35, count 2 2006.246.08:01:58.34#ibcon#about to read 5, iclass 35, count 2 2006.246.08:01:58.34#ibcon#read 5, iclass 35, count 2 2006.246.08:01:58.34#ibcon#about to read 6, iclass 35, count 2 2006.246.08:01:58.34#ibcon#read 6, iclass 35, count 2 2006.246.08:01:58.34#ibcon#end of sib2, iclass 35, count 2 2006.246.08:01:58.34#ibcon#*mode == 0, iclass 35, count 2 2006.246.08:01:58.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.08:01:58.34#ibcon#[25=AT02-07\r\n] 2006.246.08:01:58.34#ibcon#*before write, iclass 35, count 2 2006.246.08:01:58.34#ibcon#enter sib2, iclass 35, count 2 2006.246.08:01:58.34#ibcon#flushed, iclass 35, count 2 2006.246.08:01:58.34#ibcon#about to write, iclass 35, count 2 2006.246.08:01:58.34#ibcon#wrote, iclass 35, count 2 2006.246.08:01:58.34#ibcon#about to read 3, iclass 35, count 2 2006.246.08:01:58.37#ibcon#read 3, iclass 35, count 2 2006.246.08:01:58.37#ibcon#about to read 4, iclass 35, count 2 2006.246.08:01:58.37#ibcon#read 4, iclass 35, count 2 2006.246.08:01:58.37#ibcon#about to read 5, iclass 35, count 2 2006.246.08:01:58.37#ibcon#read 5, iclass 35, count 2 2006.246.08:01:58.37#ibcon#about to read 6, iclass 35, count 2 2006.246.08:01:58.37#ibcon#read 6, iclass 35, count 2 2006.246.08:01:58.37#ibcon#end of sib2, iclass 35, count 2 2006.246.08:01:58.37#ibcon#*after write, iclass 35, count 2 2006.246.08:01:58.37#ibcon#*before return 0, iclass 35, count 2 2006.246.08:01:58.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:01:58.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:01:58.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.08:01:58.37#ibcon#ireg 7 cls_cnt 0 2006.246.08:01:58.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:01:58.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:01:58.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:01:58.49#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:01:58.49#ibcon#first serial, iclass 35, count 0 2006.246.08:01:58.49#ibcon#enter sib2, iclass 35, count 0 2006.246.08:01:58.49#ibcon#flushed, iclass 35, count 0 2006.246.08:01:58.49#ibcon#about to write, iclass 35, count 0 2006.246.08:01:58.49#ibcon#wrote, iclass 35, count 0 2006.246.08:01:58.49#ibcon#about to read 3, iclass 35, count 0 2006.246.08:01:58.51#ibcon#read 3, iclass 35, count 0 2006.246.08:01:58.51#ibcon#about to read 4, iclass 35, count 0 2006.246.08:01:58.51#ibcon#read 4, iclass 35, count 0 2006.246.08:01:58.51#ibcon#about to read 5, iclass 35, count 0 2006.246.08:01:58.51#ibcon#read 5, iclass 35, count 0 2006.246.08:01:58.51#ibcon#about to read 6, iclass 35, count 0 2006.246.08:01:58.51#ibcon#read 6, iclass 35, count 0 2006.246.08:01:58.51#ibcon#end of sib2, iclass 35, count 0 2006.246.08:01:58.51#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:01:58.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:01:58.51#ibcon#[25=USB\r\n] 2006.246.08:01:58.51#ibcon#*before write, iclass 35, count 0 2006.246.08:01:58.51#ibcon#enter sib2, iclass 35, count 0 2006.246.08:01:58.51#ibcon#flushed, iclass 35, count 0 2006.246.08:01:58.51#ibcon#about to write, iclass 35, count 0 2006.246.08:01:58.51#ibcon#wrote, iclass 35, count 0 2006.246.08:01:58.51#ibcon#about to read 3, iclass 35, count 0 2006.246.08:01:58.54#ibcon#read 3, iclass 35, count 0 2006.246.08:01:58.54#ibcon#about to read 4, iclass 35, count 0 2006.246.08:01:58.54#ibcon#read 4, iclass 35, count 0 2006.246.08:01:58.54#ibcon#about to read 5, iclass 35, count 0 2006.246.08:01:58.54#ibcon#read 5, iclass 35, count 0 2006.246.08:01:58.54#ibcon#about to read 6, iclass 35, count 0 2006.246.08:01:58.54#ibcon#read 6, iclass 35, count 0 2006.246.08:01:58.54#ibcon#end of sib2, iclass 35, count 0 2006.246.08:01:58.54#ibcon#*after write, iclass 35, count 0 2006.246.08:01:58.54#ibcon#*before return 0, iclass 35, count 0 2006.246.08:01:58.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:01:58.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:01:58.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:01:58.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:01:58.54$vc4f8/valo=3,672.99 2006.246.08:01:58.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.08:01:58.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.08:01:58.54#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:58.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:01:58.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:01:58.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:01:58.54#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:01:58.54#ibcon#first serial, iclass 37, count 0 2006.246.08:01:58.54#ibcon#enter sib2, iclass 37, count 0 2006.246.08:01:58.54#ibcon#flushed, iclass 37, count 0 2006.246.08:01:58.54#ibcon#about to write, iclass 37, count 0 2006.246.08:01:58.54#ibcon#wrote, iclass 37, count 0 2006.246.08:01:58.54#ibcon#about to read 3, iclass 37, count 0 2006.246.08:01:58.56#ibcon#read 3, iclass 37, count 0 2006.246.08:01:58.56#ibcon#about to read 4, iclass 37, count 0 2006.246.08:01:58.56#ibcon#read 4, iclass 37, count 0 2006.246.08:01:58.56#ibcon#about to read 5, iclass 37, count 0 2006.246.08:01:58.56#ibcon#read 5, iclass 37, count 0 2006.246.08:01:58.56#ibcon#about to read 6, iclass 37, count 0 2006.246.08:01:58.56#ibcon#read 6, iclass 37, count 0 2006.246.08:01:58.56#ibcon#end of sib2, iclass 37, count 0 2006.246.08:01:58.56#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:01:58.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:01:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:01:58.56#ibcon#*before write, iclass 37, count 0 2006.246.08:01:58.56#ibcon#enter sib2, iclass 37, count 0 2006.246.08:01:58.56#ibcon#flushed, iclass 37, count 0 2006.246.08:01:58.56#ibcon#about to write, iclass 37, count 0 2006.246.08:01:58.56#ibcon#wrote, iclass 37, count 0 2006.246.08:01:58.56#ibcon#about to read 3, iclass 37, count 0 2006.246.08:01:58.60#ibcon#read 3, iclass 37, count 0 2006.246.08:01:58.60#ibcon#about to read 4, iclass 37, count 0 2006.246.08:01:58.60#ibcon#read 4, iclass 37, count 0 2006.246.08:01:58.60#ibcon#about to read 5, iclass 37, count 0 2006.246.08:01:58.60#ibcon#read 5, iclass 37, count 0 2006.246.08:01:58.60#ibcon#about to read 6, iclass 37, count 0 2006.246.08:01:58.60#ibcon#read 6, iclass 37, count 0 2006.246.08:01:58.60#ibcon#end of sib2, iclass 37, count 0 2006.246.08:01:58.60#ibcon#*after write, iclass 37, count 0 2006.246.08:01:58.60#ibcon#*before return 0, iclass 37, count 0 2006.246.08:01:58.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:01:58.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:01:58.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:01:58.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:01:58.60$vc4f8/va=3,6 2006.246.08:01:58.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.08:01:58.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.08:01:58.60#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:58.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:01:58.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:01:58.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:01:58.66#ibcon#enter wrdev, iclass 39, count 2 2006.246.08:01:58.66#ibcon#first serial, iclass 39, count 2 2006.246.08:01:58.66#ibcon#enter sib2, iclass 39, count 2 2006.246.08:01:58.66#ibcon#flushed, iclass 39, count 2 2006.246.08:01:58.66#ibcon#about to write, iclass 39, count 2 2006.246.08:01:58.66#ibcon#wrote, iclass 39, count 2 2006.246.08:01:58.66#ibcon#about to read 3, iclass 39, count 2 2006.246.08:01:58.68#ibcon#read 3, iclass 39, count 2 2006.246.08:01:58.68#ibcon#about to read 4, iclass 39, count 2 2006.246.08:01:58.68#ibcon#read 4, iclass 39, count 2 2006.246.08:01:58.68#ibcon#about to read 5, iclass 39, count 2 2006.246.08:01:58.68#ibcon#read 5, iclass 39, count 2 2006.246.08:01:58.68#ibcon#about to read 6, iclass 39, count 2 2006.246.08:01:58.68#ibcon#read 6, iclass 39, count 2 2006.246.08:01:58.68#ibcon#end of sib2, iclass 39, count 2 2006.246.08:01:58.68#ibcon#*mode == 0, iclass 39, count 2 2006.246.08:01:58.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.08:01:58.68#ibcon#[25=AT03-06\r\n] 2006.246.08:01:58.68#ibcon#*before write, iclass 39, count 2 2006.246.08:01:58.68#ibcon#enter sib2, iclass 39, count 2 2006.246.08:01:58.68#ibcon#flushed, iclass 39, count 2 2006.246.08:01:58.68#ibcon#about to write, iclass 39, count 2 2006.246.08:01:58.68#ibcon#wrote, iclass 39, count 2 2006.246.08:01:58.68#ibcon#about to read 3, iclass 39, count 2 2006.246.08:01:58.71#ibcon#read 3, iclass 39, count 2 2006.246.08:01:58.71#ibcon#about to read 4, iclass 39, count 2 2006.246.08:01:58.71#ibcon#read 4, iclass 39, count 2 2006.246.08:01:58.71#ibcon#about to read 5, iclass 39, count 2 2006.246.08:01:58.71#ibcon#read 5, iclass 39, count 2 2006.246.08:01:58.71#ibcon#about to read 6, iclass 39, count 2 2006.246.08:01:58.71#ibcon#read 6, iclass 39, count 2 2006.246.08:01:58.71#ibcon#end of sib2, iclass 39, count 2 2006.246.08:01:58.71#ibcon#*after write, iclass 39, count 2 2006.246.08:01:58.71#ibcon#*before return 0, iclass 39, count 2 2006.246.08:01:58.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:01:58.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:01:58.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.08:01:58.71#ibcon#ireg 7 cls_cnt 0 2006.246.08:01:58.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:01:58.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:01:58.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:01:58.83#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:01:58.83#ibcon#first serial, iclass 39, count 0 2006.246.08:01:58.83#ibcon#enter sib2, iclass 39, count 0 2006.246.08:01:58.83#ibcon#flushed, iclass 39, count 0 2006.246.08:01:58.83#ibcon#about to write, iclass 39, count 0 2006.246.08:01:58.83#ibcon#wrote, iclass 39, count 0 2006.246.08:01:58.83#ibcon#about to read 3, iclass 39, count 0 2006.246.08:01:58.85#ibcon#read 3, iclass 39, count 0 2006.246.08:01:58.85#ibcon#about to read 4, iclass 39, count 0 2006.246.08:01:58.85#ibcon#read 4, iclass 39, count 0 2006.246.08:01:58.85#ibcon#about to read 5, iclass 39, count 0 2006.246.08:01:58.85#ibcon#read 5, iclass 39, count 0 2006.246.08:01:58.85#ibcon#about to read 6, iclass 39, count 0 2006.246.08:01:58.85#ibcon#read 6, iclass 39, count 0 2006.246.08:01:58.85#ibcon#end of sib2, iclass 39, count 0 2006.246.08:01:58.85#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:01:58.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:01:58.85#ibcon#[25=USB\r\n] 2006.246.08:01:58.85#ibcon#*before write, iclass 39, count 0 2006.246.08:01:58.85#ibcon#enter sib2, iclass 39, count 0 2006.246.08:01:58.85#ibcon#flushed, iclass 39, count 0 2006.246.08:01:58.85#ibcon#about to write, iclass 39, count 0 2006.246.08:01:58.85#ibcon#wrote, iclass 39, count 0 2006.246.08:01:58.85#ibcon#about to read 3, iclass 39, count 0 2006.246.08:01:58.88#ibcon#read 3, iclass 39, count 0 2006.246.08:01:58.88#ibcon#about to read 4, iclass 39, count 0 2006.246.08:01:58.88#ibcon#read 4, iclass 39, count 0 2006.246.08:01:58.88#ibcon#about to read 5, iclass 39, count 0 2006.246.08:01:58.88#ibcon#read 5, iclass 39, count 0 2006.246.08:01:58.88#ibcon#about to read 6, iclass 39, count 0 2006.246.08:01:58.88#ibcon#read 6, iclass 39, count 0 2006.246.08:01:58.88#ibcon#end of sib2, iclass 39, count 0 2006.246.08:01:58.88#ibcon#*after write, iclass 39, count 0 2006.246.08:01:58.88#ibcon#*before return 0, iclass 39, count 0 2006.246.08:01:58.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:01:58.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:01:58.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:01:58.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:01:58.88$vc4f8/valo=4,832.99 2006.246.08:01:58.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.08:01:58.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.08:01:58.88#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:58.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:01:58.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:01:58.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:01:58.88#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:01:58.88#ibcon#first serial, iclass 3, count 0 2006.246.08:01:58.88#ibcon#enter sib2, iclass 3, count 0 2006.246.08:01:58.88#ibcon#flushed, iclass 3, count 0 2006.246.08:01:58.88#ibcon#about to write, iclass 3, count 0 2006.246.08:01:58.88#ibcon#wrote, iclass 3, count 0 2006.246.08:01:58.88#ibcon#about to read 3, iclass 3, count 0 2006.246.08:01:58.90#ibcon#read 3, iclass 3, count 0 2006.246.08:01:58.90#ibcon#about to read 4, iclass 3, count 0 2006.246.08:01:58.90#ibcon#read 4, iclass 3, count 0 2006.246.08:01:58.90#ibcon#about to read 5, iclass 3, count 0 2006.246.08:01:58.90#ibcon#read 5, iclass 3, count 0 2006.246.08:01:58.90#ibcon#about to read 6, iclass 3, count 0 2006.246.08:01:58.90#ibcon#read 6, iclass 3, count 0 2006.246.08:01:58.90#ibcon#end of sib2, iclass 3, count 0 2006.246.08:01:58.90#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:01:58.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:01:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:01:58.90#ibcon#*before write, iclass 3, count 0 2006.246.08:01:58.90#ibcon#enter sib2, iclass 3, count 0 2006.246.08:01:58.90#ibcon#flushed, iclass 3, count 0 2006.246.08:01:58.90#ibcon#about to write, iclass 3, count 0 2006.246.08:01:58.90#ibcon#wrote, iclass 3, count 0 2006.246.08:01:58.90#ibcon#about to read 3, iclass 3, count 0 2006.246.08:01:58.94#ibcon#read 3, iclass 3, count 0 2006.246.08:01:58.94#ibcon#about to read 4, iclass 3, count 0 2006.246.08:01:58.94#ibcon#read 4, iclass 3, count 0 2006.246.08:01:58.94#ibcon#about to read 5, iclass 3, count 0 2006.246.08:01:58.94#ibcon#read 5, iclass 3, count 0 2006.246.08:01:58.94#ibcon#about to read 6, iclass 3, count 0 2006.246.08:01:58.94#ibcon#read 6, iclass 3, count 0 2006.246.08:01:58.94#ibcon#end of sib2, iclass 3, count 0 2006.246.08:01:58.94#ibcon#*after write, iclass 3, count 0 2006.246.08:01:58.94#ibcon#*before return 0, iclass 3, count 0 2006.246.08:01:58.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:01:58.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:01:58.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:01:58.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:01:58.94$vc4f8/va=4,7 2006.246.08:01:58.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.08:01:58.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.08:01:58.94#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:58.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:01:59.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:01:59.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:01:59.00#ibcon#enter wrdev, iclass 5, count 2 2006.246.08:01:59.00#ibcon#first serial, iclass 5, count 2 2006.246.08:01:59.00#ibcon#enter sib2, iclass 5, count 2 2006.246.08:01:59.00#ibcon#flushed, iclass 5, count 2 2006.246.08:01:59.00#ibcon#about to write, iclass 5, count 2 2006.246.08:01:59.00#ibcon#wrote, iclass 5, count 2 2006.246.08:01:59.00#ibcon#about to read 3, iclass 5, count 2 2006.246.08:01:59.02#ibcon#read 3, iclass 5, count 2 2006.246.08:01:59.02#ibcon#about to read 4, iclass 5, count 2 2006.246.08:01:59.02#ibcon#read 4, iclass 5, count 2 2006.246.08:01:59.02#ibcon#about to read 5, iclass 5, count 2 2006.246.08:01:59.02#ibcon#read 5, iclass 5, count 2 2006.246.08:01:59.02#ibcon#about to read 6, iclass 5, count 2 2006.246.08:01:59.02#ibcon#read 6, iclass 5, count 2 2006.246.08:01:59.02#ibcon#end of sib2, iclass 5, count 2 2006.246.08:01:59.02#ibcon#*mode == 0, iclass 5, count 2 2006.246.08:01:59.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.08:01:59.02#ibcon#[25=AT04-07\r\n] 2006.246.08:01:59.02#ibcon#*before write, iclass 5, count 2 2006.246.08:01:59.02#ibcon#enter sib2, iclass 5, count 2 2006.246.08:01:59.02#ibcon#flushed, iclass 5, count 2 2006.246.08:01:59.02#ibcon#about to write, iclass 5, count 2 2006.246.08:01:59.02#ibcon#wrote, iclass 5, count 2 2006.246.08:01:59.02#ibcon#about to read 3, iclass 5, count 2 2006.246.08:01:59.05#ibcon#read 3, iclass 5, count 2 2006.246.08:01:59.05#ibcon#about to read 4, iclass 5, count 2 2006.246.08:01:59.05#ibcon#read 4, iclass 5, count 2 2006.246.08:01:59.05#ibcon#about to read 5, iclass 5, count 2 2006.246.08:01:59.05#ibcon#read 5, iclass 5, count 2 2006.246.08:01:59.05#ibcon#about to read 6, iclass 5, count 2 2006.246.08:01:59.05#ibcon#read 6, iclass 5, count 2 2006.246.08:01:59.05#ibcon#end of sib2, iclass 5, count 2 2006.246.08:01:59.05#ibcon#*after write, iclass 5, count 2 2006.246.08:01:59.05#ibcon#*before return 0, iclass 5, count 2 2006.246.08:01:59.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:01:59.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:01:59.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.08:01:59.05#ibcon#ireg 7 cls_cnt 0 2006.246.08:01:59.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:01:59.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:01:59.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:01:59.17#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:01:59.17#ibcon#first serial, iclass 5, count 0 2006.246.08:01:59.17#ibcon#enter sib2, iclass 5, count 0 2006.246.08:01:59.17#ibcon#flushed, iclass 5, count 0 2006.246.08:01:59.17#ibcon#about to write, iclass 5, count 0 2006.246.08:01:59.17#ibcon#wrote, iclass 5, count 0 2006.246.08:01:59.17#ibcon#about to read 3, iclass 5, count 0 2006.246.08:01:59.19#ibcon#read 3, iclass 5, count 0 2006.246.08:01:59.19#ibcon#about to read 4, iclass 5, count 0 2006.246.08:01:59.19#ibcon#read 4, iclass 5, count 0 2006.246.08:01:59.19#ibcon#about to read 5, iclass 5, count 0 2006.246.08:01:59.19#ibcon#read 5, iclass 5, count 0 2006.246.08:01:59.19#ibcon#about to read 6, iclass 5, count 0 2006.246.08:01:59.19#ibcon#read 6, iclass 5, count 0 2006.246.08:01:59.19#ibcon#end of sib2, iclass 5, count 0 2006.246.08:01:59.19#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:01:59.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:01:59.19#ibcon#[25=USB\r\n] 2006.246.08:01:59.19#ibcon#*before write, iclass 5, count 0 2006.246.08:01:59.19#ibcon#enter sib2, iclass 5, count 0 2006.246.08:01:59.19#ibcon#flushed, iclass 5, count 0 2006.246.08:01:59.19#ibcon#about to write, iclass 5, count 0 2006.246.08:01:59.19#ibcon#wrote, iclass 5, count 0 2006.246.08:01:59.19#ibcon#about to read 3, iclass 5, count 0 2006.246.08:01:59.22#ibcon#read 3, iclass 5, count 0 2006.246.08:01:59.22#ibcon#about to read 4, iclass 5, count 0 2006.246.08:01:59.22#ibcon#read 4, iclass 5, count 0 2006.246.08:01:59.22#ibcon#about to read 5, iclass 5, count 0 2006.246.08:01:59.22#ibcon#read 5, iclass 5, count 0 2006.246.08:01:59.22#ibcon#about to read 6, iclass 5, count 0 2006.246.08:01:59.22#ibcon#read 6, iclass 5, count 0 2006.246.08:01:59.22#ibcon#end of sib2, iclass 5, count 0 2006.246.08:01:59.22#ibcon#*after write, iclass 5, count 0 2006.246.08:01:59.22#ibcon#*before return 0, iclass 5, count 0 2006.246.08:01:59.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:01:59.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:01:59.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:01:59.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:01:59.22$vc4f8/valo=5,652.99 2006.246.08:01:59.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.08:01:59.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.08:01:59.22#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:59.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:01:59.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:01:59.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:01:59.22#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:01:59.22#ibcon#first serial, iclass 7, count 0 2006.246.08:01:59.22#ibcon#enter sib2, iclass 7, count 0 2006.246.08:01:59.22#ibcon#flushed, iclass 7, count 0 2006.246.08:01:59.22#ibcon#about to write, iclass 7, count 0 2006.246.08:01:59.22#ibcon#wrote, iclass 7, count 0 2006.246.08:01:59.22#ibcon#about to read 3, iclass 7, count 0 2006.246.08:01:59.24#ibcon#read 3, iclass 7, count 0 2006.246.08:01:59.24#ibcon#about to read 4, iclass 7, count 0 2006.246.08:01:59.24#ibcon#read 4, iclass 7, count 0 2006.246.08:01:59.24#ibcon#about to read 5, iclass 7, count 0 2006.246.08:01:59.24#ibcon#read 5, iclass 7, count 0 2006.246.08:01:59.24#ibcon#about to read 6, iclass 7, count 0 2006.246.08:01:59.24#ibcon#read 6, iclass 7, count 0 2006.246.08:01:59.24#ibcon#end of sib2, iclass 7, count 0 2006.246.08:01:59.24#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:01:59.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:01:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:01:59.24#ibcon#*before write, iclass 7, count 0 2006.246.08:01:59.24#ibcon#enter sib2, iclass 7, count 0 2006.246.08:01:59.24#ibcon#flushed, iclass 7, count 0 2006.246.08:01:59.24#ibcon#about to write, iclass 7, count 0 2006.246.08:01:59.24#ibcon#wrote, iclass 7, count 0 2006.246.08:01:59.24#ibcon#about to read 3, iclass 7, count 0 2006.246.08:01:59.28#ibcon#read 3, iclass 7, count 0 2006.246.08:01:59.28#ibcon#about to read 4, iclass 7, count 0 2006.246.08:01:59.28#ibcon#read 4, iclass 7, count 0 2006.246.08:01:59.28#ibcon#about to read 5, iclass 7, count 0 2006.246.08:01:59.28#ibcon#read 5, iclass 7, count 0 2006.246.08:01:59.28#ibcon#about to read 6, iclass 7, count 0 2006.246.08:01:59.28#ibcon#read 6, iclass 7, count 0 2006.246.08:01:59.28#ibcon#end of sib2, iclass 7, count 0 2006.246.08:01:59.28#ibcon#*after write, iclass 7, count 0 2006.246.08:01:59.28#ibcon#*before return 0, iclass 7, count 0 2006.246.08:01:59.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:01:59.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:01:59.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:01:59.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:01:59.28$vc4f8/va=5,7 2006.246.08:01:59.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.08:01:59.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.08:01:59.28#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:59.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:01:59.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:01:59.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:01:59.34#ibcon#enter wrdev, iclass 11, count 2 2006.246.08:01:59.34#ibcon#first serial, iclass 11, count 2 2006.246.08:01:59.34#ibcon#enter sib2, iclass 11, count 2 2006.246.08:01:59.34#ibcon#flushed, iclass 11, count 2 2006.246.08:01:59.34#ibcon#about to write, iclass 11, count 2 2006.246.08:01:59.34#ibcon#wrote, iclass 11, count 2 2006.246.08:01:59.34#ibcon#about to read 3, iclass 11, count 2 2006.246.08:01:59.36#ibcon#read 3, iclass 11, count 2 2006.246.08:01:59.36#ibcon#about to read 4, iclass 11, count 2 2006.246.08:01:59.36#ibcon#read 4, iclass 11, count 2 2006.246.08:01:59.36#ibcon#about to read 5, iclass 11, count 2 2006.246.08:01:59.36#ibcon#read 5, iclass 11, count 2 2006.246.08:01:59.36#ibcon#about to read 6, iclass 11, count 2 2006.246.08:01:59.36#ibcon#read 6, iclass 11, count 2 2006.246.08:01:59.36#ibcon#end of sib2, iclass 11, count 2 2006.246.08:01:59.36#ibcon#*mode == 0, iclass 11, count 2 2006.246.08:01:59.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.08:01:59.36#ibcon#[25=AT05-07\r\n] 2006.246.08:01:59.36#ibcon#*before write, iclass 11, count 2 2006.246.08:01:59.36#ibcon#enter sib2, iclass 11, count 2 2006.246.08:01:59.36#ibcon#flushed, iclass 11, count 2 2006.246.08:01:59.36#ibcon#about to write, iclass 11, count 2 2006.246.08:01:59.36#ibcon#wrote, iclass 11, count 2 2006.246.08:01:59.36#ibcon#about to read 3, iclass 11, count 2 2006.246.08:01:59.39#ibcon#read 3, iclass 11, count 2 2006.246.08:01:59.39#ibcon#about to read 4, iclass 11, count 2 2006.246.08:01:59.39#ibcon#read 4, iclass 11, count 2 2006.246.08:01:59.39#ibcon#about to read 5, iclass 11, count 2 2006.246.08:01:59.39#ibcon#read 5, iclass 11, count 2 2006.246.08:01:59.39#ibcon#about to read 6, iclass 11, count 2 2006.246.08:01:59.39#ibcon#read 6, iclass 11, count 2 2006.246.08:01:59.39#ibcon#end of sib2, iclass 11, count 2 2006.246.08:01:59.39#ibcon#*after write, iclass 11, count 2 2006.246.08:01:59.39#ibcon#*before return 0, iclass 11, count 2 2006.246.08:01:59.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:01:59.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:01:59.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.08:01:59.39#ibcon#ireg 7 cls_cnt 0 2006.246.08:01:59.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:01:59.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:01:59.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:01:59.51#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:01:59.51#ibcon#first serial, iclass 11, count 0 2006.246.08:01:59.51#ibcon#enter sib2, iclass 11, count 0 2006.246.08:01:59.51#ibcon#flushed, iclass 11, count 0 2006.246.08:01:59.51#ibcon#about to write, iclass 11, count 0 2006.246.08:01:59.51#ibcon#wrote, iclass 11, count 0 2006.246.08:01:59.51#ibcon#about to read 3, iclass 11, count 0 2006.246.08:01:59.53#ibcon#read 3, iclass 11, count 0 2006.246.08:01:59.53#ibcon#about to read 4, iclass 11, count 0 2006.246.08:01:59.53#ibcon#read 4, iclass 11, count 0 2006.246.08:01:59.53#ibcon#about to read 5, iclass 11, count 0 2006.246.08:01:59.53#ibcon#read 5, iclass 11, count 0 2006.246.08:01:59.53#ibcon#about to read 6, iclass 11, count 0 2006.246.08:01:59.53#ibcon#read 6, iclass 11, count 0 2006.246.08:01:59.53#ibcon#end of sib2, iclass 11, count 0 2006.246.08:01:59.53#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:01:59.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:01:59.53#ibcon#[25=USB\r\n] 2006.246.08:01:59.53#ibcon#*before write, iclass 11, count 0 2006.246.08:01:59.53#ibcon#enter sib2, iclass 11, count 0 2006.246.08:01:59.53#ibcon#flushed, iclass 11, count 0 2006.246.08:01:59.53#ibcon#about to write, iclass 11, count 0 2006.246.08:01:59.53#ibcon#wrote, iclass 11, count 0 2006.246.08:01:59.53#ibcon#about to read 3, iclass 11, count 0 2006.246.08:01:59.56#ibcon#read 3, iclass 11, count 0 2006.246.08:01:59.56#ibcon#about to read 4, iclass 11, count 0 2006.246.08:01:59.56#ibcon#read 4, iclass 11, count 0 2006.246.08:01:59.56#ibcon#about to read 5, iclass 11, count 0 2006.246.08:01:59.56#ibcon#read 5, iclass 11, count 0 2006.246.08:01:59.56#ibcon#about to read 6, iclass 11, count 0 2006.246.08:01:59.56#ibcon#read 6, iclass 11, count 0 2006.246.08:01:59.56#ibcon#end of sib2, iclass 11, count 0 2006.246.08:01:59.56#ibcon#*after write, iclass 11, count 0 2006.246.08:01:59.56#ibcon#*before return 0, iclass 11, count 0 2006.246.08:01:59.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:01:59.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:01:59.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:01:59.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:01:59.56$vc4f8/valo=6,772.99 2006.246.08:01:59.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:01:59.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:01:59.56#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:59.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:01:59.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:01:59.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:01:59.56#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:01:59.56#ibcon#first serial, iclass 13, count 0 2006.246.08:01:59.56#ibcon#enter sib2, iclass 13, count 0 2006.246.08:01:59.56#ibcon#flushed, iclass 13, count 0 2006.246.08:01:59.56#ibcon#about to write, iclass 13, count 0 2006.246.08:01:59.56#ibcon#wrote, iclass 13, count 0 2006.246.08:01:59.56#ibcon#about to read 3, iclass 13, count 0 2006.246.08:01:59.58#ibcon#read 3, iclass 13, count 0 2006.246.08:01:59.58#ibcon#about to read 4, iclass 13, count 0 2006.246.08:01:59.58#ibcon#read 4, iclass 13, count 0 2006.246.08:01:59.58#ibcon#about to read 5, iclass 13, count 0 2006.246.08:01:59.58#ibcon#read 5, iclass 13, count 0 2006.246.08:01:59.58#ibcon#about to read 6, iclass 13, count 0 2006.246.08:01:59.58#ibcon#read 6, iclass 13, count 0 2006.246.08:01:59.58#ibcon#end of sib2, iclass 13, count 0 2006.246.08:01:59.58#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:01:59.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:01:59.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:01:59.58#ibcon#*before write, iclass 13, count 0 2006.246.08:01:59.58#ibcon#enter sib2, iclass 13, count 0 2006.246.08:01:59.58#ibcon#flushed, iclass 13, count 0 2006.246.08:01:59.58#ibcon#about to write, iclass 13, count 0 2006.246.08:01:59.58#ibcon#wrote, iclass 13, count 0 2006.246.08:01:59.58#ibcon#about to read 3, iclass 13, count 0 2006.246.08:01:59.62#ibcon#read 3, iclass 13, count 0 2006.246.08:01:59.62#ibcon#about to read 4, iclass 13, count 0 2006.246.08:01:59.62#ibcon#read 4, iclass 13, count 0 2006.246.08:01:59.62#ibcon#about to read 5, iclass 13, count 0 2006.246.08:01:59.62#ibcon#read 5, iclass 13, count 0 2006.246.08:01:59.62#ibcon#about to read 6, iclass 13, count 0 2006.246.08:01:59.62#ibcon#read 6, iclass 13, count 0 2006.246.08:01:59.62#ibcon#end of sib2, iclass 13, count 0 2006.246.08:01:59.62#ibcon#*after write, iclass 13, count 0 2006.246.08:01:59.62#ibcon#*before return 0, iclass 13, count 0 2006.246.08:01:59.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:01:59.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:01:59.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:01:59.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:01:59.62$vc4f8/va=6,7 2006.246.08:01:59.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.08:01:59.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.08:01:59.62#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:59.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:01:59.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:01:59.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:01:59.68#ibcon#enter wrdev, iclass 15, count 2 2006.246.08:01:59.68#ibcon#first serial, iclass 15, count 2 2006.246.08:01:59.68#ibcon#enter sib2, iclass 15, count 2 2006.246.08:01:59.68#ibcon#flushed, iclass 15, count 2 2006.246.08:01:59.68#ibcon#about to write, iclass 15, count 2 2006.246.08:01:59.68#ibcon#wrote, iclass 15, count 2 2006.246.08:01:59.68#ibcon#about to read 3, iclass 15, count 2 2006.246.08:01:59.70#ibcon#read 3, iclass 15, count 2 2006.246.08:01:59.70#ibcon#about to read 4, iclass 15, count 2 2006.246.08:01:59.70#ibcon#read 4, iclass 15, count 2 2006.246.08:01:59.70#ibcon#about to read 5, iclass 15, count 2 2006.246.08:01:59.70#ibcon#read 5, iclass 15, count 2 2006.246.08:01:59.70#ibcon#about to read 6, iclass 15, count 2 2006.246.08:01:59.70#ibcon#read 6, iclass 15, count 2 2006.246.08:01:59.70#ibcon#end of sib2, iclass 15, count 2 2006.246.08:01:59.70#ibcon#*mode == 0, iclass 15, count 2 2006.246.08:01:59.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.08:01:59.70#ibcon#[25=AT06-07\r\n] 2006.246.08:01:59.70#ibcon#*before write, iclass 15, count 2 2006.246.08:01:59.70#ibcon#enter sib2, iclass 15, count 2 2006.246.08:01:59.70#ibcon#flushed, iclass 15, count 2 2006.246.08:01:59.70#ibcon#about to write, iclass 15, count 2 2006.246.08:01:59.70#ibcon#wrote, iclass 15, count 2 2006.246.08:01:59.70#ibcon#about to read 3, iclass 15, count 2 2006.246.08:01:59.73#ibcon#read 3, iclass 15, count 2 2006.246.08:01:59.73#ibcon#about to read 4, iclass 15, count 2 2006.246.08:01:59.73#ibcon#read 4, iclass 15, count 2 2006.246.08:01:59.73#ibcon#about to read 5, iclass 15, count 2 2006.246.08:01:59.73#ibcon#read 5, iclass 15, count 2 2006.246.08:01:59.73#ibcon#about to read 6, iclass 15, count 2 2006.246.08:01:59.73#ibcon#read 6, iclass 15, count 2 2006.246.08:01:59.73#ibcon#end of sib2, iclass 15, count 2 2006.246.08:01:59.73#ibcon#*after write, iclass 15, count 2 2006.246.08:01:59.73#ibcon#*before return 0, iclass 15, count 2 2006.246.08:01:59.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:01:59.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:01:59.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.08:01:59.73#ibcon#ireg 7 cls_cnt 0 2006.246.08:01:59.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:01:59.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:01:59.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:01:59.85#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:01:59.85#ibcon#first serial, iclass 15, count 0 2006.246.08:01:59.85#ibcon#enter sib2, iclass 15, count 0 2006.246.08:01:59.85#ibcon#flushed, iclass 15, count 0 2006.246.08:01:59.85#ibcon#about to write, iclass 15, count 0 2006.246.08:01:59.85#ibcon#wrote, iclass 15, count 0 2006.246.08:01:59.85#ibcon#about to read 3, iclass 15, count 0 2006.246.08:01:59.87#ibcon#read 3, iclass 15, count 0 2006.246.08:01:59.87#ibcon#about to read 4, iclass 15, count 0 2006.246.08:01:59.87#ibcon#read 4, iclass 15, count 0 2006.246.08:01:59.87#ibcon#about to read 5, iclass 15, count 0 2006.246.08:01:59.87#ibcon#read 5, iclass 15, count 0 2006.246.08:01:59.87#ibcon#about to read 6, iclass 15, count 0 2006.246.08:01:59.87#ibcon#read 6, iclass 15, count 0 2006.246.08:01:59.87#ibcon#end of sib2, iclass 15, count 0 2006.246.08:01:59.87#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:01:59.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:01:59.87#ibcon#[25=USB\r\n] 2006.246.08:01:59.87#ibcon#*before write, iclass 15, count 0 2006.246.08:01:59.87#ibcon#enter sib2, iclass 15, count 0 2006.246.08:01:59.87#ibcon#flushed, iclass 15, count 0 2006.246.08:01:59.87#ibcon#about to write, iclass 15, count 0 2006.246.08:01:59.87#ibcon#wrote, iclass 15, count 0 2006.246.08:01:59.87#ibcon#about to read 3, iclass 15, count 0 2006.246.08:01:59.90#ibcon#read 3, iclass 15, count 0 2006.246.08:01:59.90#ibcon#about to read 4, iclass 15, count 0 2006.246.08:01:59.90#ibcon#read 4, iclass 15, count 0 2006.246.08:01:59.90#ibcon#about to read 5, iclass 15, count 0 2006.246.08:01:59.90#ibcon#read 5, iclass 15, count 0 2006.246.08:01:59.90#ibcon#about to read 6, iclass 15, count 0 2006.246.08:01:59.90#ibcon#read 6, iclass 15, count 0 2006.246.08:01:59.90#ibcon#end of sib2, iclass 15, count 0 2006.246.08:01:59.90#ibcon#*after write, iclass 15, count 0 2006.246.08:01:59.90#ibcon#*before return 0, iclass 15, count 0 2006.246.08:01:59.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:01:59.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:01:59.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:01:59.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:01:59.90$vc4f8/valo=7,832.99 2006.246.08:01:59.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.08:01:59.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.08:01:59.90#ibcon#ireg 17 cls_cnt 0 2006.246.08:01:59.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:01:59.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:01:59.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:01:59.90#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:01:59.90#ibcon#first serial, iclass 17, count 0 2006.246.08:01:59.90#ibcon#enter sib2, iclass 17, count 0 2006.246.08:01:59.90#ibcon#flushed, iclass 17, count 0 2006.246.08:01:59.90#ibcon#about to write, iclass 17, count 0 2006.246.08:01:59.90#ibcon#wrote, iclass 17, count 0 2006.246.08:01:59.90#ibcon#about to read 3, iclass 17, count 0 2006.246.08:01:59.92#ibcon#read 3, iclass 17, count 0 2006.246.08:01:59.92#ibcon#about to read 4, iclass 17, count 0 2006.246.08:01:59.92#ibcon#read 4, iclass 17, count 0 2006.246.08:01:59.92#ibcon#about to read 5, iclass 17, count 0 2006.246.08:01:59.92#ibcon#read 5, iclass 17, count 0 2006.246.08:01:59.92#ibcon#about to read 6, iclass 17, count 0 2006.246.08:01:59.92#ibcon#read 6, iclass 17, count 0 2006.246.08:01:59.92#ibcon#end of sib2, iclass 17, count 0 2006.246.08:01:59.92#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:01:59.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:01:59.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:01:59.92#ibcon#*before write, iclass 17, count 0 2006.246.08:01:59.92#ibcon#enter sib2, iclass 17, count 0 2006.246.08:01:59.92#ibcon#flushed, iclass 17, count 0 2006.246.08:01:59.92#ibcon#about to write, iclass 17, count 0 2006.246.08:01:59.92#ibcon#wrote, iclass 17, count 0 2006.246.08:01:59.92#ibcon#about to read 3, iclass 17, count 0 2006.246.08:01:59.96#ibcon#read 3, iclass 17, count 0 2006.246.08:01:59.96#ibcon#about to read 4, iclass 17, count 0 2006.246.08:01:59.96#ibcon#read 4, iclass 17, count 0 2006.246.08:01:59.96#ibcon#about to read 5, iclass 17, count 0 2006.246.08:01:59.96#ibcon#read 5, iclass 17, count 0 2006.246.08:01:59.96#ibcon#about to read 6, iclass 17, count 0 2006.246.08:01:59.96#ibcon#read 6, iclass 17, count 0 2006.246.08:01:59.96#ibcon#end of sib2, iclass 17, count 0 2006.246.08:01:59.96#ibcon#*after write, iclass 17, count 0 2006.246.08:01:59.96#ibcon#*before return 0, iclass 17, count 0 2006.246.08:01:59.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:01:59.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:01:59.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:01:59.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:01:59.96$vc4f8/va=7,7 2006.246.08:01:59.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.08:01:59.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.08:01:59.96#ibcon#ireg 11 cls_cnt 2 2006.246.08:01:59.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:02:00.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:02:00.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:02:00.02#ibcon#enter wrdev, iclass 19, count 2 2006.246.08:02:00.02#ibcon#first serial, iclass 19, count 2 2006.246.08:02:00.02#ibcon#enter sib2, iclass 19, count 2 2006.246.08:02:00.02#ibcon#flushed, iclass 19, count 2 2006.246.08:02:00.02#ibcon#about to write, iclass 19, count 2 2006.246.08:02:00.02#ibcon#wrote, iclass 19, count 2 2006.246.08:02:00.02#ibcon#about to read 3, iclass 19, count 2 2006.246.08:02:00.04#ibcon#read 3, iclass 19, count 2 2006.246.08:02:00.04#ibcon#about to read 4, iclass 19, count 2 2006.246.08:02:00.04#ibcon#read 4, iclass 19, count 2 2006.246.08:02:00.04#ibcon#about to read 5, iclass 19, count 2 2006.246.08:02:00.04#ibcon#read 5, iclass 19, count 2 2006.246.08:02:00.04#ibcon#about to read 6, iclass 19, count 2 2006.246.08:02:00.04#ibcon#read 6, iclass 19, count 2 2006.246.08:02:00.04#ibcon#end of sib2, iclass 19, count 2 2006.246.08:02:00.04#ibcon#*mode == 0, iclass 19, count 2 2006.246.08:02:00.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.08:02:00.04#ibcon#[25=AT07-07\r\n] 2006.246.08:02:00.04#ibcon#*before write, iclass 19, count 2 2006.246.08:02:00.04#ibcon#enter sib2, iclass 19, count 2 2006.246.08:02:00.04#ibcon#flushed, iclass 19, count 2 2006.246.08:02:00.04#ibcon#about to write, iclass 19, count 2 2006.246.08:02:00.04#ibcon#wrote, iclass 19, count 2 2006.246.08:02:00.04#ibcon#about to read 3, iclass 19, count 2 2006.246.08:02:00.07#ibcon#read 3, iclass 19, count 2 2006.246.08:02:00.07#ibcon#about to read 4, iclass 19, count 2 2006.246.08:02:00.07#ibcon#read 4, iclass 19, count 2 2006.246.08:02:00.07#ibcon#about to read 5, iclass 19, count 2 2006.246.08:02:00.07#ibcon#read 5, iclass 19, count 2 2006.246.08:02:00.07#ibcon#about to read 6, iclass 19, count 2 2006.246.08:02:00.07#ibcon#read 6, iclass 19, count 2 2006.246.08:02:00.07#ibcon#end of sib2, iclass 19, count 2 2006.246.08:02:00.07#ibcon#*after write, iclass 19, count 2 2006.246.08:02:00.07#ibcon#*before return 0, iclass 19, count 2 2006.246.08:02:00.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:02:00.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:02:00.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.08:02:00.07#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:00.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:02:00.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:02:00.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:02:00.19#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:02:00.19#ibcon#first serial, iclass 19, count 0 2006.246.08:02:00.19#ibcon#enter sib2, iclass 19, count 0 2006.246.08:02:00.19#ibcon#flushed, iclass 19, count 0 2006.246.08:02:00.19#ibcon#about to write, iclass 19, count 0 2006.246.08:02:00.19#ibcon#wrote, iclass 19, count 0 2006.246.08:02:00.19#ibcon#about to read 3, iclass 19, count 0 2006.246.08:02:00.21#ibcon#read 3, iclass 19, count 0 2006.246.08:02:00.21#ibcon#about to read 4, iclass 19, count 0 2006.246.08:02:00.21#ibcon#read 4, iclass 19, count 0 2006.246.08:02:00.21#ibcon#about to read 5, iclass 19, count 0 2006.246.08:02:00.21#ibcon#read 5, iclass 19, count 0 2006.246.08:02:00.21#ibcon#about to read 6, iclass 19, count 0 2006.246.08:02:00.21#ibcon#read 6, iclass 19, count 0 2006.246.08:02:00.21#ibcon#end of sib2, iclass 19, count 0 2006.246.08:02:00.21#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:02:00.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:02:00.21#ibcon#[25=USB\r\n] 2006.246.08:02:00.21#ibcon#*before write, iclass 19, count 0 2006.246.08:02:00.21#ibcon#enter sib2, iclass 19, count 0 2006.246.08:02:00.21#ibcon#flushed, iclass 19, count 0 2006.246.08:02:00.21#ibcon#about to write, iclass 19, count 0 2006.246.08:02:00.21#ibcon#wrote, iclass 19, count 0 2006.246.08:02:00.21#ibcon#about to read 3, iclass 19, count 0 2006.246.08:02:00.24#ibcon#read 3, iclass 19, count 0 2006.246.08:02:00.24#ibcon#about to read 4, iclass 19, count 0 2006.246.08:02:00.24#ibcon#read 4, iclass 19, count 0 2006.246.08:02:00.24#ibcon#about to read 5, iclass 19, count 0 2006.246.08:02:00.24#ibcon#read 5, iclass 19, count 0 2006.246.08:02:00.24#ibcon#about to read 6, iclass 19, count 0 2006.246.08:02:00.24#ibcon#read 6, iclass 19, count 0 2006.246.08:02:00.24#ibcon#end of sib2, iclass 19, count 0 2006.246.08:02:00.24#ibcon#*after write, iclass 19, count 0 2006.246.08:02:00.24#ibcon#*before return 0, iclass 19, count 0 2006.246.08:02:00.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:02:00.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:02:00.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:02:00.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:02:00.24$vc4f8/valo=8,852.99 2006.246.08:02:00.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.08:02:00.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.08:02:00.24#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:00.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:02:00.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:02:00.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:02:00.24#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:02:00.24#ibcon#first serial, iclass 21, count 0 2006.246.08:02:00.24#ibcon#enter sib2, iclass 21, count 0 2006.246.08:02:00.24#ibcon#flushed, iclass 21, count 0 2006.246.08:02:00.24#ibcon#about to write, iclass 21, count 0 2006.246.08:02:00.24#ibcon#wrote, iclass 21, count 0 2006.246.08:02:00.24#ibcon#about to read 3, iclass 21, count 0 2006.246.08:02:00.26#ibcon#read 3, iclass 21, count 0 2006.246.08:02:00.26#ibcon#about to read 4, iclass 21, count 0 2006.246.08:02:00.26#ibcon#read 4, iclass 21, count 0 2006.246.08:02:00.26#ibcon#about to read 5, iclass 21, count 0 2006.246.08:02:00.26#ibcon#read 5, iclass 21, count 0 2006.246.08:02:00.26#ibcon#about to read 6, iclass 21, count 0 2006.246.08:02:00.26#ibcon#read 6, iclass 21, count 0 2006.246.08:02:00.26#ibcon#end of sib2, iclass 21, count 0 2006.246.08:02:00.26#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:02:00.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:02:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:02:00.26#ibcon#*before write, iclass 21, count 0 2006.246.08:02:00.26#ibcon#enter sib2, iclass 21, count 0 2006.246.08:02:00.26#ibcon#flushed, iclass 21, count 0 2006.246.08:02:00.26#ibcon#about to write, iclass 21, count 0 2006.246.08:02:00.26#ibcon#wrote, iclass 21, count 0 2006.246.08:02:00.26#ibcon#about to read 3, iclass 21, count 0 2006.246.08:02:00.30#ibcon#read 3, iclass 21, count 0 2006.246.08:02:00.30#ibcon#about to read 4, iclass 21, count 0 2006.246.08:02:00.30#ibcon#read 4, iclass 21, count 0 2006.246.08:02:00.30#ibcon#about to read 5, iclass 21, count 0 2006.246.08:02:00.30#ibcon#read 5, iclass 21, count 0 2006.246.08:02:00.30#ibcon#about to read 6, iclass 21, count 0 2006.246.08:02:00.30#ibcon#read 6, iclass 21, count 0 2006.246.08:02:00.30#ibcon#end of sib2, iclass 21, count 0 2006.246.08:02:00.30#ibcon#*after write, iclass 21, count 0 2006.246.08:02:00.30#ibcon#*before return 0, iclass 21, count 0 2006.246.08:02:00.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:02:00.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:02:00.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:02:00.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:02:00.30$vc4f8/va=8,8 2006.246.08:02:00.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.08:02:00.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.08:02:00.30#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:00.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:02:00.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:02:00.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:02:00.36#ibcon#enter wrdev, iclass 23, count 2 2006.246.08:02:00.36#ibcon#first serial, iclass 23, count 2 2006.246.08:02:00.36#ibcon#enter sib2, iclass 23, count 2 2006.246.08:02:00.36#ibcon#flushed, iclass 23, count 2 2006.246.08:02:00.36#ibcon#about to write, iclass 23, count 2 2006.246.08:02:00.36#ibcon#wrote, iclass 23, count 2 2006.246.08:02:00.36#ibcon#about to read 3, iclass 23, count 2 2006.246.08:02:00.38#ibcon#read 3, iclass 23, count 2 2006.246.08:02:00.38#ibcon#about to read 4, iclass 23, count 2 2006.246.08:02:00.38#ibcon#read 4, iclass 23, count 2 2006.246.08:02:00.38#ibcon#about to read 5, iclass 23, count 2 2006.246.08:02:00.38#ibcon#read 5, iclass 23, count 2 2006.246.08:02:00.38#ibcon#about to read 6, iclass 23, count 2 2006.246.08:02:00.38#ibcon#read 6, iclass 23, count 2 2006.246.08:02:00.38#ibcon#end of sib2, iclass 23, count 2 2006.246.08:02:00.38#ibcon#*mode == 0, iclass 23, count 2 2006.246.08:02:00.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.08:02:00.38#ibcon#[25=AT08-08\r\n] 2006.246.08:02:00.38#ibcon#*before write, iclass 23, count 2 2006.246.08:02:00.38#ibcon#enter sib2, iclass 23, count 2 2006.246.08:02:00.38#ibcon#flushed, iclass 23, count 2 2006.246.08:02:00.38#ibcon#about to write, iclass 23, count 2 2006.246.08:02:00.38#ibcon#wrote, iclass 23, count 2 2006.246.08:02:00.38#ibcon#about to read 3, iclass 23, count 2 2006.246.08:02:00.41#ibcon#read 3, iclass 23, count 2 2006.246.08:02:00.41#ibcon#about to read 4, iclass 23, count 2 2006.246.08:02:00.41#ibcon#read 4, iclass 23, count 2 2006.246.08:02:00.41#ibcon#about to read 5, iclass 23, count 2 2006.246.08:02:00.41#ibcon#read 5, iclass 23, count 2 2006.246.08:02:00.41#ibcon#about to read 6, iclass 23, count 2 2006.246.08:02:00.41#ibcon#read 6, iclass 23, count 2 2006.246.08:02:00.41#ibcon#end of sib2, iclass 23, count 2 2006.246.08:02:00.41#ibcon#*after write, iclass 23, count 2 2006.246.08:02:00.41#ibcon#*before return 0, iclass 23, count 2 2006.246.08:02:00.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:02:00.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:02:00.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.08:02:00.41#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:00.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:02:00.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:02:00.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:02:00.53#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:02:00.53#ibcon#first serial, iclass 23, count 0 2006.246.08:02:00.53#ibcon#enter sib2, iclass 23, count 0 2006.246.08:02:00.53#ibcon#flushed, iclass 23, count 0 2006.246.08:02:00.53#ibcon#about to write, iclass 23, count 0 2006.246.08:02:00.53#ibcon#wrote, iclass 23, count 0 2006.246.08:02:00.53#ibcon#about to read 3, iclass 23, count 0 2006.246.08:02:00.55#ibcon#read 3, iclass 23, count 0 2006.246.08:02:00.55#ibcon#about to read 4, iclass 23, count 0 2006.246.08:02:00.55#ibcon#read 4, iclass 23, count 0 2006.246.08:02:00.55#ibcon#about to read 5, iclass 23, count 0 2006.246.08:02:00.55#ibcon#read 5, iclass 23, count 0 2006.246.08:02:00.55#ibcon#about to read 6, iclass 23, count 0 2006.246.08:02:00.55#ibcon#read 6, iclass 23, count 0 2006.246.08:02:00.55#ibcon#end of sib2, iclass 23, count 0 2006.246.08:02:00.55#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:02:00.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:02:00.55#ibcon#[25=USB\r\n] 2006.246.08:02:00.55#ibcon#*before write, iclass 23, count 0 2006.246.08:02:00.55#ibcon#enter sib2, iclass 23, count 0 2006.246.08:02:00.55#ibcon#flushed, iclass 23, count 0 2006.246.08:02:00.55#ibcon#about to write, iclass 23, count 0 2006.246.08:02:00.55#ibcon#wrote, iclass 23, count 0 2006.246.08:02:00.55#ibcon#about to read 3, iclass 23, count 0 2006.246.08:02:00.58#ibcon#read 3, iclass 23, count 0 2006.246.08:02:00.58#ibcon#about to read 4, iclass 23, count 0 2006.246.08:02:00.58#ibcon#read 4, iclass 23, count 0 2006.246.08:02:00.58#ibcon#about to read 5, iclass 23, count 0 2006.246.08:02:00.58#ibcon#read 5, iclass 23, count 0 2006.246.08:02:00.58#ibcon#about to read 6, iclass 23, count 0 2006.246.08:02:00.58#ibcon#read 6, iclass 23, count 0 2006.246.08:02:00.58#ibcon#end of sib2, iclass 23, count 0 2006.246.08:02:00.58#ibcon#*after write, iclass 23, count 0 2006.246.08:02:00.58#ibcon#*before return 0, iclass 23, count 0 2006.246.08:02:00.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:02:00.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:02:00.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:02:00.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:02:00.58$vc4f8/vblo=1,632.99 2006.246.08:02:00.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.08:02:00.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.08:02:00.58#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:00.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:02:00.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:02:00.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:02:00.58#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:02:00.58#ibcon#first serial, iclass 25, count 0 2006.246.08:02:00.58#ibcon#enter sib2, iclass 25, count 0 2006.246.08:02:00.58#ibcon#flushed, iclass 25, count 0 2006.246.08:02:00.58#ibcon#about to write, iclass 25, count 0 2006.246.08:02:00.58#ibcon#wrote, iclass 25, count 0 2006.246.08:02:00.58#ibcon#about to read 3, iclass 25, count 0 2006.246.08:02:00.60#ibcon#read 3, iclass 25, count 0 2006.246.08:02:00.60#ibcon#about to read 4, iclass 25, count 0 2006.246.08:02:00.60#ibcon#read 4, iclass 25, count 0 2006.246.08:02:00.60#ibcon#about to read 5, iclass 25, count 0 2006.246.08:02:00.60#ibcon#read 5, iclass 25, count 0 2006.246.08:02:00.60#ibcon#about to read 6, iclass 25, count 0 2006.246.08:02:00.60#ibcon#read 6, iclass 25, count 0 2006.246.08:02:00.60#ibcon#end of sib2, iclass 25, count 0 2006.246.08:02:00.60#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:02:00.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:02:00.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:02:00.60#ibcon#*before write, iclass 25, count 0 2006.246.08:02:00.60#ibcon#enter sib2, iclass 25, count 0 2006.246.08:02:00.60#ibcon#flushed, iclass 25, count 0 2006.246.08:02:00.60#ibcon#about to write, iclass 25, count 0 2006.246.08:02:00.60#ibcon#wrote, iclass 25, count 0 2006.246.08:02:00.60#ibcon#about to read 3, iclass 25, count 0 2006.246.08:02:00.64#ibcon#read 3, iclass 25, count 0 2006.246.08:02:00.64#ibcon#about to read 4, iclass 25, count 0 2006.246.08:02:00.64#ibcon#read 4, iclass 25, count 0 2006.246.08:02:00.64#ibcon#about to read 5, iclass 25, count 0 2006.246.08:02:00.64#ibcon#read 5, iclass 25, count 0 2006.246.08:02:00.64#ibcon#about to read 6, iclass 25, count 0 2006.246.08:02:00.64#ibcon#read 6, iclass 25, count 0 2006.246.08:02:00.64#ibcon#end of sib2, iclass 25, count 0 2006.246.08:02:00.64#ibcon#*after write, iclass 25, count 0 2006.246.08:02:00.64#ibcon#*before return 0, iclass 25, count 0 2006.246.08:02:00.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:02:00.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:02:00.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:02:00.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:02:00.64$vc4f8/vb=1,4 2006.246.08:02:00.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.08:02:00.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.08:02:00.64#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:00.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:02:00.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:02:00.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:02:00.64#ibcon#enter wrdev, iclass 27, count 2 2006.246.08:02:00.64#ibcon#first serial, iclass 27, count 2 2006.246.08:02:00.64#ibcon#enter sib2, iclass 27, count 2 2006.246.08:02:00.64#ibcon#flushed, iclass 27, count 2 2006.246.08:02:00.64#ibcon#about to write, iclass 27, count 2 2006.246.08:02:00.64#ibcon#wrote, iclass 27, count 2 2006.246.08:02:00.64#ibcon#about to read 3, iclass 27, count 2 2006.246.08:02:00.66#ibcon#read 3, iclass 27, count 2 2006.246.08:02:00.66#ibcon#about to read 4, iclass 27, count 2 2006.246.08:02:00.66#ibcon#read 4, iclass 27, count 2 2006.246.08:02:00.66#ibcon#about to read 5, iclass 27, count 2 2006.246.08:02:00.66#ibcon#read 5, iclass 27, count 2 2006.246.08:02:00.66#ibcon#about to read 6, iclass 27, count 2 2006.246.08:02:00.66#ibcon#read 6, iclass 27, count 2 2006.246.08:02:00.66#ibcon#end of sib2, iclass 27, count 2 2006.246.08:02:00.66#ibcon#*mode == 0, iclass 27, count 2 2006.246.08:02:00.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.08:02:00.66#ibcon#[27=AT01-04\r\n] 2006.246.08:02:00.66#ibcon#*before write, iclass 27, count 2 2006.246.08:02:00.66#ibcon#enter sib2, iclass 27, count 2 2006.246.08:02:00.66#ibcon#flushed, iclass 27, count 2 2006.246.08:02:00.66#ibcon#about to write, iclass 27, count 2 2006.246.08:02:00.66#ibcon#wrote, iclass 27, count 2 2006.246.08:02:00.66#ibcon#about to read 3, iclass 27, count 2 2006.246.08:02:00.69#ibcon#read 3, iclass 27, count 2 2006.246.08:02:00.69#ibcon#about to read 4, iclass 27, count 2 2006.246.08:02:00.69#ibcon#read 4, iclass 27, count 2 2006.246.08:02:00.69#ibcon#about to read 5, iclass 27, count 2 2006.246.08:02:00.69#ibcon#read 5, iclass 27, count 2 2006.246.08:02:00.69#ibcon#about to read 6, iclass 27, count 2 2006.246.08:02:00.69#ibcon#read 6, iclass 27, count 2 2006.246.08:02:00.69#ibcon#end of sib2, iclass 27, count 2 2006.246.08:02:00.69#ibcon#*after write, iclass 27, count 2 2006.246.08:02:00.69#ibcon#*before return 0, iclass 27, count 2 2006.246.08:02:00.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:02:00.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:02:00.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.08:02:00.69#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:00.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:02:00.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:02:00.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:02:00.81#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:02:00.81#ibcon#first serial, iclass 27, count 0 2006.246.08:02:00.81#ibcon#enter sib2, iclass 27, count 0 2006.246.08:02:00.81#ibcon#flushed, iclass 27, count 0 2006.246.08:02:00.81#ibcon#about to write, iclass 27, count 0 2006.246.08:02:00.81#ibcon#wrote, iclass 27, count 0 2006.246.08:02:00.81#ibcon#about to read 3, iclass 27, count 0 2006.246.08:02:00.83#ibcon#read 3, iclass 27, count 0 2006.246.08:02:00.83#ibcon#about to read 4, iclass 27, count 0 2006.246.08:02:00.83#ibcon#read 4, iclass 27, count 0 2006.246.08:02:00.83#ibcon#about to read 5, iclass 27, count 0 2006.246.08:02:00.83#ibcon#read 5, iclass 27, count 0 2006.246.08:02:00.83#ibcon#about to read 6, iclass 27, count 0 2006.246.08:02:00.83#ibcon#read 6, iclass 27, count 0 2006.246.08:02:00.83#ibcon#end of sib2, iclass 27, count 0 2006.246.08:02:00.83#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:02:00.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:02:00.83#ibcon#[27=USB\r\n] 2006.246.08:02:00.83#ibcon#*before write, iclass 27, count 0 2006.246.08:02:00.83#ibcon#enter sib2, iclass 27, count 0 2006.246.08:02:00.83#ibcon#flushed, iclass 27, count 0 2006.246.08:02:00.83#ibcon#about to write, iclass 27, count 0 2006.246.08:02:00.83#ibcon#wrote, iclass 27, count 0 2006.246.08:02:00.83#ibcon#about to read 3, iclass 27, count 0 2006.246.08:02:00.86#ibcon#read 3, iclass 27, count 0 2006.246.08:02:00.86#ibcon#about to read 4, iclass 27, count 0 2006.246.08:02:00.86#ibcon#read 4, iclass 27, count 0 2006.246.08:02:00.86#ibcon#about to read 5, iclass 27, count 0 2006.246.08:02:00.86#ibcon#read 5, iclass 27, count 0 2006.246.08:02:00.86#ibcon#about to read 6, iclass 27, count 0 2006.246.08:02:00.86#ibcon#read 6, iclass 27, count 0 2006.246.08:02:00.86#ibcon#end of sib2, iclass 27, count 0 2006.246.08:02:00.86#ibcon#*after write, iclass 27, count 0 2006.246.08:02:00.86#ibcon#*before return 0, iclass 27, count 0 2006.246.08:02:00.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:02:00.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:02:00.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:02:00.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:02:00.86$vc4f8/vblo=2,640.99 2006.246.08:02:00.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.08:02:00.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.08:02:00.86#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:00.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:02:00.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:02:00.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:02:00.86#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:02:00.86#ibcon#first serial, iclass 29, count 0 2006.246.08:02:00.86#ibcon#enter sib2, iclass 29, count 0 2006.246.08:02:00.86#ibcon#flushed, iclass 29, count 0 2006.246.08:02:00.86#ibcon#about to write, iclass 29, count 0 2006.246.08:02:00.86#ibcon#wrote, iclass 29, count 0 2006.246.08:02:00.86#ibcon#about to read 3, iclass 29, count 0 2006.246.08:02:00.88#ibcon#read 3, iclass 29, count 0 2006.246.08:02:00.88#ibcon#about to read 4, iclass 29, count 0 2006.246.08:02:00.88#ibcon#read 4, iclass 29, count 0 2006.246.08:02:00.88#ibcon#about to read 5, iclass 29, count 0 2006.246.08:02:00.88#ibcon#read 5, iclass 29, count 0 2006.246.08:02:00.88#ibcon#about to read 6, iclass 29, count 0 2006.246.08:02:00.88#ibcon#read 6, iclass 29, count 0 2006.246.08:02:00.88#ibcon#end of sib2, iclass 29, count 0 2006.246.08:02:00.88#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:02:00.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:02:00.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:02:00.88#ibcon#*before write, iclass 29, count 0 2006.246.08:02:00.88#ibcon#enter sib2, iclass 29, count 0 2006.246.08:02:00.88#ibcon#flushed, iclass 29, count 0 2006.246.08:02:00.88#ibcon#about to write, iclass 29, count 0 2006.246.08:02:00.88#ibcon#wrote, iclass 29, count 0 2006.246.08:02:00.88#ibcon#about to read 3, iclass 29, count 0 2006.246.08:02:00.92#ibcon#read 3, iclass 29, count 0 2006.246.08:02:00.92#ibcon#about to read 4, iclass 29, count 0 2006.246.08:02:00.92#ibcon#read 4, iclass 29, count 0 2006.246.08:02:00.92#ibcon#about to read 5, iclass 29, count 0 2006.246.08:02:00.92#ibcon#read 5, iclass 29, count 0 2006.246.08:02:00.92#ibcon#about to read 6, iclass 29, count 0 2006.246.08:02:00.92#ibcon#read 6, iclass 29, count 0 2006.246.08:02:00.92#ibcon#end of sib2, iclass 29, count 0 2006.246.08:02:00.92#ibcon#*after write, iclass 29, count 0 2006.246.08:02:00.92#ibcon#*before return 0, iclass 29, count 0 2006.246.08:02:00.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:02:00.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:02:00.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:02:00.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:02:00.92$vc4f8/vb=2,4 2006.246.08:02:00.92#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.08:02:00.92#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.08:02:00.92#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:00.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:02:00.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:02:00.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:02:00.98#ibcon#enter wrdev, iclass 31, count 2 2006.246.08:02:00.98#ibcon#first serial, iclass 31, count 2 2006.246.08:02:00.98#ibcon#enter sib2, iclass 31, count 2 2006.246.08:02:00.98#ibcon#flushed, iclass 31, count 2 2006.246.08:02:00.98#ibcon#about to write, iclass 31, count 2 2006.246.08:02:00.98#ibcon#wrote, iclass 31, count 2 2006.246.08:02:00.98#ibcon#about to read 3, iclass 31, count 2 2006.246.08:02:01.00#ibcon#read 3, iclass 31, count 2 2006.246.08:02:01.00#ibcon#about to read 4, iclass 31, count 2 2006.246.08:02:01.00#ibcon#read 4, iclass 31, count 2 2006.246.08:02:01.00#ibcon#about to read 5, iclass 31, count 2 2006.246.08:02:01.00#ibcon#read 5, iclass 31, count 2 2006.246.08:02:01.00#ibcon#about to read 6, iclass 31, count 2 2006.246.08:02:01.00#ibcon#read 6, iclass 31, count 2 2006.246.08:02:01.00#ibcon#end of sib2, iclass 31, count 2 2006.246.08:02:01.00#ibcon#*mode == 0, iclass 31, count 2 2006.246.08:02:01.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.08:02:01.00#ibcon#[27=AT02-04\r\n] 2006.246.08:02:01.00#ibcon#*before write, iclass 31, count 2 2006.246.08:02:01.00#ibcon#enter sib2, iclass 31, count 2 2006.246.08:02:01.00#ibcon#flushed, iclass 31, count 2 2006.246.08:02:01.00#ibcon#about to write, iclass 31, count 2 2006.246.08:02:01.00#ibcon#wrote, iclass 31, count 2 2006.246.08:02:01.00#ibcon#about to read 3, iclass 31, count 2 2006.246.08:02:01.03#ibcon#read 3, iclass 31, count 2 2006.246.08:02:01.03#ibcon#about to read 4, iclass 31, count 2 2006.246.08:02:01.03#ibcon#read 4, iclass 31, count 2 2006.246.08:02:01.03#ibcon#about to read 5, iclass 31, count 2 2006.246.08:02:01.03#ibcon#read 5, iclass 31, count 2 2006.246.08:02:01.03#ibcon#about to read 6, iclass 31, count 2 2006.246.08:02:01.03#ibcon#read 6, iclass 31, count 2 2006.246.08:02:01.03#ibcon#end of sib2, iclass 31, count 2 2006.246.08:02:01.03#ibcon#*after write, iclass 31, count 2 2006.246.08:02:01.03#ibcon#*before return 0, iclass 31, count 2 2006.246.08:02:01.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:02:01.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:02:01.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.08:02:01.03#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:01.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:02:01.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:02:01.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:02:01.15#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:02:01.15#ibcon#first serial, iclass 31, count 0 2006.246.08:02:01.15#ibcon#enter sib2, iclass 31, count 0 2006.246.08:02:01.15#ibcon#flushed, iclass 31, count 0 2006.246.08:02:01.15#ibcon#about to write, iclass 31, count 0 2006.246.08:02:01.15#ibcon#wrote, iclass 31, count 0 2006.246.08:02:01.15#ibcon#about to read 3, iclass 31, count 0 2006.246.08:02:01.17#ibcon#read 3, iclass 31, count 0 2006.246.08:02:01.17#ibcon#about to read 4, iclass 31, count 0 2006.246.08:02:01.17#ibcon#read 4, iclass 31, count 0 2006.246.08:02:01.17#ibcon#about to read 5, iclass 31, count 0 2006.246.08:02:01.17#ibcon#read 5, iclass 31, count 0 2006.246.08:02:01.17#ibcon#about to read 6, iclass 31, count 0 2006.246.08:02:01.17#ibcon#read 6, iclass 31, count 0 2006.246.08:02:01.17#ibcon#end of sib2, iclass 31, count 0 2006.246.08:02:01.17#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:02:01.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:02:01.17#ibcon#[27=USB\r\n] 2006.246.08:02:01.17#ibcon#*before write, iclass 31, count 0 2006.246.08:02:01.17#ibcon#enter sib2, iclass 31, count 0 2006.246.08:02:01.17#ibcon#flushed, iclass 31, count 0 2006.246.08:02:01.17#ibcon#about to write, iclass 31, count 0 2006.246.08:02:01.17#ibcon#wrote, iclass 31, count 0 2006.246.08:02:01.17#ibcon#about to read 3, iclass 31, count 0 2006.246.08:02:01.20#ibcon#read 3, iclass 31, count 0 2006.246.08:02:01.20#ibcon#about to read 4, iclass 31, count 0 2006.246.08:02:01.20#ibcon#read 4, iclass 31, count 0 2006.246.08:02:01.20#ibcon#about to read 5, iclass 31, count 0 2006.246.08:02:01.20#ibcon#read 5, iclass 31, count 0 2006.246.08:02:01.20#ibcon#about to read 6, iclass 31, count 0 2006.246.08:02:01.20#ibcon#read 6, iclass 31, count 0 2006.246.08:02:01.20#ibcon#end of sib2, iclass 31, count 0 2006.246.08:02:01.20#ibcon#*after write, iclass 31, count 0 2006.246.08:02:01.20#ibcon#*before return 0, iclass 31, count 0 2006.246.08:02:01.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:02:01.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:02:01.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:02:01.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:02:01.20$vc4f8/vblo=3,656.99 2006.246.08:02:01.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.08:02:01.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.08:02:01.20#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:01.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:02:01.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:02:01.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:02:01.20#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:02:01.20#ibcon#first serial, iclass 33, count 0 2006.246.08:02:01.20#ibcon#enter sib2, iclass 33, count 0 2006.246.08:02:01.20#ibcon#flushed, iclass 33, count 0 2006.246.08:02:01.20#ibcon#about to write, iclass 33, count 0 2006.246.08:02:01.20#ibcon#wrote, iclass 33, count 0 2006.246.08:02:01.20#ibcon#about to read 3, iclass 33, count 0 2006.246.08:02:01.22#ibcon#read 3, iclass 33, count 0 2006.246.08:02:01.22#ibcon#about to read 4, iclass 33, count 0 2006.246.08:02:01.22#ibcon#read 4, iclass 33, count 0 2006.246.08:02:01.22#ibcon#about to read 5, iclass 33, count 0 2006.246.08:02:01.22#ibcon#read 5, iclass 33, count 0 2006.246.08:02:01.22#ibcon#about to read 6, iclass 33, count 0 2006.246.08:02:01.22#ibcon#read 6, iclass 33, count 0 2006.246.08:02:01.22#ibcon#end of sib2, iclass 33, count 0 2006.246.08:02:01.22#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:02:01.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:02:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:02:01.22#ibcon#*before write, iclass 33, count 0 2006.246.08:02:01.22#ibcon#enter sib2, iclass 33, count 0 2006.246.08:02:01.22#ibcon#flushed, iclass 33, count 0 2006.246.08:02:01.22#ibcon#about to write, iclass 33, count 0 2006.246.08:02:01.22#ibcon#wrote, iclass 33, count 0 2006.246.08:02:01.22#ibcon#about to read 3, iclass 33, count 0 2006.246.08:02:01.26#ibcon#read 3, iclass 33, count 0 2006.246.08:02:01.26#ibcon#about to read 4, iclass 33, count 0 2006.246.08:02:01.26#ibcon#read 4, iclass 33, count 0 2006.246.08:02:01.26#ibcon#about to read 5, iclass 33, count 0 2006.246.08:02:01.26#ibcon#read 5, iclass 33, count 0 2006.246.08:02:01.26#ibcon#about to read 6, iclass 33, count 0 2006.246.08:02:01.26#ibcon#read 6, iclass 33, count 0 2006.246.08:02:01.26#ibcon#end of sib2, iclass 33, count 0 2006.246.08:02:01.26#ibcon#*after write, iclass 33, count 0 2006.246.08:02:01.26#ibcon#*before return 0, iclass 33, count 0 2006.246.08:02:01.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:02:01.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:02:01.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:02:01.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:02:01.26$vc4f8/vb=3,4 2006.246.08:02:01.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.08:02:01.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.08:02:01.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:01.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:02:01.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:02:01.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:02:01.32#ibcon#enter wrdev, iclass 35, count 2 2006.246.08:02:01.32#ibcon#first serial, iclass 35, count 2 2006.246.08:02:01.32#ibcon#enter sib2, iclass 35, count 2 2006.246.08:02:01.32#ibcon#flushed, iclass 35, count 2 2006.246.08:02:01.32#ibcon#about to write, iclass 35, count 2 2006.246.08:02:01.32#ibcon#wrote, iclass 35, count 2 2006.246.08:02:01.32#ibcon#about to read 3, iclass 35, count 2 2006.246.08:02:01.34#ibcon#read 3, iclass 35, count 2 2006.246.08:02:01.34#ibcon#about to read 4, iclass 35, count 2 2006.246.08:02:01.34#ibcon#read 4, iclass 35, count 2 2006.246.08:02:01.34#ibcon#about to read 5, iclass 35, count 2 2006.246.08:02:01.34#ibcon#read 5, iclass 35, count 2 2006.246.08:02:01.34#ibcon#about to read 6, iclass 35, count 2 2006.246.08:02:01.34#ibcon#read 6, iclass 35, count 2 2006.246.08:02:01.34#ibcon#end of sib2, iclass 35, count 2 2006.246.08:02:01.34#ibcon#*mode == 0, iclass 35, count 2 2006.246.08:02:01.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.08:02:01.34#ibcon#[27=AT03-04\r\n] 2006.246.08:02:01.34#ibcon#*before write, iclass 35, count 2 2006.246.08:02:01.34#ibcon#enter sib2, iclass 35, count 2 2006.246.08:02:01.34#ibcon#flushed, iclass 35, count 2 2006.246.08:02:01.34#ibcon#about to write, iclass 35, count 2 2006.246.08:02:01.34#ibcon#wrote, iclass 35, count 2 2006.246.08:02:01.34#ibcon#about to read 3, iclass 35, count 2 2006.246.08:02:01.37#ibcon#read 3, iclass 35, count 2 2006.246.08:02:01.37#ibcon#about to read 4, iclass 35, count 2 2006.246.08:02:01.37#ibcon#read 4, iclass 35, count 2 2006.246.08:02:01.37#ibcon#about to read 5, iclass 35, count 2 2006.246.08:02:01.37#ibcon#read 5, iclass 35, count 2 2006.246.08:02:01.37#ibcon#about to read 6, iclass 35, count 2 2006.246.08:02:01.37#ibcon#read 6, iclass 35, count 2 2006.246.08:02:01.37#ibcon#end of sib2, iclass 35, count 2 2006.246.08:02:01.37#ibcon#*after write, iclass 35, count 2 2006.246.08:02:01.37#ibcon#*before return 0, iclass 35, count 2 2006.246.08:02:01.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:02:01.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:02:01.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.08:02:01.37#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:01.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:02:01.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:02:01.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:02:01.49#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:02:01.49#ibcon#first serial, iclass 35, count 0 2006.246.08:02:01.49#ibcon#enter sib2, iclass 35, count 0 2006.246.08:02:01.49#ibcon#flushed, iclass 35, count 0 2006.246.08:02:01.49#ibcon#about to write, iclass 35, count 0 2006.246.08:02:01.49#ibcon#wrote, iclass 35, count 0 2006.246.08:02:01.49#ibcon#about to read 3, iclass 35, count 0 2006.246.08:02:01.51#ibcon#read 3, iclass 35, count 0 2006.246.08:02:01.51#ibcon#about to read 4, iclass 35, count 0 2006.246.08:02:01.51#ibcon#read 4, iclass 35, count 0 2006.246.08:02:01.51#ibcon#about to read 5, iclass 35, count 0 2006.246.08:02:01.51#ibcon#read 5, iclass 35, count 0 2006.246.08:02:01.51#ibcon#about to read 6, iclass 35, count 0 2006.246.08:02:01.51#ibcon#read 6, iclass 35, count 0 2006.246.08:02:01.51#ibcon#end of sib2, iclass 35, count 0 2006.246.08:02:01.51#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:02:01.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:02:01.51#ibcon#[27=USB\r\n] 2006.246.08:02:01.51#ibcon#*before write, iclass 35, count 0 2006.246.08:02:01.51#ibcon#enter sib2, iclass 35, count 0 2006.246.08:02:01.51#ibcon#flushed, iclass 35, count 0 2006.246.08:02:01.51#ibcon#about to write, iclass 35, count 0 2006.246.08:02:01.51#ibcon#wrote, iclass 35, count 0 2006.246.08:02:01.51#ibcon#about to read 3, iclass 35, count 0 2006.246.08:02:01.54#ibcon#read 3, iclass 35, count 0 2006.246.08:02:01.54#ibcon#about to read 4, iclass 35, count 0 2006.246.08:02:01.54#ibcon#read 4, iclass 35, count 0 2006.246.08:02:01.54#ibcon#about to read 5, iclass 35, count 0 2006.246.08:02:01.54#ibcon#read 5, iclass 35, count 0 2006.246.08:02:01.54#ibcon#about to read 6, iclass 35, count 0 2006.246.08:02:01.54#ibcon#read 6, iclass 35, count 0 2006.246.08:02:01.54#ibcon#end of sib2, iclass 35, count 0 2006.246.08:02:01.54#ibcon#*after write, iclass 35, count 0 2006.246.08:02:01.54#ibcon#*before return 0, iclass 35, count 0 2006.246.08:02:01.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:02:01.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:02:01.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:02:01.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:02:01.54$vc4f8/vblo=4,712.99 2006.246.08:02:01.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.08:02:01.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.08:02:01.54#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:01.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:02:01.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:02:01.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:02:01.54#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:02:01.54#ibcon#first serial, iclass 37, count 0 2006.246.08:02:01.54#ibcon#enter sib2, iclass 37, count 0 2006.246.08:02:01.54#ibcon#flushed, iclass 37, count 0 2006.246.08:02:01.54#ibcon#about to write, iclass 37, count 0 2006.246.08:02:01.54#ibcon#wrote, iclass 37, count 0 2006.246.08:02:01.54#ibcon#about to read 3, iclass 37, count 0 2006.246.08:02:01.56#ibcon#read 3, iclass 37, count 0 2006.246.08:02:01.56#ibcon#about to read 4, iclass 37, count 0 2006.246.08:02:01.56#ibcon#read 4, iclass 37, count 0 2006.246.08:02:01.56#ibcon#about to read 5, iclass 37, count 0 2006.246.08:02:01.56#ibcon#read 5, iclass 37, count 0 2006.246.08:02:01.56#ibcon#about to read 6, iclass 37, count 0 2006.246.08:02:01.56#ibcon#read 6, iclass 37, count 0 2006.246.08:02:01.56#ibcon#end of sib2, iclass 37, count 0 2006.246.08:02:01.56#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:02:01.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:02:01.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:02:01.56#ibcon#*before write, iclass 37, count 0 2006.246.08:02:01.56#ibcon#enter sib2, iclass 37, count 0 2006.246.08:02:01.56#ibcon#flushed, iclass 37, count 0 2006.246.08:02:01.56#ibcon#about to write, iclass 37, count 0 2006.246.08:02:01.56#ibcon#wrote, iclass 37, count 0 2006.246.08:02:01.56#ibcon#about to read 3, iclass 37, count 0 2006.246.08:02:01.60#ibcon#read 3, iclass 37, count 0 2006.246.08:02:01.60#ibcon#about to read 4, iclass 37, count 0 2006.246.08:02:01.60#ibcon#read 4, iclass 37, count 0 2006.246.08:02:01.60#ibcon#about to read 5, iclass 37, count 0 2006.246.08:02:01.60#ibcon#read 5, iclass 37, count 0 2006.246.08:02:01.60#ibcon#about to read 6, iclass 37, count 0 2006.246.08:02:01.60#ibcon#read 6, iclass 37, count 0 2006.246.08:02:01.60#ibcon#end of sib2, iclass 37, count 0 2006.246.08:02:01.60#ibcon#*after write, iclass 37, count 0 2006.246.08:02:01.60#ibcon#*before return 0, iclass 37, count 0 2006.246.08:02:01.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:02:01.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:02:01.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:02:01.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:02:01.60$vc4f8/vb=4,4 2006.246.08:02:01.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.08:02:01.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.08:02:01.60#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:01.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:02:01.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:02:01.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:02:01.66#ibcon#enter wrdev, iclass 39, count 2 2006.246.08:02:01.66#ibcon#first serial, iclass 39, count 2 2006.246.08:02:01.66#ibcon#enter sib2, iclass 39, count 2 2006.246.08:02:01.66#ibcon#flushed, iclass 39, count 2 2006.246.08:02:01.66#ibcon#about to write, iclass 39, count 2 2006.246.08:02:01.66#ibcon#wrote, iclass 39, count 2 2006.246.08:02:01.66#ibcon#about to read 3, iclass 39, count 2 2006.246.08:02:01.68#ibcon#read 3, iclass 39, count 2 2006.246.08:02:01.68#ibcon#about to read 4, iclass 39, count 2 2006.246.08:02:01.68#ibcon#read 4, iclass 39, count 2 2006.246.08:02:01.68#ibcon#about to read 5, iclass 39, count 2 2006.246.08:02:01.68#ibcon#read 5, iclass 39, count 2 2006.246.08:02:01.68#ibcon#about to read 6, iclass 39, count 2 2006.246.08:02:01.68#ibcon#read 6, iclass 39, count 2 2006.246.08:02:01.68#ibcon#end of sib2, iclass 39, count 2 2006.246.08:02:01.68#ibcon#*mode == 0, iclass 39, count 2 2006.246.08:02:01.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.08:02:01.68#ibcon#[27=AT04-04\r\n] 2006.246.08:02:01.68#ibcon#*before write, iclass 39, count 2 2006.246.08:02:01.68#ibcon#enter sib2, iclass 39, count 2 2006.246.08:02:01.68#ibcon#flushed, iclass 39, count 2 2006.246.08:02:01.68#ibcon#about to write, iclass 39, count 2 2006.246.08:02:01.68#ibcon#wrote, iclass 39, count 2 2006.246.08:02:01.68#ibcon#about to read 3, iclass 39, count 2 2006.246.08:02:01.71#ibcon#read 3, iclass 39, count 2 2006.246.08:02:01.71#ibcon#about to read 4, iclass 39, count 2 2006.246.08:02:01.71#ibcon#read 4, iclass 39, count 2 2006.246.08:02:01.71#ibcon#about to read 5, iclass 39, count 2 2006.246.08:02:01.71#ibcon#read 5, iclass 39, count 2 2006.246.08:02:01.71#ibcon#about to read 6, iclass 39, count 2 2006.246.08:02:01.71#ibcon#read 6, iclass 39, count 2 2006.246.08:02:01.71#ibcon#end of sib2, iclass 39, count 2 2006.246.08:02:01.71#ibcon#*after write, iclass 39, count 2 2006.246.08:02:01.71#ibcon#*before return 0, iclass 39, count 2 2006.246.08:02:01.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:02:01.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:02:01.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.08:02:01.71#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:01.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:02:01.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:02:01.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:02:01.83#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:02:01.83#ibcon#first serial, iclass 39, count 0 2006.246.08:02:01.83#ibcon#enter sib2, iclass 39, count 0 2006.246.08:02:01.83#ibcon#flushed, iclass 39, count 0 2006.246.08:02:01.83#ibcon#about to write, iclass 39, count 0 2006.246.08:02:01.83#ibcon#wrote, iclass 39, count 0 2006.246.08:02:01.83#ibcon#about to read 3, iclass 39, count 0 2006.246.08:02:01.85#ibcon#read 3, iclass 39, count 0 2006.246.08:02:01.85#ibcon#about to read 4, iclass 39, count 0 2006.246.08:02:01.85#ibcon#read 4, iclass 39, count 0 2006.246.08:02:01.85#ibcon#about to read 5, iclass 39, count 0 2006.246.08:02:01.85#ibcon#read 5, iclass 39, count 0 2006.246.08:02:01.85#ibcon#about to read 6, iclass 39, count 0 2006.246.08:02:01.85#ibcon#read 6, iclass 39, count 0 2006.246.08:02:01.85#ibcon#end of sib2, iclass 39, count 0 2006.246.08:02:01.85#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:02:01.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:02:01.85#ibcon#[27=USB\r\n] 2006.246.08:02:01.85#ibcon#*before write, iclass 39, count 0 2006.246.08:02:01.85#ibcon#enter sib2, iclass 39, count 0 2006.246.08:02:01.85#ibcon#flushed, iclass 39, count 0 2006.246.08:02:01.85#ibcon#about to write, iclass 39, count 0 2006.246.08:02:01.85#ibcon#wrote, iclass 39, count 0 2006.246.08:02:01.85#ibcon#about to read 3, iclass 39, count 0 2006.246.08:02:01.88#ibcon#read 3, iclass 39, count 0 2006.246.08:02:01.88#ibcon#about to read 4, iclass 39, count 0 2006.246.08:02:01.88#ibcon#read 4, iclass 39, count 0 2006.246.08:02:01.88#ibcon#about to read 5, iclass 39, count 0 2006.246.08:02:01.88#ibcon#read 5, iclass 39, count 0 2006.246.08:02:01.88#ibcon#about to read 6, iclass 39, count 0 2006.246.08:02:01.88#ibcon#read 6, iclass 39, count 0 2006.246.08:02:01.88#ibcon#end of sib2, iclass 39, count 0 2006.246.08:02:01.88#ibcon#*after write, iclass 39, count 0 2006.246.08:02:01.88#ibcon#*before return 0, iclass 39, count 0 2006.246.08:02:01.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:02:01.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:02:01.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:02:01.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:02:01.88$vc4f8/vblo=5,744.99 2006.246.08:02:01.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.08:02:01.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.08:02:01.88#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:01.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:02:01.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:02:01.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:02:01.88#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:02:01.88#ibcon#first serial, iclass 3, count 0 2006.246.08:02:01.88#ibcon#enter sib2, iclass 3, count 0 2006.246.08:02:01.88#ibcon#flushed, iclass 3, count 0 2006.246.08:02:01.88#ibcon#about to write, iclass 3, count 0 2006.246.08:02:01.88#ibcon#wrote, iclass 3, count 0 2006.246.08:02:01.88#ibcon#about to read 3, iclass 3, count 0 2006.246.08:02:01.90#ibcon#read 3, iclass 3, count 0 2006.246.08:02:01.90#ibcon#about to read 4, iclass 3, count 0 2006.246.08:02:01.90#ibcon#read 4, iclass 3, count 0 2006.246.08:02:01.90#ibcon#about to read 5, iclass 3, count 0 2006.246.08:02:01.90#ibcon#read 5, iclass 3, count 0 2006.246.08:02:01.90#ibcon#about to read 6, iclass 3, count 0 2006.246.08:02:01.90#ibcon#read 6, iclass 3, count 0 2006.246.08:02:01.90#ibcon#end of sib2, iclass 3, count 0 2006.246.08:02:01.90#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:02:01.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:02:01.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:02:01.90#ibcon#*before write, iclass 3, count 0 2006.246.08:02:01.90#ibcon#enter sib2, iclass 3, count 0 2006.246.08:02:01.90#ibcon#flushed, iclass 3, count 0 2006.246.08:02:01.90#ibcon#about to write, iclass 3, count 0 2006.246.08:02:01.90#ibcon#wrote, iclass 3, count 0 2006.246.08:02:01.90#ibcon#about to read 3, iclass 3, count 0 2006.246.08:02:01.94#ibcon#read 3, iclass 3, count 0 2006.246.08:02:01.94#ibcon#about to read 4, iclass 3, count 0 2006.246.08:02:01.94#ibcon#read 4, iclass 3, count 0 2006.246.08:02:01.94#ibcon#about to read 5, iclass 3, count 0 2006.246.08:02:01.94#ibcon#read 5, iclass 3, count 0 2006.246.08:02:01.94#ibcon#about to read 6, iclass 3, count 0 2006.246.08:02:01.94#ibcon#read 6, iclass 3, count 0 2006.246.08:02:01.94#ibcon#end of sib2, iclass 3, count 0 2006.246.08:02:01.94#ibcon#*after write, iclass 3, count 0 2006.246.08:02:01.94#ibcon#*before return 0, iclass 3, count 0 2006.246.08:02:01.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:02:01.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:02:01.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:02:01.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:02:01.94$vc4f8/vb=5,3 2006.246.08:02:01.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.08:02:01.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.08:02:01.94#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:01.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:02:02.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:02:02.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:02:02.00#ibcon#enter wrdev, iclass 5, count 2 2006.246.08:02:02.00#ibcon#first serial, iclass 5, count 2 2006.246.08:02:02.00#ibcon#enter sib2, iclass 5, count 2 2006.246.08:02:02.00#ibcon#flushed, iclass 5, count 2 2006.246.08:02:02.00#ibcon#about to write, iclass 5, count 2 2006.246.08:02:02.00#ibcon#wrote, iclass 5, count 2 2006.246.08:02:02.00#ibcon#about to read 3, iclass 5, count 2 2006.246.08:02:02.02#ibcon#read 3, iclass 5, count 2 2006.246.08:02:02.02#ibcon#about to read 4, iclass 5, count 2 2006.246.08:02:02.02#ibcon#read 4, iclass 5, count 2 2006.246.08:02:02.02#ibcon#about to read 5, iclass 5, count 2 2006.246.08:02:02.02#ibcon#read 5, iclass 5, count 2 2006.246.08:02:02.02#ibcon#about to read 6, iclass 5, count 2 2006.246.08:02:02.02#ibcon#read 6, iclass 5, count 2 2006.246.08:02:02.02#ibcon#end of sib2, iclass 5, count 2 2006.246.08:02:02.02#ibcon#*mode == 0, iclass 5, count 2 2006.246.08:02:02.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.08:02:02.02#ibcon#[27=AT05-03\r\n] 2006.246.08:02:02.02#ibcon#*before write, iclass 5, count 2 2006.246.08:02:02.02#ibcon#enter sib2, iclass 5, count 2 2006.246.08:02:02.02#ibcon#flushed, iclass 5, count 2 2006.246.08:02:02.02#ibcon#about to write, iclass 5, count 2 2006.246.08:02:02.02#ibcon#wrote, iclass 5, count 2 2006.246.08:02:02.02#ibcon#about to read 3, iclass 5, count 2 2006.246.08:02:02.05#ibcon#read 3, iclass 5, count 2 2006.246.08:02:02.05#ibcon#about to read 4, iclass 5, count 2 2006.246.08:02:02.05#ibcon#read 4, iclass 5, count 2 2006.246.08:02:02.05#ibcon#about to read 5, iclass 5, count 2 2006.246.08:02:02.05#ibcon#read 5, iclass 5, count 2 2006.246.08:02:02.05#ibcon#about to read 6, iclass 5, count 2 2006.246.08:02:02.05#ibcon#read 6, iclass 5, count 2 2006.246.08:02:02.05#ibcon#end of sib2, iclass 5, count 2 2006.246.08:02:02.05#ibcon#*after write, iclass 5, count 2 2006.246.08:02:02.05#ibcon#*before return 0, iclass 5, count 2 2006.246.08:02:02.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:02:02.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:02:02.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.08:02:02.05#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:02.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:02:02.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:02:02.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:02:02.17#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:02:02.17#ibcon#first serial, iclass 5, count 0 2006.246.08:02:02.17#ibcon#enter sib2, iclass 5, count 0 2006.246.08:02:02.17#ibcon#flushed, iclass 5, count 0 2006.246.08:02:02.17#ibcon#about to write, iclass 5, count 0 2006.246.08:02:02.17#ibcon#wrote, iclass 5, count 0 2006.246.08:02:02.17#ibcon#about to read 3, iclass 5, count 0 2006.246.08:02:02.20#ibcon#read 3, iclass 5, count 0 2006.246.08:02:02.20#ibcon#about to read 4, iclass 5, count 0 2006.246.08:02:02.20#ibcon#read 4, iclass 5, count 0 2006.246.08:02:02.20#ibcon#about to read 5, iclass 5, count 0 2006.246.08:02:02.20#ibcon#read 5, iclass 5, count 0 2006.246.08:02:02.20#ibcon#about to read 6, iclass 5, count 0 2006.246.08:02:02.20#ibcon#read 6, iclass 5, count 0 2006.246.08:02:02.20#ibcon#end of sib2, iclass 5, count 0 2006.246.08:02:02.20#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:02:02.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:02:02.20#ibcon#[27=USB\r\n] 2006.246.08:02:02.20#ibcon#*before write, iclass 5, count 0 2006.246.08:02:02.20#ibcon#enter sib2, iclass 5, count 0 2006.246.08:02:02.20#ibcon#flushed, iclass 5, count 0 2006.246.08:02:02.20#ibcon#about to write, iclass 5, count 0 2006.246.08:02:02.20#ibcon#wrote, iclass 5, count 0 2006.246.08:02:02.20#ibcon#about to read 3, iclass 5, count 0 2006.246.08:02:02.23#ibcon#read 3, iclass 5, count 0 2006.246.08:02:02.23#ibcon#about to read 4, iclass 5, count 0 2006.246.08:02:02.23#ibcon#read 4, iclass 5, count 0 2006.246.08:02:02.23#ibcon#about to read 5, iclass 5, count 0 2006.246.08:02:02.23#ibcon#read 5, iclass 5, count 0 2006.246.08:02:02.23#ibcon#about to read 6, iclass 5, count 0 2006.246.08:02:02.23#ibcon#read 6, iclass 5, count 0 2006.246.08:02:02.23#ibcon#end of sib2, iclass 5, count 0 2006.246.08:02:02.23#ibcon#*after write, iclass 5, count 0 2006.246.08:02:02.23#ibcon#*before return 0, iclass 5, count 0 2006.246.08:02:02.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:02:02.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:02:02.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:02:02.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:02:02.23$vc4f8/vblo=6,752.99 2006.246.08:02:02.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.08:02:02.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.08:02:02.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:02:02.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:02:02.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:02:02.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:02:02.23#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:02:02.23#ibcon#first serial, iclass 7, count 0 2006.246.08:02:02.23#ibcon#enter sib2, iclass 7, count 0 2006.246.08:02:02.23#ibcon#flushed, iclass 7, count 0 2006.246.08:02:02.23#ibcon#about to write, iclass 7, count 0 2006.246.08:02:02.23#ibcon#wrote, iclass 7, count 0 2006.246.08:02:02.23#ibcon#about to read 3, iclass 7, count 0 2006.246.08:02:02.25#ibcon#read 3, iclass 7, count 0 2006.246.08:02:02.25#ibcon#about to read 4, iclass 7, count 0 2006.246.08:02:02.25#ibcon#read 4, iclass 7, count 0 2006.246.08:02:02.25#ibcon#about to read 5, iclass 7, count 0 2006.246.08:02:02.25#ibcon#read 5, iclass 7, count 0 2006.246.08:02:02.25#ibcon#about to read 6, iclass 7, count 0 2006.246.08:02:02.25#ibcon#read 6, iclass 7, count 0 2006.246.08:02:02.25#ibcon#end of sib2, iclass 7, count 0 2006.246.08:02:02.25#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:02:02.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:02:02.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:02:02.25#ibcon#*before write, iclass 7, count 0 2006.246.08:02:02.25#ibcon#enter sib2, iclass 7, count 0 2006.246.08:02:02.25#ibcon#flushed, iclass 7, count 0 2006.246.08:02:02.25#ibcon#about to write, iclass 7, count 0 2006.246.08:02:02.25#ibcon#wrote, iclass 7, count 0 2006.246.08:02:02.25#ibcon#about to read 3, iclass 7, count 0 2006.246.08:02:02.29#ibcon#read 3, iclass 7, count 0 2006.246.08:02:02.29#ibcon#about to read 4, iclass 7, count 0 2006.246.08:02:02.29#ibcon#read 4, iclass 7, count 0 2006.246.08:02:02.29#ibcon#about to read 5, iclass 7, count 0 2006.246.08:02:02.29#ibcon#read 5, iclass 7, count 0 2006.246.08:02:02.29#ibcon#about to read 6, iclass 7, count 0 2006.246.08:02:02.29#ibcon#read 6, iclass 7, count 0 2006.246.08:02:02.29#ibcon#end of sib2, iclass 7, count 0 2006.246.08:02:02.29#ibcon#*after write, iclass 7, count 0 2006.246.08:02:02.29#ibcon#*before return 0, iclass 7, count 0 2006.246.08:02:02.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:02:02.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:02:02.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:02:02.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:02:02.29$vc4f8/vb=6,3 2006.246.08:02:02.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.08:02:02.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.08:02:02.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:02:02.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:02:02.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:02:02.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:02:02.35#ibcon#enter wrdev, iclass 11, count 2 2006.246.08:02:02.35#ibcon#first serial, iclass 11, count 2 2006.246.08:02:02.35#ibcon#enter sib2, iclass 11, count 2 2006.246.08:02:02.35#ibcon#flushed, iclass 11, count 2 2006.246.08:02:02.35#ibcon#about to write, iclass 11, count 2 2006.246.08:02:02.35#ibcon#wrote, iclass 11, count 2 2006.246.08:02:02.35#ibcon#about to read 3, iclass 11, count 2 2006.246.08:02:02.37#ibcon#read 3, iclass 11, count 2 2006.246.08:02:02.37#ibcon#about to read 4, iclass 11, count 2 2006.246.08:02:02.37#ibcon#read 4, iclass 11, count 2 2006.246.08:02:02.37#ibcon#about to read 5, iclass 11, count 2 2006.246.08:02:02.37#ibcon#read 5, iclass 11, count 2 2006.246.08:02:02.37#ibcon#about to read 6, iclass 11, count 2 2006.246.08:02:02.37#ibcon#read 6, iclass 11, count 2 2006.246.08:02:02.37#ibcon#end of sib2, iclass 11, count 2 2006.246.08:02:02.37#ibcon#*mode == 0, iclass 11, count 2 2006.246.08:02:02.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.08:02:02.37#ibcon#[27=AT06-03\r\n] 2006.246.08:02:02.37#ibcon#*before write, iclass 11, count 2 2006.246.08:02:02.37#ibcon#enter sib2, iclass 11, count 2 2006.246.08:02:02.37#ibcon#flushed, iclass 11, count 2 2006.246.08:02:02.37#ibcon#about to write, iclass 11, count 2 2006.246.08:02:02.37#ibcon#wrote, iclass 11, count 2 2006.246.08:02:02.37#ibcon#about to read 3, iclass 11, count 2 2006.246.08:02:02.40#ibcon#read 3, iclass 11, count 2 2006.246.08:02:02.40#ibcon#about to read 4, iclass 11, count 2 2006.246.08:02:02.40#ibcon#read 4, iclass 11, count 2 2006.246.08:02:02.40#ibcon#about to read 5, iclass 11, count 2 2006.246.08:02:02.40#ibcon#read 5, iclass 11, count 2 2006.246.08:02:02.40#ibcon#about to read 6, iclass 11, count 2 2006.246.08:02:02.40#ibcon#read 6, iclass 11, count 2 2006.246.08:02:02.40#ibcon#end of sib2, iclass 11, count 2 2006.246.08:02:02.40#ibcon#*after write, iclass 11, count 2 2006.246.08:02:02.40#ibcon#*before return 0, iclass 11, count 2 2006.246.08:02:02.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:02:02.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:02:02.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.08:02:02.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:02:02.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:02:02.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:02:02.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:02:02.52#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:02:02.52#ibcon#first serial, iclass 11, count 0 2006.246.08:02:02.52#ibcon#enter sib2, iclass 11, count 0 2006.246.08:02:02.52#ibcon#flushed, iclass 11, count 0 2006.246.08:02:02.52#ibcon#about to write, iclass 11, count 0 2006.246.08:02:02.52#ibcon#wrote, iclass 11, count 0 2006.246.08:02:02.52#ibcon#about to read 3, iclass 11, count 0 2006.246.08:02:02.54#ibcon#read 3, iclass 11, count 0 2006.246.08:02:02.54#ibcon#about to read 4, iclass 11, count 0 2006.246.08:02:02.54#ibcon#read 4, iclass 11, count 0 2006.246.08:02:02.54#ibcon#about to read 5, iclass 11, count 0 2006.246.08:02:02.54#ibcon#read 5, iclass 11, count 0 2006.246.08:02:02.54#ibcon#about to read 6, iclass 11, count 0 2006.246.08:02:02.54#ibcon#read 6, iclass 11, count 0 2006.246.08:02:02.54#ibcon#end of sib2, iclass 11, count 0 2006.246.08:02:02.54#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:02:02.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:02:02.54#ibcon#[27=USB\r\n] 2006.246.08:02:02.54#ibcon#*before write, iclass 11, count 0 2006.246.08:02:02.54#ibcon#enter sib2, iclass 11, count 0 2006.246.08:02:02.54#ibcon#flushed, iclass 11, count 0 2006.246.08:02:02.54#ibcon#about to write, iclass 11, count 0 2006.246.08:02:02.54#ibcon#wrote, iclass 11, count 0 2006.246.08:02:02.54#ibcon#about to read 3, iclass 11, count 0 2006.246.08:02:02.57#ibcon#read 3, iclass 11, count 0 2006.246.08:02:02.57#ibcon#about to read 4, iclass 11, count 0 2006.246.08:02:02.57#ibcon#read 4, iclass 11, count 0 2006.246.08:02:02.57#ibcon#about to read 5, iclass 11, count 0 2006.246.08:02:02.57#ibcon#read 5, iclass 11, count 0 2006.246.08:02:02.57#ibcon#about to read 6, iclass 11, count 0 2006.246.08:02:02.57#ibcon#read 6, iclass 11, count 0 2006.246.08:02:02.57#ibcon#end of sib2, iclass 11, count 0 2006.246.08:02:02.57#ibcon#*after write, iclass 11, count 0 2006.246.08:02:02.57#ibcon#*before return 0, iclass 11, count 0 2006.246.08:02:02.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:02:02.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:02:02.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:02:02.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:02:02.57$vc4f8/vabw=wide 2006.246.08:02:02.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:02:02.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:02:02.57#ibcon#ireg 8 cls_cnt 0 2006.246.08:02:02.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:02:02.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:02:02.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:02:02.57#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:02:02.57#ibcon#first serial, iclass 13, count 0 2006.246.08:02:02.57#ibcon#enter sib2, iclass 13, count 0 2006.246.08:02:02.57#ibcon#flushed, iclass 13, count 0 2006.246.08:02:02.57#ibcon#about to write, iclass 13, count 0 2006.246.08:02:02.57#ibcon#wrote, iclass 13, count 0 2006.246.08:02:02.57#ibcon#about to read 3, iclass 13, count 0 2006.246.08:02:02.59#ibcon#read 3, iclass 13, count 0 2006.246.08:02:02.59#ibcon#about to read 4, iclass 13, count 0 2006.246.08:02:02.59#ibcon#read 4, iclass 13, count 0 2006.246.08:02:02.59#ibcon#about to read 5, iclass 13, count 0 2006.246.08:02:02.59#ibcon#read 5, iclass 13, count 0 2006.246.08:02:02.59#ibcon#about to read 6, iclass 13, count 0 2006.246.08:02:02.59#ibcon#read 6, iclass 13, count 0 2006.246.08:02:02.59#ibcon#end of sib2, iclass 13, count 0 2006.246.08:02:02.59#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:02:02.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:02:02.59#ibcon#[25=BW32\r\n] 2006.246.08:02:02.59#ibcon#*before write, iclass 13, count 0 2006.246.08:02:02.59#ibcon#enter sib2, iclass 13, count 0 2006.246.08:02:02.59#ibcon#flushed, iclass 13, count 0 2006.246.08:02:02.59#ibcon#about to write, iclass 13, count 0 2006.246.08:02:02.59#ibcon#wrote, iclass 13, count 0 2006.246.08:02:02.59#ibcon#about to read 3, iclass 13, count 0 2006.246.08:02:02.62#ibcon#read 3, iclass 13, count 0 2006.246.08:02:02.62#ibcon#about to read 4, iclass 13, count 0 2006.246.08:02:02.62#ibcon#read 4, iclass 13, count 0 2006.246.08:02:02.62#ibcon#about to read 5, iclass 13, count 0 2006.246.08:02:02.62#ibcon#read 5, iclass 13, count 0 2006.246.08:02:02.62#ibcon#about to read 6, iclass 13, count 0 2006.246.08:02:02.62#ibcon#read 6, iclass 13, count 0 2006.246.08:02:02.62#ibcon#end of sib2, iclass 13, count 0 2006.246.08:02:02.62#ibcon#*after write, iclass 13, count 0 2006.246.08:02:02.62#ibcon#*before return 0, iclass 13, count 0 2006.246.08:02:02.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:02:02.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:02:02.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:02:02.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:02:02.62$vc4f8/vbbw=wide 2006.246.08:02:02.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.08:02:02.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.08:02:02.62#ibcon#ireg 8 cls_cnt 0 2006.246.08:02:02.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:02:02.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:02:02.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:02:02.69#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:02:02.69#ibcon#first serial, iclass 15, count 0 2006.246.08:02:02.69#ibcon#enter sib2, iclass 15, count 0 2006.246.08:02:02.69#ibcon#flushed, iclass 15, count 0 2006.246.08:02:02.69#ibcon#about to write, iclass 15, count 0 2006.246.08:02:02.69#ibcon#wrote, iclass 15, count 0 2006.246.08:02:02.69#ibcon#about to read 3, iclass 15, count 0 2006.246.08:02:02.71#ibcon#read 3, iclass 15, count 0 2006.246.08:02:02.71#ibcon#about to read 4, iclass 15, count 0 2006.246.08:02:02.71#ibcon#read 4, iclass 15, count 0 2006.246.08:02:02.71#ibcon#about to read 5, iclass 15, count 0 2006.246.08:02:02.71#ibcon#read 5, iclass 15, count 0 2006.246.08:02:02.71#ibcon#about to read 6, iclass 15, count 0 2006.246.08:02:02.71#ibcon#read 6, iclass 15, count 0 2006.246.08:02:02.71#ibcon#end of sib2, iclass 15, count 0 2006.246.08:02:02.71#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:02:02.71#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:02:02.71#ibcon#[27=BW32\r\n] 2006.246.08:02:02.71#ibcon#*before write, iclass 15, count 0 2006.246.08:02:02.71#ibcon#enter sib2, iclass 15, count 0 2006.246.08:02:02.71#ibcon#flushed, iclass 15, count 0 2006.246.08:02:02.71#ibcon#about to write, iclass 15, count 0 2006.246.08:02:02.71#ibcon#wrote, iclass 15, count 0 2006.246.08:02:02.71#ibcon#about to read 3, iclass 15, count 0 2006.246.08:02:02.74#ibcon#read 3, iclass 15, count 0 2006.246.08:02:02.74#ibcon#about to read 4, iclass 15, count 0 2006.246.08:02:02.74#ibcon#read 4, iclass 15, count 0 2006.246.08:02:02.74#ibcon#about to read 5, iclass 15, count 0 2006.246.08:02:02.74#ibcon#read 5, iclass 15, count 0 2006.246.08:02:02.74#ibcon#about to read 6, iclass 15, count 0 2006.246.08:02:02.74#ibcon#read 6, iclass 15, count 0 2006.246.08:02:02.74#ibcon#end of sib2, iclass 15, count 0 2006.246.08:02:02.74#ibcon#*after write, iclass 15, count 0 2006.246.08:02:02.74#ibcon#*before return 0, iclass 15, count 0 2006.246.08:02:02.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:02:02.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:02:02.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:02:02.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:02:02.74$4f8m12a/ifd4f 2006.246.08:02:02.74$ifd4f/lo= 2006.246.08:02:02.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:02:02.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:02:02.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:02:02.74$ifd4f/patch= 2006.246.08:02:02.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:02:02.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:02:02.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:02:02.74$4f8m12a/"form=m,16.000,1:2 2006.246.08:02:02.74$4f8m12a/"tpicd 2006.246.08:02:02.74$4f8m12a/echo=off 2006.246.08:02:02.74$4f8m12a/xlog=off 2006.246.08:02:02.74:!2006.246.08:02:30 2006.246.08:02:10.13#trakl#Source acquired 2006.246.08:02:12.13#flagr#flagr/antenna,acquired 2006.246.08:02:30.00:preob 2006.246.08:02:31.13/onsource/TRACKING 2006.246.08:02:31.13:!2006.246.08:02:40 2006.246.08:02:40.00:data_valid=on 2006.246.08:02:40.00:midob 2006.246.08:02:40.13/onsource/TRACKING 2006.246.08:02:40.13/wx/26.57,1005.7,74 2006.246.08:02:40.29/cable/+6.4136E-03 2006.246.08:02:41.38/va/01,08,usb,yes,31,32 2006.246.08:02:41.38/va/02,07,usb,yes,30,32 2006.246.08:02:41.38/va/03,06,usb,yes,32,33 2006.246.08:02:41.38/va/04,07,usb,yes,31,34 2006.246.08:02:41.38/va/05,07,usb,yes,34,36 2006.246.08:02:41.38/va/06,07,usb,yes,29,29 2006.246.08:02:41.38/va/07,07,usb,yes,29,29 2006.246.08:02:41.38/va/08,08,usb,yes,26,25 2006.246.08:02:41.61/valo/01,532.99,yes,locked 2006.246.08:02:41.61/valo/02,572.99,yes,locked 2006.246.08:02:41.61/valo/03,672.99,yes,locked 2006.246.08:02:41.61/valo/04,832.99,yes,locked 2006.246.08:02:41.61/valo/05,652.99,yes,locked 2006.246.08:02:41.61/valo/06,772.99,yes,locked 2006.246.08:02:41.61/valo/07,832.99,yes,locked 2006.246.08:02:41.61/valo/08,852.99,yes,locked 2006.246.08:02:42.70/vb/01,04,usb,yes,30,29 2006.246.08:02:42.70/vb/02,04,usb,yes,32,33 2006.246.08:02:42.70/vb/03,04,usb,yes,28,32 2006.246.08:02:42.70/vb/04,04,usb,yes,29,29 2006.246.08:02:42.70/vb/05,03,usb,yes,34,39 2006.246.08:02:42.70/vb/06,03,usb,yes,35,39 2006.246.08:02:42.70/vb/07,04,usb,yes,31,30 2006.246.08:02:42.70/vb/08,03,usb,yes,35,39 2006.246.08:02:42.93/vblo/01,632.99,yes,locked 2006.246.08:02:42.93/vblo/02,640.99,yes,locked 2006.246.08:02:42.93/vblo/03,656.99,yes,locked 2006.246.08:02:42.93/vblo/04,712.99,yes,locked 2006.246.08:02:42.93/vblo/05,744.99,yes,locked 2006.246.08:02:42.93/vblo/06,752.99,yes,locked 2006.246.08:02:42.93/vblo/07,734.99,yes,locked 2006.246.08:02:42.93/vblo/08,744.99,yes,locked 2006.246.08:02:43.08/vabw/8 2006.246.08:02:43.23/vbbw/8 2006.246.08:02:43.37/xfe/off,on,13.2 2006.246.08:02:43.74/ifatt/23,28,28,28 2006.246.08:02:44.07/fmout-gps/S +4.39E-07 2006.246.08:02:44.11:!2006.246.08:03:40 2006.246.08:03:40.00:data_valid=off 2006.246.08:03:40.00:postob 2006.246.08:03:40.09/cable/+6.4147E-03 2006.246.08:03:40.09/wx/26.55,1005.7,75 2006.246.08:03:41.07/fmout-gps/S +4.41E-07 2006.246.08:03:41.07:scan_name=246-0804,k06246,60 2006.246.08:03:41.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.246.08:03:41.14#flagr#flagr/antenna,new-source 2006.246.08:03:42.14:checkk5 2006.246.08:03:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:03:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:03:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:03:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:03:44.04/chk_obsdata//k5ts1/T2460802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:03:44.40/chk_obsdata//k5ts2/T2460802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:03:44.77/chk_obsdata//k5ts3/T2460802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:03:45.15/chk_obsdata//k5ts4/T2460802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:03:45.83/k5log//k5ts1_log_newline 2006.246.08:03:46.53/k5log//k5ts2_log_newline 2006.246.08:03:47.21/k5log//k5ts3_log_newline 2006.246.08:03:47.90/k5log//k5ts4_log_newline 2006.246.08:03:47.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:03:47.93:4f8m12a=2 2006.246.08:03:47.93$4f8m12a/echo=on 2006.246.08:03:47.93$4f8m12a/pcalon 2006.246.08:03:47.93$pcalon/"no phase cal control is implemented here 2006.246.08:03:47.93$4f8m12a/"tpicd=stop 2006.246.08:03:47.93$4f8m12a/vc4f8 2006.246.08:03:47.93$vc4f8/valo=1,532.99 2006.246.08:03:47.94#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.08:03:47.94#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.08:03:47.94#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:47.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:47.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:47.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:47.94#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:03:47.94#ibcon#first serial, iclass 22, count 0 2006.246.08:03:47.94#ibcon#enter sib2, iclass 22, count 0 2006.246.08:03:47.94#ibcon#flushed, iclass 22, count 0 2006.246.08:03:47.94#ibcon#about to write, iclass 22, count 0 2006.246.08:03:47.94#ibcon#wrote, iclass 22, count 0 2006.246.08:03:47.94#ibcon#about to read 3, iclass 22, count 0 2006.246.08:03:47.97#ibcon#read 3, iclass 22, count 0 2006.246.08:03:47.97#ibcon#about to read 4, iclass 22, count 0 2006.246.08:03:47.97#ibcon#read 4, iclass 22, count 0 2006.246.08:03:47.97#ibcon#about to read 5, iclass 22, count 0 2006.246.08:03:47.97#ibcon#read 5, iclass 22, count 0 2006.246.08:03:47.97#ibcon#about to read 6, iclass 22, count 0 2006.246.08:03:47.97#ibcon#read 6, iclass 22, count 0 2006.246.08:03:47.97#ibcon#end of sib2, iclass 22, count 0 2006.246.08:03:47.97#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:03:47.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:03:47.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:03:47.97#ibcon#*before write, iclass 22, count 0 2006.246.08:03:47.97#ibcon#enter sib2, iclass 22, count 0 2006.246.08:03:47.97#ibcon#flushed, iclass 22, count 0 2006.246.08:03:47.97#ibcon#about to write, iclass 22, count 0 2006.246.08:03:47.97#ibcon#wrote, iclass 22, count 0 2006.246.08:03:47.97#ibcon#about to read 3, iclass 22, count 0 2006.246.08:03:48.02#ibcon#read 3, iclass 22, count 0 2006.246.08:03:48.02#ibcon#about to read 4, iclass 22, count 0 2006.246.08:03:48.02#ibcon#read 4, iclass 22, count 0 2006.246.08:03:48.02#ibcon#about to read 5, iclass 22, count 0 2006.246.08:03:48.02#ibcon#read 5, iclass 22, count 0 2006.246.08:03:48.02#ibcon#about to read 6, iclass 22, count 0 2006.246.08:03:48.02#ibcon#read 6, iclass 22, count 0 2006.246.08:03:48.02#ibcon#end of sib2, iclass 22, count 0 2006.246.08:03:48.02#ibcon#*after write, iclass 22, count 0 2006.246.08:03:48.02#ibcon#*before return 0, iclass 22, count 0 2006.246.08:03:48.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:48.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:48.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:03:48.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:03:48.02$vc4f8/va=1,8 2006.246.08:03:48.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.08:03:48.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.08:03:48.02#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:48.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:48.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:48.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:48.02#ibcon#enter wrdev, iclass 24, count 2 2006.246.08:03:48.02#ibcon#first serial, iclass 24, count 2 2006.246.08:03:48.02#ibcon#enter sib2, iclass 24, count 2 2006.246.08:03:48.02#ibcon#flushed, iclass 24, count 2 2006.246.08:03:48.02#ibcon#about to write, iclass 24, count 2 2006.246.08:03:48.02#ibcon#wrote, iclass 24, count 2 2006.246.08:03:48.02#ibcon#about to read 3, iclass 24, count 2 2006.246.08:03:48.04#ibcon#read 3, iclass 24, count 2 2006.246.08:03:48.04#ibcon#about to read 4, iclass 24, count 2 2006.246.08:03:48.04#ibcon#read 4, iclass 24, count 2 2006.246.08:03:48.04#ibcon#about to read 5, iclass 24, count 2 2006.246.08:03:48.04#ibcon#read 5, iclass 24, count 2 2006.246.08:03:48.04#ibcon#about to read 6, iclass 24, count 2 2006.246.08:03:48.04#ibcon#read 6, iclass 24, count 2 2006.246.08:03:48.04#ibcon#end of sib2, iclass 24, count 2 2006.246.08:03:48.04#ibcon#*mode == 0, iclass 24, count 2 2006.246.08:03:48.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.08:03:48.04#ibcon#[25=AT01-08\r\n] 2006.246.08:03:48.04#ibcon#*before write, iclass 24, count 2 2006.246.08:03:48.04#ibcon#enter sib2, iclass 24, count 2 2006.246.08:03:48.04#ibcon#flushed, iclass 24, count 2 2006.246.08:03:48.04#ibcon#about to write, iclass 24, count 2 2006.246.08:03:48.04#ibcon#wrote, iclass 24, count 2 2006.246.08:03:48.04#ibcon#about to read 3, iclass 24, count 2 2006.246.08:03:48.07#ibcon#read 3, iclass 24, count 2 2006.246.08:03:48.07#ibcon#about to read 4, iclass 24, count 2 2006.246.08:03:48.07#ibcon#read 4, iclass 24, count 2 2006.246.08:03:48.07#ibcon#about to read 5, iclass 24, count 2 2006.246.08:03:48.07#ibcon#read 5, iclass 24, count 2 2006.246.08:03:48.07#ibcon#about to read 6, iclass 24, count 2 2006.246.08:03:48.07#ibcon#read 6, iclass 24, count 2 2006.246.08:03:48.07#ibcon#end of sib2, iclass 24, count 2 2006.246.08:03:48.07#ibcon#*after write, iclass 24, count 2 2006.246.08:03:48.07#ibcon#*before return 0, iclass 24, count 2 2006.246.08:03:48.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:48.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:48.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.08:03:48.07#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:48.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:48.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:48.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:48.19#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:03:48.19#ibcon#first serial, iclass 24, count 0 2006.246.08:03:48.19#ibcon#enter sib2, iclass 24, count 0 2006.246.08:03:48.19#ibcon#flushed, iclass 24, count 0 2006.246.08:03:48.19#ibcon#about to write, iclass 24, count 0 2006.246.08:03:48.19#ibcon#wrote, iclass 24, count 0 2006.246.08:03:48.19#ibcon#about to read 3, iclass 24, count 0 2006.246.08:03:48.21#ibcon#read 3, iclass 24, count 0 2006.246.08:03:48.21#ibcon#about to read 4, iclass 24, count 0 2006.246.08:03:48.21#ibcon#read 4, iclass 24, count 0 2006.246.08:03:48.21#ibcon#about to read 5, iclass 24, count 0 2006.246.08:03:48.21#ibcon#read 5, iclass 24, count 0 2006.246.08:03:48.21#ibcon#about to read 6, iclass 24, count 0 2006.246.08:03:48.21#ibcon#read 6, iclass 24, count 0 2006.246.08:03:48.21#ibcon#end of sib2, iclass 24, count 0 2006.246.08:03:48.21#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:03:48.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:03:48.21#ibcon#[25=USB\r\n] 2006.246.08:03:48.21#ibcon#*before write, iclass 24, count 0 2006.246.08:03:48.21#ibcon#enter sib2, iclass 24, count 0 2006.246.08:03:48.21#ibcon#flushed, iclass 24, count 0 2006.246.08:03:48.21#ibcon#about to write, iclass 24, count 0 2006.246.08:03:48.21#ibcon#wrote, iclass 24, count 0 2006.246.08:03:48.21#ibcon#about to read 3, iclass 24, count 0 2006.246.08:03:48.24#ibcon#read 3, iclass 24, count 0 2006.246.08:03:48.24#ibcon#about to read 4, iclass 24, count 0 2006.246.08:03:48.24#ibcon#read 4, iclass 24, count 0 2006.246.08:03:48.24#ibcon#about to read 5, iclass 24, count 0 2006.246.08:03:48.24#ibcon#read 5, iclass 24, count 0 2006.246.08:03:48.24#ibcon#about to read 6, iclass 24, count 0 2006.246.08:03:48.24#ibcon#read 6, iclass 24, count 0 2006.246.08:03:48.24#ibcon#end of sib2, iclass 24, count 0 2006.246.08:03:48.24#ibcon#*after write, iclass 24, count 0 2006.246.08:03:48.24#ibcon#*before return 0, iclass 24, count 0 2006.246.08:03:48.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:48.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:48.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:03:48.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:03:48.24$vc4f8/valo=2,572.99 2006.246.08:03:48.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.08:03:48.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.08:03:48.24#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:48.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:48.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:48.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:48.24#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:03:48.24#ibcon#first serial, iclass 26, count 0 2006.246.08:03:48.24#ibcon#enter sib2, iclass 26, count 0 2006.246.08:03:48.24#ibcon#flushed, iclass 26, count 0 2006.246.08:03:48.24#ibcon#about to write, iclass 26, count 0 2006.246.08:03:48.24#ibcon#wrote, iclass 26, count 0 2006.246.08:03:48.24#ibcon#about to read 3, iclass 26, count 0 2006.246.08:03:48.26#ibcon#read 3, iclass 26, count 0 2006.246.08:03:48.26#ibcon#about to read 4, iclass 26, count 0 2006.246.08:03:48.26#ibcon#read 4, iclass 26, count 0 2006.246.08:03:48.26#ibcon#about to read 5, iclass 26, count 0 2006.246.08:03:48.26#ibcon#read 5, iclass 26, count 0 2006.246.08:03:48.26#ibcon#about to read 6, iclass 26, count 0 2006.246.08:03:48.26#ibcon#read 6, iclass 26, count 0 2006.246.08:03:48.26#ibcon#end of sib2, iclass 26, count 0 2006.246.08:03:48.26#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:03:48.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:03:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:03:48.26#ibcon#*before write, iclass 26, count 0 2006.246.08:03:48.26#ibcon#enter sib2, iclass 26, count 0 2006.246.08:03:48.26#ibcon#flushed, iclass 26, count 0 2006.246.08:03:48.26#ibcon#about to write, iclass 26, count 0 2006.246.08:03:48.26#ibcon#wrote, iclass 26, count 0 2006.246.08:03:48.26#ibcon#about to read 3, iclass 26, count 0 2006.246.08:03:48.31#ibcon#read 3, iclass 26, count 0 2006.246.08:03:48.31#ibcon#about to read 4, iclass 26, count 0 2006.246.08:03:48.31#ibcon#read 4, iclass 26, count 0 2006.246.08:03:48.31#ibcon#about to read 5, iclass 26, count 0 2006.246.08:03:48.31#ibcon#read 5, iclass 26, count 0 2006.246.08:03:48.31#ibcon#about to read 6, iclass 26, count 0 2006.246.08:03:48.31#ibcon#read 6, iclass 26, count 0 2006.246.08:03:48.31#ibcon#end of sib2, iclass 26, count 0 2006.246.08:03:48.31#ibcon#*after write, iclass 26, count 0 2006.246.08:03:48.31#ibcon#*before return 0, iclass 26, count 0 2006.246.08:03:48.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:48.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:48.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:03:48.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:03:48.31$vc4f8/va=2,7 2006.246.08:03:48.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.08:03:48.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.08:03:48.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:48.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:48.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:48.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:48.36#ibcon#enter wrdev, iclass 28, count 2 2006.246.08:03:48.36#ibcon#first serial, iclass 28, count 2 2006.246.08:03:48.36#ibcon#enter sib2, iclass 28, count 2 2006.246.08:03:48.36#ibcon#flushed, iclass 28, count 2 2006.246.08:03:48.36#ibcon#about to write, iclass 28, count 2 2006.246.08:03:48.36#ibcon#wrote, iclass 28, count 2 2006.246.08:03:48.36#ibcon#about to read 3, iclass 28, count 2 2006.246.08:03:48.38#ibcon#read 3, iclass 28, count 2 2006.246.08:03:48.38#ibcon#about to read 4, iclass 28, count 2 2006.246.08:03:48.38#ibcon#read 4, iclass 28, count 2 2006.246.08:03:48.38#ibcon#about to read 5, iclass 28, count 2 2006.246.08:03:48.38#ibcon#read 5, iclass 28, count 2 2006.246.08:03:48.38#ibcon#about to read 6, iclass 28, count 2 2006.246.08:03:48.38#ibcon#read 6, iclass 28, count 2 2006.246.08:03:48.38#ibcon#end of sib2, iclass 28, count 2 2006.246.08:03:48.38#ibcon#*mode == 0, iclass 28, count 2 2006.246.08:03:48.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.08:03:48.38#ibcon#[25=AT02-07\r\n] 2006.246.08:03:48.38#ibcon#*before write, iclass 28, count 2 2006.246.08:03:48.38#ibcon#enter sib2, iclass 28, count 2 2006.246.08:03:48.38#ibcon#flushed, iclass 28, count 2 2006.246.08:03:48.38#ibcon#about to write, iclass 28, count 2 2006.246.08:03:48.38#ibcon#wrote, iclass 28, count 2 2006.246.08:03:48.38#ibcon#about to read 3, iclass 28, count 2 2006.246.08:03:48.41#ibcon#read 3, iclass 28, count 2 2006.246.08:03:48.41#ibcon#about to read 4, iclass 28, count 2 2006.246.08:03:48.41#ibcon#read 4, iclass 28, count 2 2006.246.08:03:48.41#ibcon#about to read 5, iclass 28, count 2 2006.246.08:03:48.41#ibcon#read 5, iclass 28, count 2 2006.246.08:03:48.41#ibcon#about to read 6, iclass 28, count 2 2006.246.08:03:48.41#ibcon#read 6, iclass 28, count 2 2006.246.08:03:48.41#ibcon#end of sib2, iclass 28, count 2 2006.246.08:03:48.41#ibcon#*after write, iclass 28, count 2 2006.246.08:03:48.41#ibcon#*before return 0, iclass 28, count 2 2006.246.08:03:48.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:48.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:48.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.08:03:48.41#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:48.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:48.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:48.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:48.53#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:03:48.53#ibcon#first serial, iclass 28, count 0 2006.246.08:03:48.53#ibcon#enter sib2, iclass 28, count 0 2006.246.08:03:48.53#ibcon#flushed, iclass 28, count 0 2006.246.08:03:48.53#ibcon#about to write, iclass 28, count 0 2006.246.08:03:48.53#ibcon#wrote, iclass 28, count 0 2006.246.08:03:48.53#ibcon#about to read 3, iclass 28, count 0 2006.246.08:03:48.55#ibcon#read 3, iclass 28, count 0 2006.246.08:03:48.55#ibcon#about to read 4, iclass 28, count 0 2006.246.08:03:48.55#ibcon#read 4, iclass 28, count 0 2006.246.08:03:48.55#ibcon#about to read 5, iclass 28, count 0 2006.246.08:03:48.55#ibcon#read 5, iclass 28, count 0 2006.246.08:03:48.55#ibcon#about to read 6, iclass 28, count 0 2006.246.08:03:48.55#ibcon#read 6, iclass 28, count 0 2006.246.08:03:48.55#ibcon#end of sib2, iclass 28, count 0 2006.246.08:03:48.55#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:03:48.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:03:48.55#ibcon#[25=USB\r\n] 2006.246.08:03:48.55#ibcon#*before write, iclass 28, count 0 2006.246.08:03:48.55#ibcon#enter sib2, iclass 28, count 0 2006.246.08:03:48.55#ibcon#flushed, iclass 28, count 0 2006.246.08:03:48.55#ibcon#about to write, iclass 28, count 0 2006.246.08:03:48.55#ibcon#wrote, iclass 28, count 0 2006.246.08:03:48.55#ibcon#about to read 3, iclass 28, count 0 2006.246.08:03:48.58#ibcon#read 3, iclass 28, count 0 2006.246.08:03:48.58#ibcon#about to read 4, iclass 28, count 0 2006.246.08:03:48.58#ibcon#read 4, iclass 28, count 0 2006.246.08:03:48.58#ibcon#about to read 5, iclass 28, count 0 2006.246.08:03:48.58#ibcon#read 5, iclass 28, count 0 2006.246.08:03:48.58#ibcon#about to read 6, iclass 28, count 0 2006.246.08:03:48.58#ibcon#read 6, iclass 28, count 0 2006.246.08:03:48.58#ibcon#end of sib2, iclass 28, count 0 2006.246.08:03:48.58#ibcon#*after write, iclass 28, count 0 2006.246.08:03:48.58#ibcon#*before return 0, iclass 28, count 0 2006.246.08:03:48.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:48.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:48.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:03:48.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:03:48.58$vc4f8/valo=3,672.99 2006.246.08:03:48.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.08:03:48.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.08:03:48.58#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:48.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:48.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:48.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:48.58#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:03:48.58#ibcon#first serial, iclass 30, count 0 2006.246.08:03:48.58#ibcon#enter sib2, iclass 30, count 0 2006.246.08:03:48.58#ibcon#flushed, iclass 30, count 0 2006.246.08:03:48.58#ibcon#about to write, iclass 30, count 0 2006.246.08:03:48.58#ibcon#wrote, iclass 30, count 0 2006.246.08:03:48.58#ibcon#about to read 3, iclass 30, count 0 2006.246.08:03:48.60#ibcon#read 3, iclass 30, count 0 2006.246.08:03:48.60#ibcon#about to read 4, iclass 30, count 0 2006.246.08:03:48.60#ibcon#read 4, iclass 30, count 0 2006.246.08:03:48.60#ibcon#about to read 5, iclass 30, count 0 2006.246.08:03:48.60#ibcon#read 5, iclass 30, count 0 2006.246.08:03:48.60#ibcon#about to read 6, iclass 30, count 0 2006.246.08:03:48.60#ibcon#read 6, iclass 30, count 0 2006.246.08:03:48.60#ibcon#end of sib2, iclass 30, count 0 2006.246.08:03:48.60#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:03:48.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:03:48.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:03:48.60#ibcon#*before write, iclass 30, count 0 2006.246.08:03:48.60#ibcon#enter sib2, iclass 30, count 0 2006.246.08:03:48.60#ibcon#flushed, iclass 30, count 0 2006.246.08:03:48.60#ibcon#about to write, iclass 30, count 0 2006.246.08:03:48.60#ibcon#wrote, iclass 30, count 0 2006.246.08:03:48.60#ibcon#about to read 3, iclass 30, count 0 2006.246.08:03:48.65#ibcon#read 3, iclass 30, count 0 2006.246.08:03:48.65#ibcon#about to read 4, iclass 30, count 0 2006.246.08:03:48.65#ibcon#read 4, iclass 30, count 0 2006.246.08:03:48.65#ibcon#about to read 5, iclass 30, count 0 2006.246.08:03:48.65#ibcon#read 5, iclass 30, count 0 2006.246.08:03:48.65#ibcon#about to read 6, iclass 30, count 0 2006.246.08:03:48.65#ibcon#read 6, iclass 30, count 0 2006.246.08:03:48.65#ibcon#end of sib2, iclass 30, count 0 2006.246.08:03:48.65#ibcon#*after write, iclass 30, count 0 2006.246.08:03:48.65#ibcon#*before return 0, iclass 30, count 0 2006.246.08:03:48.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:48.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:48.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:03:48.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:03:48.65$vc4f8/va=3,6 2006.246.08:03:48.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.08:03:48.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.08:03:48.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:48.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:48.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:48.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:48.70#ibcon#enter wrdev, iclass 32, count 2 2006.246.08:03:48.70#ibcon#first serial, iclass 32, count 2 2006.246.08:03:48.70#ibcon#enter sib2, iclass 32, count 2 2006.246.08:03:48.70#ibcon#flushed, iclass 32, count 2 2006.246.08:03:48.70#ibcon#about to write, iclass 32, count 2 2006.246.08:03:48.70#ibcon#wrote, iclass 32, count 2 2006.246.08:03:48.70#ibcon#about to read 3, iclass 32, count 2 2006.246.08:03:48.72#ibcon#read 3, iclass 32, count 2 2006.246.08:03:48.72#ibcon#about to read 4, iclass 32, count 2 2006.246.08:03:48.72#ibcon#read 4, iclass 32, count 2 2006.246.08:03:48.72#ibcon#about to read 5, iclass 32, count 2 2006.246.08:03:48.72#ibcon#read 5, iclass 32, count 2 2006.246.08:03:48.72#ibcon#about to read 6, iclass 32, count 2 2006.246.08:03:48.72#ibcon#read 6, iclass 32, count 2 2006.246.08:03:48.72#ibcon#end of sib2, iclass 32, count 2 2006.246.08:03:48.72#ibcon#*mode == 0, iclass 32, count 2 2006.246.08:03:48.72#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.08:03:48.72#ibcon#[25=AT03-06\r\n] 2006.246.08:03:48.72#ibcon#*before write, iclass 32, count 2 2006.246.08:03:48.72#ibcon#enter sib2, iclass 32, count 2 2006.246.08:03:48.72#ibcon#flushed, iclass 32, count 2 2006.246.08:03:48.72#ibcon#about to write, iclass 32, count 2 2006.246.08:03:48.72#ibcon#wrote, iclass 32, count 2 2006.246.08:03:48.72#ibcon#about to read 3, iclass 32, count 2 2006.246.08:03:48.75#ibcon#read 3, iclass 32, count 2 2006.246.08:03:48.75#ibcon#about to read 4, iclass 32, count 2 2006.246.08:03:48.75#ibcon#read 4, iclass 32, count 2 2006.246.08:03:48.75#ibcon#about to read 5, iclass 32, count 2 2006.246.08:03:48.75#ibcon#read 5, iclass 32, count 2 2006.246.08:03:48.75#ibcon#about to read 6, iclass 32, count 2 2006.246.08:03:48.75#ibcon#read 6, iclass 32, count 2 2006.246.08:03:48.75#ibcon#end of sib2, iclass 32, count 2 2006.246.08:03:48.75#ibcon#*after write, iclass 32, count 2 2006.246.08:03:48.75#ibcon#*before return 0, iclass 32, count 2 2006.246.08:03:48.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:48.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:48.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.08:03:48.75#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:48.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:48.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:48.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:48.87#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:03:48.87#ibcon#first serial, iclass 32, count 0 2006.246.08:03:48.87#ibcon#enter sib2, iclass 32, count 0 2006.246.08:03:48.87#ibcon#flushed, iclass 32, count 0 2006.246.08:03:48.87#ibcon#about to write, iclass 32, count 0 2006.246.08:03:48.87#ibcon#wrote, iclass 32, count 0 2006.246.08:03:48.87#ibcon#about to read 3, iclass 32, count 0 2006.246.08:03:48.89#ibcon#read 3, iclass 32, count 0 2006.246.08:03:48.89#ibcon#about to read 4, iclass 32, count 0 2006.246.08:03:48.89#ibcon#read 4, iclass 32, count 0 2006.246.08:03:48.89#ibcon#about to read 5, iclass 32, count 0 2006.246.08:03:48.89#ibcon#read 5, iclass 32, count 0 2006.246.08:03:48.89#ibcon#about to read 6, iclass 32, count 0 2006.246.08:03:48.89#ibcon#read 6, iclass 32, count 0 2006.246.08:03:48.89#ibcon#end of sib2, iclass 32, count 0 2006.246.08:03:48.89#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:03:48.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:03:48.89#ibcon#[25=USB\r\n] 2006.246.08:03:48.89#ibcon#*before write, iclass 32, count 0 2006.246.08:03:48.89#ibcon#enter sib2, iclass 32, count 0 2006.246.08:03:48.89#ibcon#flushed, iclass 32, count 0 2006.246.08:03:48.89#ibcon#about to write, iclass 32, count 0 2006.246.08:03:48.89#ibcon#wrote, iclass 32, count 0 2006.246.08:03:48.89#ibcon#about to read 3, iclass 32, count 0 2006.246.08:03:48.92#ibcon#read 3, iclass 32, count 0 2006.246.08:03:48.92#ibcon#about to read 4, iclass 32, count 0 2006.246.08:03:48.92#ibcon#read 4, iclass 32, count 0 2006.246.08:03:48.92#ibcon#about to read 5, iclass 32, count 0 2006.246.08:03:48.92#ibcon#read 5, iclass 32, count 0 2006.246.08:03:48.92#ibcon#about to read 6, iclass 32, count 0 2006.246.08:03:48.92#ibcon#read 6, iclass 32, count 0 2006.246.08:03:48.92#ibcon#end of sib2, iclass 32, count 0 2006.246.08:03:48.92#ibcon#*after write, iclass 32, count 0 2006.246.08:03:48.92#ibcon#*before return 0, iclass 32, count 0 2006.246.08:03:48.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:48.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:48.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:03:48.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:03:48.92$vc4f8/valo=4,832.99 2006.246.08:03:48.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.08:03:48.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.08:03:48.92#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:48.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:48.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:48.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:48.92#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:03:48.92#ibcon#first serial, iclass 34, count 0 2006.246.08:03:48.92#ibcon#enter sib2, iclass 34, count 0 2006.246.08:03:48.92#ibcon#flushed, iclass 34, count 0 2006.246.08:03:48.92#ibcon#about to write, iclass 34, count 0 2006.246.08:03:48.92#ibcon#wrote, iclass 34, count 0 2006.246.08:03:48.92#ibcon#about to read 3, iclass 34, count 0 2006.246.08:03:48.94#ibcon#read 3, iclass 34, count 0 2006.246.08:03:48.94#ibcon#about to read 4, iclass 34, count 0 2006.246.08:03:48.94#ibcon#read 4, iclass 34, count 0 2006.246.08:03:48.94#ibcon#about to read 5, iclass 34, count 0 2006.246.08:03:48.94#ibcon#read 5, iclass 34, count 0 2006.246.08:03:48.94#ibcon#about to read 6, iclass 34, count 0 2006.246.08:03:48.94#ibcon#read 6, iclass 34, count 0 2006.246.08:03:48.94#ibcon#end of sib2, iclass 34, count 0 2006.246.08:03:48.94#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:03:48.94#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:03:48.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:03:48.94#ibcon#*before write, iclass 34, count 0 2006.246.08:03:48.94#ibcon#enter sib2, iclass 34, count 0 2006.246.08:03:48.94#ibcon#flushed, iclass 34, count 0 2006.246.08:03:48.94#ibcon#about to write, iclass 34, count 0 2006.246.08:03:48.94#ibcon#wrote, iclass 34, count 0 2006.246.08:03:48.94#ibcon#about to read 3, iclass 34, count 0 2006.246.08:03:48.99#ibcon#read 3, iclass 34, count 0 2006.246.08:03:48.99#ibcon#about to read 4, iclass 34, count 0 2006.246.08:03:48.99#ibcon#read 4, iclass 34, count 0 2006.246.08:03:48.99#ibcon#about to read 5, iclass 34, count 0 2006.246.08:03:48.99#ibcon#read 5, iclass 34, count 0 2006.246.08:03:48.99#ibcon#about to read 6, iclass 34, count 0 2006.246.08:03:48.99#ibcon#read 6, iclass 34, count 0 2006.246.08:03:48.99#ibcon#end of sib2, iclass 34, count 0 2006.246.08:03:48.99#ibcon#*after write, iclass 34, count 0 2006.246.08:03:48.99#ibcon#*before return 0, iclass 34, count 0 2006.246.08:03:48.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:48.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:48.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:03:48.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:03:48.99$vc4f8/va=4,7 2006.246.08:03:48.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.08:03:48.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.08:03:48.99#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:48.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:49.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:49.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:49.04#ibcon#enter wrdev, iclass 36, count 2 2006.246.08:03:49.04#ibcon#first serial, iclass 36, count 2 2006.246.08:03:49.04#ibcon#enter sib2, iclass 36, count 2 2006.246.08:03:49.04#ibcon#flushed, iclass 36, count 2 2006.246.08:03:49.04#ibcon#about to write, iclass 36, count 2 2006.246.08:03:49.04#ibcon#wrote, iclass 36, count 2 2006.246.08:03:49.04#ibcon#about to read 3, iclass 36, count 2 2006.246.08:03:49.06#ibcon#read 3, iclass 36, count 2 2006.246.08:03:49.06#ibcon#about to read 4, iclass 36, count 2 2006.246.08:03:49.06#ibcon#read 4, iclass 36, count 2 2006.246.08:03:49.06#ibcon#about to read 5, iclass 36, count 2 2006.246.08:03:49.06#ibcon#read 5, iclass 36, count 2 2006.246.08:03:49.06#ibcon#about to read 6, iclass 36, count 2 2006.246.08:03:49.06#ibcon#read 6, iclass 36, count 2 2006.246.08:03:49.06#ibcon#end of sib2, iclass 36, count 2 2006.246.08:03:49.06#ibcon#*mode == 0, iclass 36, count 2 2006.246.08:03:49.06#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.08:03:49.06#ibcon#[25=AT04-07\r\n] 2006.246.08:03:49.06#ibcon#*before write, iclass 36, count 2 2006.246.08:03:49.06#ibcon#enter sib2, iclass 36, count 2 2006.246.08:03:49.06#ibcon#flushed, iclass 36, count 2 2006.246.08:03:49.06#ibcon#about to write, iclass 36, count 2 2006.246.08:03:49.06#ibcon#wrote, iclass 36, count 2 2006.246.08:03:49.06#ibcon#about to read 3, iclass 36, count 2 2006.246.08:03:49.09#ibcon#read 3, iclass 36, count 2 2006.246.08:03:49.09#ibcon#about to read 4, iclass 36, count 2 2006.246.08:03:49.09#ibcon#read 4, iclass 36, count 2 2006.246.08:03:49.09#ibcon#about to read 5, iclass 36, count 2 2006.246.08:03:49.09#ibcon#read 5, iclass 36, count 2 2006.246.08:03:49.09#ibcon#about to read 6, iclass 36, count 2 2006.246.08:03:49.09#ibcon#read 6, iclass 36, count 2 2006.246.08:03:49.09#ibcon#end of sib2, iclass 36, count 2 2006.246.08:03:49.09#ibcon#*after write, iclass 36, count 2 2006.246.08:03:49.09#ibcon#*before return 0, iclass 36, count 2 2006.246.08:03:49.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:49.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:49.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.08:03:49.09#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:49.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:49.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:49.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:49.21#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:03:49.21#ibcon#first serial, iclass 36, count 0 2006.246.08:03:49.21#ibcon#enter sib2, iclass 36, count 0 2006.246.08:03:49.21#ibcon#flushed, iclass 36, count 0 2006.246.08:03:49.21#ibcon#about to write, iclass 36, count 0 2006.246.08:03:49.21#ibcon#wrote, iclass 36, count 0 2006.246.08:03:49.21#ibcon#about to read 3, iclass 36, count 0 2006.246.08:03:49.23#ibcon#read 3, iclass 36, count 0 2006.246.08:03:49.23#ibcon#about to read 4, iclass 36, count 0 2006.246.08:03:49.23#ibcon#read 4, iclass 36, count 0 2006.246.08:03:49.23#ibcon#about to read 5, iclass 36, count 0 2006.246.08:03:49.23#ibcon#read 5, iclass 36, count 0 2006.246.08:03:49.23#ibcon#about to read 6, iclass 36, count 0 2006.246.08:03:49.23#ibcon#read 6, iclass 36, count 0 2006.246.08:03:49.23#ibcon#end of sib2, iclass 36, count 0 2006.246.08:03:49.23#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:03:49.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:03:49.23#ibcon#[25=USB\r\n] 2006.246.08:03:49.23#ibcon#*before write, iclass 36, count 0 2006.246.08:03:49.23#ibcon#enter sib2, iclass 36, count 0 2006.246.08:03:49.23#ibcon#flushed, iclass 36, count 0 2006.246.08:03:49.23#ibcon#about to write, iclass 36, count 0 2006.246.08:03:49.23#ibcon#wrote, iclass 36, count 0 2006.246.08:03:49.23#ibcon#about to read 3, iclass 36, count 0 2006.246.08:03:49.26#ibcon#read 3, iclass 36, count 0 2006.246.08:03:49.26#ibcon#about to read 4, iclass 36, count 0 2006.246.08:03:49.26#ibcon#read 4, iclass 36, count 0 2006.246.08:03:49.26#ibcon#about to read 5, iclass 36, count 0 2006.246.08:03:49.26#ibcon#read 5, iclass 36, count 0 2006.246.08:03:49.26#ibcon#about to read 6, iclass 36, count 0 2006.246.08:03:49.26#ibcon#read 6, iclass 36, count 0 2006.246.08:03:49.26#ibcon#end of sib2, iclass 36, count 0 2006.246.08:03:49.26#ibcon#*after write, iclass 36, count 0 2006.246.08:03:49.26#ibcon#*before return 0, iclass 36, count 0 2006.246.08:03:49.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:49.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:49.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:03:49.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:03:49.26$vc4f8/valo=5,652.99 2006.246.08:03:49.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.08:03:49.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.08:03:49.26#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:49.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:49.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:49.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:49.26#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:03:49.26#ibcon#first serial, iclass 38, count 0 2006.246.08:03:49.26#ibcon#enter sib2, iclass 38, count 0 2006.246.08:03:49.26#ibcon#flushed, iclass 38, count 0 2006.246.08:03:49.26#ibcon#about to write, iclass 38, count 0 2006.246.08:03:49.26#ibcon#wrote, iclass 38, count 0 2006.246.08:03:49.26#ibcon#about to read 3, iclass 38, count 0 2006.246.08:03:49.28#ibcon#read 3, iclass 38, count 0 2006.246.08:03:49.28#ibcon#about to read 4, iclass 38, count 0 2006.246.08:03:49.28#ibcon#read 4, iclass 38, count 0 2006.246.08:03:49.28#ibcon#about to read 5, iclass 38, count 0 2006.246.08:03:49.28#ibcon#read 5, iclass 38, count 0 2006.246.08:03:49.28#ibcon#about to read 6, iclass 38, count 0 2006.246.08:03:49.28#ibcon#read 6, iclass 38, count 0 2006.246.08:03:49.28#ibcon#end of sib2, iclass 38, count 0 2006.246.08:03:49.28#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:03:49.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:03:49.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:03:49.28#ibcon#*before write, iclass 38, count 0 2006.246.08:03:49.28#ibcon#enter sib2, iclass 38, count 0 2006.246.08:03:49.28#ibcon#flushed, iclass 38, count 0 2006.246.08:03:49.28#ibcon#about to write, iclass 38, count 0 2006.246.08:03:49.28#ibcon#wrote, iclass 38, count 0 2006.246.08:03:49.28#ibcon#about to read 3, iclass 38, count 0 2006.246.08:03:49.32#ibcon#read 3, iclass 38, count 0 2006.246.08:03:49.32#ibcon#about to read 4, iclass 38, count 0 2006.246.08:03:49.32#ibcon#read 4, iclass 38, count 0 2006.246.08:03:49.32#ibcon#about to read 5, iclass 38, count 0 2006.246.08:03:49.32#ibcon#read 5, iclass 38, count 0 2006.246.08:03:49.32#ibcon#about to read 6, iclass 38, count 0 2006.246.08:03:49.32#ibcon#read 6, iclass 38, count 0 2006.246.08:03:49.32#ibcon#end of sib2, iclass 38, count 0 2006.246.08:03:49.32#ibcon#*after write, iclass 38, count 0 2006.246.08:03:49.32#ibcon#*before return 0, iclass 38, count 0 2006.246.08:03:49.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:49.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:49.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:03:49.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:03:49.32$vc4f8/va=5,7 2006.246.08:03:49.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.08:03:49.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.08:03:49.32#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:49.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:49.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:49.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:49.38#ibcon#enter wrdev, iclass 40, count 2 2006.246.08:03:49.38#ibcon#first serial, iclass 40, count 2 2006.246.08:03:49.38#ibcon#enter sib2, iclass 40, count 2 2006.246.08:03:49.38#ibcon#flushed, iclass 40, count 2 2006.246.08:03:49.38#ibcon#about to write, iclass 40, count 2 2006.246.08:03:49.38#ibcon#wrote, iclass 40, count 2 2006.246.08:03:49.38#ibcon#about to read 3, iclass 40, count 2 2006.246.08:03:49.40#ibcon#read 3, iclass 40, count 2 2006.246.08:03:49.40#ibcon#about to read 4, iclass 40, count 2 2006.246.08:03:49.40#ibcon#read 4, iclass 40, count 2 2006.246.08:03:49.40#ibcon#about to read 5, iclass 40, count 2 2006.246.08:03:49.40#ibcon#read 5, iclass 40, count 2 2006.246.08:03:49.40#ibcon#about to read 6, iclass 40, count 2 2006.246.08:03:49.40#ibcon#read 6, iclass 40, count 2 2006.246.08:03:49.40#ibcon#end of sib2, iclass 40, count 2 2006.246.08:03:49.40#ibcon#*mode == 0, iclass 40, count 2 2006.246.08:03:49.40#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.08:03:49.40#ibcon#[25=AT05-07\r\n] 2006.246.08:03:49.40#ibcon#*before write, iclass 40, count 2 2006.246.08:03:49.40#ibcon#enter sib2, iclass 40, count 2 2006.246.08:03:49.40#ibcon#flushed, iclass 40, count 2 2006.246.08:03:49.40#ibcon#about to write, iclass 40, count 2 2006.246.08:03:49.40#ibcon#wrote, iclass 40, count 2 2006.246.08:03:49.40#ibcon#about to read 3, iclass 40, count 2 2006.246.08:03:49.43#ibcon#read 3, iclass 40, count 2 2006.246.08:03:49.43#ibcon#about to read 4, iclass 40, count 2 2006.246.08:03:49.43#ibcon#read 4, iclass 40, count 2 2006.246.08:03:49.43#ibcon#about to read 5, iclass 40, count 2 2006.246.08:03:49.43#ibcon#read 5, iclass 40, count 2 2006.246.08:03:49.43#ibcon#about to read 6, iclass 40, count 2 2006.246.08:03:49.43#ibcon#read 6, iclass 40, count 2 2006.246.08:03:49.43#ibcon#end of sib2, iclass 40, count 2 2006.246.08:03:49.43#ibcon#*after write, iclass 40, count 2 2006.246.08:03:49.43#ibcon#*before return 0, iclass 40, count 2 2006.246.08:03:49.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:49.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:49.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.08:03:49.43#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:49.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:49.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:49.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:49.55#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:03:49.55#ibcon#first serial, iclass 40, count 0 2006.246.08:03:49.55#ibcon#enter sib2, iclass 40, count 0 2006.246.08:03:49.55#ibcon#flushed, iclass 40, count 0 2006.246.08:03:49.55#ibcon#about to write, iclass 40, count 0 2006.246.08:03:49.55#ibcon#wrote, iclass 40, count 0 2006.246.08:03:49.55#ibcon#about to read 3, iclass 40, count 0 2006.246.08:03:49.57#ibcon#read 3, iclass 40, count 0 2006.246.08:03:49.57#ibcon#about to read 4, iclass 40, count 0 2006.246.08:03:49.57#ibcon#read 4, iclass 40, count 0 2006.246.08:03:49.57#ibcon#about to read 5, iclass 40, count 0 2006.246.08:03:49.57#ibcon#read 5, iclass 40, count 0 2006.246.08:03:49.57#ibcon#about to read 6, iclass 40, count 0 2006.246.08:03:49.57#ibcon#read 6, iclass 40, count 0 2006.246.08:03:49.57#ibcon#end of sib2, iclass 40, count 0 2006.246.08:03:49.57#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:03:49.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:03:49.57#ibcon#[25=USB\r\n] 2006.246.08:03:49.57#ibcon#*before write, iclass 40, count 0 2006.246.08:03:49.57#ibcon#enter sib2, iclass 40, count 0 2006.246.08:03:49.57#ibcon#flushed, iclass 40, count 0 2006.246.08:03:49.57#ibcon#about to write, iclass 40, count 0 2006.246.08:03:49.57#ibcon#wrote, iclass 40, count 0 2006.246.08:03:49.57#ibcon#about to read 3, iclass 40, count 0 2006.246.08:03:49.60#ibcon#read 3, iclass 40, count 0 2006.246.08:03:49.60#ibcon#about to read 4, iclass 40, count 0 2006.246.08:03:49.60#ibcon#read 4, iclass 40, count 0 2006.246.08:03:49.60#ibcon#about to read 5, iclass 40, count 0 2006.246.08:03:49.60#ibcon#read 5, iclass 40, count 0 2006.246.08:03:49.60#ibcon#about to read 6, iclass 40, count 0 2006.246.08:03:49.60#ibcon#read 6, iclass 40, count 0 2006.246.08:03:49.60#ibcon#end of sib2, iclass 40, count 0 2006.246.08:03:49.60#ibcon#*after write, iclass 40, count 0 2006.246.08:03:49.60#ibcon#*before return 0, iclass 40, count 0 2006.246.08:03:49.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:49.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:49.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:03:49.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:03:49.60$vc4f8/valo=6,772.99 2006.246.08:03:49.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.08:03:49.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.08:03:49.60#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:49.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:49.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:49.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:49.60#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:03:49.60#ibcon#first serial, iclass 4, count 0 2006.246.08:03:49.60#ibcon#enter sib2, iclass 4, count 0 2006.246.08:03:49.60#ibcon#flushed, iclass 4, count 0 2006.246.08:03:49.60#ibcon#about to write, iclass 4, count 0 2006.246.08:03:49.60#ibcon#wrote, iclass 4, count 0 2006.246.08:03:49.60#ibcon#about to read 3, iclass 4, count 0 2006.246.08:03:49.62#ibcon#read 3, iclass 4, count 0 2006.246.08:03:49.62#ibcon#about to read 4, iclass 4, count 0 2006.246.08:03:49.62#ibcon#read 4, iclass 4, count 0 2006.246.08:03:49.62#ibcon#about to read 5, iclass 4, count 0 2006.246.08:03:49.62#ibcon#read 5, iclass 4, count 0 2006.246.08:03:49.62#ibcon#about to read 6, iclass 4, count 0 2006.246.08:03:49.62#ibcon#read 6, iclass 4, count 0 2006.246.08:03:49.62#ibcon#end of sib2, iclass 4, count 0 2006.246.08:03:49.62#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:03:49.62#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:03:49.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:03:49.62#ibcon#*before write, iclass 4, count 0 2006.246.08:03:49.62#ibcon#enter sib2, iclass 4, count 0 2006.246.08:03:49.62#ibcon#flushed, iclass 4, count 0 2006.246.08:03:49.62#ibcon#about to write, iclass 4, count 0 2006.246.08:03:49.62#ibcon#wrote, iclass 4, count 0 2006.246.08:03:49.62#ibcon#about to read 3, iclass 4, count 0 2006.246.08:03:49.67#ibcon#read 3, iclass 4, count 0 2006.246.08:03:49.67#ibcon#about to read 4, iclass 4, count 0 2006.246.08:03:49.67#ibcon#read 4, iclass 4, count 0 2006.246.08:03:49.67#ibcon#about to read 5, iclass 4, count 0 2006.246.08:03:49.67#ibcon#read 5, iclass 4, count 0 2006.246.08:03:49.67#ibcon#about to read 6, iclass 4, count 0 2006.246.08:03:49.67#ibcon#read 6, iclass 4, count 0 2006.246.08:03:49.67#ibcon#end of sib2, iclass 4, count 0 2006.246.08:03:49.67#ibcon#*after write, iclass 4, count 0 2006.246.08:03:49.67#ibcon#*before return 0, iclass 4, count 0 2006.246.08:03:49.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:49.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:49.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:03:49.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:03:49.67$vc4f8/va=6,7 2006.246.08:03:49.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.08:03:49.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.08:03:49.67#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:49.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:49.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:49.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:49.72#ibcon#enter wrdev, iclass 6, count 2 2006.246.08:03:49.72#ibcon#first serial, iclass 6, count 2 2006.246.08:03:49.72#ibcon#enter sib2, iclass 6, count 2 2006.246.08:03:49.72#ibcon#flushed, iclass 6, count 2 2006.246.08:03:49.72#ibcon#about to write, iclass 6, count 2 2006.246.08:03:49.72#ibcon#wrote, iclass 6, count 2 2006.246.08:03:49.72#ibcon#about to read 3, iclass 6, count 2 2006.246.08:03:49.74#ibcon#read 3, iclass 6, count 2 2006.246.08:03:49.74#ibcon#about to read 4, iclass 6, count 2 2006.246.08:03:49.74#ibcon#read 4, iclass 6, count 2 2006.246.08:03:49.74#ibcon#about to read 5, iclass 6, count 2 2006.246.08:03:49.74#ibcon#read 5, iclass 6, count 2 2006.246.08:03:49.74#ibcon#about to read 6, iclass 6, count 2 2006.246.08:03:49.74#ibcon#read 6, iclass 6, count 2 2006.246.08:03:49.74#ibcon#end of sib2, iclass 6, count 2 2006.246.08:03:49.74#ibcon#*mode == 0, iclass 6, count 2 2006.246.08:03:49.74#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.08:03:49.74#ibcon#[25=AT06-07\r\n] 2006.246.08:03:49.74#ibcon#*before write, iclass 6, count 2 2006.246.08:03:49.74#ibcon#enter sib2, iclass 6, count 2 2006.246.08:03:49.74#ibcon#flushed, iclass 6, count 2 2006.246.08:03:49.74#ibcon#about to write, iclass 6, count 2 2006.246.08:03:49.74#ibcon#wrote, iclass 6, count 2 2006.246.08:03:49.74#ibcon#about to read 3, iclass 6, count 2 2006.246.08:03:49.77#ibcon#read 3, iclass 6, count 2 2006.246.08:03:49.77#ibcon#about to read 4, iclass 6, count 2 2006.246.08:03:49.77#ibcon#read 4, iclass 6, count 2 2006.246.08:03:49.77#ibcon#about to read 5, iclass 6, count 2 2006.246.08:03:49.77#ibcon#read 5, iclass 6, count 2 2006.246.08:03:49.77#ibcon#about to read 6, iclass 6, count 2 2006.246.08:03:49.77#ibcon#read 6, iclass 6, count 2 2006.246.08:03:49.77#ibcon#end of sib2, iclass 6, count 2 2006.246.08:03:49.77#ibcon#*after write, iclass 6, count 2 2006.246.08:03:49.77#ibcon#*before return 0, iclass 6, count 2 2006.246.08:03:49.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:49.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:49.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.08:03:49.77#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:49.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:49.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:49.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:49.89#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:03:49.89#ibcon#first serial, iclass 6, count 0 2006.246.08:03:49.89#ibcon#enter sib2, iclass 6, count 0 2006.246.08:03:49.89#ibcon#flushed, iclass 6, count 0 2006.246.08:03:49.89#ibcon#about to write, iclass 6, count 0 2006.246.08:03:49.89#ibcon#wrote, iclass 6, count 0 2006.246.08:03:49.89#ibcon#about to read 3, iclass 6, count 0 2006.246.08:03:49.91#ibcon#read 3, iclass 6, count 0 2006.246.08:03:49.91#ibcon#about to read 4, iclass 6, count 0 2006.246.08:03:49.91#ibcon#read 4, iclass 6, count 0 2006.246.08:03:49.91#ibcon#about to read 5, iclass 6, count 0 2006.246.08:03:49.91#ibcon#read 5, iclass 6, count 0 2006.246.08:03:49.91#ibcon#about to read 6, iclass 6, count 0 2006.246.08:03:49.91#ibcon#read 6, iclass 6, count 0 2006.246.08:03:49.91#ibcon#end of sib2, iclass 6, count 0 2006.246.08:03:49.91#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:03:49.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:03:49.91#ibcon#[25=USB\r\n] 2006.246.08:03:49.91#ibcon#*before write, iclass 6, count 0 2006.246.08:03:49.91#ibcon#enter sib2, iclass 6, count 0 2006.246.08:03:49.91#ibcon#flushed, iclass 6, count 0 2006.246.08:03:49.91#ibcon#about to write, iclass 6, count 0 2006.246.08:03:49.91#ibcon#wrote, iclass 6, count 0 2006.246.08:03:49.91#ibcon#about to read 3, iclass 6, count 0 2006.246.08:03:49.94#ibcon#read 3, iclass 6, count 0 2006.246.08:03:49.94#ibcon#about to read 4, iclass 6, count 0 2006.246.08:03:49.94#ibcon#read 4, iclass 6, count 0 2006.246.08:03:49.94#ibcon#about to read 5, iclass 6, count 0 2006.246.08:03:49.94#ibcon#read 5, iclass 6, count 0 2006.246.08:03:49.94#ibcon#about to read 6, iclass 6, count 0 2006.246.08:03:49.94#ibcon#read 6, iclass 6, count 0 2006.246.08:03:49.94#ibcon#end of sib2, iclass 6, count 0 2006.246.08:03:49.94#ibcon#*after write, iclass 6, count 0 2006.246.08:03:49.94#ibcon#*before return 0, iclass 6, count 0 2006.246.08:03:49.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:49.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:49.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:03:49.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:03:49.94$vc4f8/valo=7,832.99 2006.246.08:03:49.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.08:03:49.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.08:03:49.94#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:49.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:49.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:49.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:49.94#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:03:49.94#ibcon#first serial, iclass 10, count 0 2006.246.08:03:49.94#ibcon#enter sib2, iclass 10, count 0 2006.246.08:03:49.94#ibcon#flushed, iclass 10, count 0 2006.246.08:03:49.94#ibcon#about to write, iclass 10, count 0 2006.246.08:03:49.94#ibcon#wrote, iclass 10, count 0 2006.246.08:03:49.94#ibcon#about to read 3, iclass 10, count 0 2006.246.08:03:49.96#ibcon#read 3, iclass 10, count 0 2006.246.08:03:49.96#ibcon#about to read 4, iclass 10, count 0 2006.246.08:03:49.96#ibcon#read 4, iclass 10, count 0 2006.246.08:03:49.96#ibcon#about to read 5, iclass 10, count 0 2006.246.08:03:49.96#ibcon#read 5, iclass 10, count 0 2006.246.08:03:49.96#ibcon#about to read 6, iclass 10, count 0 2006.246.08:03:49.96#ibcon#read 6, iclass 10, count 0 2006.246.08:03:49.96#ibcon#end of sib2, iclass 10, count 0 2006.246.08:03:49.96#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:03:49.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:03:49.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:03:49.96#ibcon#*before write, iclass 10, count 0 2006.246.08:03:49.96#ibcon#enter sib2, iclass 10, count 0 2006.246.08:03:49.96#ibcon#flushed, iclass 10, count 0 2006.246.08:03:49.96#ibcon#about to write, iclass 10, count 0 2006.246.08:03:49.96#ibcon#wrote, iclass 10, count 0 2006.246.08:03:49.96#ibcon#about to read 3, iclass 10, count 0 2006.246.08:03:50.00#ibcon#read 3, iclass 10, count 0 2006.246.08:03:50.00#ibcon#about to read 4, iclass 10, count 0 2006.246.08:03:50.00#ibcon#read 4, iclass 10, count 0 2006.246.08:03:50.00#ibcon#about to read 5, iclass 10, count 0 2006.246.08:03:50.00#ibcon#read 5, iclass 10, count 0 2006.246.08:03:50.00#ibcon#about to read 6, iclass 10, count 0 2006.246.08:03:50.00#ibcon#read 6, iclass 10, count 0 2006.246.08:03:50.00#ibcon#end of sib2, iclass 10, count 0 2006.246.08:03:50.00#ibcon#*after write, iclass 10, count 0 2006.246.08:03:50.00#ibcon#*before return 0, iclass 10, count 0 2006.246.08:03:50.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:50.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:50.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:03:50.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:03:50.00$vc4f8/va=7,7 2006.246.08:03:50.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.08:03:50.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.08:03:50.00#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:50.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:03:50.05#abcon#<5=/04 3.4 6.5 26.54 741005.8\r\n> 2006.246.08:03:50.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:03:50.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:03:50.06#ibcon#enter wrdev, iclass 12, count 2 2006.246.08:03:50.06#ibcon#first serial, iclass 12, count 2 2006.246.08:03:50.06#ibcon#enter sib2, iclass 12, count 2 2006.246.08:03:50.06#ibcon#flushed, iclass 12, count 2 2006.246.08:03:50.06#ibcon#about to write, iclass 12, count 2 2006.246.08:03:50.06#ibcon#wrote, iclass 12, count 2 2006.246.08:03:50.06#ibcon#about to read 3, iclass 12, count 2 2006.246.08:03:50.07#abcon#{5=INTERFACE CLEAR} 2006.246.08:03:50.08#ibcon#read 3, iclass 12, count 2 2006.246.08:03:50.08#ibcon#about to read 4, iclass 12, count 2 2006.246.08:03:50.08#ibcon#read 4, iclass 12, count 2 2006.246.08:03:50.08#ibcon#about to read 5, iclass 12, count 2 2006.246.08:03:50.08#ibcon#read 5, iclass 12, count 2 2006.246.08:03:50.08#ibcon#about to read 6, iclass 12, count 2 2006.246.08:03:50.08#ibcon#read 6, iclass 12, count 2 2006.246.08:03:50.08#ibcon#end of sib2, iclass 12, count 2 2006.246.08:03:50.08#ibcon#*mode == 0, iclass 12, count 2 2006.246.08:03:50.08#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.08:03:50.08#ibcon#[25=AT07-07\r\n] 2006.246.08:03:50.08#ibcon#*before write, iclass 12, count 2 2006.246.08:03:50.08#ibcon#enter sib2, iclass 12, count 2 2006.246.08:03:50.08#ibcon#flushed, iclass 12, count 2 2006.246.08:03:50.08#ibcon#about to write, iclass 12, count 2 2006.246.08:03:50.08#ibcon#wrote, iclass 12, count 2 2006.246.08:03:50.08#ibcon#about to read 3, iclass 12, count 2 2006.246.08:03:50.11#ibcon#read 3, iclass 12, count 2 2006.246.08:03:50.11#ibcon#about to read 4, iclass 12, count 2 2006.246.08:03:50.11#ibcon#read 4, iclass 12, count 2 2006.246.08:03:50.11#ibcon#about to read 5, iclass 12, count 2 2006.246.08:03:50.11#ibcon#read 5, iclass 12, count 2 2006.246.08:03:50.11#ibcon#about to read 6, iclass 12, count 2 2006.246.08:03:50.11#ibcon#read 6, iclass 12, count 2 2006.246.08:03:50.11#ibcon#end of sib2, iclass 12, count 2 2006.246.08:03:50.11#ibcon#*after write, iclass 12, count 2 2006.246.08:03:50.11#ibcon#*before return 0, iclass 12, count 2 2006.246.08:03:50.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:03:50.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:03:50.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.08:03:50.11#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:50.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:03:50.13#abcon#[5=S1D000X0/0*\r\n] 2006.246.08:03:50.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:03:50.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:03:50.23#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:03:50.23#ibcon#first serial, iclass 12, count 0 2006.246.08:03:50.23#ibcon#enter sib2, iclass 12, count 0 2006.246.08:03:50.23#ibcon#flushed, iclass 12, count 0 2006.246.08:03:50.23#ibcon#about to write, iclass 12, count 0 2006.246.08:03:50.23#ibcon#wrote, iclass 12, count 0 2006.246.08:03:50.23#ibcon#about to read 3, iclass 12, count 0 2006.246.08:03:50.25#ibcon#read 3, iclass 12, count 0 2006.246.08:03:50.25#ibcon#about to read 4, iclass 12, count 0 2006.246.08:03:50.25#ibcon#read 4, iclass 12, count 0 2006.246.08:03:50.25#ibcon#about to read 5, iclass 12, count 0 2006.246.08:03:50.25#ibcon#read 5, iclass 12, count 0 2006.246.08:03:50.25#ibcon#about to read 6, iclass 12, count 0 2006.246.08:03:50.25#ibcon#read 6, iclass 12, count 0 2006.246.08:03:50.25#ibcon#end of sib2, iclass 12, count 0 2006.246.08:03:50.25#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:03:50.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:03:50.25#ibcon#[25=USB\r\n] 2006.246.08:03:50.25#ibcon#*before write, iclass 12, count 0 2006.246.08:03:50.25#ibcon#enter sib2, iclass 12, count 0 2006.246.08:03:50.25#ibcon#flushed, iclass 12, count 0 2006.246.08:03:50.25#ibcon#about to write, iclass 12, count 0 2006.246.08:03:50.25#ibcon#wrote, iclass 12, count 0 2006.246.08:03:50.25#ibcon#about to read 3, iclass 12, count 0 2006.246.08:03:50.28#ibcon#read 3, iclass 12, count 0 2006.246.08:03:50.28#ibcon#about to read 4, iclass 12, count 0 2006.246.08:03:50.28#ibcon#read 4, iclass 12, count 0 2006.246.08:03:50.28#ibcon#about to read 5, iclass 12, count 0 2006.246.08:03:50.28#ibcon#read 5, iclass 12, count 0 2006.246.08:03:50.28#ibcon#about to read 6, iclass 12, count 0 2006.246.08:03:50.28#ibcon#read 6, iclass 12, count 0 2006.246.08:03:50.28#ibcon#end of sib2, iclass 12, count 0 2006.246.08:03:50.28#ibcon#*after write, iclass 12, count 0 2006.246.08:03:50.28#ibcon#*before return 0, iclass 12, count 0 2006.246.08:03:50.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:03:50.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:03:50.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:03:50.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:03:50.28$vc4f8/valo=8,852.99 2006.246.08:03:50.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.08:03:50.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.08:03:50.28#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:50.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:03:50.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:03:50.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:03:50.28#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:03:50.28#ibcon#first serial, iclass 18, count 0 2006.246.08:03:50.28#ibcon#enter sib2, iclass 18, count 0 2006.246.08:03:50.28#ibcon#flushed, iclass 18, count 0 2006.246.08:03:50.28#ibcon#about to write, iclass 18, count 0 2006.246.08:03:50.28#ibcon#wrote, iclass 18, count 0 2006.246.08:03:50.28#ibcon#about to read 3, iclass 18, count 0 2006.246.08:03:50.30#ibcon#read 3, iclass 18, count 0 2006.246.08:03:50.30#ibcon#about to read 4, iclass 18, count 0 2006.246.08:03:50.30#ibcon#read 4, iclass 18, count 0 2006.246.08:03:50.30#ibcon#about to read 5, iclass 18, count 0 2006.246.08:03:50.30#ibcon#read 5, iclass 18, count 0 2006.246.08:03:50.30#ibcon#about to read 6, iclass 18, count 0 2006.246.08:03:50.30#ibcon#read 6, iclass 18, count 0 2006.246.08:03:50.30#ibcon#end of sib2, iclass 18, count 0 2006.246.08:03:50.30#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:03:50.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:03:50.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:03:50.30#ibcon#*before write, iclass 18, count 0 2006.246.08:03:50.30#ibcon#enter sib2, iclass 18, count 0 2006.246.08:03:50.30#ibcon#flushed, iclass 18, count 0 2006.246.08:03:50.30#ibcon#about to write, iclass 18, count 0 2006.246.08:03:50.30#ibcon#wrote, iclass 18, count 0 2006.246.08:03:50.30#ibcon#about to read 3, iclass 18, count 0 2006.246.08:03:50.34#ibcon#read 3, iclass 18, count 0 2006.246.08:03:50.34#ibcon#about to read 4, iclass 18, count 0 2006.246.08:03:50.34#ibcon#read 4, iclass 18, count 0 2006.246.08:03:50.34#ibcon#about to read 5, iclass 18, count 0 2006.246.08:03:50.34#ibcon#read 5, iclass 18, count 0 2006.246.08:03:50.34#ibcon#about to read 6, iclass 18, count 0 2006.246.08:03:50.34#ibcon#read 6, iclass 18, count 0 2006.246.08:03:50.34#ibcon#end of sib2, iclass 18, count 0 2006.246.08:03:50.34#ibcon#*after write, iclass 18, count 0 2006.246.08:03:50.34#ibcon#*before return 0, iclass 18, count 0 2006.246.08:03:50.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:03:50.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:03:50.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:03:50.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:03:50.34$vc4f8/va=8,8 2006.246.08:03:50.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.08:03:50.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.08:03:50.34#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:50.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:03:50.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:03:50.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:03:50.40#ibcon#enter wrdev, iclass 20, count 2 2006.246.08:03:50.40#ibcon#first serial, iclass 20, count 2 2006.246.08:03:50.40#ibcon#enter sib2, iclass 20, count 2 2006.246.08:03:50.40#ibcon#flushed, iclass 20, count 2 2006.246.08:03:50.40#ibcon#about to write, iclass 20, count 2 2006.246.08:03:50.40#ibcon#wrote, iclass 20, count 2 2006.246.08:03:50.40#ibcon#about to read 3, iclass 20, count 2 2006.246.08:03:50.42#ibcon#read 3, iclass 20, count 2 2006.246.08:03:50.42#ibcon#about to read 4, iclass 20, count 2 2006.246.08:03:50.42#ibcon#read 4, iclass 20, count 2 2006.246.08:03:50.42#ibcon#about to read 5, iclass 20, count 2 2006.246.08:03:50.42#ibcon#read 5, iclass 20, count 2 2006.246.08:03:50.42#ibcon#about to read 6, iclass 20, count 2 2006.246.08:03:50.42#ibcon#read 6, iclass 20, count 2 2006.246.08:03:50.42#ibcon#end of sib2, iclass 20, count 2 2006.246.08:03:50.42#ibcon#*mode == 0, iclass 20, count 2 2006.246.08:03:50.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.08:03:50.42#ibcon#[25=AT08-08\r\n] 2006.246.08:03:50.42#ibcon#*before write, iclass 20, count 2 2006.246.08:03:50.42#ibcon#enter sib2, iclass 20, count 2 2006.246.08:03:50.42#ibcon#flushed, iclass 20, count 2 2006.246.08:03:50.42#ibcon#about to write, iclass 20, count 2 2006.246.08:03:50.42#ibcon#wrote, iclass 20, count 2 2006.246.08:03:50.42#ibcon#about to read 3, iclass 20, count 2 2006.246.08:03:50.45#ibcon#read 3, iclass 20, count 2 2006.246.08:03:50.45#ibcon#about to read 4, iclass 20, count 2 2006.246.08:03:50.45#ibcon#read 4, iclass 20, count 2 2006.246.08:03:50.45#ibcon#about to read 5, iclass 20, count 2 2006.246.08:03:50.45#ibcon#read 5, iclass 20, count 2 2006.246.08:03:50.45#ibcon#about to read 6, iclass 20, count 2 2006.246.08:03:50.45#ibcon#read 6, iclass 20, count 2 2006.246.08:03:50.45#ibcon#end of sib2, iclass 20, count 2 2006.246.08:03:50.45#ibcon#*after write, iclass 20, count 2 2006.246.08:03:50.45#ibcon#*before return 0, iclass 20, count 2 2006.246.08:03:50.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:03:50.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:03:50.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.08:03:50.45#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:50.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:03:50.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:03:50.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:03:50.57#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:03:50.57#ibcon#first serial, iclass 20, count 0 2006.246.08:03:50.57#ibcon#enter sib2, iclass 20, count 0 2006.246.08:03:50.57#ibcon#flushed, iclass 20, count 0 2006.246.08:03:50.57#ibcon#about to write, iclass 20, count 0 2006.246.08:03:50.57#ibcon#wrote, iclass 20, count 0 2006.246.08:03:50.57#ibcon#about to read 3, iclass 20, count 0 2006.246.08:03:50.59#ibcon#read 3, iclass 20, count 0 2006.246.08:03:50.59#ibcon#about to read 4, iclass 20, count 0 2006.246.08:03:50.59#ibcon#read 4, iclass 20, count 0 2006.246.08:03:50.59#ibcon#about to read 5, iclass 20, count 0 2006.246.08:03:50.59#ibcon#read 5, iclass 20, count 0 2006.246.08:03:50.59#ibcon#about to read 6, iclass 20, count 0 2006.246.08:03:50.59#ibcon#read 6, iclass 20, count 0 2006.246.08:03:50.59#ibcon#end of sib2, iclass 20, count 0 2006.246.08:03:50.59#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:03:50.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:03:50.59#ibcon#[25=USB\r\n] 2006.246.08:03:50.59#ibcon#*before write, iclass 20, count 0 2006.246.08:03:50.59#ibcon#enter sib2, iclass 20, count 0 2006.246.08:03:50.59#ibcon#flushed, iclass 20, count 0 2006.246.08:03:50.59#ibcon#about to write, iclass 20, count 0 2006.246.08:03:50.59#ibcon#wrote, iclass 20, count 0 2006.246.08:03:50.59#ibcon#about to read 3, iclass 20, count 0 2006.246.08:03:50.62#ibcon#read 3, iclass 20, count 0 2006.246.08:03:50.62#ibcon#about to read 4, iclass 20, count 0 2006.246.08:03:50.62#ibcon#read 4, iclass 20, count 0 2006.246.08:03:50.62#ibcon#about to read 5, iclass 20, count 0 2006.246.08:03:50.62#ibcon#read 5, iclass 20, count 0 2006.246.08:03:50.62#ibcon#about to read 6, iclass 20, count 0 2006.246.08:03:50.62#ibcon#read 6, iclass 20, count 0 2006.246.08:03:50.62#ibcon#end of sib2, iclass 20, count 0 2006.246.08:03:50.62#ibcon#*after write, iclass 20, count 0 2006.246.08:03:50.62#ibcon#*before return 0, iclass 20, count 0 2006.246.08:03:50.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:03:50.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:03:50.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:03:50.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:03:50.62$vc4f8/vblo=1,632.99 2006.246.08:03:50.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.08:03:50.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.08:03:50.62#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:50.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:50.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:50.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:50.62#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:03:50.62#ibcon#first serial, iclass 22, count 0 2006.246.08:03:50.62#ibcon#enter sib2, iclass 22, count 0 2006.246.08:03:50.62#ibcon#flushed, iclass 22, count 0 2006.246.08:03:50.62#ibcon#about to write, iclass 22, count 0 2006.246.08:03:50.62#ibcon#wrote, iclass 22, count 0 2006.246.08:03:50.62#ibcon#about to read 3, iclass 22, count 0 2006.246.08:03:50.64#ibcon#read 3, iclass 22, count 0 2006.246.08:03:50.64#ibcon#about to read 4, iclass 22, count 0 2006.246.08:03:50.64#ibcon#read 4, iclass 22, count 0 2006.246.08:03:50.64#ibcon#about to read 5, iclass 22, count 0 2006.246.08:03:50.64#ibcon#read 5, iclass 22, count 0 2006.246.08:03:50.64#ibcon#about to read 6, iclass 22, count 0 2006.246.08:03:50.64#ibcon#read 6, iclass 22, count 0 2006.246.08:03:50.64#ibcon#end of sib2, iclass 22, count 0 2006.246.08:03:50.64#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:03:50.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:03:50.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:03:50.64#ibcon#*before write, iclass 22, count 0 2006.246.08:03:50.64#ibcon#enter sib2, iclass 22, count 0 2006.246.08:03:50.64#ibcon#flushed, iclass 22, count 0 2006.246.08:03:50.64#ibcon#about to write, iclass 22, count 0 2006.246.08:03:50.64#ibcon#wrote, iclass 22, count 0 2006.246.08:03:50.64#ibcon#about to read 3, iclass 22, count 0 2006.246.08:03:50.69#ibcon#read 3, iclass 22, count 0 2006.246.08:03:50.69#ibcon#about to read 4, iclass 22, count 0 2006.246.08:03:50.69#ibcon#read 4, iclass 22, count 0 2006.246.08:03:50.69#ibcon#about to read 5, iclass 22, count 0 2006.246.08:03:50.69#ibcon#read 5, iclass 22, count 0 2006.246.08:03:50.69#ibcon#about to read 6, iclass 22, count 0 2006.246.08:03:50.69#ibcon#read 6, iclass 22, count 0 2006.246.08:03:50.69#ibcon#end of sib2, iclass 22, count 0 2006.246.08:03:50.69#ibcon#*after write, iclass 22, count 0 2006.246.08:03:50.69#ibcon#*before return 0, iclass 22, count 0 2006.246.08:03:50.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:50.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:03:50.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:03:50.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:03:50.69$vc4f8/vb=1,4 2006.246.08:03:50.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.08:03:50.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.08:03:50.69#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:50.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:50.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:50.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:50.69#ibcon#enter wrdev, iclass 24, count 2 2006.246.08:03:50.69#ibcon#first serial, iclass 24, count 2 2006.246.08:03:50.69#ibcon#enter sib2, iclass 24, count 2 2006.246.08:03:50.69#ibcon#flushed, iclass 24, count 2 2006.246.08:03:50.69#ibcon#about to write, iclass 24, count 2 2006.246.08:03:50.69#ibcon#wrote, iclass 24, count 2 2006.246.08:03:50.69#ibcon#about to read 3, iclass 24, count 2 2006.246.08:03:50.71#ibcon#read 3, iclass 24, count 2 2006.246.08:03:50.71#ibcon#about to read 4, iclass 24, count 2 2006.246.08:03:50.71#ibcon#read 4, iclass 24, count 2 2006.246.08:03:50.71#ibcon#about to read 5, iclass 24, count 2 2006.246.08:03:50.71#ibcon#read 5, iclass 24, count 2 2006.246.08:03:50.71#ibcon#about to read 6, iclass 24, count 2 2006.246.08:03:50.71#ibcon#read 6, iclass 24, count 2 2006.246.08:03:50.71#ibcon#end of sib2, iclass 24, count 2 2006.246.08:03:50.71#ibcon#*mode == 0, iclass 24, count 2 2006.246.08:03:50.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.08:03:50.71#ibcon#[27=AT01-04\r\n] 2006.246.08:03:50.71#ibcon#*before write, iclass 24, count 2 2006.246.08:03:50.71#ibcon#enter sib2, iclass 24, count 2 2006.246.08:03:50.71#ibcon#flushed, iclass 24, count 2 2006.246.08:03:50.71#ibcon#about to write, iclass 24, count 2 2006.246.08:03:50.71#ibcon#wrote, iclass 24, count 2 2006.246.08:03:50.71#ibcon#about to read 3, iclass 24, count 2 2006.246.08:03:50.74#ibcon#read 3, iclass 24, count 2 2006.246.08:03:50.74#ibcon#about to read 4, iclass 24, count 2 2006.246.08:03:50.74#ibcon#read 4, iclass 24, count 2 2006.246.08:03:50.74#ibcon#about to read 5, iclass 24, count 2 2006.246.08:03:50.74#ibcon#read 5, iclass 24, count 2 2006.246.08:03:50.74#ibcon#about to read 6, iclass 24, count 2 2006.246.08:03:50.74#ibcon#read 6, iclass 24, count 2 2006.246.08:03:50.74#ibcon#end of sib2, iclass 24, count 2 2006.246.08:03:50.74#ibcon#*after write, iclass 24, count 2 2006.246.08:03:50.74#ibcon#*before return 0, iclass 24, count 2 2006.246.08:03:50.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:50.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:03:50.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.08:03:50.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:50.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:50.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:50.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:50.86#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:03:50.86#ibcon#first serial, iclass 24, count 0 2006.246.08:03:50.86#ibcon#enter sib2, iclass 24, count 0 2006.246.08:03:50.86#ibcon#flushed, iclass 24, count 0 2006.246.08:03:50.86#ibcon#about to write, iclass 24, count 0 2006.246.08:03:50.86#ibcon#wrote, iclass 24, count 0 2006.246.08:03:50.86#ibcon#about to read 3, iclass 24, count 0 2006.246.08:03:50.88#ibcon#read 3, iclass 24, count 0 2006.246.08:03:50.88#ibcon#about to read 4, iclass 24, count 0 2006.246.08:03:50.88#ibcon#read 4, iclass 24, count 0 2006.246.08:03:50.88#ibcon#about to read 5, iclass 24, count 0 2006.246.08:03:50.88#ibcon#read 5, iclass 24, count 0 2006.246.08:03:50.88#ibcon#about to read 6, iclass 24, count 0 2006.246.08:03:50.88#ibcon#read 6, iclass 24, count 0 2006.246.08:03:50.88#ibcon#end of sib2, iclass 24, count 0 2006.246.08:03:50.88#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:03:50.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:03:50.88#ibcon#[27=USB\r\n] 2006.246.08:03:50.88#ibcon#*before write, iclass 24, count 0 2006.246.08:03:50.88#ibcon#enter sib2, iclass 24, count 0 2006.246.08:03:50.88#ibcon#flushed, iclass 24, count 0 2006.246.08:03:50.88#ibcon#about to write, iclass 24, count 0 2006.246.08:03:50.88#ibcon#wrote, iclass 24, count 0 2006.246.08:03:50.88#ibcon#about to read 3, iclass 24, count 0 2006.246.08:03:50.91#ibcon#read 3, iclass 24, count 0 2006.246.08:03:50.91#ibcon#about to read 4, iclass 24, count 0 2006.246.08:03:50.91#ibcon#read 4, iclass 24, count 0 2006.246.08:03:50.91#ibcon#about to read 5, iclass 24, count 0 2006.246.08:03:50.91#ibcon#read 5, iclass 24, count 0 2006.246.08:03:50.91#ibcon#about to read 6, iclass 24, count 0 2006.246.08:03:50.91#ibcon#read 6, iclass 24, count 0 2006.246.08:03:50.91#ibcon#end of sib2, iclass 24, count 0 2006.246.08:03:50.91#ibcon#*after write, iclass 24, count 0 2006.246.08:03:50.91#ibcon#*before return 0, iclass 24, count 0 2006.246.08:03:50.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:50.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:03:50.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:03:50.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:03:50.91$vc4f8/vblo=2,640.99 2006.246.08:03:50.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.08:03:50.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.08:03:50.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:50.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:50.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:50.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:50.91#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:03:50.91#ibcon#first serial, iclass 26, count 0 2006.246.08:03:50.91#ibcon#enter sib2, iclass 26, count 0 2006.246.08:03:50.91#ibcon#flushed, iclass 26, count 0 2006.246.08:03:50.91#ibcon#about to write, iclass 26, count 0 2006.246.08:03:50.91#ibcon#wrote, iclass 26, count 0 2006.246.08:03:50.91#ibcon#about to read 3, iclass 26, count 0 2006.246.08:03:50.93#ibcon#read 3, iclass 26, count 0 2006.246.08:03:50.93#ibcon#about to read 4, iclass 26, count 0 2006.246.08:03:50.93#ibcon#read 4, iclass 26, count 0 2006.246.08:03:50.93#ibcon#about to read 5, iclass 26, count 0 2006.246.08:03:50.93#ibcon#read 5, iclass 26, count 0 2006.246.08:03:50.93#ibcon#about to read 6, iclass 26, count 0 2006.246.08:03:50.93#ibcon#read 6, iclass 26, count 0 2006.246.08:03:50.93#ibcon#end of sib2, iclass 26, count 0 2006.246.08:03:50.93#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:03:50.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:03:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:03:50.93#ibcon#*before write, iclass 26, count 0 2006.246.08:03:50.93#ibcon#enter sib2, iclass 26, count 0 2006.246.08:03:50.93#ibcon#flushed, iclass 26, count 0 2006.246.08:03:50.93#ibcon#about to write, iclass 26, count 0 2006.246.08:03:50.93#ibcon#wrote, iclass 26, count 0 2006.246.08:03:50.93#ibcon#about to read 3, iclass 26, count 0 2006.246.08:03:50.97#ibcon#read 3, iclass 26, count 0 2006.246.08:03:50.97#ibcon#about to read 4, iclass 26, count 0 2006.246.08:03:50.97#ibcon#read 4, iclass 26, count 0 2006.246.08:03:50.97#ibcon#about to read 5, iclass 26, count 0 2006.246.08:03:50.97#ibcon#read 5, iclass 26, count 0 2006.246.08:03:50.97#ibcon#about to read 6, iclass 26, count 0 2006.246.08:03:50.97#ibcon#read 6, iclass 26, count 0 2006.246.08:03:50.97#ibcon#end of sib2, iclass 26, count 0 2006.246.08:03:50.97#ibcon#*after write, iclass 26, count 0 2006.246.08:03:50.97#ibcon#*before return 0, iclass 26, count 0 2006.246.08:03:50.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:50.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:03:50.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:03:50.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:03:50.97$vc4f8/vb=2,4 2006.246.08:03:50.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.08:03:50.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.08:03:50.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:50.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:51.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:51.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:51.03#ibcon#enter wrdev, iclass 28, count 2 2006.246.08:03:51.03#ibcon#first serial, iclass 28, count 2 2006.246.08:03:51.03#ibcon#enter sib2, iclass 28, count 2 2006.246.08:03:51.03#ibcon#flushed, iclass 28, count 2 2006.246.08:03:51.03#ibcon#about to write, iclass 28, count 2 2006.246.08:03:51.03#ibcon#wrote, iclass 28, count 2 2006.246.08:03:51.03#ibcon#about to read 3, iclass 28, count 2 2006.246.08:03:51.05#ibcon#read 3, iclass 28, count 2 2006.246.08:03:51.05#ibcon#about to read 4, iclass 28, count 2 2006.246.08:03:51.05#ibcon#read 4, iclass 28, count 2 2006.246.08:03:51.05#ibcon#about to read 5, iclass 28, count 2 2006.246.08:03:51.05#ibcon#read 5, iclass 28, count 2 2006.246.08:03:51.05#ibcon#about to read 6, iclass 28, count 2 2006.246.08:03:51.05#ibcon#read 6, iclass 28, count 2 2006.246.08:03:51.05#ibcon#end of sib2, iclass 28, count 2 2006.246.08:03:51.05#ibcon#*mode == 0, iclass 28, count 2 2006.246.08:03:51.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.08:03:51.05#ibcon#[27=AT02-04\r\n] 2006.246.08:03:51.05#ibcon#*before write, iclass 28, count 2 2006.246.08:03:51.05#ibcon#enter sib2, iclass 28, count 2 2006.246.08:03:51.05#ibcon#flushed, iclass 28, count 2 2006.246.08:03:51.05#ibcon#about to write, iclass 28, count 2 2006.246.08:03:51.05#ibcon#wrote, iclass 28, count 2 2006.246.08:03:51.05#ibcon#about to read 3, iclass 28, count 2 2006.246.08:03:51.08#ibcon#read 3, iclass 28, count 2 2006.246.08:03:51.08#ibcon#about to read 4, iclass 28, count 2 2006.246.08:03:51.08#ibcon#read 4, iclass 28, count 2 2006.246.08:03:51.08#ibcon#about to read 5, iclass 28, count 2 2006.246.08:03:51.08#ibcon#read 5, iclass 28, count 2 2006.246.08:03:51.08#ibcon#about to read 6, iclass 28, count 2 2006.246.08:03:51.08#ibcon#read 6, iclass 28, count 2 2006.246.08:03:51.08#ibcon#end of sib2, iclass 28, count 2 2006.246.08:03:51.08#ibcon#*after write, iclass 28, count 2 2006.246.08:03:51.08#ibcon#*before return 0, iclass 28, count 2 2006.246.08:03:51.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:51.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:03:51.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.08:03:51.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:51.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:51.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:51.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:51.20#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:03:51.20#ibcon#first serial, iclass 28, count 0 2006.246.08:03:51.20#ibcon#enter sib2, iclass 28, count 0 2006.246.08:03:51.20#ibcon#flushed, iclass 28, count 0 2006.246.08:03:51.20#ibcon#about to write, iclass 28, count 0 2006.246.08:03:51.20#ibcon#wrote, iclass 28, count 0 2006.246.08:03:51.20#ibcon#about to read 3, iclass 28, count 0 2006.246.08:03:51.23#ibcon#read 3, iclass 28, count 0 2006.246.08:03:51.23#ibcon#about to read 4, iclass 28, count 0 2006.246.08:03:51.23#ibcon#read 4, iclass 28, count 0 2006.246.08:03:51.23#ibcon#about to read 5, iclass 28, count 0 2006.246.08:03:51.23#ibcon#read 5, iclass 28, count 0 2006.246.08:03:51.23#ibcon#about to read 6, iclass 28, count 0 2006.246.08:03:51.23#ibcon#read 6, iclass 28, count 0 2006.246.08:03:51.23#ibcon#end of sib2, iclass 28, count 0 2006.246.08:03:51.23#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:03:51.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:03:51.23#ibcon#[27=USB\r\n] 2006.246.08:03:51.23#ibcon#*before write, iclass 28, count 0 2006.246.08:03:51.23#ibcon#enter sib2, iclass 28, count 0 2006.246.08:03:51.23#ibcon#flushed, iclass 28, count 0 2006.246.08:03:51.23#ibcon#about to write, iclass 28, count 0 2006.246.08:03:51.23#ibcon#wrote, iclass 28, count 0 2006.246.08:03:51.23#ibcon#about to read 3, iclass 28, count 0 2006.246.08:03:51.26#ibcon#read 3, iclass 28, count 0 2006.246.08:03:51.26#ibcon#about to read 4, iclass 28, count 0 2006.246.08:03:51.26#ibcon#read 4, iclass 28, count 0 2006.246.08:03:51.26#ibcon#about to read 5, iclass 28, count 0 2006.246.08:03:51.26#ibcon#read 5, iclass 28, count 0 2006.246.08:03:51.26#ibcon#about to read 6, iclass 28, count 0 2006.246.08:03:51.26#ibcon#read 6, iclass 28, count 0 2006.246.08:03:51.26#ibcon#end of sib2, iclass 28, count 0 2006.246.08:03:51.26#ibcon#*after write, iclass 28, count 0 2006.246.08:03:51.26#ibcon#*before return 0, iclass 28, count 0 2006.246.08:03:51.26#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:51.26#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:03:51.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:03:51.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:03:51.26$vc4f8/vblo=3,656.99 2006.246.08:03:51.26#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.08:03:51.26#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.08:03:51.26#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:51.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:51.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:51.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:51.26#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:03:51.26#ibcon#first serial, iclass 30, count 0 2006.246.08:03:51.26#ibcon#enter sib2, iclass 30, count 0 2006.246.08:03:51.26#ibcon#flushed, iclass 30, count 0 2006.246.08:03:51.26#ibcon#about to write, iclass 30, count 0 2006.246.08:03:51.26#ibcon#wrote, iclass 30, count 0 2006.246.08:03:51.26#ibcon#about to read 3, iclass 30, count 0 2006.246.08:03:51.28#ibcon#read 3, iclass 30, count 0 2006.246.08:03:51.28#ibcon#about to read 4, iclass 30, count 0 2006.246.08:03:51.28#ibcon#read 4, iclass 30, count 0 2006.246.08:03:51.28#ibcon#about to read 5, iclass 30, count 0 2006.246.08:03:51.28#ibcon#read 5, iclass 30, count 0 2006.246.08:03:51.28#ibcon#about to read 6, iclass 30, count 0 2006.246.08:03:51.28#ibcon#read 6, iclass 30, count 0 2006.246.08:03:51.28#ibcon#end of sib2, iclass 30, count 0 2006.246.08:03:51.28#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:03:51.28#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:03:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:03:51.28#ibcon#*before write, iclass 30, count 0 2006.246.08:03:51.28#ibcon#enter sib2, iclass 30, count 0 2006.246.08:03:51.28#ibcon#flushed, iclass 30, count 0 2006.246.08:03:51.28#ibcon#about to write, iclass 30, count 0 2006.246.08:03:51.28#ibcon#wrote, iclass 30, count 0 2006.246.08:03:51.28#ibcon#about to read 3, iclass 30, count 0 2006.246.08:03:51.32#ibcon#read 3, iclass 30, count 0 2006.246.08:03:51.32#ibcon#about to read 4, iclass 30, count 0 2006.246.08:03:51.32#ibcon#read 4, iclass 30, count 0 2006.246.08:03:51.32#ibcon#about to read 5, iclass 30, count 0 2006.246.08:03:51.32#ibcon#read 5, iclass 30, count 0 2006.246.08:03:51.32#ibcon#about to read 6, iclass 30, count 0 2006.246.08:03:51.32#ibcon#read 6, iclass 30, count 0 2006.246.08:03:51.32#ibcon#end of sib2, iclass 30, count 0 2006.246.08:03:51.32#ibcon#*after write, iclass 30, count 0 2006.246.08:03:51.32#ibcon#*before return 0, iclass 30, count 0 2006.246.08:03:51.32#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:51.32#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:03:51.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:03:51.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:03:51.32$vc4f8/vb=3,4 2006.246.08:03:51.32#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.08:03:51.32#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.08:03:51.32#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:51.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:51.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:51.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:51.38#ibcon#enter wrdev, iclass 32, count 2 2006.246.08:03:51.38#ibcon#first serial, iclass 32, count 2 2006.246.08:03:51.38#ibcon#enter sib2, iclass 32, count 2 2006.246.08:03:51.38#ibcon#flushed, iclass 32, count 2 2006.246.08:03:51.38#ibcon#about to write, iclass 32, count 2 2006.246.08:03:51.38#ibcon#wrote, iclass 32, count 2 2006.246.08:03:51.38#ibcon#about to read 3, iclass 32, count 2 2006.246.08:03:51.40#ibcon#read 3, iclass 32, count 2 2006.246.08:03:51.40#ibcon#about to read 4, iclass 32, count 2 2006.246.08:03:51.40#ibcon#read 4, iclass 32, count 2 2006.246.08:03:51.40#ibcon#about to read 5, iclass 32, count 2 2006.246.08:03:51.40#ibcon#read 5, iclass 32, count 2 2006.246.08:03:51.40#ibcon#about to read 6, iclass 32, count 2 2006.246.08:03:51.40#ibcon#read 6, iclass 32, count 2 2006.246.08:03:51.40#ibcon#end of sib2, iclass 32, count 2 2006.246.08:03:51.40#ibcon#*mode == 0, iclass 32, count 2 2006.246.08:03:51.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.08:03:51.40#ibcon#[27=AT03-04\r\n] 2006.246.08:03:51.40#ibcon#*before write, iclass 32, count 2 2006.246.08:03:51.40#ibcon#enter sib2, iclass 32, count 2 2006.246.08:03:51.40#ibcon#flushed, iclass 32, count 2 2006.246.08:03:51.40#ibcon#about to write, iclass 32, count 2 2006.246.08:03:51.40#ibcon#wrote, iclass 32, count 2 2006.246.08:03:51.40#ibcon#about to read 3, iclass 32, count 2 2006.246.08:03:51.43#ibcon#read 3, iclass 32, count 2 2006.246.08:03:51.43#ibcon#about to read 4, iclass 32, count 2 2006.246.08:03:51.43#ibcon#read 4, iclass 32, count 2 2006.246.08:03:51.43#ibcon#about to read 5, iclass 32, count 2 2006.246.08:03:51.43#ibcon#read 5, iclass 32, count 2 2006.246.08:03:51.43#ibcon#about to read 6, iclass 32, count 2 2006.246.08:03:51.43#ibcon#read 6, iclass 32, count 2 2006.246.08:03:51.43#ibcon#end of sib2, iclass 32, count 2 2006.246.08:03:51.43#ibcon#*after write, iclass 32, count 2 2006.246.08:03:51.43#ibcon#*before return 0, iclass 32, count 2 2006.246.08:03:51.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:51.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:03:51.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.08:03:51.43#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:51.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:51.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:51.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:51.55#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:03:51.55#ibcon#first serial, iclass 32, count 0 2006.246.08:03:51.55#ibcon#enter sib2, iclass 32, count 0 2006.246.08:03:51.55#ibcon#flushed, iclass 32, count 0 2006.246.08:03:51.55#ibcon#about to write, iclass 32, count 0 2006.246.08:03:51.55#ibcon#wrote, iclass 32, count 0 2006.246.08:03:51.55#ibcon#about to read 3, iclass 32, count 0 2006.246.08:03:51.57#ibcon#read 3, iclass 32, count 0 2006.246.08:03:51.57#ibcon#about to read 4, iclass 32, count 0 2006.246.08:03:51.57#ibcon#read 4, iclass 32, count 0 2006.246.08:03:51.57#ibcon#about to read 5, iclass 32, count 0 2006.246.08:03:51.57#ibcon#read 5, iclass 32, count 0 2006.246.08:03:51.57#ibcon#about to read 6, iclass 32, count 0 2006.246.08:03:51.57#ibcon#read 6, iclass 32, count 0 2006.246.08:03:51.57#ibcon#end of sib2, iclass 32, count 0 2006.246.08:03:51.57#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:03:51.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:03:51.57#ibcon#[27=USB\r\n] 2006.246.08:03:51.57#ibcon#*before write, iclass 32, count 0 2006.246.08:03:51.57#ibcon#enter sib2, iclass 32, count 0 2006.246.08:03:51.57#ibcon#flushed, iclass 32, count 0 2006.246.08:03:51.57#ibcon#about to write, iclass 32, count 0 2006.246.08:03:51.57#ibcon#wrote, iclass 32, count 0 2006.246.08:03:51.57#ibcon#about to read 3, iclass 32, count 0 2006.246.08:03:51.60#ibcon#read 3, iclass 32, count 0 2006.246.08:03:51.60#ibcon#about to read 4, iclass 32, count 0 2006.246.08:03:51.60#ibcon#read 4, iclass 32, count 0 2006.246.08:03:51.60#ibcon#about to read 5, iclass 32, count 0 2006.246.08:03:51.60#ibcon#read 5, iclass 32, count 0 2006.246.08:03:51.60#ibcon#about to read 6, iclass 32, count 0 2006.246.08:03:51.60#ibcon#read 6, iclass 32, count 0 2006.246.08:03:51.60#ibcon#end of sib2, iclass 32, count 0 2006.246.08:03:51.60#ibcon#*after write, iclass 32, count 0 2006.246.08:03:51.60#ibcon#*before return 0, iclass 32, count 0 2006.246.08:03:51.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:51.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:03:51.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:03:51.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:03:51.60$vc4f8/vblo=4,712.99 2006.246.08:03:51.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.08:03:51.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.08:03:51.60#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:51.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:51.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:51.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:51.60#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:03:51.60#ibcon#first serial, iclass 34, count 0 2006.246.08:03:51.60#ibcon#enter sib2, iclass 34, count 0 2006.246.08:03:51.60#ibcon#flushed, iclass 34, count 0 2006.246.08:03:51.60#ibcon#about to write, iclass 34, count 0 2006.246.08:03:51.60#ibcon#wrote, iclass 34, count 0 2006.246.08:03:51.60#ibcon#about to read 3, iclass 34, count 0 2006.246.08:03:51.62#ibcon#read 3, iclass 34, count 0 2006.246.08:03:51.62#ibcon#about to read 4, iclass 34, count 0 2006.246.08:03:51.62#ibcon#read 4, iclass 34, count 0 2006.246.08:03:51.62#ibcon#about to read 5, iclass 34, count 0 2006.246.08:03:51.62#ibcon#read 5, iclass 34, count 0 2006.246.08:03:51.62#ibcon#about to read 6, iclass 34, count 0 2006.246.08:03:51.62#ibcon#read 6, iclass 34, count 0 2006.246.08:03:51.62#ibcon#end of sib2, iclass 34, count 0 2006.246.08:03:51.62#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:03:51.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:03:51.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:03:51.62#ibcon#*before write, iclass 34, count 0 2006.246.08:03:51.62#ibcon#enter sib2, iclass 34, count 0 2006.246.08:03:51.62#ibcon#flushed, iclass 34, count 0 2006.246.08:03:51.62#ibcon#about to write, iclass 34, count 0 2006.246.08:03:51.62#ibcon#wrote, iclass 34, count 0 2006.246.08:03:51.62#ibcon#about to read 3, iclass 34, count 0 2006.246.08:03:51.66#ibcon#read 3, iclass 34, count 0 2006.246.08:03:51.66#ibcon#about to read 4, iclass 34, count 0 2006.246.08:03:51.66#ibcon#read 4, iclass 34, count 0 2006.246.08:03:51.66#ibcon#about to read 5, iclass 34, count 0 2006.246.08:03:51.66#ibcon#read 5, iclass 34, count 0 2006.246.08:03:51.66#ibcon#about to read 6, iclass 34, count 0 2006.246.08:03:51.66#ibcon#read 6, iclass 34, count 0 2006.246.08:03:51.66#ibcon#end of sib2, iclass 34, count 0 2006.246.08:03:51.66#ibcon#*after write, iclass 34, count 0 2006.246.08:03:51.66#ibcon#*before return 0, iclass 34, count 0 2006.246.08:03:51.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:51.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:03:51.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:03:51.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:03:51.66$vc4f8/vb=4,4 2006.246.08:03:51.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.08:03:51.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.08:03:51.66#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:51.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:51.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:51.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:51.72#ibcon#enter wrdev, iclass 36, count 2 2006.246.08:03:51.72#ibcon#first serial, iclass 36, count 2 2006.246.08:03:51.72#ibcon#enter sib2, iclass 36, count 2 2006.246.08:03:51.72#ibcon#flushed, iclass 36, count 2 2006.246.08:03:51.72#ibcon#about to write, iclass 36, count 2 2006.246.08:03:51.72#ibcon#wrote, iclass 36, count 2 2006.246.08:03:51.72#ibcon#about to read 3, iclass 36, count 2 2006.246.08:03:51.74#ibcon#read 3, iclass 36, count 2 2006.246.08:03:51.74#ibcon#about to read 4, iclass 36, count 2 2006.246.08:03:51.74#ibcon#read 4, iclass 36, count 2 2006.246.08:03:51.74#ibcon#about to read 5, iclass 36, count 2 2006.246.08:03:51.74#ibcon#read 5, iclass 36, count 2 2006.246.08:03:51.74#ibcon#about to read 6, iclass 36, count 2 2006.246.08:03:51.74#ibcon#read 6, iclass 36, count 2 2006.246.08:03:51.74#ibcon#end of sib2, iclass 36, count 2 2006.246.08:03:51.74#ibcon#*mode == 0, iclass 36, count 2 2006.246.08:03:51.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.08:03:51.74#ibcon#[27=AT04-04\r\n] 2006.246.08:03:51.74#ibcon#*before write, iclass 36, count 2 2006.246.08:03:51.74#ibcon#enter sib2, iclass 36, count 2 2006.246.08:03:51.74#ibcon#flushed, iclass 36, count 2 2006.246.08:03:51.74#ibcon#about to write, iclass 36, count 2 2006.246.08:03:51.74#ibcon#wrote, iclass 36, count 2 2006.246.08:03:51.74#ibcon#about to read 3, iclass 36, count 2 2006.246.08:03:51.77#ibcon#read 3, iclass 36, count 2 2006.246.08:03:51.77#ibcon#about to read 4, iclass 36, count 2 2006.246.08:03:51.77#ibcon#read 4, iclass 36, count 2 2006.246.08:03:51.77#ibcon#about to read 5, iclass 36, count 2 2006.246.08:03:51.77#ibcon#read 5, iclass 36, count 2 2006.246.08:03:51.77#ibcon#about to read 6, iclass 36, count 2 2006.246.08:03:51.77#ibcon#read 6, iclass 36, count 2 2006.246.08:03:51.77#ibcon#end of sib2, iclass 36, count 2 2006.246.08:03:51.77#ibcon#*after write, iclass 36, count 2 2006.246.08:03:51.77#ibcon#*before return 0, iclass 36, count 2 2006.246.08:03:51.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:51.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:03:51.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.08:03:51.77#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:51.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:51.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:51.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:51.89#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:03:51.89#ibcon#first serial, iclass 36, count 0 2006.246.08:03:51.89#ibcon#enter sib2, iclass 36, count 0 2006.246.08:03:51.89#ibcon#flushed, iclass 36, count 0 2006.246.08:03:51.89#ibcon#about to write, iclass 36, count 0 2006.246.08:03:51.89#ibcon#wrote, iclass 36, count 0 2006.246.08:03:51.89#ibcon#about to read 3, iclass 36, count 0 2006.246.08:03:51.91#ibcon#read 3, iclass 36, count 0 2006.246.08:03:51.91#ibcon#about to read 4, iclass 36, count 0 2006.246.08:03:51.91#ibcon#read 4, iclass 36, count 0 2006.246.08:03:51.91#ibcon#about to read 5, iclass 36, count 0 2006.246.08:03:51.91#ibcon#read 5, iclass 36, count 0 2006.246.08:03:51.91#ibcon#about to read 6, iclass 36, count 0 2006.246.08:03:51.91#ibcon#read 6, iclass 36, count 0 2006.246.08:03:51.91#ibcon#end of sib2, iclass 36, count 0 2006.246.08:03:51.91#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:03:51.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:03:51.91#ibcon#[27=USB\r\n] 2006.246.08:03:51.91#ibcon#*before write, iclass 36, count 0 2006.246.08:03:51.91#ibcon#enter sib2, iclass 36, count 0 2006.246.08:03:51.91#ibcon#flushed, iclass 36, count 0 2006.246.08:03:51.91#ibcon#about to write, iclass 36, count 0 2006.246.08:03:51.91#ibcon#wrote, iclass 36, count 0 2006.246.08:03:51.91#ibcon#about to read 3, iclass 36, count 0 2006.246.08:03:51.94#ibcon#read 3, iclass 36, count 0 2006.246.08:03:51.94#ibcon#about to read 4, iclass 36, count 0 2006.246.08:03:51.94#ibcon#read 4, iclass 36, count 0 2006.246.08:03:51.94#ibcon#about to read 5, iclass 36, count 0 2006.246.08:03:51.94#ibcon#read 5, iclass 36, count 0 2006.246.08:03:51.94#ibcon#about to read 6, iclass 36, count 0 2006.246.08:03:51.94#ibcon#read 6, iclass 36, count 0 2006.246.08:03:51.94#ibcon#end of sib2, iclass 36, count 0 2006.246.08:03:51.94#ibcon#*after write, iclass 36, count 0 2006.246.08:03:51.94#ibcon#*before return 0, iclass 36, count 0 2006.246.08:03:51.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:51.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:03:51.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:03:51.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:03:51.94$vc4f8/vblo=5,744.99 2006.246.08:03:51.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.08:03:51.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.08:03:51.94#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:51.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:51.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:51.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:51.94#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:03:51.94#ibcon#first serial, iclass 38, count 0 2006.246.08:03:51.94#ibcon#enter sib2, iclass 38, count 0 2006.246.08:03:51.94#ibcon#flushed, iclass 38, count 0 2006.246.08:03:51.94#ibcon#about to write, iclass 38, count 0 2006.246.08:03:51.94#ibcon#wrote, iclass 38, count 0 2006.246.08:03:51.94#ibcon#about to read 3, iclass 38, count 0 2006.246.08:03:51.96#ibcon#read 3, iclass 38, count 0 2006.246.08:03:51.96#ibcon#about to read 4, iclass 38, count 0 2006.246.08:03:51.96#ibcon#read 4, iclass 38, count 0 2006.246.08:03:51.96#ibcon#about to read 5, iclass 38, count 0 2006.246.08:03:51.96#ibcon#read 5, iclass 38, count 0 2006.246.08:03:51.96#ibcon#about to read 6, iclass 38, count 0 2006.246.08:03:51.96#ibcon#read 6, iclass 38, count 0 2006.246.08:03:51.96#ibcon#end of sib2, iclass 38, count 0 2006.246.08:03:51.96#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:03:51.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:03:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:03:51.96#ibcon#*before write, iclass 38, count 0 2006.246.08:03:51.96#ibcon#enter sib2, iclass 38, count 0 2006.246.08:03:51.96#ibcon#flushed, iclass 38, count 0 2006.246.08:03:51.96#ibcon#about to write, iclass 38, count 0 2006.246.08:03:51.96#ibcon#wrote, iclass 38, count 0 2006.246.08:03:51.96#ibcon#about to read 3, iclass 38, count 0 2006.246.08:03:52.00#ibcon#read 3, iclass 38, count 0 2006.246.08:03:52.00#ibcon#about to read 4, iclass 38, count 0 2006.246.08:03:52.00#ibcon#read 4, iclass 38, count 0 2006.246.08:03:52.00#ibcon#about to read 5, iclass 38, count 0 2006.246.08:03:52.00#ibcon#read 5, iclass 38, count 0 2006.246.08:03:52.00#ibcon#about to read 6, iclass 38, count 0 2006.246.08:03:52.00#ibcon#read 6, iclass 38, count 0 2006.246.08:03:52.00#ibcon#end of sib2, iclass 38, count 0 2006.246.08:03:52.00#ibcon#*after write, iclass 38, count 0 2006.246.08:03:52.00#ibcon#*before return 0, iclass 38, count 0 2006.246.08:03:52.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:52.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:03:52.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:03:52.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:03:52.00$vc4f8/vb=5,3 2006.246.08:03:52.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.08:03:52.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.08:03:52.00#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:52.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:52.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:52.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:52.06#ibcon#enter wrdev, iclass 40, count 2 2006.246.08:03:52.06#ibcon#first serial, iclass 40, count 2 2006.246.08:03:52.06#ibcon#enter sib2, iclass 40, count 2 2006.246.08:03:52.06#ibcon#flushed, iclass 40, count 2 2006.246.08:03:52.06#ibcon#about to write, iclass 40, count 2 2006.246.08:03:52.06#ibcon#wrote, iclass 40, count 2 2006.246.08:03:52.06#ibcon#about to read 3, iclass 40, count 2 2006.246.08:03:52.08#ibcon#read 3, iclass 40, count 2 2006.246.08:03:52.08#ibcon#about to read 4, iclass 40, count 2 2006.246.08:03:52.08#ibcon#read 4, iclass 40, count 2 2006.246.08:03:52.08#ibcon#about to read 5, iclass 40, count 2 2006.246.08:03:52.08#ibcon#read 5, iclass 40, count 2 2006.246.08:03:52.08#ibcon#about to read 6, iclass 40, count 2 2006.246.08:03:52.08#ibcon#read 6, iclass 40, count 2 2006.246.08:03:52.08#ibcon#end of sib2, iclass 40, count 2 2006.246.08:03:52.08#ibcon#*mode == 0, iclass 40, count 2 2006.246.08:03:52.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.08:03:52.08#ibcon#[27=AT05-03\r\n] 2006.246.08:03:52.08#ibcon#*before write, iclass 40, count 2 2006.246.08:03:52.08#ibcon#enter sib2, iclass 40, count 2 2006.246.08:03:52.08#ibcon#flushed, iclass 40, count 2 2006.246.08:03:52.08#ibcon#about to write, iclass 40, count 2 2006.246.08:03:52.08#ibcon#wrote, iclass 40, count 2 2006.246.08:03:52.08#ibcon#about to read 3, iclass 40, count 2 2006.246.08:03:52.11#ibcon#read 3, iclass 40, count 2 2006.246.08:03:52.11#ibcon#about to read 4, iclass 40, count 2 2006.246.08:03:52.11#ibcon#read 4, iclass 40, count 2 2006.246.08:03:52.11#ibcon#about to read 5, iclass 40, count 2 2006.246.08:03:52.11#ibcon#read 5, iclass 40, count 2 2006.246.08:03:52.11#ibcon#about to read 6, iclass 40, count 2 2006.246.08:03:52.11#ibcon#read 6, iclass 40, count 2 2006.246.08:03:52.11#ibcon#end of sib2, iclass 40, count 2 2006.246.08:03:52.11#ibcon#*after write, iclass 40, count 2 2006.246.08:03:52.11#ibcon#*before return 0, iclass 40, count 2 2006.246.08:03:52.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:52.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:03:52.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.08:03:52.11#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:52.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:52.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:52.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:52.23#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:03:52.23#ibcon#first serial, iclass 40, count 0 2006.246.08:03:52.23#ibcon#enter sib2, iclass 40, count 0 2006.246.08:03:52.23#ibcon#flushed, iclass 40, count 0 2006.246.08:03:52.23#ibcon#about to write, iclass 40, count 0 2006.246.08:03:52.23#ibcon#wrote, iclass 40, count 0 2006.246.08:03:52.23#ibcon#about to read 3, iclass 40, count 0 2006.246.08:03:52.25#ibcon#read 3, iclass 40, count 0 2006.246.08:03:52.25#ibcon#about to read 4, iclass 40, count 0 2006.246.08:03:52.25#ibcon#read 4, iclass 40, count 0 2006.246.08:03:52.25#ibcon#about to read 5, iclass 40, count 0 2006.246.08:03:52.25#ibcon#read 5, iclass 40, count 0 2006.246.08:03:52.25#ibcon#about to read 6, iclass 40, count 0 2006.246.08:03:52.25#ibcon#read 6, iclass 40, count 0 2006.246.08:03:52.25#ibcon#end of sib2, iclass 40, count 0 2006.246.08:03:52.25#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:03:52.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:03:52.25#ibcon#[27=USB\r\n] 2006.246.08:03:52.25#ibcon#*before write, iclass 40, count 0 2006.246.08:03:52.25#ibcon#enter sib2, iclass 40, count 0 2006.246.08:03:52.25#ibcon#flushed, iclass 40, count 0 2006.246.08:03:52.25#ibcon#about to write, iclass 40, count 0 2006.246.08:03:52.25#ibcon#wrote, iclass 40, count 0 2006.246.08:03:52.25#ibcon#about to read 3, iclass 40, count 0 2006.246.08:03:52.28#ibcon#read 3, iclass 40, count 0 2006.246.08:03:52.28#ibcon#about to read 4, iclass 40, count 0 2006.246.08:03:52.28#ibcon#read 4, iclass 40, count 0 2006.246.08:03:52.28#ibcon#about to read 5, iclass 40, count 0 2006.246.08:03:52.28#ibcon#read 5, iclass 40, count 0 2006.246.08:03:52.28#ibcon#about to read 6, iclass 40, count 0 2006.246.08:03:52.28#ibcon#read 6, iclass 40, count 0 2006.246.08:03:52.28#ibcon#end of sib2, iclass 40, count 0 2006.246.08:03:52.28#ibcon#*after write, iclass 40, count 0 2006.246.08:03:52.28#ibcon#*before return 0, iclass 40, count 0 2006.246.08:03:52.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:52.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:03:52.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:03:52.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:03:52.28$vc4f8/vblo=6,752.99 2006.246.08:03:52.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.08:03:52.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.08:03:52.28#ibcon#ireg 17 cls_cnt 0 2006.246.08:03:52.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:52.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:52.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:52.28#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:03:52.28#ibcon#first serial, iclass 4, count 0 2006.246.08:03:52.28#ibcon#enter sib2, iclass 4, count 0 2006.246.08:03:52.28#ibcon#flushed, iclass 4, count 0 2006.246.08:03:52.28#ibcon#about to write, iclass 4, count 0 2006.246.08:03:52.28#ibcon#wrote, iclass 4, count 0 2006.246.08:03:52.28#ibcon#about to read 3, iclass 4, count 0 2006.246.08:03:52.30#ibcon#read 3, iclass 4, count 0 2006.246.08:03:52.30#ibcon#about to read 4, iclass 4, count 0 2006.246.08:03:52.30#ibcon#read 4, iclass 4, count 0 2006.246.08:03:52.30#ibcon#about to read 5, iclass 4, count 0 2006.246.08:03:52.30#ibcon#read 5, iclass 4, count 0 2006.246.08:03:52.30#ibcon#about to read 6, iclass 4, count 0 2006.246.08:03:52.30#ibcon#read 6, iclass 4, count 0 2006.246.08:03:52.30#ibcon#end of sib2, iclass 4, count 0 2006.246.08:03:52.30#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:03:52.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:03:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:03:52.30#ibcon#*before write, iclass 4, count 0 2006.246.08:03:52.30#ibcon#enter sib2, iclass 4, count 0 2006.246.08:03:52.30#ibcon#flushed, iclass 4, count 0 2006.246.08:03:52.30#ibcon#about to write, iclass 4, count 0 2006.246.08:03:52.30#ibcon#wrote, iclass 4, count 0 2006.246.08:03:52.30#ibcon#about to read 3, iclass 4, count 0 2006.246.08:03:52.35#ibcon#read 3, iclass 4, count 0 2006.246.08:03:52.35#ibcon#about to read 4, iclass 4, count 0 2006.246.08:03:52.35#ibcon#read 4, iclass 4, count 0 2006.246.08:03:52.35#ibcon#about to read 5, iclass 4, count 0 2006.246.08:03:52.35#ibcon#read 5, iclass 4, count 0 2006.246.08:03:52.35#ibcon#about to read 6, iclass 4, count 0 2006.246.08:03:52.35#ibcon#read 6, iclass 4, count 0 2006.246.08:03:52.35#ibcon#end of sib2, iclass 4, count 0 2006.246.08:03:52.35#ibcon#*after write, iclass 4, count 0 2006.246.08:03:52.35#ibcon#*before return 0, iclass 4, count 0 2006.246.08:03:52.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:52.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:03:52.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:03:52.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:03:52.35$vc4f8/vb=6,3 2006.246.08:03:52.35#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.08:03:52.35#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.08:03:52.35#ibcon#ireg 11 cls_cnt 2 2006.246.08:03:52.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:52.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:52.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:52.40#ibcon#enter wrdev, iclass 6, count 2 2006.246.08:03:52.40#ibcon#first serial, iclass 6, count 2 2006.246.08:03:52.40#ibcon#enter sib2, iclass 6, count 2 2006.246.08:03:52.40#ibcon#flushed, iclass 6, count 2 2006.246.08:03:52.40#ibcon#about to write, iclass 6, count 2 2006.246.08:03:52.40#ibcon#wrote, iclass 6, count 2 2006.246.08:03:52.40#ibcon#about to read 3, iclass 6, count 2 2006.246.08:03:52.42#ibcon#read 3, iclass 6, count 2 2006.246.08:03:52.42#ibcon#about to read 4, iclass 6, count 2 2006.246.08:03:52.42#ibcon#read 4, iclass 6, count 2 2006.246.08:03:52.42#ibcon#about to read 5, iclass 6, count 2 2006.246.08:03:52.42#ibcon#read 5, iclass 6, count 2 2006.246.08:03:52.42#ibcon#about to read 6, iclass 6, count 2 2006.246.08:03:52.42#ibcon#read 6, iclass 6, count 2 2006.246.08:03:52.42#ibcon#end of sib2, iclass 6, count 2 2006.246.08:03:52.42#ibcon#*mode == 0, iclass 6, count 2 2006.246.08:03:52.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.08:03:52.42#ibcon#[27=AT06-03\r\n] 2006.246.08:03:52.42#ibcon#*before write, iclass 6, count 2 2006.246.08:03:52.42#ibcon#enter sib2, iclass 6, count 2 2006.246.08:03:52.42#ibcon#flushed, iclass 6, count 2 2006.246.08:03:52.42#ibcon#about to write, iclass 6, count 2 2006.246.08:03:52.42#ibcon#wrote, iclass 6, count 2 2006.246.08:03:52.42#ibcon#about to read 3, iclass 6, count 2 2006.246.08:03:52.45#ibcon#read 3, iclass 6, count 2 2006.246.08:03:52.45#ibcon#about to read 4, iclass 6, count 2 2006.246.08:03:52.45#ibcon#read 4, iclass 6, count 2 2006.246.08:03:52.45#ibcon#about to read 5, iclass 6, count 2 2006.246.08:03:52.45#ibcon#read 5, iclass 6, count 2 2006.246.08:03:52.45#ibcon#about to read 6, iclass 6, count 2 2006.246.08:03:52.45#ibcon#read 6, iclass 6, count 2 2006.246.08:03:52.45#ibcon#end of sib2, iclass 6, count 2 2006.246.08:03:52.45#ibcon#*after write, iclass 6, count 2 2006.246.08:03:52.45#ibcon#*before return 0, iclass 6, count 2 2006.246.08:03:52.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:52.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:03:52.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.08:03:52.45#ibcon#ireg 7 cls_cnt 0 2006.246.08:03:52.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:52.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:52.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:52.57#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:03:52.57#ibcon#first serial, iclass 6, count 0 2006.246.08:03:52.57#ibcon#enter sib2, iclass 6, count 0 2006.246.08:03:52.57#ibcon#flushed, iclass 6, count 0 2006.246.08:03:52.57#ibcon#about to write, iclass 6, count 0 2006.246.08:03:52.57#ibcon#wrote, iclass 6, count 0 2006.246.08:03:52.57#ibcon#about to read 3, iclass 6, count 0 2006.246.08:03:52.59#ibcon#read 3, iclass 6, count 0 2006.246.08:03:52.59#ibcon#about to read 4, iclass 6, count 0 2006.246.08:03:52.59#ibcon#read 4, iclass 6, count 0 2006.246.08:03:52.59#ibcon#about to read 5, iclass 6, count 0 2006.246.08:03:52.59#ibcon#read 5, iclass 6, count 0 2006.246.08:03:52.59#ibcon#about to read 6, iclass 6, count 0 2006.246.08:03:52.59#ibcon#read 6, iclass 6, count 0 2006.246.08:03:52.59#ibcon#end of sib2, iclass 6, count 0 2006.246.08:03:52.59#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:03:52.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:03:52.59#ibcon#[27=USB\r\n] 2006.246.08:03:52.59#ibcon#*before write, iclass 6, count 0 2006.246.08:03:52.59#ibcon#enter sib2, iclass 6, count 0 2006.246.08:03:52.59#ibcon#flushed, iclass 6, count 0 2006.246.08:03:52.59#ibcon#about to write, iclass 6, count 0 2006.246.08:03:52.59#ibcon#wrote, iclass 6, count 0 2006.246.08:03:52.59#ibcon#about to read 3, iclass 6, count 0 2006.246.08:03:52.62#ibcon#read 3, iclass 6, count 0 2006.246.08:03:52.62#ibcon#about to read 4, iclass 6, count 0 2006.246.08:03:52.62#ibcon#read 4, iclass 6, count 0 2006.246.08:03:52.62#ibcon#about to read 5, iclass 6, count 0 2006.246.08:03:52.62#ibcon#read 5, iclass 6, count 0 2006.246.08:03:52.62#ibcon#about to read 6, iclass 6, count 0 2006.246.08:03:52.62#ibcon#read 6, iclass 6, count 0 2006.246.08:03:52.62#ibcon#end of sib2, iclass 6, count 0 2006.246.08:03:52.62#ibcon#*after write, iclass 6, count 0 2006.246.08:03:52.62#ibcon#*before return 0, iclass 6, count 0 2006.246.08:03:52.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:52.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:03:52.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:03:52.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:03:52.62$vc4f8/vabw=wide 2006.246.08:03:52.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.08:03:52.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.08:03:52.62#ibcon#ireg 8 cls_cnt 0 2006.246.08:03:52.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:52.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:52.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:52.62#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:03:52.62#ibcon#first serial, iclass 10, count 0 2006.246.08:03:52.62#ibcon#enter sib2, iclass 10, count 0 2006.246.08:03:52.62#ibcon#flushed, iclass 10, count 0 2006.246.08:03:52.62#ibcon#about to write, iclass 10, count 0 2006.246.08:03:52.62#ibcon#wrote, iclass 10, count 0 2006.246.08:03:52.62#ibcon#about to read 3, iclass 10, count 0 2006.246.08:03:52.64#ibcon#read 3, iclass 10, count 0 2006.246.08:03:52.64#ibcon#about to read 4, iclass 10, count 0 2006.246.08:03:52.64#ibcon#read 4, iclass 10, count 0 2006.246.08:03:52.64#ibcon#about to read 5, iclass 10, count 0 2006.246.08:03:52.64#ibcon#read 5, iclass 10, count 0 2006.246.08:03:52.64#ibcon#about to read 6, iclass 10, count 0 2006.246.08:03:52.64#ibcon#read 6, iclass 10, count 0 2006.246.08:03:52.64#ibcon#end of sib2, iclass 10, count 0 2006.246.08:03:52.64#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:03:52.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:03:52.64#ibcon#[25=BW32\r\n] 2006.246.08:03:52.64#ibcon#*before write, iclass 10, count 0 2006.246.08:03:52.64#ibcon#enter sib2, iclass 10, count 0 2006.246.08:03:52.64#ibcon#flushed, iclass 10, count 0 2006.246.08:03:52.64#ibcon#about to write, iclass 10, count 0 2006.246.08:03:52.64#ibcon#wrote, iclass 10, count 0 2006.246.08:03:52.64#ibcon#about to read 3, iclass 10, count 0 2006.246.08:03:52.67#ibcon#read 3, iclass 10, count 0 2006.246.08:03:52.67#ibcon#about to read 4, iclass 10, count 0 2006.246.08:03:52.67#ibcon#read 4, iclass 10, count 0 2006.246.08:03:52.67#ibcon#about to read 5, iclass 10, count 0 2006.246.08:03:52.67#ibcon#read 5, iclass 10, count 0 2006.246.08:03:52.67#ibcon#about to read 6, iclass 10, count 0 2006.246.08:03:52.67#ibcon#read 6, iclass 10, count 0 2006.246.08:03:52.67#ibcon#end of sib2, iclass 10, count 0 2006.246.08:03:52.67#ibcon#*after write, iclass 10, count 0 2006.246.08:03:52.67#ibcon#*before return 0, iclass 10, count 0 2006.246.08:03:52.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:52.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:03:52.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:03:52.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:03:52.67$vc4f8/vbbw=wide 2006.246.08:03:52.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.08:03:52.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.08:03:52.67#ibcon#ireg 8 cls_cnt 0 2006.246.08:03:52.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:03:52.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:03:52.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:03:52.74#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:03:52.74#ibcon#first serial, iclass 12, count 0 2006.246.08:03:52.74#ibcon#enter sib2, iclass 12, count 0 2006.246.08:03:52.74#ibcon#flushed, iclass 12, count 0 2006.246.08:03:52.74#ibcon#about to write, iclass 12, count 0 2006.246.08:03:52.74#ibcon#wrote, iclass 12, count 0 2006.246.08:03:52.74#ibcon#about to read 3, iclass 12, count 0 2006.246.08:03:52.76#ibcon#read 3, iclass 12, count 0 2006.246.08:03:52.76#ibcon#about to read 4, iclass 12, count 0 2006.246.08:03:52.76#ibcon#read 4, iclass 12, count 0 2006.246.08:03:52.76#ibcon#about to read 5, iclass 12, count 0 2006.246.08:03:52.76#ibcon#read 5, iclass 12, count 0 2006.246.08:03:52.76#ibcon#about to read 6, iclass 12, count 0 2006.246.08:03:52.76#ibcon#read 6, iclass 12, count 0 2006.246.08:03:52.76#ibcon#end of sib2, iclass 12, count 0 2006.246.08:03:52.76#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:03:52.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:03:52.76#ibcon#[27=BW32\r\n] 2006.246.08:03:52.76#ibcon#*before write, iclass 12, count 0 2006.246.08:03:52.76#ibcon#enter sib2, iclass 12, count 0 2006.246.08:03:52.76#ibcon#flushed, iclass 12, count 0 2006.246.08:03:52.76#ibcon#about to write, iclass 12, count 0 2006.246.08:03:52.76#ibcon#wrote, iclass 12, count 0 2006.246.08:03:52.76#ibcon#about to read 3, iclass 12, count 0 2006.246.08:03:52.79#ibcon#read 3, iclass 12, count 0 2006.246.08:03:52.79#ibcon#about to read 4, iclass 12, count 0 2006.246.08:03:52.79#ibcon#read 4, iclass 12, count 0 2006.246.08:03:52.79#ibcon#about to read 5, iclass 12, count 0 2006.246.08:03:52.79#ibcon#read 5, iclass 12, count 0 2006.246.08:03:52.79#ibcon#about to read 6, iclass 12, count 0 2006.246.08:03:52.79#ibcon#read 6, iclass 12, count 0 2006.246.08:03:52.79#ibcon#end of sib2, iclass 12, count 0 2006.246.08:03:52.79#ibcon#*after write, iclass 12, count 0 2006.246.08:03:52.79#ibcon#*before return 0, iclass 12, count 0 2006.246.08:03:52.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:03:52.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:03:52.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:03:52.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:03:52.79$4f8m12a/ifd4f 2006.246.08:03:52.79$ifd4f/lo= 2006.246.08:03:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:03:52.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:03:52.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:03:52.79$ifd4f/patch= 2006.246.08:03:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:03:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:03:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:03:52.79$4f8m12a/"form=m,16.000,1:2 2006.246.08:03:52.79$4f8m12a/"tpicd 2006.246.08:03:52.79$4f8m12a/echo=off 2006.246.08:03:52.79$4f8m12a/xlog=off 2006.246.08:03:52.79:!2006.246.08:04:20 2006.246.08:04:01.14#trakl#Source acquired 2006.246.08:04:02.14#flagr#flagr/antenna,acquired 2006.246.08:04:20.00:preob 2006.246.08:04:21.14/onsource/TRACKING 2006.246.08:04:21.14:!2006.246.08:04:30 2006.246.08:04:30.00:data_valid=on 2006.246.08:04:30.00:midob 2006.246.08:04:30.14/onsource/TRACKING 2006.246.08:04:30.14/wx/26.54,1005.7,74 2006.246.08:04:30.30/cable/+6.4140E-03 2006.246.08:04:31.39/va/01,08,usb,yes,31,32 2006.246.08:04:31.39/va/02,07,usb,yes,31,32 2006.246.08:04:31.39/va/03,06,usb,yes,33,33 2006.246.08:04:31.39/va/04,07,usb,yes,32,34 2006.246.08:04:31.39/va/05,07,usb,yes,34,35 2006.246.08:04:31.39/va/06,07,usb,yes,29,29 2006.246.08:04:31.39/va/07,07,usb,yes,29,29 2006.246.08:04:31.39/va/08,08,usb,yes,25,25 2006.246.08:04:31.62/valo/01,532.99,yes,locked 2006.246.08:04:31.62/valo/02,572.99,yes,locked 2006.246.08:04:31.62/valo/03,672.99,yes,locked 2006.246.08:04:31.62/valo/04,832.99,yes,locked 2006.246.08:04:31.62/valo/05,652.99,yes,locked 2006.246.08:04:31.62/valo/06,772.99,yes,locked 2006.246.08:04:31.62/valo/07,832.99,yes,locked 2006.246.08:04:31.62/valo/08,852.99,yes,locked 2006.246.08:04:32.71/vb/01,04,usb,yes,30,29 2006.246.08:04:32.71/vb/02,04,usb,yes,32,34 2006.246.08:04:32.71/vb/03,04,usb,yes,28,32 2006.246.08:04:32.71/vb/04,04,usb,yes,29,29 2006.246.08:04:32.71/vb/05,03,usb,yes,35,39 2006.246.08:04:32.71/vb/06,03,usb,yes,35,39 2006.246.08:04:32.71/vb/07,04,usb,yes,31,31 2006.246.08:04:32.71/vb/08,03,usb,yes,35,39 2006.246.08:04:32.94/vblo/01,632.99,yes,locked 2006.246.08:04:32.94/vblo/02,640.99,yes,locked 2006.246.08:04:32.94/vblo/03,656.99,yes,locked 2006.246.08:04:32.94/vblo/04,712.99,yes,locked 2006.246.08:04:32.94/vblo/05,744.99,yes,locked 2006.246.08:04:32.94/vblo/06,752.99,yes,locked 2006.246.08:04:32.94/vblo/07,734.99,yes,locked 2006.246.08:04:32.94/vblo/08,744.99,yes,locked 2006.246.08:04:33.09/vabw/8 2006.246.08:04:33.24/vbbw/8 2006.246.08:04:33.35/xfe/off,on,13.2 2006.246.08:04:33.73/ifatt/23,28,28,28 2006.246.08:04:34.08/fmout-gps/S +4.40E-07 2006.246.08:04:34.12:!2006.246.08:05:30 2006.246.08:05:30.00:data_valid=off 2006.246.08:05:30.00:postob 2006.246.08:05:30.18/cable/+6.4139E-03 2006.246.08:05:30.18/wx/26.52,1005.7,75 2006.246.08:05:31.08/fmout-gps/S +4.41E-07 2006.246.08:05:31.08:scan_name=246-0806,k06246,60 2006.246.08:05:31.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.246.08:05:31.14#flagr#flagr/antenna,new-source 2006.246.08:05:32.14:checkk5 2006.246.08:05:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:05:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:05:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:05:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:05:34.00/chk_obsdata//k5ts1/T2460804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:05:34.37/chk_obsdata//k5ts2/T2460804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:05:34.74/chk_obsdata//k5ts3/T2460804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:05:35.11/chk_obsdata//k5ts4/T2460804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:05:35.80/k5log//k5ts1_log_newline 2006.246.08:05:36.49/k5log//k5ts2_log_newline 2006.246.08:05:37.18/k5log//k5ts3_log_newline 2006.246.08:05:37.86/k5log//k5ts4_log_newline 2006.246.08:05:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:05:37.89:4f8m12a=2 2006.246.08:05:37.89$4f8m12a/echo=on 2006.246.08:05:37.89$4f8m12a/pcalon 2006.246.08:05:37.89$pcalon/"no phase cal control is implemented here 2006.246.08:05:37.89$4f8m12a/"tpicd=stop 2006.246.08:05:37.89$4f8m12a/vc4f8 2006.246.08:05:37.89$vc4f8/valo=1,532.99 2006.246.08:05:37.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.08:05:37.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.08:05:37.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:37.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:37.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:37.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:37.89#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:05:37.89#ibcon#first serial, iclass 19, count 0 2006.246.08:05:37.89#ibcon#enter sib2, iclass 19, count 0 2006.246.08:05:37.89#ibcon#flushed, iclass 19, count 0 2006.246.08:05:37.89#ibcon#about to write, iclass 19, count 0 2006.246.08:05:37.89#ibcon#wrote, iclass 19, count 0 2006.246.08:05:37.89#ibcon#about to read 3, iclass 19, count 0 2006.246.08:05:37.93#ibcon#read 3, iclass 19, count 0 2006.246.08:05:37.93#ibcon#about to read 4, iclass 19, count 0 2006.246.08:05:37.93#ibcon#read 4, iclass 19, count 0 2006.246.08:05:37.93#ibcon#about to read 5, iclass 19, count 0 2006.246.08:05:37.93#ibcon#read 5, iclass 19, count 0 2006.246.08:05:37.93#ibcon#about to read 6, iclass 19, count 0 2006.246.08:05:37.93#ibcon#read 6, iclass 19, count 0 2006.246.08:05:37.93#ibcon#end of sib2, iclass 19, count 0 2006.246.08:05:37.93#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:05:37.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:05:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:05:37.93#ibcon#*before write, iclass 19, count 0 2006.246.08:05:37.93#ibcon#enter sib2, iclass 19, count 0 2006.246.08:05:37.93#ibcon#flushed, iclass 19, count 0 2006.246.08:05:37.93#ibcon#about to write, iclass 19, count 0 2006.246.08:05:37.93#ibcon#wrote, iclass 19, count 0 2006.246.08:05:37.93#ibcon#about to read 3, iclass 19, count 0 2006.246.08:05:37.98#ibcon#read 3, iclass 19, count 0 2006.246.08:05:37.98#ibcon#about to read 4, iclass 19, count 0 2006.246.08:05:37.98#ibcon#read 4, iclass 19, count 0 2006.246.08:05:37.98#ibcon#about to read 5, iclass 19, count 0 2006.246.08:05:37.98#ibcon#read 5, iclass 19, count 0 2006.246.08:05:37.98#ibcon#about to read 6, iclass 19, count 0 2006.246.08:05:37.98#ibcon#read 6, iclass 19, count 0 2006.246.08:05:37.98#ibcon#end of sib2, iclass 19, count 0 2006.246.08:05:37.98#ibcon#*after write, iclass 19, count 0 2006.246.08:05:37.98#ibcon#*before return 0, iclass 19, count 0 2006.246.08:05:37.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:37.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:37.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:05:37.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:05:37.98$vc4f8/va=1,8 2006.246.08:05:37.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.08:05:37.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.08:05:37.98#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:37.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:37.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:37.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:37.98#ibcon#enter wrdev, iclass 21, count 2 2006.246.08:05:37.98#ibcon#first serial, iclass 21, count 2 2006.246.08:05:37.98#ibcon#enter sib2, iclass 21, count 2 2006.246.08:05:37.98#ibcon#flushed, iclass 21, count 2 2006.246.08:05:37.98#ibcon#about to write, iclass 21, count 2 2006.246.08:05:37.98#ibcon#wrote, iclass 21, count 2 2006.246.08:05:37.98#ibcon#about to read 3, iclass 21, count 2 2006.246.08:05:38.00#ibcon#read 3, iclass 21, count 2 2006.246.08:05:38.00#ibcon#about to read 4, iclass 21, count 2 2006.246.08:05:38.00#ibcon#read 4, iclass 21, count 2 2006.246.08:05:38.00#ibcon#about to read 5, iclass 21, count 2 2006.246.08:05:38.00#ibcon#read 5, iclass 21, count 2 2006.246.08:05:38.00#ibcon#about to read 6, iclass 21, count 2 2006.246.08:05:38.00#ibcon#read 6, iclass 21, count 2 2006.246.08:05:38.00#ibcon#end of sib2, iclass 21, count 2 2006.246.08:05:38.00#ibcon#*mode == 0, iclass 21, count 2 2006.246.08:05:38.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.08:05:38.00#ibcon#[25=AT01-08\r\n] 2006.246.08:05:38.00#ibcon#*before write, iclass 21, count 2 2006.246.08:05:38.00#ibcon#enter sib2, iclass 21, count 2 2006.246.08:05:38.00#ibcon#flushed, iclass 21, count 2 2006.246.08:05:38.00#ibcon#about to write, iclass 21, count 2 2006.246.08:05:38.00#ibcon#wrote, iclass 21, count 2 2006.246.08:05:38.00#ibcon#about to read 3, iclass 21, count 2 2006.246.08:05:38.03#ibcon#read 3, iclass 21, count 2 2006.246.08:05:38.03#ibcon#about to read 4, iclass 21, count 2 2006.246.08:05:38.03#ibcon#read 4, iclass 21, count 2 2006.246.08:05:38.03#ibcon#about to read 5, iclass 21, count 2 2006.246.08:05:38.03#ibcon#read 5, iclass 21, count 2 2006.246.08:05:38.03#ibcon#about to read 6, iclass 21, count 2 2006.246.08:05:38.03#ibcon#read 6, iclass 21, count 2 2006.246.08:05:38.03#ibcon#end of sib2, iclass 21, count 2 2006.246.08:05:38.03#ibcon#*after write, iclass 21, count 2 2006.246.08:05:38.03#ibcon#*before return 0, iclass 21, count 2 2006.246.08:05:38.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:38.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:38.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.08:05:38.03#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:38.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:38.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:38.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:38.15#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:05:38.15#ibcon#first serial, iclass 21, count 0 2006.246.08:05:38.15#ibcon#enter sib2, iclass 21, count 0 2006.246.08:05:38.15#ibcon#flushed, iclass 21, count 0 2006.246.08:05:38.15#ibcon#about to write, iclass 21, count 0 2006.246.08:05:38.15#ibcon#wrote, iclass 21, count 0 2006.246.08:05:38.15#ibcon#about to read 3, iclass 21, count 0 2006.246.08:05:38.17#ibcon#read 3, iclass 21, count 0 2006.246.08:05:38.17#ibcon#about to read 4, iclass 21, count 0 2006.246.08:05:38.17#ibcon#read 4, iclass 21, count 0 2006.246.08:05:38.17#ibcon#about to read 5, iclass 21, count 0 2006.246.08:05:38.17#ibcon#read 5, iclass 21, count 0 2006.246.08:05:38.17#ibcon#about to read 6, iclass 21, count 0 2006.246.08:05:38.17#ibcon#read 6, iclass 21, count 0 2006.246.08:05:38.17#ibcon#end of sib2, iclass 21, count 0 2006.246.08:05:38.17#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:05:38.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:05:38.17#ibcon#[25=USB\r\n] 2006.246.08:05:38.17#ibcon#*before write, iclass 21, count 0 2006.246.08:05:38.17#ibcon#enter sib2, iclass 21, count 0 2006.246.08:05:38.17#ibcon#flushed, iclass 21, count 0 2006.246.08:05:38.17#ibcon#about to write, iclass 21, count 0 2006.246.08:05:38.17#ibcon#wrote, iclass 21, count 0 2006.246.08:05:38.17#ibcon#about to read 3, iclass 21, count 0 2006.246.08:05:38.20#ibcon#read 3, iclass 21, count 0 2006.246.08:05:38.20#ibcon#about to read 4, iclass 21, count 0 2006.246.08:05:38.20#ibcon#read 4, iclass 21, count 0 2006.246.08:05:38.20#ibcon#about to read 5, iclass 21, count 0 2006.246.08:05:38.20#ibcon#read 5, iclass 21, count 0 2006.246.08:05:38.20#ibcon#about to read 6, iclass 21, count 0 2006.246.08:05:38.20#ibcon#read 6, iclass 21, count 0 2006.246.08:05:38.20#ibcon#end of sib2, iclass 21, count 0 2006.246.08:05:38.20#ibcon#*after write, iclass 21, count 0 2006.246.08:05:38.20#ibcon#*before return 0, iclass 21, count 0 2006.246.08:05:38.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:38.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:38.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:05:38.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:05:38.20$vc4f8/valo=2,572.99 2006.246.08:05:38.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:05:38.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:05:38.20#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:38.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:38.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:38.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:38.20#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:05:38.20#ibcon#first serial, iclass 23, count 0 2006.246.08:05:38.20#ibcon#enter sib2, iclass 23, count 0 2006.246.08:05:38.20#ibcon#flushed, iclass 23, count 0 2006.246.08:05:38.20#ibcon#about to write, iclass 23, count 0 2006.246.08:05:38.20#ibcon#wrote, iclass 23, count 0 2006.246.08:05:38.20#ibcon#about to read 3, iclass 23, count 0 2006.246.08:05:38.22#ibcon#read 3, iclass 23, count 0 2006.246.08:05:38.22#ibcon#about to read 4, iclass 23, count 0 2006.246.08:05:38.22#ibcon#read 4, iclass 23, count 0 2006.246.08:05:38.22#ibcon#about to read 5, iclass 23, count 0 2006.246.08:05:38.22#ibcon#read 5, iclass 23, count 0 2006.246.08:05:38.22#ibcon#about to read 6, iclass 23, count 0 2006.246.08:05:38.22#ibcon#read 6, iclass 23, count 0 2006.246.08:05:38.22#ibcon#end of sib2, iclass 23, count 0 2006.246.08:05:38.22#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:05:38.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:05:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:05:38.22#ibcon#*before write, iclass 23, count 0 2006.246.08:05:38.22#ibcon#enter sib2, iclass 23, count 0 2006.246.08:05:38.22#ibcon#flushed, iclass 23, count 0 2006.246.08:05:38.22#ibcon#about to write, iclass 23, count 0 2006.246.08:05:38.22#ibcon#wrote, iclass 23, count 0 2006.246.08:05:38.22#ibcon#about to read 3, iclass 23, count 0 2006.246.08:05:38.26#ibcon#read 3, iclass 23, count 0 2006.246.08:05:38.26#ibcon#about to read 4, iclass 23, count 0 2006.246.08:05:38.26#ibcon#read 4, iclass 23, count 0 2006.246.08:05:38.26#ibcon#about to read 5, iclass 23, count 0 2006.246.08:05:38.26#ibcon#read 5, iclass 23, count 0 2006.246.08:05:38.26#ibcon#about to read 6, iclass 23, count 0 2006.246.08:05:38.26#ibcon#read 6, iclass 23, count 0 2006.246.08:05:38.26#ibcon#end of sib2, iclass 23, count 0 2006.246.08:05:38.26#ibcon#*after write, iclass 23, count 0 2006.246.08:05:38.26#ibcon#*before return 0, iclass 23, count 0 2006.246.08:05:38.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:38.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:38.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:05:38.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:05:38.26$vc4f8/va=2,7 2006.246.08:05:38.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:05:38.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:05:38.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:38.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:38.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:38.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:38.32#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:05:38.32#ibcon#first serial, iclass 25, count 2 2006.246.08:05:38.32#ibcon#enter sib2, iclass 25, count 2 2006.246.08:05:38.32#ibcon#flushed, iclass 25, count 2 2006.246.08:05:38.32#ibcon#about to write, iclass 25, count 2 2006.246.08:05:38.32#ibcon#wrote, iclass 25, count 2 2006.246.08:05:38.32#ibcon#about to read 3, iclass 25, count 2 2006.246.08:05:38.34#ibcon#read 3, iclass 25, count 2 2006.246.08:05:38.34#ibcon#about to read 4, iclass 25, count 2 2006.246.08:05:38.34#ibcon#read 4, iclass 25, count 2 2006.246.08:05:38.34#ibcon#about to read 5, iclass 25, count 2 2006.246.08:05:38.34#ibcon#read 5, iclass 25, count 2 2006.246.08:05:38.34#ibcon#about to read 6, iclass 25, count 2 2006.246.08:05:38.34#ibcon#read 6, iclass 25, count 2 2006.246.08:05:38.34#ibcon#end of sib2, iclass 25, count 2 2006.246.08:05:38.34#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:05:38.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:05:38.34#ibcon#[25=AT02-07\r\n] 2006.246.08:05:38.34#ibcon#*before write, iclass 25, count 2 2006.246.08:05:38.34#ibcon#enter sib2, iclass 25, count 2 2006.246.08:05:38.34#ibcon#flushed, iclass 25, count 2 2006.246.08:05:38.34#ibcon#about to write, iclass 25, count 2 2006.246.08:05:38.34#ibcon#wrote, iclass 25, count 2 2006.246.08:05:38.34#ibcon#about to read 3, iclass 25, count 2 2006.246.08:05:38.37#ibcon#read 3, iclass 25, count 2 2006.246.08:05:38.37#ibcon#about to read 4, iclass 25, count 2 2006.246.08:05:38.37#ibcon#read 4, iclass 25, count 2 2006.246.08:05:38.37#ibcon#about to read 5, iclass 25, count 2 2006.246.08:05:38.37#ibcon#read 5, iclass 25, count 2 2006.246.08:05:38.37#ibcon#about to read 6, iclass 25, count 2 2006.246.08:05:38.37#ibcon#read 6, iclass 25, count 2 2006.246.08:05:38.37#ibcon#end of sib2, iclass 25, count 2 2006.246.08:05:38.37#ibcon#*after write, iclass 25, count 2 2006.246.08:05:38.37#ibcon#*before return 0, iclass 25, count 2 2006.246.08:05:38.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:38.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:38.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:05:38.37#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:38.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:38.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:38.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:38.49#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:05:38.49#ibcon#first serial, iclass 25, count 0 2006.246.08:05:38.49#ibcon#enter sib2, iclass 25, count 0 2006.246.08:05:38.49#ibcon#flushed, iclass 25, count 0 2006.246.08:05:38.49#ibcon#about to write, iclass 25, count 0 2006.246.08:05:38.49#ibcon#wrote, iclass 25, count 0 2006.246.08:05:38.49#ibcon#about to read 3, iclass 25, count 0 2006.246.08:05:38.51#ibcon#read 3, iclass 25, count 0 2006.246.08:05:38.51#ibcon#about to read 4, iclass 25, count 0 2006.246.08:05:38.51#ibcon#read 4, iclass 25, count 0 2006.246.08:05:38.51#ibcon#about to read 5, iclass 25, count 0 2006.246.08:05:38.51#ibcon#read 5, iclass 25, count 0 2006.246.08:05:38.51#ibcon#about to read 6, iclass 25, count 0 2006.246.08:05:38.51#ibcon#read 6, iclass 25, count 0 2006.246.08:05:38.51#ibcon#end of sib2, iclass 25, count 0 2006.246.08:05:38.51#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:05:38.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:05:38.51#ibcon#[25=USB\r\n] 2006.246.08:05:38.51#ibcon#*before write, iclass 25, count 0 2006.246.08:05:38.51#ibcon#enter sib2, iclass 25, count 0 2006.246.08:05:38.51#ibcon#flushed, iclass 25, count 0 2006.246.08:05:38.51#ibcon#about to write, iclass 25, count 0 2006.246.08:05:38.51#ibcon#wrote, iclass 25, count 0 2006.246.08:05:38.51#ibcon#about to read 3, iclass 25, count 0 2006.246.08:05:38.54#ibcon#read 3, iclass 25, count 0 2006.246.08:05:38.54#ibcon#about to read 4, iclass 25, count 0 2006.246.08:05:38.54#ibcon#read 4, iclass 25, count 0 2006.246.08:05:38.54#ibcon#about to read 5, iclass 25, count 0 2006.246.08:05:38.54#ibcon#read 5, iclass 25, count 0 2006.246.08:05:38.54#ibcon#about to read 6, iclass 25, count 0 2006.246.08:05:38.54#ibcon#read 6, iclass 25, count 0 2006.246.08:05:38.54#ibcon#end of sib2, iclass 25, count 0 2006.246.08:05:38.54#ibcon#*after write, iclass 25, count 0 2006.246.08:05:38.54#ibcon#*before return 0, iclass 25, count 0 2006.246.08:05:38.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:38.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:38.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:05:38.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:05:38.54$vc4f8/valo=3,672.99 2006.246.08:05:38.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:05:38.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:05:38.54#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:38.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:38.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:38.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:38.54#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:05:38.54#ibcon#first serial, iclass 27, count 0 2006.246.08:05:38.54#ibcon#enter sib2, iclass 27, count 0 2006.246.08:05:38.54#ibcon#flushed, iclass 27, count 0 2006.246.08:05:38.54#ibcon#about to write, iclass 27, count 0 2006.246.08:05:38.54#ibcon#wrote, iclass 27, count 0 2006.246.08:05:38.54#ibcon#about to read 3, iclass 27, count 0 2006.246.08:05:38.56#ibcon#read 3, iclass 27, count 0 2006.246.08:05:38.56#ibcon#about to read 4, iclass 27, count 0 2006.246.08:05:38.56#ibcon#read 4, iclass 27, count 0 2006.246.08:05:38.56#ibcon#about to read 5, iclass 27, count 0 2006.246.08:05:38.56#ibcon#read 5, iclass 27, count 0 2006.246.08:05:38.56#ibcon#about to read 6, iclass 27, count 0 2006.246.08:05:38.56#ibcon#read 6, iclass 27, count 0 2006.246.08:05:38.56#ibcon#end of sib2, iclass 27, count 0 2006.246.08:05:38.56#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:05:38.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:05:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:05:38.56#ibcon#*before write, iclass 27, count 0 2006.246.08:05:38.56#ibcon#enter sib2, iclass 27, count 0 2006.246.08:05:38.56#ibcon#flushed, iclass 27, count 0 2006.246.08:05:38.56#ibcon#about to write, iclass 27, count 0 2006.246.08:05:38.56#ibcon#wrote, iclass 27, count 0 2006.246.08:05:38.56#ibcon#about to read 3, iclass 27, count 0 2006.246.08:05:38.60#ibcon#read 3, iclass 27, count 0 2006.246.08:05:38.60#ibcon#about to read 4, iclass 27, count 0 2006.246.08:05:38.60#ibcon#read 4, iclass 27, count 0 2006.246.08:05:38.60#ibcon#about to read 5, iclass 27, count 0 2006.246.08:05:38.60#ibcon#read 5, iclass 27, count 0 2006.246.08:05:38.60#ibcon#about to read 6, iclass 27, count 0 2006.246.08:05:38.60#ibcon#read 6, iclass 27, count 0 2006.246.08:05:38.60#ibcon#end of sib2, iclass 27, count 0 2006.246.08:05:38.60#ibcon#*after write, iclass 27, count 0 2006.246.08:05:38.60#ibcon#*before return 0, iclass 27, count 0 2006.246.08:05:38.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:38.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:38.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:05:38.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:05:38.60$vc4f8/va=3,6 2006.246.08:05:38.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:05:38.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:05:38.60#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:38.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:38.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:38.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:38.66#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:05:38.66#ibcon#first serial, iclass 29, count 2 2006.246.08:05:38.66#ibcon#enter sib2, iclass 29, count 2 2006.246.08:05:38.66#ibcon#flushed, iclass 29, count 2 2006.246.08:05:38.66#ibcon#about to write, iclass 29, count 2 2006.246.08:05:38.66#ibcon#wrote, iclass 29, count 2 2006.246.08:05:38.66#ibcon#about to read 3, iclass 29, count 2 2006.246.08:05:38.68#ibcon#read 3, iclass 29, count 2 2006.246.08:05:38.68#ibcon#about to read 4, iclass 29, count 2 2006.246.08:05:38.68#ibcon#read 4, iclass 29, count 2 2006.246.08:05:38.68#ibcon#about to read 5, iclass 29, count 2 2006.246.08:05:38.68#ibcon#read 5, iclass 29, count 2 2006.246.08:05:38.68#ibcon#about to read 6, iclass 29, count 2 2006.246.08:05:38.68#ibcon#read 6, iclass 29, count 2 2006.246.08:05:38.68#ibcon#end of sib2, iclass 29, count 2 2006.246.08:05:38.68#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:05:38.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:05:38.68#ibcon#[25=AT03-06\r\n] 2006.246.08:05:38.68#ibcon#*before write, iclass 29, count 2 2006.246.08:05:38.68#ibcon#enter sib2, iclass 29, count 2 2006.246.08:05:38.68#ibcon#flushed, iclass 29, count 2 2006.246.08:05:38.68#ibcon#about to write, iclass 29, count 2 2006.246.08:05:38.68#ibcon#wrote, iclass 29, count 2 2006.246.08:05:38.68#ibcon#about to read 3, iclass 29, count 2 2006.246.08:05:38.72#ibcon#read 3, iclass 29, count 2 2006.246.08:05:38.72#ibcon#about to read 4, iclass 29, count 2 2006.246.08:05:38.72#ibcon#read 4, iclass 29, count 2 2006.246.08:05:38.72#ibcon#about to read 5, iclass 29, count 2 2006.246.08:05:38.72#ibcon#read 5, iclass 29, count 2 2006.246.08:05:38.72#ibcon#about to read 6, iclass 29, count 2 2006.246.08:05:38.72#ibcon#read 6, iclass 29, count 2 2006.246.08:05:38.72#ibcon#end of sib2, iclass 29, count 2 2006.246.08:05:38.72#ibcon#*after write, iclass 29, count 2 2006.246.08:05:38.72#ibcon#*before return 0, iclass 29, count 2 2006.246.08:05:38.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:38.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:38.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:05:38.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:38.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:38.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:38.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:38.84#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:05:38.84#ibcon#first serial, iclass 29, count 0 2006.246.08:05:38.84#ibcon#enter sib2, iclass 29, count 0 2006.246.08:05:38.84#ibcon#flushed, iclass 29, count 0 2006.246.08:05:38.84#ibcon#about to write, iclass 29, count 0 2006.246.08:05:38.84#ibcon#wrote, iclass 29, count 0 2006.246.08:05:38.84#ibcon#about to read 3, iclass 29, count 0 2006.246.08:05:38.86#ibcon#read 3, iclass 29, count 0 2006.246.08:05:38.86#ibcon#about to read 4, iclass 29, count 0 2006.246.08:05:38.86#ibcon#read 4, iclass 29, count 0 2006.246.08:05:38.86#ibcon#about to read 5, iclass 29, count 0 2006.246.08:05:38.86#ibcon#read 5, iclass 29, count 0 2006.246.08:05:38.86#ibcon#about to read 6, iclass 29, count 0 2006.246.08:05:38.86#ibcon#read 6, iclass 29, count 0 2006.246.08:05:38.86#ibcon#end of sib2, iclass 29, count 0 2006.246.08:05:38.86#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:05:38.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:05:38.86#ibcon#[25=USB\r\n] 2006.246.08:05:38.86#ibcon#*before write, iclass 29, count 0 2006.246.08:05:38.86#ibcon#enter sib2, iclass 29, count 0 2006.246.08:05:38.86#ibcon#flushed, iclass 29, count 0 2006.246.08:05:38.86#ibcon#about to write, iclass 29, count 0 2006.246.08:05:38.86#ibcon#wrote, iclass 29, count 0 2006.246.08:05:38.86#ibcon#about to read 3, iclass 29, count 0 2006.246.08:05:38.89#ibcon#read 3, iclass 29, count 0 2006.246.08:05:38.89#ibcon#about to read 4, iclass 29, count 0 2006.246.08:05:38.89#ibcon#read 4, iclass 29, count 0 2006.246.08:05:38.89#ibcon#about to read 5, iclass 29, count 0 2006.246.08:05:38.89#ibcon#read 5, iclass 29, count 0 2006.246.08:05:38.89#ibcon#about to read 6, iclass 29, count 0 2006.246.08:05:38.89#ibcon#read 6, iclass 29, count 0 2006.246.08:05:38.89#ibcon#end of sib2, iclass 29, count 0 2006.246.08:05:38.89#ibcon#*after write, iclass 29, count 0 2006.246.08:05:38.89#ibcon#*before return 0, iclass 29, count 0 2006.246.08:05:38.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:38.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:38.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:05:38.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:05:38.89$vc4f8/valo=4,832.99 2006.246.08:05:38.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:05:38.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:05:38.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:38.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:38.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:38.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:38.89#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:05:38.89#ibcon#first serial, iclass 31, count 0 2006.246.08:05:38.89#ibcon#enter sib2, iclass 31, count 0 2006.246.08:05:38.89#ibcon#flushed, iclass 31, count 0 2006.246.08:05:38.89#ibcon#about to write, iclass 31, count 0 2006.246.08:05:38.89#ibcon#wrote, iclass 31, count 0 2006.246.08:05:38.89#ibcon#about to read 3, iclass 31, count 0 2006.246.08:05:38.91#ibcon#read 3, iclass 31, count 0 2006.246.08:05:38.91#ibcon#about to read 4, iclass 31, count 0 2006.246.08:05:38.91#ibcon#read 4, iclass 31, count 0 2006.246.08:05:38.91#ibcon#about to read 5, iclass 31, count 0 2006.246.08:05:38.91#ibcon#read 5, iclass 31, count 0 2006.246.08:05:38.91#ibcon#about to read 6, iclass 31, count 0 2006.246.08:05:38.91#ibcon#read 6, iclass 31, count 0 2006.246.08:05:38.91#ibcon#end of sib2, iclass 31, count 0 2006.246.08:05:38.91#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:05:38.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:05:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:05:38.91#ibcon#*before write, iclass 31, count 0 2006.246.08:05:38.91#ibcon#enter sib2, iclass 31, count 0 2006.246.08:05:38.91#ibcon#flushed, iclass 31, count 0 2006.246.08:05:38.91#ibcon#about to write, iclass 31, count 0 2006.246.08:05:38.91#ibcon#wrote, iclass 31, count 0 2006.246.08:05:38.91#ibcon#about to read 3, iclass 31, count 0 2006.246.08:05:38.95#ibcon#read 3, iclass 31, count 0 2006.246.08:05:38.95#ibcon#about to read 4, iclass 31, count 0 2006.246.08:05:38.95#ibcon#read 4, iclass 31, count 0 2006.246.08:05:38.95#ibcon#about to read 5, iclass 31, count 0 2006.246.08:05:38.95#ibcon#read 5, iclass 31, count 0 2006.246.08:05:38.95#ibcon#about to read 6, iclass 31, count 0 2006.246.08:05:38.95#ibcon#read 6, iclass 31, count 0 2006.246.08:05:38.95#ibcon#end of sib2, iclass 31, count 0 2006.246.08:05:38.95#ibcon#*after write, iclass 31, count 0 2006.246.08:05:38.95#ibcon#*before return 0, iclass 31, count 0 2006.246.08:05:38.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:38.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:38.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:05:38.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:05:38.95$vc4f8/va=4,7 2006.246.08:05:38.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:05:38.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:05:38.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:38.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:39.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:39.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:39.01#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:05:39.01#ibcon#first serial, iclass 33, count 2 2006.246.08:05:39.01#ibcon#enter sib2, iclass 33, count 2 2006.246.08:05:39.01#ibcon#flushed, iclass 33, count 2 2006.246.08:05:39.01#ibcon#about to write, iclass 33, count 2 2006.246.08:05:39.01#ibcon#wrote, iclass 33, count 2 2006.246.08:05:39.01#ibcon#about to read 3, iclass 33, count 2 2006.246.08:05:39.03#ibcon#read 3, iclass 33, count 2 2006.246.08:05:39.03#ibcon#about to read 4, iclass 33, count 2 2006.246.08:05:39.03#ibcon#read 4, iclass 33, count 2 2006.246.08:05:39.03#ibcon#about to read 5, iclass 33, count 2 2006.246.08:05:39.03#ibcon#read 5, iclass 33, count 2 2006.246.08:05:39.03#ibcon#about to read 6, iclass 33, count 2 2006.246.08:05:39.03#ibcon#read 6, iclass 33, count 2 2006.246.08:05:39.03#ibcon#end of sib2, iclass 33, count 2 2006.246.08:05:39.03#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:05:39.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:05:39.03#ibcon#[25=AT04-07\r\n] 2006.246.08:05:39.03#ibcon#*before write, iclass 33, count 2 2006.246.08:05:39.03#ibcon#enter sib2, iclass 33, count 2 2006.246.08:05:39.03#ibcon#flushed, iclass 33, count 2 2006.246.08:05:39.03#ibcon#about to write, iclass 33, count 2 2006.246.08:05:39.03#ibcon#wrote, iclass 33, count 2 2006.246.08:05:39.03#ibcon#about to read 3, iclass 33, count 2 2006.246.08:05:39.06#ibcon#read 3, iclass 33, count 2 2006.246.08:05:39.06#ibcon#about to read 4, iclass 33, count 2 2006.246.08:05:39.06#ibcon#read 4, iclass 33, count 2 2006.246.08:05:39.06#ibcon#about to read 5, iclass 33, count 2 2006.246.08:05:39.06#ibcon#read 5, iclass 33, count 2 2006.246.08:05:39.06#ibcon#about to read 6, iclass 33, count 2 2006.246.08:05:39.06#ibcon#read 6, iclass 33, count 2 2006.246.08:05:39.06#ibcon#end of sib2, iclass 33, count 2 2006.246.08:05:39.06#ibcon#*after write, iclass 33, count 2 2006.246.08:05:39.06#ibcon#*before return 0, iclass 33, count 2 2006.246.08:05:39.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:39.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:39.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:05:39.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:39.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:39.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:39.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:39.18#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:05:39.18#ibcon#first serial, iclass 33, count 0 2006.246.08:05:39.18#ibcon#enter sib2, iclass 33, count 0 2006.246.08:05:39.18#ibcon#flushed, iclass 33, count 0 2006.246.08:05:39.18#ibcon#about to write, iclass 33, count 0 2006.246.08:05:39.18#ibcon#wrote, iclass 33, count 0 2006.246.08:05:39.18#ibcon#about to read 3, iclass 33, count 0 2006.246.08:05:39.20#ibcon#read 3, iclass 33, count 0 2006.246.08:05:39.20#ibcon#about to read 4, iclass 33, count 0 2006.246.08:05:39.20#ibcon#read 4, iclass 33, count 0 2006.246.08:05:39.20#ibcon#about to read 5, iclass 33, count 0 2006.246.08:05:39.20#ibcon#read 5, iclass 33, count 0 2006.246.08:05:39.20#ibcon#about to read 6, iclass 33, count 0 2006.246.08:05:39.20#ibcon#read 6, iclass 33, count 0 2006.246.08:05:39.20#ibcon#end of sib2, iclass 33, count 0 2006.246.08:05:39.20#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:05:39.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:05:39.20#ibcon#[25=USB\r\n] 2006.246.08:05:39.20#ibcon#*before write, iclass 33, count 0 2006.246.08:05:39.20#ibcon#enter sib2, iclass 33, count 0 2006.246.08:05:39.20#ibcon#flushed, iclass 33, count 0 2006.246.08:05:39.20#ibcon#about to write, iclass 33, count 0 2006.246.08:05:39.20#ibcon#wrote, iclass 33, count 0 2006.246.08:05:39.20#ibcon#about to read 3, iclass 33, count 0 2006.246.08:05:39.23#ibcon#read 3, iclass 33, count 0 2006.246.08:05:39.23#ibcon#about to read 4, iclass 33, count 0 2006.246.08:05:39.23#ibcon#read 4, iclass 33, count 0 2006.246.08:05:39.23#ibcon#about to read 5, iclass 33, count 0 2006.246.08:05:39.23#ibcon#read 5, iclass 33, count 0 2006.246.08:05:39.23#ibcon#about to read 6, iclass 33, count 0 2006.246.08:05:39.23#ibcon#read 6, iclass 33, count 0 2006.246.08:05:39.23#ibcon#end of sib2, iclass 33, count 0 2006.246.08:05:39.23#ibcon#*after write, iclass 33, count 0 2006.246.08:05:39.23#ibcon#*before return 0, iclass 33, count 0 2006.246.08:05:39.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:39.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:39.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:05:39.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:05:39.23$vc4f8/valo=5,652.99 2006.246.08:05:39.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:05:39.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:05:39.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:39.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:05:39.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:05:39.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:05:39.23#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:05:39.23#ibcon#first serial, iclass 35, count 0 2006.246.08:05:39.23#ibcon#enter sib2, iclass 35, count 0 2006.246.08:05:39.23#ibcon#flushed, iclass 35, count 0 2006.246.08:05:39.23#ibcon#about to write, iclass 35, count 0 2006.246.08:05:39.23#ibcon#wrote, iclass 35, count 0 2006.246.08:05:39.23#ibcon#about to read 3, iclass 35, count 0 2006.246.08:05:39.25#ibcon#read 3, iclass 35, count 0 2006.246.08:05:39.25#ibcon#about to read 4, iclass 35, count 0 2006.246.08:05:39.25#ibcon#read 4, iclass 35, count 0 2006.246.08:05:39.25#ibcon#about to read 5, iclass 35, count 0 2006.246.08:05:39.25#ibcon#read 5, iclass 35, count 0 2006.246.08:05:39.25#ibcon#about to read 6, iclass 35, count 0 2006.246.08:05:39.25#ibcon#read 6, iclass 35, count 0 2006.246.08:05:39.25#ibcon#end of sib2, iclass 35, count 0 2006.246.08:05:39.25#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:05:39.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:05:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:05:39.25#ibcon#*before write, iclass 35, count 0 2006.246.08:05:39.25#ibcon#enter sib2, iclass 35, count 0 2006.246.08:05:39.25#ibcon#flushed, iclass 35, count 0 2006.246.08:05:39.25#ibcon#about to write, iclass 35, count 0 2006.246.08:05:39.25#ibcon#wrote, iclass 35, count 0 2006.246.08:05:39.25#ibcon#about to read 3, iclass 35, count 0 2006.246.08:05:39.29#ibcon#read 3, iclass 35, count 0 2006.246.08:05:39.29#ibcon#about to read 4, iclass 35, count 0 2006.246.08:05:39.29#ibcon#read 4, iclass 35, count 0 2006.246.08:05:39.29#ibcon#about to read 5, iclass 35, count 0 2006.246.08:05:39.29#ibcon#read 5, iclass 35, count 0 2006.246.08:05:39.29#ibcon#about to read 6, iclass 35, count 0 2006.246.08:05:39.29#ibcon#read 6, iclass 35, count 0 2006.246.08:05:39.29#ibcon#end of sib2, iclass 35, count 0 2006.246.08:05:39.29#ibcon#*after write, iclass 35, count 0 2006.246.08:05:39.29#ibcon#*before return 0, iclass 35, count 0 2006.246.08:05:39.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:05:39.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:05:39.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:05:39.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:05:39.29$vc4f8/va=5,7 2006.246.08:05:39.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:05:39.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:05:39.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:39.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:05:39.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:05:39.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:05:39.35#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:05:39.35#ibcon#first serial, iclass 37, count 2 2006.246.08:05:39.35#ibcon#enter sib2, iclass 37, count 2 2006.246.08:05:39.35#ibcon#flushed, iclass 37, count 2 2006.246.08:05:39.35#ibcon#about to write, iclass 37, count 2 2006.246.08:05:39.35#ibcon#wrote, iclass 37, count 2 2006.246.08:05:39.35#ibcon#about to read 3, iclass 37, count 2 2006.246.08:05:39.37#ibcon#read 3, iclass 37, count 2 2006.246.08:05:39.37#ibcon#about to read 4, iclass 37, count 2 2006.246.08:05:39.37#ibcon#read 4, iclass 37, count 2 2006.246.08:05:39.37#ibcon#about to read 5, iclass 37, count 2 2006.246.08:05:39.37#ibcon#read 5, iclass 37, count 2 2006.246.08:05:39.37#ibcon#about to read 6, iclass 37, count 2 2006.246.08:05:39.37#ibcon#read 6, iclass 37, count 2 2006.246.08:05:39.37#ibcon#end of sib2, iclass 37, count 2 2006.246.08:05:39.37#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:05:39.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:05:39.37#ibcon#[25=AT05-07\r\n] 2006.246.08:05:39.37#ibcon#*before write, iclass 37, count 2 2006.246.08:05:39.37#ibcon#enter sib2, iclass 37, count 2 2006.246.08:05:39.37#ibcon#flushed, iclass 37, count 2 2006.246.08:05:39.37#ibcon#about to write, iclass 37, count 2 2006.246.08:05:39.37#ibcon#wrote, iclass 37, count 2 2006.246.08:05:39.37#ibcon#about to read 3, iclass 37, count 2 2006.246.08:05:39.40#ibcon#read 3, iclass 37, count 2 2006.246.08:05:39.40#ibcon#about to read 4, iclass 37, count 2 2006.246.08:05:39.40#ibcon#read 4, iclass 37, count 2 2006.246.08:05:39.40#ibcon#about to read 5, iclass 37, count 2 2006.246.08:05:39.40#ibcon#read 5, iclass 37, count 2 2006.246.08:05:39.40#ibcon#about to read 6, iclass 37, count 2 2006.246.08:05:39.40#ibcon#read 6, iclass 37, count 2 2006.246.08:05:39.40#ibcon#end of sib2, iclass 37, count 2 2006.246.08:05:39.40#ibcon#*after write, iclass 37, count 2 2006.246.08:05:39.40#ibcon#*before return 0, iclass 37, count 2 2006.246.08:05:39.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:05:39.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:05:39.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:05:39.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:39.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:05:39.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:05:39.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:05:39.52#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:05:39.52#ibcon#first serial, iclass 37, count 0 2006.246.08:05:39.52#ibcon#enter sib2, iclass 37, count 0 2006.246.08:05:39.52#ibcon#flushed, iclass 37, count 0 2006.246.08:05:39.52#ibcon#about to write, iclass 37, count 0 2006.246.08:05:39.52#ibcon#wrote, iclass 37, count 0 2006.246.08:05:39.52#ibcon#about to read 3, iclass 37, count 0 2006.246.08:05:39.54#ibcon#read 3, iclass 37, count 0 2006.246.08:05:39.54#ibcon#about to read 4, iclass 37, count 0 2006.246.08:05:39.54#ibcon#read 4, iclass 37, count 0 2006.246.08:05:39.54#ibcon#about to read 5, iclass 37, count 0 2006.246.08:05:39.54#ibcon#read 5, iclass 37, count 0 2006.246.08:05:39.54#ibcon#about to read 6, iclass 37, count 0 2006.246.08:05:39.54#ibcon#read 6, iclass 37, count 0 2006.246.08:05:39.54#ibcon#end of sib2, iclass 37, count 0 2006.246.08:05:39.54#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:05:39.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:05:39.54#ibcon#[25=USB\r\n] 2006.246.08:05:39.54#ibcon#*before write, iclass 37, count 0 2006.246.08:05:39.54#ibcon#enter sib2, iclass 37, count 0 2006.246.08:05:39.54#ibcon#flushed, iclass 37, count 0 2006.246.08:05:39.54#ibcon#about to write, iclass 37, count 0 2006.246.08:05:39.54#ibcon#wrote, iclass 37, count 0 2006.246.08:05:39.54#ibcon#about to read 3, iclass 37, count 0 2006.246.08:05:39.57#ibcon#read 3, iclass 37, count 0 2006.246.08:05:39.57#ibcon#about to read 4, iclass 37, count 0 2006.246.08:05:39.57#ibcon#read 4, iclass 37, count 0 2006.246.08:05:39.57#ibcon#about to read 5, iclass 37, count 0 2006.246.08:05:39.57#ibcon#read 5, iclass 37, count 0 2006.246.08:05:39.57#ibcon#about to read 6, iclass 37, count 0 2006.246.08:05:39.57#ibcon#read 6, iclass 37, count 0 2006.246.08:05:39.57#ibcon#end of sib2, iclass 37, count 0 2006.246.08:05:39.57#ibcon#*after write, iclass 37, count 0 2006.246.08:05:39.57#ibcon#*before return 0, iclass 37, count 0 2006.246.08:05:39.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:05:39.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:05:39.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:05:39.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:05:39.57$vc4f8/valo=6,772.99 2006.246.08:05:39.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:05:39.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:05:39.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:39.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:39.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:39.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:39.57#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:05:39.57#ibcon#first serial, iclass 39, count 0 2006.246.08:05:39.57#ibcon#enter sib2, iclass 39, count 0 2006.246.08:05:39.57#ibcon#flushed, iclass 39, count 0 2006.246.08:05:39.57#ibcon#about to write, iclass 39, count 0 2006.246.08:05:39.57#ibcon#wrote, iclass 39, count 0 2006.246.08:05:39.57#ibcon#about to read 3, iclass 39, count 0 2006.246.08:05:39.59#ibcon#read 3, iclass 39, count 0 2006.246.08:05:39.59#ibcon#about to read 4, iclass 39, count 0 2006.246.08:05:39.59#ibcon#read 4, iclass 39, count 0 2006.246.08:05:39.59#ibcon#about to read 5, iclass 39, count 0 2006.246.08:05:39.59#ibcon#read 5, iclass 39, count 0 2006.246.08:05:39.59#ibcon#about to read 6, iclass 39, count 0 2006.246.08:05:39.59#ibcon#read 6, iclass 39, count 0 2006.246.08:05:39.59#ibcon#end of sib2, iclass 39, count 0 2006.246.08:05:39.59#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:05:39.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:05:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:05:39.59#ibcon#*before write, iclass 39, count 0 2006.246.08:05:39.59#ibcon#enter sib2, iclass 39, count 0 2006.246.08:05:39.59#ibcon#flushed, iclass 39, count 0 2006.246.08:05:39.59#ibcon#about to write, iclass 39, count 0 2006.246.08:05:39.59#ibcon#wrote, iclass 39, count 0 2006.246.08:05:39.59#ibcon#about to read 3, iclass 39, count 0 2006.246.08:05:39.64#ibcon#read 3, iclass 39, count 0 2006.246.08:05:39.64#ibcon#about to read 4, iclass 39, count 0 2006.246.08:05:39.64#ibcon#read 4, iclass 39, count 0 2006.246.08:05:39.64#ibcon#about to read 5, iclass 39, count 0 2006.246.08:05:39.64#ibcon#read 5, iclass 39, count 0 2006.246.08:05:39.64#ibcon#about to read 6, iclass 39, count 0 2006.246.08:05:39.64#ibcon#read 6, iclass 39, count 0 2006.246.08:05:39.64#ibcon#end of sib2, iclass 39, count 0 2006.246.08:05:39.64#ibcon#*after write, iclass 39, count 0 2006.246.08:05:39.64#ibcon#*before return 0, iclass 39, count 0 2006.246.08:05:39.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:39.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:39.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:05:39.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:05:39.64$vc4f8/va=6,7 2006.246.08:05:39.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:05:39.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:05:39.64#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:39.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:39.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:39.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:39.69#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:05:39.69#ibcon#first serial, iclass 3, count 2 2006.246.08:05:39.69#ibcon#enter sib2, iclass 3, count 2 2006.246.08:05:39.69#ibcon#flushed, iclass 3, count 2 2006.246.08:05:39.69#ibcon#about to write, iclass 3, count 2 2006.246.08:05:39.69#ibcon#wrote, iclass 3, count 2 2006.246.08:05:39.69#ibcon#about to read 3, iclass 3, count 2 2006.246.08:05:39.71#ibcon#read 3, iclass 3, count 2 2006.246.08:05:39.71#ibcon#about to read 4, iclass 3, count 2 2006.246.08:05:39.71#ibcon#read 4, iclass 3, count 2 2006.246.08:05:39.71#ibcon#about to read 5, iclass 3, count 2 2006.246.08:05:39.71#ibcon#read 5, iclass 3, count 2 2006.246.08:05:39.71#ibcon#about to read 6, iclass 3, count 2 2006.246.08:05:39.71#ibcon#read 6, iclass 3, count 2 2006.246.08:05:39.71#ibcon#end of sib2, iclass 3, count 2 2006.246.08:05:39.71#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:05:39.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:05:39.71#ibcon#[25=AT06-07\r\n] 2006.246.08:05:39.71#ibcon#*before write, iclass 3, count 2 2006.246.08:05:39.71#ibcon#enter sib2, iclass 3, count 2 2006.246.08:05:39.71#ibcon#flushed, iclass 3, count 2 2006.246.08:05:39.71#ibcon#about to write, iclass 3, count 2 2006.246.08:05:39.71#ibcon#wrote, iclass 3, count 2 2006.246.08:05:39.71#ibcon#about to read 3, iclass 3, count 2 2006.246.08:05:39.74#ibcon#read 3, iclass 3, count 2 2006.246.08:05:39.74#ibcon#about to read 4, iclass 3, count 2 2006.246.08:05:39.74#ibcon#read 4, iclass 3, count 2 2006.246.08:05:39.74#ibcon#about to read 5, iclass 3, count 2 2006.246.08:05:39.74#ibcon#read 5, iclass 3, count 2 2006.246.08:05:39.74#ibcon#about to read 6, iclass 3, count 2 2006.246.08:05:39.74#ibcon#read 6, iclass 3, count 2 2006.246.08:05:39.74#ibcon#end of sib2, iclass 3, count 2 2006.246.08:05:39.74#ibcon#*after write, iclass 3, count 2 2006.246.08:05:39.74#ibcon#*before return 0, iclass 3, count 2 2006.246.08:05:39.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:39.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:39.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:05:39.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:39.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:39.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:39.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:39.86#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:05:39.86#ibcon#first serial, iclass 3, count 0 2006.246.08:05:39.86#ibcon#enter sib2, iclass 3, count 0 2006.246.08:05:39.86#ibcon#flushed, iclass 3, count 0 2006.246.08:05:39.86#ibcon#about to write, iclass 3, count 0 2006.246.08:05:39.86#ibcon#wrote, iclass 3, count 0 2006.246.08:05:39.86#ibcon#about to read 3, iclass 3, count 0 2006.246.08:05:39.88#ibcon#read 3, iclass 3, count 0 2006.246.08:05:39.88#ibcon#about to read 4, iclass 3, count 0 2006.246.08:05:39.88#ibcon#read 4, iclass 3, count 0 2006.246.08:05:39.88#ibcon#about to read 5, iclass 3, count 0 2006.246.08:05:39.88#ibcon#read 5, iclass 3, count 0 2006.246.08:05:39.88#ibcon#about to read 6, iclass 3, count 0 2006.246.08:05:39.88#ibcon#read 6, iclass 3, count 0 2006.246.08:05:39.88#ibcon#end of sib2, iclass 3, count 0 2006.246.08:05:39.88#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:05:39.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:05:39.88#ibcon#[25=USB\r\n] 2006.246.08:05:39.88#ibcon#*before write, iclass 3, count 0 2006.246.08:05:39.88#ibcon#enter sib2, iclass 3, count 0 2006.246.08:05:39.88#ibcon#flushed, iclass 3, count 0 2006.246.08:05:39.88#ibcon#about to write, iclass 3, count 0 2006.246.08:05:39.88#ibcon#wrote, iclass 3, count 0 2006.246.08:05:39.88#ibcon#about to read 3, iclass 3, count 0 2006.246.08:05:39.91#ibcon#read 3, iclass 3, count 0 2006.246.08:05:39.91#ibcon#about to read 4, iclass 3, count 0 2006.246.08:05:39.91#ibcon#read 4, iclass 3, count 0 2006.246.08:05:39.91#ibcon#about to read 5, iclass 3, count 0 2006.246.08:05:39.91#ibcon#read 5, iclass 3, count 0 2006.246.08:05:39.91#ibcon#about to read 6, iclass 3, count 0 2006.246.08:05:39.91#ibcon#read 6, iclass 3, count 0 2006.246.08:05:39.91#ibcon#end of sib2, iclass 3, count 0 2006.246.08:05:39.91#ibcon#*after write, iclass 3, count 0 2006.246.08:05:39.91#ibcon#*before return 0, iclass 3, count 0 2006.246.08:05:39.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:39.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:39.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:05:39.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:05:39.91$vc4f8/valo=7,832.99 2006.246.08:05:39.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:05:39.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:05:39.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:39.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:39.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:39.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:39.91#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:05:39.91#ibcon#first serial, iclass 5, count 0 2006.246.08:05:39.91#ibcon#enter sib2, iclass 5, count 0 2006.246.08:05:39.91#ibcon#flushed, iclass 5, count 0 2006.246.08:05:39.91#ibcon#about to write, iclass 5, count 0 2006.246.08:05:39.91#ibcon#wrote, iclass 5, count 0 2006.246.08:05:39.91#ibcon#about to read 3, iclass 5, count 0 2006.246.08:05:39.93#ibcon#read 3, iclass 5, count 0 2006.246.08:05:39.93#ibcon#about to read 4, iclass 5, count 0 2006.246.08:05:39.93#ibcon#read 4, iclass 5, count 0 2006.246.08:05:39.93#ibcon#about to read 5, iclass 5, count 0 2006.246.08:05:39.93#ibcon#read 5, iclass 5, count 0 2006.246.08:05:39.93#ibcon#about to read 6, iclass 5, count 0 2006.246.08:05:39.93#ibcon#read 6, iclass 5, count 0 2006.246.08:05:39.93#ibcon#end of sib2, iclass 5, count 0 2006.246.08:05:39.93#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:05:39.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:05:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:05:39.93#ibcon#*before write, iclass 5, count 0 2006.246.08:05:39.93#ibcon#enter sib2, iclass 5, count 0 2006.246.08:05:39.93#ibcon#flushed, iclass 5, count 0 2006.246.08:05:39.93#ibcon#about to write, iclass 5, count 0 2006.246.08:05:39.93#ibcon#wrote, iclass 5, count 0 2006.246.08:05:39.93#ibcon#about to read 3, iclass 5, count 0 2006.246.08:05:39.97#ibcon#read 3, iclass 5, count 0 2006.246.08:05:39.97#ibcon#about to read 4, iclass 5, count 0 2006.246.08:05:39.97#ibcon#read 4, iclass 5, count 0 2006.246.08:05:39.97#ibcon#about to read 5, iclass 5, count 0 2006.246.08:05:39.97#ibcon#read 5, iclass 5, count 0 2006.246.08:05:39.97#ibcon#about to read 6, iclass 5, count 0 2006.246.08:05:39.97#ibcon#read 6, iclass 5, count 0 2006.246.08:05:39.97#ibcon#end of sib2, iclass 5, count 0 2006.246.08:05:39.97#ibcon#*after write, iclass 5, count 0 2006.246.08:05:39.97#ibcon#*before return 0, iclass 5, count 0 2006.246.08:05:39.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:39.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:39.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:05:39.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:05:39.97$vc4f8/va=7,7 2006.246.08:05:39.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.08:05:39.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.08:05:39.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:39.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:05:40.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:05:40.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:05:40.03#ibcon#enter wrdev, iclass 7, count 2 2006.246.08:05:40.03#ibcon#first serial, iclass 7, count 2 2006.246.08:05:40.03#ibcon#enter sib2, iclass 7, count 2 2006.246.08:05:40.03#ibcon#flushed, iclass 7, count 2 2006.246.08:05:40.03#ibcon#about to write, iclass 7, count 2 2006.246.08:05:40.03#ibcon#wrote, iclass 7, count 2 2006.246.08:05:40.03#ibcon#about to read 3, iclass 7, count 2 2006.246.08:05:40.05#ibcon#read 3, iclass 7, count 2 2006.246.08:05:40.05#ibcon#about to read 4, iclass 7, count 2 2006.246.08:05:40.05#ibcon#read 4, iclass 7, count 2 2006.246.08:05:40.05#ibcon#about to read 5, iclass 7, count 2 2006.246.08:05:40.05#ibcon#read 5, iclass 7, count 2 2006.246.08:05:40.05#ibcon#about to read 6, iclass 7, count 2 2006.246.08:05:40.05#ibcon#read 6, iclass 7, count 2 2006.246.08:05:40.05#ibcon#end of sib2, iclass 7, count 2 2006.246.08:05:40.05#ibcon#*mode == 0, iclass 7, count 2 2006.246.08:05:40.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.08:05:40.05#ibcon#[25=AT07-07\r\n] 2006.246.08:05:40.05#ibcon#*before write, iclass 7, count 2 2006.246.08:05:40.05#ibcon#enter sib2, iclass 7, count 2 2006.246.08:05:40.05#ibcon#flushed, iclass 7, count 2 2006.246.08:05:40.05#ibcon#about to write, iclass 7, count 2 2006.246.08:05:40.05#ibcon#wrote, iclass 7, count 2 2006.246.08:05:40.05#ibcon#about to read 3, iclass 7, count 2 2006.246.08:05:40.08#ibcon#read 3, iclass 7, count 2 2006.246.08:05:40.08#ibcon#about to read 4, iclass 7, count 2 2006.246.08:05:40.08#ibcon#read 4, iclass 7, count 2 2006.246.08:05:40.08#ibcon#about to read 5, iclass 7, count 2 2006.246.08:05:40.08#ibcon#read 5, iclass 7, count 2 2006.246.08:05:40.08#ibcon#about to read 6, iclass 7, count 2 2006.246.08:05:40.08#ibcon#read 6, iclass 7, count 2 2006.246.08:05:40.08#ibcon#end of sib2, iclass 7, count 2 2006.246.08:05:40.08#ibcon#*after write, iclass 7, count 2 2006.246.08:05:40.08#ibcon#*before return 0, iclass 7, count 2 2006.246.08:05:40.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:05:40.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:05:40.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.08:05:40.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:40.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:05:40.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:05:40.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:05:40.20#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:05:40.20#ibcon#first serial, iclass 7, count 0 2006.246.08:05:40.20#ibcon#enter sib2, iclass 7, count 0 2006.246.08:05:40.20#ibcon#flushed, iclass 7, count 0 2006.246.08:05:40.20#ibcon#about to write, iclass 7, count 0 2006.246.08:05:40.20#ibcon#wrote, iclass 7, count 0 2006.246.08:05:40.20#ibcon#about to read 3, iclass 7, count 0 2006.246.08:05:40.22#ibcon#read 3, iclass 7, count 0 2006.246.08:05:40.22#ibcon#about to read 4, iclass 7, count 0 2006.246.08:05:40.22#ibcon#read 4, iclass 7, count 0 2006.246.08:05:40.22#ibcon#about to read 5, iclass 7, count 0 2006.246.08:05:40.22#ibcon#read 5, iclass 7, count 0 2006.246.08:05:40.22#ibcon#about to read 6, iclass 7, count 0 2006.246.08:05:40.22#ibcon#read 6, iclass 7, count 0 2006.246.08:05:40.22#ibcon#end of sib2, iclass 7, count 0 2006.246.08:05:40.22#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:05:40.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:05:40.22#ibcon#[25=USB\r\n] 2006.246.08:05:40.22#ibcon#*before write, iclass 7, count 0 2006.246.08:05:40.22#ibcon#enter sib2, iclass 7, count 0 2006.246.08:05:40.22#ibcon#flushed, iclass 7, count 0 2006.246.08:05:40.22#ibcon#about to write, iclass 7, count 0 2006.246.08:05:40.22#ibcon#wrote, iclass 7, count 0 2006.246.08:05:40.22#ibcon#about to read 3, iclass 7, count 0 2006.246.08:05:40.25#ibcon#read 3, iclass 7, count 0 2006.246.08:05:40.25#ibcon#about to read 4, iclass 7, count 0 2006.246.08:05:40.25#ibcon#read 4, iclass 7, count 0 2006.246.08:05:40.25#ibcon#about to read 5, iclass 7, count 0 2006.246.08:05:40.25#ibcon#read 5, iclass 7, count 0 2006.246.08:05:40.25#ibcon#about to read 6, iclass 7, count 0 2006.246.08:05:40.25#ibcon#read 6, iclass 7, count 0 2006.246.08:05:40.25#ibcon#end of sib2, iclass 7, count 0 2006.246.08:05:40.25#ibcon#*after write, iclass 7, count 0 2006.246.08:05:40.25#ibcon#*before return 0, iclass 7, count 0 2006.246.08:05:40.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:05:40.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:05:40.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:05:40.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:05:40.25$vc4f8/valo=8,852.99 2006.246.08:05:40.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.08:05:40.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.08:05:40.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:40.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:05:40.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:05:40.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:05:40.25#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:05:40.25#ibcon#first serial, iclass 11, count 0 2006.246.08:05:40.25#ibcon#enter sib2, iclass 11, count 0 2006.246.08:05:40.25#ibcon#flushed, iclass 11, count 0 2006.246.08:05:40.25#ibcon#about to write, iclass 11, count 0 2006.246.08:05:40.25#ibcon#wrote, iclass 11, count 0 2006.246.08:05:40.25#ibcon#about to read 3, iclass 11, count 0 2006.246.08:05:40.27#ibcon#read 3, iclass 11, count 0 2006.246.08:05:40.27#ibcon#about to read 4, iclass 11, count 0 2006.246.08:05:40.27#ibcon#read 4, iclass 11, count 0 2006.246.08:05:40.27#ibcon#about to read 5, iclass 11, count 0 2006.246.08:05:40.27#ibcon#read 5, iclass 11, count 0 2006.246.08:05:40.27#ibcon#about to read 6, iclass 11, count 0 2006.246.08:05:40.27#ibcon#read 6, iclass 11, count 0 2006.246.08:05:40.27#ibcon#end of sib2, iclass 11, count 0 2006.246.08:05:40.27#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:05:40.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:05:40.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:05:40.27#ibcon#*before write, iclass 11, count 0 2006.246.08:05:40.27#ibcon#enter sib2, iclass 11, count 0 2006.246.08:05:40.27#ibcon#flushed, iclass 11, count 0 2006.246.08:05:40.27#ibcon#about to write, iclass 11, count 0 2006.246.08:05:40.27#ibcon#wrote, iclass 11, count 0 2006.246.08:05:40.27#ibcon#about to read 3, iclass 11, count 0 2006.246.08:05:40.31#ibcon#read 3, iclass 11, count 0 2006.246.08:05:40.31#ibcon#about to read 4, iclass 11, count 0 2006.246.08:05:40.31#ibcon#read 4, iclass 11, count 0 2006.246.08:05:40.31#ibcon#about to read 5, iclass 11, count 0 2006.246.08:05:40.31#ibcon#read 5, iclass 11, count 0 2006.246.08:05:40.31#ibcon#about to read 6, iclass 11, count 0 2006.246.08:05:40.31#ibcon#read 6, iclass 11, count 0 2006.246.08:05:40.31#ibcon#end of sib2, iclass 11, count 0 2006.246.08:05:40.31#ibcon#*after write, iclass 11, count 0 2006.246.08:05:40.31#ibcon#*before return 0, iclass 11, count 0 2006.246.08:05:40.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:05:40.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:05:40.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:05:40.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:05:40.31$vc4f8/va=8,8 2006.246.08:05:40.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.08:05:40.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.08:05:40.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:40.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:05:40.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:05:40.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:05:40.37#ibcon#enter wrdev, iclass 13, count 2 2006.246.08:05:40.37#ibcon#first serial, iclass 13, count 2 2006.246.08:05:40.37#ibcon#enter sib2, iclass 13, count 2 2006.246.08:05:40.37#ibcon#flushed, iclass 13, count 2 2006.246.08:05:40.37#ibcon#about to write, iclass 13, count 2 2006.246.08:05:40.37#ibcon#wrote, iclass 13, count 2 2006.246.08:05:40.37#ibcon#about to read 3, iclass 13, count 2 2006.246.08:05:40.39#ibcon#read 3, iclass 13, count 2 2006.246.08:05:40.39#ibcon#about to read 4, iclass 13, count 2 2006.246.08:05:40.39#ibcon#read 4, iclass 13, count 2 2006.246.08:05:40.39#ibcon#about to read 5, iclass 13, count 2 2006.246.08:05:40.39#ibcon#read 5, iclass 13, count 2 2006.246.08:05:40.39#ibcon#about to read 6, iclass 13, count 2 2006.246.08:05:40.39#ibcon#read 6, iclass 13, count 2 2006.246.08:05:40.39#ibcon#end of sib2, iclass 13, count 2 2006.246.08:05:40.39#ibcon#*mode == 0, iclass 13, count 2 2006.246.08:05:40.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.08:05:40.39#ibcon#[25=AT08-08\r\n] 2006.246.08:05:40.39#ibcon#*before write, iclass 13, count 2 2006.246.08:05:40.39#ibcon#enter sib2, iclass 13, count 2 2006.246.08:05:40.39#ibcon#flushed, iclass 13, count 2 2006.246.08:05:40.39#ibcon#about to write, iclass 13, count 2 2006.246.08:05:40.39#ibcon#wrote, iclass 13, count 2 2006.246.08:05:40.39#ibcon#about to read 3, iclass 13, count 2 2006.246.08:05:40.42#ibcon#read 3, iclass 13, count 2 2006.246.08:05:40.42#ibcon#about to read 4, iclass 13, count 2 2006.246.08:05:40.42#ibcon#read 4, iclass 13, count 2 2006.246.08:05:40.42#ibcon#about to read 5, iclass 13, count 2 2006.246.08:05:40.42#ibcon#read 5, iclass 13, count 2 2006.246.08:05:40.42#ibcon#about to read 6, iclass 13, count 2 2006.246.08:05:40.42#ibcon#read 6, iclass 13, count 2 2006.246.08:05:40.42#ibcon#end of sib2, iclass 13, count 2 2006.246.08:05:40.42#ibcon#*after write, iclass 13, count 2 2006.246.08:05:40.42#ibcon#*before return 0, iclass 13, count 2 2006.246.08:05:40.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:05:40.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:05:40.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.08:05:40.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:40.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:05:40.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:05:40.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:05:40.54#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:05:40.54#ibcon#first serial, iclass 13, count 0 2006.246.08:05:40.54#ibcon#enter sib2, iclass 13, count 0 2006.246.08:05:40.54#ibcon#flushed, iclass 13, count 0 2006.246.08:05:40.54#ibcon#about to write, iclass 13, count 0 2006.246.08:05:40.54#ibcon#wrote, iclass 13, count 0 2006.246.08:05:40.54#ibcon#about to read 3, iclass 13, count 0 2006.246.08:05:40.56#ibcon#read 3, iclass 13, count 0 2006.246.08:05:40.56#ibcon#about to read 4, iclass 13, count 0 2006.246.08:05:40.56#ibcon#read 4, iclass 13, count 0 2006.246.08:05:40.56#ibcon#about to read 5, iclass 13, count 0 2006.246.08:05:40.56#ibcon#read 5, iclass 13, count 0 2006.246.08:05:40.56#ibcon#about to read 6, iclass 13, count 0 2006.246.08:05:40.56#ibcon#read 6, iclass 13, count 0 2006.246.08:05:40.56#ibcon#end of sib2, iclass 13, count 0 2006.246.08:05:40.56#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:05:40.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:05:40.56#ibcon#[25=USB\r\n] 2006.246.08:05:40.56#ibcon#*before write, iclass 13, count 0 2006.246.08:05:40.56#ibcon#enter sib2, iclass 13, count 0 2006.246.08:05:40.56#ibcon#flushed, iclass 13, count 0 2006.246.08:05:40.56#ibcon#about to write, iclass 13, count 0 2006.246.08:05:40.56#ibcon#wrote, iclass 13, count 0 2006.246.08:05:40.56#ibcon#about to read 3, iclass 13, count 0 2006.246.08:05:40.59#ibcon#read 3, iclass 13, count 0 2006.246.08:05:40.59#ibcon#about to read 4, iclass 13, count 0 2006.246.08:05:40.59#ibcon#read 4, iclass 13, count 0 2006.246.08:05:40.59#ibcon#about to read 5, iclass 13, count 0 2006.246.08:05:40.59#ibcon#read 5, iclass 13, count 0 2006.246.08:05:40.59#ibcon#about to read 6, iclass 13, count 0 2006.246.08:05:40.59#ibcon#read 6, iclass 13, count 0 2006.246.08:05:40.59#ibcon#end of sib2, iclass 13, count 0 2006.246.08:05:40.59#ibcon#*after write, iclass 13, count 0 2006.246.08:05:40.59#ibcon#*before return 0, iclass 13, count 0 2006.246.08:05:40.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:05:40.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:05:40.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:05:40.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:05:40.59$vc4f8/vblo=1,632.99 2006.246.08:05:40.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.08:05:40.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.08:05:40.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:40.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:05:40.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:05:40.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:05:40.59#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:05:40.59#ibcon#first serial, iclass 15, count 0 2006.246.08:05:40.59#ibcon#enter sib2, iclass 15, count 0 2006.246.08:05:40.59#ibcon#flushed, iclass 15, count 0 2006.246.08:05:40.59#ibcon#about to write, iclass 15, count 0 2006.246.08:05:40.59#ibcon#wrote, iclass 15, count 0 2006.246.08:05:40.59#ibcon#about to read 3, iclass 15, count 0 2006.246.08:05:40.61#ibcon#read 3, iclass 15, count 0 2006.246.08:05:40.61#ibcon#about to read 4, iclass 15, count 0 2006.246.08:05:40.61#ibcon#read 4, iclass 15, count 0 2006.246.08:05:40.61#ibcon#about to read 5, iclass 15, count 0 2006.246.08:05:40.61#ibcon#read 5, iclass 15, count 0 2006.246.08:05:40.61#ibcon#about to read 6, iclass 15, count 0 2006.246.08:05:40.61#ibcon#read 6, iclass 15, count 0 2006.246.08:05:40.61#ibcon#end of sib2, iclass 15, count 0 2006.246.08:05:40.61#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:05:40.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:05:40.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:05:40.61#ibcon#*before write, iclass 15, count 0 2006.246.08:05:40.61#ibcon#enter sib2, iclass 15, count 0 2006.246.08:05:40.61#ibcon#flushed, iclass 15, count 0 2006.246.08:05:40.61#ibcon#about to write, iclass 15, count 0 2006.246.08:05:40.61#ibcon#wrote, iclass 15, count 0 2006.246.08:05:40.61#ibcon#about to read 3, iclass 15, count 0 2006.246.08:05:40.65#ibcon#read 3, iclass 15, count 0 2006.246.08:05:40.65#ibcon#about to read 4, iclass 15, count 0 2006.246.08:05:40.65#ibcon#read 4, iclass 15, count 0 2006.246.08:05:40.65#ibcon#about to read 5, iclass 15, count 0 2006.246.08:05:40.65#ibcon#read 5, iclass 15, count 0 2006.246.08:05:40.65#ibcon#about to read 6, iclass 15, count 0 2006.246.08:05:40.65#ibcon#read 6, iclass 15, count 0 2006.246.08:05:40.65#ibcon#end of sib2, iclass 15, count 0 2006.246.08:05:40.65#ibcon#*after write, iclass 15, count 0 2006.246.08:05:40.65#ibcon#*before return 0, iclass 15, count 0 2006.246.08:05:40.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:05:40.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:05:40.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:05:40.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:05:40.65$vc4f8/vb=1,4 2006.246.08:05:40.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.08:05:40.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.08:05:40.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:40.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:05:40.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:05:40.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:05:40.65#ibcon#enter wrdev, iclass 17, count 2 2006.246.08:05:40.65#ibcon#first serial, iclass 17, count 2 2006.246.08:05:40.65#ibcon#enter sib2, iclass 17, count 2 2006.246.08:05:40.65#ibcon#flushed, iclass 17, count 2 2006.246.08:05:40.65#ibcon#about to write, iclass 17, count 2 2006.246.08:05:40.65#ibcon#wrote, iclass 17, count 2 2006.246.08:05:40.65#ibcon#about to read 3, iclass 17, count 2 2006.246.08:05:40.67#ibcon#read 3, iclass 17, count 2 2006.246.08:05:40.67#ibcon#about to read 4, iclass 17, count 2 2006.246.08:05:40.67#ibcon#read 4, iclass 17, count 2 2006.246.08:05:40.67#ibcon#about to read 5, iclass 17, count 2 2006.246.08:05:40.67#ibcon#read 5, iclass 17, count 2 2006.246.08:05:40.67#ibcon#about to read 6, iclass 17, count 2 2006.246.08:05:40.67#ibcon#read 6, iclass 17, count 2 2006.246.08:05:40.67#ibcon#end of sib2, iclass 17, count 2 2006.246.08:05:40.67#ibcon#*mode == 0, iclass 17, count 2 2006.246.08:05:40.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.08:05:40.67#ibcon#[27=AT01-04\r\n] 2006.246.08:05:40.67#ibcon#*before write, iclass 17, count 2 2006.246.08:05:40.67#ibcon#enter sib2, iclass 17, count 2 2006.246.08:05:40.67#ibcon#flushed, iclass 17, count 2 2006.246.08:05:40.67#ibcon#about to write, iclass 17, count 2 2006.246.08:05:40.67#ibcon#wrote, iclass 17, count 2 2006.246.08:05:40.67#ibcon#about to read 3, iclass 17, count 2 2006.246.08:05:40.70#ibcon#read 3, iclass 17, count 2 2006.246.08:05:40.70#ibcon#about to read 4, iclass 17, count 2 2006.246.08:05:40.70#ibcon#read 4, iclass 17, count 2 2006.246.08:05:40.70#ibcon#about to read 5, iclass 17, count 2 2006.246.08:05:40.70#ibcon#read 5, iclass 17, count 2 2006.246.08:05:40.70#ibcon#about to read 6, iclass 17, count 2 2006.246.08:05:40.70#ibcon#read 6, iclass 17, count 2 2006.246.08:05:40.70#ibcon#end of sib2, iclass 17, count 2 2006.246.08:05:40.70#ibcon#*after write, iclass 17, count 2 2006.246.08:05:40.70#ibcon#*before return 0, iclass 17, count 2 2006.246.08:05:40.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:05:40.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:05:40.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.08:05:40.70#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:40.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:05:40.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:05:40.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:05:40.82#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:05:40.82#ibcon#first serial, iclass 17, count 0 2006.246.08:05:40.82#ibcon#enter sib2, iclass 17, count 0 2006.246.08:05:40.82#ibcon#flushed, iclass 17, count 0 2006.246.08:05:40.82#ibcon#about to write, iclass 17, count 0 2006.246.08:05:40.82#ibcon#wrote, iclass 17, count 0 2006.246.08:05:40.82#ibcon#about to read 3, iclass 17, count 0 2006.246.08:05:40.84#ibcon#read 3, iclass 17, count 0 2006.246.08:05:40.84#ibcon#about to read 4, iclass 17, count 0 2006.246.08:05:40.84#ibcon#read 4, iclass 17, count 0 2006.246.08:05:40.84#ibcon#about to read 5, iclass 17, count 0 2006.246.08:05:40.84#ibcon#read 5, iclass 17, count 0 2006.246.08:05:40.84#ibcon#about to read 6, iclass 17, count 0 2006.246.08:05:40.84#ibcon#read 6, iclass 17, count 0 2006.246.08:05:40.84#ibcon#end of sib2, iclass 17, count 0 2006.246.08:05:40.84#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:05:40.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:05:40.84#ibcon#[27=USB\r\n] 2006.246.08:05:40.84#ibcon#*before write, iclass 17, count 0 2006.246.08:05:40.84#ibcon#enter sib2, iclass 17, count 0 2006.246.08:05:40.84#ibcon#flushed, iclass 17, count 0 2006.246.08:05:40.84#ibcon#about to write, iclass 17, count 0 2006.246.08:05:40.84#ibcon#wrote, iclass 17, count 0 2006.246.08:05:40.84#ibcon#about to read 3, iclass 17, count 0 2006.246.08:05:40.87#ibcon#read 3, iclass 17, count 0 2006.246.08:05:40.87#ibcon#about to read 4, iclass 17, count 0 2006.246.08:05:40.87#ibcon#read 4, iclass 17, count 0 2006.246.08:05:40.87#ibcon#about to read 5, iclass 17, count 0 2006.246.08:05:40.87#ibcon#read 5, iclass 17, count 0 2006.246.08:05:40.87#ibcon#about to read 6, iclass 17, count 0 2006.246.08:05:40.87#ibcon#read 6, iclass 17, count 0 2006.246.08:05:40.87#ibcon#end of sib2, iclass 17, count 0 2006.246.08:05:40.87#ibcon#*after write, iclass 17, count 0 2006.246.08:05:40.87#ibcon#*before return 0, iclass 17, count 0 2006.246.08:05:40.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:05:40.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:05:40.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:05:40.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:05:40.87$vc4f8/vblo=2,640.99 2006.246.08:05:40.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.08:05:40.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.08:05:40.87#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:40.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:40.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:40.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:40.87#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:05:40.87#ibcon#first serial, iclass 19, count 0 2006.246.08:05:40.87#ibcon#enter sib2, iclass 19, count 0 2006.246.08:05:40.87#ibcon#flushed, iclass 19, count 0 2006.246.08:05:40.87#ibcon#about to write, iclass 19, count 0 2006.246.08:05:40.87#ibcon#wrote, iclass 19, count 0 2006.246.08:05:40.87#ibcon#about to read 3, iclass 19, count 0 2006.246.08:05:40.89#ibcon#read 3, iclass 19, count 0 2006.246.08:05:40.89#ibcon#about to read 4, iclass 19, count 0 2006.246.08:05:40.89#ibcon#read 4, iclass 19, count 0 2006.246.08:05:40.89#ibcon#about to read 5, iclass 19, count 0 2006.246.08:05:40.89#ibcon#read 5, iclass 19, count 0 2006.246.08:05:40.89#ibcon#about to read 6, iclass 19, count 0 2006.246.08:05:40.89#ibcon#read 6, iclass 19, count 0 2006.246.08:05:40.89#ibcon#end of sib2, iclass 19, count 0 2006.246.08:05:40.89#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:05:40.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:05:40.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:05:40.89#ibcon#*before write, iclass 19, count 0 2006.246.08:05:40.89#ibcon#enter sib2, iclass 19, count 0 2006.246.08:05:40.89#ibcon#flushed, iclass 19, count 0 2006.246.08:05:40.89#ibcon#about to write, iclass 19, count 0 2006.246.08:05:40.89#ibcon#wrote, iclass 19, count 0 2006.246.08:05:40.89#ibcon#about to read 3, iclass 19, count 0 2006.246.08:05:40.93#ibcon#read 3, iclass 19, count 0 2006.246.08:05:40.93#ibcon#about to read 4, iclass 19, count 0 2006.246.08:05:40.93#ibcon#read 4, iclass 19, count 0 2006.246.08:05:40.93#ibcon#about to read 5, iclass 19, count 0 2006.246.08:05:40.93#ibcon#read 5, iclass 19, count 0 2006.246.08:05:40.93#ibcon#about to read 6, iclass 19, count 0 2006.246.08:05:40.93#ibcon#read 6, iclass 19, count 0 2006.246.08:05:40.93#ibcon#end of sib2, iclass 19, count 0 2006.246.08:05:40.93#ibcon#*after write, iclass 19, count 0 2006.246.08:05:40.93#ibcon#*before return 0, iclass 19, count 0 2006.246.08:05:40.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:40.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:05:40.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:05:40.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:05:40.93$vc4f8/vb=2,4 2006.246.08:05:40.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.08:05:40.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.08:05:40.93#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:40.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:40.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:40.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:40.99#ibcon#enter wrdev, iclass 21, count 2 2006.246.08:05:40.99#ibcon#first serial, iclass 21, count 2 2006.246.08:05:40.99#ibcon#enter sib2, iclass 21, count 2 2006.246.08:05:40.99#ibcon#flushed, iclass 21, count 2 2006.246.08:05:40.99#ibcon#about to write, iclass 21, count 2 2006.246.08:05:40.99#ibcon#wrote, iclass 21, count 2 2006.246.08:05:40.99#ibcon#about to read 3, iclass 21, count 2 2006.246.08:05:41.01#ibcon#read 3, iclass 21, count 2 2006.246.08:05:41.01#ibcon#about to read 4, iclass 21, count 2 2006.246.08:05:41.01#ibcon#read 4, iclass 21, count 2 2006.246.08:05:41.01#ibcon#about to read 5, iclass 21, count 2 2006.246.08:05:41.01#ibcon#read 5, iclass 21, count 2 2006.246.08:05:41.01#ibcon#about to read 6, iclass 21, count 2 2006.246.08:05:41.01#ibcon#read 6, iclass 21, count 2 2006.246.08:05:41.01#ibcon#end of sib2, iclass 21, count 2 2006.246.08:05:41.01#ibcon#*mode == 0, iclass 21, count 2 2006.246.08:05:41.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.08:05:41.01#ibcon#[27=AT02-04\r\n] 2006.246.08:05:41.01#ibcon#*before write, iclass 21, count 2 2006.246.08:05:41.01#ibcon#enter sib2, iclass 21, count 2 2006.246.08:05:41.01#ibcon#flushed, iclass 21, count 2 2006.246.08:05:41.01#ibcon#about to write, iclass 21, count 2 2006.246.08:05:41.01#ibcon#wrote, iclass 21, count 2 2006.246.08:05:41.01#ibcon#about to read 3, iclass 21, count 2 2006.246.08:05:41.04#ibcon#read 3, iclass 21, count 2 2006.246.08:05:41.04#ibcon#about to read 4, iclass 21, count 2 2006.246.08:05:41.04#ibcon#read 4, iclass 21, count 2 2006.246.08:05:41.04#ibcon#about to read 5, iclass 21, count 2 2006.246.08:05:41.04#ibcon#read 5, iclass 21, count 2 2006.246.08:05:41.04#ibcon#about to read 6, iclass 21, count 2 2006.246.08:05:41.04#ibcon#read 6, iclass 21, count 2 2006.246.08:05:41.04#ibcon#end of sib2, iclass 21, count 2 2006.246.08:05:41.04#ibcon#*after write, iclass 21, count 2 2006.246.08:05:41.04#ibcon#*before return 0, iclass 21, count 2 2006.246.08:05:41.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:41.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:05:41.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.08:05:41.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:41.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:41.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:41.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:41.16#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:05:41.16#ibcon#first serial, iclass 21, count 0 2006.246.08:05:41.16#ibcon#enter sib2, iclass 21, count 0 2006.246.08:05:41.16#ibcon#flushed, iclass 21, count 0 2006.246.08:05:41.16#ibcon#about to write, iclass 21, count 0 2006.246.08:05:41.16#ibcon#wrote, iclass 21, count 0 2006.246.08:05:41.16#ibcon#about to read 3, iclass 21, count 0 2006.246.08:05:41.18#ibcon#read 3, iclass 21, count 0 2006.246.08:05:41.18#ibcon#about to read 4, iclass 21, count 0 2006.246.08:05:41.18#ibcon#read 4, iclass 21, count 0 2006.246.08:05:41.18#ibcon#about to read 5, iclass 21, count 0 2006.246.08:05:41.18#ibcon#read 5, iclass 21, count 0 2006.246.08:05:41.18#ibcon#about to read 6, iclass 21, count 0 2006.246.08:05:41.18#ibcon#read 6, iclass 21, count 0 2006.246.08:05:41.18#ibcon#end of sib2, iclass 21, count 0 2006.246.08:05:41.18#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:05:41.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:05:41.18#ibcon#[27=USB\r\n] 2006.246.08:05:41.18#ibcon#*before write, iclass 21, count 0 2006.246.08:05:41.18#ibcon#enter sib2, iclass 21, count 0 2006.246.08:05:41.18#ibcon#flushed, iclass 21, count 0 2006.246.08:05:41.18#ibcon#about to write, iclass 21, count 0 2006.246.08:05:41.18#ibcon#wrote, iclass 21, count 0 2006.246.08:05:41.18#ibcon#about to read 3, iclass 21, count 0 2006.246.08:05:41.21#ibcon#read 3, iclass 21, count 0 2006.246.08:05:41.21#ibcon#about to read 4, iclass 21, count 0 2006.246.08:05:41.21#ibcon#read 4, iclass 21, count 0 2006.246.08:05:41.21#ibcon#about to read 5, iclass 21, count 0 2006.246.08:05:41.21#ibcon#read 5, iclass 21, count 0 2006.246.08:05:41.21#ibcon#about to read 6, iclass 21, count 0 2006.246.08:05:41.21#ibcon#read 6, iclass 21, count 0 2006.246.08:05:41.21#ibcon#end of sib2, iclass 21, count 0 2006.246.08:05:41.21#ibcon#*after write, iclass 21, count 0 2006.246.08:05:41.21#ibcon#*before return 0, iclass 21, count 0 2006.246.08:05:41.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:41.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:05:41.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:05:41.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:05:41.21$vc4f8/vblo=3,656.99 2006.246.08:05:41.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:05:41.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:05:41.21#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:41.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:41.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:41.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:41.21#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:05:41.21#ibcon#first serial, iclass 23, count 0 2006.246.08:05:41.21#ibcon#enter sib2, iclass 23, count 0 2006.246.08:05:41.21#ibcon#flushed, iclass 23, count 0 2006.246.08:05:41.21#ibcon#about to write, iclass 23, count 0 2006.246.08:05:41.21#ibcon#wrote, iclass 23, count 0 2006.246.08:05:41.21#ibcon#about to read 3, iclass 23, count 0 2006.246.08:05:41.23#ibcon#read 3, iclass 23, count 0 2006.246.08:05:41.23#ibcon#about to read 4, iclass 23, count 0 2006.246.08:05:41.23#ibcon#read 4, iclass 23, count 0 2006.246.08:05:41.23#ibcon#about to read 5, iclass 23, count 0 2006.246.08:05:41.23#ibcon#read 5, iclass 23, count 0 2006.246.08:05:41.23#ibcon#about to read 6, iclass 23, count 0 2006.246.08:05:41.23#ibcon#read 6, iclass 23, count 0 2006.246.08:05:41.23#ibcon#end of sib2, iclass 23, count 0 2006.246.08:05:41.23#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:05:41.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:05:41.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:05:41.23#ibcon#*before write, iclass 23, count 0 2006.246.08:05:41.23#ibcon#enter sib2, iclass 23, count 0 2006.246.08:05:41.23#ibcon#flushed, iclass 23, count 0 2006.246.08:05:41.23#ibcon#about to write, iclass 23, count 0 2006.246.08:05:41.23#ibcon#wrote, iclass 23, count 0 2006.246.08:05:41.23#ibcon#about to read 3, iclass 23, count 0 2006.246.08:05:41.27#ibcon#read 3, iclass 23, count 0 2006.246.08:05:41.27#ibcon#about to read 4, iclass 23, count 0 2006.246.08:05:41.27#ibcon#read 4, iclass 23, count 0 2006.246.08:05:41.27#ibcon#about to read 5, iclass 23, count 0 2006.246.08:05:41.27#ibcon#read 5, iclass 23, count 0 2006.246.08:05:41.27#ibcon#about to read 6, iclass 23, count 0 2006.246.08:05:41.27#ibcon#read 6, iclass 23, count 0 2006.246.08:05:41.27#ibcon#end of sib2, iclass 23, count 0 2006.246.08:05:41.27#ibcon#*after write, iclass 23, count 0 2006.246.08:05:41.27#ibcon#*before return 0, iclass 23, count 0 2006.246.08:05:41.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:41.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:05:41.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:05:41.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:05:41.27$vc4f8/vb=3,4 2006.246.08:05:41.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:05:41.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:05:41.27#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:41.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:41.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:41.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:41.33#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:05:41.33#ibcon#first serial, iclass 25, count 2 2006.246.08:05:41.33#ibcon#enter sib2, iclass 25, count 2 2006.246.08:05:41.33#ibcon#flushed, iclass 25, count 2 2006.246.08:05:41.33#ibcon#about to write, iclass 25, count 2 2006.246.08:05:41.33#ibcon#wrote, iclass 25, count 2 2006.246.08:05:41.33#ibcon#about to read 3, iclass 25, count 2 2006.246.08:05:41.35#ibcon#read 3, iclass 25, count 2 2006.246.08:05:41.35#ibcon#about to read 4, iclass 25, count 2 2006.246.08:05:41.35#ibcon#read 4, iclass 25, count 2 2006.246.08:05:41.35#ibcon#about to read 5, iclass 25, count 2 2006.246.08:05:41.35#ibcon#read 5, iclass 25, count 2 2006.246.08:05:41.35#ibcon#about to read 6, iclass 25, count 2 2006.246.08:05:41.35#ibcon#read 6, iclass 25, count 2 2006.246.08:05:41.35#ibcon#end of sib2, iclass 25, count 2 2006.246.08:05:41.35#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:05:41.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:05:41.35#ibcon#[27=AT03-04\r\n] 2006.246.08:05:41.35#ibcon#*before write, iclass 25, count 2 2006.246.08:05:41.35#ibcon#enter sib2, iclass 25, count 2 2006.246.08:05:41.35#ibcon#flushed, iclass 25, count 2 2006.246.08:05:41.35#ibcon#about to write, iclass 25, count 2 2006.246.08:05:41.35#ibcon#wrote, iclass 25, count 2 2006.246.08:05:41.35#ibcon#about to read 3, iclass 25, count 2 2006.246.08:05:41.38#ibcon#read 3, iclass 25, count 2 2006.246.08:05:41.38#ibcon#about to read 4, iclass 25, count 2 2006.246.08:05:41.38#ibcon#read 4, iclass 25, count 2 2006.246.08:05:41.38#ibcon#about to read 5, iclass 25, count 2 2006.246.08:05:41.38#ibcon#read 5, iclass 25, count 2 2006.246.08:05:41.38#ibcon#about to read 6, iclass 25, count 2 2006.246.08:05:41.38#ibcon#read 6, iclass 25, count 2 2006.246.08:05:41.38#ibcon#end of sib2, iclass 25, count 2 2006.246.08:05:41.38#ibcon#*after write, iclass 25, count 2 2006.246.08:05:41.38#ibcon#*before return 0, iclass 25, count 2 2006.246.08:05:41.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:41.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:05:41.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:05:41.38#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:41.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:41.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:41.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:41.50#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:05:41.50#ibcon#first serial, iclass 25, count 0 2006.246.08:05:41.50#ibcon#enter sib2, iclass 25, count 0 2006.246.08:05:41.50#ibcon#flushed, iclass 25, count 0 2006.246.08:05:41.50#ibcon#about to write, iclass 25, count 0 2006.246.08:05:41.50#ibcon#wrote, iclass 25, count 0 2006.246.08:05:41.50#ibcon#about to read 3, iclass 25, count 0 2006.246.08:05:41.52#ibcon#read 3, iclass 25, count 0 2006.246.08:05:41.52#ibcon#about to read 4, iclass 25, count 0 2006.246.08:05:41.52#ibcon#read 4, iclass 25, count 0 2006.246.08:05:41.52#ibcon#about to read 5, iclass 25, count 0 2006.246.08:05:41.52#ibcon#read 5, iclass 25, count 0 2006.246.08:05:41.52#ibcon#about to read 6, iclass 25, count 0 2006.246.08:05:41.52#ibcon#read 6, iclass 25, count 0 2006.246.08:05:41.52#ibcon#end of sib2, iclass 25, count 0 2006.246.08:05:41.52#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:05:41.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:05:41.52#ibcon#[27=USB\r\n] 2006.246.08:05:41.52#ibcon#*before write, iclass 25, count 0 2006.246.08:05:41.52#ibcon#enter sib2, iclass 25, count 0 2006.246.08:05:41.52#ibcon#flushed, iclass 25, count 0 2006.246.08:05:41.52#ibcon#about to write, iclass 25, count 0 2006.246.08:05:41.52#ibcon#wrote, iclass 25, count 0 2006.246.08:05:41.52#ibcon#about to read 3, iclass 25, count 0 2006.246.08:05:41.55#ibcon#read 3, iclass 25, count 0 2006.246.08:05:41.55#ibcon#about to read 4, iclass 25, count 0 2006.246.08:05:41.55#ibcon#read 4, iclass 25, count 0 2006.246.08:05:41.55#ibcon#about to read 5, iclass 25, count 0 2006.246.08:05:41.55#ibcon#read 5, iclass 25, count 0 2006.246.08:05:41.55#ibcon#about to read 6, iclass 25, count 0 2006.246.08:05:41.55#ibcon#read 6, iclass 25, count 0 2006.246.08:05:41.55#ibcon#end of sib2, iclass 25, count 0 2006.246.08:05:41.55#ibcon#*after write, iclass 25, count 0 2006.246.08:05:41.55#ibcon#*before return 0, iclass 25, count 0 2006.246.08:05:41.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:41.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:05:41.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:05:41.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:05:41.55$vc4f8/vblo=4,712.99 2006.246.08:05:41.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:05:41.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:05:41.55#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:41.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:41.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:41.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:41.55#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:05:41.55#ibcon#first serial, iclass 27, count 0 2006.246.08:05:41.55#ibcon#enter sib2, iclass 27, count 0 2006.246.08:05:41.55#ibcon#flushed, iclass 27, count 0 2006.246.08:05:41.55#ibcon#about to write, iclass 27, count 0 2006.246.08:05:41.55#ibcon#wrote, iclass 27, count 0 2006.246.08:05:41.55#ibcon#about to read 3, iclass 27, count 0 2006.246.08:05:41.57#ibcon#read 3, iclass 27, count 0 2006.246.08:05:41.57#ibcon#about to read 4, iclass 27, count 0 2006.246.08:05:41.57#ibcon#read 4, iclass 27, count 0 2006.246.08:05:41.57#ibcon#about to read 5, iclass 27, count 0 2006.246.08:05:41.57#ibcon#read 5, iclass 27, count 0 2006.246.08:05:41.57#ibcon#about to read 6, iclass 27, count 0 2006.246.08:05:41.57#ibcon#read 6, iclass 27, count 0 2006.246.08:05:41.57#ibcon#end of sib2, iclass 27, count 0 2006.246.08:05:41.57#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:05:41.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:05:41.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:05:41.57#ibcon#*before write, iclass 27, count 0 2006.246.08:05:41.57#ibcon#enter sib2, iclass 27, count 0 2006.246.08:05:41.57#ibcon#flushed, iclass 27, count 0 2006.246.08:05:41.57#ibcon#about to write, iclass 27, count 0 2006.246.08:05:41.57#ibcon#wrote, iclass 27, count 0 2006.246.08:05:41.57#ibcon#about to read 3, iclass 27, count 0 2006.246.08:05:41.61#ibcon#read 3, iclass 27, count 0 2006.246.08:05:41.61#ibcon#about to read 4, iclass 27, count 0 2006.246.08:05:41.61#ibcon#read 4, iclass 27, count 0 2006.246.08:05:41.61#ibcon#about to read 5, iclass 27, count 0 2006.246.08:05:41.61#ibcon#read 5, iclass 27, count 0 2006.246.08:05:41.61#ibcon#about to read 6, iclass 27, count 0 2006.246.08:05:41.61#ibcon#read 6, iclass 27, count 0 2006.246.08:05:41.61#ibcon#end of sib2, iclass 27, count 0 2006.246.08:05:41.61#ibcon#*after write, iclass 27, count 0 2006.246.08:05:41.61#ibcon#*before return 0, iclass 27, count 0 2006.246.08:05:41.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:41.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:05:41.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:05:41.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:05:41.61$vc4f8/vb=4,4 2006.246.08:05:41.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:05:41.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:05:41.61#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:41.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:41.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:41.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:41.67#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:05:41.67#ibcon#first serial, iclass 29, count 2 2006.246.08:05:41.67#ibcon#enter sib2, iclass 29, count 2 2006.246.08:05:41.67#ibcon#flushed, iclass 29, count 2 2006.246.08:05:41.67#ibcon#about to write, iclass 29, count 2 2006.246.08:05:41.67#ibcon#wrote, iclass 29, count 2 2006.246.08:05:41.67#ibcon#about to read 3, iclass 29, count 2 2006.246.08:05:41.69#ibcon#read 3, iclass 29, count 2 2006.246.08:05:41.69#ibcon#about to read 4, iclass 29, count 2 2006.246.08:05:41.69#ibcon#read 4, iclass 29, count 2 2006.246.08:05:41.69#ibcon#about to read 5, iclass 29, count 2 2006.246.08:05:41.69#ibcon#read 5, iclass 29, count 2 2006.246.08:05:41.69#ibcon#about to read 6, iclass 29, count 2 2006.246.08:05:41.69#ibcon#read 6, iclass 29, count 2 2006.246.08:05:41.69#ibcon#end of sib2, iclass 29, count 2 2006.246.08:05:41.69#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:05:41.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:05:41.69#ibcon#[27=AT04-04\r\n] 2006.246.08:05:41.69#ibcon#*before write, iclass 29, count 2 2006.246.08:05:41.69#ibcon#enter sib2, iclass 29, count 2 2006.246.08:05:41.69#ibcon#flushed, iclass 29, count 2 2006.246.08:05:41.69#ibcon#about to write, iclass 29, count 2 2006.246.08:05:41.69#ibcon#wrote, iclass 29, count 2 2006.246.08:05:41.69#ibcon#about to read 3, iclass 29, count 2 2006.246.08:05:41.72#ibcon#read 3, iclass 29, count 2 2006.246.08:05:41.72#ibcon#about to read 4, iclass 29, count 2 2006.246.08:05:41.72#ibcon#read 4, iclass 29, count 2 2006.246.08:05:41.72#ibcon#about to read 5, iclass 29, count 2 2006.246.08:05:41.72#ibcon#read 5, iclass 29, count 2 2006.246.08:05:41.72#ibcon#about to read 6, iclass 29, count 2 2006.246.08:05:41.72#ibcon#read 6, iclass 29, count 2 2006.246.08:05:41.72#ibcon#end of sib2, iclass 29, count 2 2006.246.08:05:41.72#ibcon#*after write, iclass 29, count 2 2006.246.08:05:41.72#ibcon#*before return 0, iclass 29, count 2 2006.246.08:05:41.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:41.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:05:41.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:05:41.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:41.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:41.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:41.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:41.84#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:05:41.84#ibcon#first serial, iclass 29, count 0 2006.246.08:05:41.84#ibcon#enter sib2, iclass 29, count 0 2006.246.08:05:41.84#ibcon#flushed, iclass 29, count 0 2006.246.08:05:41.84#ibcon#about to write, iclass 29, count 0 2006.246.08:05:41.84#ibcon#wrote, iclass 29, count 0 2006.246.08:05:41.84#ibcon#about to read 3, iclass 29, count 0 2006.246.08:05:41.86#ibcon#read 3, iclass 29, count 0 2006.246.08:05:41.86#ibcon#about to read 4, iclass 29, count 0 2006.246.08:05:41.86#ibcon#read 4, iclass 29, count 0 2006.246.08:05:41.86#ibcon#about to read 5, iclass 29, count 0 2006.246.08:05:41.86#ibcon#read 5, iclass 29, count 0 2006.246.08:05:41.86#ibcon#about to read 6, iclass 29, count 0 2006.246.08:05:41.86#ibcon#read 6, iclass 29, count 0 2006.246.08:05:41.86#ibcon#end of sib2, iclass 29, count 0 2006.246.08:05:41.86#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:05:41.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:05:41.86#ibcon#[27=USB\r\n] 2006.246.08:05:41.86#ibcon#*before write, iclass 29, count 0 2006.246.08:05:41.86#ibcon#enter sib2, iclass 29, count 0 2006.246.08:05:41.86#ibcon#flushed, iclass 29, count 0 2006.246.08:05:41.86#ibcon#about to write, iclass 29, count 0 2006.246.08:05:41.86#ibcon#wrote, iclass 29, count 0 2006.246.08:05:41.86#ibcon#about to read 3, iclass 29, count 0 2006.246.08:05:41.89#ibcon#read 3, iclass 29, count 0 2006.246.08:05:41.89#ibcon#about to read 4, iclass 29, count 0 2006.246.08:05:41.89#ibcon#read 4, iclass 29, count 0 2006.246.08:05:41.89#ibcon#about to read 5, iclass 29, count 0 2006.246.08:05:41.89#ibcon#read 5, iclass 29, count 0 2006.246.08:05:41.89#ibcon#about to read 6, iclass 29, count 0 2006.246.08:05:41.89#ibcon#read 6, iclass 29, count 0 2006.246.08:05:41.89#ibcon#end of sib2, iclass 29, count 0 2006.246.08:05:41.89#ibcon#*after write, iclass 29, count 0 2006.246.08:05:41.89#ibcon#*before return 0, iclass 29, count 0 2006.246.08:05:41.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:41.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:05:41.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:05:41.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:05:41.89$vc4f8/vblo=5,744.99 2006.246.08:05:41.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:05:41.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:05:41.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:41.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:41.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:41.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:41.89#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:05:41.89#ibcon#first serial, iclass 31, count 0 2006.246.08:05:41.89#ibcon#enter sib2, iclass 31, count 0 2006.246.08:05:41.89#ibcon#flushed, iclass 31, count 0 2006.246.08:05:41.89#ibcon#about to write, iclass 31, count 0 2006.246.08:05:41.89#ibcon#wrote, iclass 31, count 0 2006.246.08:05:41.89#ibcon#about to read 3, iclass 31, count 0 2006.246.08:05:41.91#ibcon#read 3, iclass 31, count 0 2006.246.08:05:41.91#ibcon#about to read 4, iclass 31, count 0 2006.246.08:05:41.91#ibcon#read 4, iclass 31, count 0 2006.246.08:05:41.91#ibcon#about to read 5, iclass 31, count 0 2006.246.08:05:41.91#ibcon#read 5, iclass 31, count 0 2006.246.08:05:41.91#ibcon#about to read 6, iclass 31, count 0 2006.246.08:05:41.91#ibcon#read 6, iclass 31, count 0 2006.246.08:05:41.91#ibcon#end of sib2, iclass 31, count 0 2006.246.08:05:41.91#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:05:41.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:05:41.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:05:41.91#ibcon#*before write, iclass 31, count 0 2006.246.08:05:41.91#ibcon#enter sib2, iclass 31, count 0 2006.246.08:05:41.91#ibcon#flushed, iclass 31, count 0 2006.246.08:05:41.91#ibcon#about to write, iclass 31, count 0 2006.246.08:05:41.91#ibcon#wrote, iclass 31, count 0 2006.246.08:05:41.91#ibcon#about to read 3, iclass 31, count 0 2006.246.08:05:41.95#ibcon#read 3, iclass 31, count 0 2006.246.08:05:41.95#ibcon#about to read 4, iclass 31, count 0 2006.246.08:05:41.95#ibcon#read 4, iclass 31, count 0 2006.246.08:05:41.95#ibcon#about to read 5, iclass 31, count 0 2006.246.08:05:41.95#ibcon#read 5, iclass 31, count 0 2006.246.08:05:41.95#ibcon#about to read 6, iclass 31, count 0 2006.246.08:05:41.95#ibcon#read 6, iclass 31, count 0 2006.246.08:05:41.95#ibcon#end of sib2, iclass 31, count 0 2006.246.08:05:41.95#ibcon#*after write, iclass 31, count 0 2006.246.08:05:41.95#ibcon#*before return 0, iclass 31, count 0 2006.246.08:05:41.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:41.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:05:41.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:05:41.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:05:41.95$vc4f8/vb=5,3 2006.246.08:05:41.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:05:41.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:05:41.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:41.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:42.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:42.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:42.01#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:05:42.01#ibcon#first serial, iclass 33, count 2 2006.246.08:05:42.01#ibcon#enter sib2, iclass 33, count 2 2006.246.08:05:42.01#ibcon#flushed, iclass 33, count 2 2006.246.08:05:42.01#ibcon#about to write, iclass 33, count 2 2006.246.08:05:42.01#ibcon#wrote, iclass 33, count 2 2006.246.08:05:42.01#ibcon#about to read 3, iclass 33, count 2 2006.246.08:05:42.03#ibcon#read 3, iclass 33, count 2 2006.246.08:05:42.03#ibcon#about to read 4, iclass 33, count 2 2006.246.08:05:42.03#ibcon#read 4, iclass 33, count 2 2006.246.08:05:42.03#ibcon#about to read 5, iclass 33, count 2 2006.246.08:05:42.03#ibcon#read 5, iclass 33, count 2 2006.246.08:05:42.03#ibcon#about to read 6, iclass 33, count 2 2006.246.08:05:42.03#ibcon#read 6, iclass 33, count 2 2006.246.08:05:42.03#ibcon#end of sib2, iclass 33, count 2 2006.246.08:05:42.03#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:05:42.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:05:42.03#ibcon#[27=AT05-03\r\n] 2006.246.08:05:42.03#ibcon#*before write, iclass 33, count 2 2006.246.08:05:42.03#ibcon#enter sib2, iclass 33, count 2 2006.246.08:05:42.03#ibcon#flushed, iclass 33, count 2 2006.246.08:05:42.03#ibcon#about to write, iclass 33, count 2 2006.246.08:05:42.03#ibcon#wrote, iclass 33, count 2 2006.246.08:05:42.03#ibcon#about to read 3, iclass 33, count 2 2006.246.08:05:42.05#abcon#<5=/04 3.3 6.5 26.51 751005.7\r\n> 2006.246.08:05:42.06#ibcon#read 3, iclass 33, count 2 2006.246.08:05:42.06#ibcon#about to read 4, iclass 33, count 2 2006.246.08:05:42.06#ibcon#read 4, iclass 33, count 2 2006.246.08:05:42.06#ibcon#about to read 5, iclass 33, count 2 2006.246.08:05:42.06#ibcon#read 5, iclass 33, count 2 2006.246.08:05:42.06#ibcon#about to read 6, iclass 33, count 2 2006.246.08:05:42.06#ibcon#read 6, iclass 33, count 2 2006.246.08:05:42.06#ibcon#end of sib2, iclass 33, count 2 2006.246.08:05:42.06#ibcon#*after write, iclass 33, count 2 2006.246.08:05:42.06#ibcon#*before return 0, iclass 33, count 2 2006.246.08:05:42.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:42.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:05:42.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:05:42.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:42.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:42.07#abcon#{5=INTERFACE CLEAR} 2006.246.08:05:42.13#abcon#[5=S1D000X0/0*\r\n] 2006.246.08:05:42.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:42.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:42.18#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:05:42.18#ibcon#first serial, iclass 33, count 0 2006.246.08:05:42.18#ibcon#enter sib2, iclass 33, count 0 2006.246.08:05:42.18#ibcon#flushed, iclass 33, count 0 2006.246.08:05:42.18#ibcon#about to write, iclass 33, count 0 2006.246.08:05:42.18#ibcon#wrote, iclass 33, count 0 2006.246.08:05:42.18#ibcon#about to read 3, iclass 33, count 0 2006.246.08:05:42.20#ibcon#read 3, iclass 33, count 0 2006.246.08:05:42.20#ibcon#about to read 4, iclass 33, count 0 2006.246.08:05:42.20#ibcon#read 4, iclass 33, count 0 2006.246.08:05:42.20#ibcon#about to read 5, iclass 33, count 0 2006.246.08:05:42.20#ibcon#read 5, iclass 33, count 0 2006.246.08:05:42.20#ibcon#about to read 6, iclass 33, count 0 2006.246.08:05:42.20#ibcon#read 6, iclass 33, count 0 2006.246.08:05:42.20#ibcon#end of sib2, iclass 33, count 0 2006.246.08:05:42.20#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:05:42.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:05:42.20#ibcon#[27=USB\r\n] 2006.246.08:05:42.20#ibcon#*before write, iclass 33, count 0 2006.246.08:05:42.20#ibcon#enter sib2, iclass 33, count 0 2006.246.08:05:42.20#ibcon#flushed, iclass 33, count 0 2006.246.08:05:42.20#ibcon#about to write, iclass 33, count 0 2006.246.08:05:42.20#ibcon#wrote, iclass 33, count 0 2006.246.08:05:42.20#ibcon#about to read 3, iclass 33, count 0 2006.246.08:05:42.23#ibcon#read 3, iclass 33, count 0 2006.246.08:05:42.23#ibcon#about to read 4, iclass 33, count 0 2006.246.08:05:42.23#ibcon#read 4, iclass 33, count 0 2006.246.08:05:42.23#ibcon#about to read 5, iclass 33, count 0 2006.246.08:05:42.23#ibcon#read 5, iclass 33, count 0 2006.246.08:05:42.23#ibcon#about to read 6, iclass 33, count 0 2006.246.08:05:42.23#ibcon#read 6, iclass 33, count 0 2006.246.08:05:42.23#ibcon#end of sib2, iclass 33, count 0 2006.246.08:05:42.23#ibcon#*after write, iclass 33, count 0 2006.246.08:05:42.23#ibcon#*before return 0, iclass 33, count 0 2006.246.08:05:42.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:42.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:05:42.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:05:42.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:05:42.23$vc4f8/vblo=6,752.99 2006.246.08:05:42.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:05:42.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:05:42.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:05:42.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:42.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:42.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:42.23#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:05:42.23#ibcon#first serial, iclass 39, count 0 2006.246.08:05:42.23#ibcon#enter sib2, iclass 39, count 0 2006.246.08:05:42.23#ibcon#flushed, iclass 39, count 0 2006.246.08:05:42.23#ibcon#about to write, iclass 39, count 0 2006.246.08:05:42.23#ibcon#wrote, iclass 39, count 0 2006.246.08:05:42.23#ibcon#about to read 3, iclass 39, count 0 2006.246.08:05:42.25#ibcon#read 3, iclass 39, count 0 2006.246.08:05:42.25#ibcon#about to read 4, iclass 39, count 0 2006.246.08:05:42.25#ibcon#read 4, iclass 39, count 0 2006.246.08:05:42.25#ibcon#about to read 5, iclass 39, count 0 2006.246.08:05:42.25#ibcon#read 5, iclass 39, count 0 2006.246.08:05:42.25#ibcon#about to read 6, iclass 39, count 0 2006.246.08:05:42.25#ibcon#read 6, iclass 39, count 0 2006.246.08:05:42.25#ibcon#end of sib2, iclass 39, count 0 2006.246.08:05:42.25#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:05:42.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:05:42.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:05:42.25#ibcon#*before write, iclass 39, count 0 2006.246.08:05:42.25#ibcon#enter sib2, iclass 39, count 0 2006.246.08:05:42.25#ibcon#flushed, iclass 39, count 0 2006.246.08:05:42.25#ibcon#about to write, iclass 39, count 0 2006.246.08:05:42.25#ibcon#wrote, iclass 39, count 0 2006.246.08:05:42.25#ibcon#about to read 3, iclass 39, count 0 2006.246.08:05:42.29#ibcon#read 3, iclass 39, count 0 2006.246.08:05:42.29#ibcon#about to read 4, iclass 39, count 0 2006.246.08:05:42.29#ibcon#read 4, iclass 39, count 0 2006.246.08:05:42.29#ibcon#about to read 5, iclass 39, count 0 2006.246.08:05:42.29#ibcon#read 5, iclass 39, count 0 2006.246.08:05:42.29#ibcon#about to read 6, iclass 39, count 0 2006.246.08:05:42.29#ibcon#read 6, iclass 39, count 0 2006.246.08:05:42.29#ibcon#end of sib2, iclass 39, count 0 2006.246.08:05:42.29#ibcon#*after write, iclass 39, count 0 2006.246.08:05:42.29#ibcon#*before return 0, iclass 39, count 0 2006.246.08:05:42.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:42.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:05:42.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:05:42.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:05:42.29$vc4f8/vb=6,3 2006.246.08:05:42.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:05:42.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:05:42.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:05:42.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:42.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:42.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:42.35#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:05:42.35#ibcon#first serial, iclass 3, count 2 2006.246.08:05:42.35#ibcon#enter sib2, iclass 3, count 2 2006.246.08:05:42.35#ibcon#flushed, iclass 3, count 2 2006.246.08:05:42.35#ibcon#about to write, iclass 3, count 2 2006.246.08:05:42.35#ibcon#wrote, iclass 3, count 2 2006.246.08:05:42.35#ibcon#about to read 3, iclass 3, count 2 2006.246.08:05:42.37#ibcon#read 3, iclass 3, count 2 2006.246.08:05:42.37#ibcon#about to read 4, iclass 3, count 2 2006.246.08:05:42.37#ibcon#read 4, iclass 3, count 2 2006.246.08:05:42.37#ibcon#about to read 5, iclass 3, count 2 2006.246.08:05:42.37#ibcon#read 5, iclass 3, count 2 2006.246.08:05:42.37#ibcon#about to read 6, iclass 3, count 2 2006.246.08:05:42.37#ibcon#read 6, iclass 3, count 2 2006.246.08:05:42.37#ibcon#end of sib2, iclass 3, count 2 2006.246.08:05:42.37#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:05:42.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:05:42.37#ibcon#[27=AT06-03\r\n] 2006.246.08:05:42.37#ibcon#*before write, iclass 3, count 2 2006.246.08:05:42.37#ibcon#enter sib2, iclass 3, count 2 2006.246.08:05:42.37#ibcon#flushed, iclass 3, count 2 2006.246.08:05:42.37#ibcon#about to write, iclass 3, count 2 2006.246.08:05:42.37#ibcon#wrote, iclass 3, count 2 2006.246.08:05:42.37#ibcon#about to read 3, iclass 3, count 2 2006.246.08:05:42.40#ibcon#read 3, iclass 3, count 2 2006.246.08:05:42.40#ibcon#about to read 4, iclass 3, count 2 2006.246.08:05:42.40#ibcon#read 4, iclass 3, count 2 2006.246.08:05:42.40#ibcon#about to read 5, iclass 3, count 2 2006.246.08:05:42.40#ibcon#read 5, iclass 3, count 2 2006.246.08:05:42.40#ibcon#about to read 6, iclass 3, count 2 2006.246.08:05:42.40#ibcon#read 6, iclass 3, count 2 2006.246.08:05:42.40#ibcon#end of sib2, iclass 3, count 2 2006.246.08:05:42.40#ibcon#*after write, iclass 3, count 2 2006.246.08:05:42.40#ibcon#*before return 0, iclass 3, count 2 2006.246.08:05:42.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:42.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:05:42.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:05:42.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:05:42.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:42.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:42.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:42.52#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:05:42.52#ibcon#first serial, iclass 3, count 0 2006.246.08:05:42.52#ibcon#enter sib2, iclass 3, count 0 2006.246.08:05:42.52#ibcon#flushed, iclass 3, count 0 2006.246.08:05:42.52#ibcon#about to write, iclass 3, count 0 2006.246.08:05:42.52#ibcon#wrote, iclass 3, count 0 2006.246.08:05:42.52#ibcon#about to read 3, iclass 3, count 0 2006.246.08:05:42.54#ibcon#read 3, iclass 3, count 0 2006.246.08:05:42.54#ibcon#about to read 4, iclass 3, count 0 2006.246.08:05:42.54#ibcon#read 4, iclass 3, count 0 2006.246.08:05:42.54#ibcon#about to read 5, iclass 3, count 0 2006.246.08:05:42.54#ibcon#read 5, iclass 3, count 0 2006.246.08:05:42.54#ibcon#about to read 6, iclass 3, count 0 2006.246.08:05:42.54#ibcon#read 6, iclass 3, count 0 2006.246.08:05:42.54#ibcon#end of sib2, iclass 3, count 0 2006.246.08:05:42.54#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:05:42.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:05:42.54#ibcon#[27=USB\r\n] 2006.246.08:05:42.54#ibcon#*before write, iclass 3, count 0 2006.246.08:05:42.54#ibcon#enter sib2, iclass 3, count 0 2006.246.08:05:42.54#ibcon#flushed, iclass 3, count 0 2006.246.08:05:42.54#ibcon#about to write, iclass 3, count 0 2006.246.08:05:42.54#ibcon#wrote, iclass 3, count 0 2006.246.08:05:42.54#ibcon#about to read 3, iclass 3, count 0 2006.246.08:05:42.57#ibcon#read 3, iclass 3, count 0 2006.246.08:05:42.57#ibcon#about to read 4, iclass 3, count 0 2006.246.08:05:42.57#ibcon#read 4, iclass 3, count 0 2006.246.08:05:42.57#ibcon#about to read 5, iclass 3, count 0 2006.246.08:05:42.57#ibcon#read 5, iclass 3, count 0 2006.246.08:05:42.57#ibcon#about to read 6, iclass 3, count 0 2006.246.08:05:42.57#ibcon#read 6, iclass 3, count 0 2006.246.08:05:42.57#ibcon#end of sib2, iclass 3, count 0 2006.246.08:05:42.57#ibcon#*after write, iclass 3, count 0 2006.246.08:05:42.57#ibcon#*before return 0, iclass 3, count 0 2006.246.08:05:42.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:42.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:05:42.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:05:42.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:05:42.57$vc4f8/vabw=wide 2006.246.08:05:42.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:05:42.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:05:42.57#ibcon#ireg 8 cls_cnt 0 2006.246.08:05:42.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:42.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:42.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:42.57#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:05:42.57#ibcon#first serial, iclass 5, count 0 2006.246.08:05:42.57#ibcon#enter sib2, iclass 5, count 0 2006.246.08:05:42.57#ibcon#flushed, iclass 5, count 0 2006.246.08:05:42.57#ibcon#about to write, iclass 5, count 0 2006.246.08:05:42.57#ibcon#wrote, iclass 5, count 0 2006.246.08:05:42.57#ibcon#about to read 3, iclass 5, count 0 2006.246.08:05:42.59#ibcon#read 3, iclass 5, count 0 2006.246.08:05:42.59#ibcon#about to read 4, iclass 5, count 0 2006.246.08:05:42.59#ibcon#read 4, iclass 5, count 0 2006.246.08:05:42.59#ibcon#about to read 5, iclass 5, count 0 2006.246.08:05:42.59#ibcon#read 5, iclass 5, count 0 2006.246.08:05:42.59#ibcon#about to read 6, iclass 5, count 0 2006.246.08:05:42.59#ibcon#read 6, iclass 5, count 0 2006.246.08:05:42.59#ibcon#end of sib2, iclass 5, count 0 2006.246.08:05:42.59#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:05:42.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:05:42.59#ibcon#[25=BW32\r\n] 2006.246.08:05:42.59#ibcon#*before write, iclass 5, count 0 2006.246.08:05:42.59#ibcon#enter sib2, iclass 5, count 0 2006.246.08:05:42.59#ibcon#flushed, iclass 5, count 0 2006.246.08:05:42.59#ibcon#about to write, iclass 5, count 0 2006.246.08:05:42.59#ibcon#wrote, iclass 5, count 0 2006.246.08:05:42.59#ibcon#about to read 3, iclass 5, count 0 2006.246.08:05:42.62#ibcon#read 3, iclass 5, count 0 2006.246.08:05:42.62#ibcon#about to read 4, iclass 5, count 0 2006.246.08:05:42.62#ibcon#read 4, iclass 5, count 0 2006.246.08:05:42.62#ibcon#about to read 5, iclass 5, count 0 2006.246.08:05:42.62#ibcon#read 5, iclass 5, count 0 2006.246.08:05:42.62#ibcon#about to read 6, iclass 5, count 0 2006.246.08:05:42.62#ibcon#read 6, iclass 5, count 0 2006.246.08:05:42.62#ibcon#end of sib2, iclass 5, count 0 2006.246.08:05:42.62#ibcon#*after write, iclass 5, count 0 2006.246.08:05:42.62#ibcon#*before return 0, iclass 5, count 0 2006.246.08:05:42.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:42.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:05:42.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:05:42.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:05:42.62$vc4f8/vbbw=wide 2006.246.08:05:42.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.08:05:42.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.08:05:42.62#ibcon#ireg 8 cls_cnt 0 2006.246.08:05:42.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:05:42.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:05:42.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:05:42.69#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:05:42.69#ibcon#first serial, iclass 7, count 0 2006.246.08:05:42.69#ibcon#enter sib2, iclass 7, count 0 2006.246.08:05:42.69#ibcon#flushed, iclass 7, count 0 2006.246.08:05:42.69#ibcon#about to write, iclass 7, count 0 2006.246.08:05:42.69#ibcon#wrote, iclass 7, count 0 2006.246.08:05:42.69#ibcon#about to read 3, iclass 7, count 0 2006.246.08:05:42.71#ibcon#read 3, iclass 7, count 0 2006.246.08:05:42.71#ibcon#about to read 4, iclass 7, count 0 2006.246.08:05:42.71#ibcon#read 4, iclass 7, count 0 2006.246.08:05:42.71#ibcon#about to read 5, iclass 7, count 0 2006.246.08:05:42.71#ibcon#read 5, iclass 7, count 0 2006.246.08:05:42.71#ibcon#about to read 6, iclass 7, count 0 2006.246.08:05:42.71#ibcon#read 6, iclass 7, count 0 2006.246.08:05:42.71#ibcon#end of sib2, iclass 7, count 0 2006.246.08:05:42.71#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:05:42.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:05:42.71#ibcon#[27=BW32\r\n] 2006.246.08:05:42.71#ibcon#*before write, iclass 7, count 0 2006.246.08:05:42.71#ibcon#enter sib2, iclass 7, count 0 2006.246.08:05:42.71#ibcon#flushed, iclass 7, count 0 2006.246.08:05:42.71#ibcon#about to write, iclass 7, count 0 2006.246.08:05:42.71#ibcon#wrote, iclass 7, count 0 2006.246.08:05:42.71#ibcon#about to read 3, iclass 7, count 0 2006.246.08:05:42.74#ibcon#read 3, iclass 7, count 0 2006.246.08:05:42.74#ibcon#about to read 4, iclass 7, count 0 2006.246.08:05:42.74#ibcon#read 4, iclass 7, count 0 2006.246.08:05:42.74#ibcon#about to read 5, iclass 7, count 0 2006.246.08:05:42.74#ibcon#read 5, iclass 7, count 0 2006.246.08:05:42.74#ibcon#about to read 6, iclass 7, count 0 2006.246.08:05:42.74#ibcon#read 6, iclass 7, count 0 2006.246.08:05:42.74#ibcon#end of sib2, iclass 7, count 0 2006.246.08:05:42.74#ibcon#*after write, iclass 7, count 0 2006.246.08:05:42.74#ibcon#*before return 0, iclass 7, count 0 2006.246.08:05:42.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:05:42.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:05:42.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:05:42.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:05:42.74$4f8m12a/ifd4f 2006.246.08:05:42.74$ifd4f/lo= 2006.246.08:05:42.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:05:42.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:05:42.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:05:42.74$ifd4f/patch= 2006.246.08:05:42.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:05:42.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:05:42.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:05:42.74$4f8m12a/"form=m,16.000,1:2 2006.246.08:05:42.74$4f8m12a/"tpicd 2006.246.08:05:42.74$4f8m12a/echo=off 2006.246.08:05:42.74$4f8m12a/xlog=off 2006.246.08:05:42.74:!2006.246.08:06:10 2006.246.08:05:55.14#trakl#Source acquired 2006.246.08:05:55.14#flagr#flagr/antenna,acquired 2006.246.08:06:10.00:preob 2006.246.08:06:11.14/onsource/TRACKING 2006.246.08:06:11.14:!2006.246.08:06:20 2006.246.08:06:20.00:data_valid=on 2006.246.08:06:20.00:midob 2006.246.08:06:20.14/onsource/TRACKING 2006.246.08:06:20.14/wx/26.51,1005.7,74 2006.246.08:06:20.29/cable/+6.4146E-03 2006.246.08:06:21.38/va/01,08,usb,yes,34,36 2006.246.08:06:21.38/va/02,07,usb,yes,34,36 2006.246.08:06:21.38/va/03,06,usb,yes,36,36 2006.246.08:06:21.38/va/04,07,usb,yes,35,38 2006.246.08:06:21.38/va/05,07,usb,yes,38,40 2006.246.08:06:21.38/va/06,07,usb,yes,33,33 2006.246.08:06:21.38/va/07,07,usb,yes,33,33 2006.246.08:06:21.38/va/08,08,usb,yes,29,28 2006.246.08:06:21.61/valo/01,532.99,yes,locked 2006.246.08:06:21.61/valo/02,572.99,yes,locked 2006.246.08:06:21.61/valo/03,672.99,yes,locked 2006.246.08:06:21.61/valo/04,832.99,yes,locked 2006.246.08:06:21.61/valo/05,652.99,yes,locked 2006.246.08:06:21.61/valo/06,772.99,yes,locked 2006.246.08:06:21.61/valo/07,832.99,yes,locked 2006.246.08:06:21.61/valo/08,852.99,yes,locked 2006.246.08:06:22.70/vb/01,04,usb,yes,33,32 2006.246.08:06:22.70/vb/02,04,usb,yes,35,36 2006.246.08:06:22.70/vb/03,04,usb,yes,31,35 2006.246.08:06:22.70/vb/04,04,usb,yes,33,33 2006.246.08:06:22.70/vb/05,03,usb,yes,38,46 2006.246.08:06:22.70/vb/06,03,usb,yes,39,43 2006.246.08:06:22.70/vb/07,04,usb,yes,34,37 2006.246.08:06:22.70/vb/08,03,usb,yes,39,45 2006.246.08:06:22.93/vblo/01,632.99,yes,locked 2006.246.08:06:22.93/vblo/02,640.99,yes,locked 2006.246.08:06:22.93/vblo/03,656.99,yes,locked 2006.246.08:06:22.93/vblo/04,712.99,yes,locked 2006.246.08:06:22.93/vblo/05,744.99,yes,locked 2006.246.08:06:22.93/vblo/06,752.99,yes,locked 2006.246.08:06:22.93/vblo/07,734.99,yes,locked 2006.246.08:06:22.93/vblo/08,744.99,yes,locked 2006.246.08:06:23.08/vabw/8 2006.246.08:06:23.23/vbbw/8 2006.246.08:06:23.34/xfe/off,on,13.2 2006.246.08:06:23.72/ifatt/23,28,28,28 2006.246.08:06:24.07/fmout-gps/S +4.40E-07 2006.246.08:06:24.11:!2006.246.08:07:20 2006.246.08:07:20.00:data_valid=off 2006.246.08:07:20.00:postob 2006.246.08:07:20.17/cable/+6.4136E-03 2006.246.08:07:20.17/wx/26.49,1005.7,75 2006.246.08:07:21.07/fmout-gps/S +4.39E-07 2006.246.08:07:21.07:scan_name=246-0808,k06246,60 2006.246.08:07:21.07:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.246.08:07:21.14#flagr#flagr/antenna,new-source 2006.246.08:07:22.14:checkk5 2006.246.08:07:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:07:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:07:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:07:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:07:24.01/chk_obsdata//k5ts1/T2460806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:07:24.38/chk_obsdata//k5ts2/T2460806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:07:24.75/chk_obsdata//k5ts3/T2460806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:07:25.12/chk_obsdata//k5ts4/T2460806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:07:25.82/k5log//k5ts1_log_newline 2006.246.08:07:26.51/k5log//k5ts2_log_newline 2006.246.08:07:27.19/k5log//k5ts3_log_newline 2006.246.08:07:27.88/k5log//k5ts4_log_newline 2006.246.08:07:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:07:27.91:4f8m12a=2 2006.246.08:07:27.91$4f8m12a/echo=on 2006.246.08:07:27.91$4f8m12a/pcalon 2006.246.08:07:27.91$pcalon/"no phase cal control is implemented here 2006.246.08:07:27.91$4f8m12a/"tpicd=stop 2006.246.08:07:27.91$4f8m12a/vc4f8 2006.246.08:07:27.91$vc4f8/valo=1,532.99 2006.246.08:07:27.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.08:07:27.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.08:07:27.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:27.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:27.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:27.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:27.91#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:07:27.91#ibcon#first serial, iclass 16, count 0 2006.246.08:07:27.91#ibcon#enter sib2, iclass 16, count 0 2006.246.08:07:27.91#ibcon#flushed, iclass 16, count 0 2006.246.08:07:27.91#ibcon#about to write, iclass 16, count 0 2006.246.08:07:27.91#ibcon#wrote, iclass 16, count 0 2006.246.08:07:27.91#ibcon#about to read 3, iclass 16, count 0 2006.246.08:07:27.95#ibcon#read 3, iclass 16, count 0 2006.246.08:07:27.95#ibcon#about to read 4, iclass 16, count 0 2006.246.08:07:27.95#ibcon#read 4, iclass 16, count 0 2006.246.08:07:27.95#ibcon#about to read 5, iclass 16, count 0 2006.246.08:07:27.95#ibcon#read 5, iclass 16, count 0 2006.246.08:07:27.95#ibcon#about to read 6, iclass 16, count 0 2006.246.08:07:27.95#ibcon#read 6, iclass 16, count 0 2006.246.08:07:27.95#ibcon#end of sib2, iclass 16, count 0 2006.246.08:07:27.95#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:07:27.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:07:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:07:27.95#ibcon#*before write, iclass 16, count 0 2006.246.08:07:27.95#ibcon#enter sib2, iclass 16, count 0 2006.246.08:07:27.95#ibcon#flushed, iclass 16, count 0 2006.246.08:07:27.95#ibcon#about to write, iclass 16, count 0 2006.246.08:07:27.95#ibcon#wrote, iclass 16, count 0 2006.246.08:07:27.95#ibcon#about to read 3, iclass 16, count 0 2006.246.08:07:28.00#ibcon#read 3, iclass 16, count 0 2006.246.08:07:28.00#ibcon#about to read 4, iclass 16, count 0 2006.246.08:07:28.00#ibcon#read 4, iclass 16, count 0 2006.246.08:07:28.00#ibcon#about to read 5, iclass 16, count 0 2006.246.08:07:28.00#ibcon#read 5, iclass 16, count 0 2006.246.08:07:28.00#ibcon#about to read 6, iclass 16, count 0 2006.246.08:07:28.00#ibcon#read 6, iclass 16, count 0 2006.246.08:07:28.00#ibcon#end of sib2, iclass 16, count 0 2006.246.08:07:28.00#ibcon#*after write, iclass 16, count 0 2006.246.08:07:28.00#ibcon#*before return 0, iclass 16, count 0 2006.246.08:07:28.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:28.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:28.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:07:28.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:07:28.00$vc4f8/va=1,8 2006.246.08:07:28.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.08:07:28.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.08:07:28.00#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:28.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:28.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:28.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:28.00#ibcon#enter wrdev, iclass 18, count 2 2006.246.08:07:28.00#ibcon#first serial, iclass 18, count 2 2006.246.08:07:28.00#ibcon#enter sib2, iclass 18, count 2 2006.246.08:07:28.00#ibcon#flushed, iclass 18, count 2 2006.246.08:07:28.00#ibcon#about to write, iclass 18, count 2 2006.246.08:07:28.00#ibcon#wrote, iclass 18, count 2 2006.246.08:07:28.00#ibcon#about to read 3, iclass 18, count 2 2006.246.08:07:28.02#ibcon#read 3, iclass 18, count 2 2006.246.08:07:28.02#ibcon#about to read 4, iclass 18, count 2 2006.246.08:07:28.02#ibcon#read 4, iclass 18, count 2 2006.246.08:07:28.02#ibcon#about to read 5, iclass 18, count 2 2006.246.08:07:28.02#ibcon#read 5, iclass 18, count 2 2006.246.08:07:28.02#ibcon#about to read 6, iclass 18, count 2 2006.246.08:07:28.02#ibcon#read 6, iclass 18, count 2 2006.246.08:07:28.02#ibcon#end of sib2, iclass 18, count 2 2006.246.08:07:28.02#ibcon#*mode == 0, iclass 18, count 2 2006.246.08:07:28.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.08:07:28.02#ibcon#[25=AT01-08\r\n] 2006.246.08:07:28.02#ibcon#*before write, iclass 18, count 2 2006.246.08:07:28.02#ibcon#enter sib2, iclass 18, count 2 2006.246.08:07:28.02#ibcon#flushed, iclass 18, count 2 2006.246.08:07:28.02#ibcon#about to write, iclass 18, count 2 2006.246.08:07:28.02#ibcon#wrote, iclass 18, count 2 2006.246.08:07:28.02#ibcon#about to read 3, iclass 18, count 2 2006.246.08:07:28.05#ibcon#read 3, iclass 18, count 2 2006.246.08:07:28.05#ibcon#about to read 4, iclass 18, count 2 2006.246.08:07:28.05#ibcon#read 4, iclass 18, count 2 2006.246.08:07:28.05#ibcon#about to read 5, iclass 18, count 2 2006.246.08:07:28.05#ibcon#read 5, iclass 18, count 2 2006.246.08:07:28.05#ibcon#about to read 6, iclass 18, count 2 2006.246.08:07:28.05#ibcon#read 6, iclass 18, count 2 2006.246.08:07:28.05#ibcon#end of sib2, iclass 18, count 2 2006.246.08:07:28.05#ibcon#*after write, iclass 18, count 2 2006.246.08:07:28.05#ibcon#*before return 0, iclass 18, count 2 2006.246.08:07:28.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:28.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:28.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.08:07:28.05#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:28.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:28.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:28.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:28.17#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:07:28.17#ibcon#first serial, iclass 18, count 0 2006.246.08:07:28.17#ibcon#enter sib2, iclass 18, count 0 2006.246.08:07:28.17#ibcon#flushed, iclass 18, count 0 2006.246.08:07:28.17#ibcon#about to write, iclass 18, count 0 2006.246.08:07:28.17#ibcon#wrote, iclass 18, count 0 2006.246.08:07:28.17#ibcon#about to read 3, iclass 18, count 0 2006.246.08:07:28.19#ibcon#read 3, iclass 18, count 0 2006.246.08:07:28.19#ibcon#about to read 4, iclass 18, count 0 2006.246.08:07:28.19#ibcon#read 4, iclass 18, count 0 2006.246.08:07:28.19#ibcon#about to read 5, iclass 18, count 0 2006.246.08:07:28.19#ibcon#read 5, iclass 18, count 0 2006.246.08:07:28.19#ibcon#about to read 6, iclass 18, count 0 2006.246.08:07:28.19#ibcon#read 6, iclass 18, count 0 2006.246.08:07:28.19#ibcon#end of sib2, iclass 18, count 0 2006.246.08:07:28.19#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:07:28.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:07:28.19#ibcon#[25=USB\r\n] 2006.246.08:07:28.19#ibcon#*before write, iclass 18, count 0 2006.246.08:07:28.19#ibcon#enter sib2, iclass 18, count 0 2006.246.08:07:28.19#ibcon#flushed, iclass 18, count 0 2006.246.08:07:28.19#ibcon#about to write, iclass 18, count 0 2006.246.08:07:28.19#ibcon#wrote, iclass 18, count 0 2006.246.08:07:28.19#ibcon#about to read 3, iclass 18, count 0 2006.246.08:07:28.22#ibcon#read 3, iclass 18, count 0 2006.246.08:07:28.22#ibcon#about to read 4, iclass 18, count 0 2006.246.08:07:28.22#ibcon#read 4, iclass 18, count 0 2006.246.08:07:28.22#ibcon#about to read 5, iclass 18, count 0 2006.246.08:07:28.22#ibcon#read 5, iclass 18, count 0 2006.246.08:07:28.22#ibcon#about to read 6, iclass 18, count 0 2006.246.08:07:28.22#ibcon#read 6, iclass 18, count 0 2006.246.08:07:28.22#ibcon#end of sib2, iclass 18, count 0 2006.246.08:07:28.22#ibcon#*after write, iclass 18, count 0 2006.246.08:07:28.22#ibcon#*before return 0, iclass 18, count 0 2006.246.08:07:28.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:28.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:28.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:07:28.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:07:28.22$vc4f8/valo=2,572.99 2006.246.08:07:28.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.08:07:28.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.08:07:28.22#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:28.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:28.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:28.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:28.22#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:07:28.22#ibcon#first serial, iclass 20, count 0 2006.246.08:07:28.22#ibcon#enter sib2, iclass 20, count 0 2006.246.08:07:28.22#ibcon#flushed, iclass 20, count 0 2006.246.08:07:28.22#ibcon#about to write, iclass 20, count 0 2006.246.08:07:28.22#ibcon#wrote, iclass 20, count 0 2006.246.08:07:28.22#ibcon#about to read 3, iclass 20, count 0 2006.246.08:07:28.24#ibcon#read 3, iclass 20, count 0 2006.246.08:07:28.24#ibcon#about to read 4, iclass 20, count 0 2006.246.08:07:28.24#ibcon#read 4, iclass 20, count 0 2006.246.08:07:28.24#ibcon#about to read 5, iclass 20, count 0 2006.246.08:07:28.24#ibcon#read 5, iclass 20, count 0 2006.246.08:07:28.24#ibcon#about to read 6, iclass 20, count 0 2006.246.08:07:28.24#ibcon#read 6, iclass 20, count 0 2006.246.08:07:28.24#ibcon#end of sib2, iclass 20, count 0 2006.246.08:07:28.24#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:07:28.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:07:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:07:28.24#ibcon#*before write, iclass 20, count 0 2006.246.08:07:28.24#ibcon#enter sib2, iclass 20, count 0 2006.246.08:07:28.24#ibcon#flushed, iclass 20, count 0 2006.246.08:07:28.24#ibcon#about to write, iclass 20, count 0 2006.246.08:07:28.24#ibcon#wrote, iclass 20, count 0 2006.246.08:07:28.24#ibcon#about to read 3, iclass 20, count 0 2006.246.08:07:28.28#ibcon#read 3, iclass 20, count 0 2006.246.08:07:28.28#ibcon#about to read 4, iclass 20, count 0 2006.246.08:07:28.28#ibcon#read 4, iclass 20, count 0 2006.246.08:07:28.28#ibcon#about to read 5, iclass 20, count 0 2006.246.08:07:28.28#ibcon#read 5, iclass 20, count 0 2006.246.08:07:28.28#ibcon#about to read 6, iclass 20, count 0 2006.246.08:07:28.28#ibcon#read 6, iclass 20, count 0 2006.246.08:07:28.28#ibcon#end of sib2, iclass 20, count 0 2006.246.08:07:28.28#ibcon#*after write, iclass 20, count 0 2006.246.08:07:28.28#ibcon#*before return 0, iclass 20, count 0 2006.246.08:07:28.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:28.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:28.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:07:28.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:07:28.28$vc4f8/va=2,7 2006.246.08:07:28.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.08:07:28.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.08:07:28.28#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:28.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:28.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:28.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:28.34#ibcon#enter wrdev, iclass 22, count 2 2006.246.08:07:28.34#ibcon#first serial, iclass 22, count 2 2006.246.08:07:28.34#ibcon#enter sib2, iclass 22, count 2 2006.246.08:07:28.34#ibcon#flushed, iclass 22, count 2 2006.246.08:07:28.34#ibcon#about to write, iclass 22, count 2 2006.246.08:07:28.34#ibcon#wrote, iclass 22, count 2 2006.246.08:07:28.34#ibcon#about to read 3, iclass 22, count 2 2006.246.08:07:28.36#ibcon#read 3, iclass 22, count 2 2006.246.08:07:28.36#ibcon#about to read 4, iclass 22, count 2 2006.246.08:07:28.36#ibcon#read 4, iclass 22, count 2 2006.246.08:07:28.36#ibcon#about to read 5, iclass 22, count 2 2006.246.08:07:28.36#ibcon#read 5, iclass 22, count 2 2006.246.08:07:28.36#ibcon#about to read 6, iclass 22, count 2 2006.246.08:07:28.36#ibcon#read 6, iclass 22, count 2 2006.246.08:07:28.36#ibcon#end of sib2, iclass 22, count 2 2006.246.08:07:28.36#ibcon#*mode == 0, iclass 22, count 2 2006.246.08:07:28.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.08:07:28.36#ibcon#[25=AT02-07\r\n] 2006.246.08:07:28.36#ibcon#*before write, iclass 22, count 2 2006.246.08:07:28.36#ibcon#enter sib2, iclass 22, count 2 2006.246.08:07:28.36#ibcon#flushed, iclass 22, count 2 2006.246.08:07:28.36#ibcon#about to write, iclass 22, count 2 2006.246.08:07:28.36#ibcon#wrote, iclass 22, count 2 2006.246.08:07:28.36#ibcon#about to read 3, iclass 22, count 2 2006.246.08:07:28.39#ibcon#read 3, iclass 22, count 2 2006.246.08:07:28.39#ibcon#about to read 4, iclass 22, count 2 2006.246.08:07:28.39#ibcon#read 4, iclass 22, count 2 2006.246.08:07:28.39#ibcon#about to read 5, iclass 22, count 2 2006.246.08:07:28.39#ibcon#read 5, iclass 22, count 2 2006.246.08:07:28.39#ibcon#about to read 6, iclass 22, count 2 2006.246.08:07:28.39#ibcon#read 6, iclass 22, count 2 2006.246.08:07:28.39#ibcon#end of sib2, iclass 22, count 2 2006.246.08:07:28.39#ibcon#*after write, iclass 22, count 2 2006.246.08:07:28.39#ibcon#*before return 0, iclass 22, count 2 2006.246.08:07:28.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:28.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:28.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.08:07:28.39#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:28.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:28.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:28.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:28.51#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:07:28.51#ibcon#first serial, iclass 22, count 0 2006.246.08:07:28.51#ibcon#enter sib2, iclass 22, count 0 2006.246.08:07:28.51#ibcon#flushed, iclass 22, count 0 2006.246.08:07:28.51#ibcon#about to write, iclass 22, count 0 2006.246.08:07:28.51#ibcon#wrote, iclass 22, count 0 2006.246.08:07:28.51#ibcon#about to read 3, iclass 22, count 0 2006.246.08:07:28.53#ibcon#read 3, iclass 22, count 0 2006.246.08:07:28.53#ibcon#about to read 4, iclass 22, count 0 2006.246.08:07:28.53#ibcon#read 4, iclass 22, count 0 2006.246.08:07:28.53#ibcon#about to read 5, iclass 22, count 0 2006.246.08:07:28.53#ibcon#read 5, iclass 22, count 0 2006.246.08:07:28.53#ibcon#about to read 6, iclass 22, count 0 2006.246.08:07:28.53#ibcon#read 6, iclass 22, count 0 2006.246.08:07:28.53#ibcon#end of sib2, iclass 22, count 0 2006.246.08:07:28.53#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:07:28.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:07:28.53#ibcon#[25=USB\r\n] 2006.246.08:07:28.53#ibcon#*before write, iclass 22, count 0 2006.246.08:07:28.53#ibcon#enter sib2, iclass 22, count 0 2006.246.08:07:28.53#ibcon#flushed, iclass 22, count 0 2006.246.08:07:28.53#ibcon#about to write, iclass 22, count 0 2006.246.08:07:28.53#ibcon#wrote, iclass 22, count 0 2006.246.08:07:28.53#ibcon#about to read 3, iclass 22, count 0 2006.246.08:07:28.56#ibcon#read 3, iclass 22, count 0 2006.246.08:07:28.56#ibcon#about to read 4, iclass 22, count 0 2006.246.08:07:28.56#ibcon#read 4, iclass 22, count 0 2006.246.08:07:28.56#ibcon#about to read 5, iclass 22, count 0 2006.246.08:07:28.56#ibcon#read 5, iclass 22, count 0 2006.246.08:07:28.56#ibcon#about to read 6, iclass 22, count 0 2006.246.08:07:28.56#ibcon#read 6, iclass 22, count 0 2006.246.08:07:28.56#ibcon#end of sib2, iclass 22, count 0 2006.246.08:07:28.56#ibcon#*after write, iclass 22, count 0 2006.246.08:07:28.56#ibcon#*before return 0, iclass 22, count 0 2006.246.08:07:28.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:28.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:28.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:07:28.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:07:28.56$vc4f8/valo=3,672.99 2006.246.08:07:28.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.08:07:28.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.08:07:28.56#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:28.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:28.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:28.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:28.56#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:07:28.56#ibcon#first serial, iclass 24, count 0 2006.246.08:07:28.56#ibcon#enter sib2, iclass 24, count 0 2006.246.08:07:28.56#ibcon#flushed, iclass 24, count 0 2006.246.08:07:28.56#ibcon#about to write, iclass 24, count 0 2006.246.08:07:28.56#ibcon#wrote, iclass 24, count 0 2006.246.08:07:28.56#ibcon#about to read 3, iclass 24, count 0 2006.246.08:07:28.58#ibcon#read 3, iclass 24, count 0 2006.246.08:07:28.58#ibcon#about to read 4, iclass 24, count 0 2006.246.08:07:28.58#ibcon#read 4, iclass 24, count 0 2006.246.08:07:28.58#ibcon#about to read 5, iclass 24, count 0 2006.246.08:07:28.58#ibcon#read 5, iclass 24, count 0 2006.246.08:07:28.58#ibcon#about to read 6, iclass 24, count 0 2006.246.08:07:28.58#ibcon#read 6, iclass 24, count 0 2006.246.08:07:28.58#ibcon#end of sib2, iclass 24, count 0 2006.246.08:07:28.58#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:07:28.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:07:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:07:28.58#ibcon#*before write, iclass 24, count 0 2006.246.08:07:28.58#ibcon#enter sib2, iclass 24, count 0 2006.246.08:07:28.58#ibcon#flushed, iclass 24, count 0 2006.246.08:07:28.58#ibcon#about to write, iclass 24, count 0 2006.246.08:07:28.58#ibcon#wrote, iclass 24, count 0 2006.246.08:07:28.58#ibcon#about to read 3, iclass 24, count 0 2006.246.08:07:28.62#ibcon#read 3, iclass 24, count 0 2006.246.08:07:28.62#ibcon#about to read 4, iclass 24, count 0 2006.246.08:07:28.62#ibcon#read 4, iclass 24, count 0 2006.246.08:07:28.62#ibcon#about to read 5, iclass 24, count 0 2006.246.08:07:28.62#ibcon#read 5, iclass 24, count 0 2006.246.08:07:28.62#ibcon#about to read 6, iclass 24, count 0 2006.246.08:07:28.62#ibcon#read 6, iclass 24, count 0 2006.246.08:07:28.62#ibcon#end of sib2, iclass 24, count 0 2006.246.08:07:28.62#ibcon#*after write, iclass 24, count 0 2006.246.08:07:28.62#ibcon#*before return 0, iclass 24, count 0 2006.246.08:07:28.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:28.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:28.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:07:28.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:07:28.62$vc4f8/va=3,6 2006.246.08:07:28.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.08:07:28.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.08:07:28.62#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:28.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:28.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:28.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:28.68#ibcon#enter wrdev, iclass 26, count 2 2006.246.08:07:28.68#ibcon#first serial, iclass 26, count 2 2006.246.08:07:28.68#ibcon#enter sib2, iclass 26, count 2 2006.246.08:07:28.68#ibcon#flushed, iclass 26, count 2 2006.246.08:07:28.68#ibcon#about to write, iclass 26, count 2 2006.246.08:07:28.68#ibcon#wrote, iclass 26, count 2 2006.246.08:07:28.68#ibcon#about to read 3, iclass 26, count 2 2006.246.08:07:28.70#ibcon#read 3, iclass 26, count 2 2006.246.08:07:28.70#ibcon#about to read 4, iclass 26, count 2 2006.246.08:07:28.70#ibcon#read 4, iclass 26, count 2 2006.246.08:07:28.70#ibcon#about to read 5, iclass 26, count 2 2006.246.08:07:28.70#ibcon#read 5, iclass 26, count 2 2006.246.08:07:28.70#ibcon#about to read 6, iclass 26, count 2 2006.246.08:07:28.70#ibcon#read 6, iclass 26, count 2 2006.246.08:07:28.70#ibcon#end of sib2, iclass 26, count 2 2006.246.08:07:28.70#ibcon#*mode == 0, iclass 26, count 2 2006.246.08:07:28.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.08:07:28.70#ibcon#[25=AT03-06\r\n] 2006.246.08:07:28.70#ibcon#*before write, iclass 26, count 2 2006.246.08:07:28.70#ibcon#enter sib2, iclass 26, count 2 2006.246.08:07:28.70#ibcon#flushed, iclass 26, count 2 2006.246.08:07:28.70#ibcon#about to write, iclass 26, count 2 2006.246.08:07:28.70#ibcon#wrote, iclass 26, count 2 2006.246.08:07:28.70#ibcon#about to read 3, iclass 26, count 2 2006.246.08:07:28.74#ibcon#read 3, iclass 26, count 2 2006.246.08:07:28.74#ibcon#about to read 4, iclass 26, count 2 2006.246.08:07:28.74#ibcon#read 4, iclass 26, count 2 2006.246.08:07:28.74#ibcon#about to read 5, iclass 26, count 2 2006.246.08:07:28.74#ibcon#read 5, iclass 26, count 2 2006.246.08:07:28.74#ibcon#about to read 6, iclass 26, count 2 2006.246.08:07:28.74#ibcon#read 6, iclass 26, count 2 2006.246.08:07:28.74#ibcon#end of sib2, iclass 26, count 2 2006.246.08:07:28.74#ibcon#*after write, iclass 26, count 2 2006.246.08:07:28.74#ibcon#*before return 0, iclass 26, count 2 2006.246.08:07:28.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:28.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:28.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.08:07:28.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:28.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:28.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:28.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:28.86#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:07:28.86#ibcon#first serial, iclass 26, count 0 2006.246.08:07:28.86#ibcon#enter sib2, iclass 26, count 0 2006.246.08:07:28.86#ibcon#flushed, iclass 26, count 0 2006.246.08:07:28.86#ibcon#about to write, iclass 26, count 0 2006.246.08:07:28.86#ibcon#wrote, iclass 26, count 0 2006.246.08:07:28.86#ibcon#about to read 3, iclass 26, count 0 2006.246.08:07:28.88#ibcon#read 3, iclass 26, count 0 2006.246.08:07:28.88#ibcon#about to read 4, iclass 26, count 0 2006.246.08:07:28.88#ibcon#read 4, iclass 26, count 0 2006.246.08:07:28.88#ibcon#about to read 5, iclass 26, count 0 2006.246.08:07:28.88#ibcon#read 5, iclass 26, count 0 2006.246.08:07:28.88#ibcon#about to read 6, iclass 26, count 0 2006.246.08:07:28.88#ibcon#read 6, iclass 26, count 0 2006.246.08:07:28.88#ibcon#end of sib2, iclass 26, count 0 2006.246.08:07:28.88#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:07:28.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:07:28.88#ibcon#[25=USB\r\n] 2006.246.08:07:28.88#ibcon#*before write, iclass 26, count 0 2006.246.08:07:28.88#ibcon#enter sib2, iclass 26, count 0 2006.246.08:07:28.88#ibcon#flushed, iclass 26, count 0 2006.246.08:07:28.88#ibcon#about to write, iclass 26, count 0 2006.246.08:07:28.88#ibcon#wrote, iclass 26, count 0 2006.246.08:07:28.88#ibcon#about to read 3, iclass 26, count 0 2006.246.08:07:28.91#ibcon#read 3, iclass 26, count 0 2006.246.08:07:28.91#ibcon#about to read 4, iclass 26, count 0 2006.246.08:07:28.91#ibcon#read 4, iclass 26, count 0 2006.246.08:07:28.91#ibcon#about to read 5, iclass 26, count 0 2006.246.08:07:28.91#ibcon#read 5, iclass 26, count 0 2006.246.08:07:28.91#ibcon#about to read 6, iclass 26, count 0 2006.246.08:07:28.91#ibcon#read 6, iclass 26, count 0 2006.246.08:07:28.91#ibcon#end of sib2, iclass 26, count 0 2006.246.08:07:28.91#ibcon#*after write, iclass 26, count 0 2006.246.08:07:28.91#ibcon#*before return 0, iclass 26, count 0 2006.246.08:07:28.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:28.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:28.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:07:28.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:07:28.91$vc4f8/valo=4,832.99 2006.246.08:07:28.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.08:07:28.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.08:07:28.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:28.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:28.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:28.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:28.91#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:07:28.91#ibcon#first serial, iclass 28, count 0 2006.246.08:07:28.91#ibcon#enter sib2, iclass 28, count 0 2006.246.08:07:28.91#ibcon#flushed, iclass 28, count 0 2006.246.08:07:28.91#ibcon#about to write, iclass 28, count 0 2006.246.08:07:28.91#ibcon#wrote, iclass 28, count 0 2006.246.08:07:28.91#ibcon#about to read 3, iclass 28, count 0 2006.246.08:07:28.93#ibcon#read 3, iclass 28, count 0 2006.246.08:07:28.93#ibcon#about to read 4, iclass 28, count 0 2006.246.08:07:28.93#ibcon#read 4, iclass 28, count 0 2006.246.08:07:28.93#ibcon#about to read 5, iclass 28, count 0 2006.246.08:07:28.93#ibcon#read 5, iclass 28, count 0 2006.246.08:07:28.93#ibcon#about to read 6, iclass 28, count 0 2006.246.08:07:28.93#ibcon#read 6, iclass 28, count 0 2006.246.08:07:28.93#ibcon#end of sib2, iclass 28, count 0 2006.246.08:07:28.93#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:07:28.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:07:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:07:28.93#ibcon#*before write, iclass 28, count 0 2006.246.08:07:28.93#ibcon#enter sib2, iclass 28, count 0 2006.246.08:07:28.93#ibcon#flushed, iclass 28, count 0 2006.246.08:07:28.93#ibcon#about to write, iclass 28, count 0 2006.246.08:07:28.93#ibcon#wrote, iclass 28, count 0 2006.246.08:07:28.93#ibcon#about to read 3, iclass 28, count 0 2006.246.08:07:28.97#ibcon#read 3, iclass 28, count 0 2006.246.08:07:28.97#ibcon#about to read 4, iclass 28, count 0 2006.246.08:07:28.97#ibcon#read 4, iclass 28, count 0 2006.246.08:07:28.97#ibcon#about to read 5, iclass 28, count 0 2006.246.08:07:28.97#ibcon#read 5, iclass 28, count 0 2006.246.08:07:28.97#ibcon#about to read 6, iclass 28, count 0 2006.246.08:07:28.97#ibcon#read 6, iclass 28, count 0 2006.246.08:07:28.97#ibcon#end of sib2, iclass 28, count 0 2006.246.08:07:28.97#ibcon#*after write, iclass 28, count 0 2006.246.08:07:28.97#ibcon#*before return 0, iclass 28, count 0 2006.246.08:07:28.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:28.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:28.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:07:28.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:07:28.97$vc4f8/va=4,7 2006.246.08:07:28.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.08:07:28.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.08:07:28.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:28.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:29.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:29.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:29.03#ibcon#enter wrdev, iclass 30, count 2 2006.246.08:07:29.03#ibcon#first serial, iclass 30, count 2 2006.246.08:07:29.03#ibcon#enter sib2, iclass 30, count 2 2006.246.08:07:29.03#ibcon#flushed, iclass 30, count 2 2006.246.08:07:29.03#ibcon#about to write, iclass 30, count 2 2006.246.08:07:29.03#ibcon#wrote, iclass 30, count 2 2006.246.08:07:29.03#ibcon#about to read 3, iclass 30, count 2 2006.246.08:07:29.05#ibcon#read 3, iclass 30, count 2 2006.246.08:07:29.05#ibcon#about to read 4, iclass 30, count 2 2006.246.08:07:29.05#ibcon#read 4, iclass 30, count 2 2006.246.08:07:29.05#ibcon#about to read 5, iclass 30, count 2 2006.246.08:07:29.05#ibcon#read 5, iclass 30, count 2 2006.246.08:07:29.05#ibcon#about to read 6, iclass 30, count 2 2006.246.08:07:29.05#ibcon#read 6, iclass 30, count 2 2006.246.08:07:29.05#ibcon#end of sib2, iclass 30, count 2 2006.246.08:07:29.05#ibcon#*mode == 0, iclass 30, count 2 2006.246.08:07:29.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.08:07:29.05#ibcon#[25=AT04-07\r\n] 2006.246.08:07:29.05#ibcon#*before write, iclass 30, count 2 2006.246.08:07:29.05#ibcon#enter sib2, iclass 30, count 2 2006.246.08:07:29.05#ibcon#flushed, iclass 30, count 2 2006.246.08:07:29.05#ibcon#about to write, iclass 30, count 2 2006.246.08:07:29.05#ibcon#wrote, iclass 30, count 2 2006.246.08:07:29.05#ibcon#about to read 3, iclass 30, count 2 2006.246.08:07:29.08#ibcon#read 3, iclass 30, count 2 2006.246.08:07:29.08#ibcon#about to read 4, iclass 30, count 2 2006.246.08:07:29.08#ibcon#read 4, iclass 30, count 2 2006.246.08:07:29.08#ibcon#about to read 5, iclass 30, count 2 2006.246.08:07:29.08#ibcon#read 5, iclass 30, count 2 2006.246.08:07:29.08#ibcon#about to read 6, iclass 30, count 2 2006.246.08:07:29.08#ibcon#read 6, iclass 30, count 2 2006.246.08:07:29.08#ibcon#end of sib2, iclass 30, count 2 2006.246.08:07:29.08#ibcon#*after write, iclass 30, count 2 2006.246.08:07:29.08#ibcon#*before return 0, iclass 30, count 2 2006.246.08:07:29.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:29.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:29.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.08:07:29.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:29.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:29.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:29.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:29.20#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:07:29.20#ibcon#first serial, iclass 30, count 0 2006.246.08:07:29.20#ibcon#enter sib2, iclass 30, count 0 2006.246.08:07:29.20#ibcon#flushed, iclass 30, count 0 2006.246.08:07:29.20#ibcon#about to write, iclass 30, count 0 2006.246.08:07:29.20#ibcon#wrote, iclass 30, count 0 2006.246.08:07:29.20#ibcon#about to read 3, iclass 30, count 0 2006.246.08:07:29.22#ibcon#read 3, iclass 30, count 0 2006.246.08:07:29.22#ibcon#about to read 4, iclass 30, count 0 2006.246.08:07:29.22#ibcon#read 4, iclass 30, count 0 2006.246.08:07:29.22#ibcon#about to read 5, iclass 30, count 0 2006.246.08:07:29.22#ibcon#read 5, iclass 30, count 0 2006.246.08:07:29.22#ibcon#about to read 6, iclass 30, count 0 2006.246.08:07:29.22#ibcon#read 6, iclass 30, count 0 2006.246.08:07:29.22#ibcon#end of sib2, iclass 30, count 0 2006.246.08:07:29.22#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:07:29.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:07:29.22#ibcon#[25=USB\r\n] 2006.246.08:07:29.22#ibcon#*before write, iclass 30, count 0 2006.246.08:07:29.22#ibcon#enter sib2, iclass 30, count 0 2006.246.08:07:29.22#ibcon#flushed, iclass 30, count 0 2006.246.08:07:29.22#ibcon#about to write, iclass 30, count 0 2006.246.08:07:29.22#ibcon#wrote, iclass 30, count 0 2006.246.08:07:29.22#ibcon#about to read 3, iclass 30, count 0 2006.246.08:07:29.25#ibcon#read 3, iclass 30, count 0 2006.246.08:07:29.25#ibcon#about to read 4, iclass 30, count 0 2006.246.08:07:29.25#ibcon#read 4, iclass 30, count 0 2006.246.08:07:29.25#ibcon#about to read 5, iclass 30, count 0 2006.246.08:07:29.25#ibcon#read 5, iclass 30, count 0 2006.246.08:07:29.25#ibcon#about to read 6, iclass 30, count 0 2006.246.08:07:29.25#ibcon#read 6, iclass 30, count 0 2006.246.08:07:29.25#ibcon#end of sib2, iclass 30, count 0 2006.246.08:07:29.25#ibcon#*after write, iclass 30, count 0 2006.246.08:07:29.25#ibcon#*before return 0, iclass 30, count 0 2006.246.08:07:29.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:29.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:29.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:07:29.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:07:29.25$vc4f8/valo=5,652.99 2006.246.08:07:29.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:07:29.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:07:29.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:29.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:29.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:29.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:29.25#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:07:29.25#ibcon#first serial, iclass 32, count 0 2006.246.08:07:29.25#ibcon#enter sib2, iclass 32, count 0 2006.246.08:07:29.25#ibcon#flushed, iclass 32, count 0 2006.246.08:07:29.25#ibcon#about to write, iclass 32, count 0 2006.246.08:07:29.25#ibcon#wrote, iclass 32, count 0 2006.246.08:07:29.25#ibcon#about to read 3, iclass 32, count 0 2006.246.08:07:29.27#ibcon#read 3, iclass 32, count 0 2006.246.08:07:29.27#ibcon#about to read 4, iclass 32, count 0 2006.246.08:07:29.27#ibcon#read 4, iclass 32, count 0 2006.246.08:07:29.27#ibcon#about to read 5, iclass 32, count 0 2006.246.08:07:29.27#ibcon#read 5, iclass 32, count 0 2006.246.08:07:29.27#ibcon#about to read 6, iclass 32, count 0 2006.246.08:07:29.27#ibcon#read 6, iclass 32, count 0 2006.246.08:07:29.27#ibcon#end of sib2, iclass 32, count 0 2006.246.08:07:29.27#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:07:29.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:07:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:07:29.27#ibcon#*before write, iclass 32, count 0 2006.246.08:07:29.27#ibcon#enter sib2, iclass 32, count 0 2006.246.08:07:29.27#ibcon#flushed, iclass 32, count 0 2006.246.08:07:29.27#ibcon#about to write, iclass 32, count 0 2006.246.08:07:29.27#ibcon#wrote, iclass 32, count 0 2006.246.08:07:29.27#ibcon#about to read 3, iclass 32, count 0 2006.246.08:07:29.31#ibcon#read 3, iclass 32, count 0 2006.246.08:07:29.31#ibcon#about to read 4, iclass 32, count 0 2006.246.08:07:29.31#ibcon#read 4, iclass 32, count 0 2006.246.08:07:29.31#ibcon#about to read 5, iclass 32, count 0 2006.246.08:07:29.31#ibcon#read 5, iclass 32, count 0 2006.246.08:07:29.31#ibcon#about to read 6, iclass 32, count 0 2006.246.08:07:29.31#ibcon#read 6, iclass 32, count 0 2006.246.08:07:29.31#ibcon#end of sib2, iclass 32, count 0 2006.246.08:07:29.31#ibcon#*after write, iclass 32, count 0 2006.246.08:07:29.31#ibcon#*before return 0, iclass 32, count 0 2006.246.08:07:29.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:29.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:29.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:07:29.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:07:29.31$vc4f8/va=5,7 2006.246.08:07:29.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.08:07:29.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.08:07:29.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:29.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:29.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:29.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:29.37#ibcon#enter wrdev, iclass 34, count 2 2006.246.08:07:29.37#ibcon#first serial, iclass 34, count 2 2006.246.08:07:29.37#ibcon#enter sib2, iclass 34, count 2 2006.246.08:07:29.37#ibcon#flushed, iclass 34, count 2 2006.246.08:07:29.37#ibcon#about to write, iclass 34, count 2 2006.246.08:07:29.37#ibcon#wrote, iclass 34, count 2 2006.246.08:07:29.37#ibcon#about to read 3, iclass 34, count 2 2006.246.08:07:29.39#ibcon#read 3, iclass 34, count 2 2006.246.08:07:29.39#ibcon#about to read 4, iclass 34, count 2 2006.246.08:07:29.39#ibcon#read 4, iclass 34, count 2 2006.246.08:07:29.39#ibcon#about to read 5, iclass 34, count 2 2006.246.08:07:29.39#ibcon#read 5, iclass 34, count 2 2006.246.08:07:29.39#ibcon#about to read 6, iclass 34, count 2 2006.246.08:07:29.39#ibcon#read 6, iclass 34, count 2 2006.246.08:07:29.39#ibcon#end of sib2, iclass 34, count 2 2006.246.08:07:29.39#ibcon#*mode == 0, iclass 34, count 2 2006.246.08:07:29.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.08:07:29.39#ibcon#[25=AT05-07\r\n] 2006.246.08:07:29.39#ibcon#*before write, iclass 34, count 2 2006.246.08:07:29.39#ibcon#enter sib2, iclass 34, count 2 2006.246.08:07:29.39#ibcon#flushed, iclass 34, count 2 2006.246.08:07:29.39#ibcon#about to write, iclass 34, count 2 2006.246.08:07:29.39#ibcon#wrote, iclass 34, count 2 2006.246.08:07:29.39#ibcon#about to read 3, iclass 34, count 2 2006.246.08:07:29.42#ibcon#read 3, iclass 34, count 2 2006.246.08:07:29.42#ibcon#about to read 4, iclass 34, count 2 2006.246.08:07:29.42#ibcon#read 4, iclass 34, count 2 2006.246.08:07:29.42#ibcon#about to read 5, iclass 34, count 2 2006.246.08:07:29.42#ibcon#read 5, iclass 34, count 2 2006.246.08:07:29.42#ibcon#about to read 6, iclass 34, count 2 2006.246.08:07:29.42#ibcon#read 6, iclass 34, count 2 2006.246.08:07:29.42#ibcon#end of sib2, iclass 34, count 2 2006.246.08:07:29.42#ibcon#*after write, iclass 34, count 2 2006.246.08:07:29.42#ibcon#*before return 0, iclass 34, count 2 2006.246.08:07:29.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:29.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:29.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.08:07:29.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:29.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:29.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:29.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:29.54#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:07:29.54#ibcon#first serial, iclass 34, count 0 2006.246.08:07:29.54#ibcon#enter sib2, iclass 34, count 0 2006.246.08:07:29.54#ibcon#flushed, iclass 34, count 0 2006.246.08:07:29.54#ibcon#about to write, iclass 34, count 0 2006.246.08:07:29.54#ibcon#wrote, iclass 34, count 0 2006.246.08:07:29.54#ibcon#about to read 3, iclass 34, count 0 2006.246.08:07:29.56#ibcon#read 3, iclass 34, count 0 2006.246.08:07:29.56#ibcon#about to read 4, iclass 34, count 0 2006.246.08:07:29.56#ibcon#read 4, iclass 34, count 0 2006.246.08:07:29.56#ibcon#about to read 5, iclass 34, count 0 2006.246.08:07:29.56#ibcon#read 5, iclass 34, count 0 2006.246.08:07:29.56#ibcon#about to read 6, iclass 34, count 0 2006.246.08:07:29.56#ibcon#read 6, iclass 34, count 0 2006.246.08:07:29.56#ibcon#end of sib2, iclass 34, count 0 2006.246.08:07:29.56#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:07:29.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:07:29.56#ibcon#[25=USB\r\n] 2006.246.08:07:29.56#ibcon#*before write, iclass 34, count 0 2006.246.08:07:29.56#ibcon#enter sib2, iclass 34, count 0 2006.246.08:07:29.56#ibcon#flushed, iclass 34, count 0 2006.246.08:07:29.56#ibcon#about to write, iclass 34, count 0 2006.246.08:07:29.56#ibcon#wrote, iclass 34, count 0 2006.246.08:07:29.56#ibcon#about to read 3, iclass 34, count 0 2006.246.08:07:29.59#ibcon#read 3, iclass 34, count 0 2006.246.08:07:29.59#ibcon#about to read 4, iclass 34, count 0 2006.246.08:07:29.59#ibcon#read 4, iclass 34, count 0 2006.246.08:07:29.59#ibcon#about to read 5, iclass 34, count 0 2006.246.08:07:29.59#ibcon#read 5, iclass 34, count 0 2006.246.08:07:29.59#ibcon#about to read 6, iclass 34, count 0 2006.246.08:07:29.59#ibcon#read 6, iclass 34, count 0 2006.246.08:07:29.59#ibcon#end of sib2, iclass 34, count 0 2006.246.08:07:29.59#ibcon#*after write, iclass 34, count 0 2006.246.08:07:29.59#ibcon#*before return 0, iclass 34, count 0 2006.246.08:07:29.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:29.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:29.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:07:29.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:07:29.59$vc4f8/valo=6,772.99 2006.246.08:07:29.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.08:07:29.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.08:07:29.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:29.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:29.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:29.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:29.59#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:07:29.59#ibcon#first serial, iclass 36, count 0 2006.246.08:07:29.59#ibcon#enter sib2, iclass 36, count 0 2006.246.08:07:29.59#ibcon#flushed, iclass 36, count 0 2006.246.08:07:29.59#ibcon#about to write, iclass 36, count 0 2006.246.08:07:29.59#ibcon#wrote, iclass 36, count 0 2006.246.08:07:29.59#ibcon#about to read 3, iclass 36, count 0 2006.246.08:07:29.61#ibcon#read 3, iclass 36, count 0 2006.246.08:07:29.61#ibcon#about to read 4, iclass 36, count 0 2006.246.08:07:29.61#ibcon#read 4, iclass 36, count 0 2006.246.08:07:29.61#ibcon#about to read 5, iclass 36, count 0 2006.246.08:07:29.61#ibcon#read 5, iclass 36, count 0 2006.246.08:07:29.61#ibcon#about to read 6, iclass 36, count 0 2006.246.08:07:29.61#ibcon#read 6, iclass 36, count 0 2006.246.08:07:29.61#ibcon#end of sib2, iclass 36, count 0 2006.246.08:07:29.61#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:07:29.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:07:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:07:29.61#ibcon#*before write, iclass 36, count 0 2006.246.08:07:29.61#ibcon#enter sib2, iclass 36, count 0 2006.246.08:07:29.61#ibcon#flushed, iclass 36, count 0 2006.246.08:07:29.61#ibcon#about to write, iclass 36, count 0 2006.246.08:07:29.61#ibcon#wrote, iclass 36, count 0 2006.246.08:07:29.61#ibcon#about to read 3, iclass 36, count 0 2006.246.08:07:29.66#ibcon#read 3, iclass 36, count 0 2006.246.08:07:29.66#ibcon#about to read 4, iclass 36, count 0 2006.246.08:07:29.66#ibcon#read 4, iclass 36, count 0 2006.246.08:07:29.66#ibcon#about to read 5, iclass 36, count 0 2006.246.08:07:29.66#ibcon#read 5, iclass 36, count 0 2006.246.08:07:29.66#ibcon#about to read 6, iclass 36, count 0 2006.246.08:07:29.66#ibcon#read 6, iclass 36, count 0 2006.246.08:07:29.66#ibcon#end of sib2, iclass 36, count 0 2006.246.08:07:29.66#ibcon#*after write, iclass 36, count 0 2006.246.08:07:29.66#ibcon#*before return 0, iclass 36, count 0 2006.246.08:07:29.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:29.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:29.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:07:29.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:07:29.66$vc4f8/va=6,7 2006.246.08:07:29.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.08:07:29.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.08:07:29.66#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:29.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:07:29.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:07:29.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:07:29.71#ibcon#enter wrdev, iclass 38, count 2 2006.246.08:07:29.71#ibcon#first serial, iclass 38, count 2 2006.246.08:07:29.71#ibcon#enter sib2, iclass 38, count 2 2006.246.08:07:29.71#ibcon#flushed, iclass 38, count 2 2006.246.08:07:29.71#ibcon#about to write, iclass 38, count 2 2006.246.08:07:29.71#ibcon#wrote, iclass 38, count 2 2006.246.08:07:29.71#ibcon#about to read 3, iclass 38, count 2 2006.246.08:07:29.73#ibcon#read 3, iclass 38, count 2 2006.246.08:07:29.73#ibcon#about to read 4, iclass 38, count 2 2006.246.08:07:29.73#ibcon#read 4, iclass 38, count 2 2006.246.08:07:29.73#ibcon#about to read 5, iclass 38, count 2 2006.246.08:07:29.73#ibcon#read 5, iclass 38, count 2 2006.246.08:07:29.73#ibcon#about to read 6, iclass 38, count 2 2006.246.08:07:29.73#ibcon#read 6, iclass 38, count 2 2006.246.08:07:29.73#ibcon#end of sib2, iclass 38, count 2 2006.246.08:07:29.73#ibcon#*mode == 0, iclass 38, count 2 2006.246.08:07:29.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.08:07:29.73#ibcon#[25=AT06-07\r\n] 2006.246.08:07:29.73#ibcon#*before write, iclass 38, count 2 2006.246.08:07:29.73#ibcon#enter sib2, iclass 38, count 2 2006.246.08:07:29.73#ibcon#flushed, iclass 38, count 2 2006.246.08:07:29.73#ibcon#about to write, iclass 38, count 2 2006.246.08:07:29.73#ibcon#wrote, iclass 38, count 2 2006.246.08:07:29.73#ibcon#about to read 3, iclass 38, count 2 2006.246.08:07:29.76#ibcon#read 3, iclass 38, count 2 2006.246.08:07:29.76#ibcon#about to read 4, iclass 38, count 2 2006.246.08:07:29.76#ibcon#read 4, iclass 38, count 2 2006.246.08:07:29.76#ibcon#about to read 5, iclass 38, count 2 2006.246.08:07:29.76#ibcon#read 5, iclass 38, count 2 2006.246.08:07:29.76#ibcon#about to read 6, iclass 38, count 2 2006.246.08:07:29.76#ibcon#read 6, iclass 38, count 2 2006.246.08:07:29.76#ibcon#end of sib2, iclass 38, count 2 2006.246.08:07:29.76#ibcon#*after write, iclass 38, count 2 2006.246.08:07:29.76#ibcon#*before return 0, iclass 38, count 2 2006.246.08:07:29.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:07:29.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:07:29.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.08:07:29.76#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:29.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:07:29.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:07:29.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:07:29.88#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:07:29.88#ibcon#first serial, iclass 38, count 0 2006.246.08:07:29.88#ibcon#enter sib2, iclass 38, count 0 2006.246.08:07:29.88#ibcon#flushed, iclass 38, count 0 2006.246.08:07:29.88#ibcon#about to write, iclass 38, count 0 2006.246.08:07:29.88#ibcon#wrote, iclass 38, count 0 2006.246.08:07:29.88#ibcon#about to read 3, iclass 38, count 0 2006.246.08:07:29.90#ibcon#read 3, iclass 38, count 0 2006.246.08:07:29.90#ibcon#about to read 4, iclass 38, count 0 2006.246.08:07:29.90#ibcon#read 4, iclass 38, count 0 2006.246.08:07:29.90#ibcon#about to read 5, iclass 38, count 0 2006.246.08:07:29.90#ibcon#read 5, iclass 38, count 0 2006.246.08:07:29.90#ibcon#about to read 6, iclass 38, count 0 2006.246.08:07:29.90#ibcon#read 6, iclass 38, count 0 2006.246.08:07:29.90#ibcon#end of sib2, iclass 38, count 0 2006.246.08:07:29.90#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:07:29.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:07:29.90#ibcon#[25=USB\r\n] 2006.246.08:07:29.90#ibcon#*before write, iclass 38, count 0 2006.246.08:07:29.90#ibcon#enter sib2, iclass 38, count 0 2006.246.08:07:29.90#ibcon#flushed, iclass 38, count 0 2006.246.08:07:29.90#ibcon#about to write, iclass 38, count 0 2006.246.08:07:29.90#ibcon#wrote, iclass 38, count 0 2006.246.08:07:29.90#ibcon#about to read 3, iclass 38, count 0 2006.246.08:07:29.93#ibcon#read 3, iclass 38, count 0 2006.246.08:07:29.93#ibcon#about to read 4, iclass 38, count 0 2006.246.08:07:29.93#ibcon#read 4, iclass 38, count 0 2006.246.08:07:29.93#ibcon#about to read 5, iclass 38, count 0 2006.246.08:07:29.93#ibcon#read 5, iclass 38, count 0 2006.246.08:07:29.93#ibcon#about to read 6, iclass 38, count 0 2006.246.08:07:29.93#ibcon#read 6, iclass 38, count 0 2006.246.08:07:29.93#ibcon#end of sib2, iclass 38, count 0 2006.246.08:07:29.93#ibcon#*after write, iclass 38, count 0 2006.246.08:07:29.93#ibcon#*before return 0, iclass 38, count 0 2006.246.08:07:29.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:07:29.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:07:29.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:07:29.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:07:29.93$vc4f8/valo=7,832.99 2006.246.08:07:29.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.08:07:29.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.08:07:29.93#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:29.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:07:29.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:07:29.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:07:29.93#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:07:29.93#ibcon#first serial, iclass 40, count 0 2006.246.08:07:29.93#ibcon#enter sib2, iclass 40, count 0 2006.246.08:07:29.93#ibcon#flushed, iclass 40, count 0 2006.246.08:07:29.93#ibcon#about to write, iclass 40, count 0 2006.246.08:07:29.93#ibcon#wrote, iclass 40, count 0 2006.246.08:07:29.93#ibcon#about to read 3, iclass 40, count 0 2006.246.08:07:29.95#ibcon#read 3, iclass 40, count 0 2006.246.08:07:29.95#ibcon#about to read 4, iclass 40, count 0 2006.246.08:07:29.95#ibcon#read 4, iclass 40, count 0 2006.246.08:07:29.95#ibcon#about to read 5, iclass 40, count 0 2006.246.08:07:29.95#ibcon#read 5, iclass 40, count 0 2006.246.08:07:29.95#ibcon#about to read 6, iclass 40, count 0 2006.246.08:07:29.95#ibcon#read 6, iclass 40, count 0 2006.246.08:07:29.95#ibcon#end of sib2, iclass 40, count 0 2006.246.08:07:29.95#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:07:29.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:07:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:07:29.95#ibcon#*before write, iclass 40, count 0 2006.246.08:07:29.95#ibcon#enter sib2, iclass 40, count 0 2006.246.08:07:29.95#ibcon#flushed, iclass 40, count 0 2006.246.08:07:29.95#ibcon#about to write, iclass 40, count 0 2006.246.08:07:29.95#ibcon#wrote, iclass 40, count 0 2006.246.08:07:29.95#ibcon#about to read 3, iclass 40, count 0 2006.246.08:07:29.99#ibcon#read 3, iclass 40, count 0 2006.246.08:07:29.99#ibcon#about to read 4, iclass 40, count 0 2006.246.08:07:29.99#ibcon#read 4, iclass 40, count 0 2006.246.08:07:29.99#ibcon#about to read 5, iclass 40, count 0 2006.246.08:07:29.99#ibcon#read 5, iclass 40, count 0 2006.246.08:07:29.99#ibcon#about to read 6, iclass 40, count 0 2006.246.08:07:29.99#ibcon#read 6, iclass 40, count 0 2006.246.08:07:29.99#ibcon#end of sib2, iclass 40, count 0 2006.246.08:07:29.99#ibcon#*after write, iclass 40, count 0 2006.246.08:07:29.99#ibcon#*before return 0, iclass 40, count 0 2006.246.08:07:29.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:07:29.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:07:29.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:07:29.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:07:29.99$vc4f8/va=7,7 2006.246.08:07:29.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.08:07:29.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.08:07:29.99#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:29.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:07:30.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:07:30.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:07:30.05#ibcon#enter wrdev, iclass 4, count 2 2006.246.08:07:30.05#ibcon#first serial, iclass 4, count 2 2006.246.08:07:30.05#ibcon#enter sib2, iclass 4, count 2 2006.246.08:07:30.05#ibcon#flushed, iclass 4, count 2 2006.246.08:07:30.05#ibcon#about to write, iclass 4, count 2 2006.246.08:07:30.05#ibcon#wrote, iclass 4, count 2 2006.246.08:07:30.05#ibcon#about to read 3, iclass 4, count 2 2006.246.08:07:30.07#ibcon#read 3, iclass 4, count 2 2006.246.08:07:30.07#ibcon#about to read 4, iclass 4, count 2 2006.246.08:07:30.07#ibcon#read 4, iclass 4, count 2 2006.246.08:07:30.07#ibcon#about to read 5, iclass 4, count 2 2006.246.08:07:30.07#ibcon#read 5, iclass 4, count 2 2006.246.08:07:30.07#ibcon#about to read 6, iclass 4, count 2 2006.246.08:07:30.07#ibcon#read 6, iclass 4, count 2 2006.246.08:07:30.07#ibcon#end of sib2, iclass 4, count 2 2006.246.08:07:30.07#ibcon#*mode == 0, iclass 4, count 2 2006.246.08:07:30.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.08:07:30.07#ibcon#[25=AT07-07\r\n] 2006.246.08:07:30.07#ibcon#*before write, iclass 4, count 2 2006.246.08:07:30.07#ibcon#enter sib2, iclass 4, count 2 2006.246.08:07:30.07#ibcon#flushed, iclass 4, count 2 2006.246.08:07:30.07#ibcon#about to write, iclass 4, count 2 2006.246.08:07:30.07#ibcon#wrote, iclass 4, count 2 2006.246.08:07:30.07#ibcon#about to read 3, iclass 4, count 2 2006.246.08:07:30.10#ibcon#read 3, iclass 4, count 2 2006.246.08:07:30.10#ibcon#about to read 4, iclass 4, count 2 2006.246.08:07:30.10#ibcon#read 4, iclass 4, count 2 2006.246.08:07:30.10#ibcon#about to read 5, iclass 4, count 2 2006.246.08:07:30.10#ibcon#read 5, iclass 4, count 2 2006.246.08:07:30.10#ibcon#about to read 6, iclass 4, count 2 2006.246.08:07:30.10#ibcon#read 6, iclass 4, count 2 2006.246.08:07:30.10#ibcon#end of sib2, iclass 4, count 2 2006.246.08:07:30.10#ibcon#*after write, iclass 4, count 2 2006.246.08:07:30.10#ibcon#*before return 0, iclass 4, count 2 2006.246.08:07:30.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:07:30.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:07:30.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.08:07:30.10#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:30.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:07:30.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:07:30.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:07:30.22#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:07:30.22#ibcon#first serial, iclass 4, count 0 2006.246.08:07:30.22#ibcon#enter sib2, iclass 4, count 0 2006.246.08:07:30.22#ibcon#flushed, iclass 4, count 0 2006.246.08:07:30.22#ibcon#about to write, iclass 4, count 0 2006.246.08:07:30.22#ibcon#wrote, iclass 4, count 0 2006.246.08:07:30.22#ibcon#about to read 3, iclass 4, count 0 2006.246.08:07:30.24#ibcon#read 3, iclass 4, count 0 2006.246.08:07:30.24#ibcon#about to read 4, iclass 4, count 0 2006.246.08:07:30.24#ibcon#read 4, iclass 4, count 0 2006.246.08:07:30.24#ibcon#about to read 5, iclass 4, count 0 2006.246.08:07:30.24#ibcon#read 5, iclass 4, count 0 2006.246.08:07:30.24#ibcon#about to read 6, iclass 4, count 0 2006.246.08:07:30.24#ibcon#read 6, iclass 4, count 0 2006.246.08:07:30.24#ibcon#end of sib2, iclass 4, count 0 2006.246.08:07:30.24#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:07:30.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:07:30.24#ibcon#[25=USB\r\n] 2006.246.08:07:30.24#ibcon#*before write, iclass 4, count 0 2006.246.08:07:30.24#ibcon#enter sib2, iclass 4, count 0 2006.246.08:07:30.24#ibcon#flushed, iclass 4, count 0 2006.246.08:07:30.24#ibcon#about to write, iclass 4, count 0 2006.246.08:07:30.24#ibcon#wrote, iclass 4, count 0 2006.246.08:07:30.24#ibcon#about to read 3, iclass 4, count 0 2006.246.08:07:30.27#ibcon#read 3, iclass 4, count 0 2006.246.08:07:30.27#ibcon#about to read 4, iclass 4, count 0 2006.246.08:07:30.27#ibcon#read 4, iclass 4, count 0 2006.246.08:07:30.27#ibcon#about to read 5, iclass 4, count 0 2006.246.08:07:30.27#ibcon#read 5, iclass 4, count 0 2006.246.08:07:30.27#ibcon#about to read 6, iclass 4, count 0 2006.246.08:07:30.27#ibcon#read 6, iclass 4, count 0 2006.246.08:07:30.27#ibcon#end of sib2, iclass 4, count 0 2006.246.08:07:30.27#ibcon#*after write, iclass 4, count 0 2006.246.08:07:30.27#ibcon#*before return 0, iclass 4, count 0 2006.246.08:07:30.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:07:30.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:07:30.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:07:30.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:07:30.27$vc4f8/valo=8,852.99 2006.246.08:07:30.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.08:07:30.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.08:07:30.27#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:30.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:07:30.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:07:30.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:07:30.27#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:07:30.27#ibcon#first serial, iclass 6, count 0 2006.246.08:07:30.27#ibcon#enter sib2, iclass 6, count 0 2006.246.08:07:30.27#ibcon#flushed, iclass 6, count 0 2006.246.08:07:30.27#ibcon#about to write, iclass 6, count 0 2006.246.08:07:30.27#ibcon#wrote, iclass 6, count 0 2006.246.08:07:30.27#ibcon#about to read 3, iclass 6, count 0 2006.246.08:07:30.29#ibcon#read 3, iclass 6, count 0 2006.246.08:07:30.29#ibcon#about to read 4, iclass 6, count 0 2006.246.08:07:30.29#ibcon#read 4, iclass 6, count 0 2006.246.08:07:30.29#ibcon#about to read 5, iclass 6, count 0 2006.246.08:07:30.29#ibcon#read 5, iclass 6, count 0 2006.246.08:07:30.29#ibcon#about to read 6, iclass 6, count 0 2006.246.08:07:30.29#ibcon#read 6, iclass 6, count 0 2006.246.08:07:30.29#ibcon#end of sib2, iclass 6, count 0 2006.246.08:07:30.29#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:07:30.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:07:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:07:30.29#ibcon#*before write, iclass 6, count 0 2006.246.08:07:30.29#ibcon#enter sib2, iclass 6, count 0 2006.246.08:07:30.29#ibcon#flushed, iclass 6, count 0 2006.246.08:07:30.29#ibcon#about to write, iclass 6, count 0 2006.246.08:07:30.29#ibcon#wrote, iclass 6, count 0 2006.246.08:07:30.29#ibcon#about to read 3, iclass 6, count 0 2006.246.08:07:30.33#ibcon#read 3, iclass 6, count 0 2006.246.08:07:30.33#ibcon#about to read 4, iclass 6, count 0 2006.246.08:07:30.33#ibcon#read 4, iclass 6, count 0 2006.246.08:07:30.33#ibcon#about to read 5, iclass 6, count 0 2006.246.08:07:30.33#ibcon#read 5, iclass 6, count 0 2006.246.08:07:30.33#ibcon#about to read 6, iclass 6, count 0 2006.246.08:07:30.33#ibcon#read 6, iclass 6, count 0 2006.246.08:07:30.33#ibcon#end of sib2, iclass 6, count 0 2006.246.08:07:30.33#ibcon#*after write, iclass 6, count 0 2006.246.08:07:30.33#ibcon#*before return 0, iclass 6, count 0 2006.246.08:07:30.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:07:30.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:07:30.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:07:30.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:07:30.33$vc4f8/va=8,8 2006.246.08:07:30.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.08:07:30.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.08:07:30.33#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:30.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:07:30.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:07:30.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:07:30.39#ibcon#enter wrdev, iclass 10, count 2 2006.246.08:07:30.39#ibcon#first serial, iclass 10, count 2 2006.246.08:07:30.39#ibcon#enter sib2, iclass 10, count 2 2006.246.08:07:30.39#ibcon#flushed, iclass 10, count 2 2006.246.08:07:30.39#ibcon#about to write, iclass 10, count 2 2006.246.08:07:30.39#ibcon#wrote, iclass 10, count 2 2006.246.08:07:30.39#ibcon#about to read 3, iclass 10, count 2 2006.246.08:07:30.41#ibcon#read 3, iclass 10, count 2 2006.246.08:07:30.41#ibcon#about to read 4, iclass 10, count 2 2006.246.08:07:30.41#ibcon#read 4, iclass 10, count 2 2006.246.08:07:30.41#ibcon#about to read 5, iclass 10, count 2 2006.246.08:07:30.41#ibcon#read 5, iclass 10, count 2 2006.246.08:07:30.41#ibcon#about to read 6, iclass 10, count 2 2006.246.08:07:30.41#ibcon#read 6, iclass 10, count 2 2006.246.08:07:30.41#ibcon#end of sib2, iclass 10, count 2 2006.246.08:07:30.41#ibcon#*mode == 0, iclass 10, count 2 2006.246.08:07:30.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.08:07:30.41#ibcon#[25=AT08-08\r\n] 2006.246.08:07:30.41#ibcon#*before write, iclass 10, count 2 2006.246.08:07:30.41#ibcon#enter sib2, iclass 10, count 2 2006.246.08:07:30.41#ibcon#flushed, iclass 10, count 2 2006.246.08:07:30.41#ibcon#about to write, iclass 10, count 2 2006.246.08:07:30.41#ibcon#wrote, iclass 10, count 2 2006.246.08:07:30.41#ibcon#about to read 3, iclass 10, count 2 2006.246.08:07:30.44#ibcon#read 3, iclass 10, count 2 2006.246.08:07:30.44#ibcon#about to read 4, iclass 10, count 2 2006.246.08:07:30.44#ibcon#read 4, iclass 10, count 2 2006.246.08:07:30.44#ibcon#about to read 5, iclass 10, count 2 2006.246.08:07:30.44#ibcon#read 5, iclass 10, count 2 2006.246.08:07:30.44#ibcon#about to read 6, iclass 10, count 2 2006.246.08:07:30.44#ibcon#read 6, iclass 10, count 2 2006.246.08:07:30.44#ibcon#end of sib2, iclass 10, count 2 2006.246.08:07:30.44#ibcon#*after write, iclass 10, count 2 2006.246.08:07:30.44#ibcon#*before return 0, iclass 10, count 2 2006.246.08:07:30.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:07:30.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:07:30.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.08:07:30.44#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:30.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:07:30.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:07:30.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:07:30.56#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:07:30.56#ibcon#first serial, iclass 10, count 0 2006.246.08:07:30.56#ibcon#enter sib2, iclass 10, count 0 2006.246.08:07:30.56#ibcon#flushed, iclass 10, count 0 2006.246.08:07:30.56#ibcon#about to write, iclass 10, count 0 2006.246.08:07:30.56#ibcon#wrote, iclass 10, count 0 2006.246.08:07:30.56#ibcon#about to read 3, iclass 10, count 0 2006.246.08:07:30.58#ibcon#read 3, iclass 10, count 0 2006.246.08:07:30.58#ibcon#about to read 4, iclass 10, count 0 2006.246.08:07:30.58#ibcon#read 4, iclass 10, count 0 2006.246.08:07:30.58#ibcon#about to read 5, iclass 10, count 0 2006.246.08:07:30.58#ibcon#read 5, iclass 10, count 0 2006.246.08:07:30.58#ibcon#about to read 6, iclass 10, count 0 2006.246.08:07:30.58#ibcon#read 6, iclass 10, count 0 2006.246.08:07:30.58#ibcon#end of sib2, iclass 10, count 0 2006.246.08:07:30.58#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:07:30.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:07:30.58#ibcon#[25=USB\r\n] 2006.246.08:07:30.58#ibcon#*before write, iclass 10, count 0 2006.246.08:07:30.58#ibcon#enter sib2, iclass 10, count 0 2006.246.08:07:30.58#ibcon#flushed, iclass 10, count 0 2006.246.08:07:30.58#ibcon#about to write, iclass 10, count 0 2006.246.08:07:30.58#ibcon#wrote, iclass 10, count 0 2006.246.08:07:30.58#ibcon#about to read 3, iclass 10, count 0 2006.246.08:07:30.61#ibcon#read 3, iclass 10, count 0 2006.246.08:07:30.61#ibcon#about to read 4, iclass 10, count 0 2006.246.08:07:30.61#ibcon#read 4, iclass 10, count 0 2006.246.08:07:30.61#ibcon#about to read 5, iclass 10, count 0 2006.246.08:07:30.61#ibcon#read 5, iclass 10, count 0 2006.246.08:07:30.61#ibcon#about to read 6, iclass 10, count 0 2006.246.08:07:30.61#ibcon#read 6, iclass 10, count 0 2006.246.08:07:30.61#ibcon#end of sib2, iclass 10, count 0 2006.246.08:07:30.61#ibcon#*after write, iclass 10, count 0 2006.246.08:07:30.61#ibcon#*before return 0, iclass 10, count 0 2006.246.08:07:30.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:07:30.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:07:30.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:07:30.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:07:30.61$vc4f8/vblo=1,632.99 2006.246.08:07:30.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.08:07:30.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.08:07:30.61#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:30.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:07:30.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:07:30.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:07:30.61#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:07:30.61#ibcon#first serial, iclass 12, count 0 2006.246.08:07:30.61#ibcon#enter sib2, iclass 12, count 0 2006.246.08:07:30.61#ibcon#flushed, iclass 12, count 0 2006.246.08:07:30.61#ibcon#about to write, iclass 12, count 0 2006.246.08:07:30.61#ibcon#wrote, iclass 12, count 0 2006.246.08:07:30.61#ibcon#about to read 3, iclass 12, count 0 2006.246.08:07:30.63#ibcon#read 3, iclass 12, count 0 2006.246.08:07:30.63#ibcon#about to read 4, iclass 12, count 0 2006.246.08:07:30.63#ibcon#read 4, iclass 12, count 0 2006.246.08:07:30.63#ibcon#about to read 5, iclass 12, count 0 2006.246.08:07:30.63#ibcon#read 5, iclass 12, count 0 2006.246.08:07:30.63#ibcon#about to read 6, iclass 12, count 0 2006.246.08:07:30.63#ibcon#read 6, iclass 12, count 0 2006.246.08:07:30.63#ibcon#end of sib2, iclass 12, count 0 2006.246.08:07:30.63#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:07:30.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:07:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:07:30.63#ibcon#*before write, iclass 12, count 0 2006.246.08:07:30.63#ibcon#enter sib2, iclass 12, count 0 2006.246.08:07:30.63#ibcon#flushed, iclass 12, count 0 2006.246.08:07:30.63#ibcon#about to write, iclass 12, count 0 2006.246.08:07:30.63#ibcon#wrote, iclass 12, count 0 2006.246.08:07:30.63#ibcon#about to read 3, iclass 12, count 0 2006.246.08:07:30.67#ibcon#read 3, iclass 12, count 0 2006.246.08:07:30.67#ibcon#about to read 4, iclass 12, count 0 2006.246.08:07:30.67#ibcon#read 4, iclass 12, count 0 2006.246.08:07:30.67#ibcon#about to read 5, iclass 12, count 0 2006.246.08:07:30.67#ibcon#read 5, iclass 12, count 0 2006.246.08:07:30.67#ibcon#about to read 6, iclass 12, count 0 2006.246.08:07:30.67#ibcon#read 6, iclass 12, count 0 2006.246.08:07:30.67#ibcon#end of sib2, iclass 12, count 0 2006.246.08:07:30.67#ibcon#*after write, iclass 12, count 0 2006.246.08:07:30.67#ibcon#*before return 0, iclass 12, count 0 2006.246.08:07:30.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:07:30.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:07:30.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:07:30.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:07:30.67$vc4f8/vb=1,4 2006.246.08:07:30.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.08:07:30.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.08:07:30.67#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:30.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:07:30.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:07:30.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:07:30.67#ibcon#enter wrdev, iclass 14, count 2 2006.246.08:07:30.67#ibcon#first serial, iclass 14, count 2 2006.246.08:07:30.67#ibcon#enter sib2, iclass 14, count 2 2006.246.08:07:30.67#ibcon#flushed, iclass 14, count 2 2006.246.08:07:30.67#ibcon#about to write, iclass 14, count 2 2006.246.08:07:30.67#ibcon#wrote, iclass 14, count 2 2006.246.08:07:30.67#ibcon#about to read 3, iclass 14, count 2 2006.246.08:07:30.69#ibcon#read 3, iclass 14, count 2 2006.246.08:07:30.69#ibcon#about to read 4, iclass 14, count 2 2006.246.08:07:30.69#ibcon#read 4, iclass 14, count 2 2006.246.08:07:30.69#ibcon#about to read 5, iclass 14, count 2 2006.246.08:07:30.69#ibcon#read 5, iclass 14, count 2 2006.246.08:07:30.69#ibcon#about to read 6, iclass 14, count 2 2006.246.08:07:30.69#ibcon#read 6, iclass 14, count 2 2006.246.08:07:30.69#ibcon#end of sib2, iclass 14, count 2 2006.246.08:07:30.69#ibcon#*mode == 0, iclass 14, count 2 2006.246.08:07:30.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.08:07:30.69#ibcon#[27=AT01-04\r\n] 2006.246.08:07:30.69#ibcon#*before write, iclass 14, count 2 2006.246.08:07:30.69#ibcon#enter sib2, iclass 14, count 2 2006.246.08:07:30.69#ibcon#flushed, iclass 14, count 2 2006.246.08:07:30.69#ibcon#about to write, iclass 14, count 2 2006.246.08:07:30.69#ibcon#wrote, iclass 14, count 2 2006.246.08:07:30.69#ibcon#about to read 3, iclass 14, count 2 2006.246.08:07:30.72#ibcon#read 3, iclass 14, count 2 2006.246.08:07:30.72#ibcon#about to read 4, iclass 14, count 2 2006.246.08:07:30.72#ibcon#read 4, iclass 14, count 2 2006.246.08:07:30.72#ibcon#about to read 5, iclass 14, count 2 2006.246.08:07:30.72#ibcon#read 5, iclass 14, count 2 2006.246.08:07:30.72#ibcon#about to read 6, iclass 14, count 2 2006.246.08:07:30.72#ibcon#read 6, iclass 14, count 2 2006.246.08:07:30.72#ibcon#end of sib2, iclass 14, count 2 2006.246.08:07:30.72#ibcon#*after write, iclass 14, count 2 2006.246.08:07:30.72#ibcon#*before return 0, iclass 14, count 2 2006.246.08:07:30.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:07:30.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:07:30.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.08:07:30.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:30.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:07:30.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:07:30.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:07:30.84#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:07:30.84#ibcon#first serial, iclass 14, count 0 2006.246.08:07:30.84#ibcon#enter sib2, iclass 14, count 0 2006.246.08:07:30.84#ibcon#flushed, iclass 14, count 0 2006.246.08:07:30.84#ibcon#about to write, iclass 14, count 0 2006.246.08:07:30.84#ibcon#wrote, iclass 14, count 0 2006.246.08:07:30.84#ibcon#about to read 3, iclass 14, count 0 2006.246.08:07:30.86#ibcon#read 3, iclass 14, count 0 2006.246.08:07:30.86#ibcon#about to read 4, iclass 14, count 0 2006.246.08:07:30.86#ibcon#read 4, iclass 14, count 0 2006.246.08:07:30.86#ibcon#about to read 5, iclass 14, count 0 2006.246.08:07:30.86#ibcon#read 5, iclass 14, count 0 2006.246.08:07:30.86#ibcon#about to read 6, iclass 14, count 0 2006.246.08:07:30.86#ibcon#read 6, iclass 14, count 0 2006.246.08:07:30.86#ibcon#end of sib2, iclass 14, count 0 2006.246.08:07:30.86#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:07:30.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:07:30.86#ibcon#[27=USB\r\n] 2006.246.08:07:30.86#ibcon#*before write, iclass 14, count 0 2006.246.08:07:30.86#ibcon#enter sib2, iclass 14, count 0 2006.246.08:07:30.86#ibcon#flushed, iclass 14, count 0 2006.246.08:07:30.86#ibcon#about to write, iclass 14, count 0 2006.246.08:07:30.86#ibcon#wrote, iclass 14, count 0 2006.246.08:07:30.86#ibcon#about to read 3, iclass 14, count 0 2006.246.08:07:30.89#ibcon#read 3, iclass 14, count 0 2006.246.08:07:30.89#ibcon#about to read 4, iclass 14, count 0 2006.246.08:07:30.89#ibcon#read 4, iclass 14, count 0 2006.246.08:07:30.89#ibcon#about to read 5, iclass 14, count 0 2006.246.08:07:30.89#ibcon#read 5, iclass 14, count 0 2006.246.08:07:30.89#ibcon#about to read 6, iclass 14, count 0 2006.246.08:07:30.89#ibcon#read 6, iclass 14, count 0 2006.246.08:07:30.89#ibcon#end of sib2, iclass 14, count 0 2006.246.08:07:30.89#ibcon#*after write, iclass 14, count 0 2006.246.08:07:30.89#ibcon#*before return 0, iclass 14, count 0 2006.246.08:07:30.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:07:30.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:07:30.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:07:30.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:07:30.89$vc4f8/vblo=2,640.99 2006.246.08:07:30.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.08:07:30.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.08:07:30.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:30.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:30.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:30.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:30.89#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:07:30.89#ibcon#first serial, iclass 16, count 0 2006.246.08:07:30.89#ibcon#enter sib2, iclass 16, count 0 2006.246.08:07:30.89#ibcon#flushed, iclass 16, count 0 2006.246.08:07:30.89#ibcon#about to write, iclass 16, count 0 2006.246.08:07:30.89#ibcon#wrote, iclass 16, count 0 2006.246.08:07:30.89#ibcon#about to read 3, iclass 16, count 0 2006.246.08:07:30.91#ibcon#read 3, iclass 16, count 0 2006.246.08:07:30.91#ibcon#about to read 4, iclass 16, count 0 2006.246.08:07:30.91#ibcon#read 4, iclass 16, count 0 2006.246.08:07:30.91#ibcon#about to read 5, iclass 16, count 0 2006.246.08:07:30.91#ibcon#read 5, iclass 16, count 0 2006.246.08:07:30.91#ibcon#about to read 6, iclass 16, count 0 2006.246.08:07:30.91#ibcon#read 6, iclass 16, count 0 2006.246.08:07:30.91#ibcon#end of sib2, iclass 16, count 0 2006.246.08:07:30.91#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:07:30.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:07:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:07:30.91#ibcon#*before write, iclass 16, count 0 2006.246.08:07:30.91#ibcon#enter sib2, iclass 16, count 0 2006.246.08:07:30.91#ibcon#flushed, iclass 16, count 0 2006.246.08:07:30.91#ibcon#about to write, iclass 16, count 0 2006.246.08:07:30.91#ibcon#wrote, iclass 16, count 0 2006.246.08:07:30.91#ibcon#about to read 3, iclass 16, count 0 2006.246.08:07:30.95#ibcon#read 3, iclass 16, count 0 2006.246.08:07:30.95#ibcon#about to read 4, iclass 16, count 0 2006.246.08:07:30.95#ibcon#read 4, iclass 16, count 0 2006.246.08:07:30.95#ibcon#about to read 5, iclass 16, count 0 2006.246.08:07:30.95#ibcon#read 5, iclass 16, count 0 2006.246.08:07:30.95#ibcon#about to read 6, iclass 16, count 0 2006.246.08:07:30.95#ibcon#read 6, iclass 16, count 0 2006.246.08:07:30.95#ibcon#end of sib2, iclass 16, count 0 2006.246.08:07:30.95#ibcon#*after write, iclass 16, count 0 2006.246.08:07:30.95#ibcon#*before return 0, iclass 16, count 0 2006.246.08:07:30.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:30.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:07:30.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:07:30.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:07:30.95$vc4f8/vb=2,4 2006.246.08:07:30.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.08:07:30.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.08:07:30.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:30.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:31.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:31.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:31.01#ibcon#enter wrdev, iclass 18, count 2 2006.246.08:07:31.01#ibcon#first serial, iclass 18, count 2 2006.246.08:07:31.01#ibcon#enter sib2, iclass 18, count 2 2006.246.08:07:31.01#ibcon#flushed, iclass 18, count 2 2006.246.08:07:31.01#ibcon#about to write, iclass 18, count 2 2006.246.08:07:31.01#ibcon#wrote, iclass 18, count 2 2006.246.08:07:31.01#ibcon#about to read 3, iclass 18, count 2 2006.246.08:07:31.03#ibcon#read 3, iclass 18, count 2 2006.246.08:07:31.03#ibcon#about to read 4, iclass 18, count 2 2006.246.08:07:31.03#ibcon#read 4, iclass 18, count 2 2006.246.08:07:31.03#ibcon#about to read 5, iclass 18, count 2 2006.246.08:07:31.03#ibcon#read 5, iclass 18, count 2 2006.246.08:07:31.03#ibcon#about to read 6, iclass 18, count 2 2006.246.08:07:31.03#ibcon#read 6, iclass 18, count 2 2006.246.08:07:31.03#ibcon#end of sib2, iclass 18, count 2 2006.246.08:07:31.03#ibcon#*mode == 0, iclass 18, count 2 2006.246.08:07:31.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.08:07:31.03#ibcon#[27=AT02-04\r\n] 2006.246.08:07:31.03#ibcon#*before write, iclass 18, count 2 2006.246.08:07:31.03#ibcon#enter sib2, iclass 18, count 2 2006.246.08:07:31.03#ibcon#flushed, iclass 18, count 2 2006.246.08:07:31.03#ibcon#about to write, iclass 18, count 2 2006.246.08:07:31.03#ibcon#wrote, iclass 18, count 2 2006.246.08:07:31.03#ibcon#about to read 3, iclass 18, count 2 2006.246.08:07:31.06#ibcon#read 3, iclass 18, count 2 2006.246.08:07:31.06#ibcon#about to read 4, iclass 18, count 2 2006.246.08:07:31.06#ibcon#read 4, iclass 18, count 2 2006.246.08:07:31.06#ibcon#about to read 5, iclass 18, count 2 2006.246.08:07:31.06#ibcon#read 5, iclass 18, count 2 2006.246.08:07:31.06#ibcon#about to read 6, iclass 18, count 2 2006.246.08:07:31.06#ibcon#read 6, iclass 18, count 2 2006.246.08:07:31.06#ibcon#end of sib2, iclass 18, count 2 2006.246.08:07:31.06#ibcon#*after write, iclass 18, count 2 2006.246.08:07:31.06#ibcon#*before return 0, iclass 18, count 2 2006.246.08:07:31.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:31.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:07:31.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.08:07:31.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:31.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:31.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:31.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:31.18#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:07:31.18#ibcon#first serial, iclass 18, count 0 2006.246.08:07:31.18#ibcon#enter sib2, iclass 18, count 0 2006.246.08:07:31.18#ibcon#flushed, iclass 18, count 0 2006.246.08:07:31.18#ibcon#about to write, iclass 18, count 0 2006.246.08:07:31.18#ibcon#wrote, iclass 18, count 0 2006.246.08:07:31.18#ibcon#about to read 3, iclass 18, count 0 2006.246.08:07:31.20#ibcon#read 3, iclass 18, count 0 2006.246.08:07:31.20#ibcon#about to read 4, iclass 18, count 0 2006.246.08:07:31.20#ibcon#read 4, iclass 18, count 0 2006.246.08:07:31.20#ibcon#about to read 5, iclass 18, count 0 2006.246.08:07:31.20#ibcon#read 5, iclass 18, count 0 2006.246.08:07:31.20#ibcon#about to read 6, iclass 18, count 0 2006.246.08:07:31.20#ibcon#read 6, iclass 18, count 0 2006.246.08:07:31.20#ibcon#end of sib2, iclass 18, count 0 2006.246.08:07:31.20#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:07:31.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:07:31.20#ibcon#[27=USB\r\n] 2006.246.08:07:31.20#ibcon#*before write, iclass 18, count 0 2006.246.08:07:31.20#ibcon#enter sib2, iclass 18, count 0 2006.246.08:07:31.20#ibcon#flushed, iclass 18, count 0 2006.246.08:07:31.20#ibcon#about to write, iclass 18, count 0 2006.246.08:07:31.20#ibcon#wrote, iclass 18, count 0 2006.246.08:07:31.20#ibcon#about to read 3, iclass 18, count 0 2006.246.08:07:31.23#ibcon#read 3, iclass 18, count 0 2006.246.08:07:31.23#ibcon#about to read 4, iclass 18, count 0 2006.246.08:07:31.23#ibcon#read 4, iclass 18, count 0 2006.246.08:07:31.23#ibcon#about to read 5, iclass 18, count 0 2006.246.08:07:31.23#ibcon#read 5, iclass 18, count 0 2006.246.08:07:31.23#ibcon#about to read 6, iclass 18, count 0 2006.246.08:07:31.23#ibcon#read 6, iclass 18, count 0 2006.246.08:07:31.23#ibcon#end of sib2, iclass 18, count 0 2006.246.08:07:31.23#ibcon#*after write, iclass 18, count 0 2006.246.08:07:31.23#ibcon#*before return 0, iclass 18, count 0 2006.246.08:07:31.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:31.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:07:31.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:07:31.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:07:31.23$vc4f8/vblo=3,656.99 2006.246.08:07:31.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.08:07:31.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.08:07:31.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:31.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:31.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:31.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:31.23#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:07:31.23#ibcon#first serial, iclass 20, count 0 2006.246.08:07:31.23#ibcon#enter sib2, iclass 20, count 0 2006.246.08:07:31.23#ibcon#flushed, iclass 20, count 0 2006.246.08:07:31.23#ibcon#about to write, iclass 20, count 0 2006.246.08:07:31.23#ibcon#wrote, iclass 20, count 0 2006.246.08:07:31.23#ibcon#about to read 3, iclass 20, count 0 2006.246.08:07:31.25#ibcon#read 3, iclass 20, count 0 2006.246.08:07:31.25#ibcon#about to read 4, iclass 20, count 0 2006.246.08:07:31.25#ibcon#read 4, iclass 20, count 0 2006.246.08:07:31.25#ibcon#about to read 5, iclass 20, count 0 2006.246.08:07:31.25#ibcon#read 5, iclass 20, count 0 2006.246.08:07:31.25#ibcon#about to read 6, iclass 20, count 0 2006.246.08:07:31.25#ibcon#read 6, iclass 20, count 0 2006.246.08:07:31.25#ibcon#end of sib2, iclass 20, count 0 2006.246.08:07:31.25#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:07:31.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:07:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:07:31.25#ibcon#*before write, iclass 20, count 0 2006.246.08:07:31.25#ibcon#enter sib2, iclass 20, count 0 2006.246.08:07:31.25#ibcon#flushed, iclass 20, count 0 2006.246.08:07:31.25#ibcon#about to write, iclass 20, count 0 2006.246.08:07:31.25#ibcon#wrote, iclass 20, count 0 2006.246.08:07:31.25#ibcon#about to read 3, iclass 20, count 0 2006.246.08:07:31.29#ibcon#read 3, iclass 20, count 0 2006.246.08:07:31.29#ibcon#about to read 4, iclass 20, count 0 2006.246.08:07:31.29#ibcon#read 4, iclass 20, count 0 2006.246.08:07:31.29#ibcon#about to read 5, iclass 20, count 0 2006.246.08:07:31.29#ibcon#read 5, iclass 20, count 0 2006.246.08:07:31.29#ibcon#about to read 6, iclass 20, count 0 2006.246.08:07:31.29#ibcon#read 6, iclass 20, count 0 2006.246.08:07:31.29#ibcon#end of sib2, iclass 20, count 0 2006.246.08:07:31.29#ibcon#*after write, iclass 20, count 0 2006.246.08:07:31.29#ibcon#*before return 0, iclass 20, count 0 2006.246.08:07:31.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:31.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:07:31.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:07:31.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:07:31.29$vc4f8/vb=3,4 2006.246.08:07:31.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.08:07:31.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.08:07:31.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:31.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:31.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:31.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:31.35#ibcon#enter wrdev, iclass 22, count 2 2006.246.08:07:31.35#ibcon#first serial, iclass 22, count 2 2006.246.08:07:31.35#ibcon#enter sib2, iclass 22, count 2 2006.246.08:07:31.35#ibcon#flushed, iclass 22, count 2 2006.246.08:07:31.35#ibcon#about to write, iclass 22, count 2 2006.246.08:07:31.35#ibcon#wrote, iclass 22, count 2 2006.246.08:07:31.35#ibcon#about to read 3, iclass 22, count 2 2006.246.08:07:31.37#ibcon#read 3, iclass 22, count 2 2006.246.08:07:31.37#ibcon#about to read 4, iclass 22, count 2 2006.246.08:07:31.37#ibcon#read 4, iclass 22, count 2 2006.246.08:07:31.37#ibcon#about to read 5, iclass 22, count 2 2006.246.08:07:31.37#ibcon#read 5, iclass 22, count 2 2006.246.08:07:31.37#ibcon#about to read 6, iclass 22, count 2 2006.246.08:07:31.37#ibcon#read 6, iclass 22, count 2 2006.246.08:07:31.37#ibcon#end of sib2, iclass 22, count 2 2006.246.08:07:31.37#ibcon#*mode == 0, iclass 22, count 2 2006.246.08:07:31.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.08:07:31.37#ibcon#[27=AT03-04\r\n] 2006.246.08:07:31.37#ibcon#*before write, iclass 22, count 2 2006.246.08:07:31.37#ibcon#enter sib2, iclass 22, count 2 2006.246.08:07:31.37#ibcon#flushed, iclass 22, count 2 2006.246.08:07:31.37#ibcon#about to write, iclass 22, count 2 2006.246.08:07:31.37#ibcon#wrote, iclass 22, count 2 2006.246.08:07:31.37#ibcon#about to read 3, iclass 22, count 2 2006.246.08:07:31.40#ibcon#read 3, iclass 22, count 2 2006.246.08:07:31.40#ibcon#about to read 4, iclass 22, count 2 2006.246.08:07:31.40#ibcon#read 4, iclass 22, count 2 2006.246.08:07:31.40#ibcon#about to read 5, iclass 22, count 2 2006.246.08:07:31.40#ibcon#read 5, iclass 22, count 2 2006.246.08:07:31.40#ibcon#about to read 6, iclass 22, count 2 2006.246.08:07:31.40#ibcon#read 6, iclass 22, count 2 2006.246.08:07:31.40#ibcon#end of sib2, iclass 22, count 2 2006.246.08:07:31.40#ibcon#*after write, iclass 22, count 2 2006.246.08:07:31.40#ibcon#*before return 0, iclass 22, count 2 2006.246.08:07:31.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:31.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:07:31.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.08:07:31.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:31.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:31.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:31.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:31.52#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:07:31.52#ibcon#first serial, iclass 22, count 0 2006.246.08:07:31.52#ibcon#enter sib2, iclass 22, count 0 2006.246.08:07:31.52#ibcon#flushed, iclass 22, count 0 2006.246.08:07:31.52#ibcon#about to write, iclass 22, count 0 2006.246.08:07:31.52#ibcon#wrote, iclass 22, count 0 2006.246.08:07:31.52#ibcon#about to read 3, iclass 22, count 0 2006.246.08:07:31.54#ibcon#read 3, iclass 22, count 0 2006.246.08:07:31.54#ibcon#about to read 4, iclass 22, count 0 2006.246.08:07:31.54#ibcon#read 4, iclass 22, count 0 2006.246.08:07:31.54#ibcon#about to read 5, iclass 22, count 0 2006.246.08:07:31.54#ibcon#read 5, iclass 22, count 0 2006.246.08:07:31.54#ibcon#about to read 6, iclass 22, count 0 2006.246.08:07:31.54#ibcon#read 6, iclass 22, count 0 2006.246.08:07:31.54#ibcon#end of sib2, iclass 22, count 0 2006.246.08:07:31.54#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:07:31.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:07:31.54#ibcon#[27=USB\r\n] 2006.246.08:07:31.54#ibcon#*before write, iclass 22, count 0 2006.246.08:07:31.54#ibcon#enter sib2, iclass 22, count 0 2006.246.08:07:31.54#ibcon#flushed, iclass 22, count 0 2006.246.08:07:31.54#ibcon#about to write, iclass 22, count 0 2006.246.08:07:31.54#ibcon#wrote, iclass 22, count 0 2006.246.08:07:31.54#ibcon#about to read 3, iclass 22, count 0 2006.246.08:07:31.57#ibcon#read 3, iclass 22, count 0 2006.246.08:07:31.57#ibcon#about to read 4, iclass 22, count 0 2006.246.08:07:31.57#ibcon#read 4, iclass 22, count 0 2006.246.08:07:31.57#ibcon#about to read 5, iclass 22, count 0 2006.246.08:07:31.57#ibcon#read 5, iclass 22, count 0 2006.246.08:07:31.57#ibcon#about to read 6, iclass 22, count 0 2006.246.08:07:31.57#ibcon#read 6, iclass 22, count 0 2006.246.08:07:31.57#ibcon#end of sib2, iclass 22, count 0 2006.246.08:07:31.57#ibcon#*after write, iclass 22, count 0 2006.246.08:07:31.57#ibcon#*before return 0, iclass 22, count 0 2006.246.08:07:31.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:31.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:07:31.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:07:31.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:07:31.57$vc4f8/vblo=4,712.99 2006.246.08:07:31.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.08:07:31.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.08:07:31.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:31.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:31.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:31.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:31.57#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:07:31.57#ibcon#first serial, iclass 24, count 0 2006.246.08:07:31.57#ibcon#enter sib2, iclass 24, count 0 2006.246.08:07:31.57#ibcon#flushed, iclass 24, count 0 2006.246.08:07:31.57#ibcon#about to write, iclass 24, count 0 2006.246.08:07:31.57#ibcon#wrote, iclass 24, count 0 2006.246.08:07:31.57#ibcon#about to read 3, iclass 24, count 0 2006.246.08:07:31.59#ibcon#read 3, iclass 24, count 0 2006.246.08:07:31.59#ibcon#about to read 4, iclass 24, count 0 2006.246.08:07:31.59#ibcon#read 4, iclass 24, count 0 2006.246.08:07:31.59#ibcon#about to read 5, iclass 24, count 0 2006.246.08:07:31.59#ibcon#read 5, iclass 24, count 0 2006.246.08:07:31.59#ibcon#about to read 6, iclass 24, count 0 2006.246.08:07:31.59#ibcon#read 6, iclass 24, count 0 2006.246.08:07:31.59#ibcon#end of sib2, iclass 24, count 0 2006.246.08:07:31.59#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:07:31.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:07:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:07:31.59#ibcon#*before write, iclass 24, count 0 2006.246.08:07:31.59#ibcon#enter sib2, iclass 24, count 0 2006.246.08:07:31.59#ibcon#flushed, iclass 24, count 0 2006.246.08:07:31.59#ibcon#about to write, iclass 24, count 0 2006.246.08:07:31.59#ibcon#wrote, iclass 24, count 0 2006.246.08:07:31.59#ibcon#about to read 3, iclass 24, count 0 2006.246.08:07:31.63#ibcon#read 3, iclass 24, count 0 2006.246.08:07:31.63#ibcon#about to read 4, iclass 24, count 0 2006.246.08:07:31.63#ibcon#read 4, iclass 24, count 0 2006.246.08:07:31.63#ibcon#about to read 5, iclass 24, count 0 2006.246.08:07:31.63#ibcon#read 5, iclass 24, count 0 2006.246.08:07:31.63#ibcon#about to read 6, iclass 24, count 0 2006.246.08:07:31.63#ibcon#read 6, iclass 24, count 0 2006.246.08:07:31.63#ibcon#end of sib2, iclass 24, count 0 2006.246.08:07:31.63#ibcon#*after write, iclass 24, count 0 2006.246.08:07:31.63#ibcon#*before return 0, iclass 24, count 0 2006.246.08:07:31.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:31.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:07:31.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:07:31.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:07:31.63$vc4f8/vb=4,4 2006.246.08:07:31.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.08:07:31.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.08:07:31.63#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:31.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:31.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:31.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:31.69#ibcon#enter wrdev, iclass 26, count 2 2006.246.08:07:31.69#ibcon#first serial, iclass 26, count 2 2006.246.08:07:31.69#ibcon#enter sib2, iclass 26, count 2 2006.246.08:07:31.69#ibcon#flushed, iclass 26, count 2 2006.246.08:07:31.69#ibcon#about to write, iclass 26, count 2 2006.246.08:07:31.69#ibcon#wrote, iclass 26, count 2 2006.246.08:07:31.69#ibcon#about to read 3, iclass 26, count 2 2006.246.08:07:31.71#ibcon#read 3, iclass 26, count 2 2006.246.08:07:31.71#ibcon#about to read 4, iclass 26, count 2 2006.246.08:07:31.71#ibcon#read 4, iclass 26, count 2 2006.246.08:07:31.71#ibcon#about to read 5, iclass 26, count 2 2006.246.08:07:31.71#ibcon#read 5, iclass 26, count 2 2006.246.08:07:31.71#ibcon#about to read 6, iclass 26, count 2 2006.246.08:07:31.71#ibcon#read 6, iclass 26, count 2 2006.246.08:07:31.71#ibcon#end of sib2, iclass 26, count 2 2006.246.08:07:31.71#ibcon#*mode == 0, iclass 26, count 2 2006.246.08:07:31.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.08:07:31.71#ibcon#[27=AT04-04\r\n] 2006.246.08:07:31.71#ibcon#*before write, iclass 26, count 2 2006.246.08:07:31.71#ibcon#enter sib2, iclass 26, count 2 2006.246.08:07:31.71#ibcon#flushed, iclass 26, count 2 2006.246.08:07:31.71#ibcon#about to write, iclass 26, count 2 2006.246.08:07:31.71#ibcon#wrote, iclass 26, count 2 2006.246.08:07:31.71#ibcon#about to read 3, iclass 26, count 2 2006.246.08:07:31.74#ibcon#read 3, iclass 26, count 2 2006.246.08:07:31.74#ibcon#about to read 4, iclass 26, count 2 2006.246.08:07:31.74#ibcon#read 4, iclass 26, count 2 2006.246.08:07:31.74#ibcon#about to read 5, iclass 26, count 2 2006.246.08:07:31.74#ibcon#read 5, iclass 26, count 2 2006.246.08:07:31.74#ibcon#about to read 6, iclass 26, count 2 2006.246.08:07:31.74#ibcon#read 6, iclass 26, count 2 2006.246.08:07:31.74#ibcon#end of sib2, iclass 26, count 2 2006.246.08:07:31.74#ibcon#*after write, iclass 26, count 2 2006.246.08:07:31.74#ibcon#*before return 0, iclass 26, count 2 2006.246.08:07:31.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:31.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:07:31.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.08:07:31.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:31.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:31.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:31.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:31.86#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:07:31.86#ibcon#first serial, iclass 26, count 0 2006.246.08:07:31.86#ibcon#enter sib2, iclass 26, count 0 2006.246.08:07:31.86#ibcon#flushed, iclass 26, count 0 2006.246.08:07:31.86#ibcon#about to write, iclass 26, count 0 2006.246.08:07:31.86#ibcon#wrote, iclass 26, count 0 2006.246.08:07:31.86#ibcon#about to read 3, iclass 26, count 0 2006.246.08:07:31.88#ibcon#read 3, iclass 26, count 0 2006.246.08:07:31.88#ibcon#about to read 4, iclass 26, count 0 2006.246.08:07:31.88#ibcon#read 4, iclass 26, count 0 2006.246.08:07:31.88#ibcon#about to read 5, iclass 26, count 0 2006.246.08:07:31.88#ibcon#read 5, iclass 26, count 0 2006.246.08:07:31.88#ibcon#about to read 6, iclass 26, count 0 2006.246.08:07:31.88#ibcon#read 6, iclass 26, count 0 2006.246.08:07:31.88#ibcon#end of sib2, iclass 26, count 0 2006.246.08:07:31.88#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:07:31.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:07:31.88#ibcon#[27=USB\r\n] 2006.246.08:07:31.88#ibcon#*before write, iclass 26, count 0 2006.246.08:07:31.88#ibcon#enter sib2, iclass 26, count 0 2006.246.08:07:31.88#ibcon#flushed, iclass 26, count 0 2006.246.08:07:31.88#ibcon#about to write, iclass 26, count 0 2006.246.08:07:31.88#ibcon#wrote, iclass 26, count 0 2006.246.08:07:31.88#ibcon#about to read 3, iclass 26, count 0 2006.246.08:07:31.91#ibcon#read 3, iclass 26, count 0 2006.246.08:07:31.91#ibcon#about to read 4, iclass 26, count 0 2006.246.08:07:31.91#ibcon#read 4, iclass 26, count 0 2006.246.08:07:31.91#ibcon#about to read 5, iclass 26, count 0 2006.246.08:07:31.91#ibcon#read 5, iclass 26, count 0 2006.246.08:07:31.91#ibcon#about to read 6, iclass 26, count 0 2006.246.08:07:31.91#ibcon#read 6, iclass 26, count 0 2006.246.08:07:31.91#ibcon#end of sib2, iclass 26, count 0 2006.246.08:07:31.91#ibcon#*after write, iclass 26, count 0 2006.246.08:07:31.91#ibcon#*before return 0, iclass 26, count 0 2006.246.08:07:31.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:31.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:07:31.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:07:31.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:07:31.91$vc4f8/vblo=5,744.99 2006.246.08:07:31.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.08:07:31.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.08:07:31.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:31.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:31.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:31.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:31.91#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:07:31.91#ibcon#first serial, iclass 28, count 0 2006.246.08:07:31.91#ibcon#enter sib2, iclass 28, count 0 2006.246.08:07:31.91#ibcon#flushed, iclass 28, count 0 2006.246.08:07:31.91#ibcon#about to write, iclass 28, count 0 2006.246.08:07:31.91#ibcon#wrote, iclass 28, count 0 2006.246.08:07:31.91#ibcon#about to read 3, iclass 28, count 0 2006.246.08:07:31.93#ibcon#read 3, iclass 28, count 0 2006.246.08:07:31.93#ibcon#about to read 4, iclass 28, count 0 2006.246.08:07:31.93#ibcon#read 4, iclass 28, count 0 2006.246.08:07:31.93#ibcon#about to read 5, iclass 28, count 0 2006.246.08:07:31.93#ibcon#read 5, iclass 28, count 0 2006.246.08:07:31.93#ibcon#about to read 6, iclass 28, count 0 2006.246.08:07:31.93#ibcon#read 6, iclass 28, count 0 2006.246.08:07:31.93#ibcon#end of sib2, iclass 28, count 0 2006.246.08:07:31.93#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:07:31.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:07:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:07:31.93#ibcon#*before write, iclass 28, count 0 2006.246.08:07:31.93#ibcon#enter sib2, iclass 28, count 0 2006.246.08:07:31.93#ibcon#flushed, iclass 28, count 0 2006.246.08:07:31.93#ibcon#about to write, iclass 28, count 0 2006.246.08:07:31.93#ibcon#wrote, iclass 28, count 0 2006.246.08:07:31.93#ibcon#about to read 3, iclass 28, count 0 2006.246.08:07:31.97#ibcon#read 3, iclass 28, count 0 2006.246.08:07:31.97#ibcon#about to read 4, iclass 28, count 0 2006.246.08:07:31.97#ibcon#read 4, iclass 28, count 0 2006.246.08:07:31.97#ibcon#about to read 5, iclass 28, count 0 2006.246.08:07:31.97#ibcon#read 5, iclass 28, count 0 2006.246.08:07:31.97#ibcon#about to read 6, iclass 28, count 0 2006.246.08:07:31.97#ibcon#read 6, iclass 28, count 0 2006.246.08:07:31.97#ibcon#end of sib2, iclass 28, count 0 2006.246.08:07:31.97#ibcon#*after write, iclass 28, count 0 2006.246.08:07:31.97#ibcon#*before return 0, iclass 28, count 0 2006.246.08:07:31.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:31.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:07:31.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:07:31.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:07:31.97$vc4f8/vb=5,3 2006.246.08:07:31.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.08:07:31.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.08:07:31.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:31.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:32.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:32.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:32.03#ibcon#enter wrdev, iclass 30, count 2 2006.246.08:07:32.03#ibcon#first serial, iclass 30, count 2 2006.246.08:07:32.03#ibcon#enter sib2, iclass 30, count 2 2006.246.08:07:32.03#ibcon#flushed, iclass 30, count 2 2006.246.08:07:32.03#ibcon#about to write, iclass 30, count 2 2006.246.08:07:32.03#ibcon#wrote, iclass 30, count 2 2006.246.08:07:32.03#ibcon#about to read 3, iclass 30, count 2 2006.246.08:07:32.05#ibcon#read 3, iclass 30, count 2 2006.246.08:07:32.05#ibcon#about to read 4, iclass 30, count 2 2006.246.08:07:32.05#ibcon#read 4, iclass 30, count 2 2006.246.08:07:32.05#ibcon#about to read 5, iclass 30, count 2 2006.246.08:07:32.05#ibcon#read 5, iclass 30, count 2 2006.246.08:07:32.05#ibcon#about to read 6, iclass 30, count 2 2006.246.08:07:32.05#ibcon#read 6, iclass 30, count 2 2006.246.08:07:32.05#ibcon#end of sib2, iclass 30, count 2 2006.246.08:07:32.05#ibcon#*mode == 0, iclass 30, count 2 2006.246.08:07:32.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.08:07:32.05#ibcon#[27=AT05-03\r\n] 2006.246.08:07:32.05#ibcon#*before write, iclass 30, count 2 2006.246.08:07:32.05#ibcon#enter sib2, iclass 30, count 2 2006.246.08:07:32.05#ibcon#flushed, iclass 30, count 2 2006.246.08:07:32.05#ibcon#about to write, iclass 30, count 2 2006.246.08:07:32.05#ibcon#wrote, iclass 30, count 2 2006.246.08:07:32.05#ibcon#about to read 3, iclass 30, count 2 2006.246.08:07:32.08#ibcon#read 3, iclass 30, count 2 2006.246.08:07:32.08#ibcon#about to read 4, iclass 30, count 2 2006.246.08:07:32.08#ibcon#read 4, iclass 30, count 2 2006.246.08:07:32.08#ibcon#about to read 5, iclass 30, count 2 2006.246.08:07:32.08#ibcon#read 5, iclass 30, count 2 2006.246.08:07:32.08#ibcon#about to read 6, iclass 30, count 2 2006.246.08:07:32.08#ibcon#read 6, iclass 30, count 2 2006.246.08:07:32.08#ibcon#end of sib2, iclass 30, count 2 2006.246.08:07:32.08#ibcon#*after write, iclass 30, count 2 2006.246.08:07:32.08#ibcon#*before return 0, iclass 30, count 2 2006.246.08:07:32.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:32.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:07:32.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.08:07:32.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:32.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:32.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:32.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:32.20#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:07:32.20#ibcon#first serial, iclass 30, count 0 2006.246.08:07:32.20#ibcon#enter sib2, iclass 30, count 0 2006.246.08:07:32.20#ibcon#flushed, iclass 30, count 0 2006.246.08:07:32.20#ibcon#about to write, iclass 30, count 0 2006.246.08:07:32.20#ibcon#wrote, iclass 30, count 0 2006.246.08:07:32.20#ibcon#about to read 3, iclass 30, count 0 2006.246.08:07:32.22#ibcon#read 3, iclass 30, count 0 2006.246.08:07:32.22#ibcon#about to read 4, iclass 30, count 0 2006.246.08:07:32.22#ibcon#read 4, iclass 30, count 0 2006.246.08:07:32.22#ibcon#about to read 5, iclass 30, count 0 2006.246.08:07:32.22#ibcon#read 5, iclass 30, count 0 2006.246.08:07:32.22#ibcon#about to read 6, iclass 30, count 0 2006.246.08:07:32.22#ibcon#read 6, iclass 30, count 0 2006.246.08:07:32.22#ibcon#end of sib2, iclass 30, count 0 2006.246.08:07:32.22#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:07:32.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:07:32.22#ibcon#[27=USB\r\n] 2006.246.08:07:32.22#ibcon#*before write, iclass 30, count 0 2006.246.08:07:32.22#ibcon#enter sib2, iclass 30, count 0 2006.246.08:07:32.22#ibcon#flushed, iclass 30, count 0 2006.246.08:07:32.22#ibcon#about to write, iclass 30, count 0 2006.246.08:07:32.22#ibcon#wrote, iclass 30, count 0 2006.246.08:07:32.22#ibcon#about to read 3, iclass 30, count 0 2006.246.08:07:32.25#ibcon#read 3, iclass 30, count 0 2006.246.08:07:32.25#ibcon#about to read 4, iclass 30, count 0 2006.246.08:07:32.25#ibcon#read 4, iclass 30, count 0 2006.246.08:07:32.25#ibcon#about to read 5, iclass 30, count 0 2006.246.08:07:32.25#ibcon#read 5, iclass 30, count 0 2006.246.08:07:32.25#ibcon#about to read 6, iclass 30, count 0 2006.246.08:07:32.25#ibcon#read 6, iclass 30, count 0 2006.246.08:07:32.25#ibcon#end of sib2, iclass 30, count 0 2006.246.08:07:32.25#ibcon#*after write, iclass 30, count 0 2006.246.08:07:32.25#ibcon#*before return 0, iclass 30, count 0 2006.246.08:07:32.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:32.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:07:32.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:07:32.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:07:32.25$vc4f8/vblo=6,752.99 2006.246.08:07:32.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:07:32.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:07:32.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:07:32.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:32.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:32.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:32.25#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:07:32.25#ibcon#first serial, iclass 32, count 0 2006.246.08:07:32.25#ibcon#enter sib2, iclass 32, count 0 2006.246.08:07:32.25#ibcon#flushed, iclass 32, count 0 2006.246.08:07:32.25#ibcon#about to write, iclass 32, count 0 2006.246.08:07:32.25#ibcon#wrote, iclass 32, count 0 2006.246.08:07:32.25#ibcon#about to read 3, iclass 32, count 0 2006.246.08:07:32.27#ibcon#read 3, iclass 32, count 0 2006.246.08:07:32.27#ibcon#about to read 4, iclass 32, count 0 2006.246.08:07:32.27#ibcon#read 4, iclass 32, count 0 2006.246.08:07:32.27#ibcon#about to read 5, iclass 32, count 0 2006.246.08:07:32.27#ibcon#read 5, iclass 32, count 0 2006.246.08:07:32.27#ibcon#about to read 6, iclass 32, count 0 2006.246.08:07:32.27#ibcon#read 6, iclass 32, count 0 2006.246.08:07:32.27#ibcon#end of sib2, iclass 32, count 0 2006.246.08:07:32.27#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:07:32.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:07:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:07:32.27#ibcon#*before write, iclass 32, count 0 2006.246.08:07:32.27#ibcon#enter sib2, iclass 32, count 0 2006.246.08:07:32.27#ibcon#flushed, iclass 32, count 0 2006.246.08:07:32.27#ibcon#about to write, iclass 32, count 0 2006.246.08:07:32.27#ibcon#wrote, iclass 32, count 0 2006.246.08:07:32.27#ibcon#about to read 3, iclass 32, count 0 2006.246.08:07:32.31#ibcon#read 3, iclass 32, count 0 2006.246.08:07:32.31#ibcon#about to read 4, iclass 32, count 0 2006.246.08:07:32.31#ibcon#read 4, iclass 32, count 0 2006.246.08:07:32.31#ibcon#about to read 5, iclass 32, count 0 2006.246.08:07:32.31#ibcon#read 5, iclass 32, count 0 2006.246.08:07:32.31#ibcon#about to read 6, iclass 32, count 0 2006.246.08:07:32.31#ibcon#read 6, iclass 32, count 0 2006.246.08:07:32.31#ibcon#end of sib2, iclass 32, count 0 2006.246.08:07:32.31#ibcon#*after write, iclass 32, count 0 2006.246.08:07:32.31#ibcon#*before return 0, iclass 32, count 0 2006.246.08:07:32.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:32.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:07:32.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:07:32.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:07:32.31$vc4f8/vb=6,3 2006.246.08:07:32.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.08:07:32.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.08:07:32.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:07:32.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:32.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:32.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:32.37#ibcon#enter wrdev, iclass 34, count 2 2006.246.08:07:32.37#ibcon#first serial, iclass 34, count 2 2006.246.08:07:32.37#ibcon#enter sib2, iclass 34, count 2 2006.246.08:07:32.37#ibcon#flushed, iclass 34, count 2 2006.246.08:07:32.37#ibcon#about to write, iclass 34, count 2 2006.246.08:07:32.37#ibcon#wrote, iclass 34, count 2 2006.246.08:07:32.37#ibcon#about to read 3, iclass 34, count 2 2006.246.08:07:32.39#ibcon#read 3, iclass 34, count 2 2006.246.08:07:32.39#ibcon#about to read 4, iclass 34, count 2 2006.246.08:07:32.39#ibcon#read 4, iclass 34, count 2 2006.246.08:07:32.39#ibcon#about to read 5, iclass 34, count 2 2006.246.08:07:32.39#ibcon#read 5, iclass 34, count 2 2006.246.08:07:32.39#ibcon#about to read 6, iclass 34, count 2 2006.246.08:07:32.39#ibcon#read 6, iclass 34, count 2 2006.246.08:07:32.39#ibcon#end of sib2, iclass 34, count 2 2006.246.08:07:32.39#ibcon#*mode == 0, iclass 34, count 2 2006.246.08:07:32.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.08:07:32.39#ibcon#[27=AT06-03\r\n] 2006.246.08:07:32.39#ibcon#*before write, iclass 34, count 2 2006.246.08:07:32.39#ibcon#enter sib2, iclass 34, count 2 2006.246.08:07:32.39#ibcon#flushed, iclass 34, count 2 2006.246.08:07:32.39#ibcon#about to write, iclass 34, count 2 2006.246.08:07:32.39#ibcon#wrote, iclass 34, count 2 2006.246.08:07:32.39#ibcon#about to read 3, iclass 34, count 2 2006.246.08:07:32.42#ibcon#read 3, iclass 34, count 2 2006.246.08:07:32.42#ibcon#about to read 4, iclass 34, count 2 2006.246.08:07:32.42#ibcon#read 4, iclass 34, count 2 2006.246.08:07:32.42#ibcon#about to read 5, iclass 34, count 2 2006.246.08:07:32.42#ibcon#read 5, iclass 34, count 2 2006.246.08:07:32.42#ibcon#about to read 6, iclass 34, count 2 2006.246.08:07:32.42#ibcon#read 6, iclass 34, count 2 2006.246.08:07:32.42#ibcon#end of sib2, iclass 34, count 2 2006.246.08:07:32.42#ibcon#*after write, iclass 34, count 2 2006.246.08:07:32.42#ibcon#*before return 0, iclass 34, count 2 2006.246.08:07:32.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:32.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:07:32.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.08:07:32.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:07:32.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:32.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:32.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:32.54#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:07:32.54#ibcon#first serial, iclass 34, count 0 2006.246.08:07:32.54#ibcon#enter sib2, iclass 34, count 0 2006.246.08:07:32.54#ibcon#flushed, iclass 34, count 0 2006.246.08:07:32.54#ibcon#about to write, iclass 34, count 0 2006.246.08:07:32.54#ibcon#wrote, iclass 34, count 0 2006.246.08:07:32.54#ibcon#about to read 3, iclass 34, count 0 2006.246.08:07:32.56#ibcon#read 3, iclass 34, count 0 2006.246.08:07:32.56#ibcon#about to read 4, iclass 34, count 0 2006.246.08:07:32.56#ibcon#read 4, iclass 34, count 0 2006.246.08:07:32.56#ibcon#about to read 5, iclass 34, count 0 2006.246.08:07:32.56#ibcon#read 5, iclass 34, count 0 2006.246.08:07:32.56#ibcon#about to read 6, iclass 34, count 0 2006.246.08:07:32.56#ibcon#read 6, iclass 34, count 0 2006.246.08:07:32.56#ibcon#end of sib2, iclass 34, count 0 2006.246.08:07:32.56#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:07:32.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:07:32.56#ibcon#[27=USB\r\n] 2006.246.08:07:32.56#ibcon#*before write, iclass 34, count 0 2006.246.08:07:32.56#ibcon#enter sib2, iclass 34, count 0 2006.246.08:07:32.56#ibcon#flushed, iclass 34, count 0 2006.246.08:07:32.56#ibcon#about to write, iclass 34, count 0 2006.246.08:07:32.56#ibcon#wrote, iclass 34, count 0 2006.246.08:07:32.56#ibcon#about to read 3, iclass 34, count 0 2006.246.08:07:32.59#ibcon#read 3, iclass 34, count 0 2006.246.08:07:32.59#ibcon#about to read 4, iclass 34, count 0 2006.246.08:07:32.59#ibcon#read 4, iclass 34, count 0 2006.246.08:07:32.59#ibcon#about to read 5, iclass 34, count 0 2006.246.08:07:32.59#ibcon#read 5, iclass 34, count 0 2006.246.08:07:32.59#ibcon#about to read 6, iclass 34, count 0 2006.246.08:07:32.59#ibcon#read 6, iclass 34, count 0 2006.246.08:07:32.59#ibcon#end of sib2, iclass 34, count 0 2006.246.08:07:32.59#ibcon#*after write, iclass 34, count 0 2006.246.08:07:32.59#ibcon#*before return 0, iclass 34, count 0 2006.246.08:07:32.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:32.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:07:32.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:07:32.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:07:32.59$vc4f8/vabw=wide 2006.246.08:07:32.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.08:07:32.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.08:07:32.59#ibcon#ireg 8 cls_cnt 0 2006.246.08:07:32.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:32.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:32.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:32.59#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:07:32.59#ibcon#first serial, iclass 36, count 0 2006.246.08:07:32.59#ibcon#enter sib2, iclass 36, count 0 2006.246.08:07:32.59#ibcon#flushed, iclass 36, count 0 2006.246.08:07:32.59#ibcon#about to write, iclass 36, count 0 2006.246.08:07:32.59#ibcon#wrote, iclass 36, count 0 2006.246.08:07:32.59#ibcon#about to read 3, iclass 36, count 0 2006.246.08:07:32.61#ibcon#read 3, iclass 36, count 0 2006.246.08:07:32.61#ibcon#about to read 4, iclass 36, count 0 2006.246.08:07:32.61#ibcon#read 4, iclass 36, count 0 2006.246.08:07:32.61#ibcon#about to read 5, iclass 36, count 0 2006.246.08:07:32.61#ibcon#read 5, iclass 36, count 0 2006.246.08:07:32.61#ibcon#about to read 6, iclass 36, count 0 2006.246.08:07:32.61#ibcon#read 6, iclass 36, count 0 2006.246.08:07:32.61#ibcon#end of sib2, iclass 36, count 0 2006.246.08:07:32.61#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:07:32.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:07:32.61#ibcon#[25=BW32\r\n] 2006.246.08:07:32.61#ibcon#*before write, iclass 36, count 0 2006.246.08:07:32.61#ibcon#enter sib2, iclass 36, count 0 2006.246.08:07:32.61#ibcon#flushed, iclass 36, count 0 2006.246.08:07:32.61#ibcon#about to write, iclass 36, count 0 2006.246.08:07:32.61#ibcon#wrote, iclass 36, count 0 2006.246.08:07:32.61#ibcon#about to read 3, iclass 36, count 0 2006.246.08:07:32.64#ibcon#read 3, iclass 36, count 0 2006.246.08:07:32.64#ibcon#about to read 4, iclass 36, count 0 2006.246.08:07:32.64#ibcon#read 4, iclass 36, count 0 2006.246.08:07:32.64#ibcon#about to read 5, iclass 36, count 0 2006.246.08:07:32.64#ibcon#read 5, iclass 36, count 0 2006.246.08:07:32.64#ibcon#about to read 6, iclass 36, count 0 2006.246.08:07:32.64#ibcon#read 6, iclass 36, count 0 2006.246.08:07:32.64#ibcon#end of sib2, iclass 36, count 0 2006.246.08:07:32.64#ibcon#*after write, iclass 36, count 0 2006.246.08:07:32.64#ibcon#*before return 0, iclass 36, count 0 2006.246.08:07:32.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:32.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:07:32.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:07:32.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:07:32.64$vc4f8/vbbw=wide 2006.246.08:07:32.64#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.08:07:32.64#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.08:07:32.64#ibcon#ireg 8 cls_cnt 0 2006.246.08:07:32.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:07:32.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:07:32.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:07:32.71#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:07:32.71#ibcon#first serial, iclass 38, count 0 2006.246.08:07:32.71#ibcon#enter sib2, iclass 38, count 0 2006.246.08:07:32.71#ibcon#flushed, iclass 38, count 0 2006.246.08:07:32.71#ibcon#about to write, iclass 38, count 0 2006.246.08:07:32.71#ibcon#wrote, iclass 38, count 0 2006.246.08:07:32.71#ibcon#about to read 3, iclass 38, count 0 2006.246.08:07:32.73#ibcon#read 3, iclass 38, count 0 2006.246.08:07:32.73#ibcon#about to read 4, iclass 38, count 0 2006.246.08:07:32.73#ibcon#read 4, iclass 38, count 0 2006.246.08:07:32.73#ibcon#about to read 5, iclass 38, count 0 2006.246.08:07:32.73#ibcon#read 5, iclass 38, count 0 2006.246.08:07:32.73#ibcon#about to read 6, iclass 38, count 0 2006.246.08:07:32.73#ibcon#read 6, iclass 38, count 0 2006.246.08:07:32.73#ibcon#end of sib2, iclass 38, count 0 2006.246.08:07:32.73#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:07:32.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:07:32.73#ibcon#[27=BW32\r\n] 2006.246.08:07:32.73#ibcon#*before write, iclass 38, count 0 2006.246.08:07:32.73#ibcon#enter sib2, iclass 38, count 0 2006.246.08:07:32.73#ibcon#flushed, iclass 38, count 0 2006.246.08:07:32.73#ibcon#about to write, iclass 38, count 0 2006.246.08:07:32.73#ibcon#wrote, iclass 38, count 0 2006.246.08:07:32.73#ibcon#about to read 3, iclass 38, count 0 2006.246.08:07:32.76#ibcon#read 3, iclass 38, count 0 2006.246.08:07:32.76#ibcon#about to read 4, iclass 38, count 0 2006.246.08:07:32.76#ibcon#read 4, iclass 38, count 0 2006.246.08:07:32.76#ibcon#about to read 5, iclass 38, count 0 2006.246.08:07:32.76#ibcon#read 5, iclass 38, count 0 2006.246.08:07:32.76#ibcon#about to read 6, iclass 38, count 0 2006.246.08:07:32.76#ibcon#read 6, iclass 38, count 0 2006.246.08:07:32.76#ibcon#end of sib2, iclass 38, count 0 2006.246.08:07:32.76#ibcon#*after write, iclass 38, count 0 2006.246.08:07:32.76#ibcon#*before return 0, iclass 38, count 0 2006.246.08:07:32.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:07:32.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:07:32.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:07:32.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:07:32.76$4f8m12a/ifd4f 2006.246.08:07:32.76$ifd4f/lo= 2006.246.08:07:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:07:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:07:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:07:32.76$ifd4f/patch= 2006.246.08:07:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:07:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:07:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:07:32.76$4f8m12a/"form=m,16.000,1:2 2006.246.08:07:32.76$4f8m12a/"tpicd 2006.246.08:07:32.76$4f8m12a/echo=off 2006.246.08:07:32.76$4f8m12a/xlog=off 2006.246.08:07:32.76:!2006.246.08:08:00 2006.246.08:07:43.14#trakl#Source acquired 2006.246.08:07:45.14#flagr#flagr/antenna,acquired 2006.246.08:08:00.00:preob 2006.246.08:08:01.14/onsource/TRACKING 2006.246.08:08:01.14:!2006.246.08:08:10 2006.246.08:08:10.00:data_valid=on 2006.246.08:08:10.00:midob 2006.246.08:08:10.14/onsource/TRACKING 2006.246.08:08:10.14/wx/26.48,1005.7,75 2006.246.08:08:10.33/cable/+6.4139E-03 2006.246.08:08:11.42/va/01,08,usb,yes,31,32 2006.246.08:08:11.42/va/02,07,usb,yes,31,32 2006.246.08:08:11.42/va/03,06,usb,yes,33,33 2006.246.08:08:11.42/va/04,07,usb,yes,32,34 2006.246.08:08:11.42/va/05,07,usb,yes,34,35 2006.246.08:08:11.42/va/06,07,usb,yes,29,29 2006.246.08:08:11.42/va/07,07,usb,yes,29,29 2006.246.08:08:11.42/va/08,08,usb,yes,25,25 2006.246.08:08:11.65/valo/01,532.99,yes,locked 2006.246.08:08:11.65/valo/02,572.99,yes,locked 2006.246.08:08:11.65/valo/03,672.99,yes,locked 2006.246.08:08:11.65/valo/04,832.99,yes,locked 2006.246.08:08:11.65/valo/05,652.99,yes,locked 2006.246.08:08:11.65/valo/06,772.99,yes,locked 2006.246.08:08:11.65/valo/07,832.99,yes,locked 2006.246.08:08:11.65/valo/08,852.99,yes,locked 2006.246.08:08:12.74/vb/01,04,usb,yes,30,29 2006.246.08:08:12.74/vb/02,04,usb,yes,32,34 2006.246.08:08:12.74/vb/03,04,usb,yes,28,32 2006.246.08:08:12.74/vb/04,04,usb,yes,29,29 2006.246.08:08:12.74/vb/05,03,usb,yes,35,39 2006.246.08:08:12.74/vb/06,03,usb,yes,35,39 2006.246.08:08:12.74/vb/07,04,usb,yes,31,31 2006.246.08:08:12.74/vb/08,03,usb,yes,35,39 2006.246.08:08:12.97/vblo/01,632.99,yes,locked 2006.246.08:08:12.97/vblo/02,640.99,yes,locked 2006.246.08:08:12.97/vblo/03,656.99,yes,locked 2006.246.08:08:12.97/vblo/04,712.99,yes,locked 2006.246.08:08:12.97/vblo/05,744.99,yes,locked 2006.246.08:08:12.97/vblo/06,752.99,yes,locked 2006.246.08:08:12.97/vblo/07,734.99,yes,locked 2006.246.08:08:12.97/vblo/08,744.99,yes,locked 2006.246.08:08:13.12/vabw/8 2006.246.08:08:13.27/vbbw/8 2006.246.08:08:13.36/xfe/off,on,13.2 2006.246.08:08:13.74/ifatt/23,28,28,28 2006.246.08:08:14.08/fmout-gps/S +4.39E-07 2006.246.08:08:14.12:!2006.246.08:09:10 2006.246.08:09:10.00:data_valid=off 2006.246.08:09:10.00:postob 2006.246.08:09:10.11/cable/+6.4139E-03 2006.246.08:09:10.11/wx/26.46,1005.6,75 2006.246.08:09:11.08/fmout-gps/S +4.38E-07 2006.246.08:09:11.08:scan_name=246-0810,k06246,60 2006.246.08:09:11.08:source=nrao512,164029.63,394646.0,2000.0,cw 2006.246.08:09:11.16#flagr#flagr/antenna,new-source 2006.246.08:09:12.14:checkk5 2006.246.08:09:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:09:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:09:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:09:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:09:14.01/chk_obsdata//k5ts1/T2460808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:09:14.38/chk_obsdata//k5ts2/T2460808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:09:14.75/chk_obsdata//k5ts3/T2460808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:09:15.12/chk_obsdata//k5ts4/T2460808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:09:15.82/k5log//k5ts1_log_newline 2006.246.08:09:16.51/k5log//k5ts2_log_newline 2006.246.08:09:17.20/k5log//k5ts3_log_newline 2006.246.08:09:17.89/k5log//k5ts4_log_newline 2006.246.08:09:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:09:17.91:4f8m12a=2 2006.246.08:09:17.91$4f8m12a/echo=on 2006.246.08:09:17.91$4f8m12a/pcalon 2006.246.08:09:17.91$pcalon/"no phase cal control is implemented here 2006.246.08:09:17.91$4f8m12a/"tpicd=stop 2006.246.08:09:17.91$4f8m12a/vc4f8 2006.246.08:09:17.91$vc4f8/valo=1,532.99 2006.246.08:09:17.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:09:17.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:09:17.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:17.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:17.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:17.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:17.91#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:09:17.91#ibcon#first serial, iclass 13, count 0 2006.246.08:09:17.91#ibcon#enter sib2, iclass 13, count 0 2006.246.08:09:17.91#ibcon#flushed, iclass 13, count 0 2006.246.08:09:17.91#ibcon#about to write, iclass 13, count 0 2006.246.08:09:17.91#ibcon#wrote, iclass 13, count 0 2006.246.08:09:17.91#ibcon#about to read 3, iclass 13, count 0 2006.246.08:09:17.95#ibcon#read 3, iclass 13, count 0 2006.246.08:09:17.95#ibcon#about to read 4, iclass 13, count 0 2006.246.08:09:17.95#ibcon#read 4, iclass 13, count 0 2006.246.08:09:17.95#ibcon#about to read 5, iclass 13, count 0 2006.246.08:09:17.95#ibcon#read 5, iclass 13, count 0 2006.246.08:09:17.95#ibcon#about to read 6, iclass 13, count 0 2006.246.08:09:17.95#ibcon#read 6, iclass 13, count 0 2006.246.08:09:17.95#ibcon#end of sib2, iclass 13, count 0 2006.246.08:09:17.95#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:09:17.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:09:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:09:17.95#ibcon#*before write, iclass 13, count 0 2006.246.08:09:17.95#ibcon#enter sib2, iclass 13, count 0 2006.246.08:09:17.95#ibcon#flushed, iclass 13, count 0 2006.246.08:09:17.95#ibcon#about to write, iclass 13, count 0 2006.246.08:09:17.95#ibcon#wrote, iclass 13, count 0 2006.246.08:09:17.95#ibcon#about to read 3, iclass 13, count 0 2006.246.08:09:18.00#ibcon#read 3, iclass 13, count 0 2006.246.08:09:18.00#ibcon#about to read 4, iclass 13, count 0 2006.246.08:09:18.00#ibcon#read 4, iclass 13, count 0 2006.246.08:09:18.00#ibcon#about to read 5, iclass 13, count 0 2006.246.08:09:18.00#ibcon#read 5, iclass 13, count 0 2006.246.08:09:18.00#ibcon#about to read 6, iclass 13, count 0 2006.246.08:09:18.00#ibcon#read 6, iclass 13, count 0 2006.246.08:09:18.00#ibcon#end of sib2, iclass 13, count 0 2006.246.08:09:18.00#ibcon#*after write, iclass 13, count 0 2006.246.08:09:18.00#ibcon#*before return 0, iclass 13, count 0 2006.246.08:09:18.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:18.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:18.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:09:18.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:09:18.00$vc4f8/va=1,8 2006.246.08:09:18.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.08:09:18.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.08:09:18.00#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:18.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:18.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:18.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:18.00#ibcon#enter wrdev, iclass 15, count 2 2006.246.08:09:18.00#ibcon#first serial, iclass 15, count 2 2006.246.08:09:18.00#ibcon#enter sib2, iclass 15, count 2 2006.246.08:09:18.00#ibcon#flushed, iclass 15, count 2 2006.246.08:09:18.00#ibcon#about to write, iclass 15, count 2 2006.246.08:09:18.00#ibcon#wrote, iclass 15, count 2 2006.246.08:09:18.00#ibcon#about to read 3, iclass 15, count 2 2006.246.08:09:18.02#ibcon#read 3, iclass 15, count 2 2006.246.08:09:18.02#ibcon#about to read 4, iclass 15, count 2 2006.246.08:09:18.02#ibcon#read 4, iclass 15, count 2 2006.246.08:09:18.02#ibcon#about to read 5, iclass 15, count 2 2006.246.08:09:18.02#ibcon#read 5, iclass 15, count 2 2006.246.08:09:18.02#ibcon#about to read 6, iclass 15, count 2 2006.246.08:09:18.02#ibcon#read 6, iclass 15, count 2 2006.246.08:09:18.02#ibcon#end of sib2, iclass 15, count 2 2006.246.08:09:18.02#ibcon#*mode == 0, iclass 15, count 2 2006.246.08:09:18.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.08:09:18.02#ibcon#[25=AT01-08\r\n] 2006.246.08:09:18.02#ibcon#*before write, iclass 15, count 2 2006.246.08:09:18.02#ibcon#enter sib2, iclass 15, count 2 2006.246.08:09:18.02#ibcon#flushed, iclass 15, count 2 2006.246.08:09:18.02#ibcon#about to write, iclass 15, count 2 2006.246.08:09:18.02#ibcon#wrote, iclass 15, count 2 2006.246.08:09:18.02#ibcon#about to read 3, iclass 15, count 2 2006.246.08:09:18.05#ibcon#read 3, iclass 15, count 2 2006.246.08:09:18.05#ibcon#about to read 4, iclass 15, count 2 2006.246.08:09:18.05#ibcon#read 4, iclass 15, count 2 2006.246.08:09:18.05#ibcon#about to read 5, iclass 15, count 2 2006.246.08:09:18.05#ibcon#read 5, iclass 15, count 2 2006.246.08:09:18.05#ibcon#about to read 6, iclass 15, count 2 2006.246.08:09:18.05#ibcon#read 6, iclass 15, count 2 2006.246.08:09:18.05#ibcon#end of sib2, iclass 15, count 2 2006.246.08:09:18.05#ibcon#*after write, iclass 15, count 2 2006.246.08:09:18.05#ibcon#*before return 0, iclass 15, count 2 2006.246.08:09:18.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:18.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:18.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.08:09:18.05#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:18.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:18.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:18.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:18.17#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:09:18.17#ibcon#first serial, iclass 15, count 0 2006.246.08:09:18.17#ibcon#enter sib2, iclass 15, count 0 2006.246.08:09:18.17#ibcon#flushed, iclass 15, count 0 2006.246.08:09:18.17#ibcon#about to write, iclass 15, count 0 2006.246.08:09:18.17#ibcon#wrote, iclass 15, count 0 2006.246.08:09:18.17#ibcon#about to read 3, iclass 15, count 0 2006.246.08:09:18.19#ibcon#read 3, iclass 15, count 0 2006.246.08:09:18.19#ibcon#about to read 4, iclass 15, count 0 2006.246.08:09:18.19#ibcon#read 4, iclass 15, count 0 2006.246.08:09:18.19#ibcon#about to read 5, iclass 15, count 0 2006.246.08:09:18.19#ibcon#read 5, iclass 15, count 0 2006.246.08:09:18.19#ibcon#about to read 6, iclass 15, count 0 2006.246.08:09:18.19#ibcon#read 6, iclass 15, count 0 2006.246.08:09:18.19#ibcon#end of sib2, iclass 15, count 0 2006.246.08:09:18.19#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:09:18.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:09:18.19#ibcon#[25=USB\r\n] 2006.246.08:09:18.19#ibcon#*before write, iclass 15, count 0 2006.246.08:09:18.19#ibcon#enter sib2, iclass 15, count 0 2006.246.08:09:18.19#ibcon#flushed, iclass 15, count 0 2006.246.08:09:18.19#ibcon#about to write, iclass 15, count 0 2006.246.08:09:18.19#ibcon#wrote, iclass 15, count 0 2006.246.08:09:18.19#ibcon#about to read 3, iclass 15, count 0 2006.246.08:09:18.22#ibcon#read 3, iclass 15, count 0 2006.246.08:09:18.22#ibcon#about to read 4, iclass 15, count 0 2006.246.08:09:18.22#ibcon#read 4, iclass 15, count 0 2006.246.08:09:18.22#ibcon#about to read 5, iclass 15, count 0 2006.246.08:09:18.22#ibcon#read 5, iclass 15, count 0 2006.246.08:09:18.22#ibcon#about to read 6, iclass 15, count 0 2006.246.08:09:18.22#ibcon#read 6, iclass 15, count 0 2006.246.08:09:18.22#ibcon#end of sib2, iclass 15, count 0 2006.246.08:09:18.22#ibcon#*after write, iclass 15, count 0 2006.246.08:09:18.22#ibcon#*before return 0, iclass 15, count 0 2006.246.08:09:18.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:18.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:18.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:09:18.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:09:18.22$vc4f8/valo=2,572.99 2006.246.08:09:18.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.08:09:18.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.08:09:18.22#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:18.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:18.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:18.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:18.22#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:09:18.22#ibcon#first serial, iclass 17, count 0 2006.246.08:09:18.22#ibcon#enter sib2, iclass 17, count 0 2006.246.08:09:18.22#ibcon#flushed, iclass 17, count 0 2006.246.08:09:18.22#ibcon#about to write, iclass 17, count 0 2006.246.08:09:18.22#ibcon#wrote, iclass 17, count 0 2006.246.08:09:18.22#ibcon#about to read 3, iclass 17, count 0 2006.246.08:09:18.24#ibcon#read 3, iclass 17, count 0 2006.246.08:09:18.24#ibcon#about to read 4, iclass 17, count 0 2006.246.08:09:18.24#ibcon#read 4, iclass 17, count 0 2006.246.08:09:18.24#ibcon#about to read 5, iclass 17, count 0 2006.246.08:09:18.24#ibcon#read 5, iclass 17, count 0 2006.246.08:09:18.24#ibcon#about to read 6, iclass 17, count 0 2006.246.08:09:18.24#ibcon#read 6, iclass 17, count 0 2006.246.08:09:18.24#ibcon#end of sib2, iclass 17, count 0 2006.246.08:09:18.24#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:09:18.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:09:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:09:18.24#ibcon#*before write, iclass 17, count 0 2006.246.08:09:18.24#ibcon#enter sib2, iclass 17, count 0 2006.246.08:09:18.24#ibcon#flushed, iclass 17, count 0 2006.246.08:09:18.24#ibcon#about to write, iclass 17, count 0 2006.246.08:09:18.24#ibcon#wrote, iclass 17, count 0 2006.246.08:09:18.24#ibcon#about to read 3, iclass 17, count 0 2006.246.08:09:18.28#ibcon#read 3, iclass 17, count 0 2006.246.08:09:18.28#ibcon#about to read 4, iclass 17, count 0 2006.246.08:09:18.28#ibcon#read 4, iclass 17, count 0 2006.246.08:09:18.28#ibcon#about to read 5, iclass 17, count 0 2006.246.08:09:18.28#ibcon#read 5, iclass 17, count 0 2006.246.08:09:18.28#ibcon#about to read 6, iclass 17, count 0 2006.246.08:09:18.28#ibcon#read 6, iclass 17, count 0 2006.246.08:09:18.28#ibcon#end of sib2, iclass 17, count 0 2006.246.08:09:18.28#ibcon#*after write, iclass 17, count 0 2006.246.08:09:18.28#ibcon#*before return 0, iclass 17, count 0 2006.246.08:09:18.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:18.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:18.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:09:18.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:09:18.28$vc4f8/va=2,7 2006.246.08:09:18.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.08:09:18.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.08:09:18.28#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:18.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:18.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:18.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:18.34#ibcon#enter wrdev, iclass 19, count 2 2006.246.08:09:18.34#ibcon#first serial, iclass 19, count 2 2006.246.08:09:18.34#ibcon#enter sib2, iclass 19, count 2 2006.246.08:09:18.34#ibcon#flushed, iclass 19, count 2 2006.246.08:09:18.34#ibcon#about to write, iclass 19, count 2 2006.246.08:09:18.34#ibcon#wrote, iclass 19, count 2 2006.246.08:09:18.34#ibcon#about to read 3, iclass 19, count 2 2006.246.08:09:18.36#ibcon#read 3, iclass 19, count 2 2006.246.08:09:18.36#ibcon#about to read 4, iclass 19, count 2 2006.246.08:09:18.36#ibcon#read 4, iclass 19, count 2 2006.246.08:09:18.36#ibcon#about to read 5, iclass 19, count 2 2006.246.08:09:18.36#ibcon#read 5, iclass 19, count 2 2006.246.08:09:18.36#ibcon#about to read 6, iclass 19, count 2 2006.246.08:09:18.36#ibcon#read 6, iclass 19, count 2 2006.246.08:09:18.36#ibcon#end of sib2, iclass 19, count 2 2006.246.08:09:18.36#ibcon#*mode == 0, iclass 19, count 2 2006.246.08:09:18.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.08:09:18.36#ibcon#[25=AT02-07\r\n] 2006.246.08:09:18.36#ibcon#*before write, iclass 19, count 2 2006.246.08:09:18.36#ibcon#enter sib2, iclass 19, count 2 2006.246.08:09:18.36#ibcon#flushed, iclass 19, count 2 2006.246.08:09:18.36#ibcon#about to write, iclass 19, count 2 2006.246.08:09:18.36#ibcon#wrote, iclass 19, count 2 2006.246.08:09:18.36#ibcon#about to read 3, iclass 19, count 2 2006.246.08:09:18.39#ibcon#read 3, iclass 19, count 2 2006.246.08:09:18.39#ibcon#about to read 4, iclass 19, count 2 2006.246.08:09:18.39#ibcon#read 4, iclass 19, count 2 2006.246.08:09:18.39#ibcon#about to read 5, iclass 19, count 2 2006.246.08:09:18.39#ibcon#read 5, iclass 19, count 2 2006.246.08:09:18.39#ibcon#about to read 6, iclass 19, count 2 2006.246.08:09:18.39#ibcon#read 6, iclass 19, count 2 2006.246.08:09:18.39#ibcon#end of sib2, iclass 19, count 2 2006.246.08:09:18.39#ibcon#*after write, iclass 19, count 2 2006.246.08:09:18.39#ibcon#*before return 0, iclass 19, count 2 2006.246.08:09:18.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:18.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:18.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.08:09:18.39#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:18.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:18.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:18.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:18.51#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:09:18.51#ibcon#first serial, iclass 19, count 0 2006.246.08:09:18.51#ibcon#enter sib2, iclass 19, count 0 2006.246.08:09:18.51#ibcon#flushed, iclass 19, count 0 2006.246.08:09:18.51#ibcon#about to write, iclass 19, count 0 2006.246.08:09:18.51#ibcon#wrote, iclass 19, count 0 2006.246.08:09:18.51#ibcon#about to read 3, iclass 19, count 0 2006.246.08:09:18.53#ibcon#read 3, iclass 19, count 0 2006.246.08:09:18.53#ibcon#about to read 4, iclass 19, count 0 2006.246.08:09:18.53#ibcon#read 4, iclass 19, count 0 2006.246.08:09:18.53#ibcon#about to read 5, iclass 19, count 0 2006.246.08:09:18.53#ibcon#read 5, iclass 19, count 0 2006.246.08:09:18.53#ibcon#about to read 6, iclass 19, count 0 2006.246.08:09:18.53#ibcon#read 6, iclass 19, count 0 2006.246.08:09:18.53#ibcon#end of sib2, iclass 19, count 0 2006.246.08:09:18.53#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:09:18.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:09:18.53#ibcon#[25=USB\r\n] 2006.246.08:09:18.53#ibcon#*before write, iclass 19, count 0 2006.246.08:09:18.53#ibcon#enter sib2, iclass 19, count 0 2006.246.08:09:18.53#ibcon#flushed, iclass 19, count 0 2006.246.08:09:18.53#ibcon#about to write, iclass 19, count 0 2006.246.08:09:18.53#ibcon#wrote, iclass 19, count 0 2006.246.08:09:18.53#ibcon#about to read 3, iclass 19, count 0 2006.246.08:09:18.56#ibcon#read 3, iclass 19, count 0 2006.246.08:09:18.56#ibcon#about to read 4, iclass 19, count 0 2006.246.08:09:18.56#ibcon#read 4, iclass 19, count 0 2006.246.08:09:18.56#ibcon#about to read 5, iclass 19, count 0 2006.246.08:09:18.56#ibcon#read 5, iclass 19, count 0 2006.246.08:09:18.56#ibcon#about to read 6, iclass 19, count 0 2006.246.08:09:18.56#ibcon#read 6, iclass 19, count 0 2006.246.08:09:18.56#ibcon#end of sib2, iclass 19, count 0 2006.246.08:09:18.56#ibcon#*after write, iclass 19, count 0 2006.246.08:09:18.56#ibcon#*before return 0, iclass 19, count 0 2006.246.08:09:18.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:18.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:18.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:09:18.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:09:18.56$vc4f8/valo=3,672.99 2006.246.08:09:18.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.08:09:18.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.08:09:18.56#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:18.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:18.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:18.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:18.56#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:09:18.56#ibcon#first serial, iclass 21, count 0 2006.246.08:09:18.56#ibcon#enter sib2, iclass 21, count 0 2006.246.08:09:18.56#ibcon#flushed, iclass 21, count 0 2006.246.08:09:18.56#ibcon#about to write, iclass 21, count 0 2006.246.08:09:18.56#ibcon#wrote, iclass 21, count 0 2006.246.08:09:18.56#ibcon#about to read 3, iclass 21, count 0 2006.246.08:09:18.58#ibcon#read 3, iclass 21, count 0 2006.246.08:09:18.58#ibcon#about to read 4, iclass 21, count 0 2006.246.08:09:18.58#ibcon#read 4, iclass 21, count 0 2006.246.08:09:18.58#ibcon#about to read 5, iclass 21, count 0 2006.246.08:09:18.58#ibcon#read 5, iclass 21, count 0 2006.246.08:09:18.58#ibcon#about to read 6, iclass 21, count 0 2006.246.08:09:18.58#ibcon#read 6, iclass 21, count 0 2006.246.08:09:18.58#ibcon#end of sib2, iclass 21, count 0 2006.246.08:09:18.58#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:09:18.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:09:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:09:18.58#ibcon#*before write, iclass 21, count 0 2006.246.08:09:18.58#ibcon#enter sib2, iclass 21, count 0 2006.246.08:09:18.58#ibcon#flushed, iclass 21, count 0 2006.246.08:09:18.58#ibcon#about to write, iclass 21, count 0 2006.246.08:09:18.58#ibcon#wrote, iclass 21, count 0 2006.246.08:09:18.58#ibcon#about to read 3, iclass 21, count 0 2006.246.08:09:18.62#ibcon#read 3, iclass 21, count 0 2006.246.08:09:18.62#ibcon#about to read 4, iclass 21, count 0 2006.246.08:09:18.62#ibcon#read 4, iclass 21, count 0 2006.246.08:09:18.62#ibcon#about to read 5, iclass 21, count 0 2006.246.08:09:18.62#ibcon#read 5, iclass 21, count 0 2006.246.08:09:18.62#ibcon#about to read 6, iclass 21, count 0 2006.246.08:09:18.62#ibcon#read 6, iclass 21, count 0 2006.246.08:09:18.62#ibcon#end of sib2, iclass 21, count 0 2006.246.08:09:18.62#ibcon#*after write, iclass 21, count 0 2006.246.08:09:18.62#ibcon#*before return 0, iclass 21, count 0 2006.246.08:09:18.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:18.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:18.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:09:18.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:09:18.62$vc4f8/va=3,6 2006.246.08:09:18.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.08:09:18.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.08:09:18.62#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:18.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:18.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:18.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:18.68#ibcon#enter wrdev, iclass 23, count 2 2006.246.08:09:18.68#ibcon#first serial, iclass 23, count 2 2006.246.08:09:18.68#ibcon#enter sib2, iclass 23, count 2 2006.246.08:09:18.68#ibcon#flushed, iclass 23, count 2 2006.246.08:09:18.68#ibcon#about to write, iclass 23, count 2 2006.246.08:09:18.68#ibcon#wrote, iclass 23, count 2 2006.246.08:09:18.68#ibcon#about to read 3, iclass 23, count 2 2006.246.08:09:18.70#ibcon#read 3, iclass 23, count 2 2006.246.08:09:18.70#ibcon#about to read 4, iclass 23, count 2 2006.246.08:09:18.70#ibcon#read 4, iclass 23, count 2 2006.246.08:09:18.70#ibcon#about to read 5, iclass 23, count 2 2006.246.08:09:18.70#ibcon#read 5, iclass 23, count 2 2006.246.08:09:18.70#ibcon#about to read 6, iclass 23, count 2 2006.246.08:09:18.70#ibcon#read 6, iclass 23, count 2 2006.246.08:09:18.70#ibcon#end of sib2, iclass 23, count 2 2006.246.08:09:18.70#ibcon#*mode == 0, iclass 23, count 2 2006.246.08:09:18.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.08:09:18.70#ibcon#[25=AT03-06\r\n] 2006.246.08:09:18.70#ibcon#*before write, iclass 23, count 2 2006.246.08:09:18.70#ibcon#enter sib2, iclass 23, count 2 2006.246.08:09:18.70#ibcon#flushed, iclass 23, count 2 2006.246.08:09:18.70#ibcon#about to write, iclass 23, count 2 2006.246.08:09:18.70#ibcon#wrote, iclass 23, count 2 2006.246.08:09:18.70#ibcon#about to read 3, iclass 23, count 2 2006.246.08:09:18.74#ibcon#read 3, iclass 23, count 2 2006.246.08:09:18.74#ibcon#about to read 4, iclass 23, count 2 2006.246.08:09:18.74#ibcon#read 4, iclass 23, count 2 2006.246.08:09:18.74#ibcon#about to read 5, iclass 23, count 2 2006.246.08:09:18.74#ibcon#read 5, iclass 23, count 2 2006.246.08:09:18.74#ibcon#about to read 6, iclass 23, count 2 2006.246.08:09:18.74#ibcon#read 6, iclass 23, count 2 2006.246.08:09:18.74#ibcon#end of sib2, iclass 23, count 2 2006.246.08:09:18.74#ibcon#*after write, iclass 23, count 2 2006.246.08:09:18.74#ibcon#*before return 0, iclass 23, count 2 2006.246.08:09:18.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:18.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:18.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.08:09:18.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:18.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:18.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:18.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:18.86#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:09:18.86#ibcon#first serial, iclass 23, count 0 2006.246.08:09:18.86#ibcon#enter sib2, iclass 23, count 0 2006.246.08:09:18.86#ibcon#flushed, iclass 23, count 0 2006.246.08:09:18.86#ibcon#about to write, iclass 23, count 0 2006.246.08:09:18.86#ibcon#wrote, iclass 23, count 0 2006.246.08:09:18.86#ibcon#about to read 3, iclass 23, count 0 2006.246.08:09:18.88#ibcon#read 3, iclass 23, count 0 2006.246.08:09:18.88#ibcon#about to read 4, iclass 23, count 0 2006.246.08:09:18.88#ibcon#read 4, iclass 23, count 0 2006.246.08:09:18.88#ibcon#about to read 5, iclass 23, count 0 2006.246.08:09:18.88#ibcon#read 5, iclass 23, count 0 2006.246.08:09:18.88#ibcon#about to read 6, iclass 23, count 0 2006.246.08:09:18.88#ibcon#read 6, iclass 23, count 0 2006.246.08:09:18.88#ibcon#end of sib2, iclass 23, count 0 2006.246.08:09:18.88#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:09:18.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:09:18.88#ibcon#[25=USB\r\n] 2006.246.08:09:18.88#ibcon#*before write, iclass 23, count 0 2006.246.08:09:18.88#ibcon#enter sib2, iclass 23, count 0 2006.246.08:09:18.88#ibcon#flushed, iclass 23, count 0 2006.246.08:09:18.88#ibcon#about to write, iclass 23, count 0 2006.246.08:09:18.88#ibcon#wrote, iclass 23, count 0 2006.246.08:09:18.88#ibcon#about to read 3, iclass 23, count 0 2006.246.08:09:18.91#ibcon#read 3, iclass 23, count 0 2006.246.08:09:18.91#ibcon#about to read 4, iclass 23, count 0 2006.246.08:09:18.91#ibcon#read 4, iclass 23, count 0 2006.246.08:09:18.91#ibcon#about to read 5, iclass 23, count 0 2006.246.08:09:18.91#ibcon#read 5, iclass 23, count 0 2006.246.08:09:18.91#ibcon#about to read 6, iclass 23, count 0 2006.246.08:09:18.91#ibcon#read 6, iclass 23, count 0 2006.246.08:09:18.91#ibcon#end of sib2, iclass 23, count 0 2006.246.08:09:18.91#ibcon#*after write, iclass 23, count 0 2006.246.08:09:18.91#ibcon#*before return 0, iclass 23, count 0 2006.246.08:09:18.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:18.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:18.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:09:18.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:09:18.91$vc4f8/valo=4,832.99 2006.246.08:09:18.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.08:09:18.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.08:09:18.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:18.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:18.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:18.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:18.91#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:09:18.91#ibcon#first serial, iclass 25, count 0 2006.246.08:09:18.91#ibcon#enter sib2, iclass 25, count 0 2006.246.08:09:18.91#ibcon#flushed, iclass 25, count 0 2006.246.08:09:18.91#ibcon#about to write, iclass 25, count 0 2006.246.08:09:18.91#ibcon#wrote, iclass 25, count 0 2006.246.08:09:18.91#ibcon#about to read 3, iclass 25, count 0 2006.246.08:09:18.93#ibcon#read 3, iclass 25, count 0 2006.246.08:09:18.93#ibcon#about to read 4, iclass 25, count 0 2006.246.08:09:18.93#ibcon#read 4, iclass 25, count 0 2006.246.08:09:18.93#ibcon#about to read 5, iclass 25, count 0 2006.246.08:09:18.93#ibcon#read 5, iclass 25, count 0 2006.246.08:09:18.93#ibcon#about to read 6, iclass 25, count 0 2006.246.08:09:18.93#ibcon#read 6, iclass 25, count 0 2006.246.08:09:18.93#ibcon#end of sib2, iclass 25, count 0 2006.246.08:09:18.93#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:09:18.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:09:18.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:09:18.93#ibcon#*before write, iclass 25, count 0 2006.246.08:09:18.93#ibcon#enter sib2, iclass 25, count 0 2006.246.08:09:18.93#ibcon#flushed, iclass 25, count 0 2006.246.08:09:18.93#ibcon#about to write, iclass 25, count 0 2006.246.08:09:18.93#ibcon#wrote, iclass 25, count 0 2006.246.08:09:18.93#ibcon#about to read 3, iclass 25, count 0 2006.246.08:09:18.97#ibcon#read 3, iclass 25, count 0 2006.246.08:09:18.97#ibcon#about to read 4, iclass 25, count 0 2006.246.08:09:18.97#ibcon#read 4, iclass 25, count 0 2006.246.08:09:18.97#ibcon#about to read 5, iclass 25, count 0 2006.246.08:09:18.97#ibcon#read 5, iclass 25, count 0 2006.246.08:09:18.97#ibcon#about to read 6, iclass 25, count 0 2006.246.08:09:18.97#ibcon#read 6, iclass 25, count 0 2006.246.08:09:18.97#ibcon#end of sib2, iclass 25, count 0 2006.246.08:09:18.97#ibcon#*after write, iclass 25, count 0 2006.246.08:09:18.97#ibcon#*before return 0, iclass 25, count 0 2006.246.08:09:18.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:18.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:18.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:09:18.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:09:18.97$vc4f8/va=4,7 2006.246.08:09:18.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.08:09:18.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.08:09:18.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:18.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:19.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:19.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:19.03#ibcon#enter wrdev, iclass 27, count 2 2006.246.08:09:19.03#ibcon#first serial, iclass 27, count 2 2006.246.08:09:19.03#ibcon#enter sib2, iclass 27, count 2 2006.246.08:09:19.03#ibcon#flushed, iclass 27, count 2 2006.246.08:09:19.03#ibcon#about to write, iclass 27, count 2 2006.246.08:09:19.03#ibcon#wrote, iclass 27, count 2 2006.246.08:09:19.03#ibcon#about to read 3, iclass 27, count 2 2006.246.08:09:19.05#ibcon#read 3, iclass 27, count 2 2006.246.08:09:19.05#ibcon#about to read 4, iclass 27, count 2 2006.246.08:09:19.05#ibcon#read 4, iclass 27, count 2 2006.246.08:09:19.05#ibcon#about to read 5, iclass 27, count 2 2006.246.08:09:19.05#ibcon#read 5, iclass 27, count 2 2006.246.08:09:19.05#ibcon#about to read 6, iclass 27, count 2 2006.246.08:09:19.05#ibcon#read 6, iclass 27, count 2 2006.246.08:09:19.05#ibcon#end of sib2, iclass 27, count 2 2006.246.08:09:19.05#ibcon#*mode == 0, iclass 27, count 2 2006.246.08:09:19.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.08:09:19.05#ibcon#[25=AT04-07\r\n] 2006.246.08:09:19.05#ibcon#*before write, iclass 27, count 2 2006.246.08:09:19.05#ibcon#enter sib2, iclass 27, count 2 2006.246.08:09:19.05#ibcon#flushed, iclass 27, count 2 2006.246.08:09:19.05#ibcon#about to write, iclass 27, count 2 2006.246.08:09:19.05#ibcon#wrote, iclass 27, count 2 2006.246.08:09:19.05#ibcon#about to read 3, iclass 27, count 2 2006.246.08:09:19.08#ibcon#read 3, iclass 27, count 2 2006.246.08:09:19.08#ibcon#about to read 4, iclass 27, count 2 2006.246.08:09:19.08#ibcon#read 4, iclass 27, count 2 2006.246.08:09:19.08#ibcon#about to read 5, iclass 27, count 2 2006.246.08:09:19.08#ibcon#read 5, iclass 27, count 2 2006.246.08:09:19.08#ibcon#about to read 6, iclass 27, count 2 2006.246.08:09:19.08#ibcon#read 6, iclass 27, count 2 2006.246.08:09:19.08#ibcon#end of sib2, iclass 27, count 2 2006.246.08:09:19.08#ibcon#*after write, iclass 27, count 2 2006.246.08:09:19.08#ibcon#*before return 0, iclass 27, count 2 2006.246.08:09:19.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:19.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:19.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.08:09:19.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:19.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:19.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:19.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:19.20#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:09:19.20#ibcon#first serial, iclass 27, count 0 2006.246.08:09:19.20#ibcon#enter sib2, iclass 27, count 0 2006.246.08:09:19.20#ibcon#flushed, iclass 27, count 0 2006.246.08:09:19.20#ibcon#about to write, iclass 27, count 0 2006.246.08:09:19.20#ibcon#wrote, iclass 27, count 0 2006.246.08:09:19.20#ibcon#about to read 3, iclass 27, count 0 2006.246.08:09:19.22#ibcon#read 3, iclass 27, count 0 2006.246.08:09:19.22#ibcon#about to read 4, iclass 27, count 0 2006.246.08:09:19.22#ibcon#read 4, iclass 27, count 0 2006.246.08:09:19.22#ibcon#about to read 5, iclass 27, count 0 2006.246.08:09:19.22#ibcon#read 5, iclass 27, count 0 2006.246.08:09:19.22#ibcon#about to read 6, iclass 27, count 0 2006.246.08:09:19.22#ibcon#read 6, iclass 27, count 0 2006.246.08:09:19.22#ibcon#end of sib2, iclass 27, count 0 2006.246.08:09:19.22#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:09:19.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:09:19.22#ibcon#[25=USB\r\n] 2006.246.08:09:19.22#ibcon#*before write, iclass 27, count 0 2006.246.08:09:19.22#ibcon#enter sib2, iclass 27, count 0 2006.246.08:09:19.22#ibcon#flushed, iclass 27, count 0 2006.246.08:09:19.22#ibcon#about to write, iclass 27, count 0 2006.246.08:09:19.22#ibcon#wrote, iclass 27, count 0 2006.246.08:09:19.22#ibcon#about to read 3, iclass 27, count 0 2006.246.08:09:19.25#ibcon#read 3, iclass 27, count 0 2006.246.08:09:19.25#ibcon#about to read 4, iclass 27, count 0 2006.246.08:09:19.25#ibcon#read 4, iclass 27, count 0 2006.246.08:09:19.25#ibcon#about to read 5, iclass 27, count 0 2006.246.08:09:19.25#ibcon#read 5, iclass 27, count 0 2006.246.08:09:19.25#ibcon#about to read 6, iclass 27, count 0 2006.246.08:09:19.25#ibcon#read 6, iclass 27, count 0 2006.246.08:09:19.25#ibcon#end of sib2, iclass 27, count 0 2006.246.08:09:19.25#ibcon#*after write, iclass 27, count 0 2006.246.08:09:19.25#ibcon#*before return 0, iclass 27, count 0 2006.246.08:09:19.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:19.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:19.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:09:19.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:09:19.25$vc4f8/valo=5,652.99 2006.246.08:09:19.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.08:09:19.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.08:09:19.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:19.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:19.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:19.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:19.25#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:09:19.25#ibcon#first serial, iclass 29, count 0 2006.246.08:09:19.25#ibcon#enter sib2, iclass 29, count 0 2006.246.08:09:19.25#ibcon#flushed, iclass 29, count 0 2006.246.08:09:19.25#ibcon#about to write, iclass 29, count 0 2006.246.08:09:19.25#ibcon#wrote, iclass 29, count 0 2006.246.08:09:19.25#ibcon#about to read 3, iclass 29, count 0 2006.246.08:09:19.27#ibcon#read 3, iclass 29, count 0 2006.246.08:09:19.27#ibcon#about to read 4, iclass 29, count 0 2006.246.08:09:19.27#ibcon#read 4, iclass 29, count 0 2006.246.08:09:19.27#ibcon#about to read 5, iclass 29, count 0 2006.246.08:09:19.27#ibcon#read 5, iclass 29, count 0 2006.246.08:09:19.27#ibcon#about to read 6, iclass 29, count 0 2006.246.08:09:19.27#ibcon#read 6, iclass 29, count 0 2006.246.08:09:19.27#ibcon#end of sib2, iclass 29, count 0 2006.246.08:09:19.27#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:09:19.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:09:19.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:09:19.27#ibcon#*before write, iclass 29, count 0 2006.246.08:09:19.27#ibcon#enter sib2, iclass 29, count 0 2006.246.08:09:19.27#ibcon#flushed, iclass 29, count 0 2006.246.08:09:19.27#ibcon#about to write, iclass 29, count 0 2006.246.08:09:19.27#ibcon#wrote, iclass 29, count 0 2006.246.08:09:19.27#ibcon#about to read 3, iclass 29, count 0 2006.246.08:09:19.31#ibcon#read 3, iclass 29, count 0 2006.246.08:09:19.31#ibcon#about to read 4, iclass 29, count 0 2006.246.08:09:19.31#ibcon#read 4, iclass 29, count 0 2006.246.08:09:19.31#ibcon#about to read 5, iclass 29, count 0 2006.246.08:09:19.31#ibcon#read 5, iclass 29, count 0 2006.246.08:09:19.31#ibcon#about to read 6, iclass 29, count 0 2006.246.08:09:19.31#ibcon#read 6, iclass 29, count 0 2006.246.08:09:19.31#ibcon#end of sib2, iclass 29, count 0 2006.246.08:09:19.31#ibcon#*after write, iclass 29, count 0 2006.246.08:09:19.31#ibcon#*before return 0, iclass 29, count 0 2006.246.08:09:19.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:19.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:19.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:09:19.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:09:19.31$vc4f8/va=5,7 2006.246.08:09:19.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.08:09:19.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.08:09:19.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:19.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:19.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:19.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:19.37#ibcon#enter wrdev, iclass 31, count 2 2006.246.08:09:19.37#ibcon#first serial, iclass 31, count 2 2006.246.08:09:19.37#ibcon#enter sib2, iclass 31, count 2 2006.246.08:09:19.37#ibcon#flushed, iclass 31, count 2 2006.246.08:09:19.37#ibcon#about to write, iclass 31, count 2 2006.246.08:09:19.37#ibcon#wrote, iclass 31, count 2 2006.246.08:09:19.37#ibcon#about to read 3, iclass 31, count 2 2006.246.08:09:19.39#ibcon#read 3, iclass 31, count 2 2006.246.08:09:19.39#ibcon#about to read 4, iclass 31, count 2 2006.246.08:09:19.39#ibcon#read 4, iclass 31, count 2 2006.246.08:09:19.39#ibcon#about to read 5, iclass 31, count 2 2006.246.08:09:19.39#ibcon#read 5, iclass 31, count 2 2006.246.08:09:19.39#ibcon#about to read 6, iclass 31, count 2 2006.246.08:09:19.39#ibcon#read 6, iclass 31, count 2 2006.246.08:09:19.39#ibcon#end of sib2, iclass 31, count 2 2006.246.08:09:19.39#ibcon#*mode == 0, iclass 31, count 2 2006.246.08:09:19.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.08:09:19.39#ibcon#[25=AT05-07\r\n] 2006.246.08:09:19.39#ibcon#*before write, iclass 31, count 2 2006.246.08:09:19.39#ibcon#enter sib2, iclass 31, count 2 2006.246.08:09:19.39#ibcon#flushed, iclass 31, count 2 2006.246.08:09:19.39#ibcon#about to write, iclass 31, count 2 2006.246.08:09:19.39#ibcon#wrote, iclass 31, count 2 2006.246.08:09:19.39#ibcon#about to read 3, iclass 31, count 2 2006.246.08:09:19.42#ibcon#read 3, iclass 31, count 2 2006.246.08:09:19.42#ibcon#about to read 4, iclass 31, count 2 2006.246.08:09:19.42#ibcon#read 4, iclass 31, count 2 2006.246.08:09:19.42#ibcon#about to read 5, iclass 31, count 2 2006.246.08:09:19.42#ibcon#read 5, iclass 31, count 2 2006.246.08:09:19.42#ibcon#about to read 6, iclass 31, count 2 2006.246.08:09:19.42#ibcon#read 6, iclass 31, count 2 2006.246.08:09:19.42#ibcon#end of sib2, iclass 31, count 2 2006.246.08:09:19.42#ibcon#*after write, iclass 31, count 2 2006.246.08:09:19.42#ibcon#*before return 0, iclass 31, count 2 2006.246.08:09:19.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:19.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:19.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.08:09:19.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:19.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:19.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:19.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:19.54#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:09:19.54#ibcon#first serial, iclass 31, count 0 2006.246.08:09:19.54#ibcon#enter sib2, iclass 31, count 0 2006.246.08:09:19.54#ibcon#flushed, iclass 31, count 0 2006.246.08:09:19.54#ibcon#about to write, iclass 31, count 0 2006.246.08:09:19.54#ibcon#wrote, iclass 31, count 0 2006.246.08:09:19.54#ibcon#about to read 3, iclass 31, count 0 2006.246.08:09:19.56#ibcon#read 3, iclass 31, count 0 2006.246.08:09:19.56#ibcon#about to read 4, iclass 31, count 0 2006.246.08:09:19.56#ibcon#read 4, iclass 31, count 0 2006.246.08:09:19.56#ibcon#about to read 5, iclass 31, count 0 2006.246.08:09:19.56#ibcon#read 5, iclass 31, count 0 2006.246.08:09:19.56#ibcon#about to read 6, iclass 31, count 0 2006.246.08:09:19.56#ibcon#read 6, iclass 31, count 0 2006.246.08:09:19.56#ibcon#end of sib2, iclass 31, count 0 2006.246.08:09:19.56#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:09:19.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:09:19.56#ibcon#[25=USB\r\n] 2006.246.08:09:19.56#ibcon#*before write, iclass 31, count 0 2006.246.08:09:19.56#ibcon#enter sib2, iclass 31, count 0 2006.246.08:09:19.56#ibcon#flushed, iclass 31, count 0 2006.246.08:09:19.56#ibcon#about to write, iclass 31, count 0 2006.246.08:09:19.56#ibcon#wrote, iclass 31, count 0 2006.246.08:09:19.56#ibcon#about to read 3, iclass 31, count 0 2006.246.08:09:19.59#ibcon#read 3, iclass 31, count 0 2006.246.08:09:19.59#ibcon#about to read 4, iclass 31, count 0 2006.246.08:09:19.59#ibcon#read 4, iclass 31, count 0 2006.246.08:09:19.59#ibcon#about to read 5, iclass 31, count 0 2006.246.08:09:19.59#ibcon#read 5, iclass 31, count 0 2006.246.08:09:19.59#ibcon#about to read 6, iclass 31, count 0 2006.246.08:09:19.59#ibcon#read 6, iclass 31, count 0 2006.246.08:09:19.59#ibcon#end of sib2, iclass 31, count 0 2006.246.08:09:19.59#ibcon#*after write, iclass 31, count 0 2006.246.08:09:19.59#ibcon#*before return 0, iclass 31, count 0 2006.246.08:09:19.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:19.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:19.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:09:19.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:09:19.59$vc4f8/valo=6,772.99 2006.246.08:09:19.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.08:09:19.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.08:09:19.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:19.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:19.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:19.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:19.59#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:09:19.59#ibcon#first serial, iclass 33, count 0 2006.246.08:09:19.59#ibcon#enter sib2, iclass 33, count 0 2006.246.08:09:19.59#ibcon#flushed, iclass 33, count 0 2006.246.08:09:19.59#ibcon#about to write, iclass 33, count 0 2006.246.08:09:19.59#ibcon#wrote, iclass 33, count 0 2006.246.08:09:19.59#ibcon#about to read 3, iclass 33, count 0 2006.246.08:09:19.61#ibcon#read 3, iclass 33, count 0 2006.246.08:09:19.61#ibcon#about to read 4, iclass 33, count 0 2006.246.08:09:19.61#ibcon#read 4, iclass 33, count 0 2006.246.08:09:19.61#ibcon#about to read 5, iclass 33, count 0 2006.246.08:09:19.61#ibcon#read 5, iclass 33, count 0 2006.246.08:09:19.61#ibcon#about to read 6, iclass 33, count 0 2006.246.08:09:19.61#ibcon#read 6, iclass 33, count 0 2006.246.08:09:19.61#ibcon#end of sib2, iclass 33, count 0 2006.246.08:09:19.61#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:09:19.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:09:19.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:09:19.61#ibcon#*before write, iclass 33, count 0 2006.246.08:09:19.61#ibcon#enter sib2, iclass 33, count 0 2006.246.08:09:19.61#ibcon#flushed, iclass 33, count 0 2006.246.08:09:19.61#ibcon#about to write, iclass 33, count 0 2006.246.08:09:19.61#ibcon#wrote, iclass 33, count 0 2006.246.08:09:19.61#ibcon#about to read 3, iclass 33, count 0 2006.246.08:09:19.65#ibcon#read 3, iclass 33, count 0 2006.246.08:09:19.65#ibcon#about to read 4, iclass 33, count 0 2006.246.08:09:19.65#ibcon#read 4, iclass 33, count 0 2006.246.08:09:19.65#ibcon#about to read 5, iclass 33, count 0 2006.246.08:09:19.65#ibcon#read 5, iclass 33, count 0 2006.246.08:09:19.65#ibcon#about to read 6, iclass 33, count 0 2006.246.08:09:19.65#ibcon#read 6, iclass 33, count 0 2006.246.08:09:19.65#ibcon#end of sib2, iclass 33, count 0 2006.246.08:09:19.65#ibcon#*after write, iclass 33, count 0 2006.246.08:09:19.65#ibcon#*before return 0, iclass 33, count 0 2006.246.08:09:19.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:19.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:19.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:09:19.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:09:19.65$vc4f8/va=6,7 2006.246.08:09:19.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.08:09:19.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.08:09:19.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:19.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:09:19.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:09:19.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:09:19.71#ibcon#enter wrdev, iclass 35, count 2 2006.246.08:09:19.71#ibcon#first serial, iclass 35, count 2 2006.246.08:09:19.71#ibcon#enter sib2, iclass 35, count 2 2006.246.08:09:19.71#ibcon#flushed, iclass 35, count 2 2006.246.08:09:19.71#ibcon#about to write, iclass 35, count 2 2006.246.08:09:19.71#ibcon#wrote, iclass 35, count 2 2006.246.08:09:19.71#ibcon#about to read 3, iclass 35, count 2 2006.246.08:09:19.73#ibcon#read 3, iclass 35, count 2 2006.246.08:09:19.73#ibcon#about to read 4, iclass 35, count 2 2006.246.08:09:19.73#ibcon#read 4, iclass 35, count 2 2006.246.08:09:19.73#ibcon#about to read 5, iclass 35, count 2 2006.246.08:09:19.73#ibcon#read 5, iclass 35, count 2 2006.246.08:09:19.73#ibcon#about to read 6, iclass 35, count 2 2006.246.08:09:19.73#ibcon#read 6, iclass 35, count 2 2006.246.08:09:19.73#ibcon#end of sib2, iclass 35, count 2 2006.246.08:09:19.73#ibcon#*mode == 0, iclass 35, count 2 2006.246.08:09:19.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.08:09:19.73#ibcon#[25=AT06-07\r\n] 2006.246.08:09:19.73#ibcon#*before write, iclass 35, count 2 2006.246.08:09:19.73#ibcon#enter sib2, iclass 35, count 2 2006.246.08:09:19.73#ibcon#flushed, iclass 35, count 2 2006.246.08:09:19.73#ibcon#about to write, iclass 35, count 2 2006.246.08:09:19.73#ibcon#wrote, iclass 35, count 2 2006.246.08:09:19.73#ibcon#about to read 3, iclass 35, count 2 2006.246.08:09:19.76#ibcon#read 3, iclass 35, count 2 2006.246.08:09:19.76#ibcon#about to read 4, iclass 35, count 2 2006.246.08:09:19.76#ibcon#read 4, iclass 35, count 2 2006.246.08:09:19.76#ibcon#about to read 5, iclass 35, count 2 2006.246.08:09:19.76#ibcon#read 5, iclass 35, count 2 2006.246.08:09:19.76#ibcon#about to read 6, iclass 35, count 2 2006.246.08:09:19.76#ibcon#read 6, iclass 35, count 2 2006.246.08:09:19.76#ibcon#end of sib2, iclass 35, count 2 2006.246.08:09:19.76#ibcon#*after write, iclass 35, count 2 2006.246.08:09:19.76#ibcon#*before return 0, iclass 35, count 2 2006.246.08:09:19.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:09:19.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:09:19.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.08:09:19.76#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:19.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:09:19.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:09:19.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:09:19.88#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:09:19.88#ibcon#first serial, iclass 35, count 0 2006.246.08:09:19.88#ibcon#enter sib2, iclass 35, count 0 2006.246.08:09:19.88#ibcon#flushed, iclass 35, count 0 2006.246.08:09:19.88#ibcon#about to write, iclass 35, count 0 2006.246.08:09:19.88#ibcon#wrote, iclass 35, count 0 2006.246.08:09:19.88#ibcon#about to read 3, iclass 35, count 0 2006.246.08:09:19.90#ibcon#read 3, iclass 35, count 0 2006.246.08:09:19.90#ibcon#about to read 4, iclass 35, count 0 2006.246.08:09:19.90#ibcon#read 4, iclass 35, count 0 2006.246.08:09:19.90#ibcon#about to read 5, iclass 35, count 0 2006.246.08:09:19.90#ibcon#read 5, iclass 35, count 0 2006.246.08:09:19.90#ibcon#about to read 6, iclass 35, count 0 2006.246.08:09:19.90#ibcon#read 6, iclass 35, count 0 2006.246.08:09:19.90#ibcon#end of sib2, iclass 35, count 0 2006.246.08:09:19.90#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:09:19.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:09:19.90#ibcon#[25=USB\r\n] 2006.246.08:09:19.90#ibcon#*before write, iclass 35, count 0 2006.246.08:09:19.90#ibcon#enter sib2, iclass 35, count 0 2006.246.08:09:19.90#ibcon#flushed, iclass 35, count 0 2006.246.08:09:19.90#ibcon#about to write, iclass 35, count 0 2006.246.08:09:19.90#ibcon#wrote, iclass 35, count 0 2006.246.08:09:19.90#ibcon#about to read 3, iclass 35, count 0 2006.246.08:09:19.93#ibcon#read 3, iclass 35, count 0 2006.246.08:09:19.93#ibcon#about to read 4, iclass 35, count 0 2006.246.08:09:19.93#ibcon#read 4, iclass 35, count 0 2006.246.08:09:19.93#ibcon#about to read 5, iclass 35, count 0 2006.246.08:09:19.93#ibcon#read 5, iclass 35, count 0 2006.246.08:09:19.93#ibcon#about to read 6, iclass 35, count 0 2006.246.08:09:19.93#ibcon#read 6, iclass 35, count 0 2006.246.08:09:19.93#ibcon#end of sib2, iclass 35, count 0 2006.246.08:09:19.93#ibcon#*after write, iclass 35, count 0 2006.246.08:09:19.93#ibcon#*before return 0, iclass 35, count 0 2006.246.08:09:19.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:09:19.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:09:19.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:09:19.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:09:19.93$vc4f8/valo=7,832.99 2006.246.08:09:19.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.08:09:19.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.08:09:19.93#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:19.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:09:19.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:09:19.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:09:19.93#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:09:19.93#ibcon#first serial, iclass 37, count 0 2006.246.08:09:19.93#ibcon#enter sib2, iclass 37, count 0 2006.246.08:09:19.93#ibcon#flushed, iclass 37, count 0 2006.246.08:09:19.93#ibcon#about to write, iclass 37, count 0 2006.246.08:09:19.93#ibcon#wrote, iclass 37, count 0 2006.246.08:09:19.93#ibcon#about to read 3, iclass 37, count 0 2006.246.08:09:19.95#ibcon#read 3, iclass 37, count 0 2006.246.08:09:19.95#ibcon#about to read 4, iclass 37, count 0 2006.246.08:09:19.95#ibcon#read 4, iclass 37, count 0 2006.246.08:09:19.95#ibcon#about to read 5, iclass 37, count 0 2006.246.08:09:19.95#ibcon#read 5, iclass 37, count 0 2006.246.08:09:19.95#ibcon#about to read 6, iclass 37, count 0 2006.246.08:09:19.95#ibcon#read 6, iclass 37, count 0 2006.246.08:09:19.95#ibcon#end of sib2, iclass 37, count 0 2006.246.08:09:19.95#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:09:19.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:09:19.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:09:19.95#ibcon#*before write, iclass 37, count 0 2006.246.08:09:19.95#ibcon#enter sib2, iclass 37, count 0 2006.246.08:09:19.95#ibcon#flushed, iclass 37, count 0 2006.246.08:09:19.95#ibcon#about to write, iclass 37, count 0 2006.246.08:09:19.95#ibcon#wrote, iclass 37, count 0 2006.246.08:09:19.95#ibcon#about to read 3, iclass 37, count 0 2006.246.08:09:19.99#ibcon#read 3, iclass 37, count 0 2006.246.08:09:19.99#ibcon#about to read 4, iclass 37, count 0 2006.246.08:09:19.99#ibcon#read 4, iclass 37, count 0 2006.246.08:09:19.99#ibcon#about to read 5, iclass 37, count 0 2006.246.08:09:19.99#ibcon#read 5, iclass 37, count 0 2006.246.08:09:19.99#ibcon#about to read 6, iclass 37, count 0 2006.246.08:09:19.99#ibcon#read 6, iclass 37, count 0 2006.246.08:09:19.99#ibcon#end of sib2, iclass 37, count 0 2006.246.08:09:19.99#ibcon#*after write, iclass 37, count 0 2006.246.08:09:19.99#ibcon#*before return 0, iclass 37, count 0 2006.246.08:09:19.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:09:19.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:09:19.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:09:19.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:09:19.99$vc4f8/va=7,7 2006.246.08:09:19.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.08:09:19.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.08:09:19.99#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:19.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:09:20.05#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:09:20.05#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:09:20.05#ibcon#enter wrdev, iclass 39, count 2 2006.246.08:09:20.05#ibcon#first serial, iclass 39, count 2 2006.246.08:09:20.05#ibcon#enter sib2, iclass 39, count 2 2006.246.08:09:20.05#ibcon#flushed, iclass 39, count 2 2006.246.08:09:20.05#ibcon#about to write, iclass 39, count 2 2006.246.08:09:20.05#ibcon#wrote, iclass 39, count 2 2006.246.08:09:20.05#ibcon#about to read 3, iclass 39, count 2 2006.246.08:09:20.07#ibcon#read 3, iclass 39, count 2 2006.246.08:09:20.07#ibcon#about to read 4, iclass 39, count 2 2006.246.08:09:20.07#ibcon#read 4, iclass 39, count 2 2006.246.08:09:20.07#ibcon#about to read 5, iclass 39, count 2 2006.246.08:09:20.07#ibcon#read 5, iclass 39, count 2 2006.246.08:09:20.07#ibcon#about to read 6, iclass 39, count 2 2006.246.08:09:20.07#ibcon#read 6, iclass 39, count 2 2006.246.08:09:20.07#ibcon#end of sib2, iclass 39, count 2 2006.246.08:09:20.07#ibcon#*mode == 0, iclass 39, count 2 2006.246.08:09:20.07#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.08:09:20.07#ibcon#[25=AT07-07\r\n] 2006.246.08:09:20.07#ibcon#*before write, iclass 39, count 2 2006.246.08:09:20.07#ibcon#enter sib2, iclass 39, count 2 2006.246.08:09:20.07#ibcon#flushed, iclass 39, count 2 2006.246.08:09:20.07#ibcon#about to write, iclass 39, count 2 2006.246.08:09:20.07#ibcon#wrote, iclass 39, count 2 2006.246.08:09:20.07#ibcon#about to read 3, iclass 39, count 2 2006.246.08:09:20.10#ibcon#read 3, iclass 39, count 2 2006.246.08:09:20.10#ibcon#about to read 4, iclass 39, count 2 2006.246.08:09:20.10#ibcon#read 4, iclass 39, count 2 2006.246.08:09:20.10#ibcon#about to read 5, iclass 39, count 2 2006.246.08:09:20.10#ibcon#read 5, iclass 39, count 2 2006.246.08:09:20.10#ibcon#about to read 6, iclass 39, count 2 2006.246.08:09:20.10#ibcon#read 6, iclass 39, count 2 2006.246.08:09:20.10#ibcon#end of sib2, iclass 39, count 2 2006.246.08:09:20.10#ibcon#*after write, iclass 39, count 2 2006.246.08:09:20.10#ibcon#*before return 0, iclass 39, count 2 2006.246.08:09:20.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:09:20.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:09:20.10#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.08:09:20.10#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:20.10#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:09:20.22#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:09:20.22#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:09:20.22#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:09:20.22#ibcon#first serial, iclass 39, count 0 2006.246.08:09:20.22#ibcon#enter sib2, iclass 39, count 0 2006.246.08:09:20.22#ibcon#flushed, iclass 39, count 0 2006.246.08:09:20.22#ibcon#about to write, iclass 39, count 0 2006.246.08:09:20.22#ibcon#wrote, iclass 39, count 0 2006.246.08:09:20.22#ibcon#about to read 3, iclass 39, count 0 2006.246.08:09:20.24#ibcon#read 3, iclass 39, count 0 2006.246.08:09:20.24#ibcon#about to read 4, iclass 39, count 0 2006.246.08:09:20.24#ibcon#read 4, iclass 39, count 0 2006.246.08:09:20.24#ibcon#about to read 5, iclass 39, count 0 2006.246.08:09:20.24#ibcon#read 5, iclass 39, count 0 2006.246.08:09:20.24#ibcon#about to read 6, iclass 39, count 0 2006.246.08:09:20.24#ibcon#read 6, iclass 39, count 0 2006.246.08:09:20.24#ibcon#end of sib2, iclass 39, count 0 2006.246.08:09:20.24#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:09:20.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:09:20.24#ibcon#[25=USB\r\n] 2006.246.08:09:20.24#ibcon#*before write, iclass 39, count 0 2006.246.08:09:20.24#ibcon#enter sib2, iclass 39, count 0 2006.246.08:09:20.24#ibcon#flushed, iclass 39, count 0 2006.246.08:09:20.24#ibcon#about to write, iclass 39, count 0 2006.246.08:09:20.24#ibcon#wrote, iclass 39, count 0 2006.246.08:09:20.24#ibcon#about to read 3, iclass 39, count 0 2006.246.08:09:20.27#ibcon#read 3, iclass 39, count 0 2006.246.08:09:20.27#ibcon#about to read 4, iclass 39, count 0 2006.246.08:09:20.27#ibcon#read 4, iclass 39, count 0 2006.246.08:09:20.27#ibcon#about to read 5, iclass 39, count 0 2006.246.08:09:20.27#ibcon#read 5, iclass 39, count 0 2006.246.08:09:20.27#ibcon#about to read 6, iclass 39, count 0 2006.246.08:09:20.27#ibcon#read 6, iclass 39, count 0 2006.246.08:09:20.27#ibcon#end of sib2, iclass 39, count 0 2006.246.08:09:20.27#ibcon#*after write, iclass 39, count 0 2006.246.08:09:20.27#ibcon#*before return 0, iclass 39, count 0 2006.246.08:09:20.27#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:09:20.27#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:09:20.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:09:20.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:09:20.27$vc4f8/valo=8,852.99 2006.246.08:09:20.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.08:09:20.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.08:09:20.27#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:20.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:09:20.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:09:20.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:09:20.27#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:09:20.27#ibcon#first serial, iclass 3, count 0 2006.246.08:09:20.27#ibcon#enter sib2, iclass 3, count 0 2006.246.08:09:20.27#ibcon#flushed, iclass 3, count 0 2006.246.08:09:20.27#ibcon#about to write, iclass 3, count 0 2006.246.08:09:20.27#ibcon#wrote, iclass 3, count 0 2006.246.08:09:20.27#ibcon#about to read 3, iclass 3, count 0 2006.246.08:09:20.29#ibcon#read 3, iclass 3, count 0 2006.246.08:09:20.29#ibcon#about to read 4, iclass 3, count 0 2006.246.08:09:20.29#ibcon#read 4, iclass 3, count 0 2006.246.08:09:20.29#ibcon#about to read 5, iclass 3, count 0 2006.246.08:09:20.29#ibcon#read 5, iclass 3, count 0 2006.246.08:09:20.29#ibcon#about to read 6, iclass 3, count 0 2006.246.08:09:20.29#ibcon#read 6, iclass 3, count 0 2006.246.08:09:20.29#ibcon#end of sib2, iclass 3, count 0 2006.246.08:09:20.29#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:09:20.29#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:09:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:09:20.29#ibcon#*before write, iclass 3, count 0 2006.246.08:09:20.29#ibcon#enter sib2, iclass 3, count 0 2006.246.08:09:20.29#ibcon#flushed, iclass 3, count 0 2006.246.08:09:20.29#ibcon#about to write, iclass 3, count 0 2006.246.08:09:20.29#ibcon#wrote, iclass 3, count 0 2006.246.08:09:20.29#ibcon#about to read 3, iclass 3, count 0 2006.246.08:09:20.33#ibcon#read 3, iclass 3, count 0 2006.246.08:09:20.33#ibcon#about to read 4, iclass 3, count 0 2006.246.08:09:20.33#ibcon#read 4, iclass 3, count 0 2006.246.08:09:20.33#ibcon#about to read 5, iclass 3, count 0 2006.246.08:09:20.33#ibcon#read 5, iclass 3, count 0 2006.246.08:09:20.33#ibcon#about to read 6, iclass 3, count 0 2006.246.08:09:20.33#ibcon#read 6, iclass 3, count 0 2006.246.08:09:20.33#ibcon#end of sib2, iclass 3, count 0 2006.246.08:09:20.33#ibcon#*after write, iclass 3, count 0 2006.246.08:09:20.33#ibcon#*before return 0, iclass 3, count 0 2006.246.08:09:20.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:09:20.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:09:20.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:09:20.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:09:20.33$vc4f8/va=8,8 2006.246.08:09:20.33#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.08:09:20.33#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.08:09:20.33#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:20.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:09:20.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:09:20.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:09:20.39#ibcon#enter wrdev, iclass 5, count 2 2006.246.08:09:20.39#ibcon#first serial, iclass 5, count 2 2006.246.08:09:20.39#ibcon#enter sib2, iclass 5, count 2 2006.246.08:09:20.39#ibcon#flushed, iclass 5, count 2 2006.246.08:09:20.39#ibcon#about to write, iclass 5, count 2 2006.246.08:09:20.39#ibcon#wrote, iclass 5, count 2 2006.246.08:09:20.39#ibcon#about to read 3, iclass 5, count 2 2006.246.08:09:20.41#ibcon#read 3, iclass 5, count 2 2006.246.08:09:20.41#ibcon#about to read 4, iclass 5, count 2 2006.246.08:09:20.41#ibcon#read 4, iclass 5, count 2 2006.246.08:09:20.41#ibcon#about to read 5, iclass 5, count 2 2006.246.08:09:20.41#ibcon#read 5, iclass 5, count 2 2006.246.08:09:20.41#ibcon#about to read 6, iclass 5, count 2 2006.246.08:09:20.41#ibcon#read 6, iclass 5, count 2 2006.246.08:09:20.41#ibcon#end of sib2, iclass 5, count 2 2006.246.08:09:20.41#ibcon#*mode == 0, iclass 5, count 2 2006.246.08:09:20.41#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.08:09:20.41#ibcon#[25=AT08-08\r\n] 2006.246.08:09:20.41#ibcon#*before write, iclass 5, count 2 2006.246.08:09:20.41#ibcon#enter sib2, iclass 5, count 2 2006.246.08:09:20.41#ibcon#flushed, iclass 5, count 2 2006.246.08:09:20.41#ibcon#about to write, iclass 5, count 2 2006.246.08:09:20.41#ibcon#wrote, iclass 5, count 2 2006.246.08:09:20.41#ibcon#about to read 3, iclass 5, count 2 2006.246.08:09:20.44#ibcon#read 3, iclass 5, count 2 2006.246.08:09:20.44#ibcon#about to read 4, iclass 5, count 2 2006.246.08:09:20.44#ibcon#read 4, iclass 5, count 2 2006.246.08:09:20.44#ibcon#about to read 5, iclass 5, count 2 2006.246.08:09:20.44#ibcon#read 5, iclass 5, count 2 2006.246.08:09:20.44#ibcon#about to read 6, iclass 5, count 2 2006.246.08:09:20.44#ibcon#read 6, iclass 5, count 2 2006.246.08:09:20.44#ibcon#end of sib2, iclass 5, count 2 2006.246.08:09:20.44#ibcon#*after write, iclass 5, count 2 2006.246.08:09:20.44#ibcon#*before return 0, iclass 5, count 2 2006.246.08:09:20.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:09:20.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:09:20.44#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.08:09:20.44#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:20.44#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:09:20.56#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:09:20.56#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:09:20.56#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:09:20.56#ibcon#first serial, iclass 5, count 0 2006.246.08:09:20.56#ibcon#enter sib2, iclass 5, count 0 2006.246.08:09:20.56#ibcon#flushed, iclass 5, count 0 2006.246.08:09:20.56#ibcon#about to write, iclass 5, count 0 2006.246.08:09:20.56#ibcon#wrote, iclass 5, count 0 2006.246.08:09:20.56#ibcon#about to read 3, iclass 5, count 0 2006.246.08:09:20.58#ibcon#read 3, iclass 5, count 0 2006.246.08:09:20.58#ibcon#about to read 4, iclass 5, count 0 2006.246.08:09:20.58#ibcon#read 4, iclass 5, count 0 2006.246.08:09:20.58#ibcon#about to read 5, iclass 5, count 0 2006.246.08:09:20.58#ibcon#read 5, iclass 5, count 0 2006.246.08:09:20.58#ibcon#about to read 6, iclass 5, count 0 2006.246.08:09:20.58#ibcon#read 6, iclass 5, count 0 2006.246.08:09:20.58#ibcon#end of sib2, iclass 5, count 0 2006.246.08:09:20.58#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:09:20.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:09:20.58#ibcon#[25=USB\r\n] 2006.246.08:09:20.58#ibcon#*before write, iclass 5, count 0 2006.246.08:09:20.58#ibcon#enter sib2, iclass 5, count 0 2006.246.08:09:20.58#ibcon#flushed, iclass 5, count 0 2006.246.08:09:20.58#ibcon#about to write, iclass 5, count 0 2006.246.08:09:20.58#ibcon#wrote, iclass 5, count 0 2006.246.08:09:20.58#ibcon#about to read 3, iclass 5, count 0 2006.246.08:09:20.61#ibcon#read 3, iclass 5, count 0 2006.246.08:09:20.61#ibcon#about to read 4, iclass 5, count 0 2006.246.08:09:20.61#ibcon#read 4, iclass 5, count 0 2006.246.08:09:20.61#ibcon#about to read 5, iclass 5, count 0 2006.246.08:09:20.61#ibcon#read 5, iclass 5, count 0 2006.246.08:09:20.61#ibcon#about to read 6, iclass 5, count 0 2006.246.08:09:20.61#ibcon#read 6, iclass 5, count 0 2006.246.08:09:20.61#ibcon#end of sib2, iclass 5, count 0 2006.246.08:09:20.61#ibcon#*after write, iclass 5, count 0 2006.246.08:09:20.61#ibcon#*before return 0, iclass 5, count 0 2006.246.08:09:20.61#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:09:20.61#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:09:20.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:09:20.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:09:20.61$vc4f8/vblo=1,632.99 2006.246.08:09:20.61#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.08:09:20.61#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.08:09:20.61#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:20.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:09:20.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:09:20.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:09:20.61#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:09:20.61#ibcon#first serial, iclass 7, count 0 2006.246.08:09:20.61#ibcon#enter sib2, iclass 7, count 0 2006.246.08:09:20.61#ibcon#flushed, iclass 7, count 0 2006.246.08:09:20.61#ibcon#about to write, iclass 7, count 0 2006.246.08:09:20.61#ibcon#wrote, iclass 7, count 0 2006.246.08:09:20.61#ibcon#about to read 3, iclass 7, count 0 2006.246.08:09:20.63#ibcon#read 3, iclass 7, count 0 2006.246.08:09:20.63#ibcon#about to read 4, iclass 7, count 0 2006.246.08:09:20.63#ibcon#read 4, iclass 7, count 0 2006.246.08:09:20.63#ibcon#about to read 5, iclass 7, count 0 2006.246.08:09:20.63#ibcon#read 5, iclass 7, count 0 2006.246.08:09:20.63#ibcon#about to read 6, iclass 7, count 0 2006.246.08:09:20.63#ibcon#read 6, iclass 7, count 0 2006.246.08:09:20.63#ibcon#end of sib2, iclass 7, count 0 2006.246.08:09:20.63#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:09:20.63#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:09:20.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:09:20.63#ibcon#*before write, iclass 7, count 0 2006.246.08:09:20.63#ibcon#enter sib2, iclass 7, count 0 2006.246.08:09:20.63#ibcon#flushed, iclass 7, count 0 2006.246.08:09:20.63#ibcon#about to write, iclass 7, count 0 2006.246.08:09:20.63#ibcon#wrote, iclass 7, count 0 2006.246.08:09:20.63#ibcon#about to read 3, iclass 7, count 0 2006.246.08:09:20.67#ibcon#read 3, iclass 7, count 0 2006.246.08:09:20.67#ibcon#about to read 4, iclass 7, count 0 2006.246.08:09:20.67#ibcon#read 4, iclass 7, count 0 2006.246.08:09:20.67#ibcon#about to read 5, iclass 7, count 0 2006.246.08:09:20.67#ibcon#read 5, iclass 7, count 0 2006.246.08:09:20.67#ibcon#about to read 6, iclass 7, count 0 2006.246.08:09:20.67#ibcon#read 6, iclass 7, count 0 2006.246.08:09:20.67#ibcon#end of sib2, iclass 7, count 0 2006.246.08:09:20.67#ibcon#*after write, iclass 7, count 0 2006.246.08:09:20.67#ibcon#*before return 0, iclass 7, count 0 2006.246.08:09:20.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:09:20.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:09:20.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:09:20.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:09:20.67$vc4f8/vb=1,4 2006.246.08:09:20.67#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.08:09:20.67#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.08:09:20.67#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:20.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:09:20.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:09:20.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:09:20.67#ibcon#enter wrdev, iclass 11, count 2 2006.246.08:09:20.67#ibcon#first serial, iclass 11, count 2 2006.246.08:09:20.67#ibcon#enter sib2, iclass 11, count 2 2006.246.08:09:20.67#ibcon#flushed, iclass 11, count 2 2006.246.08:09:20.67#ibcon#about to write, iclass 11, count 2 2006.246.08:09:20.67#ibcon#wrote, iclass 11, count 2 2006.246.08:09:20.67#ibcon#about to read 3, iclass 11, count 2 2006.246.08:09:20.69#ibcon#read 3, iclass 11, count 2 2006.246.08:09:20.69#ibcon#about to read 4, iclass 11, count 2 2006.246.08:09:20.69#ibcon#read 4, iclass 11, count 2 2006.246.08:09:20.69#ibcon#about to read 5, iclass 11, count 2 2006.246.08:09:20.69#ibcon#read 5, iclass 11, count 2 2006.246.08:09:20.69#ibcon#about to read 6, iclass 11, count 2 2006.246.08:09:20.69#ibcon#read 6, iclass 11, count 2 2006.246.08:09:20.69#ibcon#end of sib2, iclass 11, count 2 2006.246.08:09:20.69#ibcon#*mode == 0, iclass 11, count 2 2006.246.08:09:20.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.08:09:20.69#ibcon#[27=AT01-04\r\n] 2006.246.08:09:20.69#ibcon#*before write, iclass 11, count 2 2006.246.08:09:20.69#ibcon#enter sib2, iclass 11, count 2 2006.246.08:09:20.69#ibcon#flushed, iclass 11, count 2 2006.246.08:09:20.69#ibcon#about to write, iclass 11, count 2 2006.246.08:09:20.69#ibcon#wrote, iclass 11, count 2 2006.246.08:09:20.69#ibcon#about to read 3, iclass 11, count 2 2006.246.08:09:20.72#ibcon#read 3, iclass 11, count 2 2006.246.08:09:20.72#ibcon#about to read 4, iclass 11, count 2 2006.246.08:09:20.72#ibcon#read 4, iclass 11, count 2 2006.246.08:09:20.72#ibcon#about to read 5, iclass 11, count 2 2006.246.08:09:20.72#ibcon#read 5, iclass 11, count 2 2006.246.08:09:20.72#ibcon#about to read 6, iclass 11, count 2 2006.246.08:09:20.72#ibcon#read 6, iclass 11, count 2 2006.246.08:09:20.72#ibcon#end of sib2, iclass 11, count 2 2006.246.08:09:20.72#ibcon#*after write, iclass 11, count 2 2006.246.08:09:20.72#ibcon#*before return 0, iclass 11, count 2 2006.246.08:09:20.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:09:20.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:09:20.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.08:09:20.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:20.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:09:20.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:09:20.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:09:20.84#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:09:20.84#ibcon#first serial, iclass 11, count 0 2006.246.08:09:20.84#ibcon#enter sib2, iclass 11, count 0 2006.246.08:09:20.84#ibcon#flushed, iclass 11, count 0 2006.246.08:09:20.84#ibcon#about to write, iclass 11, count 0 2006.246.08:09:20.84#ibcon#wrote, iclass 11, count 0 2006.246.08:09:20.84#ibcon#about to read 3, iclass 11, count 0 2006.246.08:09:20.86#ibcon#read 3, iclass 11, count 0 2006.246.08:09:20.86#ibcon#about to read 4, iclass 11, count 0 2006.246.08:09:20.86#ibcon#read 4, iclass 11, count 0 2006.246.08:09:20.86#ibcon#about to read 5, iclass 11, count 0 2006.246.08:09:20.86#ibcon#read 5, iclass 11, count 0 2006.246.08:09:20.86#ibcon#about to read 6, iclass 11, count 0 2006.246.08:09:20.86#ibcon#read 6, iclass 11, count 0 2006.246.08:09:20.86#ibcon#end of sib2, iclass 11, count 0 2006.246.08:09:20.86#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:09:20.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:09:20.86#ibcon#[27=USB\r\n] 2006.246.08:09:20.86#ibcon#*before write, iclass 11, count 0 2006.246.08:09:20.86#ibcon#enter sib2, iclass 11, count 0 2006.246.08:09:20.86#ibcon#flushed, iclass 11, count 0 2006.246.08:09:20.86#ibcon#about to write, iclass 11, count 0 2006.246.08:09:20.86#ibcon#wrote, iclass 11, count 0 2006.246.08:09:20.86#ibcon#about to read 3, iclass 11, count 0 2006.246.08:09:20.89#ibcon#read 3, iclass 11, count 0 2006.246.08:09:20.89#ibcon#about to read 4, iclass 11, count 0 2006.246.08:09:20.89#ibcon#read 4, iclass 11, count 0 2006.246.08:09:20.89#ibcon#about to read 5, iclass 11, count 0 2006.246.08:09:20.89#ibcon#read 5, iclass 11, count 0 2006.246.08:09:20.89#ibcon#about to read 6, iclass 11, count 0 2006.246.08:09:20.89#ibcon#read 6, iclass 11, count 0 2006.246.08:09:20.89#ibcon#end of sib2, iclass 11, count 0 2006.246.08:09:20.89#ibcon#*after write, iclass 11, count 0 2006.246.08:09:20.89#ibcon#*before return 0, iclass 11, count 0 2006.246.08:09:20.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:09:20.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:09:20.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:09:20.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:09:20.89$vc4f8/vblo=2,640.99 2006.246.08:09:20.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:09:20.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:09:20.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:20.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:20.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:20.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:20.89#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:09:20.89#ibcon#first serial, iclass 13, count 0 2006.246.08:09:20.89#ibcon#enter sib2, iclass 13, count 0 2006.246.08:09:20.89#ibcon#flushed, iclass 13, count 0 2006.246.08:09:20.89#ibcon#about to write, iclass 13, count 0 2006.246.08:09:20.89#ibcon#wrote, iclass 13, count 0 2006.246.08:09:20.89#ibcon#about to read 3, iclass 13, count 0 2006.246.08:09:20.91#ibcon#read 3, iclass 13, count 0 2006.246.08:09:20.91#ibcon#about to read 4, iclass 13, count 0 2006.246.08:09:20.91#ibcon#read 4, iclass 13, count 0 2006.246.08:09:20.91#ibcon#about to read 5, iclass 13, count 0 2006.246.08:09:20.91#ibcon#read 5, iclass 13, count 0 2006.246.08:09:20.91#ibcon#about to read 6, iclass 13, count 0 2006.246.08:09:20.91#ibcon#read 6, iclass 13, count 0 2006.246.08:09:20.91#ibcon#end of sib2, iclass 13, count 0 2006.246.08:09:20.91#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:09:20.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:09:20.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:09:20.91#ibcon#*before write, iclass 13, count 0 2006.246.08:09:20.91#ibcon#enter sib2, iclass 13, count 0 2006.246.08:09:20.91#ibcon#flushed, iclass 13, count 0 2006.246.08:09:20.91#ibcon#about to write, iclass 13, count 0 2006.246.08:09:20.91#ibcon#wrote, iclass 13, count 0 2006.246.08:09:20.91#ibcon#about to read 3, iclass 13, count 0 2006.246.08:09:20.95#ibcon#read 3, iclass 13, count 0 2006.246.08:09:20.95#ibcon#about to read 4, iclass 13, count 0 2006.246.08:09:20.95#ibcon#read 4, iclass 13, count 0 2006.246.08:09:20.95#ibcon#about to read 5, iclass 13, count 0 2006.246.08:09:20.95#ibcon#read 5, iclass 13, count 0 2006.246.08:09:20.95#ibcon#about to read 6, iclass 13, count 0 2006.246.08:09:20.95#ibcon#read 6, iclass 13, count 0 2006.246.08:09:20.95#ibcon#end of sib2, iclass 13, count 0 2006.246.08:09:20.95#ibcon#*after write, iclass 13, count 0 2006.246.08:09:20.95#ibcon#*before return 0, iclass 13, count 0 2006.246.08:09:20.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:20.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:09:20.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:09:20.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:09:20.95$vc4f8/vb=2,4 2006.246.08:09:20.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.08:09:20.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.08:09:20.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:20.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:21.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:21.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:21.01#ibcon#enter wrdev, iclass 15, count 2 2006.246.08:09:21.01#ibcon#first serial, iclass 15, count 2 2006.246.08:09:21.01#ibcon#enter sib2, iclass 15, count 2 2006.246.08:09:21.01#ibcon#flushed, iclass 15, count 2 2006.246.08:09:21.01#ibcon#about to write, iclass 15, count 2 2006.246.08:09:21.01#ibcon#wrote, iclass 15, count 2 2006.246.08:09:21.01#ibcon#about to read 3, iclass 15, count 2 2006.246.08:09:21.03#ibcon#read 3, iclass 15, count 2 2006.246.08:09:21.03#ibcon#about to read 4, iclass 15, count 2 2006.246.08:09:21.03#ibcon#read 4, iclass 15, count 2 2006.246.08:09:21.03#ibcon#about to read 5, iclass 15, count 2 2006.246.08:09:21.03#ibcon#read 5, iclass 15, count 2 2006.246.08:09:21.03#ibcon#about to read 6, iclass 15, count 2 2006.246.08:09:21.03#ibcon#read 6, iclass 15, count 2 2006.246.08:09:21.03#ibcon#end of sib2, iclass 15, count 2 2006.246.08:09:21.03#ibcon#*mode == 0, iclass 15, count 2 2006.246.08:09:21.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.08:09:21.03#ibcon#[27=AT02-04\r\n] 2006.246.08:09:21.03#ibcon#*before write, iclass 15, count 2 2006.246.08:09:21.03#ibcon#enter sib2, iclass 15, count 2 2006.246.08:09:21.03#ibcon#flushed, iclass 15, count 2 2006.246.08:09:21.03#ibcon#about to write, iclass 15, count 2 2006.246.08:09:21.03#ibcon#wrote, iclass 15, count 2 2006.246.08:09:21.03#ibcon#about to read 3, iclass 15, count 2 2006.246.08:09:21.06#ibcon#read 3, iclass 15, count 2 2006.246.08:09:21.06#ibcon#about to read 4, iclass 15, count 2 2006.246.08:09:21.06#ibcon#read 4, iclass 15, count 2 2006.246.08:09:21.06#ibcon#about to read 5, iclass 15, count 2 2006.246.08:09:21.06#ibcon#read 5, iclass 15, count 2 2006.246.08:09:21.06#ibcon#about to read 6, iclass 15, count 2 2006.246.08:09:21.06#ibcon#read 6, iclass 15, count 2 2006.246.08:09:21.06#ibcon#end of sib2, iclass 15, count 2 2006.246.08:09:21.06#ibcon#*after write, iclass 15, count 2 2006.246.08:09:21.06#ibcon#*before return 0, iclass 15, count 2 2006.246.08:09:21.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:21.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:09:21.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.08:09:21.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:21.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:21.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:21.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:21.18#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:09:21.18#ibcon#first serial, iclass 15, count 0 2006.246.08:09:21.18#ibcon#enter sib2, iclass 15, count 0 2006.246.08:09:21.18#ibcon#flushed, iclass 15, count 0 2006.246.08:09:21.18#ibcon#about to write, iclass 15, count 0 2006.246.08:09:21.18#ibcon#wrote, iclass 15, count 0 2006.246.08:09:21.18#ibcon#about to read 3, iclass 15, count 0 2006.246.08:09:21.20#ibcon#read 3, iclass 15, count 0 2006.246.08:09:21.20#ibcon#about to read 4, iclass 15, count 0 2006.246.08:09:21.20#ibcon#read 4, iclass 15, count 0 2006.246.08:09:21.20#ibcon#about to read 5, iclass 15, count 0 2006.246.08:09:21.20#ibcon#read 5, iclass 15, count 0 2006.246.08:09:21.20#ibcon#about to read 6, iclass 15, count 0 2006.246.08:09:21.20#ibcon#read 6, iclass 15, count 0 2006.246.08:09:21.20#ibcon#end of sib2, iclass 15, count 0 2006.246.08:09:21.20#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:09:21.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:09:21.20#ibcon#[27=USB\r\n] 2006.246.08:09:21.20#ibcon#*before write, iclass 15, count 0 2006.246.08:09:21.20#ibcon#enter sib2, iclass 15, count 0 2006.246.08:09:21.20#ibcon#flushed, iclass 15, count 0 2006.246.08:09:21.20#ibcon#about to write, iclass 15, count 0 2006.246.08:09:21.20#ibcon#wrote, iclass 15, count 0 2006.246.08:09:21.20#ibcon#about to read 3, iclass 15, count 0 2006.246.08:09:21.23#ibcon#read 3, iclass 15, count 0 2006.246.08:09:21.23#ibcon#about to read 4, iclass 15, count 0 2006.246.08:09:21.23#ibcon#read 4, iclass 15, count 0 2006.246.08:09:21.23#ibcon#about to read 5, iclass 15, count 0 2006.246.08:09:21.23#ibcon#read 5, iclass 15, count 0 2006.246.08:09:21.23#ibcon#about to read 6, iclass 15, count 0 2006.246.08:09:21.23#ibcon#read 6, iclass 15, count 0 2006.246.08:09:21.23#ibcon#end of sib2, iclass 15, count 0 2006.246.08:09:21.23#ibcon#*after write, iclass 15, count 0 2006.246.08:09:21.23#ibcon#*before return 0, iclass 15, count 0 2006.246.08:09:21.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:21.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:09:21.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:09:21.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:09:21.23$vc4f8/vblo=3,656.99 2006.246.08:09:21.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.08:09:21.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.08:09:21.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:21.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:21.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:21.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:21.23#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:09:21.23#ibcon#first serial, iclass 17, count 0 2006.246.08:09:21.23#ibcon#enter sib2, iclass 17, count 0 2006.246.08:09:21.23#ibcon#flushed, iclass 17, count 0 2006.246.08:09:21.23#ibcon#about to write, iclass 17, count 0 2006.246.08:09:21.23#ibcon#wrote, iclass 17, count 0 2006.246.08:09:21.23#ibcon#about to read 3, iclass 17, count 0 2006.246.08:09:21.25#ibcon#read 3, iclass 17, count 0 2006.246.08:09:21.25#ibcon#about to read 4, iclass 17, count 0 2006.246.08:09:21.25#ibcon#read 4, iclass 17, count 0 2006.246.08:09:21.25#ibcon#about to read 5, iclass 17, count 0 2006.246.08:09:21.25#ibcon#read 5, iclass 17, count 0 2006.246.08:09:21.25#ibcon#about to read 6, iclass 17, count 0 2006.246.08:09:21.25#ibcon#read 6, iclass 17, count 0 2006.246.08:09:21.25#ibcon#end of sib2, iclass 17, count 0 2006.246.08:09:21.25#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:09:21.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:09:21.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:09:21.25#ibcon#*before write, iclass 17, count 0 2006.246.08:09:21.25#ibcon#enter sib2, iclass 17, count 0 2006.246.08:09:21.25#ibcon#flushed, iclass 17, count 0 2006.246.08:09:21.25#ibcon#about to write, iclass 17, count 0 2006.246.08:09:21.25#ibcon#wrote, iclass 17, count 0 2006.246.08:09:21.25#ibcon#about to read 3, iclass 17, count 0 2006.246.08:09:21.29#ibcon#read 3, iclass 17, count 0 2006.246.08:09:21.29#ibcon#about to read 4, iclass 17, count 0 2006.246.08:09:21.29#ibcon#read 4, iclass 17, count 0 2006.246.08:09:21.29#ibcon#about to read 5, iclass 17, count 0 2006.246.08:09:21.29#ibcon#read 5, iclass 17, count 0 2006.246.08:09:21.29#ibcon#about to read 6, iclass 17, count 0 2006.246.08:09:21.29#ibcon#read 6, iclass 17, count 0 2006.246.08:09:21.29#ibcon#end of sib2, iclass 17, count 0 2006.246.08:09:21.29#ibcon#*after write, iclass 17, count 0 2006.246.08:09:21.29#ibcon#*before return 0, iclass 17, count 0 2006.246.08:09:21.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:21.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:09:21.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:09:21.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:09:21.29$vc4f8/vb=3,4 2006.246.08:09:21.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.08:09:21.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.08:09:21.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:21.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:21.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:21.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:21.35#ibcon#enter wrdev, iclass 19, count 2 2006.246.08:09:21.35#ibcon#first serial, iclass 19, count 2 2006.246.08:09:21.35#ibcon#enter sib2, iclass 19, count 2 2006.246.08:09:21.35#ibcon#flushed, iclass 19, count 2 2006.246.08:09:21.35#ibcon#about to write, iclass 19, count 2 2006.246.08:09:21.35#ibcon#wrote, iclass 19, count 2 2006.246.08:09:21.35#ibcon#about to read 3, iclass 19, count 2 2006.246.08:09:21.37#ibcon#read 3, iclass 19, count 2 2006.246.08:09:21.37#ibcon#about to read 4, iclass 19, count 2 2006.246.08:09:21.37#ibcon#read 4, iclass 19, count 2 2006.246.08:09:21.37#ibcon#about to read 5, iclass 19, count 2 2006.246.08:09:21.37#ibcon#read 5, iclass 19, count 2 2006.246.08:09:21.37#ibcon#about to read 6, iclass 19, count 2 2006.246.08:09:21.37#ibcon#read 6, iclass 19, count 2 2006.246.08:09:21.37#ibcon#end of sib2, iclass 19, count 2 2006.246.08:09:21.37#ibcon#*mode == 0, iclass 19, count 2 2006.246.08:09:21.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.08:09:21.37#ibcon#[27=AT03-04\r\n] 2006.246.08:09:21.37#ibcon#*before write, iclass 19, count 2 2006.246.08:09:21.37#ibcon#enter sib2, iclass 19, count 2 2006.246.08:09:21.37#ibcon#flushed, iclass 19, count 2 2006.246.08:09:21.37#ibcon#about to write, iclass 19, count 2 2006.246.08:09:21.37#ibcon#wrote, iclass 19, count 2 2006.246.08:09:21.37#ibcon#about to read 3, iclass 19, count 2 2006.246.08:09:21.40#ibcon#read 3, iclass 19, count 2 2006.246.08:09:21.40#ibcon#about to read 4, iclass 19, count 2 2006.246.08:09:21.40#ibcon#read 4, iclass 19, count 2 2006.246.08:09:21.40#ibcon#about to read 5, iclass 19, count 2 2006.246.08:09:21.40#ibcon#read 5, iclass 19, count 2 2006.246.08:09:21.40#ibcon#about to read 6, iclass 19, count 2 2006.246.08:09:21.40#ibcon#read 6, iclass 19, count 2 2006.246.08:09:21.40#ibcon#end of sib2, iclass 19, count 2 2006.246.08:09:21.40#ibcon#*after write, iclass 19, count 2 2006.246.08:09:21.40#ibcon#*before return 0, iclass 19, count 2 2006.246.08:09:21.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:21.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:09:21.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.08:09:21.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:21.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:21.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:21.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:21.52#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:09:21.52#ibcon#first serial, iclass 19, count 0 2006.246.08:09:21.52#ibcon#enter sib2, iclass 19, count 0 2006.246.08:09:21.52#ibcon#flushed, iclass 19, count 0 2006.246.08:09:21.52#ibcon#about to write, iclass 19, count 0 2006.246.08:09:21.52#ibcon#wrote, iclass 19, count 0 2006.246.08:09:21.52#ibcon#about to read 3, iclass 19, count 0 2006.246.08:09:21.54#ibcon#read 3, iclass 19, count 0 2006.246.08:09:21.54#ibcon#about to read 4, iclass 19, count 0 2006.246.08:09:21.54#ibcon#read 4, iclass 19, count 0 2006.246.08:09:21.54#ibcon#about to read 5, iclass 19, count 0 2006.246.08:09:21.54#ibcon#read 5, iclass 19, count 0 2006.246.08:09:21.54#ibcon#about to read 6, iclass 19, count 0 2006.246.08:09:21.54#ibcon#read 6, iclass 19, count 0 2006.246.08:09:21.54#ibcon#end of sib2, iclass 19, count 0 2006.246.08:09:21.54#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:09:21.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:09:21.54#ibcon#[27=USB\r\n] 2006.246.08:09:21.54#ibcon#*before write, iclass 19, count 0 2006.246.08:09:21.54#ibcon#enter sib2, iclass 19, count 0 2006.246.08:09:21.54#ibcon#flushed, iclass 19, count 0 2006.246.08:09:21.54#ibcon#about to write, iclass 19, count 0 2006.246.08:09:21.54#ibcon#wrote, iclass 19, count 0 2006.246.08:09:21.54#ibcon#about to read 3, iclass 19, count 0 2006.246.08:09:21.57#ibcon#read 3, iclass 19, count 0 2006.246.08:09:21.57#ibcon#about to read 4, iclass 19, count 0 2006.246.08:09:21.57#ibcon#read 4, iclass 19, count 0 2006.246.08:09:21.57#ibcon#about to read 5, iclass 19, count 0 2006.246.08:09:21.57#ibcon#read 5, iclass 19, count 0 2006.246.08:09:21.57#ibcon#about to read 6, iclass 19, count 0 2006.246.08:09:21.57#ibcon#read 6, iclass 19, count 0 2006.246.08:09:21.57#ibcon#end of sib2, iclass 19, count 0 2006.246.08:09:21.57#ibcon#*after write, iclass 19, count 0 2006.246.08:09:21.57#ibcon#*before return 0, iclass 19, count 0 2006.246.08:09:21.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:21.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:09:21.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:09:21.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:09:21.57$vc4f8/vblo=4,712.99 2006.246.08:09:21.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.08:09:21.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.08:09:21.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:21.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:21.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:21.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:21.57#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:09:21.57#ibcon#first serial, iclass 21, count 0 2006.246.08:09:21.57#ibcon#enter sib2, iclass 21, count 0 2006.246.08:09:21.57#ibcon#flushed, iclass 21, count 0 2006.246.08:09:21.57#ibcon#about to write, iclass 21, count 0 2006.246.08:09:21.57#ibcon#wrote, iclass 21, count 0 2006.246.08:09:21.57#ibcon#about to read 3, iclass 21, count 0 2006.246.08:09:21.59#ibcon#read 3, iclass 21, count 0 2006.246.08:09:21.59#ibcon#about to read 4, iclass 21, count 0 2006.246.08:09:21.59#ibcon#read 4, iclass 21, count 0 2006.246.08:09:21.59#ibcon#about to read 5, iclass 21, count 0 2006.246.08:09:21.59#ibcon#read 5, iclass 21, count 0 2006.246.08:09:21.59#ibcon#about to read 6, iclass 21, count 0 2006.246.08:09:21.59#ibcon#read 6, iclass 21, count 0 2006.246.08:09:21.59#ibcon#end of sib2, iclass 21, count 0 2006.246.08:09:21.59#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:09:21.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:09:21.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:09:21.59#ibcon#*before write, iclass 21, count 0 2006.246.08:09:21.59#ibcon#enter sib2, iclass 21, count 0 2006.246.08:09:21.59#ibcon#flushed, iclass 21, count 0 2006.246.08:09:21.59#ibcon#about to write, iclass 21, count 0 2006.246.08:09:21.59#ibcon#wrote, iclass 21, count 0 2006.246.08:09:21.59#ibcon#about to read 3, iclass 21, count 0 2006.246.08:09:21.63#ibcon#read 3, iclass 21, count 0 2006.246.08:09:21.63#ibcon#about to read 4, iclass 21, count 0 2006.246.08:09:21.63#ibcon#read 4, iclass 21, count 0 2006.246.08:09:21.63#ibcon#about to read 5, iclass 21, count 0 2006.246.08:09:21.63#ibcon#read 5, iclass 21, count 0 2006.246.08:09:21.63#ibcon#about to read 6, iclass 21, count 0 2006.246.08:09:21.63#ibcon#read 6, iclass 21, count 0 2006.246.08:09:21.63#ibcon#end of sib2, iclass 21, count 0 2006.246.08:09:21.63#ibcon#*after write, iclass 21, count 0 2006.246.08:09:21.63#ibcon#*before return 0, iclass 21, count 0 2006.246.08:09:21.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:21.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:09:21.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:09:21.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:09:21.63$vc4f8/vb=4,4 2006.246.08:09:21.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.08:09:21.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.08:09:21.63#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:21.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:21.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:21.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:21.69#ibcon#enter wrdev, iclass 23, count 2 2006.246.08:09:21.69#ibcon#first serial, iclass 23, count 2 2006.246.08:09:21.69#ibcon#enter sib2, iclass 23, count 2 2006.246.08:09:21.69#ibcon#flushed, iclass 23, count 2 2006.246.08:09:21.69#ibcon#about to write, iclass 23, count 2 2006.246.08:09:21.69#ibcon#wrote, iclass 23, count 2 2006.246.08:09:21.69#ibcon#about to read 3, iclass 23, count 2 2006.246.08:09:21.71#ibcon#read 3, iclass 23, count 2 2006.246.08:09:21.71#ibcon#about to read 4, iclass 23, count 2 2006.246.08:09:21.71#ibcon#read 4, iclass 23, count 2 2006.246.08:09:21.71#ibcon#about to read 5, iclass 23, count 2 2006.246.08:09:21.71#ibcon#read 5, iclass 23, count 2 2006.246.08:09:21.71#ibcon#about to read 6, iclass 23, count 2 2006.246.08:09:21.71#ibcon#read 6, iclass 23, count 2 2006.246.08:09:21.71#ibcon#end of sib2, iclass 23, count 2 2006.246.08:09:21.71#ibcon#*mode == 0, iclass 23, count 2 2006.246.08:09:21.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.08:09:21.71#ibcon#[27=AT04-04\r\n] 2006.246.08:09:21.71#ibcon#*before write, iclass 23, count 2 2006.246.08:09:21.71#ibcon#enter sib2, iclass 23, count 2 2006.246.08:09:21.71#ibcon#flushed, iclass 23, count 2 2006.246.08:09:21.71#ibcon#about to write, iclass 23, count 2 2006.246.08:09:21.71#ibcon#wrote, iclass 23, count 2 2006.246.08:09:21.71#ibcon#about to read 3, iclass 23, count 2 2006.246.08:09:21.74#ibcon#read 3, iclass 23, count 2 2006.246.08:09:21.74#ibcon#about to read 4, iclass 23, count 2 2006.246.08:09:21.74#ibcon#read 4, iclass 23, count 2 2006.246.08:09:21.74#ibcon#about to read 5, iclass 23, count 2 2006.246.08:09:21.74#ibcon#read 5, iclass 23, count 2 2006.246.08:09:21.74#ibcon#about to read 6, iclass 23, count 2 2006.246.08:09:21.74#ibcon#read 6, iclass 23, count 2 2006.246.08:09:21.74#ibcon#end of sib2, iclass 23, count 2 2006.246.08:09:21.74#ibcon#*after write, iclass 23, count 2 2006.246.08:09:21.74#ibcon#*before return 0, iclass 23, count 2 2006.246.08:09:21.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:21.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:09:21.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.08:09:21.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:21.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:21.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:21.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:21.86#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:09:21.86#ibcon#first serial, iclass 23, count 0 2006.246.08:09:21.86#ibcon#enter sib2, iclass 23, count 0 2006.246.08:09:21.86#ibcon#flushed, iclass 23, count 0 2006.246.08:09:21.86#ibcon#about to write, iclass 23, count 0 2006.246.08:09:21.86#ibcon#wrote, iclass 23, count 0 2006.246.08:09:21.86#ibcon#about to read 3, iclass 23, count 0 2006.246.08:09:21.88#ibcon#read 3, iclass 23, count 0 2006.246.08:09:21.88#ibcon#about to read 4, iclass 23, count 0 2006.246.08:09:21.88#ibcon#read 4, iclass 23, count 0 2006.246.08:09:21.88#ibcon#about to read 5, iclass 23, count 0 2006.246.08:09:21.88#ibcon#read 5, iclass 23, count 0 2006.246.08:09:21.88#ibcon#about to read 6, iclass 23, count 0 2006.246.08:09:21.88#ibcon#read 6, iclass 23, count 0 2006.246.08:09:21.88#ibcon#end of sib2, iclass 23, count 0 2006.246.08:09:21.88#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:09:21.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:09:21.88#ibcon#[27=USB\r\n] 2006.246.08:09:21.88#ibcon#*before write, iclass 23, count 0 2006.246.08:09:21.88#ibcon#enter sib2, iclass 23, count 0 2006.246.08:09:21.88#ibcon#flushed, iclass 23, count 0 2006.246.08:09:21.88#ibcon#about to write, iclass 23, count 0 2006.246.08:09:21.88#ibcon#wrote, iclass 23, count 0 2006.246.08:09:21.88#ibcon#about to read 3, iclass 23, count 0 2006.246.08:09:21.91#ibcon#read 3, iclass 23, count 0 2006.246.08:09:21.91#ibcon#about to read 4, iclass 23, count 0 2006.246.08:09:21.91#ibcon#read 4, iclass 23, count 0 2006.246.08:09:21.91#ibcon#about to read 5, iclass 23, count 0 2006.246.08:09:21.91#ibcon#read 5, iclass 23, count 0 2006.246.08:09:21.91#ibcon#about to read 6, iclass 23, count 0 2006.246.08:09:21.91#ibcon#read 6, iclass 23, count 0 2006.246.08:09:21.91#ibcon#end of sib2, iclass 23, count 0 2006.246.08:09:21.91#ibcon#*after write, iclass 23, count 0 2006.246.08:09:21.91#ibcon#*before return 0, iclass 23, count 0 2006.246.08:09:21.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:21.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:09:21.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:09:21.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:09:21.91$vc4f8/vblo=5,744.99 2006.246.08:09:21.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.08:09:21.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.08:09:21.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:21.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:21.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:21.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:21.91#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:09:21.91#ibcon#first serial, iclass 25, count 0 2006.246.08:09:21.91#ibcon#enter sib2, iclass 25, count 0 2006.246.08:09:21.91#ibcon#flushed, iclass 25, count 0 2006.246.08:09:21.91#ibcon#about to write, iclass 25, count 0 2006.246.08:09:21.91#ibcon#wrote, iclass 25, count 0 2006.246.08:09:21.91#ibcon#about to read 3, iclass 25, count 0 2006.246.08:09:21.93#ibcon#read 3, iclass 25, count 0 2006.246.08:09:21.93#ibcon#about to read 4, iclass 25, count 0 2006.246.08:09:21.93#ibcon#read 4, iclass 25, count 0 2006.246.08:09:21.93#ibcon#about to read 5, iclass 25, count 0 2006.246.08:09:21.93#ibcon#read 5, iclass 25, count 0 2006.246.08:09:21.93#ibcon#about to read 6, iclass 25, count 0 2006.246.08:09:21.93#ibcon#read 6, iclass 25, count 0 2006.246.08:09:21.93#ibcon#end of sib2, iclass 25, count 0 2006.246.08:09:21.93#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:09:21.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:09:21.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:09:21.93#ibcon#*before write, iclass 25, count 0 2006.246.08:09:21.93#ibcon#enter sib2, iclass 25, count 0 2006.246.08:09:21.93#ibcon#flushed, iclass 25, count 0 2006.246.08:09:21.93#ibcon#about to write, iclass 25, count 0 2006.246.08:09:21.93#ibcon#wrote, iclass 25, count 0 2006.246.08:09:21.93#ibcon#about to read 3, iclass 25, count 0 2006.246.08:09:21.97#ibcon#read 3, iclass 25, count 0 2006.246.08:09:21.97#ibcon#about to read 4, iclass 25, count 0 2006.246.08:09:21.97#ibcon#read 4, iclass 25, count 0 2006.246.08:09:21.97#ibcon#about to read 5, iclass 25, count 0 2006.246.08:09:21.97#ibcon#read 5, iclass 25, count 0 2006.246.08:09:21.97#ibcon#about to read 6, iclass 25, count 0 2006.246.08:09:21.97#ibcon#read 6, iclass 25, count 0 2006.246.08:09:21.97#ibcon#end of sib2, iclass 25, count 0 2006.246.08:09:21.97#ibcon#*after write, iclass 25, count 0 2006.246.08:09:21.97#ibcon#*before return 0, iclass 25, count 0 2006.246.08:09:21.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:21.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:09:21.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:09:21.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:09:21.97$vc4f8/vb=5,3 2006.246.08:09:21.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.08:09:21.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.08:09:21.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:21.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:22.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:22.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:22.03#ibcon#enter wrdev, iclass 27, count 2 2006.246.08:09:22.03#ibcon#first serial, iclass 27, count 2 2006.246.08:09:22.03#ibcon#enter sib2, iclass 27, count 2 2006.246.08:09:22.03#ibcon#flushed, iclass 27, count 2 2006.246.08:09:22.03#ibcon#about to write, iclass 27, count 2 2006.246.08:09:22.03#ibcon#wrote, iclass 27, count 2 2006.246.08:09:22.03#ibcon#about to read 3, iclass 27, count 2 2006.246.08:09:22.05#ibcon#read 3, iclass 27, count 2 2006.246.08:09:22.05#ibcon#about to read 4, iclass 27, count 2 2006.246.08:09:22.05#ibcon#read 4, iclass 27, count 2 2006.246.08:09:22.05#ibcon#about to read 5, iclass 27, count 2 2006.246.08:09:22.05#ibcon#read 5, iclass 27, count 2 2006.246.08:09:22.05#ibcon#about to read 6, iclass 27, count 2 2006.246.08:09:22.05#ibcon#read 6, iclass 27, count 2 2006.246.08:09:22.05#ibcon#end of sib2, iclass 27, count 2 2006.246.08:09:22.05#ibcon#*mode == 0, iclass 27, count 2 2006.246.08:09:22.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.08:09:22.05#ibcon#[27=AT05-03\r\n] 2006.246.08:09:22.05#ibcon#*before write, iclass 27, count 2 2006.246.08:09:22.05#ibcon#enter sib2, iclass 27, count 2 2006.246.08:09:22.05#ibcon#flushed, iclass 27, count 2 2006.246.08:09:22.05#ibcon#about to write, iclass 27, count 2 2006.246.08:09:22.05#ibcon#wrote, iclass 27, count 2 2006.246.08:09:22.05#ibcon#about to read 3, iclass 27, count 2 2006.246.08:09:22.08#ibcon#read 3, iclass 27, count 2 2006.246.08:09:22.08#ibcon#about to read 4, iclass 27, count 2 2006.246.08:09:22.08#ibcon#read 4, iclass 27, count 2 2006.246.08:09:22.08#ibcon#about to read 5, iclass 27, count 2 2006.246.08:09:22.08#ibcon#read 5, iclass 27, count 2 2006.246.08:09:22.08#ibcon#about to read 6, iclass 27, count 2 2006.246.08:09:22.08#ibcon#read 6, iclass 27, count 2 2006.246.08:09:22.08#ibcon#end of sib2, iclass 27, count 2 2006.246.08:09:22.08#ibcon#*after write, iclass 27, count 2 2006.246.08:09:22.08#ibcon#*before return 0, iclass 27, count 2 2006.246.08:09:22.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:22.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:09:22.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.08:09:22.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:22.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:22.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:22.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:22.20#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:09:22.20#ibcon#first serial, iclass 27, count 0 2006.246.08:09:22.20#ibcon#enter sib2, iclass 27, count 0 2006.246.08:09:22.20#ibcon#flushed, iclass 27, count 0 2006.246.08:09:22.20#ibcon#about to write, iclass 27, count 0 2006.246.08:09:22.20#ibcon#wrote, iclass 27, count 0 2006.246.08:09:22.20#ibcon#about to read 3, iclass 27, count 0 2006.246.08:09:22.22#ibcon#read 3, iclass 27, count 0 2006.246.08:09:22.22#ibcon#about to read 4, iclass 27, count 0 2006.246.08:09:22.22#ibcon#read 4, iclass 27, count 0 2006.246.08:09:22.22#ibcon#about to read 5, iclass 27, count 0 2006.246.08:09:22.22#ibcon#read 5, iclass 27, count 0 2006.246.08:09:22.22#ibcon#about to read 6, iclass 27, count 0 2006.246.08:09:22.22#ibcon#read 6, iclass 27, count 0 2006.246.08:09:22.22#ibcon#end of sib2, iclass 27, count 0 2006.246.08:09:22.22#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:09:22.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:09:22.22#ibcon#[27=USB\r\n] 2006.246.08:09:22.22#ibcon#*before write, iclass 27, count 0 2006.246.08:09:22.22#ibcon#enter sib2, iclass 27, count 0 2006.246.08:09:22.22#ibcon#flushed, iclass 27, count 0 2006.246.08:09:22.22#ibcon#about to write, iclass 27, count 0 2006.246.08:09:22.22#ibcon#wrote, iclass 27, count 0 2006.246.08:09:22.22#ibcon#about to read 3, iclass 27, count 0 2006.246.08:09:22.25#ibcon#read 3, iclass 27, count 0 2006.246.08:09:22.25#ibcon#about to read 4, iclass 27, count 0 2006.246.08:09:22.25#ibcon#read 4, iclass 27, count 0 2006.246.08:09:22.25#ibcon#about to read 5, iclass 27, count 0 2006.246.08:09:22.25#ibcon#read 5, iclass 27, count 0 2006.246.08:09:22.25#ibcon#about to read 6, iclass 27, count 0 2006.246.08:09:22.25#ibcon#read 6, iclass 27, count 0 2006.246.08:09:22.25#ibcon#end of sib2, iclass 27, count 0 2006.246.08:09:22.25#ibcon#*after write, iclass 27, count 0 2006.246.08:09:22.25#ibcon#*before return 0, iclass 27, count 0 2006.246.08:09:22.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:22.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:09:22.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:09:22.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:09:22.25$vc4f8/vblo=6,752.99 2006.246.08:09:22.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.08:09:22.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.08:09:22.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:09:22.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:22.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:22.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:22.25#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:09:22.25#ibcon#first serial, iclass 29, count 0 2006.246.08:09:22.25#ibcon#enter sib2, iclass 29, count 0 2006.246.08:09:22.25#ibcon#flushed, iclass 29, count 0 2006.246.08:09:22.25#ibcon#about to write, iclass 29, count 0 2006.246.08:09:22.25#ibcon#wrote, iclass 29, count 0 2006.246.08:09:22.25#ibcon#about to read 3, iclass 29, count 0 2006.246.08:09:22.27#ibcon#read 3, iclass 29, count 0 2006.246.08:09:22.27#ibcon#about to read 4, iclass 29, count 0 2006.246.08:09:22.27#ibcon#read 4, iclass 29, count 0 2006.246.08:09:22.27#ibcon#about to read 5, iclass 29, count 0 2006.246.08:09:22.27#ibcon#read 5, iclass 29, count 0 2006.246.08:09:22.27#ibcon#about to read 6, iclass 29, count 0 2006.246.08:09:22.27#ibcon#read 6, iclass 29, count 0 2006.246.08:09:22.27#ibcon#end of sib2, iclass 29, count 0 2006.246.08:09:22.27#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:09:22.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:09:22.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:09:22.27#ibcon#*before write, iclass 29, count 0 2006.246.08:09:22.27#ibcon#enter sib2, iclass 29, count 0 2006.246.08:09:22.27#ibcon#flushed, iclass 29, count 0 2006.246.08:09:22.27#ibcon#about to write, iclass 29, count 0 2006.246.08:09:22.27#ibcon#wrote, iclass 29, count 0 2006.246.08:09:22.27#ibcon#about to read 3, iclass 29, count 0 2006.246.08:09:22.31#ibcon#read 3, iclass 29, count 0 2006.246.08:09:22.31#ibcon#about to read 4, iclass 29, count 0 2006.246.08:09:22.31#ibcon#read 4, iclass 29, count 0 2006.246.08:09:22.31#ibcon#about to read 5, iclass 29, count 0 2006.246.08:09:22.31#ibcon#read 5, iclass 29, count 0 2006.246.08:09:22.31#ibcon#about to read 6, iclass 29, count 0 2006.246.08:09:22.31#ibcon#read 6, iclass 29, count 0 2006.246.08:09:22.31#ibcon#end of sib2, iclass 29, count 0 2006.246.08:09:22.31#ibcon#*after write, iclass 29, count 0 2006.246.08:09:22.31#ibcon#*before return 0, iclass 29, count 0 2006.246.08:09:22.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:22.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:09:22.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:09:22.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:09:22.31$vc4f8/vb=6,3 2006.246.08:09:22.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.08:09:22.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.08:09:22.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:09:22.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:22.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:22.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:22.37#ibcon#enter wrdev, iclass 31, count 2 2006.246.08:09:22.37#ibcon#first serial, iclass 31, count 2 2006.246.08:09:22.37#ibcon#enter sib2, iclass 31, count 2 2006.246.08:09:22.37#ibcon#flushed, iclass 31, count 2 2006.246.08:09:22.37#ibcon#about to write, iclass 31, count 2 2006.246.08:09:22.37#ibcon#wrote, iclass 31, count 2 2006.246.08:09:22.37#ibcon#about to read 3, iclass 31, count 2 2006.246.08:09:22.39#ibcon#read 3, iclass 31, count 2 2006.246.08:09:22.39#ibcon#about to read 4, iclass 31, count 2 2006.246.08:09:22.39#ibcon#read 4, iclass 31, count 2 2006.246.08:09:22.39#ibcon#about to read 5, iclass 31, count 2 2006.246.08:09:22.39#ibcon#read 5, iclass 31, count 2 2006.246.08:09:22.39#ibcon#about to read 6, iclass 31, count 2 2006.246.08:09:22.39#ibcon#read 6, iclass 31, count 2 2006.246.08:09:22.39#ibcon#end of sib2, iclass 31, count 2 2006.246.08:09:22.39#ibcon#*mode == 0, iclass 31, count 2 2006.246.08:09:22.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.08:09:22.39#ibcon#[27=AT06-03\r\n] 2006.246.08:09:22.39#ibcon#*before write, iclass 31, count 2 2006.246.08:09:22.39#ibcon#enter sib2, iclass 31, count 2 2006.246.08:09:22.39#ibcon#flushed, iclass 31, count 2 2006.246.08:09:22.39#ibcon#about to write, iclass 31, count 2 2006.246.08:09:22.39#ibcon#wrote, iclass 31, count 2 2006.246.08:09:22.39#ibcon#about to read 3, iclass 31, count 2 2006.246.08:09:22.42#ibcon#read 3, iclass 31, count 2 2006.246.08:09:22.42#ibcon#about to read 4, iclass 31, count 2 2006.246.08:09:22.42#ibcon#read 4, iclass 31, count 2 2006.246.08:09:22.42#ibcon#about to read 5, iclass 31, count 2 2006.246.08:09:22.42#ibcon#read 5, iclass 31, count 2 2006.246.08:09:22.42#ibcon#about to read 6, iclass 31, count 2 2006.246.08:09:22.42#ibcon#read 6, iclass 31, count 2 2006.246.08:09:22.42#ibcon#end of sib2, iclass 31, count 2 2006.246.08:09:22.42#ibcon#*after write, iclass 31, count 2 2006.246.08:09:22.42#ibcon#*before return 0, iclass 31, count 2 2006.246.08:09:22.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:22.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:09:22.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.08:09:22.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:09:22.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:22.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:22.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:22.54#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:09:22.54#ibcon#first serial, iclass 31, count 0 2006.246.08:09:22.54#ibcon#enter sib2, iclass 31, count 0 2006.246.08:09:22.54#ibcon#flushed, iclass 31, count 0 2006.246.08:09:22.54#ibcon#about to write, iclass 31, count 0 2006.246.08:09:22.54#ibcon#wrote, iclass 31, count 0 2006.246.08:09:22.54#ibcon#about to read 3, iclass 31, count 0 2006.246.08:09:22.56#ibcon#read 3, iclass 31, count 0 2006.246.08:09:22.56#ibcon#about to read 4, iclass 31, count 0 2006.246.08:09:22.56#ibcon#read 4, iclass 31, count 0 2006.246.08:09:22.56#ibcon#about to read 5, iclass 31, count 0 2006.246.08:09:22.56#ibcon#read 5, iclass 31, count 0 2006.246.08:09:22.56#ibcon#about to read 6, iclass 31, count 0 2006.246.08:09:22.56#ibcon#read 6, iclass 31, count 0 2006.246.08:09:22.56#ibcon#end of sib2, iclass 31, count 0 2006.246.08:09:22.56#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:09:22.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:09:22.56#ibcon#[27=USB\r\n] 2006.246.08:09:22.56#ibcon#*before write, iclass 31, count 0 2006.246.08:09:22.56#ibcon#enter sib2, iclass 31, count 0 2006.246.08:09:22.56#ibcon#flushed, iclass 31, count 0 2006.246.08:09:22.56#ibcon#about to write, iclass 31, count 0 2006.246.08:09:22.56#ibcon#wrote, iclass 31, count 0 2006.246.08:09:22.56#ibcon#about to read 3, iclass 31, count 0 2006.246.08:09:22.59#ibcon#read 3, iclass 31, count 0 2006.246.08:09:22.59#ibcon#about to read 4, iclass 31, count 0 2006.246.08:09:22.59#ibcon#read 4, iclass 31, count 0 2006.246.08:09:22.59#ibcon#about to read 5, iclass 31, count 0 2006.246.08:09:22.59#ibcon#read 5, iclass 31, count 0 2006.246.08:09:22.59#ibcon#about to read 6, iclass 31, count 0 2006.246.08:09:22.59#ibcon#read 6, iclass 31, count 0 2006.246.08:09:22.59#ibcon#end of sib2, iclass 31, count 0 2006.246.08:09:22.59#ibcon#*after write, iclass 31, count 0 2006.246.08:09:22.59#ibcon#*before return 0, iclass 31, count 0 2006.246.08:09:22.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:22.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:09:22.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:09:22.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:09:22.59$vc4f8/vabw=wide 2006.246.08:09:22.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.08:09:22.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.08:09:22.59#ibcon#ireg 8 cls_cnt 0 2006.246.08:09:22.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:22.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:22.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:22.59#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:09:22.59#ibcon#first serial, iclass 33, count 0 2006.246.08:09:22.59#ibcon#enter sib2, iclass 33, count 0 2006.246.08:09:22.59#ibcon#flushed, iclass 33, count 0 2006.246.08:09:22.59#ibcon#about to write, iclass 33, count 0 2006.246.08:09:22.59#ibcon#wrote, iclass 33, count 0 2006.246.08:09:22.59#ibcon#about to read 3, iclass 33, count 0 2006.246.08:09:22.61#ibcon#read 3, iclass 33, count 0 2006.246.08:09:22.61#ibcon#about to read 4, iclass 33, count 0 2006.246.08:09:22.61#ibcon#read 4, iclass 33, count 0 2006.246.08:09:22.61#ibcon#about to read 5, iclass 33, count 0 2006.246.08:09:22.61#ibcon#read 5, iclass 33, count 0 2006.246.08:09:22.61#ibcon#about to read 6, iclass 33, count 0 2006.246.08:09:22.61#ibcon#read 6, iclass 33, count 0 2006.246.08:09:22.61#ibcon#end of sib2, iclass 33, count 0 2006.246.08:09:22.61#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:09:22.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:09:22.61#ibcon#[25=BW32\r\n] 2006.246.08:09:22.61#ibcon#*before write, iclass 33, count 0 2006.246.08:09:22.61#ibcon#enter sib2, iclass 33, count 0 2006.246.08:09:22.61#ibcon#flushed, iclass 33, count 0 2006.246.08:09:22.61#ibcon#about to write, iclass 33, count 0 2006.246.08:09:22.61#ibcon#wrote, iclass 33, count 0 2006.246.08:09:22.61#ibcon#about to read 3, iclass 33, count 0 2006.246.08:09:22.64#ibcon#read 3, iclass 33, count 0 2006.246.08:09:22.64#ibcon#about to read 4, iclass 33, count 0 2006.246.08:09:22.64#ibcon#read 4, iclass 33, count 0 2006.246.08:09:22.64#ibcon#about to read 5, iclass 33, count 0 2006.246.08:09:22.64#ibcon#read 5, iclass 33, count 0 2006.246.08:09:22.64#ibcon#about to read 6, iclass 33, count 0 2006.246.08:09:22.64#ibcon#read 6, iclass 33, count 0 2006.246.08:09:22.64#ibcon#end of sib2, iclass 33, count 0 2006.246.08:09:22.64#ibcon#*after write, iclass 33, count 0 2006.246.08:09:22.64#ibcon#*before return 0, iclass 33, count 0 2006.246.08:09:22.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:22.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:09:22.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:09:22.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:09:22.64$vc4f8/vbbw=wide 2006.246.08:09:22.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:09:22.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:09:22.64#ibcon#ireg 8 cls_cnt 0 2006.246.08:09:22.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:09:22.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:09:22.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:09:22.71#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:09:22.71#ibcon#first serial, iclass 35, count 0 2006.246.08:09:22.71#ibcon#enter sib2, iclass 35, count 0 2006.246.08:09:22.71#ibcon#flushed, iclass 35, count 0 2006.246.08:09:22.71#ibcon#about to write, iclass 35, count 0 2006.246.08:09:22.71#ibcon#wrote, iclass 35, count 0 2006.246.08:09:22.71#ibcon#about to read 3, iclass 35, count 0 2006.246.08:09:22.73#ibcon#read 3, iclass 35, count 0 2006.246.08:09:22.73#ibcon#about to read 4, iclass 35, count 0 2006.246.08:09:22.73#ibcon#read 4, iclass 35, count 0 2006.246.08:09:22.73#ibcon#about to read 5, iclass 35, count 0 2006.246.08:09:22.73#ibcon#read 5, iclass 35, count 0 2006.246.08:09:22.73#ibcon#about to read 6, iclass 35, count 0 2006.246.08:09:22.73#ibcon#read 6, iclass 35, count 0 2006.246.08:09:22.73#ibcon#end of sib2, iclass 35, count 0 2006.246.08:09:22.73#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:09:22.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:09:22.73#ibcon#[27=BW32\r\n] 2006.246.08:09:22.73#ibcon#*before write, iclass 35, count 0 2006.246.08:09:22.73#ibcon#enter sib2, iclass 35, count 0 2006.246.08:09:22.73#ibcon#flushed, iclass 35, count 0 2006.246.08:09:22.73#ibcon#about to write, iclass 35, count 0 2006.246.08:09:22.73#ibcon#wrote, iclass 35, count 0 2006.246.08:09:22.73#ibcon#about to read 3, iclass 35, count 0 2006.246.08:09:22.76#ibcon#read 3, iclass 35, count 0 2006.246.08:09:22.76#ibcon#about to read 4, iclass 35, count 0 2006.246.08:09:22.76#ibcon#read 4, iclass 35, count 0 2006.246.08:09:22.76#ibcon#about to read 5, iclass 35, count 0 2006.246.08:09:22.76#ibcon#read 5, iclass 35, count 0 2006.246.08:09:22.76#ibcon#about to read 6, iclass 35, count 0 2006.246.08:09:22.76#ibcon#read 6, iclass 35, count 0 2006.246.08:09:22.76#ibcon#end of sib2, iclass 35, count 0 2006.246.08:09:22.76#ibcon#*after write, iclass 35, count 0 2006.246.08:09:22.76#ibcon#*before return 0, iclass 35, count 0 2006.246.08:09:22.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:09:22.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:09:22.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:09:22.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:09:22.76$4f8m12a/ifd4f 2006.246.08:09:22.76$ifd4f/lo= 2006.246.08:09:22.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:09:22.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:09:22.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:09:22.76$ifd4f/patch= 2006.246.08:09:22.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:09:22.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:09:22.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:09:22.76$4f8m12a/"form=m,16.000,1:2 2006.246.08:09:22.76$4f8m12a/"tpicd 2006.246.08:09:22.76$4f8m12a/echo=off 2006.246.08:09:22.76$4f8m12a/xlog=off 2006.246.08:09:22.76:!2006.246.08:09:50 2006.246.08:09:34.14#trakl#Source acquired 2006.246.08:09:35.14#flagr#flagr/antenna,acquired 2006.246.08:09:50.00:preob 2006.246.08:09:51.13/onsource/TRACKING 2006.246.08:09:51.13:!2006.246.08:10:00 2006.246.08:10:00.00:data_valid=on 2006.246.08:10:00.00:midob 2006.246.08:10:00.13/onsource/TRACKING 2006.246.08:10:00.13/wx/26.45,1005.6,75 2006.246.08:10:00.30/cable/+6.4131E-03 2006.246.08:10:01.39/va/01,08,usb,yes,30,32 2006.246.08:10:01.39/va/02,07,usb,yes,30,32 2006.246.08:10:01.39/va/03,06,usb,yes,32,32 2006.246.08:10:01.39/va/04,07,usb,yes,31,34 2006.246.08:10:01.39/va/05,07,usb,yes,34,36 2006.246.08:10:01.39/va/06,07,usb,yes,29,29 2006.246.08:10:01.39/va/07,07,usb,yes,29,29 2006.246.08:10:01.39/va/08,08,usb,yes,26,25 2006.246.08:10:01.62/valo/01,532.99,yes,locked 2006.246.08:10:01.62/valo/02,572.99,yes,locked 2006.246.08:10:01.62/valo/03,672.99,yes,locked 2006.246.08:10:01.62/valo/04,832.99,yes,locked 2006.246.08:10:01.62/valo/05,652.99,yes,locked 2006.246.08:10:01.62/valo/06,772.99,yes,locked 2006.246.08:10:01.62/valo/07,832.99,yes,locked 2006.246.08:10:01.62/valo/08,852.99,yes,locked 2006.246.08:10:02.71/vb/01,04,usb,yes,30,29 2006.246.08:10:02.71/vb/02,04,usb,yes,32,34 2006.246.08:10:02.71/vb/03,04,usb,yes,28,32 2006.246.08:10:02.71/vb/04,04,usb,yes,29,29 2006.246.08:10:02.71/vb/05,03,usb,yes,35,39 2006.246.08:10:02.71/vb/06,03,usb,yes,35,39 2006.246.08:10:02.71/vb/07,04,usb,yes,31,31 2006.246.08:10:02.71/vb/08,03,usb,yes,35,39 2006.246.08:10:02.94/vblo/01,632.99,yes,locked 2006.246.08:10:02.94/vblo/02,640.99,yes,locked 2006.246.08:10:02.94/vblo/03,656.99,yes,locked 2006.246.08:10:02.94/vblo/04,712.99,yes,locked 2006.246.08:10:02.94/vblo/05,744.99,yes,locked 2006.246.08:10:02.94/vblo/06,752.99,yes,locked 2006.246.08:10:02.94/vblo/07,734.99,yes,locked 2006.246.08:10:02.94/vblo/08,744.99,yes,locked 2006.246.08:10:03.09/vabw/8 2006.246.08:10:03.24/vbbw/8 2006.246.08:10:03.33/xfe/off,on,13.2 2006.246.08:10:03.70/ifatt/23,28,28,28 2006.246.08:10:04.08/fmout-gps/S +4.39E-07 2006.246.08:10:04.12:!2006.246.08:11:00 2006.246.08:11:00.00:data_valid=off 2006.246.08:11:00.00:postob 2006.246.08:11:00.18/cable/+6.4131E-03 2006.246.08:11:00.18/wx/26.43,1005.6,75 2006.246.08:11:01.08/fmout-gps/S +4.39E-07 2006.246.08:11:01.08:scan_name=246-0812,k06246,70 2006.246.08:11:01.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.246.08:11:01.13#flagr#flagr/antenna,new-source 2006.246.08:11:02.13:checkk5 2006.246.08:11:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:11:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:11:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:11:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:11:03.99/chk_obsdata//k5ts1/T2460810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:11:04.36/chk_obsdata//k5ts2/T2460810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:11:04.73/chk_obsdata//k5ts3/T2460810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:11:05.10/chk_obsdata//k5ts4/T2460810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:11:05.80/k5log//k5ts1_log_newline 2006.246.08:11:06.51/k5log//k5ts2_log_newline 2006.246.08:11:07.20/k5log//k5ts3_log_newline 2006.246.08:11:07.89/k5log//k5ts4_log_newline 2006.246.08:11:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:11:07.91:4f8m12a=2 2006.246.08:11:07.91$4f8m12a/echo=on 2006.246.08:11:07.91$4f8m12a/pcalon 2006.246.08:11:07.91$pcalon/"no phase cal control is implemented here 2006.246.08:11:07.91$4f8m12a/"tpicd=stop 2006.246.08:11:07.91$4f8m12a/vc4f8 2006.246.08:11:07.91$vc4f8/valo=1,532.99 2006.246.08:11:07.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.08:11:07.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.08:11:07.92#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:07.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:07.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:07.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:07.92#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:11:07.92#ibcon#first serial, iclass 10, count 0 2006.246.08:11:07.92#ibcon#enter sib2, iclass 10, count 0 2006.246.08:11:07.92#ibcon#flushed, iclass 10, count 0 2006.246.08:11:07.92#ibcon#about to write, iclass 10, count 0 2006.246.08:11:07.92#ibcon#wrote, iclass 10, count 0 2006.246.08:11:07.92#ibcon#about to read 3, iclass 10, count 0 2006.246.08:11:07.96#ibcon#read 3, iclass 10, count 0 2006.246.08:11:07.96#ibcon#about to read 4, iclass 10, count 0 2006.246.08:11:07.96#ibcon#read 4, iclass 10, count 0 2006.246.08:11:07.96#ibcon#about to read 5, iclass 10, count 0 2006.246.08:11:07.96#ibcon#read 5, iclass 10, count 0 2006.246.08:11:07.96#ibcon#about to read 6, iclass 10, count 0 2006.246.08:11:07.96#ibcon#read 6, iclass 10, count 0 2006.246.08:11:07.96#ibcon#end of sib2, iclass 10, count 0 2006.246.08:11:07.96#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:11:07.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:11:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:11:07.96#ibcon#*before write, iclass 10, count 0 2006.246.08:11:07.96#ibcon#enter sib2, iclass 10, count 0 2006.246.08:11:07.96#ibcon#flushed, iclass 10, count 0 2006.246.08:11:07.96#ibcon#about to write, iclass 10, count 0 2006.246.08:11:07.96#ibcon#wrote, iclass 10, count 0 2006.246.08:11:07.96#ibcon#about to read 3, iclass 10, count 0 2006.246.08:11:08.01#ibcon#read 3, iclass 10, count 0 2006.246.08:11:08.01#ibcon#about to read 4, iclass 10, count 0 2006.246.08:11:08.01#ibcon#read 4, iclass 10, count 0 2006.246.08:11:08.01#ibcon#about to read 5, iclass 10, count 0 2006.246.08:11:08.01#ibcon#read 5, iclass 10, count 0 2006.246.08:11:08.01#ibcon#about to read 6, iclass 10, count 0 2006.246.08:11:08.01#ibcon#read 6, iclass 10, count 0 2006.246.08:11:08.01#ibcon#end of sib2, iclass 10, count 0 2006.246.08:11:08.01#ibcon#*after write, iclass 10, count 0 2006.246.08:11:08.01#ibcon#*before return 0, iclass 10, count 0 2006.246.08:11:08.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:08.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:08.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:11:08.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:11:08.01$vc4f8/va=1,8 2006.246.08:11:08.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.08:11:08.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.08:11:08.01#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:08.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:08.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:08.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:08.01#ibcon#enter wrdev, iclass 12, count 2 2006.246.08:11:08.01#ibcon#first serial, iclass 12, count 2 2006.246.08:11:08.01#ibcon#enter sib2, iclass 12, count 2 2006.246.08:11:08.01#ibcon#flushed, iclass 12, count 2 2006.246.08:11:08.01#ibcon#about to write, iclass 12, count 2 2006.246.08:11:08.01#ibcon#wrote, iclass 12, count 2 2006.246.08:11:08.01#ibcon#about to read 3, iclass 12, count 2 2006.246.08:11:08.03#ibcon#read 3, iclass 12, count 2 2006.246.08:11:08.03#ibcon#about to read 4, iclass 12, count 2 2006.246.08:11:08.03#ibcon#read 4, iclass 12, count 2 2006.246.08:11:08.03#ibcon#about to read 5, iclass 12, count 2 2006.246.08:11:08.03#ibcon#read 5, iclass 12, count 2 2006.246.08:11:08.03#ibcon#about to read 6, iclass 12, count 2 2006.246.08:11:08.03#ibcon#read 6, iclass 12, count 2 2006.246.08:11:08.03#ibcon#end of sib2, iclass 12, count 2 2006.246.08:11:08.03#ibcon#*mode == 0, iclass 12, count 2 2006.246.08:11:08.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.08:11:08.03#ibcon#[25=AT01-08\r\n] 2006.246.08:11:08.03#ibcon#*before write, iclass 12, count 2 2006.246.08:11:08.03#ibcon#enter sib2, iclass 12, count 2 2006.246.08:11:08.03#ibcon#flushed, iclass 12, count 2 2006.246.08:11:08.03#ibcon#about to write, iclass 12, count 2 2006.246.08:11:08.03#ibcon#wrote, iclass 12, count 2 2006.246.08:11:08.03#ibcon#about to read 3, iclass 12, count 2 2006.246.08:11:08.07#ibcon#read 3, iclass 12, count 2 2006.246.08:11:08.07#ibcon#about to read 4, iclass 12, count 2 2006.246.08:11:08.07#ibcon#read 4, iclass 12, count 2 2006.246.08:11:08.07#ibcon#about to read 5, iclass 12, count 2 2006.246.08:11:08.07#ibcon#read 5, iclass 12, count 2 2006.246.08:11:08.07#ibcon#about to read 6, iclass 12, count 2 2006.246.08:11:08.07#ibcon#read 6, iclass 12, count 2 2006.246.08:11:08.07#ibcon#end of sib2, iclass 12, count 2 2006.246.08:11:08.07#ibcon#*after write, iclass 12, count 2 2006.246.08:11:08.07#ibcon#*before return 0, iclass 12, count 2 2006.246.08:11:08.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:08.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:08.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.08:11:08.07#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:08.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:08.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:08.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:08.19#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:11:08.19#ibcon#first serial, iclass 12, count 0 2006.246.08:11:08.19#ibcon#enter sib2, iclass 12, count 0 2006.246.08:11:08.19#ibcon#flushed, iclass 12, count 0 2006.246.08:11:08.19#ibcon#about to write, iclass 12, count 0 2006.246.08:11:08.19#ibcon#wrote, iclass 12, count 0 2006.246.08:11:08.19#ibcon#about to read 3, iclass 12, count 0 2006.246.08:11:08.21#ibcon#read 3, iclass 12, count 0 2006.246.08:11:08.21#ibcon#about to read 4, iclass 12, count 0 2006.246.08:11:08.21#ibcon#read 4, iclass 12, count 0 2006.246.08:11:08.21#ibcon#about to read 5, iclass 12, count 0 2006.246.08:11:08.21#ibcon#read 5, iclass 12, count 0 2006.246.08:11:08.21#ibcon#about to read 6, iclass 12, count 0 2006.246.08:11:08.21#ibcon#read 6, iclass 12, count 0 2006.246.08:11:08.21#ibcon#end of sib2, iclass 12, count 0 2006.246.08:11:08.21#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:11:08.21#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:11:08.21#ibcon#[25=USB\r\n] 2006.246.08:11:08.21#ibcon#*before write, iclass 12, count 0 2006.246.08:11:08.21#ibcon#enter sib2, iclass 12, count 0 2006.246.08:11:08.21#ibcon#flushed, iclass 12, count 0 2006.246.08:11:08.21#ibcon#about to write, iclass 12, count 0 2006.246.08:11:08.21#ibcon#wrote, iclass 12, count 0 2006.246.08:11:08.21#ibcon#about to read 3, iclass 12, count 0 2006.246.08:11:08.24#ibcon#read 3, iclass 12, count 0 2006.246.08:11:08.24#ibcon#about to read 4, iclass 12, count 0 2006.246.08:11:08.24#ibcon#read 4, iclass 12, count 0 2006.246.08:11:08.24#ibcon#about to read 5, iclass 12, count 0 2006.246.08:11:08.24#ibcon#read 5, iclass 12, count 0 2006.246.08:11:08.24#ibcon#about to read 6, iclass 12, count 0 2006.246.08:11:08.24#ibcon#read 6, iclass 12, count 0 2006.246.08:11:08.24#ibcon#end of sib2, iclass 12, count 0 2006.246.08:11:08.24#ibcon#*after write, iclass 12, count 0 2006.246.08:11:08.24#ibcon#*before return 0, iclass 12, count 0 2006.246.08:11:08.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:08.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:08.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:11:08.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:11:08.24$vc4f8/valo=2,572.99 2006.246.08:11:08.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.08:11:08.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.08:11:08.24#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:08.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:08.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:08.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:08.24#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:11:08.24#ibcon#first serial, iclass 14, count 0 2006.246.08:11:08.24#ibcon#enter sib2, iclass 14, count 0 2006.246.08:11:08.24#ibcon#flushed, iclass 14, count 0 2006.246.08:11:08.24#ibcon#about to write, iclass 14, count 0 2006.246.08:11:08.24#ibcon#wrote, iclass 14, count 0 2006.246.08:11:08.24#ibcon#about to read 3, iclass 14, count 0 2006.246.08:11:08.26#ibcon#read 3, iclass 14, count 0 2006.246.08:11:08.26#ibcon#about to read 4, iclass 14, count 0 2006.246.08:11:08.26#ibcon#read 4, iclass 14, count 0 2006.246.08:11:08.26#ibcon#about to read 5, iclass 14, count 0 2006.246.08:11:08.26#ibcon#read 5, iclass 14, count 0 2006.246.08:11:08.26#ibcon#about to read 6, iclass 14, count 0 2006.246.08:11:08.26#ibcon#read 6, iclass 14, count 0 2006.246.08:11:08.26#ibcon#end of sib2, iclass 14, count 0 2006.246.08:11:08.26#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:11:08.26#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:11:08.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:11:08.26#ibcon#*before write, iclass 14, count 0 2006.246.08:11:08.26#ibcon#enter sib2, iclass 14, count 0 2006.246.08:11:08.26#ibcon#flushed, iclass 14, count 0 2006.246.08:11:08.26#ibcon#about to write, iclass 14, count 0 2006.246.08:11:08.26#ibcon#wrote, iclass 14, count 0 2006.246.08:11:08.26#ibcon#about to read 3, iclass 14, count 0 2006.246.08:11:08.30#ibcon#read 3, iclass 14, count 0 2006.246.08:11:08.30#ibcon#about to read 4, iclass 14, count 0 2006.246.08:11:08.30#ibcon#read 4, iclass 14, count 0 2006.246.08:11:08.30#ibcon#about to read 5, iclass 14, count 0 2006.246.08:11:08.30#ibcon#read 5, iclass 14, count 0 2006.246.08:11:08.30#ibcon#about to read 6, iclass 14, count 0 2006.246.08:11:08.30#ibcon#read 6, iclass 14, count 0 2006.246.08:11:08.30#ibcon#end of sib2, iclass 14, count 0 2006.246.08:11:08.30#ibcon#*after write, iclass 14, count 0 2006.246.08:11:08.30#ibcon#*before return 0, iclass 14, count 0 2006.246.08:11:08.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:08.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:08.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:11:08.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:11:08.30$vc4f8/va=2,7 2006.246.08:11:08.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.08:11:08.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.08:11:08.30#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:08.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:08.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:08.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:08.36#ibcon#enter wrdev, iclass 16, count 2 2006.246.08:11:08.36#ibcon#first serial, iclass 16, count 2 2006.246.08:11:08.36#ibcon#enter sib2, iclass 16, count 2 2006.246.08:11:08.36#ibcon#flushed, iclass 16, count 2 2006.246.08:11:08.36#ibcon#about to write, iclass 16, count 2 2006.246.08:11:08.36#ibcon#wrote, iclass 16, count 2 2006.246.08:11:08.36#ibcon#about to read 3, iclass 16, count 2 2006.246.08:11:08.38#ibcon#read 3, iclass 16, count 2 2006.246.08:11:08.38#ibcon#about to read 4, iclass 16, count 2 2006.246.08:11:08.38#ibcon#read 4, iclass 16, count 2 2006.246.08:11:08.38#ibcon#about to read 5, iclass 16, count 2 2006.246.08:11:08.38#ibcon#read 5, iclass 16, count 2 2006.246.08:11:08.38#ibcon#about to read 6, iclass 16, count 2 2006.246.08:11:08.38#ibcon#read 6, iclass 16, count 2 2006.246.08:11:08.38#ibcon#end of sib2, iclass 16, count 2 2006.246.08:11:08.38#ibcon#*mode == 0, iclass 16, count 2 2006.246.08:11:08.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.08:11:08.38#ibcon#[25=AT02-07\r\n] 2006.246.08:11:08.38#ibcon#*before write, iclass 16, count 2 2006.246.08:11:08.38#ibcon#enter sib2, iclass 16, count 2 2006.246.08:11:08.38#ibcon#flushed, iclass 16, count 2 2006.246.08:11:08.38#ibcon#about to write, iclass 16, count 2 2006.246.08:11:08.38#ibcon#wrote, iclass 16, count 2 2006.246.08:11:08.38#ibcon#about to read 3, iclass 16, count 2 2006.246.08:11:08.41#ibcon#read 3, iclass 16, count 2 2006.246.08:11:08.41#ibcon#about to read 4, iclass 16, count 2 2006.246.08:11:08.41#ibcon#read 4, iclass 16, count 2 2006.246.08:11:08.41#ibcon#about to read 5, iclass 16, count 2 2006.246.08:11:08.41#ibcon#read 5, iclass 16, count 2 2006.246.08:11:08.41#ibcon#about to read 6, iclass 16, count 2 2006.246.08:11:08.41#ibcon#read 6, iclass 16, count 2 2006.246.08:11:08.41#ibcon#end of sib2, iclass 16, count 2 2006.246.08:11:08.41#ibcon#*after write, iclass 16, count 2 2006.246.08:11:08.41#ibcon#*before return 0, iclass 16, count 2 2006.246.08:11:08.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:08.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:08.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.08:11:08.41#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:08.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:08.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:08.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:08.53#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:11:08.53#ibcon#first serial, iclass 16, count 0 2006.246.08:11:08.53#ibcon#enter sib2, iclass 16, count 0 2006.246.08:11:08.53#ibcon#flushed, iclass 16, count 0 2006.246.08:11:08.53#ibcon#about to write, iclass 16, count 0 2006.246.08:11:08.53#ibcon#wrote, iclass 16, count 0 2006.246.08:11:08.53#ibcon#about to read 3, iclass 16, count 0 2006.246.08:11:08.55#ibcon#read 3, iclass 16, count 0 2006.246.08:11:08.55#ibcon#about to read 4, iclass 16, count 0 2006.246.08:11:08.55#ibcon#read 4, iclass 16, count 0 2006.246.08:11:08.55#ibcon#about to read 5, iclass 16, count 0 2006.246.08:11:08.55#ibcon#read 5, iclass 16, count 0 2006.246.08:11:08.55#ibcon#about to read 6, iclass 16, count 0 2006.246.08:11:08.55#ibcon#read 6, iclass 16, count 0 2006.246.08:11:08.55#ibcon#end of sib2, iclass 16, count 0 2006.246.08:11:08.55#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:11:08.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:11:08.55#ibcon#[25=USB\r\n] 2006.246.08:11:08.55#ibcon#*before write, iclass 16, count 0 2006.246.08:11:08.55#ibcon#enter sib2, iclass 16, count 0 2006.246.08:11:08.55#ibcon#flushed, iclass 16, count 0 2006.246.08:11:08.55#ibcon#about to write, iclass 16, count 0 2006.246.08:11:08.55#ibcon#wrote, iclass 16, count 0 2006.246.08:11:08.55#ibcon#about to read 3, iclass 16, count 0 2006.246.08:11:08.58#ibcon#read 3, iclass 16, count 0 2006.246.08:11:08.58#ibcon#about to read 4, iclass 16, count 0 2006.246.08:11:08.58#ibcon#read 4, iclass 16, count 0 2006.246.08:11:08.58#ibcon#about to read 5, iclass 16, count 0 2006.246.08:11:08.58#ibcon#read 5, iclass 16, count 0 2006.246.08:11:08.58#ibcon#about to read 6, iclass 16, count 0 2006.246.08:11:08.58#ibcon#read 6, iclass 16, count 0 2006.246.08:11:08.58#ibcon#end of sib2, iclass 16, count 0 2006.246.08:11:08.58#ibcon#*after write, iclass 16, count 0 2006.246.08:11:08.58#ibcon#*before return 0, iclass 16, count 0 2006.246.08:11:08.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:08.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:08.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:11:08.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:11:08.58$vc4f8/valo=3,672.99 2006.246.08:11:08.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.08:11:08.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.08:11:08.58#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:08.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:08.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:08.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:08.58#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:11:08.58#ibcon#first serial, iclass 18, count 0 2006.246.08:11:08.58#ibcon#enter sib2, iclass 18, count 0 2006.246.08:11:08.58#ibcon#flushed, iclass 18, count 0 2006.246.08:11:08.58#ibcon#about to write, iclass 18, count 0 2006.246.08:11:08.58#ibcon#wrote, iclass 18, count 0 2006.246.08:11:08.58#ibcon#about to read 3, iclass 18, count 0 2006.246.08:11:08.60#ibcon#read 3, iclass 18, count 0 2006.246.08:11:08.60#ibcon#about to read 4, iclass 18, count 0 2006.246.08:11:08.60#ibcon#read 4, iclass 18, count 0 2006.246.08:11:08.60#ibcon#about to read 5, iclass 18, count 0 2006.246.08:11:08.60#ibcon#read 5, iclass 18, count 0 2006.246.08:11:08.60#ibcon#about to read 6, iclass 18, count 0 2006.246.08:11:08.60#ibcon#read 6, iclass 18, count 0 2006.246.08:11:08.60#ibcon#end of sib2, iclass 18, count 0 2006.246.08:11:08.60#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:11:08.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:11:08.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:11:08.60#ibcon#*before write, iclass 18, count 0 2006.246.08:11:08.60#ibcon#enter sib2, iclass 18, count 0 2006.246.08:11:08.60#ibcon#flushed, iclass 18, count 0 2006.246.08:11:08.60#ibcon#about to write, iclass 18, count 0 2006.246.08:11:08.60#ibcon#wrote, iclass 18, count 0 2006.246.08:11:08.60#ibcon#about to read 3, iclass 18, count 0 2006.246.08:11:08.65#ibcon#read 3, iclass 18, count 0 2006.246.08:11:08.65#ibcon#about to read 4, iclass 18, count 0 2006.246.08:11:08.65#ibcon#read 4, iclass 18, count 0 2006.246.08:11:08.65#ibcon#about to read 5, iclass 18, count 0 2006.246.08:11:08.65#ibcon#read 5, iclass 18, count 0 2006.246.08:11:08.65#ibcon#about to read 6, iclass 18, count 0 2006.246.08:11:08.65#ibcon#read 6, iclass 18, count 0 2006.246.08:11:08.65#ibcon#end of sib2, iclass 18, count 0 2006.246.08:11:08.65#ibcon#*after write, iclass 18, count 0 2006.246.08:11:08.65#ibcon#*before return 0, iclass 18, count 0 2006.246.08:11:08.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:08.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:08.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:11:08.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:11:08.65$vc4f8/va=3,6 2006.246.08:11:08.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.08:11:08.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.08:11:08.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:08.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:08.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:08.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:08.70#ibcon#enter wrdev, iclass 20, count 2 2006.246.08:11:08.70#ibcon#first serial, iclass 20, count 2 2006.246.08:11:08.70#ibcon#enter sib2, iclass 20, count 2 2006.246.08:11:08.70#ibcon#flushed, iclass 20, count 2 2006.246.08:11:08.70#ibcon#about to write, iclass 20, count 2 2006.246.08:11:08.70#ibcon#wrote, iclass 20, count 2 2006.246.08:11:08.70#ibcon#about to read 3, iclass 20, count 2 2006.246.08:11:08.72#ibcon#read 3, iclass 20, count 2 2006.246.08:11:08.72#ibcon#about to read 4, iclass 20, count 2 2006.246.08:11:08.72#ibcon#read 4, iclass 20, count 2 2006.246.08:11:08.72#ibcon#about to read 5, iclass 20, count 2 2006.246.08:11:08.72#ibcon#read 5, iclass 20, count 2 2006.246.08:11:08.72#ibcon#about to read 6, iclass 20, count 2 2006.246.08:11:08.72#ibcon#read 6, iclass 20, count 2 2006.246.08:11:08.72#ibcon#end of sib2, iclass 20, count 2 2006.246.08:11:08.72#ibcon#*mode == 0, iclass 20, count 2 2006.246.08:11:08.72#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.08:11:08.72#ibcon#[25=AT03-06\r\n] 2006.246.08:11:08.72#ibcon#*before write, iclass 20, count 2 2006.246.08:11:08.72#ibcon#enter sib2, iclass 20, count 2 2006.246.08:11:08.72#ibcon#flushed, iclass 20, count 2 2006.246.08:11:08.72#ibcon#about to write, iclass 20, count 2 2006.246.08:11:08.72#ibcon#wrote, iclass 20, count 2 2006.246.08:11:08.72#ibcon#about to read 3, iclass 20, count 2 2006.246.08:11:08.75#ibcon#read 3, iclass 20, count 2 2006.246.08:11:08.75#ibcon#about to read 4, iclass 20, count 2 2006.246.08:11:08.75#ibcon#read 4, iclass 20, count 2 2006.246.08:11:08.75#ibcon#about to read 5, iclass 20, count 2 2006.246.08:11:08.75#ibcon#read 5, iclass 20, count 2 2006.246.08:11:08.75#ibcon#about to read 6, iclass 20, count 2 2006.246.08:11:08.75#ibcon#read 6, iclass 20, count 2 2006.246.08:11:08.75#ibcon#end of sib2, iclass 20, count 2 2006.246.08:11:08.75#ibcon#*after write, iclass 20, count 2 2006.246.08:11:08.75#ibcon#*before return 0, iclass 20, count 2 2006.246.08:11:08.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:08.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:08.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.08:11:08.75#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:08.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:08.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:08.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:08.87#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:11:08.87#ibcon#first serial, iclass 20, count 0 2006.246.08:11:08.87#ibcon#enter sib2, iclass 20, count 0 2006.246.08:11:08.87#ibcon#flushed, iclass 20, count 0 2006.246.08:11:08.87#ibcon#about to write, iclass 20, count 0 2006.246.08:11:08.87#ibcon#wrote, iclass 20, count 0 2006.246.08:11:08.87#ibcon#about to read 3, iclass 20, count 0 2006.246.08:11:08.89#ibcon#read 3, iclass 20, count 0 2006.246.08:11:08.89#ibcon#about to read 4, iclass 20, count 0 2006.246.08:11:08.89#ibcon#read 4, iclass 20, count 0 2006.246.08:11:08.89#ibcon#about to read 5, iclass 20, count 0 2006.246.08:11:08.89#ibcon#read 5, iclass 20, count 0 2006.246.08:11:08.89#ibcon#about to read 6, iclass 20, count 0 2006.246.08:11:08.89#ibcon#read 6, iclass 20, count 0 2006.246.08:11:08.89#ibcon#end of sib2, iclass 20, count 0 2006.246.08:11:08.89#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:11:08.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:11:08.89#ibcon#[25=USB\r\n] 2006.246.08:11:08.89#ibcon#*before write, iclass 20, count 0 2006.246.08:11:08.89#ibcon#enter sib2, iclass 20, count 0 2006.246.08:11:08.89#ibcon#flushed, iclass 20, count 0 2006.246.08:11:08.89#ibcon#about to write, iclass 20, count 0 2006.246.08:11:08.89#ibcon#wrote, iclass 20, count 0 2006.246.08:11:08.89#ibcon#about to read 3, iclass 20, count 0 2006.246.08:11:08.92#ibcon#read 3, iclass 20, count 0 2006.246.08:11:08.92#ibcon#about to read 4, iclass 20, count 0 2006.246.08:11:08.92#ibcon#read 4, iclass 20, count 0 2006.246.08:11:08.92#ibcon#about to read 5, iclass 20, count 0 2006.246.08:11:08.92#ibcon#read 5, iclass 20, count 0 2006.246.08:11:08.92#ibcon#about to read 6, iclass 20, count 0 2006.246.08:11:08.92#ibcon#read 6, iclass 20, count 0 2006.246.08:11:08.92#ibcon#end of sib2, iclass 20, count 0 2006.246.08:11:08.92#ibcon#*after write, iclass 20, count 0 2006.246.08:11:08.92#ibcon#*before return 0, iclass 20, count 0 2006.246.08:11:08.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:08.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:08.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:11:08.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:11:08.92$vc4f8/valo=4,832.99 2006.246.08:11:08.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.08:11:08.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.08:11:08.92#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:08.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:08.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:08.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:08.92#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:11:08.92#ibcon#first serial, iclass 22, count 0 2006.246.08:11:08.92#ibcon#enter sib2, iclass 22, count 0 2006.246.08:11:08.92#ibcon#flushed, iclass 22, count 0 2006.246.08:11:08.92#ibcon#about to write, iclass 22, count 0 2006.246.08:11:08.92#ibcon#wrote, iclass 22, count 0 2006.246.08:11:08.92#ibcon#about to read 3, iclass 22, count 0 2006.246.08:11:08.94#ibcon#read 3, iclass 22, count 0 2006.246.08:11:08.94#ibcon#about to read 4, iclass 22, count 0 2006.246.08:11:08.94#ibcon#read 4, iclass 22, count 0 2006.246.08:11:08.94#ibcon#about to read 5, iclass 22, count 0 2006.246.08:11:08.94#ibcon#read 5, iclass 22, count 0 2006.246.08:11:08.94#ibcon#about to read 6, iclass 22, count 0 2006.246.08:11:08.94#ibcon#read 6, iclass 22, count 0 2006.246.08:11:08.94#ibcon#end of sib2, iclass 22, count 0 2006.246.08:11:08.94#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:11:08.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:11:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:11:08.94#ibcon#*before write, iclass 22, count 0 2006.246.08:11:08.94#ibcon#enter sib2, iclass 22, count 0 2006.246.08:11:08.94#ibcon#flushed, iclass 22, count 0 2006.246.08:11:08.94#ibcon#about to write, iclass 22, count 0 2006.246.08:11:08.94#ibcon#wrote, iclass 22, count 0 2006.246.08:11:08.94#ibcon#about to read 3, iclass 22, count 0 2006.246.08:11:08.98#ibcon#read 3, iclass 22, count 0 2006.246.08:11:08.98#ibcon#about to read 4, iclass 22, count 0 2006.246.08:11:08.98#ibcon#read 4, iclass 22, count 0 2006.246.08:11:08.98#ibcon#about to read 5, iclass 22, count 0 2006.246.08:11:08.98#ibcon#read 5, iclass 22, count 0 2006.246.08:11:08.98#ibcon#about to read 6, iclass 22, count 0 2006.246.08:11:08.98#ibcon#read 6, iclass 22, count 0 2006.246.08:11:08.98#ibcon#end of sib2, iclass 22, count 0 2006.246.08:11:08.98#ibcon#*after write, iclass 22, count 0 2006.246.08:11:08.98#ibcon#*before return 0, iclass 22, count 0 2006.246.08:11:08.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:08.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:08.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:11:08.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:11:08.98$vc4f8/va=4,7 2006.246.08:11:08.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.08:11:08.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.08:11:08.98#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:08.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:09.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:09.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:09.04#ibcon#enter wrdev, iclass 24, count 2 2006.246.08:11:09.04#ibcon#first serial, iclass 24, count 2 2006.246.08:11:09.04#ibcon#enter sib2, iclass 24, count 2 2006.246.08:11:09.04#ibcon#flushed, iclass 24, count 2 2006.246.08:11:09.04#ibcon#about to write, iclass 24, count 2 2006.246.08:11:09.04#ibcon#wrote, iclass 24, count 2 2006.246.08:11:09.04#ibcon#about to read 3, iclass 24, count 2 2006.246.08:11:09.06#ibcon#read 3, iclass 24, count 2 2006.246.08:11:09.06#ibcon#about to read 4, iclass 24, count 2 2006.246.08:11:09.06#ibcon#read 4, iclass 24, count 2 2006.246.08:11:09.06#ibcon#about to read 5, iclass 24, count 2 2006.246.08:11:09.06#ibcon#read 5, iclass 24, count 2 2006.246.08:11:09.06#ibcon#about to read 6, iclass 24, count 2 2006.246.08:11:09.06#ibcon#read 6, iclass 24, count 2 2006.246.08:11:09.06#ibcon#end of sib2, iclass 24, count 2 2006.246.08:11:09.06#ibcon#*mode == 0, iclass 24, count 2 2006.246.08:11:09.06#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.08:11:09.06#ibcon#[25=AT04-07\r\n] 2006.246.08:11:09.06#ibcon#*before write, iclass 24, count 2 2006.246.08:11:09.06#ibcon#enter sib2, iclass 24, count 2 2006.246.08:11:09.06#ibcon#flushed, iclass 24, count 2 2006.246.08:11:09.06#ibcon#about to write, iclass 24, count 2 2006.246.08:11:09.06#ibcon#wrote, iclass 24, count 2 2006.246.08:11:09.06#ibcon#about to read 3, iclass 24, count 2 2006.246.08:11:09.09#ibcon#read 3, iclass 24, count 2 2006.246.08:11:09.09#ibcon#about to read 4, iclass 24, count 2 2006.246.08:11:09.09#ibcon#read 4, iclass 24, count 2 2006.246.08:11:09.09#ibcon#about to read 5, iclass 24, count 2 2006.246.08:11:09.09#ibcon#read 5, iclass 24, count 2 2006.246.08:11:09.09#ibcon#about to read 6, iclass 24, count 2 2006.246.08:11:09.09#ibcon#read 6, iclass 24, count 2 2006.246.08:11:09.09#ibcon#end of sib2, iclass 24, count 2 2006.246.08:11:09.09#ibcon#*after write, iclass 24, count 2 2006.246.08:11:09.09#ibcon#*before return 0, iclass 24, count 2 2006.246.08:11:09.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:09.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:09.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.08:11:09.09#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:09.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:09.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:09.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:09.21#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:11:09.21#ibcon#first serial, iclass 24, count 0 2006.246.08:11:09.21#ibcon#enter sib2, iclass 24, count 0 2006.246.08:11:09.21#ibcon#flushed, iclass 24, count 0 2006.246.08:11:09.21#ibcon#about to write, iclass 24, count 0 2006.246.08:11:09.21#ibcon#wrote, iclass 24, count 0 2006.246.08:11:09.21#ibcon#about to read 3, iclass 24, count 0 2006.246.08:11:09.23#ibcon#read 3, iclass 24, count 0 2006.246.08:11:09.23#ibcon#about to read 4, iclass 24, count 0 2006.246.08:11:09.23#ibcon#read 4, iclass 24, count 0 2006.246.08:11:09.23#ibcon#about to read 5, iclass 24, count 0 2006.246.08:11:09.23#ibcon#read 5, iclass 24, count 0 2006.246.08:11:09.23#ibcon#about to read 6, iclass 24, count 0 2006.246.08:11:09.23#ibcon#read 6, iclass 24, count 0 2006.246.08:11:09.23#ibcon#end of sib2, iclass 24, count 0 2006.246.08:11:09.23#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:11:09.23#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:11:09.23#ibcon#[25=USB\r\n] 2006.246.08:11:09.23#ibcon#*before write, iclass 24, count 0 2006.246.08:11:09.23#ibcon#enter sib2, iclass 24, count 0 2006.246.08:11:09.23#ibcon#flushed, iclass 24, count 0 2006.246.08:11:09.23#ibcon#about to write, iclass 24, count 0 2006.246.08:11:09.23#ibcon#wrote, iclass 24, count 0 2006.246.08:11:09.23#ibcon#about to read 3, iclass 24, count 0 2006.246.08:11:09.26#ibcon#read 3, iclass 24, count 0 2006.246.08:11:09.26#ibcon#about to read 4, iclass 24, count 0 2006.246.08:11:09.26#ibcon#read 4, iclass 24, count 0 2006.246.08:11:09.26#ibcon#about to read 5, iclass 24, count 0 2006.246.08:11:09.26#ibcon#read 5, iclass 24, count 0 2006.246.08:11:09.26#ibcon#about to read 6, iclass 24, count 0 2006.246.08:11:09.26#ibcon#read 6, iclass 24, count 0 2006.246.08:11:09.26#ibcon#end of sib2, iclass 24, count 0 2006.246.08:11:09.26#ibcon#*after write, iclass 24, count 0 2006.246.08:11:09.26#ibcon#*before return 0, iclass 24, count 0 2006.246.08:11:09.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:09.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:09.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:11:09.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:11:09.26$vc4f8/valo=5,652.99 2006.246.08:11:09.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.08:11:09.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.08:11:09.26#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:09.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:09.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:09.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:09.26#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:11:09.26#ibcon#first serial, iclass 26, count 0 2006.246.08:11:09.26#ibcon#enter sib2, iclass 26, count 0 2006.246.08:11:09.26#ibcon#flushed, iclass 26, count 0 2006.246.08:11:09.26#ibcon#about to write, iclass 26, count 0 2006.246.08:11:09.26#ibcon#wrote, iclass 26, count 0 2006.246.08:11:09.26#ibcon#about to read 3, iclass 26, count 0 2006.246.08:11:09.28#ibcon#read 3, iclass 26, count 0 2006.246.08:11:09.28#ibcon#about to read 4, iclass 26, count 0 2006.246.08:11:09.28#ibcon#read 4, iclass 26, count 0 2006.246.08:11:09.28#ibcon#about to read 5, iclass 26, count 0 2006.246.08:11:09.28#ibcon#read 5, iclass 26, count 0 2006.246.08:11:09.28#ibcon#about to read 6, iclass 26, count 0 2006.246.08:11:09.28#ibcon#read 6, iclass 26, count 0 2006.246.08:11:09.28#ibcon#end of sib2, iclass 26, count 0 2006.246.08:11:09.28#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:11:09.28#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:11:09.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:11:09.28#ibcon#*before write, iclass 26, count 0 2006.246.08:11:09.28#ibcon#enter sib2, iclass 26, count 0 2006.246.08:11:09.28#ibcon#flushed, iclass 26, count 0 2006.246.08:11:09.28#ibcon#about to write, iclass 26, count 0 2006.246.08:11:09.28#ibcon#wrote, iclass 26, count 0 2006.246.08:11:09.28#ibcon#about to read 3, iclass 26, count 0 2006.246.08:11:09.32#ibcon#read 3, iclass 26, count 0 2006.246.08:11:09.32#ibcon#about to read 4, iclass 26, count 0 2006.246.08:11:09.32#ibcon#read 4, iclass 26, count 0 2006.246.08:11:09.32#ibcon#about to read 5, iclass 26, count 0 2006.246.08:11:09.32#ibcon#read 5, iclass 26, count 0 2006.246.08:11:09.32#ibcon#about to read 6, iclass 26, count 0 2006.246.08:11:09.32#ibcon#read 6, iclass 26, count 0 2006.246.08:11:09.32#ibcon#end of sib2, iclass 26, count 0 2006.246.08:11:09.32#ibcon#*after write, iclass 26, count 0 2006.246.08:11:09.32#ibcon#*before return 0, iclass 26, count 0 2006.246.08:11:09.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:09.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:09.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:11:09.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:11:09.32$vc4f8/va=5,7 2006.246.08:11:09.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.08:11:09.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.08:11:09.32#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:09.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:09.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:09.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:09.38#ibcon#enter wrdev, iclass 28, count 2 2006.246.08:11:09.38#ibcon#first serial, iclass 28, count 2 2006.246.08:11:09.38#ibcon#enter sib2, iclass 28, count 2 2006.246.08:11:09.38#ibcon#flushed, iclass 28, count 2 2006.246.08:11:09.38#ibcon#about to write, iclass 28, count 2 2006.246.08:11:09.38#ibcon#wrote, iclass 28, count 2 2006.246.08:11:09.38#ibcon#about to read 3, iclass 28, count 2 2006.246.08:11:09.40#ibcon#read 3, iclass 28, count 2 2006.246.08:11:09.40#ibcon#about to read 4, iclass 28, count 2 2006.246.08:11:09.40#ibcon#read 4, iclass 28, count 2 2006.246.08:11:09.40#ibcon#about to read 5, iclass 28, count 2 2006.246.08:11:09.40#ibcon#read 5, iclass 28, count 2 2006.246.08:11:09.40#ibcon#about to read 6, iclass 28, count 2 2006.246.08:11:09.40#ibcon#read 6, iclass 28, count 2 2006.246.08:11:09.40#ibcon#end of sib2, iclass 28, count 2 2006.246.08:11:09.40#ibcon#*mode == 0, iclass 28, count 2 2006.246.08:11:09.40#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.08:11:09.40#ibcon#[25=AT05-07\r\n] 2006.246.08:11:09.40#ibcon#*before write, iclass 28, count 2 2006.246.08:11:09.40#ibcon#enter sib2, iclass 28, count 2 2006.246.08:11:09.40#ibcon#flushed, iclass 28, count 2 2006.246.08:11:09.40#ibcon#about to write, iclass 28, count 2 2006.246.08:11:09.40#ibcon#wrote, iclass 28, count 2 2006.246.08:11:09.40#ibcon#about to read 3, iclass 28, count 2 2006.246.08:11:09.43#ibcon#read 3, iclass 28, count 2 2006.246.08:11:09.43#ibcon#about to read 4, iclass 28, count 2 2006.246.08:11:09.43#ibcon#read 4, iclass 28, count 2 2006.246.08:11:09.43#ibcon#about to read 5, iclass 28, count 2 2006.246.08:11:09.43#ibcon#read 5, iclass 28, count 2 2006.246.08:11:09.43#ibcon#about to read 6, iclass 28, count 2 2006.246.08:11:09.43#ibcon#read 6, iclass 28, count 2 2006.246.08:11:09.43#ibcon#end of sib2, iclass 28, count 2 2006.246.08:11:09.43#ibcon#*after write, iclass 28, count 2 2006.246.08:11:09.43#ibcon#*before return 0, iclass 28, count 2 2006.246.08:11:09.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:09.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:09.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.08:11:09.43#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:09.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:09.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:09.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:09.55#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:11:09.55#ibcon#first serial, iclass 28, count 0 2006.246.08:11:09.55#ibcon#enter sib2, iclass 28, count 0 2006.246.08:11:09.55#ibcon#flushed, iclass 28, count 0 2006.246.08:11:09.55#ibcon#about to write, iclass 28, count 0 2006.246.08:11:09.55#ibcon#wrote, iclass 28, count 0 2006.246.08:11:09.55#ibcon#about to read 3, iclass 28, count 0 2006.246.08:11:09.57#ibcon#read 3, iclass 28, count 0 2006.246.08:11:09.57#ibcon#about to read 4, iclass 28, count 0 2006.246.08:11:09.57#ibcon#read 4, iclass 28, count 0 2006.246.08:11:09.57#ibcon#about to read 5, iclass 28, count 0 2006.246.08:11:09.57#ibcon#read 5, iclass 28, count 0 2006.246.08:11:09.57#ibcon#about to read 6, iclass 28, count 0 2006.246.08:11:09.57#ibcon#read 6, iclass 28, count 0 2006.246.08:11:09.57#ibcon#end of sib2, iclass 28, count 0 2006.246.08:11:09.57#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:11:09.57#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:11:09.57#ibcon#[25=USB\r\n] 2006.246.08:11:09.57#ibcon#*before write, iclass 28, count 0 2006.246.08:11:09.57#ibcon#enter sib2, iclass 28, count 0 2006.246.08:11:09.57#ibcon#flushed, iclass 28, count 0 2006.246.08:11:09.57#ibcon#about to write, iclass 28, count 0 2006.246.08:11:09.57#ibcon#wrote, iclass 28, count 0 2006.246.08:11:09.57#ibcon#about to read 3, iclass 28, count 0 2006.246.08:11:09.60#ibcon#read 3, iclass 28, count 0 2006.246.08:11:09.60#ibcon#about to read 4, iclass 28, count 0 2006.246.08:11:09.60#ibcon#read 4, iclass 28, count 0 2006.246.08:11:09.60#ibcon#about to read 5, iclass 28, count 0 2006.246.08:11:09.60#ibcon#read 5, iclass 28, count 0 2006.246.08:11:09.60#ibcon#about to read 6, iclass 28, count 0 2006.246.08:11:09.60#ibcon#read 6, iclass 28, count 0 2006.246.08:11:09.60#ibcon#end of sib2, iclass 28, count 0 2006.246.08:11:09.60#ibcon#*after write, iclass 28, count 0 2006.246.08:11:09.60#ibcon#*before return 0, iclass 28, count 0 2006.246.08:11:09.60#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:09.60#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:09.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:11:09.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:11:09.60$vc4f8/valo=6,772.99 2006.246.08:11:09.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.08:11:09.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.08:11:09.60#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:09.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:09.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:09.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:09.60#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:11:09.60#ibcon#first serial, iclass 30, count 0 2006.246.08:11:09.60#ibcon#enter sib2, iclass 30, count 0 2006.246.08:11:09.60#ibcon#flushed, iclass 30, count 0 2006.246.08:11:09.60#ibcon#about to write, iclass 30, count 0 2006.246.08:11:09.60#ibcon#wrote, iclass 30, count 0 2006.246.08:11:09.60#ibcon#about to read 3, iclass 30, count 0 2006.246.08:11:09.62#ibcon#read 3, iclass 30, count 0 2006.246.08:11:09.62#ibcon#about to read 4, iclass 30, count 0 2006.246.08:11:09.62#ibcon#read 4, iclass 30, count 0 2006.246.08:11:09.62#ibcon#about to read 5, iclass 30, count 0 2006.246.08:11:09.62#ibcon#read 5, iclass 30, count 0 2006.246.08:11:09.62#ibcon#about to read 6, iclass 30, count 0 2006.246.08:11:09.62#ibcon#read 6, iclass 30, count 0 2006.246.08:11:09.62#ibcon#end of sib2, iclass 30, count 0 2006.246.08:11:09.62#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:11:09.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:11:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:11:09.62#ibcon#*before write, iclass 30, count 0 2006.246.08:11:09.62#ibcon#enter sib2, iclass 30, count 0 2006.246.08:11:09.62#ibcon#flushed, iclass 30, count 0 2006.246.08:11:09.62#ibcon#about to write, iclass 30, count 0 2006.246.08:11:09.62#ibcon#wrote, iclass 30, count 0 2006.246.08:11:09.62#ibcon#about to read 3, iclass 30, count 0 2006.246.08:11:09.67#ibcon#read 3, iclass 30, count 0 2006.246.08:11:09.67#ibcon#about to read 4, iclass 30, count 0 2006.246.08:11:09.67#ibcon#read 4, iclass 30, count 0 2006.246.08:11:09.67#ibcon#about to read 5, iclass 30, count 0 2006.246.08:11:09.67#ibcon#read 5, iclass 30, count 0 2006.246.08:11:09.67#ibcon#about to read 6, iclass 30, count 0 2006.246.08:11:09.67#ibcon#read 6, iclass 30, count 0 2006.246.08:11:09.67#ibcon#end of sib2, iclass 30, count 0 2006.246.08:11:09.67#ibcon#*after write, iclass 30, count 0 2006.246.08:11:09.67#ibcon#*before return 0, iclass 30, count 0 2006.246.08:11:09.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:09.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:09.67#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:11:09.67#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:11:09.67$vc4f8/va=6,7 2006.246.08:11:09.67#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.08:11:09.67#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.08:11:09.67#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:09.67#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:11:09.72#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:11:09.72#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:11:09.72#ibcon#enter wrdev, iclass 32, count 2 2006.246.08:11:09.72#ibcon#first serial, iclass 32, count 2 2006.246.08:11:09.72#ibcon#enter sib2, iclass 32, count 2 2006.246.08:11:09.72#ibcon#flushed, iclass 32, count 2 2006.246.08:11:09.72#ibcon#about to write, iclass 32, count 2 2006.246.08:11:09.72#ibcon#wrote, iclass 32, count 2 2006.246.08:11:09.72#ibcon#about to read 3, iclass 32, count 2 2006.246.08:11:09.74#ibcon#read 3, iclass 32, count 2 2006.246.08:11:09.74#ibcon#about to read 4, iclass 32, count 2 2006.246.08:11:09.74#ibcon#read 4, iclass 32, count 2 2006.246.08:11:09.74#ibcon#about to read 5, iclass 32, count 2 2006.246.08:11:09.74#ibcon#read 5, iclass 32, count 2 2006.246.08:11:09.74#ibcon#about to read 6, iclass 32, count 2 2006.246.08:11:09.74#ibcon#read 6, iclass 32, count 2 2006.246.08:11:09.74#ibcon#end of sib2, iclass 32, count 2 2006.246.08:11:09.74#ibcon#*mode == 0, iclass 32, count 2 2006.246.08:11:09.74#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.08:11:09.74#ibcon#[25=AT06-07\r\n] 2006.246.08:11:09.74#ibcon#*before write, iclass 32, count 2 2006.246.08:11:09.74#ibcon#enter sib2, iclass 32, count 2 2006.246.08:11:09.74#ibcon#flushed, iclass 32, count 2 2006.246.08:11:09.74#ibcon#about to write, iclass 32, count 2 2006.246.08:11:09.74#ibcon#wrote, iclass 32, count 2 2006.246.08:11:09.74#ibcon#about to read 3, iclass 32, count 2 2006.246.08:11:09.77#ibcon#read 3, iclass 32, count 2 2006.246.08:11:09.77#ibcon#about to read 4, iclass 32, count 2 2006.246.08:11:09.77#ibcon#read 4, iclass 32, count 2 2006.246.08:11:09.77#ibcon#about to read 5, iclass 32, count 2 2006.246.08:11:09.77#ibcon#read 5, iclass 32, count 2 2006.246.08:11:09.77#ibcon#about to read 6, iclass 32, count 2 2006.246.08:11:09.77#ibcon#read 6, iclass 32, count 2 2006.246.08:11:09.77#ibcon#end of sib2, iclass 32, count 2 2006.246.08:11:09.77#ibcon#*after write, iclass 32, count 2 2006.246.08:11:09.77#ibcon#*before return 0, iclass 32, count 2 2006.246.08:11:09.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:11:09.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:11:09.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.08:11:09.77#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:09.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:11:09.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:11:09.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:11:09.89#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:11:09.89#ibcon#first serial, iclass 32, count 0 2006.246.08:11:09.89#ibcon#enter sib2, iclass 32, count 0 2006.246.08:11:09.89#ibcon#flushed, iclass 32, count 0 2006.246.08:11:09.89#ibcon#about to write, iclass 32, count 0 2006.246.08:11:09.89#ibcon#wrote, iclass 32, count 0 2006.246.08:11:09.89#ibcon#about to read 3, iclass 32, count 0 2006.246.08:11:09.91#ibcon#read 3, iclass 32, count 0 2006.246.08:11:09.91#ibcon#about to read 4, iclass 32, count 0 2006.246.08:11:09.91#ibcon#read 4, iclass 32, count 0 2006.246.08:11:09.91#ibcon#about to read 5, iclass 32, count 0 2006.246.08:11:09.91#ibcon#read 5, iclass 32, count 0 2006.246.08:11:09.91#ibcon#about to read 6, iclass 32, count 0 2006.246.08:11:09.91#ibcon#read 6, iclass 32, count 0 2006.246.08:11:09.91#ibcon#end of sib2, iclass 32, count 0 2006.246.08:11:09.91#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:11:09.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:11:09.91#ibcon#[25=USB\r\n] 2006.246.08:11:09.91#ibcon#*before write, iclass 32, count 0 2006.246.08:11:09.91#ibcon#enter sib2, iclass 32, count 0 2006.246.08:11:09.91#ibcon#flushed, iclass 32, count 0 2006.246.08:11:09.91#ibcon#about to write, iclass 32, count 0 2006.246.08:11:09.91#ibcon#wrote, iclass 32, count 0 2006.246.08:11:09.91#ibcon#about to read 3, iclass 32, count 0 2006.246.08:11:09.94#ibcon#read 3, iclass 32, count 0 2006.246.08:11:09.94#ibcon#about to read 4, iclass 32, count 0 2006.246.08:11:09.94#ibcon#read 4, iclass 32, count 0 2006.246.08:11:09.94#ibcon#about to read 5, iclass 32, count 0 2006.246.08:11:09.94#ibcon#read 5, iclass 32, count 0 2006.246.08:11:09.94#ibcon#about to read 6, iclass 32, count 0 2006.246.08:11:09.94#ibcon#read 6, iclass 32, count 0 2006.246.08:11:09.94#ibcon#end of sib2, iclass 32, count 0 2006.246.08:11:09.94#ibcon#*after write, iclass 32, count 0 2006.246.08:11:09.94#ibcon#*before return 0, iclass 32, count 0 2006.246.08:11:09.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:11:09.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:11:09.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:11:09.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:11:09.94$vc4f8/valo=7,832.99 2006.246.08:11:09.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.08:11:09.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.08:11:09.94#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:09.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:11:09.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:11:09.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:11:09.94#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:11:09.94#ibcon#first serial, iclass 34, count 0 2006.246.08:11:09.94#ibcon#enter sib2, iclass 34, count 0 2006.246.08:11:09.94#ibcon#flushed, iclass 34, count 0 2006.246.08:11:09.94#ibcon#about to write, iclass 34, count 0 2006.246.08:11:09.94#ibcon#wrote, iclass 34, count 0 2006.246.08:11:09.94#ibcon#about to read 3, iclass 34, count 0 2006.246.08:11:09.96#ibcon#read 3, iclass 34, count 0 2006.246.08:11:09.96#ibcon#about to read 4, iclass 34, count 0 2006.246.08:11:09.96#ibcon#read 4, iclass 34, count 0 2006.246.08:11:09.96#ibcon#about to read 5, iclass 34, count 0 2006.246.08:11:09.96#ibcon#read 5, iclass 34, count 0 2006.246.08:11:09.96#ibcon#about to read 6, iclass 34, count 0 2006.246.08:11:09.96#ibcon#read 6, iclass 34, count 0 2006.246.08:11:09.96#ibcon#end of sib2, iclass 34, count 0 2006.246.08:11:09.96#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:11:09.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:11:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:11:09.96#ibcon#*before write, iclass 34, count 0 2006.246.08:11:09.96#ibcon#enter sib2, iclass 34, count 0 2006.246.08:11:09.96#ibcon#flushed, iclass 34, count 0 2006.246.08:11:09.96#ibcon#about to write, iclass 34, count 0 2006.246.08:11:09.96#ibcon#wrote, iclass 34, count 0 2006.246.08:11:09.96#ibcon#about to read 3, iclass 34, count 0 2006.246.08:11:10.00#ibcon#read 3, iclass 34, count 0 2006.246.08:11:10.00#ibcon#about to read 4, iclass 34, count 0 2006.246.08:11:10.00#ibcon#read 4, iclass 34, count 0 2006.246.08:11:10.00#ibcon#about to read 5, iclass 34, count 0 2006.246.08:11:10.00#ibcon#read 5, iclass 34, count 0 2006.246.08:11:10.00#ibcon#about to read 6, iclass 34, count 0 2006.246.08:11:10.00#ibcon#read 6, iclass 34, count 0 2006.246.08:11:10.00#ibcon#end of sib2, iclass 34, count 0 2006.246.08:11:10.00#ibcon#*after write, iclass 34, count 0 2006.246.08:11:10.00#ibcon#*before return 0, iclass 34, count 0 2006.246.08:11:10.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:11:10.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:11:10.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:11:10.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:11:10.00$vc4f8/va=7,7 2006.246.08:11:10.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.08:11:10.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.08:11:10.00#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:10.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:11:10.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:11:10.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:11:10.06#ibcon#enter wrdev, iclass 36, count 2 2006.246.08:11:10.06#ibcon#first serial, iclass 36, count 2 2006.246.08:11:10.06#ibcon#enter sib2, iclass 36, count 2 2006.246.08:11:10.06#ibcon#flushed, iclass 36, count 2 2006.246.08:11:10.06#ibcon#about to write, iclass 36, count 2 2006.246.08:11:10.06#ibcon#wrote, iclass 36, count 2 2006.246.08:11:10.06#ibcon#about to read 3, iclass 36, count 2 2006.246.08:11:10.08#ibcon#read 3, iclass 36, count 2 2006.246.08:11:10.08#ibcon#about to read 4, iclass 36, count 2 2006.246.08:11:10.08#ibcon#read 4, iclass 36, count 2 2006.246.08:11:10.08#ibcon#about to read 5, iclass 36, count 2 2006.246.08:11:10.08#ibcon#read 5, iclass 36, count 2 2006.246.08:11:10.08#ibcon#about to read 6, iclass 36, count 2 2006.246.08:11:10.08#ibcon#read 6, iclass 36, count 2 2006.246.08:11:10.08#ibcon#end of sib2, iclass 36, count 2 2006.246.08:11:10.08#ibcon#*mode == 0, iclass 36, count 2 2006.246.08:11:10.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.08:11:10.08#ibcon#[25=AT07-07\r\n] 2006.246.08:11:10.08#ibcon#*before write, iclass 36, count 2 2006.246.08:11:10.08#ibcon#enter sib2, iclass 36, count 2 2006.246.08:11:10.08#ibcon#flushed, iclass 36, count 2 2006.246.08:11:10.08#ibcon#about to write, iclass 36, count 2 2006.246.08:11:10.08#ibcon#wrote, iclass 36, count 2 2006.246.08:11:10.08#ibcon#about to read 3, iclass 36, count 2 2006.246.08:11:10.11#ibcon#read 3, iclass 36, count 2 2006.246.08:11:10.11#ibcon#about to read 4, iclass 36, count 2 2006.246.08:11:10.11#ibcon#read 4, iclass 36, count 2 2006.246.08:11:10.11#ibcon#about to read 5, iclass 36, count 2 2006.246.08:11:10.11#ibcon#read 5, iclass 36, count 2 2006.246.08:11:10.11#ibcon#about to read 6, iclass 36, count 2 2006.246.08:11:10.11#ibcon#read 6, iclass 36, count 2 2006.246.08:11:10.11#ibcon#end of sib2, iclass 36, count 2 2006.246.08:11:10.11#ibcon#*after write, iclass 36, count 2 2006.246.08:11:10.11#ibcon#*before return 0, iclass 36, count 2 2006.246.08:11:10.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:11:10.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:11:10.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.08:11:10.11#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:10.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:11:10.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:11:10.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:11:10.23#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:11:10.23#ibcon#first serial, iclass 36, count 0 2006.246.08:11:10.23#ibcon#enter sib2, iclass 36, count 0 2006.246.08:11:10.23#ibcon#flushed, iclass 36, count 0 2006.246.08:11:10.23#ibcon#about to write, iclass 36, count 0 2006.246.08:11:10.23#ibcon#wrote, iclass 36, count 0 2006.246.08:11:10.23#ibcon#about to read 3, iclass 36, count 0 2006.246.08:11:10.25#ibcon#read 3, iclass 36, count 0 2006.246.08:11:10.25#ibcon#about to read 4, iclass 36, count 0 2006.246.08:11:10.25#ibcon#read 4, iclass 36, count 0 2006.246.08:11:10.25#ibcon#about to read 5, iclass 36, count 0 2006.246.08:11:10.25#ibcon#read 5, iclass 36, count 0 2006.246.08:11:10.25#ibcon#about to read 6, iclass 36, count 0 2006.246.08:11:10.25#ibcon#read 6, iclass 36, count 0 2006.246.08:11:10.25#ibcon#end of sib2, iclass 36, count 0 2006.246.08:11:10.25#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:11:10.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:11:10.25#ibcon#[25=USB\r\n] 2006.246.08:11:10.25#ibcon#*before write, iclass 36, count 0 2006.246.08:11:10.25#ibcon#enter sib2, iclass 36, count 0 2006.246.08:11:10.25#ibcon#flushed, iclass 36, count 0 2006.246.08:11:10.25#ibcon#about to write, iclass 36, count 0 2006.246.08:11:10.25#ibcon#wrote, iclass 36, count 0 2006.246.08:11:10.25#ibcon#about to read 3, iclass 36, count 0 2006.246.08:11:10.28#ibcon#read 3, iclass 36, count 0 2006.246.08:11:10.28#ibcon#about to read 4, iclass 36, count 0 2006.246.08:11:10.28#ibcon#read 4, iclass 36, count 0 2006.246.08:11:10.28#ibcon#about to read 5, iclass 36, count 0 2006.246.08:11:10.28#ibcon#read 5, iclass 36, count 0 2006.246.08:11:10.28#ibcon#about to read 6, iclass 36, count 0 2006.246.08:11:10.28#ibcon#read 6, iclass 36, count 0 2006.246.08:11:10.28#ibcon#end of sib2, iclass 36, count 0 2006.246.08:11:10.28#ibcon#*after write, iclass 36, count 0 2006.246.08:11:10.28#ibcon#*before return 0, iclass 36, count 0 2006.246.08:11:10.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:11:10.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:11:10.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:11:10.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:11:10.28$vc4f8/valo=8,852.99 2006.246.08:11:10.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.08:11:10.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.08:11:10.28#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:10.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:11:10.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:11:10.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:11:10.28#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:11:10.28#ibcon#first serial, iclass 38, count 0 2006.246.08:11:10.28#ibcon#enter sib2, iclass 38, count 0 2006.246.08:11:10.28#ibcon#flushed, iclass 38, count 0 2006.246.08:11:10.28#ibcon#about to write, iclass 38, count 0 2006.246.08:11:10.28#ibcon#wrote, iclass 38, count 0 2006.246.08:11:10.28#ibcon#about to read 3, iclass 38, count 0 2006.246.08:11:10.30#ibcon#read 3, iclass 38, count 0 2006.246.08:11:10.30#ibcon#about to read 4, iclass 38, count 0 2006.246.08:11:10.30#ibcon#read 4, iclass 38, count 0 2006.246.08:11:10.30#ibcon#about to read 5, iclass 38, count 0 2006.246.08:11:10.30#ibcon#read 5, iclass 38, count 0 2006.246.08:11:10.30#ibcon#about to read 6, iclass 38, count 0 2006.246.08:11:10.30#ibcon#read 6, iclass 38, count 0 2006.246.08:11:10.30#ibcon#end of sib2, iclass 38, count 0 2006.246.08:11:10.30#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:11:10.30#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:11:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:11:10.30#ibcon#*before write, iclass 38, count 0 2006.246.08:11:10.30#ibcon#enter sib2, iclass 38, count 0 2006.246.08:11:10.30#ibcon#flushed, iclass 38, count 0 2006.246.08:11:10.30#ibcon#about to write, iclass 38, count 0 2006.246.08:11:10.30#ibcon#wrote, iclass 38, count 0 2006.246.08:11:10.30#ibcon#about to read 3, iclass 38, count 0 2006.246.08:11:10.34#ibcon#read 3, iclass 38, count 0 2006.246.08:11:10.34#ibcon#about to read 4, iclass 38, count 0 2006.246.08:11:10.34#ibcon#read 4, iclass 38, count 0 2006.246.08:11:10.34#ibcon#about to read 5, iclass 38, count 0 2006.246.08:11:10.34#ibcon#read 5, iclass 38, count 0 2006.246.08:11:10.34#ibcon#about to read 6, iclass 38, count 0 2006.246.08:11:10.34#ibcon#read 6, iclass 38, count 0 2006.246.08:11:10.34#ibcon#end of sib2, iclass 38, count 0 2006.246.08:11:10.34#ibcon#*after write, iclass 38, count 0 2006.246.08:11:10.34#ibcon#*before return 0, iclass 38, count 0 2006.246.08:11:10.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:11:10.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:11:10.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:11:10.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:11:10.34$vc4f8/va=8,8 2006.246.08:11:10.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.08:11:10.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.08:11:10.34#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:10.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:11:10.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:11:10.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:11:10.40#ibcon#enter wrdev, iclass 40, count 2 2006.246.08:11:10.40#ibcon#first serial, iclass 40, count 2 2006.246.08:11:10.40#ibcon#enter sib2, iclass 40, count 2 2006.246.08:11:10.40#ibcon#flushed, iclass 40, count 2 2006.246.08:11:10.40#ibcon#about to write, iclass 40, count 2 2006.246.08:11:10.40#ibcon#wrote, iclass 40, count 2 2006.246.08:11:10.40#ibcon#about to read 3, iclass 40, count 2 2006.246.08:11:10.42#ibcon#read 3, iclass 40, count 2 2006.246.08:11:10.42#ibcon#about to read 4, iclass 40, count 2 2006.246.08:11:10.42#ibcon#read 4, iclass 40, count 2 2006.246.08:11:10.42#ibcon#about to read 5, iclass 40, count 2 2006.246.08:11:10.42#ibcon#read 5, iclass 40, count 2 2006.246.08:11:10.42#ibcon#about to read 6, iclass 40, count 2 2006.246.08:11:10.42#ibcon#read 6, iclass 40, count 2 2006.246.08:11:10.42#ibcon#end of sib2, iclass 40, count 2 2006.246.08:11:10.42#ibcon#*mode == 0, iclass 40, count 2 2006.246.08:11:10.42#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.08:11:10.42#ibcon#[25=AT08-08\r\n] 2006.246.08:11:10.42#ibcon#*before write, iclass 40, count 2 2006.246.08:11:10.42#ibcon#enter sib2, iclass 40, count 2 2006.246.08:11:10.42#ibcon#flushed, iclass 40, count 2 2006.246.08:11:10.42#ibcon#about to write, iclass 40, count 2 2006.246.08:11:10.42#ibcon#wrote, iclass 40, count 2 2006.246.08:11:10.42#ibcon#about to read 3, iclass 40, count 2 2006.246.08:11:10.45#ibcon#read 3, iclass 40, count 2 2006.246.08:11:10.45#ibcon#about to read 4, iclass 40, count 2 2006.246.08:11:10.45#ibcon#read 4, iclass 40, count 2 2006.246.08:11:10.45#ibcon#about to read 5, iclass 40, count 2 2006.246.08:11:10.45#ibcon#read 5, iclass 40, count 2 2006.246.08:11:10.45#ibcon#about to read 6, iclass 40, count 2 2006.246.08:11:10.45#ibcon#read 6, iclass 40, count 2 2006.246.08:11:10.45#ibcon#end of sib2, iclass 40, count 2 2006.246.08:11:10.45#ibcon#*after write, iclass 40, count 2 2006.246.08:11:10.45#ibcon#*before return 0, iclass 40, count 2 2006.246.08:11:10.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:11:10.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:11:10.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.08:11:10.45#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:10.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:11:10.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:11:10.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:11:10.57#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:11:10.57#ibcon#first serial, iclass 40, count 0 2006.246.08:11:10.57#ibcon#enter sib2, iclass 40, count 0 2006.246.08:11:10.57#ibcon#flushed, iclass 40, count 0 2006.246.08:11:10.57#ibcon#about to write, iclass 40, count 0 2006.246.08:11:10.57#ibcon#wrote, iclass 40, count 0 2006.246.08:11:10.57#ibcon#about to read 3, iclass 40, count 0 2006.246.08:11:10.59#ibcon#read 3, iclass 40, count 0 2006.246.08:11:10.59#ibcon#about to read 4, iclass 40, count 0 2006.246.08:11:10.59#ibcon#read 4, iclass 40, count 0 2006.246.08:11:10.59#ibcon#about to read 5, iclass 40, count 0 2006.246.08:11:10.59#ibcon#read 5, iclass 40, count 0 2006.246.08:11:10.59#ibcon#about to read 6, iclass 40, count 0 2006.246.08:11:10.59#ibcon#read 6, iclass 40, count 0 2006.246.08:11:10.59#ibcon#end of sib2, iclass 40, count 0 2006.246.08:11:10.59#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:11:10.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:11:10.59#ibcon#[25=USB\r\n] 2006.246.08:11:10.59#ibcon#*before write, iclass 40, count 0 2006.246.08:11:10.59#ibcon#enter sib2, iclass 40, count 0 2006.246.08:11:10.59#ibcon#flushed, iclass 40, count 0 2006.246.08:11:10.59#ibcon#about to write, iclass 40, count 0 2006.246.08:11:10.59#ibcon#wrote, iclass 40, count 0 2006.246.08:11:10.59#ibcon#about to read 3, iclass 40, count 0 2006.246.08:11:10.62#ibcon#read 3, iclass 40, count 0 2006.246.08:11:10.62#ibcon#about to read 4, iclass 40, count 0 2006.246.08:11:10.62#ibcon#read 4, iclass 40, count 0 2006.246.08:11:10.62#ibcon#about to read 5, iclass 40, count 0 2006.246.08:11:10.62#ibcon#read 5, iclass 40, count 0 2006.246.08:11:10.62#ibcon#about to read 6, iclass 40, count 0 2006.246.08:11:10.62#ibcon#read 6, iclass 40, count 0 2006.246.08:11:10.62#ibcon#end of sib2, iclass 40, count 0 2006.246.08:11:10.62#ibcon#*after write, iclass 40, count 0 2006.246.08:11:10.62#ibcon#*before return 0, iclass 40, count 0 2006.246.08:11:10.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:11:10.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:11:10.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:11:10.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:11:10.62$vc4f8/vblo=1,632.99 2006.246.08:11:10.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.08:11:10.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.08:11:10.62#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:10.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:11:10.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:11:10.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:11:10.62#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:11:10.62#ibcon#first serial, iclass 4, count 0 2006.246.08:11:10.62#ibcon#enter sib2, iclass 4, count 0 2006.246.08:11:10.62#ibcon#flushed, iclass 4, count 0 2006.246.08:11:10.62#ibcon#about to write, iclass 4, count 0 2006.246.08:11:10.62#ibcon#wrote, iclass 4, count 0 2006.246.08:11:10.62#ibcon#about to read 3, iclass 4, count 0 2006.246.08:11:10.64#ibcon#read 3, iclass 4, count 0 2006.246.08:11:10.64#ibcon#about to read 4, iclass 4, count 0 2006.246.08:11:10.64#ibcon#read 4, iclass 4, count 0 2006.246.08:11:10.64#ibcon#about to read 5, iclass 4, count 0 2006.246.08:11:10.64#ibcon#read 5, iclass 4, count 0 2006.246.08:11:10.64#ibcon#about to read 6, iclass 4, count 0 2006.246.08:11:10.64#ibcon#read 6, iclass 4, count 0 2006.246.08:11:10.64#ibcon#end of sib2, iclass 4, count 0 2006.246.08:11:10.64#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:11:10.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:11:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:11:10.64#ibcon#*before write, iclass 4, count 0 2006.246.08:11:10.64#ibcon#enter sib2, iclass 4, count 0 2006.246.08:11:10.64#ibcon#flushed, iclass 4, count 0 2006.246.08:11:10.64#ibcon#about to write, iclass 4, count 0 2006.246.08:11:10.64#ibcon#wrote, iclass 4, count 0 2006.246.08:11:10.64#ibcon#about to read 3, iclass 4, count 0 2006.246.08:11:10.68#ibcon#read 3, iclass 4, count 0 2006.246.08:11:10.68#ibcon#about to read 4, iclass 4, count 0 2006.246.08:11:10.68#ibcon#read 4, iclass 4, count 0 2006.246.08:11:10.68#ibcon#about to read 5, iclass 4, count 0 2006.246.08:11:10.68#ibcon#read 5, iclass 4, count 0 2006.246.08:11:10.68#ibcon#about to read 6, iclass 4, count 0 2006.246.08:11:10.68#ibcon#read 6, iclass 4, count 0 2006.246.08:11:10.68#ibcon#end of sib2, iclass 4, count 0 2006.246.08:11:10.68#ibcon#*after write, iclass 4, count 0 2006.246.08:11:10.68#ibcon#*before return 0, iclass 4, count 0 2006.246.08:11:10.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:11:10.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:11:10.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:11:10.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:11:10.68$vc4f8/vb=1,4 2006.246.08:11:10.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.08:11:10.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.08:11:10.68#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:10.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:11:10.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:11:10.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:11:10.68#ibcon#enter wrdev, iclass 6, count 2 2006.246.08:11:10.68#ibcon#first serial, iclass 6, count 2 2006.246.08:11:10.68#ibcon#enter sib2, iclass 6, count 2 2006.246.08:11:10.68#ibcon#flushed, iclass 6, count 2 2006.246.08:11:10.68#ibcon#about to write, iclass 6, count 2 2006.246.08:11:10.68#ibcon#wrote, iclass 6, count 2 2006.246.08:11:10.68#ibcon#about to read 3, iclass 6, count 2 2006.246.08:11:10.70#ibcon#read 3, iclass 6, count 2 2006.246.08:11:10.70#ibcon#about to read 4, iclass 6, count 2 2006.246.08:11:10.70#ibcon#read 4, iclass 6, count 2 2006.246.08:11:10.70#ibcon#about to read 5, iclass 6, count 2 2006.246.08:11:10.70#ibcon#read 5, iclass 6, count 2 2006.246.08:11:10.70#ibcon#about to read 6, iclass 6, count 2 2006.246.08:11:10.70#ibcon#read 6, iclass 6, count 2 2006.246.08:11:10.70#ibcon#end of sib2, iclass 6, count 2 2006.246.08:11:10.70#ibcon#*mode == 0, iclass 6, count 2 2006.246.08:11:10.70#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.08:11:10.70#ibcon#[27=AT01-04\r\n] 2006.246.08:11:10.70#ibcon#*before write, iclass 6, count 2 2006.246.08:11:10.70#ibcon#enter sib2, iclass 6, count 2 2006.246.08:11:10.70#ibcon#flushed, iclass 6, count 2 2006.246.08:11:10.70#ibcon#about to write, iclass 6, count 2 2006.246.08:11:10.70#ibcon#wrote, iclass 6, count 2 2006.246.08:11:10.70#ibcon#about to read 3, iclass 6, count 2 2006.246.08:11:10.73#ibcon#read 3, iclass 6, count 2 2006.246.08:11:10.73#ibcon#about to read 4, iclass 6, count 2 2006.246.08:11:10.73#ibcon#read 4, iclass 6, count 2 2006.246.08:11:10.73#ibcon#about to read 5, iclass 6, count 2 2006.246.08:11:10.73#ibcon#read 5, iclass 6, count 2 2006.246.08:11:10.73#ibcon#about to read 6, iclass 6, count 2 2006.246.08:11:10.73#ibcon#read 6, iclass 6, count 2 2006.246.08:11:10.73#ibcon#end of sib2, iclass 6, count 2 2006.246.08:11:10.73#ibcon#*after write, iclass 6, count 2 2006.246.08:11:10.73#ibcon#*before return 0, iclass 6, count 2 2006.246.08:11:10.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:11:10.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:11:10.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.08:11:10.73#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:10.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:11:10.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:11:10.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:11:10.85#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:11:10.85#ibcon#first serial, iclass 6, count 0 2006.246.08:11:10.85#ibcon#enter sib2, iclass 6, count 0 2006.246.08:11:10.85#ibcon#flushed, iclass 6, count 0 2006.246.08:11:10.85#ibcon#about to write, iclass 6, count 0 2006.246.08:11:10.85#ibcon#wrote, iclass 6, count 0 2006.246.08:11:10.85#ibcon#about to read 3, iclass 6, count 0 2006.246.08:11:10.87#ibcon#read 3, iclass 6, count 0 2006.246.08:11:10.87#ibcon#about to read 4, iclass 6, count 0 2006.246.08:11:10.87#ibcon#read 4, iclass 6, count 0 2006.246.08:11:10.87#ibcon#about to read 5, iclass 6, count 0 2006.246.08:11:10.87#ibcon#read 5, iclass 6, count 0 2006.246.08:11:10.87#ibcon#about to read 6, iclass 6, count 0 2006.246.08:11:10.87#ibcon#read 6, iclass 6, count 0 2006.246.08:11:10.87#ibcon#end of sib2, iclass 6, count 0 2006.246.08:11:10.87#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:11:10.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:11:10.87#ibcon#[27=USB\r\n] 2006.246.08:11:10.87#ibcon#*before write, iclass 6, count 0 2006.246.08:11:10.87#ibcon#enter sib2, iclass 6, count 0 2006.246.08:11:10.87#ibcon#flushed, iclass 6, count 0 2006.246.08:11:10.87#ibcon#about to write, iclass 6, count 0 2006.246.08:11:10.87#ibcon#wrote, iclass 6, count 0 2006.246.08:11:10.87#ibcon#about to read 3, iclass 6, count 0 2006.246.08:11:10.90#ibcon#read 3, iclass 6, count 0 2006.246.08:11:10.90#ibcon#about to read 4, iclass 6, count 0 2006.246.08:11:10.90#ibcon#read 4, iclass 6, count 0 2006.246.08:11:10.90#ibcon#about to read 5, iclass 6, count 0 2006.246.08:11:10.90#ibcon#read 5, iclass 6, count 0 2006.246.08:11:10.90#ibcon#about to read 6, iclass 6, count 0 2006.246.08:11:10.90#ibcon#read 6, iclass 6, count 0 2006.246.08:11:10.90#ibcon#end of sib2, iclass 6, count 0 2006.246.08:11:10.90#ibcon#*after write, iclass 6, count 0 2006.246.08:11:10.90#ibcon#*before return 0, iclass 6, count 0 2006.246.08:11:10.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:11:10.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:11:10.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:11:10.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:11:10.90$vc4f8/vblo=2,640.99 2006.246.08:11:10.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.08:11:10.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.08:11:10.90#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:10.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:10.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:10.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:10.90#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:11:10.90#ibcon#first serial, iclass 10, count 0 2006.246.08:11:10.90#ibcon#enter sib2, iclass 10, count 0 2006.246.08:11:10.90#ibcon#flushed, iclass 10, count 0 2006.246.08:11:10.90#ibcon#about to write, iclass 10, count 0 2006.246.08:11:10.90#ibcon#wrote, iclass 10, count 0 2006.246.08:11:10.90#ibcon#about to read 3, iclass 10, count 0 2006.246.08:11:10.92#ibcon#read 3, iclass 10, count 0 2006.246.08:11:10.92#ibcon#about to read 4, iclass 10, count 0 2006.246.08:11:10.92#ibcon#read 4, iclass 10, count 0 2006.246.08:11:10.92#ibcon#about to read 5, iclass 10, count 0 2006.246.08:11:10.92#ibcon#read 5, iclass 10, count 0 2006.246.08:11:10.92#ibcon#about to read 6, iclass 10, count 0 2006.246.08:11:10.92#ibcon#read 6, iclass 10, count 0 2006.246.08:11:10.92#ibcon#end of sib2, iclass 10, count 0 2006.246.08:11:10.92#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:11:10.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:11:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:11:10.92#ibcon#*before write, iclass 10, count 0 2006.246.08:11:10.92#ibcon#enter sib2, iclass 10, count 0 2006.246.08:11:10.92#ibcon#flushed, iclass 10, count 0 2006.246.08:11:10.92#ibcon#about to write, iclass 10, count 0 2006.246.08:11:10.92#ibcon#wrote, iclass 10, count 0 2006.246.08:11:10.92#ibcon#about to read 3, iclass 10, count 0 2006.246.08:11:10.96#ibcon#read 3, iclass 10, count 0 2006.246.08:11:10.96#ibcon#about to read 4, iclass 10, count 0 2006.246.08:11:10.96#ibcon#read 4, iclass 10, count 0 2006.246.08:11:10.96#ibcon#about to read 5, iclass 10, count 0 2006.246.08:11:10.96#ibcon#read 5, iclass 10, count 0 2006.246.08:11:10.96#ibcon#about to read 6, iclass 10, count 0 2006.246.08:11:10.96#ibcon#read 6, iclass 10, count 0 2006.246.08:11:10.96#ibcon#end of sib2, iclass 10, count 0 2006.246.08:11:10.96#ibcon#*after write, iclass 10, count 0 2006.246.08:11:10.96#ibcon#*before return 0, iclass 10, count 0 2006.246.08:11:10.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:10.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:11:10.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:11:10.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:11:10.96$vc4f8/vb=2,4 2006.246.08:11:10.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.08:11:10.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.08:11:10.96#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:10.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:11.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:11.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:11.02#ibcon#enter wrdev, iclass 12, count 2 2006.246.08:11:11.02#ibcon#first serial, iclass 12, count 2 2006.246.08:11:11.02#ibcon#enter sib2, iclass 12, count 2 2006.246.08:11:11.02#ibcon#flushed, iclass 12, count 2 2006.246.08:11:11.02#ibcon#about to write, iclass 12, count 2 2006.246.08:11:11.02#ibcon#wrote, iclass 12, count 2 2006.246.08:11:11.02#ibcon#about to read 3, iclass 12, count 2 2006.246.08:11:11.04#ibcon#read 3, iclass 12, count 2 2006.246.08:11:11.04#ibcon#about to read 4, iclass 12, count 2 2006.246.08:11:11.04#ibcon#read 4, iclass 12, count 2 2006.246.08:11:11.04#ibcon#about to read 5, iclass 12, count 2 2006.246.08:11:11.04#ibcon#read 5, iclass 12, count 2 2006.246.08:11:11.04#ibcon#about to read 6, iclass 12, count 2 2006.246.08:11:11.04#ibcon#read 6, iclass 12, count 2 2006.246.08:11:11.04#ibcon#end of sib2, iclass 12, count 2 2006.246.08:11:11.04#ibcon#*mode == 0, iclass 12, count 2 2006.246.08:11:11.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.08:11:11.04#ibcon#[27=AT02-04\r\n] 2006.246.08:11:11.04#ibcon#*before write, iclass 12, count 2 2006.246.08:11:11.04#ibcon#enter sib2, iclass 12, count 2 2006.246.08:11:11.04#ibcon#flushed, iclass 12, count 2 2006.246.08:11:11.04#ibcon#about to write, iclass 12, count 2 2006.246.08:11:11.04#ibcon#wrote, iclass 12, count 2 2006.246.08:11:11.04#ibcon#about to read 3, iclass 12, count 2 2006.246.08:11:11.07#ibcon#read 3, iclass 12, count 2 2006.246.08:11:11.07#ibcon#about to read 4, iclass 12, count 2 2006.246.08:11:11.07#ibcon#read 4, iclass 12, count 2 2006.246.08:11:11.07#ibcon#about to read 5, iclass 12, count 2 2006.246.08:11:11.07#ibcon#read 5, iclass 12, count 2 2006.246.08:11:11.07#ibcon#about to read 6, iclass 12, count 2 2006.246.08:11:11.07#ibcon#read 6, iclass 12, count 2 2006.246.08:11:11.07#ibcon#end of sib2, iclass 12, count 2 2006.246.08:11:11.07#ibcon#*after write, iclass 12, count 2 2006.246.08:11:11.07#ibcon#*before return 0, iclass 12, count 2 2006.246.08:11:11.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:11.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:11:11.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.08:11:11.07#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:11.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:11.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:11.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:11.19#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:11:11.19#ibcon#first serial, iclass 12, count 0 2006.246.08:11:11.19#ibcon#enter sib2, iclass 12, count 0 2006.246.08:11:11.19#ibcon#flushed, iclass 12, count 0 2006.246.08:11:11.19#ibcon#about to write, iclass 12, count 0 2006.246.08:11:11.19#ibcon#wrote, iclass 12, count 0 2006.246.08:11:11.19#ibcon#about to read 3, iclass 12, count 0 2006.246.08:11:11.22#ibcon#read 3, iclass 12, count 0 2006.246.08:11:11.22#ibcon#about to read 4, iclass 12, count 0 2006.246.08:11:11.22#ibcon#read 4, iclass 12, count 0 2006.246.08:11:11.22#ibcon#about to read 5, iclass 12, count 0 2006.246.08:11:11.22#ibcon#read 5, iclass 12, count 0 2006.246.08:11:11.22#ibcon#about to read 6, iclass 12, count 0 2006.246.08:11:11.22#ibcon#read 6, iclass 12, count 0 2006.246.08:11:11.22#ibcon#end of sib2, iclass 12, count 0 2006.246.08:11:11.22#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:11:11.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:11:11.22#ibcon#[27=USB\r\n] 2006.246.08:11:11.22#ibcon#*before write, iclass 12, count 0 2006.246.08:11:11.22#ibcon#enter sib2, iclass 12, count 0 2006.246.08:11:11.22#ibcon#flushed, iclass 12, count 0 2006.246.08:11:11.22#ibcon#about to write, iclass 12, count 0 2006.246.08:11:11.22#ibcon#wrote, iclass 12, count 0 2006.246.08:11:11.22#ibcon#about to read 3, iclass 12, count 0 2006.246.08:11:11.25#ibcon#read 3, iclass 12, count 0 2006.246.08:11:11.25#ibcon#about to read 4, iclass 12, count 0 2006.246.08:11:11.25#ibcon#read 4, iclass 12, count 0 2006.246.08:11:11.25#ibcon#about to read 5, iclass 12, count 0 2006.246.08:11:11.25#ibcon#read 5, iclass 12, count 0 2006.246.08:11:11.25#ibcon#about to read 6, iclass 12, count 0 2006.246.08:11:11.25#ibcon#read 6, iclass 12, count 0 2006.246.08:11:11.25#ibcon#end of sib2, iclass 12, count 0 2006.246.08:11:11.25#ibcon#*after write, iclass 12, count 0 2006.246.08:11:11.25#ibcon#*before return 0, iclass 12, count 0 2006.246.08:11:11.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:11.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:11:11.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:11:11.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:11:11.25$vc4f8/vblo=3,656.99 2006.246.08:11:11.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.08:11:11.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.08:11:11.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:11.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:11.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:11.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:11.25#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:11:11.25#ibcon#first serial, iclass 14, count 0 2006.246.08:11:11.25#ibcon#enter sib2, iclass 14, count 0 2006.246.08:11:11.25#ibcon#flushed, iclass 14, count 0 2006.246.08:11:11.25#ibcon#about to write, iclass 14, count 0 2006.246.08:11:11.25#ibcon#wrote, iclass 14, count 0 2006.246.08:11:11.25#ibcon#about to read 3, iclass 14, count 0 2006.246.08:11:11.27#ibcon#read 3, iclass 14, count 0 2006.246.08:11:11.27#ibcon#about to read 4, iclass 14, count 0 2006.246.08:11:11.27#ibcon#read 4, iclass 14, count 0 2006.246.08:11:11.27#ibcon#about to read 5, iclass 14, count 0 2006.246.08:11:11.27#ibcon#read 5, iclass 14, count 0 2006.246.08:11:11.27#ibcon#about to read 6, iclass 14, count 0 2006.246.08:11:11.27#ibcon#read 6, iclass 14, count 0 2006.246.08:11:11.27#ibcon#end of sib2, iclass 14, count 0 2006.246.08:11:11.27#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:11:11.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:11:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:11:11.27#ibcon#*before write, iclass 14, count 0 2006.246.08:11:11.27#ibcon#enter sib2, iclass 14, count 0 2006.246.08:11:11.27#ibcon#flushed, iclass 14, count 0 2006.246.08:11:11.27#ibcon#about to write, iclass 14, count 0 2006.246.08:11:11.27#ibcon#wrote, iclass 14, count 0 2006.246.08:11:11.27#ibcon#about to read 3, iclass 14, count 0 2006.246.08:11:11.31#ibcon#read 3, iclass 14, count 0 2006.246.08:11:11.31#ibcon#about to read 4, iclass 14, count 0 2006.246.08:11:11.31#ibcon#read 4, iclass 14, count 0 2006.246.08:11:11.31#ibcon#about to read 5, iclass 14, count 0 2006.246.08:11:11.31#ibcon#read 5, iclass 14, count 0 2006.246.08:11:11.31#ibcon#about to read 6, iclass 14, count 0 2006.246.08:11:11.31#ibcon#read 6, iclass 14, count 0 2006.246.08:11:11.31#ibcon#end of sib2, iclass 14, count 0 2006.246.08:11:11.31#ibcon#*after write, iclass 14, count 0 2006.246.08:11:11.31#ibcon#*before return 0, iclass 14, count 0 2006.246.08:11:11.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:11.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:11:11.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:11:11.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:11:11.31$vc4f8/vb=3,4 2006.246.08:11:11.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.08:11:11.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.08:11:11.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:11.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:11.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:11.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:11.37#ibcon#enter wrdev, iclass 16, count 2 2006.246.08:11:11.37#ibcon#first serial, iclass 16, count 2 2006.246.08:11:11.37#ibcon#enter sib2, iclass 16, count 2 2006.246.08:11:11.37#ibcon#flushed, iclass 16, count 2 2006.246.08:11:11.37#ibcon#about to write, iclass 16, count 2 2006.246.08:11:11.37#ibcon#wrote, iclass 16, count 2 2006.246.08:11:11.37#ibcon#about to read 3, iclass 16, count 2 2006.246.08:11:11.39#ibcon#read 3, iclass 16, count 2 2006.246.08:11:11.39#ibcon#about to read 4, iclass 16, count 2 2006.246.08:11:11.39#ibcon#read 4, iclass 16, count 2 2006.246.08:11:11.39#ibcon#about to read 5, iclass 16, count 2 2006.246.08:11:11.39#ibcon#read 5, iclass 16, count 2 2006.246.08:11:11.39#ibcon#about to read 6, iclass 16, count 2 2006.246.08:11:11.39#ibcon#read 6, iclass 16, count 2 2006.246.08:11:11.39#ibcon#end of sib2, iclass 16, count 2 2006.246.08:11:11.39#ibcon#*mode == 0, iclass 16, count 2 2006.246.08:11:11.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.08:11:11.39#ibcon#[27=AT03-04\r\n] 2006.246.08:11:11.39#ibcon#*before write, iclass 16, count 2 2006.246.08:11:11.39#ibcon#enter sib2, iclass 16, count 2 2006.246.08:11:11.39#ibcon#flushed, iclass 16, count 2 2006.246.08:11:11.39#ibcon#about to write, iclass 16, count 2 2006.246.08:11:11.39#ibcon#wrote, iclass 16, count 2 2006.246.08:11:11.39#ibcon#about to read 3, iclass 16, count 2 2006.246.08:11:11.42#ibcon#read 3, iclass 16, count 2 2006.246.08:11:11.42#ibcon#about to read 4, iclass 16, count 2 2006.246.08:11:11.42#ibcon#read 4, iclass 16, count 2 2006.246.08:11:11.42#ibcon#about to read 5, iclass 16, count 2 2006.246.08:11:11.42#ibcon#read 5, iclass 16, count 2 2006.246.08:11:11.42#ibcon#about to read 6, iclass 16, count 2 2006.246.08:11:11.42#ibcon#read 6, iclass 16, count 2 2006.246.08:11:11.42#ibcon#end of sib2, iclass 16, count 2 2006.246.08:11:11.42#ibcon#*after write, iclass 16, count 2 2006.246.08:11:11.42#ibcon#*before return 0, iclass 16, count 2 2006.246.08:11:11.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:11.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:11:11.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.08:11:11.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:11.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:11.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:11.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:11.54#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:11:11.54#ibcon#first serial, iclass 16, count 0 2006.246.08:11:11.54#ibcon#enter sib2, iclass 16, count 0 2006.246.08:11:11.54#ibcon#flushed, iclass 16, count 0 2006.246.08:11:11.54#ibcon#about to write, iclass 16, count 0 2006.246.08:11:11.54#ibcon#wrote, iclass 16, count 0 2006.246.08:11:11.54#ibcon#about to read 3, iclass 16, count 0 2006.246.08:11:11.56#ibcon#read 3, iclass 16, count 0 2006.246.08:11:11.56#ibcon#about to read 4, iclass 16, count 0 2006.246.08:11:11.56#ibcon#read 4, iclass 16, count 0 2006.246.08:11:11.56#ibcon#about to read 5, iclass 16, count 0 2006.246.08:11:11.56#ibcon#read 5, iclass 16, count 0 2006.246.08:11:11.56#ibcon#about to read 6, iclass 16, count 0 2006.246.08:11:11.56#ibcon#read 6, iclass 16, count 0 2006.246.08:11:11.56#ibcon#end of sib2, iclass 16, count 0 2006.246.08:11:11.56#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:11:11.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:11:11.56#ibcon#[27=USB\r\n] 2006.246.08:11:11.56#ibcon#*before write, iclass 16, count 0 2006.246.08:11:11.56#ibcon#enter sib2, iclass 16, count 0 2006.246.08:11:11.56#ibcon#flushed, iclass 16, count 0 2006.246.08:11:11.56#ibcon#about to write, iclass 16, count 0 2006.246.08:11:11.56#ibcon#wrote, iclass 16, count 0 2006.246.08:11:11.56#ibcon#about to read 3, iclass 16, count 0 2006.246.08:11:11.59#ibcon#read 3, iclass 16, count 0 2006.246.08:11:11.59#ibcon#about to read 4, iclass 16, count 0 2006.246.08:11:11.59#ibcon#read 4, iclass 16, count 0 2006.246.08:11:11.59#ibcon#about to read 5, iclass 16, count 0 2006.246.08:11:11.59#ibcon#read 5, iclass 16, count 0 2006.246.08:11:11.59#ibcon#about to read 6, iclass 16, count 0 2006.246.08:11:11.59#ibcon#read 6, iclass 16, count 0 2006.246.08:11:11.59#ibcon#end of sib2, iclass 16, count 0 2006.246.08:11:11.59#ibcon#*after write, iclass 16, count 0 2006.246.08:11:11.59#ibcon#*before return 0, iclass 16, count 0 2006.246.08:11:11.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:11.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:11:11.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:11:11.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:11:11.59$vc4f8/vblo=4,712.99 2006.246.08:11:11.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.08:11:11.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.08:11:11.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:11.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:11.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:11.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:11.59#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:11:11.59#ibcon#first serial, iclass 18, count 0 2006.246.08:11:11.59#ibcon#enter sib2, iclass 18, count 0 2006.246.08:11:11.59#ibcon#flushed, iclass 18, count 0 2006.246.08:11:11.59#ibcon#about to write, iclass 18, count 0 2006.246.08:11:11.59#ibcon#wrote, iclass 18, count 0 2006.246.08:11:11.59#ibcon#about to read 3, iclass 18, count 0 2006.246.08:11:11.61#ibcon#read 3, iclass 18, count 0 2006.246.08:11:11.61#ibcon#about to read 4, iclass 18, count 0 2006.246.08:11:11.61#ibcon#read 4, iclass 18, count 0 2006.246.08:11:11.61#ibcon#about to read 5, iclass 18, count 0 2006.246.08:11:11.61#ibcon#read 5, iclass 18, count 0 2006.246.08:11:11.61#ibcon#about to read 6, iclass 18, count 0 2006.246.08:11:11.61#ibcon#read 6, iclass 18, count 0 2006.246.08:11:11.61#ibcon#end of sib2, iclass 18, count 0 2006.246.08:11:11.61#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:11:11.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:11:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:11:11.61#ibcon#*before write, iclass 18, count 0 2006.246.08:11:11.61#ibcon#enter sib2, iclass 18, count 0 2006.246.08:11:11.61#ibcon#flushed, iclass 18, count 0 2006.246.08:11:11.61#ibcon#about to write, iclass 18, count 0 2006.246.08:11:11.61#ibcon#wrote, iclass 18, count 0 2006.246.08:11:11.61#ibcon#about to read 3, iclass 18, count 0 2006.246.08:11:11.65#ibcon#read 3, iclass 18, count 0 2006.246.08:11:11.65#ibcon#about to read 4, iclass 18, count 0 2006.246.08:11:11.65#ibcon#read 4, iclass 18, count 0 2006.246.08:11:11.65#ibcon#about to read 5, iclass 18, count 0 2006.246.08:11:11.65#ibcon#read 5, iclass 18, count 0 2006.246.08:11:11.65#ibcon#about to read 6, iclass 18, count 0 2006.246.08:11:11.65#ibcon#read 6, iclass 18, count 0 2006.246.08:11:11.65#ibcon#end of sib2, iclass 18, count 0 2006.246.08:11:11.65#ibcon#*after write, iclass 18, count 0 2006.246.08:11:11.65#ibcon#*before return 0, iclass 18, count 0 2006.246.08:11:11.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:11.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:11:11.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:11:11.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:11:11.65$vc4f8/vb=4,4 2006.246.08:11:11.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.08:11:11.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.08:11:11.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:11.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:11.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:11.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:11.71#ibcon#enter wrdev, iclass 20, count 2 2006.246.08:11:11.71#ibcon#first serial, iclass 20, count 2 2006.246.08:11:11.71#ibcon#enter sib2, iclass 20, count 2 2006.246.08:11:11.71#ibcon#flushed, iclass 20, count 2 2006.246.08:11:11.71#ibcon#about to write, iclass 20, count 2 2006.246.08:11:11.71#ibcon#wrote, iclass 20, count 2 2006.246.08:11:11.71#ibcon#about to read 3, iclass 20, count 2 2006.246.08:11:11.73#ibcon#read 3, iclass 20, count 2 2006.246.08:11:11.73#ibcon#about to read 4, iclass 20, count 2 2006.246.08:11:11.73#ibcon#read 4, iclass 20, count 2 2006.246.08:11:11.73#ibcon#about to read 5, iclass 20, count 2 2006.246.08:11:11.73#ibcon#read 5, iclass 20, count 2 2006.246.08:11:11.73#ibcon#about to read 6, iclass 20, count 2 2006.246.08:11:11.73#ibcon#read 6, iclass 20, count 2 2006.246.08:11:11.73#ibcon#end of sib2, iclass 20, count 2 2006.246.08:11:11.73#ibcon#*mode == 0, iclass 20, count 2 2006.246.08:11:11.73#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.08:11:11.73#ibcon#[27=AT04-04\r\n] 2006.246.08:11:11.73#ibcon#*before write, iclass 20, count 2 2006.246.08:11:11.73#ibcon#enter sib2, iclass 20, count 2 2006.246.08:11:11.73#ibcon#flushed, iclass 20, count 2 2006.246.08:11:11.73#ibcon#about to write, iclass 20, count 2 2006.246.08:11:11.73#ibcon#wrote, iclass 20, count 2 2006.246.08:11:11.73#ibcon#about to read 3, iclass 20, count 2 2006.246.08:11:11.76#ibcon#read 3, iclass 20, count 2 2006.246.08:11:11.76#ibcon#about to read 4, iclass 20, count 2 2006.246.08:11:11.76#ibcon#read 4, iclass 20, count 2 2006.246.08:11:11.76#ibcon#about to read 5, iclass 20, count 2 2006.246.08:11:11.76#ibcon#read 5, iclass 20, count 2 2006.246.08:11:11.76#ibcon#about to read 6, iclass 20, count 2 2006.246.08:11:11.76#ibcon#read 6, iclass 20, count 2 2006.246.08:11:11.76#ibcon#end of sib2, iclass 20, count 2 2006.246.08:11:11.76#ibcon#*after write, iclass 20, count 2 2006.246.08:11:11.76#ibcon#*before return 0, iclass 20, count 2 2006.246.08:11:11.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:11.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:11:11.76#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.08:11:11.76#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:11.76#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:11.88#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:11.88#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:11.88#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:11:11.88#ibcon#first serial, iclass 20, count 0 2006.246.08:11:11.88#ibcon#enter sib2, iclass 20, count 0 2006.246.08:11:11.88#ibcon#flushed, iclass 20, count 0 2006.246.08:11:11.88#ibcon#about to write, iclass 20, count 0 2006.246.08:11:11.88#ibcon#wrote, iclass 20, count 0 2006.246.08:11:11.88#ibcon#about to read 3, iclass 20, count 0 2006.246.08:11:11.90#ibcon#read 3, iclass 20, count 0 2006.246.08:11:11.90#ibcon#about to read 4, iclass 20, count 0 2006.246.08:11:11.90#ibcon#read 4, iclass 20, count 0 2006.246.08:11:11.90#ibcon#about to read 5, iclass 20, count 0 2006.246.08:11:11.90#ibcon#read 5, iclass 20, count 0 2006.246.08:11:11.90#ibcon#about to read 6, iclass 20, count 0 2006.246.08:11:11.90#ibcon#read 6, iclass 20, count 0 2006.246.08:11:11.90#ibcon#end of sib2, iclass 20, count 0 2006.246.08:11:11.90#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:11:11.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:11:11.90#ibcon#[27=USB\r\n] 2006.246.08:11:11.90#ibcon#*before write, iclass 20, count 0 2006.246.08:11:11.90#ibcon#enter sib2, iclass 20, count 0 2006.246.08:11:11.90#ibcon#flushed, iclass 20, count 0 2006.246.08:11:11.90#ibcon#about to write, iclass 20, count 0 2006.246.08:11:11.90#ibcon#wrote, iclass 20, count 0 2006.246.08:11:11.90#ibcon#about to read 3, iclass 20, count 0 2006.246.08:11:11.93#ibcon#read 3, iclass 20, count 0 2006.246.08:11:11.93#ibcon#about to read 4, iclass 20, count 0 2006.246.08:11:11.93#ibcon#read 4, iclass 20, count 0 2006.246.08:11:11.93#ibcon#about to read 5, iclass 20, count 0 2006.246.08:11:11.93#ibcon#read 5, iclass 20, count 0 2006.246.08:11:11.93#ibcon#about to read 6, iclass 20, count 0 2006.246.08:11:11.93#ibcon#read 6, iclass 20, count 0 2006.246.08:11:11.93#ibcon#end of sib2, iclass 20, count 0 2006.246.08:11:11.93#ibcon#*after write, iclass 20, count 0 2006.246.08:11:11.93#ibcon#*before return 0, iclass 20, count 0 2006.246.08:11:11.93#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:11.93#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:11:11.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:11:11.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:11:11.93$vc4f8/vblo=5,744.99 2006.246.08:11:11.93#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.08:11:11.93#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.08:11:11.93#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:11.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:11.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:11.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:11.93#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:11:11.93#ibcon#first serial, iclass 22, count 0 2006.246.08:11:11.93#ibcon#enter sib2, iclass 22, count 0 2006.246.08:11:11.93#ibcon#flushed, iclass 22, count 0 2006.246.08:11:11.93#ibcon#about to write, iclass 22, count 0 2006.246.08:11:11.93#ibcon#wrote, iclass 22, count 0 2006.246.08:11:11.93#ibcon#about to read 3, iclass 22, count 0 2006.246.08:11:11.95#ibcon#read 3, iclass 22, count 0 2006.246.08:11:11.95#ibcon#about to read 4, iclass 22, count 0 2006.246.08:11:11.95#ibcon#read 4, iclass 22, count 0 2006.246.08:11:11.95#ibcon#about to read 5, iclass 22, count 0 2006.246.08:11:11.95#ibcon#read 5, iclass 22, count 0 2006.246.08:11:11.95#ibcon#about to read 6, iclass 22, count 0 2006.246.08:11:11.95#ibcon#read 6, iclass 22, count 0 2006.246.08:11:11.95#ibcon#end of sib2, iclass 22, count 0 2006.246.08:11:11.95#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:11:11.95#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:11:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:11:11.95#ibcon#*before write, iclass 22, count 0 2006.246.08:11:11.95#ibcon#enter sib2, iclass 22, count 0 2006.246.08:11:11.95#ibcon#flushed, iclass 22, count 0 2006.246.08:11:11.95#ibcon#about to write, iclass 22, count 0 2006.246.08:11:11.95#ibcon#wrote, iclass 22, count 0 2006.246.08:11:11.95#ibcon#about to read 3, iclass 22, count 0 2006.246.08:11:11.99#ibcon#read 3, iclass 22, count 0 2006.246.08:11:11.99#ibcon#about to read 4, iclass 22, count 0 2006.246.08:11:11.99#ibcon#read 4, iclass 22, count 0 2006.246.08:11:11.99#ibcon#about to read 5, iclass 22, count 0 2006.246.08:11:11.99#ibcon#read 5, iclass 22, count 0 2006.246.08:11:11.99#ibcon#about to read 6, iclass 22, count 0 2006.246.08:11:11.99#ibcon#read 6, iclass 22, count 0 2006.246.08:11:11.99#ibcon#end of sib2, iclass 22, count 0 2006.246.08:11:11.99#ibcon#*after write, iclass 22, count 0 2006.246.08:11:11.99#ibcon#*before return 0, iclass 22, count 0 2006.246.08:11:11.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:11.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:11:11.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:11:11.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:11:11.99$vc4f8/vb=5,3 2006.246.08:11:11.99#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.08:11:11.99#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.08:11:11.99#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:11.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:12.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:12.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:12.05#ibcon#enter wrdev, iclass 24, count 2 2006.246.08:11:12.05#ibcon#first serial, iclass 24, count 2 2006.246.08:11:12.05#ibcon#enter sib2, iclass 24, count 2 2006.246.08:11:12.05#ibcon#flushed, iclass 24, count 2 2006.246.08:11:12.05#ibcon#about to write, iclass 24, count 2 2006.246.08:11:12.05#ibcon#wrote, iclass 24, count 2 2006.246.08:11:12.05#ibcon#about to read 3, iclass 24, count 2 2006.246.08:11:12.07#ibcon#read 3, iclass 24, count 2 2006.246.08:11:12.07#ibcon#about to read 4, iclass 24, count 2 2006.246.08:11:12.07#ibcon#read 4, iclass 24, count 2 2006.246.08:11:12.07#ibcon#about to read 5, iclass 24, count 2 2006.246.08:11:12.07#ibcon#read 5, iclass 24, count 2 2006.246.08:11:12.07#ibcon#about to read 6, iclass 24, count 2 2006.246.08:11:12.07#ibcon#read 6, iclass 24, count 2 2006.246.08:11:12.07#ibcon#end of sib2, iclass 24, count 2 2006.246.08:11:12.07#ibcon#*mode == 0, iclass 24, count 2 2006.246.08:11:12.07#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.08:11:12.07#ibcon#[27=AT05-03\r\n] 2006.246.08:11:12.07#ibcon#*before write, iclass 24, count 2 2006.246.08:11:12.07#ibcon#enter sib2, iclass 24, count 2 2006.246.08:11:12.07#ibcon#flushed, iclass 24, count 2 2006.246.08:11:12.07#ibcon#about to write, iclass 24, count 2 2006.246.08:11:12.07#ibcon#wrote, iclass 24, count 2 2006.246.08:11:12.07#ibcon#about to read 3, iclass 24, count 2 2006.246.08:11:12.10#ibcon#read 3, iclass 24, count 2 2006.246.08:11:12.10#ibcon#about to read 4, iclass 24, count 2 2006.246.08:11:12.10#ibcon#read 4, iclass 24, count 2 2006.246.08:11:12.10#ibcon#about to read 5, iclass 24, count 2 2006.246.08:11:12.10#ibcon#read 5, iclass 24, count 2 2006.246.08:11:12.10#ibcon#about to read 6, iclass 24, count 2 2006.246.08:11:12.10#ibcon#read 6, iclass 24, count 2 2006.246.08:11:12.10#ibcon#end of sib2, iclass 24, count 2 2006.246.08:11:12.10#ibcon#*after write, iclass 24, count 2 2006.246.08:11:12.10#ibcon#*before return 0, iclass 24, count 2 2006.246.08:11:12.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:12.10#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:11:12.10#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.08:11:12.10#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:12.10#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:12.22#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:12.22#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:12.22#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:11:12.22#ibcon#first serial, iclass 24, count 0 2006.246.08:11:12.22#ibcon#enter sib2, iclass 24, count 0 2006.246.08:11:12.22#ibcon#flushed, iclass 24, count 0 2006.246.08:11:12.22#ibcon#about to write, iclass 24, count 0 2006.246.08:11:12.22#ibcon#wrote, iclass 24, count 0 2006.246.08:11:12.22#ibcon#about to read 3, iclass 24, count 0 2006.246.08:11:12.24#ibcon#read 3, iclass 24, count 0 2006.246.08:11:12.24#ibcon#about to read 4, iclass 24, count 0 2006.246.08:11:12.24#ibcon#read 4, iclass 24, count 0 2006.246.08:11:12.24#ibcon#about to read 5, iclass 24, count 0 2006.246.08:11:12.24#ibcon#read 5, iclass 24, count 0 2006.246.08:11:12.24#ibcon#about to read 6, iclass 24, count 0 2006.246.08:11:12.24#ibcon#read 6, iclass 24, count 0 2006.246.08:11:12.24#ibcon#end of sib2, iclass 24, count 0 2006.246.08:11:12.24#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:11:12.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:11:12.24#ibcon#[27=USB\r\n] 2006.246.08:11:12.24#ibcon#*before write, iclass 24, count 0 2006.246.08:11:12.24#ibcon#enter sib2, iclass 24, count 0 2006.246.08:11:12.24#ibcon#flushed, iclass 24, count 0 2006.246.08:11:12.24#ibcon#about to write, iclass 24, count 0 2006.246.08:11:12.24#ibcon#wrote, iclass 24, count 0 2006.246.08:11:12.24#ibcon#about to read 3, iclass 24, count 0 2006.246.08:11:12.27#ibcon#read 3, iclass 24, count 0 2006.246.08:11:12.27#ibcon#about to read 4, iclass 24, count 0 2006.246.08:11:12.27#ibcon#read 4, iclass 24, count 0 2006.246.08:11:12.27#ibcon#about to read 5, iclass 24, count 0 2006.246.08:11:12.27#ibcon#read 5, iclass 24, count 0 2006.246.08:11:12.27#ibcon#about to read 6, iclass 24, count 0 2006.246.08:11:12.27#ibcon#read 6, iclass 24, count 0 2006.246.08:11:12.27#ibcon#end of sib2, iclass 24, count 0 2006.246.08:11:12.27#ibcon#*after write, iclass 24, count 0 2006.246.08:11:12.27#ibcon#*before return 0, iclass 24, count 0 2006.246.08:11:12.27#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:12.27#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:11:12.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:11:12.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:11:12.27$vc4f8/vblo=6,752.99 2006.246.08:11:12.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.08:11:12.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.08:11:12.27#ibcon#ireg 17 cls_cnt 0 2006.246.08:11:12.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:12.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:12.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:12.27#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:11:12.27#ibcon#first serial, iclass 26, count 0 2006.246.08:11:12.27#ibcon#enter sib2, iclass 26, count 0 2006.246.08:11:12.27#ibcon#flushed, iclass 26, count 0 2006.246.08:11:12.27#ibcon#about to write, iclass 26, count 0 2006.246.08:11:12.27#ibcon#wrote, iclass 26, count 0 2006.246.08:11:12.27#ibcon#about to read 3, iclass 26, count 0 2006.246.08:11:12.29#ibcon#read 3, iclass 26, count 0 2006.246.08:11:12.29#ibcon#about to read 4, iclass 26, count 0 2006.246.08:11:12.29#ibcon#read 4, iclass 26, count 0 2006.246.08:11:12.29#ibcon#about to read 5, iclass 26, count 0 2006.246.08:11:12.29#ibcon#read 5, iclass 26, count 0 2006.246.08:11:12.29#ibcon#about to read 6, iclass 26, count 0 2006.246.08:11:12.29#ibcon#read 6, iclass 26, count 0 2006.246.08:11:12.29#ibcon#end of sib2, iclass 26, count 0 2006.246.08:11:12.29#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:11:12.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:11:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:11:12.29#ibcon#*before write, iclass 26, count 0 2006.246.08:11:12.29#ibcon#enter sib2, iclass 26, count 0 2006.246.08:11:12.29#ibcon#flushed, iclass 26, count 0 2006.246.08:11:12.29#ibcon#about to write, iclass 26, count 0 2006.246.08:11:12.29#ibcon#wrote, iclass 26, count 0 2006.246.08:11:12.29#ibcon#about to read 3, iclass 26, count 0 2006.246.08:11:12.33#ibcon#read 3, iclass 26, count 0 2006.246.08:11:12.33#ibcon#about to read 4, iclass 26, count 0 2006.246.08:11:12.33#ibcon#read 4, iclass 26, count 0 2006.246.08:11:12.33#ibcon#about to read 5, iclass 26, count 0 2006.246.08:11:12.33#ibcon#read 5, iclass 26, count 0 2006.246.08:11:12.33#ibcon#about to read 6, iclass 26, count 0 2006.246.08:11:12.33#ibcon#read 6, iclass 26, count 0 2006.246.08:11:12.33#ibcon#end of sib2, iclass 26, count 0 2006.246.08:11:12.33#ibcon#*after write, iclass 26, count 0 2006.246.08:11:12.33#ibcon#*before return 0, iclass 26, count 0 2006.246.08:11:12.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:12.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:11:12.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:11:12.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:11:12.33$vc4f8/vb=6,3 2006.246.08:11:12.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.08:11:12.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.08:11:12.33#ibcon#ireg 11 cls_cnt 2 2006.246.08:11:12.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:12.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:12.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:12.39#ibcon#enter wrdev, iclass 28, count 2 2006.246.08:11:12.39#ibcon#first serial, iclass 28, count 2 2006.246.08:11:12.39#ibcon#enter sib2, iclass 28, count 2 2006.246.08:11:12.39#ibcon#flushed, iclass 28, count 2 2006.246.08:11:12.39#ibcon#about to write, iclass 28, count 2 2006.246.08:11:12.39#ibcon#wrote, iclass 28, count 2 2006.246.08:11:12.39#ibcon#about to read 3, iclass 28, count 2 2006.246.08:11:12.41#ibcon#read 3, iclass 28, count 2 2006.246.08:11:12.41#ibcon#about to read 4, iclass 28, count 2 2006.246.08:11:12.41#ibcon#read 4, iclass 28, count 2 2006.246.08:11:12.41#ibcon#about to read 5, iclass 28, count 2 2006.246.08:11:12.41#ibcon#read 5, iclass 28, count 2 2006.246.08:11:12.41#ibcon#about to read 6, iclass 28, count 2 2006.246.08:11:12.41#ibcon#read 6, iclass 28, count 2 2006.246.08:11:12.41#ibcon#end of sib2, iclass 28, count 2 2006.246.08:11:12.41#ibcon#*mode == 0, iclass 28, count 2 2006.246.08:11:12.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.08:11:12.41#ibcon#[27=AT06-03\r\n] 2006.246.08:11:12.41#ibcon#*before write, iclass 28, count 2 2006.246.08:11:12.41#ibcon#enter sib2, iclass 28, count 2 2006.246.08:11:12.41#ibcon#flushed, iclass 28, count 2 2006.246.08:11:12.41#ibcon#about to write, iclass 28, count 2 2006.246.08:11:12.41#ibcon#wrote, iclass 28, count 2 2006.246.08:11:12.41#ibcon#about to read 3, iclass 28, count 2 2006.246.08:11:12.44#ibcon#read 3, iclass 28, count 2 2006.246.08:11:12.44#ibcon#about to read 4, iclass 28, count 2 2006.246.08:11:12.44#ibcon#read 4, iclass 28, count 2 2006.246.08:11:12.44#ibcon#about to read 5, iclass 28, count 2 2006.246.08:11:12.44#ibcon#read 5, iclass 28, count 2 2006.246.08:11:12.44#ibcon#about to read 6, iclass 28, count 2 2006.246.08:11:12.44#ibcon#read 6, iclass 28, count 2 2006.246.08:11:12.44#ibcon#end of sib2, iclass 28, count 2 2006.246.08:11:12.44#ibcon#*after write, iclass 28, count 2 2006.246.08:11:12.44#ibcon#*before return 0, iclass 28, count 2 2006.246.08:11:12.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:12.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:11:12.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.08:11:12.44#ibcon#ireg 7 cls_cnt 0 2006.246.08:11:12.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:12.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:12.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:12.56#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:11:12.56#ibcon#first serial, iclass 28, count 0 2006.246.08:11:12.56#ibcon#enter sib2, iclass 28, count 0 2006.246.08:11:12.56#ibcon#flushed, iclass 28, count 0 2006.246.08:11:12.56#ibcon#about to write, iclass 28, count 0 2006.246.08:11:12.56#ibcon#wrote, iclass 28, count 0 2006.246.08:11:12.56#ibcon#about to read 3, iclass 28, count 0 2006.246.08:11:12.58#ibcon#read 3, iclass 28, count 0 2006.246.08:11:12.58#ibcon#about to read 4, iclass 28, count 0 2006.246.08:11:12.58#ibcon#read 4, iclass 28, count 0 2006.246.08:11:12.58#ibcon#about to read 5, iclass 28, count 0 2006.246.08:11:12.58#ibcon#read 5, iclass 28, count 0 2006.246.08:11:12.58#ibcon#about to read 6, iclass 28, count 0 2006.246.08:11:12.58#ibcon#read 6, iclass 28, count 0 2006.246.08:11:12.58#ibcon#end of sib2, iclass 28, count 0 2006.246.08:11:12.58#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:11:12.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:11:12.58#ibcon#[27=USB\r\n] 2006.246.08:11:12.58#ibcon#*before write, iclass 28, count 0 2006.246.08:11:12.58#ibcon#enter sib2, iclass 28, count 0 2006.246.08:11:12.58#ibcon#flushed, iclass 28, count 0 2006.246.08:11:12.58#ibcon#about to write, iclass 28, count 0 2006.246.08:11:12.58#ibcon#wrote, iclass 28, count 0 2006.246.08:11:12.58#ibcon#about to read 3, iclass 28, count 0 2006.246.08:11:12.61#ibcon#read 3, iclass 28, count 0 2006.246.08:11:12.61#ibcon#about to read 4, iclass 28, count 0 2006.246.08:11:12.61#ibcon#read 4, iclass 28, count 0 2006.246.08:11:12.61#ibcon#about to read 5, iclass 28, count 0 2006.246.08:11:12.61#ibcon#read 5, iclass 28, count 0 2006.246.08:11:12.61#ibcon#about to read 6, iclass 28, count 0 2006.246.08:11:12.61#ibcon#read 6, iclass 28, count 0 2006.246.08:11:12.61#ibcon#end of sib2, iclass 28, count 0 2006.246.08:11:12.61#ibcon#*after write, iclass 28, count 0 2006.246.08:11:12.61#ibcon#*before return 0, iclass 28, count 0 2006.246.08:11:12.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:12.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:11:12.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:11:12.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:11:12.61$vc4f8/vabw=wide 2006.246.08:11:12.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.08:11:12.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.08:11:12.61#ibcon#ireg 8 cls_cnt 0 2006.246.08:11:12.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:12.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:12.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:12.61#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:11:12.61#ibcon#first serial, iclass 30, count 0 2006.246.08:11:12.61#ibcon#enter sib2, iclass 30, count 0 2006.246.08:11:12.61#ibcon#flushed, iclass 30, count 0 2006.246.08:11:12.61#ibcon#about to write, iclass 30, count 0 2006.246.08:11:12.61#ibcon#wrote, iclass 30, count 0 2006.246.08:11:12.61#ibcon#about to read 3, iclass 30, count 0 2006.246.08:11:12.63#ibcon#read 3, iclass 30, count 0 2006.246.08:11:12.63#ibcon#about to read 4, iclass 30, count 0 2006.246.08:11:12.63#ibcon#read 4, iclass 30, count 0 2006.246.08:11:12.63#ibcon#about to read 5, iclass 30, count 0 2006.246.08:11:12.63#ibcon#read 5, iclass 30, count 0 2006.246.08:11:12.63#ibcon#about to read 6, iclass 30, count 0 2006.246.08:11:12.63#ibcon#read 6, iclass 30, count 0 2006.246.08:11:12.63#ibcon#end of sib2, iclass 30, count 0 2006.246.08:11:12.63#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:11:12.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:11:12.63#ibcon#[25=BW32\r\n] 2006.246.08:11:12.63#ibcon#*before write, iclass 30, count 0 2006.246.08:11:12.63#ibcon#enter sib2, iclass 30, count 0 2006.246.08:11:12.63#ibcon#flushed, iclass 30, count 0 2006.246.08:11:12.63#ibcon#about to write, iclass 30, count 0 2006.246.08:11:12.63#ibcon#wrote, iclass 30, count 0 2006.246.08:11:12.63#ibcon#about to read 3, iclass 30, count 0 2006.246.08:11:12.66#ibcon#read 3, iclass 30, count 0 2006.246.08:11:12.66#ibcon#about to read 4, iclass 30, count 0 2006.246.08:11:12.66#ibcon#read 4, iclass 30, count 0 2006.246.08:11:12.66#ibcon#about to read 5, iclass 30, count 0 2006.246.08:11:12.66#ibcon#read 5, iclass 30, count 0 2006.246.08:11:12.66#ibcon#about to read 6, iclass 30, count 0 2006.246.08:11:12.66#ibcon#read 6, iclass 30, count 0 2006.246.08:11:12.66#ibcon#end of sib2, iclass 30, count 0 2006.246.08:11:12.66#ibcon#*after write, iclass 30, count 0 2006.246.08:11:12.66#ibcon#*before return 0, iclass 30, count 0 2006.246.08:11:12.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:12.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:11:12.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:11:12.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:11:12.66$vc4f8/vbbw=wide 2006.246.08:11:12.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:11:12.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:11:12.66#ibcon#ireg 8 cls_cnt 0 2006.246.08:11:12.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:11:12.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:11:12.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:11:12.73#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:11:12.73#ibcon#first serial, iclass 32, count 0 2006.246.08:11:12.73#ibcon#enter sib2, iclass 32, count 0 2006.246.08:11:12.73#ibcon#flushed, iclass 32, count 0 2006.246.08:11:12.73#ibcon#about to write, iclass 32, count 0 2006.246.08:11:12.73#ibcon#wrote, iclass 32, count 0 2006.246.08:11:12.73#ibcon#about to read 3, iclass 32, count 0 2006.246.08:11:12.75#ibcon#read 3, iclass 32, count 0 2006.246.08:11:12.75#ibcon#about to read 4, iclass 32, count 0 2006.246.08:11:12.75#ibcon#read 4, iclass 32, count 0 2006.246.08:11:12.75#ibcon#about to read 5, iclass 32, count 0 2006.246.08:11:12.75#ibcon#read 5, iclass 32, count 0 2006.246.08:11:12.75#ibcon#about to read 6, iclass 32, count 0 2006.246.08:11:12.75#ibcon#read 6, iclass 32, count 0 2006.246.08:11:12.75#ibcon#end of sib2, iclass 32, count 0 2006.246.08:11:12.75#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:11:12.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:11:12.75#ibcon#[27=BW32\r\n] 2006.246.08:11:12.75#ibcon#*before write, iclass 32, count 0 2006.246.08:11:12.75#ibcon#enter sib2, iclass 32, count 0 2006.246.08:11:12.75#ibcon#flushed, iclass 32, count 0 2006.246.08:11:12.75#ibcon#about to write, iclass 32, count 0 2006.246.08:11:12.75#ibcon#wrote, iclass 32, count 0 2006.246.08:11:12.75#ibcon#about to read 3, iclass 32, count 0 2006.246.08:11:12.78#ibcon#read 3, iclass 32, count 0 2006.246.08:11:12.78#ibcon#about to read 4, iclass 32, count 0 2006.246.08:11:12.78#ibcon#read 4, iclass 32, count 0 2006.246.08:11:12.78#ibcon#about to read 5, iclass 32, count 0 2006.246.08:11:12.78#ibcon#read 5, iclass 32, count 0 2006.246.08:11:12.78#ibcon#about to read 6, iclass 32, count 0 2006.246.08:11:12.78#ibcon#read 6, iclass 32, count 0 2006.246.08:11:12.78#ibcon#end of sib2, iclass 32, count 0 2006.246.08:11:12.78#ibcon#*after write, iclass 32, count 0 2006.246.08:11:12.78#ibcon#*before return 0, iclass 32, count 0 2006.246.08:11:12.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:11:12.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:11:12.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:11:12.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:11:12.78$4f8m12a/ifd4f 2006.246.08:11:12.78$ifd4f/lo= 2006.246.08:11:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:11:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:11:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:11:12.78$ifd4f/patch= 2006.246.08:11:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:11:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:11:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:11:12.78$4f8m12a/"form=m,16.000,1:2 2006.246.08:11:12.78$4f8m12a/"tpicd 2006.246.08:11:12.78$4f8m12a/echo=off 2006.246.08:11:12.78$4f8m12a/xlog=off 2006.246.08:11:12.78:!2006.246.08:12:20 2006.246.08:11:58.14#trakl#Source acquired 2006.246.08:11:58.14#flagr#flagr/antenna,acquired 2006.246.08:12:20.00:preob 2006.246.08:12:20.14/onsource/TRACKING 2006.246.08:12:20.14:!2006.246.08:12:30 2006.246.08:12:30.00:data_valid=on 2006.246.08:12:30.00:midob 2006.246.08:12:31.14/onsource/TRACKING 2006.246.08:12:31.14/wx/26.41,1005.7,75 2006.246.08:12:31.26/cable/+6.4149E-03 2006.246.08:12:32.35/va/01,08,usb,yes,32,33 2006.246.08:12:32.35/va/02,07,usb,yes,32,33 2006.246.08:12:32.35/va/03,06,usb,yes,34,34 2006.246.08:12:32.35/va/04,07,usb,yes,33,35 2006.246.08:12:32.35/va/05,07,usb,yes,34,36 2006.246.08:12:32.35/va/06,07,usb,yes,30,30 2006.246.08:12:32.35/va/07,07,usb,yes,30,30 2006.246.08:12:32.35/va/08,08,usb,yes,26,26 2006.246.08:12:32.58/valo/01,532.99,yes,locked 2006.246.08:12:32.58/valo/02,572.99,yes,locked 2006.246.08:12:32.58/valo/03,672.99,yes,locked 2006.246.08:12:32.58/valo/04,832.99,yes,locked 2006.246.08:12:32.58/valo/05,652.99,yes,locked 2006.246.08:12:32.58/valo/06,772.99,yes,locked 2006.246.08:12:32.58/valo/07,832.99,yes,locked 2006.246.08:12:32.58/valo/08,852.99,yes,locked 2006.246.08:12:33.67/vb/01,04,usb,yes,31,30 2006.246.08:12:33.67/vb/02,04,usb,yes,33,34 2006.246.08:12:33.67/vb/03,04,usb,yes,29,33 2006.246.08:12:33.67/vb/04,04,usb,yes,30,30 2006.246.08:12:33.67/vb/05,03,usb,yes,35,40 2006.246.08:12:33.67/vb/06,03,usb,yes,36,40 2006.246.08:12:33.67/vb/07,04,usb,yes,32,31 2006.246.08:12:33.67/vb/08,03,usb,yes,36,40 2006.246.08:12:33.91/vblo/01,632.99,yes,locked 2006.246.08:12:33.91/vblo/02,640.99,yes,locked 2006.246.08:12:33.91/vblo/03,656.99,yes,locked 2006.246.08:12:33.91/vblo/04,712.99,yes,locked 2006.246.08:12:33.91/vblo/05,744.99,yes,locked 2006.246.08:12:33.91/vblo/06,752.99,yes,locked 2006.246.08:12:33.91/vblo/07,734.99,yes,locked 2006.246.08:12:33.91/vblo/08,744.99,yes,locked 2006.246.08:12:34.06/vabw/8 2006.246.08:12:34.21/vbbw/8 2006.246.08:12:34.37/xfe/off,on,13.0 2006.246.08:12:34.75/ifatt/23,28,28,28 2006.246.08:12:35.07/fmout-gps/S +4.39E-07 2006.246.08:12:35.11:!2006.246.08:13:40 2006.246.08:13:40.01:data_valid=off 2006.246.08:13:40.02:postob 2006.246.08:13:40.13/cable/+6.4142E-03 2006.246.08:13:40.14/wx/26.39,1005.7,75 2006.246.08:13:41.08/fmout-gps/S +4.40E-07 2006.246.08:13:41.08:scan_name=246-0814,k06246,60 2006.246.08:13:41.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.246.08:13:42.15#flagr#flagr/antenna,new-source 2006.246.08:13:42.15:checkk5 2006.246.08:13:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:13:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:13:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:13:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:13:44.01/chk_obsdata//k5ts1/T2460812??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.246.08:13:44.37/chk_obsdata//k5ts2/T2460812??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.246.08:13:44.74/chk_obsdata//k5ts3/T2460812??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.246.08:13:45.11/chk_obsdata//k5ts4/T2460812??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.246.08:13:45.81/k5log//k5ts1_log_newline 2006.246.08:13:46.50/k5log//k5ts2_log_newline 2006.246.08:13:47.19/k5log//k5ts3_log_newline 2006.246.08:13:47.87/k5log//k5ts4_log_newline 2006.246.08:13:47.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:13:47.90:4f8m12a=2 2006.246.08:13:47.90$4f8m12a/echo=on 2006.246.08:13:47.90$4f8m12a/pcalon 2006.246.08:13:47.90$pcalon/"no phase cal control is implemented here 2006.246.08:13:47.90$4f8m12a/"tpicd=stop 2006.246.08:13:47.90$4f8m12a/vc4f8 2006.246.08:13:47.90$vc4f8/valo=1,532.99 2006.246.08:13:47.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:13:47.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:13:47.90#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:47.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:47.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:47.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:47.90#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:13:47.90#ibcon#first serial, iclass 23, count 0 2006.246.08:13:47.90#ibcon#enter sib2, iclass 23, count 0 2006.246.08:13:47.90#ibcon#flushed, iclass 23, count 0 2006.246.08:13:47.90#ibcon#about to write, iclass 23, count 0 2006.246.08:13:47.90#ibcon#wrote, iclass 23, count 0 2006.246.08:13:47.90#ibcon#about to read 3, iclass 23, count 0 2006.246.08:13:47.91#ibcon#read 3, iclass 23, count 0 2006.246.08:13:47.91#ibcon#about to read 4, iclass 23, count 0 2006.246.08:13:47.91#ibcon#read 4, iclass 23, count 0 2006.246.08:13:47.91#ibcon#about to read 5, iclass 23, count 0 2006.246.08:13:47.91#ibcon#read 5, iclass 23, count 0 2006.246.08:13:47.91#ibcon#about to read 6, iclass 23, count 0 2006.246.08:13:47.91#ibcon#read 6, iclass 23, count 0 2006.246.08:13:47.91#ibcon#end of sib2, iclass 23, count 0 2006.246.08:13:47.91#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:13:47.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:13:47.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:13:47.91#ibcon#*before write, iclass 23, count 0 2006.246.08:13:47.91#ibcon#enter sib2, iclass 23, count 0 2006.246.08:13:47.92#ibcon#flushed, iclass 23, count 0 2006.246.08:13:47.92#ibcon#about to write, iclass 23, count 0 2006.246.08:13:47.92#ibcon#wrote, iclass 23, count 0 2006.246.08:13:47.92#ibcon#about to read 3, iclass 23, count 0 2006.246.08:13:47.96#ibcon#read 3, iclass 23, count 0 2006.246.08:13:47.96#ibcon#about to read 4, iclass 23, count 0 2006.246.08:13:47.96#ibcon#read 4, iclass 23, count 0 2006.246.08:13:47.96#ibcon#about to read 5, iclass 23, count 0 2006.246.08:13:47.96#ibcon#read 5, iclass 23, count 0 2006.246.08:13:47.96#ibcon#about to read 6, iclass 23, count 0 2006.246.08:13:47.96#ibcon#read 6, iclass 23, count 0 2006.246.08:13:47.96#ibcon#end of sib2, iclass 23, count 0 2006.246.08:13:47.96#ibcon#*after write, iclass 23, count 0 2006.246.08:13:47.96#ibcon#*before return 0, iclass 23, count 0 2006.246.08:13:47.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:47.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:47.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:13:47.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:13:47.97$vc4f8/va=1,8 2006.246.08:13:47.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:13:47.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:13:47.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:47.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:47.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:47.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:47.97#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:13:47.97#ibcon#first serial, iclass 25, count 2 2006.246.08:13:47.97#ibcon#enter sib2, iclass 25, count 2 2006.246.08:13:47.97#ibcon#flushed, iclass 25, count 2 2006.246.08:13:47.97#ibcon#about to write, iclass 25, count 2 2006.246.08:13:47.97#ibcon#wrote, iclass 25, count 2 2006.246.08:13:47.97#ibcon#about to read 3, iclass 25, count 2 2006.246.08:13:47.98#ibcon#read 3, iclass 25, count 2 2006.246.08:13:47.98#ibcon#about to read 4, iclass 25, count 2 2006.246.08:13:47.98#ibcon#read 4, iclass 25, count 2 2006.246.08:13:47.98#ibcon#about to read 5, iclass 25, count 2 2006.246.08:13:47.98#ibcon#read 5, iclass 25, count 2 2006.246.08:13:47.98#ibcon#about to read 6, iclass 25, count 2 2006.246.08:13:47.98#ibcon#read 6, iclass 25, count 2 2006.246.08:13:47.98#ibcon#end of sib2, iclass 25, count 2 2006.246.08:13:47.98#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:13:47.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:13:47.98#ibcon#[25=AT01-08\r\n] 2006.246.08:13:47.98#ibcon#*before write, iclass 25, count 2 2006.246.08:13:47.98#ibcon#enter sib2, iclass 25, count 2 2006.246.08:13:47.99#ibcon#flushed, iclass 25, count 2 2006.246.08:13:47.99#ibcon#about to write, iclass 25, count 2 2006.246.08:13:47.99#ibcon#wrote, iclass 25, count 2 2006.246.08:13:47.99#ibcon#about to read 3, iclass 25, count 2 2006.246.08:13:48.02#ibcon#read 3, iclass 25, count 2 2006.246.08:13:48.02#ibcon#about to read 4, iclass 25, count 2 2006.246.08:13:48.02#ibcon#read 4, iclass 25, count 2 2006.246.08:13:48.02#ibcon#about to read 5, iclass 25, count 2 2006.246.08:13:48.02#ibcon#read 5, iclass 25, count 2 2006.246.08:13:48.02#ibcon#about to read 6, iclass 25, count 2 2006.246.08:13:48.02#ibcon#read 6, iclass 25, count 2 2006.246.08:13:48.02#ibcon#end of sib2, iclass 25, count 2 2006.246.08:13:48.02#ibcon#*after write, iclass 25, count 2 2006.246.08:13:48.02#ibcon#*before return 0, iclass 25, count 2 2006.246.08:13:48.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:48.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:48.02#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:13:48.02#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:48.02#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:48.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:48.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:48.14#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:13:48.14#ibcon#first serial, iclass 25, count 0 2006.246.08:13:48.14#ibcon#enter sib2, iclass 25, count 0 2006.246.08:13:48.14#ibcon#flushed, iclass 25, count 0 2006.246.08:13:48.14#ibcon#about to write, iclass 25, count 0 2006.246.08:13:48.14#ibcon#wrote, iclass 25, count 0 2006.246.08:13:48.14#ibcon#about to read 3, iclass 25, count 0 2006.246.08:13:48.15#ibcon#read 3, iclass 25, count 0 2006.246.08:13:48.15#ibcon#about to read 4, iclass 25, count 0 2006.246.08:13:48.15#ibcon#read 4, iclass 25, count 0 2006.246.08:13:48.15#ibcon#about to read 5, iclass 25, count 0 2006.246.08:13:48.15#ibcon#read 5, iclass 25, count 0 2006.246.08:13:48.15#ibcon#about to read 6, iclass 25, count 0 2006.246.08:13:48.15#ibcon#read 6, iclass 25, count 0 2006.246.08:13:48.15#ibcon#end of sib2, iclass 25, count 0 2006.246.08:13:48.15#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:13:48.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:13:48.15#ibcon#[25=USB\r\n] 2006.246.08:13:48.15#ibcon#*before write, iclass 25, count 0 2006.246.08:13:48.16#ibcon#enter sib2, iclass 25, count 0 2006.246.08:13:48.16#ibcon#flushed, iclass 25, count 0 2006.246.08:13:48.16#ibcon#about to write, iclass 25, count 0 2006.246.08:13:48.16#ibcon#wrote, iclass 25, count 0 2006.246.08:13:48.16#ibcon#about to read 3, iclass 25, count 0 2006.246.08:13:48.18#ibcon#read 3, iclass 25, count 0 2006.246.08:13:48.18#ibcon#about to read 4, iclass 25, count 0 2006.246.08:13:48.18#ibcon#read 4, iclass 25, count 0 2006.246.08:13:48.18#ibcon#about to read 5, iclass 25, count 0 2006.246.08:13:48.18#ibcon#read 5, iclass 25, count 0 2006.246.08:13:48.18#ibcon#about to read 6, iclass 25, count 0 2006.246.08:13:48.18#ibcon#read 6, iclass 25, count 0 2006.246.08:13:48.18#ibcon#end of sib2, iclass 25, count 0 2006.246.08:13:48.18#ibcon#*after write, iclass 25, count 0 2006.246.08:13:48.18#ibcon#*before return 0, iclass 25, count 0 2006.246.08:13:48.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:48.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:48.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:13:48.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:13:48.19$vc4f8/valo=2,572.99 2006.246.08:13:48.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:13:48.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:13:48.19#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:48.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:48.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:48.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:48.19#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:13:48.19#ibcon#first serial, iclass 27, count 0 2006.246.08:13:48.19#ibcon#enter sib2, iclass 27, count 0 2006.246.08:13:48.19#ibcon#flushed, iclass 27, count 0 2006.246.08:13:48.19#ibcon#about to write, iclass 27, count 0 2006.246.08:13:48.19#ibcon#wrote, iclass 27, count 0 2006.246.08:13:48.19#ibcon#about to read 3, iclass 27, count 0 2006.246.08:13:48.21#ibcon#read 3, iclass 27, count 0 2006.246.08:13:48.21#ibcon#about to read 4, iclass 27, count 0 2006.246.08:13:48.21#ibcon#read 4, iclass 27, count 0 2006.246.08:13:48.21#ibcon#about to read 5, iclass 27, count 0 2006.246.08:13:48.21#ibcon#read 5, iclass 27, count 0 2006.246.08:13:48.21#ibcon#about to read 6, iclass 27, count 0 2006.246.08:13:48.21#ibcon#read 6, iclass 27, count 0 2006.246.08:13:48.21#ibcon#end of sib2, iclass 27, count 0 2006.246.08:13:48.21#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:13:48.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:13:48.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:13:48.21#ibcon#*before write, iclass 27, count 0 2006.246.08:13:48.21#ibcon#enter sib2, iclass 27, count 0 2006.246.08:13:48.21#ibcon#flushed, iclass 27, count 0 2006.246.08:13:48.21#ibcon#about to write, iclass 27, count 0 2006.246.08:13:48.21#ibcon#wrote, iclass 27, count 0 2006.246.08:13:48.21#ibcon#about to read 3, iclass 27, count 0 2006.246.08:13:48.25#ibcon#read 3, iclass 27, count 0 2006.246.08:13:48.25#ibcon#about to read 4, iclass 27, count 0 2006.246.08:13:48.25#ibcon#read 4, iclass 27, count 0 2006.246.08:13:48.25#ibcon#about to read 5, iclass 27, count 0 2006.246.08:13:48.25#ibcon#read 5, iclass 27, count 0 2006.246.08:13:48.25#ibcon#about to read 6, iclass 27, count 0 2006.246.08:13:48.25#ibcon#read 6, iclass 27, count 0 2006.246.08:13:48.25#ibcon#end of sib2, iclass 27, count 0 2006.246.08:13:48.25#ibcon#*after write, iclass 27, count 0 2006.246.08:13:48.25#ibcon#*before return 0, iclass 27, count 0 2006.246.08:13:48.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:48.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:48.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:13:48.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:13:48.26$vc4f8/va=2,7 2006.246.08:13:48.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:13:48.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:13:48.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:48.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:48.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:48.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:48.29#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:13:48.29#ibcon#first serial, iclass 29, count 2 2006.246.08:13:48.29#ibcon#enter sib2, iclass 29, count 2 2006.246.08:13:48.29#ibcon#flushed, iclass 29, count 2 2006.246.08:13:48.29#ibcon#about to write, iclass 29, count 2 2006.246.08:13:48.29#ibcon#wrote, iclass 29, count 2 2006.246.08:13:48.29#ibcon#about to read 3, iclass 29, count 2 2006.246.08:13:48.32#ibcon#read 3, iclass 29, count 2 2006.246.08:13:48.32#ibcon#about to read 4, iclass 29, count 2 2006.246.08:13:48.32#ibcon#read 4, iclass 29, count 2 2006.246.08:13:48.32#ibcon#about to read 5, iclass 29, count 2 2006.246.08:13:48.32#ibcon#read 5, iclass 29, count 2 2006.246.08:13:48.32#ibcon#about to read 6, iclass 29, count 2 2006.246.08:13:48.32#ibcon#read 6, iclass 29, count 2 2006.246.08:13:48.32#ibcon#end of sib2, iclass 29, count 2 2006.246.08:13:48.32#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:13:48.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:13:48.32#ibcon#[25=AT02-07\r\n] 2006.246.08:13:48.32#ibcon#*before write, iclass 29, count 2 2006.246.08:13:48.32#ibcon#enter sib2, iclass 29, count 2 2006.246.08:13:48.32#ibcon#flushed, iclass 29, count 2 2006.246.08:13:48.32#ibcon#about to write, iclass 29, count 2 2006.246.08:13:48.32#ibcon#wrote, iclass 29, count 2 2006.246.08:13:48.32#ibcon#about to read 3, iclass 29, count 2 2006.246.08:13:48.35#ibcon#read 3, iclass 29, count 2 2006.246.08:13:48.35#ibcon#about to read 4, iclass 29, count 2 2006.246.08:13:48.35#ibcon#read 4, iclass 29, count 2 2006.246.08:13:48.35#ibcon#about to read 5, iclass 29, count 2 2006.246.08:13:48.35#ibcon#read 5, iclass 29, count 2 2006.246.08:13:48.35#ibcon#about to read 6, iclass 29, count 2 2006.246.08:13:48.35#ibcon#read 6, iclass 29, count 2 2006.246.08:13:48.35#ibcon#end of sib2, iclass 29, count 2 2006.246.08:13:48.35#ibcon#*after write, iclass 29, count 2 2006.246.08:13:48.35#ibcon#*before return 0, iclass 29, count 2 2006.246.08:13:48.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:48.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:48.36#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:13:48.36#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:48.36#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:48.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:48.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:48.47#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:13:48.47#ibcon#first serial, iclass 29, count 0 2006.246.08:13:48.47#ibcon#enter sib2, iclass 29, count 0 2006.246.08:13:48.47#ibcon#flushed, iclass 29, count 0 2006.246.08:13:48.47#ibcon#about to write, iclass 29, count 0 2006.246.08:13:48.47#ibcon#wrote, iclass 29, count 0 2006.246.08:13:48.47#ibcon#about to read 3, iclass 29, count 0 2006.246.08:13:48.49#ibcon#read 3, iclass 29, count 0 2006.246.08:13:48.49#ibcon#about to read 4, iclass 29, count 0 2006.246.08:13:48.49#ibcon#read 4, iclass 29, count 0 2006.246.08:13:48.49#ibcon#about to read 5, iclass 29, count 0 2006.246.08:13:48.49#ibcon#read 5, iclass 29, count 0 2006.246.08:13:48.49#ibcon#about to read 6, iclass 29, count 0 2006.246.08:13:48.49#ibcon#read 6, iclass 29, count 0 2006.246.08:13:48.49#ibcon#end of sib2, iclass 29, count 0 2006.246.08:13:48.49#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:13:48.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:13:48.49#ibcon#[25=USB\r\n] 2006.246.08:13:48.49#ibcon#*before write, iclass 29, count 0 2006.246.08:13:48.49#ibcon#enter sib2, iclass 29, count 0 2006.246.08:13:48.49#ibcon#flushed, iclass 29, count 0 2006.246.08:13:48.50#ibcon#about to write, iclass 29, count 0 2006.246.08:13:48.50#ibcon#wrote, iclass 29, count 0 2006.246.08:13:48.50#ibcon#about to read 3, iclass 29, count 0 2006.246.08:13:48.52#ibcon#read 3, iclass 29, count 0 2006.246.08:13:48.52#ibcon#about to read 4, iclass 29, count 0 2006.246.08:13:48.52#ibcon#read 4, iclass 29, count 0 2006.246.08:13:48.52#ibcon#about to read 5, iclass 29, count 0 2006.246.08:13:48.52#ibcon#read 5, iclass 29, count 0 2006.246.08:13:48.52#ibcon#about to read 6, iclass 29, count 0 2006.246.08:13:48.52#ibcon#read 6, iclass 29, count 0 2006.246.08:13:48.52#ibcon#end of sib2, iclass 29, count 0 2006.246.08:13:48.52#ibcon#*after write, iclass 29, count 0 2006.246.08:13:48.52#ibcon#*before return 0, iclass 29, count 0 2006.246.08:13:48.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:48.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:48.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:13:48.53#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:13:48.53$vc4f8/valo=3,672.99 2006.246.08:13:48.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:13:48.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:13:48.53#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:48.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:48.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:48.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:48.53#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:13:48.53#ibcon#first serial, iclass 31, count 0 2006.246.08:13:48.53#ibcon#enter sib2, iclass 31, count 0 2006.246.08:13:48.53#ibcon#flushed, iclass 31, count 0 2006.246.08:13:48.53#ibcon#about to write, iclass 31, count 0 2006.246.08:13:48.53#ibcon#wrote, iclass 31, count 0 2006.246.08:13:48.53#ibcon#about to read 3, iclass 31, count 0 2006.246.08:13:48.55#ibcon#read 3, iclass 31, count 0 2006.246.08:13:48.55#ibcon#about to read 4, iclass 31, count 0 2006.246.08:13:48.55#ibcon#read 4, iclass 31, count 0 2006.246.08:13:48.55#ibcon#about to read 5, iclass 31, count 0 2006.246.08:13:48.55#ibcon#read 5, iclass 31, count 0 2006.246.08:13:48.55#ibcon#about to read 6, iclass 31, count 0 2006.246.08:13:48.55#ibcon#read 6, iclass 31, count 0 2006.246.08:13:48.55#ibcon#end of sib2, iclass 31, count 0 2006.246.08:13:48.55#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:13:48.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:13:48.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:13:48.55#ibcon#*before write, iclass 31, count 0 2006.246.08:13:48.55#ibcon#enter sib2, iclass 31, count 0 2006.246.08:13:48.55#ibcon#flushed, iclass 31, count 0 2006.246.08:13:48.55#ibcon#about to write, iclass 31, count 0 2006.246.08:13:48.55#ibcon#wrote, iclass 31, count 0 2006.246.08:13:48.55#ibcon#about to read 3, iclass 31, count 0 2006.246.08:13:48.59#ibcon#read 3, iclass 31, count 0 2006.246.08:13:48.59#ibcon#about to read 4, iclass 31, count 0 2006.246.08:13:48.59#ibcon#read 4, iclass 31, count 0 2006.246.08:13:48.59#ibcon#about to read 5, iclass 31, count 0 2006.246.08:13:48.59#ibcon#read 5, iclass 31, count 0 2006.246.08:13:48.59#ibcon#about to read 6, iclass 31, count 0 2006.246.08:13:48.59#ibcon#read 6, iclass 31, count 0 2006.246.08:13:48.59#ibcon#end of sib2, iclass 31, count 0 2006.246.08:13:48.59#ibcon#*after write, iclass 31, count 0 2006.246.08:13:48.59#ibcon#*before return 0, iclass 31, count 0 2006.246.08:13:48.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:48.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:48.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:13:48.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:13:48.60$vc4f8/va=3,6 2006.246.08:13:48.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:13:48.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:13:48.60#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:48.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:48.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:48.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:48.63#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:13:48.63#ibcon#first serial, iclass 33, count 2 2006.246.08:13:48.63#ibcon#enter sib2, iclass 33, count 2 2006.246.08:13:48.63#ibcon#flushed, iclass 33, count 2 2006.246.08:13:48.63#ibcon#about to write, iclass 33, count 2 2006.246.08:13:48.63#ibcon#wrote, iclass 33, count 2 2006.246.08:13:48.63#ibcon#about to read 3, iclass 33, count 2 2006.246.08:13:48.66#ibcon#read 3, iclass 33, count 2 2006.246.08:13:48.66#ibcon#about to read 4, iclass 33, count 2 2006.246.08:13:48.66#ibcon#read 4, iclass 33, count 2 2006.246.08:13:48.66#ibcon#about to read 5, iclass 33, count 2 2006.246.08:13:48.66#ibcon#read 5, iclass 33, count 2 2006.246.08:13:48.66#ibcon#about to read 6, iclass 33, count 2 2006.246.08:13:48.66#ibcon#read 6, iclass 33, count 2 2006.246.08:13:48.66#ibcon#end of sib2, iclass 33, count 2 2006.246.08:13:48.66#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:13:48.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:13:48.66#ibcon#[25=AT03-06\r\n] 2006.246.08:13:48.66#ibcon#*before write, iclass 33, count 2 2006.246.08:13:48.66#ibcon#enter sib2, iclass 33, count 2 2006.246.08:13:48.66#ibcon#flushed, iclass 33, count 2 2006.246.08:13:48.66#ibcon#about to write, iclass 33, count 2 2006.246.08:13:48.66#ibcon#wrote, iclass 33, count 2 2006.246.08:13:48.66#ibcon#about to read 3, iclass 33, count 2 2006.246.08:13:48.69#ibcon#read 3, iclass 33, count 2 2006.246.08:13:48.69#ibcon#about to read 4, iclass 33, count 2 2006.246.08:13:48.69#ibcon#read 4, iclass 33, count 2 2006.246.08:13:48.69#ibcon#about to read 5, iclass 33, count 2 2006.246.08:13:48.69#ibcon#read 5, iclass 33, count 2 2006.246.08:13:48.69#ibcon#about to read 6, iclass 33, count 2 2006.246.08:13:48.69#ibcon#read 6, iclass 33, count 2 2006.246.08:13:48.69#ibcon#end of sib2, iclass 33, count 2 2006.246.08:13:48.69#ibcon#*after write, iclass 33, count 2 2006.246.08:13:48.69#ibcon#*before return 0, iclass 33, count 2 2006.246.08:13:48.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:48.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:48.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:13:48.70#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:48.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:48.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:48.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:48.81#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:13:48.81#ibcon#first serial, iclass 33, count 0 2006.246.08:13:48.81#ibcon#enter sib2, iclass 33, count 0 2006.246.08:13:48.81#ibcon#flushed, iclass 33, count 0 2006.246.08:13:48.81#ibcon#about to write, iclass 33, count 0 2006.246.08:13:48.81#ibcon#wrote, iclass 33, count 0 2006.246.08:13:48.81#ibcon#about to read 3, iclass 33, count 0 2006.246.08:13:48.83#ibcon#read 3, iclass 33, count 0 2006.246.08:13:48.83#ibcon#about to read 4, iclass 33, count 0 2006.246.08:13:48.83#ibcon#read 4, iclass 33, count 0 2006.246.08:13:48.83#ibcon#about to read 5, iclass 33, count 0 2006.246.08:13:48.83#ibcon#read 5, iclass 33, count 0 2006.246.08:13:48.83#ibcon#about to read 6, iclass 33, count 0 2006.246.08:13:48.83#ibcon#read 6, iclass 33, count 0 2006.246.08:13:48.83#ibcon#end of sib2, iclass 33, count 0 2006.246.08:13:48.83#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:13:48.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:13:48.83#ibcon#[25=USB\r\n] 2006.246.08:13:48.83#ibcon#*before write, iclass 33, count 0 2006.246.08:13:48.83#ibcon#enter sib2, iclass 33, count 0 2006.246.08:13:48.83#ibcon#flushed, iclass 33, count 0 2006.246.08:13:48.84#ibcon#about to write, iclass 33, count 0 2006.246.08:13:48.84#ibcon#wrote, iclass 33, count 0 2006.246.08:13:48.84#ibcon#about to read 3, iclass 33, count 0 2006.246.08:13:48.86#ibcon#read 3, iclass 33, count 0 2006.246.08:13:48.86#ibcon#about to read 4, iclass 33, count 0 2006.246.08:13:48.86#ibcon#read 4, iclass 33, count 0 2006.246.08:13:48.86#ibcon#about to read 5, iclass 33, count 0 2006.246.08:13:48.86#ibcon#read 5, iclass 33, count 0 2006.246.08:13:48.86#ibcon#about to read 6, iclass 33, count 0 2006.246.08:13:48.86#ibcon#read 6, iclass 33, count 0 2006.246.08:13:48.86#ibcon#end of sib2, iclass 33, count 0 2006.246.08:13:48.86#ibcon#*after write, iclass 33, count 0 2006.246.08:13:48.86#ibcon#*before return 0, iclass 33, count 0 2006.246.08:13:48.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:48.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:48.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:13:48.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:13:48.87$vc4f8/valo=4,832.99 2006.246.08:13:48.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:13:48.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:13:48.87#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:48.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:48.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:48.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:48.87#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:13:48.87#ibcon#first serial, iclass 35, count 0 2006.246.08:13:48.87#ibcon#enter sib2, iclass 35, count 0 2006.246.08:13:48.87#ibcon#flushed, iclass 35, count 0 2006.246.08:13:48.87#ibcon#about to write, iclass 35, count 0 2006.246.08:13:48.87#ibcon#wrote, iclass 35, count 0 2006.246.08:13:48.87#ibcon#about to read 3, iclass 35, count 0 2006.246.08:13:48.88#ibcon#read 3, iclass 35, count 0 2006.246.08:13:48.88#ibcon#about to read 4, iclass 35, count 0 2006.246.08:13:48.88#ibcon#read 4, iclass 35, count 0 2006.246.08:13:48.88#ibcon#about to read 5, iclass 35, count 0 2006.246.08:13:48.88#ibcon#read 5, iclass 35, count 0 2006.246.08:13:48.88#ibcon#about to read 6, iclass 35, count 0 2006.246.08:13:48.88#ibcon#read 6, iclass 35, count 0 2006.246.08:13:48.88#ibcon#end of sib2, iclass 35, count 0 2006.246.08:13:48.88#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:13:48.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:13:48.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:13:48.88#ibcon#*before write, iclass 35, count 0 2006.246.08:13:48.88#ibcon#enter sib2, iclass 35, count 0 2006.246.08:13:48.88#ibcon#flushed, iclass 35, count 0 2006.246.08:13:48.89#ibcon#about to write, iclass 35, count 0 2006.246.08:13:48.89#ibcon#wrote, iclass 35, count 0 2006.246.08:13:48.89#ibcon#about to read 3, iclass 35, count 0 2006.246.08:13:48.92#ibcon#read 3, iclass 35, count 0 2006.246.08:13:48.92#ibcon#about to read 4, iclass 35, count 0 2006.246.08:13:48.92#ibcon#read 4, iclass 35, count 0 2006.246.08:13:48.92#ibcon#about to read 5, iclass 35, count 0 2006.246.08:13:48.92#ibcon#read 5, iclass 35, count 0 2006.246.08:13:48.92#ibcon#about to read 6, iclass 35, count 0 2006.246.08:13:48.92#ibcon#read 6, iclass 35, count 0 2006.246.08:13:48.92#ibcon#end of sib2, iclass 35, count 0 2006.246.08:13:48.92#ibcon#*after write, iclass 35, count 0 2006.246.08:13:48.92#ibcon#*before return 0, iclass 35, count 0 2006.246.08:13:48.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:48.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:48.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:13:48.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:13:48.93$vc4f8/va=4,7 2006.246.08:13:48.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:13:48.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:13:48.93#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:48.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:48.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:48.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:48.97#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:13:48.97#ibcon#first serial, iclass 37, count 2 2006.246.08:13:48.97#ibcon#enter sib2, iclass 37, count 2 2006.246.08:13:48.97#ibcon#flushed, iclass 37, count 2 2006.246.08:13:48.97#ibcon#about to write, iclass 37, count 2 2006.246.08:13:48.97#ibcon#wrote, iclass 37, count 2 2006.246.08:13:48.97#ibcon#about to read 3, iclass 37, count 2 2006.246.08:13:48.99#ibcon#read 3, iclass 37, count 2 2006.246.08:13:48.99#ibcon#about to read 4, iclass 37, count 2 2006.246.08:13:48.99#ibcon#read 4, iclass 37, count 2 2006.246.08:13:48.99#ibcon#about to read 5, iclass 37, count 2 2006.246.08:13:48.99#ibcon#read 5, iclass 37, count 2 2006.246.08:13:48.99#ibcon#about to read 6, iclass 37, count 2 2006.246.08:13:48.99#ibcon#read 6, iclass 37, count 2 2006.246.08:13:48.99#ibcon#end of sib2, iclass 37, count 2 2006.246.08:13:48.99#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:13:48.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:13:48.99#ibcon#[25=AT04-07\r\n] 2006.246.08:13:48.99#ibcon#*before write, iclass 37, count 2 2006.246.08:13:48.99#ibcon#enter sib2, iclass 37, count 2 2006.246.08:13:48.99#ibcon#flushed, iclass 37, count 2 2006.246.08:13:49.00#ibcon#about to write, iclass 37, count 2 2006.246.08:13:49.00#ibcon#wrote, iclass 37, count 2 2006.246.08:13:49.00#ibcon#about to read 3, iclass 37, count 2 2006.246.08:13:49.02#ibcon#read 3, iclass 37, count 2 2006.246.08:13:49.02#ibcon#about to read 4, iclass 37, count 2 2006.246.08:13:49.02#ibcon#read 4, iclass 37, count 2 2006.246.08:13:49.02#ibcon#about to read 5, iclass 37, count 2 2006.246.08:13:49.02#ibcon#read 5, iclass 37, count 2 2006.246.08:13:49.02#ibcon#about to read 6, iclass 37, count 2 2006.246.08:13:49.02#ibcon#read 6, iclass 37, count 2 2006.246.08:13:49.02#ibcon#end of sib2, iclass 37, count 2 2006.246.08:13:49.02#ibcon#*after write, iclass 37, count 2 2006.246.08:13:49.02#ibcon#*before return 0, iclass 37, count 2 2006.246.08:13:49.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:49.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:49.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:13:49.03#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:49.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:49.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:49.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:49.15#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:13:49.15#ibcon#first serial, iclass 37, count 0 2006.246.08:13:49.15#ibcon#enter sib2, iclass 37, count 0 2006.246.08:13:49.15#ibcon#flushed, iclass 37, count 0 2006.246.08:13:49.15#ibcon#about to write, iclass 37, count 0 2006.246.08:13:49.15#ibcon#wrote, iclass 37, count 0 2006.246.08:13:49.15#ibcon#about to read 3, iclass 37, count 0 2006.246.08:13:49.16#ibcon#read 3, iclass 37, count 0 2006.246.08:13:49.16#ibcon#about to read 4, iclass 37, count 0 2006.246.08:13:49.16#ibcon#read 4, iclass 37, count 0 2006.246.08:13:49.16#ibcon#about to read 5, iclass 37, count 0 2006.246.08:13:49.16#ibcon#read 5, iclass 37, count 0 2006.246.08:13:49.16#ibcon#about to read 6, iclass 37, count 0 2006.246.08:13:49.16#ibcon#read 6, iclass 37, count 0 2006.246.08:13:49.16#ibcon#end of sib2, iclass 37, count 0 2006.246.08:13:49.16#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:13:49.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:13:49.16#ibcon#[25=USB\r\n] 2006.246.08:13:49.16#ibcon#*before write, iclass 37, count 0 2006.246.08:13:49.16#ibcon#enter sib2, iclass 37, count 0 2006.246.08:13:49.16#ibcon#flushed, iclass 37, count 0 2006.246.08:13:49.17#ibcon#about to write, iclass 37, count 0 2006.246.08:13:49.17#ibcon#wrote, iclass 37, count 0 2006.246.08:13:49.17#ibcon#about to read 3, iclass 37, count 0 2006.246.08:13:49.19#ibcon#read 3, iclass 37, count 0 2006.246.08:13:49.19#ibcon#about to read 4, iclass 37, count 0 2006.246.08:13:49.19#ibcon#read 4, iclass 37, count 0 2006.246.08:13:49.19#ibcon#about to read 5, iclass 37, count 0 2006.246.08:13:49.19#ibcon#read 5, iclass 37, count 0 2006.246.08:13:49.19#ibcon#about to read 6, iclass 37, count 0 2006.246.08:13:49.19#ibcon#read 6, iclass 37, count 0 2006.246.08:13:49.19#ibcon#end of sib2, iclass 37, count 0 2006.246.08:13:49.19#ibcon#*after write, iclass 37, count 0 2006.246.08:13:49.19#ibcon#*before return 0, iclass 37, count 0 2006.246.08:13:49.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:49.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:49.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:13:49.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:13:49.20$vc4f8/valo=5,652.99 2006.246.08:13:49.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:13:49.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:13:49.20#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:49.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:49.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:49.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:49.20#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:13:49.20#ibcon#first serial, iclass 39, count 0 2006.246.08:13:49.20#ibcon#enter sib2, iclass 39, count 0 2006.246.08:13:49.20#ibcon#flushed, iclass 39, count 0 2006.246.08:13:49.20#ibcon#about to write, iclass 39, count 0 2006.246.08:13:49.20#ibcon#wrote, iclass 39, count 0 2006.246.08:13:49.20#ibcon#about to read 3, iclass 39, count 0 2006.246.08:13:49.21#ibcon#read 3, iclass 39, count 0 2006.246.08:13:49.21#ibcon#about to read 4, iclass 39, count 0 2006.246.08:13:49.21#ibcon#read 4, iclass 39, count 0 2006.246.08:13:49.21#ibcon#about to read 5, iclass 39, count 0 2006.246.08:13:49.21#ibcon#read 5, iclass 39, count 0 2006.246.08:13:49.21#ibcon#about to read 6, iclass 39, count 0 2006.246.08:13:49.21#ibcon#read 6, iclass 39, count 0 2006.246.08:13:49.21#ibcon#end of sib2, iclass 39, count 0 2006.246.08:13:49.21#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:13:49.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:13:49.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:13:49.21#ibcon#*before write, iclass 39, count 0 2006.246.08:13:49.21#ibcon#enter sib2, iclass 39, count 0 2006.246.08:13:49.21#ibcon#flushed, iclass 39, count 0 2006.246.08:13:49.21#ibcon#about to write, iclass 39, count 0 2006.246.08:13:49.22#ibcon#wrote, iclass 39, count 0 2006.246.08:13:49.22#ibcon#about to read 3, iclass 39, count 0 2006.246.08:13:49.25#ibcon#read 3, iclass 39, count 0 2006.246.08:13:49.25#ibcon#about to read 4, iclass 39, count 0 2006.246.08:13:49.25#ibcon#read 4, iclass 39, count 0 2006.246.08:13:49.25#ibcon#about to read 5, iclass 39, count 0 2006.246.08:13:49.25#ibcon#read 5, iclass 39, count 0 2006.246.08:13:49.25#ibcon#about to read 6, iclass 39, count 0 2006.246.08:13:49.25#ibcon#read 6, iclass 39, count 0 2006.246.08:13:49.25#ibcon#end of sib2, iclass 39, count 0 2006.246.08:13:49.25#ibcon#*after write, iclass 39, count 0 2006.246.08:13:49.25#ibcon#*before return 0, iclass 39, count 0 2006.246.08:13:49.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:49.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:49.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:13:49.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:13:49.26$vc4f8/va=5,7 2006.246.08:13:49.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:13:49.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:13:49.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:49.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:49.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:49.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:49.30#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:13:49.30#ibcon#first serial, iclass 3, count 2 2006.246.08:13:49.30#ibcon#enter sib2, iclass 3, count 2 2006.246.08:13:49.30#ibcon#flushed, iclass 3, count 2 2006.246.08:13:49.30#ibcon#about to write, iclass 3, count 2 2006.246.08:13:49.30#ibcon#wrote, iclass 3, count 2 2006.246.08:13:49.30#ibcon#about to read 3, iclass 3, count 2 2006.246.08:13:49.32#ibcon#read 3, iclass 3, count 2 2006.246.08:13:49.32#ibcon#about to read 4, iclass 3, count 2 2006.246.08:13:49.32#ibcon#read 4, iclass 3, count 2 2006.246.08:13:49.32#ibcon#about to read 5, iclass 3, count 2 2006.246.08:13:49.32#ibcon#read 5, iclass 3, count 2 2006.246.08:13:49.32#ibcon#about to read 6, iclass 3, count 2 2006.246.08:13:49.32#ibcon#read 6, iclass 3, count 2 2006.246.08:13:49.32#ibcon#end of sib2, iclass 3, count 2 2006.246.08:13:49.32#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:13:49.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:13:49.32#ibcon#[25=AT05-07\r\n] 2006.246.08:13:49.32#ibcon#*before write, iclass 3, count 2 2006.246.08:13:49.32#ibcon#enter sib2, iclass 3, count 2 2006.246.08:13:49.32#ibcon#flushed, iclass 3, count 2 2006.246.08:13:49.32#ibcon#about to write, iclass 3, count 2 2006.246.08:13:49.33#ibcon#wrote, iclass 3, count 2 2006.246.08:13:49.33#ibcon#about to read 3, iclass 3, count 2 2006.246.08:13:49.35#ibcon#read 3, iclass 3, count 2 2006.246.08:13:49.35#ibcon#about to read 4, iclass 3, count 2 2006.246.08:13:49.35#ibcon#read 4, iclass 3, count 2 2006.246.08:13:49.35#ibcon#about to read 5, iclass 3, count 2 2006.246.08:13:49.35#ibcon#read 5, iclass 3, count 2 2006.246.08:13:49.35#ibcon#about to read 6, iclass 3, count 2 2006.246.08:13:49.35#ibcon#read 6, iclass 3, count 2 2006.246.08:13:49.35#ibcon#end of sib2, iclass 3, count 2 2006.246.08:13:49.35#ibcon#*after write, iclass 3, count 2 2006.246.08:13:49.35#ibcon#*before return 0, iclass 3, count 2 2006.246.08:13:49.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:49.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:49.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:13:49.36#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:49.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:49.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:49.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:49.47#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:13:49.47#ibcon#first serial, iclass 3, count 0 2006.246.08:13:49.47#ibcon#enter sib2, iclass 3, count 0 2006.246.08:13:49.47#ibcon#flushed, iclass 3, count 0 2006.246.08:13:49.47#ibcon#about to write, iclass 3, count 0 2006.246.08:13:49.47#ibcon#wrote, iclass 3, count 0 2006.246.08:13:49.47#ibcon#about to read 3, iclass 3, count 0 2006.246.08:13:49.49#ibcon#read 3, iclass 3, count 0 2006.246.08:13:49.49#ibcon#about to read 4, iclass 3, count 0 2006.246.08:13:49.49#ibcon#read 4, iclass 3, count 0 2006.246.08:13:49.49#ibcon#about to read 5, iclass 3, count 0 2006.246.08:13:49.49#ibcon#read 5, iclass 3, count 0 2006.246.08:13:49.49#ibcon#about to read 6, iclass 3, count 0 2006.246.08:13:49.49#ibcon#read 6, iclass 3, count 0 2006.246.08:13:49.49#ibcon#end of sib2, iclass 3, count 0 2006.246.08:13:49.49#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:13:49.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:13:49.49#ibcon#[25=USB\r\n] 2006.246.08:13:49.49#ibcon#*before write, iclass 3, count 0 2006.246.08:13:49.49#ibcon#enter sib2, iclass 3, count 0 2006.246.08:13:49.49#ibcon#flushed, iclass 3, count 0 2006.246.08:13:49.49#ibcon#about to write, iclass 3, count 0 2006.246.08:13:49.50#ibcon#wrote, iclass 3, count 0 2006.246.08:13:49.50#ibcon#about to read 3, iclass 3, count 0 2006.246.08:13:49.52#ibcon#read 3, iclass 3, count 0 2006.246.08:13:49.52#ibcon#about to read 4, iclass 3, count 0 2006.246.08:13:49.52#ibcon#read 4, iclass 3, count 0 2006.246.08:13:49.52#ibcon#about to read 5, iclass 3, count 0 2006.246.08:13:49.52#ibcon#read 5, iclass 3, count 0 2006.246.08:13:49.52#ibcon#about to read 6, iclass 3, count 0 2006.246.08:13:49.52#ibcon#read 6, iclass 3, count 0 2006.246.08:13:49.52#ibcon#end of sib2, iclass 3, count 0 2006.246.08:13:49.52#ibcon#*after write, iclass 3, count 0 2006.246.08:13:49.52#ibcon#*before return 0, iclass 3, count 0 2006.246.08:13:49.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:49.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:49.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:13:49.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:13:49.53$vc4f8/valo=6,772.99 2006.246.08:13:49.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:13:49.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:13:49.53#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:49.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:49.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:49.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:49.53#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:13:49.53#ibcon#first serial, iclass 5, count 0 2006.246.08:13:49.53#ibcon#enter sib2, iclass 5, count 0 2006.246.08:13:49.53#ibcon#flushed, iclass 5, count 0 2006.246.08:13:49.53#ibcon#about to write, iclass 5, count 0 2006.246.08:13:49.53#ibcon#wrote, iclass 5, count 0 2006.246.08:13:49.53#ibcon#about to read 3, iclass 5, count 0 2006.246.08:13:49.55#ibcon#read 3, iclass 5, count 0 2006.246.08:13:49.55#ibcon#about to read 4, iclass 5, count 0 2006.246.08:13:49.55#ibcon#read 4, iclass 5, count 0 2006.246.08:13:49.55#ibcon#about to read 5, iclass 5, count 0 2006.246.08:13:49.55#ibcon#read 5, iclass 5, count 0 2006.246.08:13:49.55#ibcon#about to read 6, iclass 5, count 0 2006.246.08:13:49.55#ibcon#read 6, iclass 5, count 0 2006.246.08:13:49.55#ibcon#end of sib2, iclass 5, count 0 2006.246.08:13:49.55#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:13:49.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:13:49.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:13:49.55#ibcon#*before write, iclass 5, count 0 2006.246.08:13:49.55#ibcon#enter sib2, iclass 5, count 0 2006.246.08:13:49.55#ibcon#flushed, iclass 5, count 0 2006.246.08:13:49.55#ibcon#about to write, iclass 5, count 0 2006.246.08:13:49.55#ibcon#wrote, iclass 5, count 0 2006.246.08:13:49.55#ibcon#about to read 3, iclass 5, count 0 2006.246.08:13:49.59#ibcon#read 3, iclass 5, count 0 2006.246.08:13:49.59#ibcon#about to read 4, iclass 5, count 0 2006.246.08:13:49.59#ibcon#read 4, iclass 5, count 0 2006.246.08:13:49.59#ibcon#about to read 5, iclass 5, count 0 2006.246.08:13:49.59#ibcon#read 5, iclass 5, count 0 2006.246.08:13:49.59#ibcon#about to read 6, iclass 5, count 0 2006.246.08:13:49.59#ibcon#read 6, iclass 5, count 0 2006.246.08:13:49.59#ibcon#end of sib2, iclass 5, count 0 2006.246.08:13:49.59#ibcon#*after write, iclass 5, count 0 2006.246.08:13:49.59#ibcon#*before return 0, iclass 5, count 0 2006.246.08:13:49.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:49.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:49.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:13:49.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:13:49.60$vc4f8/va=6,7 2006.246.08:13:49.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.08:13:49.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.08:13:49.60#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:49.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:49.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:49.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:49.63#ibcon#enter wrdev, iclass 7, count 2 2006.246.08:13:49.63#ibcon#first serial, iclass 7, count 2 2006.246.08:13:49.63#ibcon#enter sib2, iclass 7, count 2 2006.246.08:13:49.63#ibcon#flushed, iclass 7, count 2 2006.246.08:13:49.63#ibcon#about to write, iclass 7, count 2 2006.246.08:13:49.63#ibcon#wrote, iclass 7, count 2 2006.246.08:13:49.63#ibcon#about to read 3, iclass 7, count 2 2006.246.08:13:49.65#ibcon#read 3, iclass 7, count 2 2006.246.08:13:49.65#ibcon#about to read 4, iclass 7, count 2 2006.246.08:13:49.65#ibcon#read 4, iclass 7, count 2 2006.246.08:13:49.65#ibcon#about to read 5, iclass 7, count 2 2006.246.08:13:49.65#ibcon#read 5, iclass 7, count 2 2006.246.08:13:49.65#ibcon#about to read 6, iclass 7, count 2 2006.246.08:13:49.65#ibcon#read 6, iclass 7, count 2 2006.246.08:13:49.65#ibcon#end of sib2, iclass 7, count 2 2006.246.08:13:49.65#ibcon#*mode == 0, iclass 7, count 2 2006.246.08:13:49.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.08:13:49.65#ibcon#[25=AT06-07\r\n] 2006.246.08:13:49.65#ibcon#*before write, iclass 7, count 2 2006.246.08:13:49.65#ibcon#enter sib2, iclass 7, count 2 2006.246.08:13:49.65#ibcon#flushed, iclass 7, count 2 2006.246.08:13:49.66#ibcon#about to write, iclass 7, count 2 2006.246.08:13:49.66#ibcon#wrote, iclass 7, count 2 2006.246.08:13:49.66#ibcon#about to read 3, iclass 7, count 2 2006.246.08:13:49.68#ibcon#read 3, iclass 7, count 2 2006.246.08:13:49.68#ibcon#about to read 4, iclass 7, count 2 2006.246.08:13:49.68#ibcon#read 4, iclass 7, count 2 2006.246.08:13:49.68#ibcon#about to read 5, iclass 7, count 2 2006.246.08:13:49.68#ibcon#read 5, iclass 7, count 2 2006.246.08:13:49.68#ibcon#about to read 6, iclass 7, count 2 2006.246.08:13:49.68#ibcon#read 6, iclass 7, count 2 2006.246.08:13:49.68#ibcon#end of sib2, iclass 7, count 2 2006.246.08:13:49.68#ibcon#*after write, iclass 7, count 2 2006.246.08:13:49.68#ibcon#*before return 0, iclass 7, count 2 2006.246.08:13:49.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:49.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:49.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.08:13:49.69#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:49.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:49.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:49.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:49.79#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:13:49.79#ibcon#first serial, iclass 7, count 0 2006.246.08:13:49.79#ibcon#enter sib2, iclass 7, count 0 2006.246.08:13:49.79#ibcon#flushed, iclass 7, count 0 2006.246.08:13:49.79#ibcon#about to write, iclass 7, count 0 2006.246.08:13:49.79#ibcon#wrote, iclass 7, count 0 2006.246.08:13:49.79#ibcon#about to read 3, iclass 7, count 0 2006.246.08:13:49.81#ibcon#read 3, iclass 7, count 0 2006.246.08:13:49.81#ibcon#about to read 4, iclass 7, count 0 2006.246.08:13:49.81#ibcon#read 4, iclass 7, count 0 2006.246.08:13:49.81#ibcon#about to read 5, iclass 7, count 0 2006.246.08:13:49.81#ibcon#read 5, iclass 7, count 0 2006.246.08:13:49.81#ibcon#about to read 6, iclass 7, count 0 2006.246.08:13:49.81#ibcon#read 6, iclass 7, count 0 2006.246.08:13:49.81#ibcon#end of sib2, iclass 7, count 0 2006.246.08:13:49.81#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:13:49.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:13:49.81#ibcon#[25=USB\r\n] 2006.246.08:13:49.81#ibcon#*before write, iclass 7, count 0 2006.246.08:13:49.81#ibcon#enter sib2, iclass 7, count 0 2006.246.08:13:49.81#ibcon#flushed, iclass 7, count 0 2006.246.08:13:49.81#ibcon#about to write, iclass 7, count 0 2006.246.08:13:49.82#ibcon#wrote, iclass 7, count 0 2006.246.08:13:49.82#ibcon#about to read 3, iclass 7, count 0 2006.246.08:13:49.84#ibcon#read 3, iclass 7, count 0 2006.246.08:13:49.84#ibcon#about to read 4, iclass 7, count 0 2006.246.08:13:49.84#ibcon#read 4, iclass 7, count 0 2006.246.08:13:49.84#ibcon#about to read 5, iclass 7, count 0 2006.246.08:13:49.84#ibcon#read 5, iclass 7, count 0 2006.246.08:13:49.84#ibcon#about to read 6, iclass 7, count 0 2006.246.08:13:49.84#ibcon#read 6, iclass 7, count 0 2006.246.08:13:49.84#ibcon#end of sib2, iclass 7, count 0 2006.246.08:13:49.84#ibcon#*after write, iclass 7, count 0 2006.246.08:13:49.84#ibcon#*before return 0, iclass 7, count 0 2006.246.08:13:49.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:49.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:49.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:13:49.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:13:49.85$vc4f8/valo=7,832.99 2006.246.08:13:49.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.08:13:49.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.08:13:49.85#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:49.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:49.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:49.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:49.85#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:13:49.85#ibcon#first serial, iclass 11, count 0 2006.246.08:13:49.85#ibcon#enter sib2, iclass 11, count 0 2006.246.08:13:49.85#ibcon#flushed, iclass 11, count 0 2006.246.08:13:49.85#ibcon#about to write, iclass 11, count 0 2006.246.08:13:49.85#ibcon#wrote, iclass 11, count 0 2006.246.08:13:49.85#ibcon#about to read 3, iclass 11, count 0 2006.246.08:13:49.86#ibcon#read 3, iclass 11, count 0 2006.246.08:13:49.86#ibcon#about to read 4, iclass 11, count 0 2006.246.08:13:49.86#ibcon#read 4, iclass 11, count 0 2006.246.08:13:49.86#ibcon#about to read 5, iclass 11, count 0 2006.246.08:13:49.86#ibcon#read 5, iclass 11, count 0 2006.246.08:13:49.86#ibcon#about to read 6, iclass 11, count 0 2006.246.08:13:49.86#ibcon#read 6, iclass 11, count 0 2006.246.08:13:49.86#ibcon#end of sib2, iclass 11, count 0 2006.246.08:13:49.86#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:13:49.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:13:49.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:13:49.86#ibcon#*before write, iclass 11, count 0 2006.246.08:13:49.86#ibcon#enter sib2, iclass 11, count 0 2006.246.08:13:49.86#ibcon#flushed, iclass 11, count 0 2006.246.08:13:49.86#ibcon#about to write, iclass 11, count 0 2006.246.08:13:49.87#ibcon#wrote, iclass 11, count 0 2006.246.08:13:49.87#ibcon#about to read 3, iclass 11, count 0 2006.246.08:13:49.90#ibcon#read 3, iclass 11, count 0 2006.246.08:13:49.90#ibcon#about to read 4, iclass 11, count 0 2006.246.08:13:49.90#ibcon#read 4, iclass 11, count 0 2006.246.08:13:49.90#ibcon#about to read 5, iclass 11, count 0 2006.246.08:13:49.90#ibcon#read 5, iclass 11, count 0 2006.246.08:13:49.90#ibcon#about to read 6, iclass 11, count 0 2006.246.08:13:49.90#ibcon#read 6, iclass 11, count 0 2006.246.08:13:49.90#ibcon#end of sib2, iclass 11, count 0 2006.246.08:13:49.90#ibcon#*after write, iclass 11, count 0 2006.246.08:13:49.90#ibcon#*before return 0, iclass 11, count 0 2006.246.08:13:49.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:49.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:49.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:13:49.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:13:49.91$vc4f8/va=7,7 2006.246.08:13:49.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.08:13:49.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.08:13:49.91#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:49.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:13:49.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:13:49.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:13:49.95#ibcon#enter wrdev, iclass 13, count 2 2006.246.08:13:49.95#ibcon#first serial, iclass 13, count 2 2006.246.08:13:49.95#ibcon#enter sib2, iclass 13, count 2 2006.246.08:13:49.95#ibcon#flushed, iclass 13, count 2 2006.246.08:13:49.95#ibcon#about to write, iclass 13, count 2 2006.246.08:13:49.95#ibcon#wrote, iclass 13, count 2 2006.246.08:13:49.95#ibcon#about to read 3, iclass 13, count 2 2006.246.08:13:49.97#ibcon#read 3, iclass 13, count 2 2006.246.08:13:49.97#ibcon#about to read 4, iclass 13, count 2 2006.246.08:13:49.97#ibcon#read 4, iclass 13, count 2 2006.246.08:13:49.97#ibcon#about to read 5, iclass 13, count 2 2006.246.08:13:49.97#ibcon#read 5, iclass 13, count 2 2006.246.08:13:49.97#ibcon#about to read 6, iclass 13, count 2 2006.246.08:13:49.97#ibcon#read 6, iclass 13, count 2 2006.246.08:13:49.97#ibcon#end of sib2, iclass 13, count 2 2006.246.08:13:49.97#ibcon#*mode == 0, iclass 13, count 2 2006.246.08:13:49.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.08:13:49.97#ibcon#[25=AT07-07\r\n] 2006.246.08:13:49.97#ibcon#*before write, iclass 13, count 2 2006.246.08:13:49.97#ibcon#enter sib2, iclass 13, count 2 2006.246.08:13:49.97#ibcon#flushed, iclass 13, count 2 2006.246.08:13:49.97#ibcon#about to write, iclass 13, count 2 2006.246.08:13:49.98#ibcon#wrote, iclass 13, count 2 2006.246.08:13:49.98#ibcon#about to read 3, iclass 13, count 2 2006.246.08:13:50.00#ibcon#read 3, iclass 13, count 2 2006.246.08:13:50.00#ibcon#about to read 4, iclass 13, count 2 2006.246.08:13:50.00#ibcon#read 4, iclass 13, count 2 2006.246.08:13:50.00#ibcon#about to read 5, iclass 13, count 2 2006.246.08:13:50.00#ibcon#read 5, iclass 13, count 2 2006.246.08:13:50.00#ibcon#about to read 6, iclass 13, count 2 2006.246.08:13:50.00#ibcon#read 6, iclass 13, count 2 2006.246.08:13:50.00#ibcon#end of sib2, iclass 13, count 2 2006.246.08:13:50.00#ibcon#*after write, iclass 13, count 2 2006.246.08:13:50.00#ibcon#*before return 0, iclass 13, count 2 2006.246.08:13:50.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:13:50.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:13:50.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.08:13:50.01#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:50.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:13:50.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:13:50.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:13:50.12#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:13:50.12#ibcon#first serial, iclass 13, count 0 2006.246.08:13:50.12#ibcon#enter sib2, iclass 13, count 0 2006.246.08:13:50.12#ibcon#flushed, iclass 13, count 0 2006.246.08:13:50.12#ibcon#about to write, iclass 13, count 0 2006.246.08:13:50.12#ibcon#wrote, iclass 13, count 0 2006.246.08:13:50.12#ibcon#about to read 3, iclass 13, count 0 2006.246.08:13:50.14#ibcon#read 3, iclass 13, count 0 2006.246.08:13:50.14#ibcon#about to read 4, iclass 13, count 0 2006.246.08:13:50.14#ibcon#read 4, iclass 13, count 0 2006.246.08:13:50.14#ibcon#about to read 5, iclass 13, count 0 2006.246.08:13:50.14#ibcon#read 5, iclass 13, count 0 2006.246.08:13:50.14#ibcon#about to read 6, iclass 13, count 0 2006.246.08:13:50.14#ibcon#read 6, iclass 13, count 0 2006.246.08:13:50.14#ibcon#end of sib2, iclass 13, count 0 2006.246.08:13:50.14#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:13:50.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:13:50.14#ibcon#[25=USB\r\n] 2006.246.08:13:50.14#ibcon#*before write, iclass 13, count 0 2006.246.08:13:50.14#ibcon#enter sib2, iclass 13, count 0 2006.246.08:13:50.14#ibcon#flushed, iclass 13, count 0 2006.246.08:13:50.15#ibcon#about to write, iclass 13, count 0 2006.246.08:13:50.15#ibcon#wrote, iclass 13, count 0 2006.246.08:13:50.15#ibcon#about to read 3, iclass 13, count 0 2006.246.08:13:50.17#ibcon#read 3, iclass 13, count 0 2006.246.08:13:50.17#ibcon#about to read 4, iclass 13, count 0 2006.246.08:13:50.17#ibcon#read 4, iclass 13, count 0 2006.246.08:13:50.17#ibcon#about to read 5, iclass 13, count 0 2006.246.08:13:50.17#ibcon#read 5, iclass 13, count 0 2006.246.08:13:50.17#ibcon#about to read 6, iclass 13, count 0 2006.246.08:13:50.17#ibcon#read 6, iclass 13, count 0 2006.246.08:13:50.17#ibcon#end of sib2, iclass 13, count 0 2006.246.08:13:50.17#ibcon#*after write, iclass 13, count 0 2006.246.08:13:50.17#ibcon#*before return 0, iclass 13, count 0 2006.246.08:13:50.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:13:50.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:13:50.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:13:50.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:13:50.18$vc4f8/valo=8,852.99 2006.246.08:13:50.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.08:13:50.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.08:13:50.18#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:50.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:13:50.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:13:50.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:13:50.18#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:13:50.18#ibcon#first serial, iclass 15, count 0 2006.246.08:13:50.18#ibcon#enter sib2, iclass 15, count 0 2006.246.08:13:50.18#ibcon#flushed, iclass 15, count 0 2006.246.08:13:50.18#ibcon#about to write, iclass 15, count 0 2006.246.08:13:50.18#ibcon#wrote, iclass 15, count 0 2006.246.08:13:50.18#ibcon#about to read 3, iclass 15, count 0 2006.246.08:13:50.20#ibcon#read 3, iclass 15, count 0 2006.246.08:13:50.20#ibcon#about to read 4, iclass 15, count 0 2006.246.08:13:50.20#ibcon#read 4, iclass 15, count 0 2006.246.08:13:50.20#ibcon#about to read 5, iclass 15, count 0 2006.246.08:13:50.20#ibcon#read 5, iclass 15, count 0 2006.246.08:13:50.20#ibcon#about to read 6, iclass 15, count 0 2006.246.08:13:50.20#ibcon#read 6, iclass 15, count 0 2006.246.08:13:50.20#ibcon#end of sib2, iclass 15, count 0 2006.246.08:13:50.20#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:13:50.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:13:50.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:13:50.20#ibcon#*before write, iclass 15, count 0 2006.246.08:13:50.20#ibcon#enter sib2, iclass 15, count 0 2006.246.08:13:50.20#ibcon#flushed, iclass 15, count 0 2006.246.08:13:50.20#ibcon#about to write, iclass 15, count 0 2006.246.08:13:50.20#ibcon#wrote, iclass 15, count 0 2006.246.08:13:50.20#ibcon#about to read 3, iclass 15, count 0 2006.246.08:13:50.24#ibcon#read 3, iclass 15, count 0 2006.246.08:13:50.24#ibcon#about to read 4, iclass 15, count 0 2006.246.08:13:50.24#ibcon#read 4, iclass 15, count 0 2006.246.08:13:50.24#ibcon#about to read 5, iclass 15, count 0 2006.246.08:13:50.24#ibcon#read 5, iclass 15, count 0 2006.246.08:13:50.24#ibcon#about to read 6, iclass 15, count 0 2006.246.08:13:50.24#ibcon#read 6, iclass 15, count 0 2006.246.08:13:50.24#ibcon#end of sib2, iclass 15, count 0 2006.246.08:13:50.24#ibcon#*after write, iclass 15, count 0 2006.246.08:13:50.24#ibcon#*before return 0, iclass 15, count 0 2006.246.08:13:50.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:13:50.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:13:50.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:13:50.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:13:50.25$vc4f8/va=8,8 2006.246.08:13:50.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.08:13:50.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.08:13:50.25#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:50.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:13:50.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:13:50.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:13:50.28#ibcon#enter wrdev, iclass 17, count 2 2006.246.08:13:50.28#ibcon#first serial, iclass 17, count 2 2006.246.08:13:50.28#ibcon#enter sib2, iclass 17, count 2 2006.246.08:13:50.28#ibcon#flushed, iclass 17, count 2 2006.246.08:13:50.28#ibcon#about to write, iclass 17, count 2 2006.246.08:13:50.28#ibcon#wrote, iclass 17, count 2 2006.246.08:13:50.28#ibcon#about to read 3, iclass 17, count 2 2006.246.08:13:50.30#abcon#<5=/04 3.5 6.8 26.39 751005.7\r\n> 2006.246.08:13:50.30#ibcon#read 3, iclass 17, count 2 2006.246.08:13:50.30#ibcon#about to read 4, iclass 17, count 2 2006.246.08:13:50.30#ibcon#read 4, iclass 17, count 2 2006.246.08:13:50.30#ibcon#about to read 5, iclass 17, count 2 2006.246.08:13:50.30#ibcon#read 5, iclass 17, count 2 2006.246.08:13:50.30#ibcon#about to read 6, iclass 17, count 2 2006.246.08:13:50.30#ibcon#read 6, iclass 17, count 2 2006.246.08:13:50.30#ibcon#end of sib2, iclass 17, count 2 2006.246.08:13:50.30#ibcon#*mode == 0, iclass 17, count 2 2006.246.08:13:50.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.08:13:50.31#ibcon#[25=AT08-08\r\n] 2006.246.08:13:50.31#ibcon#*before write, iclass 17, count 2 2006.246.08:13:50.31#ibcon#enter sib2, iclass 17, count 2 2006.246.08:13:50.31#ibcon#flushed, iclass 17, count 2 2006.246.08:13:50.31#ibcon#about to write, iclass 17, count 2 2006.246.08:13:50.31#ibcon#wrote, iclass 17, count 2 2006.246.08:13:50.31#ibcon#about to read 3, iclass 17, count 2 2006.246.08:13:50.32#abcon#{5=INTERFACE CLEAR} 2006.246.08:13:50.33#ibcon#read 3, iclass 17, count 2 2006.246.08:13:50.33#ibcon#about to read 4, iclass 17, count 2 2006.246.08:13:50.33#ibcon#read 4, iclass 17, count 2 2006.246.08:13:50.33#ibcon#about to read 5, iclass 17, count 2 2006.246.08:13:50.33#ibcon#read 5, iclass 17, count 2 2006.246.08:13:50.33#ibcon#about to read 6, iclass 17, count 2 2006.246.08:13:50.33#ibcon#read 6, iclass 17, count 2 2006.246.08:13:50.33#ibcon#end of sib2, iclass 17, count 2 2006.246.08:13:50.33#ibcon#*after write, iclass 17, count 2 2006.246.08:13:50.33#ibcon#*before return 0, iclass 17, count 2 2006.246.08:13:50.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:13:50.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:13:50.34#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.08:13:50.34#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:50.34#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:13:50.37#abcon#[5=S1D000X0/0*\r\n] 2006.246.08:13:50.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:13:50.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:13:50.44#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:13:50.44#ibcon#first serial, iclass 17, count 0 2006.246.08:13:50.44#ibcon#enter sib2, iclass 17, count 0 2006.246.08:13:50.44#ibcon#flushed, iclass 17, count 0 2006.246.08:13:50.44#ibcon#about to write, iclass 17, count 0 2006.246.08:13:50.44#ibcon#wrote, iclass 17, count 0 2006.246.08:13:50.44#ibcon#about to read 3, iclass 17, count 0 2006.246.08:13:50.46#ibcon#read 3, iclass 17, count 0 2006.246.08:13:50.46#ibcon#about to read 4, iclass 17, count 0 2006.246.08:13:50.46#ibcon#read 4, iclass 17, count 0 2006.246.08:13:50.46#ibcon#about to read 5, iclass 17, count 0 2006.246.08:13:50.46#ibcon#read 5, iclass 17, count 0 2006.246.08:13:50.46#ibcon#about to read 6, iclass 17, count 0 2006.246.08:13:50.46#ibcon#read 6, iclass 17, count 0 2006.246.08:13:50.46#ibcon#end of sib2, iclass 17, count 0 2006.246.08:13:50.46#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:13:50.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:13:50.46#ibcon#[25=USB\r\n] 2006.246.08:13:50.46#ibcon#*before write, iclass 17, count 0 2006.246.08:13:50.46#ibcon#enter sib2, iclass 17, count 0 2006.246.08:13:50.46#ibcon#flushed, iclass 17, count 0 2006.246.08:13:50.46#ibcon#about to write, iclass 17, count 0 2006.246.08:13:50.47#ibcon#wrote, iclass 17, count 0 2006.246.08:13:50.47#ibcon#about to read 3, iclass 17, count 0 2006.246.08:13:50.49#ibcon#read 3, iclass 17, count 0 2006.246.08:13:50.49#ibcon#about to read 4, iclass 17, count 0 2006.246.08:13:50.49#ibcon#read 4, iclass 17, count 0 2006.246.08:13:50.49#ibcon#about to read 5, iclass 17, count 0 2006.246.08:13:50.49#ibcon#read 5, iclass 17, count 0 2006.246.08:13:50.49#ibcon#about to read 6, iclass 17, count 0 2006.246.08:13:50.49#ibcon#read 6, iclass 17, count 0 2006.246.08:13:50.49#ibcon#end of sib2, iclass 17, count 0 2006.246.08:13:50.49#ibcon#*after write, iclass 17, count 0 2006.246.08:13:50.49#ibcon#*before return 0, iclass 17, count 0 2006.246.08:13:50.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:13:50.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:13:50.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:13:50.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:13:50.50$vc4f8/vblo=1,632.99 2006.246.08:13:50.50#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:13:50.50#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:13:50.50#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:50.50#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:50.50#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:50.50#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:50.50#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:13:50.50#ibcon#first serial, iclass 23, count 0 2006.246.08:13:50.50#ibcon#enter sib2, iclass 23, count 0 2006.246.08:13:50.50#ibcon#flushed, iclass 23, count 0 2006.246.08:13:50.50#ibcon#about to write, iclass 23, count 0 2006.246.08:13:50.50#ibcon#wrote, iclass 23, count 0 2006.246.08:13:50.50#ibcon#about to read 3, iclass 23, count 0 2006.246.08:13:50.51#ibcon#read 3, iclass 23, count 0 2006.246.08:13:50.51#ibcon#about to read 4, iclass 23, count 0 2006.246.08:13:50.51#ibcon#read 4, iclass 23, count 0 2006.246.08:13:50.51#ibcon#about to read 5, iclass 23, count 0 2006.246.08:13:50.51#ibcon#read 5, iclass 23, count 0 2006.246.08:13:50.51#ibcon#about to read 6, iclass 23, count 0 2006.246.08:13:50.51#ibcon#read 6, iclass 23, count 0 2006.246.08:13:50.51#ibcon#end of sib2, iclass 23, count 0 2006.246.08:13:50.51#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:13:50.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:13:50.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:13:50.51#ibcon#*before write, iclass 23, count 0 2006.246.08:13:50.51#ibcon#enter sib2, iclass 23, count 0 2006.246.08:13:50.51#ibcon#flushed, iclass 23, count 0 2006.246.08:13:50.51#ibcon#about to write, iclass 23, count 0 2006.246.08:13:50.52#ibcon#wrote, iclass 23, count 0 2006.246.08:13:50.52#ibcon#about to read 3, iclass 23, count 0 2006.246.08:13:50.55#ibcon#read 3, iclass 23, count 0 2006.246.08:13:50.55#ibcon#about to read 4, iclass 23, count 0 2006.246.08:13:50.55#ibcon#read 4, iclass 23, count 0 2006.246.08:13:50.55#ibcon#about to read 5, iclass 23, count 0 2006.246.08:13:50.55#ibcon#read 5, iclass 23, count 0 2006.246.08:13:50.55#ibcon#about to read 6, iclass 23, count 0 2006.246.08:13:50.55#ibcon#read 6, iclass 23, count 0 2006.246.08:13:50.55#ibcon#end of sib2, iclass 23, count 0 2006.246.08:13:50.55#ibcon#*after write, iclass 23, count 0 2006.246.08:13:50.55#ibcon#*before return 0, iclass 23, count 0 2006.246.08:13:50.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:50.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:13:50.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:13:50.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:13:50.56$vc4f8/vb=1,4 2006.246.08:13:50.56#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:13:50.56#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:13:50.56#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:50.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:50.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:50.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:50.56#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:13:50.56#ibcon#first serial, iclass 25, count 2 2006.246.08:13:50.56#ibcon#enter sib2, iclass 25, count 2 2006.246.08:13:50.56#ibcon#flushed, iclass 25, count 2 2006.246.08:13:50.56#ibcon#about to write, iclass 25, count 2 2006.246.08:13:50.56#ibcon#wrote, iclass 25, count 2 2006.246.08:13:50.56#ibcon#about to read 3, iclass 25, count 2 2006.246.08:13:50.57#ibcon#read 3, iclass 25, count 2 2006.246.08:13:50.57#ibcon#about to read 4, iclass 25, count 2 2006.246.08:13:50.57#ibcon#read 4, iclass 25, count 2 2006.246.08:13:50.57#ibcon#about to read 5, iclass 25, count 2 2006.246.08:13:50.57#ibcon#read 5, iclass 25, count 2 2006.246.08:13:50.57#ibcon#about to read 6, iclass 25, count 2 2006.246.08:13:50.57#ibcon#read 6, iclass 25, count 2 2006.246.08:13:50.57#ibcon#end of sib2, iclass 25, count 2 2006.246.08:13:50.57#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:13:50.57#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:13:50.57#ibcon#[27=AT01-04\r\n] 2006.246.08:13:50.57#ibcon#*before write, iclass 25, count 2 2006.246.08:13:50.57#ibcon#enter sib2, iclass 25, count 2 2006.246.08:13:50.57#ibcon#flushed, iclass 25, count 2 2006.246.08:13:50.57#ibcon#about to write, iclass 25, count 2 2006.246.08:13:50.58#ibcon#wrote, iclass 25, count 2 2006.246.08:13:50.58#ibcon#about to read 3, iclass 25, count 2 2006.246.08:13:50.60#ibcon#read 3, iclass 25, count 2 2006.246.08:13:50.60#ibcon#about to read 4, iclass 25, count 2 2006.246.08:13:50.60#ibcon#read 4, iclass 25, count 2 2006.246.08:13:50.60#ibcon#about to read 5, iclass 25, count 2 2006.246.08:13:50.60#ibcon#read 5, iclass 25, count 2 2006.246.08:13:50.60#ibcon#about to read 6, iclass 25, count 2 2006.246.08:13:50.60#ibcon#read 6, iclass 25, count 2 2006.246.08:13:50.60#ibcon#end of sib2, iclass 25, count 2 2006.246.08:13:50.60#ibcon#*after write, iclass 25, count 2 2006.246.08:13:50.60#ibcon#*before return 0, iclass 25, count 2 2006.246.08:13:50.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:50.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:13:50.60#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:13:50.60#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:50.61#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:50.72#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:50.72#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:50.72#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:13:50.72#ibcon#first serial, iclass 25, count 0 2006.246.08:13:50.72#ibcon#enter sib2, iclass 25, count 0 2006.246.08:13:50.72#ibcon#flushed, iclass 25, count 0 2006.246.08:13:50.72#ibcon#about to write, iclass 25, count 0 2006.246.08:13:50.72#ibcon#wrote, iclass 25, count 0 2006.246.08:13:50.72#ibcon#about to read 3, iclass 25, count 0 2006.246.08:13:50.74#ibcon#read 3, iclass 25, count 0 2006.246.08:13:50.74#ibcon#about to read 4, iclass 25, count 0 2006.246.08:13:50.74#ibcon#read 4, iclass 25, count 0 2006.246.08:13:50.74#ibcon#about to read 5, iclass 25, count 0 2006.246.08:13:50.74#ibcon#read 5, iclass 25, count 0 2006.246.08:13:50.74#ibcon#about to read 6, iclass 25, count 0 2006.246.08:13:50.74#ibcon#read 6, iclass 25, count 0 2006.246.08:13:50.74#ibcon#end of sib2, iclass 25, count 0 2006.246.08:13:50.74#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:13:50.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:13:50.74#ibcon#[27=USB\r\n] 2006.246.08:13:50.74#ibcon#*before write, iclass 25, count 0 2006.246.08:13:50.74#ibcon#enter sib2, iclass 25, count 0 2006.246.08:13:50.74#ibcon#flushed, iclass 25, count 0 2006.246.08:13:50.74#ibcon#about to write, iclass 25, count 0 2006.246.08:13:50.75#ibcon#wrote, iclass 25, count 0 2006.246.08:13:50.75#ibcon#about to read 3, iclass 25, count 0 2006.246.08:13:50.77#ibcon#read 3, iclass 25, count 0 2006.246.08:13:50.77#ibcon#about to read 4, iclass 25, count 0 2006.246.08:13:50.77#ibcon#read 4, iclass 25, count 0 2006.246.08:13:50.77#ibcon#about to read 5, iclass 25, count 0 2006.246.08:13:50.77#ibcon#read 5, iclass 25, count 0 2006.246.08:13:50.77#ibcon#about to read 6, iclass 25, count 0 2006.246.08:13:50.77#ibcon#read 6, iclass 25, count 0 2006.246.08:13:50.77#ibcon#end of sib2, iclass 25, count 0 2006.246.08:13:50.77#ibcon#*after write, iclass 25, count 0 2006.246.08:13:50.77#ibcon#*before return 0, iclass 25, count 0 2006.246.08:13:50.77#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:50.77#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:13:50.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:13:50.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:13:50.78$vc4f8/vblo=2,640.99 2006.246.08:13:50.78#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:13:50.78#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:13:50.78#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:50.78#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:50.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:50.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:50.78#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:13:50.78#ibcon#first serial, iclass 27, count 0 2006.246.08:13:50.78#ibcon#enter sib2, iclass 27, count 0 2006.246.08:13:50.78#ibcon#flushed, iclass 27, count 0 2006.246.08:13:50.78#ibcon#about to write, iclass 27, count 0 2006.246.08:13:50.78#ibcon#wrote, iclass 27, count 0 2006.246.08:13:50.78#ibcon#about to read 3, iclass 27, count 0 2006.246.08:13:50.79#ibcon#read 3, iclass 27, count 0 2006.246.08:13:50.79#ibcon#about to read 4, iclass 27, count 0 2006.246.08:13:50.79#ibcon#read 4, iclass 27, count 0 2006.246.08:13:50.79#ibcon#about to read 5, iclass 27, count 0 2006.246.08:13:50.79#ibcon#read 5, iclass 27, count 0 2006.246.08:13:50.79#ibcon#about to read 6, iclass 27, count 0 2006.246.08:13:50.79#ibcon#read 6, iclass 27, count 0 2006.246.08:13:50.79#ibcon#end of sib2, iclass 27, count 0 2006.246.08:13:50.79#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:13:50.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:13:50.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:13:50.79#ibcon#*before write, iclass 27, count 0 2006.246.08:13:50.79#ibcon#enter sib2, iclass 27, count 0 2006.246.08:13:50.79#ibcon#flushed, iclass 27, count 0 2006.246.08:13:50.79#ibcon#about to write, iclass 27, count 0 2006.246.08:13:50.80#ibcon#wrote, iclass 27, count 0 2006.246.08:13:50.80#ibcon#about to read 3, iclass 27, count 0 2006.246.08:13:50.83#ibcon#read 3, iclass 27, count 0 2006.246.08:13:50.83#ibcon#about to read 4, iclass 27, count 0 2006.246.08:13:50.83#ibcon#read 4, iclass 27, count 0 2006.246.08:13:50.83#ibcon#about to read 5, iclass 27, count 0 2006.246.08:13:50.83#ibcon#read 5, iclass 27, count 0 2006.246.08:13:50.83#ibcon#about to read 6, iclass 27, count 0 2006.246.08:13:50.83#ibcon#read 6, iclass 27, count 0 2006.246.08:13:50.83#ibcon#end of sib2, iclass 27, count 0 2006.246.08:13:50.83#ibcon#*after write, iclass 27, count 0 2006.246.08:13:50.83#ibcon#*before return 0, iclass 27, count 0 2006.246.08:13:50.83#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:50.83#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:13:50.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:13:50.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:13:50.84$vc4f8/vb=2,4 2006.246.08:13:50.84#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:13:50.84#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:13:50.84#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:50.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:50.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:50.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:50.88#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:13:50.88#ibcon#first serial, iclass 29, count 2 2006.246.08:13:50.88#ibcon#enter sib2, iclass 29, count 2 2006.246.08:13:50.88#ibcon#flushed, iclass 29, count 2 2006.246.08:13:50.88#ibcon#about to write, iclass 29, count 2 2006.246.08:13:50.88#ibcon#wrote, iclass 29, count 2 2006.246.08:13:50.88#ibcon#about to read 3, iclass 29, count 2 2006.246.08:13:50.90#ibcon#read 3, iclass 29, count 2 2006.246.08:13:50.90#ibcon#about to read 4, iclass 29, count 2 2006.246.08:13:50.90#ibcon#read 4, iclass 29, count 2 2006.246.08:13:50.90#ibcon#about to read 5, iclass 29, count 2 2006.246.08:13:50.90#ibcon#read 5, iclass 29, count 2 2006.246.08:13:50.90#ibcon#about to read 6, iclass 29, count 2 2006.246.08:13:50.90#ibcon#read 6, iclass 29, count 2 2006.246.08:13:50.90#ibcon#end of sib2, iclass 29, count 2 2006.246.08:13:50.90#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:13:50.90#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:13:50.90#ibcon#[27=AT02-04\r\n] 2006.246.08:13:50.90#ibcon#*before write, iclass 29, count 2 2006.246.08:13:50.90#ibcon#enter sib2, iclass 29, count 2 2006.246.08:13:50.90#ibcon#flushed, iclass 29, count 2 2006.246.08:13:50.90#ibcon#about to write, iclass 29, count 2 2006.246.08:13:50.91#ibcon#wrote, iclass 29, count 2 2006.246.08:13:50.91#ibcon#about to read 3, iclass 29, count 2 2006.246.08:13:50.93#ibcon#read 3, iclass 29, count 2 2006.246.08:13:50.93#ibcon#about to read 4, iclass 29, count 2 2006.246.08:13:50.93#ibcon#read 4, iclass 29, count 2 2006.246.08:13:50.93#ibcon#about to read 5, iclass 29, count 2 2006.246.08:13:50.93#ibcon#read 5, iclass 29, count 2 2006.246.08:13:50.93#ibcon#about to read 6, iclass 29, count 2 2006.246.08:13:50.93#ibcon#read 6, iclass 29, count 2 2006.246.08:13:50.93#ibcon#end of sib2, iclass 29, count 2 2006.246.08:13:50.93#ibcon#*after write, iclass 29, count 2 2006.246.08:13:50.93#ibcon#*before return 0, iclass 29, count 2 2006.246.08:13:50.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:50.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:13:50.94#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:13:50.94#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:50.94#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:51.05#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:51.05#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:51.05#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:13:51.05#ibcon#first serial, iclass 29, count 0 2006.246.08:13:51.05#ibcon#enter sib2, iclass 29, count 0 2006.246.08:13:51.05#ibcon#flushed, iclass 29, count 0 2006.246.08:13:51.05#ibcon#about to write, iclass 29, count 0 2006.246.08:13:51.05#ibcon#wrote, iclass 29, count 0 2006.246.08:13:51.05#ibcon#about to read 3, iclass 29, count 0 2006.246.08:13:51.07#ibcon#read 3, iclass 29, count 0 2006.246.08:13:51.07#ibcon#about to read 4, iclass 29, count 0 2006.246.08:13:51.07#ibcon#read 4, iclass 29, count 0 2006.246.08:13:51.07#ibcon#about to read 5, iclass 29, count 0 2006.246.08:13:51.07#ibcon#read 5, iclass 29, count 0 2006.246.08:13:51.07#ibcon#about to read 6, iclass 29, count 0 2006.246.08:13:51.07#ibcon#read 6, iclass 29, count 0 2006.246.08:13:51.07#ibcon#end of sib2, iclass 29, count 0 2006.246.08:13:51.07#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:13:51.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:13:51.07#ibcon#[27=USB\r\n] 2006.246.08:13:51.07#ibcon#*before write, iclass 29, count 0 2006.246.08:13:51.07#ibcon#enter sib2, iclass 29, count 0 2006.246.08:13:51.07#ibcon#flushed, iclass 29, count 0 2006.246.08:13:51.07#ibcon#about to write, iclass 29, count 0 2006.246.08:13:51.08#ibcon#wrote, iclass 29, count 0 2006.246.08:13:51.08#ibcon#about to read 3, iclass 29, count 0 2006.246.08:13:51.10#ibcon#read 3, iclass 29, count 0 2006.246.08:13:51.10#ibcon#about to read 4, iclass 29, count 0 2006.246.08:13:51.10#ibcon#read 4, iclass 29, count 0 2006.246.08:13:51.10#ibcon#about to read 5, iclass 29, count 0 2006.246.08:13:51.10#ibcon#read 5, iclass 29, count 0 2006.246.08:13:51.10#ibcon#about to read 6, iclass 29, count 0 2006.246.08:13:51.10#ibcon#read 6, iclass 29, count 0 2006.246.08:13:51.10#ibcon#end of sib2, iclass 29, count 0 2006.246.08:13:51.10#ibcon#*after write, iclass 29, count 0 2006.246.08:13:51.10#ibcon#*before return 0, iclass 29, count 0 2006.246.08:13:51.10#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:51.10#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:13:51.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:13:51.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:13:51.11$vc4f8/vblo=3,656.99 2006.246.08:13:51.11#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:13:51.11#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:13:51.11#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:51.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:51.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:51.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:51.11#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:13:51.11#ibcon#first serial, iclass 31, count 0 2006.246.08:13:51.11#ibcon#enter sib2, iclass 31, count 0 2006.246.08:13:51.11#ibcon#flushed, iclass 31, count 0 2006.246.08:13:51.11#ibcon#about to write, iclass 31, count 0 2006.246.08:13:51.11#ibcon#wrote, iclass 31, count 0 2006.246.08:13:51.11#ibcon#about to read 3, iclass 31, count 0 2006.246.08:13:51.13#ibcon#read 3, iclass 31, count 0 2006.246.08:13:51.13#ibcon#about to read 4, iclass 31, count 0 2006.246.08:13:51.13#ibcon#read 4, iclass 31, count 0 2006.246.08:13:51.13#ibcon#about to read 5, iclass 31, count 0 2006.246.08:13:51.13#ibcon#read 5, iclass 31, count 0 2006.246.08:13:51.13#ibcon#about to read 6, iclass 31, count 0 2006.246.08:13:51.13#ibcon#read 6, iclass 31, count 0 2006.246.08:13:51.13#ibcon#end of sib2, iclass 31, count 0 2006.246.08:13:51.13#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:13:51.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:13:51.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:13:51.13#ibcon#*before write, iclass 31, count 0 2006.246.08:13:51.13#ibcon#enter sib2, iclass 31, count 0 2006.246.08:13:51.13#ibcon#flushed, iclass 31, count 0 2006.246.08:13:51.13#ibcon#about to write, iclass 31, count 0 2006.246.08:13:51.13#ibcon#wrote, iclass 31, count 0 2006.246.08:13:51.13#ibcon#about to read 3, iclass 31, count 0 2006.246.08:13:51.16#ibcon#read 3, iclass 31, count 0 2006.246.08:13:51.16#ibcon#about to read 4, iclass 31, count 0 2006.246.08:13:51.16#ibcon#read 4, iclass 31, count 0 2006.246.08:13:51.16#ibcon#about to read 5, iclass 31, count 0 2006.246.08:13:51.16#ibcon#read 5, iclass 31, count 0 2006.246.08:13:51.16#ibcon#about to read 6, iclass 31, count 0 2006.246.08:13:51.16#ibcon#read 6, iclass 31, count 0 2006.246.08:13:51.16#ibcon#end of sib2, iclass 31, count 0 2006.246.08:13:51.16#ibcon#*after write, iclass 31, count 0 2006.246.08:13:51.16#ibcon#*before return 0, iclass 31, count 0 2006.246.08:13:51.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:51.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:13:51.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:13:51.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:13:51.17$vc4f8/vb=3,4 2006.246.08:13:51.17#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:13:51.17#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:13:51.17#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:51.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:51.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:51.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:51.21#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:13:51.21#ibcon#first serial, iclass 33, count 2 2006.246.08:13:51.21#ibcon#enter sib2, iclass 33, count 2 2006.246.08:13:51.21#ibcon#flushed, iclass 33, count 2 2006.246.08:13:51.21#ibcon#about to write, iclass 33, count 2 2006.246.08:13:51.21#ibcon#wrote, iclass 33, count 2 2006.246.08:13:51.21#ibcon#about to read 3, iclass 33, count 2 2006.246.08:13:51.23#ibcon#read 3, iclass 33, count 2 2006.246.08:13:51.23#ibcon#about to read 4, iclass 33, count 2 2006.246.08:13:51.23#ibcon#read 4, iclass 33, count 2 2006.246.08:13:51.23#ibcon#about to read 5, iclass 33, count 2 2006.246.08:13:51.23#ibcon#read 5, iclass 33, count 2 2006.246.08:13:51.23#ibcon#about to read 6, iclass 33, count 2 2006.246.08:13:51.23#ibcon#read 6, iclass 33, count 2 2006.246.08:13:51.23#ibcon#end of sib2, iclass 33, count 2 2006.246.08:13:51.23#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:13:51.23#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:13:51.23#ibcon#[27=AT03-04\r\n] 2006.246.08:13:51.23#ibcon#*before write, iclass 33, count 2 2006.246.08:13:51.23#ibcon#enter sib2, iclass 33, count 2 2006.246.08:13:51.23#ibcon#flushed, iclass 33, count 2 2006.246.08:13:51.23#ibcon#about to write, iclass 33, count 2 2006.246.08:13:51.24#ibcon#wrote, iclass 33, count 2 2006.246.08:13:51.24#ibcon#about to read 3, iclass 33, count 2 2006.246.08:13:51.26#ibcon#read 3, iclass 33, count 2 2006.246.08:13:51.26#ibcon#about to read 4, iclass 33, count 2 2006.246.08:13:51.26#ibcon#read 4, iclass 33, count 2 2006.246.08:13:51.26#ibcon#about to read 5, iclass 33, count 2 2006.246.08:13:51.26#ibcon#read 5, iclass 33, count 2 2006.246.08:13:51.26#ibcon#about to read 6, iclass 33, count 2 2006.246.08:13:51.26#ibcon#read 6, iclass 33, count 2 2006.246.08:13:51.26#ibcon#end of sib2, iclass 33, count 2 2006.246.08:13:51.26#ibcon#*after write, iclass 33, count 2 2006.246.08:13:51.26#ibcon#*before return 0, iclass 33, count 2 2006.246.08:13:51.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:51.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:13:51.26#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:13:51.26#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:51.27#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:51.38#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:51.38#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:51.38#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:13:51.38#ibcon#first serial, iclass 33, count 0 2006.246.08:13:51.38#ibcon#enter sib2, iclass 33, count 0 2006.246.08:13:51.38#ibcon#flushed, iclass 33, count 0 2006.246.08:13:51.38#ibcon#about to write, iclass 33, count 0 2006.246.08:13:51.38#ibcon#wrote, iclass 33, count 0 2006.246.08:13:51.38#ibcon#about to read 3, iclass 33, count 0 2006.246.08:13:51.40#ibcon#read 3, iclass 33, count 0 2006.246.08:13:51.40#ibcon#about to read 4, iclass 33, count 0 2006.246.08:13:51.40#ibcon#read 4, iclass 33, count 0 2006.246.08:13:51.40#ibcon#about to read 5, iclass 33, count 0 2006.246.08:13:51.40#ibcon#read 5, iclass 33, count 0 2006.246.08:13:51.40#ibcon#about to read 6, iclass 33, count 0 2006.246.08:13:51.40#ibcon#read 6, iclass 33, count 0 2006.246.08:13:51.40#ibcon#end of sib2, iclass 33, count 0 2006.246.08:13:51.40#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:13:51.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:13:51.40#ibcon#[27=USB\r\n] 2006.246.08:13:51.40#ibcon#*before write, iclass 33, count 0 2006.246.08:13:51.41#ibcon#enter sib2, iclass 33, count 0 2006.246.08:13:51.41#ibcon#flushed, iclass 33, count 0 2006.246.08:13:51.41#ibcon#about to write, iclass 33, count 0 2006.246.08:13:51.41#ibcon#wrote, iclass 33, count 0 2006.246.08:13:51.41#ibcon#about to read 3, iclass 33, count 0 2006.246.08:13:51.43#ibcon#read 3, iclass 33, count 0 2006.246.08:13:51.43#ibcon#about to read 4, iclass 33, count 0 2006.246.08:13:51.43#ibcon#read 4, iclass 33, count 0 2006.246.08:13:51.43#ibcon#about to read 5, iclass 33, count 0 2006.246.08:13:51.43#ibcon#read 5, iclass 33, count 0 2006.246.08:13:51.43#ibcon#about to read 6, iclass 33, count 0 2006.246.08:13:51.43#ibcon#read 6, iclass 33, count 0 2006.246.08:13:51.43#ibcon#end of sib2, iclass 33, count 0 2006.246.08:13:51.43#ibcon#*after write, iclass 33, count 0 2006.246.08:13:51.43#ibcon#*before return 0, iclass 33, count 0 2006.246.08:13:51.43#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:51.43#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:13:51.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:13:51.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:13:51.44$vc4f8/vblo=4,712.99 2006.246.08:13:51.44#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:13:51.44#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:13:51.44#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:51.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:51.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:51.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:51.44#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:13:51.44#ibcon#first serial, iclass 35, count 0 2006.246.08:13:51.44#ibcon#enter sib2, iclass 35, count 0 2006.246.08:13:51.44#ibcon#flushed, iclass 35, count 0 2006.246.08:13:51.44#ibcon#about to write, iclass 35, count 0 2006.246.08:13:51.44#ibcon#wrote, iclass 35, count 0 2006.246.08:13:51.44#ibcon#about to read 3, iclass 35, count 0 2006.246.08:13:51.45#ibcon#read 3, iclass 35, count 0 2006.246.08:13:51.45#ibcon#about to read 4, iclass 35, count 0 2006.246.08:13:51.45#ibcon#read 4, iclass 35, count 0 2006.246.08:13:51.45#ibcon#about to read 5, iclass 35, count 0 2006.246.08:13:51.45#ibcon#read 5, iclass 35, count 0 2006.246.08:13:51.45#ibcon#about to read 6, iclass 35, count 0 2006.246.08:13:51.45#ibcon#read 6, iclass 35, count 0 2006.246.08:13:51.45#ibcon#end of sib2, iclass 35, count 0 2006.246.08:13:51.45#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:13:51.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:13:51.45#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:13:51.45#ibcon#*before write, iclass 35, count 0 2006.246.08:13:51.45#ibcon#enter sib2, iclass 35, count 0 2006.246.08:13:51.45#ibcon#flushed, iclass 35, count 0 2006.246.08:13:51.45#ibcon#about to write, iclass 35, count 0 2006.246.08:13:51.46#ibcon#wrote, iclass 35, count 0 2006.246.08:13:51.46#ibcon#about to read 3, iclass 35, count 0 2006.246.08:13:51.49#ibcon#read 3, iclass 35, count 0 2006.246.08:13:51.49#ibcon#about to read 4, iclass 35, count 0 2006.246.08:13:51.49#ibcon#read 4, iclass 35, count 0 2006.246.08:13:51.49#ibcon#about to read 5, iclass 35, count 0 2006.246.08:13:51.49#ibcon#read 5, iclass 35, count 0 2006.246.08:13:51.49#ibcon#about to read 6, iclass 35, count 0 2006.246.08:13:51.49#ibcon#read 6, iclass 35, count 0 2006.246.08:13:51.49#ibcon#end of sib2, iclass 35, count 0 2006.246.08:13:51.49#ibcon#*after write, iclass 35, count 0 2006.246.08:13:51.49#ibcon#*before return 0, iclass 35, count 0 2006.246.08:13:51.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:51.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:13:51.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:13:51.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:13:51.50$vc4f8/vb=4,4 2006.246.08:13:51.50#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:13:51.50#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:13:51.50#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:51.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:51.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:51.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:51.54#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:13:51.54#ibcon#first serial, iclass 37, count 2 2006.246.08:13:51.54#ibcon#enter sib2, iclass 37, count 2 2006.246.08:13:51.54#ibcon#flushed, iclass 37, count 2 2006.246.08:13:51.54#ibcon#about to write, iclass 37, count 2 2006.246.08:13:51.54#ibcon#wrote, iclass 37, count 2 2006.246.08:13:51.54#ibcon#about to read 3, iclass 37, count 2 2006.246.08:13:51.56#ibcon#read 3, iclass 37, count 2 2006.246.08:13:51.56#ibcon#about to read 4, iclass 37, count 2 2006.246.08:13:51.56#ibcon#read 4, iclass 37, count 2 2006.246.08:13:51.56#ibcon#about to read 5, iclass 37, count 2 2006.246.08:13:51.56#ibcon#read 5, iclass 37, count 2 2006.246.08:13:51.56#ibcon#about to read 6, iclass 37, count 2 2006.246.08:13:51.56#ibcon#read 6, iclass 37, count 2 2006.246.08:13:51.56#ibcon#end of sib2, iclass 37, count 2 2006.246.08:13:51.56#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:13:51.56#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:13:51.56#ibcon#[27=AT04-04\r\n] 2006.246.08:13:51.56#ibcon#*before write, iclass 37, count 2 2006.246.08:13:51.56#ibcon#enter sib2, iclass 37, count 2 2006.246.08:13:51.56#ibcon#flushed, iclass 37, count 2 2006.246.08:13:51.56#ibcon#about to write, iclass 37, count 2 2006.246.08:13:51.57#ibcon#wrote, iclass 37, count 2 2006.246.08:13:51.57#ibcon#about to read 3, iclass 37, count 2 2006.246.08:13:51.59#ibcon#read 3, iclass 37, count 2 2006.246.08:13:51.59#ibcon#about to read 4, iclass 37, count 2 2006.246.08:13:51.59#ibcon#read 4, iclass 37, count 2 2006.246.08:13:51.59#ibcon#about to read 5, iclass 37, count 2 2006.246.08:13:51.59#ibcon#read 5, iclass 37, count 2 2006.246.08:13:51.59#ibcon#about to read 6, iclass 37, count 2 2006.246.08:13:51.59#ibcon#read 6, iclass 37, count 2 2006.246.08:13:51.59#ibcon#end of sib2, iclass 37, count 2 2006.246.08:13:51.59#ibcon#*after write, iclass 37, count 2 2006.246.08:13:51.59#ibcon#*before return 0, iclass 37, count 2 2006.246.08:13:51.59#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:51.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:13:51.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:13:51.60#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:51.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:51.71#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:51.71#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:51.71#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:13:51.71#ibcon#first serial, iclass 37, count 0 2006.246.08:13:51.71#ibcon#enter sib2, iclass 37, count 0 2006.246.08:13:51.71#ibcon#flushed, iclass 37, count 0 2006.246.08:13:51.71#ibcon#about to write, iclass 37, count 0 2006.246.08:13:51.71#ibcon#wrote, iclass 37, count 0 2006.246.08:13:51.71#ibcon#about to read 3, iclass 37, count 0 2006.246.08:13:51.73#ibcon#read 3, iclass 37, count 0 2006.246.08:13:51.73#ibcon#about to read 4, iclass 37, count 0 2006.246.08:13:51.73#ibcon#read 4, iclass 37, count 0 2006.246.08:13:51.73#ibcon#about to read 5, iclass 37, count 0 2006.246.08:13:51.73#ibcon#read 5, iclass 37, count 0 2006.246.08:13:51.73#ibcon#about to read 6, iclass 37, count 0 2006.246.08:13:51.73#ibcon#read 6, iclass 37, count 0 2006.246.08:13:51.73#ibcon#end of sib2, iclass 37, count 0 2006.246.08:13:51.73#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:13:51.73#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:13:51.73#ibcon#[27=USB\r\n] 2006.246.08:13:51.73#ibcon#*before write, iclass 37, count 0 2006.246.08:13:51.73#ibcon#enter sib2, iclass 37, count 0 2006.246.08:13:51.73#ibcon#flushed, iclass 37, count 0 2006.246.08:13:51.73#ibcon#about to write, iclass 37, count 0 2006.246.08:13:51.74#ibcon#wrote, iclass 37, count 0 2006.246.08:13:51.74#ibcon#about to read 3, iclass 37, count 0 2006.246.08:13:51.76#ibcon#read 3, iclass 37, count 0 2006.246.08:13:51.76#ibcon#about to read 4, iclass 37, count 0 2006.246.08:13:51.76#ibcon#read 4, iclass 37, count 0 2006.246.08:13:51.76#ibcon#about to read 5, iclass 37, count 0 2006.246.08:13:51.76#ibcon#read 5, iclass 37, count 0 2006.246.08:13:51.76#ibcon#about to read 6, iclass 37, count 0 2006.246.08:13:51.76#ibcon#read 6, iclass 37, count 0 2006.246.08:13:51.76#ibcon#end of sib2, iclass 37, count 0 2006.246.08:13:51.76#ibcon#*after write, iclass 37, count 0 2006.246.08:13:51.76#ibcon#*before return 0, iclass 37, count 0 2006.246.08:13:51.76#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:51.76#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:13:51.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:13:51.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:13:51.77$vc4f8/vblo=5,744.99 2006.246.08:13:51.77#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:13:51.77#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:13:51.77#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:51.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:51.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:51.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:51.77#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:13:51.77#ibcon#first serial, iclass 39, count 0 2006.246.08:13:51.77#ibcon#enter sib2, iclass 39, count 0 2006.246.08:13:51.77#ibcon#flushed, iclass 39, count 0 2006.246.08:13:51.77#ibcon#about to write, iclass 39, count 0 2006.246.08:13:51.77#ibcon#wrote, iclass 39, count 0 2006.246.08:13:51.77#ibcon#about to read 3, iclass 39, count 0 2006.246.08:13:51.78#ibcon#read 3, iclass 39, count 0 2006.246.08:13:51.78#ibcon#about to read 4, iclass 39, count 0 2006.246.08:13:51.78#ibcon#read 4, iclass 39, count 0 2006.246.08:13:51.78#ibcon#about to read 5, iclass 39, count 0 2006.246.08:13:51.78#ibcon#read 5, iclass 39, count 0 2006.246.08:13:51.78#ibcon#about to read 6, iclass 39, count 0 2006.246.08:13:51.78#ibcon#read 6, iclass 39, count 0 2006.246.08:13:51.78#ibcon#end of sib2, iclass 39, count 0 2006.246.08:13:51.78#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:13:51.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:13:51.78#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:13:51.78#ibcon#*before write, iclass 39, count 0 2006.246.08:13:51.78#ibcon#enter sib2, iclass 39, count 0 2006.246.08:13:51.78#ibcon#flushed, iclass 39, count 0 2006.246.08:13:51.78#ibcon#about to write, iclass 39, count 0 2006.246.08:13:51.79#ibcon#wrote, iclass 39, count 0 2006.246.08:13:51.79#ibcon#about to read 3, iclass 39, count 0 2006.246.08:13:51.82#ibcon#read 3, iclass 39, count 0 2006.246.08:13:51.82#ibcon#about to read 4, iclass 39, count 0 2006.246.08:13:51.82#ibcon#read 4, iclass 39, count 0 2006.246.08:13:51.82#ibcon#about to read 5, iclass 39, count 0 2006.246.08:13:51.82#ibcon#read 5, iclass 39, count 0 2006.246.08:13:51.82#ibcon#about to read 6, iclass 39, count 0 2006.246.08:13:51.82#ibcon#read 6, iclass 39, count 0 2006.246.08:13:51.82#ibcon#end of sib2, iclass 39, count 0 2006.246.08:13:51.82#ibcon#*after write, iclass 39, count 0 2006.246.08:13:51.82#ibcon#*before return 0, iclass 39, count 0 2006.246.08:13:51.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:51.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:13:51.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:13:51.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:13:51.83$vc4f8/vb=5,3 2006.246.08:13:51.83#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:13:51.83#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:13:51.83#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:51.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:51.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:51.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:51.87#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:13:51.87#ibcon#first serial, iclass 3, count 2 2006.246.08:13:51.87#ibcon#enter sib2, iclass 3, count 2 2006.246.08:13:51.87#ibcon#flushed, iclass 3, count 2 2006.246.08:13:51.87#ibcon#about to write, iclass 3, count 2 2006.246.08:13:51.87#ibcon#wrote, iclass 3, count 2 2006.246.08:13:51.87#ibcon#about to read 3, iclass 3, count 2 2006.246.08:13:51.89#ibcon#read 3, iclass 3, count 2 2006.246.08:13:51.89#ibcon#about to read 4, iclass 3, count 2 2006.246.08:13:51.89#ibcon#read 4, iclass 3, count 2 2006.246.08:13:51.89#ibcon#about to read 5, iclass 3, count 2 2006.246.08:13:51.89#ibcon#read 5, iclass 3, count 2 2006.246.08:13:51.89#ibcon#about to read 6, iclass 3, count 2 2006.246.08:13:51.89#ibcon#read 6, iclass 3, count 2 2006.246.08:13:51.89#ibcon#end of sib2, iclass 3, count 2 2006.246.08:13:51.89#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:13:51.89#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:13:51.89#ibcon#[27=AT05-03\r\n] 2006.246.08:13:51.89#ibcon#*before write, iclass 3, count 2 2006.246.08:13:51.89#ibcon#enter sib2, iclass 3, count 2 2006.246.08:13:51.89#ibcon#flushed, iclass 3, count 2 2006.246.08:13:51.89#ibcon#about to write, iclass 3, count 2 2006.246.08:13:51.90#ibcon#wrote, iclass 3, count 2 2006.246.08:13:51.90#ibcon#about to read 3, iclass 3, count 2 2006.246.08:13:51.92#ibcon#read 3, iclass 3, count 2 2006.246.08:13:51.92#ibcon#about to read 4, iclass 3, count 2 2006.246.08:13:51.92#ibcon#read 4, iclass 3, count 2 2006.246.08:13:51.92#ibcon#about to read 5, iclass 3, count 2 2006.246.08:13:51.92#ibcon#read 5, iclass 3, count 2 2006.246.08:13:51.92#ibcon#about to read 6, iclass 3, count 2 2006.246.08:13:51.92#ibcon#read 6, iclass 3, count 2 2006.246.08:13:51.92#ibcon#end of sib2, iclass 3, count 2 2006.246.08:13:51.92#ibcon#*after write, iclass 3, count 2 2006.246.08:13:51.92#ibcon#*before return 0, iclass 3, count 2 2006.246.08:13:51.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:51.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:13:51.93#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:13:51.93#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:51.93#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:52.04#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:52.04#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:52.04#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:13:52.04#ibcon#first serial, iclass 3, count 0 2006.246.08:13:52.04#ibcon#enter sib2, iclass 3, count 0 2006.246.08:13:52.04#ibcon#flushed, iclass 3, count 0 2006.246.08:13:52.04#ibcon#about to write, iclass 3, count 0 2006.246.08:13:52.04#ibcon#wrote, iclass 3, count 0 2006.246.08:13:52.04#ibcon#about to read 3, iclass 3, count 0 2006.246.08:13:52.06#ibcon#read 3, iclass 3, count 0 2006.246.08:13:52.06#ibcon#about to read 4, iclass 3, count 0 2006.246.08:13:52.06#ibcon#read 4, iclass 3, count 0 2006.246.08:13:52.06#ibcon#about to read 5, iclass 3, count 0 2006.246.08:13:52.06#ibcon#read 5, iclass 3, count 0 2006.246.08:13:52.06#ibcon#about to read 6, iclass 3, count 0 2006.246.08:13:52.06#ibcon#read 6, iclass 3, count 0 2006.246.08:13:52.06#ibcon#end of sib2, iclass 3, count 0 2006.246.08:13:52.06#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:13:52.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:13:52.06#ibcon#[27=USB\r\n] 2006.246.08:13:52.06#ibcon#*before write, iclass 3, count 0 2006.246.08:13:52.06#ibcon#enter sib2, iclass 3, count 0 2006.246.08:13:52.06#ibcon#flushed, iclass 3, count 0 2006.246.08:13:52.06#ibcon#about to write, iclass 3, count 0 2006.246.08:13:52.07#ibcon#wrote, iclass 3, count 0 2006.246.08:13:52.07#ibcon#about to read 3, iclass 3, count 0 2006.246.08:13:52.09#ibcon#read 3, iclass 3, count 0 2006.246.08:13:52.09#ibcon#about to read 4, iclass 3, count 0 2006.246.08:13:52.09#ibcon#read 4, iclass 3, count 0 2006.246.08:13:52.09#ibcon#about to read 5, iclass 3, count 0 2006.246.08:13:52.09#ibcon#read 5, iclass 3, count 0 2006.246.08:13:52.09#ibcon#about to read 6, iclass 3, count 0 2006.246.08:13:52.09#ibcon#read 6, iclass 3, count 0 2006.246.08:13:52.09#ibcon#end of sib2, iclass 3, count 0 2006.246.08:13:52.09#ibcon#*after write, iclass 3, count 0 2006.246.08:13:52.09#ibcon#*before return 0, iclass 3, count 0 2006.246.08:13:52.09#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:52.09#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:13:52.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:13:52.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:13:52.10$vc4f8/vblo=6,752.99 2006.246.08:13:52.10#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:13:52.10#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:13:52.10#ibcon#ireg 17 cls_cnt 0 2006.246.08:13:52.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:52.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:52.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:52.10#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:13:52.10#ibcon#first serial, iclass 5, count 0 2006.246.08:13:52.10#ibcon#enter sib2, iclass 5, count 0 2006.246.08:13:52.10#ibcon#flushed, iclass 5, count 0 2006.246.08:13:52.10#ibcon#about to write, iclass 5, count 0 2006.246.08:13:52.10#ibcon#wrote, iclass 5, count 0 2006.246.08:13:52.10#ibcon#about to read 3, iclass 5, count 0 2006.246.08:13:52.11#ibcon#read 3, iclass 5, count 0 2006.246.08:13:52.11#ibcon#about to read 4, iclass 5, count 0 2006.246.08:13:52.11#ibcon#read 4, iclass 5, count 0 2006.246.08:13:52.11#ibcon#about to read 5, iclass 5, count 0 2006.246.08:13:52.11#ibcon#read 5, iclass 5, count 0 2006.246.08:13:52.11#ibcon#about to read 6, iclass 5, count 0 2006.246.08:13:52.11#ibcon#read 6, iclass 5, count 0 2006.246.08:13:52.11#ibcon#end of sib2, iclass 5, count 0 2006.246.08:13:52.11#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:13:52.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:13:52.11#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:13:52.11#ibcon#*before write, iclass 5, count 0 2006.246.08:13:52.11#ibcon#enter sib2, iclass 5, count 0 2006.246.08:13:52.12#ibcon#flushed, iclass 5, count 0 2006.246.08:13:52.12#ibcon#about to write, iclass 5, count 0 2006.246.08:13:52.12#ibcon#wrote, iclass 5, count 0 2006.246.08:13:52.12#ibcon#about to read 3, iclass 5, count 0 2006.246.08:13:52.15#ibcon#read 3, iclass 5, count 0 2006.246.08:13:52.15#ibcon#about to read 4, iclass 5, count 0 2006.246.08:13:52.15#ibcon#read 4, iclass 5, count 0 2006.246.08:13:52.15#ibcon#about to read 5, iclass 5, count 0 2006.246.08:13:52.15#ibcon#read 5, iclass 5, count 0 2006.246.08:13:52.15#ibcon#about to read 6, iclass 5, count 0 2006.246.08:13:52.15#ibcon#read 6, iclass 5, count 0 2006.246.08:13:52.15#ibcon#end of sib2, iclass 5, count 0 2006.246.08:13:52.15#ibcon#*after write, iclass 5, count 0 2006.246.08:13:52.15#ibcon#*before return 0, iclass 5, count 0 2006.246.08:13:52.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:52.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:13:52.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:13:52.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:13:52.16$vc4f8/vb=6,3 2006.246.08:13:52.16#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.08:13:52.16#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.08:13:52.16#ibcon#ireg 11 cls_cnt 2 2006.246.08:13:52.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:52.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:52.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:52.20#ibcon#enter wrdev, iclass 7, count 2 2006.246.08:13:52.20#ibcon#first serial, iclass 7, count 2 2006.246.08:13:52.20#ibcon#enter sib2, iclass 7, count 2 2006.246.08:13:52.20#ibcon#flushed, iclass 7, count 2 2006.246.08:13:52.20#ibcon#about to write, iclass 7, count 2 2006.246.08:13:52.20#ibcon#wrote, iclass 7, count 2 2006.246.08:13:52.20#ibcon#about to read 3, iclass 7, count 2 2006.246.08:13:52.22#ibcon#read 3, iclass 7, count 2 2006.246.08:13:52.22#ibcon#about to read 4, iclass 7, count 2 2006.246.08:13:52.22#ibcon#read 4, iclass 7, count 2 2006.246.08:13:52.22#ibcon#about to read 5, iclass 7, count 2 2006.246.08:13:52.22#ibcon#read 5, iclass 7, count 2 2006.246.08:13:52.22#ibcon#about to read 6, iclass 7, count 2 2006.246.08:13:52.22#ibcon#read 6, iclass 7, count 2 2006.246.08:13:52.22#ibcon#end of sib2, iclass 7, count 2 2006.246.08:13:52.22#ibcon#*mode == 0, iclass 7, count 2 2006.246.08:13:52.22#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.08:13:52.22#ibcon#[27=AT06-03\r\n] 2006.246.08:13:52.22#ibcon#*before write, iclass 7, count 2 2006.246.08:13:52.22#ibcon#enter sib2, iclass 7, count 2 2006.246.08:13:52.22#ibcon#flushed, iclass 7, count 2 2006.246.08:13:52.22#ibcon#about to write, iclass 7, count 2 2006.246.08:13:52.23#ibcon#wrote, iclass 7, count 2 2006.246.08:13:52.23#ibcon#about to read 3, iclass 7, count 2 2006.246.08:13:52.25#ibcon#read 3, iclass 7, count 2 2006.246.08:13:52.25#ibcon#about to read 4, iclass 7, count 2 2006.246.08:13:52.25#ibcon#read 4, iclass 7, count 2 2006.246.08:13:52.25#ibcon#about to read 5, iclass 7, count 2 2006.246.08:13:52.25#ibcon#read 5, iclass 7, count 2 2006.246.08:13:52.25#ibcon#about to read 6, iclass 7, count 2 2006.246.08:13:52.25#ibcon#read 6, iclass 7, count 2 2006.246.08:13:52.25#ibcon#end of sib2, iclass 7, count 2 2006.246.08:13:52.25#ibcon#*after write, iclass 7, count 2 2006.246.08:13:52.25#ibcon#*before return 0, iclass 7, count 2 2006.246.08:13:52.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:52.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:13:52.25#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.08:13:52.25#ibcon#ireg 7 cls_cnt 0 2006.246.08:13:52.26#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:52.37#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:52.37#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:52.37#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:13:52.37#ibcon#first serial, iclass 7, count 0 2006.246.08:13:52.37#ibcon#enter sib2, iclass 7, count 0 2006.246.08:13:52.37#ibcon#flushed, iclass 7, count 0 2006.246.08:13:52.37#ibcon#about to write, iclass 7, count 0 2006.246.08:13:52.37#ibcon#wrote, iclass 7, count 0 2006.246.08:13:52.37#ibcon#about to read 3, iclass 7, count 0 2006.246.08:13:52.39#ibcon#read 3, iclass 7, count 0 2006.246.08:13:52.39#ibcon#about to read 4, iclass 7, count 0 2006.246.08:13:52.39#ibcon#read 4, iclass 7, count 0 2006.246.08:13:52.39#ibcon#about to read 5, iclass 7, count 0 2006.246.08:13:52.39#ibcon#read 5, iclass 7, count 0 2006.246.08:13:52.39#ibcon#about to read 6, iclass 7, count 0 2006.246.08:13:52.39#ibcon#read 6, iclass 7, count 0 2006.246.08:13:52.39#ibcon#end of sib2, iclass 7, count 0 2006.246.08:13:52.39#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:13:52.39#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:13:52.39#ibcon#[27=USB\r\n] 2006.246.08:13:52.39#ibcon#*before write, iclass 7, count 0 2006.246.08:13:52.39#ibcon#enter sib2, iclass 7, count 0 2006.246.08:13:52.40#ibcon#flushed, iclass 7, count 0 2006.246.08:13:52.40#ibcon#about to write, iclass 7, count 0 2006.246.08:13:52.40#ibcon#wrote, iclass 7, count 0 2006.246.08:13:52.40#ibcon#about to read 3, iclass 7, count 0 2006.246.08:13:52.42#ibcon#read 3, iclass 7, count 0 2006.246.08:13:52.42#ibcon#about to read 4, iclass 7, count 0 2006.246.08:13:52.42#ibcon#read 4, iclass 7, count 0 2006.246.08:13:52.42#ibcon#about to read 5, iclass 7, count 0 2006.246.08:13:52.42#ibcon#read 5, iclass 7, count 0 2006.246.08:13:52.42#ibcon#about to read 6, iclass 7, count 0 2006.246.08:13:52.42#ibcon#read 6, iclass 7, count 0 2006.246.08:13:52.42#ibcon#end of sib2, iclass 7, count 0 2006.246.08:13:52.42#ibcon#*after write, iclass 7, count 0 2006.246.08:13:52.42#ibcon#*before return 0, iclass 7, count 0 2006.246.08:13:52.42#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:52.42#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:13:52.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:13:52.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:13:52.43$vc4f8/vabw=wide 2006.246.08:13:52.43#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.08:13:52.43#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.08:13:52.43#ibcon#ireg 8 cls_cnt 0 2006.246.08:13:52.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:52.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:52.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:52.43#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:13:52.43#ibcon#first serial, iclass 11, count 0 2006.246.08:13:52.43#ibcon#enter sib2, iclass 11, count 0 2006.246.08:13:52.43#ibcon#flushed, iclass 11, count 0 2006.246.08:13:52.43#ibcon#about to write, iclass 11, count 0 2006.246.08:13:52.43#ibcon#wrote, iclass 11, count 0 2006.246.08:13:52.43#ibcon#about to read 3, iclass 11, count 0 2006.246.08:13:52.44#ibcon#read 3, iclass 11, count 0 2006.246.08:13:52.44#ibcon#about to read 4, iclass 11, count 0 2006.246.08:13:52.44#ibcon#read 4, iclass 11, count 0 2006.246.08:13:52.44#ibcon#about to read 5, iclass 11, count 0 2006.246.08:13:52.44#ibcon#read 5, iclass 11, count 0 2006.246.08:13:52.44#ibcon#about to read 6, iclass 11, count 0 2006.246.08:13:52.44#ibcon#read 6, iclass 11, count 0 2006.246.08:13:52.44#ibcon#end of sib2, iclass 11, count 0 2006.246.08:13:52.44#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:13:52.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:13:52.44#ibcon#[25=BW32\r\n] 2006.246.08:13:52.44#ibcon#*before write, iclass 11, count 0 2006.246.08:13:52.44#ibcon#enter sib2, iclass 11, count 0 2006.246.08:13:52.44#ibcon#flushed, iclass 11, count 0 2006.246.08:13:52.44#ibcon#about to write, iclass 11, count 0 2006.246.08:13:52.45#ibcon#wrote, iclass 11, count 0 2006.246.08:13:52.45#ibcon#about to read 3, iclass 11, count 0 2006.246.08:13:52.47#ibcon#read 3, iclass 11, count 0 2006.246.08:13:52.47#ibcon#about to read 4, iclass 11, count 0 2006.246.08:13:52.47#ibcon#read 4, iclass 11, count 0 2006.246.08:13:52.47#ibcon#about to read 5, iclass 11, count 0 2006.246.08:13:52.47#ibcon#read 5, iclass 11, count 0 2006.246.08:13:52.47#ibcon#about to read 6, iclass 11, count 0 2006.246.08:13:52.47#ibcon#read 6, iclass 11, count 0 2006.246.08:13:52.47#ibcon#end of sib2, iclass 11, count 0 2006.246.08:13:52.47#ibcon#*after write, iclass 11, count 0 2006.246.08:13:52.47#ibcon#*before return 0, iclass 11, count 0 2006.246.08:13:52.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:52.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:13:52.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:13:52.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:13:52.48$vc4f8/vbbw=wide 2006.246.08:13:52.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:13:52.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:13:52.48#ibcon#ireg 8 cls_cnt 0 2006.246.08:13:52.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:13:52.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:13:52.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:13:52.53#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:13:52.53#ibcon#first serial, iclass 13, count 0 2006.246.08:13:52.53#ibcon#enter sib2, iclass 13, count 0 2006.246.08:13:52.53#ibcon#flushed, iclass 13, count 0 2006.246.08:13:52.53#ibcon#about to write, iclass 13, count 0 2006.246.08:13:52.53#ibcon#wrote, iclass 13, count 0 2006.246.08:13:52.53#ibcon#about to read 3, iclass 13, count 0 2006.246.08:13:52.55#ibcon#read 3, iclass 13, count 0 2006.246.08:13:52.55#ibcon#about to read 4, iclass 13, count 0 2006.246.08:13:52.55#ibcon#read 4, iclass 13, count 0 2006.246.08:13:52.55#ibcon#about to read 5, iclass 13, count 0 2006.246.08:13:52.55#ibcon#read 5, iclass 13, count 0 2006.246.08:13:52.55#ibcon#about to read 6, iclass 13, count 0 2006.246.08:13:52.55#ibcon#read 6, iclass 13, count 0 2006.246.08:13:52.55#ibcon#end of sib2, iclass 13, count 0 2006.246.08:13:52.55#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:13:52.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:13:52.55#ibcon#[27=BW32\r\n] 2006.246.08:13:52.55#ibcon#*before write, iclass 13, count 0 2006.246.08:13:52.55#ibcon#enter sib2, iclass 13, count 0 2006.246.08:13:52.55#ibcon#flushed, iclass 13, count 0 2006.246.08:13:52.55#ibcon#about to write, iclass 13, count 0 2006.246.08:13:52.56#ibcon#wrote, iclass 13, count 0 2006.246.08:13:52.56#ibcon#about to read 3, iclass 13, count 0 2006.246.08:13:52.58#ibcon#read 3, iclass 13, count 0 2006.246.08:13:52.58#ibcon#about to read 4, iclass 13, count 0 2006.246.08:13:52.58#ibcon#read 4, iclass 13, count 0 2006.246.08:13:52.58#ibcon#about to read 5, iclass 13, count 0 2006.246.08:13:52.58#ibcon#read 5, iclass 13, count 0 2006.246.08:13:52.58#ibcon#about to read 6, iclass 13, count 0 2006.246.08:13:52.58#ibcon#read 6, iclass 13, count 0 2006.246.08:13:52.58#ibcon#end of sib2, iclass 13, count 0 2006.246.08:13:52.58#ibcon#*after write, iclass 13, count 0 2006.246.08:13:52.58#ibcon#*before return 0, iclass 13, count 0 2006.246.08:13:52.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:13:52.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:13:52.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:13:52.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:13:52.59$4f8m12a/ifd4f 2006.246.08:13:52.59$ifd4f/lo= 2006.246.08:13:52.59$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:13:52.59$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:13:52.59$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:13:52.59$ifd4f/patch= 2006.246.08:13:52.59$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:13:52.59$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:13:52.59$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:13:52.59$4f8m12a/"form=m,16.000,1:2 2006.246.08:13:52.59$4f8m12a/"tpicd 2006.246.08:13:52.59$4f8m12a/echo=off 2006.246.08:13:52.59$4f8m12a/xlog=off 2006.246.08:13:52.59:!2006.246.08:14:40 2006.246.08:14:17.14#trakl#Source acquired 2006.246.08:14:19.15#flagr#flagr/antenna,acquired 2006.246.08:14:40.02:preob 2006.246.08:14:41.15/onsource/TRACKING 2006.246.08:14:41.15:!2006.246.08:14:50 2006.246.08:14:50.02:data_valid=on 2006.246.08:14:50.02:midob 2006.246.08:14:51.15/onsource/TRACKING 2006.246.08:14:51.15/wx/26.38,1005.7,75 2006.246.08:14:51.34/cable/+6.4153E-03 2006.246.08:14:52.43/va/01,08,usb,yes,31,33 2006.246.08:14:52.43/va/02,07,usb,yes,31,33 2006.246.08:14:52.43/va/03,06,usb,yes,33,33 2006.246.08:14:52.43/va/04,07,usb,yes,32,35 2006.246.08:14:52.43/va/05,07,usb,yes,34,36 2006.246.08:14:52.43/va/06,07,usb,yes,30,30 2006.246.08:14:52.43/va/07,07,usb,yes,30,30 2006.246.08:14:52.43/va/08,08,usb,yes,26,25 2006.246.08:14:52.66/valo/01,532.99,yes,locked 2006.246.08:14:52.66/valo/02,572.99,yes,locked 2006.246.08:14:52.66/valo/03,672.99,yes,locked 2006.246.08:14:52.66/valo/04,832.99,yes,locked 2006.246.08:14:52.66/valo/05,652.99,yes,locked 2006.246.08:14:52.66/valo/06,772.99,yes,locked 2006.246.08:14:52.66/valo/07,832.99,yes,locked 2006.246.08:14:52.66/valo/08,852.99,yes,locked 2006.246.08:14:53.75/vb/01,04,usb,yes,31,29 2006.246.08:14:53.75/vb/02,04,usb,yes,32,34 2006.246.08:14:53.75/vb/03,04,usb,yes,29,33 2006.246.08:14:53.75/vb/04,04,usb,yes,29,30 2006.246.08:14:53.75/vb/05,03,usb,yes,35,40 2006.246.08:14:53.75/vb/06,03,usb,yes,36,39 2006.246.08:14:53.75/vb/07,04,usb,yes,31,31 2006.246.08:14:53.75/vb/08,03,usb,yes,36,40 2006.246.08:14:53.99/vblo/01,632.99,yes,locked 2006.246.08:14:53.99/vblo/02,640.99,yes,locked 2006.246.08:14:53.99/vblo/03,656.99,yes,locked 2006.246.08:14:53.99/vblo/04,712.99,yes,locked 2006.246.08:14:53.99/vblo/05,744.99,yes,locked 2006.246.08:14:53.99/vblo/06,752.99,yes,locked 2006.246.08:14:53.99/vblo/07,734.99,yes,locked 2006.246.08:14:53.99/vblo/08,744.99,yes,locked 2006.246.08:14:54.15/vabw/8 2006.246.08:14:54.29/vbbw/8 2006.246.08:14:54.38/xfe/off,on,13.0 2006.246.08:14:54.76/ifatt/23,28,28,28 2006.246.08:14:55.07/fmout-gps/S +4.41E-07 2006.246.08:14:55.12:!2006.246.08:15:50 2006.246.08:15:50.00:data_valid=off 2006.246.08:15:50.01:postob 2006.246.08:15:50.13/cable/+6.4134E-03 2006.246.08:15:50.14/wx/26.34,1005.7,75 2006.246.08:15:51.07/fmout-gps/S +4.42E-07 2006.246.08:15:51.08:scan_name=246-0816,k06246,60 2006.246.08:15:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.246.08:15:52.15#flagr#flagr/antenna,new-source 2006.246.08:15:52.15:checkk5 2006.246.08:15:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:15:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:15:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:15:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:15:54.01/chk_obsdata//k5ts1/T2460814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:15:54.37/chk_obsdata//k5ts2/T2460814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:15:54.74/chk_obsdata//k5ts3/T2460814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:15:55.11/chk_obsdata//k5ts4/T2460814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:15:55.83/k5log//k5ts1_log_newline 2006.246.08:15:56.54/k5log//k5ts2_log_newline 2006.246.08:15:57.25/k5log//k5ts3_log_newline 2006.246.08:15:57.94/k5log//k5ts4_log_newline 2006.246.08:15:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:15:57.97:4f8m12a=2 2006.246.08:15:57.97$4f8m12a/echo=on 2006.246.08:15:57.97$4f8m12a/pcalon 2006.246.08:15:57.97$pcalon/"no phase cal control is implemented here 2006.246.08:15:57.97$4f8m12a/"tpicd=stop 2006.246.08:15:57.97$4f8m12a/vc4f8 2006.246.08:15:57.97$vc4f8/valo=1,532.99 2006.246.08:15:57.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:15:57.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:15:57.97#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:57.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:15:57.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:15:57.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:15:57.97#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:15:57.97#ibcon#first serial, iclass 23, count 0 2006.246.08:15:57.97#ibcon#enter sib2, iclass 23, count 0 2006.246.08:15:57.97#ibcon#flushed, iclass 23, count 0 2006.246.08:15:57.97#ibcon#about to write, iclass 23, count 0 2006.246.08:15:57.97#ibcon#wrote, iclass 23, count 0 2006.246.08:15:57.97#ibcon#about to read 3, iclass 23, count 0 2006.246.08:15:58.01#ibcon#read 3, iclass 23, count 0 2006.246.08:15:58.01#ibcon#about to read 4, iclass 23, count 0 2006.246.08:15:58.01#ibcon#read 4, iclass 23, count 0 2006.246.08:15:58.01#ibcon#about to read 5, iclass 23, count 0 2006.246.08:15:58.01#ibcon#read 5, iclass 23, count 0 2006.246.08:15:58.01#ibcon#about to read 6, iclass 23, count 0 2006.246.08:15:58.01#ibcon#read 6, iclass 23, count 0 2006.246.08:15:58.01#ibcon#end of sib2, iclass 23, count 0 2006.246.08:15:58.01#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:15:58.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:15:58.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:15:58.01#ibcon#*before write, iclass 23, count 0 2006.246.08:15:58.01#ibcon#enter sib2, iclass 23, count 0 2006.246.08:15:58.01#ibcon#flushed, iclass 23, count 0 2006.246.08:15:58.01#ibcon#about to write, iclass 23, count 0 2006.246.08:15:58.01#ibcon#wrote, iclass 23, count 0 2006.246.08:15:58.01#ibcon#about to read 3, iclass 23, count 0 2006.246.08:15:58.05#ibcon#read 3, iclass 23, count 0 2006.246.08:15:58.05#ibcon#about to read 4, iclass 23, count 0 2006.246.08:15:58.05#ibcon#read 4, iclass 23, count 0 2006.246.08:15:58.05#ibcon#about to read 5, iclass 23, count 0 2006.246.08:15:58.05#ibcon#read 5, iclass 23, count 0 2006.246.08:15:58.05#ibcon#about to read 6, iclass 23, count 0 2006.246.08:15:58.05#ibcon#read 6, iclass 23, count 0 2006.246.08:15:58.05#ibcon#end of sib2, iclass 23, count 0 2006.246.08:15:58.05#ibcon#*after write, iclass 23, count 0 2006.246.08:15:58.05#ibcon#*before return 0, iclass 23, count 0 2006.246.08:15:58.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:15:58.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:15:58.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:15:58.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:15:58.05$vc4f8/va=1,8 2006.246.08:15:58.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:15:58.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:15:58.05#ibcon#ireg 11 cls_cnt 2 2006.246.08:15:58.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:15:58.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:15:58.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:15:58.05#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:15:58.05#ibcon#first serial, iclass 25, count 2 2006.246.08:15:58.05#ibcon#enter sib2, iclass 25, count 2 2006.246.08:15:58.05#ibcon#flushed, iclass 25, count 2 2006.246.08:15:58.05#ibcon#about to write, iclass 25, count 2 2006.246.08:15:58.05#ibcon#wrote, iclass 25, count 2 2006.246.08:15:58.06#ibcon#about to read 3, iclass 25, count 2 2006.246.08:15:58.07#ibcon#read 3, iclass 25, count 2 2006.246.08:15:58.07#ibcon#about to read 4, iclass 25, count 2 2006.246.08:15:58.07#ibcon#read 4, iclass 25, count 2 2006.246.08:15:58.07#ibcon#about to read 5, iclass 25, count 2 2006.246.08:15:58.07#ibcon#read 5, iclass 25, count 2 2006.246.08:15:58.07#ibcon#about to read 6, iclass 25, count 2 2006.246.08:15:58.07#ibcon#read 6, iclass 25, count 2 2006.246.08:15:58.07#ibcon#end of sib2, iclass 25, count 2 2006.246.08:15:58.07#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:15:58.07#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:15:58.07#ibcon#[25=AT01-08\r\n] 2006.246.08:15:58.07#ibcon#*before write, iclass 25, count 2 2006.246.08:15:58.07#ibcon#enter sib2, iclass 25, count 2 2006.246.08:15:58.07#ibcon#flushed, iclass 25, count 2 2006.246.08:15:58.07#ibcon#about to write, iclass 25, count 2 2006.246.08:15:58.07#ibcon#wrote, iclass 25, count 2 2006.246.08:15:58.07#ibcon#about to read 3, iclass 25, count 2 2006.246.08:15:58.11#ibcon#read 3, iclass 25, count 2 2006.246.08:15:58.11#ibcon#about to read 4, iclass 25, count 2 2006.246.08:15:58.11#ibcon#read 4, iclass 25, count 2 2006.246.08:15:58.11#ibcon#about to read 5, iclass 25, count 2 2006.246.08:15:58.11#ibcon#read 5, iclass 25, count 2 2006.246.08:15:58.11#ibcon#about to read 6, iclass 25, count 2 2006.246.08:15:58.11#ibcon#read 6, iclass 25, count 2 2006.246.08:15:58.11#ibcon#end of sib2, iclass 25, count 2 2006.246.08:15:58.11#ibcon#*after write, iclass 25, count 2 2006.246.08:15:58.11#ibcon#*before return 0, iclass 25, count 2 2006.246.08:15:58.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:15:58.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:15:58.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:15:58.11#ibcon#ireg 7 cls_cnt 0 2006.246.08:15:58.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:15:58.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:15:58.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:15:58.22#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:15:58.22#ibcon#first serial, iclass 25, count 0 2006.246.08:15:58.22#ibcon#enter sib2, iclass 25, count 0 2006.246.08:15:58.22#ibcon#flushed, iclass 25, count 0 2006.246.08:15:58.22#ibcon#about to write, iclass 25, count 0 2006.246.08:15:58.22#ibcon#wrote, iclass 25, count 0 2006.246.08:15:58.22#ibcon#about to read 3, iclass 25, count 0 2006.246.08:15:58.24#ibcon#read 3, iclass 25, count 0 2006.246.08:15:58.24#ibcon#about to read 4, iclass 25, count 0 2006.246.08:15:58.24#ibcon#read 4, iclass 25, count 0 2006.246.08:15:58.24#ibcon#about to read 5, iclass 25, count 0 2006.246.08:15:58.24#ibcon#read 5, iclass 25, count 0 2006.246.08:15:58.24#ibcon#about to read 6, iclass 25, count 0 2006.246.08:15:58.24#ibcon#read 6, iclass 25, count 0 2006.246.08:15:58.24#ibcon#end of sib2, iclass 25, count 0 2006.246.08:15:58.24#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:15:58.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:15:58.24#ibcon#[25=USB\r\n] 2006.246.08:15:58.24#ibcon#*before write, iclass 25, count 0 2006.246.08:15:58.24#ibcon#enter sib2, iclass 25, count 0 2006.246.08:15:58.24#ibcon#flushed, iclass 25, count 0 2006.246.08:15:58.24#ibcon#about to write, iclass 25, count 0 2006.246.08:15:58.24#ibcon#wrote, iclass 25, count 0 2006.246.08:15:58.24#ibcon#about to read 3, iclass 25, count 0 2006.246.08:15:58.27#ibcon#read 3, iclass 25, count 0 2006.246.08:15:58.27#ibcon#about to read 4, iclass 25, count 0 2006.246.08:15:58.27#ibcon#read 4, iclass 25, count 0 2006.246.08:15:58.27#ibcon#about to read 5, iclass 25, count 0 2006.246.08:15:58.27#ibcon#read 5, iclass 25, count 0 2006.246.08:15:58.27#ibcon#about to read 6, iclass 25, count 0 2006.246.08:15:58.27#ibcon#read 6, iclass 25, count 0 2006.246.08:15:58.27#ibcon#end of sib2, iclass 25, count 0 2006.246.08:15:58.27#ibcon#*after write, iclass 25, count 0 2006.246.08:15:58.27#ibcon#*before return 0, iclass 25, count 0 2006.246.08:15:58.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:15:58.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:15:58.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:15:58.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:15:58.27$vc4f8/valo=2,572.99 2006.246.08:15:58.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:15:58.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:15:58.27#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:58.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:15:58.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:15:58.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:15:58.27#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:15:58.27#ibcon#first serial, iclass 27, count 0 2006.246.08:15:58.27#ibcon#enter sib2, iclass 27, count 0 2006.246.08:15:58.27#ibcon#flushed, iclass 27, count 0 2006.246.08:15:58.27#ibcon#about to write, iclass 27, count 0 2006.246.08:15:58.27#ibcon#wrote, iclass 27, count 0 2006.246.08:15:58.28#ibcon#about to read 3, iclass 27, count 0 2006.246.08:15:58.29#ibcon#read 3, iclass 27, count 0 2006.246.08:15:58.29#ibcon#about to read 4, iclass 27, count 0 2006.246.08:15:58.29#ibcon#read 4, iclass 27, count 0 2006.246.08:15:58.29#ibcon#about to read 5, iclass 27, count 0 2006.246.08:15:58.29#ibcon#read 5, iclass 27, count 0 2006.246.08:15:58.29#ibcon#about to read 6, iclass 27, count 0 2006.246.08:15:58.29#ibcon#read 6, iclass 27, count 0 2006.246.08:15:58.29#ibcon#end of sib2, iclass 27, count 0 2006.246.08:15:58.29#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:15:58.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:15:58.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:15:58.29#ibcon#*before write, iclass 27, count 0 2006.246.08:15:58.29#ibcon#enter sib2, iclass 27, count 0 2006.246.08:15:58.29#ibcon#flushed, iclass 27, count 0 2006.246.08:15:58.29#ibcon#about to write, iclass 27, count 0 2006.246.08:15:58.29#ibcon#wrote, iclass 27, count 0 2006.246.08:15:58.29#ibcon#about to read 3, iclass 27, count 0 2006.246.08:15:58.33#ibcon#read 3, iclass 27, count 0 2006.246.08:15:58.33#ibcon#about to read 4, iclass 27, count 0 2006.246.08:15:58.33#ibcon#read 4, iclass 27, count 0 2006.246.08:15:58.33#ibcon#about to read 5, iclass 27, count 0 2006.246.08:15:58.33#ibcon#read 5, iclass 27, count 0 2006.246.08:15:58.33#ibcon#about to read 6, iclass 27, count 0 2006.246.08:15:58.33#ibcon#read 6, iclass 27, count 0 2006.246.08:15:58.33#ibcon#end of sib2, iclass 27, count 0 2006.246.08:15:58.33#ibcon#*after write, iclass 27, count 0 2006.246.08:15:58.33#ibcon#*before return 0, iclass 27, count 0 2006.246.08:15:58.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:15:58.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:15:58.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:15:58.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:15:58.33$vc4f8/va=2,7 2006.246.08:15:58.33#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:15:58.33#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:15:58.33#ibcon#ireg 11 cls_cnt 2 2006.246.08:15:58.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:15:58.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:15:58.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:15:58.40#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:15:58.40#ibcon#first serial, iclass 29, count 2 2006.246.08:15:58.40#ibcon#enter sib2, iclass 29, count 2 2006.246.08:15:58.40#ibcon#flushed, iclass 29, count 2 2006.246.08:15:58.40#ibcon#about to write, iclass 29, count 2 2006.246.08:15:58.40#ibcon#wrote, iclass 29, count 2 2006.246.08:15:58.40#ibcon#about to read 3, iclass 29, count 2 2006.246.08:15:58.42#ibcon#read 3, iclass 29, count 2 2006.246.08:15:58.42#ibcon#about to read 4, iclass 29, count 2 2006.246.08:15:58.42#ibcon#read 4, iclass 29, count 2 2006.246.08:15:58.42#ibcon#about to read 5, iclass 29, count 2 2006.246.08:15:58.42#ibcon#read 5, iclass 29, count 2 2006.246.08:15:58.42#ibcon#about to read 6, iclass 29, count 2 2006.246.08:15:58.42#ibcon#read 6, iclass 29, count 2 2006.246.08:15:58.42#ibcon#end of sib2, iclass 29, count 2 2006.246.08:15:58.42#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:15:58.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:15:58.42#ibcon#[25=AT02-07\r\n] 2006.246.08:15:58.42#ibcon#*before write, iclass 29, count 2 2006.246.08:15:58.42#ibcon#enter sib2, iclass 29, count 2 2006.246.08:15:58.42#ibcon#flushed, iclass 29, count 2 2006.246.08:15:58.42#ibcon#about to write, iclass 29, count 2 2006.246.08:15:58.42#ibcon#wrote, iclass 29, count 2 2006.246.08:15:58.42#ibcon#about to read 3, iclass 29, count 2 2006.246.08:15:58.44#ibcon#read 3, iclass 29, count 2 2006.246.08:15:58.44#ibcon#about to read 4, iclass 29, count 2 2006.246.08:15:58.44#ibcon#read 4, iclass 29, count 2 2006.246.08:15:58.44#ibcon#about to read 5, iclass 29, count 2 2006.246.08:15:58.44#ibcon#read 5, iclass 29, count 2 2006.246.08:15:58.44#ibcon#about to read 6, iclass 29, count 2 2006.246.08:15:58.44#ibcon#read 6, iclass 29, count 2 2006.246.08:15:58.44#ibcon#end of sib2, iclass 29, count 2 2006.246.08:15:58.44#ibcon#*after write, iclass 29, count 2 2006.246.08:15:58.44#ibcon#*before return 0, iclass 29, count 2 2006.246.08:15:58.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:15:58.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:15:58.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:15:58.44#ibcon#ireg 7 cls_cnt 0 2006.246.08:15:58.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:15:58.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:15:58.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:15:58.56#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:15:58.56#ibcon#first serial, iclass 29, count 0 2006.246.08:15:58.56#ibcon#enter sib2, iclass 29, count 0 2006.246.08:15:58.56#ibcon#flushed, iclass 29, count 0 2006.246.08:15:58.56#ibcon#about to write, iclass 29, count 0 2006.246.08:15:58.56#ibcon#wrote, iclass 29, count 0 2006.246.08:15:58.56#ibcon#about to read 3, iclass 29, count 0 2006.246.08:15:58.58#ibcon#read 3, iclass 29, count 0 2006.246.08:15:58.58#ibcon#about to read 4, iclass 29, count 0 2006.246.08:15:58.58#ibcon#read 4, iclass 29, count 0 2006.246.08:15:58.58#ibcon#about to read 5, iclass 29, count 0 2006.246.08:15:58.58#ibcon#read 5, iclass 29, count 0 2006.246.08:15:58.58#ibcon#about to read 6, iclass 29, count 0 2006.246.08:15:58.58#ibcon#read 6, iclass 29, count 0 2006.246.08:15:58.58#ibcon#end of sib2, iclass 29, count 0 2006.246.08:15:58.58#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:15:58.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:15:58.58#ibcon#[25=USB\r\n] 2006.246.08:15:58.58#ibcon#*before write, iclass 29, count 0 2006.246.08:15:58.58#ibcon#enter sib2, iclass 29, count 0 2006.246.08:15:58.58#ibcon#flushed, iclass 29, count 0 2006.246.08:15:58.58#ibcon#about to write, iclass 29, count 0 2006.246.08:15:58.58#ibcon#wrote, iclass 29, count 0 2006.246.08:15:58.58#ibcon#about to read 3, iclass 29, count 0 2006.246.08:15:58.61#ibcon#read 3, iclass 29, count 0 2006.246.08:15:58.61#ibcon#about to read 4, iclass 29, count 0 2006.246.08:15:58.61#ibcon#read 4, iclass 29, count 0 2006.246.08:15:58.61#ibcon#about to read 5, iclass 29, count 0 2006.246.08:15:58.61#ibcon#read 5, iclass 29, count 0 2006.246.08:15:58.61#ibcon#about to read 6, iclass 29, count 0 2006.246.08:15:58.61#ibcon#read 6, iclass 29, count 0 2006.246.08:15:58.61#ibcon#end of sib2, iclass 29, count 0 2006.246.08:15:58.61#ibcon#*after write, iclass 29, count 0 2006.246.08:15:58.61#ibcon#*before return 0, iclass 29, count 0 2006.246.08:15:58.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:15:58.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:15:58.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:15:58.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:15:58.61$vc4f8/valo=3,672.99 2006.246.08:15:58.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:15:58.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:15:58.61#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:58.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:15:58.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:15:58.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:15:58.61#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:15:58.61#ibcon#first serial, iclass 31, count 0 2006.246.08:15:58.62#ibcon#enter sib2, iclass 31, count 0 2006.246.08:15:58.62#ibcon#flushed, iclass 31, count 0 2006.246.08:15:58.62#ibcon#about to write, iclass 31, count 0 2006.246.08:15:58.62#ibcon#wrote, iclass 31, count 0 2006.246.08:15:58.62#ibcon#about to read 3, iclass 31, count 0 2006.246.08:15:58.63#ibcon#read 3, iclass 31, count 0 2006.246.08:15:58.63#ibcon#about to read 4, iclass 31, count 0 2006.246.08:15:58.63#ibcon#read 4, iclass 31, count 0 2006.246.08:15:58.63#ibcon#about to read 5, iclass 31, count 0 2006.246.08:15:58.63#ibcon#read 5, iclass 31, count 0 2006.246.08:15:58.63#ibcon#about to read 6, iclass 31, count 0 2006.246.08:15:58.63#ibcon#read 6, iclass 31, count 0 2006.246.08:15:58.63#ibcon#end of sib2, iclass 31, count 0 2006.246.08:15:58.63#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:15:58.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:15:58.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:15:58.63#ibcon#*before write, iclass 31, count 0 2006.246.08:15:58.63#ibcon#enter sib2, iclass 31, count 0 2006.246.08:15:58.63#ibcon#flushed, iclass 31, count 0 2006.246.08:15:58.63#ibcon#about to write, iclass 31, count 0 2006.246.08:15:58.63#ibcon#wrote, iclass 31, count 0 2006.246.08:15:58.63#ibcon#about to read 3, iclass 31, count 0 2006.246.08:15:58.67#ibcon#read 3, iclass 31, count 0 2006.246.08:15:58.67#ibcon#about to read 4, iclass 31, count 0 2006.246.08:15:58.67#ibcon#read 4, iclass 31, count 0 2006.246.08:15:58.67#ibcon#about to read 5, iclass 31, count 0 2006.246.08:15:58.67#ibcon#read 5, iclass 31, count 0 2006.246.08:15:58.67#ibcon#about to read 6, iclass 31, count 0 2006.246.08:15:58.67#ibcon#read 6, iclass 31, count 0 2006.246.08:15:58.67#ibcon#end of sib2, iclass 31, count 0 2006.246.08:15:58.67#ibcon#*after write, iclass 31, count 0 2006.246.08:15:58.67#ibcon#*before return 0, iclass 31, count 0 2006.246.08:15:58.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:15:58.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:15:58.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:15:58.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:15:58.67$vc4f8/va=3,6 2006.246.08:15:58.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:15:58.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:15:58.67#ibcon#ireg 11 cls_cnt 2 2006.246.08:15:58.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:15:58.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:15:58.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:15:58.74#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:15:58.74#ibcon#first serial, iclass 33, count 2 2006.246.08:15:58.74#ibcon#enter sib2, iclass 33, count 2 2006.246.08:15:58.74#ibcon#flushed, iclass 33, count 2 2006.246.08:15:58.74#ibcon#about to write, iclass 33, count 2 2006.246.08:15:58.74#ibcon#wrote, iclass 33, count 2 2006.246.08:15:58.74#ibcon#about to read 3, iclass 33, count 2 2006.246.08:15:58.76#ibcon#read 3, iclass 33, count 2 2006.246.08:15:58.76#ibcon#about to read 4, iclass 33, count 2 2006.246.08:15:58.76#ibcon#read 4, iclass 33, count 2 2006.246.08:15:58.76#ibcon#about to read 5, iclass 33, count 2 2006.246.08:15:58.76#ibcon#read 5, iclass 33, count 2 2006.246.08:15:58.76#ibcon#about to read 6, iclass 33, count 2 2006.246.08:15:58.76#ibcon#read 6, iclass 33, count 2 2006.246.08:15:58.76#ibcon#end of sib2, iclass 33, count 2 2006.246.08:15:58.76#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:15:58.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:15:58.76#ibcon#[25=AT03-06\r\n] 2006.246.08:15:58.76#ibcon#*before write, iclass 33, count 2 2006.246.08:15:58.76#ibcon#enter sib2, iclass 33, count 2 2006.246.08:15:58.76#ibcon#flushed, iclass 33, count 2 2006.246.08:15:58.76#ibcon#about to write, iclass 33, count 2 2006.246.08:15:58.76#ibcon#wrote, iclass 33, count 2 2006.246.08:15:58.76#ibcon#about to read 3, iclass 33, count 2 2006.246.08:15:58.78#ibcon#read 3, iclass 33, count 2 2006.246.08:15:58.78#ibcon#about to read 4, iclass 33, count 2 2006.246.08:15:58.78#ibcon#read 4, iclass 33, count 2 2006.246.08:15:58.78#ibcon#about to read 5, iclass 33, count 2 2006.246.08:15:58.78#ibcon#read 5, iclass 33, count 2 2006.246.08:15:58.78#ibcon#about to read 6, iclass 33, count 2 2006.246.08:15:58.78#ibcon#read 6, iclass 33, count 2 2006.246.08:15:58.78#ibcon#end of sib2, iclass 33, count 2 2006.246.08:15:58.78#ibcon#*after write, iclass 33, count 2 2006.246.08:15:58.78#ibcon#*before return 0, iclass 33, count 2 2006.246.08:15:58.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:15:58.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:15:58.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:15:58.78#ibcon#ireg 7 cls_cnt 0 2006.246.08:15:58.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:15:58.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:15:58.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:15:58.90#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:15:58.90#ibcon#first serial, iclass 33, count 0 2006.246.08:15:58.90#ibcon#enter sib2, iclass 33, count 0 2006.246.08:15:58.90#ibcon#flushed, iclass 33, count 0 2006.246.08:15:58.90#ibcon#about to write, iclass 33, count 0 2006.246.08:15:58.90#ibcon#wrote, iclass 33, count 0 2006.246.08:15:58.90#ibcon#about to read 3, iclass 33, count 0 2006.246.08:15:58.92#ibcon#read 3, iclass 33, count 0 2006.246.08:15:58.92#ibcon#about to read 4, iclass 33, count 0 2006.246.08:15:58.92#ibcon#read 4, iclass 33, count 0 2006.246.08:15:58.92#ibcon#about to read 5, iclass 33, count 0 2006.246.08:15:58.92#ibcon#read 5, iclass 33, count 0 2006.246.08:15:58.92#ibcon#about to read 6, iclass 33, count 0 2006.246.08:15:58.92#ibcon#read 6, iclass 33, count 0 2006.246.08:15:58.92#ibcon#end of sib2, iclass 33, count 0 2006.246.08:15:58.92#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:15:58.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:15:58.92#ibcon#[25=USB\r\n] 2006.246.08:15:58.92#ibcon#*before write, iclass 33, count 0 2006.246.08:15:58.92#ibcon#enter sib2, iclass 33, count 0 2006.246.08:15:58.92#ibcon#flushed, iclass 33, count 0 2006.246.08:15:58.92#ibcon#about to write, iclass 33, count 0 2006.246.08:15:58.92#ibcon#wrote, iclass 33, count 0 2006.246.08:15:58.92#ibcon#about to read 3, iclass 33, count 0 2006.246.08:15:58.95#ibcon#read 3, iclass 33, count 0 2006.246.08:15:58.95#ibcon#about to read 4, iclass 33, count 0 2006.246.08:15:58.95#ibcon#read 4, iclass 33, count 0 2006.246.08:15:58.95#ibcon#about to read 5, iclass 33, count 0 2006.246.08:15:58.95#ibcon#read 5, iclass 33, count 0 2006.246.08:15:58.95#ibcon#about to read 6, iclass 33, count 0 2006.246.08:15:58.95#ibcon#read 6, iclass 33, count 0 2006.246.08:15:58.95#ibcon#end of sib2, iclass 33, count 0 2006.246.08:15:58.95#ibcon#*after write, iclass 33, count 0 2006.246.08:15:58.95#ibcon#*before return 0, iclass 33, count 0 2006.246.08:15:58.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:15:58.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:15:58.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:15:58.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:15:58.95$vc4f8/valo=4,832.99 2006.246.08:15:58.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:15:58.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:15:58.95#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:58.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:15:58.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:15:58.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:15:58.95#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:15:58.95#ibcon#first serial, iclass 35, count 0 2006.246.08:15:58.95#ibcon#enter sib2, iclass 35, count 0 2006.246.08:15:58.95#ibcon#flushed, iclass 35, count 0 2006.246.08:15:58.95#ibcon#about to write, iclass 35, count 0 2006.246.08:15:58.95#ibcon#wrote, iclass 35, count 0 2006.246.08:15:58.96#ibcon#about to read 3, iclass 35, count 0 2006.246.08:15:58.97#ibcon#read 3, iclass 35, count 0 2006.246.08:15:58.97#ibcon#about to read 4, iclass 35, count 0 2006.246.08:15:58.97#ibcon#read 4, iclass 35, count 0 2006.246.08:15:58.97#ibcon#about to read 5, iclass 35, count 0 2006.246.08:15:58.97#ibcon#read 5, iclass 35, count 0 2006.246.08:15:58.97#ibcon#about to read 6, iclass 35, count 0 2006.246.08:15:58.97#ibcon#read 6, iclass 35, count 0 2006.246.08:15:58.97#ibcon#end of sib2, iclass 35, count 0 2006.246.08:15:58.97#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:15:58.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:15:58.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:15:58.97#ibcon#*before write, iclass 35, count 0 2006.246.08:15:58.97#ibcon#enter sib2, iclass 35, count 0 2006.246.08:15:58.97#ibcon#flushed, iclass 35, count 0 2006.246.08:15:58.97#ibcon#about to write, iclass 35, count 0 2006.246.08:15:58.97#ibcon#wrote, iclass 35, count 0 2006.246.08:15:58.97#ibcon#about to read 3, iclass 35, count 0 2006.246.08:15:59.01#ibcon#read 3, iclass 35, count 0 2006.246.08:15:59.01#ibcon#about to read 4, iclass 35, count 0 2006.246.08:15:59.01#ibcon#read 4, iclass 35, count 0 2006.246.08:15:59.01#ibcon#about to read 5, iclass 35, count 0 2006.246.08:15:59.01#ibcon#read 5, iclass 35, count 0 2006.246.08:15:59.01#ibcon#about to read 6, iclass 35, count 0 2006.246.08:15:59.01#ibcon#read 6, iclass 35, count 0 2006.246.08:15:59.01#ibcon#end of sib2, iclass 35, count 0 2006.246.08:15:59.01#ibcon#*after write, iclass 35, count 0 2006.246.08:15:59.01#ibcon#*before return 0, iclass 35, count 0 2006.246.08:15:59.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:15:59.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:15:59.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:15:59.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:15:59.01$vc4f8/va=4,7 2006.246.08:15:59.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:15:59.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:15:59.01#ibcon#ireg 11 cls_cnt 2 2006.246.08:15:59.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:15:59.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:15:59.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:15:59.07#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:15:59.07#ibcon#first serial, iclass 37, count 2 2006.246.08:15:59.07#ibcon#enter sib2, iclass 37, count 2 2006.246.08:15:59.07#ibcon#flushed, iclass 37, count 2 2006.246.08:15:59.07#ibcon#about to write, iclass 37, count 2 2006.246.08:15:59.07#ibcon#wrote, iclass 37, count 2 2006.246.08:15:59.07#ibcon#about to read 3, iclass 37, count 2 2006.246.08:15:59.09#ibcon#read 3, iclass 37, count 2 2006.246.08:15:59.09#ibcon#about to read 4, iclass 37, count 2 2006.246.08:15:59.09#ibcon#read 4, iclass 37, count 2 2006.246.08:15:59.09#ibcon#about to read 5, iclass 37, count 2 2006.246.08:15:59.09#ibcon#read 5, iclass 37, count 2 2006.246.08:15:59.09#ibcon#about to read 6, iclass 37, count 2 2006.246.08:15:59.09#ibcon#read 6, iclass 37, count 2 2006.246.08:15:59.09#ibcon#end of sib2, iclass 37, count 2 2006.246.08:15:59.09#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:15:59.09#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:15:59.09#ibcon#[25=AT04-07\r\n] 2006.246.08:15:59.09#ibcon#*before write, iclass 37, count 2 2006.246.08:15:59.09#ibcon#enter sib2, iclass 37, count 2 2006.246.08:15:59.09#ibcon#flushed, iclass 37, count 2 2006.246.08:15:59.09#ibcon#about to write, iclass 37, count 2 2006.246.08:15:59.09#ibcon#wrote, iclass 37, count 2 2006.246.08:15:59.09#ibcon#about to read 3, iclass 37, count 2 2006.246.08:15:59.12#ibcon#read 3, iclass 37, count 2 2006.246.08:15:59.12#ibcon#about to read 4, iclass 37, count 2 2006.246.08:15:59.12#ibcon#read 4, iclass 37, count 2 2006.246.08:15:59.12#ibcon#about to read 5, iclass 37, count 2 2006.246.08:15:59.12#ibcon#read 5, iclass 37, count 2 2006.246.08:15:59.12#ibcon#about to read 6, iclass 37, count 2 2006.246.08:15:59.12#ibcon#read 6, iclass 37, count 2 2006.246.08:15:59.12#ibcon#end of sib2, iclass 37, count 2 2006.246.08:15:59.12#ibcon#*after write, iclass 37, count 2 2006.246.08:15:59.12#ibcon#*before return 0, iclass 37, count 2 2006.246.08:15:59.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:15:59.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:15:59.12#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:15:59.12#ibcon#ireg 7 cls_cnt 0 2006.246.08:15:59.12#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:15:59.24#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:15:59.24#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:15:59.24#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:15:59.24#ibcon#first serial, iclass 37, count 0 2006.246.08:15:59.24#ibcon#enter sib2, iclass 37, count 0 2006.246.08:15:59.24#ibcon#flushed, iclass 37, count 0 2006.246.08:15:59.24#ibcon#about to write, iclass 37, count 0 2006.246.08:15:59.24#ibcon#wrote, iclass 37, count 0 2006.246.08:15:59.24#ibcon#about to read 3, iclass 37, count 0 2006.246.08:15:59.26#ibcon#read 3, iclass 37, count 0 2006.246.08:15:59.26#ibcon#about to read 4, iclass 37, count 0 2006.246.08:15:59.26#ibcon#read 4, iclass 37, count 0 2006.246.08:15:59.26#ibcon#about to read 5, iclass 37, count 0 2006.246.08:15:59.26#ibcon#read 5, iclass 37, count 0 2006.246.08:15:59.26#ibcon#about to read 6, iclass 37, count 0 2006.246.08:15:59.26#ibcon#read 6, iclass 37, count 0 2006.246.08:15:59.26#ibcon#end of sib2, iclass 37, count 0 2006.246.08:15:59.26#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:15:59.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:15:59.26#ibcon#[25=USB\r\n] 2006.246.08:15:59.26#ibcon#*before write, iclass 37, count 0 2006.246.08:15:59.26#ibcon#enter sib2, iclass 37, count 0 2006.246.08:15:59.26#ibcon#flushed, iclass 37, count 0 2006.246.08:15:59.26#ibcon#about to write, iclass 37, count 0 2006.246.08:15:59.26#ibcon#wrote, iclass 37, count 0 2006.246.08:15:59.26#ibcon#about to read 3, iclass 37, count 0 2006.246.08:15:59.29#ibcon#read 3, iclass 37, count 0 2006.246.08:15:59.29#ibcon#about to read 4, iclass 37, count 0 2006.246.08:15:59.29#ibcon#read 4, iclass 37, count 0 2006.246.08:15:59.29#ibcon#about to read 5, iclass 37, count 0 2006.246.08:15:59.29#ibcon#read 5, iclass 37, count 0 2006.246.08:15:59.29#ibcon#about to read 6, iclass 37, count 0 2006.246.08:15:59.29#ibcon#read 6, iclass 37, count 0 2006.246.08:15:59.29#ibcon#end of sib2, iclass 37, count 0 2006.246.08:15:59.29#ibcon#*after write, iclass 37, count 0 2006.246.08:15:59.29#ibcon#*before return 0, iclass 37, count 0 2006.246.08:15:59.29#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:15:59.29#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:15:59.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:15:59.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:15:59.29$vc4f8/valo=5,652.99 2006.246.08:15:59.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:15:59.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:15:59.29#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:59.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:15:59.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:15:59.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:15:59.29#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:15:59.29#ibcon#first serial, iclass 39, count 0 2006.246.08:15:59.29#ibcon#enter sib2, iclass 39, count 0 2006.246.08:15:59.29#ibcon#flushed, iclass 39, count 0 2006.246.08:15:59.29#ibcon#about to write, iclass 39, count 0 2006.246.08:15:59.29#ibcon#wrote, iclass 39, count 0 2006.246.08:15:59.30#ibcon#about to read 3, iclass 39, count 0 2006.246.08:15:59.31#ibcon#read 3, iclass 39, count 0 2006.246.08:15:59.31#ibcon#about to read 4, iclass 39, count 0 2006.246.08:15:59.31#ibcon#read 4, iclass 39, count 0 2006.246.08:15:59.31#ibcon#about to read 5, iclass 39, count 0 2006.246.08:15:59.31#ibcon#read 5, iclass 39, count 0 2006.246.08:15:59.31#ibcon#about to read 6, iclass 39, count 0 2006.246.08:15:59.31#ibcon#read 6, iclass 39, count 0 2006.246.08:15:59.31#ibcon#end of sib2, iclass 39, count 0 2006.246.08:15:59.31#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:15:59.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:15:59.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:15:59.31#ibcon#*before write, iclass 39, count 0 2006.246.08:15:59.31#ibcon#enter sib2, iclass 39, count 0 2006.246.08:15:59.31#ibcon#flushed, iclass 39, count 0 2006.246.08:15:59.31#ibcon#about to write, iclass 39, count 0 2006.246.08:15:59.31#ibcon#wrote, iclass 39, count 0 2006.246.08:15:59.31#ibcon#about to read 3, iclass 39, count 0 2006.246.08:15:59.35#ibcon#read 3, iclass 39, count 0 2006.246.08:15:59.35#ibcon#about to read 4, iclass 39, count 0 2006.246.08:15:59.35#ibcon#read 4, iclass 39, count 0 2006.246.08:15:59.35#ibcon#about to read 5, iclass 39, count 0 2006.246.08:15:59.35#ibcon#read 5, iclass 39, count 0 2006.246.08:15:59.35#ibcon#about to read 6, iclass 39, count 0 2006.246.08:15:59.35#ibcon#read 6, iclass 39, count 0 2006.246.08:15:59.35#ibcon#end of sib2, iclass 39, count 0 2006.246.08:15:59.35#ibcon#*after write, iclass 39, count 0 2006.246.08:15:59.35#ibcon#*before return 0, iclass 39, count 0 2006.246.08:15:59.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:15:59.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:15:59.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:15:59.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:15:59.35$vc4f8/va=5,7 2006.246.08:15:59.35#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:15:59.35#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:15:59.35#ibcon#ireg 11 cls_cnt 2 2006.246.08:15:59.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:15:59.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:15:59.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:15:59.41#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:15:59.41#ibcon#first serial, iclass 3, count 2 2006.246.08:15:59.41#ibcon#enter sib2, iclass 3, count 2 2006.246.08:15:59.41#ibcon#flushed, iclass 3, count 2 2006.246.08:15:59.41#ibcon#about to write, iclass 3, count 2 2006.246.08:15:59.41#ibcon#wrote, iclass 3, count 2 2006.246.08:15:59.41#ibcon#about to read 3, iclass 3, count 2 2006.246.08:15:59.43#ibcon#read 3, iclass 3, count 2 2006.246.08:15:59.43#ibcon#about to read 4, iclass 3, count 2 2006.246.08:15:59.43#ibcon#read 4, iclass 3, count 2 2006.246.08:15:59.43#ibcon#about to read 5, iclass 3, count 2 2006.246.08:15:59.43#ibcon#read 5, iclass 3, count 2 2006.246.08:15:59.43#ibcon#about to read 6, iclass 3, count 2 2006.246.08:15:59.43#ibcon#read 6, iclass 3, count 2 2006.246.08:15:59.43#ibcon#end of sib2, iclass 3, count 2 2006.246.08:15:59.43#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:15:59.43#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:15:59.43#ibcon#[25=AT05-07\r\n] 2006.246.08:15:59.43#ibcon#*before write, iclass 3, count 2 2006.246.08:15:59.43#ibcon#enter sib2, iclass 3, count 2 2006.246.08:15:59.43#ibcon#flushed, iclass 3, count 2 2006.246.08:15:59.43#ibcon#about to write, iclass 3, count 2 2006.246.08:15:59.43#ibcon#wrote, iclass 3, count 2 2006.246.08:15:59.43#ibcon#about to read 3, iclass 3, count 2 2006.246.08:15:59.46#ibcon#read 3, iclass 3, count 2 2006.246.08:15:59.46#ibcon#about to read 4, iclass 3, count 2 2006.246.08:15:59.46#ibcon#read 4, iclass 3, count 2 2006.246.08:15:59.46#ibcon#about to read 5, iclass 3, count 2 2006.246.08:15:59.46#ibcon#read 5, iclass 3, count 2 2006.246.08:15:59.46#ibcon#about to read 6, iclass 3, count 2 2006.246.08:15:59.46#ibcon#read 6, iclass 3, count 2 2006.246.08:15:59.46#ibcon#end of sib2, iclass 3, count 2 2006.246.08:15:59.46#ibcon#*after write, iclass 3, count 2 2006.246.08:15:59.46#ibcon#*before return 0, iclass 3, count 2 2006.246.08:15:59.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:15:59.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:15:59.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:15:59.46#ibcon#ireg 7 cls_cnt 0 2006.246.08:15:59.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:15:59.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:15:59.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:15:59.58#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:15:59.58#ibcon#first serial, iclass 3, count 0 2006.246.08:15:59.58#ibcon#enter sib2, iclass 3, count 0 2006.246.08:15:59.58#ibcon#flushed, iclass 3, count 0 2006.246.08:15:59.58#ibcon#about to write, iclass 3, count 0 2006.246.08:15:59.58#ibcon#wrote, iclass 3, count 0 2006.246.08:15:59.58#ibcon#about to read 3, iclass 3, count 0 2006.246.08:15:59.60#ibcon#read 3, iclass 3, count 0 2006.246.08:15:59.60#ibcon#about to read 4, iclass 3, count 0 2006.246.08:15:59.60#ibcon#read 4, iclass 3, count 0 2006.246.08:15:59.60#ibcon#about to read 5, iclass 3, count 0 2006.246.08:15:59.60#ibcon#read 5, iclass 3, count 0 2006.246.08:15:59.60#ibcon#about to read 6, iclass 3, count 0 2006.246.08:15:59.60#ibcon#read 6, iclass 3, count 0 2006.246.08:15:59.60#ibcon#end of sib2, iclass 3, count 0 2006.246.08:15:59.60#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:15:59.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:15:59.60#ibcon#[25=USB\r\n] 2006.246.08:15:59.60#ibcon#*before write, iclass 3, count 0 2006.246.08:15:59.60#ibcon#enter sib2, iclass 3, count 0 2006.246.08:15:59.60#ibcon#flushed, iclass 3, count 0 2006.246.08:15:59.60#ibcon#about to write, iclass 3, count 0 2006.246.08:15:59.60#ibcon#wrote, iclass 3, count 0 2006.246.08:15:59.60#ibcon#about to read 3, iclass 3, count 0 2006.246.08:15:59.63#ibcon#read 3, iclass 3, count 0 2006.246.08:15:59.63#ibcon#about to read 4, iclass 3, count 0 2006.246.08:15:59.63#ibcon#read 4, iclass 3, count 0 2006.246.08:15:59.63#ibcon#about to read 5, iclass 3, count 0 2006.246.08:15:59.63#ibcon#read 5, iclass 3, count 0 2006.246.08:15:59.63#ibcon#about to read 6, iclass 3, count 0 2006.246.08:15:59.63#ibcon#read 6, iclass 3, count 0 2006.246.08:15:59.63#ibcon#end of sib2, iclass 3, count 0 2006.246.08:15:59.63#ibcon#*after write, iclass 3, count 0 2006.246.08:15:59.63#ibcon#*before return 0, iclass 3, count 0 2006.246.08:15:59.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:15:59.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:15:59.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:15:59.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:15:59.63$vc4f8/valo=6,772.99 2006.246.08:15:59.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:15:59.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:15:59.63#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:59.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:15:59.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:15:59.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:15:59.63#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:15:59.63#ibcon#first serial, iclass 5, count 0 2006.246.08:15:59.63#ibcon#enter sib2, iclass 5, count 0 2006.246.08:15:59.63#ibcon#flushed, iclass 5, count 0 2006.246.08:15:59.63#ibcon#about to write, iclass 5, count 0 2006.246.08:15:59.63#ibcon#wrote, iclass 5, count 0 2006.246.08:15:59.64#ibcon#about to read 3, iclass 5, count 0 2006.246.08:15:59.65#ibcon#read 3, iclass 5, count 0 2006.246.08:15:59.65#ibcon#about to read 4, iclass 5, count 0 2006.246.08:15:59.65#ibcon#read 4, iclass 5, count 0 2006.246.08:15:59.65#ibcon#about to read 5, iclass 5, count 0 2006.246.08:15:59.65#ibcon#read 5, iclass 5, count 0 2006.246.08:15:59.65#ibcon#about to read 6, iclass 5, count 0 2006.246.08:15:59.65#ibcon#read 6, iclass 5, count 0 2006.246.08:15:59.65#ibcon#end of sib2, iclass 5, count 0 2006.246.08:15:59.65#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:15:59.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:15:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:15:59.65#ibcon#*before write, iclass 5, count 0 2006.246.08:15:59.65#ibcon#enter sib2, iclass 5, count 0 2006.246.08:15:59.65#ibcon#flushed, iclass 5, count 0 2006.246.08:15:59.65#ibcon#about to write, iclass 5, count 0 2006.246.08:15:59.65#ibcon#wrote, iclass 5, count 0 2006.246.08:15:59.65#ibcon#about to read 3, iclass 5, count 0 2006.246.08:15:59.69#ibcon#read 3, iclass 5, count 0 2006.246.08:15:59.69#ibcon#about to read 4, iclass 5, count 0 2006.246.08:15:59.69#ibcon#read 4, iclass 5, count 0 2006.246.08:15:59.69#ibcon#about to read 5, iclass 5, count 0 2006.246.08:15:59.69#ibcon#read 5, iclass 5, count 0 2006.246.08:15:59.69#ibcon#about to read 6, iclass 5, count 0 2006.246.08:15:59.69#ibcon#read 6, iclass 5, count 0 2006.246.08:15:59.69#ibcon#end of sib2, iclass 5, count 0 2006.246.08:15:59.69#ibcon#*after write, iclass 5, count 0 2006.246.08:15:59.69#ibcon#*before return 0, iclass 5, count 0 2006.246.08:15:59.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:15:59.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:15:59.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:15:59.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:15:59.69$vc4f8/va=6,7 2006.246.08:15:59.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.08:15:59.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.08:15:59.69#ibcon#ireg 11 cls_cnt 2 2006.246.08:15:59.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:15:59.76#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:15:59.76#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:15:59.76#ibcon#enter wrdev, iclass 7, count 2 2006.246.08:15:59.76#ibcon#first serial, iclass 7, count 2 2006.246.08:15:59.76#ibcon#enter sib2, iclass 7, count 2 2006.246.08:15:59.76#ibcon#flushed, iclass 7, count 2 2006.246.08:15:59.76#ibcon#about to write, iclass 7, count 2 2006.246.08:15:59.76#ibcon#wrote, iclass 7, count 2 2006.246.08:15:59.76#ibcon#about to read 3, iclass 7, count 2 2006.246.08:15:59.78#ibcon#read 3, iclass 7, count 2 2006.246.08:15:59.78#ibcon#about to read 4, iclass 7, count 2 2006.246.08:15:59.78#ibcon#read 4, iclass 7, count 2 2006.246.08:15:59.78#ibcon#about to read 5, iclass 7, count 2 2006.246.08:15:59.78#ibcon#read 5, iclass 7, count 2 2006.246.08:15:59.78#ibcon#about to read 6, iclass 7, count 2 2006.246.08:15:59.78#ibcon#read 6, iclass 7, count 2 2006.246.08:15:59.78#ibcon#end of sib2, iclass 7, count 2 2006.246.08:15:59.78#ibcon#*mode == 0, iclass 7, count 2 2006.246.08:15:59.78#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.08:15:59.78#ibcon#[25=AT06-07\r\n] 2006.246.08:15:59.78#ibcon#*before write, iclass 7, count 2 2006.246.08:15:59.78#ibcon#enter sib2, iclass 7, count 2 2006.246.08:15:59.78#ibcon#flushed, iclass 7, count 2 2006.246.08:15:59.78#ibcon#about to write, iclass 7, count 2 2006.246.08:15:59.78#ibcon#wrote, iclass 7, count 2 2006.246.08:15:59.78#ibcon#about to read 3, iclass 7, count 2 2006.246.08:15:59.80#ibcon#read 3, iclass 7, count 2 2006.246.08:15:59.80#ibcon#about to read 4, iclass 7, count 2 2006.246.08:15:59.80#ibcon#read 4, iclass 7, count 2 2006.246.08:15:59.80#ibcon#about to read 5, iclass 7, count 2 2006.246.08:15:59.80#ibcon#read 5, iclass 7, count 2 2006.246.08:15:59.80#ibcon#about to read 6, iclass 7, count 2 2006.246.08:15:59.80#ibcon#read 6, iclass 7, count 2 2006.246.08:15:59.80#ibcon#end of sib2, iclass 7, count 2 2006.246.08:15:59.80#ibcon#*after write, iclass 7, count 2 2006.246.08:15:59.80#ibcon#*before return 0, iclass 7, count 2 2006.246.08:15:59.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:15:59.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:15:59.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.08:15:59.80#ibcon#ireg 7 cls_cnt 0 2006.246.08:15:59.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:15:59.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:15:59.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:15:59.92#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:15:59.92#ibcon#first serial, iclass 7, count 0 2006.246.08:15:59.92#ibcon#enter sib2, iclass 7, count 0 2006.246.08:15:59.92#ibcon#flushed, iclass 7, count 0 2006.246.08:15:59.92#ibcon#about to write, iclass 7, count 0 2006.246.08:15:59.92#ibcon#wrote, iclass 7, count 0 2006.246.08:15:59.92#ibcon#about to read 3, iclass 7, count 0 2006.246.08:15:59.94#ibcon#read 3, iclass 7, count 0 2006.246.08:15:59.94#ibcon#about to read 4, iclass 7, count 0 2006.246.08:15:59.94#ibcon#read 4, iclass 7, count 0 2006.246.08:15:59.94#ibcon#about to read 5, iclass 7, count 0 2006.246.08:15:59.94#ibcon#read 5, iclass 7, count 0 2006.246.08:15:59.94#ibcon#about to read 6, iclass 7, count 0 2006.246.08:15:59.94#ibcon#read 6, iclass 7, count 0 2006.246.08:15:59.94#ibcon#end of sib2, iclass 7, count 0 2006.246.08:15:59.94#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:15:59.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:15:59.94#ibcon#[25=USB\r\n] 2006.246.08:15:59.94#ibcon#*before write, iclass 7, count 0 2006.246.08:15:59.94#ibcon#enter sib2, iclass 7, count 0 2006.246.08:15:59.94#ibcon#flushed, iclass 7, count 0 2006.246.08:15:59.94#ibcon#about to write, iclass 7, count 0 2006.246.08:15:59.94#ibcon#wrote, iclass 7, count 0 2006.246.08:15:59.94#ibcon#about to read 3, iclass 7, count 0 2006.246.08:15:59.97#ibcon#read 3, iclass 7, count 0 2006.246.08:15:59.97#ibcon#about to read 4, iclass 7, count 0 2006.246.08:15:59.97#ibcon#read 4, iclass 7, count 0 2006.246.08:15:59.97#ibcon#about to read 5, iclass 7, count 0 2006.246.08:15:59.97#ibcon#read 5, iclass 7, count 0 2006.246.08:15:59.97#ibcon#about to read 6, iclass 7, count 0 2006.246.08:15:59.97#ibcon#read 6, iclass 7, count 0 2006.246.08:15:59.97#ibcon#end of sib2, iclass 7, count 0 2006.246.08:15:59.97#ibcon#*after write, iclass 7, count 0 2006.246.08:15:59.97#ibcon#*before return 0, iclass 7, count 0 2006.246.08:15:59.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:15:59.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:15:59.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:15:59.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:15:59.97$vc4f8/valo=7,832.99 2006.246.08:15:59.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.08:15:59.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.08:15:59.97#ibcon#ireg 17 cls_cnt 0 2006.246.08:15:59.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:15:59.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:15:59.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:15:59.97#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:15:59.97#ibcon#first serial, iclass 11, count 0 2006.246.08:15:59.97#ibcon#enter sib2, iclass 11, count 0 2006.246.08:15:59.97#ibcon#flushed, iclass 11, count 0 2006.246.08:15:59.97#ibcon#about to write, iclass 11, count 0 2006.246.08:15:59.97#ibcon#wrote, iclass 11, count 0 2006.246.08:15:59.98#ibcon#about to read 3, iclass 11, count 0 2006.246.08:15:59.99#ibcon#read 3, iclass 11, count 0 2006.246.08:15:59.99#ibcon#about to read 4, iclass 11, count 0 2006.246.08:15:59.99#ibcon#read 4, iclass 11, count 0 2006.246.08:15:59.99#ibcon#about to read 5, iclass 11, count 0 2006.246.08:15:59.99#ibcon#read 5, iclass 11, count 0 2006.246.08:15:59.99#ibcon#about to read 6, iclass 11, count 0 2006.246.08:15:59.99#ibcon#read 6, iclass 11, count 0 2006.246.08:15:59.99#ibcon#end of sib2, iclass 11, count 0 2006.246.08:15:59.99#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:15:59.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:15:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:15:59.99#ibcon#*before write, iclass 11, count 0 2006.246.08:15:59.99#ibcon#enter sib2, iclass 11, count 0 2006.246.08:15:59.99#ibcon#flushed, iclass 11, count 0 2006.246.08:15:59.99#ibcon#about to write, iclass 11, count 0 2006.246.08:15:59.99#ibcon#wrote, iclass 11, count 0 2006.246.08:15:59.99#ibcon#about to read 3, iclass 11, count 0 2006.246.08:16:00.03#ibcon#read 3, iclass 11, count 0 2006.246.08:16:00.03#ibcon#about to read 4, iclass 11, count 0 2006.246.08:16:00.03#ibcon#read 4, iclass 11, count 0 2006.246.08:16:00.03#ibcon#about to read 5, iclass 11, count 0 2006.246.08:16:00.03#ibcon#read 5, iclass 11, count 0 2006.246.08:16:00.03#ibcon#about to read 6, iclass 11, count 0 2006.246.08:16:00.03#ibcon#read 6, iclass 11, count 0 2006.246.08:16:00.03#ibcon#end of sib2, iclass 11, count 0 2006.246.08:16:00.03#ibcon#*after write, iclass 11, count 0 2006.246.08:16:00.03#ibcon#*before return 0, iclass 11, count 0 2006.246.08:16:00.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:16:00.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:16:00.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:16:00.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:16:00.03$vc4f8/va=7,7 2006.246.08:16:00.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.08:16:00.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.08:16:00.03#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:00.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:16:00.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:16:00.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:16:00.09#ibcon#enter wrdev, iclass 13, count 2 2006.246.08:16:00.09#ibcon#first serial, iclass 13, count 2 2006.246.08:16:00.09#ibcon#enter sib2, iclass 13, count 2 2006.246.08:16:00.09#ibcon#flushed, iclass 13, count 2 2006.246.08:16:00.09#ibcon#about to write, iclass 13, count 2 2006.246.08:16:00.09#ibcon#wrote, iclass 13, count 2 2006.246.08:16:00.09#ibcon#about to read 3, iclass 13, count 2 2006.246.08:16:00.11#ibcon#read 3, iclass 13, count 2 2006.246.08:16:00.11#ibcon#about to read 4, iclass 13, count 2 2006.246.08:16:00.11#ibcon#read 4, iclass 13, count 2 2006.246.08:16:00.11#ibcon#about to read 5, iclass 13, count 2 2006.246.08:16:00.11#ibcon#read 5, iclass 13, count 2 2006.246.08:16:00.11#ibcon#about to read 6, iclass 13, count 2 2006.246.08:16:00.11#ibcon#read 6, iclass 13, count 2 2006.246.08:16:00.11#ibcon#end of sib2, iclass 13, count 2 2006.246.08:16:00.11#ibcon#*mode == 0, iclass 13, count 2 2006.246.08:16:00.11#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.08:16:00.11#ibcon#[25=AT07-07\r\n] 2006.246.08:16:00.11#ibcon#*before write, iclass 13, count 2 2006.246.08:16:00.11#ibcon#enter sib2, iclass 13, count 2 2006.246.08:16:00.11#ibcon#flushed, iclass 13, count 2 2006.246.08:16:00.11#ibcon#about to write, iclass 13, count 2 2006.246.08:16:00.11#ibcon#wrote, iclass 13, count 2 2006.246.08:16:00.11#ibcon#about to read 3, iclass 13, count 2 2006.246.08:16:00.14#ibcon#read 3, iclass 13, count 2 2006.246.08:16:00.14#ibcon#about to read 4, iclass 13, count 2 2006.246.08:16:00.15#ibcon#read 4, iclass 13, count 2 2006.246.08:16:00.15#ibcon#about to read 5, iclass 13, count 2 2006.246.08:16:00.15#ibcon#read 5, iclass 13, count 2 2006.246.08:16:00.15#ibcon#about to read 6, iclass 13, count 2 2006.246.08:16:00.15#ibcon#read 6, iclass 13, count 2 2006.246.08:16:00.15#ibcon#end of sib2, iclass 13, count 2 2006.246.08:16:00.15#ibcon#*after write, iclass 13, count 2 2006.246.08:16:00.15#ibcon#*before return 0, iclass 13, count 2 2006.246.08:16:00.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:16:00.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:16:00.15#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.08:16:00.15#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:00.15#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:16:00.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:16:00.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:16:00.26#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:16:00.26#ibcon#first serial, iclass 13, count 0 2006.246.08:16:00.26#ibcon#enter sib2, iclass 13, count 0 2006.246.08:16:00.26#ibcon#flushed, iclass 13, count 0 2006.246.08:16:00.26#ibcon#about to write, iclass 13, count 0 2006.246.08:16:00.26#ibcon#wrote, iclass 13, count 0 2006.246.08:16:00.26#ibcon#about to read 3, iclass 13, count 0 2006.246.08:16:00.28#ibcon#read 3, iclass 13, count 0 2006.246.08:16:00.28#ibcon#about to read 4, iclass 13, count 0 2006.246.08:16:00.28#ibcon#read 4, iclass 13, count 0 2006.246.08:16:00.28#ibcon#about to read 5, iclass 13, count 0 2006.246.08:16:00.28#ibcon#read 5, iclass 13, count 0 2006.246.08:16:00.28#ibcon#about to read 6, iclass 13, count 0 2006.246.08:16:00.28#ibcon#read 6, iclass 13, count 0 2006.246.08:16:00.28#ibcon#end of sib2, iclass 13, count 0 2006.246.08:16:00.28#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:16:00.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:16:00.28#ibcon#[25=USB\r\n] 2006.246.08:16:00.28#ibcon#*before write, iclass 13, count 0 2006.246.08:16:00.28#ibcon#enter sib2, iclass 13, count 0 2006.246.08:16:00.28#ibcon#flushed, iclass 13, count 0 2006.246.08:16:00.28#ibcon#about to write, iclass 13, count 0 2006.246.08:16:00.28#ibcon#wrote, iclass 13, count 0 2006.246.08:16:00.28#ibcon#about to read 3, iclass 13, count 0 2006.246.08:16:00.31#ibcon#read 3, iclass 13, count 0 2006.246.08:16:00.31#ibcon#about to read 4, iclass 13, count 0 2006.246.08:16:00.31#ibcon#read 4, iclass 13, count 0 2006.246.08:16:00.31#ibcon#about to read 5, iclass 13, count 0 2006.246.08:16:00.31#ibcon#read 5, iclass 13, count 0 2006.246.08:16:00.31#ibcon#about to read 6, iclass 13, count 0 2006.246.08:16:00.31#ibcon#read 6, iclass 13, count 0 2006.246.08:16:00.31#ibcon#end of sib2, iclass 13, count 0 2006.246.08:16:00.31#ibcon#*after write, iclass 13, count 0 2006.246.08:16:00.31#ibcon#*before return 0, iclass 13, count 0 2006.246.08:16:00.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:16:00.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:16:00.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:16:00.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:16:00.31$vc4f8/valo=8,852.99 2006.246.08:16:00.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.08:16:00.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.08:16:00.31#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:00.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:16:00.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:16:00.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:16:00.31#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:16:00.31#ibcon#first serial, iclass 15, count 0 2006.246.08:16:00.31#ibcon#enter sib2, iclass 15, count 0 2006.246.08:16:00.31#ibcon#flushed, iclass 15, count 0 2006.246.08:16:00.31#ibcon#about to write, iclass 15, count 0 2006.246.08:16:00.31#ibcon#wrote, iclass 15, count 0 2006.246.08:16:00.32#ibcon#about to read 3, iclass 15, count 0 2006.246.08:16:00.33#ibcon#read 3, iclass 15, count 0 2006.246.08:16:00.33#ibcon#about to read 4, iclass 15, count 0 2006.246.08:16:00.33#ibcon#read 4, iclass 15, count 0 2006.246.08:16:00.33#ibcon#about to read 5, iclass 15, count 0 2006.246.08:16:00.33#ibcon#read 5, iclass 15, count 0 2006.246.08:16:00.33#ibcon#about to read 6, iclass 15, count 0 2006.246.08:16:00.33#ibcon#read 6, iclass 15, count 0 2006.246.08:16:00.33#ibcon#end of sib2, iclass 15, count 0 2006.246.08:16:00.33#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:16:00.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:16:00.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:16:00.33#ibcon#*before write, iclass 15, count 0 2006.246.08:16:00.33#ibcon#enter sib2, iclass 15, count 0 2006.246.08:16:00.33#ibcon#flushed, iclass 15, count 0 2006.246.08:16:00.33#ibcon#about to write, iclass 15, count 0 2006.246.08:16:00.33#ibcon#wrote, iclass 15, count 0 2006.246.08:16:00.33#ibcon#about to read 3, iclass 15, count 0 2006.246.08:16:00.37#ibcon#read 3, iclass 15, count 0 2006.246.08:16:00.37#ibcon#about to read 4, iclass 15, count 0 2006.246.08:16:00.37#ibcon#read 4, iclass 15, count 0 2006.246.08:16:00.37#ibcon#about to read 5, iclass 15, count 0 2006.246.08:16:00.37#ibcon#read 5, iclass 15, count 0 2006.246.08:16:00.37#ibcon#about to read 6, iclass 15, count 0 2006.246.08:16:00.37#ibcon#read 6, iclass 15, count 0 2006.246.08:16:00.37#ibcon#end of sib2, iclass 15, count 0 2006.246.08:16:00.37#ibcon#*after write, iclass 15, count 0 2006.246.08:16:00.37#ibcon#*before return 0, iclass 15, count 0 2006.246.08:16:00.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:16:00.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:16:00.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:16:00.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:16:00.37$vc4f8/va=8,8 2006.246.08:16:00.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.08:16:00.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.08:16:00.37#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:00.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:16:00.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:16:00.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:16:00.44#ibcon#enter wrdev, iclass 17, count 2 2006.246.08:16:00.44#ibcon#first serial, iclass 17, count 2 2006.246.08:16:00.44#ibcon#enter sib2, iclass 17, count 2 2006.246.08:16:00.44#ibcon#flushed, iclass 17, count 2 2006.246.08:16:00.44#ibcon#about to write, iclass 17, count 2 2006.246.08:16:00.44#ibcon#wrote, iclass 17, count 2 2006.246.08:16:00.44#ibcon#about to read 3, iclass 17, count 2 2006.246.08:16:00.46#ibcon#read 3, iclass 17, count 2 2006.246.08:16:00.46#ibcon#about to read 4, iclass 17, count 2 2006.246.08:16:00.46#ibcon#read 4, iclass 17, count 2 2006.246.08:16:00.46#ibcon#about to read 5, iclass 17, count 2 2006.246.08:16:00.46#ibcon#read 5, iclass 17, count 2 2006.246.08:16:00.46#ibcon#about to read 6, iclass 17, count 2 2006.246.08:16:00.46#ibcon#read 6, iclass 17, count 2 2006.246.08:16:00.46#ibcon#end of sib2, iclass 17, count 2 2006.246.08:16:00.46#ibcon#*mode == 0, iclass 17, count 2 2006.246.08:16:00.46#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.08:16:00.46#ibcon#[25=AT08-08\r\n] 2006.246.08:16:00.46#ibcon#*before write, iclass 17, count 2 2006.246.08:16:00.46#ibcon#enter sib2, iclass 17, count 2 2006.246.08:16:00.46#ibcon#flushed, iclass 17, count 2 2006.246.08:16:00.46#ibcon#about to write, iclass 17, count 2 2006.246.08:16:00.46#ibcon#wrote, iclass 17, count 2 2006.246.08:16:00.46#ibcon#about to read 3, iclass 17, count 2 2006.246.08:16:00.48#ibcon#read 3, iclass 17, count 2 2006.246.08:16:00.48#ibcon#about to read 4, iclass 17, count 2 2006.246.08:16:00.48#ibcon#read 4, iclass 17, count 2 2006.246.08:16:00.48#ibcon#about to read 5, iclass 17, count 2 2006.246.08:16:00.48#ibcon#read 5, iclass 17, count 2 2006.246.08:16:00.48#ibcon#about to read 6, iclass 17, count 2 2006.246.08:16:00.48#ibcon#read 6, iclass 17, count 2 2006.246.08:16:00.48#ibcon#end of sib2, iclass 17, count 2 2006.246.08:16:00.48#ibcon#*after write, iclass 17, count 2 2006.246.08:16:00.48#ibcon#*before return 0, iclass 17, count 2 2006.246.08:16:00.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:16:00.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:16:00.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.08:16:00.48#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:00.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:16:00.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:16:00.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:16:00.60#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:16:00.60#ibcon#first serial, iclass 17, count 0 2006.246.08:16:00.60#ibcon#enter sib2, iclass 17, count 0 2006.246.08:16:00.60#ibcon#flushed, iclass 17, count 0 2006.246.08:16:00.60#ibcon#about to write, iclass 17, count 0 2006.246.08:16:00.60#ibcon#wrote, iclass 17, count 0 2006.246.08:16:00.60#ibcon#about to read 3, iclass 17, count 0 2006.246.08:16:00.62#ibcon#read 3, iclass 17, count 0 2006.246.08:16:00.62#ibcon#about to read 4, iclass 17, count 0 2006.246.08:16:00.62#ibcon#read 4, iclass 17, count 0 2006.246.08:16:00.62#ibcon#about to read 5, iclass 17, count 0 2006.246.08:16:00.62#ibcon#read 5, iclass 17, count 0 2006.246.08:16:00.62#ibcon#about to read 6, iclass 17, count 0 2006.246.08:16:00.62#ibcon#read 6, iclass 17, count 0 2006.246.08:16:00.62#ibcon#end of sib2, iclass 17, count 0 2006.246.08:16:00.62#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:16:00.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:16:00.62#ibcon#[25=USB\r\n] 2006.246.08:16:00.62#ibcon#*before write, iclass 17, count 0 2006.246.08:16:00.62#ibcon#enter sib2, iclass 17, count 0 2006.246.08:16:00.62#ibcon#flushed, iclass 17, count 0 2006.246.08:16:00.62#ibcon#about to write, iclass 17, count 0 2006.246.08:16:00.62#ibcon#wrote, iclass 17, count 0 2006.246.08:16:00.62#ibcon#about to read 3, iclass 17, count 0 2006.246.08:16:00.65#ibcon#read 3, iclass 17, count 0 2006.246.08:16:00.65#ibcon#about to read 4, iclass 17, count 0 2006.246.08:16:00.65#ibcon#read 4, iclass 17, count 0 2006.246.08:16:00.65#ibcon#about to read 5, iclass 17, count 0 2006.246.08:16:00.65#ibcon#read 5, iclass 17, count 0 2006.246.08:16:00.65#ibcon#about to read 6, iclass 17, count 0 2006.246.08:16:00.65#ibcon#read 6, iclass 17, count 0 2006.246.08:16:00.65#ibcon#end of sib2, iclass 17, count 0 2006.246.08:16:00.65#ibcon#*after write, iclass 17, count 0 2006.246.08:16:00.65#ibcon#*before return 0, iclass 17, count 0 2006.246.08:16:00.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:16:00.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:16:00.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:16:00.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:16:00.65$vc4f8/vblo=1,632.99 2006.246.08:16:00.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.08:16:00.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.08:16:00.65#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:00.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:16:00.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:16:00.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:16:00.65#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:16:00.65#ibcon#first serial, iclass 19, count 0 2006.246.08:16:00.65#ibcon#enter sib2, iclass 19, count 0 2006.246.08:16:00.65#ibcon#flushed, iclass 19, count 0 2006.246.08:16:00.65#ibcon#about to write, iclass 19, count 0 2006.246.08:16:00.65#ibcon#wrote, iclass 19, count 0 2006.246.08:16:00.66#ibcon#about to read 3, iclass 19, count 0 2006.246.08:16:00.67#ibcon#read 3, iclass 19, count 0 2006.246.08:16:00.67#ibcon#about to read 4, iclass 19, count 0 2006.246.08:16:00.67#ibcon#read 4, iclass 19, count 0 2006.246.08:16:00.67#ibcon#about to read 5, iclass 19, count 0 2006.246.08:16:00.67#ibcon#read 5, iclass 19, count 0 2006.246.08:16:00.67#ibcon#about to read 6, iclass 19, count 0 2006.246.08:16:00.67#ibcon#read 6, iclass 19, count 0 2006.246.08:16:00.67#ibcon#end of sib2, iclass 19, count 0 2006.246.08:16:00.67#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:16:00.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:16:00.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:16:00.67#ibcon#*before write, iclass 19, count 0 2006.246.08:16:00.67#ibcon#enter sib2, iclass 19, count 0 2006.246.08:16:00.67#ibcon#flushed, iclass 19, count 0 2006.246.08:16:00.67#ibcon#about to write, iclass 19, count 0 2006.246.08:16:00.67#ibcon#wrote, iclass 19, count 0 2006.246.08:16:00.67#ibcon#about to read 3, iclass 19, count 0 2006.246.08:16:00.71#ibcon#read 3, iclass 19, count 0 2006.246.08:16:00.71#ibcon#about to read 4, iclass 19, count 0 2006.246.08:16:00.71#ibcon#read 4, iclass 19, count 0 2006.246.08:16:00.71#ibcon#about to read 5, iclass 19, count 0 2006.246.08:16:00.71#ibcon#read 5, iclass 19, count 0 2006.246.08:16:00.71#ibcon#about to read 6, iclass 19, count 0 2006.246.08:16:00.71#ibcon#read 6, iclass 19, count 0 2006.246.08:16:00.71#ibcon#end of sib2, iclass 19, count 0 2006.246.08:16:00.71#ibcon#*after write, iclass 19, count 0 2006.246.08:16:00.71#ibcon#*before return 0, iclass 19, count 0 2006.246.08:16:00.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:16:00.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:16:00.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:16:00.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:16:00.71$vc4f8/vb=1,4 2006.246.08:16:00.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.08:16:00.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.08:16:00.71#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:00.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:16:00.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:16:00.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:16:00.71#ibcon#enter wrdev, iclass 21, count 2 2006.246.08:16:00.71#ibcon#first serial, iclass 21, count 2 2006.246.08:16:00.71#ibcon#enter sib2, iclass 21, count 2 2006.246.08:16:00.71#ibcon#flushed, iclass 21, count 2 2006.246.08:16:00.71#ibcon#about to write, iclass 21, count 2 2006.246.08:16:00.72#ibcon#wrote, iclass 21, count 2 2006.246.08:16:00.72#ibcon#about to read 3, iclass 21, count 2 2006.246.08:16:00.73#ibcon#read 3, iclass 21, count 2 2006.246.08:16:00.73#ibcon#about to read 4, iclass 21, count 2 2006.246.08:16:00.73#ibcon#read 4, iclass 21, count 2 2006.246.08:16:00.73#ibcon#about to read 5, iclass 21, count 2 2006.246.08:16:00.73#ibcon#read 5, iclass 21, count 2 2006.246.08:16:00.73#ibcon#about to read 6, iclass 21, count 2 2006.246.08:16:00.73#ibcon#read 6, iclass 21, count 2 2006.246.08:16:00.73#ibcon#end of sib2, iclass 21, count 2 2006.246.08:16:00.73#ibcon#*mode == 0, iclass 21, count 2 2006.246.08:16:00.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.08:16:00.73#ibcon#[27=AT01-04\r\n] 2006.246.08:16:00.73#ibcon#*before write, iclass 21, count 2 2006.246.08:16:00.73#ibcon#enter sib2, iclass 21, count 2 2006.246.08:16:00.73#ibcon#flushed, iclass 21, count 2 2006.246.08:16:00.73#ibcon#about to write, iclass 21, count 2 2006.246.08:16:00.73#ibcon#wrote, iclass 21, count 2 2006.246.08:16:00.73#ibcon#about to read 3, iclass 21, count 2 2006.246.08:16:00.76#ibcon#read 3, iclass 21, count 2 2006.246.08:16:00.76#ibcon#about to read 4, iclass 21, count 2 2006.246.08:16:00.76#ibcon#read 4, iclass 21, count 2 2006.246.08:16:00.76#ibcon#about to read 5, iclass 21, count 2 2006.246.08:16:00.76#ibcon#read 5, iclass 21, count 2 2006.246.08:16:00.76#ibcon#about to read 6, iclass 21, count 2 2006.246.08:16:00.76#ibcon#read 6, iclass 21, count 2 2006.246.08:16:00.76#ibcon#end of sib2, iclass 21, count 2 2006.246.08:16:00.76#ibcon#*after write, iclass 21, count 2 2006.246.08:16:00.76#ibcon#*before return 0, iclass 21, count 2 2006.246.08:16:00.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:16:00.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:16:00.76#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.08:16:00.76#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:00.76#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:16:00.88#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:16:00.88#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:16:00.88#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:16:00.88#ibcon#first serial, iclass 21, count 0 2006.246.08:16:00.88#ibcon#enter sib2, iclass 21, count 0 2006.246.08:16:00.88#ibcon#flushed, iclass 21, count 0 2006.246.08:16:00.88#ibcon#about to write, iclass 21, count 0 2006.246.08:16:00.88#ibcon#wrote, iclass 21, count 0 2006.246.08:16:00.88#ibcon#about to read 3, iclass 21, count 0 2006.246.08:16:00.90#ibcon#read 3, iclass 21, count 0 2006.246.08:16:00.90#ibcon#about to read 4, iclass 21, count 0 2006.246.08:16:00.90#ibcon#read 4, iclass 21, count 0 2006.246.08:16:00.90#ibcon#about to read 5, iclass 21, count 0 2006.246.08:16:00.90#ibcon#read 5, iclass 21, count 0 2006.246.08:16:00.90#ibcon#about to read 6, iclass 21, count 0 2006.246.08:16:00.90#ibcon#read 6, iclass 21, count 0 2006.246.08:16:00.90#ibcon#end of sib2, iclass 21, count 0 2006.246.08:16:00.90#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:16:00.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:16:00.90#ibcon#[27=USB\r\n] 2006.246.08:16:00.90#ibcon#*before write, iclass 21, count 0 2006.246.08:16:00.90#ibcon#enter sib2, iclass 21, count 0 2006.246.08:16:00.90#ibcon#flushed, iclass 21, count 0 2006.246.08:16:00.90#ibcon#about to write, iclass 21, count 0 2006.246.08:16:00.90#ibcon#wrote, iclass 21, count 0 2006.246.08:16:00.90#ibcon#about to read 3, iclass 21, count 0 2006.246.08:16:00.93#ibcon#read 3, iclass 21, count 0 2006.246.08:16:00.93#ibcon#about to read 4, iclass 21, count 0 2006.246.08:16:00.93#ibcon#read 4, iclass 21, count 0 2006.246.08:16:00.93#ibcon#about to read 5, iclass 21, count 0 2006.246.08:16:00.93#ibcon#read 5, iclass 21, count 0 2006.246.08:16:00.93#ibcon#about to read 6, iclass 21, count 0 2006.246.08:16:00.93#ibcon#read 6, iclass 21, count 0 2006.246.08:16:00.93#ibcon#end of sib2, iclass 21, count 0 2006.246.08:16:00.93#ibcon#*after write, iclass 21, count 0 2006.246.08:16:00.93#ibcon#*before return 0, iclass 21, count 0 2006.246.08:16:00.93#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:16:00.93#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:16:00.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:16:00.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:16:00.93$vc4f8/vblo=2,640.99 2006.246.08:16:00.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:16:00.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:16:00.93#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:00.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:16:00.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:16:00.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:16:00.93#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:16:00.93#ibcon#first serial, iclass 23, count 0 2006.246.08:16:00.93#ibcon#enter sib2, iclass 23, count 0 2006.246.08:16:00.93#ibcon#flushed, iclass 23, count 0 2006.246.08:16:00.93#ibcon#about to write, iclass 23, count 0 2006.246.08:16:00.93#ibcon#wrote, iclass 23, count 0 2006.246.08:16:00.93#ibcon#about to read 3, iclass 23, count 0 2006.246.08:16:00.95#ibcon#read 3, iclass 23, count 0 2006.246.08:16:00.95#ibcon#about to read 4, iclass 23, count 0 2006.246.08:16:00.95#ibcon#read 4, iclass 23, count 0 2006.246.08:16:00.95#ibcon#about to read 5, iclass 23, count 0 2006.246.08:16:00.95#ibcon#read 5, iclass 23, count 0 2006.246.08:16:00.95#ibcon#about to read 6, iclass 23, count 0 2006.246.08:16:00.95#ibcon#read 6, iclass 23, count 0 2006.246.08:16:00.95#ibcon#end of sib2, iclass 23, count 0 2006.246.08:16:00.95#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:16:00.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:16:00.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:16:00.95#ibcon#*before write, iclass 23, count 0 2006.246.08:16:00.95#ibcon#enter sib2, iclass 23, count 0 2006.246.08:16:00.95#ibcon#flushed, iclass 23, count 0 2006.246.08:16:00.95#ibcon#about to write, iclass 23, count 0 2006.246.08:16:00.95#ibcon#wrote, iclass 23, count 0 2006.246.08:16:00.95#ibcon#about to read 3, iclass 23, count 0 2006.246.08:16:00.99#ibcon#read 3, iclass 23, count 0 2006.246.08:16:00.99#ibcon#about to read 4, iclass 23, count 0 2006.246.08:16:00.99#ibcon#read 4, iclass 23, count 0 2006.246.08:16:00.99#ibcon#about to read 5, iclass 23, count 0 2006.246.08:16:00.99#ibcon#read 5, iclass 23, count 0 2006.246.08:16:00.99#ibcon#about to read 6, iclass 23, count 0 2006.246.08:16:00.99#ibcon#read 6, iclass 23, count 0 2006.246.08:16:00.99#ibcon#end of sib2, iclass 23, count 0 2006.246.08:16:00.99#ibcon#*after write, iclass 23, count 0 2006.246.08:16:00.99#ibcon#*before return 0, iclass 23, count 0 2006.246.08:16:00.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:16:00.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:16:00.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:16:00.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:16:00.99$vc4f8/vb=2,4 2006.246.08:16:00.99#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:16:00.99#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:16:00.99#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:00.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:16:01.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:16:01.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:16:01.06#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:16:01.06#ibcon#first serial, iclass 25, count 2 2006.246.08:16:01.06#ibcon#enter sib2, iclass 25, count 2 2006.246.08:16:01.06#ibcon#flushed, iclass 25, count 2 2006.246.08:16:01.06#ibcon#about to write, iclass 25, count 2 2006.246.08:16:01.06#ibcon#wrote, iclass 25, count 2 2006.246.08:16:01.06#ibcon#about to read 3, iclass 25, count 2 2006.246.08:16:01.08#ibcon#read 3, iclass 25, count 2 2006.246.08:16:01.08#ibcon#about to read 4, iclass 25, count 2 2006.246.08:16:01.08#ibcon#read 4, iclass 25, count 2 2006.246.08:16:01.08#ibcon#about to read 5, iclass 25, count 2 2006.246.08:16:01.08#ibcon#read 5, iclass 25, count 2 2006.246.08:16:01.08#ibcon#about to read 6, iclass 25, count 2 2006.246.08:16:01.08#ibcon#read 6, iclass 25, count 2 2006.246.08:16:01.08#ibcon#end of sib2, iclass 25, count 2 2006.246.08:16:01.08#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:16:01.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:16:01.08#ibcon#[27=AT02-04\r\n] 2006.246.08:16:01.08#ibcon#*before write, iclass 25, count 2 2006.246.08:16:01.08#ibcon#enter sib2, iclass 25, count 2 2006.246.08:16:01.08#ibcon#flushed, iclass 25, count 2 2006.246.08:16:01.08#ibcon#about to write, iclass 25, count 2 2006.246.08:16:01.08#ibcon#wrote, iclass 25, count 2 2006.246.08:16:01.08#ibcon#about to read 3, iclass 25, count 2 2006.246.08:16:01.10#ibcon#read 3, iclass 25, count 2 2006.246.08:16:01.10#ibcon#about to read 4, iclass 25, count 2 2006.246.08:16:01.10#ibcon#read 4, iclass 25, count 2 2006.246.08:16:01.10#ibcon#about to read 5, iclass 25, count 2 2006.246.08:16:01.10#ibcon#read 5, iclass 25, count 2 2006.246.08:16:01.10#ibcon#about to read 6, iclass 25, count 2 2006.246.08:16:01.10#ibcon#read 6, iclass 25, count 2 2006.246.08:16:01.10#ibcon#end of sib2, iclass 25, count 2 2006.246.08:16:01.10#ibcon#*after write, iclass 25, count 2 2006.246.08:16:01.10#ibcon#*before return 0, iclass 25, count 2 2006.246.08:16:01.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:16:01.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:16:01.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:16:01.10#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:01.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:16:01.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:16:01.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:16:01.22#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:16:01.22#ibcon#first serial, iclass 25, count 0 2006.246.08:16:01.22#ibcon#enter sib2, iclass 25, count 0 2006.246.08:16:01.22#ibcon#flushed, iclass 25, count 0 2006.246.08:16:01.22#ibcon#about to write, iclass 25, count 0 2006.246.08:16:01.22#ibcon#wrote, iclass 25, count 0 2006.246.08:16:01.22#ibcon#about to read 3, iclass 25, count 0 2006.246.08:16:01.26#ibcon#read 3, iclass 25, count 0 2006.246.08:16:01.26#ibcon#about to read 4, iclass 25, count 0 2006.246.08:16:01.26#ibcon#read 4, iclass 25, count 0 2006.246.08:16:01.26#ibcon#about to read 5, iclass 25, count 0 2006.246.08:16:01.26#ibcon#read 5, iclass 25, count 0 2006.246.08:16:01.26#ibcon#about to read 6, iclass 25, count 0 2006.246.08:16:01.26#ibcon#read 6, iclass 25, count 0 2006.246.08:16:01.26#ibcon#end of sib2, iclass 25, count 0 2006.246.08:16:01.26#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:16:01.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:16:01.26#ibcon#[27=USB\r\n] 2006.246.08:16:01.26#ibcon#*before write, iclass 25, count 0 2006.246.08:16:01.26#ibcon#enter sib2, iclass 25, count 0 2006.246.08:16:01.26#ibcon#flushed, iclass 25, count 0 2006.246.08:16:01.26#ibcon#about to write, iclass 25, count 0 2006.246.08:16:01.26#ibcon#wrote, iclass 25, count 0 2006.246.08:16:01.26#ibcon#about to read 3, iclass 25, count 0 2006.246.08:16:01.28#ibcon#read 3, iclass 25, count 0 2006.246.08:16:01.28#ibcon#about to read 4, iclass 25, count 0 2006.246.08:16:01.28#ibcon#read 4, iclass 25, count 0 2006.246.08:16:01.28#ibcon#about to read 5, iclass 25, count 0 2006.246.08:16:01.28#ibcon#read 5, iclass 25, count 0 2006.246.08:16:01.28#ibcon#about to read 6, iclass 25, count 0 2006.246.08:16:01.28#ibcon#read 6, iclass 25, count 0 2006.246.08:16:01.28#ibcon#end of sib2, iclass 25, count 0 2006.246.08:16:01.28#ibcon#*after write, iclass 25, count 0 2006.246.08:16:01.28#ibcon#*before return 0, iclass 25, count 0 2006.246.08:16:01.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:16:01.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:16:01.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:16:01.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:16:01.28$vc4f8/vblo=3,656.99 2006.246.08:16:01.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:16:01.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:16:01.28#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:01.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:16:01.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:16:01.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:16:01.28#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:16:01.28#ibcon#first serial, iclass 27, count 0 2006.246.08:16:01.28#ibcon#enter sib2, iclass 27, count 0 2006.246.08:16:01.28#ibcon#flushed, iclass 27, count 0 2006.246.08:16:01.28#ibcon#about to write, iclass 27, count 0 2006.246.08:16:01.29#ibcon#wrote, iclass 27, count 0 2006.246.08:16:01.29#ibcon#about to read 3, iclass 27, count 0 2006.246.08:16:01.30#ibcon#read 3, iclass 27, count 0 2006.246.08:16:01.30#ibcon#about to read 4, iclass 27, count 0 2006.246.08:16:01.30#ibcon#read 4, iclass 27, count 0 2006.246.08:16:01.30#ibcon#about to read 5, iclass 27, count 0 2006.246.08:16:01.30#ibcon#read 5, iclass 27, count 0 2006.246.08:16:01.30#ibcon#about to read 6, iclass 27, count 0 2006.246.08:16:01.30#ibcon#read 6, iclass 27, count 0 2006.246.08:16:01.30#ibcon#end of sib2, iclass 27, count 0 2006.246.08:16:01.30#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:16:01.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:16:01.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:16:01.30#ibcon#*before write, iclass 27, count 0 2006.246.08:16:01.30#ibcon#enter sib2, iclass 27, count 0 2006.246.08:16:01.30#ibcon#flushed, iclass 27, count 0 2006.246.08:16:01.30#ibcon#about to write, iclass 27, count 0 2006.246.08:16:01.30#ibcon#wrote, iclass 27, count 0 2006.246.08:16:01.30#ibcon#about to read 3, iclass 27, count 0 2006.246.08:16:01.34#ibcon#read 3, iclass 27, count 0 2006.246.08:16:01.34#ibcon#about to read 4, iclass 27, count 0 2006.246.08:16:01.34#ibcon#read 4, iclass 27, count 0 2006.246.08:16:01.34#ibcon#about to read 5, iclass 27, count 0 2006.246.08:16:01.34#ibcon#read 5, iclass 27, count 0 2006.246.08:16:01.34#ibcon#about to read 6, iclass 27, count 0 2006.246.08:16:01.34#ibcon#read 6, iclass 27, count 0 2006.246.08:16:01.34#ibcon#end of sib2, iclass 27, count 0 2006.246.08:16:01.34#ibcon#*after write, iclass 27, count 0 2006.246.08:16:01.34#ibcon#*before return 0, iclass 27, count 0 2006.246.08:16:01.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:16:01.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:16:01.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:16:01.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:16:01.34$vc4f8/vb=3,4 2006.246.08:16:01.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:16:01.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:16:01.34#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:01.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:16:01.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:16:01.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:16:01.40#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:16:01.40#ibcon#first serial, iclass 29, count 2 2006.246.08:16:01.40#ibcon#enter sib2, iclass 29, count 2 2006.246.08:16:01.40#ibcon#flushed, iclass 29, count 2 2006.246.08:16:01.40#ibcon#about to write, iclass 29, count 2 2006.246.08:16:01.40#ibcon#wrote, iclass 29, count 2 2006.246.08:16:01.40#ibcon#about to read 3, iclass 29, count 2 2006.246.08:16:01.42#ibcon#read 3, iclass 29, count 2 2006.246.08:16:01.42#ibcon#about to read 4, iclass 29, count 2 2006.246.08:16:01.42#ibcon#read 4, iclass 29, count 2 2006.246.08:16:01.42#ibcon#about to read 5, iclass 29, count 2 2006.246.08:16:01.42#ibcon#read 5, iclass 29, count 2 2006.246.08:16:01.42#ibcon#about to read 6, iclass 29, count 2 2006.246.08:16:01.42#ibcon#read 6, iclass 29, count 2 2006.246.08:16:01.42#ibcon#end of sib2, iclass 29, count 2 2006.246.08:16:01.42#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:16:01.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:16:01.42#ibcon#[27=AT03-04\r\n] 2006.246.08:16:01.42#ibcon#*before write, iclass 29, count 2 2006.246.08:16:01.42#ibcon#enter sib2, iclass 29, count 2 2006.246.08:16:01.42#ibcon#flushed, iclass 29, count 2 2006.246.08:16:01.42#ibcon#about to write, iclass 29, count 2 2006.246.08:16:01.42#ibcon#wrote, iclass 29, count 2 2006.246.08:16:01.42#ibcon#about to read 3, iclass 29, count 2 2006.246.08:16:01.45#ibcon#read 3, iclass 29, count 2 2006.246.08:16:01.45#ibcon#about to read 4, iclass 29, count 2 2006.246.08:16:01.45#ibcon#read 4, iclass 29, count 2 2006.246.08:16:01.45#ibcon#about to read 5, iclass 29, count 2 2006.246.08:16:01.45#ibcon#read 5, iclass 29, count 2 2006.246.08:16:01.45#ibcon#about to read 6, iclass 29, count 2 2006.246.08:16:01.45#ibcon#read 6, iclass 29, count 2 2006.246.08:16:01.45#ibcon#end of sib2, iclass 29, count 2 2006.246.08:16:01.45#ibcon#*after write, iclass 29, count 2 2006.246.08:16:01.45#ibcon#*before return 0, iclass 29, count 2 2006.246.08:16:01.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:16:01.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:16:01.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:16:01.45#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:01.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:16:01.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:16:01.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:16:01.57#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:16:01.57#ibcon#first serial, iclass 29, count 0 2006.246.08:16:01.57#ibcon#enter sib2, iclass 29, count 0 2006.246.08:16:01.57#ibcon#flushed, iclass 29, count 0 2006.246.08:16:01.57#ibcon#about to write, iclass 29, count 0 2006.246.08:16:01.57#ibcon#wrote, iclass 29, count 0 2006.246.08:16:01.57#ibcon#about to read 3, iclass 29, count 0 2006.246.08:16:01.59#ibcon#read 3, iclass 29, count 0 2006.246.08:16:01.59#ibcon#about to read 4, iclass 29, count 0 2006.246.08:16:01.59#ibcon#read 4, iclass 29, count 0 2006.246.08:16:01.59#ibcon#about to read 5, iclass 29, count 0 2006.246.08:16:01.59#ibcon#read 5, iclass 29, count 0 2006.246.08:16:01.59#ibcon#about to read 6, iclass 29, count 0 2006.246.08:16:01.59#ibcon#read 6, iclass 29, count 0 2006.246.08:16:01.59#ibcon#end of sib2, iclass 29, count 0 2006.246.08:16:01.59#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:16:01.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:16:01.59#ibcon#[27=USB\r\n] 2006.246.08:16:01.59#ibcon#*before write, iclass 29, count 0 2006.246.08:16:01.59#ibcon#enter sib2, iclass 29, count 0 2006.246.08:16:01.59#ibcon#flushed, iclass 29, count 0 2006.246.08:16:01.59#ibcon#about to write, iclass 29, count 0 2006.246.08:16:01.59#ibcon#wrote, iclass 29, count 0 2006.246.08:16:01.59#ibcon#about to read 3, iclass 29, count 0 2006.246.08:16:01.62#ibcon#read 3, iclass 29, count 0 2006.246.08:16:01.62#ibcon#about to read 4, iclass 29, count 0 2006.246.08:16:01.62#ibcon#read 4, iclass 29, count 0 2006.246.08:16:01.62#ibcon#about to read 5, iclass 29, count 0 2006.246.08:16:01.62#ibcon#read 5, iclass 29, count 0 2006.246.08:16:01.62#ibcon#about to read 6, iclass 29, count 0 2006.246.08:16:01.62#ibcon#read 6, iclass 29, count 0 2006.246.08:16:01.62#ibcon#end of sib2, iclass 29, count 0 2006.246.08:16:01.62#ibcon#*after write, iclass 29, count 0 2006.246.08:16:01.62#ibcon#*before return 0, iclass 29, count 0 2006.246.08:16:01.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:16:01.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:16:01.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:16:01.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:16:01.62$vc4f8/vblo=4,712.99 2006.246.08:16:01.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:16:01.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:16:01.62#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:01.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:16:01.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:16:01.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:16:01.62#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:16:01.62#ibcon#first serial, iclass 31, count 0 2006.246.08:16:01.62#ibcon#enter sib2, iclass 31, count 0 2006.246.08:16:01.62#ibcon#flushed, iclass 31, count 0 2006.246.08:16:01.62#ibcon#about to write, iclass 31, count 0 2006.246.08:16:01.62#ibcon#wrote, iclass 31, count 0 2006.246.08:16:01.62#ibcon#about to read 3, iclass 31, count 0 2006.246.08:16:01.64#ibcon#read 3, iclass 31, count 0 2006.246.08:16:01.64#ibcon#about to read 4, iclass 31, count 0 2006.246.08:16:01.64#ibcon#read 4, iclass 31, count 0 2006.246.08:16:01.64#ibcon#about to read 5, iclass 31, count 0 2006.246.08:16:01.64#ibcon#read 5, iclass 31, count 0 2006.246.08:16:01.64#ibcon#about to read 6, iclass 31, count 0 2006.246.08:16:01.64#ibcon#read 6, iclass 31, count 0 2006.246.08:16:01.64#ibcon#end of sib2, iclass 31, count 0 2006.246.08:16:01.64#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:16:01.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:16:01.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:16:01.64#ibcon#*before write, iclass 31, count 0 2006.246.08:16:01.64#ibcon#enter sib2, iclass 31, count 0 2006.246.08:16:01.64#ibcon#flushed, iclass 31, count 0 2006.246.08:16:01.64#ibcon#about to write, iclass 31, count 0 2006.246.08:16:01.64#ibcon#wrote, iclass 31, count 0 2006.246.08:16:01.64#ibcon#about to read 3, iclass 31, count 0 2006.246.08:16:01.68#ibcon#read 3, iclass 31, count 0 2006.246.08:16:01.68#ibcon#about to read 4, iclass 31, count 0 2006.246.08:16:01.68#ibcon#read 4, iclass 31, count 0 2006.246.08:16:01.68#ibcon#about to read 5, iclass 31, count 0 2006.246.08:16:01.68#ibcon#read 5, iclass 31, count 0 2006.246.08:16:01.68#ibcon#about to read 6, iclass 31, count 0 2006.246.08:16:01.68#ibcon#read 6, iclass 31, count 0 2006.246.08:16:01.68#ibcon#end of sib2, iclass 31, count 0 2006.246.08:16:01.68#ibcon#*after write, iclass 31, count 0 2006.246.08:16:01.68#ibcon#*before return 0, iclass 31, count 0 2006.246.08:16:01.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:16:01.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:16:01.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:16:01.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:16:01.68$vc4f8/vb=4,4 2006.246.08:16:01.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:16:01.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:16:01.68#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:01.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:16:01.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:16:01.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:16:01.74#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:16:01.74#ibcon#first serial, iclass 33, count 2 2006.246.08:16:01.74#ibcon#enter sib2, iclass 33, count 2 2006.246.08:16:01.74#ibcon#flushed, iclass 33, count 2 2006.246.08:16:01.74#ibcon#about to write, iclass 33, count 2 2006.246.08:16:01.74#ibcon#wrote, iclass 33, count 2 2006.246.08:16:01.74#ibcon#about to read 3, iclass 33, count 2 2006.246.08:16:01.76#ibcon#read 3, iclass 33, count 2 2006.246.08:16:01.76#ibcon#about to read 4, iclass 33, count 2 2006.246.08:16:01.76#ibcon#read 4, iclass 33, count 2 2006.246.08:16:01.76#ibcon#about to read 5, iclass 33, count 2 2006.246.08:16:01.76#ibcon#read 5, iclass 33, count 2 2006.246.08:16:01.76#ibcon#about to read 6, iclass 33, count 2 2006.246.08:16:01.76#ibcon#read 6, iclass 33, count 2 2006.246.08:16:01.76#ibcon#end of sib2, iclass 33, count 2 2006.246.08:16:01.76#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:16:01.76#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:16:01.76#ibcon#[27=AT04-04\r\n] 2006.246.08:16:01.76#ibcon#*before write, iclass 33, count 2 2006.246.08:16:01.76#ibcon#enter sib2, iclass 33, count 2 2006.246.08:16:01.76#ibcon#flushed, iclass 33, count 2 2006.246.08:16:01.76#ibcon#about to write, iclass 33, count 2 2006.246.08:16:01.76#ibcon#wrote, iclass 33, count 2 2006.246.08:16:01.76#ibcon#about to read 3, iclass 33, count 2 2006.246.08:16:01.79#ibcon#read 3, iclass 33, count 2 2006.246.08:16:01.79#ibcon#about to read 4, iclass 33, count 2 2006.246.08:16:01.79#ibcon#read 4, iclass 33, count 2 2006.246.08:16:01.79#ibcon#about to read 5, iclass 33, count 2 2006.246.08:16:01.79#ibcon#read 5, iclass 33, count 2 2006.246.08:16:01.79#ibcon#about to read 6, iclass 33, count 2 2006.246.08:16:01.79#ibcon#read 6, iclass 33, count 2 2006.246.08:16:01.79#ibcon#end of sib2, iclass 33, count 2 2006.246.08:16:01.79#ibcon#*after write, iclass 33, count 2 2006.246.08:16:01.79#ibcon#*before return 0, iclass 33, count 2 2006.246.08:16:01.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:16:01.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:16:01.79#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:16:01.79#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:01.79#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:16:01.91#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:16:01.91#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:16:01.91#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:16:01.91#ibcon#first serial, iclass 33, count 0 2006.246.08:16:01.91#ibcon#enter sib2, iclass 33, count 0 2006.246.08:16:01.91#ibcon#flushed, iclass 33, count 0 2006.246.08:16:01.91#ibcon#about to write, iclass 33, count 0 2006.246.08:16:01.91#ibcon#wrote, iclass 33, count 0 2006.246.08:16:01.91#ibcon#about to read 3, iclass 33, count 0 2006.246.08:16:01.93#ibcon#read 3, iclass 33, count 0 2006.246.08:16:01.93#ibcon#about to read 4, iclass 33, count 0 2006.246.08:16:01.93#ibcon#read 4, iclass 33, count 0 2006.246.08:16:01.93#ibcon#about to read 5, iclass 33, count 0 2006.246.08:16:01.93#ibcon#read 5, iclass 33, count 0 2006.246.08:16:01.93#ibcon#about to read 6, iclass 33, count 0 2006.246.08:16:01.93#ibcon#read 6, iclass 33, count 0 2006.246.08:16:01.93#ibcon#end of sib2, iclass 33, count 0 2006.246.08:16:01.93#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:16:01.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:16:01.93#ibcon#[27=USB\r\n] 2006.246.08:16:01.93#ibcon#*before write, iclass 33, count 0 2006.246.08:16:01.93#ibcon#enter sib2, iclass 33, count 0 2006.246.08:16:01.93#ibcon#flushed, iclass 33, count 0 2006.246.08:16:01.93#ibcon#about to write, iclass 33, count 0 2006.246.08:16:01.93#ibcon#wrote, iclass 33, count 0 2006.246.08:16:01.93#ibcon#about to read 3, iclass 33, count 0 2006.246.08:16:01.96#ibcon#read 3, iclass 33, count 0 2006.246.08:16:01.96#ibcon#about to read 4, iclass 33, count 0 2006.246.08:16:01.96#ibcon#read 4, iclass 33, count 0 2006.246.08:16:01.96#ibcon#about to read 5, iclass 33, count 0 2006.246.08:16:01.96#ibcon#read 5, iclass 33, count 0 2006.246.08:16:01.96#ibcon#about to read 6, iclass 33, count 0 2006.246.08:16:01.96#ibcon#read 6, iclass 33, count 0 2006.246.08:16:01.96#ibcon#end of sib2, iclass 33, count 0 2006.246.08:16:01.96#ibcon#*after write, iclass 33, count 0 2006.246.08:16:01.96#ibcon#*before return 0, iclass 33, count 0 2006.246.08:16:01.96#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:16:01.96#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:16:01.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:16:01.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:16:01.96$vc4f8/vblo=5,744.99 2006.246.08:16:01.96#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:16:01.96#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:16:01.96#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:01.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:16:01.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:16:01.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:16:01.96#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:16:01.96#ibcon#first serial, iclass 35, count 0 2006.246.08:16:01.96#ibcon#enter sib2, iclass 35, count 0 2006.246.08:16:01.96#ibcon#flushed, iclass 35, count 0 2006.246.08:16:01.96#ibcon#about to write, iclass 35, count 0 2006.246.08:16:01.96#ibcon#wrote, iclass 35, count 0 2006.246.08:16:01.96#ibcon#about to read 3, iclass 35, count 0 2006.246.08:16:01.98#ibcon#read 3, iclass 35, count 0 2006.246.08:16:01.98#ibcon#about to read 4, iclass 35, count 0 2006.246.08:16:01.98#ibcon#read 4, iclass 35, count 0 2006.246.08:16:01.98#ibcon#about to read 5, iclass 35, count 0 2006.246.08:16:01.98#ibcon#read 5, iclass 35, count 0 2006.246.08:16:01.98#ibcon#about to read 6, iclass 35, count 0 2006.246.08:16:01.98#ibcon#read 6, iclass 35, count 0 2006.246.08:16:01.98#ibcon#end of sib2, iclass 35, count 0 2006.246.08:16:01.98#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:16:01.98#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:16:01.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:16:01.98#ibcon#*before write, iclass 35, count 0 2006.246.08:16:01.98#ibcon#enter sib2, iclass 35, count 0 2006.246.08:16:01.98#ibcon#flushed, iclass 35, count 0 2006.246.08:16:01.98#ibcon#about to write, iclass 35, count 0 2006.246.08:16:01.98#ibcon#wrote, iclass 35, count 0 2006.246.08:16:01.98#ibcon#about to read 3, iclass 35, count 0 2006.246.08:16:02.02#ibcon#read 3, iclass 35, count 0 2006.246.08:16:02.02#ibcon#about to read 4, iclass 35, count 0 2006.246.08:16:02.02#ibcon#read 4, iclass 35, count 0 2006.246.08:16:02.02#ibcon#about to read 5, iclass 35, count 0 2006.246.08:16:02.02#ibcon#read 5, iclass 35, count 0 2006.246.08:16:02.02#ibcon#about to read 6, iclass 35, count 0 2006.246.08:16:02.02#ibcon#read 6, iclass 35, count 0 2006.246.08:16:02.02#ibcon#end of sib2, iclass 35, count 0 2006.246.08:16:02.02#ibcon#*after write, iclass 35, count 0 2006.246.08:16:02.02#ibcon#*before return 0, iclass 35, count 0 2006.246.08:16:02.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:16:02.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:16:02.02#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:16:02.02#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:16:02.02$vc4f8/vb=5,3 2006.246.08:16:02.02#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:16:02.02#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:16:02.02#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:02.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:16:02.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:16:02.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:16:02.09#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:16:02.09#ibcon#first serial, iclass 37, count 2 2006.246.08:16:02.09#ibcon#enter sib2, iclass 37, count 2 2006.246.08:16:02.09#ibcon#flushed, iclass 37, count 2 2006.246.08:16:02.09#ibcon#about to write, iclass 37, count 2 2006.246.08:16:02.09#ibcon#wrote, iclass 37, count 2 2006.246.08:16:02.09#ibcon#about to read 3, iclass 37, count 2 2006.246.08:16:02.10#ibcon#read 3, iclass 37, count 2 2006.246.08:16:02.10#ibcon#about to read 4, iclass 37, count 2 2006.246.08:16:02.10#ibcon#read 4, iclass 37, count 2 2006.246.08:16:02.10#ibcon#about to read 5, iclass 37, count 2 2006.246.08:16:02.10#ibcon#read 5, iclass 37, count 2 2006.246.08:16:02.10#ibcon#about to read 6, iclass 37, count 2 2006.246.08:16:02.10#ibcon#read 6, iclass 37, count 2 2006.246.08:16:02.10#ibcon#end of sib2, iclass 37, count 2 2006.246.08:16:02.10#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:16:02.10#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:16:02.10#ibcon#[27=AT05-03\r\n] 2006.246.08:16:02.10#ibcon#*before write, iclass 37, count 2 2006.246.08:16:02.10#ibcon#enter sib2, iclass 37, count 2 2006.246.08:16:02.10#ibcon#flushed, iclass 37, count 2 2006.246.08:16:02.10#ibcon#about to write, iclass 37, count 2 2006.246.08:16:02.10#ibcon#wrote, iclass 37, count 2 2006.246.08:16:02.10#ibcon#about to read 3, iclass 37, count 2 2006.246.08:16:02.13#ibcon#read 3, iclass 37, count 2 2006.246.08:16:02.13#ibcon#about to read 4, iclass 37, count 2 2006.246.08:16:02.13#ibcon#read 4, iclass 37, count 2 2006.246.08:16:02.13#ibcon#about to read 5, iclass 37, count 2 2006.246.08:16:02.13#ibcon#read 5, iclass 37, count 2 2006.246.08:16:02.13#ibcon#about to read 6, iclass 37, count 2 2006.246.08:16:02.13#ibcon#read 6, iclass 37, count 2 2006.246.08:16:02.13#ibcon#end of sib2, iclass 37, count 2 2006.246.08:16:02.13#ibcon#*after write, iclass 37, count 2 2006.246.08:16:02.14#ibcon#*before return 0, iclass 37, count 2 2006.246.08:16:02.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:16:02.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:16:02.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:16:02.14#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:02.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:16:02.25#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:16:02.25#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:16:02.25#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:16:02.25#ibcon#first serial, iclass 37, count 0 2006.246.08:16:02.25#ibcon#enter sib2, iclass 37, count 0 2006.246.08:16:02.25#ibcon#flushed, iclass 37, count 0 2006.246.08:16:02.25#ibcon#about to write, iclass 37, count 0 2006.246.08:16:02.25#ibcon#wrote, iclass 37, count 0 2006.246.08:16:02.25#ibcon#about to read 3, iclass 37, count 0 2006.246.08:16:02.27#ibcon#read 3, iclass 37, count 0 2006.246.08:16:02.27#ibcon#about to read 4, iclass 37, count 0 2006.246.08:16:02.27#ibcon#read 4, iclass 37, count 0 2006.246.08:16:02.27#ibcon#about to read 5, iclass 37, count 0 2006.246.08:16:02.27#ibcon#read 5, iclass 37, count 0 2006.246.08:16:02.27#ibcon#about to read 6, iclass 37, count 0 2006.246.08:16:02.27#ibcon#read 6, iclass 37, count 0 2006.246.08:16:02.27#ibcon#end of sib2, iclass 37, count 0 2006.246.08:16:02.27#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:16:02.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:16:02.27#ibcon#[27=USB\r\n] 2006.246.08:16:02.27#ibcon#*before write, iclass 37, count 0 2006.246.08:16:02.27#ibcon#enter sib2, iclass 37, count 0 2006.246.08:16:02.27#ibcon#flushed, iclass 37, count 0 2006.246.08:16:02.27#ibcon#about to write, iclass 37, count 0 2006.246.08:16:02.27#ibcon#wrote, iclass 37, count 0 2006.246.08:16:02.27#ibcon#about to read 3, iclass 37, count 0 2006.246.08:16:02.30#ibcon#read 3, iclass 37, count 0 2006.246.08:16:02.30#ibcon#about to read 4, iclass 37, count 0 2006.246.08:16:02.30#ibcon#read 4, iclass 37, count 0 2006.246.08:16:02.30#ibcon#about to read 5, iclass 37, count 0 2006.246.08:16:02.30#ibcon#read 5, iclass 37, count 0 2006.246.08:16:02.30#ibcon#about to read 6, iclass 37, count 0 2006.246.08:16:02.30#ibcon#read 6, iclass 37, count 0 2006.246.08:16:02.30#ibcon#end of sib2, iclass 37, count 0 2006.246.08:16:02.30#ibcon#*after write, iclass 37, count 0 2006.246.08:16:02.30#ibcon#*before return 0, iclass 37, count 0 2006.246.08:16:02.30#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:16:02.30#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:16:02.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:16:02.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:16:02.30$vc4f8/vblo=6,752.99 2006.246.08:16:02.30#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:16:02.30#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:16:02.30#ibcon#ireg 17 cls_cnt 0 2006.246.08:16:02.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:16:02.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:16:02.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:16:02.30#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:16:02.30#ibcon#first serial, iclass 39, count 0 2006.246.08:16:02.30#ibcon#enter sib2, iclass 39, count 0 2006.246.08:16:02.30#ibcon#flushed, iclass 39, count 0 2006.246.08:16:02.30#ibcon#about to write, iclass 39, count 0 2006.246.08:16:02.30#ibcon#wrote, iclass 39, count 0 2006.246.08:16:02.30#ibcon#about to read 3, iclass 39, count 0 2006.246.08:16:02.32#ibcon#read 3, iclass 39, count 0 2006.246.08:16:02.32#ibcon#about to read 4, iclass 39, count 0 2006.246.08:16:02.32#ibcon#read 4, iclass 39, count 0 2006.246.08:16:02.32#ibcon#about to read 5, iclass 39, count 0 2006.246.08:16:02.32#ibcon#read 5, iclass 39, count 0 2006.246.08:16:02.32#ibcon#about to read 6, iclass 39, count 0 2006.246.08:16:02.32#ibcon#read 6, iclass 39, count 0 2006.246.08:16:02.32#ibcon#end of sib2, iclass 39, count 0 2006.246.08:16:02.32#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:16:02.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:16:02.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:16:02.32#ibcon#*before write, iclass 39, count 0 2006.246.08:16:02.32#ibcon#enter sib2, iclass 39, count 0 2006.246.08:16:02.32#ibcon#flushed, iclass 39, count 0 2006.246.08:16:02.32#ibcon#about to write, iclass 39, count 0 2006.246.08:16:02.32#ibcon#wrote, iclass 39, count 0 2006.246.08:16:02.32#ibcon#about to read 3, iclass 39, count 0 2006.246.08:16:02.36#ibcon#read 3, iclass 39, count 0 2006.246.08:16:02.36#ibcon#about to read 4, iclass 39, count 0 2006.246.08:16:02.36#ibcon#read 4, iclass 39, count 0 2006.246.08:16:02.36#ibcon#about to read 5, iclass 39, count 0 2006.246.08:16:02.36#ibcon#read 5, iclass 39, count 0 2006.246.08:16:02.36#ibcon#about to read 6, iclass 39, count 0 2006.246.08:16:02.36#ibcon#read 6, iclass 39, count 0 2006.246.08:16:02.36#ibcon#end of sib2, iclass 39, count 0 2006.246.08:16:02.36#ibcon#*after write, iclass 39, count 0 2006.246.08:16:02.36#ibcon#*before return 0, iclass 39, count 0 2006.246.08:16:02.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:16:02.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:16:02.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:16:02.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:16:02.36$vc4f8/vb=6,3 2006.246.08:16:02.36#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:16:02.36#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:16:02.36#ibcon#ireg 11 cls_cnt 2 2006.246.08:16:02.36#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:16:02.42#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:16:02.42#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:16:02.42#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:16:02.42#ibcon#first serial, iclass 3, count 2 2006.246.08:16:02.42#ibcon#enter sib2, iclass 3, count 2 2006.246.08:16:02.42#ibcon#flushed, iclass 3, count 2 2006.246.08:16:02.42#ibcon#about to write, iclass 3, count 2 2006.246.08:16:02.42#ibcon#wrote, iclass 3, count 2 2006.246.08:16:02.42#ibcon#about to read 3, iclass 3, count 2 2006.246.08:16:02.44#ibcon#read 3, iclass 3, count 2 2006.246.08:16:02.44#ibcon#about to read 4, iclass 3, count 2 2006.246.08:16:02.44#ibcon#read 4, iclass 3, count 2 2006.246.08:16:02.44#ibcon#about to read 5, iclass 3, count 2 2006.246.08:16:02.44#ibcon#read 5, iclass 3, count 2 2006.246.08:16:02.44#ibcon#about to read 6, iclass 3, count 2 2006.246.08:16:02.44#ibcon#read 6, iclass 3, count 2 2006.246.08:16:02.44#ibcon#end of sib2, iclass 3, count 2 2006.246.08:16:02.44#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:16:02.44#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:16:02.44#ibcon#[27=AT06-03\r\n] 2006.246.08:16:02.44#ibcon#*before write, iclass 3, count 2 2006.246.08:16:02.44#ibcon#enter sib2, iclass 3, count 2 2006.246.08:16:02.44#ibcon#flushed, iclass 3, count 2 2006.246.08:16:02.44#ibcon#about to write, iclass 3, count 2 2006.246.08:16:02.44#ibcon#wrote, iclass 3, count 2 2006.246.08:16:02.44#ibcon#about to read 3, iclass 3, count 2 2006.246.08:16:02.47#ibcon#read 3, iclass 3, count 2 2006.246.08:16:02.47#ibcon#about to read 4, iclass 3, count 2 2006.246.08:16:02.47#ibcon#read 4, iclass 3, count 2 2006.246.08:16:02.47#ibcon#about to read 5, iclass 3, count 2 2006.246.08:16:02.47#ibcon#read 5, iclass 3, count 2 2006.246.08:16:02.47#ibcon#about to read 6, iclass 3, count 2 2006.246.08:16:02.47#ibcon#read 6, iclass 3, count 2 2006.246.08:16:02.47#ibcon#end of sib2, iclass 3, count 2 2006.246.08:16:02.47#ibcon#*after write, iclass 3, count 2 2006.246.08:16:02.47#ibcon#*before return 0, iclass 3, count 2 2006.246.08:16:02.47#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:16:02.47#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:16:02.47#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:16:02.47#ibcon#ireg 7 cls_cnt 0 2006.246.08:16:02.47#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:16:02.59#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:16:02.59#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:16:02.59#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:16:02.59#ibcon#first serial, iclass 3, count 0 2006.246.08:16:02.59#ibcon#enter sib2, iclass 3, count 0 2006.246.08:16:02.59#ibcon#flushed, iclass 3, count 0 2006.246.08:16:02.59#ibcon#about to write, iclass 3, count 0 2006.246.08:16:02.59#ibcon#wrote, iclass 3, count 0 2006.246.08:16:02.59#ibcon#about to read 3, iclass 3, count 0 2006.246.08:16:02.61#ibcon#read 3, iclass 3, count 0 2006.246.08:16:02.61#ibcon#about to read 4, iclass 3, count 0 2006.246.08:16:02.61#ibcon#read 4, iclass 3, count 0 2006.246.08:16:02.61#ibcon#about to read 5, iclass 3, count 0 2006.246.08:16:02.61#ibcon#read 5, iclass 3, count 0 2006.246.08:16:02.61#ibcon#about to read 6, iclass 3, count 0 2006.246.08:16:02.61#ibcon#read 6, iclass 3, count 0 2006.246.08:16:02.61#ibcon#end of sib2, iclass 3, count 0 2006.246.08:16:02.61#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:16:02.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:16:02.61#ibcon#[27=USB\r\n] 2006.246.08:16:02.61#ibcon#*before write, iclass 3, count 0 2006.246.08:16:02.61#ibcon#enter sib2, iclass 3, count 0 2006.246.08:16:02.61#ibcon#flushed, iclass 3, count 0 2006.246.08:16:02.61#ibcon#about to write, iclass 3, count 0 2006.246.08:16:02.61#ibcon#wrote, iclass 3, count 0 2006.246.08:16:02.61#ibcon#about to read 3, iclass 3, count 0 2006.246.08:16:02.64#ibcon#read 3, iclass 3, count 0 2006.246.08:16:02.64#ibcon#about to read 4, iclass 3, count 0 2006.246.08:16:02.64#ibcon#read 4, iclass 3, count 0 2006.246.08:16:02.64#ibcon#about to read 5, iclass 3, count 0 2006.246.08:16:02.64#ibcon#read 5, iclass 3, count 0 2006.246.08:16:02.64#ibcon#about to read 6, iclass 3, count 0 2006.246.08:16:02.64#ibcon#read 6, iclass 3, count 0 2006.246.08:16:02.64#ibcon#end of sib2, iclass 3, count 0 2006.246.08:16:02.64#ibcon#*after write, iclass 3, count 0 2006.246.08:16:02.64#ibcon#*before return 0, iclass 3, count 0 2006.246.08:16:02.64#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:16:02.64#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:16:02.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:16:02.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:16:02.64$vc4f8/vabw=wide 2006.246.08:16:02.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:16:02.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:16:02.64#ibcon#ireg 8 cls_cnt 0 2006.246.08:16:02.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:16:02.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:16:02.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:16:02.64#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:16:02.64#ibcon#first serial, iclass 5, count 0 2006.246.08:16:02.64#ibcon#enter sib2, iclass 5, count 0 2006.246.08:16:02.64#ibcon#flushed, iclass 5, count 0 2006.246.08:16:02.64#ibcon#about to write, iclass 5, count 0 2006.246.08:16:02.64#ibcon#wrote, iclass 5, count 0 2006.246.08:16:02.64#ibcon#about to read 3, iclass 5, count 0 2006.246.08:16:02.66#ibcon#read 3, iclass 5, count 0 2006.246.08:16:02.66#ibcon#about to read 4, iclass 5, count 0 2006.246.08:16:02.66#ibcon#read 4, iclass 5, count 0 2006.246.08:16:02.66#ibcon#about to read 5, iclass 5, count 0 2006.246.08:16:02.66#ibcon#read 5, iclass 5, count 0 2006.246.08:16:02.66#ibcon#about to read 6, iclass 5, count 0 2006.246.08:16:02.66#ibcon#read 6, iclass 5, count 0 2006.246.08:16:02.66#ibcon#end of sib2, iclass 5, count 0 2006.246.08:16:02.66#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:16:02.66#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:16:02.66#ibcon#[25=BW32\r\n] 2006.246.08:16:02.66#ibcon#*before write, iclass 5, count 0 2006.246.08:16:02.66#ibcon#enter sib2, iclass 5, count 0 2006.246.08:16:02.66#ibcon#flushed, iclass 5, count 0 2006.246.08:16:02.66#ibcon#about to write, iclass 5, count 0 2006.246.08:16:02.66#ibcon#wrote, iclass 5, count 0 2006.246.08:16:02.66#ibcon#about to read 3, iclass 5, count 0 2006.246.08:16:02.69#ibcon#read 3, iclass 5, count 0 2006.246.08:16:02.69#ibcon#about to read 4, iclass 5, count 0 2006.246.08:16:02.69#ibcon#read 4, iclass 5, count 0 2006.246.08:16:02.69#ibcon#about to read 5, iclass 5, count 0 2006.246.08:16:02.69#ibcon#read 5, iclass 5, count 0 2006.246.08:16:02.69#ibcon#about to read 6, iclass 5, count 0 2006.246.08:16:02.69#ibcon#read 6, iclass 5, count 0 2006.246.08:16:02.69#ibcon#end of sib2, iclass 5, count 0 2006.246.08:16:02.69#ibcon#*after write, iclass 5, count 0 2006.246.08:16:02.69#ibcon#*before return 0, iclass 5, count 0 2006.246.08:16:02.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:16:02.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:16:02.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:16:02.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:16:02.69$vc4f8/vbbw=wide 2006.246.08:16:02.69#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.08:16:02.69#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.08:16:02.69#ibcon#ireg 8 cls_cnt 0 2006.246.08:16:02.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:16:02.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:16:02.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:16:02.77#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:16:02.77#ibcon#first serial, iclass 7, count 0 2006.246.08:16:02.77#ibcon#enter sib2, iclass 7, count 0 2006.246.08:16:02.77#ibcon#flushed, iclass 7, count 0 2006.246.08:16:02.77#ibcon#about to write, iclass 7, count 0 2006.246.08:16:02.77#ibcon#wrote, iclass 7, count 0 2006.246.08:16:02.77#ibcon#about to read 3, iclass 7, count 0 2006.246.08:16:02.79#ibcon#read 3, iclass 7, count 0 2006.246.08:16:02.79#ibcon#about to read 4, iclass 7, count 0 2006.246.08:16:02.79#ibcon#read 4, iclass 7, count 0 2006.246.08:16:02.79#ibcon#about to read 5, iclass 7, count 0 2006.246.08:16:02.79#ibcon#read 5, iclass 7, count 0 2006.246.08:16:02.79#ibcon#about to read 6, iclass 7, count 0 2006.246.08:16:02.79#ibcon#read 6, iclass 7, count 0 2006.246.08:16:02.79#ibcon#end of sib2, iclass 7, count 0 2006.246.08:16:02.79#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:16:02.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:16:02.79#ibcon#[27=BW32\r\n] 2006.246.08:16:02.79#ibcon#*before write, iclass 7, count 0 2006.246.08:16:02.79#ibcon#enter sib2, iclass 7, count 0 2006.246.08:16:02.79#ibcon#flushed, iclass 7, count 0 2006.246.08:16:02.79#ibcon#about to write, iclass 7, count 0 2006.246.08:16:02.79#ibcon#wrote, iclass 7, count 0 2006.246.08:16:02.79#ibcon#about to read 3, iclass 7, count 0 2006.246.08:16:02.81#ibcon#read 3, iclass 7, count 0 2006.246.08:16:02.81#ibcon#about to read 4, iclass 7, count 0 2006.246.08:16:02.81#ibcon#read 4, iclass 7, count 0 2006.246.08:16:02.81#ibcon#about to read 5, iclass 7, count 0 2006.246.08:16:02.81#ibcon#read 5, iclass 7, count 0 2006.246.08:16:02.81#ibcon#about to read 6, iclass 7, count 0 2006.246.08:16:02.81#ibcon#read 6, iclass 7, count 0 2006.246.08:16:02.81#ibcon#end of sib2, iclass 7, count 0 2006.246.08:16:02.81#ibcon#*after write, iclass 7, count 0 2006.246.08:16:02.81#ibcon#*before return 0, iclass 7, count 0 2006.246.08:16:02.81#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:16:02.81#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:16:02.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:16:02.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:16:02.81$4f8m12a/ifd4f 2006.246.08:16:02.81$ifd4f/lo= 2006.246.08:16:02.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:16:02.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:16:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:16:02.82$ifd4f/patch= 2006.246.08:16:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:16:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:16:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:16:02.82$4f8m12a/"form=m,16.000,1:2 2006.246.08:16:02.82$4f8m12a/"tpicd 2006.246.08:16:02.82$4f8m12a/echo=off 2006.246.08:16:02.82$4f8m12a/xlog=off 2006.246.08:16:02.82:!2006.246.08:16:30 2006.246.08:16:15.14#trakl#Source acquired 2006.246.08:16:15.14#flagr#flagr/antenna,acquired 2006.246.08:16:30.01:preob 2006.246.08:16:31.14/onsource/TRACKING 2006.246.08:16:31.14:!2006.246.08:16:40 2006.246.08:16:40.00:data_valid=on 2006.246.08:16:40.00:midob 2006.246.08:16:40.14/onsource/TRACKING 2006.246.08:16:40.15/wx/26.33,1005.7,75 2006.246.08:16:40.26/cable/+6.4155E-03 2006.246.08:16:41.35/va/01,08,usb,yes,31,33 2006.246.08:16:41.35/va/02,07,usb,yes,31,33 2006.246.08:16:41.35/va/03,06,usb,yes,33,33 2006.246.08:16:41.35/va/04,07,usb,yes,32,35 2006.246.08:16:41.35/va/05,07,usb,yes,35,37 2006.246.08:16:41.35/va/06,07,usb,yes,30,30 2006.246.08:16:41.35/va/07,07,usb,yes,30,30 2006.246.08:16:41.35/va/08,08,usb,yes,26,26 2006.246.08:16:41.58/valo/01,532.99,yes,locked 2006.246.08:16:41.58/valo/02,572.99,yes,locked 2006.246.08:16:41.58/valo/03,672.99,yes,locked 2006.246.08:16:41.58/valo/04,832.99,yes,locked 2006.246.08:16:41.58/valo/05,652.99,yes,locked 2006.246.08:16:41.58/valo/06,772.99,yes,locked 2006.246.08:16:41.58/valo/07,832.99,yes,locked 2006.246.08:16:41.58/valo/08,852.99,yes,locked 2006.246.08:16:42.67/vb/01,04,usb,yes,31,30 2006.246.08:16:42.67/vb/02,04,usb,yes,33,34 2006.246.08:16:42.67/vb/03,04,usb,yes,29,33 2006.246.08:16:42.67/vb/04,04,usb,yes,30,30 2006.246.08:16:42.67/vb/05,03,usb,yes,35,40 2006.246.08:16:42.67/vb/06,03,usb,yes,36,39 2006.246.08:16:42.67/vb/07,04,usb,yes,31,31 2006.246.08:16:42.67/vb/08,03,usb,yes,36,40 2006.246.08:16:42.91/vblo/01,632.99,yes,locked 2006.246.08:16:42.91/vblo/02,640.99,yes,locked 2006.246.08:16:42.91/vblo/03,656.99,yes,locked 2006.246.08:16:42.91/vblo/04,712.99,yes,locked 2006.246.08:16:42.91/vblo/05,744.99,yes,locked 2006.246.08:16:42.91/vblo/06,752.99,yes,locked 2006.246.08:16:42.91/vblo/07,734.99,yes,locked 2006.246.08:16:42.91/vblo/08,744.99,yes,locked 2006.246.08:16:43.06/vabw/8 2006.246.08:16:43.21/vbbw/8 2006.246.08:16:43.34/xfe/off,on,13.0 2006.246.08:16:43.71/ifatt/23,28,28,28 2006.246.08:16:44.07/fmout-gps/S +4.43E-07 2006.246.08:16:44.12:!2006.246.08:17:40 2006.246.08:17:40.00:data_valid=off 2006.246.08:17:40.01:postob 2006.246.08:17:40.22/cable/+6.4140E-03 2006.246.08:17:40.23/wx/26.31,1005.7,76 2006.246.08:17:41.07/fmout-gps/S +4.45E-07 2006.246.08:17:41.08:scan_name=246-0818,k06246,60 2006.246.08:17:41.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.246.08:17:41.14#flagr#flagr/antenna,new-source 2006.246.08:17:42.14:checkk5 2006.246.08:17:42.54/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:17:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:17:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:17:43.78/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:17:44.15/chk_obsdata//k5ts1/T2460816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:17:44.51/chk_obsdata//k5ts2/T2460816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:17:44.88/chk_obsdata//k5ts3/T2460816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:17:45.27/chk_obsdata//k5ts4/T2460816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:17:45.96/k5log//k5ts1_log_newline 2006.246.08:17:46.68/k5log//k5ts2_log_newline 2006.246.08:17:47.38/k5log//k5ts3_log_newline 2006.246.08:17:48.09/k5log//k5ts4_log_newline 2006.246.08:17:48.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:17:48.11:4f8m12a=2 2006.246.08:17:48.11$4f8m12a/echo=on 2006.246.08:17:48.11$4f8m12a/pcalon 2006.246.08:17:48.11$pcalon/"no phase cal control is implemented here 2006.246.08:17:48.11$4f8m12a/"tpicd=stop 2006.246.08:17:48.11$4f8m12a/vc4f8 2006.246.08:17:48.11$vc4f8/valo=1,532.99 2006.246.08:17:48.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.08:17:48.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.08:17:48.12#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:48.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:48.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:48.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:48.12#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:17:48.12#ibcon#first serial, iclass 20, count 0 2006.246.08:17:48.12#ibcon#enter sib2, iclass 20, count 0 2006.246.08:17:48.12#ibcon#flushed, iclass 20, count 0 2006.246.08:17:48.12#ibcon#about to write, iclass 20, count 0 2006.246.08:17:48.12#ibcon#wrote, iclass 20, count 0 2006.246.08:17:48.12#ibcon#about to read 3, iclass 20, count 0 2006.246.08:17:48.16#ibcon#read 3, iclass 20, count 0 2006.246.08:17:48.16#ibcon#about to read 4, iclass 20, count 0 2006.246.08:17:48.16#ibcon#read 4, iclass 20, count 0 2006.246.08:17:48.16#ibcon#about to read 5, iclass 20, count 0 2006.246.08:17:48.16#ibcon#read 5, iclass 20, count 0 2006.246.08:17:48.16#ibcon#about to read 6, iclass 20, count 0 2006.246.08:17:48.16#ibcon#read 6, iclass 20, count 0 2006.246.08:17:48.16#ibcon#end of sib2, iclass 20, count 0 2006.246.08:17:48.16#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:17:48.16#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:17:48.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:17:48.16#ibcon#*before write, iclass 20, count 0 2006.246.08:17:48.16#ibcon#enter sib2, iclass 20, count 0 2006.246.08:17:48.16#ibcon#flushed, iclass 20, count 0 2006.246.08:17:48.16#ibcon#about to write, iclass 20, count 0 2006.246.08:17:48.16#ibcon#wrote, iclass 20, count 0 2006.246.08:17:48.16#ibcon#about to read 3, iclass 20, count 0 2006.246.08:17:48.20#ibcon#read 3, iclass 20, count 0 2006.246.08:17:48.20#ibcon#about to read 4, iclass 20, count 0 2006.246.08:17:48.20#ibcon#read 4, iclass 20, count 0 2006.246.08:17:48.20#ibcon#about to read 5, iclass 20, count 0 2006.246.08:17:48.20#ibcon#read 5, iclass 20, count 0 2006.246.08:17:48.20#ibcon#about to read 6, iclass 20, count 0 2006.246.08:17:48.20#ibcon#read 6, iclass 20, count 0 2006.246.08:17:48.20#ibcon#end of sib2, iclass 20, count 0 2006.246.08:17:48.20#ibcon#*after write, iclass 20, count 0 2006.246.08:17:48.20#ibcon#*before return 0, iclass 20, count 0 2006.246.08:17:48.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:48.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:48.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:17:48.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:17:48.20$vc4f8/va=1,8 2006.246.08:17:48.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.08:17:48.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.08:17:48.20#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:48.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:48.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:48.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:48.20#ibcon#enter wrdev, iclass 22, count 2 2006.246.08:17:48.20#ibcon#first serial, iclass 22, count 2 2006.246.08:17:48.20#ibcon#enter sib2, iclass 22, count 2 2006.246.08:17:48.20#ibcon#flushed, iclass 22, count 2 2006.246.08:17:48.20#ibcon#about to write, iclass 22, count 2 2006.246.08:17:48.20#ibcon#wrote, iclass 22, count 2 2006.246.08:17:48.20#ibcon#about to read 3, iclass 22, count 2 2006.246.08:17:48.23#ibcon#read 3, iclass 22, count 2 2006.246.08:17:48.23#ibcon#about to read 4, iclass 22, count 2 2006.246.08:17:48.23#ibcon#read 4, iclass 22, count 2 2006.246.08:17:48.23#ibcon#about to read 5, iclass 22, count 2 2006.246.08:17:48.23#ibcon#read 5, iclass 22, count 2 2006.246.08:17:48.23#ibcon#about to read 6, iclass 22, count 2 2006.246.08:17:48.23#ibcon#read 6, iclass 22, count 2 2006.246.08:17:48.23#ibcon#end of sib2, iclass 22, count 2 2006.246.08:17:48.23#ibcon#*mode == 0, iclass 22, count 2 2006.246.08:17:48.23#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.08:17:48.23#ibcon#[25=AT01-08\r\n] 2006.246.08:17:48.23#ibcon#*before write, iclass 22, count 2 2006.246.08:17:48.23#ibcon#enter sib2, iclass 22, count 2 2006.246.08:17:48.23#ibcon#flushed, iclass 22, count 2 2006.246.08:17:48.23#ibcon#about to write, iclass 22, count 2 2006.246.08:17:48.23#ibcon#wrote, iclass 22, count 2 2006.246.08:17:48.23#ibcon#about to read 3, iclass 22, count 2 2006.246.08:17:48.25#ibcon#read 3, iclass 22, count 2 2006.246.08:17:48.25#ibcon#about to read 4, iclass 22, count 2 2006.246.08:17:48.25#ibcon#read 4, iclass 22, count 2 2006.246.08:17:48.25#ibcon#about to read 5, iclass 22, count 2 2006.246.08:17:48.25#ibcon#read 5, iclass 22, count 2 2006.246.08:17:48.25#ibcon#about to read 6, iclass 22, count 2 2006.246.08:17:48.25#ibcon#read 6, iclass 22, count 2 2006.246.08:17:48.25#ibcon#end of sib2, iclass 22, count 2 2006.246.08:17:48.25#ibcon#*after write, iclass 22, count 2 2006.246.08:17:48.25#ibcon#*before return 0, iclass 22, count 2 2006.246.08:17:48.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:48.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:48.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.08:17:48.25#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:48.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:48.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:48.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:48.37#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:17:48.37#ibcon#first serial, iclass 22, count 0 2006.246.08:17:48.37#ibcon#enter sib2, iclass 22, count 0 2006.246.08:17:48.37#ibcon#flushed, iclass 22, count 0 2006.246.08:17:48.37#ibcon#about to write, iclass 22, count 0 2006.246.08:17:48.37#ibcon#wrote, iclass 22, count 0 2006.246.08:17:48.37#ibcon#about to read 3, iclass 22, count 0 2006.246.08:17:48.39#ibcon#read 3, iclass 22, count 0 2006.246.08:17:48.39#ibcon#about to read 4, iclass 22, count 0 2006.246.08:17:48.39#ibcon#read 4, iclass 22, count 0 2006.246.08:17:48.39#ibcon#about to read 5, iclass 22, count 0 2006.246.08:17:48.39#ibcon#read 5, iclass 22, count 0 2006.246.08:17:48.39#ibcon#about to read 6, iclass 22, count 0 2006.246.08:17:48.39#ibcon#read 6, iclass 22, count 0 2006.246.08:17:48.39#ibcon#end of sib2, iclass 22, count 0 2006.246.08:17:48.39#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:17:48.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:17:48.39#ibcon#[25=USB\r\n] 2006.246.08:17:48.39#ibcon#*before write, iclass 22, count 0 2006.246.08:17:48.39#ibcon#enter sib2, iclass 22, count 0 2006.246.08:17:48.39#ibcon#flushed, iclass 22, count 0 2006.246.08:17:48.39#ibcon#about to write, iclass 22, count 0 2006.246.08:17:48.39#ibcon#wrote, iclass 22, count 0 2006.246.08:17:48.39#ibcon#about to read 3, iclass 22, count 0 2006.246.08:17:48.42#ibcon#read 3, iclass 22, count 0 2006.246.08:17:48.42#ibcon#about to read 4, iclass 22, count 0 2006.246.08:17:48.42#ibcon#read 4, iclass 22, count 0 2006.246.08:17:48.42#ibcon#about to read 5, iclass 22, count 0 2006.246.08:17:48.42#ibcon#read 5, iclass 22, count 0 2006.246.08:17:48.42#ibcon#about to read 6, iclass 22, count 0 2006.246.08:17:48.42#ibcon#read 6, iclass 22, count 0 2006.246.08:17:48.42#ibcon#end of sib2, iclass 22, count 0 2006.246.08:17:48.42#ibcon#*after write, iclass 22, count 0 2006.246.08:17:48.42#ibcon#*before return 0, iclass 22, count 0 2006.246.08:17:48.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:48.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:48.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:17:48.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:17:48.42$vc4f8/valo=2,572.99 2006.246.08:17:48.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.08:17:48.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.08:17:48.42#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:48.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:48.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:48.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:48.42#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:17:48.42#ibcon#first serial, iclass 24, count 0 2006.246.08:17:48.42#ibcon#enter sib2, iclass 24, count 0 2006.246.08:17:48.42#ibcon#flushed, iclass 24, count 0 2006.246.08:17:48.42#ibcon#about to write, iclass 24, count 0 2006.246.08:17:48.42#ibcon#wrote, iclass 24, count 0 2006.246.08:17:48.42#ibcon#about to read 3, iclass 24, count 0 2006.246.08:17:48.45#ibcon#read 3, iclass 24, count 0 2006.246.08:17:48.45#ibcon#about to read 4, iclass 24, count 0 2006.246.08:17:48.45#ibcon#read 4, iclass 24, count 0 2006.246.08:17:48.45#ibcon#about to read 5, iclass 24, count 0 2006.246.08:17:48.45#ibcon#read 5, iclass 24, count 0 2006.246.08:17:48.45#ibcon#about to read 6, iclass 24, count 0 2006.246.08:17:48.45#ibcon#read 6, iclass 24, count 0 2006.246.08:17:48.45#ibcon#end of sib2, iclass 24, count 0 2006.246.08:17:48.45#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:17:48.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:17:48.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:17:48.45#ibcon#*before write, iclass 24, count 0 2006.246.08:17:48.45#ibcon#enter sib2, iclass 24, count 0 2006.246.08:17:48.45#ibcon#flushed, iclass 24, count 0 2006.246.08:17:48.45#ibcon#about to write, iclass 24, count 0 2006.246.08:17:48.45#ibcon#wrote, iclass 24, count 0 2006.246.08:17:48.45#ibcon#about to read 3, iclass 24, count 0 2006.246.08:17:48.49#ibcon#read 3, iclass 24, count 0 2006.246.08:17:48.49#ibcon#about to read 4, iclass 24, count 0 2006.246.08:17:48.49#ibcon#read 4, iclass 24, count 0 2006.246.08:17:48.49#ibcon#about to read 5, iclass 24, count 0 2006.246.08:17:48.49#ibcon#read 5, iclass 24, count 0 2006.246.08:17:48.49#ibcon#about to read 6, iclass 24, count 0 2006.246.08:17:48.49#ibcon#read 6, iclass 24, count 0 2006.246.08:17:48.49#ibcon#end of sib2, iclass 24, count 0 2006.246.08:17:48.49#ibcon#*after write, iclass 24, count 0 2006.246.08:17:48.49#ibcon#*before return 0, iclass 24, count 0 2006.246.08:17:48.49#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:48.49#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:48.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:17:48.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:17:48.49$vc4f8/va=2,7 2006.246.08:17:48.49#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.08:17:48.49#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.08:17:48.49#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:48.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:48.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:48.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:48.55#ibcon#enter wrdev, iclass 26, count 2 2006.246.08:17:48.55#ibcon#first serial, iclass 26, count 2 2006.246.08:17:48.55#ibcon#enter sib2, iclass 26, count 2 2006.246.08:17:48.55#ibcon#flushed, iclass 26, count 2 2006.246.08:17:48.55#ibcon#about to write, iclass 26, count 2 2006.246.08:17:48.55#ibcon#wrote, iclass 26, count 2 2006.246.08:17:48.55#ibcon#about to read 3, iclass 26, count 2 2006.246.08:17:48.56#ibcon#read 3, iclass 26, count 2 2006.246.08:17:48.56#ibcon#about to read 4, iclass 26, count 2 2006.246.08:17:48.56#ibcon#read 4, iclass 26, count 2 2006.246.08:17:48.56#ibcon#about to read 5, iclass 26, count 2 2006.246.08:17:48.56#ibcon#read 5, iclass 26, count 2 2006.246.08:17:48.56#ibcon#about to read 6, iclass 26, count 2 2006.246.08:17:48.56#ibcon#read 6, iclass 26, count 2 2006.246.08:17:48.56#ibcon#end of sib2, iclass 26, count 2 2006.246.08:17:48.56#ibcon#*mode == 0, iclass 26, count 2 2006.246.08:17:48.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.08:17:48.56#ibcon#[25=AT02-07\r\n] 2006.246.08:17:48.56#ibcon#*before write, iclass 26, count 2 2006.246.08:17:48.56#ibcon#enter sib2, iclass 26, count 2 2006.246.08:17:48.56#ibcon#flushed, iclass 26, count 2 2006.246.08:17:48.56#ibcon#about to write, iclass 26, count 2 2006.246.08:17:48.56#ibcon#wrote, iclass 26, count 2 2006.246.08:17:48.56#ibcon#about to read 3, iclass 26, count 2 2006.246.08:17:48.59#ibcon#read 3, iclass 26, count 2 2006.246.08:17:48.59#ibcon#about to read 4, iclass 26, count 2 2006.246.08:17:48.59#ibcon#read 4, iclass 26, count 2 2006.246.08:17:48.59#ibcon#about to read 5, iclass 26, count 2 2006.246.08:17:48.59#ibcon#read 5, iclass 26, count 2 2006.246.08:17:48.59#ibcon#about to read 6, iclass 26, count 2 2006.246.08:17:48.59#ibcon#read 6, iclass 26, count 2 2006.246.08:17:48.59#ibcon#end of sib2, iclass 26, count 2 2006.246.08:17:48.59#ibcon#*after write, iclass 26, count 2 2006.246.08:17:48.59#ibcon#*before return 0, iclass 26, count 2 2006.246.08:17:48.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:48.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:48.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.08:17:48.59#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:48.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:48.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:48.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:48.71#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:17:48.71#ibcon#first serial, iclass 26, count 0 2006.246.08:17:48.71#ibcon#enter sib2, iclass 26, count 0 2006.246.08:17:48.71#ibcon#flushed, iclass 26, count 0 2006.246.08:17:48.71#ibcon#about to write, iclass 26, count 0 2006.246.08:17:48.71#ibcon#wrote, iclass 26, count 0 2006.246.08:17:48.71#ibcon#about to read 3, iclass 26, count 0 2006.246.08:17:48.73#ibcon#read 3, iclass 26, count 0 2006.246.08:17:48.73#ibcon#about to read 4, iclass 26, count 0 2006.246.08:17:48.73#ibcon#read 4, iclass 26, count 0 2006.246.08:17:48.73#ibcon#about to read 5, iclass 26, count 0 2006.246.08:17:48.73#ibcon#read 5, iclass 26, count 0 2006.246.08:17:48.73#ibcon#about to read 6, iclass 26, count 0 2006.246.08:17:48.73#ibcon#read 6, iclass 26, count 0 2006.246.08:17:48.73#ibcon#end of sib2, iclass 26, count 0 2006.246.08:17:48.73#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:17:48.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:17:48.73#ibcon#[25=USB\r\n] 2006.246.08:17:48.73#ibcon#*before write, iclass 26, count 0 2006.246.08:17:48.73#ibcon#enter sib2, iclass 26, count 0 2006.246.08:17:48.73#ibcon#flushed, iclass 26, count 0 2006.246.08:17:48.73#ibcon#about to write, iclass 26, count 0 2006.246.08:17:48.73#ibcon#wrote, iclass 26, count 0 2006.246.08:17:48.73#ibcon#about to read 3, iclass 26, count 0 2006.246.08:17:48.76#ibcon#read 3, iclass 26, count 0 2006.246.08:17:48.76#ibcon#about to read 4, iclass 26, count 0 2006.246.08:17:48.76#ibcon#read 4, iclass 26, count 0 2006.246.08:17:48.76#ibcon#about to read 5, iclass 26, count 0 2006.246.08:17:48.76#ibcon#read 5, iclass 26, count 0 2006.246.08:17:48.76#ibcon#about to read 6, iclass 26, count 0 2006.246.08:17:48.76#ibcon#read 6, iclass 26, count 0 2006.246.08:17:48.76#ibcon#end of sib2, iclass 26, count 0 2006.246.08:17:48.76#ibcon#*after write, iclass 26, count 0 2006.246.08:17:48.76#ibcon#*before return 0, iclass 26, count 0 2006.246.08:17:48.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:48.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:48.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:17:48.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:17:48.76$vc4f8/valo=3,672.99 2006.246.08:17:48.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.08:17:48.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.08:17:48.76#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:48.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:48.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:48.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:48.76#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:17:48.76#ibcon#first serial, iclass 28, count 0 2006.246.08:17:48.76#ibcon#enter sib2, iclass 28, count 0 2006.246.08:17:48.76#ibcon#flushed, iclass 28, count 0 2006.246.08:17:48.76#ibcon#about to write, iclass 28, count 0 2006.246.08:17:48.76#ibcon#wrote, iclass 28, count 0 2006.246.08:17:48.76#ibcon#about to read 3, iclass 28, count 0 2006.246.08:17:48.79#ibcon#read 3, iclass 28, count 0 2006.246.08:17:48.79#ibcon#about to read 4, iclass 28, count 0 2006.246.08:17:48.79#ibcon#read 4, iclass 28, count 0 2006.246.08:17:48.79#ibcon#about to read 5, iclass 28, count 0 2006.246.08:17:48.79#ibcon#read 5, iclass 28, count 0 2006.246.08:17:48.79#ibcon#about to read 6, iclass 28, count 0 2006.246.08:17:48.79#ibcon#read 6, iclass 28, count 0 2006.246.08:17:48.79#ibcon#end of sib2, iclass 28, count 0 2006.246.08:17:48.79#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:17:48.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:17:48.79#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:17:48.79#ibcon#*before write, iclass 28, count 0 2006.246.08:17:48.79#ibcon#enter sib2, iclass 28, count 0 2006.246.08:17:48.79#ibcon#flushed, iclass 28, count 0 2006.246.08:17:48.79#ibcon#about to write, iclass 28, count 0 2006.246.08:17:48.79#ibcon#wrote, iclass 28, count 0 2006.246.08:17:48.79#ibcon#about to read 3, iclass 28, count 0 2006.246.08:17:48.83#ibcon#read 3, iclass 28, count 0 2006.246.08:17:48.83#ibcon#about to read 4, iclass 28, count 0 2006.246.08:17:48.83#ibcon#read 4, iclass 28, count 0 2006.246.08:17:48.83#ibcon#about to read 5, iclass 28, count 0 2006.246.08:17:48.83#ibcon#read 5, iclass 28, count 0 2006.246.08:17:48.83#ibcon#about to read 6, iclass 28, count 0 2006.246.08:17:48.83#ibcon#read 6, iclass 28, count 0 2006.246.08:17:48.83#ibcon#end of sib2, iclass 28, count 0 2006.246.08:17:48.83#ibcon#*after write, iclass 28, count 0 2006.246.08:17:48.83#ibcon#*before return 0, iclass 28, count 0 2006.246.08:17:48.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:48.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:48.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:17:48.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:17:48.83$vc4f8/va=3,6 2006.246.08:17:48.83#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.08:17:48.83#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.08:17:48.83#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:48.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:48.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:48.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:48.89#ibcon#enter wrdev, iclass 30, count 2 2006.246.08:17:48.89#ibcon#first serial, iclass 30, count 2 2006.246.08:17:48.89#ibcon#enter sib2, iclass 30, count 2 2006.246.08:17:48.89#ibcon#flushed, iclass 30, count 2 2006.246.08:17:48.89#ibcon#about to write, iclass 30, count 2 2006.246.08:17:48.89#ibcon#wrote, iclass 30, count 2 2006.246.08:17:48.89#ibcon#about to read 3, iclass 30, count 2 2006.246.08:17:48.90#ibcon#read 3, iclass 30, count 2 2006.246.08:17:48.90#ibcon#about to read 4, iclass 30, count 2 2006.246.08:17:48.90#ibcon#read 4, iclass 30, count 2 2006.246.08:17:48.90#ibcon#about to read 5, iclass 30, count 2 2006.246.08:17:48.90#ibcon#read 5, iclass 30, count 2 2006.246.08:17:48.90#ibcon#about to read 6, iclass 30, count 2 2006.246.08:17:48.90#ibcon#read 6, iclass 30, count 2 2006.246.08:17:48.90#ibcon#end of sib2, iclass 30, count 2 2006.246.08:17:48.90#ibcon#*mode == 0, iclass 30, count 2 2006.246.08:17:48.90#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.08:17:48.90#ibcon#[25=AT03-06\r\n] 2006.246.08:17:48.90#ibcon#*before write, iclass 30, count 2 2006.246.08:17:48.90#ibcon#enter sib2, iclass 30, count 2 2006.246.08:17:48.90#ibcon#flushed, iclass 30, count 2 2006.246.08:17:48.90#ibcon#about to write, iclass 30, count 2 2006.246.08:17:48.90#ibcon#wrote, iclass 30, count 2 2006.246.08:17:48.90#ibcon#about to read 3, iclass 30, count 2 2006.246.08:17:48.93#ibcon#read 3, iclass 30, count 2 2006.246.08:17:48.93#ibcon#about to read 4, iclass 30, count 2 2006.246.08:17:48.93#ibcon#read 4, iclass 30, count 2 2006.246.08:17:48.93#ibcon#about to read 5, iclass 30, count 2 2006.246.08:17:48.93#ibcon#read 5, iclass 30, count 2 2006.246.08:17:48.93#ibcon#about to read 6, iclass 30, count 2 2006.246.08:17:48.93#ibcon#read 6, iclass 30, count 2 2006.246.08:17:48.93#ibcon#end of sib2, iclass 30, count 2 2006.246.08:17:48.93#ibcon#*after write, iclass 30, count 2 2006.246.08:17:48.93#ibcon#*before return 0, iclass 30, count 2 2006.246.08:17:48.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:48.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:48.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.08:17:48.93#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:48.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:49.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:49.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:49.05#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:17:49.05#ibcon#first serial, iclass 30, count 0 2006.246.08:17:49.05#ibcon#enter sib2, iclass 30, count 0 2006.246.08:17:49.05#ibcon#flushed, iclass 30, count 0 2006.246.08:17:49.05#ibcon#about to write, iclass 30, count 0 2006.246.08:17:49.05#ibcon#wrote, iclass 30, count 0 2006.246.08:17:49.05#ibcon#about to read 3, iclass 30, count 0 2006.246.08:17:49.07#ibcon#read 3, iclass 30, count 0 2006.246.08:17:49.07#ibcon#about to read 4, iclass 30, count 0 2006.246.08:17:49.07#ibcon#read 4, iclass 30, count 0 2006.246.08:17:49.07#ibcon#about to read 5, iclass 30, count 0 2006.246.08:17:49.07#ibcon#read 5, iclass 30, count 0 2006.246.08:17:49.07#ibcon#about to read 6, iclass 30, count 0 2006.246.08:17:49.07#ibcon#read 6, iclass 30, count 0 2006.246.08:17:49.07#ibcon#end of sib2, iclass 30, count 0 2006.246.08:17:49.07#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:17:49.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:17:49.07#ibcon#[25=USB\r\n] 2006.246.08:17:49.07#ibcon#*before write, iclass 30, count 0 2006.246.08:17:49.07#ibcon#enter sib2, iclass 30, count 0 2006.246.08:17:49.07#ibcon#flushed, iclass 30, count 0 2006.246.08:17:49.07#ibcon#about to write, iclass 30, count 0 2006.246.08:17:49.07#ibcon#wrote, iclass 30, count 0 2006.246.08:17:49.07#ibcon#about to read 3, iclass 30, count 0 2006.246.08:17:49.10#ibcon#read 3, iclass 30, count 0 2006.246.08:17:49.10#ibcon#about to read 4, iclass 30, count 0 2006.246.08:17:49.10#ibcon#read 4, iclass 30, count 0 2006.246.08:17:49.10#ibcon#about to read 5, iclass 30, count 0 2006.246.08:17:49.10#ibcon#read 5, iclass 30, count 0 2006.246.08:17:49.10#ibcon#about to read 6, iclass 30, count 0 2006.246.08:17:49.10#ibcon#read 6, iclass 30, count 0 2006.246.08:17:49.10#ibcon#end of sib2, iclass 30, count 0 2006.246.08:17:49.10#ibcon#*after write, iclass 30, count 0 2006.246.08:17:49.10#ibcon#*before return 0, iclass 30, count 0 2006.246.08:17:49.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:49.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:49.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:17:49.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:17:49.10$vc4f8/valo=4,832.99 2006.246.08:17:49.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:17:49.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:17:49.10#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:49.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:49.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:49.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:49.10#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:17:49.10#ibcon#first serial, iclass 32, count 0 2006.246.08:17:49.10#ibcon#enter sib2, iclass 32, count 0 2006.246.08:17:49.10#ibcon#flushed, iclass 32, count 0 2006.246.08:17:49.10#ibcon#about to write, iclass 32, count 0 2006.246.08:17:49.10#ibcon#wrote, iclass 32, count 0 2006.246.08:17:49.10#ibcon#about to read 3, iclass 32, count 0 2006.246.08:17:49.12#ibcon#read 3, iclass 32, count 0 2006.246.08:17:49.12#ibcon#about to read 4, iclass 32, count 0 2006.246.08:17:49.12#ibcon#read 4, iclass 32, count 0 2006.246.08:17:49.12#ibcon#about to read 5, iclass 32, count 0 2006.246.08:17:49.12#ibcon#read 5, iclass 32, count 0 2006.246.08:17:49.12#ibcon#about to read 6, iclass 32, count 0 2006.246.08:17:49.12#ibcon#read 6, iclass 32, count 0 2006.246.08:17:49.12#ibcon#end of sib2, iclass 32, count 0 2006.246.08:17:49.12#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:17:49.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:17:49.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:17:49.12#ibcon#*before write, iclass 32, count 0 2006.246.08:17:49.12#ibcon#enter sib2, iclass 32, count 0 2006.246.08:17:49.12#ibcon#flushed, iclass 32, count 0 2006.246.08:17:49.12#ibcon#about to write, iclass 32, count 0 2006.246.08:17:49.12#ibcon#wrote, iclass 32, count 0 2006.246.08:17:49.12#ibcon#about to read 3, iclass 32, count 0 2006.246.08:17:49.16#ibcon#read 3, iclass 32, count 0 2006.246.08:17:49.16#ibcon#about to read 4, iclass 32, count 0 2006.246.08:17:49.16#ibcon#read 4, iclass 32, count 0 2006.246.08:17:49.16#ibcon#about to read 5, iclass 32, count 0 2006.246.08:17:49.16#ibcon#read 5, iclass 32, count 0 2006.246.08:17:49.16#ibcon#about to read 6, iclass 32, count 0 2006.246.08:17:49.16#ibcon#read 6, iclass 32, count 0 2006.246.08:17:49.16#ibcon#end of sib2, iclass 32, count 0 2006.246.08:17:49.16#ibcon#*after write, iclass 32, count 0 2006.246.08:17:49.16#ibcon#*before return 0, iclass 32, count 0 2006.246.08:17:49.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:49.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:49.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:17:49.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:17:49.16$vc4f8/va=4,7 2006.246.08:17:49.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.08:17:49.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.08:17:49.16#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:49.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:49.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:49.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:49.22#ibcon#enter wrdev, iclass 34, count 2 2006.246.08:17:49.22#ibcon#first serial, iclass 34, count 2 2006.246.08:17:49.22#ibcon#enter sib2, iclass 34, count 2 2006.246.08:17:49.22#ibcon#flushed, iclass 34, count 2 2006.246.08:17:49.22#ibcon#about to write, iclass 34, count 2 2006.246.08:17:49.22#ibcon#wrote, iclass 34, count 2 2006.246.08:17:49.22#ibcon#about to read 3, iclass 34, count 2 2006.246.08:17:49.24#ibcon#read 3, iclass 34, count 2 2006.246.08:17:49.24#ibcon#about to read 4, iclass 34, count 2 2006.246.08:17:49.24#ibcon#read 4, iclass 34, count 2 2006.246.08:17:49.24#ibcon#about to read 5, iclass 34, count 2 2006.246.08:17:49.24#ibcon#read 5, iclass 34, count 2 2006.246.08:17:49.24#ibcon#about to read 6, iclass 34, count 2 2006.246.08:17:49.24#ibcon#read 6, iclass 34, count 2 2006.246.08:17:49.24#ibcon#end of sib2, iclass 34, count 2 2006.246.08:17:49.24#ibcon#*mode == 0, iclass 34, count 2 2006.246.08:17:49.24#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.08:17:49.24#ibcon#[25=AT04-07\r\n] 2006.246.08:17:49.24#ibcon#*before write, iclass 34, count 2 2006.246.08:17:49.24#ibcon#enter sib2, iclass 34, count 2 2006.246.08:17:49.24#ibcon#flushed, iclass 34, count 2 2006.246.08:17:49.24#ibcon#about to write, iclass 34, count 2 2006.246.08:17:49.24#ibcon#wrote, iclass 34, count 2 2006.246.08:17:49.24#ibcon#about to read 3, iclass 34, count 2 2006.246.08:17:49.27#ibcon#read 3, iclass 34, count 2 2006.246.08:17:49.27#ibcon#about to read 4, iclass 34, count 2 2006.246.08:17:49.27#ibcon#read 4, iclass 34, count 2 2006.246.08:17:49.27#ibcon#about to read 5, iclass 34, count 2 2006.246.08:17:49.27#ibcon#read 5, iclass 34, count 2 2006.246.08:17:49.27#ibcon#about to read 6, iclass 34, count 2 2006.246.08:17:49.27#ibcon#read 6, iclass 34, count 2 2006.246.08:17:49.27#ibcon#end of sib2, iclass 34, count 2 2006.246.08:17:49.27#ibcon#*after write, iclass 34, count 2 2006.246.08:17:49.27#ibcon#*before return 0, iclass 34, count 2 2006.246.08:17:49.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:49.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:49.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.08:17:49.27#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:49.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:49.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:49.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:49.39#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:17:49.39#ibcon#first serial, iclass 34, count 0 2006.246.08:17:49.39#ibcon#enter sib2, iclass 34, count 0 2006.246.08:17:49.39#ibcon#flushed, iclass 34, count 0 2006.246.08:17:49.39#ibcon#about to write, iclass 34, count 0 2006.246.08:17:49.39#ibcon#wrote, iclass 34, count 0 2006.246.08:17:49.39#ibcon#about to read 3, iclass 34, count 0 2006.246.08:17:49.41#ibcon#read 3, iclass 34, count 0 2006.246.08:17:49.41#ibcon#about to read 4, iclass 34, count 0 2006.246.08:17:49.41#ibcon#read 4, iclass 34, count 0 2006.246.08:17:49.41#ibcon#about to read 5, iclass 34, count 0 2006.246.08:17:49.41#ibcon#read 5, iclass 34, count 0 2006.246.08:17:49.41#ibcon#about to read 6, iclass 34, count 0 2006.246.08:17:49.41#ibcon#read 6, iclass 34, count 0 2006.246.08:17:49.41#ibcon#end of sib2, iclass 34, count 0 2006.246.08:17:49.41#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:17:49.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:17:49.41#ibcon#[25=USB\r\n] 2006.246.08:17:49.41#ibcon#*before write, iclass 34, count 0 2006.246.08:17:49.41#ibcon#enter sib2, iclass 34, count 0 2006.246.08:17:49.41#ibcon#flushed, iclass 34, count 0 2006.246.08:17:49.41#ibcon#about to write, iclass 34, count 0 2006.246.08:17:49.41#ibcon#wrote, iclass 34, count 0 2006.246.08:17:49.41#ibcon#about to read 3, iclass 34, count 0 2006.246.08:17:49.44#ibcon#read 3, iclass 34, count 0 2006.246.08:17:49.44#ibcon#about to read 4, iclass 34, count 0 2006.246.08:17:49.44#ibcon#read 4, iclass 34, count 0 2006.246.08:17:49.44#ibcon#about to read 5, iclass 34, count 0 2006.246.08:17:49.44#ibcon#read 5, iclass 34, count 0 2006.246.08:17:49.44#ibcon#about to read 6, iclass 34, count 0 2006.246.08:17:49.44#ibcon#read 6, iclass 34, count 0 2006.246.08:17:49.44#ibcon#end of sib2, iclass 34, count 0 2006.246.08:17:49.44#ibcon#*after write, iclass 34, count 0 2006.246.08:17:49.44#ibcon#*before return 0, iclass 34, count 0 2006.246.08:17:49.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:49.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:49.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:17:49.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:17:49.44$vc4f8/valo=5,652.99 2006.246.08:17:49.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.08:17:49.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.08:17:49.44#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:49.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:49.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:49.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:49.44#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:17:49.44#ibcon#first serial, iclass 36, count 0 2006.246.08:17:49.44#ibcon#enter sib2, iclass 36, count 0 2006.246.08:17:49.44#ibcon#flushed, iclass 36, count 0 2006.246.08:17:49.44#ibcon#about to write, iclass 36, count 0 2006.246.08:17:49.44#ibcon#wrote, iclass 36, count 0 2006.246.08:17:49.44#ibcon#about to read 3, iclass 36, count 0 2006.246.08:17:49.46#ibcon#read 3, iclass 36, count 0 2006.246.08:17:49.46#ibcon#about to read 4, iclass 36, count 0 2006.246.08:17:49.46#ibcon#read 4, iclass 36, count 0 2006.246.08:17:49.46#ibcon#about to read 5, iclass 36, count 0 2006.246.08:17:49.46#ibcon#read 5, iclass 36, count 0 2006.246.08:17:49.46#ibcon#about to read 6, iclass 36, count 0 2006.246.08:17:49.46#ibcon#read 6, iclass 36, count 0 2006.246.08:17:49.46#ibcon#end of sib2, iclass 36, count 0 2006.246.08:17:49.46#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:17:49.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:17:49.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:17:49.46#ibcon#*before write, iclass 36, count 0 2006.246.08:17:49.46#ibcon#enter sib2, iclass 36, count 0 2006.246.08:17:49.46#ibcon#flushed, iclass 36, count 0 2006.246.08:17:49.46#ibcon#about to write, iclass 36, count 0 2006.246.08:17:49.46#ibcon#wrote, iclass 36, count 0 2006.246.08:17:49.46#ibcon#about to read 3, iclass 36, count 0 2006.246.08:17:49.50#ibcon#read 3, iclass 36, count 0 2006.246.08:17:49.50#ibcon#about to read 4, iclass 36, count 0 2006.246.08:17:49.50#ibcon#read 4, iclass 36, count 0 2006.246.08:17:49.50#ibcon#about to read 5, iclass 36, count 0 2006.246.08:17:49.50#ibcon#read 5, iclass 36, count 0 2006.246.08:17:49.50#ibcon#about to read 6, iclass 36, count 0 2006.246.08:17:49.50#ibcon#read 6, iclass 36, count 0 2006.246.08:17:49.50#ibcon#end of sib2, iclass 36, count 0 2006.246.08:17:49.50#ibcon#*after write, iclass 36, count 0 2006.246.08:17:49.50#ibcon#*before return 0, iclass 36, count 0 2006.246.08:17:49.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:49.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:49.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:17:49.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:17:49.50$vc4f8/va=5,7 2006.246.08:17:49.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.08:17:49.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.08:17:49.50#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:49.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:49.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:49.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:49.56#ibcon#enter wrdev, iclass 38, count 2 2006.246.08:17:49.56#ibcon#first serial, iclass 38, count 2 2006.246.08:17:49.56#ibcon#enter sib2, iclass 38, count 2 2006.246.08:17:49.56#ibcon#flushed, iclass 38, count 2 2006.246.08:17:49.56#ibcon#about to write, iclass 38, count 2 2006.246.08:17:49.56#ibcon#wrote, iclass 38, count 2 2006.246.08:17:49.56#ibcon#about to read 3, iclass 38, count 2 2006.246.08:17:49.58#ibcon#read 3, iclass 38, count 2 2006.246.08:17:49.58#ibcon#about to read 4, iclass 38, count 2 2006.246.08:17:49.58#ibcon#read 4, iclass 38, count 2 2006.246.08:17:49.58#ibcon#about to read 5, iclass 38, count 2 2006.246.08:17:49.58#ibcon#read 5, iclass 38, count 2 2006.246.08:17:49.58#ibcon#about to read 6, iclass 38, count 2 2006.246.08:17:49.58#ibcon#read 6, iclass 38, count 2 2006.246.08:17:49.58#ibcon#end of sib2, iclass 38, count 2 2006.246.08:17:49.58#ibcon#*mode == 0, iclass 38, count 2 2006.246.08:17:49.58#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.08:17:49.58#ibcon#[25=AT05-07\r\n] 2006.246.08:17:49.58#ibcon#*before write, iclass 38, count 2 2006.246.08:17:49.58#ibcon#enter sib2, iclass 38, count 2 2006.246.08:17:49.58#ibcon#flushed, iclass 38, count 2 2006.246.08:17:49.58#ibcon#about to write, iclass 38, count 2 2006.246.08:17:49.58#ibcon#wrote, iclass 38, count 2 2006.246.08:17:49.58#ibcon#about to read 3, iclass 38, count 2 2006.246.08:17:49.61#ibcon#read 3, iclass 38, count 2 2006.246.08:17:49.61#ibcon#about to read 4, iclass 38, count 2 2006.246.08:17:49.61#ibcon#read 4, iclass 38, count 2 2006.246.08:17:49.61#ibcon#about to read 5, iclass 38, count 2 2006.246.08:17:49.61#ibcon#read 5, iclass 38, count 2 2006.246.08:17:49.61#ibcon#about to read 6, iclass 38, count 2 2006.246.08:17:49.61#ibcon#read 6, iclass 38, count 2 2006.246.08:17:49.61#ibcon#end of sib2, iclass 38, count 2 2006.246.08:17:49.61#ibcon#*after write, iclass 38, count 2 2006.246.08:17:49.61#ibcon#*before return 0, iclass 38, count 2 2006.246.08:17:49.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:49.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:49.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.08:17:49.61#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:49.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:49.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:49.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:49.73#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:17:49.73#ibcon#first serial, iclass 38, count 0 2006.246.08:17:49.73#ibcon#enter sib2, iclass 38, count 0 2006.246.08:17:49.73#ibcon#flushed, iclass 38, count 0 2006.246.08:17:49.73#ibcon#about to write, iclass 38, count 0 2006.246.08:17:49.73#ibcon#wrote, iclass 38, count 0 2006.246.08:17:49.73#ibcon#about to read 3, iclass 38, count 0 2006.246.08:17:49.75#ibcon#read 3, iclass 38, count 0 2006.246.08:17:49.75#ibcon#about to read 4, iclass 38, count 0 2006.246.08:17:49.75#ibcon#read 4, iclass 38, count 0 2006.246.08:17:49.75#ibcon#about to read 5, iclass 38, count 0 2006.246.08:17:49.75#ibcon#read 5, iclass 38, count 0 2006.246.08:17:49.75#ibcon#about to read 6, iclass 38, count 0 2006.246.08:17:49.75#ibcon#read 6, iclass 38, count 0 2006.246.08:17:49.75#ibcon#end of sib2, iclass 38, count 0 2006.246.08:17:49.75#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:17:49.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:17:49.75#ibcon#[25=USB\r\n] 2006.246.08:17:49.75#ibcon#*before write, iclass 38, count 0 2006.246.08:17:49.75#ibcon#enter sib2, iclass 38, count 0 2006.246.08:17:49.75#ibcon#flushed, iclass 38, count 0 2006.246.08:17:49.75#ibcon#about to write, iclass 38, count 0 2006.246.08:17:49.75#ibcon#wrote, iclass 38, count 0 2006.246.08:17:49.75#ibcon#about to read 3, iclass 38, count 0 2006.246.08:17:49.78#ibcon#read 3, iclass 38, count 0 2006.246.08:17:49.78#ibcon#about to read 4, iclass 38, count 0 2006.246.08:17:49.78#ibcon#read 4, iclass 38, count 0 2006.246.08:17:49.78#ibcon#about to read 5, iclass 38, count 0 2006.246.08:17:49.78#ibcon#read 5, iclass 38, count 0 2006.246.08:17:49.78#ibcon#about to read 6, iclass 38, count 0 2006.246.08:17:49.78#ibcon#read 6, iclass 38, count 0 2006.246.08:17:49.78#ibcon#end of sib2, iclass 38, count 0 2006.246.08:17:49.78#ibcon#*after write, iclass 38, count 0 2006.246.08:17:49.78#ibcon#*before return 0, iclass 38, count 0 2006.246.08:17:49.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:49.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:49.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:17:49.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:17:49.78$vc4f8/valo=6,772.99 2006.246.08:17:49.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.08:17:49.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.08:17:49.78#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:49.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:49.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:49.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:49.78#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:17:49.78#ibcon#first serial, iclass 40, count 0 2006.246.08:17:49.78#ibcon#enter sib2, iclass 40, count 0 2006.246.08:17:49.78#ibcon#flushed, iclass 40, count 0 2006.246.08:17:49.78#ibcon#about to write, iclass 40, count 0 2006.246.08:17:49.78#ibcon#wrote, iclass 40, count 0 2006.246.08:17:49.78#ibcon#about to read 3, iclass 40, count 0 2006.246.08:17:49.80#ibcon#read 3, iclass 40, count 0 2006.246.08:17:49.80#ibcon#about to read 4, iclass 40, count 0 2006.246.08:17:49.80#ibcon#read 4, iclass 40, count 0 2006.246.08:17:49.80#ibcon#about to read 5, iclass 40, count 0 2006.246.08:17:49.80#ibcon#read 5, iclass 40, count 0 2006.246.08:17:49.80#ibcon#about to read 6, iclass 40, count 0 2006.246.08:17:49.80#ibcon#read 6, iclass 40, count 0 2006.246.08:17:49.80#ibcon#end of sib2, iclass 40, count 0 2006.246.08:17:49.80#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:17:49.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:17:49.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:17:49.80#ibcon#*before write, iclass 40, count 0 2006.246.08:17:49.80#ibcon#enter sib2, iclass 40, count 0 2006.246.08:17:49.80#ibcon#flushed, iclass 40, count 0 2006.246.08:17:49.80#ibcon#about to write, iclass 40, count 0 2006.246.08:17:49.80#ibcon#wrote, iclass 40, count 0 2006.246.08:17:49.80#ibcon#about to read 3, iclass 40, count 0 2006.246.08:17:49.84#ibcon#read 3, iclass 40, count 0 2006.246.08:17:49.84#ibcon#about to read 4, iclass 40, count 0 2006.246.08:17:49.84#ibcon#read 4, iclass 40, count 0 2006.246.08:17:49.84#ibcon#about to read 5, iclass 40, count 0 2006.246.08:17:49.84#ibcon#read 5, iclass 40, count 0 2006.246.08:17:49.84#ibcon#about to read 6, iclass 40, count 0 2006.246.08:17:49.84#ibcon#read 6, iclass 40, count 0 2006.246.08:17:49.84#ibcon#end of sib2, iclass 40, count 0 2006.246.08:17:49.84#ibcon#*after write, iclass 40, count 0 2006.246.08:17:49.84#ibcon#*before return 0, iclass 40, count 0 2006.246.08:17:49.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:49.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:49.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:17:49.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:17:49.84$vc4f8/va=6,7 2006.246.08:17:49.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.246.08:17:49.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.246.08:17:49.84#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:49.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:17:49.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:17:49.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:17:49.90#ibcon#enter wrdev, iclass 4, count 2 2006.246.08:17:49.90#ibcon#first serial, iclass 4, count 2 2006.246.08:17:49.90#ibcon#enter sib2, iclass 4, count 2 2006.246.08:17:49.90#ibcon#flushed, iclass 4, count 2 2006.246.08:17:49.90#ibcon#about to write, iclass 4, count 2 2006.246.08:17:49.90#ibcon#wrote, iclass 4, count 2 2006.246.08:17:49.90#ibcon#about to read 3, iclass 4, count 2 2006.246.08:17:49.93#ibcon#read 3, iclass 4, count 2 2006.246.08:17:49.93#ibcon#about to read 4, iclass 4, count 2 2006.246.08:17:49.93#ibcon#read 4, iclass 4, count 2 2006.246.08:17:49.93#ibcon#about to read 5, iclass 4, count 2 2006.246.08:17:49.93#ibcon#read 5, iclass 4, count 2 2006.246.08:17:49.93#ibcon#about to read 6, iclass 4, count 2 2006.246.08:17:49.93#ibcon#read 6, iclass 4, count 2 2006.246.08:17:49.93#ibcon#end of sib2, iclass 4, count 2 2006.246.08:17:49.93#ibcon#*mode == 0, iclass 4, count 2 2006.246.08:17:49.93#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.246.08:17:49.93#ibcon#[25=AT06-07\r\n] 2006.246.08:17:49.93#ibcon#*before write, iclass 4, count 2 2006.246.08:17:49.93#ibcon#enter sib2, iclass 4, count 2 2006.246.08:17:49.93#ibcon#flushed, iclass 4, count 2 2006.246.08:17:49.93#ibcon#about to write, iclass 4, count 2 2006.246.08:17:49.93#ibcon#wrote, iclass 4, count 2 2006.246.08:17:49.93#ibcon#about to read 3, iclass 4, count 2 2006.246.08:17:49.95#ibcon#read 3, iclass 4, count 2 2006.246.08:17:49.95#ibcon#about to read 4, iclass 4, count 2 2006.246.08:17:49.95#ibcon#read 4, iclass 4, count 2 2006.246.08:17:49.95#ibcon#about to read 5, iclass 4, count 2 2006.246.08:17:49.95#ibcon#read 5, iclass 4, count 2 2006.246.08:17:49.95#ibcon#about to read 6, iclass 4, count 2 2006.246.08:17:49.95#ibcon#read 6, iclass 4, count 2 2006.246.08:17:49.95#ibcon#end of sib2, iclass 4, count 2 2006.246.08:17:49.95#ibcon#*after write, iclass 4, count 2 2006.246.08:17:49.95#ibcon#*before return 0, iclass 4, count 2 2006.246.08:17:49.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:17:49.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.246.08:17:49.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.246.08:17:49.95#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:49.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:17:50.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:17:50.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:17:50.07#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:17:50.07#ibcon#first serial, iclass 4, count 0 2006.246.08:17:50.07#ibcon#enter sib2, iclass 4, count 0 2006.246.08:17:50.07#ibcon#flushed, iclass 4, count 0 2006.246.08:17:50.07#ibcon#about to write, iclass 4, count 0 2006.246.08:17:50.07#ibcon#wrote, iclass 4, count 0 2006.246.08:17:50.07#ibcon#about to read 3, iclass 4, count 0 2006.246.08:17:50.09#ibcon#read 3, iclass 4, count 0 2006.246.08:17:50.09#ibcon#about to read 4, iclass 4, count 0 2006.246.08:17:50.09#ibcon#read 4, iclass 4, count 0 2006.246.08:17:50.09#ibcon#about to read 5, iclass 4, count 0 2006.246.08:17:50.09#ibcon#read 5, iclass 4, count 0 2006.246.08:17:50.09#ibcon#about to read 6, iclass 4, count 0 2006.246.08:17:50.09#ibcon#read 6, iclass 4, count 0 2006.246.08:17:50.09#ibcon#end of sib2, iclass 4, count 0 2006.246.08:17:50.09#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:17:50.09#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:17:50.09#ibcon#[25=USB\r\n] 2006.246.08:17:50.09#ibcon#*before write, iclass 4, count 0 2006.246.08:17:50.09#ibcon#enter sib2, iclass 4, count 0 2006.246.08:17:50.09#ibcon#flushed, iclass 4, count 0 2006.246.08:17:50.09#ibcon#about to write, iclass 4, count 0 2006.246.08:17:50.09#ibcon#wrote, iclass 4, count 0 2006.246.08:17:50.09#ibcon#about to read 3, iclass 4, count 0 2006.246.08:17:50.12#ibcon#read 3, iclass 4, count 0 2006.246.08:17:50.12#ibcon#about to read 4, iclass 4, count 0 2006.246.08:17:50.12#ibcon#read 4, iclass 4, count 0 2006.246.08:17:50.12#ibcon#about to read 5, iclass 4, count 0 2006.246.08:17:50.12#ibcon#read 5, iclass 4, count 0 2006.246.08:17:50.12#ibcon#about to read 6, iclass 4, count 0 2006.246.08:17:50.12#ibcon#read 6, iclass 4, count 0 2006.246.08:17:50.12#ibcon#end of sib2, iclass 4, count 0 2006.246.08:17:50.12#ibcon#*after write, iclass 4, count 0 2006.246.08:17:50.12#ibcon#*before return 0, iclass 4, count 0 2006.246.08:17:50.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:17:50.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.246.08:17:50.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:17:50.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:17:50.12$vc4f8/valo=7,832.99 2006.246.08:17:50.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.246.08:17:50.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.246.08:17:50.12#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:50.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:17:50.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:17:50.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:17:50.12#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:17:50.12#ibcon#first serial, iclass 6, count 0 2006.246.08:17:50.12#ibcon#enter sib2, iclass 6, count 0 2006.246.08:17:50.12#ibcon#flushed, iclass 6, count 0 2006.246.08:17:50.12#ibcon#about to write, iclass 6, count 0 2006.246.08:17:50.12#ibcon#wrote, iclass 6, count 0 2006.246.08:17:50.12#ibcon#about to read 3, iclass 6, count 0 2006.246.08:17:50.14#ibcon#read 3, iclass 6, count 0 2006.246.08:17:50.14#ibcon#about to read 4, iclass 6, count 0 2006.246.08:17:50.14#ibcon#read 4, iclass 6, count 0 2006.246.08:17:50.14#ibcon#about to read 5, iclass 6, count 0 2006.246.08:17:50.14#ibcon#read 5, iclass 6, count 0 2006.246.08:17:50.14#ibcon#about to read 6, iclass 6, count 0 2006.246.08:17:50.14#ibcon#read 6, iclass 6, count 0 2006.246.08:17:50.14#ibcon#end of sib2, iclass 6, count 0 2006.246.08:17:50.14#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:17:50.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:17:50.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:17:50.14#ibcon#*before write, iclass 6, count 0 2006.246.08:17:50.14#ibcon#enter sib2, iclass 6, count 0 2006.246.08:17:50.14#ibcon#flushed, iclass 6, count 0 2006.246.08:17:50.14#ibcon#about to write, iclass 6, count 0 2006.246.08:17:50.14#ibcon#wrote, iclass 6, count 0 2006.246.08:17:50.14#ibcon#about to read 3, iclass 6, count 0 2006.246.08:17:50.18#ibcon#read 3, iclass 6, count 0 2006.246.08:17:50.18#ibcon#about to read 4, iclass 6, count 0 2006.246.08:17:50.18#ibcon#read 4, iclass 6, count 0 2006.246.08:17:50.18#ibcon#about to read 5, iclass 6, count 0 2006.246.08:17:50.18#ibcon#read 5, iclass 6, count 0 2006.246.08:17:50.18#ibcon#about to read 6, iclass 6, count 0 2006.246.08:17:50.18#ibcon#read 6, iclass 6, count 0 2006.246.08:17:50.18#ibcon#end of sib2, iclass 6, count 0 2006.246.08:17:50.18#ibcon#*after write, iclass 6, count 0 2006.246.08:17:50.18#ibcon#*before return 0, iclass 6, count 0 2006.246.08:17:50.18#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:17:50.18#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.246.08:17:50.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:17:50.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:17:50.18$vc4f8/va=7,7 2006.246.08:17:50.18#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.246.08:17:50.18#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.246.08:17:50.18#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:50.18#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:17:50.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:17:50.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:17:50.24#ibcon#enter wrdev, iclass 10, count 2 2006.246.08:17:50.24#ibcon#first serial, iclass 10, count 2 2006.246.08:17:50.24#ibcon#enter sib2, iclass 10, count 2 2006.246.08:17:50.24#ibcon#flushed, iclass 10, count 2 2006.246.08:17:50.24#ibcon#about to write, iclass 10, count 2 2006.246.08:17:50.24#ibcon#wrote, iclass 10, count 2 2006.246.08:17:50.24#ibcon#about to read 3, iclass 10, count 2 2006.246.08:17:50.26#ibcon#read 3, iclass 10, count 2 2006.246.08:17:50.26#ibcon#about to read 4, iclass 10, count 2 2006.246.08:17:50.26#ibcon#read 4, iclass 10, count 2 2006.246.08:17:50.26#ibcon#about to read 5, iclass 10, count 2 2006.246.08:17:50.26#ibcon#read 5, iclass 10, count 2 2006.246.08:17:50.26#ibcon#about to read 6, iclass 10, count 2 2006.246.08:17:50.26#ibcon#read 6, iclass 10, count 2 2006.246.08:17:50.26#ibcon#end of sib2, iclass 10, count 2 2006.246.08:17:50.26#ibcon#*mode == 0, iclass 10, count 2 2006.246.08:17:50.26#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.246.08:17:50.26#ibcon#[25=AT07-07\r\n] 2006.246.08:17:50.26#ibcon#*before write, iclass 10, count 2 2006.246.08:17:50.26#ibcon#enter sib2, iclass 10, count 2 2006.246.08:17:50.26#ibcon#flushed, iclass 10, count 2 2006.246.08:17:50.26#ibcon#about to write, iclass 10, count 2 2006.246.08:17:50.26#ibcon#wrote, iclass 10, count 2 2006.246.08:17:50.26#ibcon#about to read 3, iclass 10, count 2 2006.246.08:17:50.29#ibcon#read 3, iclass 10, count 2 2006.246.08:17:50.29#ibcon#about to read 4, iclass 10, count 2 2006.246.08:17:50.29#ibcon#read 4, iclass 10, count 2 2006.246.08:17:50.29#ibcon#about to read 5, iclass 10, count 2 2006.246.08:17:50.29#ibcon#read 5, iclass 10, count 2 2006.246.08:17:50.29#ibcon#about to read 6, iclass 10, count 2 2006.246.08:17:50.29#ibcon#read 6, iclass 10, count 2 2006.246.08:17:50.29#ibcon#end of sib2, iclass 10, count 2 2006.246.08:17:50.29#ibcon#*after write, iclass 10, count 2 2006.246.08:17:50.29#ibcon#*before return 0, iclass 10, count 2 2006.246.08:17:50.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:17:50.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.246.08:17:50.29#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.246.08:17:50.29#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:50.29#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:17:50.41#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:17:50.41#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:17:50.41#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:17:50.41#ibcon#first serial, iclass 10, count 0 2006.246.08:17:50.41#ibcon#enter sib2, iclass 10, count 0 2006.246.08:17:50.41#ibcon#flushed, iclass 10, count 0 2006.246.08:17:50.41#ibcon#about to write, iclass 10, count 0 2006.246.08:17:50.41#ibcon#wrote, iclass 10, count 0 2006.246.08:17:50.41#ibcon#about to read 3, iclass 10, count 0 2006.246.08:17:50.43#ibcon#read 3, iclass 10, count 0 2006.246.08:17:50.43#ibcon#about to read 4, iclass 10, count 0 2006.246.08:17:50.43#ibcon#read 4, iclass 10, count 0 2006.246.08:17:50.43#ibcon#about to read 5, iclass 10, count 0 2006.246.08:17:50.43#ibcon#read 5, iclass 10, count 0 2006.246.08:17:50.43#ibcon#about to read 6, iclass 10, count 0 2006.246.08:17:50.43#ibcon#read 6, iclass 10, count 0 2006.246.08:17:50.43#ibcon#end of sib2, iclass 10, count 0 2006.246.08:17:50.43#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:17:50.43#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:17:50.43#ibcon#[25=USB\r\n] 2006.246.08:17:50.43#ibcon#*before write, iclass 10, count 0 2006.246.08:17:50.43#ibcon#enter sib2, iclass 10, count 0 2006.246.08:17:50.43#ibcon#flushed, iclass 10, count 0 2006.246.08:17:50.43#ibcon#about to write, iclass 10, count 0 2006.246.08:17:50.43#ibcon#wrote, iclass 10, count 0 2006.246.08:17:50.43#ibcon#about to read 3, iclass 10, count 0 2006.246.08:17:50.46#ibcon#read 3, iclass 10, count 0 2006.246.08:17:50.46#ibcon#about to read 4, iclass 10, count 0 2006.246.08:17:50.46#ibcon#read 4, iclass 10, count 0 2006.246.08:17:50.46#ibcon#about to read 5, iclass 10, count 0 2006.246.08:17:50.46#ibcon#read 5, iclass 10, count 0 2006.246.08:17:50.46#ibcon#about to read 6, iclass 10, count 0 2006.246.08:17:50.46#ibcon#read 6, iclass 10, count 0 2006.246.08:17:50.46#ibcon#end of sib2, iclass 10, count 0 2006.246.08:17:50.46#ibcon#*after write, iclass 10, count 0 2006.246.08:17:50.46#ibcon#*before return 0, iclass 10, count 0 2006.246.08:17:50.46#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:17:50.46#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.246.08:17:50.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:17:50.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:17:50.46$vc4f8/valo=8,852.99 2006.246.08:17:50.46#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.246.08:17:50.46#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.246.08:17:50.46#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:50.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:17:50.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:17:50.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:17:50.46#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:17:50.46#ibcon#first serial, iclass 12, count 0 2006.246.08:17:50.46#ibcon#enter sib2, iclass 12, count 0 2006.246.08:17:50.46#ibcon#flushed, iclass 12, count 0 2006.246.08:17:50.46#ibcon#about to write, iclass 12, count 0 2006.246.08:17:50.46#ibcon#wrote, iclass 12, count 0 2006.246.08:17:50.46#ibcon#about to read 3, iclass 12, count 0 2006.246.08:17:50.48#ibcon#read 3, iclass 12, count 0 2006.246.08:17:50.48#ibcon#about to read 4, iclass 12, count 0 2006.246.08:17:50.48#ibcon#read 4, iclass 12, count 0 2006.246.08:17:50.48#ibcon#about to read 5, iclass 12, count 0 2006.246.08:17:50.48#ibcon#read 5, iclass 12, count 0 2006.246.08:17:50.48#ibcon#about to read 6, iclass 12, count 0 2006.246.08:17:50.48#ibcon#read 6, iclass 12, count 0 2006.246.08:17:50.48#ibcon#end of sib2, iclass 12, count 0 2006.246.08:17:50.48#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:17:50.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:17:50.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:17:50.48#ibcon#*before write, iclass 12, count 0 2006.246.08:17:50.48#ibcon#enter sib2, iclass 12, count 0 2006.246.08:17:50.48#ibcon#flushed, iclass 12, count 0 2006.246.08:17:50.48#ibcon#about to write, iclass 12, count 0 2006.246.08:17:50.48#ibcon#wrote, iclass 12, count 0 2006.246.08:17:50.48#ibcon#about to read 3, iclass 12, count 0 2006.246.08:17:50.52#ibcon#read 3, iclass 12, count 0 2006.246.08:17:50.52#ibcon#about to read 4, iclass 12, count 0 2006.246.08:17:50.52#ibcon#read 4, iclass 12, count 0 2006.246.08:17:50.52#ibcon#about to read 5, iclass 12, count 0 2006.246.08:17:50.52#ibcon#read 5, iclass 12, count 0 2006.246.08:17:50.52#ibcon#about to read 6, iclass 12, count 0 2006.246.08:17:50.52#ibcon#read 6, iclass 12, count 0 2006.246.08:17:50.52#ibcon#end of sib2, iclass 12, count 0 2006.246.08:17:50.52#ibcon#*after write, iclass 12, count 0 2006.246.08:17:50.52#ibcon#*before return 0, iclass 12, count 0 2006.246.08:17:50.52#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:17:50.52#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.246.08:17:50.52#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:17:50.52#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:17:50.52$vc4f8/va=8,8 2006.246.08:17:50.52#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.246.08:17:50.52#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.246.08:17:50.52#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:50.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:17:50.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:17:50.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:17:50.58#ibcon#enter wrdev, iclass 14, count 2 2006.246.08:17:50.58#ibcon#first serial, iclass 14, count 2 2006.246.08:17:50.58#ibcon#enter sib2, iclass 14, count 2 2006.246.08:17:50.58#ibcon#flushed, iclass 14, count 2 2006.246.08:17:50.58#ibcon#about to write, iclass 14, count 2 2006.246.08:17:50.58#ibcon#wrote, iclass 14, count 2 2006.246.08:17:50.58#ibcon#about to read 3, iclass 14, count 2 2006.246.08:17:50.60#ibcon#read 3, iclass 14, count 2 2006.246.08:17:50.60#ibcon#about to read 4, iclass 14, count 2 2006.246.08:17:50.60#ibcon#read 4, iclass 14, count 2 2006.246.08:17:50.60#ibcon#about to read 5, iclass 14, count 2 2006.246.08:17:50.60#ibcon#read 5, iclass 14, count 2 2006.246.08:17:50.60#ibcon#about to read 6, iclass 14, count 2 2006.246.08:17:50.60#ibcon#read 6, iclass 14, count 2 2006.246.08:17:50.60#ibcon#end of sib2, iclass 14, count 2 2006.246.08:17:50.60#ibcon#*mode == 0, iclass 14, count 2 2006.246.08:17:50.60#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.246.08:17:50.60#ibcon#[25=AT08-08\r\n] 2006.246.08:17:50.60#ibcon#*before write, iclass 14, count 2 2006.246.08:17:50.60#ibcon#enter sib2, iclass 14, count 2 2006.246.08:17:50.60#ibcon#flushed, iclass 14, count 2 2006.246.08:17:50.60#ibcon#about to write, iclass 14, count 2 2006.246.08:17:50.60#ibcon#wrote, iclass 14, count 2 2006.246.08:17:50.60#ibcon#about to read 3, iclass 14, count 2 2006.246.08:17:50.63#ibcon#read 3, iclass 14, count 2 2006.246.08:17:50.63#ibcon#about to read 4, iclass 14, count 2 2006.246.08:17:50.63#ibcon#read 4, iclass 14, count 2 2006.246.08:17:50.63#ibcon#about to read 5, iclass 14, count 2 2006.246.08:17:50.63#ibcon#read 5, iclass 14, count 2 2006.246.08:17:50.63#ibcon#about to read 6, iclass 14, count 2 2006.246.08:17:50.63#ibcon#read 6, iclass 14, count 2 2006.246.08:17:50.63#ibcon#end of sib2, iclass 14, count 2 2006.246.08:17:50.63#ibcon#*after write, iclass 14, count 2 2006.246.08:17:50.63#ibcon#*before return 0, iclass 14, count 2 2006.246.08:17:50.63#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:17:50.63#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.246.08:17:50.63#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.246.08:17:50.63#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:50.63#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:17:50.75#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:17:50.75#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:17:50.75#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:17:50.75#ibcon#first serial, iclass 14, count 0 2006.246.08:17:50.75#ibcon#enter sib2, iclass 14, count 0 2006.246.08:17:50.75#ibcon#flushed, iclass 14, count 0 2006.246.08:17:50.75#ibcon#about to write, iclass 14, count 0 2006.246.08:17:50.75#ibcon#wrote, iclass 14, count 0 2006.246.08:17:50.75#ibcon#about to read 3, iclass 14, count 0 2006.246.08:17:50.77#ibcon#read 3, iclass 14, count 0 2006.246.08:17:50.77#ibcon#about to read 4, iclass 14, count 0 2006.246.08:17:50.77#ibcon#read 4, iclass 14, count 0 2006.246.08:17:50.77#ibcon#about to read 5, iclass 14, count 0 2006.246.08:17:50.77#ibcon#read 5, iclass 14, count 0 2006.246.08:17:50.77#ibcon#about to read 6, iclass 14, count 0 2006.246.08:17:50.77#ibcon#read 6, iclass 14, count 0 2006.246.08:17:50.77#ibcon#end of sib2, iclass 14, count 0 2006.246.08:17:50.77#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:17:50.77#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:17:50.77#ibcon#[25=USB\r\n] 2006.246.08:17:50.77#ibcon#*before write, iclass 14, count 0 2006.246.08:17:50.77#ibcon#enter sib2, iclass 14, count 0 2006.246.08:17:50.77#ibcon#flushed, iclass 14, count 0 2006.246.08:17:50.77#ibcon#about to write, iclass 14, count 0 2006.246.08:17:50.77#ibcon#wrote, iclass 14, count 0 2006.246.08:17:50.77#ibcon#about to read 3, iclass 14, count 0 2006.246.08:17:50.80#ibcon#read 3, iclass 14, count 0 2006.246.08:17:50.80#ibcon#about to read 4, iclass 14, count 0 2006.246.08:17:50.80#ibcon#read 4, iclass 14, count 0 2006.246.08:17:50.80#ibcon#about to read 5, iclass 14, count 0 2006.246.08:17:50.80#ibcon#read 5, iclass 14, count 0 2006.246.08:17:50.80#ibcon#about to read 6, iclass 14, count 0 2006.246.08:17:50.80#ibcon#read 6, iclass 14, count 0 2006.246.08:17:50.80#ibcon#end of sib2, iclass 14, count 0 2006.246.08:17:50.80#ibcon#*after write, iclass 14, count 0 2006.246.08:17:50.80#ibcon#*before return 0, iclass 14, count 0 2006.246.08:17:50.80#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:17:50.80#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.246.08:17:50.80#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:17:50.80#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:17:50.80$vc4f8/vblo=1,632.99 2006.246.08:17:50.80#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.246.08:17:50.80#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.246.08:17:50.80#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:50.80#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:17:50.80#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:17:50.80#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:17:50.80#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:17:50.80#ibcon#first serial, iclass 16, count 0 2006.246.08:17:50.80#ibcon#enter sib2, iclass 16, count 0 2006.246.08:17:50.80#ibcon#flushed, iclass 16, count 0 2006.246.08:17:50.80#ibcon#about to write, iclass 16, count 0 2006.246.08:17:50.80#ibcon#wrote, iclass 16, count 0 2006.246.08:17:50.80#ibcon#about to read 3, iclass 16, count 0 2006.246.08:17:50.82#ibcon#read 3, iclass 16, count 0 2006.246.08:17:50.82#ibcon#about to read 4, iclass 16, count 0 2006.246.08:17:50.82#ibcon#read 4, iclass 16, count 0 2006.246.08:17:50.82#ibcon#about to read 5, iclass 16, count 0 2006.246.08:17:50.82#ibcon#read 5, iclass 16, count 0 2006.246.08:17:50.82#ibcon#about to read 6, iclass 16, count 0 2006.246.08:17:50.82#ibcon#read 6, iclass 16, count 0 2006.246.08:17:50.82#ibcon#end of sib2, iclass 16, count 0 2006.246.08:17:50.82#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:17:50.82#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:17:50.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:17:50.82#ibcon#*before write, iclass 16, count 0 2006.246.08:17:50.82#ibcon#enter sib2, iclass 16, count 0 2006.246.08:17:50.82#ibcon#flushed, iclass 16, count 0 2006.246.08:17:50.82#ibcon#about to write, iclass 16, count 0 2006.246.08:17:50.82#ibcon#wrote, iclass 16, count 0 2006.246.08:17:50.82#ibcon#about to read 3, iclass 16, count 0 2006.246.08:17:50.86#ibcon#read 3, iclass 16, count 0 2006.246.08:17:50.86#ibcon#about to read 4, iclass 16, count 0 2006.246.08:17:50.86#ibcon#read 4, iclass 16, count 0 2006.246.08:17:50.86#ibcon#about to read 5, iclass 16, count 0 2006.246.08:17:50.86#ibcon#read 5, iclass 16, count 0 2006.246.08:17:50.86#ibcon#about to read 6, iclass 16, count 0 2006.246.08:17:50.86#ibcon#read 6, iclass 16, count 0 2006.246.08:17:50.86#ibcon#end of sib2, iclass 16, count 0 2006.246.08:17:50.86#ibcon#*after write, iclass 16, count 0 2006.246.08:17:50.86#ibcon#*before return 0, iclass 16, count 0 2006.246.08:17:50.86#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:17:50.86#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.246.08:17:50.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:17:50.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:17:50.86$vc4f8/vb=1,4 2006.246.08:17:50.86#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.246.08:17:50.86#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.246.08:17:50.86#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:50.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:17:50.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:17:50.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:17:50.86#ibcon#enter wrdev, iclass 18, count 2 2006.246.08:17:50.86#ibcon#first serial, iclass 18, count 2 2006.246.08:17:50.86#ibcon#enter sib2, iclass 18, count 2 2006.246.08:17:50.86#ibcon#flushed, iclass 18, count 2 2006.246.08:17:50.86#ibcon#about to write, iclass 18, count 2 2006.246.08:17:50.86#ibcon#wrote, iclass 18, count 2 2006.246.08:17:50.86#ibcon#about to read 3, iclass 18, count 2 2006.246.08:17:50.88#ibcon#read 3, iclass 18, count 2 2006.246.08:17:50.88#ibcon#about to read 4, iclass 18, count 2 2006.246.08:17:50.88#ibcon#read 4, iclass 18, count 2 2006.246.08:17:50.88#ibcon#about to read 5, iclass 18, count 2 2006.246.08:17:50.88#ibcon#read 5, iclass 18, count 2 2006.246.08:17:50.88#ibcon#about to read 6, iclass 18, count 2 2006.246.08:17:50.88#ibcon#read 6, iclass 18, count 2 2006.246.08:17:50.88#ibcon#end of sib2, iclass 18, count 2 2006.246.08:17:50.88#ibcon#*mode == 0, iclass 18, count 2 2006.246.08:17:50.88#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.246.08:17:50.88#ibcon#[27=AT01-04\r\n] 2006.246.08:17:50.88#ibcon#*before write, iclass 18, count 2 2006.246.08:17:50.88#ibcon#enter sib2, iclass 18, count 2 2006.246.08:17:50.88#ibcon#flushed, iclass 18, count 2 2006.246.08:17:50.88#ibcon#about to write, iclass 18, count 2 2006.246.08:17:50.88#ibcon#wrote, iclass 18, count 2 2006.246.08:17:50.88#ibcon#about to read 3, iclass 18, count 2 2006.246.08:17:50.91#ibcon#read 3, iclass 18, count 2 2006.246.08:17:50.91#ibcon#about to read 4, iclass 18, count 2 2006.246.08:17:50.91#ibcon#read 4, iclass 18, count 2 2006.246.08:17:50.91#ibcon#about to read 5, iclass 18, count 2 2006.246.08:17:50.91#ibcon#read 5, iclass 18, count 2 2006.246.08:17:50.91#ibcon#about to read 6, iclass 18, count 2 2006.246.08:17:50.91#ibcon#read 6, iclass 18, count 2 2006.246.08:17:50.91#ibcon#end of sib2, iclass 18, count 2 2006.246.08:17:50.91#ibcon#*after write, iclass 18, count 2 2006.246.08:17:50.91#ibcon#*before return 0, iclass 18, count 2 2006.246.08:17:50.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:17:50.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.246.08:17:50.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.246.08:17:50.91#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:50.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:17:51.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:17:51.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:17:51.03#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:17:51.03#ibcon#first serial, iclass 18, count 0 2006.246.08:17:51.03#ibcon#enter sib2, iclass 18, count 0 2006.246.08:17:51.03#ibcon#flushed, iclass 18, count 0 2006.246.08:17:51.03#ibcon#about to write, iclass 18, count 0 2006.246.08:17:51.03#ibcon#wrote, iclass 18, count 0 2006.246.08:17:51.03#ibcon#about to read 3, iclass 18, count 0 2006.246.08:17:51.05#ibcon#read 3, iclass 18, count 0 2006.246.08:17:51.05#ibcon#about to read 4, iclass 18, count 0 2006.246.08:17:51.05#ibcon#read 4, iclass 18, count 0 2006.246.08:17:51.05#ibcon#about to read 5, iclass 18, count 0 2006.246.08:17:51.05#ibcon#read 5, iclass 18, count 0 2006.246.08:17:51.05#ibcon#about to read 6, iclass 18, count 0 2006.246.08:17:51.05#ibcon#read 6, iclass 18, count 0 2006.246.08:17:51.05#ibcon#end of sib2, iclass 18, count 0 2006.246.08:17:51.05#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:17:51.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:17:51.05#ibcon#[27=USB\r\n] 2006.246.08:17:51.05#ibcon#*before write, iclass 18, count 0 2006.246.08:17:51.05#ibcon#enter sib2, iclass 18, count 0 2006.246.08:17:51.05#ibcon#flushed, iclass 18, count 0 2006.246.08:17:51.05#ibcon#about to write, iclass 18, count 0 2006.246.08:17:51.05#ibcon#wrote, iclass 18, count 0 2006.246.08:17:51.05#ibcon#about to read 3, iclass 18, count 0 2006.246.08:17:51.08#ibcon#read 3, iclass 18, count 0 2006.246.08:17:51.08#ibcon#about to read 4, iclass 18, count 0 2006.246.08:17:51.08#ibcon#read 4, iclass 18, count 0 2006.246.08:17:51.08#ibcon#about to read 5, iclass 18, count 0 2006.246.08:17:51.08#ibcon#read 5, iclass 18, count 0 2006.246.08:17:51.08#ibcon#about to read 6, iclass 18, count 0 2006.246.08:17:51.08#ibcon#read 6, iclass 18, count 0 2006.246.08:17:51.08#ibcon#end of sib2, iclass 18, count 0 2006.246.08:17:51.08#ibcon#*after write, iclass 18, count 0 2006.246.08:17:51.08#ibcon#*before return 0, iclass 18, count 0 2006.246.08:17:51.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:17:51.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.246.08:17:51.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:17:51.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:17:51.08$vc4f8/vblo=2,640.99 2006.246.08:17:51.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.246.08:17:51.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.246.08:17:51.08#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:51.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:51.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:51.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:51.08#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:17:51.08#ibcon#first serial, iclass 20, count 0 2006.246.08:17:51.08#ibcon#enter sib2, iclass 20, count 0 2006.246.08:17:51.08#ibcon#flushed, iclass 20, count 0 2006.246.08:17:51.08#ibcon#about to write, iclass 20, count 0 2006.246.08:17:51.08#ibcon#wrote, iclass 20, count 0 2006.246.08:17:51.08#ibcon#about to read 3, iclass 20, count 0 2006.246.08:17:51.10#ibcon#read 3, iclass 20, count 0 2006.246.08:17:51.10#ibcon#about to read 4, iclass 20, count 0 2006.246.08:17:51.10#ibcon#read 4, iclass 20, count 0 2006.246.08:17:51.10#ibcon#about to read 5, iclass 20, count 0 2006.246.08:17:51.10#ibcon#read 5, iclass 20, count 0 2006.246.08:17:51.10#ibcon#about to read 6, iclass 20, count 0 2006.246.08:17:51.10#ibcon#read 6, iclass 20, count 0 2006.246.08:17:51.10#ibcon#end of sib2, iclass 20, count 0 2006.246.08:17:51.10#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:17:51.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:17:51.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:17:51.10#ibcon#*before write, iclass 20, count 0 2006.246.08:17:51.10#ibcon#enter sib2, iclass 20, count 0 2006.246.08:17:51.10#ibcon#flushed, iclass 20, count 0 2006.246.08:17:51.10#ibcon#about to write, iclass 20, count 0 2006.246.08:17:51.10#ibcon#wrote, iclass 20, count 0 2006.246.08:17:51.10#ibcon#about to read 3, iclass 20, count 0 2006.246.08:17:51.14#ibcon#read 3, iclass 20, count 0 2006.246.08:17:51.14#ibcon#about to read 4, iclass 20, count 0 2006.246.08:17:51.14#ibcon#read 4, iclass 20, count 0 2006.246.08:17:51.14#ibcon#about to read 5, iclass 20, count 0 2006.246.08:17:51.14#ibcon#read 5, iclass 20, count 0 2006.246.08:17:51.14#ibcon#about to read 6, iclass 20, count 0 2006.246.08:17:51.14#ibcon#read 6, iclass 20, count 0 2006.246.08:17:51.14#ibcon#end of sib2, iclass 20, count 0 2006.246.08:17:51.14#ibcon#*after write, iclass 20, count 0 2006.246.08:17:51.14#ibcon#*before return 0, iclass 20, count 0 2006.246.08:17:51.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:51.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.246.08:17:51.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:17:51.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:17:51.14$vc4f8/vb=2,4 2006.246.08:17:51.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.246.08:17:51.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.246.08:17:51.14#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:51.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:51.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:51.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:51.20#ibcon#enter wrdev, iclass 22, count 2 2006.246.08:17:51.20#ibcon#first serial, iclass 22, count 2 2006.246.08:17:51.20#ibcon#enter sib2, iclass 22, count 2 2006.246.08:17:51.20#ibcon#flushed, iclass 22, count 2 2006.246.08:17:51.20#ibcon#about to write, iclass 22, count 2 2006.246.08:17:51.20#ibcon#wrote, iclass 22, count 2 2006.246.08:17:51.20#ibcon#about to read 3, iclass 22, count 2 2006.246.08:17:51.22#ibcon#read 3, iclass 22, count 2 2006.246.08:17:51.22#ibcon#about to read 4, iclass 22, count 2 2006.246.08:17:51.22#ibcon#read 4, iclass 22, count 2 2006.246.08:17:51.22#ibcon#about to read 5, iclass 22, count 2 2006.246.08:17:51.22#ibcon#read 5, iclass 22, count 2 2006.246.08:17:51.22#ibcon#about to read 6, iclass 22, count 2 2006.246.08:17:51.22#ibcon#read 6, iclass 22, count 2 2006.246.08:17:51.22#ibcon#end of sib2, iclass 22, count 2 2006.246.08:17:51.22#ibcon#*mode == 0, iclass 22, count 2 2006.246.08:17:51.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.246.08:17:51.22#ibcon#[27=AT02-04\r\n] 2006.246.08:17:51.22#ibcon#*before write, iclass 22, count 2 2006.246.08:17:51.22#ibcon#enter sib2, iclass 22, count 2 2006.246.08:17:51.22#ibcon#flushed, iclass 22, count 2 2006.246.08:17:51.22#ibcon#about to write, iclass 22, count 2 2006.246.08:17:51.22#ibcon#wrote, iclass 22, count 2 2006.246.08:17:51.22#ibcon#about to read 3, iclass 22, count 2 2006.246.08:17:51.25#ibcon#read 3, iclass 22, count 2 2006.246.08:17:51.25#ibcon#about to read 4, iclass 22, count 2 2006.246.08:17:51.25#ibcon#read 4, iclass 22, count 2 2006.246.08:17:51.25#ibcon#about to read 5, iclass 22, count 2 2006.246.08:17:51.25#ibcon#read 5, iclass 22, count 2 2006.246.08:17:51.25#ibcon#about to read 6, iclass 22, count 2 2006.246.08:17:51.25#ibcon#read 6, iclass 22, count 2 2006.246.08:17:51.25#ibcon#end of sib2, iclass 22, count 2 2006.246.08:17:51.25#ibcon#*after write, iclass 22, count 2 2006.246.08:17:51.25#ibcon#*before return 0, iclass 22, count 2 2006.246.08:17:51.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:51.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.246.08:17:51.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.246.08:17:51.25#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:51.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:51.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:51.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:51.37#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:17:51.37#ibcon#first serial, iclass 22, count 0 2006.246.08:17:51.37#ibcon#enter sib2, iclass 22, count 0 2006.246.08:17:51.37#ibcon#flushed, iclass 22, count 0 2006.246.08:17:51.37#ibcon#about to write, iclass 22, count 0 2006.246.08:17:51.37#ibcon#wrote, iclass 22, count 0 2006.246.08:17:51.37#ibcon#about to read 3, iclass 22, count 0 2006.246.08:17:51.39#ibcon#read 3, iclass 22, count 0 2006.246.08:17:51.39#ibcon#about to read 4, iclass 22, count 0 2006.246.08:17:51.39#ibcon#read 4, iclass 22, count 0 2006.246.08:17:51.39#ibcon#about to read 5, iclass 22, count 0 2006.246.08:17:51.39#ibcon#read 5, iclass 22, count 0 2006.246.08:17:51.39#ibcon#about to read 6, iclass 22, count 0 2006.246.08:17:51.39#ibcon#read 6, iclass 22, count 0 2006.246.08:17:51.39#ibcon#end of sib2, iclass 22, count 0 2006.246.08:17:51.39#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:17:51.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:17:51.39#ibcon#[27=USB\r\n] 2006.246.08:17:51.39#ibcon#*before write, iclass 22, count 0 2006.246.08:17:51.39#ibcon#enter sib2, iclass 22, count 0 2006.246.08:17:51.39#ibcon#flushed, iclass 22, count 0 2006.246.08:17:51.39#ibcon#about to write, iclass 22, count 0 2006.246.08:17:51.39#ibcon#wrote, iclass 22, count 0 2006.246.08:17:51.39#ibcon#about to read 3, iclass 22, count 0 2006.246.08:17:51.42#ibcon#read 3, iclass 22, count 0 2006.246.08:17:51.42#ibcon#about to read 4, iclass 22, count 0 2006.246.08:17:51.42#ibcon#read 4, iclass 22, count 0 2006.246.08:17:51.42#ibcon#about to read 5, iclass 22, count 0 2006.246.08:17:51.42#ibcon#read 5, iclass 22, count 0 2006.246.08:17:51.42#ibcon#about to read 6, iclass 22, count 0 2006.246.08:17:51.42#ibcon#read 6, iclass 22, count 0 2006.246.08:17:51.42#ibcon#end of sib2, iclass 22, count 0 2006.246.08:17:51.42#ibcon#*after write, iclass 22, count 0 2006.246.08:17:51.42#ibcon#*before return 0, iclass 22, count 0 2006.246.08:17:51.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:51.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.246.08:17:51.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:17:51.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:17:51.42$vc4f8/vblo=3,656.99 2006.246.08:17:51.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.08:17:51.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.08:17:51.42#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:51.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:51.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:51.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:51.42#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:17:51.42#ibcon#first serial, iclass 24, count 0 2006.246.08:17:51.42#ibcon#enter sib2, iclass 24, count 0 2006.246.08:17:51.42#ibcon#flushed, iclass 24, count 0 2006.246.08:17:51.42#ibcon#about to write, iclass 24, count 0 2006.246.08:17:51.42#ibcon#wrote, iclass 24, count 0 2006.246.08:17:51.42#ibcon#about to read 3, iclass 24, count 0 2006.246.08:17:51.44#ibcon#read 3, iclass 24, count 0 2006.246.08:17:51.44#ibcon#about to read 4, iclass 24, count 0 2006.246.08:17:51.44#ibcon#read 4, iclass 24, count 0 2006.246.08:17:51.44#ibcon#about to read 5, iclass 24, count 0 2006.246.08:17:51.44#ibcon#read 5, iclass 24, count 0 2006.246.08:17:51.44#ibcon#about to read 6, iclass 24, count 0 2006.246.08:17:51.44#ibcon#read 6, iclass 24, count 0 2006.246.08:17:51.44#ibcon#end of sib2, iclass 24, count 0 2006.246.08:17:51.44#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:17:51.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:17:51.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:17:51.44#ibcon#*before write, iclass 24, count 0 2006.246.08:17:51.44#ibcon#enter sib2, iclass 24, count 0 2006.246.08:17:51.44#ibcon#flushed, iclass 24, count 0 2006.246.08:17:51.44#ibcon#about to write, iclass 24, count 0 2006.246.08:17:51.44#ibcon#wrote, iclass 24, count 0 2006.246.08:17:51.44#ibcon#about to read 3, iclass 24, count 0 2006.246.08:17:51.48#ibcon#read 3, iclass 24, count 0 2006.246.08:17:51.48#ibcon#about to read 4, iclass 24, count 0 2006.246.08:17:51.48#ibcon#read 4, iclass 24, count 0 2006.246.08:17:51.48#ibcon#about to read 5, iclass 24, count 0 2006.246.08:17:51.48#ibcon#read 5, iclass 24, count 0 2006.246.08:17:51.48#ibcon#about to read 6, iclass 24, count 0 2006.246.08:17:51.48#ibcon#read 6, iclass 24, count 0 2006.246.08:17:51.48#ibcon#end of sib2, iclass 24, count 0 2006.246.08:17:51.48#ibcon#*after write, iclass 24, count 0 2006.246.08:17:51.48#ibcon#*before return 0, iclass 24, count 0 2006.246.08:17:51.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:51.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:17:51.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:17:51.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:17:51.48$vc4f8/vb=3,4 2006.246.08:17:51.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.246.08:17:51.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.246.08:17:51.48#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:51.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:51.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:51.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:51.54#ibcon#enter wrdev, iclass 26, count 2 2006.246.08:17:51.54#ibcon#first serial, iclass 26, count 2 2006.246.08:17:51.54#ibcon#enter sib2, iclass 26, count 2 2006.246.08:17:51.54#ibcon#flushed, iclass 26, count 2 2006.246.08:17:51.54#ibcon#about to write, iclass 26, count 2 2006.246.08:17:51.54#ibcon#wrote, iclass 26, count 2 2006.246.08:17:51.54#ibcon#about to read 3, iclass 26, count 2 2006.246.08:17:51.56#ibcon#read 3, iclass 26, count 2 2006.246.08:17:51.56#ibcon#about to read 4, iclass 26, count 2 2006.246.08:17:51.56#ibcon#read 4, iclass 26, count 2 2006.246.08:17:51.56#ibcon#about to read 5, iclass 26, count 2 2006.246.08:17:51.56#ibcon#read 5, iclass 26, count 2 2006.246.08:17:51.56#ibcon#about to read 6, iclass 26, count 2 2006.246.08:17:51.56#ibcon#read 6, iclass 26, count 2 2006.246.08:17:51.56#ibcon#end of sib2, iclass 26, count 2 2006.246.08:17:51.56#ibcon#*mode == 0, iclass 26, count 2 2006.246.08:17:51.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.246.08:17:51.56#ibcon#[27=AT03-04\r\n] 2006.246.08:17:51.56#ibcon#*before write, iclass 26, count 2 2006.246.08:17:51.56#ibcon#enter sib2, iclass 26, count 2 2006.246.08:17:51.56#ibcon#flushed, iclass 26, count 2 2006.246.08:17:51.56#ibcon#about to write, iclass 26, count 2 2006.246.08:17:51.56#ibcon#wrote, iclass 26, count 2 2006.246.08:17:51.56#ibcon#about to read 3, iclass 26, count 2 2006.246.08:17:51.59#ibcon#read 3, iclass 26, count 2 2006.246.08:17:51.59#ibcon#about to read 4, iclass 26, count 2 2006.246.08:17:51.59#ibcon#read 4, iclass 26, count 2 2006.246.08:17:51.59#ibcon#about to read 5, iclass 26, count 2 2006.246.08:17:51.59#ibcon#read 5, iclass 26, count 2 2006.246.08:17:51.59#ibcon#about to read 6, iclass 26, count 2 2006.246.08:17:51.59#ibcon#read 6, iclass 26, count 2 2006.246.08:17:51.59#ibcon#end of sib2, iclass 26, count 2 2006.246.08:17:51.59#ibcon#*after write, iclass 26, count 2 2006.246.08:17:51.59#ibcon#*before return 0, iclass 26, count 2 2006.246.08:17:51.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:51.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.246.08:17:51.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.246.08:17:51.59#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:51.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:51.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:51.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:51.71#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:17:51.71#ibcon#first serial, iclass 26, count 0 2006.246.08:17:51.71#ibcon#enter sib2, iclass 26, count 0 2006.246.08:17:51.71#ibcon#flushed, iclass 26, count 0 2006.246.08:17:51.71#ibcon#about to write, iclass 26, count 0 2006.246.08:17:51.71#ibcon#wrote, iclass 26, count 0 2006.246.08:17:51.71#ibcon#about to read 3, iclass 26, count 0 2006.246.08:17:51.73#ibcon#read 3, iclass 26, count 0 2006.246.08:17:51.73#ibcon#about to read 4, iclass 26, count 0 2006.246.08:17:51.73#ibcon#read 4, iclass 26, count 0 2006.246.08:17:51.73#ibcon#about to read 5, iclass 26, count 0 2006.246.08:17:51.73#ibcon#read 5, iclass 26, count 0 2006.246.08:17:51.73#ibcon#about to read 6, iclass 26, count 0 2006.246.08:17:51.73#ibcon#read 6, iclass 26, count 0 2006.246.08:17:51.73#ibcon#end of sib2, iclass 26, count 0 2006.246.08:17:51.73#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:17:51.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:17:51.73#ibcon#[27=USB\r\n] 2006.246.08:17:51.73#ibcon#*before write, iclass 26, count 0 2006.246.08:17:51.73#ibcon#enter sib2, iclass 26, count 0 2006.246.08:17:51.73#ibcon#flushed, iclass 26, count 0 2006.246.08:17:51.73#ibcon#about to write, iclass 26, count 0 2006.246.08:17:51.73#ibcon#wrote, iclass 26, count 0 2006.246.08:17:51.73#ibcon#about to read 3, iclass 26, count 0 2006.246.08:17:51.76#ibcon#read 3, iclass 26, count 0 2006.246.08:17:51.76#ibcon#about to read 4, iclass 26, count 0 2006.246.08:17:51.76#ibcon#read 4, iclass 26, count 0 2006.246.08:17:51.76#ibcon#about to read 5, iclass 26, count 0 2006.246.08:17:51.76#ibcon#read 5, iclass 26, count 0 2006.246.08:17:51.76#ibcon#about to read 6, iclass 26, count 0 2006.246.08:17:51.76#ibcon#read 6, iclass 26, count 0 2006.246.08:17:51.76#ibcon#end of sib2, iclass 26, count 0 2006.246.08:17:51.76#ibcon#*after write, iclass 26, count 0 2006.246.08:17:51.76#ibcon#*before return 0, iclass 26, count 0 2006.246.08:17:51.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:51.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.246.08:17:51.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:17:51.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:17:51.76$vc4f8/vblo=4,712.99 2006.246.08:17:51.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.246.08:17:51.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.246.08:17:51.76#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:51.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:51.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:51.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:51.76#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:17:51.76#ibcon#first serial, iclass 28, count 0 2006.246.08:17:51.76#ibcon#enter sib2, iclass 28, count 0 2006.246.08:17:51.76#ibcon#flushed, iclass 28, count 0 2006.246.08:17:51.76#ibcon#about to write, iclass 28, count 0 2006.246.08:17:51.76#ibcon#wrote, iclass 28, count 0 2006.246.08:17:51.76#ibcon#about to read 3, iclass 28, count 0 2006.246.08:17:51.78#ibcon#read 3, iclass 28, count 0 2006.246.08:17:51.78#ibcon#about to read 4, iclass 28, count 0 2006.246.08:17:51.78#ibcon#read 4, iclass 28, count 0 2006.246.08:17:51.78#ibcon#about to read 5, iclass 28, count 0 2006.246.08:17:51.78#ibcon#read 5, iclass 28, count 0 2006.246.08:17:51.78#ibcon#about to read 6, iclass 28, count 0 2006.246.08:17:51.78#ibcon#read 6, iclass 28, count 0 2006.246.08:17:51.78#ibcon#end of sib2, iclass 28, count 0 2006.246.08:17:51.78#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:17:51.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:17:51.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:17:51.78#ibcon#*before write, iclass 28, count 0 2006.246.08:17:51.78#ibcon#enter sib2, iclass 28, count 0 2006.246.08:17:51.78#ibcon#flushed, iclass 28, count 0 2006.246.08:17:51.78#ibcon#about to write, iclass 28, count 0 2006.246.08:17:51.78#ibcon#wrote, iclass 28, count 0 2006.246.08:17:51.78#ibcon#about to read 3, iclass 28, count 0 2006.246.08:17:51.82#ibcon#read 3, iclass 28, count 0 2006.246.08:17:51.82#ibcon#about to read 4, iclass 28, count 0 2006.246.08:17:51.82#ibcon#read 4, iclass 28, count 0 2006.246.08:17:51.82#ibcon#about to read 5, iclass 28, count 0 2006.246.08:17:51.82#ibcon#read 5, iclass 28, count 0 2006.246.08:17:51.82#ibcon#about to read 6, iclass 28, count 0 2006.246.08:17:51.82#ibcon#read 6, iclass 28, count 0 2006.246.08:17:51.82#ibcon#end of sib2, iclass 28, count 0 2006.246.08:17:51.82#ibcon#*after write, iclass 28, count 0 2006.246.08:17:51.82#ibcon#*before return 0, iclass 28, count 0 2006.246.08:17:51.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:51.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.246.08:17:51.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:17:51.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:17:51.82$vc4f8/vb=4,4 2006.246.08:17:51.82#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.08:17:51.82#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.08:17:51.82#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:51.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:51.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:51.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:51.89#ibcon#enter wrdev, iclass 30, count 2 2006.246.08:17:51.89#ibcon#first serial, iclass 30, count 2 2006.246.08:17:51.89#ibcon#enter sib2, iclass 30, count 2 2006.246.08:17:51.89#ibcon#flushed, iclass 30, count 2 2006.246.08:17:51.89#ibcon#about to write, iclass 30, count 2 2006.246.08:17:51.89#ibcon#wrote, iclass 30, count 2 2006.246.08:17:51.89#ibcon#about to read 3, iclass 30, count 2 2006.246.08:17:51.90#ibcon#read 3, iclass 30, count 2 2006.246.08:17:51.90#ibcon#about to read 4, iclass 30, count 2 2006.246.08:17:51.90#ibcon#read 4, iclass 30, count 2 2006.246.08:17:51.90#ibcon#about to read 5, iclass 30, count 2 2006.246.08:17:51.90#ibcon#read 5, iclass 30, count 2 2006.246.08:17:51.90#ibcon#about to read 6, iclass 30, count 2 2006.246.08:17:51.90#ibcon#read 6, iclass 30, count 2 2006.246.08:17:51.90#ibcon#end of sib2, iclass 30, count 2 2006.246.08:17:51.90#ibcon#*mode == 0, iclass 30, count 2 2006.246.08:17:51.90#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.08:17:51.90#ibcon#[27=AT04-04\r\n] 2006.246.08:17:51.90#ibcon#*before write, iclass 30, count 2 2006.246.08:17:51.90#ibcon#enter sib2, iclass 30, count 2 2006.246.08:17:51.90#ibcon#flushed, iclass 30, count 2 2006.246.08:17:51.90#ibcon#about to write, iclass 30, count 2 2006.246.08:17:51.90#ibcon#wrote, iclass 30, count 2 2006.246.08:17:51.90#ibcon#about to read 3, iclass 30, count 2 2006.246.08:17:51.93#ibcon#read 3, iclass 30, count 2 2006.246.08:17:51.93#ibcon#about to read 4, iclass 30, count 2 2006.246.08:17:51.93#ibcon#read 4, iclass 30, count 2 2006.246.08:17:51.93#ibcon#about to read 5, iclass 30, count 2 2006.246.08:17:51.93#ibcon#read 5, iclass 30, count 2 2006.246.08:17:51.93#ibcon#about to read 6, iclass 30, count 2 2006.246.08:17:51.93#ibcon#read 6, iclass 30, count 2 2006.246.08:17:51.93#ibcon#end of sib2, iclass 30, count 2 2006.246.08:17:51.93#ibcon#*after write, iclass 30, count 2 2006.246.08:17:51.93#ibcon#*before return 0, iclass 30, count 2 2006.246.08:17:51.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:51.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:17:51.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.08:17:51.93#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:51.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:52.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:52.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:52.05#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:17:52.05#ibcon#first serial, iclass 30, count 0 2006.246.08:17:52.05#ibcon#enter sib2, iclass 30, count 0 2006.246.08:17:52.05#ibcon#flushed, iclass 30, count 0 2006.246.08:17:52.05#ibcon#about to write, iclass 30, count 0 2006.246.08:17:52.05#ibcon#wrote, iclass 30, count 0 2006.246.08:17:52.05#ibcon#about to read 3, iclass 30, count 0 2006.246.08:17:52.07#ibcon#read 3, iclass 30, count 0 2006.246.08:17:52.07#ibcon#about to read 4, iclass 30, count 0 2006.246.08:17:52.07#ibcon#read 4, iclass 30, count 0 2006.246.08:17:52.07#ibcon#about to read 5, iclass 30, count 0 2006.246.08:17:52.07#ibcon#read 5, iclass 30, count 0 2006.246.08:17:52.07#ibcon#about to read 6, iclass 30, count 0 2006.246.08:17:52.07#ibcon#read 6, iclass 30, count 0 2006.246.08:17:52.07#ibcon#end of sib2, iclass 30, count 0 2006.246.08:17:52.07#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:17:52.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:17:52.07#ibcon#[27=USB\r\n] 2006.246.08:17:52.07#ibcon#*before write, iclass 30, count 0 2006.246.08:17:52.07#ibcon#enter sib2, iclass 30, count 0 2006.246.08:17:52.07#ibcon#flushed, iclass 30, count 0 2006.246.08:17:52.07#ibcon#about to write, iclass 30, count 0 2006.246.08:17:52.07#ibcon#wrote, iclass 30, count 0 2006.246.08:17:52.07#ibcon#about to read 3, iclass 30, count 0 2006.246.08:17:52.10#ibcon#read 3, iclass 30, count 0 2006.246.08:17:52.10#ibcon#about to read 4, iclass 30, count 0 2006.246.08:17:52.10#ibcon#read 4, iclass 30, count 0 2006.246.08:17:52.10#ibcon#about to read 5, iclass 30, count 0 2006.246.08:17:52.10#ibcon#read 5, iclass 30, count 0 2006.246.08:17:52.10#ibcon#about to read 6, iclass 30, count 0 2006.246.08:17:52.10#ibcon#read 6, iclass 30, count 0 2006.246.08:17:52.10#ibcon#end of sib2, iclass 30, count 0 2006.246.08:17:52.10#ibcon#*after write, iclass 30, count 0 2006.246.08:17:52.10#ibcon#*before return 0, iclass 30, count 0 2006.246.08:17:52.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:52.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:17:52.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:17:52.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:17:52.10$vc4f8/vblo=5,744.99 2006.246.08:17:52.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.246.08:17:52.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.246.08:17:52.10#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:52.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:52.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:52.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:52.10#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:17:52.10#ibcon#first serial, iclass 32, count 0 2006.246.08:17:52.10#ibcon#enter sib2, iclass 32, count 0 2006.246.08:17:52.10#ibcon#flushed, iclass 32, count 0 2006.246.08:17:52.10#ibcon#about to write, iclass 32, count 0 2006.246.08:17:52.10#ibcon#wrote, iclass 32, count 0 2006.246.08:17:52.10#ibcon#about to read 3, iclass 32, count 0 2006.246.08:17:52.12#ibcon#read 3, iclass 32, count 0 2006.246.08:17:52.12#ibcon#about to read 4, iclass 32, count 0 2006.246.08:17:52.12#ibcon#read 4, iclass 32, count 0 2006.246.08:17:52.12#ibcon#about to read 5, iclass 32, count 0 2006.246.08:17:52.12#ibcon#read 5, iclass 32, count 0 2006.246.08:17:52.12#ibcon#about to read 6, iclass 32, count 0 2006.246.08:17:52.12#ibcon#read 6, iclass 32, count 0 2006.246.08:17:52.12#ibcon#end of sib2, iclass 32, count 0 2006.246.08:17:52.12#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:17:52.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:17:52.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:17:52.12#ibcon#*before write, iclass 32, count 0 2006.246.08:17:52.12#ibcon#enter sib2, iclass 32, count 0 2006.246.08:17:52.12#ibcon#flushed, iclass 32, count 0 2006.246.08:17:52.12#ibcon#about to write, iclass 32, count 0 2006.246.08:17:52.12#ibcon#wrote, iclass 32, count 0 2006.246.08:17:52.12#ibcon#about to read 3, iclass 32, count 0 2006.246.08:17:52.16#ibcon#read 3, iclass 32, count 0 2006.246.08:17:52.16#ibcon#about to read 4, iclass 32, count 0 2006.246.08:17:52.16#ibcon#read 4, iclass 32, count 0 2006.246.08:17:52.16#ibcon#about to read 5, iclass 32, count 0 2006.246.08:17:52.16#ibcon#read 5, iclass 32, count 0 2006.246.08:17:52.16#ibcon#about to read 6, iclass 32, count 0 2006.246.08:17:52.16#ibcon#read 6, iclass 32, count 0 2006.246.08:17:52.16#ibcon#end of sib2, iclass 32, count 0 2006.246.08:17:52.16#ibcon#*after write, iclass 32, count 0 2006.246.08:17:52.16#ibcon#*before return 0, iclass 32, count 0 2006.246.08:17:52.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:52.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.246.08:17:52.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:17:52.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:17:52.16$vc4f8/vb=5,3 2006.246.08:17:52.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.246.08:17:52.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.246.08:17:52.16#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:52.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:52.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:52.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:52.22#ibcon#enter wrdev, iclass 34, count 2 2006.246.08:17:52.22#ibcon#first serial, iclass 34, count 2 2006.246.08:17:52.22#ibcon#enter sib2, iclass 34, count 2 2006.246.08:17:52.22#ibcon#flushed, iclass 34, count 2 2006.246.08:17:52.22#ibcon#about to write, iclass 34, count 2 2006.246.08:17:52.22#ibcon#wrote, iclass 34, count 2 2006.246.08:17:52.22#ibcon#about to read 3, iclass 34, count 2 2006.246.08:17:52.24#ibcon#read 3, iclass 34, count 2 2006.246.08:17:52.24#ibcon#about to read 4, iclass 34, count 2 2006.246.08:17:52.24#ibcon#read 4, iclass 34, count 2 2006.246.08:17:52.24#ibcon#about to read 5, iclass 34, count 2 2006.246.08:17:52.24#ibcon#read 5, iclass 34, count 2 2006.246.08:17:52.24#ibcon#about to read 6, iclass 34, count 2 2006.246.08:17:52.24#ibcon#read 6, iclass 34, count 2 2006.246.08:17:52.24#ibcon#end of sib2, iclass 34, count 2 2006.246.08:17:52.24#ibcon#*mode == 0, iclass 34, count 2 2006.246.08:17:52.24#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.246.08:17:52.24#ibcon#[27=AT05-03\r\n] 2006.246.08:17:52.24#ibcon#*before write, iclass 34, count 2 2006.246.08:17:52.24#ibcon#enter sib2, iclass 34, count 2 2006.246.08:17:52.24#ibcon#flushed, iclass 34, count 2 2006.246.08:17:52.24#ibcon#about to write, iclass 34, count 2 2006.246.08:17:52.24#ibcon#wrote, iclass 34, count 2 2006.246.08:17:52.24#ibcon#about to read 3, iclass 34, count 2 2006.246.08:17:52.27#ibcon#read 3, iclass 34, count 2 2006.246.08:17:52.27#ibcon#about to read 4, iclass 34, count 2 2006.246.08:17:52.27#ibcon#read 4, iclass 34, count 2 2006.246.08:17:52.27#ibcon#about to read 5, iclass 34, count 2 2006.246.08:17:52.27#ibcon#read 5, iclass 34, count 2 2006.246.08:17:52.27#ibcon#about to read 6, iclass 34, count 2 2006.246.08:17:52.27#ibcon#read 6, iclass 34, count 2 2006.246.08:17:52.27#ibcon#end of sib2, iclass 34, count 2 2006.246.08:17:52.27#ibcon#*after write, iclass 34, count 2 2006.246.08:17:52.27#ibcon#*before return 0, iclass 34, count 2 2006.246.08:17:52.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:52.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.246.08:17:52.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.246.08:17:52.27#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:52.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:52.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:52.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:52.39#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:17:52.39#ibcon#first serial, iclass 34, count 0 2006.246.08:17:52.39#ibcon#enter sib2, iclass 34, count 0 2006.246.08:17:52.39#ibcon#flushed, iclass 34, count 0 2006.246.08:17:52.39#ibcon#about to write, iclass 34, count 0 2006.246.08:17:52.39#ibcon#wrote, iclass 34, count 0 2006.246.08:17:52.39#ibcon#about to read 3, iclass 34, count 0 2006.246.08:17:52.41#ibcon#read 3, iclass 34, count 0 2006.246.08:17:52.41#ibcon#about to read 4, iclass 34, count 0 2006.246.08:17:52.41#ibcon#read 4, iclass 34, count 0 2006.246.08:17:52.41#ibcon#about to read 5, iclass 34, count 0 2006.246.08:17:52.41#ibcon#read 5, iclass 34, count 0 2006.246.08:17:52.41#ibcon#about to read 6, iclass 34, count 0 2006.246.08:17:52.41#ibcon#read 6, iclass 34, count 0 2006.246.08:17:52.41#ibcon#end of sib2, iclass 34, count 0 2006.246.08:17:52.41#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:17:52.41#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:17:52.41#ibcon#[27=USB\r\n] 2006.246.08:17:52.41#ibcon#*before write, iclass 34, count 0 2006.246.08:17:52.41#ibcon#enter sib2, iclass 34, count 0 2006.246.08:17:52.41#ibcon#flushed, iclass 34, count 0 2006.246.08:17:52.41#ibcon#about to write, iclass 34, count 0 2006.246.08:17:52.41#ibcon#wrote, iclass 34, count 0 2006.246.08:17:52.41#ibcon#about to read 3, iclass 34, count 0 2006.246.08:17:52.44#ibcon#read 3, iclass 34, count 0 2006.246.08:17:52.44#ibcon#about to read 4, iclass 34, count 0 2006.246.08:17:52.44#ibcon#read 4, iclass 34, count 0 2006.246.08:17:52.44#ibcon#about to read 5, iclass 34, count 0 2006.246.08:17:52.44#ibcon#read 5, iclass 34, count 0 2006.246.08:17:52.44#ibcon#about to read 6, iclass 34, count 0 2006.246.08:17:52.44#ibcon#read 6, iclass 34, count 0 2006.246.08:17:52.44#ibcon#end of sib2, iclass 34, count 0 2006.246.08:17:52.44#ibcon#*after write, iclass 34, count 0 2006.246.08:17:52.44#ibcon#*before return 0, iclass 34, count 0 2006.246.08:17:52.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:52.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.246.08:17:52.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:17:52.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:17:52.44$vc4f8/vblo=6,752.99 2006.246.08:17:52.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.246.08:17:52.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.246.08:17:52.44#ibcon#ireg 17 cls_cnt 0 2006.246.08:17:52.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:52.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:52.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:52.44#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:17:52.44#ibcon#first serial, iclass 36, count 0 2006.246.08:17:52.44#ibcon#enter sib2, iclass 36, count 0 2006.246.08:17:52.44#ibcon#flushed, iclass 36, count 0 2006.246.08:17:52.44#ibcon#about to write, iclass 36, count 0 2006.246.08:17:52.44#ibcon#wrote, iclass 36, count 0 2006.246.08:17:52.44#ibcon#about to read 3, iclass 36, count 0 2006.246.08:17:52.46#ibcon#read 3, iclass 36, count 0 2006.246.08:17:52.46#ibcon#about to read 4, iclass 36, count 0 2006.246.08:17:52.46#ibcon#read 4, iclass 36, count 0 2006.246.08:17:52.46#ibcon#about to read 5, iclass 36, count 0 2006.246.08:17:52.46#ibcon#read 5, iclass 36, count 0 2006.246.08:17:52.46#ibcon#about to read 6, iclass 36, count 0 2006.246.08:17:52.46#ibcon#read 6, iclass 36, count 0 2006.246.08:17:52.46#ibcon#end of sib2, iclass 36, count 0 2006.246.08:17:52.46#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:17:52.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:17:52.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:17:52.46#ibcon#*before write, iclass 36, count 0 2006.246.08:17:52.46#ibcon#enter sib2, iclass 36, count 0 2006.246.08:17:52.46#ibcon#flushed, iclass 36, count 0 2006.246.08:17:52.46#ibcon#about to write, iclass 36, count 0 2006.246.08:17:52.46#ibcon#wrote, iclass 36, count 0 2006.246.08:17:52.46#ibcon#about to read 3, iclass 36, count 0 2006.246.08:17:52.50#ibcon#read 3, iclass 36, count 0 2006.246.08:17:52.50#ibcon#about to read 4, iclass 36, count 0 2006.246.08:17:52.50#ibcon#read 4, iclass 36, count 0 2006.246.08:17:52.50#ibcon#about to read 5, iclass 36, count 0 2006.246.08:17:52.50#ibcon#read 5, iclass 36, count 0 2006.246.08:17:52.50#ibcon#about to read 6, iclass 36, count 0 2006.246.08:17:52.50#ibcon#read 6, iclass 36, count 0 2006.246.08:17:52.50#ibcon#end of sib2, iclass 36, count 0 2006.246.08:17:52.50#ibcon#*after write, iclass 36, count 0 2006.246.08:17:52.50#ibcon#*before return 0, iclass 36, count 0 2006.246.08:17:52.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:52.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.246.08:17:52.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:17:52.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:17:52.50$vc4f8/vb=6,3 2006.246.08:17:52.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.246.08:17:52.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.246.08:17:52.50#ibcon#ireg 11 cls_cnt 2 2006.246.08:17:52.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:52.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:52.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:52.56#ibcon#enter wrdev, iclass 38, count 2 2006.246.08:17:52.56#ibcon#first serial, iclass 38, count 2 2006.246.08:17:52.56#ibcon#enter sib2, iclass 38, count 2 2006.246.08:17:52.56#ibcon#flushed, iclass 38, count 2 2006.246.08:17:52.56#ibcon#about to write, iclass 38, count 2 2006.246.08:17:52.56#ibcon#wrote, iclass 38, count 2 2006.246.08:17:52.56#ibcon#about to read 3, iclass 38, count 2 2006.246.08:17:52.58#ibcon#read 3, iclass 38, count 2 2006.246.08:17:52.58#ibcon#about to read 4, iclass 38, count 2 2006.246.08:17:52.58#ibcon#read 4, iclass 38, count 2 2006.246.08:17:52.58#ibcon#about to read 5, iclass 38, count 2 2006.246.08:17:52.58#ibcon#read 5, iclass 38, count 2 2006.246.08:17:52.58#ibcon#about to read 6, iclass 38, count 2 2006.246.08:17:52.58#ibcon#read 6, iclass 38, count 2 2006.246.08:17:52.58#ibcon#end of sib2, iclass 38, count 2 2006.246.08:17:52.58#ibcon#*mode == 0, iclass 38, count 2 2006.246.08:17:52.58#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.246.08:17:52.58#ibcon#[27=AT06-03\r\n] 2006.246.08:17:52.58#ibcon#*before write, iclass 38, count 2 2006.246.08:17:52.58#ibcon#enter sib2, iclass 38, count 2 2006.246.08:17:52.58#ibcon#flushed, iclass 38, count 2 2006.246.08:17:52.58#ibcon#about to write, iclass 38, count 2 2006.246.08:17:52.58#ibcon#wrote, iclass 38, count 2 2006.246.08:17:52.58#ibcon#about to read 3, iclass 38, count 2 2006.246.08:17:52.61#ibcon#read 3, iclass 38, count 2 2006.246.08:17:52.61#ibcon#about to read 4, iclass 38, count 2 2006.246.08:17:52.61#ibcon#read 4, iclass 38, count 2 2006.246.08:17:52.61#ibcon#about to read 5, iclass 38, count 2 2006.246.08:17:52.61#ibcon#read 5, iclass 38, count 2 2006.246.08:17:52.61#ibcon#about to read 6, iclass 38, count 2 2006.246.08:17:52.61#ibcon#read 6, iclass 38, count 2 2006.246.08:17:52.61#ibcon#end of sib2, iclass 38, count 2 2006.246.08:17:52.61#ibcon#*after write, iclass 38, count 2 2006.246.08:17:52.61#ibcon#*before return 0, iclass 38, count 2 2006.246.08:17:52.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:52.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.246.08:17:52.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.246.08:17:52.61#ibcon#ireg 7 cls_cnt 0 2006.246.08:17:52.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:52.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:52.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:52.73#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:17:52.73#ibcon#first serial, iclass 38, count 0 2006.246.08:17:52.73#ibcon#enter sib2, iclass 38, count 0 2006.246.08:17:52.73#ibcon#flushed, iclass 38, count 0 2006.246.08:17:52.73#ibcon#about to write, iclass 38, count 0 2006.246.08:17:52.73#ibcon#wrote, iclass 38, count 0 2006.246.08:17:52.73#ibcon#about to read 3, iclass 38, count 0 2006.246.08:17:52.75#ibcon#read 3, iclass 38, count 0 2006.246.08:17:52.75#ibcon#about to read 4, iclass 38, count 0 2006.246.08:17:52.75#ibcon#read 4, iclass 38, count 0 2006.246.08:17:52.75#ibcon#about to read 5, iclass 38, count 0 2006.246.08:17:52.75#ibcon#read 5, iclass 38, count 0 2006.246.08:17:52.75#ibcon#about to read 6, iclass 38, count 0 2006.246.08:17:52.75#ibcon#read 6, iclass 38, count 0 2006.246.08:17:52.75#ibcon#end of sib2, iclass 38, count 0 2006.246.08:17:52.75#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:17:52.75#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:17:52.75#ibcon#[27=USB\r\n] 2006.246.08:17:52.75#ibcon#*before write, iclass 38, count 0 2006.246.08:17:52.75#ibcon#enter sib2, iclass 38, count 0 2006.246.08:17:52.75#ibcon#flushed, iclass 38, count 0 2006.246.08:17:52.75#ibcon#about to write, iclass 38, count 0 2006.246.08:17:52.75#ibcon#wrote, iclass 38, count 0 2006.246.08:17:52.75#ibcon#about to read 3, iclass 38, count 0 2006.246.08:17:52.78#ibcon#read 3, iclass 38, count 0 2006.246.08:17:52.78#ibcon#about to read 4, iclass 38, count 0 2006.246.08:17:52.78#ibcon#read 4, iclass 38, count 0 2006.246.08:17:52.78#ibcon#about to read 5, iclass 38, count 0 2006.246.08:17:52.78#ibcon#read 5, iclass 38, count 0 2006.246.08:17:52.78#ibcon#about to read 6, iclass 38, count 0 2006.246.08:17:52.78#ibcon#read 6, iclass 38, count 0 2006.246.08:17:52.78#ibcon#end of sib2, iclass 38, count 0 2006.246.08:17:52.78#ibcon#*after write, iclass 38, count 0 2006.246.08:17:52.78#ibcon#*before return 0, iclass 38, count 0 2006.246.08:17:52.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:52.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.246.08:17:52.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:17:52.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:17:52.78$vc4f8/vabw=wide 2006.246.08:17:52.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.246.08:17:52.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.246.08:17:52.78#ibcon#ireg 8 cls_cnt 0 2006.246.08:17:52.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:52.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:52.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:52.78#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:17:52.78#ibcon#first serial, iclass 40, count 0 2006.246.08:17:52.78#ibcon#enter sib2, iclass 40, count 0 2006.246.08:17:52.78#ibcon#flushed, iclass 40, count 0 2006.246.08:17:52.78#ibcon#about to write, iclass 40, count 0 2006.246.08:17:52.78#ibcon#wrote, iclass 40, count 0 2006.246.08:17:52.78#ibcon#about to read 3, iclass 40, count 0 2006.246.08:17:52.80#ibcon#read 3, iclass 40, count 0 2006.246.08:17:52.80#ibcon#about to read 4, iclass 40, count 0 2006.246.08:17:52.80#ibcon#read 4, iclass 40, count 0 2006.246.08:17:52.80#ibcon#about to read 5, iclass 40, count 0 2006.246.08:17:52.80#ibcon#read 5, iclass 40, count 0 2006.246.08:17:52.80#ibcon#about to read 6, iclass 40, count 0 2006.246.08:17:52.80#ibcon#read 6, iclass 40, count 0 2006.246.08:17:52.80#ibcon#end of sib2, iclass 40, count 0 2006.246.08:17:52.80#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:17:52.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:17:52.80#ibcon#[25=BW32\r\n] 2006.246.08:17:52.80#ibcon#*before write, iclass 40, count 0 2006.246.08:17:52.80#ibcon#enter sib2, iclass 40, count 0 2006.246.08:17:52.80#ibcon#flushed, iclass 40, count 0 2006.246.08:17:52.80#ibcon#about to write, iclass 40, count 0 2006.246.08:17:52.80#ibcon#wrote, iclass 40, count 0 2006.246.08:17:52.80#ibcon#about to read 3, iclass 40, count 0 2006.246.08:17:52.83#ibcon#read 3, iclass 40, count 0 2006.246.08:17:52.83#ibcon#about to read 4, iclass 40, count 0 2006.246.08:17:52.83#ibcon#read 4, iclass 40, count 0 2006.246.08:17:52.83#ibcon#about to read 5, iclass 40, count 0 2006.246.08:17:52.83#ibcon#read 5, iclass 40, count 0 2006.246.08:17:52.83#ibcon#about to read 6, iclass 40, count 0 2006.246.08:17:52.83#ibcon#read 6, iclass 40, count 0 2006.246.08:17:52.83#ibcon#end of sib2, iclass 40, count 0 2006.246.08:17:52.83#ibcon#*after write, iclass 40, count 0 2006.246.08:17:52.83#ibcon#*before return 0, iclass 40, count 0 2006.246.08:17:52.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:52.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.246.08:17:52.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:17:52.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:17:52.83$vc4f8/vbbw=wide 2006.246.08:17:52.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.08:17:52.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.08:17:52.83#ibcon#ireg 8 cls_cnt 0 2006.246.08:17:52.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:17:52.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:17:52.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:17:52.91#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:17:52.91#ibcon#first serial, iclass 4, count 0 2006.246.08:17:52.91#ibcon#enter sib2, iclass 4, count 0 2006.246.08:17:52.91#ibcon#flushed, iclass 4, count 0 2006.246.08:17:52.91#ibcon#about to write, iclass 4, count 0 2006.246.08:17:52.91#ibcon#wrote, iclass 4, count 0 2006.246.08:17:52.91#ibcon#about to read 3, iclass 4, count 0 2006.246.08:17:52.92#ibcon#read 3, iclass 4, count 0 2006.246.08:17:52.92#ibcon#about to read 4, iclass 4, count 0 2006.246.08:17:52.92#ibcon#read 4, iclass 4, count 0 2006.246.08:17:52.92#ibcon#about to read 5, iclass 4, count 0 2006.246.08:17:52.92#ibcon#read 5, iclass 4, count 0 2006.246.08:17:52.92#ibcon#about to read 6, iclass 4, count 0 2006.246.08:17:52.92#ibcon#read 6, iclass 4, count 0 2006.246.08:17:52.92#ibcon#end of sib2, iclass 4, count 0 2006.246.08:17:52.92#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:17:52.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:17:52.92#ibcon#[27=BW32\r\n] 2006.246.08:17:52.92#ibcon#*before write, iclass 4, count 0 2006.246.08:17:52.92#ibcon#enter sib2, iclass 4, count 0 2006.246.08:17:52.92#ibcon#flushed, iclass 4, count 0 2006.246.08:17:52.92#ibcon#about to write, iclass 4, count 0 2006.246.08:17:52.92#ibcon#wrote, iclass 4, count 0 2006.246.08:17:52.92#ibcon#about to read 3, iclass 4, count 0 2006.246.08:17:52.95#ibcon#read 3, iclass 4, count 0 2006.246.08:17:52.95#ibcon#about to read 4, iclass 4, count 0 2006.246.08:17:52.95#ibcon#read 4, iclass 4, count 0 2006.246.08:17:52.95#ibcon#about to read 5, iclass 4, count 0 2006.246.08:17:52.95#ibcon#read 5, iclass 4, count 0 2006.246.08:17:52.95#ibcon#about to read 6, iclass 4, count 0 2006.246.08:17:52.95#ibcon#read 6, iclass 4, count 0 2006.246.08:17:52.95#ibcon#end of sib2, iclass 4, count 0 2006.246.08:17:52.95#ibcon#*after write, iclass 4, count 0 2006.246.08:17:52.95#ibcon#*before return 0, iclass 4, count 0 2006.246.08:17:52.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:17:52.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:17:52.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:17:52.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:17:52.95$4f8m12a/ifd4f 2006.246.08:17:52.95$ifd4f/lo= 2006.246.08:17:52.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:17:52.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:17:52.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:17:52.96$ifd4f/patch= 2006.246.08:17:52.96$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:17:52.96$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:17:52.96$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:17:52.96$4f8m12a/"form=m,16.000,1:2 2006.246.08:17:52.96$4f8m12a/"tpicd 2006.246.08:17:52.96$4f8m12a/echo=off 2006.246.08:17:52.96$4f8m12a/xlog=off 2006.246.08:17:52.96:!2006.246.08:18:20 2006.246.08:18:01.14#trakl#Source acquired 2006.246.08:18:02.14#flagr#flagr/antenna,acquired 2006.246.08:18:20.01:preob 2006.246.08:18:21.13/onsource/TRACKING 2006.246.08:18:21.13:!2006.246.08:18:30 2006.246.08:18:30.00:data_valid=on 2006.246.08:18:30.00:midob 2006.246.08:18:30.13/onsource/TRACKING 2006.246.08:18:30.13/wx/26.29,1005.7,76 2006.246.08:18:30.20/cable/+6.4150E-03 2006.246.08:18:31.29/va/01,08,usb,yes,44,46 2006.246.08:18:31.29/va/02,07,usb,yes,44,46 2006.246.08:18:31.29/va/03,06,usb,yes,46,46 2006.246.08:18:31.29/va/04,07,usb,yes,44,48 2006.246.08:18:31.29/va/05,07,usb,yes,48,51 2006.246.08:18:31.29/va/06,07,usb,yes,42,42 2006.246.08:18:31.29/va/07,07,usb,yes,41,42 2006.246.08:18:31.29/va/08,08,usb,yes,36,36 2006.246.08:18:31.52/valo/01,532.99,yes,locked 2006.246.08:18:31.52/valo/02,572.99,yes,locked 2006.246.08:18:31.52/valo/03,672.99,yes,locked 2006.246.08:18:31.52/valo/04,832.99,yes,locked 2006.246.08:18:31.52/valo/05,652.99,yes,locked 2006.246.08:18:31.52/valo/06,772.99,yes,locked 2006.246.08:18:31.52/valo/07,832.99,yes,locked 2006.246.08:18:31.52/valo/08,852.99,yes,locked 2006.246.08:18:32.61/vb/01,04,usb,yes,40,38 2006.246.08:18:32.61/vb/02,04,usb,yes,42,44 2006.246.08:18:32.61/vb/03,04,usb,yes,38,43 2006.246.08:18:32.61/vb/04,04,usb,yes,39,40 2006.246.08:18:32.61/vb/05,03,usb,yes,46,52 2006.246.08:18:32.61/vb/06,03,usb,yes,47,51 2006.246.08:18:32.61/vb/07,04,usb,yes,41,41 2006.246.08:18:32.61/vb/08,03,usb,yes,46,51 2006.246.08:18:32.85/vblo/01,632.99,yes,locked 2006.246.08:18:32.85/vblo/02,640.99,yes,locked 2006.246.08:18:32.85/vblo/03,656.99,yes,locked 2006.246.08:18:32.85/vblo/04,712.99,yes,locked 2006.246.08:18:32.85/vblo/05,744.99,yes,locked 2006.246.08:18:32.85/vblo/06,752.99,yes,locked 2006.246.08:18:32.85/vblo/07,734.99,yes,locked 2006.246.08:18:32.85/vblo/08,744.99,yes,locked 2006.246.08:18:33.00/vabw/8 2006.246.08:18:33.15/vbbw/8 2006.246.08:18:33.24/xfe/off,on,13.0 2006.246.08:18:33.63/ifatt/23,28,28,28 2006.246.08:18:34.07/fmout-gps/S +4.45E-07 2006.246.08:18:34.12:!2006.246.08:19:30 2006.246.08:19:30.01:data_valid=off 2006.246.08:19:30.02:postob 2006.246.08:19:30.10/cable/+6.4161E-03 2006.246.08:19:30.11/wx/26.27,1005.7,76 2006.246.08:19:31.07/fmout-gps/S +4.46E-07 2006.246.08:19:31.08:scan_name=246-0821,k06246,60 2006.246.08:19:31.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.246.08:19:31.13#flagr#flagr/antenna,new-source 2006.246.08:19:32.13:checkk5 2006.246.08:19:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:19:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:19:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:19:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:19:33.99/chk_obsdata//k5ts1/T2460818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:19:34.36/chk_obsdata//k5ts2/T2460818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:19:34.73/chk_obsdata//k5ts3/T2460818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:19:35.10/chk_obsdata//k5ts4/T2460818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:19:35.80/k5log//k5ts1_log_newline 2006.246.08:19:36.48/k5log//k5ts2_log_newline 2006.246.08:19:37.17/k5log//k5ts3_log_newline 2006.246.08:19:37.86/k5log//k5ts4_log_newline 2006.246.08:19:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:19:37.88:4f8m12a=3 2006.246.08:19:37.88$4f8m12a/echo=on 2006.246.08:19:37.88$4f8m12a/pcalon 2006.246.08:19:37.88$pcalon/"no phase cal control is implemented here 2006.246.08:19:37.88$4f8m12a/"tpicd=stop 2006.246.08:19:37.88$4f8m12a/vc4f8 2006.246.08:19:37.88$vc4f8/valo=1,532.99 2006.246.08:19:37.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:19:37.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:19:37.88#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:37.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:37.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:37.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:37.88#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:19:37.88#ibcon#first serial, iclass 13, count 0 2006.246.08:19:37.88#ibcon#enter sib2, iclass 13, count 0 2006.246.08:19:37.88#ibcon#flushed, iclass 13, count 0 2006.246.08:19:37.88#ibcon#about to write, iclass 13, count 0 2006.246.08:19:37.88#ibcon#wrote, iclass 13, count 0 2006.246.08:19:37.88#ibcon#about to read 3, iclass 13, count 0 2006.246.08:19:37.92#ibcon#read 3, iclass 13, count 0 2006.246.08:19:37.93#ibcon#about to read 4, iclass 13, count 0 2006.246.08:19:37.93#ibcon#read 4, iclass 13, count 0 2006.246.08:19:37.93#ibcon#about to read 5, iclass 13, count 0 2006.246.08:19:37.93#ibcon#read 5, iclass 13, count 0 2006.246.08:19:37.93#ibcon#about to read 6, iclass 13, count 0 2006.246.08:19:37.93#ibcon#read 6, iclass 13, count 0 2006.246.08:19:37.93#ibcon#end of sib2, iclass 13, count 0 2006.246.08:19:37.93#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:19:37.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:19:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:19:37.93#ibcon#*before write, iclass 13, count 0 2006.246.08:19:37.93#ibcon#enter sib2, iclass 13, count 0 2006.246.08:19:37.93#ibcon#flushed, iclass 13, count 0 2006.246.08:19:37.93#ibcon#about to write, iclass 13, count 0 2006.246.08:19:37.93#ibcon#wrote, iclass 13, count 0 2006.246.08:19:37.93#ibcon#about to read 3, iclass 13, count 0 2006.246.08:19:37.97#ibcon#read 3, iclass 13, count 0 2006.246.08:19:37.97#ibcon#about to read 4, iclass 13, count 0 2006.246.08:19:37.97#ibcon#read 4, iclass 13, count 0 2006.246.08:19:37.97#ibcon#about to read 5, iclass 13, count 0 2006.246.08:19:37.97#ibcon#read 5, iclass 13, count 0 2006.246.08:19:37.97#ibcon#about to read 6, iclass 13, count 0 2006.246.08:19:37.97#ibcon#read 6, iclass 13, count 0 2006.246.08:19:37.97#ibcon#end of sib2, iclass 13, count 0 2006.246.08:19:37.97#ibcon#*after write, iclass 13, count 0 2006.246.08:19:37.97#ibcon#*before return 0, iclass 13, count 0 2006.246.08:19:37.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:37.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:37.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:19:37.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:19:37.97$vc4f8/va=1,8 2006.246.08:19:37.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.08:19:37.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.08:19:37.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:37.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:37.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:37.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:37.97#ibcon#enter wrdev, iclass 15, count 2 2006.246.08:19:37.97#ibcon#first serial, iclass 15, count 2 2006.246.08:19:37.97#ibcon#enter sib2, iclass 15, count 2 2006.246.08:19:37.97#ibcon#flushed, iclass 15, count 2 2006.246.08:19:37.97#ibcon#about to write, iclass 15, count 2 2006.246.08:19:37.97#ibcon#wrote, iclass 15, count 2 2006.246.08:19:37.97#ibcon#about to read 3, iclass 15, count 2 2006.246.08:19:37.99#ibcon#read 3, iclass 15, count 2 2006.246.08:19:37.99#ibcon#about to read 4, iclass 15, count 2 2006.246.08:19:37.99#ibcon#read 4, iclass 15, count 2 2006.246.08:19:37.99#ibcon#about to read 5, iclass 15, count 2 2006.246.08:19:37.99#ibcon#read 5, iclass 15, count 2 2006.246.08:19:37.99#ibcon#about to read 6, iclass 15, count 2 2006.246.08:19:37.99#ibcon#read 6, iclass 15, count 2 2006.246.08:19:37.99#ibcon#end of sib2, iclass 15, count 2 2006.246.08:19:37.99#ibcon#*mode == 0, iclass 15, count 2 2006.246.08:19:37.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.08:19:37.99#ibcon#[25=AT01-08\r\n] 2006.246.08:19:37.99#ibcon#*before write, iclass 15, count 2 2006.246.08:19:37.99#ibcon#enter sib2, iclass 15, count 2 2006.246.08:19:37.99#ibcon#flushed, iclass 15, count 2 2006.246.08:19:37.99#ibcon#about to write, iclass 15, count 2 2006.246.08:19:37.99#ibcon#wrote, iclass 15, count 2 2006.246.08:19:37.99#ibcon#about to read 3, iclass 15, count 2 2006.246.08:19:38.03#ibcon#read 3, iclass 15, count 2 2006.246.08:19:38.03#ibcon#about to read 4, iclass 15, count 2 2006.246.08:19:38.03#ibcon#read 4, iclass 15, count 2 2006.246.08:19:38.03#ibcon#about to read 5, iclass 15, count 2 2006.246.08:19:38.03#ibcon#read 5, iclass 15, count 2 2006.246.08:19:38.03#ibcon#about to read 6, iclass 15, count 2 2006.246.08:19:38.03#ibcon#read 6, iclass 15, count 2 2006.246.08:19:38.03#ibcon#end of sib2, iclass 15, count 2 2006.246.08:19:38.03#ibcon#*after write, iclass 15, count 2 2006.246.08:19:38.03#ibcon#*before return 0, iclass 15, count 2 2006.246.08:19:38.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:38.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:38.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.08:19:38.03#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:38.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:38.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:38.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:38.14#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:19:38.14#ibcon#first serial, iclass 15, count 0 2006.246.08:19:38.14#ibcon#enter sib2, iclass 15, count 0 2006.246.08:19:38.14#ibcon#flushed, iclass 15, count 0 2006.246.08:19:38.14#ibcon#about to write, iclass 15, count 0 2006.246.08:19:38.14#ibcon#wrote, iclass 15, count 0 2006.246.08:19:38.14#ibcon#about to read 3, iclass 15, count 0 2006.246.08:19:38.16#ibcon#read 3, iclass 15, count 0 2006.246.08:19:38.16#ibcon#about to read 4, iclass 15, count 0 2006.246.08:19:38.16#ibcon#read 4, iclass 15, count 0 2006.246.08:19:38.16#ibcon#about to read 5, iclass 15, count 0 2006.246.08:19:38.16#ibcon#read 5, iclass 15, count 0 2006.246.08:19:38.16#ibcon#about to read 6, iclass 15, count 0 2006.246.08:19:38.16#ibcon#read 6, iclass 15, count 0 2006.246.08:19:38.16#ibcon#end of sib2, iclass 15, count 0 2006.246.08:19:38.16#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:19:38.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:19:38.16#ibcon#[25=USB\r\n] 2006.246.08:19:38.16#ibcon#*before write, iclass 15, count 0 2006.246.08:19:38.16#ibcon#enter sib2, iclass 15, count 0 2006.246.08:19:38.16#ibcon#flushed, iclass 15, count 0 2006.246.08:19:38.16#ibcon#about to write, iclass 15, count 0 2006.246.08:19:38.16#ibcon#wrote, iclass 15, count 0 2006.246.08:19:38.16#ibcon#about to read 3, iclass 15, count 0 2006.246.08:19:38.19#ibcon#read 3, iclass 15, count 0 2006.246.08:19:38.19#ibcon#about to read 4, iclass 15, count 0 2006.246.08:19:38.19#ibcon#read 4, iclass 15, count 0 2006.246.08:19:38.19#ibcon#about to read 5, iclass 15, count 0 2006.246.08:19:38.19#ibcon#read 5, iclass 15, count 0 2006.246.08:19:38.19#ibcon#about to read 6, iclass 15, count 0 2006.246.08:19:38.19#ibcon#read 6, iclass 15, count 0 2006.246.08:19:38.19#ibcon#end of sib2, iclass 15, count 0 2006.246.08:19:38.19#ibcon#*after write, iclass 15, count 0 2006.246.08:19:38.19#ibcon#*before return 0, iclass 15, count 0 2006.246.08:19:38.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:38.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:38.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:19:38.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:19:38.19$vc4f8/valo=2,572.99 2006.246.08:19:38.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.08:19:38.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.08:19:38.19#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:38.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:38.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:38.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:38.19#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:19:38.19#ibcon#first serial, iclass 17, count 0 2006.246.08:19:38.19#ibcon#enter sib2, iclass 17, count 0 2006.246.08:19:38.19#ibcon#flushed, iclass 17, count 0 2006.246.08:19:38.19#ibcon#about to write, iclass 17, count 0 2006.246.08:19:38.19#ibcon#wrote, iclass 17, count 0 2006.246.08:19:38.19#ibcon#about to read 3, iclass 17, count 0 2006.246.08:19:38.22#ibcon#read 3, iclass 17, count 0 2006.246.08:19:38.22#ibcon#about to read 4, iclass 17, count 0 2006.246.08:19:38.22#ibcon#read 4, iclass 17, count 0 2006.246.08:19:38.22#ibcon#about to read 5, iclass 17, count 0 2006.246.08:19:38.22#ibcon#read 5, iclass 17, count 0 2006.246.08:19:38.22#ibcon#about to read 6, iclass 17, count 0 2006.246.08:19:38.22#ibcon#read 6, iclass 17, count 0 2006.246.08:19:38.22#ibcon#end of sib2, iclass 17, count 0 2006.246.08:19:38.22#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:19:38.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:19:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:19:38.22#ibcon#*before write, iclass 17, count 0 2006.246.08:19:38.22#ibcon#enter sib2, iclass 17, count 0 2006.246.08:19:38.22#ibcon#flushed, iclass 17, count 0 2006.246.08:19:38.22#ibcon#about to write, iclass 17, count 0 2006.246.08:19:38.22#ibcon#wrote, iclass 17, count 0 2006.246.08:19:38.22#ibcon#about to read 3, iclass 17, count 0 2006.246.08:19:38.26#ibcon#read 3, iclass 17, count 0 2006.246.08:19:38.26#ibcon#about to read 4, iclass 17, count 0 2006.246.08:19:38.26#ibcon#read 4, iclass 17, count 0 2006.246.08:19:38.26#ibcon#about to read 5, iclass 17, count 0 2006.246.08:19:38.26#ibcon#read 5, iclass 17, count 0 2006.246.08:19:38.26#ibcon#about to read 6, iclass 17, count 0 2006.246.08:19:38.26#ibcon#read 6, iclass 17, count 0 2006.246.08:19:38.26#ibcon#end of sib2, iclass 17, count 0 2006.246.08:19:38.26#ibcon#*after write, iclass 17, count 0 2006.246.08:19:38.26#ibcon#*before return 0, iclass 17, count 0 2006.246.08:19:38.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:38.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:38.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:19:38.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:19:38.26$vc4f8/va=2,7 2006.246.08:19:38.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.08:19:38.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.08:19:38.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:38.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:38.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:38.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:38.32#ibcon#enter wrdev, iclass 19, count 2 2006.246.08:19:38.32#ibcon#first serial, iclass 19, count 2 2006.246.08:19:38.32#ibcon#enter sib2, iclass 19, count 2 2006.246.08:19:38.32#ibcon#flushed, iclass 19, count 2 2006.246.08:19:38.32#ibcon#about to write, iclass 19, count 2 2006.246.08:19:38.32#ibcon#wrote, iclass 19, count 2 2006.246.08:19:38.32#ibcon#about to read 3, iclass 19, count 2 2006.246.08:19:38.33#ibcon#read 3, iclass 19, count 2 2006.246.08:19:38.33#ibcon#about to read 4, iclass 19, count 2 2006.246.08:19:38.33#ibcon#read 4, iclass 19, count 2 2006.246.08:19:38.33#ibcon#about to read 5, iclass 19, count 2 2006.246.08:19:38.33#ibcon#read 5, iclass 19, count 2 2006.246.08:19:38.33#ibcon#about to read 6, iclass 19, count 2 2006.246.08:19:38.33#ibcon#read 6, iclass 19, count 2 2006.246.08:19:38.33#ibcon#end of sib2, iclass 19, count 2 2006.246.08:19:38.33#ibcon#*mode == 0, iclass 19, count 2 2006.246.08:19:38.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.08:19:38.33#ibcon#[25=AT02-07\r\n] 2006.246.08:19:38.33#ibcon#*before write, iclass 19, count 2 2006.246.08:19:38.33#ibcon#enter sib2, iclass 19, count 2 2006.246.08:19:38.33#ibcon#flushed, iclass 19, count 2 2006.246.08:19:38.33#ibcon#about to write, iclass 19, count 2 2006.246.08:19:38.33#ibcon#wrote, iclass 19, count 2 2006.246.08:19:38.33#ibcon#about to read 3, iclass 19, count 2 2006.246.08:19:38.36#ibcon#read 3, iclass 19, count 2 2006.246.08:19:38.36#ibcon#about to read 4, iclass 19, count 2 2006.246.08:19:38.36#ibcon#read 4, iclass 19, count 2 2006.246.08:19:38.36#ibcon#about to read 5, iclass 19, count 2 2006.246.08:19:38.36#ibcon#read 5, iclass 19, count 2 2006.246.08:19:38.36#ibcon#about to read 6, iclass 19, count 2 2006.246.08:19:38.36#ibcon#read 6, iclass 19, count 2 2006.246.08:19:38.36#ibcon#end of sib2, iclass 19, count 2 2006.246.08:19:38.36#ibcon#*after write, iclass 19, count 2 2006.246.08:19:38.36#ibcon#*before return 0, iclass 19, count 2 2006.246.08:19:38.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:38.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:38.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.08:19:38.36#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:38.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:38.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:38.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:38.48#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:19:38.48#ibcon#first serial, iclass 19, count 0 2006.246.08:19:38.48#ibcon#enter sib2, iclass 19, count 0 2006.246.08:19:38.48#ibcon#flushed, iclass 19, count 0 2006.246.08:19:38.48#ibcon#about to write, iclass 19, count 0 2006.246.08:19:38.48#ibcon#wrote, iclass 19, count 0 2006.246.08:19:38.48#ibcon#about to read 3, iclass 19, count 0 2006.246.08:19:38.50#ibcon#read 3, iclass 19, count 0 2006.246.08:19:38.50#ibcon#about to read 4, iclass 19, count 0 2006.246.08:19:38.50#ibcon#read 4, iclass 19, count 0 2006.246.08:19:38.50#ibcon#about to read 5, iclass 19, count 0 2006.246.08:19:38.50#ibcon#read 5, iclass 19, count 0 2006.246.08:19:38.50#ibcon#about to read 6, iclass 19, count 0 2006.246.08:19:38.50#ibcon#read 6, iclass 19, count 0 2006.246.08:19:38.50#ibcon#end of sib2, iclass 19, count 0 2006.246.08:19:38.50#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:19:38.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:19:38.50#ibcon#[25=USB\r\n] 2006.246.08:19:38.50#ibcon#*before write, iclass 19, count 0 2006.246.08:19:38.50#ibcon#enter sib2, iclass 19, count 0 2006.246.08:19:38.50#ibcon#flushed, iclass 19, count 0 2006.246.08:19:38.50#ibcon#about to write, iclass 19, count 0 2006.246.08:19:38.50#ibcon#wrote, iclass 19, count 0 2006.246.08:19:38.50#ibcon#about to read 3, iclass 19, count 0 2006.246.08:19:38.53#ibcon#read 3, iclass 19, count 0 2006.246.08:19:38.53#ibcon#about to read 4, iclass 19, count 0 2006.246.08:19:38.53#ibcon#read 4, iclass 19, count 0 2006.246.08:19:38.53#ibcon#about to read 5, iclass 19, count 0 2006.246.08:19:38.53#ibcon#read 5, iclass 19, count 0 2006.246.08:19:38.53#ibcon#about to read 6, iclass 19, count 0 2006.246.08:19:38.53#ibcon#read 6, iclass 19, count 0 2006.246.08:19:38.53#ibcon#end of sib2, iclass 19, count 0 2006.246.08:19:38.53#ibcon#*after write, iclass 19, count 0 2006.246.08:19:38.53#ibcon#*before return 0, iclass 19, count 0 2006.246.08:19:38.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:38.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:38.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:19:38.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:19:38.53$vc4f8/valo=3,672.99 2006.246.08:19:38.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.08:19:38.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.08:19:38.53#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:38.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:38.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:38.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:38.53#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:19:38.53#ibcon#first serial, iclass 21, count 0 2006.246.08:19:38.53#ibcon#enter sib2, iclass 21, count 0 2006.246.08:19:38.53#ibcon#flushed, iclass 21, count 0 2006.246.08:19:38.53#ibcon#about to write, iclass 21, count 0 2006.246.08:19:38.53#ibcon#wrote, iclass 21, count 0 2006.246.08:19:38.53#ibcon#about to read 3, iclass 21, count 0 2006.246.08:19:38.55#ibcon#read 3, iclass 21, count 0 2006.246.08:19:38.55#ibcon#about to read 4, iclass 21, count 0 2006.246.08:19:38.55#ibcon#read 4, iclass 21, count 0 2006.246.08:19:38.55#ibcon#about to read 5, iclass 21, count 0 2006.246.08:19:38.55#ibcon#read 5, iclass 21, count 0 2006.246.08:19:38.55#ibcon#about to read 6, iclass 21, count 0 2006.246.08:19:38.55#ibcon#read 6, iclass 21, count 0 2006.246.08:19:38.55#ibcon#end of sib2, iclass 21, count 0 2006.246.08:19:38.55#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:19:38.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:19:38.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:19:38.55#ibcon#*before write, iclass 21, count 0 2006.246.08:19:38.55#ibcon#enter sib2, iclass 21, count 0 2006.246.08:19:38.55#ibcon#flushed, iclass 21, count 0 2006.246.08:19:38.55#ibcon#about to write, iclass 21, count 0 2006.246.08:19:38.55#ibcon#wrote, iclass 21, count 0 2006.246.08:19:38.55#ibcon#about to read 3, iclass 21, count 0 2006.246.08:19:38.59#ibcon#read 3, iclass 21, count 0 2006.246.08:19:38.59#ibcon#about to read 4, iclass 21, count 0 2006.246.08:19:38.59#ibcon#read 4, iclass 21, count 0 2006.246.08:19:38.59#ibcon#about to read 5, iclass 21, count 0 2006.246.08:19:38.59#ibcon#read 5, iclass 21, count 0 2006.246.08:19:38.59#ibcon#about to read 6, iclass 21, count 0 2006.246.08:19:38.59#ibcon#read 6, iclass 21, count 0 2006.246.08:19:38.59#ibcon#end of sib2, iclass 21, count 0 2006.246.08:19:38.59#ibcon#*after write, iclass 21, count 0 2006.246.08:19:38.59#ibcon#*before return 0, iclass 21, count 0 2006.246.08:19:38.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:38.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:38.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:19:38.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:19:38.59$vc4f8/va=3,6 2006.246.08:19:38.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.08:19:38.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.08:19:38.59#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:38.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:38.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:38.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:38.66#ibcon#enter wrdev, iclass 23, count 2 2006.246.08:19:38.66#ibcon#first serial, iclass 23, count 2 2006.246.08:19:38.66#ibcon#enter sib2, iclass 23, count 2 2006.246.08:19:38.66#ibcon#flushed, iclass 23, count 2 2006.246.08:19:38.66#ibcon#about to write, iclass 23, count 2 2006.246.08:19:38.66#ibcon#wrote, iclass 23, count 2 2006.246.08:19:38.66#ibcon#about to read 3, iclass 23, count 2 2006.246.08:19:38.67#ibcon#read 3, iclass 23, count 2 2006.246.08:19:38.67#ibcon#about to read 4, iclass 23, count 2 2006.246.08:19:38.67#ibcon#read 4, iclass 23, count 2 2006.246.08:19:38.67#ibcon#about to read 5, iclass 23, count 2 2006.246.08:19:38.67#ibcon#read 5, iclass 23, count 2 2006.246.08:19:38.67#ibcon#about to read 6, iclass 23, count 2 2006.246.08:19:38.67#ibcon#read 6, iclass 23, count 2 2006.246.08:19:38.67#ibcon#end of sib2, iclass 23, count 2 2006.246.08:19:38.68#ibcon#*mode == 0, iclass 23, count 2 2006.246.08:19:38.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.08:19:38.68#ibcon#[25=AT03-06\r\n] 2006.246.08:19:38.68#ibcon#*before write, iclass 23, count 2 2006.246.08:19:38.68#ibcon#enter sib2, iclass 23, count 2 2006.246.08:19:38.68#ibcon#flushed, iclass 23, count 2 2006.246.08:19:38.68#ibcon#about to write, iclass 23, count 2 2006.246.08:19:38.68#ibcon#wrote, iclass 23, count 2 2006.246.08:19:38.68#ibcon#about to read 3, iclass 23, count 2 2006.246.08:19:38.70#ibcon#read 3, iclass 23, count 2 2006.246.08:19:38.70#ibcon#about to read 4, iclass 23, count 2 2006.246.08:19:38.70#ibcon#read 4, iclass 23, count 2 2006.246.08:19:38.70#ibcon#about to read 5, iclass 23, count 2 2006.246.08:19:38.70#ibcon#read 5, iclass 23, count 2 2006.246.08:19:38.70#ibcon#about to read 6, iclass 23, count 2 2006.246.08:19:38.70#ibcon#read 6, iclass 23, count 2 2006.246.08:19:38.70#ibcon#end of sib2, iclass 23, count 2 2006.246.08:19:38.70#ibcon#*after write, iclass 23, count 2 2006.246.08:19:38.70#ibcon#*before return 0, iclass 23, count 2 2006.246.08:19:38.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:38.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:38.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.08:19:38.70#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:38.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:38.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:38.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:38.82#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:19:38.82#ibcon#first serial, iclass 23, count 0 2006.246.08:19:38.82#ibcon#enter sib2, iclass 23, count 0 2006.246.08:19:38.82#ibcon#flushed, iclass 23, count 0 2006.246.08:19:38.82#ibcon#about to write, iclass 23, count 0 2006.246.08:19:38.82#ibcon#wrote, iclass 23, count 0 2006.246.08:19:38.82#ibcon#about to read 3, iclass 23, count 0 2006.246.08:19:38.84#ibcon#read 3, iclass 23, count 0 2006.246.08:19:38.84#ibcon#about to read 4, iclass 23, count 0 2006.246.08:19:38.84#ibcon#read 4, iclass 23, count 0 2006.246.08:19:38.84#ibcon#about to read 5, iclass 23, count 0 2006.246.08:19:38.84#ibcon#read 5, iclass 23, count 0 2006.246.08:19:38.84#ibcon#about to read 6, iclass 23, count 0 2006.246.08:19:38.84#ibcon#read 6, iclass 23, count 0 2006.246.08:19:38.84#ibcon#end of sib2, iclass 23, count 0 2006.246.08:19:38.84#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:19:38.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:19:38.84#ibcon#[25=USB\r\n] 2006.246.08:19:38.84#ibcon#*before write, iclass 23, count 0 2006.246.08:19:38.84#ibcon#enter sib2, iclass 23, count 0 2006.246.08:19:38.84#ibcon#flushed, iclass 23, count 0 2006.246.08:19:38.84#ibcon#about to write, iclass 23, count 0 2006.246.08:19:38.84#ibcon#wrote, iclass 23, count 0 2006.246.08:19:38.84#ibcon#about to read 3, iclass 23, count 0 2006.246.08:19:38.87#ibcon#read 3, iclass 23, count 0 2006.246.08:19:38.87#ibcon#about to read 4, iclass 23, count 0 2006.246.08:19:38.87#ibcon#read 4, iclass 23, count 0 2006.246.08:19:38.87#ibcon#about to read 5, iclass 23, count 0 2006.246.08:19:38.87#ibcon#read 5, iclass 23, count 0 2006.246.08:19:38.87#ibcon#about to read 6, iclass 23, count 0 2006.246.08:19:38.87#ibcon#read 6, iclass 23, count 0 2006.246.08:19:38.87#ibcon#end of sib2, iclass 23, count 0 2006.246.08:19:38.87#ibcon#*after write, iclass 23, count 0 2006.246.08:19:38.87#ibcon#*before return 0, iclass 23, count 0 2006.246.08:19:38.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:38.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:38.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:19:38.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:19:38.87$vc4f8/valo=4,832.99 2006.246.08:19:38.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.08:19:38.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.08:19:38.87#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:38.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:38.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:38.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:38.87#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:19:38.87#ibcon#first serial, iclass 25, count 0 2006.246.08:19:38.87#ibcon#enter sib2, iclass 25, count 0 2006.246.08:19:38.87#ibcon#flushed, iclass 25, count 0 2006.246.08:19:38.87#ibcon#about to write, iclass 25, count 0 2006.246.08:19:38.87#ibcon#wrote, iclass 25, count 0 2006.246.08:19:38.87#ibcon#about to read 3, iclass 25, count 0 2006.246.08:19:38.89#ibcon#read 3, iclass 25, count 0 2006.246.08:19:38.89#ibcon#about to read 4, iclass 25, count 0 2006.246.08:19:38.89#ibcon#read 4, iclass 25, count 0 2006.246.08:19:38.89#ibcon#about to read 5, iclass 25, count 0 2006.246.08:19:38.89#ibcon#read 5, iclass 25, count 0 2006.246.08:19:38.89#ibcon#about to read 6, iclass 25, count 0 2006.246.08:19:38.89#ibcon#read 6, iclass 25, count 0 2006.246.08:19:38.89#ibcon#end of sib2, iclass 25, count 0 2006.246.08:19:38.89#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:19:38.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:19:38.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:19:38.89#ibcon#*before write, iclass 25, count 0 2006.246.08:19:38.89#ibcon#enter sib2, iclass 25, count 0 2006.246.08:19:38.89#ibcon#flushed, iclass 25, count 0 2006.246.08:19:38.89#ibcon#about to write, iclass 25, count 0 2006.246.08:19:38.89#ibcon#wrote, iclass 25, count 0 2006.246.08:19:38.89#ibcon#about to read 3, iclass 25, count 0 2006.246.08:19:38.92#abcon#<5=/05 3.9 6.7 26.27 761005.7\r\n> 2006.246.08:19:38.93#ibcon#read 3, iclass 25, count 0 2006.246.08:19:38.93#ibcon#about to read 4, iclass 25, count 0 2006.246.08:19:38.93#ibcon#read 4, iclass 25, count 0 2006.246.08:19:38.93#ibcon#about to read 5, iclass 25, count 0 2006.246.08:19:38.93#ibcon#read 5, iclass 25, count 0 2006.246.08:19:38.93#ibcon#about to read 6, iclass 25, count 0 2006.246.08:19:38.93#ibcon#read 6, iclass 25, count 0 2006.246.08:19:38.93#ibcon#end of sib2, iclass 25, count 0 2006.246.08:19:38.93#ibcon#*after write, iclass 25, count 0 2006.246.08:19:38.93#ibcon#*before return 0, iclass 25, count 0 2006.246.08:19:38.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:38.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:38.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:19:38.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:19:38.93$vc4f8/va=4,7 2006.246.08:19:38.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.246.08:19:38.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.246.08:19:38.93#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:38.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:19:38.94#abcon#{5=INTERFACE CLEAR} 2006.246.08:19:38.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:19:38.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:19:38.99#ibcon#enter wrdev, iclass 30, count 2 2006.246.08:19:38.99#ibcon#first serial, iclass 30, count 2 2006.246.08:19:38.99#ibcon#enter sib2, iclass 30, count 2 2006.246.08:19:38.99#ibcon#flushed, iclass 30, count 2 2006.246.08:19:38.99#ibcon#about to write, iclass 30, count 2 2006.246.08:19:38.99#ibcon#wrote, iclass 30, count 2 2006.246.08:19:38.99#ibcon#about to read 3, iclass 30, count 2 2006.246.08:19:39.00#abcon#[5=S1D000X0/0*\r\n] 2006.246.08:19:39.01#ibcon#read 3, iclass 30, count 2 2006.246.08:19:39.01#ibcon#about to read 4, iclass 30, count 2 2006.246.08:19:39.01#ibcon#read 4, iclass 30, count 2 2006.246.08:19:39.01#ibcon#about to read 5, iclass 30, count 2 2006.246.08:19:39.01#ibcon#read 5, iclass 30, count 2 2006.246.08:19:39.01#ibcon#about to read 6, iclass 30, count 2 2006.246.08:19:39.01#ibcon#read 6, iclass 30, count 2 2006.246.08:19:39.01#ibcon#end of sib2, iclass 30, count 2 2006.246.08:19:39.01#ibcon#*mode == 0, iclass 30, count 2 2006.246.08:19:39.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.246.08:19:39.01#ibcon#[25=AT04-07\r\n] 2006.246.08:19:39.01#ibcon#*before write, iclass 30, count 2 2006.246.08:19:39.01#ibcon#enter sib2, iclass 30, count 2 2006.246.08:19:39.01#ibcon#flushed, iclass 30, count 2 2006.246.08:19:39.01#ibcon#about to write, iclass 30, count 2 2006.246.08:19:39.01#ibcon#wrote, iclass 30, count 2 2006.246.08:19:39.01#ibcon#about to read 3, iclass 30, count 2 2006.246.08:19:39.04#ibcon#read 3, iclass 30, count 2 2006.246.08:19:39.04#ibcon#about to read 4, iclass 30, count 2 2006.246.08:19:39.04#ibcon#read 4, iclass 30, count 2 2006.246.08:19:39.04#ibcon#about to read 5, iclass 30, count 2 2006.246.08:19:39.04#ibcon#read 5, iclass 30, count 2 2006.246.08:19:39.04#ibcon#about to read 6, iclass 30, count 2 2006.246.08:19:39.04#ibcon#read 6, iclass 30, count 2 2006.246.08:19:39.04#ibcon#end of sib2, iclass 30, count 2 2006.246.08:19:39.04#ibcon#*after write, iclass 30, count 2 2006.246.08:19:39.04#ibcon#*before return 0, iclass 30, count 2 2006.246.08:19:39.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:19:39.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.246.08:19:39.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.246.08:19:39.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:39.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:19:39.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:19:39.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:19:39.16#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:19:39.16#ibcon#first serial, iclass 30, count 0 2006.246.08:19:39.16#ibcon#enter sib2, iclass 30, count 0 2006.246.08:19:39.16#ibcon#flushed, iclass 30, count 0 2006.246.08:19:39.16#ibcon#about to write, iclass 30, count 0 2006.246.08:19:39.16#ibcon#wrote, iclass 30, count 0 2006.246.08:19:39.16#ibcon#about to read 3, iclass 30, count 0 2006.246.08:19:39.18#ibcon#read 3, iclass 30, count 0 2006.246.08:19:39.18#ibcon#about to read 4, iclass 30, count 0 2006.246.08:19:39.18#ibcon#read 4, iclass 30, count 0 2006.246.08:19:39.18#ibcon#about to read 5, iclass 30, count 0 2006.246.08:19:39.18#ibcon#read 5, iclass 30, count 0 2006.246.08:19:39.18#ibcon#about to read 6, iclass 30, count 0 2006.246.08:19:39.18#ibcon#read 6, iclass 30, count 0 2006.246.08:19:39.18#ibcon#end of sib2, iclass 30, count 0 2006.246.08:19:39.18#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:19:39.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:19:39.18#ibcon#[25=USB\r\n] 2006.246.08:19:39.18#ibcon#*before write, iclass 30, count 0 2006.246.08:19:39.18#ibcon#enter sib2, iclass 30, count 0 2006.246.08:19:39.18#ibcon#flushed, iclass 30, count 0 2006.246.08:19:39.18#ibcon#about to write, iclass 30, count 0 2006.246.08:19:39.18#ibcon#wrote, iclass 30, count 0 2006.246.08:19:39.18#ibcon#about to read 3, iclass 30, count 0 2006.246.08:19:39.21#ibcon#read 3, iclass 30, count 0 2006.246.08:19:39.21#ibcon#about to read 4, iclass 30, count 0 2006.246.08:19:39.21#ibcon#read 4, iclass 30, count 0 2006.246.08:19:39.21#ibcon#about to read 5, iclass 30, count 0 2006.246.08:19:39.21#ibcon#read 5, iclass 30, count 0 2006.246.08:19:39.21#ibcon#about to read 6, iclass 30, count 0 2006.246.08:19:39.21#ibcon#read 6, iclass 30, count 0 2006.246.08:19:39.21#ibcon#end of sib2, iclass 30, count 0 2006.246.08:19:39.21#ibcon#*after write, iclass 30, count 0 2006.246.08:19:39.21#ibcon#*before return 0, iclass 30, count 0 2006.246.08:19:39.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:19:39.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.246.08:19:39.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:19:39.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:19:39.21$vc4f8/valo=5,652.99 2006.246.08:19:39.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.08:19:39.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.08:19:39.21#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:39.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:39.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:39.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:39.21#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:19:39.21#ibcon#first serial, iclass 33, count 0 2006.246.08:19:39.21#ibcon#enter sib2, iclass 33, count 0 2006.246.08:19:39.21#ibcon#flushed, iclass 33, count 0 2006.246.08:19:39.21#ibcon#about to write, iclass 33, count 0 2006.246.08:19:39.21#ibcon#wrote, iclass 33, count 0 2006.246.08:19:39.21#ibcon#about to read 3, iclass 33, count 0 2006.246.08:19:39.23#ibcon#read 3, iclass 33, count 0 2006.246.08:19:39.23#ibcon#about to read 4, iclass 33, count 0 2006.246.08:19:39.23#ibcon#read 4, iclass 33, count 0 2006.246.08:19:39.23#ibcon#about to read 5, iclass 33, count 0 2006.246.08:19:39.23#ibcon#read 5, iclass 33, count 0 2006.246.08:19:39.23#ibcon#about to read 6, iclass 33, count 0 2006.246.08:19:39.23#ibcon#read 6, iclass 33, count 0 2006.246.08:19:39.23#ibcon#end of sib2, iclass 33, count 0 2006.246.08:19:39.23#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:19:39.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:19:39.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:19:39.23#ibcon#*before write, iclass 33, count 0 2006.246.08:19:39.23#ibcon#enter sib2, iclass 33, count 0 2006.246.08:19:39.23#ibcon#flushed, iclass 33, count 0 2006.246.08:19:39.23#ibcon#about to write, iclass 33, count 0 2006.246.08:19:39.23#ibcon#wrote, iclass 33, count 0 2006.246.08:19:39.23#ibcon#about to read 3, iclass 33, count 0 2006.246.08:19:39.27#ibcon#read 3, iclass 33, count 0 2006.246.08:19:39.27#ibcon#about to read 4, iclass 33, count 0 2006.246.08:19:39.27#ibcon#read 4, iclass 33, count 0 2006.246.08:19:39.27#ibcon#about to read 5, iclass 33, count 0 2006.246.08:19:39.27#ibcon#read 5, iclass 33, count 0 2006.246.08:19:39.27#ibcon#about to read 6, iclass 33, count 0 2006.246.08:19:39.27#ibcon#read 6, iclass 33, count 0 2006.246.08:19:39.27#ibcon#end of sib2, iclass 33, count 0 2006.246.08:19:39.27#ibcon#*after write, iclass 33, count 0 2006.246.08:19:39.27#ibcon#*before return 0, iclass 33, count 0 2006.246.08:19:39.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:39.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:39.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:19:39.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:19:39.27$vc4f8/va=5,7 2006.246.08:19:39.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.08:19:39.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.08:19:39.27#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:39.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:39.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:39.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:39.33#ibcon#enter wrdev, iclass 35, count 2 2006.246.08:19:39.33#ibcon#first serial, iclass 35, count 2 2006.246.08:19:39.33#ibcon#enter sib2, iclass 35, count 2 2006.246.08:19:39.33#ibcon#flushed, iclass 35, count 2 2006.246.08:19:39.33#ibcon#about to write, iclass 35, count 2 2006.246.08:19:39.33#ibcon#wrote, iclass 35, count 2 2006.246.08:19:39.33#ibcon#about to read 3, iclass 35, count 2 2006.246.08:19:39.35#ibcon#read 3, iclass 35, count 2 2006.246.08:19:39.35#ibcon#about to read 4, iclass 35, count 2 2006.246.08:19:39.35#ibcon#read 4, iclass 35, count 2 2006.246.08:19:39.35#ibcon#about to read 5, iclass 35, count 2 2006.246.08:19:39.35#ibcon#read 5, iclass 35, count 2 2006.246.08:19:39.35#ibcon#about to read 6, iclass 35, count 2 2006.246.08:19:39.35#ibcon#read 6, iclass 35, count 2 2006.246.08:19:39.35#ibcon#end of sib2, iclass 35, count 2 2006.246.08:19:39.35#ibcon#*mode == 0, iclass 35, count 2 2006.246.08:19:39.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.08:19:39.35#ibcon#[25=AT05-07\r\n] 2006.246.08:19:39.35#ibcon#*before write, iclass 35, count 2 2006.246.08:19:39.35#ibcon#enter sib2, iclass 35, count 2 2006.246.08:19:39.35#ibcon#flushed, iclass 35, count 2 2006.246.08:19:39.35#ibcon#about to write, iclass 35, count 2 2006.246.08:19:39.35#ibcon#wrote, iclass 35, count 2 2006.246.08:19:39.35#ibcon#about to read 3, iclass 35, count 2 2006.246.08:19:39.38#ibcon#read 3, iclass 35, count 2 2006.246.08:19:39.38#ibcon#about to read 4, iclass 35, count 2 2006.246.08:19:39.38#ibcon#read 4, iclass 35, count 2 2006.246.08:19:39.38#ibcon#about to read 5, iclass 35, count 2 2006.246.08:19:39.38#ibcon#read 5, iclass 35, count 2 2006.246.08:19:39.38#ibcon#about to read 6, iclass 35, count 2 2006.246.08:19:39.38#ibcon#read 6, iclass 35, count 2 2006.246.08:19:39.38#ibcon#end of sib2, iclass 35, count 2 2006.246.08:19:39.38#ibcon#*after write, iclass 35, count 2 2006.246.08:19:39.38#ibcon#*before return 0, iclass 35, count 2 2006.246.08:19:39.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:39.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:39.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.08:19:39.38#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:39.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:39.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:39.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:39.50#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:19:39.50#ibcon#first serial, iclass 35, count 0 2006.246.08:19:39.50#ibcon#enter sib2, iclass 35, count 0 2006.246.08:19:39.50#ibcon#flushed, iclass 35, count 0 2006.246.08:19:39.50#ibcon#about to write, iclass 35, count 0 2006.246.08:19:39.50#ibcon#wrote, iclass 35, count 0 2006.246.08:19:39.50#ibcon#about to read 3, iclass 35, count 0 2006.246.08:19:39.52#ibcon#read 3, iclass 35, count 0 2006.246.08:19:39.52#ibcon#about to read 4, iclass 35, count 0 2006.246.08:19:39.52#ibcon#read 4, iclass 35, count 0 2006.246.08:19:39.52#ibcon#about to read 5, iclass 35, count 0 2006.246.08:19:39.52#ibcon#read 5, iclass 35, count 0 2006.246.08:19:39.52#ibcon#about to read 6, iclass 35, count 0 2006.246.08:19:39.52#ibcon#read 6, iclass 35, count 0 2006.246.08:19:39.52#ibcon#end of sib2, iclass 35, count 0 2006.246.08:19:39.52#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:19:39.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:19:39.52#ibcon#[25=USB\r\n] 2006.246.08:19:39.52#ibcon#*before write, iclass 35, count 0 2006.246.08:19:39.52#ibcon#enter sib2, iclass 35, count 0 2006.246.08:19:39.52#ibcon#flushed, iclass 35, count 0 2006.246.08:19:39.52#ibcon#about to write, iclass 35, count 0 2006.246.08:19:39.52#ibcon#wrote, iclass 35, count 0 2006.246.08:19:39.52#ibcon#about to read 3, iclass 35, count 0 2006.246.08:19:39.55#ibcon#read 3, iclass 35, count 0 2006.246.08:19:39.55#ibcon#about to read 4, iclass 35, count 0 2006.246.08:19:39.55#ibcon#read 4, iclass 35, count 0 2006.246.08:19:39.55#ibcon#about to read 5, iclass 35, count 0 2006.246.08:19:39.55#ibcon#read 5, iclass 35, count 0 2006.246.08:19:39.55#ibcon#about to read 6, iclass 35, count 0 2006.246.08:19:39.55#ibcon#read 6, iclass 35, count 0 2006.246.08:19:39.55#ibcon#end of sib2, iclass 35, count 0 2006.246.08:19:39.55#ibcon#*after write, iclass 35, count 0 2006.246.08:19:39.55#ibcon#*before return 0, iclass 35, count 0 2006.246.08:19:39.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:39.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:39.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:19:39.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:19:39.55$vc4f8/valo=6,772.99 2006.246.08:19:39.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.08:19:39.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.08:19:39.55#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:39.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:39.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:39.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:39.55#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:19:39.55#ibcon#first serial, iclass 37, count 0 2006.246.08:19:39.55#ibcon#enter sib2, iclass 37, count 0 2006.246.08:19:39.55#ibcon#flushed, iclass 37, count 0 2006.246.08:19:39.55#ibcon#about to write, iclass 37, count 0 2006.246.08:19:39.55#ibcon#wrote, iclass 37, count 0 2006.246.08:19:39.55#ibcon#about to read 3, iclass 37, count 0 2006.246.08:19:39.57#ibcon#read 3, iclass 37, count 0 2006.246.08:19:39.57#ibcon#about to read 4, iclass 37, count 0 2006.246.08:19:39.57#ibcon#read 4, iclass 37, count 0 2006.246.08:19:39.57#ibcon#about to read 5, iclass 37, count 0 2006.246.08:19:39.57#ibcon#read 5, iclass 37, count 0 2006.246.08:19:39.57#ibcon#about to read 6, iclass 37, count 0 2006.246.08:19:39.57#ibcon#read 6, iclass 37, count 0 2006.246.08:19:39.57#ibcon#end of sib2, iclass 37, count 0 2006.246.08:19:39.57#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:19:39.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:19:39.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:19:39.57#ibcon#*before write, iclass 37, count 0 2006.246.08:19:39.57#ibcon#enter sib2, iclass 37, count 0 2006.246.08:19:39.57#ibcon#flushed, iclass 37, count 0 2006.246.08:19:39.57#ibcon#about to write, iclass 37, count 0 2006.246.08:19:39.57#ibcon#wrote, iclass 37, count 0 2006.246.08:19:39.57#ibcon#about to read 3, iclass 37, count 0 2006.246.08:19:39.61#ibcon#read 3, iclass 37, count 0 2006.246.08:19:39.61#ibcon#about to read 4, iclass 37, count 0 2006.246.08:19:39.61#ibcon#read 4, iclass 37, count 0 2006.246.08:19:39.61#ibcon#about to read 5, iclass 37, count 0 2006.246.08:19:39.61#ibcon#read 5, iclass 37, count 0 2006.246.08:19:39.61#ibcon#about to read 6, iclass 37, count 0 2006.246.08:19:39.61#ibcon#read 6, iclass 37, count 0 2006.246.08:19:39.61#ibcon#end of sib2, iclass 37, count 0 2006.246.08:19:39.61#ibcon#*after write, iclass 37, count 0 2006.246.08:19:39.61#ibcon#*before return 0, iclass 37, count 0 2006.246.08:19:39.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:39.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:39.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:19:39.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:19:39.61$vc4f8/va=6,7 2006.246.08:19:39.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.246.08:19:39.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.246.08:19:39.61#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:39.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:19:39.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:19:39.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:19:39.68#ibcon#enter wrdev, iclass 39, count 2 2006.246.08:19:39.68#ibcon#first serial, iclass 39, count 2 2006.246.08:19:39.68#ibcon#enter sib2, iclass 39, count 2 2006.246.08:19:39.68#ibcon#flushed, iclass 39, count 2 2006.246.08:19:39.68#ibcon#about to write, iclass 39, count 2 2006.246.08:19:39.68#ibcon#wrote, iclass 39, count 2 2006.246.08:19:39.68#ibcon#about to read 3, iclass 39, count 2 2006.246.08:19:39.69#ibcon#read 3, iclass 39, count 2 2006.246.08:19:39.69#ibcon#about to read 4, iclass 39, count 2 2006.246.08:19:39.69#ibcon#read 4, iclass 39, count 2 2006.246.08:19:39.69#ibcon#about to read 5, iclass 39, count 2 2006.246.08:19:39.69#ibcon#read 5, iclass 39, count 2 2006.246.08:19:39.69#ibcon#about to read 6, iclass 39, count 2 2006.246.08:19:39.69#ibcon#read 6, iclass 39, count 2 2006.246.08:19:39.69#ibcon#end of sib2, iclass 39, count 2 2006.246.08:19:39.69#ibcon#*mode == 0, iclass 39, count 2 2006.246.08:19:39.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.246.08:19:39.70#ibcon#[25=AT06-07\r\n] 2006.246.08:19:39.70#ibcon#*before write, iclass 39, count 2 2006.246.08:19:39.70#ibcon#enter sib2, iclass 39, count 2 2006.246.08:19:39.70#ibcon#flushed, iclass 39, count 2 2006.246.08:19:39.70#ibcon#about to write, iclass 39, count 2 2006.246.08:19:39.70#ibcon#wrote, iclass 39, count 2 2006.246.08:19:39.70#ibcon#about to read 3, iclass 39, count 2 2006.246.08:19:39.72#ibcon#read 3, iclass 39, count 2 2006.246.08:19:39.72#ibcon#about to read 4, iclass 39, count 2 2006.246.08:19:39.72#ibcon#read 4, iclass 39, count 2 2006.246.08:19:39.72#ibcon#about to read 5, iclass 39, count 2 2006.246.08:19:39.72#ibcon#read 5, iclass 39, count 2 2006.246.08:19:39.72#ibcon#about to read 6, iclass 39, count 2 2006.246.08:19:39.72#ibcon#read 6, iclass 39, count 2 2006.246.08:19:39.72#ibcon#end of sib2, iclass 39, count 2 2006.246.08:19:39.72#ibcon#*after write, iclass 39, count 2 2006.246.08:19:39.72#ibcon#*before return 0, iclass 39, count 2 2006.246.08:19:39.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:19:39.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.246.08:19:39.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.246.08:19:39.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:39.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:19:39.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:19:39.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:19:39.84#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:19:39.84#ibcon#first serial, iclass 39, count 0 2006.246.08:19:39.84#ibcon#enter sib2, iclass 39, count 0 2006.246.08:19:39.84#ibcon#flushed, iclass 39, count 0 2006.246.08:19:39.84#ibcon#about to write, iclass 39, count 0 2006.246.08:19:39.84#ibcon#wrote, iclass 39, count 0 2006.246.08:19:39.84#ibcon#about to read 3, iclass 39, count 0 2006.246.08:19:39.86#ibcon#read 3, iclass 39, count 0 2006.246.08:19:39.86#ibcon#about to read 4, iclass 39, count 0 2006.246.08:19:39.86#ibcon#read 4, iclass 39, count 0 2006.246.08:19:39.86#ibcon#about to read 5, iclass 39, count 0 2006.246.08:19:39.86#ibcon#read 5, iclass 39, count 0 2006.246.08:19:39.86#ibcon#about to read 6, iclass 39, count 0 2006.246.08:19:39.86#ibcon#read 6, iclass 39, count 0 2006.246.08:19:39.86#ibcon#end of sib2, iclass 39, count 0 2006.246.08:19:39.86#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:19:39.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:19:39.86#ibcon#[25=USB\r\n] 2006.246.08:19:39.86#ibcon#*before write, iclass 39, count 0 2006.246.08:19:39.86#ibcon#enter sib2, iclass 39, count 0 2006.246.08:19:39.86#ibcon#flushed, iclass 39, count 0 2006.246.08:19:39.86#ibcon#about to write, iclass 39, count 0 2006.246.08:19:39.86#ibcon#wrote, iclass 39, count 0 2006.246.08:19:39.86#ibcon#about to read 3, iclass 39, count 0 2006.246.08:19:39.89#ibcon#read 3, iclass 39, count 0 2006.246.08:19:39.89#ibcon#about to read 4, iclass 39, count 0 2006.246.08:19:39.89#ibcon#read 4, iclass 39, count 0 2006.246.08:19:39.89#ibcon#about to read 5, iclass 39, count 0 2006.246.08:19:39.89#ibcon#read 5, iclass 39, count 0 2006.246.08:19:39.89#ibcon#about to read 6, iclass 39, count 0 2006.246.08:19:39.89#ibcon#read 6, iclass 39, count 0 2006.246.08:19:39.89#ibcon#end of sib2, iclass 39, count 0 2006.246.08:19:39.89#ibcon#*after write, iclass 39, count 0 2006.246.08:19:39.89#ibcon#*before return 0, iclass 39, count 0 2006.246.08:19:39.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:19:39.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.246.08:19:39.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:19:39.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:19:39.89$vc4f8/valo=7,832.99 2006.246.08:19:39.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.246.08:19:39.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.246.08:19:39.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:39.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:19:39.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:19:39.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:19:39.89#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:19:39.89#ibcon#first serial, iclass 3, count 0 2006.246.08:19:39.89#ibcon#enter sib2, iclass 3, count 0 2006.246.08:19:39.89#ibcon#flushed, iclass 3, count 0 2006.246.08:19:39.89#ibcon#about to write, iclass 3, count 0 2006.246.08:19:39.89#ibcon#wrote, iclass 3, count 0 2006.246.08:19:39.89#ibcon#about to read 3, iclass 3, count 0 2006.246.08:19:39.91#ibcon#read 3, iclass 3, count 0 2006.246.08:19:39.91#ibcon#about to read 4, iclass 3, count 0 2006.246.08:19:39.91#ibcon#read 4, iclass 3, count 0 2006.246.08:19:39.91#ibcon#about to read 5, iclass 3, count 0 2006.246.08:19:39.91#ibcon#read 5, iclass 3, count 0 2006.246.08:19:39.91#ibcon#about to read 6, iclass 3, count 0 2006.246.08:19:39.91#ibcon#read 6, iclass 3, count 0 2006.246.08:19:39.91#ibcon#end of sib2, iclass 3, count 0 2006.246.08:19:39.91#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:19:39.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:19:39.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:19:39.91#ibcon#*before write, iclass 3, count 0 2006.246.08:19:39.91#ibcon#enter sib2, iclass 3, count 0 2006.246.08:19:39.91#ibcon#flushed, iclass 3, count 0 2006.246.08:19:39.91#ibcon#about to write, iclass 3, count 0 2006.246.08:19:39.91#ibcon#wrote, iclass 3, count 0 2006.246.08:19:39.91#ibcon#about to read 3, iclass 3, count 0 2006.246.08:19:39.95#ibcon#read 3, iclass 3, count 0 2006.246.08:19:39.95#ibcon#about to read 4, iclass 3, count 0 2006.246.08:19:39.95#ibcon#read 4, iclass 3, count 0 2006.246.08:19:39.95#ibcon#about to read 5, iclass 3, count 0 2006.246.08:19:39.95#ibcon#read 5, iclass 3, count 0 2006.246.08:19:39.95#ibcon#about to read 6, iclass 3, count 0 2006.246.08:19:39.95#ibcon#read 6, iclass 3, count 0 2006.246.08:19:39.95#ibcon#end of sib2, iclass 3, count 0 2006.246.08:19:39.95#ibcon#*after write, iclass 3, count 0 2006.246.08:19:39.95#ibcon#*before return 0, iclass 3, count 0 2006.246.08:19:39.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:19:39.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.246.08:19:39.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:19:39.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:19:39.95$vc4f8/va=7,7 2006.246.08:19:39.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.246.08:19:39.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.246.08:19:39.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:39.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:19:40.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:19:40.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:19:40.01#ibcon#enter wrdev, iclass 5, count 2 2006.246.08:19:40.01#ibcon#first serial, iclass 5, count 2 2006.246.08:19:40.01#ibcon#enter sib2, iclass 5, count 2 2006.246.08:19:40.01#ibcon#flushed, iclass 5, count 2 2006.246.08:19:40.01#ibcon#about to write, iclass 5, count 2 2006.246.08:19:40.01#ibcon#wrote, iclass 5, count 2 2006.246.08:19:40.01#ibcon#about to read 3, iclass 5, count 2 2006.246.08:19:40.03#ibcon#read 3, iclass 5, count 2 2006.246.08:19:40.03#ibcon#about to read 4, iclass 5, count 2 2006.246.08:19:40.03#ibcon#read 4, iclass 5, count 2 2006.246.08:19:40.03#ibcon#about to read 5, iclass 5, count 2 2006.246.08:19:40.03#ibcon#read 5, iclass 5, count 2 2006.246.08:19:40.03#ibcon#about to read 6, iclass 5, count 2 2006.246.08:19:40.03#ibcon#read 6, iclass 5, count 2 2006.246.08:19:40.03#ibcon#end of sib2, iclass 5, count 2 2006.246.08:19:40.03#ibcon#*mode == 0, iclass 5, count 2 2006.246.08:19:40.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.246.08:19:40.03#ibcon#[25=AT07-07\r\n] 2006.246.08:19:40.03#ibcon#*before write, iclass 5, count 2 2006.246.08:19:40.03#ibcon#enter sib2, iclass 5, count 2 2006.246.08:19:40.03#ibcon#flushed, iclass 5, count 2 2006.246.08:19:40.03#ibcon#about to write, iclass 5, count 2 2006.246.08:19:40.03#ibcon#wrote, iclass 5, count 2 2006.246.08:19:40.03#ibcon#about to read 3, iclass 5, count 2 2006.246.08:19:40.06#ibcon#read 3, iclass 5, count 2 2006.246.08:19:40.06#ibcon#about to read 4, iclass 5, count 2 2006.246.08:19:40.06#ibcon#read 4, iclass 5, count 2 2006.246.08:19:40.06#ibcon#about to read 5, iclass 5, count 2 2006.246.08:19:40.06#ibcon#read 5, iclass 5, count 2 2006.246.08:19:40.06#ibcon#about to read 6, iclass 5, count 2 2006.246.08:19:40.06#ibcon#read 6, iclass 5, count 2 2006.246.08:19:40.06#ibcon#end of sib2, iclass 5, count 2 2006.246.08:19:40.06#ibcon#*after write, iclass 5, count 2 2006.246.08:19:40.06#ibcon#*before return 0, iclass 5, count 2 2006.246.08:19:40.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:19:40.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.246.08:19:40.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.246.08:19:40.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:40.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:19:40.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:19:40.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:19:40.18#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:19:40.18#ibcon#first serial, iclass 5, count 0 2006.246.08:19:40.18#ibcon#enter sib2, iclass 5, count 0 2006.246.08:19:40.18#ibcon#flushed, iclass 5, count 0 2006.246.08:19:40.18#ibcon#about to write, iclass 5, count 0 2006.246.08:19:40.18#ibcon#wrote, iclass 5, count 0 2006.246.08:19:40.18#ibcon#about to read 3, iclass 5, count 0 2006.246.08:19:40.20#ibcon#read 3, iclass 5, count 0 2006.246.08:19:40.20#ibcon#about to read 4, iclass 5, count 0 2006.246.08:19:40.20#ibcon#read 4, iclass 5, count 0 2006.246.08:19:40.20#ibcon#about to read 5, iclass 5, count 0 2006.246.08:19:40.20#ibcon#read 5, iclass 5, count 0 2006.246.08:19:40.20#ibcon#about to read 6, iclass 5, count 0 2006.246.08:19:40.20#ibcon#read 6, iclass 5, count 0 2006.246.08:19:40.20#ibcon#end of sib2, iclass 5, count 0 2006.246.08:19:40.20#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:19:40.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:19:40.20#ibcon#[25=USB\r\n] 2006.246.08:19:40.20#ibcon#*before write, iclass 5, count 0 2006.246.08:19:40.20#ibcon#enter sib2, iclass 5, count 0 2006.246.08:19:40.20#ibcon#flushed, iclass 5, count 0 2006.246.08:19:40.20#ibcon#about to write, iclass 5, count 0 2006.246.08:19:40.20#ibcon#wrote, iclass 5, count 0 2006.246.08:19:40.20#ibcon#about to read 3, iclass 5, count 0 2006.246.08:19:40.23#ibcon#read 3, iclass 5, count 0 2006.246.08:19:40.23#ibcon#about to read 4, iclass 5, count 0 2006.246.08:19:40.23#ibcon#read 4, iclass 5, count 0 2006.246.08:19:40.23#ibcon#about to read 5, iclass 5, count 0 2006.246.08:19:40.23#ibcon#read 5, iclass 5, count 0 2006.246.08:19:40.23#ibcon#about to read 6, iclass 5, count 0 2006.246.08:19:40.23#ibcon#read 6, iclass 5, count 0 2006.246.08:19:40.23#ibcon#end of sib2, iclass 5, count 0 2006.246.08:19:40.23#ibcon#*after write, iclass 5, count 0 2006.246.08:19:40.23#ibcon#*before return 0, iclass 5, count 0 2006.246.08:19:40.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:19:40.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.246.08:19:40.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:19:40.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:19:40.23$vc4f8/valo=8,852.99 2006.246.08:19:40.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.246.08:19:40.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.246.08:19:40.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:40.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:19:40.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:19:40.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:19:40.23#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:19:40.23#ibcon#first serial, iclass 7, count 0 2006.246.08:19:40.23#ibcon#enter sib2, iclass 7, count 0 2006.246.08:19:40.23#ibcon#flushed, iclass 7, count 0 2006.246.08:19:40.23#ibcon#about to write, iclass 7, count 0 2006.246.08:19:40.23#ibcon#wrote, iclass 7, count 0 2006.246.08:19:40.23#ibcon#about to read 3, iclass 7, count 0 2006.246.08:19:40.25#ibcon#read 3, iclass 7, count 0 2006.246.08:19:40.25#ibcon#about to read 4, iclass 7, count 0 2006.246.08:19:40.25#ibcon#read 4, iclass 7, count 0 2006.246.08:19:40.25#ibcon#about to read 5, iclass 7, count 0 2006.246.08:19:40.25#ibcon#read 5, iclass 7, count 0 2006.246.08:19:40.25#ibcon#about to read 6, iclass 7, count 0 2006.246.08:19:40.25#ibcon#read 6, iclass 7, count 0 2006.246.08:19:40.25#ibcon#end of sib2, iclass 7, count 0 2006.246.08:19:40.25#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:19:40.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:19:40.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:19:40.25#ibcon#*before write, iclass 7, count 0 2006.246.08:19:40.25#ibcon#enter sib2, iclass 7, count 0 2006.246.08:19:40.25#ibcon#flushed, iclass 7, count 0 2006.246.08:19:40.25#ibcon#about to write, iclass 7, count 0 2006.246.08:19:40.25#ibcon#wrote, iclass 7, count 0 2006.246.08:19:40.25#ibcon#about to read 3, iclass 7, count 0 2006.246.08:19:40.29#ibcon#read 3, iclass 7, count 0 2006.246.08:19:40.29#ibcon#about to read 4, iclass 7, count 0 2006.246.08:19:40.29#ibcon#read 4, iclass 7, count 0 2006.246.08:19:40.29#ibcon#about to read 5, iclass 7, count 0 2006.246.08:19:40.29#ibcon#read 5, iclass 7, count 0 2006.246.08:19:40.29#ibcon#about to read 6, iclass 7, count 0 2006.246.08:19:40.29#ibcon#read 6, iclass 7, count 0 2006.246.08:19:40.29#ibcon#end of sib2, iclass 7, count 0 2006.246.08:19:40.29#ibcon#*after write, iclass 7, count 0 2006.246.08:19:40.29#ibcon#*before return 0, iclass 7, count 0 2006.246.08:19:40.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:19:40.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.246.08:19:40.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:19:40.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:19:40.29$vc4f8/va=8,8 2006.246.08:19:40.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.246.08:19:40.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.246.08:19:40.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:40.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:19:40.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:19:40.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:19:40.35#ibcon#enter wrdev, iclass 11, count 2 2006.246.08:19:40.35#ibcon#first serial, iclass 11, count 2 2006.246.08:19:40.35#ibcon#enter sib2, iclass 11, count 2 2006.246.08:19:40.35#ibcon#flushed, iclass 11, count 2 2006.246.08:19:40.35#ibcon#about to write, iclass 11, count 2 2006.246.08:19:40.35#ibcon#wrote, iclass 11, count 2 2006.246.08:19:40.35#ibcon#about to read 3, iclass 11, count 2 2006.246.08:19:40.37#ibcon#read 3, iclass 11, count 2 2006.246.08:19:40.37#ibcon#about to read 4, iclass 11, count 2 2006.246.08:19:40.37#ibcon#read 4, iclass 11, count 2 2006.246.08:19:40.37#ibcon#about to read 5, iclass 11, count 2 2006.246.08:19:40.37#ibcon#read 5, iclass 11, count 2 2006.246.08:19:40.37#ibcon#about to read 6, iclass 11, count 2 2006.246.08:19:40.37#ibcon#read 6, iclass 11, count 2 2006.246.08:19:40.37#ibcon#end of sib2, iclass 11, count 2 2006.246.08:19:40.37#ibcon#*mode == 0, iclass 11, count 2 2006.246.08:19:40.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.246.08:19:40.37#ibcon#[25=AT08-08\r\n] 2006.246.08:19:40.37#ibcon#*before write, iclass 11, count 2 2006.246.08:19:40.37#ibcon#enter sib2, iclass 11, count 2 2006.246.08:19:40.37#ibcon#flushed, iclass 11, count 2 2006.246.08:19:40.37#ibcon#about to write, iclass 11, count 2 2006.246.08:19:40.37#ibcon#wrote, iclass 11, count 2 2006.246.08:19:40.37#ibcon#about to read 3, iclass 11, count 2 2006.246.08:19:40.40#ibcon#read 3, iclass 11, count 2 2006.246.08:19:40.40#ibcon#about to read 4, iclass 11, count 2 2006.246.08:19:40.40#ibcon#read 4, iclass 11, count 2 2006.246.08:19:40.40#ibcon#about to read 5, iclass 11, count 2 2006.246.08:19:40.40#ibcon#read 5, iclass 11, count 2 2006.246.08:19:40.40#ibcon#about to read 6, iclass 11, count 2 2006.246.08:19:40.40#ibcon#read 6, iclass 11, count 2 2006.246.08:19:40.40#ibcon#end of sib2, iclass 11, count 2 2006.246.08:19:40.40#ibcon#*after write, iclass 11, count 2 2006.246.08:19:40.40#ibcon#*before return 0, iclass 11, count 2 2006.246.08:19:40.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:19:40.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.246.08:19:40.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.246.08:19:40.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:40.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:19:40.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:19:40.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:19:40.52#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:19:40.52#ibcon#first serial, iclass 11, count 0 2006.246.08:19:40.52#ibcon#enter sib2, iclass 11, count 0 2006.246.08:19:40.52#ibcon#flushed, iclass 11, count 0 2006.246.08:19:40.52#ibcon#about to write, iclass 11, count 0 2006.246.08:19:40.52#ibcon#wrote, iclass 11, count 0 2006.246.08:19:40.52#ibcon#about to read 3, iclass 11, count 0 2006.246.08:19:40.54#ibcon#read 3, iclass 11, count 0 2006.246.08:19:40.54#ibcon#about to read 4, iclass 11, count 0 2006.246.08:19:40.54#ibcon#read 4, iclass 11, count 0 2006.246.08:19:40.54#ibcon#about to read 5, iclass 11, count 0 2006.246.08:19:40.54#ibcon#read 5, iclass 11, count 0 2006.246.08:19:40.54#ibcon#about to read 6, iclass 11, count 0 2006.246.08:19:40.54#ibcon#read 6, iclass 11, count 0 2006.246.08:19:40.54#ibcon#end of sib2, iclass 11, count 0 2006.246.08:19:40.54#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:19:40.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:19:40.54#ibcon#[25=USB\r\n] 2006.246.08:19:40.54#ibcon#*before write, iclass 11, count 0 2006.246.08:19:40.54#ibcon#enter sib2, iclass 11, count 0 2006.246.08:19:40.54#ibcon#flushed, iclass 11, count 0 2006.246.08:19:40.54#ibcon#about to write, iclass 11, count 0 2006.246.08:19:40.54#ibcon#wrote, iclass 11, count 0 2006.246.08:19:40.54#ibcon#about to read 3, iclass 11, count 0 2006.246.08:19:40.57#ibcon#read 3, iclass 11, count 0 2006.246.08:19:40.57#ibcon#about to read 4, iclass 11, count 0 2006.246.08:19:40.57#ibcon#read 4, iclass 11, count 0 2006.246.08:19:40.57#ibcon#about to read 5, iclass 11, count 0 2006.246.08:19:40.57#ibcon#read 5, iclass 11, count 0 2006.246.08:19:40.57#ibcon#about to read 6, iclass 11, count 0 2006.246.08:19:40.57#ibcon#read 6, iclass 11, count 0 2006.246.08:19:40.57#ibcon#end of sib2, iclass 11, count 0 2006.246.08:19:40.57#ibcon#*after write, iclass 11, count 0 2006.246.08:19:40.57#ibcon#*before return 0, iclass 11, count 0 2006.246.08:19:40.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:19:40.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.246.08:19:40.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:19:40.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:19:40.57$vc4f8/vblo=1,632.99 2006.246.08:19:40.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.246.08:19:40.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.246.08:19:40.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:40.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:40.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:40.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:40.57#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:19:40.57#ibcon#first serial, iclass 13, count 0 2006.246.08:19:40.57#ibcon#enter sib2, iclass 13, count 0 2006.246.08:19:40.57#ibcon#flushed, iclass 13, count 0 2006.246.08:19:40.57#ibcon#about to write, iclass 13, count 0 2006.246.08:19:40.57#ibcon#wrote, iclass 13, count 0 2006.246.08:19:40.57#ibcon#about to read 3, iclass 13, count 0 2006.246.08:19:40.59#ibcon#read 3, iclass 13, count 0 2006.246.08:19:40.59#ibcon#about to read 4, iclass 13, count 0 2006.246.08:19:40.59#ibcon#read 4, iclass 13, count 0 2006.246.08:19:40.59#ibcon#about to read 5, iclass 13, count 0 2006.246.08:19:40.59#ibcon#read 5, iclass 13, count 0 2006.246.08:19:40.59#ibcon#about to read 6, iclass 13, count 0 2006.246.08:19:40.59#ibcon#read 6, iclass 13, count 0 2006.246.08:19:40.59#ibcon#end of sib2, iclass 13, count 0 2006.246.08:19:40.59#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:19:40.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:19:40.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:19:40.59#ibcon#*before write, iclass 13, count 0 2006.246.08:19:40.59#ibcon#enter sib2, iclass 13, count 0 2006.246.08:19:40.59#ibcon#flushed, iclass 13, count 0 2006.246.08:19:40.59#ibcon#about to write, iclass 13, count 0 2006.246.08:19:40.59#ibcon#wrote, iclass 13, count 0 2006.246.08:19:40.59#ibcon#about to read 3, iclass 13, count 0 2006.246.08:19:40.63#ibcon#read 3, iclass 13, count 0 2006.246.08:19:40.63#ibcon#about to read 4, iclass 13, count 0 2006.246.08:19:40.63#ibcon#read 4, iclass 13, count 0 2006.246.08:19:40.63#ibcon#about to read 5, iclass 13, count 0 2006.246.08:19:40.63#ibcon#read 5, iclass 13, count 0 2006.246.08:19:40.63#ibcon#about to read 6, iclass 13, count 0 2006.246.08:19:40.63#ibcon#read 6, iclass 13, count 0 2006.246.08:19:40.63#ibcon#end of sib2, iclass 13, count 0 2006.246.08:19:40.63#ibcon#*after write, iclass 13, count 0 2006.246.08:19:40.63#ibcon#*before return 0, iclass 13, count 0 2006.246.08:19:40.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:40.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.246.08:19:40.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:19:40.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:19:40.63$vc4f8/vb=1,4 2006.246.08:19:40.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.246.08:19:40.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.246.08:19:40.63#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:40.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:40.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:40.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:40.63#ibcon#enter wrdev, iclass 15, count 2 2006.246.08:19:40.63#ibcon#first serial, iclass 15, count 2 2006.246.08:19:40.63#ibcon#enter sib2, iclass 15, count 2 2006.246.08:19:40.63#ibcon#flushed, iclass 15, count 2 2006.246.08:19:40.63#ibcon#about to write, iclass 15, count 2 2006.246.08:19:40.63#ibcon#wrote, iclass 15, count 2 2006.246.08:19:40.63#ibcon#about to read 3, iclass 15, count 2 2006.246.08:19:40.65#ibcon#read 3, iclass 15, count 2 2006.246.08:19:40.65#ibcon#about to read 4, iclass 15, count 2 2006.246.08:19:40.65#ibcon#read 4, iclass 15, count 2 2006.246.08:19:40.65#ibcon#about to read 5, iclass 15, count 2 2006.246.08:19:40.65#ibcon#read 5, iclass 15, count 2 2006.246.08:19:40.65#ibcon#about to read 6, iclass 15, count 2 2006.246.08:19:40.65#ibcon#read 6, iclass 15, count 2 2006.246.08:19:40.65#ibcon#end of sib2, iclass 15, count 2 2006.246.08:19:40.65#ibcon#*mode == 0, iclass 15, count 2 2006.246.08:19:40.65#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.246.08:19:40.65#ibcon#[27=AT01-04\r\n] 2006.246.08:19:40.65#ibcon#*before write, iclass 15, count 2 2006.246.08:19:40.65#ibcon#enter sib2, iclass 15, count 2 2006.246.08:19:40.65#ibcon#flushed, iclass 15, count 2 2006.246.08:19:40.65#ibcon#about to write, iclass 15, count 2 2006.246.08:19:40.65#ibcon#wrote, iclass 15, count 2 2006.246.08:19:40.65#ibcon#about to read 3, iclass 15, count 2 2006.246.08:19:40.68#ibcon#read 3, iclass 15, count 2 2006.246.08:19:40.68#ibcon#about to read 4, iclass 15, count 2 2006.246.08:19:40.68#ibcon#read 4, iclass 15, count 2 2006.246.08:19:40.68#ibcon#about to read 5, iclass 15, count 2 2006.246.08:19:40.68#ibcon#read 5, iclass 15, count 2 2006.246.08:19:40.68#ibcon#about to read 6, iclass 15, count 2 2006.246.08:19:40.68#ibcon#read 6, iclass 15, count 2 2006.246.08:19:40.68#ibcon#end of sib2, iclass 15, count 2 2006.246.08:19:40.68#ibcon#*after write, iclass 15, count 2 2006.246.08:19:40.68#ibcon#*before return 0, iclass 15, count 2 2006.246.08:19:40.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:40.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.246.08:19:40.68#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.246.08:19:40.68#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:40.68#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:40.80#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:40.80#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:40.80#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:19:40.80#ibcon#first serial, iclass 15, count 0 2006.246.08:19:40.80#ibcon#enter sib2, iclass 15, count 0 2006.246.08:19:40.80#ibcon#flushed, iclass 15, count 0 2006.246.08:19:40.80#ibcon#about to write, iclass 15, count 0 2006.246.08:19:40.80#ibcon#wrote, iclass 15, count 0 2006.246.08:19:40.80#ibcon#about to read 3, iclass 15, count 0 2006.246.08:19:40.82#ibcon#read 3, iclass 15, count 0 2006.246.08:19:40.82#ibcon#about to read 4, iclass 15, count 0 2006.246.08:19:40.82#ibcon#read 4, iclass 15, count 0 2006.246.08:19:40.82#ibcon#about to read 5, iclass 15, count 0 2006.246.08:19:40.82#ibcon#read 5, iclass 15, count 0 2006.246.08:19:40.82#ibcon#about to read 6, iclass 15, count 0 2006.246.08:19:40.82#ibcon#read 6, iclass 15, count 0 2006.246.08:19:40.82#ibcon#end of sib2, iclass 15, count 0 2006.246.08:19:40.82#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:19:40.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:19:40.82#ibcon#[27=USB\r\n] 2006.246.08:19:40.82#ibcon#*before write, iclass 15, count 0 2006.246.08:19:40.82#ibcon#enter sib2, iclass 15, count 0 2006.246.08:19:40.82#ibcon#flushed, iclass 15, count 0 2006.246.08:19:40.82#ibcon#about to write, iclass 15, count 0 2006.246.08:19:40.82#ibcon#wrote, iclass 15, count 0 2006.246.08:19:40.82#ibcon#about to read 3, iclass 15, count 0 2006.246.08:19:40.85#ibcon#read 3, iclass 15, count 0 2006.246.08:19:40.85#ibcon#about to read 4, iclass 15, count 0 2006.246.08:19:40.85#ibcon#read 4, iclass 15, count 0 2006.246.08:19:40.85#ibcon#about to read 5, iclass 15, count 0 2006.246.08:19:40.85#ibcon#read 5, iclass 15, count 0 2006.246.08:19:40.85#ibcon#about to read 6, iclass 15, count 0 2006.246.08:19:40.85#ibcon#read 6, iclass 15, count 0 2006.246.08:19:40.85#ibcon#end of sib2, iclass 15, count 0 2006.246.08:19:40.85#ibcon#*after write, iclass 15, count 0 2006.246.08:19:40.85#ibcon#*before return 0, iclass 15, count 0 2006.246.08:19:40.85#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:40.85#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.246.08:19:40.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:19:40.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:19:40.85$vc4f8/vblo=2,640.99 2006.246.08:19:40.85#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.246.08:19:40.85#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.246.08:19:40.85#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:40.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:40.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:40.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:40.85#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:19:40.85#ibcon#first serial, iclass 17, count 0 2006.246.08:19:40.85#ibcon#enter sib2, iclass 17, count 0 2006.246.08:19:40.85#ibcon#flushed, iclass 17, count 0 2006.246.08:19:40.85#ibcon#about to write, iclass 17, count 0 2006.246.08:19:40.85#ibcon#wrote, iclass 17, count 0 2006.246.08:19:40.85#ibcon#about to read 3, iclass 17, count 0 2006.246.08:19:40.87#ibcon#read 3, iclass 17, count 0 2006.246.08:19:40.87#ibcon#about to read 4, iclass 17, count 0 2006.246.08:19:40.87#ibcon#read 4, iclass 17, count 0 2006.246.08:19:40.87#ibcon#about to read 5, iclass 17, count 0 2006.246.08:19:40.87#ibcon#read 5, iclass 17, count 0 2006.246.08:19:40.87#ibcon#about to read 6, iclass 17, count 0 2006.246.08:19:40.87#ibcon#read 6, iclass 17, count 0 2006.246.08:19:40.87#ibcon#end of sib2, iclass 17, count 0 2006.246.08:19:40.87#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:19:40.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:19:40.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:19:40.87#ibcon#*before write, iclass 17, count 0 2006.246.08:19:40.87#ibcon#enter sib2, iclass 17, count 0 2006.246.08:19:40.87#ibcon#flushed, iclass 17, count 0 2006.246.08:19:40.87#ibcon#about to write, iclass 17, count 0 2006.246.08:19:40.87#ibcon#wrote, iclass 17, count 0 2006.246.08:19:40.87#ibcon#about to read 3, iclass 17, count 0 2006.246.08:19:40.91#ibcon#read 3, iclass 17, count 0 2006.246.08:19:40.91#ibcon#about to read 4, iclass 17, count 0 2006.246.08:19:40.91#ibcon#read 4, iclass 17, count 0 2006.246.08:19:40.91#ibcon#about to read 5, iclass 17, count 0 2006.246.08:19:40.91#ibcon#read 5, iclass 17, count 0 2006.246.08:19:40.91#ibcon#about to read 6, iclass 17, count 0 2006.246.08:19:40.91#ibcon#read 6, iclass 17, count 0 2006.246.08:19:40.91#ibcon#end of sib2, iclass 17, count 0 2006.246.08:19:40.91#ibcon#*after write, iclass 17, count 0 2006.246.08:19:40.91#ibcon#*before return 0, iclass 17, count 0 2006.246.08:19:40.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:40.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.246.08:19:40.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:19:40.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:19:40.91$vc4f8/vb=2,4 2006.246.08:19:40.91#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.246.08:19:40.91#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.246.08:19:40.91#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:40.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:40.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:40.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:40.97#ibcon#enter wrdev, iclass 19, count 2 2006.246.08:19:40.97#ibcon#first serial, iclass 19, count 2 2006.246.08:19:40.97#ibcon#enter sib2, iclass 19, count 2 2006.246.08:19:40.97#ibcon#flushed, iclass 19, count 2 2006.246.08:19:40.97#ibcon#about to write, iclass 19, count 2 2006.246.08:19:40.97#ibcon#wrote, iclass 19, count 2 2006.246.08:19:40.97#ibcon#about to read 3, iclass 19, count 2 2006.246.08:19:40.99#ibcon#read 3, iclass 19, count 2 2006.246.08:19:40.99#ibcon#about to read 4, iclass 19, count 2 2006.246.08:19:40.99#ibcon#read 4, iclass 19, count 2 2006.246.08:19:40.99#ibcon#about to read 5, iclass 19, count 2 2006.246.08:19:40.99#ibcon#read 5, iclass 19, count 2 2006.246.08:19:40.99#ibcon#about to read 6, iclass 19, count 2 2006.246.08:19:40.99#ibcon#read 6, iclass 19, count 2 2006.246.08:19:40.99#ibcon#end of sib2, iclass 19, count 2 2006.246.08:19:40.99#ibcon#*mode == 0, iclass 19, count 2 2006.246.08:19:40.99#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.246.08:19:40.99#ibcon#[27=AT02-04\r\n] 2006.246.08:19:40.99#ibcon#*before write, iclass 19, count 2 2006.246.08:19:40.99#ibcon#enter sib2, iclass 19, count 2 2006.246.08:19:40.99#ibcon#flushed, iclass 19, count 2 2006.246.08:19:40.99#ibcon#about to write, iclass 19, count 2 2006.246.08:19:40.99#ibcon#wrote, iclass 19, count 2 2006.246.08:19:40.99#ibcon#about to read 3, iclass 19, count 2 2006.246.08:19:41.02#ibcon#read 3, iclass 19, count 2 2006.246.08:19:41.02#ibcon#about to read 4, iclass 19, count 2 2006.246.08:19:41.02#ibcon#read 4, iclass 19, count 2 2006.246.08:19:41.02#ibcon#about to read 5, iclass 19, count 2 2006.246.08:19:41.02#ibcon#read 5, iclass 19, count 2 2006.246.08:19:41.02#ibcon#about to read 6, iclass 19, count 2 2006.246.08:19:41.02#ibcon#read 6, iclass 19, count 2 2006.246.08:19:41.02#ibcon#end of sib2, iclass 19, count 2 2006.246.08:19:41.02#ibcon#*after write, iclass 19, count 2 2006.246.08:19:41.02#ibcon#*before return 0, iclass 19, count 2 2006.246.08:19:41.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:41.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.246.08:19:41.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.246.08:19:41.02#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:41.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:41.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:41.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:41.14#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:19:41.14#ibcon#first serial, iclass 19, count 0 2006.246.08:19:41.14#ibcon#enter sib2, iclass 19, count 0 2006.246.08:19:41.14#ibcon#flushed, iclass 19, count 0 2006.246.08:19:41.14#ibcon#about to write, iclass 19, count 0 2006.246.08:19:41.14#ibcon#wrote, iclass 19, count 0 2006.246.08:19:41.14#ibcon#about to read 3, iclass 19, count 0 2006.246.08:19:41.16#ibcon#read 3, iclass 19, count 0 2006.246.08:19:41.16#ibcon#about to read 4, iclass 19, count 0 2006.246.08:19:41.16#ibcon#read 4, iclass 19, count 0 2006.246.08:19:41.16#ibcon#about to read 5, iclass 19, count 0 2006.246.08:19:41.16#ibcon#read 5, iclass 19, count 0 2006.246.08:19:41.16#ibcon#about to read 6, iclass 19, count 0 2006.246.08:19:41.16#ibcon#read 6, iclass 19, count 0 2006.246.08:19:41.16#ibcon#end of sib2, iclass 19, count 0 2006.246.08:19:41.16#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:19:41.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:19:41.16#ibcon#[27=USB\r\n] 2006.246.08:19:41.16#ibcon#*before write, iclass 19, count 0 2006.246.08:19:41.16#ibcon#enter sib2, iclass 19, count 0 2006.246.08:19:41.16#ibcon#flushed, iclass 19, count 0 2006.246.08:19:41.16#ibcon#about to write, iclass 19, count 0 2006.246.08:19:41.16#ibcon#wrote, iclass 19, count 0 2006.246.08:19:41.16#ibcon#about to read 3, iclass 19, count 0 2006.246.08:19:41.19#ibcon#read 3, iclass 19, count 0 2006.246.08:19:41.19#ibcon#about to read 4, iclass 19, count 0 2006.246.08:19:41.19#ibcon#read 4, iclass 19, count 0 2006.246.08:19:41.19#ibcon#about to read 5, iclass 19, count 0 2006.246.08:19:41.19#ibcon#read 5, iclass 19, count 0 2006.246.08:19:41.19#ibcon#about to read 6, iclass 19, count 0 2006.246.08:19:41.19#ibcon#read 6, iclass 19, count 0 2006.246.08:19:41.19#ibcon#end of sib2, iclass 19, count 0 2006.246.08:19:41.19#ibcon#*after write, iclass 19, count 0 2006.246.08:19:41.19#ibcon#*before return 0, iclass 19, count 0 2006.246.08:19:41.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:41.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.246.08:19:41.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:19:41.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:19:41.19$vc4f8/vblo=3,656.99 2006.246.08:19:41.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.08:19:41.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.08:19:41.19#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:41.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:41.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:41.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:41.19#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:19:41.19#ibcon#first serial, iclass 21, count 0 2006.246.08:19:41.19#ibcon#enter sib2, iclass 21, count 0 2006.246.08:19:41.19#ibcon#flushed, iclass 21, count 0 2006.246.08:19:41.19#ibcon#about to write, iclass 21, count 0 2006.246.08:19:41.19#ibcon#wrote, iclass 21, count 0 2006.246.08:19:41.19#ibcon#about to read 3, iclass 21, count 0 2006.246.08:19:41.21#ibcon#read 3, iclass 21, count 0 2006.246.08:19:41.21#ibcon#about to read 4, iclass 21, count 0 2006.246.08:19:41.21#ibcon#read 4, iclass 21, count 0 2006.246.08:19:41.21#ibcon#about to read 5, iclass 21, count 0 2006.246.08:19:41.21#ibcon#read 5, iclass 21, count 0 2006.246.08:19:41.21#ibcon#about to read 6, iclass 21, count 0 2006.246.08:19:41.21#ibcon#read 6, iclass 21, count 0 2006.246.08:19:41.21#ibcon#end of sib2, iclass 21, count 0 2006.246.08:19:41.21#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:19:41.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:19:41.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:19:41.21#ibcon#*before write, iclass 21, count 0 2006.246.08:19:41.21#ibcon#enter sib2, iclass 21, count 0 2006.246.08:19:41.21#ibcon#flushed, iclass 21, count 0 2006.246.08:19:41.21#ibcon#about to write, iclass 21, count 0 2006.246.08:19:41.21#ibcon#wrote, iclass 21, count 0 2006.246.08:19:41.21#ibcon#about to read 3, iclass 21, count 0 2006.246.08:19:41.25#ibcon#read 3, iclass 21, count 0 2006.246.08:19:41.25#ibcon#about to read 4, iclass 21, count 0 2006.246.08:19:41.25#ibcon#read 4, iclass 21, count 0 2006.246.08:19:41.25#ibcon#about to read 5, iclass 21, count 0 2006.246.08:19:41.25#ibcon#read 5, iclass 21, count 0 2006.246.08:19:41.25#ibcon#about to read 6, iclass 21, count 0 2006.246.08:19:41.25#ibcon#read 6, iclass 21, count 0 2006.246.08:19:41.25#ibcon#end of sib2, iclass 21, count 0 2006.246.08:19:41.25#ibcon#*after write, iclass 21, count 0 2006.246.08:19:41.25#ibcon#*before return 0, iclass 21, count 0 2006.246.08:19:41.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:41.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:19:41.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:19:41.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:19:41.25$vc4f8/vb=3,4 2006.246.08:19:41.25#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.246.08:19:41.25#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.246.08:19:41.25#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:41.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:41.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:41.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:41.31#ibcon#enter wrdev, iclass 23, count 2 2006.246.08:19:41.31#ibcon#first serial, iclass 23, count 2 2006.246.08:19:41.31#ibcon#enter sib2, iclass 23, count 2 2006.246.08:19:41.31#ibcon#flushed, iclass 23, count 2 2006.246.08:19:41.31#ibcon#about to write, iclass 23, count 2 2006.246.08:19:41.31#ibcon#wrote, iclass 23, count 2 2006.246.08:19:41.31#ibcon#about to read 3, iclass 23, count 2 2006.246.08:19:41.33#ibcon#read 3, iclass 23, count 2 2006.246.08:19:41.33#ibcon#about to read 4, iclass 23, count 2 2006.246.08:19:41.33#ibcon#read 4, iclass 23, count 2 2006.246.08:19:41.33#ibcon#about to read 5, iclass 23, count 2 2006.246.08:19:41.33#ibcon#read 5, iclass 23, count 2 2006.246.08:19:41.33#ibcon#about to read 6, iclass 23, count 2 2006.246.08:19:41.33#ibcon#read 6, iclass 23, count 2 2006.246.08:19:41.33#ibcon#end of sib2, iclass 23, count 2 2006.246.08:19:41.33#ibcon#*mode == 0, iclass 23, count 2 2006.246.08:19:41.33#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.246.08:19:41.33#ibcon#[27=AT03-04\r\n] 2006.246.08:19:41.33#ibcon#*before write, iclass 23, count 2 2006.246.08:19:41.33#ibcon#enter sib2, iclass 23, count 2 2006.246.08:19:41.33#ibcon#flushed, iclass 23, count 2 2006.246.08:19:41.33#ibcon#about to write, iclass 23, count 2 2006.246.08:19:41.33#ibcon#wrote, iclass 23, count 2 2006.246.08:19:41.33#ibcon#about to read 3, iclass 23, count 2 2006.246.08:19:41.36#ibcon#read 3, iclass 23, count 2 2006.246.08:19:41.36#ibcon#about to read 4, iclass 23, count 2 2006.246.08:19:41.36#ibcon#read 4, iclass 23, count 2 2006.246.08:19:41.36#ibcon#about to read 5, iclass 23, count 2 2006.246.08:19:41.36#ibcon#read 5, iclass 23, count 2 2006.246.08:19:41.36#ibcon#about to read 6, iclass 23, count 2 2006.246.08:19:41.36#ibcon#read 6, iclass 23, count 2 2006.246.08:19:41.36#ibcon#end of sib2, iclass 23, count 2 2006.246.08:19:41.36#ibcon#*after write, iclass 23, count 2 2006.246.08:19:41.36#ibcon#*before return 0, iclass 23, count 2 2006.246.08:19:41.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:41.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.246.08:19:41.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.246.08:19:41.36#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:41.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:41.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:41.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:41.48#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:19:41.48#ibcon#first serial, iclass 23, count 0 2006.246.08:19:41.48#ibcon#enter sib2, iclass 23, count 0 2006.246.08:19:41.48#ibcon#flushed, iclass 23, count 0 2006.246.08:19:41.48#ibcon#about to write, iclass 23, count 0 2006.246.08:19:41.48#ibcon#wrote, iclass 23, count 0 2006.246.08:19:41.48#ibcon#about to read 3, iclass 23, count 0 2006.246.08:19:41.50#ibcon#read 3, iclass 23, count 0 2006.246.08:19:41.50#ibcon#about to read 4, iclass 23, count 0 2006.246.08:19:41.50#ibcon#read 4, iclass 23, count 0 2006.246.08:19:41.50#ibcon#about to read 5, iclass 23, count 0 2006.246.08:19:41.50#ibcon#read 5, iclass 23, count 0 2006.246.08:19:41.50#ibcon#about to read 6, iclass 23, count 0 2006.246.08:19:41.50#ibcon#read 6, iclass 23, count 0 2006.246.08:19:41.50#ibcon#end of sib2, iclass 23, count 0 2006.246.08:19:41.50#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:19:41.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:19:41.50#ibcon#[27=USB\r\n] 2006.246.08:19:41.50#ibcon#*before write, iclass 23, count 0 2006.246.08:19:41.50#ibcon#enter sib2, iclass 23, count 0 2006.246.08:19:41.50#ibcon#flushed, iclass 23, count 0 2006.246.08:19:41.50#ibcon#about to write, iclass 23, count 0 2006.246.08:19:41.50#ibcon#wrote, iclass 23, count 0 2006.246.08:19:41.50#ibcon#about to read 3, iclass 23, count 0 2006.246.08:19:41.53#ibcon#read 3, iclass 23, count 0 2006.246.08:19:41.53#ibcon#about to read 4, iclass 23, count 0 2006.246.08:19:41.53#ibcon#read 4, iclass 23, count 0 2006.246.08:19:41.53#ibcon#about to read 5, iclass 23, count 0 2006.246.08:19:41.53#ibcon#read 5, iclass 23, count 0 2006.246.08:19:41.53#ibcon#about to read 6, iclass 23, count 0 2006.246.08:19:41.53#ibcon#read 6, iclass 23, count 0 2006.246.08:19:41.53#ibcon#end of sib2, iclass 23, count 0 2006.246.08:19:41.53#ibcon#*after write, iclass 23, count 0 2006.246.08:19:41.53#ibcon#*before return 0, iclass 23, count 0 2006.246.08:19:41.53#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:41.53#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.246.08:19:41.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:19:41.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:19:41.53$vc4f8/vblo=4,712.99 2006.246.08:19:41.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.246.08:19:41.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.246.08:19:41.53#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:41.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:41.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:41.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:41.53#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:19:41.53#ibcon#first serial, iclass 25, count 0 2006.246.08:19:41.53#ibcon#enter sib2, iclass 25, count 0 2006.246.08:19:41.53#ibcon#flushed, iclass 25, count 0 2006.246.08:19:41.53#ibcon#about to write, iclass 25, count 0 2006.246.08:19:41.53#ibcon#wrote, iclass 25, count 0 2006.246.08:19:41.53#ibcon#about to read 3, iclass 25, count 0 2006.246.08:19:41.55#ibcon#read 3, iclass 25, count 0 2006.246.08:19:41.55#ibcon#about to read 4, iclass 25, count 0 2006.246.08:19:41.55#ibcon#read 4, iclass 25, count 0 2006.246.08:19:41.55#ibcon#about to read 5, iclass 25, count 0 2006.246.08:19:41.55#ibcon#read 5, iclass 25, count 0 2006.246.08:19:41.55#ibcon#about to read 6, iclass 25, count 0 2006.246.08:19:41.55#ibcon#read 6, iclass 25, count 0 2006.246.08:19:41.55#ibcon#end of sib2, iclass 25, count 0 2006.246.08:19:41.55#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:19:41.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:19:41.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:19:41.55#ibcon#*before write, iclass 25, count 0 2006.246.08:19:41.55#ibcon#enter sib2, iclass 25, count 0 2006.246.08:19:41.55#ibcon#flushed, iclass 25, count 0 2006.246.08:19:41.55#ibcon#about to write, iclass 25, count 0 2006.246.08:19:41.55#ibcon#wrote, iclass 25, count 0 2006.246.08:19:41.55#ibcon#about to read 3, iclass 25, count 0 2006.246.08:19:41.59#ibcon#read 3, iclass 25, count 0 2006.246.08:19:41.59#ibcon#about to read 4, iclass 25, count 0 2006.246.08:19:41.59#ibcon#read 4, iclass 25, count 0 2006.246.08:19:41.59#ibcon#about to read 5, iclass 25, count 0 2006.246.08:19:41.59#ibcon#read 5, iclass 25, count 0 2006.246.08:19:41.59#ibcon#about to read 6, iclass 25, count 0 2006.246.08:19:41.59#ibcon#read 6, iclass 25, count 0 2006.246.08:19:41.59#ibcon#end of sib2, iclass 25, count 0 2006.246.08:19:41.59#ibcon#*after write, iclass 25, count 0 2006.246.08:19:41.59#ibcon#*before return 0, iclass 25, count 0 2006.246.08:19:41.59#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:41.59#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.246.08:19:41.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:19:41.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:19:41.59$vc4f8/vb=4,4 2006.246.08:19:41.59#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.246.08:19:41.59#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.246.08:19:41.59#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:41.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:19:41.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:19:41.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:19:41.65#ibcon#enter wrdev, iclass 27, count 2 2006.246.08:19:41.65#ibcon#first serial, iclass 27, count 2 2006.246.08:19:41.65#ibcon#enter sib2, iclass 27, count 2 2006.246.08:19:41.65#ibcon#flushed, iclass 27, count 2 2006.246.08:19:41.65#ibcon#about to write, iclass 27, count 2 2006.246.08:19:41.65#ibcon#wrote, iclass 27, count 2 2006.246.08:19:41.65#ibcon#about to read 3, iclass 27, count 2 2006.246.08:19:41.67#ibcon#read 3, iclass 27, count 2 2006.246.08:19:41.67#ibcon#about to read 4, iclass 27, count 2 2006.246.08:19:41.67#ibcon#read 4, iclass 27, count 2 2006.246.08:19:41.67#ibcon#about to read 5, iclass 27, count 2 2006.246.08:19:41.67#ibcon#read 5, iclass 27, count 2 2006.246.08:19:41.67#ibcon#about to read 6, iclass 27, count 2 2006.246.08:19:41.67#ibcon#read 6, iclass 27, count 2 2006.246.08:19:41.67#ibcon#end of sib2, iclass 27, count 2 2006.246.08:19:41.67#ibcon#*mode == 0, iclass 27, count 2 2006.246.08:19:41.67#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.246.08:19:41.67#ibcon#[27=AT04-04\r\n] 2006.246.08:19:41.67#ibcon#*before write, iclass 27, count 2 2006.246.08:19:41.67#ibcon#enter sib2, iclass 27, count 2 2006.246.08:19:41.67#ibcon#flushed, iclass 27, count 2 2006.246.08:19:41.67#ibcon#about to write, iclass 27, count 2 2006.246.08:19:41.67#ibcon#wrote, iclass 27, count 2 2006.246.08:19:41.67#ibcon#about to read 3, iclass 27, count 2 2006.246.08:19:41.70#ibcon#read 3, iclass 27, count 2 2006.246.08:19:41.70#ibcon#about to read 4, iclass 27, count 2 2006.246.08:19:41.70#ibcon#read 4, iclass 27, count 2 2006.246.08:19:41.70#ibcon#about to read 5, iclass 27, count 2 2006.246.08:19:41.70#ibcon#read 5, iclass 27, count 2 2006.246.08:19:41.70#ibcon#about to read 6, iclass 27, count 2 2006.246.08:19:41.70#ibcon#read 6, iclass 27, count 2 2006.246.08:19:41.70#ibcon#end of sib2, iclass 27, count 2 2006.246.08:19:41.70#ibcon#*after write, iclass 27, count 2 2006.246.08:19:41.70#ibcon#*before return 0, iclass 27, count 2 2006.246.08:19:41.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:19:41.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.246.08:19:41.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.246.08:19:41.70#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:41.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:19:41.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:19:41.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:19:41.82#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:19:41.82#ibcon#first serial, iclass 27, count 0 2006.246.08:19:41.82#ibcon#enter sib2, iclass 27, count 0 2006.246.08:19:41.82#ibcon#flushed, iclass 27, count 0 2006.246.08:19:41.82#ibcon#about to write, iclass 27, count 0 2006.246.08:19:41.82#ibcon#wrote, iclass 27, count 0 2006.246.08:19:41.82#ibcon#about to read 3, iclass 27, count 0 2006.246.08:19:41.84#ibcon#read 3, iclass 27, count 0 2006.246.08:19:41.84#ibcon#about to read 4, iclass 27, count 0 2006.246.08:19:41.84#ibcon#read 4, iclass 27, count 0 2006.246.08:19:41.84#ibcon#about to read 5, iclass 27, count 0 2006.246.08:19:41.84#ibcon#read 5, iclass 27, count 0 2006.246.08:19:41.84#ibcon#about to read 6, iclass 27, count 0 2006.246.08:19:41.84#ibcon#read 6, iclass 27, count 0 2006.246.08:19:41.84#ibcon#end of sib2, iclass 27, count 0 2006.246.08:19:41.84#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:19:41.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:19:41.84#ibcon#[27=USB\r\n] 2006.246.08:19:41.84#ibcon#*before write, iclass 27, count 0 2006.246.08:19:41.84#ibcon#enter sib2, iclass 27, count 0 2006.246.08:19:41.84#ibcon#flushed, iclass 27, count 0 2006.246.08:19:41.84#ibcon#about to write, iclass 27, count 0 2006.246.08:19:41.84#ibcon#wrote, iclass 27, count 0 2006.246.08:19:41.84#ibcon#about to read 3, iclass 27, count 0 2006.246.08:19:41.87#ibcon#read 3, iclass 27, count 0 2006.246.08:19:41.87#ibcon#about to read 4, iclass 27, count 0 2006.246.08:19:41.87#ibcon#read 4, iclass 27, count 0 2006.246.08:19:41.87#ibcon#about to read 5, iclass 27, count 0 2006.246.08:19:41.87#ibcon#read 5, iclass 27, count 0 2006.246.08:19:41.87#ibcon#about to read 6, iclass 27, count 0 2006.246.08:19:41.87#ibcon#read 6, iclass 27, count 0 2006.246.08:19:41.87#ibcon#end of sib2, iclass 27, count 0 2006.246.08:19:41.87#ibcon#*after write, iclass 27, count 0 2006.246.08:19:41.87#ibcon#*before return 0, iclass 27, count 0 2006.246.08:19:41.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:19:41.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.246.08:19:41.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:19:41.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:19:41.87$vc4f8/vblo=5,744.99 2006.246.08:19:41.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.246.08:19:41.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.246.08:19:41.87#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:41.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:19:41.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:19:41.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:19:41.87#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:19:41.87#ibcon#first serial, iclass 29, count 0 2006.246.08:19:41.87#ibcon#enter sib2, iclass 29, count 0 2006.246.08:19:41.87#ibcon#flushed, iclass 29, count 0 2006.246.08:19:41.87#ibcon#about to write, iclass 29, count 0 2006.246.08:19:41.87#ibcon#wrote, iclass 29, count 0 2006.246.08:19:41.87#ibcon#about to read 3, iclass 29, count 0 2006.246.08:19:41.89#ibcon#read 3, iclass 29, count 0 2006.246.08:19:41.89#ibcon#about to read 4, iclass 29, count 0 2006.246.08:19:41.89#ibcon#read 4, iclass 29, count 0 2006.246.08:19:41.89#ibcon#about to read 5, iclass 29, count 0 2006.246.08:19:41.89#ibcon#read 5, iclass 29, count 0 2006.246.08:19:41.89#ibcon#about to read 6, iclass 29, count 0 2006.246.08:19:41.89#ibcon#read 6, iclass 29, count 0 2006.246.08:19:41.89#ibcon#end of sib2, iclass 29, count 0 2006.246.08:19:41.89#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:19:41.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:19:41.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:19:41.89#ibcon#*before write, iclass 29, count 0 2006.246.08:19:41.89#ibcon#enter sib2, iclass 29, count 0 2006.246.08:19:41.89#ibcon#flushed, iclass 29, count 0 2006.246.08:19:41.89#ibcon#about to write, iclass 29, count 0 2006.246.08:19:41.89#ibcon#wrote, iclass 29, count 0 2006.246.08:19:41.89#ibcon#about to read 3, iclass 29, count 0 2006.246.08:19:41.93#ibcon#read 3, iclass 29, count 0 2006.246.08:19:41.93#ibcon#about to read 4, iclass 29, count 0 2006.246.08:19:41.93#ibcon#read 4, iclass 29, count 0 2006.246.08:19:41.93#ibcon#about to read 5, iclass 29, count 0 2006.246.08:19:41.93#ibcon#read 5, iclass 29, count 0 2006.246.08:19:41.93#ibcon#about to read 6, iclass 29, count 0 2006.246.08:19:41.93#ibcon#read 6, iclass 29, count 0 2006.246.08:19:41.93#ibcon#end of sib2, iclass 29, count 0 2006.246.08:19:41.93#ibcon#*after write, iclass 29, count 0 2006.246.08:19:41.93#ibcon#*before return 0, iclass 29, count 0 2006.246.08:19:41.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:19:41.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.246.08:19:41.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:19:41.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:19:41.93$vc4f8/vb=5,3 2006.246.08:19:41.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.246.08:19:41.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.246.08:19:41.93#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:41.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:19:41.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:19:41.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:19:41.99#ibcon#enter wrdev, iclass 31, count 2 2006.246.08:19:41.99#ibcon#first serial, iclass 31, count 2 2006.246.08:19:41.99#ibcon#enter sib2, iclass 31, count 2 2006.246.08:19:41.99#ibcon#flushed, iclass 31, count 2 2006.246.08:19:41.99#ibcon#about to write, iclass 31, count 2 2006.246.08:19:41.99#ibcon#wrote, iclass 31, count 2 2006.246.08:19:41.99#ibcon#about to read 3, iclass 31, count 2 2006.246.08:19:42.01#ibcon#read 3, iclass 31, count 2 2006.246.08:19:42.01#ibcon#about to read 4, iclass 31, count 2 2006.246.08:19:42.01#ibcon#read 4, iclass 31, count 2 2006.246.08:19:42.01#ibcon#about to read 5, iclass 31, count 2 2006.246.08:19:42.01#ibcon#read 5, iclass 31, count 2 2006.246.08:19:42.01#ibcon#about to read 6, iclass 31, count 2 2006.246.08:19:42.01#ibcon#read 6, iclass 31, count 2 2006.246.08:19:42.01#ibcon#end of sib2, iclass 31, count 2 2006.246.08:19:42.01#ibcon#*mode == 0, iclass 31, count 2 2006.246.08:19:42.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.246.08:19:42.01#ibcon#[27=AT05-03\r\n] 2006.246.08:19:42.01#ibcon#*before write, iclass 31, count 2 2006.246.08:19:42.01#ibcon#enter sib2, iclass 31, count 2 2006.246.08:19:42.01#ibcon#flushed, iclass 31, count 2 2006.246.08:19:42.01#ibcon#about to write, iclass 31, count 2 2006.246.08:19:42.01#ibcon#wrote, iclass 31, count 2 2006.246.08:19:42.01#ibcon#about to read 3, iclass 31, count 2 2006.246.08:19:42.04#ibcon#read 3, iclass 31, count 2 2006.246.08:19:42.04#ibcon#about to read 4, iclass 31, count 2 2006.246.08:19:42.04#ibcon#read 4, iclass 31, count 2 2006.246.08:19:42.04#ibcon#about to read 5, iclass 31, count 2 2006.246.08:19:42.04#ibcon#read 5, iclass 31, count 2 2006.246.08:19:42.04#ibcon#about to read 6, iclass 31, count 2 2006.246.08:19:42.04#ibcon#read 6, iclass 31, count 2 2006.246.08:19:42.04#ibcon#end of sib2, iclass 31, count 2 2006.246.08:19:42.04#ibcon#*after write, iclass 31, count 2 2006.246.08:19:42.04#ibcon#*before return 0, iclass 31, count 2 2006.246.08:19:42.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:19:42.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.246.08:19:42.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.246.08:19:42.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:42.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:19:42.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:19:42.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:19:42.16#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:19:42.16#ibcon#first serial, iclass 31, count 0 2006.246.08:19:42.16#ibcon#enter sib2, iclass 31, count 0 2006.246.08:19:42.16#ibcon#flushed, iclass 31, count 0 2006.246.08:19:42.16#ibcon#about to write, iclass 31, count 0 2006.246.08:19:42.16#ibcon#wrote, iclass 31, count 0 2006.246.08:19:42.16#ibcon#about to read 3, iclass 31, count 0 2006.246.08:19:42.20#ibcon#read 3, iclass 31, count 0 2006.246.08:19:42.20#ibcon#about to read 4, iclass 31, count 0 2006.246.08:19:42.20#ibcon#read 4, iclass 31, count 0 2006.246.08:19:42.20#ibcon#about to read 5, iclass 31, count 0 2006.246.08:19:42.20#ibcon#read 5, iclass 31, count 0 2006.246.08:19:42.20#ibcon#about to read 6, iclass 31, count 0 2006.246.08:19:42.20#ibcon#read 6, iclass 31, count 0 2006.246.08:19:42.20#ibcon#end of sib2, iclass 31, count 0 2006.246.08:19:42.20#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:19:42.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:19:42.20#ibcon#[27=USB\r\n] 2006.246.08:19:42.20#ibcon#*before write, iclass 31, count 0 2006.246.08:19:42.20#ibcon#enter sib2, iclass 31, count 0 2006.246.08:19:42.20#ibcon#flushed, iclass 31, count 0 2006.246.08:19:42.20#ibcon#about to write, iclass 31, count 0 2006.246.08:19:42.20#ibcon#wrote, iclass 31, count 0 2006.246.08:19:42.20#ibcon#about to read 3, iclass 31, count 0 2006.246.08:19:42.22#ibcon#read 3, iclass 31, count 0 2006.246.08:19:42.22#ibcon#about to read 4, iclass 31, count 0 2006.246.08:19:42.22#ibcon#read 4, iclass 31, count 0 2006.246.08:19:42.22#ibcon#about to read 5, iclass 31, count 0 2006.246.08:19:42.22#ibcon#read 5, iclass 31, count 0 2006.246.08:19:42.22#ibcon#about to read 6, iclass 31, count 0 2006.246.08:19:42.22#ibcon#read 6, iclass 31, count 0 2006.246.08:19:42.22#ibcon#end of sib2, iclass 31, count 0 2006.246.08:19:42.22#ibcon#*after write, iclass 31, count 0 2006.246.08:19:42.22#ibcon#*before return 0, iclass 31, count 0 2006.246.08:19:42.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:19:42.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.246.08:19:42.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:19:42.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:19:42.22$vc4f8/vblo=6,752.99 2006.246.08:19:42.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.246.08:19:42.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.246.08:19:42.22#ibcon#ireg 17 cls_cnt 0 2006.246.08:19:42.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:42.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:42.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:42.22#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:19:42.22#ibcon#first serial, iclass 33, count 0 2006.246.08:19:42.22#ibcon#enter sib2, iclass 33, count 0 2006.246.08:19:42.22#ibcon#flushed, iclass 33, count 0 2006.246.08:19:42.22#ibcon#about to write, iclass 33, count 0 2006.246.08:19:42.22#ibcon#wrote, iclass 33, count 0 2006.246.08:19:42.22#ibcon#about to read 3, iclass 33, count 0 2006.246.08:19:42.24#ibcon#read 3, iclass 33, count 0 2006.246.08:19:42.24#ibcon#about to read 4, iclass 33, count 0 2006.246.08:19:42.24#ibcon#read 4, iclass 33, count 0 2006.246.08:19:42.24#ibcon#about to read 5, iclass 33, count 0 2006.246.08:19:42.24#ibcon#read 5, iclass 33, count 0 2006.246.08:19:42.24#ibcon#about to read 6, iclass 33, count 0 2006.246.08:19:42.24#ibcon#read 6, iclass 33, count 0 2006.246.08:19:42.24#ibcon#end of sib2, iclass 33, count 0 2006.246.08:19:42.24#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:19:42.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:19:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:19:42.24#ibcon#*before write, iclass 33, count 0 2006.246.08:19:42.24#ibcon#enter sib2, iclass 33, count 0 2006.246.08:19:42.24#ibcon#flushed, iclass 33, count 0 2006.246.08:19:42.24#ibcon#about to write, iclass 33, count 0 2006.246.08:19:42.24#ibcon#wrote, iclass 33, count 0 2006.246.08:19:42.24#ibcon#about to read 3, iclass 33, count 0 2006.246.08:19:42.28#ibcon#read 3, iclass 33, count 0 2006.246.08:19:42.28#ibcon#about to read 4, iclass 33, count 0 2006.246.08:19:42.28#ibcon#read 4, iclass 33, count 0 2006.246.08:19:42.28#ibcon#about to read 5, iclass 33, count 0 2006.246.08:19:42.28#ibcon#read 5, iclass 33, count 0 2006.246.08:19:42.28#ibcon#about to read 6, iclass 33, count 0 2006.246.08:19:42.28#ibcon#read 6, iclass 33, count 0 2006.246.08:19:42.28#ibcon#end of sib2, iclass 33, count 0 2006.246.08:19:42.28#ibcon#*after write, iclass 33, count 0 2006.246.08:19:42.28#ibcon#*before return 0, iclass 33, count 0 2006.246.08:19:42.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:42.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.246.08:19:42.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:19:42.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:19:42.28$vc4f8/vb=6,3 2006.246.08:19:42.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.246.08:19:42.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.246.08:19:42.28#ibcon#ireg 11 cls_cnt 2 2006.246.08:19:42.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:42.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:42.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:42.34#ibcon#enter wrdev, iclass 35, count 2 2006.246.08:19:42.34#ibcon#first serial, iclass 35, count 2 2006.246.08:19:42.34#ibcon#enter sib2, iclass 35, count 2 2006.246.08:19:42.34#ibcon#flushed, iclass 35, count 2 2006.246.08:19:42.34#ibcon#about to write, iclass 35, count 2 2006.246.08:19:42.34#ibcon#wrote, iclass 35, count 2 2006.246.08:19:42.34#ibcon#about to read 3, iclass 35, count 2 2006.246.08:19:42.36#ibcon#read 3, iclass 35, count 2 2006.246.08:19:42.36#ibcon#about to read 4, iclass 35, count 2 2006.246.08:19:42.36#ibcon#read 4, iclass 35, count 2 2006.246.08:19:42.36#ibcon#about to read 5, iclass 35, count 2 2006.246.08:19:42.36#ibcon#read 5, iclass 35, count 2 2006.246.08:19:42.36#ibcon#about to read 6, iclass 35, count 2 2006.246.08:19:42.36#ibcon#read 6, iclass 35, count 2 2006.246.08:19:42.36#ibcon#end of sib2, iclass 35, count 2 2006.246.08:19:42.36#ibcon#*mode == 0, iclass 35, count 2 2006.246.08:19:42.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.246.08:19:42.36#ibcon#[27=AT06-03\r\n] 2006.246.08:19:42.36#ibcon#*before write, iclass 35, count 2 2006.246.08:19:42.36#ibcon#enter sib2, iclass 35, count 2 2006.246.08:19:42.36#ibcon#flushed, iclass 35, count 2 2006.246.08:19:42.36#ibcon#about to write, iclass 35, count 2 2006.246.08:19:42.36#ibcon#wrote, iclass 35, count 2 2006.246.08:19:42.36#ibcon#about to read 3, iclass 35, count 2 2006.246.08:19:42.39#ibcon#read 3, iclass 35, count 2 2006.246.08:19:42.39#ibcon#about to read 4, iclass 35, count 2 2006.246.08:19:42.39#ibcon#read 4, iclass 35, count 2 2006.246.08:19:42.39#ibcon#about to read 5, iclass 35, count 2 2006.246.08:19:42.39#ibcon#read 5, iclass 35, count 2 2006.246.08:19:42.39#ibcon#about to read 6, iclass 35, count 2 2006.246.08:19:42.39#ibcon#read 6, iclass 35, count 2 2006.246.08:19:42.39#ibcon#end of sib2, iclass 35, count 2 2006.246.08:19:42.39#ibcon#*after write, iclass 35, count 2 2006.246.08:19:42.39#ibcon#*before return 0, iclass 35, count 2 2006.246.08:19:42.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:42.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.246.08:19:42.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.246.08:19:42.39#ibcon#ireg 7 cls_cnt 0 2006.246.08:19:42.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:42.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:42.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:42.51#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:19:42.51#ibcon#first serial, iclass 35, count 0 2006.246.08:19:42.51#ibcon#enter sib2, iclass 35, count 0 2006.246.08:19:42.51#ibcon#flushed, iclass 35, count 0 2006.246.08:19:42.51#ibcon#about to write, iclass 35, count 0 2006.246.08:19:42.51#ibcon#wrote, iclass 35, count 0 2006.246.08:19:42.51#ibcon#about to read 3, iclass 35, count 0 2006.246.08:19:42.53#ibcon#read 3, iclass 35, count 0 2006.246.08:19:42.53#ibcon#about to read 4, iclass 35, count 0 2006.246.08:19:42.53#ibcon#read 4, iclass 35, count 0 2006.246.08:19:42.53#ibcon#about to read 5, iclass 35, count 0 2006.246.08:19:42.53#ibcon#read 5, iclass 35, count 0 2006.246.08:19:42.53#ibcon#about to read 6, iclass 35, count 0 2006.246.08:19:42.53#ibcon#read 6, iclass 35, count 0 2006.246.08:19:42.53#ibcon#end of sib2, iclass 35, count 0 2006.246.08:19:42.53#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:19:42.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:19:42.53#ibcon#[27=USB\r\n] 2006.246.08:19:42.53#ibcon#*before write, iclass 35, count 0 2006.246.08:19:42.53#ibcon#enter sib2, iclass 35, count 0 2006.246.08:19:42.53#ibcon#flushed, iclass 35, count 0 2006.246.08:19:42.53#ibcon#about to write, iclass 35, count 0 2006.246.08:19:42.53#ibcon#wrote, iclass 35, count 0 2006.246.08:19:42.53#ibcon#about to read 3, iclass 35, count 0 2006.246.08:19:42.56#ibcon#read 3, iclass 35, count 0 2006.246.08:19:42.56#ibcon#about to read 4, iclass 35, count 0 2006.246.08:19:42.56#ibcon#read 4, iclass 35, count 0 2006.246.08:19:42.56#ibcon#about to read 5, iclass 35, count 0 2006.246.08:19:42.56#ibcon#read 5, iclass 35, count 0 2006.246.08:19:42.56#ibcon#about to read 6, iclass 35, count 0 2006.246.08:19:42.56#ibcon#read 6, iclass 35, count 0 2006.246.08:19:42.56#ibcon#end of sib2, iclass 35, count 0 2006.246.08:19:42.56#ibcon#*after write, iclass 35, count 0 2006.246.08:19:42.56#ibcon#*before return 0, iclass 35, count 0 2006.246.08:19:42.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:42.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.246.08:19:42.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:19:42.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:19:42.56$vc4f8/vabw=wide 2006.246.08:19:42.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.246.08:19:42.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.246.08:19:42.56#ibcon#ireg 8 cls_cnt 0 2006.246.08:19:42.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:42.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:42.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:42.56#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:19:42.56#ibcon#first serial, iclass 37, count 0 2006.246.08:19:42.56#ibcon#enter sib2, iclass 37, count 0 2006.246.08:19:42.56#ibcon#flushed, iclass 37, count 0 2006.246.08:19:42.56#ibcon#about to write, iclass 37, count 0 2006.246.08:19:42.56#ibcon#wrote, iclass 37, count 0 2006.246.08:19:42.56#ibcon#about to read 3, iclass 37, count 0 2006.246.08:19:42.58#ibcon#read 3, iclass 37, count 0 2006.246.08:19:42.58#ibcon#about to read 4, iclass 37, count 0 2006.246.08:19:42.58#ibcon#read 4, iclass 37, count 0 2006.246.08:19:42.58#ibcon#about to read 5, iclass 37, count 0 2006.246.08:19:42.58#ibcon#read 5, iclass 37, count 0 2006.246.08:19:42.58#ibcon#about to read 6, iclass 37, count 0 2006.246.08:19:42.58#ibcon#read 6, iclass 37, count 0 2006.246.08:19:42.58#ibcon#end of sib2, iclass 37, count 0 2006.246.08:19:42.58#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:19:42.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:19:42.58#ibcon#[25=BW32\r\n] 2006.246.08:19:42.58#ibcon#*before write, iclass 37, count 0 2006.246.08:19:42.58#ibcon#enter sib2, iclass 37, count 0 2006.246.08:19:42.58#ibcon#flushed, iclass 37, count 0 2006.246.08:19:42.58#ibcon#about to write, iclass 37, count 0 2006.246.08:19:42.58#ibcon#wrote, iclass 37, count 0 2006.246.08:19:42.58#ibcon#about to read 3, iclass 37, count 0 2006.246.08:19:42.61#ibcon#read 3, iclass 37, count 0 2006.246.08:19:42.61#ibcon#about to read 4, iclass 37, count 0 2006.246.08:19:42.61#ibcon#read 4, iclass 37, count 0 2006.246.08:19:42.61#ibcon#about to read 5, iclass 37, count 0 2006.246.08:19:42.61#ibcon#read 5, iclass 37, count 0 2006.246.08:19:42.61#ibcon#about to read 6, iclass 37, count 0 2006.246.08:19:42.61#ibcon#read 6, iclass 37, count 0 2006.246.08:19:42.61#ibcon#end of sib2, iclass 37, count 0 2006.246.08:19:42.61#ibcon#*after write, iclass 37, count 0 2006.246.08:19:42.61#ibcon#*before return 0, iclass 37, count 0 2006.246.08:19:42.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:42.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.246.08:19:42.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:19:42.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:19:42.61$vc4f8/vbbw=wide 2006.246.08:19:42.61#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:19:42.61#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:19:42.61#ibcon#ireg 8 cls_cnt 0 2006.246.08:19:42.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:19:42.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:19:42.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:19:42.68#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:19:42.68#ibcon#first serial, iclass 39, count 0 2006.246.08:19:42.68#ibcon#enter sib2, iclass 39, count 0 2006.246.08:19:42.68#ibcon#flushed, iclass 39, count 0 2006.246.08:19:42.68#ibcon#about to write, iclass 39, count 0 2006.246.08:19:42.68#ibcon#wrote, iclass 39, count 0 2006.246.08:19:42.68#ibcon#about to read 3, iclass 39, count 0 2006.246.08:19:42.70#ibcon#read 3, iclass 39, count 0 2006.246.08:19:42.70#ibcon#about to read 4, iclass 39, count 0 2006.246.08:19:42.70#ibcon#read 4, iclass 39, count 0 2006.246.08:19:42.70#ibcon#about to read 5, iclass 39, count 0 2006.246.08:19:42.70#ibcon#read 5, iclass 39, count 0 2006.246.08:19:42.70#ibcon#about to read 6, iclass 39, count 0 2006.246.08:19:42.70#ibcon#read 6, iclass 39, count 0 2006.246.08:19:42.70#ibcon#end of sib2, iclass 39, count 0 2006.246.08:19:42.70#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:19:42.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:19:42.70#ibcon#[27=BW32\r\n] 2006.246.08:19:42.70#ibcon#*before write, iclass 39, count 0 2006.246.08:19:42.70#ibcon#enter sib2, iclass 39, count 0 2006.246.08:19:42.70#ibcon#flushed, iclass 39, count 0 2006.246.08:19:42.70#ibcon#about to write, iclass 39, count 0 2006.246.08:19:42.70#ibcon#wrote, iclass 39, count 0 2006.246.08:19:42.70#ibcon#about to read 3, iclass 39, count 0 2006.246.08:19:42.73#ibcon#read 3, iclass 39, count 0 2006.246.08:19:42.73#ibcon#about to read 4, iclass 39, count 0 2006.246.08:19:42.73#ibcon#read 4, iclass 39, count 0 2006.246.08:19:42.73#ibcon#about to read 5, iclass 39, count 0 2006.246.08:19:42.73#ibcon#read 5, iclass 39, count 0 2006.246.08:19:42.73#ibcon#about to read 6, iclass 39, count 0 2006.246.08:19:42.73#ibcon#read 6, iclass 39, count 0 2006.246.08:19:42.73#ibcon#end of sib2, iclass 39, count 0 2006.246.08:19:42.73#ibcon#*after write, iclass 39, count 0 2006.246.08:19:42.73#ibcon#*before return 0, iclass 39, count 0 2006.246.08:19:42.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:19:42.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:19:42.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:19:42.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:19:42.73$4f8m12a/ifd4f 2006.246.08:19:42.73$ifd4f/lo= 2006.246.08:19:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:19:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:19:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:19:42.73$ifd4f/patch= 2006.246.08:19:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:19:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:19:42.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:19:42.74$4f8m12a/"form=m,16.000,1:2 2006.246.08:19:42.74$4f8m12a/"tpicd 2006.246.08:19:42.74$4f8m12a/echo=off 2006.246.08:19:42.74$4f8m12a/xlog=off 2006.246.08:19:42.74:!2006.246.08:21:10 2006.246.08:20:05.13#trakl#Source acquired 2006.246.08:20:07.13#flagr#flagr/antenna,acquired 2006.246.08:21:10.01:preob 2006.246.08:21:11.14/onsource/TRACKING 2006.246.08:21:11.14:!2006.246.08:21:20 2006.246.08:21:20.00:data_valid=on 2006.246.08:21:20.00:midob 2006.246.08:21:20.14/onsource/TRACKING 2006.246.08:21:20.14/wx/26.24,1005.7,77 2006.246.08:21:20.25/cable/+6.4133E-03 2006.246.08:21:21.34/va/01,08,usb,yes,34,35 2006.246.08:21:21.34/va/02,07,usb,yes,34,35 2006.246.08:21:21.34/va/03,06,usb,yes,36,36 2006.246.08:21:21.34/va/04,07,usb,yes,35,37 2006.246.08:21:21.34/va/05,07,usb,yes,38,40 2006.246.08:21:21.34/va/06,07,usb,yes,33,33 2006.246.08:21:21.34/va/07,07,usb,yes,33,33 2006.246.08:21:21.34/va/08,08,usb,yes,28,28 2006.246.08:21:21.57/valo/01,532.99,yes,locked 2006.246.08:21:21.57/valo/02,572.99,yes,locked 2006.246.08:21:21.57/valo/03,672.99,yes,locked 2006.246.08:21:21.57/valo/04,832.99,yes,locked 2006.246.08:21:21.57/valo/05,652.99,yes,locked 2006.246.08:21:21.57/valo/06,772.99,yes,locked 2006.246.08:21:21.57/valo/07,832.99,yes,locked 2006.246.08:21:21.57/valo/08,852.99,yes,locked 2006.246.08:21:22.66/vb/01,04,usb,yes,33,31 2006.246.08:21:22.66/vb/02,04,usb,yes,35,36 2006.246.08:21:22.66/vb/03,04,usb,yes,31,35 2006.246.08:21:22.66/vb/04,04,usb,yes,32,32 2006.246.08:21:22.66/vb/05,03,usb,yes,38,43 2006.246.08:21:22.66/vb/06,03,usb,yes,38,42 2006.246.08:21:22.66/vb/07,04,usb,yes,33,34 2006.246.08:21:22.66/vb/08,03,usb,yes,38,43 2006.246.08:21:22.89/vblo/01,632.99,yes,locked 2006.246.08:21:22.89/vblo/02,640.99,yes,locked 2006.246.08:21:22.89/vblo/03,656.99,yes,locked 2006.246.08:21:22.89/vblo/04,712.99,yes,locked 2006.246.08:21:22.89/vblo/05,744.99,yes,locked 2006.246.08:21:22.89/vblo/06,752.99,yes,locked 2006.246.08:21:22.89/vblo/07,734.99,yes,locked 2006.246.08:21:22.89/vblo/08,744.99,yes,locked 2006.246.08:21:23.04/vabw/8 2006.246.08:21:23.19/vbbw/8 2006.246.08:21:23.28/xfe/off,on,13.0 2006.246.08:21:23.68/ifatt/23,28,28,28 2006.246.08:21:24.07/fmout-gps/S +4.45E-07 2006.246.08:21:24.11:!2006.246.08:22:20 2006.246.08:22:20.00:data_valid=off 2006.246.08:22:20.01:postob 2006.246.08:22:20.08/cable/+6.4136E-03 2006.246.08:22:20.08/wx/26.22,1005.7,77 2006.246.08:22:21.07/fmout-gps/S +4.44E-07 2006.246.08:22:21.08:scan_name=246-0824,k06246,60 2006.246.08:22:21.08:source=nrao512,164029.63,394646.0,2000.0,cw 2006.246.08:22:21.14#flagr#flagr/antenna,new-source 2006.246.08:22:22.14:checkk5 2006.246.08:22:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:22:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:22:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:22:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:22:24.00/chk_obsdata//k5ts1/T2460821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:22:24.37/chk_obsdata//k5ts2/T2460821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:22:24.74/chk_obsdata//k5ts3/T2460821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:22:25.11/chk_obsdata//k5ts4/T2460821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:22:25.81/k5log//k5ts1_log_newline 2006.246.08:22:26.49/k5log//k5ts2_log_newline 2006.246.08:22:27.18/k5log//k5ts3_log_newline 2006.246.08:22:27.87/k5log//k5ts4_log_newline 2006.246.08:22:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:22:27.89:4f8m12a=3 2006.246.08:22:27.89$4f8m12a/echo=on 2006.246.08:22:27.89$4f8m12a/pcalon 2006.246.08:22:27.89$pcalon/"no phase cal control is implemented here 2006.246.08:22:27.89$4f8m12a/"tpicd=stop 2006.246.08:22:27.89$4f8m12a/vc4f8 2006.246.08:22:27.89$vc4f8/valo=1,532.99 2006.246.08:22:27.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.08:22:27.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.08:22:27.90#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:27.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:27.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:27.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:27.90#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:22:27.90#ibcon#first serial, iclass 34, count 0 2006.246.08:22:27.90#ibcon#enter sib2, iclass 34, count 0 2006.246.08:22:27.90#ibcon#flushed, iclass 34, count 0 2006.246.08:22:27.90#ibcon#about to write, iclass 34, count 0 2006.246.08:22:27.90#ibcon#wrote, iclass 34, count 0 2006.246.08:22:27.90#ibcon#about to read 3, iclass 34, count 0 2006.246.08:22:27.93#ibcon#read 3, iclass 34, count 0 2006.246.08:22:27.93#ibcon#about to read 4, iclass 34, count 0 2006.246.08:22:27.93#ibcon#read 4, iclass 34, count 0 2006.246.08:22:27.93#ibcon#about to read 5, iclass 34, count 0 2006.246.08:22:27.93#ibcon#read 5, iclass 34, count 0 2006.246.08:22:27.93#ibcon#about to read 6, iclass 34, count 0 2006.246.08:22:27.93#ibcon#read 6, iclass 34, count 0 2006.246.08:22:27.93#ibcon#end of sib2, iclass 34, count 0 2006.246.08:22:27.93#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:22:27.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:22:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:22:27.93#ibcon#*before write, iclass 34, count 0 2006.246.08:22:27.93#ibcon#enter sib2, iclass 34, count 0 2006.246.08:22:27.93#ibcon#flushed, iclass 34, count 0 2006.246.08:22:27.93#ibcon#about to write, iclass 34, count 0 2006.246.08:22:27.93#ibcon#wrote, iclass 34, count 0 2006.246.08:22:27.93#ibcon#about to read 3, iclass 34, count 0 2006.246.08:22:27.98#ibcon#read 3, iclass 34, count 0 2006.246.08:22:27.98#ibcon#about to read 4, iclass 34, count 0 2006.246.08:22:27.98#ibcon#read 4, iclass 34, count 0 2006.246.08:22:27.98#ibcon#about to read 5, iclass 34, count 0 2006.246.08:22:27.98#ibcon#read 5, iclass 34, count 0 2006.246.08:22:27.98#ibcon#about to read 6, iclass 34, count 0 2006.246.08:22:27.98#ibcon#read 6, iclass 34, count 0 2006.246.08:22:27.98#ibcon#end of sib2, iclass 34, count 0 2006.246.08:22:27.98#ibcon#*after write, iclass 34, count 0 2006.246.08:22:27.98#ibcon#*before return 0, iclass 34, count 0 2006.246.08:22:27.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:27.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:27.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:22:27.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:22:27.98$vc4f8/va=1,8 2006.246.08:22:27.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.08:22:27.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.08:22:27.98#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:27.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:27.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:27.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:27.98#ibcon#enter wrdev, iclass 36, count 2 2006.246.08:22:27.98#ibcon#first serial, iclass 36, count 2 2006.246.08:22:27.98#ibcon#enter sib2, iclass 36, count 2 2006.246.08:22:27.98#ibcon#flushed, iclass 36, count 2 2006.246.08:22:27.98#ibcon#about to write, iclass 36, count 2 2006.246.08:22:27.98#ibcon#wrote, iclass 36, count 2 2006.246.08:22:27.98#ibcon#about to read 3, iclass 36, count 2 2006.246.08:22:28.01#ibcon#read 3, iclass 36, count 2 2006.246.08:22:28.01#ibcon#about to read 4, iclass 36, count 2 2006.246.08:22:28.01#ibcon#read 4, iclass 36, count 2 2006.246.08:22:28.01#ibcon#about to read 5, iclass 36, count 2 2006.246.08:22:28.01#ibcon#read 5, iclass 36, count 2 2006.246.08:22:28.01#ibcon#about to read 6, iclass 36, count 2 2006.246.08:22:28.01#ibcon#read 6, iclass 36, count 2 2006.246.08:22:28.01#ibcon#end of sib2, iclass 36, count 2 2006.246.08:22:28.01#ibcon#*mode == 0, iclass 36, count 2 2006.246.08:22:28.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.08:22:28.01#ibcon#[25=AT01-08\r\n] 2006.246.08:22:28.01#ibcon#*before write, iclass 36, count 2 2006.246.08:22:28.01#ibcon#enter sib2, iclass 36, count 2 2006.246.08:22:28.01#ibcon#flushed, iclass 36, count 2 2006.246.08:22:28.01#ibcon#about to write, iclass 36, count 2 2006.246.08:22:28.01#ibcon#wrote, iclass 36, count 2 2006.246.08:22:28.01#ibcon#about to read 3, iclass 36, count 2 2006.246.08:22:28.04#ibcon#read 3, iclass 36, count 2 2006.246.08:22:28.04#ibcon#about to read 4, iclass 36, count 2 2006.246.08:22:28.04#ibcon#read 4, iclass 36, count 2 2006.246.08:22:28.04#ibcon#about to read 5, iclass 36, count 2 2006.246.08:22:28.04#ibcon#read 5, iclass 36, count 2 2006.246.08:22:28.04#ibcon#about to read 6, iclass 36, count 2 2006.246.08:22:28.04#ibcon#read 6, iclass 36, count 2 2006.246.08:22:28.04#ibcon#end of sib2, iclass 36, count 2 2006.246.08:22:28.04#ibcon#*after write, iclass 36, count 2 2006.246.08:22:28.04#ibcon#*before return 0, iclass 36, count 2 2006.246.08:22:28.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:28.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:28.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.08:22:28.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:28.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:28.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:28.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:28.16#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:22:28.16#ibcon#first serial, iclass 36, count 0 2006.246.08:22:28.16#ibcon#enter sib2, iclass 36, count 0 2006.246.08:22:28.16#ibcon#flushed, iclass 36, count 0 2006.246.08:22:28.16#ibcon#about to write, iclass 36, count 0 2006.246.08:22:28.16#ibcon#wrote, iclass 36, count 0 2006.246.08:22:28.16#ibcon#about to read 3, iclass 36, count 0 2006.246.08:22:28.18#ibcon#read 3, iclass 36, count 0 2006.246.08:22:28.18#ibcon#about to read 4, iclass 36, count 0 2006.246.08:22:28.18#ibcon#read 4, iclass 36, count 0 2006.246.08:22:28.18#ibcon#about to read 5, iclass 36, count 0 2006.246.08:22:28.18#ibcon#read 5, iclass 36, count 0 2006.246.08:22:28.18#ibcon#about to read 6, iclass 36, count 0 2006.246.08:22:28.18#ibcon#read 6, iclass 36, count 0 2006.246.08:22:28.18#ibcon#end of sib2, iclass 36, count 0 2006.246.08:22:28.18#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:22:28.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:22:28.18#ibcon#[25=USB\r\n] 2006.246.08:22:28.18#ibcon#*before write, iclass 36, count 0 2006.246.08:22:28.18#ibcon#enter sib2, iclass 36, count 0 2006.246.08:22:28.18#ibcon#flushed, iclass 36, count 0 2006.246.08:22:28.18#ibcon#about to write, iclass 36, count 0 2006.246.08:22:28.18#ibcon#wrote, iclass 36, count 0 2006.246.08:22:28.18#ibcon#about to read 3, iclass 36, count 0 2006.246.08:22:28.21#ibcon#read 3, iclass 36, count 0 2006.246.08:22:28.21#ibcon#about to read 4, iclass 36, count 0 2006.246.08:22:28.21#ibcon#read 4, iclass 36, count 0 2006.246.08:22:28.21#ibcon#about to read 5, iclass 36, count 0 2006.246.08:22:28.21#ibcon#read 5, iclass 36, count 0 2006.246.08:22:28.21#ibcon#about to read 6, iclass 36, count 0 2006.246.08:22:28.21#ibcon#read 6, iclass 36, count 0 2006.246.08:22:28.21#ibcon#end of sib2, iclass 36, count 0 2006.246.08:22:28.21#ibcon#*after write, iclass 36, count 0 2006.246.08:22:28.21#ibcon#*before return 0, iclass 36, count 0 2006.246.08:22:28.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:28.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:28.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:22:28.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:22:28.21$vc4f8/valo=2,572.99 2006.246.08:22:28.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.08:22:28.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.08:22:28.21#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:28.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:28.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:28.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:28.21#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:22:28.21#ibcon#first serial, iclass 38, count 0 2006.246.08:22:28.21#ibcon#enter sib2, iclass 38, count 0 2006.246.08:22:28.21#ibcon#flushed, iclass 38, count 0 2006.246.08:22:28.21#ibcon#about to write, iclass 38, count 0 2006.246.08:22:28.21#ibcon#wrote, iclass 38, count 0 2006.246.08:22:28.21#ibcon#about to read 3, iclass 38, count 0 2006.246.08:22:28.23#ibcon#read 3, iclass 38, count 0 2006.246.08:22:28.23#ibcon#about to read 4, iclass 38, count 0 2006.246.08:22:28.23#ibcon#read 4, iclass 38, count 0 2006.246.08:22:28.23#ibcon#about to read 5, iclass 38, count 0 2006.246.08:22:28.23#ibcon#read 5, iclass 38, count 0 2006.246.08:22:28.23#ibcon#about to read 6, iclass 38, count 0 2006.246.08:22:28.23#ibcon#read 6, iclass 38, count 0 2006.246.08:22:28.23#ibcon#end of sib2, iclass 38, count 0 2006.246.08:22:28.23#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:22:28.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:22:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:22:28.23#ibcon#*before write, iclass 38, count 0 2006.246.08:22:28.23#ibcon#enter sib2, iclass 38, count 0 2006.246.08:22:28.23#ibcon#flushed, iclass 38, count 0 2006.246.08:22:28.23#ibcon#about to write, iclass 38, count 0 2006.246.08:22:28.23#ibcon#wrote, iclass 38, count 0 2006.246.08:22:28.23#ibcon#about to read 3, iclass 38, count 0 2006.246.08:22:28.27#ibcon#read 3, iclass 38, count 0 2006.246.08:22:28.27#ibcon#about to read 4, iclass 38, count 0 2006.246.08:22:28.27#ibcon#read 4, iclass 38, count 0 2006.246.08:22:28.27#ibcon#about to read 5, iclass 38, count 0 2006.246.08:22:28.27#ibcon#read 5, iclass 38, count 0 2006.246.08:22:28.27#ibcon#about to read 6, iclass 38, count 0 2006.246.08:22:28.27#ibcon#read 6, iclass 38, count 0 2006.246.08:22:28.27#ibcon#end of sib2, iclass 38, count 0 2006.246.08:22:28.27#ibcon#*after write, iclass 38, count 0 2006.246.08:22:28.27#ibcon#*before return 0, iclass 38, count 0 2006.246.08:22:28.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:28.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:28.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:22:28.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:22:28.27$vc4f8/va=2,7 2006.246.08:22:28.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.08:22:28.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.08:22:28.27#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:28.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:28.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:28.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:28.33#ibcon#enter wrdev, iclass 40, count 2 2006.246.08:22:28.33#ibcon#first serial, iclass 40, count 2 2006.246.08:22:28.33#ibcon#enter sib2, iclass 40, count 2 2006.246.08:22:28.33#ibcon#flushed, iclass 40, count 2 2006.246.08:22:28.33#ibcon#about to write, iclass 40, count 2 2006.246.08:22:28.33#ibcon#wrote, iclass 40, count 2 2006.246.08:22:28.33#ibcon#about to read 3, iclass 40, count 2 2006.246.08:22:28.35#ibcon#read 3, iclass 40, count 2 2006.246.08:22:28.35#ibcon#about to read 4, iclass 40, count 2 2006.246.08:22:28.35#ibcon#read 4, iclass 40, count 2 2006.246.08:22:28.35#ibcon#about to read 5, iclass 40, count 2 2006.246.08:22:28.35#ibcon#read 5, iclass 40, count 2 2006.246.08:22:28.35#ibcon#about to read 6, iclass 40, count 2 2006.246.08:22:28.35#ibcon#read 6, iclass 40, count 2 2006.246.08:22:28.35#ibcon#end of sib2, iclass 40, count 2 2006.246.08:22:28.35#ibcon#*mode == 0, iclass 40, count 2 2006.246.08:22:28.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.08:22:28.35#ibcon#[25=AT02-07\r\n] 2006.246.08:22:28.35#ibcon#*before write, iclass 40, count 2 2006.246.08:22:28.35#ibcon#enter sib2, iclass 40, count 2 2006.246.08:22:28.35#ibcon#flushed, iclass 40, count 2 2006.246.08:22:28.35#ibcon#about to write, iclass 40, count 2 2006.246.08:22:28.35#ibcon#wrote, iclass 40, count 2 2006.246.08:22:28.35#ibcon#about to read 3, iclass 40, count 2 2006.246.08:22:28.38#ibcon#read 3, iclass 40, count 2 2006.246.08:22:28.38#ibcon#about to read 4, iclass 40, count 2 2006.246.08:22:28.38#ibcon#read 4, iclass 40, count 2 2006.246.08:22:28.38#ibcon#about to read 5, iclass 40, count 2 2006.246.08:22:28.38#ibcon#read 5, iclass 40, count 2 2006.246.08:22:28.38#ibcon#about to read 6, iclass 40, count 2 2006.246.08:22:28.38#ibcon#read 6, iclass 40, count 2 2006.246.08:22:28.38#ibcon#end of sib2, iclass 40, count 2 2006.246.08:22:28.38#ibcon#*after write, iclass 40, count 2 2006.246.08:22:28.38#ibcon#*before return 0, iclass 40, count 2 2006.246.08:22:28.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:28.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:28.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.08:22:28.38#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:28.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:28.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:28.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:28.51#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:22:28.51#ibcon#first serial, iclass 40, count 0 2006.246.08:22:28.51#ibcon#enter sib2, iclass 40, count 0 2006.246.08:22:28.51#ibcon#flushed, iclass 40, count 0 2006.246.08:22:28.51#ibcon#about to write, iclass 40, count 0 2006.246.08:22:28.51#ibcon#wrote, iclass 40, count 0 2006.246.08:22:28.51#ibcon#about to read 3, iclass 40, count 0 2006.246.08:22:28.52#ibcon#read 3, iclass 40, count 0 2006.246.08:22:28.52#ibcon#about to read 4, iclass 40, count 0 2006.246.08:22:28.52#ibcon#read 4, iclass 40, count 0 2006.246.08:22:28.52#ibcon#about to read 5, iclass 40, count 0 2006.246.08:22:28.52#ibcon#read 5, iclass 40, count 0 2006.246.08:22:28.52#ibcon#about to read 6, iclass 40, count 0 2006.246.08:22:28.52#ibcon#read 6, iclass 40, count 0 2006.246.08:22:28.52#ibcon#end of sib2, iclass 40, count 0 2006.246.08:22:28.52#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:22:28.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:22:28.52#ibcon#[25=USB\r\n] 2006.246.08:22:28.52#ibcon#*before write, iclass 40, count 0 2006.246.08:22:28.52#ibcon#enter sib2, iclass 40, count 0 2006.246.08:22:28.52#ibcon#flushed, iclass 40, count 0 2006.246.08:22:28.52#ibcon#about to write, iclass 40, count 0 2006.246.08:22:28.52#ibcon#wrote, iclass 40, count 0 2006.246.08:22:28.52#ibcon#about to read 3, iclass 40, count 0 2006.246.08:22:28.55#ibcon#read 3, iclass 40, count 0 2006.246.08:22:28.55#ibcon#about to read 4, iclass 40, count 0 2006.246.08:22:28.55#ibcon#read 4, iclass 40, count 0 2006.246.08:22:28.55#ibcon#about to read 5, iclass 40, count 0 2006.246.08:22:28.55#ibcon#read 5, iclass 40, count 0 2006.246.08:22:28.55#ibcon#about to read 6, iclass 40, count 0 2006.246.08:22:28.55#ibcon#read 6, iclass 40, count 0 2006.246.08:22:28.55#ibcon#end of sib2, iclass 40, count 0 2006.246.08:22:28.55#ibcon#*after write, iclass 40, count 0 2006.246.08:22:28.55#ibcon#*before return 0, iclass 40, count 0 2006.246.08:22:28.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:28.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:28.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:22:28.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:22:28.55$vc4f8/valo=3,672.99 2006.246.08:22:28.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.08:22:28.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.08:22:28.55#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:28.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:28.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:28.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:28.55#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:22:28.55#ibcon#first serial, iclass 4, count 0 2006.246.08:22:28.55#ibcon#enter sib2, iclass 4, count 0 2006.246.08:22:28.55#ibcon#flushed, iclass 4, count 0 2006.246.08:22:28.55#ibcon#about to write, iclass 4, count 0 2006.246.08:22:28.55#ibcon#wrote, iclass 4, count 0 2006.246.08:22:28.55#ibcon#about to read 3, iclass 4, count 0 2006.246.08:22:28.58#ibcon#read 3, iclass 4, count 0 2006.246.08:22:28.58#ibcon#about to read 4, iclass 4, count 0 2006.246.08:22:28.58#ibcon#read 4, iclass 4, count 0 2006.246.08:22:28.58#ibcon#about to read 5, iclass 4, count 0 2006.246.08:22:28.58#ibcon#read 5, iclass 4, count 0 2006.246.08:22:28.58#ibcon#about to read 6, iclass 4, count 0 2006.246.08:22:28.58#ibcon#read 6, iclass 4, count 0 2006.246.08:22:28.58#ibcon#end of sib2, iclass 4, count 0 2006.246.08:22:28.58#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:22:28.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:22:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:22:28.58#ibcon#*before write, iclass 4, count 0 2006.246.08:22:28.58#ibcon#enter sib2, iclass 4, count 0 2006.246.08:22:28.58#ibcon#flushed, iclass 4, count 0 2006.246.08:22:28.58#ibcon#about to write, iclass 4, count 0 2006.246.08:22:28.58#ibcon#wrote, iclass 4, count 0 2006.246.08:22:28.58#ibcon#about to read 3, iclass 4, count 0 2006.246.08:22:28.62#ibcon#read 3, iclass 4, count 0 2006.246.08:22:28.62#ibcon#about to read 4, iclass 4, count 0 2006.246.08:22:28.62#ibcon#read 4, iclass 4, count 0 2006.246.08:22:28.62#ibcon#about to read 5, iclass 4, count 0 2006.246.08:22:28.62#ibcon#read 5, iclass 4, count 0 2006.246.08:22:28.62#ibcon#about to read 6, iclass 4, count 0 2006.246.08:22:28.62#ibcon#read 6, iclass 4, count 0 2006.246.08:22:28.62#ibcon#end of sib2, iclass 4, count 0 2006.246.08:22:28.62#ibcon#*after write, iclass 4, count 0 2006.246.08:22:28.62#ibcon#*before return 0, iclass 4, count 0 2006.246.08:22:28.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:28.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:28.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:22:28.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:22:28.62$vc4f8/va=3,6 2006.246.08:22:28.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.08:22:28.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.08:22:28.62#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:28.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:28.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:28.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:28.67#ibcon#enter wrdev, iclass 6, count 2 2006.246.08:22:28.67#ibcon#first serial, iclass 6, count 2 2006.246.08:22:28.67#ibcon#enter sib2, iclass 6, count 2 2006.246.08:22:28.67#ibcon#flushed, iclass 6, count 2 2006.246.08:22:28.67#ibcon#about to write, iclass 6, count 2 2006.246.08:22:28.67#ibcon#wrote, iclass 6, count 2 2006.246.08:22:28.67#ibcon#about to read 3, iclass 6, count 2 2006.246.08:22:28.69#ibcon#read 3, iclass 6, count 2 2006.246.08:22:28.69#ibcon#about to read 4, iclass 6, count 2 2006.246.08:22:28.69#ibcon#read 4, iclass 6, count 2 2006.246.08:22:28.69#ibcon#about to read 5, iclass 6, count 2 2006.246.08:22:28.69#ibcon#read 5, iclass 6, count 2 2006.246.08:22:28.69#ibcon#about to read 6, iclass 6, count 2 2006.246.08:22:28.69#ibcon#read 6, iclass 6, count 2 2006.246.08:22:28.69#ibcon#end of sib2, iclass 6, count 2 2006.246.08:22:28.69#ibcon#*mode == 0, iclass 6, count 2 2006.246.08:22:28.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.08:22:28.69#ibcon#[25=AT03-06\r\n] 2006.246.08:22:28.69#ibcon#*before write, iclass 6, count 2 2006.246.08:22:28.69#ibcon#enter sib2, iclass 6, count 2 2006.246.08:22:28.69#ibcon#flushed, iclass 6, count 2 2006.246.08:22:28.69#ibcon#about to write, iclass 6, count 2 2006.246.08:22:28.69#ibcon#wrote, iclass 6, count 2 2006.246.08:22:28.69#ibcon#about to read 3, iclass 6, count 2 2006.246.08:22:28.72#ibcon#read 3, iclass 6, count 2 2006.246.08:22:28.72#ibcon#about to read 4, iclass 6, count 2 2006.246.08:22:28.72#ibcon#read 4, iclass 6, count 2 2006.246.08:22:28.72#ibcon#about to read 5, iclass 6, count 2 2006.246.08:22:28.72#ibcon#read 5, iclass 6, count 2 2006.246.08:22:28.72#ibcon#about to read 6, iclass 6, count 2 2006.246.08:22:28.72#ibcon#read 6, iclass 6, count 2 2006.246.08:22:28.72#ibcon#end of sib2, iclass 6, count 2 2006.246.08:22:28.72#ibcon#*after write, iclass 6, count 2 2006.246.08:22:28.72#ibcon#*before return 0, iclass 6, count 2 2006.246.08:22:28.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:28.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:28.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.08:22:28.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:28.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:28.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:28.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:28.84#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:22:28.84#ibcon#first serial, iclass 6, count 0 2006.246.08:22:28.84#ibcon#enter sib2, iclass 6, count 0 2006.246.08:22:28.84#ibcon#flushed, iclass 6, count 0 2006.246.08:22:28.84#ibcon#about to write, iclass 6, count 0 2006.246.08:22:28.84#ibcon#wrote, iclass 6, count 0 2006.246.08:22:28.84#ibcon#about to read 3, iclass 6, count 0 2006.246.08:22:28.86#ibcon#read 3, iclass 6, count 0 2006.246.08:22:28.86#ibcon#about to read 4, iclass 6, count 0 2006.246.08:22:28.86#ibcon#read 4, iclass 6, count 0 2006.246.08:22:28.86#ibcon#about to read 5, iclass 6, count 0 2006.246.08:22:28.86#ibcon#read 5, iclass 6, count 0 2006.246.08:22:28.86#ibcon#about to read 6, iclass 6, count 0 2006.246.08:22:28.86#ibcon#read 6, iclass 6, count 0 2006.246.08:22:28.86#ibcon#end of sib2, iclass 6, count 0 2006.246.08:22:28.86#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:22:28.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:22:28.86#ibcon#[25=USB\r\n] 2006.246.08:22:28.86#ibcon#*before write, iclass 6, count 0 2006.246.08:22:28.86#ibcon#enter sib2, iclass 6, count 0 2006.246.08:22:28.86#ibcon#flushed, iclass 6, count 0 2006.246.08:22:28.86#ibcon#about to write, iclass 6, count 0 2006.246.08:22:28.86#ibcon#wrote, iclass 6, count 0 2006.246.08:22:28.86#ibcon#about to read 3, iclass 6, count 0 2006.246.08:22:28.89#ibcon#read 3, iclass 6, count 0 2006.246.08:22:28.89#ibcon#about to read 4, iclass 6, count 0 2006.246.08:22:28.89#ibcon#read 4, iclass 6, count 0 2006.246.08:22:28.89#ibcon#about to read 5, iclass 6, count 0 2006.246.08:22:28.89#ibcon#read 5, iclass 6, count 0 2006.246.08:22:28.89#ibcon#about to read 6, iclass 6, count 0 2006.246.08:22:28.89#ibcon#read 6, iclass 6, count 0 2006.246.08:22:28.89#ibcon#end of sib2, iclass 6, count 0 2006.246.08:22:28.89#ibcon#*after write, iclass 6, count 0 2006.246.08:22:28.89#ibcon#*before return 0, iclass 6, count 0 2006.246.08:22:28.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:28.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:28.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:22:28.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:22:28.89$vc4f8/valo=4,832.99 2006.246.08:22:28.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.08:22:28.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.08:22:28.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:28.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:28.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:28.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:28.89#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:22:28.89#ibcon#first serial, iclass 10, count 0 2006.246.08:22:28.89#ibcon#enter sib2, iclass 10, count 0 2006.246.08:22:28.89#ibcon#flushed, iclass 10, count 0 2006.246.08:22:28.89#ibcon#about to write, iclass 10, count 0 2006.246.08:22:28.89#ibcon#wrote, iclass 10, count 0 2006.246.08:22:28.89#ibcon#about to read 3, iclass 10, count 0 2006.246.08:22:28.91#ibcon#read 3, iclass 10, count 0 2006.246.08:22:28.91#ibcon#about to read 4, iclass 10, count 0 2006.246.08:22:28.91#ibcon#read 4, iclass 10, count 0 2006.246.08:22:28.91#ibcon#about to read 5, iclass 10, count 0 2006.246.08:22:28.91#ibcon#read 5, iclass 10, count 0 2006.246.08:22:28.91#ibcon#about to read 6, iclass 10, count 0 2006.246.08:22:28.91#ibcon#read 6, iclass 10, count 0 2006.246.08:22:28.91#ibcon#end of sib2, iclass 10, count 0 2006.246.08:22:28.91#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:22:28.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:22:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:22:28.91#ibcon#*before write, iclass 10, count 0 2006.246.08:22:28.91#ibcon#enter sib2, iclass 10, count 0 2006.246.08:22:28.91#ibcon#flushed, iclass 10, count 0 2006.246.08:22:28.91#ibcon#about to write, iclass 10, count 0 2006.246.08:22:28.91#ibcon#wrote, iclass 10, count 0 2006.246.08:22:28.91#ibcon#about to read 3, iclass 10, count 0 2006.246.08:22:28.95#ibcon#read 3, iclass 10, count 0 2006.246.08:22:28.95#ibcon#about to read 4, iclass 10, count 0 2006.246.08:22:28.95#ibcon#read 4, iclass 10, count 0 2006.246.08:22:28.95#ibcon#about to read 5, iclass 10, count 0 2006.246.08:22:28.95#ibcon#read 5, iclass 10, count 0 2006.246.08:22:28.95#ibcon#about to read 6, iclass 10, count 0 2006.246.08:22:28.95#ibcon#read 6, iclass 10, count 0 2006.246.08:22:28.95#ibcon#end of sib2, iclass 10, count 0 2006.246.08:22:28.95#ibcon#*after write, iclass 10, count 0 2006.246.08:22:28.95#ibcon#*before return 0, iclass 10, count 0 2006.246.08:22:28.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:28.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:28.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:22:28.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:22:28.95$vc4f8/va=4,7 2006.246.08:22:28.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.08:22:28.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.08:22:28.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:28.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:29.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:29.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:29.01#ibcon#enter wrdev, iclass 12, count 2 2006.246.08:22:29.01#ibcon#first serial, iclass 12, count 2 2006.246.08:22:29.01#ibcon#enter sib2, iclass 12, count 2 2006.246.08:22:29.01#ibcon#flushed, iclass 12, count 2 2006.246.08:22:29.01#ibcon#about to write, iclass 12, count 2 2006.246.08:22:29.01#ibcon#wrote, iclass 12, count 2 2006.246.08:22:29.01#ibcon#about to read 3, iclass 12, count 2 2006.246.08:22:29.03#ibcon#read 3, iclass 12, count 2 2006.246.08:22:29.03#ibcon#about to read 4, iclass 12, count 2 2006.246.08:22:29.03#ibcon#read 4, iclass 12, count 2 2006.246.08:22:29.03#ibcon#about to read 5, iclass 12, count 2 2006.246.08:22:29.03#ibcon#read 5, iclass 12, count 2 2006.246.08:22:29.03#ibcon#about to read 6, iclass 12, count 2 2006.246.08:22:29.03#ibcon#read 6, iclass 12, count 2 2006.246.08:22:29.03#ibcon#end of sib2, iclass 12, count 2 2006.246.08:22:29.03#ibcon#*mode == 0, iclass 12, count 2 2006.246.08:22:29.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.08:22:29.03#ibcon#[25=AT04-07\r\n] 2006.246.08:22:29.03#ibcon#*before write, iclass 12, count 2 2006.246.08:22:29.03#ibcon#enter sib2, iclass 12, count 2 2006.246.08:22:29.03#ibcon#flushed, iclass 12, count 2 2006.246.08:22:29.03#ibcon#about to write, iclass 12, count 2 2006.246.08:22:29.03#ibcon#wrote, iclass 12, count 2 2006.246.08:22:29.03#ibcon#about to read 3, iclass 12, count 2 2006.246.08:22:29.06#ibcon#read 3, iclass 12, count 2 2006.246.08:22:29.06#ibcon#about to read 4, iclass 12, count 2 2006.246.08:22:29.06#ibcon#read 4, iclass 12, count 2 2006.246.08:22:29.06#ibcon#about to read 5, iclass 12, count 2 2006.246.08:22:29.06#ibcon#read 5, iclass 12, count 2 2006.246.08:22:29.06#ibcon#about to read 6, iclass 12, count 2 2006.246.08:22:29.06#ibcon#read 6, iclass 12, count 2 2006.246.08:22:29.06#ibcon#end of sib2, iclass 12, count 2 2006.246.08:22:29.06#ibcon#*after write, iclass 12, count 2 2006.246.08:22:29.06#ibcon#*before return 0, iclass 12, count 2 2006.246.08:22:29.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:29.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:29.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.08:22:29.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:29.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:29.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:29.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:29.18#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:22:29.18#ibcon#first serial, iclass 12, count 0 2006.246.08:22:29.18#ibcon#enter sib2, iclass 12, count 0 2006.246.08:22:29.18#ibcon#flushed, iclass 12, count 0 2006.246.08:22:29.18#ibcon#about to write, iclass 12, count 0 2006.246.08:22:29.18#ibcon#wrote, iclass 12, count 0 2006.246.08:22:29.18#ibcon#about to read 3, iclass 12, count 0 2006.246.08:22:29.20#ibcon#read 3, iclass 12, count 0 2006.246.08:22:29.20#ibcon#about to read 4, iclass 12, count 0 2006.246.08:22:29.20#ibcon#read 4, iclass 12, count 0 2006.246.08:22:29.20#ibcon#about to read 5, iclass 12, count 0 2006.246.08:22:29.20#ibcon#read 5, iclass 12, count 0 2006.246.08:22:29.20#ibcon#about to read 6, iclass 12, count 0 2006.246.08:22:29.20#ibcon#read 6, iclass 12, count 0 2006.246.08:22:29.20#ibcon#end of sib2, iclass 12, count 0 2006.246.08:22:29.20#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:22:29.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:22:29.20#ibcon#[25=USB\r\n] 2006.246.08:22:29.20#ibcon#*before write, iclass 12, count 0 2006.246.08:22:29.20#ibcon#enter sib2, iclass 12, count 0 2006.246.08:22:29.20#ibcon#flushed, iclass 12, count 0 2006.246.08:22:29.20#ibcon#about to write, iclass 12, count 0 2006.246.08:22:29.20#ibcon#wrote, iclass 12, count 0 2006.246.08:22:29.20#ibcon#about to read 3, iclass 12, count 0 2006.246.08:22:29.23#ibcon#read 3, iclass 12, count 0 2006.246.08:22:29.23#ibcon#about to read 4, iclass 12, count 0 2006.246.08:22:29.23#ibcon#read 4, iclass 12, count 0 2006.246.08:22:29.23#ibcon#about to read 5, iclass 12, count 0 2006.246.08:22:29.23#ibcon#read 5, iclass 12, count 0 2006.246.08:22:29.23#ibcon#about to read 6, iclass 12, count 0 2006.246.08:22:29.23#ibcon#read 6, iclass 12, count 0 2006.246.08:22:29.23#ibcon#end of sib2, iclass 12, count 0 2006.246.08:22:29.23#ibcon#*after write, iclass 12, count 0 2006.246.08:22:29.23#ibcon#*before return 0, iclass 12, count 0 2006.246.08:22:29.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:29.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:29.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:22:29.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:22:29.23$vc4f8/valo=5,652.99 2006.246.08:22:29.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.246.08:22:29.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.246.08:22:29.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:29.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:22:29.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:22:29.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:22:29.23#ibcon#enter wrdev, iclass 14, count 0 2006.246.08:22:29.23#ibcon#first serial, iclass 14, count 0 2006.246.08:22:29.23#ibcon#enter sib2, iclass 14, count 0 2006.246.08:22:29.23#ibcon#flushed, iclass 14, count 0 2006.246.08:22:29.23#ibcon#about to write, iclass 14, count 0 2006.246.08:22:29.23#ibcon#wrote, iclass 14, count 0 2006.246.08:22:29.23#ibcon#about to read 3, iclass 14, count 0 2006.246.08:22:29.25#ibcon#read 3, iclass 14, count 0 2006.246.08:22:29.25#ibcon#about to read 4, iclass 14, count 0 2006.246.08:22:29.25#ibcon#read 4, iclass 14, count 0 2006.246.08:22:29.25#ibcon#about to read 5, iclass 14, count 0 2006.246.08:22:29.25#ibcon#read 5, iclass 14, count 0 2006.246.08:22:29.25#ibcon#about to read 6, iclass 14, count 0 2006.246.08:22:29.25#ibcon#read 6, iclass 14, count 0 2006.246.08:22:29.25#ibcon#end of sib2, iclass 14, count 0 2006.246.08:22:29.25#ibcon#*mode == 0, iclass 14, count 0 2006.246.08:22:29.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.246.08:22:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:22:29.25#ibcon#*before write, iclass 14, count 0 2006.246.08:22:29.25#ibcon#enter sib2, iclass 14, count 0 2006.246.08:22:29.25#ibcon#flushed, iclass 14, count 0 2006.246.08:22:29.25#ibcon#about to write, iclass 14, count 0 2006.246.08:22:29.25#ibcon#wrote, iclass 14, count 0 2006.246.08:22:29.25#ibcon#about to read 3, iclass 14, count 0 2006.246.08:22:29.29#ibcon#read 3, iclass 14, count 0 2006.246.08:22:29.29#ibcon#about to read 4, iclass 14, count 0 2006.246.08:22:29.29#ibcon#read 4, iclass 14, count 0 2006.246.08:22:29.29#ibcon#about to read 5, iclass 14, count 0 2006.246.08:22:29.29#ibcon#read 5, iclass 14, count 0 2006.246.08:22:29.29#ibcon#about to read 6, iclass 14, count 0 2006.246.08:22:29.29#ibcon#read 6, iclass 14, count 0 2006.246.08:22:29.29#ibcon#end of sib2, iclass 14, count 0 2006.246.08:22:29.29#ibcon#*after write, iclass 14, count 0 2006.246.08:22:29.29#ibcon#*before return 0, iclass 14, count 0 2006.246.08:22:29.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:22:29.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.246.08:22:29.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.246.08:22:29.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.246.08:22:29.29$vc4f8/va=5,7 2006.246.08:22:29.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.246.08:22:29.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.246.08:22:29.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:29.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:22:29.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:22:29.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:22:29.35#ibcon#enter wrdev, iclass 16, count 2 2006.246.08:22:29.35#ibcon#first serial, iclass 16, count 2 2006.246.08:22:29.35#ibcon#enter sib2, iclass 16, count 2 2006.246.08:22:29.35#ibcon#flushed, iclass 16, count 2 2006.246.08:22:29.35#ibcon#about to write, iclass 16, count 2 2006.246.08:22:29.35#ibcon#wrote, iclass 16, count 2 2006.246.08:22:29.35#ibcon#about to read 3, iclass 16, count 2 2006.246.08:22:29.37#ibcon#read 3, iclass 16, count 2 2006.246.08:22:29.37#ibcon#about to read 4, iclass 16, count 2 2006.246.08:22:29.37#ibcon#read 4, iclass 16, count 2 2006.246.08:22:29.37#ibcon#about to read 5, iclass 16, count 2 2006.246.08:22:29.37#ibcon#read 5, iclass 16, count 2 2006.246.08:22:29.37#ibcon#about to read 6, iclass 16, count 2 2006.246.08:22:29.37#ibcon#read 6, iclass 16, count 2 2006.246.08:22:29.37#ibcon#end of sib2, iclass 16, count 2 2006.246.08:22:29.37#ibcon#*mode == 0, iclass 16, count 2 2006.246.08:22:29.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.246.08:22:29.37#ibcon#[25=AT05-07\r\n] 2006.246.08:22:29.37#ibcon#*before write, iclass 16, count 2 2006.246.08:22:29.37#ibcon#enter sib2, iclass 16, count 2 2006.246.08:22:29.37#ibcon#flushed, iclass 16, count 2 2006.246.08:22:29.37#ibcon#about to write, iclass 16, count 2 2006.246.08:22:29.37#ibcon#wrote, iclass 16, count 2 2006.246.08:22:29.37#ibcon#about to read 3, iclass 16, count 2 2006.246.08:22:29.40#ibcon#read 3, iclass 16, count 2 2006.246.08:22:29.40#ibcon#about to read 4, iclass 16, count 2 2006.246.08:22:29.40#ibcon#read 4, iclass 16, count 2 2006.246.08:22:29.40#ibcon#about to read 5, iclass 16, count 2 2006.246.08:22:29.40#ibcon#read 5, iclass 16, count 2 2006.246.08:22:29.40#ibcon#about to read 6, iclass 16, count 2 2006.246.08:22:29.40#ibcon#read 6, iclass 16, count 2 2006.246.08:22:29.40#ibcon#end of sib2, iclass 16, count 2 2006.246.08:22:29.40#ibcon#*after write, iclass 16, count 2 2006.246.08:22:29.40#ibcon#*before return 0, iclass 16, count 2 2006.246.08:22:29.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:22:29.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.246.08:22:29.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.246.08:22:29.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:29.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:22:29.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:22:29.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:22:29.52#ibcon#enter wrdev, iclass 16, count 0 2006.246.08:22:29.52#ibcon#first serial, iclass 16, count 0 2006.246.08:22:29.52#ibcon#enter sib2, iclass 16, count 0 2006.246.08:22:29.52#ibcon#flushed, iclass 16, count 0 2006.246.08:22:29.52#ibcon#about to write, iclass 16, count 0 2006.246.08:22:29.52#ibcon#wrote, iclass 16, count 0 2006.246.08:22:29.52#ibcon#about to read 3, iclass 16, count 0 2006.246.08:22:29.54#ibcon#read 3, iclass 16, count 0 2006.246.08:22:29.54#ibcon#about to read 4, iclass 16, count 0 2006.246.08:22:29.54#ibcon#read 4, iclass 16, count 0 2006.246.08:22:29.54#ibcon#about to read 5, iclass 16, count 0 2006.246.08:22:29.54#ibcon#read 5, iclass 16, count 0 2006.246.08:22:29.54#ibcon#about to read 6, iclass 16, count 0 2006.246.08:22:29.54#ibcon#read 6, iclass 16, count 0 2006.246.08:22:29.54#ibcon#end of sib2, iclass 16, count 0 2006.246.08:22:29.54#ibcon#*mode == 0, iclass 16, count 0 2006.246.08:22:29.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.246.08:22:29.54#ibcon#[25=USB\r\n] 2006.246.08:22:29.54#ibcon#*before write, iclass 16, count 0 2006.246.08:22:29.54#ibcon#enter sib2, iclass 16, count 0 2006.246.08:22:29.54#ibcon#flushed, iclass 16, count 0 2006.246.08:22:29.54#ibcon#about to write, iclass 16, count 0 2006.246.08:22:29.54#ibcon#wrote, iclass 16, count 0 2006.246.08:22:29.54#ibcon#about to read 3, iclass 16, count 0 2006.246.08:22:29.57#ibcon#read 3, iclass 16, count 0 2006.246.08:22:29.57#ibcon#about to read 4, iclass 16, count 0 2006.246.08:22:29.57#ibcon#read 4, iclass 16, count 0 2006.246.08:22:29.57#ibcon#about to read 5, iclass 16, count 0 2006.246.08:22:29.57#ibcon#read 5, iclass 16, count 0 2006.246.08:22:29.57#ibcon#about to read 6, iclass 16, count 0 2006.246.08:22:29.57#ibcon#read 6, iclass 16, count 0 2006.246.08:22:29.57#ibcon#end of sib2, iclass 16, count 0 2006.246.08:22:29.57#ibcon#*after write, iclass 16, count 0 2006.246.08:22:29.57#ibcon#*before return 0, iclass 16, count 0 2006.246.08:22:29.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:22:29.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.246.08:22:29.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.246.08:22:29.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.246.08:22:29.57$vc4f8/valo=6,772.99 2006.246.08:22:29.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.08:22:29.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.08:22:29.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:29.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:29.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:29.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:29.57#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:22:29.57#ibcon#first serial, iclass 18, count 0 2006.246.08:22:29.57#ibcon#enter sib2, iclass 18, count 0 2006.246.08:22:29.57#ibcon#flushed, iclass 18, count 0 2006.246.08:22:29.57#ibcon#about to write, iclass 18, count 0 2006.246.08:22:29.57#ibcon#wrote, iclass 18, count 0 2006.246.08:22:29.57#ibcon#about to read 3, iclass 18, count 0 2006.246.08:22:29.59#ibcon#read 3, iclass 18, count 0 2006.246.08:22:29.59#ibcon#about to read 4, iclass 18, count 0 2006.246.08:22:29.59#ibcon#read 4, iclass 18, count 0 2006.246.08:22:29.59#ibcon#about to read 5, iclass 18, count 0 2006.246.08:22:29.59#ibcon#read 5, iclass 18, count 0 2006.246.08:22:29.59#ibcon#about to read 6, iclass 18, count 0 2006.246.08:22:29.59#ibcon#read 6, iclass 18, count 0 2006.246.08:22:29.59#ibcon#end of sib2, iclass 18, count 0 2006.246.08:22:29.59#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:22:29.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:22:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:22:29.59#ibcon#*before write, iclass 18, count 0 2006.246.08:22:29.59#ibcon#enter sib2, iclass 18, count 0 2006.246.08:22:29.59#ibcon#flushed, iclass 18, count 0 2006.246.08:22:29.59#ibcon#about to write, iclass 18, count 0 2006.246.08:22:29.59#ibcon#wrote, iclass 18, count 0 2006.246.08:22:29.59#ibcon#about to read 3, iclass 18, count 0 2006.246.08:22:29.63#ibcon#read 3, iclass 18, count 0 2006.246.08:22:29.63#ibcon#about to read 4, iclass 18, count 0 2006.246.08:22:29.63#ibcon#read 4, iclass 18, count 0 2006.246.08:22:29.63#ibcon#about to read 5, iclass 18, count 0 2006.246.08:22:29.63#ibcon#read 5, iclass 18, count 0 2006.246.08:22:29.63#ibcon#about to read 6, iclass 18, count 0 2006.246.08:22:29.63#ibcon#read 6, iclass 18, count 0 2006.246.08:22:29.63#ibcon#end of sib2, iclass 18, count 0 2006.246.08:22:29.63#ibcon#*after write, iclass 18, count 0 2006.246.08:22:29.63#ibcon#*before return 0, iclass 18, count 0 2006.246.08:22:29.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:29.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:29.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:22:29.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:22:29.63$vc4f8/va=6,7 2006.246.08:22:29.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.08:22:29.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.08:22:29.63#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:29.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:29.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:29.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:29.69#ibcon#enter wrdev, iclass 20, count 2 2006.246.08:22:29.69#ibcon#first serial, iclass 20, count 2 2006.246.08:22:29.69#ibcon#enter sib2, iclass 20, count 2 2006.246.08:22:29.69#ibcon#flushed, iclass 20, count 2 2006.246.08:22:29.69#ibcon#about to write, iclass 20, count 2 2006.246.08:22:29.69#ibcon#wrote, iclass 20, count 2 2006.246.08:22:29.69#ibcon#about to read 3, iclass 20, count 2 2006.246.08:22:29.71#ibcon#read 3, iclass 20, count 2 2006.246.08:22:29.71#ibcon#about to read 4, iclass 20, count 2 2006.246.08:22:29.71#ibcon#read 4, iclass 20, count 2 2006.246.08:22:29.71#ibcon#about to read 5, iclass 20, count 2 2006.246.08:22:29.71#ibcon#read 5, iclass 20, count 2 2006.246.08:22:29.71#ibcon#about to read 6, iclass 20, count 2 2006.246.08:22:29.71#ibcon#read 6, iclass 20, count 2 2006.246.08:22:29.71#ibcon#end of sib2, iclass 20, count 2 2006.246.08:22:29.71#ibcon#*mode == 0, iclass 20, count 2 2006.246.08:22:29.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.08:22:29.71#ibcon#[25=AT06-07\r\n] 2006.246.08:22:29.71#ibcon#*before write, iclass 20, count 2 2006.246.08:22:29.71#ibcon#enter sib2, iclass 20, count 2 2006.246.08:22:29.71#ibcon#flushed, iclass 20, count 2 2006.246.08:22:29.71#ibcon#about to write, iclass 20, count 2 2006.246.08:22:29.71#ibcon#wrote, iclass 20, count 2 2006.246.08:22:29.71#ibcon#about to read 3, iclass 20, count 2 2006.246.08:22:29.74#ibcon#read 3, iclass 20, count 2 2006.246.08:22:29.74#ibcon#about to read 4, iclass 20, count 2 2006.246.08:22:29.74#ibcon#read 4, iclass 20, count 2 2006.246.08:22:29.74#ibcon#about to read 5, iclass 20, count 2 2006.246.08:22:29.74#ibcon#read 5, iclass 20, count 2 2006.246.08:22:29.74#ibcon#about to read 6, iclass 20, count 2 2006.246.08:22:29.74#ibcon#read 6, iclass 20, count 2 2006.246.08:22:29.74#ibcon#end of sib2, iclass 20, count 2 2006.246.08:22:29.74#ibcon#*after write, iclass 20, count 2 2006.246.08:22:29.74#ibcon#*before return 0, iclass 20, count 2 2006.246.08:22:29.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:29.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:29.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.08:22:29.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:29.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:29.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:29.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:29.86#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:22:29.86#ibcon#first serial, iclass 20, count 0 2006.246.08:22:29.86#ibcon#enter sib2, iclass 20, count 0 2006.246.08:22:29.86#ibcon#flushed, iclass 20, count 0 2006.246.08:22:29.86#ibcon#about to write, iclass 20, count 0 2006.246.08:22:29.86#ibcon#wrote, iclass 20, count 0 2006.246.08:22:29.86#ibcon#about to read 3, iclass 20, count 0 2006.246.08:22:29.88#ibcon#read 3, iclass 20, count 0 2006.246.08:22:29.88#ibcon#about to read 4, iclass 20, count 0 2006.246.08:22:29.88#ibcon#read 4, iclass 20, count 0 2006.246.08:22:29.88#ibcon#about to read 5, iclass 20, count 0 2006.246.08:22:29.88#ibcon#read 5, iclass 20, count 0 2006.246.08:22:29.88#ibcon#about to read 6, iclass 20, count 0 2006.246.08:22:29.88#ibcon#read 6, iclass 20, count 0 2006.246.08:22:29.88#ibcon#end of sib2, iclass 20, count 0 2006.246.08:22:29.88#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:22:29.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:22:29.88#ibcon#[25=USB\r\n] 2006.246.08:22:29.88#ibcon#*before write, iclass 20, count 0 2006.246.08:22:29.88#ibcon#enter sib2, iclass 20, count 0 2006.246.08:22:29.88#ibcon#flushed, iclass 20, count 0 2006.246.08:22:29.88#ibcon#about to write, iclass 20, count 0 2006.246.08:22:29.88#ibcon#wrote, iclass 20, count 0 2006.246.08:22:29.88#ibcon#about to read 3, iclass 20, count 0 2006.246.08:22:29.91#ibcon#read 3, iclass 20, count 0 2006.246.08:22:29.91#ibcon#about to read 4, iclass 20, count 0 2006.246.08:22:29.91#ibcon#read 4, iclass 20, count 0 2006.246.08:22:29.91#ibcon#about to read 5, iclass 20, count 0 2006.246.08:22:29.91#ibcon#read 5, iclass 20, count 0 2006.246.08:22:29.91#ibcon#about to read 6, iclass 20, count 0 2006.246.08:22:29.91#ibcon#read 6, iclass 20, count 0 2006.246.08:22:29.91#ibcon#end of sib2, iclass 20, count 0 2006.246.08:22:29.91#ibcon#*after write, iclass 20, count 0 2006.246.08:22:29.91#ibcon#*before return 0, iclass 20, count 0 2006.246.08:22:29.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:29.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:29.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:22:29.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:22:29.91$vc4f8/valo=7,832.99 2006.246.08:22:29.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.08:22:29.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.08:22:29.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:29.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:29.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:29.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:29.91#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:22:29.91#ibcon#first serial, iclass 22, count 0 2006.246.08:22:29.91#ibcon#enter sib2, iclass 22, count 0 2006.246.08:22:29.91#ibcon#flushed, iclass 22, count 0 2006.246.08:22:29.91#ibcon#about to write, iclass 22, count 0 2006.246.08:22:29.91#ibcon#wrote, iclass 22, count 0 2006.246.08:22:29.91#ibcon#about to read 3, iclass 22, count 0 2006.246.08:22:29.93#ibcon#read 3, iclass 22, count 0 2006.246.08:22:29.93#ibcon#about to read 4, iclass 22, count 0 2006.246.08:22:29.93#ibcon#read 4, iclass 22, count 0 2006.246.08:22:29.93#ibcon#about to read 5, iclass 22, count 0 2006.246.08:22:29.93#ibcon#read 5, iclass 22, count 0 2006.246.08:22:29.93#ibcon#about to read 6, iclass 22, count 0 2006.246.08:22:29.93#ibcon#read 6, iclass 22, count 0 2006.246.08:22:29.93#ibcon#end of sib2, iclass 22, count 0 2006.246.08:22:29.93#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:22:29.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:22:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:22:29.93#ibcon#*before write, iclass 22, count 0 2006.246.08:22:29.93#ibcon#enter sib2, iclass 22, count 0 2006.246.08:22:29.93#ibcon#flushed, iclass 22, count 0 2006.246.08:22:29.93#ibcon#about to write, iclass 22, count 0 2006.246.08:22:29.93#ibcon#wrote, iclass 22, count 0 2006.246.08:22:29.93#ibcon#about to read 3, iclass 22, count 0 2006.246.08:22:29.97#ibcon#read 3, iclass 22, count 0 2006.246.08:22:29.97#ibcon#about to read 4, iclass 22, count 0 2006.246.08:22:29.97#ibcon#read 4, iclass 22, count 0 2006.246.08:22:29.97#ibcon#about to read 5, iclass 22, count 0 2006.246.08:22:29.97#ibcon#read 5, iclass 22, count 0 2006.246.08:22:29.97#ibcon#about to read 6, iclass 22, count 0 2006.246.08:22:29.97#ibcon#read 6, iclass 22, count 0 2006.246.08:22:29.97#ibcon#end of sib2, iclass 22, count 0 2006.246.08:22:29.97#ibcon#*after write, iclass 22, count 0 2006.246.08:22:29.97#ibcon#*before return 0, iclass 22, count 0 2006.246.08:22:29.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:29.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:29.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:22:29.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:22:29.97$vc4f8/va=7,7 2006.246.08:22:29.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.246.08:22:29.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.246.08:22:29.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:29.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:22:30.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:22:30.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:22:30.03#ibcon#enter wrdev, iclass 24, count 2 2006.246.08:22:30.03#ibcon#first serial, iclass 24, count 2 2006.246.08:22:30.03#ibcon#enter sib2, iclass 24, count 2 2006.246.08:22:30.03#ibcon#flushed, iclass 24, count 2 2006.246.08:22:30.03#ibcon#about to write, iclass 24, count 2 2006.246.08:22:30.03#ibcon#wrote, iclass 24, count 2 2006.246.08:22:30.03#ibcon#about to read 3, iclass 24, count 2 2006.246.08:22:30.05#ibcon#read 3, iclass 24, count 2 2006.246.08:22:30.05#ibcon#about to read 4, iclass 24, count 2 2006.246.08:22:30.05#ibcon#read 4, iclass 24, count 2 2006.246.08:22:30.05#ibcon#about to read 5, iclass 24, count 2 2006.246.08:22:30.05#ibcon#read 5, iclass 24, count 2 2006.246.08:22:30.05#ibcon#about to read 6, iclass 24, count 2 2006.246.08:22:30.05#ibcon#read 6, iclass 24, count 2 2006.246.08:22:30.05#ibcon#end of sib2, iclass 24, count 2 2006.246.08:22:30.05#ibcon#*mode == 0, iclass 24, count 2 2006.246.08:22:30.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.246.08:22:30.05#ibcon#[25=AT07-07\r\n] 2006.246.08:22:30.05#ibcon#*before write, iclass 24, count 2 2006.246.08:22:30.05#ibcon#enter sib2, iclass 24, count 2 2006.246.08:22:30.05#ibcon#flushed, iclass 24, count 2 2006.246.08:22:30.05#ibcon#about to write, iclass 24, count 2 2006.246.08:22:30.05#ibcon#wrote, iclass 24, count 2 2006.246.08:22:30.05#ibcon#about to read 3, iclass 24, count 2 2006.246.08:22:30.08#ibcon#read 3, iclass 24, count 2 2006.246.08:22:30.08#ibcon#about to read 4, iclass 24, count 2 2006.246.08:22:30.08#ibcon#read 4, iclass 24, count 2 2006.246.08:22:30.08#ibcon#about to read 5, iclass 24, count 2 2006.246.08:22:30.08#ibcon#read 5, iclass 24, count 2 2006.246.08:22:30.08#ibcon#about to read 6, iclass 24, count 2 2006.246.08:22:30.08#ibcon#read 6, iclass 24, count 2 2006.246.08:22:30.08#ibcon#end of sib2, iclass 24, count 2 2006.246.08:22:30.08#ibcon#*after write, iclass 24, count 2 2006.246.08:22:30.08#ibcon#*before return 0, iclass 24, count 2 2006.246.08:22:30.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:22:30.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.246.08:22:30.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.246.08:22:30.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:30.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:22:30.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:22:30.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:22:30.20#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:22:30.20#ibcon#first serial, iclass 24, count 0 2006.246.08:22:30.20#ibcon#enter sib2, iclass 24, count 0 2006.246.08:22:30.20#ibcon#flushed, iclass 24, count 0 2006.246.08:22:30.20#ibcon#about to write, iclass 24, count 0 2006.246.08:22:30.20#ibcon#wrote, iclass 24, count 0 2006.246.08:22:30.20#ibcon#about to read 3, iclass 24, count 0 2006.246.08:22:30.22#ibcon#read 3, iclass 24, count 0 2006.246.08:22:30.22#ibcon#about to read 4, iclass 24, count 0 2006.246.08:22:30.22#ibcon#read 4, iclass 24, count 0 2006.246.08:22:30.22#ibcon#about to read 5, iclass 24, count 0 2006.246.08:22:30.22#ibcon#read 5, iclass 24, count 0 2006.246.08:22:30.22#ibcon#about to read 6, iclass 24, count 0 2006.246.08:22:30.22#ibcon#read 6, iclass 24, count 0 2006.246.08:22:30.22#ibcon#end of sib2, iclass 24, count 0 2006.246.08:22:30.22#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:22:30.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:22:30.22#ibcon#[25=USB\r\n] 2006.246.08:22:30.22#ibcon#*before write, iclass 24, count 0 2006.246.08:22:30.22#ibcon#enter sib2, iclass 24, count 0 2006.246.08:22:30.22#ibcon#flushed, iclass 24, count 0 2006.246.08:22:30.22#ibcon#about to write, iclass 24, count 0 2006.246.08:22:30.22#ibcon#wrote, iclass 24, count 0 2006.246.08:22:30.22#ibcon#about to read 3, iclass 24, count 0 2006.246.08:22:30.25#ibcon#read 3, iclass 24, count 0 2006.246.08:22:30.25#ibcon#about to read 4, iclass 24, count 0 2006.246.08:22:30.25#ibcon#read 4, iclass 24, count 0 2006.246.08:22:30.25#ibcon#about to read 5, iclass 24, count 0 2006.246.08:22:30.25#ibcon#read 5, iclass 24, count 0 2006.246.08:22:30.25#ibcon#about to read 6, iclass 24, count 0 2006.246.08:22:30.25#ibcon#read 6, iclass 24, count 0 2006.246.08:22:30.25#ibcon#end of sib2, iclass 24, count 0 2006.246.08:22:30.25#ibcon#*after write, iclass 24, count 0 2006.246.08:22:30.25#ibcon#*before return 0, iclass 24, count 0 2006.246.08:22:30.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:22:30.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.246.08:22:30.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:22:30.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:22:30.25$vc4f8/valo=8,852.99 2006.246.08:22:30.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.246.08:22:30.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.246.08:22:30.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:30.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:22:30.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:22:30.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:22:30.25#ibcon#enter wrdev, iclass 26, count 0 2006.246.08:22:30.25#ibcon#first serial, iclass 26, count 0 2006.246.08:22:30.25#ibcon#enter sib2, iclass 26, count 0 2006.246.08:22:30.25#ibcon#flushed, iclass 26, count 0 2006.246.08:22:30.25#ibcon#about to write, iclass 26, count 0 2006.246.08:22:30.25#ibcon#wrote, iclass 26, count 0 2006.246.08:22:30.25#ibcon#about to read 3, iclass 26, count 0 2006.246.08:22:30.27#ibcon#read 3, iclass 26, count 0 2006.246.08:22:30.27#ibcon#about to read 4, iclass 26, count 0 2006.246.08:22:30.27#ibcon#read 4, iclass 26, count 0 2006.246.08:22:30.27#ibcon#about to read 5, iclass 26, count 0 2006.246.08:22:30.27#ibcon#read 5, iclass 26, count 0 2006.246.08:22:30.27#ibcon#about to read 6, iclass 26, count 0 2006.246.08:22:30.27#ibcon#read 6, iclass 26, count 0 2006.246.08:22:30.27#ibcon#end of sib2, iclass 26, count 0 2006.246.08:22:30.27#ibcon#*mode == 0, iclass 26, count 0 2006.246.08:22:30.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.246.08:22:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:22:30.27#ibcon#*before write, iclass 26, count 0 2006.246.08:22:30.27#ibcon#enter sib2, iclass 26, count 0 2006.246.08:22:30.27#ibcon#flushed, iclass 26, count 0 2006.246.08:22:30.27#ibcon#about to write, iclass 26, count 0 2006.246.08:22:30.27#ibcon#wrote, iclass 26, count 0 2006.246.08:22:30.27#ibcon#about to read 3, iclass 26, count 0 2006.246.08:22:30.31#ibcon#read 3, iclass 26, count 0 2006.246.08:22:30.31#ibcon#about to read 4, iclass 26, count 0 2006.246.08:22:30.31#ibcon#read 4, iclass 26, count 0 2006.246.08:22:30.31#ibcon#about to read 5, iclass 26, count 0 2006.246.08:22:30.31#ibcon#read 5, iclass 26, count 0 2006.246.08:22:30.31#ibcon#about to read 6, iclass 26, count 0 2006.246.08:22:30.31#ibcon#read 6, iclass 26, count 0 2006.246.08:22:30.31#ibcon#end of sib2, iclass 26, count 0 2006.246.08:22:30.31#ibcon#*after write, iclass 26, count 0 2006.246.08:22:30.31#ibcon#*before return 0, iclass 26, count 0 2006.246.08:22:30.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:22:30.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.246.08:22:30.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.246.08:22:30.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.246.08:22:30.31$vc4f8/va=8,8 2006.246.08:22:30.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.246.08:22:30.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.246.08:22:30.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:30.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:22:30.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:22:30.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:22:30.37#ibcon#enter wrdev, iclass 28, count 2 2006.246.08:22:30.37#ibcon#first serial, iclass 28, count 2 2006.246.08:22:30.37#ibcon#enter sib2, iclass 28, count 2 2006.246.08:22:30.37#ibcon#flushed, iclass 28, count 2 2006.246.08:22:30.37#ibcon#about to write, iclass 28, count 2 2006.246.08:22:30.37#ibcon#wrote, iclass 28, count 2 2006.246.08:22:30.37#ibcon#about to read 3, iclass 28, count 2 2006.246.08:22:30.39#ibcon#read 3, iclass 28, count 2 2006.246.08:22:30.39#ibcon#about to read 4, iclass 28, count 2 2006.246.08:22:30.39#ibcon#read 4, iclass 28, count 2 2006.246.08:22:30.39#ibcon#about to read 5, iclass 28, count 2 2006.246.08:22:30.39#ibcon#read 5, iclass 28, count 2 2006.246.08:22:30.39#ibcon#about to read 6, iclass 28, count 2 2006.246.08:22:30.39#ibcon#read 6, iclass 28, count 2 2006.246.08:22:30.39#ibcon#end of sib2, iclass 28, count 2 2006.246.08:22:30.39#ibcon#*mode == 0, iclass 28, count 2 2006.246.08:22:30.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.246.08:22:30.39#ibcon#[25=AT08-08\r\n] 2006.246.08:22:30.39#ibcon#*before write, iclass 28, count 2 2006.246.08:22:30.39#ibcon#enter sib2, iclass 28, count 2 2006.246.08:22:30.39#ibcon#flushed, iclass 28, count 2 2006.246.08:22:30.39#ibcon#about to write, iclass 28, count 2 2006.246.08:22:30.39#ibcon#wrote, iclass 28, count 2 2006.246.08:22:30.39#ibcon#about to read 3, iclass 28, count 2 2006.246.08:22:30.42#ibcon#read 3, iclass 28, count 2 2006.246.08:22:30.42#ibcon#about to read 4, iclass 28, count 2 2006.246.08:22:30.42#ibcon#read 4, iclass 28, count 2 2006.246.08:22:30.42#ibcon#about to read 5, iclass 28, count 2 2006.246.08:22:30.42#ibcon#read 5, iclass 28, count 2 2006.246.08:22:30.42#ibcon#about to read 6, iclass 28, count 2 2006.246.08:22:30.42#ibcon#read 6, iclass 28, count 2 2006.246.08:22:30.42#ibcon#end of sib2, iclass 28, count 2 2006.246.08:22:30.42#ibcon#*after write, iclass 28, count 2 2006.246.08:22:30.42#ibcon#*before return 0, iclass 28, count 2 2006.246.08:22:30.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:22:30.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.246.08:22:30.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.246.08:22:30.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:30.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:22:30.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:22:30.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:22:30.54#ibcon#enter wrdev, iclass 28, count 0 2006.246.08:22:30.54#ibcon#first serial, iclass 28, count 0 2006.246.08:22:30.54#ibcon#enter sib2, iclass 28, count 0 2006.246.08:22:30.54#ibcon#flushed, iclass 28, count 0 2006.246.08:22:30.54#ibcon#about to write, iclass 28, count 0 2006.246.08:22:30.54#ibcon#wrote, iclass 28, count 0 2006.246.08:22:30.54#ibcon#about to read 3, iclass 28, count 0 2006.246.08:22:30.56#ibcon#read 3, iclass 28, count 0 2006.246.08:22:30.56#ibcon#about to read 4, iclass 28, count 0 2006.246.08:22:30.56#ibcon#read 4, iclass 28, count 0 2006.246.08:22:30.56#ibcon#about to read 5, iclass 28, count 0 2006.246.08:22:30.56#ibcon#read 5, iclass 28, count 0 2006.246.08:22:30.56#ibcon#about to read 6, iclass 28, count 0 2006.246.08:22:30.56#ibcon#read 6, iclass 28, count 0 2006.246.08:22:30.56#ibcon#end of sib2, iclass 28, count 0 2006.246.08:22:30.56#ibcon#*mode == 0, iclass 28, count 0 2006.246.08:22:30.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.246.08:22:30.56#ibcon#[25=USB\r\n] 2006.246.08:22:30.56#ibcon#*before write, iclass 28, count 0 2006.246.08:22:30.56#ibcon#enter sib2, iclass 28, count 0 2006.246.08:22:30.56#ibcon#flushed, iclass 28, count 0 2006.246.08:22:30.56#ibcon#about to write, iclass 28, count 0 2006.246.08:22:30.56#ibcon#wrote, iclass 28, count 0 2006.246.08:22:30.56#ibcon#about to read 3, iclass 28, count 0 2006.246.08:22:30.59#ibcon#read 3, iclass 28, count 0 2006.246.08:22:30.59#ibcon#about to read 4, iclass 28, count 0 2006.246.08:22:30.59#ibcon#read 4, iclass 28, count 0 2006.246.08:22:30.59#ibcon#about to read 5, iclass 28, count 0 2006.246.08:22:30.59#ibcon#read 5, iclass 28, count 0 2006.246.08:22:30.59#ibcon#about to read 6, iclass 28, count 0 2006.246.08:22:30.59#ibcon#read 6, iclass 28, count 0 2006.246.08:22:30.59#ibcon#end of sib2, iclass 28, count 0 2006.246.08:22:30.59#ibcon#*after write, iclass 28, count 0 2006.246.08:22:30.59#ibcon#*before return 0, iclass 28, count 0 2006.246.08:22:30.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:22:30.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.246.08:22:30.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.246.08:22:30.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.246.08:22:30.59$vc4f8/vblo=1,632.99 2006.246.08:22:30.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.246.08:22:30.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.246.08:22:30.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:30.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:22:30.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:22:30.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:22:30.59#ibcon#enter wrdev, iclass 30, count 0 2006.246.08:22:30.59#ibcon#first serial, iclass 30, count 0 2006.246.08:22:30.59#ibcon#enter sib2, iclass 30, count 0 2006.246.08:22:30.59#ibcon#flushed, iclass 30, count 0 2006.246.08:22:30.59#ibcon#about to write, iclass 30, count 0 2006.246.08:22:30.59#ibcon#wrote, iclass 30, count 0 2006.246.08:22:30.59#ibcon#about to read 3, iclass 30, count 0 2006.246.08:22:30.61#ibcon#read 3, iclass 30, count 0 2006.246.08:22:30.61#ibcon#about to read 4, iclass 30, count 0 2006.246.08:22:30.61#ibcon#read 4, iclass 30, count 0 2006.246.08:22:30.61#ibcon#about to read 5, iclass 30, count 0 2006.246.08:22:30.61#ibcon#read 5, iclass 30, count 0 2006.246.08:22:30.61#ibcon#about to read 6, iclass 30, count 0 2006.246.08:22:30.61#ibcon#read 6, iclass 30, count 0 2006.246.08:22:30.61#ibcon#end of sib2, iclass 30, count 0 2006.246.08:22:30.61#ibcon#*mode == 0, iclass 30, count 0 2006.246.08:22:30.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.246.08:22:30.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:22:30.61#ibcon#*before write, iclass 30, count 0 2006.246.08:22:30.61#ibcon#enter sib2, iclass 30, count 0 2006.246.08:22:30.61#ibcon#flushed, iclass 30, count 0 2006.246.08:22:30.61#ibcon#about to write, iclass 30, count 0 2006.246.08:22:30.61#ibcon#wrote, iclass 30, count 0 2006.246.08:22:30.61#ibcon#about to read 3, iclass 30, count 0 2006.246.08:22:30.65#ibcon#read 3, iclass 30, count 0 2006.246.08:22:30.65#ibcon#about to read 4, iclass 30, count 0 2006.246.08:22:30.65#ibcon#read 4, iclass 30, count 0 2006.246.08:22:30.65#ibcon#about to read 5, iclass 30, count 0 2006.246.08:22:30.65#ibcon#read 5, iclass 30, count 0 2006.246.08:22:30.65#ibcon#about to read 6, iclass 30, count 0 2006.246.08:22:30.65#ibcon#read 6, iclass 30, count 0 2006.246.08:22:30.65#ibcon#end of sib2, iclass 30, count 0 2006.246.08:22:30.65#ibcon#*after write, iclass 30, count 0 2006.246.08:22:30.65#ibcon#*before return 0, iclass 30, count 0 2006.246.08:22:30.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:22:30.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.246.08:22:30.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.246.08:22:30.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.246.08:22:30.65$vc4f8/vb=1,4 2006.246.08:22:30.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.246.08:22:30.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.246.08:22:30.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:30.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:22:30.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:22:30.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:22:30.65#ibcon#enter wrdev, iclass 32, count 2 2006.246.08:22:30.65#ibcon#first serial, iclass 32, count 2 2006.246.08:22:30.65#ibcon#enter sib2, iclass 32, count 2 2006.246.08:22:30.65#ibcon#flushed, iclass 32, count 2 2006.246.08:22:30.65#ibcon#about to write, iclass 32, count 2 2006.246.08:22:30.65#ibcon#wrote, iclass 32, count 2 2006.246.08:22:30.65#ibcon#about to read 3, iclass 32, count 2 2006.246.08:22:30.67#ibcon#read 3, iclass 32, count 2 2006.246.08:22:30.67#ibcon#about to read 4, iclass 32, count 2 2006.246.08:22:30.67#ibcon#read 4, iclass 32, count 2 2006.246.08:22:30.67#ibcon#about to read 5, iclass 32, count 2 2006.246.08:22:30.67#ibcon#read 5, iclass 32, count 2 2006.246.08:22:30.67#ibcon#about to read 6, iclass 32, count 2 2006.246.08:22:30.67#ibcon#read 6, iclass 32, count 2 2006.246.08:22:30.67#ibcon#end of sib2, iclass 32, count 2 2006.246.08:22:30.67#ibcon#*mode == 0, iclass 32, count 2 2006.246.08:22:30.67#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.246.08:22:30.67#ibcon#[27=AT01-04\r\n] 2006.246.08:22:30.67#ibcon#*before write, iclass 32, count 2 2006.246.08:22:30.67#ibcon#enter sib2, iclass 32, count 2 2006.246.08:22:30.67#ibcon#flushed, iclass 32, count 2 2006.246.08:22:30.67#ibcon#about to write, iclass 32, count 2 2006.246.08:22:30.67#ibcon#wrote, iclass 32, count 2 2006.246.08:22:30.67#ibcon#about to read 3, iclass 32, count 2 2006.246.08:22:30.70#ibcon#read 3, iclass 32, count 2 2006.246.08:22:30.70#ibcon#about to read 4, iclass 32, count 2 2006.246.08:22:30.70#ibcon#read 4, iclass 32, count 2 2006.246.08:22:30.70#ibcon#about to read 5, iclass 32, count 2 2006.246.08:22:30.70#ibcon#read 5, iclass 32, count 2 2006.246.08:22:30.70#ibcon#about to read 6, iclass 32, count 2 2006.246.08:22:30.70#ibcon#read 6, iclass 32, count 2 2006.246.08:22:30.70#ibcon#end of sib2, iclass 32, count 2 2006.246.08:22:30.70#ibcon#*after write, iclass 32, count 2 2006.246.08:22:30.70#ibcon#*before return 0, iclass 32, count 2 2006.246.08:22:30.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:22:30.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.246.08:22:30.70#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.246.08:22:30.70#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:30.70#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:22:30.82#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:22:30.82#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:22:30.82#ibcon#enter wrdev, iclass 32, count 0 2006.246.08:22:30.82#ibcon#first serial, iclass 32, count 0 2006.246.08:22:30.82#ibcon#enter sib2, iclass 32, count 0 2006.246.08:22:30.82#ibcon#flushed, iclass 32, count 0 2006.246.08:22:30.82#ibcon#about to write, iclass 32, count 0 2006.246.08:22:30.82#ibcon#wrote, iclass 32, count 0 2006.246.08:22:30.82#ibcon#about to read 3, iclass 32, count 0 2006.246.08:22:30.84#ibcon#read 3, iclass 32, count 0 2006.246.08:22:30.84#ibcon#about to read 4, iclass 32, count 0 2006.246.08:22:30.84#ibcon#read 4, iclass 32, count 0 2006.246.08:22:30.84#ibcon#about to read 5, iclass 32, count 0 2006.246.08:22:30.84#ibcon#read 5, iclass 32, count 0 2006.246.08:22:30.84#ibcon#about to read 6, iclass 32, count 0 2006.246.08:22:30.84#ibcon#read 6, iclass 32, count 0 2006.246.08:22:30.84#ibcon#end of sib2, iclass 32, count 0 2006.246.08:22:30.84#ibcon#*mode == 0, iclass 32, count 0 2006.246.08:22:30.84#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.246.08:22:30.84#ibcon#[27=USB\r\n] 2006.246.08:22:30.84#ibcon#*before write, iclass 32, count 0 2006.246.08:22:30.84#ibcon#enter sib2, iclass 32, count 0 2006.246.08:22:30.84#ibcon#flushed, iclass 32, count 0 2006.246.08:22:30.84#ibcon#about to write, iclass 32, count 0 2006.246.08:22:30.84#ibcon#wrote, iclass 32, count 0 2006.246.08:22:30.84#ibcon#about to read 3, iclass 32, count 0 2006.246.08:22:30.87#ibcon#read 3, iclass 32, count 0 2006.246.08:22:30.87#ibcon#about to read 4, iclass 32, count 0 2006.246.08:22:30.87#ibcon#read 4, iclass 32, count 0 2006.246.08:22:30.87#ibcon#about to read 5, iclass 32, count 0 2006.246.08:22:30.87#ibcon#read 5, iclass 32, count 0 2006.246.08:22:30.87#ibcon#about to read 6, iclass 32, count 0 2006.246.08:22:30.87#ibcon#read 6, iclass 32, count 0 2006.246.08:22:30.87#ibcon#end of sib2, iclass 32, count 0 2006.246.08:22:30.87#ibcon#*after write, iclass 32, count 0 2006.246.08:22:30.87#ibcon#*before return 0, iclass 32, count 0 2006.246.08:22:30.87#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:22:30.87#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.246.08:22:30.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.246.08:22:30.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.246.08:22:30.87$vc4f8/vblo=2,640.99 2006.246.08:22:30.87#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.246.08:22:30.87#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.246.08:22:30.87#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:30.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:30.87#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:30.87#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:30.87#ibcon#enter wrdev, iclass 34, count 0 2006.246.08:22:30.87#ibcon#first serial, iclass 34, count 0 2006.246.08:22:30.87#ibcon#enter sib2, iclass 34, count 0 2006.246.08:22:30.87#ibcon#flushed, iclass 34, count 0 2006.246.08:22:30.87#ibcon#about to write, iclass 34, count 0 2006.246.08:22:30.87#ibcon#wrote, iclass 34, count 0 2006.246.08:22:30.87#ibcon#about to read 3, iclass 34, count 0 2006.246.08:22:30.89#ibcon#read 3, iclass 34, count 0 2006.246.08:22:30.89#ibcon#about to read 4, iclass 34, count 0 2006.246.08:22:30.89#ibcon#read 4, iclass 34, count 0 2006.246.08:22:30.89#ibcon#about to read 5, iclass 34, count 0 2006.246.08:22:30.89#ibcon#read 5, iclass 34, count 0 2006.246.08:22:30.89#ibcon#about to read 6, iclass 34, count 0 2006.246.08:22:30.89#ibcon#read 6, iclass 34, count 0 2006.246.08:22:30.89#ibcon#end of sib2, iclass 34, count 0 2006.246.08:22:30.89#ibcon#*mode == 0, iclass 34, count 0 2006.246.08:22:30.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.246.08:22:30.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:22:30.89#ibcon#*before write, iclass 34, count 0 2006.246.08:22:30.89#ibcon#enter sib2, iclass 34, count 0 2006.246.08:22:30.89#ibcon#flushed, iclass 34, count 0 2006.246.08:22:30.89#ibcon#about to write, iclass 34, count 0 2006.246.08:22:30.89#ibcon#wrote, iclass 34, count 0 2006.246.08:22:30.89#ibcon#about to read 3, iclass 34, count 0 2006.246.08:22:30.93#ibcon#read 3, iclass 34, count 0 2006.246.08:22:30.93#ibcon#about to read 4, iclass 34, count 0 2006.246.08:22:30.93#ibcon#read 4, iclass 34, count 0 2006.246.08:22:30.93#ibcon#about to read 5, iclass 34, count 0 2006.246.08:22:30.93#ibcon#read 5, iclass 34, count 0 2006.246.08:22:30.93#ibcon#about to read 6, iclass 34, count 0 2006.246.08:22:30.93#ibcon#read 6, iclass 34, count 0 2006.246.08:22:30.93#ibcon#end of sib2, iclass 34, count 0 2006.246.08:22:30.93#ibcon#*after write, iclass 34, count 0 2006.246.08:22:30.93#ibcon#*before return 0, iclass 34, count 0 2006.246.08:22:30.93#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:30.93#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.246.08:22:30.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.246.08:22:30.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.246.08:22:30.93$vc4f8/vb=2,4 2006.246.08:22:30.93#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.246.08:22:30.93#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.246.08:22:30.93#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:30.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:30.99#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:30.99#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:30.99#ibcon#enter wrdev, iclass 36, count 2 2006.246.08:22:30.99#ibcon#first serial, iclass 36, count 2 2006.246.08:22:30.99#ibcon#enter sib2, iclass 36, count 2 2006.246.08:22:30.99#ibcon#flushed, iclass 36, count 2 2006.246.08:22:30.99#ibcon#about to write, iclass 36, count 2 2006.246.08:22:30.99#ibcon#wrote, iclass 36, count 2 2006.246.08:22:30.99#ibcon#about to read 3, iclass 36, count 2 2006.246.08:22:31.01#ibcon#read 3, iclass 36, count 2 2006.246.08:22:31.01#ibcon#about to read 4, iclass 36, count 2 2006.246.08:22:31.01#ibcon#read 4, iclass 36, count 2 2006.246.08:22:31.01#ibcon#about to read 5, iclass 36, count 2 2006.246.08:22:31.01#ibcon#read 5, iclass 36, count 2 2006.246.08:22:31.01#ibcon#about to read 6, iclass 36, count 2 2006.246.08:22:31.01#ibcon#read 6, iclass 36, count 2 2006.246.08:22:31.01#ibcon#end of sib2, iclass 36, count 2 2006.246.08:22:31.01#ibcon#*mode == 0, iclass 36, count 2 2006.246.08:22:31.01#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.246.08:22:31.01#ibcon#[27=AT02-04\r\n] 2006.246.08:22:31.01#ibcon#*before write, iclass 36, count 2 2006.246.08:22:31.01#ibcon#enter sib2, iclass 36, count 2 2006.246.08:22:31.01#ibcon#flushed, iclass 36, count 2 2006.246.08:22:31.01#ibcon#about to write, iclass 36, count 2 2006.246.08:22:31.01#ibcon#wrote, iclass 36, count 2 2006.246.08:22:31.01#ibcon#about to read 3, iclass 36, count 2 2006.246.08:22:31.04#ibcon#read 3, iclass 36, count 2 2006.246.08:22:31.04#ibcon#about to read 4, iclass 36, count 2 2006.246.08:22:31.04#ibcon#read 4, iclass 36, count 2 2006.246.08:22:31.04#ibcon#about to read 5, iclass 36, count 2 2006.246.08:22:31.04#ibcon#read 5, iclass 36, count 2 2006.246.08:22:31.04#ibcon#about to read 6, iclass 36, count 2 2006.246.08:22:31.04#ibcon#read 6, iclass 36, count 2 2006.246.08:22:31.04#ibcon#end of sib2, iclass 36, count 2 2006.246.08:22:31.04#ibcon#*after write, iclass 36, count 2 2006.246.08:22:31.04#ibcon#*before return 0, iclass 36, count 2 2006.246.08:22:31.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:31.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.246.08:22:31.04#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.246.08:22:31.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:31.04#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:31.16#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:31.16#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:31.16#ibcon#enter wrdev, iclass 36, count 0 2006.246.08:22:31.16#ibcon#first serial, iclass 36, count 0 2006.246.08:22:31.16#ibcon#enter sib2, iclass 36, count 0 2006.246.08:22:31.16#ibcon#flushed, iclass 36, count 0 2006.246.08:22:31.16#ibcon#about to write, iclass 36, count 0 2006.246.08:22:31.16#ibcon#wrote, iclass 36, count 0 2006.246.08:22:31.16#ibcon#about to read 3, iclass 36, count 0 2006.246.08:22:31.18#ibcon#read 3, iclass 36, count 0 2006.246.08:22:31.18#ibcon#about to read 4, iclass 36, count 0 2006.246.08:22:31.18#ibcon#read 4, iclass 36, count 0 2006.246.08:22:31.18#ibcon#about to read 5, iclass 36, count 0 2006.246.08:22:31.18#ibcon#read 5, iclass 36, count 0 2006.246.08:22:31.18#ibcon#about to read 6, iclass 36, count 0 2006.246.08:22:31.18#ibcon#read 6, iclass 36, count 0 2006.246.08:22:31.18#ibcon#end of sib2, iclass 36, count 0 2006.246.08:22:31.18#ibcon#*mode == 0, iclass 36, count 0 2006.246.08:22:31.18#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.246.08:22:31.18#ibcon#[27=USB\r\n] 2006.246.08:22:31.18#ibcon#*before write, iclass 36, count 0 2006.246.08:22:31.18#ibcon#enter sib2, iclass 36, count 0 2006.246.08:22:31.18#ibcon#flushed, iclass 36, count 0 2006.246.08:22:31.18#ibcon#about to write, iclass 36, count 0 2006.246.08:22:31.18#ibcon#wrote, iclass 36, count 0 2006.246.08:22:31.18#ibcon#about to read 3, iclass 36, count 0 2006.246.08:22:31.21#ibcon#read 3, iclass 36, count 0 2006.246.08:22:31.21#ibcon#about to read 4, iclass 36, count 0 2006.246.08:22:31.21#ibcon#read 4, iclass 36, count 0 2006.246.08:22:31.21#ibcon#about to read 5, iclass 36, count 0 2006.246.08:22:31.21#ibcon#read 5, iclass 36, count 0 2006.246.08:22:31.21#ibcon#about to read 6, iclass 36, count 0 2006.246.08:22:31.21#ibcon#read 6, iclass 36, count 0 2006.246.08:22:31.21#ibcon#end of sib2, iclass 36, count 0 2006.246.08:22:31.21#ibcon#*after write, iclass 36, count 0 2006.246.08:22:31.21#ibcon#*before return 0, iclass 36, count 0 2006.246.08:22:31.21#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:31.21#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.246.08:22:31.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.246.08:22:31.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.246.08:22:31.21$vc4f8/vblo=3,656.99 2006.246.08:22:31.21#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.246.08:22:31.21#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.246.08:22:31.21#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:31.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:31.21#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:31.21#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:31.21#ibcon#enter wrdev, iclass 38, count 0 2006.246.08:22:31.21#ibcon#first serial, iclass 38, count 0 2006.246.08:22:31.21#ibcon#enter sib2, iclass 38, count 0 2006.246.08:22:31.21#ibcon#flushed, iclass 38, count 0 2006.246.08:22:31.21#ibcon#about to write, iclass 38, count 0 2006.246.08:22:31.21#ibcon#wrote, iclass 38, count 0 2006.246.08:22:31.21#ibcon#about to read 3, iclass 38, count 0 2006.246.08:22:31.23#ibcon#read 3, iclass 38, count 0 2006.246.08:22:31.23#ibcon#about to read 4, iclass 38, count 0 2006.246.08:22:31.23#ibcon#read 4, iclass 38, count 0 2006.246.08:22:31.23#ibcon#about to read 5, iclass 38, count 0 2006.246.08:22:31.23#ibcon#read 5, iclass 38, count 0 2006.246.08:22:31.23#ibcon#about to read 6, iclass 38, count 0 2006.246.08:22:31.23#ibcon#read 6, iclass 38, count 0 2006.246.08:22:31.23#ibcon#end of sib2, iclass 38, count 0 2006.246.08:22:31.23#ibcon#*mode == 0, iclass 38, count 0 2006.246.08:22:31.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.246.08:22:31.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:22:31.23#ibcon#*before write, iclass 38, count 0 2006.246.08:22:31.23#ibcon#enter sib2, iclass 38, count 0 2006.246.08:22:31.23#ibcon#flushed, iclass 38, count 0 2006.246.08:22:31.23#ibcon#about to write, iclass 38, count 0 2006.246.08:22:31.23#ibcon#wrote, iclass 38, count 0 2006.246.08:22:31.23#ibcon#about to read 3, iclass 38, count 0 2006.246.08:22:31.27#ibcon#read 3, iclass 38, count 0 2006.246.08:22:31.27#ibcon#about to read 4, iclass 38, count 0 2006.246.08:22:31.27#ibcon#read 4, iclass 38, count 0 2006.246.08:22:31.27#ibcon#about to read 5, iclass 38, count 0 2006.246.08:22:31.27#ibcon#read 5, iclass 38, count 0 2006.246.08:22:31.27#ibcon#about to read 6, iclass 38, count 0 2006.246.08:22:31.27#ibcon#read 6, iclass 38, count 0 2006.246.08:22:31.27#ibcon#end of sib2, iclass 38, count 0 2006.246.08:22:31.27#ibcon#*after write, iclass 38, count 0 2006.246.08:22:31.27#ibcon#*before return 0, iclass 38, count 0 2006.246.08:22:31.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:31.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.246.08:22:31.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.246.08:22:31.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.246.08:22:31.27$vc4f8/vb=3,4 2006.246.08:22:31.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.246.08:22:31.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.246.08:22:31.27#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:31.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:31.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:31.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:31.33#ibcon#enter wrdev, iclass 40, count 2 2006.246.08:22:31.33#ibcon#first serial, iclass 40, count 2 2006.246.08:22:31.33#ibcon#enter sib2, iclass 40, count 2 2006.246.08:22:31.33#ibcon#flushed, iclass 40, count 2 2006.246.08:22:31.33#ibcon#about to write, iclass 40, count 2 2006.246.08:22:31.33#ibcon#wrote, iclass 40, count 2 2006.246.08:22:31.33#ibcon#about to read 3, iclass 40, count 2 2006.246.08:22:31.35#ibcon#read 3, iclass 40, count 2 2006.246.08:22:31.35#ibcon#about to read 4, iclass 40, count 2 2006.246.08:22:31.35#ibcon#read 4, iclass 40, count 2 2006.246.08:22:31.35#ibcon#about to read 5, iclass 40, count 2 2006.246.08:22:31.35#ibcon#read 5, iclass 40, count 2 2006.246.08:22:31.35#ibcon#about to read 6, iclass 40, count 2 2006.246.08:22:31.35#ibcon#read 6, iclass 40, count 2 2006.246.08:22:31.35#ibcon#end of sib2, iclass 40, count 2 2006.246.08:22:31.35#ibcon#*mode == 0, iclass 40, count 2 2006.246.08:22:31.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.246.08:22:31.35#ibcon#[27=AT03-04\r\n] 2006.246.08:22:31.35#ibcon#*before write, iclass 40, count 2 2006.246.08:22:31.35#ibcon#enter sib2, iclass 40, count 2 2006.246.08:22:31.35#ibcon#flushed, iclass 40, count 2 2006.246.08:22:31.35#ibcon#about to write, iclass 40, count 2 2006.246.08:22:31.35#ibcon#wrote, iclass 40, count 2 2006.246.08:22:31.35#ibcon#about to read 3, iclass 40, count 2 2006.246.08:22:31.38#ibcon#read 3, iclass 40, count 2 2006.246.08:22:31.38#ibcon#about to read 4, iclass 40, count 2 2006.246.08:22:31.38#ibcon#read 4, iclass 40, count 2 2006.246.08:22:31.38#ibcon#about to read 5, iclass 40, count 2 2006.246.08:22:31.38#ibcon#read 5, iclass 40, count 2 2006.246.08:22:31.38#ibcon#about to read 6, iclass 40, count 2 2006.246.08:22:31.38#ibcon#read 6, iclass 40, count 2 2006.246.08:22:31.38#ibcon#end of sib2, iclass 40, count 2 2006.246.08:22:31.38#ibcon#*after write, iclass 40, count 2 2006.246.08:22:31.38#ibcon#*before return 0, iclass 40, count 2 2006.246.08:22:31.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:31.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.246.08:22:31.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.246.08:22:31.38#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:31.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:31.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:31.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:31.50#ibcon#enter wrdev, iclass 40, count 0 2006.246.08:22:31.50#ibcon#first serial, iclass 40, count 0 2006.246.08:22:31.50#ibcon#enter sib2, iclass 40, count 0 2006.246.08:22:31.50#ibcon#flushed, iclass 40, count 0 2006.246.08:22:31.50#ibcon#about to write, iclass 40, count 0 2006.246.08:22:31.50#ibcon#wrote, iclass 40, count 0 2006.246.08:22:31.50#ibcon#about to read 3, iclass 40, count 0 2006.246.08:22:31.52#ibcon#read 3, iclass 40, count 0 2006.246.08:22:31.52#ibcon#about to read 4, iclass 40, count 0 2006.246.08:22:31.52#ibcon#read 4, iclass 40, count 0 2006.246.08:22:31.52#ibcon#about to read 5, iclass 40, count 0 2006.246.08:22:31.52#ibcon#read 5, iclass 40, count 0 2006.246.08:22:31.52#ibcon#about to read 6, iclass 40, count 0 2006.246.08:22:31.52#ibcon#read 6, iclass 40, count 0 2006.246.08:22:31.52#ibcon#end of sib2, iclass 40, count 0 2006.246.08:22:31.52#ibcon#*mode == 0, iclass 40, count 0 2006.246.08:22:31.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.246.08:22:31.52#ibcon#[27=USB\r\n] 2006.246.08:22:31.52#ibcon#*before write, iclass 40, count 0 2006.246.08:22:31.52#ibcon#enter sib2, iclass 40, count 0 2006.246.08:22:31.52#ibcon#flushed, iclass 40, count 0 2006.246.08:22:31.52#ibcon#about to write, iclass 40, count 0 2006.246.08:22:31.52#ibcon#wrote, iclass 40, count 0 2006.246.08:22:31.52#ibcon#about to read 3, iclass 40, count 0 2006.246.08:22:31.55#ibcon#read 3, iclass 40, count 0 2006.246.08:22:31.55#ibcon#about to read 4, iclass 40, count 0 2006.246.08:22:31.55#ibcon#read 4, iclass 40, count 0 2006.246.08:22:31.55#ibcon#about to read 5, iclass 40, count 0 2006.246.08:22:31.55#ibcon#read 5, iclass 40, count 0 2006.246.08:22:31.55#ibcon#about to read 6, iclass 40, count 0 2006.246.08:22:31.55#ibcon#read 6, iclass 40, count 0 2006.246.08:22:31.55#ibcon#end of sib2, iclass 40, count 0 2006.246.08:22:31.55#ibcon#*after write, iclass 40, count 0 2006.246.08:22:31.55#ibcon#*before return 0, iclass 40, count 0 2006.246.08:22:31.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:31.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.246.08:22:31.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.246.08:22:31.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.246.08:22:31.55$vc4f8/vblo=4,712.99 2006.246.08:22:31.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.246.08:22:31.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.246.08:22:31.55#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:31.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:31.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:31.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:31.55#ibcon#enter wrdev, iclass 4, count 0 2006.246.08:22:31.55#ibcon#first serial, iclass 4, count 0 2006.246.08:22:31.55#ibcon#enter sib2, iclass 4, count 0 2006.246.08:22:31.55#ibcon#flushed, iclass 4, count 0 2006.246.08:22:31.55#ibcon#about to write, iclass 4, count 0 2006.246.08:22:31.55#ibcon#wrote, iclass 4, count 0 2006.246.08:22:31.55#ibcon#about to read 3, iclass 4, count 0 2006.246.08:22:31.57#ibcon#read 3, iclass 4, count 0 2006.246.08:22:31.57#ibcon#about to read 4, iclass 4, count 0 2006.246.08:22:31.57#ibcon#read 4, iclass 4, count 0 2006.246.08:22:31.57#ibcon#about to read 5, iclass 4, count 0 2006.246.08:22:31.57#ibcon#read 5, iclass 4, count 0 2006.246.08:22:31.57#ibcon#about to read 6, iclass 4, count 0 2006.246.08:22:31.57#ibcon#read 6, iclass 4, count 0 2006.246.08:22:31.57#ibcon#end of sib2, iclass 4, count 0 2006.246.08:22:31.57#ibcon#*mode == 0, iclass 4, count 0 2006.246.08:22:31.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.246.08:22:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:22:31.57#ibcon#*before write, iclass 4, count 0 2006.246.08:22:31.57#ibcon#enter sib2, iclass 4, count 0 2006.246.08:22:31.57#ibcon#flushed, iclass 4, count 0 2006.246.08:22:31.57#ibcon#about to write, iclass 4, count 0 2006.246.08:22:31.57#ibcon#wrote, iclass 4, count 0 2006.246.08:22:31.57#ibcon#about to read 3, iclass 4, count 0 2006.246.08:22:31.61#ibcon#read 3, iclass 4, count 0 2006.246.08:22:31.61#ibcon#about to read 4, iclass 4, count 0 2006.246.08:22:31.61#ibcon#read 4, iclass 4, count 0 2006.246.08:22:31.61#ibcon#about to read 5, iclass 4, count 0 2006.246.08:22:31.61#ibcon#read 5, iclass 4, count 0 2006.246.08:22:31.61#ibcon#about to read 6, iclass 4, count 0 2006.246.08:22:31.61#ibcon#read 6, iclass 4, count 0 2006.246.08:22:31.61#ibcon#end of sib2, iclass 4, count 0 2006.246.08:22:31.61#ibcon#*after write, iclass 4, count 0 2006.246.08:22:31.61#ibcon#*before return 0, iclass 4, count 0 2006.246.08:22:31.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:31.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.246.08:22:31.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.246.08:22:31.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.246.08:22:31.61$vc4f8/vb=4,4 2006.246.08:22:31.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.246.08:22:31.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.246.08:22:31.61#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:31.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:31.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:31.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:31.67#ibcon#enter wrdev, iclass 6, count 2 2006.246.08:22:31.67#ibcon#first serial, iclass 6, count 2 2006.246.08:22:31.67#ibcon#enter sib2, iclass 6, count 2 2006.246.08:22:31.67#ibcon#flushed, iclass 6, count 2 2006.246.08:22:31.67#ibcon#about to write, iclass 6, count 2 2006.246.08:22:31.67#ibcon#wrote, iclass 6, count 2 2006.246.08:22:31.67#ibcon#about to read 3, iclass 6, count 2 2006.246.08:22:31.69#ibcon#read 3, iclass 6, count 2 2006.246.08:22:31.69#ibcon#about to read 4, iclass 6, count 2 2006.246.08:22:31.69#ibcon#read 4, iclass 6, count 2 2006.246.08:22:31.69#ibcon#about to read 5, iclass 6, count 2 2006.246.08:22:31.69#ibcon#read 5, iclass 6, count 2 2006.246.08:22:31.69#ibcon#about to read 6, iclass 6, count 2 2006.246.08:22:31.69#ibcon#read 6, iclass 6, count 2 2006.246.08:22:31.69#ibcon#end of sib2, iclass 6, count 2 2006.246.08:22:31.69#ibcon#*mode == 0, iclass 6, count 2 2006.246.08:22:31.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.246.08:22:31.69#ibcon#[27=AT04-04\r\n] 2006.246.08:22:31.69#ibcon#*before write, iclass 6, count 2 2006.246.08:22:31.69#ibcon#enter sib2, iclass 6, count 2 2006.246.08:22:31.69#ibcon#flushed, iclass 6, count 2 2006.246.08:22:31.69#ibcon#about to write, iclass 6, count 2 2006.246.08:22:31.69#ibcon#wrote, iclass 6, count 2 2006.246.08:22:31.69#ibcon#about to read 3, iclass 6, count 2 2006.246.08:22:31.72#ibcon#read 3, iclass 6, count 2 2006.246.08:22:31.72#ibcon#about to read 4, iclass 6, count 2 2006.246.08:22:31.72#ibcon#read 4, iclass 6, count 2 2006.246.08:22:31.72#ibcon#about to read 5, iclass 6, count 2 2006.246.08:22:31.72#ibcon#read 5, iclass 6, count 2 2006.246.08:22:31.72#ibcon#about to read 6, iclass 6, count 2 2006.246.08:22:31.72#ibcon#read 6, iclass 6, count 2 2006.246.08:22:31.72#ibcon#end of sib2, iclass 6, count 2 2006.246.08:22:31.72#ibcon#*after write, iclass 6, count 2 2006.246.08:22:31.72#ibcon#*before return 0, iclass 6, count 2 2006.246.08:22:31.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:31.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.246.08:22:31.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.246.08:22:31.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:31.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:31.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:31.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:31.84#ibcon#enter wrdev, iclass 6, count 0 2006.246.08:22:31.84#ibcon#first serial, iclass 6, count 0 2006.246.08:22:31.84#ibcon#enter sib2, iclass 6, count 0 2006.246.08:22:31.84#ibcon#flushed, iclass 6, count 0 2006.246.08:22:31.84#ibcon#about to write, iclass 6, count 0 2006.246.08:22:31.84#ibcon#wrote, iclass 6, count 0 2006.246.08:22:31.84#ibcon#about to read 3, iclass 6, count 0 2006.246.08:22:31.86#ibcon#read 3, iclass 6, count 0 2006.246.08:22:31.86#ibcon#about to read 4, iclass 6, count 0 2006.246.08:22:31.86#ibcon#read 4, iclass 6, count 0 2006.246.08:22:31.86#ibcon#about to read 5, iclass 6, count 0 2006.246.08:22:31.86#ibcon#read 5, iclass 6, count 0 2006.246.08:22:31.86#ibcon#about to read 6, iclass 6, count 0 2006.246.08:22:31.86#ibcon#read 6, iclass 6, count 0 2006.246.08:22:31.86#ibcon#end of sib2, iclass 6, count 0 2006.246.08:22:31.86#ibcon#*mode == 0, iclass 6, count 0 2006.246.08:22:31.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.246.08:22:31.86#ibcon#[27=USB\r\n] 2006.246.08:22:31.86#ibcon#*before write, iclass 6, count 0 2006.246.08:22:31.86#ibcon#enter sib2, iclass 6, count 0 2006.246.08:22:31.86#ibcon#flushed, iclass 6, count 0 2006.246.08:22:31.86#ibcon#about to write, iclass 6, count 0 2006.246.08:22:31.86#ibcon#wrote, iclass 6, count 0 2006.246.08:22:31.86#ibcon#about to read 3, iclass 6, count 0 2006.246.08:22:31.89#ibcon#read 3, iclass 6, count 0 2006.246.08:22:31.89#ibcon#about to read 4, iclass 6, count 0 2006.246.08:22:31.89#ibcon#read 4, iclass 6, count 0 2006.246.08:22:31.89#ibcon#about to read 5, iclass 6, count 0 2006.246.08:22:31.89#ibcon#read 5, iclass 6, count 0 2006.246.08:22:31.89#ibcon#about to read 6, iclass 6, count 0 2006.246.08:22:31.89#ibcon#read 6, iclass 6, count 0 2006.246.08:22:31.89#ibcon#end of sib2, iclass 6, count 0 2006.246.08:22:31.89#ibcon#*after write, iclass 6, count 0 2006.246.08:22:31.89#ibcon#*before return 0, iclass 6, count 0 2006.246.08:22:31.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:31.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.246.08:22:31.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.246.08:22:31.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.246.08:22:31.89$vc4f8/vblo=5,744.99 2006.246.08:22:31.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.246.08:22:31.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.246.08:22:31.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:31.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:31.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:31.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:31.89#ibcon#enter wrdev, iclass 10, count 0 2006.246.08:22:31.89#ibcon#first serial, iclass 10, count 0 2006.246.08:22:31.89#ibcon#enter sib2, iclass 10, count 0 2006.246.08:22:31.89#ibcon#flushed, iclass 10, count 0 2006.246.08:22:31.89#ibcon#about to write, iclass 10, count 0 2006.246.08:22:31.89#ibcon#wrote, iclass 10, count 0 2006.246.08:22:31.89#ibcon#about to read 3, iclass 10, count 0 2006.246.08:22:31.91#ibcon#read 3, iclass 10, count 0 2006.246.08:22:31.91#ibcon#about to read 4, iclass 10, count 0 2006.246.08:22:31.91#ibcon#read 4, iclass 10, count 0 2006.246.08:22:31.91#ibcon#about to read 5, iclass 10, count 0 2006.246.08:22:31.91#ibcon#read 5, iclass 10, count 0 2006.246.08:22:31.91#ibcon#about to read 6, iclass 10, count 0 2006.246.08:22:31.91#ibcon#read 6, iclass 10, count 0 2006.246.08:22:31.91#ibcon#end of sib2, iclass 10, count 0 2006.246.08:22:31.91#ibcon#*mode == 0, iclass 10, count 0 2006.246.08:22:31.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.246.08:22:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:22:31.91#ibcon#*before write, iclass 10, count 0 2006.246.08:22:31.91#ibcon#enter sib2, iclass 10, count 0 2006.246.08:22:31.91#ibcon#flushed, iclass 10, count 0 2006.246.08:22:31.91#ibcon#about to write, iclass 10, count 0 2006.246.08:22:31.91#ibcon#wrote, iclass 10, count 0 2006.246.08:22:31.91#ibcon#about to read 3, iclass 10, count 0 2006.246.08:22:31.95#ibcon#read 3, iclass 10, count 0 2006.246.08:22:31.95#ibcon#about to read 4, iclass 10, count 0 2006.246.08:22:31.95#ibcon#read 4, iclass 10, count 0 2006.246.08:22:31.95#ibcon#about to read 5, iclass 10, count 0 2006.246.08:22:31.95#ibcon#read 5, iclass 10, count 0 2006.246.08:22:31.95#ibcon#about to read 6, iclass 10, count 0 2006.246.08:22:31.95#ibcon#read 6, iclass 10, count 0 2006.246.08:22:31.95#ibcon#end of sib2, iclass 10, count 0 2006.246.08:22:31.95#ibcon#*after write, iclass 10, count 0 2006.246.08:22:31.95#ibcon#*before return 0, iclass 10, count 0 2006.246.08:22:31.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:31.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.246.08:22:31.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.246.08:22:31.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.246.08:22:31.95$vc4f8/vb=5,3 2006.246.08:22:31.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.246.08:22:31.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.246.08:22:31.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:31.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:32.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:32.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:32.02#ibcon#enter wrdev, iclass 12, count 2 2006.246.08:22:32.02#ibcon#first serial, iclass 12, count 2 2006.246.08:22:32.02#ibcon#enter sib2, iclass 12, count 2 2006.246.08:22:32.02#ibcon#flushed, iclass 12, count 2 2006.246.08:22:32.02#ibcon#about to write, iclass 12, count 2 2006.246.08:22:32.02#ibcon#wrote, iclass 12, count 2 2006.246.08:22:32.02#ibcon#about to read 3, iclass 12, count 2 2006.246.08:22:32.03#ibcon#read 3, iclass 12, count 2 2006.246.08:22:32.04#ibcon#about to read 4, iclass 12, count 2 2006.246.08:22:32.04#ibcon#read 4, iclass 12, count 2 2006.246.08:22:32.04#ibcon#about to read 5, iclass 12, count 2 2006.246.08:22:32.04#ibcon#read 5, iclass 12, count 2 2006.246.08:22:32.04#ibcon#about to read 6, iclass 12, count 2 2006.246.08:22:32.04#ibcon#read 6, iclass 12, count 2 2006.246.08:22:32.04#ibcon#end of sib2, iclass 12, count 2 2006.246.08:22:32.04#ibcon#*mode == 0, iclass 12, count 2 2006.246.08:22:32.04#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.246.08:22:32.04#ibcon#[27=AT05-03\r\n] 2006.246.08:22:32.04#ibcon#*before write, iclass 12, count 2 2006.246.08:22:32.04#ibcon#enter sib2, iclass 12, count 2 2006.246.08:22:32.04#ibcon#flushed, iclass 12, count 2 2006.246.08:22:32.04#ibcon#about to write, iclass 12, count 2 2006.246.08:22:32.04#ibcon#wrote, iclass 12, count 2 2006.246.08:22:32.04#ibcon#about to read 3, iclass 12, count 2 2006.246.08:22:32.04#abcon#<5=/05 3.7 6.7 26.22 771005.7\r\n> 2006.246.08:22:32.06#abcon#{5=INTERFACE CLEAR} 2006.246.08:22:32.06#ibcon#read 3, iclass 12, count 2 2006.246.08:22:32.06#ibcon#about to read 4, iclass 12, count 2 2006.246.08:22:32.06#ibcon#read 4, iclass 12, count 2 2006.246.08:22:32.06#ibcon#about to read 5, iclass 12, count 2 2006.246.08:22:32.06#ibcon#read 5, iclass 12, count 2 2006.246.08:22:32.06#ibcon#about to read 6, iclass 12, count 2 2006.246.08:22:32.06#ibcon#read 6, iclass 12, count 2 2006.246.08:22:32.06#ibcon#end of sib2, iclass 12, count 2 2006.246.08:22:32.06#ibcon#*after write, iclass 12, count 2 2006.246.08:22:32.06#ibcon#*before return 0, iclass 12, count 2 2006.246.08:22:32.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:32.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.246.08:22:32.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.246.08:22:32.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:32.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:32.12#abcon#[5=S1D000X0/0*\r\n] 2006.246.08:22:32.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:32.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:32.18#ibcon#enter wrdev, iclass 12, count 0 2006.246.08:22:32.18#ibcon#first serial, iclass 12, count 0 2006.246.08:22:32.18#ibcon#enter sib2, iclass 12, count 0 2006.246.08:22:32.18#ibcon#flushed, iclass 12, count 0 2006.246.08:22:32.18#ibcon#about to write, iclass 12, count 0 2006.246.08:22:32.18#ibcon#wrote, iclass 12, count 0 2006.246.08:22:32.18#ibcon#about to read 3, iclass 12, count 0 2006.246.08:22:32.20#ibcon#read 3, iclass 12, count 0 2006.246.08:22:32.20#ibcon#about to read 4, iclass 12, count 0 2006.246.08:22:32.20#ibcon#read 4, iclass 12, count 0 2006.246.08:22:32.20#ibcon#about to read 5, iclass 12, count 0 2006.246.08:22:32.20#ibcon#read 5, iclass 12, count 0 2006.246.08:22:32.20#ibcon#about to read 6, iclass 12, count 0 2006.246.08:22:32.20#ibcon#read 6, iclass 12, count 0 2006.246.08:22:32.20#ibcon#end of sib2, iclass 12, count 0 2006.246.08:22:32.20#ibcon#*mode == 0, iclass 12, count 0 2006.246.08:22:32.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.246.08:22:32.20#ibcon#[27=USB\r\n] 2006.246.08:22:32.20#ibcon#*before write, iclass 12, count 0 2006.246.08:22:32.20#ibcon#enter sib2, iclass 12, count 0 2006.246.08:22:32.20#ibcon#flushed, iclass 12, count 0 2006.246.08:22:32.20#ibcon#about to write, iclass 12, count 0 2006.246.08:22:32.20#ibcon#wrote, iclass 12, count 0 2006.246.08:22:32.20#ibcon#about to read 3, iclass 12, count 0 2006.246.08:22:32.23#ibcon#read 3, iclass 12, count 0 2006.246.08:22:32.23#ibcon#about to read 4, iclass 12, count 0 2006.246.08:22:32.23#ibcon#read 4, iclass 12, count 0 2006.246.08:22:32.23#ibcon#about to read 5, iclass 12, count 0 2006.246.08:22:32.23#ibcon#read 5, iclass 12, count 0 2006.246.08:22:32.23#ibcon#about to read 6, iclass 12, count 0 2006.246.08:22:32.23#ibcon#read 6, iclass 12, count 0 2006.246.08:22:32.23#ibcon#end of sib2, iclass 12, count 0 2006.246.08:22:32.23#ibcon#*after write, iclass 12, count 0 2006.246.08:22:32.23#ibcon#*before return 0, iclass 12, count 0 2006.246.08:22:32.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:32.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.246.08:22:32.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.246.08:22:32.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.246.08:22:32.23$vc4f8/vblo=6,752.99 2006.246.08:22:32.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.246.08:22:32.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.246.08:22:32.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:22:32.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:32.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:32.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:32.23#ibcon#enter wrdev, iclass 18, count 0 2006.246.08:22:32.23#ibcon#first serial, iclass 18, count 0 2006.246.08:22:32.23#ibcon#enter sib2, iclass 18, count 0 2006.246.08:22:32.23#ibcon#flushed, iclass 18, count 0 2006.246.08:22:32.23#ibcon#about to write, iclass 18, count 0 2006.246.08:22:32.23#ibcon#wrote, iclass 18, count 0 2006.246.08:22:32.23#ibcon#about to read 3, iclass 18, count 0 2006.246.08:22:32.25#ibcon#read 3, iclass 18, count 0 2006.246.08:22:32.25#ibcon#about to read 4, iclass 18, count 0 2006.246.08:22:32.25#ibcon#read 4, iclass 18, count 0 2006.246.08:22:32.25#ibcon#about to read 5, iclass 18, count 0 2006.246.08:22:32.25#ibcon#read 5, iclass 18, count 0 2006.246.08:22:32.25#ibcon#about to read 6, iclass 18, count 0 2006.246.08:22:32.25#ibcon#read 6, iclass 18, count 0 2006.246.08:22:32.25#ibcon#end of sib2, iclass 18, count 0 2006.246.08:22:32.25#ibcon#*mode == 0, iclass 18, count 0 2006.246.08:22:32.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.246.08:22:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:22:32.25#ibcon#*before write, iclass 18, count 0 2006.246.08:22:32.25#ibcon#enter sib2, iclass 18, count 0 2006.246.08:22:32.25#ibcon#flushed, iclass 18, count 0 2006.246.08:22:32.25#ibcon#about to write, iclass 18, count 0 2006.246.08:22:32.25#ibcon#wrote, iclass 18, count 0 2006.246.08:22:32.25#ibcon#about to read 3, iclass 18, count 0 2006.246.08:22:32.29#ibcon#read 3, iclass 18, count 0 2006.246.08:22:32.29#ibcon#about to read 4, iclass 18, count 0 2006.246.08:22:32.29#ibcon#read 4, iclass 18, count 0 2006.246.08:22:32.29#ibcon#about to read 5, iclass 18, count 0 2006.246.08:22:32.29#ibcon#read 5, iclass 18, count 0 2006.246.08:22:32.29#ibcon#about to read 6, iclass 18, count 0 2006.246.08:22:32.29#ibcon#read 6, iclass 18, count 0 2006.246.08:22:32.29#ibcon#end of sib2, iclass 18, count 0 2006.246.08:22:32.29#ibcon#*after write, iclass 18, count 0 2006.246.08:22:32.29#ibcon#*before return 0, iclass 18, count 0 2006.246.08:22:32.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:32.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.246.08:22:32.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.246.08:22:32.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.246.08:22:32.29$vc4f8/vb=6,3 2006.246.08:22:32.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.246.08:22:32.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.246.08:22:32.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:22:32.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:32.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:32.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:32.35#ibcon#enter wrdev, iclass 20, count 2 2006.246.08:22:32.35#ibcon#first serial, iclass 20, count 2 2006.246.08:22:32.35#ibcon#enter sib2, iclass 20, count 2 2006.246.08:22:32.35#ibcon#flushed, iclass 20, count 2 2006.246.08:22:32.35#ibcon#about to write, iclass 20, count 2 2006.246.08:22:32.35#ibcon#wrote, iclass 20, count 2 2006.246.08:22:32.35#ibcon#about to read 3, iclass 20, count 2 2006.246.08:22:32.37#ibcon#read 3, iclass 20, count 2 2006.246.08:22:32.37#ibcon#about to read 4, iclass 20, count 2 2006.246.08:22:32.37#ibcon#read 4, iclass 20, count 2 2006.246.08:22:32.37#ibcon#about to read 5, iclass 20, count 2 2006.246.08:22:32.37#ibcon#read 5, iclass 20, count 2 2006.246.08:22:32.37#ibcon#about to read 6, iclass 20, count 2 2006.246.08:22:32.37#ibcon#read 6, iclass 20, count 2 2006.246.08:22:32.37#ibcon#end of sib2, iclass 20, count 2 2006.246.08:22:32.37#ibcon#*mode == 0, iclass 20, count 2 2006.246.08:22:32.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.246.08:22:32.37#ibcon#[27=AT06-03\r\n] 2006.246.08:22:32.37#ibcon#*before write, iclass 20, count 2 2006.246.08:22:32.37#ibcon#enter sib2, iclass 20, count 2 2006.246.08:22:32.37#ibcon#flushed, iclass 20, count 2 2006.246.08:22:32.37#ibcon#about to write, iclass 20, count 2 2006.246.08:22:32.37#ibcon#wrote, iclass 20, count 2 2006.246.08:22:32.37#ibcon#about to read 3, iclass 20, count 2 2006.246.08:22:32.40#ibcon#read 3, iclass 20, count 2 2006.246.08:22:32.40#ibcon#about to read 4, iclass 20, count 2 2006.246.08:22:32.40#ibcon#read 4, iclass 20, count 2 2006.246.08:22:32.40#ibcon#about to read 5, iclass 20, count 2 2006.246.08:22:32.40#ibcon#read 5, iclass 20, count 2 2006.246.08:22:32.40#ibcon#about to read 6, iclass 20, count 2 2006.246.08:22:32.40#ibcon#read 6, iclass 20, count 2 2006.246.08:22:32.40#ibcon#end of sib2, iclass 20, count 2 2006.246.08:22:32.40#ibcon#*after write, iclass 20, count 2 2006.246.08:22:32.40#ibcon#*before return 0, iclass 20, count 2 2006.246.08:22:32.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:32.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.246.08:22:32.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.246.08:22:32.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:22:32.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:32.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:32.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:32.52#ibcon#enter wrdev, iclass 20, count 0 2006.246.08:22:32.52#ibcon#first serial, iclass 20, count 0 2006.246.08:22:32.52#ibcon#enter sib2, iclass 20, count 0 2006.246.08:22:32.52#ibcon#flushed, iclass 20, count 0 2006.246.08:22:32.52#ibcon#about to write, iclass 20, count 0 2006.246.08:22:32.52#ibcon#wrote, iclass 20, count 0 2006.246.08:22:32.52#ibcon#about to read 3, iclass 20, count 0 2006.246.08:22:32.54#ibcon#read 3, iclass 20, count 0 2006.246.08:22:32.54#ibcon#about to read 4, iclass 20, count 0 2006.246.08:22:32.54#ibcon#read 4, iclass 20, count 0 2006.246.08:22:32.54#ibcon#about to read 5, iclass 20, count 0 2006.246.08:22:32.54#ibcon#read 5, iclass 20, count 0 2006.246.08:22:32.54#ibcon#about to read 6, iclass 20, count 0 2006.246.08:22:32.54#ibcon#read 6, iclass 20, count 0 2006.246.08:22:32.54#ibcon#end of sib2, iclass 20, count 0 2006.246.08:22:32.54#ibcon#*mode == 0, iclass 20, count 0 2006.246.08:22:32.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.246.08:22:32.54#ibcon#[27=USB\r\n] 2006.246.08:22:32.54#ibcon#*before write, iclass 20, count 0 2006.246.08:22:32.54#ibcon#enter sib2, iclass 20, count 0 2006.246.08:22:32.54#ibcon#flushed, iclass 20, count 0 2006.246.08:22:32.54#ibcon#about to write, iclass 20, count 0 2006.246.08:22:32.54#ibcon#wrote, iclass 20, count 0 2006.246.08:22:32.54#ibcon#about to read 3, iclass 20, count 0 2006.246.08:22:32.57#ibcon#read 3, iclass 20, count 0 2006.246.08:22:32.57#ibcon#about to read 4, iclass 20, count 0 2006.246.08:22:32.57#ibcon#read 4, iclass 20, count 0 2006.246.08:22:32.57#ibcon#about to read 5, iclass 20, count 0 2006.246.08:22:32.57#ibcon#read 5, iclass 20, count 0 2006.246.08:22:32.57#ibcon#about to read 6, iclass 20, count 0 2006.246.08:22:32.57#ibcon#read 6, iclass 20, count 0 2006.246.08:22:32.57#ibcon#end of sib2, iclass 20, count 0 2006.246.08:22:32.57#ibcon#*after write, iclass 20, count 0 2006.246.08:22:32.57#ibcon#*before return 0, iclass 20, count 0 2006.246.08:22:32.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:32.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.246.08:22:32.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.246.08:22:32.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.246.08:22:32.57$vc4f8/vabw=wide 2006.246.08:22:32.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.246.08:22:32.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.246.08:22:32.57#ibcon#ireg 8 cls_cnt 0 2006.246.08:22:32.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:32.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:32.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:32.57#ibcon#enter wrdev, iclass 22, count 0 2006.246.08:22:32.57#ibcon#first serial, iclass 22, count 0 2006.246.08:22:32.57#ibcon#enter sib2, iclass 22, count 0 2006.246.08:22:32.57#ibcon#flushed, iclass 22, count 0 2006.246.08:22:32.57#ibcon#about to write, iclass 22, count 0 2006.246.08:22:32.57#ibcon#wrote, iclass 22, count 0 2006.246.08:22:32.57#ibcon#about to read 3, iclass 22, count 0 2006.246.08:22:32.59#ibcon#read 3, iclass 22, count 0 2006.246.08:22:32.59#ibcon#about to read 4, iclass 22, count 0 2006.246.08:22:32.59#ibcon#read 4, iclass 22, count 0 2006.246.08:22:32.59#ibcon#about to read 5, iclass 22, count 0 2006.246.08:22:32.59#ibcon#read 5, iclass 22, count 0 2006.246.08:22:32.59#ibcon#about to read 6, iclass 22, count 0 2006.246.08:22:32.59#ibcon#read 6, iclass 22, count 0 2006.246.08:22:32.59#ibcon#end of sib2, iclass 22, count 0 2006.246.08:22:32.59#ibcon#*mode == 0, iclass 22, count 0 2006.246.08:22:32.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.246.08:22:32.59#ibcon#[25=BW32\r\n] 2006.246.08:22:32.59#ibcon#*before write, iclass 22, count 0 2006.246.08:22:32.59#ibcon#enter sib2, iclass 22, count 0 2006.246.08:22:32.59#ibcon#flushed, iclass 22, count 0 2006.246.08:22:32.59#ibcon#about to write, iclass 22, count 0 2006.246.08:22:32.59#ibcon#wrote, iclass 22, count 0 2006.246.08:22:32.59#ibcon#about to read 3, iclass 22, count 0 2006.246.08:22:32.62#ibcon#read 3, iclass 22, count 0 2006.246.08:22:32.62#ibcon#about to read 4, iclass 22, count 0 2006.246.08:22:32.62#ibcon#read 4, iclass 22, count 0 2006.246.08:22:32.62#ibcon#about to read 5, iclass 22, count 0 2006.246.08:22:32.62#ibcon#read 5, iclass 22, count 0 2006.246.08:22:32.62#ibcon#about to read 6, iclass 22, count 0 2006.246.08:22:32.62#ibcon#read 6, iclass 22, count 0 2006.246.08:22:32.62#ibcon#end of sib2, iclass 22, count 0 2006.246.08:22:32.62#ibcon#*after write, iclass 22, count 0 2006.246.08:22:32.62#ibcon#*before return 0, iclass 22, count 0 2006.246.08:22:32.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:32.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.246.08:22:32.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.246.08:22:32.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.246.08:22:32.62$vc4f8/vbbw=wide 2006.246.08:22:32.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.246.08:22:32.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.246.08:22:32.62#ibcon#ireg 8 cls_cnt 0 2006.246.08:22:32.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:22:32.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:22:32.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:22:32.69#ibcon#enter wrdev, iclass 24, count 0 2006.246.08:22:32.69#ibcon#first serial, iclass 24, count 0 2006.246.08:22:32.69#ibcon#enter sib2, iclass 24, count 0 2006.246.08:22:32.69#ibcon#flushed, iclass 24, count 0 2006.246.08:22:32.69#ibcon#about to write, iclass 24, count 0 2006.246.08:22:32.69#ibcon#wrote, iclass 24, count 0 2006.246.08:22:32.69#ibcon#about to read 3, iclass 24, count 0 2006.246.08:22:32.71#ibcon#read 3, iclass 24, count 0 2006.246.08:22:32.71#ibcon#about to read 4, iclass 24, count 0 2006.246.08:22:32.71#ibcon#read 4, iclass 24, count 0 2006.246.08:22:32.71#ibcon#about to read 5, iclass 24, count 0 2006.246.08:22:32.71#ibcon#read 5, iclass 24, count 0 2006.246.08:22:32.71#ibcon#about to read 6, iclass 24, count 0 2006.246.08:22:32.71#ibcon#read 6, iclass 24, count 0 2006.246.08:22:32.71#ibcon#end of sib2, iclass 24, count 0 2006.246.08:22:32.71#ibcon#*mode == 0, iclass 24, count 0 2006.246.08:22:32.71#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.246.08:22:32.71#ibcon#[27=BW32\r\n] 2006.246.08:22:32.71#ibcon#*before write, iclass 24, count 0 2006.246.08:22:32.71#ibcon#enter sib2, iclass 24, count 0 2006.246.08:22:32.71#ibcon#flushed, iclass 24, count 0 2006.246.08:22:32.71#ibcon#about to write, iclass 24, count 0 2006.246.08:22:32.71#ibcon#wrote, iclass 24, count 0 2006.246.08:22:32.71#ibcon#about to read 3, iclass 24, count 0 2006.246.08:22:32.74#ibcon#read 3, iclass 24, count 0 2006.246.08:22:32.74#ibcon#about to read 4, iclass 24, count 0 2006.246.08:22:32.74#ibcon#read 4, iclass 24, count 0 2006.246.08:22:32.74#ibcon#about to read 5, iclass 24, count 0 2006.246.08:22:32.74#ibcon#read 5, iclass 24, count 0 2006.246.08:22:32.74#ibcon#about to read 6, iclass 24, count 0 2006.246.08:22:32.74#ibcon#read 6, iclass 24, count 0 2006.246.08:22:32.74#ibcon#end of sib2, iclass 24, count 0 2006.246.08:22:32.74#ibcon#*after write, iclass 24, count 0 2006.246.08:22:32.74#ibcon#*before return 0, iclass 24, count 0 2006.246.08:22:32.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:22:32.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.246.08:22:32.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.246.08:22:32.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.246.08:22:32.74$4f8m12a/ifd4f 2006.246.08:22:32.74$ifd4f/lo= 2006.246.08:22:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:22:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:22:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:22:32.74$ifd4f/patch= 2006.246.08:22:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:22:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:22:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:22:32.74$4f8m12a/"form=m,16.000,1:2 2006.246.08:22:32.74$4f8m12a/"tpicd 2006.246.08:22:32.74$4f8m12a/echo=off 2006.246.08:22:32.74$4f8m12a/xlog=off 2006.246.08:22:32.74:!2006.246.08:24:40 2006.246.08:22:55.14#trakl#Source acquired 2006.246.08:22:57.14#flagr#flagr/antenna,acquired 2006.246.08:24:40.00:preob 2006.246.08:24:40.14/onsource/TRACKING 2006.246.08:24:40.14:!2006.246.08:24:50 2006.246.08:24:50.00:data_valid=on 2006.246.08:24:50.00:midob 2006.246.08:24:51.14/onsource/TRACKING 2006.246.08:24:51.14/wx/26.18,1005.8,77 2006.246.08:24:51.34/cable/+6.4129E-03 2006.246.08:24:52.43/va/01,08,usb,yes,31,32 2006.246.08:24:52.43/va/02,07,usb,yes,30,32 2006.246.08:24:52.43/va/03,06,usb,yes,32,32 2006.246.08:24:52.43/va/04,07,usb,yes,31,34 2006.246.08:24:52.43/va/05,07,usb,yes,34,36 2006.246.08:24:52.43/va/06,07,usb,yes,29,29 2006.246.08:24:52.43/va/07,07,usb,yes,29,29 2006.246.08:24:52.43/va/08,08,usb,yes,26,25 2006.246.08:24:52.66/valo/01,532.99,yes,locked 2006.246.08:24:52.66/valo/02,572.99,yes,locked 2006.246.08:24:52.66/valo/03,672.99,yes,locked 2006.246.08:24:52.66/valo/04,832.99,yes,locked 2006.246.08:24:52.66/valo/05,652.99,yes,locked 2006.246.08:24:52.66/valo/06,772.99,yes,locked 2006.246.08:24:52.66/valo/07,832.99,yes,locked 2006.246.08:24:52.66/valo/08,852.99,yes,locked 2006.246.08:24:53.75/vb/01,04,usb,yes,30,29 2006.246.08:24:53.75/vb/02,04,usb,yes,32,34 2006.246.08:24:53.75/vb/03,04,usb,yes,28,32 2006.246.08:24:53.75/vb/04,04,usb,yes,29,29 2006.246.08:24:53.75/vb/05,03,usb,yes,35,39 2006.246.08:24:53.75/vb/06,03,usb,yes,35,39 2006.246.08:24:53.75/vb/07,04,usb,yes,31,31 2006.246.08:24:53.75/vb/08,03,usb,yes,35,39 2006.246.08:24:53.99/vblo/01,632.99,yes,locked 2006.246.08:24:53.99/vblo/02,640.99,yes,locked 2006.246.08:24:53.99/vblo/03,656.99,yes,locked 2006.246.08:24:53.99/vblo/04,712.99,yes,locked 2006.246.08:24:53.99/vblo/05,744.99,yes,locked 2006.246.08:24:53.99/vblo/06,752.99,yes,locked 2006.246.08:24:53.99/vblo/07,734.99,yes,locked 2006.246.08:24:53.99/vblo/08,744.99,yes,locked 2006.246.08:24:54.14/vabw/8 2006.246.08:24:54.29/vbbw/8 2006.246.08:24:54.38/xfe/off,on,13.0 2006.246.08:24:54.80/ifatt/23,28,28,28 2006.246.08:24:55.07/fmout-gps/S +4.43E-07 2006.246.08:24:55.11:!2006.246.08:25:50 2006.246.08:25:50.01:data_valid=off 2006.246.08:25:50.02:postob 2006.246.08:25:50.18/cable/+6.4137E-03 2006.246.08:25:50.22/wx/26.16,1005.8,77 2006.246.08:25:51.08/fmout-gps/S +4.42E-07 2006.246.08:25:51.09:scan_name=246-0826,k06246,60 2006.246.08:25:51.09:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.246.08:25:51.14#flagr#flagr/antenna,new-source 2006.246.08:25:52.14:checkk5 2006.246.08:25:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.246.08:25:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.246.08:25:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.246.08:25:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.246.08:25:54.00/chk_obsdata//k5ts1/T2460824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:25:54.37/chk_obsdata//k5ts2/T2460824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:25:54.74/chk_obsdata//k5ts3/T2460824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:25:55.11/chk_obsdata//k5ts4/T2460824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.246.08:25:55.80/k5log//k5ts1_log_newline 2006.246.08:25:56.49/k5log//k5ts2_log_newline 2006.246.08:25:57.18/k5log//k5ts3_log_newline 2006.246.08:25:57.87/k5log//k5ts4_log_newline 2006.246.08:25:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:25:57.89:4f8m12a=3 2006.246.08:25:57.89$4f8m12a/echo=on 2006.246.08:25:57.89$4f8m12a/pcalon 2006.246.08:25:57.89$pcalon/"no phase cal control is implemented here 2006.246.08:25:57.89$4f8m12a/"tpicd=stop 2006.246.08:25:57.89$4f8m12a/vc4f8 2006.246.08:25:57.89$vc4f8/valo=1,532.99 2006.246.08:25:57.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:25:57.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:25:57.90#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:57.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:25:57.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:25:57.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:25:57.90#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:25:57.90#ibcon#first serial, iclass 35, count 0 2006.246.08:25:57.90#ibcon#enter sib2, iclass 35, count 0 2006.246.08:25:57.90#ibcon#flushed, iclass 35, count 0 2006.246.08:25:57.90#ibcon#about to write, iclass 35, count 0 2006.246.08:25:57.90#ibcon#wrote, iclass 35, count 0 2006.246.08:25:57.90#ibcon#about to read 3, iclass 35, count 0 2006.246.08:25:57.93#ibcon#read 3, iclass 35, count 0 2006.246.08:25:57.93#ibcon#about to read 4, iclass 35, count 0 2006.246.08:25:57.93#ibcon#read 4, iclass 35, count 0 2006.246.08:25:57.93#ibcon#about to read 5, iclass 35, count 0 2006.246.08:25:57.93#ibcon#read 5, iclass 35, count 0 2006.246.08:25:57.93#ibcon#about to read 6, iclass 35, count 0 2006.246.08:25:57.93#ibcon#read 6, iclass 35, count 0 2006.246.08:25:57.93#ibcon#end of sib2, iclass 35, count 0 2006.246.08:25:57.93#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:25:57.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:25:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.246.08:25:57.93#ibcon#*before write, iclass 35, count 0 2006.246.08:25:57.93#ibcon#enter sib2, iclass 35, count 0 2006.246.08:25:57.93#ibcon#flushed, iclass 35, count 0 2006.246.08:25:57.93#ibcon#about to write, iclass 35, count 0 2006.246.08:25:57.93#ibcon#wrote, iclass 35, count 0 2006.246.08:25:57.93#ibcon#about to read 3, iclass 35, count 0 2006.246.08:25:57.98#ibcon#read 3, iclass 35, count 0 2006.246.08:25:57.98#ibcon#about to read 4, iclass 35, count 0 2006.246.08:25:57.98#ibcon#read 4, iclass 35, count 0 2006.246.08:25:57.98#ibcon#about to read 5, iclass 35, count 0 2006.246.08:25:57.98#ibcon#read 5, iclass 35, count 0 2006.246.08:25:57.98#ibcon#about to read 6, iclass 35, count 0 2006.246.08:25:57.98#ibcon#read 6, iclass 35, count 0 2006.246.08:25:57.98#ibcon#end of sib2, iclass 35, count 0 2006.246.08:25:57.98#ibcon#*after write, iclass 35, count 0 2006.246.08:25:57.98#ibcon#*before return 0, iclass 35, count 0 2006.246.08:25:57.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:25:57.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:25:57.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:25:57.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:25:57.98$vc4f8/va=1,8 2006.246.08:25:57.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:25:57.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:25:57.98#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:57.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:25:57.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:25:57.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:25:57.98#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:25:57.98#ibcon#first serial, iclass 37, count 2 2006.246.08:25:57.98#ibcon#enter sib2, iclass 37, count 2 2006.246.08:25:57.98#ibcon#flushed, iclass 37, count 2 2006.246.08:25:57.98#ibcon#about to write, iclass 37, count 2 2006.246.08:25:57.98#ibcon#wrote, iclass 37, count 2 2006.246.08:25:57.98#ibcon#about to read 3, iclass 37, count 2 2006.246.08:25:58.00#ibcon#read 3, iclass 37, count 2 2006.246.08:25:58.00#ibcon#about to read 4, iclass 37, count 2 2006.246.08:25:58.00#ibcon#read 4, iclass 37, count 2 2006.246.08:25:58.00#ibcon#about to read 5, iclass 37, count 2 2006.246.08:25:58.00#ibcon#read 5, iclass 37, count 2 2006.246.08:25:58.00#ibcon#about to read 6, iclass 37, count 2 2006.246.08:25:58.00#ibcon#read 6, iclass 37, count 2 2006.246.08:25:58.00#ibcon#end of sib2, iclass 37, count 2 2006.246.08:25:58.00#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:25:58.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:25:58.00#ibcon#[25=AT01-08\r\n] 2006.246.08:25:58.00#ibcon#*before write, iclass 37, count 2 2006.246.08:25:58.00#ibcon#enter sib2, iclass 37, count 2 2006.246.08:25:58.00#ibcon#flushed, iclass 37, count 2 2006.246.08:25:58.00#ibcon#about to write, iclass 37, count 2 2006.246.08:25:58.00#ibcon#wrote, iclass 37, count 2 2006.246.08:25:58.00#ibcon#about to read 3, iclass 37, count 2 2006.246.08:25:58.04#ibcon#read 3, iclass 37, count 2 2006.246.08:25:58.04#ibcon#about to read 4, iclass 37, count 2 2006.246.08:25:58.04#ibcon#read 4, iclass 37, count 2 2006.246.08:25:58.04#ibcon#about to read 5, iclass 37, count 2 2006.246.08:25:58.04#ibcon#read 5, iclass 37, count 2 2006.246.08:25:58.04#ibcon#about to read 6, iclass 37, count 2 2006.246.08:25:58.04#ibcon#read 6, iclass 37, count 2 2006.246.08:25:58.04#ibcon#end of sib2, iclass 37, count 2 2006.246.08:25:58.04#ibcon#*after write, iclass 37, count 2 2006.246.08:25:58.04#ibcon#*before return 0, iclass 37, count 2 2006.246.08:25:58.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:25:58.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:25:58.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:25:58.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:25:58.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:25:58.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:25:58.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:25:58.15#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:25:58.15#ibcon#first serial, iclass 37, count 0 2006.246.08:25:58.15#ibcon#enter sib2, iclass 37, count 0 2006.246.08:25:58.15#ibcon#flushed, iclass 37, count 0 2006.246.08:25:58.15#ibcon#about to write, iclass 37, count 0 2006.246.08:25:58.15#ibcon#wrote, iclass 37, count 0 2006.246.08:25:58.15#ibcon#about to read 3, iclass 37, count 0 2006.246.08:25:58.17#ibcon#read 3, iclass 37, count 0 2006.246.08:25:58.17#ibcon#about to read 4, iclass 37, count 0 2006.246.08:25:58.17#ibcon#read 4, iclass 37, count 0 2006.246.08:25:58.17#ibcon#about to read 5, iclass 37, count 0 2006.246.08:25:58.17#ibcon#read 5, iclass 37, count 0 2006.246.08:25:58.17#ibcon#about to read 6, iclass 37, count 0 2006.246.08:25:58.17#ibcon#read 6, iclass 37, count 0 2006.246.08:25:58.17#ibcon#end of sib2, iclass 37, count 0 2006.246.08:25:58.17#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:25:58.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:25:58.17#ibcon#[25=USB\r\n] 2006.246.08:25:58.17#ibcon#*before write, iclass 37, count 0 2006.246.08:25:58.17#ibcon#enter sib2, iclass 37, count 0 2006.246.08:25:58.17#ibcon#flushed, iclass 37, count 0 2006.246.08:25:58.17#ibcon#about to write, iclass 37, count 0 2006.246.08:25:58.17#ibcon#wrote, iclass 37, count 0 2006.246.08:25:58.17#ibcon#about to read 3, iclass 37, count 0 2006.246.08:25:58.20#ibcon#read 3, iclass 37, count 0 2006.246.08:25:58.20#ibcon#about to read 4, iclass 37, count 0 2006.246.08:25:58.20#ibcon#read 4, iclass 37, count 0 2006.246.08:25:58.20#ibcon#about to read 5, iclass 37, count 0 2006.246.08:25:58.20#ibcon#read 5, iclass 37, count 0 2006.246.08:25:58.20#ibcon#about to read 6, iclass 37, count 0 2006.246.08:25:58.20#ibcon#read 6, iclass 37, count 0 2006.246.08:25:58.20#ibcon#end of sib2, iclass 37, count 0 2006.246.08:25:58.20#ibcon#*after write, iclass 37, count 0 2006.246.08:25:58.20#ibcon#*before return 0, iclass 37, count 0 2006.246.08:25:58.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:25:58.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:25:58.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:25:58.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:25:58.20$vc4f8/valo=2,572.99 2006.246.08:25:58.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:25:58.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:25:58.20#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:58.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:25:58.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:25:58.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:25:58.20#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:25:58.20#ibcon#first serial, iclass 39, count 0 2006.246.08:25:58.20#ibcon#enter sib2, iclass 39, count 0 2006.246.08:25:58.20#ibcon#flushed, iclass 39, count 0 2006.246.08:25:58.20#ibcon#about to write, iclass 39, count 0 2006.246.08:25:58.20#ibcon#wrote, iclass 39, count 0 2006.246.08:25:58.20#ibcon#about to read 3, iclass 39, count 0 2006.246.08:25:58.22#ibcon#read 3, iclass 39, count 0 2006.246.08:25:58.22#ibcon#about to read 4, iclass 39, count 0 2006.246.08:25:58.22#ibcon#read 4, iclass 39, count 0 2006.246.08:25:58.22#ibcon#about to read 5, iclass 39, count 0 2006.246.08:25:58.22#ibcon#read 5, iclass 39, count 0 2006.246.08:25:58.22#ibcon#about to read 6, iclass 39, count 0 2006.246.08:25:58.22#ibcon#read 6, iclass 39, count 0 2006.246.08:25:58.22#ibcon#end of sib2, iclass 39, count 0 2006.246.08:25:58.22#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:25:58.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:25:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.246.08:25:58.22#ibcon#*before write, iclass 39, count 0 2006.246.08:25:58.22#ibcon#enter sib2, iclass 39, count 0 2006.246.08:25:58.22#ibcon#flushed, iclass 39, count 0 2006.246.08:25:58.22#ibcon#about to write, iclass 39, count 0 2006.246.08:25:58.22#ibcon#wrote, iclass 39, count 0 2006.246.08:25:58.22#ibcon#about to read 3, iclass 39, count 0 2006.246.08:25:58.26#ibcon#read 3, iclass 39, count 0 2006.246.08:25:58.26#ibcon#about to read 4, iclass 39, count 0 2006.246.08:25:58.26#ibcon#read 4, iclass 39, count 0 2006.246.08:25:58.26#ibcon#about to read 5, iclass 39, count 0 2006.246.08:25:58.26#ibcon#read 5, iclass 39, count 0 2006.246.08:25:58.26#ibcon#about to read 6, iclass 39, count 0 2006.246.08:25:58.26#ibcon#read 6, iclass 39, count 0 2006.246.08:25:58.26#ibcon#end of sib2, iclass 39, count 0 2006.246.08:25:58.26#ibcon#*after write, iclass 39, count 0 2006.246.08:25:58.26#ibcon#*before return 0, iclass 39, count 0 2006.246.08:25:58.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:25:58.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:25:58.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:25:58.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:25:58.26$vc4f8/va=2,7 2006.246.08:25:58.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:25:58.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:25:58.26#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:58.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:25:58.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:25:58.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:25:58.32#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:25:58.32#ibcon#first serial, iclass 3, count 2 2006.246.08:25:58.32#ibcon#enter sib2, iclass 3, count 2 2006.246.08:25:58.32#ibcon#flushed, iclass 3, count 2 2006.246.08:25:58.32#ibcon#about to write, iclass 3, count 2 2006.246.08:25:58.32#ibcon#wrote, iclass 3, count 2 2006.246.08:25:58.32#ibcon#about to read 3, iclass 3, count 2 2006.246.08:25:58.34#ibcon#read 3, iclass 3, count 2 2006.246.08:25:58.34#ibcon#about to read 4, iclass 3, count 2 2006.246.08:25:58.34#ibcon#read 4, iclass 3, count 2 2006.246.08:25:58.34#ibcon#about to read 5, iclass 3, count 2 2006.246.08:25:58.34#ibcon#read 5, iclass 3, count 2 2006.246.08:25:58.34#ibcon#about to read 6, iclass 3, count 2 2006.246.08:25:58.34#ibcon#read 6, iclass 3, count 2 2006.246.08:25:58.34#ibcon#end of sib2, iclass 3, count 2 2006.246.08:25:58.34#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:25:58.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:25:58.34#ibcon#[25=AT02-07\r\n] 2006.246.08:25:58.34#ibcon#*before write, iclass 3, count 2 2006.246.08:25:58.34#ibcon#enter sib2, iclass 3, count 2 2006.246.08:25:58.34#ibcon#flushed, iclass 3, count 2 2006.246.08:25:58.34#ibcon#about to write, iclass 3, count 2 2006.246.08:25:58.34#ibcon#wrote, iclass 3, count 2 2006.246.08:25:58.34#ibcon#about to read 3, iclass 3, count 2 2006.246.08:25:58.37#ibcon#read 3, iclass 3, count 2 2006.246.08:25:58.37#ibcon#about to read 4, iclass 3, count 2 2006.246.08:25:58.37#ibcon#read 4, iclass 3, count 2 2006.246.08:25:58.37#ibcon#about to read 5, iclass 3, count 2 2006.246.08:25:58.37#ibcon#read 5, iclass 3, count 2 2006.246.08:25:58.37#ibcon#about to read 6, iclass 3, count 2 2006.246.08:25:58.37#ibcon#read 6, iclass 3, count 2 2006.246.08:25:58.37#ibcon#end of sib2, iclass 3, count 2 2006.246.08:25:58.37#ibcon#*after write, iclass 3, count 2 2006.246.08:25:58.37#ibcon#*before return 0, iclass 3, count 2 2006.246.08:25:58.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:25:58.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:25:58.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:25:58.37#ibcon#ireg 7 cls_cnt 0 2006.246.08:25:58.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:25:58.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:25:58.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:25:58.49#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:25:58.49#ibcon#first serial, iclass 3, count 0 2006.246.08:25:58.49#ibcon#enter sib2, iclass 3, count 0 2006.246.08:25:58.49#ibcon#flushed, iclass 3, count 0 2006.246.08:25:58.49#ibcon#about to write, iclass 3, count 0 2006.246.08:25:58.49#ibcon#wrote, iclass 3, count 0 2006.246.08:25:58.49#ibcon#about to read 3, iclass 3, count 0 2006.246.08:25:58.51#ibcon#read 3, iclass 3, count 0 2006.246.08:25:58.51#ibcon#about to read 4, iclass 3, count 0 2006.246.08:25:58.51#ibcon#read 4, iclass 3, count 0 2006.246.08:25:58.51#ibcon#about to read 5, iclass 3, count 0 2006.246.08:25:58.51#ibcon#read 5, iclass 3, count 0 2006.246.08:25:58.51#ibcon#about to read 6, iclass 3, count 0 2006.246.08:25:58.51#ibcon#read 6, iclass 3, count 0 2006.246.08:25:58.51#ibcon#end of sib2, iclass 3, count 0 2006.246.08:25:58.51#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:25:58.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:25:58.51#ibcon#[25=USB\r\n] 2006.246.08:25:58.51#ibcon#*before write, iclass 3, count 0 2006.246.08:25:58.51#ibcon#enter sib2, iclass 3, count 0 2006.246.08:25:58.51#ibcon#flushed, iclass 3, count 0 2006.246.08:25:58.51#ibcon#about to write, iclass 3, count 0 2006.246.08:25:58.51#ibcon#wrote, iclass 3, count 0 2006.246.08:25:58.51#ibcon#about to read 3, iclass 3, count 0 2006.246.08:25:58.54#ibcon#read 3, iclass 3, count 0 2006.246.08:25:58.54#ibcon#about to read 4, iclass 3, count 0 2006.246.08:25:58.54#ibcon#read 4, iclass 3, count 0 2006.246.08:25:58.54#ibcon#about to read 5, iclass 3, count 0 2006.246.08:25:58.54#ibcon#read 5, iclass 3, count 0 2006.246.08:25:58.54#ibcon#about to read 6, iclass 3, count 0 2006.246.08:25:58.54#ibcon#read 6, iclass 3, count 0 2006.246.08:25:58.54#ibcon#end of sib2, iclass 3, count 0 2006.246.08:25:58.54#ibcon#*after write, iclass 3, count 0 2006.246.08:25:58.54#ibcon#*before return 0, iclass 3, count 0 2006.246.08:25:58.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:25:58.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:25:58.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:25:58.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:25:58.54$vc4f8/valo=3,672.99 2006.246.08:25:58.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:25:58.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:25:58.54#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:58.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:25:58.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:25:58.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:25:58.54#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:25:58.54#ibcon#first serial, iclass 5, count 0 2006.246.08:25:58.54#ibcon#enter sib2, iclass 5, count 0 2006.246.08:25:58.54#ibcon#flushed, iclass 5, count 0 2006.246.08:25:58.54#ibcon#about to write, iclass 5, count 0 2006.246.08:25:58.54#ibcon#wrote, iclass 5, count 0 2006.246.08:25:58.54#ibcon#about to read 3, iclass 5, count 0 2006.246.08:25:58.56#ibcon#read 3, iclass 5, count 0 2006.246.08:25:58.56#ibcon#about to read 4, iclass 5, count 0 2006.246.08:25:58.56#ibcon#read 4, iclass 5, count 0 2006.246.08:25:58.56#ibcon#about to read 5, iclass 5, count 0 2006.246.08:25:58.56#ibcon#read 5, iclass 5, count 0 2006.246.08:25:58.56#ibcon#about to read 6, iclass 5, count 0 2006.246.08:25:58.56#ibcon#read 6, iclass 5, count 0 2006.246.08:25:58.56#ibcon#end of sib2, iclass 5, count 0 2006.246.08:25:58.56#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:25:58.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:25:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.246.08:25:58.56#ibcon#*before write, iclass 5, count 0 2006.246.08:25:58.56#ibcon#enter sib2, iclass 5, count 0 2006.246.08:25:58.56#ibcon#flushed, iclass 5, count 0 2006.246.08:25:58.56#ibcon#about to write, iclass 5, count 0 2006.246.08:25:58.56#ibcon#wrote, iclass 5, count 0 2006.246.08:25:58.56#ibcon#about to read 3, iclass 5, count 0 2006.246.08:25:58.60#ibcon#read 3, iclass 5, count 0 2006.246.08:25:58.60#ibcon#about to read 4, iclass 5, count 0 2006.246.08:25:58.60#ibcon#read 4, iclass 5, count 0 2006.246.08:25:58.60#ibcon#about to read 5, iclass 5, count 0 2006.246.08:25:58.60#ibcon#read 5, iclass 5, count 0 2006.246.08:25:58.60#ibcon#about to read 6, iclass 5, count 0 2006.246.08:25:58.60#ibcon#read 6, iclass 5, count 0 2006.246.08:25:58.60#ibcon#end of sib2, iclass 5, count 0 2006.246.08:25:58.60#ibcon#*after write, iclass 5, count 0 2006.246.08:25:58.60#ibcon#*before return 0, iclass 5, count 0 2006.246.08:25:58.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:25:58.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:25:58.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:25:58.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:25:58.60$vc4f8/va=3,6 2006.246.08:25:58.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.08:25:58.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.08:25:58.60#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:58.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:25:58.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:25:58.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:25:58.66#ibcon#enter wrdev, iclass 7, count 2 2006.246.08:25:58.66#ibcon#first serial, iclass 7, count 2 2006.246.08:25:58.66#ibcon#enter sib2, iclass 7, count 2 2006.246.08:25:58.66#ibcon#flushed, iclass 7, count 2 2006.246.08:25:58.66#ibcon#about to write, iclass 7, count 2 2006.246.08:25:58.66#ibcon#wrote, iclass 7, count 2 2006.246.08:25:58.66#ibcon#about to read 3, iclass 7, count 2 2006.246.08:25:58.69#ibcon#read 3, iclass 7, count 2 2006.246.08:25:58.69#ibcon#about to read 4, iclass 7, count 2 2006.246.08:25:58.69#ibcon#read 4, iclass 7, count 2 2006.246.08:25:58.69#ibcon#about to read 5, iclass 7, count 2 2006.246.08:25:58.69#ibcon#read 5, iclass 7, count 2 2006.246.08:25:58.69#ibcon#about to read 6, iclass 7, count 2 2006.246.08:25:58.69#ibcon#read 6, iclass 7, count 2 2006.246.08:25:58.69#ibcon#end of sib2, iclass 7, count 2 2006.246.08:25:58.69#ibcon#*mode == 0, iclass 7, count 2 2006.246.08:25:58.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.08:25:58.69#ibcon#[25=AT03-06\r\n] 2006.246.08:25:58.69#ibcon#*before write, iclass 7, count 2 2006.246.08:25:58.69#ibcon#enter sib2, iclass 7, count 2 2006.246.08:25:58.69#ibcon#flushed, iclass 7, count 2 2006.246.08:25:58.69#ibcon#about to write, iclass 7, count 2 2006.246.08:25:58.69#ibcon#wrote, iclass 7, count 2 2006.246.08:25:58.69#ibcon#about to read 3, iclass 7, count 2 2006.246.08:25:58.72#ibcon#read 3, iclass 7, count 2 2006.246.08:25:58.72#ibcon#about to read 4, iclass 7, count 2 2006.246.08:25:58.72#ibcon#read 4, iclass 7, count 2 2006.246.08:25:58.72#ibcon#about to read 5, iclass 7, count 2 2006.246.08:25:58.72#ibcon#read 5, iclass 7, count 2 2006.246.08:25:58.72#ibcon#about to read 6, iclass 7, count 2 2006.246.08:25:58.72#ibcon#read 6, iclass 7, count 2 2006.246.08:25:58.72#ibcon#end of sib2, iclass 7, count 2 2006.246.08:25:58.72#ibcon#*after write, iclass 7, count 2 2006.246.08:25:58.72#ibcon#*before return 0, iclass 7, count 2 2006.246.08:25:58.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:25:58.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:25:58.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.08:25:58.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:25:58.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:25:58.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:25:58.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:25:58.84#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:25:58.84#ibcon#first serial, iclass 7, count 0 2006.246.08:25:58.84#ibcon#enter sib2, iclass 7, count 0 2006.246.08:25:58.84#ibcon#flushed, iclass 7, count 0 2006.246.08:25:58.84#ibcon#about to write, iclass 7, count 0 2006.246.08:25:58.84#ibcon#wrote, iclass 7, count 0 2006.246.08:25:58.84#ibcon#about to read 3, iclass 7, count 0 2006.246.08:25:58.86#ibcon#read 3, iclass 7, count 0 2006.246.08:25:58.86#ibcon#about to read 4, iclass 7, count 0 2006.246.08:25:58.86#ibcon#read 4, iclass 7, count 0 2006.246.08:25:58.86#ibcon#about to read 5, iclass 7, count 0 2006.246.08:25:58.86#ibcon#read 5, iclass 7, count 0 2006.246.08:25:58.86#ibcon#about to read 6, iclass 7, count 0 2006.246.08:25:58.86#ibcon#read 6, iclass 7, count 0 2006.246.08:25:58.86#ibcon#end of sib2, iclass 7, count 0 2006.246.08:25:58.86#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:25:58.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:25:58.86#ibcon#[25=USB\r\n] 2006.246.08:25:58.86#ibcon#*before write, iclass 7, count 0 2006.246.08:25:58.86#ibcon#enter sib2, iclass 7, count 0 2006.246.08:25:58.86#ibcon#flushed, iclass 7, count 0 2006.246.08:25:58.86#ibcon#about to write, iclass 7, count 0 2006.246.08:25:58.86#ibcon#wrote, iclass 7, count 0 2006.246.08:25:58.86#ibcon#about to read 3, iclass 7, count 0 2006.246.08:25:58.89#ibcon#read 3, iclass 7, count 0 2006.246.08:25:58.89#ibcon#about to read 4, iclass 7, count 0 2006.246.08:25:58.89#ibcon#read 4, iclass 7, count 0 2006.246.08:25:58.89#ibcon#about to read 5, iclass 7, count 0 2006.246.08:25:58.89#ibcon#read 5, iclass 7, count 0 2006.246.08:25:58.89#ibcon#about to read 6, iclass 7, count 0 2006.246.08:25:58.89#ibcon#read 6, iclass 7, count 0 2006.246.08:25:58.89#ibcon#end of sib2, iclass 7, count 0 2006.246.08:25:58.89#ibcon#*after write, iclass 7, count 0 2006.246.08:25:58.89#ibcon#*before return 0, iclass 7, count 0 2006.246.08:25:58.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:25:58.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:25:58.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:25:58.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:25:58.89$vc4f8/valo=4,832.99 2006.246.08:25:58.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.08:25:58.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.08:25:58.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:58.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:25:58.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:25:58.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:25:58.89#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:25:58.89#ibcon#first serial, iclass 11, count 0 2006.246.08:25:58.89#ibcon#enter sib2, iclass 11, count 0 2006.246.08:25:58.89#ibcon#flushed, iclass 11, count 0 2006.246.08:25:58.89#ibcon#about to write, iclass 11, count 0 2006.246.08:25:58.89#ibcon#wrote, iclass 11, count 0 2006.246.08:25:58.89#ibcon#about to read 3, iclass 11, count 0 2006.246.08:25:58.91#ibcon#read 3, iclass 11, count 0 2006.246.08:25:58.91#ibcon#about to read 4, iclass 11, count 0 2006.246.08:25:58.91#ibcon#read 4, iclass 11, count 0 2006.246.08:25:58.91#ibcon#about to read 5, iclass 11, count 0 2006.246.08:25:58.91#ibcon#read 5, iclass 11, count 0 2006.246.08:25:58.91#ibcon#about to read 6, iclass 11, count 0 2006.246.08:25:58.91#ibcon#read 6, iclass 11, count 0 2006.246.08:25:58.91#ibcon#end of sib2, iclass 11, count 0 2006.246.08:25:58.91#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:25:58.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:25:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.246.08:25:58.91#ibcon#*before write, iclass 11, count 0 2006.246.08:25:58.91#ibcon#enter sib2, iclass 11, count 0 2006.246.08:25:58.91#ibcon#flushed, iclass 11, count 0 2006.246.08:25:58.91#ibcon#about to write, iclass 11, count 0 2006.246.08:25:58.91#ibcon#wrote, iclass 11, count 0 2006.246.08:25:58.91#ibcon#about to read 3, iclass 11, count 0 2006.246.08:25:58.95#ibcon#read 3, iclass 11, count 0 2006.246.08:25:58.95#ibcon#about to read 4, iclass 11, count 0 2006.246.08:25:58.95#ibcon#read 4, iclass 11, count 0 2006.246.08:25:58.95#ibcon#about to read 5, iclass 11, count 0 2006.246.08:25:58.95#ibcon#read 5, iclass 11, count 0 2006.246.08:25:58.95#ibcon#about to read 6, iclass 11, count 0 2006.246.08:25:58.95#ibcon#read 6, iclass 11, count 0 2006.246.08:25:58.95#ibcon#end of sib2, iclass 11, count 0 2006.246.08:25:58.95#ibcon#*after write, iclass 11, count 0 2006.246.08:25:58.95#ibcon#*before return 0, iclass 11, count 0 2006.246.08:25:58.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:25:58.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:25:58.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:25:58.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:25:58.95$vc4f8/va=4,7 2006.246.08:25:58.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.08:25:58.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.08:25:58.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:58.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:25:59.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:25:59.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:25:59.01#ibcon#enter wrdev, iclass 13, count 2 2006.246.08:25:59.01#ibcon#first serial, iclass 13, count 2 2006.246.08:25:59.01#ibcon#enter sib2, iclass 13, count 2 2006.246.08:25:59.01#ibcon#flushed, iclass 13, count 2 2006.246.08:25:59.01#ibcon#about to write, iclass 13, count 2 2006.246.08:25:59.01#ibcon#wrote, iclass 13, count 2 2006.246.08:25:59.01#ibcon#about to read 3, iclass 13, count 2 2006.246.08:25:59.03#ibcon#read 3, iclass 13, count 2 2006.246.08:25:59.03#ibcon#about to read 4, iclass 13, count 2 2006.246.08:25:59.03#ibcon#read 4, iclass 13, count 2 2006.246.08:25:59.03#ibcon#about to read 5, iclass 13, count 2 2006.246.08:25:59.03#ibcon#read 5, iclass 13, count 2 2006.246.08:25:59.03#ibcon#about to read 6, iclass 13, count 2 2006.246.08:25:59.03#ibcon#read 6, iclass 13, count 2 2006.246.08:25:59.03#ibcon#end of sib2, iclass 13, count 2 2006.246.08:25:59.03#ibcon#*mode == 0, iclass 13, count 2 2006.246.08:25:59.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.08:25:59.03#ibcon#[25=AT04-07\r\n] 2006.246.08:25:59.03#ibcon#*before write, iclass 13, count 2 2006.246.08:25:59.03#ibcon#enter sib2, iclass 13, count 2 2006.246.08:25:59.03#ibcon#flushed, iclass 13, count 2 2006.246.08:25:59.03#ibcon#about to write, iclass 13, count 2 2006.246.08:25:59.03#ibcon#wrote, iclass 13, count 2 2006.246.08:25:59.03#ibcon#about to read 3, iclass 13, count 2 2006.246.08:25:59.06#ibcon#read 3, iclass 13, count 2 2006.246.08:25:59.06#ibcon#about to read 4, iclass 13, count 2 2006.246.08:25:59.06#ibcon#read 4, iclass 13, count 2 2006.246.08:25:59.06#ibcon#about to read 5, iclass 13, count 2 2006.246.08:25:59.06#ibcon#read 5, iclass 13, count 2 2006.246.08:25:59.06#ibcon#about to read 6, iclass 13, count 2 2006.246.08:25:59.06#ibcon#read 6, iclass 13, count 2 2006.246.08:25:59.06#ibcon#end of sib2, iclass 13, count 2 2006.246.08:25:59.06#ibcon#*after write, iclass 13, count 2 2006.246.08:25:59.06#ibcon#*before return 0, iclass 13, count 2 2006.246.08:25:59.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:25:59.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:25:59.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.08:25:59.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:25:59.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:25:59.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:25:59.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:25:59.18#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:25:59.18#ibcon#first serial, iclass 13, count 0 2006.246.08:25:59.18#ibcon#enter sib2, iclass 13, count 0 2006.246.08:25:59.18#ibcon#flushed, iclass 13, count 0 2006.246.08:25:59.18#ibcon#about to write, iclass 13, count 0 2006.246.08:25:59.18#ibcon#wrote, iclass 13, count 0 2006.246.08:25:59.18#ibcon#about to read 3, iclass 13, count 0 2006.246.08:25:59.20#ibcon#read 3, iclass 13, count 0 2006.246.08:25:59.20#ibcon#about to read 4, iclass 13, count 0 2006.246.08:25:59.20#ibcon#read 4, iclass 13, count 0 2006.246.08:25:59.20#ibcon#about to read 5, iclass 13, count 0 2006.246.08:25:59.20#ibcon#read 5, iclass 13, count 0 2006.246.08:25:59.20#ibcon#about to read 6, iclass 13, count 0 2006.246.08:25:59.20#ibcon#read 6, iclass 13, count 0 2006.246.08:25:59.20#ibcon#end of sib2, iclass 13, count 0 2006.246.08:25:59.20#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:25:59.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:25:59.20#ibcon#[25=USB\r\n] 2006.246.08:25:59.20#ibcon#*before write, iclass 13, count 0 2006.246.08:25:59.20#ibcon#enter sib2, iclass 13, count 0 2006.246.08:25:59.20#ibcon#flushed, iclass 13, count 0 2006.246.08:25:59.20#ibcon#about to write, iclass 13, count 0 2006.246.08:25:59.20#ibcon#wrote, iclass 13, count 0 2006.246.08:25:59.20#ibcon#about to read 3, iclass 13, count 0 2006.246.08:25:59.23#ibcon#read 3, iclass 13, count 0 2006.246.08:25:59.23#ibcon#about to read 4, iclass 13, count 0 2006.246.08:25:59.23#ibcon#read 4, iclass 13, count 0 2006.246.08:25:59.23#ibcon#about to read 5, iclass 13, count 0 2006.246.08:25:59.23#ibcon#read 5, iclass 13, count 0 2006.246.08:25:59.23#ibcon#about to read 6, iclass 13, count 0 2006.246.08:25:59.23#ibcon#read 6, iclass 13, count 0 2006.246.08:25:59.23#ibcon#end of sib2, iclass 13, count 0 2006.246.08:25:59.23#ibcon#*after write, iclass 13, count 0 2006.246.08:25:59.23#ibcon#*before return 0, iclass 13, count 0 2006.246.08:25:59.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:25:59.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:25:59.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:25:59.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:25:59.23$vc4f8/valo=5,652.99 2006.246.08:25:59.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.08:25:59.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.08:25:59.23#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:59.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:25:59.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:25:59.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:25:59.23#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:25:59.23#ibcon#first serial, iclass 15, count 0 2006.246.08:25:59.23#ibcon#enter sib2, iclass 15, count 0 2006.246.08:25:59.23#ibcon#flushed, iclass 15, count 0 2006.246.08:25:59.23#ibcon#about to write, iclass 15, count 0 2006.246.08:25:59.23#ibcon#wrote, iclass 15, count 0 2006.246.08:25:59.23#ibcon#about to read 3, iclass 15, count 0 2006.246.08:25:59.25#ibcon#read 3, iclass 15, count 0 2006.246.08:25:59.25#ibcon#about to read 4, iclass 15, count 0 2006.246.08:25:59.25#ibcon#read 4, iclass 15, count 0 2006.246.08:25:59.25#ibcon#about to read 5, iclass 15, count 0 2006.246.08:25:59.25#ibcon#read 5, iclass 15, count 0 2006.246.08:25:59.25#ibcon#about to read 6, iclass 15, count 0 2006.246.08:25:59.25#ibcon#read 6, iclass 15, count 0 2006.246.08:25:59.25#ibcon#end of sib2, iclass 15, count 0 2006.246.08:25:59.25#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:25:59.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:25:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.246.08:25:59.25#ibcon#*before write, iclass 15, count 0 2006.246.08:25:59.25#ibcon#enter sib2, iclass 15, count 0 2006.246.08:25:59.25#ibcon#flushed, iclass 15, count 0 2006.246.08:25:59.25#ibcon#about to write, iclass 15, count 0 2006.246.08:25:59.25#ibcon#wrote, iclass 15, count 0 2006.246.08:25:59.25#ibcon#about to read 3, iclass 15, count 0 2006.246.08:25:59.29#ibcon#read 3, iclass 15, count 0 2006.246.08:25:59.29#ibcon#about to read 4, iclass 15, count 0 2006.246.08:25:59.29#ibcon#read 4, iclass 15, count 0 2006.246.08:25:59.29#ibcon#about to read 5, iclass 15, count 0 2006.246.08:25:59.29#ibcon#read 5, iclass 15, count 0 2006.246.08:25:59.29#ibcon#about to read 6, iclass 15, count 0 2006.246.08:25:59.29#ibcon#read 6, iclass 15, count 0 2006.246.08:25:59.29#ibcon#end of sib2, iclass 15, count 0 2006.246.08:25:59.29#ibcon#*after write, iclass 15, count 0 2006.246.08:25:59.29#ibcon#*before return 0, iclass 15, count 0 2006.246.08:25:59.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:25:59.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:25:59.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:25:59.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:25:59.29$vc4f8/va=5,7 2006.246.08:25:59.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.08:25:59.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.08:25:59.29#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:59.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:25:59.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:25:59.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:25:59.35#ibcon#enter wrdev, iclass 17, count 2 2006.246.08:25:59.35#ibcon#first serial, iclass 17, count 2 2006.246.08:25:59.35#ibcon#enter sib2, iclass 17, count 2 2006.246.08:25:59.35#ibcon#flushed, iclass 17, count 2 2006.246.08:25:59.35#ibcon#about to write, iclass 17, count 2 2006.246.08:25:59.35#ibcon#wrote, iclass 17, count 2 2006.246.08:25:59.35#ibcon#about to read 3, iclass 17, count 2 2006.246.08:25:59.37#ibcon#read 3, iclass 17, count 2 2006.246.08:25:59.37#ibcon#about to read 4, iclass 17, count 2 2006.246.08:25:59.37#ibcon#read 4, iclass 17, count 2 2006.246.08:25:59.37#ibcon#about to read 5, iclass 17, count 2 2006.246.08:25:59.37#ibcon#read 5, iclass 17, count 2 2006.246.08:25:59.37#ibcon#about to read 6, iclass 17, count 2 2006.246.08:25:59.37#ibcon#read 6, iclass 17, count 2 2006.246.08:25:59.37#ibcon#end of sib2, iclass 17, count 2 2006.246.08:25:59.37#ibcon#*mode == 0, iclass 17, count 2 2006.246.08:25:59.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.08:25:59.37#ibcon#[25=AT05-07\r\n] 2006.246.08:25:59.37#ibcon#*before write, iclass 17, count 2 2006.246.08:25:59.37#ibcon#enter sib2, iclass 17, count 2 2006.246.08:25:59.37#ibcon#flushed, iclass 17, count 2 2006.246.08:25:59.37#ibcon#about to write, iclass 17, count 2 2006.246.08:25:59.37#ibcon#wrote, iclass 17, count 2 2006.246.08:25:59.37#ibcon#about to read 3, iclass 17, count 2 2006.246.08:25:59.40#ibcon#read 3, iclass 17, count 2 2006.246.08:25:59.40#ibcon#about to read 4, iclass 17, count 2 2006.246.08:25:59.40#ibcon#read 4, iclass 17, count 2 2006.246.08:25:59.40#ibcon#about to read 5, iclass 17, count 2 2006.246.08:25:59.40#ibcon#read 5, iclass 17, count 2 2006.246.08:25:59.40#ibcon#about to read 6, iclass 17, count 2 2006.246.08:25:59.40#ibcon#read 6, iclass 17, count 2 2006.246.08:25:59.40#ibcon#end of sib2, iclass 17, count 2 2006.246.08:25:59.40#ibcon#*after write, iclass 17, count 2 2006.246.08:25:59.40#ibcon#*before return 0, iclass 17, count 2 2006.246.08:25:59.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:25:59.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:25:59.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.08:25:59.40#ibcon#ireg 7 cls_cnt 0 2006.246.08:25:59.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:25:59.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:25:59.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:25:59.52#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:25:59.52#ibcon#first serial, iclass 17, count 0 2006.246.08:25:59.52#ibcon#enter sib2, iclass 17, count 0 2006.246.08:25:59.52#ibcon#flushed, iclass 17, count 0 2006.246.08:25:59.52#ibcon#about to write, iclass 17, count 0 2006.246.08:25:59.52#ibcon#wrote, iclass 17, count 0 2006.246.08:25:59.52#ibcon#about to read 3, iclass 17, count 0 2006.246.08:25:59.54#ibcon#read 3, iclass 17, count 0 2006.246.08:25:59.54#ibcon#about to read 4, iclass 17, count 0 2006.246.08:25:59.54#ibcon#read 4, iclass 17, count 0 2006.246.08:25:59.54#ibcon#about to read 5, iclass 17, count 0 2006.246.08:25:59.54#ibcon#read 5, iclass 17, count 0 2006.246.08:25:59.54#ibcon#about to read 6, iclass 17, count 0 2006.246.08:25:59.54#ibcon#read 6, iclass 17, count 0 2006.246.08:25:59.54#ibcon#end of sib2, iclass 17, count 0 2006.246.08:25:59.54#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:25:59.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:25:59.54#ibcon#[25=USB\r\n] 2006.246.08:25:59.54#ibcon#*before write, iclass 17, count 0 2006.246.08:25:59.54#ibcon#enter sib2, iclass 17, count 0 2006.246.08:25:59.54#ibcon#flushed, iclass 17, count 0 2006.246.08:25:59.54#ibcon#about to write, iclass 17, count 0 2006.246.08:25:59.54#ibcon#wrote, iclass 17, count 0 2006.246.08:25:59.54#ibcon#about to read 3, iclass 17, count 0 2006.246.08:25:59.57#ibcon#read 3, iclass 17, count 0 2006.246.08:25:59.57#ibcon#about to read 4, iclass 17, count 0 2006.246.08:25:59.57#ibcon#read 4, iclass 17, count 0 2006.246.08:25:59.57#ibcon#about to read 5, iclass 17, count 0 2006.246.08:25:59.57#ibcon#read 5, iclass 17, count 0 2006.246.08:25:59.57#ibcon#about to read 6, iclass 17, count 0 2006.246.08:25:59.57#ibcon#read 6, iclass 17, count 0 2006.246.08:25:59.57#ibcon#end of sib2, iclass 17, count 0 2006.246.08:25:59.57#ibcon#*after write, iclass 17, count 0 2006.246.08:25:59.57#ibcon#*before return 0, iclass 17, count 0 2006.246.08:25:59.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:25:59.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:25:59.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:25:59.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:25:59.57$vc4f8/valo=6,772.99 2006.246.08:25:59.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.08:25:59.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.08:25:59.57#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:59.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:25:59.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:25:59.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:25:59.57#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:25:59.57#ibcon#first serial, iclass 19, count 0 2006.246.08:25:59.57#ibcon#enter sib2, iclass 19, count 0 2006.246.08:25:59.57#ibcon#flushed, iclass 19, count 0 2006.246.08:25:59.57#ibcon#about to write, iclass 19, count 0 2006.246.08:25:59.57#ibcon#wrote, iclass 19, count 0 2006.246.08:25:59.57#ibcon#about to read 3, iclass 19, count 0 2006.246.08:25:59.59#ibcon#read 3, iclass 19, count 0 2006.246.08:25:59.59#ibcon#about to read 4, iclass 19, count 0 2006.246.08:25:59.59#ibcon#read 4, iclass 19, count 0 2006.246.08:25:59.59#ibcon#about to read 5, iclass 19, count 0 2006.246.08:25:59.59#ibcon#read 5, iclass 19, count 0 2006.246.08:25:59.59#ibcon#about to read 6, iclass 19, count 0 2006.246.08:25:59.59#ibcon#read 6, iclass 19, count 0 2006.246.08:25:59.59#ibcon#end of sib2, iclass 19, count 0 2006.246.08:25:59.59#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:25:59.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:25:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.246.08:25:59.59#ibcon#*before write, iclass 19, count 0 2006.246.08:25:59.59#ibcon#enter sib2, iclass 19, count 0 2006.246.08:25:59.59#ibcon#flushed, iclass 19, count 0 2006.246.08:25:59.59#ibcon#about to write, iclass 19, count 0 2006.246.08:25:59.59#ibcon#wrote, iclass 19, count 0 2006.246.08:25:59.59#ibcon#about to read 3, iclass 19, count 0 2006.246.08:25:59.63#ibcon#read 3, iclass 19, count 0 2006.246.08:25:59.63#ibcon#about to read 4, iclass 19, count 0 2006.246.08:25:59.63#ibcon#read 4, iclass 19, count 0 2006.246.08:25:59.63#ibcon#about to read 5, iclass 19, count 0 2006.246.08:25:59.63#ibcon#read 5, iclass 19, count 0 2006.246.08:25:59.63#ibcon#about to read 6, iclass 19, count 0 2006.246.08:25:59.63#ibcon#read 6, iclass 19, count 0 2006.246.08:25:59.63#ibcon#end of sib2, iclass 19, count 0 2006.246.08:25:59.63#ibcon#*after write, iclass 19, count 0 2006.246.08:25:59.63#ibcon#*before return 0, iclass 19, count 0 2006.246.08:25:59.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:25:59.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:25:59.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:25:59.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:25:59.63$vc4f8/va=6,7 2006.246.08:25:59.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.246.08:25:59.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.246.08:25:59.63#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:59.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:25:59.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:25:59.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:25:59.69#ibcon#enter wrdev, iclass 21, count 2 2006.246.08:25:59.69#ibcon#first serial, iclass 21, count 2 2006.246.08:25:59.69#ibcon#enter sib2, iclass 21, count 2 2006.246.08:25:59.69#ibcon#flushed, iclass 21, count 2 2006.246.08:25:59.69#ibcon#about to write, iclass 21, count 2 2006.246.08:25:59.69#ibcon#wrote, iclass 21, count 2 2006.246.08:25:59.69#ibcon#about to read 3, iclass 21, count 2 2006.246.08:25:59.71#ibcon#read 3, iclass 21, count 2 2006.246.08:25:59.71#ibcon#about to read 4, iclass 21, count 2 2006.246.08:25:59.71#ibcon#read 4, iclass 21, count 2 2006.246.08:25:59.71#ibcon#about to read 5, iclass 21, count 2 2006.246.08:25:59.71#ibcon#read 5, iclass 21, count 2 2006.246.08:25:59.71#ibcon#about to read 6, iclass 21, count 2 2006.246.08:25:59.71#ibcon#read 6, iclass 21, count 2 2006.246.08:25:59.71#ibcon#end of sib2, iclass 21, count 2 2006.246.08:25:59.71#ibcon#*mode == 0, iclass 21, count 2 2006.246.08:25:59.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.246.08:25:59.71#ibcon#[25=AT06-07\r\n] 2006.246.08:25:59.71#ibcon#*before write, iclass 21, count 2 2006.246.08:25:59.71#ibcon#enter sib2, iclass 21, count 2 2006.246.08:25:59.71#ibcon#flushed, iclass 21, count 2 2006.246.08:25:59.71#ibcon#about to write, iclass 21, count 2 2006.246.08:25:59.71#ibcon#wrote, iclass 21, count 2 2006.246.08:25:59.71#ibcon#about to read 3, iclass 21, count 2 2006.246.08:25:59.74#ibcon#read 3, iclass 21, count 2 2006.246.08:25:59.74#ibcon#about to read 4, iclass 21, count 2 2006.246.08:25:59.74#ibcon#read 4, iclass 21, count 2 2006.246.08:25:59.74#ibcon#about to read 5, iclass 21, count 2 2006.246.08:25:59.74#ibcon#read 5, iclass 21, count 2 2006.246.08:25:59.74#ibcon#about to read 6, iclass 21, count 2 2006.246.08:25:59.74#ibcon#read 6, iclass 21, count 2 2006.246.08:25:59.74#ibcon#end of sib2, iclass 21, count 2 2006.246.08:25:59.74#ibcon#*after write, iclass 21, count 2 2006.246.08:25:59.74#ibcon#*before return 0, iclass 21, count 2 2006.246.08:25:59.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:25:59.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.246.08:25:59.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.246.08:25:59.74#ibcon#ireg 7 cls_cnt 0 2006.246.08:25:59.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:25:59.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:25:59.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:25:59.86#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:25:59.86#ibcon#first serial, iclass 21, count 0 2006.246.08:25:59.86#ibcon#enter sib2, iclass 21, count 0 2006.246.08:25:59.86#ibcon#flushed, iclass 21, count 0 2006.246.08:25:59.86#ibcon#about to write, iclass 21, count 0 2006.246.08:25:59.86#ibcon#wrote, iclass 21, count 0 2006.246.08:25:59.86#ibcon#about to read 3, iclass 21, count 0 2006.246.08:25:59.88#ibcon#read 3, iclass 21, count 0 2006.246.08:25:59.88#ibcon#about to read 4, iclass 21, count 0 2006.246.08:25:59.88#ibcon#read 4, iclass 21, count 0 2006.246.08:25:59.88#ibcon#about to read 5, iclass 21, count 0 2006.246.08:25:59.88#ibcon#read 5, iclass 21, count 0 2006.246.08:25:59.88#ibcon#about to read 6, iclass 21, count 0 2006.246.08:25:59.88#ibcon#read 6, iclass 21, count 0 2006.246.08:25:59.88#ibcon#end of sib2, iclass 21, count 0 2006.246.08:25:59.88#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:25:59.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:25:59.88#ibcon#[25=USB\r\n] 2006.246.08:25:59.88#ibcon#*before write, iclass 21, count 0 2006.246.08:25:59.88#ibcon#enter sib2, iclass 21, count 0 2006.246.08:25:59.88#ibcon#flushed, iclass 21, count 0 2006.246.08:25:59.88#ibcon#about to write, iclass 21, count 0 2006.246.08:25:59.88#ibcon#wrote, iclass 21, count 0 2006.246.08:25:59.88#ibcon#about to read 3, iclass 21, count 0 2006.246.08:25:59.91#ibcon#read 3, iclass 21, count 0 2006.246.08:25:59.91#ibcon#about to read 4, iclass 21, count 0 2006.246.08:25:59.91#ibcon#read 4, iclass 21, count 0 2006.246.08:25:59.91#ibcon#about to read 5, iclass 21, count 0 2006.246.08:25:59.91#ibcon#read 5, iclass 21, count 0 2006.246.08:25:59.91#ibcon#about to read 6, iclass 21, count 0 2006.246.08:25:59.91#ibcon#read 6, iclass 21, count 0 2006.246.08:25:59.91#ibcon#end of sib2, iclass 21, count 0 2006.246.08:25:59.91#ibcon#*after write, iclass 21, count 0 2006.246.08:25:59.91#ibcon#*before return 0, iclass 21, count 0 2006.246.08:25:59.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:25:59.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.246.08:25:59.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:25:59.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:25:59.91$vc4f8/valo=7,832.99 2006.246.08:25:59.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.246.08:25:59.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.246.08:25:59.91#ibcon#ireg 17 cls_cnt 0 2006.246.08:25:59.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:25:59.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:25:59.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:25:59.91#ibcon#enter wrdev, iclass 23, count 0 2006.246.08:25:59.91#ibcon#first serial, iclass 23, count 0 2006.246.08:25:59.91#ibcon#enter sib2, iclass 23, count 0 2006.246.08:25:59.91#ibcon#flushed, iclass 23, count 0 2006.246.08:25:59.91#ibcon#about to write, iclass 23, count 0 2006.246.08:25:59.91#ibcon#wrote, iclass 23, count 0 2006.246.08:25:59.91#ibcon#about to read 3, iclass 23, count 0 2006.246.08:25:59.93#ibcon#read 3, iclass 23, count 0 2006.246.08:25:59.93#ibcon#about to read 4, iclass 23, count 0 2006.246.08:25:59.93#ibcon#read 4, iclass 23, count 0 2006.246.08:25:59.93#ibcon#about to read 5, iclass 23, count 0 2006.246.08:25:59.93#ibcon#read 5, iclass 23, count 0 2006.246.08:25:59.93#ibcon#about to read 6, iclass 23, count 0 2006.246.08:25:59.93#ibcon#read 6, iclass 23, count 0 2006.246.08:25:59.93#ibcon#end of sib2, iclass 23, count 0 2006.246.08:25:59.93#ibcon#*mode == 0, iclass 23, count 0 2006.246.08:25:59.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.246.08:25:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.246.08:25:59.93#ibcon#*before write, iclass 23, count 0 2006.246.08:25:59.93#ibcon#enter sib2, iclass 23, count 0 2006.246.08:25:59.93#ibcon#flushed, iclass 23, count 0 2006.246.08:25:59.93#ibcon#about to write, iclass 23, count 0 2006.246.08:25:59.93#ibcon#wrote, iclass 23, count 0 2006.246.08:25:59.93#ibcon#about to read 3, iclass 23, count 0 2006.246.08:25:59.97#ibcon#read 3, iclass 23, count 0 2006.246.08:25:59.97#ibcon#about to read 4, iclass 23, count 0 2006.246.08:25:59.97#ibcon#read 4, iclass 23, count 0 2006.246.08:25:59.97#ibcon#about to read 5, iclass 23, count 0 2006.246.08:25:59.97#ibcon#read 5, iclass 23, count 0 2006.246.08:25:59.97#ibcon#about to read 6, iclass 23, count 0 2006.246.08:25:59.97#ibcon#read 6, iclass 23, count 0 2006.246.08:25:59.97#ibcon#end of sib2, iclass 23, count 0 2006.246.08:25:59.97#ibcon#*after write, iclass 23, count 0 2006.246.08:25:59.97#ibcon#*before return 0, iclass 23, count 0 2006.246.08:25:59.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:25:59.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.246.08:25:59.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.246.08:25:59.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.246.08:25:59.97$vc4f8/va=7,7 2006.246.08:25:59.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.246.08:25:59.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.246.08:25:59.97#ibcon#ireg 11 cls_cnt 2 2006.246.08:25:59.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:26:00.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:26:00.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:26:00.03#ibcon#enter wrdev, iclass 25, count 2 2006.246.08:26:00.03#ibcon#first serial, iclass 25, count 2 2006.246.08:26:00.03#ibcon#enter sib2, iclass 25, count 2 2006.246.08:26:00.03#ibcon#flushed, iclass 25, count 2 2006.246.08:26:00.03#ibcon#about to write, iclass 25, count 2 2006.246.08:26:00.03#ibcon#wrote, iclass 25, count 2 2006.246.08:26:00.03#ibcon#about to read 3, iclass 25, count 2 2006.246.08:26:00.05#ibcon#read 3, iclass 25, count 2 2006.246.08:26:00.05#ibcon#about to read 4, iclass 25, count 2 2006.246.08:26:00.05#ibcon#read 4, iclass 25, count 2 2006.246.08:26:00.05#ibcon#about to read 5, iclass 25, count 2 2006.246.08:26:00.05#ibcon#read 5, iclass 25, count 2 2006.246.08:26:00.05#ibcon#about to read 6, iclass 25, count 2 2006.246.08:26:00.05#ibcon#read 6, iclass 25, count 2 2006.246.08:26:00.05#ibcon#end of sib2, iclass 25, count 2 2006.246.08:26:00.05#ibcon#*mode == 0, iclass 25, count 2 2006.246.08:26:00.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.246.08:26:00.05#ibcon#[25=AT07-07\r\n] 2006.246.08:26:00.05#ibcon#*before write, iclass 25, count 2 2006.246.08:26:00.05#ibcon#enter sib2, iclass 25, count 2 2006.246.08:26:00.05#ibcon#flushed, iclass 25, count 2 2006.246.08:26:00.05#ibcon#about to write, iclass 25, count 2 2006.246.08:26:00.05#ibcon#wrote, iclass 25, count 2 2006.246.08:26:00.05#ibcon#about to read 3, iclass 25, count 2 2006.246.08:26:00.08#ibcon#read 3, iclass 25, count 2 2006.246.08:26:00.08#ibcon#about to read 4, iclass 25, count 2 2006.246.08:26:00.08#ibcon#read 4, iclass 25, count 2 2006.246.08:26:00.08#ibcon#about to read 5, iclass 25, count 2 2006.246.08:26:00.08#ibcon#read 5, iclass 25, count 2 2006.246.08:26:00.08#ibcon#about to read 6, iclass 25, count 2 2006.246.08:26:00.08#ibcon#read 6, iclass 25, count 2 2006.246.08:26:00.08#ibcon#end of sib2, iclass 25, count 2 2006.246.08:26:00.08#ibcon#*after write, iclass 25, count 2 2006.246.08:26:00.08#ibcon#*before return 0, iclass 25, count 2 2006.246.08:26:00.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:26:00.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.246.08:26:00.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.246.08:26:00.08#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:00.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:26:00.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:26:00.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:26:00.20#ibcon#enter wrdev, iclass 25, count 0 2006.246.08:26:00.20#ibcon#first serial, iclass 25, count 0 2006.246.08:26:00.20#ibcon#enter sib2, iclass 25, count 0 2006.246.08:26:00.20#ibcon#flushed, iclass 25, count 0 2006.246.08:26:00.20#ibcon#about to write, iclass 25, count 0 2006.246.08:26:00.20#ibcon#wrote, iclass 25, count 0 2006.246.08:26:00.20#ibcon#about to read 3, iclass 25, count 0 2006.246.08:26:00.22#ibcon#read 3, iclass 25, count 0 2006.246.08:26:00.22#ibcon#about to read 4, iclass 25, count 0 2006.246.08:26:00.22#ibcon#read 4, iclass 25, count 0 2006.246.08:26:00.22#ibcon#about to read 5, iclass 25, count 0 2006.246.08:26:00.22#ibcon#read 5, iclass 25, count 0 2006.246.08:26:00.22#ibcon#about to read 6, iclass 25, count 0 2006.246.08:26:00.22#ibcon#read 6, iclass 25, count 0 2006.246.08:26:00.22#ibcon#end of sib2, iclass 25, count 0 2006.246.08:26:00.22#ibcon#*mode == 0, iclass 25, count 0 2006.246.08:26:00.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.246.08:26:00.22#ibcon#[25=USB\r\n] 2006.246.08:26:00.22#ibcon#*before write, iclass 25, count 0 2006.246.08:26:00.22#ibcon#enter sib2, iclass 25, count 0 2006.246.08:26:00.22#ibcon#flushed, iclass 25, count 0 2006.246.08:26:00.22#ibcon#about to write, iclass 25, count 0 2006.246.08:26:00.22#ibcon#wrote, iclass 25, count 0 2006.246.08:26:00.22#ibcon#about to read 3, iclass 25, count 0 2006.246.08:26:00.25#ibcon#read 3, iclass 25, count 0 2006.246.08:26:00.25#ibcon#about to read 4, iclass 25, count 0 2006.246.08:26:00.25#ibcon#read 4, iclass 25, count 0 2006.246.08:26:00.25#ibcon#about to read 5, iclass 25, count 0 2006.246.08:26:00.25#ibcon#read 5, iclass 25, count 0 2006.246.08:26:00.25#ibcon#about to read 6, iclass 25, count 0 2006.246.08:26:00.25#ibcon#read 6, iclass 25, count 0 2006.246.08:26:00.25#ibcon#end of sib2, iclass 25, count 0 2006.246.08:26:00.25#ibcon#*after write, iclass 25, count 0 2006.246.08:26:00.25#ibcon#*before return 0, iclass 25, count 0 2006.246.08:26:00.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:26:00.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.246.08:26:00.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.246.08:26:00.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.246.08:26:00.25$vc4f8/valo=8,852.99 2006.246.08:26:00.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.246.08:26:00.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.246.08:26:00.25#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:00.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:26:00.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:26:00.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:26:00.25#ibcon#enter wrdev, iclass 27, count 0 2006.246.08:26:00.25#ibcon#first serial, iclass 27, count 0 2006.246.08:26:00.25#ibcon#enter sib2, iclass 27, count 0 2006.246.08:26:00.25#ibcon#flushed, iclass 27, count 0 2006.246.08:26:00.25#ibcon#about to write, iclass 27, count 0 2006.246.08:26:00.25#ibcon#wrote, iclass 27, count 0 2006.246.08:26:00.25#ibcon#about to read 3, iclass 27, count 0 2006.246.08:26:00.27#ibcon#read 3, iclass 27, count 0 2006.246.08:26:00.27#ibcon#about to read 4, iclass 27, count 0 2006.246.08:26:00.27#ibcon#read 4, iclass 27, count 0 2006.246.08:26:00.27#ibcon#about to read 5, iclass 27, count 0 2006.246.08:26:00.27#ibcon#read 5, iclass 27, count 0 2006.246.08:26:00.27#ibcon#about to read 6, iclass 27, count 0 2006.246.08:26:00.27#ibcon#read 6, iclass 27, count 0 2006.246.08:26:00.27#ibcon#end of sib2, iclass 27, count 0 2006.246.08:26:00.27#ibcon#*mode == 0, iclass 27, count 0 2006.246.08:26:00.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.246.08:26:00.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.246.08:26:00.27#ibcon#*before write, iclass 27, count 0 2006.246.08:26:00.27#ibcon#enter sib2, iclass 27, count 0 2006.246.08:26:00.27#ibcon#flushed, iclass 27, count 0 2006.246.08:26:00.27#ibcon#about to write, iclass 27, count 0 2006.246.08:26:00.27#ibcon#wrote, iclass 27, count 0 2006.246.08:26:00.27#ibcon#about to read 3, iclass 27, count 0 2006.246.08:26:00.31#ibcon#read 3, iclass 27, count 0 2006.246.08:26:00.31#ibcon#about to read 4, iclass 27, count 0 2006.246.08:26:00.31#ibcon#read 4, iclass 27, count 0 2006.246.08:26:00.31#ibcon#about to read 5, iclass 27, count 0 2006.246.08:26:00.31#ibcon#read 5, iclass 27, count 0 2006.246.08:26:00.31#ibcon#about to read 6, iclass 27, count 0 2006.246.08:26:00.31#ibcon#read 6, iclass 27, count 0 2006.246.08:26:00.31#ibcon#end of sib2, iclass 27, count 0 2006.246.08:26:00.31#ibcon#*after write, iclass 27, count 0 2006.246.08:26:00.31#ibcon#*before return 0, iclass 27, count 0 2006.246.08:26:00.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:26:00.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.246.08:26:00.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.246.08:26:00.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.246.08:26:00.31$vc4f8/va=8,8 2006.246.08:26:00.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.246.08:26:00.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.246.08:26:00.31#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:00.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:26:00.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:26:00.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:26:00.37#ibcon#enter wrdev, iclass 29, count 2 2006.246.08:26:00.37#ibcon#first serial, iclass 29, count 2 2006.246.08:26:00.37#ibcon#enter sib2, iclass 29, count 2 2006.246.08:26:00.37#ibcon#flushed, iclass 29, count 2 2006.246.08:26:00.37#ibcon#about to write, iclass 29, count 2 2006.246.08:26:00.37#ibcon#wrote, iclass 29, count 2 2006.246.08:26:00.37#ibcon#about to read 3, iclass 29, count 2 2006.246.08:26:00.39#ibcon#read 3, iclass 29, count 2 2006.246.08:26:00.39#ibcon#about to read 4, iclass 29, count 2 2006.246.08:26:00.39#ibcon#read 4, iclass 29, count 2 2006.246.08:26:00.39#ibcon#about to read 5, iclass 29, count 2 2006.246.08:26:00.39#ibcon#read 5, iclass 29, count 2 2006.246.08:26:00.39#ibcon#about to read 6, iclass 29, count 2 2006.246.08:26:00.39#ibcon#read 6, iclass 29, count 2 2006.246.08:26:00.39#ibcon#end of sib2, iclass 29, count 2 2006.246.08:26:00.39#ibcon#*mode == 0, iclass 29, count 2 2006.246.08:26:00.39#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.246.08:26:00.39#ibcon#[25=AT08-08\r\n] 2006.246.08:26:00.39#ibcon#*before write, iclass 29, count 2 2006.246.08:26:00.39#ibcon#enter sib2, iclass 29, count 2 2006.246.08:26:00.39#ibcon#flushed, iclass 29, count 2 2006.246.08:26:00.39#ibcon#about to write, iclass 29, count 2 2006.246.08:26:00.39#ibcon#wrote, iclass 29, count 2 2006.246.08:26:00.39#ibcon#about to read 3, iclass 29, count 2 2006.246.08:26:00.42#ibcon#read 3, iclass 29, count 2 2006.246.08:26:00.42#ibcon#about to read 4, iclass 29, count 2 2006.246.08:26:00.42#ibcon#read 4, iclass 29, count 2 2006.246.08:26:00.42#ibcon#about to read 5, iclass 29, count 2 2006.246.08:26:00.42#ibcon#read 5, iclass 29, count 2 2006.246.08:26:00.42#ibcon#about to read 6, iclass 29, count 2 2006.246.08:26:00.42#ibcon#read 6, iclass 29, count 2 2006.246.08:26:00.42#ibcon#end of sib2, iclass 29, count 2 2006.246.08:26:00.42#ibcon#*after write, iclass 29, count 2 2006.246.08:26:00.42#ibcon#*before return 0, iclass 29, count 2 2006.246.08:26:00.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:26:00.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.246.08:26:00.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.246.08:26:00.42#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:00.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:26:00.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:26:00.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:26:00.54#ibcon#enter wrdev, iclass 29, count 0 2006.246.08:26:00.54#ibcon#first serial, iclass 29, count 0 2006.246.08:26:00.54#ibcon#enter sib2, iclass 29, count 0 2006.246.08:26:00.54#ibcon#flushed, iclass 29, count 0 2006.246.08:26:00.54#ibcon#about to write, iclass 29, count 0 2006.246.08:26:00.54#ibcon#wrote, iclass 29, count 0 2006.246.08:26:00.54#ibcon#about to read 3, iclass 29, count 0 2006.246.08:26:00.56#ibcon#read 3, iclass 29, count 0 2006.246.08:26:00.56#ibcon#about to read 4, iclass 29, count 0 2006.246.08:26:00.56#ibcon#read 4, iclass 29, count 0 2006.246.08:26:00.56#ibcon#about to read 5, iclass 29, count 0 2006.246.08:26:00.56#ibcon#read 5, iclass 29, count 0 2006.246.08:26:00.56#ibcon#about to read 6, iclass 29, count 0 2006.246.08:26:00.56#ibcon#read 6, iclass 29, count 0 2006.246.08:26:00.56#ibcon#end of sib2, iclass 29, count 0 2006.246.08:26:00.56#ibcon#*mode == 0, iclass 29, count 0 2006.246.08:26:00.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.246.08:26:00.56#ibcon#[25=USB\r\n] 2006.246.08:26:00.56#ibcon#*before write, iclass 29, count 0 2006.246.08:26:00.56#ibcon#enter sib2, iclass 29, count 0 2006.246.08:26:00.56#ibcon#flushed, iclass 29, count 0 2006.246.08:26:00.56#ibcon#about to write, iclass 29, count 0 2006.246.08:26:00.56#ibcon#wrote, iclass 29, count 0 2006.246.08:26:00.56#ibcon#about to read 3, iclass 29, count 0 2006.246.08:26:00.59#ibcon#read 3, iclass 29, count 0 2006.246.08:26:00.59#ibcon#about to read 4, iclass 29, count 0 2006.246.08:26:00.59#ibcon#read 4, iclass 29, count 0 2006.246.08:26:00.59#ibcon#about to read 5, iclass 29, count 0 2006.246.08:26:00.59#ibcon#read 5, iclass 29, count 0 2006.246.08:26:00.59#ibcon#about to read 6, iclass 29, count 0 2006.246.08:26:00.59#ibcon#read 6, iclass 29, count 0 2006.246.08:26:00.59#ibcon#end of sib2, iclass 29, count 0 2006.246.08:26:00.59#ibcon#*after write, iclass 29, count 0 2006.246.08:26:00.59#ibcon#*before return 0, iclass 29, count 0 2006.246.08:26:00.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:26:00.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.246.08:26:00.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.246.08:26:00.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.246.08:26:00.59$vc4f8/vblo=1,632.99 2006.246.08:26:00.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.246.08:26:00.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.246.08:26:00.59#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:00.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:26:00.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:26:00.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:26:00.59#ibcon#enter wrdev, iclass 31, count 0 2006.246.08:26:00.59#ibcon#first serial, iclass 31, count 0 2006.246.08:26:00.59#ibcon#enter sib2, iclass 31, count 0 2006.246.08:26:00.59#ibcon#flushed, iclass 31, count 0 2006.246.08:26:00.59#ibcon#about to write, iclass 31, count 0 2006.246.08:26:00.59#ibcon#wrote, iclass 31, count 0 2006.246.08:26:00.59#ibcon#about to read 3, iclass 31, count 0 2006.246.08:26:00.61#ibcon#read 3, iclass 31, count 0 2006.246.08:26:00.61#ibcon#about to read 4, iclass 31, count 0 2006.246.08:26:00.61#ibcon#read 4, iclass 31, count 0 2006.246.08:26:00.61#ibcon#about to read 5, iclass 31, count 0 2006.246.08:26:00.61#ibcon#read 5, iclass 31, count 0 2006.246.08:26:00.61#ibcon#about to read 6, iclass 31, count 0 2006.246.08:26:00.61#ibcon#read 6, iclass 31, count 0 2006.246.08:26:00.61#ibcon#end of sib2, iclass 31, count 0 2006.246.08:26:00.61#ibcon#*mode == 0, iclass 31, count 0 2006.246.08:26:00.61#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.246.08:26:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.246.08:26:00.61#ibcon#*before write, iclass 31, count 0 2006.246.08:26:00.61#ibcon#enter sib2, iclass 31, count 0 2006.246.08:26:00.61#ibcon#flushed, iclass 31, count 0 2006.246.08:26:00.61#ibcon#about to write, iclass 31, count 0 2006.246.08:26:00.61#ibcon#wrote, iclass 31, count 0 2006.246.08:26:00.61#ibcon#about to read 3, iclass 31, count 0 2006.246.08:26:00.65#ibcon#read 3, iclass 31, count 0 2006.246.08:26:00.65#ibcon#about to read 4, iclass 31, count 0 2006.246.08:26:00.65#ibcon#read 4, iclass 31, count 0 2006.246.08:26:00.65#ibcon#about to read 5, iclass 31, count 0 2006.246.08:26:00.65#ibcon#read 5, iclass 31, count 0 2006.246.08:26:00.65#ibcon#about to read 6, iclass 31, count 0 2006.246.08:26:00.65#ibcon#read 6, iclass 31, count 0 2006.246.08:26:00.65#ibcon#end of sib2, iclass 31, count 0 2006.246.08:26:00.65#ibcon#*after write, iclass 31, count 0 2006.246.08:26:00.65#ibcon#*before return 0, iclass 31, count 0 2006.246.08:26:00.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:26:00.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.246.08:26:00.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.246.08:26:00.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.246.08:26:00.65$vc4f8/vb=1,4 2006.246.08:26:00.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.246.08:26:00.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.246.08:26:00.65#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:00.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:26:00.65#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:26:00.65#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:26:00.65#ibcon#enter wrdev, iclass 33, count 2 2006.246.08:26:00.65#ibcon#first serial, iclass 33, count 2 2006.246.08:26:00.65#ibcon#enter sib2, iclass 33, count 2 2006.246.08:26:00.65#ibcon#flushed, iclass 33, count 2 2006.246.08:26:00.65#ibcon#about to write, iclass 33, count 2 2006.246.08:26:00.65#ibcon#wrote, iclass 33, count 2 2006.246.08:26:00.65#ibcon#about to read 3, iclass 33, count 2 2006.246.08:26:00.67#ibcon#read 3, iclass 33, count 2 2006.246.08:26:00.67#ibcon#about to read 4, iclass 33, count 2 2006.246.08:26:00.67#ibcon#read 4, iclass 33, count 2 2006.246.08:26:00.67#ibcon#about to read 5, iclass 33, count 2 2006.246.08:26:00.67#ibcon#read 5, iclass 33, count 2 2006.246.08:26:00.67#ibcon#about to read 6, iclass 33, count 2 2006.246.08:26:00.67#ibcon#read 6, iclass 33, count 2 2006.246.08:26:00.67#ibcon#end of sib2, iclass 33, count 2 2006.246.08:26:00.67#ibcon#*mode == 0, iclass 33, count 2 2006.246.08:26:00.67#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.246.08:26:00.67#ibcon#[27=AT01-04\r\n] 2006.246.08:26:00.67#ibcon#*before write, iclass 33, count 2 2006.246.08:26:00.67#ibcon#enter sib2, iclass 33, count 2 2006.246.08:26:00.67#ibcon#flushed, iclass 33, count 2 2006.246.08:26:00.67#ibcon#about to write, iclass 33, count 2 2006.246.08:26:00.67#ibcon#wrote, iclass 33, count 2 2006.246.08:26:00.67#ibcon#about to read 3, iclass 33, count 2 2006.246.08:26:00.70#ibcon#read 3, iclass 33, count 2 2006.246.08:26:00.70#ibcon#about to read 4, iclass 33, count 2 2006.246.08:26:00.70#ibcon#read 4, iclass 33, count 2 2006.246.08:26:00.70#ibcon#about to read 5, iclass 33, count 2 2006.246.08:26:00.70#ibcon#read 5, iclass 33, count 2 2006.246.08:26:00.70#ibcon#about to read 6, iclass 33, count 2 2006.246.08:26:00.70#ibcon#read 6, iclass 33, count 2 2006.246.08:26:00.70#ibcon#end of sib2, iclass 33, count 2 2006.246.08:26:00.70#ibcon#*after write, iclass 33, count 2 2006.246.08:26:00.70#ibcon#*before return 0, iclass 33, count 2 2006.246.08:26:00.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:26:00.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.246.08:26:00.70#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.246.08:26:00.70#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:00.70#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:26:00.82#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:26:00.82#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:26:00.82#ibcon#enter wrdev, iclass 33, count 0 2006.246.08:26:00.82#ibcon#first serial, iclass 33, count 0 2006.246.08:26:00.82#ibcon#enter sib2, iclass 33, count 0 2006.246.08:26:00.82#ibcon#flushed, iclass 33, count 0 2006.246.08:26:00.82#ibcon#about to write, iclass 33, count 0 2006.246.08:26:00.82#ibcon#wrote, iclass 33, count 0 2006.246.08:26:00.82#ibcon#about to read 3, iclass 33, count 0 2006.246.08:26:00.84#ibcon#read 3, iclass 33, count 0 2006.246.08:26:00.84#ibcon#about to read 4, iclass 33, count 0 2006.246.08:26:00.84#ibcon#read 4, iclass 33, count 0 2006.246.08:26:00.84#ibcon#about to read 5, iclass 33, count 0 2006.246.08:26:00.84#ibcon#read 5, iclass 33, count 0 2006.246.08:26:00.84#ibcon#about to read 6, iclass 33, count 0 2006.246.08:26:00.84#ibcon#read 6, iclass 33, count 0 2006.246.08:26:00.84#ibcon#end of sib2, iclass 33, count 0 2006.246.08:26:00.84#ibcon#*mode == 0, iclass 33, count 0 2006.246.08:26:00.84#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.246.08:26:00.84#ibcon#[27=USB\r\n] 2006.246.08:26:00.84#ibcon#*before write, iclass 33, count 0 2006.246.08:26:00.84#ibcon#enter sib2, iclass 33, count 0 2006.246.08:26:00.84#ibcon#flushed, iclass 33, count 0 2006.246.08:26:00.84#ibcon#about to write, iclass 33, count 0 2006.246.08:26:00.84#ibcon#wrote, iclass 33, count 0 2006.246.08:26:00.84#ibcon#about to read 3, iclass 33, count 0 2006.246.08:26:00.87#ibcon#read 3, iclass 33, count 0 2006.246.08:26:00.87#ibcon#about to read 4, iclass 33, count 0 2006.246.08:26:00.87#ibcon#read 4, iclass 33, count 0 2006.246.08:26:00.87#ibcon#about to read 5, iclass 33, count 0 2006.246.08:26:00.87#ibcon#read 5, iclass 33, count 0 2006.246.08:26:00.87#ibcon#about to read 6, iclass 33, count 0 2006.246.08:26:00.87#ibcon#read 6, iclass 33, count 0 2006.246.08:26:00.87#ibcon#end of sib2, iclass 33, count 0 2006.246.08:26:00.87#ibcon#*after write, iclass 33, count 0 2006.246.08:26:00.87#ibcon#*before return 0, iclass 33, count 0 2006.246.08:26:00.87#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:26:00.87#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.246.08:26:00.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.246.08:26:00.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.246.08:26:00.87$vc4f8/vblo=2,640.99 2006.246.08:26:00.87#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.246.08:26:00.87#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.246.08:26:00.87#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:00.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:26:00.87#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:26:00.87#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:26:00.87#ibcon#enter wrdev, iclass 35, count 0 2006.246.08:26:00.87#ibcon#first serial, iclass 35, count 0 2006.246.08:26:00.87#ibcon#enter sib2, iclass 35, count 0 2006.246.08:26:00.87#ibcon#flushed, iclass 35, count 0 2006.246.08:26:00.87#ibcon#about to write, iclass 35, count 0 2006.246.08:26:00.87#ibcon#wrote, iclass 35, count 0 2006.246.08:26:00.87#ibcon#about to read 3, iclass 35, count 0 2006.246.08:26:00.89#ibcon#read 3, iclass 35, count 0 2006.246.08:26:00.89#ibcon#about to read 4, iclass 35, count 0 2006.246.08:26:00.89#ibcon#read 4, iclass 35, count 0 2006.246.08:26:00.89#ibcon#about to read 5, iclass 35, count 0 2006.246.08:26:00.89#ibcon#read 5, iclass 35, count 0 2006.246.08:26:00.89#ibcon#about to read 6, iclass 35, count 0 2006.246.08:26:00.89#ibcon#read 6, iclass 35, count 0 2006.246.08:26:00.89#ibcon#end of sib2, iclass 35, count 0 2006.246.08:26:00.89#ibcon#*mode == 0, iclass 35, count 0 2006.246.08:26:00.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.246.08:26:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.246.08:26:00.89#ibcon#*before write, iclass 35, count 0 2006.246.08:26:00.89#ibcon#enter sib2, iclass 35, count 0 2006.246.08:26:00.89#ibcon#flushed, iclass 35, count 0 2006.246.08:26:00.89#ibcon#about to write, iclass 35, count 0 2006.246.08:26:00.89#ibcon#wrote, iclass 35, count 0 2006.246.08:26:00.89#ibcon#about to read 3, iclass 35, count 0 2006.246.08:26:00.93#ibcon#read 3, iclass 35, count 0 2006.246.08:26:00.93#ibcon#about to read 4, iclass 35, count 0 2006.246.08:26:00.93#ibcon#read 4, iclass 35, count 0 2006.246.08:26:00.93#ibcon#about to read 5, iclass 35, count 0 2006.246.08:26:00.93#ibcon#read 5, iclass 35, count 0 2006.246.08:26:00.93#ibcon#about to read 6, iclass 35, count 0 2006.246.08:26:00.93#ibcon#read 6, iclass 35, count 0 2006.246.08:26:00.93#ibcon#end of sib2, iclass 35, count 0 2006.246.08:26:00.93#ibcon#*after write, iclass 35, count 0 2006.246.08:26:00.93#ibcon#*before return 0, iclass 35, count 0 2006.246.08:26:00.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:26:00.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.246.08:26:00.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.246.08:26:00.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.246.08:26:00.93$vc4f8/vb=2,4 2006.246.08:26:00.93#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.246.08:26:00.93#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.246.08:26:00.93#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:00.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:26:00.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:26:00.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:26:00.99#ibcon#enter wrdev, iclass 37, count 2 2006.246.08:26:00.99#ibcon#first serial, iclass 37, count 2 2006.246.08:26:00.99#ibcon#enter sib2, iclass 37, count 2 2006.246.08:26:00.99#ibcon#flushed, iclass 37, count 2 2006.246.08:26:00.99#ibcon#about to write, iclass 37, count 2 2006.246.08:26:00.99#ibcon#wrote, iclass 37, count 2 2006.246.08:26:00.99#ibcon#about to read 3, iclass 37, count 2 2006.246.08:26:01.01#ibcon#read 3, iclass 37, count 2 2006.246.08:26:01.01#ibcon#about to read 4, iclass 37, count 2 2006.246.08:26:01.01#ibcon#read 4, iclass 37, count 2 2006.246.08:26:01.01#ibcon#about to read 5, iclass 37, count 2 2006.246.08:26:01.01#ibcon#read 5, iclass 37, count 2 2006.246.08:26:01.01#ibcon#about to read 6, iclass 37, count 2 2006.246.08:26:01.01#ibcon#read 6, iclass 37, count 2 2006.246.08:26:01.01#ibcon#end of sib2, iclass 37, count 2 2006.246.08:26:01.01#ibcon#*mode == 0, iclass 37, count 2 2006.246.08:26:01.01#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.246.08:26:01.01#ibcon#[27=AT02-04\r\n] 2006.246.08:26:01.01#ibcon#*before write, iclass 37, count 2 2006.246.08:26:01.01#ibcon#enter sib2, iclass 37, count 2 2006.246.08:26:01.01#ibcon#flushed, iclass 37, count 2 2006.246.08:26:01.01#ibcon#about to write, iclass 37, count 2 2006.246.08:26:01.01#ibcon#wrote, iclass 37, count 2 2006.246.08:26:01.01#ibcon#about to read 3, iclass 37, count 2 2006.246.08:26:01.04#ibcon#read 3, iclass 37, count 2 2006.246.08:26:01.04#ibcon#about to read 4, iclass 37, count 2 2006.246.08:26:01.04#ibcon#read 4, iclass 37, count 2 2006.246.08:26:01.04#ibcon#about to read 5, iclass 37, count 2 2006.246.08:26:01.04#ibcon#read 5, iclass 37, count 2 2006.246.08:26:01.04#ibcon#about to read 6, iclass 37, count 2 2006.246.08:26:01.04#ibcon#read 6, iclass 37, count 2 2006.246.08:26:01.04#ibcon#end of sib2, iclass 37, count 2 2006.246.08:26:01.04#ibcon#*after write, iclass 37, count 2 2006.246.08:26:01.04#ibcon#*before return 0, iclass 37, count 2 2006.246.08:26:01.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:26:01.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.246.08:26:01.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.246.08:26:01.04#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:01.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:26:01.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:26:01.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:26:01.16#ibcon#enter wrdev, iclass 37, count 0 2006.246.08:26:01.16#ibcon#first serial, iclass 37, count 0 2006.246.08:26:01.16#ibcon#enter sib2, iclass 37, count 0 2006.246.08:26:01.16#ibcon#flushed, iclass 37, count 0 2006.246.08:26:01.16#ibcon#about to write, iclass 37, count 0 2006.246.08:26:01.16#ibcon#wrote, iclass 37, count 0 2006.246.08:26:01.16#ibcon#about to read 3, iclass 37, count 0 2006.246.08:26:01.18#ibcon#read 3, iclass 37, count 0 2006.246.08:26:01.18#ibcon#about to read 4, iclass 37, count 0 2006.246.08:26:01.18#ibcon#read 4, iclass 37, count 0 2006.246.08:26:01.18#ibcon#about to read 5, iclass 37, count 0 2006.246.08:26:01.18#ibcon#read 5, iclass 37, count 0 2006.246.08:26:01.18#ibcon#about to read 6, iclass 37, count 0 2006.246.08:26:01.18#ibcon#read 6, iclass 37, count 0 2006.246.08:26:01.18#ibcon#end of sib2, iclass 37, count 0 2006.246.08:26:01.18#ibcon#*mode == 0, iclass 37, count 0 2006.246.08:26:01.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.246.08:26:01.18#ibcon#[27=USB\r\n] 2006.246.08:26:01.18#ibcon#*before write, iclass 37, count 0 2006.246.08:26:01.18#ibcon#enter sib2, iclass 37, count 0 2006.246.08:26:01.18#ibcon#flushed, iclass 37, count 0 2006.246.08:26:01.18#ibcon#about to write, iclass 37, count 0 2006.246.08:26:01.18#ibcon#wrote, iclass 37, count 0 2006.246.08:26:01.18#ibcon#about to read 3, iclass 37, count 0 2006.246.08:26:01.21#ibcon#read 3, iclass 37, count 0 2006.246.08:26:01.21#ibcon#about to read 4, iclass 37, count 0 2006.246.08:26:01.21#ibcon#read 4, iclass 37, count 0 2006.246.08:26:01.21#ibcon#about to read 5, iclass 37, count 0 2006.246.08:26:01.21#ibcon#read 5, iclass 37, count 0 2006.246.08:26:01.21#ibcon#about to read 6, iclass 37, count 0 2006.246.08:26:01.21#ibcon#read 6, iclass 37, count 0 2006.246.08:26:01.21#ibcon#end of sib2, iclass 37, count 0 2006.246.08:26:01.21#ibcon#*after write, iclass 37, count 0 2006.246.08:26:01.21#ibcon#*before return 0, iclass 37, count 0 2006.246.08:26:01.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:26:01.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.246.08:26:01.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.246.08:26:01.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.246.08:26:01.21$vc4f8/vblo=3,656.99 2006.246.08:26:01.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.246.08:26:01.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.246.08:26:01.21#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:01.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:26:01.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:26:01.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:26:01.21#ibcon#enter wrdev, iclass 39, count 0 2006.246.08:26:01.21#ibcon#first serial, iclass 39, count 0 2006.246.08:26:01.21#ibcon#enter sib2, iclass 39, count 0 2006.246.08:26:01.21#ibcon#flushed, iclass 39, count 0 2006.246.08:26:01.21#ibcon#about to write, iclass 39, count 0 2006.246.08:26:01.21#ibcon#wrote, iclass 39, count 0 2006.246.08:26:01.21#ibcon#about to read 3, iclass 39, count 0 2006.246.08:26:01.23#ibcon#read 3, iclass 39, count 0 2006.246.08:26:01.23#ibcon#about to read 4, iclass 39, count 0 2006.246.08:26:01.23#ibcon#read 4, iclass 39, count 0 2006.246.08:26:01.23#ibcon#about to read 5, iclass 39, count 0 2006.246.08:26:01.23#ibcon#read 5, iclass 39, count 0 2006.246.08:26:01.23#ibcon#about to read 6, iclass 39, count 0 2006.246.08:26:01.23#ibcon#read 6, iclass 39, count 0 2006.246.08:26:01.23#ibcon#end of sib2, iclass 39, count 0 2006.246.08:26:01.23#ibcon#*mode == 0, iclass 39, count 0 2006.246.08:26:01.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.246.08:26:01.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.246.08:26:01.23#ibcon#*before write, iclass 39, count 0 2006.246.08:26:01.23#ibcon#enter sib2, iclass 39, count 0 2006.246.08:26:01.23#ibcon#flushed, iclass 39, count 0 2006.246.08:26:01.23#ibcon#about to write, iclass 39, count 0 2006.246.08:26:01.23#ibcon#wrote, iclass 39, count 0 2006.246.08:26:01.23#ibcon#about to read 3, iclass 39, count 0 2006.246.08:26:01.27#ibcon#read 3, iclass 39, count 0 2006.246.08:26:01.27#ibcon#about to read 4, iclass 39, count 0 2006.246.08:26:01.27#ibcon#read 4, iclass 39, count 0 2006.246.08:26:01.27#ibcon#about to read 5, iclass 39, count 0 2006.246.08:26:01.27#ibcon#read 5, iclass 39, count 0 2006.246.08:26:01.27#ibcon#about to read 6, iclass 39, count 0 2006.246.08:26:01.27#ibcon#read 6, iclass 39, count 0 2006.246.08:26:01.27#ibcon#end of sib2, iclass 39, count 0 2006.246.08:26:01.27#ibcon#*after write, iclass 39, count 0 2006.246.08:26:01.27#ibcon#*before return 0, iclass 39, count 0 2006.246.08:26:01.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:26:01.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.246.08:26:01.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.246.08:26:01.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.246.08:26:01.27$vc4f8/vb=3,4 2006.246.08:26:01.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.246.08:26:01.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.246.08:26:01.27#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:01.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:26:01.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:26:01.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:26:01.33#ibcon#enter wrdev, iclass 3, count 2 2006.246.08:26:01.33#ibcon#first serial, iclass 3, count 2 2006.246.08:26:01.33#ibcon#enter sib2, iclass 3, count 2 2006.246.08:26:01.33#ibcon#flushed, iclass 3, count 2 2006.246.08:26:01.33#ibcon#about to write, iclass 3, count 2 2006.246.08:26:01.33#ibcon#wrote, iclass 3, count 2 2006.246.08:26:01.33#ibcon#about to read 3, iclass 3, count 2 2006.246.08:26:01.35#ibcon#read 3, iclass 3, count 2 2006.246.08:26:01.35#ibcon#about to read 4, iclass 3, count 2 2006.246.08:26:01.35#ibcon#read 4, iclass 3, count 2 2006.246.08:26:01.35#ibcon#about to read 5, iclass 3, count 2 2006.246.08:26:01.35#ibcon#read 5, iclass 3, count 2 2006.246.08:26:01.35#ibcon#about to read 6, iclass 3, count 2 2006.246.08:26:01.35#ibcon#read 6, iclass 3, count 2 2006.246.08:26:01.35#ibcon#end of sib2, iclass 3, count 2 2006.246.08:26:01.35#ibcon#*mode == 0, iclass 3, count 2 2006.246.08:26:01.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.246.08:26:01.35#ibcon#[27=AT03-04\r\n] 2006.246.08:26:01.35#ibcon#*before write, iclass 3, count 2 2006.246.08:26:01.35#ibcon#enter sib2, iclass 3, count 2 2006.246.08:26:01.35#ibcon#flushed, iclass 3, count 2 2006.246.08:26:01.35#ibcon#about to write, iclass 3, count 2 2006.246.08:26:01.35#ibcon#wrote, iclass 3, count 2 2006.246.08:26:01.35#ibcon#about to read 3, iclass 3, count 2 2006.246.08:26:01.38#ibcon#read 3, iclass 3, count 2 2006.246.08:26:01.38#ibcon#about to read 4, iclass 3, count 2 2006.246.08:26:01.38#ibcon#read 4, iclass 3, count 2 2006.246.08:26:01.38#ibcon#about to read 5, iclass 3, count 2 2006.246.08:26:01.38#ibcon#read 5, iclass 3, count 2 2006.246.08:26:01.38#ibcon#about to read 6, iclass 3, count 2 2006.246.08:26:01.38#ibcon#read 6, iclass 3, count 2 2006.246.08:26:01.38#ibcon#end of sib2, iclass 3, count 2 2006.246.08:26:01.38#ibcon#*after write, iclass 3, count 2 2006.246.08:26:01.38#ibcon#*before return 0, iclass 3, count 2 2006.246.08:26:01.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:26:01.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.246.08:26:01.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.246.08:26:01.38#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:01.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:26:01.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:26:01.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:26:01.50#ibcon#enter wrdev, iclass 3, count 0 2006.246.08:26:01.50#ibcon#first serial, iclass 3, count 0 2006.246.08:26:01.50#ibcon#enter sib2, iclass 3, count 0 2006.246.08:26:01.50#ibcon#flushed, iclass 3, count 0 2006.246.08:26:01.50#ibcon#about to write, iclass 3, count 0 2006.246.08:26:01.50#ibcon#wrote, iclass 3, count 0 2006.246.08:26:01.50#ibcon#about to read 3, iclass 3, count 0 2006.246.08:26:01.52#ibcon#read 3, iclass 3, count 0 2006.246.08:26:01.52#ibcon#about to read 4, iclass 3, count 0 2006.246.08:26:01.52#ibcon#read 4, iclass 3, count 0 2006.246.08:26:01.52#ibcon#about to read 5, iclass 3, count 0 2006.246.08:26:01.52#ibcon#read 5, iclass 3, count 0 2006.246.08:26:01.52#ibcon#about to read 6, iclass 3, count 0 2006.246.08:26:01.52#ibcon#read 6, iclass 3, count 0 2006.246.08:26:01.52#ibcon#end of sib2, iclass 3, count 0 2006.246.08:26:01.52#ibcon#*mode == 0, iclass 3, count 0 2006.246.08:26:01.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.246.08:26:01.52#ibcon#[27=USB\r\n] 2006.246.08:26:01.52#ibcon#*before write, iclass 3, count 0 2006.246.08:26:01.52#ibcon#enter sib2, iclass 3, count 0 2006.246.08:26:01.52#ibcon#flushed, iclass 3, count 0 2006.246.08:26:01.52#ibcon#about to write, iclass 3, count 0 2006.246.08:26:01.52#ibcon#wrote, iclass 3, count 0 2006.246.08:26:01.52#ibcon#about to read 3, iclass 3, count 0 2006.246.08:26:01.55#ibcon#read 3, iclass 3, count 0 2006.246.08:26:01.55#ibcon#about to read 4, iclass 3, count 0 2006.246.08:26:01.55#ibcon#read 4, iclass 3, count 0 2006.246.08:26:01.55#ibcon#about to read 5, iclass 3, count 0 2006.246.08:26:01.55#ibcon#read 5, iclass 3, count 0 2006.246.08:26:01.55#ibcon#about to read 6, iclass 3, count 0 2006.246.08:26:01.55#ibcon#read 6, iclass 3, count 0 2006.246.08:26:01.55#ibcon#end of sib2, iclass 3, count 0 2006.246.08:26:01.55#ibcon#*after write, iclass 3, count 0 2006.246.08:26:01.55#ibcon#*before return 0, iclass 3, count 0 2006.246.08:26:01.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:26:01.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.246.08:26:01.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.246.08:26:01.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.246.08:26:01.55$vc4f8/vblo=4,712.99 2006.246.08:26:01.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.246.08:26:01.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.246.08:26:01.55#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:01.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:26:01.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:26:01.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:26:01.55#ibcon#enter wrdev, iclass 5, count 0 2006.246.08:26:01.55#ibcon#first serial, iclass 5, count 0 2006.246.08:26:01.55#ibcon#enter sib2, iclass 5, count 0 2006.246.08:26:01.55#ibcon#flushed, iclass 5, count 0 2006.246.08:26:01.55#ibcon#about to write, iclass 5, count 0 2006.246.08:26:01.55#ibcon#wrote, iclass 5, count 0 2006.246.08:26:01.55#ibcon#about to read 3, iclass 5, count 0 2006.246.08:26:01.57#ibcon#read 3, iclass 5, count 0 2006.246.08:26:01.57#ibcon#about to read 4, iclass 5, count 0 2006.246.08:26:01.57#ibcon#read 4, iclass 5, count 0 2006.246.08:26:01.57#ibcon#about to read 5, iclass 5, count 0 2006.246.08:26:01.57#ibcon#read 5, iclass 5, count 0 2006.246.08:26:01.57#ibcon#about to read 6, iclass 5, count 0 2006.246.08:26:01.57#ibcon#read 6, iclass 5, count 0 2006.246.08:26:01.57#ibcon#end of sib2, iclass 5, count 0 2006.246.08:26:01.57#ibcon#*mode == 0, iclass 5, count 0 2006.246.08:26:01.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.246.08:26:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.246.08:26:01.57#ibcon#*before write, iclass 5, count 0 2006.246.08:26:01.57#ibcon#enter sib2, iclass 5, count 0 2006.246.08:26:01.57#ibcon#flushed, iclass 5, count 0 2006.246.08:26:01.57#ibcon#about to write, iclass 5, count 0 2006.246.08:26:01.57#ibcon#wrote, iclass 5, count 0 2006.246.08:26:01.57#ibcon#about to read 3, iclass 5, count 0 2006.246.08:26:01.61#ibcon#read 3, iclass 5, count 0 2006.246.08:26:01.61#ibcon#about to read 4, iclass 5, count 0 2006.246.08:26:01.61#ibcon#read 4, iclass 5, count 0 2006.246.08:26:01.61#ibcon#about to read 5, iclass 5, count 0 2006.246.08:26:01.61#ibcon#read 5, iclass 5, count 0 2006.246.08:26:01.61#ibcon#about to read 6, iclass 5, count 0 2006.246.08:26:01.61#ibcon#read 6, iclass 5, count 0 2006.246.08:26:01.61#ibcon#end of sib2, iclass 5, count 0 2006.246.08:26:01.61#ibcon#*after write, iclass 5, count 0 2006.246.08:26:01.61#ibcon#*before return 0, iclass 5, count 0 2006.246.08:26:01.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:26:01.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.246.08:26:01.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.246.08:26:01.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.246.08:26:01.61$vc4f8/vb=4,4 2006.246.08:26:01.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.246.08:26:01.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.246.08:26:01.61#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:01.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:26:01.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:26:01.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:26:01.67#ibcon#enter wrdev, iclass 7, count 2 2006.246.08:26:01.67#ibcon#first serial, iclass 7, count 2 2006.246.08:26:01.67#ibcon#enter sib2, iclass 7, count 2 2006.246.08:26:01.67#ibcon#flushed, iclass 7, count 2 2006.246.08:26:01.67#ibcon#about to write, iclass 7, count 2 2006.246.08:26:01.67#ibcon#wrote, iclass 7, count 2 2006.246.08:26:01.67#ibcon#about to read 3, iclass 7, count 2 2006.246.08:26:01.69#ibcon#read 3, iclass 7, count 2 2006.246.08:26:01.69#ibcon#about to read 4, iclass 7, count 2 2006.246.08:26:01.69#ibcon#read 4, iclass 7, count 2 2006.246.08:26:01.69#ibcon#about to read 5, iclass 7, count 2 2006.246.08:26:01.69#ibcon#read 5, iclass 7, count 2 2006.246.08:26:01.69#ibcon#about to read 6, iclass 7, count 2 2006.246.08:26:01.69#ibcon#read 6, iclass 7, count 2 2006.246.08:26:01.69#ibcon#end of sib2, iclass 7, count 2 2006.246.08:26:01.69#ibcon#*mode == 0, iclass 7, count 2 2006.246.08:26:01.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.246.08:26:01.69#ibcon#[27=AT04-04\r\n] 2006.246.08:26:01.69#ibcon#*before write, iclass 7, count 2 2006.246.08:26:01.69#ibcon#enter sib2, iclass 7, count 2 2006.246.08:26:01.69#ibcon#flushed, iclass 7, count 2 2006.246.08:26:01.69#ibcon#about to write, iclass 7, count 2 2006.246.08:26:01.69#ibcon#wrote, iclass 7, count 2 2006.246.08:26:01.69#ibcon#about to read 3, iclass 7, count 2 2006.246.08:26:01.72#ibcon#read 3, iclass 7, count 2 2006.246.08:26:01.72#ibcon#about to read 4, iclass 7, count 2 2006.246.08:26:01.72#ibcon#read 4, iclass 7, count 2 2006.246.08:26:01.72#ibcon#about to read 5, iclass 7, count 2 2006.246.08:26:01.72#ibcon#read 5, iclass 7, count 2 2006.246.08:26:01.72#ibcon#about to read 6, iclass 7, count 2 2006.246.08:26:01.72#ibcon#read 6, iclass 7, count 2 2006.246.08:26:01.72#ibcon#end of sib2, iclass 7, count 2 2006.246.08:26:01.72#ibcon#*after write, iclass 7, count 2 2006.246.08:26:01.72#ibcon#*before return 0, iclass 7, count 2 2006.246.08:26:01.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:26:01.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.246.08:26:01.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.246.08:26:01.72#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:01.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:26:01.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:26:01.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:26:01.84#ibcon#enter wrdev, iclass 7, count 0 2006.246.08:26:01.84#ibcon#first serial, iclass 7, count 0 2006.246.08:26:01.84#ibcon#enter sib2, iclass 7, count 0 2006.246.08:26:01.84#ibcon#flushed, iclass 7, count 0 2006.246.08:26:01.84#ibcon#about to write, iclass 7, count 0 2006.246.08:26:01.84#ibcon#wrote, iclass 7, count 0 2006.246.08:26:01.84#ibcon#about to read 3, iclass 7, count 0 2006.246.08:26:01.86#ibcon#read 3, iclass 7, count 0 2006.246.08:26:01.86#ibcon#about to read 4, iclass 7, count 0 2006.246.08:26:01.86#ibcon#read 4, iclass 7, count 0 2006.246.08:26:01.86#ibcon#about to read 5, iclass 7, count 0 2006.246.08:26:01.86#ibcon#read 5, iclass 7, count 0 2006.246.08:26:01.86#ibcon#about to read 6, iclass 7, count 0 2006.246.08:26:01.86#ibcon#read 6, iclass 7, count 0 2006.246.08:26:01.86#ibcon#end of sib2, iclass 7, count 0 2006.246.08:26:01.86#ibcon#*mode == 0, iclass 7, count 0 2006.246.08:26:01.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.246.08:26:01.86#ibcon#[27=USB\r\n] 2006.246.08:26:01.86#ibcon#*before write, iclass 7, count 0 2006.246.08:26:01.86#ibcon#enter sib2, iclass 7, count 0 2006.246.08:26:01.86#ibcon#flushed, iclass 7, count 0 2006.246.08:26:01.86#ibcon#about to write, iclass 7, count 0 2006.246.08:26:01.86#ibcon#wrote, iclass 7, count 0 2006.246.08:26:01.86#ibcon#about to read 3, iclass 7, count 0 2006.246.08:26:01.89#ibcon#read 3, iclass 7, count 0 2006.246.08:26:01.89#ibcon#about to read 4, iclass 7, count 0 2006.246.08:26:01.89#ibcon#read 4, iclass 7, count 0 2006.246.08:26:01.89#ibcon#about to read 5, iclass 7, count 0 2006.246.08:26:01.89#ibcon#read 5, iclass 7, count 0 2006.246.08:26:01.89#ibcon#about to read 6, iclass 7, count 0 2006.246.08:26:01.89#ibcon#read 6, iclass 7, count 0 2006.246.08:26:01.89#ibcon#end of sib2, iclass 7, count 0 2006.246.08:26:01.89#ibcon#*after write, iclass 7, count 0 2006.246.08:26:01.89#ibcon#*before return 0, iclass 7, count 0 2006.246.08:26:01.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:26:01.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.246.08:26:01.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.246.08:26:01.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.246.08:26:01.89$vc4f8/vblo=5,744.99 2006.246.08:26:01.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.246.08:26:01.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.246.08:26:01.89#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:01.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:26:01.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:26:01.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:26:01.89#ibcon#enter wrdev, iclass 11, count 0 2006.246.08:26:01.89#ibcon#first serial, iclass 11, count 0 2006.246.08:26:01.89#ibcon#enter sib2, iclass 11, count 0 2006.246.08:26:01.89#ibcon#flushed, iclass 11, count 0 2006.246.08:26:01.89#ibcon#about to write, iclass 11, count 0 2006.246.08:26:01.89#ibcon#wrote, iclass 11, count 0 2006.246.08:26:01.89#ibcon#about to read 3, iclass 11, count 0 2006.246.08:26:01.91#ibcon#read 3, iclass 11, count 0 2006.246.08:26:01.91#ibcon#about to read 4, iclass 11, count 0 2006.246.08:26:01.91#ibcon#read 4, iclass 11, count 0 2006.246.08:26:01.91#ibcon#about to read 5, iclass 11, count 0 2006.246.08:26:01.91#ibcon#read 5, iclass 11, count 0 2006.246.08:26:01.91#ibcon#about to read 6, iclass 11, count 0 2006.246.08:26:01.91#ibcon#read 6, iclass 11, count 0 2006.246.08:26:01.91#ibcon#end of sib2, iclass 11, count 0 2006.246.08:26:01.91#ibcon#*mode == 0, iclass 11, count 0 2006.246.08:26:01.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.246.08:26:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.246.08:26:01.91#ibcon#*before write, iclass 11, count 0 2006.246.08:26:01.91#ibcon#enter sib2, iclass 11, count 0 2006.246.08:26:01.91#ibcon#flushed, iclass 11, count 0 2006.246.08:26:01.91#ibcon#about to write, iclass 11, count 0 2006.246.08:26:01.91#ibcon#wrote, iclass 11, count 0 2006.246.08:26:01.91#ibcon#about to read 3, iclass 11, count 0 2006.246.08:26:01.95#ibcon#read 3, iclass 11, count 0 2006.246.08:26:01.95#ibcon#about to read 4, iclass 11, count 0 2006.246.08:26:01.95#ibcon#read 4, iclass 11, count 0 2006.246.08:26:01.95#ibcon#about to read 5, iclass 11, count 0 2006.246.08:26:01.95#ibcon#read 5, iclass 11, count 0 2006.246.08:26:01.95#ibcon#about to read 6, iclass 11, count 0 2006.246.08:26:01.95#ibcon#read 6, iclass 11, count 0 2006.246.08:26:01.95#ibcon#end of sib2, iclass 11, count 0 2006.246.08:26:01.95#ibcon#*after write, iclass 11, count 0 2006.246.08:26:01.95#ibcon#*before return 0, iclass 11, count 0 2006.246.08:26:01.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:26:01.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.246.08:26:01.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.246.08:26:01.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.246.08:26:01.95$vc4f8/vb=5,3 2006.246.08:26:01.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.246.08:26:01.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.246.08:26:01.95#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:01.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:26:02.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:26:02.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:26:02.02#ibcon#enter wrdev, iclass 13, count 2 2006.246.08:26:02.02#ibcon#first serial, iclass 13, count 2 2006.246.08:26:02.02#ibcon#enter sib2, iclass 13, count 2 2006.246.08:26:02.02#ibcon#flushed, iclass 13, count 2 2006.246.08:26:02.02#ibcon#about to write, iclass 13, count 2 2006.246.08:26:02.02#ibcon#wrote, iclass 13, count 2 2006.246.08:26:02.02#ibcon#about to read 3, iclass 13, count 2 2006.246.08:26:02.03#ibcon#read 3, iclass 13, count 2 2006.246.08:26:02.03#ibcon#about to read 4, iclass 13, count 2 2006.246.08:26:02.03#ibcon#read 4, iclass 13, count 2 2006.246.08:26:02.03#ibcon#about to read 5, iclass 13, count 2 2006.246.08:26:02.03#ibcon#read 5, iclass 13, count 2 2006.246.08:26:02.03#ibcon#about to read 6, iclass 13, count 2 2006.246.08:26:02.03#ibcon#read 6, iclass 13, count 2 2006.246.08:26:02.03#ibcon#end of sib2, iclass 13, count 2 2006.246.08:26:02.03#ibcon#*mode == 0, iclass 13, count 2 2006.246.08:26:02.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.246.08:26:02.03#ibcon#[27=AT05-03\r\n] 2006.246.08:26:02.03#ibcon#*before write, iclass 13, count 2 2006.246.08:26:02.03#ibcon#enter sib2, iclass 13, count 2 2006.246.08:26:02.03#ibcon#flushed, iclass 13, count 2 2006.246.08:26:02.03#ibcon#about to write, iclass 13, count 2 2006.246.08:26:02.03#ibcon#wrote, iclass 13, count 2 2006.246.08:26:02.03#ibcon#about to read 3, iclass 13, count 2 2006.246.08:26:02.06#ibcon#read 3, iclass 13, count 2 2006.246.08:26:02.06#ibcon#about to read 4, iclass 13, count 2 2006.246.08:26:02.06#ibcon#read 4, iclass 13, count 2 2006.246.08:26:02.06#ibcon#about to read 5, iclass 13, count 2 2006.246.08:26:02.06#ibcon#read 5, iclass 13, count 2 2006.246.08:26:02.06#ibcon#about to read 6, iclass 13, count 2 2006.246.08:26:02.06#ibcon#read 6, iclass 13, count 2 2006.246.08:26:02.06#ibcon#end of sib2, iclass 13, count 2 2006.246.08:26:02.06#ibcon#*after write, iclass 13, count 2 2006.246.08:26:02.06#ibcon#*before return 0, iclass 13, count 2 2006.246.08:26:02.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:26:02.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.246.08:26:02.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.246.08:26:02.06#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:02.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:26:02.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:26:02.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:26:02.18#ibcon#enter wrdev, iclass 13, count 0 2006.246.08:26:02.18#ibcon#first serial, iclass 13, count 0 2006.246.08:26:02.18#ibcon#enter sib2, iclass 13, count 0 2006.246.08:26:02.18#ibcon#flushed, iclass 13, count 0 2006.246.08:26:02.18#ibcon#about to write, iclass 13, count 0 2006.246.08:26:02.18#ibcon#wrote, iclass 13, count 0 2006.246.08:26:02.18#ibcon#about to read 3, iclass 13, count 0 2006.246.08:26:02.22#ibcon#read 3, iclass 13, count 0 2006.246.08:26:02.22#ibcon#about to read 4, iclass 13, count 0 2006.246.08:26:02.22#ibcon#read 4, iclass 13, count 0 2006.246.08:26:02.22#ibcon#about to read 5, iclass 13, count 0 2006.246.08:26:02.22#ibcon#read 5, iclass 13, count 0 2006.246.08:26:02.22#ibcon#about to read 6, iclass 13, count 0 2006.246.08:26:02.22#ibcon#read 6, iclass 13, count 0 2006.246.08:26:02.22#ibcon#end of sib2, iclass 13, count 0 2006.246.08:26:02.22#ibcon#*mode == 0, iclass 13, count 0 2006.246.08:26:02.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.246.08:26:02.22#ibcon#[27=USB\r\n] 2006.246.08:26:02.22#ibcon#*before write, iclass 13, count 0 2006.246.08:26:02.22#ibcon#enter sib2, iclass 13, count 0 2006.246.08:26:02.22#ibcon#flushed, iclass 13, count 0 2006.246.08:26:02.22#ibcon#about to write, iclass 13, count 0 2006.246.08:26:02.22#ibcon#wrote, iclass 13, count 0 2006.246.08:26:02.22#ibcon#about to read 3, iclass 13, count 0 2006.246.08:26:02.24#ibcon#read 3, iclass 13, count 0 2006.246.08:26:02.24#ibcon#about to read 4, iclass 13, count 0 2006.246.08:26:02.24#ibcon#read 4, iclass 13, count 0 2006.246.08:26:02.24#ibcon#about to read 5, iclass 13, count 0 2006.246.08:26:02.24#ibcon#read 5, iclass 13, count 0 2006.246.08:26:02.24#ibcon#about to read 6, iclass 13, count 0 2006.246.08:26:02.24#ibcon#read 6, iclass 13, count 0 2006.246.08:26:02.24#ibcon#end of sib2, iclass 13, count 0 2006.246.08:26:02.24#ibcon#*after write, iclass 13, count 0 2006.246.08:26:02.24#ibcon#*before return 0, iclass 13, count 0 2006.246.08:26:02.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:26:02.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.246.08:26:02.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.246.08:26:02.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.246.08:26:02.24$vc4f8/vblo=6,752.99 2006.246.08:26:02.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.246.08:26:02.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.246.08:26:02.24#ibcon#ireg 17 cls_cnt 0 2006.246.08:26:02.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:26:02.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:26:02.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:26:02.24#ibcon#enter wrdev, iclass 15, count 0 2006.246.08:26:02.24#ibcon#first serial, iclass 15, count 0 2006.246.08:26:02.24#ibcon#enter sib2, iclass 15, count 0 2006.246.08:26:02.24#ibcon#flushed, iclass 15, count 0 2006.246.08:26:02.24#ibcon#about to write, iclass 15, count 0 2006.246.08:26:02.24#ibcon#wrote, iclass 15, count 0 2006.246.08:26:02.24#ibcon#about to read 3, iclass 15, count 0 2006.246.08:26:02.26#ibcon#read 3, iclass 15, count 0 2006.246.08:26:02.26#ibcon#about to read 4, iclass 15, count 0 2006.246.08:26:02.26#ibcon#read 4, iclass 15, count 0 2006.246.08:26:02.26#ibcon#about to read 5, iclass 15, count 0 2006.246.08:26:02.26#ibcon#read 5, iclass 15, count 0 2006.246.08:26:02.26#ibcon#about to read 6, iclass 15, count 0 2006.246.08:26:02.26#ibcon#read 6, iclass 15, count 0 2006.246.08:26:02.26#ibcon#end of sib2, iclass 15, count 0 2006.246.08:26:02.26#ibcon#*mode == 0, iclass 15, count 0 2006.246.08:26:02.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.246.08:26:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.246.08:26:02.26#ibcon#*before write, iclass 15, count 0 2006.246.08:26:02.26#ibcon#enter sib2, iclass 15, count 0 2006.246.08:26:02.26#ibcon#flushed, iclass 15, count 0 2006.246.08:26:02.26#ibcon#about to write, iclass 15, count 0 2006.246.08:26:02.26#ibcon#wrote, iclass 15, count 0 2006.246.08:26:02.26#ibcon#about to read 3, iclass 15, count 0 2006.246.08:26:02.30#ibcon#read 3, iclass 15, count 0 2006.246.08:26:02.30#ibcon#about to read 4, iclass 15, count 0 2006.246.08:26:02.30#ibcon#read 4, iclass 15, count 0 2006.246.08:26:02.30#ibcon#about to read 5, iclass 15, count 0 2006.246.08:26:02.30#ibcon#read 5, iclass 15, count 0 2006.246.08:26:02.30#ibcon#about to read 6, iclass 15, count 0 2006.246.08:26:02.30#ibcon#read 6, iclass 15, count 0 2006.246.08:26:02.30#ibcon#end of sib2, iclass 15, count 0 2006.246.08:26:02.30#ibcon#*after write, iclass 15, count 0 2006.246.08:26:02.30#ibcon#*before return 0, iclass 15, count 0 2006.246.08:26:02.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:26:02.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.246.08:26:02.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.246.08:26:02.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.246.08:26:02.30$vc4f8/vb=6,3 2006.246.08:26:02.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.246.08:26:02.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.246.08:26:02.30#ibcon#ireg 11 cls_cnt 2 2006.246.08:26:02.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:26:02.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:26:02.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:26:02.36#ibcon#enter wrdev, iclass 17, count 2 2006.246.08:26:02.36#ibcon#first serial, iclass 17, count 2 2006.246.08:26:02.36#ibcon#enter sib2, iclass 17, count 2 2006.246.08:26:02.36#ibcon#flushed, iclass 17, count 2 2006.246.08:26:02.36#ibcon#about to write, iclass 17, count 2 2006.246.08:26:02.36#ibcon#wrote, iclass 17, count 2 2006.246.08:26:02.36#ibcon#about to read 3, iclass 17, count 2 2006.246.08:26:02.38#ibcon#read 3, iclass 17, count 2 2006.246.08:26:02.38#ibcon#about to read 4, iclass 17, count 2 2006.246.08:26:02.38#ibcon#read 4, iclass 17, count 2 2006.246.08:26:02.38#ibcon#about to read 5, iclass 17, count 2 2006.246.08:26:02.38#ibcon#read 5, iclass 17, count 2 2006.246.08:26:02.38#ibcon#about to read 6, iclass 17, count 2 2006.246.08:26:02.38#ibcon#read 6, iclass 17, count 2 2006.246.08:26:02.38#ibcon#end of sib2, iclass 17, count 2 2006.246.08:26:02.38#ibcon#*mode == 0, iclass 17, count 2 2006.246.08:26:02.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.246.08:26:02.38#ibcon#[27=AT06-03\r\n] 2006.246.08:26:02.38#ibcon#*before write, iclass 17, count 2 2006.246.08:26:02.38#ibcon#enter sib2, iclass 17, count 2 2006.246.08:26:02.38#ibcon#flushed, iclass 17, count 2 2006.246.08:26:02.38#ibcon#about to write, iclass 17, count 2 2006.246.08:26:02.38#ibcon#wrote, iclass 17, count 2 2006.246.08:26:02.38#ibcon#about to read 3, iclass 17, count 2 2006.246.08:26:02.41#ibcon#read 3, iclass 17, count 2 2006.246.08:26:02.41#ibcon#about to read 4, iclass 17, count 2 2006.246.08:26:02.41#ibcon#read 4, iclass 17, count 2 2006.246.08:26:02.41#ibcon#about to read 5, iclass 17, count 2 2006.246.08:26:02.41#ibcon#read 5, iclass 17, count 2 2006.246.08:26:02.41#ibcon#about to read 6, iclass 17, count 2 2006.246.08:26:02.41#ibcon#read 6, iclass 17, count 2 2006.246.08:26:02.41#ibcon#end of sib2, iclass 17, count 2 2006.246.08:26:02.41#ibcon#*after write, iclass 17, count 2 2006.246.08:26:02.41#ibcon#*before return 0, iclass 17, count 2 2006.246.08:26:02.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:26:02.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.246.08:26:02.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.246.08:26:02.41#ibcon#ireg 7 cls_cnt 0 2006.246.08:26:02.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:26:02.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:26:02.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:26:02.53#ibcon#enter wrdev, iclass 17, count 0 2006.246.08:26:02.53#ibcon#first serial, iclass 17, count 0 2006.246.08:26:02.53#ibcon#enter sib2, iclass 17, count 0 2006.246.08:26:02.53#ibcon#flushed, iclass 17, count 0 2006.246.08:26:02.53#ibcon#about to write, iclass 17, count 0 2006.246.08:26:02.53#ibcon#wrote, iclass 17, count 0 2006.246.08:26:02.53#ibcon#about to read 3, iclass 17, count 0 2006.246.08:26:02.55#ibcon#read 3, iclass 17, count 0 2006.246.08:26:02.55#ibcon#about to read 4, iclass 17, count 0 2006.246.08:26:02.55#ibcon#read 4, iclass 17, count 0 2006.246.08:26:02.55#ibcon#about to read 5, iclass 17, count 0 2006.246.08:26:02.55#ibcon#read 5, iclass 17, count 0 2006.246.08:26:02.55#ibcon#about to read 6, iclass 17, count 0 2006.246.08:26:02.55#ibcon#read 6, iclass 17, count 0 2006.246.08:26:02.55#ibcon#end of sib2, iclass 17, count 0 2006.246.08:26:02.55#ibcon#*mode == 0, iclass 17, count 0 2006.246.08:26:02.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.246.08:26:02.55#ibcon#[27=USB\r\n] 2006.246.08:26:02.55#ibcon#*before write, iclass 17, count 0 2006.246.08:26:02.55#ibcon#enter sib2, iclass 17, count 0 2006.246.08:26:02.55#ibcon#flushed, iclass 17, count 0 2006.246.08:26:02.55#ibcon#about to write, iclass 17, count 0 2006.246.08:26:02.55#ibcon#wrote, iclass 17, count 0 2006.246.08:26:02.55#ibcon#about to read 3, iclass 17, count 0 2006.246.08:26:02.58#ibcon#read 3, iclass 17, count 0 2006.246.08:26:02.58#ibcon#about to read 4, iclass 17, count 0 2006.246.08:26:02.58#ibcon#read 4, iclass 17, count 0 2006.246.08:26:02.58#ibcon#about to read 5, iclass 17, count 0 2006.246.08:26:02.58#ibcon#read 5, iclass 17, count 0 2006.246.08:26:02.58#ibcon#about to read 6, iclass 17, count 0 2006.246.08:26:02.58#ibcon#read 6, iclass 17, count 0 2006.246.08:26:02.58#ibcon#end of sib2, iclass 17, count 0 2006.246.08:26:02.58#ibcon#*after write, iclass 17, count 0 2006.246.08:26:02.58#ibcon#*before return 0, iclass 17, count 0 2006.246.08:26:02.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:26:02.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.246.08:26:02.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.246.08:26:02.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.246.08:26:02.58$vc4f8/vabw=wide 2006.246.08:26:02.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.246.08:26:02.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.246.08:26:02.58#ibcon#ireg 8 cls_cnt 0 2006.246.08:26:02.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:26:02.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:26:02.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:26:02.58#ibcon#enter wrdev, iclass 19, count 0 2006.246.08:26:02.58#ibcon#first serial, iclass 19, count 0 2006.246.08:26:02.58#ibcon#enter sib2, iclass 19, count 0 2006.246.08:26:02.58#ibcon#flushed, iclass 19, count 0 2006.246.08:26:02.58#ibcon#about to write, iclass 19, count 0 2006.246.08:26:02.58#ibcon#wrote, iclass 19, count 0 2006.246.08:26:02.58#ibcon#about to read 3, iclass 19, count 0 2006.246.08:26:02.60#ibcon#read 3, iclass 19, count 0 2006.246.08:26:02.60#ibcon#about to read 4, iclass 19, count 0 2006.246.08:26:02.60#ibcon#read 4, iclass 19, count 0 2006.246.08:26:02.60#ibcon#about to read 5, iclass 19, count 0 2006.246.08:26:02.60#ibcon#read 5, iclass 19, count 0 2006.246.08:26:02.60#ibcon#about to read 6, iclass 19, count 0 2006.246.08:26:02.60#ibcon#read 6, iclass 19, count 0 2006.246.08:26:02.60#ibcon#end of sib2, iclass 19, count 0 2006.246.08:26:02.60#ibcon#*mode == 0, iclass 19, count 0 2006.246.08:26:02.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.246.08:26:02.60#ibcon#[25=BW32\r\n] 2006.246.08:26:02.60#ibcon#*before write, iclass 19, count 0 2006.246.08:26:02.60#ibcon#enter sib2, iclass 19, count 0 2006.246.08:26:02.60#ibcon#flushed, iclass 19, count 0 2006.246.08:26:02.60#ibcon#about to write, iclass 19, count 0 2006.246.08:26:02.60#ibcon#wrote, iclass 19, count 0 2006.246.08:26:02.60#ibcon#about to read 3, iclass 19, count 0 2006.246.08:26:02.63#ibcon#read 3, iclass 19, count 0 2006.246.08:26:02.63#ibcon#about to read 4, iclass 19, count 0 2006.246.08:26:02.63#ibcon#read 4, iclass 19, count 0 2006.246.08:26:02.63#ibcon#about to read 5, iclass 19, count 0 2006.246.08:26:02.63#ibcon#read 5, iclass 19, count 0 2006.246.08:26:02.63#ibcon#about to read 6, iclass 19, count 0 2006.246.08:26:02.63#ibcon#read 6, iclass 19, count 0 2006.246.08:26:02.63#ibcon#end of sib2, iclass 19, count 0 2006.246.08:26:02.63#ibcon#*after write, iclass 19, count 0 2006.246.08:26:02.63#ibcon#*before return 0, iclass 19, count 0 2006.246.08:26:02.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:26:02.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.246.08:26:02.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.246.08:26:02.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.246.08:26:02.63$vc4f8/vbbw=wide 2006.246.08:26:02.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.246.08:26:02.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.246.08:26:02.63#ibcon#ireg 8 cls_cnt 0 2006.246.08:26:02.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:26:02.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:26:02.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:26:02.70#ibcon#enter wrdev, iclass 21, count 0 2006.246.08:26:02.70#ibcon#first serial, iclass 21, count 0 2006.246.08:26:02.70#ibcon#enter sib2, iclass 21, count 0 2006.246.08:26:02.70#ibcon#flushed, iclass 21, count 0 2006.246.08:26:02.70#ibcon#about to write, iclass 21, count 0 2006.246.08:26:02.70#ibcon#wrote, iclass 21, count 0 2006.246.08:26:02.70#ibcon#about to read 3, iclass 21, count 0 2006.246.08:26:02.72#ibcon#read 3, iclass 21, count 0 2006.246.08:26:02.72#ibcon#about to read 4, iclass 21, count 0 2006.246.08:26:02.72#ibcon#read 4, iclass 21, count 0 2006.246.08:26:02.72#ibcon#about to read 5, iclass 21, count 0 2006.246.08:26:02.72#ibcon#read 5, iclass 21, count 0 2006.246.08:26:02.72#ibcon#about to read 6, iclass 21, count 0 2006.246.08:26:02.72#ibcon#read 6, iclass 21, count 0 2006.246.08:26:02.72#ibcon#end of sib2, iclass 21, count 0 2006.246.08:26:02.72#ibcon#*mode == 0, iclass 21, count 0 2006.246.08:26:02.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.246.08:26:02.72#ibcon#[27=BW32\r\n] 2006.246.08:26:02.72#ibcon#*before write, iclass 21, count 0 2006.246.08:26:02.72#ibcon#enter sib2, iclass 21, count 0 2006.246.08:26:02.72#ibcon#flushed, iclass 21, count 0 2006.246.08:26:02.72#ibcon#about to write, iclass 21, count 0 2006.246.08:26:02.72#ibcon#wrote, iclass 21, count 0 2006.246.08:26:02.72#ibcon#about to read 3, iclass 21, count 0 2006.246.08:26:02.75#ibcon#read 3, iclass 21, count 0 2006.246.08:26:02.75#ibcon#about to read 4, iclass 21, count 0 2006.246.08:26:02.75#ibcon#read 4, iclass 21, count 0 2006.246.08:26:02.75#ibcon#about to read 5, iclass 21, count 0 2006.246.08:26:02.75#ibcon#read 5, iclass 21, count 0 2006.246.08:26:02.75#ibcon#about to read 6, iclass 21, count 0 2006.246.08:26:02.75#ibcon#read 6, iclass 21, count 0 2006.246.08:26:02.75#ibcon#end of sib2, iclass 21, count 0 2006.246.08:26:02.75#ibcon#*after write, iclass 21, count 0 2006.246.08:26:02.75#ibcon#*before return 0, iclass 21, count 0 2006.246.08:26:02.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:26:02.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.246.08:26:02.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.246.08:26:02.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.246.08:26:02.75$4f8m12a/ifd4f 2006.246.08:26:02.75$ifd4f/lo= 2006.246.08:26:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.246.08:26:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.246.08:26:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.246.08:26:02.75$ifd4f/patch= 2006.246.08:26:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.246.08:26:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.246.08:26:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.246.08:26:02.75$4f8m12a/"form=m,16.000,1:2 2006.246.08:26:02.75$4f8m12a/"tpicd 2006.246.08:26:02.75$4f8m12a/echo=off 2006.246.08:26:02.75$4f8m12a/xlog=off 2006.246.08:26:02.75:!2006.246.08:26:30 2006.246.08:26:17.14#trakl#Source acquired 2006.246.08:26:18.14#flagr#flagr/antenna,acquired 2006.246.08:26:30.00:preob 2006.246.08:26:31.14/onsource/TRACKING 2006.246.08:26:31.14:!2006.246.08:26:40 2006.246.08:26:40.00:data_valid=on 2006.246.08:26:40.00:midob 2006.246.08:26:40.13/onsource/TRACKING 2006.246.08:26:40.13/wx/26.15,1005.8,77 2006.246.08:26:40.33/cable/+6.4149E-03 2006.246.08:26:41.42/va/01,08,usb,yes,31,32 2006.246.08:26:41.42/va/02,07,usb,yes,31,32 2006.246.08:26:41.42/va/03,06,usb,yes,33,33 2006.246.08:26:41.42/va/04,07,usb,yes,32,34 2006.246.08:26:41.42/va/05,07,usb,yes,34,36 2006.246.08:26:41.42/va/06,07,usb,yes,30,29 2006.246.08:26:41.42/va/07,07,usb,yes,29,29 2006.246.08:26:41.42/va/08,08,usb,yes,26,25 2006.246.08:26:41.65/valo/01,532.99,yes,locked 2006.246.08:26:41.65/valo/02,572.99,yes,locked 2006.246.08:26:41.65/valo/03,672.99,yes,locked 2006.246.08:26:41.65/valo/04,832.99,yes,locked 2006.246.08:26:41.65/valo/05,652.99,yes,locked 2006.246.08:26:41.65/valo/06,772.99,yes,locked 2006.246.08:26:41.65/valo/07,832.99,yes,locked 2006.246.08:26:41.65/valo/08,852.99,yes,locked 2006.246.08:26:42.74/vb/01,04,usb,yes,30,29 2006.246.08:26:42.74/vb/02,04,usb,yes,32,34 2006.246.08:26:42.74/vb/03,04,usb,yes,28,32 2006.246.08:26:42.74/vb/04,04,usb,yes,29,29 2006.246.08:26:42.74/vb/05,03,usb,yes,35,39 2006.246.08:26:42.74/vb/06,03,usb,yes,35,39 2006.246.08:26:42.74/vb/07,04,usb,yes,31,31 2006.246.08:26:42.74/vb/08,03,usb,yes,35,39 2006.246.08:26:42.98/vblo/01,632.99,yes,locked 2006.246.08:26:42.98/vblo/02,640.99,yes,locked 2006.246.08:26:42.98/vblo/03,656.99,yes,locked 2006.246.08:26:42.98/vblo/04,712.99,yes,locked 2006.246.08:26:42.98/vblo/05,744.99,yes,locked 2006.246.08:26:42.98/vblo/06,752.99,yes,locked 2006.246.08:26:42.98/vblo/07,734.99,yes,locked 2006.246.08:26:42.98/vblo/08,744.99,yes,locked 2006.246.08:26:43.13/vabw/8 2006.246.08:26:43.28/vbbw/8 2006.246.08:26:43.37/xfe/off,on,13.0 2006.246.08:26:43.74/ifatt/23,28,28,28 2006.246.08:26:44.07/fmout-gps/S +4.42E-07 2006.246.08:26:44.11:!2006.246.08:27:40 2006.246.08:27:40.00:data_valid=off 2006.246.08:27:40.01:postob 2006.246.08:27:40.22/cable/+6.4135E-03 2006.246.08:27:40.22/wx/26.13,1005.8,77 2006.246.08:27:41.08/fmout-gps/S +4.43E-07 2006.246.08:27:41.08:checkk5last 2006.246.08:27:41.09&checkk5last/chk_obsdata=1 2006.246.08:27:41.09&checkk5last/chk_obsdata=2 2006.246.08:27:41.09&checkk5last/chk_obsdata=3 2006.246.08:27:41.10&checkk5last/chk_obsdata=4 2006.246.08:27:41.10&checkk5last/k5log=1 2006.246.08:27:41.10&checkk5last/k5log=2 2006.246.08:27:41.11&checkk5last/k5log=3 2006.246.08:27:41.11&checkk5last/k5log=4 2006.246.08:27:41.11&checkk5last/obsinfo 2006.246.08:27:41.50/chk_obsdata//k5ts1/T2460826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:27:41.86/chk_obsdata//k5ts2/T2460826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:27:42.23/chk_obsdata//k5ts3/T2460826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:27:42.60/chk_obsdata//k5ts4/T2460826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.246.08:27:43.30/k5log//k5ts1_log_newline 2006.246.08:27:43.99/k5log//k5ts2_log_newline 2006.246.08:27:44.68/k5log//k5ts3_log_newline 2006.246.08:27:45.37/k5log//k5ts4_log_newline 2006.246.08:27:45.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.246.08:27:45.39:sched_end 2006.246.08:27:45.39&sched_end/stopcheck 2006.246.08:27:45.39&stopcheck/sy=killall check_fsrun.pl 2006.246.08:27:45.39&stopcheck/" sy=killall chmem.sh 2006.246.08:27:45.48:source=idle 2006.246.08:27:46.13#flagr#flagr/antenna,new-source 2006.246.08:27:46.14:stow 2006.246.08:27:46.14&stow/source=idle 2006.246.08:27:46.14&stow/"this is stow command. 2006.246.08:27:46.15&stow/antenna=m3 2006.246.08:27:50.01:!+10m 2006.246.08:37:50.03:standby 2006.246.08:37:50.03&standby/"this is standby command. 2006.246.08:37:50.04&standby/antenna=m0 2006.246.08:37:51.01:checkk5hdd 2006.246.08:37:51.01&checkk5hdd/chk_hdd=1 2006.246.08:37:51.02&checkk5hdd/chk_hdd=2 2006.246.08:37:51.02&checkk5hdd/chk_hdd=3 2006.246.08:37:51.02&checkk5hdd/chk_hdd=4 2006.246.08:37:53.83/chk_hdd//k5ts1/GSI00161:T246073000a.dat~T246082640a.dat[13001424896Byte] 2006.246.08:37:56.64/chk_hdd//k5ts2/GSI00255:T246073000b.dat~T246082640b.dat[13001424896Byte] 2006.246.08:37:59.44/chk_hdd//k5ts3/GSI00278:T246073000c.dat~T246082640c.dat[13001424896Byte] 2006.246.08:38:02.26/chk_hdd//k5ts4/GSI00141:T246073000d.dat~T246082640d.dat[13001424896Byte] 2006.246.08:38:02.26:sy=cp /usr2/log/k06246ts.log /usr2/log_backup/ 2006.246.08:38:02.36:*end of schedule