2006.244.07:37:53.48;Log Opened: Mark IV Field System Version 9.7.7 2006.244.07:37:53.48;location,TSUKUB32,-140.09,36.10,61.0 2006.244.07:37:53.48;horizon1,0.,5.,360. 2006.244.07:37:53.48;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.244.07:37:53.48;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.244.07:37:53.48;drivev11,330,270,no 2006.244.07:37:53.48;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.244.07:37:53.48;drivev13,15.000,268,10.000,10.000,10.000 2006.244.07:37:53.48;drivev21,330,270,no 2006.244.07:37:53.48;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.244.07:37:53.48;drivev23,15.000,268,10.000,10.000,10.000 2006.244.07:37:53.48;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.244.07:37:53.48;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.244.07:37:53.48;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.244.07:37:53.48;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.244.07:37:53.48;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.244.07:37:53.48;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.244.07:37:53.48;time,-0.364,101.533,rate 2006.244.07:37:53.48;flagr,200 2006.244.07:37:53.48:" K06245 2006 TSUKUB32 T Ts 2006.244.07:37:53.48:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.244.07:37:53.48:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.244.07:37:53.48:" 108 TSUKUB32 14 17400 2006.244.07:37:53.48:" drudg version 050216 compiled under FS 9.7.07 2006.244.07:37:53.48:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.244.07:37:53.48:exper_initi 2006.244.07:37:53.48&exper_initi/proc_library 2006.244.07:37:53.48&exper_initi/sched_initi 2006.244.07:37:53.48:!2006.245.06:29:50 2006.244.07:37:53.48&proc_library/" k06245 tsukub32 ts 2006.244.07:37:53.48&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.244.07:37:53.48&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.244.07:37:53.48&sched_initi/startcheck 2006.244.07:37:53.48&startcheck/sy=check_fsrun.pl & 2006.244.07:37:53.48&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.244.07:38:06.74;cable 2006.244.07:38:06.89/cable/+6.4518E-03 2006.244.07:39:10.34;cablelong 2006.244.07:39:10.50/cablelong/+7.0213E-03 2006.244.07:39:12.43;cablediff 2006.244.07:39:12.43/cablediff/569.5e-6,+ 2006.244.07:40:04.42;cable 2006.244.07:40:04.63/cable/+6.4533E-03 2006.244.07:40:15.78;wx 2006.244.07:40:15.78/wx/20.95,1002.2,100 2006.244.07:40:23.22;"Sky is rainy. 2006.244.07:40:31.05;xfe 2006.244.07:40:31.14/xfe/off,on,13.7 2006.244.07:40:36.54;clockoff 2006.244.07:40:36.54&clockoff/"gps-fmout=1p 2006.244.07:40:36.54&clockoff/fmout-gps=1p 2006.244.07:40:37.08/fmout-gps/S +4.33E-07 2006.245.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.245.06:29:50.02:!2006.245.07:19:50 2006.245.07:19:50.00:unstow 2006.245.07:19:50.00&unstow/antenna=e 2006.245.07:19:50.00&unstow/!+10s 2006.245.07:19:50.00&unstow/antenna=m2 2006.245.07:20:02.01:scan_name=245-0730,k06245,60 2006.245.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.245.07:20:02.02#antcn#PM 1 00019 2005 228 00 22 31 00 2006.245.07:20:02.02#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.245.07:20:02.02#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.245.07:20:02.02#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.245.07:20:02.02#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.245.07:20:02.02#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.245.07:20:03.14:ready_k5 2006.245.07:20:03.14&ready_k5/obsinfo=st 2006.245.07:20:03.14&ready_k5/autoobs=1 2006.245.07:20:03.14&ready_k5/autoobs=2 2006.245.07:20:03.14&ready_k5/autoobs=3 2006.245.07:20:03.14&ready_k5/autoobs=4 2006.245.07:20:03.14&ready_k5/obsinfo 2006.245.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.245.07:20:03.15#flagr#flagr/antenna,new-source 2006.245.07:20:07.46/autoobs//k5ts1/ autoobs started! 2006.245.07:20:12.11/autoobs//k5ts2/ autoobs started! 2006.245.07:20:16.53/autoobs//k5ts3/ autoobs started! 2006.245.07:20:19.98/autoobs//k5ts4/ autoobs started! 2006.245.07:20:20.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:20:20.01:4f8m12a=1 2006.245.07:20:20.01&4f8m12a/xlog=on 2006.245.07:20:20.01&4f8m12a/echo=on 2006.245.07:20:20.01&4f8m12a/pcalon 2006.245.07:20:20.01&4f8m12a/"tpicd=stop 2006.245.07:20:20.01&4f8m12a/vc4f8 2006.245.07:20:20.01&4f8m12a/ifd4f 2006.245.07:20:20.01&4f8m12a/"form=m,16.000,1:2 2006.245.07:20:20.01&4f8m12a/"tpicd 2006.245.07:20:20.01&4f8m12a/echo=off 2006.245.07:20:20.01&4f8m12a/xlog=off 2006.245.07:20:20.01$4f8m12a/echo=on 2006.245.07:20:20.01$4f8m12a/pcalon 2006.245.07:20:20.01&pcalon/"no phase cal control is implemented here 2006.245.07:20:20.01$pcalon/"no phase cal control is implemented here 2006.245.07:20:20.01$4f8m12a/"tpicd=stop 2006.245.07:20:20.01$4f8m12a/vc4f8 2006.245.07:20:20.01&vc4f8/valo=1,532.99 2006.245.07:20:20.01&vc4f8/va=1,8 2006.245.07:20:20.01&vc4f8/valo=2,572.99 2006.245.07:20:20.01&vc4f8/va=2,7 2006.245.07:20:20.01&vc4f8/valo=3,672.99 2006.245.07:20:20.01&vc4f8/va=3,6 2006.245.07:20:20.01&vc4f8/valo=4,832.99 2006.245.07:20:20.01&vc4f8/va=4,7 2006.245.07:20:20.01&vc4f8/valo=5,652.99 2006.245.07:20:20.01&vc4f8/va=5,7 2006.245.07:20:20.01&vc4f8/valo=6,772.99 2006.245.07:20:20.01&vc4f8/va=6,7 2006.245.07:20:20.01&vc4f8/valo=7,832.99 2006.245.07:20:20.01&vc4f8/va=7,7 2006.245.07:20:20.01&vc4f8/valo=8,852.99 2006.245.07:20:20.01&vc4f8/va=8,8 2006.245.07:20:20.01&vc4f8/vblo=1,632.99 2006.245.07:20:20.01&vc4f8/vb=1,4 2006.245.07:20:20.01&vc4f8/vblo=2,640.99 2006.245.07:20:20.01&vc4f8/vb=2,4 2006.245.07:20:20.01&vc4f8/vblo=3,656.99 2006.245.07:20:20.01&vc4f8/vb=3,4 2006.245.07:20:20.01&vc4f8/vblo=4,712.99 2006.245.07:20:20.01&vc4f8/vb=4,4 2006.245.07:20:20.01&vc4f8/vblo=5,744.99 2006.245.07:20:20.01&vc4f8/vb=5,3 2006.245.07:20:20.01&vc4f8/vblo=6,752.99 2006.245.07:20:20.01&vc4f8/vb=6,3 2006.245.07:20:20.01&vc4f8/vabw=wide 2006.245.07:20:20.01&vc4f8/vbbw=wide 2006.245.07:20:20.01$vc4f8/valo=1,532.99 2006.245.07:20:20.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:20:20.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:20:20.03#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:20.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:20.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:20.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:20.03#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:20:20.03#ibcon#first serial, iclass 30, count 0 2006.245.07:20:20.03#ibcon#enter sib2, iclass 30, count 0 2006.245.07:20:20.03#ibcon#flushed, iclass 30, count 0 2006.245.07:20:20.03#ibcon#about to write, iclass 30, count 0 2006.245.07:20:20.03#ibcon#wrote, iclass 30, count 0 2006.245.07:20:20.03#ibcon#about to read 3, iclass 30, count 0 2006.245.07:20:20.06#ibcon#read 3, iclass 30, count 0 2006.245.07:20:20.06#ibcon#about to read 4, iclass 30, count 0 2006.245.07:20:20.06#ibcon#read 4, iclass 30, count 0 2006.245.07:20:20.06#ibcon#about to read 5, iclass 30, count 0 2006.245.07:20:20.06#ibcon#read 5, iclass 30, count 0 2006.245.07:20:20.06#ibcon#about to read 6, iclass 30, count 0 2006.245.07:20:20.06#ibcon#read 6, iclass 30, count 0 2006.245.07:20:20.06#ibcon#end of sib2, iclass 30, count 0 2006.245.07:20:20.06#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:20:20.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:20:20.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:20:20.06#ibcon#*before write, iclass 30, count 0 2006.245.07:20:20.06#ibcon#enter sib2, iclass 30, count 0 2006.245.07:20:20.06#ibcon#flushed, iclass 30, count 0 2006.245.07:20:20.06#ibcon#about to write, iclass 30, count 0 2006.245.07:20:20.06#ibcon#wrote, iclass 30, count 0 2006.245.07:20:20.06#ibcon#about to read 3, iclass 30, count 0 2006.245.07:20:20.11#ibcon#read 3, iclass 30, count 0 2006.245.07:20:20.11#ibcon#about to read 4, iclass 30, count 0 2006.245.07:20:20.11#ibcon#read 4, iclass 30, count 0 2006.245.07:20:20.11#ibcon#about to read 5, iclass 30, count 0 2006.245.07:20:20.11#ibcon#read 5, iclass 30, count 0 2006.245.07:20:20.11#ibcon#about to read 6, iclass 30, count 0 2006.245.07:20:20.11#ibcon#read 6, iclass 30, count 0 2006.245.07:20:20.11#ibcon#end of sib2, iclass 30, count 0 2006.245.07:20:20.11#ibcon#*after write, iclass 30, count 0 2006.245.07:20:20.11#ibcon#*before return 0, iclass 30, count 0 2006.245.07:20:20.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:20.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:20.11#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:20:20.11#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:20:20.11$vc4f8/va=1,8 2006.245.07:20:20.11#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.07:20:20.11#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.07:20:20.11#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:20.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:20.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:20.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:20.11#ibcon#enter wrdev, iclass 32, count 2 2006.245.07:20:20.11#ibcon#first serial, iclass 32, count 2 2006.245.07:20:20.11#ibcon#enter sib2, iclass 32, count 2 2006.245.07:20:20.11#ibcon#flushed, iclass 32, count 2 2006.245.07:20:20.11#ibcon#about to write, iclass 32, count 2 2006.245.07:20:20.11#ibcon#wrote, iclass 32, count 2 2006.245.07:20:20.11#ibcon#about to read 3, iclass 32, count 2 2006.245.07:20:20.13#ibcon#read 3, iclass 32, count 2 2006.245.07:20:20.13#ibcon#about to read 4, iclass 32, count 2 2006.245.07:20:20.13#ibcon#read 4, iclass 32, count 2 2006.245.07:20:20.13#ibcon#about to read 5, iclass 32, count 2 2006.245.07:20:20.13#ibcon#read 5, iclass 32, count 2 2006.245.07:20:20.13#ibcon#about to read 6, iclass 32, count 2 2006.245.07:20:20.13#ibcon#read 6, iclass 32, count 2 2006.245.07:20:20.13#ibcon#end of sib2, iclass 32, count 2 2006.245.07:20:20.13#ibcon#*mode == 0, iclass 32, count 2 2006.245.07:20:20.13#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.07:20:20.13#ibcon#[25=AT01-08\r\n] 2006.245.07:20:20.13#ibcon#*before write, iclass 32, count 2 2006.245.07:20:20.13#ibcon#enter sib2, iclass 32, count 2 2006.245.07:20:20.13#ibcon#flushed, iclass 32, count 2 2006.245.07:20:20.13#ibcon#about to write, iclass 32, count 2 2006.245.07:20:20.13#ibcon#wrote, iclass 32, count 2 2006.245.07:20:20.13#ibcon#about to read 3, iclass 32, count 2 2006.245.07:20:20.17#ibcon#read 3, iclass 32, count 2 2006.245.07:20:20.17#ibcon#about to read 4, iclass 32, count 2 2006.245.07:20:20.17#ibcon#read 4, iclass 32, count 2 2006.245.07:20:20.17#ibcon#about to read 5, iclass 32, count 2 2006.245.07:20:20.17#ibcon#read 5, iclass 32, count 2 2006.245.07:20:20.17#ibcon#about to read 6, iclass 32, count 2 2006.245.07:20:20.17#ibcon#read 6, iclass 32, count 2 2006.245.07:20:20.17#ibcon#end of sib2, iclass 32, count 2 2006.245.07:20:20.17#ibcon#*after write, iclass 32, count 2 2006.245.07:20:20.17#ibcon#*before return 0, iclass 32, count 2 2006.245.07:20:20.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:20.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:20.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.07:20:20.17#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:20.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:20.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:20.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:20.29#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:20:20.29#ibcon#first serial, iclass 32, count 0 2006.245.07:20:20.29#ibcon#enter sib2, iclass 32, count 0 2006.245.07:20:20.29#ibcon#flushed, iclass 32, count 0 2006.245.07:20:20.29#ibcon#about to write, iclass 32, count 0 2006.245.07:20:20.29#ibcon#wrote, iclass 32, count 0 2006.245.07:20:20.29#ibcon#about to read 3, iclass 32, count 0 2006.245.07:20:20.31#ibcon#read 3, iclass 32, count 0 2006.245.07:20:20.31#ibcon#about to read 4, iclass 32, count 0 2006.245.07:20:20.31#ibcon#read 4, iclass 32, count 0 2006.245.07:20:20.31#ibcon#about to read 5, iclass 32, count 0 2006.245.07:20:20.31#ibcon#read 5, iclass 32, count 0 2006.245.07:20:20.31#ibcon#about to read 6, iclass 32, count 0 2006.245.07:20:20.31#ibcon#read 6, iclass 32, count 0 2006.245.07:20:20.31#ibcon#end of sib2, iclass 32, count 0 2006.245.07:20:20.31#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:20:20.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:20:20.31#ibcon#[25=USB\r\n] 2006.245.07:20:20.31#ibcon#*before write, iclass 32, count 0 2006.245.07:20:20.31#ibcon#enter sib2, iclass 32, count 0 2006.245.07:20:20.31#ibcon#flushed, iclass 32, count 0 2006.245.07:20:20.31#ibcon#about to write, iclass 32, count 0 2006.245.07:20:20.31#ibcon#wrote, iclass 32, count 0 2006.245.07:20:20.31#ibcon#about to read 3, iclass 32, count 0 2006.245.07:20:20.34#ibcon#read 3, iclass 32, count 0 2006.245.07:20:20.34#ibcon#about to read 4, iclass 32, count 0 2006.245.07:20:20.34#ibcon#read 4, iclass 32, count 0 2006.245.07:20:20.34#ibcon#about to read 5, iclass 32, count 0 2006.245.07:20:20.34#ibcon#read 5, iclass 32, count 0 2006.245.07:20:20.34#ibcon#about to read 6, iclass 32, count 0 2006.245.07:20:20.34#ibcon#read 6, iclass 32, count 0 2006.245.07:20:20.34#ibcon#end of sib2, iclass 32, count 0 2006.245.07:20:20.34#ibcon#*after write, iclass 32, count 0 2006.245.07:20:20.34#ibcon#*before return 0, iclass 32, count 0 2006.245.07:20:20.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:20.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:20.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:20:20.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:20:20.34$vc4f8/valo=2,572.99 2006.245.07:20:20.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:20:20.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:20:20.34#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:20.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:20.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:20.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:20.34#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:20:20.34#ibcon#first serial, iclass 34, count 0 2006.245.07:20:20.34#ibcon#enter sib2, iclass 34, count 0 2006.245.07:20:20.34#ibcon#flushed, iclass 34, count 0 2006.245.07:20:20.34#ibcon#about to write, iclass 34, count 0 2006.245.07:20:20.34#ibcon#wrote, iclass 34, count 0 2006.245.07:20:20.34#ibcon#about to read 3, iclass 34, count 0 2006.245.07:20:20.37#ibcon#read 3, iclass 34, count 0 2006.245.07:20:20.37#ibcon#about to read 4, iclass 34, count 0 2006.245.07:20:20.37#ibcon#read 4, iclass 34, count 0 2006.245.07:20:20.37#ibcon#about to read 5, iclass 34, count 0 2006.245.07:20:20.37#ibcon#read 5, iclass 34, count 0 2006.245.07:20:20.37#ibcon#about to read 6, iclass 34, count 0 2006.245.07:20:20.37#ibcon#read 6, iclass 34, count 0 2006.245.07:20:20.37#ibcon#end of sib2, iclass 34, count 0 2006.245.07:20:20.37#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:20:20.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:20:20.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:20:20.37#ibcon#*before write, iclass 34, count 0 2006.245.07:20:20.37#ibcon#enter sib2, iclass 34, count 0 2006.245.07:20:20.37#ibcon#flushed, iclass 34, count 0 2006.245.07:20:20.37#ibcon#about to write, iclass 34, count 0 2006.245.07:20:20.37#ibcon#wrote, iclass 34, count 0 2006.245.07:20:20.37#ibcon#about to read 3, iclass 34, count 0 2006.245.07:20:20.41#ibcon#read 3, iclass 34, count 0 2006.245.07:20:20.41#ibcon#about to read 4, iclass 34, count 0 2006.245.07:20:20.41#ibcon#read 4, iclass 34, count 0 2006.245.07:20:20.41#ibcon#about to read 5, iclass 34, count 0 2006.245.07:20:20.41#ibcon#read 5, iclass 34, count 0 2006.245.07:20:20.41#ibcon#about to read 6, iclass 34, count 0 2006.245.07:20:20.41#ibcon#read 6, iclass 34, count 0 2006.245.07:20:20.41#ibcon#end of sib2, iclass 34, count 0 2006.245.07:20:20.41#ibcon#*after write, iclass 34, count 0 2006.245.07:20:20.41#ibcon#*before return 0, iclass 34, count 0 2006.245.07:20:20.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:20.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:20.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:20:20.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:20:20.41$vc4f8/va=2,7 2006.245.07:20:20.41#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:20:20.41#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:20:20.41#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:20.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:20.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:20.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:20.47#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:20:20.47#ibcon#first serial, iclass 36, count 2 2006.245.07:20:20.47#ibcon#enter sib2, iclass 36, count 2 2006.245.07:20:20.47#ibcon#flushed, iclass 36, count 2 2006.245.07:20:20.47#ibcon#about to write, iclass 36, count 2 2006.245.07:20:20.47#ibcon#wrote, iclass 36, count 2 2006.245.07:20:20.47#ibcon#about to read 3, iclass 36, count 2 2006.245.07:20:20.48#ibcon#read 3, iclass 36, count 2 2006.245.07:20:20.48#ibcon#about to read 4, iclass 36, count 2 2006.245.07:20:20.48#ibcon#read 4, iclass 36, count 2 2006.245.07:20:20.48#ibcon#about to read 5, iclass 36, count 2 2006.245.07:20:20.48#ibcon#read 5, iclass 36, count 2 2006.245.07:20:20.48#ibcon#about to read 6, iclass 36, count 2 2006.245.07:20:20.48#ibcon#read 6, iclass 36, count 2 2006.245.07:20:20.48#ibcon#end of sib2, iclass 36, count 2 2006.245.07:20:20.48#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:20:20.48#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:20:20.48#ibcon#[25=AT02-07\r\n] 2006.245.07:20:20.48#ibcon#*before write, iclass 36, count 2 2006.245.07:20:20.48#ibcon#enter sib2, iclass 36, count 2 2006.245.07:20:20.48#ibcon#flushed, iclass 36, count 2 2006.245.07:20:20.48#ibcon#about to write, iclass 36, count 2 2006.245.07:20:20.48#ibcon#wrote, iclass 36, count 2 2006.245.07:20:20.48#ibcon#about to read 3, iclass 36, count 2 2006.245.07:20:20.51#ibcon#read 3, iclass 36, count 2 2006.245.07:20:20.51#ibcon#about to read 4, iclass 36, count 2 2006.245.07:20:20.51#ibcon#read 4, iclass 36, count 2 2006.245.07:20:20.51#ibcon#about to read 5, iclass 36, count 2 2006.245.07:20:20.51#ibcon#read 5, iclass 36, count 2 2006.245.07:20:20.51#ibcon#about to read 6, iclass 36, count 2 2006.245.07:20:20.51#ibcon#read 6, iclass 36, count 2 2006.245.07:20:20.51#ibcon#end of sib2, iclass 36, count 2 2006.245.07:20:20.51#ibcon#*after write, iclass 36, count 2 2006.245.07:20:20.51#ibcon#*before return 0, iclass 36, count 2 2006.245.07:20:20.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:20.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:20.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:20:20.51#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:20.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:20.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:20.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:20.63#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:20:20.63#ibcon#first serial, iclass 36, count 0 2006.245.07:20:20.63#ibcon#enter sib2, iclass 36, count 0 2006.245.07:20:20.63#ibcon#flushed, iclass 36, count 0 2006.245.07:20:20.63#ibcon#about to write, iclass 36, count 0 2006.245.07:20:20.63#ibcon#wrote, iclass 36, count 0 2006.245.07:20:20.63#ibcon#about to read 3, iclass 36, count 0 2006.245.07:20:20.65#ibcon#read 3, iclass 36, count 0 2006.245.07:20:20.65#ibcon#about to read 4, iclass 36, count 0 2006.245.07:20:20.65#ibcon#read 4, iclass 36, count 0 2006.245.07:20:20.65#ibcon#about to read 5, iclass 36, count 0 2006.245.07:20:20.65#ibcon#read 5, iclass 36, count 0 2006.245.07:20:20.65#ibcon#about to read 6, iclass 36, count 0 2006.245.07:20:20.65#ibcon#read 6, iclass 36, count 0 2006.245.07:20:20.65#ibcon#end of sib2, iclass 36, count 0 2006.245.07:20:20.65#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:20:20.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:20:20.65#ibcon#[25=USB\r\n] 2006.245.07:20:20.65#ibcon#*before write, iclass 36, count 0 2006.245.07:20:20.65#ibcon#enter sib2, iclass 36, count 0 2006.245.07:20:20.65#ibcon#flushed, iclass 36, count 0 2006.245.07:20:20.65#ibcon#about to write, iclass 36, count 0 2006.245.07:20:20.65#ibcon#wrote, iclass 36, count 0 2006.245.07:20:20.65#ibcon#about to read 3, iclass 36, count 0 2006.245.07:20:20.68#ibcon#read 3, iclass 36, count 0 2006.245.07:20:20.68#ibcon#about to read 4, iclass 36, count 0 2006.245.07:20:20.68#ibcon#read 4, iclass 36, count 0 2006.245.07:20:20.68#ibcon#about to read 5, iclass 36, count 0 2006.245.07:20:20.68#ibcon#read 5, iclass 36, count 0 2006.245.07:20:20.68#ibcon#about to read 6, iclass 36, count 0 2006.245.07:20:20.68#ibcon#read 6, iclass 36, count 0 2006.245.07:20:20.68#ibcon#end of sib2, iclass 36, count 0 2006.245.07:20:20.68#ibcon#*after write, iclass 36, count 0 2006.245.07:20:20.68#ibcon#*before return 0, iclass 36, count 0 2006.245.07:20:20.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:20.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:20.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:20:20.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:20:20.68$vc4f8/valo=3,672.99 2006.245.07:20:20.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:20:20.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:20:20.68#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:20.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:20.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:20.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:20.68#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:20:20.68#ibcon#first serial, iclass 38, count 0 2006.245.07:20:20.68#ibcon#enter sib2, iclass 38, count 0 2006.245.07:20:20.68#ibcon#flushed, iclass 38, count 0 2006.245.07:20:20.68#ibcon#about to write, iclass 38, count 0 2006.245.07:20:20.68#ibcon#wrote, iclass 38, count 0 2006.245.07:20:20.68#ibcon#about to read 3, iclass 38, count 0 2006.245.07:20:20.71#ibcon#read 3, iclass 38, count 0 2006.245.07:20:20.71#ibcon#about to read 4, iclass 38, count 0 2006.245.07:20:20.71#ibcon#read 4, iclass 38, count 0 2006.245.07:20:20.71#ibcon#about to read 5, iclass 38, count 0 2006.245.07:20:20.71#ibcon#read 5, iclass 38, count 0 2006.245.07:20:20.71#ibcon#about to read 6, iclass 38, count 0 2006.245.07:20:20.71#ibcon#read 6, iclass 38, count 0 2006.245.07:20:20.71#ibcon#end of sib2, iclass 38, count 0 2006.245.07:20:20.71#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:20:20.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:20:20.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:20:20.71#ibcon#*before write, iclass 38, count 0 2006.245.07:20:20.71#ibcon#enter sib2, iclass 38, count 0 2006.245.07:20:20.71#ibcon#flushed, iclass 38, count 0 2006.245.07:20:20.71#ibcon#about to write, iclass 38, count 0 2006.245.07:20:20.71#ibcon#wrote, iclass 38, count 0 2006.245.07:20:20.71#ibcon#about to read 3, iclass 38, count 0 2006.245.07:20:20.75#ibcon#read 3, iclass 38, count 0 2006.245.07:20:20.75#ibcon#about to read 4, iclass 38, count 0 2006.245.07:20:20.75#ibcon#read 4, iclass 38, count 0 2006.245.07:20:20.75#ibcon#about to read 5, iclass 38, count 0 2006.245.07:20:20.75#ibcon#read 5, iclass 38, count 0 2006.245.07:20:20.75#ibcon#about to read 6, iclass 38, count 0 2006.245.07:20:20.75#ibcon#read 6, iclass 38, count 0 2006.245.07:20:20.75#ibcon#end of sib2, iclass 38, count 0 2006.245.07:20:20.75#ibcon#*after write, iclass 38, count 0 2006.245.07:20:20.75#ibcon#*before return 0, iclass 38, count 0 2006.245.07:20:20.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:20.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:20.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:20:20.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:20:20.75$vc4f8/va=3,6 2006.245.07:20:20.75#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:20:20.75#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:20:20.75#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:20.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:20.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:20.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:20.81#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:20:20.81#ibcon#first serial, iclass 40, count 2 2006.245.07:20:20.81#ibcon#enter sib2, iclass 40, count 2 2006.245.07:20:20.81#ibcon#flushed, iclass 40, count 2 2006.245.07:20:20.81#ibcon#about to write, iclass 40, count 2 2006.245.07:20:20.81#ibcon#wrote, iclass 40, count 2 2006.245.07:20:20.81#ibcon#about to read 3, iclass 40, count 2 2006.245.07:20:20.82#ibcon#read 3, iclass 40, count 2 2006.245.07:20:20.82#ibcon#about to read 4, iclass 40, count 2 2006.245.07:20:20.82#ibcon#read 4, iclass 40, count 2 2006.245.07:20:20.82#ibcon#about to read 5, iclass 40, count 2 2006.245.07:20:20.82#ibcon#read 5, iclass 40, count 2 2006.245.07:20:20.82#ibcon#about to read 6, iclass 40, count 2 2006.245.07:20:20.82#ibcon#read 6, iclass 40, count 2 2006.245.07:20:20.82#ibcon#end of sib2, iclass 40, count 2 2006.245.07:20:20.82#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:20:20.82#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:20:20.82#ibcon#[25=AT03-06\r\n] 2006.245.07:20:20.82#ibcon#*before write, iclass 40, count 2 2006.245.07:20:20.82#ibcon#enter sib2, iclass 40, count 2 2006.245.07:20:20.82#ibcon#flushed, iclass 40, count 2 2006.245.07:20:20.82#ibcon#about to write, iclass 40, count 2 2006.245.07:20:20.82#ibcon#wrote, iclass 40, count 2 2006.245.07:20:20.82#ibcon#about to read 3, iclass 40, count 2 2006.245.07:20:20.85#ibcon#read 3, iclass 40, count 2 2006.245.07:20:20.85#ibcon#about to read 4, iclass 40, count 2 2006.245.07:20:20.85#ibcon#read 4, iclass 40, count 2 2006.245.07:20:20.85#ibcon#about to read 5, iclass 40, count 2 2006.245.07:20:20.85#ibcon#read 5, iclass 40, count 2 2006.245.07:20:20.85#ibcon#about to read 6, iclass 40, count 2 2006.245.07:20:20.85#ibcon#read 6, iclass 40, count 2 2006.245.07:20:20.85#ibcon#end of sib2, iclass 40, count 2 2006.245.07:20:20.85#ibcon#*after write, iclass 40, count 2 2006.245.07:20:20.85#ibcon#*before return 0, iclass 40, count 2 2006.245.07:20:20.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:20.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:20.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:20:20.85#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:20.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:20.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:20.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:20.97#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:20:20.97#ibcon#first serial, iclass 40, count 0 2006.245.07:20:20.97#ibcon#enter sib2, iclass 40, count 0 2006.245.07:20:20.97#ibcon#flushed, iclass 40, count 0 2006.245.07:20:20.97#ibcon#about to write, iclass 40, count 0 2006.245.07:20:20.97#ibcon#wrote, iclass 40, count 0 2006.245.07:20:20.97#ibcon#about to read 3, iclass 40, count 0 2006.245.07:20:20.99#ibcon#read 3, iclass 40, count 0 2006.245.07:20:20.99#ibcon#about to read 4, iclass 40, count 0 2006.245.07:20:20.99#ibcon#read 4, iclass 40, count 0 2006.245.07:20:20.99#ibcon#about to read 5, iclass 40, count 0 2006.245.07:20:20.99#ibcon#read 5, iclass 40, count 0 2006.245.07:20:20.99#ibcon#about to read 6, iclass 40, count 0 2006.245.07:20:20.99#ibcon#read 6, iclass 40, count 0 2006.245.07:20:20.99#ibcon#end of sib2, iclass 40, count 0 2006.245.07:20:20.99#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:20:20.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:20:20.99#ibcon#[25=USB\r\n] 2006.245.07:20:20.99#ibcon#*before write, iclass 40, count 0 2006.245.07:20:20.99#ibcon#enter sib2, iclass 40, count 0 2006.245.07:20:20.99#ibcon#flushed, iclass 40, count 0 2006.245.07:20:20.99#ibcon#about to write, iclass 40, count 0 2006.245.07:20:20.99#ibcon#wrote, iclass 40, count 0 2006.245.07:20:20.99#ibcon#about to read 3, iclass 40, count 0 2006.245.07:20:21.02#ibcon#read 3, iclass 40, count 0 2006.245.07:20:21.02#ibcon#about to read 4, iclass 40, count 0 2006.245.07:20:21.02#ibcon#read 4, iclass 40, count 0 2006.245.07:20:21.02#ibcon#about to read 5, iclass 40, count 0 2006.245.07:20:21.02#ibcon#read 5, iclass 40, count 0 2006.245.07:20:21.02#ibcon#about to read 6, iclass 40, count 0 2006.245.07:20:21.02#ibcon#read 6, iclass 40, count 0 2006.245.07:20:21.02#ibcon#end of sib2, iclass 40, count 0 2006.245.07:20:21.02#ibcon#*after write, iclass 40, count 0 2006.245.07:20:21.02#ibcon#*before return 0, iclass 40, count 0 2006.245.07:20:21.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:21.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:21.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:20:21.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:20:21.02$vc4f8/valo=4,832.99 2006.245.07:20:21.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:20:21.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:20:21.02#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:21.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:21.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:21.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:21.02#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:20:21.02#ibcon#first serial, iclass 4, count 0 2006.245.07:20:21.02#ibcon#enter sib2, iclass 4, count 0 2006.245.07:20:21.02#ibcon#flushed, iclass 4, count 0 2006.245.07:20:21.02#ibcon#about to write, iclass 4, count 0 2006.245.07:20:21.02#ibcon#wrote, iclass 4, count 0 2006.245.07:20:21.02#ibcon#about to read 3, iclass 4, count 0 2006.245.07:20:21.04#ibcon#read 3, iclass 4, count 0 2006.245.07:20:21.04#ibcon#about to read 4, iclass 4, count 0 2006.245.07:20:21.04#ibcon#read 4, iclass 4, count 0 2006.245.07:20:21.04#ibcon#about to read 5, iclass 4, count 0 2006.245.07:20:21.04#ibcon#read 5, iclass 4, count 0 2006.245.07:20:21.04#ibcon#about to read 6, iclass 4, count 0 2006.245.07:20:21.04#ibcon#read 6, iclass 4, count 0 2006.245.07:20:21.04#ibcon#end of sib2, iclass 4, count 0 2006.245.07:20:21.04#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:20:21.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:20:21.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:20:21.04#ibcon#*before write, iclass 4, count 0 2006.245.07:20:21.04#ibcon#enter sib2, iclass 4, count 0 2006.245.07:20:21.04#ibcon#flushed, iclass 4, count 0 2006.245.07:20:21.04#ibcon#about to write, iclass 4, count 0 2006.245.07:20:21.04#ibcon#wrote, iclass 4, count 0 2006.245.07:20:21.04#ibcon#about to read 3, iclass 4, count 0 2006.245.07:20:21.08#ibcon#read 3, iclass 4, count 0 2006.245.07:20:21.08#ibcon#about to read 4, iclass 4, count 0 2006.245.07:20:21.08#ibcon#read 4, iclass 4, count 0 2006.245.07:20:21.08#ibcon#about to read 5, iclass 4, count 0 2006.245.07:20:21.08#ibcon#read 5, iclass 4, count 0 2006.245.07:20:21.08#ibcon#about to read 6, iclass 4, count 0 2006.245.07:20:21.08#ibcon#read 6, iclass 4, count 0 2006.245.07:20:21.08#ibcon#end of sib2, iclass 4, count 0 2006.245.07:20:21.08#ibcon#*after write, iclass 4, count 0 2006.245.07:20:21.08#ibcon#*before return 0, iclass 4, count 0 2006.245.07:20:21.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:21.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:21.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:20:21.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:20:21.08$vc4f8/va=4,7 2006.245.07:20:21.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:20:21.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:20:21.08#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:21.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:21.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:21.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:21.14#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:20:21.14#ibcon#first serial, iclass 6, count 2 2006.245.07:20:21.14#ibcon#enter sib2, iclass 6, count 2 2006.245.07:20:21.14#ibcon#flushed, iclass 6, count 2 2006.245.07:20:21.14#ibcon#about to write, iclass 6, count 2 2006.245.07:20:21.14#ibcon#wrote, iclass 6, count 2 2006.245.07:20:21.14#ibcon#about to read 3, iclass 6, count 2 2006.245.07:20:21.16#ibcon#read 3, iclass 6, count 2 2006.245.07:20:21.16#ibcon#about to read 4, iclass 6, count 2 2006.245.07:20:21.16#ibcon#read 4, iclass 6, count 2 2006.245.07:20:21.16#ibcon#about to read 5, iclass 6, count 2 2006.245.07:20:21.16#ibcon#read 5, iclass 6, count 2 2006.245.07:20:21.16#ibcon#about to read 6, iclass 6, count 2 2006.245.07:20:21.16#ibcon#read 6, iclass 6, count 2 2006.245.07:20:21.16#ibcon#end of sib2, iclass 6, count 2 2006.245.07:20:21.16#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:20:21.16#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:20:21.16#ibcon#[25=AT04-07\r\n] 2006.245.07:20:21.16#ibcon#*before write, iclass 6, count 2 2006.245.07:20:21.16#ibcon#enter sib2, iclass 6, count 2 2006.245.07:20:21.16#ibcon#flushed, iclass 6, count 2 2006.245.07:20:21.16#ibcon#about to write, iclass 6, count 2 2006.245.07:20:21.16#ibcon#wrote, iclass 6, count 2 2006.245.07:20:21.16#ibcon#about to read 3, iclass 6, count 2 2006.245.07:20:21.19#ibcon#read 3, iclass 6, count 2 2006.245.07:20:21.19#ibcon#about to read 4, iclass 6, count 2 2006.245.07:20:21.19#ibcon#read 4, iclass 6, count 2 2006.245.07:20:21.19#ibcon#about to read 5, iclass 6, count 2 2006.245.07:20:21.19#ibcon#read 5, iclass 6, count 2 2006.245.07:20:21.19#ibcon#about to read 6, iclass 6, count 2 2006.245.07:20:21.19#ibcon#read 6, iclass 6, count 2 2006.245.07:20:21.19#ibcon#end of sib2, iclass 6, count 2 2006.245.07:20:21.19#ibcon#*after write, iclass 6, count 2 2006.245.07:20:21.19#ibcon#*before return 0, iclass 6, count 2 2006.245.07:20:21.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:21.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:21.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:20:21.19#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:21.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:21.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:21.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:21.31#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:20:21.31#ibcon#first serial, iclass 6, count 0 2006.245.07:20:21.31#ibcon#enter sib2, iclass 6, count 0 2006.245.07:20:21.31#ibcon#flushed, iclass 6, count 0 2006.245.07:20:21.31#ibcon#about to write, iclass 6, count 0 2006.245.07:20:21.31#ibcon#wrote, iclass 6, count 0 2006.245.07:20:21.31#ibcon#about to read 3, iclass 6, count 0 2006.245.07:20:21.33#ibcon#read 3, iclass 6, count 0 2006.245.07:20:21.33#ibcon#about to read 4, iclass 6, count 0 2006.245.07:20:21.33#ibcon#read 4, iclass 6, count 0 2006.245.07:20:21.33#ibcon#about to read 5, iclass 6, count 0 2006.245.07:20:21.33#ibcon#read 5, iclass 6, count 0 2006.245.07:20:21.33#ibcon#about to read 6, iclass 6, count 0 2006.245.07:20:21.33#ibcon#read 6, iclass 6, count 0 2006.245.07:20:21.33#ibcon#end of sib2, iclass 6, count 0 2006.245.07:20:21.33#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:20:21.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:20:21.33#ibcon#[25=USB\r\n] 2006.245.07:20:21.33#ibcon#*before write, iclass 6, count 0 2006.245.07:20:21.33#ibcon#enter sib2, iclass 6, count 0 2006.245.07:20:21.33#ibcon#flushed, iclass 6, count 0 2006.245.07:20:21.33#ibcon#about to write, iclass 6, count 0 2006.245.07:20:21.33#ibcon#wrote, iclass 6, count 0 2006.245.07:20:21.33#ibcon#about to read 3, iclass 6, count 0 2006.245.07:20:21.36#ibcon#read 3, iclass 6, count 0 2006.245.07:20:21.36#ibcon#about to read 4, iclass 6, count 0 2006.245.07:20:21.36#ibcon#read 4, iclass 6, count 0 2006.245.07:20:21.36#ibcon#about to read 5, iclass 6, count 0 2006.245.07:20:21.36#ibcon#read 5, iclass 6, count 0 2006.245.07:20:21.36#ibcon#about to read 6, iclass 6, count 0 2006.245.07:20:21.36#ibcon#read 6, iclass 6, count 0 2006.245.07:20:21.36#ibcon#end of sib2, iclass 6, count 0 2006.245.07:20:21.36#ibcon#*after write, iclass 6, count 0 2006.245.07:20:21.36#ibcon#*before return 0, iclass 6, count 0 2006.245.07:20:21.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:21.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:21.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:20:21.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:20:21.36$vc4f8/valo=5,652.99 2006.245.07:20:21.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:20:21.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:20:21.36#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:21.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:21.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:21.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:21.36#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:20:21.36#ibcon#first serial, iclass 10, count 0 2006.245.07:20:21.36#ibcon#enter sib2, iclass 10, count 0 2006.245.07:20:21.36#ibcon#flushed, iclass 10, count 0 2006.245.07:20:21.36#ibcon#about to write, iclass 10, count 0 2006.245.07:20:21.36#ibcon#wrote, iclass 10, count 0 2006.245.07:20:21.36#ibcon#about to read 3, iclass 10, count 0 2006.245.07:20:21.38#ibcon#read 3, iclass 10, count 0 2006.245.07:20:21.38#ibcon#about to read 4, iclass 10, count 0 2006.245.07:20:21.38#ibcon#read 4, iclass 10, count 0 2006.245.07:20:21.38#ibcon#about to read 5, iclass 10, count 0 2006.245.07:20:21.38#ibcon#read 5, iclass 10, count 0 2006.245.07:20:21.38#ibcon#about to read 6, iclass 10, count 0 2006.245.07:20:21.38#ibcon#read 6, iclass 10, count 0 2006.245.07:20:21.38#ibcon#end of sib2, iclass 10, count 0 2006.245.07:20:21.38#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:20:21.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:20:21.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:20:21.38#ibcon#*before write, iclass 10, count 0 2006.245.07:20:21.38#ibcon#enter sib2, iclass 10, count 0 2006.245.07:20:21.38#ibcon#flushed, iclass 10, count 0 2006.245.07:20:21.38#ibcon#about to write, iclass 10, count 0 2006.245.07:20:21.38#ibcon#wrote, iclass 10, count 0 2006.245.07:20:21.38#ibcon#about to read 3, iclass 10, count 0 2006.245.07:20:21.42#ibcon#read 3, iclass 10, count 0 2006.245.07:20:21.42#ibcon#about to read 4, iclass 10, count 0 2006.245.07:20:21.42#ibcon#read 4, iclass 10, count 0 2006.245.07:20:21.42#ibcon#about to read 5, iclass 10, count 0 2006.245.07:20:21.42#ibcon#read 5, iclass 10, count 0 2006.245.07:20:21.42#ibcon#about to read 6, iclass 10, count 0 2006.245.07:20:21.42#ibcon#read 6, iclass 10, count 0 2006.245.07:20:21.42#ibcon#end of sib2, iclass 10, count 0 2006.245.07:20:21.42#ibcon#*after write, iclass 10, count 0 2006.245.07:20:21.42#ibcon#*before return 0, iclass 10, count 0 2006.245.07:20:21.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:21.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:21.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:20:21.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:20:21.42$vc4f8/va=5,7 2006.245.07:20:21.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:20:21.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:20:21.42#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:21.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:21.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:21.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:21.49#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:20:21.49#ibcon#first serial, iclass 12, count 2 2006.245.07:20:21.49#ibcon#enter sib2, iclass 12, count 2 2006.245.07:20:21.49#ibcon#flushed, iclass 12, count 2 2006.245.07:20:21.49#ibcon#about to write, iclass 12, count 2 2006.245.07:20:21.49#ibcon#wrote, iclass 12, count 2 2006.245.07:20:21.49#ibcon#about to read 3, iclass 12, count 2 2006.245.07:20:21.50#ibcon#read 3, iclass 12, count 2 2006.245.07:20:21.50#ibcon#about to read 4, iclass 12, count 2 2006.245.07:20:21.50#ibcon#read 4, iclass 12, count 2 2006.245.07:20:21.50#ibcon#about to read 5, iclass 12, count 2 2006.245.07:20:21.50#ibcon#read 5, iclass 12, count 2 2006.245.07:20:21.50#ibcon#about to read 6, iclass 12, count 2 2006.245.07:20:21.50#ibcon#read 6, iclass 12, count 2 2006.245.07:20:21.50#ibcon#end of sib2, iclass 12, count 2 2006.245.07:20:21.50#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:20:21.50#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:20:21.50#ibcon#[25=AT05-07\r\n] 2006.245.07:20:21.50#ibcon#*before write, iclass 12, count 2 2006.245.07:20:21.50#ibcon#enter sib2, iclass 12, count 2 2006.245.07:20:21.50#ibcon#flushed, iclass 12, count 2 2006.245.07:20:21.50#ibcon#about to write, iclass 12, count 2 2006.245.07:20:21.50#ibcon#wrote, iclass 12, count 2 2006.245.07:20:21.50#ibcon#about to read 3, iclass 12, count 2 2006.245.07:20:21.53#ibcon#read 3, iclass 12, count 2 2006.245.07:20:21.53#ibcon#about to read 4, iclass 12, count 2 2006.245.07:20:21.53#ibcon#read 4, iclass 12, count 2 2006.245.07:20:21.53#ibcon#about to read 5, iclass 12, count 2 2006.245.07:20:21.53#ibcon#read 5, iclass 12, count 2 2006.245.07:20:21.53#ibcon#about to read 6, iclass 12, count 2 2006.245.07:20:21.53#ibcon#read 6, iclass 12, count 2 2006.245.07:20:21.53#ibcon#end of sib2, iclass 12, count 2 2006.245.07:20:21.53#ibcon#*after write, iclass 12, count 2 2006.245.07:20:21.53#ibcon#*before return 0, iclass 12, count 2 2006.245.07:20:21.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:21.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:21.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:20:21.53#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:21.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:21.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:21.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:21.65#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:20:21.65#ibcon#first serial, iclass 12, count 0 2006.245.07:20:21.65#ibcon#enter sib2, iclass 12, count 0 2006.245.07:20:21.65#ibcon#flushed, iclass 12, count 0 2006.245.07:20:21.65#ibcon#about to write, iclass 12, count 0 2006.245.07:20:21.65#ibcon#wrote, iclass 12, count 0 2006.245.07:20:21.65#ibcon#about to read 3, iclass 12, count 0 2006.245.07:20:21.67#ibcon#read 3, iclass 12, count 0 2006.245.07:20:21.67#ibcon#about to read 4, iclass 12, count 0 2006.245.07:20:21.67#ibcon#read 4, iclass 12, count 0 2006.245.07:20:21.67#ibcon#about to read 5, iclass 12, count 0 2006.245.07:20:21.67#ibcon#read 5, iclass 12, count 0 2006.245.07:20:21.67#ibcon#about to read 6, iclass 12, count 0 2006.245.07:20:21.67#ibcon#read 6, iclass 12, count 0 2006.245.07:20:21.67#ibcon#end of sib2, iclass 12, count 0 2006.245.07:20:21.67#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:20:21.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:20:21.67#ibcon#[25=USB\r\n] 2006.245.07:20:21.67#ibcon#*before write, iclass 12, count 0 2006.245.07:20:21.67#ibcon#enter sib2, iclass 12, count 0 2006.245.07:20:21.67#ibcon#flushed, iclass 12, count 0 2006.245.07:20:21.67#ibcon#about to write, iclass 12, count 0 2006.245.07:20:21.67#ibcon#wrote, iclass 12, count 0 2006.245.07:20:21.67#ibcon#about to read 3, iclass 12, count 0 2006.245.07:20:21.70#ibcon#read 3, iclass 12, count 0 2006.245.07:20:21.70#ibcon#about to read 4, iclass 12, count 0 2006.245.07:20:21.70#ibcon#read 4, iclass 12, count 0 2006.245.07:20:21.70#ibcon#about to read 5, iclass 12, count 0 2006.245.07:20:21.70#ibcon#read 5, iclass 12, count 0 2006.245.07:20:21.70#ibcon#about to read 6, iclass 12, count 0 2006.245.07:20:21.70#ibcon#read 6, iclass 12, count 0 2006.245.07:20:21.70#ibcon#end of sib2, iclass 12, count 0 2006.245.07:20:21.70#ibcon#*after write, iclass 12, count 0 2006.245.07:20:21.70#ibcon#*before return 0, iclass 12, count 0 2006.245.07:20:21.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:21.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:21.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:20:21.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:20:21.70$vc4f8/valo=6,772.99 2006.245.07:20:21.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:20:21.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:20:21.70#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:21.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:21.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:21.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:21.70#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:20:21.70#ibcon#first serial, iclass 14, count 0 2006.245.07:20:21.70#ibcon#enter sib2, iclass 14, count 0 2006.245.07:20:21.70#ibcon#flushed, iclass 14, count 0 2006.245.07:20:21.70#ibcon#about to write, iclass 14, count 0 2006.245.07:20:21.70#ibcon#wrote, iclass 14, count 0 2006.245.07:20:21.70#ibcon#about to read 3, iclass 14, count 0 2006.245.07:20:21.73#ibcon#read 3, iclass 14, count 0 2006.245.07:20:21.73#ibcon#about to read 4, iclass 14, count 0 2006.245.07:20:21.73#ibcon#read 4, iclass 14, count 0 2006.245.07:20:21.73#ibcon#about to read 5, iclass 14, count 0 2006.245.07:20:21.73#ibcon#read 5, iclass 14, count 0 2006.245.07:20:21.73#ibcon#about to read 6, iclass 14, count 0 2006.245.07:20:21.73#ibcon#read 6, iclass 14, count 0 2006.245.07:20:21.73#ibcon#end of sib2, iclass 14, count 0 2006.245.07:20:21.73#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:20:21.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:20:21.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:20:21.73#ibcon#*before write, iclass 14, count 0 2006.245.07:20:21.73#ibcon#enter sib2, iclass 14, count 0 2006.245.07:20:21.73#ibcon#flushed, iclass 14, count 0 2006.245.07:20:21.73#ibcon#about to write, iclass 14, count 0 2006.245.07:20:21.73#ibcon#wrote, iclass 14, count 0 2006.245.07:20:21.73#ibcon#about to read 3, iclass 14, count 0 2006.245.07:20:21.77#ibcon#read 3, iclass 14, count 0 2006.245.07:20:21.77#ibcon#about to read 4, iclass 14, count 0 2006.245.07:20:21.77#ibcon#read 4, iclass 14, count 0 2006.245.07:20:21.77#ibcon#about to read 5, iclass 14, count 0 2006.245.07:20:21.77#ibcon#read 5, iclass 14, count 0 2006.245.07:20:21.77#ibcon#about to read 6, iclass 14, count 0 2006.245.07:20:21.77#ibcon#read 6, iclass 14, count 0 2006.245.07:20:21.77#ibcon#end of sib2, iclass 14, count 0 2006.245.07:20:21.77#ibcon#*after write, iclass 14, count 0 2006.245.07:20:21.77#ibcon#*before return 0, iclass 14, count 0 2006.245.07:20:21.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:21.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:21.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:20:21.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:20:21.77$vc4f8/va=6,7 2006.245.07:20:21.77#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.07:20:21.77#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.07:20:21.77#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:21.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:20:21.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:20:21.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:20:21.83#ibcon#enter wrdev, iclass 16, count 2 2006.245.07:20:21.83#ibcon#first serial, iclass 16, count 2 2006.245.07:20:21.83#ibcon#enter sib2, iclass 16, count 2 2006.245.07:20:21.83#ibcon#flushed, iclass 16, count 2 2006.245.07:20:21.83#ibcon#about to write, iclass 16, count 2 2006.245.07:20:21.83#ibcon#wrote, iclass 16, count 2 2006.245.07:20:21.83#ibcon#about to read 3, iclass 16, count 2 2006.245.07:20:21.84#ibcon#read 3, iclass 16, count 2 2006.245.07:20:21.84#ibcon#about to read 4, iclass 16, count 2 2006.245.07:20:21.84#ibcon#read 4, iclass 16, count 2 2006.245.07:20:21.84#ibcon#about to read 5, iclass 16, count 2 2006.245.07:20:21.84#ibcon#read 5, iclass 16, count 2 2006.245.07:20:21.84#ibcon#about to read 6, iclass 16, count 2 2006.245.07:20:21.84#ibcon#read 6, iclass 16, count 2 2006.245.07:20:21.84#ibcon#end of sib2, iclass 16, count 2 2006.245.07:20:21.84#ibcon#*mode == 0, iclass 16, count 2 2006.245.07:20:21.84#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.07:20:21.84#ibcon#[25=AT06-07\r\n] 2006.245.07:20:21.84#ibcon#*before write, iclass 16, count 2 2006.245.07:20:21.84#ibcon#enter sib2, iclass 16, count 2 2006.245.07:20:21.84#ibcon#flushed, iclass 16, count 2 2006.245.07:20:21.84#ibcon#about to write, iclass 16, count 2 2006.245.07:20:21.84#ibcon#wrote, iclass 16, count 2 2006.245.07:20:21.84#ibcon#about to read 3, iclass 16, count 2 2006.245.07:20:21.87#ibcon#read 3, iclass 16, count 2 2006.245.07:20:21.87#ibcon#about to read 4, iclass 16, count 2 2006.245.07:20:21.87#ibcon#read 4, iclass 16, count 2 2006.245.07:20:21.87#ibcon#about to read 5, iclass 16, count 2 2006.245.07:20:21.87#ibcon#read 5, iclass 16, count 2 2006.245.07:20:21.87#ibcon#about to read 6, iclass 16, count 2 2006.245.07:20:21.87#ibcon#read 6, iclass 16, count 2 2006.245.07:20:21.87#ibcon#end of sib2, iclass 16, count 2 2006.245.07:20:21.87#ibcon#*after write, iclass 16, count 2 2006.245.07:20:21.87#ibcon#*before return 0, iclass 16, count 2 2006.245.07:20:21.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:20:21.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:20:21.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.07:20:21.87#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:21.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:20:21.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:20:21.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:20:21.99#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:20:21.99#ibcon#first serial, iclass 16, count 0 2006.245.07:20:21.99#ibcon#enter sib2, iclass 16, count 0 2006.245.07:20:21.99#ibcon#flushed, iclass 16, count 0 2006.245.07:20:21.99#ibcon#about to write, iclass 16, count 0 2006.245.07:20:21.99#ibcon#wrote, iclass 16, count 0 2006.245.07:20:21.99#ibcon#about to read 3, iclass 16, count 0 2006.245.07:20:22.01#ibcon#read 3, iclass 16, count 0 2006.245.07:20:22.01#ibcon#about to read 4, iclass 16, count 0 2006.245.07:20:22.01#ibcon#read 4, iclass 16, count 0 2006.245.07:20:22.01#ibcon#about to read 5, iclass 16, count 0 2006.245.07:20:22.01#ibcon#read 5, iclass 16, count 0 2006.245.07:20:22.01#ibcon#about to read 6, iclass 16, count 0 2006.245.07:20:22.01#ibcon#read 6, iclass 16, count 0 2006.245.07:20:22.01#ibcon#end of sib2, iclass 16, count 0 2006.245.07:20:22.01#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:20:22.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:20:22.01#ibcon#[25=USB\r\n] 2006.245.07:20:22.01#ibcon#*before write, iclass 16, count 0 2006.245.07:20:22.01#ibcon#enter sib2, iclass 16, count 0 2006.245.07:20:22.01#ibcon#flushed, iclass 16, count 0 2006.245.07:20:22.01#ibcon#about to write, iclass 16, count 0 2006.245.07:20:22.01#ibcon#wrote, iclass 16, count 0 2006.245.07:20:22.01#ibcon#about to read 3, iclass 16, count 0 2006.245.07:20:22.04#ibcon#read 3, iclass 16, count 0 2006.245.07:20:22.04#ibcon#about to read 4, iclass 16, count 0 2006.245.07:20:22.04#ibcon#read 4, iclass 16, count 0 2006.245.07:20:22.04#ibcon#about to read 5, iclass 16, count 0 2006.245.07:20:22.04#ibcon#read 5, iclass 16, count 0 2006.245.07:20:22.04#ibcon#about to read 6, iclass 16, count 0 2006.245.07:20:22.04#ibcon#read 6, iclass 16, count 0 2006.245.07:20:22.04#ibcon#end of sib2, iclass 16, count 0 2006.245.07:20:22.04#ibcon#*after write, iclass 16, count 0 2006.245.07:20:22.04#ibcon#*before return 0, iclass 16, count 0 2006.245.07:20:22.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:20:22.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:20:22.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:20:22.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:20:22.04$vc4f8/valo=7,832.99 2006.245.07:20:22.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.07:20:22.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.07:20:22.04#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:22.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:20:22.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:20:22.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:20:22.04#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:20:22.04#ibcon#first serial, iclass 18, count 0 2006.245.07:20:22.04#ibcon#enter sib2, iclass 18, count 0 2006.245.07:20:22.04#ibcon#flushed, iclass 18, count 0 2006.245.07:20:22.04#ibcon#about to write, iclass 18, count 0 2006.245.07:20:22.04#ibcon#wrote, iclass 18, count 0 2006.245.07:20:22.04#ibcon#about to read 3, iclass 18, count 0 2006.245.07:20:22.06#ibcon#read 3, iclass 18, count 0 2006.245.07:20:22.06#ibcon#about to read 4, iclass 18, count 0 2006.245.07:20:22.06#ibcon#read 4, iclass 18, count 0 2006.245.07:20:22.06#ibcon#about to read 5, iclass 18, count 0 2006.245.07:20:22.06#ibcon#read 5, iclass 18, count 0 2006.245.07:20:22.06#ibcon#about to read 6, iclass 18, count 0 2006.245.07:20:22.06#ibcon#read 6, iclass 18, count 0 2006.245.07:20:22.06#ibcon#end of sib2, iclass 18, count 0 2006.245.07:20:22.06#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:20:22.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:20:22.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:20:22.06#ibcon#*before write, iclass 18, count 0 2006.245.07:20:22.06#ibcon#enter sib2, iclass 18, count 0 2006.245.07:20:22.06#ibcon#flushed, iclass 18, count 0 2006.245.07:20:22.06#ibcon#about to write, iclass 18, count 0 2006.245.07:20:22.06#ibcon#wrote, iclass 18, count 0 2006.245.07:20:22.06#ibcon#about to read 3, iclass 18, count 0 2006.245.07:20:22.10#ibcon#read 3, iclass 18, count 0 2006.245.07:20:22.10#ibcon#about to read 4, iclass 18, count 0 2006.245.07:20:22.10#ibcon#read 4, iclass 18, count 0 2006.245.07:20:22.10#ibcon#about to read 5, iclass 18, count 0 2006.245.07:20:22.10#ibcon#read 5, iclass 18, count 0 2006.245.07:20:22.10#ibcon#about to read 6, iclass 18, count 0 2006.245.07:20:22.10#ibcon#read 6, iclass 18, count 0 2006.245.07:20:22.10#ibcon#end of sib2, iclass 18, count 0 2006.245.07:20:22.10#ibcon#*after write, iclass 18, count 0 2006.245.07:20:22.10#ibcon#*before return 0, iclass 18, count 0 2006.245.07:20:22.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:20:22.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:20:22.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:20:22.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:20:22.10$vc4f8/va=7,7 2006.245.07:20:22.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.07:20:22.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.07:20:22.10#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:22.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:20:22.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:20:22.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:20:22.16#ibcon#enter wrdev, iclass 20, count 2 2006.245.07:20:22.16#ibcon#first serial, iclass 20, count 2 2006.245.07:20:22.16#ibcon#enter sib2, iclass 20, count 2 2006.245.07:20:22.16#ibcon#flushed, iclass 20, count 2 2006.245.07:20:22.16#ibcon#about to write, iclass 20, count 2 2006.245.07:20:22.16#ibcon#wrote, iclass 20, count 2 2006.245.07:20:22.16#ibcon#about to read 3, iclass 20, count 2 2006.245.07:20:22.18#ibcon#read 3, iclass 20, count 2 2006.245.07:20:22.18#ibcon#about to read 4, iclass 20, count 2 2006.245.07:20:22.18#ibcon#read 4, iclass 20, count 2 2006.245.07:20:22.18#ibcon#about to read 5, iclass 20, count 2 2006.245.07:20:22.18#ibcon#read 5, iclass 20, count 2 2006.245.07:20:22.18#ibcon#about to read 6, iclass 20, count 2 2006.245.07:20:22.18#ibcon#read 6, iclass 20, count 2 2006.245.07:20:22.18#ibcon#end of sib2, iclass 20, count 2 2006.245.07:20:22.18#ibcon#*mode == 0, iclass 20, count 2 2006.245.07:20:22.18#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.07:20:22.18#ibcon#[25=AT07-07\r\n] 2006.245.07:20:22.18#ibcon#*before write, iclass 20, count 2 2006.245.07:20:22.18#ibcon#enter sib2, iclass 20, count 2 2006.245.07:20:22.18#ibcon#flushed, iclass 20, count 2 2006.245.07:20:22.18#ibcon#about to write, iclass 20, count 2 2006.245.07:20:22.18#ibcon#wrote, iclass 20, count 2 2006.245.07:20:22.18#ibcon#about to read 3, iclass 20, count 2 2006.245.07:20:22.21#ibcon#read 3, iclass 20, count 2 2006.245.07:20:22.21#ibcon#about to read 4, iclass 20, count 2 2006.245.07:20:22.21#ibcon#read 4, iclass 20, count 2 2006.245.07:20:22.21#ibcon#about to read 5, iclass 20, count 2 2006.245.07:20:22.21#ibcon#read 5, iclass 20, count 2 2006.245.07:20:22.21#ibcon#about to read 6, iclass 20, count 2 2006.245.07:20:22.21#ibcon#read 6, iclass 20, count 2 2006.245.07:20:22.21#ibcon#end of sib2, iclass 20, count 2 2006.245.07:20:22.21#ibcon#*after write, iclass 20, count 2 2006.245.07:20:22.21#ibcon#*before return 0, iclass 20, count 2 2006.245.07:20:22.21#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:20:22.21#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:20:22.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.07:20:22.21#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:22.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:20:22.33#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:20:22.33#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:20:22.33#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:20:22.33#ibcon#first serial, iclass 20, count 0 2006.245.07:20:22.33#ibcon#enter sib2, iclass 20, count 0 2006.245.07:20:22.33#ibcon#flushed, iclass 20, count 0 2006.245.07:20:22.33#ibcon#about to write, iclass 20, count 0 2006.245.07:20:22.33#ibcon#wrote, iclass 20, count 0 2006.245.07:20:22.33#ibcon#about to read 3, iclass 20, count 0 2006.245.07:20:22.35#ibcon#read 3, iclass 20, count 0 2006.245.07:20:22.35#ibcon#about to read 4, iclass 20, count 0 2006.245.07:20:22.35#ibcon#read 4, iclass 20, count 0 2006.245.07:20:22.35#ibcon#about to read 5, iclass 20, count 0 2006.245.07:20:22.35#ibcon#read 5, iclass 20, count 0 2006.245.07:20:22.35#ibcon#about to read 6, iclass 20, count 0 2006.245.07:20:22.35#ibcon#read 6, iclass 20, count 0 2006.245.07:20:22.35#ibcon#end of sib2, iclass 20, count 0 2006.245.07:20:22.35#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:20:22.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:20:22.35#ibcon#[25=USB\r\n] 2006.245.07:20:22.35#ibcon#*before write, iclass 20, count 0 2006.245.07:20:22.35#ibcon#enter sib2, iclass 20, count 0 2006.245.07:20:22.35#ibcon#flushed, iclass 20, count 0 2006.245.07:20:22.35#ibcon#about to write, iclass 20, count 0 2006.245.07:20:22.35#ibcon#wrote, iclass 20, count 0 2006.245.07:20:22.35#ibcon#about to read 3, iclass 20, count 0 2006.245.07:20:22.38#ibcon#read 3, iclass 20, count 0 2006.245.07:20:22.38#ibcon#about to read 4, iclass 20, count 0 2006.245.07:20:22.38#ibcon#read 4, iclass 20, count 0 2006.245.07:20:22.38#ibcon#about to read 5, iclass 20, count 0 2006.245.07:20:22.38#ibcon#read 5, iclass 20, count 0 2006.245.07:20:22.38#ibcon#about to read 6, iclass 20, count 0 2006.245.07:20:22.38#ibcon#read 6, iclass 20, count 0 2006.245.07:20:22.38#ibcon#end of sib2, iclass 20, count 0 2006.245.07:20:22.38#ibcon#*after write, iclass 20, count 0 2006.245.07:20:22.38#ibcon#*before return 0, iclass 20, count 0 2006.245.07:20:22.38#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:20:22.38#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:20:22.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:20:22.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:20:22.38$vc4f8/valo=8,852.99 2006.245.07:20:22.38#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.07:20:22.38#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.07:20:22.38#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:22.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:20:22.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:20:22.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:20:22.38#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:20:22.38#ibcon#first serial, iclass 22, count 0 2006.245.07:20:22.38#ibcon#enter sib2, iclass 22, count 0 2006.245.07:20:22.38#ibcon#flushed, iclass 22, count 0 2006.245.07:20:22.38#ibcon#about to write, iclass 22, count 0 2006.245.07:20:22.38#ibcon#wrote, iclass 22, count 0 2006.245.07:20:22.38#ibcon#about to read 3, iclass 22, count 0 2006.245.07:20:22.41#ibcon#read 3, iclass 22, count 0 2006.245.07:20:22.41#ibcon#about to read 4, iclass 22, count 0 2006.245.07:20:22.41#ibcon#read 4, iclass 22, count 0 2006.245.07:20:22.41#ibcon#about to read 5, iclass 22, count 0 2006.245.07:20:22.41#ibcon#read 5, iclass 22, count 0 2006.245.07:20:22.41#ibcon#about to read 6, iclass 22, count 0 2006.245.07:20:22.41#ibcon#read 6, iclass 22, count 0 2006.245.07:20:22.41#ibcon#end of sib2, iclass 22, count 0 2006.245.07:20:22.41#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:20:22.41#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:20:22.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:20:22.41#ibcon#*before write, iclass 22, count 0 2006.245.07:20:22.41#ibcon#enter sib2, iclass 22, count 0 2006.245.07:20:22.41#ibcon#flushed, iclass 22, count 0 2006.245.07:20:22.41#ibcon#about to write, iclass 22, count 0 2006.245.07:20:22.41#ibcon#wrote, iclass 22, count 0 2006.245.07:20:22.41#ibcon#about to read 3, iclass 22, count 0 2006.245.07:20:22.45#ibcon#read 3, iclass 22, count 0 2006.245.07:20:22.45#ibcon#about to read 4, iclass 22, count 0 2006.245.07:20:22.45#ibcon#read 4, iclass 22, count 0 2006.245.07:20:22.45#ibcon#about to read 5, iclass 22, count 0 2006.245.07:20:22.45#ibcon#read 5, iclass 22, count 0 2006.245.07:20:22.45#ibcon#about to read 6, iclass 22, count 0 2006.245.07:20:22.45#ibcon#read 6, iclass 22, count 0 2006.245.07:20:22.45#ibcon#end of sib2, iclass 22, count 0 2006.245.07:20:22.45#ibcon#*after write, iclass 22, count 0 2006.245.07:20:22.45#ibcon#*before return 0, iclass 22, count 0 2006.245.07:20:22.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:20:22.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:20:22.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:20:22.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:20:22.45$vc4f8/va=8,8 2006.245.07:20:22.45#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.07:20:22.45#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.07:20:22.45#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:22.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:20:22.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:20:22.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:20:22.51#ibcon#enter wrdev, iclass 24, count 2 2006.245.07:20:22.51#ibcon#first serial, iclass 24, count 2 2006.245.07:20:22.51#ibcon#enter sib2, iclass 24, count 2 2006.245.07:20:22.51#ibcon#flushed, iclass 24, count 2 2006.245.07:20:22.51#ibcon#about to write, iclass 24, count 2 2006.245.07:20:22.51#ibcon#wrote, iclass 24, count 2 2006.245.07:20:22.51#ibcon#about to read 3, iclass 24, count 2 2006.245.07:20:22.52#ibcon#read 3, iclass 24, count 2 2006.245.07:20:22.52#ibcon#about to read 4, iclass 24, count 2 2006.245.07:20:22.52#ibcon#read 4, iclass 24, count 2 2006.245.07:20:22.52#ibcon#about to read 5, iclass 24, count 2 2006.245.07:20:22.52#ibcon#read 5, iclass 24, count 2 2006.245.07:20:22.52#ibcon#about to read 6, iclass 24, count 2 2006.245.07:20:22.52#ibcon#read 6, iclass 24, count 2 2006.245.07:20:22.52#ibcon#end of sib2, iclass 24, count 2 2006.245.07:20:22.52#ibcon#*mode == 0, iclass 24, count 2 2006.245.07:20:22.52#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.07:20:22.52#ibcon#[25=AT08-08\r\n] 2006.245.07:20:22.52#ibcon#*before write, iclass 24, count 2 2006.245.07:20:22.52#ibcon#enter sib2, iclass 24, count 2 2006.245.07:20:22.52#ibcon#flushed, iclass 24, count 2 2006.245.07:20:22.52#ibcon#about to write, iclass 24, count 2 2006.245.07:20:22.52#ibcon#wrote, iclass 24, count 2 2006.245.07:20:22.52#ibcon#about to read 3, iclass 24, count 2 2006.245.07:20:22.55#ibcon#read 3, iclass 24, count 2 2006.245.07:20:22.55#ibcon#about to read 4, iclass 24, count 2 2006.245.07:20:22.55#ibcon#read 4, iclass 24, count 2 2006.245.07:20:22.55#ibcon#about to read 5, iclass 24, count 2 2006.245.07:20:22.55#ibcon#read 5, iclass 24, count 2 2006.245.07:20:22.55#ibcon#about to read 6, iclass 24, count 2 2006.245.07:20:22.55#ibcon#read 6, iclass 24, count 2 2006.245.07:20:22.55#ibcon#end of sib2, iclass 24, count 2 2006.245.07:20:22.55#ibcon#*after write, iclass 24, count 2 2006.245.07:20:22.55#ibcon#*before return 0, iclass 24, count 2 2006.245.07:20:22.55#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:20:22.55#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:20:22.55#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.07:20:22.55#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:22.55#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:20:22.67#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:20:22.67#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:20:22.67#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:20:22.67#ibcon#first serial, iclass 24, count 0 2006.245.07:20:22.67#ibcon#enter sib2, iclass 24, count 0 2006.245.07:20:22.67#ibcon#flushed, iclass 24, count 0 2006.245.07:20:22.67#ibcon#about to write, iclass 24, count 0 2006.245.07:20:22.67#ibcon#wrote, iclass 24, count 0 2006.245.07:20:22.67#ibcon#about to read 3, iclass 24, count 0 2006.245.07:20:22.69#ibcon#read 3, iclass 24, count 0 2006.245.07:20:22.69#ibcon#about to read 4, iclass 24, count 0 2006.245.07:20:22.69#ibcon#read 4, iclass 24, count 0 2006.245.07:20:22.69#ibcon#about to read 5, iclass 24, count 0 2006.245.07:20:22.69#ibcon#read 5, iclass 24, count 0 2006.245.07:20:22.69#ibcon#about to read 6, iclass 24, count 0 2006.245.07:20:22.69#ibcon#read 6, iclass 24, count 0 2006.245.07:20:22.69#ibcon#end of sib2, iclass 24, count 0 2006.245.07:20:22.69#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:20:22.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:20:22.69#ibcon#[25=USB\r\n] 2006.245.07:20:22.69#ibcon#*before write, iclass 24, count 0 2006.245.07:20:22.69#ibcon#enter sib2, iclass 24, count 0 2006.245.07:20:22.69#ibcon#flushed, iclass 24, count 0 2006.245.07:20:22.69#ibcon#about to write, iclass 24, count 0 2006.245.07:20:22.69#ibcon#wrote, iclass 24, count 0 2006.245.07:20:22.69#ibcon#about to read 3, iclass 24, count 0 2006.245.07:20:22.72#ibcon#read 3, iclass 24, count 0 2006.245.07:20:22.72#ibcon#about to read 4, iclass 24, count 0 2006.245.07:20:22.72#ibcon#read 4, iclass 24, count 0 2006.245.07:20:22.72#ibcon#about to read 5, iclass 24, count 0 2006.245.07:20:22.72#ibcon#read 5, iclass 24, count 0 2006.245.07:20:22.72#ibcon#about to read 6, iclass 24, count 0 2006.245.07:20:22.72#ibcon#read 6, iclass 24, count 0 2006.245.07:20:22.72#ibcon#end of sib2, iclass 24, count 0 2006.245.07:20:22.72#ibcon#*after write, iclass 24, count 0 2006.245.07:20:22.72#ibcon#*before return 0, iclass 24, count 0 2006.245.07:20:22.72#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:20:22.72#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:20:22.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:20:22.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:20:22.72$vc4f8/vblo=1,632.99 2006.245.07:20:22.72#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.07:20:22.72#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.07:20:22.72#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:22.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:20:22.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:20:22.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:20:22.72#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:20:22.72#ibcon#first serial, iclass 26, count 0 2006.245.07:20:22.72#ibcon#enter sib2, iclass 26, count 0 2006.245.07:20:22.72#ibcon#flushed, iclass 26, count 0 2006.245.07:20:22.72#ibcon#about to write, iclass 26, count 0 2006.245.07:20:22.72#ibcon#wrote, iclass 26, count 0 2006.245.07:20:22.72#ibcon#about to read 3, iclass 26, count 0 2006.245.07:20:22.74#ibcon#read 3, iclass 26, count 0 2006.245.07:20:22.74#ibcon#about to read 4, iclass 26, count 0 2006.245.07:20:22.74#ibcon#read 4, iclass 26, count 0 2006.245.07:20:22.74#ibcon#about to read 5, iclass 26, count 0 2006.245.07:20:22.74#ibcon#read 5, iclass 26, count 0 2006.245.07:20:22.74#ibcon#about to read 6, iclass 26, count 0 2006.245.07:20:22.74#ibcon#read 6, iclass 26, count 0 2006.245.07:20:22.74#ibcon#end of sib2, iclass 26, count 0 2006.245.07:20:22.74#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:20:22.74#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:20:22.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:20:22.74#ibcon#*before write, iclass 26, count 0 2006.245.07:20:22.74#ibcon#enter sib2, iclass 26, count 0 2006.245.07:20:22.74#ibcon#flushed, iclass 26, count 0 2006.245.07:20:22.74#ibcon#about to write, iclass 26, count 0 2006.245.07:20:22.74#ibcon#wrote, iclass 26, count 0 2006.245.07:20:22.74#ibcon#about to read 3, iclass 26, count 0 2006.245.07:20:22.80#ibcon#read 3, iclass 26, count 0 2006.245.07:20:22.80#ibcon#about to read 4, iclass 26, count 0 2006.245.07:20:22.80#ibcon#read 4, iclass 26, count 0 2006.245.07:20:22.80#ibcon#about to read 5, iclass 26, count 0 2006.245.07:20:22.80#ibcon#read 5, iclass 26, count 0 2006.245.07:20:22.80#ibcon#about to read 6, iclass 26, count 0 2006.245.07:20:22.80#ibcon#read 6, iclass 26, count 0 2006.245.07:20:22.80#ibcon#end of sib2, iclass 26, count 0 2006.245.07:20:22.80#ibcon#*after write, iclass 26, count 0 2006.245.07:20:22.80#ibcon#*before return 0, iclass 26, count 0 2006.245.07:20:22.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:20:22.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:20:22.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:20:22.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:20:22.80$vc4f8/vb=1,4 2006.245.07:20:22.80#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.07:20:22.80#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.07:20:22.80#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:22.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:20:22.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:20:22.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:20:22.80#ibcon#enter wrdev, iclass 28, count 2 2006.245.07:20:22.80#ibcon#first serial, iclass 28, count 2 2006.245.07:20:22.80#ibcon#enter sib2, iclass 28, count 2 2006.245.07:20:22.80#ibcon#flushed, iclass 28, count 2 2006.245.07:20:22.80#ibcon#about to write, iclass 28, count 2 2006.245.07:20:22.80#ibcon#wrote, iclass 28, count 2 2006.245.07:20:22.80#ibcon#about to read 3, iclass 28, count 2 2006.245.07:20:22.82#ibcon#read 3, iclass 28, count 2 2006.245.07:20:22.82#ibcon#about to read 4, iclass 28, count 2 2006.245.07:20:22.82#ibcon#read 4, iclass 28, count 2 2006.245.07:20:22.82#ibcon#about to read 5, iclass 28, count 2 2006.245.07:20:22.82#ibcon#read 5, iclass 28, count 2 2006.245.07:20:22.82#ibcon#about to read 6, iclass 28, count 2 2006.245.07:20:22.82#ibcon#read 6, iclass 28, count 2 2006.245.07:20:22.82#ibcon#end of sib2, iclass 28, count 2 2006.245.07:20:22.82#ibcon#*mode == 0, iclass 28, count 2 2006.245.07:20:22.82#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.07:20:22.82#ibcon#[27=AT01-04\r\n] 2006.245.07:20:22.82#ibcon#*before write, iclass 28, count 2 2006.245.07:20:22.82#ibcon#enter sib2, iclass 28, count 2 2006.245.07:20:22.82#ibcon#flushed, iclass 28, count 2 2006.245.07:20:22.82#ibcon#about to write, iclass 28, count 2 2006.245.07:20:22.82#ibcon#wrote, iclass 28, count 2 2006.245.07:20:22.82#ibcon#about to read 3, iclass 28, count 2 2006.245.07:20:22.86#ibcon#read 3, iclass 28, count 2 2006.245.07:20:22.86#ibcon#about to read 4, iclass 28, count 2 2006.245.07:20:22.86#ibcon#read 4, iclass 28, count 2 2006.245.07:20:22.86#ibcon#about to read 5, iclass 28, count 2 2006.245.07:20:22.86#ibcon#read 5, iclass 28, count 2 2006.245.07:20:22.86#ibcon#about to read 6, iclass 28, count 2 2006.245.07:20:22.86#ibcon#read 6, iclass 28, count 2 2006.245.07:20:22.86#ibcon#end of sib2, iclass 28, count 2 2006.245.07:20:22.86#ibcon#*after write, iclass 28, count 2 2006.245.07:20:22.86#ibcon#*before return 0, iclass 28, count 2 2006.245.07:20:22.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:20:22.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:20:22.86#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.07:20:22.86#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:22.86#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:20:22.98#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:20:22.98#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:20:22.98#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:20:22.98#ibcon#first serial, iclass 28, count 0 2006.245.07:20:22.98#ibcon#enter sib2, iclass 28, count 0 2006.245.07:20:22.98#ibcon#flushed, iclass 28, count 0 2006.245.07:20:22.98#ibcon#about to write, iclass 28, count 0 2006.245.07:20:22.98#ibcon#wrote, iclass 28, count 0 2006.245.07:20:22.98#ibcon#about to read 3, iclass 28, count 0 2006.245.07:20:23.00#ibcon#read 3, iclass 28, count 0 2006.245.07:20:23.00#ibcon#about to read 4, iclass 28, count 0 2006.245.07:20:23.00#ibcon#read 4, iclass 28, count 0 2006.245.07:20:23.00#ibcon#about to read 5, iclass 28, count 0 2006.245.07:20:23.00#ibcon#read 5, iclass 28, count 0 2006.245.07:20:23.00#ibcon#about to read 6, iclass 28, count 0 2006.245.07:20:23.00#ibcon#read 6, iclass 28, count 0 2006.245.07:20:23.00#ibcon#end of sib2, iclass 28, count 0 2006.245.07:20:23.00#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:20:23.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:20:23.00#ibcon#[27=USB\r\n] 2006.245.07:20:23.00#ibcon#*before write, iclass 28, count 0 2006.245.07:20:23.00#ibcon#enter sib2, iclass 28, count 0 2006.245.07:20:23.00#ibcon#flushed, iclass 28, count 0 2006.245.07:20:23.00#ibcon#about to write, iclass 28, count 0 2006.245.07:20:23.00#ibcon#wrote, iclass 28, count 0 2006.245.07:20:23.00#ibcon#about to read 3, iclass 28, count 0 2006.245.07:20:23.03#ibcon#read 3, iclass 28, count 0 2006.245.07:20:23.03#ibcon#about to read 4, iclass 28, count 0 2006.245.07:20:23.03#ibcon#read 4, iclass 28, count 0 2006.245.07:20:23.03#ibcon#about to read 5, iclass 28, count 0 2006.245.07:20:23.03#ibcon#read 5, iclass 28, count 0 2006.245.07:20:23.03#ibcon#about to read 6, iclass 28, count 0 2006.245.07:20:23.03#ibcon#read 6, iclass 28, count 0 2006.245.07:20:23.03#ibcon#end of sib2, iclass 28, count 0 2006.245.07:20:23.03#ibcon#*after write, iclass 28, count 0 2006.245.07:20:23.03#ibcon#*before return 0, iclass 28, count 0 2006.245.07:20:23.03#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:20:23.03#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:20:23.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:20:23.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:20:23.03$vc4f8/vblo=2,640.99 2006.245.07:20:23.03#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:20:23.03#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:20:23.03#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:23.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:23.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:23.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:23.03#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:20:23.03#ibcon#first serial, iclass 30, count 0 2006.245.07:20:23.03#ibcon#enter sib2, iclass 30, count 0 2006.245.07:20:23.03#ibcon#flushed, iclass 30, count 0 2006.245.07:20:23.03#ibcon#about to write, iclass 30, count 0 2006.245.07:20:23.03#ibcon#wrote, iclass 30, count 0 2006.245.07:20:23.03#ibcon#about to read 3, iclass 30, count 0 2006.245.07:20:23.05#ibcon#read 3, iclass 30, count 0 2006.245.07:20:23.05#ibcon#about to read 4, iclass 30, count 0 2006.245.07:20:23.05#ibcon#read 4, iclass 30, count 0 2006.245.07:20:23.05#ibcon#about to read 5, iclass 30, count 0 2006.245.07:20:23.05#ibcon#read 5, iclass 30, count 0 2006.245.07:20:23.05#ibcon#about to read 6, iclass 30, count 0 2006.245.07:20:23.05#ibcon#read 6, iclass 30, count 0 2006.245.07:20:23.05#ibcon#end of sib2, iclass 30, count 0 2006.245.07:20:23.05#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:20:23.05#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:20:23.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:20:23.05#ibcon#*before write, iclass 30, count 0 2006.245.07:20:23.05#ibcon#enter sib2, iclass 30, count 0 2006.245.07:20:23.05#ibcon#flushed, iclass 30, count 0 2006.245.07:20:23.05#ibcon#about to write, iclass 30, count 0 2006.245.07:20:23.05#ibcon#wrote, iclass 30, count 0 2006.245.07:20:23.05#ibcon#about to read 3, iclass 30, count 0 2006.245.07:20:23.09#ibcon#read 3, iclass 30, count 0 2006.245.07:20:23.09#ibcon#about to read 4, iclass 30, count 0 2006.245.07:20:23.09#ibcon#read 4, iclass 30, count 0 2006.245.07:20:23.09#ibcon#about to read 5, iclass 30, count 0 2006.245.07:20:23.09#ibcon#read 5, iclass 30, count 0 2006.245.07:20:23.09#ibcon#about to read 6, iclass 30, count 0 2006.245.07:20:23.09#ibcon#read 6, iclass 30, count 0 2006.245.07:20:23.09#ibcon#end of sib2, iclass 30, count 0 2006.245.07:20:23.09#ibcon#*after write, iclass 30, count 0 2006.245.07:20:23.09#ibcon#*before return 0, iclass 30, count 0 2006.245.07:20:23.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:23.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:20:23.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:20:23.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:20:23.09$vc4f8/vb=2,4 2006.245.07:20:23.09#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.07:20:23.09#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.07:20:23.09#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:23.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:23.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:23.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:23.16#ibcon#enter wrdev, iclass 32, count 2 2006.245.07:20:23.16#ibcon#first serial, iclass 32, count 2 2006.245.07:20:23.16#ibcon#enter sib2, iclass 32, count 2 2006.245.07:20:23.16#ibcon#flushed, iclass 32, count 2 2006.245.07:20:23.16#ibcon#about to write, iclass 32, count 2 2006.245.07:20:23.16#ibcon#wrote, iclass 32, count 2 2006.245.07:20:23.16#ibcon#about to read 3, iclass 32, count 2 2006.245.07:20:23.17#ibcon#read 3, iclass 32, count 2 2006.245.07:20:23.17#ibcon#about to read 4, iclass 32, count 2 2006.245.07:20:23.17#ibcon#read 4, iclass 32, count 2 2006.245.07:20:23.17#ibcon#about to read 5, iclass 32, count 2 2006.245.07:20:23.17#ibcon#read 5, iclass 32, count 2 2006.245.07:20:23.17#ibcon#about to read 6, iclass 32, count 2 2006.245.07:20:23.17#ibcon#read 6, iclass 32, count 2 2006.245.07:20:23.17#ibcon#end of sib2, iclass 32, count 2 2006.245.07:20:23.17#ibcon#*mode == 0, iclass 32, count 2 2006.245.07:20:23.17#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.07:20:23.17#ibcon#[27=AT02-04\r\n] 2006.245.07:20:23.17#ibcon#*before write, iclass 32, count 2 2006.245.07:20:23.17#ibcon#enter sib2, iclass 32, count 2 2006.245.07:20:23.17#ibcon#flushed, iclass 32, count 2 2006.245.07:20:23.17#ibcon#about to write, iclass 32, count 2 2006.245.07:20:23.17#ibcon#wrote, iclass 32, count 2 2006.245.07:20:23.17#ibcon#about to read 3, iclass 32, count 2 2006.245.07:20:23.20#ibcon#read 3, iclass 32, count 2 2006.245.07:20:23.20#ibcon#about to read 4, iclass 32, count 2 2006.245.07:20:23.20#ibcon#read 4, iclass 32, count 2 2006.245.07:20:23.20#ibcon#about to read 5, iclass 32, count 2 2006.245.07:20:23.20#ibcon#read 5, iclass 32, count 2 2006.245.07:20:23.20#ibcon#about to read 6, iclass 32, count 2 2006.245.07:20:23.20#ibcon#read 6, iclass 32, count 2 2006.245.07:20:23.20#ibcon#end of sib2, iclass 32, count 2 2006.245.07:20:23.20#ibcon#*after write, iclass 32, count 2 2006.245.07:20:23.20#ibcon#*before return 0, iclass 32, count 2 2006.245.07:20:23.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:23.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:20:23.20#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.07:20:23.20#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:23.20#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:23.32#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:23.32#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:23.32#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:20:23.32#ibcon#first serial, iclass 32, count 0 2006.245.07:20:23.32#ibcon#enter sib2, iclass 32, count 0 2006.245.07:20:23.32#ibcon#flushed, iclass 32, count 0 2006.245.07:20:23.32#ibcon#about to write, iclass 32, count 0 2006.245.07:20:23.32#ibcon#wrote, iclass 32, count 0 2006.245.07:20:23.32#ibcon#about to read 3, iclass 32, count 0 2006.245.07:20:23.34#ibcon#read 3, iclass 32, count 0 2006.245.07:20:23.34#ibcon#about to read 4, iclass 32, count 0 2006.245.07:20:23.34#ibcon#read 4, iclass 32, count 0 2006.245.07:20:23.34#ibcon#about to read 5, iclass 32, count 0 2006.245.07:20:23.34#ibcon#read 5, iclass 32, count 0 2006.245.07:20:23.34#ibcon#about to read 6, iclass 32, count 0 2006.245.07:20:23.34#ibcon#read 6, iclass 32, count 0 2006.245.07:20:23.34#ibcon#end of sib2, iclass 32, count 0 2006.245.07:20:23.34#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:20:23.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:20:23.34#ibcon#[27=USB\r\n] 2006.245.07:20:23.34#ibcon#*before write, iclass 32, count 0 2006.245.07:20:23.34#ibcon#enter sib2, iclass 32, count 0 2006.245.07:20:23.34#ibcon#flushed, iclass 32, count 0 2006.245.07:20:23.34#ibcon#about to write, iclass 32, count 0 2006.245.07:20:23.34#ibcon#wrote, iclass 32, count 0 2006.245.07:20:23.34#ibcon#about to read 3, iclass 32, count 0 2006.245.07:20:23.37#ibcon#read 3, iclass 32, count 0 2006.245.07:20:23.37#ibcon#about to read 4, iclass 32, count 0 2006.245.07:20:23.37#ibcon#read 4, iclass 32, count 0 2006.245.07:20:23.37#ibcon#about to read 5, iclass 32, count 0 2006.245.07:20:23.37#ibcon#read 5, iclass 32, count 0 2006.245.07:20:23.37#ibcon#about to read 6, iclass 32, count 0 2006.245.07:20:23.37#ibcon#read 6, iclass 32, count 0 2006.245.07:20:23.37#ibcon#end of sib2, iclass 32, count 0 2006.245.07:20:23.37#ibcon#*after write, iclass 32, count 0 2006.245.07:20:23.37#ibcon#*before return 0, iclass 32, count 0 2006.245.07:20:23.37#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:23.37#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:20:23.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:20:23.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:20:23.37$vc4f8/vblo=3,656.99 2006.245.07:20:23.37#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:20:23.37#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:20:23.37#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:23.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:23.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:23.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:23.37#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:20:23.37#ibcon#first serial, iclass 34, count 0 2006.245.07:20:23.37#ibcon#enter sib2, iclass 34, count 0 2006.245.07:20:23.37#ibcon#flushed, iclass 34, count 0 2006.245.07:20:23.37#ibcon#about to write, iclass 34, count 0 2006.245.07:20:23.37#ibcon#wrote, iclass 34, count 0 2006.245.07:20:23.37#ibcon#about to read 3, iclass 34, count 0 2006.245.07:20:23.40#ibcon#read 3, iclass 34, count 0 2006.245.07:20:23.40#ibcon#about to read 4, iclass 34, count 0 2006.245.07:20:23.40#ibcon#read 4, iclass 34, count 0 2006.245.07:20:23.40#ibcon#about to read 5, iclass 34, count 0 2006.245.07:20:23.40#ibcon#read 5, iclass 34, count 0 2006.245.07:20:23.40#ibcon#about to read 6, iclass 34, count 0 2006.245.07:20:23.40#ibcon#read 6, iclass 34, count 0 2006.245.07:20:23.40#ibcon#end of sib2, iclass 34, count 0 2006.245.07:20:23.40#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:20:23.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:20:23.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:20:23.40#ibcon#*before write, iclass 34, count 0 2006.245.07:20:23.40#ibcon#enter sib2, iclass 34, count 0 2006.245.07:20:23.40#ibcon#flushed, iclass 34, count 0 2006.245.07:20:23.40#ibcon#about to write, iclass 34, count 0 2006.245.07:20:23.40#ibcon#wrote, iclass 34, count 0 2006.245.07:20:23.40#ibcon#about to read 3, iclass 34, count 0 2006.245.07:20:23.44#ibcon#read 3, iclass 34, count 0 2006.245.07:20:23.44#ibcon#about to read 4, iclass 34, count 0 2006.245.07:20:23.44#ibcon#read 4, iclass 34, count 0 2006.245.07:20:23.44#ibcon#about to read 5, iclass 34, count 0 2006.245.07:20:23.44#ibcon#read 5, iclass 34, count 0 2006.245.07:20:23.44#ibcon#about to read 6, iclass 34, count 0 2006.245.07:20:23.44#ibcon#read 6, iclass 34, count 0 2006.245.07:20:23.44#ibcon#end of sib2, iclass 34, count 0 2006.245.07:20:23.44#ibcon#*after write, iclass 34, count 0 2006.245.07:20:23.44#ibcon#*before return 0, iclass 34, count 0 2006.245.07:20:23.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:23.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:20:23.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:20:23.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:20:23.44$vc4f8/vb=3,4 2006.245.07:20:23.44#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:20:23.44#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:20:23.44#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:23.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:23.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:23.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:23.50#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:20:23.50#ibcon#first serial, iclass 36, count 2 2006.245.07:20:23.50#ibcon#enter sib2, iclass 36, count 2 2006.245.07:20:23.50#ibcon#flushed, iclass 36, count 2 2006.245.07:20:23.50#ibcon#about to write, iclass 36, count 2 2006.245.07:20:23.50#ibcon#wrote, iclass 36, count 2 2006.245.07:20:23.50#ibcon#about to read 3, iclass 36, count 2 2006.245.07:20:23.51#ibcon#read 3, iclass 36, count 2 2006.245.07:20:23.51#ibcon#about to read 4, iclass 36, count 2 2006.245.07:20:23.51#ibcon#read 4, iclass 36, count 2 2006.245.07:20:23.51#ibcon#about to read 5, iclass 36, count 2 2006.245.07:20:23.51#ibcon#read 5, iclass 36, count 2 2006.245.07:20:23.51#ibcon#about to read 6, iclass 36, count 2 2006.245.07:20:23.51#ibcon#read 6, iclass 36, count 2 2006.245.07:20:23.51#ibcon#end of sib2, iclass 36, count 2 2006.245.07:20:23.51#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:20:23.51#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:20:23.51#ibcon#[27=AT03-04\r\n] 2006.245.07:20:23.51#ibcon#*before write, iclass 36, count 2 2006.245.07:20:23.51#ibcon#enter sib2, iclass 36, count 2 2006.245.07:20:23.51#ibcon#flushed, iclass 36, count 2 2006.245.07:20:23.51#ibcon#about to write, iclass 36, count 2 2006.245.07:20:23.51#ibcon#wrote, iclass 36, count 2 2006.245.07:20:23.51#ibcon#about to read 3, iclass 36, count 2 2006.245.07:20:23.54#ibcon#read 3, iclass 36, count 2 2006.245.07:20:23.54#ibcon#about to read 4, iclass 36, count 2 2006.245.07:20:23.54#ibcon#read 4, iclass 36, count 2 2006.245.07:20:23.54#ibcon#about to read 5, iclass 36, count 2 2006.245.07:20:23.54#ibcon#read 5, iclass 36, count 2 2006.245.07:20:23.54#ibcon#about to read 6, iclass 36, count 2 2006.245.07:20:23.54#ibcon#read 6, iclass 36, count 2 2006.245.07:20:23.54#ibcon#end of sib2, iclass 36, count 2 2006.245.07:20:23.54#ibcon#*after write, iclass 36, count 2 2006.245.07:20:23.54#ibcon#*before return 0, iclass 36, count 2 2006.245.07:20:23.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:23.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:20:23.54#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:20:23.54#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:23.54#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:23.66#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:23.66#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:23.66#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:20:23.66#ibcon#first serial, iclass 36, count 0 2006.245.07:20:23.66#ibcon#enter sib2, iclass 36, count 0 2006.245.07:20:23.66#ibcon#flushed, iclass 36, count 0 2006.245.07:20:23.66#ibcon#about to write, iclass 36, count 0 2006.245.07:20:23.66#ibcon#wrote, iclass 36, count 0 2006.245.07:20:23.66#ibcon#about to read 3, iclass 36, count 0 2006.245.07:20:23.68#ibcon#read 3, iclass 36, count 0 2006.245.07:20:23.68#ibcon#about to read 4, iclass 36, count 0 2006.245.07:20:23.68#ibcon#read 4, iclass 36, count 0 2006.245.07:20:23.68#ibcon#about to read 5, iclass 36, count 0 2006.245.07:20:23.68#ibcon#read 5, iclass 36, count 0 2006.245.07:20:23.68#ibcon#about to read 6, iclass 36, count 0 2006.245.07:20:23.68#ibcon#read 6, iclass 36, count 0 2006.245.07:20:23.68#ibcon#end of sib2, iclass 36, count 0 2006.245.07:20:23.68#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:20:23.68#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:20:23.68#ibcon#[27=USB\r\n] 2006.245.07:20:23.68#ibcon#*before write, iclass 36, count 0 2006.245.07:20:23.68#ibcon#enter sib2, iclass 36, count 0 2006.245.07:20:23.68#ibcon#flushed, iclass 36, count 0 2006.245.07:20:23.68#ibcon#about to write, iclass 36, count 0 2006.245.07:20:23.68#ibcon#wrote, iclass 36, count 0 2006.245.07:20:23.68#ibcon#about to read 3, iclass 36, count 0 2006.245.07:20:23.71#ibcon#read 3, iclass 36, count 0 2006.245.07:20:23.71#ibcon#about to read 4, iclass 36, count 0 2006.245.07:20:23.71#ibcon#read 4, iclass 36, count 0 2006.245.07:20:23.71#ibcon#about to read 5, iclass 36, count 0 2006.245.07:20:23.71#ibcon#read 5, iclass 36, count 0 2006.245.07:20:23.71#ibcon#about to read 6, iclass 36, count 0 2006.245.07:20:23.71#ibcon#read 6, iclass 36, count 0 2006.245.07:20:23.71#ibcon#end of sib2, iclass 36, count 0 2006.245.07:20:23.71#ibcon#*after write, iclass 36, count 0 2006.245.07:20:23.71#ibcon#*before return 0, iclass 36, count 0 2006.245.07:20:23.71#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:23.71#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:20:23.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:20:23.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:20:23.71$vc4f8/vblo=4,712.99 2006.245.07:20:23.71#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:20:23.71#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:20:23.71#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:23.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:23.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:23.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:23.71#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:20:23.71#ibcon#first serial, iclass 38, count 0 2006.245.07:20:23.71#ibcon#enter sib2, iclass 38, count 0 2006.245.07:20:23.71#ibcon#flushed, iclass 38, count 0 2006.245.07:20:23.71#ibcon#about to write, iclass 38, count 0 2006.245.07:20:23.71#ibcon#wrote, iclass 38, count 0 2006.245.07:20:23.71#ibcon#about to read 3, iclass 38, count 0 2006.245.07:20:23.73#ibcon#read 3, iclass 38, count 0 2006.245.07:20:23.73#ibcon#about to read 4, iclass 38, count 0 2006.245.07:20:23.73#ibcon#read 4, iclass 38, count 0 2006.245.07:20:23.73#ibcon#about to read 5, iclass 38, count 0 2006.245.07:20:23.73#ibcon#read 5, iclass 38, count 0 2006.245.07:20:23.73#ibcon#about to read 6, iclass 38, count 0 2006.245.07:20:23.73#ibcon#read 6, iclass 38, count 0 2006.245.07:20:23.73#ibcon#end of sib2, iclass 38, count 0 2006.245.07:20:23.73#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:20:23.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:20:23.73#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:20:23.73#ibcon#*before write, iclass 38, count 0 2006.245.07:20:23.73#ibcon#enter sib2, iclass 38, count 0 2006.245.07:20:23.73#ibcon#flushed, iclass 38, count 0 2006.245.07:20:23.73#ibcon#about to write, iclass 38, count 0 2006.245.07:20:23.73#ibcon#wrote, iclass 38, count 0 2006.245.07:20:23.73#ibcon#about to read 3, iclass 38, count 0 2006.245.07:20:23.77#ibcon#read 3, iclass 38, count 0 2006.245.07:20:23.77#ibcon#about to read 4, iclass 38, count 0 2006.245.07:20:23.77#ibcon#read 4, iclass 38, count 0 2006.245.07:20:23.77#ibcon#about to read 5, iclass 38, count 0 2006.245.07:20:23.77#ibcon#read 5, iclass 38, count 0 2006.245.07:20:23.77#ibcon#about to read 6, iclass 38, count 0 2006.245.07:20:23.77#ibcon#read 6, iclass 38, count 0 2006.245.07:20:23.77#ibcon#end of sib2, iclass 38, count 0 2006.245.07:20:23.77#ibcon#*after write, iclass 38, count 0 2006.245.07:20:23.77#ibcon#*before return 0, iclass 38, count 0 2006.245.07:20:23.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:23.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:20:23.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:20:23.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:20:23.77$vc4f8/vb=4,4 2006.245.07:20:23.77#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:20:23.77#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:20:23.77#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:23.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:23.84#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:23.84#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:23.84#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:20:23.84#ibcon#first serial, iclass 40, count 2 2006.245.07:20:23.84#ibcon#enter sib2, iclass 40, count 2 2006.245.07:20:23.84#ibcon#flushed, iclass 40, count 2 2006.245.07:20:23.84#ibcon#about to write, iclass 40, count 2 2006.245.07:20:23.84#ibcon#wrote, iclass 40, count 2 2006.245.07:20:23.84#ibcon#about to read 3, iclass 40, count 2 2006.245.07:20:23.85#ibcon#read 3, iclass 40, count 2 2006.245.07:20:23.85#ibcon#about to read 4, iclass 40, count 2 2006.245.07:20:23.85#ibcon#read 4, iclass 40, count 2 2006.245.07:20:23.85#ibcon#about to read 5, iclass 40, count 2 2006.245.07:20:23.85#ibcon#read 5, iclass 40, count 2 2006.245.07:20:23.85#ibcon#about to read 6, iclass 40, count 2 2006.245.07:20:23.85#ibcon#read 6, iclass 40, count 2 2006.245.07:20:23.85#ibcon#end of sib2, iclass 40, count 2 2006.245.07:20:23.85#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:20:23.85#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:20:23.85#ibcon#[27=AT04-04\r\n] 2006.245.07:20:23.85#ibcon#*before write, iclass 40, count 2 2006.245.07:20:23.85#ibcon#enter sib2, iclass 40, count 2 2006.245.07:20:23.85#ibcon#flushed, iclass 40, count 2 2006.245.07:20:23.85#ibcon#about to write, iclass 40, count 2 2006.245.07:20:23.85#ibcon#wrote, iclass 40, count 2 2006.245.07:20:23.85#ibcon#about to read 3, iclass 40, count 2 2006.245.07:20:23.88#ibcon#read 3, iclass 40, count 2 2006.245.07:20:23.88#ibcon#about to read 4, iclass 40, count 2 2006.245.07:20:23.88#ibcon#read 4, iclass 40, count 2 2006.245.07:20:23.88#ibcon#about to read 5, iclass 40, count 2 2006.245.07:20:23.88#ibcon#read 5, iclass 40, count 2 2006.245.07:20:23.88#ibcon#about to read 6, iclass 40, count 2 2006.245.07:20:23.88#ibcon#read 6, iclass 40, count 2 2006.245.07:20:23.88#ibcon#end of sib2, iclass 40, count 2 2006.245.07:20:23.88#ibcon#*after write, iclass 40, count 2 2006.245.07:20:23.88#ibcon#*before return 0, iclass 40, count 2 2006.245.07:20:23.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:23.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:20:23.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:20:23.88#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:23.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:24.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:24.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:24.00#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:20:24.00#ibcon#first serial, iclass 40, count 0 2006.245.07:20:24.00#ibcon#enter sib2, iclass 40, count 0 2006.245.07:20:24.00#ibcon#flushed, iclass 40, count 0 2006.245.07:20:24.00#ibcon#about to write, iclass 40, count 0 2006.245.07:20:24.00#ibcon#wrote, iclass 40, count 0 2006.245.07:20:24.00#ibcon#about to read 3, iclass 40, count 0 2006.245.07:20:24.02#ibcon#read 3, iclass 40, count 0 2006.245.07:20:24.02#ibcon#about to read 4, iclass 40, count 0 2006.245.07:20:24.02#ibcon#read 4, iclass 40, count 0 2006.245.07:20:24.02#ibcon#about to read 5, iclass 40, count 0 2006.245.07:20:24.02#ibcon#read 5, iclass 40, count 0 2006.245.07:20:24.02#ibcon#about to read 6, iclass 40, count 0 2006.245.07:20:24.02#ibcon#read 6, iclass 40, count 0 2006.245.07:20:24.02#ibcon#end of sib2, iclass 40, count 0 2006.245.07:20:24.02#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:20:24.02#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:20:24.02#ibcon#[27=USB\r\n] 2006.245.07:20:24.02#ibcon#*before write, iclass 40, count 0 2006.245.07:20:24.02#ibcon#enter sib2, iclass 40, count 0 2006.245.07:20:24.02#ibcon#flushed, iclass 40, count 0 2006.245.07:20:24.02#ibcon#about to write, iclass 40, count 0 2006.245.07:20:24.02#ibcon#wrote, iclass 40, count 0 2006.245.07:20:24.02#ibcon#about to read 3, iclass 40, count 0 2006.245.07:20:24.05#ibcon#read 3, iclass 40, count 0 2006.245.07:20:24.05#ibcon#about to read 4, iclass 40, count 0 2006.245.07:20:24.05#ibcon#read 4, iclass 40, count 0 2006.245.07:20:24.05#ibcon#about to read 5, iclass 40, count 0 2006.245.07:20:24.05#ibcon#read 5, iclass 40, count 0 2006.245.07:20:24.05#ibcon#about to read 6, iclass 40, count 0 2006.245.07:20:24.05#ibcon#read 6, iclass 40, count 0 2006.245.07:20:24.05#ibcon#end of sib2, iclass 40, count 0 2006.245.07:20:24.05#ibcon#*after write, iclass 40, count 0 2006.245.07:20:24.05#ibcon#*before return 0, iclass 40, count 0 2006.245.07:20:24.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:24.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:20:24.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:20:24.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:20:24.05$vc4f8/vblo=5,744.99 2006.245.07:20:24.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:20:24.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:20:24.05#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:24.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:24.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:24.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:24.05#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:20:24.05#ibcon#first serial, iclass 4, count 0 2006.245.07:20:24.05#ibcon#enter sib2, iclass 4, count 0 2006.245.07:20:24.05#ibcon#flushed, iclass 4, count 0 2006.245.07:20:24.05#ibcon#about to write, iclass 4, count 0 2006.245.07:20:24.05#ibcon#wrote, iclass 4, count 0 2006.245.07:20:24.05#ibcon#about to read 3, iclass 4, count 0 2006.245.07:20:24.08#ibcon#read 3, iclass 4, count 0 2006.245.07:20:24.08#ibcon#about to read 4, iclass 4, count 0 2006.245.07:20:24.08#ibcon#read 4, iclass 4, count 0 2006.245.07:20:24.08#ibcon#about to read 5, iclass 4, count 0 2006.245.07:20:24.08#ibcon#read 5, iclass 4, count 0 2006.245.07:20:24.08#ibcon#about to read 6, iclass 4, count 0 2006.245.07:20:24.08#ibcon#read 6, iclass 4, count 0 2006.245.07:20:24.08#ibcon#end of sib2, iclass 4, count 0 2006.245.07:20:24.08#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:20:24.08#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:20:24.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:20:24.08#ibcon#*before write, iclass 4, count 0 2006.245.07:20:24.08#ibcon#enter sib2, iclass 4, count 0 2006.245.07:20:24.08#ibcon#flushed, iclass 4, count 0 2006.245.07:20:24.08#ibcon#about to write, iclass 4, count 0 2006.245.07:20:24.08#ibcon#wrote, iclass 4, count 0 2006.245.07:20:24.08#ibcon#about to read 3, iclass 4, count 0 2006.245.07:20:24.12#ibcon#read 3, iclass 4, count 0 2006.245.07:20:24.12#ibcon#about to read 4, iclass 4, count 0 2006.245.07:20:24.12#ibcon#read 4, iclass 4, count 0 2006.245.07:20:24.12#ibcon#about to read 5, iclass 4, count 0 2006.245.07:20:24.12#ibcon#read 5, iclass 4, count 0 2006.245.07:20:24.12#ibcon#about to read 6, iclass 4, count 0 2006.245.07:20:24.12#ibcon#read 6, iclass 4, count 0 2006.245.07:20:24.12#ibcon#end of sib2, iclass 4, count 0 2006.245.07:20:24.12#ibcon#*after write, iclass 4, count 0 2006.245.07:20:24.12#ibcon#*before return 0, iclass 4, count 0 2006.245.07:20:24.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:24.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:20:24.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:20:24.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:20:24.12$vc4f8/vb=5,3 2006.245.07:20:24.12#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:20:24.12#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:20:24.12#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:24.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:24.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:24.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:24.18#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:20:24.18#ibcon#first serial, iclass 6, count 2 2006.245.07:20:24.18#ibcon#enter sib2, iclass 6, count 2 2006.245.07:20:24.18#ibcon#flushed, iclass 6, count 2 2006.245.07:20:24.18#ibcon#about to write, iclass 6, count 2 2006.245.07:20:24.18#ibcon#wrote, iclass 6, count 2 2006.245.07:20:24.18#ibcon#about to read 3, iclass 6, count 2 2006.245.07:20:24.19#ibcon#read 3, iclass 6, count 2 2006.245.07:20:24.19#ibcon#about to read 4, iclass 6, count 2 2006.245.07:20:24.19#ibcon#read 4, iclass 6, count 2 2006.245.07:20:24.19#ibcon#about to read 5, iclass 6, count 2 2006.245.07:20:24.19#ibcon#read 5, iclass 6, count 2 2006.245.07:20:24.19#ibcon#about to read 6, iclass 6, count 2 2006.245.07:20:24.19#ibcon#read 6, iclass 6, count 2 2006.245.07:20:24.19#ibcon#end of sib2, iclass 6, count 2 2006.245.07:20:24.19#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:20:24.19#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:20:24.19#ibcon#[27=AT05-03\r\n] 2006.245.07:20:24.19#ibcon#*before write, iclass 6, count 2 2006.245.07:20:24.19#ibcon#enter sib2, iclass 6, count 2 2006.245.07:20:24.19#ibcon#flushed, iclass 6, count 2 2006.245.07:20:24.19#ibcon#about to write, iclass 6, count 2 2006.245.07:20:24.19#ibcon#wrote, iclass 6, count 2 2006.245.07:20:24.19#ibcon#about to read 3, iclass 6, count 2 2006.245.07:20:24.22#ibcon#read 3, iclass 6, count 2 2006.245.07:20:24.22#ibcon#about to read 4, iclass 6, count 2 2006.245.07:20:24.22#ibcon#read 4, iclass 6, count 2 2006.245.07:20:24.22#ibcon#about to read 5, iclass 6, count 2 2006.245.07:20:24.22#ibcon#read 5, iclass 6, count 2 2006.245.07:20:24.22#ibcon#about to read 6, iclass 6, count 2 2006.245.07:20:24.22#ibcon#read 6, iclass 6, count 2 2006.245.07:20:24.22#ibcon#end of sib2, iclass 6, count 2 2006.245.07:20:24.22#ibcon#*after write, iclass 6, count 2 2006.245.07:20:24.22#ibcon#*before return 0, iclass 6, count 2 2006.245.07:20:24.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:24.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:20:24.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:20:24.22#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:24.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:24.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:24.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:24.34#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:20:24.34#ibcon#first serial, iclass 6, count 0 2006.245.07:20:24.34#ibcon#enter sib2, iclass 6, count 0 2006.245.07:20:24.34#ibcon#flushed, iclass 6, count 0 2006.245.07:20:24.34#ibcon#about to write, iclass 6, count 0 2006.245.07:20:24.34#ibcon#wrote, iclass 6, count 0 2006.245.07:20:24.34#ibcon#about to read 3, iclass 6, count 0 2006.245.07:20:24.36#ibcon#read 3, iclass 6, count 0 2006.245.07:20:24.36#ibcon#about to read 4, iclass 6, count 0 2006.245.07:20:24.36#ibcon#read 4, iclass 6, count 0 2006.245.07:20:24.36#ibcon#about to read 5, iclass 6, count 0 2006.245.07:20:24.36#ibcon#read 5, iclass 6, count 0 2006.245.07:20:24.36#ibcon#about to read 6, iclass 6, count 0 2006.245.07:20:24.36#ibcon#read 6, iclass 6, count 0 2006.245.07:20:24.36#ibcon#end of sib2, iclass 6, count 0 2006.245.07:20:24.36#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:20:24.36#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:20:24.36#ibcon#[27=USB\r\n] 2006.245.07:20:24.36#ibcon#*before write, iclass 6, count 0 2006.245.07:20:24.36#ibcon#enter sib2, iclass 6, count 0 2006.245.07:20:24.36#ibcon#flushed, iclass 6, count 0 2006.245.07:20:24.36#ibcon#about to write, iclass 6, count 0 2006.245.07:20:24.36#ibcon#wrote, iclass 6, count 0 2006.245.07:20:24.36#ibcon#about to read 3, iclass 6, count 0 2006.245.07:20:24.39#ibcon#read 3, iclass 6, count 0 2006.245.07:20:24.39#ibcon#about to read 4, iclass 6, count 0 2006.245.07:20:24.39#ibcon#read 4, iclass 6, count 0 2006.245.07:20:24.39#ibcon#about to read 5, iclass 6, count 0 2006.245.07:20:24.39#ibcon#read 5, iclass 6, count 0 2006.245.07:20:24.39#ibcon#about to read 6, iclass 6, count 0 2006.245.07:20:24.39#ibcon#read 6, iclass 6, count 0 2006.245.07:20:24.39#ibcon#end of sib2, iclass 6, count 0 2006.245.07:20:24.39#ibcon#*after write, iclass 6, count 0 2006.245.07:20:24.39#ibcon#*before return 0, iclass 6, count 0 2006.245.07:20:24.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:24.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:20:24.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:20:24.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:20:24.39$vc4f8/vblo=6,752.99 2006.245.07:20:24.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:20:24.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:20:24.39#ibcon#ireg 17 cls_cnt 0 2006.245.07:20:24.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:24.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:24.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:24.39#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:20:24.39#ibcon#first serial, iclass 10, count 0 2006.245.07:20:24.39#ibcon#enter sib2, iclass 10, count 0 2006.245.07:20:24.39#ibcon#flushed, iclass 10, count 0 2006.245.07:20:24.39#ibcon#about to write, iclass 10, count 0 2006.245.07:20:24.39#ibcon#wrote, iclass 10, count 0 2006.245.07:20:24.39#ibcon#about to read 3, iclass 10, count 0 2006.245.07:20:24.41#ibcon#read 3, iclass 10, count 0 2006.245.07:20:24.41#ibcon#about to read 4, iclass 10, count 0 2006.245.07:20:24.41#ibcon#read 4, iclass 10, count 0 2006.245.07:20:24.41#ibcon#about to read 5, iclass 10, count 0 2006.245.07:20:24.41#ibcon#read 5, iclass 10, count 0 2006.245.07:20:24.41#ibcon#about to read 6, iclass 10, count 0 2006.245.07:20:24.41#ibcon#read 6, iclass 10, count 0 2006.245.07:20:24.41#ibcon#end of sib2, iclass 10, count 0 2006.245.07:20:24.41#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:20:24.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:20:24.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:20:24.41#ibcon#*before write, iclass 10, count 0 2006.245.07:20:24.41#ibcon#enter sib2, iclass 10, count 0 2006.245.07:20:24.41#ibcon#flushed, iclass 10, count 0 2006.245.07:20:24.41#ibcon#about to write, iclass 10, count 0 2006.245.07:20:24.41#ibcon#wrote, iclass 10, count 0 2006.245.07:20:24.41#ibcon#about to read 3, iclass 10, count 0 2006.245.07:20:24.45#ibcon#read 3, iclass 10, count 0 2006.245.07:20:24.45#ibcon#about to read 4, iclass 10, count 0 2006.245.07:20:24.45#ibcon#read 4, iclass 10, count 0 2006.245.07:20:24.45#ibcon#about to read 5, iclass 10, count 0 2006.245.07:20:24.45#ibcon#read 5, iclass 10, count 0 2006.245.07:20:24.45#ibcon#about to read 6, iclass 10, count 0 2006.245.07:20:24.45#ibcon#read 6, iclass 10, count 0 2006.245.07:20:24.45#ibcon#end of sib2, iclass 10, count 0 2006.245.07:20:24.45#ibcon#*after write, iclass 10, count 0 2006.245.07:20:24.45#ibcon#*before return 0, iclass 10, count 0 2006.245.07:20:24.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:24.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:20:24.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:20:24.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:20:24.45$vc4f8/vb=6,3 2006.245.07:20:24.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:20:24.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:20:24.45#ibcon#ireg 11 cls_cnt 2 2006.245.07:20:24.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:24.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:24.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:24.51#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:20:24.51#ibcon#first serial, iclass 12, count 2 2006.245.07:20:24.51#ibcon#enter sib2, iclass 12, count 2 2006.245.07:20:24.51#ibcon#flushed, iclass 12, count 2 2006.245.07:20:24.51#ibcon#about to write, iclass 12, count 2 2006.245.07:20:24.51#ibcon#wrote, iclass 12, count 2 2006.245.07:20:24.51#ibcon#about to read 3, iclass 12, count 2 2006.245.07:20:24.53#ibcon#read 3, iclass 12, count 2 2006.245.07:20:24.53#ibcon#about to read 4, iclass 12, count 2 2006.245.07:20:24.53#ibcon#read 4, iclass 12, count 2 2006.245.07:20:24.53#ibcon#about to read 5, iclass 12, count 2 2006.245.07:20:24.53#ibcon#read 5, iclass 12, count 2 2006.245.07:20:24.53#ibcon#about to read 6, iclass 12, count 2 2006.245.07:20:24.53#ibcon#read 6, iclass 12, count 2 2006.245.07:20:24.53#ibcon#end of sib2, iclass 12, count 2 2006.245.07:20:24.53#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:20:24.53#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:20:24.53#ibcon#[27=AT06-03\r\n] 2006.245.07:20:24.53#ibcon#*before write, iclass 12, count 2 2006.245.07:20:24.53#ibcon#enter sib2, iclass 12, count 2 2006.245.07:20:24.53#ibcon#flushed, iclass 12, count 2 2006.245.07:20:24.53#ibcon#about to write, iclass 12, count 2 2006.245.07:20:24.53#ibcon#wrote, iclass 12, count 2 2006.245.07:20:24.53#ibcon#about to read 3, iclass 12, count 2 2006.245.07:20:24.56#ibcon#read 3, iclass 12, count 2 2006.245.07:20:24.56#ibcon#about to read 4, iclass 12, count 2 2006.245.07:20:24.56#ibcon#read 4, iclass 12, count 2 2006.245.07:20:24.56#ibcon#about to read 5, iclass 12, count 2 2006.245.07:20:24.56#ibcon#read 5, iclass 12, count 2 2006.245.07:20:24.56#ibcon#about to read 6, iclass 12, count 2 2006.245.07:20:24.56#ibcon#read 6, iclass 12, count 2 2006.245.07:20:24.56#ibcon#end of sib2, iclass 12, count 2 2006.245.07:20:24.56#ibcon#*after write, iclass 12, count 2 2006.245.07:20:24.56#ibcon#*before return 0, iclass 12, count 2 2006.245.07:20:24.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:24.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:20:24.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:20:24.56#ibcon#ireg 7 cls_cnt 0 2006.245.07:20:24.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:24.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:24.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:24.68#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:20:24.68#ibcon#first serial, iclass 12, count 0 2006.245.07:20:24.68#ibcon#enter sib2, iclass 12, count 0 2006.245.07:20:24.68#ibcon#flushed, iclass 12, count 0 2006.245.07:20:24.68#ibcon#about to write, iclass 12, count 0 2006.245.07:20:24.68#ibcon#wrote, iclass 12, count 0 2006.245.07:20:24.68#ibcon#about to read 3, iclass 12, count 0 2006.245.07:20:24.70#ibcon#read 3, iclass 12, count 0 2006.245.07:20:24.70#ibcon#about to read 4, iclass 12, count 0 2006.245.07:20:24.70#ibcon#read 4, iclass 12, count 0 2006.245.07:20:24.70#ibcon#about to read 5, iclass 12, count 0 2006.245.07:20:24.70#ibcon#read 5, iclass 12, count 0 2006.245.07:20:24.70#ibcon#about to read 6, iclass 12, count 0 2006.245.07:20:24.70#ibcon#read 6, iclass 12, count 0 2006.245.07:20:24.70#ibcon#end of sib2, iclass 12, count 0 2006.245.07:20:24.70#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:20:24.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:20:24.70#ibcon#[27=USB\r\n] 2006.245.07:20:24.70#ibcon#*before write, iclass 12, count 0 2006.245.07:20:24.70#ibcon#enter sib2, iclass 12, count 0 2006.245.07:20:24.70#ibcon#flushed, iclass 12, count 0 2006.245.07:20:24.70#ibcon#about to write, iclass 12, count 0 2006.245.07:20:24.70#ibcon#wrote, iclass 12, count 0 2006.245.07:20:24.70#ibcon#about to read 3, iclass 12, count 0 2006.245.07:20:24.73#ibcon#read 3, iclass 12, count 0 2006.245.07:20:24.73#ibcon#about to read 4, iclass 12, count 0 2006.245.07:20:24.73#ibcon#read 4, iclass 12, count 0 2006.245.07:20:24.73#ibcon#about to read 5, iclass 12, count 0 2006.245.07:20:24.73#ibcon#read 5, iclass 12, count 0 2006.245.07:20:24.73#ibcon#about to read 6, iclass 12, count 0 2006.245.07:20:24.73#ibcon#read 6, iclass 12, count 0 2006.245.07:20:24.73#ibcon#end of sib2, iclass 12, count 0 2006.245.07:20:24.73#ibcon#*after write, iclass 12, count 0 2006.245.07:20:24.73#ibcon#*before return 0, iclass 12, count 0 2006.245.07:20:24.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:24.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:20:24.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:20:24.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:20:24.73$vc4f8/vabw=wide 2006.245.07:20:24.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:20:24.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:20:24.73#ibcon#ireg 8 cls_cnt 0 2006.245.07:20:24.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:24.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:24.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:24.73#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:20:24.73#ibcon#first serial, iclass 14, count 0 2006.245.07:20:24.73#ibcon#enter sib2, iclass 14, count 0 2006.245.07:20:24.73#ibcon#flushed, iclass 14, count 0 2006.245.07:20:24.73#ibcon#about to write, iclass 14, count 0 2006.245.07:20:24.73#ibcon#wrote, iclass 14, count 0 2006.245.07:20:24.73#ibcon#about to read 3, iclass 14, count 0 2006.245.07:20:24.76#ibcon#read 3, iclass 14, count 0 2006.245.07:20:24.76#ibcon#about to read 4, iclass 14, count 0 2006.245.07:20:24.76#ibcon#read 4, iclass 14, count 0 2006.245.07:20:24.76#ibcon#about to read 5, iclass 14, count 0 2006.245.07:20:24.76#ibcon#read 5, iclass 14, count 0 2006.245.07:20:24.76#ibcon#about to read 6, iclass 14, count 0 2006.245.07:20:24.76#ibcon#read 6, iclass 14, count 0 2006.245.07:20:24.76#ibcon#end of sib2, iclass 14, count 0 2006.245.07:20:24.76#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:20:24.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:20:24.76#ibcon#[25=BW32\r\n] 2006.245.07:20:24.76#ibcon#*before write, iclass 14, count 0 2006.245.07:20:24.76#ibcon#enter sib2, iclass 14, count 0 2006.245.07:20:24.76#ibcon#flushed, iclass 14, count 0 2006.245.07:20:24.76#ibcon#about to write, iclass 14, count 0 2006.245.07:20:24.76#ibcon#wrote, iclass 14, count 0 2006.245.07:20:24.76#ibcon#about to read 3, iclass 14, count 0 2006.245.07:20:24.79#ibcon#read 3, iclass 14, count 0 2006.245.07:20:24.79#ibcon#about to read 4, iclass 14, count 0 2006.245.07:20:24.79#ibcon#read 4, iclass 14, count 0 2006.245.07:20:24.79#ibcon#about to read 5, iclass 14, count 0 2006.245.07:20:24.79#ibcon#read 5, iclass 14, count 0 2006.245.07:20:24.79#ibcon#about to read 6, iclass 14, count 0 2006.245.07:20:24.79#ibcon#read 6, iclass 14, count 0 2006.245.07:20:24.79#ibcon#end of sib2, iclass 14, count 0 2006.245.07:20:24.79#ibcon#*after write, iclass 14, count 0 2006.245.07:20:24.79#ibcon#*before return 0, iclass 14, count 0 2006.245.07:20:24.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:24.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:20:24.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:20:24.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:20:24.79$vc4f8/vbbw=wide 2006.245.07:20:24.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:20:24.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:20:24.79#ibcon#ireg 8 cls_cnt 0 2006.245.07:20:24.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:20:24.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:20:24.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:20:24.86#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:20:24.86#ibcon#first serial, iclass 16, count 0 2006.245.07:20:24.86#ibcon#enter sib2, iclass 16, count 0 2006.245.07:20:24.86#ibcon#flushed, iclass 16, count 0 2006.245.07:20:24.86#ibcon#about to write, iclass 16, count 0 2006.245.07:20:24.86#ibcon#wrote, iclass 16, count 0 2006.245.07:20:24.86#ibcon#about to read 3, iclass 16, count 0 2006.245.07:20:24.87#ibcon#read 3, iclass 16, count 0 2006.245.07:20:24.87#ibcon#about to read 4, iclass 16, count 0 2006.245.07:20:24.87#ibcon#read 4, iclass 16, count 0 2006.245.07:20:24.87#ibcon#about to read 5, iclass 16, count 0 2006.245.07:20:24.87#ibcon#read 5, iclass 16, count 0 2006.245.07:20:24.87#ibcon#about to read 6, iclass 16, count 0 2006.245.07:20:24.87#ibcon#read 6, iclass 16, count 0 2006.245.07:20:24.87#ibcon#end of sib2, iclass 16, count 0 2006.245.07:20:24.87#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:20:24.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:20:24.87#ibcon#[27=BW32\r\n] 2006.245.07:20:24.87#ibcon#*before write, iclass 16, count 0 2006.245.07:20:24.87#ibcon#enter sib2, iclass 16, count 0 2006.245.07:20:24.87#ibcon#flushed, iclass 16, count 0 2006.245.07:20:24.87#ibcon#about to write, iclass 16, count 0 2006.245.07:20:24.87#ibcon#wrote, iclass 16, count 0 2006.245.07:20:24.87#ibcon#about to read 3, iclass 16, count 0 2006.245.07:20:24.90#ibcon#read 3, iclass 16, count 0 2006.245.07:20:24.90#ibcon#about to read 4, iclass 16, count 0 2006.245.07:20:24.90#ibcon#read 4, iclass 16, count 0 2006.245.07:20:24.90#ibcon#about to read 5, iclass 16, count 0 2006.245.07:20:24.90#ibcon#read 5, iclass 16, count 0 2006.245.07:20:24.90#ibcon#about to read 6, iclass 16, count 0 2006.245.07:20:24.90#ibcon#read 6, iclass 16, count 0 2006.245.07:20:24.90#ibcon#end of sib2, iclass 16, count 0 2006.245.07:20:24.90#ibcon#*after write, iclass 16, count 0 2006.245.07:20:24.90#ibcon#*before return 0, iclass 16, count 0 2006.245.07:20:24.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:20:24.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:20:24.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:20:24.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:20:24.90$4f8m12a/ifd4f 2006.245.07:20:24.90&ifd4f/lo= 2006.245.07:20:24.90&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:20:24.90&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:20:24.90&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:20:24.90&ifd4f/patch= 2006.245.07:20:24.90&ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:20:24.90&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:20:24.90&ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:20:24.90$ifd4f/lo= 2006.245.07:20:24.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:20:24.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:20:24.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:20:24.91$ifd4f/patch= 2006.245.07:20:24.91$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:20:24.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:20:24.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:20:24.91$4f8m12a/"form=m,16.000,1:2 2006.245.07:20:24.91$4f8m12a/"tpicd 2006.245.07:20:24.91$4f8m12a/echo=off 2006.245.07:20:24.91$4f8m12a/xlog=off 2006.245.07:20:24.91:!2006.245.07:29:50 2006.245.07:20:34.14#trakl#Source acquired 2006.245.07:20:35.14#flagr#flagr/antenna,acquired 2006.245.07:29:50.00:preob 2006.245.07:29:50.00&preob/onsource 2006.245.07:29:51.13/onsource/TRACKING 2006.245.07:29:51.13:!2006.245.07:30:00 2006.245.07:30:00.00:data_valid=on 2006.245.07:30:00.00:midob 2006.245.07:30:00.00&midob/onsource 2006.245.07:30:00.00&midob/wx 2006.245.07:30:00.00&midob/cable 2006.245.07:30:00.00&midob/va 2006.245.07:30:00.00&midob/valo 2006.245.07:30:00.00&midob/vb 2006.245.07:30:00.00&midob/vblo 2006.245.07:30:00.00&midob/vabw 2006.245.07:30:00.00&midob/vbbw 2006.245.07:30:00.00&midob/"form 2006.245.07:30:00.00&midob/xfe 2006.245.07:30:00.00&midob/ifatt 2006.245.07:30:00.00&midob/clockoff 2006.245.07:30:00.00&midob/sy=logmail 2006.245.07:30:00.00&midob/"sy=run setcl adapt & 2006.245.07:30:00.13/onsource/TRACKING 2006.245.07:30:00.13/wx/27.66,1004.4,67 2006.245.07:30:00.22/cable/+6.4081E-03 2006.245.07:30:01.31/va/01,08,usb,yes,31,33 2006.245.07:30:01.31/va/02,07,usb,yes,31,33 2006.245.07:30:01.31/va/03,06,usb,yes,33,33 2006.245.07:30:01.31/va/04,07,usb,yes,32,35 2006.245.07:30:01.31/va/05,07,usb,yes,34,35 2006.245.07:30:01.31/va/06,07,usb,yes,29,29 2006.245.07:30:01.31/va/07,07,usb,yes,29,29 2006.245.07:30:01.31/va/08,08,usb,yes,25,25 2006.245.07:30:01.54/valo/01,532.99,yes,locked 2006.245.07:30:01.54/valo/02,572.99,yes,locked 2006.245.07:30:01.54/valo/03,672.99,yes,locked 2006.245.07:30:01.54/valo/04,832.99,yes,locked 2006.245.07:30:01.54/valo/05,652.99,yes,locked 2006.245.07:30:01.54/valo/06,772.99,yes,locked 2006.245.07:30:01.54/valo/07,832.99,yes,locked 2006.245.07:30:01.54/valo/08,852.99,yes,locked 2006.245.07:30:02.63/vb/01,04,usb,yes,31,30 2006.245.07:30:02.63/vb/02,04,usb,yes,33,35 2006.245.07:30:02.63/vb/03,04,usb,yes,29,33 2006.245.07:30:02.63/vb/04,04,usb,yes,30,30 2006.245.07:30:02.63/vb/05,03,usb,yes,36,40 2006.245.07:30:02.63/vb/06,03,usb,yes,36,40 2006.245.07:30:02.63/vb/07,04,usb,yes,32,32 2006.245.07:30:02.63/vb/08,03,usb,yes,36,40 2006.245.07:30:02.87/vblo/01,632.99,yes,locked 2006.245.07:30:02.87/vblo/02,640.99,yes,locked 2006.245.07:30:02.87/vblo/03,656.99,yes,locked 2006.245.07:30:02.87/vblo/04,712.99,yes,locked 2006.245.07:30:02.87/vblo/05,744.99,yes,locked 2006.245.07:30:02.87/vblo/06,752.99,yes,locked 2006.245.07:30:02.87/vblo/07,734.99,yes,locked 2006.245.07:30:02.87/vblo/08,744.99,yes,locked 2006.245.07:30:03.02/vabw/8 2006.245.07:30:03.17/vbbw/8 2006.245.07:30:03.32/xfe/off,on,14.2 2006.245.07:30:03.70/ifatt/23,28,28,28 2006.245.07:30:04.07/fmout-gps/S +4.49E-07 2006.245.07:30:04.13:!2006.245.07:31:00 2006.245.07:31:00.01:data_valid=off 2006.245.07:31:00.02:postob 2006.245.07:31:00.02&postob/cable 2006.245.07:31:00.02&postob/wx 2006.245.07:31:00.03&postob/clockoff 2006.245.07:31:00.22/cable/+6.4117E-03 2006.245.07:31:00.22/wx/27.65,1004.4,67 2006.245.07:31:00.29/fmout-gps/S +4.48E-07 2006.245.07:31:00.29:scan_name=245-0733,k06245,60 2006.245.07:31:00.29:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.245.07:31:01.13#flagr#flagr/antenna,new-source 2006.245.07:31:01.13:checkk5 2006.245.07:31:01.13&checkk5/chk_autoobs=1 2006.245.07:31:01.13&checkk5/chk_autoobs=2 2006.245.07:31:01.13&checkk5/chk_autoobs=3 2006.245.07:31:01.13&checkk5/chk_autoobs=4 2006.245.07:31:01.13&checkk5/chk_obsdata=1 2006.245.07:31:01.13&checkk5/chk_obsdata=2 2006.245.07:31:01.13&checkk5/chk_obsdata=3 2006.245.07:31:01.13&checkk5/chk_obsdata=4 2006.245.07:31:01.13&checkk5/k5log=1 2006.245.07:31:01.13&checkk5/k5log=2 2006.245.07:31:01.13&checkk5/k5log=3 2006.245.07:31:01.13&checkk5/k5log=4 2006.245.07:31:01.13&checkk5/obsinfo 2006.245.07:31:01.62/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:31:02.19/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:31:03.75/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:31:05.35/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:31:06.00/chk_obsdata//k5ts1/T2450730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:31:06.45/chk_obsdata//k5ts2/T2450730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:31:06.88/chk_obsdata//k5ts3/T2450730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:31:07.37/chk_obsdata//k5ts4/T2450730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:31:08.75/k5log//k5ts1_log_newline 2006.245.07:31:09.55/k5log//k5ts2_log_newline 2006.245.07:31:10.54/k5log//k5ts3_log_newline 2006.245.07:31:11.36/k5log//k5ts4_log_newline 2006.245.07:31:11.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:31:11.39:4f8m12a=1 2006.245.07:31:11.39$4f8m12a/echo=on 2006.245.07:31:11.39$4f8m12a/pcalon 2006.245.07:31:11.39$pcalon/"no phase cal control is implemented here 2006.245.07:31:11.39$4f8m12a/"tpicd=stop 2006.245.07:31:11.39$4f8m12a/vc4f8 2006.245.07:31:11.39$vc4f8/valo=1,532.99 2006.245.07:31:11.39#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.07:31:11.39#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.07:31:11.39#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:11.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:11.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:11.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:11.39#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:31:11.39#ibcon#first serial, iclass 23, count 0 2006.245.07:31:11.39#ibcon#enter sib2, iclass 23, count 0 2006.245.07:31:11.39#ibcon#flushed, iclass 23, count 0 2006.245.07:31:11.39#ibcon#about to write, iclass 23, count 0 2006.245.07:31:11.39#ibcon#wrote, iclass 23, count 0 2006.245.07:31:11.39#ibcon#about to read 3, iclass 23, count 0 2006.245.07:31:11.43#ibcon#read 3, iclass 23, count 0 2006.245.07:31:11.43#ibcon#about to read 4, iclass 23, count 0 2006.245.07:31:11.43#ibcon#read 4, iclass 23, count 0 2006.245.07:31:11.43#ibcon#about to read 5, iclass 23, count 0 2006.245.07:31:11.43#ibcon#read 5, iclass 23, count 0 2006.245.07:31:11.43#ibcon#about to read 6, iclass 23, count 0 2006.245.07:31:11.43#ibcon#read 6, iclass 23, count 0 2006.245.07:31:11.43#ibcon#end of sib2, iclass 23, count 0 2006.245.07:31:11.43#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:31:11.43#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:31:11.43#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:31:11.43#ibcon#*before write, iclass 23, count 0 2006.245.07:31:11.43#ibcon#enter sib2, iclass 23, count 0 2006.245.07:31:11.43#ibcon#flushed, iclass 23, count 0 2006.245.07:31:11.43#ibcon#about to write, iclass 23, count 0 2006.245.07:31:11.43#ibcon#wrote, iclass 23, count 0 2006.245.07:31:11.43#ibcon#about to read 3, iclass 23, count 0 2006.245.07:31:11.48#ibcon#read 3, iclass 23, count 0 2006.245.07:31:11.48#ibcon#about to read 4, iclass 23, count 0 2006.245.07:31:11.48#ibcon#read 4, iclass 23, count 0 2006.245.07:31:11.48#ibcon#about to read 5, iclass 23, count 0 2006.245.07:31:11.48#ibcon#read 5, iclass 23, count 0 2006.245.07:31:11.48#ibcon#about to read 6, iclass 23, count 0 2006.245.07:31:11.48#ibcon#read 6, iclass 23, count 0 2006.245.07:31:11.48#ibcon#end of sib2, iclass 23, count 0 2006.245.07:31:11.48#ibcon#*after write, iclass 23, count 0 2006.245.07:31:11.48#ibcon#*before return 0, iclass 23, count 0 2006.245.07:31:11.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:11.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:11.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:31:11.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:31:11.48$vc4f8/va=1,8 2006.245.07:31:11.48#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.07:31:11.48#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.07:31:11.48#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:11.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:11.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:11.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:11.48#ibcon#enter wrdev, iclass 25, count 2 2006.245.07:31:11.48#ibcon#first serial, iclass 25, count 2 2006.245.07:31:11.48#ibcon#enter sib2, iclass 25, count 2 2006.245.07:31:11.48#ibcon#flushed, iclass 25, count 2 2006.245.07:31:11.48#ibcon#about to write, iclass 25, count 2 2006.245.07:31:11.48#ibcon#wrote, iclass 25, count 2 2006.245.07:31:11.48#ibcon#about to read 3, iclass 25, count 2 2006.245.07:31:11.50#ibcon#read 3, iclass 25, count 2 2006.245.07:31:11.50#ibcon#about to read 4, iclass 25, count 2 2006.245.07:31:11.50#ibcon#read 4, iclass 25, count 2 2006.245.07:31:11.50#ibcon#about to read 5, iclass 25, count 2 2006.245.07:31:11.50#ibcon#read 5, iclass 25, count 2 2006.245.07:31:11.50#ibcon#about to read 6, iclass 25, count 2 2006.245.07:31:11.50#ibcon#read 6, iclass 25, count 2 2006.245.07:31:11.50#ibcon#end of sib2, iclass 25, count 2 2006.245.07:31:11.50#ibcon#*mode == 0, iclass 25, count 2 2006.245.07:31:11.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.07:31:11.50#ibcon#[25=AT01-08\r\n] 2006.245.07:31:11.50#ibcon#*before write, iclass 25, count 2 2006.245.07:31:11.50#ibcon#enter sib2, iclass 25, count 2 2006.245.07:31:11.50#ibcon#flushed, iclass 25, count 2 2006.245.07:31:11.50#ibcon#about to write, iclass 25, count 2 2006.245.07:31:11.50#ibcon#wrote, iclass 25, count 2 2006.245.07:31:11.50#ibcon#about to read 3, iclass 25, count 2 2006.245.07:31:11.53#ibcon#read 3, iclass 25, count 2 2006.245.07:31:11.53#ibcon#about to read 4, iclass 25, count 2 2006.245.07:31:11.53#ibcon#read 4, iclass 25, count 2 2006.245.07:31:11.53#ibcon#about to read 5, iclass 25, count 2 2006.245.07:31:11.53#ibcon#read 5, iclass 25, count 2 2006.245.07:31:11.53#ibcon#about to read 6, iclass 25, count 2 2006.245.07:31:11.53#ibcon#read 6, iclass 25, count 2 2006.245.07:31:11.53#ibcon#end of sib2, iclass 25, count 2 2006.245.07:31:11.53#ibcon#*after write, iclass 25, count 2 2006.245.07:31:11.53#ibcon#*before return 0, iclass 25, count 2 2006.245.07:31:11.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:11.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:11.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.07:31:11.53#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:11.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:11.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:11.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:11.65#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:31:11.65#ibcon#first serial, iclass 25, count 0 2006.245.07:31:11.65#ibcon#enter sib2, iclass 25, count 0 2006.245.07:31:11.65#ibcon#flushed, iclass 25, count 0 2006.245.07:31:11.65#ibcon#about to write, iclass 25, count 0 2006.245.07:31:11.65#ibcon#wrote, iclass 25, count 0 2006.245.07:31:11.65#ibcon#about to read 3, iclass 25, count 0 2006.245.07:31:11.67#ibcon#read 3, iclass 25, count 0 2006.245.07:31:11.67#ibcon#about to read 4, iclass 25, count 0 2006.245.07:31:11.67#ibcon#read 4, iclass 25, count 0 2006.245.07:31:11.67#ibcon#about to read 5, iclass 25, count 0 2006.245.07:31:11.67#ibcon#read 5, iclass 25, count 0 2006.245.07:31:11.67#ibcon#about to read 6, iclass 25, count 0 2006.245.07:31:11.67#ibcon#read 6, iclass 25, count 0 2006.245.07:31:11.67#ibcon#end of sib2, iclass 25, count 0 2006.245.07:31:11.67#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:31:11.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:31:11.67#ibcon#[25=USB\r\n] 2006.245.07:31:11.67#ibcon#*before write, iclass 25, count 0 2006.245.07:31:11.67#ibcon#enter sib2, iclass 25, count 0 2006.245.07:31:11.67#ibcon#flushed, iclass 25, count 0 2006.245.07:31:11.67#ibcon#about to write, iclass 25, count 0 2006.245.07:31:11.67#ibcon#wrote, iclass 25, count 0 2006.245.07:31:11.67#ibcon#about to read 3, iclass 25, count 0 2006.245.07:31:11.70#ibcon#read 3, iclass 25, count 0 2006.245.07:31:11.70#ibcon#about to read 4, iclass 25, count 0 2006.245.07:31:11.70#ibcon#read 4, iclass 25, count 0 2006.245.07:31:11.70#ibcon#about to read 5, iclass 25, count 0 2006.245.07:31:11.70#ibcon#read 5, iclass 25, count 0 2006.245.07:31:11.70#ibcon#about to read 6, iclass 25, count 0 2006.245.07:31:11.70#ibcon#read 6, iclass 25, count 0 2006.245.07:31:11.70#ibcon#end of sib2, iclass 25, count 0 2006.245.07:31:11.70#ibcon#*after write, iclass 25, count 0 2006.245.07:31:11.70#ibcon#*before return 0, iclass 25, count 0 2006.245.07:31:11.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:11.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:11.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:31:11.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:31:11.70$vc4f8/valo=2,572.99 2006.245.07:31:11.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:31:11.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:31:11.70#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:11.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:11.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:11.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:11.70#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:31:11.70#ibcon#first serial, iclass 27, count 0 2006.245.07:31:11.70#ibcon#enter sib2, iclass 27, count 0 2006.245.07:31:11.70#ibcon#flushed, iclass 27, count 0 2006.245.07:31:11.70#ibcon#about to write, iclass 27, count 0 2006.245.07:31:11.70#ibcon#wrote, iclass 27, count 0 2006.245.07:31:11.70#ibcon#about to read 3, iclass 27, count 0 2006.245.07:31:11.72#ibcon#read 3, iclass 27, count 0 2006.245.07:31:11.72#ibcon#about to read 4, iclass 27, count 0 2006.245.07:31:11.72#ibcon#read 4, iclass 27, count 0 2006.245.07:31:11.72#ibcon#about to read 5, iclass 27, count 0 2006.245.07:31:11.72#ibcon#read 5, iclass 27, count 0 2006.245.07:31:11.72#ibcon#about to read 6, iclass 27, count 0 2006.245.07:31:11.72#ibcon#read 6, iclass 27, count 0 2006.245.07:31:11.72#ibcon#end of sib2, iclass 27, count 0 2006.245.07:31:11.72#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:31:11.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:31:11.72#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:31:11.72#ibcon#*before write, iclass 27, count 0 2006.245.07:31:11.72#ibcon#enter sib2, iclass 27, count 0 2006.245.07:31:11.72#ibcon#flushed, iclass 27, count 0 2006.245.07:31:11.72#ibcon#about to write, iclass 27, count 0 2006.245.07:31:11.72#ibcon#wrote, iclass 27, count 0 2006.245.07:31:11.72#ibcon#about to read 3, iclass 27, count 0 2006.245.07:31:11.76#ibcon#read 3, iclass 27, count 0 2006.245.07:31:11.76#ibcon#about to read 4, iclass 27, count 0 2006.245.07:31:11.76#ibcon#read 4, iclass 27, count 0 2006.245.07:31:11.76#ibcon#about to read 5, iclass 27, count 0 2006.245.07:31:11.76#ibcon#read 5, iclass 27, count 0 2006.245.07:31:11.76#ibcon#about to read 6, iclass 27, count 0 2006.245.07:31:11.76#ibcon#read 6, iclass 27, count 0 2006.245.07:31:11.76#ibcon#end of sib2, iclass 27, count 0 2006.245.07:31:11.76#ibcon#*after write, iclass 27, count 0 2006.245.07:31:11.76#ibcon#*before return 0, iclass 27, count 0 2006.245.07:31:11.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:11.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:11.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:31:11.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:31:11.76$vc4f8/va=2,7 2006.245.07:31:11.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:31:11.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:31:11.76#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:11.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:11.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:11.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:11.83#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:31:11.83#ibcon#first serial, iclass 29, count 2 2006.245.07:31:11.83#ibcon#enter sib2, iclass 29, count 2 2006.245.07:31:11.83#ibcon#flushed, iclass 29, count 2 2006.245.07:31:11.83#ibcon#about to write, iclass 29, count 2 2006.245.07:31:11.83#ibcon#wrote, iclass 29, count 2 2006.245.07:31:11.83#ibcon#about to read 3, iclass 29, count 2 2006.245.07:31:11.84#ibcon#read 3, iclass 29, count 2 2006.245.07:31:11.84#ibcon#about to read 4, iclass 29, count 2 2006.245.07:31:11.84#ibcon#read 4, iclass 29, count 2 2006.245.07:31:11.84#ibcon#about to read 5, iclass 29, count 2 2006.245.07:31:11.84#ibcon#read 5, iclass 29, count 2 2006.245.07:31:11.84#ibcon#about to read 6, iclass 29, count 2 2006.245.07:31:11.84#ibcon#read 6, iclass 29, count 2 2006.245.07:31:11.84#ibcon#end of sib2, iclass 29, count 2 2006.245.07:31:11.84#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:31:11.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:31:11.84#ibcon#[25=AT02-07\r\n] 2006.245.07:31:11.84#ibcon#*before write, iclass 29, count 2 2006.245.07:31:11.84#ibcon#enter sib2, iclass 29, count 2 2006.245.07:31:11.84#ibcon#flushed, iclass 29, count 2 2006.245.07:31:11.84#ibcon#about to write, iclass 29, count 2 2006.245.07:31:11.84#ibcon#wrote, iclass 29, count 2 2006.245.07:31:11.84#ibcon#about to read 3, iclass 29, count 2 2006.245.07:31:11.87#ibcon#read 3, iclass 29, count 2 2006.245.07:31:11.87#ibcon#about to read 4, iclass 29, count 2 2006.245.07:31:11.87#ibcon#read 4, iclass 29, count 2 2006.245.07:31:11.87#ibcon#about to read 5, iclass 29, count 2 2006.245.07:31:11.87#ibcon#read 5, iclass 29, count 2 2006.245.07:31:11.87#ibcon#about to read 6, iclass 29, count 2 2006.245.07:31:11.87#ibcon#read 6, iclass 29, count 2 2006.245.07:31:11.87#ibcon#end of sib2, iclass 29, count 2 2006.245.07:31:11.87#ibcon#*after write, iclass 29, count 2 2006.245.07:31:11.87#ibcon#*before return 0, iclass 29, count 2 2006.245.07:31:11.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:11.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:11.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:31:11.87#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:11.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:11.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:11.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:11.99#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:31:11.99#ibcon#first serial, iclass 29, count 0 2006.245.07:31:11.99#ibcon#enter sib2, iclass 29, count 0 2006.245.07:31:11.99#ibcon#flushed, iclass 29, count 0 2006.245.07:31:11.99#ibcon#about to write, iclass 29, count 0 2006.245.07:31:11.99#ibcon#wrote, iclass 29, count 0 2006.245.07:31:11.99#ibcon#about to read 3, iclass 29, count 0 2006.245.07:31:12.01#ibcon#read 3, iclass 29, count 0 2006.245.07:31:12.01#ibcon#about to read 4, iclass 29, count 0 2006.245.07:31:12.01#ibcon#read 4, iclass 29, count 0 2006.245.07:31:12.01#ibcon#about to read 5, iclass 29, count 0 2006.245.07:31:12.01#ibcon#read 5, iclass 29, count 0 2006.245.07:31:12.01#ibcon#about to read 6, iclass 29, count 0 2006.245.07:31:12.01#ibcon#read 6, iclass 29, count 0 2006.245.07:31:12.01#ibcon#end of sib2, iclass 29, count 0 2006.245.07:31:12.01#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:31:12.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:31:12.01#ibcon#[25=USB\r\n] 2006.245.07:31:12.01#ibcon#*before write, iclass 29, count 0 2006.245.07:31:12.01#ibcon#enter sib2, iclass 29, count 0 2006.245.07:31:12.01#ibcon#flushed, iclass 29, count 0 2006.245.07:31:12.01#ibcon#about to write, iclass 29, count 0 2006.245.07:31:12.01#ibcon#wrote, iclass 29, count 0 2006.245.07:31:12.01#ibcon#about to read 3, iclass 29, count 0 2006.245.07:31:12.04#ibcon#read 3, iclass 29, count 0 2006.245.07:31:12.04#ibcon#about to read 4, iclass 29, count 0 2006.245.07:31:12.04#ibcon#read 4, iclass 29, count 0 2006.245.07:31:12.04#ibcon#about to read 5, iclass 29, count 0 2006.245.07:31:12.04#ibcon#read 5, iclass 29, count 0 2006.245.07:31:12.04#ibcon#about to read 6, iclass 29, count 0 2006.245.07:31:12.04#ibcon#read 6, iclass 29, count 0 2006.245.07:31:12.04#ibcon#end of sib2, iclass 29, count 0 2006.245.07:31:12.04#ibcon#*after write, iclass 29, count 0 2006.245.07:31:12.04#ibcon#*before return 0, iclass 29, count 0 2006.245.07:31:12.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:12.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:12.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:31:12.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:31:12.04$vc4f8/valo=3,672.99 2006.245.07:31:12.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:31:12.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:31:12.04#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:12.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:12.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:12.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:12.04#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:31:12.04#ibcon#first serial, iclass 31, count 0 2006.245.07:31:12.04#ibcon#enter sib2, iclass 31, count 0 2006.245.07:31:12.04#ibcon#flushed, iclass 31, count 0 2006.245.07:31:12.04#ibcon#about to write, iclass 31, count 0 2006.245.07:31:12.04#ibcon#wrote, iclass 31, count 0 2006.245.07:31:12.04#ibcon#about to read 3, iclass 31, count 0 2006.245.07:31:12.06#ibcon#read 3, iclass 31, count 0 2006.245.07:31:12.06#ibcon#about to read 4, iclass 31, count 0 2006.245.07:31:12.06#ibcon#read 4, iclass 31, count 0 2006.245.07:31:12.06#ibcon#about to read 5, iclass 31, count 0 2006.245.07:31:12.06#ibcon#read 5, iclass 31, count 0 2006.245.07:31:12.06#ibcon#about to read 6, iclass 31, count 0 2006.245.07:31:12.06#ibcon#read 6, iclass 31, count 0 2006.245.07:31:12.06#ibcon#end of sib2, iclass 31, count 0 2006.245.07:31:12.06#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:31:12.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:31:12.06#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:31:12.06#ibcon#*before write, iclass 31, count 0 2006.245.07:31:12.06#ibcon#enter sib2, iclass 31, count 0 2006.245.07:31:12.06#ibcon#flushed, iclass 31, count 0 2006.245.07:31:12.06#ibcon#about to write, iclass 31, count 0 2006.245.07:31:12.06#ibcon#wrote, iclass 31, count 0 2006.245.07:31:12.06#ibcon#about to read 3, iclass 31, count 0 2006.245.07:31:12.10#ibcon#read 3, iclass 31, count 0 2006.245.07:31:12.10#ibcon#about to read 4, iclass 31, count 0 2006.245.07:31:12.10#ibcon#read 4, iclass 31, count 0 2006.245.07:31:12.10#ibcon#about to read 5, iclass 31, count 0 2006.245.07:31:12.10#ibcon#read 5, iclass 31, count 0 2006.245.07:31:12.10#ibcon#about to read 6, iclass 31, count 0 2006.245.07:31:12.10#ibcon#read 6, iclass 31, count 0 2006.245.07:31:12.10#ibcon#end of sib2, iclass 31, count 0 2006.245.07:31:12.10#ibcon#*after write, iclass 31, count 0 2006.245.07:31:12.10#ibcon#*before return 0, iclass 31, count 0 2006.245.07:31:12.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:12.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:12.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:31:12.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:31:12.10$vc4f8/va=3,6 2006.245.07:31:12.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:31:12.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:31:12.10#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:12.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:12.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:12.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:12.16#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:31:12.16#ibcon#first serial, iclass 33, count 2 2006.245.07:31:12.16#ibcon#enter sib2, iclass 33, count 2 2006.245.07:31:12.16#ibcon#flushed, iclass 33, count 2 2006.245.07:31:12.16#ibcon#about to write, iclass 33, count 2 2006.245.07:31:12.16#ibcon#wrote, iclass 33, count 2 2006.245.07:31:12.16#ibcon#about to read 3, iclass 33, count 2 2006.245.07:31:12.18#ibcon#read 3, iclass 33, count 2 2006.245.07:31:12.18#ibcon#about to read 4, iclass 33, count 2 2006.245.07:31:12.18#ibcon#read 4, iclass 33, count 2 2006.245.07:31:12.18#ibcon#about to read 5, iclass 33, count 2 2006.245.07:31:12.18#ibcon#read 5, iclass 33, count 2 2006.245.07:31:12.18#ibcon#about to read 6, iclass 33, count 2 2006.245.07:31:12.18#ibcon#read 6, iclass 33, count 2 2006.245.07:31:12.18#ibcon#end of sib2, iclass 33, count 2 2006.245.07:31:12.18#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:31:12.18#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:31:12.18#ibcon#[25=AT03-06\r\n] 2006.245.07:31:12.18#ibcon#*before write, iclass 33, count 2 2006.245.07:31:12.18#ibcon#enter sib2, iclass 33, count 2 2006.245.07:31:12.18#ibcon#flushed, iclass 33, count 2 2006.245.07:31:12.18#ibcon#about to write, iclass 33, count 2 2006.245.07:31:12.18#ibcon#wrote, iclass 33, count 2 2006.245.07:31:12.18#ibcon#about to read 3, iclass 33, count 2 2006.245.07:31:12.21#ibcon#read 3, iclass 33, count 2 2006.245.07:31:12.21#ibcon#about to read 4, iclass 33, count 2 2006.245.07:31:12.21#ibcon#read 4, iclass 33, count 2 2006.245.07:31:12.21#ibcon#about to read 5, iclass 33, count 2 2006.245.07:31:12.21#ibcon#read 5, iclass 33, count 2 2006.245.07:31:12.21#ibcon#about to read 6, iclass 33, count 2 2006.245.07:31:12.21#ibcon#read 6, iclass 33, count 2 2006.245.07:31:12.21#ibcon#end of sib2, iclass 33, count 2 2006.245.07:31:12.21#ibcon#*after write, iclass 33, count 2 2006.245.07:31:12.21#ibcon#*before return 0, iclass 33, count 2 2006.245.07:31:12.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:12.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:12.21#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:31:12.21#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:12.21#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:12.33#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:12.33#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:12.33#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:31:12.33#ibcon#first serial, iclass 33, count 0 2006.245.07:31:12.33#ibcon#enter sib2, iclass 33, count 0 2006.245.07:31:12.33#ibcon#flushed, iclass 33, count 0 2006.245.07:31:12.33#ibcon#about to write, iclass 33, count 0 2006.245.07:31:12.33#ibcon#wrote, iclass 33, count 0 2006.245.07:31:12.33#ibcon#about to read 3, iclass 33, count 0 2006.245.07:31:12.35#ibcon#read 3, iclass 33, count 0 2006.245.07:31:12.35#ibcon#about to read 4, iclass 33, count 0 2006.245.07:31:12.35#ibcon#read 4, iclass 33, count 0 2006.245.07:31:12.35#ibcon#about to read 5, iclass 33, count 0 2006.245.07:31:12.35#ibcon#read 5, iclass 33, count 0 2006.245.07:31:12.35#ibcon#about to read 6, iclass 33, count 0 2006.245.07:31:12.35#ibcon#read 6, iclass 33, count 0 2006.245.07:31:12.35#ibcon#end of sib2, iclass 33, count 0 2006.245.07:31:12.35#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:31:12.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:31:12.35#ibcon#[25=USB\r\n] 2006.245.07:31:12.35#ibcon#*before write, iclass 33, count 0 2006.245.07:31:12.35#ibcon#enter sib2, iclass 33, count 0 2006.245.07:31:12.35#ibcon#flushed, iclass 33, count 0 2006.245.07:31:12.35#ibcon#about to write, iclass 33, count 0 2006.245.07:31:12.35#ibcon#wrote, iclass 33, count 0 2006.245.07:31:12.35#ibcon#about to read 3, iclass 33, count 0 2006.245.07:31:12.38#ibcon#read 3, iclass 33, count 0 2006.245.07:31:12.38#ibcon#about to read 4, iclass 33, count 0 2006.245.07:31:12.38#ibcon#read 4, iclass 33, count 0 2006.245.07:31:12.38#ibcon#about to read 5, iclass 33, count 0 2006.245.07:31:12.38#ibcon#read 5, iclass 33, count 0 2006.245.07:31:12.38#ibcon#about to read 6, iclass 33, count 0 2006.245.07:31:12.38#ibcon#read 6, iclass 33, count 0 2006.245.07:31:12.38#ibcon#end of sib2, iclass 33, count 0 2006.245.07:31:12.38#ibcon#*after write, iclass 33, count 0 2006.245.07:31:12.38#ibcon#*before return 0, iclass 33, count 0 2006.245.07:31:12.38#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:12.38#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:12.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:31:12.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:31:12.38$vc4f8/valo=4,832.99 2006.245.07:31:12.38#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:31:12.38#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:31:12.38#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:12.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:12.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:12.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:12.38#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:31:12.38#ibcon#first serial, iclass 35, count 0 2006.245.07:31:12.38#ibcon#enter sib2, iclass 35, count 0 2006.245.07:31:12.38#ibcon#flushed, iclass 35, count 0 2006.245.07:31:12.38#ibcon#about to write, iclass 35, count 0 2006.245.07:31:12.38#ibcon#wrote, iclass 35, count 0 2006.245.07:31:12.38#ibcon#about to read 3, iclass 35, count 0 2006.245.07:31:12.40#ibcon#read 3, iclass 35, count 0 2006.245.07:31:12.40#ibcon#about to read 4, iclass 35, count 0 2006.245.07:31:12.40#ibcon#read 4, iclass 35, count 0 2006.245.07:31:12.40#ibcon#about to read 5, iclass 35, count 0 2006.245.07:31:12.40#ibcon#read 5, iclass 35, count 0 2006.245.07:31:12.40#ibcon#about to read 6, iclass 35, count 0 2006.245.07:31:12.40#ibcon#read 6, iclass 35, count 0 2006.245.07:31:12.40#ibcon#end of sib2, iclass 35, count 0 2006.245.07:31:12.40#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:31:12.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:31:12.40#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:31:12.40#ibcon#*before write, iclass 35, count 0 2006.245.07:31:12.40#ibcon#enter sib2, iclass 35, count 0 2006.245.07:31:12.40#ibcon#flushed, iclass 35, count 0 2006.245.07:31:12.40#ibcon#about to write, iclass 35, count 0 2006.245.07:31:12.40#ibcon#wrote, iclass 35, count 0 2006.245.07:31:12.40#ibcon#about to read 3, iclass 35, count 0 2006.245.07:31:12.44#ibcon#read 3, iclass 35, count 0 2006.245.07:31:12.44#ibcon#about to read 4, iclass 35, count 0 2006.245.07:31:12.44#ibcon#read 4, iclass 35, count 0 2006.245.07:31:12.44#ibcon#about to read 5, iclass 35, count 0 2006.245.07:31:12.44#ibcon#read 5, iclass 35, count 0 2006.245.07:31:12.44#ibcon#about to read 6, iclass 35, count 0 2006.245.07:31:12.44#ibcon#read 6, iclass 35, count 0 2006.245.07:31:12.44#ibcon#end of sib2, iclass 35, count 0 2006.245.07:31:12.44#ibcon#*after write, iclass 35, count 0 2006.245.07:31:12.44#ibcon#*before return 0, iclass 35, count 0 2006.245.07:31:12.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:12.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:12.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:31:12.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:31:12.44$vc4f8/va=4,7 2006.245.07:31:12.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:31:12.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:31:12.44#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:12.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:12.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:12.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:12.50#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:31:12.50#ibcon#first serial, iclass 37, count 2 2006.245.07:31:12.50#ibcon#enter sib2, iclass 37, count 2 2006.245.07:31:12.50#ibcon#flushed, iclass 37, count 2 2006.245.07:31:12.50#ibcon#about to write, iclass 37, count 2 2006.245.07:31:12.50#ibcon#wrote, iclass 37, count 2 2006.245.07:31:12.50#ibcon#about to read 3, iclass 37, count 2 2006.245.07:31:12.52#ibcon#read 3, iclass 37, count 2 2006.245.07:31:12.52#ibcon#about to read 4, iclass 37, count 2 2006.245.07:31:12.52#ibcon#read 4, iclass 37, count 2 2006.245.07:31:12.52#ibcon#about to read 5, iclass 37, count 2 2006.245.07:31:12.52#ibcon#read 5, iclass 37, count 2 2006.245.07:31:12.52#ibcon#about to read 6, iclass 37, count 2 2006.245.07:31:12.52#ibcon#read 6, iclass 37, count 2 2006.245.07:31:12.52#ibcon#end of sib2, iclass 37, count 2 2006.245.07:31:12.52#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:31:12.52#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:31:12.52#ibcon#[25=AT04-07\r\n] 2006.245.07:31:12.52#ibcon#*before write, iclass 37, count 2 2006.245.07:31:12.52#ibcon#enter sib2, iclass 37, count 2 2006.245.07:31:12.52#ibcon#flushed, iclass 37, count 2 2006.245.07:31:12.52#ibcon#about to write, iclass 37, count 2 2006.245.07:31:12.52#ibcon#wrote, iclass 37, count 2 2006.245.07:31:12.52#ibcon#about to read 3, iclass 37, count 2 2006.245.07:31:12.55#ibcon#read 3, iclass 37, count 2 2006.245.07:31:12.55#ibcon#about to read 4, iclass 37, count 2 2006.245.07:31:12.55#ibcon#read 4, iclass 37, count 2 2006.245.07:31:12.55#ibcon#about to read 5, iclass 37, count 2 2006.245.07:31:12.55#ibcon#read 5, iclass 37, count 2 2006.245.07:31:12.55#ibcon#about to read 6, iclass 37, count 2 2006.245.07:31:12.55#ibcon#read 6, iclass 37, count 2 2006.245.07:31:12.55#ibcon#end of sib2, iclass 37, count 2 2006.245.07:31:12.55#ibcon#*after write, iclass 37, count 2 2006.245.07:31:12.55#ibcon#*before return 0, iclass 37, count 2 2006.245.07:31:12.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:12.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:12.55#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:31:12.55#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:12.55#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:12.67#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:12.67#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:12.67#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:31:12.67#ibcon#first serial, iclass 37, count 0 2006.245.07:31:12.67#ibcon#enter sib2, iclass 37, count 0 2006.245.07:31:12.67#ibcon#flushed, iclass 37, count 0 2006.245.07:31:12.67#ibcon#about to write, iclass 37, count 0 2006.245.07:31:12.67#ibcon#wrote, iclass 37, count 0 2006.245.07:31:12.67#ibcon#about to read 3, iclass 37, count 0 2006.245.07:31:12.69#ibcon#read 3, iclass 37, count 0 2006.245.07:31:12.69#ibcon#about to read 4, iclass 37, count 0 2006.245.07:31:12.69#ibcon#read 4, iclass 37, count 0 2006.245.07:31:12.69#ibcon#about to read 5, iclass 37, count 0 2006.245.07:31:12.69#ibcon#read 5, iclass 37, count 0 2006.245.07:31:12.69#ibcon#about to read 6, iclass 37, count 0 2006.245.07:31:12.69#ibcon#read 6, iclass 37, count 0 2006.245.07:31:12.69#ibcon#end of sib2, iclass 37, count 0 2006.245.07:31:12.69#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:31:12.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:31:12.69#ibcon#[25=USB\r\n] 2006.245.07:31:12.69#ibcon#*before write, iclass 37, count 0 2006.245.07:31:12.69#ibcon#enter sib2, iclass 37, count 0 2006.245.07:31:12.69#ibcon#flushed, iclass 37, count 0 2006.245.07:31:12.69#ibcon#about to write, iclass 37, count 0 2006.245.07:31:12.69#ibcon#wrote, iclass 37, count 0 2006.245.07:31:12.69#ibcon#about to read 3, iclass 37, count 0 2006.245.07:31:12.72#ibcon#read 3, iclass 37, count 0 2006.245.07:31:12.72#ibcon#about to read 4, iclass 37, count 0 2006.245.07:31:12.72#ibcon#read 4, iclass 37, count 0 2006.245.07:31:12.72#ibcon#about to read 5, iclass 37, count 0 2006.245.07:31:12.72#ibcon#read 5, iclass 37, count 0 2006.245.07:31:12.72#ibcon#about to read 6, iclass 37, count 0 2006.245.07:31:12.72#ibcon#read 6, iclass 37, count 0 2006.245.07:31:12.72#ibcon#end of sib2, iclass 37, count 0 2006.245.07:31:12.72#ibcon#*after write, iclass 37, count 0 2006.245.07:31:12.72#ibcon#*before return 0, iclass 37, count 0 2006.245.07:31:12.72#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:12.72#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:12.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:31:12.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:31:12.72$vc4f8/valo=5,652.99 2006.245.07:31:12.72#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:31:12.72#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:31:12.72#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:12.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:12.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:12.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:12.72#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:31:12.72#ibcon#first serial, iclass 39, count 0 2006.245.07:31:12.72#ibcon#enter sib2, iclass 39, count 0 2006.245.07:31:12.72#ibcon#flushed, iclass 39, count 0 2006.245.07:31:12.72#ibcon#about to write, iclass 39, count 0 2006.245.07:31:12.72#ibcon#wrote, iclass 39, count 0 2006.245.07:31:12.72#ibcon#about to read 3, iclass 39, count 0 2006.245.07:31:12.74#ibcon#read 3, iclass 39, count 0 2006.245.07:31:12.74#ibcon#about to read 4, iclass 39, count 0 2006.245.07:31:12.74#ibcon#read 4, iclass 39, count 0 2006.245.07:31:12.74#ibcon#about to read 5, iclass 39, count 0 2006.245.07:31:12.74#ibcon#read 5, iclass 39, count 0 2006.245.07:31:12.74#ibcon#about to read 6, iclass 39, count 0 2006.245.07:31:12.74#ibcon#read 6, iclass 39, count 0 2006.245.07:31:12.74#ibcon#end of sib2, iclass 39, count 0 2006.245.07:31:12.74#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:31:12.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:31:12.74#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:31:12.74#ibcon#*before write, iclass 39, count 0 2006.245.07:31:12.74#ibcon#enter sib2, iclass 39, count 0 2006.245.07:31:12.74#ibcon#flushed, iclass 39, count 0 2006.245.07:31:12.74#ibcon#about to write, iclass 39, count 0 2006.245.07:31:12.74#ibcon#wrote, iclass 39, count 0 2006.245.07:31:12.74#ibcon#about to read 3, iclass 39, count 0 2006.245.07:31:12.78#ibcon#read 3, iclass 39, count 0 2006.245.07:31:12.78#ibcon#about to read 4, iclass 39, count 0 2006.245.07:31:12.78#ibcon#read 4, iclass 39, count 0 2006.245.07:31:12.78#ibcon#about to read 5, iclass 39, count 0 2006.245.07:31:12.78#ibcon#read 5, iclass 39, count 0 2006.245.07:31:12.78#ibcon#about to read 6, iclass 39, count 0 2006.245.07:31:12.78#ibcon#read 6, iclass 39, count 0 2006.245.07:31:12.78#ibcon#end of sib2, iclass 39, count 0 2006.245.07:31:12.78#ibcon#*after write, iclass 39, count 0 2006.245.07:31:12.78#ibcon#*before return 0, iclass 39, count 0 2006.245.07:31:12.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:12.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:12.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:31:12.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:31:12.78$vc4f8/va=5,7 2006.245.07:31:12.78#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:31:12.78#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:31:12.78#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:12.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:12.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:12.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:12.84#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:31:12.84#ibcon#first serial, iclass 3, count 2 2006.245.07:31:12.84#ibcon#enter sib2, iclass 3, count 2 2006.245.07:31:12.84#ibcon#flushed, iclass 3, count 2 2006.245.07:31:12.84#ibcon#about to write, iclass 3, count 2 2006.245.07:31:12.84#ibcon#wrote, iclass 3, count 2 2006.245.07:31:12.84#ibcon#about to read 3, iclass 3, count 2 2006.245.07:31:12.86#ibcon#read 3, iclass 3, count 2 2006.245.07:31:12.86#ibcon#about to read 4, iclass 3, count 2 2006.245.07:31:12.86#ibcon#read 4, iclass 3, count 2 2006.245.07:31:12.86#ibcon#about to read 5, iclass 3, count 2 2006.245.07:31:12.86#ibcon#read 5, iclass 3, count 2 2006.245.07:31:12.86#ibcon#about to read 6, iclass 3, count 2 2006.245.07:31:12.86#ibcon#read 6, iclass 3, count 2 2006.245.07:31:12.86#ibcon#end of sib2, iclass 3, count 2 2006.245.07:31:12.86#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:31:12.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:31:12.86#ibcon#[25=AT05-07\r\n] 2006.245.07:31:12.86#ibcon#*before write, iclass 3, count 2 2006.245.07:31:12.86#ibcon#enter sib2, iclass 3, count 2 2006.245.07:31:12.86#ibcon#flushed, iclass 3, count 2 2006.245.07:31:12.86#ibcon#about to write, iclass 3, count 2 2006.245.07:31:12.86#ibcon#wrote, iclass 3, count 2 2006.245.07:31:12.86#ibcon#about to read 3, iclass 3, count 2 2006.245.07:31:12.89#ibcon#read 3, iclass 3, count 2 2006.245.07:31:12.89#ibcon#about to read 4, iclass 3, count 2 2006.245.07:31:12.89#ibcon#read 4, iclass 3, count 2 2006.245.07:31:12.89#ibcon#about to read 5, iclass 3, count 2 2006.245.07:31:12.89#ibcon#read 5, iclass 3, count 2 2006.245.07:31:12.89#ibcon#about to read 6, iclass 3, count 2 2006.245.07:31:12.89#ibcon#read 6, iclass 3, count 2 2006.245.07:31:12.89#ibcon#end of sib2, iclass 3, count 2 2006.245.07:31:12.89#ibcon#*after write, iclass 3, count 2 2006.245.07:31:12.89#ibcon#*before return 0, iclass 3, count 2 2006.245.07:31:12.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:12.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:12.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:31:12.89#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:12.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:13.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:13.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:13.01#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:31:13.01#ibcon#first serial, iclass 3, count 0 2006.245.07:31:13.01#ibcon#enter sib2, iclass 3, count 0 2006.245.07:31:13.01#ibcon#flushed, iclass 3, count 0 2006.245.07:31:13.01#ibcon#about to write, iclass 3, count 0 2006.245.07:31:13.01#ibcon#wrote, iclass 3, count 0 2006.245.07:31:13.01#ibcon#about to read 3, iclass 3, count 0 2006.245.07:31:13.03#ibcon#read 3, iclass 3, count 0 2006.245.07:31:13.03#ibcon#about to read 4, iclass 3, count 0 2006.245.07:31:13.03#ibcon#read 4, iclass 3, count 0 2006.245.07:31:13.03#ibcon#about to read 5, iclass 3, count 0 2006.245.07:31:13.03#ibcon#read 5, iclass 3, count 0 2006.245.07:31:13.03#ibcon#about to read 6, iclass 3, count 0 2006.245.07:31:13.03#ibcon#read 6, iclass 3, count 0 2006.245.07:31:13.03#ibcon#end of sib2, iclass 3, count 0 2006.245.07:31:13.03#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:31:13.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:31:13.03#ibcon#[25=USB\r\n] 2006.245.07:31:13.03#ibcon#*before write, iclass 3, count 0 2006.245.07:31:13.03#ibcon#enter sib2, iclass 3, count 0 2006.245.07:31:13.03#ibcon#flushed, iclass 3, count 0 2006.245.07:31:13.03#ibcon#about to write, iclass 3, count 0 2006.245.07:31:13.03#ibcon#wrote, iclass 3, count 0 2006.245.07:31:13.03#ibcon#about to read 3, iclass 3, count 0 2006.245.07:31:13.06#ibcon#read 3, iclass 3, count 0 2006.245.07:31:13.06#ibcon#about to read 4, iclass 3, count 0 2006.245.07:31:13.06#ibcon#read 4, iclass 3, count 0 2006.245.07:31:13.06#ibcon#about to read 5, iclass 3, count 0 2006.245.07:31:13.06#ibcon#read 5, iclass 3, count 0 2006.245.07:31:13.06#ibcon#about to read 6, iclass 3, count 0 2006.245.07:31:13.06#ibcon#read 6, iclass 3, count 0 2006.245.07:31:13.06#ibcon#end of sib2, iclass 3, count 0 2006.245.07:31:13.06#ibcon#*after write, iclass 3, count 0 2006.245.07:31:13.06#ibcon#*before return 0, iclass 3, count 0 2006.245.07:31:13.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:13.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:13.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:31:13.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:31:13.06$vc4f8/valo=6,772.99 2006.245.07:31:13.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:31:13.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:31:13.06#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:13.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:13.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:13.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:13.06#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:31:13.06#ibcon#first serial, iclass 5, count 0 2006.245.07:31:13.06#ibcon#enter sib2, iclass 5, count 0 2006.245.07:31:13.06#ibcon#flushed, iclass 5, count 0 2006.245.07:31:13.06#ibcon#about to write, iclass 5, count 0 2006.245.07:31:13.06#ibcon#wrote, iclass 5, count 0 2006.245.07:31:13.06#ibcon#about to read 3, iclass 5, count 0 2006.245.07:31:13.09#ibcon#read 3, iclass 5, count 0 2006.245.07:31:13.09#ibcon#about to read 4, iclass 5, count 0 2006.245.07:31:13.09#ibcon#read 4, iclass 5, count 0 2006.245.07:31:13.09#ibcon#about to read 5, iclass 5, count 0 2006.245.07:31:13.09#ibcon#read 5, iclass 5, count 0 2006.245.07:31:13.09#ibcon#about to read 6, iclass 5, count 0 2006.245.07:31:13.09#ibcon#read 6, iclass 5, count 0 2006.245.07:31:13.09#ibcon#end of sib2, iclass 5, count 0 2006.245.07:31:13.09#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:31:13.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:31:13.09#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:31:13.09#ibcon#*before write, iclass 5, count 0 2006.245.07:31:13.09#ibcon#enter sib2, iclass 5, count 0 2006.245.07:31:13.09#ibcon#flushed, iclass 5, count 0 2006.245.07:31:13.09#ibcon#about to write, iclass 5, count 0 2006.245.07:31:13.09#ibcon#wrote, iclass 5, count 0 2006.245.07:31:13.09#ibcon#about to read 3, iclass 5, count 0 2006.245.07:31:13.13#ibcon#read 3, iclass 5, count 0 2006.245.07:31:13.13#ibcon#about to read 4, iclass 5, count 0 2006.245.07:31:13.13#ibcon#read 4, iclass 5, count 0 2006.245.07:31:13.13#ibcon#about to read 5, iclass 5, count 0 2006.245.07:31:13.13#ibcon#read 5, iclass 5, count 0 2006.245.07:31:13.13#ibcon#about to read 6, iclass 5, count 0 2006.245.07:31:13.13#ibcon#read 6, iclass 5, count 0 2006.245.07:31:13.13#ibcon#end of sib2, iclass 5, count 0 2006.245.07:31:13.13#ibcon#*after write, iclass 5, count 0 2006.245.07:31:13.13#ibcon#*before return 0, iclass 5, count 0 2006.245.07:31:13.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:13.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:13.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:31:13.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:31:13.13$vc4f8/va=6,7 2006.245.07:31:13.13#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:31:13.13#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:31:13.13#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:13.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:31:13.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:31:13.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:31:13.18#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:31:13.18#ibcon#first serial, iclass 7, count 2 2006.245.07:31:13.18#ibcon#enter sib2, iclass 7, count 2 2006.245.07:31:13.18#ibcon#flushed, iclass 7, count 2 2006.245.07:31:13.18#ibcon#about to write, iclass 7, count 2 2006.245.07:31:13.18#ibcon#wrote, iclass 7, count 2 2006.245.07:31:13.18#ibcon#about to read 3, iclass 7, count 2 2006.245.07:31:13.20#ibcon#read 3, iclass 7, count 2 2006.245.07:31:13.20#ibcon#about to read 4, iclass 7, count 2 2006.245.07:31:13.20#ibcon#read 4, iclass 7, count 2 2006.245.07:31:13.20#ibcon#about to read 5, iclass 7, count 2 2006.245.07:31:13.20#ibcon#read 5, iclass 7, count 2 2006.245.07:31:13.20#ibcon#about to read 6, iclass 7, count 2 2006.245.07:31:13.20#ibcon#read 6, iclass 7, count 2 2006.245.07:31:13.20#ibcon#end of sib2, iclass 7, count 2 2006.245.07:31:13.20#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:31:13.20#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:31:13.20#ibcon#[25=AT06-07\r\n] 2006.245.07:31:13.20#ibcon#*before write, iclass 7, count 2 2006.245.07:31:13.20#ibcon#enter sib2, iclass 7, count 2 2006.245.07:31:13.20#ibcon#flushed, iclass 7, count 2 2006.245.07:31:13.20#ibcon#about to write, iclass 7, count 2 2006.245.07:31:13.20#ibcon#wrote, iclass 7, count 2 2006.245.07:31:13.20#ibcon#about to read 3, iclass 7, count 2 2006.245.07:31:13.23#ibcon#read 3, iclass 7, count 2 2006.245.07:31:13.23#ibcon#about to read 4, iclass 7, count 2 2006.245.07:31:13.23#ibcon#read 4, iclass 7, count 2 2006.245.07:31:13.23#ibcon#about to read 5, iclass 7, count 2 2006.245.07:31:13.23#ibcon#read 5, iclass 7, count 2 2006.245.07:31:13.23#ibcon#about to read 6, iclass 7, count 2 2006.245.07:31:13.23#ibcon#read 6, iclass 7, count 2 2006.245.07:31:13.23#ibcon#end of sib2, iclass 7, count 2 2006.245.07:31:13.23#ibcon#*after write, iclass 7, count 2 2006.245.07:31:13.23#ibcon#*before return 0, iclass 7, count 2 2006.245.07:31:13.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:31:13.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:31:13.23#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:31:13.23#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:13.23#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:31:13.35#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:31:13.35#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:31:13.35#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:31:13.35#ibcon#first serial, iclass 7, count 0 2006.245.07:31:13.35#ibcon#enter sib2, iclass 7, count 0 2006.245.07:31:13.35#ibcon#flushed, iclass 7, count 0 2006.245.07:31:13.35#ibcon#about to write, iclass 7, count 0 2006.245.07:31:13.35#ibcon#wrote, iclass 7, count 0 2006.245.07:31:13.35#ibcon#about to read 3, iclass 7, count 0 2006.245.07:31:13.37#ibcon#read 3, iclass 7, count 0 2006.245.07:31:13.37#ibcon#about to read 4, iclass 7, count 0 2006.245.07:31:13.37#ibcon#read 4, iclass 7, count 0 2006.245.07:31:13.37#ibcon#about to read 5, iclass 7, count 0 2006.245.07:31:13.37#ibcon#read 5, iclass 7, count 0 2006.245.07:31:13.37#ibcon#about to read 6, iclass 7, count 0 2006.245.07:31:13.37#ibcon#read 6, iclass 7, count 0 2006.245.07:31:13.37#ibcon#end of sib2, iclass 7, count 0 2006.245.07:31:13.37#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:31:13.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:31:13.37#ibcon#[25=USB\r\n] 2006.245.07:31:13.37#ibcon#*before write, iclass 7, count 0 2006.245.07:31:13.37#ibcon#enter sib2, iclass 7, count 0 2006.245.07:31:13.37#ibcon#flushed, iclass 7, count 0 2006.245.07:31:13.37#ibcon#about to write, iclass 7, count 0 2006.245.07:31:13.37#ibcon#wrote, iclass 7, count 0 2006.245.07:31:13.37#ibcon#about to read 3, iclass 7, count 0 2006.245.07:31:13.40#ibcon#read 3, iclass 7, count 0 2006.245.07:31:13.40#ibcon#about to read 4, iclass 7, count 0 2006.245.07:31:13.40#ibcon#read 4, iclass 7, count 0 2006.245.07:31:13.40#ibcon#about to read 5, iclass 7, count 0 2006.245.07:31:13.40#ibcon#read 5, iclass 7, count 0 2006.245.07:31:13.40#ibcon#about to read 6, iclass 7, count 0 2006.245.07:31:13.40#ibcon#read 6, iclass 7, count 0 2006.245.07:31:13.40#ibcon#end of sib2, iclass 7, count 0 2006.245.07:31:13.40#ibcon#*after write, iclass 7, count 0 2006.245.07:31:13.40#ibcon#*before return 0, iclass 7, count 0 2006.245.07:31:13.40#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:31:13.40#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:31:13.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:31:13.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:31:13.40$vc4f8/valo=7,832.99 2006.245.07:31:13.40#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:31:13.40#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:31:13.40#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:13.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:31:13.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:31:13.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:31:13.40#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:31:13.40#ibcon#first serial, iclass 11, count 0 2006.245.07:31:13.40#ibcon#enter sib2, iclass 11, count 0 2006.245.07:31:13.40#ibcon#flushed, iclass 11, count 0 2006.245.07:31:13.40#ibcon#about to write, iclass 11, count 0 2006.245.07:31:13.40#ibcon#wrote, iclass 11, count 0 2006.245.07:31:13.40#ibcon#about to read 3, iclass 11, count 0 2006.245.07:31:13.42#ibcon#read 3, iclass 11, count 0 2006.245.07:31:13.42#ibcon#about to read 4, iclass 11, count 0 2006.245.07:31:13.42#ibcon#read 4, iclass 11, count 0 2006.245.07:31:13.42#ibcon#about to read 5, iclass 11, count 0 2006.245.07:31:13.42#ibcon#read 5, iclass 11, count 0 2006.245.07:31:13.42#ibcon#about to read 6, iclass 11, count 0 2006.245.07:31:13.42#ibcon#read 6, iclass 11, count 0 2006.245.07:31:13.42#ibcon#end of sib2, iclass 11, count 0 2006.245.07:31:13.42#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:31:13.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:31:13.42#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:31:13.42#ibcon#*before write, iclass 11, count 0 2006.245.07:31:13.42#ibcon#enter sib2, iclass 11, count 0 2006.245.07:31:13.42#ibcon#flushed, iclass 11, count 0 2006.245.07:31:13.42#ibcon#about to write, iclass 11, count 0 2006.245.07:31:13.42#ibcon#wrote, iclass 11, count 0 2006.245.07:31:13.42#ibcon#about to read 3, iclass 11, count 0 2006.245.07:31:13.46#ibcon#read 3, iclass 11, count 0 2006.245.07:31:13.46#ibcon#about to read 4, iclass 11, count 0 2006.245.07:31:13.46#ibcon#read 4, iclass 11, count 0 2006.245.07:31:13.46#ibcon#about to read 5, iclass 11, count 0 2006.245.07:31:13.46#ibcon#read 5, iclass 11, count 0 2006.245.07:31:13.46#ibcon#about to read 6, iclass 11, count 0 2006.245.07:31:13.46#ibcon#read 6, iclass 11, count 0 2006.245.07:31:13.46#ibcon#end of sib2, iclass 11, count 0 2006.245.07:31:13.46#ibcon#*after write, iclass 11, count 0 2006.245.07:31:13.46#ibcon#*before return 0, iclass 11, count 0 2006.245.07:31:13.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:31:13.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:31:13.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:31:13.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:31:13.46$vc4f8/va=7,7 2006.245.07:31:13.46#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.07:31:13.46#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.07:31:13.46#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:13.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:31:13.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:31:13.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:31:13.52#ibcon#enter wrdev, iclass 13, count 2 2006.245.07:31:13.52#ibcon#first serial, iclass 13, count 2 2006.245.07:31:13.52#ibcon#enter sib2, iclass 13, count 2 2006.245.07:31:13.52#ibcon#flushed, iclass 13, count 2 2006.245.07:31:13.52#ibcon#about to write, iclass 13, count 2 2006.245.07:31:13.52#ibcon#wrote, iclass 13, count 2 2006.245.07:31:13.52#ibcon#about to read 3, iclass 13, count 2 2006.245.07:31:13.54#ibcon#read 3, iclass 13, count 2 2006.245.07:31:13.54#ibcon#about to read 4, iclass 13, count 2 2006.245.07:31:13.54#ibcon#read 4, iclass 13, count 2 2006.245.07:31:13.54#ibcon#about to read 5, iclass 13, count 2 2006.245.07:31:13.54#ibcon#read 5, iclass 13, count 2 2006.245.07:31:13.54#ibcon#about to read 6, iclass 13, count 2 2006.245.07:31:13.54#ibcon#read 6, iclass 13, count 2 2006.245.07:31:13.54#ibcon#end of sib2, iclass 13, count 2 2006.245.07:31:13.54#ibcon#*mode == 0, iclass 13, count 2 2006.245.07:31:13.54#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.07:31:13.54#ibcon#[25=AT07-07\r\n] 2006.245.07:31:13.54#ibcon#*before write, iclass 13, count 2 2006.245.07:31:13.54#ibcon#enter sib2, iclass 13, count 2 2006.245.07:31:13.54#ibcon#flushed, iclass 13, count 2 2006.245.07:31:13.54#ibcon#about to write, iclass 13, count 2 2006.245.07:31:13.54#ibcon#wrote, iclass 13, count 2 2006.245.07:31:13.54#ibcon#about to read 3, iclass 13, count 2 2006.245.07:31:13.57#ibcon#read 3, iclass 13, count 2 2006.245.07:31:13.57#ibcon#about to read 4, iclass 13, count 2 2006.245.07:31:13.57#ibcon#read 4, iclass 13, count 2 2006.245.07:31:13.57#ibcon#about to read 5, iclass 13, count 2 2006.245.07:31:13.57#ibcon#read 5, iclass 13, count 2 2006.245.07:31:13.57#ibcon#about to read 6, iclass 13, count 2 2006.245.07:31:13.57#ibcon#read 6, iclass 13, count 2 2006.245.07:31:13.57#ibcon#end of sib2, iclass 13, count 2 2006.245.07:31:13.57#ibcon#*after write, iclass 13, count 2 2006.245.07:31:13.57#ibcon#*before return 0, iclass 13, count 2 2006.245.07:31:13.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:31:13.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:31:13.57#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.07:31:13.57#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:13.57#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:31:13.69#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:31:13.69#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:31:13.69#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:31:13.69#ibcon#first serial, iclass 13, count 0 2006.245.07:31:13.69#ibcon#enter sib2, iclass 13, count 0 2006.245.07:31:13.69#ibcon#flushed, iclass 13, count 0 2006.245.07:31:13.69#ibcon#about to write, iclass 13, count 0 2006.245.07:31:13.69#ibcon#wrote, iclass 13, count 0 2006.245.07:31:13.69#ibcon#about to read 3, iclass 13, count 0 2006.245.07:31:13.71#ibcon#read 3, iclass 13, count 0 2006.245.07:31:13.71#ibcon#about to read 4, iclass 13, count 0 2006.245.07:31:13.71#ibcon#read 4, iclass 13, count 0 2006.245.07:31:13.71#ibcon#about to read 5, iclass 13, count 0 2006.245.07:31:13.71#ibcon#read 5, iclass 13, count 0 2006.245.07:31:13.71#ibcon#about to read 6, iclass 13, count 0 2006.245.07:31:13.71#ibcon#read 6, iclass 13, count 0 2006.245.07:31:13.71#ibcon#end of sib2, iclass 13, count 0 2006.245.07:31:13.71#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:31:13.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:31:13.71#ibcon#[25=USB\r\n] 2006.245.07:31:13.71#ibcon#*before write, iclass 13, count 0 2006.245.07:31:13.71#ibcon#enter sib2, iclass 13, count 0 2006.245.07:31:13.71#ibcon#flushed, iclass 13, count 0 2006.245.07:31:13.71#ibcon#about to write, iclass 13, count 0 2006.245.07:31:13.71#ibcon#wrote, iclass 13, count 0 2006.245.07:31:13.71#ibcon#about to read 3, iclass 13, count 0 2006.245.07:31:13.74#ibcon#read 3, iclass 13, count 0 2006.245.07:31:13.74#ibcon#about to read 4, iclass 13, count 0 2006.245.07:31:13.74#ibcon#read 4, iclass 13, count 0 2006.245.07:31:13.74#ibcon#about to read 5, iclass 13, count 0 2006.245.07:31:13.74#ibcon#read 5, iclass 13, count 0 2006.245.07:31:13.74#ibcon#about to read 6, iclass 13, count 0 2006.245.07:31:13.74#ibcon#read 6, iclass 13, count 0 2006.245.07:31:13.74#ibcon#end of sib2, iclass 13, count 0 2006.245.07:31:13.74#ibcon#*after write, iclass 13, count 0 2006.245.07:31:13.74#ibcon#*before return 0, iclass 13, count 0 2006.245.07:31:13.74#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:31:13.74#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:31:13.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:31:13.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:31:13.74$vc4f8/valo=8,852.99 2006.245.07:31:13.74#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.07:31:13.74#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.07:31:13.74#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:13.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:31:13.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:31:13.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:31:13.74#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:31:13.74#ibcon#first serial, iclass 15, count 0 2006.245.07:31:13.74#ibcon#enter sib2, iclass 15, count 0 2006.245.07:31:13.74#ibcon#flushed, iclass 15, count 0 2006.245.07:31:13.74#ibcon#about to write, iclass 15, count 0 2006.245.07:31:13.74#ibcon#wrote, iclass 15, count 0 2006.245.07:31:13.74#ibcon#about to read 3, iclass 15, count 0 2006.245.07:31:13.76#ibcon#read 3, iclass 15, count 0 2006.245.07:31:13.76#ibcon#about to read 4, iclass 15, count 0 2006.245.07:31:13.76#ibcon#read 4, iclass 15, count 0 2006.245.07:31:13.76#ibcon#about to read 5, iclass 15, count 0 2006.245.07:31:13.76#ibcon#read 5, iclass 15, count 0 2006.245.07:31:13.76#ibcon#about to read 6, iclass 15, count 0 2006.245.07:31:13.76#ibcon#read 6, iclass 15, count 0 2006.245.07:31:13.76#ibcon#end of sib2, iclass 15, count 0 2006.245.07:31:13.76#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:31:13.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:31:13.76#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:31:13.76#ibcon#*before write, iclass 15, count 0 2006.245.07:31:13.76#ibcon#enter sib2, iclass 15, count 0 2006.245.07:31:13.76#ibcon#flushed, iclass 15, count 0 2006.245.07:31:13.76#ibcon#about to write, iclass 15, count 0 2006.245.07:31:13.76#ibcon#wrote, iclass 15, count 0 2006.245.07:31:13.76#ibcon#about to read 3, iclass 15, count 0 2006.245.07:31:13.80#ibcon#read 3, iclass 15, count 0 2006.245.07:31:13.80#ibcon#about to read 4, iclass 15, count 0 2006.245.07:31:13.80#ibcon#read 4, iclass 15, count 0 2006.245.07:31:13.80#ibcon#about to read 5, iclass 15, count 0 2006.245.07:31:13.80#ibcon#read 5, iclass 15, count 0 2006.245.07:31:13.80#ibcon#about to read 6, iclass 15, count 0 2006.245.07:31:13.80#ibcon#read 6, iclass 15, count 0 2006.245.07:31:13.80#ibcon#end of sib2, iclass 15, count 0 2006.245.07:31:13.80#ibcon#*after write, iclass 15, count 0 2006.245.07:31:13.80#ibcon#*before return 0, iclass 15, count 0 2006.245.07:31:13.80#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:31:13.80#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:31:13.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:31:13.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:31:13.80$vc4f8/va=8,8 2006.245.07:31:13.80#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.07:31:13.80#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.07:31:13.80#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:13.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:31:13.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:31:13.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:31:13.87#ibcon#enter wrdev, iclass 17, count 2 2006.245.07:31:13.87#ibcon#first serial, iclass 17, count 2 2006.245.07:31:13.87#ibcon#enter sib2, iclass 17, count 2 2006.245.07:31:13.87#ibcon#flushed, iclass 17, count 2 2006.245.07:31:13.87#ibcon#about to write, iclass 17, count 2 2006.245.07:31:13.87#ibcon#wrote, iclass 17, count 2 2006.245.07:31:13.87#ibcon#about to read 3, iclass 17, count 2 2006.245.07:31:13.88#ibcon#read 3, iclass 17, count 2 2006.245.07:31:13.88#ibcon#about to read 4, iclass 17, count 2 2006.245.07:31:13.88#ibcon#read 4, iclass 17, count 2 2006.245.07:31:13.88#ibcon#about to read 5, iclass 17, count 2 2006.245.07:31:13.88#ibcon#read 5, iclass 17, count 2 2006.245.07:31:13.88#ibcon#about to read 6, iclass 17, count 2 2006.245.07:31:13.88#ibcon#read 6, iclass 17, count 2 2006.245.07:31:13.88#ibcon#end of sib2, iclass 17, count 2 2006.245.07:31:13.88#ibcon#*mode == 0, iclass 17, count 2 2006.245.07:31:13.88#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.07:31:13.88#ibcon#[25=AT08-08\r\n] 2006.245.07:31:13.88#ibcon#*before write, iclass 17, count 2 2006.245.07:31:13.88#ibcon#enter sib2, iclass 17, count 2 2006.245.07:31:13.88#ibcon#flushed, iclass 17, count 2 2006.245.07:31:13.88#ibcon#about to write, iclass 17, count 2 2006.245.07:31:13.88#ibcon#wrote, iclass 17, count 2 2006.245.07:31:13.88#ibcon#about to read 3, iclass 17, count 2 2006.245.07:31:13.91#ibcon#read 3, iclass 17, count 2 2006.245.07:31:13.91#ibcon#about to read 4, iclass 17, count 2 2006.245.07:31:13.91#ibcon#read 4, iclass 17, count 2 2006.245.07:31:13.91#ibcon#about to read 5, iclass 17, count 2 2006.245.07:31:13.91#ibcon#read 5, iclass 17, count 2 2006.245.07:31:13.91#ibcon#about to read 6, iclass 17, count 2 2006.245.07:31:13.91#ibcon#read 6, iclass 17, count 2 2006.245.07:31:13.91#ibcon#end of sib2, iclass 17, count 2 2006.245.07:31:13.91#ibcon#*after write, iclass 17, count 2 2006.245.07:31:13.91#ibcon#*before return 0, iclass 17, count 2 2006.245.07:31:13.91#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:31:13.91#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:31:13.91#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.07:31:13.91#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:13.91#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:31:14.03#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:31:14.03#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:31:14.03#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:31:14.03#ibcon#first serial, iclass 17, count 0 2006.245.07:31:14.03#ibcon#enter sib2, iclass 17, count 0 2006.245.07:31:14.03#ibcon#flushed, iclass 17, count 0 2006.245.07:31:14.03#ibcon#about to write, iclass 17, count 0 2006.245.07:31:14.03#ibcon#wrote, iclass 17, count 0 2006.245.07:31:14.03#ibcon#about to read 3, iclass 17, count 0 2006.245.07:31:14.05#ibcon#read 3, iclass 17, count 0 2006.245.07:31:14.05#ibcon#about to read 4, iclass 17, count 0 2006.245.07:31:14.05#ibcon#read 4, iclass 17, count 0 2006.245.07:31:14.05#ibcon#about to read 5, iclass 17, count 0 2006.245.07:31:14.05#ibcon#read 5, iclass 17, count 0 2006.245.07:31:14.05#ibcon#about to read 6, iclass 17, count 0 2006.245.07:31:14.05#ibcon#read 6, iclass 17, count 0 2006.245.07:31:14.05#ibcon#end of sib2, iclass 17, count 0 2006.245.07:31:14.05#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:31:14.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:31:14.05#ibcon#[25=USB\r\n] 2006.245.07:31:14.05#ibcon#*before write, iclass 17, count 0 2006.245.07:31:14.05#ibcon#enter sib2, iclass 17, count 0 2006.245.07:31:14.05#ibcon#flushed, iclass 17, count 0 2006.245.07:31:14.05#ibcon#about to write, iclass 17, count 0 2006.245.07:31:14.05#ibcon#wrote, iclass 17, count 0 2006.245.07:31:14.05#ibcon#about to read 3, iclass 17, count 0 2006.245.07:31:14.08#ibcon#read 3, iclass 17, count 0 2006.245.07:31:14.08#ibcon#about to read 4, iclass 17, count 0 2006.245.07:31:14.08#ibcon#read 4, iclass 17, count 0 2006.245.07:31:14.08#ibcon#about to read 5, iclass 17, count 0 2006.245.07:31:14.08#ibcon#read 5, iclass 17, count 0 2006.245.07:31:14.08#ibcon#about to read 6, iclass 17, count 0 2006.245.07:31:14.08#ibcon#read 6, iclass 17, count 0 2006.245.07:31:14.08#ibcon#end of sib2, iclass 17, count 0 2006.245.07:31:14.08#ibcon#*after write, iclass 17, count 0 2006.245.07:31:14.08#ibcon#*before return 0, iclass 17, count 0 2006.245.07:31:14.08#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:31:14.08#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:31:14.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:31:14.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:31:14.08$vc4f8/vblo=1,632.99 2006.245.07:31:14.08#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.07:31:14.08#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.07:31:14.08#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:14.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:31:14.08#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:31:14.08#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:31:14.08#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:31:14.08#ibcon#first serial, iclass 19, count 0 2006.245.07:31:14.08#ibcon#enter sib2, iclass 19, count 0 2006.245.07:31:14.08#ibcon#flushed, iclass 19, count 0 2006.245.07:31:14.08#ibcon#about to write, iclass 19, count 0 2006.245.07:31:14.08#ibcon#wrote, iclass 19, count 0 2006.245.07:31:14.08#ibcon#about to read 3, iclass 19, count 0 2006.245.07:31:14.10#ibcon#read 3, iclass 19, count 0 2006.245.07:31:14.10#ibcon#about to read 4, iclass 19, count 0 2006.245.07:31:14.10#ibcon#read 4, iclass 19, count 0 2006.245.07:31:14.10#ibcon#about to read 5, iclass 19, count 0 2006.245.07:31:14.10#ibcon#read 5, iclass 19, count 0 2006.245.07:31:14.10#ibcon#about to read 6, iclass 19, count 0 2006.245.07:31:14.10#ibcon#read 6, iclass 19, count 0 2006.245.07:31:14.10#ibcon#end of sib2, iclass 19, count 0 2006.245.07:31:14.10#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:31:14.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:31:14.10#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:31:14.10#ibcon#*before write, iclass 19, count 0 2006.245.07:31:14.10#ibcon#enter sib2, iclass 19, count 0 2006.245.07:31:14.10#ibcon#flushed, iclass 19, count 0 2006.245.07:31:14.10#ibcon#about to write, iclass 19, count 0 2006.245.07:31:14.10#ibcon#wrote, iclass 19, count 0 2006.245.07:31:14.10#ibcon#about to read 3, iclass 19, count 0 2006.245.07:31:14.14#ibcon#read 3, iclass 19, count 0 2006.245.07:31:14.14#ibcon#about to read 4, iclass 19, count 0 2006.245.07:31:14.14#ibcon#read 4, iclass 19, count 0 2006.245.07:31:14.14#ibcon#about to read 5, iclass 19, count 0 2006.245.07:31:14.14#ibcon#read 5, iclass 19, count 0 2006.245.07:31:14.14#ibcon#about to read 6, iclass 19, count 0 2006.245.07:31:14.14#ibcon#read 6, iclass 19, count 0 2006.245.07:31:14.14#ibcon#end of sib2, iclass 19, count 0 2006.245.07:31:14.14#ibcon#*after write, iclass 19, count 0 2006.245.07:31:14.14#ibcon#*before return 0, iclass 19, count 0 2006.245.07:31:14.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:31:14.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:31:14.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:31:14.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:31:14.14$vc4f8/vb=1,4 2006.245.07:31:14.14#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.07:31:14.14#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.07:31:14.14#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:14.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:31:14.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:31:14.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:31:14.14#ibcon#enter wrdev, iclass 21, count 2 2006.245.07:31:14.14#ibcon#first serial, iclass 21, count 2 2006.245.07:31:14.14#ibcon#enter sib2, iclass 21, count 2 2006.245.07:31:14.14#ibcon#flushed, iclass 21, count 2 2006.245.07:31:14.14#ibcon#about to write, iclass 21, count 2 2006.245.07:31:14.14#ibcon#wrote, iclass 21, count 2 2006.245.07:31:14.14#ibcon#about to read 3, iclass 21, count 2 2006.245.07:31:14.16#ibcon#read 3, iclass 21, count 2 2006.245.07:31:14.16#ibcon#about to read 4, iclass 21, count 2 2006.245.07:31:14.16#ibcon#read 4, iclass 21, count 2 2006.245.07:31:14.16#ibcon#about to read 5, iclass 21, count 2 2006.245.07:31:14.16#ibcon#read 5, iclass 21, count 2 2006.245.07:31:14.16#ibcon#about to read 6, iclass 21, count 2 2006.245.07:31:14.16#ibcon#read 6, iclass 21, count 2 2006.245.07:31:14.16#ibcon#end of sib2, iclass 21, count 2 2006.245.07:31:14.16#ibcon#*mode == 0, iclass 21, count 2 2006.245.07:31:14.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.07:31:14.16#ibcon#[27=AT01-04\r\n] 2006.245.07:31:14.16#ibcon#*before write, iclass 21, count 2 2006.245.07:31:14.16#ibcon#enter sib2, iclass 21, count 2 2006.245.07:31:14.16#ibcon#flushed, iclass 21, count 2 2006.245.07:31:14.16#ibcon#about to write, iclass 21, count 2 2006.245.07:31:14.16#ibcon#wrote, iclass 21, count 2 2006.245.07:31:14.16#ibcon#about to read 3, iclass 21, count 2 2006.245.07:31:14.19#ibcon#read 3, iclass 21, count 2 2006.245.07:31:14.19#ibcon#about to read 4, iclass 21, count 2 2006.245.07:31:14.19#ibcon#read 4, iclass 21, count 2 2006.245.07:31:14.19#ibcon#about to read 5, iclass 21, count 2 2006.245.07:31:14.19#ibcon#read 5, iclass 21, count 2 2006.245.07:31:14.19#ibcon#about to read 6, iclass 21, count 2 2006.245.07:31:14.19#ibcon#read 6, iclass 21, count 2 2006.245.07:31:14.19#ibcon#end of sib2, iclass 21, count 2 2006.245.07:31:14.19#ibcon#*after write, iclass 21, count 2 2006.245.07:31:14.19#ibcon#*before return 0, iclass 21, count 2 2006.245.07:31:14.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:31:14.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:31:14.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.07:31:14.19#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:14.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:31:14.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:31:14.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:31:14.31#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:31:14.31#ibcon#first serial, iclass 21, count 0 2006.245.07:31:14.31#ibcon#enter sib2, iclass 21, count 0 2006.245.07:31:14.31#ibcon#flushed, iclass 21, count 0 2006.245.07:31:14.31#ibcon#about to write, iclass 21, count 0 2006.245.07:31:14.31#ibcon#wrote, iclass 21, count 0 2006.245.07:31:14.31#ibcon#about to read 3, iclass 21, count 0 2006.245.07:31:14.33#ibcon#read 3, iclass 21, count 0 2006.245.07:31:14.33#ibcon#about to read 4, iclass 21, count 0 2006.245.07:31:14.33#ibcon#read 4, iclass 21, count 0 2006.245.07:31:14.33#ibcon#about to read 5, iclass 21, count 0 2006.245.07:31:14.33#ibcon#read 5, iclass 21, count 0 2006.245.07:31:14.33#ibcon#about to read 6, iclass 21, count 0 2006.245.07:31:14.33#ibcon#read 6, iclass 21, count 0 2006.245.07:31:14.33#ibcon#end of sib2, iclass 21, count 0 2006.245.07:31:14.33#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:31:14.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:31:14.33#ibcon#[27=USB\r\n] 2006.245.07:31:14.33#ibcon#*before write, iclass 21, count 0 2006.245.07:31:14.33#ibcon#enter sib2, iclass 21, count 0 2006.245.07:31:14.33#ibcon#flushed, iclass 21, count 0 2006.245.07:31:14.33#ibcon#about to write, iclass 21, count 0 2006.245.07:31:14.33#ibcon#wrote, iclass 21, count 0 2006.245.07:31:14.33#ibcon#about to read 3, iclass 21, count 0 2006.245.07:31:14.36#ibcon#read 3, iclass 21, count 0 2006.245.07:31:14.36#ibcon#about to read 4, iclass 21, count 0 2006.245.07:31:14.36#ibcon#read 4, iclass 21, count 0 2006.245.07:31:14.36#ibcon#about to read 5, iclass 21, count 0 2006.245.07:31:14.36#ibcon#read 5, iclass 21, count 0 2006.245.07:31:14.36#ibcon#about to read 6, iclass 21, count 0 2006.245.07:31:14.36#ibcon#read 6, iclass 21, count 0 2006.245.07:31:14.36#ibcon#end of sib2, iclass 21, count 0 2006.245.07:31:14.36#ibcon#*after write, iclass 21, count 0 2006.245.07:31:14.36#ibcon#*before return 0, iclass 21, count 0 2006.245.07:31:14.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:31:14.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:31:14.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:31:14.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:31:14.36$vc4f8/vblo=2,640.99 2006.245.07:31:14.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.07:31:14.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.07:31:14.36#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:14.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:14.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:14.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:14.36#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:31:14.36#ibcon#first serial, iclass 23, count 0 2006.245.07:31:14.36#ibcon#enter sib2, iclass 23, count 0 2006.245.07:31:14.36#ibcon#flushed, iclass 23, count 0 2006.245.07:31:14.36#ibcon#about to write, iclass 23, count 0 2006.245.07:31:14.36#ibcon#wrote, iclass 23, count 0 2006.245.07:31:14.36#ibcon#about to read 3, iclass 23, count 0 2006.245.07:31:14.38#ibcon#read 3, iclass 23, count 0 2006.245.07:31:14.38#ibcon#about to read 4, iclass 23, count 0 2006.245.07:31:14.38#ibcon#read 4, iclass 23, count 0 2006.245.07:31:14.38#ibcon#about to read 5, iclass 23, count 0 2006.245.07:31:14.38#ibcon#read 5, iclass 23, count 0 2006.245.07:31:14.38#ibcon#about to read 6, iclass 23, count 0 2006.245.07:31:14.38#ibcon#read 6, iclass 23, count 0 2006.245.07:31:14.38#ibcon#end of sib2, iclass 23, count 0 2006.245.07:31:14.38#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:31:14.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:31:14.38#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:31:14.38#ibcon#*before write, iclass 23, count 0 2006.245.07:31:14.38#ibcon#enter sib2, iclass 23, count 0 2006.245.07:31:14.38#ibcon#flushed, iclass 23, count 0 2006.245.07:31:14.38#ibcon#about to write, iclass 23, count 0 2006.245.07:31:14.38#ibcon#wrote, iclass 23, count 0 2006.245.07:31:14.38#ibcon#about to read 3, iclass 23, count 0 2006.245.07:31:14.42#ibcon#read 3, iclass 23, count 0 2006.245.07:31:14.42#ibcon#about to read 4, iclass 23, count 0 2006.245.07:31:14.42#ibcon#read 4, iclass 23, count 0 2006.245.07:31:14.42#ibcon#about to read 5, iclass 23, count 0 2006.245.07:31:14.42#ibcon#read 5, iclass 23, count 0 2006.245.07:31:14.42#ibcon#about to read 6, iclass 23, count 0 2006.245.07:31:14.42#ibcon#read 6, iclass 23, count 0 2006.245.07:31:14.42#ibcon#end of sib2, iclass 23, count 0 2006.245.07:31:14.42#ibcon#*after write, iclass 23, count 0 2006.245.07:31:14.42#ibcon#*before return 0, iclass 23, count 0 2006.245.07:31:14.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:14.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:31:14.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:31:14.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:31:14.42$vc4f8/vb=2,4 2006.245.07:31:14.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.07:31:14.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.07:31:14.42#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:14.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:14.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:14.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:14.48#ibcon#enter wrdev, iclass 25, count 2 2006.245.07:31:14.48#ibcon#first serial, iclass 25, count 2 2006.245.07:31:14.48#ibcon#enter sib2, iclass 25, count 2 2006.245.07:31:14.48#ibcon#flushed, iclass 25, count 2 2006.245.07:31:14.48#ibcon#about to write, iclass 25, count 2 2006.245.07:31:14.48#ibcon#wrote, iclass 25, count 2 2006.245.07:31:14.48#ibcon#about to read 3, iclass 25, count 2 2006.245.07:31:14.50#ibcon#read 3, iclass 25, count 2 2006.245.07:31:14.50#ibcon#about to read 4, iclass 25, count 2 2006.245.07:31:14.50#ibcon#read 4, iclass 25, count 2 2006.245.07:31:14.50#ibcon#about to read 5, iclass 25, count 2 2006.245.07:31:14.50#ibcon#read 5, iclass 25, count 2 2006.245.07:31:14.50#ibcon#about to read 6, iclass 25, count 2 2006.245.07:31:14.50#ibcon#read 6, iclass 25, count 2 2006.245.07:31:14.50#ibcon#end of sib2, iclass 25, count 2 2006.245.07:31:14.50#ibcon#*mode == 0, iclass 25, count 2 2006.245.07:31:14.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.07:31:14.50#ibcon#[27=AT02-04\r\n] 2006.245.07:31:14.50#ibcon#*before write, iclass 25, count 2 2006.245.07:31:14.50#ibcon#enter sib2, iclass 25, count 2 2006.245.07:31:14.50#ibcon#flushed, iclass 25, count 2 2006.245.07:31:14.50#ibcon#about to write, iclass 25, count 2 2006.245.07:31:14.50#ibcon#wrote, iclass 25, count 2 2006.245.07:31:14.50#ibcon#about to read 3, iclass 25, count 2 2006.245.07:31:14.53#ibcon#read 3, iclass 25, count 2 2006.245.07:31:14.53#ibcon#about to read 4, iclass 25, count 2 2006.245.07:31:14.53#ibcon#read 4, iclass 25, count 2 2006.245.07:31:14.53#ibcon#about to read 5, iclass 25, count 2 2006.245.07:31:14.53#ibcon#read 5, iclass 25, count 2 2006.245.07:31:14.53#ibcon#about to read 6, iclass 25, count 2 2006.245.07:31:14.53#ibcon#read 6, iclass 25, count 2 2006.245.07:31:14.53#ibcon#end of sib2, iclass 25, count 2 2006.245.07:31:14.53#ibcon#*after write, iclass 25, count 2 2006.245.07:31:14.53#ibcon#*before return 0, iclass 25, count 2 2006.245.07:31:14.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:14.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:31:14.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.07:31:14.53#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:14.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:14.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:14.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:14.65#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:31:14.65#ibcon#first serial, iclass 25, count 0 2006.245.07:31:14.65#ibcon#enter sib2, iclass 25, count 0 2006.245.07:31:14.65#ibcon#flushed, iclass 25, count 0 2006.245.07:31:14.65#ibcon#about to write, iclass 25, count 0 2006.245.07:31:14.65#ibcon#wrote, iclass 25, count 0 2006.245.07:31:14.65#ibcon#about to read 3, iclass 25, count 0 2006.245.07:31:14.67#ibcon#read 3, iclass 25, count 0 2006.245.07:31:14.67#ibcon#about to read 4, iclass 25, count 0 2006.245.07:31:14.67#ibcon#read 4, iclass 25, count 0 2006.245.07:31:14.67#ibcon#about to read 5, iclass 25, count 0 2006.245.07:31:14.67#ibcon#read 5, iclass 25, count 0 2006.245.07:31:14.67#ibcon#about to read 6, iclass 25, count 0 2006.245.07:31:14.67#ibcon#read 6, iclass 25, count 0 2006.245.07:31:14.67#ibcon#end of sib2, iclass 25, count 0 2006.245.07:31:14.67#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:31:14.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:31:14.67#ibcon#[27=USB\r\n] 2006.245.07:31:14.67#ibcon#*before write, iclass 25, count 0 2006.245.07:31:14.67#ibcon#enter sib2, iclass 25, count 0 2006.245.07:31:14.67#ibcon#flushed, iclass 25, count 0 2006.245.07:31:14.67#ibcon#about to write, iclass 25, count 0 2006.245.07:31:14.67#ibcon#wrote, iclass 25, count 0 2006.245.07:31:14.67#ibcon#about to read 3, iclass 25, count 0 2006.245.07:31:14.70#ibcon#read 3, iclass 25, count 0 2006.245.07:31:14.70#ibcon#about to read 4, iclass 25, count 0 2006.245.07:31:14.70#ibcon#read 4, iclass 25, count 0 2006.245.07:31:14.70#ibcon#about to read 5, iclass 25, count 0 2006.245.07:31:14.70#ibcon#read 5, iclass 25, count 0 2006.245.07:31:14.70#ibcon#about to read 6, iclass 25, count 0 2006.245.07:31:14.70#ibcon#read 6, iclass 25, count 0 2006.245.07:31:14.70#ibcon#end of sib2, iclass 25, count 0 2006.245.07:31:14.70#ibcon#*after write, iclass 25, count 0 2006.245.07:31:14.70#ibcon#*before return 0, iclass 25, count 0 2006.245.07:31:14.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:14.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:31:14.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:31:14.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:31:14.70$vc4f8/vblo=3,656.99 2006.245.07:31:14.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:31:14.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:31:14.70#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:14.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:14.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:14.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:14.70#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:31:14.70#ibcon#first serial, iclass 27, count 0 2006.245.07:31:14.70#ibcon#enter sib2, iclass 27, count 0 2006.245.07:31:14.70#ibcon#flushed, iclass 27, count 0 2006.245.07:31:14.70#ibcon#about to write, iclass 27, count 0 2006.245.07:31:14.70#ibcon#wrote, iclass 27, count 0 2006.245.07:31:14.70#ibcon#about to read 3, iclass 27, count 0 2006.245.07:31:14.72#ibcon#read 3, iclass 27, count 0 2006.245.07:31:14.72#ibcon#about to read 4, iclass 27, count 0 2006.245.07:31:14.72#ibcon#read 4, iclass 27, count 0 2006.245.07:31:14.72#ibcon#about to read 5, iclass 27, count 0 2006.245.07:31:14.72#ibcon#read 5, iclass 27, count 0 2006.245.07:31:14.72#ibcon#about to read 6, iclass 27, count 0 2006.245.07:31:14.72#ibcon#read 6, iclass 27, count 0 2006.245.07:31:14.72#ibcon#end of sib2, iclass 27, count 0 2006.245.07:31:14.72#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:31:14.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:31:14.72#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:31:14.72#ibcon#*before write, iclass 27, count 0 2006.245.07:31:14.72#ibcon#enter sib2, iclass 27, count 0 2006.245.07:31:14.72#ibcon#flushed, iclass 27, count 0 2006.245.07:31:14.72#ibcon#about to write, iclass 27, count 0 2006.245.07:31:14.72#ibcon#wrote, iclass 27, count 0 2006.245.07:31:14.72#ibcon#about to read 3, iclass 27, count 0 2006.245.07:31:14.76#ibcon#read 3, iclass 27, count 0 2006.245.07:31:14.76#ibcon#about to read 4, iclass 27, count 0 2006.245.07:31:14.76#ibcon#read 4, iclass 27, count 0 2006.245.07:31:14.76#ibcon#about to read 5, iclass 27, count 0 2006.245.07:31:14.76#ibcon#read 5, iclass 27, count 0 2006.245.07:31:14.76#ibcon#about to read 6, iclass 27, count 0 2006.245.07:31:14.76#ibcon#read 6, iclass 27, count 0 2006.245.07:31:14.76#ibcon#end of sib2, iclass 27, count 0 2006.245.07:31:14.76#ibcon#*after write, iclass 27, count 0 2006.245.07:31:14.76#ibcon#*before return 0, iclass 27, count 0 2006.245.07:31:14.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:14.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:31:14.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:31:14.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:31:14.76$vc4f8/vb=3,4 2006.245.07:31:14.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:31:14.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:31:14.76#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:14.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:14.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:14.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:14.83#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:31:14.83#ibcon#first serial, iclass 29, count 2 2006.245.07:31:14.83#ibcon#enter sib2, iclass 29, count 2 2006.245.07:31:14.83#ibcon#flushed, iclass 29, count 2 2006.245.07:31:14.83#ibcon#about to write, iclass 29, count 2 2006.245.07:31:14.83#ibcon#wrote, iclass 29, count 2 2006.245.07:31:14.83#ibcon#about to read 3, iclass 29, count 2 2006.245.07:31:14.84#ibcon#read 3, iclass 29, count 2 2006.245.07:31:14.84#ibcon#about to read 4, iclass 29, count 2 2006.245.07:31:14.84#ibcon#read 4, iclass 29, count 2 2006.245.07:31:14.84#ibcon#about to read 5, iclass 29, count 2 2006.245.07:31:14.84#ibcon#read 5, iclass 29, count 2 2006.245.07:31:14.84#ibcon#about to read 6, iclass 29, count 2 2006.245.07:31:14.84#ibcon#read 6, iclass 29, count 2 2006.245.07:31:14.84#ibcon#end of sib2, iclass 29, count 2 2006.245.07:31:14.84#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:31:14.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:31:14.84#ibcon#[27=AT03-04\r\n] 2006.245.07:31:14.84#ibcon#*before write, iclass 29, count 2 2006.245.07:31:14.84#ibcon#enter sib2, iclass 29, count 2 2006.245.07:31:14.84#ibcon#flushed, iclass 29, count 2 2006.245.07:31:14.84#ibcon#about to write, iclass 29, count 2 2006.245.07:31:14.84#ibcon#wrote, iclass 29, count 2 2006.245.07:31:14.84#ibcon#about to read 3, iclass 29, count 2 2006.245.07:31:14.87#ibcon#read 3, iclass 29, count 2 2006.245.07:31:14.87#ibcon#about to read 4, iclass 29, count 2 2006.245.07:31:14.87#ibcon#read 4, iclass 29, count 2 2006.245.07:31:14.87#ibcon#about to read 5, iclass 29, count 2 2006.245.07:31:14.87#ibcon#read 5, iclass 29, count 2 2006.245.07:31:14.87#ibcon#about to read 6, iclass 29, count 2 2006.245.07:31:14.87#ibcon#read 6, iclass 29, count 2 2006.245.07:31:14.87#ibcon#end of sib2, iclass 29, count 2 2006.245.07:31:14.87#ibcon#*after write, iclass 29, count 2 2006.245.07:31:14.87#ibcon#*before return 0, iclass 29, count 2 2006.245.07:31:14.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:14.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:31:14.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:31:14.87#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:14.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:14.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:14.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:14.99#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:31:14.99#ibcon#first serial, iclass 29, count 0 2006.245.07:31:14.99#ibcon#enter sib2, iclass 29, count 0 2006.245.07:31:14.99#ibcon#flushed, iclass 29, count 0 2006.245.07:31:14.99#ibcon#about to write, iclass 29, count 0 2006.245.07:31:14.99#ibcon#wrote, iclass 29, count 0 2006.245.07:31:14.99#ibcon#about to read 3, iclass 29, count 0 2006.245.07:31:15.01#ibcon#read 3, iclass 29, count 0 2006.245.07:31:15.01#ibcon#about to read 4, iclass 29, count 0 2006.245.07:31:15.01#ibcon#read 4, iclass 29, count 0 2006.245.07:31:15.01#ibcon#about to read 5, iclass 29, count 0 2006.245.07:31:15.01#ibcon#read 5, iclass 29, count 0 2006.245.07:31:15.01#ibcon#about to read 6, iclass 29, count 0 2006.245.07:31:15.01#ibcon#read 6, iclass 29, count 0 2006.245.07:31:15.01#ibcon#end of sib2, iclass 29, count 0 2006.245.07:31:15.01#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:31:15.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:31:15.01#ibcon#[27=USB\r\n] 2006.245.07:31:15.01#ibcon#*before write, iclass 29, count 0 2006.245.07:31:15.01#ibcon#enter sib2, iclass 29, count 0 2006.245.07:31:15.01#ibcon#flushed, iclass 29, count 0 2006.245.07:31:15.01#ibcon#about to write, iclass 29, count 0 2006.245.07:31:15.01#ibcon#wrote, iclass 29, count 0 2006.245.07:31:15.01#ibcon#about to read 3, iclass 29, count 0 2006.245.07:31:15.04#ibcon#read 3, iclass 29, count 0 2006.245.07:31:15.04#ibcon#about to read 4, iclass 29, count 0 2006.245.07:31:15.04#ibcon#read 4, iclass 29, count 0 2006.245.07:31:15.04#ibcon#about to read 5, iclass 29, count 0 2006.245.07:31:15.04#ibcon#read 5, iclass 29, count 0 2006.245.07:31:15.04#ibcon#about to read 6, iclass 29, count 0 2006.245.07:31:15.04#ibcon#read 6, iclass 29, count 0 2006.245.07:31:15.04#ibcon#end of sib2, iclass 29, count 0 2006.245.07:31:15.04#ibcon#*after write, iclass 29, count 0 2006.245.07:31:15.04#ibcon#*before return 0, iclass 29, count 0 2006.245.07:31:15.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:15.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:31:15.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:31:15.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:31:15.04$vc4f8/vblo=4,712.99 2006.245.07:31:15.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:31:15.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:31:15.04#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:15.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:15.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:15.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:15.04#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:31:15.04#ibcon#first serial, iclass 31, count 0 2006.245.07:31:15.04#ibcon#enter sib2, iclass 31, count 0 2006.245.07:31:15.04#ibcon#flushed, iclass 31, count 0 2006.245.07:31:15.04#ibcon#about to write, iclass 31, count 0 2006.245.07:31:15.04#ibcon#wrote, iclass 31, count 0 2006.245.07:31:15.04#ibcon#about to read 3, iclass 31, count 0 2006.245.07:31:15.06#ibcon#read 3, iclass 31, count 0 2006.245.07:31:15.06#ibcon#about to read 4, iclass 31, count 0 2006.245.07:31:15.06#ibcon#read 4, iclass 31, count 0 2006.245.07:31:15.06#ibcon#about to read 5, iclass 31, count 0 2006.245.07:31:15.06#ibcon#read 5, iclass 31, count 0 2006.245.07:31:15.06#ibcon#about to read 6, iclass 31, count 0 2006.245.07:31:15.06#ibcon#read 6, iclass 31, count 0 2006.245.07:31:15.06#ibcon#end of sib2, iclass 31, count 0 2006.245.07:31:15.06#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:31:15.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:31:15.06#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:31:15.06#ibcon#*before write, iclass 31, count 0 2006.245.07:31:15.06#ibcon#enter sib2, iclass 31, count 0 2006.245.07:31:15.06#ibcon#flushed, iclass 31, count 0 2006.245.07:31:15.06#ibcon#about to write, iclass 31, count 0 2006.245.07:31:15.06#ibcon#wrote, iclass 31, count 0 2006.245.07:31:15.06#ibcon#about to read 3, iclass 31, count 0 2006.245.07:31:15.10#ibcon#read 3, iclass 31, count 0 2006.245.07:31:15.10#ibcon#about to read 4, iclass 31, count 0 2006.245.07:31:15.10#ibcon#read 4, iclass 31, count 0 2006.245.07:31:15.10#ibcon#about to read 5, iclass 31, count 0 2006.245.07:31:15.10#ibcon#read 5, iclass 31, count 0 2006.245.07:31:15.10#ibcon#about to read 6, iclass 31, count 0 2006.245.07:31:15.10#ibcon#read 6, iclass 31, count 0 2006.245.07:31:15.10#ibcon#end of sib2, iclass 31, count 0 2006.245.07:31:15.10#ibcon#*after write, iclass 31, count 0 2006.245.07:31:15.10#ibcon#*before return 0, iclass 31, count 0 2006.245.07:31:15.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:15.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:31:15.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:31:15.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:31:15.10$vc4f8/vb=4,4 2006.245.07:31:15.10#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:31:15.10#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:31:15.10#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:15.10#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:15.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:15.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:15.16#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:31:15.16#ibcon#first serial, iclass 33, count 2 2006.245.07:31:15.16#ibcon#enter sib2, iclass 33, count 2 2006.245.07:31:15.16#ibcon#flushed, iclass 33, count 2 2006.245.07:31:15.16#ibcon#about to write, iclass 33, count 2 2006.245.07:31:15.16#ibcon#wrote, iclass 33, count 2 2006.245.07:31:15.16#ibcon#about to read 3, iclass 33, count 2 2006.245.07:31:15.18#ibcon#read 3, iclass 33, count 2 2006.245.07:31:15.18#ibcon#about to read 4, iclass 33, count 2 2006.245.07:31:15.18#ibcon#read 4, iclass 33, count 2 2006.245.07:31:15.18#ibcon#about to read 5, iclass 33, count 2 2006.245.07:31:15.18#ibcon#read 5, iclass 33, count 2 2006.245.07:31:15.18#ibcon#about to read 6, iclass 33, count 2 2006.245.07:31:15.18#ibcon#read 6, iclass 33, count 2 2006.245.07:31:15.18#ibcon#end of sib2, iclass 33, count 2 2006.245.07:31:15.18#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:31:15.18#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:31:15.18#ibcon#[27=AT04-04\r\n] 2006.245.07:31:15.18#ibcon#*before write, iclass 33, count 2 2006.245.07:31:15.18#ibcon#enter sib2, iclass 33, count 2 2006.245.07:31:15.18#ibcon#flushed, iclass 33, count 2 2006.245.07:31:15.18#ibcon#about to write, iclass 33, count 2 2006.245.07:31:15.18#ibcon#wrote, iclass 33, count 2 2006.245.07:31:15.18#ibcon#about to read 3, iclass 33, count 2 2006.245.07:31:15.21#ibcon#read 3, iclass 33, count 2 2006.245.07:31:15.21#ibcon#about to read 4, iclass 33, count 2 2006.245.07:31:15.21#ibcon#read 4, iclass 33, count 2 2006.245.07:31:15.21#ibcon#about to read 5, iclass 33, count 2 2006.245.07:31:15.21#ibcon#read 5, iclass 33, count 2 2006.245.07:31:15.21#ibcon#about to read 6, iclass 33, count 2 2006.245.07:31:15.21#ibcon#read 6, iclass 33, count 2 2006.245.07:31:15.21#ibcon#end of sib2, iclass 33, count 2 2006.245.07:31:15.21#ibcon#*after write, iclass 33, count 2 2006.245.07:31:15.21#ibcon#*before return 0, iclass 33, count 2 2006.245.07:31:15.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:15.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:31:15.21#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:31:15.21#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:15.21#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:15.33#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:15.33#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:15.33#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:31:15.33#ibcon#first serial, iclass 33, count 0 2006.245.07:31:15.33#ibcon#enter sib2, iclass 33, count 0 2006.245.07:31:15.33#ibcon#flushed, iclass 33, count 0 2006.245.07:31:15.33#ibcon#about to write, iclass 33, count 0 2006.245.07:31:15.33#ibcon#wrote, iclass 33, count 0 2006.245.07:31:15.33#ibcon#about to read 3, iclass 33, count 0 2006.245.07:31:15.35#ibcon#read 3, iclass 33, count 0 2006.245.07:31:15.35#ibcon#about to read 4, iclass 33, count 0 2006.245.07:31:15.35#ibcon#read 4, iclass 33, count 0 2006.245.07:31:15.35#ibcon#about to read 5, iclass 33, count 0 2006.245.07:31:15.35#ibcon#read 5, iclass 33, count 0 2006.245.07:31:15.35#ibcon#about to read 6, iclass 33, count 0 2006.245.07:31:15.35#ibcon#read 6, iclass 33, count 0 2006.245.07:31:15.35#ibcon#end of sib2, iclass 33, count 0 2006.245.07:31:15.35#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:31:15.35#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:31:15.35#ibcon#[27=USB\r\n] 2006.245.07:31:15.35#ibcon#*before write, iclass 33, count 0 2006.245.07:31:15.35#ibcon#enter sib2, iclass 33, count 0 2006.245.07:31:15.35#ibcon#flushed, iclass 33, count 0 2006.245.07:31:15.35#ibcon#about to write, iclass 33, count 0 2006.245.07:31:15.35#ibcon#wrote, iclass 33, count 0 2006.245.07:31:15.35#ibcon#about to read 3, iclass 33, count 0 2006.245.07:31:15.38#ibcon#read 3, iclass 33, count 0 2006.245.07:31:15.38#ibcon#about to read 4, iclass 33, count 0 2006.245.07:31:15.38#ibcon#read 4, iclass 33, count 0 2006.245.07:31:15.38#ibcon#about to read 5, iclass 33, count 0 2006.245.07:31:15.38#ibcon#read 5, iclass 33, count 0 2006.245.07:31:15.38#ibcon#about to read 6, iclass 33, count 0 2006.245.07:31:15.38#ibcon#read 6, iclass 33, count 0 2006.245.07:31:15.38#ibcon#end of sib2, iclass 33, count 0 2006.245.07:31:15.38#ibcon#*after write, iclass 33, count 0 2006.245.07:31:15.38#ibcon#*before return 0, iclass 33, count 0 2006.245.07:31:15.38#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:15.38#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:31:15.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:31:15.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:31:15.38$vc4f8/vblo=5,744.99 2006.245.07:31:15.38#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:31:15.38#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:31:15.38#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:15.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:15.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:15.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:15.38#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:31:15.38#ibcon#first serial, iclass 35, count 0 2006.245.07:31:15.38#ibcon#enter sib2, iclass 35, count 0 2006.245.07:31:15.38#ibcon#flushed, iclass 35, count 0 2006.245.07:31:15.38#ibcon#about to write, iclass 35, count 0 2006.245.07:31:15.38#ibcon#wrote, iclass 35, count 0 2006.245.07:31:15.38#ibcon#about to read 3, iclass 35, count 0 2006.245.07:31:15.40#ibcon#read 3, iclass 35, count 0 2006.245.07:31:15.40#ibcon#about to read 4, iclass 35, count 0 2006.245.07:31:15.40#ibcon#read 4, iclass 35, count 0 2006.245.07:31:15.40#ibcon#about to read 5, iclass 35, count 0 2006.245.07:31:15.40#ibcon#read 5, iclass 35, count 0 2006.245.07:31:15.40#ibcon#about to read 6, iclass 35, count 0 2006.245.07:31:15.40#ibcon#read 6, iclass 35, count 0 2006.245.07:31:15.40#ibcon#end of sib2, iclass 35, count 0 2006.245.07:31:15.40#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:31:15.40#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:31:15.40#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:31:15.40#ibcon#*before write, iclass 35, count 0 2006.245.07:31:15.40#ibcon#enter sib2, iclass 35, count 0 2006.245.07:31:15.40#ibcon#flushed, iclass 35, count 0 2006.245.07:31:15.40#ibcon#about to write, iclass 35, count 0 2006.245.07:31:15.40#ibcon#wrote, iclass 35, count 0 2006.245.07:31:15.40#ibcon#about to read 3, iclass 35, count 0 2006.245.07:31:15.44#ibcon#read 3, iclass 35, count 0 2006.245.07:31:15.44#ibcon#about to read 4, iclass 35, count 0 2006.245.07:31:15.44#ibcon#read 4, iclass 35, count 0 2006.245.07:31:15.44#ibcon#about to read 5, iclass 35, count 0 2006.245.07:31:15.44#ibcon#read 5, iclass 35, count 0 2006.245.07:31:15.44#ibcon#about to read 6, iclass 35, count 0 2006.245.07:31:15.44#ibcon#read 6, iclass 35, count 0 2006.245.07:31:15.44#ibcon#end of sib2, iclass 35, count 0 2006.245.07:31:15.44#ibcon#*after write, iclass 35, count 0 2006.245.07:31:15.44#ibcon#*before return 0, iclass 35, count 0 2006.245.07:31:15.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:15.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:31:15.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:31:15.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:31:15.44$vc4f8/vb=5,3 2006.245.07:31:15.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:31:15.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:31:15.44#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:15.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:15.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:15.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:15.51#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:31:15.51#ibcon#first serial, iclass 37, count 2 2006.245.07:31:15.51#ibcon#enter sib2, iclass 37, count 2 2006.245.07:31:15.51#ibcon#flushed, iclass 37, count 2 2006.245.07:31:15.51#ibcon#about to write, iclass 37, count 2 2006.245.07:31:15.51#ibcon#wrote, iclass 37, count 2 2006.245.07:31:15.51#ibcon#about to read 3, iclass 37, count 2 2006.245.07:31:15.52#ibcon#read 3, iclass 37, count 2 2006.245.07:31:15.52#ibcon#about to read 4, iclass 37, count 2 2006.245.07:31:15.52#ibcon#read 4, iclass 37, count 2 2006.245.07:31:15.52#ibcon#about to read 5, iclass 37, count 2 2006.245.07:31:15.52#ibcon#read 5, iclass 37, count 2 2006.245.07:31:15.52#ibcon#about to read 6, iclass 37, count 2 2006.245.07:31:15.52#ibcon#read 6, iclass 37, count 2 2006.245.07:31:15.52#ibcon#end of sib2, iclass 37, count 2 2006.245.07:31:15.52#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:31:15.52#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:31:15.52#ibcon#[27=AT05-03\r\n] 2006.245.07:31:15.52#ibcon#*before write, iclass 37, count 2 2006.245.07:31:15.52#ibcon#enter sib2, iclass 37, count 2 2006.245.07:31:15.52#ibcon#flushed, iclass 37, count 2 2006.245.07:31:15.52#ibcon#about to write, iclass 37, count 2 2006.245.07:31:15.52#ibcon#wrote, iclass 37, count 2 2006.245.07:31:15.52#ibcon#about to read 3, iclass 37, count 2 2006.245.07:31:15.55#ibcon#read 3, iclass 37, count 2 2006.245.07:31:15.55#ibcon#about to read 4, iclass 37, count 2 2006.245.07:31:15.55#ibcon#read 4, iclass 37, count 2 2006.245.07:31:15.55#ibcon#about to read 5, iclass 37, count 2 2006.245.07:31:15.55#ibcon#read 5, iclass 37, count 2 2006.245.07:31:15.55#ibcon#about to read 6, iclass 37, count 2 2006.245.07:31:15.55#ibcon#read 6, iclass 37, count 2 2006.245.07:31:15.55#ibcon#end of sib2, iclass 37, count 2 2006.245.07:31:15.55#ibcon#*after write, iclass 37, count 2 2006.245.07:31:15.55#ibcon#*before return 0, iclass 37, count 2 2006.245.07:31:15.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:15.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:31:15.55#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:31:15.55#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:15.55#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:15.67#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:15.67#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:15.67#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:31:15.67#ibcon#first serial, iclass 37, count 0 2006.245.07:31:15.67#ibcon#enter sib2, iclass 37, count 0 2006.245.07:31:15.67#ibcon#flushed, iclass 37, count 0 2006.245.07:31:15.67#ibcon#about to write, iclass 37, count 0 2006.245.07:31:15.67#ibcon#wrote, iclass 37, count 0 2006.245.07:31:15.67#ibcon#about to read 3, iclass 37, count 0 2006.245.07:31:15.69#ibcon#read 3, iclass 37, count 0 2006.245.07:31:15.69#ibcon#about to read 4, iclass 37, count 0 2006.245.07:31:15.69#ibcon#read 4, iclass 37, count 0 2006.245.07:31:15.69#ibcon#about to read 5, iclass 37, count 0 2006.245.07:31:15.69#ibcon#read 5, iclass 37, count 0 2006.245.07:31:15.69#ibcon#about to read 6, iclass 37, count 0 2006.245.07:31:15.69#ibcon#read 6, iclass 37, count 0 2006.245.07:31:15.69#ibcon#end of sib2, iclass 37, count 0 2006.245.07:31:15.69#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:31:15.69#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:31:15.69#ibcon#[27=USB\r\n] 2006.245.07:31:15.69#ibcon#*before write, iclass 37, count 0 2006.245.07:31:15.69#ibcon#enter sib2, iclass 37, count 0 2006.245.07:31:15.69#ibcon#flushed, iclass 37, count 0 2006.245.07:31:15.69#ibcon#about to write, iclass 37, count 0 2006.245.07:31:15.69#ibcon#wrote, iclass 37, count 0 2006.245.07:31:15.69#ibcon#about to read 3, iclass 37, count 0 2006.245.07:31:15.72#ibcon#read 3, iclass 37, count 0 2006.245.07:31:15.72#ibcon#about to read 4, iclass 37, count 0 2006.245.07:31:15.72#ibcon#read 4, iclass 37, count 0 2006.245.07:31:15.72#ibcon#about to read 5, iclass 37, count 0 2006.245.07:31:15.72#ibcon#read 5, iclass 37, count 0 2006.245.07:31:15.72#ibcon#about to read 6, iclass 37, count 0 2006.245.07:31:15.72#ibcon#read 6, iclass 37, count 0 2006.245.07:31:15.72#ibcon#end of sib2, iclass 37, count 0 2006.245.07:31:15.72#ibcon#*after write, iclass 37, count 0 2006.245.07:31:15.72#ibcon#*before return 0, iclass 37, count 0 2006.245.07:31:15.72#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:15.72#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:31:15.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:31:15.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:31:15.72$vc4f8/vblo=6,752.99 2006.245.07:31:15.72#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:31:15.72#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:31:15.72#ibcon#ireg 17 cls_cnt 0 2006.245.07:31:15.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:15.72#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:15.72#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:15.72#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:31:15.72#ibcon#first serial, iclass 39, count 0 2006.245.07:31:15.72#ibcon#enter sib2, iclass 39, count 0 2006.245.07:31:15.72#ibcon#flushed, iclass 39, count 0 2006.245.07:31:15.72#ibcon#about to write, iclass 39, count 0 2006.245.07:31:15.72#ibcon#wrote, iclass 39, count 0 2006.245.07:31:15.72#ibcon#about to read 3, iclass 39, count 0 2006.245.07:31:15.74#ibcon#read 3, iclass 39, count 0 2006.245.07:31:15.74#ibcon#about to read 4, iclass 39, count 0 2006.245.07:31:15.74#ibcon#read 4, iclass 39, count 0 2006.245.07:31:15.74#ibcon#about to read 5, iclass 39, count 0 2006.245.07:31:15.74#ibcon#read 5, iclass 39, count 0 2006.245.07:31:15.74#ibcon#about to read 6, iclass 39, count 0 2006.245.07:31:15.74#ibcon#read 6, iclass 39, count 0 2006.245.07:31:15.74#ibcon#end of sib2, iclass 39, count 0 2006.245.07:31:15.74#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:31:15.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:31:15.74#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:31:15.74#ibcon#*before write, iclass 39, count 0 2006.245.07:31:15.74#ibcon#enter sib2, iclass 39, count 0 2006.245.07:31:15.74#ibcon#flushed, iclass 39, count 0 2006.245.07:31:15.74#ibcon#about to write, iclass 39, count 0 2006.245.07:31:15.74#ibcon#wrote, iclass 39, count 0 2006.245.07:31:15.74#ibcon#about to read 3, iclass 39, count 0 2006.245.07:31:15.78#ibcon#read 3, iclass 39, count 0 2006.245.07:31:15.78#ibcon#about to read 4, iclass 39, count 0 2006.245.07:31:15.78#ibcon#read 4, iclass 39, count 0 2006.245.07:31:15.78#ibcon#about to read 5, iclass 39, count 0 2006.245.07:31:15.78#ibcon#read 5, iclass 39, count 0 2006.245.07:31:15.78#ibcon#about to read 6, iclass 39, count 0 2006.245.07:31:15.78#ibcon#read 6, iclass 39, count 0 2006.245.07:31:15.78#ibcon#end of sib2, iclass 39, count 0 2006.245.07:31:15.78#ibcon#*after write, iclass 39, count 0 2006.245.07:31:15.78#ibcon#*before return 0, iclass 39, count 0 2006.245.07:31:15.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:15.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:31:15.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:31:15.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:31:15.78$vc4f8/vb=6,3 2006.245.07:31:15.78#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:31:15.78#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:31:15.78#ibcon#ireg 11 cls_cnt 2 2006.245.07:31:15.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:15.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:15.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:15.84#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:31:15.84#ibcon#first serial, iclass 3, count 2 2006.245.07:31:15.84#ibcon#enter sib2, iclass 3, count 2 2006.245.07:31:15.84#ibcon#flushed, iclass 3, count 2 2006.245.07:31:15.84#ibcon#about to write, iclass 3, count 2 2006.245.07:31:15.84#ibcon#wrote, iclass 3, count 2 2006.245.07:31:15.84#ibcon#about to read 3, iclass 3, count 2 2006.245.07:31:15.86#ibcon#read 3, iclass 3, count 2 2006.245.07:31:15.86#ibcon#about to read 4, iclass 3, count 2 2006.245.07:31:15.86#ibcon#read 4, iclass 3, count 2 2006.245.07:31:15.86#ibcon#about to read 5, iclass 3, count 2 2006.245.07:31:15.86#ibcon#read 5, iclass 3, count 2 2006.245.07:31:15.86#ibcon#about to read 6, iclass 3, count 2 2006.245.07:31:15.86#ibcon#read 6, iclass 3, count 2 2006.245.07:31:15.86#ibcon#end of sib2, iclass 3, count 2 2006.245.07:31:15.86#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:31:15.86#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:31:15.86#ibcon#[27=AT06-03\r\n] 2006.245.07:31:15.86#ibcon#*before write, iclass 3, count 2 2006.245.07:31:15.86#ibcon#enter sib2, iclass 3, count 2 2006.245.07:31:15.86#ibcon#flushed, iclass 3, count 2 2006.245.07:31:15.86#ibcon#about to write, iclass 3, count 2 2006.245.07:31:15.86#ibcon#wrote, iclass 3, count 2 2006.245.07:31:15.86#ibcon#about to read 3, iclass 3, count 2 2006.245.07:31:15.89#ibcon#read 3, iclass 3, count 2 2006.245.07:31:15.89#ibcon#about to read 4, iclass 3, count 2 2006.245.07:31:15.89#ibcon#read 4, iclass 3, count 2 2006.245.07:31:15.89#ibcon#about to read 5, iclass 3, count 2 2006.245.07:31:15.89#ibcon#read 5, iclass 3, count 2 2006.245.07:31:15.89#ibcon#about to read 6, iclass 3, count 2 2006.245.07:31:15.89#ibcon#read 6, iclass 3, count 2 2006.245.07:31:15.89#ibcon#end of sib2, iclass 3, count 2 2006.245.07:31:15.89#ibcon#*after write, iclass 3, count 2 2006.245.07:31:15.89#ibcon#*before return 0, iclass 3, count 2 2006.245.07:31:15.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:15.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:31:15.89#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:31:15.89#ibcon#ireg 7 cls_cnt 0 2006.245.07:31:15.89#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:16.01#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:16.01#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:16.01#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:31:16.01#ibcon#first serial, iclass 3, count 0 2006.245.07:31:16.01#ibcon#enter sib2, iclass 3, count 0 2006.245.07:31:16.01#ibcon#flushed, iclass 3, count 0 2006.245.07:31:16.01#ibcon#about to write, iclass 3, count 0 2006.245.07:31:16.01#ibcon#wrote, iclass 3, count 0 2006.245.07:31:16.01#ibcon#about to read 3, iclass 3, count 0 2006.245.07:31:16.03#ibcon#read 3, iclass 3, count 0 2006.245.07:31:16.03#ibcon#about to read 4, iclass 3, count 0 2006.245.07:31:16.03#ibcon#read 4, iclass 3, count 0 2006.245.07:31:16.03#ibcon#about to read 5, iclass 3, count 0 2006.245.07:31:16.03#ibcon#read 5, iclass 3, count 0 2006.245.07:31:16.03#ibcon#about to read 6, iclass 3, count 0 2006.245.07:31:16.03#ibcon#read 6, iclass 3, count 0 2006.245.07:31:16.03#ibcon#end of sib2, iclass 3, count 0 2006.245.07:31:16.03#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:31:16.03#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:31:16.03#ibcon#[27=USB\r\n] 2006.245.07:31:16.03#ibcon#*before write, iclass 3, count 0 2006.245.07:31:16.03#ibcon#enter sib2, iclass 3, count 0 2006.245.07:31:16.03#ibcon#flushed, iclass 3, count 0 2006.245.07:31:16.03#ibcon#about to write, iclass 3, count 0 2006.245.07:31:16.03#ibcon#wrote, iclass 3, count 0 2006.245.07:31:16.03#ibcon#about to read 3, iclass 3, count 0 2006.245.07:31:16.06#ibcon#read 3, iclass 3, count 0 2006.245.07:31:16.06#ibcon#about to read 4, iclass 3, count 0 2006.245.07:31:16.06#ibcon#read 4, iclass 3, count 0 2006.245.07:31:16.06#ibcon#about to read 5, iclass 3, count 0 2006.245.07:31:16.06#ibcon#read 5, iclass 3, count 0 2006.245.07:31:16.06#ibcon#about to read 6, iclass 3, count 0 2006.245.07:31:16.06#ibcon#read 6, iclass 3, count 0 2006.245.07:31:16.06#ibcon#end of sib2, iclass 3, count 0 2006.245.07:31:16.06#ibcon#*after write, iclass 3, count 0 2006.245.07:31:16.06#ibcon#*before return 0, iclass 3, count 0 2006.245.07:31:16.06#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:16.06#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:31:16.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:31:16.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:31:16.06$vc4f8/vabw=wide 2006.245.07:31:16.06#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:31:16.06#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:31:16.06#ibcon#ireg 8 cls_cnt 0 2006.245.07:31:16.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:16.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:16.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:16.06#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:31:16.06#ibcon#first serial, iclass 5, count 0 2006.245.07:31:16.06#ibcon#enter sib2, iclass 5, count 0 2006.245.07:31:16.06#ibcon#flushed, iclass 5, count 0 2006.245.07:31:16.06#ibcon#about to write, iclass 5, count 0 2006.245.07:31:16.06#ibcon#wrote, iclass 5, count 0 2006.245.07:31:16.06#ibcon#about to read 3, iclass 5, count 0 2006.245.07:31:16.08#ibcon#read 3, iclass 5, count 0 2006.245.07:31:16.08#ibcon#about to read 4, iclass 5, count 0 2006.245.07:31:16.08#ibcon#read 4, iclass 5, count 0 2006.245.07:31:16.08#ibcon#about to read 5, iclass 5, count 0 2006.245.07:31:16.08#ibcon#read 5, iclass 5, count 0 2006.245.07:31:16.08#ibcon#about to read 6, iclass 5, count 0 2006.245.07:31:16.08#ibcon#read 6, iclass 5, count 0 2006.245.07:31:16.08#ibcon#end of sib2, iclass 5, count 0 2006.245.07:31:16.08#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:31:16.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:31:16.08#ibcon#[25=BW32\r\n] 2006.245.07:31:16.08#ibcon#*before write, iclass 5, count 0 2006.245.07:31:16.08#ibcon#enter sib2, iclass 5, count 0 2006.245.07:31:16.08#ibcon#flushed, iclass 5, count 0 2006.245.07:31:16.08#ibcon#about to write, iclass 5, count 0 2006.245.07:31:16.08#ibcon#wrote, iclass 5, count 0 2006.245.07:31:16.08#ibcon#about to read 3, iclass 5, count 0 2006.245.07:31:16.11#ibcon#read 3, iclass 5, count 0 2006.245.07:31:16.11#ibcon#about to read 4, iclass 5, count 0 2006.245.07:31:16.11#ibcon#read 4, iclass 5, count 0 2006.245.07:31:16.11#ibcon#about to read 5, iclass 5, count 0 2006.245.07:31:16.11#ibcon#read 5, iclass 5, count 0 2006.245.07:31:16.11#ibcon#about to read 6, iclass 5, count 0 2006.245.07:31:16.11#ibcon#read 6, iclass 5, count 0 2006.245.07:31:16.11#ibcon#end of sib2, iclass 5, count 0 2006.245.07:31:16.11#ibcon#*after write, iclass 5, count 0 2006.245.07:31:16.11#ibcon#*before return 0, iclass 5, count 0 2006.245.07:31:16.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:16.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:31:16.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:31:16.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:31:16.11$vc4f8/vbbw=wide 2006.245.07:31:16.11#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:31:16.11#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:31:16.11#ibcon#ireg 8 cls_cnt 0 2006.245.07:31:16.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:31:16.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:31:16.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:31:16.18#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:31:16.18#ibcon#first serial, iclass 7, count 0 2006.245.07:31:16.18#ibcon#enter sib2, iclass 7, count 0 2006.245.07:31:16.18#ibcon#flushed, iclass 7, count 0 2006.245.07:31:16.18#ibcon#about to write, iclass 7, count 0 2006.245.07:31:16.18#ibcon#wrote, iclass 7, count 0 2006.245.07:31:16.18#ibcon#about to read 3, iclass 7, count 0 2006.245.07:31:16.20#ibcon#read 3, iclass 7, count 0 2006.245.07:31:16.20#ibcon#about to read 4, iclass 7, count 0 2006.245.07:31:16.20#ibcon#read 4, iclass 7, count 0 2006.245.07:31:16.20#ibcon#about to read 5, iclass 7, count 0 2006.245.07:31:16.20#ibcon#read 5, iclass 7, count 0 2006.245.07:31:16.20#ibcon#about to read 6, iclass 7, count 0 2006.245.07:31:16.20#ibcon#read 6, iclass 7, count 0 2006.245.07:31:16.20#ibcon#end of sib2, iclass 7, count 0 2006.245.07:31:16.20#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:31:16.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:31:16.20#ibcon#[27=BW32\r\n] 2006.245.07:31:16.20#ibcon#*before write, iclass 7, count 0 2006.245.07:31:16.20#ibcon#enter sib2, iclass 7, count 0 2006.245.07:31:16.20#ibcon#flushed, iclass 7, count 0 2006.245.07:31:16.20#ibcon#about to write, iclass 7, count 0 2006.245.07:31:16.20#ibcon#wrote, iclass 7, count 0 2006.245.07:31:16.20#ibcon#about to read 3, iclass 7, count 0 2006.245.07:31:16.23#ibcon#read 3, iclass 7, count 0 2006.245.07:31:16.23#ibcon#about to read 4, iclass 7, count 0 2006.245.07:31:16.23#ibcon#read 4, iclass 7, count 0 2006.245.07:31:16.23#ibcon#about to read 5, iclass 7, count 0 2006.245.07:31:16.23#ibcon#read 5, iclass 7, count 0 2006.245.07:31:16.23#ibcon#about to read 6, iclass 7, count 0 2006.245.07:31:16.23#ibcon#read 6, iclass 7, count 0 2006.245.07:31:16.23#ibcon#end of sib2, iclass 7, count 0 2006.245.07:31:16.23#ibcon#*after write, iclass 7, count 0 2006.245.07:31:16.23#ibcon#*before return 0, iclass 7, count 0 2006.245.07:31:16.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:31:16.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:31:16.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:31:16.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:31:16.23$4f8m12a/ifd4f 2006.245.07:31:16.23$ifd4f/lo= 2006.245.07:31:16.23$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:31:16.23$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:31:16.23$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:31:16.23$ifd4f/patch= 2006.245.07:31:16.23$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:31:16.23$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:31:16.23$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:31:16.23$4f8m12a/"form=m,16.000,1:2 2006.245.07:31:16.23$4f8m12a/"tpicd 2006.245.07:31:16.23$4f8m12a/echo=off 2006.245.07:31:16.23$4f8m12a/xlog=off 2006.245.07:31:16.23:!2006.245.07:33:20 2006.245.07:31:43.13#trakl#Source acquired 2006.245.07:31:45.13#flagr#flagr/antenna,acquired 2006.245.07:33:20.00:preob 2006.245.07:33:20.14/onsource/TRACKING 2006.245.07:33:20.14:!2006.245.07:33:30 2006.245.07:33:30.00:data_valid=on 2006.245.07:33:30.00:midob 2006.245.07:33:30.14/onsource/TRACKING 2006.245.07:33:30.14/wx/27.63,1004.4,66 2006.245.07:33:30.22/cable/+6.4110E-03 2006.245.07:33:31.31/va/01,08,usb,yes,33,35 2006.245.07:33:31.31/va/02,07,usb,yes,33,35 2006.245.07:33:31.31/va/03,06,usb,yes,35,35 2006.245.07:33:31.31/va/04,07,usb,yes,34,37 2006.245.07:33:31.31/va/05,07,usb,yes,36,37 2006.245.07:33:31.31/va/06,07,usb,yes,31,31 2006.245.07:33:31.31/va/07,07,usb,yes,31,31 2006.245.07:33:31.31/va/08,08,usb,yes,27,26 2006.245.07:33:31.54/valo/01,532.99,yes,locked 2006.245.07:33:31.54/valo/02,572.99,yes,locked 2006.245.07:33:31.54/valo/03,672.99,yes,locked 2006.245.07:33:31.54/valo/04,832.99,yes,locked 2006.245.07:33:31.54/valo/05,652.99,yes,locked 2006.245.07:33:31.54/valo/06,772.99,yes,locked 2006.245.07:33:31.54/valo/07,832.99,yes,locked 2006.245.07:33:31.54/valo/08,852.99,yes,locked 2006.245.07:33:32.63/vb/01,04,usb,yes,32,31 2006.245.07:33:32.63/vb/02,04,usb,yes,34,35 2006.245.07:33:32.63/vb/03,04,usb,yes,30,34 2006.245.07:33:32.63/vb/04,04,usb,yes,31,31 2006.245.07:33:32.63/vb/05,03,usb,yes,37,41 2006.245.07:33:32.63/vb/06,03,usb,yes,37,41 2006.245.07:33:32.63/vb/07,04,usb,yes,33,33 2006.245.07:33:32.63/vb/08,03,usb,yes,37,41 2006.245.07:33:32.86/vblo/01,632.99,yes,locked 2006.245.07:33:32.86/vblo/02,640.99,yes,locked 2006.245.07:33:32.86/vblo/03,656.99,yes,locked 2006.245.07:33:32.86/vblo/04,712.99,yes,locked 2006.245.07:33:32.86/vblo/05,744.99,yes,locked 2006.245.07:33:32.86/vblo/06,752.99,yes,locked 2006.245.07:33:32.86/vblo/07,734.99,yes,locked 2006.245.07:33:32.86/vblo/08,744.99,yes,locked 2006.245.07:33:33.01/vabw/8 2006.245.07:33:33.16/vbbw/8 2006.245.07:33:33.25/xfe/off,on,13.7 2006.245.07:33:33.63/ifatt/23,28,28,28 2006.245.07:33:34.07/fmout-gps/S +4.48E-07 2006.245.07:33:34.11:!2006.245.07:34:30 2006.245.07:34:30.01:data_valid=off 2006.245.07:34:30.01:postob 2006.245.07:34:30.13/cable/+6.4115E-03 2006.245.07:34:30.13/wx/27.62,1004.4,66 2006.245.07:34:31.08/fmout-gps/S +4.48E-07 2006.245.07:34:31.08:scan_name=245-0735,k06245,60 2006.245.07:34:31.09:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.245.07:34:31.14#flagr#flagr/antenna,new-source 2006.245.07:34:32.14:checkk5 2006.245.07:34:32.71/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:34:33.16/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:34:33.60/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:34:34.06/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:34:34.56/chk_obsdata//k5ts1/T2450733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:34:35.17/chk_obsdata//k5ts2/T2450733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:34:35.61/chk_obsdata//k5ts3/T2450733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:34:36.01/chk_obsdata//k5ts4/T2450733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:34:36.84/k5log//k5ts1_log_newline 2006.245.07:34:37.69/k5log//k5ts2_log_newline 2006.245.07:34:38.52/k5log//k5ts3_log_newline 2006.245.07:34:39.84/k5log//k5ts4_log_newline 2006.245.07:34:39.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:34:39.86:4f8m12a=1 2006.245.07:34:39.86$4f8m12a/echo=on 2006.245.07:34:39.86$4f8m12a/pcalon 2006.245.07:34:39.86$pcalon/"no phase cal control is implemented here 2006.245.07:34:39.86$4f8m12a/"tpicd=stop 2006.245.07:34:39.86$4f8m12a/vc4f8 2006.245.07:34:39.86$vc4f8/valo=1,532.99 2006.245.07:34:39.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.07:34:39.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.07:34:39.86#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:39.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:39.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:39.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:39.86#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:34:39.86#ibcon#first serial, iclass 15, count 0 2006.245.07:34:39.86#ibcon#enter sib2, iclass 15, count 0 2006.245.07:34:39.86#ibcon#flushed, iclass 15, count 0 2006.245.07:34:39.86#ibcon#about to write, iclass 15, count 0 2006.245.07:34:39.86#ibcon#wrote, iclass 15, count 0 2006.245.07:34:39.86#ibcon#about to read 3, iclass 15, count 0 2006.245.07:34:39.88#ibcon#read 3, iclass 15, count 0 2006.245.07:34:39.88#ibcon#about to read 4, iclass 15, count 0 2006.245.07:34:39.88#ibcon#read 4, iclass 15, count 0 2006.245.07:34:39.88#ibcon#about to read 5, iclass 15, count 0 2006.245.07:34:39.88#ibcon#read 5, iclass 15, count 0 2006.245.07:34:39.88#ibcon#about to read 6, iclass 15, count 0 2006.245.07:34:39.88#ibcon#read 6, iclass 15, count 0 2006.245.07:34:39.88#ibcon#end of sib2, iclass 15, count 0 2006.245.07:34:39.88#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:34:39.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:34:39.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:34:39.88#ibcon#*before write, iclass 15, count 0 2006.245.07:34:39.88#ibcon#enter sib2, iclass 15, count 0 2006.245.07:34:39.88#ibcon#flushed, iclass 15, count 0 2006.245.07:34:39.88#ibcon#about to write, iclass 15, count 0 2006.245.07:34:39.88#ibcon#wrote, iclass 15, count 0 2006.245.07:34:39.88#ibcon#about to read 3, iclass 15, count 0 2006.245.07:34:39.93#ibcon#read 3, iclass 15, count 0 2006.245.07:34:39.93#ibcon#about to read 4, iclass 15, count 0 2006.245.07:34:39.93#ibcon#read 4, iclass 15, count 0 2006.245.07:34:39.93#ibcon#about to read 5, iclass 15, count 0 2006.245.07:34:39.93#ibcon#read 5, iclass 15, count 0 2006.245.07:34:39.93#ibcon#about to read 6, iclass 15, count 0 2006.245.07:34:39.93#ibcon#read 6, iclass 15, count 0 2006.245.07:34:39.93#ibcon#end of sib2, iclass 15, count 0 2006.245.07:34:39.93#ibcon#*after write, iclass 15, count 0 2006.245.07:34:39.93#ibcon#*before return 0, iclass 15, count 0 2006.245.07:34:39.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:39.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:39.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:34:39.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:34:39.93$vc4f8/va=1,8 2006.245.07:34:39.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.07:34:39.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.07:34:39.93#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:39.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:39.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:39.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:39.93#ibcon#enter wrdev, iclass 17, count 2 2006.245.07:34:39.93#ibcon#first serial, iclass 17, count 2 2006.245.07:34:39.93#ibcon#enter sib2, iclass 17, count 2 2006.245.07:34:39.93#ibcon#flushed, iclass 17, count 2 2006.245.07:34:39.93#ibcon#about to write, iclass 17, count 2 2006.245.07:34:39.93#ibcon#wrote, iclass 17, count 2 2006.245.07:34:39.93#ibcon#about to read 3, iclass 17, count 2 2006.245.07:34:39.95#ibcon#read 3, iclass 17, count 2 2006.245.07:34:39.95#ibcon#about to read 4, iclass 17, count 2 2006.245.07:34:39.95#ibcon#read 4, iclass 17, count 2 2006.245.07:34:39.95#ibcon#about to read 5, iclass 17, count 2 2006.245.07:34:39.95#ibcon#read 5, iclass 17, count 2 2006.245.07:34:39.95#ibcon#about to read 6, iclass 17, count 2 2006.245.07:34:39.95#ibcon#read 6, iclass 17, count 2 2006.245.07:34:39.95#ibcon#end of sib2, iclass 17, count 2 2006.245.07:34:39.95#ibcon#*mode == 0, iclass 17, count 2 2006.245.07:34:39.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.07:34:39.95#ibcon#[25=AT01-08\r\n] 2006.245.07:34:39.95#ibcon#*before write, iclass 17, count 2 2006.245.07:34:39.95#ibcon#enter sib2, iclass 17, count 2 2006.245.07:34:39.95#ibcon#flushed, iclass 17, count 2 2006.245.07:34:39.95#ibcon#about to write, iclass 17, count 2 2006.245.07:34:39.95#ibcon#wrote, iclass 17, count 2 2006.245.07:34:39.95#ibcon#about to read 3, iclass 17, count 2 2006.245.07:34:39.98#ibcon#read 3, iclass 17, count 2 2006.245.07:34:39.98#ibcon#about to read 4, iclass 17, count 2 2006.245.07:34:39.98#ibcon#read 4, iclass 17, count 2 2006.245.07:34:39.98#ibcon#about to read 5, iclass 17, count 2 2006.245.07:34:39.98#ibcon#read 5, iclass 17, count 2 2006.245.07:34:39.98#ibcon#about to read 6, iclass 17, count 2 2006.245.07:34:39.98#ibcon#read 6, iclass 17, count 2 2006.245.07:34:39.98#ibcon#end of sib2, iclass 17, count 2 2006.245.07:34:39.98#ibcon#*after write, iclass 17, count 2 2006.245.07:34:39.98#ibcon#*before return 0, iclass 17, count 2 2006.245.07:34:39.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:39.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:39.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.07:34:39.98#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:39.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:40.11#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:40.11#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:40.11#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:34:40.11#ibcon#first serial, iclass 17, count 0 2006.245.07:34:40.11#ibcon#enter sib2, iclass 17, count 0 2006.245.07:34:40.11#ibcon#flushed, iclass 17, count 0 2006.245.07:34:40.11#ibcon#about to write, iclass 17, count 0 2006.245.07:34:40.11#ibcon#wrote, iclass 17, count 0 2006.245.07:34:40.11#ibcon#about to read 3, iclass 17, count 0 2006.245.07:34:40.12#ibcon#read 3, iclass 17, count 0 2006.245.07:34:40.12#ibcon#about to read 4, iclass 17, count 0 2006.245.07:34:40.12#ibcon#read 4, iclass 17, count 0 2006.245.07:34:40.12#ibcon#about to read 5, iclass 17, count 0 2006.245.07:34:40.12#ibcon#read 5, iclass 17, count 0 2006.245.07:34:40.12#ibcon#about to read 6, iclass 17, count 0 2006.245.07:34:40.12#ibcon#read 6, iclass 17, count 0 2006.245.07:34:40.12#ibcon#end of sib2, iclass 17, count 0 2006.245.07:34:40.12#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:34:40.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:34:40.12#ibcon#[25=USB\r\n] 2006.245.07:34:40.12#ibcon#*before write, iclass 17, count 0 2006.245.07:34:40.12#ibcon#enter sib2, iclass 17, count 0 2006.245.07:34:40.12#ibcon#flushed, iclass 17, count 0 2006.245.07:34:40.12#ibcon#about to write, iclass 17, count 0 2006.245.07:34:40.12#ibcon#wrote, iclass 17, count 0 2006.245.07:34:40.12#ibcon#about to read 3, iclass 17, count 0 2006.245.07:34:40.15#ibcon#read 3, iclass 17, count 0 2006.245.07:34:40.15#ibcon#about to read 4, iclass 17, count 0 2006.245.07:34:40.15#ibcon#read 4, iclass 17, count 0 2006.245.07:34:40.15#ibcon#about to read 5, iclass 17, count 0 2006.245.07:34:40.15#ibcon#read 5, iclass 17, count 0 2006.245.07:34:40.15#ibcon#about to read 6, iclass 17, count 0 2006.245.07:34:40.15#ibcon#read 6, iclass 17, count 0 2006.245.07:34:40.15#ibcon#end of sib2, iclass 17, count 0 2006.245.07:34:40.15#ibcon#*after write, iclass 17, count 0 2006.245.07:34:40.15#ibcon#*before return 0, iclass 17, count 0 2006.245.07:34:40.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:40.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:40.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:34:40.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:34:40.15$vc4f8/valo=2,572.99 2006.245.07:34:40.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.07:34:40.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.07:34:40.15#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:40.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:40.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:40.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:40.15#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:34:40.15#ibcon#first serial, iclass 19, count 0 2006.245.07:34:40.15#ibcon#enter sib2, iclass 19, count 0 2006.245.07:34:40.15#ibcon#flushed, iclass 19, count 0 2006.245.07:34:40.15#ibcon#about to write, iclass 19, count 0 2006.245.07:34:40.15#ibcon#wrote, iclass 19, count 0 2006.245.07:34:40.15#ibcon#about to read 3, iclass 19, count 0 2006.245.07:34:40.18#ibcon#read 3, iclass 19, count 0 2006.245.07:34:40.18#ibcon#about to read 4, iclass 19, count 0 2006.245.07:34:40.18#ibcon#read 4, iclass 19, count 0 2006.245.07:34:40.18#ibcon#about to read 5, iclass 19, count 0 2006.245.07:34:40.18#ibcon#read 5, iclass 19, count 0 2006.245.07:34:40.18#ibcon#about to read 6, iclass 19, count 0 2006.245.07:34:40.18#ibcon#read 6, iclass 19, count 0 2006.245.07:34:40.18#ibcon#end of sib2, iclass 19, count 0 2006.245.07:34:40.18#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:34:40.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:34:40.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:34:40.18#ibcon#*before write, iclass 19, count 0 2006.245.07:34:40.18#ibcon#enter sib2, iclass 19, count 0 2006.245.07:34:40.18#ibcon#flushed, iclass 19, count 0 2006.245.07:34:40.18#ibcon#about to write, iclass 19, count 0 2006.245.07:34:40.18#ibcon#wrote, iclass 19, count 0 2006.245.07:34:40.18#ibcon#about to read 3, iclass 19, count 0 2006.245.07:34:40.22#ibcon#read 3, iclass 19, count 0 2006.245.07:34:40.22#ibcon#about to read 4, iclass 19, count 0 2006.245.07:34:40.22#ibcon#read 4, iclass 19, count 0 2006.245.07:34:40.22#ibcon#about to read 5, iclass 19, count 0 2006.245.07:34:40.22#ibcon#read 5, iclass 19, count 0 2006.245.07:34:40.22#ibcon#about to read 6, iclass 19, count 0 2006.245.07:34:40.22#ibcon#read 6, iclass 19, count 0 2006.245.07:34:40.22#ibcon#end of sib2, iclass 19, count 0 2006.245.07:34:40.22#ibcon#*after write, iclass 19, count 0 2006.245.07:34:40.22#ibcon#*before return 0, iclass 19, count 0 2006.245.07:34:40.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:40.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:40.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:34:40.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:34:40.22$vc4f8/va=2,7 2006.245.07:34:40.22#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.07:34:40.22#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.07:34:40.22#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:40.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:40.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:40.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:40.27#ibcon#enter wrdev, iclass 21, count 2 2006.245.07:34:40.27#ibcon#first serial, iclass 21, count 2 2006.245.07:34:40.27#ibcon#enter sib2, iclass 21, count 2 2006.245.07:34:40.27#ibcon#flushed, iclass 21, count 2 2006.245.07:34:40.27#ibcon#about to write, iclass 21, count 2 2006.245.07:34:40.27#ibcon#wrote, iclass 21, count 2 2006.245.07:34:40.27#ibcon#about to read 3, iclass 21, count 2 2006.245.07:34:40.29#ibcon#read 3, iclass 21, count 2 2006.245.07:34:40.29#ibcon#about to read 4, iclass 21, count 2 2006.245.07:34:40.29#ibcon#read 4, iclass 21, count 2 2006.245.07:34:40.29#ibcon#about to read 5, iclass 21, count 2 2006.245.07:34:40.29#ibcon#read 5, iclass 21, count 2 2006.245.07:34:40.29#ibcon#about to read 6, iclass 21, count 2 2006.245.07:34:40.29#ibcon#read 6, iclass 21, count 2 2006.245.07:34:40.29#ibcon#end of sib2, iclass 21, count 2 2006.245.07:34:40.29#ibcon#*mode == 0, iclass 21, count 2 2006.245.07:34:40.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.07:34:40.29#ibcon#[25=AT02-07\r\n] 2006.245.07:34:40.29#ibcon#*before write, iclass 21, count 2 2006.245.07:34:40.29#ibcon#enter sib2, iclass 21, count 2 2006.245.07:34:40.29#ibcon#flushed, iclass 21, count 2 2006.245.07:34:40.29#ibcon#about to write, iclass 21, count 2 2006.245.07:34:40.29#ibcon#wrote, iclass 21, count 2 2006.245.07:34:40.29#ibcon#about to read 3, iclass 21, count 2 2006.245.07:34:40.32#ibcon#read 3, iclass 21, count 2 2006.245.07:34:40.32#ibcon#about to read 4, iclass 21, count 2 2006.245.07:34:40.32#ibcon#read 4, iclass 21, count 2 2006.245.07:34:40.32#ibcon#about to read 5, iclass 21, count 2 2006.245.07:34:40.32#ibcon#read 5, iclass 21, count 2 2006.245.07:34:40.32#ibcon#about to read 6, iclass 21, count 2 2006.245.07:34:40.32#ibcon#read 6, iclass 21, count 2 2006.245.07:34:40.32#ibcon#end of sib2, iclass 21, count 2 2006.245.07:34:40.32#ibcon#*after write, iclass 21, count 2 2006.245.07:34:40.32#ibcon#*before return 0, iclass 21, count 2 2006.245.07:34:40.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:40.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:40.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.07:34:40.32#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:40.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:40.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:40.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:40.44#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:34:40.44#ibcon#first serial, iclass 21, count 0 2006.245.07:34:40.44#ibcon#enter sib2, iclass 21, count 0 2006.245.07:34:40.44#ibcon#flushed, iclass 21, count 0 2006.245.07:34:40.44#ibcon#about to write, iclass 21, count 0 2006.245.07:34:40.44#ibcon#wrote, iclass 21, count 0 2006.245.07:34:40.44#ibcon#about to read 3, iclass 21, count 0 2006.245.07:34:40.46#ibcon#read 3, iclass 21, count 0 2006.245.07:34:40.46#ibcon#about to read 4, iclass 21, count 0 2006.245.07:34:40.46#ibcon#read 4, iclass 21, count 0 2006.245.07:34:40.46#ibcon#about to read 5, iclass 21, count 0 2006.245.07:34:40.46#ibcon#read 5, iclass 21, count 0 2006.245.07:34:40.46#ibcon#about to read 6, iclass 21, count 0 2006.245.07:34:40.46#ibcon#read 6, iclass 21, count 0 2006.245.07:34:40.46#ibcon#end of sib2, iclass 21, count 0 2006.245.07:34:40.46#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:34:40.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:34:40.46#ibcon#[25=USB\r\n] 2006.245.07:34:40.46#ibcon#*before write, iclass 21, count 0 2006.245.07:34:40.46#ibcon#enter sib2, iclass 21, count 0 2006.245.07:34:40.46#ibcon#flushed, iclass 21, count 0 2006.245.07:34:40.46#ibcon#about to write, iclass 21, count 0 2006.245.07:34:40.46#ibcon#wrote, iclass 21, count 0 2006.245.07:34:40.46#ibcon#about to read 3, iclass 21, count 0 2006.245.07:34:40.49#ibcon#read 3, iclass 21, count 0 2006.245.07:34:40.49#ibcon#about to read 4, iclass 21, count 0 2006.245.07:34:40.49#ibcon#read 4, iclass 21, count 0 2006.245.07:34:40.49#ibcon#about to read 5, iclass 21, count 0 2006.245.07:34:40.49#ibcon#read 5, iclass 21, count 0 2006.245.07:34:40.49#ibcon#about to read 6, iclass 21, count 0 2006.245.07:34:40.49#ibcon#read 6, iclass 21, count 0 2006.245.07:34:40.49#ibcon#end of sib2, iclass 21, count 0 2006.245.07:34:40.49#ibcon#*after write, iclass 21, count 0 2006.245.07:34:40.49#ibcon#*before return 0, iclass 21, count 0 2006.245.07:34:40.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:40.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:40.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:34:40.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:34:40.49$vc4f8/valo=3,672.99 2006.245.07:34:40.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.07:34:40.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.07:34:40.49#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:40.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:40.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:40.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:40.49#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:34:40.49#ibcon#first serial, iclass 23, count 0 2006.245.07:34:40.49#ibcon#enter sib2, iclass 23, count 0 2006.245.07:34:40.49#ibcon#flushed, iclass 23, count 0 2006.245.07:34:40.49#ibcon#about to write, iclass 23, count 0 2006.245.07:34:40.49#ibcon#wrote, iclass 23, count 0 2006.245.07:34:40.49#ibcon#about to read 3, iclass 23, count 0 2006.245.07:34:40.52#ibcon#read 3, iclass 23, count 0 2006.245.07:34:40.52#ibcon#about to read 4, iclass 23, count 0 2006.245.07:34:40.52#ibcon#read 4, iclass 23, count 0 2006.245.07:34:40.52#ibcon#about to read 5, iclass 23, count 0 2006.245.07:34:40.52#ibcon#read 5, iclass 23, count 0 2006.245.07:34:40.52#ibcon#about to read 6, iclass 23, count 0 2006.245.07:34:40.52#ibcon#read 6, iclass 23, count 0 2006.245.07:34:40.52#ibcon#end of sib2, iclass 23, count 0 2006.245.07:34:40.52#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:34:40.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:34:40.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:34:40.52#ibcon#*before write, iclass 23, count 0 2006.245.07:34:40.52#ibcon#enter sib2, iclass 23, count 0 2006.245.07:34:40.52#ibcon#flushed, iclass 23, count 0 2006.245.07:34:40.52#ibcon#about to write, iclass 23, count 0 2006.245.07:34:40.52#ibcon#wrote, iclass 23, count 0 2006.245.07:34:40.52#ibcon#about to read 3, iclass 23, count 0 2006.245.07:34:40.56#ibcon#read 3, iclass 23, count 0 2006.245.07:34:40.56#ibcon#about to read 4, iclass 23, count 0 2006.245.07:34:40.56#ibcon#read 4, iclass 23, count 0 2006.245.07:34:40.56#ibcon#about to read 5, iclass 23, count 0 2006.245.07:34:40.56#ibcon#read 5, iclass 23, count 0 2006.245.07:34:40.56#ibcon#about to read 6, iclass 23, count 0 2006.245.07:34:40.56#ibcon#read 6, iclass 23, count 0 2006.245.07:34:40.56#ibcon#end of sib2, iclass 23, count 0 2006.245.07:34:40.56#ibcon#*after write, iclass 23, count 0 2006.245.07:34:40.56#ibcon#*before return 0, iclass 23, count 0 2006.245.07:34:40.56#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:40.56#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:40.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:34:40.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:34:40.56$vc4f8/va=3,6 2006.245.07:34:40.56#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.07:34:40.56#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.07:34:40.56#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:40.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:40.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:40.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:40.61#ibcon#enter wrdev, iclass 25, count 2 2006.245.07:34:40.61#ibcon#first serial, iclass 25, count 2 2006.245.07:34:40.61#ibcon#enter sib2, iclass 25, count 2 2006.245.07:34:40.61#ibcon#flushed, iclass 25, count 2 2006.245.07:34:40.61#ibcon#about to write, iclass 25, count 2 2006.245.07:34:40.61#ibcon#wrote, iclass 25, count 2 2006.245.07:34:40.61#ibcon#about to read 3, iclass 25, count 2 2006.245.07:34:40.63#ibcon#read 3, iclass 25, count 2 2006.245.07:34:40.63#ibcon#about to read 4, iclass 25, count 2 2006.245.07:34:40.63#ibcon#read 4, iclass 25, count 2 2006.245.07:34:40.63#ibcon#about to read 5, iclass 25, count 2 2006.245.07:34:40.63#ibcon#read 5, iclass 25, count 2 2006.245.07:34:40.63#ibcon#about to read 6, iclass 25, count 2 2006.245.07:34:40.63#ibcon#read 6, iclass 25, count 2 2006.245.07:34:40.63#ibcon#end of sib2, iclass 25, count 2 2006.245.07:34:40.63#ibcon#*mode == 0, iclass 25, count 2 2006.245.07:34:40.63#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.07:34:40.63#ibcon#[25=AT03-06\r\n] 2006.245.07:34:40.63#ibcon#*before write, iclass 25, count 2 2006.245.07:34:40.63#ibcon#enter sib2, iclass 25, count 2 2006.245.07:34:40.63#ibcon#flushed, iclass 25, count 2 2006.245.07:34:40.63#ibcon#about to write, iclass 25, count 2 2006.245.07:34:40.63#ibcon#wrote, iclass 25, count 2 2006.245.07:34:40.63#ibcon#about to read 3, iclass 25, count 2 2006.245.07:34:40.66#ibcon#read 3, iclass 25, count 2 2006.245.07:34:40.66#ibcon#about to read 4, iclass 25, count 2 2006.245.07:34:40.66#ibcon#read 4, iclass 25, count 2 2006.245.07:34:40.66#ibcon#about to read 5, iclass 25, count 2 2006.245.07:34:40.66#ibcon#read 5, iclass 25, count 2 2006.245.07:34:40.66#ibcon#about to read 6, iclass 25, count 2 2006.245.07:34:40.66#ibcon#read 6, iclass 25, count 2 2006.245.07:34:40.66#ibcon#end of sib2, iclass 25, count 2 2006.245.07:34:40.66#ibcon#*after write, iclass 25, count 2 2006.245.07:34:40.66#ibcon#*before return 0, iclass 25, count 2 2006.245.07:34:40.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:40.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:40.66#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.07:34:40.66#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:40.66#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:40.78#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:40.78#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:40.78#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:34:40.78#ibcon#first serial, iclass 25, count 0 2006.245.07:34:40.78#ibcon#enter sib2, iclass 25, count 0 2006.245.07:34:40.78#ibcon#flushed, iclass 25, count 0 2006.245.07:34:40.78#ibcon#about to write, iclass 25, count 0 2006.245.07:34:40.78#ibcon#wrote, iclass 25, count 0 2006.245.07:34:40.78#ibcon#about to read 3, iclass 25, count 0 2006.245.07:34:40.80#ibcon#read 3, iclass 25, count 0 2006.245.07:34:40.80#ibcon#about to read 4, iclass 25, count 0 2006.245.07:34:40.80#ibcon#read 4, iclass 25, count 0 2006.245.07:34:40.80#ibcon#about to read 5, iclass 25, count 0 2006.245.07:34:40.80#ibcon#read 5, iclass 25, count 0 2006.245.07:34:40.80#ibcon#about to read 6, iclass 25, count 0 2006.245.07:34:40.80#ibcon#read 6, iclass 25, count 0 2006.245.07:34:40.80#ibcon#end of sib2, iclass 25, count 0 2006.245.07:34:40.80#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:34:40.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:34:40.80#ibcon#[25=USB\r\n] 2006.245.07:34:40.80#ibcon#*before write, iclass 25, count 0 2006.245.07:34:40.80#ibcon#enter sib2, iclass 25, count 0 2006.245.07:34:40.80#ibcon#flushed, iclass 25, count 0 2006.245.07:34:40.80#ibcon#about to write, iclass 25, count 0 2006.245.07:34:40.80#ibcon#wrote, iclass 25, count 0 2006.245.07:34:40.80#ibcon#about to read 3, iclass 25, count 0 2006.245.07:34:40.83#ibcon#read 3, iclass 25, count 0 2006.245.07:34:40.83#ibcon#about to read 4, iclass 25, count 0 2006.245.07:34:40.83#ibcon#read 4, iclass 25, count 0 2006.245.07:34:40.83#ibcon#about to read 5, iclass 25, count 0 2006.245.07:34:40.83#ibcon#read 5, iclass 25, count 0 2006.245.07:34:40.83#ibcon#about to read 6, iclass 25, count 0 2006.245.07:34:40.83#ibcon#read 6, iclass 25, count 0 2006.245.07:34:40.83#ibcon#end of sib2, iclass 25, count 0 2006.245.07:34:40.83#ibcon#*after write, iclass 25, count 0 2006.245.07:34:40.83#ibcon#*before return 0, iclass 25, count 0 2006.245.07:34:40.83#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:40.83#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:40.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:34:40.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:34:40.83$vc4f8/valo=4,832.99 2006.245.07:34:40.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:34:40.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:34:40.83#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:40.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:40.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:40.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:40.83#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:34:40.83#ibcon#first serial, iclass 27, count 0 2006.245.07:34:40.83#ibcon#enter sib2, iclass 27, count 0 2006.245.07:34:40.83#ibcon#flushed, iclass 27, count 0 2006.245.07:34:40.83#ibcon#about to write, iclass 27, count 0 2006.245.07:34:40.83#ibcon#wrote, iclass 27, count 0 2006.245.07:34:40.83#ibcon#about to read 3, iclass 27, count 0 2006.245.07:34:40.85#ibcon#read 3, iclass 27, count 0 2006.245.07:34:40.85#ibcon#about to read 4, iclass 27, count 0 2006.245.07:34:40.85#ibcon#read 4, iclass 27, count 0 2006.245.07:34:40.85#ibcon#about to read 5, iclass 27, count 0 2006.245.07:34:40.85#ibcon#read 5, iclass 27, count 0 2006.245.07:34:40.85#ibcon#about to read 6, iclass 27, count 0 2006.245.07:34:40.85#ibcon#read 6, iclass 27, count 0 2006.245.07:34:40.85#ibcon#end of sib2, iclass 27, count 0 2006.245.07:34:40.85#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:34:40.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:34:40.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:34:40.85#ibcon#*before write, iclass 27, count 0 2006.245.07:34:40.85#ibcon#enter sib2, iclass 27, count 0 2006.245.07:34:40.85#ibcon#flushed, iclass 27, count 0 2006.245.07:34:40.85#ibcon#about to write, iclass 27, count 0 2006.245.07:34:40.85#ibcon#wrote, iclass 27, count 0 2006.245.07:34:40.85#ibcon#about to read 3, iclass 27, count 0 2006.245.07:34:40.89#ibcon#read 3, iclass 27, count 0 2006.245.07:34:40.89#ibcon#about to read 4, iclass 27, count 0 2006.245.07:34:40.89#ibcon#read 4, iclass 27, count 0 2006.245.07:34:40.89#ibcon#about to read 5, iclass 27, count 0 2006.245.07:34:40.89#ibcon#read 5, iclass 27, count 0 2006.245.07:34:40.89#ibcon#about to read 6, iclass 27, count 0 2006.245.07:34:40.89#ibcon#read 6, iclass 27, count 0 2006.245.07:34:40.89#ibcon#end of sib2, iclass 27, count 0 2006.245.07:34:40.89#ibcon#*after write, iclass 27, count 0 2006.245.07:34:40.89#ibcon#*before return 0, iclass 27, count 0 2006.245.07:34:40.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:40.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:40.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:34:40.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:34:40.89$vc4f8/va=4,7 2006.245.07:34:40.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:34:40.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:34:40.89#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:40.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:40.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:40.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:40.95#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:34:40.95#ibcon#first serial, iclass 29, count 2 2006.245.07:34:40.95#ibcon#enter sib2, iclass 29, count 2 2006.245.07:34:40.95#ibcon#flushed, iclass 29, count 2 2006.245.07:34:40.95#ibcon#about to write, iclass 29, count 2 2006.245.07:34:40.95#ibcon#wrote, iclass 29, count 2 2006.245.07:34:40.95#ibcon#about to read 3, iclass 29, count 2 2006.245.07:34:40.97#ibcon#read 3, iclass 29, count 2 2006.245.07:34:40.97#ibcon#about to read 4, iclass 29, count 2 2006.245.07:34:40.97#ibcon#read 4, iclass 29, count 2 2006.245.07:34:40.97#ibcon#about to read 5, iclass 29, count 2 2006.245.07:34:40.97#ibcon#read 5, iclass 29, count 2 2006.245.07:34:40.97#ibcon#about to read 6, iclass 29, count 2 2006.245.07:34:40.97#ibcon#read 6, iclass 29, count 2 2006.245.07:34:40.97#ibcon#end of sib2, iclass 29, count 2 2006.245.07:34:40.97#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:34:40.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:34:40.97#ibcon#[25=AT04-07\r\n] 2006.245.07:34:40.97#ibcon#*before write, iclass 29, count 2 2006.245.07:34:40.97#ibcon#enter sib2, iclass 29, count 2 2006.245.07:34:40.97#ibcon#flushed, iclass 29, count 2 2006.245.07:34:40.97#ibcon#about to write, iclass 29, count 2 2006.245.07:34:40.97#ibcon#wrote, iclass 29, count 2 2006.245.07:34:40.97#ibcon#about to read 3, iclass 29, count 2 2006.245.07:34:41.00#ibcon#read 3, iclass 29, count 2 2006.245.07:34:41.00#ibcon#about to read 4, iclass 29, count 2 2006.245.07:34:41.00#ibcon#read 4, iclass 29, count 2 2006.245.07:34:41.00#ibcon#about to read 5, iclass 29, count 2 2006.245.07:34:41.00#ibcon#read 5, iclass 29, count 2 2006.245.07:34:41.00#ibcon#about to read 6, iclass 29, count 2 2006.245.07:34:41.00#ibcon#read 6, iclass 29, count 2 2006.245.07:34:41.00#ibcon#end of sib2, iclass 29, count 2 2006.245.07:34:41.00#ibcon#*after write, iclass 29, count 2 2006.245.07:34:41.00#ibcon#*before return 0, iclass 29, count 2 2006.245.07:34:41.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:41.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:41.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:34:41.00#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:41.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:41.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:41.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:41.12#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:34:41.12#ibcon#first serial, iclass 29, count 0 2006.245.07:34:41.12#ibcon#enter sib2, iclass 29, count 0 2006.245.07:34:41.12#ibcon#flushed, iclass 29, count 0 2006.245.07:34:41.12#ibcon#about to write, iclass 29, count 0 2006.245.07:34:41.12#ibcon#wrote, iclass 29, count 0 2006.245.07:34:41.12#ibcon#about to read 3, iclass 29, count 0 2006.245.07:34:41.14#ibcon#read 3, iclass 29, count 0 2006.245.07:34:41.14#ibcon#about to read 4, iclass 29, count 0 2006.245.07:34:41.14#ibcon#read 4, iclass 29, count 0 2006.245.07:34:41.14#ibcon#about to read 5, iclass 29, count 0 2006.245.07:34:41.14#ibcon#read 5, iclass 29, count 0 2006.245.07:34:41.14#ibcon#about to read 6, iclass 29, count 0 2006.245.07:34:41.14#ibcon#read 6, iclass 29, count 0 2006.245.07:34:41.14#ibcon#end of sib2, iclass 29, count 0 2006.245.07:34:41.14#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:34:41.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:34:41.14#ibcon#[25=USB\r\n] 2006.245.07:34:41.14#ibcon#*before write, iclass 29, count 0 2006.245.07:34:41.14#ibcon#enter sib2, iclass 29, count 0 2006.245.07:34:41.14#ibcon#flushed, iclass 29, count 0 2006.245.07:34:41.14#ibcon#about to write, iclass 29, count 0 2006.245.07:34:41.14#ibcon#wrote, iclass 29, count 0 2006.245.07:34:41.14#ibcon#about to read 3, iclass 29, count 0 2006.245.07:34:41.17#ibcon#read 3, iclass 29, count 0 2006.245.07:34:41.17#ibcon#about to read 4, iclass 29, count 0 2006.245.07:34:41.17#ibcon#read 4, iclass 29, count 0 2006.245.07:34:41.17#ibcon#about to read 5, iclass 29, count 0 2006.245.07:34:41.17#ibcon#read 5, iclass 29, count 0 2006.245.07:34:41.17#ibcon#about to read 6, iclass 29, count 0 2006.245.07:34:41.17#ibcon#read 6, iclass 29, count 0 2006.245.07:34:41.17#ibcon#end of sib2, iclass 29, count 0 2006.245.07:34:41.17#ibcon#*after write, iclass 29, count 0 2006.245.07:34:41.17#ibcon#*before return 0, iclass 29, count 0 2006.245.07:34:41.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:41.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:41.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:34:41.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:34:41.17$vc4f8/valo=5,652.99 2006.245.07:34:41.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:34:41.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:34:41.17#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:41.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:41.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:41.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:41.17#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:34:41.17#ibcon#first serial, iclass 31, count 0 2006.245.07:34:41.17#ibcon#enter sib2, iclass 31, count 0 2006.245.07:34:41.17#ibcon#flushed, iclass 31, count 0 2006.245.07:34:41.17#ibcon#about to write, iclass 31, count 0 2006.245.07:34:41.17#ibcon#wrote, iclass 31, count 0 2006.245.07:34:41.17#ibcon#about to read 3, iclass 31, count 0 2006.245.07:34:41.19#ibcon#read 3, iclass 31, count 0 2006.245.07:34:41.19#ibcon#about to read 4, iclass 31, count 0 2006.245.07:34:41.19#ibcon#read 4, iclass 31, count 0 2006.245.07:34:41.19#ibcon#about to read 5, iclass 31, count 0 2006.245.07:34:41.19#ibcon#read 5, iclass 31, count 0 2006.245.07:34:41.19#ibcon#about to read 6, iclass 31, count 0 2006.245.07:34:41.19#ibcon#read 6, iclass 31, count 0 2006.245.07:34:41.19#ibcon#end of sib2, iclass 31, count 0 2006.245.07:34:41.19#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:34:41.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:34:41.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:34:41.19#ibcon#*before write, iclass 31, count 0 2006.245.07:34:41.19#ibcon#enter sib2, iclass 31, count 0 2006.245.07:34:41.19#ibcon#flushed, iclass 31, count 0 2006.245.07:34:41.19#ibcon#about to write, iclass 31, count 0 2006.245.07:34:41.19#ibcon#wrote, iclass 31, count 0 2006.245.07:34:41.19#ibcon#about to read 3, iclass 31, count 0 2006.245.07:34:41.23#ibcon#read 3, iclass 31, count 0 2006.245.07:34:41.23#ibcon#about to read 4, iclass 31, count 0 2006.245.07:34:41.23#ibcon#read 4, iclass 31, count 0 2006.245.07:34:41.23#ibcon#about to read 5, iclass 31, count 0 2006.245.07:34:41.23#ibcon#read 5, iclass 31, count 0 2006.245.07:34:41.23#ibcon#about to read 6, iclass 31, count 0 2006.245.07:34:41.23#ibcon#read 6, iclass 31, count 0 2006.245.07:34:41.23#ibcon#end of sib2, iclass 31, count 0 2006.245.07:34:41.23#ibcon#*after write, iclass 31, count 0 2006.245.07:34:41.23#ibcon#*before return 0, iclass 31, count 0 2006.245.07:34:41.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:41.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:41.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:34:41.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:34:41.23$vc4f8/va=5,7 2006.245.07:34:41.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:34:41.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:34:41.23#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:41.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:41.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:41.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:41.29#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:34:41.29#ibcon#first serial, iclass 33, count 2 2006.245.07:34:41.29#ibcon#enter sib2, iclass 33, count 2 2006.245.07:34:41.29#ibcon#flushed, iclass 33, count 2 2006.245.07:34:41.29#ibcon#about to write, iclass 33, count 2 2006.245.07:34:41.29#ibcon#wrote, iclass 33, count 2 2006.245.07:34:41.29#ibcon#about to read 3, iclass 33, count 2 2006.245.07:34:41.31#ibcon#read 3, iclass 33, count 2 2006.245.07:34:41.31#ibcon#about to read 4, iclass 33, count 2 2006.245.07:34:41.31#ibcon#read 4, iclass 33, count 2 2006.245.07:34:41.31#ibcon#about to read 5, iclass 33, count 2 2006.245.07:34:41.31#ibcon#read 5, iclass 33, count 2 2006.245.07:34:41.31#ibcon#about to read 6, iclass 33, count 2 2006.245.07:34:41.31#ibcon#read 6, iclass 33, count 2 2006.245.07:34:41.31#ibcon#end of sib2, iclass 33, count 2 2006.245.07:34:41.31#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:34:41.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:34:41.31#ibcon#[25=AT05-07\r\n] 2006.245.07:34:41.31#ibcon#*before write, iclass 33, count 2 2006.245.07:34:41.31#ibcon#enter sib2, iclass 33, count 2 2006.245.07:34:41.31#ibcon#flushed, iclass 33, count 2 2006.245.07:34:41.31#ibcon#about to write, iclass 33, count 2 2006.245.07:34:41.31#ibcon#wrote, iclass 33, count 2 2006.245.07:34:41.31#ibcon#about to read 3, iclass 33, count 2 2006.245.07:34:41.34#ibcon#read 3, iclass 33, count 2 2006.245.07:34:41.34#ibcon#about to read 4, iclass 33, count 2 2006.245.07:34:41.34#ibcon#read 4, iclass 33, count 2 2006.245.07:34:41.34#ibcon#about to read 5, iclass 33, count 2 2006.245.07:34:41.34#ibcon#read 5, iclass 33, count 2 2006.245.07:34:41.34#ibcon#about to read 6, iclass 33, count 2 2006.245.07:34:41.34#ibcon#read 6, iclass 33, count 2 2006.245.07:34:41.34#ibcon#end of sib2, iclass 33, count 2 2006.245.07:34:41.34#ibcon#*after write, iclass 33, count 2 2006.245.07:34:41.34#ibcon#*before return 0, iclass 33, count 2 2006.245.07:34:41.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:41.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:41.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:34:41.34#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:41.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:41.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:41.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:41.46#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:34:41.46#ibcon#first serial, iclass 33, count 0 2006.245.07:34:41.46#ibcon#enter sib2, iclass 33, count 0 2006.245.07:34:41.46#ibcon#flushed, iclass 33, count 0 2006.245.07:34:41.46#ibcon#about to write, iclass 33, count 0 2006.245.07:34:41.46#ibcon#wrote, iclass 33, count 0 2006.245.07:34:41.46#ibcon#about to read 3, iclass 33, count 0 2006.245.07:34:41.48#ibcon#read 3, iclass 33, count 0 2006.245.07:34:41.48#ibcon#about to read 4, iclass 33, count 0 2006.245.07:34:41.48#ibcon#read 4, iclass 33, count 0 2006.245.07:34:41.48#ibcon#about to read 5, iclass 33, count 0 2006.245.07:34:41.48#ibcon#read 5, iclass 33, count 0 2006.245.07:34:41.48#ibcon#about to read 6, iclass 33, count 0 2006.245.07:34:41.48#ibcon#read 6, iclass 33, count 0 2006.245.07:34:41.48#ibcon#end of sib2, iclass 33, count 0 2006.245.07:34:41.48#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:34:41.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:34:41.48#ibcon#[25=USB\r\n] 2006.245.07:34:41.48#ibcon#*before write, iclass 33, count 0 2006.245.07:34:41.48#ibcon#enter sib2, iclass 33, count 0 2006.245.07:34:41.48#ibcon#flushed, iclass 33, count 0 2006.245.07:34:41.48#ibcon#about to write, iclass 33, count 0 2006.245.07:34:41.48#ibcon#wrote, iclass 33, count 0 2006.245.07:34:41.48#ibcon#about to read 3, iclass 33, count 0 2006.245.07:34:41.51#ibcon#read 3, iclass 33, count 0 2006.245.07:34:41.51#ibcon#about to read 4, iclass 33, count 0 2006.245.07:34:41.51#ibcon#read 4, iclass 33, count 0 2006.245.07:34:41.51#ibcon#about to read 5, iclass 33, count 0 2006.245.07:34:41.51#ibcon#read 5, iclass 33, count 0 2006.245.07:34:41.51#ibcon#about to read 6, iclass 33, count 0 2006.245.07:34:41.51#ibcon#read 6, iclass 33, count 0 2006.245.07:34:41.51#ibcon#end of sib2, iclass 33, count 0 2006.245.07:34:41.51#ibcon#*after write, iclass 33, count 0 2006.245.07:34:41.51#ibcon#*before return 0, iclass 33, count 0 2006.245.07:34:41.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:41.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:41.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:34:41.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:34:41.51$vc4f8/valo=6,772.99 2006.245.07:34:41.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:34:41.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:34:41.51#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:41.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:34:41.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:34:41.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:34:41.51#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:34:41.51#ibcon#first serial, iclass 35, count 0 2006.245.07:34:41.51#ibcon#enter sib2, iclass 35, count 0 2006.245.07:34:41.51#ibcon#flushed, iclass 35, count 0 2006.245.07:34:41.51#ibcon#about to write, iclass 35, count 0 2006.245.07:34:41.51#ibcon#wrote, iclass 35, count 0 2006.245.07:34:41.51#ibcon#about to read 3, iclass 35, count 0 2006.245.07:34:41.53#ibcon#read 3, iclass 35, count 0 2006.245.07:34:41.53#ibcon#about to read 4, iclass 35, count 0 2006.245.07:34:41.53#ibcon#read 4, iclass 35, count 0 2006.245.07:34:41.53#ibcon#about to read 5, iclass 35, count 0 2006.245.07:34:41.53#ibcon#read 5, iclass 35, count 0 2006.245.07:34:41.53#ibcon#about to read 6, iclass 35, count 0 2006.245.07:34:41.53#ibcon#read 6, iclass 35, count 0 2006.245.07:34:41.53#ibcon#end of sib2, iclass 35, count 0 2006.245.07:34:41.53#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:34:41.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:34:41.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:34:41.53#ibcon#*before write, iclass 35, count 0 2006.245.07:34:41.53#ibcon#enter sib2, iclass 35, count 0 2006.245.07:34:41.53#ibcon#flushed, iclass 35, count 0 2006.245.07:34:41.53#ibcon#about to write, iclass 35, count 0 2006.245.07:34:41.53#ibcon#wrote, iclass 35, count 0 2006.245.07:34:41.53#ibcon#about to read 3, iclass 35, count 0 2006.245.07:34:41.57#ibcon#read 3, iclass 35, count 0 2006.245.07:34:41.57#ibcon#about to read 4, iclass 35, count 0 2006.245.07:34:41.57#ibcon#read 4, iclass 35, count 0 2006.245.07:34:41.57#ibcon#about to read 5, iclass 35, count 0 2006.245.07:34:41.57#ibcon#read 5, iclass 35, count 0 2006.245.07:34:41.57#ibcon#about to read 6, iclass 35, count 0 2006.245.07:34:41.57#ibcon#read 6, iclass 35, count 0 2006.245.07:34:41.57#ibcon#end of sib2, iclass 35, count 0 2006.245.07:34:41.57#ibcon#*after write, iclass 35, count 0 2006.245.07:34:41.57#ibcon#*before return 0, iclass 35, count 0 2006.245.07:34:41.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:34:41.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:34:41.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:34:41.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:34:41.57$vc4f8/va=6,7 2006.245.07:34:41.57#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:34:41.57#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:34:41.57#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:41.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:34:41.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:34:41.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:34:41.64#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:34:41.64#ibcon#first serial, iclass 37, count 2 2006.245.07:34:41.64#ibcon#enter sib2, iclass 37, count 2 2006.245.07:34:41.64#ibcon#flushed, iclass 37, count 2 2006.245.07:34:41.64#ibcon#about to write, iclass 37, count 2 2006.245.07:34:41.64#ibcon#wrote, iclass 37, count 2 2006.245.07:34:41.64#ibcon#about to read 3, iclass 37, count 2 2006.245.07:34:41.65#ibcon#read 3, iclass 37, count 2 2006.245.07:34:41.65#ibcon#about to read 4, iclass 37, count 2 2006.245.07:34:41.65#ibcon#read 4, iclass 37, count 2 2006.245.07:34:41.65#ibcon#about to read 5, iclass 37, count 2 2006.245.07:34:41.65#ibcon#read 5, iclass 37, count 2 2006.245.07:34:41.65#ibcon#about to read 6, iclass 37, count 2 2006.245.07:34:41.65#ibcon#read 6, iclass 37, count 2 2006.245.07:34:41.65#ibcon#end of sib2, iclass 37, count 2 2006.245.07:34:41.65#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:34:41.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:34:41.65#ibcon#[25=AT06-07\r\n] 2006.245.07:34:41.65#ibcon#*before write, iclass 37, count 2 2006.245.07:34:41.65#ibcon#enter sib2, iclass 37, count 2 2006.245.07:34:41.65#ibcon#flushed, iclass 37, count 2 2006.245.07:34:41.65#ibcon#about to write, iclass 37, count 2 2006.245.07:34:41.65#ibcon#wrote, iclass 37, count 2 2006.245.07:34:41.65#ibcon#about to read 3, iclass 37, count 2 2006.245.07:34:41.68#ibcon#read 3, iclass 37, count 2 2006.245.07:34:41.68#ibcon#about to read 4, iclass 37, count 2 2006.245.07:34:41.68#ibcon#read 4, iclass 37, count 2 2006.245.07:34:41.68#ibcon#about to read 5, iclass 37, count 2 2006.245.07:34:41.68#ibcon#read 5, iclass 37, count 2 2006.245.07:34:41.68#ibcon#about to read 6, iclass 37, count 2 2006.245.07:34:41.68#ibcon#read 6, iclass 37, count 2 2006.245.07:34:41.68#ibcon#end of sib2, iclass 37, count 2 2006.245.07:34:41.68#ibcon#*after write, iclass 37, count 2 2006.245.07:34:41.68#ibcon#*before return 0, iclass 37, count 2 2006.245.07:34:41.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:34:41.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:34:41.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:34:41.68#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:41.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:34:41.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:34:41.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:34:41.80#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:34:41.80#ibcon#first serial, iclass 37, count 0 2006.245.07:34:41.80#ibcon#enter sib2, iclass 37, count 0 2006.245.07:34:41.80#ibcon#flushed, iclass 37, count 0 2006.245.07:34:41.80#ibcon#about to write, iclass 37, count 0 2006.245.07:34:41.80#ibcon#wrote, iclass 37, count 0 2006.245.07:34:41.80#ibcon#about to read 3, iclass 37, count 0 2006.245.07:34:41.82#ibcon#read 3, iclass 37, count 0 2006.245.07:34:41.82#ibcon#about to read 4, iclass 37, count 0 2006.245.07:34:41.82#ibcon#read 4, iclass 37, count 0 2006.245.07:34:41.82#ibcon#about to read 5, iclass 37, count 0 2006.245.07:34:41.82#ibcon#read 5, iclass 37, count 0 2006.245.07:34:41.82#ibcon#about to read 6, iclass 37, count 0 2006.245.07:34:41.82#ibcon#read 6, iclass 37, count 0 2006.245.07:34:41.82#ibcon#end of sib2, iclass 37, count 0 2006.245.07:34:41.82#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:34:41.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:34:41.82#ibcon#[25=USB\r\n] 2006.245.07:34:41.82#ibcon#*before write, iclass 37, count 0 2006.245.07:34:41.82#ibcon#enter sib2, iclass 37, count 0 2006.245.07:34:41.82#ibcon#flushed, iclass 37, count 0 2006.245.07:34:41.82#ibcon#about to write, iclass 37, count 0 2006.245.07:34:41.82#ibcon#wrote, iclass 37, count 0 2006.245.07:34:41.82#ibcon#about to read 3, iclass 37, count 0 2006.245.07:34:41.85#ibcon#read 3, iclass 37, count 0 2006.245.07:34:41.85#ibcon#about to read 4, iclass 37, count 0 2006.245.07:34:41.85#ibcon#read 4, iclass 37, count 0 2006.245.07:34:41.85#ibcon#about to read 5, iclass 37, count 0 2006.245.07:34:41.85#ibcon#read 5, iclass 37, count 0 2006.245.07:34:41.85#ibcon#about to read 6, iclass 37, count 0 2006.245.07:34:41.85#ibcon#read 6, iclass 37, count 0 2006.245.07:34:41.85#ibcon#end of sib2, iclass 37, count 0 2006.245.07:34:41.85#ibcon#*after write, iclass 37, count 0 2006.245.07:34:41.85#ibcon#*before return 0, iclass 37, count 0 2006.245.07:34:41.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:34:41.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:34:41.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:34:41.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:34:41.85$vc4f8/valo=7,832.99 2006.245.07:34:41.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:34:41.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:34:41.85#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:41.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:34:41.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:34:41.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:34:41.85#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:34:41.85#ibcon#first serial, iclass 39, count 0 2006.245.07:34:41.85#ibcon#enter sib2, iclass 39, count 0 2006.245.07:34:41.85#ibcon#flushed, iclass 39, count 0 2006.245.07:34:41.85#ibcon#about to write, iclass 39, count 0 2006.245.07:34:41.85#ibcon#wrote, iclass 39, count 0 2006.245.07:34:41.85#ibcon#about to read 3, iclass 39, count 0 2006.245.07:34:41.87#ibcon#read 3, iclass 39, count 0 2006.245.07:34:41.87#ibcon#about to read 4, iclass 39, count 0 2006.245.07:34:41.87#ibcon#read 4, iclass 39, count 0 2006.245.07:34:41.87#ibcon#about to read 5, iclass 39, count 0 2006.245.07:34:41.87#ibcon#read 5, iclass 39, count 0 2006.245.07:34:41.87#ibcon#about to read 6, iclass 39, count 0 2006.245.07:34:41.87#ibcon#read 6, iclass 39, count 0 2006.245.07:34:41.87#ibcon#end of sib2, iclass 39, count 0 2006.245.07:34:41.87#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:34:41.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:34:41.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:34:41.87#ibcon#*before write, iclass 39, count 0 2006.245.07:34:41.87#ibcon#enter sib2, iclass 39, count 0 2006.245.07:34:41.87#ibcon#flushed, iclass 39, count 0 2006.245.07:34:41.87#ibcon#about to write, iclass 39, count 0 2006.245.07:34:41.87#ibcon#wrote, iclass 39, count 0 2006.245.07:34:41.87#ibcon#about to read 3, iclass 39, count 0 2006.245.07:34:41.91#ibcon#read 3, iclass 39, count 0 2006.245.07:34:41.91#ibcon#about to read 4, iclass 39, count 0 2006.245.07:34:41.91#ibcon#read 4, iclass 39, count 0 2006.245.07:34:41.91#ibcon#about to read 5, iclass 39, count 0 2006.245.07:34:41.91#ibcon#read 5, iclass 39, count 0 2006.245.07:34:41.91#ibcon#about to read 6, iclass 39, count 0 2006.245.07:34:41.91#ibcon#read 6, iclass 39, count 0 2006.245.07:34:41.91#ibcon#end of sib2, iclass 39, count 0 2006.245.07:34:41.91#ibcon#*after write, iclass 39, count 0 2006.245.07:34:41.91#ibcon#*before return 0, iclass 39, count 0 2006.245.07:34:41.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:34:41.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:34:41.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:34:41.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:34:41.91$vc4f8/va=7,7 2006.245.07:34:41.91#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:34:41.91#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:34:41.91#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:41.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:34:41.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:34:41.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:34:41.97#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:34:41.97#ibcon#first serial, iclass 3, count 2 2006.245.07:34:41.97#ibcon#enter sib2, iclass 3, count 2 2006.245.07:34:41.97#ibcon#flushed, iclass 3, count 2 2006.245.07:34:41.97#ibcon#about to write, iclass 3, count 2 2006.245.07:34:41.97#ibcon#wrote, iclass 3, count 2 2006.245.07:34:41.97#ibcon#about to read 3, iclass 3, count 2 2006.245.07:34:41.99#ibcon#read 3, iclass 3, count 2 2006.245.07:34:41.99#ibcon#about to read 4, iclass 3, count 2 2006.245.07:34:41.99#ibcon#read 4, iclass 3, count 2 2006.245.07:34:41.99#ibcon#about to read 5, iclass 3, count 2 2006.245.07:34:41.99#ibcon#read 5, iclass 3, count 2 2006.245.07:34:41.99#ibcon#about to read 6, iclass 3, count 2 2006.245.07:34:41.99#ibcon#read 6, iclass 3, count 2 2006.245.07:34:41.99#ibcon#end of sib2, iclass 3, count 2 2006.245.07:34:41.99#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:34:41.99#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:34:41.99#ibcon#[25=AT07-07\r\n] 2006.245.07:34:41.99#ibcon#*before write, iclass 3, count 2 2006.245.07:34:41.99#ibcon#enter sib2, iclass 3, count 2 2006.245.07:34:41.99#ibcon#flushed, iclass 3, count 2 2006.245.07:34:41.99#ibcon#about to write, iclass 3, count 2 2006.245.07:34:41.99#ibcon#wrote, iclass 3, count 2 2006.245.07:34:41.99#ibcon#about to read 3, iclass 3, count 2 2006.245.07:34:42.02#ibcon#read 3, iclass 3, count 2 2006.245.07:34:42.02#ibcon#about to read 4, iclass 3, count 2 2006.245.07:34:42.02#ibcon#read 4, iclass 3, count 2 2006.245.07:34:42.02#ibcon#about to read 5, iclass 3, count 2 2006.245.07:34:42.02#ibcon#read 5, iclass 3, count 2 2006.245.07:34:42.02#ibcon#about to read 6, iclass 3, count 2 2006.245.07:34:42.02#ibcon#read 6, iclass 3, count 2 2006.245.07:34:42.02#ibcon#end of sib2, iclass 3, count 2 2006.245.07:34:42.02#ibcon#*after write, iclass 3, count 2 2006.245.07:34:42.02#ibcon#*before return 0, iclass 3, count 2 2006.245.07:34:42.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:34:42.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:34:42.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:34:42.02#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:42.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:34:42.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:34:42.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:34:42.14#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:34:42.14#ibcon#first serial, iclass 3, count 0 2006.245.07:34:42.14#ibcon#enter sib2, iclass 3, count 0 2006.245.07:34:42.14#ibcon#flushed, iclass 3, count 0 2006.245.07:34:42.14#ibcon#about to write, iclass 3, count 0 2006.245.07:34:42.14#ibcon#wrote, iclass 3, count 0 2006.245.07:34:42.14#ibcon#about to read 3, iclass 3, count 0 2006.245.07:34:42.16#ibcon#read 3, iclass 3, count 0 2006.245.07:34:42.16#ibcon#about to read 4, iclass 3, count 0 2006.245.07:34:42.16#ibcon#read 4, iclass 3, count 0 2006.245.07:34:42.16#ibcon#about to read 5, iclass 3, count 0 2006.245.07:34:42.16#ibcon#read 5, iclass 3, count 0 2006.245.07:34:42.16#ibcon#about to read 6, iclass 3, count 0 2006.245.07:34:42.16#ibcon#read 6, iclass 3, count 0 2006.245.07:34:42.16#ibcon#end of sib2, iclass 3, count 0 2006.245.07:34:42.16#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:34:42.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:34:42.16#ibcon#[25=USB\r\n] 2006.245.07:34:42.16#ibcon#*before write, iclass 3, count 0 2006.245.07:34:42.16#ibcon#enter sib2, iclass 3, count 0 2006.245.07:34:42.16#ibcon#flushed, iclass 3, count 0 2006.245.07:34:42.16#ibcon#about to write, iclass 3, count 0 2006.245.07:34:42.16#ibcon#wrote, iclass 3, count 0 2006.245.07:34:42.16#ibcon#about to read 3, iclass 3, count 0 2006.245.07:34:42.19#ibcon#read 3, iclass 3, count 0 2006.245.07:34:42.19#ibcon#about to read 4, iclass 3, count 0 2006.245.07:34:42.19#ibcon#read 4, iclass 3, count 0 2006.245.07:34:42.19#ibcon#about to read 5, iclass 3, count 0 2006.245.07:34:42.19#ibcon#read 5, iclass 3, count 0 2006.245.07:34:42.19#ibcon#about to read 6, iclass 3, count 0 2006.245.07:34:42.19#ibcon#read 6, iclass 3, count 0 2006.245.07:34:42.19#ibcon#end of sib2, iclass 3, count 0 2006.245.07:34:42.19#ibcon#*after write, iclass 3, count 0 2006.245.07:34:42.19#ibcon#*before return 0, iclass 3, count 0 2006.245.07:34:42.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:34:42.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:34:42.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:34:42.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:34:42.19$vc4f8/valo=8,852.99 2006.245.07:34:42.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:34:42.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:34:42.19#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:42.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:34:42.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:34:42.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:34:42.19#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:34:42.19#ibcon#first serial, iclass 5, count 0 2006.245.07:34:42.19#ibcon#enter sib2, iclass 5, count 0 2006.245.07:34:42.19#ibcon#flushed, iclass 5, count 0 2006.245.07:34:42.19#ibcon#about to write, iclass 5, count 0 2006.245.07:34:42.19#ibcon#wrote, iclass 5, count 0 2006.245.07:34:42.19#ibcon#about to read 3, iclass 5, count 0 2006.245.07:34:42.21#ibcon#read 3, iclass 5, count 0 2006.245.07:34:42.21#ibcon#about to read 4, iclass 5, count 0 2006.245.07:34:42.21#ibcon#read 4, iclass 5, count 0 2006.245.07:34:42.21#ibcon#about to read 5, iclass 5, count 0 2006.245.07:34:42.21#ibcon#read 5, iclass 5, count 0 2006.245.07:34:42.21#ibcon#about to read 6, iclass 5, count 0 2006.245.07:34:42.21#ibcon#read 6, iclass 5, count 0 2006.245.07:34:42.21#ibcon#end of sib2, iclass 5, count 0 2006.245.07:34:42.21#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:34:42.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:34:42.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:34:42.21#ibcon#*before write, iclass 5, count 0 2006.245.07:34:42.21#ibcon#enter sib2, iclass 5, count 0 2006.245.07:34:42.21#ibcon#flushed, iclass 5, count 0 2006.245.07:34:42.21#ibcon#about to write, iclass 5, count 0 2006.245.07:34:42.21#ibcon#wrote, iclass 5, count 0 2006.245.07:34:42.21#ibcon#about to read 3, iclass 5, count 0 2006.245.07:34:42.25#ibcon#read 3, iclass 5, count 0 2006.245.07:34:42.25#ibcon#about to read 4, iclass 5, count 0 2006.245.07:34:42.25#ibcon#read 4, iclass 5, count 0 2006.245.07:34:42.25#ibcon#about to read 5, iclass 5, count 0 2006.245.07:34:42.25#ibcon#read 5, iclass 5, count 0 2006.245.07:34:42.25#ibcon#about to read 6, iclass 5, count 0 2006.245.07:34:42.25#ibcon#read 6, iclass 5, count 0 2006.245.07:34:42.25#ibcon#end of sib2, iclass 5, count 0 2006.245.07:34:42.25#ibcon#*after write, iclass 5, count 0 2006.245.07:34:42.25#ibcon#*before return 0, iclass 5, count 0 2006.245.07:34:42.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:34:42.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:34:42.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:34:42.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:34:42.25$vc4f8/va=8,8 2006.245.07:34:42.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:34:42.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:34:42.25#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:42.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:34:42.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:34:42.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:34:42.31#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:34:42.31#ibcon#first serial, iclass 7, count 2 2006.245.07:34:42.31#ibcon#enter sib2, iclass 7, count 2 2006.245.07:34:42.31#ibcon#flushed, iclass 7, count 2 2006.245.07:34:42.31#ibcon#about to write, iclass 7, count 2 2006.245.07:34:42.31#ibcon#wrote, iclass 7, count 2 2006.245.07:34:42.31#ibcon#about to read 3, iclass 7, count 2 2006.245.07:34:42.33#ibcon#read 3, iclass 7, count 2 2006.245.07:34:42.33#ibcon#about to read 4, iclass 7, count 2 2006.245.07:34:42.33#ibcon#read 4, iclass 7, count 2 2006.245.07:34:42.33#ibcon#about to read 5, iclass 7, count 2 2006.245.07:34:42.33#ibcon#read 5, iclass 7, count 2 2006.245.07:34:42.33#ibcon#about to read 6, iclass 7, count 2 2006.245.07:34:42.33#ibcon#read 6, iclass 7, count 2 2006.245.07:34:42.33#ibcon#end of sib2, iclass 7, count 2 2006.245.07:34:42.33#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:34:42.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:34:42.33#ibcon#[25=AT08-08\r\n] 2006.245.07:34:42.33#ibcon#*before write, iclass 7, count 2 2006.245.07:34:42.33#ibcon#enter sib2, iclass 7, count 2 2006.245.07:34:42.33#ibcon#flushed, iclass 7, count 2 2006.245.07:34:42.33#ibcon#about to write, iclass 7, count 2 2006.245.07:34:42.33#ibcon#wrote, iclass 7, count 2 2006.245.07:34:42.33#ibcon#about to read 3, iclass 7, count 2 2006.245.07:34:42.36#ibcon#read 3, iclass 7, count 2 2006.245.07:34:42.36#ibcon#about to read 4, iclass 7, count 2 2006.245.07:34:42.36#ibcon#read 4, iclass 7, count 2 2006.245.07:34:42.36#ibcon#about to read 5, iclass 7, count 2 2006.245.07:34:42.36#ibcon#read 5, iclass 7, count 2 2006.245.07:34:42.36#ibcon#about to read 6, iclass 7, count 2 2006.245.07:34:42.36#ibcon#read 6, iclass 7, count 2 2006.245.07:34:42.36#ibcon#end of sib2, iclass 7, count 2 2006.245.07:34:42.36#ibcon#*after write, iclass 7, count 2 2006.245.07:34:42.36#ibcon#*before return 0, iclass 7, count 2 2006.245.07:34:42.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:34:42.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:34:42.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:34:42.36#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:42.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:34:42.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:34:42.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:34:42.48#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:34:42.48#ibcon#first serial, iclass 7, count 0 2006.245.07:34:42.48#ibcon#enter sib2, iclass 7, count 0 2006.245.07:34:42.48#ibcon#flushed, iclass 7, count 0 2006.245.07:34:42.48#ibcon#about to write, iclass 7, count 0 2006.245.07:34:42.48#ibcon#wrote, iclass 7, count 0 2006.245.07:34:42.48#ibcon#about to read 3, iclass 7, count 0 2006.245.07:34:42.50#ibcon#read 3, iclass 7, count 0 2006.245.07:34:42.50#ibcon#about to read 4, iclass 7, count 0 2006.245.07:34:42.50#ibcon#read 4, iclass 7, count 0 2006.245.07:34:42.50#ibcon#about to read 5, iclass 7, count 0 2006.245.07:34:42.50#ibcon#read 5, iclass 7, count 0 2006.245.07:34:42.50#ibcon#about to read 6, iclass 7, count 0 2006.245.07:34:42.50#ibcon#read 6, iclass 7, count 0 2006.245.07:34:42.50#ibcon#end of sib2, iclass 7, count 0 2006.245.07:34:42.50#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:34:42.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:34:42.50#ibcon#[25=USB\r\n] 2006.245.07:34:42.50#ibcon#*before write, iclass 7, count 0 2006.245.07:34:42.50#ibcon#enter sib2, iclass 7, count 0 2006.245.07:34:42.50#ibcon#flushed, iclass 7, count 0 2006.245.07:34:42.50#ibcon#about to write, iclass 7, count 0 2006.245.07:34:42.50#ibcon#wrote, iclass 7, count 0 2006.245.07:34:42.50#ibcon#about to read 3, iclass 7, count 0 2006.245.07:34:42.53#ibcon#read 3, iclass 7, count 0 2006.245.07:34:42.53#ibcon#about to read 4, iclass 7, count 0 2006.245.07:34:42.53#ibcon#read 4, iclass 7, count 0 2006.245.07:34:42.53#ibcon#about to read 5, iclass 7, count 0 2006.245.07:34:42.53#ibcon#read 5, iclass 7, count 0 2006.245.07:34:42.53#ibcon#about to read 6, iclass 7, count 0 2006.245.07:34:42.53#ibcon#read 6, iclass 7, count 0 2006.245.07:34:42.53#ibcon#end of sib2, iclass 7, count 0 2006.245.07:34:42.53#ibcon#*after write, iclass 7, count 0 2006.245.07:34:42.53#ibcon#*before return 0, iclass 7, count 0 2006.245.07:34:42.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:34:42.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:34:42.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:34:42.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:34:42.53$vc4f8/vblo=1,632.99 2006.245.07:34:42.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:34:42.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:34:42.53#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:42.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:34:42.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:34:42.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:34:42.53#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:34:42.53#ibcon#first serial, iclass 11, count 0 2006.245.07:34:42.53#ibcon#enter sib2, iclass 11, count 0 2006.245.07:34:42.53#ibcon#flushed, iclass 11, count 0 2006.245.07:34:42.53#ibcon#about to write, iclass 11, count 0 2006.245.07:34:42.53#ibcon#wrote, iclass 11, count 0 2006.245.07:34:42.53#ibcon#about to read 3, iclass 11, count 0 2006.245.07:34:42.55#ibcon#read 3, iclass 11, count 0 2006.245.07:34:42.55#ibcon#about to read 4, iclass 11, count 0 2006.245.07:34:42.55#ibcon#read 4, iclass 11, count 0 2006.245.07:34:42.55#ibcon#about to read 5, iclass 11, count 0 2006.245.07:34:42.55#ibcon#read 5, iclass 11, count 0 2006.245.07:34:42.55#ibcon#about to read 6, iclass 11, count 0 2006.245.07:34:42.55#ibcon#read 6, iclass 11, count 0 2006.245.07:34:42.55#ibcon#end of sib2, iclass 11, count 0 2006.245.07:34:42.55#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:34:42.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:34:42.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:34:42.55#ibcon#*before write, iclass 11, count 0 2006.245.07:34:42.55#ibcon#enter sib2, iclass 11, count 0 2006.245.07:34:42.55#ibcon#flushed, iclass 11, count 0 2006.245.07:34:42.55#ibcon#about to write, iclass 11, count 0 2006.245.07:34:42.55#ibcon#wrote, iclass 11, count 0 2006.245.07:34:42.55#ibcon#about to read 3, iclass 11, count 0 2006.245.07:34:42.59#ibcon#read 3, iclass 11, count 0 2006.245.07:34:42.59#ibcon#about to read 4, iclass 11, count 0 2006.245.07:34:42.59#ibcon#read 4, iclass 11, count 0 2006.245.07:34:42.59#ibcon#about to read 5, iclass 11, count 0 2006.245.07:34:42.59#ibcon#read 5, iclass 11, count 0 2006.245.07:34:42.59#ibcon#about to read 6, iclass 11, count 0 2006.245.07:34:42.59#ibcon#read 6, iclass 11, count 0 2006.245.07:34:42.59#ibcon#end of sib2, iclass 11, count 0 2006.245.07:34:42.59#ibcon#*after write, iclass 11, count 0 2006.245.07:34:42.59#ibcon#*before return 0, iclass 11, count 0 2006.245.07:34:42.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:34:42.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:34:42.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:34:42.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:34:42.59$vc4f8/vb=1,4 2006.245.07:34:42.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.07:34:42.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.07:34:42.59#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:42.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:34:42.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:34:42.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:34:42.59#ibcon#enter wrdev, iclass 13, count 2 2006.245.07:34:42.59#ibcon#first serial, iclass 13, count 2 2006.245.07:34:42.59#ibcon#enter sib2, iclass 13, count 2 2006.245.07:34:42.59#ibcon#flushed, iclass 13, count 2 2006.245.07:34:42.59#ibcon#about to write, iclass 13, count 2 2006.245.07:34:42.59#ibcon#wrote, iclass 13, count 2 2006.245.07:34:42.59#ibcon#about to read 3, iclass 13, count 2 2006.245.07:34:42.61#ibcon#read 3, iclass 13, count 2 2006.245.07:34:42.61#ibcon#about to read 4, iclass 13, count 2 2006.245.07:34:42.61#ibcon#read 4, iclass 13, count 2 2006.245.07:34:42.61#ibcon#about to read 5, iclass 13, count 2 2006.245.07:34:42.61#ibcon#read 5, iclass 13, count 2 2006.245.07:34:42.61#ibcon#about to read 6, iclass 13, count 2 2006.245.07:34:42.61#ibcon#read 6, iclass 13, count 2 2006.245.07:34:42.61#ibcon#end of sib2, iclass 13, count 2 2006.245.07:34:42.61#ibcon#*mode == 0, iclass 13, count 2 2006.245.07:34:42.61#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.07:34:42.61#ibcon#[27=AT01-04\r\n] 2006.245.07:34:42.61#ibcon#*before write, iclass 13, count 2 2006.245.07:34:42.61#ibcon#enter sib2, iclass 13, count 2 2006.245.07:34:42.61#ibcon#flushed, iclass 13, count 2 2006.245.07:34:42.61#ibcon#about to write, iclass 13, count 2 2006.245.07:34:42.61#ibcon#wrote, iclass 13, count 2 2006.245.07:34:42.61#ibcon#about to read 3, iclass 13, count 2 2006.245.07:34:42.64#ibcon#read 3, iclass 13, count 2 2006.245.07:34:42.64#ibcon#about to read 4, iclass 13, count 2 2006.245.07:34:42.64#ibcon#read 4, iclass 13, count 2 2006.245.07:34:42.64#ibcon#about to read 5, iclass 13, count 2 2006.245.07:34:42.64#ibcon#read 5, iclass 13, count 2 2006.245.07:34:42.64#ibcon#about to read 6, iclass 13, count 2 2006.245.07:34:42.64#ibcon#read 6, iclass 13, count 2 2006.245.07:34:42.64#ibcon#end of sib2, iclass 13, count 2 2006.245.07:34:42.64#ibcon#*after write, iclass 13, count 2 2006.245.07:34:42.64#ibcon#*before return 0, iclass 13, count 2 2006.245.07:34:42.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:34:42.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:34:42.64#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.07:34:42.64#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:42.64#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:34:42.76#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:34:42.76#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:34:42.76#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:34:42.76#ibcon#first serial, iclass 13, count 0 2006.245.07:34:42.76#ibcon#enter sib2, iclass 13, count 0 2006.245.07:34:42.76#ibcon#flushed, iclass 13, count 0 2006.245.07:34:42.76#ibcon#about to write, iclass 13, count 0 2006.245.07:34:42.76#ibcon#wrote, iclass 13, count 0 2006.245.07:34:42.76#ibcon#about to read 3, iclass 13, count 0 2006.245.07:34:42.78#ibcon#read 3, iclass 13, count 0 2006.245.07:34:42.78#ibcon#about to read 4, iclass 13, count 0 2006.245.07:34:42.78#ibcon#read 4, iclass 13, count 0 2006.245.07:34:42.78#ibcon#about to read 5, iclass 13, count 0 2006.245.07:34:42.78#ibcon#read 5, iclass 13, count 0 2006.245.07:34:42.78#ibcon#about to read 6, iclass 13, count 0 2006.245.07:34:42.78#ibcon#read 6, iclass 13, count 0 2006.245.07:34:42.78#ibcon#end of sib2, iclass 13, count 0 2006.245.07:34:42.78#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:34:42.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:34:42.78#ibcon#[27=USB\r\n] 2006.245.07:34:42.78#ibcon#*before write, iclass 13, count 0 2006.245.07:34:42.78#ibcon#enter sib2, iclass 13, count 0 2006.245.07:34:42.78#ibcon#flushed, iclass 13, count 0 2006.245.07:34:42.78#ibcon#about to write, iclass 13, count 0 2006.245.07:34:42.78#ibcon#wrote, iclass 13, count 0 2006.245.07:34:42.78#ibcon#about to read 3, iclass 13, count 0 2006.245.07:34:42.81#ibcon#read 3, iclass 13, count 0 2006.245.07:34:42.81#ibcon#about to read 4, iclass 13, count 0 2006.245.07:34:42.81#ibcon#read 4, iclass 13, count 0 2006.245.07:34:42.81#ibcon#about to read 5, iclass 13, count 0 2006.245.07:34:42.81#ibcon#read 5, iclass 13, count 0 2006.245.07:34:42.81#ibcon#about to read 6, iclass 13, count 0 2006.245.07:34:42.81#ibcon#read 6, iclass 13, count 0 2006.245.07:34:42.81#ibcon#end of sib2, iclass 13, count 0 2006.245.07:34:42.81#ibcon#*after write, iclass 13, count 0 2006.245.07:34:42.81#ibcon#*before return 0, iclass 13, count 0 2006.245.07:34:42.81#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:34:42.81#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:34:42.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:34:42.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:34:42.81$vc4f8/vblo=2,640.99 2006.245.07:34:42.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.07:34:42.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.07:34:42.81#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:42.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:42.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:42.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:42.81#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:34:42.81#ibcon#first serial, iclass 15, count 0 2006.245.07:34:42.81#ibcon#enter sib2, iclass 15, count 0 2006.245.07:34:42.81#ibcon#flushed, iclass 15, count 0 2006.245.07:34:42.81#ibcon#about to write, iclass 15, count 0 2006.245.07:34:42.81#ibcon#wrote, iclass 15, count 0 2006.245.07:34:42.81#ibcon#about to read 3, iclass 15, count 0 2006.245.07:34:42.83#ibcon#read 3, iclass 15, count 0 2006.245.07:34:42.83#ibcon#about to read 4, iclass 15, count 0 2006.245.07:34:42.83#ibcon#read 4, iclass 15, count 0 2006.245.07:34:42.83#ibcon#about to read 5, iclass 15, count 0 2006.245.07:34:42.83#ibcon#read 5, iclass 15, count 0 2006.245.07:34:42.83#ibcon#about to read 6, iclass 15, count 0 2006.245.07:34:42.83#ibcon#read 6, iclass 15, count 0 2006.245.07:34:42.83#ibcon#end of sib2, iclass 15, count 0 2006.245.07:34:42.83#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:34:42.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:34:42.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:34:42.83#ibcon#*before write, iclass 15, count 0 2006.245.07:34:42.83#ibcon#enter sib2, iclass 15, count 0 2006.245.07:34:42.83#ibcon#flushed, iclass 15, count 0 2006.245.07:34:42.83#ibcon#about to write, iclass 15, count 0 2006.245.07:34:42.83#ibcon#wrote, iclass 15, count 0 2006.245.07:34:42.83#ibcon#about to read 3, iclass 15, count 0 2006.245.07:34:42.87#ibcon#read 3, iclass 15, count 0 2006.245.07:34:42.87#ibcon#about to read 4, iclass 15, count 0 2006.245.07:34:42.87#ibcon#read 4, iclass 15, count 0 2006.245.07:34:42.87#ibcon#about to read 5, iclass 15, count 0 2006.245.07:34:42.87#ibcon#read 5, iclass 15, count 0 2006.245.07:34:42.87#ibcon#about to read 6, iclass 15, count 0 2006.245.07:34:42.87#ibcon#read 6, iclass 15, count 0 2006.245.07:34:42.87#ibcon#end of sib2, iclass 15, count 0 2006.245.07:34:42.87#ibcon#*after write, iclass 15, count 0 2006.245.07:34:42.87#ibcon#*before return 0, iclass 15, count 0 2006.245.07:34:42.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:42.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:34:42.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:34:42.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:34:42.87$vc4f8/vb=2,4 2006.245.07:34:42.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.07:34:42.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.07:34:42.87#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:42.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:42.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:42.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:42.93#ibcon#enter wrdev, iclass 17, count 2 2006.245.07:34:42.93#ibcon#first serial, iclass 17, count 2 2006.245.07:34:42.93#ibcon#enter sib2, iclass 17, count 2 2006.245.07:34:42.93#ibcon#flushed, iclass 17, count 2 2006.245.07:34:42.93#ibcon#about to write, iclass 17, count 2 2006.245.07:34:42.93#ibcon#wrote, iclass 17, count 2 2006.245.07:34:42.93#ibcon#about to read 3, iclass 17, count 2 2006.245.07:34:42.95#ibcon#read 3, iclass 17, count 2 2006.245.07:34:42.95#ibcon#about to read 4, iclass 17, count 2 2006.245.07:34:42.95#ibcon#read 4, iclass 17, count 2 2006.245.07:34:42.95#ibcon#about to read 5, iclass 17, count 2 2006.245.07:34:42.95#ibcon#read 5, iclass 17, count 2 2006.245.07:34:42.95#ibcon#about to read 6, iclass 17, count 2 2006.245.07:34:42.95#ibcon#read 6, iclass 17, count 2 2006.245.07:34:42.95#ibcon#end of sib2, iclass 17, count 2 2006.245.07:34:42.95#ibcon#*mode == 0, iclass 17, count 2 2006.245.07:34:42.95#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.07:34:42.95#ibcon#[27=AT02-04\r\n] 2006.245.07:34:42.95#ibcon#*before write, iclass 17, count 2 2006.245.07:34:42.95#ibcon#enter sib2, iclass 17, count 2 2006.245.07:34:42.95#ibcon#flushed, iclass 17, count 2 2006.245.07:34:42.95#ibcon#about to write, iclass 17, count 2 2006.245.07:34:42.95#ibcon#wrote, iclass 17, count 2 2006.245.07:34:42.95#ibcon#about to read 3, iclass 17, count 2 2006.245.07:34:42.98#ibcon#read 3, iclass 17, count 2 2006.245.07:34:42.98#ibcon#about to read 4, iclass 17, count 2 2006.245.07:34:42.98#ibcon#read 4, iclass 17, count 2 2006.245.07:34:42.98#ibcon#about to read 5, iclass 17, count 2 2006.245.07:34:42.98#ibcon#read 5, iclass 17, count 2 2006.245.07:34:42.98#ibcon#about to read 6, iclass 17, count 2 2006.245.07:34:42.98#ibcon#read 6, iclass 17, count 2 2006.245.07:34:42.98#ibcon#end of sib2, iclass 17, count 2 2006.245.07:34:42.98#ibcon#*after write, iclass 17, count 2 2006.245.07:34:42.98#ibcon#*before return 0, iclass 17, count 2 2006.245.07:34:42.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:42.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:34:42.98#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.07:34:42.98#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:42.98#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:43.10#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:43.10#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:43.10#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:34:43.10#ibcon#first serial, iclass 17, count 0 2006.245.07:34:43.10#ibcon#enter sib2, iclass 17, count 0 2006.245.07:34:43.10#ibcon#flushed, iclass 17, count 0 2006.245.07:34:43.10#ibcon#about to write, iclass 17, count 0 2006.245.07:34:43.10#ibcon#wrote, iclass 17, count 0 2006.245.07:34:43.10#ibcon#about to read 3, iclass 17, count 0 2006.245.07:34:43.12#ibcon#read 3, iclass 17, count 0 2006.245.07:34:43.12#ibcon#about to read 4, iclass 17, count 0 2006.245.07:34:43.12#ibcon#read 4, iclass 17, count 0 2006.245.07:34:43.12#ibcon#about to read 5, iclass 17, count 0 2006.245.07:34:43.12#ibcon#read 5, iclass 17, count 0 2006.245.07:34:43.12#ibcon#about to read 6, iclass 17, count 0 2006.245.07:34:43.12#ibcon#read 6, iclass 17, count 0 2006.245.07:34:43.12#ibcon#end of sib2, iclass 17, count 0 2006.245.07:34:43.12#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:34:43.12#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:34:43.12#ibcon#[27=USB\r\n] 2006.245.07:34:43.12#ibcon#*before write, iclass 17, count 0 2006.245.07:34:43.12#ibcon#enter sib2, iclass 17, count 0 2006.245.07:34:43.12#ibcon#flushed, iclass 17, count 0 2006.245.07:34:43.12#ibcon#about to write, iclass 17, count 0 2006.245.07:34:43.12#ibcon#wrote, iclass 17, count 0 2006.245.07:34:43.12#ibcon#about to read 3, iclass 17, count 0 2006.245.07:34:43.15#ibcon#read 3, iclass 17, count 0 2006.245.07:34:43.15#ibcon#about to read 4, iclass 17, count 0 2006.245.07:34:43.15#ibcon#read 4, iclass 17, count 0 2006.245.07:34:43.15#ibcon#about to read 5, iclass 17, count 0 2006.245.07:34:43.15#ibcon#read 5, iclass 17, count 0 2006.245.07:34:43.15#ibcon#about to read 6, iclass 17, count 0 2006.245.07:34:43.15#ibcon#read 6, iclass 17, count 0 2006.245.07:34:43.15#ibcon#end of sib2, iclass 17, count 0 2006.245.07:34:43.15#ibcon#*after write, iclass 17, count 0 2006.245.07:34:43.15#ibcon#*before return 0, iclass 17, count 0 2006.245.07:34:43.15#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:43.15#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:34:43.15#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:34:43.15#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:34:43.15$vc4f8/vblo=3,656.99 2006.245.07:34:43.15#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.07:34:43.15#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.07:34:43.15#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:43.15#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:43.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:43.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:43.15#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:34:43.15#ibcon#first serial, iclass 19, count 0 2006.245.07:34:43.15#ibcon#enter sib2, iclass 19, count 0 2006.245.07:34:43.15#ibcon#flushed, iclass 19, count 0 2006.245.07:34:43.15#ibcon#about to write, iclass 19, count 0 2006.245.07:34:43.15#ibcon#wrote, iclass 19, count 0 2006.245.07:34:43.15#ibcon#about to read 3, iclass 19, count 0 2006.245.07:34:43.17#ibcon#read 3, iclass 19, count 0 2006.245.07:34:43.17#ibcon#about to read 4, iclass 19, count 0 2006.245.07:34:43.17#ibcon#read 4, iclass 19, count 0 2006.245.07:34:43.17#ibcon#about to read 5, iclass 19, count 0 2006.245.07:34:43.17#ibcon#read 5, iclass 19, count 0 2006.245.07:34:43.17#ibcon#about to read 6, iclass 19, count 0 2006.245.07:34:43.17#ibcon#read 6, iclass 19, count 0 2006.245.07:34:43.17#ibcon#end of sib2, iclass 19, count 0 2006.245.07:34:43.17#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:34:43.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:34:43.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:34:43.17#ibcon#*before write, iclass 19, count 0 2006.245.07:34:43.17#ibcon#enter sib2, iclass 19, count 0 2006.245.07:34:43.17#ibcon#flushed, iclass 19, count 0 2006.245.07:34:43.17#ibcon#about to write, iclass 19, count 0 2006.245.07:34:43.17#ibcon#wrote, iclass 19, count 0 2006.245.07:34:43.17#ibcon#about to read 3, iclass 19, count 0 2006.245.07:34:43.21#ibcon#read 3, iclass 19, count 0 2006.245.07:34:43.21#ibcon#about to read 4, iclass 19, count 0 2006.245.07:34:43.21#ibcon#read 4, iclass 19, count 0 2006.245.07:34:43.21#ibcon#about to read 5, iclass 19, count 0 2006.245.07:34:43.21#ibcon#read 5, iclass 19, count 0 2006.245.07:34:43.21#ibcon#about to read 6, iclass 19, count 0 2006.245.07:34:43.21#ibcon#read 6, iclass 19, count 0 2006.245.07:34:43.21#ibcon#end of sib2, iclass 19, count 0 2006.245.07:34:43.21#ibcon#*after write, iclass 19, count 0 2006.245.07:34:43.21#ibcon#*before return 0, iclass 19, count 0 2006.245.07:34:43.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:43.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:34:43.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:34:43.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:34:43.21$vc4f8/vb=3,4 2006.245.07:34:43.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.07:34:43.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.07:34:43.21#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:43.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:43.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:43.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:43.27#ibcon#enter wrdev, iclass 21, count 2 2006.245.07:34:43.27#ibcon#first serial, iclass 21, count 2 2006.245.07:34:43.27#ibcon#enter sib2, iclass 21, count 2 2006.245.07:34:43.27#ibcon#flushed, iclass 21, count 2 2006.245.07:34:43.27#ibcon#about to write, iclass 21, count 2 2006.245.07:34:43.27#ibcon#wrote, iclass 21, count 2 2006.245.07:34:43.27#ibcon#about to read 3, iclass 21, count 2 2006.245.07:34:43.29#ibcon#read 3, iclass 21, count 2 2006.245.07:34:43.29#ibcon#about to read 4, iclass 21, count 2 2006.245.07:34:43.29#ibcon#read 4, iclass 21, count 2 2006.245.07:34:43.29#ibcon#about to read 5, iclass 21, count 2 2006.245.07:34:43.29#ibcon#read 5, iclass 21, count 2 2006.245.07:34:43.29#ibcon#about to read 6, iclass 21, count 2 2006.245.07:34:43.29#ibcon#read 6, iclass 21, count 2 2006.245.07:34:43.29#ibcon#end of sib2, iclass 21, count 2 2006.245.07:34:43.29#ibcon#*mode == 0, iclass 21, count 2 2006.245.07:34:43.29#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.07:34:43.29#ibcon#[27=AT03-04\r\n] 2006.245.07:34:43.29#ibcon#*before write, iclass 21, count 2 2006.245.07:34:43.29#ibcon#enter sib2, iclass 21, count 2 2006.245.07:34:43.29#ibcon#flushed, iclass 21, count 2 2006.245.07:34:43.29#ibcon#about to write, iclass 21, count 2 2006.245.07:34:43.29#ibcon#wrote, iclass 21, count 2 2006.245.07:34:43.29#ibcon#about to read 3, iclass 21, count 2 2006.245.07:34:43.32#ibcon#read 3, iclass 21, count 2 2006.245.07:34:43.32#ibcon#about to read 4, iclass 21, count 2 2006.245.07:34:43.32#ibcon#read 4, iclass 21, count 2 2006.245.07:34:43.32#ibcon#about to read 5, iclass 21, count 2 2006.245.07:34:43.32#ibcon#read 5, iclass 21, count 2 2006.245.07:34:43.32#ibcon#about to read 6, iclass 21, count 2 2006.245.07:34:43.32#ibcon#read 6, iclass 21, count 2 2006.245.07:34:43.32#ibcon#end of sib2, iclass 21, count 2 2006.245.07:34:43.32#ibcon#*after write, iclass 21, count 2 2006.245.07:34:43.32#ibcon#*before return 0, iclass 21, count 2 2006.245.07:34:43.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:43.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:34:43.32#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.07:34:43.32#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:43.32#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:43.44#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:43.44#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:43.44#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:34:43.44#ibcon#first serial, iclass 21, count 0 2006.245.07:34:43.44#ibcon#enter sib2, iclass 21, count 0 2006.245.07:34:43.44#ibcon#flushed, iclass 21, count 0 2006.245.07:34:43.44#ibcon#about to write, iclass 21, count 0 2006.245.07:34:43.44#ibcon#wrote, iclass 21, count 0 2006.245.07:34:43.44#ibcon#about to read 3, iclass 21, count 0 2006.245.07:34:43.46#ibcon#read 3, iclass 21, count 0 2006.245.07:34:43.46#ibcon#about to read 4, iclass 21, count 0 2006.245.07:34:43.46#ibcon#read 4, iclass 21, count 0 2006.245.07:34:43.46#ibcon#about to read 5, iclass 21, count 0 2006.245.07:34:43.46#ibcon#read 5, iclass 21, count 0 2006.245.07:34:43.46#ibcon#about to read 6, iclass 21, count 0 2006.245.07:34:43.46#ibcon#read 6, iclass 21, count 0 2006.245.07:34:43.46#ibcon#end of sib2, iclass 21, count 0 2006.245.07:34:43.46#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:34:43.46#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:34:43.46#ibcon#[27=USB\r\n] 2006.245.07:34:43.46#ibcon#*before write, iclass 21, count 0 2006.245.07:34:43.46#ibcon#enter sib2, iclass 21, count 0 2006.245.07:34:43.46#ibcon#flushed, iclass 21, count 0 2006.245.07:34:43.46#ibcon#about to write, iclass 21, count 0 2006.245.07:34:43.46#ibcon#wrote, iclass 21, count 0 2006.245.07:34:43.46#ibcon#about to read 3, iclass 21, count 0 2006.245.07:34:43.49#ibcon#read 3, iclass 21, count 0 2006.245.07:34:43.49#ibcon#about to read 4, iclass 21, count 0 2006.245.07:34:43.49#ibcon#read 4, iclass 21, count 0 2006.245.07:34:43.49#ibcon#about to read 5, iclass 21, count 0 2006.245.07:34:43.49#ibcon#read 5, iclass 21, count 0 2006.245.07:34:43.49#ibcon#about to read 6, iclass 21, count 0 2006.245.07:34:43.49#ibcon#read 6, iclass 21, count 0 2006.245.07:34:43.49#ibcon#end of sib2, iclass 21, count 0 2006.245.07:34:43.49#ibcon#*after write, iclass 21, count 0 2006.245.07:34:43.49#ibcon#*before return 0, iclass 21, count 0 2006.245.07:34:43.49#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:43.49#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:34:43.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:34:43.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:34:43.49$vc4f8/vblo=4,712.99 2006.245.07:34:43.49#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.07:34:43.49#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.07:34:43.49#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:43.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:43.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:43.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:43.49#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:34:43.49#ibcon#first serial, iclass 23, count 0 2006.245.07:34:43.49#ibcon#enter sib2, iclass 23, count 0 2006.245.07:34:43.49#ibcon#flushed, iclass 23, count 0 2006.245.07:34:43.49#ibcon#about to write, iclass 23, count 0 2006.245.07:34:43.49#ibcon#wrote, iclass 23, count 0 2006.245.07:34:43.49#ibcon#about to read 3, iclass 23, count 0 2006.245.07:34:43.51#ibcon#read 3, iclass 23, count 0 2006.245.07:34:43.51#ibcon#about to read 4, iclass 23, count 0 2006.245.07:34:43.51#ibcon#read 4, iclass 23, count 0 2006.245.07:34:43.51#ibcon#about to read 5, iclass 23, count 0 2006.245.07:34:43.51#ibcon#read 5, iclass 23, count 0 2006.245.07:34:43.51#ibcon#about to read 6, iclass 23, count 0 2006.245.07:34:43.51#ibcon#read 6, iclass 23, count 0 2006.245.07:34:43.51#ibcon#end of sib2, iclass 23, count 0 2006.245.07:34:43.51#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:34:43.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:34:43.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:34:43.51#ibcon#*before write, iclass 23, count 0 2006.245.07:34:43.51#ibcon#enter sib2, iclass 23, count 0 2006.245.07:34:43.51#ibcon#flushed, iclass 23, count 0 2006.245.07:34:43.51#ibcon#about to write, iclass 23, count 0 2006.245.07:34:43.51#ibcon#wrote, iclass 23, count 0 2006.245.07:34:43.51#ibcon#about to read 3, iclass 23, count 0 2006.245.07:34:43.55#ibcon#read 3, iclass 23, count 0 2006.245.07:34:43.55#ibcon#about to read 4, iclass 23, count 0 2006.245.07:34:43.55#ibcon#read 4, iclass 23, count 0 2006.245.07:34:43.55#ibcon#about to read 5, iclass 23, count 0 2006.245.07:34:43.55#ibcon#read 5, iclass 23, count 0 2006.245.07:34:43.55#ibcon#about to read 6, iclass 23, count 0 2006.245.07:34:43.55#ibcon#read 6, iclass 23, count 0 2006.245.07:34:43.55#ibcon#end of sib2, iclass 23, count 0 2006.245.07:34:43.55#ibcon#*after write, iclass 23, count 0 2006.245.07:34:43.55#ibcon#*before return 0, iclass 23, count 0 2006.245.07:34:43.55#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:43.55#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:34:43.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:34:43.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:34:43.55$vc4f8/vb=4,4 2006.245.07:34:43.55#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.07:34:43.55#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.07:34:43.55#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:43.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:43.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:43.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:43.61#ibcon#enter wrdev, iclass 25, count 2 2006.245.07:34:43.61#ibcon#first serial, iclass 25, count 2 2006.245.07:34:43.61#ibcon#enter sib2, iclass 25, count 2 2006.245.07:34:43.61#ibcon#flushed, iclass 25, count 2 2006.245.07:34:43.61#ibcon#about to write, iclass 25, count 2 2006.245.07:34:43.61#ibcon#wrote, iclass 25, count 2 2006.245.07:34:43.61#ibcon#about to read 3, iclass 25, count 2 2006.245.07:34:43.63#ibcon#read 3, iclass 25, count 2 2006.245.07:34:43.63#ibcon#about to read 4, iclass 25, count 2 2006.245.07:34:43.63#ibcon#read 4, iclass 25, count 2 2006.245.07:34:43.63#ibcon#about to read 5, iclass 25, count 2 2006.245.07:34:43.63#ibcon#read 5, iclass 25, count 2 2006.245.07:34:43.63#ibcon#about to read 6, iclass 25, count 2 2006.245.07:34:43.63#ibcon#read 6, iclass 25, count 2 2006.245.07:34:43.63#ibcon#end of sib2, iclass 25, count 2 2006.245.07:34:43.63#ibcon#*mode == 0, iclass 25, count 2 2006.245.07:34:43.63#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.07:34:43.63#ibcon#[27=AT04-04\r\n] 2006.245.07:34:43.63#ibcon#*before write, iclass 25, count 2 2006.245.07:34:43.63#ibcon#enter sib2, iclass 25, count 2 2006.245.07:34:43.63#ibcon#flushed, iclass 25, count 2 2006.245.07:34:43.63#ibcon#about to write, iclass 25, count 2 2006.245.07:34:43.63#ibcon#wrote, iclass 25, count 2 2006.245.07:34:43.63#ibcon#about to read 3, iclass 25, count 2 2006.245.07:34:43.66#ibcon#read 3, iclass 25, count 2 2006.245.07:34:43.66#ibcon#about to read 4, iclass 25, count 2 2006.245.07:34:43.66#ibcon#read 4, iclass 25, count 2 2006.245.07:34:43.66#ibcon#about to read 5, iclass 25, count 2 2006.245.07:34:43.66#ibcon#read 5, iclass 25, count 2 2006.245.07:34:43.66#ibcon#about to read 6, iclass 25, count 2 2006.245.07:34:43.66#ibcon#read 6, iclass 25, count 2 2006.245.07:34:43.66#ibcon#end of sib2, iclass 25, count 2 2006.245.07:34:43.66#ibcon#*after write, iclass 25, count 2 2006.245.07:34:43.66#ibcon#*before return 0, iclass 25, count 2 2006.245.07:34:43.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:43.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:34:43.66#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.07:34:43.66#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:43.66#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:43.78#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:43.78#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:43.78#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:34:43.78#ibcon#first serial, iclass 25, count 0 2006.245.07:34:43.78#ibcon#enter sib2, iclass 25, count 0 2006.245.07:34:43.78#ibcon#flushed, iclass 25, count 0 2006.245.07:34:43.78#ibcon#about to write, iclass 25, count 0 2006.245.07:34:43.78#ibcon#wrote, iclass 25, count 0 2006.245.07:34:43.78#ibcon#about to read 3, iclass 25, count 0 2006.245.07:34:43.80#ibcon#read 3, iclass 25, count 0 2006.245.07:34:43.80#ibcon#about to read 4, iclass 25, count 0 2006.245.07:34:43.80#ibcon#read 4, iclass 25, count 0 2006.245.07:34:43.80#ibcon#about to read 5, iclass 25, count 0 2006.245.07:34:43.80#ibcon#read 5, iclass 25, count 0 2006.245.07:34:43.80#ibcon#about to read 6, iclass 25, count 0 2006.245.07:34:43.80#ibcon#read 6, iclass 25, count 0 2006.245.07:34:43.80#ibcon#end of sib2, iclass 25, count 0 2006.245.07:34:43.80#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:34:43.80#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:34:43.80#ibcon#[27=USB\r\n] 2006.245.07:34:43.80#ibcon#*before write, iclass 25, count 0 2006.245.07:34:43.80#ibcon#enter sib2, iclass 25, count 0 2006.245.07:34:43.80#ibcon#flushed, iclass 25, count 0 2006.245.07:34:43.80#ibcon#about to write, iclass 25, count 0 2006.245.07:34:43.80#ibcon#wrote, iclass 25, count 0 2006.245.07:34:43.80#ibcon#about to read 3, iclass 25, count 0 2006.245.07:34:43.83#ibcon#read 3, iclass 25, count 0 2006.245.07:34:43.83#ibcon#about to read 4, iclass 25, count 0 2006.245.07:34:43.83#ibcon#read 4, iclass 25, count 0 2006.245.07:34:43.83#ibcon#about to read 5, iclass 25, count 0 2006.245.07:34:43.83#ibcon#read 5, iclass 25, count 0 2006.245.07:34:43.83#ibcon#about to read 6, iclass 25, count 0 2006.245.07:34:43.83#ibcon#read 6, iclass 25, count 0 2006.245.07:34:43.83#ibcon#end of sib2, iclass 25, count 0 2006.245.07:34:43.83#ibcon#*after write, iclass 25, count 0 2006.245.07:34:43.83#ibcon#*before return 0, iclass 25, count 0 2006.245.07:34:43.83#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:43.83#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:34:43.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:34:43.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:34:43.83$vc4f8/vblo=5,744.99 2006.245.07:34:43.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:34:43.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:34:43.83#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:43.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:43.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:43.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:43.83#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:34:43.83#ibcon#first serial, iclass 27, count 0 2006.245.07:34:43.83#ibcon#enter sib2, iclass 27, count 0 2006.245.07:34:43.83#ibcon#flushed, iclass 27, count 0 2006.245.07:34:43.83#ibcon#about to write, iclass 27, count 0 2006.245.07:34:43.83#ibcon#wrote, iclass 27, count 0 2006.245.07:34:43.83#ibcon#about to read 3, iclass 27, count 0 2006.245.07:34:43.85#ibcon#read 3, iclass 27, count 0 2006.245.07:34:43.85#ibcon#about to read 4, iclass 27, count 0 2006.245.07:34:43.85#ibcon#read 4, iclass 27, count 0 2006.245.07:34:43.85#ibcon#about to read 5, iclass 27, count 0 2006.245.07:34:43.85#ibcon#read 5, iclass 27, count 0 2006.245.07:34:43.85#ibcon#about to read 6, iclass 27, count 0 2006.245.07:34:43.85#ibcon#read 6, iclass 27, count 0 2006.245.07:34:43.85#ibcon#end of sib2, iclass 27, count 0 2006.245.07:34:43.85#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:34:43.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:34:43.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:34:43.85#ibcon#*before write, iclass 27, count 0 2006.245.07:34:43.85#ibcon#enter sib2, iclass 27, count 0 2006.245.07:34:43.85#ibcon#flushed, iclass 27, count 0 2006.245.07:34:43.85#ibcon#about to write, iclass 27, count 0 2006.245.07:34:43.85#ibcon#wrote, iclass 27, count 0 2006.245.07:34:43.85#ibcon#about to read 3, iclass 27, count 0 2006.245.07:34:43.89#ibcon#read 3, iclass 27, count 0 2006.245.07:34:43.89#ibcon#about to read 4, iclass 27, count 0 2006.245.07:34:43.89#ibcon#read 4, iclass 27, count 0 2006.245.07:34:43.89#ibcon#about to read 5, iclass 27, count 0 2006.245.07:34:43.89#ibcon#read 5, iclass 27, count 0 2006.245.07:34:43.89#ibcon#about to read 6, iclass 27, count 0 2006.245.07:34:43.89#ibcon#read 6, iclass 27, count 0 2006.245.07:34:43.89#ibcon#end of sib2, iclass 27, count 0 2006.245.07:34:43.89#ibcon#*after write, iclass 27, count 0 2006.245.07:34:43.89#ibcon#*before return 0, iclass 27, count 0 2006.245.07:34:43.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:43.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:34:43.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:34:43.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:34:43.89$vc4f8/vb=5,3 2006.245.07:34:43.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:34:43.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:34:43.89#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:43.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:43.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:43.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:43.95#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:34:43.95#ibcon#first serial, iclass 29, count 2 2006.245.07:34:43.95#ibcon#enter sib2, iclass 29, count 2 2006.245.07:34:43.95#ibcon#flushed, iclass 29, count 2 2006.245.07:34:43.95#ibcon#about to write, iclass 29, count 2 2006.245.07:34:43.95#ibcon#wrote, iclass 29, count 2 2006.245.07:34:43.95#ibcon#about to read 3, iclass 29, count 2 2006.245.07:34:43.97#ibcon#read 3, iclass 29, count 2 2006.245.07:34:43.97#ibcon#about to read 4, iclass 29, count 2 2006.245.07:34:43.97#ibcon#read 4, iclass 29, count 2 2006.245.07:34:43.97#ibcon#about to read 5, iclass 29, count 2 2006.245.07:34:43.97#ibcon#read 5, iclass 29, count 2 2006.245.07:34:43.97#ibcon#about to read 6, iclass 29, count 2 2006.245.07:34:43.97#ibcon#read 6, iclass 29, count 2 2006.245.07:34:43.97#ibcon#end of sib2, iclass 29, count 2 2006.245.07:34:43.97#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:34:43.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:34:43.97#ibcon#[27=AT05-03\r\n] 2006.245.07:34:43.97#ibcon#*before write, iclass 29, count 2 2006.245.07:34:43.97#ibcon#enter sib2, iclass 29, count 2 2006.245.07:34:43.97#ibcon#flushed, iclass 29, count 2 2006.245.07:34:43.97#ibcon#about to write, iclass 29, count 2 2006.245.07:34:43.97#ibcon#wrote, iclass 29, count 2 2006.245.07:34:43.97#ibcon#about to read 3, iclass 29, count 2 2006.245.07:34:44.00#ibcon#read 3, iclass 29, count 2 2006.245.07:34:44.00#ibcon#about to read 4, iclass 29, count 2 2006.245.07:34:44.00#ibcon#read 4, iclass 29, count 2 2006.245.07:34:44.00#ibcon#about to read 5, iclass 29, count 2 2006.245.07:34:44.00#ibcon#read 5, iclass 29, count 2 2006.245.07:34:44.00#ibcon#about to read 6, iclass 29, count 2 2006.245.07:34:44.00#ibcon#read 6, iclass 29, count 2 2006.245.07:34:44.00#ibcon#end of sib2, iclass 29, count 2 2006.245.07:34:44.00#ibcon#*after write, iclass 29, count 2 2006.245.07:34:44.00#ibcon#*before return 0, iclass 29, count 2 2006.245.07:34:44.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:44.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:34:44.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:34:44.00#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:44.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:44.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:44.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:44.12#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:34:44.12#ibcon#first serial, iclass 29, count 0 2006.245.07:34:44.12#ibcon#enter sib2, iclass 29, count 0 2006.245.07:34:44.12#ibcon#flushed, iclass 29, count 0 2006.245.07:34:44.12#ibcon#about to write, iclass 29, count 0 2006.245.07:34:44.12#ibcon#wrote, iclass 29, count 0 2006.245.07:34:44.12#ibcon#about to read 3, iclass 29, count 0 2006.245.07:34:44.14#ibcon#read 3, iclass 29, count 0 2006.245.07:34:44.14#ibcon#about to read 4, iclass 29, count 0 2006.245.07:34:44.14#ibcon#read 4, iclass 29, count 0 2006.245.07:34:44.14#ibcon#about to read 5, iclass 29, count 0 2006.245.07:34:44.14#ibcon#read 5, iclass 29, count 0 2006.245.07:34:44.14#ibcon#about to read 6, iclass 29, count 0 2006.245.07:34:44.14#ibcon#read 6, iclass 29, count 0 2006.245.07:34:44.14#ibcon#end of sib2, iclass 29, count 0 2006.245.07:34:44.14#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:34:44.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:34:44.14#ibcon#[27=USB\r\n] 2006.245.07:34:44.14#ibcon#*before write, iclass 29, count 0 2006.245.07:34:44.14#ibcon#enter sib2, iclass 29, count 0 2006.245.07:34:44.14#ibcon#flushed, iclass 29, count 0 2006.245.07:34:44.14#ibcon#about to write, iclass 29, count 0 2006.245.07:34:44.14#ibcon#wrote, iclass 29, count 0 2006.245.07:34:44.14#ibcon#about to read 3, iclass 29, count 0 2006.245.07:34:44.17#ibcon#read 3, iclass 29, count 0 2006.245.07:34:44.17#ibcon#about to read 4, iclass 29, count 0 2006.245.07:34:44.17#ibcon#read 4, iclass 29, count 0 2006.245.07:34:44.17#ibcon#about to read 5, iclass 29, count 0 2006.245.07:34:44.17#ibcon#read 5, iclass 29, count 0 2006.245.07:34:44.17#ibcon#about to read 6, iclass 29, count 0 2006.245.07:34:44.17#ibcon#read 6, iclass 29, count 0 2006.245.07:34:44.17#ibcon#end of sib2, iclass 29, count 0 2006.245.07:34:44.17#ibcon#*after write, iclass 29, count 0 2006.245.07:34:44.17#ibcon#*before return 0, iclass 29, count 0 2006.245.07:34:44.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:44.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:34:44.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:34:44.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:34:44.17$vc4f8/vblo=6,752.99 2006.245.07:34:44.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:34:44.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:34:44.17#ibcon#ireg 17 cls_cnt 0 2006.245.07:34:44.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:44.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:44.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:44.17#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:34:44.17#ibcon#first serial, iclass 31, count 0 2006.245.07:34:44.17#ibcon#enter sib2, iclass 31, count 0 2006.245.07:34:44.17#ibcon#flushed, iclass 31, count 0 2006.245.07:34:44.17#ibcon#about to write, iclass 31, count 0 2006.245.07:34:44.17#ibcon#wrote, iclass 31, count 0 2006.245.07:34:44.17#ibcon#about to read 3, iclass 31, count 0 2006.245.07:34:44.19#ibcon#read 3, iclass 31, count 0 2006.245.07:34:44.19#ibcon#about to read 4, iclass 31, count 0 2006.245.07:34:44.19#ibcon#read 4, iclass 31, count 0 2006.245.07:34:44.19#ibcon#about to read 5, iclass 31, count 0 2006.245.07:34:44.19#ibcon#read 5, iclass 31, count 0 2006.245.07:34:44.19#ibcon#about to read 6, iclass 31, count 0 2006.245.07:34:44.19#ibcon#read 6, iclass 31, count 0 2006.245.07:34:44.19#ibcon#end of sib2, iclass 31, count 0 2006.245.07:34:44.19#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:34:44.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:34:44.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:34:44.19#ibcon#*before write, iclass 31, count 0 2006.245.07:34:44.19#ibcon#enter sib2, iclass 31, count 0 2006.245.07:34:44.19#ibcon#flushed, iclass 31, count 0 2006.245.07:34:44.19#ibcon#about to write, iclass 31, count 0 2006.245.07:34:44.19#ibcon#wrote, iclass 31, count 0 2006.245.07:34:44.19#ibcon#about to read 3, iclass 31, count 0 2006.245.07:34:44.23#ibcon#read 3, iclass 31, count 0 2006.245.07:34:44.23#ibcon#about to read 4, iclass 31, count 0 2006.245.07:34:44.23#ibcon#read 4, iclass 31, count 0 2006.245.07:34:44.23#ibcon#about to read 5, iclass 31, count 0 2006.245.07:34:44.23#ibcon#read 5, iclass 31, count 0 2006.245.07:34:44.23#ibcon#about to read 6, iclass 31, count 0 2006.245.07:34:44.23#ibcon#read 6, iclass 31, count 0 2006.245.07:34:44.23#ibcon#end of sib2, iclass 31, count 0 2006.245.07:34:44.23#ibcon#*after write, iclass 31, count 0 2006.245.07:34:44.23#ibcon#*before return 0, iclass 31, count 0 2006.245.07:34:44.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:44.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:34:44.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:34:44.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:34:44.23$vc4f8/vb=6,3 2006.245.07:34:44.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:34:44.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:34:44.23#ibcon#ireg 11 cls_cnt 2 2006.245.07:34:44.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:44.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:44.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:44.30#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:34:44.30#ibcon#first serial, iclass 33, count 2 2006.245.07:34:44.30#ibcon#enter sib2, iclass 33, count 2 2006.245.07:34:44.30#ibcon#flushed, iclass 33, count 2 2006.245.07:34:44.30#ibcon#about to write, iclass 33, count 2 2006.245.07:34:44.30#ibcon#wrote, iclass 33, count 2 2006.245.07:34:44.30#ibcon#about to read 3, iclass 33, count 2 2006.245.07:34:44.31#ibcon#read 3, iclass 33, count 2 2006.245.07:34:44.31#ibcon#about to read 4, iclass 33, count 2 2006.245.07:34:44.31#ibcon#read 4, iclass 33, count 2 2006.245.07:34:44.31#ibcon#about to read 5, iclass 33, count 2 2006.245.07:34:44.31#ibcon#read 5, iclass 33, count 2 2006.245.07:34:44.31#ibcon#about to read 6, iclass 33, count 2 2006.245.07:34:44.31#ibcon#read 6, iclass 33, count 2 2006.245.07:34:44.31#ibcon#end of sib2, iclass 33, count 2 2006.245.07:34:44.31#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:34:44.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:34:44.31#ibcon#[27=AT06-03\r\n] 2006.245.07:34:44.31#ibcon#*before write, iclass 33, count 2 2006.245.07:34:44.31#ibcon#enter sib2, iclass 33, count 2 2006.245.07:34:44.31#ibcon#flushed, iclass 33, count 2 2006.245.07:34:44.31#ibcon#about to write, iclass 33, count 2 2006.245.07:34:44.31#ibcon#wrote, iclass 33, count 2 2006.245.07:34:44.31#ibcon#about to read 3, iclass 33, count 2 2006.245.07:34:44.34#ibcon#read 3, iclass 33, count 2 2006.245.07:34:44.34#ibcon#about to read 4, iclass 33, count 2 2006.245.07:34:44.34#ibcon#read 4, iclass 33, count 2 2006.245.07:34:44.34#ibcon#about to read 5, iclass 33, count 2 2006.245.07:34:44.34#ibcon#read 5, iclass 33, count 2 2006.245.07:34:44.34#ibcon#about to read 6, iclass 33, count 2 2006.245.07:34:44.34#ibcon#read 6, iclass 33, count 2 2006.245.07:34:44.34#ibcon#end of sib2, iclass 33, count 2 2006.245.07:34:44.34#ibcon#*after write, iclass 33, count 2 2006.245.07:34:44.34#ibcon#*before return 0, iclass 33, count 2 2006.245.07:34:44.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:44.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:34:44.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:34:44.34#ibcon#ireg 7 cls_cnt 0 2006.245.07:34:44.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:44.46#abcon#<5=/05 3.0 5.6 27.62 671004.4\r\n> 2006.245.07:34:44.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:44.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:44.46#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:34:44.46#ibcon#first serial, iclass 33, count 0 2006.245.07:34:44.46#ibcon#enter sib2, iclass 33, count 0 2006.245.07:34:44.46#ibcon#flushed, iclass 33, count 0 2006.245.07:34:44.46#ibcon#about to write, iclass 33, count 0 2006.245.07:34:44.46#ibcon#wrote, iclass 33, count 0 2006.245.07:34:44.46#ibcon#about to read 3, iclass 33, count 0 2006.245.07:34:44.48#ibcon#read 3, iclass 33, count 0 2006.245.07:34:44.48#ibcon#about to read 4, iclass 33, count 0 2006.245.07:34:44.48#ibcon#read 4, iclass 33, count 0 2006.245.07:34:44.48#ibcon#about to read 5, iclass 33, count 0 2006.245.07:34:44.48#ibcon#read 5, iclass 33, count 0 2006.245.07:34:44.48#ibcon#about to read 6, iclass 33, count 0 2006.245.07:34:44.48#ibcon#read 6, iclass 33, count 0 2006.245.07:34:44.48#ibcon#end of sib2, iclass 33, count 0 2006.245.07:34:44.48#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:34:44.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:34:44.48#ibcon#[27=USB\r\n] 2006.245.07:34:44.48#ibcon#*before write, iclass 33, count 0 2006.245.07:34:44.48#ibcon#enter sib2, iclass 33, count 0 2006.245.07:34:44.48#ibcon#flushed, iclass 33, count 0 2006.245.07:34:44.48#ibcon#about to write, iclass 33, count 0 2006.245.07:34:44.48#ibcon#wrote, iclass 33, count 0 2006.245.07:34:44.48#ibcon#about to read 3, iclass 33, count 0 2006.245.07:34:44.48#abcon#{5=INTERFACE CLEAR} 2006.245.07:34:44.51#ibcon#read 3, iclass 33, count 0 2006.245.07:34:44.51#ibcon#about to read 4, iclass 33, count 0 2006.245.07:34:44.51#ibcon#read 4, iclass 33, count 0 2006.245.07:34:44.51#ibcon#about to read 5, iclass 33, count 0 2006.245.07:34:44.51#ibcon#read 5, iclass 33, count 0 2006.245.07:34:44.51#ibcon#about to read 6, iclass 33, count 0 2006.245.07:34:44.51#ibcon#read 6, iclass 33, count 0 2006.245.07:34:44.51#ibcon#end of sib2, iclass 33, count 0 2006.245.07:34:44.51#ibcon#*after write, iclass 33, count 0 2006.245.07:34:44.51#ibcon#*before return 0, iclass 33, count 0 2006.245.07:34:44.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:44.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:34:44.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:34:44.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:34:44.51$vc4f8/vabw=wide 2006.245.07:34:44.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:34:44.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:34:44.51#ibcon#ireg 8 cls_cnt 0 2006.245.07:34:44.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:34:44.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:34:44.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:34:44.51#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:34:44.51#ibcon#first serial, iclass 38, count 0 2006.245.07:34:44.51#ibcon#enter sib2, iclass 38, count 0 2006.245.07:34:44.51#ibcon#flushed, iclass 38, count 0 2006.245.07:34:44.51#ibcon#about to write, iclass 38, count 0 2006.245.07:34:44.51#ibcon#wrote, iclass 38, count 0 2006.245.07:34:44.51#ibcon#about to read 3, iclass 38, count 0 2006.245.07:34:44.53#ibcon#read 3, iclass 38, count 0 2006.245.07:34:44.53#ibcon#about to read 4, iclass 38, count 0 2006.245.07:34:44.53#ibcon#read 4, iclass 38, count 0 2006.245.07:34:44.53#ibcon#about to read 5, iclass 38, count 0 2006.245.07:34:44.53#ibcon#read 5, iclass 38, count 0 2006.245.07:34:44.53#ibcon#about to read 6, iclass 38, count 0 2006.245.07:34:44.53#ibcon#read 6, iclass 38, count 0 2006.245.07:34:44.53#ibcon#end of sib2, iclass 38, count 0 2006.245.07:34:44.53#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:34:44.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:34:44.53#ibcon#[25=BW32\r\n] 2006.245.07:34:44.53#ibcon#*before write, iclass 38, count 0 2006.245.07:34:44.53#ibcon#enter sib2, iclass 38, count 0 2006.245.07:34:44.53#ibcon#flushed, iclass 38, count 0 2006.245.07:34:44.53#ibcon#about to write, iclass 38, count 0 2006.245.07:34:44.53#ibcon#wrote, iclass 38, count 0 2006.245.07:34:44.53#ibcon#about to read 3, iclass 38, count 0 2006.245.07:34:44.54#abcon#[5=S1D000X0/0*\r\n] 2006.245.07:34:44.56#ibcon#read 3, iclass 38, count 0 2006.245.07:34:44.56#ibcon#about to read 4, iclass 38, count 0 2006.245.07:34:44.56#ibcon#read 4, iclass 38, count 0 2006.245.07:34:44.56#ibcon#about to read 5, iclass 38, count 0 2006.245.07:34:44.56#ibcon#read 5, iclass 38, count 0 2006.245.07:34:44.56#ibcon#about to read 6, iclass 38, count 0 2006.245.07:34:44.56#ibcon#read 6, iclass 38, count 0 2006.245.07:34:44.56#ibcon#end of sib2, iclass 38, count 0 2006.245.07:34:44.56#ibcon#*after write, iclass 38, count 0 2006.245.07:34:44.56#ibcon#*before return 0, iclass 38, count 0 2006.245.07:34:44.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:34:44.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:34:44.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:34:44.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:34:44.56$vc4f8/vbbw=wide 2006.245.07:34:44.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.07:34:44.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.07:34:44.56#ibcon#ireg 8 cls_cnt 0 2006.245.07:34:44.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:34:44.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:34:44.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:34:44.63#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:34:44.63#ibcon#first serial, iclass 3, count 0 2006.245.07:34:44.63#ibcon#enter sib2, iclass 3, count 0 2006.245.07:34:44.63#ibcon#flushed, iclass 3, count 0 2006.245.07:34:44.63#ibcon#about to write, iclass 3, count 0 2006.245.07:34:44.63#ibcon#wrote, iclass 3, count 0 2006.245.07:34:44.63#ibcon#about to read 3, iclass 3, count 0 2006.245.07:34:44.65#ibcon#read 3, iclass 3, count 0 2006.245.07:34:44.65#ibcon#about to read 4, iclass 3, count 0 2006.245.07:34:44.65#ibcon#read 4, iclass 3, count 0 2006.245.07:34:44.65#ibcon#about to read 5, iclass 3, count 0 2006.245.07:34:44.65#ibcon#read 5, iclass 3, count 0 2006.245.07:34:44.65#ibcon#about to read 6, iclass 3, count 0 2006.245.07:34:44.65#ibcon#read 6, iclass 3, count 0 2006.245.07:34:44.65#ibcon#end of sib2, iclass 3, count 0 2006.245.07:34:44.65#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:34:44.65#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:34:44.65#ibcon#[27=BW32\r\n] 2006.245.07:34:44.65#ibcon#*before write, iclass 3, count 0 2006.245.07:34:44.65#ibcon#enter sib2, iclass 3, count 0 2006.245.07:34:44.65#ibcon#flushed, iclass 3, count 0 2006.245.07:34:44.65#ibcon#about to write, iclass 3, count 0 2006.245.07:34:44.65#ibcon#wrote, iclass 3, count 0 2006.245.07:34:44.65#ibcon#about to read 3, iclass 3, count 0 2006.245.07:34:44.68#ibcon#read 3, iclass 3, count 0 2006.245.07:34:44.68#ibcon#about to read 4, iclass 3, count 0 2006.245.07:34:44.68#ibcon#read 4, iclass 3, count 0 2006.245.07:34:44.68#ibcon#about to read 5, iclass 3, count 0 2006.245.07:34:44.68#ibcon#read 5, iclass 3, count 0 2006.245.07:34:44.68#ibcon#about to read 6, iclass 3, count 0 2006.245.07:34:44.68#ibcon#read 6, iclass 3, count 0 2006.245.07:34:44.68#ibcon#end of sib2, iclass 3, count 0 2006.245.07:34:44.68#ibcon#*after write, iclass 3, count 0 2006.245.07:34:44.68#ibcon#*before return 0, iclass 3, count 0 2006.245.07:34:44.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:34:44.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:34:44.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:34:44.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:34:44.68$4f8m12a/ifd4f 2006.245.07:34:44.68$ifd4f/lo= 2006.245.07:34:44.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:34:44.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:34:44.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:34:44.68$ifd4f/patch= 2006.245.07:34:44.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:34:44.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:34:44.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:34:44.68$4f8m12a/"form=m,16.000,1:2 2006.245.07:34:44.68$4f8m12a/"tpicd 2006.245.07:34:44.68$4f8m12a/echo=off 2006.245.07:34:44.68$4f8m12a/xlog=off 2006.245.07:34:44.68:!2006.245.07:35:10 2006.245.07:34:54.14#trakl#Source acquired 2006.245.07:34:55.14#flagr#flagr/antenna,acquired 2006.245.07:35:10.00:preob 2006.245.07:35:11.14/onsource/TRACKING 2006.245.07:35:11.14:!2006.245.07:35:20 2006.245.07:35:20.00:data_valid=on 2006.245.07:35:20.00:midob 2006.245.07:35:20.14/onsource/TRACKING 2006.245.07:35:20.14/wx/27.61,1004.4,68 2006.245.07:35:20.34/cable/+6.4113E-03 2006.245.07:35:21.43/va/01,08,usb,yes,31,32 2006.245.07:35:21.43/va/02,07,usb,yes,30,32 2006.245.07:35:21.43/va/03,06,usb,yes,32,33 2006.245.07:35:21.43/va/04,07,usb,yes,32,34 2006.245.07:35:21.43/va/05,07,usb,yes,33,35 2006.245.07:35:21.43/va/06,07,usb,yes,29,29 2006.245.07:35:21.43/va/07,07,usb,yes,29,28 2006.245.07:35:21.43/va/08,08,usb,yes,25,25 2006.245.07:35:21.66/valo/01,532.99,yes,locked 2006.245.07:35:21.66/valo/02,572.99,yes,locked 2006.245.07:35:21.66/valo/03,672.99,yes,locked 2006.245.07:35:21.66/valo/04,832.99,yes,locked 2006.245.07:35:21.66/valo/05,652.99,yes,locked 2006.245.07:35:21.66/valo/06,772.99,yes,locked 2006.245.07:35:21.66/valo/07,832.99,yes,locked 2006.245.07:35:21.66/valo/08,852.99,yes,locked 2006.245.07:35:22.75/vb/01,04,usb,yes,30,29 2006.245.07:35:22.75/vb/02,04,usb,yes,32,33 2006.245.07:35:22.75/vb/03,04,usb,yes,28,32 2006.245.07:35:22.75/vb/04,04,usb,yes,29,29 2006.245.07:35:22.75/vb/05,03,usb,yes,34,39 2006.245.07:35:22.75/vb/06,03,usb,yes,35,39 2006.245.07:35:22.75/vb/07,04,usb,yes,31,31 2006.245.07:35:22.75/vb/08,03,usb,yes,35,39 2006.245.07:35:22.98/vblo/01,632.99,yes,locked 2006.245.07:35:22.98/vblo/02,640.99,yes,locked 2006.245.07:35:22.98/vblo/03,656.99,yes,locked 2006.245.07:35:22.98/vblo/04,712.99,yes,locked 2006.245.07:35:22.98/vblo/05,744.99,yes,locked 2006.245.07:35:22.98/vblo/06,752.99,yes,locked 2006.245.07:35:22.98/vblo/07,734.99,yes,locked 2006.245.07:35:22.98/vblo/08,744.99,yes,locked 2006.245.07:35:23.13/vabw/8 2006.245.07:35:23.28/vbbw/8 2006.245.07:35:23.37/xfe/off,on,13.2 2006.245.07:35:23.75/ifatt/23,28,28,28 2006.245.07:35:24.08/fmout-gps/S +4.47E-07 2006.245.07:35:24.12:!2006.245.07:36:20 2006.245.07:36:20.00:data_valid=off 2006.245.07:36:20.00:postob 2006.245.07:36:20.08/cable/+6.4100E-03 2006.245.07:36:20.08/wx/27.61,1004.4,66 2006.245.07:36:21.08/fmout-gps/S +4.45E-07 2006.245.07:36:21.08:scan_name=245-0737,k06245,60 2006.245.07:36:21.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.245.07:36:21.14#flagr#flagr/antenna,new-source 2006.245.07:36:22.14:checkk5 2006.245.07:36:22.59/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:36:22.99/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:36:23.45/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:36:24.10/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:36:24.51/chk_obsdata//k5ts1/T2450735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:36:24.96/chk_obsdata//k5ts2/T2450735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:36:25.40/chk_obsdata//k5ts3/T2450735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:36:26.19/chk_obsdata//k5ts4/T2450735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:36:26.91/k5log//k5ts1_log_newline 2006.245.07:36:27.82/k5log//k5ts2_log_newline 2006.245.07:36:28.79/k5log//k5ts3_log_newline 2006.245.07:36:29.68/k5log//k5ts4_log_newline 2006.245.07:36:29.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:36:29.70:4f8m12a=1 2006.245.07:36:29.70$4f8m12a/echo=on 2006.245.07:36:29.70$4f8m12a/pcalon 2006.245.07:36:29.70$pcalon/"no phase cal control is implemented here 2006.245.07:36:29.70$4f8m12a/"tpicd=stop 2006.245.07:36:29.70$4f8m12a/vc4f8 2006.245.07:36:29.70$vc4f8/valo=1,532.99 2006.245.07:36:29.71#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.07:36:29.71#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.07:36:29.71#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:29.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:29.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:29.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:29.71#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:36:29.71#ibcon#first serial, iclass 12, count 0 2006.245.07:36:29.71#ibcon#enter sib2, iclass 12, count 0 2006.245.07:36:29.71#ibcon#flushed, iclass 12, count 0 2006.245.07:36:29.71#ibcon#about to write, iclass 12, count 0 2006.245.07:36:29.71#ibcon#wrote, iclass 12, count 0 2006.245.07:36:29.71#ibcon#about to read 3, iclass 12, count 0 2006.245.07:36:29.75#ibcon#read 3, iclass 12, count 0 2006.245.07:36:29.75#ibcon#about to read 4, iclass 12, count 0 2006.245.07:36:29.75#ibcon#read 4, iclass 12, count 0 2006.245.07:36:29.75#ibcon#about to read 5, iclass 12, count 0 2006.245.07:36:29.75#ibcon#read 5, iclass 12, count 0 2006.245.07:36:29.75#ibcon#about to read 6, iclass 12, count 0 2006.245.07:36:29.75#ibcon#read 6, iclass 12, count 0 2006.245.07:36:29.75#ibcon#end of sib2, iclass 12, count 0 2006.245.07:36:29.75#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:36:29.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:36:29.75#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:36:29.75#ibcon#*before write, iclass 12, count 0 2006.245.07:36:29.75#ibcon#enter sib2, iclass 12, count 0 2006.245.07:36:29.75#ibcon#flushed, iclass 12, count 0 2006.245.07:36:29.75#ibcon#about to write, iclass 12, count 0 2006.245.07:36:29.75#ibcon#wrote, iclass 12, count 0 2006.245.07:36:29.75#ibcon#about to read 3, iclass 12, count 0 2006.245.07:36:29.79#ibcon#read 3, iclass 12, count 0 2006.245.07:36:29.79#ibcon#about to read 4, iclass 12, count 0 2006.245.07:36:29.79#ibcon#read 4, iclass 12, count 0 2006.245.07:36:29.79#ibcon#about to read 5, iclass 12, count 0 2006.245.07:36:29.79#ibcon#read 5, iclass 12, count 0 2006.245.07:36:29.79#ibcon#about to read 6, iclass 12, count 0 2006.245.07:36:29.79#ibcon#read 6, iclass 12, count 0 2006.245.07:36:29.79#ibcon#end of sib2, iclass 12, count 0 2006.245.07:36:29.79#ibcon#*after write, iclass 12, count 0 2006.245.07:36:29.79#ibcon#*before return 0, iclass 12, count 0 2006.245.07:36:29.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:29.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:29.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:36:29.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:36:29.79$vc4f8/va=1,8 2006.245.07:36:29.79#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.07:36:29.79#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.07:36:29.79#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:29.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:29.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:29.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:29.79#ibcon#enter wrdev, iclass 14, count 2 2006.245.07:36:29.79#ibcon#first serial, iclass 14, count 2 2006.245.07:36:29.79#ibcon#enter sib2, iclass 14, count 2 2006.245.07:36:29.79#ibcon#flushed, iclass 14, count 2 2006.245.07:36:29.79#ibcon#about to write, iclass 14, count 2 2006.245.07:36:29.79#ibcon#wrote, iclass 14, count 2 2006.245.07:36:29.79#ibcon#about to read 3, iclass 14, count 2 2006.245.07:36:29.81#ibcon#read 3, iclass 14, count 2 2006.245.07:36:29.81#ibcon#about to read 4, iclass 14, count 2 2006.245.07:36:29.81#ibcon#read 4, iclass 14, count 2 2006.245.07:36:29.81#ibcon#about to read 5, iclass 14, count 2 2006.245.07:36:29.81#ibcon#read 5, iclass 14, count 2 2006.245.07:36:29.81#ibcon#about to read 6, iclass 14, count 2 2006.245.07:36:29.81#ibcon#read 6, iclass 14, count 2 2006.245.07:36:29.81#ibcon#end of sib2, iclass 14, count 2 2006.245.07:36:29.81#ibcon#*mode == 0, iclass 14, count 2 2006.245.07:36:29.81#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.07:36:29.81#ibcon#[25=AT01-08\r\n] 2006.245.07:36:29.81#ibcon#*before write, iclass 14, count 2 2006.245.07:36:29.81#ibcon#enter sib2, iclass 14, count 2 2006.245.07:36:29.81#ibcon#flushed, iclass 14, count 2 2006.245.07:36:29.81#ibcon#about to write, iclass 14, count 2 2006.245.07:36:29.81#ibcon#wrote, iclass 14, count 2 2006.245.07:36:29.81#ibcon#about to read 3, iclass 14, count 2 2006.245.07:36:29.84#ibcon#read 3, iclass 14, count 2 2006.245.07:36:29.84#ibcon#about to read 4, iclass 14, count 2 2006.245.07:36:29.84#ibcon#read 4, iclass 14, count 2 2006.245.07:36:29.84#ibcon#about to read 5, iclass 14, count 2 2006.245.07:36:29.84#ibcon#read 5, iclass 14, count 2 2006.245.07:36:29.84#ibcon#about to read 6, iclass 14, count 2 2006.245.07:36:29.84#ibcon#read 6, iclass 14, count 2 2006.245.07:36:29.84#ibcon#end of sib2, iclass 14, count 2 2006.245.07:36:29.84#ibcon#*after write, iclass 14, count 2 2006.245.07:36:29.84#ibcon#*before return 0, iclass 14, count 2 2006.245.07:36:29.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:29.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:29.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.07:36:29.84#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:29.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:29.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:29.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:29.96#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:36:29.96#ibcon#first serial, iclass 14, count 0 2006.245.07:36:29.96#ibcon#enter sib2, iclass 14, count 0 2006.245.07:36:29.96#ibcon#flushed, iclass 14, count 0 2006.245.07:36:29.96#ibcon#about to write, iclass 14, count 0 2006.245.07:36:29.96#ibcon#wrote, iclass 14, count 0 2006.245.07:36:29.96#ibcon#about to read 3, iclass 14, count 0 2006.245.07:36:29.98#ibcon#read 3, iclass 14, count 0 2006.245.07:36:29.98#ibcon#about to read 4, iclass 14, count 0 2006.245.07:36:29.98#ibcon#read 4, iclass 14, count 0 2006.245.07:36:29.98#ibcon#about to read 5, iclass 14, count 0 2006.245.07:36:29.98#ibcon#read 5, iclass 14, count 0 2006.245.07:36:29.98#ibcon#about to read 6, iclass 14, count 0 2006.245.07:36:29.98#ibcon#read 6, iclass 14, count 0 2006.245.07:36:29.98#ibcon#end of sib2, iclass 14, count 0 2006.245.07:36:29.98#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:36:29.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:36:29.98#ibcon#[25=USB\r\n] 2006.245.07:36:29.98#ibcon#*before write, iclass 14, count 0 2006.245.07:36:29.98#ibcon#enter sib2, iclass 14, count 0 2006.245.07:36:29.98#ibcon#flushed, iclass 14, count 0 2006.245.07:36:29.98#ibcon#about to write, iclass 14, count 0 2006.245.07:36:29.98#ibcon#wrote, iclass 14, count 0 2006.245.07:36:29.98#ibcon#about to read 3, iclass 14, count 0 2006.245.07:36:30.01#ibcon#read 3, iclass 14, count 0 2006.245.07:36:30.01#ibcon#about to read 4, iclass 14, count 0 2006.245.07:36:30.01#ibcon#read 4, iclass 14, count 0 2006.245.07:36:30.01#ibcon#about to read 5, iclass 14, count 0 2006.245.07:36:30.01#ibcon#read 5, iclass 14, count 0 2006.245.07:36:30.01#ibcon#about to read 6, iclass 14, count 0 2006.245.07:36:30.01#ibcon#read 6, iclass 14, count 0 2006.245.07:36:30.01#ibcon#end of sib2, iclass 14, count 0 2006.245.07:36:30.01#ibcon#*after write, iclass 14, count 0 2006.245.07:36:30.01#ibcon#*before return 0, iclass 14, count 0 2006.245.07:36:30.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:30.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:30.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:36:30.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:36:30.01$vc4f8/valo=2,572.99 2006.245.07:36:30.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:36:30.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:36:30.01#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:30.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:30.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:30.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:30.01#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:36:30.01#ibcon#first serial, iclass 16, count 0 2006.245.07:36:30.01#ibcon#enter sib2, iclass 16, count 0 2006.245.07:36:30.01#ibcon#flushed, iclass 16, count 0 2006.245.07:36:30.01#ibcon#about to write, iclass 16, count 0 2006.245.07:36:30.01#ibcon#wrote, iclass 16, count 0 2006.245.07:36:30.01#ibcon#about to read 3, iclass 16, count 0 2006.245.07:36:30.04#ibcon#read 3, iclass 16, count 0 2006.245.07:36:30.04#ibcon#about to read 4, iclass 16, count 0 2006.245.07:36:30.04#ibcon#read 4, iclass 16, count 0 2006.245.07:36:30.04#ibcon#about to read 5, iclass 16, count 0 2006.245.07:36:30.04#ibcon#read 5, iclass 16, count 0 2006.245.07:36:30.04#ibcon#about to read 6, iclass 16, count 0 2006.245.07:36:30.04#ibcon#read 6, iclass 16, count 0 2006.245.07:36:30.04#ibcon#end of sib2, iclass 16, count 0 2006.245.07:36:30.04#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:36:30.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:36:30.04#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:36:30.04#ibcon#*before write, iclass 16, count 0 2006.245.07:36:30.04#ibcon#enter sib2, iclass 16, count 0 2006.245.07:36:30.04#ibcon#flushed, iclass 16, count 0 2006.245.07:36:30.04#ibcon#about to write, iclass 16, count 0 2006.245.07:36:30.04#ibcon#wrote, iclass 16, count 0 2006.245.07:36:30.04#ibcon#about to read 3, iclass 16, count 0 2006.245.07:36:30.08#ibcon#read 3, iclass 16, count 0 2006.245.07:36:30.08#ibcon#about to read 4, iclass 16, count 0 2006.245.07:36:30.08#ibcon#read 4, iclass 16, count 0 2006.245.07:36:30.08#ibcon#about to read 5, iclass 16, count 0 2006.245.07:36:30.08#ibcon#read 5, iclass 16, count 0 2006.245.07:36:30.08#ibcon#about to read 6, iclass 16, count 0 2006.245.07:36:30.08#ibcon#read 6, iclass 16, count 0 2006.245.07:36:30.08#ibcon#end of sib2, iclass 16, count 0 2006.245.07:36:30.08#ibcon#*after write, iclass 16, count 0 2006.245.07:36:30.08#ibcon#*before return 0, iclass 16, count 0 2006.245.07:36:30.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:30.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:30.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:36:30.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:36:30.08$vc4f8/va=2,7 2006.245.07:36:30.08#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.07:36:30.08#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.07:36:30.08#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:30.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:30.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:30.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:30.13#ibcon#enter wrdev, iclass 18, count 2 2006.245.07:36:30.13#ibcon#first serial, iclass 18, count 2 2006.245.07:36:30.13#ibcon#enter sib2, iclass 18, count 2 2006.245.07:36:30.13#ibcon#flushed, iclass 18, count 2 2006.245.07:36:30.13#ibcon#about to write, iclass 18, count 2 2006.245.07:36:30.13#ibcon#wrote, iclass 18, count 2 2006.245.07:36:30.13#ibcon#about to read 3, iclass 18, count 2 2006.245.07:36:30.15#ibcon#read 3, iclass 18, count 2 2006.245.07:36:30.15#ibcon#about to read 4, iclass 18, count 2 2006.245.07:36:30.15#ibcon#read 4, iclass 18, count 2 2006.245.07:36:30.15#ibcon#about to read 5, iclass 18, count 2 2006.245.07:36:30.15#ibcon#read 5, iclass 18, count 2 2006.245.07:36:30.15#ibcon#about to read 6, iclass 18, count 2 2006.245.07:36:30.15#ibcon#read 6, iclass 18, count 2 2006.245.07:36:30.15#ibcon#end of sib2, iclass 18, count 2 2006.245.07:36:30.15#ibcon#*mode == 0, iclass 18, count 2 2006.245.07:36:30.15#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.07:36:30.15#ibcon#[25=AT02-07\r\n] 2006.245.07:36:30.15#ibcon#*before write, iclass 18, count 2 2006.245.07:36:30.15#ibcon#enter sib2, iclass 18, count 2 2006.245.07:36:30.15#ibcon#flushed, iclass 18, count 2 2006.245.07:36:30.15#ibcon#about to write, iclass 18, count 2 2006.245.07:36:30.15#ibcon#wrote, iclass 18, count 2 2006.245.07:36:30.15#ibcon#about to read 3, iclass 18, count 2 2006.245.07:36:30.18#ibcon#read 3, iclass 18, count 2 2006.245.07:36:30.18#ibcon#about to read 4, iclass 18, count 2 2006.245.07:36:30.18#ibcon#read 4, iclass 18, count 2 2006.245.07:36:30.18#ibcon#about to read 5, iclass 18, count 2 2006.245.07:36:30.18#ibcon#read 5, iclass 18, count 2 2006.245.07:36:30.18#ibcon#about to read 6, iclass 18, count 2 2006.245.07:36:30.18#ibcon#read 6, iclass 18, count 2 2006.245.07:36:30.18#ibcon#end of sib2, iclass 18, count 2 2006.245.07:36:30.18#ibcon#*after write, iclass 18, count 2 2006.245.07:36:30.18#ibcon#*before return 0, iclass 18, count 2 2006.245.07:36:30.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:30.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:30.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.07:36:30.18#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:30.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:30.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:30.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:30.30#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:36:30.30#ibcon#first serial, iclass 18, count 0 2006.245.07:36:30.30#ibcon#enter sib2, iclass 18, count 0 2006.245.07:36:30.30#ibcon#flushed, iclass 18, count 0 2006.245.07:36:30.30#ibcon#about to write, iclass 18, count 0 2006.245.07:36:30.30#ibcon#wrote, iclass 18, count 0 2006.245.07:36:30.30#ibcon#about to read 3, iclass 18, count 0 2006.245.07:36:30.32#ibcon#read 3, iclass 18, count 0 2006.245.07:36:30.32#ibcon#about to read 4, iclass 18, count 0 2006.245.07:36:30.32#ibcon#read 4, iclass 18, count 0 2006.245.07:36:30.32#ibcon#about to read 5, iclass 18, count 0 2006.245.07:36:30.32#ibcon#read 5, iclass 18, count 0 2006.245.07:36:30.32#ibcon#about to read 6, iclass 18, count 0 2006.245.07:36:30.32#ibcon#read 6, iclass 18, count 0 2006.245.07:36:30.32#ibcon#end of sib2, iclass 18, count 0 2006.245.07:36:30.32#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:36:30.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:36:30.32#ibcon#[25=USB\r\n] 2006.245.07:36:30.32#ibcon#*before write, iclass 18, count 0 2006.245.07:36:30.32#ibcon#enter sib2, iclass 18, count 0 2006.245.07:36:30.32#ibcon#flushed, iclass 18, count 0 2006.245.07:36:30.32#ibcon#about to write, iclass 18, count 0 2006.245.07:36:30.32#ibcon#wrote, iclass 18, count 0 2006.245.07:36:30.32#ibcon#about to read 3, iclass 18, count 0 2006.245.07:36:30.35#ibcon#read 3, iclass 18, count 0 2006.245.07:36:30.35#ibcon#about to read 4, iclass 18, count 0 2006.245.07:36:30.35#ibcon#read 4, iclass 18, count 0 2006.245.07:36:30.35#ibcon#about to read 5, iclass 18, count 0 2006.245.07:36:30.35#ibcon#read 5, iclass 18, count 0 2006.245.07:36:30.35#ibcon#about to read 6, iclass 18, count 0 2006.245.07:36:30.35#ibcon#read 6, iclass 18, count 0 2006.245.07:36:30.35#ibcon#end of sib2, iclass 18, count 0 2006.245.07:36:30.35#ibcon#*after write, iclass 18, count 0 2006.245.07:36:30.35#ibcon#*before return 0, iclass 18, count 0 2006.245.07:36:30.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:30.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:30.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:36:30.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:36:30.35$vc4f8/valo=3,672.99 2006.245.07:36:30.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.07:36:30.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.07:36:30.35#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:30.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:30.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:30.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:30.35#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:36:30.35#ibcon#first serial, iclass 20, count 0 2006.245.07:36:30.35#ibcon#enter sib2, iclass 20, count 0 2006.245.07:36:30.35#ibcon#flushed, iclass 20, count 0 2006.245.07:36:30.35#ibcon#about to write, iclass 20, count 0 2006.245.07:36:30.35#ibcon#wrote, iclass 20, count 0 2006.245.07:36:30.35#ibcon#about to read 3, iclass 20, count 0 2006.245.07:36:30.38#ibcon#read 3, iclass 20, count 0 2006.245.07:36:30.38#ibcon#about to read 4, iclass 20, count 0 2006.245.07:36:30.38#ibcon#read 4, iclass 20, count 0 2006.245.07:36:30.38#ibcon#about to read 5, iclass 20, count 0 2006.245.07:36:30.38#ibcon#read 5, iclass 20, count 0 2006.245.07:36:30.38#ibcon#about to read 6, iclass 20, count 0 2006.245.07:36:30.38#ibcon#read 6, iclass 20, count 0 2006.245.07:36:30.38#ibcon#end of sib2, iclass 20, count 0 2006.245.07:36:30.38#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:36:30.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:36:30.38#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:36:30.38#ibcon#*before write, iclass 20, count 0 2006.245.07:36:30.38#ibcon#enter sib2, iclass 20, count 0 2006.245.07:36:30.38#ibcon#flushed, iclass 20, count 0 2006.245.07:36:30.38#ibcon#about to write, iclass 20, count 0 2006.245.07:36:30.38#ibcon#wrote, iclass 20, count 0 2006.245.07:36:30.38#ibcon#about to read 3, iclass 20, count 0 2006.245.07:36:30.42#ibcon#read 3, iclass 20, count 0 2006.245.07:36:30.42#ibcon#about to read 4, iclass 20, count 0 2006.245.07:36:30.42#ibcon#read 4, iclass 20, count 0 2006.245.07:36:30.42#ibcon#about to read 5, iclass 20, count 0 2006.245.07:36:30.42#ibcon#read 5, iclass 20, count 0 2006.245.07:36:30.42#ibcon#about to read 6, iclass 20, count 0 2006.245.07:36:30.42#ibcon#read 6, iclass 20, count 0 2006.245.07:36:30.42#ibcon#end of sib2, iclass 20, count 0 2006.245.07:36:30.42#ibcon#*after write, iclass 20, count 0 2006.245.07:36:30.42#ibcon#*before return 0, iclass 20, count 0 2006.245.07:36:30.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:30.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:30.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:36:30.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:36:30.42$vc4f8/va=3,6 2006.245.07:36:30.42#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.07:36:30.42#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.07:36:30.42#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:30.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:30.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:30.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:30.47#ibcon#enter wrdev, iclass 22, count 2 2006.245.07:36:30.47#ibcon#first serial, iclass 22, count 2 2006.245.07:36:30.47#ibcon#enter sib2, iclass 22, count 2 2006.245.07:36:30.47#ibcon#flushed, iclass 22, count 2 2006.245.07:36:30.47#ibcon#about to write, iclass 22, count 2 2006.245.07:36:30.47#ibcon#wrote, iclass 22, count 2 2006.245.07:36:30.47#ibcon#about to read 3, iclass 22, count 2 2006.245.07:36:30.49#ibcon#read 3, iclass 22, count 2 2006.245.07:36:30.49#ibcon#about to read 4, iclass 22, count 2 2006.245.07:36:30.49#ibcon#read 4, iclass 22, count 2 2006.245.07:36:30.49#ibcon#about to read 5, iclass 22, count 2 2006.245.07:36:30.49#ibcon#read 5, iclass 22, count 2 2006.245.07:36:30.49#ibcon#about to read 6, iclass 22, count 2 2006.245.07:36:30.49#ibcon#read 6, iclass 22, count 2 2006.245.07:36:30.49#ibcon#end of sib2, iclass 22, count 2 2006.245.07:36:30.49#ibcon#*mode == 0, iclass 22, count 2 2006.245.07:36:30.49#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.07:36:30.49#ibcon#[25=AT03-06\r\n] 2006.245.07:36:30.49#ibcon#*before write, iclass 22, count 2 2006.245.07:36:30.49#ibcon#enter sib2, iclass 22, count 2 2006.245.07:36:30.49#ibcon#flushed, iclass 22, count 2 2006.245.07:36:30.49#ibcon#about to write, iclass 22, count 2 2006.245.07:36:30.49#ibcon#wrote, iclass 22, count 2 2006.245.07:36:30.49#ibcon#about to read 3, iclass 22, count 2 2006.245.07:36:30.52#ibcon#read 3, iclass 22, count 2 2006.245.07:36:30.52#ibcon#about to read 4, iclass 22, count 2 2006.245.07:36:30.52#ibcon#read 4, iclass 22, count 2 2006.245.07:36:30.52#ibcon#about to read 5, iclass 22, count 2 2006.245.07:36:30.52#ibcon#read 5, iclass 22, count 2 2006.245.07:36:30.52#ibcon#about to read 6, iclass 22, count 2 2006.245.07:36:30.52#ibcon#read 6, iclass 22, count 2 2006.245.07:36:30.52#ibcon#end of sib2, iclass 22, count 2 2006.245.07:36:30.52#ibcon#*after write, iclass 22, count 2 2006.245.07:36:30.52#ibcon#*before return 0, iclass 22, count 2 2006.245.07:36:30.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:30.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:30.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.07:36:30.52#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:30.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:30.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:30.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:30.64#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:36:30.64#ibcon#first serial, iclass 22, count 0 2006.245.07:36:30.64#ibcon#enter sib2, iclass 22, count 0 2006.245.07:36:30.64#ibcon#flushed, iclass 22, count 0 2006.245.07:36:30.64#ibcon#about to write, iclass 22, count 0 2006.245.07:36:30.64#ibcon#wrote, iclass 22, count 0 2006.245.07:36:30.64#ibcon#about to read 3, iclass 22, count 0 2006.245.07:36:30.66#ibcon#read 3, iclass 22, count 0 2006.245.07:36:30.66#ibcon#about to read 4, iclass 22, count 0 2006.245.07:36:30.66#ibcon#read 4, iclass 22, count 0 2006.245.07:36:30.66#ibcon#about to read 5, iclass 22, count 0 2006.245.07:36:30.66#ibcon#read 5, iclass 22, count 0 2006.245.07:36:30.66#ibcon#about to read 6, iclass 22, count 0 2006.245.07:36:30.66#ibcon#read 6, iclass 22, count 0 2006.245.07:36:30.66#ibcon#end of sib2, iclass 22, count 0 2006.245.07:36:30.66#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:36:30.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:36:30.66#ibcon#[25=USB\r\n] 2006.245.07:36:30.66#ibcon#*before write, iclass 22, count 0 2006.245.07:36:30.66#ibcon#enter sib2, iclass 22, count 0 2006.245.07:36:30.66#ibcon#flushed, iclass 22, count 0 2006.245.07:36:30.66#ibcon#about to write, iclass 22, count 0 2006.245.07:36:30.66#ibcon#wrote, iclass 22, count 0 2006.245.07:36:30.66#ibcon#about to read 3, iclass 22, count 0 2006.245.07:36:30.69#ibcon#read 3, iclass 22, count 0 2006.245.07:36:30.69#ibcon#about to read 4, iclass 22, count 0 2006.245.07:36:30.69#ibcon#read 4, iclass 22, count 0 2006.245.07:36:30.69#ibcon#about to read 5, iclass 22, count 0 2006.245.07:36:30.69#ibcon#read 5, iclass 22, count 0 2006.245.07:36:30.69#ibcon#about to read 6, iclass 22, count 0 2006.245.07:36:30.69#ibcon#read 6, iclass 22, count 0 2006.245.07:36:30.69#ibcon#end of sib2, iclass 22, count 0 2006.245.07:36:30.69#ibcon#*after write, iclass 22, count 0 2006.245.07:36:30.69#ibcon#*before return 0, iclass 22, count 0 2006.245.07:36:30.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:30.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:30.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:36:30.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:36:30.69$vc4f8/valo=4,832.99 2006.245.07:36:30.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.07:36:30.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.07:36:30.69#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:30.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:30.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:30.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:30.69#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:36:30.69#ibcon#first serial, iclass 24, count 0 2006.245.07:36:30.69#ibcon#enter sib2, iclass 24, count 0 2006.245.07:36:30.69#ibcon#flushed, iclass 24, count 0 2006.245.07:36:30.69#ibcon#about to write, iclass 24, count 0 2006.245.07:36:30.69#ibcon#wrote, iclass 24, count 0 2006.245.07:36:30.69#ibcon#about to read 3, iclass 24, count 0 2006.245.07:36:30.72#ibcon#read 3, iclass 24, count 0 2006.245.07:36:30.72#ibcon#about to read 4, iclass 24, count 0 2006.245.07:36:30.72#ibcon#read 4, iclass 24, count 0 2006.245.07:36:30.72#ibcon#about to read 5, iclass 24, count 0 2006.245.07:36:30.72#ibcon#read 5, iclass 24, count 0 2006.245.07:36:30.72#ibcon#about to read 6, iclass 24, count 0 2006.245.07:36:30.72#ibcon#read 6, iclass 24, count 0 2006.245.07:36:30.72#ibcon#end of sib2, iclass 24, count 0 2006.245.07:36:30.72#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:36:30.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:36:30.72#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:36:30.72#ibcon#*before write, iclass 24, count 0 2006.245.07:36:30.72#ibcon#enter sib2, iclass 24, count 0 2006.245.07:36:30.72#ibcon#flushed, iclass 24, count 0 2006.245.07:36:30.72#ibcon#about to write, iclass 24, count 0 2006.245.07:36:30.72#ibcon#wrote, iclass 24, count 0 2006.245.07:36:30.72#ibcon#about to read 3, iclass 24, count 0 2006.245.07:36:30.76#ibcon#read 3, iclass 24, count 0 2006.245.07:36:30.76#ibcon#about to read 4, iclass 24, count 0 2006.245.07:36:30.76#ibcon#read 4, iclass 24, count 0 2006.245.07:36:30.76#ibcon#about to read 5, iclass 24, count 0 2006.245.07:36:30.76#ibcon#read 5, iclass 24, count 0 2006.245.07:36:30.76#ibcon#about to read 6, iclass 24, count 0 2006.245.07:36:30.76#ibcon#read 6, iclass 24, count 0 2006.245.07:36:30.76#ibcon#end of sib2, iclass 24, count 0 2006.245.07:36:30.76#ibcon#*after write, iclass 24, count 0 2006.245.07:36:30.76#ibcon#*before return 0, iclass 24, count 0 2006.245.07:36:30.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:30.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:30.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:36:30.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:36:30.76$vc4f8/va=4,7 2006.245.07:36:30.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.07:36:30.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.07:36:30.76#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:30.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:30.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:30.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:30.81#ibcon#enter wrdev, iclass 26, count 2 2006.245.07:36:30.81#ibcon#first serial, iclass 26, count 2 2006.245.07:36:30.81#ibcon#enter sib2, iclass 26, count 2 2006.245.07:36:30.81#ibcon#flushed, iclass 26, count 2 2006.245.07:36:30.81#ibcon#about to write, iclass 26, count 2 2006.245.07:36:30.81#ibcon#wrote, iclass 26, count 2 2006.245.07:36:30.81#ibcon#about to read 3, iclass 26, count 2 2006.245.07:36:30.83#ibcon#read 3, iclass 26, count 2 2006.245.07:36:30.83#ibcon#about to read 4, iclass 26, count 2 2006.245.07:36:30.83#ibcon#read 4, iclass 26, count 2 2006.245.07:36:30.83#ibcon#about to read 5, iclass 26, count 2 2006.245.07:36:30.83#ibcon#read 5, iclass 26, count 2 2006.245.07:36:30.83#ibcon#about to read 6, iclass 26, count 2 2006.245.07:36:30.83#ibcon#read 6, iclass 26, count 2 2006.245.07:36:30.83#ibcon#end of sib2, iclass 26, count 2 2006.245.07:36:30.83#ibcon#*mode == 0, iclass 26, count 2 2006.245.07:36:30.83#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.07:36:30.83#ibcon#[25=AT04-07\r\n] 2006.245.07:36:30.83#ibcon#*before write, iclass 26, count 2 2006.245.07:36:30.83#ibcon#enter sib2, iclass 26, count 2 2006.245.07:36:30.83#ibcon#flushed, iclass 26, count 2 2006.245.07:36:30.83#ibcon#about to write, iclass 26, count 2 2006.245.07:36:30.83#ibcon#wrote, iclass 26, count 2 2006.245.07:36:30.83#ibcon#about to read 3, iclass 26, count 2 2006.245.07:36:30.86#ibcon#read 3, iclass 26, count 2 2006.245.07:36:30.86#ibcon#about to read 4, iclass 26, count 2 2006.245.07:36:30.86#ibcon#read 4, iclass 26, count 2 2006.245.07:36:30.86#ibcon#about to read 5, iclass 26, count 2 2006.245.07:36:30.86#ibcon#read 5, iclass 26, count 2 2006.245.07:36:30.86#ibcon#about to read 6, iclass 26, count 2 2006.245.07:36:30.86#ibcon#read 6, iclass 26, count 2 2006.245.07:36:30.86#ibcon#end of sib2, iclass 26, count 2 2006.245.07:36:30.86#ibcon#*after write, iclass 26, count 2 2006.245.07:36:30.86#ibcon#*before return 0, iclass 26, count 2 2006.245.07:36:30.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:30.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:30.86#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.07:36:30.86#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:30.86#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:30.98#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:30.98#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:30.98#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:36:30.98#ibcon#first serial, iclass 26, count 0 2006.245.07:36:30.98#ibcon#enter sib2, iclass 26, count 0 2006.245.07:36:30.98#ibcon#flushed, iclass 26, count 0 2006.245.07:36:30.98#ibcon#about to write, iclass 26, count 0 2006.245.07:36:30.98#ibcon#wrote, iclass 26, count 0 2006.245.07:36:30.98#ibcon#about to read 3, iclass 26, count 0 2006.245.07:36:31.00#ibcon#read 3, iclass 26, count 0 2006.245.07:36:31.00#ibcon#about to read 4, iclass 26, count 0 2006.245.07:36:31.00#ibcon#read 4, iclass 26, count 0 2006.245.07:36:31.00#ibcon#about to read 5, iclass 26, count 0 2006.245.07:36:31.00#ibcon#read 5, iclass 26, count 0 2006.245.07:36:31.00#ibcon#about to read 6, iclass 26, count 0 2006.245.07:36:31.00#ibcon#read 6, iclass 26, count 0 2006.245.07:36:31.00#ibcon#end of sib2, iclass 26, count 0 2006.245.07:36:31.00#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:36:31.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:36:31.00#ibcon#[25=USB\r\n] 2006.245.07:36:31.00#ibcon#*before write, iclass 26, count 0 2006.245.07:36:31.00#ibcon#enter sib2, iclass 26, count 0 2006.245.07:36:31.00#ibcon#flushed, iclass 26, count 0 2006.245.07:36:31.00#ibcon#about to write, iclass 26, count 0 2006.245.07:36:31.00#ibcon#wrote, iclass 26, count 0 2006.245.07:36:31.00#ibcon#about to read 3, iclass 26, count 0 2006.245.07:36:31.03#ibcon#read 3, iclass 26, count 0 2006.245.07:36:31.03#ibcon#about to read 4, iclass 26, count 0 2006.245.07:36:31.03#ibcon#read 4, iclass 26, count 0 2006.245.07:36:31.03#ibcon#about to read 5, iclass 26, count 0 2006.245.07:36:31.03#ibcon#read 5, iclass 26, count 0 2006.245.07:36:31.03#ibcon#about to read 6, iclass 26, count 0 2006.245.07:36:31.03#ibcon#read 6, iclass 26, count 0 2006.245.07:36:31.03#ibcon#end of sib2, iclass 26, count 0 2006.245.07:36:31.03#ibcon#*after write, iclass 26, count 0 2006.245.07:36:31.03#ibcon#*before return 0, iclass 26, count 0 2006.245.07:36:31.03#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:31.03#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:31.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:36:31.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:36:31.03$vc4f8/valo=5,652.99 2006.245.07:36:31.03#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:36:31.03#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:36:31.03#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:31.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:31.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:31.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:31.03#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:36:31.03#ibcon#first serial, iclass 28, count 0 2006.245.07:36:31.03#ibcon#enter sib2, iclass 28, count 0 2006.245.07:36:31.03#ibcon#flushed, iclass 28, count 0 2006.245.07:36:31.03#ibcon#about to write, iclass 28, count 0 2006.245.07:36:31.03#ibcon#wrote, iclass 28, count 0 2006.245.07:36:31.03#ibcon#about to read 3, iclass 28, count 0 2006.245.07:36:31.05#ibcon#read 3, iclass 28, count 0 2006.245.07:36:31.05#ibcon#about to read 4, iclass 28, count 0 2006.245.07:36:31.05#ibcon#read 4, iclass 28, count 0 2006.245.07:36:31.05#ibcon#about to read 5, iclass 28, count 0 2006.245.07:36:31.05#ibcon#read 5, iclass 28, count 0 2006.245.07:36:31.05#ibcon#about to read 6, iclass 28, count 0 2006.245.07:36:31.05#ibcon#read 6, iclass 28, count 0 2006.245.07:36:31.05#ibcon#end of sib2, iclass 28, count 0 2006.245.07:36:31.05#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:36:31.05#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:36:31.05#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:36:31.05#ibcon#*before write, iclass 28, count 0 2006.245.07:36:31.05#ibcon#enter sib2, iclass 28, count 0 2006.245.07:36:31.05#ibcon#flushed, iclass 28, count 0 2006.245.07:36:31.05#ibcon#about to write, iclass 28, count 0 2006.245.07:36:31.05#ibcon#wrote, iclass 28, count 0 2006.245.07:36:31.05#ibcon#about to read 3, iclass 28, count 0 2006.245.07:36:31.09#ibcon#read 3, iclass 28, count 0 2006.245.07:36:31.09#ibcon#about to read 4, iclass 28, count 0 2006.245.07:36:31.09#ibcon#read 4, iclass 28, count 0 2006.245.07:36:31.09#ibcon#about to read 5, iclass 28, count 0 2006.245.07:36:31.09#ibcon#read 5, iclass 28, count 0 2006.245.07:36:31.09#ibcon#about to read 6, iclass 28, count 0 2006.245.07:36:31.09#ibcon#read 6, iclass 28, count 0 2006.245.07:36:31.09#ibcon#end of sib2, iclass 28, count 0 2006.245.07:36:31.09#ibcon#*after write, iclass 28, count 0 2006.245.07:36:31.09#ibcon#*before return 0, iclass 28, count 0 2006.245.07:36:31.09#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:31.09#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:31.09#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:36:31.09#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:36:31.09$vc4f8/va=5,7 2006.245.07:36:31.09#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.07:36:31.09#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.07:36:31.09#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:31.09#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:31.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:31.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:31.15#ibcon#enter wrdev, iclass 30, count 2 2006.245.07:36:31.15#ibcon#first serial, iclass 30, count 2 2006.245.07:36:31.15#ibcon#enter sib2, iclass 30, count 2 2006.245.07:36:31.15#ibcon#flushed, iclass 30, count 2 2006.245.07:36:31.15#ibcon#about to write, iclass 30, count 2 2006.245.07:36:31.15#ibcon#wrote, iclass 30, count 2 2006.245.07:36:31.15#ibcon#about to read 3, iclass 30, count 2 2006.245.07:36:31.17#ibcon#read 3, iclass 30, count 2 2006.245.07:36:31.17#ibcon#about to read 4, iclass 30, count 2 2006.245.07:36:31.17#ibcon#read 4, iclass 30, count 2 2006.245.07:36:31.17#ibcon#about to read 5, iclass 30, count 2 2006.245.07:36:31.17#ibcon#read 5, iclass 30, count 2 2006.245.07:36:31.17#ibcon#about to read 6, iclass 30, count 2 2006.245.07:36:31.17#ibcon#read 6, iclass 30, count 2 2006.245.07:36:31.17#ibcon#end of sib2, iclass 30, count 2 2006.245.07:36:31.17#ibcon#*mode == 0, iclass 30, count 2 2006.245.07:36:31.17#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.07:36:31.17#ibcon#[25=AT05-07\r\n] 2006.245.07:36:31.17#ibcon#*before write, iclass 30, count 2 2006.245.07:36:31.17#ibcon#enter sib2, iclass 30, count 2 2006.245.07:36:31.17#ibcon#flushed, iclass 30, count 2 2006.245.07:36:31.17#ibcon#about to write, iclass 30, count 2 2006.245.07:36:31.17#ibcon#wrote, iclass 30, count 2 2006.245.07:36:31.17#ibcon#about to read 3, iclass 30, count 2 2006.245.07:36:31.20#ibcon#read 3, iclass 30, count 2 2006.245.07:36:31.20#ibcon#about to read 4, iclass 30, count 2 2006.245.07:36:31.20#ibcon#read 4, iclass 30, count 2 2006.245.07:36:31.20#ibcon#about to read 5, iclass 30, count 2 2006.245.07:36:31.20#ibcon#read 5, iclass 30, count 2 2006.245.07:36:31.20#ibcon#about to read 6, iclass 30, count 2 2006.245.07:36:31.20#ibcon#read 6, iclass 30, count 2 2006.245.07:36:31.20#ibcon#end of sib2, iclass 30, count 2 2006.245.07:36:31.20#ibcon#*after write, iclass 30, count 2 2006.245.07:36:31.20#ibcon#*before return 0, iclass 30, count 2 2006.245.07:36:31.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:31.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:31.20#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.07:36:31.20#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:31.20#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:31.32#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:31.32#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:31.32#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:36:31.32#ibcon#first serial, iclass 30, count 0 2006.245.07:36:31.32#ibcon#enter sib2, iclass 30, count 0 2006.245.07:36:31.32#ibcon#flushed, iclass 30, count 0 2006.245.07:36:31.32#ibcon#about to write, iclass 30, count 0 2006.245.07:36:31.32#ibcon#wrote, iclass 30, count 0 2006.245.07:36:31.32#ibcon#about to read 3, iclass 30, count 0 2006.245.07:36:31.34#ibcon#read 3, iclass 30, count 0 2006.245.07:36:31.34#ibcon#about to read 4, iclass 30, count 0 2006.245.07:36:31.34#ibcon#read 4, iclass 30, count 0 2006.245.07:36:31.34#ibcon#about to read 5, iclass 30, count 0 2006.245.07:36:31.34#ibcon#read 5, iclass 30, count 0 2006.245.07:36:31.34#ibcon#about to read 6, iclass 30, count 0 2006.245.07:36:31.34#ibcon#read 6, iclass 30, count 0 2006.245.07:36:31.34#ibcon#end of sib2, iclass 30, count 0 2006.245.07:36:31.34#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:36:31.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:36:31.34#ibcon#[25=USB\r\n] 2006.245.07:36:31.34#ibcon#*before write, iclass 30, count 0 2006.245.07:36:31.34#ibcon#enter sib2, iclass 30, count 0 2006.245.07:36:31.34#ibcon#flushed, iclass 30, count 0 2006.245.07:36:31.34#ibcon#about to write, iclass 30, count 0 2006.245.07:36:31.34#ibcon#wrote, iclass 30, count 0 2006.245.07:36:31.34#ibcon#about to read 3, iclass 30, count 0 2006.245.07:36:31.37#ibcon#read 3, iclass 30, count 0 2006.245.07:36:31.37#ibcon#about to read 4, iclass 30, count 0 2006.245.07:36:31.37#ibcon#read 4, iclass 30, count 0 2006.245.07:36:31.37#ibcon#about to read 5, iclass 30, count 0 2006.245.07:36:31.37#ibcon#read 5, iclass 30, count 0 2006.245.07:36:31.37#ibcon#about to read 6, iclass 30, count 0 2006.245.07:36:31.37#ibcon#read 6, iclass 30, count 0 2006.245.07:36:31.37#ibcon#end of sib2, iclass 30, count 0 2006.245.07:36:31.37#ibcon#*after write, iclass 30, count 0 2006.245.07:36:31.37#ibcon#*before return 0, iclass 30, count 0 2006.245.07:36:31.37#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:31.37#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:31.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:36:31.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:36:31.37$vc4f8/valo=6,772.99 2006.245.07:36:31.37#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.07:36:31.37#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.07:36:31.37#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:31.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:31.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:31.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:31.37#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:36:31.37#ibcon#first serial, iclass 32, count 0 2006.245.07:36:31.37#ibcon#enter sib2, iclass 32, count 0 2006.245.07:36:31.37#ibcon#flushed, iclass 32, count 0 2006.245.07:36:31.37#ibcon#about to write, iclass 32, count 0 2006.245.07:36:31.37#ibcon#wrote, iclass 32, count 0 2006.245.07:36:31.37#ibcon#about to read 3, iclass 32, count 0 2006.245.07:36:31.40#ibcon#read 3, iclass 32, count 0 2006.245.07:36:31.40#ibcon#about to read 4, iclass 32, count 0 2006.245.07:36:31.40#ibcon#read 4, iclass 32, count 0 2006.245.07:36:31.40#ibcon#about to read 5, iclass 32, count 0 2006.245.07:36:31.40#ibcon#read 5, iclass 32, count 0 2006.245.07:36:31.40#ibcon#about to read 6, iclass 32, count 0 2006.245.07:36:31.40#ibcon#read 6, iclass 32, count 0 2006.245.07:36:31.40#ibcon#end of sib2, iclass 32, count 0 2006.245.07:36:31.40#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:36:31.40#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:36:31.40#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:36:31.40#ibcon#*before write, iclass 32, count 0 2006.245.07:36:31.40#ibcon#enter sib2, iclass 32, count 0 2006.245.07:36:31.40#ibcon#flushed, iclass 32, count 0 2006.245.07:36:31.40#ibcon#about to write, iclass 32, count 0 2006.245.07:36:31.40#ibcon#wrote, iclass 32, count 0 2006.245.07:36:31.40#ibcon#about to read 3, iclass 32, count 0 2006.245.07:36:31.44#ibcon#read 3, iclass 32, count 0 2006.245.07:36:31.44#ibcon#about to read 4, iclass 32, count 0 2006.245.07:36:31.44#ibcon#read 4, iclass 32, count 0 2006.245.07:36:31.44#ibcon#about to read 5, iclass 32, count 0 2006.245.07:36:31.44#ibcon#read 5, iclass 32, count 0 2006.245.07:36:31.44#ibcon#about to read 6, iclass 32, count 0 2006.245.07:36:31.44#ibcon#read 6, iclass 32, count 0 2006.245.07:36:31.44#ibcon#end of sib2, iclass 32, count 0 2006.245.07:36:31.44#ibcon#*after write, iclass 32, count 0 2006.245.07:36:31.44#ibcon#*before return 0, iclass 32, count 0 2006.245.07:36:31.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:31.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:31.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:36:31.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:36:31.44$vc4f8/va=6,7 2006.245.07:36:31.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.07:36:31.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.07:36:31.44#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:31.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:36:31.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:36:31.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:36:31.49#ibcon#enter wrdev, iclass 34, count 2 2006.245.07:36:31.49#ibcon#first serial, iclass 34, count 2 2006.245.07:36:31.49#ibcon#enter sib2, iclass 34, count 2 2006.245.07:36:31.49#ibcon#flushed, iclass 34, count 2 2006.245.07:36:31.49#ibcon#about to write, iclass 34, count 2 2006.245.07:36:31.49#ibcon#wrote, iclass 34, count 2 2006.245.07:36:31.49#ibcon#about to read 3, iclass 34, count 2 2006.245.07:36:31.51#ibcon#read 3, iclass 34, count 2 2006.245.07:36:31.51#ibcon#about to read 4, iclass 34, count 2 2006.245.07:36:31.51#ibcon#read 4, iclass 34, count 2 2006.245.07:36:31.51#ibcon#about to read 5, iclass 34, count 2 2006.245.07:36:31.51#ibcon#read 5, iclass 34, count 2 2006.245.07:36:31.51#ibcon#about to read 6, iclass 34, count 2 2006.245.07:36:31.51#ibcon#read 6, iclass 34, count 2 2006.245.07:36:31.51#ibcon#end of sib2, iclass 34, count 2 2006.245.07:36:31.51#ibcon#*mode == 0, iclass 34, count 2 2006.245.07:36:31.51#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.07:36:31.51#ibcon#[25=AT06-07\r\n] 2006.245.07:36:31.51#ibcon#*before write, iclass 34, count 2 2006.245.07:36:31.51#ibcon#enter sib2, iclass 34, count 2 2006.245.07:36:31.51#ibcon#flushed, iclass 34, count 2 2006.245.07:36:31.51#ibcon#about to write, iclass 34, count 2 2006.245.07:36:31.51#ibcon#wrote, iclass 34, count 2 2006.245.07:36:31.51#ibcon#about to read 3, iclass 34, count 2 2006.245.07:36:31.54#ibcon#read 3, iclass 34, count 2 2006.245.07:36:31.54#ibcon#about to read 4, iclass 34, count 2 2006.245.07:36:31.54#ibcon#read 4, iclass 34, count 2 2006.245.07:36:31.54#ibcon#about to read 5, iclass 34, count 2 2006.245.07:36:31.54#ibcon#read 5, iclass 34, count 2 2006.245.07:36:31.54#ibcon#about to read 6, iclass 34, count 2 2006.245.07:36:31.54#ibcon#read 6, iclass 34, count 2 2006.245.07:36:31.54#ibcon#end of sib2, iclass 34, count 2 2006.245.07:36:31.54#ibcon#*after write, iclass 34, count 2 2006.245.07:36:31.54#ibcon#*before return 0, iclass 34, count 2 2006.245.07:36:31.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:36:31.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:36:31.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.07:36:31.54#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:31.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:36:31.66#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:36:31.66#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:36:31.66#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:36:31.66#ibcon#first serial, iclass 34, count 0 2006.245.07:36:31.66#ibcon#enter sib2, iclass 34, count 0 2006.245.07:36:31.66#ibcon#flushed, iclass 34, count 0 2006.245.07:36:31.66#ibcon#about to write, iclass 34, count 0 2006.245.07:36:31.66#ibcon#wrote, iclass 34, count 0 2006.245.07:36:31.66#ibcon#about to read 3, iclass 34, count 0 2006.245.07:36:31.68#ibcon#read 3, iclass 34, count 0 2006.245.07:36:31.68#ibcon#about to read 4, iclass 34, count 0 2006.245.07:36:31.68#ibcon#read 4, iclass 34, count 0 2006.245.07:36:31.68#ibcon#about to read 5, iclass 34, count 0 2006.245.07:36:31.68#ibcon#read 5, iclass 34, count 0 2006.245.07:36:31.68#ibcon#about to read 6, iclass 34, count 0 2006.245.07:36:31.68#ibcon#read 6, iclass 34, count 0 2006.245.07:36:31.68#ibcon#end of sib2, iclass 34, count 0 2006.245.07:36:31.68#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:36:31.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:36:31.68#ibcon#[25=USB\r\n] 2006.245.07:36:31.68#ibcon#*before write, iclass 34, count 0 2006.245.07:36:31.68#ibcon#enter sib2, iclass 34, count 0 2006.245.07:36:31.68#ibcon#flushed, iclass 34, count 0 2006.245.07:36:31.68#ibcon#about to write, iclass 34, count 0 2006.245.07:36:31.68#ibcon#wrote, iclass 34, count 0 2006.245.07:36:31.68#ibcon#about to read 3, iclass 34, count 0 2006.245.07:36:31.71#ibcon#read 3, iclass 34, count 0 2006.245.07:36:31.71#ibcon#about to read 4, iclass 34, count 0 2006.245.07:36:31.71#ibcon#read 4, iclass 34, count 0 2006.245.07:36:31.71#ibcon#about to read 5, iclass 34, count 0 2006.245.07:36:31.71#ibcon#read 5, iclass 34, count 0 2006.245.07:36:31.71#ibcon#about to read 6, iclass 34, count 0 2006.245.07:36:31.71#ibcon#read 6, iclass 34, count 0 2006.245.07:36:31.71#ibcon#end of sib2, iclass 34, count 0 2006.245.07:36:31.71#ibcon#*after write, iclass 34, count 0 2006.245.07:36:31.71#ibcon#*before return 0, iclass 34, count 0 2006.245.07:36:31.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:36:31.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:36:31.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:36:31.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:36:31.71$vc4f8/valo=7,832.99 2006.245.07:36:31.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.07:36:31.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.07:36:31.71#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:31.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:36:31.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:36:31.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:36:31.71#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:36:31.71#ibcon#first serial, iclass 36, count 0 2006.245.07:36:31.71#ibcon#enter sib2, iclass 36, count 0 2006.245.07:36:31.71#ibcon#flushed, iclass 36, count 0 2006.245.07:36:31.71#ibcon#about to write, iclass 36, count 0 2006.245.07:36:31.71#ibcon#wrote, iclass 36, count 0 2006.245.07:36:31.71#ibcon#about to read 3, iclass 36, count 0 2006.245.07:36:31.73#ibcon#read 3, iclass 36, count 0 2006.245.07:36:31.73#ibcon#about to read 4, iclass 36, count 0 2006.245.07:36:31.73#ibcon#read 4, iclass 36, count 0 2006.245.07:36:31.73#ibcon#about to read 5, iclass 36, count 0 2006.245.07:36:31.73#ibcon#read 5, iclass 36, count 0 2006.245.07:36:31.73#ibcon#about to read 6, iclass 36, count 0 2006.245.07:36:31.73#ibcon#read 6, iclass 36, count 0 2006.245.07:36:31.73#ibcon#end of sib2, iclass 36, count 0 2006.245.07:36:31.73#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:36:31.73#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:36:31.73#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:36:31.73#ibcon#*before write, iclass 36, count 0 2006.245.07:36:31.73#ibcon#enter sib2, iclass 36, count 0 2006.245.07:36:31.73#ibcon#flushed, iclass 36, count 0 2006.245.07:36:31.73#ibcon#about to write, iclass 36, count 0 2006.245.07:36:31.73#ibcon#wrote, iclass 36, count 0 2006.245.07:36:31.73#ibcon#about to read 3, iclass 36, count 0 2006.245.07:36:31.77#ibcon#read 3, iclass 36, count 0 2006.245.07:36:31.77#ibcon#about to read 4, iclass 36, count 0 2006.245.07:36:31.77#ibcon#read 4, iclass 36, count 0 2006.245.07:36:31.77#ibcon#about to read 5, iclass 36, count 0 2006.245.07:36:31.77#ibcon#read 5, iclass 36, count 0 2006.245.07:36:31.77#ibcon#about to read 6, iclass 36, count 0 2006.245.07:36:31.77#ibcon#read 6, iclass 36, count 0 2006.245.07:36:31.77#ibcon#end of sib2, iclass 36, count 0 2006.245.07:36:31.77#ibcon#*after write, iclass 36, count 0 2006.245.07:36:31.77#ibcon#*before return 0, iclass 36, count 0 2006.245.07:36:31.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:36:31.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:36:31.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:36:31.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:36:31.77$vc4f8/va=7,7 2006.245.07:36:31.77#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.07:36:31.77#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.07:36:31.77#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:31.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:36:31.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:36:31.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:36:31.83#ibcon#enter wrdev, iclass 38, count 2 2006.245.07:36:31.83#ibcon#first serial, iclass 38, count 2 2006.245.07:36:31.83#ibcon#enter sib2, iclass 38, count 2 2006.245.07:36:31.83#ibcon#flushed, iclass 38, count 2 2006.245.07:36:31.83#ibcon#about to write, iclass 38, count 2 2006.245.07:36:31.83#ibcon#wrote, iclass 38, count 2 2006.245.07:36:31.83#ibcon#about to read 3, iclass 38, count 2 2006.245.07:36:31.85#ibcon#read 3, iclass 38, count 2 2006.245.07:36:31.85#ibcon#about to read 4, iclass 38, count 2 2006.245.07:36:31.85#ibcon#read 4, iclass 38, count 2 2006.245.07:36:31.85#ibcon#about to read 5, iclass 38, count 2 2006.245.07:36:31.85#ibcon#read 5, iclass 38, count 2 2006.245.07:36:31.85#ibcon#about to read 6, iclass 38, count 2 2006.245.07:36:31.85#ibcon#read 6, iclass 38, count 2 2006.245.07:36:31.85#ibcon#end of sib2, iclass 38, count 2 2006.245.07:36:31.85#ibcon#*mode == 0, iclass 38, count 2 2006.245.07:36:31.85#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.07:36:31.85#ibcon#[25=AT07-07\r\n] 2006.245.07:36:31.85#ibcon#*before write, iclass 38, count 2 2006.245.07:36:31.85#ibcon#enter sib2, iclass 38, count 2 2006.245.07:36:31.85#ibcon#flushed, iclass 38, count 2 2006.245.07:36:31.85#ibcon#about to write, iclass 38, count 2 2006.245.07:36:31.85#ibcon#wrote, iclass 38, count 2 2006.245.07:36:31.85#ibcon#about to read 3, iclass 38, count 2 2006.245.07:36:31.88#ibcon#read 3, iclass 38, count 2 2006.245.07:36:31.88#ibcon#about to read 4, iclass 38, count 2 2006.245.07:36:31.88#ibcon#read 4, iclass 38, count 2 2006.245.07:36:31.88#ibcon#about to read 5, iclass 38, count 2 2006.245.07:36:31.88#ibcon#read 5, iclass 38, count 2 2006.245.07:36:31.88#ibcon#about to read 6, iclass 38, count 2 2006.245.07:36:31.88#ibcon#read 6, iclass 38, count 2 2006.245.07:36:31.88#ibcon#end of sib2, iclass 38, count 2 2006.245.07:36:31.88#ibcon#*after write, iclass 38, count 2 2006.245.07:36:31.88#ibcon#*before return 0, iclass 38, count 2 2006.245.07:36:31.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:36:31.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:36:31.88#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.07:36:31.88#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:31.88#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:36:32.00#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:36:32.00#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:36:32.00#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:36:32.00#ibcon#first serial, iclass 38, count 0 2006.245.07:36:32.00#ibcon#enter sib2, iclass 38, count 0 2006.245.07:36:32.00#ibcon#flushed, iclass 38, count 0 2006.245.07:36:32.00#ibcon#about to write, iclass 38, count 0 2006.245.07:36:32.00#ibcon#wrote, iclass 38, count 0 2006.245.07:36:32.00#ibcon#about to read 3, iclass 38, count 0 2006.245.07:36:32.02#ibcon#read 3, iclass 38, count 0 2006.245.07:36:32.02#ibcon#about to read 4, iclass 38, count 0 2006.245.07:36:32.02#ibcon#read 4, iclass 38, count 0 2006.245.07:36:32.02#ibcon#about to read 5, iclass 38, count 0 2006.245.07:36:32.02#ibcon#read 5, iclass 38, count 0 2006.245.07:36:32.02#ibcon#about to read 6, iclass 38, count 0 2006.245.07:36:32.02#ibcon#read 6, iclass 38, count 0 2006.245.07:36:32.02#ibcon#end of sib2, iclass 38, count 0 2006.245.07:36:32.02#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:36:32.02#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:36:32.02#ibcon#[25=USB\r\n] 2006.245.07:36:32.02#ibcon#*before write, iclass 38, count 0 2006.245.07:36:32.02#ibcon#enter sib2, iclass 38, count 0 2006.245.07:36:32.02#ibcon#flushed, iclass 38, count 0 2006.245.07:36:32.02#ibcon#about to write, iclass 38, count 0 2006.245.07:36:32.02#ibcon#wrote, iclass 38, count 0 2006.245.07:36:32.02#ibcon#about to read 3, iclass 38, count 0 2006.245.07:36:32.05#ibcon#read 3, iclass 38, count 0 2006.245.07:36:32.05#ibcon#about to read 4, iclass 38, count 0 2006.245.07:36:32.05#ibcon#read 4, iclass 38, count 0 2006.245.07:36:32.05#ibcon#about to read 5, iclass 38, count 0 2006.245.07:36:32.05#ibcon#read 5, iclass 38, count 0 2006.245.07:36:32.05#ibcon#about to read 6, iclass 38, count 0 2006.245.07:36:32.05#ibcon#read 6, iclass 38, count 0 2006.245.07:36:32.05#ibcon#end of sib2, iclass 38, count 0 2006.245.07:36:32.05#ibcon#*after write, iclass 38, count 0 2006.245.07:36:32.05#ibcon#*before return 0, iclass 38, count 0 2006.245.07:36:32.05#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:36:32.05#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:36:32.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:36:32.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:36:32.05$vc4f8/valo=8,852.99 2006.245.07:36:32.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.07:36:32.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.07:36:32.05#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:32.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:36:32.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:36:32.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:36:32.05#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:36:32.05#ibcon#first serial, iclass 40, count 0 2006.245.07:36:32.05#ibcon#enter sib2, iclass 40, count 0 2006.245.07:36:32.05#ibcon#flushed, iclass 40, count 0 2006.245.07:36:32.05#ibcon#about to write, iclass 40, count 0 2006.245.07:36:32.05#ibcon#wrote, iclass 40, count 0 2006.245.07:36:32.05#ibcon#about to read 3, iclass 40, count 0 2006.245.07:36:32.08#ibcon#read 3, iclass 40, count 0 2006.245.07:36:32.08#ibcon#about to read 4, iclass 40, count 0 2006.245.07:36:32.08#ibcon#read 4, iclass 40, count 0 2006.245.07:36:32.08#ibcon#about to read 5, iclass 40, count 0 2006.245.07:36:32.08#ibcon#read 5, iclass 40, count 0 2006.245.07:36:32.08#ibcon#about to read 6, iclass 40, count 0 2006.245.07:36:32.08#ibcon#read 6, iclass 40, count 0 2006.245.07:36:32.08#ibcon#end of sib2, iclass 40, count 0 2006.245.07:36:32.08#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:36:32.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:36:32.08#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:36:32.08#ibcon#*before write, iclass 40, count 0 2006.245.07:36:32.08#ibcon#enter sib2, iclass 40, count 0 2006.245.07:36:32.08#ibcon#flushed, iclass 40, count 0 2006.245.07:36:32.08#ibcon#about to write, iclass 40, count 0 2006.245.07:36:32.08#ibcon#wrote, iclass 40, count 0 2006.245.07:36:32.08#ibcon#about to read 3, iclass 40, count 0 2006.245.07:36:32.12#ibcon#read 3, iclass 40, count 0 2006.245.07:36:32.12#ibcon#about to read 4, iclass 40, count 0 2006.245.07:36:32.12#ibcon#read 4, iclass 40, count 0 2006.245.07:36:32.12#ibcon#about to read 5, iclass 40, count 0 2006.245.07:36:32.12#ibcon#read 5, iclass 40, count 0 2006.245.07:36:32.12#ibcon#about to read 6, iclass 40, count 0 2006.245.07:36:32.12#ibcon#read 6, iclass 40, count 0 2006.245.07:36:32.12#ibcon#end of sib2, iclass 40, count 0 2006.245.07:36:32.12#ibcon#*after write, iclass 40, count 0 2006.245.07:36:32.12#ibcon#*before return 0, iclass 40, count 0 2006.245.07:36:32.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:36:32.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:36:32.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:36:32.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:36:32.12$vc4f8/va=8,8 2006.245.07:36:32.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.07:36:32.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.07:36:32.12#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:32.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:36:32.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:36:32.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:36:32.17#ibcon#enter wrdev, iclass 4, count 2 2006.245.07:36:32.17#ibcon#first serial, iclass 4, count 2 2006.245.07:36:32.17#ibcon#enter sib2, iclass 4, count 2 2006.245.07:36:32.17#ibcon#flushed, iclass 4, count 2 2006.245.07:36:32.17#ibcon#about to write, iclass 4, count 2 2006.245.07:36:32.17#ibcon#wrote, iclass 4, count 2 2006.245.07:36:32.17#ibcon#about to read 3, iclass 4, count 2 2006.245.07:36:32.19#ibcon#read 3, iclass 4, count 2 2006.245.07:36:32.19#ibcon#about to read 4, iclass 4, count 2 2006.245.07:36:32.19#ibcon#read 4, iclass 4, count 2 2006.245.07:36:32.19#ibcon#about to read 5, iclass 4, count 2 2006.245.07:36:32.19#ibcon#read 5, iclass 4, count 2 2006.245.07:36:32.19#ibcon#about to read 6, iclass 4, count 2 2006.245.07:36:32.19#ibcon#read 6, iclass 4, count 2 2006.245.07:36:32.19#ibcon#end of sib2, iclass 4, count 2 2006.245.07:36:32.19#ibcon#*mode == 0, iclass 4, count 2 2006.245.07:36:32.19#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.07:36:32.19#ibcon#[25=AT08-08\r\n] 2006.245.07:36:32.19#ibcon#*before write, iclass 4, count 2 2006.245.07:36:32.19#ibcon#enter sib2, iclass 4, count 2 2006.245.07:36:32.19#ibcon#flushed, iclass 4, count 2 2006.245.07:36:32.19#ibcon#about to write, iclass 4, count 2 2006.245.07:36:32.19#ibcon#wrote, iclass 4, count 2 2006.245.07:36:32.19#ibcon#about to read 3, iclass 4, count 2 2006.245.07:36:32.22#ibcon#read 3, iclass 4, count 2 2006.245.07:36:32.22#ibcon#about to read 4, iclass 4, count 2 2006.245.07:36:32.22#ibcon#read 4, iclass 4, count 2 2006.245.07:36:32.22#ibcon#about to read 5, iclass 4, count 2 2006.245.07:36:32.22#ibcon#read 5, iclass 4, count 2 2006.245.07:36:32.22#ibcon#about to read 6, iclass 4, count 2 2006.245.07:36:32.22#ibcon#read 6, iclass 4, count 2 2006.245.07:36:32.22#ibcon#end of sib2, iclass 4, count 2 2006.245.07:36:32.22#ibcon#*after write, iclass 4, count 2 2006.245.07:36:32.22#ibcon#*before return 0, iclass 4, count 2 2006.245.07:36:32.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:36:32.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:36:32.22#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.07:36:32.22#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:32.22#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:36:32.34#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:36:32.34#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:36:32.34#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:36:32.34#ibcon#first serial, iclass 4, count 0 2006.245.07:36:32.34#ibcon#enter sib2, iclass 4, count 0 2006.245.07:36:32.34#ibcon#flushed, iclass 4, count 0 2006.245.07:36:32.34#ibcon#about to write, iclass 4, count 0 2006.245.07:36:32.34#ibcon#wrote, iclass 4, count 0 2006.245.07:36:32.34#ibcon#about to read 3, iclass 4, count 0 2006.245.07:36:32.36#ibcon#read 3, iclass 4, count 0 2006.245.07:36:32.36#ibcon#about to read 4, iclass 4, count 0 2006.245.07:36:32.36#ibcon#read 4, iclass 4, count 0 2006.245.07:36:32.36#ibcon#about to read 5, iclass 4, count 0 2006.245.07:36:32.36#ibcon#read 5, iclass 4, count 0 2006.245.07:36:32.36#ibcon#about to read 6, iclass 4, count 0 2006.245.07:36:32.36#ibcon#read 6, iclass 4, count 0 2006.245.07:36:32.36#ibcon#end of sib2, iclass 4, count 0 2006.245.07:36:32.36#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:36:32.36#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:36:32.36#ibcon#[25=USB\r\n] 2006.245.07:36:32.36#ibcon#*before write, iclass 4, count 0 2006.245.07:36:32.36#ibcon#enter sib2, iclass 4, count 0 2006.245.07:36:32.36#ibcon#flushed, iclass 4, count 0 2006.245.07:36:32.36#ibcon#about to write, iclass 4, count 0 2006.245.07:36:32.36#ibcon#wrote, iclass 4, count 0 2006.245.07:36:32.36#ibcon#about to read 3, iclass 4, count 0 2006.245.07:36:32.39#ibcon#read 3, iclass 4, count 0 2006.245.07:36:32.39#ibcon#about to read 4, iclass 4, count 0 2006.245.07:36:32.39#ibcon#read 4, iclass 4, count 0 2006.245.07:36:32.39#ibcon#about to read 5, iclass 4, count 0 2006.245.07:36:32.39#ibcon#read 5, iclass 4, count 0 2006.245.07:36:32.39#ibcon#about to read 6, iclass 4, count 0 2006.245.07:36:32.39#ibcon#read 6, iclass 4, count 0 2006.245.07:36:32.39#ibcon#end of sib2, iclass 4, count 0 2006.245.07:36:32.39#ibcon#*after write, iclass 4, count 0 2006.245.07:36:32.39#ibcon#*before return 0, iclass 4, count 0 2006.245.07:36:32.39#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:36:32.39#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:36:32.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:36:32.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:36:32.39$vc4f8/vblo=1,632.99 2006.245.07:36:32.39#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.07:36:32.39#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.07:36:32.39#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:32.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:36:32.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:36:32.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:36:32.39#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:36:32.39#ibcon#first serial, iclass 6, count 0 2006.245.07:36:32.39#ibcon#enter sib2, iclass 6, count 0 2006.245.07:36:32.39#ibcon#flushed, iclass 6, count 0 2006.245.07:36:32.39#ibcon#about to write, iclass 6, count 0 2006.245.07:36:32.39#ibcon#wrote, iclass 6, count 0 2006.245.07:36:32.39#ibcon#about to read 3, iclass 6, count 0 2006.245.07:36:32.42#ibcon#read 3, iclass 6, count 0 2006.245.07:36:32.42#ibcon#about to read 4, iclass 6, count 0 2006.245.07:36:32.42#ibcon#read 4, iclass 6, count 0 2006.245.07:36:32.42#ibcon#about to read 5, iclass 6, count 0 2006.245.07:36:32.42#ibcon#read 5, iclass 6, count 0 2006.245.07:36:32.42#ibcon#about to read 6, iclass 6, count 0 2006.245.07:36:32.42#ibcon#read 6, iclass 6, count 0 2006.245.07:36:32.42#ibcon#end of sib2, iclass 6, count 0 2006.245.07:36:32.42#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:36:32.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:36:32.42#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:36:32.42#ibcon#*before write, iclass 6, count 0 2006.245.07:36:32.42#ibcon#enter sib2, iclass 6, count 0 2006.245.07:36:32.42#ibcon#flushed, iclass 6, count 0 2006.245.07:36:32.42#ibcon#about to write, iclass 6, count 0 2006.245.07:36:32.42#ibcon#wrote, iclass 6, count 0 2006.245.07:36:32.42#ibcon#about to read 3, iclass 6, count 0 2006.245.07:36:32.46#ibcon#read 3, iclass 6, count 0 2006.245.07:36:32.46#ibcon#about to read 4, iclass 6, count 0 2006.245.07:36:32.46#ibcon#read 4, iclass 6, count 0 2006.245.07:36:32.46#ibcon#about to read 5, iclass 6, count 0 2006.245.07:36:32.46#ibcon#read 5, iclass 6, count 0 2006.245.07:36:32.46#ibcon#about to read 6, iclass 6, count 0 2006.245.07:36:32.46#ibcon#read 6, iclass 6, count 0 2006.245.07:36:32.46#ibcon#end of sib2, iclass 6, count 0 2006.245.07:36:32.46#ibcon#*after write, iclass 6, count 0 2006.245.07:36:32.46#ibcon#*before return 0, iclass 6, count 0 2006.245.07:36:32.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:36:32.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:36:32.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:36:32.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:36:32.46$vc4f8/vb=1,4 2006.245.07:36:32.46#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.07:36:32.46#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.07:36:32.46#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:32.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:36:32.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:36:32.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:36:32.46#ibcon#enter wrdev, iclass 10, count 2 2006.245.07:36:32.46#ibcon#first serial, iclass 10, count 2 2006.245.07:36:32.46#ibcon#enter sib2, iclass 10, count 2 2006.245.07:36:32.46#ibcon#flushed, iclass 10, count 2 2006.245.07:36:32.46#ibcon#about to write, iclass 10, count 2 2006.245.07:36:32.46#ibcon#wrote, iclass 10, count 2 2006.245.07:36:32.46#ibcon#about to read 3, iclass 10, count 2 2006.245.07:36:32.48#ibcon#read 3, iclass 10, count 2 2006.245.07:36:32.48#ibcon#about to read 4, iclass 10, count 2 2006.245.07:36:32.48#ibcon#read 4, iclass 10, count 2 2006.245.07:36:32.48#ibcon#about to read 5, iclass 10, count 2 2006.245.07:36:32.48#ibcon#read 5, iclass 10, count 2 2006.245.07:36:32.48#ibcon#about to read 6, iclass 10, count 2 2006.245.07:36:32.48#ibcon#read 6, iclass 10, count 2 2006.245.07:36:32.48#ibcon#end of sib2, iclass 10, count 2 2006.245.07:36:32.48#ibcon#*mode == 0, iclass 10, count 2 2006.245.07:36:32.48#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.07:36:32.48#ibcon#[27=AT01-04\r\n] 2006.245.07:36:32.48#ibcon#*before write, iclass 10, count 2 2006.245.07:36:32.48#ibcon#enter sib2, iclass 10, count 2 2006.245.07:36:32.48#ibcon#flushed, iclass 10, count 2 2006.245.07:36:32.48#ibcon#about to write, iclass 10, count 2 2006.245.07:36:32.48#ibcon#wrote, iclass 10, count 2 2006.245.07:36:32.48#ibcon#about to read 3, iclass 10, count 2 2006.245.07:36:32.51#ibcon#read 3, iclass 10, count 2 2006.245.07:36:32.51#ibcon#about to read 4, iclass 10, count 2 2006.245.07:36:32.51#ibcon#read 4, iclass 10, count 2 2006.245.07:36:32.51#ibcon#about to read 5, iclass 10, count 2 2006.245.07:36:32.51#ibcon#read 5, iclass 10, count 2 2006.245.07:36:32.51#ibcon#about to read 6, iclass 10, count 2 2006.245.07:36:32.51#ibcon#read 6, iclass 10, count 2 2006.245.07:36:32.51#ibcon#end of sib2, iclass 10, count 2 2006.245.07:36:32.51#ibcon#*after write, iclass 10, count 2 2006.245.07:36:32.51#ibcon#*before return 0, iclass 10, count 2 2006.245.07:36:32.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:36:32.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:36:32.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.07:36:32.51#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:32.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:36:32.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:36:32.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:36:32.63#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:36:32.63#ibcon#first serial, iclass 10, count 0 2006.245.07:36:32.63#ibcon#enter sib2, iclass 10, count 0 2006.245.07:36:32.63#ibcon#flushed, iclass 10, count 0 2006.245.07:36:32.63#ibcon#about to write, iclass 10, count 0 2006.245.07:36:32.63#ibcon#wrote, iclass 10, count 0 2006.245.07:36:32.63#ibcon#about to read 3, iclass 10, count 0 2006.245.07:36:32.65#ibcon#read 3, iclass 10, count 0 2006.245.07:36:32.65#ibcon#about to read 4, iclass 10, count 0 2006.245.07:36:32.65#ibcon#read 4, iclass 10, count 0 2006.245.07:36:32.65#ibcon#about to read 5, iclass 10, count 0 2006.245.07:36:32.65#ibcon#read 5, iclass 10, count 0 2006.245.07:36:32.65#ibcon#about to read 6, iclass 10, count 0 2006.245.07:36:32.65#ibcon#read 6, iclass 10, count 0 2006.245.07:36:32.65#ibcon#end of sib2, iclass 10, count 0 2006.245.07:36:32.65#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:36:32.65#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:36:32.65#ibcon#[27=USB\r\n] 2006.245.07:36:32.65#ibcon#*before write, iclass 10, count 0 2006.245.07:36:32.65#ibcon#enter sib2, iclass 10, count 0 2006.245.07:36:32.65#ibcon#flushed, iclass 10, count 0 2006.245.07:36:32.65#ibcon#about to write, iclass 10, count 0 2006.245.07:36:32.65#ibcon#wrote, iclass 10, count 0 2006.245.07:36:32.65#ibcon#about to read 3, iclass 10, count 0 2006.245.07:36:32.68#ibcon#read 3, iclass 10, count 0 2006.245.07:36:32.68#ibcon#about to read 4, iclass 10, count 0 2006.245.07:36:32.68#ibcon#read 4, iclass 10, count 0 2006.245.07:36:32.68#ibcon#about to read 5, iclass 10, count 0 2006.245.07:36:32.68#ibcon#read 5, iclass 10, count 0 2006.245.07:36:32.68#ibcon#about to read 6, iclass 10, count 0 2006.245.07:36:32.68#ibcon#read 6, iclass 10, count 0 2006.245.07:36:32.68#ibcon#end of sib2, iclass 10, count 0 2006.245.07:36:32.68#ibcon#*after write, iclass 10, count 0 2006.245.07:36:32.68#ibcon#*before return 0, iclass 10, count 0 2006.245.07:36:32.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:36:32.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:36:32.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:36:32.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:36:32.68$vc4f8/vblo=2,640.99 2006.245.07:36:32.68#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.07:36:32.68#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.07:36:32.68#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:32.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:32.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:32.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:32.68#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:36:32.68#ibcon#first serial, iclass 12, count 0 2006.245.07:36:32.68#ibcon#enter sib2, iclass 12, count 0 2006.245.07:36:32.68#ibcon#flushed, iclass 12, count 0 2006.245.07:36:32.68#ibcon#about to write, iclass 12, count 0 2006.245.07:36:32.68#ibcon#wrote, iclass 12, count 0 2006.245.07:36:32.68#ibcon#about to read 3, iclass 12, count 0 2006.245.07:36:32.70#ibcon#read 3, iclass 12, count 0 2006.245.07:36:32.70#ibcon#about to read 4, iclass 12, count 0 2006.245.07:36:32.70#ibcon#read 4, iclass 12, count 0 2006.245.07:36:32.70#ibcon#about to read 5, iclass 12, count 0 2006.245.07:36:32.70#ibcon#read 5, iclass 12, count 0 2006.245.07:36:32.70#ibcon#about to read 6, iclass 12, count 0 2006.245.07:36:32.70#ibcon#read 6, iclass 12, count 0 2006.245.07:36:32.70#ibcon#end of sib2, iclass 12, count 0 2006.245.07:36:32.70#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:36:32.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:36:32.70#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:36:32.70#ibcon#*before write, iclass 12, count 0 2006.245.07:36:32.70#ibcon#enter sib2, iclass 12, count 0 2006.245.07:36:32.70#ibcon#flushed, iclass 12, count 0 2006.245.07:36:32.70#ibcon#about to write, iclass 12, count 0 2006.245.07:36:32.70#ibcon#wrote, iclass 12, count 0 2006.245.07:36:32.70#ibcon#about to read 3, iclass 12, count 0 2006.245.07:36:32.74#ibcon#read 3, iclass 12, count 0 2006.245.07:36:32.74#ibcon#about to read 4, iclass 12, count 0 2006.245.07:36:32.74#ibcon#read 4, iclass 12, count 0 2006.245.07:36:32.74#ibcon#about to read 5, iclass 12, count 0 2006.245.07:36:32.74#ibcon#read 5, iclass 12, count 0 2006.245.07:36:32.74#ibcon#about to read 6, iclass 12, count 0 2006.245.07:36:32.74#ibcon#read 6, iclass 12, count 0 2006.245.07:36:32.74#ibcon#end of sib2, iclass 12, count 0 2006.245.07:36:32.74#ibcon#*after write, iclass 12, count 0 2006.245.07:36:32.74#ibcon#*before return 0, iclass 12, count 0 2006.245.07:36:32.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:32.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:36:32.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:36:32.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:36:32.74$vc4f8/vb=2,4 2006.245.07:36:32.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.07:36:32.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.07:36:32.74#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:32.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:32.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:32.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:32.80#ibcon#enter wrdev, iclass 14, count 2 2006.245.07:36:32.80#ibcon#first serial, iclass 14, count 2 2006.245.07:36:32.80#ibcon#enter sib2, iclass 14, count 2 2006.245.07:36:32.80#ibcon#flushed, iclass 14, count 2 2006.245.07:36:32.80#ibcon#about to write, iclass 14, count 2 2006.245.07:36:32.80#ibcon#wrote, iclass 14, count 2 2006.245.07:36:32.80#ibcon#about to read 3, iclass 14, count 2 2006.245.07:36:32.82#ibcon#read 3, iclass 14, count 2 2006.245.07:36:32.82#ibcon#about to read 4, iclass 14, count 2 2006.245.07:36:32.82#ibcon#read 4, iclass 14, count 2 2006.245.07:36:32.82#ibcon#about to read 5, iclass 14, count 2 2006.245.07:36:32.82#ibcon#read 5, iclass 14, count 2 2006.245.07:36:32.82#ibcon#about to read 6, iclass 14, count 2 2006.245.07:36:32.82#ibcon#read 6, iclass 14, count 2 2006.245.07:36:32.82#ibcon#end of sib2, iclass 14, count 2 2006.245.07:36:32.82#ibcon#*mode == 0, iclass 14, count 2 2006.245.07:36:32.82#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.07:36:32.82#ibcon#[27=AT02-04\r\n] 2006.245.07:36:32.82#ibcon#*before write, iclass 14, count 2 2006.245.07:36:32.82#ibcon#enter sib2, iclass 14, count 2 2006.245.07:36:32.82#ibcon#flushed, iclass 14, count 2 2006.245.07:36:32.82#ibcon#about to write, iclass 14, count 2 2006.245.07:36:32.82#ibcon#wrote, iclass 14, count 2 2006.245.07:36:32.82#ibcon#about to read 3, iclass 14, count 2 2006.245.07:36:32.85#ibcon#read 3, iclass 14, count 2 2006.245.07:36:32.85#ibcon#about to read 4, iclass 14, count 2 2006.245.07:36:32.85#ibcon#read 4, iclass 14, count 2 2006.245.07:36:32.85#ibcon#about to read 5, iclass 14, count 2 2006.245.07:36:32.85#ibcon#read 5, iclass 14, count 2 2006.245.07:36:32.85#ibcon#about to read 6, iclass 14, count 2 2006.245.07:36:32.85#ibcon#read 6, iclass 14, count 2 2006.245.07:36:32.85#ibcon#end of sib2, iclass 14, count 2 2006.245.07:36:32.85#ibcon#*after write, iclass 14, count 2 2006.245.07:36:32.85#ibcon#*before return 0, iclass 14, count 2 2006.245.07:36:32.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:32.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:36:32.85#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.07:36:32.85#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:32.85#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:32.97#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:32.97#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:32.97#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:36:32.97#ibcon#first serial, iclass 14, count 0 2006.245.07:36:32.97#ibcon#enter sib2, iclass 14, count 0 2006.245.07:36:32.97#ibcon#flushed, iclass 14, count 0 2006.245.07:36:32.97#ibcon#about to write, iclass 14, count 0 2006.245.07:36:32.97#ibcon#wrote, iclass 14, count 0 2006.245.07:36:32.97#ibcon#about to read 3, iclass 14, count 0 2006.245.07:36:32.99#ibcon#read 3, iclass 14, count 0 2006.245.07:36:32.99#ibcon#about to read 4, iclass 14, count 0 2006.245.07:36:32.99#ibcon#read 4, iclass 14, count 0 2006.245.07:36:32.99#ibcon#about to read 5, iclass 14, count 0 2006.245.07:36:32.99#ibcon#read 5, iclass 14, count 0 2006.245.07:36:32.99#ibcon#about to read 6, iclass 14, count 0 2006.245.07:36:32.99#ibcon#read 6, iclass 14, count 0 2006.245.07:36:32.99#ibcon#end of sib2, iclass 14, count 0 2006.245.07:36:32.99#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:36:32.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:36:32.99#ibcon#[27=USB\r\n] 2006.245.07:36:32.99#ibcon#*before write, iclass 14, count 0 2006.245.07:36:32.99#ibcon#enter sib2, iclass 14, count 0 2006.245.07:36:32.99#ibcon#flushed, iclass 14, count 0 2006.245.07:36:32.99#ibcon#about to write, iclass 14, count 0 2006.245.07:36:32.99#ibcon#wrote, iclass 14, count 0 2006.245.07:36:32.99#ibcon#about to read 3, iclass 14, count 0 2006.245.07:36:33.02#ibcon#read 3, iclass 14, count 0 2006.245.07:36:33.02#ibcon#about to read 4, iclass 14, count 0 2006.245.07:36:33.02#ibcon#read 4, iclass 14, count 0 2006.245.07:36:33.02#ibcon#about to read 5, iclass 14, count 0 2006.245.07:36:33.02#ibcon#read 5, iclass 14, count 0 2006.245.07:36:33.02#ibcon#about to read 6, iclass 14, count 0 2006.245.07:36:33.02#ibcon#read 6, iclass 14, count 0 2006.245.07:36:33.02#ibcon#end of sib2, iclass 14, count 0 2006.245.07:36:33.02#ibcon#*after write, iclass 14, count 0 2006.245.07:36:33.02#ibcon#*before return 0, iclass 14, count 0 2006.245.07:36:33.02#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:33.02#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:36:33.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:36:33.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:36:33.02$vc4f8/vblo=3,656.99 2006.245.07:36:33.02#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:36:33.02#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:36:33.02#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:33.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:33.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:33.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:33.02#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:36:33.02#ibcon#first serial, iclass 16, count 0 2006.245.07:36:33.02#ibcon#enter sib2, iclass 16, count 0 2006.245.07:36:33.02#ibcon#flushed, iclass 16, count 0 2006.245.07:36:33.02#ibcon#about to write, iclass 16, count 0 2006.245.07:36:33.02#ibcon#wrote, iclass 16, count 0 2006.245.07:36:33.02#ibcon#about to read 3, iclass 16, count 0 2006.245.07:36:33.04#ibcon#read 3, iclass 16, count 0 2006.245.07:36:33.04#ibcon#about to read 4, iclass 16, count 0 2006.245.07:36:33.04#ibcon#read 4, iclass 16, count 0 2006.245.07:36:33.04#ibcon#about to read 5, iclass 16, count 0 2006.245.07:36:33.04#ibcon#read 5, iclass 16, count 0 2006.245.07:36:33.04#ibcon#about to read 6, iclass 16, count 0 2006.245.07:36:33.04#ibcon#read 6, iclass 16, count 0 2006.245.07:36:33.04#ibcon#end of sib2, iclass 16, count 0 2006.245.07:36:33.04#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:36:33.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:36:33.04#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:36:33.04#ibcon#*before write, iclass 16, count 0 2006.245.07:36:33.04#ibcon#enter sib2, iclass 16, count 0 2006.245.07:36:33.04#ibcon#flushed, iclass 16, count 0 2006.245.07:36:33.04#ibcon#about to write, iclass 16, count 0 2006.245.07:36:33.04#ibcon#wrote, iclass 16, count 0 2006.245.07:36:33.04#ibcon#about to read 3, iclass 16, count 0 2006.245.07:36:33.08#ibcon#read 3, iclass 16, count 0 2006.245.07:36:33.08#ibcon#about to read 4, iclass 16, count 0 2006.245.07:36:33.08#ibcon#read 4, iclass 16, count 0 2006.245.07:36:33.08#ibcon#about to read 5, iclass 16, count 0 2006.245.07:36:33.08#ibcon#read 5, iclass 16, count 0 2006.245.07:36:33.08#ibcon#about to read 6, iclass 16, count 0 2006.245.07:36:33.08#ibcon#read 6, iclass 16, count 0 2006.245.07:36:33.08#ibcon#end of sib2, iclass 16, count 0 2006.245.07:36:33.08#ibcon#*after write, iclass 16, count 0 2006.245.07:36:33.08#ibcon#*before return 0, iclass 16, count 0 2006.245.07:36:33.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:33.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:36:33.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:36:33.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:36:33.08$vc4f8/vb=3,4 2006.245.07:36:33.08#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.07:36:33.08#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.07:36:33.08#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:33.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:33.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:33.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:33.15#ibcon#enter wrdev, iclass 18, count 2 2006.245.07:36:33.15#ibcon#first serial, iclass 18, count 2 2006.245.07:36:33.15#ibcon#enter sib2, iclass 18, count 2 2006.245.07:36:33.15#ibcon#flushed, iclass 18, count 2 2006.245.07:36:33.15#ibcon#about to write, iclass 18, count 2 2006.245.07:36:33.15#ibcon#wrote, iclass 18, count 2 2006.245.07:36:33.15#ibcon#about to read 3, iclass 18, count 2 2006.245.07:36:33.16#ibcon#read 3, iclass 18, count 2 2006.245.07:36:33.16#ibcon#about to read 4, iclass 18, count 2 2006.245.07:36:33.16#ibcon#read 4, iclass 18, count 2 2006.245.07:36:33.16#ibcon#about to read 5, iclass 18, count 2 2006.245.07:36:33.16#ibcon#read 5, iclass 18, count 2 2006.245.07:36:33.16#ibcon#about to read 6, iclass 18, count 2 2006.245.07:36:33.16#ibcon#read 6, iclass 18, count 2 2006.245.07:36:33.16#ibcon#end of sib2, iclass 18, count 2 2006.245.07:36:33.16#ibcon#*mode == 0, iclass 18, count 2 2006.245.07:36:33.16#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.07:36:33.16#ibcon#[27=AT03-04\r\n] 2006.245.07:36:33.16#ibcon#*before write, iclass 18, count 2 2006.245.07:36:33.16#ibcon#enter sib2, iclass 18, count 2 2006.245.07:36:33.16#ibcon#flushed, iclass 18, count 2 2006.245.07:36:33.16#ibcon#about to write, iclass 18, count 2 2006.245.07:36:33.16#ibcon#wrote, iclass 18, count 2 2006.245.07:36:33.16#ibcon#about to read 3, iclass 18, count 2 2006.245.07:36:33.19#ibcon#read 3, iclass 18, count 2 2006.245.07:36:33.19#ibcon#about to read 4, iclass 18, count 2 2006.245.07:36:33.19#ibcon#read 4, iclass 18, count 2 2006.245.07:36:33.19#ibcon#about to read 5, iclass 18, count 2 2006.245.07:36:33.19#ibcon#read 5, iclass 18, count 2 2006.245.07:36:33.19#ibcon#about to read 6, iclass 18, count 2 2006.245.07:36:33.19#ibcon#read 6, iclass 18, count 2 2006.245.07:36:33.19#ibcon#end of sib2, iclass 18, count 2 2006.245.07:36:33.19#ibcon#*after write, iclass 18, count 2 2006.245.07:36:33.19#ibcon#*before return 0, iclass 18, count 2 2006.245.07:36:33.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:33.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:36:33.19#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.07:36:33.19#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:33.19#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:33.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:33.31#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:33.31#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:36:33.31#ibcon#first serial, iclass 18, count 0 2006.245.07:36:33.31#ibcon#enter sib2, iclass 18, count 0 2006.245.07:36:33.31#ibcon#flushed, iclass 18, count 0 2006.245.07:36:33.31#ibcon#about to write, iclass 18, count 0 2006.245.07:36:33.31#ibcon#wrote, iclass 18, count 0 2006.245.07:36:33.31#ibcon#about to read 3, iclass 18, count 0 2006.245.07:36:33.33#ibcon#read 3, iclass 18, count 0 2006.245.07:36:33.33#ibcon#about to read 4, iclass 18, count 0 2006.245.07:36:33.33#ibcon#read 4, iclass 18, count 0 2006.245.07:36:33.33#ibcon#about to read 5, iclass 18, count 0 2006.245.07:36:33.33#ibcon#read 5, iclass 18, count 0 2006.245.07:36:33.33#ibcon#about to read 6, iclass 18, count 0 2006.245.07:36:33.33#ibcon#read 6, iclass 18, count 0 2006.245.07:36:33.33#ibcon#end of sib2, iclass 18, count 0 2006.245.07:36:33.33#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:36:33.33#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:36:33.33#ibcon#[27=USB\r\n] 2006.245.07:36:33.33#ibcon#*before write, iclass 18, count 0 2006.245.07:36:33.33#ibcon#enter sib2, iclass 18, count 0 2006.245.07:36:33.33#ibcon#flushed, iclass 18, count 0 2006.245.07:36:33.33#ibcon#about to write, iclass 18, count 0 2006.245.07:36:33.33#ibcon#wrote, iclass 18, count 0 2006.245.07:36:33.33#ibcon#about to read 3, iclass 18, count 0 2006.245.07:36:33.36#ibcon#read 3, iclass 18, count 0 2006.245.07:36:33.36#ibcon#about to read 4, iclass 18, count 0 2006.245.07:36:33.36#ibcon#read 4, iclass 18, count 0 2006.245.07:36:33.36#ibcon#about to read 5, iclass 18, count 0 2006.245.07:36:33.36#ibcon#read 5, iclass 18, count 0 2006.245.07:36:33.36#ibcon#about to read 6, iclass 18, count 0 2006.245.07:36:33.36#ibcon#read 6, iclass 18, count 0 2006.245.07:36:33.36#ibcon#end of sib2, iclass 18, count 0 2006.245.07:36:33.36#ibcon#*after write, iclass 18, count 0 2006.245.07:36:33.36#ibcon#*before return 0, iclass 18, count 0 2006.245.07:36:33.36#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:33.36#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:36:33.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:36:33.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:36:33.36$vc4f8/vblo=4,712.99 2006.245.07:36:33.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.07:36:33.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.07:36:33.36#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:33.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:33.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:33.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:33.36#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:36:33.36#ibcon#first serial, iclass 20, count 0 2006.245.07:36:33.36#ibcon#enter sib2, iclass 20, count 0 2006.245.07:36:33.36#ibcon#flushed, iclass 20, count 0 2006.245.07:36:33.36#ibcon#about to write, iclass 20, count 0 2006.245.07:36:33.36#ibcon#wrote, iclass 20, count 0 2006.245.07:36:33.36#ibcon#about to read 3, iclass 20, count 0 2006.245.07:36:33.38#ibcon#read 3, iclass 20, count 0 2006.245.07:36:33.38#ibcon#about to read 4, iclass 20, count 0 2006.245.07:36:33.38#ibcon#read 4, iclass 20, count 0 2006.245.07:36:33.38#ibcon#about to read 5, iclass 20, count 0 2006.245.07:36:33.38#ibcon#read 5, iclass 20, count 0 2006.245.07:36:33.38#ibcon#about to read 6, iclass 20, count 0 2006.245.07:36:33.38#ibcon#read 6, iclass 20, count 0 2006.245.07:36:33.38#ibcon#end of sib2, iclass 20, count 0 2006.245.07:36:33.38#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:36:33.38#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:36:33.38#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:36:33.38#ibcon#*before write, iclass 20, count 0 2006.245.07:36:33.38#ibcon#enter sib2, iclass 20, count 0 2006.245.07:36:33.38#ibcon#flushed, iclass 20, count 0 2006.245.07:36:33.38#ibcon#about to write, iclass 20, count 0 2006.245.07:36:33.38#ibcon#wrote, iclass 20, count 0 2006.245.07:36:33.38#ibcon#about to read 3, iclass 20, count 0 2006.245.07:36:33.42#ibcon#read 3, iclass 20, count 0 2006.245.07:36:33.42#ibcon#about to read 4, iclass 20, count 0 2006.245.07:36:33.42#ibcon#read 4, iclass 20, count 0 2006.245.07:36:33.42#ibcon#about to read 5, iclass 20, count 0 2006.245.07:36:33.42#ibcon#read 5, iclass 20, count 0 2006.245.07:36:33.42#ibcon#about to read 6, iclass 20, count 0 2006.245.07:36:33.42#ibcon#read 6, iclass 20, count 0 2006.245.07:36:33.42#ibcon#end of sib2, iclass 20, count 0 2006.245.07:36:33.42#ibcon#*after write, iclass 20, count 0 2006.245.07:36:33.42#ibcon#*before return 0, iclass 20, count 0 2006.245.07:36:33.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:33.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:36:33.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:36:33.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:36:33.42$vc4f8/vb=4,4 2006.245.07:36:33.42#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.07:36:33.42#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.07:36:33.42#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:33.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:33.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:33.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:33.48#ibcon#enter wrdev, iclass 22, count 2 2006.245.07:36:33.48#ibcon#first serial, iclass 22, count 2 2006.245.07:36:33.48#ibcon#enter sib2, iclass 22, count 2 2006.245.07:36:33.48#ibcon#flushed, iclass 22, count 2 2006.245.07:36:33.48#ibcon#about to write, iclass 22, count 2 2006.245.07:36:33.48#ibcon#wrote, iclass 22, count 2 2006.245.07:36:33.48#ibcon#about to read 3, iclass 22, count 2 2006.245.07:36:33.50#ibcon#read 3, iclass 22, count 2 2006.245.07:36:33.50#ibcon#about to read 4, iclass 22, count 2 2006.245.07:36:33.50#ibcon#read 4, iclass 22, count 2 2006.245.07:36:33.50#ibcon#about to read 5, iclass 22, count 2 2006.245.07:36:33.50#ibcon#read 5, iclass 22, count 2 2006.245.07:36:33.50#ibcon#about to read 6, iclass 22, count 2 2006.245.07:36:33.50#ibcon#read 6, iclass 22, count 2 2006.245.07:36:33.50#ibcon#end of sib2, iclass 22, count 2 2006.245.07:36:33.50#ibcon#*mode == 0, iclass 22, count 2 2006.245.07:36:33.50#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.07:36:33.50#ibcon#[27=AT04-04\r\n] 2006.245.07:36:33.50#ibcon#*before write, iclass 22, count 2 2006.245.07:36:33.50#ibcon#enter sib2, iclass 22, count 2 2006.245.07:36:33.50#ibcon#flushed, iclass 22, count 2 2006.245.07:36:33.50#ibcon#about to write, iclass 22, count 2 2006.245.07:36:33.50#ibcon#wrote, iclass 22, count 2 2006.245.07:36:33.50#ibcon#about to read 3, iclass 22, count 2 2006.245.07:36:33.53#ibcon#read 3, iclass 22, count 2 2006.245.07:36:33.53#ibcon#about to read 4, iclass 22, count 2 2006.245.07:36:33.53#ibcon#read 4, iclass 22, count 2 2006.245.07:36:33.53#ibcon#about to read 5, iclass 22, count 2 2006.245.07:36:33.53#ibcon#read 5, iclass 22, count 2 2006.245.07:36:33.53#ibcon#about to read 6, iclass 22, count 2 2006.245.07:36:33.53#ibcon#read 6, iclass 22, count 2 2006.245.07:36:33.53#ibcon#end of sib2, iclass 22, count 2 2006.245.07:36:33.53#ibcon#*after write, iclass 22, count 2 2006.245.07:36:33.53#ibcon#*before return 0, iclass 22, count 2 2006.245.07:36:33.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:33.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:36:33.53#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.07:36:33.53#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:33.53#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:33.65#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:33.65#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:33.65#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:36:33.65#ibcon#first serial, iclass 22, count 0 2006.245.07:36:33.65#ibcon#enter sib2, iclass 22, count 0 2006.245.07:36:33.65#ibcon#flushed, iclass 22, count 0 2006.245.07:36:33.65#ibcon#about to write, iclass 22, count 0 2006.245.07:36:33.65#ibcon#wrote, iclass 22, count 0 2006.245.07:36:33.65#ibcon#about to read 3, iclass 22, count 0 2006.245.07:36:33.67#ibcon#read 3, iclass 22, count 0 2006.245.07:36:33.67#ibcon#about to read 4, iclass 22, count 0 2006.245.07:36:33.67#ibcon#read 4, iclass 22, count 0 2006.245.07:36:33.67#ibcon#about to read 5, iclass 22, count 0 2006.245.07:36:33.67#ibcon#read 5, iclass 22, count 0 2006.245.07:36:33.67#ibcon#about to read 6, iclass 22, count 0 2006.245.07:36:33.67#ibcon#read 6, iclass 22, count 0 2006.245.07:36:33.67#ibcon#end of sib2, iclass 22, count 0 2006.245.07:36:33.67#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:36:33.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:36:33.67#ibcon#[27=USB\r\n] 2006.245.07:36:33.67#ibcon#*before write, iclass 22, count 0 2006.245.07:36:33.67#ibcon#enter sib2, iclass 22, count 0 2006.245.07:36:33.67#ibcon#flushed, iclass 22, count 0 2006.245.07:36:33.67#ibcon#about to write, iclass 22, count 0 2006.245.07:36:33.67#ibcon#wrote, iclass 22, count 0 2006.245.07:36:33.67#ibcon#about to read 3, iclass 22, count 0 2006.245.07:36:33.70#ibcon#read 3, iclass 22, count 0 2006.245.07:36:33.70#ibcon#about to read 4, iclass 22, count 0 2006.245.07:36:33.70#ibcon#read 4, iclass 22, count 0 2006.245.07:36:33.70#ibcon#about to read 5, iclass 22, count 0 2006.245.07:36:33.70#ibcon#read 5, iclass 22, count 0 2006.245.07:36:33.70#ibcon#about to read 6, iclass 22, count 0 2006.245.07:36:33.70#ibcon#read 6, iclass 22, count 0 2006.245.07:36:33.70#ibcon#end of sib2, iclass 22, count 0 2006.245.07:36:33.70#ibcon#*after write, iclass 22, count 0 2006.245.07:36:33.70#ibcon#*before return 0, iclass 22, count 0 2006.245.07:36:33.70#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:33.70#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:36:33.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:36:33.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:36:33.70$vc4f8/vblo=5,744.99 2006.245.07:36:33.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.07:36:33.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.07:36:33.70#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:33.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:33.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:33.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:33.70#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:36:33.70#ibcon#first serial, iclass 24, count 0 2006.245.07:36:33.70#ibcon#enter sib2, iclass 24, count 0 2006.245.07:36:33.70#ibcon#flushed, iclass 24, count 0 2006.245.07:36:33.70#ibcon#about to write, iclass 24, count 0 2006.245.07:36:33.70#ibcon#wrote, iclass 24, count 0 2006.245.07:36:33.70#ibcon#about to read 3, iclass 24, count 0 2006.245.07:36:33.72#ibcon#read 3, iclass 24, count 0 2006.245.07:36:33.72#ibcon#about to read 4, iclass 24, count 0 2006.245.07:36:33.72#ibcon#read 4, iclass 24, count 0 2006.245.07:36:33.72#ibcon#about to read 5, iclass 24, count 0 2006.245.07:36:33.72#ibcon#read 5, iclass 24, count 0 2006.245.07:36:33.72#ibcon#about to read 6, iclass 24, count 0 2006.245.07:36:33.72#ibcon#read 6, iclass 24, count 0 2006.245.07:36:33.72#ibcon#end of sib2, iclass 24, count 0 2006.245.07:36:33.72#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:36:33.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:36:33.72#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:36:33.72#ibcon#*before write, iclass 24, count 0 2006.245.07:36:33.72#ibcon#enter sib2, iclass 24, count 0 2006.245.07:36:33.72#ibcon#flushed, iclass 24, count 0 2006.245.07:36:33.72#ibcon#about to write, iclass 24, count 0 2006.245.07:36:33.72#ibcon#wrote, iclass 24, count 0 2006.245.07:36:33.72#ibcon#about to read 3, iclass 24, count 0 2006.245.07:36:33.76#ibcon#read 3, iclass 24, count 0 2006.245.07:36:33.76#ibcon#about to read 4, iclass 24, count 0 2006.245.07:36:33.76#ibcon#read 4, iclass 24, count 0 2006.245.07:36:33.76#ibcon#about to read 5, iclass 24, count 0 2006.245.07:36:33.76#ibcon#read 5, iclass 24, count 0 2006.245.07:36:33.76#ibcon#about to read 6, iclass 24, count 0 2006.245.07:36:33.76#ibcon#read 6, iclass 24, count 0 2006.245.07:36:33.76#ibcon#end of sib2, iclass 24, count 0 2006.245.07:36:33.76#ibcon#*after write, iclass 24, count 0 2006.245.07:36:33.76#ibcon#*before return 0, iclass 24, count 0 2006.245.07:36:33.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:33.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:36:33.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:36:33.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:36:33.76$vc4f8/vb=5,3 2006.245.07:36:33.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.07:36:33.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.07:36:33.76#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:33.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:33.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:33.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:33.82#ibcon#enter wrdev, iclass 26, count 2 2006.245.07:36:33.82#ibcon#first serial, iclass 26, count 2 2006.245.07:36:33.82#ibcon#enter sib2, iclass 26, count 2 2006.245.07:36:33.82#ibcon#flushed, iclass 26, count 2 2006.245.07:36:33.82#ibcon#about to write, iclass 26, count 2 2006.245.07:36:33.82#ibcon#wrote, iclass 26, count 2 2006.245.07:36:33.82#ibcon#about to read 3, iclass 26, count 2 2006.245.07:36:33.84#ibcon#read 3, iclass 26, count 2 2006.245.07:36:33.84#ibcon#about to read 4, iclass 26, count 2 2006.245.07:36:33.84#ibcon#read 4, iclass 26, count 2 2006.245.07:36:33.84#ibcon#about to read 5, iclass 26, count 2 2006.245.07:36:33.84#ibcon#read 5, iclass 26, count 2 2006.245.07:36:33.84#ibcon#about to read 6, iclass 26, count 2 2006.245.07:36:33.84#ibcon#read 6, iclass 26, count 2 2006.245.07:36:33.84#ibcon#end of sib2, iclass 26, count 2 2006.245.07:36:33.84#ibcon#*mode == 0, iclass 26, count 2 2006.245.07:36:33.84#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.07:36:33.84#ibcon#[27=AT05-03\r\n] 2006.245.07:36:33.84#ibcon#*before write, iclass 26, count 2 2006.245.07:36:33.84#ibcon#enter sib2, iclass 26, count 2 2006.245.07:36:33.84#ibcon#flushed, iclass 26, count 2 2006.245.07:36:33.84#ibcon#about to write, iclass 26, count 2 2006.245.07:36:33.84#ibcon#wrote, iclass 26, count 2 2006.245.07:36:33.84#ibcon#about to read 3, iclass 26, count 2 2006.245.07:36:33.87#ibcon#read 3, iclass 26, count 2 2006.245.07:36:33.87#ibcon#about to read 4, iclass 26, count 2 2006.245.07:36:33.87#ibcon#read 4, iclass 26, count 2 2006.245.07:36:33.87#ibcon#about to read 5, iclass 26, count 2 2006.245.07:36:33.87#ibcon#read 5, iclass 26, count 2 2006.245.07:36:33.87#ibcon#about to read 6, iclass 26, count 2 2006.245.07:36:33.87#ibcon#read 6, iclass 26, count 2 2006.245.07:36:33.87#ibcon#end of sib2, iclass 26, count 2 2006.245.07:36:33.87#ibcon#*after write, iclass 26, count 2 2006.245.07:36:33.87#ibcon#*before return 0, iclass 26, count 2 2006.245.07:36:33.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:33.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:36:33.87#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.07:36:33.87#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:33.87#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:33.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:33.99#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:33.99#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:36:33.99#ibcon#first serial, iclass 26, count 0 2006.245.07:36:33.99#ibcon#enter sib2, iclass 26, count 0 2006.245.07:36:33.99#ibcon#flushed, iclass 26, count 0 2006.245.07:36:33.99#ibcon#about to write, iclass 26, count 0 2006.245.07:36:33.99#ibcon#wrote, iclass 26, count 0 2006.245.07:36:33.99#ibcon#about to read 3, iclass 26, count 0 2006.245.07:36:34.01#ibcon#read 3, iclass 26, count 0 2006.245.07:36:34.01#ibcon#about to read 4, iclass 26, count 0 2006.245.07:36:34.01#ibcon#read 4, iclass 26, count 0 2006.245.07:36:34.01#ibcon#about to read 5, iclass 26, count 0 2006.245.07:36:34.01#ibcon#read 5, iclass 26, count 0 2006.245.07:36:34.01#ibcon#about to read 6, iclass 26, count 0 2006.245.07:36:34.01#ibcon#read 6, iclass 26, count 0 2006.245.07:36:34.01#ibcon#end of sib2, iclass 26, count 0 2006.245.07:36:34.01#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:36:34.01#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:36:34.01#ibcon#[27=USB\r\n] 2006.245.07:36:34.01#ibcon#*before write, iclass 26, count 0 2006.245.07:36:34.01#ibcon#enter sib2, iclass 26, count 0 2006.245.07:36:34.01#ibcon#flushed, iclass 26, count 0 2006.245.07:36:34.01#ibcon#about to write, iclass 26, count 0 2006.245.07:36:34.01#ibcon#wrote, iclass 26, count 0 2006.245.07:36:34.01#ibcon#about to read 3, iclass 26, count 0 2006.245.07:36:34.04#ibcon#read 3, iclass 26, count 0 2006.245.07:36:34.04#ibcon#about to read 4, iclass 26, count 0 2006.245.07:36:34.04#ibcon#read 4, iclass 26, count 0 2006.245.07:36:34.04#ibcon#about to read 5, iclass 26, count 0 2006.245.07:36:34.04#ibcon#read 5, iclass 26, count 0 2006.245.07:36:34.04#ibcon#about to read 6, iclass 26, count 0 2006.245.07:36:34.04#ibcon#read 6, iclass 26, count 0 2006.245.07:36:34.04#ibcon#end of sib2, iclass 26, count 0 2006.245.07:36:34.04#ibcon#*after write, iclass 26, count 0 2006.245.07:36:34.04#ibcon#*before return 0, iclass 26, count 0 2006.245.07:36:34.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:34.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:36:34.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:36:34.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:36:34.04$vc4f8/vblo=6,752.99 2006.245.07:36:34.04#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:36:34.04#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:36:34.04#ibcon#ireg 17 cls_cnt 0 2006.245.07:36:34.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:34.04#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:34.04#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:34.04#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:36:34.04#ibcon#first serial, iclass 28, count 0 2006.245.07:36:34.04#ibcon#enter sib2, iclass 28, count 0 2006.245.07:36:34.04#ibcon#flushed, iclass 28, count 0 2006.245.07:36:34.04#ibcon#about to write, iclass 28, count 0 2006.245.07:36:34.04#ibcon#wrote, iclass 28, count 0 2006.245.07:36:34.04#ibcon#about to read 3, iclass 28, count 0 2006.245.07:36:34.07#ibcon#read 3, iclass 28, count 0 2006.245.07:36:34.07#ibcon#about to read 4, iclass 28, count 0 2006.245.07:36:34.07#ibcon#read 4, iclass 28, count 0 2006.245.07:36:34.07#ibcon#about to read 5, iclass 28, count 0 2006.245.07:36:34.07#ibcon#read 5, iclass 28, count 0 2006.245.07:36:34.07#ibcon#about to read 6, iclass 28, count 0 2006.245.07:36:34.07#ibcon#read 6, iclass 28, count 0 2006.245.07:36:34.07#ibcon#end of sib2, iclass 28, count 0 2006.245.07:36:34.07#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:36:34.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:36:34.07#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:36:34.07#ibcon#*before write, iclass 28, count 0 2006.245.07:36:34.07#ibcon#enter sib2, iclass 28, count 0 2006.245.07:36:34.07#ibcon#flushed, iclass 28, count 0 2006.245.07:36:34.07#ibcon#about to write, iclass 28, count 0 2006.245.07:36:34.07#ibcon#wrote, iclass 28, count 0 2006.245.07:36:34.07#ibcon#about to read 3, iclass 28, count 0 2006.245.07:36:34.11#ibcon#read 3, iclass 28, count 0 2006.245.07:36:34.11#ibcon#about to read 4, iclass 28, count 0 2006.245.07:36:34.11#ibcon#read 4, iclass 28, count 0 2006.245.07:36:34.11#ibcon#about to read 5, iclass 28, count 0 2006.245.07:36:34.11#ibcon#read 5, iclass 28, count 0 2006.245.07:36:34.11#ibcon#about to read 6, iclass 28, count 0 2006.245.07:36:34.11#ibcon#read 6, iclass 28, count 0 2006.245.07:36:34.11#ibcon#end of sib2, iclass 28, count 0 2006.245.07:36:34.11#ibcon#*after write, iclass 28, count 0 2006.245.07:36:34.11#ibcon#*before return 0, iclass 28, count 0 2006.245.07:36:34.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:34.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:36:34.11#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:36:34.11#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:36:34.11$vc4f8/vb=6,3 2006.245.07:36:34.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.07:36:34.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.07:36:34.11#ibcon#ireg 11 cls_cnt 2 2006.245.07:36:34.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:34.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:34.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:34.16#ibcon#enter wrdev, iclass 30, count 2 2006.245.07:36:34.16#ibcon#first serial, iclass 30, count 2 2006.245.07:36:34.16#ibcon#enter sib2, iclass 30, count 2 2006.245.07:36:34.16#ibcon#flushed, iclass 30, count 2 2006.245.07:36:34.16#ibcon#about to write, iclass 30, count 2 2006.245.07:36:34.16#ibcon#wrote, iclass 30, count 2 2006.245.07:36:34.16#ibcon#about to read 3, iclass 30, count 2 2006.245.07:36:34.18#ibcon#read 3, iclass 30, count 2 2006.245.07:36:34.18#ibcon#about to read 4, iclass 30, count 2 2006.245.07:36:34.18#ibcon#read 4, iclass 30, count 2 2006.245.07:36:34.18#ibcon#about to read 5, iclass 30, count 2 2006.245.07:36:34.18#ibcon#read 5, iclass 30, count 2 2006.245.07:36:34.18#ibcon#about to read 6, iclass 30, count 2 2006.245.07:36:34.18#ibcon#read 6, iclass 30, count 2 2006.245.07:36:34.18#ibcon#end of sib2, iclass 30, count 2 2006.245.07:36:34.18#ibcon#*mode == 0, iclass 30, count 2 2006.245.07:36:34.18#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.07:36:34.18#ibcon#[27=AT06-03\r\n] 2006.245.07:36:34.18#ibcon#*before write, iclass 30, count 2 2006.245.07:36:34.18#ibcon#enter sib2, iclass 30, count 2 2006.245.07:36:34.18#ibcon#flushed, iclass 30, count 2 2006.245.07:36:34.18#ibcon#about to write, iclass 30, count 2 2006.245.07:36:34.18#ibcon#wrote, iclass 30, count 2 2006.245.07:36:34.18#ibcon#about to read 3, iclass 30, count 2 2006.245.07:36:34.21#ibcon#read 3, iclass 30, count 2 2006.245.07:36:34.21#ibcon#about to read 4, iclass 30, count 2 2006.245.07:36:34.21#ibcon#read 4, iclass 30, count 2 2006.245.07:36:34.21#ibcon#about to read 5, iclass 30, count 2 2006.245.07:36:34.21#ibcon#read 5, iclass 30, count 2 2006.245.07:36:34.21#ibcon#about to read 6, iclass 30, count 2 2006.245.07:36:34.21#ibcon#read 6, iclass 30, count 2 2006.245.07:36:34.21#ibcon#end of sib2, iclass 30, count 2 2006.245.07:36:34.21#ibcon#*after write, iclass 30, count 2 2006.245.07:36:34.21#ibcon#*before return 0, iclass 30, count 2 2006.245.07:36:34.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:34.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:36:34.21#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.07:36:34.21#ibcon#ireg 7 cls_cnt 0 2006.245.07:36:34.21#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:34.33#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:34.33#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:34.33#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:36:34.33#ibcon#first serial, iclass 30, count 0 2006.245.07:36:34.33#ibcon#enter sib2, iclass 30, count 0 2006.245.07:36:34.33#ibcon#flushed, iclass 30, count 0 2006.245.07:36:34.33#ibcon#about to write, iclass 30, count 0 2006.245.07:36:34.33#ibcon#wrote, iclass 30, count 0 2006.245.07:36:34.33#ibcon#about to read 3, iclass 30, count 0 2006.245.07:36:34.35#ibcon#read 3, iclass 30, count 0 2006.245.07:36:34.35#ibcon#about to read 4, iclass 30, count 0 2006.245.07:36:34.35#ibcon#read 4, iclass 30, count 0 2006.245.07:36:34.35#ibcon#about to read 5, iclass 30, count 0 2006.245.07:36:34.35#ibcon#read 5, iclass 30, count 0 2006.245.07:36:34.35#ibcon#about to read 6, iclass 30, count 0 2006.245.07:36:34.35#ibcon#read 6, iclass 30, count 0 2006.245.07:36:34.35#ibcon#end of sib2, iclass 30, count 0 2006.245.07:36:34.35#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:36:34.35#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:36:34.35#ibcon#[27=USB\r\n] 2006.245.07:36:34.35#ibcon#*before write, iclass 30, count 0 2006.245.07:36:34.35#ibcon#enter sib2, iclass 30, count 0 2006.245.07:36:34.35#ibcon#flushed, iclass 30, count 0 2006.245.07:36:34.35#ibcon#about to write, iclass 30, count 0 2006.245.07:36:34.35#ibcon#wrote, iclass 30, count 0 2006.245.07:36:34.35#ibcon#about to read 3, iclass 30, count 0 2006.245.07:36:34.38#ibcon#read 3, iclass 30, count 0 2006.245.07:36:34.38#ibcon#about to read 4, iclass 30, count 0 2006.245.07:36:34.38#ibcon#read 4, iclass 30, count 0 2006.245.07:36:34.38#ibcon#about to read 5, iclass 30, count 0 2006.245.07:36:34.38#ibcon#read 5, iclass 30, count 0 2006.245.07:36:34.38#ibcon#about to read 6, iclass 30, count 0 2006.245.07:36:34.38#ibcon#read 6, iclass 30, count 0 2006.245.07:36:34.38#ibcon#end of sib2, iclass 30, count 0 2006.245.07:36:34.38#ibcon#*after write, iclass 30, count 0 2006.245.07:36:34.38#ibcon#*before return 0, iclass 30, count 0 2006.245.07:36:34.38#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:34.38#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:36:34.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:36:34.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:36:34.38$vc4f8/vabw=wide 2006.245.07:36:34.38#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.07:36:34.38#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.07:36:34.38#ibcon#ireg 8 cls_cnt 0 2006.245.07:36:34.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:34.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:34.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:34.38#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:36:34.38#ibcon#first serial, iclass 32, count 0 2006.245.07:36:34.38#ibcon#enter sib2, iclass 32, count 0 2006.245.07:36:34.38#ibcon#flushed, iclass 32, count 0 2006.245.07:36:34.38#ibcon#about to write, iclass 32, count 0 2006.245.07:36:34.38#ibcon#wrote, iclass 32, count 0 2006.245.07:36:34.38#ibcon#about to read 3, iclass 32, count 0 2006.245.07:36:34.40#ibcon#read 3, iclass 32, count 0 2006.245.07:36:34.40#ibcon#about to read 4, iclass 32, count 0 2006.245.07:36:34.40#ibcon#read 4, iclass 32, count 0 2006.245.07:36:34.40#ibcon#about to read 5, iclass 32, count 0 2006.245.07:36:34.40#ibcon#read 5, iclass 32, count 0 2006.245.07:36:34.40#ibcon#about to read 6, iclass 32, count 0 2006.245.07:36:34.40#ibcon#read 6, iclass 32, count 0 2006.245.07:36:34.40#ibcon#end of sib2, iclass 32, count 0 2006.245.07:36:34.40#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:36:34.40#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:36:34.40#ibcon#[25=BW32\r\n] 2006.245.07:36:34.40#ibcon#*before write, iclass 32, count 0 2006.245.07:36:34.40#ibcon#enter sib2, iclass 32, count 0 2006.245.07:36:34.40#ibcon#flushed, iclass 32, count 0 2006.245.07:36:34.40#ibcon#about to write, iclass 32, count 0 2006.245.07:36:34.40#ibcon#wrote, iclass 32, count 0 2006.245.07:36:34.40#ibcon#about to read 3, iclass 32, count 0 2006.245.07:36:34.43#ibcon#read 3, iclass 32, count 0 2006.245.07:36:34.43#ibcon#about to read 4, iclass 32, count 0 2006.245.07:36:34.43#ibcon#read 4, iclass 32, count 0 2006.245.07:36:34.43#ibcon#about to read 5, iclass 32, count 0 2006.245.07:36:34.43#ibcon#read 5, iclass 32, count 0 2006.245.07:36:34.43#ibcon#about to read 6, iclass 32, count 0 2006.245.07:36:34.43#ibcon#read 6, iclass 32, count 0 2006.245.07:36:34.43#ibcon#end of sib2, iclass 32, count 0 2006.245.07:36:34.43#ibcon#*after write, iclass 32, count 0 2006.245.07:36:34.43#ibcon#*before return 0, iclass 32, count 0 2006.245.07:36:34.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:34.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:36:34.43#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:36:34.43#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:36:34.43$vc4f8/vbbw=wide 2006.245.07:36:34.43#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:36:34.43#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:36:34.43#ibcon#ireg 8 cls_cnt 0 2006.245.07:36:34.43#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:36:34.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:36:34.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:36:34.50#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:36:34.50#ibcon#first serial, iclass 34, count 0 2006.245.07:36:34.50#ibcon#enter sib2, iclass 34, count 0 2006.245.07:36:34.50#ibcon#flushed, iclass 34, count 0 2006.245.07:36:34.50#ibcon#about to write, iclass 34, count 0 2006.245.07:36:34.50#ibcon#wrote, iclass 34, count 0 2006.245.07:36:34.50#ibcon#about to read 3, iclass 34, count 0 2006.245.07:36:34.52#ibcon#read 3, iclass 34, count 0 2006.245.07:36:34.52#ibcon#about to read 4, iclass 34, count 0 2006.245.07:36:34.52#ibcon#read 4, iclass 34, count 0 2006.245.07:36:34.52#ibcon#about to read 5, iclass 34, count 0 2006.245.07:36:34.52#ibcon#read 5, iclass 34, count 0 2006.245.07:36:34.52#ibcon#about to read 6, iclass 34, count 0 2006.245.07:36:34.52#ibcon#read 6, iclass 34, count 0 2006.245.07:36:34.52#ibcon#end of sib2, iclass 34, count 0 2006.245.07:36:34.52#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:36:34.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:36:34.52#ibcon#[27=BW32\r\n] 2006.245.07:36:34.52#ibcon#*before write, iclass 34, count 0 2006.245.07:36:34.52#ibcon#enter sib2, iclass 34, count 0 2006.245.07:36:34.52#ibcon#flushed, iclass 34, count 0 2006.245.07:36:34.52#ibcon#about to write, iclass 34, count 0 2006.245.07:36:34.52#ibcon#wrote, iclass 34, count 0 2006.245.07:36:34.52#ibcon#about to read 3, iclass 34, count 0 2006.245.07:36:34.55#ibcon#read 3, iclass 34, count 0 2006.245.07:36:34.55#ibcon#about to read 4, iclass 34, count 0 2006.245.07:36:34.55#ibcon#read 4, iclass 34, count 0 2006.245.07:36:34.55#ibcon#about to read 5, iclass 34, count 0 2006.245.07:36:34.55#ibcon#read 5, iclass 34, count 0 2006.245.07:36:34.55#ibcon#about to read 6, iclass 34, count 0 2006.245.07:36:34.55#ibcon#read 6, iclass 34, count 0 2006.245.07:36:34.55#ibcon#end of sib2, iclass 34, count 0 2006.245.07:36:34.55#ibcon#*after write, iclass 34, count 0 2006.245.07:36:34.55#ibcon#*before return 0, iclass 34, count 0 2006.245.07:36:34.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:36:34.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:36:34.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:36:34.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:36:34.55$4f8m12a/ifd4f 2006.245.07:36:34.55$ifd4f/lo= 2006.245.07:36:34.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:36:34.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:36:34.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:36:34.55$ifd4f/patch= 2006.245.07:36:34.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:36:34.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:36:34.55$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:36:34.55$4f8m12a/"form=m,16.000,1:2 2006.245.07:36:34.55$4f8m12a/"tpicd 2006.245.07:36:34.55$4f8m12a/echo=off 2006.245.07:36:34.55$4f8m12a/xlog=off 2006.245.07:36:34.55:!2006.245.07:37:00 2006.245.07:36:41.14#trakl#Source acquired 2006.245.07:36:42.14#flagr#flagr/antenna,acquired 2006.245.07:37:00.00:preob 2006.245.07:37:01.14/onsource/TRACKING 2006.245.07:37:01.14:!2006.245.07:37:10 2006.245.07:37:10.00:data_valid=on 2006.245.07:37:10.00:midob 2006.245.07:37:10.14/onsource/TRACKING 2006.245.07:37:10.14/wx/27.60,1004.4,67 2006.245.07:37:10.25/cable/+6.4116E-03 2006.245.07:37:11.34/va/01,08,usb,yes,31,33 2006.245.07:37:11.34/va/02,07,usb,yes,31,32 2006.245.07:37:11.34/va/03,06,usb,yes,33,33 2006.245.07:37:11.34/va/04,07,usb,yes,32,35 2006.245.07:37:11.34/va/05,07,usb,yes,33,35 2006.245.07:37:11.34/va/06,07,usb,yes,29,29 2006.245.07:37:11.34/va/07,07,usb,yes,29,29 2006.245.07:37:11.34/va/08,08,usb,yes,25,25 2006.245.07:37:11.57/valo/01,532.99,yes,locked 2006.245.07:37:11.57/valo/02,572.99,yes,locked 2006.245.07:37:11.57/valo/03,672.99,yes,locked 2006.245.07:37:11.57/valo/04,832.99,yes,locked 2006.245.07:37:11.57/valo/05,652.99,yes,locked 2006.245.07:37:11.57/valo/06,772.99,yes,locked 2006.245.07:37:11.57/valo/07,832.99,yes,locked 2006.245.07:37:11.57/valo/08,852.99,yes,locked 2006.245.07:37:12.66/vb/01,04,usb,yes,31,29 2006.245.07:37:12.66/vb/02,04,usb,yes,33,34 2006.245.07:37:12.66/vb/03,04,usb,yes,29,33 2006.245.07:37:12.66/vb/04,04,usb,yes,30,30 2006.245.07:37:12.66/vb/05,03,usb,yes,35,40 2006.245.07:37:12.66/vb/06,03,usb,yes,36,39 2006.245.07:37:12.66/vb/07,04,usb,yes,31,31 2006.245.07:37:12.66/vb/08,03,usb,yes,36,39 2006.245.07:37:12.89/vblo/01,632.99,yes,locked 2006.245.07:37:12.89/vblo/02,640.99,yes,locked 2006.245.07:37:12.89/vblo/03,656.99,yes,locked 2006.245.07:37:12.89/vblo/04,712.99,yes,locked 2006.245.07:37:12.89/vblo/05,744.99,yes,locked 2006.245.07:37:12.89/vblo/06,752.99,yes,locked 2006.245.07:37:12.89/vblo/07,734.99,yes,locked 2006.245.07:37:12.89/vblo/08,744.99,yes,locked 2006.245.07:37:13.04/vabw/8 2006.245.07:37:13.19/vbbw/8 2006.245.07:37:13.28/xfe/off,on,13.5 2006.245.07:37:13.66/ifatt/23,28,28,28 2006.245.07:37:14.08/fmout-gps/S +4.46E-07 2006.245.07:37:14.12:!2006.245.07:38:10 2006.245.07:38:10.00:data_valid=off 2006.245.07:38:10.00:postob 2006.245.07:38:10.11/cable/+6.4115E-03 2006.245.07:38:10.11/wx/27.58,1004.4,67 2006.245.07:38:11.08/fmout-gps/S +4.45E-07 2006.245.07:38:11.08:scan_name=245-0739,k06245,60 2006.245.07:38:11.09:source=oq208,140700.39,282714.7,2000.0,ccw 2006.245.07:38:11.15#flagr#flagr/antenna,new-source 2006.245.07:38:12.13:checkk5 2006.245.07:38:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:38:12.92/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:38:13.61/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:38:14.01/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:38:14.63/chk_obsdata//k5ts1/T2450737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:38:15.07/chk_obsdata//k5ts2/T2450737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:38:15.57/chk_obsdata//k5ts3/T2450737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:38:16.01/chk_obsdata//k5ts4/T2450737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:38:17.14/k5log//k5ts1_log_newline 2006.245.07:38:18.34/k5log//k5ts2_log_newline 2006.245.07:38:19.41/k5log//k5ts3_log_newline 2006.245.07:38:20.20/k5log//k5ts4_log_newline 2006.245.07:38:20.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:38:20.23:4f8m12a=1 2006.245.07:38:20.23$4f8m12a/echo=on 2006.245.07:38:20.23$4f8m12a/pcalon 2006.245.07:38:20.23$pcalon/"no phase cal control is implemented here 2006.245.07:38:20.23$4f8m12a/"tpicd=stop 2006.245.07:38:20.23$4f8m12a/vc4f8 2006.245.07:38:20.23$vc4f8/valo=1,532.99 2006.245.07:38:20.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:38:20.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:38:20.23#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:20.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:20.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:20.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:20.23#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:38:20.23#ibcon#first serial, iclass 7, count 0 2006.245.07:38:20.23#ibcon#enter sib2, iclass 7, count 0 2006.245.07:38:20.23#ibcon#flushed, iclass 7, count 0 2006.245.07:38:20.23#ibcon#about to write, iclass 7, count 0 2006.245.07:38:20.23#ibcon#wrote, iclass 7, count 0 2006.245.07:38:20.23#ibcon#about to read 3, iclass 7, count 0 2006.245.07:38:20.27#ibcon#read 3, iclass 7, count 0 2006.245.07:38:20.27#ibcon#about to read 4, iclass 7, count 0 2006.245.07:38:20.27#ibcon#read 4, iclass 7, count 0 2006.245.07:38:20.27#ibcon#about to read 5, iclass 7, count 0 2006.245.07:38:20.27#ibcon#read 5, iclass 7, count 0 2006.245.07:38:20.27#ibcon#about to read 6, iclass 7, count 0 2006.245.07:38:20.27#ibcon#read 6, iclass 7, count 0 2006.245.07:38:20.27#ibcon#end of sib2, iclass 7, count 0 2006.245.07:38:20.27#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:38:20.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:38:20.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:38:20.27#ibcon#*before write, iclass 7, count 0 2006.245.07:38:20.27#ibcon#enter sib2, iclass 7, count 0 2006.245.07:38:20.27#ibcon#flushed, iclass 7, count 0 2006.245.07:38:20.27#ibcon#about to write, iclass 7, count 0 2006.245.07:38:20.27#ibcon#wrote, iclass 7, count 0 2006.245.07:38:20.27#ibcon#about to read 3, iclass 7, count 0 2006.245.07:38:20.32#ibcon#read 3, iclass 7, count 0 2006.245.07:38:20.32#ibcon#about to read 4, iclass 7, count 0 2006.245.07:38:20.32#ibcon#read 4, iclass 7, count 0 2006.245.07:38:20.32#ibcon#about to read 5, iclass 7, count 0 2006.245.07:38:20.32#ibcon#read 5, iclass 7, count 0 2006.245.07:38:20.32#ibcon#about to read 6, iclass 7, count 0 2006.245.07:38:20.32#ibcon#read 6, iclass 7, count 0 2006.245.07:38:20.32#ibcon#end of sib2, iclass 7, count 0 2006.245.07:38:20.32#ibcon#*after write, iclass 7, count 0 2006.245.07:38:20.32#ibcon#*before return 0, iclass 7, count 0 2006.245.07:38:20.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:20.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:20.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:38:20.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:38:20.32$vc4f8/va=1,8 2006.245.07:38:20.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.07:38:20.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.07:38:20.32#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:20.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:20.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:20.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:20.32#ibcon#enter wrdev, iclass 11, count 2 2006.245.07:38:20.32#ibcon#first serial, iclass 11, count 2 2006.245.07:38:20.32#ibcon#enter sib2, iclass 11, count 2 2006.245.07:38:20.32#ibcon#flushed, iclass 11, count 2 2006.245.07:38:20.32#ibcon#about to write, iclass 11, count 2 2006.245.07:38:20.32#ibcon#wrote, iclass 11, count 2 2006.245.07:38:20.32#ibcon#about to read 3, iclass 11, count 2 2006.245.07:38:20.34#ibcon#read 3, iclass 11, count 2 2006.245.07:38:20.34#ibcon#about to read 4, iclass 11, count 2 2006.245.07:38:20.34#ibcon#read 4, iclass 11, count 2 2006.245.07:38:20.34#ibcon#about to read 5, iclass 11, count 2 2006.245.07:38:20.34#ibcon#read 5, iclass 11, count 2 2006.245.07:38:20.34#ibcon#about to read 6, iclass 11, count 2 2006.245.07:38:20.34#ibcon#read 6, iclass 11, count 2 2006.245.07:38:20.34#ibcon#end of sib2, iclass 11, count 2 2006.245.07:38:20.34#ibcon#*mode == 0, iclass 11, count 2 2006.245.07:38:20.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.07:38:20.34#ibcon#[25=AT01-08\r\n] 2006.245.07:38:20.34#ibcon#*before write, iclass 11, count 2 2006.245.07:38:20.34#ibcon#enter sib2, iclass 11, count 2 2006.245.07:38:20.34#ibcon#flushed, iclass 11, count 2 2006.245.07:38:20.34#ibcon#about to write, iclass 11, count 2 2006.245.07:38:20.34#ibcon#wrote, iclass 11, count 2 2006.245.07:38:20.34#ibcon#about to read 3, iclass 11, count 2 2006.245.07:38:20.37#ibcon#read 3, iclass 11, count 2 2006.245.07:38:20.37#ibcon#about to read 4, iclass 11, count 2 2006.245.07:38:20.37#ibcon#read 4, iclass 11, count 2 2006.245.07:38:20.37#ibcon#about to read 5, iclass 11, count 2 2006.245.07:38:20.37#ibcon#read 5, iclass 11, count 2 2006.245.07:38:20.37#ibcon#about to read 6, iclass 11, count 2 2006.245.07:38:20.37#ibcon#read 6, iclass 11, count 2 2006.245.07:38:20.37#ibcon#end of sib2, iclass 11, count 2 2006.245.07:38:20.37#ibcon#*after write, iclass 11, count 2 2006.245.07:38:20.37#ibcon#*before return 0, iclass 11, count 2 2006.245.07:38:20.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:20.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:20.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.07:38:20.37#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:20.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:20.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:20.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:20.49#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:38:20.49#ibcon#first serial, iclass 11, count 0 2006.245.07:38:20.49#ibcon#enter sib2, iclass 11, count 0 2006.245.07:38:20.49#ibcon#flushed, iclass 11, count 0 2006.245.07:38:20.49#ibcon#about to write, iclass 11, count 0 2006.245.07:38:20.49#ibcon#wrote, iclass 11, count 0 2006.245.07:38:20.49#ibcon#about to read 3, iclass 11, count 0 2006.245.07:38:20.51#ibcon#read 3, iclass 11, count 0 2006.245.07:38:20.51#ibcon#about to read 4, iclass 11, count 0 2006.245.07:38:20.51#ibcon#read 4, iclass 11, count 0 2006.245.07:38:20.51#ibcon#about to read 5, iclass 11, count 0 2006.245.07:38:20.51#ibcon#read 5, iclass 11, count 0 2006.245.07:38:20.51#ibcon#about to read 6, iclass 11, count 0 2006.245.07:38:20.51#ibcon#read 6, iclass 11, count 0 2006.245.07:38:20.51#ibcon#end of sib2, iclass 11, count 0 2006.245.07:38:20.51#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:38:20.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:38:20.51#ibcon#[25=USB\r\n] 2006.245.07:38:20.51#ibcon#*before write, iclass 11, count 0 2006.245.07:38:20.51#ibcon#enter sib2, iclass 11, count 0 2006.245.07:38:20.51#ibcon#flushed, iclass 11, count 0 2006.245.07:38:20.51#ibcon#about to write, iclass 11, count 0 2006.245.07:38:20.51#ibcon#wrote, iclass 11, count 0 2006.245.07:38:20.51#ibcon#about to read 3, iclass 11, count 0 2006.245.07:38:20.54#ibcon#read 3, iclass 11, count 0 2006.245.07:38:20.54#ibcon#about to read 4, iclass 11, count 0 2006.245.07:38:20.54#ibcon#read 4, iclass 11, count 0 2006.245.07:38:20.54#ibcon#about to read 5, iclass 11, count 0 2006.245.07:38:20.54#ibcon#read 5, iclass 11, count 0 2006.245.07:38:20.54#ibcon#about to read 6, iclass 11, count 0 2006.245.07:38:20.54#ibcon#read 6, iclass 11, count 0 2006.245.07:38:20.54#ibcon#end of sib2, iclass 11, count 0 2006.245.07:38:20.54#ibcon#*after write, iclass 11, count 0 2006.245.07:38:20.54#ibcon#*before return 0, iclass 11, count 0 2006.245.07:38:20.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:20.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:20.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:38:20.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:38:20.54$vc4f8/valo=2,572.99 2006.245.07:38:20.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.07:38:20.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.07:38:20.54#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:20.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:20.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:20.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:20.54#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:38:20.54#ibcon#first serial, iclass 13, count 0 2006.245.07:38:20.54#ibcon#enter sib2, iclass 13, count 0 2006.245.07:38:20.54#ibcon#flushed, iclass 13, count 0 2006.245.07:38:20.54#ibcon#about to write, iclass 13, count 0 2006.245.07:38:20.54#ibcon#wrote, iclass 13, count 0 2006.245.07:38:20.54#ibcon#about to read 3, iclass 13, count 0 2006.245.07:38:20.56#ibcon#read 3, iclass 13, count 0 2006.245.07:38:20.56#ibcon#about to read 4, iclass 13, count 0 2006.245.07:38:20.56#ibcon#read 4, iclass 13, count 0 2006.245.07:38:20.56#ibcon#about to read 5, iclass 13, count 0 2006.245.07:38:20.56#ibcon#read 5, iclass 13, count 0 2006.245.07:38:20.56#ibcon#about to read 6, iclass 13, count 0 2006.245.07:38:20.56#ibcon#read 6, iclass 13, count 0 2006.245.07:38:20.56#ibcon#end of sib2, iclass 13, count 0 2006.245.07:38:20.56#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:38:20.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:38:20.56#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:38:20.56#ibcon#*before write, iclass 13, count 0 2006.245.07:38:20.56#ibcon#enter sib2, iclass 13, count 0 2006.245.07:38:20.56#ibcon#flushed, iclass 13, count 0 2006.245.07:38:20.56#ibcon#about to write, iclass 13, count 0 2006.245.07:38:20.56#ibcon#wrote, iclass 13, count 0 2006.245.07:38:20.56#ibcon#about to read 3, iclass 13, count 0 2006.245.07:38:20.60#ibcon#read 3, iclass 13, count 0 2006.245.07:38:20.60#ibcon#about to read 4, iclass 13, count 0 2006.245.07:38:20.60#ibcon#read 4, iclass 13, count 0 2006.245.07:38:20.60#ibcon#about to read 5, iclass 13, count 0 2006.245.07:38:20.60#ibcon#read 5, iclass 13, count 0 2006.245.07:38:20.60#ibcon#about to read 6, iclass 13, count 0 2006.245.07:38:20.60#ibcon#read 6, iclass 13, count 0 2006.245.07:38:20.60#ibcon#end of sib2, iclass 13, count 0 2006.245.07:38:20.60#ibcon#*after write, iclass 13, count 0 2006.245.07:38:20.60#ibcon#*before return 0, iclass 13, count 0 2006.245.07:38:20.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:20.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:20.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:38:20.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:38:20.60$vc4f8/va=2,7 2006.245.07:38:20.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.07:38:20.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.07:38:20.60#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:20.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:20.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:20.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:20.66#ibcon#enter wrdev, iclass 15, count 2 2006.245.07:38:20.67#ibcon#first serial, iclass 15, count 2 2006.245.07:38:20.67#ibcon#enter sib2, iclass 15, count 2 2006.245.07:38:20.67#ibcon#flushed, iclass 15, count 2 2006.245.07:38:20.67#ibcon#about to write, iclass 15, count 2 2006.245.07:38:20.67#ibcon#wrote, iclass 15, count 2 2006.245.07:38:20.67#ibcon#about to read 3, iclass 15, count 2 2006.245.07:38:20.68#ibcon#read 3, iclass 15, count 2 2006.245.07:38:20.68#ibcon#about to read 4, iclass 15, count 2 2006.245.07:38:20.68#ibcon#read 4, iclass 15, count 2 2006.245.07:38:20.68#ibcon#about to read 5, iclass 15, count 2 2006.245.07:38:20.68#ibcon#read 5, iclass 15, count 2 2006.245.07:38:20.68#ibcon#about to read 6, iclass 15, count 2 2006.245.07:38:20.68#ibcon#read 6, iclass 15, count 2 2006.245.07:38:20.68#ibcon#end of sib2, iclass 15, count 2 2006.245.07:38:20.68#ibcon#*mode == 0, iclass 15, count 2 2006.245.07:38:20.68#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.07:38:20.68#ibcon#[25=AT02-07\r\n] 2006.245.07:38:20.68#ibcon#*before write, iclass 15, count 2 2006.245.07:38:20.68#ibcon#enter sib2, iclass 15, count 2 2006.245.07:38:20.68#ibcon#flushed, iclass 15, count 2 2006.245.07:38:20.68#ibcon#about to write, iclass 15, count 2 2006.245.07:38:20.68#ibcon#wrote, iclass 15, count 2 2006.245.07:38:20.68#ibcon#about to read 3, iclass 15, count 2 2006.245.07:38:20.71#ibcon#read 3, iclass 15, count 2 2006.245.07:38:20.71#ibcon#about to read 4, iclass 15, count 2 2006.245.07:38:20.71#ibcon#read 4, iclass 15, count 2 2006.245.07:38:20.71#ibcon#about to read 5, iclass 15, count 2 2006.245.07:38:20.71#ibcon#read 5, iclass 15, count 2 2006.245.07:38:20.71#ibcon#about to read 6, iclass 15, count 2 2006.245.07:38:20.71#ibcon#read 6, iclass 15, count 2 2006.245.07:38:20.71#ibcon#end of sib2, iclass 15, count 2 2006.245.07:38:20.71#ibcon#*after write, iclass 15, count 2 2006.245.07:38:20.71#ibcon#*before return 0, iclass 15, count 2 2006.245.07:38:20.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:20.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:20.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.07:38:20.71#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:20.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:20.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:20.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:20.83#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:38:20.83#ibcon#first serial, iclass 15, count 0 2006.245.07:38:20.83#ibcon#enter sib2, iclass 15, count 0 2006.245.07:38:20.83#ibcon#flushed, iclass 15, count 0 2006.245.07:38:20.83#ibcon#about to write, iclass 15, count 0 2006.245.07:38:20.83#ibcon#wrote, iclass 15, count 0 2006.245.07:38:20.83#ibcon#about to read 3, iclass 15, count 0 2006.245.07:38:20.85#ibcon#read 3, iclass 15, count 0 2006.245.07:38:20.85#ibcon#about to read 4, iclass 15, count 0 2006.245.07:38:20.85#ibcon#read 4, iclass 15, count 0 2006.245.07:38:20.85#ibcon#about to read 5, iclass 15, count 0 2006.245.07:38:20.85#ibcon#read 5, iclass 15, count 0 2006.245.07:38:20.85#ibcon#about to read 6, iclass 15, count 0 2006.245.07:38:20.85#ibcon#read 6, iclass 15, count 0 2006.245.07:38:20.85#ibcon#end of sib2, iclass 15, count 0 2006.245.07:38:20.85#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:38:20.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:38:20.85#ibcon#[25=USB\r\n] 2006.245.07:38:20.85#ibcon#*before write, iclass 15, count 0 2006.245.07:38:20.85#ibcon#enter sib2, iclass 15, count 0 2006.245.07:38:20.85#ibcon#flushed, iclass 15, count 0 2006.245.07:38:20.85#ibcon#about to write, iclass 15, count 0 2006.245.07:38:20.85#ibcon#wrote, iclass 15, count 0 2006.245.07:38:20.85#ibcon#about to read 3, iclass 15, count 0 2006.245.07:38:20.88#ibcon#read 3, iclass 15, count 0 2006.245.07:38:20.88#ibcon#about to read 4, iclass 15, count 0 2006.245.07:38:20.88#ibcon#read 4, iclass 15, count 0 2006.245.07:38:20.88#ibcon#about to read 5, iclass 15, count 0 2006.245.07:38:20.88#ibcon#read 5, iclass 15, count 0 2006.245.07:38:20.88#ibcon#about to read 6, iclass 15, count 0 2006.245.07:38:20.88#ibcon#read 6, iclass 15, count 0 2006.245.07:38:20.88#ibcon#end of sib2, iclass 15, count 0 2006.245.07:38:20.88#ibcon#*after write, iclass 15, count 0 2006.245.07:38:20.88#ibcon#*before return 0, iclass 15, count 0 2006.245.07:38:20.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:20.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:20.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:38:20.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:38:20.88$vc4f8/valo=3,672.99 2006.245.07:38:20.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.07:38:20.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.07:38:20.88#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:20.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:20.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:20.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:20.88#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:38:20.88#ibcon#first serial, iclass 17, count 0 2006.245.07:38:20.88#ibcon#enter sib2, iclass 17, count 0 2006.245.07:38:20.88#ibcon#flushed, iclass 17, count 0 2006.245.07:38:20.88#ibcon#about to write, iclass 17, count 0 2006.245.07:38:20.88#ibcon#wrote, iclass 17, count 0 2006.245.07:38:20.88#ibcon#about to read 3, iclass 17, count 0 2006.245.07:38:20.90#ibcon#read 3, iclass 17, count 0 2006.245.07:38:20.90#ibcon#about to read 4, iclass 17, count 0 2006.245.07:38:20.90#ibcon#read 4, iclass 17, count 0 2006.245.07:38:20.90#ibcon#about to read 5, iclass 17, count 0 2006.245.07:38:20.90#ibcon#read 5, iclass 17, count 0 2006.245.07:38:20.90#ibcon#about to read 6, iclass 17, count 0 2006.245.07:38:20.90#ibcon#read 6, iclass 17, count 0 2006.245.07:38:20.90#ibcon#end of sib2, iclass 17, count 0 2006.245.07:38:20.90#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:38:20.90#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:38:20.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:38:20.90#ibcon#*before write, iclass 17, count 0 2006.245.07:38:20.90#ibcon#enter sib2, iclass 17, count 0 2006.245.07:38:20.90#ibcon#flushed, iclass 17, count 0 2006.245.07:38:20.90#ibcon#about to write, iclass 17, count 0 2006.245.07:38:20.90#ibcon#wrote, iclass 17, count 0 2006.245.07:38:20.90#ibcon#about to read 3, iclass 17, count 0 2006.245.07:38:20.94#ibcon#read 3, iclass 17, count 0 2006.245.07:38:20.94#ibcon#about to read 4, iclass 17, count 0 2006.245.07:38:20.94#ibcon#read 4, iclass 17, count 0 2006.245.07:38:20.94#ibcon#about to read 5, iclass 17, count 0 2006.245.07:38:20.94#ibcon#read 5, iclass 17, count 0 2006.245.07:38:20.94#ibcon#about to read 6, iclass 17, count 0 2006.245.07:38:20.94#ibcon#read 6, iclass 17, count 0 2006.245.07:38:20.94#ibcon#end of sib2, iclass 17, count 0 2006.245.07:38:20.94#ibcon#*after write, iclass 17, count 0 2006.245.07:38:20.94#ibcon#*before return 0, iclass 17, count 0 2006.245.07:38:20.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:20.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:20.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:38:20.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:38:20.94$vc4f8/va=3,6 2006.245.07:38:20.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.07:38:20.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.07:38:20.94#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:20.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:21.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:21.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:21.00#ibcon#enter wrdev, iclass 19, count 2 2006.245.07:38:21.00#ibcon#first serial, iclass 19, count 2 2006.245.07:38:21.00#ibcon#enter sib2, iclass 19, count 2 2006.245.07:38:21.01#ibcon#flushed, iclass 19, count 2 2006.245.07:38:21.01#ibcon#about to write, iclass 19, count 2 2006.245.07:38:21.01#ibcon#wrote, iclass 19, count 2 2006.245.07:38:21.01#ibcon#about to read 3, iclass 19, count 2 2006.245.07:38:21.02#ibcon#read 3, iclass 19, count 2 2006.245.07:38:21.02#ibcon#about to read 4, iclass 19, count 2 2006.245.07:38:21.02#ibcon#read 4, iclass 19, count 2 2006.245.07:38:21.02#ibcon#about to read 5, iclass 19, count 2 2006.245.07:38:21.02#ibcon#read 5, iclass 19, count 2 2006.245.07:38:21.02#ibcon#about to read 6, iclass 19, count 2 2006.245.07:38:21.02#ibcon#read 6, iclass 19, count 2 2006.245.07:38:21.02#ibcon#end of sib2, iclass 19, count 2 2006.245.07:38:21.02#ibcon#*mode == 0, iclass 19, count 2 2006.245.07:38:21.02#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.07:38:21.02#ibcon#[25=AT03-06\r\n] 2006.245.07:38:21.02#ibcon#*before write, iclass 19, count 2 2006.245.07:38:21.02#ibcon#enter sib2, iclass 19, count 2 2006.245.07:38:21.02#ibcon#flushed, iclass 19, count 2 2006.245.07:38:21.02#ibcon#about to write, iclass 19, count 2 2006.245.07:38:21.02#ibcon#wrote, iclass 19, count 2 2006.245.07:38:21.02#ibcon#about to read 3, iclass 19, count 2 2006.245.07:38:21.05#ibcon#read 3, iclass 19, count 2 2006.245.07:38:21.05#ibcon#about to read 4, iclass 19, count 2 2006.245.07:38:21.05#ibcon#read 4, iclass 19, count 2 2006.245.07:38:21.05#ibcon#about to read 5, iclass 19, count 2 2006.245.07:38:21.05#ibcon#read 5, iclass 19, count 2 2006.245.07:38:21.05#ibcon#about to read 6, iclass 19, count 2 2006.245.07:38:21.05#ibcon#read 6, iclass 19, count 2 2006.245.07:38:21.05#ibcon#end of sib2, iclass 19, count 2 2006.245.07:38:21.05#ibcon#*after write, iclass 19, count 2 2006.245.07:38:21.05#ibcon#*before return 0, iclass 19, count 2 2006.245.07:38:21.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:21.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:21.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.07:38:21.05#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:21.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:21.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:21.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:21.17#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:38:21.17#ibcon#first serial, iclass 19, count 0 2006.245.07:38:21.17#ibcon#enter sib2, iclass 19, count 0 2006.245.07:38:21.17#ibcon#flushed, iclass 19, count 0 2006.245.07:38:21.17#ibcon#about to write, iclass 19, count 0 2006.245.07:38:21.17#ibcon#wrote, iclass 19, count 0 2006.245.07:38:21.17#ibcon#about to read 3, iclass 19, count 0 2006.245.07:38:21.20#ibcon#read 3, iclass 19, count 0 2006.245.07:38:21.20#ibcon#about to read 4, iclass 19, count 0 2006.245.07:38:21.20#ibcon#read 4, iclass 19, count 0 2006.245.07:38:21.20#ibcon#about to read 5, iclass 19, count 0 2006.245.07:38:21.20#ibcon#read 5, iclass 19, count 0 2006.245.07:38:21.20#ibcon#about to read 6, iclass 19, count 0 2006.245.07:38:21.20#ibcon#read 6, iclass 19, count 0 2006.245.07:38:21.20#ibcon#end of sib2, iclass 19, count 0 2006.245.07:38:21.20#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:38:21.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:38:21.20#ibcon#[25=USB\r\n] 2006.245.07:38:21.20#ibcon#*before write, iclass 19, count 0 2006.245.07:38:21.20#ibcon#enter sib2, iclass 19, count 0 2006.245.07:38:21.20#ibcon#flushed, iclass 19, count 0 2006.245.07:38:21.20#ibcon#about to write, iclass 19, count 0 2006.245.07:38:21.20#ibcon#wrote, iclass 19, count 0 2006.245.07:38:21.20#ibcon#about to read 3, iclass 19, count 0 2006.245.07:38:21.23#ibcon#read 3, iclass 19, count 0 2006.245.07:38:21.23#ibcon#about to read 4, iclass 19, count 0 2006.245.07:38:21.23#ibcon#read 4, iclass 19, count 0 2006.245.07:38:21.23#ibcon#about to read 5, iclass 19, count 0 2006.245.07:38:21.23#ibcon#read 5, iclass 19, count 0 2006.245.07:38:21.23#ibcon#about to read 6, iclass 19, count 0 2006.245.07:38:21.23#ibcon#read 6, iclass 19, count 0 2006.245.07:38:21.23#ibcon#end of sib2, iclass 19, count 0 2006.245.07:38:21.23#ibcon#*after write, iclass 19, count 0 2006.245.07:38:21.23#ibcon#*before return 0, iclass 19, count 0 2006.245.07:38:21.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:21.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:21.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:38:21.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:38:21.23$vc4f8/valo=4,832.99 2006.245.07:38:21.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.07:38:21.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.07:38:21.23#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:21.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:21.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:21.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:21.23#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:38:21.23#ibcon#first serial, iclass 21, count 0 2006.245.07:38:21.23#ibcon#enter sib2, iclass 21, count 0 2006.245.07:38:21.23#ibcon#flushed, iclass 21, count 0 2006.245.07:38:21.23#ibcon#about to write, iclass 21, count 0 2006.245.07:38:21.23#ibcon#wrote, iclass 21, count 0 2006.245.07:38:21.23#ibcon#about to read 3, iclass 21, count 0 2006.245.07:38:21.25#ibcon#read 3, iclass 21, count 0 2006.245.07:38:21.25#ibcon#about to read 4, iclass 21, count 0 2006.245.07:38:21.25#ibcon#read 4, iclass 21, count 0 2006.245.07:38:21.25#ibcon#about to read 5, iclass 21, count 0 2006.245.07:38:21.25#ibcon#read 5, iclass 21, count 0 2006.245.07:38:21.25#ibcon#about to read 6, iclass 21, count 0 2006.245.07:38:21.25#ibcon#read 6, iclass 21, count 0 2006.245.07:38:21.25#ibcon#end of sib2, iclass 21, count 0 2006.245.07:38:21.25#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:38:21.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:38:21.25#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:38:21.25#ibcon#*before write, iclass 21, count 0 2006.245.07:38:21.25#ibcon#enter sib2, iclass 21, count 0 2006.245.07:38:21.25#ibcon#flushed, iclass 21, count 0 2006.245.07:38:21.25#ibcon#about to write, iclass 21, count 0 2006.245.07:38:21.25#ibcon#wrote, iclass 21, count 0 2006.245.07:38:21.25#ibcon#about to read 3, iclass 21, count 0 2006.245.07:38:21.29#ibcon#read 3, iclass 21, count 0 2006.245.07:38:21.29#ibcon#about to read 4, iclass 21, count 0 2006.245.07:38:21.29#ibcon#read 4, iclass 21, count 0 2006.245.07:38:21.29#ibcon#about to read 5, iclass 21, count 0 2006.245.07:38:21.29#ibcon#read 5, iclass 21, count 0 2006.245.07:38:21.29#ibcon#about to read 6, iclass 21, count 0 2006.245.07:38:21.29#ibcon#read 6, iclass 21, count 0 2006.245.07:38:21.29#ibcon#end of sib2, iclass 21, count 0 2006.245.07:38:21.29#ibcon#*after write, iclass 21, count 0 2006.245.07:38:21.29#ibcon#*before return 0, iclass 21, count 0 2006.245.07:38:21.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:21.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:21.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:38:21.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:38:21.29$vc4f8/va=4,7 2006.245.07:38:21.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.07:38:21.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.07:38:21.29#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:21.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:21.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:21.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:21.35#ibcon#enter wrdev, iclass 23, count 2 2006.245.07:38:21.35#ibcon#first serial, iclass 23, count 2 2006.245.07:38:21.35#ibcon#enter sib2, iclass 23, count 2 2006.245.07:38:21.35#ibcon#flushed, iclass 23, count 2 2006.245.07:38:21.35#ibcon#about to write, iclass 23, count 2 2006.245.07:38:21.35#ibcon#wrote, iclass 23, count 2 2006.245.07:38:21.35#ibcon#about to read 3, iclass 23, count 2 2006.245.07:38:21.37#ibcon#read 3, iclass 23, count 2 2006.245.07:38:21.37#ibcon#about to read 4, iclass 23, count 2 2006.245.07:38:21.37#ibcon#read 4, iclass 23, count 2 2006.245.07:38:21.37#ibcon#about to read 5, iclass 23, count 2 2006.245.07:38:21.37#ibcon#read 5, iclass 23, count 2 2006.245.07:38:21.37#ibcon#about to read 6, iclass 23, count 2 2006.245.07:38:21.37#ibcon#read 6, iclass 23, count 2 2006.245.07:38:21.37#ibcon#end of sib2, iclass 23, count 2 2006.245.07:38:21.37#ibcon#*mode == 0, iclass 23, count 2 2006.245.07:38:21.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.07:38:21.37#ibcon#[25=AT04-07\r\n] 2006.245.07:38:21.37#ibcon#*before write, iclass 23, count 2 2006.245.07:38:21.37#ibcon#enter sib2, iclass 23, count 2 2006.245.07:38:21.37#ibcon#flushed, iclass 23, count 2 2006.245.07:38:21.37#ibcon#about to write, iclass 23, count 2 2006.245.07:38:21.37#ibcon#wrote, iclass 23, count 2 2006.245.07:38:21.37#ibcon#about to read 3, iclass 23, count 2 2006.245.07:38:21.40#ibcon#read 3, iclass 23, count 2 2006.245.07:38:21.40#ibcon#about to read 4, iclass 23, count 2 2006.245.07:38:21.40#ibcon#read 4, iclass 23, count 2 2006.245.07:38:21.40#ibcon#about to read 5, iclass 23, count 2 2006.245.07:38:21.40#ibcon#read 5, iclass 23, count 2 2006.245.07:38:21.40#ibcon#about to read 6, iclass 23, count 2 2006.245.07:38:21.40#ibcon#read 6, iclass 23, count 2 2006.245.07:38:21.40#ibcon#end of sib2, iclass 23, count 2 2006.245.07:38:21.40#ibcon#*after write, iclass 23, count 2 2006.245.07:38:21.40#ibcon#*before return 0, iclass 23, count 2 2006.245.07:38:21.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:21.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:21.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.07:38:21.40#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:21.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:21.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:21.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:21.52#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:38:21.52#ibcon#first serial, iclass 23, count 0 2006.245.07:38:21.52#ibcon#enter sib2, iclass 23, count 0 2006.245.07:38:21.52#ibcon#flushed, iclass 23, count 0 2006.245.07:38:21.52#ibcon#about to write, iclass 23, count 0 2006.245.07:38:21.52#ibcon#wrote, iclass 23, count 0 2006.245.07:38:21.52#ibcon#about to read 3, iclass 23, count 0 2006.245.07:38:21.54#ibcon#read 3, iclass 23, count 0 2006.245.07:38:21.54#ibcon#about to read 4, iclass 23, count 0 2006.245.07:38:21.54#ibcon#read 4, iclass 23, count 0 2006.245.07:38:21.54#ibcon#about to read 5, iclass 23, count 0 2006.245.07:38:21.54#ibcon#read 5, iclass 23, count 0 2006.245.07:38:21.54#ibcon#about to read 6, iclass 23, count 0 2006.245.07:38:21.54#ibcon#read 6, iclass 23, count 0 2006.245.07:38:21.54#ibcon#end of sib2, iclass 23, count 0 2006.245.07:38:21.54#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:38:21.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:38:21.54#ibcon#[25=USB\r\n] 2006.245.07:38:21.54#ibcon#*before write, iclass 23, count 0 2006.245.07:38:21.54#ibcon#enter sib2, iclass 23, count 0 2006.245.07:38:21.54#ibcon#flushed, iclass 23, count 0 2006.245.07:38:21.54#ibcon#about to write, iclass 23, count 0 2006.245.07:38:21.54#ibcon#wrote, iclass 23, count 0 2006.245.07:38:21.54#ibcon#about to read 3, iclass 23, count 0 2006.245.07:38:21.57#ibcon#read 3, iclass 23, count 0 2006.245.07:38:21.57#ibcon#about to read 4, iclass 23, count 0 2006.245.07:38:21.57#ibcon#read 4, iclass 23, count 0 2006.245.07:38:21.57#ibcon#about to read 5, iclass 23, count 0 2006.245.07:38:21.57#ibcon#read 5, iclass 23, count 0 2006.245.07:38:21.57#ibcon#about to read 6, iclass 23, count 0 2006.245.07:38:21.57#ibcon#read 6, iclass 23, count 0 2006.245.07:38:21.57#ibcon#end of sib2, iclass 23, count 0 2006.245.07:38:21.57#ibcon#*after write, iclass 23, count 0 2006.245.07:38:21.57#ibcon#*before return 0, iclass 23, count 0 2006.245.07:38:21.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:21.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:21.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:38:21.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:38:21.57$vc4f8/valo=5,652.99 2006.245.07:38:21.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.07:38:21.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.07:38:21.57#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:21.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:21.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:21.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:21.57#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:38:21.57#ibcon#first serial, iclass 25, count 0 2006.245.07:38:21.57#ibcon#enter sib2, iclass 25, count 0 2006.245.07:38:21.57#ibcon#flushed, iclass 25, count 0 2006.245.07:38:21.57#ibcon#about to write, iclass 25, count 0 2006.245.07:38:21.57#ibcon#wrote, iclass 25, count 0 2006.245.07:38:21.57#ibcon#about to read 3, iclass 25, count 0 2006.245.07:38:21.59#ibcon#read 3, iclass 25, count 0 2006.245.07:38:21.59#ibcon#about to read 4, iclass 25, count 0 2006.245.07:38:21.59#ibcon#read 4, iclass 25, count 0 2006.245.07:38:21.59#ibcon#about to read 5, iclass 25, count 0 2006.245.07:38:21.59#ibcon#read 5, iclass 25, count 0 2006.245.07:38:21.59#ibcon#about to read 6, iclass 25, count 0 2006.245.07:38:21.59#ibcon#read 6, iclass 25, count 0 2006.245.07:38:21.59#ibcon#end of sib2, iclass 25, count 0 2006.245.07:38:21.59#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:38:21.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:38:21.59#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:38:21.59#ibcon#*before write, iclass 25, count 0 2006.245.07:38:21.59#ibcon#enter sib2, iclass 25, count 0 2006.245.07:38:21.59#ibcon#flushed, iclass 25, count 0 2006.245.07:38:21.59#ibcon#about to write, iclass 25, count 0 2006.245.07:38:21.59#ibcon#wrote, iclass 25, count 0 2006.245.07:38:21.59#ibcon#about to read 3, iclass 25, count 0 2006.245.07:38:21.63#ibcon#read 3, iclass 25, count 0 2006.245.07:38:21.63#ibcon#about to read 4, iclass 25, count 0 2006.245.07:38:21.63#ibcon#read 4, iclass 25, count 0 2006.245.07:38:21.63#ibcon#about to read 5, iclass 25, count 0 2006.245.07:38:21.63#ibcon#read 5, iclass 25, count 0 2006.245.07:38:21.63#ibcon#about to read 6, iclass 25, count 0 2006.245.07:38:21.63#ibcon#read 6, iclass 25, count 0 2006.245.07:38:21.63#ibcon#end of sib2, iclass 25, count 0 2006.245.07:38:21.63#ibcon#*after write, iclass 25, count 0 2006.245.07:38:21.63#ibcon#*before return 0, iclass 25, count 0 2006.245.07:38:21.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:21.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:21.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:38:21.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:38:21.63$vc4f8/va=5,7 2006.245.07:38:21.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.07:38:21.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.07:38:21.63#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:21.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:21.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:21.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:21.69#ibcon#enter wrdev, iclass 27, count 2 2006.245.07:38:21.69#ibcon#first serial, iclass 27, count 2 2006.245.07:38:21.69#ibcon#enter sib2, iclass 27, count 2 2006.245.07:38:21.69#ibcon#flushed, iclass 27, count 2 2006.245.07:38:21.69#ibcon#about to write, iclass 27, count 2 2006.245.07:38:21.69#ibcon#wrote, iclass 27, count 2 2006.245.07:38:21.69#ibcon#about to read 3, iclass 27, count 2 2006.245.07:38:21.71#ibcon#read 3, iclass 27, count 2 2006.245.07:38:21.71#ibcon#about to read 4, iclass 27, count 2 2006.245.07:38:21.71#ibcon#read 4, iclass 27, count 2 2006.245.07:38:21.71#ibcon#about to read 5, iclass 27, count 2 2006.245.07:38:21.71#ibcon#read 5, iclass 27, count 2 2006.245.07:38:21.71#ibcon#about to read 6, iclass 27, count 2 2006.245.07:38:21.71#ibcon#read 6, iclass 27, count 2 2006.245.07:38:21.71#ibcon#end of sib2, iclass 27, count 2 2006.245.07:38:21.71#ibcon#*mode == 0, iclass 27, count 2 2006.245.07:38:21.71#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.07:38:21.71#ibcon#[25=AT05-07\r\n] 2006.245.07:38:21.71#ibcon#*before write, iclass 27, count 2 2006.245.07:38:21.71#ibcon#enter sib2, iclass 27, count 2 2006.245.07:38:21.71#ibcon#flushed, iclass 27, count 2 2006.245.07:38:21.71#ibcon#about to write, iclass 27, count 2 2006.245.07:38:21.71#ibcon#wrote, iclass 27, count 2 2006.245.07:38:21.71#ibcon#about to read 3, iclass 27, count 2 2006.245.07:38:21.74#ibcon#read 3, iclass 27, count 2 2006.245.07:38:21.74#ibcon#about to read 4, iclass 27, count 2 2006.245.07:38:21.74#ibcon#read 4, iclass 27, count 2 2006.245.07:38:21.74#ibcon#about to read 5, iclass 27, count 2 2006.245.07:38:21.74#ibcon#read 5, iclass 27, count 2 2006.245.07:38:21.74#ibcon#about to read 6, iclass 27, count 2 2006.245.07:38:21.74#ibcon#read 6, iclass 27, count 2 2006.245.07:38:21.74#ibcon#end of sib2, iclass 27, count 2 2006.245.07:38:21.74#ibcon#*after write, iclass 27, count 2 2006.245.07:38:21.74#ibcon#*before return 0, iclass 27, count 2 2006.245.07:38:21.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:21.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:21.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.07:38:21.74#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:21.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:21.86#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:21.86#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:21.86#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:38:21.86#ibcon#first serial, iclass 27, count 0 2006.245.07:38:21.86#ibcon#enter sib2, iclass 27, count 0 2006.245.07:38:21.86#ibcon#flushed, iclass 27, count 0 2006.245.07:38:21.86#ibcon#about to write, iclass 27, count 0 2006.245.07:38:21.86#ibcon#wrote, iclass 27, count 0 2006.245.07:38:21.86#ibcon#about to read 3, iclass 27, count 0 2006.245.07:38:21.88#ibcon#read 3, iclass 27, count 0 2006.245.07:38:21.88#ibcon#about to read 4, iclass 27, count 0 2006.245.07:38:21.88#ibcon#read 4, iclass 27, count 0 2006.245.07:38:21.88#ibcon#about to read 5, iclass 27, count 0 2006.245.07:38:21.88#ibcon#read 5, iclass 27, count 0 2006.245.07:38:21.88#ibcon#about to read 6, iclass 27, count 0 2006.245.07:38:21.88#ibcon#read 6, iclass 27, count 0 2006.245.07:38:21.88#ibcon#end of sib2, iclass 27, count 0 2006.245.07:38:21.88#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:38:21.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:38:21.88#ibcon#[25=USB\r\n] 2006.245.07:38:21.88#ibcon#*before write, iclass 27, count 0 2006.245.07:38:21.88#ibcon#enter sib2, iclass 27, count 0 2006.245.07:38:21.88#ibcon#flushed, iclass 27, count 0 2006.245.07:38:21.88#ibcon#about to write, iclass 27, count 0 2006.245.07:38:21.88#ibcon#wrote, iclass 27, count 0 2006.245.07:38:21.88#ibcon#about to read 3, iclass 27, count 0 2006.245.07:38:21.91#ibcon#read 3, iclass 27, count 0 2006.245.07:38:21.91#ibcon#about to read 4, iclass 27, count 0 2006.245.07:38:21.91#ibcon#read 4, iclass 27, count 0 2006.245.07:38:21.91#ibcon#about to read 5, iclass 27, count 0 2006.245.07:38:21.91#ibcon#read 5, iclass 27, count 0 2006.245.07:38:21.91#ibcon#about to read 6, iclass 27, count 0 2006.245.07:38:21.91#ibcon#read 6, iclass 27, count 0 2006.245.07:38:21.91#ibcon#end of sib2, iclass 27, count 0 2006.245.07:38:21.91#ibcon#*after write, iclass 27, count 0 2006.245.07:38:21.91#ibcon#*before return 0, iclass 27, count 0 2006.245.07:38:21.91#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:21.91#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:21.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:38:21.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:38:21.91$vc4f8/valo=6,772.99 2006.245.07:38:21.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.07:38:21.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.07:38:21.91#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:21.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:21.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:21.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:21.91#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:38:21.91#ibcon#first serial, iclass 29, count 0 2006.245.07:38:21.91#ibcon#enter sib2, iclass 29, count 0 2006.245.07:38:21.91#ibcon#flushed, iclass 29, count 0 2006.245.07:38:21.91#ibcon#about to write, iclass 29, count 0 2006.245.07:38:21.91#ibcon#wrote, iclass 29, count 0 2006.245.07:38:21.91#ibcon#about to read 3, iclass 29, count 0 2006.245.07:38:21.93#ibcon#read 3, iclass 29, count 0 2006.245.07:38:21.93#ibcon#about to read 4, iclass 29, count 0 2006.245.07:38:21.93#ibcon#read 4, iclass 29, count 0 2006.245.07:38:21.93#ibcon#about to read 5, iclass 29, count 0 2006.245.07:38:21.93#ibcon#read 5, iclass 29, count 0 2006.245.07:38:21.93#ibcon#about to read 6, iclass 29, count 0 2006.245.07:38:21.93#ibcon#read 6, iclass 29, count 0 2006.245.07:38:21.93#ibcon#end of sib2, iclass 29, count 0 2006.245.07:38:21.93#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:38:21.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:38:21.93#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:38:21.93#ibcon#*before write, iclass 29, count 0 2006.245.07:38:21.93#ibcon#enter sib2, iclass 29, count 0 2006.245.07:38:21.93#ibcon#flushed, iclass 29, count 0 2006.245.07:38:21.93#ibcon#about to write, iclass 29, count 0 2006.245.07:38:21.93#ibcon#wrote, iclass 29, count 0 2006.245.07:38:21.93#ibcon#about to read 3, iclass 29, count 0 2006.245.07:38:21.97#ibcon#read 3, iclass 29, count 0 2006.245.07:38:21.97#ibcon#about to read 4, iclass 29, count 0 2006.245.07:38:21.97#ibcon#read 4, iclass 29, count 0 2006.245.07:38:21.97#ibcon#about to read 5, iclass 29, count 0 2006.245.07:38:21.97#ibcon#read 5, iclass 29, count 0 2006.245.07:38:21.97#ibcon#about to read 6, iclass 29, count 0 2006.245.07:38:21.97#ibcon#read 6, iclass 29, count 0 2006.245.07:38:21.97#ibcon#end of sib2, iclass 29, count 0 2006.245.07:38:21.97#ibcon#*after write, iclass 29, count 0 2006.245.07:38:21.97#ibcon#*before return 0, iclass 29, count 0 2006.245.07:38:21.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:21.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:21.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:38:21.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:38:21.97$vc4f8/va=6,7 2006.245.07:38:21.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.07:38:21.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.07:38:21.97#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:21.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:38:22.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:38:22.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:38:22.03#ibcon#enter wrdev, iclass 31, count 2 2006.245.07:38:22.03#ibcon#first serial, iclass 31, count 2 2006.245.07:38:22.03#ibcon#enter sib2, iclass 31, count 2 2006.245.07:38:22.03#ibcon#flushed, iclass 31, count 2 2006.245.07:38:22.03#ibcon#about to write, iclass 31, count 2 2006.245.07:38:22.03#ibcon#wrote, iclass 31, count 2 2006.245.07:38:22.03#ibcon#about to read 3, iclass 31, count 2 2006.245.07:38:22.05#ibcon#read 3, iclass 31, count 2 2006.245.07:38:22.05#ibcon#about to read 4, iclass 31, count 2 2006.245.07:38:22.05#ibcon#read 4, iclass 31, count 2 2006.245.07:38:22.05#ibcon#about to read 5, iclass 31, count 2 2006.245.07:38:22.05#ibcon#read 5, iclass 31, count 2 2006.245.07:38:22.05#ibcon#about to read 6, iclass 31, count 2 2006.245.07:38:22.05#ibcon#read 6, iclass 31, count 2 2006.245.07:38:22.05#ibcon#end of sib2, iclass 31, count 2 2006.245.07:38:22.05#ibcon#*mode == 0, iclass 31, count 2 2006.245.07:38:22.05#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.07:38:22.05#ibcon#[25=AT06-07\r\n] 2006.245.07:38:22.05#ibcon#*before write, iclass 31, count 2 2006.245.07:38:22.05#ibcon#enter sib2, iclass 31, count 2 2006.245.07:38:22.05#ibcon#flushed, iclass 31, count 2 2006.245.07:38:22.05#ibcon#about to write, iclass 31, count 2 2006.245.07:38:22.05#ibcon#wrote, iclass 31, count 2 2006.245.07:38:22.05#ibcon#about to read 3, iclass 31, count 2 2006.245.07:38:22.08#ibcon#read 3, iclass 31, count 2 2006.245.07:38:22.08#ibcon#about to read 4, iclass 31, count 2 2006.245.07:38:22.08#ibcon#read 4, iclass 31, count 2 2006.245.07:38:22.08#ibcon#about to read 5, iclass 31, count 2 2006.245.07:38:22.08#ibcon#read 5, iclass 31, count 2 2006.245.07:38:22.08#ibcon#about to read 6, iclass 31, count 2 2006.245.07:38:22.08#ibcon#read 6, iclass 31, count 2 2006.245.07:38:22.08#ibcon#end of sib2, iclass 31, count 2 2006.245.07:38:22.08#ibcon#*after write, iclass 31, count 2 2006.245.07:38:22.08#ibcon#*before return 0, iclass 31, count 2 2006.245.07:38:22.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:38:22.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:38:22.08#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.07:38:22.08#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:22.08#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:38:22.20#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:38:22.20#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:38:22.20#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:38:22.20#ibcon#first serial, iclass 31, count 0 2006.245.07:38:22.20#ibcon#enter sib2, iclass 31, count 0 2006.245.07:38:22.20#ibcon#flushed, iclass 31, count 0 2006.245.07:38:22.20#ibcon#about to write, iclass 31, count 0 2006.245.07:38:22.20#ibcon#wrote, iclass 31, count 0 2006.245.07:38:22.20#ibcon#about to read 3, iclass 31, count 0 2006.245.07:38:22.22#ibcon#read 3, iclass 31, count 0 2006.245.07:38:22.22#ibcon#about to read 4, iclass 31, count 0 2006.245.07:38:22.22#ibcon#read 4, iclass 31, count 0 2006.245.07:38:22.22#ibcon#about to read 5, iclass 31, count 0 2006.245.07:38:22.22#ibcon#read 5, iclass 31, count 0 2006.245.07:38:22.22#ibcon#about to read 6, iclass 31, count 0 2006.245.07:38:22.22#ibcon#read 6, iclass 31, count 0 2006.245.07:38:22.22#ibcon#end of sib2, iclass 31, count 0 2006.245.07:38:22.22#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:38:22.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:38:22.22#ibcon#[25=USB\r\n] 2006.245.07:38:22.22#ibcon#*before write, iclass 31, count 0 2006.245.07:38:22.22#ibcon#enter sib2, iclass 31, count 0 2006.245.07:38:22.22#ibcon#flushed, iclass 31, count 0 2006.245.07:38:22.22#ibcon#about to write, iclass 31, count 0 2006.245.07:38:22.22#ibcon#wrote, iclass 31, count 0 2006.245.07:38:22.22#ibcon#about to read 3, iclass 31, count 0 2006.245.07:38:22.25#ibcon#read 3, iclass 31, count 0 2006.245.07:38:22.25#ibcon#about to read 4, iclass 31, count 0 2006.245.07:38:22.25#ibcon#read 4, iclass 31, count 0 2006.245.07:38:22.25#ibcon#about to read 5, iclass 31, count 0 2006.245.07:38:22.25#ibcon#read 5, iclass 31, count 0 2006.245.07:38:22.25#ibcon#about to read 6, iclass 31, count 0 2006.245.07:38:22.25#ibcon#read 6, iclass 31, count 0 2006.245.07:38:22.25#ibcon#end of sib2, iclass 31, count 0 2006.245.07:38:22.25#ibcon#*after write, iclass 31, count 0 2006.245.07:38:22.25#ibcon#*before return 0, iclass 31, count 0 2006.245.07:38:22.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:38:22.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:38:22.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:38:22.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:38:22.25$vc4f8/valo=7,832.99 2006.245.07:38:22.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.07:38:22.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.07:38:22.25#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:22.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:38:22.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:38:22.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:38:22.25#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:38:22.25#ibcon#first serial, iclass 33, count 0 2006.245.07:38:22.25#ibcon#enter sib2, iclass 33, count 0 2006.245.07:38:22.25#ibcon#flushed, iclass 33, count 0 2006.245.07:38:22.25#ibcon#about to write, iclass 33, count 0 2006.245.07:38:22.25#ibcon#wrote, iclass 33, count 0 2006.245.07:38:22.25#ibcon#about to read 3, iclass 33, count 0 2006.245.07:38:22.27#ibcon#read 3, iclass 33, count 0 2006.245.07:38:22.27#ibcon#about to read 4, iclass 33, count 0 2006.245.07:38:22.27#ibcon#read 4, iclass 33, count 0 2006.245.07:38:22.27#ibcon#about to read 5, iclass 33, count 0 2006.245.07:38:22.27#ibcon#read 5, iclass 33, count 0 2006.245.07:38:22.27#ibcon#about to read 6, iclass 33, count 0 2006.245.07:38:22.27#ibcon#read 6, iclass 33, count 0 2006.245.07:38:22.27#ibcon#end of sib2, iclass 33, count 0 2006.245.07:38:22.27#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:38:22.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:38:22.27#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:38:22.27#ibcon#*before write, iclass 33, count 0 2006.245.07:38:22.27#ibcon#enter sib2, iclass 33, count 0 2006.245.07:38:22.27#ibcon#flushed, iclass 33, count 0 2006.245.07:38:22.27#ibcon#about to write, iclass 33, count 0 2006.245.07:38:22.27#ibcon#wrote, iclass 33, count 0 2006.245.07:38:22.27#ibcon#about to read 3, iclass 33, count 0 2006.245.07:38:22.31#ibcon#read 3, iclass 33, count 0 2006.245.07:38:22.31#ibcon#about to read 4, iclass 33, count 0 2006.245.07:38:22.31#ibcon#read 4, iclass 33, count 0 2006.245.07:38:22.31#ibcon#about to read 5, iclass 33, count 0 2006.245.07:38:22.31#ibcon#read 5, iclass 33, count 0 2006.245.07:38:22.31#ibcon#about to read 6, iclass 33, count 0 2006.245.07:38:22.31#ibcon#read 6, iclass 33, count 0 2006.245.07:38:22.31#ibcon#end of sib2, iclass 33, count 0 2006.245.07:38:22.31#ibcon#*after write, iclass 33, count 0 2006.245.07:38:22.31#ibcon#*before return 0, iclass 33, count 0 2006.245.07:38:22.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:38:22.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:38:22.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:38:22.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:38:22.31$vc4f8/va=7,7 2006.245.07:38:22.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.07:38:22.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.07:38:22.31#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:22.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:38:22.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:38:22.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:38:22.37#ibcon#enter wrdev, iclass 35, count 2 2006.245.07:38:22.37#ibcon#first serial, iclass 35, count 2 2006.245.07:38:22.37#ibcon#enter sib2, iclass 35, count 2 2006.245.07:38:22.37#ibcon#flushed, iclass 35, count 2 2006.245.07:38:22.37#ibcon#about to write, iclass 35, count 2 2006.245.07:38:22.37#ibcon#wrote, iclass 35, count 2 2006.245.07:38:22.37#ibcon#about to read 3, iclass 35, count 2 2006.245.07:38:22.39#ibcon#read 3, iclass 35, count 2 2006.245.07:38:22.39#ibcon#about to read 4, iclass 35, count 2 2006.245.07:38:22.39#ibcon#read 4, iclass 35, count 2 2006.245.07:38:22.39#ibcon#about to read 5, iclass 35, count 2 2006.245.07:38:22.39#ibcon#read 5, iclass 35, count 2 2006.245.07:38:22.39#ibcon#about to read 6, iclass 35, count 2 2006.245.07:38:22.39#ibcon#read 6, iclass 35, count 2 2006.245.07:38:22.39#ibcon#end of sib2, iclass 35, count 2 2006.245.07:38:22.39#ibcon#*mode == 0, iclass 35, count 2 2006.245.07:38:22.39#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.07:38:22.39#ibcon#[25=AT07-07\r\n] 2006.245.07:38:22.39#ibcon#*before write, iclass 35, count 2 2006.245.07:38:22.39#ibcon#enter sib2, iclass 35, count 2 2006.245.07:38:22.39#ibcon#flushed, iclass 35, count 2 2006.245.07:38:22.39#ibcon#about to write, iclass 35, count 2 2006.245.07:38:22.39#ibcon#wrote, iclass 35, count 2 2006.245.07:38:22.39#ibcon#about to read 3, iclass 35, count 2 2006.245.07:38:22.42#ibcon#read 3, iclass 35, count 2 2006.245.07:38:22.42#ibcon#about to read 4, iclass 35, count 2 2006.245.07:38:22.42#ibcon#read 4, iclass 35, count 2 2006.245.07:38:22.42#ibcon#about to read 5, iclass 35, count 2 2006.245.07:38:22.42#ibcon#read 5, iclass 35, count 2 2006.245.07:38:22.42#ibcon#about to read 6, iclass 35, count 2 2006.245.07:38:22.42#ibcon#read 6, iclass 35, count 2 2006.245.07:38:22.42#ibcon#end of sib2, iclass 35, count 2 2006.245.07:38:22.42#ibcon#*after write, iclass 35, count 2 2006.245.07:38:22.42#ibcon#*before return 0, iclass 35, count 2 2006.245.07:38:22.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:38:22.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:38:22.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.07:38:22.42#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:22.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:38:22.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:38:22.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:38:22.54#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:38:22.54#ibcon#first serial, iclass 35, count 0 2006.245.07:38:22.54#ibcon#enter sib2, iclass 35, count 0 2006.245.07:38:22.54#ibcon#flushed, iclass 35, count 0 2006.245.07:38:22.54#ibcon#about to write, iclass 35, count 0 2006.245.07:38:22.54#ibcon#wrote, iclass 35, count 0 2006.245.07:38:22.54#ibcon#about to read 3, iclass 35, count 0 2006.245.07:38:22.56#ibcon#read 3, iclass 35, count 0 2006.245.07:38:22.56#ibcon#about to read 4, iclass 35, count 0 2006.245.07:38:22.56#ibcon#read 4, iclass 35, count 0 2006.245.07:38:22.56#ibcon#about to read 5, iclass 35, count 0 2006.245.07:38:22.56#ibcon#read 5, iclass 35, count 0 2006.245.07:38:22.56#ibcon#about to read 6, iclass 35, count 0 2006.245.07:38:22.56#ibcon#read 6, iclass 35, count 0 2006.245.07:38:22.56#ibcon#end of sib2, iclass 35, count 0 2006.245.07:38:22.56#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:38:22.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:38:22.56#ibcon#[25=USB\r\n] 2006.245.07:38:22.56#ibcon#*before write, iclass 35, count 0 2006.245.07:38:22.56#ibcon#enter sib2, iclass 35, count 0 2006.245.07:38:22.56#ibcon#flushed, iclass 35, count 0 2006.245.07:38:22.56#ibcon#about to write, iclass 35, count 0 2006.245.07:38:22.56#ibcon#wrote, iclass 35, count 0 2006.245.07:38:22.56#ibcon#about to read 3, iclass 35, count 0 2006.245.07:38:22.59#ibcon#read 3, iclass 35, count 0 2006.245.07:38:22.59#ibcon#about to read 4, iclass 35, count 0 2006.245.07:38:22.59#ibcon#read 4, iclass 35, count 0 2006.245.07:38:22.59#ibcon#about to read 5, iclass 35, count 0 2006.245.07:38:22.59#ibcon#read 5, iclass 35, count 0 2006.245.07:38:22.59#ibcon#about to read 6, iclass 35, count 0 2006.245.07:38:22.59#ibcon#read 6, iclass 35, count 0 2006.245.07:38:22.59#ibcon#end of sib2, iclass 35, count 0 2006.245.07:38:22.59#ibcon#*after write, iclass 35, count 0 2006.245.07:38:22.59#ibcon#*before return 0, iclass 35, count 0 2006.245.07:38:22.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:38:22.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:38:22.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:38:22.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:38:22.59$vc4f8/valo=8,852.99 2006.245.07:38:22.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.07:38:22.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.07:38:22.59#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:22.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:38:22.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:38:22.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:38:22.59#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:38:22.59#ibcon#first serial, iclass 37, count 0 2006.245.07:38:22.59#ibcon#enter sib2, iclass 37, count 0 2006.245.07:38:22.59#ibcon#flushed, iclass 37, count 0 2006.245.07:38:22.59#ibcon#about to write, iclass 37, count 0 2006.245.07:38:22.59#ibcon#wrote, iclass 37, count 0 2006.245.07:38:22.59#ibcon#about to read 3, iclass 37, count 0 2006.245.07:38:22.61#ibcon#read 3, iclass 37, count 0 2006.245.07:38:22.61#ibcon#about to read 4, iclass 37, count 0 2006.245.07:38:22.61#ibcon#read 4, iclass 37, count 0 2006.245.07:38:22.61#ibcon#about to read 5, iclass 37, count 0 2006.245.07:38:22.61#ibcon#read 5, iclass 37, count 0 2006.245.07:38:22.61#ibcon#about to read 6, iclass 37, count 0 2006.245.07:38:22.61#ibcon#read 6, iclass 37, count 0 2006.245.07:38:22.61#ibcon#end of sib2, iclass 37, count 0 2006.245.07:38:22.61#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:38:22.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:38:22.61#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:38:22.61#ibcon#*before write, iclass 37, count 0 2006.245.07:38:22.61#ibcon#enter sib2, iclass 37, count 0 2006.245.07:38:22.61#ibcon#flushed, iclass 37, count 0 2006.245.07:38:22.61#ibcon#about to write, iclass 37, count 0 2006.245.07:38:22.61#ibcon#wrote, iclass 37, count 0 2006.245.07:38:22.61#ibcon#about to read 3, iclass 37, count 0 2006.245.07:38:22.65#ibcon#read 3, iclass 37, count 0 2006.245.07:38:22.65#ibcon#about to read 4, iclass 37, count 0 2006.245.07:38:22.65#ibcon#read 4, iclass 37, count 0 2006.245.07:38:22.65#ibcon#about to read 5, iclass 37, count 0 2006.245.07:38:22.65#ibcon#read 5, iclass 37, count 0 2006.245.07:38:22.65#ibcon#about to read 6, iclass 37, count 0 2006.245.07:38:22.65#ibcon#read 6, iclass 37, count 0 2006.245.07:38:22.65#ibcon#end of sib2, iclass 37, count 0 2006.245.07:38:22.65#ibcon#*after write, iclass 37, count 0 2006.245.07:38:22.65#ibcon#*before return 0, iclass 37, count 0 2006.245.07:38:22.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:38:22.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:38:22.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:38:22.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:38:22.65$vc4f8/va=8,8 2006.245.07:38:22.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.07:38:22.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.07:38:22.65#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:22.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:38:22.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:38:22.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:38:22.71#ibcon#enter wrdev, iclass 39, count 2 2006.245.07:38:22.71#ibcon#first serial, iclass 39, count 2 2006.245.07:38:22.71#ibcon#enter sib2, iclass 39, count 2 2006.245.07:38:22.71#ibcon#flushed, iclass 39, count 2 2006.245.07:38:22.71#ibcon#about to write, iclass 39, count 2 2006.245.07:38:22.71#ibcon#wrote, iclass 39, count 2 2006.245.07:38:22.71#ibcon#about to read 3, iclass 39, count 2 2006.245.07:38:22.73#ibcon#read 3, iclass 39, count 2 2006.245.07:38:22.73#ibcon#about to read 4, iclass 39, count 2 2006.245.07:38:22.73#ibcon#read 4, iclass 39, count 2 2006.245.07:38:22.73#ibcon#about to read 5, iclass 39, count 2 2006.245.07:38:22.73#ibcon#read 5, iclass 39, count 2 2006.245.07:38:22.73#ibcon#about to read 6, iclass 39, count 2 2006.245.07:38:22.73#ibcon#read 6, iclass 39, count 2 2006.245.07:38:22.73#ibcon#end of sib2, iclass 39, count 2 2006.245.07:38:22.73#ibcon#*mode == 0, iclass 39, count 2 2006.245.07:38:22.73#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.07:38:22.73#ibcon#[25=AT08-08\r\n] 2006.245.07:38:22.73#ibcon#*before write, iclass 39, count 2 2006.245.07:38:22.73#ibcon#enter sib2, iclass 39, count 2 2006.245.07:38:22.73#ibcon#flushed, iclass 39, count 2 2006.245.07:38:22.73#ibcon#about to write, iclass 39, count 2 2006.245.07:38:22.73#ibcon#wrote, iclass 39, count 2 2006.245.07:38:22.73#ibcon#about to read 3, iclass 39, count 2 2006.245.07:38:22.76#ibcon#read 3, iclass 39, count 2 2006.245.07:38:22.76#ibcon#about to read 4, iclass 39, count 2 2006.245.07:38:22.76#ibcon#read 4, iclass 39, count 2 2006.245.07:38:22.76#ibcon#about to read 5, iclass 39, count 2 2006.245.07:38:22.76#ibcon#read 5, iclass 39, count 2 2006.245.07:38:22.76#ibcon#about to read 6, iclass 39, count 2 2006.245.07:38:22.76#ibcon#read 6, iclass 39, count 2 2006.245.07:38:22.76#ibcon#end of sib2, iclass 39, count 2 2006.245.07:38:22.76#ibcon#*after write, iclass 39, count 2 2006.245.07:38:22.76#ibcon#*before return 0, iclass 39, count 2 2006.245.07:38:22.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:38:22.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:38:22.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.07:38:22.76#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:22.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:38:22.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:38:22.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:38:22.88#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:38:22.88#ibcon#first serial, iclass 39, count 0 2006.245.07:38:22.88#ibcon#enter sib2, iclass 39, count 0 2006.245.07:38:22.88#ibcon#flushed, iclass 39, count 0 2006.245.07:38:22.88#ibcon#about to write, iclass 39, count 0 2006.245.07:38:22.88#ibcon#wrote, iclass 39, count 0 2006.245.07:38:22.88#ibcon#about to read 3, iclass 39, count 0 2006.245.07:38:22.90#ibcon#read 3, iclass 39, count 0 2006.245.07:38:22.90#ibcon#about to read 4, iclass 39, count 0 2006.245.07:38:22.90#ibcon#read 4, iclass 39, count 0 2006.245.07:38:22.90#ibcon#about to read 5, iclass 39, count 0 2006.245.07:38:22.90#ibcon#read 5, iclass 39, count 0 2006.245.07:38:22.90#ibcon#about to read 6, iclass 39, count 0 2006.245.07:38:22.90#ibcon#read 6, iclass 39, count 0 2006.245.07:38:22.90#ibcon#end of sib2, iclass 39, count 0 2006.245.07:38:22.90#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:38:22.90#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:38:22.90#ibcon#[25=USB\r\n] 2006.245.07:38:22.90#ibcon#*before write, iclass 39, count 0 2006.245.07:38:22.90#ibcon#enter sib2, iclass 39, count 0 2006.245.07:38:22.90#ibcon#flushed, iclass 39, count 0 2006.245.07:38:22.90#ibcon#about to write, iclass 39, count 0 2006.245.07:38:22.90#ibcon#wrote, iclass 39, count 0 2006.245.07:38:22.90#ibcon#about to read 3, iclass 39, count 0 2006.245.07:38:22.93#ibcon#read 3, iclass 39, count 0 2006.245.07:38:22.93#ibcon#about to read 4, iclass 39, count 0 2006.245.07:38:22.93#ibcon#read 4, iclass 39, count 0 2006.245.07:38:22.93#ibcon#about to read 5, iclass 39, count 0 2006.245.07:38:22.93#ibcon#read 5, iclass 39, count 0 2006.245.07:38:22.93#ibcon#about to read 6, iclass 39, count 0 2006.245.07:38:22.93#ibcon#read 6, iclass 39, count 0 2006.245.07:38:22.93#ibcon#end of sib2, iclass 39, count 0 2006.245.07:38:22.93#ibcon#*after write, iclass 39, count 0 2006.245.07:38:22.93#ibcon#*before return 0, iclass 39, count 0 2006.245.07:38:22.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:38:22.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:38:22.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:38:22.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:38:22.93$vc4f8/vblo=1,632.99 2006.245.07:38:22.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.07:38:22.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.07:38:22.93#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:22.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:38:22.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:38:22.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:38:22.93#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:38:22.93#ibcon#first serial, iclass 3, count 0 2006.245.07:38:22.93#ibcon#enter sib2, iclass 3, count 0 2006.245.07:38:22.93#ibcon#flushed, iclass 3, count 0 2006.245.07:38:22.93#ibcon#about to write, iclass 3, count 0 2006.245.07:38:22.93#ibcon#wrote, iclass 3, count 0 2006.245.07:38:22.93#ibcon#about to read 3, iclass 3, count 0 2006.245.07:38:22.95#ibcon#read 3, iclass 3, count 0 2006.245.07:38:22.95#ibcon#about to read 4, iclass 3, count 0 2006.245.07:38:22.95#ibcon#read 4, iclass 3, count 0 2006.245.07:38:22.95#ibcon#about to read 5, iclass 3, count 0 2006.245.07:38:22.95#ibcon#read 5, iclass 3, count 0 2006.245.07:38:22.95#ibcon#about to read 6, iclass 3, count 0 2006.245.07:38:22.95#ibcon#read 6, iclass 3, count 0 2006.245.07:38:22.95#ibcon#end of sib2, iclass 3, count 0 2006.245.07:38:22.95#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:38:22.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:38:22.95#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:38:22.95#ibcon#*before write, iclass 3, count 0 2006.245.07:38:22.95#ibcon#enter sib2, iclass 3, count 0 2006.245.07:38:22.95#ibcon#flushed, iclass 3, count 0 2006.245.07:38:22.95#ibcon#about to write, iclass 3, count 0 2006.245.07:38:22.95#ibcon#wrote, iclass 3, count 0 2006.245.07:38:22.95#ibcon#about to read 3, iclass 3, count 0 2006.245.07:38:22.99#ibcon#read 3, iclass 3, count 0 2006.245.07:38:22.99#ibcon#about to read 4, iclass 3, count 0 2006.245.07:38:22.99#ibcon#read 4, iclass 3, count 0 2006.245.07:38:22.99#ibcon#about to read 5, iclass 3, count 0 2006.245.07:38:22.99#ibcon#read 5, iclass 3, count 0 2006.245.07:38:22.99#ibcon#about to read 6, iclass 3, count 0 2006.245.07:38:22.99#ibcon#read 6, iclass 3, count 0 2006.245.07:38:22.99#ibcon#end of sib2, iclass 3, count 0 2006.245.07:38:22.99#ibcon#*after write, iclass 3, count 0 2006.245.07:38:22.99#ibcon#*before return 0, iclass 3, count 0 2006.245.07:38:22.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:38:22.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:38:22.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:38:22.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:38:22.99$vc4f8/vb=1,4 2006.245.07:38:22.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.07:38:22.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.07:38:22.99#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:22.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:38:22.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:38:22.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:38:22.99#ibcon#enter wrdev, iclass 5, count 2 2006.245.07:38:22.99#ibcon#first serial, iclass 5, count 2 2006.245.07:38:22.99#ibcon#enter sib2, iclass 5, count 2 2006.245.07:38:22.99#ibcon#flushed, iclass 5, count 2 2006.245.07:38:22.99#ibcon#about to write, iclass 5, count 2 2006.245.07:38:22.99#ibcon#wrote, iclass 5, count 2 2006.245.07:38:22.99#ibcon#about to read 3, iclass 5, count 2 2006.245.07:38:23.01#ibcon#read 3, iclass 5, count 2 2006.245.07:38:23.01#ibcon#about to read 4, iclass 5, count 2 2006.245.07:38:23.01#ibcon#read 4, iclass 5, count 2 2006.245.07:38:23.01#ibcon#about to read 5, iclass 5, count 2 2006.245.07:38:23.01#ibcon#read 5, iclass 5, count 2 2006.245.07:38:23.01#ibcon#about to read 6, iclass 5, count 2 2006.245.07:38:23.01#ibcon#read 6, iclass 5, count 2 2006.245.07:38:23.01#ibcon#end of sib2, iclass 5, count 2 2006.245.07:38:23.01#ibcon#*mode == 0, iclass 5, count 2 2006.245.07:38:23.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.07:38:23.01#ibcon#[27=AT01-04\r\n] 2006.245.07:38:23.01#ibcon#*before write, iclass 5, count 2 2006.245.07:38:23.01#ibcon#enter sib2, iclass 5, count 2 2006.245.07:38:23.01#ibcon#flushed, iclass 5, count 2 2006.245.07:38:23.01#ibcon#about to write, iclass 5, count 2 2006.245.07:38:23.01#ibcon#wrote, iclass 5, count 2 2006.245.07:38:23.01#ibcon#about to read 3, iclass 5, count 2 2006.245.07:38:23.04#ibcon#read 3, iclass 5, count 2 2006.245.07:38:23.04#ibcon#about to read 4, iclass 5, count 2 2006.245.07:38:23.04#ibcon#read 4, iclass 5, count 2 2006.245.07:38:23.04#ibcon#about to read 5, iclass 5, count 2 2006.245.07:38:23.04#ibcon#read 5, iclass 5, count 2 2006.245.07:38:23.04#ibcon#about to read 6, iclass 5, count 2 2006.245.07:38:23.04#ibcon#read 6, iclass 5, count 2 2006.245.07:38:23.04#ibcon#end of sib2, iclass 5, count 2 2006.245.07:38:23.04#ibcon#*after write, iclass 5, count 2 2006.245.07:38:23.04#ibcon#*before return 0, iclass 5, count 2 2006.245.07:38:23.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:38:23.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:38:23.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.07:38:23.04#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:23.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:38:23.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:38:23.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:38:23.16#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:38:23.16#ibcon#first serial, iclass 5, count 0 2006.245.07:38:23.16#ibcon#enter sib2, iclass 5, count 0 2006.245.07:38:23.16#ibcon#flushed, iclass 5, count 0 2006.245.07:38:23.16#ibcon#about to write, iclass 5, count 0 2006.245.07:38:23.16#ibcon#wrote, iclass 5, count 0 2006.245.07:38:23.16#ibcon#about to read 3, iclass 5, count 0 2006.245.07:38:23.18#ibcon#read 3, iclass 5, count 0 2006.245.07:38:23.18#ibcon#about to read 4, iclass 5, count 0 2006.245.07:38:23.18#ibcon#read 4, iclass 5, count 0 2006.245.07:38:23.18#ibcon#about to read 5, iclass 5, count 0 2006.245.07:38:23.18#ibcon#read 5, iclass 5, count 0 2006.245.07:38:23.18#ibcon#about to read 6, iclass 5, count 0 2006.245.07:38:23.18#ibcon#read 6, iclass 5, count 0 2006.245.07:38:23.18#ibcon#end of sib2, iclass 5, count 0 2006.245.07:38:23.18#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:38:23.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:38:23.18#ibcon#[27=USB\r\n] 2006.245.07:38:23.18#ibcon#*before write, iclass 5, count 0 2006.245.07:38:23.18#ibcon#enter sib2, iclass 5, count 0 2006.245.07:38:23.18#ibcon#flushed, iclass 5, count 0 2006.245.07:38:23.18#ibcon#about to write, iclass 5, count 0 2006.245.07:38:23.18#ibcon#wrote, iclass 5, count 0 2006.245.07:38:23.18#ibcon#about to read 3, iclass 5, count 0 2006.245.07:38:23.21#ibcon#read 3, iclass 5, count 0 2006.245.07:38:23.21#ibcon#about to read 4, iclass 5, count 0 2006.245.07:38:23.21#ibcon#read 4, iclass 5, count 0 2006.245.07:38:23.21#ibcon#about to read 5, iclass 5, count 0 2006.245.07:38:23.21#ibcon#read 5, iclass 5, count 0 2006.245.07:38:23.21#ibcon#about to read 6, iclass 5, count 0 2006.245.07:38:23.21#ibcon#read 6, iclass 5, count 0 2006.245.07:38:23.21#ibcon#end of sib2, iclass 5, count 0 2006.245.07:38:23.21#ibcon#*after write, iclass 5, count 0 2006.245.07:38:23.21#ibcon#*before return 0, iclass 5, count 0 2006.245.07:38:23.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:38:23.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:38:23.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:38:23.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:38:23.21$vc4f8/vblo=2,640.99 2006.245.07:38:23.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:38:23.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:38:23.21#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:23.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:23.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:23.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:23.21#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:38:23.21#ibcon#first serial, iclass 7, count 0 2006.245.07:38:23.21#ibcon#enter sib2, iclass 7, count 0 2006.245.07:38:23.21#ibcon#flushed, iclass 7, count 0 2006.245.07:38:23.21#ibcon#about to write, iclass 7, count 0 2006.245.07:38:23.21#ibcon#wrote, iclass 7, count 0 2006.245.07:38:23.21#ibcon#about to read 3, iclass 7, count 0 2006.245.07:38:23.23#ibcon#read 3, iclass 7, count 0 2006.245.07:38:23.23#ibcon#about to read 4, iclass 7, count 0 2006.245.07:38:23.23#ibcon#read 4, iclass 7, count 0 2006.245.07:38:23.23#ibcon#about to read 5, iclass 7, count 0 2006.245.07:38:23.23#ibcon#read 5, iclass 7, count 0 2006.245.07:38:23.23#ibcon#about to read 6, iclass 7, count 0 2006.245.07:38:23.23#ibcon#read 6, iclass 7, count 0 2006.245.07:38:23.23#ibcon#end of sib2, iclass 7, count 0 2006.245.07:38:23.23#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:38:23.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:38:23.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:38:23.23#ibcon#*before write, iclass 7, count 0 2006.245.07:38:23.23#ibcon#enter sib2, iclass 7, count 0 2006.245.07:38:23.23#ibcon#flushed, iclass 7, count 0 2006.245.07:38:23.23#ibcon#about to write, iclass 7, count 0 2006.245.07:38:23.23#ibcon#wrote, iclass 7, count 0 2006.245.07:38:23.23#ibcon#about to read 3, iclass 7, count 0 2006.245.07:38:23.27#ibcon#read 3, iclass 7, count 0 2006.245.07:38:23.27#ibcon#about to read 4, iclass 7, count 0 2006.245.07:38:23.27#ibcon#read 4, iclass 7, count 0 2006.245.07:38:23.27#ibcon#about to read 5, iclass 7, count 0 2006.245.07:38:23.27#ibcon#read 5, iclass 7, count 0 2006.245.07:38:23.27#ibcon#about to read 6, iclass 7, count 0 2006.245.07:38:23.27#ibcon#read 6, iclass 7, count 0 2006.245.07:38:23.27#ibcon#end of sib2, iclass 7, count 0 2006.245.07:38:23.27#ibcon#*after write, iclass 7, count 0 2006.245.07:38:23.27#ibcon#*before return 0, iclass 7, count 0 2006.245.07:38:23.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:23.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:38:23.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:38:23.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:38:23.27$vc4f8/vb=2,4 2006.245.07:38:23.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.07:38:23.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.07:38:23.27#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:23.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:23.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:23.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:23.33#ibcon#enter wrdev, iclass 11, count 2 2006.245.07:38:23.33#ibcon#first serial, iclass 11, count 2 2006.245.07:38:23.33#ibcon#enter sib2, iclass 11, count 2 2006.245.07:38:23.33#ibcon#flushed, iclass 11, count 2 2006.245.07:38:23.33#ibcon#about to write, iclass 11, count 2 2006.245.07:38:23.33#ibcon#wrote, iclass 11, count 2 2006.245.07:38:23.33#ibcon#about to read 3, iclass 11, count 2 2006.245.07:38:23.35#ibcon#read 3, iclass 11, count 2 2006.245.07:38:23.35#ibcon#about to read 4, iclass 11, count 2 2006.245.07:38:23.35#ibcon#read 4, iclass 11, count 2 2006.245.07:38:23.35#ibcon#about to read 5, iclass 11, count 2 2006.245.07:38:23.35#ibcon#read 5, iclass 11, count 2 2006.245.07:38:23.35#ibcon#about to read 6, iclass 11, count 2 2006.245.07:38:23.35#ibcon#read 6, iclass 11, count 2 2006.245.07:38:23.35#ibcon#end of sib2, iclass 11, count 2 2006.245.07:38:23.35#ibcon#*mode == 0, iclass 11, count 2 2006.245.07:38:23.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.07:38:23.35#ibcon#[27=AT02-04\r\n] 2006.245.07:38:23.35#ibcon#*before write, iclass 11, count 2 2006.245.07:38:23.35#ibcon#enter sib2, iclass 11, count 2 2006.245.07:38:23.35#ibcon#flushed, iclass 11, count 2 2006.245.07:38:23.35#ibcon#about to write, iclass 11, count 2 2006.245.07:38:23.35#ibcon#wrote, iclass 11, count 2 2006.245.07:38:23.35#ibcon#about to read 3, iclass 11, count 2 2006.245.07:38:23.38#ibcon#read 3, iclass 11, count 2 2006.245.07:38:23.38#ibcon#about to read 4, iclass 11, count 2 2006.245.07:38:23.38#ibcon#read 4, iclass 11, count 2 2006.245.07:38:23.38#ibcon#about to read 5, iclass 11, count 2 2006.245.07:38:23.38#ibcon#read 5, iclass 11, count 2 2006.245.07:38:23.38#ibcon#about to read 6, iclass 11, count 2 2006.245.07:38:23.38#ibcon#read 6, iclass 11, count 2 2006.245.07:38:23.38#ibcon#end of sib2, iclass 11, count 2 2006.245.07:38:23.38#ibcon#*after write, iclass 11, count 2 2006.245.07:38:23.38#ibcon#*before return 0, iclass 11, count 2 2006.245.07:38:23.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:23.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:38:23.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.07:38:23.38#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:23.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:23.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:23.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:23.50#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:38:23.50#ibcon#first serial, iclass 11, count 0 2006.245.07:38:23.50#ibcon#enter sib2, iclass 11, count 0 2006.245.07:38:23.50#ibcon#flushed, iclass 11, count 0 2006.245.07:38:23.50#ibcon#about to write, iclass 11, count 0 2006.245.07:38:23.50#ibcon#wrote, iclass 11, count 0 2006.245.07:38:23.50#ibcon#about to read 3, iclass 11, count 0 2006.245.07:38:23.52#ibcon#read 3, iclass 11, count 0 2006.245.07:38:23.52#ibcon#about to read 4, iclass 11, count 0 2006.245.07:38:23.52#ibcon#read 4, iclass 11, count 0 2006.245.07:38:23.52#ibcon#about to read 5, iclass 11, count 0 2006.245.07:38:23.52#ibcon#read 5, iclass 11, count 0 2006.245.07:38:23.52#ibcon#about to read 6, iclass 11, count 0 2006.245.07:38:23.52#ibcon#read 6, iclass 11, count 0 2006.245.07:38:23.52#ibcon#end of sib2, iclass 11, count 0 2006.245.07:38:23.52#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:38:23.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:38:23.52#ibcon#[27=USB\r\n] 2006.245.07:38:23.52#ibcon#*before write, iclass 11, count 0 2006.245.07:38:23.52#ibcon#enter sib2, iclass 11, count 0 2006.245.07:38:23.52#ibcon#flushed, iclass 11, count 0 2006.245.07:38:23.52#ibcon#about to write, iclass 11, count 0 2006.245.07:38:23.52#ibcon#wrote, iclass 11, count 0 2006.245.07:38:23.52#ibcon#about to read 3, iclass 11, count 0 2006.245.07:38:23.55#ibcon#read 3, iclass 11, count 0 2006.245.07:38:23.55#ibcon#about to read 4, iclass 11, count 0 2006.245.07:38:23.55#ibcon#read 4, iclass 11, count 0 2006.245.07:38:23.55#ibcon#about to read 5, iclass 11, count 0 2006.245.07:38:23.55#ibcon#read 5, iclass 11, count 0 2006.245.07:38:23.55#ibcon#about to read 6, iclass 11, count 0 2006.245.07:38:23.55#ibcon#read 6, iclass 11, count 0 2006.245.07:38:23.55#ibcon#end of sib2, iclass 11, count 0 2006.245.07:38:23.55#ibcon#*after write, iclass 11, count 0 2006.245.07:38:23.55#ibcon#*before return 0, iclass 11, count 0 2006.245.07:38:23.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:23.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:38:23.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:38:23.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:38:23.55$vc4f8/vblo=3,656.99 2006.245.07:38:23.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.07:38:23.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.07:38:23.55#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:23.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:23.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:23.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:23.55#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:38:23.55#ibcon#first serial, iclass 13, count 0 2006.245.07:38:23.55#ibcon#enter sib2, iclass 13, count 0 2006.245.07:38:23.55#ibcon#flushed, iclass 13, count 0 2006.245.07:38:23.55#ibcon#about to write, iclass 13, count 0 2006.245.07:38:23.55#ibcon#wrote, iclass 13, count 0 2006.245.07:38:23.55#ibcon#about to read 3, iclass 13, count 0 2006.245.07:38:23.57#ibcon#read 3, iclass 13, count 0 2006.245.07:38:23.57#ibcon#about to read 4, iclass 13, count 0 2006.245.07:38:23.57#ibcon#read 4, iclass 13, count 0 2006.245.07:38:23.57#ibcon#about to read 5, iclass 13, count 0 2006.245.07:38:23.57#ibcon#read 5, iclass 13, count 0 2006.245.07:38:23.57#ibcon#about to read 6, iclass 13, count 0 2006.245.07:38:23.57#ibcon#read 6, iclass 13, count 0 2006.245.07:38:23.57#ibcon#end of sib2, iclass 13, count 0 2006.245.07:38:23.57#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:38:23.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:38:23.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:38:23.57#ibcon#*before write, iclass 13, count 0 2006.245.07:38:23.57#ibcon#enter sib2, iclass 13, count 0 2006.245.07:38:23.57#ibcon#flushed, iclass 13, count 0 2006.245.07:38:23.57#ibcon#about to write, iclass 13, count 0 2006.245.07:38:23.57#ibcon#wrote, iclass 13, count 0 2006.245.07:38:23.57#ibcon#about to read 3, iclass 13, count 0 2006.245.07:38:23.61#ibcon#read 3, iclass 13, count 0 2006.245.07:38:23.61#ibcon#about to read 4, iclass 13, count 0 2006.245.07:38:23.61#ibcon#read 4, iclass 13, count 0 2006.245.07:38:23.61#ibcon#about to read 5, iclass 13, count 0 2006.245.07:38:23.61#ibcon#read 5, iclass 13, count 0 2006.245.07:38:23.61#ibcon#about to read 6, iclass 13, count 0 2006.245.07:38:23.61#ibcon#read 6, iclass 13, count 0 2006.245.07:38:23.61#ibcon#end of sib2, iclass 13, count 0 2006.245.07:38:23.61#ibcon#*after write, iclass 13, count 0 2006.245.07:38:23.61#ibcon#*before return 0, iclass 13, count 0 2006.245.07:38:23.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:23.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:38:23.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:38:23.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:38:23.61$vc4f8/vb=3,4 2006.245.07:38:23.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.07:38:23.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.07:38:23.61#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:23.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:23.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:23.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:23.67#ibcon#enter wrdev, iclass 15, count 2 2006.245.07:38:23.67#ibcon#first serial, iclass 15, count 2 2006.245.07:38:23.67#ibcon#enter sib2, iclass 15, count 2 2006.245.07:38:23.67#ibcon#flushed, iclass 15, count 2 2006.245.07:38:23.67#ibcon#about to write, iclass 15, count 2 2006.245.07:38:23.67#ibcon#wrote, iclass 15, count 2 2006.245.07:38:23.67#ibcon#about to read 3, iclass 15, count 2 2006.245.07:38:23.69#ibcon#read 3, iclass 15, count 2 2006.245.07:38:23.69#ibcon#about to read 4, iclass 15, count 2 2006.245.07:38:23.69#ibcon#read 4, iclass 15, count 2 2006.245.07:38:23.69#ibcon#about to read 5, iclass 15, count 2 2006.245.07:38:23.69#ibcon#read 5, iclass 15, count 2 2006.245.07:38:23.69#ibcon#about to read 6, iclass 15, count 2 2006.245.07:38:23.69#ibcon#read 6, iclass 15, count 2 2006.245.07:38:23.69#ibcon#end of sib2, iclass 15, count 2 2006.245.07:38:23.69#ibcon#*mode == 0, iclass 15, count 2 2006.245.07:38:23.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.07:38:23.69#ibcon#[27=AT03-04\r\n] 2006.245.07:38:23.69#ibcon#*before write, iclass 15, count 2 2006.245.07:38:23.69#ibcon#enter sib2, iclass 15, count 2 2006.245.07:38:23.69#ibcon#flushed, iclass 15, count 2 2006.245.07:38:23.69#ibcon#about to write, iclass 15, count 2 2006.245.07:38:23.69#ibcon#wrote, iclass 15, count 2 2006.245.07:38:23.69#ibcon#about to read 3, iclass 15, count 2 2006.245.07:38:23.72#ibcon#read 3, iclass 15, count 2 2006.245.07:38:23.72#ibcon#about to read 4, iclass 15, count 2 2006.245.07:38:23.72#ibcon#read 4, iclass 15, count 2 2006.245.07:38:23.72#ibcon#about to read 5, iclass 15, count 2 2006.245.07:38:23.72#ibcon#read 5, iclass 15, count 2 2006.245.07:38:23.72#ibcon#about to read 6, iclass 15, count 2 2006.245.07:38:23.72#ibcon#read 6, iclass 15, count 2 2006.245.07:38:23.72#ibcon#end of sib2, iclass 15, count 2 2006.245.07:38:23.72#ibcon#*after write, iclass 15, count 2 2006.245.07:38:23.72#ibcon#*before return 0, iclass 15, count 2 2006.245.07:38:23.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:23.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:38:23.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.07:38:23.72#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:23.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:23.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:23.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:23.84#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:38:23.84#ibcon#first serial, iclass 15, count 0 2006.245.07:38:23.84#ibcon#enter sib2, iclass 15, count 0 2006.245.07:38:23.84#ibcon#flushed, iclass 15, count 0 2006.245.07:38:23.84#ibcon#about to write, iclass 15, count 0 2006.245.07:38:23.84#ibcon#wrote, iclass 15, count 0 2006.245.07:38:23.84#ibcon#about to read 3, iclass 15, count 0 2006.245.07:38:23.86#ibcon#read 3, iclass 15, count 0 2006.245.07:38:23.86#ibcon#about to read 4, iclass 15, count 0 2006.245.07:38:23.86#ibcon#read 4, iclass 15, count 0 2006.245.07:38:23.86#ibcon#about to read 5, iclass 15, count 0 2006.245.07:38:23.86#ibcon#read 5, iclass 15, count 0 2006.245.07:38:23.86#ibcon#about to read 6, iclass 15, count 0 2006.245.07:38:23.86#ibcon#read 6, iclass 15, count 0 2006.245.07:38:23.86#ibcon#end of sib2, iclass 15, count 0 2006.245.07:38:23.86#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:38:23.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:38:23.86#ibcon#[27=USB\r\n] 2006.245.07:38:23.86#ibcon#*before write, iclass 15, count 0 2006.245.07:38:23.86#ibcon#enter sib2, iclass 15, count 0 2006.245.07:38:23.86#ibcon#flushed, iclass 15, count 0 2006.245.07:38:23.86#ibcon#about to write, iclass 15, count 0 2006.245.07:38:23.86#ibcon#wrote, iclass 15, count 0 2006.245.07:38:23.86#ibcon#about to read 3, iclass 15, count 0 2006.245.07:38:23.89#ibcon#read 3, iclass 15, count 0 2006.245.07:38:23.89#ibcon#about to read 4, iclass 15, count 0 2006.245.07:38:23.89#ibcon#read 4, iclass 15, count 0 2006.245.07:38:23.89#ibcon#about to read 5, iclass 15, count 0 2006.245.07:38:23.89#ibcon#read 5, iclass 15, count 0 2006.245.07:38:23.89#ibcon#about to read 6, iclass 15, count 0 2006.245.07:38:23.89#ibcon#read 6, iclass 15, count 0 2006.245.07:38:23.89#ibcon#end of sib2, iclass 15, count 0 2006.245.07:38:23.89#ibcon#*after write, iclass 15, count 0 2006.245.07:38:23.89#ibcon#*before return 0, iclass 15, count 0 2006.245.07:38:23.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:23.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:38:23.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:38:23.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:38:23.89$vc4f8/vblo=4,712.99 2006.245.07:38:23.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.07:38:23.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.07:38:23.89#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:23.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:23.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:23.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:23.89#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:38:23.89#ibcon#first serial, iclass 17, count 0 2006.245.07:38:23.89#ibcon#enter sib2, iclass 17, count 0 2006.245.07:38:23.89#ibcon#flushed, iclass 17, count 0 2006.245.07:38:23.89#ibcon#about to write, iclass 17, count 0 2006.245.07:38:23.89#ibcon#wrote, iclass 17, count 0 2006.245.07:38:23.89#ibcon#about to read 3, iclass 17, count 0 2006.245.07:38:23.91#ibcon#read 3, iclass 17, count 0 2006.245.07:38:23.91#ibcon#about to read 4, iclass 17, count 0 2006.245.07:38:23.91#ibcon#read 4, iclass 17, count 0 2006.245.07:38:23.91#ibcon#about to read 5, iclass 17, count 0 2006.245.07:38:23.91#ibcon#read 5, iclass 17, count 0 2006.245.07:38:23.91#ibcon#about to read 6, iclass 17, count 0 2006.245.07:38:23.91#ibcon#read 6, iclass 17, count 0 2006.245.07:38:23.91#ibcon#end of sib2, iclass 17, count 0 2006.245.07:38:23.91#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:38:23.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:38:23.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:38:23.91#ibcon#*before write, iclass 17, count 0 2006.245.07:38:23.91#ibcon#enter sib2, iclass 17, count 0 2006.245.07:38:23.91#ibcon#flushed, iclass 17, count 0 2006.245.07:38:23.91#ibcon#about to write, iclass 17, count 0 2006.245.07:38:23.91#ibcon#wrote, iclass 17, count 0 2006.245.07:38:23.91#ibcon#about to read 3, iclass 17, count 0 2006.245.07:38:23.95#ibcon#read 3, iclass 17, count 0 2006.245.07:38:23.95#ibcon#about to read 4, iclass 17, count 0 2006.245.07:38:23.95#ibcon#read 4, iclass 17, count 0 2006.245.07:38:23.95#ibcon#about to read 5, iclass 17, count 0 2006.245.07:38:23.95#ibcon#read 5, iclass 17, count 0 2006.245.07:38:23.95#ibcon#about to read 6, iclass 17, count 0 2006.245.07:38:23.95#ibcon#read 6, iclass 17, count 0 2006.245.07:38:23.95#ibcon#end of sib2, iclass 17, count 0 2006.245.07:38:23.95#ibcon#*after write, iclass 17, count 0 2006.245.07:38:23.95#ibcon#*before return 0, iclass 17, count 0 2006.245.07:38:23.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:23.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:38:23.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:38:23.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:38:23.95$vc4f8/vb=4,4 2006.245.07:38:23.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.07:38:23.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.07:38:23.95#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:23.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:24.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:24.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:24.01#ibcon#enter wrdev, iclass 19, count 2 2006.245.07:38:24.01#ibcon#first serial, iclass 19, count 2 2006.245.07:38:24.01#ibcon#enter sib2, iclass 19, count 2 2006.245.07:38:24.01#ibcon#flushed, iclass 19, count 2 2006.245.07:38:24.01#ibcon#about to write, iclass 19, count 2 2006.245.07:38:24.01#ibcon#wrote, iclass 19, count 2 2006.245.07:38:24.01#ibcon#about to read 3, iclass 19, count 2 2006.245.07:38:24.03#ibcon#read 3, iclass 19, count 2 2006.245.07:38:24.03#ibcon#about to read 4, iclass 19, count 2 2006.245.07:38:24.03#ibcon#read 4, iclass 19, count 2 2006.245.07:38:24.03#ibcon#about to read 5, iclass 19, count 2 2006.245.07:38:24.03#ibcon#read 5, iclass 19, count 2 2006.245.07:38:24.03#ibcon#about to read 6, iclass 19, count 2 2006.245.07:38:24.03#ibcon#read 6, iclass 19, count 2 2006.245.07:38:24.03#ibcon#end of sib2, iclass 19, count 2 2006.245.07:38:24.03#ibcon#*mode == 0, iclass 19, count 2 2006.245.07:38:24.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.07:38:24.03#ibcon#[27=AT04-04\r\n] 2006.245.07:38:24.03#ibcon#*before write, iclass 19, count 2 2006.245.07:38:24.03#ibcon#enter sib2, iclass 19, count 2 2006.245.07:38:24.03#ibcon#flushed, iclass 19, count 2 2006.245.07:38:24.03#ibcon#about to write, iclass 19, count 2 2006.245.07:38:24.03#ibcon#wrote, iclass 19, count 2 2006.245.07:38:24.03#ibcon#about to read 3, iclass 19, count 2 2006.245.07:38:24.06#ibcon#read 3, iclass 19, count 2 2006.245.07:38:24.06#ibcon#about to read 4, iclass 19, count 2 2006.245.07:38:24.06#ibcon#read 4, iclass 19, count 2 2006.245.07:38:24.06#ibcon#about to read 5, iclass 19, count 2 2006.245.07:38:24.06#ibcon#read 5, iclass 19, count 2 2006.245.07:38:24.06#ibcon#about to read 6, iclass 19, count 2 2006.245.07:38:24.06#ibcon#read 6, iclass 19, count 2 2006.245.07:38:24.06#ibcon#end of sib2, iclass 19, count 2 2006.245.07:38:24.06#ibcon#*after write, iclass 19, count 2 2006.245.07:38:24.06#ibcon#*before return 0, iclass 19, count 2 2006.245.07:38:24.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:24.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:38:24.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.07:38:24.06#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:24.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:24.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:24.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:24.18#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:38:24.18#ibcon#first serial, iclass 19, count 0 2006.245.07:38:24.18#ibcon#enter sib2, iclass 19, count 0 2006.245.07:38:24.18#ibcon#flushed, iclass 19, count 0 2006.245.07:38:24.18#ibcon#about to write, iclass 19, count 0 2006.245.07:38:24.18#ibcon#wrote, iclass 19, count 0 2006.245.07:38:24.18#ibcon#about to read 3, iclass 19, count 0 2006.245.07:38:24.21#ibcon#read 3, iclass 19, count 0 2006.245.07:38:24.21#ibcon#about to read 4, iclass 19, count 0 2006.245.07:38:24.21#ibcon#read 4, iclass 19, count 0 2006.245.07:38:24.21#ibcon#about to read 5, iclass 19, count 0 2006.245.07:38:24.21#ibcon#read 5, iclass 19, count 0 2006.245.07:38:24.21#ibcon#about to read 6, iclass 19, count 0 2006.245.07:38:24.21#ibcon#read 6, iclass 19, count 0 2006.245.07:38:24.21#ibcon#end of sib2, iclass 19, count 0 2006.245.07:38:24.21#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:38:24.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:38:24.21#ibcon#[27=USB\r\n] 2006.245.07:38:24.21#ibcon#*before write, iclass 19, count 0 2006.245.07:38:24.21#ibcon#enter sib2, iclass 19, count 0 2006.245.07:38:24.21#ibcon#flushed, iclass 19, count 0 2006.245.07:38:24.21#ibcon#about to write, iclass 19, count 0 2006.245.07:38:24.21#ibcon#wrote, iclass 19, count 0 2006.245.07:38:24.21#ibcon#about to read 3, iclass 19, count 0 2006.245.07:38:24.24#ibcon#read 3, iclass 19, count 0 2006.245.07:38:24.24#ibcon#about to read 4, iclass 19, count 0 2006.245.07:38:24.24#ibcon#read 4, iclass 19, count 0 2006.245.07:38:24.24#ibcon#about to read 5, iclass 19, count 0 2006.245.07:38:24.24#ibcon#read 5, iclass 19, count 0 2006.245.07:38:24.24#ibcon#about to read 6, iclass 19, count 0 2006.245.07:38:24.24#ibcon#read 6, iclass 19, count 0 2006.245.07:38:24.24#ibcon#end of sib2, iclass 19, count 0 2006.245.07:38:24.24#ibcon#*after write, iclass 19, count 0 2006.245.07:38:24.24#ibcon#*before return 0, iclass 19, count 0 2006.245.07:38:24.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:24.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:38:24.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:38:24.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:38:24.24$vc4f8/vblo=5,744.99 2006.245.07:38:24.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.07:38:24.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.07:38:24.24#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:24.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:24.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:24.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:24.24#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:38:24.24#ibcon#first serial, iclass 21, count 0 2006.245.07:38:24.24#ibcon#enter sib2, iclass 21, count 0 2006.245.07:38:24.24#ibcon#flushed, iclass 21, count 0 2006.245.07:38:24.24#ibcon#about to write, iclass 21, count 0 2006.245.07:38:24.24#ibcon#wrote, iclass 21, count 0 2006.245.07:38:24.24#ibcon#about to read 3, iclass 21, count 0 2006.245.07:38:24.26#ibcon#read 3, iclass 21, count 0 2006.245.07:38:24.26#ibcon#about to read 4, iclass 21, count 0 2006.245.07:38:24.26#ibcon#read 4, iclass 21, count 0 2006.245.07:38:24.26#ibcon#about to read 5, iclass 21, count 0 2006.245.07:38:24.26#ibcon#read 5, iclass 21, count 0 2006.245.07:38:24.26#ibcon#about to read 6, iclass 21, count 0 2006.245.07:38:24.26#ibcon#read 6, iclass 21, count 0 2006.245.07:38:24.26#ibcon#end of sib2, iclass 21, count 0 2006.245.07:38:24.26#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:38:24.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:38:24.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:38:24.26#ibcon#*before write, iclass 21, count 0 2006.245.07:38:24.26#ibcon#enter sib2, iclass 21, count 0 2006.245.07:38:24.26#ibcon#flushed, iclass 21, count 0 2006.245.07:38:24.26#ibcon#about to write, iclass 21, count 0 2006.245.07:38:24.26#ibcon#wrote, iclass 21, count 0 2006.245.07:38:24.26#ibcon#about to read 3, iclass 21, count 0 2006.245.07:38:24.30#ibcon#read 3, iclass 21, count 0 2006.245.07:38:24.30#ibcon#about to read 4, iclass 21, count 0 2006.245.07:38:24.30#ibcon#read 4, iclass 21, count 0 2006.245.07:38:24.30#ibcon#about to read 5, iclass 21, count 0 2006.245.07:38:24.30#ibcon#read 5, iclass 21, count 0 2006.245.07:38:24.30#ibcon#about to read 6, iclass 21, count 0 2006.245.07:38:24.30#ibcon#read 6, iclass 21, count 0 2006.245.07:38:24.30#ibcon#end of sib2, iclass 21, count 0 2006.245.07:38:24.30#ibcon#*after write, iclass 21, count 0 2006.245.07:38:24.30#ibcon#*before return 0, iclass 21, count 0 2006.245.07:38:24.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:24.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:38:24.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:38:24.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:38:24.30$vc4f8/vb=5,3 2006.245.07:38:24.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.07:38:24.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.07:38:24.30#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:24.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:24.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:24.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:24.36#ibcon#enter wrdev, iclass 23, count 2 2006.245.07:38:24.36#ibcon#first serial, iclass 23, count 2 2006.245.07:38:24.36#ibcon#enter sib2, iclass 23, count 2 2006.245.07:38:24.36#ibcon#flushed, iclass 23, count 2 2006.245.07:38:24.36#ibcon#about to write, iclass 23, count 2 2006.245.07:38:24.36#ibcon#wrote, iclass 23, count 2 2006.245.07:38:24.36#ibcon#about to read 3, iclass 23, count 2 2006.245.07:38:24.38#ibcon#read 3, iclass 23, count 2 2006.245.07:38:24.38#ibcon#about to read 4, iclass 23, count 2 2006.245.07:38:24.38#ibcon#read 4, iclass 23, count 2 2006.245.07:38:24.38#ibcon#about to read 5, iclass 23, count 2 2006.245.07:38:24.38#ibcon#read 5, iclass 23, count 2 2006.245.07:38:24.38#ibcon#about to read 6, iclass 23, count 2 2006.245.07:38:24.38#ibcon#read 6, iclass 23, count 2 2006.245.07:38:24.38#ibcon#end of sib2, iclass 23, count 2 2006.245.07:38:24.38#ibcon#*mode == 0, iclass 23, count 2 2006.245.07:38:24.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.07:38:24.38#ibcon#[27=AT05-03\r\n] 2006.245.07:38:24.38#ibcon#*before write, iclass 23, count 2 2006.245.07:38:24.38#ibcon#enter sib2, iclass 23, count 2 2006.245.07:38:24.38#ibcon#flushed, iclass 23, count 2 2006.245.07:38:24.38#ibcon#about to write, iclass 23, count 2 2006.245.07:38:24.38#ibcon#wrote, iclass 23, count 2 2006.245.07:38:24.38#ibcon#about to read 3, iclass 23, count 2 2006.245.07:38:24.41#ibcon#read 3, iclass 23, count 2 2006.245.07:38:24.41#ibcon#about to read 4, iclass 23, count 2 2006.245.07:38:24.41#ibcon#read 4, iclass 23, count 2 2006.245.07:38:24.41#ibcon#about to read 5, iclass 23, count 2 2006.245.07:38:24.41#ibcon#read 5, iclass 23, count 2 2006.245.07:38:24.41#ibcon#about to read 6, iclass 23, count 2 2006.245.07:38:24.41#ibcon#read 6, iclass 23, count 2 2006.245.07:38:24.41#ibcon#end of sib2, iclass 23, count 2 2006.245.07:38:24.41#ibcon#*after write, iclass 23, count 2 2006.245.07:38:24.41#ibcon#*before return 0, iclass 23, count 2 2006.245.07:38:24.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:24.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:38:24.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.07:38:24.41#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:24.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:24.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:24.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:24.53#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:38:24.53#ibcon#first serial, iclass 23, count 0 2006.245.07:38:24.53#ibcon#enter sib2, iclass 23, count 0 2006.245.07:38:24.53#ibcon#flushed, iclass 23, count 0 2006.245.07:38:24.53#ibcon#about to write, iclass 23, count 0 2006.245.07:38:24.53#ibcon#wrote, iclass 23, count 0 2006.245.07:38:24.53#ibcon#about to read 3, iclass 23, count 0 2006.245.07:38:24.55#ibcon#read 3, iclass 23, count 0 2006.245.07:38:24.55#ibcon#about to read 4, iclass 23, count 0 2006.245.07:38:24.55#ibcon#read 4, iclass 23, count 0 2006.245.07:38:24.55#ibcon#about to read 5, iclass 23, count 0 2006.245.07:38:24.55#ibcon#read 5, iclass 23, count 0 2006.245.07:38:24.55#ibcon#about to read 6, iclass 23, count 0 2006.245.07:38:24.55#ibcon#read 6, iclass 23, count 0 2006.245.07:38:24.55#ibcon#end of sib2, iclass 23, count 0 2006.245.07:38:24.55#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:38:24.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:38:24.55#ibcon#[27=USB\r\n] 2006.245.07:38:24.55#ibcon#*before write, iclass 23, count 0 2006.245.07:38:24.55#ibcon#enter sib2, iclass 23, count 0 2006.245.07:38:24.55#ibcon#flushed, iclass 23, count 0 2006.245.07:38:24.55#ibcon#about to write, iclass 23, count 0 2006.245.07:38:24.55#ibcon#wrote, iclass 23, count 0 2006.245.07:38:24.55#ibcon#about to read 3, iclass 23, count 0 2006.245.07:38:24.58#ibcon#read 3, iclass 23, count 0 2006.245.07:38:24.58#ibcon#about to read 4, iclass 23, count 0 2006.245.07:38:24.58#ibcon#read 4, iclass 23, count 0 2006.245.07:38:24.58#ibcon#about to read 5, iclass 23, count 0 2006.245.07:38:24.58#ibcon#read 5, iclass 23, count 0 2006.245.07:38:24.58#ibcon#about to read 6, iclass 23, count 0 2006.245.07:38:24.58#ibcon#read 6, iclass 23, count 0 2006.245.07:38:24.58#ibcon#end of sib2, iclass 23, count 0 2006.245.07:38:24.58#ibcon#*after write, iclass 23, count 0 2006.245.07:38:24.58#ibcon#*before return 0, iclass 23, count 0 2006.245.07:38:24.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:24.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:38:24.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:38:24.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:38:24.58$vc4f8/vblo=6,752.99 2006.245.07:38:24.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.07:38:24.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.07:38:24.58#ibcon#ireg 17 cls_cnt 0 2006.245.07:38:24.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:24.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:24.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:24.58#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:38:24.58#ibcon#first serial, iclass 25, count 0 2006.245.07:38:24.58#ibcon#enter sib2, iclass 25, count 0 2006.245.07:38:24.58#ibcon#flushed, iclass 25, count 0 2006.245.07:38:24.58#ibcon#about to write, iclass 25, count 0 2006.245.07:38:24.58#ibcon#wrote, iclass 25, count 0 2006.245.07:38:24.58#ibcon#about to read 3, iclass 25, count 0 2006.245.07:38:24.60#ibcon#read 3, iclass 25, count 0 2006.245.07:38:24.60#ibcon#about to read 4, iclass 25, count 0 2006.245.07:38:24.60#ibcon#read 4, iclass 25, count 0 2006.245.07:38:24.60#ibcon#about to read 5, iclass 25, count 0 2006.245.07:38:24.60#ibcon#read 5, iclass 25, count 0 2006.245.07:38:24.60#ibcon#about to read 6, iclass 25, count 0 2006.245.07:38:24.60#ibcon#read 6, iclass 25, count 0 2006.245.07:38:24.60#ibcon#end of sib2, iclass 25, count 0 2006.245.07:38:24.60#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:38:24.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:38:24.60#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:38:24.60#ibcon#*before write, iclass 25, count 0 2006.245.07:38:24.60#ibcon#enter sib2, iclass 25, count 0 2006.245.07:38:24.60#ibcon#flushed, iclass 25, count 0 2006.245.07:38:24.60#ibcon#about to write, iclass 25, count 0 2006.245.07:38:24.60#ibcon#wrote, iclass 25, count 0 2006.245.07:38:24.60#ibcon#about to read 3, iclass 25, count 0 2006.245.07:38:24.64#ibcon#read 3, iclass 25, count 0 2006.245.07:38:24.64#ibcon#about to read 4, iclass 25, count 0 2006.245.07:38:24.64#ibcon#read 4, iclass 25, count 0 2006.245.07:38:24.64#ibcon#about to read 5, iclass 25, count 0 2006.245.07:38:24.64#ibcon#read 5, iclass 25, count 0 2006.245.07:38:24.64#ibcon#about to read 6, iclass 25, count 0 2006.245.07:38:24.64#ibcon#read 6, iclass 25, count 0 2006.245.07:38:24.64#ibcon#end of sib2, iclass 25, count 0 2006.245.07:38:24.64#ibcon#*after write, iclass 25, count 0 2006.245.07:38:24.64#ibcon#*before return 0, iclass 25, count 0 2006.245.07:38:24.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:24.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:38:24.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:38:24.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:38:24.64$vc4f8/vb=6,3 2006.245.07:38:24.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.07:38:24.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.07:38:24.64#ibcon#ireg 11 cls_cnt 2 2006.245.07:38:24.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:24.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:24.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:24.70#ibcon#enter wrdev, iclass 27, count 2 2006.245.07:38:24.70#ibcon#first serial, iclass 27, count 2 2006.245.07:38:24.70#ibcon#enter sib2, iclass 27, count 2 2006.245.07:38:24.70#ibcon#flushed, iclass 27, count 2 2006.245.07:38:24.70#ibcon#about to write, iclass 27, count 2 2006.245.07:38:24.70#ibcon#wrote, iclass 27, count 2 2006.245.07:38:24.70#ibcon#about to read 3, iclass 27, count 2 2006.245.07:38:24.72#ibcon#read 3, iclass 27, count 2 2006.245.07:38:24.72#ibcon#about to read 4, iclass 27, count 2 2006.245.07:38:24.72#ibcon#read 4, iclass 27, count 2 2006.245.07:38:24.72#ibcon#about to read 5, iclass 27, count 2 2006.245.07:38:24.72#ibcon#read 5, iclass 27, count 2 2006.245.07:38:24.72#ibcon#about to read 6, iclass 27, count 2 2006.245.07:38:24.72#ibcon#read 6, iclass 27, count 2 2006.245.07:38:24.72#ibcon#end of sib2, iclass 27, count 2 2006.245.07:38:24.72#ibcon#*mode == 0, iclass 27, count 2 2006.245.07:38:24.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.07:38:24.72#ibcon#[27=AT06-03\r\n] 2006.245.07:38:24.72#ibcon#*before write, iclass 27, count 2 2006.245.07:38:24.72#ibcon#enter sib2, iclass 27, count 2 2006.245.07:38:24.72#ibcon#flushed, iclass 27, count 2 2006.245.07:38:24.72#ibcon#about to write, iclass 27, count 2 2006.245.07:38:24.72#ibcon#wrote, iclass 27, count 2 2006.245.07:38:24.72#ibcon#about to read 3, iclass 27, count 2 2006.245.07:38:24.75#ibcon#read 3, iclass 27, count 2 2006.245.07:38:24.75#ibcon#about to read 4, iclass 27, count 2 2006.245.07:38:24.75#ibcon#read 4, iclass 27, count 2 2006.245.07:38:24.75#ibcon#about to read 5, iclass 27, count 2 2006.245.07:38:24.75#ibcon#read 5, iclass 27, count 2 2006.245.07:38:24.75#ibcon#about to read 6, iclass 27, count 2 2006.245.07:38:24.75#ibcon#read 6, iclass 27, count 2 2006.245.07:38:24.75#ibcon#end of sib2, iclass 27, count 2 2006.245.07:38:24.75#ibcon#*after write, iclass 27, count 2 2006.245.07:38:24.75#ibcon#*before return 0, iclass 27, count 2 2006.245.07:38:24.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:24.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:38:24.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.07:38:24.75#ibcon#ireg 7 cls_cnt 0 2006.245.07:38:24.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:24.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:24.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:24.87#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:38:24.87#ibcon#first serial, iclass 27, count 0 2006.245.07:38:24.87#ibcon#enter sib2, iclass 27, count 0 2006.245.07:38:24.87#ibcon#flushed, iclass 27, count 0 2006.245.07:38:24.87#ibcon#about to write, iclass 27, count 0 2006.245.07:38:24.87#ibcon#wrote, iclass 27, count 0 2006.245.07:38:24.87#ibcon#about to read 3, iclass 27, count 0 2006.245.07:38:24.89#ibcon#read 3, iclass 27, count 0 2006.245.07:38:24.89#ibcon#about to read 4, iclass 27, count 0 2006.245.07:38:24.89#ibcon#read 4, iclass 27, count 0 2006.245.07:38:24.89#ibcon#about to read 5, iclass 27, count 0 2006.245.07:38:24.89#ibcon#read 5, iclass 27, count 0 2006.245.07:38:24.89#ibcon#about to read 6, iclass 27, count 0 2006.245.07:38:24.89#ibcon#read 6, iclass 27, count 0 2006.245.07:38:24.89#ibcon#end of sib2, iclass 27, count 0 2006.245.07:38:24.89#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:38:24.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:38:24.89#ibcon#[27=USB\r\n] 2006.245.07:38:24.89#ibcon#*before write, iclass 27, count 0 2006.245.07:38:24.89#ibcon#enter sib2, iclass 27, count 0 2006.245.07:38:24.89#ibcon#flushed, iclass 27, count 0 2006.245.07:38:24.89#ibcon#about to write, iclass 27, count 0 2006.245.07:38:24.89#ibcon#wrote, iclass 27, count 0 2006.245.07:38:24.89#ibcon#about to read 3, iclass 27, count 0 2006.245.07:38:24.92#ibcon#read 3, iclass 27, count 0 2006.245.07:38:24.92#ibcon#about to read 4, iclass 27, count 0 2006.245.07:38:24.92#ibcon#read 4, iclass 27, count 0 2006.245.07:38:24.92#ibcon#about to read 5, iclass 27, count 0 2006.245.07:38:24.92#ibcon#read 5, iclass 27, count 0 2006.245.07:38:24.92#ibcon#about to read 6, iclass 27, count 0 2006.245.07:38:24.92#ibcon#read 6, iclass 27, count 0 2006.245.07:38:24.92#ibcon#end of sib2, iclass 27, count 0 2006.245.07:38:24.92#ibcon#*after write, iclass 27, count 0 2006.245.07:38:24.92#ibcon#*before return 0, iclass 27, count 0 2006.245.07:38:24.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:24.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:38:24.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:38:24.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:38:24.92$vc4f8/vabw=wide 2006.245.07:38:24.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.07:38:24.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.07:38:24.92#ibcon#ireg 8 cls_cnt 0 2006.245.07:38:24.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:24.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:24.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:24.92#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:38:24.92#ibcon#first serial, iclass 29, count 0 2006.245.07:38:24.92#ibcon#enter sib2, iclass 29, count 0 2006.245.07:38:24.92#ibcon#flushed, iclass 29, count 0 2006.245.07:38:24.92#ibcon#about to write, iclass 29, count 0 2006.245.07:38:24.92#ibcon#wrote, iclass 29, count 0 2006.245.07:38:24.92#ibcon#about to read 3, iclass 29, count 0 2006.245.07:38:24.94#ibcon#read 3, iclass 29, count 0 2006.245.07:38:24.94#ibcon#about to read 4, iclass 29, count 0 2006.245.07:38:24.94#ibcon#read 4, iclass 29, count 0 2006.245.07:38:24.94#ibcon#about to read 5, iclass 29, count 0 2006.245.07:38:24.94#ibcon#read 5, iclass 29, count 0 2006.245.07:38:24.94#ibcon#about to read 6, iclass 29, count 0 2006.245.07:38:24.94#ibcon#read 6, iclass 29, count 0 2006.245.07:38:24.94#ibcon#end of sib2, iclass 29, count 0 2006.245.07:38:24.94#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:38:24.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:38:24.94#ibcon#[25=BW32\r\n] 2006.245.07:38:24.94#ibcon#*before write, iclass 29, count 0 2006.245.07:38:24.94#ibcon#enter sib2, iclass 29, count 0 2006.245.07:38:24.94#ibcon#flushed, iclass 29, count 0 2006.245.07:38:24.94#ibcon#about to write, iclass 29, count 0 2006.245.07:38:24.94#ibcon#wrote, iclass 29, count 0 2006.245.07:38:24.94#ibcon#about to read 3, iclass 29, count 0 2006.245.07:38:24.97#ibcon#read 3, iclass 29, count 0 2006.245.07:38:24.97#ibcon#about to read 4, iclass 29, count 0 2006.245.07:38:24.97#ibcon#read 4, iclass 29, count 0 2006.245.07:38:24.97#ibcon#about to read 5, iclass 29, count 0 2006.245.07:38:24.97#ibcon#read 5, iclass 29, count 0 2006.245.07:38:24.97#ibcon#about to read 6, iclass 29, count 0 2006.245.07:38:24.97#ibcon#read 6, iclass 29, count 0 2006.245.07:38:24.97#ibcon#end of sib2, iclass 29, count 0 2006.245.07:38:24.97#ibcon#*after write, iclass 29, count 0 2006.245.07:38:24.97#ibcon#*before return 0, iclass 29, count 0 2006.245.07:38:24.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:24.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:38:24.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:38:24.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:38:24.97$vc4f8/vbbw=wide 2006.245.07:38:24.97#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:38:24.97#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:38:24.97#ibcon#ireg 8 cls_cnt 0 2006.245.07:38:24.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:38:25.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:38:25.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:38:25.04#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:38:25.04#ibcon#first serial, iclass 31, count 0 2006.245.07:38:25.04#ibcon#enter sib2, iclass 31, count 0 2006.245.07:38:25.04#ibcon#flushed, iclass 31, count 0 2006.245.07:38:25.04#ibcon#about to write, iclass 31, count 0 2006.245.07:38:25.04#ibcon#wrote, iclass 31, count 0 2006.245.07:38:25.04#ibcon#about to read 3, iclass 31, count 0 2006.245.07:38:25.06#ibcon#read 3, iclass 31, count 0 2006.245.07:38:25.06#ibcon#about to read 4, iclass 31, count 0 2006.245.07:38:25.06#ibcon#read 4, iclass 31, count 0 2006.245.07:38:25.06#ibcon#about to read 5, iclass 31, count 0 2006.245.07:38:25.06#ibcon#read 5, iclass 31, count 0 2006.245.07:38:25.06#ibcon#about to read 6, iclass 31, count 0 2006.245.07:38:25.06#ibcon#read 6, iclass 31, count 0 2006.245.07:38:25.06#ibcon#end of sib2, iclass 31, count 0 2006.245.07:38:25.06#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:38:25.06#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:38:25.06#ibcon#[27=BW32\r\n] 2006.245.07:38:25.06#ibcon#*before write, iclass 31, count 0 2006.245.07:38:25.06#ibcon#enter sib2, iclass 31, count 0 2006.245.07:38:25.06#ibcon#flushed, iclass 31, count 0 2006.245.07:38:25.06#ibcon#about to write, iclass 31, count 0 2006.245.07:38:25.06#ibcon#wrote, iclass 31, count 0 2006.245.07:38:25.06#ibcon#about to read 3, iclass 31, count 0 2006.245.07:38:25.09#ibcon#read 3, iclass 31, count 0 2006.245.07:38:25.09#ibcon#about to read 4, iclass 31, count 0 2006.245.07:38:25.09#ibcon#read 4, iclass 31, count 0 2006.245.07:38:25.09#ibcon#about to read 5, iclass 31, count 0 2006.245.07:38:25.09#ibcon#read 5, iclass 31, count 0 2006.245.07:38:25.09#ibcon#about to read 6, iclass 31, count 0 2006.245.07:38:25.09#ibcon#read 6, iclass 31, count 0 2006.245.07:38:25.09#ibcon#end of sib2, iclass 31, count 0 2006.245.07:38:25.09#ibcon#*after write, iclass 31, count 0 2006.245.07:38:25.09#ibcon#*before return 0, iclass 31, count 0 2006.245.07:38:25.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:38:25.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:38:25.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:38:25.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:38:25.09$4f8m12a/ifd4f 2006.245.07:38:25.09$ifd4f/lo= 2006.245.07:38:25.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:38:25.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:38:25.09$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:38:25.09$ifd4f/patch= 2006.245.07:38:25.09$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:38:25.09$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:38:25.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:38:25.09$4f8m12a/"form=m,16.000,1:2 2006.245.07:38:25.09$4f8m12a/"tpicd 2006.245.07:38:25.09$4f8m12a/echo=off 2006.245.07:38:25.09$4f8m12a/xlog=off 2006.245.07:38:25.09:!2006.245.07:38:50 2006.245.07:38:33.13#trakl#Source acquired 2006.245.07:38:35.13#flagr#flagr/antenna,acquired 2006.245.07:38:50.00:preob 2006.245.07:38:51.13/onsource/TRACKING 2006.245.07:38:51.13:!2006.245.07:39:00 2006.245.07:39:00.00:data_valid=on 2006.245.07:39:00.00:midob 2006.245.07:39:00.13/onsource/TRACKING 2006.245.07:39:00.13/wx/27.57,1004.4,66 2006.245.07:39:00.29/cable/+6.4121E-03 2006.245.07:39:01.38/va/01,08,usb,yes,31,32 2006.245.07:39:01.38/va/02,07,usb,yes,30,32 2006.245.07:39:01.38/va/03,06,usb,yes,32,33 2006.245.07:39:01.38/va/04,07,usb,yes,31,34 2006.245.07:39:01.38/va/05,07,usb,yes,32,34 2006.245.07:39:01.38/va/06,07,usb,yes,28,28 2006.245.07:39:01.38/va/07,07,usb,yes,28,28 2006.245.07:39:01.38/va/08,08,usb,yes,25,24 2006.245.07:39:01.61/valo/01,532.99,yes,locked 2006.245.07:39:01.61/valo/02,572.99,yes,locked 2006.245.07:39:01.61/valo/03,672.99,yes,locked 2006.245.07:39:01.61/valo/04,832.99,yes,locked 2006.245.07:39:01.61/valo/05,652.99,yes,locked 2006.245.07:39:01.61/valo/06,772.99,yes,locked 2006.245.07:39:01.61/valo/07,832.99,yes,locked 2006.245.07:39:01.61/valo/08,852.99,yes,locked 2006.245.07:39:02.70/vb/01,04,usb,yes,30,29 2006.245.07:39:02.70/vb/02,04,usb,yes,32,33 2006.245.07:39:02.70/vb/03,04,usb,yes,28,32 2006.245.07:39:02.70/vb/04,04,usb,yes,29,29 2006.245.07:39:02.70/vb/05,03,usb,yes,34,39 2006.245.07:39:02.70/vb/06,03,usb,yes,35,39 2006.245.07:39:02.70/vb/07,04,usb,yes,31,31 2006.245.07:39:02.70/vb/08,03,usb,yes,35,39 2006.245.07:39:02.94/vblo/01,632.99,yes,locked 2006.245.07:39:02.94/vblo/02,640.99,yes,locked 2006.245.07:39:02.94/vblo/03,656.99,yes,locked 2006.245.07:39:02.94/vblo/04,712.99,yes,locked 2006.245.07:39:02.94/vblo/05,744.99,yes,locked 2006.245.07:39:02.94/vblo/06,752.99,yes,locked 2006.245.07:39:02.94/vblo/07,734.99,yes,locked 2006.245.07:39:02.94/vblo/08,744.99,yes,locked 2006.245.07:39:03.09/vabw/8 2006.245.07:39:03.24/vbbw/8 2006.245.07:39:03.33/xfe/off,on,13.2 2006.245.07:39:03.73/ifatt/23,28,28,28 2006.245.07:39:04.08/fmout-gps/S +4.44E-07 2006.245.07:39:04.12:!2006.245.07:40:00 2006.245.07:40:00.00:data_valid=off 2006.245.07:40:00.00:postob 2006.245.07:40:00.06/cable/+6.4118E-03 2006.245.07:40:00.06/wx/27.54,1004.4,66 2006.245.07:40:01.08/fmout-gps/S +4.45E-07 2006.245.07:40:01.08:scan_name=245-0741,k06245,60 2006.245.07:40:01.09:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.245.07:40:01.13#flagr#flagr/antenna,new-source 2006.245.07:40:02.13:checkk5 2006.245.07:40:02.55/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:40:03.26/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:40:03.93/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:40:04.35/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:40:04.87/chk_obsdata//k5ts1/T2450739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:40:05.29/chk_obsdata//k5ts2/T2450739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:40:05.74/chk_obsdata//k5ts3/T2450739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:40:06.18/chk_obsdata//k5ts4/T2450739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:40:06.99/k5log//k5ts1_log_newline 2006.245.07:40:07.84/k5log//k5ts2_log_newline 2006.245.07:40:08.65/k5log//k5ts3_log_newline 2006.245.07:40:09.53/k5log//k5ts4_log_newline 2006.245.07:40:09.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:40:09.55:4f8m12a=1 2006.245.07:40:09.55$4f8m12a/echo=on 2006.245.07:40:09.55$4f8m12a/pcalon 2006.245.07:40:09.55$pcalon/"no phase cal control is implemented here 2006.245.07:40:09.55$4f8m12a/"tpicd=stop 2006.245.07:40:09.55$4f8m12a/vc4f8 2006.245.07:40:09.55$vc4f8/valo=1,532.99 2006.245.07:40:09.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:40:09.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:40:09.55#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:09.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:09.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:09.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:09.55#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:40:09.55#ibcon#first serial, iclass 38, count 0 2006.245.07:40:09.55#ibcon#enter sib2, iclass 38, count 0 2006.245.07:40:09.55#ibcon#flushed, iclass 38, count 0 2006.245.07:40:09.55#ibcon#about to write, iclass 38, count 0 2006.245.07:40:09.55#ibcon#wrote, iclass 38, count 0 2006.245.07:40:09.55#ibcon#about to read 3, iclass 38, count 0 2006.245.07:40:09.57#ibcon#read 3, iclass 38, count 0 2006.245.07:40:09.57#ibcon#about to read 4, iclass 38, count 0 2006.245.07:40:09.57#ibcon#read 4, iclass 38, count 0 2006.245.07:40:09.57#ibcon#about to read 5, iclass 38, count 0 2006.245.07:40:09.57#ibcon#read 5, iclass 38, count 0 2006.245.07:40:09.57#ibcon#about to read 6, iclass 38, count 0 2006.245.07:40:09.57#ibcon#read 6, iclass 38, count 0 2006.245.07:40:09.57#ibcon#end of sib2, iclass 38, count 0 2006.245.07:40:09.57#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:40:09.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:40:09.57#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:40:09.57#ibcon#*before write, iclass 38, count 0 2006.245.07:40:09.57#ibcon#enter sib2, iclass 38, count 0 2006.245.07:40:09.57#ibcon#flushed, iclass 38, count 0 2006.245.07:40:09.57#ibcon#about to write, iclass 38, count 0 2006.245.07:40:09.57#ibcon#wrote, iclass 38, count 0 2006.245.07:40:09.57#ibcon#about to read 3, iclass 38, count 0 2006.245.07:40:09.62#ibcon#read 3, iclass 38, count 0 2006.245.07:40:09.62#ibcon#about to read 4, iclass 38, count 0 2006.245.07:40:09.62#ibcon#read 4, iclass 38, count 0 2006.245.07:40:09.62#ibcon#about to read 5, iclass 38, count 0 2006.245.07:40:09.62#ibcon#read 5, iclass 38, count 0 2006.245.07:40:09.62#ibcon#about to read 6, iclass 38, count 0 2006.245.07:40:09.62#ibcon#read 6, iclass 38, count 0 2006.245.07:40:09.62#ibcon#end of sib2, iclass 38, count 0 2006.245.07:40:09.62#ibcon#*after write, iclass 38, count 0 2006.245.07:40:09.62#ibcon#*before return 0, iclass 38, count 0 2006.245.07:40:09.62#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:09.62#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:09.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:40:09.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:40:09.62$vc4f8/va=1,8 2006.245.07:40:09.62#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:40:09.62#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:40:09.62#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:09.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:09.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:09.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:09.62#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:40:09.62#ibcon#first serial, iclass 40, count 2 2006.245.07:40:09.62#ibcon#enter sib2, iclass 40, count 2 2006.245.07:40:09.62#ibcon#flushed, iclass 40, count 2 2006.245.07:40:09.62#ibcon#about to write, iclass 40, count 2 2006.245.07:40:09.62#ibcon#wrote, iclass 40, count 2 2006.245.07:40:09.62#ibcon#about to read 3, iclass 40, count 2 2006.245.07:40:09.64#ibcon#read 3, iclass 40, count 2 2006.245.07:40:09.64#ibcon#about to read 4, iclass 40, count 2 2006.245.07:40:09.64#ibcon#read 4, iclass 40, count 2 2006.245.07:40:09.64#ibcon#about to read 5, iclass 40, count 2 2006.245.07:40:09.64#ibcon#read 5, iclass 40, count 2 2006.245.07:40:09.64#ibcon#about to read 6, iclass 40, count 2 2006.245.07:40:09.64#ibcon#read 6, iclass 40, count 2 2006.245.07:40:09.64#ibcon#end of sib2, iclass 40, count 2 2006.245.07:40:09.64#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:40:09.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:40:09.64#ibcon#[25=AT01-08\r\n] 2006.245.07:40:09.64#ibcon#*before write, iclass 40, count 2 2006.245.07:40:09.64#ibcon#enter sib2, iclass 40, count 2 2006.245.07:40:09.64#ibcon#flushed, iclass 40, count 2 2006.245.07:40:09.64#ibcon#about to write, iclass 40, count 2 2006.245.07:40:09.64#ibcon#wrote, iclass 40, count 2 2006.245.07:40:09.64#ibcon#about to read 3, iclass 40, count 2 2006.245.07:40:09.67#ibcon#read 3, iclass 40, count 2 2006.245.07:40:09.67#ibcon#about to read 4, iclass 40, count 2 2006.245.07:40:09.67#ibcon#read 4, iclass 40, count 2 2006.245.07:40:09.67#ibcon#about to read 5, iclass 40, count 2 2006.245.07:40:09.67#ibcon#read 5, iclass 40, count 2 2006.245.07:40:09.67#ibcon#about to read 6, iclass 40, count 2 2006.245.07:40:09.67#ibcon#read 6, iclass 40, count 2 2006.245.07:40:09.67#ibcon#end of sib2, iclass 40, count 2 2006.245.07:40:09.67#ibcon#*after write, iclass 40, count 2 2006.245.07:40:09.67#ibcon#*before return 0, iclass 40, count 2 2006.245.07:40:09.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:09.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:09.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:40:09.67#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:09.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:09.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:09.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:09.79#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:40:09.79#ibcon#first serial, iclass 40, count 0 2006.245.07:40:09.79#ibcon#enter sib2, iclass 40, count 0 2006.245.07:40:09.79#ibcon#flushed, iclass 40, count 0 2006.245.07:40:09.79#ibcon#about to write, iclass 40, count 0 2006.245.07:40:09.79#ibcon#wrote, iclass 40, count 0 2006.245.07:40:09.79#ibcon#about to read 3, iclass 40, count 0 2006.245.07:40:09.81#ibcon#read 3, iclass 40, count 0 2006.245.07:40:09.81#ibcon#about to read 4, iclass 40, count 0 2006.245.07:40:09.81#ibcon#read 4, iclass 40, count 0 2006.245.07:40:09.81#ibcon#about to read 5, iclass 40, count 0 2006.245.07:40:09.81#ibcon#read 5, iclass 40, count 0 2006.245.07:40:09.81#ibcon#about to read 6, iclass 40, count 0 2006.245.07:40:09.81#ibcon#read 6, iclass 40, count 0 2006.245.07:40:09.81#ibcon#end of sib2, iclass 40, count 0 2006.245.07:40:09.81#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:40:09.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:40:09.81#ibcon#[25=USB\r\n] 2006.245.07:40:09.81#ibcon#*before write, iclass 40, count 0 2006.245.07:40:09.81#ibcon#enter sib2, iclass 40, count 0 2006.245.07:40:09.81#ibcon#flushed, iclass 40, count 0 2006.245.07:40:09.81#ibcon#about to write, iclass 40, count 0 2006.245.07:40:09.81#ibcon#wrote, iclass 40, count 0 2006.245.07:40:09.81#ibcon#about to read 3, iclass 40, count 0 2006.245.07:40:09.84#ibcon#read 3, iclass 40, count 0 2006.245.07:40:09.84#ibcon#about to read 4, iclass 40, count 0 2006.245.07:40:09.84#ibcon#read 4, iclass 40, count 0 2006.245.07:40:09.84#ibcon#about to read 5, iclass 40, count 0 2006.245.07:40:09.84#ibcon#read 5, iclass 40, count 0 2006.245.07:40:09.84#ibcon#about to read 6, iclass 40, count 0 2006.245.07:40:09.84#ibcon#read 6, iclass 40, count 0 2006.245.07:40:09.84#ibcon#end of sib2, iclass 40, count 0 2006.245.07:40:09.84#ibcon#*after write, iclass 40, count 0 2006.245.07:40:09.84#ibcon#*before return 0, iclass 40, count 0 2006.245.07:40:09.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:09.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:09.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:40:09.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:40:09.84$vc4f8/valo=2,572.99 2006.245.07:40:09.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:40:09.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:40:09.84#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:09.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:09.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:09.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:09.84#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:40:09.84#ibcon#first serial, iclass 4, count 0 2006.245.07:40:09.84#ibcon#enter sib2, iclass 4, count 0 2006.245.07:40:09.84#ibcon#flushed, iclass 4, count 0 2006.245.07:40:09.84#ibcon#about to write, iclass 4, count 0 2006.245.07:40:09.84#ibcon#wrote, iclass 4, count 0 2006.245.07:40:09.84#ibcon#about to read 3, iclass 4, count 0 2006.245.07:40:09.86#ibcon#read 3, iclass 4, count 0 2006.245.07:40:09.86#ibcon#about to read 4, iclass 4, count 0 2006.245.07:40:09.86#ibcon#read 4, iclass 4, count 0 2006.245.07:40:09.86#ibcon#about to read 5, iclass 4, count 0 2006.245.07:40:09.86#ibcon#read 5, iclass 4, count 0 2006.245.07:40:09.86#ibcon#about to read 6, iclass 4, count 0 2006.245.07:40:09.86#ibcon#read 6, iclass 4, count 0 2006.245.07:40:09.86#ibcon#end of sib2, iclass 4, count 0 2006.245.07:40:09.86#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:40:09.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:40:09.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:40:09.86#ibcon#*before write, iclass 4, count 0 2006.245.07:40:09.86#ibcon#enter sib2, iclass 4, count 0 2006.245.07:40:09.86#ibcon#flushed, iclass 4, count 0 2006.245.07:40:09.86#ibcon#about to write, iclass 4, count 0 2006.245.07:40:09.86#ibcon#wrote, iclass 4, count 0 2006.245.07:40:09.86#ibcon#about to read 3, iclass 4, count 0 2006.245.07:40:09.91#ibcon#read 3, iclass 4, count 0 2006.245.07:40:09.91#ibcon#about to read 4, iclass 4, count 0 2006.245.07:40:09.91#ibcon#read 4, iclass 4, count 0 2006.245.07:40:09.91#ibcon#about to read 5, iclass 4, count 0 2006.245.07:40:09.91#ibcon#read 5, iclass 4, count 0 2006.245.07:40:09.91#ibcon#about to read 6, iclass 4, count 0 2006.245.07:40:09.91#ibcon#read 6, iclass 4, count 0 2006.245.07:40:09.91#ibcon#end of sib2, iclass 4, count 0 2006.245.07:40:09.91#ibcon#*after write, iclass 4, count 0 2006.245.07:40:09.91#ibcon#*before return 0, iclass 4, count 0 2006.245.07:40:09.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:09.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:09.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:40:09.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:40:09.91$vc4f8/va=2,7 2006.245.07:40:09.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:40:09.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:40:09.91#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:09.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:40:09.91#abcon#<5=/05 3.2 5.6 27.54 661004.4\r\n> 2006.245.07:40:09.93#abcon#{5=INTERFACE CLEAR} 2006.245.07:40:09.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:40:09.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:40:09.96#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:40:09.96#ibcon#first serial, iclass 7, count 2 2006.245.07:40:09.96#ibcon#enter sib2, iclass 7, count 2 2006.245.07:40:09.96#ibcon#flushed, iclass 7, count 2 2006.245.07:40:09.96#ibcon#about to write, iclass 7, count 2 2006.245.07:40:09.96#ibcon#wrote, iclass 7, count 2 2006.245.07:40:09.96#ibcon#about to read 3, iclass 7, count 2 2006.245.07:40:09.98#ibcon#read 3, iclass 7, count 2 2006.245.07:40:09.98#ibcon#about to read 4, iclass 7, count 2 2006.245.07:40:09.98#ibcon#read 4, iclass 7, count 2 2006.245.07:40:09.98#ibcon#about to read 5, iclass 7, count 2 2006.245.07:40:09.98#ibcon#read 5, iclass 7, count 2 2006.245.07:40:09.98#ibcon#about to read 6, iclass 7, count 2 2006.245.07:40:09.98#ibcon#read 6, iclass 7, count 2 2006.245.07:40:09.98#ibcon#end of sib2, iclass 7, count 2 2006.245.07:40:09.98#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:40:09.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:40:09.98#ibcon#[25=AT02-07\r\n] 2006.245.07:40:09.98#ibcon#*before write, iclass 7, count 2 2006.245.07:40:09.98#ibcon#enter sib2, iclass 7, count 2 2006.245.07:40:09.98#ibcon#flushed, iclass 7, count 2 2006.245.07:40:09.98#ibcon#about to write, iclass 7, count 2 2006.245.07:40:09.98#ibcon#wrote, iclass 7, count 2 2006.245.07:40:09.98#ibcon#about to read 3, iclass 7, count 2 2006.245.07:40:09.99#abcon#[5=S1D000X0/0*\r\n] 2006.245.07:40:10.01#ibcon#read 3, iclass 7, count 2 2006.245.07:40:10.01#ibcon#about to read 4, iclass 7, count 2 2006.245.07:40:10.01#ibcon#read 4, iclass 7, count 2 2006.245.07:40:10.01#ibcon#about to read 5, iclass 7, count 2 2006.245.07:40:10.01#ibcon#read 5, iclass 7, count 2 2006.245.07:40:10.01#ibcon#about to read 6, iclass 7, count 2 2006.245.07:40:10.01#ibcon#read 6, iclass 7, count 2 2006.245.07:40:10.01#ibcon#end of sib2, iclass 7, count 2 2006.245.07:40:10.01#ibcon#*after write, iclass 7, count 2 2006.245.07:40:10.01#ibcon#*before return 0, iclass 7, count 2 2006.245.07:40:10.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:40:10.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:40:10.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:40:10.01#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:10.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:40:10.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:40:10.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:40:10.13#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:40:10.13#ibcon#first serial, iclass 7, count 0 2006.245.07:40:10.13#ibcon#enter sib2, iclass 7, count 0 2006.245.07:40:10.13#ibcon#flushed, iclass 7, count 0 2006.245.07:40:10.13#ibcon#about to write, iclass 7, count 0 2006.245.07:40:10.13#ibcon#wrote, iclass 7, count 0 2006.245.07:40:10.13#ibcon#about to read 3, iclass 7, count 0 2006.245.07:40:10.15#ibcon#read 3, iclass 7, count 0 2006.245.07:40:10.15#ibcon#about to read 4, iclass 7, count 0 2006.245.07:40:10.15#ibcon#read 4, iclass 7, count 0 2006.245.07:40:10.15#ibcon#about to read 5, iclass 7, count 0 2006.245.07:40:10.15#ibcon#read 5, iclass 7, count 0 2006.245.07:40:10.15#ibcon#about to read 6, iclass 7, count 0 2006.245.07:40:10.15#ibcon#read 6, iclass 7, count 0 2006.245.07:40:10.15#ibcon#end of sib2, iclass 7, count 0 2006.245.07:40:10.15#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:40:10.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:40:10.15#ibcon#[25=USB\r\n] 2006.245.07:40:10.15#ibcon#*before write, iclass 7, count 0 2006.245.07:40:10.15#ibcon#enter sib2, iclass 7, count 0 2006.245.07:40:10.15#ibcon#flushed, iclass 7, count 0 2006.245.07:40:10.15#ibcon#about to write, iclass 7, count 0 2006.245.07:40:10.15#ibcon#wrote, iclass 7, count 0 2006.245.07:40:10.15#ibcon#about to read 3, iclass 7, count 0 2006.245.07:40:10.18#ibcon#read 3, iclass 7, count 0 2006.245.07:40:10.18#ibcon#about to read 4, iclass 7, count 0 2006.245.07:40:10.18#ibcon#read 4, iclass 7, count 0 2006.245.07:40:10.18#ibcon#about to read 5, iclass 7, count 0 2006.245.07:40:10.18#ibcon#read 5, iclass 7, count 0 2006.245.07:40:10.18#ibcon#about to read 6, iclass 7, count 0 2006.245.07:40:10.18#ibcon#read 6, iclass 7, count 0 2006.245.07:40:10.18#ibcon#end of sib2, iclass 7, count 0 2006.245.07:40:10.18#ibcon#*after write, iclass 7, count 0 2006.245.07:40:10.18#ibcon#*before return 0, iclass 7, count 0 2006.245.07:40:10.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:40:10.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:40:10.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:40:10.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:40:10.18$vc4f8/valo=3,672.99 2006.245.07:40:10.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:40:10.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:40:10.18#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:10.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:10.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:10.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:10.18#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:40:10.18#ibcon#first serial, iclass 14, count 0 2006.245.07:40:10.18#ibcon#enter sib2, iclass 14, count 0 2006.245.07:40:10.18#ibcon#flushed, iclass 14, count 0 2006.245.07:40:10.18#ibcon#about to write, iclass 14, count 0 2006.245.07:40:10.18#ibcon#wrote, iclass 14, count 0 2006.245.07:40:10.18#ibcon#about to read 3, iclass 14, count 0 2006.245.07:40:10.20#ibcon#read 3, iclass 14, count 0 2006.245.07:40:10.20#ibcon#about to read 4, iclass 14, count 0 2006.245.07:40:10.20#ibcon#read 4, iclass 14, count 0 2006.245.07:40:10.20#ibcon#about to read 5, iclass 14, count 0 2006.245.07:40:10.20#ibcon#read 5, iclass 14, count 0 2006.245.07:40:10.20#ibcon#about to read 6, iclass 14, count 0 2006.245.07:40:10.20#ibcon#read 6, iclass 14, count 0 2006.245.07:40:10.20#ibcon#end of sib2, iclass 14, count 0 2006.245.07:40:10.20#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:40:10.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:40:10.20#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:40:10.20#ibcon#*before write, iclass 14, count 0 2006.245.07:40:10.20#ibcon#enter sib2, iclass 14, count 0 2006.245.07:40:10.20#ibcon#flushed, iclass 14, count 0 2006.245.07:40:10.20#ibcon#about to write, iclass 14, count 0 2006.245.07:40:10.20#ibcon#wrote, iclass 14, count 0 2006.245.07:40:10.20#ibcon#about to read 3, iclass 14, count 0 2006.245.07:40:10.25#ibcon#read 3, iclass 14, count 0 2006.245.07:40:10.25#ibcon#about to read 4, iclass 14, count 0 2006.245.07:40:10.25#ibcon#read 4, iclass 14, count 0 2006.245.07:40:10.25#ibcon#about to read 5, iclass 14, count 0 2006.245.07:40:10.25#ibcon#read 5, iclass 14, count 0 2006.245.07:40:10.25#ibcon#about to read 6, iclass 14, count 0 2006.245.07:40:10.25#ibcon#read 6, iclass 14, count 0 2006.245.07:40:10.25#ibcon#end of sib2, iclass 14, count 0 2006.245.07:40:10.25#ibcon#*after write, iclass 14, count 0 2006.245.07:40:10.25#ibcon#*before return 0, iclass 14, count 0 2006.245.07:40:10.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:10.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:10.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:40:10.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:40:10.25$vc4f8/va=3,6 2006.245.07:40:10.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.07:40:10.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.07:40:10.25#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:10.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:10.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:10.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:10.30#ibcon#enter wrdev, iclass 16, count 2 2006.245.07:40:10.30#ibcon#first serial, iclass 16, count 2 2006.245.07:40:10.30#ibcon#enter sib2, iclass 16, count 2 2006.245.07:40:10.30#ibcon#flushed, iclass 16, count 2 2006.245.07:40:10.30#ibcon#about to write, iclass 16, count 2 2006.245.07:40:10.30#ibcon#wrote, iclass 16, count 2 2006.245.07:40:10.30#ibcon#about to read 3, iclass 16, count 2 2006.245.07:40:10.32#ibcon#read 3, iclass 16, count 2 2006.245.07:40:10.32#ibcon#about to read 4, iclass 16, count 2 2006.245.07:40:10.32#ibcon#read 4, iclass 16, count 2 2006.245.07:40:10.32#ibcon#about to read 5, iclass 16, count 2 2006.245.07:40:10.32#ibcon#read 5, iclass 16, count 2 2006.245.07:40:10.32#ibcon#about to read 6, iclass 16, count 2 2006.245.07:40:10.32#ibcon#read 6, iclass 16, count 2 2006.245.07:40:10.32#ibcon#end of sib2, iclass 16, count 2 2006.245.07:40:10.32#ibcon#*mode == 0, iclass 16, count 2 2006.245.07:40:10.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.07:40:10.32#ibcon#[25=AT03-06\r\n] 2006.245.07:40:10.32#ibcon#*before write, iclass 16, count 2 2006.245.07:40:10.32#ibcon#enter sib2, iclass 16, count 2 2006.245.07:40:10.32#ibcon#flushed, iclass 16, count 2 2006.245.07:40:10.32#ibcon#about to write, iclass 16, count 2 2006.245.07:40:10.32#ibcon#wrote, iclass 16, count 2 2006.245.07:40:10.32#ibcon#about to read 3, iclass 16, count 2 2006.245.07:40:10.35#ibcon#read 3, iclass 16, count 2 2006.245.07:40:10.35#ibcon#about to read 4, iclass 16, count 2 2006.245.07:40:10.35#ibcon#read 4, iclass 16, count 2 2006.245.07:40:10.35#ibcon#about to read 5, iclass 16, count 2 2006.245.07:40:10.35#ibcon#read 5, iclass 16, count 2 2006.245.07:40:10.35#ibcon#about to read 6, iclass 16, count 2 2006.245.07:40:10.35#ibcon#read 6, iclass 16, count 2 2006.245.07:40:10.35#ibcon#end of sib2, iclass 16, count 2 2006.245.07:40:10.35#ibcon#*after write, iclass 16, count 2 2006.245.07:40:10.35#ibcon#*before return 0, iclass 16, count 2 2006.245.07:40:10.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:10.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:10.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.07:40:10.35#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:10.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:10.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:10.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:10.47#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:40:10.47#ibcon#first serial, iclass 16, count 0 2006.245.07:40:10.47#ibcon#enter sib2, iclass 16, count 0 2006.245.07:40:10.47#ibcon#flushed, iclass 16, count 0 2006.245.07:40:10.47#ibcon#about to write, iclass 16, count 0 2006.245.07:40:10.47#ibcon#wrote, iclass 16, count 0 2006.245.07:40:10.47#ibcon#about to read 3, iclass 16, count 0 2006.245.07:40:10.49#ibcon#read 3, iclass 16, count 0 2006.245.07:40:10.49#ibcon#about to read 4, iclass 16, count 0 2006.245.07:40:10.49#ibcon#read 4, iclass 16, count 0 2006.245.07:40:10.49#ibcon#about to read 5, iclass 16, count 0 2006.245.07:40:10.49#ibcon#read 5, iclass 16, count 0 2006.245.07:40:10.49#ibcon#about to read 6, iclass 16, count 0 2006.245.07:40:10.49#ibcon#read 6, iclass 16, count 0 2006.245.07:40:10.49#ibcon#end of sib2, iclass 16, count 0 2006.245.07:40:10.49#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:40:10.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:40:10.49#ibcon#[25=USB\r\n] 2006.245.07:40:10.49#ibcon#*before write, iclass 16, count 0 2006.245.07:40:10.49#ibcon#enter sib2, iclass 16, count 0 2006.245.07:40:10.49#ibcon#flushed, iclass 16, count 0 2006.245.07:40:10.49#ibcon#about to write, iclass 16, count 0 2006.245.07:40:10.49#ibcon#wrote, iclass 16, count 0 2006.245.07:40:10.49#ibcon#about to read 3, iclass 16, count 0 2006.245.07:40:10.52#ibcon#read 3, iclass 16, count 0 2006.245.07:40:10.52#ibcon#about to read 4, iclass 16, count 0 2006.245.07:40:10.52#ibcon#read 4, iclass 16, count 0 2006.245.07:40:10.52#ibcon#about to read 5, iclass 16, count 0 2006.245.07:40:10.52#ibcon#read 5, iclass 16, count 0 2006.245.07:40:10.52#ibcon#about to read 6, iclass 16, count 0 2006.245.07:40:10.52#ibcon#read 6, iclass 16, count 0 2006.245.07:40:10.52#ibcon#end of sib2, iclass 16, count 0 2006.245.07:40:10.52#ibcon#*after write, iclass 16, count 0 2006.245.07:40:10.52#ibcon#*before return 0, iclass 16, count 0 2006.245.07:40:10.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:10.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:10.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:40:10.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:40:10.52$vc4f8/valo=4,832.99 2006.245.07:40:10.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.07:40:10.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.07:40:10.52#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:10.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:10.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:10.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:10.52#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:40:10.52#ibcon#first serial, iclass 18, count 0 2006.245.07:40:10.52#ibcon#enter sib2, iclass 18, count 0 2006.245.07:40:10.52#ibcon#flushed, iclass 18, count 0 2006.245.07:40:10.52#ibcon#about to write, iclass 18, count 0 2006.245.07:40:10.52#ibcon#wrote, iclass 18, count 0 2006.245.07:40:10.52#ibcon#about to read 3, iclass 18, count 0 2006.245.07:40:10.54#ibcon#read 3, iclass 18, count 0 2006.245.07:40:10.54#ibcon#about to read 4, iclass 18, count 0 2006.245.07:40:10.54#ibcon#read 4, iclass 18, count 0 2006.245.07:40:10.54#ibcon#about to read 5, iclass 18, count 0 2006.245.07:40:10.54#ibcon#read 5, iclass 18, count 0 2006.245.07:40:10.54#ibcon#about to read 6, iclass 18, count 0 2006.245.07:40:10.54#ibcon#read 6, iclass 18, count 0 2006.245.07:40:10.54#ibcon#end of sib2, iclass 18, count 0 2006.245.07:40:10.54#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:40:10.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:40:10.54#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:40:10.54#ibcon#*before write, iclass 18, count 0 2006.245.07:40:10.54#ibcon#enter sib2, iclass 18, count 0 2006.245.07:40:10.54#ibcon#flushed, iclass 18, count 0 2006.245.07:40:10.54#ibcon#about to write, iclass 18, count 0 2006.245.07:40:10.54#ibcon#wrote, iclass 18, count 0 2006.245.07:40:10.54#ibcon#about to read 3, iclass 18, count 0 2006.245.07:40:10.59#ibcon#read 3, iclass 18, count 0 2006.245.07:40:10.59#ibcon#about to read 4, iclass 18, count 0 2006.245.07:40:10.59#ibcon#read 4, iclass 18, count 0 2006.245.07:40:10.59#ibcon#about to read 5, iclass 18, count 0 2006.245.07:40:10.59#ibcon#read 5, iclass 18, count 0 2006.245.07:40:10.59#ibcon#about to read 6, iclass 18, count 0 2006.245.07:40:10.59#ibcon#read 6, iclass 18, count 0 2006.245.07:40:10.59#ibcon#end of sib2, iclass 18, count 0 2006.245.07:40:10.59#ibcon#*after write, iclass 18, count 0 2006.245.07:40:10.59#ibcon#*before return 0, iclass 18, count 0 2006.245.07:40:10.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:10.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:10.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:40:10.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:40:10.59$vc4f8/va=4,7 2006.245.07:40:10.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.07:40:10.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.07:40:10.59#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:10.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:10.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:10.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:10.64#ibcon#enter wrdev, iclass 20, count 2 2006.245.07:40:10.64#ibcon#first serial, iclass 20, count 2 2006.245.07:40:10.64#ibcon#enter sib2, iclass 20, count 2 2006.245.07:40:10.64#ibcon#flushed, iclass 20, count 2 2006.245.07:40:10.64#ibcon#about to write, iclass 20, count 2 2006.245.07:40:10.64#ibcon#wrote, iclass 20, count 2 2006.245.07:40:10.64#ibcon#about to read 3, iclass 20, count 2 2006.245.07:40:10.66#ibcon#read 3, iclass 20, count 2 2006.245.07:40:10.66#ibcon#about to read 4, iclass 20, count 2 2006.245.07:40:10.66#ibcon#read 4, iclass 20, count 2 2006.245.07:40:10.66#ibcon#about to read 5, iclass 20, count 2 2006.245.07:40:10.66#ibcon#read 5, iclass 20, count 2 2006.245.07:40:10.66#ibcon#about to read 6, iclass 20, count 2 2006.245.07:40:10.66#ibcon#read 6, iclass 20, count 2 2006.245.07:40:10.66#ibcon#end of sib2, iclass 20, count 2 2006.245.07:40:10.66#ibcon#*mode == 0, iclass 20, count 2 2006.245.07:40:10.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.07:40:10.66#ibcon#[25=AT04-07\r\n] 2006.245.07:40:10.66#ibcon#*before write, iclass 20, count 2 2006.245.07:40:10.66#ibcon#enter sib2, iclass 20, count 2 2006.245.07:40:10.66#ibcon#flushed, iclass 20, count 2 2006.245.07:40:10.66#ibcon#about to write, iclass 20, count 2 2006.245.07:40:10.66#ibcon#wrote, iclass 20, count 2 2006.245.07:40:10.66#ibcon#about to read 3, iclass 20, count 2 2006.245.07:40:10.69#ibcon#read 3, iclass 20, count 2 2006.245.07:40:10.69#ibcon#about to read 4, iclass 20, count 2 2006.245.07:40:10.69#ibcon#read 4, iclass 20, count 2 2006.245.07:40:10.69#ibcon#about to read 5, iclass 20, count 2 2006.245.07:40:10.69#ibcon#read 5, iclass 20, count 2 2006.245.07:40:10.69#ibcon#about to read 6, iclass 20, count 2 2006.245.07:40:10.69#ibcon#read 6, iclass 20, count 2 2006.245.07:40:10.69#ibcon#end of sib2, iclass 20, count 2 2006.245.07:40:10.69#ibcon#*after write, iclass 20, count 2 2006.245.07:40:10.69#ibcon#*before return 0, iclass 20, count 2 2006.245.07:40:10.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:10.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:10.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.07:40:10.69#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:10.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:10.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:10.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:10.81#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:40:10.81#ibcon#first serial, iclass 20, count 0 2006.245.07:40:10.81#ibcon#enter sib2, iclass 20, count 0 2006.245.07:40:10.81#ibcon#flushed, iclass 20, count 0 2006.245.07:40:10.81#ibcon#about to write, iclass 20, count 0 2006.245.07:40:10.81#ibcon#wrote, iclass 20, count 0 2006.245.07:40:10.81#ibcon#about to read 3, iclass 20, count 0 2006.245.07:40:10.83#ibcon#read 3, iclass 20, count 0 2006.245.07:40:10.83#ibcon#about to read 4, iclass 20, count 0 2006.245.07:40:10.83#ibcon#read 4, iclass 20, count 0 2006.245.07:40:10.83#ibcon#about to read 5, iclass 20, count 0 2006.245.07:40:10.83#ibcon#read 5, iclass 20, count 0 2006.245.07:40:10.83#ibcon#about to read 6, iclass 20, count 0 2006.245.07:40:10.83#ibcon#read 6, iclass 20, count 0 2006.245.07:40:10.83#ibcon#end of sib2, iclass 20, count 0 2006.245.07:40:10.83#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:40:10.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:40:10.83#ibcon#[25=USB\r\n] 2006.245.07:40:10.83#ibcon#*before write, iclass 20, count 0 2006.245.07:40:10.83#ibcon#enter sib2, iclass 20, count 0 2006.245.07:40:10.83#ibcon#flushed, iclass 20, count 0 2006.245.07:40:10.83#ibcon#about to write, iclass 20, count 0 2006.245.07:40:10.83#ibcon#wrote, iclass 20, count 0 2006.245.07:40:10.83#ibcon#about to read 3, iclass 20, count 0 2006.245.07:40:10.86#ibcon#read 3, iclass 20, count 0 2006.245.07:40:10.86#ibcon#about to read 4, iclass 20, count 0 2006.245.07:40:10.86#ibcon#read 4, iclass 20, count 0 2006.245.07:40:10.86#ibcon#about to read 5, iclass 20, count 0 2006.245.07:40:10.86#ibcon#read 5, iclass 20, count 0 2006.245.07:40:10.86#ibcon#about to read 6, iclass 20, count 0 2006.245.07:40:10.86#ibcon#read 6, iclass 20, count 0 2006.245.07:40:10.86#ibcon#end of sib2, iclass 20, count 0 2006.245.07:40:10.86#ibcon#*after write, iclass 20, count 0 2006.245.07:40:10.86#ibcon#*before return 0, iclass 20, count 0 2006.245.07:40:10.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:10.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:10.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:40:10.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:40:10.86$vc4f8/valo=5,652.99 2006.245.07:40:10.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.07:40:10.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.07:40:10.86#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:10.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:10.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:10.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:10.86#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:40:10.86#ibcon#first serial, iclass 22, count 0 2006.245.07:40:10.86#ibcon#enter sib2, iclass 22, count 0 2006.245.07:40:10.86#ibcon#flushed, iclass 22, count 0 2006.245.07:40:10.86#ibcon#about to write, iclass 22, count 0 2006.245.07:40:10.86#ibcon#wrote, iclass 22, count 0 2006.245.07:40:10.86#ibcon#about to read 3, iclass 22, count 0 2006.245.07:40:10.88#ibcon#read 3, iclass 22, count 0 2006.245.07:40:10.88#ibcon#about to read 4, iclass 22, count 0 2006.245.07:40:10.88#ibcon#read 4, iclass 22, count 0 2006.245.07:40:10.88#ibcon#about to read 5, iclass 22, count 0 2006.245.07:40:10.88#ibcon#read 5, iclass 22, count 0 2006.245.07:40:10.88#ibcon#about to read 6, iclass 22, count 0 2006.245.07:40:10.88#ibcon#read 6, iclass 22, count 0 2006.245.07:40:10.88#ibcon#end of sib2, iclass 22, count 0 2006.245.07:40:10.88#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:40:10.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:40:10.88#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:40:10.88#ibcon#*before write, iclass 22, count 0 2006.245.07:40:10.88#ibcon#enter sib2, iclass 22, count 0 2006.245.07:40:10.88#ibcon#flushed, iclass 22, count 0 2006.245.07:40:10.88#ibcon#about to write, iclass 22, count 0 2006.245.07:40:10.88#ibcon#wrote, iclass 22, count 0 2006.245.07:40:10.88#ibcon#about to read 3, iclass 22, count 0 2006.245.07:40:10.92#ibcon#read 3, iclass 22, count 0 2006.245.07:40:10.92#ibcon#about to read 4, iclass 22, count 0 2006.245.07:40:10.92#ibcon#read 4, iclass 22, count 0 2006.245.07:40:10.92#ibcon#about to read 5, iclass 22, count 0 2006.245.07:40:10.92#ibcon#read 5, iclass 22, count 0 2006.245.07:40:10.92#ibcon#about to read 6, iclass 22, count 0 2006.245.07:40:10.92#ibcon#read 6, iclass 22, count 0 2006.245.07:40:10.92#ibcon#end of sib2, iclass 22, count 0 2006.245.07:40:10.92#ibcon#*after write, iclass 22, count 0 2006.245.07:40:10.92#ibcon#*before return 0, iclass 22, count 0 2006.245.07:40:10.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:10.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:10.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:40:10.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:40:10.92$vc4f8/va=5,7 2006.245.07:40:10.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.07:40:10.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.07:40:10.92#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:10.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:10.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:10.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:10.98#ibcon#enter wrdev, iclass 24, count 2 2006.245.07:40:10.98#ibcon#first serial, iclass 24, count 2 2006.245.07:40:10.98#ibcon#enter sib2, iclass 24, count 2 2006.245.07:40:10.98#ibcon#flushed, iclass 24, count 2 2006.245.07:40:10.98#ibcon#about to write, iclass 24, count 2 2006.245.07:40:10.98#ibcon#wrote, iclass 24, count 2 2006.245.07:40:10.98#ibcon#about to read 3, iclass 24, count 2 2006.245.07:40:11.00#ibcon#read 3, iclass 24, count 2 2006.245.07:40:11.00#ibcon#about to read 4, iclass 24, count 2 2006.245.07:40:11.00#ibcon#read 4, iclass 24, count 2 2006.245.07:40:11.00#ibcon#about to read 5, iclass 24, count 2 2006.245.07:40:11.00#ibcon#read 5, iclass 24, count 2 2006.245.07:40:11.00#ibcon#about to read 6, iclass 24, count 2 2006.245.07:40:11.00#ibcon#read 6, iclass 24, count 2 2006.245.07:40:11.00#ibcon#end of sib2, iclass 24, count 2 2006.245.07:40:11.00#ibcon#*mode == 0, iclass 24, count 2 2006.245.07:40:11.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.07:40:11.00#ibcon#[25=AT05-07\r\n] 2006.245.07:40:11.00#ibcon#*before write, iclass 24, count 2 2006.245.07:40:11.00#ibcon#enter sib2, iclass 24, count 2 2006.245.07:40:11.00#ibcon#flushed, iclass 24, count 2 2006.245.07:40:11.00#ibcon#about to write, iclass 24, count 2 2006.245.07:40:11.00#ibcon#wrote, iclass 24, count 2 2006.245.07:40:11.00#ibcon#about to read 3, iclass 24, count 2 2006.245.07:40:11.03#ibcon#read 3, iclass 24, count 2 2006.245.07:40:11.03#ibcon#about to read 4, iclass 24, count 2 2006.245.07:40:11.03#ibcon#read 4, iclass 24, count 2 2006.245.07:40:11.03#ibcon#about to read 5, iclass 24, count 2 2006.245.07:40:11.03#ibcon#read 5, iclass 24, count 2 2006.245.07:40:11.03#ibcon#about to read 6, iclass 24, count 2 2006.245.07:40:11.03#ibcon#read 6, iclass 24, count 2 2006.245.07:40:11.03#ibcon#end of sib2, iclass 24, count 2 2006.245.07:40:11.03#ibcon#*after write, iclass 24, count 2 2006.245.07:40:11.03#ibcon#*before return 0, iclass 24, count 2 2006.245.07:40:11.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:11.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:11.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.07:40:11.03#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:11.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:11.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:11.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:11.15#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:40:11.15#ibcon#first serial, iclass 24, count 0 2006.245.07:40:11.15#ibcon#enter sib2, iclass 24, count 0 2006.245.07:40:11.15#ibcon#flushed, iclass 24, count 0 2006.245.07:40:11.15#ibcon#about to write, iclass 24, count 0 2006.245.07:40:11.15#ibcon#wrote, iclass 24, count 0 2006.245.07:40:11.15#ibcon#about to read 3, iclass 24, count 0 2006.245.07:40:11.17#ibcon#read 3, iclass 24, count 0 2006.245.07:40:11.17#ibcon#about to read 4, iclass 24, count 0 2006.245.07:40:11.17#ibcon#read 4, iclass 24, count 0 2006.245.07:40:11.17#ibcon#about to read 5, iclass 24, count 0 2006.245.07:40:11.17#ibcon#read 5, iclass 24, count 0 2006.245.07:40:11.17#ibcon#about to read 6, iclass 24, count 0 2006.245.07:40:11.17#ibcon#read 6, iclass 24, count 0 2006.245.07:40:11.17#ibcon#end of sib2, iclass 24, count 0 2006.245.07:40:11.17#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:40:11.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:40:11.17#ibcon#[25=USB\r\n] 2006.245.07:40:11.17#ibcon#*before write, iclass 24, count 0 2006.245.07:40:11.17#ibcon#enter sib2, iclass 24, count 0 2006.245.07:40:11.17#ibcon#flushed, iclass 24, count 0 2006.245.07:40:11.17#ibcon#about to write, iclass 24, count 0 2006.245.07:40:11.17#ibcon#wrote, iclass 24, count 0 2006.245.07:40:11.17#ibcon#about to read 3, iclass 24, count 0 2006.245.07:40:11.20#ibcon#read 3, iclass 24, count 0 2006.245.07:40:11.20#ibcon#about to read 4, iclass 24, count 0 2006.245.07:40:11.20#ibcon#read 4, iclass 24, count 0 2006.245.07:40:11.20#ibcon#about to read 5, iclass 24, count 0 2006.245.07:40:11.20#ibcon#read 5, iclass 24, count 0 2006.245.07:40:11.20#ibcon#about to read 6, iclass 24, count 0 2006.245.07:40:11.20#ibcon#read 6, iclass 24, count 0 2006.245.07:40:11.20#ibcon#end of sib2, iclass 24, count 0 2006.245.07:40:11.20#ibcon#*after write, iclass 24, count 0 2006.245.07:40:11.20#ibcon#*before return 0, iclass 24, count 0 2006.245.07:40:11.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:11.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:11.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:40:11.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:40:11.20$vc4f8/valo=6,772.99 2006.245.07:40:11.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.07:40:11.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.07:40:11.20#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:11.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:11.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:11.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:11.20#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:40:11.20#ibcon#first serial, iclass 26, count 0 2006.245.07:40:11.20#ibcon#enter sib2, iclass 26, count 0 2006.245.07:40:11.20#ibcon#flushed, iclass 26, count 0 2006.245.07:40:11.20#ibcon#about to write, iclass 26, count 0 2006.245.07:40:11.20#ibcon#wrote, iclass 26, count 0 2006.245.07:40:11.20#ibcon#about to read 3, iclass 26, count 0 2006.245.07:40:11.22#ibcon#read 3, iclass 26, count 0 2006.245.07:40:11.22#ibcon#about to read 4, iclass 26, count 0 2006.245.07:40:11.22#ibcon#read 4, iclass 26, count 0 2006.245.07:40:11.22#ibcon#about to read 5, iclass 26, count 0 2006.245.07:40:11.22#ibcon#read 5, iclass 26, count 0 2006.245.07:40:11.22#ibcon#about to read 6, iclass 26, count 0 2006.245.07:40:11.22#ibcon#read 6, iclass 26, count 0 2006.245.07:40:11.22#ibcon#end of sib2, iclass 26, count 0 2006.245.07:40:11.22#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:40:11.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:40:11.22#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:40:11.22#ibcon#*before write, iclass 26, count 0 2006.245.07:40:11.22#ibcon#enter sib2, iclass 26, count 0 2006.245.07:40:11.22#ibcon#flushed, iclass 26, count 0 2006.245.07:40:11.22#ibcon#about to write, iclass 26, count 0 2006.245.07:40:11.22#ibcon#wrote, iclass 26, count 0 2006.245.07:40:11.22#ibcon#about to read 3, iclass 26, count 0 2006.245.07:40:11.26#ibcon#read 3, iclass 26, count 0 2006.245.07:40:11.26#ibcon#about to read 4, iclass 26, count 0 2006.245.07:40:11.26#ibcon#read 4, iclass 26, count 0 2006.245.07:40:11.26#ibcon#about to read 5, iclass 26, count 0 2006.245.07:40:11.26#ibcon#read 5, iclass 26, count 0 2006.245.07:40:11.26#ibcon#about to read 6, iclass 26, count 0 2006.245.07:40:11.26#ibcon#read 6, iclass 26, count 0 2006.245.07:40:11.26#ibcon#end of sib2, iclass 26, count 0 2006.245.07:40:11.26#ibcon#*after write, iclass 26, count 0 2006.245.07:40:11.26#ibcon#*before return 0, iclass 26, count 0 2006.245.07:40:11.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:11.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:11.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:40:11.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:40:11.26$vc4f8/va=6,7 2006.245.07:40:11.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.07:40:11.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.07:40:11.26#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:11.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:40:11.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:40:11.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:40:11.32#ibcon#enter wrdev, iclass 28, count 2 2006.245.07:40:11.32#ibcon#first serial, iclass 28, count 2 2006.245.07:40:11.32#ibcon#enter sib2, iclass 28, count 2 2006.245.07:40:11.32#ibcon#flushed, iclass 28, count 2 2006.245.07:40:11.32#ibcon#about to write, iclass 28, count 2 2006.245.07:40:11.32#ibcon#wrote, iclass 28, count 2 2006.245.07:40:11.32#ibcon#about to read 3, iclass 28, count 2 2006.245.07:40:11.34#ibcon#read 3, iclass 28, count 2 2006.245.07:40:11.34#ibcon#about to read 4, iclass 28, count 2 2006.245.07:40:11.34#ibcon#read 4, iclass 28, count 2 2006.245.07:40:11.34#ibcon#about to read 5, iclass 28, count 2 2006.245.07:40:11.34#ibcon#read 5, iclass 28, count 2 2006.245.07:40:11.34#ibcon#about to read 6, iclass 28, count 2 2006.245.07:40:11.34#ibcon#read 6, iclass 28, count 2 2006.245.07:40:11.34#ibcon#end of sib2, iclass 28, count 2 2006.245.07:40:11.34#ibcon#*mode == 0, iclass 28, count 2 2006.245.07:40:11.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.07:40:11.34#ibcon#[25=AT06-07\r\n] 2006.245.07:40:11.34#ibcon#*before write, iclass 28, count 2 2006.245.07:40:11.34#ibcon#enter sib2, iclass 28, count 2 2006.245.07:40:11.34#ibcon#flushed, iclass 28, count 2 2006.245.07:40:11.34#ibcon#about to write, iclass 28, count 2 2006.245.07:40:11.34#ibcon#wrote, iclass 28, count 2 2006.245.07:40:11.34#ibcon#about to read 3, iclass 28, count 2 2006.245.07:40:11.37#ibcon#read 3, iclass 28, count 2 2006.245.07:40:11.37#ibcon#about to read 4, iclass 28, count 2 2006.245.07:40:11.37#ibcon#read 4, iclass 28, count 2 2006.245.07:40:11.37#ibcon#about to read 5, iclass 28, count 2 2006.245.07:40:11.37#ibcon#read 5, iclass 28, count 2 2006.245.07:40:11.37#ibcon#about to read 6, iclass 28, count 2 2006.245.07:40:11.37#ibcon#read 6, iclass 28, count 2 2006.245.07:40:11.37#ibcon#end of sib2, iclass 28, count 2 2006.245.07:40:11.37#ibcon#*after write, iclass 28, count 2 2006.245.07:40:11.37#ibcon#*before return 0, iclass 28, count 2 2006.245.07:40:11.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:40:11.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:40:11.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.07:40:11.37#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:11.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:40:11.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:40:11.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:40:11.49#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:40:11.49#ibcon#first serial, iclass 28, count 0 2006.245.07:40:11.49#ibcon#enter sib2, iclass 28, count 0 2006.245.07:40:11.49#ibcon#flushed, iclass 28, count 0 2006.245.07:40:11.49#ibcon#about to write, iclass 28, count 0 2006.245.07:40:11.49#ibcon#wrote, iclass 28, count 0 2006.245.07:40:11.49#ibcon#about to read 3, iclass 28, count 0 2006.245.07:40:11.51#ibcon#read 3, iclass 28, count 0 2006.245.07:40:11.51#ibcon#about to read 4, iclass 28, count 0 2006.245.07:40:11.51#ibcon#read 4, iclass 28, count 0 2006.245.07:40:11.51#ibcon#about to read 5, iclass 28, count 0 2006.245.07:40:11.51#ibcon#read 5, iclass 28, count 0 2006.245.07:40:11.51#ibcon#about to read 6, iclass 28, count 0 2006.245.07:40:11.51#ibcon#read 6, iclass 28, count 0 2006.245.07:40:11.51#ibcon#end of sib2, iclass 28, count 0 2006.245.07:40:11.51#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:40:11.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:40:11.51#ibcon#[25=USB\r\n] 2006.245.07:40:11.51#ibcon#*before write, iclass 28, count 0 2006.245.07:40:11.51#ibcon#enter sib2, iclass 28, count 0 2006.245.07:40:11.51#ibcon#flushed, iclass 28, count 0 2006.245.07:40:11.51#ibcon#about to write, iclass 28, count 0 2006.245.07:40:11.51#ibcon#wrote, iclass 28, count 0 2006.245.07:40:11.51#ibcon#about to read 3, iclass 28, count 0 2006.245.07:40:11.54#ibcon#read 3, iclass 28, count 0 2006.245.07:40:11.54#ibcon#about to read 4, iclass 28, count 0 2006.245.07:40:11.54#ibcon#read 4, iclass 28, count 0 2006.245.07:40:11.54#ibcon#about to read 5, iclass 28, count 0 2006.245.07:40:11.54#ibcon#read 5, iclass 28, count 0 2006.245.07:40:11.54#ibcon#about to read 6, iclass 28, count 0 2006.245.07:40:11.54#ibcon#read 6, iclass 28, count 0 2006.245.07:40:11.54#ibcon#end of sib2, iclass 28, count 0 2006.245.07:40:11.54#ibcon#*after write, iclass 28, count 0 2006.245.07:40:11.54#ibcon#*before return 0, iclass 28, count 0 2006.245.07:40:11.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:40:11.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:40:11.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:40:11.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:40:11.54$vc4f8/valo=7,832.99 2006.245.07:40:11.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:40:11.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:40:11.54#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:11.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:40:11.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:40:11.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:40:11.54#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:40:11.54#ibcon#first serial, iclass 30, count 0 2006.245.07:40:11.54#ibcon#enter sib2, iclass 30, count 0 2006.245.07:40:11.54#ibcon#flushed, iclass 30, count 0 2006.245.07:40:11.54#ibcon#about to write, iclass 30, count 0 2006.245.07:40:11.54#ibcon#wrote, iclass 30, count 0 2006.245.07:40:11.54#ibcon#about to read 3, iclass 30, count 0 2006.245.07:40:11.56#ibcon#read 3, iclass 30, count 0 2006.245.07:40:11.56#ibcon#about to read 4, iclass 30, count 0 2006.245.07:40:11.56#ibcon#read 4, iclass 30, count 0 2006.245.07:40:11.56#ibcon#about to read 5, iclass 30, count 0 2006.245.07:40:11.56#ibcon#read 5, iclass 30, count 0 2006.245.07:40:11.56#ibcon#about to read 6, iclass 30, count 0 2006.245.07:40:11.56#ibcon#read 6, iclass 30, count 0 2006.245.07:40:11.56#ibcon#end of sib2, iclass 30, count 0 2006.245.07:40:11.56#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:40:11.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:40:11.56#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:40:11.56#ibcon#*before write, iclass 30, count 0 2006.245.07:40:11.56#ibcon#enter sib2, iclass 30, count 0 2006.245.07:40:11.56#ibcon#flushed, iclass 30, count 0 2006.245.07:40:11.56#ibcon#about to write, iclass 30, count 0 2006.245.07:40:11.56#ibcon#wrote, iclass 30, count 0 2006.245.07:40:11.56#ibcon#about to read 3, iclass 30, count 0 2006.245.07:40:11.60#ibcon#read 3, iclass 30, count 0 2006.245.07:40:11.60#ibcon#about to read 4, iclass 30, count 0 2006.245.07:40:11.60#ibcon#read 4, iclass 30, count 0 2006.245.07:40:11.60#ibcon#about to read 5, iclass 30, count 0 2006.245.07:40:11.60#ibcon#read 5, iclass 30, count 0 2006.245.07:40:11.60#ibcon#about to read 6, iclass 30, count 0 2006.245.07:40:11.60#ibcon#read 6, iclass 30, count 0 2006.245.07:40:11.60#ibcon#end of sib2, iclass 30, count 0 2006.245.07:40:11.60#ibcon#*after write, iclass 30, count 0 2006.245.07:40:11.60#ibcon#*before return 0, iclass 30, count 0 2006.245.07:40:11.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:40:11.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:40:11.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:40:11.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:40:11.60$vc4f8/va=7,7 2006.245.07:40:11.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.07:40:11.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.07:40:11.60#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:11.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:40:11.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:40:11.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:40:11.66#ibcon#enter wrdev, iclass 32, count 2 2006.245.07:40:11.66#ibcon#first serial, iclass 32, count 2 2006.245.07:40:11.66#ibcon#enter sib2, iclass 32, count 2 2006.245.07:40:11.66#ibcon#flushed, iclass 32, count 2 2006.245.07:40:11.66#ibcon#about to write, iclass 32, count 2 2006.245.07:40:11.66#ibcon#wrote, iclass 32, count 2 2006.245.07:40:11.66#ibcon#about to read 3, iclass 32, count 2 2006.245.07:40:11.68#ibcon#read 3, iclass 32, count 2 2006.245.07:40:11.68#ibcon#about to read 4, iclass 32, count 2 2006.245.07:40:11.68#ibcon#read 4, iclass 32, count 2 2006.245.07:40:11.68#ibcon#about to read 5, iclass 32, count 2 2006.245.07:40:11.68#ibcon#read 5, iclass 32, count 2 2006.245.07:40:11.68#ibcon#about to read 6, iclass 32, count 2 2006.245.07:40:11.68#ibcon#read 6, iclass 32, count 2 2006.245.07:40:11.68#ibcon#end of sib2, iclass 32, count 2 2006.245.07:40:11.68#ibcon#*mode == 0, iclass 32, count 2 2006.245.07:40:11.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.07:40:11.68#ibcon#[25=AT07-07\r\n] 2006.245.07:40:11.68#ibcon#*before write, iclass 32, count 2 2006.245.07:40:11.68#ibcon#enter sib2, iclass 32, count 2 2006.245.07:40:11.68#ibcon#flushed, iclass 32, count 2 2006.245.07:40:11.68#ibcon#about to write, iclass 32, count 2 2006.245.07:40:11.68#ibcon#wrote, iclass 32, count 2 2006.245.07:40:11.68#ibcon#about to read 3, iclass 32, count 2 2006.245.07:40:11.71#ibcon#read 3, iclass 32, count 2 2006.245.07:40:11.71#ibcon#about to read 4, iclass 32, count 2 2006.245.07:40:11.71#ibcon#read 4, iclass 32, count 2 2006.245.07:40:11.71#ibcon#about to read 5, iclass 32, count 2 2006.245.07:40:11.71#ibcon#read 5, iclass 32, count 2 2006.245.07:40:11.71#ibcon#about to read 6, iclass 32, count 2 2006.245.07:40:11.71#ibcon#read 6, iclass 32, count 2 2006.245.07:40:11.71#ibcon#end of sib2, iclass 32, count 2 2006.245.07:40:11.71#ibcon#*after write, iclass 32, count 2 2006.245.07:40:11.71#ibcon#*before return 0, iclass 32, count 2 2006.245.07:40:11.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:40:11.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:40:11.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.07:40:11.71#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:11.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:40:11.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:40:11.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:40:11.83#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:40:11.83#ibcon#first serial, iclass 32, count 0 2006.245.07:40:11.83#ibcon#enter sib2, iclass 32, count 0 2006.245.07:40:11.83#ibcon#flushed, iclass 32, count 0 2006.245.07:40:11.83#ibcon#about to write, iclass 32, count 0 2006.245.07:40:11.83#ibcon#wrote, iclass 32, count 0 2006.245.07:40:11.83#ibcon#about to read 3, iclass 32, count 0 2006.245.07:40:11.85#ibcon#read 3, iclass 32, count 0 2006.245.07:40:11.85#ibcon#about to read 4, iclass 32, count 0 2006.245.07:40:11.85#ibcon#read 4, iclass 32, count 0 2006.245.07:40:11.85#ibcon#about to read 5, iclass 32, count 0 2006.245.07:40:11.85#ibcon#read 5, iclass 32, count 0 2006.245.07:40:11.85#ibcon#about to read 6, iclass 32, count 0 2006.245.07:40:11.85#ibcon#read 6, iclass 32, count 0 2006.245.07:40:11.85#ibcon#end of sib2, iclass 32, count 0 2006.245.07:40:11.85#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:40:11.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:40:11.85#ibcon#[25=USB\r\n] 2006.245.07:40:11.85#ibcon#*before write, iclass 32, count 0 2006.245.07:40:11.85#ibcon#enter sib2, iclass 32, count 0 2006.245.07:40:11.85#ibcon#flushed, iclass 32, count 0 2006.245.07:40:11.85#ibcon#about to write, iclass 32, count 0 2006.245.07:40:11.85#ibcon#wrote, iclass 32, count 0 2006.245.07:40:11.85#ibcon#about to read 3, iclass 32, count 0 2006.245.07:40:11.88#ibcon#read 3, iclass 32, count 0 2006.245.07:40:11.88#ibcon#about to read 4, iclass 32, count 0 2006.245.07:40:11.88#ibcon#read 4, iclass 32, count 0 2006.245.07:40:11.88#ibcon#about to read 5, iclass 32, count 0 2006.245.07:40:11.88#ibcon#read 5, iclass 32, count 0 2006.245.07:40:11.88#ibcon#about to read 6, iclass 32, count 0 2006.245.07:40:11.88#ibcon#read 6, iclass 32, count 0 2006.245.07:40:11.88#ibcon#end of sib2, iclass 32, count 0 2006.245.07:40:11.88#ibcon#*after write, iclass 32, count 0 2006.245.07:40:11.88#ibcon#*before return 0, iclass 32, count 0 2006.245.07:40:11.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:40:11.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:40:11.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:40:11.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:40:11.88$vc4f8/valo=8,852.99 2006.245.07:40:11.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:40:11.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:40:11.88#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:11.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:40:11.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:40:11.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:40:11.88#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:40:11.88#ibcon#first serial, iclass 34, count 0 2006.245.07:40:11.88#ibcon#enter sib2, iclass 34, count 0 2006.245.07:40:11.88#ibcon#flushed, iclass 34, count 0 2006.245.07:40:11.88#ibcon#about to write, iclass 34, count 0 2006.245.07:40:11.88#ibcon#wrote, iclass 34, count 0 2006.245.07:40:11.88#ibcon#about to read 3, iclass 34, count 0 2006.245.07:40:11.90#ibcon#read 3, iclass 34, count 0 2006.245.07:40:11.90#ibcon#about to read 4, iclass 34, count 0 2006.245.07:40:11.90#ibcon#read 4, iclass 34, count 0 2006.245.07:40:11.90#ibcon#about to read 5, iclass 34, count 0 2006.245.07:40:11.90#ibcon#read 5, iclass 34, count 0 2006.245.07:40:11.90#ibcon#about to read 6, iclass 34, count 0 2006.245.07:40:11.90#ibcon#read 6, iclass 34, count 0 2006.245.07:40:11.90#ibcon#end of sib2, iclass 34, count 0 2006.245.07:40:11.90#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:40:11.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:40:11.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:40:11.90#ibcon#*before write, iclass 34, count 0 2006.245.07:40:11.90#ibcon#enter sib2, iclass 34, count 0 2006.245.07:40:11.90#ibcon#flushed, iclass 34, count 0 2006.245.07:40:11.90#ibcon#about to write, iclass 34, count 0 2006.245.07:40:11.90#ibcon#wrote, iclass 34, count 0 2006.245.07:40:11.90#ibcon#about to read 3, iclass 34, count 0 2006.245.07:40:11.94#ibcon#read 3, iclass 34, count 0 2006.245.07:40:11.94#ibcon#about to read 4, iclass 34, count 0 2006.245.07:40:11.94#ibcon#read 4, iclass 34, count 0 2006.245.07:40:11.94#ibcon#about to read 5, iclass 34, count 0 2006.245.07:40:11.94#ibcon#read 5, iclass 34, count 0 2006.245.07:40:11.94#ibcon#about to read 6, iclass 34, count 0 2006.245.07:40:11.94#ibcon#read 6, iclass 34, count 0 2006.245.07:40:11.94#ibcon#end of sib2, iclass 34, count 0 2006.245.07:40:11.94#ibcon#*after write, iclass 34, count 0 2006.245.07:40:11.94#ibcon#*before return 0, iclass 34, count 0 2006.245.07:40:11.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:40:11.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:40:11.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:40:11.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:40:11.94$vc4f8/va=8,8 2006.245.07:40:11.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:40:11.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:40:11.94#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:11.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:40:12.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:40:12.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:40:12.00#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:40:12.00#ibcon#first serial, iclass 36, count 2 2006.245.07:40:12.00#ibcon#enter sib2, iclass 36, count 2 2006.245.07:40:12.00#ibcon#flushed, iclass 36, count 2 2006.245.07:40:12.00#ibcon#about to write, iclass 36, count 2 2006.245.07:40:12.00#ibcon#wrote, iclass 36, count 2 2006.245.07:40:12.00#ibcon#about to read 3, iclass 36, count 2 2006.245.07:40:12.02#ibcon#read 3, iclass 36, count 2 2006.245.07:40:12.02#ibcon#about to read 4, iclass 36, count 2 2006.245.07:40:12.02#ibcon#read 4, iclass 36, count 2 2006.245.07:40:12.02#ibcon#about to read 5, iclass 36, count 2 2006.245.07:40:12.02#ibcon#read 5, iclass 36, count 2 2006.245.07:40:12.02#ibcon#about to read 6, iclass 36, count 2 2006.245.07:40:12.02#ibcon#read 6, iclass 36, count 2 2006.245.07:40:12.02#ibcon#end of sib2, iclass 36, count 2 2006.245.07:40:12.02#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:40:12.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:40:12.02#ibcon#[25=AT08-08\r\n] 2006.245.07:40:12.02#ibcon#*before write, iclass 36, count 2 2006.245.07:40:12.02#ibcon#enter sib2, iclass 36, count 2 2006.245.07:40:12.02#ibcon#flushed, iclass 36, count 2 2006.245.07:40:12.02#ibcon#about to write, iclass 36, count 2 2006.245.07:40:12.02#ibcon#wrote, iclass 36, count 2 2006.245.07:40:12.02#ibcon#about to read 3, iclass 36, count 2 2006.245.07:40:12.05#ibcon#read 3, iclass 36, count 2 2006.245.07:40:12.05#ibcon#about to read 4, iclass 36, count 2 2006.245.07:40:12.05#ibcon#read 4, iclass 36, count 2 2006.245.07:40:12.05#ibcon#about to read 5, iclass 36, count 2 2006.245.07:40:12.05#ibcon#read 5, iclass 36, count 2 2006.245.07:40:12.05#ibcon#about to read 6, iclass 36, count 2 2006.245.07:40:12.05#ibcon#read 6, iclass 36, count 2 2006.245.07:40:12.05#ibcon#end of sib2, iclass 36, count 2 2006.245.07:40:12.05#ibcon#*after write, iclass 36, count 2 2006.245.07:40:12.05#ibcon#*before return 0, iclass 36, count 2 2006.245.07:40:12.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:40:12.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:40:12.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:40:12.05#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:12.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:40:12.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:40:12.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:40:12.17#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:40:12.17#ibcon#first serial, iclass 36, count 0 2006.245.07:40:12.17#ibcon#enter sib2, iclass 36, count 0 2006.245.07:40:12.17#ibcon#flushed, iclass 36, count 0 2006.245.07:40:12.17#ibcon#about to write, iclass 36, count 0 2006.245.07:40:12.17#ibcon#wrote, iclass 36, count 0 2006.245.07:40:12.17#ibcon#about to read 3, iclass 36, count 0 2006.245.07:40:12.19#ibcon#read 3, iclass 36, count 0 2006.245.07:40:12.19#ibcon#about to read 4, iclass 36, count 0 2006.245.07:40:12.19#ibcon#read 4, iclass 36, count 0 2006.245.07:40:12.19#ibcon#about to read 5, iclass 36, count 0 2006.245.07:40:12.19#ibcon#read 5, iclass 36, count 0 2006.245.07:40:12.19#ibcon#about to read 6, iclass 36, count 0 2006.245.07:40:12.19#ibcon#read 6, iclass 36, count 0 2006.245.07:40:12.19#ibcon#end of sib2, iclass 36, count 0 2006.245.07:40:12.19#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:40:12.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:40:12.19#ibcon#[25=USB\r\n] 2006.245.07:40:12.19#ibcon#*before write, iclass 36, count 0 2006.245.07:40:12.19#ibcon#enter sib2, iclass 36, count 0 2006.245.07:40:12.19#ibcon#flushed, iclass 36, count 0 2006.245.07:40:12.19#ibcon#about to write, iclass 36, count 0 2006.245.07:40:12.19#ibcon#wrote, iclass 36, count 0 2006.245.07:40:12.19#ibcon#about to read 3, iclass 36, count 0 2006.245.07:40:12.22#ibcon#read 3, iclass 36, count 0 2006.245.07:40:12.22#ibcon#about to read 4, iclass 36, count 0 2006.245.07:40:12.22#ibcon#read 4, iclass 36, count 0 2006.245.07:40:12.22#ibcon#about to read 5, iclass 36, count 0 2006.245.07:40:12.22#ibcon#read 5, iclass 36, count 0 2006.245.07:40:12.22#ibcon#about to read 6, iclass 36, count 0 2006.245.07:40:12.22#ibcon#read 6, iclass 36, count 0 2006.245.07:40:12.22#ibcon#end of sib2, iclass 36, count 0 2006.245.07:40:12.22#ibcon#*after write, iclass 36, count 0 2006.245.07:40:12.22#ibcon#*before return 0, iclass 36, count 0 2006.245.07:40:12.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:40:12.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:40:12.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:40:12.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:40:12.22$vc4f8/vblo=1,632.99 2006.245.07:40:12.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:40:12.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:40:12.22#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:12.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:12.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:12.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:12.22#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:40:12.22#ibcon#first serial, iclass 38, count 0 2006.245.07:40:12.22#ibcon#enter sib2, iclass 38, count 0 2006.245.07:40:12.22#ibcon#flushed, iclass 38, count 0 2006.245.07:40:12.22#ibcon#about to write, iclass 38, count 0 2006.245.07:40:12.22#ibcon#wrote, iclass 38, count 0 2006.245.07:40:12.22#ibcon#about to read 3, iclass 38, count 0 2006.245.07:40:12.24#ibcon#read 3, iclass 38, count 0 2006.245.07:40:12.24#ibcon#about to read 4, iclass 38, count 0 2006.245.07:40:12.24#ibcon#read 4, iclass 38, count 0 2006.245.07:40:12.24#ibcon#about to read 5, iclass 38, count 0 2006.245.07:40:12.24#ibcon#read 5, iclass 38, count 0 2006.245.07:40:12.24#ibcon#about to read 6, iclass 38, count 0 2006.245.07:40:12.24#ibcon#read 6, iclass 38, count 0 2006.245.07:40:12.24#ibcon#end of sib2, iclass 38, count 0 2006.245.07:40:12.24#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:40:12.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:40:12.24#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:40:12.24#ibcon#*before write, iclass 38, count 0 2006.245.07:40:12.24#ibcon#enter sib2, iclass 38, count 0 2006.245.07:40:12.24#ibcon#flushed, iclass 38, count 0 2006.245.07:40:12.24#ibcon#about to write, iclass 38, count 0 2006.245.07:40:12.24#ibcon#wrote, iclass 38, count 0 2006.245.07:40:12.24#ibcon#about to read 3, iclass 38, count 0 2006.245.07:40:12.28#ibcon#read 3, iclass 38, count 0 2006.245.07:40:12.28#ibcon#about to read 4, iclass 38, count 0 2006.245.07:40:12.28#ibcon#read 4, iclass 38, count 0 2006.245.07:40:12.28#ibcon#about to read 5, iclass 38, count 0 2006.245.07:40:12.28#ibcon#read 5, iclass 38, count 0 2006.245.07:40:12.28#ibcon#about to read 6, iclass 38, count 0 2006.245.07:40:12.28#ibcon#read 6, iclass 38, count 0 2006.245.07:40:12.28#ibcon#end of sib2, iclass 38, count 0 2006.245.07:40:12.28#ibcon#*after write, iclass 38, count 0 2006.245.07:40:12.28#ibcon#*before return 0, iclass 38, count 0 2006.245.07:40:12.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:12.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:40:12.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:40:12.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:40:12.28$vc4f8/vb=1,4 2006.245.07:40:12.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:40:12.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:40:12.28#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:12.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:12.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:12.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:12.28#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:40:12.28#ibcon#first serial, iclass 40, count 2 2006.245.07:40:12.28#ibcon#enter sib2, iclass 40, count 2 2006.245.07:40:12.28#ibcon#flushed, iclass 40, count 2 2006.245.07:40:12.28#ibcon#about to write, iclass 40, count 2 2006.245.07:40:12.28#ibcon#wrote, iclass 40, count 2 2006.245.07:40:12.28#ibcon#about to read 3, iclass 40, count 2 2006.245.07:40:12.30#ibcon#read 3, iclass 40, count 2 2006.245.07:40:12.30#ibcon#about to read 4, iclass 40, count 2 2006.245.07:40:12.30#ibcon#read 4, iclass 40, count 2 2006.245.07:40:12.30#ibcon#about to read 5, iclass 40, count 2 2006.245.07:40:12.30#ibcon#read 5, iclass 40, count 2 2006.245.07:40:12.30#ibcon#about to read 6, iclass 40, count 2 2006.245.07:40:12.30#ibcon#read 6, iclass 40, count 2 2006.245.07:40:12.30#ibcon#end of sib2, iclass 40, count 2 2006.245.07:40:12.30#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:40:12.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:40:12.30#ibcon#[27=AT01-04\r\n] 2006.245.07:40:12.30#ibcon#*before write, iclass 40, count 2 2006.245.07:40:12.30#ibcon#enter sib2, iclass 40, count 2 2006.245.07:40:12.30#ibcon#flushed, iclass 40, count 2 2006.245.07:40:12.30#ibcon#about to write, iclass 40, count 2 2006.245.07:40:12.30#ibcon#wrote, iclass 40, count 2 2006.245.07:40:12.30#ibcon#about to read 3, iclass 40, count 2 2006.245.07:40:12.33#ibcon#read 3, iclass 40, count 2 2006.245.07:40:12.33#ibcon#about to read 4, iclass 40, count 2 2006.245.07:40:12.33#ibcon#read 4, iclass 40, count 2 2006.245.07:40:12.33#ibcon#about to read 5, iclass 40, count 2 2006.245.07:40:12.33#ibcon#read 5, iclass 40, count 2 2006.245.07:40:12.33#ibcon#about to read 6, iclass 40, count 2 2006.245.07:40:12.33#ibcon#read 6, iclass 40, count 2 2006.245.07:40:12.33#ibcon#end of sib2, iclass 40, count 2 2006.245.07:40:12.33#ibcon#*after write, iclass 40, count 2 2006.245.07:40:12.33#ibcon#*before return 0, iclass 40, count 2 2006.245.07:40:12.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:12.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:40:12.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:40:12.33#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:12.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:12.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:12.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:12.45#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:40:12.45#ibcon#first serial, iclass 40, count 0 2006.245.07:40:12.45#ibcon#enter sib2, iclass 40, count 0 2006.245.07:40:12.45#ibcon#flushed, iclass 40, count 0 2006.245.07:40:12.45#ibcon#about to write, iclass 40, count 0 2006.245.07:40:12.45#ibcon#wrote, iclass 40, count 0 2006.245.07:40:12.45#ibcon#about to read 3, iclass 40, count 0 2006.245.07:40:12.47#ibcon#read 3, iclass 40, count 0 2006.245.07:40:12.47#ibcon#about to read 4, iclass 40, count 0 2006.245.07:40:12.47#ibcon#read 4, iclass 40, count 0 2006.245.07:40:12.47#ibcon#about to read 5, iclass 40, count 0 2006.245.07:40:12.47#ibcon#read 5, iclass 40, count 0 2006.245.07:40:12.47#ibcon#about to read 6, iclass 40, count 0 2006.245.07:40:12.47#ibcon#read 6, iclass 40, count 0 2006.245.07:40:12.47#ibcon#end of sib2, iclass 40, count 0 2006.245.07:40:12.47#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:40:12.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:40:12.47#ibcon#[27=USB\r\n] 2006.245.07:40:12.47#ibcon#*before write, iclass 40, count 0 2006.245.07:40:12.47#ibcon#enter sib2, iclass 40, count 0 2006.245.07:40:12.47#ibcon#flushed, iclass 40, count 0 2006.245.07:40:12.47#ibcon#about to write, iclass 40, count 0 2006.245.07:40:12.47#ibcon#wrote, iclass 40, count 0 2006.245.07:40:12.47#ibcon#about to read 3, iclass 40, count 0 2006.245.07:40:12.50#ibcon#read 3, iclass 40, count 0 2006.245.07:40:12.50#ibcon#about to read 4, iclass 40, count 0 2006.245.07:40:12.50#ibcon#read 4, iclass 40, count 0 2006.245.07:40:12.50#ibcon#about to read 5, iclass 40, count 0 2006.245.07:40:12.50#ibcon#read 5, iclass 40, count 0 2006.245.07:40:12.50#ibcon#about to read 6, iclass 40, count 0 2006.245.07:40:12.50#ibcon#read 6, iclass 40, count 0 2006.245.07:40:12.50#ibcon#end of sib2, iclass 40, count 0 2006.245.07:40:12.50#ibcon#*after write, iclass 40, count 0 2006.245.07:40:12.50#ibcon#*before return 0, iclass 40, count 0 2006.245.07:40:12.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:12.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:40:12.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:40:12.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:40:12.50$vc4f8/vblo=2,640.99 2006.245.07:40:12.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:40:12.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:40:12.50#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:12.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:12.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:12.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:12.50#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:40:12.50#ibcon#first serial, iclass 4, count 0 2006.245.07:40:12.50#ibcon#enter sib2, iclass 4, count 0 2006.245.07:40:12.50#ibcon#flushed, iclass 4, count 0 2006.245.07:40:12.50#ibcon#about to write, iclass 4, count 0 2006.245.07:40:12.50#ibcon#wrote, iclass 4, count 0 2006.245.07:40:12.50#ibcon#about to read 3, iclass 4, count 0 2006.245.07:40:12.52#ibcon#read 3, iclass 4, count 0 2006.245.07:40:12.52#ibcon#about to read 4, iclass 4, count 0 2006.245.07:40:12.52#ibcon#read 4, iclass 4, count 0 2006.245.07:40:12.52#ibcon#about to read 5, iclass 4, count 0 2006.245.07:40:12.52#ibcon#read 5, iclass 4, count 0 2006.245.07:40:12.52#ibcon#about to read 6, iclass 4, count 0 2006.245.07:40:12.52#ibcon#read 6, iclass 4, count 0 2006.245.07:40:12.52#ibcon#end of sib2, iclass 4, count 0 2006.245.07:40:12.52#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:40:12.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:40:12.52#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:40:12.52#ibcon#*before write, iclass 4, count 0 2006.245.07:40:12.52#ibcon#enter sib2, iclass 4, count 0 2006.245.07:40:12.52#ibcon#flushed, iclass 4, count 0 2006.245.07:40:12.52#ibcon#about to write, iclass 4, count 0 2006.245.07:40:12.52#ibcon#wrote, iclass 4, count 0 2006.245.07:40:12.52#ibcon#about to read 3, iclass 4, count 0 2006.245.07:40:12.56#ibcon#read 3, iclass 4, count 0 2006.245.07:40:12.56#ibcon#about to read 4, iclass 4, count 0 2006.245.07:40:12.56#ibcon#read 4, iclass 4, count 0 2006.245.07:40:12.56#ibcon#about to read 5, iclass 4, count 0 2006.245.07:40:12.56#ibcon#read 5, iclass 4, count 0 2006.245.07:40:12.56#ibcon#about to read 6, iclass 4, count 0 2006.245.07:40:12.56#ibcon#read 6, iclass 4, count 0 2006.245.07:40:12.56#ibcon#end of sib2, iclass 4, count 0 2006.245.07:40:12.56#ibcon#*after write, iclass 4, count 0 2006.245.07:40:12.56#ibcon#*before return 0, iclass 4, count 0 2006.245.07:40:12.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:12.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:40:12.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:40:12.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:40:12.56$vc4f8/vb=2,4 2006.245.07:40:12.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:40:12.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:40:12.56#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:12.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:40:12.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:40:12.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:40:12.62#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:40:12.62#ibcon#first serial, iclass 6, count 2 2006.245.07:40:12.62#ibcon#enter sib2, iclass 6, count 2 2006.245.07:40:12.62#ibcon#flushed, iclass 6, count 2 2006.245.07:40:12.62#ibcon#about to write, iclass 6, count 2 2006.245.07:40:12.62#ibcon#wrote, iclass 6, count 2 2006.245.07:40:12.62#ibcon#about to read 3, iclass 6, count 2 2006.245.07:40:12.64#ibcon#read 3, iclass 6, count 2 2006.245.07:40:12.64#ibcon#about to read 4, iclass 6, count 2 2006.245.07:40:12.64#ibcon#read 4, iclass 6, count 2 2006.245.07:40:12.64#ibcon#about to read 5, iclass 6, count 2 2006.245.07:40:12.64#ibcon#read 5, iclass 6, count 2 2006.245.07:40:12.64#ibcon#about to read 6, iclass 6, count 2 2006.245.07:40:12.64#ibcon#read 6, iclass 6, count 2 2006.245.07:40:12.64#ibcon#end of sib2, iclass 6, count 2 2006.245.07:40:12.64#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:40:12.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:40:12.64#ibcon#[27=AT02-04\r\n] 2006.245.07:40:12.64#ibcon#*before write, iclass 6, count 2 2006.245.07:40:12.64#ibcon#enter sib2, iclass 6, count 2 2006.245.07:40:12.64#ibcon#flushed, iclass 6, count 2 2006.245.07:40:12.64#ibcon#about to write, iclass 6, count 2 2006.245.07:40:12.64#ibcon#wrote, iclass 6, count 2 2006.245.07:40:12.64#ibcon#about to read 3, iclass 6, count 2 2006.245.07:40:12.67#ibcon#read 3, iclass 6, count 2 2006.245.07:40:12.67#ibcon#about to read 4, iclass 6, count 2 2006.245.07:40:12.67#ibcon#read 4, iclass 6, count 2 2006.245.07:40:12.67#ibcon#about to read 5, iclass 6, count 2 2006.245.07:40:12.67#ibcon#read 5, iclass 6, count 2 2006.245.07:40:12.67#ibcon#about to read 6, iclass 6, count 2 2006.245.07:40:12.67#ibcon#read 6, iclass 6, count 2 2006.245.07:40:12.67#ibcon#end of sib2, iclass 6, count 2 2006.245.07:40:12.67#ibcon#*after write, iclass 6, count 2 2006.245.07:40:12.67#ibcon#*before return 0, iclass 6, count 2 2006.245.07:40:12.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:40:12.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:40:12.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:40:12.67#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:12.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:40:12.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:40:12.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:40:12.79#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:40:12.79#ibcon#first serial, iclass 6, count 0 2006.245.07:40:12.79#ibcon#enter sib2, iclass 6, count 0 2006.245.07:40:12.79#ibcon#flushed, iclass 6, count 0 2006.245.07:40:12.79#ibcon#about to write, iclass 6, count 0 2006.245.07:40:12.79#ibcon#wrote, iclass 6, count 0 2006.245.07:40:12.79#ibcon#about to read 3, iclass 6, count 0 2006.245.07:40:12.81#ibcon#read 3, iclass 6, count 0 2006.245.07:40:12.81#ibcon#about to read 4, iclass 6, count 0 2006.245.07:40:12.81#ibcon#read 4, iclass 6, count 0 2006.245.07:40:12.81#ibcon#about to read 5, iclass 6, count 0 2006.245.07:40:12.81#ibcon#read 5, iclass 6, count 0 2006.245.07:40:12.81#ibcon#about to read 6, iclass 6, count 0 2006.245.07:40:12.81#ibcon#read 6, iclass 6, count 0 2006.245.07:40:12.81#ibcon#end of sib2, iclass 6, count 0 2006.245.07:40:12.81#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:40:12.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:40:12.81#ibcon#[27=USB\r\n] 2006.245.07:40:12.81#ibcon#*before write, iclass 6, count 0 2006.245.07:40:12.81#ibcon#enter sib2, iclass 6, count 0 2006.245.07:40:12.81#ibcon#flushed, iclass 6, count 0 2006.245.07:40:12.81#ibcon#about to write, iclass 6, count 0 2006.245.07:40:12.81#ibcon#wrote, iclass 6, count 0 2006.245.07:40:12.81#ibcon#about to read 3, iclass 6, count 0 2006.245.07:40:12.84#ibcon#read 3, iclass 6, count 0 2006.245.07:40:12.84#ibcon#about to read 4, iclass 6, count 0 2006.245.07:40:12.84#ibcon#read 4, iclass 6, count 0 2006.245.07:40:12.84#ibcon#about to read 5, iclass 6, count 0 2006.245.07:40:12.84#ibcon#read 5, iclass 6, count 0 2006.245.07:40:12.84#ibcon#about to read 6, iclass 6, count 0 2006.245.07:40:12.84#ibcon#read 6, iclass 6, count 0 2006.245.07:40:12.84#ibcon#end of sib2, iclass 6, count 0 2006.245.07:40:12.84#ibcon#*after write, iclass 6, count 0 2006.245.07:40:12.84#ibcon#*before return 0, iclass 6, count 0 2006.245.07:40:12.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:40:12.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:40:12.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:40:12.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:40:12.84$vc4f8/vblo=3,656.99 2006.245.07:40:12.84#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:40:12.84#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:40:12.84#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:12.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:40:12.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:40:12.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:40:12.84#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:40:12.84#ibcon#first serial, iclass 10, count 0 2006.245.07:40:12.84#ibcon#enter sib2, iclass 10, count 0 2006.245.07:40:12.84#ibcon#flushed, iclass 10, count 0 2006.245.07:40:12.84#ibcon#about to write, iclass 10, count 0 2006.245.07:40:12.84#ibcon#wrote, iclass 10, count 0 2006.245.07:40:12.84#ibcon#about to read 3, iclass 10, count 0 2006.245.07:40:12.86#ibcon#read 3, iclass 10, count 0 2006.245.07:40:12.86#ibcon#about to read 4, iclass 10, count 0 2006.245.07:40:12.86#ibcon#read 4, iclass 10, count 0 2006.245.07:40:12.86#ibcon#about to read 5, iclass 10, count 0 2006.245.07:40:12.86#ibcon#read 5, iclass 10, count 0 2006.245.07:40:12.86#ibcon#about to read 6, iclass 10, count 0 2006.245.07:40:12.86#ibcon#read 6, iclass 10, count 0 2006.245.07:40:12.86#ibcon#end of sib2, iclass 10, count 0 2006.245.07:40:12.86#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:40:12.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:40:12.86#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:40:12.86#ibcon#*before write, iclass 10, count 0 2006.245.07:40:12.86#ibcon#enter sib2, iclass 10, count 0 2006.245.07:40:12.86#ibcon#flushed, iclass 10, count 0 2006.245.07:40:12.86#ibcon#about to write, iclass 10, count 0 2006.245.07:40:12.86#ibcon#wrote, iclass 10, count 0 2006.245.07:40:12.86#ibcon#about to read 3, iclass 10, count 0 2006.245.07:40:12.91#ibcon#read 3, iclass 10, count 0 2006.245.07:40:12.91#ibcon#about to read 4, iclass 10, count 0 2006.245.07:40:12.91#ibcon#read 4, iclass 10, count 0 2006.245.07:40:12.91#ibcon#about to read 5, iclass 10, count 0 2006.245.07:40:12.91#ibcon#read 5, iclass 10, count 0 2006.245.07:40:12.91#ibcon#about to read 6, iclass 10, count 0 2006.245.07:40:12.91#ibcon#read 6, iclass 10, count 0 2006.245.07:40:12.91#ibcon#end of sib2, iclass 10, count 0 2006.245.07:40:12.91#ibcon#*after write, iclass 10, count 0 2006.245.07:40:12.91#ibcon#*before return 0, iclass 10, count 0 2006.245.07:40:12.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:40:12.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:40:12.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:40:12.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:40:12.91$vc4f8/vb=3,4 2006.245.07:40:12.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:40:12.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:40:12.91#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:12.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:40:12.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:40:12.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:40:12.96#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:40:12.96#ibcon#first serial, iclass 12, count 2 2006.245.07:40:12.96#ibcon#enter sib2, iclass 12, count 2 2006.245.07:40:12.96#ibcon#flushed, iclass 12, count 2 2006.245.07:40:12.96#ibcon#about to write, iclass 12, count 2 2006.245.07:40:12.96#ibcon#wrote, iclass 12, count 2 2006.245.07:40:12.96#ibcon#about to read 3, iclass 12, count 2 2006.245.07:40:12.98#ibcon#read 3, iclass 12, count 2 2006.245.07:40:12.98#ibcon#about to read 4, iclass 12, count 2 2006.245.07:40:12.98#ibcon#read 4, iclass 12, count 2 2006.245.07:40:12.98#ibcon#about to read 5, iclass 12, count 2 2006.245.07:40:12.98#ibcon#read 5, iclass 12, count 2 2006.245.07:40:12.98#ibcon#about to read 6, iclass 12, count 2 2006.245.07:40:12.98#ibcon#read 6, iclass 12, count 2 2006.245.07:40:12.98#ibcon#end of sib2, iclass 12, count 2 2006.245.07:40:12.98#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:40:12.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:40:12.98#ibcon#[27=AT03-04\r\n] 2006.245.07:40:12.98#ibcon#*before write, iclass 12, count 2 2006.245.07:40:12.98#ibcon#enter sib2, iclass 12, count 2 2006.245.07:40:12.98#ibcon#flushed, iclass 12, count 2 2006.245.07:40:12.98#ibcon#about to write, iclass 12, count 2 2006.245.07:40:12.98#ibcon#wrote, iclass 12, count 2 2006.245.07:40:12.98#ibcon#about to read 3, iclass 12, count 2 2006.245.07:40:13.01#ibcon#read 3, iclass 12, count 2 2006.245.07:40:13.01#ibcon#about to read 4, iclass 12, count 2 2006.245.07:40:13.01#ibcon#read 4, iclass 12, count 2 2006.245.07:40:13.01#ibcon#about to read 5, iclass 12, count 2 2006.245.07:40:13.01#ibcon#read 5, iclass 12, count 2 2006.245.07:40:13.01#ibcon#about to read 6, iclass 12, count 2 2006.245.07:40:13.01#ibcon#read 6, iclass 12, count 2 2006.245.07:40:13.01#ibcon#end of sib2, iclass 12, count 2 2006.245.07:40:13.01#ibcon#*after write, iclass 12, count 2 2006.245.07:40:13.01#ibcon#*before return 0, iclass 12, count 2 2006.245.07:40:13.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:40:13.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:40:13.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:40:13.01#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:13.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:40:13.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:40:13.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:40:13.13#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:40:13.13#ibcon#first serial, iclass 12, count 0 2006.245.07:40:13.13#ibcon#enter sib2, iclass 12, count 0 2006.245.07:40:13.13#ibcon#flushed, iclass 12, count 0 2006.245.07:40:13.13#ibcon#about to write, iclass 12, count 0 2006.245.07:40:13.13#ibcon#wrote, iclass 12, count 0 2006.245.07:40:13.13#ibcon#about to read 3, iclass 12, count 0 2006.245.07:40:13.15#ibcon#read 3, iclass 12, count 0 2006.245.07:40:13.15#ibcon#about to read 4, iclass 12, count 0 2006.245.07:40:13.15#ibcon#read 4, iclass 12, count 0 2006.245.07:40:13.15#ibcon#about to read 5, iclass 12, count 0 2006.245.07:40:13.15#ibcon#read 5, iclass 12, count 0 2006.245.07:40:13.15#ibcon#about to read 6, iclass 12, count 0 2006.245.07:40:13.15#ibcon#read 6, iclass 12, count 0 2006.245.07:40:13.15#ibcon#end of sib2, iclass 12, count 0 2006.245.07:40:13.15#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:40:13.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:40:13.15#ibcon#[27=USB\r\n] 2006.245.07:40:13.15#ibcon#*before write, iclass 12, count 0 2006.245.07:40:13.15#ibcon#enter sib2, iclass 12, count 0 2006.245.07:40:13.15#ibcon#flushed, iclass 12, count 0 2006.245.07:40:13.15#ibcon#about to write, iclass 12, count 0 2006.245.07:40:13.15#ibcon#wrote, iclass 12, count 0 2006.245.07:40:13.15#ibcon#about to read 3, iclass 12, count 0 2006.245.07:40:13.18#ibcon#read 3, iclass 12, count 0 2006.245.07:40:13.18#ibcon#about to read 4, iclass 12, count 0 2006.245.07:40:13.18#ibcon#read 4, iclass 12, count 0 2006.245.07:40:13.18#ibcon#about to read 5, iclass 12, count 0 2006.245.07:40:13.18#ibcon#read 5, iclass 12, count 0 2006.245.07:40:13.18#ibcon#about to read 6, iclass 12, count 0 2006.245.07:40:13.18#ibcon#read 6, iclass 12, count 0 2006.245.07:40:13.18#ibcon#end of sib2, iclass 12, count 0 2006.245.07:40:13.18#ibcon#*after write, iclass 12, count 0 2006.245.07:40:13.18#ibcon#*before return 0, iclass 12, count 0 2006.245.07:40:13.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:40:13.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:40:13.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:40:13.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:40:13.18$vc4f8/vblo=4,712.99 2006.245.07:40:13.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:40:13.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:40:13.18#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:13.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:13.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:13.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:13.18#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:40:13.18#ibcon#first serial, iclass 14, count 0 2006.245.07:40:13.18#ibcon#enter sib2, iclass 14, count 0 2006.245.07:40:13.18#ibcon#flushed, iclass 14, count 0 2006.245.07:40:13.18#ibcon#about to write, iclass 14, count 0 2006.245.07:40:13.18#ibcon#wrote, iclass 14, count 0 2006.245.07:40:13.18#ibcon#about to read 3, iclass 14, count 0 2006.245.07:40:13.20#ibcon#read 3, iclass 14, count 0 2006.245.07:40:13.20#ibcon#about to read 4, iclass 14, count 0 2006.245.07:40:13.20#ibcon#read 4, iclass 14, count 0 2006.245.07:40:13.20#ibcon#about to read 5, iclass 14, count 0 2006.245.07:40:13.20#ibcon#read 5, iclass 14, count 0 2006.245.07:40:13.20#ibcon#about to read 6, iclass 14, count 0 2006.245.07:40:13.20#ibcon#read 6, iclass 14, count 0 2006.245.07:40:13.20#ibcon#end of sib2, iclass 14, count 0 2006.245.07:40:13.20#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:40:13.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:40:13.20#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:40:13.20#ibcon#*before write, iclass 14, count 0 2006.245.07:40:13.20#ibcon#enter sib2, iclass 14, count 0 2006.245.07:40:13.20#ibcon#flushed, iclass 14, count 0 2006.245.07:40:13.20#ibcon#about to write, iclass 14, count 0 2006.245.07:40:13.20#ibcon#wrote, iclass 14, count 0 2006.245.07:40:13.20#ibcon#about to read 3, iclass 14, count 0 2006.245.07:40:13.24#ibcon#read 3, iclass 14, count 0 2006.245.07:40:13.24#ibcon#about to read 4, iclass 14, count 0 2006.245.07:40:13.24#ibcon#read 4, iclass 14, count 0 2006.245.07:40:13.24#ibcon#about to read 5, iclass 14, count 0 2006.245.07:40:13.24#ibcon#read 5, iclass 14, count 0 2006.245.07:40:13.24#ibcon#about to read 6, iclass 14, count 0 2006.245.07:40:13.24#ibcon#read 6, iclass 14, count 0 2006.245.07:40:13.24#ibcon#end of sib2, iclass 14, count 0 2006.245.07:40:13.24#ibcon#*after write, iclass 14, count 0 2006.245.07:40:13.24#ibcon#*before return 0, iclass 14, count 0 2006.245.07:40:13.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:13.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:40:13.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:40:13.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:40:13.24$vc4f8/vb=4,4 2006.245.07:40:13.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.07:40:13.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.07:40:13.24#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:13.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:13.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:13.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:13.30#ibcon#enter wrdev, iclass 16, count 2 2006.245.07:40:13.30#ibcon#first serial, iclass 16, count 2 2006.245.07:40:13.30#ibcon#enter sib2, iclass 16, count 2 2006.245.07:40:13.30#ibcon#flushed, iclass 16, count 2 2006.245.07:40:13.30#ibcon#about to write, iclass 16, count 2 2006.245.07:40:13.30#ibcon#wrote, iclass 16, count 2 2006.245.07:40:13.30#ibcon#about to read 3, iclass 16, count 2 2006.245.07:40:13.32#ibcon#read 3, iclass 16, count 2 2006.245.07:40:13.32#ibcon#about to read 4, iclass 16, count 2 2006.245.07:40:13.32#ibcon#read 4, iclass 16, count 2 2006.245.07:40:13.32#ibcon#about to read 5, iclass 16, count 2 2006.245.07:40:13.32#ibcon#read 5, iclass 16, count 2 2006.245.07:40:13.32#ibcon#about to read 6, iclass 16, count 2 2006.245.07:40:13.32#ibcon#read 6, iclass 16, count 2 2006.245.07:40:13.32#ibcon#end of sib2, iclass 16, count 2 2006.245.07:40:13.32#ibcon#*mode == 0, iclass 16, count 2 2006.245.07:40:13.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.07:40:13.32#ibcon#[27=AT04-04\r\n] 2006.245.07:40:13.32#ibcon#*before write, iclass 16, count 2 2006.245.07:40:13.32#ibcon#enter sib2, iclass 16, count 2 2006.245.07:40:13.32#ibcon#flushed, iclass 16, count 2 2006.245.07:40:13.32#ibcon#about to write, iclass 16, count 2 2006.245.07:40:13.32#ibcon#wrote, iclass 16, count 2 2006.245.07:40:13.32#ibcon#about to read 3, iclass 16, count 2 2006.245.07:40:13.35#ibcon#read 3, iclass 16, count 2 2006.245.07:40:13.35#ibcon#about to read 4, iclass 16, count 2 2006.245.07:40:13.35#ibcon#read 4, iclass 16, count 2 2006.245.07:40:13.35#ibcon#about to read 5, iclass 16, count 2 2006.245.07:40:13.35#ibcon#read 5, iclass 16, count 2 2006.245.07:40:13.35#ibcon#about to read 6, iclass 16, count 2 2006.245.07:40:13.35#ibcon#read 6, iclass 16, count 2 2006.245.07:40:13.35#ibcon#end of sib2, iclass 16, count 2 2006.245.07:40:13.35#ibcon#*after write, iclass 16, count 2 2006.245.07:40:13.35#ibcon#*before return 0, iclass 16, count 2 2006.245.07:40:13.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:13.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:40:13.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.07:40:13.35#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:13.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:13.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:13.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:13.47#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:40:13.47#ibcon#first serial, iclass 16, count 0 2006.245.07:40:13.47#ibcon#enter sib2, iclass 16, count 0 2006.245.07:40:13.47#ibcon#flushed, iclass 16, count 0 2006.245.07:40:13.47#ibcon#about to write, iclass 16, count 0 2006.245.07:40:13.47#ibcon#wrote, iclass 16, count 0 2006.245.07:40:13.47#ibcon#about to read 3, iclass 16, count 0 2006.245.07:40:13.49#ibcon#read 3, iclass 16, count 0 2006.245.07:40:13.49#ibcon#about to read 4, iclass 16, count 0 2006.245.07:40:13.49#ibcon#read 4, iclass 16, count 0 2006.245.07:40:13.49#ibcon#about to read 5, iclass 16, count 0 2006.245.07:40:13.49#ibcon#read 5, iclass 16, count 0 2006.245.07:40:13.49#ibcon#about to read 6, iclass 16, count 0 2006.245.07:40:13.49#ibcon#read 6, iclass 16, count 0 2006.245.07:40:13.49#ibcon#end of sib2, iclass 16, count 0 2006.245.07:40:13.49#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:40:13.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:40:13.49#ibcon#[27=USB\r\n] 2006.245.07:40:13.49#ibcon#*before write, iclass 16, count 0 2006.245.07:40:13.49#ibcon#enter sib2, iclass 16, count 0 2006.245.07:40:13.49#ibcon#flushed, iclass 16, count 0 2006.245.07:40:13.49#ibcon#about to write, iclass 16, count 0 2006.245.07:40:13.49#ibcon#wrote, iclass 16, count 0 2006.245.07:40:13.49#ibcon#about to read 3, iclass 16, count 0 2006.245.07:40:13.52#ibcon#read 3, iclass 16, count 0 2006.245.07:40:13.52#ibcon#about to read 4, iclass 16, count 0 2006.245.07:40:13.52#ibcon#read 4, iclass 16, count 0 2006.245.07:40:13.52#ibcon#about to read 5, iclass 16, count 0 2006.245.07:40:13.52#ibcon#read 5, iclass 16, count 0 2006.245.07:40:13.52#ibcon#about to read 6, iclass 16, count 0 2006.245.07:40:13.52#ibcon#read 6, iclass 16, count 0 2006.245.07:40:13.52#ibcon#end of sib2, iclass 16, count 0 2006.245.07:40:13.52#ibcon#*after write, iclass 16, count 0 2006.245.07:40:13.52#ibcon#*before return 0, iclass 16, count 0 2006.245.07:40:13.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:13.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:40:13.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:40:13.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:40:13.52$vc4f8/vblo=5,744.99 2006.245.07:40:13.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.07:40:13.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.07:40:13.52#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:13.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:13.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:13.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:13.52#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:40:13.52#ibcon#first serial, iclass 18, count 0 2006.245.07:40:13.52#ibcon#enter sib2, iclass 18, count 0 2006.245.07:40:13.52#ibcon#flushed, iclass 18, count 0 2006.245.07:40:13.52#ibcon#about to write, iclass 18, count 0 2006.245.07:40:13.52#ibcon#wrote, iclass 18, count 0 2006.245.07:40:13.52#ibcon#about to read 3, iclass 18, count 0 2006.245.07:40:13.54#ibcon#read 3, iclass 18, count 0 2006.245.07:40:13.54#ibcon#about to read 4, iclass 18, count 0 2006.245.07:40:13.54#ibcon#read 4, iclass 18, count 0 2006.245.07:40:13.54#ibcon#about to read 5, iclass 18, count 0 2006.245.07:40:13.54#ibcon#read 5, iclass 18, count 0 2006.245.07:40:13.54#ibcon#about to read 6, iclass 18, count 0 2006.245.07:40:13.54#ibcon#read 6, iclass 18, count 0 2006.245.07:40:13.54#ibcon#end of sib2, iclass 18, count 0 2006.245.07:40:13.54#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:40:13.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:40:13.54#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:40:13.54#ibcon#*before write, iclass 18, count 0 2006.245.07:40:13.54#ibcon#enter sib2, iclass 18, count 0 2006.245.07:40:13.54#ibcon#flushed, iclass 18, count 0 2006.245.07:40:13.54#ibcon#about to write, iclass 18, count 0 2006.245.07:40:13.54#ibcon#wrote, iclass 18, count 0 2006.245.07:40:13.54#ibcon#about to read 3, iclass 18, count 0 2006.245.07:40:13.58#ibcon#read 3, iclass 18, count 0 2006.245.07:40:13.58#ibcon#about to read 4, iclass 18, count 0 2006.245.07:40:13.58#ibcon#read 4, iclass 18, count 0 2006.245.07:40:13.58#ibcon#about to read 5, iclass 18, count 0 2006.245.07:40:13.58#ibcon#read 5, iclass 18, count 0 2006.245.07:40:13.58#ibcon#about to read 6, iclass 18, count 0 2006.245.07:40:13.58#ibcon#read 6, iclass 18, count 0 2006.245.07:40:13.58#ibcon#end of sib2, iclass 18, count 0 2006.245.07:40:13.58#ibcon#*after write, iclass 18, count 0 2006.245.07:40:13.58#ibcon#*before return 0, iclass 18, count 0 2006.245.07:40:13.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:13.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:40:13.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:40:13.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:40:13.58$vc4f8/vb=5,3 2006.245.07:40:13.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.07:40:13.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.07:40:13.58#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:13.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:13.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:13.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:13.64#ibcon#enter wrdev, iclass 20, count 2 2006.245.07:40:13.64#ibcon#first serial, iclass 20, count 2 2006.245.07:40:13.64#ibcon#enter sib2, iclass 20, count 2 2006.245.07:40:13.64#ibcon#flushed, iclass 20, count 2 2006.245.07:40:13.64#ibcon#about to write, iclass 20, count 2 2006.245.07:40:13.64#ibcon#wrote, iclass 20, count 2 2006.245.07:40:13.64#ibcon#about to read 3, iclass 20, count 2 2006.245.07:40:13.66#ibcon#read 3, iclass 20, count 2 2006.245.07:40:13.66#ibcon#about to read 4, iclass 20, count 2 2006.245.07:40:13.66#ibcon#read 4, iclass 20, count 2 2006.245.07:40:13.66#ibcon#about to read 5, iclass 20, count 2 2006.245.07:40:13.66#ibcon#read 5, iclass 20, count 2 2006.245.07:40:13.66#ibcon#about to read 6, iclass 20, count 2 2006.245.07:40:13.66#ibcon#read 6, iclass 20, count 2 2006.245.07:40:13.66#ibcon#end of sib2, iclass 20, count 2 2006.245.07:40:13.66#ibcon#*mode == 0, iclass 20, count 2 2006.245.07:40:13.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.07:40:13.66#ibcon#[27=AT05-03\r\n] 2006.245.07:40:13.66#ibcon#*before write, iclass 20, count 2 2006.245.07:40:13.66#ibcon#enter sib2, iclass 20, count 2 2006.245.07:40:13.66#ibcon#flushed, iclass 20, count 2 2006.245.07:40:13.66#ibcon#about to write, iclass 20, count 2 2006.245.07:40:13.66#ibcon#wrote, iclass 20, count 2 2006.245.07:40:13.66#ibcon#about to read 3, iclass 20, count 2 2006.245.07:40:13.69#ibcon#read 3, iclass 20, count 2 2006.245.07:40:13.69#ibcon#about to read 4, iclass 20, count 2 2006.245.07:40:13.69#ibcon#read 4, iclass 20, count 2 2006.245.07:40:13.69#ibcon#about to read 5, iclass 20, count 2 2006.245.07:40:13.69#ibcon#read 5, iclass 20, count 2 2006.245.07:40:13.69#ibcon#about to read 6, iclass 20, count 2 2006.245.07:40:13.69#ibcon#read 6, iclass 20, count 2 2006.245.07:40:13.69#ibcon#end of sib2, iclass 20, count 2 2006.245.07:40:13.69#ibcon#*after write, iclass 20, count 2 2006.245.07:40:13.69#ibcon#*before return 0, iclass 20, count 2 2006.245.07:40:13.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:13.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:40:13.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.07:40:13.69#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:13.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:13.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:13.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:13.81#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:40:13.81#ibcon#first serial, iclass 20, count 0 2006.245.07:40:13.81#ibcon#enter sib2, iclass 20, count 0 2006.245.07:40:13.81#ibcon#flushed, iclass 20, count 0 2006.245.07:40:13.81#ibcon#about to write, iclass 20, count 0 2006.245.07:40:13.81#ibcon#wrote, iclass 20, count 0 2006.245.07:40:13.81#ibcon#about to read 3, iclass 20, count 0 2006.245.07:40:13.83#ibcon#read 3, iclass 20, count 0 2006.245.07:40:13.83#ibcon#about to read 4, iclass 20, count 0 2006.245.07:40:13.83#ibcon#read 4, iclass 20, count 0 2006.245.07:40:13.83#ibcon#about to read 5, iclass 20, count 0 2006.245.07:40:13.83#ibcon#read 5, iclass 20, count 0 2006.245.07:40:13.83#ibcon#about to read 6, iclass 20, count 0 2006.245.07:40:13.83#ibcon#read 6, iclass 20, count 0 2006.245.07:40:13.83#ibcon#end of sib2, iclass 20, count 0 2006.245.07:40:13.83#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:40:13.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:40:13.83#ibcon#[27=USB\r\n] 2006.245.07:40:13.83#ibcon#*before write, iclass 20, count 0 2006.245.07:40:13.83#ibcon#enter sib2, iclass 20, count 0 2006.245.07:40:13.83#ibcon#flushed, iclass 20, count 0 2006.245.07:40:13.83#ibcon#about to write, iclass 20, count 0 2006.245.07:40:13.83#ibcon#wrote, iclass 20, count 0 2006.245.07:40:13.83#ibcon#about to read 3, iclass 20, count 0 2006.245.07:40:13.86#ibcon#read 3, iclass 20, count 0 2006.245.07:40:13.86#ibcon#about to read 4, iclass 20, count 0 2006.245.07:40:13.86#ibcon#read 4, iclass 20, count 0 2006.245.07:40:13.86#ibcon#about to read 5, iclass 20, count 0 2006.245.07:40:13.86#ibcon#read 5, iclass 20, count 0 2006.245.07:40:13.86#ibcon#about to read 6, iclass 20, count 0 2006.245.07:40:13.86#ibcon#read 6, iclass 20, count 0 2006.245.07:40:13.86#ibcon#end of sib2, iclass 20, count 0 2006.245.07:40:13.86#ibcon#*after write, iclass 20, count 0 2006.245.07:40:13.86#ibcon#*before return 0, iclass 20, count 0 2006.245.07:40:13.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:13.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:40:13.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:40:13.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:40:13.86$vc4f8/vblo=6,752.99 2006.245.07:40:13.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.07:40:13.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.07:40:13.86#ibcon#ireg 17 cls_cnt 0 2006.245.07:40:13.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:13.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:13.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:13.86#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:40:13.86#ibcon#first serial, iclass 22, count 0 2006.245.07:40:13.86#ibcon#enter sib2, iclass 22, count 0 2006.245.07:40:13.86#ibcon#flushed, iclass 22, count 0 2006.245.07:40:13.86#ibcon#about to write, iclass 22, count 0 2006.245.07:40:13.86#ibcon#wrote, iclass 22, count 0 2006.245.07:40:13.86#ibcon#about to read 3, iclass 22, count 0 2006.245.07:40:13.88#ibcon#read 3, iclass 22, count 0 2006.245.07:40:13.88#ibcon#about to read 4, iclass 22, count 0 2006.245.07:40:13.88#ibcon#read 4, iclass 22, count 0 2006.245.07:40:13.88#ibcon#about to read 5, iclass 22, count 0 2006.245.07:40:13.88#ibcon#read 5, iclass 22, count 0 2006.245.07:40:13.88#ibcon#about to read 6, iclass 22, count 0 2006.245.07:40:13.88#ibcon#read 6, iclass 22, count 0 2006.245.07:40:13.88#ibcon#end of sib2, iclass 22, count 0 2006.245.07:40:13.88#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:40:13.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:40:13.88#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:40:13.88#ibcon#*before write, iclass 22, count 0 2006.245.07:40:13.88#ibcon#enter sib2, iclass 22, count 0 2006.245.07:40:13.88#ibcon#flushed, iclass 22, count 0 2006.245.07:40:13.88#ibcon#about to write, iclass 22, count 0 2006.245.07:40:13.88#ibcon#wrote, iclass 22, count 0 2006.245.07:40:13.88#ibcon#about to read 3, iclass 22, count 0 2006.245.07:40:13.93#ibcon#read 3, iclass 22, count 0 2006.245.07:40:13.93#ibcon#about to read 4, iclass 22, count 0 2006.245.07:40:13.93#ibcon#read 4, iclass 22, count 0 2006.245.07:40:13.93#ibcon#about to read 5, iclass 22, count 0 2006.245.07:40:13.93#ibcon#read 5, iclass 22, count 0 2006.245.07:40:13.93#ibcon#about to read 6, iclass 22, count 0 2006.245.07:40:13.93#ibcon#read 6, iclass 22, count 0 2006.245.07:40:13.93#ibcon#end of sib2, iclass 22, count 0 2006.245.07:40:13.93#ibcon#*after write, iclass 22, count 0 2006.245.07:40:13.93#ibcon#*before return 0, iclass 22, count 0 2006.245.07:40:13.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:13.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:40:13.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:40:13.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:40:13.93$vc4f8/vb=6,3 2006.245.07:40:13.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.07:40:13.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.07:40:13.93#ibcon#ireg 11 cls_cnt 2 2006.245.07:40:13.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:13.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:13.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:13.98#ibcon#enter wrdev, iclass 24, count 2 2006.245.07:40:13.98#ibcon#first serial, iclass 24, count 2 2006.245.07:40:13.98#ibcon#enter sib2, iclass 24, count 2 2006.245.07:40:13.98#ibcon#flushed, iclass 24, count 2 2006.245.07:40:13.98#ibcon#about to write, iclass 24, count 2 2006.245.07:40:13.98#ibcon#wrote, iclass 24, count 2 2006.245.07:40:13.98#ibcon#about to read 3, iclass 24, count 2 2006.245.07:40:14.00#ibcon#read 3, iclass 24, count 2 2006.245.07:40:14.00#ibcon#about to read 4, iclass 24, count 2 2006.245.07:40:14.00#ibcon#read 4, iclass 24, count 2 2006.245.07:40:14.00#ibcon#about to read 5, iclass 24, count 2 2006.245.07:40:14.00#ibcon#read 5, iclass 24, count 2 2006.245.07:40:14.00#ibcon#about to read 6, iclass 24, count 2 2006.245.07:40:14.00#ibcon#read 6, iclass 24, count 2 2006.245.07:40:14.00#ibcon#end of sib2, iclass 24, count 2 2006.245.07:40:14.00#ibcon#*mode == 0, iclass 24, count 2 2006.245.07:40:14.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.07:40:14.00#ibcon#[27=AT06-03\r\n] 2006.245.07:40:14.00#ibcon#*before write, iclass 24, count 2 2006.245.07:40:14.00#ibcon#enter sib2, iclass 24, count 2 2006.245.07:40:14.00#ibcon#flushed, iclass 24, count 2 2006.245.07:40:14.00#ibcon#about to write, iclass 24, count 2 2006.245.07:40:14.00#ibcon#wrote, iclass 24, count 2 2006.245.07:40:14.00#ibcon#about to read 3, iclass 24, count 2 2006.245.07:40:14.03#ibcon#read 3, iclass 24, count 2 2006.245.07:40:14.03#ibcon#about to read 4, iclass 24, count 2 2006.245.07:40:14.03#ibcon#read 4, iclass 24, count 2 2006.245.07:40:14.03#ibcon#about to read 5, iclass 24, count 2 2006.245.07:40:14.03#ibcon#read 5, iclass 24, count 2 2006.245.07:40:14.03#ibcon#about to read 6, iclass 24, count 2 2006.245.07:40:14.03#ibcon#read 6, iclass 24, count 2 2006.245.07:40:14.03#ibcon#end of sib2, iclass 24, count 2 2006.245.07:40:14.03#ibcon#*after write, iclass 24, count 2 2006.245.07:40:14.03#ibcon#*before return 0, iclass 24, count 2 2006.245.07:40:14.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:14.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:40:14.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.07:40:14.03#ibcon#ireg 7 cls_cnt 0 2006.245.07:40:14.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:14.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:14.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:14.15#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:40:14.15#ibcon#first serial, iclass 24, count 0 2006.245.07:40:14.15#ibcon#enter sib2, iclass 24, count 0 2006.245.07:40:14.15#ibcon#flushed, iclass 24, count 0 2006.245.07:40:14.15#ibcon#about to write, iclass 24, count 0 2006.245.07:40:14.15#ibcon#wrote, iclass 24, count 0 2006.245.07:40:14.15#ibcon#about to read 3, iclass 24, count 0 2006.245.07:40:14.17#ibcon#read 3, iclass 24, count 0 2006.245.07:40:14.17#ibcon#about to read 4, iclass 24, count 0 2006.245.07:40:14.17#ibcon#read 4, iclass 24, count 0 2006.245.07:40:14.17#ibcon#about to read 5, iclass 24, count 0 2006.245.07:40:14.17#ibcon#read 5, iclass 24, count 0 2006.245.07:40:14.17#ibcon#about to read 6, iclass 24, count 0 2006.245.07:40:14.17#ibcon#read 6, iclass 24, count 0 2006.245.07:40:14.17#ibcon#end of sib2, iclass 24, count 0 2006.245.07:40:14.17#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:40:14.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:40:14.17#ibcon#[27=USB\r\n] 2006.245.07:40:14.17#ibcon#*before write, iclass 24, count 0 2006.245.07:40:14.17#ibcon#enter sib2, iclass 24, count 0 2006.245.07:40:14.17#ibcon#flushed, iclass 24, count 0 2006.245.07:40:14.17#ibcon#about to write, iclass 24, count 0 2006.245.07:40:14.17#ibcon#wrote, iclass 24, count 0 2006.245.07:40:14.17#ibcon#about to read 3, iclass 24, count 0 2006.245.07:40:14.20#ibcon#read 3, iclass 24, count 0 2006.245.07:40:14.20#ibcon#about to read 4, iclass 24, count 0 2006.245.07:40:14.20#ibcon#read 4, iclass 24, count 0 2006.245.07:40:14.20#ibcon#about to read 5, iclass 24, count 0 2006.245.07:40:14.20#ibcon#read 5, iclass 24, count 0 2006.245.07:40:14.20#ibcon#about to read 6, iclass 24, count 0 2006.245.07:40:14.20#ibcon#read 6, iclass 24, count 0 2006.245.07:40:14.20#ibcon#end of sib2, iclass 24, count 0 2006.245.07:40:14.20#ibcon#*after write, iclass 24, count 0 2006.245.07:40:14.20#ibcon#*before return 0, iclass 24, count 0 2006.245.07:40:14.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:14.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:40:14.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:40:14.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:40:14.20$vc4f8/vabw=wide 2006.245.07:40:14.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.07:40:14.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.07:40:14.20#ibcon#ireg 8 cls_cnt 0 2006.245.07:40:14.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:14.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:14.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:14.20#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:40:14.20#ibcon#first serial, iclass 26, count 0 2006.245.07:40:14.20#ibcon#enter sib2, iclass 26, count 0 2006.245.07:40:14.20#ibcon#flushed, iclass 26, count 0 2006.245.07:40:14.20#ibcon#about to write, iclass 26, count 0 2006.245.07:40:14.20#ibcon#wrote, iclass 26, count 0 2006.245.07:40:14.20#ibcon#about to read 3, iclass 26, count 0 2006.245.07:40:14.22#ibcon#read 3, iclass 26, count 0 2006.245.07:40:14.22#ibcon#about to read 4, iclass 26, count 0 2006.245.07:40:14.22#ibcon#read 4, iclass 26, count 0 2006.245.07:40:14.22#ibcon#about to read 5, iclass 26, count 0 2006.245.07:40:14.22#ibcon#read 5, iclass 26, count 0 2006.245.07:40:14.22#ibcon#about to read 6, iclass 26, count 0 2006.245.07:40:14.22#ibcon#read 6, iclass 26, count 0 2006.245.07:40:14.22#ibcon#end of sib2, iclass 26, count 0 2006.245.07:40:14.22#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:40:14.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:40:14.22#ibcon#[25=BW32\r\n] 2006.245.07:40:14.22#ibcon#*before write, iclass 26, count 0 2006.245.07:40:14.22#ibcon#enter sib2, iclass 26, count 0 2006.245.07:40:14.22#ibcon#flushed, iclass 26, count 0 2006.245.07:40:14.22#ibcon#about to write, iclass 26, count 0 2006.245.07:40:14.22#ibcon#wrote, iclass 26, count 0 2006.245.07:40:14.22#ibcon#about to read 3, iclass 26, count 0 2006.245.07:40:14.25#ibcon#read 3, iclass 26, count 0 2006.245.07:40:14.25#ibcon#about to read 4, iclass 26, count 0 2006.245.07:40:14.25#ibcon#read 4, iclass 26, count 0 2006.245.07:40:14.25#ibcon#about to read 5, iclass 26, count 0 2006.245.07:40:14.25#ibcon#read 5, iclass 26, count 0 2006.245.07:40:14.25#ibcon#about to read 6, iclass 26, count 0 2006.245.07:40:14.25#ibcon#read 6, iclass 26, count 0 2006.245.07:40:14.25#ibcon#end of sib2, iclass 26, count 0 2006.245.07:40:14.25#ibcon#*after write, iclass 26, count 0 2006.245.07:40:14.25#ibcon#*before return 0, iclass 26, count 0 2006.245.07:40:14.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:14.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:40:14.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:40:14.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:40:14.25$vc4f8/vbbw=wide 2006.245.07:40:14.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:40:14.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:40:14.25#ibcon#ireg 8 cls_cnt 0 2006.245.07:40:14.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:40:14.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:40:14.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:40:14.32#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:40:14.32#ibcon#first serial, iclass 28, count 0 2006.245.07:40:14.32#ibcon#enter sib2, iclass 28, count 0 2006.245.07:40:14.32#ibcon#flushed, iclass 28, count 0 2006.245.07:40:14.32#ibcon#about to write, iclass 28, count 0 2006.245.07:40:14.32#ibcon#wrote, iclass 28, count 0 2006.245.07:40:14.32#ibcon#about to read 3, iclass 28, count 0 2006.245.07:40:14.34#ibcon#read 3, iclass 28, count 0 2006.245.07:40:14.34#ibcon#about to read 4, iclass 28, count 0 2006.245.07:40:14.34#ibcon#read 4, iclass 28, count 0 2006.245.07:40:14.34#ibcon#about to read 5, iclass 28, count 0 2006.245.07:40:14.34#ibcon#read 5, iclass 28, count 0 2006.245.07:40:14.34#ibcon#about to read 6, iclass 28, count 0 2006.245.07:40:14.34#ibcon#read 6, iclass 28, count 0 2006.245.07:40:14.34#ibcon#end of sib2, iclass 28, count 0 2006.245.07:40:14.34#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:40:14.34#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:40:14.34#ibcon#[27=BW32\r\n] 2006.245.07:40:14.34#ibcon#*before write, iclass 28, count 0 2006.245.07:40:14.34#ibcon#enter sib2, iclass 28, count 0 2006.245.07:40:14.34#ibcon#flushed, iclass 28, count 0 2006.245.07:40:14.34#ibcon#about to write, iclass 28, count 0 2006.245.07:40:14.34#ibcon#wrote, iclass 28, count 0 2006.245.07:40:14.34#ibcon#about to read 3, iclass 28, count 0 2006.245.07:40:14.37#ibcon#read 3, iclass 28, count 0 2006.245.07:40:14.37#ibcon#about to read 4, iclass 28, count 0 2006.245.07:40:14.37#ibcon#read 4, iclass 28, count 0 2006.245.07:40:14.37#ibcon#about to read 5, iclass 28, count 0 2006.245.07:40:14.37#ibcon#read 5, iclass 28, count 0 2006.245.07:40:14.37#ibcon#about to read 6, iclass 28, count 0 2006.245.07:40:14.37#ibcon#read 6, iclass 28, count 0 2006.245.07:40:14.37#ibcon#end of sib2, iclass 28, count 0 2006.245.07:40:14.37#ibcon#*after write, iclass 28, count 0 2006.245.07:40:14.37#ibcon#*before return 0, iclass 28, count 0 2006.245.07:40:14.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:40:14.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:40:14.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:40:14.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:40:14.37$4f8m12a/ifd4f 2006.245.07:40:14.37$ifd4f/lo= 2006.245.07:40:14.37$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:40:14.37$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:40:14.37$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:40:14.37$ifd4f/patch= 2006.245.07:40:14.37$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:40:14.37$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:40:14.37$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:40:14.37$4f8m12a/"form=m,16.000,1:2 2006.245.07:40:14.37$4f8m12a/"tpicd 2006.245.07:40:14.37$4f8m12a/echo=off 2006.245.07:40:14.37$4f8m12a/xlog=off 2006.245.07:40:14.37:!2006.245.07:40:50 2006.245.07:40:33.14#trakl#Source acquired 2006.245.07:40:34.14#flagr#flagr/antenna,acquired 2006.245.07:40:50.00:preob 2006.245.07:40:50.14/onsource/TRACKING 2006.245.07:40:50.14:!2006.245.07:41:00 2006.245.07:41:00.00:data_valid=on 2006.245.07:41:00.00:midob 2006.245.07:41:01.14/onsource/TRACKING 2006.245.07:41:01.14/wx/27.51,1004.4,67 2006.245.07:41:01.22/cable/+6.4117E-03 2006.245.07:41:02.31/va/01,08,usb,yes,31,32 2006.245.07:41:02.31/va/02,07,usb,yes,30,32 2006.245.07:41:02.31/va/03,06,usb,yes,32,33 2006.245.07:41:02.31/va/04,07,usb,yes,31,34 2006.245.07:41:02.31/va/05,07,usb,yes,33,35 2006.245.07:41:02.31/va/06,07,usb,yes,29,29 2006.245.07:41:02.31/va/07,07,usb,yes,29,28 2006.245.07:41:02.31/va/08,08,usb,yes,25,25 2006.245.07:41:02.54/valo/01,532.99,yes,locked 2006.245.07:41:02.54/valo/02,572.99,yes,locked 2006.245.07:41:02.54/valo/03,672.99,yes,locked 2006.245.07:41:02.54/valo/04,832.99,yes,locked 2006.245.07:41:02.54/valo/05,652.99,yes,locked 2006.245.07:41:02.54/valo/06,772.99,yes,locked 2006.245.07:41:02.54/valo/07,832.99,yes,locked 2006.245.07:41:02.54/valo/08,852.99,yes,locked 2006.245.07:41:03.63/vb/01,04,usb,yes,30,29 2006.245.07:41:03.63/vb/02,04,usb,yes,32,33 2006.245.07:41:03.63/vb/03,04,usb,yes,28,32 2006.245.07:41:03.63/vb/04,04,usb,yes,29,29 2006.245.07:41:03.63/vb/05,03,usb,yes,34,39 2006.245.07:41:03.63/vb/06,03,usb,yes,35,39 2006.245.07:41:03.63/vb/07,04,usb,yes,31,31 2006.245.07:41:03.63/vb/08,03,usb,yes,35,39 2006.245.07:41:03.86/vblo/01,632.99,yes,locked 2006.245.07:41:03.86/vblo/02,640.99,yes,locked 2006.245.07:41:03.86/vblo/03,656.99,yes,locked 2006.245.07:41:03.86/vblo/04,712.99,yes,locked 2006.245.07:41:03.86/vblo/05,744.99,yes,locked 2006.245.07:41:03.86/vblo/06,752.99,yes,locked 2006.245.07:41:03.86/vblo/07,734.99,yes,locked 2006.245.07:41:03.86/vblo/08,744.99,yes,locked 2006.245.07:41:04.01/vabw/8 2006.245.07:41:04.16/vbbw/8 2006.245.07:41:04.25/xfe/off,on,13.0 2006.245.07:41:04.63/ifatt/23,28,28,28 2006.245.07:41:05.08/fmout-gps/S +4.45E-07 2006.245.07:41:05.12:!2006.245.07:42:00 2006.245.07:42:00.00:data_valid=off 2006.245.07:42:00.00:postob 2006.245.07:42:00.10/cable/+6.4109E-03 2006.245.07:42:00.10/wx/27.49,1004.4,67 2006.245.07:42:01.08/fmout-gps/S +4.45E-07 2006.245.07:42:01.08:scan_name=245-0742,k06245,60 2006.245.07:42:01.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.245.07:42:01.14#flagr#flagr/antenna,new-source 2006.245.07:42:02.14:checkk5 2006.245.07:42:02.70/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:42:03.14/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:42:04.03/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:42:04.47/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:42:05.10/chk_obsdata//k5ts1/T2450741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:42:05.51/chk_obsdata//k5ts2/T2450741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:42:05.93/chk_obsdata//k5ts3/T2450741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:42:06.39/chk_obsdata//k5ts4/T2450741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:42:07.25/k5log//k5ts1_log_newline 2006.245.07:42:08.47/k5log//k5ts2_log_newline 2006.245.07:42:09.47/k5log//k5ts3_log_newline 2006.245.07:42:10.57/k5log//k5ts4_log_newline 2006.245.07:42:10.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:42:10.59:4f8m12a=1 2006.245.07:42:10.59$4f8m12a/echo=on 2006.245.07:42:10.59$4f8m12a/pcalon 2006.245.07:42:10.60$pcalon/"no phase cal control is implemented here 2006.245.07:42:10.60$4f8m12a/"tpicd=stop 2006.245.07:42:10.60$4f8m12a/vc4f8 2006.245.07:42:10.60$vc4f8/valo=1,532.99 2006.245.07:42:10.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:42:10.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:42:10.60#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:10.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:10.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:10.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:10.60#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:42:10.60#ibcon#first serial, iclass 34, count 0 2006.245.07:42:10.60#ibcon#enter sib2, iclass 34, count 0 2006.245.07:42:10.60#ibcon#flushed, iclass 34, count 0 2006.245.07:42:10.60#ibcon#about to write, iclass 34, count 0 2006.245.07:42:10.60#ibcon#wrote, iclass 34, count 0 2006.245.07:42:10.60#ibcon#about to read 3, iclass 34, count 0 2006.245.07:42:10.64#ibcon#read 3, iclass 34, count 0 2006.245.07:42:10.64#ibcon#about to read 4, iclass 34, count 0 2006.245.07:42:10.64#ibcon#read 4, iclass 34, count 0 2006.245.07:42:10.64#ibcon#about to read 5, iclass 34, count 0 2006.245.07:42:10.64#ibcon#read 5, iclass 34, count 0 2006.245.07:42:10.64#ibcon#about to read 6, iclass 34, count 0 2006.245.07:42:10.64#ibcon#read 6, iclass 34, count 0 2006.245.07:42:10.64#ibcon#end of sib2, iclass 34, count 0 2006.245.07:42:10.64#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:42:10.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:42:10.64#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:42:10.64#ibcon#*before write, iclass 34, count 0 2006.245.07:42:10.64#ibcon#enter sib2, iclass 34, count 0 2006.245.07:42:10.64#ibcon#flushed, iclass 34, count 0 2006.245.07:42:10.64#ibcon#about to write, iclass 34, count 0 2006.245.07:42:10.64#ibcon#wrote, iclass 34, count 0 2006.245.07:42:10.64#ibcon#about to read 3, iclass 34, count 0 2006.245.07:42:10.69#ibcon#read 3, iclass 34, count 0 2006.245.07:42:10.69#ibcon#about to read 4, iclass 34, count 0 2006.245.07:42:10.69#ibcon#read 4, iclass 34, count 0 2006.245.07:42:10.69#ibcon#about to read 5, iclass 34, count 0 2006.245.07:42:10.69#ibcon#read 5, iclass 34, count 0 2006.245.07:42:10.69#ibcon#about to read 6, iclass 34, count 0 2006.245.07:42:10.69#ibcon#read 6, iclass 34, count 0 2006.245.07:42:10.69#ibcon#end of sib2, iclass 34, count 0 2006.245.07:42:10.69#ibcon#*after write, iclass 34, count 0 2006.245.07:42:10.69#ibcon#*before return 0, iclass 34, count 0 2006.245.07:42:10.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:10.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:10.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:42:10.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:42:10.69$vc4f8/va=1,8 2006.245.07:42:10.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:42:10.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:42:10.69#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:10.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:10.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:10.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:10.69#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:42:10.69#ibcon#first serial, iclass 36, count 2 2006.245.07:42:10.69#ibcon#enter sib2, iclass 36, count 2 2006.245.07:42:10.69#ibcon#flushed, iclass 36, count 2 2006.245.07:42:10.69#ibcon#about to write, iclass 36, count 2 2006.245.07:42:10.69#ibcon#wrote, iclass 36, count 2 2006.245.07:42:10.69#ibcon#about to read 3, iclass 36, count 2 2006.245.07:42:10.71#ibcon#read 3, iclass 36, count 2 2006.245.07:42:10.71#ibcon#about to read 4, iclass 36, count 2 2006.245.07:42:10.71#ibcon#read 4, iclass 36, count 2 2006.245.07:42:10.71#ibcon#about to read 5, iclass 36, count 2 2006.245.07:42:10.71#ibcon#read 5, iclass 36, count 2 2006.245.07:42:10.71#ibcon#about to read 6, iclass 36, count 2 2006.245.07:42:10.71#ibcon#read 6, iclass 36, count 2 2006.245.07:42:10.71#ibcon#end of sib2, iclass 36, count 2 2006.245.07:42:10.71#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:42:10.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:42:10.71#ibcon#[25=AT01-08\r\n] 2006.245.07:42:10.71#ibcon#*before write, iclass 36, count 2 2006.245.07:42:10.71#ibcon#enter sib2, iclass 36, count 2 2006.245.07:42:10.71#ibcon#flushed, iclass 36, count 2 2006.245.07:42:10.71#ibcon#about to write, iclass 36, count 2 2006.245.07:42:10.71#ibcon#wrote, iclass 36, count 2 2006.245.07:42:10.71#ibcon#about to read 3, iclass 36, count 2 2006.245.07:42:10.75#ibcon#read 3, iclass 36, count 2 2006.245.07:42:10.75#ibcon#about to read 4, iclass 36, count 2 2006.245.07:42:10.75#ibcon#read 4, iclass 36, count 2 2006.245.07:42:10.75#ibcon#about to read 5, iclass 36, count 2 2006.245.07:42:10.75#ibcon#read 5, iclass 36, count 2 2006.245.07:42:10.75#ibcon#about to read 6, iclass 36, count 2 2006.245.07:42:10.75#ibcon#read 6, iclass 36, count 2 2006.245.07:42:10.75#ibcon#end of sib2, iclass 36, count 2 2006.245.07:42:10.75#ibcon#*after write, iclass 36, count 2 2006.245.07:42:10.75#ibcon#*before return 0, iclass 36, count 2 2006.245.07:42:10.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:10.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:10.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:42:10.75#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:10.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:10.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:10.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:10.87#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:42:10.87#ibcon#first serial, iclass 36, count 0 2006.245.07:42:10.87#ibcon#enter sib2, iclass 36, count 0 2006.245.07:42:10.87#ibcon#flushed, iclass 36, count 0 2006.245.07:42:10.87#ibcon#about to write, iclass 36, count 0 2006.245.07:42:10.87#ibcon#wrote, iclass 36, count 0 2006.245.07:42:10.87#ibcon#about to read 3, iclass 36, count 0 2006.245.07:42:10.89#ibcon#read 3, iclass 36, count 0 2006.245.07:42:10.89#ibcon#about to read 4, iclass 36, count 0 2006.245.07:42:10.89#ibcon#read 4, iclass 36, count 0 2006.245.07:42:10.89#ibcon#about to read 5, iclass 36, count 0 2006.245.07:42:10.89#ibcon#read 5, iclass 36, count 0 2006.245.07:42:10.89#ibcon#about to read 6, iclass 36, count 0 2006.245.07:42:10.89#ibcon#read 6, iclass 36, count 0 2006.245.07:42:10.89#ibcon#end of sib2, iclass 36, count 0 2006.245.07:42:10.89#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:42:10.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:42:10.89#ibcon#[25=USB\r\n] 2006.245.07:42:10.89#ibcon#*before write, iclass 36, count 0 2006.245.07:42:10.89#ibcon#enter sib2, iclass 36, count 0 2006.245.07:42:10.89#ibcon#flushed, iclass 36, count 0 2006.245.07:42:10.89#ibcon#about to write, iclass 36, count 0 2006.245.07:42:10.89#ibcon#wrote, iclass 36, count 0 2006.245.07:42:10.89#ibcon#about to read 3, iclass 36, count 0 2006.245.07:42:10.92#ibcon#read 3, iclass 36, count 0 2006.245.07:42:10.92#ibcon#about to read 4, iclass 36, count 0 2006.245.07:42:10.92#ibcon#read 4, iclass 36, count 0 2006.245.07:42:10.92#ibcon#about to read 5, iclass 36, count 0 2006.245.07:42:10.92#ibcon#read 5, iclass 36, count 0 2006.245.07:42:10.92#ibcon#about to read 6, iclass 36, count 0 2006.245.07:42:10.92#ibcon#read 6, iclass 36, count 0 2006.245.07:42:10.92#ibcon#end of sib2, iclass 36, count 0 2006.245.07:42:10.92#ibcon#*after write, iclass 36, count 0 2006.245.07:42:10.92#ibcon#*before return 0, iclass 36, count 0 2006.245.07:42:10.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:10.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:10.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:42:10.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:42:10.92$vc4f8/valo=2,572.99 2006.245.07:42:10.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:42:10.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:42:10.92#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:10.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:10.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:10.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:10.92#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:42:10.92#ibcon#first serial, iclass 38, count 0 2006.245.07:42:10.92#ibcon#enter sib2, iclass 38, count 0 2006.245.07:42:10.92#ibcon#flushed, iclass 38, count 0 2006.245.07:42:10.92#ibcon#about to write, iclass 38, count 0 2006.245.07:42:10.92#ibcon#wrote, iclass 38, count 0 2006.245.07:42:10.92#ibcon#about to read 3, iclass 38, count 0 2006.245.07:42:10.94#ibcon#read 3, iclass 38, count 0 2006.245.07:42:10.94#ibcon#about to read 4, iclass 38, count 0 2006.245.07:42:10.94#ibcon#read 4, iclass 38, count 0 2006.245.07:42:10.94#ibcon#about to read 5, iclass 38, count 0 2006.245.07:42:10.94#ibcon#read 5, iclass 38, count 0 2006.245.07:42:10.94#ibcon#about to read 6, iclass 38, count 0 2006.245.07:42:10.94#ibcon#read 6, iclass 38, count 0 2006.245.07:42:10.94#ibcon#end of sib2, iclass 38, count 0 2006.245.07:42:10.94#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:42:10.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:42:10.94#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:42:10.94#ibcon#*before write, iclass 38, count 0 2006.245.07:42:10.94#ibcon#enter sib2, iclass 38, count 0 2006.245.07:42:10.94#ibcon#flushed, iclass 38, count 0 2006.245.07:42:10.94#ibcon#about to write, iclass 38, count 0 2006.245.07:42:10.94#ibcon#wrote, iclass 38, count 0 2006.245.07:42:10.94#ibcon#about to read 3, iclass 38, count 0 2006.245.07:42:10.98#ibcon#read 3, iclass 38, count 0 2006.245.07:42:10.98#ibcon#about to read 4, iclass 38, count 0 2006.245.07:42:10.98#ibcon#read 4, iclass 38, count 0 2006.245.07:42:10.98#ibcon#about to read 5, iclass 38, count 0 2006.245.07:42:10.98#ibcon#read 5, iclass 38, count 0 2006.245.07:42:10.98#ibcon#about to read 6, iclass 38, count 0 2006.245.07:42:10.98#ibcon#read 6, iclass 38, count 0 2006.245.07:42:10.98#ibcon#end of sib2, iclass 38, count 0 2006.245.07:42:10.98#ibcon#*after write, iclass 38, count 0 2006.245.07:42:10.98#ibcon#*before return 0, iclass 38, count 0 2006.245.07:42:10.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:10.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:10.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:42:10.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:42:10.98$vc4f8/va=2,7 2006.245.07:42:10.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:42:10.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:42:10.98#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:10.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:11.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:11.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:11.04#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:42:11.04#ibcon#first serial, iclass 40, count 2 2006.245.07:42:11.04#ibcon#enter sib2, iclass 40, count 2 2006.245.07:42:11.04#ibcon#flushed, iclass 40, count 2 2006.245.07:42:11.04#ibcon#about to write, iclass 40, count 2 2006.245.07:42:11.04#ibcon#wrote, iclass 40, count 2 2006.245.07:42:11.04#ibcon#about to read 3, iclass 40, count 2 2006.245.07:42:11.06#ibcon#read 3, iclass 40, count 2 2006.245.07:42:11.06#ibcon#about to read 4, iclass 40, count 2 2006.245.07:42:11.06#ibcon#read 4, iclass 40, count 2 2006.245.07:42:11.06#ibcon#about to read 5, iclass 40, count 2 2006.245.07:42:11.06#ibcon#read 5, iclass 40, count 2 2006.245.07:42:11.06#ibcon#about to read 6, iclass 40, count 2 2006.245.07:42:11.06#ibcon#read 6, iclass 40, count 2 2006.245.07:42:11.06#ibcon#end of sib2, iclass 40, count 2 2006.245.07:42:11.06#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:42:11.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:42:11.06#ibcon#[25=AT02-07\r\n] 2006.245.07:42:11.06#ibcon#*before write, iclass 40, count 2 2006.245.07:42:11.06#ibcon#enter sib2, iclass 40, count 2 2006.245.07:42:11.06#ibcon#flushed, iclass 40, count 2 2006.245.07:42:11.06#ibcon#about to write, iclass 40, count 2 2006.245.07:42:11.06#ibcon#wrote, iclass 40, count 2 2006.245.07:42:11.06#ibcon#about to read 3, iclass 40, count 2 2006.245.07:42:11.09#ibcon#read 3, iclass 40, count 2 2006.245.07:42:11.09#ibcon#about to read 4, iclass 40, count 2 2006.245.07:42:11.09#ibcon#read 4, iclass 40, count 2 2006.245.07:42:11.09#ibcon#about to read 5, iclass 40, count 2 2006.245.07:42:11.09#ibcon#read 5, iclass 40, count 2 2006.245.07:42:11.09#ibcon#about to read 6, iclass 40, count 2 2006.245.07:42:11.09#ibcon#read 6, iclass 40, count 2 2006.245.07:42:11.09#ibcon#end of sib2, iclass 40, count 2 2006.245.07:42:11.09#ibcon#*after write, iclass 40, count 2 2006.245.07:42:11.09#ibcon#*before return 0, iclass 40, count 2 2006.245.07:42:11.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:11.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:11.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:42:11.09#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:11.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:11.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:11.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:11.21#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:42:11.21#ibcon#first serial, iclass 40, count 0 2006.245.07:42:11.21#ibcon#enter sib2, iclass 40, count 0 2006.245.07:42:11.21#ibcon#flushed, iclass 40, count 0 2006.245.07:42:11.21#ibcon#about to write, iclass 40, count 0 2006.245.07:42:11.21#ibcon#wrote, iclass 40, count 0 2006.245.07:42:11.21#ibcon#about to read 3, iclass 40, count 0 2006.245.07:42:11.24#ibcon#read 3, iclass 40, count 0 2006.245.07:42:11.24#ibcon#about to read 4, iclass 40, count 0 2006.245.07:42:11.24#ibcon#read 4, iclass 40, count 0 2006.245.07:42:11.24#ibcon#about to read 5, iclass 40, count 0 2006.245.07:42:11.24#ibcon#read 5, iclass 40, count 0 2006.245.07:42:11.24#ibcon#about to read 6, iclass 40, count 0 2006.245.07:42:11.24#ibcon#read 6, iclass 40, count 0 2006.245.07:42:11.24#ibcon#end of sib2, iclass 40, count 0 2006.245.07:42:11.24#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:42:11.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:42:11.24#ibcon#[25=USB\r\n] 2006.245.07:42:11.24#ibcon#*before write, iclass 40, count 0 2006.245.07:42:11.24#ibcon#enter sib2, iclass 40, count 0 2006.245.07:42:11.24#ibcon#flushed, iclass 40, count 0 2006.245.07:42:11.24#ibcon#about to write, iclass 40, count 0 2006.245.07:42:11.24#ibcon#wrote, iclass 40, count 0 2006.245.07:42:11.24#ibcon#about to read 3, iclass 40, count 0 2006.245.07:42:11.27#ibcon#read 3, iclass 40, count 0 2006.245.07:42:11.27#ibcon#about to read 4, iclass 40, count 0 2006.245.07:42:11.27#ibcon#read 4, iclass 40, count 0 2006.245.07:42:11.27#ibcon#about to read 5, iclass 40, count 0 2006.245.07:42:11.27#ibcon#read 5, iclass 40, count 0 2006.245.07:42:11.27#ibcon#about to read 6, iclass 40, count 0 2006.245.07:42:11.27#ibcon#read 6, iclass 40, count 0 2006.245.07:42:11.27#ibcon#end of sib2, iclass 40, count 0 2006.245.07:42:11.27#ibcon#*after write, iclass 40, count 0 2006.245.07:42:11.27#ibcon#*before return 0, iclass 40, count 0 2006.245.07:42:11.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:11.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:11.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:42:11.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:42:11.27$vc4f8/valo=3,672.99 2006.245.07:42:11.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:42:11.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:42:11.27#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:11.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:11.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:11.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:11.27#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:42:11.27#ibcon#first serial, iclass 4, count 0 2006.245.07:42:11.27#ibcon#enter sib2, iclass 4, count 0 2006.245.07:42:11.27#ibcon#flushed, iclass 4, count 0 2006.245.07:42:11.27#ibcon#about to write, iclass 4, count 0 2006.245.07:42:11.27#ibcon#wrote, iclass 4, count 0 2006.245.07:42:11.27#ibcon#about to read 3, iclass 4, count 0 2006.245.07:42:11.29#ibcon#read 3, iclass 4, count 0 2006.245.07:42:11.29#ibcon#about to read 4, iclass 4, count 0 2006.245.07:42:11.29#ibcon#read 4, iclass 4, count 0 2006.245.07:42:11.29#ibcon#about to read 5, iclass 4, count 0 2006.245.07:42:11.29#ibcon#read 5, iclass 4, count 0 2006.245.07:42:11.29#ibcon#about to read 6, iclass 4, count 0 2006.245.07:42:11.29#ibcon#read 6, iclass 4, count 0 2006.245.07:42:11.29#ibcon#end of sib2, iclass 4, count 0 2006.245.07:42:11.29#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:42:11.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:42:11.29#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:42:11.29#ibcon#*before write, iclass 4, count 0 2006.245.07:42:11.29#ibcon#enter sib2, iclass 4, count 0 2006.245.07:42:11.29#ibcon#flushed, iclass 4, count 0 2006.245.07:42:11.29#ibcon#about to write, iclass 4, count 0 2006.245.07:42:11.29#ibcon#wrote, iclass 4, count 0 2006.245.07:42:11.29#ibcon#about to read 3, iclass 4, count 0 2006.245.07:42:11.33#ibcon#read 3, iclass 4, count 0 2006.245.07:42:11.33#ibcon#about to read 4, iclass 4, count 0 2006.245.07:42:11.33#ibcon#read 4, iclass 4, count 0 2006.245.07:42:11.33#ibcon#about to read 5, iclass 4, count 0 2006.245.07:42:11.33#ibcon#read 5, iclass 4, count 0 2006.245.07:42:11.33#ibcon#about to read 6, iclass 4, count 0 2006.245.07:42:11.33#ibcon#read 6, iclass 4, count 0 2006.245.07:42:11.33#ibcon#end of sib2, iclass 4, count 0 2006.245.07:42:11.33#ibcon#*after write, iclass 4, count 0 2006.245.07:42:11.33#ibcon#*before return 0, iclass 4, count 0 2006.245.07:42:11.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:11.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:11.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:42:11.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:42:11.33$vc4f8/va=3,6 2006.245.07:42:11.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:42:11.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:42:11.33#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:11.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:11.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:11.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:11.39#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:42:11.39#ibcon#first serial, iclass 6, count 2 2006.245.07:42:11.39#ibcon#enter sib2, iclass 6, count 2 2006.245.07:42:11.39#ibcon#flushed, iclass 6, count 2 2006.245.07:42:11.39#ibcon#about to write, iclass 6, count 2 2006.245.07:42:11.39#ibcon#wrote, iclass 6, count 2 2006.245.07:42:11.39#ibcon#about to read 3, iclass 6, count 2 2006.245.07:42:11.41#ibcon#read 3, iclass 6, count 2 2006.245.07:42:11.41#ibcon#about to read 4, iclass 6, count 2 2006.245.07:42:11.41#ibcon#read 4, iclass 6, count 2 2006.245.07:42:11.41#ibcon#about to read 5, iclass 6, count 2 2006.245.07:42:11.41#ibcon#read 5, iclass 6, count 2 2006.245.07:42:11.41#ibcon#about to read 6, iclass 6, count 2 2006.245.07:42:11.41#ibcon#read 6, iclass 6, count 2 2006.245.07:42:11.41#ibcon#end of sib2, iclass 6, count 2 2006.245.07:42:11.41#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:42:11.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:42:11.41#ibcon#[25=AT03-06\r\n] 2006.245.07:42:11.41#ibcon#*before write, iclass 6, count 2 2006.245.07:42:11.41#ibcon#enter sib2, iclass 6, count 2 2006.245.07:42:11.41#ibcon#flushed, iclass 6, count 2 2006.245.07:42:11.41#ibcon#about to write, iclass 6, count 2 2006.245.07:42:11.41#ibcon#wrote, iclass 6, count 2 2006.245.07:42:11.41#ibcon#about to read 3, iclass 6, count 2 2006.245.07:42:11.45#ibcon#read 3, iclass 6, count 2 2006.245.07:42:11.45#ibcon#about to read 4, iclass 6, count 2 2006.245.07:42:11.45#ibcon#read 4, iclass 6, count 2 2006.245.07:42:11.45#ibcon#about to read 5, iclass 6, count 2 2006.245.07:42:11.45#ibcon#read 5, iclass 6, count 2 2006.245.07:42:11.45#ibcon#about to read 6, iclass 6, count 2 2006.245.07:42:11.45#ibcon#read 6, iclass 6, count 2 2006.245.07:42:11.45#ibcon#end of sib2, iclass 6, count 2 2006.245.07:42:11.45#ibcon#*after write, iclass 6, count 2 2006.245.07:42:11.45#ibcon#*before return 0, iclass 6, count 2 2006.245.07:42:11.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:11.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:11.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:42:11.45#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:11.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:11.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:11.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:11.57#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:42:11.57#ibcon#first serial, iclass 6, count 0 2006.245.07:42:11.57#ibcon#enter sib2, iclass 6, count 0 2006.245.07:42:11.57#ibcon#flushed, iclass 6, count 0 2006.245.07:42:11.57#ibcon#about to write, iclass 6, count 0 2006.245.07:42:11.57#ibcon#wrote, iclass 6, count 0 2006.245.07:42:11.57#ibcon#about to read 3, iclass 6, count 0 2006.245.07:42:11.59#ibcon#read 3, iclass 6, count 0 2006.245.07:42:11.59#ibcon#about to read 4, iclass 6, count 0 2006.245.07:42:11.59#ibcon#read 4, iclass 6, count 0 2006.245.07:42:11.59#ibcon#about to read 5, iclass 6, count 0 2006.245.07:42:11.59#ibcon#read 5, iclass 6, count 0 2006.245.07:42:11.59#ibcon#about to read 6, iclass 6, count 0 2006.245.07:42:11.59#ibcon#read 6, iclass 6, count 0 2006.245.07:42:11.59#ibcon#end of sib2, iclass 6, count 0 2006.245.07:42:11.59#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:42:11.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:42:11.59#ibcon#[25=USB\r\n] 2006.245.07:42:11.59#ibcon#*before write, iclass 6, count 0 2006.245.07:42:11.59#ibcon#enter sib2, iclass 6, count 0 2006.245.07:42:11.59#ibcon#flushed, iclass 6, count 0 2006.245.07:42:11.59#ibcon#about to write, iclass 6, count 0 2006.245.07:42:11.59#ibcon#wrote, iclass 6, count 0 2006.245.07:42:11.59#ibcon#about to read 3, iclass 6, count 0 2006.245.07:42:11.62#ibcon#read 3, iclass 6, count 0 2006.245.07:42:11.62#ibcon#about to read 4, iclass 6, count 0 2006.245.07:42:11.62#ibcon#read 4, iclass 6, count 0 2006.245.07:42:11.62#ibcon#about to read 5, iclass 6, count 0 2006.245.07:42:11.62#ibcon#read 5, iclass 6, count 0 2006.245.07:42:11.62#ibcon#about to read 6, iclass 6, count 0 2006.245.07:42:11.62#ibcon#read 6, iclass 6, count 0 2006.245.07:42:11.62#ibcon#end of sib2, iclass 6, count 0 2006.245.07:42:11.62#ibcon#*after write, iclass 6, count 0 2006.245.07:42:11.62#ibcon#*before return 0, iclass 6, count 0 2006.245.07:42:11.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:11.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:11.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:42:11.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:42:11.62$vc4f8/valo=4,832.99 2006.245.07:42:11.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:42:11.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:42:11.62#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:11.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:11.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:11.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:11.62#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:42:11.62#ibcon#first serial, iclass 10, count 0 2006.245.07:42:11.62#ibcon#enter sib2, iclass 10, count 0 2006.245.07:42:11.62#ibcon#flushed, iclass 10, count 0 2006.245.07:42:11.62#ibcon#about to write, iclass 10, count 0 2006.245.07:42:11.62#ibcon#wrote, iclass 10, count 0 2006.245.07:42:11.62#ibcon#about to read 3, iclass 10, count 0 2006.245.07:42:11.64#ibcon#read 3, iclass 10, count 0 2006.245.07:42:11.64#ibcon#about to read 4, iclass 10, count 0 2006.245.07:42:11.64#ibcon#read 4, iclass 10, count 0 2006.245.07:42:11.64#ibcon#about to read 5, iclass 10, count 0 2006.245.07:42:11.64#ibcon#read 5, iclass 10, count 0 2006.245.07:42:11.64#ibcon#about to read 6, iclass 10, count 0 2006.245.07:42:11.64#ibcon#read 6, iclass 10, count 0 2006.245.07:42:11.64#ibcon#end of sib2, iclass 10, count 0 2006.245.07:42:11.64#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:42:11.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:42:11.64#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:42:11.64#ibcon#*before write, iclass 10, count 0 2006.245.07:42:11.64#ibcon#enter sib2, iclass 10, count 0 2006.245.07:42:11.64#ibcon#flushed, iclass 10, count 0 2006.245.07:42:11.64#ibcon#about to write, iclass 10, count 0 2006.245.07:42:11.64#ibcon#wrote, iclass 10, count 0 2006.245.07:42:11.64#ibcon#about to read 3, iclass 10, count 0 2006.245.07:42:11.68#ibcon#read 3, iclass 10, count 0 2006.245.07:42:11.68#ibcon#about to read 4, iclass 10, count 0 2006.245.07:42:11.68#ibcon#read 4, iclass 10, count 0 2006.245.07:42:11.68#ibcon#about to read 5, iclass 10, count 0 2006.245.07:42:11.68#ibcon#read 5, iclass 10, count 0 2006.245.07:42:11.68#ibcon#about to read 6, iclass 10, count 0 2006.245.07:42:11.68#ibcon#read 6, iclass 10, count 0 2006.245.07:42:11.68#ibcon#end of sib2, iclass 10, count 0 2006.245.07:42:11.68#ibcon#*after write, iclass 10, count 0 2006.245.07:42:11.68#ibcon#*before return 0, iclass 10, count 0 2006.245.07:42:11.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:11.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:11.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:42:11.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:42:11.68$vc4f8/va=4,7 2006.245.07:42:11.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:42:11.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:42:11.68#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:11.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:11.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:11.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:11.74#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:42:11.74#ibcon#first serial, iclass 12, count 2 2006.245.07:42:11.74#ibcon#enter sib2, iclass 12, count 2 2006.245.07:42:11.74#ibcon#flushed, iclass 12, count 2 2006.245.07:42:11.74#ibcon#about to write, iclass 12, count 2 2006.245.07:42:11.74#ibcon#wrote, iclass 12, count 2 2006.245.07:42:11.74#ibcon#about to read 3, iclass 12, count 2 2006.245.07:42:11.76#ibcon#read 3, iclass 12, count 2 2006.245.07:42:11.76#ibcon#about to read 4, iclass 12, count 2 2006.245.07:42:11.76#ibcon#read 4, iclass 12, count 2 2006.245.07:42:11.76#ibcon#about to read 5, iclass 12, count 2 2006.245.07:42:11.76#ibcon#read 5, iclass 12, count 2 2006.245.07:42:11.76#ibcon#about to read 6, iclass 12, count 2 2006.245.07:42:11.76#ibcon#read 6, iclass 12, count 2 2006.245.07:42:11.76#ibcon#end of sib2, iclass 12, count 2 2006.245.07:42:11.76#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:42:11.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:42:11.76#ibcon#[25=AT04-07\r\n] 2006.245.07:42:11.76#ibcon#*before write, iclass 12, count 2 2006.245.07:42:11.76#ibcon#enter sib2, iclass 12, count 2 2006.245.07:42:11.76#ibcon#flushed, iclass 12, count 2 2006.245.07:42:11.76#ibcon#about to write, iclass 12, count 2 2006.245.07:42:11.76#ibcon#wrote, iclass 12, count 2 2006.245.07:42:11.76#ibcon#about to read 3, iclass 12, count 2 2006.245.07:42:11.79#ibcon#read 3, iclass 12, count 2 2006.245.07:42:11.79#ibcon#about to read 4, iclass 12, count 2 2006.245.07:42:11.79#ibcon#read 4, iclass 12, count 2 2006.245.07:42:11.79#ibcon#about to read 5, iclass 12, count 2 2006.245.07:42:11.79#ibcon#read 5, iclass 12, count 2 2006.245.07:42:11.79#ibcon#about to read 6, iclass 12, count 2 2006.245.07:42:11.79#ibcon#read 6, iclass 12, count 2 2006.245.07:42:11.79#ibcon#end of sib2, iclass 12, count 2 2006.245.07:42:11.79#ibcon#*after write, iclass 12, count 2 2006.245.07:42:11.79#ibcon#*before return 0, iclass 12, count 2 2006.245.07:42:11.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:11.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:11.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:42:11.79#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:11.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:11.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:11.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:11.91#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:42:11.91#ibcon#first serial, iclass 12, count 0 2006.245.07:42:11.91#ibcon#enter sib2, iclass 12, count 0 2006.245.07:42:11.91#ibcon#flushed, iclass 12, count 0 2006.245.07:42:11.91#ibcon#about to write, iclass 12, count 0 2006.245.07:42:11.91#ibcon#wrote, iclass 12, count 0 2006.245.07:42:11.91#ibcon#about to read 3, iclass 12, count 0 2006.245.07:42:11.93#ibcon#read 3, iclass 12, count 0 2006.245.07:42:11.93#ibcon#about to read 4, iclass 12, count 0 2006.245.07:42:11.93#ibcon#read 4, iclass 12, count 0 2006.245.07:42:11.93#ibcon#about to read 5, iclass 12, count 0 2006.245.07:42:11.93#ibcon#read 5, iclass 12, count 0 2006.245.07:42:11.93#ibcon#about to read 6, iclass 12, count 0 2006.245.07:42:11.93#ibcon#read 6, iclass 12, count 0 2006.245.07:42:11.93#ibcon#end of sib2, iclass 12, count 0 2006.245.07:42:11.93#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:42:11.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:42:11.93#ibcon#[25=USB\r\n] 2006.245.07:42:11.93#ibcon#*before write, iclass 12, count 0 2006.245.07:42:11.93#ibcon#enter sib2, iclass 12, count 0 2006.245.07:42:11.93#ibcon#flushed, iclass 12, count 0 2006.245.07:42:11.93#ibcon#about to write, iclass 12, count 0 2006.245.07:42:11.93#ibcon#wrote, iclass 12, count 0 2006.245.07:42:11.93#ibcon#about to read 3, iclass 12, count 0 2006.245.07:42:11.96#ibcon#read 3, iclass 12, count 0 2006.245.07:42:11.96#ibcon#about to read 4, iclass 12, count 0 2006.245.07:42:11.96#ibcon#read 4, iclass 12, count 0 2006.245.07:42:11.96#ibcon#about to read 5, iclass 12, count 0 2006.245.07:42:11.96#ibcon#read 5, iclass 12, count 0 2006.245.07:42:11.96#ibcon#about to read 6, iclass 12, count 0 2006.245.07:42:11.96#ibcon#read 6, iclass 12, count 0 2006.245.07:42:11.96#ibcon#end of sib2, iclass 12, count 0 2006.245.07:42:11.96#ibcon#*after write, iclass 12, count 0 2006.245.07:42:11.96#ibcon#*before return 0, iclass 12, count 0 2006.245.07:42:11.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:11.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:11.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:42:11.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:42:11.96$vc4f8/valo=5,652.99 2006.245.07:42:11.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:42:11.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:42:11.96#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:11.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:42:11.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:42:11.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:42:11.96#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:42:11.96#ibcon#first serial, iclass 14, count 0 2006.245.07:42:11.96#ibcon#enter sib2, iclass 14, count 0 2006.245.07:42:11.96#ibcon#flushed, iclass 14, count 0 2006.245.07:42:11.96#ibcon#about to write, iclass 14, count 0 2006.245.07:42:11.96#ibcon#wrote, iclass 14, count 0 2006.245.07:42:11.96#ibcon#about to read 3, iclass 14, count 0 2006.245.07:42:11.98#ibcon#read 3, iclass 14, count 0 2006.245.07:42:11.98#ibcon#about to read 4, iclass 14, count 0 2006.245.07:42:11.98#ibcon#read 4, iclass 14, count 0 2006.245.07:42:11.98#ibcon#about to read 5, iclass 14, count 0 2006.245.07:42:11.98#ibcon#read 5, iclass 14, count 0 2006.245.07:42:11.98#ibcon#about to read 6, iclass 14, count 0 2006.245.07:42:11.98#ibcon#read 6, iclass 14, count 0 2006.245.07:42:11.98#ibcon#end of sib2, iclass 14, count 0 2006.245.07:42:11.98#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:42:11.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:42:11.98#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:42:11.98#ibcon#*before write, iclass 14, count 0 2006.245.07:42:11.98#ibcon#enter sib2, iclass 14, count 0 2006.245.07:42:11.98#ibcon#flushed, iclass 14, count 0 2006.245.07:42:11.98#ibcon#about to write, iclass 14, count 0 2006.245.07:42:11.98#ibcon#wrote, iclass 14, count 0 2006.245.07:42:11.98#ibcon#about to read 3, iclass 14, count 0 2006.245.07:42:12.02#ibcon#read 3, iclass 14, count 0 2006.245.07:42:12.02#ibcon#about to read 4, iclass 14, count 0 2006.245.07:42:12.02#ibcon#read 4, iclass 14, count 0 2006.245.07:42:12.02#ibcon#about to read 5, iclass 14, count 0 2006.245.07:42:12.02#ibcon#read 5, iclass 14, count 0 2006.245.07:42:12.02#ibcon#about to read 6, iclass 14, count 0 2006.245.07:42:12.02#ibcon#read 6, iclass 14, count 0 2006.245.07:42:12.02#ibcon#end of sib2, iclass 14, count 0 2006.245.07:42:12.02#ibcon#*after write, iclass 14, count 0 2006.245.07:42:12.02#ibcon#*before return 0, iclass 14, count 0 2006.245.07:42:12.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:42:12.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:42:12.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:42:12.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:42:12.02$vc4f8/va=5,7 2006.245.07:42:12.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.07:42:12.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.07:42:12.02#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:12.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:42:12.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:42:12.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:42:12.08#ibcon#enter wrdev, iclass 16, count 2 2006.245.07:42:12.08#ibcon#first serial, iclass 16, count 2 2006.245.07:42:12.08#ibcon#enter sib2, iclass 16, count 2 2006.245.07:42:12.08#ibcon#flushed, iclass 16, count 2 2006.245.07:42:12.08#ibcon#about to write, iclass 16, count 2 2006.245.07:42:12.08#ibcon#wrote, iclass 16, count 2 2006.245.07:42:12.08#ibcon#about to read 3, iclass 16, count 2 2006.245.07:42:12.10#ibcon#read 3, iclass 16, count 2 2006.245.07:42:12.10#ibcon#about to read 4, iclass 16, count 2 2006.245.07:42:12.10#ibcon#read 4, iclass 16, count 2 2006.245.07:42:12.10#ibcon#about to read 5, iclass 16, count 2 2006.245.07:42:12.10#ibcon#read 5, iclass 16, count 2 2006.245.07:42:12.10#ibcon#about to read 6, iclass 16, count 2 2006.245.07:42:12.10#ibcon#read 6, iclass 16, count 2 2006.245.07:42:12.10#ibcon#end of sib2, iclass 16, count 2 2006.245.07:42:12.10#ibcon#*mode == 0, iclass 16, count 2 2006.245.07:42:12.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.07:42:12.10#ibcon#[25=AT05-07\r\n] 2006.245.07:42:12.10#ibcon#*before write, iclass 16, count 2 2006.245.07:42:12.10#ibcon#enter sib2, iclass 16, count 2 2006.245.07:42:12.10#ibcon#flushed, iclass 16, count 2 2006.245.07:42:12.10#ibcon#about to write, iclass 16, count 2 2006.245.07:42:12.10#ibcon#wrote, iclass 16, count 2 2006.245.07:42:12.10#ibcon#about to read 3, iclass 16, count 2 2006.245.07:42:12.13#ibcon#read 3, iclass 16, count 2 2006.245.07:42:12.13#ibcon#about to read 4, iclass 16, count 2 2006.245.07:42:12.13#ibcon#read 4, iclass 16, count 2 2006.245.07:42:12.13#ibcon#about to read 5, iclass 16, count 2 2006.245.07:42:12.13#ibcon#read 5, iclass 16, count 2 2006.245.07:42:12.13#ibcon#about to read 6, iclass 16, count 2 2006.245.07:42:12.13#ibcon#read 6, iclass 16, count 2 2006.245.07:42:12.13#ibcon#end of sib2, iclass 16, count 2 2006.245.07:42:12.13#ibcon#*after write, iclass 16, count 2 2006.245.07:42:12.13#ibcon#*before return 0, iclass 16, count 2 2006.245.07:42:12.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:42:12.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:42:12.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.07:42:12.13#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:12.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:42:12.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:42:12.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:42:12.25#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:42:12.25#ibcon#first serial, iclass 16, count 0 2006.245.07:42:12.25#ibcon#enter sib2, iclass 16, count 0 2006.245.07:42:12.25#ibcon#flushed, iclass 16, count 0 2006.245.07:42:12.25#ibcon#about to write, iclass 16, count 0 2006.245.07:42:12.25#ibcon#wrote, iclass 16, count 0 2006.245.07:42:12.25#ibcon#about to read 3, iclass 16, count 0 2006.245.07:42:12.27#ibcon#read 3, iclass 16, count 0 2006.245.07:42:12.27#ibcon#about to read 4, iclass 16, count 0 2006.245.07:42:12.27#ibcon#read 4, iclass 16, count 0 2006.245.07:42:12.27#ibcon#about to read 5, iclass 16, count 0 2006.245.07:42:12.27#ibcon#read 5, iclass 16, count 0 2006.245.07:42:12.27#ibcon#about to read 6, iclass 16, count 0 2006.245.07:42:12.27#ibcon#read 6, iclass 16, count 0 2006.245.07:42:12.27#ibcon#end of sib2, iclass 16, count 0 2006.245.07:42:12.27#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:42:12.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:42:12.27#ibcon#[25=USB\r\n] 2006.245.07:42:12.27#ibcon#*before write, iclass 16, count 0 2006.245.07:42:12.27#ibcon#enter sib2, iclass 16, count 0 2006.245.07:42:12.27#ibcon#flushed, iclass 16, count 0 2006.245.07:42:12.27#ibcon#about to write, iclass 16, count 0 2006.245.07:42:12.27#ibcon#wrote, iclass 16, count 0 2006.245.07:42:12.27#ibcon#about to read 3, iclass 16, count 0 2006.245.07:42:12.30#ibcon#read 3, iclass 16, count 0 2006.245.07:42:12.30#ibcon#about to read 4, iclass 16, count 0 2006.245.07:42:12.30#ibcon#read 4, iclass 16, count 0 2006.245.07:42:12.30#ibcon#about to read 5, iclass 16, count 0 2006.245.07:42:12.30#ibcon#read 5, iclass 16, count 0 2006.245.07:42:12.30#ibcon#about to read 6, iclass 16, count 0 2006.245.07:42:12.30#ibcon#read 6, iclass 16, count 0 2006.245.07:42:12.30#ibcon#end of sib2, iclass 16, count 0 2006.245.07:42:12.30#ibcon#*after write, iclass 16, count 0 2006.245.07:42:12.30#ibcon#*before return 0, iclass 16, count 0 2006.245.07:42:12.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:42:12.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:42:12.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:42:12.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:42:12.30$vc4f8/valo=6,772.99 2006.245.07:42:12.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.07:42:12.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.07:42:12.30#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:12.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:12.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:12.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:12.30#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:42:12.30#ibcon#first serial, iclass 18, count 0 2006.245.07:42:12.30#ibcon#enter sib2, iclass 18, count 0 2006.245.07:42:12.30#ibcon#flushed, iclass 18, count 0 2006.245.07:42:12.30#ibcon#about to write, iclass 18, count 0 2006.245.07:42:12.30#ibcon#wrote, iclass 18, count 0 2006.245.07:42:12.30#ibcon#about to read 3, iclass 18, count 0 2006.245.07:42:12.32#ibcon#read 3, iclass 18, count 0 2006.245.07:42:12.32#ibcon#about to read 4, iclass 18, count 0 2006.245.07:42:12.32#ibcon#read 4, iclass 18, count 0 2006.245.07:42:12.32#ibcon#about to read 5, iclass 18, count 0 2006.245.07:42:12.32#ibcon#read 5, iclass 18, count 0 2006.245.07:42:12.32#ibcon#about to read 6, iclass 18, count 0 2006.245.07:42:12.32#ibcon#read 6, iclass 18, count 0 2006.245.07:42:12.32#ibcon#end of sib2, iclass 18, count 0 2006.245.07:42:12.32#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:42:12.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:42:12.32#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:42:12.32#ibcon#*before write, iclass 18, count 0 2006.245.07:42:12.32#ibcon#enter sib2, iclass 18, count 0 2006.245.07:42:12.32#ibcon#flushed, iclass 18, count 0 2006.245.07:42:12.32#ibcon#about to write, iclass 18, count 0 2006.245.07:42:12.32#ibcon#wrote, iclass 18, count 0 2006.245.07:42:12.32#ibcon#about to read 3, iclass 18, count 0 2006.245.07:42:12.36#ibcon#read 3, iclass 18, count 0 2006.245.07:42:12.36#ibcon#about to read 4, iclass 18, count 0 2006.245.07:42:12.36#ibcon#read 4, iclass 18, count 0 2006.245.07:42:12.36#ibcon#about to read 5, iclass 18, count 0 2006.245.07:42:12.36#ibcon#read 5, iclass 18, count 0 2006.245.07:42:12.36#ibcon#about to read 6, iclass 18, count 0 2006.245.07:42:12.36#ibcon#read 6, iclass 18, count 0 2006.245.07:42:12.36#ibcon#end of sib2, iclass 18, count 0 2006.245.07:42:12.36#ibcon#*after write, iclass 18, count 0 2006.245.07:42:12.36#ibcon#*before return 0, iclass 18, count 0 2006.245.07:42:12.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:12.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:12.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:42:12.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:42:12.36$vc4f8/va=6,7 2006.245.07:42:12.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.07:42:12.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.07:42:12.36#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:12.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:12.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:12.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:12.42#ibcon#enter wrdev, iclass 20, count 2 2006.245.07:42:12.42#ibcon#first serial, iclass 20, count 2 2006.245.07:42:12.42#ibcon#enter sib2, iclass 20, count 2 2006.245.07:42:12.42#ibcon#flushed, iclass 20, count 2 2006.245.07:42:12.42#ibcon#about to write, iclass 20, count 2 2006.245.07:42:12.42#ibcon#wrote, iclass 20, count 2 2006.245.07:42:12.42#ibcon#about to read 3, iclass 20, count 2 2006.245.07:42:12.44#ibcon#read 3, iclass 20, count 2 2006.245.07:42:12.44#ibcon#about to read 4, iclass 20, count 2 2006.245.07:42:12.44#ibcon#read 4, iclass 20, count 2 2006.245.07:42:12.44#ibcon#about to read 5, iclass 20, count 2 2006.245.07:42:12.44#ibcon#read 5, iclass 20, count 2 2006.245.07:42:12.44#ibcon#about to read 6, iclass 20, count 2 2006.245.07:42:12.44#ibcon#read 6, iclass 20, count 2 2006.245.07:42:12.44#ibcon#end of sib2, iclass 20, count 2 2006.245.07:42:12.44#ibcon#*mode == 0, iclass 20, count 2 2006.245.07:42:12.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.07:42:12.44#ibcon#[25=AT06-07\r\n] 2006.245.07:42:12.44#ibcon#*before write, iclass 20, count 2 2006.245.07:42:12.44#ibcon#enter sib2, iclass 20, count 2 2006.245.07:42:12.44#ibcon#flushed, iclass 20, count 2 2006.245.07:42:12.44#ibcon#about to write, iclass 20, count 2 2006.245.07:42:12.44#ibcon#wrote, iclass 20, count 2 2006.245.07:42:12.44#ibcon#about to read 3, iclass 20, count 2 2006.245.07:42:12.47#ibcon#read 3, iclass 20, count 2 2006.245.07:42:12.47#ibcon#about to read 4, iclass 20, count 2 2006.245.07:42:12.47#ibcon#read 4, iclass 20, count 2 2006.245.07:42:12.47#ibcon#about to read 5, iclass 20, count 2 2006.245.07:42:12.47#ibcon#read 5, iclass 20, count 2 2006.245.07:42:12.47#ibcon#about to read 6, iclass 20, count 2 2006.245.07:42:12.47#ibcon#read 6, iclass 20, count 2 2006.245.07:42:12.47#ibcon#end of sib2, iclass 20, count 2 2006.245.07:42:12.47#ibcon#*after write, iclass 20, count 2 2006.245.07:42:12.47#ibcon#*before return 0, iclass 20, count 2 2006.245.07:42:12.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:12.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:12.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.07:42:12.47#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:12.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:12.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:12.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:12.59#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:42:12.59#ibcon#first serial, iclass 20, count 0 2006.245.07:42:12.59#ibcon#enter sib2, iclass 20, count 0 2006.245.07:42:12.59#ibcon#flushed, iclass 20, count 0 2006.245.07:42:12.59#ibcon#about to write, iclass 20, count 0 2006.245.07:42:12.59#ibcon#wrote, iclass 20, count 0 2006.245.07:42:12.59#ibcon#about to read 3, iclass 20, count 0 2006.245.07:42:12.61#ibcon#read 3, iclass 20, count 0 2006.245.07:42:12.61#ibcon#about to read 4, iclass 20, count 0 2006.245.07:42:12.61#ibcon#read 4, iclass 20, count 0 2006.245.07:42:12.61#ibcon#about to read 5, iclass 20, count 0 2006.245.07:42:12.61#ibcon#read 5, iclass 20, count 0 2006.245.07:42:12.61#ibcon#about to read 6, iclass 20, count 0 2006.245.07:42:12.61#ibcon#read 6, iclass 20, count 0 2006.245.07:42:12.61#ibcon#end of sib2, iclass 20, count 0 2006.245.07:42:12.61#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:42:12.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:42:12.61#ibcon#[25=USB\r\n] 2006.245.07:42:12.61#ibcon#*before write, iclass 20, count 0 2006.245.07:42:12.61#ibcon#enter sib2, iclass 20, count 0 2006.245.07:42:12.61#ibcon#flushed, iclass 20, count 0 2006.245.07:42:12.61#ibcon#about to write, iclass 20, count 0 2006.245.07:42:12.61#ibcon#wrote, iclass 20, count 0 2006.245.07:42:12.61#ibcon#about to read 3, iclass 20, count 0 2006.245.07:42:12.64#ibcon#read 3, iclass 20, count 0 2006.245.07:42:12.64#ibcon#about to read 4, iclass 20, count 0 2006.245.07:42:12.64#ibcon#read 4, iclass 20, count 0 2006.245.07:42:12.64#ibcon#about to read 5, iclass 20, count 0 2006.245.07:42:12.64#ibcon#read 5, iclass 20, count 0 2006.245.07:42:12.64#ibcon#about to read 6, iclass 20, count 0 2006.245.07:42:12.64#ibcon#read 6, iclass 20, count 0 2006.245.07:42:12.64#ibcon#end of sib2, iclass 20, count 0 2006.245.07:42:12.64#ibcon#*after write, iclass 20, count 0 2006.245.07:42:12.64#ibcon#*before return 0, iclass 20, count 0 2006.245.07:42:12.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:12.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:12.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:42:12.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:42:12.64$vc4f8/valo=7,832.99 2006.245.07:42:12.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.07:42:12.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.07:42:12.64#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:12.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:12.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:12.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:12.64#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:42:12.64#ibcon#first serial, iclass 22, count 0 2006.245.07:42:12.64#ibcon#enter sib2, iclass 22, count 0 2006.245.07:42:12.64#ibcon#flushed, iclass 22, count 0 2006.245.07:42:12.64#ibcon#about to write, iclass 22, count 0 2006.245.07:42:12.64#ibcon#wrote, iclass 22, count 0 2006.245.07:42:12.64#ibcon#about to read 3, iclass 22, count 0 2006.245.07:42:12.66#ibcon#read 3, iclass 22, count 0 2006.245.07:42:12.66#ibcon#about to read 4, iclass 22, count 0 2006.245.07:42:12.66#ibcon#read 4, iclass 22, count 0 2006.245.07:42:12.66#ibcon#about to read 5, iclass 22, count 0 2006.245.07:42:12.66#ibcon#read 5, iclass 22, count 0 2006.245.07:42:12.66#ibcon#about to read 6, iclass 22, count 0 2006.245.07:42:12.66#ibcon#read 6, iclass 22, count 0 2006.245.07:42:12.66#ibcon#end of sib2, iclass 22, count 0 2006.245.07:42:12.66#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:42:12.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:42:12.66#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:42:12.66#ibcon#*before write, iclass 22, count 0 2006.245.07:42:12.66#ibcon#enter sib2, iclass 22, count 0 2006.245.07:42:12.66#ibcon#flushed, iclass 22, count 0 2006.245.07:42:12.66#ibcon#about to write, iclass 22, count 0 2006.245.07:42:12.66#ibcon#wrote, iclass 22, count 0 2006.245.07:42:12.66#ibcon#about to read 3, iclass 22, count 0 2006.245.07:42:12.70#ibcon#read 3, iclass 22, count 0 2006.245.07:42:12.70#ibcon#about to read 4, iclass 22, count 0 2006.245.07:42:12.70#ibcon#read 4, iclass 22, count 0 2006.245.07:42:12.70#ibcon#about to read 5, iclass 22, count 0 2006.245.07:42:12.70#ibcon#read 5, iclass 22, count 0 2006.245.07:42:12.70#ibcon#about to read 6, iclass 22, count 0 2006.245.07:42:12.70#ibcon#read 6, iclass 22, count 0 2006.245.07:42:12.70#ibcon#end of sib2, iclass 22, count 0 2006.245.07:42:12.70#ibcon#*after write, iclass 22, count 0 2006.245.07:42:12.70#ibcon#*before return 0, iclass 22, count 0 2006.245.07:42:12.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:12.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:12.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:42:12.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:42:12.70$vc4f8/va=7,7 2006.245.07:42:12.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.07:42:12.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.07:42:12.70#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:12.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:42:12.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:42:12.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:42:12.76#ibcon#enter wrdev, iclass 24, count 2 2006.245.07:42:12.76#ibcon#first serial, iclass 24, count 2 2006.245.07:42:12.76#ibcon#enter sib2, iclass 24, count 2 2006.245.07:42:12.76#ibcon#flushed, iclass 24, count 2 2006.245.07:42:12.76#ibcon#about to write, iclass 24, count 2 2006.245.07:42:12.76#ibcon#wrote, iclass 24, count 2 2006.245.07:42:12.76#ibcon#about to read 3, iclass 24, count 2 2006.245.07:42:12.78#ibcon#read 3, iclass 24, count 2 2006.245.07:42:12.78#ibcon#about to read 4, iclass 24, count 2 2006.245.07:42:12.78#ibcon#read 4, iclass 24, count 2 2006.245.07:42:12.78#ibcon#about to read 5, iclass 24, count 2 2006.245.07:42:12.78#ibcon#read 5, iclass 24, count 2 2006.245.07:42:12.78#ibcon#about to read 6, iclass 24, count 2 2006.245.07:42:12.78#ibcon#read 6, iclass 24, count 2 2006.245.07:42:12.78#ibcon#end of sib2, iclass 24, count 2 2006.245.07:42:12.78#ibcon#*mode == 0, iclass 24, count 2 2006.245.07:42:12.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.07:42:12.78#ibcon#[25=AT07-07\r\n] 2006.245.07:42:12.78#ibcon#*before write, iclass 24, count 2 2006.245.07:42:12.78#ibcon#enter sib2, iclass 24, count 2 2006.245.07:42:12.78#ibcon#flushed, iclass 24, count 2 2006.245.07:42:12.78#ibcon#about to write, iclass 24, count 2 2006.245.07:42:12.78#ibcon#wrote, iclass 24, count 2 2006.245.07:42:12.78#ibcon#about to read 3, iclass 24, count 2 2006.245.07:42:12.81#ibcon#read 3, iclass 24, count 2 2006.245.07:42:12.81#ibcon#about to read 4, iclass 24, count 2 2006.245.07:42:12.81#ibcon#read 4, iclass 24, count 2 2006.245.07:42:12.81#ibcon#about to read 5, iclass 24, count 2 2006.245.07:42:12.81#ibcon#read 5, iclass 24, count 2 2006.245.07:42:12.81#ibcon#about to read 6, iclass 24, count 2 2006.245.07:42:12.81#ibcon#read 6, iclass 24, count 2 2006.245.07:42:12.81#ibcon#end of sib2, iclass 24, count 2 2006.245.07:42:12.81#ibcon#*after write, iclass 24, count 2 2006.245.07:42:12.81#ibcon#*before return 0, iclass 24, count 2 2006.245.07:42:12.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:42:12.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:42:12.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.07:42:12.81#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:12.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:42:12.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:42:12.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:42:12.93#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:42:12.93#ibcon#first serial, iclass 24, count 0 2006.245.07:42:12.93#ibcon#enter sib2, iclass 24, count 0 2006.245.07:42:12.93#ibcon#flushed, iclass 24, count 0 2006.245.07:42:12.93#ibcon#about to write, iclass 24, count 0 2006.245.07:42:12.93#ibcon#wrote, iclass 24, count 0 2006.245.07:42:12.93#ibcon#about to read 3, iclass 24, count 0 2006.245.07:42:12.95#ibcon#read 3, iclass 24, count 0 2006.245.07:42:12.95#ibcon#about to read 4, iclass 24, count 0 2006.245.07:42:12.95#ibcon#read 4, iclass 24, count 0 2006.245.07:42:12.95#ibcon#about to read 5, iclass 24, count 0 2006.245.07:42:12.95#ibcon#read 5, iclass 24, count 0 2006.245.07:42:12.95#ibcon#about to read 6, iclass 24, count 0 2006.245.07:42:12.95#ibcon#read 6, iclass 24, count 0 2006.245.07:42:12.95#ibcon#end of sib2, iclass 24, count 0 2006.245.07:42:12.95#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:42:12.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:42:12.95#ibcon#[25=USB\r\n] 2006.245.07:42:12.95#ibcon#*before write, iclass 24, count 0 2006.245.07:42:12.95#ibcon#enter sib2, iclass 24, count 0 2006.245.07:42:12.95#ibcon#flushed, iclass 24, count 0 2006.245.07:42:12.95#ibcon#about to write, iclass 24, count 0 2006.245.07:42:12.95#ibcon#wrote, iclass 24, count 0 2006.245.07:42:12.95#ibcon#about to read 3, iclass 24, count 0 2006.245.07:42:12.98#ibcon#read 3, iclass 24, count 0 2006.245.07:42:12.98#ibcon#about to read 4, iclass 24, count 0 2006.245.07:42:12.98#ibcon#read 4, iclass 24, count 0 2006.245.07:42:12.98#ibcon#about to read 5, iclass 24, count 0 2006.245.07:42:12.98#ibcon#read 5, iclass 24, count 0 2006.245.07:42:12.98#ibcon#about to read 6, iclass 24, count 0 2006.245.07:42:12.98#ibcon#read 6, iclass 24, count 0 2006.245.07:42:12.98#ibcon#end of sib2, iclass 24, count 0 2006.245.07:42:12.98#ibcon#*after write, iclass 24, count 0 2006.245.07:42:12.98#ibcon#*before return 0, iclass 24, count 0 2006.245.07:42:12.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:42:12.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:42:12.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:42:12.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:42:12.98$vc4f8/valo=8,852.99 2006.245.07:42:12.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.07:42:12.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.07:42:12.98#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:12.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:42:12.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:42:12.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:42:12.98#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:42:12.98#ibcon#first serial, iclass 26, count 0 2006.245.07:42:12.98#ibcon#enter sib2, iclass 26, count 0 2006.245.07:42:12.98#ibcon#flushed, iclass 26, count 0 2006.245.07:42:12.98#ibcon#about to write, iclass 26, count 0 2006.245.07:42:12.98#ibcon#wrote, iclass 26, count 0 2006.245.07:42:12.98#ibcon#about to read 3, iclass 26, count 0 2006.245.07:42:13.00#ibcon#read 3, iclass 26, count 0 2006.245.07:42:13.00#ibcon#about to read 4, iclass 26, count 0 2006.245.07:42:13.00#ibcon#read 4, iclass 26, count 0 2006.245.07:42:13.00#ibcon#about to read 5, iclass 26, count 0 2006.245.07:42:13.00#ibcon#read 5, iclass 26, count 0 2006.245.07:42:13.00#ibcon#about to read 6, iclass 26, count 0 2006.245.07:42:13.00#ibcon#read 6, iclass 26, count 0 2006.245.07:42:13.00#ibcon#end of sib2, iclass 26, count 0 2006.245.07:42:13.00#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:42:13.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:42:13.00#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:42:13.00#ibcon#*before write, iclass 26, count 0 2006.245.07:42:13.00#ibcon#enter sib2, iclass 26, count 0 2006.245.07:42:13.00#ibcon#flushed, iclass 26, count 0 2006.245.07:42:13.00#ibcon#about to write, iclass 26, count 0 2006.245.07:42:13.00#ibcon#wrote, iclass 26, count 0 2006.245.07:42:13.00#ibcon#about to read 3, iclass 26, count 0 2006.245.07:42:13.04#ibcon#read 3, iclass 26, count 0 2006.245.07:42:13.04#ibcon#about to read 4, iclass 26, count 0 2006.245.07:42:13.04#ibcon#read 4, iclass 26, count 0 2006.245.07:42:13.04#ibcon#about to read 5, iclass 26, count 0 2006.245.07:42:13.04#ibcon#read 5, iclass 26, count 0 2006.245.07:42:13.04#ibcon#about to read 6, iclass 26, count 0 2006.245.07:42:13.04#ibcon#read 6, iclass 26, count 0 2006.245.07:42:13.04#ibcon#end of sib2, iclass 26, count 0 2006.245.07:42:13.04#ibcon#*after write, iclass 26, count 0 2006.245.07:42:13.04#ibcon#*before return 0, iclass 26, count 0 2006.245.07:42:13.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:42:13.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:42:13.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:42:13.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:42:13.04$vc4f8/va=8,8 2006.245.07:42:13.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.07:42:13.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.07:42:13.04#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:13.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:42:13.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:42:13.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:42:13.10#ibcon#enter wrdev, iclass 28, count 2 2006.245.07:42:13.10#ibcon#first serial, iclass 28, count 2 2006.245.07:42:13.10#ibcon#enter sib2, iclass 28, count 2 2006.245.07:42:13.10#ibcon#flushed, iclass 28, count 2 2006.245.07:42:13.10#ibcon#about to write, iclass 28, count 2 2006.245.07:42:13.10#ibcon#wrote, iclass 28, count 2 2006.245.07:42:13.10#ibcon#about to read 3, iclass 28, count 2 2006.245.07:42:13.12#ibcon#read 3, iclass 28, count 2 2006.245.07:42:13.12#ibcon#about to read 4, iclass 28, count 2 2006.245.07:42:13.12#ibcon#read 4, iclass 28, count 2 2006.245.07:42:13.12#ibcon#about to read 5, iclass 28, count 2 2006.245.07:42:13.12#ibcon#read 5, iclass 28, count 2 2006.245.07:42:13.12#ibcon#about to read 6, iclass 28, count 2 2006.245.07:42:13.12#ibcon#read 6, iclass 28, count 2 2006.245.07:42:13.12#ibcon#end of sib2, iclass 28, count 2 2006.245.07:42:13.12#ibcon#*mode == 0, iclass 28, count 2 2006.245.07:42:13.12#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.07:42:13.12#ibcon#[25=AT08-08\r\n] 2006.245.07:42:13.12#ibcon#*before write, iclass 28, count 2 2006.245.07:42:13.12#ibcon#enter sib2, iclass 28, count 2 2006.245.07:42:13.12#ibcon#flushed, iclass 28, count 2 2006.245.07:42:13.12#ibcon#about to write, iclass 28, count 2 2006.245.07:42:13.12#ibcon#wrote, iclass 28, count 2 2006.245.07:42:13.12#ibcon#about to read 3, iclass 28, count 2 2006.245.07:42:13.15#ibcon#read 3, iclass 28, count 2 2006.245.07:42:13.15#ibcon#about to read 4, iclass 28, count 2 2006.245.07:42:13.15#ibcon#read 4, iclass 28, count 2 2006.245.07:42:13.15#ibcon#about to read 5, iclass 28, count 2 2006.245.07:42:13.15#ibcon#read 5, iclass 28, count 2 2006.245.07:42:13.15#ibcon#about to read 6, iclass 28, count 2 2006.245.07:42:13.15#ibcon#read 6, iclass 28, count 2 2006.245.07:42:13.15#ibcon#end of sib2, iclass 28, count 2 2006.245.07:42:13.15#ibcon#*after write, iclass 28, count 2 2006.245.07:42:13.15#ibcon#*before return 0, iclass 28, count 2 2006.245.07:42:13.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:42:13.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:42:13.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.07:42:13.15#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:13.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:42:13.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:42:13.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:42:13.27#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:42:13.27#ibcon#first serial, iclass 28, count 0 2006.245.07:42:13.27#ibcon#enter sib2, iclass 28, count 0 2006.245.07:42:13.27#ibcon#flushed, iclass 28, count 0 2006.245.07:42:13.27#ibcon#about to write, iclass 28, count 0 2006.245.07:42:13.27#ibcon#wrote, iclass 28, count 0 2006.245.07:42:13.27#ibcon#about to read 3, iclass 28, count 0 2006.245.07:42:13.29#ibcon#read 3, iclass 28, count 0 2006.245.07:42:13.29#ibcon#about to read 4, iclass 28, count 0 2006.245.07:42:13.29#ibcon#read 4, iclass 28, count 0 2006.245.07:42:13.29#ibcon#about to read 5, iclass 28, count 0 2006.245.07:42:13.29#ibcon#read 5, iclass 28, count 0 2006.245.07:42:13.29#ibcon#about to read 6, iclass 28, count 0 2006.245.07:42:13.29#ibcon#read 6, iclass 28, count 0 2006.245.07:42:13.29#ibcon#end of sib2, iclass 28, count 0 2006.245.07:42:13.29#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:42:13.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:42:13.29#ibcon#[25=USB\r\n] 2006.245.07:42:13.29#ibcon#*before write, iclass 28, count 0 2006.245.07:42:13.29#ibcon#enter sib2, iclass 28, count 0 2006.245.07:42:13.29#ibcon#flushed, iclass 28, count 0 2006.245.07:42:13.29#ibcon#about to write, iclass 28, count 0 2006.245.07:42:13.29#ibcon#wrote, iclass 28, count 0 2006.245.07:42:13.29#ibcon#about to read 3, iclass 28, count 0 2006.245.07:42:13.32#ibcon#read 3, iclass 28, count 0 2006.245.07:42:13.32#ibcon#about to read 4, iclass 28, count 0 2006.245.07:42:13.32#ibcon#read 4, iclass 28, count 0 2006.245.07:42:13.32#ibcon#about to read 5, iclass 28, count 0 2006.245.07:42:13.32#ibcon#read 5, iclass 28, count 0 2006.245.07:42:13.32#ibcon#about to read 6, iclass 28, count 0 2006.245.07:42:13.32#ibcon#read 6, iclass 28, count 0 2006.245.07:42:13.32#ibcon#end of sib2, iclass 28, count 0 2006.245.07:42:13.32#ibcon#*after write, iclass 28, count 0 2006.245.07:42:13.32#ibcon#*before return 0, iclass 28, count 0 2006.245.07:42:13.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:42:13.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:42:13.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:42:13.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:42:13.32$vc4f8/vblo=1,632.99 2006.245.07:42:13.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:42:13.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:42:13.32#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:13.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:42:13.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:42:13.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:42:13.32#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:42:13.32#ibcon#first serial, iclass 30, count 0 2006.245.07:42:13.32#ibcon#enter sib2, iclass 30, count 0 2006.245.07:42:13.32#ibcon#flushed, iclass 30, count 0 2006.245.07:42:13.32#ibcon#about to write, iclass 30, count 0 2006.245.07:42:13.32#ibcon#wrote, iclass 30, count 0 2006.245.07:42:13.32#ibcon#about to read 3, iclass 30, count 0 2006.245.07:42:13.34#ibcon#read 3, iclass 30, count 0 2006.245.07:42:13.34#ibcon#about to read 4, iclass 30, count 0 2006.245.07:42:13.34#ibcon#read 4, iclass 30, count 0 2006.245.07:42:13.34#ibcon#about to read 5, iclass 30, count 0 2006.245.07:42:13.34#ibcon#read 5, iclass 30, count 0 2006.245.07:42:13.34#ibcon#about to read 6, iclass 30, count 0 2006.245.07:42:13.34#ibcon#read 6, iclass 30, count 0 2006.245.07:42:13.34#ibcon#end of sib2, iclass 30, count 0 2006.245.07:42:13.34#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:42:13.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:42:13.34#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:42:13.34#ibcon#*before write, iclass 30, count 0 2006.245.07:42:13.34#ibcon#enter sib2, iclass 30, count 0 2006.245.07:42:13.34#ibcon#flushed, iclass 30, count 0 2006.245.07:42:13.34#ibcon#about to write, iclass 30, count 0 2006.245.07:42:13.34#ibcon#wrote, iclass 30, count 0 2006.245.07:42:13.34#ibcon#about to read 3, iclass 30, count 0 2006.245.07:42:13.38#ibcon#read 3, iclass 30, count 0 2006.245.07:42:13.38#ibcon#about to read 4, iclass 30, count 0 2006.245.07:42:13.38#ibcon#read 4, iclass 30, count 0 2006.245.07:42:13.38#ibcon#about to read 5, iclass 30, count 0 2006.245.07:42:13.38#ibcon#read 5, iclass 30, count 0 2006.245.07:42:13.38#ibcon#about to read 6, iclass 30, count 0 2006.245.07:42:13.38#ibcon#read 6, iclass 30, count 0 2006.245.07:42:13.38#ibcon#end of sib2, iclass 30, count 0 2006.245.07:42:13.38#ibcon#*after write, iclass 30, count 0 2006.245.07:42:13.38#ibcon#*before return 0, iclass 30, count 0 2006.245.07:42:13.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:42:13.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:42:13.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:42:13.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:42:13.38$vc4f8/vb=1,4 2006.245.07:42:13.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.07:42:13.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.07:42:13.38#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:13.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:42:13.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:42:13.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:42:13.38#ibcon#enter wrdev, iclass 32, count 2 2006.245.07:42:13.38#ibcon#first serial, iclass 32, count 2 2006.245.07:42:13.38#ibcon#enter sib2, iclass 32, count 2 2006.245.07:42:13.38#ibcon#flushed, iclass 32, count 2 2006.245.07:42:13.38#ibcon#about to write, iclass 32, count 2 2006.245.07:42:13.38#ibcon#wrote, iclass 32, count 2 2006.245.07:42:13.38#ibcon#about to read 3, iclass 32, count 2 2006.245.07:42:13.40#ibcon#read 3, iclass 32, count 2 2006.245.07:42:13.40#ibcon#about to read 4, iclass 32, count 2 2006.245.07:42:13.40#ibcon#read 4, iclass 32, count 2 2006.245.07:42:13.40#ibcon#about to read 5, iclass 32, count 2 2006.245.07:42:13.40#ibcon#read 5, iclass 32, count 2 2006.245.07:42:13.40#ibcon#about to read 6, iclass 32, count 2 2006.245.07:42:13.40#ibcon#read 6, iclass 32, count 2 2006.245.07:42:13.40#ibcon#end of sib2, iclass 32, count 2 2006.245.07:42:13.40#ibcon#*mode == 0, iclass 32, count 2 2006.245.07:42:13.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.07:42:13.40#ibcon#[27=AT01-04\r\n] 2006.245.07:42:13.40#ibcon#*before write, iclass 32, count 2 2006.245.07:42:13.40#ibcon#enter sib2, iclass 32, count 2 2006.245.07:42:13.40#ibcon#flushed, iclass 32, count 2 2006.245.07:42:13.40#ibcon#about to write, iclass 32, count 2 2006.245.07:42:13.40#ibcon#wrote, iclass 32, count 2 2006.245.07:42:13.40#ibcon#about to read 3, iclass 32, count 2 2006.245.07:42:13.43#ibcon#read 3, iclass 32, count 2 2006.245.07:42:13.43#ibcon#about to read 4, iclass 32, count 2 2006.245.07:42:13.43#ibcon#read 4, iclass 32, count 2 2006.245.07:42:13.43#ibcon#about to read 5, iclass 32, count 2 2006.245.07:42:13.43#ibcon#read 5, iclass 32, count 2 2006.245.07:42:13.43#ibcon#about to read 6, iclass 32, count 2 2006.245.07:42:13.43#ibcon#read 6, iclass 32, count 2 2006.245.07:42:13.43#ibcon#end of sib2, iclass 32, count 2 2006.245.07:42:13.43#ibcon#*after write, iclass 32, count 2 2006.245.07:42:13.43#ibcon#*before return 0, iclass 32, count 2 2006.245.07:42:13.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:42:13.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:42:13.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.07:42:13.43#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:13.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:42:13.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:42:13.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:42:13.55#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:42:13.55#ibcon#first serial, iclass 32, count 0 2006.245.07:42:13.55#ibcon#enter sib2, iclass 32, count 0 2006.245.07:42:13.55#ibcon#flushed, iclass 32, count 0 2006.245.07:42:13.55#ibcon#about to write, iclass 32, count 0 2006.245.07:42:13.55#ibcon#wrote, iclass 32, count 0 2006.245.07:42:13.55#ibcon#about to read 3, iclass 32, count 0 2006.245.07:42:13.57#ibcon#read 3, iclass 32, count 0 2006.245.07:42:13.57#ibcon#about to read 4, iclass 32, count 0 2006.245.07:42:13.57#ibcon#read 4, iclass 32, count 0 2006.245.07:42:13.57#ibcon#about to read 5, iclass 32, count 0 2006.245.07:42:13.57#ibcon#read 5, iclass 32, count 0 2006.245.07:42:13.57#ibcon#about to read 6, iclass 32, count 0 2006.245.07:42:13.57#ibcon#read 6, iclass 32, count 0 2006.245.07:42:13.57#ibcon#end of sib2, iclass 32, count 0 2006.245.07:42:13.57#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:42:13.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:42:13.57#ibcon#[27=USB\r\n] 2006.245.07:42:13.57#ibcon#*before write, iclass 32, count 0 2006.245.07:42:13.57#ibcon#enter sib2, iclass 32, count 0 2006.245.07:42:13.57#ibcon#flushed, iclass 32, count 0 2006.245.07:42:13.57#ibcon#about to write, iclass 32, count 0 2006.245.07:42:13.57#ibcon#wrote, iclass 32, count 0 2006.245.07:42:13.57#ibcon#about to read 3, iclass 32, count 0 2006.245.07:42:13.60#ibcon#read 3, iclass 32, count 0 2006.245.07:42:13.60#ibcon#about to read 4, iclass 32, count 0 2006.245.07:42:13.60#ibcon#read 4, iclass 32, count 0 2006.245.07:42:13.60#ibcon#about to read 5, iclass 32, count 0 2006.245.07:42:13.60#ibcon#read 5, iclass 32, count 0 2006.245.07:42:13.60#ibcon#about to read 6, iclass 32, count 0 2006.245.07:42:13.60#ibcon#read 6, iclass 32, count 0 2006.245.07:42:13.60#ibcon#end of sib2, iclass 32, count 0 2006.245.07:42:13.60#ibcon#*after write, iclass 32, count 0 2006.245.07:42:13.60#ibcon#*before return 0, iclass 32, count 0 2006.245.07:42:13.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:42:13.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:42:13.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:42:13.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:42:13.60$vc4f8/vblo=2,640.99 2006.245.07:42:13.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:42:13.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:42:13.60#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:13.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:13.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:13.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:13.60#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:42:13.60#ibcon#first serial, iclass 34, count 0 2006.245.07:42:13.60#ibcon#enter sib2, iclass 34, count 0 2006.245.07:42:13.60#ibcon#flushed, iclass 34, count 0 2006.245.07:42:13.60#ibcon#about to write, iclass 34, count 0 2006.245.07:42:13.60#ibcon#wrote, iclass 34, count 0 2006.245.07:42:13.60#ibcon#about to read 3, iclass 34, count 0 2006.245.07:42:13.62#ibcon#read 3, iclass 34, count 0 2006.245.07:42:13.62#ibcon#about to read 4, iclass 34, count 0 2006.245.07:42:13.62#ibcon#read 4, iclass 34, count 0 2006.245.07:42:13.62#ibcon#about to read 5, iclass 34, count 0 2006.245.07:42:13.62#ibcon#read 5, iclass 34, count 0 2006.245.07:42:13.62#ibcon#about to read 6, iclass 34, count 0 2006.245.07:42:13.62#ibcon#read 6, iclass 34, count 0 2006.245.07:42:13.62#ibcon#end of sib2, iclass 34, count 0 2006.245.07:42:13.62#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:42:13.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:42:13.62#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:42:13.62#ibcon#*before write, iclass 34, count 0 2006.245.07:42:13.62#ibcon#enter sib2, iclass 34, count 0 2006.245.07:42:13.62#ibcon#flushed, iclass 34, count 0 2006.245.07:42:13.62#ibcon#about to write, iclass 34, count 0 2006.245.07:42:13.62#ibcon#wrote, iclass 34, count 0 2006.245.07:42:13.62#ibcon#about to read 3, iclass 34, count 0 2006.245.07:42:13.66#ibcon#read 3, iclass 34, count 0 2006.245.07:42:13.66#ibcon#about to read 4, iclass 34, count 0 2006.245.07:42:13.66#ibcon#read 4, iclass 34, count 0 2006.245.07:42:13.66#ibcon#about to read 5, iclass 34, count 0 2006.245.07:42:13.66#ibcon#read 5, iclass 34, count 0 2006.245.07:42:13.66#ibcon#about to read 6, iclass 34, count 0 2006.245.07:42:13.66#ibcon#read 6, iclass 34, count 0 2006.245.07:42:13.66#ibcon#end of sib2, iclass 34, count 0 2006.245.07:42:13.66#ibcon#*after write, iclass 34, count 0 2006.245.07:42:13.66#ibcon#*before return 0, iclass 34, count 0 2006.245.07:42:13.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:13.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:42:13.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:42:13.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:42:13.66$vc4f8/vb=2,4 2006.245.07:42:13.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:42:13.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:42:13.66#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:13.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:13.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:13.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:13.72#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:42:13.72#ibcon#first serial, iclass 36, count 2 2006.245.07:42:13.72#ibcon#enter sib2, iclass 36, count 2 2006.245.07:42:13.72#ibcon#flushed, iclass 36, count 2 2006.245.07:42:13.72#ibcon#about to write, iclass 36, count 2 2006.245.07:42:13.72#ibcon#wrote, iclass 36, count 2 2006.245.07:42:13.72#ibcon#about to read 3, iclass 36, count 2 2006.245.07:42:13.74#ibcon#read 3, iclass 36, count 2 2006.245.07:42:13.74#ibcon#about to read 4, iclass 36, count 2 2006.245.07:42:13.74#ibcon#read 4, iclass 36, count 2 2006.245.07:42:13.74#ibcon#about to read 5, iclass 36, count 2 2006.245.07:42:13.74#ibcon#read 5, iclass 36, count 2 2006.245.07:42:13.74#ibcon#about to read 6, iclass 36, count 2 2006.245.07:42:13.74#ibcon#read 6, iclass 36, count 2 2006.245.07:42:13.74#ibcon#end of sib2, iclass 36, count 2 2006.245.07:42:13.74#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:42:13.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:42:13.74#ibcon#[27=AT02-04\r\n] 2006.245.07:42:13.74#ibcon#*before write, iclass 36, count 2 2006.245.07:42:13.74#ibcon#enter sib2, iclass 36, count 2 2006.245.07:42:13.74#ibcon#flushed, iclass 36, count 2 2006.245.07:42:13.74#ibcon#about to write, iclass 36, count 2 2006.245.07:42:13.74#ibcon#wrote, iclass 36, count 2 2006.245.07:42:13.74#ibcon#about to read 3, iclass 36, count 2 2006.245.07:42:13.77#ibcon#read 3, iclass 36, count 2 2006.245.07:42:13.77#ibcon#about to read 4, iclass 36, count 2 2006.245.07:42:13.77#ibcon#read 4, iclass 36, count 2 2006.245.07:42:13.77#ibcon#about to read 5, iclass 36, count 2 2006.245.07:42:13.77#ibcon#read 5, iclass 36, count 2 2006.245.07:42:13.77#ibcon#about to read 6, iclass 36, count 2 2006.245.07:42:13.77#ibcon#read 6, iclass 36, count 2 2006.245.07:42:13.77#ibcon#end of sib2, iclass 36, count 2 2006.245.07:42:13.77#ibcon#*after write, iclass 36, count 2 2006.245.07:42:13.77#ibcon#*before return 0, iclass 36, count 2 2006.245.07:42:13.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:13.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:42:13.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:42:13.77#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:13.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:13.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:13.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:13.89#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:42:13.89#ibcon#first serial, iclass 36, count 0 2006.245.07:42:13.89#ibcon#enter sib2, iclass 36, count 0 2006.245.07:42:13.89#ibcon#flushed, iclass 36, count 0 2006.245.07:42:13.89#ibcon#about to write, iclass 36, count 0 2006.245.07:42:13.89#ibcon#wrote, iclass 36, count 0 2006.245.07:42:13.89#ibcon#about to read 3, iclass 36, count 0 2006.245.07:42:13.91#ibcon#read 3, iclass 36, count 0 2006.245.07:42:13.91#ibcon#about to read 4, iclass 36, count 0 2006.245.07:42:13.91#ibcon#read 4, iclass 36, count 0 2006.245.07:42:13.91#ibcon#about to read 5, iclass 36, count 0 2006.245.07:42:13.91#ibcon#read 5, iclass 36, count 0 2006.245.07:42:13.91#ibcon#about to read 6, iclass 36, count 0 2006.245.07:42:13.91#ibcon#read 6, iclass 36, count 0 2006.245.07:42:13.91#ibcon#end of sib2, iclass 36, count 0 2006.245.07:42:13.91#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:42:13.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:42:13.91#ibcon#[27=USB\r\n] 2006.245.07:42:13.91#ibcon#*before write, iclass 36, count 0 2006.245.07:42:13.91#ibcon#enter sib2, iclass 36, count 0 2006.245.07:42:13.91#ibcon#flushed, iclass 36, count 0 2006.245.07:42:13.91#ibcon#about to write, iclass 36, count 0 2006.245.07:42:13.91#ibcon#wrote, iclass 36, count 0 2006.245.07:42:13.91#ibcon#about to read 3, iclass 36, count 0 2006.245.07:42:13.94#ibcon#read 3, iclass 36, count 0 2006.245.07:42:13.94#ibcon#about to read 4, iclass 36, count 0 2006.245.07:42:13.94#ibcon#read 4, iclass 36, count 0 2006.245.07:42:13.94#ibcon#about to read 5, iclass 36, count 0 2006.245.07:42:13.94#ibcon#read 5, iclass 36, count 0 2006.245.07:42:13.94#ibcon#about to read 6, iclass 36, count 0 2006.245.07:42:13.94#ibcon#read 6, iclass 36, count 0 2006.245.07:42:13.94#ibcon#end of sib2, iclass 36, count 0 2006.245.07:42:13.94#ibcon#*after write, iclass 36, count 0 2006.245.07:42:13.94#ibcon#*before return 0, iclass 36, count 0 2006.245.07:42:13.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:13.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:42:13.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:42:13.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:42:13.94$vc4f8/vblo=3,656.99 2006.245.07:42:13.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:42:13.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:42:13.94#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:13.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:13.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:13.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:13.94#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:42:13.94#ibcon#first serial, iclass 38, count 0 2006.245.07:42:13.94#ibcon#enter sib2, iclass 38, count 0 2006.245.07:42:13.94#ibcon#flushed, iclass 38, count 0 2006.245.07:42:13.94#ibcon#about to write, iclass 38, count 0 2006.245.07:42:13.94#ibcon#wrote, iclass 38, count 0 2006.245.07:42:13.94#ibcon#about to read 3, iclass 38, count 0 2006.245.07:42:13.96#ibcon#read 3, iclass 38, count 0 2006.245.07:42:13.96#ibcon#about to read 4, iclass 38, count 0 2006.245.07:42:13.96#ibcon#read 4, iclass 38, count 0 2006.245.07:42:13.96#ibcon#about to read 5, iclass 38, count 0 2006.245.07:42:13.96#ibcon#read 5, iclass 38, count 0 2006.245.07:42:13.96#ibcon#about to read 6, iclass 38, count 0 2006.245.07:42:13.96#ibcon#read 6, iclass 38, count 0 2006.245.07:42:13.96#ibcon#end of sib2, iclass 38, count 0 2006.245.07:42:13.96#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:42:13.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:42:13.96#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:42:13.96#ibcon#*before write, iclass 38, count 0 2006.245.07:42:13.96#ibcon#enter sib2, iclass 38, count 0 2006.245.07:42:13.96#ibcon#flushed, iclass 38, count 0 2006.245.07:42:13.96#ibcon#about to write, iclass 38, count 0 2006.245.07:42:13.96#ibcon#wrote, iclass 38, count 0 2006.245.07:42:13.96#ibcon#about to read 3, iclass 38, count 0 2006.245.07:42:14.01#ibcon#read 3, iclass 38, count 0 2006.245.07:42:14.01#ibcon#about to read 4, iclass 38, count 0 2006.245.07:42:14.01#ibcon#read 4, iclass 38, count 0 2006.245.07:42:14.01#ibcon#about to read 5, iclass 38, count 0 2006.245.07:42:14.01#ibcon#read 5, iclass 38, count 0 2006.245.07:42:14.01#ibcon#about to read 6, iclass 38, count 0 2006.245.07:42:14.01#ibcon#read 6, iclass 38, count 0 2006.245.07:42:14.01#ibcon#end of sib2, iclass 38, count 0 2006.245.07:42:14.01#ibcon#*after write, iclass 38, count 0 2006.245.07:42:14.01#ibcon#*before return 0, iclass 38, count 0 2006.245.07:42:14.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:14.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:42:14.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:42:14.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:42:14.01$vc4f8/vb=3,4 2006.245.07:42:14.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:42:14.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:42:14.01#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:14.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:14.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:14.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:14.06#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:42:14.06#ibcon#first serial, iclass 40, count 2 2006.245.07:42:14.06#ibcon#enter sib2, iclass 40, count 2 2006.245.07:42:14.06#ibcon#flushed, iclass 40, count 2 2006.245.07:42:14.06#ibcon#about to write, iclass 40, count 2 2006.245.07:42:14.06#ibcon#wrote, iclass 40, count 2 2006.245.07:42:14.06#ibcon#about to read 3, iclass 40, count 2 2006.245.07:42:14.08#ibcon#read 3, iclass 40, count 2 2006.245.07:42:14.08#ibcon#about to read 4, iclass 40, count 2 2006.245.07:42:14.08#ibcon#read 4, iclass 40, count 2 2006.245.07:42:14.08#ibcon#about to read 5, iclass 40, count 2 2006.245.07:42:14.08#ibcon#read 5, iclass 40, count 2 2006.245.07:42:14.08#ibcon#about to read 6, iclass 40, count 2 2006.245.07:42:14.08#ibcon#read 6, iclass 40, count 2 2006.245.07:42:14.08#ibcon#end of sib2, iclass 40, count 2 2006.245.07:42:14.08#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:42:14.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:42:14.08#ibcon#[27=AT03-04\r\n] 2006.245.07:42:14.08#ibcon#*before write, iclass 40, count 2 2006.245.07:42:14.08#ibcon#enter sib2, iclass 40, count 2 2006.245.07:42:14.08#ibcon#flushed, iclass 40, count 2 2006.245.07:42:14.08#ibcon#about to write, iclass 40, count 2 2006.245.07:42:14.08#ibcon#wrote, iclass 40, count 2 2006.245.07:42:14.08#ibcon#about to read 3, iclass 40, count 2 2006.245.07:42:14.11#ibcon#read 3, iclass 40, count 2 2006.245.07:42:14.11#ibcon#about to read 4, iclass 40, count 2 2006.245.07:42:14.11#ibcon#read 4, iclass 40, count 2 2006.245.07:42:14.11#ibcon#about to read 5, iclass 40, count 2 2006.245.07:42:14.11#ibcon#read 5, iclass 40, count 2 2006.245.07:42:14.11#ibcon#about to read 6, iclass 40, count 2 2006.245.07:42:14.11#ibcon#read 6, iclass 40, count 2 2006.245.07:42:14.11#ibcon#end of sib2, iclass 40, count 2 2006.245.07:42:14.11#ibcon#*after write, iclass 40, count 2 2006.245.07:42:14.11#ibcon#*before return 0, iclass 40, count 2 2006.245.07:42:14.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:14.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:42:14.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:42:14.11#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:14.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:14.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:14.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:14.23#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:42:14.23#ibcon#first serial, iclass 40, count 0 2006.245.07:42:14.23#ibcon#enter sib2, iclass 40, count 0 2006.245.07:42:14.23#ibcon#flushed, iclass 40, count 0 2006.245.07:42:14.23#ibcon#about to write, iclass 40, count 0 2006.245.07:42:14.23#ibcon#wrote, iclass 40, count 0 2006.245.07:42:14.23#ibcon#about to read 3, iclass 40, count 0 2006.245.07:42:14.25#ibcon#read 3, iclass 40, count 0 2006.245.07:42:14.25#ibcon#about to read 4, iclass 40, count 0 2006.245.07:42:14.25#ibcon#read 4, iclass 40, count 0 2006.245.07:42:14.25#ibcon#about to read 5, iclass 40, count 0 2006.245.07:42:14.25#ibcon#read 5, iclass 40, count 0 2006.245.07:42:14.25#ibcon#about to read 6, iclass 40, count 0 2006.245.07:42:14.25#ibcon#read 6, iclass 40, count 0 2006.245.07:42:14.25#ibcon#end of sib2, iclass 40, count 0 2006.245.07:42:14.25#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:42:14.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:42:14.25#ibcon#[27=USB\r\n] 2006.245.07:42:14.25#ibcon#*before write, iclass 40, count 0 2006.245.07:42:14.25#ibcon#enter sib2, iclass 40, count 0 2006.245.07:42:14.25#ibcon#flushed, iclass 40, count 0 2006.245.07:42:14.25#ibcon#about to write, iclass 40, count 0 2006.245.07:42:14.25#ibcon#wrote, iclass 40, count 0 2006.245.07:42:14.25#ibcon#about to read 3, iclass 40, count 0 2006.245.07:42:14.28#ibcon#read 3, iclass 40, count 0 2006.245.07:42:14.28#ibcon#about to read 4, iclass 40, count 0 2006.245.07:42:14.28#ibcon#read 4, iclass 40, count 0 2006.245.07:42:14.28#ibcon#about to read 5, iclass 40, count 0 2006.245.07:42:14.28#ibcon#read 5, iclass 40, count 0 2006.245.07:42:14.28#ibcon#about to read 6, iclass 40, count 0 2006.245.07:42:14.28#ibcon#read 6, iclass 40, count 0 2006.245.07:42:14.28#ibcon#end of sib2, iclass 40, count 0 2006.245.07:42:14.28#ibcon#*after write, iclass 40, count 0 2006.245.07:42:14.28#ibcon#*before return 0, iclass 40, count 0 2006.245.07:42:14.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:14.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:42:14.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:42:14.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:42:14.28$vc4f8/vblo=4,712.99 2006.245.07:42:14.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:42:14.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:42:14.28#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:14.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:14.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:14.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:14.28#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:42:14.28#ibcon#first serial, iclass 4, count 0 2006.245.07:42:14.28#ibcon#enter sib2, iclass 4, count 0 2006.245.07:42:14.28#ibcon#flushed, iclass 4, count 0 2006.245.07:42:14.28#ibcon#about to write, iclass 4, count 0 2006.245.07:42:14.28#ibcon#wrote, iclass 4, count 0 2006.245.07:42:14.28#ibcon#about to read 3, iclass 4, count 0 2006.245.07:42:14.30#ibcon#read 3, iclass 4, count 0 2006.245.07:42:14.30#ibcon#about to read 4, iclass 4, count 0 2006.245.07:42:14.30#ibcon#read 4, iclass 4, count 0 2006.245.07:42:14.30#ibcon#about to read 5, iclass 4, count 0 2006.245.07:42:14.30#ibcon#read 5, iclass 4, count 0 2006.245.07:42:14.30#ibcon#about to read 6, iclass 4, count 0 2006.245.07:42:14.30#ibcon#read 6, iclass 4, count 0 2006.245.07:42:14.30#ibcon#end of sib2, iclass 4, count 0 2006.245.07:42:14.30#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:42:14.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:42:14.30#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:42:14.30#ibcon#*before write, iclass 4, count 0 2006.245.07:42:14.30#ibcon#enter sib2, iclass 4, count 0 2006.245.07:42:14.30#ibcon#flushed, iclass 4, count 0 2006.245.07:42:14.30#ibcon#about to write, iclass 4, count 0 2006.245.07:42:14.30#ibcon#wrote, iclass 4, count 0 2006.245.07:42:14.30#ibcon#about to read 3, iclass 4, count 0 2006.245.07:42:14.34#ibcon#read 3, iclass 4, count 0 2006.245.07:42:14.34#ibcon#about to read 4, iclass 4, count 0 2006.245.07:42:14.34#ibcon#read 4, iclass 4, count 0 2006.245.07:42:14.34#ibcon#about to read 5, iclass 4, count 0 2006.245.07:42:14.34#ibcon#read 5, iclass 4, count 0 2006.245.07:42:14.34#ibcon#about to read 6, iclass 4, count 0 2006.245.07:42:14.34#ibcon#read 6, iclass 4, count 0 2006.245.07:42:14.34#ibcon#end of sib2, iclass 4, count 0 2006.245.07:42:14.34#ibcon#*after write, iclass 4, count 0 2006.245.07:42:14.34#ibcon#*before return 0, iclass 4, count 0 2006.245.07:42:14.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:14.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:42:14.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:42:14.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:42:14.34$vc4f8/vb=4,4 2006.245.07:42:14.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:42:14.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:42:14.34#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:14.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:14.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:14.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:14.40#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:42:14.40#ibcon#first serial, iclass 6, count 2 2006.245.07:42:14.40#ibcon#enter sib2, iclass 6, count 2 2006.245.07:42:14.40#ibcon#flushed, iclass 6, count 2 2006.245.07:42:14.40#ibcon#about to write, iclass 6, count 2 2006.245.07:42:14.40#ibcon#wrote, iclass 6, count 2 2006.245.07:42:14.40#ibcon#about to read 3, iclass 6, count 2 2006.245.07:42:14.42#ibcon#read 3, iclass 6, count 2 2006.245.07:42:14.42#ibcon#about to read 4, iclass 6, count 2 2006.245.07:42:14.42#ibcon#read 4, iclass 6, count 2 2006.245.07:42:14.42#ibcon#about to read 5, iclass 6, count 2 2006.245.07:42:14.42#ibcon#read 5, iclass 6, count 2 2006.245.07:42:14.42#ibcon#about to read 6, iclass 6, count 2 2006.245.07:42:14.42#ibcon#read 6, iclass 6, count 2 2006.245.07:42:14.42#ibcon#end of sib2, iclass 6, count 2 2006.245.07:42:14.42#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:42:14.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:42:14.42#ibcon#[27=AT04-04\r\n] 2006.245.07:42:14.42#ibcon#*before write, iclass 6, count 2 2006.245.07:42:14.42#ibcon#enter sib2, iclass 6, count 2 2006.245.07:42:14.42#ibcon#flushed, iclass 6, count 2 2006.245.07:42:14.42#ibcon#about to write, iclass 6, count 2 2006.245.07:42:14.42#ibcon#wrote, iclass 6, count 2 2006.245.07:42:14.42#ibcon#about to read 3, iclass 6, count 2 2006.245.07:42:14.45#ibcon#read 3, iclass 6, count 2 2006.245.07:42:14.45#ibcon#about to read 4, iclass 6, count 2 2006.245.07:42:14.45#ibcon#read 4, iclass 6, count 2 2006.245.07:42:14.45#ibcon#about to read 5, iclass 6, count 2 2006.245.07:42:14.45#ibcon#read 5, iclass 6, count 2 2006.245.07:42:14.45#ibcon#about to read 6, iclass 6, count 2 2006.245.07:42:14.45#ibcon#read 6, iclass 6, count 2 2006.245.07:42:14.45#ibcon#end of sib2, iclass 6, count 2 2006.245.07:42:14.45#ibcon#*after write, iclass 6, count 2 2006.245.07:42:14.45#ibcon#*before return 0, iclass 6, count 2 2006.245.07:42:14.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:14.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:42:14.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:42:14.45#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:14.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:14.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:14.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:14.57#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:42:14.57#ibcon#first serial, iclass 6, count 0 2006.245.07:42:14.57#ibcon#enter sib2, iclass 6, count 0 2006.245.07:42:14.57#ibcon#flushed, iclass 6, count 0 2006.245.07:42:14.57#ibcon#about to write, iclass 6, count 0 2006.245.07:42:14.57#ibcon#wrote, iclass 6, count 0 2006.245.07:42:14.57#ibcon#about to read 3, iclass 6, count 0 2006.245.07:42:14.59#ibcon#read 3, iclass 6, count 0 2006.245.07:42:14.59#ibcon#about to read 4, iclass 6, count 0 2006.245.07:42:14.59#ibcon#read 4, iclass 6, count 0 2006.245.07:42:14.59#ibcon#about to read 5, iclass 6, count 0 2006.245.07:42:14.59#ibcon#read 5, iclass 6, count 0 2006.245.07:42:14.59#ibcon#about to read 6, iclass 6, count 0 2006.245.07:42:14.59#ibcon#read 6, iclass 6, count 0 2006.245.07:42:14.59#ibcon#end of sib2, iclass 6, count 0 2006.245.07:42:14.59#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:42:14.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:42:14.59#ibcon#[27=USB\r\n] 2006.245.07:42:14.59#ibcon#*before write, iclass 6, count 0 2006.245.07:42:14.59#ibcon#enter sib2, iclass 6, count 0 2006.245.07:42:14.59#ibcon#flushed, iclass 6, count 0 2006.245.07:42:14.59#ibcon#about to write, iclass 6, count 0 2006.245.07:42:14.59#ibcon#wrote, iclass 6, count 0 2006.245.07:42:14.59#ibcon#about to read 3, iclass 6, count 0 2006.245.07:42:14.62#ibcon#read 3, iclass 6, count 0 2006.245.07:42:14.62#ibcon#about to read 4, iclass 6, count 0 2006.245.07:42:14.62#ibcon#read 4, iclass 6, count 0 2006.245.07:42:14.62#ibcon#about to read 5, iclass 6, count 0 2006.245.07:42:14.62#ibcon#read 5, iclass 6, count 0 2006.245.07:42:14.62#ibcon#about to read 6, iclass 6, count 0 2006.245.07:42:14.62#ibcon#read 6, iclass 6, count 0 2006.245.07:42:14.62#ibcon#end of sib2, iclass 6, count 0 2006.245.07:42:14.62#ibcon#*after write, iclass 6, count 0 2006.245.07:42:14.62#ibcon#*before return 0, iclass 6, count 0 2006.245.07:42:14.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:14.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:42:14.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:42:14.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:42:14.62$vc4f8/vblo=5,744.99 2006.245.07:42:14.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:42:14.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:42:14.62#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:14.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:14.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:14.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:14.62#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:42:14.62#ibcon#first serial, iclass 10, count 0 2006.245.07:42:14.62#ibcon#enter sib2, iclass 10, count 0 2006.245.07:42:14.62#ibcon#flushed, iclass 10, count 0 2006.245.07:42:14.62#ibcon#about to write, iclass 10, count 0 2006.245.07:42:14.62#ibcon#wrote, iclass 10, count 0 2006.245.07:42:14.62#ibcon#about to read 3, iclass 10, count 0 2006.245.07:42:14.64#ibcon#read 3, iclass 10, count 0 2006.245.07:42:14.64#ibcon#about to read 4, iclass 10, count 0 2006.245.07:42:14.64#ibcon#read 4, iclass 10, count 0 2006.245.07:42:14.64#ibcon#about to read 5, iclass 10, count 0 2006.245.07:42:14.64#ibcon#read 5, iclass 10, count 0 2006.245.07:42:14.64#ibcon#about to read 6, iclass 10, count 0 2006.245.07:42:14.64#ibcon#read 6, iclass 10, count 0 2006.245.07:42:14.64#ibcon#end of sib2, iclass 10, count 0 2006.245.07:42:14.64#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:42:14.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:42:14.64#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:42:14.64#ibcon#*before write, iclass 10, count 0 2006.245.07:42:14.64#ibcon#enter sib2, iclass 10, count 0 2006.245.07:42:14.64#ibcon#flushed, iclass 10, count 0 2006.245.07:42:14.64#ibcon#about to write, iclass 10, count 0 2006.245.07:42:14.64#ibcon#wrote, iclass 10, count 0 2006.245.07:42:14.64#ibcon#about to read 3, iclass 10, count 0 2006.245.07:42:14.68#ibcon#read 3, iclass 10, count 0 2006.245.07:42:14.68#ibcon#about to read 4, iclass 10, count 0 2006.245.07:42:14.68#ibcon#read 4, iclass 10, count 0 2006.245.07:42:14.68#ibcon#about to read 5, iclass 10, count 0 2006.245.07:42:14.68#ibcon#read 5, iclass 10, count 0 2006.245.07:42:14.68#ibcon#about to read 6, iclass 10, count 0 2006.245.07:42:14.68#ibcon#read 6, iclass 10, count 0 2006.245.07:42:14.68#ibcon#end of sib2, iclass 10, count 0 2006.245.07:42:14.68#ibcon#*after write, iclass 10, count 0 2006.245.07:42:14.68#ibcon#*before return 0, iclass 10, count 0 2006.245.07:42:14.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:14.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:42:14.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:42:14.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:42:14.68$vc4f8/vb=5,3 2006.245.07:42:14.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:42:14.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:42:14.68#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:14.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:14.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:14.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:14.74#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:42:14.74#ibcon#first serial, iclass 12, count 2 2006.245.07:42:14.74#ibcon#enter sib2, iclass 12, count 2 2006.245.07:42:14.74#ibcon#flushed, iclass 12, count 2 2006.245.07:42:14.74#ibcon#about to write, iclass 12, count 2 2006.245.07:42:14.74#ibcon#wrote, iclass 12, count 2 2006.245.07:42:14.74#ibcon#about to read 3, iclass 12, count 2 2006.245.07:42:14.76#ibcon#read 3, iclass 12, count 2 2006.245.07:42:14.76#ibcon#about to read 4, iclass 12, count 2 2006.245.07:42:14.76#ibcon#read 4, iclass 12, count 2 2006.245.07:42:14.76#ibcon#about to read 5, iclass 12, count 2 2006.245.07:42:14.76#ibcon#read 5, iclass 12, count 2 2006.245.07:42:14.76#ibcon#about to read 6, iclass 12, count 2 2006.245.07:42:14.76#ibcon#read 6, iclass 12, count 2 2006.245.07:42:14.76#ibcon#end of sib2, iclass 12, count 2 2006.245.07:42:14.76#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:42:14.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:42:14.76#ibcon#[27=AT05-03\r\n] 2006.245.07:42:14.76#ibcon#*before write, iclass 12, count 2 2006.245.07:42:14.76#ibcon#enter sib2, iclass 12, count 2 2006.245.07:42:14.76#ibcon#flushed, iclass 12, count 2 2006.245.07:42:14.76#ibcon#about to write, iclass 12, count 2 2006.245.07:42:14.76#ibcon#wrote, iclass 12, count 2 2006.245.07:42:14.76#ibcon#about to read 3, iclass 12, count 2 2006.245.07:42:14.79#abcon#<5=/05 3.3 5.6 27.48 671004.4\r\n> 2006.245.07:42:14.79#ibcon#read 3, iclass 12, count 2 2006.245.07:42:14.79#ibcon#about to read 4, iclass 12, count 2 2006.245.07:42:14.79#ibcon#read 4, iclass 12, count 2 2006.245.07:42:14.79#ibcon#about to read 5, iclass 12, count 2 2006.245.07:42:14.79#ibcon#read 5, iclass 12, count 2 2006.245.07:42:14.79#ibcon#about to read 6, iclass 12, count 2 2006.245.07:42:14.79#ibcon#read 6, iclass 12, count 2 2006.245.07:42:14.79#ibcon#end of sib2, iclass 12, count 2 2006.245.07:42:14.79#ibcon#*after write, iclass 12, count 2 2006.245.07:42:14.79#ibcon#*before return 0, iclass 12, count 2 2006.245.07:42:14.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:14.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:42:14.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:42:14.79#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:14.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:14.81#abcon#{5=INTERFACE CLEAR} 2006.245.07:42:14.87#abcon#[5=S1D000X0/0*\r\n] 2006.245.07:42:14.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:14.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:14.91#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:42:14.91#ibcon#first serial, iclass 12, count 0 2006.245.07:42:14.91#ibcon#enter sib2, iclass 12, count 0 2006.245.07:42:14.91#ibcon#flushed, iclass 12, count 0 2006.245.07:42:14.91#ibcon#about to write, iclass 12, count 0 2006.245.07:42:14.91#ibcon#wrote, iclass 12, count 0 2006.245.07:42:14.91#ibcon#about to read 3, iclass 12, count 0 2006.245.07:42:14.94#ibcon#read 3, iclass 12, count 0 2006.245.07:42:14.94#ibcon#about to read 4, iclass 12, count 0 2006.245.07:42:14.94#ibcon#read 4, iclass 12, count 0 2006.245.07:42:14.94#ibcon#about to read 5, iclass 12, count 0 2006.245.07:42:14.94#ibcon#read 5, iclass 12, count 0 2006.245.07:42:14.94#ibcon#about to read 6, iclass 12, count 0 2006.245.07:42:14.94#ibcon#read 6, iclass 12, count 0 2006.245.07:42:14.94#ibcon#end of sib2, iclass 12, count 0 2006.245.07:42:14.94#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:42:14.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:42:14.94#ibcon#[27=USB\r\n] 2006.245.07:42:14.94#ibcon#*before write, iclass 12, count 0 2006.245.07:42:14.94#ibcon#enter sib2, iclass 12, count 0 2006.245.07:42:14.94#ibcon#flushed, iclass 12, count 0 2006.245.07:42:14.94#ibcon#about to write, iclass 12, count 0 2006.245.07:42:14.94#ibcon#wrote, iclass 12, count 0 2006.245.07:42:14.94#ibcon#about to read 3, iclass 12, count 0 2006.245.07:42:14.97#ibcon#read 3, iclass 12, count 0 2006.245.07:42:14.97#ibcon#about to read 4, iclass 12, count 0 2006.245.07:42:14.97#ibcon#read 4, iclass 12, count 0 2006.245.07:42:14.97#ibcon#about to read 5, iclass 12, count 0 2006.245.07:42:14.97#ibcon#read 5, iclass 12, count 0 2006.245.07:42:14.97#ibcon#about to read 6, iclass 12, count 0 2006.245.07:42:14.97#ibcon#read 6, iclass 12, count 0 2006.245.07:42:14.97#ibcon#end of sib2, iclass 12, count 0 2006.245.07:42:14.97#ibcon#*after write, iclass 12, count 0 2006.245.07:42:14.97#ibcon#*before return 0, iclass 12, count 0 2006.245.07:42:14.97#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:14.97#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:42:14.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:42:14.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:42:14.97$vc4f8/vblo=6,752.99 2006.245.07:42:14.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.07:42:14.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.07:42:14.97#ibcon#ireg 17 cls_cnt 0 2006.245.07:42:14.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:14.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:14.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:14.97#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:42:14.97#ibcon#first serial, iclass 18, count 0 2006.245.07:42:14.97#ibcon#enter sib2, iclass 18, count 0 2006.245.07:42:14.97#ibcon#flushed, iclass 18, count 0 2006.245.07:42:14.97#ibcon#about to write, iclass 18, count 0 2006.245.07:42:14.97#ibcon#wrote, iclass 18, count 0 2006.245.07:42:14.97#ibcon#about to read 3, iclass 18, count 0 2006.245.07:42:14.99#ibcon#read 3, iclass 18, count 0 2006.245.07:42:14.99#ibcon#about to read 4, iclass 18, count 0 2006.245.07:42:14.99#ibcon#read 4, iclass 18, count 0 2006.245.07:42:14.99#ibcon#about to read 5, iclass 18, count 0 2006.245.07:42:14.99#ibcon#read 5, iclass 18, count 0 2006.245.07:42:14.99#ibcon#about to read 6, iclass 18, count 0 2006.245.07:42:14.99#ibcon#read 6, iclass 18, count 0 2006.245.07:42:14.99#ibcon#end of sib2, iclass 18, count 0 2006.245.07:42:14.99#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:42:14.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:42:14.99#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:42:14.99#ibcon#*before write, iclass 18, count 0 2006.245.07:42:14.99#ibcon#enter sib2, iclass 18, count 0 2006.245.07:42:14.99#ibcon#flushed, iclass 18, count 0 2006.245.07:42:14.99#ibcon#about to write, iclass 18, count 0 2006.245.07:42:14.99#ibcon#wrote, iclass 18, count 0 2006.245.07:42:14.99#ibcon#about to read 3, iclass 18, count 0 2006.245.07:42:15.03#ibcon#read 3, iclass 18, count 0 2006.245.07:42:15.03#ibcon#about to read 4, iclass 18, count 0 2006.245.07:42:15.03#ibcon#read 4, iclass 18, count 0 2006.245.07:42:15.03#ibcon#about to read 5, iclass 18, count 0 2006.245.07:42:15.03#ibcon#read 5, iclass 18, count 0 2006.245.07:42:15.03#ibcon#about to read 6, iclass 18, count 0 2006.245.07:42:15.03#ibcon#read 6, iclass 18, count 0 2006.245.07:42:15.03#ibcon#end of sib2, iclass 18, count 0 2006.245.07:42:15.03#ibcon#*after write, iclass 18, count 0 2006.245.07:42:15.03#ibcon#*before return 0, iclass 18, count 0 2006.245.07:42:15.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:15.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:42:15.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:42:15.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:42:15.03$vc4f8/vb=6,3 2006.245.07:42:15.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.07:42:15.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.07:42:15.03#ibcon#ireg 11 cls_cnt 2 2006.245.07:42:15.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:15.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:15.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:15.09#ibcon#enter wrdev, iclass 20, count 2 2006.245.07:42:15.09#ibcon#first serial, iclass 20, count 2 2006.245.07:42:15.09#ibcon#enter sib2, iclass 20, count 2 2006.245.07:42:15.09#ibcon#flushed, iclass 20, count 2 2006.245.07:42:15.09#ibcon#about to write, iclass 20, count 2 2006.245.07:42:15.09#ibcon#wrote, iclass 20, count 2 2006.245.07:42:15.09#ibcon#about to read 3, iclass 20, count 2 2006.245.07:42:15.11#ibcon#read 3, iclass 20, count 2 2006.245.07:42:15.11#ibcon#about to read 4, iclass 20, count 2 2006.245.07:42:15.11#ibcon#read 4, iclass 20, count 2 2006.245.07:42:15.11#ibcon#about to read 5, iclass 20, count 2 2006.245.07:42:15.11#ibcon#read 5, iclass 20, count 2 2006.245.07:42:15.11#ibcon#about to read 6, iclass 20, count 2 2006.245.07:42:15.11#ibcon#read 6, iclass 20, count 2 2006.245.07:42:15.11#ibcon#end of sib2, iclass 20, count 2 2006.245.07:42:15.11#ibcon#*mode == 0, iclass 20, count 2 2006.245.07:42:15.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.07:42:15.11#ibcon#[27=AT06-03\r\n] 2006.245.07:42:15.11#ibcon#*before write, iclass 20, count 2 2006.245.07:42:15.11#ibcon#enter sib2, iclass 20, count 2 2006.245.07:42:15.11#ibcon#flushed, iclass 20, count 2 2006.245.07:42:15.11#ibcon#about to write, iclass 20, count 2 2006.245.07:42:15.11#ibcon#wrote, iclass 20, count 2 2006.245.07:42:15.11#ibcon#about to read 3, iclass 20, count 2 2006.245.07:42:15.14#ibcon#read 3, iclass 20, count 2 2006.245.07:42:15.14#ibcon#about to read 4, iclass 20, count 2 2006.245.07:42:15.14#ibcon#read 4, iclass 20, count 2 2006.245.07:42:15.14#ibcon#about to read 5, iclass 20, count 2 2006.245.07:42:15.14#ibcon#read 5, iclass 20, count 2 2006.245.07:42:15.14#ibcon#about to read 6, iclass 20, count 2 2006.245.07:42:15.14#ibcon#read 6, iclass 20, count 2 2006.245.07:42:15.14#ibcon#end of sib2, iclass 20, count 2 2006.245.07:42:15.14#ibcon#*after write, iclass 20, count 2 2006.245.07:42:15.14#ibcon#*before return 0, iclass 20, count 2 2006.245.07:42:15.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:15.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:42:15.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.07:42:15.14#ibcon#ireg 7 cls_cnt 0 2006.245.07:42:15.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:15.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:15.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:15.26#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:42:15.26#ibcon#first serial, iclass 20, count 0 2006.245.07:42:15.26#ibcon#enter sib2, iclass 20, count 0 2006.245.07:42:15.26#ibcon#flushed, iclass 20, count 0 2006.245.07:42:15.26#ibcon#about to write, iclass 20, count 0 2006.245.07:42:15.26#ibcon#wrote, iclass 20, count 0 2006.245.07:42:15.26#ibcon#about to read 3, iclass 20, count 0 2006.245.07:42:15.28#ibcon#read 3, iclass 20, count 0 2006.245.07:42:15.28#ibcon#about to read 4, iclass 20, count 0 2006.245.07:42:15.28#ibcon#read 4, iclass 20, count 0 2006.245.07:42:15.28#ibcon#about to read 5, iclass 20, count 0 2006.245.07:42:15.28#ibcon#read 5, iclass 20, count 0 2006.245.07:42:15.28#ibcon#about to read 6, iclass 20, count 0 2006.245.07:42:15.28#ibcon#read 6, iclass 20, count 0 2006.245.07:42:15.28#ibcon#end of sib2, iclass 20, count 0 2006.245.07:42:15.28#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:42:15.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:42:15.28#ibcon#[27=USB\r\n] 2006.245.07:42:15.28#ibcon#*before write, iclass 20, count 0 2006.245.07:42:15.28#ibcon#enter sib2, iclass 20, count 0 2006.245.07:42:15.28#ibcon#flushed, iclass 20, count 0 2006.245.07:42:15.28#ibcon#about to write, iclass 20, count 0 2006.245.07:42:15.28#ibcon#wrote, iclass 20, count 0 2006.245.07:42:15.28#ibcon#about to read 3, iclass 20, count 0 2006.245.07:42:15.31#ibcon#read 3, iclass 20, count 0 2006.245.07:42:15.31#ibcon#about to read 4, iclass 20, count 0 2006.245.07:42:15.31#ibcon#read 4, iclass 20, count 0 2006.245.07:42:15.31#ibcon#about to read 5, iclass 20, count 0 2006.245.07:42:15.31#ibcon#read 5, iclass 20, count 0 2006.245.07:42:15.31#ibcon#about to read 6, iclass 20, count 0 2006.245.07:42:15.31#ibcon#read 6, iclass 20, count 0 2006.245.07:42:15.31#ibcon#end of sib2, iclass 20, count 0 2006.245.07:42:15.31#ibcon#*after write, iclass 20, count 0 2006.245.07:42:15.31#ibcon#*before return 0, iclass 20, count 0 2006.245.07:42:15.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:15.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:42:15.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:42:15.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:42:15.31$vc4f8/vabw=wide 2006.245.07:42:15.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.07:42:15.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.07:42:15.31#ibcon#ireg 8 cls_cnt 0 2006.245.07:42:15.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:15.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:15.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:15.31#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:42:15.31#ibcon#first serial, iclass 22, count 0 2006.245.07:42:15.31#ibcon#enter sib2, iclass 22, count 0 2006.245.07:42:15.31#ibcon#flushed, iclass 22, count 0 2006.245.07:42:15.31#ibcon#about to write, iclass 22, count 0 2006.245.07:42:15.31#ibcon#wrote, iclass 22, count 0 2006.245.07:42:15.31#ibcon#about to read 3, iclass 22, count 0 2006.245.07:42:15.33#ibcon#read 3, iclass 22, count 0 2006.245.07:42:15.33#ibcon#about to read 4, iclass 22, count 0 2006.245.07:42:15.33#ibcon#read 4, iclass 22, count 0 2006.245.07:42:15.33#ibcon#about to read 5, iclass 22, count 0 2006.245.07:42:15.33#ibcon#read 5, iclass 22, count 0 2006.245.07:42:15.33#ibcon#about to read 6, iclass 22, count 0 2006.245.07:42:15.33#ibcon#read 6, iclass 22, count 0 2006.245.07:42:15.33#ibcon#end of sib2, iclass 22, count 0 2006.245.07:42:15.33#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:42:15.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:42:15.33#ibcon#[25=BW32\r\n] 2006.245.07:42:15.33#ibcon#*before write, iclass 22, count 0 2006.245.07:42:15.33#ibcon#enter sib2, iclass 22, count 0 2006.245.07:42:15.33#ibcon#flushed, iclass 22, count 0 2006.245.07:42:15.33#ibcon#about to write, iclass 22, count 0 2006.245.07:42:15.33#ibcon#wrote, iclass 22, count 0 2006.245.07:42:15.33#ibcon#about to read 3, iclass 22, count 0 2006.245.07:42:15.36#ibcon#read 3, iclass 22, count 0 2006.245.07:42:15.36#ibcon#about to read 4, iclass 22, count 0 2006.245.07:42:15.36#ibcon#read 4, iclass 22, count 0 2006.245.07:42:15.36#ibcon#about to read 5, iclass 22, count 0 2006.245.07:42:15.36#ibcon#read 5, iclass 22, count 0 2006.245.07:42:15.36#ibcon#about to read 6, iclass 22, count 0 2006.245.07:42:15.36#ibcon#read 6, iclass 22, count 0 2006.245.07:42:15.36#ibcon#end of sib2, iclass 22, count 0 2006.245.07:42:15.36#ibcon#*after write, iclass 22, count 0 2006.245.07:42:15.36#ibcon#*before return 0, iclass 22, count 0 2006.245.07:42:15.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:15.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:42:15.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:42:15.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:42:15.36$vc4f8/vbbw=wide 2006.245.07:42:15.36#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.07:42:15.36#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.07:42:15.36#ibcon#ireg 8 cls_cnt 0 2006.245.07:42:15.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:42:15.43#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:42:15.43#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:42:15.43#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:42:15.43#ibcon#first serial, iclass 24, count 0 2006.245.07:42:15.43#ibcon#enter sib2, iclass 24, count 0 2006.245.07:42:15.43#ibcon#flushed, iclass 24, count 0 2006.245.07:42:15.43#ibcon#about to write, iclass 24, count 0 2006.245.07:42:15.43#ibcon#wrote, iclass 24, count 0 2006.245.07:42:15.43#ibcon#about to read 3, iclass 24, count 0 2006.245.07:42:15.45#ibcon#read 3, iclass 24, count 0 2006.245.07:42:15.45#ibcon#about to read 4, iclass 24, count 0 2006.245.07:42:15.45#ibcon#read 4, iclass 24, count 0 2006.245.07:42:15.45#ibcon#about to read 5, iclass 24, count 0 2006.245.07:42:15.45#ibcon#read 5, iclass 24, count 0 2006.245.07:42:15.45#ibcon#about to read 6, iclass 24, count 0 2006.245.07:42:15.45#ibcon#read 6, iclass 24, count 0 2006.245.07:42:15.45#ibcon#end of sib2, iclass 24, count 0 2006.245.07:42:15.45#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:42:15.45#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:42:15.45#ibcon#[27=BW32\r\n] 2006.245.07:42:15.45#ibcon#*before write, iclass 24, count 0 2006.245.07:42:15.45#ibcon#enter sib2, iclass 24, count 0 2006.245.07:42:15.45#ibcon#flushed, iclass 24, count 0 2006.245.07:42:15.45#ibcon#about to write, iclass 24, count 0 2006.245.07:42:15.45#ibcon#wrote, iclass 24, count 0 2006.245.07:42:15.45#ibcon#about to read 3, iclass 24, count 0 2006.245.07:42:15.48#ibcon#read 3, iclass 24, count 0 2006.245.07:42:15.48#ibcon#about to read 4, iclass 24, count 0 2006.245.07:42:15.48#ibcon#read 4, iclass 24, count 0 2006.245.07:42:15.48#ibcon#about to read 5, iclass 24, count 0 2006.245.07:42:15.48#ibcon#read 5, iclass 24, count 0 2006.245.07:42:15.48#ibcon#about to read 6, iclass 24, count 0 2006.245.07:42:15.48#ibcon#read 6, iclass 24, count 0 2006.245.07:42:15.48#ibcon#end of sib2, iclass 24, count 0 2006.245.07:42:15.48#ibcon#*after write, iclass 24, count 0 2006.245.07:42:15.48#ibcon#*before return 0, iclass 24, count 0 2006.245.07:42:15.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:42:15.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:42:15.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:42:15.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:42:15.48$4f8m12a/ifd4f 2006.245.07:42:15.48$ifd4f/lo= 2006.245.07:42:15.48$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:42:15.48$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:42:15.48$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:42:15.48$ifd4f/patch= 2006.245.07:42:15.48$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:42:15.48$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:42:15.48$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:42:15.48$4f8m12a/"form=m,16.000,1:2 2006.245.07:42:15.48$4f8m12a/"tpicd 2006.245.07:42:15.48$4f8m12a/echo=off 2006.245.07:42:15.48$4f8m12a/xlog=off 2006.245.07:42:15.48:!2006.245.07:42:40 2006.245.07:42:25.14#trakl#Source acquired 2006.245.07:42:25.14#flagr#flagr/antenna,acquired 2006.245.07:42:40.00:preob 2006.245.07:42:41.14/onsource/TRACKING 2006.245.07:42:41.14:!2006.245.07:42:50 2006.245.07:42:50.00:data_valid=on 2006.245.07:42:50.00:midob 2006.245.07:42:50.14/onsource/TRACKING 2006.245.07:42:50.14/wx/27.47,1004.5,67 2006.245.07:42:50.25/cable/+6.4105E-03 2006.245.07:42:51.34/va/01,08,usb,yes,31,32 2006.245.07:42:51.34/va/02,07,usb,yes,31,32 2006.245.07:42:51.34/va/03,06,usb,yes,33,33 2006.245.07:42:51.34/va/04,07,usb,yes,32,34 2006.245.07:42:51.34/va/05,07,usb,yes,33,35 2006.245.07:42:51.34/va/06,07,usb,yes,29,29 2006.245.07:42:51.34/va/07,07,usb,yes,29,29 2006.245.07:42:51.34/va/08,08,usb,yes,25,25 2006.245.07:42:51.57/valo/01,532.99,yes,locked 2006.245.07:42:51.57/valo/02,572.99,yes,locked 2006.245.07:42:51.57/valo/03,672.99,yes,locked 2006.245.07:42:51.57/valo/04,832.99,yes,locked 2006.245.07:42:51.57/valo/05,652.99,yes,locked 2006.245.07:42:51.57/valo/06,772.99,yes,locked 2006.245.07:42:51.57/valo/07,832.99,yes,locked 2006.245.07:42:51.57/valo/08,852.99,yes,locked 2006.245.07:42:52.66/vb/01,04,usb,yes,31,29 2006.245.07:42:52.66/vb/02,04,usb,yes,32,34 2006.245.07:42:52.66/vb/03,04,usb,yes,29,32 2006.245.07:42:52.66/vb/04,04,usb,yes,29,30 2006.245.07:42:52.66/vb/05,03,usb,yes,35,39 2006.245.07:42:52.66/vb/06,03,usb,yes,35,39 2006.245.07:42:52.66/vb/07,04,usb,yes,31,31 2006.245.07:42:52.66/vb/08,03,usb,yes,35,39 2006.245.07:42:52.89/vblo/01,632.99,yes,locked 2006.245.07:42:52.89/vblo/02,640.99,yes,locked 2006.245.07:42:52.89/vblo/03,656.99,yes,locked 2006.245.07:42:52.89/vblo/04,712.99,yes,locked 2006.245.07:42:52.89/vblo/05,744.99,yes,locked 2006.245.07:42:52.89/vblo/06,752.99,yes,locked 2006.245.07:42:52.89/vblo/07,734.99,yes,locked 2006.245.07:42:52.89/vblo/08,744.99,yes,locked 2006.245.07:42:53.04/vabw/8 2006.245.07:42:53.19/vbbw/8 2006.245.07:42:53.28/xfe/off,on,13.7 2006.245.07:42:53.67/ifatt/23,28,28,28 2006.245.07:42:54.08/fmout-gps/S +4.44E-07 2006.245.07:42:54.12:!2006.245.07:43:50 2006.245.07:43:50.00:data_valid=off 2006.245.07:43:50.00:postob 2006.245.07:43:50.19/cable/+6.4086E-03 2006.245.07:43:50.19/wx/27.45,1004.5,66 2006.245.07:43:51.08/fmout-gps/S +4.43E-07 2006.245.07:43:51.08:scan_name=245-0744,k06245,60 2006.245.07:43:51.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.245.07:43:51.14#flagr#flagr/antenna,new-source 2006.245.07:43:52.14:checkk5 2006.245.07:43:52.73/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:43:53.42/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:43:53.87/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:43:54.38/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:43:54.81/chk_obsdata//k5ts1/T2450742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:43:55.26/chk_obsdata//k5ts2/T2450742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:43:55.74/chk_obsdata//k5ts3/T2450742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:43:56.24/chk_obsdata//k5ts4/T2450742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:43:57.35/k5log//k5ts1_log_newline 2006.245.07:43:58.72/k5log//k5ts2_log_newline 2006.245.07:43:59.52/k5log//k5ts3_log_newline 2006.245.07:44:00.37/k5log//k5ts4_log_newline 2006.245.07:44:00.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:44:00.40:4f8m12a=1 2006.245.07:44:00.40$4f8m12a/echo=on 2006.245.07:44:00.40$4f8m12a/pcalon 2006.245.07:44:00.40$pcalon/"no phase cal control is implemented here 2006.245.07:44:00.40$4f8m12a/"tpicd=stop 2006.245.07:44:00.40$4f8m12a/vc4f8 2006.245.07:44:00.40$vc4f8/valo=1,532.99 2006.245.07:44:00.40#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:44:00.40#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:44:00.40#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:00.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:00.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:00.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:00.40#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:44:00.40#ibcon#first serial, iclass 31, count 0 2006.245.07:44:00.40#ibcon#enter sib2, iclass 31, count 0 2006.245.07:44:00.40#ibcon#flushed, iclass 31, count 0 2006.245.07:44:00.40#ibcon#about to write, iclass 31, count 0 2006.245.07:44:00.40#ibcon#wrote, iclass 31, count 0 2006.245.07:44:00.40#ibcon#about to read 3, iclass 31, count 0 2006.245.07:44:00.42#ibcon#read 3, iclass 31, count 0 2006.245.07:44:00.42#ibcon#about to read 4, iclass 31, count 0 2006.245.07:44:00.42#ibcon#read 4, iclass 31, count 0 2006.245.07:44:00.42#ibcon#about to read 5, iclass 31, count 0 2006.245.07:44:00.42#ibcon#read 5, iclass 31, count 0 2006.245.07:44:00.42#ibcon#about to read 6, iclass 31, count 0 2006.245.07:44:00.42#ibcon#read 6, iclass 31, count 0 2006.245.07:44:00.42#ibcon#end of sib2, iclass 31, count 0 2006.245.07:44:00.42#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:44:00.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:44:00.42#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:44:00.42#ibcon#*before write, iclass 31, count 0 2006.245.07:44:00.42#ibcon#enter sib2, iclass 31, count 0 2006.245.07:44:00.42#ibcon#flushed, iclass 31, count 0 2006.245.07:44:00.42#ibcon#about to write, iclass 31, count 0 2006.245.07:44:00.42#ibcon#wrote, iclass 31, count 0 2006.245.07:44:00.42#ibcon#about to read 3, iclass 31, count 0 2006.245.07:44:00.47#ibcon#read 3, iclass 31, count 0 2006.245.07:44:00.47#ibcon#about to read 4, iclass 31, count 0 2006.245.07:44:00.47#ibcon#read 4, iclass 31, count 0 2006.245.07:44:00.47#ibcon#about to read 5, iclass 31, count 0 2006.245.07:44:00.47#ibcon#read 5, iclass 31, count 0 2006.245.07:44:00.47#ibcon#about to read 6, iclass 31, count 0 2006.245.07:44:00.47#ibcon#read 6, iclass 31, count 0 2006.245.07:44:00.47#ibcon#end of sib2, iclass 31, count 0 2006.245.07:44:00.47#ibcon#*after write, iclass 31, count 0 2006.245.07:44:00.47#ibcon#*before return 0, iclass 31, count 0 2006.245.07:44:00.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:00.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:00.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:44:00.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:44:00.47$vc4f8/va=1,8 2006.245.07:44:00.47#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:44:00.47#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:44:00.47#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:00.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:00.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:00.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:00.47#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:44:00.47#ibcon#first serial, iclass 33, count 2 2006.245.07:44:00.47#ibcon#enter sib2, iclass 33, count 2 2006.245.07:44:00.47#ibcon#flushed, iclass 33, count 2 2006.245.07:44:00.47#ibcon#about to write, iclass 33, count 2 2006.245.07:44:00.47#ibcon#wrote, iclass 33, count 2 2006.245.07:44:00.47#ibcon#about to read 3, iclass 33, count 2 2006.245.07:44:00.49#ibcon#read 3, iclass 33, count 2 2006.245.07:44:00.49#ibcon#about to read 4, iclass 33, count 2 2006.245.07:44:00.49#ibcon#read 4, iclass 33, count 2 2006.245.07:44:00.49#ibcon#about to read 5, iclass 33, count 2 2006.245.07:44:00.49#ibcon#read 5, iclass 33, count 2 2006.245.07:44:00.49#ibcon#about to read 6, iclass 33, count 2 2006.245.07:44:00.49#ibcon#read 6, iclass 33, count 2 2006.245.07:44:00.49#ibcon#end of sib2, iclass 33, count 2 2006.245.07:44:00.49#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:44:00.49#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:44:00.49#ibcon#[25=AT01-08\r\n] 2006.245.07:44:00.49#ibcon#*before write, iclass 33, count 2 2006.245.07:44:00.49#ibcon#enter sib2, iclass 33, count 2 2006.245.07:44:00.49#ibcon#flushed, iclass 33, count 2 2006.245.07:44:00.49#ibcon#about to write, iclass 33, count 2 2006.245.07:44:00.49#ibcon#wrote, iclass 33, count 2 2006.245.07:44:00.49#ibcon#about to read 3, iclass 33, count 2 2006.245.07:44:00.52#ibcon#read 3, iclass 33, count 2 2006.245.07:44:00.52#ibcon#about to read 4, iclass 33, count 2 2006.245.07:44:00.52#ibcon#read 4, iclass 33, count 2 2006.245.07:44:00.52#ibcon#about to read 5, iclass 33, count 2 2006.245.07:44:00.52#ibcon#read 5, iclass 33, count 2 2006.245.07:44:00.52#ibcon#about to read 6, iclass 33, count 2 2006.245.07:44:00.52#ibcon#read 6, iclass 33, count 2 2006.245.07:44:00.52#ibcon#end of sib2, iclass 33, count 2 2006.245.07:44:00.52#ibcon#*after write, iclass 33, count 2 2006.245.07:44:00.52#ibcon#*before return 0, iclass 33, count 2 2006.245.07:44:00.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:00.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:00.52#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:44:00.52#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:00.52#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:00.64#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:00.64#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:00.64#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:44:00.64#ibcon#first serial, iclass 33, count 0 2006.245.07:44:00.64#ibcon#enter sib2, iclass 33, count 0 2006.245.07:44:00.64#ibcon#flushed, iclass 33, count 0 2006.245.07:44:00.64#ibcon#about to write, iclass 33, count 0 2006.245.07:44:00.64#ibcon#wrote, iclass 33, count 0 2006.245.07:44:00.64#ibcon#about to read 3, iclass 33, count 0 2006.245.07:44:00.66#ibcon#read 3, iclass 33, count 0 2006.245.07:44:00.66#ibcon#about to read 4, iclass 33, count 0 2006.245.07:44:00.66#ibcon#read 4, iclass 33, count 0 2006.245.07:44:00.66#ibcon#about to read 5, iclass 33, count 0 2006.245.07:44:00.66#ibcon#read 5, iclass 33, count 0 2006.245.07:44:00.66#ibcon#about to read 6, iclass 33, count 0 2006.245.07:44:00.66#ibcon#read 6, iclass 33, count 0 2006.245.07:44:00.66#ibcon#end of sib2, iclass 33, count 0 2006.245.07:44:00.66#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:44:00.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:44:00.66#ibcon#[25=USB\r\n] 2006.245.07:44:00.66#ibcon#*before write, iclass 33, count 0 2006.245.07:44:00.66#ibcon#enter sib2, iclass 33, count 0 2006.245.07:44:00.66#ibcon#flushed, iclass 33, count 0 2006.245.07:44:00.66#ibcon#about to write, iclass 33, count 0 2006.245.07:44:00.66#ibcon#wrote, iclass 33, count 0 2006.245.07:44:00.66#ibcon#about to read 3, iclass 33, count 0 2006.245.07:44:00.69#ibcon#read 3, iclass 33, count 0 2006.245.07:44:00.69#ibcon#about to read 4, iclass 33, count 0 2006.245.07:44:00.69#ibcon#read 4, iclass 33, count 0 2006.245.07:44:00.69#ibcon#about to read 5, iclass 33, count 0 2006.245.07:44:00.69#ibcon#read 5, iclass 33, count 0 2006.245.07:44:00.69#ibcon#about to read 6, iclass 33, count 0 2006.245.07:44:00.69#ibcon#read 6, iclass 33, count 0 2006.245.07:44:00.69#ibcon#end of sib2, iclass 33, count 0 2006.245.07:44:00.69#ibcon#*after write, iclass 33, count 0 2006.245.07:44:00.69#ibcon#*before return 0, iclass 33, count 0 2006.245.07:44:00.69#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:00.69#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:00.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:44:00.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:44:00.69$vc4f8/valo=2,572.99 2006.245.07:44:00.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:44:00.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:44:00.69#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:00.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:00.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:00.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:00.69#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:44:00.69#ibcon#first serial, iclass 35, count 0 2006.245.07:44:00.69#ibcon#enter sib2, iclass 35, count 0 2006.245.07:44:00.69#ibcon#flushed, iclass 35, count 0 2006.245.07:44:00.69#ibcon#about to write, iclass 35, count 0 2006.245.07:44:00.69#ibcon#wrote, iclass 35, count 0 2006.245.07:44:00.69#ibcon#about to read 3, iclass 35, count 0 2006.245.07:44:00.71#ibcon#read 3, iclass 35, count 0 2006.245.07:44:00.71#ibcon#about to read 4, iclass 35, count 0 2006.245.07:44:00.71#ibcon#read 4, iclass 35, count 0 2006.245.07:44:00.71#ibcon#about to read 5, iclass 35, count 0 2006.245.07:44:00.71#ibcon#read 5, iclass 35, count 0 2006.245.07:44:00.71#ibcon#about to read 6, iclass 35, count 0 2006.245.07:44:00.71#ibcon#read 6, iclass 35, count 0 2006.245.07:44:00.71#ibcon#end of sib2, iclass 35, count 0 2006.245.07:44:00.71#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:44:00.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:44:00.71#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:44:00.71#ibcon#*before write, iclass 35, count 0 2006.245.07:44:00.71#ibcon#enter sib2, iclass 35, count 0 2006.245.07:44:00.71#ibcon#flushed, iclass 35, count 0 2006.245.07:44:00.71#ibcon#about to write, iclass 35, count 0 2006.245.07:44:00.71#ibcon#wrote, iclass 35, count 0 2006.245.07:44:00.71#ibcon#about to read 3, iclass 35, count 0 2006.245.07:44:00.76#ibcon#read 3, iclass 35, count 0 2006.245.07:44:00.76#ibcon#about to read 4, iclass 35, count 0 2006.245.07:44:00.76#ibcon#read 4, iclass 35, count 0 2006.245.07:44:00.76#ibcon#about to read 5, iclass 35, count 0 2006.245.07:44:00.76#ibcon#read 5, iclass 35, count 0 2006.245.07:44:00.76#ibcon#about to read 6, iclass 35, count 0 2006.245.07:44:00.76#ibcon#read 6, iclass 35, count 0 2006.245.07:44:00.76#ibcon#end of sib2, iclass 35, count 0 2006.245.07:44:00.76#ibcon#*after write, iclass 35, count 0 2006.245.07:44:00.76#ibcon#*before return 0, iclass 35, count 0 2006.245.07:44:00.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:00.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:00.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:44:00.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:44:00.76$vc4f8/va=2,7 2006.245.07:44:00.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:44:00.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:44:00.76#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:00.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:00.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:00.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:00.81#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:44:00.81#ibcon#first serial, iclass 37, count 2 2006.245.07:44:00.81#ibcon#enter sib2, iclass 37, count 2 2006.245.07:44:00.81#ibcon#flushed, iclass 37, count 2 2006.245.07:44:00.81#ibcon#about to write, iclass 37, count 2 2006.245.07:44:00.81#ibcon#wrote, iclass 37, count 2 2006.245.07:44:00.81#ibcon#about to read 3, iclass 37, count 2 2006.245.07:44:00.83#ibcon#read 3, iclass 37, count 2 2006.245.07:44:00.83#ibcon#about to read 4, iclass 37, count 2 2006.245.07:44:00.83#ibcon#read 4, iclass 37, count 2 2006.245.07:44:00.83#ibcon#about to read 5, iclass 37, count 2 2006.245.07:44:00.83#ibcon#read 5, iclass 37, count 2 2006.245.07:44:00.83#ibcon#about to read 6, iclass 37, count 2 2006.245.07:44:00.83#ibcon#read 6, iclass 37, count 2 2006.245.07:44:00.83#ibcon#end of sib2, iclass 37, count 2 2006.245.07:44:00.83#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:44:00.83#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:44:00.83#ibcon#[25=AT02-07\r\n] 2006.245.07:44:00.83#ibcon#*before write, iclass 37, count 2 2006.245.07:44:00.83#ibcon#enter sib2, iclass 37, count 2 2006.245.07:44:00.83#ibcon#flushed, iclass 37, count 2 2006.245.07:44:00.83#ibcon#about to write, iclass 37, count 2 2006.245.07:44:00.83#ibcon#wrote, iclass 37, count 2 2006.245.07:44:00.83#ibcon#about to read 3, iclass 37, count 2 2006.245.07:44:00.86#ibcon#read 3, iclass 37, count 2 2006.245.07:44:00.86#ibcon#about to read 4, iclass 37, count 2 2006.245.07:44:00.86#ibcon#read 4, iclass 37, count 2 2006.245.07:44:00.86#ibcon#about to read 5, iclass 37, count 2 2006.245.07:44:00.86#ibcon#read 5, iclass 37, count 2 2006.245.07:44:00.86#ibcon#about to read 6, iclass 37, count 2 2006.245.07:44:00.86#ibcon#read 6, iclass 37, count 2 2006.245.07:44:00.86#ibcon#end of sib2, iclass 37, count 2 2006.245.07:44:00.86#ibcon#*after write, iclass 37, count 2 2006.245.07:44:00.86#ibcon#*before return 0, iclass 37, count 2 2006.245.07:44:00.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:00.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:00.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:44:00.86#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:00.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:00.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:00.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:00.98#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:44:00.98#ibcon#first serial, iclass 37, count 0 2006.245.07:44:00.98#ibcon#enter sib2, iclass 37, count 0 2006.245.07:44:00.98#ibcon#flushed, iclass 37, count 0 2006.245.07:44:00.98#ibcon#about to write, iclass 37, count 0 2006.245.07:44:00.98#ibcon#wrote, iclass 37, count 0 2006.245.07:44:00.98#ibcon#about to read 3, iclass 37, count 0 2006.245.07:44:01.00#ibcon#read 3, iclass 37, count 0 2006.245.07:44:01.00#ibcon#about to read 4, iclass 37, count 0 2006.245.07:44:01.00#ibcon#read 4, iclass 37, count 0 2006.245.07:44:01.00#ibcon#about to read 5, iclass 37, count 0 2006.245.07:44:01.00#ibcon#read 5, iclass 37, count 0 2006.245.07:44:01.00#ibcon#about to read 6, iclass 37, count 0 2006.245.07:44:01.00#ibcon#read 6, iclass 37, count 0 2006.245.07:44:01.00#ibcon#end of sib2, iclass 37, count 0 2006.245.07:44:01.00#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:44:01.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:44:01.00#ibcon#[25=USB\r\n] 2006.245.07:44:01.00#ibcon#*before write, iclass 37, count 0 2006.245.07:44:01.00#ibcon#enter sib2, iclass 37, count 0 2006.245.07:44:01.00#ibcon#flushed, iclass 37, count 0 2006.245.07:44:01.00#ibcon#about to write, iclass 37, count 0 2006.245.07:44:01.00#ibcon#wrote, iclass 37, count 0 2006.245.07:44:01.00#ibcon#about to read 3, iclass 37, count 0 2006.245.07:44:01.03#ibcon#read 3, iclass 37, count 0 2006.245.07:44:01.03#ibcon#about to read 4, iclass 37, count 0 2006.245.07:44:01.03#ibcon#read 4, iclass 37, count 0 2006.245.07:44:01.03#ibcon#about to read 5, iclass 37, count 0 2006.245.07:44:01.03#ibcon#read 5, iclass 37, count 0 2006.245.07:44:01.03#ibcon#about to read 6, iclass 37, count 0 2006.245.07:44:01.03#ibcon#read 6, iclass 37, count 0 2006.245.07:44:01.03#ibcon#end of sib2, iclass 37, count 0 2006.245.07:44:01.03#ibcon#*after write, iclass 37, count 0 2006.245.07:44:01.03#ibcon#*before return 0, iclass 37, count 0 2006.245.07:44:01.03#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:01.03#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:01.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:44:01.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:44:01.03$vc4f8/valo=3,672.99 2006.245.07:44:01.03#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:44:01.03#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:44:01.03#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:01.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:01.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:01.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:01.03#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:44:01.03#ibcon#first serial, iclass 39, count 0 2006.245.07:44:01.03#ibcon#enter sib2, iclass 39, count 0 2006.245.07:44:01.03#ibcon#flushed, iclass 39, count 0 2006.245.07:44:01.03#ibcon#about to write, iclass 39, count 0 2006.245.07:44:01.03#ibcon#wrote, iclass 39, count 0 2006.245.07:44:01.03#ibcon#about to read 3, iclass 39, count 0 2006.245.07:44:01.05#ibcon#read 3, iclass 39, count 0 2006.245.07:44:01.05#ibcon#about to read 4, iclass 39, count 0 2006.245.07:44:01.05#ibcon#read 4, iclass 39, count 0 2006.245.07:44:01.05#ibcon#about to read 5, iclass 39, count 0 2006.245.07:44:01.05#ibcon#read 5, iclass 39, count 0 2006.245.07:44:01.05#ibcon#about to read 6, iclass 39, count 0 2006.245.07:44:01.05#ibcon#read 6, iclass 39, count 0 2006.245.07:44:01.05#ibcon#end of sib2, iclass 39, count 0 2006.245.07:44:01.05#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:44:01.05#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:44:01.05#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:44:01.05#ibcon#*before write, iclass 39, count 0 2006.245.07:44:01.05#ibcon#enter sib2, iclass 39, count 0 2006.245.07:44:01.05#ibcon#flushed, iclass 39, count 0 2006.245.07:44:01.05#ibcon#about to write, iclass 39, count 0 2006.245.07:44:01.05#ibcon#wrote, iclass 39, count 0 2006.245.07:44:01.05#ibcon#about to read 3, iclass 39, count 0 2006.245.07:44:01.10#ibcon#read 3, iclass 39, count 0 2006.245.07:44:01.10#ibcon#about to read 4, iclass 39, count 0 2006.245.07:44:01.10#ibcon#read 4, iclass 39, count 0 2006.245.07:44:01.10#ibcon#about to read 5, iclass 39, count 0 2006.245.07:44:01.10#ibcon#read 5, iclass 39, count 0 2006.245.07:44:01.10#ibcon#about to read 6, iclass 39, count 0 2006.245.07:44:01.10#ibcon#read 6, iclass 39, count 0 2006.245.07:44:01.10#ibcon#end of sib2, iclass 39, count 0 2006.245.07:44:01.10#ibcon#*after write, iclass 39, count 0 2006.245.07:44:01.10#ibcon#*before return 0, iclass 39, count 0 2006.245.07:44:01.10#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:01.10#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:01.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:44:01.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:44:01.10$vc4f8/va=3,6 2006.245.07:44:01.10#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:44:01.10#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:44:01.10#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:01.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:01.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:01.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:01.15#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:44:01.15#ibcon#first serial, iclass 3, count 2 2006.245.07:44:01.15#ibcon#enter sib2, iclass 3, count 2 2006.245.07:44:01.15#ibcon#flushed, iclass 3, count 2 2006.245.07:44:01.15#ibcon#about to write, iclass 3, count 2 2006.245.07:44:01.15#ibcon#wrote, iclass 3, count 2 2006.245.07:44:01.15#ibcon#about to read 3, iclass 3, count 2 2006.245.07:44:01.17#ibcon#read 3, iclass 3, count 2 2006.245.07:44:01.17#ibcon#about to read 4, iclass 3, count 2 2006.245.07:44:01.17#ibcon#read 4, iclass 3, count 2 2006.245.07:44:01.17#ibcon#about to read 5, iclass 3, count 2 2006.245.07:44:01.17#ibcon#read 5, iclass 3, count 2 2006.245.07:44:01.17#ibcon#about to read 6, iclass 3, count 2 2006.245.07:44:01.17#ibcon#read 6, iclass 3, count 2 2006.245.07:44:01.17#ibcon#end of sib2, iclass 3, count 2 2006.245.07:44:01.17#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:44:01.17#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:44:01.17#ibcon#[25=AT03-06\r\n] 2006.245.07:44:01.17#ibcon#*before write, iclass 3, count 2 2006.245.07:44:01.17#ibcon#enter sib2, iclass 3, count 2 2006.245.07:44:01.17#ibcon#flushed, iclass 3, count 2 2006.245.07:44:01.17#ibcon#about to write, iclass 3, count 2 2006.245.07:44:01.17#ibcon#wrote, iclass 3, count 2 2006.245.07:44:01.17#ibcon#about to read 3, iclass 3, count 2 2006.245.07:44:01.20#ibcon#read 3, iclass 3, count 2 2006.245.07:44:01.20#ibcon#about to read 4, iclass 3, count 2 2006.245.07:44:01.20#ibcon#read 4, iclass 3, count 2 2006.245.07:44:01.20#ibcon#about to read 5, iclass 3, count 2 2006.245.07:44:01.20#ibcon#read 5, iclass 3, count 2 2006.245.07:44:01.20#ibcon#about to read 6, iclass 3, count 2 2006.245.07:44:01.20#ibcon#read 6, iclass 3, count 2 2006.245.07:44:01.20#ibcon#end of sib2, iclass 3, count 2 2006.245.07:44:01.20#ibcon#*after write, iclass 3, count 2 2006.245.07:44:01.20#ibcon#*before return 0, iclass 3, count 2 2006.245.07:44:01.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:01.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:01.20#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:44:01.20#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:01.20#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:01.32#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:01.32#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:01.32#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:44:01.32#ibcon#first serial, iclass 3, count 0 2006.245.07:44:01.32#ibcon#enter sib2, iclass 3, count 0 2006.245.07:44:01.32#ibcon#flushed, iclass 3, count 0 2006.245.07:44:01.32#ibcon#about to write, iclass 3, count 0 2006.245.07:44:01.32#ibcon#wrote, iclass 3, count 0 2006.245.07:44:01.32#ibcon#about to read 3, iclass 3, count 0 2006.245.07:44:01.34#ibcon#read 3, iclass 3, count 0 2006.245.07:44:01.34#ibcon#about to read 4, iclass 3, count 0 2006.245.07:44:01.34#ibcon#read 4, iclass 3, count 0 2006.245.07:44:01.34#ibcon#about to read 5, iclass 3, count 0 2006.245.07:44:01.34#ibcon#read 5, iclass 3, count 0 2006.245.07:44:01.34#ibcon#about to read 6, iclass 3, count 0 2006.245.07:44:01.34#ibcon#read 6, iclass 3, count 0 2006.245.07:44:01.34#ibcon#end of sib2, iclass 3, count 0 2006.245.07:44:01.34#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:44:01.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:44:01.34#ibcon#[25=USB\r\n] 2006.245.07:44:01.34#ibcon#*before write, iclass 3, count 0 2006.245.07:44:01.34#ibcon#enter sib2, iclass 3, count 0 2006.245.07:44:01.34#ibcon#flushed, iclass 3, count 0 2006.245.07:44:01.34#ibcon#about to write, iclass 3, count 0 2006.245.07:44:01.34#ibcon#wrote, iclass 3, count 0 2006.245.07:44:01.34#ibcon#about to read 3, iclass 3, count 0 2006.245.07:44:01.37#ibcon#read 3, iclass 3, count 0 2006.245.07:44:01.37#ibcon#about to read 4, iclass 3, count 0 2006.245.07:44:01.37#ibcon#read 4, iclass 3, count 0 2006.245.07:44:01.37#ibcon#about to read 5, iclass 3, count 0 2006.245.07:44:01.37#ibcon#read 5, iclass 3, count 0 2006.245.07:44:01.37#ibcon#about to read 6, iclass 3, count 0 2006.245.07:44:01.37#ibcon#read 6, iclass 3, count 0 2006.245.07:44:01.37#ibcon#end of sib2, iclass 3, count 0 2006.245.07:44:01.37#ibcon#*after write, iclass 3, count 0 2006.245.07:44:01.37#ibcon#*before return 0, iclass 3, count 0 2006.245.07:44:01.37#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:01.37#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:01.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:44:01.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:44:01.37$vc4f8/valo=4,832.99 2006.245.07:44:01.37#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:44:01.37#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:44:01.37#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:01.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:01.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:01.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:01.37#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:44:01.37#ibcon#first serial, iclass 5, count 0 2006.245.07:44:01.37#ibcon#enter sib2, iclass 5, count 0 2006.245.07:44:01.37#ibcon#flushed, iclass 5, count 0 2006.245.07:44:01.37#ibcon#about to write, iclass 5, count 0 2006.245.07:44:01.37#ibcon#wrote, iclass 5, count 0 2006.245.07:44:01.37#ibcon#about to read 3, iclass 5, count 0 2006.245.07:44:01.39#ibcon#read 3, iclass 5, count 0 2006.245.07:44:01.39#ibcon#about to read 4, iclass 5, count 0 2006.245.07:44:01.39#ibcon#read 4, iclass 5, count 0 2006.245.07:44:01.39#ibcon#about to read 5, iclass 5, count 0 2006.245.07:44:01.39#ibcon#read 5, iclass 5, count 0 2006.245.07:44:01.39#ibcon#about to read 6, iclass 5, count 0 2006.245.07:44:01.39#ibcon#read 6, iclass 5, count 0 2006.245.07:44:01.39#ibcon#end of sib2, iclass 5, count 0 2006.245.07:44:01.39#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:44:01.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:44:01.39#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:44:01.39#ibcon#*before write, iclass 5, count 0 2006.245.07:44:01.39#ibcon#enter sib2, iclass 5, count 0 2006.245.07:44:01.39#ibcon#flushed, iclass 5, count 0 2006.245.07:44:01.39#ibcon#about to write, iclass 5, count 0 2006.245.07:44:01.39#ibcon#wrote, iclass 5, count 0 2006.245.07:44:01.39#ibcon#about to read 3, iclass 5, count 0 2006.245.07:44:01.44#ibcon#read 3, iclass 5, count 0 2006.245.07:44:01.44#ibcon#about to read 4, iclass 5, count 0 2006.245.07:44:01.44#ibcon#read 4, iclass 5, count 0 2006.245.07:44:01.44#ibcon#about to read 5, iclass 5, count 0 2006.245.07:44:01.44#ibcon#read 5, iclass 5, count 0 2006.245.07:44:01.44#ibcon#about to read 6, iclass 5, count 0 2006.245.07:44:01.44#ibcon#read 6, iclass 5, count 0 2006.245.07:44:01.44#ibcon#end of sib2, iclass 5, count 0 2006.245.07:44:01.44#ibcon#*after write, iclass 5, count 0 2006.245.07:44:01.44#ibcon#*before return 0, iclass 5, count 0 2006.245.07:44:01.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:01.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:01.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:44:01.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:44:01.44$vc4f8/va=4,7 2006.245.07:44:01.44#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:44:01.44#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:44:01.44#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:01.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:01.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:01.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:01.49#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:44:01.49#ibcon#first serial, iclass 7, count 2 2006.245.07:44:01.49#ibcon#enter sib2, iclass 7, count 2 2006.245.07:44:01.49#ibcon#flushed, iclass 7, count 2 2006.245.07:44:01.49#ibcon#about to write, iclass 7, count 2 2006.245.07:44:01.49#ibcon#wrote, iclass 7, count 2 2006.245.07:44:01.49#ibcon#about to read 3, iclass 7, count 2 2006.245.07:44:01.51#ibcon#read 3, iclass 7, count 2 2006.245.07:44:01.51#ibcon#about to read 4, iclass 7, count 2 2006.245.07:44:01.51#ibcon#read 4, iclass 7, count 2 2006.245.07:44:01.51#ibcon#about to read 5, iclass 7, count 2 2006.245.07:44:01.51#ibcon#read 5, iclass 7, count 2 2006.245.07:44:01.51#ibcon#about to read 6, iclass 7, count 2 2006.245.07:44:01.51#ibcon#read 6, iclass 7, count 2 2006.245.07:44:01.51#ibcon#end of sib2, iclass 7, count 2 2006.245.07:44:01.51#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:44:01.51#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:44:01.51#ibcon#[25=AT04-07\r\n] 2006.245.07:44:01.51#ibcon#*before write, iclass 7, count 2 2006.245.07:44:01.51#ibcon#enter sib2, iclass 7, count 2 2006.245.07:44:01.51#ibcon#flushed, iclass 7, count 2 2006.245.07:44:01.51#ibcon#about to write, iclass 7, count 2 2006.245.07:44:01.51#ibcon#wrote, iclass 7, count 2 2006.245.07:44:01.51#ibcon#about to read 3, iclass 7, count 2 2006.245.07:44:01.54#ibcon#read 3, iclass 7, count 2 2006.245.07:44:01.54#ibcon#about to read 4, iclass 7, count 2 2006.245.07:44:01.54#ibcon#read 4, iclass 7, count 2 2006.245.07:44:01.54#ibcon#about to read 5, iclass 7, count 2 2006.245.07:44:01.54#ibcon#read 5, iclass 7, count 2 2006.245.07:44:01.54#ibcon#about to read 6, iclass 7, count 2 2006.245.07:44:01.54#ibcon#read 6, iclass 7, count 2 2006.245.07:44:01.54#ibcon#end of sib2, iclass 7, count 2 2006.245.07:44:01.54#ibcon#*after write, iclass 7, count 2 2006.245.07:44:01.54#ibcon#*before return 0, iclass 7, count 2 2006.245.07:44:01.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:01.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:01.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:44:01.54#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:01.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:01.66#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:01.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:01.66#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:44:01.66#ibcon#first serial, iclass 7, count 0 2006.245.07:44:01.66#ibcon#enter sib2, iclass 7, count 0 2006.245.07:44:01.66#ibcon#flushed, iclass 7, count 0 2006.245.07:44:01.66#ibcon#about to write, iclass 7, count 0 2006.245.07:44:01.66#ibcon#wrote, iclass 7, count 0 2006.245.07:44:01.66#ibcon#about to read 3, iclass 7, count 0 2006.245.07:44:01.68#ibcon#read 3, iclass 7, count 0 2006.245.07:44:01.68#ibcon#about to read 4, iclass 7, count 0 2006.245.07:44:01.68#ibcon#read 4, iclass 7, count 0 2006.245.07:44:01.68#ibcon#about to read 5, iclass 7, count 0 2006.245.07:44:01.68#ibcon#read 5, iclass 7, count 0 2006.245.07:44:01.68#ibcon#about to read 6, iclass 7, count 0 2006.245.07:44:01.68#ibcon#read 6, iclass 7, count 0 2006.245.07:44:01.68#ibcon#end of sib2, iclass 7, count 0 2006.245.07:44:01.68#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:44:01.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:44:01.68#ibcon#[25=USB\r\n] 2006.245.07:44:01.68#ibcon#*before write, iclass 7, count 0 2006.245.07:44:01.68#ibcon#enter sib2, iclass 7, count 0 2006.245.07:44:01.68#ibcon#flushed, iclass 7, count 0 2006.245.07:44:01.68#ibcon#about to write, iclass 7, count 0 2006.245.07:44:01.68#ibcon#wrote, iclass 7, count 0 2006.245.07:44:01.68#ibcon#about to read 3, iclass 7, count 0 2006.245.07:44:01.71#ibcon#read 3, iclass 7, count 0 2006.245.07:44:01.71#ibcon#about to read 4, iclass 7, count 0 2006.245.07:44:01.71#ibcon#read 4, iclass 7, count 0 2006.245.07:44:01.71#ibcon#about to read 5, iclass 7, count 0 2006.245.07:44:01.71#ibcon#read 5, iclass 7, count 0 2006.245.07:44:01.71#ibcon#about to read 6, iclass 7, count 0 2006.245.07:44:01.71#ibcon#read 6, iclass 7, count 0 2006.245.07:44:01.71#ibcon#end of sib2, iclass 7, count 0 2006.245.07:44:01.71#ibcon#*after write, iclass 7, count 0 2006.245.07:44:01.71#ibcon#*before return 0, iclass 7, count 0 2006.245.07:44:01.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:01.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:01.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:44:01.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:44:01.71$vc4f8/valo=5,652.99 2006.245.07:44:01.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:44:01.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:44:01.71#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:01.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:01.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:01.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:01.71#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:44:01.71#ibcon#first serial, iclass 11, count 0 2006.245.07:44:01.71#ibcon#enter sib2, iclass 11, count 0 2006.245.07:44:01.71#ibcon#flushed, iclass 11, count 0 2006.245.07:44:01.71#ibcon#about to write, iclass 11, count 0 2006.245.07:44:01.71#ibcon#wrote, iclass 11, count 0 2006.245.07:44:01.71#ibcon#about to read 3, iclass 11, count 0 2006.245.07:44:01.73#ibcon#read 3, iclass 11, count 0 2006.245.07:44:01.73#ibcon#about to read 4, iclass 11, count 0 2006.245.07:44:01.73#ibcon#read 4, iclass 11, count 0 2006.245.07:44:01.73#ibcon#about to read 5, iclass 11, count 0 2006.245.07:44:01.73#ibcon#read 5, iclass 11, count 0 2006.245.07:44:01.73#ibcon#about to read 6, iclass 11, count 0 2006.245.07:44:01.73#ibcon#read 6, iclass 11, count 0 2006.245.07:44:01.73#ibcon#end of sib2, iclass 11, count 0 2006.245.07:44:01.73#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:44:01.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:44:01.73#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:44:01.73#ibcon#*before write, iclass 11, count 0 2006.245.07:44:01.73#ibcon#enter sib2, iclass 11, count 0 2006.245.07:44:01.73#ibcon#flushed, iclass 11, count 0 2006.245.07:44:01.73#ibcon#about to write, iclass 11, count 0 2006.245.07:44:01.73#ibcon#wrote, iclass 11, count 0 2006.245.07:44:01.73#ibcon#about to read 3, iclass 11, count 0 2006.245.07:44:01.77#ibcon#read 3, iclass 11, count 0 2006.245.07:44:01.77#ibcon#about to read 4, iclass 11, count 0 2006.245.07:44:01.77#ibcon#read 4, iclass 11, count 0 2006.245.07:44:01.77#ibcon#about to read 5, iclass 11, count 0 2006.245.07:44:01.77#ibcon#read 5, iclass 11, count 0 2006.245.07:44:01.77#ibcon#about to read 6, iclass 11, count 0 2006.245.07:44:01.77#ibcon#read 6, iclass 11, count 0 2006.245.07:44:01.77#ibcon#end of sib2, iclass 11, count 0 2006.245.07:44:01.77#ibcon#*after write, iclass 11, count 0 2006.245.07:44:01.77#ibcon#*before return 0, iclass 11, count 0 2006.245.07:44:01.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:01.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:01.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:44:01.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:44:01.77$vc4f8/va=5,7 2006.245.07:44:01.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.07:44:01.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.07:44:01.77#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:01.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:01.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:01.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:01.83#ibcon#enter wrdev, iclass 13, count 2 2006.245.07:44:01.83#ibcon#first serial, iclass 13, count 2 2006.245.07:44:01.83#ibcon#enter sib2, iclass 13, count 2 2006.245.07:44:01.83#ibcon#flushed, iclass 13, count 2 2006.245.07:44:01.83#ibcon#about to write, iclass 13, count 2 2006.245.07:44:01.83#ibcon#wrote, iclass 13, count 2 2006.245.07:44:01.83#ibcon#about to read 3, iclass 13, count 2 2006.245.07:44:01.85#ibcon#read 3, iclass 13, count 2 2006.245.07:44:01.85#ibcon#about to read 4, iclass 13, count 2 2006.245.07:44:01.85#ibcon#read 4, iclass 13, count 2 2006.245.07:44:01.85#ibcon#about to read 5, iclass 13, count 2 2006.245.07:44:01.85#ibcon#read 5, iclass 13, count 2 2006.245.07:44:01.85#ibcon#about to read 6, iclass 13, count 2 2006.245.07:44:01.85#ibcon#read 6, iclass 13, count 2 2006.245.07:44:01.85#ibcon#end of sib2, iclass 13, count 2 2006.245.07:44:01.85#ibcon#*mode == 0, iclass 13, count 2 2006.245.07:44:01.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.07:44:01.85#ibcon#[25=AT05-07\r\n] 2006.245.07:44:01.85#ibcon#*before write, iclass 13, count 2 2006.245.07:44:01.85#ibcon#enter sib2, iclass 13, count 2 2006.245.07:44:01.85#ibcon#flushed, iclass 13, count 2 2006.245.07:44:01.85#ibcon#about to write, iclass 13, count 2 2006.245.07:44:01.85#ibcon#wrote, iclass 13, count 2 2006.245.07:44:01.85#ibcon#about to read 3, iclass 13, count 2 2006.245.07:44:01.88#ibcon#read 3, iclass 13, count 2 2006.245.07:44:01.88#ibcon#about to read 4, iclass 13, count 2 2006.245.07:44:01.88#ibcon#read 4, iclass 13, count 2 2006.245.07:44:01.88#ibcon#about to read 5, iclass 13, count 2 2006.245.07:44:01.88#ibcon#read 5, iclass 13, count 2 2006.245.07:44:01.88#ibcon#about to read 6, iclass 13, count 2 2006.245.07:44:01.88#ibcon#read 6, iclass 13, count 2 2006.245.07:44:01.88#ibcon#end of sib2, iclass 13, count 2 2006.245.07:44:01.88#ibcon#*after write, iclass 13, count 2 2006.245.07:44:01.88#ibcon#*before return 0, iclass 13, count 2 2006.245.07:44:01.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:01.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:01.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.07:44:01.88#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:01.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:02.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:02.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:02.00#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:44:02.00#ibcon#first serial, iclass 13, count 0 2006.245.07:44:02.00#ibcon#enter sib2, iclass 13, count 0 2006.245.07:44:02.00#ibcon#flushed, iclass 13, count 0 2006.245.07:44:02.00#ibcon#about to write, iclass 13, count 0 2006.245.07:44:02.00#ibcon#wrote, iclass 13, count 0 2006.245.07:44:02.00#ibcon#about to read 3, iclass 13, count 0 2006.245.07:44:02.02#ibcon#read 3, iclass 13, count 0 2006.245.07:44:02.02#ibcon#about to read 4, iclass 13, count 0 2006.245.07:44:02.02#ibcon#read 4, iclass 13, count 0 2006.245.07:44:02.02#ibcon#about to read 5, iclass 13, count 0 2006.245.07:44:02.02#ibcon#read 5, iclass 13, count 0 2006.245.07:44:02.02#ibcon#about to read 6, iclass 13, count 0 2006.245.07:44:02.02#ibcon#read 6, iclass 13, count 0 2006.245.07:44:02.02#ibcon#end of sib2, iclass 13, count 0 2006.245.07:44:02.02#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:44:02.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:44:02.02#ibcon#[25=USB\r\n] 2006.245.07:44:02.02#ibcon#*before write, iclass 13, count 0 2006.245.07:44:02.02#ibcon#enter sib2, iclass 13, count 0 2006.245.07:44:02.02#ibcon#flushed, iclass 13, count 0 2006.245.07:44:02.02#ibcon#about to write, iclass 13, count 0 2006.245.07:44:02.02#ibcon#wrote, iclass 13, count 0 2006.245.07:44:02.02#ibcon#about to read 3, iclass 13, count 0 2006.245.07:44:02.05#ibcon#read 3, iclass 13, count 0 2006.245.07:44:02.05#ibcon#about to read 4, iclass 13, count 0 2006.245.07:44:02.05#ibcon#read 4, iclass 13, count 0 2006.245.07:44:02.05#ibcon#about to read 5, iclass 13, count 0 2006.245.07:44:02.05#ibcon#read 5, iclass 13, count 0 2006.245.07:44:02.05#ibcon#about to read 6, iclass 13, count 0 2006.245.07:44:02.05#ibcon#read 6, iclass 13, count 0 2006.245.07:44:02.05#ibcon#end of sib2, iclass 13, count 0 2006.245.07:44:02.05#ibcon#*after write, iclass 13, count 0 2006.245.07:44:02.05#ibcon#*before return 0, iclass 13, count 0 2006.245.07:44:02.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:02.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:02.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:44:02.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:44:02.05$vc4f8/valo=6,772.99 2006.245.07:44:02.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.07:44:02.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.07:44:02.05#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:02.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:02.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:02.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:02.05#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:44:02.05#ibcon#first serial, iclass 15, count 0 2006.245.07:44:02.05#ibcon#enter sib2, iclass 15, count 0 2006.245.07:44:02.05#ibcon#flushed, iclass 15, count 0 2006.245.07:44:02.05#ibcon#about to write, iclass 15, count 0 2006.245.07:44:02.05#ibcon#wrote, iclass 15, count 0 2006.245.07:44:02.05#ibcon#about to read 3, iclass 15, count 0 2006.245.07:44:02.07#ibcon#read 3, iclass 15, count 0 2006.245.07:44:02.07#ibcon#about to read 4, iclass 15, count 0 2006.245.07:44:02.07#ibcon#read 4, iclass 15, count 0 2006.245.07:44:02.07#ibcon#about to read 5, iclass 15, count 0 2006.245.07:44:02.07#ibcon#read 5, iclass 15, count 0 2006.245.07:44:02.07#ibcon#about to read 6, iclass 15, count 0 2006.245.07:44:02.07#ibcon#read 6, iclass 15, count 0 2006.245.07:44:02.07#ibcon#end of sib2, iclass 15, count 0 2006.245.07:44:02.07#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:44:02.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:44:02.07#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:44:02.07#ibcon#*before write, iclass 15, count 0 2006.245.07:44:02.07#ibcon#enter sib2, iclass 15, count 0 2006.245.07:44:02.07#ibcon#flushed, iclass 15, count 0 2006.245.07:44:02.07#ibcon#about to write, iclass 15, count 0 2006.245.07:44:02.07#ibcon#wrote, iclass 15, count 0 2006.245.07:44:02.07#ibcon#about to read 3, iclass 15, count 0 2006.245.07:44:02.12#ibcon#read 3, iclass 15, count 0 2006.245.07:44:02.12#ibcon#about to read 4, iclass 15, count 0 2006.245.07:44:02.12#ibcon#read 4, iclass 15, count 0 2006.245.07:44:02.12#ibcon#about to read 5, iclass 15, count 0 2006.245.07:44:02.12#ibcon#read 5, iclass 15, count 0 2006.245.07:44:02.12#ibcon#about to read 6, iclass 15, count 0 2006.245.07:44:02.12#ibcon#read 6, iclass 15, count 0 2006.245.07:44:02.12#ibcon#end of sib2, iclass 15, count 0 2006.245.07:44:02.12#ibcon#*after write, iclass 15, count 0 2006.245.07:44:02.12#ibcon#*before return 0, iclass 15, count 0 2006.245.07:44:02.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:02.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:02.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:44:02.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:44:02.12$vc4f8/va=6,7 2006.245.07:44:02.12#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.07:44:02.12#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.07:44:02.12#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:02.12#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:44:02.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:44:02.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:44:02.17#ibcon#enter wrdev, iclass 17, count 2 2006.245.07:44:02.17#ibcon#first serial, iclass 17, count 2 2006.245.07:44:02.17#ibcon#enter sib2, iclass 17, count 2 2006.245.07:44:02.17#ibcon#flushed, iclass 17, count 2 2006.245.07:44:02.17#ibcon#about to write, iclass 17, count 2 2006.245.07:44:02.17#ibcon#wrote, iclass 17, count 2 2006.245.07:44:02.17#ibcon#about to read 3, iclass 17, count 2 2006.245.07:44:02.19#ibcon#read 3, iclass 17, count 2 2006.245.07:44:02.19#ibcon#about to read 4, iclass 17, count 2 2006.245.07:44:02.19#ibcon#read 4, iclass 17, count 2 2006.245.07:44:02.19#ibcon#about to read 5, iclass 17, count 2 2006.245.07:44:02.19#ibcon#read 5, iclass 17, count 2 2006.245.07:44:02.19#ibcon#about to read 6, iclass 17, count 2 2006.245.07:44:02.19#ibcon#read 6, iclass 17, count 2 2006.245.07:44:02.19#ibcon#end of sib2, iclass 17, count 2 2006.245.07:44:02.19#ibcon#*mode == 0, iclass 17, count 2 2006.245.07:44:02.19#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.07:44:02.19#ibcon#[25=AT06-07\r\n] 2006.245.07:44:02.19#ibcon#*before write, iclass 17, count 2 2006.245.07:44:02.19#ibcon#enter sib2, iclass 17, count 2 2006.245.07:44:02.19#ibcon#flushed, iclass 17, count 2 2006.245.07:44:02.19#ibcon#about to write, iclass 17, count 2 2006.245.07:44:02.19#ibcon#wrote, iclass 17, count 2 2006.245.07:44:02.19#ibcon#about to read 3, iclass 17, count 2 2006.245.07:44:02.22#ibcon#read 3, iclass 17, count 2 2006.245.07:44:02.22#ibcon#about to read 4, iclass 17, count 2 2006.245.07:44:02.22#ibcon#read 4, iclass 17, count 2 2006.245.07:44:02.22#ibcon#about to read 5, iclass 17, count 2 2006.245.07:44:02.22#ibcon#read 5, iclass 17, count 2 2006.245.07:44:02.22#ibcon#about to read 6, iclass 17, count 2 2006.245.07:44:02.22#ibcon#read 6, iclass 17, count 2 2006.245.07:44:02.22#ibcon#end of sib2, iclass 17, count 2 2006.245.07:44:02.22#ibcon#*after write, iclass 17, count 2 2006.245.07:44:02.22#ibcon#*before return 0, iclass 17, count 2 2006.245.07:44:02.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:44:02.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:44:02.22#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.07:44:02.22#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:02.22#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:44:02.34#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:44:02.34#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:44:02.34#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:44:02.34#ibcon#first serial, iclass 17, count 0 2006.245.07:44:02.34#ibcon#enter sib2, iclass 17, count 0 2006.245.07:44:02.34#ibcon#flushed, iclass 17, count 0 2006.245.07:44:02.34#ibcon#about to write, iclass 17, count 0 2006.245.07:44:02.34#ibcon#wrote, iclass 17, count 0 2006.245.07:44:02.34#ibcon#about to read 3, iclass 17, count 0 2006.245.07:44:02.36#ibcon#read 3, iclass 17, count 0 2006.245.07:44:02.36#ibcon#about to read 4, iclass 17, count 0 2006.245.07:44:02.36#ibcon#read 4, iclass 17, count 0 2006.245.07:44:02.36#ibcon#about to read 5, iclass 17, count 0 2006.245.07:44:02.36#ibcon#read 5, iclass 17, count 0 2006.245.07:44:02.36#ibcon#about to read 6, iclass 17, count 0 2006.245.07:44:02.36#ibcon#read 6, iclass 17, count 0 2006.245.07:44:02.36#ibcon#end of sib2, iclass 17, count 0 2006.245.07:44:02.36#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:44:02.36#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:44:02.36#ibcon#[25=USB\r\n] 2006.245.07:44:02.36#ibcon#*before write, iclass 17, count 0 2006.245.07:44:02.36#ibcon#enter sib2, iclass 17, count 0 2006.245.07:44:02.36#ibcon#flushed, iclass 17, count 0 2006.245.07:44:02.36#ibcon#about to write, iclass 17, count 0 2006.245.07:44:02.36#ibcon#wrote, iclass 17, count 0 2006.245.07:44:02.36#ibcon#about to read 3, iclass 17, count 0 2006.245.07:44:02.39#ibcon#read 3, iclass 17, count 0 2006.245.07:44:02.39#ibcon#about to read 4, iclass 17, count 0 2006.245.07:44:02.39#ibcon#read 4, iclass 17, count 0 2006.245.07:44:02.39#ibcon#about to read 5, iclass 17, count 0 2006.245.07:44:02.39#ibcon#read 5, iclass 17, count 0 2006.245.07:44:02.39#ibcon#about to read 6, iclass 17, count 0 2006.245.07:44:02.39#ibcon#read 6, iclass 17, count 0 2006.245.07:44:02.39#ibcon#end of sib2, iclass 17, count 0 2006.245.07:44:02.39#ibcon#*after write, iclass 17, count 0 2006.245.07:44:02.39#ibcon#*before return 0, iclass 17, count 0 2006.245.07:44:02.39#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:44:02.39#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:44:02.39#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:44:02.39#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:44:02.39$vc4f8/valo=7,832.99 2006.245.07:44:02.39#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.07:44:02.39#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.07:44:02.39#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:02.39#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:44:02.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:44:02.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:44:02.39#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:44:02.39#ibcon#first serial, iclass 19, count 0 2006.245.07:44:02.39#ibcon#enter sib2, iclass 19, count 0 2006.245.07:44:02.39#ibcon#flushed, iclass 19, count 0 2006.245.07:44:02.39#ibcon#about to write, iclass 19, count 0 2006.245.07:44:02.39#ibcon#wrote, iclass 19, count 0 2006.245.07:44:02.39#ibcon#about to read 3, iclass 19, count 0 2006.245.07:44:02.41#ibcon#read 3, iclass 19, count 0 2006.245.07:44:02.41#ibcon#about to read 4, iclass 19, count 0 2006.245.07:44:02.41#ibcon#read 4, iclass 19, count 0 2006.245.07:44:02.41#ibcon#about to read 5, iclass 19, count 0 2006.245.07:44:02.41#ibcon#read 5, iclass 19, count 0 2006.245.07:44:02.41#ibcon#about to read 6, iclass 19, count 0 2006.245.07:44:02.41#ibcon#read 6, iclass 19, count 0 2006.245.07:44:02.41#ibcon#end of sib2, iclass 19, count 0 2006.245.07:44:02.41#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:44:02.41#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:44:02.41#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:44:02.41#ibcon#*before write, iclass 19, count 0 2006.245.07:44:02.41#ibcon#enter sib2, iclass 19, count 0 2006.245.07:44:02.41#ibcon#flushed, iclass 19, count 0 2006.245.07:44:02.41#ibcon#about to write, iclass 19, count 0 2006.245.07:44:02.41#ibcon#wrote, iclass 19, count 0 2006.245.07:44:02.41#ibcon#about to read 3, iclass 19, count 0 2006.245.07:44:02.45#ibcon#read 3, iclass 19, count 0 2006.245.07:44:02.45#ibcon#about to read 4, iclass 19, count 0 2006.245.07:44:02.45#ibcon#read 4, iclass 19, count 0 2006.245.07:44:02.45#ibcon#about to read 5, iclass 19, count 0 2006.245.07:44:02.45#ibcon#read 5, iclass 19, count 0 2006.245.07:44:02.45#ibcon#about to read 6, iclass 19, count 0 2006.245.07:44:02.45#ibcon#read 6, iclass 19, count 0 2006.245.07:44:02.45#ibcon#end of sib2, iclass 19, count 0 2006.245.07:44:02.45#ibcon#*after write, iclass 19, count 0 2006.245.07:44:02.45#ibcon#*before return 0, iclass 19, count 0 2006.245.07:44:02.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:44:02.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:44:02.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:44:02.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:44:02.45$vc4f8/va=7,7 2006.245.07:44:02.45#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.07:44:02.45#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.07:44:02.45#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:02.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:44:02.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:44:02.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:44:02.51#ibcon#enter wrdev, iclass 21, count 2 2006.245.07:44:02.51#ibcon#first serial, iclass 21, count 2 2006.245.07:44:02.51#ibcon#enter sib2, iclass 21, count 2 2006.245.07:44:02.51#ibcon#flushed, iclass 21, count 2 2006.245.07:44:02.51#ibcon#about to write, iclass 21, count 2 2006.245.07:44:02.51#ibcon#wrote, iclass 21, count 2 2006.245.07:44:02.51#ibcon#about to read 3, iclass 21, count 2 2006.245.07:44:02.53#ibcon#read 3, iclass 21, count 2 2006.245.07:44:02.53#ibcon#about to read 4, iclass 21, count 2 2006.245.07:44:02.53#ibcon#read 4, iclass 21, count 2 2006.245.07:44:02.53#ibcon#about to read 5, iclass 21, count 2 2006.245.07:44:02.53#ibcon#read 5, iclass 21, count 2 2006.245.07:44:02.53#ibcon#about to read 6, iclass 21, count 2 2006.245.07:44:02.53#ibcon#read 6, iclass 21, count 2 2006.245.07:44:02.53#ibcon#end of sib2, iclass 21, count 2 2006.245.07:44:02.53#ibcon#*mode == 0, iclass 21, count 2 2006.245.07:44:02.53#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.07:44:02.53#ibcon#[25=AT07-07\r\n] 2006.245.07:44:02.53#ibcon#*before write, iclass 21, count 2 2006.245.07:44:02.53#ibcon#enter sib2, iclass 21, count 2 2006.245.07:44:02.53#ibcon#flushed, iclass 21, count 2 2006.245.07:44:02.53#ibcon#about to write, iclass 21, count 2 2006.245.07:44:02.53#ibcon#wrote, iclass 21, count 2 2006.245.07:44:02.53#ibcon#about to read 3, iclass 21, count 2 2006.245.07:44:02.56#ibcon#read 3, iclass 21, count 2 2006.245.07:44:02.56#ibcon#about to read 4, iclass 21, count 2 2006.245.07:44:02.56#ibcon#read 4, iclass 21, count 2 2006.245.07:44:02.56#ibcon#about to read 5, iclass 21, count 2 2006.245.07:44:02.56#ibcon#read 5, iclass 21, count 2 2006.245.07:44:02.56#ibcon#about to read 6, iclass 21, count 2 2006.245.07:44:02.56#ibcon#read 6, iclass 21, count 2 2006.245.07:44:02.56#ibcon#end of sib2, iclass 21, count 2 2006.245.07:44:02.56#ibcon#*after write, iclass 21, count 2 2006.245.07:44:02.56#ibcon#*before return 0, iclass 21, count 2 2006.245.07:44:02.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:44:02.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:44:02.56#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.07:44:02.56#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:02.56#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:44:02.68#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:44:02.68#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:44:02.68#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:44:02.68#ibcon#first serial, iclass 21, count 0 2006.245.07:44:02.68#ibcon#enter sib2, iclass 21, count 0 2006.245.07:44:02.68#ibcon#flushed, iclass 21, count 0 2006.245.07:44:02.68#ibcon#about to write, iclass 21, count 0 2006.245.07:44:02.68#ibcon#wrote, iclass 21, count 0 2006.245.07:44:02.68#ibcon#about to read 3, iclass 21, count 0 2006.245.07:44:02.70#ibcon#read 3, iclass 21, count 0 2006.245.07:44:02.70#ibcon#about to read 4, iclass 21, count 0 2006.245.07:44:02.70#ibcon#read 4, iclass 21, count 0 2006.245.07:44:02.70#ibcon#about to read 5, iclass 21, count 0 2006.245.07:44:02.70#ibcon#read 5, iclass 21, count 0 2006.245.07:44:02.70#ibcon#about to read 6, iclass 21, count 0 2006.245.07:44:02.70#ibcon#read 6, iclass 21, count 0 2006.245.07:44:02.70#ibcon#end of sib2, iclass 21, count 0 2006.245.07:44:02.70#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:44:02.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:44:02.70#ibcon#[25=USB\r\n] 2006.245.07:44:02.70#ibcon#*before write, iclass 21, count 0 2006.245.07:44:02.70#ibcon#enter sib2, iclass 21, count 0 2006.245.07:44:02.70#ibcon#flushed, iclass 21, count 0 2006.245.07:44:02.70#ibcon#about to write, iclass 21, count 0 2006.245.07:44:02.70#ibcon#wrote, iclass 21, count 0 2006.245.07:44:02.70#ibcon#about to read 3, iclass 21, count 0 2006.245.07:44:02.73#ibcon#read 3, iclass 21, count 0 2006.245.07:44:02.73#ibcon#about to read 4, iclass 21, count 0 2006.245.07:44:02.73#ibcon#read 4, iclass 21, count 0 2006.245.07:44:02.73#ibcon#about to read 5, iclass 21, count 0 2006.245.07:44:02.73#ibcon#read 5, iclass 21, count 0 2006.245.07:44:02.73#ibcon#about to read 6, iclass 21, count 0 2006.245.07:44:02.73#ibcon#read 6, iclass 21, count 0 2006.245.07:44:02.73#ibcon#end of sib2, iclass 21, count 0 2006.245.07:44:02.73#ibcon#*after write, iclass 21, count 0 2006.245.07:44:02.73#ibcon#*before return 0, iclass 21, count 0 2006.245.07:44:02.73#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:44:02.73#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:44:02.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:44:02.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:44:02.73$vc4f8/valo=8,852.99 2006.245.07:44:02.73#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.07:44:02.73#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.07:44:02.73#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:02.73#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:44:02.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:44:02.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:44:02.73#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:44:02.73#ibcon#first serial, iclass 23, count 0 2006.245.07:44:02.73#ibcon#enter sib2, iclass 23, count 0 2006.245.07:44:02.73#ibcon#flushed, iclass 23, count 0 2006.245.07:44:02.73#ibcon#about to write, iclass 23, count 0 2006.245.07:44:02.73#ibcon#wrote, iclass 23, count 0 2006.245.07:44:02.73#ibcon#about to read 3, iclass 23, count 0 2006.245.07:44:02.75#ibcon#read 3, iclass 23, count 0 2006.245.07:44:02.75#ibcon#about to read 4, iclass 23, count 0 2006.245.07:44:02.75#ibcon#read 4, iclass 23, count 0 2006.245.07:44:02.75#ibcon#about to read 5, iclass 23, count 0 2006.245.07:44:02.75#ibcon#read 5, iclass 23, count 0 2006.245.07:44:02.75#ibcon#about to read 6, iclass 23, count 0 2006.245.07:44:02.75#ibcon#read 6, iclass 23, count 0 2006.245.07:44:02.75#ibcon#end of sib2, iclass 23, count 0 2006.245.07:44:02.75#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:44:02.75#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:44:02.75#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:44:02.75#ibcon#*before write, iclass 23, count 0 2006.245.07:44:02.75#ibcon#enter sib2, iclass 23, count 0 2006.245.07:44:02.75#ibcon#flushed, iclass 23, count 0 2006.245.07:44:02.75#ibcon#about to write, iclass 23, count 0 2006.245.07:44:02.75#ibcon#wrote, iclass 23, count 0 2006.245.07:44:02.75#ibcon#about to read 3, iclass 23, count 0 2006.245.07:44:02.80#ibcon#read 3, iclass 23, count 0 2006.245.07:44:02.80#ibcon#about to read 4, iclass 23, count 0 2006.245.07:44:02.80#ibcon#read 4, iclass 23, count 0 2006.245.07:44:02.80#ibcon#about to read 5, iclass 23, count 0 2006.245.07:44:02.80#ibcon#read 5, iclass 23, count 0 2006.245.07:44:02.80#ibcon#about to read 6, iclass 23, count 0 2006.245.07:44:02.80#ibcon#read 6, iclass 23, count 0 2006.245.07:44:02.80#ibcon#end of sib2, iclass 23, count 0 2006.245.07:44:02.80#ibcon#*after write, iclass 23, count 0 2006.245.07:44:02.80#ibcon#*before return 0, iclass 23, count 0 2006.245.07:44:02.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:44:02.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:44:02.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:44:02.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:44:02.80$vc4f8/va=8,8 2006.245.07:44:02.80#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.07:44:02.80#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.07:44:02.80#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:02.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:44:02.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:44:02.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:44:02.85#ibcon#enter wrdev, iclass 25, count 2 2006.245.07:44:02.85#ibcon#first serial, iclass 25, count 2 2006.245.07:44:02.85#ibcon#enter sib2, iclass 25, count 2 2006.245.07:44:02.85#ibcon#flushed, iclass 25, count 2 2006.245.07:44:02.85#ibcon#about to write, iclass 25, count 2 2006.245.07:44:02.85#ibcon#wrote, iclass 25, count 2 2006.245.07:44:02.85#ibcon#about to read 3, iclass 25, count 2 2006.245.07:44:02.87#ibcon#read 3, iclass 25, count 2 2006.245.07:44:02.87#ibcon#about to read 4, iclass 25, count 2 2006.245.07:44:02.87#ibcon#read 4, iclass 25, count 2 2006.245.07:44:02.87#ibcon#about to read 5, iclass 25, count 2 2006.245.07:44:02.87#ibcon#read 5, iclass 25, count 2 2006.245.07:44:02.87#ibcon#about to read 6, iclass 25, count 2 2006.245.07:44:02.87#ibcon#read 6, iclass 25, count 2 2006.245.07:44:02.87#ibcon#end of sib2, iclass 25, count 2 2006.245.07:44:02.87#ibcon#*mode == 0, iclass 25, count 2 2006.245.07:44:02.87#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.07:44:02.87#ibcon#[25=AT08-08\r\n] 2006.245.07:44:02.87#ibcon#*before write, iclass 25, count 2 2006.245.07:44:02.87#ibcon#enter sib2, iclass 25, count 2 2006.245.07:44:02.87#ibcon#flushed, iclass 25, count 2 2006.245.07:44:02.87#ibcon#about to write, iclass 25, count 2 2006.245.07:44:02.87#ibcon#wrote, iclass 25, count 2 2006.245.07:44:02.87#ibcon#about to read 3, iclass 25, count 2 2006.245.07:44:02.90#ibcon#read 3, iclass 25, count 2 2006.245.07:44:02.90#ibcon#about to read 4, iclass 25, count 2 2006.245.07:44:02.90#ibcon#read 4, iclass 25, count 2 2006.245.07:44:02.90#ibcon#about to read 5, iclass 25, count 2 2006.245.07:44:02.90#ibcon#read 5, iclass 25, count 2 2006.245.07:44:02.90#ibcon#about to read 6, iclass 25, count 2 2006.245.07:44:02.90#ibcon#read 6, iclass 25, count 2 2006.245.07:44:02.90#ibcon#end of sib2, iclass 25, count 2 2006.245.07:44:02.90#ibcon#*after write, iclass 25, count 2 2006.245.07:44:02.90#ibcon#*before return 0, iclass 25, count 2 2006.245.07:44:02.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:44:02.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:44:02.90#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.07:44:02.90#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:02.90#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:44:03.02#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:44:03.02#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:44:03.02#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:44:03.02#ibcon#first serial, iclass 25, count 0 2006.245.07:44:03.02#ibcon#enter sib2, iclass 25, count 0 2006.245.07:44:03.02#ibcon#flushed, iclass 25, count 0 2006.245.07:44:03.02#ibcon#about to write, iclass 25, count 0 2006.245.07:44:03.02#ibcon#wrote, iclass 25, count 0 2006.245.07:44:03.02#ibcon#about to read 3, iclass 25, count 0 2006.245.07:44:03.04#ibcon#read 3, iclass 25, count 0 2006.245.07:44:03.04#ibcon#about to read 4, iclass 25, count 0 2006.245.07:44:03.04#ibcon#read 4, iclass 25, count 0 2006.245.07:44:03.04#ibcon#about to read 5, iclass 25, count 0 2006.245.07:44:03.04#ibcon#read 5, iclass 25, count 0 2006.245.07:44:03.04#ibcon#about to read 6, iclass 25, count 0 2006.245.07:44:03.04#ibcon#read 6, iclass 25, count 0 2006.245.07:44:03.04#ibcon#end of sib2, iclass 25, count 0 2006.245.07:44:03.04#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:44:03.04#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:44:03.04#ibcon#[25=USB\r\n] 2006.245.07:44:03.04#ibcon#*before write, iclass 25, count 0 2006.245.07:44:03.04#ibcon#enter sib2, iclass 25, count 0 2006.245.07:44:03.04#ibcon#flushed, iclass 25, count 0 2006.245.07:44:03.04#ibcon#about to write, iclass 25, count 0 2006.245.07:44:03.04#ibcon#wrote, iclass 25, count 0 2006.245.07:44:03.04#ibcon#about to read 3, iclass 25, count 0 2006.245.07:44:03.07#ibcon#read 3, iclass 25, count 0 2006.245.07:44:03.07#ibcon#about to read 4, iclass 25, count 0 2006.245.07:44:03.07#ibcon#read 4, iclass 25, count 0 2006.245.07:44:03.07#ibcon#about to read 5, iclass 25, count 0 2006.245.07:44:03.07#ibcon#read 5, iclass 25, count 0 2006.245.07:44:03.07#ibcon#about to read 6, iclass 25, count 0 2006.245.07:44:03.07#ibcon#read 6, iclass 25, count 0 2006.245.07:44:03.07#ibcon#end of sib2, iclass 25, count 0 2006.245.07:44:03.07#ibcon#*after write, iclass 25, count 0 2006.245.07:44:03.07#ibcon#*before return 0, iclass 25, count 0 2006.245.07:44:03.07#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:44:03.07#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:44:03.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:44:03.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:44:03.07$vc4f8/vblo=1,632.99 2006.245.07:44:03.07#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:44:03.07#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:44:03.07#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:03.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:44:03.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:44:03.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:44:03.07#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:44:03.07#ibcon#first serial, iclass 27, count 0 2006.245.07:44:03.07#ibcon#enter sib2, iclass 27, count 0 2006.245.07:44:03.07#ibcon#flushed, iclass 27, count 0 2006.245.07:44:03.07#ibcon#about to write, iclass 27, count 0 2006.245.07:44:03.07#ibcon#wrote, iclass 27, count 0 2006.245.07:44:03.07#ibcon#about to read 3, iclass 27, count 0 2006.245.07:44:03.09#ibcon#read 3, iclass 27, count 0 2006.245.07:44:03.09#ibcon#about to read 4, iclass 27, count 0 2006.245.07:44:03.09#ibcon#read 4, iclass 27, count 0 2006.245.07:44:03.09#ibcon#about to read 5, iclass 27, count 0 2006.245.07:44:03.09#ibcon#read 5, iclass 27, count 0 2006.245.07:44:03.09#ibcon#about to read 6, iclass 27, count 0 2006.245.07:44:03.09#ibcon#read 6, iclass 27, count 0 2006.245.07:44:03.09#ibcon#end of sib2, iclass 27, count 0 2006.245.07:44:03.09#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:44:03.09#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:44:03.09#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:44:03.09#ibcon#*before write, iclass 27, count 0 2006.245.07:44:03.09#ibcon#enter sib2, iclass 27, count 0 2006.245.07:44:03.09#ibcon#flushed, iclass 27, count 0 2006.245.07:44:03.09#ibcon#about to write, iclass 27, count 0 2006.245.07:44:03.09#ibcon#wrote, iclass 27, count 0 2006.245.07:44:03.09#ibcon#about to read 3, iclass 27, count 0 2006.245.07:44:03.13#ibcon#read 3, iclass 27, count 0 2006.245.07:44:03.13#ibcon#about to read 4, iclass 27, count 0 2006.245.07:44:03.13#ibcon#read 4, iclass 27, count 0 2006.245.07:44:03.13#ibcon#about to read 5, iclass 27, count 0 2006.245.07:44:03.13#ibcon#read 5, iclass 27, count 0 2006.245.07:44:03.13#ibcon#about to read 6, iclass 27, count 0 2006.245.07:44:03.13#ibcon#read 6, iclass 27, count 0 2006.245.07:44:03.13#ibcon#end of sib2, iclass 27, count 0 2006.245.07:44:03.13#ibcon#*after write, iclass 27, count 0 2006.245.07:44:03.13#ibcon#*before return 0, iclass 27, count 0 2006.245.07:44:03.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:44:03.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:44:03.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:44:03.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:44:03.13$vc4f8/vb=1,4 2006.245.07:44:03.13#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:44:03.13#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:44:03.13#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:03.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:44:03.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:44:03.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:44:03.13#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:44:03.13#ibcon#first serial, iclass 29, count 2 2006.245.07:44:03.13#ibcon#enter sib2, iclass 29, count 2 2006.245.07:44:03.13#ibcon#flushed, iclass 29, count 2 2006.245.07:44:03.13#ibcon#about to write, iclass 29, count 2 2006.245.07:44:03.13#ibcon#wrote, iclass 29, count 2 2006.245.07:44:03.13#ibcon#about to read 3, iclass 29, count 2 2006.245.07:44:03.15#ibcon#read 3, iclass 29, count 2 2006.245.07:44:03.15#ibcon#about to read 4, iclass 29, count 2 2006.245.07:44:03.15#ibcon#read 4, iclass 29, count 2 2006.245.07:44:03.15#ibcon#about to read 5, iclass 29, count 2 2006.245.07:44:03.15#ibcon#read 5, iclass 29, count 2 2006.245.07:44:03.15#ibcon#about to read 6, iclass 29, count 2 2006.245.07:44:03.15#ibcon#read 6, iclass 29, count 2 2006.245.07:44:03.15#ibcon#end of sib2, iclass 29, count 2 2006.245.07:44:03.15#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:44:03.15#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:44:03.15#ibcon#[27=AT01-04\r\n] 2006.245.07:44:03.15#ibcon#*before write, iclass 29, count 2 2006.245.07:44:03.15#ibcon#enter sib2, iclass 29, count 2 2006.245.07:44:03.15#ibcon#flushed, iclass 29, count 2 2006.245.07:44:03.15#ibcon#about to write, iclass 29, count 2 2006.245.07:44:03.15#ibcon#wrote, iclass 29, count 2 2006.245.07:44:03.15#ibcon#about to read 3, iclass 29, count 2 2006.245.07:44:03.18#ibcon#read 3, iclass 29, count 2 2006.245.07:44:03.18#ibcon#about to read 4, iclass 29, count 2 2006.245.07:44:03.18#ibcon#read 4, iclass 29, count 2 2006.245.07:44:03.18#ibcon#about to read 5, iclass 29, count 2 2006.245.07:44:03.18#ibcon#read 5, iclass 29, count 2 2006.245.07:44:03.18#ibcon#about to read 6, iclass 29, count 2 2006.245.07:44:03.18#ibcon#read 6, iclass 29, count 2 2006.245.07:44:03.18#ibcon#end of sib2, iclass 29, count 2 2006.245.07:44:03.18#ibcon#*after write, iclass 29, count 2 2006.245.07:44:03.18#ibcon#*before return 0, iclass 29, count 2 2006.245.07:44:03.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:44:03.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:44:03.18#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:44:03.18#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:03.18#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:44:03.30#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:44:03.30#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:44:03.30#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:44:03.30#ibcon#first serial, iclass 29, count 0 2006.245.07:44:03.30#ibcon#enter sib2, iclass 29, count 0 2006.245.07:44:03.30#ibcon#flushed, iclass 29, count 0 2006.245.07:44:03.30#ibcon#about to write, iclass 29, count 0 2006.245.07:44:03.30#ibcon#wrote, iclass 29, count 0 2006.245.07:44:03.30#ibcon#about to read 3, iclass 29, count 0 2006.245.07:44:03.32#ibcon#read 3, iclass 29, count 0 2006.245.07:44:03.32#ibcon#about to read 4, iclass 29, count 0 2006.245.07:44:03.32#ibcon#read 4, iclass 29, count 0 2006.245.07:44:03.32#ibcon#about to read 5, iclass 29, count 0 2006.245.07:44:03.32#ibcon#read 5, iclass 29, count 0 2006.245.07:44:03.32#ibcon#about to read 6, iclass 29, count 0 2006.245.07:44:03.32#ibcon#read 6, iclass 29, count 0 2006.245.07:44:03.32#ibcon#end of sib2, iclass 29, count 0 2006.245.07:44:03.32#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:44:03.32#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:44:03.32#ibcon#[27=USB\r\n] 2006.245.07:44:03.32#ibcon#*before write, iclass 29, count 0 2006.245.07:44:03.32#ibcon#enter sib2, iclass 29, count 0 2006.245.07:44:03.32#ibcon#flushed, iclass 29, count 0 2006.245.07:44:03.32#ibcon#about to write, iclass 29, count 0 2006.245.07:44:03.32#ibcon#wrote, iclass 29, count 0 2006.245.07:44:03.32#ibcon#about to read 3, iclass 29, count 0 2006.245.07:44:03.35#ibcon#read 3, iclass 29, count 0 2006.245.07:44:03.35#ibcon#about to read 4, iclass 29, count 0 2006.245.07:44:03.35#ibcon#read 4, iclass 29, count 0 2006.245.07:44:03.35#ibcon#about to read 5, iclass 29, count 0 2006.245.07:44:03.35#ibcon#read 5, iclass 29, count 0 2006.245.07:44:03.35#ibcon#about to read 6, iclass 29, count 0 2006.245.07:44:03.35#ibcon#read 6, iclass 29, count 0 2006.245.07:44:03.35#ibcon#end of sib2, iclass 29, count 0 2006.245.07:44:03.35#ibcon#*after write, iclass 29, count 0 2006.245.07:44:03.35#ibcon#*before return 0, iclass 29, count 0 2006.245.07:44:03.35#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:44:03.35#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:44:03.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:44:03.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:44:03.35$vc4f8/vblo=2,640.99 2006.245.07:44:03.35#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:44:03.35#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:44:03.35#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:03.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:03.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:03.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:03.35#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:44:03.35#ibcon#first serial, iclass 31, count 0 2006.245.07:44:03.35#ibcon#enter sib2, iclass 31, count 0 2006.245.07:44:03.35#ibcon#flushed, iclass 31, count 0 2006.245.07:44:03.35#ibcon#about to write, iclass 31, count 0 2006.245.07:44:03.35#ibcon#wrote, iclass 31, count 0 2006.245.07:44:03.35#ibcon#about to read 3, iclass 31, count 0 2006.245.07:44:03.37#ibcon#read 3, iclass 31, count 0 2006.245.07:44:03.37#ibcon#about to read 4, iclass 31, count 0 2006.245.07:44:03.37#ibcon#read 4, iclass 31, count 0 2006.245.07:44:03.37#ibcon#about to read 5, iclass 31, count 0 2006.245.07:44:03.37#ibcon#read 5, iclass 31, count 0 2006.245.07:44:03.37#ibcon#about to read 6, iclass 31, count 0 2006.245.07:44:03.37#ibcon#read 6, iclass 31, count 0 2006.245.07:44:03.37#ibcon#end of sib2, iclass 31, count 0 2006.245.07:44:03.37#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:44:03.37#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:44:03.37#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:44:03.37#ibcon#*before write, iclass 31, count 0 2006.245.07:44:03.37#ibcon#enter sib2, iclass 31, count 0 2006.245.07:44:03.37#ibcon#flushed, iclass 31, count 0 2006.245.07:44:03.37#ibcon#about to write, iclass 31, count 0 2006.245.07:44:03.37#ibcon#wrote, iclass 31, count 0 2006.245.07:44:03.37#ibcon#about to read 3, iclass 31, count 0 2006.245.07:44:03.41#ibcon#read 3, iclass 31, count 0 2006.245.07:44:03.41#ibcon#about to read 4, iclass 31, count 0 2006.245.07:44:03.41#ibcon#read 4, iclass 31, count 0 2006.245.07:44:03.41#ibcon#about to read 5, iclass 31, count 0 2006.245.07:44:03.41#ibcon#read 5, iclass 31, count 0 2006.245.07:44:03.41#ibcon#about to read 6, iclass 31, count 0 2006.245.07:44:03.41#ibcon#read 6, iclass 31, count 0 2006.245.07:44:03.41#ibcon#end of sib2, iclass 31, count 0 2006.245.07:44:03.41#ibcon#*after write, iclass 31, count 0 2006.245.07:44:03.41#ibcon#*before return 0, iclass 31, count 0 2006.245.07:44:03.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:03.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:44:03.41#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:44:03.41#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:44:03.41$vc4f8/vb=2,4 2006.245.07:44:03.41#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:44:03.41#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:44:03.41#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:03.41#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:03.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:03.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:03.47#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:44:03.47#ibcon#first serial, iclass 33, count 2 2006.245.07:44:03.47#ibcon#enter sib2, iclass 33, count 2 2006.245.07:44:03.47#ibcon#flushed, iclass 33, count 2 2006.245.07:44:03.47#ibcon#about to write, iclass 33, count 2 2006.245.07:44:03.47#ibcon#wrote, iclass 33, count 2 2006.245.07:44:03.47#ibcon#about to read 3, iclass 33, count 2 2006.245.07:44:03.49#ibcon#read 3, iclass 33, count 2 2006.245.07:44:03.49#ibcon#about to read 4, iclass 33, count 2 2006.245.07:44:03.49#ibcon#read 4, iclass 33, count 2 2006.245.07:44:03.49#ibcon#about to read 5, iclass 33, count 2 2006.245.07:44:03.49#ibcon#read 5, iclass 33, count 2 2006.245.07:44:03.49#ibcon#about to read 6, iclass 33, count 2 2006.245.07:44:03.49#ibcon#read 6, iclass 33, count 2 2006.245.07:44:03.49#ibcon#end of sib2, iclass 33, count 2 2006.245.07:44:03.49#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:44:03.49#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:44:03.49#ibcon#[27=AT02-04\r\n] 2006.245.07:44:03.49#ibcon#*before write, iclass 33, count 2 2006.245.07:44:03.49#ibcon#enter sib2, iclass 33, count 2 2006.245.07:44:03.49#ibcon#flushed, iclass 33, count 2 2006.245.07:44:03.49#ibcon#about to write, iclass 33, count 2 2006.245.07:44:03.49#ibcon#wrote, iclass 33, count 2 2006.245.07:44:03.49#ibcon#about to read 3, iclass 33, count 2 2006.245.07:44:03.52#ibcon#read 3, iclass 33, count 2 2006.245.07:44:03.52#ibcon#about to read 4, iclass 33, count 2 2006.245.07:44:03.52#ibcon#read 4, iclass 33, count 2 2006.245.07:44:03.52#ibcon#about to read 5, iclass 33, count 2 2006.245.07:44:03.52#ibcon#read 5, iclass 33, count 2 2006.245.07:44:03.52#ibcon#about to read 6, iclass 33, count 2 2006.245.07:44:03.52#ibcon#read 6, iclass 33, count 2 2006.245.07:44:03.52#ibcon#end of sib2, iclass 33, count 2 2006.245.07:44:03.52#ibcon#*after write, iclass 33, count 2 2006.245.07:44:03.52#ibcon#*before return 0, iclass 33, count 2 2006.245.07:44:03.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:03.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:44:03.52#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:44:03.52#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:03.52#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:03.64#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:03.64#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:03.64#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:44:03.64#ibcon#first serial, iclass 33, count 0 2006.245.07:44:03.64#ibcon#enter sib2, iclass 33, count 0 2006.245.07:44:03.64#ibcon#flushed, iclass 33, count 0 2006.245.07:44:03.64#ibcon#about to write, iclass 33, count 0 2006.245.07:44:03.64#ibcon#wrote, iclass 33, count 0 2006.245.07:44:03.64#ibcon#about to read 3, iclass 33, count 0 2006.245.07:44:03.66#ibcon#read 3, iclass 33, count 0 2006.245.07:44:03.66#ibcon#about to read 4, iclass 33, count 0 2006.245.07:44:03.66#ibcon#read 4, iclass 33, count 0 2006.245.07:44:03.66#ibcon#about to read 5, iclass 33, count 0 2006.245.07:44:03.66#ibcon#read 5, iclass 33, count 0 2006.245.07:44:03.66#ibcon#about to read 6, iclass 33, count 0 2006.245.07:44:03.66#ibcon#read 6, iclass 33, count 0 2006.245.07:44:03.66#ibcon#end of sib2, iclass 33, count 0 2006.245.07:44:03.66#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:44:03.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:44:03.66#ibcon#[27=USB\r\n] 2006.245.07:44:03.66#ibcon#*before write, iclass 33, count 0 2006.245.07:44:03.66#ibcon#enter sib2, iclass 33, count 0 2006.245.07:44:03.66#ibcon#flushed, iclass 33, count 0 2006.245.07:44:03.66#ibcon#about to write, iclass 33, count 0 2006.245.07:44:03.66#ibcon#wrote, iclass 33, count 0 2006.245.07:44:03.66#ibcon#about to read 3, iclass 33, count 0 2006.245.07:44:03.69#ibcon#read 3, iclass 33, count 0 2006.245.07:44:03.69#ibcon#about to read 4, iclass 33, count 0 2006.245.07:44:03.69#ibcon#read 4, iclass 33, count 0 2006.245.07:44:03.69#ibcon#about to read 5, iclass 33, count 0 2006.245.07:44:03.69#ibcon#read 5, iclass 33, count 0 2006.245.07:44:03.69#ibcon#about to read 6, iclass 33, count 0 2006.245.07:44:03.69#ibcon#read 6, iclass 33, count 0 2006.245.07:44:03.69#ibcon#end of sib2, iclass 33, count 0 2006.245.07:44:03.69#ibcon#*after write, iclass 33, count 0 2006.245.07:44:03.69#ibcon#*before return 0, iclass 33, count 0 2006.245.07:44:03.69#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:03.69#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:44:03.69#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:44:03.69#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:44:03.69$vc4f8/vblo=3,656.99 2006.245.07:44:03.69#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:44:03.69#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:44:03.69#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:03.69#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:03.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:03.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:03.69#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:44:03.69#ibcon#first serial, iclass 35, count 0 2006.245.07:44:03.69#ibcon#enter sib2, iclass 35, count 0 2006.245.07:44:03.69#ibcon#flushed, iclass 35, count 0 2006.245.07:44:03.69#ibcon#about to write, iclass 35, count 0 2006.245.07:44:03.69#ibcon#wrote, iclass 35, count 0 2006.245.07:44:03.69#ibcon#about to read 3, iclass 35, count 0 2006.245.07:44:03.71#ibcon#read 3, iclass 35, count 0 2006.245.07:44:03.71#ibcon#about to read 4, iclass 35, count 0 2006.245.07:44:03.71#ibcon#read 4, iclass 35, count 0 2006.245.07:44:03.71#ibcon#about to read 5, iclass 35, count 0 2006.245.07:44:03.71#ibcon#read 5, iclass 35, count 0 2006.245.07:44:03.71#ibcon#about to read 6, iclass 35, count 0 2006.245.07:44:03.71#ibcon#read 6, iclass 35, count 0 2006.245.07:44:03.71#ibcon#end of sib2, iclass 35, count 0 2006.245.07:44:03.71#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:44:03.71#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:44:03.71#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:44:03.71#ibcon#*before write, iclass 35, count 0 2006.245.07:44:03.71#ibcon#enter sib2, iclass 35, count 0 2006.245.07:44:03.71#ibcon#flushed, iclass 35, count 0 2006.245.07:44:03.71#ibcon#about to write, iclass 35, count 0 2006.245.07:44:03.71#ibcon#wrote, iclass 35, count 0 2006.245.07:44:03.71#ibcon#about to read 3, iclass 35, count 0 2006.245.07:44:03.76#ibcon#read 3, iclass 35, count 0 2006.245.07:44:03.76#ibcon#about to read 4, iclass 35, count 0 2006.245.07:44:03.76#ibcon#read 4, iclass 35, count 0 2006.245.07:44:03.76#ibcon#about to read 5, iclass 35, count 0 2006.245.07:44:03.76#ibcon#read 5, iclass 35, count 0 2006.245.07:44:03.76#ibcon#about to read 6, iclass 35, count 0 2006.245.07:44:03.76#ibcon#read 6, iclass 35, count 0 2006.245.07:44:03.76#ibcon#end of sib2, iclass 35, count 0 2006.245.07:44:03.76#ibcon#*after write, iclass 35, count 0 2006.245.07:44:03.76#ibcon#*before return 0, iclass 35, count 0 2006.245.07:44:03.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:03.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:44:03.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:44:03.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:44:03.76$vc4f8/vb=3,4 2006.245.07:44:03.76#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:44:03.76#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:44:03.76#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:03.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:03.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:03.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:03.81#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:44:03.81#ibcon#first serial, iclass 37, count 2 2006.245.07:44:03.81#ibcon#enter sib2, iclass 37, count 2 2006.245.07:44:03.81#ibcon#flushed, iclass 37, count 2 2006.245.07:44:03.81#ibcon#about to write, iclass 37, count 2 2006.245.07:44:03.81#ibcon#wrote, iclass 37, count 2 2006.245.07:44:03.81#ibcon#about to read 3, iclass 37, count 2 2006.245.07:44:03.83#ibcon#read 3, iclass 37, count 2 2006.245.07:44:03.83#ibcon#about to read 4, iclass 37, count 2 2006.245.07:44:03.83#ibcon#read 4, iclass 37, count 2 2006.245.07:44:03.83#ibcon#about to read 5, iclass 37, count 2 2006.245.07:44:03.83#ibcon#read 5, iclass 37, count 2 2006.245.07:44:03.83#ibcon#about to read 6, iclass 37, count 2 2006.245.07:44:03.83#ibcon#read 6, iclass 37, count 2 2006.245.07:44:03.83#ibcon#end of sib2, iclass 37, count 2 2006.245.07:44:03.83#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:44:03.83#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:44:03.83#ibcon#[27=AT03-04\r\n] 2006.245.07:44:03.83#ibcon#*before write, iclass 37, count 2 2006.245.07:44:03.83#ibcon#enter sib2, iclass 37, count 2 2006.245.07:44:03.83#ibcon#flushed, iclass 37, count 2 2006.245.07:44:03.83#ibcon#about to write, iclass 37, count 2 2006.245.07:44:03.83#ibcon#wrote, iclass 37, count 2 2006.245.07:44:03.83#ibcon#about to read 3, iclass 37, count 2 2006.245.07:44:03.86#ibcon#read 3, iclass 37, count 2 2006.245.07:44:03.86#ibcon#about to read 4, iclass 37, count 2 2006.245.07:44:03.86#ibcon#read 4, iclass 37, count 2 2006.245.07:44:03.86#ibcon#about to read 5, iclass 37, count 2 2006.245.07:44:03.86#ibcon#read 5, iclass 37, count 2 2006.245.07:44:03.86#ibcon#about to read 6, iclass 37, count 2 2006.245.07:44:03.86#ibcon#read 6, iclass 37, count 2 2006.245.07:44:03.86#ibcon#end of sib2, iclass 37, count 2 2006.245.07:44:03.86#ibcon#*after write, iclass 37, count 2 2006.245.07:44:03.86#ibcon#*before return 0, iclass 37, count 2 2006.245.07:44:03.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:03.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:44:03.86#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:44:03.86#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:03.86#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:03.98#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:03.98#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:03.98#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:44:03.98#ibcon#first serial, iclass 37, count 0 2006.245.07:44:03.98#ibcon#enter sib2, iclass 37, count 0 2006.245.07:44:03.98#ibcon#flushed, iclass 37, count 0 2006.245.07:44:03.98#ibcon#about to write, iclass 37, count 0 2006.245.07:44:03.98#ibcon#wrote, iclass 37, count 0 2006.245.07:44:03.98#ibcon#about to read 3, iclass 37, count 0 2006.245.07:44:04.00#ibcon#read 3, iclass 37, count 0 2006.245.07:44:04.00#ibcon#about to read 4, iclass 37, count 0 2006.245.07:44:04.00#ibcon#read 4, iclass 37, count 0 2006.245.07:44:04.00#ibcon#about to read 5, iclass 37, count 0 2006.245.07:44:04.00#ibcon#read 5, iclass 37, count 0 2006.245.07:44:04.00#ibcon#about to read 6, iclass 37, count 0 2006.245.07:44:04.00#ibcon#read 6, iclass 37, count 0 2006.245.07:44:04.00#ibcon#end of sib2, iclass 37, count 0 2006.245.07:44:04.00#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:44:04.00#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:44:04.00#ibcon#[27=USB\r\n] 2006.245.07:44:04.00#ibcon#*before write, iclass 37, count 0 2006.245.07:44:04.00#ibcon#enter sib2, iclass 37, count 0 2006.245.07:44:04.00#ibcon#flushed, iclass 37, count 0 2006.245.07:44:04.00#ibcon#about to write, iclass 37, count 0 2006.245.07:44:04.00#ibcon#wrote, iclass 37, count 0 2006.245.07:44:04.00#ibcon#about to read 3, iclass 37, count 0 2006.245.07:44:04.03#ibcon#read 3, iclass 37, count 0 2006.245.07:44:04.03#ibcon#about to read 4, iclass 37, count 0 2006.245.07:44:04.03#ibcon#read 4, iclass 37, count 0 2006.245.07:44:04.03#ibcon#about to read 5, iclass 37, count 0 2006.245.07:44:04.03#ibcon#read 5, iclass 37, count 0 2006.245.07:44:04.03#ibcon#about to read 6, iclass 37, count 0 2006.245.07:44:04.03#ibcon#read 6, iclass 37, count 0 2006.245.07:44:04.03#ibcon#end of sib2, iclass 37, count 0 2006.245.07:44:04.03#ibcon#*after write, iclass 37, count 0 2006.245.07:44:04.03#ibcon#*before return 0, iclass 37, count 0 2006.245.07:44:04.03#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:04.03#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:44:04.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:44:04.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:44:04.03$vc4f8/vblo=4,712.99 2006.245.07:44:04.03#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:44:04.03#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:44:04.03#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:04.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:04.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:04.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:04.03#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:44:04.03#ibcon#first serial, iclass 39, count 0 2006.245.07:44:04.03#ibcon#enter sib2, iclass 39, count 0 2006.245.07:44:04.03#ibcon#flushed, iclass 39, count 0 2006.245.07:44:04.03#ibcon#about to write, iclass 39, count 0 2006.245.07:44:04.03#ibcon#wrote, iclass 39, count 0 2006.245.07:44:04.03#ibcon#about to read 3, iclass 39, count 0 2006.245.07:44:04.05#ibcon#read 3, iclass 39, count 0 2006.245.07:44:04.05#ibcon#about to read 4, iclass 39, count 0 2006.245.07:44:04.05#ibcon#read 4, iclass 39, count 0 2006.245.07:44:04.05#ibcon#about to read 5, iclass 39, count 0 2006.245.07:44:04.05#ibcon#read 5, iclass 39, count 0 2006.245.07:44:04.05#ibcon#about to read 6, iclass 39, count 0 2006.245.07:44:04.05#ibcon#read 6, iclass 39, count 0 2006.245.07:44:04.05#ibcon#end of sib2, iclass 39, count 0 2006.245.07:44:04.05#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:44:04.05#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:44:04.05#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:44:04.05#ibcon#*before write, iclass 39, count 0 2006.245.07:44:04.05#ibcon#enter sib2, iclass 39, count 0 2006.245.07:44:04.05#ibcon#flushed, iclass 39, count 0 2006.245.07:44:04.05#ibcon#about to write, iclass 39, count 0 2006.245.07:44:04.05#ibcon#wrote, iclass 39, count 0 2006.245.07:44:04.05#ibcon#about to read 3, iclass 39, count 0 2006.245.07:44:04.09#ibcon#read 3, iclass 39, count 0 2006.245.07:44:04.09#ibcon#about to read 4, iclass 39, count 0 2006.245.07:44:04.09#ibcon#read 4, iclass 39, count 0 2006.245.07:44:04.09#ibcon#about to read 5, iclass 39, count 0 2006.245.07:44:04.09#ibcon#read 5, iclass 39, count 0 2006.245.07:44:04.09#ibcon#about to read 6, iclass 39, count 0 2006.245.07:44:04.09#ibcon#read 6, iclass 39, count 0 2006.245.07:44:04.09#ibcon#end of sib2, iclass 39, count 0 2006.245.07:44:04.09#ibcon#*after write, iclass 39, count 0 2006.245.07:44:04.09#ibcon#*before return 0, iclass 39, count 0 2006.245.07:44:04.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:04.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:44:04.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:44:04.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:44:04.09$vc4f8/vb=4,4 2006.245.07:44:04.09#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:44:04.09#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:44:04.09#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:04.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:04.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:04.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:04.15#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:44:04.15#ibcon#first serial, iclass 3, count 2 2006.245.07:44:04.15#ibcon#enter sib2, iclass 3, count 2 2006.245.07:44:04.15#ibcon#flushed, iclass 3, count 2 2006.245.07:44:04.15#ibcon#about to write, iclass 3, count 2 2006.245.07:44:04.15#ibcon#wrote, iclass 3, count 2 2006.245.07:44:04.15#ibcon#about to read 3, iclass 3, count 2 2006.245.07:44:04.17#ibcon#read 3, iclass 3, count 2 2006.245.07:44:04.17#ibcon#about to read 4, iclass 3, count 2 2006.245.07:44:04.17#ibcon#read 4, iclass 3, count 2 2006.245.07:44:04.17#ibcon#about to read 5, iclass 3, count 2 2006.245.07:44:04.17#ibcon#read 5, iclass 3, count 2 2006.245.07:44:04.17#ibcon#about to read 6, iclass 3, count 2 2006.245.07:44:04.17#ibcon#read 6, iclass 3, count 2 2006.245.07:44:04.17#ibcon#end of sib2, iclass 3, count 2 2006.245.07:44:04.17#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:44:04.17#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:44:04.17#ibcon#[27=AT04-04\r\n] 2006.245.07:44:04.17#ibcon#*before write, iclass 3, count 2 2006.245.07:44:04.17#ibcon#enter sib2, iclass 3, count 2 2006.245.07:44:04.17#ibcon#flushed, iclass 3, count 2 2006.245.07:44:04.17#ibcon#about to write, iclass 3, count 2 2006.245.07:44:04.17#ibcon#wrote, iclass 3, count 2 2006.245.07:44:04.17#ibcon#about to read 3, iclass 3, count 2 2006.245.07:44:04.20#ibcon#read 3, iclass 3, count 2 2006.245.07:44:04.20#ibcon#about to read 4, iclass 3, count 2 2006.245.07:44:04.20#ibcon#read 4, iclass 3, count 2 2006.245.07:44:04.20#ibcon#about to read 5, iclass 3, count 2 2006.245.07:44:04.20#ibcon#read 5, iclass 3, count 2 2006.245.07:44:04.20#ibcon#about to read 6, iclass 3, count 2 2006.245.07:44:04.20#ibcon#read 6, iclass 3, count 2 2006.245.07:44:04.20#ibcon#end of sib2, iclass 3, count 2 2006.245.07:44:04.20#ibcon#*after write, iclass 3, count 2 2006.245.07:44:04.20#ibcon#*before return 0, iclass 3, count 2 2006.245.07:44:04.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:04.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:44:04.20#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:44:04.20#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:04.20#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:04.32#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:04.32#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:04.32#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:44:04.32#ibcon#first serial, iclass 3, count 0 2006.245.07:44:04.32#ibcon#enter sib2, iclass 3, count 0 2006.245.07:44:04.32#ibcon#flushed, iclass 3, count 0 2006.245.07:44:04.32#ibcon#about to write, iclass 3, count 0 2006.245.07:44:04.32#ibcon#wrote, iclass 3, count 0 2006.245.07:44:04.32#ibcon#about to read 3, iclass 3, count 0 2006.245.07:44:04.34#ibcon#read 3, iclass 3, count 0 2006.245.07:44:04.34#ibcon#about to read 4, iclass 3, count 0 2006.245.07:44:04.34#ibcon#read 4, iclass 3, count 0 2006.245.07:44:04.34#ibcon#about to read 5, iclass 3, count 0 2006.245.07:44:04.34#ibcon#read 5, iclass 3, count 0 2006.245.07:44:04.34#ibcon#about to read 6, iclass 3, count 0 2006.245.07:44:04.34#ibcon#read 6, iclass 3, count 0 2006.245.07:44:04.34#ibcon#end of sib2, iclass 3, count 0 2006.245.07:44:04.34#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:44:04.34#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:44:04.34#ibcon#[27=USB\r\n] 2006.245.07:44:04.34#ibcon#*before write, iclass 3, count 0 2006.245.07:44:04.34#ibcon#enter sib2, iclass 3, count 0 2006.245.07:44:04.34#ibcon#flushed, iclass 3, count 0 2006.245.07:44:04.34#ibcon#about to write, iclass 3, count 0 2006.245.07:44:04.34#ibcon#wrote, iclass 3, count 0 2006.245.07:44:04.34#ibcon#about to read 3, iclass 3, count 0 2006.245.07:44:04.37#ibcon#read 3, iclass 3, count 0 2006.245.07:44:04.37#ibcon#about to read 4, iclass 3, count 0 2006.245.07:44:04.37#ibcon#read 4, iclass 3, count 0 2006.245.07:44:04.37#ibcon#about to read 5, iclass 3, count 0 2006.245.07:44:04.37#ibcon#read 5, iclass 3, count 0 2006.245.07:44:04.37#ibcon#about to read 6, iclass 3, count 0 2006.245.07:44:04.37#ibcon#read 6, iclass 3, count 0 2006.245.07:44:04.37#ibcon#end of sib2, iclass 3, count 0 2006.245.07:44:04.37#ibcon#*after write, iclass 3, count 0 2006.245.07:44:04.37#ibcon#*before return 0, iclass 3, count 0 2006.245.07:44:04.37#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:04.37#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:44:04.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:44:04.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:44:04.37$vc4f8/vblo=5,744.99 2006.245.07:44:04.37#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:44:04.37#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:44:04.37#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:04.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:04.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:04.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:04.37#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:44:04.37#ibcon#first serial, iclass 5, count 0 2006.245.07:44:04.37#ibcon#enter sib2, iclass 5, count 0 2006.245.07:44:04.37#ibcon#flushed, iclass 5, count 0 2006.245.07:44:04.37#ibcon#about to write, iclass 5, count 0 2006.245.07:44:04.37#ibcon#wrote, iclass 5, count 0 2006.245.07:44:04.37#ibcon#about to read 3, iclass 5, count 0 2006.245.07:44:04.39#ibcon#read 3, iclass 5, count 0 2006.245.07:44:04.39#ibcon#about to read 4, iclass 5, count 0 2006.245.07:44:04.39#ibcon#read 4, iclass 5, count 0 2006.245.07:44:04.39#ibcon#about to read 5, iclass 5, count 0 2006.245.07:44:04.39#ibcon#read 5, iclass 5, count 0 2006.245.07:44:04.39#ibcon#about to read 6, iclass 5, count 0 2006.245.07:44:04.39#ibcon#read 6, iclass 5, count 0 2006.245.07:44:04.39#ibcon#end of sib2, iclass 5, count 0 2006.245.07:44:04.39#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:44:04.39#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:44:04.39#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:44:04.39#ibcon#*before write, iclass 5, count 0 2006.245.07:44:04.39#ibcon#enter sib2, iclass 5, count 0 2006.245.07:44:04.39#ibcon#flushed, iclass 5, count 0 2006.245.07:44:04.39#ibcon#about to write, iclass 5, count 0 2006.245.07:44:04.39#ibcon#wrote, iclass 5, count 0 2006.245.07:44:04.39#ibcon#about to read 3, iclass 5, count 0 2006.245.07:44:04.44#ibcon#read 3, iclass 5, count 0 2006.245.07:44:04.44#ibcon#about to read 4, iclass 5, count 0 2006.245.07:44:04.44#ibcon#read 4, iclass 5, count 0 2006.245.07:44:04.44#ibcon#about to read 5, iclass 5, count 0 2006.245.07:44:04.44#ibcon#read 5, iclass 5, count 0 2006.245.07:44:04.44#ibcon#about to read 6, iclass 5, count 0 2006.245.07:44:04.44#ibcon#read 6, iclass 5, count 0 2006.245.07:44:04.44#ibcon#end of sib2, iclass 5, count 0 2006.245.07:44:04.44#ibcon#*after write, iclass 5, count 0 2006.245.07:44:04.44#ibcon#*before return 0, iclass 5, count 0 2006.245.07:44:04.44#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:04.44#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:44:04.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:44:04.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:44:04.44$vc4f8/vb=5,3 2006.245.07:44:04.44#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:44:04.44#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:44:04.44#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:04.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:04.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:04.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:04.49#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:44:04.49#ibcon#first serial, iclass 7, count 2 2006.245.07:44:04.49#ibcon#enter sib2, iclass 7, count 2 2006.245.07:44:04.49#ibcon#flushed, iclass 7, count 2 2006.245.07:44:04.49#ibcon#about to write, iclass 7, count 2 2006.245.07:44:04.49#ibcon#wrote, iclass 7, count 2 2006.245.07:44:04.49#ibcon#about to read 3, iclass 7, count 2 2006.245.07:44:04.51#ibcon#read 3, iclass 7, count 2 2006.245.07:44:04.51#ibcon#about to read 4, iclass 7, count 2 2006.245.07:44:04.51#ibcon#read 4, iclass 7, count 2 2006.245.07:44:04.51#ibcon#about to read 5, iclass 7, count 2 2006.245.07:44:04.51#ibcon#read 5, iclass 7, count 2 2006.245.07:44:04.51#ibcon#about to read 6, iclass 7, count 2 2006.245.07:44:04.51#ibcon#read 6, iclass 7, count 2 2006.245.07:44:04.51#ibcon#end of sib2, iclass 7, count 2 2006.245.07:44:04.51#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:44:04.51#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:44:04.51#ibcon#[27=AT05-03\r\n] 2006.245.07:44:04.51#ibcon#*before write, iclass 7, count 2 2006.245.07:44:04.51#ibcon#enter sib2, iclass 7, count 2 2006.245.07:44:04.51#ibcon#flushed, iclass 7, count 2 2006.245.07:44:04.51#ibcon#about to write, iclass 7, count 2 2006.245.07:44:04.51#ibcon#wrote, iclass 7, count 2 2006.245.07:44:04.51#ibcon#about to read 3, iclass 7, count 2 2006.245.07:44:04.54#ibcon#read 3, iclass 7, count 2 2006.245.07:44:04.54#ibcon#about to read 4, iclass 7, count 2 2006.245.07:44:04.54#ibcon#read 4, iclass 7, count 2 2006.245.07:44:04.54#ibcon#about to read 5, iclass 7, count 2 2006.245.07:44:04.54#ibcon#read 5, iclass 7, count 2 2006.245.07:44:04.54#ibcon#about to read 6, iclass 7, count 2 2006.245.07:44:04.54#ibcon#read 6, iclass 7, count 2 2006.245.07:44:04.54#ibcon#end of sib2, iclass 7, count 2 2006.245.07:44:04.54#ibcon#*after write, iclass 7, count 2 2006.245.07:44:04.54#ibcon#*before return 0, iclass 7, count 2 2006.245.07:44:04.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:04.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:44:04.54#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:44:04.54#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:04.54#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:04.66#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:04.66#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:04.66#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:44:04.66#ibcon#first serial, iclass 7, count 0 2006.245.07:44:04.66#ibcon#enter sib2, iclass 7, count 0 2006.245.07:44:04.66#ibcon#flushed, iclass 7, count 0 2006.245.07:44:04.66#ibcon#about to write, iclass 7, count 0 2006.245.07:44:04.66#ibcon#wrote, iclass 7, count 0 2006.245.07:44:04.66#ibcon#about to read 3, iclass 7, count 0 2006.245.07:44:04.68#ibcon#read 3, iclass 7, count 0 2006.245.07:44:04.68#ibcon#about to read 4, iclass 7, count 0 2006.245.07:44:04.68#ibcon#read 4, iclass 7, count 0 2006.245.07:44:04.68#ibcon#about to read 5, iclass 7, count 0 2006.245.07:44:04.68#ibcon#read 5, iclass 7, count 0 2006.245.07:44:04.68#ibcon#about to read 6, iclass 7, count 0 2006.245.07:44:04.68#ibcon#read 6, iclass 7, count 0 2006.245.07:44:04.68#ibcon#end of sib2, iclass 7, count 0 2006.245.07:44:04.68#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:44:04.68#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:44:04.68#ibcon#[27=USB\r\n] 2006.245.07:44:04.68#ibcon#*before write, iclass 7, count 0 2006.245.07:44:04.68#ibcon#enter sib2, iclass 7, count 0 2006.245.07:44:04.68#ibcon#flushed, iclass 7, count 0 2006.245.07:44:04.68#ibcon#about to write, iclass 7, count 0 2006.245.07:44:04.68#ibcon#wrote, iclass 7, count 0 2006.245.07:44:04.68#ibcon#about to read 3, iclass 7, count 0 2006.245.07:44:04.71#ibcon#read 3, iclass 7, count 0 2006.245.07:44:04.71#ibcon#about to read 4, iclass 7, count 0 2006.245.07:44:04.71#ibcon#read 4, iclass 7, count 0 2006.245.07:44:04.71#ibcon#about to read 5, iclass 7, count 0 2006.245.07:44:04.71#ibcon#read 5, iclass 7, count 0 2006.245.07:44:04.71#ibcon#about to read 6, iclass 7, count 0 2006.245.07:44:04.71#ibcon#read 6, iclass 7, count 0 2006.245.07:44:04.71#ibcon#end of sib2, iclass 7, count 0 2006.245.07:44:04.71#ibcon#*after write, iclass 7, count 0 2006.245.07:44:04.71#ibcon#*before return 0, iclass 7, count 0 2006.245.07:44:04.71#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:04.71#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:44:04.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:44:04.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:44:04.71$vc4f8/vblo=6,752.99 2006.245.07:44:04.71#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:44:04.71#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:44:04.71#ibcon#ireg 17 cls_cnt 0 2006.245.07:44:04.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:04.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:04.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:04.71#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:44:04.71#ibcon#first serial, iclass 11, count 0 2006.245.07:44:04.71#ibcon#enter sib2, iclass 11, count 0 2006.245.07:44:04.71#ibcon#flushed, iclass 11, count 0 2006.245.07:44:04.71#ibcon#about to write, iclass 11, count 0 2006.245.07:44:04.71#ibcon#wrote, iclass 11, count 0 2006.245.07:44:04.71#ibcon#about to read 3, iclass 11, count 0 2006.245.07:44:04.73#ibcon#read 3, iclass 11, count 0 2006.245.07:44:04.73#ibcon#about to read 4, iclass 11, count 0 2006.245.07:44:04.73#ibcon#read 4, iclass 11, count 0 2006.245.07:44:04.73#ibcon#about to read 5, iclass 11, count 0 2006.245.07:44:04.73#ibcon#read 5, iclass 11, count 0 2006.245.07:44:04.73#ibcon#about to read 6, iclass 11, count 0 2006.245.07:44:04.73#ibcon#read 6, iclass 11, count 0 2006.245.07:44:04.73#ibcon#end of sib2, iclass 11, count 0 2006.245.07:44:04.73#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:44:04.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:44:04.73#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:44:04.73#ibcon#*before write, iclass 11, count 0 2006.245.07:44:04.73#ibcon#enter sib2, iclass 11, count 0 2006.245.07:44:04.73#ibcon#flushed, iclass 11, count 0 2006.245.07:44:04.73#ibcon#about to write, iclass 11, count 0 2006.245.07:44:04.73#ibcon#wrote, iclass 11, count 0 2006.245.07:44:04.73#ibcon#about to read 3, iclass 11, count 0 2006.245.07:44:04.77#ibcon#read 3, iclass 11, count 0 2006.245.07:44:04.77#ibcon#about to read 4, iclass 11, count 0 2006.245.07:44:04.77#ibcon#read 4, iclass 11, count 0 2006.245.07:44:04.77#ibcon#about to read 5, iclass 11, count 0 2006.245.07:44:04.77#ibcon#read 5, iclass 11, count 0 2006.245.07:44:04.77#ibcon#about to read 6, iclass 11, count 0 2006.245.07:44:04.77#ibcon#read 6, iclass 11, count 0 2006.245.07:44:04.77#ibcon#end of sib2, iclass 11, count 0 2006.245.07:44:04.77#ibcon#*after write, iclass 11, count 0 2006.245.07:44:04.77#ibcon#*before return 0, iclass 11, count 0 2006.245.07:44:04.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:04.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:44:04.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:44:04.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:44:04.77$vc4f8/vb=6,3 2006.245.07:44:04.77#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.07:44:04.77#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.07:44:04.77#ibcon#ireg 11 cls_cnt 2 2006.245.07:44:04.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:04.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:04.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:04.83#ibcon#enter wrdev, iclass 13, count 2 2006.245.07:44:04.83#ibcon#first serial, iclass 13, count 2 2006.245.07:44:04.83#ibcon#enter sib2, iclass 13, count 2 2006.245.07:44:04.83#ibcon#flushed, iclass 13, count 2 2006.245.07:44:04.83#ibcon#about to write, iclass 13, count 2 2006.245.07:44:04.83#ibcon#wrote, iclass 13, count 2 2006.245.07:44:04.83#ibcon#about to read 3, iclass 13, count 2 2006.245.07:44:04.85#ibcon#read 3, iclass 13, count 2 2006.245.07:44:04.85#ibcon#about to read 4, iclass 13, count 2 2006.245.07:44:04.85#ibcon#read 4, iclass 13, count 2 2006.245.07:44:04.85#ibcon#about to read 5, iclass 13, count 2 2006.245.07:44:04.85#ibcon#read 5, iclass 13, count 2 2006.245.07:44:04.85#ibcon#about to read 6, iclass 13, count 2 2006.245.07:44:04.85#ibcon#read 6, iclass 13, count 2 2006.245.07:44:04.85#ibcon#end of sib2, iclass 13, count 2 2006.245.07:44:04.85#ibcon#*mode == 0, iclass 13, count 2 2006.245.07:44:04.85#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.07:44:04.85#ibcon#[27=AT06-03\r\n] 2006.245.07:44:04.85#ibcon#*before write, iclass 13, count 2 2006.245.07:44:04.85#ibcon#enter sib2, iclass 13, count 2 2006.245.07:44:04.85#ibcon#flushed, iclass 13, count 2 2006.245.07:44:04.85#ibcon#about to write, iclass 13, count 2 2006.245.07:44:04.85#ibcon#wrote, iclass 13, count 2 2006.245.07:44:04.85#ibcon#about to read 3, iclass 13, count 2 2006.245.07:44:04.88#ibcon#read 3, iclass 13, count 2 2006.245.07:44:04.88#ibcon#about to read 4, iclass 13, count 2 2006.245.07:44:04.88#ibcon#read 4, iclass 13, count 2 2006.245.07:44:04.88#ibcon#about to read 5, iclass 13, count 2 2006.245.07:44:04.88#ibcon#read 5, iclass 13, count 2 2006.245.07:44:04.88#ibcon#about to read 6, iclass 13, count 2 2006.245.07:44:04.88#ibcon#read 6, iclass 13, count 2 2006.245.07:44:04.88#ibcon#end of sib2, iclass 13, count 2 2006.245.07:44:04.88#ibcon#*after write, iclass 13, count 2 2006.245.07:44:04.88#ibcon#*before return 0, iclass 13, count 2 2006.245.07:44:04.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:04.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:44:04.88#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.07:44:04.88#ibcon#ireg 7 cls_cnt 0 2006.245.07:44:04.88#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:05.00#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:05.00#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:05.00#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:44:05.00#ibcon#first serial, iclass 13, count 0 2006.245.07:44:05.00#ibcon#enter sib2, iclass 13, count 0 2006.245.07:44:05.00#ibcon#flushed, iclass 13, count 0 2006.245.07:44:05.00#ibcon#about to write, iclass 13, count 0 2006.245.07:44:05.00#ibcon#wrote, iclass 13, count 0 2006.245.07:44:05.00#ibcon#about to read 3, iclass 13, count 0 2006.245.07:44:05.02#ibcon#read 3, iclass 13, count 0 2006.245.07:44:05.02#ibcon#about to read 4, iclass 13, count 0 2006.245.07:44:05.02#ibcon#read 4, iclass 13, count 0 2006.245.07:44:05.02#ibcon#about to read 5, iclass 13, count 0 2006.245.07:44:05.02#ibcon#read 5, iclass 13, count 0 2006.245.07:44:05.02#ibcon#about to read 6, iclass 13, count 0 2006.245.07:44:05.02#ibcon#read 6, iclass 13, count 0 2006.245.07:44:05.02#ibcon#end of sib2, iclass 13, count 0 2006.245.07:44:05.02#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:44:05.02#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:44:05.02#ibcon#[27=USB\r\n] 2006.245.07:44:05.02#ibcon#*before write, iclass 13, count 0 2006.245.07:44:05.02#ibcon#enter sib2, iclass 13, count 0 2006.245.07:44:05.02#ibcon#flushed, iclass 13, count 0 2006.245.07:44:05.02#ibcon#about to write, iclass 13, count 0 2006.245.07:44:05.02#ibcon#wrote, iclass 13, count 0 2006.245.07:44:05.02#ibcon#about to read 3, iclass 13, count 0 2006.245.07:44:05.05#ibcon#read 3, iclass 13, count 0 2006.245.07:44:05.05#ibcon#about to read 4, iclass 13, count 0 2006.245.07:44:05.05#ibcon#read 4, iclass 13, count 0 2006.245.07:44:05.05#ibcon#about to read 5, iclass 13, count 0 2006.245.07:44:05.05#ibcon#read 5, iclass 13, count 0 2006.245.07:44:05.05#ibcon#about to read 6, iclass 13, count 0 2006.245.07:44:05.05#ibcon#read 6, iclass 13, count 0 2006.245.07:44:05.05#ibcon#end of sib2, iclass 13, count 0 2006.245.07:44:05.05#ibcon#*after write, iclass 13, count 0 2006.245.07:44:05.05#ibcon#*before return 0, iclass 13, count 0 2006.245.07:44:05.05#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:05.05#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:44:05.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:44:05.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:44:05.05$vc4f8/vabw=wide 2006.245.07:44:05.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.07:44:05.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.07:44:05.05#ibcon#ireg 8 cls_cnt 0 2006.245.07:44:05.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:05.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:05.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:05.05#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:44:05.05#ibcon#first serial, iclass 15, count 0 2006.245.07:44:05.05#ibcon#enter sib2, iclass 15, count 0 2006.245.07:44:05.05#ibcon#flushed, iclass 15, count 0 2006.245.07:44:05.05#ibcon#about to write, iclass 15, count 0 2006.245.07:44:05.05#ibcon#wrote, iclass 15, count 0 2006.245.07:44:05.05#ibcon#about to read 3, iclass 15, count 0 2006.245.07:44:05.07#ibcon#read 3, iclass 15, count 0 2006.245.07:44:05.07#ibcon#about to read 4, iclass 15, count 0 2006.245.07:44:05.07#ibcon#read 4, iclass 15, count 0 2006.245.07:44:05.07#ibcon#about to read 5, iclass 15, count 0 2006.245.07:44:05.07#ibcon#read 5, iclass 15, count 0 2006.245.07:44:05.07#ibcon#about to read 6, iclass 15, count 0 2006.245.07:44:05.07#ibcon#read 6, iclass 15, count 0 2006.245.07:44:05.07#ibcon#end of sib2, iclass 15, count 0 2006.245.07:44:05.07#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:44:05.07#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:44:05.07#ibcon#[25=BW32\r\n] 2006.245.07:44:05.07#ibcon#*before write, iclass 15, count 0 2006.245.07:44:05.07#ibcon#enter sib2, iclass 15, count 0 2006.245.07:44:05.07#ibcon#flushed, iclass 15, count 0 2006.245.07:44:05.07#ibcon#about to write, iclass 15, count 0 2006.245.07:44:05.07#ibcon#wrote, iclass 15, count 0 2006.245.07:44:05.07#ibcon#about to read 3, iclass 15, count 0 2006.245.07:44:05.10#ibcon#read 3, iclass 15, count 0 2006.245.07:44:05.10#ibcon#about to read 4, iclass 15, count 0 2006.245.07:44:05.10#ibcon#read 4, iclass 15, count 0 2006.245.07:44:05.10#ibcon#about to read 5, iclass 15, count 0 2006.245.07:44:05.10#ibcon#read 5, iclass 15, count 0 2006.245.07:44:05.10#ibcon#about to read 6, iclass 15, count 0 2006.245.07:44:05.10#ibcon#read 6, iclass 15, count 0 2006.245.07:44:05.10#ibcon#end of sib2, iclass 15, count 0 2006.245.07:44:05.10#ibcon#*after write, iclass 15, count 0 2006.245.07:44:05.10#ibcon#*before return 0, iclass 15, count 0 2006.245.07:44:05.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:05.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:44:05.10#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:44:05.10#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:44:05.10$vc4f8/vbbw=wide 2006.245.07:44:05.10#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.07:44:05.10#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.07:44:05.10#ibcon#ireg 8 cls_cnt 0 2006.245.07:44:05.10#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:44:05.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:44:05.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:44:05.17#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:44:05.17#ibcon#first serial, iclass 17, count 0 2006.245.07:44:05.17#ibcon#enter sib2, iclass 17, count 0 2006.245.07:44:05.17#ibcon#flushed, iclass 17, count 0 2006.245.07:44:05.17#ibcon#about to write, iclass 17, count 0 2006.245.07:44:05.17#ibcon#wrote, iclass 17, count 0 2006.245.07:44:05.17#ibcon#about to read 3, iclass 17, count 0 2006.245.07:44:05.19#ibcon#read 3, iclass 17, count 0 2006.245.07:44:05.19#ibcon#about to read 4, iclass 17, count 0 2006.245.07:44:05.19#ibcon#read 4, iclass 17, count 0 2006.245.07:44:05.19#ibcon#about to read 5, iclass 17, count 0 2006.245.07:44:05.19#ibcon#read 5, iclass 17, count 0 2006.245.07:44:05.19#ibcon#about to read 6, iclass 17, count 0 2006.245.07:44:05.19#ibcon#read 6, iclass 17, count 0 2006.245.07:44:05.19#ibcon#end of sib2, iclass 17, count 0 2006.245.07:44:05.19#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:44:05.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:44:05.19#ibcon#[27=BW32\r\n] 2006.245.07:44:05.19#ibcon#*before write, iclass 17, count 0 2006.245.07:44:05.19#ibcon#enter sib2, iclass 17, count 0 2006.245.07:44:05.19#ibcon#flushed, iclass 17, count 0 2006.245.07:44:05.19#ibcon#about to write, iclass 17, count 0 2006.245.07:44:05.19#ibcon#wrote, iclass 17, count 0 2006.245.07:44:05.19#ibcon#about to read 3, iclass 17, count 0 2006.245.07:44:05.22#ibcon#read 3, iclass 17, count 0 2006.245.07:44:05.22#ibcon#about to read 4, iclass 17, count 0 2006.245.07:44:05.22#ibcon#read 4, iclass 17, count 0 2006.245.07:44:05.22#ibcon#about to read 5, iclass 17, count 0 2006.245.07:44:05.22#ibcon#read 5, iclass 17, count 0 2006.245.07:44:05.22#ibcon#about to read 6, iclass 17, count 0 2006.245.07:44:05.22#ibcon#read 6, iclass 17, count 0 2006.245.07:44:05.22#ibcon#end of sib2, iclass 17, count 0 2006.245.07:44:05.22#ibcon#*after write, iclass 17, count 0 2006.245.07:44:05.22#ibcon#*before return 0, iclass 17, count 0 2006.245.07:44:05.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:44:05.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:44:05.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:44:05.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:44:05.22$4f8m12a/ifd4f 2006.245.07:44:05.22$ifd4f/lo= 2006.245.07:44:05.22$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:44:05.22$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:44:05.22$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:44:05.22$ifd4f/patch= 2006.245.07:44:05.22$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:44:05.22$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:44:05.22$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:44:05.22$4f8m12a/"form=m,16.000,1:2 2006.245.07:44:05.22$4f8m12a/"tpicd 2006.245.07:44:05.22$4f8m12a/echo=off 2006.245.07:44:05.22$4f8m12a/xlog=off 2006.245.07:44:05.22:!2006.245.07:44:30 2006.245.07:44:15.14#trakl#Source acquired 2006.245.07:44:15.14#flagr#flagr/antenna,acquired 2006.245.07:44:30.00:preob 2006.245.07:44:31.14/onsource/TRACKING 2006.245.07:44:31.14:!2006.245.07:44:40 2006.245.07:44:40.00:data_valid=on 2006.245.07:44:40.00:midob 2006.245.07:44:40.14/onsource/TRACKING 2006.245.07:44:40.14/wx/27.43,1004.5,66 2006.245.07:44:40.23/cable/+6.4090E-03 2006.245.07:44:41.32/va/01,08,usb,yes,35,37 2006.245.07:44:41.32/va/02,07,usb,yes,35,37 2006.245.07:44:41.32/va/03,06,usb,yes,37,37 2006.245.07:44:41.32/va/04,07,usb,yes,36,39 2006.245.07:44:41.32/va/05,07,usb,yes,38,40 2006.245.07:44:41.32/va/06,07,usb,yes,33,33 2006.245.07:44:41.32/va/07,07,usb,yes,33,33 2006.245.07:44:41.32/va/08,08,usb,yes,29,28 2006.245.07:44:41.55/valo/01,532.99,yes,locked 2006.245.07:44:41.55/valo/02,572.99,yes,locked 2006.245.07:44:41.55/valo/03,672.99,yes,locked 2006.245.07:44:41.55/valo/04,832.99,yes,locked 2006.245.07:44:41.55/valo/05,652.99,yes,locked 2006.245.07:44:41.55/valo/06,772.99,yes,locked 2006.245.07:44:41.55/valo/07,832.99,yes,locked 2006.245.07:44:41.55/valo/08,852.99,yes,locked 2006.245.07:44:42.64/vb/01,04,usb,yes,33,58 2006.245.07:44:42.64/vb/02,04,usb,yes,34,59 2006.245.07:44:42.64/vb/03,04,usb,yes,31,37 2006.245.07:44:42.64/vb/04,04,usb,yes,36,33 2006.245.07:44:42.64/vb/05,03,usb,yes,39,44 2006.245.07:44:42.64/vb/06,03,usb,yes,39,43 2006.245.07:44:42.64/vb/07,04,usb,yes,34,36 2006.245.07:44:42.64/vb/08,03,usb,yes,39,43 2006.245.07:44:42.87/vblo/01,632.99,yes,locked 2006.245.07:44:42.87/vblo/02,640.99,yes,locked 2006.245.07:44:42.87/vblo/03,656.99,yes,locked 2006.245.07:44:42.87/vblo/04,712.99,yes,locked 2006.245.07:44:42.87/vblo/05,744.99,yes,locked 2006.245.07:44:42.87/vblo/06,752.99,yes,locked 2006.245.07:44:42.87/vblo/07,734.99,yes,locked 2006.245.07:44:42.87/vblo/08,744.99,yes,locked 2006.245.07:44:43.02/vabw/8 2006.245.07:44:43.17/vbbw/8 2006.245.07:44:43.27/xfe/off,on,13.7 2006.245.07:44:43.64/ifatt/23,28,28,28 2006.245.07:44:44.08/fmout-gps/S +4.42E-07 2006.245.07:44:44.12:!2006.245.07:45:40 2006.245.07:45:40.00:data_valid=off 2006.245.07:45:40.00:postob 2006.245.07:45:40.07/cable/+6.4087E-03 2006.245.07:45:40.07/wx/27.40,1004.5,68 2006.245.07:45:41.08/fmout-gps/S +4.40E-07 2006.245.07:45:41.08:scan_name=245-0746,k06245,60 2006.245.07:45:41.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.245.07:45:41.14#flagr#flagr/antenna,new-source 2006.245.07:45:42.14:checkk5 2006.245.07:45:42.69/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:45:43.32/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:45:43.75/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:45:44.16/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:45:44.63/chk_obsdata//k5ts1/T2450744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:45:45.06/chk_obsdata//k5ts2/T2450744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:45:45.90/chk_obsdata//k5ts3/T2450744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:45:46.74/chk_obsdata//k5ts4/T2450744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:45:47.55/k5log//k5ts1_log_newline 2006.245.07:45:48.34/k5log//k5ts2_log_newline 2006.245.07:45:49.10/k5log//k5ts3_log_newline 2006.245.07:45:50.12/k5log//k5ts4_log_newline 2006.245.07:45:50.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:45:50.14:4f8m12a=1 2006.245.07:45:50.15$4f8m12a/echo=on 2006.245.07:45:50.15$4f8m12a/pcalon 2006.245.07:45:50.15$pcalon/"no phase cal control is implemented here 2006.245.07:45:50.15$4f8m12a/"tpicd=stop 2006.245.07:45:50.15$4f8m12a/vc4f8 2006.245.07:45:50.15$vc4f8/valo=1,532.99 2006.245.07:45:50.15#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:45:50.15#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:45:50.15#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:50.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:50.15#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:50.15#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:50.15#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:45:50.15#ibcon#first serial, iclass 28, count 0 2006.245.07:45:50.15#ibcon#enter sib2, iclass 28, count 0 2006.245.07:45:50.15#ibcon#flushed, iclass 28, count 0 2006.245.07:45:50.15#ibcon#about to write, iclass 28, count 0 2006.245.07:45:50.15#ibcon#wrote, iclass 28, count 0 2006.245.07:45:50.15#ibcon#about to read 3, iclass 28, count 0 2006.245.07:45:50.19#ibcon#read 3, iclass 28, count 0 2006.245.07:45:50.19#ibcon#about to read 4, iclass 28, count 0 2006.245.07:45:50.19#ibcon#read 4, iclass 28, count 0 2006.245.07:45:50.19#ibcon#about to read 5, iclass 28, count 0 2006.245.07:45:50.19#ibcon#read 5, iclass 28, count 0 2006.245.07:45:50.19#ibcon#about to read 6, iclass 28, count 0 2006.245.07:45:50.19#ibcon#read 6, iclass 28, count 0 2006.245.07:45:50.19#ibcon#end of sib2, iclass 28, count 0 2006.245.07:45:50.19#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:45:50.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:45:50.19#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:45:50.19#ibcon#*before write, iclass 28, count 0 2006.245.07:45:50.19#ibcon#enter sib2, iclass 28, count 0 2006.245.07:45:50.19#ibcon#flushed, iclass 28, count 0 2006.245.07:45:50.19#ibcon#about to write, iclass 28, count 0 2006.245.07:45:50.19#ibcon#wrote, iclass 28, count 0 2006.245.07:45:50.19#ibcon#about to read 3, iclass 28, count 0 2006.245.07:45:50.24#ibcon#read 3, iclass 28, count 0 2006.245.07:45:50.24#ibcon#about to read 4, iclass 28, count 0 2006.245.07:45:50.24#ibcon#read 4, iclass 28, count 0 2006.245.07:45:50.24#ibcon#about to read 5, iclass 28, count 0 2006.245.07:45:50.24#ibcon#read 5, iclass 28, count 0 2006.245.07:45:50.24#ibcon#about to read 6, iclass 28, count 0 2006.245.07:45:50.24#ibcon#read 6, iclass 28, count 0 2006.245.07:45:50.24#ibcon#end of sib2, iclass 28, count 0 2006.245.07:45:50.24#ibcon#*after write, iclass 28, count 0 2006.245.07:45:50.24#ibcon#*before return 0, iclass 28, count 0 2006.245.07:45:50.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:50.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:50.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:45:50.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:45:50.24$vc4f8/va=1,8 2006.245.07:45:50.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.07:45:50.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.07:45:50.24#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:50.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:50.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:50.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:50.24#ibcon#enter wrdev, iclass 30, count 2 2006.245.07:45:50.24#ibcon#first serial, iclass 30, count 2 2006.245.07:45:50.24#ibcon#enter sib2, iclass 30, count 2 2006.245.07:45:50.24#ibcon#flushed, iclass 30, count 2 2006.245.07:45:50.24#ibcon#about to write, iclass 30, count 2 2006.245.07:45:50.24#ibcon#wrote, iclass 30, count 2 2006.245.07:45:50.24#ibcon#about to read 3, iclass 30, count 2 2006.245.07:45:50.26#ibcon#read 3, iclass 30, count 2 2006.245.07:45:50.26#ibcon#about to read 4, iclass 30, count 2 2006.245.07:45:50.26#ibcon#read 4, iclass 30, count 2 2006.245.07:45:50.26#ibcon#about to read 5, iclass 30, count 2 2006.245.07:45:50.26#ibcon#read 5, iclass 30, count 2 2006.245.07:45:50.26#ibcon#about to read 6, iclass 30, count 2 2006.245.07:45:50.26#ibcon#read 6, iclass 30, count 2 2006.245.07:45:50.26#ibcon#end of sib2, iclass 30, count 2 2006.245.07:45:50.26#ibcon#*mode == 0, iclass 30, count 2 2006.245.07:45:50.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.07:45:50.26#ibcon#[25=AT01-08\r\n] 2006.245.07:45:50.26#ibcon#*before write, iclass 30, count 2 2006.245.07:45:50.26#ibcon#enter sib2, iclass 30, count 2 2006.245.07:45:50.26#ibcon#flushed, iclass 30, count 2 2006.245.07:45:50.26#ibcon#about to write, iclass 30, count 2 2006.245.07:45:50.26#ibcon#wrote, iclass 30, count 2 2006.245.07:45:50.26#ibcon#about to read 3, iclass 30, count 2 2006.245.07:45:50.29#ibcon#read 3, iclass 30, count 2 2006.245.07:45:50.29#ibcon#about to read 4, iclass 30, count 2 2006.245.07:45:50.29#ibcon#read 4, iclass 30, count 2 2006.245.07:45:50.29#ibcon#about to read 5, iclass 30, count 2 2006.245.07:45:50.29#ibcon#read 5, iclass 30, count 2 2006.245.07:45:50.29#ibcon#about to read 6, iclass 30, count 2 2006.245.07:45:50.29#ibcon#read 6, iclass 30, count 2 2006.245.07:45:50.29#ibcon#end of sib2, iclass 30, count 2 2006.245.07:45:50.29#ibcon#*after write, iclass 30, count 2 2006.245.07:45:50.29#ibcon#*before return 0, iclass 30, count 2 2006.245.07:45:50.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:50.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:50.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.07:45:50.29#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:50.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:50.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:50.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:50.41#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:45:50.41#ibcon#first serial, iclass 30, count 0 2006.245.07:45:50.41#ibcon#enter sib2, iclass 30, count 0 2006.245.07:45:50.41#ibcon#flushed, iclass 30, count 0 2006.245.07:45:50.41#ibcon#about to write, iclass 30, count 0 2006.245.07:45:50.41#ibcon#wrote, iclass 30, count 0 2006.245.07:45:50.41#ibcon#about to read 3, iclass 30, count 0 2006.245.07:45:50.43#ibcon#read 3, iclass 30, count 0 2006.245.07:45:50.43#ibcon#about to read 4, iclass 30, count 0 2006.245.07:45:50.43#ibcon#read 4, iclass 30, count 0 2006.245.07:45:50.43#ibcon#about to read 5, iclass 30, count 0 2006.245.07:45:50.43#ibcon#read 5, iclass 30, count 0 2006.245.07:45:50.43#ibcon#about to read 6, iclass 30, count 0 2006.245.07:45:50.43#ibcon#read 6, iclass 30, count 0 2006.245.07:45:50.43#ibcon#end of sib2, iclass 30, count 0 2006.245.07:45:50.43#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:45:50.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:45:50.43#ibcon#[25=USB\r\n] 2006.245.07:45:50.43#ibcon#*before write, iclass 30, count 0 2006.245.07:45:50.43#ibcon#enter sib2, iclass 30, count 0 2006.245.07:45:50.43#ibcon#flushed, iclass 30, count 0 2006.245.07:45:50.43#ibcon#about to write, iclass 30, count 0 2006.245.07:45:50.43#ibcon#wrote, iclass 30, count 0 2006.245.07:45:50.43#ibcon#about to read 3, iclass 30, count 0 2006.245.07:45:50.46#ibcon#read 3, iclass 30, count 0 2006.245.07:45:50.46#ibcon#about to read 4, iclass 30, count 0 2006.245.07:45:50.46#ibcon#read 4, iclass 30, count 0 2006.245.07:45:50.46#ibcon#about to read 5, iclass 30, count 0 2006.245.07:45:50.46#ibcon#read 5, iclass 30, count 0 2006.245.07:45:50.46#ibcon#about to read 6, iclass 30, count 0 2006.245.07:45:50.46#ibcon#read 6, iclass 30, count 0 2006.245.07:45:50.46#ibcon#end of sib2, iclass 30, count 0 2006.245.07:45:50.46#ibcon#*after write, iclass 30, count 0 2006.245.07:45:50.46#ibcon#*before return 0, iclass 30, count 0 2006.245.07:45:50.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:50.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:50.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:45:50.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:45:50.46$vc4f8/valo=2,572.99 2006.245.07:45:50.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.07:45:50.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.07:45:50.46#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:50.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:50.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:50.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:50.46#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:45:50.46#ibcon#first serial, iclass 32, count 0 2006.245.07:45:50.46#ibcon#enter sib2, iclass 32, count 0 2006.245.07:45:50.46#ibcon#flushed, iclass 32, count 0 2006.245.07:45:50.46#ibcon#about to write, iclass 32, count 0 2006.245.07:45:50.46#ibcon#wrote, iclass 32, count 0 2006.245.07:45:50.46#ibcon#about to read 3, iclass 32, count 0 2006.245.07:45:50.48#ibcon#read 3, iclass 32, count 0 2006.245.07:45:50.48#ibcon#about to read 4, iclass 32, count 0 2006.245.07:45:50.48#ibcon#read 4, iclass 32, count 0 2006.245.07:45:50.48#ibcon#about to read 5, iclass 32, count 0 2006.245.07:45:50.48#ibcon#read 5, iclass 32, count 0 2006.245.07:45:50.48#ibcon#about to read 6, iclass 32, count 0 2006.245.07:45:50.48#ibcon#read 6, iclass 32, count 0 2006.245.07:45:50.48#ibcon#end of sib2, iclass 32, count 0 2006.245.07:45:50.48#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:45:50.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:45:50.48#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:45:50.48#ibcon#*before write, iclass 32, count 0 2006.245.07:45:50.48#ibcon#enter sib2, iclass 32, count 0 2006.245.07:45:50.48#ibcon#flushed, iclass 32, count 0 2006.245.07:45:50.48#ibcon#about to write, iclass 32, count 0 2006.245.07:45:50.48#ibcon#wrote, iclass 32, count 0 2006.245.07:45:50.48#ibcon#about to read 3, iclass 32, count 0 2006.245.07:45:50.52#ibcon#read 3, iclass 32, count 0 2006.245.07:45:50.52#ibcon#about to read 4, iclass 32, count 0 2006.245.07:45:50.52#ibcon#read 4, iclass 32, count 0 2006.245.07:45:50.52#ibcon#about to read 5, iclass 32, count 0 2006.245.07:45:50.52#ibcon#read 5, iclass 32, count 0 2006.245.07:45:50.52#ibcon#about to read 6, iclass 32, count 0 2006.245.07:45:50.52#ibcon#read 6, iclass 32, count 0 2006.245.07:45:50.52#ibcon#end of sib2, iclass 32, count 0 2006.245.07:45:50.52#ibcon#*after write, iclass 32, count 0 2006.245.07:45:50.52#ibcon#*before return 0, iclass 32, count 0 2006.245.07:45:50.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:50.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:50.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:45:50.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:45:50.52$vc4f8/va=2,7 2006.245.07:45:50.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.07:45:50.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.07:45:50.52#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:50.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:50.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:50.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:50.58#ibcon#enter wrdev, iclass 34, count 2 2006.245.07:45:50.58#ibcon#first serial, iclass 34, count 2 2006.245.07:45:50.58#ibcon#enter sib2, iclass 34, count 2 2006.245.07:45:50.58#ibcon#flushed, iclass 34, count 2 2006.245.07:45:50.58#ibcon#about to write, iclass 34, count 2 2006.245.07:45:50.58#ibcon#wrote, iclass 34, count 2 2006.245.07:45:50.58#ibcon#about to read 3, iclass 34, count 2 2006.245.07:45:50.60#ibcon#read 3, iclass 34, count 2 2006.245.07:45:50.60#ibcon#about to read 4, iclass 34, count 2 2006.245.07:45:50.60#ibcon#read 4, iclass 34, count 2 2006.245.07:45:50.60#ibcon#about to read 5, iclass 34, count 2 2006.245.07:45:50.60#ibcon#read 5, iclass 34, count 2 2006.245.07:45:50.60#ibcon#about to read 6, iclass 34, count 2 2006.245.07:45:50.60#ibcon#read 6, iclass 34, count 2 2006.245.07:45:50.60#ibcon#end of sib2, iclass 34, count 2 2006.245.07:45:50.60#ibcon#*mode == 0, iclass 34, count 2 2006.245.07:45:50.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.07:45:50.60#ibcon#[25=AT02-07\r\n] 2006.245.07:45:50.60#ibcon#*before write, iclass 34, count 2 2006.245.07:45:50.60#ibcon#enter sib2, iclass 34, count 2 2006.245.07:45:50.60#ibcon#flushed, iclass 34, count 2 2006.245.07:45:50.60#ibcon#about to write, iclass 34, count 2 2006.245.07:45:50.60#ibcon#wrote, iclass 34, count 2 2006.245.07:45:50.60#ibcon#about to read 3, iclass 34, count 2 2006.245.07:45:50.63#ibcon#read 3, iclass 34, count 2 2006.245.07:45:50.63#ibcon#about to read 4, iclass 34, count 2 2006.245.07:45:50.63#ibcon#read 4, iclass 34, count 2 2006.245.07:45:50.63#ibcon#about to read 5, iclass 34, count 2 2006.245.07:45:50.63#ibcon#read 5, iclass 34, count 2 2006.245.07:45:50.63#ibcon#about to read 6, iclass 34, count 2 2006.245.07:45:50.63#ibcon#read 6, iclass 34, count 2 2006.245.07:45:50.63#ibcon#end of sib2, iclass 34, count 2 2006.245.07:45:50.63#ibcon#*after write, iclass 34, count 2 2006.245.07:45:50.63#ibcon#*before return 0, iclass 34, count 2 2006.245.07:45:50.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:50.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:50.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.07:45:50.63#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:50.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:50.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:50.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:50.75#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:45:50.75#ibcon#first serial, iclass 34, count 0 2006.245.07:45:50.75#ibcon#enter sib2, iclass 34, count 0 2006.245.07:45:50.75#ibcon#flushed, iclass 34, count 0 2006.245.07:45:50.75#ibcon#about to write, iclass 34, count 0 2006.245.07:45:50.75#ibcon#wrote, iclass 34, count 0 2006.245.07:45:50.75#ibcon#about to read 3, iclass 34, count 0 2006.245.07:45:50.77#ibcon#read 3, iclass 34, count 0 2006.245.07:45:50.77#ibcon#about to read 4, iclass 34, count 0 2006.245.07:45:50.77#ibcon#read 4, iclass 34, count 0 2006.245.07:45:50.77#ibcon#about to read 5, iclass 34, count 0 2006.245.07:45:50.77#ibcon#read 5, iclass 34, count 0 2006.245.07:45:50.77#ibcon#about to read 6, iclass 34, count 0 2006.245.07:45:50.77#ibcon#read 6, iclass 34, count 0 2006.245.07:45:50.77#ibcon#end of sib2, iclass 34, count 0 2006.245.07:45:50.77#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:45:50.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:45:50.77#ibcon#[25=USB\r\n] 2006.245.07:45:50.77#ibcon#*before write, iclass 34, count 0 2006.245.07:45:50.77#ibcon#enter sib2, iclass 34, count 0 2006.245.07:45:50.77#ibcon#flushed, iclass 34, count 0 2006.245.07:45:50.77#ibcon#about to write, iclass 34, count 0 2006.245.07:45:50.77#ibcon#wrote, iclass 34, count 0 2006.245.07:45:50.77#ibcon#about to read 3, iclass 34, count 0 2006.245.07:45:50.80#ibcon#read 3, iclass 34, count 0 2006.245.07:45:50.80#ibcon#about to read 4, iclass 34, count 0 2006.245.07:45:50.80#ibcon#read 4, iclass 34, count 0 2006.245.07:45:50.80#ibcon#about to read 5, iclass 34, count 0 2006.245.07:45:50.80#ibcon#read 5, iclass 34, count 0 2006.245.07:45:50.80#ibcon#about to read 6, iclass 34, count 0 2006.245.07:45:50.80#ibcon#read 6, iclass 34, count 0 2006.245.07:45:50.80#ibcon#end of sib2, iclass 34, count 0 2006.245.07:45:50.80#ibcon#*after write, iclass 34, count 0 2006.245.07:45:50.80#ibcon#*before return 0, iclass 34, count 0 2006.245.07:45:50.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:50.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:50.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:45:50.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:45:50.80$vc4f8/valo=3,672.99 2006.245.07:45:50.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.07:45:50.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.07:45:50.80#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:50.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:50.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:50.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:50.80#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:45:50.80#ibcon#first serial, iclass 36, count 0 2006.245.07:45:50.80#ibcon#enter sib2, iclass 36, count 0 2006.245.07:45:50.80#ibcon#flushed, iclass 36, count 0 2006.245.07:45:50.80#ibcon#about to write, iclass 36, count 0 2006.245.07:45:50.80#ibcon#wrote, iclass 36, count 0 2006.245.07:45:50.80#ibcon#about to read 3, iclass 36, count 0 2006.245.07:45:50.82#ibcon#read 3, iclass 36, count 0 2006.245.07:45:50.82#ibcon#about to read 4, iclass 36, count 0 2006.245.07:45:50.82#ibcon#read 4, iclass 36, count 0 2006.245.07:45:50.82#ibcon#about to read 5, iclass 36, count 0 2006.245.07:45:50.82#ibcon#read 5, iclass 36, count 0 2006.245.07:45:50.82#ibcon#about to read 6, iclass 36, count 0 2006.245.07:45:50.82#ibcon#read 6, iclass 36, count 0 2006.245.07:45:50.82#ibcon#end of sib2, iclass 36, count 0 2006.245.07:45:50.82#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:45:50.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:45:50.82#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:45:50.82#ibcon#*before write, iclass 36, count 0 2006.245.07:45:50.82#ibcon#enter sib2, iclass 36, count 0 2006.245.07:45:50.82#ibcon#flushed, iclass 36, count 0 2006.245.07:45:50.82#ibcon#about to write, iclass 36, count 0 2006.245.07:45:50.82#ibcon#wrote, iclass 36, count 0 2006.245.07:45:50.82#ibcon#about to read 3, iclass 36, count 0 2006.245.07:45:50.86#ibcon#read 3, iclass 36, count 0 2006.245.07:45:50.86#ibcon#about to read 4, iclass 36, count 0 2006.245.07:45:50.86#ibcon#read 4, iclass 36, count 0 2006.245.07:45:50.86#ibcon#about to read 5, iclass 36, count 0 2006.245.07:45:50.86#ibcon#read 5, iclass 36, count 0 2006.245.07:45:50.86#ibcon#about to read 6, iclass 36, count 0 2006.245.07:45:50.86#ibcon#read 6, iclass 36, count 0 2006.245.07:45:50.86#ibcon#end of sib2, iclass 36, count 0 2006.245.07:45:50.86#ibcon#*after write, iclass 36, count 0 2006.245.07:45:50.86#ibcon#*before return 0, iclass 36, count 0 2006.245.07:45:50.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:50.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:50.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:45:50.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:45:50.86$vc4f8/va=3,6 2006.245.07:45:50.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.07:45:50.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.07:45:50.86#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:50.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:50.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:50.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:50.92#ibcon#enter wrdev, iclass 38, count 2 2006.245.07:45:50.92#ibcon#first serial, iclass 38, count 2 2006.245.07:45:50.92#ibcon#enter sib2, iclass 38, count 2 2006.245.07:45:50.92#ibcon#flushed, iclass 38, count 2 2006.245.07:45:50.92#ibcon#about to write, iclass 38, count 2 2006.245.07:45:50.92#ibcon#wrote, iclass 38, count 2 2006.245.07:45:50.92#ibcon#about to read 3, iclass 38, count 2 2006.245.07:45:50.94#ibcon#read 3, iclass 38, count 2 2006.245.07:45:50.94#ibcon#about to read 4, iclass 38, count 2 2006.245.07:45:50.94#ibcon#read 4, iclass 38, count 2 2006.245.07:45:50.94#ibcon#about to read 5, iclass 38, count 2 2006.245.07:45:50.94#ibcon#read 5, iclass 38, count 2 2006.245.07:45:50.94#ibcon#about to read 6, iclass 38, count 2 2006.245.07:45:50.94#ibcon#read 6, iclass 38, count 2 2006.245.07:45:50.94#ibcon#end of sib2, iclass 38, count 2 2006.245.07:45:50.94#ibcon#*mode == 0, iclass 38, count 2 2006.245.07:45:50.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.07:45:50.94#ibcon#[25=AT03-06\r\n] 2006.245.07:45:50.94#ibcon#*before write, iclass 38, count 2 2006.245.07:45:50.94#ibcon#enter sib2, iclass 38, count 2 2006.245.07:45:50.94#ibcon#flushed, iclass 38, count 2 2006.245.07:45:50.94#ibcon#about to write, iclass 38, count 2 2006.245.07:45:50.94#ibcon#wrote, iclass 38, count 2 2006.245.07:45:50.94#ibcon#about to read 3, iclass 38, count 2 2006.245.07:45:50.97#ibcon#read 3, iclass 38, count 2 2006.245.07:45:50.97#ibcon#about to read 4, iclass 38, count 2 2006.245.07:45:50.97#ibcon#read 4, iclass 38, count 2 2006.245.07:45:50.97#ibcon#about to read 5, iclass 38, count 2 2006.245.07:45:50.97#ibcon#read 5, iclass 38, count 2 2006.245.07:45:50.97#ibcon#about to read 6, iclass 38, count 2 2006.245.07:45:50.97#ibcon#read 6, iclass 38, count 2 2006.245.07:45:50.97#ibcon#end of sib2, iclass 38, count 2 2006.245.07:45:50.97#ibcon#*after write, iclass 38, count 2 2006.245.07:45:50.97#ibcon#*before return 0, iclass 38, count 2 2006.245.07:45:50.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:50.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:50.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.07:45:50.97#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:50.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:51.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:51.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:51.09#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:45:51.09#ibcon#first serial, iclass 38, count 0 2006.245.07:45:51.09#ibcon#enter sib2, iclass 38, count 0 2006.245.07:45:51.09#ibcon#flushed, iclass 38, count 0 2006.245.07:45:51.09#ibcon#about to write, iclass 38, count 0 2006.245.07:45:51.09#ibcon#wrote, iclass 38, count 0 2006.245.07:45:51.09#ibcon#about to read 3, iclass 38, count 0 2006.245.07:45:51.11#ibcon#read 3, iclass 38, count 0 2006.245.07:45:51.11#ibcon#about to read 4, iclass 38, count 0 2006.245.07:45:51.11#ibcon#read 4, iclass 38, count 0 2006.245.07:45:51.11#ibcon#about to read 5, iclass 38, count 0 2006.245.07:45:51.11#ibcon#read 5, iclass 38, count 0 2006.245.07:45:51.11#ibcon#about to read 6, iclass 38, count 0 2006.245.07:45:51.11#ibcon#read 6, iclass 38, count 0 2006.245.07:45:51.11#ibcon#end of sib2, iclass 38, count 0 2006.245.07:45:51.11#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:45:51.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:45:51.11#ibcon#[25=USB\r\n] 2006.245.07:45:51.11#ibcon#*before write, iclass 38, count 0 2006.245.07:45:51.11#ibcon#enter sib2, iclass 38, count 0 2006.245.07:45:51.11#ibcon#flushed, iclass 38, count 0 2006.245.07:45:51.11#ibcon#about to write, iclass 38, count 0 2006.245.07:45:51.11#ibcon#wrote, iclass 38, count 0 2006.245.07:45:51.11#ibcon#about to read 3, iclass 38, count 0 2006.245.07:45:51.14#ibcon#read 3, iclass 38, count 0 2006.245.07:45:51.14#ibcon#about to read 4, iclass 38, count 0 2006.245.07:45:51.14#ibcon#read 4, iclass 38, count 0 2006.245.07:45:51.14#ibcon#about to read 5, iclass 38, count 0 2006.245.07:45:51.14#ibcon#read 5, iclass 38, count 0 2006.245.07:45:51.14#ibcon#about to read 6, iclass 38, count 0 2006.245.07:45:51.14#ibcon#read 6, iclass 38, count 0 2006.245.07:45:51.14#ibcon#end of sib2, iclass 38, count 0 2006.245.07:45:51.14#ibcon#*after write, iclass 38, count 0 2006.245.07:45:51.14#ibcon#*before return 0, iclass 38, count 0 2006.245.07:45:51.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:51.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:51.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:45:51.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:45:51.14$vc4f8/valo=4,832.99 2006.245.07:45:51.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.07:45:51.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.07:45:51.14#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:51.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:51.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:51.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:51.14#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:45:51.14#ibcon#first serial, iclass 40, count 0 2006.245.07:45:51.14#ibcon#enter sib2, iclass 40, count 0 2006.245.07:45:51.14#ibcon#flushed, iclass 40, count 0 2006.245.07:45:51.14#ibcon#about to write, iclass 40, count 0 2006.245.07:45:51.14#ibcon#wrote, iclass 40, count 0 2006.245.07:45:51.14#ibcon#about to read 3, iclass 40, count 0 2006.245.07:45:51.16#ibcon#read 3, iclass 40, count 0 2006.245.07:45:51.16#ibcon#about to read 4, iclass 40, count 0 2006.245.07:45:51.16#ibcon#read 4, iclass 40, count 0 2006.245.07:45:51.16#ibcon#about to read 5, iclass 40, count 0 2006.245.07:45:51.16#ibcon#read 5, iclass 40, count 0 2006.245.07:45:51.16#ibcon#about to read 6, iclass 40, count 0 2006.245.07:45:51.16#ibcon#read 6, iclass 40, count 0 2006.245.07:45:51.16#ibcon#end of sib2, iclass 40, count 0 2006.245.07:45:51.16#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:45:51.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:45:51.16#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:45:51.16#ibcon#*before write, iclass 40, count 0 2006.245.07:45:51.16#ibcon#enter sib2, iclass 40, count 0 2006.245.07:45:51.16#ibcon#flushed, iclass 40, count 0 2006.245.07:45:51.16#ibcon#about to write, iclass 40, count 0 2006.245.07:45:51.16#ibcon#wrote, iclass 40, count 0 2006.245.07:45:51.16#ibcon#about to read 3, iclass 40, count 0 2006.245.07:45:51.20#ibcon#read 3, iclass 40, count 0 2006.245.07:45:51.20#ibcon#about to read 4, iclass 40, count 0 2006.245.07:45:51.20#ibcon#read 4, iclass 40, count 0 2006.245.07:45:51.20#ibcon#about to read 5, iclass 40, count 0 2006.245.07:45:51.20#ibcon#read 5, iclass 40, count 0 2006.245.07:45:51.20#ibcon#about to read 6, iclass 40, count 0 2006.245.07:45:51.20#ibcon#read 6, iclass 40, count 0 2006.245.07:45:51.20#ibcon#end of sib2, iclass 40, count 0 2006.245.07:45:51.20#ibcon#*after write, iclass 40, count 0 2006.245.07:45:51.20#ibcon#*before return 0, iclass 40, count 0 2006.245.07:45:51.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:51.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:51.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:45:51.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:45:51.20$vc4f8/va=4,7 2006.245.07:45:51.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.07:45:51.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.07:45:51.20#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:51.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:51.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:51.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:51.26#ibcon#enter wrdev, iclass 4, count 2 2006.245.07:45:51.26#ibcon#first serial, iclass 4, count 2 2006.245.07:45:51.26#ibcon#enter sib2, iclass 4, count 2 2006.245.07:45:51.26#ibcon#flushed, iclass 4, count 2 2006.245.07:45:51.26#ibcon#about to write, iclass 4, count 2 2006.245.07:45:51.26#ibcon#wrote, iclass 4, count 2 2006.245.07:45:51.26#ibcon#about to read 3, iclass 4, count 2 2006.245.07:45:51.28#ibcon#read 3, iclass 4, count 2 2006.245.07:45:51.28#ibcon#about to read 4, iclass 4, count 2 2006.245.07:45:51.28#ibcon#read 4, iclass 4, count 2 2006.245.07:45:51.28#ibcon#about to read 5, iclass 4, count 2 2006.245.07:45:51.28#ibcon#read 5, iclass 4, count 2 2006.245.07:45:51.28#ibcon#about to read 6, iclass 4, count 2 2006.245.07:45:51.28#ibcon#read 6, iclass 4, count 2 2006.245.07:45:51.28#ibcon#end of sib2, iclass 4, count 2 2006.245.07:45:51.28#ibcon#*mode == 0, iclass 4, count 2 2006.245.07:45:51.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.07:45:51.28#ibcon#[25=AT04-07\r\n] 2006.245.07:45:51.28#ibcon#*before write, iclass 4, count 2 2006.245.07:45:51.28#ibcon#enter sib2, iclass 4, count 2 2006.245.07:45:51.28#ibcon#flushed, iclass 4, count 2 2006.245.07:45:51.28#ibcon#about to write, iclass 4, count 2 2006.245.07:45:51.28#ibcon#wrote, iclass 4, count 2 2006.245.07:45:51.28#ibcon#about to read 3, iclass 4, count 2 2006.245.07:45:51.31#ibcon#read 3, iclass 4, count 2 2006.245.07:45:51.31#ibcon#about to read 4, iclass 4, count 2 2006.245.07:45:51.31#ibcon#read 4, iclass 4, count 2 2006.245.07:45:51.31#ibcon#about to read 5, iclass 4, count 2 2006.245.07:45:51.31#ibcon#read 5, iclass 4, count 2 2006.245.07:45:51.31#ibcon#about to read 6, iclass 4, count 2 2006.245.07:45:51.31#ibcon#read 6, iclass 4, count 2 2006.245.07:45:51.31#ibcon#end of sib2, iclass 4, count 2 2006.245.07:45:51.31#ibcon#*after write, iclass 4, count 2 2006.245.07:45:51.31#ibcon#*before return 0, iclass 4, count 2 2006.245.07:45:51.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:51.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:51.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.07:45:51.31#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:51.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:51.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:51.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:51.43#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:45:51.43#ibcon#first serial, iclass 4, count 0 2006.245.07:45:51.43#ibcon#enter sib2, iclass 4, count 0 2006.245.07:45:51.43#ibcon#flushed, iclass 4, count 0 2006.245.07:45:51.43#ibcon#about to write, iclass 4, count 0 2006.245.07:45:51.43#ibcon#wrote, iclass 4, count 0 2006.245.07:45:51.43#ibcon#about to read 3, iclass 4, count 0 2006.245.07:45:51.45#ibcon#read 3, iclass 4, count 0 2006.245.07:45:51.45#ibcon#about to read 4, iclass 4, count 0 2006.245.07:45:51.45#ibcon#read 4, iclass 4, count 0 2006.245.07:45:51.45#ibcon#about to read 5, iclass 4, count 0 2006.245.07:45:51.45#ibcon#read 5, iclass 4, count 0 2006.245.07:45:51.45#ibcon#about to read 6, iclass 4, count 0 2006.245.07:45:51.45#ibcon#read 6, iclass 4, count 0 2006.245.07:45:51.45#ibcon#end of sib2, iclass 4, count 0 2006.245.07:45:51.45#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:45:51.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:45:51.45#ibcon#[25=USB\r\n] 2006.245.07:45:51.45#ibcon#*before write, iclass 4, count 0 2006.245.07:45:51.45#ibcon#enter sib2, iclass 4, count 0 2006.245.07:45:51.45#ibcon#flushed, iclass 4, count 0 2006.245.07:45:51.45#ibcon#about to write, iclass 4, count 0 2006.245.07:45:51.45#ibcon#wrote, iclass 4, count 0 2006.245.07:45:51.45#ibcon#about to read 3, iclass 4, count 0 2006.245.07:45:51.48#ibcon#read 3, iclass 4, count 0 2006.245.07:45:51.48#ibcon#about to read 4, iclass 4, count 0 2006.245.07:45:51.48#ibcon#read 4, iclass 4, count 0 2006.245.07:45:51.48#ibcon#about to read 5, iclass 4, count 0 2006.245.07:45:51.48#ibcon#read 5, iclass 4, count 0 2006.245.07:45:51.48#ibcon#about to read 6, iclass 4, count 0 2006.245.07:45:51.48#ibcon#read 6, iclass 4, count 0 2006.245.07:45:51.48#ibcon#end of sib2, iclass 4, count 0 2006.245.07:45:51.48#ibcon#*after write, iclass 4, count 0 2006.245.07:45:51.48#ibcon#*before return 0, iclass 4, count 0 2006.245.07:45:51.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:51.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:51.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:45:51.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:45:51.48$vc4f8/valo=5,652.99 2006.245.07:45:51.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.07:45:51.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.07:45:51.48#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:51.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:51.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:51.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:51.48#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:45:51.48#ibcon#first serial, iclass 6, count 0 2006.245.07:45:51.48#ibcon#enter sib2, iclass 6, count 0 2006.245.07:45:51.48#ibcon#flushed, iclass 6, count 0 2006.245.07:45:51.48#ibcon#about to write, iclass 6, count 0 2006.245.07:45:51.48#ibcon#wrote, iclass 6, count 0 2006.245.07:45:51.48#ibcon#about to read 3, iclass 6, count 0 2006.245.07:45:51.50#ibcon#read 3, iclass 6, count 0 2006.245.07:45:51.50#ibcon#about to read 4, iclass 6, count 0 2006.245.07:45:51.50#ibcon#read 4, iclass 6, count 0 2006.245.07:45:51.50#ibcon#about to read 5, iclass 6, count 0 2006.245.07:45:51.50#ibcon#read 5, iclass 6, count 0 2006.245.07:45:51.50#ibcon#about to read 6, iclass 6, count 0 2006.245.07:45:51.50#ibcon#read 6, iclass 6, count 0 2006.245.07:45:51.50#ibcon#end of sib2, iclass 6, count 0 2006.245.07:45:51.50#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:45:51.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:45:51.50#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:45:51.50#ibcon#*before write, iclass 6, count 0 2006.245.07:45:51.50#ibcon#enter sib2, iclass 6, count 0 2006.245.07:45:51.50#ibcon#flushed, iclass 6, count 0 2006.245.07:45:51.50#ibcon#about to write, iclass 6, count 0 2006.245.07:45:51.50#ibcon#wrote, iclass 6, count 0 2006.245.07:45:51.50#ibcon#about to read 3, iclass 6, count 0 2006.245.07:45:51.54#ibcon#read 3, iclass 6, count 0 2006.245.07:45:51.54#ibcon#about to read 4, iclass 6, count 0 2006.245.07:45:51.54#ibcon#read 4, iclass 6, count 0 2006.245.07:45:51.54#ibcon#about to read 5, iclass 6, count 0 2006.245.07:45:51.54#ibcon#read 5, iclass 6, count 0 2006.245.07:45:51.54#ibcon#about to read 6, iclass 6, count 0 2006.245.07:45:51.54#ibcon#read 6, iclass 6, count 0 2006.245.07:45:51.54#ibcon#end of sib2, iclass 6, count 0 2006.245.07:45:51.54#ibcon#*after write, iclass 6, count 0 2006.245.07:45:51.54#ibcon#*before return 0, iclass 6, count 0 2006.245.07:45:51.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:51.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:51.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:45:51.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:45:51.54$vc4f8/va=5,7 2006.245.07:45:51.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.07:45:51.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.07:45:51.54#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:51.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:51.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:51.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:51.60#ibcon#enter wrdev, iclass 10, count 2 2006.245.07:45:51.60#ibcon#first serial, iclass 10, count 2 2006.245.07:45:51.60#ibcon#enter sib2, iclass 10, count 2 2006.245.07:45:51.60#ibcon#flushed, iclass 10, count 2 2006.245.07:45:51.60#ibcon#about to write, iclass 10, count 2 2006.245.07:45:51.60#ibcon#wrote, iclass 10, count 2 2006.245.07:45:51.60#ibcon#about to read 3, iclass 10, count 2 2006.245.07:45:51.62#ibcon#read 3, iclass 10, count 2 2006.245.07:45:51.62#ibcon#about to read 4, iclass 10, count 2 2006.245.07:45:51.62#ibcon#read 4, iclass 10, count 2 2006.245.07:45:51.62#ibcon#about to read 5, iclass 10, count 2 2006.245.07:45:51.62#ibcon#read 5, iclass 10, count 2 2006.245.07:45:51.62#ibcon#about to read 6, iclass 10, count 2 2006.245.07:45:51.62#ibcon#read 6, iclass 10, count 2 2006.245.07:45:51.62#ibcon#end of sib2, iclass 10, count 2 2006.245.07:45:51.62#ibcon#*mode == 0, iclass 10, count 2 2006.245.07:45:51.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.07:45:51.62#ibcon#[25=AT05-07\r\n] 2006.245.07:45:51.62#ibcon#*before write, iclass 10, count 2 2006.245.07:45:51.62#ibcon#enter sib2, iclass 10, count 2 2006.245.07:45:51.62#ibcon#flushed, iclass 10, count 2 2006.245.07:45:51.62#ibcon#about to write, iclass 10, count 2 2006.245.07:45:51.62#ibcon#wrote, iclass 10, count 2 2006.245.07:45:51.62#ibcon#about to read 3, iclass 10, count 2 2006.245.07:45:51.65#ibcon#read 3, iclass 10, count 2 2006.245.07:45:51.65#ibcon#about to read 4, iclass 10, count 2 2006.245.07:45:51.65#ibcon#read 4, iclass 10, count 2 2006.245.07:45:51.65#ibcon#about to read 5, iclass 10, count 2 2006.245.07:45:51.65#ibcon#read 5, iclass 10, count 2 2006.245.07:45:51.65#ibcon#about to read 6, iclass 10, count 2 2006.245.07:45:51.65#ibcon#read 6, iclass 10, count 2 2006.245.07:45:51.65#ibcon#end of sib2, iclass 10, count 2 2006.245.07:45:51.65#ibcon#*after write, iclass 10, count 2 2006.245.07:45:51.65#ibcon#*before return 0, iclass 10, count 2 2006.245.07:45:51.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:51.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:51.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.07:45:51.65#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:51.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:51.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:51.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:51.77#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:45:51.77#ibcon#first serial, iclass 10, count 0 2006.245.07:45:51.77#ibcon#enter sib2, iclass 10, count 0 2006.245.07:45:51.77#ibcon#flushed, iclass 10, count 0 2006.245.07:45:51.77#ibcon#about to write, iclass 10, count 0 2006.245.07:45:51.77#ibcon#wrote, iclass 10, count 0 2006.245.07:45:51.77#ibcon#about to read 3, iclass 10, count 0 2006.245.07:45:51.79#ibcon#read 3, iclass 10, count 0 2006.245.07:45:51.79#ibcon#about to read 4, iclass 10, count 0 2006.245.07:45:51.79#ibcon#read 4, iclass 10, count 0 2006.245.07:45:51.79#ibcon#about to read 5, iclass 10, count 0 2006.245.07:45:51.79#ibcon#read 5, iclass 10, count 0 2006.245.07:45:51.79#ibcon#about to read 6, iclass 10, count 0 2006.245.07:45:51.79#ibcon#read 6, iclass 10, count 0 2006.245.07:45:51.79#ibcon#end of sib2, iclass 10, count 0 2006.245.07:45:51.79#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:45:51.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:45:51.79#ibcon#[25=USB\r\n] 2006.245.07:45:51.79#ibcon#*before write, iclass 10, count 0 2006.245.07:45:51.79#ibcon#enter sib2, iclass 10, count 0 2006.245.07:45:51.79#ibcon#flushed, iclass 10, count 0 2006.245.07:45:51.79#ibcon#about to write, iclass 10, count 0 2006.245.07:45:51.79#ibcon#wrote, iclass 10, count 0 2006.245.07:45:51.79#ibcon#about to read 3, iclass 10, count 0 2006.245.07:45:51.82#ibcon#read 3, iclass 10, count 0 2006.245.07:45:51.82#ibcon#about to read 4, iclass 10, count 0 2006.245.07:45:51.82#ibcon#read 4, iclass 10, count 0 2006.245.07:45:51.82#ibcon#about to read 5, iclass 10, count 0 2006.245.07:45:51.82#ibcon#read 5, iclass 10, count 0 2006.245.07:45:51.82#ibcon#about to read 6, iclass 10, count 0 2006.245.07:45:51.82#ibcon#read 6, iclass 10, count 0 2006.245.07:45:51.82#ibcon#end of sib2, iclass 10, count 0 2006.245.07:45:51.82#ibcon#*after write, iclass 10, count 0 2006.245.07:45:51.82#ibcon#*before return 0, iclass 10, count 0 2006.245.07:45:51.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:51.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:51.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:45:51.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:45:51.82$vc4f8/valo=6,772.99 2006.245.07:45:51.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.07:45:51.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.07:45:51.82#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:51.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:51.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:51.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:51.82#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:45:51.82#ibcon#first serial, iclass 12, count 0 2006.245.07:45:51.82#ibcon#enter sib2, iclass 12, count 0 2006.245.07:45:51.82#ibcon#flushed, iclass 12, count 0 2006.245.07:45:51.82#ibcon#about to write, iclass 12, count 0 2006.245.07:45:51.82#ibcon#wrote, iclass 12, count 0 2006.245.07:45:51.82#ibcon#about to read 3, iclass 12, count 0 2006.245.07:45:51.84#ibcon#read 3, iclass 12, count 0 2006.245.07:45:51.84#ibcon#about to read 4, iclass 12, count 0 2006.245.07:45:51.84#ibcon#read 4, iclass 12, count 0 2006.245.07:45:51.84#ibcon#about to read 5, iclass 12, count 0 2006.245.07:45:51.84#ibcon#read 5, iclass 12, count 0 2006.245.07:45:51.84#ibcon#about to read 6, iclass 12, count 0 2006.245.07:45:51.84#ibcon#read 6, iclass 12, count 0 2006.245.07:45:51.84#ibcon#end of sib2, iclass 12, count 0 2006.245.07:45:51.84#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:45:51.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:45:51.84#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:45:51.84#ibcon#*before write, iclass 12, count 0 2006.245.07:45:51.84#ibcon#enter sib2, iclass 12, count 0 2006.245.07:45:51.84#ibcon#flushed, iclass 12, count 0 2006.245.07:45:51.84#ibcon#about to write, iclass 12, count 0 2006.245.07:45:51.84#ibcon#wrote, iclass 12, count 0 2006.245.07:45:51.84#ibcon#about to read 3, iclass 12, count 0 2006.245.07:45:51.88#ibcon#read 3, iclass 12, count 0 2006.245.07:45:51.88#ibcon#about to read 4, iclass 12, count 0 2006.245.07:45:51.88#ibcon#read 4, iclass 12, count 0 2006.245.07:45:51.88#ibcon#about to read 5, iclass 12, count 0 2006.245.07:45:51.88#ibcon#read 5, iclass 12, count 0 2006.245.07:45:51.88#ibcon#about to read 6, iclass 12, count 0 2006.245.07:45:51.88#ibcon#read 6, iclass 12, count 0 2006.245.07:45:51.88#ibcon#end of sib2, iclass 12, count 0 2006.245.07:45:51.88#ibcon#*after write, iclass 12, count 0 2006.245.07:45:51.88#ibcon#*before return 0, iclass 12, count 0 2006.245.07:45:51.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:51.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:51.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:45:51.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:45:51.88$vc4f8/va=6,7 2006.245.07:45:51.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.07:45:51.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.07:45:51.88#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:51.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:45:51.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:45:51.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:45:51.94#ibcon#enter wrdev, iclass 14, count 2 2006.245.07:45:51.94#ibcon#first serial, iclass 14, count 2 2006.245.07:45:51.94#ibcon#enter sib2, iclass 14, count 2 2006.245.07:45:51.94#ibcon#flushed, iclass 14, count 2 2006.245.07:45:51.94#ibcon#about to write, iclass 14, count 2 2006.245.07:45:51.94#ibcon#wrote, iclass 14, count 2 2006.245.07:45:51.94#ibcon#about to read 3, iclass 14, count 2 2006.245.07:45:51.96#ibcon#read 3, iclass 14, count 2 2006.245.07:45:51.96#ibcon#about to read 4, iclass 14, count 2 2006.245.07:45:51.96#ibcon#read 4, iclass 14, count 2 2006.245.07:45:51.96#ibcon#about to read 5, iclass 14, count 2 2006.245.07:45:51.96#ibcon#read 5, iclass 14, count 2 2006.245.07:45:51.96#ibcon#about to read 6, iclass 14, count 2 2006.245.07:45:51.96#ibcon#read 6, iclass 14, count 2 2006.245.07:45:51.96#ibcon#end of sib2, iclass 14, count 2 2006.245.07:45:51.96#ibcon#*mode == 0, iclass 14, count 2 2006.245.07:45:51.96#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.07:45:51.96#ibcon#[25=AT06-07\r\n] 2006.245.07:45:51.96#ibcon#*before write, iclass 14, count 2 2006.245.07:45:51.96#ibcon#enter sib2, iclass 14, count 2 2006.245.07:45:51.96#ibcon#flushed, iclass 14, count 2 2006.245.07:45:51.96#ibcon#about to write, iclass 14, count 2 2006.245.07:45:51.96#ibcon#wrote, iclass 14, count 2 2006.245.07:45:51.96#ibcon#about to read 3, iclass 14, count 2 2006.245.07:45:51.99#ibcon#read 3, iclass 14, count 2 2006.245.07:45:51.99#ibcon#about to read 4, iclass 14, count 2 2006.245.07:45:51.99#ibcon#read 4, iclass 14, count 2 2006.245.07:45:51.99#ibcon#about to read 5, iclass 14, count 2 2006.245.07:45:51.99#ibcon#read 5, iclass 14, count 2 2006.245.07:45:51.99#ibcon#about to read 6, iclass 14, count 2 2006.245.07:45:51.99#ibcon#read 6, iclass 14, count 2 2006.245.07:45:51.99#ibcon#end of sib2, iclass 14, count 2 2006.245.07:45:51.99#ibcon#*after write, iclass 14, count 2 2006.245.07:45:51.99#ibcon#*before return 0, iclass 14, count 2 2006.245.07:45:51.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:45:51.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:45:51.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.07:45:51.99#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:51.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:45:52.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:45:52.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:45:52.11#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:45:52.11#ibcon#first serial, iclass 14, count 0 2006.245.07:45:52.11#ibcon#enter sib2, iclass 14, count 0 2006.245.07:45:52.11#ibcon#flushed, iclass 14, count 0 2006.245.07:45:52.11#ibcon#about to write, iclass 14, count 0 2006.245.07:45:52.11#ibcon#wrote, iclass 14, count 0 2006.245.07:45:52.11#ibcon#about to read 3, iclass 14, count 0 2006.245.07:45:52.13#ibcon#read 3, iclass 14, count 0 2006.245.07:45:52.13#ibcon#about to read 4, iclass 14, count 0 2006.245.07:45:52.13#ibcon#read 4, iclass 14, count 0 2006.245.07:45:52.13#ibcon#about to read 5, iclass 14, count 0 2006.245.07:45:52.13#ibcon#read 5, iclass 14, count 0 2006.245.07:45:52.13#ibcon#about to read 6, iclass 14, count 0 2006.245.07:45:52.13#ibcon#read 6, iclass 14, count 0 2006.245.07:45:52.13#ibcon#end of sib2, iclass 14, count 0 2006.245.07:45:52.13#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:45:52.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:45:52.13#ibcon#[25=USB\r\n] 2006.245.07:45:52.13#ibcon#*before write, iclass 14, count 0 2006.245.07:45:52.13#ibcon#enter sib2, iclass 14, count 0 2006.245.07:45:52.13#ibcon#flushed, iclass 14, count 0 2006.245.07:45:52.13#ibcon#about to write, iclass 14, count 0 2006.245.07:45:52.13#ibcon#wrote, iclass 14, count 0 2006.245.07:45:52.13#ibcon#about to read 3, iclass 14, count 0 2006.245.07:45:52.16#ibcon#read 3, iclass 14, count 0 2006.245.07:45:52.16#ibcon#about to read 4, iclass 14, count 0 2006.245.07:45:52.16#ibcon#read 4, iclass 14, count 0 2006.245.07:45:52.16#ibcon#about to read 5, iclass 14, count 0 2006.245.07:45:52.16#ibcon#read 5, iclass 14, count 0 2006.245.07:45:52.16#ibcon#about to read 6, iclass 14, count 0 2006.245.07:45:52.16#ibcon#read 6, iclass 14, count 0 2006.245.07:45:52.16#ibcon#end of sib2, iclass 14, count 0 2006.245.07:45:52.16#ibcon#*after write, iclass 14, count 0 2006.245.07:45:52.16#ibcon#*before return 0, iclass 14, count 0 2006.245.07:45:52.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:45:52.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:45:52.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:45:52.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:45:52.16$vc4f8/valo=7,832.99 2006.245.07:45:52.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:45:52.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:45:52.16#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:52.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:45:52.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:45:52.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:45:52.16#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:45:52.16#ibcon#first serial, iclass 16, count 0 2006.245.07:45:52.16#ibcon#enter sib2, iclass 16, count 0 2006.245.07:45:52.16#ibcon#flushed, iclass 16, count 0 2006.245.07:45:52.16#ibcon#about to write, iclass 16, count 0 2006.245.07:45:52.16#ibcon#wrote, iclass 16, count 0 2006.245.07:45:52.16#ibcon#about to read 3, iclass 16, count 0 2006.245.07:45:52.18#ibcon#read 3, iclass 16, count 0 2006.245.07:45:52.18#ibcon#about to read 4, iclass 16, count 0 2006.245.07:45:52.18#ibcon#read 4, iclass 16, count 0 2006.245.07:45:52.18#ibcon#about to read 5, iclass 16, count 0 2006.245.07:45:52.18#ibcon#read 5, iclass 16, count 0 2006.245.07:45:52.18#ibcon#about to read 6, iclass 16, count 0 2006.245.07:45:52.18#ibcon#read 6, iclass 16, count 0 2006.245.07:45:52.18#ibcon#end of sib2, iclass 16, count 0 2006.245.07:45:52.18#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:45:52.18#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:45:52.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:45:52.18#ibcon#*before write, iclass 16, count 0 2006.245.07:45:52.18#ibcon#enter sib2, iclass 16, count 0 2006.245.07:45:52.18#ibcon#flushed, iclass 16, count 0 2006.245.07:45:52.18#ibcon#about to write, iclass 16, count 0 2006.245.07:45:52.18#ibcon#wrote, iclass 16, count 0 2006.245.07:45:52.18#ibcon#about to read 3, iclass 16, count 0 2006.245.07:45:52.22#ibcon#read 3, iclass 16, count 0 2006.245.07:45:52.22#ibcon#about to read 4, iclass 16, count 0 2006.245.07:45:52.22#ibcon#read 4, iclass 16, count 0 2006.245.07:45:52.22#ibcon#about to read 5, iclass 16, count 0 2006.245.07:45:52.22#ibcon#read 5, iclass 16, count 0 2006.245.07:45:52.22#ibcon#about to read 6, iclass 16, count 0 2006.245.07:45:52.22#ibcon#read 6, iclass 16, count 0 2006.245.07:45:52.22#ibcon#end of sib2, iclass 16, count 0 2006.245.07:45:52.22#ibcon#*after write, iclass 16, count 0 2006.245.07:45:52.22#ibcon#*before return 0, iclass 16, count 0 2006.245.07:45:52.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:45:52.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:45:52.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:45:52.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:45:52.22$vc4f8/va=7,7 2006.245.07:45:52.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.07:45:52.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.07:45:52.22#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:52.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:45:52.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:45:52.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:45:52.28#ibcon#enter wrdev, iclass 18, count 2 2006.245.07:45:52.28#ibcon#first serial, iclass 18, count 2 2006.245.07:45:52.28#ibcon#enter sib2, iclass 18, count 2 2006.245.07:45:52.28#ibcon#flushed, iclass 18, count 2 2006.245.07:45:52.28#ibcon#about to write, iclass 18, count 2 2006.245.07:45:52.28#ibcon#wrote, iclass 18, count 2 2006.245.07:45:52.28#ibcon#about to read 3, iclass 18, count 2 2006.245.07:45:52.30#ibcon#read 3, iclass 18, count 2 2006.245.07:45:52.30#ibcon#about to read 4, iclass 18, count 2 2006.245.07:45:52.30#ibcon#read 4, iclass 18, count 2 2006.245.07:45:52.30#ibcon#about to read 5, iclass 18, count 2 2006.245.07:45:52.30#ibcon#read 5, iclass 18, count 2 2006.245.07:45:52.30#ibcon#about to read 6, iclass 18, count 2 2006.245.07:45:52.30#ibcon#read 6, iclass 18, count 2 2006.245.07:45:52.30#ibcon#end of sib2, iclass 18, count 2 2006.245.07:45:52.30#ibcon#*mode == 0, iclass 18, count 2 2006.245.07:45:52.30#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.07:45:52.30#ibcon#[25=AT07-07\r\n] 2006.245.07:45:52.30#ibcon#*before write, iclass 18, count 2 2006.245.07:45:52.30#ibcon#enter sib2, iclass 18, count 2 2006.245.07:45:52.30#ibcon#flushed, iclass 18, count 2 2006.245.07:45:52.30#ibcon#about to write, iclass 18, count 2 2006.245.07:45:52.30#ibcon#wrote, iclass 18, count 2 2006.245.07:45:52.30#ibcon#about to read 3, iclass 18, count 2 2006.245.07:45:52.33#ibcon#read 3, iclass 18, count 2 2006.245.07:45:52.33#ibcon#about to read 4, iclass 18, count 2 2006.245.07:45:52.33#ibcon#read 4, iclass 18, count 2 2006.245.07:45:52.33#ibcon#about to read 5, iclass 18, count 2 2006.245.07:45:52.33#ibcon#read 5, iclass 18, count 2 2006.245.07:45:52.33#ibcon#about to read 6, iclass 18, count 2 2006.245.07:45:52.33#ibcon#read 6, iclass 18, count 2 2006.245.07:45:52.33#ibcon#end of sib2, iclass 18, count 2 2006.245.07:45:52.33#ibcon#*after write, iclass 18, count 2 2006.245.07:45:52.33#ibcon#*before return 0, iclass 18, count 2 2006.245.07:45:52.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:45:52.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:45:52.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.07:45:52.33#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:52.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:45:52.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:45:52.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:45:52.45#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:45:52.45#ibcon#first serial, iclass 18, count 0 2006.245.07:45:52.45#ibcon#enter sib2, iclass 18, count 0 2006.245.07:45:52.45#ibcon#flushed, iclass 18, count 0 2006.245.07:45:52.45#ibcon#about to write, iclass 18, count 0 2006.245.07:45:52.45#ibcon#wrote, iclass 18, count 0 2006.245.07:45:52.45#ibcon#about to read 3, iclass 18, count 0 2006.245.07:45:52.47#ibcon#read 3, iclass 18, count 0 2006.245.07:45:52.47#ibcon#about to read 4, iclass 18, count 0 2006.245.07:45:52.47#ibcon#read 4, iclass 18, count 0 2006.245.07:45:52.47#ibcon#about to read 5, iclass 18, count 0 2006.245.07:45:52.47#ibcon#read 5, iclass 18, count 0 2006.245.07:45:52.47#ibcon#about to read 6, iclass 18, count 0 2006.245.07:45:52.47#ibcon#read 6, iclass 18, count 0 2006.245.07:45:52.47#ibcon#end of sib2, iclass 18, count 0 2006.245.07:45:52.47#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:45:52.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:45:52.47#ibcon#[25=USB\r\n] 2006.245.07:45:52.47#ibcon#*before write, iclass 18, count 0 2006.245.07:45:52.47#ibcon#enter sib2, iclass 18, count 0 2006.245.07:45:52.47#ibcon#flushed, iclass 18, count 0 2006.245.07:45:52.47#ibcon#about to write, iclass 18, count 0 2006.245.07:45:52.47#ibcon#wrote, iclass 18, count 0 2006.245.07:45:52.47#ibcon#about to read 3, iclass 18, count 0 2006.245.07:45:52.50#ibcon#read 3, iclass 18, count 0 2006.245.07:45:52.50#ibcon#about to read 4, iclass 18, count 0 2006.245.07:45:52.50#ibcon#read 4, iclass 18, count 0 2006.245.07:45:52.50#ibcon#about to read 5, iclass 18, count 0 2006.245.07:45:52.50#ibcon#read 5, iclass 18, count 0 2006.245.07:45:52.50#ibcon#about to read 6, iclass 18, count 0 2006.245.07:45:52.50#ibcon#read 6, iclass 18, count 0 2006.245.07:45:52.50#ibcon#end of sib2, iclass 18, count 0 2006.245.07:45:52.50#ibcon#*after write, iclass 18, count 0 2006.245.07:45:52.50#ibcon#*before return 0, iclass 18, count 0 2006.245.07:45:52.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:45:52.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:45:52.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:45:52.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:45:52.50$vc4f8/valo=8,852.99 2006.245.07:45:52.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.07:45:52.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.07:45:52.50#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:52.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:45:52.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:45:52.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:45:52.50#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:45:52.50#ibcon#first serial, iclass 20, count 0 2006.245.07:45:52.50#ibcon#enter sib2, iclass 20, count 0 2006.245.07:45:52.50#ibcon#flushed, iclass 20, count 0 2006.245.07:45:52.50#ibcon#about to write, iclass 20, count 0 2006.245.07:45:52.50#ibcon#wrote, iclass 20, count 0 2006.245.07:45:52.50#ibcon#about to read 3, iclass 20, count 0 2006.245.07:45:52.52#ibcon#read 3, iclass 20, count 0 2006.245.07:45:52.52#ibcon#about to read 4, iclass 20, count 0 2006.245.07:45:52.52#ibcon#read 4, iclass 20, count 0 2006.245.07:45:52.52#ibcon#about to read 5, iclass 20, count 0 2006.245.07:45:52.52#ibcon#read 5, iclass 20, count 0 2006.245.07:45:52.52#ibcon#about to read 6, iclass 20, count 0 2006.245.07:45:52.52#ibcon#read 6, iclass 20, count 0 2006.245.07:45:52.52#ibcon#end of sib2, iclass 20, count 0 2006.245.07:45:52.52#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:45:52.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:45:52.52#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:45:52.52#ibcon#*before write, iclass 20, count 0 2006.245.07:45:52.52#ibcon#enter sib2, iclass 20, count 0 2006.245.07:45:52.52#ibcon#flushed, iclass 20, count 0 2006.245.07:45:52.52#ibcon#about to write, iclass 20, count 0 2006.245.07:45:52.52#ibcon#wrote, iclass 20, count 0 2006.245.07:45:52.52#ibcon#about to read 3, iclass 20, count 0 2006.245.07:45:52.56#ibcon#read 3, iclass 20, count 0 2006.245.07:45:52.56#ibcon#about to read 4, iclass 20, count 0 2006.245.07:45:52.56#ibcon#read 4, iclass 20, count 0 2006.245.07:45:52.56#ibcon#about to read 5, iclass 20, count 0 2006.245.07:45:52.56#ibcon#read 5, iclass 20, count 0 2006.245.07:45:52.56#ibcon#about to read 6, iclass 20, count 0 2006.245.07:45:52.56#ibcon#read 6, iclass 20, count 0 2006.245.07:45:52.56#ibcon#end of sib2, iclass 20, count 0 2006.245.07:45:52.56#ibcon#*after write, iclass 20, count 0 2006.245.07:45:52.56#ibcon#*before return 0, iclass 20, count 0 2006.245.07:45:52.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:45:52.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:45:52.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:45:52.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:45:52.56$vc4f8/va=8,8 2006.245.07:45:52.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.07:45:52.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.07:45:52.56#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:52.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:45:52.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:45:52.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:45:52.62#ibcon#enter wrdev, iclass 22, count 2 2006.245.07:45:52.62#ibcon#first serial, iclass 22, count 2 2006.245.07:45:52.62#ibcon#enter sib2, iclass 22, count 2 2006.245.07:45:52.62#ibcon#flushed, iclass 22, count 2 2006.245.07:45:52.62#ibcon#about to write, iclass 22, count 2 2006.245.07:45:52.62#ibcon#wrote, iclass 22, count 2 2006.245.07:45:52.62#ibcon#about to read 3, iclass 22, count 2 2006.245.07:45:52.64#ibcon#read 3, iclass 22, count 2 2006.245.07:45:52.64#ibcon#about to read 4, iclass 22, count 2 2006.245.07:45:52.64#ibcon#read 4, iclass 22, count 2 2006.245.07:45:52.64#ibcon#about to read 5, iclass 22, count 2 2006.245.07:45:52.64#ibcon#read 5, iclass 22, count 2 2006.245.07:45:52.64#ibcon#about to read 6, iclass 22, count 2 2006.245.07:45:52.64#ibcon#read 6, iclass 22, count 2 2006.245.07:45:52.64#ibcon#end of sib2, iclass 22, count 2 2006.245.07:45:52.64#ibcon#*mode == 0, iclass 22, count 2 2006.245.07:45:52.64#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.07:45:52.64#ibcon#[25=AT08-08\r\n] 2006.245.07:45:52.64#ibcon#*before write, iclass 22, count 2 2006.245.07:45:52.64#ibcon#enter sib2, iclass 22, count 2 2006.245.07:45:52.64#ibcon#flushed, iclass 22, count 2 2006.245.07:45:52.64#ibcon#about to write, iclass 22, count 2 2006.245.07:45:52.64#ibcon#wrote, iclass 22, count 2 2006.245.07:45:52.64#ibcon#about to read 3, iclass 22, count 2 2006.245.07:45:52.67#ibcon#read 3, iclass 22, count 2 2006.245.07:45:52.67#ibcon#about to read 4, iclass 22, count 2 2006.245.07:45:52.67#ibcon#read 4, iclass 22, count 2 2006.245.07:45:52.67#ibcon#about to read 5, iclass 22, count 2 2006.245.07:45:52.67#ibcon#read 5, iclass 22, count 2 2006.245.07:45:52.67#ibcon#about to read 6, iclass 22, count 2 2006.245.07:45:52.67#ibcon#read 6, iclass 22, count 2 2006.245.07:45:52.67#ibcon#end of sib2, iclass 22, count 2 2006.245.07:45:52.67#ibcon#*after write, iclass 22, count 2 2006.245.07:45:52.67#ibcon#*before return 0, iclass 22, count 2 2006.245.07:45:52.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:45:52.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:45:52.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.07:45:52.67#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:52.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:45:52.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:45:52.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:45:52.79#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:45:52.79#ibcon#first serial, iclass 22, count 0 2006.245.07:45:52.79#ibcon#enter sib2, iclass 22, count 0 2006.245.07:45:52.79#ibcon#flushed, iclass 22, count 0 2006.245.07:45:52.79#ibcon#about to write, iclass 22, count 0 2006.245.07:45:52.79#ibcon#wrote, iclass 22, count 0 2006.245.07:45:52.79#ibcon#about to read 3, iclass 22, count 0 2006.245.07:45:52.81#ibcon#read 3, iclass 22, count 0 2006.245.07:45:52.81#ibcon#about to read 4, iclass 22, count 0 2006.245.07:45:52.81#ibcon#read 4, iclass 22, count 0 2006.245.07:45:52.81#ibcon#about to read 5, iclass 22, count 0 2006.245.07:45:52.81#ibcon#read 5, iclass 22, count 0 2006.245.07:45:52.81#ibcon#about to read 6, iclass 22, count 0 2006.245.07:45:52.81#ibcon#read 6, iclass 22, count 0 2006.245.07:45:52.81#ibcon#end of sib2, iclass 22, count 0 2006.245.07:45:52.81#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:45:52.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:45:52.81#ibcon#[25=USB\r\n] 2006.245.07:45:52.81#ibcon#*before write, iclass 22, count 0 2006.245.07:45:52.81#ibcon#enter sib2, iclass 22, count 0 2006.245.07:45:52.81#ibcon#flushed, iclass 22, count 0 2006.245.07:45:52.81#ibcon#about to write, iclass 22, count 0 2006.245.07:45:52.81#ibcon#wrote, iclass 22, count 0 2006.245.07:45:52.81#ibcon#about to read 3, iclass 22, count 0 2006.245.07:45:52.84#ibcon#read 3, iclass 22, count 0 2006.245.07:45:52.84#ibcon#about to read 4, iclass 22, count 0 2006.245.07:45:52.84#ibcon#read 4, iclass 22, count 0 2006.245.07:45:52.84#ibcon#about to read 5, iclass 22, count 0 2006.245.07:45:52.84#ibcon#read 5, iclass 22, count 0 2006.245.07:45:52.84#ibcon#about to read 6, iclass 22, count 0 2006.245.07:45:52.84#ibcon#read 6, iclass 22, count 0 2006.245.07:45:52.84#ibcon#end of sib2, iclass 22, count 0 2006.245.07:45:52.84#ibcon#*after write, iclass 22, count 0 2006.245.07:45:52.84#ibcon#*before return 0, iclass 22, count 0 2006.245.07:45:52.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:45:52.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:45:52.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:45:52.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:45:52.84$vc4f8/vblo=1,632.99 2006.245.07:45:52.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.07:45:52.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.07:45:52.84#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:52.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:45:52.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:45:52.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:45:52.84#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:45:52.84#ibcon#first serial, iclass 24, count 0 2006.245.07:45:52.84#ibcon#enter sib2, iclass 24, count 0 2006.245.07:45:52.84#ibcon#flushed, iclass 24, count 0 2006.245.07:45:52.84#ibcon#about to write, iclass 24, count 0 2006.245.07:45:52.84#ibcon#wrote, iclass 24, count 0 2006.245.07:45:52.84#ibcon#about to read 3, iclass 24, count 0 2006.245.07:45:52.86#ibcon#read 3, iclass 24, count 0 2006.245.07:45:52.86#ibcon#about to read 4, iclass 24, count 0 2006.245.07:45:52.86#ibcon#read 4, iclass 24, count 0 2006.245.07:45:52.86#ibcon#about to read 5, iclass 24, count 0 2006.245.07:45:52.86#ibcon#read 5, iclass 24, count 0 2006.245.07:45:52.86#ibcon#about to read 6, iclass 24, count 0 2006.245.07:45:52.86#ibcon#read 6, iclass 24, count 0 2006.245.07:45:52.86#ibcon#end of sib2, iclass 24, count 0 2006.245.07:45:52.86#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:45:52.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:45:52.86#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:45:52.86#ibcon#*before write, iclass 24, count 0 2006.245.07:45:52.86#ibcon#enter sib2, iclass 24, count 0 2006.245.07:45:52.86#ibcon#flushed, iclass 24, count 0 2006.245.07:45:52.86#ibcon#about to write, iclass 24, count 0 2006.245.07:45:52.86#ibcon#wrote, iclass 24, count 0 2006.245.07:45:52.86#ibcon#about to read 3, iclass 24, count 0 2006.245.07:45:52.90#ibcon#read 3, iclass 24, count 0 2006.245.07:45:52.90#ibcon#about to read 4, iclass 24, count 0 2006.245.07:45:52.90#ibcon#read 4, iclass 24, count 0 2006.245.07:45:52.90#ibcon#about to read 5, iclass 24, count 0 2006.245.07:45:52.90#ibcon#read 5, iclass 24, count 0 2006.245.07:45:52.90#ibcon#about to read 6, iclass 24, count 0 2006.245.07:45:52.90#ibcon#read 6, iclass 24, count 0 2006.245.07:45:52.90#ibcon#end of sib2, iclass 24, count 0 2006.245.07:45:52.90#ibcon#*after write, iclass 24, count 0 2006.245.07:45:52.90#ibcon#*before return 0, iclass 24, count 0 2006.245.07:45:52.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:45:52.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:45:52.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:45:52.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:45:52.90$vc4f8/vb=1,4 2006.245.07:45:52.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.07:45:52.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.07:45:52.90#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:52.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:45:52.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:45:52.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:45:52.90#ibcon#enter wrdev, iclass 26, count 2 2006.245.07:45:52.90#ibcon#first serial, iclass 26, count 2 2006.245.07:45:52.90#ibcon#enter sib2, iclass 26, count 2 2006.245.07:45:52.90#ibcon#flushed, iclass 26, count 2 2006.245.07:45:52.90#ibcon#about to write, iclass 26, count 2 2006.245.07:45:52.90#ibcon#wrote, iclass 26, count 2 2006.245.07:45:52.90#ibcon#about to read 3, iclass 26, count 2 2006.245.07:45:52.92#ibcon#read 3, iclass 26, count 2 2006.245.07:45:52.92#ibcon#about to read 4, iclass 26, count 2 2006.245.07:45:52.92#ibcon#read 4, iclass 26, count 2 2006.245.07:45:52.92#ibcon#about to read 5, iclass 26, count 2 2006.245.07:45:52.92#ibcon#read 5, iclass 26, count 2 2006.245.07:45:52.92#ibcon#about to read 6, iclass 26, count 2 2006.245.07:45:52.92#ibcon#read 6, iclass 26, count 2 2006.245.07:45:52.92#ibcon#end of sib2, iclass 26, count 2 2006.245.07:45:52.92#ibcon#*mode == 0, iclass 26, count 2 2006.245.07:45:52.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.07:45:52.92#ibcon#[27=AT01-04\r\n] 2006.245.07:45:52.92#ibcon#*before write, iclass 26, count 2 2006.245.07:45:52.92#ibcon#enter sib2, iclass 26, count 2 2006.245.07:45:52.92#ibcon#flushed, iclass 26, count 2 2006.245.07:45:52.92#ibcon#about to write, iclass 26, count 2 2006.245.07:45:52.92#ibcon#wrote, iclass 26, count 2 2006.245.07:45:52.92#ibcon#about to read 3, iclass 26, count 2 2006.245.07:45:52.95#ibcon#read 3, iclass 26, count 2 2006.245.07:45:52.95#ibcon#about to read 4, iclass 26, count 2 2006.245.07:45:52.95#ibcon#read 4, iclass 26, count 2 2006.245.07:45:52.95#ibcon#about to read 5, iclass 26, count 2 2006.245.07:45:52.95#ibcon#read 5, iclass 26, count 2 2006.245.07:45:52.95#ibcon#about to read 6, iclass 26, count 2 2006.245.07:45:52.95#ibcon#read 6, iclass 26, count 2 2006.245.07:45:52.95#ibcon#end of sib2, iclass 26, count 2 2006.245.07:45:52.95#ibcon#*after write, iclass 26, count 2 2006.245.07:45:52.95#ibcon#*before return 0, iclass 26, count 2 2006.245.07:45:52.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:45:52.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:45:52.95#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.07:45:52.95#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:52.95#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:45:53.07#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:45:53.07#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:45:53.07#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:45:53.07#ibcon#first serial, iclass 26, count 0 2006.245.07:45:53.07#ibcon#enter sib2, iclass 26, count 0 2006.245.07:45:53.07#ibcon#flushed, iclass 26, count 0 2006.245.07:45:53.07#ibcon#about to write, iclass 26, count 0 2006.245.07:45:53.07#ibcon#wrote, iclass 26, count 0 2006.245.07:45:53.07#ibcon#about to read 3, iclass 26, count 0 2006.245.07:45:53.09#ibcon#read 3, iclass 26, count 0 2006.245.07:45:53.09#ibcon#about to read 4, iclass 26, count 0 2006.245.07:45:53.09#ibcon#read 4, iclass 26, count 0 2006.245.07:45:53.09#ibcon#about to read 5, iclass 26, count 0 2006.245.07:45:53.09#ibcon#read 5, iclass 26, count 0 2006.245.07:45:53.09#ibcon#about to read 6, iclass 26, count 0 2006.245.07:45:53.09#ibcon#read 6, iclass 26, count 0 2006.245.07:45:53.09#ibcon#end of sib2, iclass 26, count 0 2006.245.07:45:53.09#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:45:53.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:45:53.09#ibcon#[27=USB\r\n] 2006.245.07:45:53.09#ibcon#*before write, iclass 26, count 0 2006.245.07:45:53.09#ibcon#enter sib2, iclass 26, count 0 2006.245.07:45:53.09#ibcon#flushed, iclass 26, count 0 2006.245.07:45:53.09#ibcon#about to write, iclass 26, count 0 2006.245.07:45:53.09#ibcon#wrote, iclass 26, count 0 2006.245.07:45:53.09#ibcon#about to read 3, iclass 26, count 0 2006.245.07:45:53.12#ibcon#read 3, iclass 26, count 0 2006.245.07:45:53.12#ibcon#about to read 4, iclass 26, count 0 2006.245.07:45:53.12#ibcon#read 4, iclass 26, count 0 2006.245.07:45:53.12#ibcon#about to read 5, iclass 26, count 0 2006.245.07:45:53.12#ibcon#read 5, iclass 26, count 0 2006.245.07:45:53.12#ibcon#about to read 6, iclass 26, count 0 2006.245.07:45:53.12#ibcon#read 6, iclass 26, count 0 2006.245.07:45:53.12#ibcon#end of sib2, iclass 26, count 0 2006.245.07:45:53.12#ibcon#*after write, iclass 26, count 0 2006.245.07:45:53.12#ibcon#*before return 0, iclass 26, count 0 2006.245.07:45:53.12#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:45:53.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:45:53.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:45:53.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:45:53.12$vc4f8/vblo=2,640.99 2006.245.07:45:53.12#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:45:53.12#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:45:53.12#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:53.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:53.12#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:53.12#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:53.12#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:45:53.12#ibcon#first serial, iclass 28, count 0 2006.245.07:45:53.12#ibcon#enter sib2, iclass 28, count 0 2006.245.07:45:53.12#ibcon#flushed, iclass 28, count 0 2006.245.07:45:53.12#ibcon#about to write, iclass 28, count 0 2006.245.07:45:53.12#ibcon#wrote, iclass 28, count 0 2006.245.07:45:53.12#ibcon#about to read 3, iclass 28, count 0 2006.245.07:45:53.14#ibcon#read 3, iclass 28, count 0 2006.245.07:45:53.14#ibcon#about to read 4, iclass 28, count 0 2006.245.07:45:53.14#ibcon#read 4, iclass 28, count 0 2006.245.07:45:53.14#ibcon#about to read 5, iclass 28, count 0 2006.245.07:45:53.14#ibcon#read 5, iclass 28, count 0 2006.245.07:45:53.14#ibcon#about to read 6, iclass 28, count 0 2006.245.07:45:53.14#ibcon#read 6, iclass 28, count 0 2006.245.07:45:53.14#ibcon#end of sib2, iclass 28, count 0 2006.245.07:45:53.14#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:45:53.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:45:53.14#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:45:53.14#ibcon#*before write, iclass 28, count 0 2006.245.07:45:53.14#ibcon#enter sib2, iclass 28, count 0 2006.245.07:45:53.14#ibcon#flushed, iclass 28, count 0 2006.245.07:45:53.14#ibcon#about to write, iclass 28, count 0 2006.245.07:45:53.14#ibcon#wrote, iclass 28, count 0 2006.245.07:45:53.14#ibcon#about to read 3, iclass 28, count 0 2006.245.07:45:53.18#ibcon#read 3, iclass 28, count 0 2006.245.07:45:53.18#ibcon#about to read 4, iclass 28, count 0 2006.245.07:45:53.18#ibcon#read 4, iclass 28, count 0 2006.245.07:45:53.18#ibcon#about to read 5, iclass 28, count 0 2006.245.07:45:53.18#ibcon#read 5, iclass 28, count 0 2006.245.07:45:53.18#ibcon#about to read 6, iclass 28, count 0 2006.245.07:45:53.18#ibcon#read 6, iclass 28, count 0 2006.245.07:45:53.18#ibcon#end of sib2, iclass 28, count 0 2006.245.07:45:53.18#ibcon#*after write, iclass 28, count 0 2006.245.07:45:53.18#ibcon#*before return 0, iclass 28, count 0 2006.245.07:45:53.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:53.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:45:53.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:45:53.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:45:53.18$vc4f8/vb=2,4 2006.245.07:45:53.18#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.07:45:53.18#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.07:45:53.18#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:53.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:53.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:53.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:53.24#ibcon#enter wrdev, iclass 30, count 2 2006.245.07:45:53.24#ibcon#first serial, iclass 30, count 2 2006.245.07:45:53.24#ibcon#enter sib2, iclass 30, count 2 2006.245.07:45:53.24#ibcon#flushed, iclass 30, count 2 2006.245.07:45:53.24#ibcon#about to write, iclass 30, count 2 2006.245.07:45:53.24#ibcon#wrote, iclass 30, count 2 2006.245.07:45:53.24#ibcon#about to read 3, iclass 30, count 2 2006.245.07:45:53.26#ibcon#read 3, iclass 30, count 2 2006.245.07:45:53.26#ibcon#about to read 4, iclass 30, count 2 2006.245.07:45:53.26#ibcon#read 4, iclass 30, count 2 2006.245.07:45:53.26#ibcon#about to read 5, iclass 30, count 2 2006.245.07:45:53.26#ibcon#read 5, iclass 30, count 2 2006.245.07:45:53.26#ibcon#about to read 6, iclass 30, count 2 2006.245.07:45:53.26#ibcon#read 6, iclass 30, count 2 2006.245.07:45:53.26#ibcon#end of sib2, iclass 30, count 2 2006.245.07:45:53.26#ibcon#*mode == 0, iclass 30, count 2 2006.245.07:45:53.26#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.07:45:53.26#ibcon#[27=AT02-04\r\n] 2006.245.07:45:53.26#ibcon#*before write, iclass 30, count 2 2006.245.07:45:53.26#ibcon#enter sib2, iclass 30, count 2 2006.245.07:45:53.26#ibcon#flushed, iclass 30, count 2 2006.245.07:45:53.26#ibcon#about to write, iclass 30, count 2 2006.245.07:45:53.26#ibcon#wrote, iclass 30, count 2 2006.245.07:45:53.26#ibcon#about to read 3, iclass 30, count 2 2006.245.07:45:53.29#ibcon#read 3, iclass 30, count 2 2006.245.07:45:53.29#ibcon#about to read 4, iclass 30, count 2 2006.245.07:45:53.29#ibcon#read 4, iclass 30, count 2 2006.245.07:45:53.29#ibcon#about to read 5, iclass 30, count 2 2006.245.07:45:53.29#ibcon#read 5, iclass 30, count 2 2006.245.07:45:53.29#ibcon#about to read 6, iclass 30, count 2 2006.245.07:45:53.29#ibcon#read 6, iclass 30, count 2 2006.245.07:45:53.29#ibcon#end of sib2, iclass 30, count 2 2006.245.07:45:53.29#ibcon#*after write, iclass 30, count 2 2006.245.07:45:53.29#ibcon#*before return 0, iclass 30, count 2 2006.245.07:45:53.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:53.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.07:45:53.29#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.07:45:53.29#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:53.29#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:53.41#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:53.41#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:53.41#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:45:53.41#ibcon#first serial, iclass 30, count 0 2006.245.07:45:53.41#ibcon#enter sib2, iclass 30, count 0 2006.245.07:45:53.41#ibcon#flushed, iclass 30, count 0 2006.245.07:45:53.41#ibcon#about to write, iclass 30, count 0 2006.245.07:45:53.41#ibcon#wrote, iclass 30, count 0 2006.245.07:45:53.41#ibcon#about to read 3, iclass 30, count 0 2006.245.07:45:53.43#ibcon#read 3, iclass 30, count 0 2006.245.07:45:53.43#ibcon#about to read 4, iclass 30, count 0 2006.245.07:45:53.43#ibcon#read 4, iclass 30, count 0 2006.245.07:45:53.43#ibcon#about to read 5, iclass 30, count 0 2006.245.07:45:53.43#ibcon#read 5, iclass 30, count 0 2006.245.07:45:53.43#ibcon#about to read 6, iclass 30, count 0 2006.245.07:45:53.43#ibcon#read 6, iclass 30, count 0 2006.245.07:45:53.43#ibcon#end of sib2, iclass 30, count 0 2006.245.07:45:53.43#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:45:53.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:45:53.43#ibcon#[27=USB\r\n] 2006.245.07:45:53.43#ibcon#*before write, iclass 30, count 0 2006.245.07:45:53.43#ibcon#enter sib2, iclass 30, count 0 2006.245.07:45:53.43#ibcon#flushed, iclass 30, count 0 2006.245.07:45:53.43#ibcon#about to write, iclass 30, count 0 2006.245.07:45:53.43#ibcon#wrote, iclass 30, count 0 2006.245.07:45:53.43#ibcon#about to read 3, iclass 30, count 0 2006.245.07:45:53.46#ibcon#read 3, iclass 30, count 0 2006.245.07:45:53.46#ibcon#about to read 4, iclass 30, count 0 2006.245.07:45:53.46#ibcon#read 4, iclass 30, count 0 2006.245.07:45:53.46#ibcon#about to read 5, iclass 30, count 0 2006.245.07:45:53.46#ibcon#read 5, iclass 30, count 0 2006.245.07:45:53.46#ibcon#about to read 6, iclass 30, count 0 2006.245.07:45:53.46#ibcon#read 6, iclass 30, count 0 2006.245.07:45:53.46#ibcon#end of sib2, iclass 30, count 0 2006.245.07:45:53.46#ibcon#*after write, iclass 30, count 0 2006.245.07:45:53.46#ibcon#*before return 0, iclass 30, count 0 2006.245.07:45:53.46#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:53.46#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.07:45:53.46#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:45:53.46#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:45:53.46$vc4f8/vblo=3,656.99 2006.245.07:45:53.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.07:45:53.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.07:45:53.46#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:53.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:53.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:53.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:53.46#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:45:53.46#ibcon#first serial, iclass 32, count 0 2006.245.07:45:53.46#ibcon#enter sib2, iclass 32, count 0 2006.245.07:45:53.46#ibcon#flushed, iclass 32, count 0 2006.245.07:45:53.46#ibcon#about to write, iclass 32, count 0 2006.245.07:45:53.46#ibcon#wrote, iclass 32, count 0 2006.245.07:45:53.46#ibcon#about to read 3, iclass 32, count 0 2006.245.07:45:53.48#ibcon#read 3, iclass 32, count 0 2006.245.07:45:53.48#ibcon#about to read 4, iclass 32, count 0 2006.245.07:45:53.48#ibcon#read 4, iclass 32, count 0 2006.245.07:45:53.48#ibcon#about to read 5, iclass 32, count 0 2006.245.07:45:53.48#ibcon#read 5, iclass 32, count 0 2006.245.07:45:53.48#ibcon#about to read 6, iclass 32, count 0 2006.245.07:45:53.48#ibcon#read 6, iclass 32, count 0 2006.245.07:45:53.48#ibcon#end of sib2, iclass 32, count 0 2006.245.07:45:53.48#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:45:53.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:45:53.48#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:45:53.48#ibcon#*before write, iclass 32, count 0 2006.245.07:45:53.48#ibcon#enter sib2, iclass 32, count 0 2006.245.07:45:53.48#ibcon#flushed, iclass 32, count 0 2006.245.07:45:53.48#ibcon#about to write, iclass 32, count 0 2006.245.07:45:53.48#ibcon#wrote, iclass 32, count 0 2006.245.07:45:53.48#ibcon#about to read 3, iclass 32, count 0 2006.245.07:45:53.52#ibcon#read 3, iclass 32, count 0 2006.245.07:45:53.52#ibcon#about to read 4, iclass 32, count 0 2006.245.07:45:53.52#ibcon#read 4, iclass 32, count 0 2006.245.07:45:53.52#ibcon#about to read 5, iclass 32, count 0 2006.245.07:45:53.52#ibcon#read 5, iclass 32, count 0 2006.245.07:45:53.52#ibcon#about to read 6, iclass 32, count 0 2006.245.07:45:53.52#ibcon#read 6, iclass 32, count 0 2006.245.07:45:53.52#ibcon#end of sib2, iclass 32, count 0 2006.245.07:45:53.52#ibcon#*after write, iclass 32, count 0 2006.245.07:45:53.52#ibcon#*before return 0, iclass 32, count 0 2006.245.07:45:53.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:53.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.07:45:53.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:45:53.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:45:53.52$vc4f8/vb=3,4 2006.245.07:45:53.52#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.07:45:53.52#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.07:45:53.52#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:53.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:53.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:53.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:53.58#ibcon#enter wrdev, iclass 34, count 2 2006.245.07:45:53.58#ibcon#first serial, iclass 34, count 2 2006.245.07:45:53.58#ibcon#enter sib2, iclass 34, count 2 2006.245.07:45:53.58#ibcon#flushed, iclass 34, count 2 2006.245.07:45:53.58#ibcon#about to write, iclass 34, count 2 2006.245.07:45:53.58#ibcon#wrote, iclass 34, count 2 2006.245.07:45:53.58#ibcon#about to read 3, iclass 34, count 2 2006.245.07:45:53.60#ibcon#read 3, iclass 34, count 2 2006.245.07:45:53.60#ibcon#about to read 4, iclass 34, count 2 2006.245.07:45:53.60#ibcon#read 4, iclass 34, count 2 2006.245.07:45:53.60#ibcon#about to read 5, iclass 34, count 2 2006.245.07:45:53.60#ibcon#read 5, iclass 34, count 2 2006.245.07:45:53.60#ibcon#about to read 6, iclass 34, count 2 2006.245.07:45:53.60#ibcon#read 6, iclass 34, count 2 2006.245.07:45:53.60#ibcon#end of sib2, iclass 34, count 2 2006.245.07:45:53.60#ibcon#*mode == 0, iclass 34, count 2 2006.245.07:45:53.60#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.07:45:53.60#ibcon#[27=AT03-04\r\n] 2006.245.07:45:53.60#ibcon#*before write, iclass 34, count 2 2006.245.07:45:53.60#ibcon#enter sib2, iclass 34, count 2 2006.245.07:45:53.60#ibcon#flushed, iclass 34, count 2 2006.245.07:45:53.60#ibcon#about to write, iclass 34, count 2 2006.245.07:45:53.60#ibcon#wrote, iclass 34, count 2 2006.245.07:45:53.60#ibcon#about to read 3, iclass 34, count 2 2006.245.07:45:53.63#ibcon#read 3, iclass 34, count 2 2006.245.07:45:53.63#ibcon#about to read 4, iclass 34, count 2 2006.245.07:45:53.63#ibcon#read 4, iclass 34, count 2 2006.245.07:45:53.63#ibcon#about to read 5, iclass 34, count 2 2006.245.07:45:53.63#ibcon#read 5, iclass 34, count 2 2006.245.07:45:53.63#ibcon#about to read 6, iclass 34, count 2 2006.245.07:45:53.63#ibcon#read 6, iclass 34, count 2 2006.245.07:45:53.63#ibcon#end of sib2, iclass 34, count 2 2006.245.07:45:53.63#ibcon#*after write, iclass 34, count 2 2006.245.07:45:53.63#ibcon#*before return 0, iclass 34, count 2 2006.245.07:45:53.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:53.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.07:45:53.63#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.07:45:53.63#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:53.63#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:53.75#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:53.75#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:53.75#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:45:53.75#ibcon#first serial, iclass 34, count 0 2006.245.07:45:53.75#ibcon#enter sib2, iclass 34, count 0 2006.245.07:45:53.75#ibcon#flushed, iclass 34, count 0 2006.245.07:45:53.75#ibcon#about to write, iclass 34, count 0 2006.245.07:45:53.75#ibcon#wrote, iclass 34, count 0 2006.245.07:45:53.75#ibcon#about to read 3, iclass 34, count 0 2006.245.07:45:53.77#ibcon#read 3, iclass 34, count 0 2006.245.07:45:53.77#ibcon#about to read 4, iclass 34, count 0 2006.245.07:45:53.77#ibcon#read 4, iclass 34, count 0 2006.245.07:45:53.77#ibcon#about to read 5, iclass 34, count 0 2006.245.07:45:53.77#ibcon#read 5, iclass 34, count 0 2006.245.07:45:53.77#ibcon#about to read 6, iclass 34, count 0 2006.245.07:45:53.77#ibcon#read 6, iclass 34, count 0 2006.245.07:45:53.77#ibcon#end of sib2, iclass 34, count 0 2006.245.07:45:53.77#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:45:53.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:45:53.77#ibcon#[27=USB\r\n] 2006.245.07:45:53.77#ibcon#*before write, iclass 34, count 0 2006.245.07:45:53.77#ibcon#enter sib2, iclass 34, count 0 2006.245.07:45:53.77#ibcon#flushed, iclass 34, count 0 2006.245.07:45:53.77#ibcon#about to write, iclass 34, count 0 2006.245.07:45:53.77#ibcon#wrote, iclass 34, count 0 2006.245.07:45:53.77#ibcon#about to read 3, iclass 34, count 0 2006.245.07:45:53.80#ibcon#read 3, iclass 34, count 0 2006.245.07:45:53.80#ibcon#about to read 4, iclass 34, count 0 2006.245.07:45:53.80#ibcon#read 4, iclass 34, count 0 2006.245.07:45:53.80#ibcon#about to read 5, iclass 34, count 0 2006.245.07:45:53.80#ibcon#read 5, iclass 34, count 0 2006.245.07:45:53.80#ibcon#about to read 6, iclass 34, count 0 2006.245.07:45:53.80#ibcon#read 6, iclass 34, count 0 2006.245.07:45:53.80#ibcon#end of sib2, iclass 34, count 0 2006.245.07:45:53.80#ibcon#*after write, iclass 34, count 0 2006.245.07:45:53.80#ibcon#*before return 0, iclass 34, count 0 2006.245.07:45:53.80#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:53.80#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.07:45:53.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:45:53.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:45:53.80$vc4f8/vblo=4,712.99 2006.245.07:45:53.80#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.07:45:53.80#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.07:45:53.80#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:53.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:53.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:53.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:53.80#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:45:53.80#ibcon#first serial, iclass 36, count 0 2006.245.07:45:53.80#ibcon#enter sib2, iclass 36, count 0 2006.245.07:45:53.80#ibcon#flushed, iclass 36, count 0 2006.245.07:45:53.80#ibcon#about to write, iclass 36, count 0 2006.245.07:45:53.80#ibcon#wrote, iclass 36, count 0 2006.245.07:45:53.80#ibcon#about to read 3, iclass 36, count 0 2006.245.07:45:53.82#ibcon#read 3, iclass 36, count 0 2006.245.07:45:53.82#ibcon#about to read 4, iclass 36, count 0 2006.245.07:45:53.82#ibcon#read 4, iclass 36, count 0 2006.245.07:45:53.82#ibcon#about to read 5, iclass 36, count 0 2006.245.07:45:53.82#ibcon#read 5, iclass 36, count 0 2006.245.07:45:53.82#ibcon#about to read 6, iclass 36, count 0 2006.245.07:45:53.82#ibcon#read 6, iclass 36, count 0 2006.245.07:45:53.82#ibcon#end of sib2, iclass 36, count 0 2006.245.07:45:53.82#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:45:53.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:45:53.82#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:45:53.82#ibcon#*before write, iclass 36, count 0 2006.245.07:45:53.82#ibcon#enter sib2, iclass 36, count 0 2006.245.07:45:53.82#ibcon#flushed, iclass 36, count 0 2006.245.07:45:53.82#ibcon#about to write, iclass 36, count 0 2006.245.07:45:53.82#ibcon#wrote, iclass 36, count 0 2006.245.07:45:53.82#ibcon#about to read 3, iclass 36, count 0 2006.245.07:45:53.86#ibcon#read 3, iclass 36, count 0 2006.245.07:45:53.86#ibcon#about to read 4, iclass 36, count 0 2006.245.07:45:53.86#ibcon#read 4, iclass 36, count 0 2006.245.07:45:53.86#ibcon#about to read 5, iclass 36, count 0 2006.245.07:45:53.86#ibcon#read 5, iclass 36, count 0 2006.245.07:45:53.86#ibcon#about to read 6, iclass 36, count 0 2006.245.07:45:53.86#ibcon#read 6, iclass 36, count 0 2006.245.07:45:53.86#ibcon#end of sib2, iclass 36, count 0 2006.245.07:45:53.86#ibcon#*after write, iclass 36, count 0 2006.245.07:45:53.86#ibcon#*before return 0, iclass 36, count 0 2006.245.07:45:53.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:53.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:45:53.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:45:53.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:45:53.86$vc4f8/vb=4,4 2006.245.07:45:53.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.07:45:53.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.07:45:53.86#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:53.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:53.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:53.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:53.92#ibcon#enter wrdev, iclass 38, count 2 2006.245.07:45:53.92#ibcon#first serial, iclass 38, count 2 2006.245.07:45:53.92#ibcon#enter sib2, iclass 38, count 2 2006.245.07:45:53.92#ibcon#flushed, iclass 38, count 2 2006.245.07:45:53.92#ibcon#about to write, iclass 38, count 2 2006.245.07:45:53.92#ibcon#wrote, iclass 38, count 2 2006.245.07:45:53.92#ibcon#about to read 3, iclass 38, count 2 2006.245.07:45:53.94#ibcon#read 3, iclass 38, count 2 2006.245.07:45:53.94#ibcon#about to read 4, iclass 38, count 2 2006.245.07:45:53.94#ibcon#read 4, iclass 38, count 2 2006.245.07:45:53.94#ibcon#about to read 5, iclass 38, count 2 2006.245.07:45:53.94#ibcon#read 5, iclass 38, count 2 2006.245.07:45:53.94#ibcon#about to read 6, iclass 38, count 2 2006.245.07:45:53.94#ibcon#read 6, iclass 38, count 2 2006.245.07:45:53.94#ibcon#end of sib2, iclass 38, count 2 2006.245.07:45:53.94#ibcon#*mode == 0, iclass 38, count 2 2006.245.07:45:53.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.07:45:53.94#ibcon#[27=AT04-04\r\n] 2006.245.07:45:53.94#ibcon#*before write, iclass 38, count 2 2006.245.07:45:53.94#ibcon#enter sib2, iclass 38, count 2 2006.245.07:45:53.94#ibcon#flushed, iclass 38, count 2 2006.245.07:45:53.94#ibcon#about to write, iclass 38, count 2 2006.245.07:45:53.94#ibcon#wrote, iclass 38, count 2 2006.245.07:45:53.94#ibcon#about to read 3, iclass 38, count 2 2006.245.07:45:53.97#ibcon#read 3, iclass 38, count 2 2006.245.07:45:53.97#ibcon#about to read 4, iclass 38, count 2 2006.245.07:45:53.97#ibcon#read 4, iclass 38, count 2 2006.245.07:45:53.97#ibcon#about to read 5, iclass 38, count 2 2006.245.07:45:53.97#ibcon#read 5, iclass 38, count 2 2006.245.07:45:53.97#ibcon#about to read 6, iclass 38, count 2 2006.245.07:45:53.97#ibcon#read 6, iclass 38, count 2 2006.245.07:45:53.97#ibcon#end of sib2, iclass 38, count 2 2006.245.07:45:53.97#ibcon#*after write, iclass 38, count 2 2006.245.07:45:53.97#ibcon#*before return 0, iclass 38, count 2 2006.245.07:45:53.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:53.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:45:53.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.07:45:53.97#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:53.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:54.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:54.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:54.09#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:45:54.09#ibcon#first serial, iclass 38, count 0 2006.245.07:45:54.09#ibcon#enter sib2, iclass 38, count 0 2006.245.07:45:54.09#ibcon#flushed, iclass 38, count 0 2006.245.07:45:54.09#ibcon#about to write, iclass 38, count 0 2006.245.07:45:54.09#ibcon#wrote, iclass 38, count 0 2006.245.07:45:54.09#ibcon#about to read 3, iclass 38, count 0 2006.245.07:45:54.11#ibcon#read 3, iclass 38, count 0 2006.245.07:45:54.11#ibcon#about to read 4, iclass 38, count 0 2006.245.07:45:54.11#ibcon#read 4, iclass 38, count 0 2006.245.07:45:54.11#ibcon#about to read 5, iclass 38, count 0 2006.245.07:45:54.11#ibcon#read 5, iclass 38, count 0 2006.245.07:45:54.11#ibcon#about to read 6, iclass 38, count 0 2006.245.07:45:54.11#ibcon#read 6, iclass 38, count 0 2006.245.07:45:54.11#ibcon#end of sib2, iclass 38, count 0 2006.245.07:45:54.11#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:45:54.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:45:54.11#ibcon#[27=USB\r\n] 2006.245.07:45:54.11#ibcon#*before write, iclass 38, count 0 2006.245.07:45:54.11#ibcon#enter sib2, iclass 38, count 0 2006.245.07:45:54.11#ibcon#flushed, iclass 38, count 0 2006.245.07:45:54.11#ibcon#about to write, iclass 38, count 0 2006.245.07:45:54.11#ibcon#wrote, iclass 38, count 0 2006.245.07:45:54.11#ibcon#about to read 3, iclass 38, count 0 2006.245.07:45:54.14#ibcon#read 3, iclass 38, count 0 2006.245.07:45:54.14#ibcon#about to read 4, iclass 38, count 0 2006.245.07:45:54.14#ibcon#read 4, iclass 38, count 0 2006.245.07:45:54.14#ibcon#about to read 5, iclass 38, count 0 2006.245.07:45:54.14#ibcon#read 5, iclass 38, count 0 2006.245.07:45:54.14#ibcon#about to read 6, iclass 38, count 0 2006.245.07:45:54.14#ibcon#read 6, iclass 38, count 0 2006.245.07:45:54.14#ibcon#end of sib2, iclass 38, count 0 2006.245.07:45:54.14#ibcon#*after write, iclass 38, count 0 2006.245.07:45:54.14#ibcon#*before return 0, iclass 38, count 0 2006.245.07:45:54.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:54.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:45:54.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:45:54.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:45:54.14$vc4f8/vblo=5,744.99 2006.245.07:45:54.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.07:45:54.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.07:45:54.14#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:54.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:54.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:54.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:54.14#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:45:54.14#ibcon#first serial, iclass 40, count 0 2006.245.07:45:54.14#ibcon#enter sib2, iclass 40, count 0 2006.245.07:45:54.14#ibcon#flushed, iclass 40, count 0 2006.245.07:45:54.14#ibcon#about to write, iclass 40, count 0 2006.245.07:45:54.14#ibcon#wrote, iclass 40, count 0 2006.245.07:45:54.14#ibcon#about to read 3, iclass 40, count 0 2006.245.07:45:54.16#ibcon#read 3, iclass 40, count 0 2006.245.07:45:54.16#ibcon#about to read 4, iclass 40, count 0 2006.245.07:45:54.16#ibcon#read 4, iclass 40, count 0 2006.245.07:45:54.16#ibcon#about to read 5, iclass 40, count 0 2006.245.07:45:54.16#ibcon#read 5, iclass 40, count 0 2006.245.07:45:54.16#ibcon#about to read 6, iclass 40, count 0 2006.245.07:45:54.16#ibcon#read 6, iclass 40, count 0 2006.245.07:45:54.16#ibcon#end of sib2, iclass 40, count 0 2006.245.07:45:54.16#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:45:54.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:45:54.16#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:45:54.16#ibcon#*before write, iclass 40, count 0 2006.245.07:45:54.16#ibcon#enter sib2, iclass 40, count 0 2006.245.07:45:54.16#ibcon#flushed, iclass 40, count 0 2006.245.07:45:54.16#ibcon#about to write, iclass 40, count 0 2006.245.07:45:54.16#ibcon#wrote, iclass 40, count 0 2006.245.07:45:54.16#ibcon#about to read 3, iclass 40, count 0 2006.245.07:45:54.20#ibcon#read 3, iclass 40, count 0 2006.245.07:45:54.20#ibcon#about to read 4, iclass 40, count 0 2006.245.07:45:54.20#ibcon#read 4, iclass 40, count 0 2006.245.07:45:54.20#ibcon#about to read 5, iclass 40, count 0 2006.245.07:45:54.20#ibcon#read 5, iclass 40, count 0 2006.245.07:45:54.20#ibcon#about to read 6, iclass 40, count 0 2006.245.07:45:54.20#ibcon#read 6, iclass 40, count 0 2006.245.07:45:54.20#ibcon#end of sib2, iclass 40, count 0 2006.245.07:45:54.20#ibcon#*after write, iclass 40, count 0 2006.245.07:45:54.20#ibcon#*before return 0, iclass 40, count 0 2006.245.07:45:54.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:54.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:45:54.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:45:54.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:45:54.20$vc4f8/vb=5,3 2006.245.07:45:54.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.07:45:54.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.07:45:54.20#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:54.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:54.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:54.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:54.26#ibcon#enter wrdev, iclass 4, count 2 2006.245.07:45:54.26#ibcon#first serial, iclass 4, count 2 2006.245.07:45:54.26#ibcon#enter sib2, iclass 4, count 2 2006.245.07:45:54.26#ibcon#flushed, iclass 4, count 2 2006.245.07:45:54.26#ibcon#about to write, iclass 4, count 2 2006.245.07:45:54.26#ibcon#wrote, iclass 4, count 2 2006.245.07:45:54.26#ibcon#about to read 3, iclass 4, count 2 2006.245.07:45:54.28#ibcon#read 3, iclass 4, count 2 2006.245.07:45:54.28#ibcon#about to read 4, iclass 4, count 2 2006.245.07:45:54.28#ibcon#read 4, iclass 4, count 2 2006.245.07:45:54.28#ibcon#about to read 5, iclass 4, count 2 2006.245.07:45:54.28#ibcon#read 5, iclass 4, count 2 2006.245.07:45:54.28#ibcon#about to read 6, iclass 4, count 2 2006.245.07:45:54.28#ibcon#read 6, iclass 4, count 2 2006.245.07:45:54.28#ibcon#end of sib2, iclass 4, count 2 2006.245.07:45:54.28#ibcon#*mode == 0, iclass 4, count 2 2006.245.07:45:54.28#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.07:45:54.28#ibcon#[27=AT05-03\r\n] 2006.245.07:45:54.28#ibcon#*before write, iclass 4, count 2 2006.245.07:45:54.28#ibcon#enter sib2, iclass 4, count 2 2006.245.07:45:54.28#ibcon#flushed, iclass 4, count 2 2006.245.07:45:54.28#ibcon#about to write, iclass 4, count 2 2006.245.07:45:54.28#ibcon#wrote, iclass 4, count 2 2006.245.07:45:54.28#ibcon#about to read 3, iclass 4, count 2 2006.245.07:45:54.31#ibcon#read 3, iclass 4, count 2 2006.245.07:45:54.31#ibcon#about to read 4, iclass 4, count 2 2006.245.07:45:54.31#ibcon#read 4, iclass 4, count 2 2006.245.07:45:54.31#ibcon#about to read 5, iclass 4, count 2 2006.245.07:45:54.31#ibcon#read 5, iclass 4, count 2 2006.245.07:45:54.31#ibcon#about to read 6, iclass 4, count 2 2006.245.07:45:54.31#ibcon#read 6, iclass 4, count 2 2006.245.07:45:54.31#ibcon#end of sib2, iclass 4, count 2 2006.245.07:45:54.31#ibcon#*after write, iclass 4, count 2 2006.245.07:45:54.31#ibcon#*before return 0, iclass 4, count 2 2006.245.07:45:54.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:54.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:45:54.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.07:45:54.31#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:54.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:54.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:54.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:54.43#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:45:54.43#ibcon#first serial, iclass 4, count 0 2006.245.07:45:54.43#ibcon#enter sib2, iclass 4, count 0 2006.245.07:45:54.43#ibcon#flushed, iclass 4, count 0 2006.245.07:45:54.43#ibcon#about to write, iclass 4, count 0 2006.245.07:45:54.43#ibcon#wrote, iclass 4, count 0 2006.245.07:45:54.43#ibcon#about to read 3, iclass 4, count 0 2006.245.07:45:54.45#ibcon#read 3, iclass 4, count 0 2006.245.07:45:54.45#ibcon#about to read 4, iclass 4, count 0 2006.245.07:45:54.45#ibcon#read 4, iclass 4, count 0 2006.245.07:45:54.45#ibcon#about to read 5, iclass 4, count 0 2006.245.07:45:54.45#ibcon#read 5, iclass 4, count 0 2006.245.07:45:54.45#ibcon#about to read 6, iclass 4, count 0 2006.245.07:45:54.45#ibcon#read 6, iclass 4, count 0 2006.245.07:45:54.45#ibcon#end of sib2, iclass 4, count 0 2006.245.07:45:54.45#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:45:54.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:45:54.45#ibcon#[27=USB\r\n] 2006.245.07:45:54.45#ibcon#*before write, iclass 4, count 0 2006.245.07:45:54.45#ibcon#enter sib2, iclass 4, count 0 2006.245.07:45:54.45#ibcon#flushed, iclass 4, count 0 2006.245.07:45:54.45#ibcon#about to write, iclass 4, count 0 2006.245.07:45:54.45#ibcon#wrote, iclass 4, count 0 2006.245.07:45:54.45#ibcon#about to read 3, iclass 4, count 0 2006.245.07:45:54.48#ibcon#read 3, iclass 4, count 0 2006.245.07:45:54.48#ibcon#about to read 4, iclass 4, count 0 2006.245.07:45:54.48#ibcon#read 4, iclass 4, count 0 2006.245.07:45:54.48#ibcon#about to read 5, iclass 4, count 0 2006.245.07:45:54.48#ibcon#read 5, iclass 4, count 0 2006.245.07:45:54.48#ibcon#about to read 6, iclass 4, count 0 2006.245.07:45:54.48#ibcon#read 6, iclass 4, count 0 2006.245.07:45:54.48#ibcon#end of sib2, iclass 4, count 0 2006.245.07:45:54.48#ibcon#*after write, iclass 4, count 0 2006.245.07:45:54.48#ibcon#*before return 0, iclass 4, count 0 2006.245.07:45:54.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:54.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:45:54.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:45:54.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:45:54.48$vc4f8/vblo=6,752.99 2006.245.07:45:54.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.07:45:54.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.07:45:54.48#ibcon#ireg 17 cls_cnt 0 2006.245.07:45:54.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:54.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:54.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:54.48#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:45:54.48#ibcon#first serial, iclass 6, count 0 2006.245.07:45:54.48#ibcon#enter sib2, iclass 6, count 0 2006.245.07:45:54.48#ibcon#flushed, iclass 6, count 0 2006.245.07:45:54.48#ibcon#about to write, iclass 6, count 0 2006.245.07:45:54.48#ibcon#wrote, iclass 6, count 0 2006.245.07:45:54.48#ibcon#about to read 3, iclass 6, count 0 2006.245.07:45:54.50#ibcon#read 3, iclass 6, count 0 2006.245.07:45:54.50#ibcon#about to read 4, iclass 6, count 0 2006.245.07:45:54.50#ibcon#read 4, iclass 6, count 0 2006.245.07:45:54.50#ibcon#about to read 5, iclass 6, count 0 2006.245.07:45:54.50#ibcon#read 5, iclass 6, count 0 2006.245.07:45:54.50#ibcon#about to read 6, iclass 6, count 0 2006.245.07:45:54.50#ibcon#read 6, iclass 6, count 0 2006.245.07:45:54.50#ibcon#end of sib2, iclass 6, count 0 2006.245.07:45:54.50#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:45:54.50#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:45:54.50#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:45:54.50#ibcon#*before write, iclass 6, count 0 2006.245.07:45:54.50#ibcon#enter sib2, iclass 6, count 0 2006.245.07:45:54.50#ibcon#flushed, iclass 6, count 0 2006.245.07:45:54.50#ibcon#about to write, iclass 6, count 0 2006.245.07:45:54.50#ibcon#wrote, iclass 6, count 0 2006.245.07:45:54.50#ibcon#about to read 3, iclass 6, count 0 2006.245.07:45:54.54#ibcon#read 3, iclass 6, count 0 2006.245.07:45:54.54#ibcon#about to read 4, iclass 6, count 0 2006.245.07:45:54.54#ibcon#read 4, iclass 6, count 0 2006.245.07:45:54.54#ibcon#about to read 5, iclass 6, count 0 2006.245.07:45:54.54#ibcon#read 5, iclass 6, count 0 2006.245.07:45:54.54#ibcon#about to read 6, iclass 6, count 0 2006.245.07:45:54.54#ibcon#read 6, iclass 6, count 0 2006.245.07:45:54.54#ibcon#end of sib2, iclass 6, count 0 2006.245.07:45:54.54#ibcon#*after write, iclass 6, count 0 2006.245.07:45:54.54#ibcon#*before return 0, iclass 6, count 0 2006.245.07:45:54.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:54.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:45:54.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:45:54.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:45:54.54$vc4f8/vb=6,3 2006.245.07:45:54.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.07:45:54.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.07:45:54.54#ibcon#ireg 11 cls_cnt 2 2006.245.07:45:54.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:54.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:54.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:54.60#ibcon#enter wrdev, iclass 10, count 2 2006.245.07:45:54.60#ibcon#first serial, iclass 10, count 2 2006.245.07:45:54.60#ibcon#enter sib2, iclass 10, count 2 2006.245.07:45:54.60#ibcon#flushed, iclass 10, count 2 2006.245.07:45:54.60#ibcon#about to write, iclass 10, count 2 2006.245.07:45:54.60#ibcon#wrote, iclass 10, count 2 2006.245.07:45:54.60#ibcon#about to read 3, iclass 10, count 2 2006.245.07:45:54.62#ibcon#read 3, iclass 10, count 2 2006.245.07:45:54.62#ibcon#about to read 4, iclass 10, count 2 2006.245.07:45:54.62#ibcon#read 4, iclass 10, count 2 2006.245.07:45:54.62#ibcon#about to read 5, iclass 10, count 2 2006.245.07:45:54.62#ibcon#read 5, iclass 10, count 2 2006.245.07:45:54.62#ibcon#about to read 6, iclass 10, count 2 2006.245.07:45:54.62#ibcon#read 6, iclass 10, count 2 2006.245.07:45:54.62#ibcon#end of sib2, iclass 10, count 2 2006.245.07:45:54.62#ibcon#*mode == 0, iclass 10, count 2 2006.245.07:45:54.62#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.07:45:54.62#ibcon#[27=AT06-03\r\n] 2006.245.07:45:54.62#ibcon#*before write, iclass 10, count 2 2006.245.07:45:54.62#ibcon#enter sib2, iclass 10, count 2 2006.245.07:45:54.62#ibcon#flushed, iclass 10, count 2 2006.245.07:45:54.62#ibcon#about to write, iclass 10, count 2 2006.245.07:45:54.62#ibcon#wrote, iclass 10, count 2 2006.245.07:45:54.62#ibcon#about to read 3, iclass 10, count 2 2006.245.07:45:54.65#ibcon#read 3, iclass 10, count 2 2006.245.07:45:54.65#ibcon#about to read 4, iclass 10, count 2 2006.245.07:45:54.65#ibcon#read 4, iclass 10, count 2 2006.245.07:45:54.65#ibcon#about to read 5, iclass 10, count 2 2006.245.07:45:54.65#ibcon#read 5, iclass 10, count 2 2006.245.07:45:54.65#ibcon#about to read 6, iclass 10, count 2 2006.245.07:45:54.65#ibcon#read 6, iclass 10, count 2 2006.245.07:45:54.65#ibcon#end of sib2, iclass 10, count 2 2006.245.07:45:54.65#ibcon#*after write, iclass 10, count 2 2006.245.07:45:54.65#ibcon#*before return 0, iclass 10, count 2 2006.245.07:45:54.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:54.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:45:54.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.07:45:54.65#ibcon#ireg 7 cls_cnt 0 2006.245.07:45:54.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:54.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:54.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:54.77#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:45:54.77#ibcon#first serial, iclass 10, count 0 2006.245.07:45:54.77#ibcon#enter sib2, iclass 10, count 0 2006.245.07:45:54.77#ibcon#flushed, iclass 10, count 0 2006.245.07:45:54.77#ibcon#about to write, iclass 10, count 0 2006.245.07:45:54.77#ibcon#wrote, iclass 10, count 0 2006.245.07:45:54.77#ibcon#about to read 3, iclass 10, count 0 2006.245.07:45:54.79#ibcon#read 3, iclass 10, count 0 2006.245.07:45:54.79#ibcon#about to read 4, iclass 10, count 0 2006.245.07:45:54.79#ibcon#read 4, iclass 10, count 0 2006.245.07:45:54.79#ibcon#about to read 5, iclass 10, count 0 2006.245.07:45:54.79#ibcon#read 5, iclass 10, count 0 2006.245.07:45:54.79#ibcon#about to read 6, iclass 10, count 0 2006.245.07:45:54.79#ibcon#read 6, iclass 10, count 0 2006.245.07:45:54.79#ibcon#end of sib2, iclass 10, count 0 2006.245.07:45:54.79#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:45:54.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:45:54.79#ibcon#[27=USB\r\n] 2006.245.07:45:54.79#ibcon#*before write, iclass 10, count 0 2006.245.07:45:54.79#ibcon#enter sib2, iclass 10, count 0 2006.245.07:45:54.79#ibcon#flushed, iclass 10, count 0 2006.245.07:45:54.79#ibcon#about to write, iclass 10, count 0 2006.245.07:45:54.79#ibcon#wrote, iclass 10, count 0 2006.245.07:45:54.79#ibcon#about to read 3, iclass 10, count 0 2006.245.07:45:54.82#ibcon#read 3, iclass 10, count 0 2006.245.07:45:54.82#ibcon#about to read 4, iclass 10, count 0 2006.245.07:45:54.82#ibcon#read 4, iclass 10, count 0 2006.245.07:45:54.82#ibcon#about to read 5, iclass 10, count 0 2006.245.07:45:54.82#ibcon#read 5, iclass 10, count 0 2006.245.07:45:54.82#ibcon#about to read 6, iclass 10, count 0 2006.245.07:45:54.82#ibcon#read 6, iclass 10, count 0 2006.245.07:45:54.82#ibcon#end of sib2, iclass 10, count 0 2006.245.07:45:54.82#ibcon#*after write, iclass 10, count 0 2006.245.07:45:54.82#ibcon#*before return 0, iclass 10, count 0 2006.245.07:45:54.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:54.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:45:54.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:45:54.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:45:54.82$vc4f8/vabw=wide 2006.245.07:45:54.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.07:45:54.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.07:45:54.82#ibcon#ireg 8 cls_cnt 0 2006.245.07:45:54.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:54.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:54.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:54.82#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:45:54.82#ibcon#first serial, iclass 12, count 0 2006.245.07:45:54.82#ibcon#enter sib2, iclass 12, count 0 2006.245.07:45:54.82#ibcon#flushed, iclass 12, count 0 2006.245.07:45:54.82#ibcon#about to write, iclass 12, count 0 2006.245.07:45:54.82#ibcon#wrote, iclass 12, count 0 2006.245.07:45:54.82#ibcon#about to read 3, iclass 12, count 0 2006.245.07:45:54.84#ibcon#read 3, iclass 12, count 0 2006.245.07:45:54.84#ibcon#about to read 4, iclass 12, count 0 2006.245.07:45:54.84#ibcon#read 4, iclass 12, count 0 2006.245.07:45:54.84#ibcon#about to read 5, iclass 12, count 0 2006.245.07:45:54.84#ibcon#read 5, iclass 12, count 0 2006.245.07:45:54.84#ibcon#about to read 6, iclass 12, count 0 2006.245.07:45:54.84#ibcon#read 6, iclass 12, count 0 2006.245.07:45:54.84#ibcon#end of sib2, iclass 12, count 0 2006.245.07:45:54.84#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:45:54.84#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:45:54.84#ibcon#[25=BW32\r\n] 2006.245.07:45:54.84#ibcon#*before write, iclass 12, count 0 2006.245.07:45:54.84#ibcon#enter sib2, iclass 12, count 0 2006.245.07:45:54.84#ibcon#flushed, iclass 12, count 0 2006.245.07:45:54.84#ibcon#about to write, iclass 12, count 0 2006.245.07:45:54.84#ibcon#wrote, iclass 12, count 0 2006.245.07:45:54.84#ibcon#about to read 3, iclass 12, count 0 2006.245.07:45:54.87#ibcon#read 3, iclass 12, count 0 2006.245.07:45:54.87#ibcon#about to read 4, iclass 12, count 0 2006.245.07:45:54.87#ibcon#read 4, iclass 12, count 0 2006.245.07:45:54.87#ibcon#about to read 5, iclass 12, count 0 2006.245.07:45:54.87#ibcon#read 5, iclass 12, count 0 2006.245.07:45:54.87#ibcon#about to read 6, iclass 12, count 0 2006.245.07:45:54.87#ibcon#read 6, iclass 12, count 0 2006.245.07:45:54.87#ibcon#end of sib2, iclass 12, count 0 2006.245.07:45:54.87#ibcon#*after write, iclass 12, count 0 2006.245.07:45:54.87#ibcon#*before return 0, iclass 12, count 0 2006.245.07:45:54.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:54.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:45:54.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:45:54.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:45:54.87$vc4f8/vbbw=wide 2006.245.07:45:54.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:45:54.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:45:54.87#ibcon#ireg 8 cls_cnt 0 2006.245.07:45:54.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:45:54.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:45:54.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:45:54.94#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:45:54.94#ibcon#first serial, iclass 14, count 0 2006.245.07:45:54.94#ibcon#enter sib2, iclass 14, count 0 2006.245.07:45:54.94#ibcon#flushed, iclass 14, count 0 2006.245.07:45:54.94#ibcon#about to write, iclass 14, count 0 2006.245.07:45:54.94#ibcon#wrote, iclass 14, count 0 2006.245.07:45:54.94#ibcon#about to read 3, iclass 14, count 0 2006.245.07:45:54.96#ibcon#read 3, iclass 14, count 0 2006.245.07:45:54.96#ibcon#about to read 4, iclass 14, count 0 2006.245.07:45:54.96#ibcon#read 4, iclass 14, count 0 2006.245.07:45:54.96#ibcon#about to read 5, iclass 14, count 0 2006.245.07:45:54.96#ibcon#read 5, iclass 14, count 0 2006.245.07:45:54.96#ibcon#about to read 6, iclass 14, count 0 2006.245.07:45:54.96#ibcon#read 6, iclass 14, count 0 2006.245.07:45:54.96#ibcon#end of sib2, iclass 14, count 0 2006.245.07:45:54.96#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:45:54.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:45:54.96#ibcon#[27=BW32\r\n] 2006.245.07:45:54.96#ibcon#*before write, iclass 14, count 0 2006.245.07:45:54.96#ibcon#enter sib2, iclass 14, count 0 2006.245.07:45:54.96#ibcon#flushed, iclass 14, count 0 2006.245.07:45:54.96#ibcon#about to write, iclass 14, count 0 2006.245.07:45:54.96#ibcon#wrote, iclass 14, count 0 2006.245.07:45:54.96#ibcon#about to read 3, iclass 14, count 0 2006.245.07:45:54.99#ibcon#read 3, iclass 14, count 0 2006.245.07:45:54.99#ibcon#about to read 4, iclass 14, count 0 2006.245.07:45:54.99#ibcon#read 4, iclass 14, count 0 2006.245.07:45:54.99#ibcon#about to read 5, iclass 14, count 0 2006.245.07:45:54.99#ibcon#read 5, iclass 14, count 0 2006.245.07:45:54.99#ibcon#about to read 6, iclass 14, count 0 2006.245.07:45:54.99#ibcon#read 6, iclass 14, count 0 2006.245.07:45:54.99#ibcon#end of sib2, iclass 14, count 0 2006.245.07:45:54.99#ibcon#*after write, iclass 14, count 0 2006.245.07:45:54.99#ibcon#*before return 0, iclass 14, count 0 2006.245.07:45:54.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:45:54.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:45:54.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:45:54.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:45:54.99$4f8m12a/ifd4f 2006.245.07:45:54.99$ifd4f/lo= 2006.245.07:45:54.99$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:45:54.99$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:45:54.99$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:45:54.99$ifd4f/patch= 2006.245.07:45:54.99$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:45:54.99$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:45:54.99$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:45:54.99$4f8m12a/"form=m,16.000,1:2 2006.245.07:45:54.99$4f8m12a/"tpicd 2006.245.07:45:54.99$4f8m12a/echo=off 2006.245.07:45:54.99$4f8m12a/xlog=off 2006.245.07:45:54.99:!2006.245.07:46:20 2006.245.07:46:04.14#trakl#Source acquired 2006.245.07:46:05.14#flagr#flagr/antenna,acquired 2006.245.07:46:20.00:preob 2006.245.07:46:21.14/onsource/TRACKING 2006.245.07:46:21.14:!2006.245.07:46:30 2006.245.07:46:30.00:data_valid=on 2006.245.07:46:30.00:midob 2006.245.07:46:30.14/onsource/TRACKING 2006.245.07:46:30.14/wx/27.39,1004.5,67 2006.245.07:46:30.21/cable/+6.4113E-03 2006.245.07:46:31.30/va/01,08,usb,yes,31,32 2006.245.07:46:31.30/va/02,07,usb,yes,31,32 2006.245.07:46:31.30/va/03,06,usb,yes,33,33 2006.245.07:46:31.30/va/04,07,usb,yes,32,34 2006.245.07:46:31.30/va/05,07,usb,yes,33,35 2006.245.07:46:31.30/va/06,07,usb,yes,29,29 2006.245.07:46:31.30/va/07,07,usb,yes,29,28 2006.245.07:46:31.30/va/08,08,usb,yes,25,24 2006.245.07:46:31.53/valo/01,532.99,yes,locked 2006.245.07:46:31.53/valo/02,572.99,yes,locked 2006.245.07:46:31.53/valo/03,672.99,yes,locked 2006.245.07:46:31.53/valo/04,832.99,yes,locked 2006.245.07:46:31.53/valo/05,652.99,yes,locked 2006.245.07:46:31.53/valo/06,772.99,yes,locked 2006.245.07:46:31.53/valo/07,832.99,yes,locked 2006.245.07:46:31.53/valo/08,852.99,yes,locked 2006.245.07:46:32.62/vb/01,04,usb,yes,30,29 2006.245.07:46:32.62/vb/02,04,usb,yes,32,34 2006.245.07:46:32.62/vb/03,04,usb,yes,28,32 2006.245.07:46:32.62/vb/04,04,usb,yes,29,29 2006.245.07:46:32.62/vb/05,03,usb,yes,35,39 2006.245.07:46:32.62/vb/06,03,usb,yes,35,39 2006.245.07:46:32.62/vb/07,04,usb,yes,31,31 2006.245.07:46:32.62/vb/08,03,usb,yes,35,39 2006.245.07:46:32.86/vblo/01,632.99,yes,locked 2006.245.07:46:32.86/vblo/02,640.99,yes,locked 2006.245.07:46:32.86/vblo/03,656.99,yes,locked 2006.245.07:46:32.86/vblo/04,712.99,yes,locked 2006.245.07:46:32.86/vblo/05,744.99,yes,locked 2006.245.07:46:32.86/vblo/06,752.99,yes,locked 2006.245.07:46:32.86/vblo/07,734.99,yes,locked 2006.245.07:46:32.86/vblo/08,744.99,yes,locked 2006.245.07:46:33.01/vabw/8 2006.245.07:46:33.16/vbbw/8 2006.245.07:46:33.25/xfe/off,on,13.5 2006.245.07:46:33.63/ifatt/23,28,28,28 2006.245.07:46:34.08/fmout-gps/S +4.41E-07 2006.245.07:46:34.12:!2006.245.07:47:30 2006.245.07:47:30.00:data_valid=off 2006.245.07:47:30.00:postob 2006.245.07:47:30.18/cable/+6.4096E-03 2006.245.07:47:30.18/wx/27.38,1004.5,69 2006.245.07:47:31.08/fmout-gps/S +4.41E-07 2006.245.07:47:31.08:scan_name=245-0748,k06245,80 2006.245.07:47:31.08:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.245.07:47:31.13#flagr#flagr/antenna,new-source 2006.245.07:47:32.13:checkk5 2006.245.07:47:32.55/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:47:33.00/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:47:33.43/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:47:33.87/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:47:34.28/chk_obsdata//k5ts1/T2450746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:47:34.91/chk_obsdata//k5ts2/T2450746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:47:35.35/chk_obsdata//k5ts3/T2450746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:47:35.79/chk_obsdata//k5ts4/T2450746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:47:36.58/k5log//k5ts1_log_newline 2006.245.07:47:37.90/k5log//k5ts2_log_newline 2006.245.07:47:38.98/k5log//k5ts3_log_newline 2006.245.07:47:39.75/k5log//k5ts4_log_newline 2006.245.07:47:39.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:47:39.77:4f8m12a=1 2006.245.07:47:39.77$4f8m12a/echo=on 2006.245.07:47:39.77$4f8m12a/pcalon 2006.245.07:47:39.77$pcalon/"no phase cal control is implemented here 2006.245.07:47:39.77$4f8m12a/"tpicd=stop 2006.245.07:47:39.77$4f8m12a/vc4f8 2006.245.07:47:39.77$vc4f8/valo=1,532.99 2006.245.07:47:39.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.07:47:39.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.07:47:39.78#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:39.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:39.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:39.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:39.78#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:47:39.78#ibcon#first serial, iclass 21, count 0 2006.245.07:47:39.78#ibcon#enter sib2, iclass 21, count 0 2006.245.07:47:39.78#ibcon#flushed, iclass 21, count 0 2006.245.07:47:39.78#ibcon#about to write, iclass 21, count 0 2006.245.07:47:39.78#ibcon#wrote, iclass 21, count 0 2006.245.07:47:39.78#ibcon#about to read 3, iclass 21, count 0 2006.245.07:47:39.81#ibcon#read 3, iclass 21, count 0 2006.245.07:47:39.81#ibcon#about to read 4, iclass 21, count 0 2006.245.07:47:39.81#ibcon#read 4, iclass 21, count 0 2006.245.07:47:39.81#ibcon#about to read 5, iclass 21, count 0 2006.245.07:47:39.81#ibcon#read 5, iclass 21, count 0 2006.245.07:47:39.81#ibcon#about to read 6, iclass 21, count 0 2006.245.07:47:39.81#ibcon#read 6, iclass 21, count 0 2006.245.07:47:39.81#ibcon#end of sib2, iclass 21, count 0 2006.245.07:47:39.81#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:47:39.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:47:39.81#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:47:39.81#ibcon#*before write, iclass 21, count 0 2006.245.07:47:39.81#ibcon#enter sib2, iclass 21, count 0 2006.245.07:47:39.81#ibcon#flushed, iclass 21, count 0 2006.245.07:47:39.81#ibcon#about to write, iclass 21, count 0 2006.245.07:47:39.81#ibcon#wrote, iclass 21, count 0 2006.245.07:47:39.81#ibcon#about to read 3, iclass 21, count 0 2006.245.07:47:39.87#ibcon#read 3, iclass 21, count 0 2006.245.07:47:39.87#ibcon#about to read 4, iclass 21, count 0 2006.245.07:47:39.87#ibcon#read 4, iclass 21, count 0 2006.245.07:47:39.87#ibcon#about to read 5, iclass 21, count 0 2006.245.07:47:39.87#ibcon#read 5, iclass 21, count 0 2006.245.07:47:39.87#ibcon#about to read 6, iclass 21, count 0 2006.245.07:47:39.87#ibcon#read 6, iclass 21, count 0 2006.245.07:47:39.87#ibcon#end of sib2, iclass 21, count 0 2006.245.07:47:39.87#ibcon#*after write, iclass 21, count 0 2006.245.07:47:39.87#ibcon#*before return 0, iclass 21, count 0 2006.245.07:47:39.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:39.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:39.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:47:39.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:47:39.87$vc4f8/va=1,8 2006.245.07:47:39.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.07:47:39.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.07:47:39.87#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:39.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:39.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:39.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:39.87#ibcon#enter wrdev, iclass 23, count 2 2006.245.07:47:39.87#ibcon#first serial, iclass 23, count 2 2006.245.07:47:39.87#ibcon#enter sib2, iclass 23, count 2 2006.245.07:47:39.87#ibcon#flushed, iclass 23, count 2 2006.245.07:47:39.87#ibcon#about to write, iclass 23, count 2 2006.245.07:47:39.87#ibcon#wrote, iclass 23, count 2 2006.245.07:47:39.87#ibcon#about to read 3, iclass 23, count 2 2006.245.07:47:39.89#ibcon#read 3, iclass 23, count 2 2006.245.07:47:39.89#ibcon#about to read 4, iclass 23, count 2 2006.245.07:47:39.89#ibcon#read 4, iclass 23, count 2 2006.245.07:47:39.89#ibcon#about to read 5, iclass 23, count 2 2006.245.07:47:39.89#ibcon#read 5, iclass 23, count 2 2006.245.07:47:39.89#ibcon#about to read 6, iclass 23, count 2 2006.245.07:47:39.89#ibcon#read 6, iclass 23, count 2 2006.245.07:47:39.89#ibcon#end of sib2, iclass 23, count 2 2006.245.07:47:39.89#ibcon#*mode == 0, iclass 23, count 2 2006.245.07:47:39.89#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.07:47:39.89#ibcon#[25=AT01-08\r\n] 2006.245.07:47:39.89#ibcon#*before write, iclass 23, count 2 2006.245.07:47:39.89#ibcon#enter sib2, iclass 23, count 2 2006.245.07:47:39.89#ibcon#flushed, iclass 23, count 2 2006.245.07:47:39.89#ibcon#about to write, iclass 23, count 2 2006.245.07:47:39.89#ibcon#wrote, iclass 23, count 2 2006.245.07:47:39.89#ibcon#about to read 3, iclass 23, count 2 2006.245.07:47:39.93#ibcon#read 3, iclass 23, count 2 2006.245.07:47:39.93#ibcon#about to read 4, iclass 23, count 2 2006.245.07:47:39.93#ibcon#read 4, iclass 23, count 2 2006.245.07:47:39.93#ibcon#about to read 5, iclass 23, count 2 2006.245.07:47:39.93#ibcon#read 5, iclass 23, count 2 2006.245.07:47:39.93#ibcon#about to read 6, iclass 23, count 2 2006.245.07:47:39.93#ibcon#read 6, iclass 23, count 2 2006.245.07:47:39.93#ibcon#end of sib2, iclass 23, count 2 2006.245.07:47:39.93#ibcon#*after write, iclass 23, count 2 2006.245.07:47:39.93#ibcon#*before return 0, iclass 23, count 2 2006.245.07:47:39.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:39.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:39.93#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.07:47:39.93#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:39.93#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:40.05#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:40.05#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:40.05#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:47:40.05#ibcon#first serial, iclass 23, count 0 2006.245.07:47:40.05#ibcon#enter sib2, iclass 23, count 0 2006.245.07:47:40.05#ibcon#flushed, iclass 23, count 0 2006.245.07:47:40.05#ibcon#about to write, iclass 23, count 0 2006.245.07:47:40.05#ibcon#wrote, iclass 23, count 0 2006.245.07:47:40.05#ibcon#about to read 3, iclass 23, count 0 2006.245.07:47:40.08#ibcon#read 3, iclass 23, count 0 2006.245.07:47:40.08#ibcon#about to read 4, iclass 23, count 0 2006.245.07:47:40.08#ibcon#read 4, iclass 23, count 0 2006.245.07:47:40.08#ibcon#about to read 5, iclass 23, count 0 2006.245.07:47:40.08#ibcon#read 5, iclass 23, count 0 2006.245.07:47:40.08#ibcon#about to read 6, iclass 23, count 0 2006.245.07:47:40.08#ibcon#read 6, iclass 23, count 0 2006.245.07:47:40.08#ibcon#end of sib2, iclass 23, count 0 2006.245.07:47:40.08#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:47:40.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:47:40.08#ibcon#[25=USB\r\n] 2006.245.07:47:40.08#ibcon#*before write, iclass 23, count 0 2006.245.07:47:40.08#ibcon#enter sib2, iclass 23, count 0 2006.245.07:47:40.08#ibcon#flushed, iclass 23, count 0 2006.245.07:47:40.08#ibcon#about to write, iclass 23, count 0 2006.245.07:47:40.08#ibcon#wrote, iclass 23, count 0 2006.245.07:47:40.08#ibcon#about to read 3, iclass 23, count 0 2006.245.07:47:40.11#ibcon#read 3, iclass 23, count 0 2006.245.07:47:40.11#ibcon#about to read 4, iclass 23, count 0 2006.245.07:47:40.11#ibcon#read 4, iclass 23, count 0 2006.245.07:47:40.11#ibcon#about to read 5, iclass 23, count 0 2006.245.07:47:40.11#ibcon#read 5, iclass 23, count 0 2006.245.07:47:40.11#ibcon#about to read 6, iclass 23, count 0 2006.245.07:47:40.11#ibcon#read 6, iclass 23, count 0 2006.245.07:47:40.11#ibcon#end of sib2, iclass 23, count 0 2006.245.07:47:40.11#ibcon#*after write, iclass 23, count 0 2006.245.07:47:40.11#ibcon#*before return 0, iclass 23, count 0 2006.245.07:47:40.11#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:40.11#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:40.11#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:47:40.11#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:47:40.11$vc4f8/valo=2,572.99 2006.245.07:47:40.11#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.07:47:40.11#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.07:47:40.11#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:40.11#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:40.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:40.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:40.11#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:47:40.11#ibcon#first serial, iclass 25, count 0 2006.245.07:47:40.11#ibcon#enter sib2, iclass 25, count 0 2006.245.07:47:40.11#ibcon#flushed, iclass 25, count 0 2006.245.07:47:40.11#ibcon#about to write, iclass 25, count 0 2006.245.07:47:40.11#ibcon#wrote, iclass 25, count 0 2006.245.07:47:40.11#ibcon#about to read 3, iclass 25, count 0 2006.245.07:47:40.13#ibcon#read 3, iclass 25, count 0 2006.245.07:47:40.13#ibcon#about to read 4, iclass 25, count 0 2006.245.07:47:40.13#ibcon#read 4, iclass 25, count 0 2006.245.07:47:40.13#ibcon#about to read 5, iclass 25, count 0 2006.245.07:47:40.13#ibcon#read 5, iclass 25, count 0 2006.245.07:47:40.13#ibcon#about to read 6, iclass 25, count 0 2006.245.07:47:40.13#ibcon#read 6, iclass 25, count 0 2006.245.07:47:40.13#ibcon#end of sib2, iclass 25, count 0 2006.245.07:47:40.13#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:47:40.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:47:40.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:47:40.13#ibcon#*before write, iclass 25, count 0 2006.245.07:47:40.13#ibcon#enter sib2, iclass 25, count 0 2006.245.07:47:40.13#ibcon#flushed, iclass 25, count 0 2006.245.07:47:40.13#ibcon#about to write, iclass 25, count 0 2006.245.07:47:40.13#ibcon#wrote, iclass 25, count 0 2006.245.07:47:40.13#ibcon#about to read 3, iclass 25, count 0 2006.245.07:47:40.17#ibcon#read 3, iclass 25, count 0 2006.245.07:47:40.17#ibcon#about to read 4, iclass 25, count 0 2006.245.07:47:40.17#ibcon#read 4, iclass 25, count 0 2006.245.07:47:40.17#ibcon#about to read 5, iclass 25, count 0 2006.245.07:47:40.17#ibcon#read 5, iclass 25, count 0 2006.245.07:47:40.17#ibcon#about to read 6, iclass 25, count 0 2006.245.07:47:40.17#ibcon#read 6, iclass 25, count 0 2006.245.07:47:40.17#ibcon#end of sib2, iclass 25, count 0 2006.245.07:47:40.17#ibcon#*after write, iclass 25, count 0 2006.245.07:47:40.17#ibcon#*before return 0, iclass 25, count 0 2006.245.07:47:40.17#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:40.17#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:40.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:47:40.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:47:40.17$vc4f8/va=2,7 2006.245.07:47:40.17#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.07:47:40.17#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.07:47:40.17#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:40.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:40.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:40.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:40.23#ibcon#enter wrdev, iclass 27, count 2 2006.245.07:47:40.23#ibcon#first serial, iclass 27, count 2 2006.245.07:47:40.23#ibcon#enter sib2, iclass 27, count 2 2006.245.07:47:40.23#ibcon#flushed, iclass 27, count 2 2006.245.07:47:40.23#ibcon#about to write, iclass 27, count 2 2006.245.07:47:40.23#ibcon#wrote, iclass 27, count 2 2006.245.07:47:40.23#ibcon#about to read 3, iclass 27, count 2 2006.245.07:47:40.25#ibcon#read 3, iclass 27, count 2 2006.245.07:47:40.25#ibcon#about to read 4, iclass 27, count 2 2006.245.07:47:40.25#ibcon#read 4, iclass 27, count 2 2006.245.07:47:40.25#ibcon#about to read 5, iclass 27, count 2 2006.245.07:47:40.25#ibcon#read 5, iclass 27, count 2 2006.245.07:47:40.25#ibcon#about to read 6, iclass 27, count 2 2006.245.07:47:40.25#ibcon#read 6, iclass 27, count 2 2006.245.07:47:40.25#ibcon#end of sib2, iclass 27, count 2 2006.245.07:47:40.25#ibcon#*mode == 0, iclass 27, count 2 2006.245.07:47:40.25#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.07:47:40.25#ibcon#[25=AT02-07\r\n] 2006.245.07:47:40.25#ibcon#*before write, iclass 27, count 2 2006.245.07:47:40.25#ibcon#enter sib2, iclass 27, count 2 2006.245.07:47:40.25#ibcon#flushed, iclass 27, count 2 2006.245.07:47:40.25#ibcon#about to write, iclass 27, count 2 2006.245.07:47:40.25#ibcon#wrote, iclass 27, count 2 2006.245.07:47:40.25#ibcon#about to read 3, iclass 27, count 2 2006.245.07:47:40.28#ibcon#read 3, iclass 27, count 2 2006.245.07:47:40.28#ibcon#about to read 4, iclass 27, count 2 2006.245.07:47:40.28#ibcon#read 4, iclass 27, count 2 2006.245.07:47:40.28#ibcon#about to read 5, iclass 27, count 2 2006.245.07:47:40.28#ibcon#read 5, iclass 27, count 2 2006.245.07:47:40.28#ibcon#about to read 6, iclass 27, count 2 2006.245.07:47:40.28#ibcon#read 6, iclass 27, count 2 2006.245.07:47:40.28#ibcon#end of sib2, iclass 27, count 2 2006.245.07:47:40.28#ibcon#*after write, iclass 27, count 2 2006.245.07:47:40.28#ibcon#*before return 0, iclass 27, count 2 2006.245.07:47:40.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:40.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:40.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.07:47:40.28#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:40.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:40.34#abcon#<5=/05 3.4 5.6 27.37 691004.5\r\n> 2006.245.07:47:40.36#abcon#{5=INTERFACE CLEAR} 2006.245.07:47:40.40#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:40.40#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:40.40#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:47:40.40#ibcon#first serial, iclass 27, count 0 2006.245.07:47:40.40#ibcon#enter sib2, iclass 27, count 0 2006.245.07:47:40.40#ibcon#flushed, iclass 27, count 0 2006.245.07:47:40.40#ibcon#about to write, iclass 27, count 0 2006.245.07:47:40.40#ibcon#wrote, iclass 27, count 0 2006.245.07:47:40.40#ibcon#about to read 3, iclass 27, count 0 2006.245.07:47:40.42#ibcon#read 3, iclass 27, count 0 2006.245.07:47:40.42#ibcon#about to read 4, iclass 27, count 0 2006.245.07:47:40.42#ibcon#read 4, iclass 27, count 0 2006.245.07:47:40.42#ibcon#about to read 5, iclass 27, count 0 2006.245.07:47:40.42#ibcon#read 5, iclass 27, count 0 2006.245.07:47:40.42#ibcon#about to read 6, iclass 27, count 0 2006.245.07:47:40.42#ibcon#read 6, iclass 27, count 0 2006.245.07:47:40.42#ibcon#end of sib2, iclass 27, count 0 2006.245.07:47:40.42#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:47:40.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:47:40.42#ibcon#[25=USB\r\n] 2006.245.07:47:40.42#ibcon#*before write, iclass 27, count 0 2006.245.07:47:40.42#ibcon#enter sib2, iclass 27, count 0 2006.245.07:47:40.42#ibcon#flushed, iclass 27, count 0 2006.245.07:47:40.42#ibcon#about to write, iclass 27, count 0 2006.245.07:47:40.42#ibcon#wrote, iclass 27, count 0 2006.245.07:47:40.42#ibcon#about to read 3, iclass 27, count 0 2006.245.07:47:40.42#abcon#[5=S1D000X0/0*\r\n] 2006.245.07:47:40.45#ibcon#read 3, iclass 27, count 0 2006.245.07:47:40.45#ibcon#about to read 4, iclass 27, count 0 2006.245.07:47:40.45#ibcon#read 4, iclass 27, count 0 2006.245.07:47:40.45#ibcon#about to read 5, iclass 27, count 0 2006.245.07:47:40.45#ibcon#read 5, iclass 27, count 0 2006.245.07:47:40.45#ibcon#about to read 6, iclass 27, count 0 2006.245.07:47:40.45#ibcon#read 6, iclass 27, count 0 2006.245.07:47:40.45#ibcon#end of sib2, iclass 27, count 0 2006.245.07:47:40.45#ibcon#*after write, iclass 27, count 0 2006.245.07:47:40.45#ibcon#*before return 0, iclass 27, count 0 2006.245.07:47:40.45#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:40.45#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:40.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:47:40.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:47:40.45$vc4f8/valo=3,672.99 2006.245.07:47:40.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.07:47:40.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.07:47:40.45#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:40.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:40.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:40.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:40.45#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:47:40.45#ibcon#first serial, iclass 33, count 0 2006.245.07:47:40.45#ibcon#enter sib2, iclass 33, count 0 2006.245.07:47:40.45#ibcon#flushed, iclass 33, count 0 2006.245.07:47:40.45#ibcon#about to write, iclass 33, count 0 2006.245.07:47:40.45#ibcon#wrote, iclass 33, count 0 2006.245.07:47:40.45#ibcon#about to read 3, iclass 33, count 0 2006.245.07:47:40.47#ibcon#read 3, iclass 33, count 0 2006.245.07:47:40.47#ibcon#about to read 4, iclass 33, count 0 2006.245.07:47:40.47#ibcon#read 4, iclass 33, count 0 2006.245.07:47:40.47#ibcon#about to read 5, iclass 33, count 0 2006.245.07:47:40.47#ibcon#read 5, iclass 33, count 0 2006.245.07:47:40.47#ibcon#about to read 6, iclass 33, count 0 2006.245.07:47:40.47#ibcon#read 6, iclass 33, count 0 2006.245.07:47:40.47#ibcon#end of sib2, iclass 33, count 0 2006.245.07:47:40.47#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:47:40.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:47:40.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:47:40.47#ibcon#*before write, iclass 33, count 0 2006.245.07:47:40.47#ibcon#enter sib2, iclass 33, count 0 2006.245.07:47:40.47#ibcon#flushed, iclass 33, count 0 2006.245.07:47:40.47#ibcon#about to write, iclass 33, count 0 2006.245.07:47:40.47#ibcon#wrote, iclass 33, count 0 2006.245.07:47:40.47#ibcon#about to read 3, iclass 33, count 0 2006.245.07:47:40.51#ibcon#read 3, iclass 33, count 0 2006.245.07:47:40.51#ibcon#about to read 4, iclass 33, count 0 2006.245.07:47:40.51#ibcon#read 4, iclass 33, count 0 2006.245.07:47:40.51#ibcon#about to read 5, iclass 33, count 0 2006.245.07:47:40.51#ibcon#read 5, iclass 33, count 0 2006.245.07:47:40.51#ibcon#about to read 6, iclass 33, count 0 2006.245.07:47:40.51#ibcon#read 6, iclass 33, count 0 2006.245.07:47:40.51#ibcon#end of sib2, iclass 33, count 0 2006.245.07:47:40.51#ibcon#*after write, iclass 33, count 0 2006.245.07:47:40.51#ibcon#*before return 0, iclass 33, count 0 2006.245.07:47:40.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:40.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:40.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:47:40.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:47:40.51$vc4f8/va=3,6 2006.245.07:47:40.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.07:47:40.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.07:47:40.51#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:40.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:40.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:40.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:40.57#ibcon#enter wrdev, iclass 35, count 2 2006.245.07:47:40.57#ibcon#first serial, iclass 35, count 2 2006.245.07:47:40.57#ibcon#enter sib2, iclass 35, count 2 2006.245.07:47:40.57#ibcon#flushed, iclass 35, count 2 2006.245.07:47:40.57#ibcon#about to write, iclass 35, count 2 2006.245.07:47:40.57#ibcon#wrote, iclass 35, count 2 2006.245.07:47:40.57#ibcon#about to read 3, iclass 35, count 2 2006.245.07:47:40.59#ibcon#read 3, iclass 35, count 2 2006.245.07:47:40.59#ibcon#about to read 4, iclass 35, count 2 2006.245.07:47:40.59#ibcon#read 4, iclass 35, count 2 2006.245.07:47:40.59#ibcon#about to read 5, iclass 35, count 2 2006.245.07:47:40.59#ibcon#read 5, iclass 35, count 2 2006.245.07:47:40.59#ibcon#about to read 6, iclass 35, count 2 2006.245.07:47:40.59#ibcon#read 6, iclass 35, count 2 2006.245.07:47:40.59#ibcon#end of sib2, iclass 35, count 2 2006.245.07:47:40.59#ibcon#*mode == 0, iclass 35, count 2 2006.245.07:47:40.59#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.07:47:40.59#ibcon#[25=AT03-06\r\n] 2006.245.07:47:40.59#ibcon#*before write, iclass 35, count 2 2006.245.07:47:40.59#ibcon#enter sib2, iclass 35, count 2 2006.245.07:47:40.59#ibcon#flushed, iclass 35, count 2 2006.245.07:47:40.59#ibcon#about to write, iclass 35, count 2 2006.245.07:47:40.59#ibcon#wrote, iclass 35, count 2 2006.245.07:47:40.59#ibcon#about to read 3, iclass 35, count 2 2006.245.07:47:40.62#ibcon#read 3, iclass 35, count 2 2006.245.07:47:40.62#ibcon#about to read 4, iclass 35, count 2 2006.245.07:47:40.62#ibcon#read 4, iclass 35, count 2 2006.245.07:47:40.62#ibcon#about to read 5, iclass 35, count 2 2006.245.07:47:40.62#ibcon#read 5, iclass 35, count 2 2006.245.07:47:40.62#ibcon#about to read 6, iclass 35, count 2 2006.245.07:47:40.62#ibcon#read 6, iclass 35, count 2 2006.245.07:47:40.62#ibcon#end of sib2, iclass 35, count 2 2006.245.07:47:40.62#ibcon#*after write, iclass 35, count 2 2006.245.07:47:40.62#ibcon#*before return 0, iclass 35, count 2 2006.245.07:47:40.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:40.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:40.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.07:47:40.62#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:40.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:40.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:40.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:40.74#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:47:40.74#ibcon#first serial, iclass 35, count 0 2006.245.07:47:40.74#ibcon#enter sib2, iclass 35, count 0 2006.245.07:47:40.74#ibcon#flushed, iclass 35, count 0 2006.245.07:47:40.74#ibcon#about to write, iclass 35, count 0 2006.245.07:47:40.74#ibcon#wrote, iclass 35, count 0 2006.245.07:47:40.74#ibcon#about to read 3, iclass 35, count 0 2006.245.07:47:40.76#ibcon#read 3, iclass 35, count 0 2006.245.07:47:40.76#ibcon#about to read 4, iclass 35, count 0 2006.245.07:47:40.76#ibcon#read 4, iclass 35, count 0 2006.245.07:47:40.76#ibcon#about to read 5, iclass 35, count 0 2006.245.07:47:40.76#ibcon#read 5, iclass 35, count 0 2006.245.07:47:40.76#ibcon#about to read 6, iclass 35, count 0 2006.245.07:47:40.76#ibcon#read 6, iclass 35, count 0 2006.245.07:47:40.76#ibcon#end of sib2, iclass 35, count 0 2006.245.07:47:40.76#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:47:40.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:47:40.76#ibcon#[25=USB\r\n] 2006.245.07:47:40.76#ibcon#*before write, iclass 35, count 0 2006.245.07:47:40.76#ibcon#enter sib2, iclass 35, count 0 2006.245.07:47:40.76#ibcon#flushed, iclass 35, count 0 2006.245.07:47:40.76#ibcon#about to write, iclass 35, count 0 2006.245.07:47:40.76#ibcon#wrote, iclass 35, count 0 2006.245.07:47:40.76#ibcon#about to read 3, iclass 35, count 0 2006.245.07:47:40.79#ibcon#read 3, iclass 35, count 0 2006.245.07:47:40.79#ibcon#about to read 4, iclass 35, count 0 2006.245.07:47:40.79#ibcon#read 4, iclass 35, count 0 2006.245.07:47:40.79#ibcon#about to read 5, iclass 35, count 0 2006.245.07:47:40.79#ibcon#read 5, iclass 35, count 0 2006.245.07:47:40.79#ibcon#about to read 6, iclass 35, count 0 2006.245.07:47:40.79#ibcon#read 6, iclass 35, count 0 2006.245.07:47:40.79#ibcon#end of sib2, iclass 35, count 0 2006.245.07:47:40.79#ibcon#*after write, iclass 35, count 0 2006.245.07:47:40.79#ibcon#*before return 0, iclass 35, count 0 2006.245.07:47:40.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:40.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:40.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:47:40.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:47:40.79$vc4f8/valo=4,832.99 2006.245.07:47:40.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.07:47:40.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.07:47:40.79#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:40.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:40.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:40.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:40.79#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:47:40.79#ibcon#first serial, iclass 37, count 0 2006.245.07:47:40.79#ibcon#enter sib2, iclass 37, count 0 2006.245.07:47:40.79#ibcon#flushed, iclass 37, count 0 2006.245.07:47:40.79#ibcon#about to write, iclass 37, count 0 2006.245.07:47:40.79#ibcon#wrote, iclass 37, count 0 2006.245.07:47:40.79#ibcon#about to read 3, iclass 37, count 0 2006.245.07:47:40.81#ibcon#read 3, iclass 37, count 0 2006.245.07:47:40.81#ibcon#about to read 4, iclass 37, count 0 2006.245.07:47:40.81#ibcon#read 4, iclass 37, count 0 2006.245.07:47:40.81#ibcon#about to read 5, iclass 37, count 0 2006.245.07:47:40.81#ibcon#read 5, iclass 37, count 0 2006.245.07:47:40.81#ibcon#about to read 6, iclass 37, count 0 2006.245.07:47:40.81#ibcon#read 6, iclass 37, count 0 2006.245.07:47:40.81#ibcon#end of sib2, iclass 37, count 0 2006.245.07:47:40.81#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:47:40.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:47:40.81#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:47:40.81#ibcon#*before write, iclass 37, count 0 2006.245.07:47:40.81#ibcon#enter sib2, iclass 37, count 0 2006.245.07:47:40.81#ibcon#flushed, iclass 37, count 0 2006.245.07:47:40.81#ibcon#about to write, iclass 37, count 0 2006.245.07:47:40.81#ibcon#wrote, iclass 37, count 0 2006.245.07:47:40.81#ibcon#about to read 3, iclass 37, count 0 2006.245.07:47:40.85#ibcon#read 3, iclass 37, count 0 2006.245.07:47:40.85#ibcon#about to read 4, iclass 37, count 0 2006.245.07:47:40.85#ibcon#read 4, iclass 37, count 0 2006.245.07:47:40.85#ibcon#about to read 5, iclass 37, count 0 2006.245.07:47:40.85#ibcon#read 5, iclass 37, count 0 2006.245.07:47:40.85#ibcon#about to read 6, iclass 37, count 0 2006.245.07:47:40.85#ibcon#read 6, iclass 37, count 0 2006.245.07:47:40.85#ibcon#end of sib2, iclass 37, count 0 2006.245.07:47:40.85#ibcon#*after write, iclass 37, count 0 2006.245.07:47:40.85#ibcon#*before return 0, iclass 37, count 0 2006.245.07:47:40.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:40.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:40.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:47:40.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:47:40.85$vc4f8/va=4,7 2006.245.07:47:40.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.07:47:40.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.07:47:40.85#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:40.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:40.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:40.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:40.91#ibcon#enter wrdev, iclass 39, count 2 2006.245.07:47:40.91#ibcon#first serial, iclass 39, count 2 2006.245.07:47:40.91#ibcon#enter sib2, iclass 39, count 2 2006.245.07:47:40.91#ibcon#flushed, iclass 39, count 2 2006.245.07:47:40.91#ibcon#about to write, iclass 39, count 2 2006.245.07:47:40.91#ibcon#wrote, iclass 39, count 2 2006.245.07:47:40.91#ibcon#about to read 3, iclass 39, count 2 2006.245.07:47:40.93#ibcon#read 3, iclass 39, count 2 2006.245.07:47:40.93#ibcon#about to read 4, iclass 39, count 2 2006.245.07:47:40.93#ibcon#read 4, iclass 39, count 2 2006.245.07:47:40.93#ibcon#about to read 5, iclass 39, count 2 2006.245.07:47:40.93#ibcon#read 5, iclass 39, count 2 2006.245.07:47:40.93#ibcon#about to read 6, iclass 39, count 2 2006.245.07:47:40.93#ibcon#read 6, iclass 39, count 2 2006.245.07:47:40.93#ibcon#end of sib2, iclass 39, count 2 2006.245.07:47:40.93#ibcon#*mode == 0, iclass 39, count 2 2006.245.07:47:40.93#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.07:47:40.93#ibcon#[25=AT04-07\r\n] 2006.245.07:47:40.93#ibcon#*before write, iclass 39, count 2 2006.245.07:47:40.93#ibcon#enter sib2, iclass 39, count 2 2006.245.07:47:40.93#ibcon#flushed, iclass 39, count 2 2006.245.07:47:40.93#ibcon#about to write, iclass 39, count 2 2006.245.07:47:40.93#ibcon#wrote, iclass 39, count 2 2006.245.07:47:40.93#ibcon#about to read 3, iclass 39, count 2 2006.245.07:47:40.96#ibcon#read 3, iclass 39, count 2 2006.245.07:47:40.96#ibcon#about to read 4, iclass 39, count 2 2006.245.07:47:40.96#ibcon#read 4, iclass 39, count 2 2006.245.07:47:40.96#ibcon#about to read 5, iclass 39, count 2 2006.245.07:47:40.96#ibcon#read 5, iclass 39, count 2 2006.245.07:47:40.96#ibcon#about to read 6, iclass 39, count 2 2006.245.07:47:40.96#ibcon#read 6, iclass 39, count 2 2006.245.07:47:40.96#ibcon#end of sib2, iclass 39, count 2 2006.245.07:47:40.96#ibcon#*after write, iclass 39, count 2 2006.245.07:47:40.96#ibcon#*before return 0, iclass 39, count 2 2006.245.07:47:40.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:40.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:40.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.07:47:40.96#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:40.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:41.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:41.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:41.08#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:47:41.08#ibcon#first serial, iclass 39, count 0 2006.245.07:47:41.08#ibcon#enter sib2, iclass 39, count 0 2006.245.07:47:41.08#ibcon#flushed, iclass 39, count 0 2006.245.07:47:41.08#ibcon#about to write, iclass 39, count 0 2006.245.07:47:41.08#ibcon#wrote, iclass 39, count 0 2006.245.07:47:41.08#ibcon#about to read 3, iclass 39, count 0 2006.245.07:47:41.10#ibcon#read 3, iclass 39, count 0 2006.245.07:47:41.10#ibcon#about to read 4, iclass 39, count 0 2006.245.07:47:41.10#ibcon#read 4, iclass 39, count 0 2006.245.07:47:41.10#ibcon#about to read 5, iclass 39, count 0 2006.245.07:47:41.10#ibcon#read 5, iclass 39, count 0 2006.245.07:47:41.10#ibcon#about to read 6, iclass 39, count 0 2006.245.07:47:41.10#ibcon#read 6, iclass 39, count 0 2006.245.07:47:41.10#ibcon#end of sib2, iclass 39, count 0 2006.245.07:47:41.10#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:47:41.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:47:41.10#ibcon#[25=USB\r\n] 2006.245.07:47:41.10#ibcon#*before write, iclass 39, count 0 2006.245.07:47:41.10#ibcon#enter sib2, iclass 39, count 0 2006.245.07:47:41.10#ibcon#flushed, iclass 39, count 0 2006.245.07:47:41.10#ibcon#about to write, iclass 39, count 0 2006.245.07:47:41.10#ibcon#wrote, iclass 39, count 0 2006.245.07:47:41.10#ibcon#about to read 3, iclass 39, count 0 2006.245.07:47:41.13#ibcon#read 3, iclass 39, count 0 2006.245.07:47:41.13#ibcon#about to read 4, iclass 39, count 0 2006.245.07:47:41.13#ibcon#read 4, iclass 39, count 0 2006.245.07:47:41.13#ibcon#about to read 5, iclass 39, count 0 2006.245.07:47:41.13#ibcon#read 5, iclass 39, count 0 2006.245.07:47:41.13#ibcon#about to read 6, iclass 39, count 0 2006.245.07:47:41.13#ibcon#read 6, iclass 39, count 0 2006.245.07:47:41.13#ibcon#end of sib2, iclass 39, count 0 2006.245.07:47:41.13#ibcon#*after write, iclass 39, count 0 2006.245.07:47:41.13#ibcon#*before return 0, iclass 39, count 0 2006.245.07:47:41.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:41.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:41.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:47:41.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:47:41.13$vc4f8/valo=5,652.99 2006.245.07:47:41.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.07:47:41.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.07:47:41.13#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:41.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:41.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:41.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:41.13#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:47:41.13#ibcon#first serial, iclass 3, count 0 2006.245.07:47:41.13#ibcon#enter sib2, iclass 3, count 0 2006.245.07:47:41.13#ibcon#flushed, iclass 3, count 0 2006.245.07:47:41.13#ibcon#about to write, iclass 3, count 0 2006.245.07:47:41.13#ibcon#wrote, iclass 3, count 0 2006.245.07:47:41.13#ibcon#about to read 3, iclass 3, count 0 2006.245.07:47:41.15#ibcon#read 3, iclass 3, count 0 2006.245.07:47:41.15#ibcon#about to read 4, iclass 3, count 0 2006.245.07:47:41.15#ibcon#read 4, iclass 3, count 0 2006.245.07:47:41.15#ibcon#about to read 5, iclass 3, count 0 2006.245.07:47:41.15#ibcon#read 5, iclass 3, count 0 2006.245.07:47:41.15#ibcon#about to read 6, iclass 3, count 0 2006.245.07:47:41.15#ibcon#read 6, iclass 3, count 0 2006.245.07:47:41.15#ibcon#end of sib2, iclass 3, count 0 2006.245.07:47:41.15#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:47:41.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:47:41.15#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:47:41.15#ibcon#*before write, iclass 3, count 0 2006.245.07:47:41.15#ibcon#enter sib2, iclass 3, count 0 2006.245.07:47:41.15#ibcon#flushed, iclass 3, count 0 2006.245.07:47:41.15#ibcon#about to write, iclass 3, count 0 2006.245.07:47:41.15#ibcon#wrote, iclass 3, count 0 2006.245.07:47:41.15#ibcon#about to read 3, iclass 3, count 0 2006.245.07:47:41.19#ibcon#read 3, iclass 3, count 0 2006.245.07:47:41.19#ibcon#about to read 4, iclass 3, count 0 2006.245.07:47:41.19#ibcon#read 4, iclass 3, count 0 2006.245.07:47:41.19#ibcon#about to read 5, iclass 3, count 0 2006.245.07:47:41.19#ibcon#read 5, iclass 3, count 0 2006.245.07:47:41.19#ibcon#about to read 6, iclass 3, count 0 2006.245.07:47:41.19#ibcon#read 6, iclass 3, count 0 2006.245.07:47:41.19#ibcon#end of sib2, iclass 3, count 0 2006.245.07:47:41.19#ibcon#*after write, iclass 3, count 0 2006.245.07:47:41.19#ibcon#*before return 0, iclass 3, count 0 2006.245.07:47:41.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:41.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:41.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:47:41.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:47:41.19$vc4f8/va=5,7 2006.245.07:47:41.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.07:47:41.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.07:47:41.19#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:41.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:41.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:41.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:41.25#ibcon#enter wrdev, iclass 5, count 2 2006.245.07:47:41.25#ibcon#first serial, iclass 5, count 2 2006.245.07:47:41.25#ibcon#enter sib2, iclass 5, count 2 2006.245.07:47:41.25#ibcon#flushed, iclass 5, count 2 2006.245.07:47:41.25#ibcon#about to write, iclass 5, count 2 2006.245.07:47:41.25#ibcon#wrote, iclass 5, count 2 2006.245.07:47:41.25#ibcon#about to read 3, iclass 5, count 2 2006.245.07:47:41.27#ibcon#read 3, iclass 5, count 2 2006.245.07:47:41.27#ibcon#about to read 4, iclass 5, count 2 2006.245.07:47:41.27#ibcon#read 4, iclass 5, count 2 2006.245.07:47:41.27#ibcon#about to read 5, iclass 5, count 2 2006.245.07:47:41.27#ibcon#read 5, iclass 5, count 2 2006.245.07:47:41.27#ibcon#about to read 6, iclass 5, count 2 2006.245.07:47:41.27#ibcon#read 6, iclass 5, count 2 2006.245.07:47:41.27#ibcon#end of sib2, iclass 5, count 2 2006.245.07:47:41.27#ibcon#*mode == 0, iclass 5, count 2 2006.245.07:47:41.27#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.07:47:41.27#ibcon#[25=AT05-07\r\n] 2006.245.07:47:41.27#ibcon#*before write, iclass 5, count 2 2006.245.07:47:41.27#ibcon#enter sib2, iclass 5, count 2 2006.245.07:47:41.27#ibcon#flushed, iclass 5, count 2 2006.245.07:47:41.27#ibcon#about to write, iclass 5, count 2 2006.245.07:47:41.27#ibcon#wrote, iclass 5, count 2 2006.245.07:47:41.27#ibcon#about to read 3, iclass 5, count 2 2006.245.07:47:41.30#ibcon#read 3, iclass 5, count 2 2006.245.07:47:41.30#ibcon#about to read 4, iclass 5, count 2 2006.245.07:47:41.30#ibcon#read 4, iclass 5, count 2 2006.245.07:47:41.30#ibcon#about to read 5, iclass 5, count 2 2006.245.07:47:41.30#ibcon#read 5, iclass 5, count 2 2006.245.07:47:41.30#ibcon#about to read 6, iclass 5, count 2 2006.245.07:47:41.30#ibcon#read 6, iclass 5, count 2 2006.245.07:47:41.30#ibcon#end of sib2, iclass 5, count 2 2006.245.07:47:41.30#ibcon#*after write, iclass 5, count 2 2006.245.07:47:41.30#ibcon#*before return 0, iclass 5, count 2 2006.245.07:47:41.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:41.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:41.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.07:47:41.30#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:41.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:41.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:41.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:41.42#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:47:41.42#ibcon#first serial, iclass 5, count 0 2006.245.07:47:41.42#ibcon#enter sib2, iclass 5, count 0 2006.245.07:47:41.42#ibcon#flushed, iclass 5, count 0 2006.245.07:47:41.42#ibcon#about to write, iclass 5, count 0 2006.245.07:47:41.42#ibcon#wrote, iclass 5, count 0 2006.245.07:47:41.42#ibcon#about to read 3, iclass 5, count 0 2006.245.07:47:41.44#ibcon#read 3, iclass 5, count 0 2006.245.07:47:41.44#ibcon#about to read 4, iclass 5, count 0 2006.245.07:47:41.44#ibcon#read 4, iclass 5, count 0 2006.245.07:47:41.44#ibcon#about to read 5, iclass 5, count 0 2006.245.07:47:41.44#ibcon#read 5, iclass 5, count 0 2006.245.07:47:41.44#ibcon#about to read 6, iclass 5, count 0 2006.245.07:47:41.44#ibcon#read 6, iclass 5, count 0 2006.245.07:47:41.44#ibcon#end of sib2, iclass 5, count 0 2006.245.07:47:41.44#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:47:41.44#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:47:41.44#ibcon#[25=USB\r\n] 2006.245.07:47:41.44#ibcon#*before write, iclass 5, count 0 2006.245.07:47:41.44#ibcon#enter sib2, iclass 5, count 0 2006.245.07:47:41.44#ibcon#flushed, iclass 5, count 0 2006.245.07:47:41.44#ibcon#about to write, iclass 5, count 0 2006.245.07:47:41.44#ibcon#wrote, iclass 5, count 0 2006.245.07:47:41.44#ibcon#about to read 3, iclass 5, count 0 2006.245.07:47:41.47#ibcon#read 3, iclass 5, count 0 2006.245.07:47:41.47#ibcon#about to read 4, iclass 5, count 0 2006.245.07:47:41.47#ibcon#read 4, iclass 5, count 0 2006.245.07:47:41.47#ibcon#about to read 5, iclass 5, count 0 2006.245.07:47:41.47#ibcon#read 5, iclass 5, count 0 2006.245.07:47:41.47#ibcon#about to read 6, iclass 5, count 0 2006.245.07:47:41.47#ibcon#read 6, iclass 5, count 0 2006.245.07:47:41.47#ibcon#end of sib2, iclass 5, count 0 2006.245.07:47:41.47#ibcon#*after write, iclass 5, count 0 2006.245.07:47:41.47#ibcon#*before return 0, iclass 5, count 0 2006.245.07:47:41.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:41.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:41.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:47:41.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:47:41.47$vc4f8/valo=6,772.99 2006.245.07:47:41.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:47:41.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:47:41.47#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:41.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:41.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:41.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:41.47#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:47:41.47#ibcon#first serial, iclass 7, count 0 2006.245.07:47:41.47#ibcon#enter sib2, iclass 7, count 0 2006.245.07:47:41.47#ibcon#flushed, iclass 7, count 0 2006.245.07:47:41.47#ibcon#about to write, iclass 7, count 0 2006.245.07:47:41.47#ibcon#wrote, iclass 7, count 0 2006.245.07:47:41.47#ibcon#about to read 3, iclass 7, count 0 2006.245.07:47:41.49#ibcon#read 3, iclass 7, count 0 2006.245.07:47:41.49#ibcon#about to read 4, iclass 7, count 0 2006.245.07:47:41.49#ibcon#read 4, iclass 7, count 0 2006.245.07:47:41.49#ibcon#about to read 5, iclass 7, count 0 2006.245.07:47:41.49#ibcon#read 5, iclass 7, count 0 2006.245.07:47:41.49#ibcon#about to read 6, iclass 7, count 0 2006.245.07:47:41.49#ibcon#read 6, iclass 7, count 0 2006.245.07:47:41.49#ibcon#end of sib2, iclass 7, count 0 2006.245.07:47:41.49#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:47:41.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:47:41.49#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:47:41.49#ibcon#*before write, iclass 7, count 0 2006.245.07:47:41.49#ibcon#enter sib2, iclass 7, count 0 2006.245.07:47:41.49#ibcon#flushed, iclass 7, count 0 2006.245.07:47:41.49#ibcon#about to write, iclass 7, count 0 2006.245.07:47:41.49#ibcon#wrote, iclass 7, count 0 2006.245.07:47:41.49#ibcon#about to read 3, iclass 7, count 0 2006.245.07:47:41.54#ibcon#read 3, iclass 7, count 0 2006.245.07:47:41.54#ibcon#about to read 4, iclass 7, count 0 2006.245.07:47:41.54#ibcon#read 4, iclass 7, count 0 2006.245.07:47:41.54#ibcon#about to read 5, iclass 7, count 0 2006.245.07:47:41.54#ibcon#read 5, iclass 7, count 0 2006.245.07:47:41.54#ibcon#about to read 6, iclass 7, count 0 2006.245.07:47:41.54#ibcon#read 6, iclass 7, count 0 2006.245.07:47:41.54#ibcon#end of sib2, iclass 7, count 0 2006.245.07:47:41.54#ibcon#*after write, iclass 7, count 0 2006.245.07:47:41.54#ibcon#*before return 0, iclass 7, count 0 2006.245.07:47:41.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:41.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:41.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:47:41.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:47:41.54$vc4f8/va=6,7 2006.245.07:47:41.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.07:47:41.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.07:47:41.54#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:41.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:47:41.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:47:41.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:47:41.59#ibcon#enter wrdev, iclass 11, count 2 2006.245.07:47:41.59#ibcon#first serial, iclass 11, count 2 2006.245.07:47:41.59#ibcon#enter sib2, iclass 11, count 2 2006.245.07:47:41.59#ibcon#flushed, iclass 11, count 2 2006.245.07:47:41.59#ibcon#about to write, iclass 11, count 2 2006.245.07:47:41.59#ibcon#wrote, iclass 11, count 2 2006.245.07:47:41.59#ibcon#about to read 3, iclass 11, count 2 2006.245.07:47:41.61#ibcon#read 3, iclass 11, count 2 2006.245.07:47:41.61#ibcon#about to read 4, iclass 11, count 2 2006.245.07:47:41.61#ibcon#read 4, iclass 11, count 2 2006.245.07:47:41.61#ibcon#about to read 5, iclass 11, count 2 2006.245.07:47:41.61#ibcon#read 5, iclass 11, count 2 2006.245.07:47:41.61#ibcon#about to read 6, iclass 11, count 2 2006.245.07:47:41.61#ibcon#read 6, iclass 11, count 2 2006.245.07:47:41.61#ibcon#end of sib2, iclass 11, count 2 2006.245.07:47:41.61#ibcon#*mode == 0, iclass 11, count 2 2006.245.07:47:41.61#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.07:47:41.61#ibcon#[25=AT06-07\r\n] 2006.245.07:47:41.61#ibcon#*before write, iclass 11, count 2 2006.245.07:47:41.61#ibcon#enter sib2, iclass 11, count 2 2006.245.07:47:41.61#ibcon#flushed, iclass 11, count 2 2006.245.07:47:41.61#ibcon#about to write, iclass 11, count 2 2006.245.07:47:41.61#ibcon#wrote, iclass 11, count 2 2006.245.07:47:41.61#ibcon#about to read 3, iclass 11, count 2 2006.245.07:47:41.64#ibcon#read 3, iclass 11, count 2 2006.245.07:47:41.64#ibcon#about to read 4, iclass 11, count 2 2006.245.07:47:41.64#ibcon#read 4, iclass 11, count 2 2006.245.07:47:41.64#ibcon#about to read 5, iclass 11, count 2 2006.245.07:47:41.64#ibcon#read 5, iclass 11, count 2 2006.245.07:47:41.64#ibcon#about to read 6, iclass 11, count 2 2006.245.07:47:41.64#ibcon#read 6, iclass 11, count 2 2006.245.07:47:41.64#ibcon#end of sib2, iclass 11, count 2 2006.245.07:47:41.64#ibcon#*after write, iclass 11, count 2 2006.245.07:47:41.64#ibcon#*before return 0, iclass 11, count 2 2006.245.07:47:41.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:47:41.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:47:41.64#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.07:47:41.64#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:41.64#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:47:41.76#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:47:41.76#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:47:41.76#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:47:41.76#ibcon#first serial, iclass 11, count 0 2006.245.07:47:41.76#ibcon#enter sib2, iclass 11, count 0 2006.245.07:47:41.76#ibcon#flushed, iclass 11, count 0 2006.245.07:47:41.76#ibcon#about to write, iclass 11, count 0 2006.245.07:47:41.76#ibcon#wrote, iclass 11, count 0 2006.245.07:47:41.76#ibcon#about to read 3, iclass 11, count 0 2006.245.07:47:41.78#ibcon#read 3, iclass 11, count 0 2006.245.07:47:41.78#ibcon#about to read 4, iclass 11, count 0 2006.245.07:47:41.78#ibcon#read 4, iclass 11, count 0 2006.245.07:47:41.78#ibcon#about to read 5, iclass 11, count 0 2006.245.07:47:41.78#ibcon#read 5, iclass 11, count 0 2006.245.07:47:41.78#ibcon#about to read 6, iclass 11, count 0 2006.245.07:47:41.78#ibcon#read 6, iclass 11, count 0 2006.245.07:47:41.78#ibcon#end of sib2, iclass 11, count 0 2006.245.07:47:41.78#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:47:41.78#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:47:41.78#ibcon#[25=USB\r\n] 2006.245.07:47:41.78#ibcon#*before write, iclass 11, count 0 2006.245.07:47:41.78#ibcon#enter sib2, iclass 11, count 0 2006.245.07:47:41.78#ibcon#flushed, iclass 11, count 0 2006.245.07:47:41.78#ibcon#about to write, iclass 11, count 0 2006.245.07:47:41.78#ibcon#wrote, iclass 11, count 0 2006.245.07:47:41.78#ibcon#about to read 3, iclass 11, count 0 2006.245.07:47:41.81#ibcon#read 3, iclass 11, count 0 2006.245.07:47:41.81#ibcon#about to read 4, iclass 11, count 0 2006.245.07:47:41.81#ibcon#read 4, iclass 11, count 0 2006.245.07:47:41.81#ibcon#about to read 5, iclass 11, count 0 2006.245.07:47:41.81#ibcon#read 5, iclass 11, count 0 2006.245.07:47:41.81#ibcon#about to read 6, iclass 11, count 0 2006.245.07:47:41.81#ibcon#read 6, iclass 11, count 0 2006.245.07:47:41.81#ibcon#end of sib2, iclass 11, count 0 2006.245.07:47:41.81#ibcon#*after write, iclass 11, count 0 2006.245.07:47:41.81#ibcon#*before return 0, iclass 11, count 0 2006.245.07:47:41.81#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:47:41.81#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:47:41.81#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:47:41.81#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:47:41.81$vc4f8/valo=7,832.99 2006.245.07:47:41.81#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.07:47:41.81#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.07:47:41.81#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:41.81#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:47:41.81#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:47:41.81#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:47:41.81#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:47:41.81#ibcon#first serial, iclass 13, count 0 2006.245.07:47:41.81#ibcon#enter sib2, iclass 13, count 0 2006.245.07:47:41.81#ibcon#flushed, iclass 13, count 0 2006.245.07:47:41.81#ibcon#about to write, iclass 13, count 0 2006.245.07:47:41.81#ibcon#wrote, iclass 13, count 0 2006.245.07:47:41.81#ibcon#about to read 3, iclass 13, count 0 2006.245.07:47:41.83#ibcon#read 3, iclass 13, count 0 2006.245.07:47:41.83#ibcon#about to read 4, iclass 13, count 0 2006.245.07:47:41.83#ibcon#read 4, iclass 13, count 0 2006.245.07:47:41.83#ibcon#about to read 5, iclass 13, count 0 2006.245.07:47:41.83#ibcon#read 5, iclass 13, count 0 2006.245.07:47:41.83#ibcon#about to read 6, iclass 13, count 0 2006.245.07:47:41.83#ibcon#read 6, iclass 13, count 0 2006.245.07:47:41.83#ibcon#end of sib2, iclass 13, count 0 2006.245.07:47:41.83#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:47:41.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:47:41.83#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:47:41.83#ibcon#*before write, iclass 13, count 0 2006.245.07:47:41.83#ibcon#enter sib2, iclass 13, count 0 2006.245.07:47:41.83#ibcon#flushed, iclass 13, count 0 2006.245.07:47:41.83#ibcon#about to write, iclass 13, count 0 2006.245.07:47:41.83#ibcon#wrote, iclass 13, count 0 2006.245.07:47:41.83#ibcon#about to read 3, iclass 13, count 0 2006.245.07:47:41.87#ibcon#read 3, iclass 13, count 0 2006.245.07:47:41.87#ibcon#about to read 4, iclass 13, count 0 2006.245.07:47:41.87#ibcon#read 4, iclass 13, count 0 2006.245.07:47:41.87#ibcon#about to read 5, iclass 13, count 0 2006.245.07:47:41.87#ibcon#read 5, iclass 13, count 0 2006.245.07:47:41.87#ibcon#about to read 6, iclass 13, count 0 2006.245.07:47:41.87#ibcon#read 6, iclass 13, count 0 2006.245.07:47:41.87#ibcon#end of sib2, iclass 13, count 0 2006.245.07:47:41.87#ibcon#*after write, iclass 13, count 0 2006.245.07:47:41.87#ibcon#*before return 0, iclass 13, count 0 2006.245.07:47:41.87#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:47:41.87#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:47:41.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:47:41.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:47:41.87$vc4f8/va=7,7 2006.245.07:47:41.87#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.07:47:41.87#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.07:47:41.87#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:41.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:47:41.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:47:41.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:47:41.93#ibcon#enter wrdev, iclass 15, count 2 2006.245.07:47:41.93#ibcon#first serial, iclass 15, count 2 2006.245.07:47:41.93#ibcon#enter sib2, iclass 15, count 2 2006.245.07:47:41.93#ibcon#flushed, iclass 15, count 2 2006.245.07:47:41.93#ibcon#about to write, iclass 15, count 2 2006.245.07:47:41.93#ibcon#wrote, iclass 15, count 2 2006.245.07:47:41.93#ibcon#about to read 3, iclass 15, count 2 2006.245.07:47:41.95#ibcon#read 3, iclass 15, count 2 2006.245.07:47:41.95#ibcon#about to read 4, iclass 15, count 2 2006.245.07:47:41.95#ibcon#read 4, iclass 15, count 2 2006.245.07:47:41.95#ibcon#about to read 5, iclass 15, count 2 2006.245.07:47:41.95#ibcon#read 5, iclass 15, count 2 2006.245.07:47:41.95#ibcon#about to read 6, iclass 15, count 2 2006.245.07:47:41.95#ibcon#read 6, iclass 15, count 2 2006.245.07:47:41.95#ibcon#end of sib2, iclass 15, count 2 2006.245.07:47:41.95#ibcon#*mode == 0, iclass 15, count 2 2006.245.07:47:41.95#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.07:47:41.95#ibcon#[25=AT07-07\r\n] 2006.245.07:47:41.95#ibcon#*before write, iclass 15, count 2 2006.245.07:47:41.95#ibcon#enter sib2, iclass 15, count 2 2006.245.07:47:41.95#ibcon#flushed, iclass 15, count 2 2006.245.07:47:41.95#ibcon#about to write, iclass 15, count 2 2006.245.07:47:41.95#ibcon#wrote, iclass 15, count 2 2006.245.07:47:41.95#ibcon#about to read 3, iclass 15, count 2 2006.245.07:47:41.98#ibcon#read 3, iclass 15, count 2 2006.245.07:47:41.98#ibcon#about to read 4, iclass 15, count 2 2006.245.07:47:41.98#ibcon#read 4, iclass 15, count 2 2006.245.07:47:41.98#ibcon#about to read 5, iclass 15, count 2 2006.245.07:47:41.98#ibcon#read 5, iclass 15, count 2 2006.245.07:47:41.98#ibcon#about to read 6, iclass 15, count 2 2006.245.07:47:41.98#ibcon#read 6, iclass 15, count 2 2006.245.07:47:41.98#ibcon#end of sib2, iclass 15, count 2 2006.245.07:47:41.98#ibcon#*after write, iclass 15, count 2 2006.245.07:47:41.98#ibcon#*before return 0, iclass 15, count 2 2006.245.07:47:41.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:47:41.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:47:41.98#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.07:47:41.98#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:41.98#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:47:42.10#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:47:42.10#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:47:42.10#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:47:42.10#ibcon#first serial, iclass 15, count 0 2006.245.07:47:42.10#ibcon#enter sib2, iclass 15, count 0 2006.245.07:47:42.10#ibcon#flushed, iclass 15, count 0 2006.245.07:47:42.10#ibcon#about to write, iclass 15, count 0 2006.245.07:47:42.10#ibcon#wrote, iclass 15, count 0 2006.245.07:47:42.10#ibcon#about to read 3, iclass 15, count 0 2006.245.07:47:42.12#ibcon#read 3, iclass 15, count 0 2006.245.07:47:42.12#ibcon#about to read 4, iclass 15, count 0 2006.245.07:47:42.12#ibcon#read 4, iclass 15, count 0 2006.245.07:47:42.12#ibcon#about to read 5, iclass 15, count 0 2006.245.07:47:42.12#ibcon#read 5, iclass 15, count 0 2006.245.07:47:42.12#ibcon#about to read 6, iclass 15, count 0 2006.245.07:47:42.12#ibcon#read 6, iclass 15, count 0 2006.245.07:47:42.12#ibcon#end of sib2, iclass 15, count 0 2006.245.07:47:42.12#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:47:42.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:47:42.12#ibcon#[25=USB\r\n] 2006.245.07:47:42.12#ibcon#*before write, iclass 15, count 0 2006.245.07:47:42.12#ibcon#enter sib2, iclass 15, count 0 2006.245.07:47:42.12#ibcon#flushed, iclass 15, count 0 2006.245.07:47:42.12#ibcon#about to write, iclass 15, count 0 2006.245.07:47:42.12#ibcon#wrote, iclass 15, count 0 2006.245.07:47:42.12#ibcon#about to read 3, iclass 15, count 0 2006.245.07:47:42.15#ibcon#read 3, iclass 15, count 0 2006.245.07:47:42.15#ibcon#about to read 4, iclass 15, count 0 2006.245.07:47:42.15#ibcon#read 4, iclass 15, count 0 2006.245.07:47:42.15#ibcon#about to read 5, iclass 15, count 0 2006.245.07:47:42.15#ibcon#read 5, iclass 15, count 0 2006.245.07:47:42.15#ibcon#about to read 6, iclass 15, count 0 2006.245.07:47:42.15#ibcon#read 6, iclass 15, count 0 2006.245.07:47:42.15#ibcon#end of sib2, iclass 15, count 0 2006.245.07:47:42.15#ibcon#*after write, iclass 15, count 0 2006.245.07:47:42.15#ibcon#*before return 0, iclass 15, count 0 2006.245.07:47:42.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:47:42.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:47:42.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:47:42.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:47:42.15$vc4f8/valo=8,852.99 2006.245.07:47:42.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.07:47:42.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.07:47:42.15#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:42.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:47:42.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:47:42.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:47:42.15#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:47:42.15#ibcon#first serial, iclass 17, count 0 2006.245.07:47:42.15#ibcon#enter sib2, iclass 17, count 0 2006.245.07:47:42.15#ibcon#flushed, iclass 17, count 0 2006.245.07:47:42.15#ibcon#about to write, iclass 17, count 0 2006.245.07:47:42.15#ibcon#wrote, iclass 17, count 0 2006.245.07:47:42.15#ibcon#about to read 3, iclass 17, count 0 2006.245.07:47:42.17#ibcon#read 3, iclass 17, count 0 2006.245.07:47:42.17#ibcon#about to read 4, iclass 17, count 0 2006.245.07:47:42.17#ibcon#read 4, iclass 17, count 0 2006.245.07:47:42.17#ibcon#about to read 5, iclass 17, count 0 2006.245.07:47:42.17#ibcon#read 5, iclass 17, count 0 2006.245.07:47:42.17#ibcon#about to read 6, iclass 17, count 0 2006.245.07:47:42.17#ibcon#read 6, iclass 17, count 0 2006.245.07:47:42.17#ibcon#end of sib2, iclass 17, count 0 2006.245.07:47:42.17#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:47:42.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:47:42.17#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:47:42.17#ibcon#*before write, iclass 17, count 0 2006.245.07:47:42.17#ibcon#enter sib2, iclass 17, count 0 2006.245.07:47:42.17#ibcon#flushed, iclass 17, count 0 2006.245.07:47:42.17#ibcon#about to write, iclass 17, count 0 2006.245.07:47:42.17#ibcon#wrote, iclass 17, count 0 2006.245.07:47:42.17#ibcon#about to read 3, iclass 17, count 0 2006.245.07:47:42.21#ibcon#read 3, iclass 17, count 0 2006.245.07:47:42.21#ibcon#about to read 4, iclass 17, count 0 2006.245.07:47:42.21#ibcon#read 4, iclass 17, count 0 2006.245.07:47:42.21#ibcon#about to read 5, iclass 17, count 0 2006.245.07:47:42.21#ibcon#read 5, iclass 17, count 0 2006.245.07:47:42.21#ibcon#about to read 6, iclass 17, count 0 2006.245.07:47:42.21#ibcon#read 6, iclass 17, count 0 2006.245.07:47:42.21#ibcon#end of sib2, iclass 17, count 0 2006.245.07:47:42.21#ibcon#*after write, iclass 17, count 0 2006.245.07:47:42.21#ibcon#*before return 0, iclass 17, count 0 2006.245.07:47:42.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:47:42.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:47:42.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:47:42.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:47:42.21$vc4f8/va=8,8 2006.245.07:47:42.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.07:47:42.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.07:47:42.21#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:42.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:47:42.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:47:42.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:47:42.27#ibcon#enter wrdev, iclass 19, count 2 2006.245.07:47:42.27#ibcon#first serial, iclass 19, count 2 2006.245.07:47:42.27#ibcon#enter sib2, iclass 19, count 2 2006.245.07:47:42.27#ibcon#flushed, iclass 19, count 2 2006.245.07:47:42.27#ibcon#about to write, iclass 19, count 2 2006.245.07:47:42.27#ibcon#wrote, iclass 19, count 2 2006.245.07:47:42.27#ibcon#about to read 3, iclass 19, count 2 2006.245.07:47:42.29#ibcon#read 3, iclass 19, count 2 2006.245.07:47:42.29#ibcon#about to read 4, iclass 19, count 2 2006.245.07:47:42.29#ibcon#read 4, iclass 19, count 2 2006.245.07:47:42.29#ibcon#about to read 5, iclass 19, count 2 2006.245.07:47:42.29#ibcon#read 5, iclass 19, count 2 2006.245.07:47:42.29#ibcon#about to read 6, iclass 19, count 2 2006.245.07:47:42.29#ibcon#read 6, iclass 19, count 2 2006.245.07:47:42.29#ibcon#end of sib2, iclass 19, count 2 2006.245.07:47:42.29#ibcon#*mode == 0, iclass 19, count 2 2006.245.07:47:42.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.07:47:42.29#ibcon#[25=AT08-08\r\n] 2006.245.07:47:42.29#ibcon#*before write, iclass 19, count 2 2006.245.07:47:42.29#ibcon#enter sib2, iclass 19, count 2 2006.245.07:47:42.29#ibcon#flushed, iclass 19, count 2 2006.245.07:47:42.29#ibcon#about to write, iclass 19, count 2 2006.245.07:47:42.29#ibcon#wrote, iclass 19, count 2 2006.245.07:47:42.29#ibcon#about to read 3, iclass 19, count 2 2006.245.07:47:42.32#ibcon#read 3, iclass 19, count 2 2006.245.07:47:42.32#ibcon#about to read 4, iclass 19, count 2 2006.245.07:47:42.32#ibcon#read 4, iclass 19, count 2 2006.245.07:47:42.32#ibcon#about to read 5, iclass 19, count 2 2006.245.07:47:42.32#ibcon#read 5, iclass 19, count 2 2006.245.07:47:42.32#ibcon#about to read 6, iclass 19, count 2 2006.245.07:47:42.32#ibcon#read 6, iclass 19, count 2 2006.245.07:47:42.32#ibcon#end of sib2, iclass 19, count 2 2006.245.07:47:42.32#ibcon#*after write, iclass 19, count 2 2006.245.07:47:42.32#ibcon#*before return 0, iclass 19, count 2 2006.245.07:47:42.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:47:42.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:47:42.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.07:47:42.32#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:42.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:47:42.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:47:42.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:47:42.44#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:47:42.44#ibcon#first serial, iclass 19, count 0 2006.245.07:47:42.44#ibcon#enter sib2, iclass 19, count 0 2006.245.07:47:42.44#ibcon#flushed, iclass 19, count 0 2006.245.07:47:42.44#ibcon#about to write, iclass 19, count 0 2006.245.07:47:42.44#ibcon#wrote, iclass 19, count 0 2006.245.07:47:42.44#ibcon#about to read 3, iclass 19, count 0 2006.245.07:47:42.46#ibcon#read 3, iclass 19, count 0 2006.245.07:47:42.46#ibcon#about to read 4, iclass 19, count 0 2006.245.07:47:42.46#ibcon#read 4, iclass 19, count 0 2006.245.07:47:42.46#ibcon#about to read 5, iclass 19, count 0 2006.245.07:47:42.46#ibcon#read 5, iclass 19, count 0 2006.245.07:47:42.46#ibcon#about to read 6, iclass 19, count 0 2006.245.07:47:42.46#ibcon#read 6, iclass 19, count 0 2006.245.07:47:42.46#ibcon#end of sib2, iclass 19, count 0 2006.245.07:47:42.46#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:47:42.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:47:42.46#ibcon#[25=USB\r\n] 2006.245.07:47:42.46#ibcon#*before write, iclass 19, count 0 2006.245.07:47:42.46#ibcon#enter sib2, iclass 19, count 0 2006.245.07:47:42.46#ibcon#flushed, iclass 19, count 0 2006.245.07:47:42.46#ibcon#about to write, iclass 19, count 0 2006.245.07:47:42.46#ibcon#wrote, iclass 19, count 0 2006.245.07:47:42.46#ibcon#about to read 3, iclass 19, count 0 2006.245.07:47:42.49#ibcon#read 3, iclass 19, count 0 2006.245.07:47:42.49#ibcon#about to read 4, iclass 19, count 0 2006.245.07:47:42.49#ibcon#read 4, iclass 19, count 0 2006.245.07:47:42.49#ibcon#about to read 5, iclass 19, count 0 2006.245.07:47:42.49#ibcon#read 5, iclass 19, count 0 2006.245.07:47:42.49#ibcon#about to read 6, iclass 19, count 0 2006.245.07:47:42.49#ibcon#read 6, iclass 19, count 0 2006.245.07:47:42.49#ibcon#end of sib2, iclass 19, count 0 2006.245.07:47:42.49#ibcon#*after write, iclass 19, count 0 2006.245.07:47:42.49#ibcon#*before return 0, iclass 19, count 0 2006.245.07:47:42.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:47:42.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:47:42.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:47:42.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:47:42.49$vc4f8/vblo=1,632.99 2006.245.07:47:42.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.07:47:42.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.07:47:42.49#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:42.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:42.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:42.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:42.49#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:47:42.49#ibcon#first serial, iclass 21, count 0 2006.245.07:47:42.49#ibcon#enter sib2, iclass 21, count 0 2006.245.07:47:42.49#ibcon#flushed, iclass 21, count 0 2006.245.07:47:42.49#ibcon#about to write, iclass 21, count 0 2006.245.07:47:42.49#ibcon#wrote, iclass 21, count 0 2006.245.07:47:42.49#ibcon#about to read 3, iclass 21, count 0 2006.245.07:47:42.51#ibcon#read 3, iclass 21, count 0 2006.245.07:47:42.51#ibcon#about to read 4, iclass 21, count 0 2006.245.07:47:42.51#ibcon#read 4, iclass 21, count 0 2006.245.07:47:42.51#ibcon#about to read 5, iclass 21, count 0 2006.245.07:47:42.51#ibcon#read 5, iclass 21, count 0 2006.245.07:47:42.51#ibcon#about to read 6, iclass 21, count 0 2006.245.07:47:42.51#ibcon#read 6, iclass 21, count 0 2006.245.07:47:42.51#ibcon#end of sib2, iclass 21, count 0 2006.245.07:47:42.51#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:47:42.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:47:42.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:47:42.51#ibcon#*before write, iclass 21, count 0 2006.245.07:47:42.51#ibcon#enter sib2, iclass 21, count 0 2006.245.07:47:42.51#ibcon#flushed, iclass 21, count 0 2006.245.07:47:42.51#ibcon#about to write, iclass 21, count 0 2006.245.07:47:42.51#ibcon#wrote, iclass 21, count 0 2006.245.07:47:42.51#ibcon#about to read 3, iclass 21, count 0 2006.245.07:47:42.55#ibcon#read 3, iclass 21, count 0 2006.245.07:47:42.55#ibcon#about to read 4, iclass 21, count 0 2006.245.07:47:42.55#ibcon#read 4, iclass 21, count 0 2006.245.07:47:42.55#ibcon#about to read 5, iclass 21, count 0 2006.245.07:47:42.55#ibcon#read 5, iclass 21, count 0 2006.245.07:47:42.55#ibcon#about to read 6, iclass 21, count 0 2006.245.07:47:42.55#ibcon#read 6, iclass 21, count 0 2006.245.07:47:42.55#ibcon#end of sib2, iclass 21, count 0 2006.245.07:47:42.55#ibcon#*after write, iclass 21, count 0 2006.245.07:47:42.55#ibcon#*before return 0, iclass 21, count 0 2006.245.07:47:42.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:42.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:47:42.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:47:42.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:47:42.55$vc4f8/vb=1,4 2006.245.07:47:42.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.07:47:42.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.07:47:42.55#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:42.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:42.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:42.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:42.55#ibcon#enter wrdev, iclass 23, count 2 2006.245.07:47:42.55#ibcon#first serial, iclass 23, count 2 2006.245.07:47:42.55#ibcon#enter sib2, iclass 23, count 2 2006.245.07:47:42.55#ibcon#flushed, iclass 23, count 2 2006.245.07:47:42.55#ibcon#about to write, iclass 23, count 2 2006.245.07:47:42.55#ibcon#wrote, iclass 23, count 2 2006.245.07:47:42.55#ibcon#about to read 3, iclass 23, count 2 2006.245.07:47:42.57#ibcon#read 3, iclass 23, count 2 2006.245.07:47:42.57#ibcon#about to read 4, iclass 23, count 2 2006.245.07:47:42.57#ibcon#read 4, iclass 23, count 2 2006.245.07:47:42.57#ibcon#about to read 5, iclass 23, count 2 2006.245.07:47:42.57#ibcon#read 5, iclass 23, count 2 2006.245.07:47:42.57#ibcon#about to read 6, iclass 23, count 2 2006.245.07:47:42.57#ibcon#read 6, iclass 23, count 2 2006.245.07:47:42.57#ibcon#end of sib2, iclass 23, count 2 2006.245.07:47:42.57#ibcon#*mode == 0, iclass 23, count 2 2006.245.07:47:42.57#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.07:47:42.57#ibcon#[27=AT01-04\r\n] 2006.245.07:47:42.57#ibcon#*before write, iclass 23, count 2 2006.245.07:47:42.57#ibcon#enter sib2, iclass 23, count 2 2006.245.07:47:42.57#ibcon#flushed, iclass 23, count 2 2006.245.07:47:42.57#ibcon#about to write, iclass 23, count 2 2006.245.07:47:42.57#ibcon#wrote, iclass 23, count 2 2006.245.07:47:42.57#ibcon#about to read 3, iclass 23, count 2 2006.245.07:47:42.60#ibcon#read 3, iclass 23, count 2 2006.245.07:47:42.60#ibcon#about to read 4, iclass 23, count 2 2006.245.07:47:42.60#ibcon#read 4, iclass 23, count 2 2006.245.07:47:42.60#ibcon#about to read 5, iclass 23, count 2 2006.245.07:47:42.60#ibcon#read 5, iclass 23, count 2 2006.245.07:47:42.60#ibcon#about to read 6, iclass 23, count 2 2006.245.07:47:42.60#ibcon#read 6, iclass 23, count 2 2006.245.07:47:42.60#ibcon#end of sib2, iclass 23, count 2 2006.245.07:47:42.60#ibcon#*after write, iclass 23, count 2 2006.245.07:47:42.60#ibcon#*before return 0, iclass 23, count 2 2006.245.07:47:42.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:42.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:47:42.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.07:47:42.60#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:42.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:42.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:42.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:42.72#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:47:42.72#ibcon#first serial, iclass 23, count 0 2006.245.07:47:42.72#ibcon#enter sib2, iclass 23, count 0 2006.245.07:47:42.72#ibcon#flushed, iclass 23, count 0 2006.245.07:47:42.72#ibcon#about to write, iclass 23, count 0 2006.245.07:47:42.72#ibcon#wrote, iclass 23, count 0 2006.245.07:47:42.72#ibcon#about to read 3, iclass 23, count 0 2006.245.07:47:42.74#ibcon#read 3, iclass 23, count 0 2006.245.07:47:42.74#ibcon#about to read 4, iclass 23, count 0 2006.245.07:47:42.74#ibcon#read 4, iclass 23, count 0 2006.245.07:47:42.74#ibcon#about to read 5, iclass 23, count 0 2006.245.07:47:42.74#ibcon#read 5, iclass 23, count 0 2006.245.07:47:42.74#ibcon#about to read 6, iclass 23, count 0 2006.245.07:47:42.74#ibcon#read 6, iclass 23, count 0 2006.245.07:47:42.74#ibcon#end of sib2, iclass 23, count 0 2006.245.07:47:42.74#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:47:42.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:47:42.74#ibcon#[27=USB\r\n] 2006.245.07:47:42.74#ibcon#*before write, iclass 23, count 0 2006.245.07:47:42.74#ibcon#enter sib2, iclass 23, count 0 2006.245.07:47:42.74#ibcon#flushed, iclass 23, count 0 2006.245.07:47:42.74#ibcon#about to write, iclass 23, count 0 2006.245.07:47:42.74#ibcon#wrote, iclass 23, count 0 2006.245.07:47:42.74#ibcon#about to read 3, iclass 23, count 0 2006.245.07:47:42.77#ibcon#read 3, iclass 23, count 0 2006.245.07:47:42.77#ibcon#about to read 4, iclass 23, count 0 2006.245.07:47:42.77#ibcon#read 4, iclass 23, count 0 2006.245.07:47:42.77#ibcon#about to read 5, iclass 23, count 0 2006.245.07:47:42.77#ibcon#read 5, iclass 23, count 0 2006.245.07:47:42.77#ibcon#about to read 6, iclass 23, count 0 2006.245.07:47:42.77#ibcon#read 6, iclass 23, count 0 2006.245.07:47:42.77#ibcon#end of sib2, iclass 23, count 0 2006.245.07:47:42.77#ibcon#*after write, iclass 23, count 0 2006.245.07:47:42.77#ibcon#*before return 0, iclass 23, count 0 2006.245.07:47:42.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:42.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:47:42.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:47:42.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:47:42.77$vc4f8/vblo=2,640.99 2006.245.07:47:42.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.07:47:42.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.07:47:42.77#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:42.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:42.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:42.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:42.77#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:47:42.77#ibcon#first serial, iclass 25, count 0 2006.245.07:47:42.77#ibcon#enter sib2, iclass 25, count 0 2006.245.07:47:42.77#ibcon#flushed, iclass 25, count 0 2006.245.07:47:42.77#ibcon#about to write, iclass 25, count 0 2006.245.07:47:42.77#ibcon#wrote, iclass 25, count 0 2006.245.07:47:42.77#ibcon#about to read 3, iclass 25, count 0 2006.245.07:47:42.79#ibcon#read 3, iclass 25, count 0 2006.245.07:47:42.79#ibcon#about to read 4, iclass 25, count 0 2006.245.07:47:42.79#ibcon#read 4, iclass 25, count 0 2006.245.07:47:42.79#ibcon#about to read 5, iclass 25, count 0 2006.245.07:47:42.79#ibcon#read 5, iclass 25, count 0 2006.245.07:47:42.79#ibcon#about to read 6, iclass 25, count 0 2006.245.07:47:42.79#ibcon#read 6, iclass 25, count 0 2006.245.07:47:42.79#ibcon#end of sib2, iclass 25, count 0 2006.245.07:47:42.79#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:47:42.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:47:42.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:47:42.79#ibcon#*before write, iclass 25, count 0 2006.245.07:47:42.79#ibcon#enter sib2, iclass 25, count 0 2006.245.07:47:42.79#ibcon#flushed, iclass 25, count 0 2006.245.07:47:42.79#ibcon#about to write, iclass 25, count 0 2006.245.07:47:42.79#ibcon#wrote, iclass 25, count 0 2006.245.07:47:42.79#ibcon#about to read 3, iclass 25, count 0 2006.245.07:47:42.83#ibcon#read 3, iclass 25, count 0 2006.245.07:47:42.83#ibcon#about to read 4, iclass 25, count 0 2006.245.07:47:42.83#ibcon#read 4, iclass 25, count 0 2006.245.07:47:42.83#ibcon#about to read 5, iclass 25, count 0 2006.245.07:47:42.83#ibcon#read 5, iclass 25, count 0 2006.245.07:47:42.83#ibcon#about to read 6, iclass 25, count 0 2006.245.07:47:42.83#ibcon#read 6, iclass 25, count 0 2006.245.07:47:42.83#ibcon#end of sib2, iclass 25, count 0 2006.245.07:47:42.83#ibcon#*after write, iclass 25, count 0 2006.245.07:47:42.83#ibcon#*before return 0, iclass 25, count 0 2006.245.07:47:42.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:42.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:47:42.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:47:42.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:47:42.83$vc4f8/vb=2,4 2006.245.07:47:42.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.07:47:42.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.07:47:42.83#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:42.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:42.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:42.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:42.89#ibcon#enter wrdev, iclass 27, count 2 2006.245.07:47:42.89#ibcon#first serial, iclass 27, count 2 2006.245.07:47:42.89#ibcon#enter sib2, iclass 27, count 2 2006.245.07:47:42.89#ibcon#flushed, iclass 27, count 2 2006.245.07:47:42.89#ibcon#about to write, iclass 27, count 2 2006.245.07:47:42.89#ibcon#wrote, iclass 27, count 2 2006.245.07:47:42.89#ibcon#about to read 3, iclass 27, count 2 2006.245.07:47:42.91#ibcon#read 3, iclass 27, count 2 2006.245.07:47:42.91#ibcon#about to read 4, iclass 27, count 2 2006.245.07:47:42.91#ibcon#read 4, iclass 27, count 2 2006.245.07:47:42.91#ibcon#about to read 5, iclass 27, count 2 2006.245.07:47:42.91#ibcon#read 5, iclass 27, count 2 2006.245.07:47:42.91#ibcon#about to read 6, iclass 27, count 2 2006.245.07:47:42.91#ibcon#read 6, iclass 27, count 2 2006.245.07:47:42.91#ibcon#end of sib2, iclass 27, count 2 2006.245.07:47:42.91#ibcon#*mode == 0, iclass 27, count 2 2006.245.07:47:42.91#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.07:47:42.91#ibcon#[27=AT02-04\r\n] 2006.245.07:47:42.91#ibcon#*before write, iclass 27, count 2 2006.245.07:47:42.91#ibcon#enter sib2, iclass 27, count 2 2006.245.07:47:42.91#ibcon#flushed, iclass 27, count 2 2006.245.07:47:42.91#ibcon#about to write, iclass 27, count 2 2006.245.07:47:42.91#ibcon#wrote, iclass 27, count 2 2006.245.07:47:42.91#ibcon#about to read 3, iclass 27, count 2 2006.245.07:47:42.94#ibcon#read 3, iclass 27, count 2 2006.245.07:47:42.94#ibcon#about to read 4, iclass 27, count 2 2006.245.07:47:42.94#ibcon#read 4, iclass 27, count 2 2006.245.07:47:42.94#ibcon#about to read 5, iclass 27, count 2 2006.245.07:47:42.94#ibcon#read 5, iclass 27, count 2 2006.245.07:47:42.94#ibcon#about to read 6, iclass 27, count 2 2006.245.07:47:42.94#ibcon#read 6, iclass 27, count 2 2006.245.07:47:42.94#ibcon#end of sib2, iclass 27, count 2 2006.245.07:47:42.94#ibcon#*after write, iclass 27, count 2 2006.245.07:47:42.94#ibcon#*before return 0, iclass 27, count 2 2006.245.07:47:42.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:42.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:47:42.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.07:47:42.94#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:42.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:43.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:43.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:43.06#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:47:43.06#ibcon#first serial, iclass 27, count 0 2006.245.07:47:43.06#ibcon#enter sib2, iclass 27, count 0 2006.245.07:47:43.06#ibcon#flushed, iclass 27, count 0 2006.245.07:47:43.06#ibcon#about to write, iclass 27, count 0 2006.245.07:47:43.06#ibcon#wrote, iclass 27, count 0 2006.245.07:47:43.06#ibcon#about to read 3, iclass 27, count 0 2006.245.07:47:43.08#ibcon#read 3, iclass 27, count 0 2006.245.07:47:43.08#ibcon#about to read 4, iclass 27, count 0 2006.245.07:47:43.08#ibcon#read 4, iclass 27, count 0 2006.245.07:47:43.08#ibcon#about to read 5, iclass 27, count 0 2006.245.07:47:43.08#ibcon#read 5, iclass 27, count 0 2006.245.07:47:43.08#ibcon#about to read 6, iclass 27, count 0 2006.245.07:47:43.08#ibcon#read 6, iclass 27, count 0 2006.245.07:47:43.08#ibcon#end of sib2, iclass 27, count 0 2006.245.07:47:43.08#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:47:43.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:47:43.08#ibcon#[27=USB\r\n] 2006.245.07:47:43.08#ibcon#*before write, iclass 27, count 0 2006.245.07:47:43.08#ibcon#enter sib2, iclass 27, count 0 2006.245.07:47:43.08#ibcon#flushed, iclass 27, count 0 2006.245.07:47:43.08#ibcon#about to write, iclass 27, count 0 2006.245.07:47:43.08#ibcon#wrote, iclass 27, count 0 2006.245.07:47:43.08#ibcon#about to read 3, iclass 27, count 0 2006.245.07:47:43.11#ibcon#read 3, iclass 27, count 0 2006.245.07:47:43.11#ibcon#about to read 4, iclass 27, count 0 2006.245.07:47:43.11#ibcon#read 4, iclass 27, count 0 2006.245.07:47:43.11#ibcon#about to read 5, iclass 27, count 0 2006.245.07:47:43.11#ibcon#read 5, iclass 27, count 0 2006.245.07:47:43.11#ibcon#about to read 6, iclass 27, count 0 2006.245.07:47:43.11#ibcon#read 6, iclass 27, count 0 2006.245.07:47:43.11#ibcon#end of sib2, iclass 27, count 0 2006.245.07:47:43.11#ibcon#*after write, iclass 27, count 0 2006.245.07:47:43.11#ibcon#*before return 0, iclass 27, count 0 2006.245.07:47:43.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:43.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:47:43.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:47:43.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:47:43.11$vc4f8/vblo=3,656.99 2006.245.07:47:43.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.07:47:43.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.07:47:43.11#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:43.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:47:43.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:47:43.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:47:43.11#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:47:43.11#ibcon#first serial, iclass 29, count 0 2006.245.07:47:43.11#ibcon#enter sib2, iclass 29, count 0 2006.245.07:47:43.11#ibcon#flushed, iclass 29, count 0 2006.245.07:47:43.11#ibcon#about to write, iclass 29, count 0 2006.245.07:47:43.11#ibcon#wrote, iclass 29, count 0 2006.245.07:47:43.11#ibcon#about to read 3, iclass 29, count 0 2006.245.07:47:43.13#ibcon#read 3, iclass 29, count 0 2006.245.07:47:43.13#ibcon#about to read 4, iclass 29, count 0 2006.245.07:47:43.13#ibcon#read 4, iclass 29, count 0 2006.245.07:47:43.13#ibcon#about to read 5, iclass 29, count 0 2006.245.07:47:43.13#ibcon#read 5, iclass 29, count 0 2006.245.07:47:43.13#ibcon#about to read 6, iclass 29, count 0 2006.245.07:47:43.13#ibcon#read 6, iclass 29, count 0 2006.245.07:47:43.13#ibcon#end of sib2, iclass 29, count 0 2006.245.07:47:43.13#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:47:43.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:47:43.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:47:43.13#ibcon#*before write, iclass 29, count 0 2006.245.07:47:43.13#ibcon#enter sib2, iclass 29, count 0 2006.245.07:47:43.13#ibcon#flushed, iclass 29, count 0 2006.245.07:47:43.13#ibcon#about to write, iclass 29, count 0 2006.245.07:47:43.13#ibcon#wrote, iclass 29, count 0 2006.245.07:47:43.13#ibcon#about to read 3, iclass 29, count 0 2006.245.07:47:43.17#ibcon#read 3, iclass 29, count 0 2006.245.07:47:43.17#ibcon#about to read 4, iclass 29, count 0 2006.245.07:47:43.17#ibcon#read 4, iclass 29, count 0 2006.245.07:47:43.17#ibcon#about to read 5, iclass 29, count 0 2006.245.07:47:43.17#ibcon#read 5, iclass 29, count 0 2006.245.07:47:43.17#ibcon#about to read 6, iclass 29, count 0 2006.245.07:47:43.17#ibcon#read 6, iclass 29, count 0 2006.245.07:47:43.17#ibcon#end of sib2, iclass 29, count 0 2006.245.07:47:43.17#ibcon#*after write, iclass 29, count 0 2006.245.07:47:43.17#ibcon#*before return 0, iclass 29, count 0 2006.245.07:47:43.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:47:43.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:47:43.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:47:43.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:47:43.17$vc4f8/vb=3,4 2006.245.07:47:43.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.07:47:43.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.07:47:43.17#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:43.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:47:43.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:47:43.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:47:43.23#ibcon#enter wrdev, iclass 31, count 2 2006.245.07:47:43.23#ibcon#first serial, iclass 31, count 2 2006.245.07:47:43.23#ibcon#enter sib2, iclass 31, count 2 2006.245.07:47:43.23#ibcon#flushed, iclass 31, count 2 2006.245.07:47:43.23#ibcon#about to write, iclass 31, count 2 2006.245.07:47:43.23#ibcon#wrote, iclass 31, count 2 2006.245.07:47:43.23#ibcon#about to read 3, iclass 31, count 2 2006.245.07:47:43.25#ibcon#read 3, iclass 31, count 2 2006.245.07:47:43.25#ibcon#about to read 4, iclass 31, count 2 2006.245.07:47:43.25#ibcon#read 4, iclass 31, count 2 2006.245.07:47:43.25#ibcon#about to read 5, iclass 31, count 2 2006.245.07:47:43.25#ibcon#read 5, iclass 31, count 2 2006.245.07:47:43.25#ibcon#about to read 6, iclass 31, count 2 2006.245.07:47:43.25#ibcon#read 6, iclass 31, count 2 2006.245.07:47:43.25#ibcon#end of sib2, iclass 31, count 2 2006.245.07:47:43.25#ibcon#*mode == 0, iclass 31, count 2 2006.245.07:47:43.25#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.07:47:43.25#ibcon#[27=AT03-04\r\n] 2006.245.07:47:43.25#ibcon#*before write, iclass 31, count 2 2006.245.07:47:43.25#ibcon#enter sib2, iclass 31, count 2 2006.245.07:47:43.25#ibcon#flushed, iclass 31, count 2 2006.245.07:47:43.25#ibcon#about to write, iclass 31, count 2 2006.245.07:47:43.25#ibcon#wrote, iclass 31, count 2 2006.245.07:47:43.25#ibcon#about to read 3, iclass 31, count 2 2006.245.07:47:43.28#ibcon#read 3, iclass 31, count 2 2006.245.07:47:43.28#ibcon#about to read 4, iclass 31, count 2 2006.245.07:47:43.28#ibcon#read 4, iclass 31, count 2 2006.245.07:47:43.28#ibcon#about to read 5, iclass 31, count 2 2006.245.07:47:43.28#ibcon#read 5, iclass 31, count 2 2006.245.07:47:43.28#ibcon#about to read 6, iclass 31, count 2 2006.245.07:47:43.28#ibcon#read 6, iclass 31, count 2 2006.245.07:47:43.28#ibcon#end of sib2, iclass 31, count 2 2006.245.07:47:43.28#ibcon#*after write, iclass 31, count 2 2006.245.07:47:43.28#ibcon#*before return 0, iclass 31, count 2 2006.245.07:47:43.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:47:43.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:47:43.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.07:47:43.28#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:43.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:47:43.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:47:43.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:47:43.40#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:47:43.40#ibcon#first serial, iclass 31, count 0 2006.245.07:47:43.40#ibcon#enter sib2, iclass 31, count 0 2006.245.07:47:43.40#ibcon#flushed, iclass 31, count 0 2006.245.07:47:43.40#ibcon#about to write, iclass 31, count 0 2006.245.07:47:43.40#ibcon#wrote, iclass 31, count 0 2006.245.07:47:43.40#ibcon#about to read 3, iclass 31, count 0 2006.245.07:47:43.42#ibcon#read 3, iclass 31, count 0 2006.245.07:47:43.42#ibcon#about to read 4, iclass 31, count 0 2006.245.07:47:43.42#ibcon#read 4, iclass 31, count 0 2006.245.07:47:43.42#ibcon#about to read 5, iclass 31, count 0 2006.245.07:47:43.42#ibcon#read 5, iclass 31, count 0 2006.245.07:47:43.42#ibcon#about to read 6, iclass 31, count 0 2006.245.07:47:43.42#ibcon#read 6, iclass 31, count 0 2006.245.07:47:43.42#ibcon#end of sib2, iclass 31, count 0 2006.245.07:47:43.42#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:47:43.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:47:43.42#ibcon#[27=USB\r\n] 2006.245.07:47:43.42#ibcon#*before write, iclass 31, count 0 2006.245.07:47:43.42#ibcon#enter sib2, iclass 31, count 0 2006.245.07:47:43.42#ibcon#flushed, iclass 31, count 0 2006.245.07:47:43.42#ibcon#about to write, iclass 31, count 0 2006.245.07:47:43.42#ibcon#wrote, iclass 31, count 0 2006.245.07:47:43.42#ibcon#about to read 3, iclass 31, count 0 2006.245.07:47:43.45#ibcon#read 3, iclass 31, count 0 2006.245.07:47:43.45#ibcon#about to read 4, iclass 31, count 0 2006.245.07:47:43.45#ibcon#read 4, iclass 31, count 0 2006.245.07:47:43.45#ibcon#about to read 5, iclass 31, count 0 2006.245.07:47:43.45#ibcon#read 5, iclass 31, count 0 2006.245.07:47:43.45#ibcon#about to read 6, iclass 31, count 0 2006.245.07:47:43.45#ibcon#read 6, iclass 31, count 0 2006.245.07:47:43.45#ibcon#end of sib2, iclass 31, count 0 2006.245.07:47:43.45#ibcon#*after write, iclass 31, count 0 2006.245.07:47:43.45#ibcon#*before return 0, iclass 31, count 0 2006.245.07:47:43.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:47:43.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:47:43.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:47:43.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:47:43.45$vc4f8/vblo=4,712.99 2006.245.07:47:43.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.07:47:43.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.07:47:43.45#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:43.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:43.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:43.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:43.45#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:47:43.45#ibcon#first serial, iclass 33, count 0 2006.245.07:47:43.45#ibcon#enter sib2, iclass 33, count 0 2006.245.07:47:43.45#ibcon#flushed, iclass 33, count 0 2006.245.07:47:43.45#ibcon#about to write, iclass 33, count 0 2006.245.07:47:43.45#ibcon#wrote, iclass 33, count 0 2006.245.07:47:43.45#ibcon#about to read 3, iclass 33, count 0 2006.245.07:47:43.47#ibcon#read 3, iclass 33, count 0 2006.245.07:47:43.47#ibcon#about to read 4, iclass 33, count 0 2006.245.07:47:43.47#ibcon#read 4, iclass 33, count 0 2006.245.07:47:43.47#ibcon#about to read 5, iclass 33, count 0 2006.245.07:47:43.47#ibcon#read 5, iclass 33, count 0 2006.245.07:47:43.47#ibcon#about to read 6, iclass 33, count 0 2006.245.07:47:43.47#ibcon#read 6, iclass 33, count 0 2006.245.07:47:43.47#ibcon#end of sib2, iclass 33, count 0 2006.245.07:47:43.47#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:47:43.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:47:43.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:47:43.47#ibcon#*before write, iclass 33, count 0 2006.245.07:47:43.47#ibcon#enter sib2, iclass 33, count 0 2006.245.07:47:43.47#ibcon#flushed, iclass 33, count 0 2006.245.07:47:43.47#ibcon#about to write, iclass 33, count 0 2006.245.07:47:43.47#ibcon#wrote, iclass 33, count 0 2006.245.07:47:43.47#ibcon#about to read 3, iclass 33, count 0 2006.245.07:47:43.51#ibcon#read 3, iclass 33, count 0 2006.245.07:47:43.51#ibcon#about to read 4, iclass 33, count 0 2006.245.07:47:43.51#ibcon#read 4, iclass 33, count 0 2006.245.07:47:43.51#ibcon#about to read 5, iclass 33, count 0 2006.245.07:47:43.51#ibcon#read 5, iclass 33, count 0 2006.245.07:47:43.51#ibcon#about to read 6, iclass 33, count 0 2006.245.07:47:43.51#ibcon#read 6, iclass 33, count 0 2006.245.07:47:43.51#ibcon#end of sib2, iclass 33, count 0 2006.245.07:47:43.51#ibcon#*after write, iclass 33, count 0 2006.245.07:47:43.51#ibcon#*before return 0, iclass 33, count 0 2006.245.07:47:43.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:43.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:47:43.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:47:43.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:47:43.51$vc4f8/vb=4,4 2006.245.07:47:43.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.07:47:43.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.07:47:43.51#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:43.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:43.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:43.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:43.57#ibcon#enter wrdev, iclass 35, count 2 2006.245.07:47:43.57#ibcon#first serial, iclass 35, count 2 2006.245.07:47:43.57#ibcon#enter sib2, iclass 35, count 2 2006.245.07:47:43.57#ibcon#flushed, iclass 35, count 2 2006.245.07:47:43.57#ibcon#about to write, iclass 35, count 2 2006.245.07:47:43.57#ibcon#wrote, iclass 35, count 2 2006.245.07:47:43.57#ibcon#about to read 3, iclass 35, count 2 2006.245.07:47:43.59#ibcon#read 3, iclass 35, count 2 2006.245.07:47:43.59#ibcon#about to read 4, iclass 35, count 2 2006.245.07:47:43.59#ibcon#read 4, iclass 35, count 2 2006.245.07:47:43.59#ibcon#about to read 5, iclass 35, count 2 2006.245.07:47:43.59#ibcon#read 5, iclass 35, count 2 2006.245.07:47:43.59#ibcon#about to read 6, iclass 35, count 2 2006.245.07:47:43.59#ibcon#read 6, iclass 35, count 2 2006.245.07:47:43.59#ibcon#end of sib2, iclass 35, count 2 2006.245.07:47:43.59#ibcon#*mode == 0, iclass 35, count 2 2006.245.07:47:43.59#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.07:47:43.59#ibcon#[27=AT04-04\r\n] 2006.245.07:47:43.59#ibcon#*before write, iclass 35, count 2 2006.245.07:47:43.59#ibcon#enter sib2, iclass 35, count 2 2006.245.07:47:43.59#ibcon#flushed, iclass 35, count 2 2006.245.07:47:43.59#ibcon#about to write, iclass 35, count 2 2006.245.07:47:43.59#ibcon#wrote, iclass 35, count 2 2006.245.07:47:43.59#ibcon#about to read 3, iclass 35, count 2 2006.245.07:47:43.62#ibcon#read 3, iclass 35, count 2 2006.245.07:47:43.62#ibcon#about to read 4, iclass 35, count 2 2006.245.07:47:43.62#ibcon#read 4, iclass 35, count 2 2006.245.07:47:43.62#ibcon#about to read 5, iclass 35, count 2 2006.245.07:47:43.62#ibcon#read 5, iclass 35, count 2 2006.245.07:47:43.62#ibcon#about to read 6, iclass 35, count 2 2006.245.07:47:43.62#ibcon#read 6, iclass 35, count 2 2006.245.07:47:43.62#ibcon#end of sib2, iclass 35, count 2 2006.245.07:47:43.62#ibcon#*after write, iclass 35, count 2 2006.245.07:47:43.62#ibcon#*before return 0, iclass 35, count 2 2006.245.07:47:43.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:43.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:47:43.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.07:47:43.62#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:43.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:43.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:43.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:43.74#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:47:43.74#ibcon#first serial, iclass 35, count 0 2006.245.07:47:43.74#ibcon#enter sib2, iclass 35, count 0 2006.245.07:47:43.74#ibcon#flushed, iclass 35, count 0 2006.245.07:47:43.74#ibcon#about to write, iclass 35, count 0 2006.245.07:47:43.74#ibcon#wrote, iclass 35, count 0 2006.245.07:47:43.74#ibcon#about to read 3, iclass 35, count 0 2006.245.07:47:43.76#ibcon#read 3, iclass 35, count 0 2006.245.07:47:43.76#ibcon#about to read 4, iclass 35, count 0 2006.245.07:47:43.76#ibcon#read 4, iclass 35, count 0 2006.245.07:47:43.76#ibcon#about to read 5, iclass 35, count 0 2006.245.07:47:43.76#ibcon#read 5, iclass 35, count 0 2006.245.07:47:43.76#ibcon#about to read 6, iclass 35, count 0 2006.245.07:47:43.76#ibcon#read 6, iclass 35, count 0 2006.245.07:47:43.76#ibcon#end of sib2, iclass 35, count 0 2006.245.07:47:43.76#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:47:43.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:47:43.76#ibcon#[27=USB\r\n] 2006.245.07:47:43.76#ibcon#*before write, iclass 35, count 0 2006.245.07:47:43.76#ibcon#enter sib2, iclass 35, count 0 2006.245.07:47:43.76#ibcon#flushed, iclass 35, count 0 2006.245.07:47:43.76#ibcon#about to write, iclass 35, count 0 2006.245.07:47:43.76#ibcon#wrote, iclass 35, count 0 2006.245.07:47:43.76#ibcon#about to read 3, iclass 35, count 0 2006.245.07:47:43.79#ibcon#read 3, iclass 35, count 0 2006.245.07:47:43.79#ibcon#about to read 4, iclass 35, count 0 2006.245.07:47:43.79#ibcon#read 4, iclass 35, count 0 2006.245.07:47:43.79#ibcon#about to read 5, iclass 35, count 0 2006.245.07:47:43.79#ibcon#read 5, iclass 35, count 0 2006.245.07:47:43.79#ibcon#about to read 6, iclass 35, count 0 2006.245.07:47:43.79#ibcon#read 6, iclass 35, count 0 2006.245.07:47:43.79#ibcon#end of sib2, iclass 35, count 0 2006.245.07:47:43.79#ibcon#*after write, iclass 35, count 0 2006.245.07:47:43.79#ibcon#*before return 0, iclass 35, count 0 2006.245.07:47:43.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:43.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:47:43.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:47:43.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:47:43.79$vc4f8/vblo=5,744.99 2006.245.07:47:43.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.07:47:43.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.07:47:43.79#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:43.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:43.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:43.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:43.79#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:47:43.79#ibcon#first serial, iclass 37, count 0 2006.245.07:47:43.79#ibcon#enter sib2, iclass 37, count 0 2006.245.07:47:43.79#ibcon#flushed, iclass 37, count 0 2006.245.07:47:43.79#ibcon#about to write, iclass 37, count 0 2006.245.07:47:43.79#ibcon#wrote, iclass 37, count 0 2006.245.07:47:43.79#ibcon#about to read 3, iclass 37, count 0 2006.245.07:47:43.81#ibcon#read 3, iclass 37, count 0 2006.245.07:47:43.81#ibcon#about to read 4, iclass 37, count 0 2006.245.07:47:43.81#ibcon#read 4, iclass 37, count 0 2006.245.07:47:43.81#ibcon#about to read 5, iclass 37, count 0 2006.245.07:47:43.81#ibcon#read 5, iclass 37, count 0 2006.245.07:47:43.81#ibcon#about to read 6, iclass 37, count 0 2006.245.07:47:43.81#ibcon#read 6, iclass 37, count 0 2006.245.07:47:43.81#ibcon#end of sib2, iclass 37, count 0 2006.245.07:47:43.81#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:47:43.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:47:43.81#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:47:43.81#ibcon#*before write, iclass 37, count 0 2006.245.07:47:43.81#ibcon#enter sib2, iclass 37, count 0 2006.245.07:47:43.81#ibcon#flushed, iclass 37, count 0 2006.245.07:47:43.81#ibcon#about to write, iclass 37, count 0 2006.245.07:47:43.81#ibcon#wrote, iclass 37, count 0 2006.245.07:47:43.81#ibcon#about to read 3, iclass 37, count 0 2006.245.07:47:43.85#ibcon#read 3, iclass 37, count 0 2006.245.07:47:43.85#ibcon#about to read 4, iclass 37, count 0 2006.245.07:47:43.85#ibcon#read 4, iclass 37, count 0 2006.245.07:47:43.85#ibcon#about to read 5, iclass 37, count 0 2006.245.07:47:43.85#ibcon#read 5, iclass 37, count 0 2006.245.07:47:43.85#ibcon#about to read 6, iclass 37, count 0 2006.245.07:47:43.85#ibcon#read 6, iclass 37, count 0 2006.245.07:47:43.85#ibcon#end of sib2, iclass 37, count 0 2006.245.07:47:43.85#ibcon#*after write, iclass 37, count 0 2006.245.07:47:43.85#ibcon#*before return 0, iclass 37, count 0 2006.245.07:47:43.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:43.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:47:43.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:47:43.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:47:43.85$vc4f8/vb=5,3 2006.245.07:47:43.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.07:47:43.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.07:47:43.85#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:43.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:43.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:43.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:43.91#ibcon#enter wrdev, iclass 39, count 2 2006.245.07:47:43.91#ibcon#first serial, iclass 39, count 2 2006.245.07:47:43.91#ibcon#enter sib2, iclass 39, count 2 2006.245.07:47:43.91#ibcon#flushed, iclass 39, count 2 2006.245.07:47:43.91#ibcon#about to write, iclass 39, count 2 2006.245.07:47:43.91#ibcon#wrote, iclass 39, count 2 2006.245.07:47:43.91#ibcon#about to read 3, iclass 39, count 2 2006.245.07:47:43.93#ibcon#read 3, iclass 39, count 2 2006.245.07:47:43.93#ibcon#about to read 4, iclass 39, count 2 2006.245.07:47:43.93#ibcon#read 4, iclass 39, count 2 2006.245.07:47:43.93#ibcon#about to read 5, iclass 39, count 2 2006.245.07:47:43.93#ibcon#read 5, iclass 39, count 2 2006.245.07:47:43.93#ibcon#about to read 6, iclass 39, count 2 2006.245.07:47:43.93#ibcon#read 6, iclass 39, count 2 2006.245.07:47:43.93#ibcon#end of sib2, iclass 39, count 2 2006.245.07:47:43.93#ibcon#*mode == 0, iclass 39, count 2 2006.245.07:47:43.93#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.07:47:43.93#ibcon#[27=AT05-03\r\n] 2006.245.07:47:43.93#ibcon#*before write, iclass 39, count 2 2006.245.07:47:43.93#ibcon#enter sib2, iclass 39, count 2 2006.245.07:47:43.93#ibcon#flushed, iclass 39, count 2 2006.245.07:47:43.93#ibcon#about to write, iclass 39, count 2 2006.245.07:47:43.93#ibcon#wrote, iclass 39, count 2 2006.245.07:47:43.93#ibcon#about to read 3, iclass 39, count 2 2006.245.07:47:43.96#ibcon#read 3, iclass 39, count 2 2006.245.07:47:43.96#ibcon#about to read 4, iclass 39, count 2 2006.245.07:47:43.96#ibcon#read 4, iclass 39, count 2 2006.245.07:47:43.96#ibcon#about to read 5, iclass 39, count 2 2006.245.07:47:43.96#ibcon#read 5, iclass 39, count 2 2006.245.07:47:43.96#ibcon#about to read 6, iclass 39, count 2 2006.245.07:47:43.96#ibcon#read 6, iclass 39, count 2 2006.245.07:47:43.96#ibcon#end of sib2, iclass 39, count 2 2006.245.07:47:43.96#ibcon#*after write, iclass 39, count 2 2006.245.07:47:43.96#ibcon#*before return 0, iclass 39, count 2 2006.245.07:47:43.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:43.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:47:43.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.07:47:43.96#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:43.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:44.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:44.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:44.08#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:47:44.08#ibcon#first serial, iclass 39, count 0 2006.245.07:47:44.08#ibcon#enter sib2, iclass 39, count 0 2006.245.07:47:44.08#ibcon#flushed, iclass 39, count 0 2006.245.07:47:44.08#ibcon#about to write, iclass 39, count 0 2006.245.07:47:44.08#ibcon#wrote, iclass 39, count 0 2006.245.07:47:44.08#ibcon#about to read 3, iclass 39, count 0 2006.245.07:47:44.11#ibcon#read 3, iclass 39, count 0 2006.245.07:47:44.11#ibcon#about to read 4, iclass 39, count 0 2006.245.07:47:44.11#ibcon#read 4, iclass 39, count 0 2006.245.07:47:44.11#ibcon#about to read 5, iclass 39, count 0 2006.245.07:47:44.11#ibcon#read 5, iclass 39, count 0 2006.245.07:47:44.11#ibcon#about to read 6, iclass 39, count 0 2006.245.07:47:44.11#ibcon#read 6, iclass 39, count 0 2006.245.07:47:44.11#ibcon#end of sib2, iclass 39, count 0 2006.245.07:47:44.11#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:47:44.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:47:44.11#ibcon#[27=USB\r\n] 2006.245.07:47:44.11#ibcon#*before write, iclass 39, count 0 2006.245.07:47:44.11#ibcon#enter sib2, iclass 39, count 0 2006.245.07:47:44.11#ibcon#flushed, iclass 39, count 0 2006.245.07:47:44.11#ibcon#about to write, iclass 39, count 0 2006.245.07:47:44.11#ibcon#wrote, iclass 39, count 0 2006.245.07:47:44.11#ibcon#about to read 3, iclass 39, count 0 2006.245.07:47:44.14#ibcon#read 3, iclass 39, count 0 2006.245.07:47:44.14#ibcon#about to read 4, iclass 39, count 0 2006.245.07:47:44.14#ibcon#read 4, iclass 39, count 0 2006.245.07:47:44.14#ibcon#about to read 5, iclass 39, count 0 2006.245.07:47:44.14#ibcon#read 5, iclass 39, count 0 2006.245.07:47:44.14#ibcon#about to read 6, iclass 39, count 0 2006.245.07:47:44.14#ibcon#read 6, iclass 39, count 0 2006.245.07:47:44.14#ibcon#end of sib2, iclass 39, count 0 2006.245.07:47:44.14#ibcon#*after write, iclass 39, count 0 2006.245.07:47:44.14#ibcon#*before return 0, iclass 39, count 0 2006.245.07:47:44.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:44.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:47:44.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:47:44.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:47:44.14$vc4f8/vblo=6,752.99 2006.245.07:47:44.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.07:47:44.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.07:47:44.14#ibcon#ireg 17 cls_cnt 0 2006.245.07:47:44.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:44.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:44.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:44.14#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:47:44.14#ibcon#first serial, iclass 3, count 0 2006.245.07:47:44.14#ibcon#enter sib2, iclass 3, count 0 2006.245.07:47:44.14#ibcon#flushed, iclass 3, count 0 2006.245.07:47:44.14#ibcon#about to write, iclass 3, count 0 2006.245.07:47:44.14#ibcon#wrote, iclass 3, count 0 2006.245.07:47:44.14#ibcon#about to read 3, iclass 3, count 0 2006.245.07:47:44.16#ibcon#read 3, iclass 3, count 0 2006.245.07:47:44.16#ibcon#about to read 4, iclass 3, count 0 2006.245.07:47:44.16#ibcon#read 4, iclass 3, count 0 2006.245.07:47:44.16#ibcon#about to read 5, iclass 3, count 0 2006.245.07:47:44.16#ibcon#read 5, iclass 3, count 0 2006.245.07:47:44.16#ibcon#about to read 6, iclass 3, count 0 2006.245.07:47:44.16#ibcon#read 6, iclass 3, count 0 2006.245.07:47:44.16#ibcon#end of sib2, iclass 3, count 0 2006.245.07:47:44.16#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:47:44.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:47:44.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:47:44.16#ibcon#*before write, iclass 3, count 0 2006.245.07:47:44.16#ibcon#enter sib2, iclass 3, count 0 2006.245.07:47:44.16#ibcon#flushed, iclass 3, count 0 2006.245.07:47:44.16#ibcon#about to write, iclass 3, count 0 2006.245.07:47:44.16#ibcon#wrote, iclass 3, count 0 2006.245.07:47:44.16#ibcon#about to read 3, iclass 3, count 0 2006.245.07:47:44.20#ibcon#read 3, iclass 3, count 0 2006.245.07:47:44.20#ibcon#about to read 4, iclass 3, count 0 2006.245.07:47:44.20#ibcon#read 4, iclass 3, count 0 2006.245.07:47:44.20#ibcon#about to read 5, iclass 3, count 0 2006.245.07:47:44.20#ibcon#read 5, iclass 3, count 0 2006.245.07:47:44.20#ibcon#about to read 6, iclass 3, count 0 2006.245.07:47:44.20#ibcon#read 6, iclass 3, count 0 2006.245.07:47:44.20#ibcon#end of sib2, iclass 3, count 0 2006.245.07:47:44.20#ibcon#*after write, iclass 3, count 0 2006.245.07:47:44.20#ibcon#*before return 0, iclass 3, count 0 2006.245.07:47:44.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:44.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:47:44.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:47:44.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:47:44.20$vc4f8/vb=6,3 2006.245.07:47:44.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.07:47:44.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.07:47:44.20#ibcon#ireg 11 cls_cnt 2 2006.245.07:47:44.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:44.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:44.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:44.26#ibcon#enter wrdev, iclass 5, count 2 2006.245.07:47:44.26#ibcon#first serial, iclass 5, count 2 2006.245.07:47:44.26#ibcon#enter sib2, iclass 5, count 2 2006.245.07:47:44.26#ibcon#flushed, iclass 5, count 2 2006.245.07:47:44.26#ibcon#about to write, iclass 5, count 2 2006.245.07:47:44.26#ibcon#wrote, iclass 5, count 2 2006.245.07:47:44.26#ibcon#about to read 3, iclass 5, count 2 2006.245.07:47:44.28#ibcon#read 3, iclass 5, count 2 2006.245.07:47:44.28#ibcon#about to read 4, iclass 5, count 2 2006.245.07:47:44.28#ibcon#read 4, iclass 5, count 2 2006.245.07:47:44.28#ibcon#about to read 5, iclass 5, count 2 2006.245.07:47:44.28#ibcon#read 5, iclass 5, count 2 2006.245.07:47:44.28#ibcon#about to read 6, iclass 5, count 2 2006.245.07:47:44.28#ibcon#read 6, iclass 5, count 2 2006.245.07:47:44.28#ibcon#end of sib2, iclass 5, count 2 2006.245.07:47:44.28#ibcon#*mode == 0, iclass 5, count 2 2006.245.07:47:44.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.07:47:44.28#ibcon#[27=AT06-03\r\n] 2006.245.07:47:44.28#ibcon#*before write, iclass 5, count 2 2006.245.07:47:44.28#ibcon#enter sib2, iclass 5, count 2 2006.245.07:47:44.28#ibcon#flushed, iclass 5, count 2 2006.245.07:47:44.28#ibcon#about to write, iclass 5, count 2 2006.245.07:47:44.28#ibcon#wrote, iclass 5, count 2 2006.245.07:47:44.28#ibcon#about to read 3, iclass 5, count 2 2006.245.07:47:44.31#ibcon#read 3, iclass 5, count 2 2006.245.07:47:44.31#ibcon#about to read 4, iclass 5, count 2 2006.245.07:47:44.31#ibcon#read 4, iclass 5, count 2 2006.245.07:47:44.31#ibcon#about to read 5, iclass 5, count 2 2006.245.07:47:44.31#ibcon#read 5, iclass 5, count 2 2006.245.07:47:44.31#ibcon#about to read 6, iclass 5, count 2 2006.245.07:47:44.31#ibcon#read 6, iclass 5, count 2 2006.245.07:47:44.31#ibcon#end of sib2, iclass 5, count 2 2006.245.07:47:44.31#ibcon#*after write, iclass 5, count 2 2006.245.07:47:44.31#ibcon#*before return 0, iclass 5, count 2 2006.245.07:47:44.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:44.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:47:44.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.07:47:44.31#ibcon#ireg 7 cls_cnt 0 2006.245.07:47:44.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:44.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:44.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:44.43#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:47:44.43#ibcon#first serial, iclass 5, count 0 2006.245.07:47:44.43#ibcon#enter sib2, iclass 5, count 0 2006.245.07:47:44.43#ibcon#flushed, iclass 5, count 0 2006.245.07:47:44.43#ibcon#about to write, iclass 5, count 0 2006.245.07:47:44.43#ibcon#wrote, iclass 5, count 0 2006.245.07:47:44.43#ibcon#about to read 3, iclass 5, count 0 2006.245.07:47:44.45#ibcon#read 3, iclass 5, count 0 2006.245.07:47:44.45#ibcon#about to read 4, iclass 5, count 0 2006.245.07:47:44.45#ibcon#read 4, iclass 5, count 0 2006.245.07:47:44.45#ibcon#about to read 5, iclass 5, count 0 2006.245.07:47:44.45#ibcon#read 5, iclass 5, count 0 2006.245.07:47:44.45#ibcon#about to read 6, iclass 5, count 0 2006.245.07:47:44.45#ibcon#read 6, iclass 5, count 0 2006.245.07:47:44.45#ibcon#end of sib2, iclass 5, count 0 2006.245.07:47:44.45#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:47:44.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:47:44.45#ibcon#[27=USB\r\n] 2006.245.07:47:44.45#ibcon#*before write, iclass 5, count 0 2006.245.07:47:44.45#ibcon#enter sib2, iclass 5, count 0 2006.245.07:47:44.45#ibcon#flushed, iclass 5, count 0 2006.245.07:47:44.45#ibcon#about to write, iclass 5, count 0 2006.245.07:47:44.45#ibcon#wrote, iclass 5, count 0 2006.245.07:47:44.45#ibcon#about to read 3, iclass 5, count 0 2006.245.07:47:44.48#ibcon#read 3, iclass 5, count 0 2006.245.07:47:44.48#ibcon#about to read 4, iclass 5, count 0 2006.245.07:47:44.48#ibcon#read 4, iclass 5, count 0 2006.245.07:47:44.48#ibcon#about to read 5, iclass 5, count 0 2006.245.07:47:44.48#ibcon#read 5, iclass 5, count 0 2006.245.07:47:44.48#ibcon#about to read 6, iclass 5, count 0 2006.245.07:47:44.48#ibcon#read 6, iclass 5, count 0 2006.245.07:47:44.48#ibcon#end of sib2, iclass 5, count 0 2006.245.07:47:44.48#ibcon#*after write, iclass 5, count 0 2006.245.07:47:44.48#ibcon#*before return 0, iclass 5, count 0 2006.245.07:47:44.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:44.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:47:44.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:47:44.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:47:44.48$vc4f8/vabw=wide 2006.245.07:47:44.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:47:44.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:47:44.48#ibcon#ireg 8 cls_cnt 0 2006.245.07:47:44.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:44.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:44.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:44.48#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:47:44.48#ibcon#first serial, iclass 7, count 0 2006.245.07:47:44.48#ibcon#enter sib2, iclass 7, count 0 2006.245.07:47:44.48#ibcon#flushed, iclass 7, count 0 2006.245.07:47:44.48#ibcon#about to write, iclass 7, count 0 2006.245.07:47:44.48#ibcon#wrote, iclass 7, count 0 2006.245.07:47:44.48#ibcon#about to read 3, iclass 7, count 0 2006.245.07:47:44.50#ibcon#read 3, iclass 7, count 0 2006.245.07:47:44.50#ibcon#about to read 4, iclass 7, count 0 2006.245.07:47:44.50#ibcon#read 4, iclass 7, count 0 2006.245.07:47:44.50#ibcon#about to read 5, iclass 7, count 0 2006.245.07:47:44.50#ibcon#read 5, iclass 7, count 0 2006.245.07:47:44.50#ibcon#about to read 6, iclass 7, count 0 2006.245.07:47:44.50#ibcon#read 6, iclass 7, count 0 2006.245.07:47:44.50#ibcon#end of sib2, iclass 7, count 0 2006.245.07:47:44.50#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:47:44.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:47:44.50#ibcon#[25=BW32\r\n] 2006.245.07:47:44.50#ibcon#*before write, iclass 7, count 0 2006.245.07:47:44.50#ibcon#enter sib2, iclass 7, count 0 2006.245.07:47:44.50#ibcon#flushed, iclass 7, count 0 2006.245.07:47:44.50#ibcon#about to write, iclass 7, count 0 2006.245.07:47:44.50#ibcon#wrote, iclass 7, count 0 2006.245.07:47:44.50#ibcon#about to read 3, iclass 7, count 0 2006.245.07:47:44.53#ibcon#read 3, iclass 7, count 0 2006.245.07:47:44.53#ibcon#about to read 4, iclass 7, count 0 2006.245.07:47:44.53#ibcon#read 4, iclass 7, count 0 2006.245.07:47:44.53#ibcon#about to read 5, iclass 7, count 0 2006.245.07:47:44.53#ibcon#read 5, iclass 7, count 0 2006.245.07:47:44.53#ibcon#about to read 6, iclass 7, count 0 2006.245.07:47:44.53#ibcon#read 6, iclass 7, count 0 2006.245.07:47:44.53#ibcon#end of sib2, iclass 7, count 0 2006.245.07:47:44.53#ibcon#*after write, iclass 7, count 0 2006.245.07:47:44.53#ibcon#*before return 0, iclass 7, count 0 2006.245.07:47:44.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:44.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:47:44.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:47:44.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:47:44.53$vc4f8/vbbw=wide 2006.245.07:47:44.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:47:44.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:47:44.53#ibcon#ireg 8 cls_cnt 0 2006.245.07:47:44.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:47:44.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:47:44.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:47:44.60#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:47:44.60#ibcon#first serial, iclass 11, count 0 2006.245.07:47:44.60#ibcon#enter sib2, iclass 11, count 0 2006.245.07:47:44.60#ibcon#flushed, iclass 11, count 0 2006.245.07:47:44.60#ibcon#about to write, iclass 11, count 0 2006.245.07:47:44.60#ibcon#wrote, iclass 11, count 0 2006.245.07:47:44.60#ibcon#about to read 3, iclass 11, count 0 2006.245.07:47:44.62#ibcon#read 3, iclass 11, count 0 2006.245.07:47:44.62#ibcon#about to read 4, iclass 11, count 0 2006.245.07:47:44.62#ibcon#read 4, iclass 11, count 0 2006.245.07:47:44.62#ibcon#about to read 5, iclass 11, count 0 2006.245.07:47:44.62#ibcon#read 5, iclass 11, count 0 2006.245.07:47:44.62#ibcon#about to read 6, iclass 11, count 0 2006.245.07:47:44.62#ibcon#read 6, iclass 11, count 0 2006.245.07:47:44.62#ibcon#end of sib2, iclass 11, count 0 2006.245.07:47:44.62#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:47:44.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:47:44.62#ibcon#[27=BW32\r\n] 2006.245.07:47:44.62#ibcon#*before write, iclass 11, count 0 2006.245.07:47:44.62#ibcon#enter sib2, iclass 11, count 0 2006.245.07:47:44.62#ibcon#flushed, iclass 11, count 0 2006.245.07:47:44.62#ibcon#about to write, iclass 11, count 0 2006.245.07:47:44.62#ibcon#wrote, iclass 11, count 0 2006.245.07:47:44.62#ibcon#about to read 3, iclass 11, count 0 2006.245.07:47:44.65#ibcon#read 3, iclass 11, count 0 2006.245.07:47:44.65#ibcon#about to read 4, iclass 11, count 0 2006.245.07:47:44.65#ibcon#read 4, iclass 11, count 0 2006.245.07:47:44.65#ibcon#about to read 5, iclass 11, count 0 2006.245.07:47:44.65#ibcon#read 5, iclass 11, count 0 2006.245.07:47:44.65#ibcon#about to read 6, iclass 11, count 0 2006.245.07:47:44.65#ibcon#read 6, iclass 11, count 0 2006.245.07:47:44.65#ibcon#end of sib2, iclass 11, count 0 2006.245.07:47:44.65#ibcon#*after write, iclass 11, count 0 2006.245.07:47:44.65#ibcon#*before return 0, iclass 11, count 0 2006.245.07:47:44.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:47:44.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:47:44.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:47:44.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:47:44.65$4f8m12a/ifd4f 2006.245.07:47:44.65$ifd4f/lo= 2006.245.07:47:44.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:47:44.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:47:44.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:47:44.65$ifd4f/patch= 2006.245.07:47:44.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:47:44.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:47:44.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:47:44.65$4f8m12a/"form=m,16.000,1:2 2006.245.07:47:44.65$4f8m12a/"tpicd 2006.245.07:47:44.65$4f8m12a/echo=off 2006.245.07:47:44.65$4f8m12a/xlog=off 2006.245.07:47:44.65:!2006.245.07:48:30 2006.245.07:48:13.13#trakl#Source acquired 2006.245.07:48:13.13#flagr#flagr/antenna,acquired 2006.245.07:48:30.00:preob 2006.245.07:48:30.13/onsource/TRACKING 2006.245.07:48:30.13:!2006.245.07:48:40 2006.245.07:48:40.00:data_valid=on 2006.245.07:48:40.00:midob 2006.245.07:48:40.13/onsource/TRACKING 2006.245.07:48:40.13/wx/27.37,1004.5,69 2006.245.07:48:40.22/cable/+6.4120E-03 2006.245.07:48:41.31/va/01,08,usb,yes,31,33 2006.245.07:48:41.31/va/02,07,usb,yes,31,33 2006.245.07:48:41.31/va/03,06,usb,yes,33,33 2006.245.07:48:41.31/va/04,07,usb,yes,32,35 2006.245.07:48:41.31/va/05,07,usb,yes,34,35 2006.245.07:48:41.31/va/06,07,usb,yes,29,29 2006.245.07:48:41.31/va/07,07,usb,yes,29,29 2006.245.07:48:41.31/va/08,08,usb,yes,25,25 2006.245.07:48:41.54/valo/01,532.99,yes,locked 2006.245.07:48:41.54/valo/02,572.99,yes,locked 2006.245.07:48:41.54/valo/03,672.99,yes,locked 2006.245.07:48:41.54/valo/04,832.99,yes,locked 2006.245.07:48:41.54/valo/05,652.99,yes,locked 2006.245.07:48:41.54/valo/06,772.99,yes,locked 2006.245.07:48:41.54/valo/07,832.99,yes,locked 2006.245.07:48:41.54/valo/08,852.99,yes,locked 2006.245.07:48:42.63/vb/01,04,usb,yes,31,30 2006.245.07:48:42.63/vb/02,04,usb,yes,33,34 2006.245.07:48:42.63/vb/03,04,usb,yes,29,33 2006.245.07:48:42.63/vb/04,04,usb,yes,30,30 2006.245.07:48:42.63/vb/05,03,usb,yes,35,40 2006.245.07:48:42.63/vb/06,03,usb,yes,36,39 2006.245.07:48:42.63/vb/07,04,usb,yes,31,31 2006.245.07:48:42.63/vb/08,03,usb,yes,36,40 2006.245.07:48:42.86/vblo/01,632.99,yes,locked 2006.245.07:48:42.86/vblo/02,640.99,yes,locked 2006.245.07:48:42.86/vblo/03,656.99,yes,locked 2006.245.07:48:42.86/vblo/04,712.99,yes,locked 2006.245.07:48:42.86/vblo/05,744.99,yes,locked 2006.245.07:48:42.86/vblo/06,752.99,yes,locked 2006.245.07:48:42.86/vblo/07,734.99,yes,locked 2006.245.07:48:42.86/vblo/08,744.99,yes,locked 2006.245.07:48:43.01/vabw/8 2006.245.07:48:43.16/vbbw/8 2006.245.07:48:43.25/xfe/off,on,13.7 2006.245.07:48:43.62/ifatt/23,28,28,28 2006.245.07:48:44.08/fmout-gps/S +4.42E-07 2006.245.07:48:44.12:!2006.245.07:50:00 2006.245.07:50:00.00:data_valid=off 2006.245.07:50:00.00:postob 2006.245.07:50:00.07/cable/+6.4105E-03 2006.245.07:50:00.07/wx/27.36,1004.5,67 2006.245.07:50:01.08/fmout-gps/S +4.41E-07 2006.245.07:50:01.08:scan_name=245-0751,k06245,60 2006.245.07:50:01.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.245.07:50:02.14#flagr#flagr/antenna,new-source 2006.245.07:50:02.14:checkk5 2006.245.07:50:06.16/chk_autoobs//k5ts1?ERROR: timeout happened! 2006.245.07:50:06.65/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:50:07.41/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:50:08.15/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:50:08.65/chk_obsdata//k5ts1/T2450748??a.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.07:50:09.09/chk_obsdata//k5ts2/T2450748??b.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.07:50:09.49/chk_obsdata//k5ts3/T2450748??c.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.07:50:10.20/chk_obsdata//k5ts4/T2450748??d.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.07:50:11.26/k5log//k5ts1_log_newline 2006.245.07:50:12.05/k5log//k5ts2_log_newline 2006.245.07:50:12.91/k5log//k5ts3_log_newline 2006.245.07:50:14.10/k5log//k5ts4_log_newline 2006.245.07:50:14.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:50:14.23:4f8m12a=1 2006.245.07:50:14.23$4f8m12a/echo=on 2006.245.07:50:14.23$4f8m12a/pcalon 2006.245.07:50:14.23$pcalon/"no phase cal control is implemented here 2006.245.07:50:14.23$4f8m12a/"tpicd=stop 2006.245.07:50:14.23$4f8m12a/vc4f8 2006.245.07:50:14.23$vc4f8/valo=1,532.99 2006.245.07:50:14.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.07:50:14.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.07:50:14.23#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:14.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:14.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:14.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:14.23#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:50:14.23#ibcon#first serial, iclass 29, count 0 2006.245.07:50:14.23#ibcon#enter sib2, iclass 29, count 0 2006.245.07:50:14.23#ibcon#flushed, iclass 29, count 0 2006.245.07:50:14.23#ibcon#about to write, iclass 29, count 0 2006.245.07:50:14.23#ibcon#wrote, iclass 29, count 0 2006.245.07:50:14.23#ibcon#about to read 3, iclass 29, count 0 2006.245.07:50:14.26#ibcon#read 3, iclass 29, count 0 2006.245.07:50:14.26#ibcon#about to read 4, iclass 29, count 0 2006.245.07:50:14.26#ibcon#read 4, iclass 29, count 0 2006.245.07:50:14.26#ibcon#about to read 5, iclass 29, count 0 2006.245.07:50:14.26#ibcon#read 5, iclass 29, count 0 2006.245.07:50:14.26#ibcon#about to read 6, iclass 29, count 0 2006.245.07:50:14.26#ibcon#read 6, iclass 29, count 0 2006.245.07:50:14.26#ibcon#end of sib2, iclass 29, count 0 2006.245.07:50:14.26#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:50:14.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:50:14.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:50:14.26#ibcon#*before write, iclass 29, count 0 2006.245.07:50:14.26#ibcon#enter sib2, iclass 29, count 0 2006.245.07:50:14.26#ibcon#flushed, iclass 29, count 0 2006.245.07:50:14.26#ibcon#about to write, iclass 29, count 0 2006.245.07:50:14.26#ibcon#wrote, iclass 29, count 0 2006.245.07:50:14.26#ibcon#about to read 3, iclass 29, count 0 2006.245.07:50:14.31#ibcon#read 3, iclass 29, count 0 2006.245.07:50:14.31#ibcon#about to read 4, iclass 29, count 0 2006.245.07:50:14.31#ibcon#read 4, iclass 29, count 0 2006.245.07:50:14.31#ibcon#about to read 5, iclass 29, count 0 2006.245.07:50:14.31#ibcon#read 5, iclass 29, count 0 2006.245.07:50:14.31#ibcon#about to read 6, iclass 29, count 0 2006.245.07:50:14.31#ibcon#read 6, iclass 29, count 0 2006.245.07:50:14.31#ibcon#end of sib2, iclass 29, count 0 2006.245.07:50:14.31#ibcon#*after write, iclass 29, count 0 2006.245.07:50:14.31#ibcon#*before return 0, iclass 29, count 0 2006.245.07:50:14.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:14.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:14.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:50:14.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:50:14.31$vc4f8/va=1,8 2006.245.07:50:14.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.07:50:14.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.07:50:14.31#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:14.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:14.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:14.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:14.31#ibcon#enter wrdev, iclass 31, count 2 2006.245.07:50:14.31#ibcon#first serial, iclass 31, count 2 2006.245.07:50:14.31#ibcon#enter sib2, iclass 31, count 2 2006.245.07:50:14.31#ibcon#flushed, iclass 31, count 2 2006.245.07:50:14.31#ibcon#about to write, iclass 31, count 2 2006.245.07:50:14.31#ibcon#wrote, iclass 31, count 2 2006.245.07:50:14.31#ibcon#about to read 3, iclass 31, count 2 2006.245.07:50:14.33#ibcon#read 3, iclass 31, count 2 2006.245.07:50:14.33#ibcon#about to read 4, iclass 31, count 2 2006.245.07:50:14.33#ibcon#read 4, iclass 31, count 2 2006.245.07:50:14.33#ibcon#about to read 5, iclass 31, count 2 2006.245.07:50:14.33#ibcon#read 5, iclass 31, count 2 2006.245.07:50:14.33#ibcon#about to read 6, iclass 31, count 2 2006.245.07:50:14.33#ibcon#read 6, iclass 31, count 2 2006.245.07:50:14.33#ibcon#end of sib2, iclass 31, count 2 2006.245.07:50:14.33#ibcon#*mode == 0, iclass 31, count 2 2006.245.07:50:14.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.07:50:14.33#ibcon#[25=AT01-08\r\n] 2006.245.07:50:14.33#ibcon#*before write, iclass 31, count 2 2006.245.07:50:14.33#ibcon#enter sib2, iclass 31, count 2 2006.245.07:50:14.33#ibcon#flushed, iclass 31, count 2 2006.245.07:50:14.33#ibcon#about to write, iclass 31, count 2 2006.245.07:50:14.33#ibcon#wrote, iclass 31, count 2 2006.245.07:50:14.33#ibcon#about to read 3, iclass 31, count 2 2006.245.07:50:14.36#ibcon#read 3, iclass 31, count 2 2006.245.07:50:14.36#ibcon#about to read 4, iclass 31, count 2 2006.245.07:50:14.36#ibcon#read 4, iclass 31, count 2 2006.245.07:50:14.36#ibcon#about to read 5, iclass 31, count 2 2006.245.07:50:14.36#ibcon#read 5, iclass 31, count 2 2006.245.07:50:14.36#ibcon#about to read 6, iclass 31, count 2 2006.245.07:50:14.36#ibcon#read 6, iclass 31, count 2 2006.245.07:50:14.36#ibcon#end of sib2, iclass 31, count 2 2006.245.07:50:14.36#ibcon#*after write, iclass 31, count 2 2006.245.07:50:14.36#ibcon#*before return 0, iclass 31, count 2 2006.245.07:50:14.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:14.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:14.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.07:50:14.36#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:14.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:14.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:14.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:14.48#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:50:14.48#ibcon#first serial, iclass 31, count 0 2006.245.07:50:14.48#ibcon#enter sib2, iclass 31, count 0 2006.245.07:50:14.48#ibcon#flushed, iclass 31, count 0 2006.245.07:50:14.48#ibcon#about to write, iclass 31, count 0 2006.245.07:50:14.48#ibcon#wrote, iclass 31, count 0 2006.245.07:50:14.48#ibcon#about to read 3, iclass 31, count 0 2006.245.07:50:14.50#ibcon#read 3, iclass 31, count 0 2006.245.07:50:14.50#ibcon#about to read 4, iclass 31, count 0 2006.245.07:50:14.50#ibcon#read 4, iclass 31, count 0 2006.245.07:50:14.50#ibcon#about to read 5, iclass 31, count 0 2006.245.07:50:14.50#ibcon#read 5, iclass 31, count 0 2006.245.07:50:14.50#ibcon#about to read 6, iclass 31, count 0 2006.245.07:50:14.50#ibcon#read 6, iclass 31, count 0 2006.245.07:50:14.50#ibcon#end of sib2, iclass 31, count 0 2006.245.07:50:14.50#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:50:14.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:50:14.50#ibcon#[25=USB\r\n] 2006.245.07:50:14.50#ibcon#*before write, iclass 31, count 0 2006.245.07:50:14.50#ibcon#enter sib2, iclass 31, count 0 2006.245.07:50:14.50#ibcon#flushed, iclass 31, count 0 2006.245.07:50:14.50#ibcon#about to write, iclass 31, count 0 2006.245.07:50:14.50#ibcon#wrote, iclass 31, count 0 2006.245.07:50:14.50#ibcon#about to read 3, iclass 31, count 0 2006.245.07:50:14.53#ibcon#read 3, iclass 31, count 0 2006.245.07:50:14.53#ibcon#about to read 4, iclass 31, count 0 2006.245.07:50:14.53#ibcon#read 4, iclass 31, count 0 2006.245.07:50:14.53#ibcon#about to read 5, iclass 31, count 0 2006.245.07:50:14.53#ibcon#read 5, iclass 31, count 0 2006.245.07:50:14.53#ibcon#about to read 6, iclass 31, count 0 2006.245.07:50:14.53#ibcon#read 6, iclass 31, count 0 2006.245.07:50:14.53#ibcon#end of sib2, iclass 31, count 0 2006.245.07:50:14.53#ibcon#*after write, iclass 31, count 0 2006.245.07:50:14.53#ibcon#*before return 0, iclass 31, count 0 2006.245.07:50:14.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:14.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:14.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:50:14.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:50:14.53$vc4f8/valo=2,572.99 2006.245.07:50:14.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.07:50:14.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.07:50:14.53#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:14.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:14.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:14.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:14.53#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:50:14.53#ibcon#first serial, iclass 33, count 0 2006.245.07:50:14.53#ibcon#enter sib2, iclass 33, count 0 2006.245.07:50:14.53#ibcon#flushed, iclass 33, count 0 2006.245.07:50:14.53#ibcon#about to write, iclass 33, count 0 2006.245.07:50:14.53#ibcon#wrote, iclass 33, count 0 2006.245.07:50:14.53#ibcon#about to read 3, iclass 33, count 0 2006.245.07:50:14.55#ibcon#read 3, iclass 33, count 0 2006.245.07:50:14.55#ibcon#about to read 4, iclass 33, count 0 2006.245.07:50:14.55#ibcon#read 4, iclass 33, count 0 2006.245.07:50:14.55#ibcon#about to read 5, iclass 33, count 0 2006.245.07:50:14.55#ibcon#read 5, iclass 33, count 0 2006.245.07:50:14.55#ibcon#about to read 6, iclass 33, count 0 2006.245.07:50:14.55#ibcon#read 6, iclass 33, count 0 2006.245.07:50:14.55#ibcon#end of sib2, iclass 33, count 0 2006.245.07:50:14.55#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:50:14.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:50:14.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:50:14.55#ibcon#*before write, iclass 33, count 0 2006.245.07:50:14.55#ibcon#enter sib2, iclass 33, count 0 2006.245.07:50:14.55#ibcon#flushed, iclass 33, count 0 2006.245.07:50:14.55#ibcon#about to write, iclass 33, count 0 2006.245.07:50:14.55#ibcon#wrote, iclass 33, count 0 2006.245.07:50:14.55#ibcon#about to read 3, iclass 33, count 0 2006.245.07:50:14.59#ibcon#read 3, iclass 33, count 0 2006.245.07:50:14.59#ibcon#about to read 4, iclass 33, count 0 2006.245.07:50:14.59#ibcon#read 4, iclass 33, count 0 2006.245.07:50:14.59#ibcon#about to read 5, iclass 33, count 0 2006.245.07:50:14.59#ibcon#read 5, iclass 33, count 0 2006.245.07:50:14.59#ibcon#about to read 6, iclass 33, count 0 2006.245.07:50:14.59#ibcon#read 6, iclass 33, count 0 2006.245.07:50:14.59#ibcon#end of sib2, iclass 33, count 0 2006.245.07:50:14.59#ibcon#*after write, iclass 33, count 0 2006.245.07:50:14.59#ibcon#*before return 0, iclass 33, count 0 2006.245.07:50:14.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:14.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:14.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:50:14.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:50:14.59$vc4f8/va=2,7 2006.245.07:50:14.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.07:50:14.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.07:50:14.59#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:14.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:14.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:14.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:14.65#ibcon#enter wrdev, iclass 35, count 2 2006.245.07:50:14.65#ibcon#first serial, iclass 35, count 2 2006.245.07:50:14.65#ibcon#enter sib2, iclass 35, count 2 2006.245.07:50:14.65#ibcon#flushed, iclass 35, count 2 2006.245.07:50:14.65#ibcon#about to write, iclass 35, count 2 2006.245.07:50:14.65#ibcon#wrote, iclass 35, count 2 2006.245.07:50:14.65#ibcon#about to read 3, iclass 35, count 2 2006.245.07:50:14.67#ibcon#read 3, iclass 35, count 2 2006.245.07:50:14.67#ibcon#about to read 4, iclass 35, count 2 2006.245.07:50:14.67#ibcon#read 4, iclass 35, count 2 2006.245.07:50:14.67#ibcon#about to read 5, iclass 35, count 2 2006.245.07:50:14.67#ibcon#read 5, iclass 35, count 2 2006.245.07:50:14.67#ibcon#about to read 6, iclass 35, count 2 2006.245.07:50:14.67#ibcon#read 6, iclass 35, count 2 2006.245.07:50:14.67#ibcon#end of sib2, iclass 35, count 2 2006.245.07:50:14.67#ibcon#*mode == 0, iclass 35, count 2 2006.245.07:50:14.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.07:50:14.67#ibcon#[25=AT02-07\r\n] 2006.245.07:50:14.67#ibcon#*before write, iclass 35, count 2 2006.245.07:50:14.67#ibcon#enter sib2, iclass 35, count 2 2006.245.07:50:14.67#ibcon#flushed, iclass 35, count 2 2006.245.07:50:14.67#ibcon#about to write, iclass 35, count 2 2006.245.07:50:14.67#ibcon#wrote, iclass 35, count 2 2006.245.07:50:14.67#ibcon#about to read 3, iclass 35, count 2 2006.245.07:50:14.71#ibcon#read 3, iclass 35, count 2 2006.245.07:50:14.71#ibcon#about to read 4, iclass 35, count 2 2006.245.07:50:14.71#ibcon#read 4, iclass 35, count 2 2006.245.07:50:14.71#ibcon#about to read 5, iclass 35, count 2 2006.245.07:50:14.71#ibcon#read 5, iclass 35, count 2 2006.245.07:50:14.71#ibcon#about to read 6, iclass 35, count 2 2006.245.07:50:14.71#ibcon#read 6, iclass 35, count 2 2006.245.07:50:14.71#ibcon#end of sib2, iclass 35, count 2 2006.245.07:50:14.71#ibcon#*after write, iclass 35, count 2 2006.245.07:50:14.71#ibcon#*before return 0, iclass 35, count 2 2006.245.07:50:14.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:14.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:14.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.07:50:14.71#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:14.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:14.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:14.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:14.83#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:50:14.83#ibcon#first serial, iclass 35, count 0 2006.245.07:50:14.83#ibcon#enter sib2, iclass 35, count 0 2006.245.07:50:14.83#ibcon#flushed, iclass 35, count 0 2006.245.07:50:14.83#ibcon#about to write, iclass 35, count 0 2006.245.07:50:14.83#ibcon#wrote, iclass 35, count 0 2006.245.07:50:14.83#ibcon#about to read 3, iclass 35, count 0 2006.245.07:50:14.85#ibcon#read 3, iclass 35, count 0 2006.245.07:50:14.85#ibcon#about to read 4, iclass 35, count 0 2006.245.07:50:14.85#ibcon#read 4, iclass 35, count 0 2006.245.07:50:14.85#ibcon#about to read 5, iclass 35, count 0 2006.245.07:50:14.85#ibcon#read 5, iclass 35, count 0 2006.245.07:50:14.85#ibcon#about to read 6, iclass 35, count 0 2006.245.07:50:14.85#ibcon#read 6, iclass 35, count 0 2006.245.07:50:14.85#ibcon#end of sib2, iclass 35, count 0 2006.245.07:50:14.85#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:50:14.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:50:14.85#ibcon#[25=USB\r\n] 2006.245.07:50:14.85#ibcon#*before write, iclass 35, count 0 2006.245.07:50:14.85#ibcon#enter sib2, iclass 35, count 0 2006.245.07:50:14.85#ibcon#flushed, iclass 35, count 0 2006.245.07:50:14.85#ibcon#about to write, iclass 35, count 0 2006.245.07:50:14.85#ibcon#wrote, iclass 35, count 0 2006.245.07:50:14.85#ibcon#about to read 3, iclass 35, count 0 2006.245.07:50:14.88#ibcon#read 3, iclass 35, count 0 2006.245.07:50:14.88#ibcon#about to read 4, iclass 35, count 0 2006.245.07:50:14.88#ibcon#read 4, iclass 35, count 0 2006.245.07:50:14.88#ibcon#about to read 5, iclass 35, count 0 2006.245.07:50:14.88#ibcon#read 5, iclass 35, count 0 2006.245.07:50:14.88#ibcon#about to read 6, iclass 35, count 0 2006.245.07:50:14.88#ibcon#read 6, iclass 35, count 0 2006.245.07:50:14.88#ibcon#end of sib2, iclass 35, count 0 2006.245.07:50:14.88#ibcon#*after write, iclass 35, count 0 2006.245.07:50:14.88#ibcon#*before return 0, iclass 35, count 0 2006.245.07:50:14.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:14.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:14.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:50:14.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:50:14.88$vc4f8/valo=3,672.99 2006.245.07:50:14.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.07:50:14.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.07:50:14.88#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:14.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:14.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:14.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:14.88#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:50:14.88#ibcon#first serial, iclass 37, count 0 2006.245.07:50:14.88#ibcon#enter sib2, iclass 37, count 0 2006.245.07:50:14.88#ibcon#flushed, iclass 37, count 0 2006.245.07:50:14.88#ibcon#about to write, iclass 37, count 0 2006.245.07:50:14.88#ibcon#wrote, iclass 37, count 0 2006.245.07:50:14.88#ibcon#about to read 3, iclass 37, count 0 2006.245.07:50:14.90#ibcon#read 3, iclass 37, count 0 2006.245.07:50:14.90#ibcon#about to read 4, iclass 37, count 0 2006.245.07:50:14.90#ibcon#read 4, iclass 37, count 0 2006.245.07:50:14.90#ibcon#about to read 5, iclass 37, count 0 2006.245.07:50:14.90#ibcon#read 5, iclass 37, count 0 2006.245.07:50:14.90#ibcon#about to read 6, iclass 37, count 0 2006.245.07:50:14.90#ibcon#read 6, iclass 37, count 0 2006.245.07:50:14.90#ibcon#end of sib2, iclass 37, count 0 2006.245.07:50:14.90#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:50:14.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:50:14.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:50:14.90#ibcon#*before write, iclass 37, count 0 2006.245.07:50:14.90#ibcon#enter sib2, iclass 37, count 0 2006.245.07:50:14.90#ibcon#flushed, iclass 37, count 0 2006.245.07:50:14.90#ibcon#about to write, iclass 37, count 0 2006.245.07:50:14.90#ibcon#wrote, iclass 37, count 0 2006.245.07:50:14.90#ibcon#about to read 3, iclass 37, count 0 2006.245.07:50:14.94#ibcon#read 3, iclass 37, count 0 2006.245.07:50:14.94#ibcon#about to read 4, iclass 37, count 0 2006.245.07:50:14.94#ibcon#read 4, iclass 37, count 0 2006.245.07:50:14.94#ibcon#about to read 5, iclass 37, count 0 2006.245.07:50:14.94#ibcon#read 5, iclass 37, count 0 2006.245.07:50:14.94#ibcon#about to read 6, iclass 37, count 0 2006.245.07:50:14.94#ibcon#read 6, iclass 37, count 0 2006.245.07:50:14.94#ibcon#end of sib2, iclass 37, count 0 2006.245.07:50:14.94#ibcon#*after write, iclass 37, count 0 2006.245.07:50:14.94#ibcon#*before return 0, iclass 37, count 0 2006.245.07:50:14.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:14.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:14.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:50:14.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:50:14.94$vc4f8/va=3,6 2006.245.07:50:14.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.07:50:14.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.07:50:14.94#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:14.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:15.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:15.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:15.00#ibcon#enter wrdev, iclass 39, count 2 2006.245.07:50:15.00#ibcon#first serial, iclass 39, count 2 2006.245.07:50:15.00#ibcon#enter sib2, iclass 39, count 2 2006.245.07:50:15.00#ibcon#flushed, iclass 39, count 2 2006.245.07:50:15.00#ibcon#about to write, iclass 39, count 2 2006.245.07:50:15.00#ibcon#wrote, iclass 39, count 2 2006.245.07:50:15.00#ibcon#about to read 3, iclass 39, count 2 2006.245.07:50:15.02#ibcon#read 3, iclass 39, count 2 2006.245.07:50:15.02#ibcon#about to read 4, iclass 39, count 2 2006.245.07:50:15.02#ibcon#read 4, iclass 39, count 2 2006.245.07:50:15.02#ibcon#about to read 5, iclass 39, count 2 2006.245.07:50:15.02#ibcon#read 5, iclass 39, count 2 2006.245.07:50:15.02#ibcon#about to read 6, iclass 39, count 2 2006.245.07:50:15.02#ibcon#read 6, iclass 39, count 2 2006.245.07:50:15.02#ibcon#end of sib2, iclass 39, count 2 2006.245.07:50:15.02#ibcon#*mode == 0, iclass 39, count 2 2006.245.07:50:15.02#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.07:50:15.02#ibcon#[25=AT03-06\r\n] 2006.245.07:50:15.02#ibcon#*before write, iclass 39, count 2 2006.245.07:50:15.02#ibcon#enter sib2, iclass 39, count 2 2006.245.07:50:15.02#ibcon#flushed, iclass 39, count 2 2006.245.07:50:15.02#ibcon#about to write, iclass 39, count 2 2006.245.07:50:15.02#ibcon#wrote, iclass 39, count 2 2006.245.07:50:15.02#ibcon#about to read 3, iclass 39, count 2 2006.245.07:50:15.05#ibcon#read 3, iclass 39, count 2 2006.245.07:50:15.05#ibcon#about to read 4, iclass 39, count 2 2006.245.07:50:15.05#ibcon#read 4, iclass 39, count 2 2006.245.07:50:15.05#ibcon#about to read 5, iclass 39, count 2 2006.245.07:50:15.05#ibcon#read 5, iclass 39, count 2 2006.245.07:50:15.05#ibcon#about to read 6, iclass 39, count 2 2006.245.07:50:15.05#ibcon#read 6, iclass 39, count 2 2006.245.07:50:15.05#ibcon#end of sib2, iclass 39, count 2 2006.245.07:50:15.05#ibcon#*after write, iclass 39, count 2 2006.245.07:50:15.05#ibcon#*before return 0, iclass 39, count 2 2006.245.07:50:15.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:15.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:15.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.07:50:15.05#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:15.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:15.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:15.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:15.17#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:50:15.17#ibcon#first serial, iclass 39, count 0 2006.245.07:50:15.17#ibcon#enter sib2, iclass 39, count 0 2006.245.07:50:15.17#ibcon#flushed, iclass 39, count 0 2006.245.07:50:15.17#ibcon#about to write, iclass 39, count 0 2006.245.07:50:15.17#ibcon#wrote, iclass 39, count 0 2006.245.07:50:15.17#ibcon#about to read 3, iclass 39, count 0 2006.245.07:50:15.19#ibcon#read 3, iclass 39, count 0 2006.245.07:50:15.19#ibcon#about to read 4, iclass 39, count 0 2006.245.07:50:15.19#ibcon#read 4, iclass 39, count 0 2006.245.07:50:15.19#ibcon#about to read 5, iclass 39, count 0 2006.245.07:50:15.19#ibcon#read 5, iclass 39, count 0 2006.245.07:50:15.19#ibcon#about to read 6, iclass 39, count 0 2006.245.07:50:15.19#ibcon#read 6, iclass 39, count 0 2006.245.07:50:15.19#ibcon#end of sib2, iclass 39, count 0 2006.245.07:50:15.19#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:50:15.19#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:50:15.19#ibcon#[25=USB\r\n] 2006.245.07:50:15.19#ibcon#*before write, iclass 39, count 0 2006.245.07:50:15.19#ibcon#enter sib2, iclass 39, count 0 2006.245.07:50:15.19#ibcon#flushed, iclass 39, count 0 2006.245.07:50:15.19#ibcon#about to write, iclass 39, count 0 2006.245.07:50:15.19#ibcon#wrote, iclass 39, count 0 2006.245.07:50:15.19#ibcon#about to read 3, iclass 39, count 0 2006.245.07:50:15.22#ibcon#read 3, iclass 39, count 0 2006.245.07:50:15.22#ibcon#about to read 4, iclass 39, count 0 2006.245.07:50:15.22#ibcon#read 4, iclass 39, count 0 2006.245.07:50:15.22#ibcon#about to read 5, iclass 39, count 0 2006.245.07:50:15.22#ibcon#read 5, iclass 39, count 0 2006.245.07:50:15.22#ibcon#about to read 6, iclass 39, count 0 2006.245.07:50:15.22#ibcon#read 6, iclass 39, count 0 2006.245.07:50:15.22#ibcon#end of sib2, iclass 39, count 0 2006.245.07:50:15.22#ibcon#*after write, iclass 39, count 0 2006.245.07:50:15.22#ibcon#*before return 0, iclass 39, count 0 2006.245.07:50:15.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:15.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:15.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:50:15.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:50:15.22$vc4f8/valo=4,832.99 2006.245.07:50:15.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.07:50:15.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.07:50:15.22#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:15.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:15.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:15.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:15.22#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:50:15.22#ibcon#first serial, iclass 3, count 0 2006.245.07:50:15.22#ibcon#enter sib2, iclass 3, count 0 2006.245.07:50:15.22#ibcon#flushed, iclass 3, count 0 2006.245.07:50:15.22#ibcon#about to write, iclass 3, count 0 2006.245.07:50:15.22#ibcon#wrote, iclass 3, count 0 2006.245.07:50:15.22#ibcon#about to read 3, iclass 3, count 0 2006.245.07:50:15.24#ibcon#read 3, iclass 3, count 0 2006.245.07:50:15.24#ibcon#about to read 4, iclass 3, count 0 2006.245.07:50:15.24#ibcon#read 4, iclass 3, count 0 2006.245.07:50:15.24#ibcon#about to read 5, iclass 3, count 0 2006.245.07:50:15.24#ibcon#read 5, iclass 3, count 0 2006.245.07:50:15.24#ibcon#about to read 6, iclass 3, count 0 2006.245.07:50:15.24#ibcon#read 6, iclass 3, count 0 2006.245.07:50:15.24#ibcon#end of sib2, iclass 3, count 0 2006.245.07:50:15.24#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:50:15.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:50:15.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:50:15.24#ibcon#*before write, iclass 3, count 0 2006.245.07:50:15.24#ibcon#enter sib2, iclass 3, count 0 2006.245.07:50:15.24#ibcon#flushed, iclass 3, count 0 2006.245.07:50:15.24#ibcon#about to write, iclass 3, count 0 2006.245.07:50:15.24#ibcon#wrote, iclass 3, count 0 2006.245.07:50:15.24#ibcon#about to read 3, iclass 3, count 0 2006.245.07:50:15.28#ibcon#read 3, iclass 3, count 0 2006.245.07:50:15.28#ibcon#about to read 4, iclass 3, count 0 2006.245.07:50:15.28#ibcon#read 4, iclass 3, count 0 2006.245.07:50:15.28#ibcon#about to read 5, iclass 3, count 0 2006.245.07:50:15.28#ibcon#read 5, iclass 3, count 0 2006.245.07:50:15.28#ibcon#about to read 6, iclass 3, count 0 2006.245.07:50:15.28#ibcon#read 6, iclass 3, count 0 2006.245.07:50:15.28#ibcon#end of sib2, iclass 3, count 0 2006.245.07:50:15.28#ibcon#*after write, iclass 3, count 0 2006.245.07:50:15.28#ibcon#*before return 0, iclass 3, count 0 2006.245.07:50:15.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:15.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:15.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:50:15.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:50:15.28$vc4f8/va=4,7 2006.245.07:50:15.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.07:50:15.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.07:50:15.28#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:15.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:15.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:15.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:15.34#ibcon#enter wrdev, iclass 5, count 2 2006.245.07:50:15.34#ibcon#first serial, iclass 5, count 2 2006.245.07:50:15.34#ibcon#enter sib2, iclass 5, count 2 2006.245.07:50:15.34#ibcon#flushed, iclass 5, count 2 2006.245.07:50:15.34#ibcon#about to write, iclass 5, count 2 2006.245.07:50:15.34#ibcon#wrote, iclass 5, count 2 2006.245.07:50:15.34#ibcon#about to read 3, iclass 5, count 2 2006.245.07:50:15.36#ibcon#read 3, iclass 5, count 2 2006.245.07:50:15.36#ibcon#about to read 4, iclass 5, count 2 2006.245.07:50:15.36#ibcon#read 4, iclass 5, count 2 2006.245.07:50:15.36#ibcon#about to read 5, iclass 5, count 2 2006.245.07:50:15.36#ibcon#read 5, iclass 5, count 2 2006.245.07:50:15.36#ibcon#about to read 6, iclass 5, count 2 2006.245.07:50:15.36#ibcon#read 6, iclass 5, count 2 2006.245.07:50:15.36#ibcon#end of sib2, iclass 5, count 2 2006.245.07:50:15.36#ibcon#*mode == 0, iclass 5, count 2 2006.245.07:50:15.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.07:50:15.36#ibcon#[25=AT04-07\r\n] 2006.245.07:50:15.36#ibcon#*before write, iclass 5, count 2 2006.245.07:50:15.36#ibcon#enter sib2, iclass 5, count 2 2006.245.07:50:15.36#ibcon#flushed, iclass 5, count 2 2006.245.07:50:15.36#ibcon#about to write, iclass 5, count 2 2006.245.07:50:15.36#ibcon#wrote, iclass 5, count 2 2006.245.07:50:15.36#ibcon#about to read 3, iclass 5, count 2 2006.245.07:50:15.39#ibcon#read 3, iclass 5, count 2 2006.245.07:50:15.39#ibcon#about to read 4, iclass 5, count 2 2006.245.07:50:15.39#ibcon#read 4, iclass 5, count 2 2006.245.07:50:15.39#ibcon#about to read 5, iclass 5, count 2 2006.245.07:50:15.39#ibcon#read 5, iclass 5, count 2 2006.245.07:50:15.39#ibcon#about to read 6, iclass 5, count 2 2006.245.07:50:15.39#ibcon#read 6, iclass 5, count 2 2006.245.07:50:15.39#ibcon#end of sib2, iclass 5, count 2 2006.245.07:50:15.39#ibcon#*after write, iclass 5, count 2 2006.245.07:50:15.39#ibcon#*before return 0, iclass 5, count 2 2006.245.07:50:15.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:15.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:15.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.07:50:15.39#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:15.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:15.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:15.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:15.51#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:50:15.51#ibcon#first serial, iclass 5, count 0 2006.245.07:50:15.51#ibcon#enter sib2, iclass 5, count 0 2006.245.07:50:15.51#ibcon#flushed, iclass 5, count 0 2006.245.07:50:15.51#ibcon#about to write, iclass 5, count 0 2006.245.07:50:15.51#ibcon#wrote, iclass 5, count 0 2006.245.07:50:15.51#ibcon#about to read 3, iclass 5, count 0 2006.245.07:50:15.53#ibcon#read 3, iclass 5, count 0 2006.245.07:50:15.53#ibcon#about to read 4, iclass 5, count 0 2006.245.07:50:15.53#ibcon#read 4, iclass 5, count 0 2006.245.07:50:15.53#ibcon#about to read 5, iclass 5, count 0 2006.245.07:50:15.53#ibcon#read 5, iclass 5, count 0 2006.245.07:50:15.53#ibcon#about to read 6, iclass 5, count 0 2006.245.07:50:15.53#ibcon#read 6, iclass 5, count 0 2006.245.07:50:15.53#ibcon#end of sib2, iclass 5, count 0 2006.245.07:50:15.53#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:50:15.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:50:15.53#ibcon#[25=USB\r\n] 2006.245.07:50:15.53#ibcon#*before write, iclass 5, count 0 2006.245.07:50:15.53#ibcon#enter sib2, iclass 5, count 0 2006.245.07:50:15.53#ibcon#flushed, iclass 5, count 0 2006.245.07:50:15.53#ibcon#about to write, iclass 5, count 0 2006.245.07:50:15.53#ibcon#wrote, iclass 5, count 0 2006.245.07:50:15.53#ibcon#about to read 3, iclass 5, count 0 2006.245.07:50:15.56#ibcon#read 3, iclass 5, count 0 2006.245.07:50:15.56#ibcon#about to read 4, iclass 5, count 0 2006.245.07:50:15.56#ibcon#read 4, iclass 5, count 0 2006.245.07:50:15.56#ibcon#about to read 5, iclass 5, count 0 2006.245.07:50:15.56#ibcon#read 5, iclass 5, count 0 2006.245.07:50:15.56#ibcon#about to read 6, iclass 5, count 0 2006.245.07:50:15.56#ibcon#read 6, iclass 5, count 0 2006.245.07:50:15.56#ibcon#end of sib2, iclass 5, count 0 2006.245.07:50:15.56#ibcon#*after write, iclass 5, count 0 2006.245.07:50:15.56#ibcon#*before return 0, iclass 5, count 0 2006.245.07:50:15.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:15.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:15.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:50:15.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:50:15.56$vc4f8/valo=5,652.99 2006.245.07:50:15.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:50:15.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:50:15.56#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:15.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:15.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:15.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:15.56#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:50:15.56#ibcon#first serial, iclass 7, count 0 2006.245.07:50:15.56#ibcon#enter sib2, iclass 7, count 0 2006.245.07:50:15.56#ibcon#flushed, iclass 7, count 0 2006.245.07:50:15.56#ibcon#about to write, iclass 7, count 0 2006.245.07:50:15.56#ibcon#wrote, iclass 7, count 0 2006.245.07:50:15.56#ibcon#about to read 3, iclass 7, count 0 2006.245.07:50:15.58#ibcon#read 3, iclass 7, count 0 2006.245.07:50:15.58#ibcon#about to read 4, iclass 7, count 0 2006.245.07:50:15.58#ibcon#read 4, iclass 7, count 0 2006.245.07:50:15.58#ibcon#about to read 5, iclass 7, count 0 2006.245.07:50:15.58#ibcon#read 5, iclass 7, count 0 2006.245.07:50:15.58#ibcon#about to read 6, iclass 7, count 0 2006.245.07:50:15.58#ibcon#read 6, iclass 7, count 0 2006.245.07:50:15.58#ibcon#end of sib2, iclass 7, count 0 2006.245.07:50:15.58#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:50:15.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:50:15.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:50:15.58#ibcon#*before write, iclass 7, count 0 2006.245.07:50:15.58#ibcon#enter sib2, iclass 7, count 0 2006.245.07:50:15.58#ibcon#flushed, iclass 7, count 0 2006.245.07:50:15.58#ibcon#about to write, iclass 7, count 0 2006.245.07:50:15.58#ibcon#wrote, iclass 7, count 0 2006.245.07:50:15.58#ibcon#about to read 3, iclass 7, count 0 2006.245.07:50:15.62#ibcon#read 3, iclass 7, count 0 2006.245.07:50:15.62#ibcon#about to read 4, iclass 7, count 0 2006.245.07:50:15.62#ibcon#read 4, iclass 7, count 0 2006.245.07:50:15.62#ibcon#about to read 5, iclass 7, count 0 2006.245.07:50:15.62#ibcon#read 5, iclass 7, count 0 2006.245.07:50:15.62#ibcon#about to read 6, iclass 7, count 0 2006.245.07:50:15.62#ibcon#read 6, iclass 7, count 0 2006.245.07:50:15.62#ibcon#end of sib2, iclass 7, count 0 2006.245.07:50:15.62#ibcon#*after write, iclass 7, count 0 2006.245.07:50:15.62#ibcon#*before return 0, iclass 7, count 0 2006.245.07:50:15.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:15.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:15.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:50:15.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:50:15.62$vc4f8/va=5,7 2006.245.07:50:15.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.07:50:15.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.07:50:15.62#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:15.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:15.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:15.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:15.68#ibcon#enter wrdev, iclass 11, count 2 2006.245.07:50:15.68#ibcon#first serial, iclass 11, count 2 2006.245.07:50:15.68#ibcon#enter sib2, iclass 11, count 2 2006.245.07:50:15.68#ibcon#flushed, iclass 11, count 2 2006.245.07:50:15.68#ibcon#about to write, iclass 11, count 2 2006.245.07:50:15.68#ibcon#wrote, iclass 11, count 2 2006.245.07:50:15.68#ibcon#about to read 3, iclass 11, count 2 2006.245.07:50:15.70#ibcon#read 3, iclass 11, count 2 2006.245.07:50:15.70#ibcon#about to read 4, iclass 11, count 2 2006.245.07:50:15.70#ibcon#read 4, iclass 11, count 2 2006.245.07:50:15.70#ibcon#about to read 5, iclass 11, count 2 2006.245.07:50:15.70#ibcon#read 5, iclass 11, count 2 2006.245.07:50:15.70#ibcon#about to read 6, iclass 11, count 2 2006.245.07:50:15.70#ibcon#read 6, iclass 11, count 2 2006.245.07:50:15.70#ibcon#end of sib2, iclass 11, count 2 2006.245.07:50:15.70#ibcon#*mode == 0, iclass 11, count 2 2006.245.07:50:15.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.07:50:15.70#ibcon#[25=AT05-07\r\n] 2006.245.07:50:15.70#ibcon#*before write, iclass 11, count 2 2006.245.07:50:15.70#ibcon#enter sib2, iclass 11, count 2 2006.245.07:50:15.70#ibcon#flushed, iclass 11, count 2 2006.245.07:50:15.70#ibcon#about to write, iclass 11, count 2 2006.245.07:50:15.70#ibcon#wrote, iclass 11, count 2 2006.245.07:50:15.70#ibcon#about to read 3, iclass 11, count 2 2006.245.07:50:15.72#abcon#<5=/05 3.0 4.7 27.36 671004.5\r\n> 2006.245.07:50:15.73#ibcon#read 3, iclass 11, count 2 2006.245.07:50:15.73#ibcon#about to read 4, iclass 11, count 2 2006.245.07:50:15.73#ibcon#read 4, iclass 11, count 2 2006.245.07:50:15.73#ibcon#about to read 5, iclass 11, count 2 2006.245.07:50:15.73#ibcon#read 5, iclass 11, count 2 2006.245.07:50:15.73#ibcon#about to read 6, iclass 11, count 2 2006.245.07:50:15.73#ibcon#read 6, iclass 11, count 2 2006.245.07:50:15.73#ibcon#end of sib2, iclass 11, count 2 2006.245.07:50:15.73#ibcon#*after write, iclass 11, count 2 2006.245.07:50:15.73#ibcon#*before return 0, iclass 11, count 2 2006.245.07:50:15.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:15.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:15.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.07:50:15.73#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:15.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:15.74#abcon#{5=INTERFACE CLEAR} 2006.245.07:50:15.80#abcon#[5=S1D000X0/0*\r\n] 2006.245.07:50:15.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:15.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:15.85#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:50:15.85#ibcon#first serial, iclass 11, count 0 2006.245.07:50:15.85#ibcon#enter sib2, iclass 11, count 0 2006.245.07:50:15.85#ibcon#flushed, iclass 11, count 0 2006.245.07:50:15.85#ibcon#about to write, iclass 11, count 0 2006.245.07:50:15.85#ibcon#wrote, iclass 11, count 0 2006.245.07:50:15.85#ibcon#about to read 3, iclass 11, count 0 2006.245.07:50:15.87#ibcon#read 3, iclass 11, count 0 2006.245.07:50:15.87#ibcon#about to read 4, iclass 11, count 0 2006.245.07:50:15.87#ibcon#read 4, iclass 11, count 0 2006.245.07:50:15.87#ibcon#about to read 5, iclass 11, count 0 2006.245.07:50:15.87#ibcon#read 5, iclass 11, count 0 2006.245.07:50:15.87#ibcon#about to read 6, iclass 11, count 0 2006.245.07:50:15.87#ibcon#read 6, iclass 11, count 0 2006.245.07:50:15.87#ibcon#end of sib2, iclass 11, count 0 2006.245.07:50:15.87#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:50:15.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:50:15.87#ibcon#[25=USB\r\n] 2006.245.07:50:15.87#ibcon#*before write, iclass 11, count 0 2006.245.07:50:15.87#ibcon#enter sib2, iclass 11, count 0 2006.245.07:50:15.87#ibcon#flushed, iclass 11, count 0 2006.245.07:50:15.87#ibcon#about to write, iclass 11, count 0 2006.245.07:50:15.87#ibcon#wrote, iclass 11, count 0 2006.245.07:50:15.87#ibcon#about to read 3, iclass 11, count 0 2006.245.07:50:15.90#ibcon#read 3, iclass 11, count 0 2006.245.07:50:15.90#ibcon#about to read 4, iclass 11, count 0 2006.245.07:50:15.90#ibcon#read 4, iclass 11, count 0 2006.245.07:50:15.90#ibcon#about to read 5, iclass 11, count 0 2006.245.07:50:15.90#ibcon#read 5, iclass 11, count 0 2006.245.07:50:15.90#ibcon#about to read 6, iclass 11, count 0 2006.245.07:50:15.90#ibcon#read 6, iclass 11, count 0 2006.245.07:50:15.90#ibcon#end of sib2, iclass 11, count 0 2006.245.07:50:15.90#ibcon#*after write, iclass 11, count 0 2006.245.07:50:15.90#ibcon#*before return 0, iclass 11, count 0 2006.245.07:50:15.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:15.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:15.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:50:15.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:50:15.90$vc4f8/valo=6,772.99 2006.245.07:50:15.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.07:50:15.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.07:50:15.90#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:15.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:15.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:15.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:15.90#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:50:15.90#ibcon#first serial, iclass 17, count 0 2006.245.07:50:15.90#ibcon#enter sib2, iclass 17, count 0 2006.245.07:50:15.90#ibcon#flushed, iclass 17, count 0 2006.245.07:50:15.90#ibcon#about to write, iclass 17, count 0 2006.245.07:50:15.90#ibcon#wrote, iclass 17, count 0 2006.245.07:50:15.90#ibcon#about to read 3, iclass 17, count 0 2006.245.07:50:15.92#ibcon#read 3, iclass 17, count 0 2006.245.07:50:15.92#ibcon#about to read 4, iclass 17, count 0 2006.245.07:50:15.92#ibcon#read 4, iclass 17, count 0 2006.245.07:50:15.92#ibcon#about to read 5, iclass 17, count 0 2006.245.07:50:15.92#ibcon#read 5, iclass 17, count 0 2006.245.07:50:15.92#ibcon#about to read 6, iclass 17, count 0 2006.245.07:50:15.92#ibcon#read 6, iclass 17, count 0 2006.245.07:50:15.92#ibcon#end of sib2, iclass 17, count 0 2006.245.07:50:15.92#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:50:15.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:50:15.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:50:15.92#ibcon#*before write, iclass 17, count 0 2006.245.07:50:15.92#ibcon#enter sib2, iclass 17, count 0 2006.245.07:50:15.92#ibcon#flushed, iclass 17, count 0 2006.245.07:50:15.92#ibcon#about to write, iclass 17, count 0 2006.245.07:50:15.92#ibcon#wrote, iclass 17, count 0 2006.245.07:50:15.92#ibcon#about to read 3, iclass 17, count 0 2006.245.07:50:15.96#ibcon#read 3, iclass 17, count 0 2006.245.07:50:15.96#ibcon#about to read 4, iclass 17, count 0 2006.245.07:50:15.96#ibcon#read 4, iclass 17, count 0 2006.245.07:50:15.96#ibcon#about to read 5, iclass 17, count 0 2006.245.07:50:15.96#ibcon#read 5, iclass 17, count 0 2006.245.07:50:15.96#ibcon#about to read 6, iclass 17, count 0 2006.245.07:50:15.96#ibcon#read 6, iclass 17, count 0 2006.245.07:50:15.96#ibcon#end of sib2, iclass 17, count 0 2006.245.07:50:15.96#ibcon#*after write, iclass 17, count 0 2006.245.07:50:15.96#ibcon#*before return 0, iclass 17, count 0 2006.245.07:50:15.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:15.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:15.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:50:15.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:50:15.96$vc4f8/va=6,7 2006.245.07:50:15.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.07:50:15.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.07:50:15.96#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:15.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:50:16.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:50:16.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:50:16.02#ibcon#enter wrdev, iclass 19, count 2 2006.245.07:50:16.02#ibcon#first serial, iclass 19, count 2 2006.245.07:50:16.02#ibcon#enter sib2, iclass 19, count 2 2006.245.07:50:16.02#ibcon#flushed, iclass 19, count 2 2006.245.07:50:16.02#ibcon#about to write, iclass 19, count 2 2006.245.07:50:16.02#ibcon#wrote, iclass 19, count 2 2006.245.07:50:16.02#ibcon#about to read 3, iclass 19, count 2 2006.245.07:50:16.04#ibcon#read 3, iclass 19, count 2 2006.245.07:50:16.04#ibcon#about to read 4, iclass 19, count 2 2006.245.07:50:16.04#ibcon#read 4, iclass 19, count 2 2006.245.07:50:16.04#ibcon#about to read 5, iclass 19, count 2 2006.245.07:50:16.04#ibcon#read 5, iclass 19, count 2 2006.245.07:50:16.04#ibcon#about to read 6, iclass 19, count 2 2006.245.07:50:16.04#ibcon#read 6, iclass 19, count 2 2006.245.07:50:16.04#ibcon#end of sib2, iclass 19, count 2 2006.245.07:50:16.04#ibcon#*mode == 0, iclass 19, count 2 2006.245.07:50:16.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.07:50:16.04#ibcon#[25=AT06-07\r\n] 2006.245.07:50:16.04#ibcon#*before write, iclass 19, count 2 2006.245.07:50:16.04#ibcon#enter sib2, iclass 19, count 2 2006.245.07:50:16.04#ibcon#flushed, iclass 19, count 2 2006.245.07:50:16.04#ibcon#about to write, iclass 19, count 2 2006.245.07:50:16.04#ibcon#wrote, iclass 19, count 2 2006.245.07:50:16.04#ibcon#about to read 3, iclass 19, count 2 2006.245.07:50:16.07#ibcon#read 3, iclass 19, count 2 2006.245.07:50:16.07#ibcon#about to read 4, iclass 19, count 2 2006.245.07:50:16.07#ibcon#read 4, iclass 19, count 2 2006.245.07:50:16.07#ibcon#about to read 5, iclass 19, count 2 2006.245.07:50:16.07#ibcon#read 5, iclass 19, count 2 2006.245.07:50:16.07#ibcon#about to read 6, iclass 19, count 2 2006.245.07:50:16.07#ibcon#read 6, iclass 19, count 2 2006.245.07:50:16.07#ibcon#end of sib2, iclass 19, count 2 2006.245.07:50:16.07#ibcon#*after write, iclass 19, count 2 2006.245.07:50:16.07#ibcon#*before return 0, iclass 19, count 2 2006.245.07:50:16.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:50:16.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.07:50:16.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.07:50:16.07#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:16.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:50:16.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:50:16.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:50:16.19#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:50:16.19#ibcon#first serial, iclass 19, count 0 2006.245.07:50:16.19#ibcon#enter sib2, iclass 19, count 0 2006.245.07:50:16.19#ibcon#flushed, iclass 19, count 0 2006.245.07:50:16.19#ibcon#about to write, iclass 19, count 0 2006.245.07:50:16.19#ibcon#wrote, iclass 19, count 0 2006.245.07:50:16.19#ibcon#about to read 3, iclass 19, count 0 2006.245.07:50:16.21#ibcon#read 3, iclass 19, count 0 2006.245.07:50:16.21#ibcon#about to read 4, iclass 19, count 0 2006.245.07:50:16.21#ibcon#read 4, iclass 19, count 0 2006.245.07:50:16.21#ibcon#about to read 5, iclass 19, count 0 2006.245.07:50:16.21#ibcon#read 5, iclass 19, count 0 2006.245.07:50:16.21#ibcon#about to read 6, iclass 19, count 0 2006.245.07:50:16.21#ibcon#read 6, iclass 19, count 0 2006.245.07:50:16.21#ibcon#end of sib2, iclass 19, count 0 2006.245.07:50:16.21#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:50:16.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:50:16.21#ibcon#[25=USB\r\n] 2006.245.07:50:16.21#ibcon#*before write, iclass 19, count 0 2006.245.07:50:16.21#ibcon#enter sib2, iclass 19, count 0 2006.245.07:50:16.21#ibcon#flushed, iclass 19, count 0 2006.245.07:50:16.21#ibcon#about to write, iclass 19, count 0 2006.245.07:50:16.21#ibcon#wrote, iclass 19, count 0 2006.245.07:50:16.21#ibcon#about to read 3, iclass 19, count 0 2006.245.07:50:16.24#ibcon#read 3, iclass 19, count 0 2006.245.07:50:16.24#ibcon#about to read 4, iclass 19, count 0 2006.245.07:50:16.24#ibcon#read 4, iclass 19, count 0 2006.245.07:50:16.24#ibcon#about to read 5, iclass 19, count 0 2006.245.07:50:16.24#ibcon#read 5, iclass 19, count 0 2006.245.07:50:16.24#ibcon#about to read 6, iclass 19, count 0 2006.245.07:50:16.24#ibcon#read 6, iclass 19, count 0 2006.245.07:50:16.24#ibcon#end of sib2, iclass 19, count 0 2006.245.07:50:16.24#ibcon#*after write, iclass 19, count 0 2006.245.07:50:16.24#ibcon#*before return 0, iclass 19, count 0 2006.245.07:50:16.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:50:16.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.07:50:16.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:50:16.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:50:16.24$vc4f8/valo=7,832.99 2006.245.07:50:16.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.07:50:16.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.07:50:16.24#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:16.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:50:16.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:50:16.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:50:16.24#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:50:16.24#ibcon#first serial, iclass 21, count 0 2006.245.07:50:16.24#ibcon#enter sib2, iclass 21, count 0 2006.245.07:50:16.24#ibcon#flushed, iclass 21, count 0 2006.245.07:50:16.24#ibcon#about to write, iclass 21, count 0 2006.245.07:50:16.24#ibcon#wrote, iclass 21, count 0 2006.245.07:50:16.24#ibcon#about to read 3, iclass 21, count 0 2006.245.07:50:16.26#ibcon#read 3, iclass 21, count 0 2006.245.07:50:16.26#ibcon#about to read 4, iclass 21, count 0 2006.245.07:50:16.26#ibcon#read 4, iclass 21, count 0 2006.245.07:50:16.26#ibcon#about to read 5, iclass 21, count 0 2006.245.07:50:16.26#ibcon#read 5, iclass 21, count 0 2006.245.07:50:16.26#ibcon#about to read 6, iclass 21, count 0 2006.245.07:50:16.26#ibcon#read 6, iclass 21, count 0 2006.245.07:50:16.26#ibcon#end of sib2, iclass 21, count 0 2006.245.07:50:16.26#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:50:16.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:50:16.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:50:16.26#ibcon#*before write, iclass 21, count 0 2006.245.07:50:16.26#ibcon#enter sib2, iclass 21, count 0 2006.245.07:50:16.26#ibcon#flushed, iclass 21, count 0 2006.245.07:50:16.26#ibcon#about to write, iclass 21, count 0 2006.245.07:50:16.26#ibcon#wrote, iclass 21, count 0 2006.245.07:50:16.26#ibcon#about to read 3, iclass 21, count 0 2006.245.07:50:16.30#ibcon#read 3, iclass 21, count 0 2006.245.07:50:16.30#ibcon#about to read 4, iclass 21, count 0 2006.245.07:50:16.30#ibcon#read 4, iclass 21, count 0 2006.245.07:50:16.30#ibcon#about to read 5, iclass 21, count 0 2006.245.07:50:16.30#ibcon#read 5, iclass 21, count 0 2006.245.07:50:16.30#ibcon#about to read 6, iclass 21, count 0 2006.245.07:50:16.30#ibcon#read 6, iclass 21, count 0 2006.245.07:50:16.30#ibcon#end of sib2, iclass 21, count 0 2006.245.07:50:16.30#ibcon#*after write, iclass 21, count 0 2006.245.07:50:16.30#ibcon#*before return 0, iclass 21, count 0 2006.245.07:50:16.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:50:16.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.07:50:16.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:50:16.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:50:16.30$vc4f8/va=7,7 2006.245.07:50:16.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.07:50:16.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.07:50:16.30#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:16.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:50:16.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:50:16.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:50:16.36#ibcon#enter wrdev, iclass 23, count 2 2006.245.07:50:16.36#ibcon#first serial, iclass 23, count 2 2006.245.07:50:16.36#ibcon#enter sib2, iclass 23, count 2 2006.245.07:50:16.36#ibcon#flushed, iclass 23, count 2 2006.245.07:50:16.36#ibcon#about to write, iclass 23, count 2 2006.245.07:50:16.36#ibcon#wrote, iclass 23, count 2 2006.245.07:50:16.36#ibcon#about to read 3, iclass 23, count 2 2006.245.07:50:16.38#ibcon#read 3, iclass 23, count 2 2006.245.07:50:16.38#ibcon#about to read 4, iclass 23, count 2 2006.245.07:50:16.38#ibcon#read 4, iclass 23, count 2 2006.245.07:50:16.38#ibcon#about to read 5, iclass 23, count 2 2006.245.07:50:16.38#ibcon#read 5, iclass 23, count 2 2006.245.07:50:16.38#ibcon#about to read 6, iclass 23, count 2 2006.245.07:50:16.38#ibcon#read 6, iclass 23, count 2 2006.245.07:50:16.38#ibcon#end of sib2, iclass 23, count 2 2006.245.07:50:16.38#ibcon#*mode == 0, iclass 23, count 2 2006.245.07:50:16.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.07:50:16.38#ibcon#[25=AT07-07\r\n] 2006.245.07:50:16.38#ibcon#*before write, iclass 23, count 2 2006.245.07:50:16.38#ibcon#enter sib2, iclass 23, count 2 2006.245.07:50:16.38#ibcon#flushed, iclass 23, count 2 2006.245.07:50:16.38#ibcon#about to write, iclass 23, count 2 2006.245.07:50:16.38#ibcon#wrote, iclass 23, count 2 2006.245.07:50:16.38#ibcon#about to read 3, iclass 23, count 2 2006.245.07:50:16.41#ibcon#read 3, iclass 23, count 2 2006.245.07:50:16.41#ibcon#about to read 4, iclass 23, count 2 2006.245.07:50:16.41#ibcon#read 4, iclass 23, count 2 2006.245.07:50:16.41#ibcon#about to read 5, iclass 23, count 2 2006.245.07:50:16.41#ibcon#read 5, iclass 23, count 2 2006.245.07:50:16.41#ibcon#about to read 6, iclass 23, count 2 2006.245.07:50:16.41#ibcon#read 6, iclass 23, count 2 2006.245.07:50:16.41#ibcon#end of sib2, iclass 23, count 2 2006.245.07:50:16.41#ibcon#*after write, iclass 23, count 2 2006.245.07:50:16.41#ibcon#*before return 0, iclass 23, count 2 2006.245.07:50:16.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:50:16.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.07:50:16.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.07:50:16.41#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:16.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:50:16.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:50:16.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:50:16.53#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:50:16.53#ibcon#first serial, iclass 23, count 0 2006.245.07:50:16.53#ibcon#enter sib2, iclass 23, count 0 2006.245.07:50:16.53#ibcon#flushed, iclass 23, count 0 2006.245.07:50:16.53#ibcon#about to write, iclass 23, count 0 2006.245.07:50:16.53#ibcon#wrote, iclass 23, count 0 2006.245.07:50:16.53#ibcon#about to read 3, iclass 23, count 0 2006.245.07:50:16.55#ibcon#read 3, iclass 23, count 0 2006.245.07:50:16.55#ibcon#about to read 4, iclass 23, count 0 2006.245.07:50:16.55#ibcon#read 4, iclass 23, count 0 2006.245.07:50:16.55#ibcon#about to read 5, iclass 23, count 0 2006.245.07:50:16.55#ibcon#read 5, iclass 23, count 0 2006.245.07:50:16.55#ibcon#about to read 6, iclass 23, count 0 2006.245.07:50:16.55#ibcon#read 6, iclass 23, count 0 2006.245.07:50:16.55#ibcon#end of sib2, iclass 23, count 0 2006.245.07:50:16.55#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:50:16.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:50:16.55#ibcon#[25=USB\r\n] 2006.245.07:50:16.55#ibcon#*before write, iclass 23, count 0 2006.245.07:50:16.55#ibcon#enter sib2, iclass 23, count 0 2006.245.07:50:16.55#ibcon#flushed, iclass 23, count 0 2006.245.07:50:16.55#ibcon#about to write, iclass 23, count 0 2006.245.07:50:16.55#ibcon#wrote, iclass 23, count 0 2006.245.07:50:16.55#ibcon#about to read 3, iclass 23, count 0 2006.245.07:50:16.58#ibcon#read 3, iclass 23, count 0 2006.245.07:50:16.58#ibcon#about to read 4, iclass 23, count 0 2006.245.07:50:16.58#ibcon#read 4, iclass 23, count 0 2006.245.07:50:16.58#ibcon#about to read 5, iclass 23, count 0 2006.245.07:50:16.58#ibcon#read 5, iclass 23, count 0 2006.245.07:50:16.58#ibcon#about to read 6, iclass 23, count 0 2006.245.07:50:16.58#ibcon#read 6, iclass 23, count 0 2006.245.07:50:16.58#ibcon#end of sib2, iclass 23, count 0 2006.245.07:50:16.58#ibcon#*after write, iclass 23, count 0 2006.245.07:50:16.58#ibcon#*before return 0, iclass 23, count 0 2006.245.07:50:16.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:50:16.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.07:50:16.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:50:16.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:50:16.58$vc4f8/valo=8,852.99 2006.245.07:50:16.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.07:50:16.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.07:50:16.58#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:16.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:50:16.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:50:16.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:50:16.58#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:50:16.58#ibcon#first serial, iclass 25, count 0 2006.245.07:50:16.58#ibcon#enter sib2, iclass 25, count 0 2006.245.07:50:16.58#ibcon#flushed, iclass 25, count 0 2006.245.07:50:16.58#ibcon#about to write, iclass 25, count 0 2006.245.07:50:16.58#ibcon#wrote, iclass 25, count 0 2006.245.07:50:16.58#ibcon#about to read 3, iclass 25, count 0 2006.245.07:50:16.60#ibcon#read 3, iclass 25, count 0 2006.245.07:50:16.60#ibcon#about to read 4, iclass 25, count 0 2006.245.07:50:16.60#ibcon#read 4, iclass 25, count 0 2006.245.07:50:16.60#ibcon#about to read 5, iclass 25, count 0 2006.245.07:50:16.60#ibcon#read 5, iclass 25, count 0 2006.245.07:50:16.60#ibcon#about to read 6, iclass 25, count 0 2006.245.07:50:16.60#ibcon#read 6, iclass 25, count 0 2006.245.07:50:16.60#ibcon#end of sib2, iclass 25, count 0 2006.245.07:50:16.60#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:50:16.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:50:16.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:50:16.60#ibcon#*before write, iclass 25, count 0 2006.245.07:50:16.60#ibcon#enter sib2, iclass 25, count 0 2006.245.07:50:16.60#ibcon#flushed, iclass 25, count 0 2006.245.07:50:16.60#ibcon#about to write, iclass 25, count 0 2006.245.07:50:16.60#ibcon#wrote, iclass 25, count 0 2006.245.07:50:16.60#ibcon#about to read 3, iclass 25, count 0 2006.245.07:50:16.64#ibcon#read 3, iclass 25, count 0 2006.245.07:50:16.64#ibcon#about to read 4, iclass 25, count 0 2006.245.07:50:16.64#ibcon#read 4, iclass 25, count 0 2006.245.07:50:16.64#ibcon#about to read 5, iclass 25, count 0 2006.245.07:50:16.64#ibcon#read 5, iclass 25, count 0 2006.245.07:50:16.64#ibcon#about to read 6, iclass 25, count 0 2006.245.07:50:16.64#ibcon#read 6, iclass 25, count 0 2006.245.07:50:16.64#ibcon#end of sib2, iclass 25, count 0 2006.245.07:50:16.64#ibcon#*after write, iclass 25, count 0 2006.245.07:50:16.64#ibcon#*before return 0, iclass 25, count 0 2006.245.07:50:16.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:50:16.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.07:50:16.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:50:16.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:50:16.64$vc4f8/va=8,8 2006.245.07:50:16.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.07:50:16.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.07:50:16.64#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:16.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:50:16.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:50:16.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:50:16.70#ibcon#enter wrdev, iclass 27, count 2 2006.245.07:50:16.70#ibcon#first serial, iclass 27, count 2 2006.245.07:50:16.70#ibcon#enter sib2, iclass 27, count 2 2006.245.07:50:16.70#ibcon#flushed, iclass 27, count 2 2006.245.07:50:16.70#ibcon#about to write, iclass 27, count 2 2006.245.07:50:16.70#ibcon#wrote, iclass 27, count 2 2006.245.07:50:16.70#ibcon#about to read 3, iclass 27, count 2 2006.245.07:50:16.72#ibcon#read 3, iclass 27, count 2 2006.245.07:50:16.72#ibcon#about to read 4, iclass 27, count 2 2006.245.07:50:16.72#ibcon#read 4, iclass 27, count 2 2006.245.07:50:16.72#ibcon#about to read 5, iclass 27, count 2 2006.245.07:50:16.72#ibcon#read 5, iclass 27, count 2 2006.245.07:50:16.72#ibcon#about to read 6, iclass 27, count 2 2006.245.07:50:16.72#ibcon#read 6, iclass 27, count 2 2006.245.07:50:16.72#ibcon#end of sib2, iclass 27, count 2 2006.245.07:50:16.72#ibcon#*mode == 0, iclass 27, count 2 2006.245.07:50:16.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.07:50:16.72#ibcon#[25=AT08-08\r\n] 2006.245.07:50:16.72#ibcon#*before write, iclass 27, count 2 2006.245.07:50:16.72#ibcon#enter sib2, iclass 27, count 2 2006.245.07:50:16.72#ibcon#flushed, iclass 27, count 2 2006.245.07:50:16.72#ibcon#about to write, iclass 27, count 2 2006.245.07:50:16.72#ibcon#wrote, iclass 27, count 2 2006.245.07:50:16.72#ibcon#about to read 3, iclass 27, count 2 2006.245.07:50:16.75#ibcon#read 3, iclass 27, count 2 2006.245.07:50:16.75#ibcon#about to read 4, iclass 27, count 2 2006.245.07:50:16.75#ibcon#read 4, iclass 27, count 2 2006.245.07:50:16.75#ibcon#about to read 5, iclass 27, count 2 2006.245.07:50:16.75#ibcon#read 5, iclass 27, count 2 2006.245.07:50:16.75#ibcon#about to read 6, iclass 27, count 2 2006.245.07:50:16.75#ibcon#read 6, iclass 27, count 2 2006.245.07:50:16.75#ibcon#end of sib2, iclass 27, count 2 2006.245.07:50:16.75#ibcon#*after write, iclass 27, count 2 2006.245.07:50:16.75#ibcon#*before return 0, iclass 27, count 2 2006.245.07:50:16.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:50:16.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.07:50:16.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.07:50:16.75#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:16.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:50:16.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:50:16.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:50:16.87#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:50:16.87#ibcon#first serial, iclass 27, count 0 2006.245.07:50:16.87#ibcon#enter sib2, iclass 27, count 0 2006.245.07:50:16.87#ibcon#flushed, iclass 27, count 0 2006.245.07:50:16.87#ibcon#about to write, iclass 27, count 0 2006.245.07:50:16.87#ibcon#wrote, iclass 27, count 0 2006.245.07:50:16.87#ibcon#about to read 3, iclass 27, count 0 2006.245.07:50:16.89#ibcon#read 3, iclass 27, count 0 2006.245.07:50:16.89#ibcon#about to read 4, iclass 27, count 0 2006.245.07:50:16.89#ibcon#read 4, iclass 27, count 0 2006.245.07:50:16.89#ibcon#about to read 5, iclass 27, count 0 2006.245.07:50:16.89#ibcon#read 5, iclass 27, count 0 2006.245.07:50:16.89#ibcon#about to read 6, iclass 27, count 0 2006.245.07:50:16.89#ibcon#read 6, iclass 27, count 0 2006.245.07:50:16.89#ibcon#end of sib2, iclass 27, count 0 2006.245.07:50:16.89#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:50:16.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:50:16.89#ibcon#[25=USB\r\n] 2006.245.07:50:16.89#ibcon#*before write, iclass 27, count 0 2006.245.07:50:16.89#ibcon#enter sib2, iclass 27, count 0 2006.245.07:50:16.89#ibcon#flushed, iclass 27, count 0 2006.245.07:50:16.89#ibcon#about to write, iclass 27, count 0 2006.245.07:50:16.89#ibcon#wrote, iclass 27, count 0 2006.245.07:50:16.89#ibcon#about to read 3, iclass 27, count 0 2006.245.07:50:16.92#ibcon#read 3, iclass 27, count 0 2006.245.07:50:16.92#ibcon#about to read 4, iclass 27, count 0 2006.245.07:50:16.92#ibcon#read 4, iclass 27, count 0 2006.245.07:50:16.92#ibcon#about to read 5, iclass 27, count 0 2006.245.07:50:16.92#ibcon#read 5, iclass 27, count 0 2006.245.07:50:16.92#ibcon#about to read 6, iclass 27, count 0 2006.245.07:50:16.92#ibcon#read 6, iclass 27, count 0 2006.245.07:50:16.92#ibcon#end of sib2, iclass 27, count 0 2006.245.07:50:16.92#ibcon#*after write, iclass 27, count 0 2006.245.07:50:16.92#ibcon#*before return 0, iclass 27, count 0 2006.245.07:50:16.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:50:16.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.07:50:16.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:50:16.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:50:16.92$vc4f8/vblo=1,632.99 2006.245.07:50:16.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.07:50:16.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.07:50:16.92#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:16.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:16.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:16.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:16.92#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:50:16.92#ibcon#first serial, iclass 29, count 0 2006.245.07:50:16.92#ibcon#enter sib2, iclass 29, count 0 2006.245.07:50:16.92#ibcon#flushed, iclass 29, count 0 2006.245.07:50:16.92#ibcon#about to write, iclass 29, count 0 2006.245.07:50:16.92#ibcon#wrote, iclass 29, count 0 2006.245.07:50:16.92#ibcon#about to read 3, iclass 29, count 0 2006.245.07:50:16.94#ibcon#read 3, iclass 29, count 0 2006.245.07:50:16.94#ibcon#about to read 4, iclass 29, count 0 2006.245.07:50:16.94#ibcon#read 4, iclass 29, count 0 2006.245.07:50:16.94#ibcon#about to read 5, iclass 29, count 0 2006.245.07:50:16.94#ibcon#read 5, iclass 29, count 0 2006.245.07:50:16.94#ibcon#about to read 6, iclass 29, count 0 2006.245.07:50:16.94#ibcon#read 6, iclass 29, count 0 2006.245.07:50:16.94#ibcon#end of sib2, iclass 29, count 0 2006.245.07:50:16.94#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:50:16.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:50:16.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:50:16.94#ibcon#*before write, iclass 29, count 0 2006.245.07:50:16.94#ibcon#enter sib2, iclass 29, count 0 2006.245.07:50:16.94#ibcon#flushed, iclass 29, count 0 2006.245.07:50:16.94#ibcon#about to write, iclass 29, count 0 2006.245.07:50:16.94#ibcon#wrote, iclass 29, count 0 2006.245.07:50:16.94#ibcon#about to read 3, iclass 29, count 0 2006.245.07:50:16.98#ibcon#read 3, iclass 29, count 0 2006.245.07:50:16.98#ibcon#about to read 4, iclass 29, count 0 2006.245.07:50:16.98#ibcon#read 4, iclass 29, count 0 2006.245.07:50:16.98#ibcon#about to read 5, iclass 29, count 0 2006.245.07:50:16.98#ibcon#read 5, iclass 29, count 0 2006.245.07:50:16.98#ibcon#about to read 6, iclass 29, count 0 2006.245.07:50:16.98#ibcon#read 6, iclass 29, count 0 2006.245.07:50:16.98#ibcon#end of sib2, iclass 29, count 0 2006.245.07:50:16.98#ibcon#*after write, iclass 29, count 0 2006.245.07:50:16.98#ibcon#*before return 0, iclass 29, count 0 2006.245.07:50:16.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:16.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.07:50:16.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:50:16.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:50:16.98$vc4f8/vb=1,4 2006.245.07:50:16.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.07:50:16.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.07:50:16.98#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:16.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:16.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:16.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:16.98#ibcon#enter wrdev, iclass 31, count 2 2006.245.07:50:16.98#ibcon#first serial, iclass 31, count 2 2006.245.07:50:16.98#ibcon#enter sib2, iclass 31, count 2 2006.245.07:50:16.98#ibcon#flushed, iclass 31, count 2 2006.245.07:50:16.98#ibcon#about to write, iclass 31, count 2 2006.245.07:50:16.98#ibcon#wrote, iclass 31, count 2 2006.245.07:50:16.98#ibcon#about to read 3, iclass 31, count 2 2006.245.07:50:17.00#ibcon#read 3, iclass 31, count 2 2006.245.07:50:17.00#ibcon#about to read 4, iclass 31, count 2 2006.245.07:50:17.00#ibcon#read 4, iclass 31, count 2 2006.245.07:50:17.00#ibcon#about to read 5, iclass 31, count 2 2006.245.07:50:17.00#ibcon#read 5, iclass 31, count 2 2006.245.07:50:17.00#ibcon#about to read 6, iclass 31, count 2 2006.245.07:50:17.00#ibcon#read 6, iclass 31, count 2 2006.245.07:50:17.00#ibcon#end of sib2, iclass 31, count 2 2006.245.07:50:17.00#ibcon#*mode == 0, iclass 31, count 2 2006.245.07:50:17.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.07:50:17.00#ibcon#[27=AT01-04\r\n] 2006.245.07:50:17.00#ibcon#*before write, iclass 31, count 2 2006.245.07:50:17.00#ibcon#enter sib2, iclass 31, count 2 2006.245.07:50:17.00#ibcon#flushed, iclass 31, count 2 2006.245.07:50:17.00#ibcon#about to write, iclass 31, count 2 2006.245.07:50:17.00#ibcon#wrote, iclass 31, count 2 2006.245.07:50:17.00#ibcon#about to read 3, iclass 31, count 2 2006.245.07:50:17.03#ibcon#read 3, iclass 31, count 2 2006.245.07:50:17.03#ibcon#about to read 4, iclass 31, count 2 2006.245.07:50:17.03#ibcon#read 4, iclass 31, count 2 2006.245.07:50:17.03#ibcon#about to read 5, iclass 31, count 2 2006.245.07:50:17.03#ibcon#read 5, iclass 31, count 2 2006.245.07:50:17.03#ibcon#about to read 6, iclass 31, count 2 2006.245.07:50:17.03#ibcon#read 6, iclass 31, count 2 2006.245.07:50:17.03#ibcon#end of sib2, iclass 31, count 2 2006.245.07:50:17.03#ibcon#*after write, iclass 31, count 2 2006.245.07:50:17.03#ibcon#*before return 0, iclass 31, count 2 2006.245.07:50:17.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:17.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:50:17.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.07:50:17.03#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:17.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:17.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:17.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:17.15#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:50:17.15#ibcon#first serial, iclass 31, count 0 2006.245.07:50:17.15#ibcon#enter sib2, iclass 31, count 0 2006.245.07:50:17.15#ibcon#flushed, iclass 31, count 0 2006.245.07:50:17.15#ibcon#about to write, iclass 31, count 0 2006.245.07:50:17.15#ibcon#wrote, iclass 31, count 0 2006.245.07:50:17.15#ibcon#about to read 3, iclass 31, count 0 2006.245.07:50:17.17#ibcon#read 3, iclass 31, count 0 2006.245.07:50:17.17#ibcon#about to read 4, iclass 31, count 0 2006.245.07:50:17.17#ibcon#read 4, iclass 31, count 0 2006.245.07:50:17.17#ibcon#about to read 5, iclass 31, count 0 2006.245.07:50:17.17#ibcon#read 5, iclass 31, count 0 2006.245.07:50:17.17#ibcon#about to read 6, iclass 31, count 0 2006.245.07:50:17.17#ibcon#read 6, iclass 31, count 0 2006.245.07:50:17.17#ibcon#end of sib2, iclass 31, count 0 2006.245.07:50:17.17#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:50:17.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:50:17.17#ibcon#[27=USB\r\n] 2006.245.07:50:17.17#ibcon#*before write, iclass 31, count 0 2006.245.07:50:17.17#ibcon#enter sib2, iclass 31, count 0 2006.245.07:50:17.17#ibcon#flushed, iclass 31, count 0 2006.245.07:50:17.17#ibcon#about to write, iclass 31, count 0 2006.245.07:50:17.17#ibcon#wrote, iclass 31, count 0 2006.245.07:50:17.17#ibcon#about to read 3, iclass 31, count 0 2006.245.07:50:17.20#ibcon#read 3, iclass 31, count 0 2006.245.07:50:17.20#ibcon#about to read 4, iclass 31, count 0 2006.245.07:50:17.20#ibcon#read 4, iclass 31, count 0 2006.245.07:50:17.20#ibcon#about to read 5, iclass 31, count 0 2006.245.07:50:17.20#ibcon#read 5, iclass 31, count 0 2006.245.07:50:17.20#ibcon#about to read 6, iclass 31, count 0 2006.245.07:50:17.20#ibcon#read 6, iclass 31, count 0 2006.245.07:50:17.20#ibcon#end of sib2, iclass 31, count 0 2006.245.07:50:17.20#ibcon#*after write, iclass 31, count 0 2006.245.07:50:17.20#ibcon#*before return 0, iclass 31, count 0 2006.245.07:50:17.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:17.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:50:17.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:50:17.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:50:17.20$vc4f8/vblo=2,640.99 2006.245.07:50:17.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.07:50:17.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.07:50:17.20#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:17.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:17.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:17.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:17.20#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:50:17.20#ibcon#first serial, iclass 33, count 0 2006.245.07:50:17.20#ibcon#enter sib2, iclass 33, count 0 2006.245.07:50:17.20#ibcon#flushed, iclass 33, count 0 2006.245.07:50:17.20#ibcon#about to write, iclass 33, count 0 2006.245.07:50:17.20#ibcon#wrote, iclass 33, count 0 2006.245.07:50:17.20#ibcon#about to read 3, iclass 33, count 0 2006.245.07:50:17.22#ibcon#read 3, iclass 33, count 0 2006.245.07:50:17.22#ibcon#about to read 4, iclass 33, count 0 2006.245.07:50:17.22#ibcon#read 4, iclass 33, count 0 2006.245.07:50:17.22#ibcon#about to read 5, iclass 33, count 0 2006.245.07:50:17.22#ibcon#read 5, iclass 33, count 0 2006.245.07:50:17.22#ibcon#about to read 6, iclass 33, count 0 2006.245.07:50:17.22#ibcon#read 6, iclass 33, count 0 2006.245.07:50:17.22#ibcon#end of sib2, iclass 33, count 0 2006.245.07:50:17.22#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:50:17.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:50:17.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:50:17.22#ibcon#*before write, iclass 33, count 0 2006.245.07:50:17.22#ibcon#enter sib2, iclass 33, count 0 2006.245.07:50:17.22#ibcon#flushed, iclass 33, count 0 2006.245.07:50:17.22#ibcon#about to write, iclass 33, count 0 2006.245.07:50:17.22#ibcon#wrote, iclass 33, count 0 2006.245.07:50:17.22#ibcon#about to read 3, iclass 33, count 0 2006.245.07:50:17.26#ibcon#read 3, iclass 33, count 0 2006.245.07:50:17.26#ibcon#about to read 4, iclass 33, count 0 2006.245.07:50:17.26#ibcon#read 4, iclass 33, count 0 2006.245.07:50:17.26#ibcon#about to read 5, iclass 33, count 0 2006.245.07:50:17.26#ibcon#read 5, iclass 33, count 0 2006.245.07:50:17.26#ibcon#about to read 6, iclass 33, count 0 2006.245.07:50:17.26#ibcon#read 6, iclass 33, count 0 2006.245.07:50:17.26#ibcon#end of sib2, iclass 33, count 0 2006.245.07:50:17.26#ibcon#*after write, iclass 33, count 0 2006.245.07:50:17.26#ibcon#*before return 0, iclass 33, count 0 2006.245.07:50:17.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:17.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.07:50:17.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:50:17.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:50:17.26$vc4f8/vb=2,4 2006.245.07:50:17.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.07:50:17.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.07:50:17.26#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:17.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:17.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:17.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:17.32#ibcon#enter wrdev, iclass 35, count 2 2006.245.07:50:17.32#ibcon#first serial, iclass 35, count 2 2006.245.07:50:17.32#ibcon#enter sib2, iclass 35, count 2 2006.245.07:50:17.32#ibcon#flushed, iclass 35, count 2 2006.245.07:50:17.32#ibcon#about to write, iclass 35, count 2 2006.245.07:50:17.32#ibcon#wrote, iclass 35, count 2 2006.245.07:50:17.32#ibcon#about to read 3, iclass 35, count 2 2006.245.07:50:17.34#ibcon#read 3, iclass 35, count 2 2006.245.07:50:17.34#ibcon#about to read 4, iclass 35, count 2 2006.245.07:50:17.34#ibcon#read 4, iclass 35, count 2 2006.245.07:50:17.34#ibcon#about to read 5, iclass 35, count 2 2006.245.07:50:17.34#ibcon#read 5, iclass 35, count 2 2006.245.07:50:17.34#ibcon#about to read 6, iclass 35, count 2 2006.245.07:50:17.34#ibcon#read 6, iclass 35, count 2 2006.245.07:50:17.34#ibcon#end of sib2, iclass 35, count 2 2006.245.07:50:17.34#ibcon#*mode == 0, iclass 35, count 2 2006.245.07:50:17.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.07:50:17.34#ibcon#[27=AT02-04\r\n] 2006.245.07:50:17.34#ibcon#*before write, iclass 35, count 2 2006.245.07:50:17.34#ibcon#enter sib2, iclass 35, count 2 2006.245.07:50:17.34#ibcon#flushed, iclass 35, count 2 2006.245.07:50:17.34#ibcon#about to write, iclass 35, count 2 2006.245.07:50:17.34#ibcon#wrote, iclass 35, count 2 2006.245.07:50:17.34#ibcon#about to read 3, iclass 35, count 2 2006.245.07:50:17.37#ibcon#read 3, iclass 35, count 2 2006.245.07:50:17.37#ibcon#about to read 4, iclass 35, count 2 2006.245.07:50:17.37#ibcon#read 4, iclass 35, count 2 2006.245.07:50:17.37#ibcon#about to read 5, iclass 35, count 2 2006.245.07:50:17.37#ibcon#read 5, iclass 35, count 2 2006.245.07:50:17.37#ibcon#about to read 6, iclass 35, count 2 2006.245.07:50:17.37#ibcon#read 6, iclass 35, count 2 2006.245.07:50:17.37#ibcon#end of sib2, iclass 35, count 2 2006.245.07:50:17.37#ibcon#*after write, iclass 35, count 2 2006.245.07:50:17.37#ibcon#*before return 0, iclass 35, count 2 2006.245.07:50:17.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:17.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.07:50:17.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.07:50:17.37#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:17.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:17.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:17.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:17.49#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:50:17.49#ibcon#first serial, iclass 35, count 0 2006.245.07:50:17.49#ibcon#enter sib2, iclass 35, count 0 2006.245.07:50:17.49#ibcon#flushed, iclass 35, count 0 2006.245.07:50:17.49#ibcon#about to write, iclass 35, count 0 2006.245.07:50:17.49#ibcon#wrote, iclass 35, count 0 2006.245.07:50:17.49#ibcon#about to read 3, iclass 35, count 0 2006.245.07:50:17.51#ibcon#read 3, iclass 35, count 0 2006.245.07:50:17.51#ibcon#about to read 4, iclass 35, count 0 2006.245.07:50:17.51#ibcon#read 4, iclass 35, count 0 2006.245.07:50:17.51#ibcon#about to read 5, iclass 35, count 0 2006.245.07:50:17.51#ibcon#read 5, iclass 35, count 0 2006.245.07:50:17.51#ibcon#about to read 6, iclass 35, count 0 2006.245.07:50:17.51#ibcon#read 6, iclass 35, count 0 2006.245.07:50:17.51#ibcon#end of sib2, iclass 35, count 0 2006.245.07:50:17.51#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:50:17.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:50:17.51#ibcon#[27=USB\r\n] 2006.245.07:50:17.51#ibcon#*before write, iclass 35, count 0 2006.245.07:50:17.51#ibcon#enter sib2, iclass 35, count 0 2006.245.07:50:17.51#ibcon#flushed, iclass 35, count 0 2006.245.07:50:17.51#ibcon#about to write, iclass 35, count 0 2006.245.07:50:17.51#ibcon#wrote, iclass 35, count 0 2006.245.07:50:17.51#ibcon#about to read 3, iclass 35, count 0 2006.245.07:50:17.54#ibcon#read 3, iclass 35, count 0 2006.245.07:50:17.54#ibcon#about to read 4, iclass 35, count 0 2006.245.07:50:17.54#ibcon#read 4, iclass 35, count 0 2006.245.07:50:17.54#ibcon#about to read 5, iclass 35, count 0 2006.245.07:50:17.54#ibcon#read 5, iclass 35, count 0 2006.245.07:50:17.54#ibcon#about to read 6, iclass 35, count 0 2006.245.07:50:17.54#ibcon#read 6, iclass 35, count 0 2006.245.07:50:17.54#ibcon#end of sib2, iclass 35, count 0 2006.245.07:50:17.54#ibcon#*after write, iclass 35, count 0 2006.245.07:50:17.54#ibcon#*before return 0, iclass 35, count 0 2006.245.07:50:17.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:17.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.07:50:17.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:50:17.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:50:17.54$vc4f8/vblo=3,656.99 2006.245.07:50:17.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.07:50:17.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.07:50:17.54#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:17.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:17.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:17.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:17.54#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:50:17.54#ibcon#first serial, iclass 37, count 0 2006.245.07:50:17.54#ibcon#enter sib2, iclass 37, count 0 2006.245.07:50:17.54#ibcon#flushed, iclass 37, count 0 2006.245.07:50:17.54#ibcon#about to write, iclass 37, count 0 2006.245.07:50:17.54#ibcon#wrote, iclass 37, count 0 2006.245.07:50:17.54#ibcon#about to read 3, iclass 37, count 0 2006.245.07:50:17.56#ibcon#read 3, iclass 37, count 0 2006.245.07:50:17.56#ibcon#about to read 4, iclass 37, count 0 2006.245.07:50:17.56#ibcon#read 4, iclass 37, count 0 2006.245.07:50:17.56#ibcon#about to read 5, iclass 37, count 0 2006.245.07:50:17.56#ibcon#read 5, iclass 37, count 0 2006.245.07:50:17.56#ibcon#about to read 6, iclass 37, count 0 2006.245.07:50:17.56#ibcon#read 6, iclass 37, count 0 2006.245.07:50:17.56#ibcon#end of sib2, iclass 37, count 0 2006.245.07:50:17.56#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:50:17.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:50:17.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:50:17.56#ibcon#*before write, iclass 37, count 0 2006.245.07:50:17.56#ibcon#enter sib2, iclass 37, count 0 2006.245.07:50:17.56#ibcon#flushed, iclass 37, count 0 2006.245.07:50:17.56#ibcon#about to write, iclass 37, count 0 2006.245.07:50:17.56#ibcon#wrote, iclass 37, count 0 2006.245.07:50:17.56#ibcon#about to read 3, iclass 37, count 0 2006.245.07:50:17.60#ibcon#read 3, iclass 37, count 0 2006.245.07:50:17.60#ibcon#about to read 4, iclass 37, count 0 2006.245.07:50:17.60#ibcon#read 4, iclass 37, count 0 2006.245.07:50:17.60#ibcon#about to read 5, iclass 37, count 0 2006.245.07:50:17.60#ibcon#read 5, iclass 37, count 0 2006.245.07:50:17.60#ibcon#about to read 6, iclass 37, count 0 2006.245.07:50:17.60#ibcon#read 6, iclass 37, count 0 2006.245.07:50:17.60#ibcon#end of sib2, iclass 37, count 0 2006.245.07:50:17.60#ibcon#*after write, iclass 37, count 0 2006.245.07:50:17.60#ibcon#*before return 0, iclass 37, count 0 2006.245.07:50:17.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:17.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.07:50:17.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:50:17.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:50:17.60$vc4f8/vb=3,4 2006.245.07:50:17.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.07:50:17.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.07:50:17.60#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:17.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:17.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:17.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:17.66#ibcon#enter wrdev, iclass 39, count 2 2006.245.07:50:17.66#ibcon#first serial, iclass 39, count 2 2006.245.07:50:17.66#ibcon#enter sib2, iclass 39, count 2 2006.245.07:50:17.66#ibcon#flushed, iclass 39, count 2 2006.245.07:50:17.66#ibcon#about to write, iclass 39, count 2 2006.245.07:50:17.66#ibcon#wrote, iclass 39, count 2 2006.245.07:50:17.66#ibcon#about to read 3, iclass 39, count 2 2006.245.07:50:17.68#ibcon#read 3, iclass 39, count 2 2006.245.07:50:17.68#ibcon#about to read 4, iclass 39, count 2 2006.245.07:50:17.68#ibcon#read 4, iclass 39, count 2 2006.245.07:50:17.68#ibcon#about to read 5, iclass 39, count 2 2006.245.07:50:17.68#ibcon#read 5, iclass 39, count 2 2006.245.07:50:17.68#ibcon#about to read 6, iclass 39, count 2 2006.245.07:50:17.68#ibcon#read 6, iclass 39, count 2 2006.245.07:50:17.68#ibcon#end of sib2, iclass 39, count 2 2006.245.07:50:17.68#ibcon#*mode == 0, iclass 39, count 2 2006.245.07:50:17.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.07:50:17.68#ibcon#[27=AT03-04\r\n] 2006.245.07:50:17.68#ibcon#*before write, iclass 39, count 2 2006.245.07:50:17.68#ibcon#enter sib2, iclass 39, count 2 2006.245.07:50:17.68#ibcon#flushed, iclass 39, count 2 2006.245.07:50:17.68#ibcon#about to write, iclass 39, count 2 2006.245.07:50:17.68#ibcon#wrote, iclass 39, count 2 2006.245.07:50:17.68#ibcon#about to read 3, iclass 39, count 2 2006.245.07:50:17.71#ibcon#read 3, iclass 39, count 2 2006.245.07:50:17.71#ibcon#about to read 4, iclass 39, count 2 2006.245.07:50:17.71#ibcon#read 4, iclass 39, count 2 2006.245.07:50:17.71#ibcon#about to read 5, iclass 39, count 2 2006.245.07:50:17.71#ibcon#read 5, iclass 39, count 2 2006.245.07:50:17.71#ibcon#about to read 6, iclass 39, count 2 2006.245.07:50:17.71#ibcon#read 6, iclass 39, count 2 2006.245.07:50:17.71#ibcon#end of sib2, iclass 39, count 2 2006.245.07:50:17.71#ibcon#*after write, iclass 39, count 2 2006.245.07:50:17.71#ibcon#*before return 0, iclass 39, count 2 2006.245.07:50:17.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:17.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.07:50:17.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.07:50:17.71#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:17.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:17.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:17.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:17.83#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:50:17.83#ibcon#first serial, iclass 39, count 0 2006.245.07:50:17.83#ibcon#enter sib2, iclass 39, count 0 2006.245.07:50:17.83#ibcon#flushed, iclass 39, count 0 2006.245.07:50:17.83#ibcon#about to write, iclass 39, count 0 2006.245.07:50:17.83#ibcon#wrote, iclass 39, count 0 2006.245.07:50:17.83#ibcon#about to read 3, iclass 39, count 0 2006.245.07:50:17.85#ibcon#read 3, iclass 39, count 0 2006.245.07:50:17.85#ibcon#about to read 4, iclass 39, count 0 2006.245.07:50:17.85#ibcon#read 4, iclass 39, count 0 2006.245.07:50:17.85#ibcon#about to read 5, iclass 39, count 0 2006.245.07:50:17.85#ibcon#read 5, iclass 39, count 0 2006.245.07:50:17.85#ibcon#about to read 6, iclass 39, count 0 2006.245.07:50:17.85#ibcon#read 6, iclass 39, count 0 2006.245.07:50:17.85#ibcon#end of sib2, iclass 39, count 0 2006.245.07:50:17.85#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:50:17.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:50:17.85#ibcon#[27=USB\r\n] 2006.245.07:50:17.85#ibcon#*before write, iclass 39, count 0 2006.245.07:50:17.85#ibcon#enter sib2, iclass 39, count 0 2006.245.07:50:17.85#ibcon#flushed, iclass 39, count 0 2006.245.07:50:17.85#ibcon#about to write, iclass 39, count 0 2006.245.07:50:17.85#ibcon#wrote, iclass 39, count 0 2006.245.07:50:17.85#ibcon#about to read 3, iclass 39, count 0 2006.245.07:50:17.88#ibcon#read 3, iclass 39, count 0 2006.245.07:50:17.88#ibcon#about to read 4, iclass 39, count 0 2006.245.07:50:17.88#ibcon#read 4, iclass 39, count 0 2006.245.07:50:17.88#ibcon#about to read 5, iclass 39, count 0 2006.245.07:50:17.88#ibcon#read 5, iclass 39, count 0 2006.245.07:50:17.88#ibcon#about to read 6, iclass 39, count 0 2006.245.07:50:17.88#ibcon#read 6, iclass 39, count 0 2006.245.07:50:17.88#ibcon#end of sib2, iclass 39, count 0 2006.245.07:50:17.88#ibcon#*after write, iclass 39, count 0 2006.245.07:50:17.88#ibcon#*before return 0, iclass 39, count 0 2006.245.07:50:17.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:17.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.07:50:17.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:50:17.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:50:17.88$vc4f8/vblo=4,712.99 2006.245.07:50:17.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.07:50:17.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.07:50:17.88#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:17.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:17.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:17.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:17.88#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:50:17.88#ibcon#first serial, iclass 3, count 0 2006.245.07:50:17.88#ibcon#enter sib2, iclass 3, count 0 2006.245.07:50:17.88#ibcon#flushed, iclass 3, count 0 2006.245.07:50:17.88#ibcon#about to write, iclass 3, count 0 2006.245.07:50:17.88#ibcon#wrote, iclass 3, count 0 2006.245.07:50:17.88#ibcon#about to read 3, iclass 3, count 0 2006.245.07:50:17.90#ibcon#read 3, iclass 3, count 0 2006.245.07:50:17.90#ibcon#about to read 4, iclass 3, count 0 2006.245.07:50:17.90#ibcon#read 4, iclass 3, count 0 2006.245.07:50:17.90#ibcon#about to read 5, iclass 3, count 0 2006.245.07:50:17.90#ibcon#read 5, iclass 3, count 0 2006.245.07:50:17.90#ibcon#about to read 6, iclass 3, count 0 2006.245.07:50:17.90#ibcon#read 6, iclass 3, count 0 2006.245.07:50:17.90#ibcon#end of sib2, iclass 3, count 0 2006.245.07:50:17.90#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:50:17.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:50:17.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:50:17.90#ibcon#*before write, iclass 3, count 0 2006.245.07:50:17.90#ibcon#enter sib2, iclass 3, count 0 2006.245.07:50:17.90#ibcon#flushed, iclass 3, count 0 2006.245.07:50:17.90#ibcon#about to write, iclass 3, count 0 2006.245.07:50:17.90#ibcon#wrote, iclass 3, count 0 2006.245.07:50:17.90#ibcon#about to read 3, iclass 3, count 0 2006.245.07:50:17.94#ibcon#read 3, iclass 3, count 0 2006.245.07:50:17.94#ibcon#about to read 4, iclass 3, count 0 2006.245.07:50:17.94#ibcon#read 4, iclass 3, count 0 2006.245.07:50:17.94#ibcon#about to read 5, iclass 3, count 0 2006.245.07:50:17.94#ibcon#read 5, iclass 3, count 0 2006.245.07:50:17.94#ibcon#about to read 6, iclass 3, count 0 2006.245.07:50:17.94#ibcon#read 6, iclass 3, count 0 2006.245.07:50:17.94#ibcon#end of sib2, iclass 3, count 0 2006.245.07:50:17.94#ibcon#*after write, iclass 3, count 0 2006.245.07:50:17.94#ibcon#*before return 0, iclass 3, count 0 2006.245.07:50:17.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:17.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.07:50:17.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:50:17.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:50:17.94$vc4f8/vb=4,4 2006.245.07:50:17.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.07:50:17.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.07:50:17.94#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:17.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:18.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:18.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:18.00#ibcon#enter wrdev, iclass 5, count 2 2006.245.07:50:18.00#ibcon#first serial, iclass 5, count 2 2006.245.07:50:18.00#ibcon#enter sib2, iclass 5, count 2 2006.245.07:50:18.00#ibcon#flushed, iclass 5, count 2 2006.245.07:50:18.00#ibcon#about to write, iclass 5, count 2 2006.245.07:50:18.00#ibcon#wrote, iclass 5, count 2 2006.245.07:50:18.00#ibcon#about to read 3, iclass 5, count 2 2006.245.07:50:18.02#ibcon#read 3, iclass 5, count 2 2006.245.07:50:18.02#ibcon#about to read 4, iclass 5, count 2 2006.245.07:50:18.02#ibcon#read 4, iclass 5, count 2 2006.245.07:50:18.02#ibcon#about to read 5, iclass 5, count 2 2006.245.07:50:18.02#ibcon#read 5, iclass 5, count 2 2006.245.07:50:18.02#ibcon#about to read 6, iclass 5, count 2 2006.245.07:50:18.02#ibcon#read 6, iclass 5, count 2 2006.245.07:50:18.02#ibcon#end of sib2, iclass 5, count 2 2006.245.07:50:18.02#ibcon#*mode == 0, iclass 5, count 2 2006.245.07:50:18.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.07:50:18.02#ibcon#[27=AT04-04\r\n] 2006.245.07:50:18.02#ibcon#*before write, iclass 5, count 2 2006.245.07:50:18.02#ibcon#enter sib2, iclass 5, count 2 2006.245.07:50:18.02#ibcon#flushed, iclass 5, count 2 2006.245.07:50:18.02#ibcon#about to write, iclass 5, count 2 2006.245.07:50:18.02#ibcon#wrote, iclass 5, count 2 2006.245.07:50:18.02#ibcon#about to read 3, iclass 5, count 2 2006.245.07:50:18.05#ibcon#read 3, iclass 5, count 2 2006.245.07:50:18.05#ibcon#about to read 4, iclass 5, count 2 2006.245.07:50:18.05#ibcon#read 4, iclass 5, count 2 2006.245.07:50:18.05#ibcon#about to read 5, iclass 5, count 2 2006.245.07:50:18.05#ibcon#read 5, iclass 5, count 2 2006.245.07:50:18.05#ibcon#about to read 6, iclass 5, count 2 2006.245.07:50:18.05#ibcon#read 6, iclass 5, count 2 2006.245.07:50:18.05#ibcon#end of sib2, iclass 5, count 2 2006.245.07:50:18.05#ibcon#*after write, iclass 5, count 2 2006.245.07:50:18.05#ibcon#*before return 0, iclass 5, count 2 2006.245.07:50:18.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:18.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.07:50:18.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.07:50:18.05#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:18.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:18.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:18.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:18.17#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:50:18.17#ibcon#first serial, iclass 5, count 0 2006.245.07:50:18.17#ibcon#enter sib2, iclass 5, count 0 2006.245.07:50:18.17#ibcon#flushed, iclass 5, count 0 2006.245.07:50:18.17#ibcon#about to write, iclass 5, count 0 2006.245.07:50:18.17#ibcon#wrote, iclass 5, count 0 2006.245.07:50:18.17#ibcon#about to read 3, iclass 5, count 0 2006.245.07:50:18.19#ibcon#read 3, iclass 5, count 0 2006.245.07:50:18.19#ibcon#about to read 4, iclass 5, count 0 2006.245.07:50:18.19#ibcon#read 4, iclass 5, count 0 2006.245.07:50:18.19#ibcon#about to read 5, iclass 5, count 0 2006.245.07:50:18.19#ibcon#read 5, iclass 5, count 0 2006.245.07:50:18.19#ibcon#about to read 6, iclass 5, count 0 2006.245.07:50:18.19#ibcon#read 6, iclass 5, count 0 2006.245.07:50:18.19#ibcon#end of sib2, iclass 5, count 0 2006.245.07:50:18.19#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:50:18.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:50:18.19#ibcon#[27=USB\r\n] 2006.245.07:50:18.19#ibcon#*before write, iclass 5, count 0 2006.245.07:50:18.19#ibcon#enter sib2, iclass 5, count 0 2006.245.07:50:18.19#ibcon#flushed, iclass 5, count 0 2006.245.07:50:18.19#ibcon#about to write, iclass 5, count 0 2006.245.07:50:18.19#ibcon#wrote, iclass 5, count 0 2006.245.07:50:18.19#ibcon#about to read 3, iclass 5, count 0 2006.245.07:50:18.22#ibcon#read 3, iclass 5, count 0 2006.245.07:50:18.22#ibcon#about to read 4, iclass 5, count 0 2006.245.07:50:18.22#ibcon#read 4, iclass 5, count 0 2006.245.07:50:18.22#ibcon#about to read 5, iclass 5, count 0 2006.245.07:50:18.22#ibcon#read 5, iclass 5, count 0 2006.245.07:50:18.22#ibcon#about to read 6, iclass 5, count 0 2006.245.07:50:18.22#ibcon#read 6, iclass 5, count 0 2006.245.07:50:18.22#ibcon#end of sib2, iclass 5, count 0 2006.245.07:50:18.22#ibcon#*after write, iclass 5, count 0 2006.245.07:50:18.22#ibcon#*before return 0, iclass 5, count 0 2006.245.07:50:18.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:18.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.07:50:18.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:50:18.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:50:18.22$vc4f8/vblo=5,744.99 2006.245.07:50:18.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.07:50:18.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.07:50:18.22#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:18.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:18.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:18.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:18.22#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:50:18.22#ibcon#first serial, iclass 7, count 0 2006.245.07:50:18.22#ibcon#enter sib2, iclass 7, count 0 2006.245.07:50:18.22#ibcon#flushed, iclass 7, count 0 2006.245.07:50:18.22#ibcon#about to write, iclass 7, count 0 2006.245.07:50:18.22#ibcon#wrote, iclass 7, count 0 2006.245.07:50:18.22#ibcon#about to read 3, iclass 7, count 0 2006.245.07:50:18.24#ibcon#read 3, iclass 7, count 0 2006.245.07:50:18.24#ibcon#about to read 4, iclass 7, count 0 2006.245.07:50:18.24#ibcon#read 4, iclass 7, count 0 2006.245.07:50:18.24#ibcon#about to read 5, iclass 7, count 0 2006.245.07:50:18.24#ibcon#read 5, iclass 7, count 0 2006.245.07:50:18.24#ibcon#about to read 6, iclass 7, count 0 2006.245.07:50:18.24#ibcon#read 6, iclass 7, count 0 2006.245.07:50:18.24#ibcon#end of sib2, iclass 7, count 0 2006.245.07:50:18.24#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:50:18.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:50:18.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:50:18.24#ibcon#*before write, iclass 7, count 0 2006.245.07:50:18.24#ibcon#enter sib2, iclass 7, count 0 2006.245.07:50:18.24#ibcon#flushed, iclass 7, count 0 2006.245.07:50:18.24#ibcon#about to write, iclass 7, count 0 2006.245.07:50:18.24#ibcon#wrote, iclass 7, count 0 2006.245.07:50:18.24#ibcon#about to read 3, iclass 7, count 0 2006.245.07:50:18.28#ibcon#read 3, iclass 7, count 0 2006.245.07:50:18.28#ibcon#about to read 4, iclass 7, count 0 2006.245.07:50:18.28#ibcon#read 4, iclass 7, count 0 2006.245.07:50:18.28#ibcon#about to read 5, iclass 7, count 0 2006.245.07:50:18.28#ibcon#read 5, iclass 7, count 0 2006.245.07:50:18.28#ibcon#about to read 6, iclass 7, count 0 2006.245.07:50:18.28#ibcon#read 6, iclass 7, count 0 2006.245.07:50:18.28#ibcon#end of sib2, iclass 7, count 0 2006.245.07:50:18.28#ibcon#*after write, iclass 7, count 0 2006.245.07:50:18.28#ibcon#*before return 0, iclass 7, count 0 2006.245.07:50:18.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:18.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.07:50:18.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:50:18.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:50:18.28$vc4f8/vb=5,3 2006.245.07:50:18.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.07:50:18.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.07:50:18.28#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:18.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:18.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:18.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:18.34#ibcon#enter wrdev, iclass 11, count 2 2006.245.07:50:18.34#ibcon#first serial, iclass 11, count 2 2006.245.07:50:18.34#ibcon#enter sib2, iclass 11, count 2 2006.245.07:50:18.34#ibcon#flushed, iclass 11, count 2 2006.245.07:50:18.34#ibcon#about to write, iclass 11, count 2 2006.245.07:50:18.34#ibcon#wrote, iclass 11, count 2 2006.245.07:50:18.34#ibcon#about to read 3, iclass 11, count 2 2006.245.07:50:18.36#ibcon#read 3, iclass 11, count 2 2006.245.07:50:18.36#ibcon#about to read 4, iclass 11, count 2 2006.245.07:50:18.36#ibcon#read 4, iclass 11, count 2 2006.245.07:50:18.36#ibcon#about to read 5, iclass 11, count 2 2006.245.07:50:18.36#ibcon#read 5, iclass 11, count 2 2006.245.07:50:18.36#ibcon#about to read 6, iclass 11, count 2 2006.245.07:50:18.36#ibcon#read 6, iclass 11, count 2 2006.245.07:50:18.36#ibcon#end of sib2, iclass 11, count 2 2006.245.07:50:18.36#ibcon#*mode == 0, iclass 11, count 2 2006.245.07:50:18.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.07:50:18.36#ibcon#[27=AT05-03\r\n] 2006.245.07:50:18.36#ibcon#*before write, iclass 11, count 2 2006.245.07:50:18.36#ibcon#enter sib2, iclass 11, count 2 2006.245.07:50:18.36#ibcon#flushed, iclass 11, count 2 2006.245.07:50:18.36#ibcon#about to write, iclass 11, count 2 2006.245.07:50:18.36#ibcon#wrote, iclass 11, count 2 2006.245.07:50:18.36#ibcon#about to read 3, iclass 11, count 2 2006.245.07:50:18.39#ibcon#read 3, iclass 11, count 2 2006.245.07:50:18.39#ibcon#about to read 4, iclass 11, count 2 2006.245.07:50:18.39#ibcon#read 4, iclass 11, count 2 2006.245.07:50:18.39#ibcon#about to read 5, iclass 11, count 2 2006.245.07:50:18.39#ibcon#read 5, iclass 11, count 2 2006.245.07:50:18.39#ibcon#about to read 6, iclass 11, count 2 2006.245.07:50:18.39#ibcon#read 6, iclass 11, count 2 2006.245.07:50:18.39#ibcon#end of sib2, iclass 11, count 2 2006.245.07:50:18.39#ibcon#*after write, iclass 11, count 2 2006.245.07:50:18.39#ibcon#*before return 0, iclass 11, count 2 2006.245.07:50:18.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:18.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.07:50:18.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.07:50:18.39#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:18.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:18.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:18.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:18.51#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:50:18.51#ibcon#first serial, iclass 11, count 0 2006.245.07:50:18.51#ibcon#enter sib2, iclass 11, count 0 2006.245.07:50:18.51#ibcon#flushed, iclass 11, count 0 2006.245.07:50:18.51#ibcon#about to write, iclass 11, count 0 2006.245.07:50:18.51#ibcon#wrote, iclass 11, count 0 2006.245.07:50:18.51#ibcon#about to read 3, iclass 11, count 0 2006.245.07:50:18.53#ibcon#read 3, iclass 11, count 0 2006.245.07:50:18.53#ibcon#about to read 4, iclass 11, count 0 2006.245.07:50:18.53#ibcon#read 4, iclass 11, count 0 2006.245.07:50:18.53#ibcon#about to read 5, iclass 11, count 0 2006.245.07:50:18.53#ibcon#read 5, iclass 11, count 0 2006.245.07:50:18.53#ibcon#about to read 6, iclass 11, count 0 2006.245.07:50:18.53#ibcon#read 6, iclass 11, count 0 2006.245.07:50:18.53#ibcon#end of sib2, iclass 11, count 0 2006.245.07:50:18.53#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:50:18.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:50:18.53#ibcon#[27=USB\r\n] 2006.245.07:50:18.53#ibcon#*before write, iclass 11, count 0 2006.245.07:50:18.53#ibcon#enter sib2, iclass 11, count 0 2006.245.07:50:18.53#ibcon#flushed, iclass 11, count 0 2006.245.07:50:18.53#ibcon#about to write, iclass 11, count 0 2006.245.07:50:18.53#ibcon#wrote, iclass 11, count 0 2006.245.07:50:18.53#ibcon#about to read 3, iclass 11, count 0 2006.245.07:50:18.56#ibcon#read 3, iclass 11, count 0 2006.245.07:50:18.56#ibcon#about to read 4, iclass 11, count 0 2006.245.07:50:18.56#ibcon#read 4, iclass 11, count 0 2006.245.07:50:18.56#ibcon#about to read 5, iclass 11, count 0 2006.245.07:50:18.56#ibcon#read 5, iclass 11, count 0 2006.245.07:50:18.56#ibcon#about to read 6, iclass 11, count 0 2006.245.07:50:18.56#ibcon#read 6, iclass 11, count 0 2006.245.07:50:18.56#ibcon#end of sib2, iclass 11, count 0 2006.245.07:50:18.56#ibcon#*after write, iclass 11, count 0 2006.245.07:50:18.56#ibcon#*before return 0, iclass 11, count 0 2006.245.07:50:18.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:18.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.07:50:18.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:50:18.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:50:18.56$vc4f8/vblo=6,752.99 2006.245.07:50:18.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.07:50:18.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.07:50:18.56#ibcon#ireg 17 cls_cnt 0 2006.245.07:50:18.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:50:18.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:50:18.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:50:18.56#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:50:18.56#ibcon#first serial, iclass 13, count 0 2006.245.07:50:18.56#ibcon#enter sib2, iclass 13, count 0 2006.245.07:50:18.56#ibcon#flushed, iclass 13, count 0 2006.245.07:50:18.56#ibcon#about to write, iclass 13, count 0 2006.245.07:50:18.56#ibcon#wrote, iclass 13, count 0 2006.245.07:50:18.56#ibcon#about to read 3, iclass 13, count 0 2006.245.07:50:18.58#ibcon#read 3, iclass 13, count 0 2006.245.07:50:18.58#ibcon#about to read 4, iclass 13, count 0 2006.245.07:50:18.58#ibcon#read 4, iclass 13, count 0 2006.245.07:50:18.58#ibcon#about to read 5, iclass 13, count 0 2006.245.07:50:18.58#ibcon#read 5, iclass 13, count 0 2006.245.07:50:18.58#ibcon#about to read 6, iclass 13, count 0 2006.245.07:50:18.58#ibcon#read 6, iclass 13, count 0 2006.245.07:50:18.58#ibcon#end of sib2, iclass 13, count 0 2006.245.07:50:18.58#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:50:18.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:50:18.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:50:18.58#ibcon#*before write, iclass 13, count 0 2006.245.07:50:18.58#ibcon#enter sib2, iclass 13, count 0 2006.245.07:50:18.58#ibcon#flushed, iclass 13, count 0 2006.245.07:50:18.58#ibcon#about to write, iclass 13, count 0 2006.245.07:50:18.58#ibcon#wrote, iclass 13, count 0 2006.245.07:50:18.58#ibcon#about to read 3, iclass 13, count 0 2006.245.07:50:18.62#ibcon#read 3, iclass 13, count 0 2006.245.07:50:18.62#ibcon#about to read 4, iclass 13, count 0 2006.245.07:50:18.62#ibcon#read 4, iclass 13, count 0 2006.245.07:50:18.62#ibcon#about to read 5, iclass 13, count 0 2006.245.07:50:18.62#ibcon#read 5, iclass 13, count 0 2006.245.07:50:18.62#ibcon#about to read 6, iclass 13, count 0 2006.245.07:50:18.62#ibcon#read 6, iclass 13, count 0 2006.245.07:50:18.62#ibcon#end of sib2, iclass 13, count 0 2006.245.07:50:18.62#ibcon#*after write, iclass 13, count 0 2006.245.07:50:18.62#ibcon#*before return 0, iclass 13, count 0 2006.245.07:50:18.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:50:18.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:50:18.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:50:18.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:50:18.62$vc4f8/vb=6,3 2006.245.07:50:18.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.07:50:18.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.07:50:18.62#ibcon#ireg 11 cls_cnt 2 2006.245.07:50:18.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:50:18.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:50:18.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:50:18.68#ibcon#enter wrdev, iclass 15, count 2 2006.245.07:50:18.68#ibcon#first serial, iclass 15, count 2 2006.245.07:50:18.68#ibcon#enter sib2, iclass 15, count 2 2006.245.07:50:18.68#ibcon#flushed, iclass 15, count 2 2006.245.07:50:18.68#ibcon#about to write, iclass 15, count 2 2006.245.07:50:18.68#ibcon#wrote, iclass 15, count 2 2006.245.07:50:18.68#ibcon#about to read 3, iclass 15, count 2 2006.245.07:50:18.70#ibcon#read 3, iclass 15, count 2 2006.245.07:50:18.70#ibcon#about to read 4, iclass 15, count 2 2006.245.07:50:18.70#ibcon#read 4, iclass 15, count 2 2006.245.07:50:18.70#ibcon#about to read 5, iclass 15, count 2 2006.245.07:50:18.70#ibcon#read 5, iclass 15, count 2 2006.245.07:50:18.70#ibcon#about to read 6, iclass 15, count 2 2006.245.07:50:18.70#ibcon#read 6, iclass 15, count 2 2006.245.07:50:18.70#ibcon#end of sib2, iclass 15, count 2 2006.245.07:50:18.70#ibcon#*mode == 0, iclass 15, count 2 2006.245.07:50:18.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.07:50:18.70#ibcon#[27=AT06-03\r\n] 2006.245.07:50:18.70#ibcon#*before write, iclass 15, count 2 2006.245.07:50:18.70#ibcon#enter sib2, iclass 15, count 2 2006.245.07:50:18.70#ibcon#flushed, iclass 15, count 2 2006.245.07:50:18.70#ibcon#about to write, iclass 15, count 2 2006.245.07:50:18.70#ibcon#wrote, iclass 15, count 2 2006.245.07:50:18.70#ibcon#about to read 3, iclass 15, count 2 2006.245.07:50:18.73#ibcon#read 3, iclass 15, count 2 2006.245.07:50:18.73#ibcon#about to read 4, iclass 15, count 2 2006.245.07:50:18.73#ibcon#read 4, iclass 15, count 2 2006.245.07:50:18.73#ibcon#about to read 5, iclass 15, count 2 2006.245.07:50:18.73#ibcon#read 5, iclass 15, count 2 2006.245.07:50:18.73#ibcon#about to read 6, iclass 15, count 2 2006.245.07:50:18.73#ibcon#read 6, iclass 15, count 2 2006.245.07:50:18.73#ibcon#end of sib2, iclass 15, count 2 2006.245.07:50:18.73#ibcon#*after write, iclass 15, count 2 2006.245.07:50:18.73#ibcon#*before return 0, iclass 15, count 2 2006.245.07:50:18.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:50:18.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.07:50:18.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.07:50:18.73#ibcon#ireg 7 cls_cnt 0 2006.245.07:50:18.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:50:18.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:50:18.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:50:18.85#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:50:18.85#ibcon#first serial, iclass 15, count 0 2006.245.07:50:18.85#ibcon#enter sib2, iclass 15, count 0 2006.245.07:50:18.85#ibcon#flushed, iclass 15, count 0 2006.245.07:50:18.85#ibcon#about to write, iclass 15, count 0 2006.245.07:50:18.85#ibcon#wrote, iclass 15, count 0 2006.245.07:50:18.85#ibcon#about to read 3, iclass 15, count 0 2006.245.07:50:18.87#ibcon#read 3, iclass 15, count 0 2006.245.07:50:18.87#ibcon#about to read 4, iclass 15, count 0 2006.245.07:50:18.87#ibcon#read 4, iclass 15, count 0 2006.245.07:50:18.87#ibcon#about to read 5, iclass 15, count 0 2006.245.07:50:18.87#ibcon#read 5, iclass 15, count 0 2006.245.07:50:18.87#ibcon#about to read 6, iclass 15, count 0 2006.245.07:50:18.87#ibcon#read 6, iclass 15, count 0 2006.245.07:50:18.87#ibcon#end of sib2, iclass 15, count 0 2006.245.07:50:18.87#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:50:18.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:50:18.87#ibcon#[27=USB\r\n] 2006.245.07:50:18.87#ibcon#*before write, iclass 15, count 0 2006.245.07:50:18.87#ibcon#enter sib2, iclass 15, count 0 2006.245.07:50:18.87#ibcon#flushed, iclass 15, count 0 2006.245.07:50:18.87#ibcon#about to write, iclass 15, count 0 2006.245.07:50:18.87#ibcon#wrote, iclass 15, count 0 2006.245.07:50:18.87#ibcon#about to read 3, iclass 15, count 0 2006.245.07:50:18.90#ibcon#read 3, iclass 15, count 0 2006.245.07:50:18.90#ibcon#about to read 4, iclass 15, count 0 2006.245.07:50:18.90#ibcon#read 4, iclass 15, count 0 2006.245.07:50:18.90#ibcon#about to read 5, iclass 15, count 0 2006.245.07:50:18.90#ibcon#read 5, iclass 15, count 0 2006.245.07:50:18.90#ibcon#about to read 6, iclass 15, count 0 2006.245.07:50:18.90#ibcon#read 6, iclass 15, count 0 2006.245.07:50:18.90#ibcon#end of sib2, iclass 15, count 0 2006.245.07:50:18.90#ibcon#*after write, iclass 15, count 0 2006.245.07:50:18.90#ibcon#*before return 0, iclass 15, count 0 2006.245.07:50:18.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:50:18.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.07:50:18.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:50:18.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:50:18.90$vc4f8/vabw=wide 2006.245.07:50:18.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.07:50:18.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.07:50:18.90#ibcon#ireg 8 cls_cnt 0 2006.245.07:50:18.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:18.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:18.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:18.90#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:50:18.90#ibcon#first serial, iclass 17, count 0 2006.245.07:50:18.90#ibcon#enter sib2, iclass 17, count 0 2006.245.07:50:18.90#ibcon#flushed, iclass 17, count 0 2006.245.07:50:18.90#ibcon#about to write, iclass 17, count 0 2006.245.07:50:18.90#ibcon#wrote, iclass 17, count 0 2006.245.07:50:18.90#ibcon#about to read 3, iclass 17, count 0 2006.245.07:50:18.92#ibcon#read 3, iclass 17, count 0 2006.245.07:50:18.92#ibcon#about to read 4, iclass 17, count 0 2006.245.07:50:18.92#ibcon#read 4, iclass 17, count 0 2006.245.07:50:18.92#ibcon#about to read 5, iclass 17, count 0 2006.245.07:50:18.92#ibcon#read 5, iclass 17, count 0 2006.245.07:50:18.92#ibcon#about to read 6, iclass 17, count 0 2006.245.07:50:18.92#ibcon#read 6, iclass 17, count 0 2006.245.07:50:18.92#ibcon#end of sib2, iclass 17, count 0 2006.245.07:50:18.92#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:50:18.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:50:18.92#ibcon#[25=BW32\r\n] 2006.245.07:50:18.92#ibcon#*before write, iclass 17, count 0 2006.245.07:50:18.92#ibcon#enter sib2, iclass 17, count 0 2006.245.07:50:18.92#ibcon#flushed, iclass 17, count 0 2006.245.07:50:18.92#ibcon#about to write, iclass 17, count 0 2006.245.07:50:18.92#ibcon#wrote, iclass 17, count 0 2006.245.07:50:18.92#ibcon#about to read 3, iclass 17, count 0 2006.245.07:50:18.95#ibcon#read 3, iclass 17, count 0 2006.245.07:50:18.95#ibcon#about to read 4, iclass 17, count 0 2006.245.07:50:18.95#ibcon#read 4, iclass 17, count 0 2006.245.07:50:18.95#ibcon#about to read 5, iclass 17, count 0 2006.245.07:50:18.95#ibcon#read 5, iclass 17, count 0 2006.245.07:50:18.95#ibcon#about to read 6, iclass 17, count 0 2006.245.07:50:18.95#ibcon#read 6, iclass 17, count 0 2006.245.07:50:18.95#ibcon#end of sib2, iclass 17, count 0 2006.245.07:50:18.95#ibcon#*after write, iclass 17, count 0 2006.245.07:50:18.95#ibcon#*before return 0, iclass 17, count 0 2006.245.07:50:18.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:18.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.07:50:18.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:50:18.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:50:18.95$vc4f8/vbbw=wide 2006.245.07:50:18.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.07:50:18.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.07:50:18.95#ibcon#ireg 8 cls_cnt 0 2006.245.07:50:18.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:50:19.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:50:19.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:50:19.02#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:50:19.02#ibcon#first serial, iclass 19, count 0 2006.245.07:50:19.02#ibcon#enter sib2, iclass 19, count 0 2006.245.07:50:19.02#ibcon#flushed, iclass 19, count 0 2006.245.07:50:19.02#ibcon#about to write, iclass 19, count 0 2006.245.07:50:19.02#ibcon#wrote, iclass 19, count 0 2006.245.07:50:19.02#ibcon#about to read 3, iclass 19, count 0 2006.245.07:50:19.04#ibcon#read 3, iclass 19, count 0 2006.245.07:50:19.04#ibcon#about to read 4, iclass 19, count 0 2006.245.07:50:19.04#ibcon#read 4, iclass 19, count 0 2006.245.07:50:19.04#ibcon#about to read 5, iclass 19, count 0 2006.245.07:50:19.04#ibcon#read 5, iclass 19, count 0 2006.245.07:50:19.04#ibcon#about to read 6, iclass 19, count 0 2006.245.07:50:19.04#ibcon#read 6, iclass 19, count 0 2006.245.07:50:19.04#ibcon#end of sib2, iclass 19, count 0 2006.245.07:50:19.04#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:50:19.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:50:19.04#ibcon#[27=BW32\r\n] 2006.245.07:50:19.04#ibcon#*before write, iclass 19, count 0 2006.245.07:50:19.04#ibcon#enter sib2, iclass 19, count 0 2006.245.07:50:19.04#ibcon#flushed, iclass 19, count 0 2006.245.07:50:19.04#ibcon#about to write, iclass 19, count 0 2006.245.07:50:19.04#ibcon#wrote, iclass 19, count 0 2006.245.07:50:19.04#ibcon#about to read 3, iclass 19, count 0 2006.245.07:50:19.07#ibcon#read 3, iclass 19, count 0 2006.245.07:50:19.07#ibcon#about to read 4, iclass 19, count 0 2006.245.07:50:19.07#ibcon#read 4, iclass 19, count 0 2006.245.07:50:19.07#ibcon#about to read 5, iclass 19, count 0 2006.245.07:50:19.07#ibcon#read 5, iclass 19, count 0 2006.245.07:50:19.07#ibcon#about to read 6, iclass 19, count 0 2006.245.07:50:19.07#ibcon#read 6, iclass 19, count 0 2006.245.07:50:19.07#ibcon#end of sib2, iclass 19, count 0 2006.245.07:50:19.07#ibcon#*after write, iclass 19, count 0 2006.245.07:50:19.07#ibcon#*before return 0, iclass 19, count 0 2006.245.07:50:19.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:50:19.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:50:19.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:50:19.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:50:19.07$4f8m12a/ifd4f 2006.245.07:50:19.07$ifd4f/lo= 2006.245.07:50:19.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:50:19.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:50:19.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:50:19.07$ifd4f/patch= 2006.245.07:50:19.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:50:19.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:50:19.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:50:19.07$4f8m12a/"form=m,16.000,1:2 2006.245.07:50:19.07$4f8m12a/"tpicd 2006.245.07:50:19.07$4f8m12a/echo=off 2006.245.07:50:19.07$4f8m12a/xlog=off 2006.245.07:50:19.07:!2006.245.07:50:50 2006.245.07:50:29.14#trakl#Source acquired 2006.245.07:50:31.14#flagr#flagr/antenna,acquired 2006.245.07:50:50.02:preob 2006.245.07:50:51.14/onsource/TRACKING 2006.245.07:50:51.14:!2006.245.07:51:00 2006.245.07:51:00.02:data_valid=on 2006.245.07:51:00.02:midob 2006.245.07:51:01.14/onsource/TRACKING 2006.245.07:51:01.14/wx/27.35,1004.5,69 2006.245.07:51:01.26/cable/+6.4130E-03 2006.245.07:51:02.35/va/01,08,usb,yes,35,36 2006.245.07:51:02.35/va/02,07,usb,yes,34,36 2006.245.07:51:02.35/va/03,06,usb,yes,36,37 2006.245.07:51:02.35/va/04,07,usb,yes,35,38 2006.245.07:51:02.35/va/05,07,usb,yes,37,40 2006.245.07:51:02.35/va/06,07,usb,yes,33,33 2006.245.07:51:02.35/va/07,07,usb,yes,32,32 2006.245.07:51:02.35/va/08,08,usb,yes,28,28 2006.245.07:51:02.58/valo/01,532.99,yes,locked 2006.245.07:51:02.58/valo/02,572.99,yes,locked 2006.245.07:51:02.58/valo/03,672.99,yes,locked 2006.245.07:51:02.58/valo/04,832.99,yes,locked 2006.245.07:51:02.58/valo/05,652.99,yes,locked 2006.245.07:51:02.58/valo/06,772.99,yes,locked 2006.245.07:51:02.58/valo/07,832.99,yes,locked 2006.245.07:51:02.58/valo/08,852.99,yes,locked 2006.245.07:51:03.67/vb/01,04,usb,yes,33,31 2006.245.07:51:03.67/vb/02,04,usb,yes,35,36 2006.245.07:51:03.67/vb/03,04,usb,yes,31,35 2006.245.07:51:03.67/vb/04,04,usb,yes,32,32 2006.245.07:51:03.67/vb/05,03,usb,yes,37,42 2006.245.07:51:03.67/vb/06,03,usb,yes,38,42 2006.245.07:51:03.67/vb/07,04,usb,yes,33,33 2006.245.07:51:03.67/vb/08,03,usb,yes,38,42 2006.245.07:51:03.90/vblo/01,632.99,yes,locked 2006.245.07:51:03.90/vblo/02,640.99,yes,locked 2006.245.07:51:03.90/vblo/03,656.99,yes,locked 2006.245.07:51:03.90/vblo/04,712.99,yes,locked 2006.245.07:51:03.90/vblo/05,744.99,yes,locked 2006.245.07:51:03.90/vblo/06,752.99,yes,locked 2006.245.07:51:03.90/vblo/07,734.99,yes,locked 2006.245.07:51:03.90/vblo/08,744.99,yes,locked 2006.245.07:51:04.04/vabw/8 2006.245.07:51:04.21/vbbw/8 2006.245.07:51:04.32/xfe/off,on,13.5 2006.245.07:51:04.69/ifatt/23,28,28,28 2006.245.07:51:05.08/fmout-gps/S +4.40E-07 2006.245.07:51:05.12:!2006.245.07:52:00 2006.245.07:52:00.02:data_valid=off 2006.245.07:52:00.02:postob 2006.245.07:52:00.15/cable/+6.4115E-03 2006.245.07:52:00.15/wx/27.33,1004.5,69 2006.245.07:52:01.07/fmout-gps/S +4.40E-07 2006.245.07:52:01.08:scan_name=245-0752,k06245,60 2006.245.07:52:01.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.245.07:52:01.15#flagr#flagr/antenna,new-source 2006.245.07:52:02.15:checkk5 2006.245.07:52:02.60/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:52:03.07/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:52:03.77/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:52:04.42/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:52:05.00/chk_obsdata//k5ts1/T2450751??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.07:52:05.79/chk_obsdata//k5ts2/T2450751??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.07:52:06.24/chk_obsdata//k5ts3/T2450751??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.07:52:06.66/chk_obsdata//k5ts4/T2450751??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.07:52:07.57/k5log//k5ts1_log_newline 2006.245.07:52:08.38/k5log//k5ts2_log_newline 2006.245.07:52:09.30/k5log//k5ts3_log_newline 2006.245.07:52:10.31/k5log//k5ts4_log_newline 2006.245.07:52:10.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:52:10.34:4f8m12a=1 2006.245.07:52:10.34$4f8m12a/echo=on 2006.245.07:52:10.34$4f8m12a/pcalon 2006.245.07:52:10.34$pcalon/"no phase cal control is implemented here 2006.245.07:52:10.34$4f8m12a/"tpicd=stop 2006.245.07:52:10.34$4f8m12a/vc4f8 2006.245.07:52:10.34$vc4f8/valo=1,532.99 2006.245.07:52:10.34#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:52:10.34#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:52:10.34#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:10.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:10.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:10.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:10.34#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:52:10.34#ibcon#first serial, iclass 30, count 0 2006.245.07:52:10.34#ibcon#enter sib2, iclass 30, count 0 2006.245.07:52:10.34#ibcon#flushed, iclass 30, count 0 2006.245.07:52:10.34#ibcon#about to write, iclass 30, count 0 2006.245.07:52:10.34#ibcon#wrote, iclass 30, count 0 2006.245.07:52:10.34#ibcon#about to read 3, iclass 30, count 0 2006.245.07:52:10.38#ibcon#read 3, iclass 30, count 0 2006.245.07:52:10.38#ibcon#about to read 4, iclass 30, count 0 2006.245.07:52:10.38#ibcon#read 4, iclass 30, count 0 2006.245.07:52:10.38#ibcon#about to read 5, iclass 30, count 0 2006.245.07:52:10.38#ibcon#read 5, iclass 30, count 0 2006.245.07:52:10.38#ibcon#about to read 6, iclass 30, count 0 2006.245.07:52:10.38#ibcon#read 6, iclass 30, count 0 2006.245.07:52:10.38#ibcon#end of sib2, iclass 30, count 0 2006.245.07:52:10.38#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:52:10.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:52:10.38#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:52:10.38#ibcon#*before write, iclass 30, count 0 2006.245.07:52:10.38#ibcon#enter sib2, iclass 30, count 0 2006.245.07:52:10.38#ibcon#flushed, iclass 30, count 0 2006.245.07:52:10.38#ibcon#about to write, iclass 30, count 0 2006.245.07:52:10.38#ibcon#wrote, iclass 30, count 0 2006.245.07:52:10.38#ibcon#about to read 3, iclass 30, count 0 2006.245.07:52:10.42#ibcon#read 3, iclass 30, count 0 2006.245.07:52:10.42#ibcon#about to read 4, iclass 30, count 0 2006.245.07:52:10.42#ibcon#read 4, iclass 30, count 0 2006.245.07:52:10.42#ibcon#about to read 5, iclass 30, count 0 2006.245.07:52:10.42#ibcon#read 5, iclass 30, count 0 2006.245.07:52:10.42#ibcon#about to read 6, iclass 30, count 0 2006.245.07:52:10.42#ibcon#read 6, iclass 30, count 0 2006.245.07:52:10.42#ibcon#end of sib2, iclass 30, count 0 2006.245.07:52:10.42#ibcon#*after write, iclass 30, count 0 2006.245.07:52:10.42#ibcon#*before return 0, iclass 30, count 0 2006.245.07:52:10.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:10.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:10.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:52:10.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:52:10.43$vc4f8/va=1,8 2006.245.07:52:10.43#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.07:52:10.43#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.07:52:10.43#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:10.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:10.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:10.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:10.43#ibcon#enter wrdev, iclass 32, count 2 2006.245.07:52:10.43#ibcon#first serial, iclass 32, count 2 2006.245.07:52:10.43#ibcon#enter sib2, iclass 32, count 2 2006.245.07:52:10.43#ibcon#flushed, iclass 32, count 2 2006.245.07:52:10.43#ibcon#about to write, iclass 32, count 2 2006.245.07:52:10.43#ibcon#wrote, iclass 32, count 2 2006.245.07:52:10.43#ibcon#about to read 3, iclass 32, count 2 2006.245.07:52:10.45#ibcon#read 3, iclass 32, count 2 2006.245.07:52:10.45#ibcon#about to read 4, iclass 32, count 2 2006.245.07:52:10.45#ibcon#read 4, iclass 32, count 2 2006.245.07:52:10.45#ibcon#about to read 5, iclass 32, count 2 2006.245.07:52:10.45#ibcon#read 5, iclass 32, count 2 2006.245.07:52:10.45#ibcon#about to read 6, iclass 32, count 2 2006.245.07:52:10.45#ibcon#read 6, iclass 32, count 2 2006.245.07:52:10.45#ibcon#end of sib2, iclass 32, count 2 2006.245.07:52:10.45#ibcon#*mode == 0, iclass 32, count 2 2006.245.07:52:10.45#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.07:52:10.45#ibcon#[25=AT01-08\r\n] 2006.245.07:52:10.45#ibcon#*before write, iclass 32, count 2 2006.245.07:52:10.45#ibcon#enter sib2, iclass 32, count 2 2006.245.07:52:10.45#ibcon#flushed, iclass 32, count 2 2006.245.07:52:10.45#ibcon#about to write, iclass 32, count 2 2006.245.07:52:10.45#ibcon#wrote, iclass 32, count 2 2006.245.07:52:10.45#ibcon#about to read 3, iclass 32, count 2 2006.245.07:52:10.48#ibcon#read 3, iclass 32, count 2 2006.245.07:52:10.48#ibcon#about to read 4, iclass 32, count 2 2006.245.07:52:10.48#ibcon#read 4, iclass 32, count 2 2006.245.07:52:10.48#ibcon#about to read 5, iclass 32, count 2 2006.245.07:52:10.48#ibcon#read 5, iclass 32, count 2 2006.245.07:52:10.48#ibcon#about to read 6, iclass 32, count 2 2006.245.07:52:10.48#ibcon#read 6, iclass 32, count 2 2006.245.07:52:10.48#ibcon#end of sib2, iclass 32, count 2 2006.245.07:52:10.48#ibcon#*after write, iclass 32, count 2 2006.245.07:52:10.48#ibcon#*before return 0, iclass 32, count 2 2006.245.07:52:10.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:10.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:10.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.07:52:10.48#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:10.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:10.59#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:10.59#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:10.59#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:52:10.59#ibcon#first serial, iclass 32, count 0 2006.245.07:52:10.59#ibcon#enter sib2, iclass 32, count 0 2006.245.07:52:10.59#ibcon#flushed, iclass 32, count 0 2006.245.07:52:10.59#ibcon#about to write, iclass 32, count 0 2006.245.07:52:10.59#ibcon#wrote, iclass 32, count 0 2006.245.07:52:10.59#ibcon#about to read 3, iclass 32, count 0 2006.245.07:52:10.61#ibcon#read 3, iclass 32, count 0 2006.245.07:52:10.61#ibcon#about to read 4, iclass 32, count 0 2006.245.07:52:10.61#ibcon#read 4, iclass 32, count 0 2006.245.07:52:10.61#ibcon#about to read 5, iclass 32, count 0 2006.245.07:52:10.61#ibcon#read 5, iclass 32, count 0 2006.245.07:52:10.61#ibcon#about to read 6, iclass 32, count 0 2006.245.07:52:10.61#ibcon#read 6, iclass 32, count 0 2006.245.07:52:10.61#ibcon#end of sib2, iclass 32, count 0 2006.245.07:52:10.61#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:52:10.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:52:10.61#ibcon#[25=USB\r\n] 2006.245.07:52:10.61#ibcon#*before write, iclass 32, count 0 2006.245.07:52:10.61#ibcon#enter sib2, iclass 32, count 0 2006.245.07:52:10.61#ibcon#flushed, iclass 32, count 0 2006.245.07:52:10.61#ibcon#about to write, iclass 32, count 0 2006.245.07:52:10.61#ibcon#wrote, iclass 32, count 0 2006.245.07:52:10.61#ibcon#about to read 3, iclass 32, count 0 2006.245.07:52:10.64#ibcon#read 3, iclass 32, count 0 2006.245.07:52:10.64#ibcon#about to read 4, iclass 32, count 0 2006.245.07:52:10.64#ibcon#read 4, iclass 32, count 0 2006.245.07:52:10.64#ibcon#about to read 5, iclass 32, count 0 2006.245.07:52:10.64#ibcon#read 5, iclass 32, count 0 2006.245.07:52:10.64#ibcon#about to read 6, iclass 32, count 0 2006.245.07:52:10.64#ibcon#read 6, iclass 32, count 0 2006.245.07:52:10.64#ibcon#end of sib2, iclass 32, count 0 2006.245.07:52:10.64#ibcon#*after write, iclass 32, count 0 2006.245.07:52:10.64#ibcon#*before return 0, iclass 32, count 0 2006.245.07:52:10.64#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:10.64#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:10.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:52:10.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:52:10.65$vc4f8/valo=2,572.99 2006.245.07:52:10.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:52:10.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:52:10.65#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:10.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:10.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:10.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:10.65#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:52:10.65#ibcon#first serial, iclass 34, count 0 2006.245.07:52:10.65#ibcon#enter sib2, iclass 34, count 0 2006.245.07:52:10.65#ibcon#flushed, iclass 34, count 0 2006.245.07:52:10.65#ibcon#about to write, iclass 34, count 0 2006.245.07:52:10.65#ibcon#wrote, iclass 34, count 0 2006.245.07:52:10.65#ibcon#about to read 3, iclass 34, count 0 2006.245.07:52:10.67#ibcon#read 3, iclass 34, count 0 2006.245.07:52:10.67#ibcon#about to read 4, iclass 34, count 0 2006.245.07:52:10.67#ibcon#read 4, iclass 34, count 0 2006.245.07:52:10.67#ibcon#about to read 5, iclass 34, count 0 2006.245.07:52:10.67#ibcon#read 5, iclass 34, count 0 2006.245.07:52:10.67#ibcon#about to read 6, iclass 34, count 0 2006.245.07:52:10.67#ibcon#read 6, iclass 34, count 0 2006.245.07:52:10.67#ibcon#end of sib2, iclass 34, count 0 2006.245.07:52:10.67#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:52:10.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:52:10.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:52:10.67#ibcon#*before write, iclass 34, count 0 2006.245.07:52:10.67#ibcon#enter sib2, iclass 34, count 0 2006.245.07:52:10.67#ibcon#flushed, iclass 34, count 0 2006.245.07:52:10.67#ibcon#about to write, iclass 34, count 0 2006.245.07:52:10.67#ibcon#wrote, iclass 34, count 0 2006.245.07:52:10.67#ibcon#about to read 3, iclass 34, count 0 2006.245.07:52:10.71#ibcon#read 3, iclass 34, count 0 2006.245.07:52:10.71#ibcon#about to read 4, iclass 34, count 0 2006.245.07:52:10.71#ibcon#read 4, iclass 34, count 0 2006.245.07:52:10.71#ibcon#about to read 5, iclass 34, count 0 2006.245.07:52:10.71#ibcon#read 5, iclass 34, count 0 2006.245.07:52:10.71#ibcon#about to read 6, iclass 34, count 0 2006.245.07:52:10.71#ibcon#read 6, iclass 34, count 0 2006.245.07:52:10.71#ibcon#end of sib2, iclass 34, count 0 2006.245.07:52:10.71#ibcon#*after write, iclass 34, count 0 2006.245.07:52:10.71#ibcon#*before return 0, iclass 34, count 0 2006.245.07:52:10.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:10.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:10.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:52:10.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:52:10.72$vc4f8/va=2,7 2006.245.07:52:10.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:52:10.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:52:10.72#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:10.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:10.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:10.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:10.75#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:52:10.75#ibcon#first serial, iclass 36, count 2 2006.245.07:52:10.75#ibcon#enter sib2, iclass 36, count 2 2006.245.07:52:10.75#ibcon#flushed, iclass 36, count 2 2006.245.07:52:10.75#ibcon#about to write, iclass 36, count 2 2006.245.07:52:10.75#ibcon#wrote, iclass 36, count 2 2006.245.07:52:10.75#ibcon#about to read 3, iclass 36, count 2 2006.245.07:52:10.78#ibcon#read 3, iclass 36, count 2 2006.245.07:52:10.78#ibcon#about to read 4, iclass 36, count 2 2006.245.07:52:10.78#ibcon#read 4, iclass 36, count 2 2006.245.07:52:10.78#ibcon#about to read 5, iclass 36, count 2 2006.245.07:52:10.78#ibcon#read 5, iclass 36, count 2 2006.245.07:52:10.78#ibcon#about to read 6, iclass 36, count 2 2006.245.07:52:10.78#ibcon#read 6, iclass 36, count 2 2006.245.07:52:10.78#ibcon#end of sib2, iclass 36, count 2 2006.245.07:52:10.78#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:52:10.78#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:52:10.78#ibcon#[25=AT02-07\r\n] 2006.245.07:52:10.78#ibcon#*before write, iclass 36, count 2 2006.245.07:52:10.78#ibcon#enter sib2, iclass 36, count 2 2006.245.07:52:10.78#ibcon#flushed, iclass 36, count 2 2006.245.07:52:10.78#ibcon#about to write, iclass 36, count 2 2006.245.07:52:10.78#ibcon#wrote, iclass 36, count 2 2006.245.07:52:10.78#ibcon#about to read 3, iclass 36, count 2 2006.245.07:52:10.81#ibcon#read 3, iclass 36, count 2 2006.245.07:52:10.81#ibcon#about to read 4, iclass 36, count 2 2006.245.07:52:10.81#ibcon#read 4, iclass 36, count 2 2006.245.07:52:10.81#ibcon#about to read 5, iclass 36, count 2 2006.245.07:52:10.81#ibcon#read 5, iclass 36, count 2 2006.245.07:52:10.81#ibcon#about to read 6, iclass 36, count 2 2006.245.07:52:10.81#ibcon#read 6, iclass 36, count 2 2006.245.07:52:10.81#ibcon#end of sib2, iclass 36, count 2 2006.245.07:52:10.81#ibcon#*after write, iclass 36, count 2 2006.245.07:52:10.81#ibcon#*before return 0, iclass 36, count 2 2006.245.07:52:10.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:10.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:10.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:52:10.81#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:10.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:10.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:10.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:10.93#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:52:10.93#ibcon#first serial, iclass 36, count 0 2006.245.07:52:10.93#ibcon#enter sib2, iclass 36, count 0 2006.245.07:52:10.93#ibcon#flushed, iclass 36, count 0 2006.245.07:52:10.93#ibcon#about to write, iclass 36, count 0 2006.245.07:52:10.93#ibcon#wrote, iclass 36, count 0 2006.245.07:52:10.93#ibcon#about to read 3, iclass 36, count 0 2006.245.07:52:10.95#ibcon#read 3, iclass 36, count 0 2006.245.07:52:10.95#ibcon#about to read 4, iclass 36, count 0 2006.245.07:52:10.95#ibcon#read 4, iclass 36, count 0 2006.245.07:52:10.95#ibcon#about to read 5, iclass 36, count 0 2006.245.07:52:10.95#ibcon#read 5, iclass 36, count 0 2006.245.07:52:10.95#ibcon#about to read 6, iclass 36, count 0 2006.245.07:52:10.95#ibcon#read 6, iclass 36, count 0 2006.245.07:52:10.95#ibcon#end of sib2, iclass 36, count 0 2006.245.07:52:10.95#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:52:10.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:52:10.95#ibcon#[25=USB\r\n] 2006.245.07:52:10.95#ibcon#*before write, iclass 36, count 0 2006.245.07:52:10.95#ibcon#enter sib2, iclass 36, count 0 2006.245.07:52:10.95#ibcon#flushed, iclass 36, count 0 2006.245.07:52:10.95#ibcon#about to write, iclass 36, count 0 2006.245.07:52:10.95#ibcon#wrote, iclass 36, count 0 2006.245.07:52:10.95#ibcon#about to read 3, iclass 36, count 0 2006.245.07:52:10.98#ibcon#read 3, iclass 36, count 0 2006.245.07:52:10.98#ibcon#about to read 4, iclass 36, count 0 2006.245.07:52:10.98#ibcon#read 4, iclass 36, count 0 2006.245.07:52:10.98#ibcon#about to read 5, iclass 36, count 0 2006.245.07:52:10.98#ibcon#read 5, iclass 36, count 0 2006.245.07:52:10.98#ibcon#about to read 6, iclass 36, count 0 2006.245.07:52:10.98#ibcon#read 6, iclass 36, count 0 2006.245.07:52:10.98#ibcon#end of sib2, iclass 36, count 0 2006.245.07:52:10.98#ibcon#*after write, iclass 36, count 0 2006.245.07:52:10.98#ibcon#*before return 0, iclass 36, count 0 2006.245.07:52:10.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:10.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:10.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:52:10.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:52:10.99$vc4f8/valo=3,672.99 2006.245.07:52:10.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:52:10.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:52:10.99#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:10.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:10.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:10.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:10.99#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:52:10.99#ibcon#first serial, iclass 38, count 0 2006.245.07:52:10.99#ibcon#enter sib2, iclass 38, count 0 2006.245.07:52:10.99#ibcon#flushed, iclass 38, count 0 2006.245.07:52:10.99#ibcon#about to write, iclass 38, count 0 2006.245.07:52:10.99#ibcon#wrote, iclass 38, count 0 2006.245.07:52:10.99#ibcon#about to read 3, iclass 38, count 0 2006.245.07:52:11.01#ibcon#read 3, iclass 38, count 0 2006.245.07:52:11.01#ibcon#about to read 4, iclass 38, count 0 2006.245.07:52:11.01#ibcon#read 4, iclass 38, count 0 2006.245.07:52:11.01#ibcon#about to read 5, iclass 38, count 0 2006.245.07:52:11.01#ibcon#read 5, iclass 38, count 0 2006.245.07:52:11.01#ibcon#about to read 6, iclass 38, count 0 2006.245.07:52:11.01#ibcon#read 6, iclass 38, count 0 2006.245.07:52:11.01#ibcon#end of sib2, iclass 38, count 0 2006.245.07:52:11.01#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:52:11.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:52:11.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:52:11.01#ibcon#*before write, iclass 38, count 0 2006.245.07:52:11.01#ibcon#enter sib2, iclass 38, count 0 2006.245.07:52:11.01#ibcon#flushed, iclass 38, count 0 2006.245.07:52:11.01#ibcon#about to write, iclass 38, count 0 2006.245.07:52:11.01#ibcon#wrote, iclass 38, count 0 2006.245.07:52:11.01#ibcon#about to read 3, iclass 38, count 0 2006.245.07:52:11.05#ibcon#read 3, iclass 38, count 0 2006.245.07:52:11.05#ibcon#about to read 4, iclass 38, count 0 2006.245.07:52:11.05#ibcon#read 4, iclass 38, count 0 2006.245.07:52:11.05#ibcon#about to read 5, iclass 38, count 0 2006.245.07:52:11.05#ibcon#read 5, iclass 38, count 0 2006.245.07:52:11.05#ibcon#about to read 6, iclass 38, count 0 2006.245.07:52:11.05#ibcon#read 6, iclass 38, count 0 2006.245.07:52:11.05#ibcon#end of sib2, iclass 38, count 0 2006.245.07:52:11.05#ibcon#*after write, iclass 38, count 0 2006.245.07:52:11.05#ibcon#*before return 0, iclass 38, count 0 2006.245.07:52:11.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:11.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:11.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:52:11.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:52:11.06$vc4f8/va=3,6 2006.245.07:52:11.06#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:52:11.06#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:52:11.06#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:11.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:11.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:11.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:11.09#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:52:11.09#ibcon#first serial, iclass 40, count 2 2006.245.07:52:11.09#ibcon#enter sib2, iclass 40, count 2 2006.245.07:52:11.09#ibcon#flushed, iclass 40, count 2 2006.245.07:52:11.09#ibcon#about to write, iclass 40, count 2 2006.245.07:52:11.09#ibcon#wrote, iclass 40, count 2 2006.245.07:52:11.09#ibcon#about to read 3, iclass 40, count 2 2006.245.07:52:11.12#ibcon#read 3, iclass 40, count 2 2006.245.07:52:11.12#ibcon#about to read 4, iclass 40, count 2 2006.245.07:52:11.12#ibcon#read 4, iclass 40, count 2 2006.245.07:52:11.12#ibcon#about to read 5, iclass 40, count 2 2006.245.07:52:11.12#ibcon#read 5, iclass 40, count 2 2006.245.07:52:11.12#ibcon#about to read 6, iclass 40, count 2 2006.245.07:52:11.12#ibcon#read 6, iclass 40, count 2 2006.245.07:52:11.12#ibcon#end of sib2, iclass 40, count 2 2006.245.07:52:11.12#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:52:11.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:52:11.12#ibcon#[25=AT03-06\r\n] 2006.245.07:52:11.12#ibcon#*before write, iclass 40, count 2 2006.245.07:52:11.12#ibcon#enter sib2, iclass 40, count 2 2006.245.07:52:11.12#ibcon#flushed, iclass 40, count 2 2006.245.07:52:11.12#ibcon#about to write, iclass 40, count 2 2006.245.07:52:11.12#ibcon#wrote, iclass 40, count 2 2006.245.07:52:11.12#ibcon#about to read 3, iclass 40, count 2 2006.245.07:52:11.15#ibcon#read 3, iclass 40, count 2 2006.245.07:52:11.15#ibcon#about to read 4, iclass 40, count 2 2006.245.07:52:11.15#ibcon#read 4, iclass 40, count 2 2006.245.07:52:11.15#ibcon#about to read 5, iclass 40, count 2 2006.245.07:52:11.15#ibcon#read 5, iclass 40, count 2 2006.245.07:52:11.15#ibcon#about to read 6, iclass 40, count 2 2006.245.07:52:11.15#ibcon#read 6, iclass 40, count 2 2006.245.07:52:11.15#ibcon#end of sib2, iclass 40, count 2 2006.245.07:52:11.15#ibcon#*after write, iclass 40, count 2 2006.245.07:52:11.15#ibcon#*before return 0, iclass 40, count 2 2006.245.07:52:11.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:11.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:11.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:52:11.15#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:11.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:11.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:11.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:11.27#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:52:11.27#ibcon#first serial, iclass 40, count 0 2006.245.07:52:11.27#ibcon#enter sib2, iclass 40, count 0 2006.245.07:52:11.27#ibcon#flushed, iclass 40, count 0 2006.245.07:52:11.27#ibcon#about to write, iclass 40, count 0 2006.245.07:52:11.27#ibcon#wrote, iclass 40, count 0 2006.245.07:52:11.27#ibcon#about to read 3, iclass 40, count 0 2006.245.07:52:11.29#ibcon#read 3, iclass 40, count 0 2006.245.07:52:11.29#ibcon#about to read 4, iclass 40, count 0 2006.245.07:52:11.29#ibcon#read 4, iclass 40, count 0 2006.245.07:52:11.29#ibcon#about to read 5, iclass 40, count 0 2006.245.07:52:11.29#ibcon#read 5, iclass 40, count 0 2006.245.07:52:11.29#ibcon#about to read 6, iclass 40, count 0 2006.245.07:52:11.29#ibcon#read 6, iclass 40, count 0 2006.245.07:52:11.29#ibcon#end of sib2, iclass 40, count 0 2006.245.07:52:11.29#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:52:11.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:52:11.29#ibcon#[25=USB\r\n] 2006.245.07:52:11.29#ibcon#*before write, iclass 40, count 0 2006.245.07:52:11.29#ibcon#enter sib2, iclass 40, count 0 2006.245.07:52:11.29#ibcon#flushed, iclass 40, count 0 2006.245.07:52:11.29#ibcon#about to write, iclass 40, count 0 2006.245.07:52:11.29#ibcon#wrote, iclass 40, count 0 2006.245.07:52:11.29#ibcon#about to read 3, iclass 40, count 0 2006.245.07:52:11.32#ibcon#read 3, iclass 40, count 0 2006.245.07:52:11.32#ibcon#about to read 4, iclass 40, count 0 2006.245.07:52:11.32#ibcon#read 4, iclass 40, count 0 2006.245.07:52:11.32#ibcon#about to read 5, iclass 40, count 0 2006.245.07:52:11.32#ibcon#read 5, iclass 40, count 0 2006.245.07:52:11.32#ibcon#about to read 6, iclass 40, count 0 2006.245.07:52:11.32#ibcon#read 6, iclass 40, count 0 2006.245.07:52:11.32#ibcon#end of sib2, iclass 40, count 0 2006.245.07:52:11.32#ibcon#*after write, iclass 40, count 0 2006.245.07:52:11.32#ibcon#*before return 0, iclass 40, count 0 2006.245.07:52:11.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:11.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:11.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:52:11.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:52:11.33$vc4f8/valo=4,832.99 2006.245.07:52:11.33#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:52:11.33#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:52:11.33#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:11.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:11.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:11.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:11.33#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:52:11.33#ibcon#first serial, iclass 4, count 0 2006.245.07:52:11.33#ibcon#enter sib2, iclass 4, count 0 2006.245.07:52:11.33#ibcon#flushed, iclass 4, count 0 2006.245.07:52:11.33#ibcon#about to write, iclass 4, count 0 2006.245.07:52:11.33#ibcon#wrote, iclass 4, count 0 2006.245.07:52:11.33#ibcon#about to read 3, iclass 4, count 0 2006.245.07:52:11.34#ibcon#read 3, iclass 4, count 0 2006.245.07:52:11.34#ibcon#about to read 4, iclass 4, count 0 2006.245.07:52:11.34#ibcon#read 4, iclass 4, count 0 2006.245.07:52:11.34#ibcon#about to read 5, iclass 4, count 0 2006.245.07:52:11.34#ibcon#read 5, iclass 4, count 0 2006.245.07:52:11.34#ibcon#about to read 6, iclass 4, count 0 2006.245.07:52:11.34#ibcon#read 6, iclass 4, count 0 2006.245.07:52:11.34#ibcon#end of sib2, iclass 4, count 0 2006.245.07:52:11.34#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:52:11.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:52:11.34#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:52:11.34#ibcon#*before write, iclass 4, count 0 2006.245.07:52:11.34#ibcon#enter sib2, iclass 4, count 0 2006.245.07:52:11.34#ibcon#flushed, iclass 4, count 0 2006.245.07:52:11.34#ibcon#about to write, iclass 4, count 0 2006.245.07:52:11.34#ibcon#wrote, iclass 4, count 0 2006.245.07:52:11.34#ibcon#about to read 3, iclass 4, count 0 2006.245.07:52:11.38#ibcon#read 3, iclass 4, count 0 2006.245.07:52:11.38#ibcon#about to read 4, iclass 4, count 0 2006.245.07:52:11.38#ibcon#read 4, iclass 4, count 0 2006.245.07:52:11.38#ibcon#about to read 5, iclass 4, count 0 2006.245.07:52:11.38#ibcon#read 5, iclass 4, count 0 2006.245.07:52:11.38#ibcon#about to read 6, iclass 4, count 0 2006.245.07:52:11.38#ibcon#read 6, iclass 4, count 0 2006.245.07:52:11.38#ibcon#end of sib2, iclass 4, count 0 2006.245.07:52:11.38#ibcon#*after write, iclass 4, count 0 2006.245.07:52:11.38#ibcon#*before return 0, iclass 4, count 0 2006.245.07:52:11.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:11.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:11.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:52:11.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:52:11.39$vc4f8/va=4,7 2006.245.07:52:11.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:52:11.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:52:11.39#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:11.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:11.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:11.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:11.43#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:52:11.43#ibcon#first serial, iclass 6, count 2 2006.245.07:52:11.43#ibcon#enter sib2, iclass 6, count 2 2006.245.07:52:11.43#ibcon#flushed, iclass 6, count 2 2006.245.07:52:11.43#ibcon#about to write, iclass 6, count 2 2006.245.07:52:11.43#ibcon#wrote, iclass 6, count 2 2006.245.07:52:11.43#ibcon#about to read 3, iclass 6, count 2 2006.245.07:52:11.45#ibcon#read 3, iclass 6, count 2 2006.245.07:52:11.45#ibcon#about to read 4, iclass 6, count 2 2006.245.07:52:11.45#ibcon#read 4, iclass 6, count 2 2006.245.07:52:11.45#ibcon#about to read 5, iclass 6, count 2 2006.245.07:52:11.45#ibcon#read 5, iclass 6, count 2 2006.245.07:52:11.45#ibcon#about to read 6, iclass 6, count 2 2006.245.07:52:11.45#ibcon#read 6, iclass 6, count 2 2006.245.07:52:11.45#ibcon#end of sib2, iclass 6, count 2 2006.245.07:52:11.45#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:52:11.45#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:52:11.45#ibcon#[25=AT04-07\r\n] 2006.245.07:52:11.45#ibcon#*before write, iclass 6, count 2 2006.245.07:52:11.45#ibcon#enter sib2, iclass 6, count 2 2006.245.07:52:11.45#ibcon#flushed, iclass 6, count 2 2006.245.07:52:11.45#ibcon#about to write, iclass 6, count 2 2006.245.07:52:11.45#ibcon#wrote, iclass 6, count 2 2006.245.07:52:11.45#ibcon#about to read 3, iclass 6, count 2 2006.245.07:52:11.48#ibcon#read 3, iclass 6, count 2 2006.245.07:52:11.48#ibcon#about to read 4, iclass 6, count 2 2006.245.07:52:11.48#ibcon#read 4, iclass 6, count 2 2006.245.07:52:11.48#ibcon#about to read 5, iclass 6, count 2 2006.245.07:52:11.48#ibcon#read 5, iclass 6, count 2 2006.245.07:52:11.48#ibcon#about to read 6, iclass 6, count 2 2006.245.07:52:11.48#ibcon#read 6, iclass 6, count 2 2006.245.07:52:11.48#ibcon#end of sib2, iclass 6, count 2 2006.245.07:52:11.48#ibcon#*after write, iclass 6, count 2 2006.245.07:52:11.48#ibcon#*before return 0, iclass 6, count 2 2006.245.07:52:11.48#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:11.48#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:11.48#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:52:11.48#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:11.48#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:11.60#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:11.60#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:11.60#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:52:11.60#ibcon#first serial, iclass 6, count 0 2006.245.07:52:11.60#ibcon#enter sib2, iclass 6, count 0 2006.245.07:52:11.60#ibcon#flushed, iclass 6, count 0 2006.245.07:52:11.60#ibcon#about to write, iclass 6, count 0 2006.245.07:52:11.60#ibcon#wrote, iclass 6, count 0 2006.245.07:52:11.60#ibcon#about to read 3, iclass 6, count 0 2006.245.07:52:11.62#ibcon#read 3, iclass 6, count 0 2006.245.07:52:11.62#ibcon#about to read 4, iclass 6, count 0 2006.245.07:52:11.62#ibcon#read 4, iclass 6, count 0 2006.245.07:52:11.62#ibcon#about to read 5, iclass 6, count 0 2006.245.07:52:11.62#ibcon#read 5, iclass 6, count 0 2006.245.07:52:11.62#ibcon#about to read 6, iclass 6, count 0 2006.245.07:52:11.62#ibcon#read 6, iclass 6, count 0 2006.245.07:52:11.62#ibcon#end of sib2, iclass 6, count 0 2006.245.07:52:11.62#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:52:11.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:52:11.62#ibcon#[25=USB\r\n] 2006.245.07:52:11.62#ibcon#*before write, iclass 6, count 0 2006.245.07:52:11.62#ibcon#enter sib2, iclass 6, count 0 2006.245.07:52:11.62#ibcon#flushed, iclass 6, count 0 2006.245.07:52:11.62#ibcon#about to write, iclass 6, count 0 2006.245.07:52:11.62#ibcon#wrote, iclass 6, count 0 2006.245.07:52:11.62#ibcon#about to read 3, iclass 6, count 0 2006.245.07:52:11.65#ibcon#read 3, iclass 6, count 0 2006.245.07:52:11.65#ibcon#about to read 4, iclass 6, count 0 2006.245.07:52:11.65#ibcon#read 4, iclass 6, count 0 2006.245.07:52:11.65#ibcon#about to read 5, iclass 6, count 0 2006.245.07:52:11.65#ibcon#read 5, iclass 6, count 0 2006.245.07:52:11.65#ibcon#about to read 6, iclass 6, count 0 2006.245.07:52:11.65#ibcon#read 6, iclass 6, count 0 2006.245.07:52:11.65#ibcon#end of sib2, iclass 6, count 0 2006.245.07:52:11.65#ibcon#*after write, iclass 6, count 0 2006.245.07:52:11.65#ibcon#*before return 0, iclass 6, count 0 2006.245.07:52:11.65#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:11.65#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:11.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:52:11.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:52:11.66$vc4f8/valo=5,652.99 2006.245.07:52:11.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:52:11.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:52:11.66#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:11.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:11.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:11.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:11.66#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:52:11.66#ibcon#first serial, iclass 10, count 0 2006.245.07:52:11.66#ibcon#enter sib2, iclass 10, count 0 2006.245.07:52:11.66#ibcon#flushed, iclass 10, count 0 2006.245.07:52:11.66#ibcon#about to write, iclass 10, count 0 2006.245.07:52:11.66#ibcon#wrote, iclass 10, count 0 2006.245.07:52:11.66#ibcon#about to read 3, iclass 10, count 0 2006.245.07:52:11.67#ibcon#read 3, iclass 10, count 0 2006.245.07:52:11.67#ibcon#about to read 4, iclass 10, count 0 2006.245.07:52:11.67#ibcon#read 4, iclass 10, count 0 2006.245.07:52:11.67#ibcon#about to read 5, iclass 10, count 0 2006.245.07:52:11.67#ibcon#read 5, iclass 10, count 0 2006.245.07:52:11.67#ibcon#about to read 6, iclass 10, count 0 2006.245.07:52:11.67#ibcon#read 6, iclass 10, count 0 2006.245.07:52:11.67#ibcon#end of sib2, iclass 10, count 0 2006.245.07:52:11.67#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:52:11.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:52:11.67#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:52:11.67#ibcon#*before write, iclass 10, count 0 2006.245.07:52:11.67#ibcon#enter sib2, iclass 10, count 0 2006.245.07:52:11.67#ibcon#flushed, iclass 10, count 0 2006.245.07:52:11.67#ibcon#about to write, iclass 10, count 0 2006.245.07:52:11.67#ibcon#wrote, iclass 10, count 0 2006.245.07:52:11.67#ibcon#about to read 3, iclass 10, count 0 2006.245.07:52:11.71#ibcon#read 3, iclass 10, count 0 2006.245.07:52:11.71#ibcon#about to read 4, iclass 10, count 0 2006.245.07:52:11.71#ibcon#read 4, iclass 10, count 0 2006.245.07:52:11.71#ibcon#about to read 5, iclass 10, count 0 2006.245.07:52:11.71#ibcon#read 5, iclass 10, count 0 2006.245.07:52:11.71#ibcon#about to read 6, iclass 10, count 0 2006.245.07:52:11.71#ibcon#read 6, iclass 10, count 0 2006.245.07:52:11.71#ibcon#end of sib2, iclass 10, count 0 2006.245.07:52:11.71#ibcon#*after write, iclass 10, count 0 2006.245.07:52:11.71#ibcon#*before return 0, iclass 10, count 0 2006.245.07:52:11.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:11.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:11.71#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:52:11.71#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:52:11.72$vc4f8/va=5,7 2006.245.07:52:11.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:52:11.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:52:11.72#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:11.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:11.76#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:11.76#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:11.76#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:52:11.76#ibcon#first serial, iclass 12, count 2 2006.245.07:52:11.76#ibcon#enter sib2, iclass 12, count 2 2006.245.07:52:11.76#ibcon#flushed, iclass 12, count 2 2006.245.07:52:11.76#ibcon#about to write, iclass 12, count 2 2006.245.07:52:11.76#ibcon#wrote, iclass 12, count 2 2006.245.07:52:11.76#ibcon#about to read 3, iclass 12, count 2 2006.245.07:52:11.78#ibcon#read 3, iclass 12, count 2 2006.245.07:52:11.78#ibcon#about to read 4, iclass 12, count 2 2006.245.07:52:11.78#ibcon#read 4, iclass 12, count 2 2006.245.07:52:11.78#ibcon#about to read 5, iclass 12, count 2 2006.245.07:52:11.78#ibcon#read 5, iclass 12, count 2 2006.245.07:52:11.78#ibcon#about to read 6, iclass 12, count 2 2006.245.07:52:11.78#ibcon#read 6, iclass 12, count 2 2006.245.07:52:11.78#ibcon#end of sib2, iclass 12, count 2 2006.245.07:52:11.78#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:52:11.78#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:52:11.78#ibcon#[25=AT05-07\r\n] 2006.245.07:52:11.78#ibcon#*before write, iclass 12, count 2 2006.245.07:52:11.78#ibcon#enter sib2, iclass 12, count 2 2006.245.07:52:11.78#ibcon#flushed, iclass 12, count 2 2006.245.07:52:11.78#ibcon#about to write, iclass 12, count 2 2006.245.07:52:11.78#ibcon#wrote, iclass 12, count 2 2006.245.07:52:11.78#ibcon#about to read 3, iclass 12, count 2 2006.245.07:52:11.81#ibcon#read 3, iclass 12, count 2 2006.245.07:52:11.81#ibcon#about to read 4, iclass 12, count 2 2006.245.07:52:11.81#ibcon#read 4, iclass 12, count 2 2006.245.07:52:11.81#ibcon#about to read 5, iclass 12, count 2 2006.245.07:52:11.81#ibcon#read 5, iclass 12, count 2 2006.245.07:52:11.81#ibcon#about to read 6, iclass 12, count 2 2006.245.07:52:11.81#ibcon#read 6, iclass 12, count 2 2006.245.07:52:11.81#ibcon#end of sib2, iclass 12, count 2 2006.245.07:52:11.81#ibcon#*after write, iclass 12, count 2 2006.245.07:52:11.81#ibcon#*before return 0, iclass 12, count 2 2006.245.07:52:11.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:11.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:11.81#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:52:11.81#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:11.81#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:11.93#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:11.93#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:11.93#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:52:11.93#ibcon#first serial, iclass 12, count 0 2006.245.07:52:11.93#ibcon#enter sib2, iclass 12, count 0 2006.245.07:52:11.93#ibcon#flushed, iclass 12, count 0 2006.245.07:52:11.93#ibcon#about to write, iclass 12, count 0 2006.245.07:52:11.93#ibcon#wrote, iclass 12, count 0 2006.245.07:52:11.93#ibcon#about to read 3, iclass 12, count 0 2006.245.07:52:11.95#ibcon#read 3, iclass 12, count 0 2006.245.07:52:11.95#ibcon#about to read 4, iclass 12, count 0 2006.245.07:52:11.95#ibcon#read 4, iclass 12, count 0 2006.245.07:52:11.95#ibcon#about to read 5, iclass 12, count 0 2006.245.07:52:11.95#ibcon#read 5, iclass 12, count 0 2006.245.07:52:11.95#ibcon#about to read 6, iclass 12, count 0 2006.245.07:52:11.95#ibcon#read 6, iclass 12, count 0 2006.245.07:52:11.95#ibcon#end of sib2, iclass 12, count 0 2006.245.07:52:11.95#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:52:11.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:52:11.95#ibcon#[25=USB\r\n] 2006.245.07:52:11.95#ibcon#*before write, iclass 12, count 0 2006.245.07:52:11.95#ibcon#enter sib2, iclass 12, count 0 2006.245.07:52:11.95#ibcon#flushed, iclass 12, count 0 2006.245.07:52:11.95#ibcon#about to write, iclass 12, count 0 2006.245.07:52:11.95#ibcon#wrote, iclass 12, count 0 2006.245.07:52:11.95#ibcon#about to read 3, iclass 12, count 0 2006.245.07:52:11.98#ibcon#read 3, iclass 12, count 0 2006.245.07:52:11.98#ibcon#about to read 4, iclass 12, count 0 2006.245.07:52:11.98#ibcon#read 4, iclass 12, count 0 2006.245.07:52:11.98#ibcon#about to read 5, iclass 12, count 0 2006.245.07:52:11.98#ibcon#read 5, iclass 12, count 0 2006.245.07:52:11.98#ibcon#about to read 6, iclass 12, count 0 2006.245.07:52:11.98#ibcon#read 6, iclass 12, count 0 2006.245.07:52:11.98#ibcon#end of sib2, iclass 12, count 0 2006.245.07:52:11.98#ibcon#*after write, iclass 12, count 0 2006.245.07:52:11.98#ibcon#*before return 0, iclass 12, count 0 2006.245.07:52:11.98#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:11.98#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:11.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:52:11.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:52:11.99$vc4f8/valo=6,772.99 2006.245.07:52:11.99#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:52:11.99#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:52:11.99#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:11.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:11.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:11.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:11.99#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:52:11.99#ibcon#first serial, iclass 14, count 0 2006.245.07:52:11.99#ibcon#enter sib2, iclass 14, count 0 2006.245.07:52:11.99#ibcon#flushed, iclass 14, count 0 2006.245.07:52:11.99#ibcon#about to write, iclass 14, count 0 2006.245.07:52:11.99#ibcon#wrote, iclass 14, count 0 2006.245.07:52:11.99#ibcon#about to read 3, iclass 14, count 0 2006.245.07:52:12.01#ibcon#read 3, iclass 14, count 0 2006.245.07:52:12.01#ibcon#about to read 4, iclass 14, count 0 2006.245.07:52:12.01#ibcon#read 4, iclass 14, count 0 2006.245.07:52:12.01#ibcon#about to read 5, iclass 14, count 0 2006.245.07:52:12.01#ibcon#read 5, iclass 14, count 0 2006.245.07:52:12.01#ibcon#about to read 6, iclass 14, count 0 2006.245.07:52:12.01#ibcon#read 6, iclass 14, count 0 2006.245.07:52:12.01#ibcon#end of sib2, iclass 14, count 0 2006.245.07:52:12.01#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:52:12.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:52:12.01#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:52:12.01#ibcon#*before write, iclass 14, count 0 2006.245.07:52:12.01#ibcon#enter sib2, iclass 14, count 0 2006.245.07:52:12.01#ibcon#flushed, iclass 14, count 0 2006.245.07:52:12.01#ibcon#about to write, iclass 14, count 0 2006.245.07:52:12.01#ibcon#wrote, iclass 14, count 0 2006.245.07:52:12.01#ibcon#about to read 3, iclass 14, count 0 2006.245.07:52:12.05#ibcon#read 3, iclass 14, count 0 2006.245.07:52:12.05#ibcon#about to read 4, iclass 14, count 0 2006.245.07:52:12.05#ibcon#read 4, iclass 14, count 0 2006.245.07:52:12.05#ibcon#about to read 5, iclass 14, count 0 2006.245.07:52:12.05#ibcon#read 5, iclass 14, count 0 2006.245.07:52:12.05#ibcon#about to read 6, iclass 14, count 0 2006.245.07:52:12.05#ibcon#read 6, iclass 14, count 0 2006.245.07:52:12.05#ibcon#end of sib2, iclass 14, count 0 2006.245.07:52:12.05#ibcon#*after write, iclass 14, count 0 2006.245.07:52:12.05#ibcon#*before return 0, iclass 14, count 0 2006.245.07:52:12.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:12.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:12.05#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:52:12.05#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:52:12.06$vc4f8/va=6,7 2006.245.07:52:12.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.07:52:12.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.07:52:12.06#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:12.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:52:12.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:52:12.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:52:12.09#ibcon#enter wrdev, iclass 16, count 2 2006.245.07:52:12.09#ibcon#first serial, iclass 16, count 2 2006.245.07:52:12.09#ibcon#enter sib2, iclass 16, count 2 2006.245.07:52:12.09#ibcon#flushed, iclass 16, count 2 2006.245.07:52:12.09#ibcon#about to write, iclass 16, count 2 2006.245.07:52:12.09#ibcon#wrote, iclass 16, count 2 2006.245.07:52:12.09#ibcon#about to read 3, iclass 16, count 2 2006.245.07:52:12.12#ibcon#read 3, iclass 16, count 2 2006.245.07:52:12.12#ibcon#about to read 4, iclass 16, count 2 2006.245.07:52:12.12#ibcon#read 4, iclass 16, count 2 2006.245.07:52:12.12#ibcon#about to read 5, iclass 16, count 2 2006.245.07:52:12.12#ibcon#read 5, iclass 16, count 2 2006.245.07:52:12.12#ibcon#about to read 6, iclass 16, count 2 2006.245.07:52:12.12#ibcon#read 6, iclass 16, count 2 2006.245.07:52:12.12#ibcon#end of sib2, iclass 16, count 2 2006.245.07:52:12.12#ibcon#*mode == 0, iclass 16, count 2 2006.245.07:52:12.12#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.07:52:12.12#ibcon#[25=AT06-07\r\n] 2006.245.07:52:12.12#ibcon#*before write, iclass 16, count 2 2006.245.07:52:12.12#ibcon#enter sib2, iclass 16, count 2 2006.245.07:52:12.12#ibcon#flushed, iclass 16, count 2 2006.245.07:52:12.12#ibcon#about to write, iclass 16, count 2 2006.245.07:52:12.12#ibcon#wrote, iclass 16, count 2 2006.245.07:52:12.12#ibcon#about to read 3, iclass 16, count 2 2006.245.07:52:12.15#ibcon#read 3, iclass 16, count 2 2006.245.07:52:12.15#ibcon#about to read 4, iclass 16, count 2 2006.245.07:52:12.15#ibcon#read 4, iclass 16, count 2 2006.245.07:52:12.15#ibcon#about to read 5, iclass 16, count 2 2006.245.07:52:12.15#ibcon#read 5, iclass 16, count 2 2006.245.07:52:12.15#ibcon#about to read 6, iclass 16, count 2 2006.245.07:52:12.15#ibcon#read 6, iclass 16, count 2 2006.245.07:52:12.15#ibcon#end of sib2, iclass 16, count 2 2006.245.07:52:12.15#ibcon#*after write, iclass 16, count 2 2006.245.07:52:12.15#ibcon#*before return 0, iclass 16, count 2 2006.245.07:52:12.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:52:12.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.07:52:12.15#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.07:52:12.15#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:12.15#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:52:12.27#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:52:12.27#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:52:12.27#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:52:12.27#ibcon#first serial, iclass 16, count 0 2006.245.07:52:12.27#ibcon#enter sib2, iclass 16, count 0 2006.245.07:52:12.27#ibcon#flushed, iclass 16, count 0 2006.245.07:52:12.27#ibcon#about to write, iclass 16, count 0 2006.245.07:52:12.27#ibcon#wrote, iclass 16, count 0 2006.245.07:52:12.27#ibcon#about to read 3, iclass 16, count 0 2006.245.07:52:12.29#ibcon#read 3, iclass 16, count 0 2006.245.07:52:12.29#ibcon#about to read 4, iclass 16, count 0 2006.245.07:52:12.29#ibcon#read 4, iclass 16, count 0 2006.245.07:52:12.29#ibcon#about to read 5, iclass 16, count 0 2006.245.07:52:12.29#ibcon#read 5, iclass 16, count 0 2006.245.07:52:12.29#ibcon#about to read 6, iclass 16, count 0 2006.245.07:52:12.29#ibcon#read 6, iclass 16, count 0 2006.245.07:52:12.29#ibcon#end of sib2, iclass 16, count 0 2006.245.07:52:12.29#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:52:12.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:52:12.29#ibcon#[25=USB\r\n] 2006.245.07:52:12.29#ibcon#*before write, iclass 16, count 0 2006.245.07:52:12.29#ibcon#enter sib2, iclass 16, count 0 2006.245.07:52:12.29#ibcon#flushed, iclass 16, count 0 2006.245.07:52:12.29#ibcon#about to write, iclass 16, count 0 2006.245.07:52:12.29#ibcon#wrote, iclass 16, count 0 2006.245.07:52:12.29#ibcon#about to read 3, iclass 16, count 0 2006.245.07:52:12.32#ibcon#read 3, iclass 16, count 0 2006.245.07:52:12.32#ibcon#about to read 4, iclass 16, count 0 2006.245.07:52:12.32#ibcon#read 4, iclass 16, count 0 2006.245.07:52:12.32#ibcon#about to read 5, iclass 16, count 0 2006.245.07:52:12.32#ibcon#read 5, iclass 16, count 0 2006.245.07:52:12.32#ibcon#about to read 6, iclass 16, count 0 2006.245.07:52:12.32#ibcon#read 6, iclass 16, count 0 2006.245.07:52:12.32#ibcon#end of sib2, iclass 16, count 0 2006.245.07:52:12.32#ibcon#*after write, iclass 16, count 0 2006.245.07:52:12.32#ibcon#*before return 0, iclass 16, count 0 2006.245.07:52:12.32#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:52:12.32#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.07:52:12.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:52:12.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:52:12.33$vc4f8/valo=7,832.99 2006.245.07:52:12.33#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.07:52:12.33#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.07:52:12.33#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:12.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:52:12.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:52:12.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:52:12.33#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:52:12.33#ibcon#first serial, iclass 18, count 0 2006.245.07:52:12.33#ibcon#enter sib2, iclass 18, count 0 2006.245.07:52:12.33#ibcon#flushed, iclass 18, count 0 2006.245.07:52:12.33#ibcon#about to write, iclass 18, count 0 2006.245.07:52:12.33#ibcon#wrote, iclass 18, count 0 2006.245.07:52:12.33#ibcon#about to read 3, iclass 18, count 0 2006.245.07:52:12.34#ibcon#read 3, iclass 18, count 0 2006.245.07:52:12.34#ibcon#about to read 4, iclass 18, count 0 2006.245.07:52:12.34#ibcon#read 4, iclass 18, count 0 2006.245.07:52:12.34#ibcon#about to read 5, iclass 18, count 0 2006.245.07:52:12.34#ibcon#read 5, iclass 18, count 0 2006.245.07:52:12.34#ibcon#about to read 6, iclass 18, count 0 2006.245.07:52:12.34#ibcon#read 6, iclass 18, count 0 2006.245.07:52:12.34#ibcon#end of sib2, iclass 18, count 0 2006.245.07:52:12.34#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:52:12.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:52:12.34#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:52:12.34#ibcon#*before write, iclass 18, count 0 2006.245.07:52:12.34#ibcon#enter sib2, iclass 18, count 0 2006.245.07:52:12.34#ibcon#flushed, iclass 18, count 0 2006.245.07:52:12.34#ibcon#about to write, iclass 18, count 0 2006.245.07:52:12.34#ibcon#wrote, iclass 18, count 0 2006.245.07:52:12.34#ibcon#about to read 3, iclass 18, count 0 2006.245.07:52:12.38#ibcon#read 3, iclass 18, count 0 2006.245.07:52:12.38#ibcon#about to read 4, iclass 18, count 0 2006.245.07:52:12.38#ibcon#read 4, iclass 18, count 0 2006.245.07:52:12.38#ibcon#about to read 5, iclass 18, count 0 2006.245.07:52:12.38#ibcon#read 5, iclass 18, count 0 2006.245.07:52:12.38#ibcon#about to read 6, iclass 18, count 0 2006.245.07:52:12.38#ibcon#read 6, iclass 18, count 0 2006.245.07:52:12.38#ibcon#end of sib2, iclass 18, count 0 2006.245.07:52:12.38#ibcon#*after write, iclass 18, count 0 2006.245.07:52:12.38#ibcon#*before return 0, iclass 18, count 0 2006.245.07:52:12.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:52:12.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.07:52:12.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:52:12.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:52:12.39$vc4f8/va=7,7 2006.245.07:52:12.39#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.07:52:12.39#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.07:52:12.39#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:12.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:52:12.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:52:12.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:52:12.43#ibcon#enter wrdev, iclass 20, count 2 2006.245.07:52:12.43#ibcon#first serial, iclass 20, count 2 2006.245.07:52:12.43#ibcon#enter sib2, iclass 20, count 2 2006.245.07:52:12.43#ibcon#flushed, iclass 20, count 2 2006.245.07:52:12.43#ibcon#about to write, iclass 20, count 2 2006.245.07:52:12.43#ibcon#wrote, iclass 20, count 2 2006.245.07:52:12.43#ibcon#about to read 3, iclass 20, count 2 2006.245.07:52:12.45#ibcon#read 3, iclass 20, count 2 2006.245.07:52:12.45#ibcon#about to read 4, iclass 20, count 2 2006.245.07:52:12.45#ibcon#read 4, iclass 20, count 2 2006.245.07:52:12.45#ibcon#about to read 5, iclass 20, count 2 2006.245.07:52:12.45#ibcon#read 5, iclass 20, count 2 2006.245.07:52:12.45#ibcon#about to read 6, iclass 20, count 2 2006.245.07:52:12.45#ibcon#read 6, iclass 20, count 2 2006.245.07:52:12.45#ibcon#end of sib2, iclass 20, count 2 2006.245.07:52:12.45#ibcon#*mode == 0, iclass 20, count 2 2006.245.07:52:12.45#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.07:52:12.45#ibcon#[25=AT07-07\r\n] 2006.245.07:52:12.45#ibcon#*before write, iclass 20, count 2 2006.245.07:52:12.45#ibcon#enter sib2, iclass 20, count 2 2006.245.07:52:12.45#ibcon#flushed, iclass 20, count 2 2006.245.07:52:12.45#ibcon#about to write, iclass 20, count 2 2006.245.07:52:12.45#ibcon#wrote, iclass 20, count 2 2006.245.07:52:12.45#ibcon#about to read 3, iclass 20, count 2 2006.245.07:52:12.48#ibcon#read 3, iclass 20, count 2 2006.245.07:52:12.48#ibcon#about to read 4, iclass 20, count 2 2006.245.07:52:12.48#ibcon#read 4, iclass 20, count 2 2006.245.07:52:12.48#ibcon#about to read 5, iclass 20, count 2 2006.245.07:52:12.48#ibcon#read 5, iclass 20, count 2 2006.245.07:52:12.48#ibcon#about to read 6, iclass 20, count 2 2006.245.07:52:12.48#ibcon#read 6, iclass 20, count 2 2006.245.07:52:12.48#ibcon#end of sib2, iclass 20, count 2 2006.245.07:52:12.48#ibcon#*after write, iclass 20, count 2 2006.245.07:52:12.48#ibcon#*before return 0, iclass 20, count 2 2006.245.07:52:12.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:52:12.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.07:52:12.48#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.07:52:12.48#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:12.48#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:52:12.60#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:52:12.60#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:52:12.60#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:52:12.60#ibcon#first serial, iclass 20, count 0 2006.245.07:52:12.60#ibcon#enter sib2, iclass 20, count 0 2006.245.07:52:12.60#ibcon#flushed, iclass 20, count 0 2006.245.07:52:12.60#ibcon#about to write, iclass 20, count 0 2006.245.07:52:12.60#ibcon#wrote, iclass 20, count 0 2006.245.07:52:12.60#ibcon#about to read 3, iclass 20, count 0 2006.245.07:52:12.62#ibcon#read 3, iclass 20, count 0 2006.245.07:52:12.62#ibcon#about to read 4, iclass 20, count 0 2006.245.07:52:12.62#ibcon#read 4, iclass 20, count 0 2006.245.07:52:12.62#ibcon#about to read 5, iclass 20, count 0 2006.245.07:52:12.62#ibcon#read 5, iclass 20, count 0 2006.245.07:52:12.62#ibcon#about to read 6, iclass 20, count 0 2006.245.07:52:12.62#ibcon#read 6, iclass 20, count 0 2006.245.07:52:12.62#ibcon#end of sib2, iclass 20, count 0 2006.245.07:52:12.62#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:52:12.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:52:12.62#ibcon#[25=USB\r\n] 2006.245.07:52:12.62#ibcon#*before write, iclass 20, count 0 2006.245.07:52:12.62#ibcon#enter sib2, iclass 20, count 0 2006.245.07:52:12.62#ibcon#flushed, iclass 20, count 0 2006.245.07:52:12.62#ibcon#about to write, iclass 20, count 0 2006.245.07:52:12.62#ibcon#wrote, iclass 20, count 0 2006.245.07:52:12.62#ibcon#about to read 3, iclass 20, count 0 2006.245.07:52:12.65#ibcon#read 3, iclass 20, count 0 2006.245.07:52:12.65#ibcon#about to read 4, iclass 20, count 0 2006.245.07:52:12.65#ibcon#read 4, iclass 20, count 0 2006.245.07:52:12.65#ibcon#about to read 5, iclass 20, count 0 2006.245.07:52:12.65#ibcon#read 5, iclass 20, count 0 2006.245.07:52:12.65#ibcon#about to read 6, iclass 20, count 0 2006.245.07:52:12.65#ibcon#read 6, iclass 20, count 0 2006.245.07:52:12.65#ibcon#end of sib2, iclass 20, count 0 2006.245.07:52:12.65#ibcon#*after write, iclass 20, count 0 2006.245.07:52:12.65#ibcon#*before return 0, iclass 20, count 0 2006.245.07:52:12.65#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:52:12.65#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.07:52:12.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:52:12.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:52:12.66$vc4f8/valo=8,852.99 2006.245.07:52:12.66#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.07:52:12.66#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.07:52:12.66#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:12.66#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:52:12.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:52:12.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:52:12.66#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:52:12.66#ibcon#first serial, iclass 22, count 0 2006.245.07:52:12.66#ibcon#enter sib2, iclass 22, count 0 2006.245.07:52:12.66#ibcon#flushed, iclass 22, count 0 2006.245.07:52:12.66#ibcon#about to write, iclass 22, count 0 2006.245.07:52:12.66#ibcon#wrote, iclass 22, count 0 2006.245.07:52:12.66#ibcon#about to read 3, iclass 22, count 0 2006.245.07:52:12.67#ibcon#read 3, iclass 22, count 0 2006.245.07:52:12.67#ibcon#about to read 4, iclass 22, count 0 2006.245.07:52:12.67#ibcon#read 4, iclass 22, count 0 2006.245.07:52:12.67#ibcon#about to read 5, iclass 22, count 0 2006.245.07:52:12.67#ibcon#read 5, iclass 22, count 0 2006.245.07:52:12.67#ibcon#about to read 6, iclass 22, count 0 2006.245.07:52:12.67#ibcon#read 6, iclass 22, count 0 2006.245.07:52:12.67#ibcon#end of sib2, iclass 22, count 0 2006.245.07:52:12.67#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:52:12.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:52:12.67#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:52:12.67#ibcon#*before write, iclass 22, count 0 2006.245.07:52:12.67#ibcon#enter sib2, iclass 22, count 0 2006.245.07:52:12.67#ibcon#flushed, iclass 22, count 0 2006.245.07:52:12.67#ibcon#about to write, iclass 22, count 0 2006.245.07:52:12.67#ibcon#wrote, iclass 22, count 0 2006.245.07:52:12.67#ibcon#about to read 3, iclass 22, count 0 2006.245.07:52:12.71#ibcon#read 3, iclass 22, count 0 2006.245.07:52:12.71#ibcon#about to read 4, iclass 22, count 0 2006.245.07:52:12.71#ibcon#read 4, iclass 22, count 0 2006.245.07:52:12.71#ibcon#about to read 5, iclass 22, count 0 2006.245.07:52:12.71#ibcon#read 5, iclass 22, count 0 2006.245.07:52:12.71#ibcon#about to read 6, iclass 22, count 0 2006.245.07:52:12.71#ibcon#read 6, iclass 22, count 0 2006.245.07:52:12.71#ibcon#end of sib2, iclass 22, count 0 2006.245.07:52:12.71#ibcon#*after write, iclass 22, count 0 2006.245.07:52:12.71#ibcon#*before return 0, iclass 22, count 0 2006.245.07:52:12.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:52:12.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.07:52:12.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:52:12.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:52:12.72$vc4f8/va=8,8 2006.245.07:52:12.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.07:52:12.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.07:52:12.72#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:12.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:52:12.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:52:12.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:52:12.76#ibcon#enter wrdev, iclass 24, count 2 2006.245.07:52:12.76#ibcon#first serial, iclass 24, count 2 2006.245.07:52:12.76#ibcon#enter sib2, iclass 24, count 2 2006.245.07:52:12.76#ibcon#flushed, iclass 24, count 2 2006.245.07:52:12.76#ibcon#about to write, iclass 24, count 2 2006.245.07:52:12.76#ibcon#wrote, iclass 24, count 2 2006.245.07:52:12.76#ibcon#about to read 3, iclass 24, count 2 2006.245.07:52:12.78#ibcon#read 3, iclass 24, count 2 2006.245.07:52:12.78#ibcon#about to read 4, iclass 24, count 2 2006.245.07:52:12.78#ibcon#read 4, iclass 24, count 2 2006.245.07:52:12.78#ibcon#about to read 5, iclass 24, count 2 2006.245.07:52:12.78#ibcon#read 5, iclass 24, count 2 2006.245.07:52:12.78#ibcon#about to read 6, iclass 24, count 2 2006.245.07:52:12.78#ibcon#read 6, iclass 24, count 2 2006.245.07:52:12.78#ibcon#end of sib2, iclass 24, count 2 2006.245.07:52:12.78#ibcon#*mode == 0, iclass 24, count 2 2006.245.07:52:12.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.07:52:12.78#ibcon#[25=AT08-08\r\n] 2006.245.07:52:12.78#ibcon#*before write, iclass 24, count 2 2006.245.07:52:12.78#ibcon#enter sib2, iclass 24, count 2 2006.245.07:52:12.78#ibcon#flushed, iclass 24, count 2 2006.245.07:52:12.78#ibcon#about to write, iclass 24, count 2 2006.245.07:52:12.78#ibcon#wrote, iclass 24, count 2 2006.245.07:52:12.78#ibcon#about to read 3, iclass 24, count 2 2006.245.07:52:12.81#ibcon#read 3, iclass 24, count 2 2006.245.07:52:12.81#ibcon#about to read 4, iclass 24, count 2 2006.245.07:52:12.81#ibcon#read 4, iclass 24, count 2 2006.245.07:52:12.81#ibcon#about to read 5, iclass 24, count 2 2006.245.07:52:12.81#ibcon#read 5, iclass 24, count 2 2006.245.07:52:12.81#ibcon#about to read 6, iclass 24, count 2 2006.245.07:52:12.81#ibcon#read 6, iclass 24, count 2 2006.245.07:52:12.81#ibcon#end of sib2, iclass 24, count 2 2006.245.07:52:12.81#ibcon#*after write, iclass 24, count 2 2006.245.07:52:12.81#ibcon#*before return 0, iclass 24, count 2 2006.245.07:52:12.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:52:12.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.07:52:12.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.07:52:12.81#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:12.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:52:12.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:52:12.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:52:12.93#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:52:12.93#ibcon#first serial, iclass 24, count 0 2006.245.07:52:12.93#ibcon#enter sib2, iclass 24, count 0 2006.245.07:52:12.93#ibcon#flushed, iclass 24, count 0 2006.245.07:52:12.93#ibcon#about to write, iclass 24, count 0 2006.245.07:52:12.93#ibcon#wrote, iclass 24, count 0 2006.245.07:52:12.93#ibcon#about to read 3, iclass 24, count 0 2006.245.07:52:12.95#ibcon#read 3, iclass 24, count 0 2006.245.07:52:12.95#ibcon#about to read 4, iclass 24, count 0 2006.245.07:52:12.95#ibcon#read 4, iclass 24, count 0 2006.245.07:52:12.95#ibcon#about to read 5, iclass 24, count 0 2006.245.07:52:12.95#ibcon#read 5, iclass 24, count 0 2006.245.07:52:12.95#ibcon#about to read 6, iclass 24, count 0 2006.245.07:52:12.95#ibcon#read 6, iclass 24, count 0 2006.245.07:52:12.95#ibcon#end of sib2, iclass 24, count 0 2006.245.07:52:12.95#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:52:12.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:52:12.95#ibcon#[25=USB\r\n] 2006.245.07:52:12.95#ibcon#*before write, iclass 24, count 0 2006.245.07:52:12.95#ibcon#enter sib2, iclass 24, count 0 2006.245.07:52:12.95#ibcon#flushed, iclass 24, count 0 2006.245.07:52:12.95#ibcon#about to write, iclass 24, count 0 2006.245.07:52:12.95#ibcon#wrote, iclass 24, count 0 2006.245.07:52:12.95#ibcon#about to read 3, iclass 24, count 0 2006.245.07:52:12.98#ibcon#read 3, iclass 24, count 0 2006.245.07:52:12.98#ibcon#about to read 4, iclass 24, count 0 2006.245.07:52:12.98#ibcon#read 4, iclass 24, count 0 2006.245.07:52:12.98#ibcon#about to read 5, iclass 24, count 0 2006.245.07:52:12.98#ibcon#read 5, iclass 24, count 0 2006.245.07:52:12.98#ibcon#about to read 6, iclass 24, count 0 2006.245.07:52:12.98#ibcon#read 6, iclass 24, count 0 2006.245.07:52:12.98#ibcon#end of sib2, iclass 24, count 0 2006.245.07:52:12.98#ibcon#*after write, iclass 24, count 0 2006.245.07:52:12.98#ibcon#*before return 0, iclass 24, count 0 2006.245.07:52:12.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:52:12.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.07:52:12.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:52:12.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:52:12.99$vc4f8/vblo=1,632.99 2006.245.07:52:12.99#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.07:52:12.99#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.07:52:12.99#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:12.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:52:12.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:52:12.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:52:12.99#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:52:12.99#ibcon#first serial, iclass 26, count 0 2006.245.07:52:12.99#ibcon#enter sib2, iclass 26, count 0 2006.245.07:52:12.99#ibcon#flushed, iclass 26, count 0 2006.245.07:52:12.99#ibcon#about to write, iclass 26, count 0 2006.245.07:52:12.99#ibcon#wrote, iclass 26, count 0 2006.245.07:52:12.99#ibcon#about to read 3, iclass 26, count 0 2006.245.07:52:13.01#ibcon#read 3, iclass 26, count 0 2006.245.07:52:13.01#ibcon#about to read 4, iclass 26, count 0 2006.245.07:52:13.01#ibcon#read 4, iclass 26, count 0 2006.245.07:52:13.01#ibcon#about to read 5, iclass 26, count 0 2006.245.07:52:13.01#ibcon#read 5, iclass 26, count 0 2006.245.07:52:13.01#ibcon#about to read 6, iclass 26, count 0 2006.245.07:52:13.01#ibcon#read 6, iclass 26, count 0 2006.245.07:52:13.01#ibcon#end of sib2, iclass 26, count 0 2006.245.07:52:13.01#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:52:13.01#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:52:13.01#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:52:13.01#ibcon#*before write, iclass 26, count 0 2006.245.07:52:13.01#ibcon#enter sib2, iclass 26, count 0 2006.245.07:52:13.01#ibcon#flushed, iclass 26, count 0 2006.245.07:52:13.01#ibcon#about to write, iclass 26, count 0 2006.245.07:52:13.01#ibcon#wrote, iclass 26, count 0 2006.245.07:52:13.01#ibcon#about to read 3, iclass 26, count 0 2006.245.07:52:13.05#ibcon#read 3, iclass 26, count 0 2006.245.07:52:13.05#ibcon#about to read 4, iclass 26, count 0 2006.245.07:52:13.05#ibcon#read 4, iclass 26, count 0 2006.245.07:52:13.05#ibcon#about to read 5, iclass 26, count 0 2006.245.07:52:13.05#ibcon#read 5, iclass 26, count 0 2006.245.07:52:13.05#ibcon#about to read 6, iclass 26, count 0 2006.245.07:52:13.05#ibcon#read 6, iclass 26, count 0 2006.245.07:52:13.05#ibcon#end of sib2, iclass 26, count 0 2006.245.07:52:13.05#ibcon#*after write, iclass 26, count 0 2006.245.07:52:13.05#ibcon#*before return 0, iclass 26, count 0 2006.245.07:52:13.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:52:13.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.07:52:13.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:52:13.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:52:13.06$vc4f8/vb=1,4 2006.245.07:52:13.06#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.07:52:13.06#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.07:52:13.06#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:13.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:52:13.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:52:13.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:52:13.06#ibcon#enter wrdev, iclass 28, count 2 2006.245.07:52:13.06#ibcon#first serial, iclass 28, count 2 2006.245.07:52:13.06#ibcon#enter sib2, iclass 28, count 2 2006.245.07:52:13.06#ibcon#flushed, iclass 28, count 2 2006.245.07:52:13.06#ibcon#about to write, iclass 28, count 2 2006.245.07:52:13.06#ibcon#wrote, iclass 28, count 2 2006.245.07:52:13.06#ibcon#about to read 3, iclass 28, count 2 2006.245.07:52:13.07#ibcon#read 3, iclass 28, count 2 2006.245.07:52:13.07#ibcon#about to read 4, iclass 28, count 2 2006.245.07:52:13.07#ibcon#read 4, iclass 28, count 2 2006.245.07:52:13.07#ibcon#about to read 5, iclass 28, count 2 2006.245.07:52:13.07#ibcon#read 5, iclass 28, count 2 2006.245.07:52:13.07#ibcon#about to read 6, iclass 28, count 2 2006.245.07:52:13.07#ibcon#read 6, iclass 28, count 2 2006.245.07:52:13.07#ibcon#end of sib2, iclass 28, count 2 2006.245.07:52:13.07#ibcon#*mode == 0, iclass 28, count 2 2006.245.07:52:13.07#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.07:52:13.07#ibcon#[27=AT01-04\r\n] 2006.245.07:52:13.07#ibcon#*before write, iclass 28, count 2 2006.245.07:52:13.07#ibcon#enter sib2, iclass 28, count 2 2006.245.07:52:13.07#ibcon#flushed, iclass 28, count 2 2006.245.07:52:13.07#ibcon#about to write, iclass 28, count 2 2006.245.07:52:13.07#ibcon#wrote, iclass 28, count 2 2006.245.07:52:13.07#ibcon#about to read 3, iclass 28, count 2 2006.245.07:52:13.10#ibcon#read 3, iclass 28, count 2 2006.245.07:52:13.10#ibcon#about to read 4, iclass 28, count 2 2006.245.07:52:13.10#ibcon#read 4, iclass 28, count 2 2006.245.07:52:13.10#ibcon#about to read 5, iclass 28, count 2 2006.245.07:52:13.10#ibcon#read 5, iclass 28, count 2 2006.245.07:52:13.10#ibcon#about to read 6, iclass 28, count 2 2006.245.07:52:13.10#ibcon#read 6, iclass 28, count 2 2006.245.07:52:13.10#ibcon#end of sib2, iclass 28, count 2 2006.245.07:52:13.10#ibcon#*after write, iclass 28, count 2 2006.245.07:52:13.10#ibcon#*before return 0, iclass 28, count 2 2006.245.07:52:13.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:52:13.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.07:52:13.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.07:52:13.10#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:13.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:52:13.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:52:13.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:52:13.22#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:52:13.22#ibcon#first serial, iclass 28, count 0 2006.245.07:52:13.22#ibcon#enter sib2, iclass 28, count 0 2006.245.07:52:13.22#ibcon#flushed, iclass 28, count 0 2006.245.07:52:13.22#ibcon#about to write, iclass 28, count 0 2006.245.07:52:13.22#ibcon#wrote, iclass 28, count 0 2006.245.07:52:13.22#ibcon#about to read 3, iclass 28, count 0 2006.245.07:52:13.24#ibcon#read 3, iclass 28, count 0 2006.245.07:52:13.24#ibcon#about to read 4, iclass 28, count 0 2006.245.07:52:13.24#ibcon#read 4, iclass 28, count 0 2006.245.07:52:13.24#ibcon#about to read 5, iclass 28, count 0 2006.245.07:52:13.24#ibcon#read 5, iclass 28, count 0 2006.245.07:52:13.24#ibcon#about to read 6, iclass 28, count 0 2006.245.07:52:13.24#ibcon#read 6, iclass 28, count 0 2006.245.07:52:13.24#ibcon#end of sib2, iclass 28, count 0 2006.245.07:52:13.24#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:52:13.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:52:13.24#ibcon#[27=USB\r\n] 2006.245.07:52:13.24#ibcon#*before write, iclass 28, count 0 2006.245.07:52:13.24#ibcon#enter sib2, iclass 28, count 0 2006.245.07:52:13.24#ibcon#flushed, iclass 28, count 0 2006.245.07:52:13.24#ibcon#about to write, iclass 28, count 0 2006.245.07:52:13.24#ibcon#wrote, iclass 28, count 0 2006.245.07:52:13.24#ibcon#about to read 3, iclass 28, count 0 2006.245.07:52:13.27#ibcon#read 3, iclass 28, count 0 2006.245.07:52:13.27#ibcon#about to read 4, iclass 28, count 0 2006.245.07:52:13.27#ibcon#read 4, iclass 28, count 0 2006.245.07:52:13.27#ibcon#about to read 5, iclass 28, count 0 2006.245.07:52:13.27#ibcon#read 5, iclass 28, count 0 2006.245.07:52:13.27#ibcon#about to read 6, iclass 28, count 0 2006.245.07:52:13.27#ibcon#read 6, iclass 28, count 0 2006.245.07:52:13.27#ibcon#end of sib2, iclass 28, count 0 2006.245.07:52:13.27#ibcon#*after write, iclass 28, count 0 2006.245.07:52:13.27#ibcon#*before return 0, iclass 28, count 0 2006.245.07:52:13.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:52:13.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.07:52:13.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:52:13.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:52:13.28$vc4f8/vblo=2,640.99 2006.245.07:52:13.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:52:13.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:52:13.28#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:13.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:13.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:13.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:13.28#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:52:13.28#ibcon#first serial, iclass 30, count 0 2006.245.07:52:13.28#ibcon#enter sib2, iclass 30, count 0 2006.245.07:52:13.28#ibcon#flushed, iclass 30, count 0 2006.245.07:52:13.28#ibcon#about to write, iclass 30, count 0 2006.245.07:52:13.28#ibcon#wrote, iclass 30, count 0 2006.245.07:52:13.28#ibcon#about to read 3, iclass 30, count 0 2006.245.07:52:13.29#ibcon#read 3, iclass 30, count 0 2006.245.07:52:13.29#ibcon#about to read 4, iclass 30, count 0 2006.245.07:52:13.29#ibcon#read 4, iclass 30, count 0 2006.245.07:52:13.29#ibcon#about to read 5, iclass 30, count 0 2006.245.07:52:13.29#ibcon#read 5, iclass 30, count 0 2006.245.07:52:13.29#ibcon#about to read 6, iclass 30, count 0 2006.245.07:52:13.29#ibcon#read 6, iclass 30, count 0 2006.245.07:52:13.29#ibcon#end of sib2, iclass 30, count 0 2006.245.07:52:13.29#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:52:13.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:52:13.29#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:52:13.29#ibcon#*before write, iclass 30, count 0 2006.245.07:52:13.29#ibcon#enter sib2, iclass 30, count 0 2006.245.07:52:13.29#ibcon#flushed, iclass 30, count 0 2006.245.07:52:13.29#ibcon#about to write, iclass 30, count 0 2006.245.07:52:13.29#ibcon#wrote, iclass 30, count 0 2006.245.07:52:13.29#ibcon#about to read 3, iclass 30, count 0 2006.245.07:52:13.33#ibcon#read 3, iclass 30, count 0 2006.245.07:52:13.33#ibcon#about to read 4, iclass 30, count 0 2006.245.07:52:13.33#ibcon#read 4, iclass 30, count 0 2006.245.07:52:13.33#ibcon#about to read 5, iclass 30, count 0 2006.245.07:52:13.33#ibcon#read 5, iclass 30, count 0 2006.245.07:52:13.33#ibcon#about to read 6, iclass 30, count 0 2006.245.07:52:13.33#ibcon#read 6, iclass 30, count 0 2006.245.07:52:13.33#ibcon#end of sib2, iclass 30, count 0 2006.245.07:52:13.33#ibcon#*after write, iclass 30, count 0 2006.245.07:52:13.33#ibcon#*before return 0, iclass 30, count 0 2006.245.07:52:13.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:13.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:52:13.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:52:13.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:52:13.34$vc4f8/vb=2,4 2006.245.07:52:13.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.07:52:13.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.07:52:13.34#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:13.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:13.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:13.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:13.38#ibcon#enter wrdev, iclass 32, count 2 2006.245.07:52:13.38#ibcon#first serial, iclass 32, count 2 2006.245.07:52:13.38#ibcon#enter sib2, iclass 32, count 2 2006.245.07:52:13.38#ibcon#flushed, iclass 32, count 2 2006.245.07:52:13.38#ibcon#about to write, iclass 32, count 2 2006.245.07:52:13.38#ibcon#wrote, iclass 32, count 2 2006.245.07:52:13.38#ibcon#about to read 3, iclass 32, count 2 2006.245.07:52:13.40#ibcon#read 3, iclass 32, count 2 2006.245.07:52:13.40#ibcon#about to read 4, iclass 32, count 2 2006.245.07:52:13.40#ibcon#read 4, iclass 32, count 2 2006.245.07:52:13.40#ibcon#about to read 5, iclass 32, count 2 2006.245.07:52:13.40#ibcon#read 5, iclass 32, count 2 2006.245.07:52:13.40#ibcon#about to read 6, iclass 32, count 2 2006.245.07:52:13.40#ibcon#read 6, iclass 32, count 2 2006.245.07:52:13.40#ibcon#end of sib2, iclass 32, count 2 2006.245.07:52:13.40#ibcon#*mode == 0, iclass 32, count 2 2006.245.07:52:13.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.07:52:13.40#ibcon#[27=AT02-04\r\n] 2006.245.07:52:13.40#ibcon#*before write, iclass 32, count 2 2006.245.07:52:13.40#ibcon#enter sib2, iclass 32, count 2 2006.245.07:52:13.40#ibcon#flushed, iclass 32, count 2 2006.245.07:52:13.40#ibcon#about to write, iclass 32, count 2 2006.245.07:52:13.40#ibcon#wrote, iclass 32, count 2 2006.245.07:52:13.40#ibcon#about to read 3, iclass 32, count 2 2006.245.07:52:13.43#ibcon#read 3, iclass 32, count 2 2006.245.07:52:13.43#ibcon#about to read 4, iclass 32, count 2 2006.245.07:52:13.43#ibcon#read 4, iclass 32, count 2 2006.245.07:52:13.43#ibcon#about to read 5, iclass 32, count 2 2006.245.07:52:13.43#ibcon#read 5, iclass 32, count 2 2006.245.07:52:13.43#ibcon#about to read 6, iclass 32, count 2 2006.245.07:52:13.43#ibcon#read 6, iclass 32, count 2 2006.245.07:52:13.43#ibcon#end of sib2, iclass 32, count 2 2006.245.07:52:13.43#ibcon#*after write, iclass 32, count 2 2006.245.07:52:13.43#ibcon#*before return 0, iclass 32, count 2 2006.245.07:52:13.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:13.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.07:52:13.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.07:52:13.43#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:13.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:13.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:13.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:13.55#ibcon#enter wrdev, iclass 32, count 0 2006.245.07:52:13.55#ibcon#first serial, iclass 32, count 0 2006.245.07:52:13.55#ibcon#enter sib2, iclass 32, count 0 2006.245.07:52:13.55#ibcon#flushed, iclass 32, count 0 2006.245.07:52:13.55#ibcon#about to write, iclass 32, count 0 2006.245.07:52:13.55#ibcon#wrote, iclass 32, count 0 2006.245.07:52:13.55#ibcon#about to read 3, iclass 32, count 0 2006.245.07:52:13.57#ibcon#read 3, iclass 32, count 0 2006.245.07:52:13.57#ibcon#about to read 4, iclass 32, count 0 2006.245.07:52:13.57#ibcon#read 4, iclass 32, count 0 2006.245.07:52:13.57#ibcon#about to read 5, iclass 32, count 0 2006.245.07:52:13.57#ibcon#read 5, iclass 32, count 0 2006.245.07:52:13.57#ibcon#about to read 6, iclass 32, count 0 2006.245.07:52:13.57#ibcon#read 6, iclass 32, count 0 2006.245.07:52:13.57#ibcon#end of sib2, iclass 32, count 0 2006.245.07:52:13.57#ibcon#*mode == 0, iclass 32, count 0 2006.245.07:52:13.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.07:52:13.57#ibcon#[27=USB\r\n] 2006.245.07:52:13.57#ibcon#*before write, iclass 32, count 0 2006.245.07:52:13.57#ibcon#enter sib2, iclass 32, count 0 2006.245.07:52:13.57#ibcon#flushed, iclass 32, count 0 2006.245.07:52:13.57#ibcon#about to write, iclass 32, count 0 2006.245.07:52:13.57#ibcon#wrote, iclass 32, count 0 2006.245.07:52:13.57#ibcon#about to read 3, iclass 32, count 0 2006.245.07:52:13.60#ibcon#read 3, iclass 32, count 0 2006.245.07:52:13.60#ibcon#about to read 4, iclass 32, count 0 2006.245.07:52:13.60#ibcon#read 4, iclass 32, count 0 2006.245.07:52:13.60#ibcon#about to read 5, iclass 32, count 0 2006.245.07:52:13.60#ibcon#read 5, iclass 32, count 0 2006.245.07:52:13.60#ibcon#about to read 6, iclass 32, count 0 2006.245.07:52:13.60#ibcon#read 6, iclass 32, count 0 2006.245.07:52:13.60#ibcon#end of sib2, iclass 32, count 0 2006.245.07:52:13.60#ibcon#*after write, iclass 32, count 0 2006.245.07:52:13.60#ibcon#*before return 0, iclass 32, count 0 2006.245.07:52:13.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:13.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.07:52:13.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.07:52:13.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.07:52:13.61$vc4f8/vblo=3,656.99 2006.245.07:52:13.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.07:52:13.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.07:52:13.61#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:13.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:13.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:13.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:13.61#ibcon#enter wrdev, iclass 34, count 0 2006.245.07:52:13.61#ibcon#first serial, iclass 34, count 0 2006.245.07:52:13.61#ibcon#enter sib2, iclass 34, count 0 2006.245.07:52:13.61#ibcon#flushed, iclass 34, count 0 2006.245.07:52:13.61#ibcon#about to write, iclass 34, count 0 2006.245.07:52:13.61#ibcon#wrote, iclass 34, count 0 2006.245.07:52:13.61#ibcon#about to read 3, iclass 34, count 0 2006.245.07:52:13.62#ibcon#read 3, iclass 34, count 0 2006.245.07:52:13.62#ibcon#about to read 4, iclass 34, count 0 2006.245.07:52:13.62#ibcon#read 4, iclass 34, count 0 2006.245.07:52:13.62#ibcon#about to read 5, iclass 34, count 0 2006.245.07:52:13.62#ibcon#read 5, iclass 34, count 0 2006.245.07:52:13.62#ibcon#about to read 6, iclass 34, count 0 2006.245.07:52:13.62#ibcon#read 6, iclass 34, count 0 2006.245.07:52:13.62#ibcon#end of sib2, iclass 34, count 0 2006.245.07:52:13.62#ibcon#*mode == 0, iclass 34, count 0 2006.245.07:52:13.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.07:52:13.62#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:52:13.62#ibcon#*before write, iclass 34, count 0 2006.245.07:52:13.62#ibcon#enter sib2, iclass 34, count 0 2006.245.07:52:13.62#ibcon#flushed, iclass 34, count 0 2006.245.07:52:13.62#ibcon#about to write, iclass 34, count 0 2006.245.07:52:13.62#ibcon#wrote, iclass 34, count 0 2006.245.07:52:13.62#ibcon#about to read 3, iclass 34, count 0 2006.245.07:52:13.66#ibcon#read 3, iclass 34, count 0 2006.245.07:52:13.66#ibcon#about to read 4, iclass 34, count 0 2006.245.07:52:13.66#ibcon#read 4, iclass 34, count 0 2006.245.07:52:13.66#ibcon#about to read 5, iclass 34, count 0 2006.245.07:52:13.66#ibcon#read 5, iclass 34, count 0 2006.245.07:52:13.66#ibcon#about to read 6, iclass 34, count 0 2006.245.07:52:13.66#ibcon#read 6, iclass 34, count 0 2006.245.07:52:13.66#ibcon#end of sib2, iclass 34, count 0 2006.245.07:52:13.66#ibcon#*after write, iclass 34, count 0 2006.245.07:52:13.66#ibcon#*before return 0, iclass 34, count 0 2006.245.07:52:13.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:13.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.07:52:13.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.07:52:13.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.07:52:13.67$vc4f8/vb=3,4 2006.245.07:52:13.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.07:52:13.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.07:52:13.67#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:13.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:13.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:13.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:13.72#ibcon#enter wrdev, iclass 36, count 2 2006.245.07:52:13.72#ibcon#first serial, iclass 36, count 2 2006.245.07:52:13.72#ibcon#enter sib2, iclass 36, count 2 2006.245.07:52:13.72#ibcon#flushed, iclass 36, count 2 2006.245.07:52:13.72#ibcon#about to write, iclass 36, count 2 2006.245.07:52:13.72#ibcon#wrote, iclass 36, count 2 2006.245.07:52:13.72#ibcon#about to read 3, iclass 36, count 2 2006.245.07:52:13.74#ibcon#read 3, iclass 36, count 2 2006.245.07:52:13.74#ibcon#about to read 4, iclass 36, count 2 2006.245.07:52:13.74#ibcon#read 4, iclass 36, count 2 2006.245.07:52:13.74#ibcon#about to read 5, iclass 36, count 2 2006.245.07:52:13.74#ibcon#read 5, iclass 36, count 2 2006.245.07:52:13.74#ibcon#about to read 6, iclass 36, count 2 2006.245.07:52:13.74#ibcon#read 6, iclass 36, count 2 2006.245.07:52:13.74#ibcon#end of sib2, iclass 36, count 2 2006.245.07:52:13.74#ibcon#*mode == 0, iclass 36, count 2 2006.245.07:52:13.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.07:52:13.74#ibcon#[27=AT03-04\r\n] 2006.245.07:52:13.74#ibcon#*before write, iclass 36, count 2 2006.245.07:52:13.74#ibcon#enter sib2, iclass 36, count 2 2006.245.07:52:13.74#ibcon#flushed, iclass 36, count 2 2006.245.07:52:13.74#ibcon#about to write, iclass 36, count 2 2006.245.07:52:13.74#ibcon#wrote, iclass 36, count 2 2006.245.07:52:13.74#ibcon#about to read 3, iclass 36, count 2 2006.245.07:52:13.76#ibcon#read 3, iclass 36, count 2 2006.245.07:52:13.76#ibcon#about to read 4, iclass 36, count 2 2006.245.07:52:13.76#ibcon#read 4, iclass 36, count 2 2006.245.07:52:13.76#ibcon#about to read 5, iclass 36, count 2 2006.245.07:52:13.76#ibcon#read 5, iclass 36, count 2 2006.245.07:52:13.76#ibcon#about to read 6, iclass 36, count 2 2006.245.07:52:13.76#ibcon#read 6, iclass 36, count 2 2006.245.07:52:13.76#ibcon#end of sib2, iclass 36, count 2 2006.245.07:52:13.76#ibcon#*after write, iclass 36, count 2 2006.245.07:52:13.76#ibcon#*before return 0, iclass 36, count 2 2006.245.07:52:13.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:13.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.07:52:13.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.07:52:13.76#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:13.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:13.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:13.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:13.88#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:52:13.88#ibcon#first serial, iclass 36, count 0 2006.245.07:52:13.88#ibcon#enter sib2, iclass 36, count 0 2006.245.07:52:13.88#ibcon#flushed, iclass 36, count 0 2006.245.07:52:13.88#ibcon#about to write, iclass 36, count 0 2006.245.07:52:13.88#ibcon#wrote, iclass 36, count 0 2006.245.07:52:13.88#ibcon#about to read 3, iclass 36, count 0 2006.245.07:52:13.90#ibcon#read 3, iclass 36, count 0 2006.245.07:52:13.90#ibcon#about to read 4, iclass 36, count 0 2006.245.07:52:13.90#ibcon#read 4, iclass 36, count 0 2006.245.07:52:13.90#ibcon#about to read 5, iclass 36, count 0 2006.245.07:52:13.90#ibcon#read 5, iclass 36, count 0 2006.245.07:52:13.90#ibcon#about to read 6, iclass 36, count 0 2006.245.07:52:13.90#ibcon#read 6, iclass 36, count 0 2006.245.07:52:13.90#ibcon#end of sib2, iclass 36, count 0 2006.245.07:52:13.90#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:52:13.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:52:13.90#ibcon#[27=USB\r\n] 2006.245.07:52:13.90#ibcon#*before write, iclass 36, count 0 2006.245.07:52:13.90#ibcon#enter sib2, iclass 36, count 0 2006.245.07:52:13.90#ibcon#flushed, iclass 36, count 0 2006.245.07:52:13.90#ibcon#about to write, iclass 36, count 0 2006.245.07:52:13.90#ibcon#wrote, iclass 36, count 0 2006.245.07:52:13.90#ibcon#about to read 3, iclass 36, count 0 2006.245.07:52:13.93#ibcon#read 3, iclass 36, count 0 2006.245.07:52:13.93#ibcon#about to read 4, iclass 36, count 0 2006.245.07:52:13.93#ibcon#read 4, iclass 36, count 0 2006.245.07:52:13.93#ibcon#about to read 5, iclass 36, count 0 2006.245.07:52:13.93#ibcon#read 5, iclass 36, count 0 2006.245.07:52:13.93#ibcon#about to read 6, iclass 36, count 0 2006.245.07:52:13.93#ibcon#read 6, iclass 36, count 0 2006.245.07:52:13.93#ibcon#end of sib2, iclass 36, count 0 2006.245.07:52:13.93#ibcon#*after write, iclass 36, count 0 2006.245.07:52:13.93#ibcon#*before return 0, iclass 36, count 0 2006.245.07:52:13.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:13.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.07:52:13.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:52:13.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:52:13.94$vc4f8/vblo=4,712.99 2006.245.07:52:13.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.07:52:13.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.07:52:13.94#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:13.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:13.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:13.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:13.94#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:52:13.94#ibcon#first serial, iclass 38, count 0 2006.245.07:52:13.94#ibcon#enter sib2, iclass 38, count 0 2006.245.07:52:13.94#ibcon#flushed, iclass 38, count 0 2006.245.07:52:13.94#ibcon#about to write, iclass 38, count 0 2006.245.07:52:13.94#ibcon#wrote, iclass 38, count 0 2006.245.07:52:13.94#ibcon#about to read 3, iclass 38, count 0 2006.245.07:52:13.95#ibcon#read 3, iclass 38, count 0 2006.245.07:52:13.95#ibcon#about to read 4, iclass 38, count 0 2006.245.07:52:13.95#ibcon#read 4, iclass 38, count 0 2006.245.07:52:13.95#ibcon#about to read 5, iclass 38, count 0 2006.245.07:52:13.95#ibcon#read 5, iclass 38, count 0 2006.245.07:52:13.95#ibcon#about to read 6, iclass 38, count 0 2006.245.07:52:13.95#ibcon#read 6, iclass 38, count 0 2006.245.07:52:13.95#ibcon#end of sib2, iclass 38, count 0 2006.245.07:52:13.95#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:52:13.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:52:13.95#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:52:13.95#ibcon#*before write, iclass 38, count 0 2006.245.07:52:13.95#ibcon#enter sib2, iclass 38, count 0 2006.245.07:52:13.95#ibcon#flushed, iclass 38, count 0 2006.245.07:52:13.95#ibcon#about to write, iclass 38, count 0 2006.245.07:52:13.95#ibcon#wrote, iclass 38, count 0 2006.245.07:52:13.95#ibcon#about to read 3, iclass 38, count 0 2006.245.07:52:13.99#ibcon#read 3, iclass 38, count 0 2006.245.07:52:13.99#ibcon#about to read 4, iclass 38, count 0 2006.245.07:52:13.99#ibcon#read 4, iclass 38, count 0 2006.245.07:52:13.99#ibcon#about to read 5, iclass 38, count 0 2006.245.07:52:13.99#ibcon#read 5, iclass 38, count 0 2006.245.07:52:13.99#ibcon#about to read 6, iclass 38, count 0 2006.245.07:52:13.99#ibcon#read 6, iclass 38, count 0 2006.245.07:52:13.99#ibcon#end of sib2, iclass 38, count 0 2006.245.07:52:13.99#ibcon#*after write, iclass 38, count 0 2006.245.07:52:13.99#ibcon#*before return 0, iclass 38, count 0 2006.245.07:52:13.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:13.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.07:52:13.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:52:13.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:52:14.00$vc4f8/vb=4,4 2006.245.07:52:14.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.07:52:14.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.07:52:14.00#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:14.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:14.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:14.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:14.04#ibcon#enter wrdev, iclass 40, count 2 2006.245.07:52:14.04#ibcon#first serial, iclass 40, count 2 2006.245.07:52:14.04#ibcon#enter sib2, iclass 40, count 2 2006.245.07:52:14.04#ibcon#flushed, iclass 40, count 2 2006.245.07:52:14.04#ibcon#about to write, iclass 40, count 2 2006.245.07:52:14.04#ibcon#wrote, iclass 40, count 2 2006.245.07:52:14.04#ibcon#about to read 3, iclass 40, count 2 2006.245.07:52:14.06#ibcon#read 3, iclass 40, count 2 2006.245.07:52:14.06#ibcon#about to read 4, iclass 40, count 2 2006.245.07:52:14.06#ibcon#read 4, iclass 40, count 2 2006.245.07:52:14.06#ibcon#about to read 5, iclass 40, count 2 2006.245.07:52:14.06#ibcon#read 5, iclass 40, count 2 2006.245.07:52:14.06#ibcon#about to read 6, iclass 40, count 2 2006.245.07:52:14.06#ibcon#read 6, iclass 40, count 2 2006.245.07:52:14.06#ibcon#end of sib2, iclass 40, count 2 2006.245.07:52:14.06#ibcon#*mode == 0, iclass 40, count 2 2006.245.07:52:14.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.07:52:14.06#ibcon#[27=AT04-04\r\n] 2006.245.07:52:14.06#ibcon#*before write, iclass 40, count 2 2006.245.07:52:14.06#ibcon#enter sib2, iclass 40, count 2 2006.245.07:52:14.06#ibcon#flushed, iclass 40, count 2 2006.245.07:52:14.06#ibcon#about to write, iclass 40, count 2 2006.245.07:52:14.06#ibcon#wrote, iclass 40, count 2 2006.245.07:52:14.06#ibcon#about to read 3, iclass 40, count 2 2006.245.07:52:14.09#ibcon#read 3, iclass 40, count 2 2006.245.07:52:14.09#ibcon#about to read 4, iclass 40, count 2 2006.245.07:52:14.09#ibcon#read 4, iclass 40, count 2 2006.245.07:52:14.09#ibcon#about to read 5, iclass 40, count 2 2006.245.07:52:14.09#ibcon#read 5, iclass 40, count 2 2006.245.07:52:14.09#ibcon#about to read 6, iclass 40, count 2 2006.245.07:52:14.09#ibcon#read 6, iclass 40, count 2 2006.245.07:52:14.09#ibcon#end of sib2, iclass 40, count 2 2006.245.07:52:14.09#ibcon#*after write, iclass 40, count 2 2006.245.07:52:14.09#ibcon#*before return 0, iclass 40, count 2 2006.245.07:52:14.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:14.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.07:52:14.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.07:52:14.09#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:14.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:14.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:14.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:14.21#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:52:14.21#ibcon#first serial, iclass 40, count 0 2006.245.07:52:14.21#ibcon#enter sib2, iclass 40, count 0 2006.245.07:52:14.21#ibcon#flushed, iclass 40, count 0 2006.245.07:52:14.21#ibcon#about to write, iclass 40, count 0 2006.245.07:52:14.21#ibcon#wrote, iclass 40, count 0 2006.245.07:52:14.21#ibcon#about to read 3, iclass 40, count 0 2006.245.07:52:14.23#ibcon#read 3, iclass 40, count 0 2006.245.07:52:14.23#ibcon#about to read 4, iclass 40, count 0 2006.245.07:52:14.23#ibcon#read 4, iclass 40, count 0 2006.245.07:52:14.23#ibcon#about to read 5, iclass 40, count 0 2006.245.07:52:14.23#ibcon#read 5, iclass 40, count 0 2006.245.07:52:14.23#ibcon#about to read 6, iclass 40, count 0 2006.245.07:52:14.23#ibcon#read 6, iclass 40, count 0 2006.245.07:52:14.23#ibcon#end of sib2, iclass 40, count 0 2006.245.07:52:14.23#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:52:14.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:52:14.23#ibcon#[27=USB\r\n] 2006.245.07:52:14.23#ibcon#*before write, iclass 40, count 0 2006.245.07:52:14.23#ibcon#enter sib2, iclass 40, count 0 2006.245.07:52:14.23#ibcon#flushed, iclass 40, count 0 2006.245.07:52:14.23#ibcon#about to write, iclass 40, count 0 2006.245.07:52:14.23#ibcon#wrote, iclass 40, count 0 2006.245.07:52:14.23#ibcon#about to read 3, iclass 40, count 0 2006.245.07:52:14.27#ibcon#read 3, iclass 40, count 0 2006.245.07:52:14.27#ibcon#about to read 4, iclass 40, count 0 2006.245.07:52:14.27#ibcon#read 4, iclass 40, count 0 2006.245.07:52:14.27#ibcon#about to read 5, iclass 40, count 0 2006.245.07:52:14.27#ibcon#read 5, iclass 40, count 0 2006.245.07:52:14.27#ibcon#about to read 6, iclass 40, count 0 2006.245.07:52:14.27#ibcon#read 6, iclass 40, count 0 2006.245.07:52:14.27#ibcon#end of sib2, iclass 40, count 0 2006.245.07:52:14.27#ibcon#*after write, iclass 40, count 0 2006.245.07:52:14.27#ibcon#*before return 0, iclass 40, count 0 2006.245.07:52:14.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:14.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.07:52:14.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:52:14.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:52:14.27$vc4f8/vblo=5,744.99 2006.245.07:52:14.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.07:52:14.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.07:52:14.27#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:14.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:14.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:14.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:14.27#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:52:14.27#ibcon#first serial, iclass 4, count 0 2006.245.07:52:14.27#ibcon#enter sib2, iclass 4, count 0 2006.245.07:52:14.27#ibcon#flushed, iclass 4, count 0 2006.245.07:52:14.27#ibcon#about to write, iclass 4, count 0 2006.245.07:52:14.27#ibcon#wrote, iclass 4, count 0 2006.245.07:52:14.27#ibcon#about to read 3, iclass 4, count 0 2006.245.07:52:14.28#ibcon#read 3, iclass 4, count 0 2006.245.07:52:14.28#ibcon#about to read 4, iclass 4, count 0 2006.245.07:52:14.28#ibcon#read 4, iclass 4, count 0 2006.245.07:52:14.28#ibcon#about to read 5, iclass 4, count 0 2006.245.07:52:14.28#ibcon#read 5, iclass 4, count 0 2006.245.07:52:14.28#ibcon#about to read 6, iclass 4, count 0 2006.245.07:52:14.28#ibcon#read 6, iclass 4, count 0 2006.245.07:52:14.28#ibcon#end of sib2, iclass 4, count 0 2006.245.07:52:14.28#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:52:14.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:52:14.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:52:14.28#ibcon#*before write, iclass 4, count 0 2006.245.07:52:14.28#ibcon#enter sib2, iclass 4, count 0 2006.245.07:52:14.28#ibcon#flushed, iclass 4, count 0 2006.245.07:52:14.28#ibcon#about to write, iclass 4, count 0 2006.245.07:52:14.28#ibcon#wrote, iclass 4, count 0 2006.245.07:52:14.28#ibcon#about to read 3, iclass 4, count 0 2006.245.07:52:14.32#ibcon#read 3, iclass 4, count 0 2006.245.07:52:14.32#ibcon#about to read 4, iclass 4, count 0 2006.245.07:52:14.32#ibcon#read 4, iclass 4, count 0 2006.245.07:52:14.32#ibcon#about to read 5, iclass 4, count 0 2006.245.07:52:14.32#ibcon#read 5, iclass 4, count 0 2006.245.07:52:14.32#ibcon#about to read 6, iclass 4, count 0 2006.245.07:52:14.32#ibcon#read 6, iclass 4, count 0 2006.245.07:52:14.32#ibcon#end of sib2, iclass 4, count 0 2006.245.07:52:14.32#ibcon#*after write, iclass 4, count 0 2006.245.07:52:14.32#ibcon#*before return 0, iclass 4, count 0 2006.245.07:52:14.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:14.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.07:52:14.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:52:14.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:52:14.33$vc4f8/vb=5,3 2006.245.07:52:14.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.07:52:14.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.07:52:14.33#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:14.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:14.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:14.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:14.38#ibcon#enter wrdev, iclass 6, count 2 2006.245.07:52:14.38#ibcon#first serial, iclass 6, count 2 2006.245.07:52:14.38#ibcon#enter sib2, iclass 6, count 2 2006.245.07:52:14.38#ibcon#flushed, iclass 6, count 2 2006.245.07:52:14.38#ibcon#about to write, iclass 6, count 2 2006.245.07:52:14.38#ibcon#wrote, iclass 6, count 2 2006.245.07:52:14.38#ibcon#about to read 3, iclass 6, count 2 2006.245.07:52:14.40#ibcon#read 3, iclass 6, count 2 2006.245.07:52:14.40#ibcon#about to read 4, iclass 6, count 2 2006.245.07:52:14.40#ibcon#read 4, iclass 6, count 2 2006.245.07:52:14.40#ibcon#about to read 5, iclass 6, count 2 2006.245.07:52:14.40#ibcon#read 5, iclass 6, count 2 2006.245.07:52:14.40#ibcon#about to read 6, iclass 6, count 2 2006.245.07:52:14.40#ibcon#read 6, iclass 6, count 2 2006.245.07:52:14.40#ibcon#end of sib2, iclass 6, count 2 2006.245.07:52:14.40#ibcon#*mode == 0, iclass 6, count 2 2006.245.07:52:14.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.07:52:14.40#ibcon#[27=AT05-03\r\n] 2006.245.07:52:14.40#ibcon#*before write, iclass 6, count 2 2006.245.07:52:14.40#ibcon#enter sib2, iclass 6, count 2 2006.245.07:52:14.40#ibcon#flushed, iclass 6, count 2 2006.245.07:52:14.40#ibcon#about to write, iclass 6, count 2 2006.245.07:52:14.40#ibcon#wrote, iclass 6, count 2 2006.245.07:52:14.40#ibcon#about to read 3, iclass 6, count 2 2006.245.07:52:14.43#ibcon#read 3, iclass 6, count 2 2006.245.07:52:14.43#ibcon#about to read 4, iclass 6, count 2 2006.245.07:52:14.43#ibcon#read 4, iclass 6, count 2 2006.245.07:52:14.43#ibcon#about to read 5, iclass 6, count 2 2006.245.07:52:14.43#ibcon#read 5, iclass 6, count 2 2006.245.07:52:14.43#ibcon#about to read 6, iclass 6, count 2 2006.245.07:52:14.43#ibcon#read 6, iclass 6, count 2 2006.245.07:52:14.43#ibcon#end of sib2, iclass 6, count 2 2006.245.07:52:14.43#ibcon#*after write, iclass 6, count 2 2006.245.07:52:14.43#ibcon#*before return 0, iclass 6, count 2 2006.245.07:52:14.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:14.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.07:52:14.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.07:52:14.43#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:14.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:14.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:14.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:14.55#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:52:14.55#ibcon#first serial, iclass 6, count 0 2006.245.07:52:14.55#ibcon#enter sib2, iclass 6, count 0 2006.245.07:52:14.55#ibcon#flushed, iclass 6, count 0 2006.245.07:52:14.55#ibcon#about to write, iclass 6, count 0 2006.245.07:52:14.55#ibcon#wrote, iclass 6, count 0 2006.245.07:52:14.55#ibcon#about to read 3, iclass 6, count 0 2006.245.07:52:14.57#ibcon#read 3, iclass 6, count 0 2006.245.07:52:14.57#ibcon#about to read 4, iclass 6, count 0 2006.245.07:52:14.57#ibcon#read 4, iclass 6, count 0 2006.245.07:52:14.57#ibcon#about to read 5, iclass 6, count 0 2006.245.07:52:14.57#ibcon#read 5, iclass 6, count 0 2006.245.07:52:14.57#ibcon#about to read 6, iclass 6, count 0 2006.245.07:52:14.57#ibcon#read 6, iclass 6, count 0 2006.245.07:52:14.57#ibcon#end of sib2, iclass 6, count 0 2006.245.07:52:14.57#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:52:14.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:52:14.57#ibcon#[27=USB\r\n] 2006.245.07:52:14.57#ibcon#*before write, iclass 6, count 0 2006.245.07:52:14.57#ibcon#enter sib2, iclass 6, count 0 2006.245.07:52:14.57#ibcon#flushed, iclass 6, count 0 2006.245.07:52:14.57#ibcon#about to write, iclass 6, count 0 2006.245.07:52:14.57#ibcon#wrote, iclass 6, count 0 2006.245.07:52:14.57#ibcon#about to read 3, iclass 6, count 0 2006.245.07:52:14.60#ibcon#read 3, iclass 6, count 0 2006.245.07:52:14.60#ibcon#about to read 4, iclass 6, count 0 2006.245.07:52:14.60#ibcon#read 4, iclass 6, count 0 2006.245.07:52:14.60#ibcon#about to read 5, iclass 6, count 0 2006.245.07:52:14.60#ibcon#read 5, iclass 6, count 0 2006.245.07:52:14.60#ibcon#about to read 6, iclass 6, count 0 2006.245.07:52:14.60#ibcon#read 6, iclass 6, count 0 2006.245.07:52:14.60#ibcon#end of sib2, iclass 6, count 0 2006.245.07:52:14.60#ibcon#*after write, iclass 6, count 0 2006.245.07:52:14.60#ibcon#*before return 0, iclass 6, count 0 2006.245.07:52:14.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:14.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.07:52:14.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:52:14.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:52:14.61$vc4f8/vblo=6,752.99 2006.245.07:52:14.61#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.07:52:14.61#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.07:52:14.61#ibcon#ireg 17 cls_cnt 0 2006.245.07:52:14.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:14.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:14.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:14.61#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:52:14.61#ibcon#first serial, iclass 10, count 0 2006.245.07:52:14.61#ibcon#enter sib2, iclass 10, count 0 2006.245.07:52:14.61#ibcon#flushed, iclass 10, count 0 2006.245.07:52:14.61#ibcon#about to write, iclass 10, count 0 2006.245.07:52:14.61#ibcon#wrote, iclass 10, count 0 2006.245.07:52:14.61#ibcon#about to read 3, iclass 10, count 0 2006.245.07:52:14.62#ibcon#read 3, iclass 10, count 0 2006.245.07:52:14.62#ibcon#about to read 4, iclass 10, count 0 2006.245.07:52:14.62#ibcon#read 4, iclass 10, count 0 2006.245.07:52:14.62#ibcon#about to read 5, iclass 10, count 0 2006.245.07:52:14.62#ibcon#read 5, iclass 10, count 0 2006.245.07:52:14.62#ibcon#about to read 6, iclass 10, count 0 2006.245.07:52:14.62#ibcon#read 6, iclass 10, count 0 2006.245.07:52:14.62#ibcon#end of sib2, iclass 10, count 0 2006.245.07:52:14.62#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:52:14.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:52:14.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:52:14.62#ibcon#*before write, iclass 10, count 0 2006.245.07:52:14.62#ibcon#enter sib2, iclass 10, count 0 2006.245.07:52:14.62#ibcon#flushed, iclass 10, count 0 2006.245.07:52:14.62#ibcon#about to write, iclass 10, count 0 2006.245.07:52:14.62#ibcon#wrote, iclass 10, count 0 2006.245.07:52:14.62#ibcon#about to read 3, iclass 10, count 0 2006.245.07:52:14.66#ibcon#read 3, iclass 10, count 0 2006.245.07:52:14.66#ibcon#about to read 4, iclass 10, count 0 2006.245.07:52:14.66#ibcon#read 4, iclass 10, count 0 2006.245.07:52:14.66#ibcon#about to read 5, iclass 10, count 0 2006.245.07:52:14.66#ibcon#read 5, iclass 10, count 0 2006.245.07:52:14.66#ibcon#about to read 6, iclass 10, count 0 2006.245.07:52:14.66#ibcon#read 6, iclass 10, count 0 2006.245.07:52:14.66#ibcon#end of sib2, iclass 10, count 0 2006.245.07:52:14.66#ibcon#*after write, iclass 10, count 0 2006.245.07:52:14.66#ibcon#*before return 0, iclass 10, count 0 2006.245.07:52:14.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:14.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.07:52:14.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:52:14.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:52:14.67$vc4f8/vb=6,3 2006.245.07:52:14.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.07:52:14.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.07:52:14.67#ibcon#ireg 11 cls_cnt 2 2006.245.07:52:14.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:14.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:14.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:14.71#ibcon#enter wrdev, iclass 12, count 2 2006.245.07:52:14.71#ibcon#first serial, iclass 12, count 2 2006.245.07:52:14.71#ibcon#enter sib2, iclass 12, count 2 2006.245.07:52:14.71#ibcon#flushed, iclass 12, count 2 2006.245.07:52:14.71#ibcon#about to write, iclass 12, count 2 2006.245.07:52:14.71#ibcon#wrote, iclass 12, count 2 2006.245.07:52:14.71#ibcon#about to read 3, iclass 12, count 2 2006.245.07:52:14.74#ibcon#read 3, iclass 12, count 2 2006.245.07:52:14.74#ibcon#about to read 4, iclass 12, count 2 2006.245.07:52:14.74#ibcon#read 4, iclass 12, count 2 2006.245.07:52:14.74#ibcon#about to read 5, iclass 12, count 2 2006.245.07:52:14.74#ibcon#read 5, iclass 12, count 2 2006.245.07:52:14.74#ibcon#about to read 6, iclass 12, count 2 2006.245.07:52:14.74#ibcon#read 6, iclass 12, count 2 2006.245.07:52:14.74#ibcon#end of sib2, iclass 12, count 2 2006.245.07:52:14.74#ibcon#*mode == 0, iclass 12, count 2 2006.245.07:52:14.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.07:52:14.74#ibcon#[27=AT06-03\r\n] 2006.245.07:52:14.74#ibcon#*before write, iclass 12, count 2 2006.245.07:52:14.74#ibcon#enter sib2, iclass 12, count 2 2006.245.07:52:14.74#ibcon#flushed, iclass 12, count 2 2006.245.07:52:14.74#ibcon#about to write, iclass 12, count 2 2006.245.07:52:14.74#ibcon#wrote, iclass 12, count 2 2006.245.07:52:14.74#ibcon#about to read 3, iclass 12, count 2 2006.245.07:52:14.77#ibcon#read 3, iclass 12, count 2 2006.245.07:52:14.77#ibcon#about to read 4, iclass 12, count 2 2006.245.07:52:14.77#ibcon#read 4, iclass 12, count 2 2006.245.07:52:14.77#ibcon#about to read 5, iclass 12, count 2 2006.245.07:52:14.77#ibcon#read 5, iclass 12, count 2 2006.245.07:52:14.77#ibcon#about to read 6, iclass 12, count 2 2006.245.07:52:14.77#ibcon#read 6, iclass 12, count 2 2006.245.07:52:14.77#ibcon#end of sib2, iclass 12, count 2 2006.245.07:52:14.77#ibcon#*after write, iclass 12, count 2 2006.245.07:52:14.77#ibcon#*before return 0, iclass 12, count 2 2006.245.07:52:14.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:14.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.07:52:14.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.07:52:14.77#ibcon#ireg 7 cls_cnt 0 2006.245.07:52:14.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:14.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:14.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:14.89#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:52:14.89#ibcon#first serial, iclass 12, count 0 2006.245.07:52:14.89#ibcon#enter sib2, iclass 12, count 0 2006.245.07:52:14.89#ibcon#flushed, iclass 12, count 0 2006.245.07:52:14.89#ibcon#about to write, iclass 12, count 0 2006.245.07:52:14.89#ibcon#wrote, iclass 12, count 0 2006.245.07:52:14.89#ibcon#about to read 3, iclass 12, count 0 2006.245.07:52:14.91#ibcon#read 3, iclass 12, count 0 2006.245.07:52:14.91#ibcon#about to read 4, iclass 12, count 0 2006.245.07:52:14.91#ibcon#read 4, iclass 12, count 0 2006.245.07:52:14.91#ibcon#about to read 5, iclass 12, count 0 2006.245.07:52:14.91#ibcon#read 5, iclass 12, count 0 2006.245.07:52:14.91#ibcon#about to read 6, iclass 12, count 0 2006.245.07:52:14.91#ibcon#read 6, iclass 12, count 0 2006.245.07:52:14.91#ibcon#end of sib2, iclass 12, count 0 2006.245.07:52:14.91#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:52:14.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:52:14.91#ibcon#[27=USB\r\n] 2006.245.07:52:14.91#ibcon#*before write, iclass 12, count 0 2006.245.07:52:14.91#ibcon#enter sib2, iclass 12, count 0 2006.245.07:52:14.91#ibcon#flushed, iclass 12, count 0 2006.245.07:52:14.91#ibcon#about to write, iclass 12, count 0 2006.245.07:52:14.91#ibcon#wrote, iclass 12, count 0 2006.245.07:52:14.91#ibcon#about to read 3, iclass 12, count 0 2006.245.07:52:14.94#ibcon#read 3, iclass 12, count 0 2006.245.07:52:14.94#ibcon#about to read 4, iclass 12, count 0 2006.245.07:52:14.94#ibcon#read 4, iclass 12, count 0 2006.245.07:52:14.94#ibcon#about to read 5, iclass 12, count 0 2006.245.07:52:14.94#ibcon#read 5, iclass 12, count 0 2006.245.07:52:14.94#ibcon#about to read 6, iclass 12, count 0 2006.245.07:52:14.94#ibcon#read 6, iclass 12, count 0 2006.245.07:52:14.94#ibcon#end of sib2, iclass 12, count 0 2006.245.07:52:14.94#ibcon#*after write, iclass 12, count 0 2006.245.07:52:14.94#ibcon#*before return 0, iclass 12, count 0 2006.245.07:52:14.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:14.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.07:52:14.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:52:14.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:52:14.95$vc4f8/vabw=wide 2006.245.07:52:14.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.07:52:14.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.07:52:14.95#ibcon#ireg 8 cls_cnt 0 2006.245.07:52:14.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:14.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:14.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:14.95#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:52:14.95#ibcon#first serial, iclass 14, count 0 2006.245.07:52:14.95#ibcon#enter sib2, iclass 14, count 0 2006.245.07:52:14.95#ibcon#flushed, iclass 14, count 0 2006.245.07:52:14.95#ibcon#about to write, iclass 14, count 0 2006.245.07:52:14.95#ibcon#wrote, iclass 14, count 0 2006.245.07:52:14.95#ibcon#about to read 3, iclass 14, count 0 2006.245.07:52:14.96#ibcon#read 3, iclass 14, count 0 2006.245.07:52:14.96#ibcon#about to read 4, iclass 14, count 0 2006.245.07:52:14.96#ibcon#read 4, iclass 14, count 0 2006.245.07:52:14.96#ibcon#about to read 5, iclass 14, count 0 2006.245.07:52:14.96#ibcon#read 5, iclass 14, count 0 2006.245.07:52:14.96#ibcon#about to read 6, iclass 14, count 0 2006.245.07:52:14.96#ibcon#read 6, iclass 14, count 0 2006.245.07:52:14.96#ibcon#end of sib2, iclass 14, count 0 2006.245.07:52:14.96#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:52:14.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:52:14.96#ibcon#[25=BW32\r\n] 2006.245.07:52:14.96#ibcon#*before write, iclass 14, count 0 2006.245.07:52:14.96#ibcon#enter sib2, iclass 14, count 0 2006.245.07:52:14.96#ibcon#flushed, iclass 14, count 0 2006.245.07:52:14.96#ibcon#about to write, iclass 14, count 0 2006.245.07:52:14.96#ibcon#wrote, iclass 14, count 0 2006.245.07:52:14.96#ibcon#about to read 3, iclass 14, count 0 2006.245.07:52:14.99#ibcon#read 3, iclass 14, count 0 2006.245.07:52:14.99#ibcon#about to read 4, iclass 14, count 0 2006.245.07:52:14.99#ibcon#read 4, iclass 14, count 0 2006.245.07:52:14.99#ibcon#about to read 5, iclass 14, count 0 2006.245.07:52:14.99#ibcon#read 5, iclass 14, count 0 2006.245.07:52:14.99#ibcon#about to read 6, iclass 14, count 0 2006.245.07:52:14.99#ibcon#read 6, iclass 14, count 0 2006.245.07:52:14.99#ibcon#end of sib2, iclass 14, count 0 2006.245.07:52:14.99#ibcon#*after write, iclass 14, count 0 2006.245.07:52:14.99#ibcon#*before return 0, iclass 14, count 0 2006.245.07:52:14.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:14.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.07:52:14.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:52:14.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:52:15.00$vc4f8/vbbw=wide 2006.245.07:52:15.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:52:15.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:52:15.00#ibcon#ireg 8 cls_cnt 0 2006.245.07:52:15.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:52:15.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:52:15.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:52:15.05#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:52:15.05#ibcon#first serial, iclass 16, count 0 2006.245.07:52:15.05#ibcon#enter sib2, iclass 16, count 0 2006.245.07:52:15.05#ibcon#flushed, iclass 16, count 0 2006.245.07:52:15.05#ibcon#about to write, iclass 16, count 0 2006.245.07:52:15.05#ibcon#wrote, iclass 16, count 0 2006.245.07:52:15.05#ibcon#about to read 3, iclass 16, count 0 2006.245.07:52:15.07#ibcon#read 3, iclass 16, count 0 2006.245.07:52:15.07#ibcon#about to read 4, iclass 16, count 0 2006.245.07:52:15.07#ibcon#read 4, iclass 16, count 0 2006.245.07:52:15.07#ibcon#about to read 5, iclass 16, count 0 2006.245.07:52:15.07#ibcon#read 5, iclass 16, count 0 2006.245.07:52:15.07#ibcon#about to read 6, iclass 16, count 0 2006.245.07:52:15.07#ibcon#read 6, iclass 16, count 0 2006.245.07:52:15.07#ibcon#end of sib2, iclass 16, count 0 2006.245.07:52:15.07#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:52:15.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:52:15.07#ibcon#[27=BW32\r\n] 2006.245.07:52:15.07#ibcon#*before write, iclass 16, count 0 2006.245.07:52:15.07#ibcon#enter sib2, iclass 16, count 0 2006.245.07:52:15.07#ibcon#flushed, iclass 16, count 0 2006.245.07:52:15.07#ibcon#about to write, iclass 16, count 0 2006.245.07:52:15.07#ibcon#wrote, iclass 16, count 0 2006.245.07:52:15.07#ibcon#about to read 3, iclass 16, count 0 2006.245.07:52:15.10#ibcon#read 3, iclass 16, count 0 2006.245.07:52:15.10#ibcon#about to read 4, iclass 16, count 0 2006.245.07:52:15.10#ibcon#read 4, iclass 16, count 0 2006.245.07:52:15.10#ibcon#about to read 5, iclass 16, count 0 2006.245.07:52:15.10#ibcon#read 5, iclass 16, count 0 2006.245.07:52:15.10#ibcon#about to read 6, iclass 16, count 0 2006.245.07:52:15.10#ibcon#read 6, iclass 16, count 0 2006.245.07:52:15.10#ibcon#end of sib2, iclass 16, count 0 2006.245.07:52:15.10#ibcon#*after write, iclass 16, count 0 2006.245.07:52:15.10#ibcon#*before return 0, iclass 16, count 0 2006.245.07:52:15.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:52:15.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:52:15.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:52:15.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:52:15.11$4f8m12a/ifd4f 2006.245.07:52:15.11$ifd4f/lo= 2006.245.07:52:15.11$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:52:15.11$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:52:15.11$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:52:15.11$ifd4f/patch= 2006.245.07:52:15.11$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:52:15.11$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:52:15.11$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:52:15.11$4f8m12a/"form=m,16.000,1:2 2006.245.07:52:15.11$4f8m12a/"tpicd 2006.245.07:52:15.11$4f8m12a/echo=off 2006.245.07:52:15.11$4f8m12a/xlog=off 2006.245.07:52:15.11:!2006.245.07:52:40 2006.245.07:52:22.14#trakl#Source acquired 2006.245.07:52:22.15#flagr#flagr/antenna,acquired 2006.245.07:52:40.02:preob 2006.245.07:52:41.15/onsource/TRACKING 2006.245.07:52:41.15:!2006.245.07:52:50 2006.245.07:52:50.02:data_valid=on 2006.245.07:52:50.02:midob 2006.245.07:52:51.15/onsource/TRACKING 2006.245.07:52:51.15/wx/27.32,1004.5,69 2006.245.07:52:51.21/cable/+6.4091E-03 2006.245.07:52:52.30/va/01,08,usb,yes,31,33 2006.245.07:52:52.30/va/02,07,usb,yes,31,32 2006.245.07:52:52.30/va/03,06,usb,yes,33,33 2006.245.07:52:52.30/va/04,07,usb,yes,32,35 2006.245.07:52:52.30/va/05,07,usb,yes,33,35 2006.245.07:52:52.30/va/06,07,usb,yes,29,29 2006.245.07:52:52.30/va/07,07,usb,yes,29,29 2006.245.07:52:52.30/va/08,08,usb,yes,25,25 2006.245.07:52:52.53/valo/01,532.99,yes,locked 2006.245.07:52:52.53/valo/02,572.99,yes,locked 2006.245.07:52:52.53/valo/03,672.99,yes,locked 2006.245.07:52:52.53/valo/04,832.99,yes,locked 2006.245.07:52:52.53/valo/05,652.99,yes,locked 2006.245.07:52:52.53/valo/06,772.99,yes,locked 2006.245.07:52:52.53/valo/07,832.99,yes,locked 2006.245.07:52:52.53/valo/08,852.99,yes,locked 2006.245.07:52:53.62/vb/01,04,usb,yes,31,29 2006.245.07:52:53.62/vb/02,04,usb,yes,32,34 2006.245.07:52:53.62/vb/03,04,usb,yes,29,33 2006.245.07:52:53.62/vb/04,04,usb,yes,30,30 2006.245.07:52:53.62/vb/05,03,usb,yes,35,40 2006.245.07:52:53.62/vb/06,03,usb,yes,36,39 2006.245.07:52:53.62/vb/07,04,usb,yes,31,31 2006.245.07:52:53.62/vb/08,03,usb,yes,36,40 2006.245.07:52:53.85/vblo/01,632.99,yes,locked 2006.245.07:52:53.85/vblo/02,640.99,yes,locked 2006.245.07:52:53.85/vblo/03,656.99,yes,locked 2006.245.07:52:53.85/vblo/04,712.99,yes,locked 2006.245.07:52:53.85/vblo/05,744.99,yes,locked 2006.245.07:52:53.85/vblo/06,752.99,yes,locked 2006.245.07:52:53.85/vblo/07,734.99,yes,locked 2006.245.07:52:53.85/vblo/08,744.99,yes,locked 2006.245.07:52:54.00/vabw/8 2006.245.07:52:54.15/vbbw/8 2006.245.07:52:54.24/xfe/off,on,13.0 2006.245.07:52:54.61/ifatt/23,28,28,28 2006.245.07:52:55.07/fmout-gps/S +4.40E-07 2006.245.07:52:55.12:!2006.245.07:53:50 2006.245.07:53:50.02:data_valid=off 2006.245.07:53:50.02:postob 2006.245.07:53:50.13/cable/+6.4095E-03 2006.245.07:53:50.14/wx/27.30,1004.5,70 2006.245.07:53:51.07/fmout-gps/S +4.39E-07 2006.245.07:53:51.08:scan_name=245-0755,k06245,60 2006.245.07:53:51.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.245.07:53:52.13#flagr#flagr/antenna,new-source 2006.245.07:53:52.14:checkk5 2006.245.07:53:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:53:53.04/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:53:53.51/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:53:53.98/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:53:54.69/chk_obsdata//k5ts1/T2450752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:53:55.24/chk_obsdata//k5ts2/T2450752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:53:55.68/chk_obsdata//k5ts3/T2450752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:53:56.17/chk_obsdata//k5ts4/T2450752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:53:57.48/k5log//k5ts1_log_newline 2006.245.07:53:58.56/k5log//k5ts2_log_newline 2006.245.07:53:59.54/k5log//k5ts3_log_newline 2006.245.07:54:00.57/k5log//k5ts4_log_newline 2006.245.07:54:00.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:54:00.60:4f8m12a=2 2006.245.07:54:00.60$4f8m12a/echo=on 2006.245.07:54:00.60$4f8m12a/pcalon 2006.245.07:54:00.60$pcalon/"no phase cal control is implemented here 2006.245.07:54:00.60$4f8m12a/"tpicd=stop 2006.245.07:54:00.60$4f8m12a/vc4f8 2006.245.07:54:00.60$vc4f8/valo=1,532.99 2006.245.07:54:00.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:54:00.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:54:00.61#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:00.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:00.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:00.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:00.61#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:54:00.61#ibcon#first serial, iclass 27, count 0 2006.245.07:54:00.61#ibcon#enter sib2, iclass 27, count 0 2006.245.07:54:00.61#ibcon#flushed, iclass 27, count 0 2006.245.07:54:00.61#ibcon#about to write, iclass 27, count 0 2006.245.07:54:00.61#ibcon#wrote, iclass 27, count 0 2006.245.07:54:00.61#ibcon#about to read 3, iclass 27, count 0 2006.245.07:54:00.64#ibcon#read 3, iclass 27, count 0 2006.245.07:54:00.64#ibcon#about to read 4, iclass 27, count 0 2006.245.07:54:00.64#ibcon#read 4, iclass 27, count 0 2006.245.07:54:00.64#ibcon#about to read 5, iclass 27, count 0 2006.245.07:54:00.64#ibcon#read 5, iclass 27, count 0 2006.245.07:54:00.64#ibcon#about to read 6, iclass 27, count 0 2006.245.07:54:00.64#ibcon#read 6, iclass 27, count 0 2006.245.07:54:00.64#ibcon#end of sib2, iclass 27, count 0 2006.245.07:54:00.64#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:54:00.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:54:00.64#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:54:00.64#ibcon#*before write, iclass 27, count 0 2006.245.07:54:00.64#ibcon#enter sib2, iclass 27, count 0 2006.245.07:54:00.64#ibcon#flushed, iclass 27, count 0 2006.245.07:54:00.64#ibcon#about to write, iclass 27, count 0 2006.245.07:54:00.64#ibcon#wrote, iclass 27, count 0 2006.245.07:54:00.64#ibcon#about to read 3, iclass 27, count 0 2006.245.07:54:00.69#ibcon#read 3, iclass 27, count 0 2006.245.07:54:00.69#ibcon#about to read 4, iclass 27, count 0 2006.245.07:54:00.69#ibcon#read 4, iclass 27, count 0 2006.245.07:54:00.69#ibcon#about to read 5, iclass 27, count 0 2006.245.07:54:00.69#ibcon#read 5, iclass 27, count 0 2006.245.07:54:00.69#ibcon#about to read 6, iclass 27, count 0 2006.245.07:54:00.69#ibcon#read 6, iclass 27, count 0 2006.245.07:54:00.69#ibcon#end of sib2, iclass 27, count 0 2006.245.07:54:00.69#ibcon#*after write, iclass 27, count 0 2006.245.07:54:00.69#ibcon#*before return 0, iclass 27, count 0 2006.245.07:54:00.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:00.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:00.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:54:00.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:54:00.69$vc4f8/va=1,8 2006.245.07:54:00.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:54:00.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:54:00.69#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:00.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:00.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:00.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:00.69#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:54:00.69#ibcon#first serial, iclass 29, count 2 2006.245.07:54:00.69#ibcon#enter sib2, iclass 29, count 2 2006.245.07:54:00.69#ibcon#flushed, iclass 29, count 2 2006.245.07:54:00.69#ibcon#about to write, iclass 29, count 2 2006.245.07:54:00.69#ibcon#wrote, iclass 29, count 2 2006.245.07:54:00.70#ibcon#about to read 3, iclass 29, count 2 2006.245.07:54:00.72#ibcon#read 3, iclass 29, count 2 2006.245.07:54:00.72#ibcon#about to read 4, iclass 29, count 2 2006.245.07:54:00.72#ibcon#read 4, iclass 29, count 2 2006.245.07:54:00.72#ibcon#about to read 5, iclass 29, count 2 2006.245.07:54:00.72#ibcon#read 5, iclass 29, count 2 2006.245.07:54:00.72#ibcon#about to read 6, iclass 29, count 2 2006.245.07:54:00.72#ibcon#read 6, iclass 29, count 2 2006.245.07:54:00.72#ibcon#end of sib2, iclass 29, count 2 2006.245.07:54:00.72#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:54:00.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:54:00.72#ibcon#[25=AT01-08\r\n] 2006.245.07:54:00.72#ibcon#*before write, iclass 29, count 2 2006.245.07:54:00.72#ibcon#enter sib2, iclass 29, count 2 2006.245.07:54:00.72#ibcon#flushed, iclass 29, count 2 2006.245.07:54:00.72#ibcon#about to write, iclass 29, count 2 2006.245.07:54:00.72#ibcon#wrote, iclass 29, count 2 2006.245.07:54:00.72#ibcon#about to read 3, iclass 29, count 2 2006.245.07:54:00.75#ibcon#read 3, iclass 29, count 2 2006.245.07:54:00.75#ibcon#about to read 4, iclass 29, count 2 2006.245.07:54:00.75#ibcon#read 4, iclass 29, count 2 2006.245.07:54:00.75#ibcon#about to read 5, iclass 29, count 2 2006.245.07:54:00.75#ibcon#read 5, iclass 29, count 2 2006.245.07:54:00.75#ibcon#about to read 6, iclass 29, count 2 2006.245.07:54:00.75#ibcon#read 6, iclass 29, count 2 2006.245.07:54:00.75#ibcon#end of sib2, iclass 29, count 2 2006.245.07:54:00.75#ibcon#*after write, iclass 29, count 2 2006.245.07:54:00.75#ibcon#*before return 0, iclass 29, count 2 2006.245.07:54:00.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:00.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:00.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:54:00.75#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:00.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:00.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:00.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:00.87#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:54:00.87#ibcon#first serial, iclass 29, count 0 2006.245.07:54:00.87#ibcon#enter sib2, iclass 29, count 0 2006.245.07:54:00.87#ibcon#flushed, iclass 29, count 0 2006.245.07:54:00.87#ibcon#about to write, iclass 29, count 0 2006.245.07:54:00.87#ibcon#wrote, iclass 29, count 0 2006.245.07:54:00.87#ibcon#about to read 3, iclass 29, count 0 2006.245.07:54:00.89#ibcon#read 3, iclass 29, count 0 2006.245.07:54:00.89#ibcon#about to read 4, iclass 29, count 0 2006.245.07:54:00.89#ibcon#read 4, iclass 29, count 0 2006.245.07:54:00.89#ibcon#about to read 5, iclass 29, count 0 2006.245.07:54:00.89#ibcon#read 5, iclass 29, count 0 2006.245.07:54:00.89#ibcon#about to read 6, iclass 29, count 0 2006.245.07:54:00.89#ibcon#read 6, iclass 29, count 0 2006.245.07:54:00.89#ibcon#end of sib2, iclass 29, count 0 2006.245.07:54:00.89#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:54:00.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:54:00.89#ibcon#[25=USB\r\n] 2006.245.07:54:00.89#ibcon#*before write, iclass 29, count 0 2006.245.07:54:00.89#ibcon#enter sib2, iclass 29, count 0 2006.245.07:54:00.89#ibcon#flushed, iclass 29, count 0 2006.245.07:54:00.89#ibcon#about to write, iclass 29, count 0 2006.245.07:54:00.89#ibcon#wrote, iclass 29, count 0 2006.245.07:54:00.89#ibcon#about to read 3, iclass 29, count 0 2006.245.07:54:00.92#ibcon#read 3, iclass 29, count 0 2006.245.07:54:00.92#ibcon#about to read 4, iclass 29, count 0 2006.245.07:54:00.92#ibcon#read 4, iclass 29, count 0 2006.245.07:54:00.92#ibcon#about to read 5, iclass 29, count 0 2006.245.07:54:00.92#ibcon#read 5, iclass 29, count 0 2006.245.07:54:00.92#ibcon#about to read 6, iclass 29, count 0 2006.245.07:54:00.92#ibcon#read 6, iclass 29, count 0 2006.245.07:54:00.92#ibcon#end of sib2, iclass 29, count 0 2006.245.07:54:00.92#ibcon#*after write, iclass 29, count 0 2006.245.07:54:00.92#ibcon#*before return 0, iclass 29, count 0 2006.245.07:54:00.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:00.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:00.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:54:00.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:54:00.92$vc4f8/valo=2,572.99 2006.245.07:54:00.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:54:00.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:54:00.92#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:00.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:00.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:00.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:00.92#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:54:00.92#ibcon#first serial, iclass 31, count 0 2006.245.07:54:00.92#ibcon#enter sib2, iclass 31, count 0 2006.245.07:54:00.92#ibcon#flushed, iclass 31, count 0 2006.245.07:54:00.92#ibcon#about to write, iclass 31, count 0 2006.245.07:54:00.93#ibcon#wrote, iclass 31, count 0 2006.245.07:54:00.93#ibcon#about to read 3, iclass 31, count 0 2006.245.07:54:00.94#ibcon#read 3, iclass 31, count 0 2006.245.07:54:00.94#ibcon#about to read 4, iclass 31, count 0 2006.245.07:54:00.94#ibcon#read 4, iclass 31, count 0 2006.245.07:54:00.94#ibcon#about to read 5, iclass 31, count 0 2006.245.07:54:00.94#ibcon#read 5, iclass 31, count 0 2006.245.07:54:00.94#ibcon#about to read 6, iclass 31, count 0 2006.245.07:54:00.94#ibcon#read 6, iclass 31, count 0 2006.245.07:54:00.94#ibcon#end of sib2, iclass 31, count 0 2006.245.07:54:00.94#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:54:00.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:54:00.94#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:54:00.94#ibcon#*before write, iclass 31, count 0 2006.245.07:54:00.94#ibcon#enter sib2, iclass 31, count 0 2006.245.07:54:00.94#ibcon#flushed, iclass 31, count 0 2006.245.07:54:00.94#ibcon#about to write, iclass 31, count 0 2006.245.07:54:00.94#ibcon#wrote, iclass 31, count 0 2006.245.07:54:00.94#ibcon#about to read 3, iclass 31, count 0 2006.245.07:54:00.98#ibcon#read 3, iclass 31, count 0 2006.245.07:54:00.98#ibcon#about to read 4, iclass 31, count 0 2006.245.07:54:00.98#ibcon#read 4, iclass 31, count 0 2006.245.07:54:00.98#ibcon#about to read 5, iclass 31, count 0 2006.245.07:54:00.98#ibcon#read 5, iclass 31, count 0 2006.245.07:54:00.98#ibcon#about to read 6, iclass 31, count 0 2006.245.07:54:00.98#ibcon#read 6, iclass 31, count 0 2006.245.07:54:00.98#ibcon#end of sib2, iclass 31, count 0 2006.245.07:54:00.98#ibcon#*after write, iclass 31, count 0 2006.245.07:54:00.98#ibcon#*before return 0, iclass 31, count 0 2006.245.07:54:00.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:00.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:00.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:54:00.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:54:00.98$vc4f8/va=2,7 2006.245.07:54:00.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:54:00.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:54:00.98#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:00.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:01.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:01.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:01.05#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:54:01.05#ibcon#first serial, iclass 33, count 2 2006.245.07:54:01.05#ibcon#enter sib2, iclass 33, count 2 2006.245.07:54:01.05#ibcon#flushed, iclass 33, count 2 2006.245.07:54:01.05#ibcon#about to write, iclass 33, count 2 2006.245.07:54:01.05#ibcon#wrote, iclass 33, count 2 2006.245.07:54:01.05#ibcon#about to read 3, iclass 33, count 2 2006.245.07:54:01.07#ibcon#read 3, iclass 33, count 2 2006.245.07:54:01.07#ibcon#about to read 4, iclass 33, count 2 2006.245.07:54:01.07#ibcon#read 4, iclass 33, count 2 2006.245.07:54:01.07#ibcon#about to read 5, iclass 33, count 2 2006.245.07:54:01.07#ibcon#read 5, iclass 33, count 2 2006.245.07:54:01.07#ibcon#about to read 6, iclass 33, count 2 2006.245.07:54:01.07#ibcon#read 6, iclass 33, count 2 2006.245.07:54:01.07#ibcon#end of sib2, iclass 33, count 2 2006.245.07:54:01.07#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:54:01.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:54:01.07#ibcon#[25=AT02-07\r\n] 2006.245.07:54:01.07#ibcon#*before write, iclass 33, count 2 2006.245.07:54:01.07#ibcon#enter sib2, iclass 33, count 2 2006.245.07:54:01.07#ibcon#flushed, iclass 33, count 2 2006.245.07:54:01.07#ibcon#about to write, iclass 33, count 2 2006.245.07:54:01.07#ibcon#wrote, iclass 33, count 2 2006.245.07:54:01.07#ibcon#about to read 3, iclass 33, count 2 2006.245.07:54:01.09#ibcon#read 3, iclass 33, count 2 2006.245.07:54:01.09#ibcon#about to read 4, iclass 33, count 2 2006.245.07:54:01.09#ibcon#read 4, iclass 33, count 2 2006.245.07:54:01.09#ibcon#about to read 5, iclass 33, count 2 2006.245.07:54:01.09#ibcon#read 5, iclass 33, count 2 2006.245.07:54:01.09#ibcon#about to read 6, iclass 33, count 2 2006.245.07:54:01.09#ibcon#read 6, iclass 33, count 2 2006.245.07:54:01.09#ibcon#end of sib2, iclass 33, count 2 2006.245.07:54:01.09#ibcon#*after write, iclass 33, count 2 2006.245.07:54:01.09#ibcon#*before return 0, iclass 33, count 2 2006.245.07:54:01.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:01.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:01.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:54:01.09#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:01.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:01.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:01.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:01.21#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:54:01.21#ibcon#first serial, iclass 33, count 0 2006.245.07:54:01.21#ibcon#enter sib2, iclass 33, count 0 2006.245.07:54:01.21#ibcon#flushed, iclass 33, count 0 2006.245.07:54:01.21#ibcon#about to write, iclass 33, count 0 2006.245.07:54:01.21#ibcon#wrote, iclass 33, count 0 2006.245.07:54:01.21#ibcon#about to read 3, iclass 33, count 0 2006.245.07:54:01.25#ibcon#read 3, iclass 33, count 0 2006.245.07:54:01.25#ibcon#about to read 4, iclass 33, count 0 2006.245.07:54:01.25#ibcon#read 4, iclass 33, count 0 2006.245.07:54:01.25#ibcon#about to read 5, iclass 33, count 0 2006.245.07:54:01.25#ibcon#read 5, iclass 33, count 0 2006.245.07:54:01.25#ibcon#about to read 6, iclass 33, count 0 2006.245.07:54:01.25#ibcon#read 6, iclass 33, count 0 2006.245.07:54:01.25#ibcon#end of sib2, iclass 33, count 0 2006.245.07:54:01.25#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:54:01.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:54:01.25#ibcon#[25=USB\r\n] 2006.245.07:54:01.25#ibcon#*before write, iclass 33, count 0 2006.245.07:54:01.25#ibcon#enter sib2, iclass 33, count 0 2006.245.07:54:01.25#ibcon#flushed, iclass 33, count 0 2006.245.07:54:01.25#ibcon#about to write, iclass 33, count 0 2006.245.07:54:01.25#ibcon#wrote, iclass 33, count 0 2006.245.07:54:01.25#ibcon#about to read 3, iclass 33, count 0 2006.245.07:54:01.27#ibcon#read 3, iclass 33, count 0 2006.245.07:54:01.27#ibcon#about to read 4, iclass 33, count 0 2006.245.07:54:01.27#ibcon#read 4, iclass 33, count 0 2006.245.07:54:01.27#ibcon#about to read 5, iclass 33, count 0 2006.245.07:54:01.27#ibcon#read 5, iclass 33, count 0 2006.245.07:54:01.27#ibcon#about to read 6, iclass 33, count 0 2006.245.07:54:01.27#ibcon#read 6, iclass 33, count 0 2006.245.07:54:01.27#ibcon#end of sib2, iclass 33, count 0 2006.245.07:54:01.27#ibcon#*after write, iclass 33, count 0 2006.245.07:54:01.27#ibcon#*before return 0, iclass 33, count 0 2006.245.07:54:01.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:01.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:01.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:54:01.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:54:01.27$vc4f8/valo=3,672.99 2006.245.07:54:01.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:54:01.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:54:01.27#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:01.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:01.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:01.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:01.27#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:54:01.27#ibcon#first serial, iclass 35, count 0 2006.245.07:54:01.27#ibcon#enter sib2, iclass 35, count 0 2006.245.07:54:01.27#ibcon#flushed, iclass 35, count 0 2006.245.07:54:01.27#ibcon#about to write, iclass 35, count 0 2006.245.07:54:01.28#ibcon#wrote, iclass 35, count 0 2006.245.07:54:01.28#ibcon#about to read 3, iclass 35, count 0 2006.245.07:54:01.29#ibcon#read 3, iclass 35, count 0 2006.245.07:54:01.29#ibcon#about to read 4, iclass 35, count 0 2006.245.07:54:01.29#ibcon#read 4, iclass 35, count 0 2006.245.07:54:01.29#ibcon#about to read 5, iclass 35, count 0 2006.245.07:54:01.29#ibcon#read 5, iclass 35, count 0 2006.245.07:54:01.29#ibcon#about to read 6, iclass 35, count 0 2006.245.07:54:01.29#ibcon#read 6, iclass 35, count 0 2006.245.07:54:01.29#ibcon#end of sib2, iclass 35, count 0 2006.245.07:54:01.29#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:54:01.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:54:01.29#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:54:01.29#ibcon#*before write, iclass 35, count 0 2006.245.07:54:01.29#ibcon#enter sib2, iclass 35, count 0 2006.245.07:54:01.29#ibcon#flushed, iclass 35, count 0 2006.245.07:54:01.29#ibcon#about to write, iclass 35, count 0 2006.245.07:54:01.29#ibcon#wrote, iclass 35, count 0 2006.245.07:54:01.29#ibcon#about to read 3, iclass 35, count 0 2006.245.07:54:01.34#ibcon#read 3, iclass 35, count 0 2006.245.07:54:01.34#ibcon#about to read 4, iclass 35, count 0 2006.245.07:54:01.34#ibcon#read 4, iclass 35, count 0 2006.245.07:54:01.34#ibcon#about to read 5, iclass 35, count 0 2006.245.07:54:01.34#ibcon#read 5, iclass 35, count 0 2006.245.07:54:01.34#ibcon#about to read 6, iclass 35, count 0 2006.245.07:54:01.34#ibcon#read 6, iclass 35, count 0 2006.245.07:54:01.34#ibcon#end of sib2, iclass 35, count 0 2006.245.07:54:01.34#ibcon#*after write, iclass 35, count 0 2006.245.07:54:01.34#ibcon#*before return 0, iclass 35, count 0 2006.245.07:54:01.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:01.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:01.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:54:01.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:54:01.34$vc4f8/va=3,6 2006.245.07:54:01.34#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:54:01.34#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:54:01.34#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:01.34#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:01.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:01.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:01.38#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:54:01.38#ibcon#first serial, iclass 37, count 2 2006.245.07:54:01.38#ibcon#enter sib2, iclass 37, count 2 2006.245.07:54:01.38#ibcon#flushed, iclass 37, count 2 2006.245.07:54:01.38#ibcon#about to write, iclass 37, count 2 2006.245.07:54:01.38#ibcon#wrote, iclass 37, count 2 2006.245.07:54:01.38#ibcon#about to read 3, iclass 37, count 2 2006.245.07:54:01.40#ibcon#read 3, iclass 37, count 2 2006.245.07:54:01.40#ibcon#about to read 4, iclass 37, count 2 2006.245.07:54:01.40#ibcon#read 4, iclass 37, count 2 2006.245.07:54:01.40#ibcon#about to read 5, iclass 37, count 2 2006.245.07:54:01.40#ibcon#read 5, iclass 37, count 2 2006.245.07:54:01.40#ibcon#about to read 6, iclass 37, count 2 2006.245.07:54:01.40#ibcon#read 6, iclass 37, count 2 2006.245.07:54:01.40#ibcon#end of sib2, iclass 37, count 2 2006.245.07:54:01.40#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:54:01.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:54:01.40#ibcon#[25=AT03-06\r\n] 2006.245.07:54:01.40#ibcon#*before write, iclass 37, count 2 2006.245.07:54:01.40#ibcon#enter sib2, iclass 37, count 2 2006.245.07:54:01.40#ibcon#flushed, iclass 37, count 2 2006.245.07:54:01.40#ibcon#about to write, iclass 37, count 2 2006.245.07:54:01.40#ibcon#wrote, iclass 37, count 2 2006.245.07:54:01.40#ibcon#about to read 3, iclass 37, count 2 2006.245.07:54:01.44#ibcon#read 3, iclass 37, count 2 2006.245.07:54:01.44#ibcon#about to read 4, iclass 37, count 2 2006.245.07:54:01.44#ibcon#read 4, iclass 37, count 2 2006.245.07:54:01.44#ibcon#about to read 5, iclass 37, count 2 2006.245.07:54:01.44#ibcon#read 5, iclass 37, count 2 2006.245.07:54:01.44#ibcon#about to read 6, iclass 37, count 2 2006.245.07:54:01.44#ibcon#read 6, iclass 37, count 2 2006.245.07:54:01.44#ibcon#end of sib2, iclass 37, count 2 2006.245.07:54:01.44#ibcon#*after write, iclass 37, count 2 2006.245.07:54:01.44#ibcon#*before return 0, iclass 37, count 2 2006.245.07:54:01.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:01.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:01.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:54:01.44#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:01.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:01.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:01.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:01.55#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:54:01.55#ibcon#first serial, iclass 37, count 0 2006.245.07:54:01.55#ibcon#enter sib2, iclass 37, count 0 2006.245.07:54:01.55#ibcon#flushed, iclass 37, count 0 2006.245.07:54:01.55#ibcon#about to write, iclass 37, count 0 2006.245.07:54:01.55#ibcon#wrote, iclass 37, count 0 2006.245.07:54:01.55#ibcon#about to read 3, iclass 37, count 0 2006.245.07:54:01.57#ibcon#read 3, iclass 37, count 0 2006.245.07:54:01.57#ibcon#about to read 4, iclass 37, count 0 2006.245.07:54:01.57#ibcon#read 4, iclass 37, count 0 2006.245.07:54:01.57#ibcon#about to read 5, iclass 37, count 0 2006.245.07:54:01.57#ibcon#read 5, iclass 37, count 0 2006.245.07:54:01.57#ibcon#about to read 6, iclass 37, count 0 2006.245.07:54:01.57#ibcon#read 6, iclass 37, count 0 2006.245.07:54:01.57#ibcon#end of sib2, iclass 37, count 0 2006.245.07:54:01.57#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:54:01.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:54:01.57#ibcon#[25=USB\r\n] 2006.245.07:54:01.57#ibcon#*before write, iclass 37, count 0 2006.245.07:54:01.57#ibcon#enter sib2, iclass 37, count 0 2006.245.07:54:01.57#ibcon#flushed, iclass 37, count 0 2006.245.07:54:01.57#ibcon#about to write, iclass 37, count 0 2006.245.07:54:01.57#ibcon#wrote, iclass 37, count 0 2006.245.07:54:01.57#ibcon#about to read 3, iclass 37, count 0 2006.245.07:54:01.60#ibcon#read 3, iclass 37, count 0 2006.245.07:54:01.60#ibcon#about to read 4, iclass 37, count 0 2006.245.07:54:01.60#ibcon#read 4, iclass 37, count 0 2006.245.07:54:01.60#ibcon#about to read 5, iclass 37, count 0 2006.245.07:54:01.60#ibcon#read 5, iclass 37, count 0 2006.245.07:54:01.60#ibcon#about to read 6, iclass 37, count 0 2006.245.07:54:01.60#ibcon#read 6, iclass 37, count 0 2006.245.07:54:01.60#ibcon#end of sib2, iclass 37, count 0 2006.245.07:54:01.60#ibcon#*after write, iclass 37, count 0 2006.245.07:54:01.60#ibcon#*before return 0, iclass 37, count 0 2006.245.07:54:01.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:01.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:01.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:54:01.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:54:01.60$vc4f8/valo=4,832.99 2006.245.07:54:01.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:54:01.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:54:01.60#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:01.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:01.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:01.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:01.60#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:54:01.60#ibcon#first serial, iclass 39, count 0 2006.245.07:54:01.60#ibcon#enter sib2, iclass 39, count 0 2006.245.07:54:01.60#ibcon#flushed, iclass 39, count 0 2006.245.07:54:01.60#ibcon#about to write, iclass 39, count 0 2006.245.07:54:01.61#ibcon#wrote, iclass 39, count 0 2006.245.07:54:01.61#ibcon#about to read 3, iclass 39, count 0 2006.245.07:54:01.62#ibcon#read 3, iclass 39, count 0 2006.245.07:54:01.62#ibcon#about to read 4, iclass 39, count 0 2006.245.07:54:01.62#ibcon#read 4, iclass 39, count 0 2006.245.07:54:01.62#ibcon#about to read 5, iclass 39, count 0 2006.245.07:54:01.62#ibcon#read 5, iclass 39, count 0 2006.245.07:54:01.62#ibcon#about to read 6, iclass 39, count 0 2006.245.07:54:01.62#ibcon#read 6, iclass 39, count 0 2006.245.07:54:01.62#ibcon#end of sib2, iclass 39, count 0 2006.245.07:54:01.62#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:54:01.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:54:01.62#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:54:01.62#ibcon#*before write, iclass 39, count 0 2006.245.07:54:01.62#ibcon#enter sib2, iclass 39, count 0 2006.245.07:54:01.62#ibcon#flushed, iclass 39, count 0 2006.245.07:54:01.62#ibcon#about to write, iclass 39, count 0 2006.245.07:54:01.62#ibcon#wrote, iclass 39, count 0 2006.245.07:54:01.62#ibcon#about to read 3, iclass 39, count 0 2006.245.07:54:01.66#ibcon#read 3, iclass 39, count 0 2006.245.07:54:01.66#ibcon#about to read 4, iclass 39, count 0 2006.245.07:54:01.66#ibcon#read 4, iclass 39, count 0 2006.245.07:54:01.66#ibcon#about to read 5, iclass 39, count 0 2006.245.07:54:01.66#ibcon#read 5, iclass 39, count 0 2006.245.07:54:01.66#ibcon#about to read 6, iclass 39, count 0 2006.245.07:54:01.66#ibcon#read 6, iclass 39, count 0 2006.245.07:54:01.66#ibcon#end of sib2, iclass 39, count 0 2006.245.07:54:01.66#ibcon#*after write, iclass 39, count 0 2006.245.07:54:01.66#ibcon#*before return 0, iclass 39, count 0 2006.245.07:54:01.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:01.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:01.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:54:01.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:54:01.66$vc4f8/va=4,7 2006.245.07:54:01.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:54:01.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:54:01.66#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:01.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:01.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:01.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:01.72#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:54:01.72#ibcon#first serial, iclass 3, count 2 2006.245.07:54:01.72#ibcon#enter sib2, iclass 3, count 2 2006.245.07:54:01.72#ibcon#flushed, iclass 3, count 2 2006.245.07:54:01.72#ibcon#about to write, iclass 3, count 2 2006.245.07:54:01.72#ibcon#wrote, iclass 3, count 2 2006.245.07:54:01.72#ibcon#about to read 3, iclass 3, count 2 2006.245.07:54:01.74#ibcon#read 3, iclass 3, count 2 2006.245.07:54:01.74#ibcon#about to read 4, iclass 3, count 2 2006.245.07:54:01.74#ibcon#read 4, iclass 3, count 2 2006.245.07:54:01.74#ibcon#about to read 5, iclass 3, count 2 2006.245.07:54:01.74#ibcon#read 5, iclass 3, count 2 2006.245.07:54:01.74#ibcon#about to read 6, iclass 3, count 2 2006.245.07:54:01.74#ibcon#read 6, iclass 3, count 2 2006.245.07:54:01.74#ibcon#end of sib2, iclass 3, count 2 2006.245.07:54:01.74#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:54:01.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:54:01.74#ibcon#[25=AT04-07\r\n] 2006.245.07:54:01.74#ibcon#*before write, iclass 3, count 2 2006.245.07:54:01.74#ibcon#enter sib2, iclass 3, count 2 2006.245.07:54:01.74#ibcon#flushed, iclass 3, count 2 2006.245.07:54:01.74#ibcon#about to write, iclass 3, count 2 2006.245.07:54:01.74#ibcon#wrote, iclass 3, count 2 2006.245.07:54:01.74#ibcon#about to read 3, iclass 3, count 2 2006.245.07:54:01.77#ibcon#read 3, iclass 3, count 2 2006.245.07:54:01.77#ibcon#about to read 4, iclass 3, count 2 2006.245.07:54:01.77#ibcon#read 4, iclass 3, count 2 2006.245.07:54:01.77#ibcon#about to read 5, iclass 3, count 2 2006.245.07:54:01.77#ibcon#read 5, iclass 3, count 2 2006.245.07:54:01.77#ibcon#about to read 6, iclass 3, count 2 2006.245.07:54:01.77#ibcon#read 6, iclass 3, count 2 2006.245.07:54:01.77#ibcon#end of sib2, iclass 3, count 2 2006.245.07:54:01.77#ibcon#*after write, iclass 3, count 2 2006.245.07:54:01.77#ibcon#*before return 0, iclass 3, count 2 2006.245.07:54:01.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:01.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:01.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:54:01.77#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:01.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:01.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:01.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:01.89#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:54:01.89#ibcon#first serial, iclass 3, count 0 2006.245.07:54:01.89#ibcon#enter sib2, iclass 3, count 0 2006.245.07:54:01.89#ibcon#flushed, iclass 3, count 0 2006.245.07:54:01.89#ibcon#about to write, iclass 3, count 0 2006.245.07:54:01.89#ibcon#wrote, iclass 3, count 0 2006.245.07:54:01.89#ibcon#about to read 3, iclass 3, count 0 2006.245.07:54:01.91#ibcon#read 3, iclass 3, count 0 2006.245.07:54:01.91#ibcon#about to read 4, iclass 3, count 0 2006.245.07:54:01.91#ibcon#read 4, iclass 3, count 0 2006.245.07:54:01.91#ibcon#about to read 5, iclass 3, count 0 2006.245.07:54:01.91#ibcon#read 5, iclass 3, count 0 2006.245.07:54:01.91#ibcon#about to read 6, iclass 3, count 0 2006.245.07:54:01.91#ibcon#read 6, iclass 3, count 0 2006.245.07:54:01.91#ibcon#end of sib2, iclass 3, count 0 2006.245.07:54:01.91#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:54:01.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:54:01.91#ibcon#[25=USB\r\n] 2006.245.07:54:01.91#ibcon#*before write, iclass 3, count 0 2006.245.07:54:01.91#ibcon#enter sib2, iclass 3, count 0 2006.245.07:54:01.91#ibcon#flushed, iclass 3, count 0 2006.245.07:54:01.91#ibcon#about to write, iclass 3, count 0 2006.245.07:54:01.91#ibcon#wrote, iclass 3, count 0 2006.245.07:54:01.91#ibcon#about to read 3, iclass 3, count 0 2006.245.07:54:01.94#ibcon#read 3, iclass 3, count 0 2006.245.07:54:01.94#ibcon#about to read 4, iclass 3, count 0 2006.245.07:54:01.94#ibcon#read 4, iclass 3, count 0 2006.245.07:54:01.94#ibcon#about to read 5, iclass 3, count 0 2006.245.07:54:01.94#ibcon#read 5, iclass 3, count 0 2006.245.07:54:01.94#ibcon#about to read 6, iclass 3, count 0 2006.245.07:54:01.94#ibcon#read 6, iclass 3, count 0 2006.245.07:54:01.94#ibcon#end of sib2, iclass 3, count 0 2006.245.07:54:01.94#ibcon#*after write, iclass 3, count 0 2006.245.07:54:01.94#ibcon#*before return 0, iclass 3, count 0 2006.245.07:54:01.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:01.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:01.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:54:01.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:54:01.94$vc4f8/valo=5,652.99 2006.245.07:54:01.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:54:01.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:54:01.94#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:01.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:01.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:01.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:01.94#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:54:01.94#ibcon#first serial, iclass 5, count 0 2006.245.07:54:01.94#ibcon#enter sib2, iclass 5, count 0 2006.245.07:54:01.94#ibcon#flushed, iclass 5, count 0 2006.245.07:54:01.94#ibcon#about to write, iclass 5, count 0 2006.245.07:54:01.95#ibcon#wrote, iclass 5, count 0 2006.245.07:54:01.95#ibcon#about to read 3, iclass 5, count 0 2006.245.07:54:01.96#ibcon#read 3, iclass 5, count 0 2006.245.07:54:01.96#ibcon#about to read 4, iclass 5, count 0 2006.245.07:54:01.96#ibcon#read 4, iclass 5, count 0 2006.245.07:54:01.96#ibcon#about to read 5, iclass 5, count 0 2006.245.07:54:01.96#ibcon#read 5, iclass 5, count 0 2006.245.07:54:01.96#ibcon#about to read 6, iclass 5, count 0 2006.245.07:54:01.96#ibcon#read 6, iclass 5, count 0 2006.245.07:54:01.96#ibcon#end of sib2, iclass 5, count 0 2006.245.07:54:01.96#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:54:01.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:54:01.96#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:54:01.96#ibcon#*before write, iclass 5, count 0 2006.245.07:54:01.96#ibcon#enter sib2, iclass 5, count 0 2006.245.07:54:01.96#ibcon#flushed, iclass 5, count 0 2006.245.07:54:01.96#ibcon#about to write, iclass 5, count 0 2006.245.07:54:01.96#ibcon#wrote, iclass 5, count 0 2006.245.07:54:01.96#ibcon#about to read 3, iclass 5, count 0 2006.245.07:54:02.00#ibcon#read 3, iclass 5, count 0 2006.245.07:54:02.00#ibcon#about to read 4, iclass 5, count 0 2006.245.07:54:02.00#ibcon#read 4, iclass 5, count 0 2006.245.07:54:02.00#ibcon#about to read 5, iclass 5, count 0 2006.245.07:54:02.00#ibcon#read 5, iclass 5, count 0 2006.245.07:54:02.00#ibcon#about to read 6, iclass 5, count 0 2006.245.07:54:02.00#ibcon#read 6, iclass 5, count 0 2006.245.07:54:02.00#ibcon#end of sib2, iclass 5, count 0 2006.245.07:54:02.00#ibcon#*after write, iclass 5, count 0 2006.245.07:54:02.00#ibcon#*before return 0, iclass 5, count 0 2006.245.07:54:02.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:02.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:02.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:54:02.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:54:02.00$vc4f8/va=5,7 2006.245.07:54:02.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:54:02.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:54:02.00#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:02.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:02.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:02.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:02.06#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:54:02.06#ibcon#first serial, iclass 7, count 2 2006.245.07:54:02.06#ibcon#enter sib2, iclass 7, count 2 2006.245.07:54:02.06#ibcon#flushed, iclass 7, count 2 2006.245.07:54:02.06#ibcon#about to write, iclass 7, count 2 2006.245.07:54:02.06#ibcon#wrote, iclass 7, count 2 2006.245.07:54:02.06#ibcon#about to read 3, iclass 7, count 2 2006.245.07:54:02.08#ibcon#read 3, iclass 7, count 2 2006.245.07:54:02.08#ibcon#about to read 4, iclass 7, count 2 2006.245.07:54:02.08#ibcon#read 4, iclass 7, count 2 2006.245.07:54:02.08#ibcon#about to read 5, iclass 7, count 2 2006.245.07:54:02.08#ibcon#read 5, iclass 7, count 2 2006.245.07:54:02.08#ibcon#about to read 6, iclass 7, count 2 2006.245.07:54:02.08#ibcon#read 6, iclass 7, count 2 2006.245.07:54:02.08#ibcon#end of sib2, iclass 7, count 2 2006.245.07:54:02.08#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:54:02.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:54:02.08#ibcon#[25=AT05-07\r\n] 2006.245.07:54:02.08#ibcon#*before write, iclass 7, count 2 2006.245.07:54:02.08#ibcon#enter sib2, iclass 7, count 2 2006.245.07:54:02.08#ibcon#flushed, iclass 7, count 2 2006.245.07:54:02.08#ibcon#about to write, iclass 7, count 2 2006.245.07:54:02.08#ibcon#wrote, iclass 7, count 2 2006.245.07:54:02.08#ibcon#about to read 3, iclass 7, count 2 2006.245.07:54:02.11#ibcon#read 3, iclass 7, count 2 2006.245.07:54:02.11#ibcon#about to read 4, iclass 7, count 2 2006.245.07:54:02.11#ibcon#read 4, iclass 7, count 2 2006.245.07:54:02.11#ibcon#about to read 5, iclass 7, count 2 2006.245.07:54:02.11#ibcon#read 5, iclass 7, count 2 2006.245.07:54:02.11#ibcon#about to read 6, iclass 7, count 2 2006.245.07:54:02.11#ibcon#read 6, iclass 7, count 2 2006.245.07:54:02.11#ibcon#end of sib2, iclass 7, count 2 2006.245.07:54:02.11#ibcon#*after write, iclass 7, count 2 2006.245.07:54:02.11#ibcon#*before return 0, iclass 7, count 2 2006.245.07:54:02.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:02.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:02.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:54:02.11#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:02.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:02.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:02.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:02.23#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:54:02.23#ibcon#first serial, iclass 7, count 0 2006.245.07:54:02.23#ibcon#enter sib2, iclass 7, count 0 2006.245.07:54:02.23#ibcon#flushed, iclass 7, count 0 2006.245.07:54:02.23#ibcon#about to write, iclass 7, count 0 2006.245.07:54:02.23#ibcon#wrote, iclass 7, count 0 2006.245.07:54:02.23#ibcon#about to read 3, iclass 7, count 0 2006.245.07:54:02.25#ibcon#read 3, iclass 7, count 0 2006.245.07:54:02.25#ibcon#about to read 4, iclass 7, count 0 2006.245.07:54:02.25#ibcon#read 4, iclass 7, count 0 2006.245.07:54:02.25#ibcon#about to read 5, iclass 7, count 0 2006.245.07:54:02.25#ibcon#read 5, iclass 7, count 0 2006.245.07:54:02.25#ibcon#about to read 6, iclass 7, count 0 2006.245.07:54:02.25#ibcon#read 6, iclass 7, count 0 2006.245.07:54:02.25#ibcon#end of sib2, iclass 7, count 0 2006.245.07:54:02.25#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:54:02.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:54:02.25#ibcon#[25=USB\r\n] 2006.245.07:54:02.25#ibcon#*before write, iclass 7, count 0 2006.245.07:54:02.25#ibcon#enter sib2, iclass 7, count 0 2006.245.07:54:02.25#ibcon#flushed, iclass 7, count 0 2006.245.07:54:02.25#ibcon#about to write, iclass 7, count 0 2006.245.07:54:02.25#ibcon#wrote, iclass 7, count 0 2006.245.07:54:02.25#ibcon#about to read 3, iclass 7, count 0 2006.245.07:54:02.28#ibcon#read 3, iclass 7, count 0 2006.245.07:54:02.28#ibcon#about to read 4, iclass 7, count 0 2006.245.07:54:02.28#ibcon#read 4, iclass 7, count 0 2006.245.07:54:02.28#ibcon#about to read 5, iclass 7, count 0 2006.245.07:54:02.28#ibcon#read 5, iclass 7, count 0 2006.245.07:54:02.28#ibcon#about to read 6, iclass 7, count 0 2006.245.07:54:02.28#ibcon#read 6, iclass 7, count 0 2006.245.07:54:02.28#ibcon#end of sib2, iclass 7, count 0 2006.245.07:54:02.28#ibcon#*after write, iclass 7, count 0 2006.245.07:54:02.28#ibcon#*before return 0, iclass 7, count 0 2006.245.07:54:02.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:02.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:02.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:54:02.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:54:02.28$vc4f8/valo=6,772.99 2006.245.07:54:02.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:54:02.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:54:02.28#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:02.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:02.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:02.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:02.28#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:54:02.28#ibcon#first serial, iclass 11, count 0 2006.245.07:54:02.28#ibcon#enter sib2, iclass 11, count 0 2006.245.07:54:02.28#ibcon#flushed, iclass 11, count 0 2006.245.07:54:02.28#ibcon#about to write, iclass 11, count 0 2006.245.07:54:02.29#ibcon#wrote, iclass 11, count 0 2006.245.07:54:02.29#ibcon#about to read 3, iclass 11, count 0 2006.245.07:54:02.30#ibcon#read 3, iclass 11, count 0 2006.245.07:54:02.30#ibcon#about to read 4, iclass 11, count 0 2006.245.07:54:02.30#ibcon#read 4, iclass 11, count 0 2006.245.07:54:02.30#ibcon#about to read 5, iclass 11, count 0 2006.245.07:54:02.30#ibcon#read 5, iclass 11, count 0 2006.245.07:54:02.30#ibcon#about to read 6, iclass 11, count 0 2006.245.07:54:02.30#ibcon#read 6, iclass 11, count 0 2006.245.07:54:02.30#ibcon#end of sib2, iclass 11, count 0 2006.245.07:54:02.30#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:54:02.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:54:02.30#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:54:02.30#ibcon#*before write, iclass 11, count 0 2006.245.07:54:02.30#ibcon#enter sib2, iclass 11, count 0 2006.245.07:54:02.30#ibcon#flushed, iclass 11, count 0 2006.245.07:54:02.30#ibcon#about to write, iclass 11, count 0 2006.245.07:54:02.30#ibcon#wrote, iclass 11, count 0 2006.245.07:54:02.30#ibcon#about to read 3, iclass 11, count 0 2006.245.07:54:02.34#ibcon#read 3, iclass 11, count 0 2006.245.07:54:02.34#ibcon#about to read 4, iclass 11, count 0 2006.245.07:54:02.34#ibcon#read 4, iclass 11, count 0 2006.245.07:54:02.34#ibcon#about to read 5, iclass 11, count 0 2006.245.07:54:02.34#ibcon#read 5, iclass 11, count 0 2006.245.07:54:02.34#ibcon#about to read 6, iclass 11, count 0 2006.245.07:54:02.34#ibcon#read 6, iclass 11, count 0 2006.245.07:54:02.34#ibcon#end of sib2, iclass 11, count 0 2006.245.07:54:02.34#ibcon#*after write, iclass 11, count 0 2006.245.07:54:02.34#ibcon#*before return 0, iclass 11, count 0 2006.245.07:54:02.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:02.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:02.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:54:02.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:54:02.34$vc4f8/va=6,7 2006.245.07:54:02.34#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.07:54:02.34#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.07:54:02.34#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:02.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:54:02.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:54:02.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:54:02.41#ibcon#enter wrdev, iclass 13, count 2 2006.245.07:54:02.41#ibcon#first serial, iclass 13, count 2 2006.245.07:54:02.41#ibcon#enter sib2, iclass 13, count 2 2006.245.07:54:02.41#ibcon#flushed, iclass 13, count 2 2006.245.07:54:02.41#ibcon#about to write, iclass 13, count 2 2006.245.07:54:02.41#ibcon#wrote, iclass 13, count 2 2006.245.07:54:02.41#ibcon#about to read 3, iclass 13, count 2 2006.245.07:54:02.43#ibcon#read 3, iclass 13, count 2 2006.245.07:54:02.43#ibcon#about to read 4, iclass 13, count 2 2006.245.07:54:02.43#ibcon#read 4, iclass 13, count 2 2006.245.07:54:02.43#ibcon#about to read 5, iclass 13, count 2 2006.245.07:54:02.43#ibcon#read 5, iclass 13, count 2 2006.245.07:54:02.43#ibcon#about to read 6, iclass 13, count 2 2006.245.07:54:02.43#ibcon#read 6, iclass 13, count 2 2006.245.07:54:02.43#ibcon#end of sib2, iclass 13, count 2 2006.245.07:54:02.43#ibcon#*mode == 0, iclass 13, count 2 2006.245.07:54:02.43#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.07:54:02.43#ibcon#[25=AT06-07\r\n] 2006.245.07:54:02.43#ibcon#*before write, iclass 13, count 2 2006.245.07:54:02.43#ibcon#enter sib2, iclass 13, count 2 2006.245.07:54:02.43#ibcon#flushed, iclass 13, count 2 2006.245.07:54:02.43#ibcon#about to write, iclass 13, count 2 2006.245.07:54:02.43#ibcon#wrote, iclass 13, count 2 2006.245.07:54:02.43#ibcon#about to read 3, iclass 13, count 2 2006.245.07:54:02.45#ibcon#read 3, iclass 13, count 2 2006.245.07:54:02.45#ibcon#about to read 4, iclass 13, count 2 2006.245.07:54:02.45#ibcon#read 4, iclass 13, count 2 2006.245.07:54:02.45#ibcon#about to read 5, iclass 13, count 2 2006.245.07:54:02.45#ibcon#read 5, iclass 13, count 2 2006.245.07:54:02.45#ibcon#about to read 6, iclass 13, count 2 2006.245.07:54:02.45#ibcon#read 6, iclass 13, count 2 2006.245.07:54:02.45#ibcon#end of sib2, iclass 13, count 2 2006.245.07:54:02.45#ibcon#*after write, iclass 13, count 2 2006.245.07:54:02.45#ibcon#*before return 0, iclass 13, count 2 2006.245.07:54:02.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:54:02.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.07:54:02.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.07:54:02.45#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:02.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:54:02.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:54:02.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:54:02.57#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:54:02.57#ibcon#first serial, iclass 13, count 0 2006.245.07:54:02.57#ibcon#enter sib2, iclass 13, count 0 2006.245.07:54:02.57#ibcon#flushed, iclass 13, count 0 2006.245.07:54:02.57#ibcon#about to write, iclass 13, count 0 2006.245.07:54:02.57#ibcon#wrote, iclass 13, count 0 2006.245.07:54:02.57#ibcon#about to read 3, iclass 13, count 0 2006.245.07:54:02.59#ibcon#read 3, iclass 13, count 0 2006.245.07:54:02.59#ibcon#about to read 4, iclass 13, count 0 2006.245.07:54:02.59#ibcon#read 4, iclass 13, count 0 2006.245.07:54:02.59#ibcon#about to read 5, iclass 13, count 0 2006.245.07:54:02.59#ibcon#read 5, iclass 13, count 0 2006.245.07:54:02.59#ibcon#about to read 6, iclass 13, count 0 2006.245.07:54:02.59#ibcon#read 6, iclass 13, count 0 2006.245.07:54:02.59#ibcon#end of sib2, iclass 13, count 0 2006.245.07:54:02.59#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:54:02.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:54:02.59#ibcon#[25=USB\r\n] 2006.245.07:54:02.59#ibcon#*before write, iclass 13, count 0 2006.245.07:54:02.59#ibcon#enter sib2, iclass 13, count 0 2006.245.07:54:02.59#ibcon#flushed, iclass 13, count 0 2006.245.07:54:02.59#ibcon#about to write, iclass 13, count 0 2006.245.07:54:02.59#ibcon#wrote, iclass 13, count 0 2006.245.07:54:02.59#ibcon#about to read 3, iclass 13, count 0 2006.245.07:54:02.62#ibcon#read 3, iclass 13, count 0 2006.245.07:54:02.62#ibcon#about to read 4, iclass 13, count 0 2006.245.07:54:02.62#ibcon#read 4, iclass 13, count 0 2006.245.07:54:02.62#ibcon#about to read 5, iclass 13, count 0 2006.245.07:54:02.62#ibcon#read 5, iclass 13, count 0 2006.245.07:54:02.62#ibcon#about to read 6, iclass 13, count 0 2006.245.07:54:02.62#ibcon#read 6, iclass 13, count 0 2006.245.07:54:02.62#ibcon#end of sib2, iclass 13, count 0 2006.245.07:54:02.62#ibcon#*after write, iclass 13, count 0 2006.245.07:54:02.62#ibcon#*before return 0, iclass 13, count 0 2006.245.07:54:02.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:54:02.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.07:54:02.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:54:02.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:54:02.62$vc4f8/valo=7,832.99 2006.245.07:54:02.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.07:54:02.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.07:54:02.62#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:02.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:54:02.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:54:02.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:54:02.62#ibcon#enter wrdev, iclass 15, count 0 2006.245.07:54:02.62#ibcon#first serial, iclass 15, count 0 2006.245.07:54:02.62#ibcon#enter sib2, iclass 15, count 0 2006.245.07:54:02.62#ibcon#flushed, iclass 15, count 0 2006.245.07:54:02.62#ibcon#about to write, iclass 15, count 0 2006.245.07:54:02.62#ibcon#wrote, iclass 15, count 0 2006.245.07:54:02.63#ibcon#about to read 3, iclass 15, count 0 2006.245.07:54:02.64#ibcon#read 3, iclass 15, count 0 2006.245.07:54:02.64#ibcon#about to read 4, iclass 15, count 0 2006.245.07:54:02.64#ibcon#read 4, iclass 15, count 0 2006.245.07:54:02.64#ibcon#about to read 5, iclass 15, count 0 2006.245.07:54:02.64#ibcon#read 5, iclass 15, count 0 2006.245.07:54:02.64#ibcon#about to read 6, iclass 15, count 0 2006.245.07:54:02.64#ibcon#read 6, iclass 15, count 0 2006.245.07:54:02.64#ibcon#end of sib2, iclass 15, count 0 2006.245.07:54:02.64#ibcon#*mode == 0, iclass 15, count 0 2006.245.07:54:02.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.07:54:02.64#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:54:02.64#ibcon#*before write, iclass 15, count 0 2006.245.07:54:02.64#ibcon#enter sib2, iclass 15, count 0 2006.245.07:54:02.64#ibcon#flushed, iclass 15, count 0 2006.245.07:54:02.64#ibcon#about to write, iclass 15, count 0 2006.245.07:54:02.64#ibcon#wrote, iclass 15, count 0 2006.245.07:54:02.64#ibcon#about to read 3, iclass 15, count 0 2006.245.07:54:02.68#ibcon#read 3, iclass 15, count 0 2006.245.07:54:02.68#ibcon#about to read 4, iclass 15, count 0 2006.245.07:54:02.68#ibcon#read 4, iclass 15, count 0 2006.245.07:54:02.68#ibcon#about to read 5, iclass 15, count 0 2006.245.07:54:02.68#ibcon#read 5, iclass 15, count 0 2006.245.07:54:02.68#ibcon#about to read 6, iclass 15, count 0 2006.245.07:54:02.68#ibcon#read 6, iclass 15, count 0 2006.245.07:54:02.68#ibcon#end of sib2, iclass 15, count 0 2006.245.07:54:02.68#ibcon#*after write, iclass 15, count 0 2006.245.07:54:02.68#ibcon#*before return 0, iclass 15, count 0 2006.245.07:54:02.68#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:54:02.68#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.07:54:02.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.07:54:02.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.07:54:02.68$vc4f8/va=7,7 2006.245.07:54:02.68#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.07:54:02.68#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.07:54:02.68#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:02.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:54:02.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:54:02.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:54:02.74#ibcon#enter wrdev, iclass 17, count 2 2006.245.07:54:02.74#ibcon#first serial, iclass 17, count 2 2006.245.07:54:02.74#ibcon#enter sib2, iclass 17, count 2 2006.245.07:54:02.74#ibcon#flushed, iclass 17, count 2 2006.245.07:54:02.74#ibcon#about to write, iclass 17, count 2 2006.245.07:54:02.74#ibcon#wrote, iclass 17, count 2 2006.245.07:54:02.74#ibcon#about to read 3, iclass 17, count 2 2006.245.07:54:02.76#ibcon#read 3, iclass 17, count 2 2006.245.07:54:02.76#ibcon#about to read 4, iclass 17, count 2 2006.245.07:54:02.76#ibcon#read 4, iclass 17, count 2 2006.245.07:54:02.76#ibcon#about to read 5, iclass 17, count 2 2006.245.07:54:02.76#ibcon#read 5, iclass 17, count 2 2006.245.07:54:02.76#ibcon#about to read 6, iclass 17, count 2 2006.245.07:54:02.76#ibcon#read 6, iclass 17, count 2 2006.245.07:54:02.76#ibcon#end of sib2, iclass 17, count 2 2006.245.07:54:02.76#ibcon#*mode == 0, iclass 17, count 2 2006.245.07:54:02.76#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.07:54:02.76#ibcon#[25=AT07-07\r\n] 2006.245.07:54:02.76#ibcon#*before write, iclass 17, count 2 2006.245.07:54:02.76#ibcon#enter sib2, iclass 17, count 2 2006.245.07:54:02.76#ibcon#flushed, iclass 17, count 2 2006.245.07:54:02.76#ibcon#about to write, iclass 17, count 2 2006.245.07:54:02.76#ibcon#wrote, iclass 17, count 2 2006.245.07:54:02.76#ibcon#about to read 3, iclass 17, count 2 2006.245.07:54:02.79#ibcon#read 3, iclass 17, count 2 2006.245.07:54:02.79#ibcon#about to read 4, iclass 17, count 2 2006.245.07:54:02.79#ibcon#read 4, iclass 17, count 2 2006.245.07:54:02.79#ibcon#about to read 5, iclass 17, count 2 2006.245.07:54:02.79#ibcon#read 5, iclass 17, count 2 2006.245.07:54:02.79#ibcon#about to read 6, iclass 17, count 2 2006.245.07:54:02.79#ibcon#read 6, iclass 17, count 2 2006.245.07:54:02.79#ibcon#end of sib2, iclass 17, count 2 2006.245.07:54:02.79#ibcon#*after write, iclass 17, count 2 2006.245.07:54:02.79#ibcon#*before return 0, iclass 17, count 2 2006.245.07:54:02.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:54:02.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.07:54:02.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.07:54:02.79#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:02.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:54:02.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:54:02.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:54:02.91#ibcon#enter wrdev, iclass 17, count 0 2006.245.07:54:02.91#ibcon#first serial, iclass 17, count 0 2006.245.07:54:02.91#ibcon#enter sib2, iclass 17, count 0 2006.245.07:54:02.91#ibcon#flushed, iclass 17, count 0 2006.245.07:54:02.91#ibcon#about to write, iclass 17, count 0 2006.245.07:54:02.91#ibcon#wrote, iclass 17, count 0 2006.245.07:54:02.91#ibcon#about to read 3, iclass 17, count 0 2006.245.07:54:02.93#ibcon#read 3, iclass 17, count 0 2006.245.07:54:02.93#ibcon#about to read 4, iclass 17, count 0 2006.245.07:54:02.93#ibcon#read 4, iclass 17, count 0 2006.245.07:54:02.93#ibcon#about to read 5, iclass 17, count 0 2006.245.07:54:02.93#ibcon#read 5, iclass 17, count 0 2006.245.07:54:02.93#ibcon#about to read 6, iclass 17, count 0 2006.245.07:54:02.93#ibcon#read 6, iclass 17, count 0 2006.245.07:54:02.93#ibcon#end of sib2, iclass 17, count 0 2006.245.07:54:02.93#ibcon#*mode == 0, iclass 17, count 0 2006.245.07:54:02.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.07:54:02.93#ibcon#[25=USB\r\n] 2006.245.07:54:02.93#ibcon#*before write, iclass 17, count 0 2006.245.07:54:02.93#ibcon#enter sib2, iclass 17, count 0 2006.245.07:54:02.93#ibcon#flushed, iclass 17, count 0 2006.245.07:54:02.93#ibcon#about to write, iclass 17, count 0 2006.245.07:54:02.93#ibcon#wrote, iclass 17, count 0 2006.245.07:54:02.93#ibcon#about to read 3, iclass 17, count 0 2006.245.07:54:02.96#ibcon#read 3, iclass 17, count 0 2006.245.07:54:02.96#ibcon#about to read 4, iclass 17, count 0 2006.245.07:54:02.96#ibcon#read 4, iclass 17, count 0 2006.245.07:54:02.96#ibcon#about to read 5, iclass 17, count 0 2006.245.07:54:02.96#ibcon#read 5, iclass 17, count 0 2006.245.07:54:02.96#ibcon#about to read 6, iclass 17, count 0 2006.245.07:54:02.96#ibcon#read 6, iclass 17, count 0 2006.245.07:54:02.96#ibcon#end of sib2, iclass 17, count 0 2006.245.07:54:02.96#ibcon#*after write, iclass 17, count 0 2006.245.07:54:02.96#ibcon#*before return 0, iclass 17, count 0 2006.245.07:54:02.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:54:02.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.07:54:02.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.07:54:02.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.07:54:02.96$vc4f8/valo=8,852.99 2006.245.07:54:02.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.07:54:02.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.07:54:02.96#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:02.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:54:02.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:54:02.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:54:02.96#ibcon#enter wrdev, iclass 19, count 0 2006.245.07:54:02.96#ibcon#first serial, iclass 19, count 0 2006.245.07:54:02.96#ibcon#enter sib2, iclass 19, count 0 2006.245.07:54:02.96#ibcon#flushed, iclass 19, count 0 2006.245.07:54:02.96#ibcon#about to write, iclass 19, count 0 2006.245.07:54:02.96#ibcon#wrote, iclass 19, count 0 2006.245.07:54:02.97#ibcon#about to read 3, iclass 19, count 0 2006.245.07:54:02.98#ibcon#read 3, iclass 19, count 0 2006.245.07:54:02.98#ibcon#about to read 4, iclass 19, count 0 2006.245.07:54:02.98#ibcon#read 4, iclass 19, count 0 2006.245.07:54:02.98#ibcon#about to read 5, iclass 19, count 0 2006.245.07:54:02.98#ibcon#read 5, iclass 19, count 0 2006.245.07:54:02.98#ibcon#about to read 6, iclass 19, count 0 2006.245.07:54:02.98#ibcon#read 6, iclass 19, count 0 2006.245.07:54:02.98#ibcon#end of sib2, iclass 19, count 0 2006.245.07:54:02.98#ibcon#*mode == 0, iclass 19, count 0 2006.245.07:54:02.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.07:54:02.98#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:54:02.98#ibcon#*before write, iclass 19, count 0 2006.245.07:54:02.98#ibcon#enter sib2, iclass 19, count 0 2006.245.07:54:02.98#ibcon#flushed, iclass 19, count 0 2006.245.07:54:02.98#ibcon#about to write, iclass 19, count 0 2006.245.07:54:02.98#ibcon#wrote, iclass 19, count 0 2006.245.07:54:02.98#ibcon#about to read 3, iclass 19, count 0 2006.245.07:54:03.02#ibcon#read 3, iclass 19, count 0 2006.245.07:54:03.02#ibcon#about to read 4, iclass 19, count 0 2006.245.07:54:03.02#ibcon#read 4, iclass 19, count 0 2006.245.07:54:03.02#ibcon#about to read 5, iclass 19, count 0 2006.245.07:54:03.02#ibcon#read 5, iclass 19, count 0 2006.245.07:54:03.02#ibcon#about to read 6, iclass 19, count 0 2006.245.07:54:03.02#ibcon#read 6, iclass 19, count 0 2006.245.07:54:03.02#ibcon#end of sib2, iclass 19, count 0 2006.245.07:54:03.02#ibcon#*after write, iclass 19, count 0 2006.245.07:54:03.02#ibcon#*before return 0, iclass 19, count 0 2006.245.07:54:03.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:54:03.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.07:54:03.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.07:54:03.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.07:54:03.02$vc4f8/va=8,8 2006.245.07:54:03.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.07:54:03.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.07:54:03.02#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:03.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:54:03.09#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:54:03.09#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:54:03.09#ibcon#enter wrdev, iclass 21, count 2 2006.245.07:54:03.09#ibcon#first serial, iclass 21, count 2 2006.245.07:54:03.09#ibcon#enter sib2, iclass 21, count 2 2006.245.07:54:03.09#ibcon#flushed, iclass 21, count 2 2006.245.07:54:03.09#ibcon#about to write, iclass 21, count 2 2006.245.07:54:03.09#ibcon#wrote, iclass 21, count 2 2006.245.07:54:03.09#ibcon#about to read 3, iclass 21, count 2 2006.245.07:54:03.11#ibcon#read 3, iclass 21, count 2 2006.245.07:54:03.11#ibcon#about to read 4, iclass 21, count 2 2006.245.07:54:03.11#ibcon#read 4, iclass 21, count 2 2006.245.07:54:03.11#ibcon#about to read 5, iclass 21, count 2 2006.245.07:54:03.11#ibcon#read 5, iclass 21, count 2 2006.245.07:54:03.11#ibcon#about to read 6, iclass 21, count 2 2006.245.07:54:03.11#ibcon#read 6, iclass 21, count 2 2006.245.07:54:03.11#ibcon#end of sib2, iclass 21, count 2 2006.245.07:54:03.11#ibcon#*mode == 0, iclass 21, count 2 2006.245.07:54:03.11#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.07:54:03.11#ibcon#[25=AT08-08\r\n] 2006.245.07:54:03.11#ibcon#*before write, iclass 21, count 2 2006.245.07:54:03.11#ibcon#enter sib2, iclass 21, count 2 2006.245.07:54:03.11#ibcon#flushed, iclass 21, count 2 2006.245.07:54:03.11#ibcon#about to write, iclass 21, count 2 2006.245.07:54:03.11#ibcon#wrote, iclass 21, count 2 2006.245.07:54:03.11#ibcon#about to read 3, iclass 21, count 2 2006.245.07:54:03.13#ibcon#read 3, iclass 21, count 2 2006.245.07:54:03.13#ibcon#about to read 4, iclass 21, count 2 2006.245.07:54:03.13#ibcon#read 4, iclass 21, count 2 2006.245.07:54:03.13#ibcon#about to read 5, iclass 21, count 2 2006.245.07:54:03.13#ibcon#read 5, iclass 21, count 2 2006.245.07:54:03.13#ibcon#about to read 6, iclass 21, count 2 2006.245.07:54:03.13#ibcon#read 6, iclass 21, count 2 2006.245.07:54:03.13#ibcon#end of sib2, iclass 21, count 2 2006.245.07:54:03.13#ibcon#*after write, iclass 21, count 2 2006.245.07:54:03.13#ibcon#*before return 0, iclass 21, count 2 2006.245.07:54:03.13#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:54:03.13#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.07:54:03.13#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.07:54:03.13#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:03.13#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:54:03.25#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:54:03.25#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:54:03.25#ibcon#enter wrdev, iclass 21, count 0 2006.245.07:54:03.25#ibcon#first serial, iclass 21, count 0 2006.245.07:54:03.25#ibcon#enter sib2, iclass 21, count 0 2006.245.07:54:03.25#ibcon#flushed, iclass 21, count 0 2006.245.07:54:03.25#ibcon#about to write, iclass 21, count 0 2006.245.07:54:03.25#ibcon#wrote, iclass 21, count 0 2006.245.07:54:03.25#ibcon#about to read 3, iclass 21, count 0 2006.245.07:54:03.27#ibcon#read 3, iclass 21, count 0 2006.245.07:54:03.27#ibcon#about to read 4, iclass 21, count 0 2006.245.07:54:03.27#ibcon#read 4, iclass 21, count 0 2006.245.07:54:03.27#ibcon#about to read 5, iclass 21, count 0 2006.245.07:54:03.27#ibcon#read 5, iclass 21, count 0 2006.245.07:54:03.27#ibcon#about to read 6, iclass 21, count 0 2006.245.07:54:03.27#ibcon#read 6, iclass 21, count 0 2006.245.07:54:03.27#ibcon#end of sib2, iclass 21, count 0 2006.245.07:54:03.27#ibcon#*mode == 0, iclass 21, count 0 2006.245.07:54:03.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.07:54:03.27#ibcon#[25=USB\r\n] 2006.245.07:54:03.27#ibcon#*before write, iclass 21, count 0 2006.245.07:54:03.27#ibcon#enter sib2, iclass 21, count 0 2006.245.07:54:03.27#ibcon#flushed, iclass 21, count 0 2006.245.07:54:03.27#ibcon#about to write, iclass 21, count 0 2006.245.07:54:03.27#ibcon#wrote, iclass 21, count 0 2006.245.07:54:03.27#ibcon#about to read 3, iclass 21, count 0 2006.245.07:54:03.30#ibcon#read 3, iclass 21, count 0 2006.245.07:54:03.30#ibcon#about to read 4, iclass 21, count 0 2006.245.07:54:03.30#ibcon#read 4, iclass 21, count 0 2006.245.07:54:03.30#ibcon#about to read 5, iclass 21, count 0 2006.245.07:54:03.30#ibcon#read 5, iclass 21, count 0 2006.245.07:54:03.30#ibcon#about to read 6, iclass 21, count 0 2006.245.07:54:03.30#ibcon#read 6, iclass 21, count 0 2006.245.07:54:03.30#ibcon#end of sib2, iclass 21, count 0 2006.245.07:54:03.30#ibcon#*after write, iclass 21, count 0 2006.245.07:54:03.30#ibcon#*before return 0, iclass 21, count 0 2006.245.07:54:03.30#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:54:03.30#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.07:54:03.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.07:54:03.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.07:54:03.30$vc4f8/vblo=1,632.99 2006.245.07:54:03.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.07:54:03.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.07:54:03.30#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:03.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:54:03.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:54:03.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:54:03.30#ibcon#enter wrdev, iclass 23, count 0 2006.245.07:54:03.30#ibcon#first serial, iclass 23, count 0 2006.245.07:54:03.30#ibcon#enter sib2, iclass 23, count 0 2006.245.07:54:03.30#ibcon#flushed, iclass 23, count 0 2006.245.07:54:03.30#ibcon#about to write, iclass 23, count 0 2006.245.07:54:03.31#ibcon#wrote, iclass 23, count 0 2006.245.07:54:03.31#ibcon#about to read 3, iclass 23, count 0 2006.245.07:54:03.32#ibcon#read 3, iclass 23, count 0 2006.245.07:54:03.32#ibcon#about to read 4, iclass 23, count 0 2006.245.07:54:03.32#ibcon#read 4, iclass 23, count 0 2006.245.07:54:03.32#ibcon#about to read 5, iclass 23, count 0 2006.245.07:54:03.32#ibcon#read 5, iclass 23, count 0 2006.245.07:54:03.32#ibcon#about to read 6, iclass 23, count 0 2006.245.07:54:03.32#ibcon#read 6, iclass 23, count 0 2006.245.07:54:03.32#ibcon#end of sib2, iclass 23, count 0 2006.245.07:54:03.32#ibcon#*mode == 0, iclass 23, count 0 2006.245.07:54:03.32#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.07:54:03.32#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:54:03.32#ibcon#*before write, iclass 23, count 0 2006.245.07:54:03.32#ibcon#enter sib2, iclass 23, count 0 2006.245.07:54:03.32#ibcon#flushed, iclass 23, count 0 2006.245.07:54:03.32#ibcon#about to write, iclass 23, count 0 2006.245.07:54:03.32#ibcon#wrote, iclass 23, count 0 2006.245.07:54:03.32#ibcon#about to read 3, iclass 23, count 0 2006.245.07:54:03.36#ibcon#read 3, iclass 23, count 0 2006.245.07:54:03.36#ibcon#about to read 4, iclass 23, count 0 2006.245.07:54:03.36#ibcon#read 4, iclass 23, count 0 2006.245.07:54:03.36#ibcon#about to read 5, iclass 23, count 0 2006.245.07:54:03.36#ibcon#read 5, iclass 23, count 0 2006.245.07:54:03.36#ibcon#about to read 6, iclass 23, count 0 2006.245.07:54:03.36#ibcon#read 6, iclass 23, count 0 2006.245.07:54:03.36#ibcon#end of sib2, iclass 23, count 0 2006.245.07:54:03.36#ibcon#*after write, iclass 23, count 0 2006.245.07:54:03.36#ibcon#*before return 0, iclass 23, count 0 2006.245.07:54:03.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:54:03.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.07:54:03.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.07:54:03.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.07:54:03.36$vc4f8/vb=1,4 2006.245.07:54:03.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.07:54:03.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.07:54:03.36#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:03.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:54:03.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:54:03.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:54:03.36#ibcon#enter wrdev, iclass 25, count 2 2006.245.07:54:03.36#ibcon#first serial, iclass 25, count 2 2006.245.07:54:03.36#ibcon#enter sib2, iclass 25, count 2 2006.245.07:54:03.36#ibcon#flushed, iclass 25, count 2 2006.245.07:54:03.36#ibcon#about to write, iclass 25, count 2 2006.245.07:54:03.37#ibcon#wrote, iclass 25, count 2 2006.245.07:54:03.37#ibcon#about to read 3, iclass 25, count 2 2006.245.07:54:03.38#ibcon#read 3, iclass 25, count 2 2006.245.07:54:03.38#ibcon#about to read 4, iclass 25, count 2 2006.245.07:54:03.38#ibcon#read 4, iclass 25, count 2 2006.245.07:54:03.38#ibcon#about to read 5, iclass 25, count 2 2006.245.07:54:03.38#ibcon#read 5, iclass 25, count 2 2006.245.07:54:03.38#ibcon#about to read 6, iclass 25, count 2 2006.245.07:54:03.38#ibcon#read 6, iclass 25, count 2 2006.245.07:54:03.38#ibcon#end of sib2, iclass 25, count 2 2006.245.07:54:03.38#ibcon#*mode == 0, iclass 25, count 2 2006.245.07:54:03.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.07:54:03.38#ibcon#[27=AT01-04\r\n] 2006.245.07:54:03.38#ibcon#*before write, iclass 25, count 2 2006.245.07:54:03.38#ibcon#enter sib2, iclass 25, count 2 2006.245.07:54:03.38#ibcon#flushed, iclass 25, count 2 2006.245.07:54:03.38#ibcon#about to write, iclass 25, count 2 2006.245.07:54:03.38#ibcon#wrote, iclass 25, count 2 2006.245.07:54:03.38#ibcon#about to read 3, iclass 25, count 2 2006.245.07:54:03.41#ibcon#read 3, iclass 25, count 2 2006.245.07:54:03.41#ibcon#about to read 4, iclass 25, count 2 2006.245.07:54:03.41#ibcon#read 4, iclass 25, count 2 2006.245.07:54:03.41#ibcon#about to read 5, iclass 25, count 2 2006.245.07:54:03.41#ibcon#read 5, iclass 25, count 2 2006.245.07:54:03.41#ibcon#about to read 6, iclass 25, count 2 2006.245.07:54:03.41#ibcon#read 6, iclass 25, count 2 2006.245.07:54:03.41#ibcon#end of sib2, iclass 25, count 2 2006.245.07:54:03.41#ibcon#*after write, iclass 25, count 2 2006.245.07:54:03.41#ibcon#*before return 0, iclass 25, count 2 2006.245.07:54:03.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:54:03.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.07:54:03.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.07:54:03.41#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:03.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:54:03.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:54:03.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:54:03.53#ibcon#enter wrdev, iclass 25, count 0 2006.245.07:54:03.53#ibcon#first serial, iclass 25, count 0 2006.245.07:54:03.53#ibcon#enter sib2, iclass 25, count 0 2006.245.07:54:03.53#ibcon#flushed, iclass 25, count 0 2006.245.07:54:03.53#ibcon#about to write, iclass 25, count 0 2006.245.07:54:03.53#ibcon#wrote, iclass 25, count 0 2006.245.07:54:03.53#ibcon#about to read 3, iclass 25, count 0 2006.245.07:54:03.55#ibcon#read 3, iclass 25, count 0 2006.245.07:54:03.55#ibcon#about to read 4, iclass 25, count 0 2006.245.07:54:03.55#ibcon#read 4, iclass 25, count 0 2006.245.07:54:03.55#ibcon#about to read 5, iclass 25, count 0 2006.245.07:54:03.55#ibcon#read 5, iclass 25, count 0 2006.245.07:54:03.55#ibcon#about to read 6, iclass 25, count 0 2006.245.07:54:03.55#ibcon#read 6, iclass 25, count 0 2006.245.07:54:03.55#ibcon#end of sib2, iclass 25, count 0 2006.245.07:54:03.55#ibcon#*mode == 0, iclass 25, count 0 2006.245.07:54:03.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.07:54:03.55#ibcon#[27=USB\r\n] 2006.245.07:54:03.55#ibcon#*before write, iclass 25, count 0 2006.245.07:54:03.55#ibcon#enter sib2, iclass 25, count 0 2006.245.07:54:03.55#ibcon#flushed, iclass 25, count 0 2006.245.07:54:03.55#ibcon#about to write, iclass 25, count 0 2006.245.07:54:03.55#ibcon#wrote, iclass 25, count 0 2006.245.07:54:03.55#ibcon#about to read 3, iclass 25, count 0 2006.245.07:54:03.58#ibcon#read 3, iclass 25, count 0 2006.245.07:54:03.58#ibcon#about to read 4, iclass 25, count 0 2006.245.07:54:03.58#ibcon#read 4, iclass 25, count 0 2006.245.07:54:03.58#ibcon#about to read 5, iclass 25, count 0 2006.245.07:54:03.58#ibcon#read 5, iclass 25, count 0 2006.245.07:54:03.58#ibcon#about to read 6, iclass 25, count 0 2006.245.07:54:03.58#ibcon#read 6, iclass 25, count 0 2006.245.07:54:03.58#ibcon#end of sib2, iclass 25, count 0 2006.245.07:54:03.58#ibcon#*after write, iclass 25, count 0 2006.245.07:54:03.58#ibcon#*before return 0, iclass 25, count 0 2006.245.07:54:03.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:54:03.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.07:54:03.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.07:54:03.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.07:54:03.58$vc4f8/vblo=2,640.99 2006.245.07:54:03.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.07:54:03.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.07:54:03.58#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:03.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:03.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:03.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:03.58#ibcon#enter wrdev, iclass 27, count 0 2006.245.07:54:03.58#ibcon#first serial, iclass 27, count 0 2006.245.07:54:03.58#ibcon#enter sib2, iclass 27, count 0 2006.245.07:54:03.58#ibcon#flushed, iclass 27, count 0 2006.245.07:54:03.58#ibcon#about to write, iclass 27, count 0 2006.245.07:54:03.58#ibcon#wrote, iclass 27, count 0 2006.245.07:54:03.59#ibcon#about to read 3, iclass 27, count 0 2006.245.07:54:03.60#ibcon#read 3, iclass 27, count 0 2006.245.07:54:03.60#ibcon#about to read 4, iclass 27, count 0 2006.245.07:54:03.60#ibcon#read 4, iclass 27, count 0 2006.245.07:54:03.60#ibcon#about to read 5, iclass 27, count 0 2006.245.07:54:03.60#ibcon#read 5, iclass 27, count 0 2006.245.07:54:03.60#ibcon#about to read 6, iclass 27, count 0 2006.245.07:54:03.60#ibcon#read 6, iclass 27, count 0 2006.245.07:54:03.60#ibcon#end of sib2, iclass 27, count 0 2006.245.07:54:03.60#ibcon#*mode == 0, iclass 27, count 0 2006.245.07:54:03.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.07:54:03.60#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:54:03.60#ibcon#*before write, iclass 27, count 0 2006.245.07:54:03.60#ibcon#enter sib2, iclass 27, count 0 2006.245.07:54:03.60#ibcon#flushed, iclass 27, count 0 2006.245.07:54:03.60#ibcon#about to write, iclass 27, count 0 2006.245.07:54:03.60#ibcon#wrote, iclass 27, count 0 2006.245.07:54:03.60#ibcon#about to read 3, iclass 27, count 0 2006.245.07:54:03.64#ibcon#read 3, iclass 27, count 0 2006.245.07:54:03.64#ibcon#about to read 4, iclass 27, count 0 2006.245.07:54:03.64#ibcon#read 4, iclass 27, count 0 2006.245.07:54:03.64#ibcon#about to read 5, iclass 27, count 0 2006.245.07:54:03.64#ibcon#read 5, iclass 27, count 0 2006.245.07:54:03.64#ibcon#about to read 6, iclass 27, count 0 2006.245.07:54:03.64#ibcon#read 6, iclass 27, count 0 2006.245.07:54:03.64#ibcon#end of sib2, iclass 27, count 0 2006.245.07:54:03.64#ibcon#*after write, iclass 27, count 0 2006.245.07:54:03.64#ibcon#*before return 0, iclass 27, count 0 2006.245.07:54:03.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:03.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.07:54:03.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.07:54:03.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.07:54:03.64$vc4f8/vb=2,4 2006.245.07:54:03.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.07:54:03.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.07:54:03.64#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:03.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:03.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:03.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:03.70#ibcon#enter wrdev, iclass 29, count 2 2006.245.07:54:03.70#ibcon#first serial, iclass 29, count 2 2006.245.07:54:03.70#ibcon#enter sib2, iclass 29, count 2 2006.245.07:54:03.70#ibcon#flushed, iclass 29, count 2 2006.245.07:54:03.70#ibcon#about to write, iclass 29, count 2 2006.245.07:54:03.70#ibcon#wrote, iclass 29, count 2 2006.245.07:54:03.70#ibcon#about to read 3, iclass 29, count 2 2006.245.07:54:03.72#ibcon#read 3, iclass 29, count 2 2006.245.07:54:03.72#ibcon#about to read 4, iclass 29, count 2 2006.245.07:54:03.72#ibcon#read 4, iclass 29, count 2 2006.245.07:54:03.72#ibcon#about to read 5, iclass 29, count 2 2006.245.07:54:03.72#ibcon#read 5, iclass 29, count 2 2006.245.07:54:03.72#ibcon#about to read 6, iclass 29, count 2 2006.245.07:54:03.72#ibcon#read 6, iclass 29, count 2 2006.245.07:54:03.72#ibcon#end of sib2, iclass 29, count 2 2006.245.07:54:03.72#ibcon#*mode == 0, iclass 29, count 2 2006.245.07:54:03.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.07:54:03.72#ibcon#[27=AT02-04\r\n] 2006.245.07:54:03.72#ibcon#*before write, iclass 29, count 2 2006.245.07:54:03.72#ibcon#enter sib2, iclass 29, count 2 2006.245.07:54:03.72#ibcon#flushed, iclass 29, count 2 2006.245.07:54:03.72#ibcon#about to write, iclass 29, count 2 2006.245.07:54:03.72#ibcon#wrote, iclass 29, count 2 2006.245.07:54:03.72#ibcon#about to read 3, iclass 29, count 2 2006.245.07:54:03.75#ibcon#read 3, iclass 29, count 2 2006.245.07:54:03.75#ibcon#about to read 4, iclass 29, count 2 2006.245.07:54:03.75#ibcon#read 4, iclass 29, count 2 2006.245.07:54:03.75#ibcon#about to read 5, iclass 29, count 2 2006.245.07:54:03.75#ibcon#read 5, iclass 29, count 2 2006.245.07:54:03.75#ibcon#about to read 6, iclass 29, count 2 2006.245.07:54:03.75#ibcon#read 6, iclass 29, count 2 2006.245.07:54:03.75#ibcon#end of sib2, iclass 29, count 2 2006.245.07:54:03.75#ibcon#*after write, iclass 29, count 2 2006.245.07:54:03.75#ibcon#*before return 0, iclass 29, count 2 2006.245.07:54:03.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:03.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.07:54:03.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.07:54:03.75#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:03.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:03.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:03.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:03.87#ibcon#enter wrdev, iclass 29, count 0 2006.245.07:54:03.87#ibcon#first serial, iclass 29, count 0 2006.245.07:54:03.87#ibcon#enter sib2, iclass 29, count 0 2006.245.07:54:03.87#ibcon#flushed, iclass 29, count 0 2006.245.07:54:03.87#ibcon#about to write, iclass 29, count 0 2006.245.07:54:03.87#ibcon#wrote, iclass 29, count 0 2006.245.07:54:03.87#ibcon#about to read 3, iclass 29, count 0 2006.245.07:54:03.89#ibcon#read 3, iclass 29, count 0 2006.245.07:54:03.89#ibcon#about to read 4, iclass 29, count 0 2006.245.07:54:03.89#ibcon#read 4, iclass 29, count 0 2006.245.07:54:03.89#ibcon#about to read 5, iclass 29, count 0 2006.245.07:54:03.89#ibcon#read 5, iclass 29, count 0 2006.245.07:54:03.89#ibcon#about to read 6, iclass 29, count 0 2006.245.07:54:03.89#ibcon#read 6, iclass 29, count 0 2006.245.07:54:03.89#ibcon#end of sib2, iclass 29, count 0 2006.245.07:54:03.89#ibcon#*mode == 0, iclass 29, count 0 2006.245.07:54:03.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.07:54:03.89#ibcon#[27=USB\r\n] 2006.245.07:54:03.89#ibcon#*before write, iclass 29, count 0 2006.245.07:54:03.89#ibcon#enter sib2, iclass 29, count 0 2006.245.07:54:03.89#ibcon#flushed, iclass 29, count 0 2006.245.07:54:03.89#ibcon#about to write, iclass 29, count 0 2006.245.07:54:03.89#ibcon#wrote, iclass 29, count 0 2006.245.07:54:03.89#ibcon#about to read 3, iclass 29, count 0 2006.245.07:54:03.92#ibcon#read 3, iclass 29, count 0 2006.245.07:54:03.92#ibcon#about to read 4, iclass 29, count 0 2006.245.07:54:03.92#ibcon#read 4, iclass 29, count 0 2006.245.07:54:03.92#ibcon#about to read 5, iclass 29, count 0 2006.245.07:54:03.92#ibcon#read 5, iclass 29, count 0 2006.245.07:54:03.92#ibcon#about to read 6, iclass 29, count 0 2006.245.07:54:03.92#ibcon#read 6, iclass 29, count 0 2006.245.07:54:03.92#ibcon#end of sib2, iclass 29, count 0 2006.245.07:54:03.92#ibcon#*after write, iclass 29, count 0 2006.245.07:54:03.92#ibcon#*before return 0, iclass 29, count 0 2006.245.07:54:03.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:03.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.07:54:03.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.07:54:03.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.07:54:03.92$vc4f8/vblo=3,656.99 2006.245.07:54:03.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.07:54:03.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.07:54:03.92#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:03.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:03.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:03.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:03.92#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:54:03.92#ibcon#first serial, iclass 31, count 0 2006.245.07:54:03.92#ibcon#enter sib2, iclass 31, count 0 2006.245.07:54:03.92#ibcon#flushed, iclass 31, count 0 2006.245.07:54:03.92#ibcon#about to write, iclass 31, count 0 2006.245.07:54:03.92#ibcon#wrote, iclass 31, count 0 2006.245.07:54:03.93#ibcon#about to read 3, iclass 31, count 0 2006.245.07:54:03.94#ibcon#read 3, iclass 31, count 0 2006.245.07:54:03.94#ibcon#about to read 4, iclass 31, count 0 2006.245.07:54:03.94#ibcon#read 4, iclass 31, count 0 2006.245.07:54:03.94#ibcon#about to read 5, iclass 31, count 0 2006.245.07:54:03.94#ibcon#read 5, iclass 31, count 0 2006.245.07:54:03.94#ibcon#about to read 6, iclass 31, count 0 2006.245.07:54:03.94#ibcon#read 6, iclass 31, count 0 2006.245.07:54:03.94#ibcon#end of sib2, iclass 31, count 0 2006.245.07:54:03.94#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:54:03.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:54:03.94#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:54:03.94#ibcon#*before write, iclass 31, count 0 2006.245.07:54:03.94#ibcon#enter sib2, iclass 31, count 0 2006.245.07:54:03.94#ibcon#flushed, iclass 31, count 0 2006.245.07:54:03.94#ibcon#about to write, iclass 31, count 0 2006.245.07:54:03.94#ibcon#wrote, iclass 31, count 0 2006.245.07:54:03.94#ibcon#about to read 3, iclass 31, count 0 2006.245.07:54:03.98#ibcon#read 3, iclass 31, count 0 2006.245.07:54:03.98#ibcon#about to read 4, iclass 31, count 0 2006.245.07:54:03.98#ibcon#read 4, iclass 31, count 0 2006.245.07:54:03.98#ibcon#about to read 5, iclass 31, count 0 2006.245.07:54:03.98#ibcon#read 5, iclass 31, count 0 2006.245.07:54:03.98#ibcon#about to read 6, iclass 31, count 0 2006.245.07:54:03.98#ibcon#read 6, iclass 31, count 0 2006.245.07:54:03.98#ibcon#end of sib2, iclass 31, count 0 2006.245.07:54:03.98#ibcon#*after write, iclass 31, count 0 2006.245.07:54:03.98#ibcon#*before return 0, iclass 31, count 0 2006.245.07:54:03.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:03.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.07:54:03.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:54:03.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:54:03.98$vc4f8/vb=3,4 2006.245.07:54:03.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.07:54:03.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.07:54:03.98#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:03.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:04.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:04.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:04.05#ibcon#enter wrdev, iclass 33, count 2 2006.245.07:54:04.05#ibcon#first serial, iclass 33, count 2 2006.245.07:54:04.05#ibcon#enter sib2, iclass 33, count 2 2006.245.07:54:04.05#ibcon#flushed, iclass 33, count 2 2006.245.07:54:04.05#ibcon#about to write, iclass 33, count 2 2006.245.07:54:04.05#ibcon#wrote, iclass 33, count 2 2006.245.07:54:04.05#ibcon#about to read 3, iclass 33, count 2 2006.245.07:54:04.07#ibcon#read 3, iclass 33, count 2 2006.245.07:54:04.07#ibcon#about to read 4, iclass 33, count 2 2006.245.07:54:04.07#ibcon#read 4, iclass 33, count 2 2006.245.07:54:04.07#ibcon#about to read 5, iclass 33, count 2 2006.245.07:54:04.07#ibcon#read 5, iclass 33, count 2 2006.245.07:54:04.07#ibcon#about to read 6, iclass 33, count 2 2006.245.07:54:04.07#ibcon#read 6, iclass 33, count 2 2006.245.07:54:04.07#ibcon#end of sib2, iclass 33, count 2 2006.245.07:54:04.07#ibcon#*mode == 0, iclass 33, count 2 2006.245.07:54:04.07#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.07:54:04.07#ibcon#[27=AT03-04\r\n] 2006.245.07:54:04.07#ibcon#*before write, iclass 33, count 2 2006.245.07:54:04.07#ibcon#enter sib2, iclass 33, count 2 2006.245.07:54:04.07#ibcon#flushed, iclass 33, count 2 2006.245.07:54:04.07#ibcon#about to write, iclass 33, count 2 2006.245.07:54:04.07#ibcon#wrote, iclass 33, count 2 2006.245.07:54:04.07#ibcon#about to read 3, iclass 33, count 2 2006.245.07:54:04.09#ibcon#read 3, iclass 33, count 2 2006.245.07:54:04.09#ibcon#about to read 4, iclass 33, count 2 2006.245.07:54:04.09#ibcon#read 4, iclass 33, count 2 2006.245.07:54:04.09#ibcon#about to read 5, iclass 33, count 2 2006.245.07:54:04.09#ibcon#read 5, iclass 33, count 2 2006.245.07:54:04.09#ibcon#about to read 6, iclass 33, count 2 2006.245.07:54:04.09#ibcon#read 6, iclass 33, count 2 2006.245.07:54:04.09#ibcon#end of sib2, iclass 33, count 2 2006.245.07:54:04.09#ibcon#*after write, iclass 33, count 2 2006.245.07:54:04.09#ibcon#*before return 0, iclass 33, count 2 2006.245.07:54:04.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:04.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.07:54:04.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.07:54:04.09#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:04.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:04.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:04.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:04.21#ibcon#enter wrdev, iclass 33, count 0 2006.245.07:54:04.21#ibcon#first serial, iclass 33, count 0 2006.245.07:54:04.21#ibcon#enter sib2, iclass 33, count 0 2006.245.07:54:04.21#ibcon#flushed, iclass 33, count 0 2006.245.07:54:04.21#ibcon#about to write, iclass 33, count 0 2006.245.07:54:04.21#ibcon#wrote, iclass 33, count 0 2006.245.07:54:04.21#ibcon#about to read 3, iclass 33, count 0 2006.245.07:54:04.23#ibcon#read 3, iclass 33, count 0 2006.245.07:54:04.23#ibcon#about to read 4, iclass 33, count 0 2006.245.07:54:04.23#ibcon#read 4, iclass 33, count 0 2006.245.07:54:04.23#ibcon#about to read 5, iclass 33, count 0 2006.245.07:54:04.23#ibcon#read 5, iclass 33, count 0 2006.245.07:54:04.23#ibcon#about to read 6, iclass 33, count 0 2006.245.07:54:04.23#ibcon#read 6, iclass 33, count 0 2006.245.07:54:04.23#ibcon#end of sib2, iclass 33, count 0 2006.245.07:54:04.23#ibcon#*mode == 0, iclass 33, count 0 2006.245.07:54:04.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.07:54:04.23#ibcon#[27=USB\r\n] 2006.245.07:54:04.23#ibcon#*before write, iclass 33, count 0 2006.245.07:54:04.23#ibcon#enter sib2, iclass 33, count 0 2006.245.07:54:04.23#ibcon#flushed, iclass 33, count 0 2006.245.07:54:04.23#ibcon#about to write, iclass 33, count 0 2006.245.07:54:04.23#ibcon#wrote, iclass 33, count 0 2006.245.07:54:04.23#ibcon#about to read 3, iclass 33, count 0 2006.245.07:54:04.26#ibcon#read 3, iclass 33, count 0 2006.245.07:54:04.26#ibcon#about to read 4, iclass 33, count 0 2006.245.07:54:04.26#ibcon#read 4, iclass 33, count 0 2006.245.07:54:04.26#ibcon#about to read 5, iclass 33, count 0 2006.245.07:54:04.26#ibcon#read 5, iclass 33, count 0 2006.245.07:54:04.26#ibcon#about to read 6, iclass 33, count 0 2006.245.07:54:04.26#ibcon#read 6, iclass 33, count 0 2006.245.07:54:04.26#ibcon#end of sib2, iclass 33, count 0 2006.245.07:54:04.26#ibcon#*after write, iclass 33, count 0 2006.245.07:54:04.26#ibcon#*before return 0, iclass 33, count 0 2006.245.07:54:04.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:04.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.07:54:04.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.07:54:04.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.07:54:04.26$vc4f8/vblo=4,712.99 2006.245.07:54:04.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.07:54:04.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.07:54:04.26#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:04.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:04.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:04.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:04.27#ibcon#enter wrdev, iclass 35, count 0 2006.245.07:54:04.27#ibcon#first serial, iclass 35, count 0 2006.245.07:54:04.27#ibcon#enter sib2, iclass 35, count 0 2006.245.07:54:04.27#ibcon#flushed, iclass 35, count 0 2006.245.07:54:04.27#ibcon#about to write, iclass 35, count 0 2006.245.07:54:04.27#ibcon#wrote, iclass 35, count 0 2006.245.07:54:04.27#ibcon#about to read 3, iclass 35, count 0 2006.245.07:54:04.28#ibcon#read 3, iclass 35, count 0 2006.245.07:54:04.28#ibcon#about to read 4, iclass 35, count 0 2006.245.07:54:04.28#ibcon#read 4, iclass 35, count 0 2006.245.07:54:04.28#ibcon#about to read 5, iclass 35, count 0 2006.245.07:54:04.28#ibcon#read 5, iclass 35, count 0 2006.245.07:54:04.28#ibcon#about to read 6, iclass 35, count 0 2006.245.07:54:04.28#ibcon#read 6, iclass 35, count 0 2006.245.07:54:04.28#ibcon#end of sib2, iclass 35, count 0 2006.245.07:54:04.28#ibcon#*mode == 0, iclass 35, count 0 2006.245.07:54:04.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.07:54:04.28#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:54:04.28#ibcon#*before write, iclass 35, count 0 2006.245.07:54:04.28#ibcon#enter sib2, iclass 35, count 0 2006.245.07:54:04.28#ibcon#flushed, iclass 35, count 0 2006.245.07:54:04.28#ibcon#about to write, iclass 35, count 0 2006.245.07:54:04.28#ibcon#wrote, iclass 35, count 0 2006.245.07:54:04.28#ibcon#about to read 3, iclass 35, count 0 2006.245.07:54:04.32#ibcon#read 3, iclass 35, count 0 2006.245.07:54:04.32#ibcon#about to read 4, iclass 35, count 0 2006.245.07:54:04.32#ibcon#read 4, iclass 35, count 0 2006.245.07:54:04.32#ibcon#about to read 5, iclass 35, count 0 2006.245.07:54:04.32#ibcon#read 5, iclass 35, count 0 2006.245.07:54:04.32#ibcon#about to read 6, iclass 35, count 0 2006.245.07:54:04.32#ibcon#read 6, iclass 35, count 0 2006.245.07:54:04.32#ibcon#end of sib2, iclass 35, count 0 2006.245.07:54:04.32#ibcon#*after write, iclass 35, count 0 2006.245.07:54:04.32#ibcon#*before return 0, iclass 35, count 0 2006.245.07:54:04.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:04.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.07:54:04.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.07:54:04.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.07:54:04.32$vc4f8/vb=4,4 2006.245.07:54:04.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.07:54:04.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.07:54:04.32#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:04.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:04.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:04.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:04.38#ibcon#enter wrdev, iclass 37, count 2 2006.245.07:54:04.38#ibcon#first serial, iclass 37, count 2 2006.245.07:54:04.38#ibcon#enter sib2, iclass 37, count 2 2006.245.07:54:04.38#ibcon#flushed, iclass 37, count 2 2006.245.07:54:04.38#ibcon#about to write, iclass 37, count 2 2006.245.07:54:04.38#ibcon#wrote, iclass 37, count 2 2006.245.07:54:04.38#ibcon#about to read 3, iclass 37, count 2 2006.245.07:54:04.40#ibcon#read 3, iclass 37, count 2 2006.245.07:54:04.40#ibcon#about to read 4, iclass 37, count 2 2006.245.07:54:04.40#ibcon#read 4, iclass 37, count 2 2006.245.07:54:04.40#ibcon#about to read 5, iclass 37, count 2 2006.245.07:54:04.40#ibcon#read 5, iclass 37, count 2 2006.245.07:54:04.40#ibcon#about to read 6, iclass 37, count 2 2006.245.07:54:04.40#ibcon#read 6, iclass 37, count 2 2006.245.07:54:04.40#ibcon#end of sib2, iclass 37, count 2 2006.245.07:54:04.40#ibcon#*mode == 0, iclass 37, count 2 2006.245.07:54:04.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.07:54:04.40#ibcon#[27=AT04-04\r\n] 2006.245.07:54:04.40#ibcon#*before write, iclass 37, count 2 2006.245.07:54:04.40#ibcon#enter sib2, iclass 37, count 2 2006.245.07:54:04.40#ibcon#flushed, iclass 37, count 2 2006.245.07:54:04.40#ibcon#about to write, iclass 37, count 2 2006.245.07:54:04.40#ibcon#wrote, iclass 37, count 2 2006.245.07:54:04.40#ibcon#about to read 3, iclass 37, count 2 2006.245.07:54:04.43#ibcon#read 3, iclass 37, count 2 2006.245.07:54:04.43#ibcon#about to read 4, iclass 37, count 2 2006.245.07:54:04.43#ibcon#read 4, iclass 37, count 2 2006.245.07:54:04.43#ibcon#about to read 5, iclass 37, count 2 2006.245.07:54:04.43#ibcon#read 5, iclass 37, count 2 2006.245.07:54:04.43#ibcon#about to read 6, iclass 37, count 2 2006.245.07:54:04.43#ibcon#read 6, iclass 37, count 2 2006.245.07:54:04.43#ibcon#end of sib2, iclass 37, count 2 2006.245.07:54:04.43#ibcon#*after write, iclass 37, count 2 2006.245.07:54:04.43#ibcon#*before return 0, iclass 37, count 2 2006.245.07:54:04.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:04.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.07:54:04.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.07:54:04.43#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:04.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:04.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:04.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:04.55#ibcon#enter wrdev, iclass 37, count 0 2006.245.07:54:04.55#ibcon#first serial, iclass 37, count 0 2006.245.07:54:04.55#ibcon#enter sib2, iclass 37, count 0 2006.245.07:54:04.55#ibcon#flushed, iclass 37, count 0 2006.245.07:54:04.55#ibcon#about to write, iclass 37, count 0 2006.245.07:54:04.55#ibcon#wrote, iclass 37, count 0 2006.245.07:54:04.55#ibcon#about to read 3, iclass 37, count 0 2006.245.07:54:04.57#ibcon#read 3, iclass 37, count 0 2006.245.07:54:04.57#ibcon#about to read 4, iclass 37, count 0 2006.245.07:54:04.57#ibcon#read 4, iclass 37, count 0 2006.245.07:54:04.57#ibcon#about to read 5, iclass 37, count 0 2006.245.07:54:04.57#ibcon#read 5, iclass 37, count 0 2006.245.07:54:04.57#ibcon#about to read 6, iclass 37, count 0 2006.245.07:54:04.57#ibcon#read 6, iclass 37, count 0 2006.245.07:54:04.57#ibcon#end of sib2, iclass 37, count 0 2006.245.07:54:04.57#ibcon#*mode == 0, iclass 37, count 0 2006.245.07:54:04.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.07:54:04.57#ibcon#[27=USB\r\n] 2006.245.07:54:04.57#ibcon#*before write, iclass 37, count 0 2006.245.07:54:04.57#ibcon#enter sib2, iclass 37, count 0 2006.245.07:54:04.57#ibcon#flushed, iclass 37, count 0 2006.245.07:54:04.57#ibcon#about to write, iclass 37, count 0 2006.245.07:54:04.57#ibcon#wrote, iclass 37, count 0 2006.245.07:54:04.57#ibcon#about to read 3, iclass 37, count 0 2006.245.07:54:04.60#ibcon#read 3, iclass 37, count 0 2006.245.07:54:04.60#ibcon#about to read 4, iclass 37, count 0 2006.245.07:54:04.60#ibcon#read 4, iclass 37, count 0 2006.245.07:54:04.60#ibcon#about to read 5, iclass 37, count 0 2006.245.07:54:04.60#ibcon#read 5, iclass 37, count 0 2006.245.07:54:04.60#ibcon#about to read 6, iclass 37, count 0 2006.245.07:54:04.60#ibcon#read 6, iclass 37, count 0 2006.245.07:54:04.60#ibcon#end of sib2, iclass 37, count 0 2006.245.07:54:04.60#ibcon#*after write, iclass 37, count 0 2006.245.07:54:04.60#ibcon#*before return 0, iclass 37, count 0 2006.245.07:54:04.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:04.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.07:54:04.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.07:54:04.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.07:54:04.60$vc4f8/vblo=5,744.99 2006.245.07:54:04.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.07:54:04.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.07:54:04.60#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:04.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:04.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:04.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:04.60#ibcon#enter wrdev, iclass 39, count 0 2006.245.07:54:04.60#ibcon#first serial, iclass 39, count 0 2006.245.07:54:04.60#ibcon#enter sib2, iclass 39, count 0 2006.245.07:54:04.60#ibcon#flushed, iclass 39, count 0 2006.245.07:54:04.60#ibcon#about to write, iclass 39, count 0 2006.245.07:54:04.60#ibcon#wrote, iclass 39, count 0 2006.245.07:54:04.61#ibcon#about to read 3, iclass 39, count 0 2006.245.07:54:04.62#ibcon#read 3, iclass 39, count 0 2006.245.07:54:04.62#ibcon#about to read 4, iclass 39, count 0 2006.245.07:54:04.62#ibcon#read 4, iclass 39, count 0 2006.245.07:54:04.62#ibcon#about to read 5, iclass 39, count 0 2006.245.07:54:04.62#ibcon#read 5, iclass 39, count 0 2006.245.07:54:04.62#ibcon#about to read 6, iclass 39, count 0 2006.245.07:54:04.62#ibcon#read 6, iclass 39, count 0 2006.245.07:54:04.62#ibcon#end of sib2, iclass 39, count 0 2006.245.07:54:04.62#ibcon#*mode == 0, iclass 39, count 0 2006.245.07:54:04.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.07:54:04.62#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:54:04.62#ibcon#*before write, iclass 39, count 0 2006.245.07:54:04.62#ibcon#enter sib2, iclass 39, count 0 2006.245.07:54:04.62#ibcon#flushed, iclass 39, count 0 2006.245.07:54:04.62#ibcon#about to write, iclass 39, count 0 2006.245.07:54:04.62#ibcon#wrote, iclass 39, count 0 2006.245.07:54:04.62#ibcon#about to read 3, iclass 39, count 0 2006.245.07:54:04.66#ibcon#read 3, iclass 39, count 0 2006.245.07:54:04.66#ibcon#about to read 4, iclass 39, count 0 2006.245.07:54:04.66#ibcon#read 4, iclass 39, count 0 2006.245.07:54:04.66#ibcon#about to read 5, iclass 39, count 0 2006.245.07:54:04.66#ibcon#read 5, iclass 39, count 0 2006.245.07:54:04.66#ibcon#about to read 6, iclass 39, count 0 2006.245.07:54:04.66#ibcon#read 6, iclass 39, count 0 2006.245.07:54:04.66#ibcon#end of sib2, iclass 39, count 0 2006.245.07:54:04.66#ibcon#*after write, iclass 39, count 0 2006.245.07:54:04.66#ibcon#*before return 0, iclass 39, count 0 2006.245.07:54:04.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:04.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.07:54:04.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.07:54:04.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.07:54:04.66$vc4f8/vb=5,3 2006.245.07:54:04.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.07:54:04.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.07:54:04.66#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:04.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:04.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:04.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:04.72#ibcon#enter wrdev, iclass 3, count 2 2006.245.07:54:04.72#ibcon#first serial, iclass 3, count 2 2006.245.07:54:04.72#ibcon#enter sib2, iclass 3, count 2 2006.245.07:54:04.72#ibcon#flushed, iclass 3, count 2 2006.245.07:54:04.72#ibcon#about to write, iclass 3, count 2 2006.245.07:54:04.72#ibcon#wrote, iclass 3, count 2 2006.245.07:54:04.72#ibcon#about to read 3, iclass 3, count 2 2006.245.07:54:04.74#ibcon#read 3, iclass 3, count 2 2006.245.07:54:04.74#ibcon#about to read 4, iclass 3, count 2 2006.245.07:54:04.74#ibcon#read 4, iclass 3, count 2 2006.245.07:54:04.74#ibcon#about to read 5, iclass 3, count 2 2006.245.07:54:04.74#ibcon#read 5, iclass 3, count 2 2006.245.07:54:04.74#ibcon#about to read 6, iclass 3, count 2 2006.245.07:54:04.74#ibcon#read 6, iclass 3, count 2 2006.245.07:54:04.74#ibcon#end of sib2, iclass 3, count 2 2006.245.07:54:04.74#ibcon#*mode == 0, iclass 3, count 2 2006.245.07:54:04.74#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.07:54:04.74#ibcon#[27=AT05-03\r\n] 2006.245.07:54:04.74#ibcon#*before write, iclass 3, count 2 2006.245.07:54:04.74#ibcon#enter sib2, iclass 3, count 2 2006.245.07:54:04.74#ibcon#flushed, iclass 3, count 2 2006.245.07:54:04.74#ibcon#about to write, iclass 3, count 2 2006.245.07:54:04.74#ibcon#wrote, iclass 3, count 2 2006.245.07:54:04.74#ibcon#about to read 3, iclass 3, count 2 2006.245.07:54:04.77#ibcon#read 3, iclass 3, count 2 2006.245.07:54:04.77#ibcon#about to read 4, iclass 3, count 2 2006.245.07:54:04.77#ibcon#read 4, iclass 3, count 2 2006.245.07:54:04.77#ibcon#about to read 5, iclass 3, count 2 2006.245.07:54:04.77#ibcon#read 5, iclass 3, count 2 2006.245.07:54:04.77#ibcon#about to read 6, iclass 3, count 2 2006.245.07:54:04.77#ibcon#read 6, iclass 3, count 2 2006.245.07:54:04.77#ibcon#end of sib2, iclass 3, count 2 2006.245.07:54:04.77#ibcon#*after write, iclass 3, count 2 2006.245.07:54:04.77#ibcon#*before return 0, iclass 3, count 2 2006.245.07:54:04.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:04.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.07:54:04.77#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.07:54:04.77#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:04.77#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:04.89#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:04.89#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:04.89#ibcon#enter wrdev, iclass 3, count 0 2006.245.07:54:04.89#ibcon#first serial, iclass 3, count 0 2006.245.07:54:04.89#ibcon#enter sib2, iclass 3, count 0 2006.245.07:54:04.89#ibcon#flushed, iclass 3, count 0 2006.245.07:54:04.89#ibcon#about to write, iclass 3, count 0 2006.245.07:54:04.89#ibcon#wrote, iclass 3, count 0 2006.245.07:54:04.89#ibcon#about to read 3, iclass 3, count 0 2006.245.07:54:04.91#ibcon#read 3, iclass 3, count 0 2006.245.07:54:04.91#ibcon#about to read 4, iclass 3, count 0 2006.245.07:54:04.91#ibcon#read 4, iclass 3, count 0 2006.245.07:54:04.91#ibcon#about to read 5, iclass 3, count 0 2006.245.07:54:04.91#ibcon#read 5, iclass 3, count 0 2006.245.07:54:04.91#ibcon#about to read 6, iclass 3, count 0 2006.245.07:54:04.91#ibcon#read 6, iclass 3, count 0 2006.245.07:54:04.91#ibcon#end of sib2, iclass 3, count 0 2006.245.07:54:04.91#ibcon#*mode == 0, iclass 3, count 0 2006.245.07:54:04.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.07:54:04.91#ibcon#[27=USB\r\n] 2006.245.07:54:04.91#ibcon#*before write, iclass 3, count 0 2006.245.07:54:04.91#ibcon#enter sib2, iclass 3, count 0 2006.245.07:54:04.91#ibcon#flushed, iclass 3, count 0 2006.245.07:54:04.91#ibcon#about to write, iclass 3, count 0 2006.245.07:54:04.91#ibcon#wrote, iclass 3, count 0 2006.245.07:54:04.91#ibcon#about to read 3, iclass 3, count 0 2006.245.07:54:04.94#ibcon#read 3, iclass 3, count 0 2006.245.07:54:04.94#ibcon#about to read 4, iclass 3, count 0 2006.245.07:54:04.94#ibcon#read 4, iclass 3, count 0 2006.245.07:54:04.94#ibcon#about to read 5, iclass 3, count 0 2006.245.07:54:04.94#ibcon#read 5, iclass 3, count 0 2006.245.07:54:04.94#ibcon#about to read 6, iclass 3, count 0 2006.245.07:54:04.94#ibcon#read 6, iclass 3, count 0 2006.245.07:54:04.94#ibcon#end of sib2, iclass 3, count 0 2006.245.07:54:04.94#ibcon#*after write, iclass 3, count 0 2006.245.07:54:04.94#ibcon#*before return 0, iclass 3, count 0 2006.245.07:54:04.94#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:04.94#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.07:54:04.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.07:54:04.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.07:54:04.94$vc4f8/vblo=6,752.99 2006.245.07:54:04.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.07:54:04.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.07:54:04.94#ibcon#ireg 17 cls_cnt 0 2006.245.07:54:04.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:04.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:04.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:04.94#ibcon#enter wrdev, iclass 5, count 0 2006.245.07:54:04.94#ibcon#first serial, iclass 5, count 0 2006.245.07:54:04.94#ibcon#enter sib2, iclass 5, count 0 2006.245.07:54:04.94#ibcon#flushed, iclass 5, count 0 2006.245.07:54:04.94#ibcon#about to write, iclass 5, count 0 2006.245.07:54:04.94#ibcon#wrote, iclass 5, count 0 2006.245.07:54:04.95#ibcon#about to read 3, iclass 5, count 0 2006.245.07:54:04.96#ibcon#read 3, iclass 5, count 0 2006.245.07:54:04.96#ibcon#about to read 4, iclass 5, count 0 2006.245.07:54:04.96#ibcon#read 4, iclass 5, count 0 2006.245.07:54:04.96#ibcon#about to read 5, iclass 5, count 0 2006.245.07:54:04.96#ibcon#read 5, iclass 5, count 0 2006.245.07:54:04.96#ibcon#about to read 6, iclass 5, count 0 2006.245.07:54:04.96#ibcon#read 6, iclass 5, count 0 2006.245.07:54:04.96#ibcon#end of sib2, iclass 5, count 0 2006.245.07:54:04.96#ibcon#*mode == 0, iclass 5, count 0 2006.245.07:54:04.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.07:54:04.96#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:54:04.96#ibcon#*before write, iclass 5, count 0 2006.245.07:54:04.96#ibcon#enter sib2, iclass 5, count 0 2006.245.07:54:04.96#ibcon#flushed, iclass 5, count 0 2006.245.07:54:04.96#ibcon#about to write, iclass 5, count 0 2006.245.07:54:04.96#ibcon#wrote, iclass 5, count 0 2006.245.07:54:04.96#ibcon#about to read 3, iclass 5, count 0 2006.245.07:54:05.00#ibcon#read 3, iclass 5, count 0 2006.245.07:54:05.00#ibcon#about to read 4, iclass 5, count 0 2006.245.07:54:05.00#ibcon#read 4, iclass 5, count 0 2006.245.07:54:05.00#ibcon#about to read 5, iclass 5, count 0 2006.245.07:54:05.00#ibcon#read 5, iclass 5, count 0 2006.245.07:54:05.00#ibcon#about to read 6, iclass 5, count 0 2006.245.07:54:05.00#ibcon#read 6, iclass 5, count 0 2006.245.07:54:05.00#ibcon#end of sib2, iclass 5, count 0 2006.245.07:54:05.00#ibcon#*after write, iclass 5, count 0 2006.245.07:54:05.00#ibcon#*before return 0, iclass 5, count 0 2006.245.07:54:05.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:05.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.07:54:05.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.07:54:05.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.07:54:05.00$vc4f8/vb=6,3 2006.245.07:54:05.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.07:54:05.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.07:54:05.00#ibcon#ireg 11 cls_cnt 2 2006.245.07:54:05.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:05.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:05.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:05.06#ibcon#enter wrdev, iclass 7, count 2 2006.245.07:54:05.06#ibcon#first serial, iclass 7, count 2 2006.245.07:54:05.06#ibcon#enter sib2, iclass 7, count 2 2006.245.07:54:05.06#ibcon#flushed, iclass 7, count 2 2006.245.07:54:05.06#ibcon#about to write, iclass 7, count 2 2006.245.07:54:05.06#ibcon#wrote, iclass 7, count 2 2006.245.07:54:05.06#ibcon#about to read 3, iclass 7, count 2 2006.245.07:54:05.08#ibcon#read 3, iclass 7, count 2 2006.245.07:54:05.08#ibcon#about to read 4, iclass 7, count 2 2006.245.07:54:05.08#ibcon#read 4, iclass 7, count 2 2006.245.07:54:05.08#ibcon#about to read 5, iclass 7, count 2 2006.245.07:54:05.08#ibcon#read 5, iclass 7, count 2 2006.245.07:54:05.08#ibcon#about to read 6, iclass 7, count 2 2006.245.07:54:05.08#ibcon#read 6, iclass 7, count 2 2006.245.07:54:05.08#ibcon#end of sib2, iclass 7, count 2 2006.245.07:54:05.08#ibcon#*mode == 0, iclass 7, count 2 2006.245.07:54:05.08#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.07:54:05.08#ibcon#[27=AT06-03\r\n] 2006.245.07:54:05.08#ibcon#*before write, iclass 7, count 2 2006.245.07:54:05.08#ibcon#enter sib2, iclass 7, count 2 2006.245.07:54:05.08#ibcon#flushed, iclass 7, count 2 2006.245.07:54:05.08#ibcon#about to write, iclass 7, count 2 2006.245.07:54:05.08#ibcon#wrote, iclass 7, count 2 2006.245.07:54:05.08#ibcon#about to read 3, iclass 7, count 2 2006.245.07:54:05.11#ibcon#read 3, iclass 7, count 2 2006.245.07:54:05.11#ibcon#about to read 4, iclass 7, count 2 2006.245.07:54:05.11#ibcon#read 4, iclass 7, count 2 2006.245.07:54:05.11#ibcon#about to read 5, iclass 7, count 2 2006.245.07:54:05.11#ibcon#read 5, iclass 7, count 2 2006.245.07:54:05.11#ibcon#about to read 6, iclass 7, count 2 2006.245.07:54:05.11#ibcon#read 6, iclass 7, count 2 2006.245.07:54:05.11#ibcon#end of sib2, iclass 7, count 2 2006.245.07:54:05.11#ibcon#*after write, iclass 7, count 2 2006.245.07:54:05.11#ibcon#*before return 0, iclass 7, count 2 2006.245.07:54:05.11#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:05.11#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.07:54:05.11#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.07:54:05.11#ibcon#ireg 7 cls_cnt 0 2006.245.07:54:05.11#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:05.23#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:05.23#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:05.23#ibcon#enter wrdev, iclass 7, count 0 2006.245.07:54:05.23#ibcon#first serial, iclass 7, count 0 2006.245.07:54:05.23#ibcon#enter sib2, iclass 7, count 0 2006.245.07:54:05.23#ibcon#flushed, iclass 7, count 0 2006.245.07:54:05.23#ibcon#about to write, iclass 7, count 0 2006.245.07:54:05.23#ibcon#wrote, iclass 7, count 0 2006.245.07:54:05.23#ibcon#about to read 3, iclass 7, count 0 2006.245.07:54:05.25#ibcon#read 3, iclass 7, count 0 2006.245.07:54:05.25#ibcon#about to read 4, iclass 7, count 0 2006.245.07:54:05.25#ibcon#read 4, iclass 7, count 0 2006.245.07:54:05.25#ibcon#about to read 5, iclass 7, count 0 2006.245.07:54:05.25#ibcon#read 5, iclass 7, count 0 2006.245.07:54:05.25#ibcon#about to read 6, iclass 7, count 0 2006.245.07:54:05.25#ibcon#read 6, iclass 7, count 0 2006.245.07:54:05.25#ibcon#end of sib2, iclass 7, count 0 2006.245.07:54:05.25#ibcon#*mode == 0, iclass 7, count 0 2006.245.07:54:05.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.07:54:05.25#ibcon#[27=USB\r\n] 2006.245.07:54:05.25#ibcon#*before write, iclass 7, count 0 2006.245.07:54:05.25#ibcon#enter sib2, iclass 7, count 0 2006.245.07:54:05.25#ibcon#flushed, iclass 7, count 0 2006.245.07:54:05.25#ibcon#about to write, iclass 7, count 0 2006.245.07:54:05.25#ibcon#wrote, iclass 7, count 0 2006.245.07:54:05.25#ibcon#about to read 3, iclass 7, count 0 2006.245.07:54:05.28#ibcon#read 3, iclass 7, count 0 2006.245.07:54:05.28#ibcon#about to read 4, iclass 7, count 0 2006.245.07:54:05.28#ibcon#read 4, iclass 7, count 0 2006.245.07:54:05.28#ibcon#about to read 5, iclass 7, count 0 2006.245.07:54:05.28#ibcon#read 5, iclass 7, count 0 2006.245.07:54:05.28#ibcon#about to read 6, iclass 7, count 0 2006.245.07:54:05.28#ibcon#read 6, iclass 7, count 0 2006.245.07:54:05.28#ibcon#end of sib2, iclass 7, count 0 2006.245.07:54:05.28#ibcon#*after write, iclass 7, count 0 2006.245.07:54:05.28#ibcon#*before return 0, iclass 7, count 0 2006.245.07:54:05.28#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:05.28#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.07:54:05.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.07:54:05.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.07:54:05.28$vc4f8/vabw=wide 2006.245.07:54:05.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.07:54:05.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.07:54:05.28#ibcon#ireg 8 cls_cnt 0 2006.245.07:54:05.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:05.28#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:05.28#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:05.28#ibcon#enter wrdev, iclass 11, count 0 2006.245.07:54:05.28#ibcon#first serial, iclass 11, count 0 2006.245.07:54:05.28#ibcon#enter sib2, iclass 11, count 0 2006.245.07:54:05.29#ibcon#flushed, iclass 11, count 0 2006.245.07:54:05.29#ibcon#about to write, iclass 11, count 0 2006.245.07:54:05.29#ibcon#wrote, iclass 11, count 0 2006.245.07:54:05.29#ibcon#about to read 3, iclass 11, count 0 2006.245.07:54:05.30#ibcon#read 3, iclass 11, count 0 2006.245.07:54:05.30#ibcon#about to read 4, iclass 11, count 0 2006.245.07:54:05.30#ibcon#read 4, iclass 11, count 0 2006.245.07:54:05.30#ibcon#about to read 5, iclass 11, count 0 2006.245.07:54:05.30#ibcon#read 5, iclass 11, count 0 2006.245.07:54:05.30#ibcon#about to read 6, iclass 11, count 0 2006.245.07:54:05.30#ibcon#read 6, iclass 11, count 0 2006.245.07:54:05.30#ibcon#end of sib2, iclass 11, count 0 2006.245.07:54:05.30#ibcon#*mode == 0, iclass 11, count 0 2006.245.07:54:05.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.07:54:05.30#ibcon#[25=BW32\r\n] 2006.245.07:54:05.30#ibcon#*before write, iclass 11, count 0 2006.245.07:54:05.30#ibcon#enter sib2, iclass 11, count 0 2006.245.07:54:05.30#ibcon#flushed, iclass 11, count 0 2006.245.07:54:05.30#ibcon#about to write, iclass 11, count 0 2006.245.07:54:05.30#ibcon#wrote, iclass 11, count 0 2006.245.07:54:05.30#ibcon#about to read 3, iclass 11, count 0 2006.245.07:54:05.33#ibcon#read 3, iclass 11, count 0 2006.245.07:54:05.33#ibcon#about to read 4, iclass 11, count 0 2006.245.07:54:05.33#ibcon#read 4, iclass 11, count 0 2006.245.07:54:05.33#ibcon#about to read 5, iclass 11, count 0 2006.245.07:54:05.33#ibcon#read 5, iclass 11, count 0 2006.245.07:54:05.33#ibcon#about to read 6, iclass 11, count 0 2006.245.07:54:05.33#ibcon#read 6, iclass 11, count 0 2006.245.07:54:05.33#ibcon#end of sib2, iclass 11, count 0 2006.245.07:54:05.33#ibcon#*after write, iclass 11, count 0 2006.245.07:54:05.33#ibcon#*before return 0, iclass 11, count 0 2006.245.07:54:05.33#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:05.33#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.07:54:05.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.07:54:05.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.07:54:05.33$vc4f8/vbbw=wide 2006.245.07:54:05.33#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.07:54:05.33#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.07:54:05.33#ibcon#ireg 8 cls_cnt 0 2006.245.07:54:05.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:54:05.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:54:05.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:54:05.40#ibcon#enter wrdev, iclass 13, count 0 2006.245.07:54:05.40#ibcon#first serial, iclass 13, count 0 2006.245.07:54:05.40#ibcon#enter sib2, iclass 13, count 0 2006.245.07:54:05.40#ibcon#flushed, iclass 13, count 0 2006.245.07:54:05.40#ibcon#about to write, iclass 13, count 0 2006.245.07:54:05.40#ibcon#wrote, iclass 13, count 0 2006.245.07:54:05.40#ibcon#about to read 3, iclass 13, count 0 2006.245.07:54:05.42#ibcon#read 3, iclass 13, count 0 2006.245.07:54:05.42#ibcon#about to read 4, iclass 13, count 0 2006.245.07:54:05.42#ibcon#read 4, iclass 13, count 0 2006.245.07:54:05.42#ibcon#about to read 5, iclass 13, count 0 2006.245.07:54:05.42#ibcon#read 5, iclass 13, count 0 2006.245.07:54:05.42#ibcon#about to read 6, iclass 13, count 0 2006.245.07:54:05.42#ibcon#read 6, iclass 13, count 0 2006.245.07:54:05.42#ibcon#end of sib2, iclass 13, count 0 2006.245.07:54:05.42#ibcon#*mode == 0, iclass 13, count 0 2006.245.07:54:05.42#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.07:54:05.42#ibcon#[27=BW32\r\n] 2006.245.07:54:05.42#ibcon#*before write, iclass 13, count 0 2006.245.07:54:05.42#ibcon#enter sib2, iclass 13, count 0 2006.245.07:54:05.42#ibcon#flushed, iclass 13, count 0 2006.245.07:54:05.42#ibcon#about to write, iclass 13, count 0 2006.245.07:54:05.42#ibcon#wrote, iclass 13, count 0 2006.245.07:54:05.42#ibcon#about to read 3, iclass 13, count 0 2006.245.07:54:05.45#ibcon#read 3, iclass 13, count 0 2006.245.07:54:05.45#ibcon#about to read 4, iclass 13, count 0 2006.245.07:54:05.45#ibcon#read 4, iclass 13, count 0 2006.245.07:54:05.45#ibcon#about to read 5, iclass 13, count 0 2006.245.07:54:05.45#ibcon#read 5, iclass 13, count 0 2006.245.07:54:05.45#ibcon#about to read 6, iclass 13, count 0 2006.245.07:54:05.45#ibcon#read 6, iclass 13, count 0 2006.245.07:54:05.45#ibcon#end of sib2, iclass 13, count 0 2006.245.07:54:05.45#ibcon#*after write, iclass 13, count 0 2006.245.07:54:05.45#ibcon#*before return 0, iclass 13, count 0 2006.245.07:54:05.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:54:05.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.07:54:05.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.07:54:05.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.07:54:05.45$4f8m12a/ifd4f 2006.245.07:54:05.45$ifd4f/lo= 2006.245.07:54:05.46$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:54:05.46$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:54:05.46$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:54:05.46$ifd4f/patch= 2006.245.07:54:05.46$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:54:05.46$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:54:05.46$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:54:05.46$4f8m12a/"form=m,16.000,1:2 2006.245.07:54:05.46$4f8m12a/"tpicd 2006.245.07:54:05.46$4f8m12a/echo=off 2006.245.07:54:05.46$4f8m12a/xlog=off 2006.245.07:54:05.46:!2006.245.07:55:20 2006.245.07:54:18.14#trakl#Source acquired 2006.245.07:54:20.14#flagr#flagr/antenna,acquired 2006.245.07:55:20.01:preob 2006.245.07:55:21.13/onsource/TRACKING 2006.245.07:55:21.13:!2006.245.07:55:30 2006.245.07:55:30.00:data_valid=on 2006.245.07:55:30.00:midob 2006.245.07:55:30.13/onsource/TRACKING 2006.245.07:55:30.13/wx/27.28,1004.5,69 2006.245.07:55:30.29/cable/+6.4096E-03 2006.245.07:55:31.38/va/01,08,usb,yes,30,32 2006.245.07:55:31.38/va/02,07,usb,yes,30,32 2006.245.07:55:31.38/va/03,06,usb,yes,32,32 2006.245.07:55:31.38/va/04,07,usb,yes,31,34 2006.245.07:55:31.38/va/05,07,usb,yes,33,35 2006.245.07:55:31.38/va/06,07,usb,yes,29,28 2006.245.07:55:31.38/va/07,07,usb,yes,28,28 2006.245.07:55:31.38/va/08,08,usb,yes,25,24 2006.245.07:55:31.61/valo/01,532.99,yes,locked 2006.245.07:55:31.61/valo/02,572.99,yes,locked 2006.245.07:55:31.61/valo/03,672.99,yes,locked 2006.245.07:55:31.61/valo/04,832.99,yes,locked 2006.245.07:55:31.61/valo/05,652.99,yes,locked 2006.245.07:55:31.61/valo/06,772.99,yes,locked 2006.245.07:55:31.61/valo/07,832.99,yes,locked 2006.245.07:55:31.61/valo/08,852.99,yes,locked 2006.245.07:55:32.70/vb/01,04,usb,yes,30,29 2006.245.07:55:32.70/vb/02,04,usb,yes,32,34 2006.245.07:55:32.70/vb/03,04,usb,yes,28,32 2006.245.07:55:32.70/vb/04,04,usb,yes,29,29 2006.245.07:55:32.70/vb/05,03,usb,yes,34,39 2006.245.07:55:32.70/vb/06,03,usb,yes,35,39 2006.245.07:55:32.70/vb/07,04,usb,yes,31,31 2006.245.07:55:32.70/vb/08,03,usb,yes,35,39 2006.245.07:55:32.93/vblo/01,632.99,yes,locked 2006.245.07:55:32.93/vblo/02,640.99,yes,locked 2006.245.07:55:32.93/vblo/03,656.99,yes,locked 2006.245.07:55:32.93/vblo/04,712.99,yes,locked 2006.245.07:55:32.93/vblo/05,744.99,yes,locked 2006.245.07:55:32.93/vblo/06,752.99,yes,locked 2006.245.07:55:32.93/vblo/07,734.99,yes,locked 2006.245.07:55:32.93/vblo/08,744.99,yes,locked 2006.245.07:55:33.08/vabw/8 2006.245.07:55:33.23/vbbw/8 2006.245.07:55:33.36/xfe/off,on,14.0 2006.245.07:55:33.73/ifatt/23,28,28,28 2006.245.07:55:34.07/fmout-gps/S +4.39E-07 2006.245.07:55:34.12:!2006.245.07:56:30 2006.245.07:56:30.00:data_valid=off 2006.245.07:56:30.01:postob 2006.245.07:56:30.09/cable/+6.4101E-03 2006.245.07:56:30.09/wx/27.26,1004.5,69 2006.245.07:56:31.07/fmout-gps/S +4.39E-07 2006.245.07:56:31.08:scan_name=245-0759,k06245,60 2006.245.07:56:31.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.245.07:56:31.13#flagr#flagr/antenna,new-source 2006.245.07:56:32.13:checkk5 2006.245.07:56:32.58/chk_autoobs//k5ts1/ autoobs is running! 2006.245.07:56:32.99/chk_autoobs//k5ts2/ autoobs is running! 2006.245.07:56:33.44/chk_autoobs//k5ts3/ autoobs is running! 2006.245.07:56:33.93/chk_autoobs//k5ts4/ autoobs is running! 2006.245.07:56:34.40/chk_obsdata//k5ts1/T2450755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:56:35.03/chk_obsdata//k5ts2/T2450755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:56:35.47/chk_obsdata//k5ts3/T2450755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:56:35.92/chk_obsdata//k5ts4/T2450755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.07:56:36.77/k5log//k5ts1_log_newline 2006.245.07:56:38.29/k5log//k5ts2_log_newline 2006.245.07:56:39.27/k5log//k5ts3_log_newline 2006.245.07:56:40.31/k5log//k5ts4_log_newline 2006.245.07:56:40.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.07:56:40.33:4f8m12a=2 2006.245.07:56:40.33$4f8m12a/echo=on 2006.245.07:56:40.34$4f8m12a/pcalon 2006.245.07:56:40.34$pcalon/"no phase cal control is implemented here 2006.245.07:56:40.34$4f8m12a/"tpicd=stop 2006.245.07:56:40.34$4f8m12a/vc4f8 2006.245.07:56:40.34$vc4f8/valo=1,532.99 2006.245.07:56:40.34#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.07:56:40.34#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.07:56:40.34#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:40.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:40.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:40.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:40.34#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:56:40.34#ibcon#first serial, iclass 40, count 0 2006.245.07:56:40.34#ibcon#enter sib2, iclass 40, count 0 2006.245.07:56:40.34#ibcon#flushed, iclass 40, count 0 2006.245.07:56:40.34#ibcon#about to write, iclass 40, count 0 2006.245.07:56:40.34#ibcon#wrote, iclass 40, count 0 2006.245.07:56:40.34#ibcon#about to read 3, iclass 40, count 0 2006.245.07:56:40.38#ibcon#read 3, iclass 40, count 0 2006.245.07:56:40.38#ibcon#about to read 4, iclass 40, count 0 2006.245.07:56:40.38#ibcon#read 4, iclass 40, count 0 2006.245.07:56:40.38#ibcon#about to read 5, iclass 40, count 0 2006.245.07:56:40.38#ibcon#read 5, iclass 40, count 0 2006.245.07:56:40.38#ibcon#about to read 6, iclass 40, count 0 2006.245.07:56:40.38#ibcon#read 6, iclass 40, count 0 2006.245.07:56:40.38#ibcon#end of sib2, iclass 40, count 0 2006.245.07:56:40.38#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:56:40.38#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:56:40.38#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.07:56:40.38#ibcon#*before write, iclass 40, count 0 2006.245.07:56:40.38#ibcon#enter sib2, iclass 40, count 0 2006.245.07:56:40.38#ibcon#flushed, iclass 40, count 0 2006.245.07:56:40.38#ibcon#about to write, iclass 40, count 0 2006.245.07:56:40.38#ibcon#wrote, iclass 40, count 0 2006.245.07:56:40.38#ibcon#about to read 3, iclass 40, count 0 2006.245.07:56:40.42#ibcon#read 3, iclass 40, count 0 2006.245.07:56:40.42#ibcon#about to read 4, iclass 40, count 0 2006.245.07:56:40.42#ibcon#read 4, iclass 40, count 0 2006.245.07:56:40.42#ibcon#about to read 5, iclass 40, count 0 2006.245.07:56:40.42#ibcon#read 5, iclass 40, count 0 2006.245.07:56:40.42#ibcon#about to read 6, iclass 40, count 0 2006.245.07:56:40.42#ibcon#read 6, iclass 40, count 0 2006.245.07:56:40.42#ibcon#end of sib2, iclass 40, count 0 2006.245.07:56:40.42#ibcon#*after write, iclass 40, count 0 2006.245.07:56:40.42#ibcon#*before return 0, iclass 40, count 0 2006.245.07:56:40.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:40.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:40.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:56:40.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:56:40.42$vc4f8/va=1,8 2006.245.07:56:40.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.07:56:40.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.07:56:40.42#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:40.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:40.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:40.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:40.42#ibcon#enter wrdev, iclass 4, count 2 2006.245.07:56:40.42#ibcon#first serial, iclass 4, count 2 2006.245.07:56:40.42#ibcon#enter sib2, iclass 4, count 2 2006.245.07:56:40.42#ibcon#flushed, iclass 4, count 2 2006.245.07:56:40.42#ibcon#about to write, iclass 4, count 2 2006.245.07:56:40.42#ibcon#wrote, iclass 4, count 2 2006.245.07:56:40.42#ibcon#about to read 3, iclass 4, count 2 2006.245.07:56:40.45#ibcon#read 3, iclass 4, count 2 2006.245.07:56:40.45#ibcon#about to read 4, iclass 4, count 2 2006.245.07:56:40.45#ibcon#read 4, iclass 4, count 2 2006.245.07:56:40.45#ibcon#about to read 5, iclass 4, count 2 2006.245.07:56:40.45#ibcon#read 5, iclass 4, count 2 2006.245.07:56:40.45#ibcon#about to read 6, iclass 4, count 2 2006.245.07:56:40.45#ibcon#read 6, iclass 4, count 2 2006.245.07:56:40.45#ibcon#end of sib2, iclass 4, count 2 2006.245.07:56:40.45#ibcon#*mode == 0, iclass 4, count 2 2006.245.07:56:40.45#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.07:56:40.45#ibcon#[25=AT01-08\r\n] 2006.245.07:56:40.45#ibcon#*before write, iclass 4, count 2 2006.245.07:56:40.45#ibcon#enter sib2, iclass 4, count 2 2006.245.07:56:40.45#ibcon#flushed, iclass 4, count 2 2006.245.07:56:40.45#ibcon#about to write, iclass 4, count 2 2006.245.07:56:40.45#ibcon#wrote, iclass 4, count 2 2006.245.07:56:40.45#ibcon#about to read 3, iclass 4, count 2 2006.245.07:56:40.47#ibcon#read 3, iclass 4, count 2 2006.245.07:56:40.47#ibcon#about to read 4, iclass 4, count 2 2006.245.07:56:40.47#ibcon#read 4, iclass 4, count 2 2006.245.07:56:40.48#ibcon#about to read 5, iclass 4, count 2 2006.245.07:56:40.48#ibcon#read 5, iclass 4, count 2 2006.245.07:56:40.48#ibcon#about to read 6, iclass 4, count 2 2006.245.07:56:40.48#ibcon#read 6, iclass 4, count 2 2006.245.07:56:40.48#ibcon#end of sib2, iclass 4, count 2 2006.245.07:56:40.48#ibcon#*after write, iclass 4, count 2 2006.245.07:56:40.48#ibcon#*before return 0, iclass 4, count 2 2006.245.07:56:40.48#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:40.48#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:40.48#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.07:56:40.48#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:40.48#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:40.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:40.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:40.59#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:56:40.59#ibcon#first serial, iclass 4, count 0 2006.245.07:56:40.59#ibcon#enter sib2, iclass 4, count 0 2006.245.07:56:40.59#ibcon#flushed, iclass 4, count 0 2006.245.07:56:40.59#ibcon#about to write, iclass 4, count 0 2006.245.07:56:40.59#ibcon#wrote, iclass 4, count 0 2006.245.07:56:40.59#ibcon#about to read 3, iclass 4, count 0 2006.245.07:56:40.61#ibcon#read 3, iclass 4, count 0 2006.245.07:56:40.61#ibcon#about to read 4, iclass 4, count 0 2006.245.07:56:40.61#ibcon#read 4, iclass 4, count 0 2006.245.07:56:40.61#ibcon#about to read 5, iclass 4, count 0 2006.245.07:56:40.61#ibcon#read 5, iclass 4, count 0 2006.245.07:56:40.61#ibcon#about to read 6, iclass 4, count 0 2006.245.07:56:40.61#ibcon#read 6, iclass 4, count 0 2006.245.07:56:40.61#ibcon#end of sib2, iclass 4, count 0 2006.245.07:56:40.61#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:56:40.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:56:40.61#ibcon#[25=USB\r\n] 2006.245.07:56:40.61#ibcon#*before write, iclass 4, count 0 2006.245.07:56:40.61#ibcon#enter sib2, iclass 4, count 0 2006.245.07:56:40.61#ibcon#flushed, iclass 4, count 0 2006.245.07:56:40.61#ibcon#about to write, iclass 4, count 0 2006.245.07:56:40.61#ibcon#wrote, iclass 4, count 0 2006.245.07:56:40.61#ibcon#about to read 3, iclass 4, count 0 2006.245.07:56:40.64#ibcon#read 3, iclass 4, count 0 2006.245.07:56:40.64#ibcon#about to read 4, iclass 4, count 0 2006.245.07:56:40.64#ibcon#read 4, iclass 4, count 0 2006.245.07:56:40.64#ibcon#about to read 5, iclass 4, count 0 2006.245.07:56:40.64#ibcon#read 5, iclass 4, count 0 2006.245.07:56:40.64#ibcon#about to read 6, iclass 4, count 0 2006.245.07:56:40.64#ibcon#read 6, iclass 4, count 0 2006.245.07:56:40.64#ibcon#end of sib2, iclass 4, count 0 2006.245.07:56:40.64#ibcon#*after write, iclass 4, count 0 2006.245.07:56:40.64#ibcon#*before return 0, iclass 4, count 0 2006.245.07:56:40.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:40.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:40.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:56:40.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:56:40.64$vc4f8/valo=2,572.99 2006.245.07:56:40.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.07:56:40.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.07:56:40.64#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:40.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:40.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:40.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:40.64#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:56:40.64#ibcon#first serial, iclass 6, count 0 2006.245.07:56:40.64#ibcon#enter sib2, iclass 6, count 0 2006.245.07:56:40.64#ibcon#flushed, iclass 6, count 0 2006.245.07:56:40.64#ibcon#about to write, iclass 6, count 0 2006.245.07:56:40.64#ibcon#wrote, iclass 6, count 0 2006.245.07:56:40.64#ibcon#about to read 3, iclass 6, count 0 2006.245.07:56:40.67#ibcon#read 3, iclass 6, count 0 2006.245.07:56:40.67#ibcon#about to read 4, iclass 6, count 0 2006.245.07:56:40.67#ibcon#read 4, iclass 6, count 0 2006.245.07:56:40.67#ibcon#about to read 5, iclass 6, count 0 2006.245.07:56:40.67#ibcon#read 5, iclass 6, count 0 2006.245.07:56:40.67#ibcon#about to read 6, iclass 6, count 0 2006.245.07:56:40.67#ibcon#read 6, iclass 6, count 0 2006.245.07:56:40.67#ibcon#end of sib2, iclass 6, count 0 2006.245.07:56:40.67#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:56:40.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:56:40.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.07:56:40.67#ibcon#*before write, iclass 6, count 0 2006.245.07:56:40.67#ibcon#enter sib2, iclass 6, count 0 2006.245.07:56:40.67#ibcon#flushed, iclass 6, count 0 2006.245.07:56:40.67#ibcon#about to write, iclass 6, count 0 2006.245.07:56:40.67#ibcon#wrote, iclass 6, count 0 2006.245.07:56:40.67#ibcon#about to read 3, iclass 6, count 0 2006.245.07:56:40.71#ibcon#read 3, iclass 6, count 0 2006.245.07:56:40.71#ibcon#about to read 4, iclass 6, count 0 2006.245.07:56:40.71#ibcon#read 4, iclass 6, count 0 2006.245.07:56:40.71#ibcon#about to read 5, iclass 6, count 0 2006.245.07:56:40.71#ibcon#read 5, iclass 6, count 0 2006.245.07:56:40.71#ibcon#about to read 6, iclass 6, count 0 2006.245.07:56:40.71#ibcon#read 6, iclass 6, count 0 2006.245.07:56:40.71#ibcon#end of sib2, iclass 6, count 0 2006.245.07:56:40.71#ibcon#*after write, iclass 6, count 0 2006.245.07:56:40.71#ibcon#*before return 0, iclass 6, count 0 2006.245.07:56:40.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:40.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:40.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:56:40.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:56:40.71$vc4f8/va=2,7 2006.245.07:56:40.71#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.07:56:40.71#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.07:56:40.71#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:40.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:40.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:40.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:40.77#ibcon#enter wrdev, iclass 10, count 2 2006.245.07:56:40.77#ibcon#first serial, iclass 10, count 2 2006.245.07:56:40.77#ibcon#enter sib2, iclass 10, count 2 2006.245.07:56:40.77#ibcon#flushed, iclass 10, count 2 2006.245.07:56:40.77#ibcon#about to write, iclass 10, count 2 2006.245.07:56:40.77#ibcon#wrote, iclass 10, count 2 2006.245.07:56:40.77#ibcon#about to read 3, iclass 10, count 2 2006.245.07:56:40.78#ibcon#read 3, iclass 10, count 2 2006.245.07:56:40.78#ibcon#about to read 4, iclass 10, count 2 2006.245.07:56:40.78#ibcon#read 4, iclass 10, count 2 2006.245.07:56:40.78#ibcon#about to read 5, iclass 10, count 2 2006.245.07:56:40.78#ibcon#read 5, iclass 10, count 2 2006.245.07:56:40.78#ibcon#about to read 6, iclass 10, count 2 2006.245.07:56:40.78#ibcon#read 6, iclass 10, count 2 2006.245.07:56:40.78#ibcon#end of sib2, iclass 10, count 2 2006.245.07:56:40.78#ibcon#*mode == 0, iclass 10, count 2 2006.245.07:56:40.78#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.07:56:40.78#ibcon#[25=AT02-07\r\n] 2006.245.07:56:40.78#ibcon#*before write, iclass 10, count 2 2006.245.07:56:40.78#ibcon#enter sib2, iclass 10, count 2 2006.245.07:56:40.78#ibcon#flushed, iclass 10, count 2 2006.245.07:56:40.78#ibcon#about to write, iclass 10, count 2 2006.245.07:56:40.78#ibcon#wrote, iclass 10, count 2 2006.245.07:56:40.78#ibcon#about to read 3, iclass 10, count 2 2006.245.07:56:40.81#ibcon#read 3, iclass 10, count 2 2006.245.07:56:40.81#ibcon#about to read 4, iclass 10, count 2 2006.245.07:56:40.81#ibcon#read 4, iclass 10, count 2 2006.245.07:56:40.81#ibcon#about to read 5, iclass 10, count 2 2006.245.07:56:40.81#ibcon#read 5, iclass 10, count 2 2006.245.07:56:40.81#ibcon#about to read 6, iclass 10, count 2 2006.245.07:56:40.81#ibcon#read 6, iclass 10, count 2 2006.245.07:56:40.81#ibcon#end of sib2, iclass 10, count 2 2006.245.07:56:40.81#ibcon#*after write, iclass 10, count 2 2006.245.07:56:40.81#ibcon#*before return 0, iclass 10, count 2 2006.245.07:56:40.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:40.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:40.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.07:56:40.81#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:40.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:40.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:40.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:40.93#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:56:40.93#ibcon#first serial, iclass 10, count 0 2006.245.07:56:40.93#ibcon#enter sib2, iclass 10, count 0 2006.245.07:56:40.93#ibcon#flushed, iclass 10, count 0 2006.245.07:56:40.93#ibcon#about to write, iclass 10, count 0 2006.245.07:56:40.93#ibcon#wrote, iclass 10, count 0 2006.245.07:56:40.93#ibcon#about to read 3, iclass 10, count 0 2006.245.07:56:40.95#ibcon#read 3, iclass 10, count 0 2006.245.07:56:40.95#ibcon#about to read 4, iclass 10, count 0 2006.245.07:56:40.95#ibcon#read 4, iclass 10, count 0 2006.245.07:56:40.95#ibcon#about to read 5, iclass 10, count 0 2006.245.07:56:40.95#ibcon#read 5, iclass 10, count 0 2006.245.07:56:40.95#ibcon#about to read 6, iclass 10, count 0 2006.245.07:56:40.95#ibcon#read 6, iclass 10, count 0 2006.245.07:56:40.95#ibcon#end of sib2, iclass 10, count 0 2006.245.07:56:40.95#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:56:40.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:56:40.95#ibcon#[25=USB\r\n] 2006.245.07:56:40.95#ibcon#*before write, iclass 10, count 0 2006.245.07:56:40.95#ibcon#enter sib2, iclass 10, count 0 2006.245.07:56:40.95#ibcon#flushed, iclass 10, count 0 2006.245.07:56:40.95#ibcon#about to write, iclass 10, count 0 2006.245.07:56:40.95#ibcon#wrote, iclass 10, count 0 2006.245.07:56:40.95#ibcon#about to read 3, iclass 10, count 0 2006.245.07:56:40.98#ibcon#read 3, iclass 10, count 0 2006.245.07:56:40.98#ibcon#about to read 4, iclass 10, count 0 2006.245.07:56:40.98#ibcon#read 4, iclass 10, count 0 2006.245.07:56:40.98#ibcon#about to read 5, iclass 10, count 0 2006.245.07:56:40.98#ibcon#read 5, iclass 10, count 0 2006.245.07:56:40.98#ibcon#about to read 6, iclass 10, count 0 2006.245.07:56:40.98#ibcon#read 6, iclass 10, count 0 2006.245.07:56:40.98#ibcon#end of sib2, iclass 10, count 0 2006.245.07:56:40.98#ibcon#*after write, iclass 10, count 0 2006.245.07:56:40.98#ibcon#*before return 0, iclass 10, count 0 2006.245.07:56:40.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:40.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:40.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:56:40.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:56:40.98$vc4f8/valo=3,672.99 2006.245.07:56:40.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.07:56:40.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.07:56:40.98#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:40.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:40.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:40.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:40.98#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:56:40.98#ibcon#first serial, iclass 12, count 0 2006.245.07:56:40.98#ibcon#enter sib2, iclass 12, count 0 2006.245.07:56:40.98#ibcon#flushed, iclass 12, count 0 2006.245.07:56:40.98#ibcon#about to write, iclass 12, count 0 2006.245.07:56:40.98#ibcon#wrote, iclass 12, count 0 2006.245.07:56:40.98#ibcon#about to read 3, iclass 12, count 0 2006.245.07:56:41.01#ibcon#read 3, iclass 12, count 0 2006.245.07:56:41.01#ibcon#about to read 4, iclass 12, count 0 2006.245.07:56:41.01#ibcon#read 4, iclass 12, count 0 2006.245.07:56:41.01#ibcon#about to read 5, iclass 12, count 0 2006.245.07:56:41.01#ibcon#read 5, iclass 12, count 0 2006.245.07:56:41.01#ibcon#about to read 6, iclass 12, count 0 2006.245.07:56:41.01#ibcon#read 6, iclass 12, count 0 2006.245.07:56:41.01#ibcon#end of sib2, iclass 12, count 0 2006.245.07:56:41.01#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:56:41.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:56:41.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.07:56:41.01#ibcon#*before write, iclass 12, count 0 2006.245.07:56:41.01#ibcon#enter sib2, iclass 12, count 0 2006.245.07:56:41.01#ibcon#flushed, iclass 12, count 0 2006.245.07:56:41.01#ibcon#about to write, iclass 12, count 0 2006.245.07:56:41.01#ibcon#wrote, iclass 12, count 0 2006.245.07:56:41.01#ibcon#about to read 3, iclass 12, count 0 2006.245.07:56:41.05#ibcon#read 3, iclass 12, count 0 2006.245.07:56:41.05#ibcon#about to read 4, iclass 12, count 0 2006.245.07:56:41.05#ibcon#read 4, iclass 12, count 0 2006.245.07:56:41.05#ibcon#about to read 5, iclass 12, count 0 2006.245.07:56:41.05#ibcon#read 5, iclass 12, count 0 2006.245.07:56:41.05#ibcon#about to read 6, iclass 12, count 0 2006.245.07:56:41.05#ibcon#read 6, iclass 12, count 0 2006.245.07:56:41.05#ibcon#end of sib2, iclass 12, count 0 2006.245.07:56:41.05#ibcon#*after write, iclass 12, count 0 2006.245.07:56:41.05#ibcon#*before return 0, iclass 12, count 0 2006.245.07:56:41.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:41.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:41.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:56:41.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:56:41.05$vc4f8/va=3,6 2006.245.07:56:41.05#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.07:56:41.05#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.07:56:41.05#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:41.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:41.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:41.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:41.11#ibcon#enter wrdev, iclass 14, count 2 2006.245.07:56:41.11#ibcon#first serial, iclass 14, count 2 2006.245.07:56:41.11#ibcon#enter sib2, iclass 14, count 2 2006.245.07:56:41.11#ibcon#flushed, iclass 14, count 2 2006.245.07:56:41.11#ibcon#about to write, iclass 14, count 2 2006.245.07:56:41.11#ibcon#wrote, iclass 14, count 2 2006.245.07:56:41.11#ibcon#about to read 3, iclass 14, count 2 2006.245.07:56:41.12#ibcon#read 3, iclass 14, count 2 2006.245.07:56:41.12#ibcon#about to read 4, iclass 14, count 2 2006.245.07:56:41.12#ibcon#read 4, iclass 14, count 2 2006.245.07:56:41.12#ibcon#about to read 5, iclass 14, count 2 2006.245.07:56:41.12#ibcon#read 5, iclass 14, count 2 2006.245.07:56:41.12#ibcon#about to read 6, iclass 14, count 2 2006.245.07:56:41.12#ibcon#read 6, iclass 14, count 2 2006.245.07:56:41.12#ibcon#end of sib2, iclass 14, count 2 2006.245.07:56:41.12#ibcon#*mode == 0, iclass 14, count 2 2006.245.07:56:41.12#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.07:56:41.12#ibcon#[25=AT03-06\r\n] 2006.245.07:56:41.12#ibcon#*before write, iclass 14, count 2 2006.245.07:56:41.12#ibcon#enter sib2, iclass 14, count 2 2006.245.07:56:41.12#ibcon#flushed, iclass 14, count 2 2006.245.07:56:41.12#ibcon#about to write, iclass 14, count 2 2006.245.07:56:41.12#ibcon#wrote, iclass 14, count 2 2006.245.07:56:41.12#ibcon#about to read 3, iclass 14, count 2 2006.245.07:56:41.15#ibcon#read 3, iclass 14, count 2 2006.245.07:56:41.15#ibcon#about to read 4, iclass 14, count 2 2006.245.07:56:41.15#ibcon#read 4, iclass 14, count 2 2006.245.07:56:41.15#ibcon#about to read 5, iclass 14, count 2 2006.245.07:56:41.15#ibcon#read 5, iclass 14, count 2 2006.245.07:56:41.15#ibcon#about to read 6, iclass 14, count 2 2006.245.07:56:41.15#ibcon#read 6, iclass 14, count 2 2006.245.07:56:41.15#ibcon#end of sib2, iclass 14, count 2 2006.245.07:56:41.15#ibcon#*after write, iclass 14, count 2 2006.245.07:56:41.15#ibcon#*before return 0, iclass 14, count 2 2006.245.07:56:41.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:41.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:41.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.07:56:41.15#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:41.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:41.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:41.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:41.27#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:56:41.27#ibcon#first serial, iclass 14, count 0 2006.245.07:56:41.27#ibcon#enter sib2, iclass 14, count 0 2006.245.07:56:41.27#ibcon#flushed, iclass 14, count 0 2006.245.07:56:41.27#ibcon#about to write, iclass 14, count 0 2006.245.07:56:41.27#ibcon#wrote, iclass 14, count 0 2006.245.07:56:41.27#ibcon#about to read 3, iclass 14, count 0 2006.245.07:56:41.29#ibcon#read 3, iclass 14, count 0 2006.245.07:56:41.29#ibcon#about to read 4, iclass 14, count 0 2006.245.07:56:41.29#ibcon#read 4, iclass 14, count 0 2006.245.07:56:41.29#ibcon#about to read 5, iclass 14, count 0 2006.245.07:56:41.29#ibcon#read 5, iclass 14, count 0 2006.245.07:56:41.29#ibcon#about to read 6, iclass 14, count 0 2006.245.07:56:41.29#ibcon#read 6, iclass 14, count 0 2006.245.07:56:41.29#ibcon#end of sib2, iclass 14, count 0 2006.245.07:56:41.29#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:56:41.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:56:41.29#ibcon#[25=USB\r\n] 2006.245.07:56:41.29#ibcon#*before write, iclass 14, count 0 2006.245.07:56:41.29#ibcon#enter sib2, iclass 14, count 0 2006.245.07:56:41.29#ibcon#flushed, iclass 14, count 0 2006.245.07:56:41.29#ibcon#about to write, iclass 14, count 0 2006.245.07:56:41.29#ibcon#wrote, iclass 14, count 0 2006.245.07:56:41.29#ibcon#about to read 3, iclass 14, count 0 2006.245.07:56:41.32#ibcon#read 3, iclass 14, count 0 2006.245.07:56:41.32#ibcon#about to read 4, iclass 14, count 0 2006.245.07:56:41.32#ibcon#read 4, iclass 14, count 0 2006.245.07:56:41.32#ibcon#about to read 5, iclass 14, count 0 2006.245.07:56:41.32#ibcon#read 5, iclass 14, count 0 2006.245.07:56:41.32#ibcon#about to read 6, iclass 14, count 0 2006.245.07:56:41.32#ibcon#read 6, iclass 14, count 0 2006.245.07:56:41.32#ibcon#end of sib2, iclass 14, count 0 2006.245.07:56:41.32#ibcon#*after write, iclass 14, count 0 2006.245.07:56:41.32#ibcon#*before return 0, iclass 14, count 0 2006.245.07:56:41.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:41.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:41.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:56:41.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:56:41.32$vc4f8/valo=4,832.99 2006.245.07:56:41.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:56:41.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:56:41.32#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:41.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:41.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:41.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:41.32#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:56:41.32#ibcon#first serial, iclass 16, count 0 2006.245.07:56:41.32#ibcon#enter sib2, iclass 16, count 0 2006.245.07:56:41.32#ibcon#flushed, iclass 16, count 0 2006.245.07:56:41.32#ibcon#about to write, iclass 16, count 0 2006.245.07:56:41.32#ibcon#wrote, iclass 16, count 0 2006.245.07:56:41.32#ibcon#about to read 3, iclass 16, count 0 2006.245.07:56:41.35#ibcon#read 3, iclass 16, count 0 2006.245.07:56:41.35#ibcon#about to read 4, iclass 16, count 0 2006.245.07:56:41.35#ibcon#read 4, iclass 16, count 0 2006.245.07:56:41.35#ibcon#about to read 5, iclass 16, count 0 2006.245.07:56:41.35#ibcon#read 5, iclass 16, count 0 2006.245.07:56:41.35#ibcon#about to read 6, iclass 16, count 0 2006.245.07:56:41.35#ibcon#read 6, iclass 16, count 0 2006.245.07:56:41.35#ibcon#end of sib2, iclass 16, count 0 2006.245.07:56:41.35#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:56:41.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:56:41.35#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.07:56:41.35#ibcon#*before write, iclass 16, count 0 2006.245.07:56:41.35#ibcon#enter sib2, iclass 16, count 0 2006.245.07:56:41.35#ibcon#flushed, iclass 16, count 0 2006.245.07:56:41.35#ibcon#about to write, iclass 16, count 0 2006.245.07:56:41.35#ibcon#wrote, iclass 16, count 0 2006.245.07:56:41.35#ibcon#about to read 3, iclass 16, count 0 2006.245.07:56:41.39#ibcon#read 3, iclass 16, count 0 2006.245.07:56:41.39#ibcon#about to read 4, iclass 16, count 0 2006.245.07:56:41.39#ibcon#read 4, iclass 16, count 0 2006.245.07:56:41.39#ibcon#about to read 5, iclass 16, count 0 2006.245.07:56:41.39#ibcon#read 5, iclass 16, count 0 2006.245.07:56:41.39#ibcon#about to read 6, iclass 16, count 0 2006.245.07:56:41.39#ibcon#read 6, iclass 16, count 0 2006.245.07:56:41.39#ibcon#end of sib2, iclass 16, count 0 2006.245.07:56:41.39#ibcon#*after write, iclass 16, count 0 2006.245.07:56:41.39#ibcon#*before return 0, iclass 16, count 0 2006.245.07:56:41.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:41.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:41.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:56:41.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:56:41.39$vc4f8/va=4,7 2006.245.07:56:41.39#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.07:56:41.39#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.07:56:41.39#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:41.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:41.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:41.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:41.44#ibcon#enter wrdev, iclass 18, count 2 2006.245.07:56:41.44#ibcon#first serial, iclass 18, count 2 2006.245.07:56:41.44#ibcon#enter sib2, iclass 18, count 2 2006.245.07:56:41.44#ibcon#flushed, iclass 18, count 2 2006.245.07:56:41.44#ibcon#about to write, iclass 18, count 2 2006.245.07:56:41.44#ibcon#wrote, iclass 18, count 2 2006.245.07:56:41.44#ibcon#about to read 3, iclass 18, count 2 2006.245.07:56:41.46#ibcon#read 3, iclass 18, count 2 2006.245.07:56:41.46#ibcon#about to read 4, iclass 18, count 2 2006.245.07:56:41.46#ibcon#read 4, iclass 18, count 2 2006.245.07:56:41.46#ibcon#about to read 5, iclass 18, count 2 2006.245.07:56:41.46#ibcon#read 5, iclass 18, count 2 2006.245.07:56:41.46#ibcon#about to read 6, iclass 18, count 2 2006.245.07:56:41.46#ibcon#read 6, iclass 18, count 2 2006.245.07:56:41.46#ibcon#end of sib2, iclass 18, count 2 2006.245.07:56:41.46#ibcon#*mode == 0, iclass 18, count 2 2006.245.07:56:41.46#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.07:56:41.46#ibcon#[25=AT04-07\r\n] 2006.245.07:56:41.46#ibcon#*before write, iclass 18, count 2 2006.245.07:56:41.46#ibcon#enter sib2, iclass 18, count 2 2006.245.07:56:41.46#ibcon#flushed, iclass 18, count 2 2006.245.07:56:41.46#ibcon#about to write, iclass 18, count 2 2006.245.07:56:41.46#ibcon#wrote, iclass 18, count 2 2006.245.07:56:41.46#ibcon#about to read 3, iclass 18, count 2 2006.245.07:56:41.49#ibcon#read 3, iclass 18, count 2 2006.245.07:56:41.49#ibcon#about to read 4, iclass 18, count 2 2006.245.07:56:41.49#ibcon#read 4, iclass 18, count 2 2006.245.07:56:41.49#ibcon#about to read 5, iclass 18, count 2 2006.245.07:56:41.49#ibcon#read 5, iclass 18, count 2 2006.245.07:56:41.49#ibcon#about to read 6, iclass 18, count 2 2006.245.07:56:41.49#ibcon#read 6, iclass 18, count 2 2006.245.07:56:41.49#ibcon#end of sib2, iclass 18, count 2 2006.245.07:56:41.49#ibcon#*after write, iclass 18, count 2 2006.245.07:56:41.49#ibcon#*before return 0, iclass 18, count 2 2006.245.07:56:41.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:41.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:41.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.07:56:41.49#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:41.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:41.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:41.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:41.61#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:56:41.61#ibcon#first serial, iclass 18, count 0 2006.245.07:56:41.61#ibcon#enter sib2, iclass 18, count 0 2006.245.07:56:41.61#ibcon#flushed, iclass 18, count 0 2006.245.07:56:41.61#ibcon#about to write, iclass 18, count 0 2006.245.07:56:41.61#ibcon#wrote, iclass 18, count 0 2006.245.07:56:41.61#ibcon#about to read 3, iclass 18, count 0 2006.245.07:56:41.63#ibcon#read 3, iclass 18, count 0 2006.245.07:56:41.63#ibcon#about to read 4, iclass 18, count 0 2006.245.07:56:41.63#ibcon#read 4, iclass 18, count 0 2006.245.07:56:41.63#ibcon#about to read 5, iclass 18, count 0 2006.245.07:56:41.63#ibcon#read 5, iclass 18, count 0 2006.245.07:56:41.63#ibcon#about to read 6, iclass 18, count 0 2006.245.07:56:41.63#ibcon#read 6, iclass 18, count 0 2006.245.07:56:41.63#ibcon#end of sib2, iclass 18, count 0 2006.245.07:56:41.63#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:56:41.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:56:41.63#ibcon#[25=USB\r\n] 2006.245.07:56:41.63#ibcon#*before write, iclass 18, count 0 2006.245.07:56:41.63#ibcon#enter sib2, iclass 18, count 0 2006.245.07:56:41.63#ibcon#flushed, iclass 18, count 0 2006.245.07:56:41.63#ibcon#about to write, iclass 18, count 0 2006.245.07:56:41.63#ibcon#wrote, iclass 18, count 0 2006.245.07:56:41.63#ibcon#about to read 3, iclass 18, count 0 2006.245.07:56:41.66#ibcon#read 3, iclass 18, count 0 2006.245.07:56:41.66#ibcon#about to read 4, iclass 18, count 0 2006.245.07:56:41.66#ibcon#read 4, iclass 18, count 0 2006.245.07:56:41.66#ibcon#about to read 5, iclass 18, count 0 2006.245.07:56:41.66#ibcon#read 5, iclass 18, count 0 2006.245.07:56:41.66#ibcon#about to read 6, iclass 18, count 0 2006.245.07:56:41.66#ibcon#read 6, iclass 18, count 0 2006.245.07:56:41.66#ibcon#end of sib2, iclass 18, count 0 2006.245.07:56:41.66#ibcon#*after write, iclass 18, count 0 2006.245.07:56:41.66#ibcon#*before return 0, iclass 18, count 0 2006.245.07:56:41.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:41.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:41.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:56:41.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:56:41.66$vc4f8/valo=5,652.99 2006.245.07:56:41.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.07:56:41.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.07:56:41.66#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:41.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:41.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:41.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:41.66#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:56:41.66#ibcon#first serial, iclass 20, count 0 2006.245.07:56:41.66#ibcon#enter sib2, iclass 20, count 0 2006.245.07:56:41.66#ibcon#flushed, iclass 20, count 0 2006.245.07:56:41.66#ibcon#about to write, iclass 20, count 0 2006.245.07:56:41.66#ibcon#wrote, iclass 20, count 0 2006.245.07:56:41.66#ibcon#about to read 3, iclass 20, count 0 2006.245.07:56:41.68#ibcon#read 3, iclass 20, count 0 2006.245.07:56:41.68#ibcon#about to read 4, iclass 20, count 0 2006.245.07:56:41.68#ibcon#read 4, iclass 20, count 0 2006.245.07:56:41.68#ibcon#about to read 5, iclass 20, count 0 2006.245.07:56:41.68#ibcon#read 5, iclass 20, count 0 2006.245.07:56:41.68#ibcon#about to read 6, iclass 20, count 0 2006.245.07:56:41.68#ibcon#read 6, iclass 20, count 0 2006.245.07:56:41.68#ibcon#end of sib2, iclass 20, count 0 2006.245.07:56:41.68#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:56:41.68#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:56:41.68#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.07:56:41.68#ibcon#*before write, iclass 20, count 0 2006.245.07:56:41.68#ibcon#enter sib2, iclass 20, count 0 2006.245.07:56:41.68#ibcon#flushed, iclass 20, count 0 2006.245.07:56:41.68#ibcon#about to write, iclass 20, count 0 2006.245.07:56:41.68#ibcon#wrote, iclass 20, count 0 2006.245.07:56:41.68#ibcon#about to read 3, iclass 20, count 0 2006.245.07:56:41.72#ibcon#read 3, iclass 20, count 0 2006.245.07:56:41.72#ibcon#about to read 4, iclass 20, count 0 2006.245.07:56:41.72#ibcon#read 4, iclass 20, count 0 2006.245.07:56:41.72#ibcon#about to read 5, iclass 20, count 0 2006.245.07:56:41.72#ibcon#read 5, iclass 20, count 0 2006.245.07:56:41.72#ibcon#about to read 6, iclass 20, count 0 2006.245.07:56:41.72#ibcon#read 6, iclass 20, count 0 2006.245.07:56:41.72#ibcon#end of sib2, iclass 20, count 0 2006.245.07:56:41.72#ibcon#*after write, iclass 20, count 0 2006.245.07:56:41.72#ibcon#*before return 0, iclass 20, count 0 2006.245.07:56:41.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:41.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:41.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:56:41.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:56:41.72$vc4f8/va=5,7 2006.245.07:56:41.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.07:56:41.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.07:56:41.72#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:41.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:41.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:41.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:41.78#ibcon#enter wrdev, iclass 22, count 2 2006.245.07:56:41.78#ibcon#first serial, iclass 22, count 2 2006.245.07:56:41.78#ibcon#enter sib2, iclass 22, count 2 2006.245.07:56:41.78#ibcon#flushed, iclass 22, count 2 2006.245.07:56:41.78#ibcon#about to write, iclass 22, count 2 2006.245.07:56:41.78#ibcon#wrote, iclass 22, count 2 2006.245.07:56:41.78#ibcon#about to read 3, iclass 22, count 2 2006.245.07:56:41.80#ibcon#read 3, iclass 22, count 2 2006.245.07:56:41.80#ibcon#about to read 4, iclass 22, count 2 2006.245.07:56:41.80#ibcon#read 4, iclass 22, count 2 2006.245.07:56:41.80#ibcon#about to read 5, iclass 22, count 2 2006.245.07:56:41.80#ibcon#read 5, iclass 22, count 2 2006.245.07:56:41.80#ibcon#about to read 6, iclass 22, count 2 2006.245.07:56:41.80#ibcon#read 6, iclass 22, count 2 2006.245.07:56:41.80#ibcon#end of sib2, iclass 22, count 2 2006.245.07:56:41.80#ibcon#*mode == 0, iclass 22, count 2 2006.245.07:56:41.80#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.07:56:41.80#ibcon#[25=AT05-07\r\n] 2006.245.07:56:41.80#ibcon#*before write, iclass 22, count 2 2006.245.07:56:41.80#ibcon#enter sib2, iclass 22, count 2 2006.245.07:56:41.80#ibcon#flushed, iclass 22, count 2 2006.245.07:56:41.80#ibcon#about to write, iclass 22, count 2 2006.245.07:56:41.80#ibcon#wrote, iclass 22, count 2 2006.245.07:56:41.80#ibcon#about to read 3, iclass 22, count 2 2006.245.07:56:41.83#ibcon#read 3, iclass 22, count 2 2006.245.07:56:41.83#ibcon#about to read 4, iclass 22, count 2 2006.245.07:56:41.83#ibcon#read 4, iclass 22, count 2 2006.245.07:56:41.83#ibcon#about to read 5, iclass 22, count 2 2006.245.07:56:41.83#ibcon#read 5, iclass 22, count 2 2006.245.07:56:41.83#ibcon#about to read 6, iclass 22, count 2 2006.245.07:56:41.83#ibcon#read 6, iclass 22, count 2 2006.245.07:56:41.83#ibcon#end of sib2, iclass 22, count 2 2006.245.07:56:41.83#ibcon#*after write, iclass 22, count 2 2006.245.07:56:41.83#ibcon#*before return 0, iclass 22, count 2 2006.245.07:56:41.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:41.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:41.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.07:56:41.83#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:41.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:41.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:41.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:41.95#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:56:41.95#ibcon#first serial, iclass 22, count 0 2006.245.07:56:41.95#ibcon#enter sib2, iclass 22, count 0 2006.245.07:56:41.95#ibcon#flushed, iclass 22, count 0 2006.245.07:56:41.95#ibcon#about to write, iclass 22, count 0 2006.245.07:56:41.95#ibcon#wrote, iclass 22, count 0 2006.245.07:56:41.95#ibcon#about to read 3, iclass 22, count 0 2006.245.07:56:41.97#ibcon#read 3, iclass 22, count 0 2006.245.07:56:41.97#ibcon#about to read 4, iclass 22, count 0 2006.245.07:56:41.97#ibcon#read 4, iclass 22, count 0 2006.245.07:56:41.97#ibcon#about to read 5, iclass 22, count 0 2006.245.07:56:41.97#ibcon#read 5, iclass 22, count 0 2006.245.07:56:41.97#ibcon#about to read 6, iclass 22, count 0 2006.245.07:56:41.97#ibcon#read 6, iclass 22, count 0 2006.245.07:56:41.97#ibcon#end of sib2, iclass 22, count 0 2006.245.07:56:41.97#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:56:41.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:56:41.97#ibcon#[25=USB\r\n] 2006.245.07:56:41.97#ibcon#*before write, iclass 22, count 0 2006.245.07:56:41.97#ibcon#enter sib2, iclass 22, count 0 2006.245.07:56:41.97#ibcon#flushed, iclass 22, count 0 2006.245.07:56:41.97#ibcon#about to write, iclass 22, count 0 2006.245.07:56:41.97#ibcon#wrote, iclass 22, count 0 2006.245.07:56:41.97#ibcon#about to read 3, iclass 22, count 0 2006.245.07:56:42.00#ibcon#read 3, iclass 22, count 0 2006.245.07:56:42.00#ibcon#about to read 4, iclass 22, count 0 2006.245.07:56:42.00#ibcon#read 4, iclass 22, count 0 2006.245.07:56:42.00#ibcon#about to read 5, iclass 22, count 0 2006.245.07:56:42.00#ibcon#read 5, iclass 22, count 0 2006.245.07:56:42.00#ibcon#about to read 6, iclass 22, count 0 2006.245.07:56:42.00#ibcon#read 6, iclass 22, count 0 2006.245.07:56:42.00#ibcon#end of sib2, iclass 22, count 0 2006.245.07:56:42.00#ibcon#*after write, iclass 22, count 0 2006.245.07:56:42.00#ibcon#*before return 0, iclass 22, count 0 2006.245.07:56:42.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:42.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:42.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:56:42.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:56:42.00$vc4f8/valo=6,772.99 2006.245.07:56:42.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.07:56:42.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.07:56:42.00#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:42.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:42.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:42.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:42.00#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:56:42.00#ibcon#first serial, iclass 24, count 0 2006.245.07:56:42.00#ibcon#enter sib2, iclass 24, count 0 2006.245.07:56:42.00#ibcon#flushed, iclass 24, count 0 2006.245.07:56:42.00#ibcon#about to write, iclass 24, count 0 2006.245.07:56:42.00#ibcon#wrote, iclass 24, count 0 2006.245.07:56:42.00#ibcon#about to read 3, iclass 24, count 0 2006.245.07:56:42.03#ibcon#read 3, iclass 24, count 0 2006.245.07:56:42.03#ibcon#about to read 4, iclass 24, count 0 2006.245.07:56:42.03#ibcon#read 4, iclass 24, count 0 2006.245.07:56:42.03#ibcon#about to read 5, iclass 24, count 0 2006.245.07:56:42.03#ibcon#read 5, iclass 24, count 0 2006.245.07:56:42.03#ibcon#about to read 6, iclass 24, count 0 2006.245.07:56:42.03#ibcon#read 6, iclass 24, count 0 2006.245.07:56:42.03#ibcon#end of sib2, iclass 24, count 0 2006.245.07:56:42.03#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:56:42.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:56:42.03#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.07:56:42.03#ibcon#*before write, iclass 24, count 0 2006.245.07:56:42.03#ibcon#enter sib2, iclass 24, count 0 2006.245.07:56:42.03#ibcon#flushed, iclass 24, count 0 2006.245.07:56:42.03#ibcon#about to write, iclass 24, count 0 2006.245.07:56:42.03#ibcon#wrote, iclass 24, count 0 2006.245.07:56:42.03#ibcon#about to read 3, iclass 24, count 0 2006.245.07:56:42.07#ibcon#read 3, iclass 24, count 0 2006.245.07:56:42.07#ibcon#about to read 4, iclass 24, count 0 2006.245.07:56:42.07#ibcon#read 4, iclass 24, count 0 2006.245.07:56:42.07#ibcon#about to read 5, iclass 24, count 0 2006.245.07:56:42.07#ibcon#read 5, iclass 24, count 0 2006.245.07:56:42.07#ibcon#about to read 6, iclass 24, count 0 2006.245.07:56:42.07#ibcon#read 6, iclass 24, count 0 2006.245.07:56:42.07#ibcon#end of sib2, iclass 24, count 0 2006.245.07:56:42.07#ibcon#*after write, iclass 24, count 0 2006.245.07:56:42.07#ibcon#*before return 0, iclass 24, count 0 2006.245.07:56:42.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:42.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:42.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:56:42.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:56:42.07$vc4f8/va=6,7 2006.245.07:56:42.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.07:56:42.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.07:56:42.07#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:42.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:42.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:42.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:42.13#ibcon#enter wrdev, iclass 26, count 2 2006.245.07:56:42.13#ibcon#first serial, iclass 26, count 2 2006.245.07:56:42.13#ibcon#enter sib2, iclass 26, count 2 2006.245.07:56:42.13#ibcon#flushed, iclass 26, count 2 2006.245.07:56:42.13#ibcon#about to write, iclass 26, count 2 2006.245.07:56:42.13#ibcon#wrote, iclass 26, count 2 2006.245.07:56:42.13#ibcon#about to read 3, iclass 26, count 2 2006.245.07:56:42.14#ibcon#read 3, iclass 26, count 2 2006.245.07:56:42.14#ibcon#about to read 4, iclass 26, count 2 2006.245.07:56:42.14#ibcon#read 4, iclass 26, count 2 2006.245.07:56:42.14#ibcon#about to read 5, iclass 26, count 2 2006.245.07:56:42.14#ibcon#read 5, iclass 26, count 2 2006.245.07:56:42.14#ibcon#about to read 6, iclass 26, count 2 2006.245.07:56:42.14#ibcon#read 6, iclass 26, count 2 2006.245.07:56:42.14#ibcon#end of sib2, iclass 26, count 2 2006.245.07:56:42.14#ibcon#*mode == 0, iclass 26, count 2 2006.245.07:56:42.14#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.07:56:42.14#ibcon#[25=AT06-07\r\n] 2006.245.07:56:42.14#ibcon#*before write, iclass 26, count 2 2006.245.07:56:42.14#ibcon#enter sib2, iclass 26, count 2 2006.245.07:56:42.14#ibcon#flushed, iclass 26, count 2 2006.245.07:56:42.14#ibcon#about to write, iclass 26, count 2 2006.245.07:56:42.14#ibcon#wrote, iclass 26, count 2 2006.245.07:56:42.14#ibcon#about to read 3, iclass 26, count 2 2006.245.07:56:42.17#ibcon#read 3, iclass 26, count 2 2006.245.07:56:42.17#ibcon#about to read 4, iclass 26, count 2 2006.245.07:56:42.17#ibcon#read 4, iclass 26, count 2 2006.245.07:56:42.17#ibcon#about to read 5, iclass 26, count 2 2006.245.07:56:42.17#ibcon#read 5, iclass 26, count 2 2006.245.07:56:42.17#ibcon#about to read 6, iclass 26, count 2 2006.245.07:56:42.17#ibcon#read 6, iclass 26, count 2 2006.245.07:56:42.17#ibcon#end of sib2, iclass 26, count 2 2006.245.07:56:42.17#ibcon#*after write, iclass 26, count 2 2006.245.07:56:42.17#ibcon#*before return 0, iclass 26, count 2 2006.245.07:56:42.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:42.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:42.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.07:56:42.17#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:42.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:42.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:42.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:42.29#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:56:42.29#ibcon#first serial, iclass 26, count 0 2006.245.07:56:42.29#ibcon#enter sib2, iclass 26, count 0 2006.245.07:56:42.29#ibcon#flushed, iclass 26, count 0 2006.245.07:56:42.29#ibcon#about to write, iclass 26, count 0 2006.245.07:56:42.29#ibcon#wrote, iclass 26, count 0 2006.245.07:56:42.29#ibcon#about to read 3, iclass 26, count 0 2006.245.07:56:42.31#ibcon#read 3, iclass 26, count 0 2006.245.07:56:42.31#ibcon#about to read 4, iclass 26, count 0 2006.245.07:56:42.31#ibcon#read 4, iclass 26, count 0 2006.245.07:56:42.31#ibcon#about to read 5, iclass 26, count 0 2006.245.07:56:42.31#ibcon#read 5, iclass 26, count 0 2006.245.07:56:42.31#ibcon#about to read 6, iclass 26, count 0 2006.245.07:56:42.31#ibcon#read 6, iclass 26, count 0 2006.245.07:56:42.31#ibcon#end of sib2, iclass 26, count 0 2006.245.07:56:42.31#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:56:42.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:56:42.31#ibcon#[25=USB\r\n] 2006.245.07:56:42.31#ibcon#*before write, iclass 26, count 0 2006.245.07:56:42.31#ibcon#enter sib2, iclass 26, count 0 2006.245.07:56:42.31#ibcon#flushed, iclass 26, count 0 2006.245.07:56:42.31#ibcon#about to write, iclass 26, count 0 2006.245.07:56:42.31#ibcon#wrote, iclass 26, count 0 2006.245.07:56:42.31#ibcon#about to read 3, iclass 26, count 0 2006.245.07:56:42.34#ibcon#read 3, iclass 26, count 0 2006.245.07:56:42.34#ibcon#about to read 4, iclass 26, count 0 2006.245.07:56:42.34#ibcon#read 4, iclass 26, count 0 2006.245.07:56:42.34#ibcon#about to read 5, iclass 26, count 0 2006.245.07:56:42.34#ibcon#read 5, iclass 26, count 0 2006.245.07:56:42.34#ibcon#about to read 6, iclass 26, count 0 2006.245.07:56:42.34#ibcon#read 6, iclass 26, count 0 2006.245.07:56:42.34#ibcon#end of sib2, iclass 26, count 0 2006.245.07:56:42.34#ibcon#*after write, iclass 26, count 0 2006.245.07:56:42.34#ibcon#*before return 0, iclass 26, count 0 2006.245.07:56:42.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:42.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:42.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:56:42.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:56:42.34$vc4f8/valo=7,832.99 2006.245.07:56:42.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:56:42.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:56:42.34#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:42.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:42.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:42.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:42.34#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:56:42.34#ibcon#first serial, iclass 28, count 0 2006.245.07:56:42.34#ibcon#enter sib2, iclass 28, count 0 2006.245.07:56:42.34#ibcon#flushed, iclass 28, count 0 2006.245.07:56:42.34#ibcon#about to write, iclass 28, count 0 2006.245.07:56:42.34#ibcon#wrote, iclass 28, count 0 2006.245.07:56:42.34#ibcon#about to read 3, iclass 28, count 0 2006.245.07:56:42.36#ibcon#read 3, iclass 28, count 0 2006.245.07:56:42.36#ibcon#about to read 4, iclass 28, count 0 2006.245.07:56:42.36#ibcon#read 4, iclass 28, count 0 2006.245.07:56:42.36#ibcon#about to read 5, iclass 28, count 0 2006.245.07:56:42.36#ibcon#read 5, iclass 28, count 0 2006.245.07:56:42.36#ibcon#about to read 6, iclass 28, count 0 2006.245.07:56:42.36#ibcon#read 6, iclass 28, count 0 2006.245.07:56:42.36#ibcon#end of sib2, iclass 28, count 0 2006.245.07:56:42.36#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:56:42.36#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:56:42.36#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.07:56:42.36#ibcon#*before write, iclass 28, count 0 2006.245.07:56:42.36#ibcon#enter sib2, iclass 28, count 0 2006.245.07:56:42.36#ibcon#flushed, iclass 28, count 0 2006.245.07:56:42.36#ibcon#about to write, iclass 28, count 0 2006.245.07:56:42.36#ibcon#wrote, iclass 28, count 0 2006.245.07:56:42.36#ibcon#about to read 3, iclass 28, count 0 2006.245.07:56:42.40#ibcon#read 3, iclass 28, count 0 2006.245.07:56:42.40#ibcon#about to read 4, iclass 28, count 0 2006.245.07:56:42.40#ibcon#read 4, iclass 28, count 0 2006.245.07:56:42.40#ibcon#about to read 5, iclass 28, count 0 2006.245.07:56:42.40#ibcon#read 5, iclass 28, count 0 2006.245.07:56:42.40#ibcon#about to read 6, iclass 28, count 0 2006.245.07:56:42.40#ibcon#read 6, iclass 28, count 0 2006.245.07:56:42.40#ibcon#end of sib2, iclass 28, count 0 2006.245.07:56:42.40#ibcon#*after write, iclass 28, count 0 2006.245.07:56:42.40#ibcon#*before return 0, iclass 28, count 0 2006.245.07:56:42.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:42.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:42.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:56:42.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:56:42.40$vc4f8/va=7,7 2006.245.07:56:42.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.07:56:42.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.07:56:42.40#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:42.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:56:42.42#abcon#<5=/05 2.8 5.3 27.26 691004.5\r\n> 2006.245.07:56:42.44#abcon#{5=INTERFACE CLEAR} 2006.245.07:56:42.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:56:42.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:56:42.46#ibcon#enter wrdev, iclass 31, count 2 2006.245.07:56:42.46#ibcon#first serial, iclass 31, count 2 2006.245.07:56:42.46#ibcon#enter sib2, iclass 31, count 2 2006.245.07:56:42.46#ibcon#flushed, iclass 31, count 2 2006.245.07:56:42.46#ibcon#about to write, iclass 31, count 2 2006.245.07:56:42.46#ibcon#wrote, iclass 31, count 2 2006.245.07:56:42.46#ibcon#about to read 3, iclass 31, count 2 2006.245.07:56:42.48#ibcon#read 3, iclass 31, count 2 2006.245.07:56:42.48#ibcon#about to read 4, iclass 31, count 2 2006.245.07:56:42.48#ibcon#read 4, iclass 31, count 2 2006.245.07:56:42.48#ibcon#about to read 5, iclass 31, count 2 2006.245.07:56:42.48#ibcon#read 5, iclass 31, count 2 2006.245.07:56:42.48#ibcon#about to read 6, iclass 31, count 2 2006.245.07:56:42.48#ibcon#read 6, iclass 31, count 2 2006.245.07:56:42.48#ibcon#end of sib2, iclass 31, count 2 2006.245.07:56:42.48#ibcon#*mode == 0, iclass 31, count 2 2006.245.07:56:42.48#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.07:56:42.48#ibcon#[25=AT07-07\r\n] 2006.245.07:56:42.48#ibcon#*before write, iclass 31, count 2 2006.245.07:56:42.48#ibcon#enter sib2, iclass 31, count 2 2006.245.07:56:42.48#ibcon#flushed, iclass 31, count 2 2006.245.07:56:42.48#ibcon#about to write, iclass 31, count 2 2006.245.07:56:42.48#ibcon#wrote, iclass 31, count 2 2006.245.07:56:42.48#ibcon#about to read 3, iclass 31, count 2 2006.245.07:56:42.50#abcon#[5=S1D000X0/0*\r\n] 2006.245.07:56:42.51#ibcon#read 3, iclass 31, count 2 2006.245.07:56:42.51#ibcon#about to read 4, iclass 31, count 2 2006.245.07:56:42.51#ibcon#read 4, iclass 31, count 2 2006.245.07:56:42.51#ibcon#about to read 5, iclass 31, count 2 2006.245.07:56:42.51#ibcon#read 5, iclass 31, count 2 2006.245.07:56:42.51#ibcon#about to read 6, iclass 31, count 2 2006.245.07:56:42.51#ibcon#read 6, iclass 31, count 2 2006.245.07:56:42.51#ibcon#end of sib2, iclass 31, count 2 2006.245.07:56:42.51#ibcon#*after write, iclass 31, count 2 2006.245.07:56:42.51#ibcon#*before return 0, iclass 31, count 2 2006.245.07:56:42.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:56:42.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.07:56:42.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.07:56:42.51#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:42.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:56:42.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:56:42.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:56:42.63#ibcon#enter wrdev, iclass 31, count 0 2006.245.07:56:42.63#ibcon#first serial, iclass 31, count 0 2006.245.07:56:42.63#ibcon#enter sib2, iclass 31, count 0 2006.245.07:56:42.63#ibcon#flushed, iclass 31, count 0 2006.245.07:56:42.63#ibcon#about to write, iclass 31, count 0 2006.245.07:56:42.63#ibcon#wrote, iclass 31, count 0 2006.245.07:56:42.63#ibcon#about to read 3, iclass 31, count 0 2006.245.07:56:42.65#ibcon#read 3, iclass 31, count 0 2006.245.07:56:42.65#ibcon#about to read 4, iclass 31, count 0 2006.245.07:56:42.65#ibcon#read 4, iclass 31, count 0 2006.245.07:56:42.65#ibcon#about to read 5, iclass 31, count 0 2006.245.07:56:42.65#ibcon#read 5, iclass 31, count 0 2006.245.07:56:42.65#ibcon#about to read 6, iclass 31, count 0 2006.245.07:56:42.65#ibcon#read 6, iclass 31, count 0 2006.245.07:56:42.65#ibcon#end of sib2, iclass 31, count 0 2006.245.07:56:42.65#ibcon#*mode == 0, iclass 31, count 0 2006.245.07:56:42.65#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.07:56:42.65#ibcon#[25=USB\r\n] 2006.245.07:56:42.65#ibcon#*before write, iclass 31, count 0 2006.245.07:56:42.65#ibcon#enter sib2, iclass 31, count 0 2006.245.07:56:42.65#ibcon#flushed, iclass 31, count 0 2006.245.07:56:42.65#ibcon#about to write, iclass 31, count 0 2006.245.07:56:42.65#ibcon#wrote, iclass 31, count 0 2006.245.07:56:42.65#ibcon#about to read 3, iclass 31, count 0 2006.245.07:56:42.68#ibcon#read 3, iclass 31, count 0 2006.245.07:56:42.68#ibcon#about to read 4, iclass 31, count 0 2006.245.07:56:42.68#ibcon#read 4, iclass 31, count 0 2006.245.07:56:42.68#ibcon#about to read 5, iclass 31, count 0 2006.245.07:56:42.68#ibcon#read 5, iclass 31, count 0 2006.245.07:56:42.68#ibcon#about to read 6, iclass 31, count 0 2006.245.07:56:42.68#ibcon#read 6, iclass 31, count 0 2006.245.07:56:42.68#ibcon#end of sib2, iclass 31, count 0 2006.245.07:56:42.68#ibcon#*after write, iclass 31, count 0 2006.245.07:56:42.68#ibcon#*before return 0, iclass 31, count 0 2006.245.07:56:42.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:56:42.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.07:56:42.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.07:56:42.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.07:56:42.68$vc4f8/valo=8,852.99 2006.245.07:56:42.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.07:56:42.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.07:56:42.68#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:42.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:56:42.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:56:42.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:56:42.68#ibcon#enter wrdev, iclass 36, count 0 2006.245.07:56:42.68#ibcon#first serial, iclass 36, count 0 2006.245.07:56:42.68#ibcon#enter sib2, iclass 36, count 0 2006.245.07:56:42.68#ibcon#flushed, iclass 36, count 0 2006.245.07:56:42.68#ibcon#about to write, iclass 36, count 0 2006.245.07:56:42.68#ibcon#wrote, iclass 36, count 0 2006.245.07:56:42.68#ibcon#about to read 3, iclass 36, count 0 2006.245.07:56:42.70#ibcon#read 3, iclass 36, count 0 2006.245.07:56:42.70#ibcon#about to read 4, iclass 36, count 0 2006.245.07:56:42.70#ibcon#read 4, iclass 36, count 0 2006.245.07:56:42.70#ibcon#about to read 5, iclass 36, count 0 2006.245.07:56:42.70#ibcon#read 5, iclass 36, count 0 2006.245.07:56:42.70#ibcon#about to read 6, iclass 36, count 0 2006.245.07:56:42.70#ibcon#read 6, iclass 36, count 0 2006.245.07:56:42.70#ibcon#end of sib2, iclass 36, count 0 2006.245.07:56:42.70#ibcon#*mode == 0, iclass 36, count 0 2006.245.07:56:42.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.07:56:42.70#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.07:56:42.70#ibcon#*before write, iclass 36, count 0 2006.245.07:56:42.70#ibcon#enter sib2, iclass 36, count 0 2006.245.07:56:42.70#ibcon#flushed, iclass 36, count 0 2006.245.07:56:42.70#ibcon#about to write, iclass 36, count 0 2006.245.07:56:42.70#ibcon#wrote, iclass 36, count 0 2006.245.07:56:42.70#ibcon#about to read 3, iclass 36, count 0 2006.245.07:56:42.74#ibcon#read 3, iclass 36, count 0 2006.245.07:56:42.74#ibcon#about to read 4, iclass 36, count 0 2006.245.07:56:42.74#ibcon#read 4, iclass 36, count 0 2006.245.07:56:42.74#ibcon#about to read 5, iclass 36, count 0 2006.245.07:56:42.74#ibcon#read 5, iclass 36, count 0 2006.245.07:56:42.74#ibcon#about to read 6, iclass 36, count 0 2006.245.07:56:42.74#ibcon#read 6, iclass 36, count 0 2006.245.07:56:42.74#ibcon#end of sib2, iclass 36, count 0 2006.245.07:56:42.74#ibcon#*after write, iclass 36, count 0 2006.245.07:56:42.74#ibcon#*before return 0, iclass 36, count 0 2006.245.07:56:42.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:56:42.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.07:56:42.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.07:56:42.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.07:56:42.74$vc4f8/va=8,8 2006.245.07:56:42.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.07:56:42.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.07:56:42.74#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:42.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:56:42.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:56:42.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:56:42.80#ibcon#enter wrdev, iclass 38, count 2 2006.245.07:56:42.80#ibcon#first serial, iclass 38, count 2 2006.245.07:56:42.80#ibcon#enter sib2, iclass 38, count 2 2006.245.07:56:42.80#ibcon#flushed, iclass 38, count 2 2006.245.07:56:42.80#ibcon#about to write, iclass 38, count 2 2006.245.07:56:42.80#ibcon#wrote, iclass 38, count 2 2006.245.07:56:42.80#ibcon#about to read 3, iclass 38, count 2 2006.245.07:56:42.82#ibcon#read 3, iclass 38, count 2 2006.245.07:56:42.82#ibcon#about to read 4, iclass 38, count 2 2006.245.07:56:42.82#ibcon#read 4, iclass 38, count 2 2006.245.07:56:42.82#ibcon#about to read 5, iclass 38, count 2 2006.245.07:56:42.82#ibcon#read 5, iclass 38, count 2 2006.245.07:56:42.82#ibcon#about to read 6, iclass 38, count 2 2006.245.07:56:42.82#ibcon#read 6, iclass 38, count 2 2006.245.07:56:42.82#ibcon#end of sib2, iclass 38, count 2 2006.245.07:56:42.82#ibcon#*mode == 0, iclass 38, count 2 2006.245.07:56:42.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.07:56:42.82#ibcon#[25=AT08-08\r\n] 2006.245.07:56:42.82#ibcon#*before write, iclass 38, count 2 2006.245.07:56:42.82#ibcon#enter sib2, iclass 38, count 2 2006.245.07:56:42.82#ibcon#flushed, iclass 38, count 2 2006.245.07:56:42.82#ibcon#about to write, iclass 38, count 2 2006.245.07:56:42.82#ibcon#wrote, iclass 38, count 2 2006.245.07:56:42.82#ibcon#about to read 3, iclass 38, count 2 2006.245.07:56:42.85#ibcon#read 3, iclass 38, count 2 2006.245.07:56:42.85#ibcon#about to read 4, iclass 38, count 2 2006.245.07:56:42.85#ibcon#read 4, iclass 38, count 2 2006.245.07:56:42.85#ibcon#about to read 5, iclass 38, count 2 2006.245.07:56:42.85#ibcon#read 5, iclass 38, count 2 2006.245.07:56:42.85#ibcon#about to read 6, iclass 38, count 2 2006.245.07:56:42.85#ibcon#read 6, iclass 38, count 2 2006.245.07:56:42.85#ibcon#end of sib2, iclass 38, count 2 2006.245.07:56:42.85#ibcon#*after write, iclass 38, count 2 2006.245.07:56:42.85#ibcon#*before return 0, iclass 38, count 2 2006.245.07:56:42.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:56:42.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.07:56:42.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.07:56:42.85#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:42.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:56:42.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:56:42.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:56:42.97#ibcon#enter wrdev, iclass 38, count 0 2006.245.07:56:42.97#ibcon#first serial, iclass 38, count 0 2006.245.07:56:42.97#ibcon#enter sib2, iclass 38, count 0 2006.245.07:56:42.97#ibcon#flushed, iclass 38, count 0 2006.245.07:56:42.97#ibcon#about to write, iclass 38, count 0 2006.245.07:56:42.97#ibcon#wrote, iclass 38, count 0 2006.245.07:56:42.97#ibcon#about to read 3, iclass 38, count 0 2006.245.07:56:42.99#ibcon#read 3, iclass 38, count 0 2006.245.07:56:42.99#ibcon#about to read 4, iclass 38, count 0 2006.245.07:56:42.99#ibcon#read 4, iclass 38, count 0 2006.245.07:56:42.99#ibcon#about to read 5, iclass 38, count 0 2006.245.07:56:42.99#ibcon#read 5, iclass 38, count 0 2006.245.07:56:42.99#ibcon#about to read 6, iclass 38, count 0 2006.245.07:56:42.99#ibcon#read 6, iclass 38, count 0 2006.245.07:56:42.99#ibcon#end of sib2, iclass 38, count 0 2006.245.07:56:42.99#ibcon#*mode == 0, iclass 38, count 0 2006.245.07:56:42.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.07:56:42.99#ibcon#[25=USB\r\n] 2006.245.07:56:42.99#ibcon#*before write, iclass 38, count 0 2006.245.07:56:42.99#ibcon#enter sib2, iclass 38, count 0 2006.245.07:56:42.99#ibcon#flushed, iclass 38, count 0 2006.245.07:56:42.99#ibcon#about to write, iclass 38, count 0 2006.245.07:56:42.99#ibcon#wrote, iclass 38, count 0 2006.245.07:56:42.99#ibcon#about to read 3, iclass 38, count 0 2006.245.07:56:43.02#ibcon#read 3, iclass 38, count 0 2006.245.07:56:43.02#ibcon#about to read 4, iclass 38, count 0 2006.245.07:56:43.02#ibcon#read 4, iclass 38, count 0 2006.245.07:56:43.02#ibcon#about to read 5, iclass 38, count 0 2006.245.07:56:43.02#ibcon#read 5, iclass 38, count 0 2006.245.07:56:43.02#ibcon#about to read 6, iclass 38, count 0 2006.245.07:56:43.02#ibcon#read 6, iclass 38, count 0 2006.245.07:56:43.02#ibcon#end of sib2, iclass 38, count 0 2006.245.07:56:43.02#ibcon#*after write, iclass 38, count 0 2006.245.07:56:43.02#ibcon#*before return 0, iclass 38, count 0 2006.245.07:56:43.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:56:43.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.07:56:43.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.07:56:43.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.07:56:43.02$vc4f8/vblo=1,632.99 2006.245.07:56:43.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.07:56:43.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.07:56:43.02#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:43.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:43.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:43.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:43.02#ibcon#enter wrdev, iclass 40, count 0 2006.245.07:56:43.02#ibcon#first serial, iclass 40, count 0 2006.245.07:56:43.02#ibcon#enter sib2, iclass 40, count 0 2006.245.07:56:43.02#ibcon#flushed, iclass 40, count 0 2006.245.07:56:43.02#ibcon#about to write, iclass 40, count 0 2006.245.07:56:43.02#ibcon#wrote, iclass 40, count 0 2006.245.07:56:43.02#ibcon#about to read 3, iclass 40, count 0 2006.245.07:56:43.05#ibcon#read 3, iclass 40, count 0 2006.245.07:56:43.05#ibcon#about to read 4, iclass 40, count 0 2006.245.07:56:43.05#ibcon#read 4, iclass 40, count 0 2006.245.07:56:43.05#ibcon#about to read 5, iclass 40, count 0 2006.245.07:56:43.05#ibcon#read 5, iclass 40, count 0 2006.245.07:56:43.05#ibcon#about to read 6, iclass 40, count 0 2006.245.07:56:43.05#ibcon#read 6, iclass 40, count 0 2006.245.07:56:43.05#ibcon#end of sib2, iclass 40, count 0 2006.245.07:56:43.05#ibcon#*mode == 0, iclass 40, count 0 2006.245.07:56:43.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.07:56:43.05#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.07:56:43.05#ibcon#*before write, iclass 40, count 0 2006.245.07:56:43.05#ibcon#enter sib2, iclass 40, count 0 2006.245.07:56:43.05#ibcon#flushed, iclass 40, count 0 2006.245.07:56:43.05#ibcon#about to write, iclass 40, count 0 2006.245.07:56:43.05#ibcon#wrote, iclass 40, count 0 2006.245.07:56:43.05#ibcon#about to read 3, iclass 40, count 0 2006.245.07:56:43.09#ibcon#read 3, iclass 40, count 0 2006.245.07:56:43.09#ibcon#about to read 4, iclass 40, count 0 2006.245.07:56:43.09#ibcon#read 4, iclass 40, count 0 2006.245.07:56:43.09#ibcon#about to read 5, iclass 40, count 0 2006.245.07:56:43.09#ibcon#read 5, iclass 40, count 0 2006.245.07:56:43.09#ibcon#about to read 6, iclass 40, count 0 2006.245.07:56:43.09#ibcon#read 6, iclass 40, count 0 2006.245.07:56:43.09#ibcon#end of sib2, iclass 40, count 0 2006.245.07:56:43.09#ibcon#*after write, iclass 40, count 0 2006.245.07:56:43.09#ibcon#*before return 0, iclass 40, count 0 2006.245.07:56:43.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:43.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.07:56:43.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.07:56:43.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.07:56:43.09$vc4f8/vb=1,4 2006.245.07:56:43.09#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.07:56:43.09#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.07:56:43.09#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:43.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:43.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:43.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:43.09#ibcon#enter wrdev, iclass 4, count 2 2006.245.07:56:43.09#ibcon#first serial, iclass 4, count 2 2006.245.07:56:43.09#ibcon#enter sib2, iclass 4, count 2 2006.245.07:56:43.09#ibcon#flushed, iclass 4, count 2 2006.245.07:56:43.09#ibcon#about to write, iclass 4, count 2 2006.245.07:56:43.09#ibcon#wrote, iclass 4, count 2 2006.245.07:56:43.09#ibcon#about to read 3, iclass 4, count 2 2006.245.07:56:43.11#ibcon#read 3, iclass 4, count 2 2006.245.07:56:43.11#ibcon#about to read 4, iclass 4, count 2 2006.245.07:56:43.11#ibcon#read 4, iclass 4, count 2 2006.245.07:56:43.11#ibcon#about to read 5, iclass 4, count 2 2006.245.07:56:43.11#ibcon#read 5, iclass 4, count 2 2006.245.07:56:43.11#ibcon#about to read 6, iclass 4, count 2 2006.245.07:56:43.11#ibcon#read 6, iclass 4, count 2 2006.245.07:56:43.11#ibcon#end of sib2, iclass 4, count 2 2006.245.07:56:43.11#ibcon#*mode == 0, iclass 4, count 2 2006.245.07:56:43.11#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.07:56:43.11#ibcon#[27=AT01-04\r\n] 2006.245.07:56:43.11#ibcon#*before write, iclass 4, count 2 2006.245.07:56:43.11#ibcon#enter sib2, iclass 4, count 2 2006.245.07:56:43.11#ibcon#flushed, iclass 4, count 2 2006.245.07:56:43.11#ibcon#about to write, iclass 4, count 2 2006.245.07:56:43.11#ibcon#wrote, iclass 4, count 2 2006.245.07:56:43.11#ibcon#about to read 3, iclass 4, count 2 2006.245.07:56:43.14#ibcon#read 3, iclass 4, count 2 2006.245.07:56:43.14#ibcon#about to read 4, iclass 4, count 2 2006.245.07:56:43.14#ibcon#read 4, iclass 4, count 2 2006.245.07:56:43.14#ibcon#about to read 5, iclass 4, count 2 2006.245.07:56:43.14#ibcon#read 5, iclass 4, count 2 2006.245.07:56:43.14#ibcon#about to read 6, iclass 4, count 2 2006.245.07:56:43.14#ibcon#read 6, iclass 4, count 2 2006.245.07:56:43.14#ibcon#end of sib2, iclass 4, count 2 2006.245.07:56:43.14#ibcon#*after write, iclass 4, count 2 2006.245.07:56:43.14#ibcon#*before return 0, iclass 4, count 2 2006.245.07:56:43.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:43.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.07:56:43.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.07:56:43.14#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:43.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:43.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:43.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:43.26#ibcon#enter wrdev, iclass 4, count 0 2006.245.07:56:43.26#ibcon#first serial, iclass 4, count 0 2006.245.07:56:43.26#ibcon#enter sib2, iclass 4, count 0 2006.245.07:56:43.26#ibcon#flushed, iclass 4, count 0 2006.245.07:56:43.26#ibcon#about to write, iclass 4, count 0 2006.245.07:56:43.26#ibcon#wrote, iclass 4, count 0 2006.245.07:56:43.26#ibcon#about to read 3, iclass 4, count 0 2006.245.07:56:43.28#ibcon#read 3, iclass 4, count 0 2006.245.07:56:43.28#ibcon#about to read 4, iclass 4, count 0 2006.245.07:56:43.28#ibcon#read 4, iclass 4, count 0 2006.245.07:56:43.28#ibcon#about to read 5, iclass 4, count 0 2006.245.07:56:43.28#ibcon#read 5, iclass 4, count 0 2006.245.07:56:43.28#ibcon#about to read 6, iclass 4, count 0 2006.245.07:56:43.28#ibcon#read 6, iclass 4, count 0 2006.245.07:56:43.28#ibcon#end of sib2, iclass 4, count 0 2006.245.07:56:43.28#ibcon#*mode == 0, iclass 4, count 0 2006.245.07:56:43.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.07:56:43.28#ibcon#[27=USB\r\n] 2006.245.07:56:43.28#ibcon#*before write, iclass 4, count 0 2006.245.07:56:43.28#ibcon#enter sib2, iclass 4, count 0 2006.245.07:56:43.28#ibcon#flushed, iclass 4, count 0 2006.245.07:56:43.28#ibcon#about to write, iclass 4, count 0 2006.245.07:56:43.28#ibcon#wrote, iclass 4, count 0 2006.245.07:56:43.28#ibcon#about to read 3, iclass 4, count 0 2006.245.07:56:43.31#ibcon#read 3, iclass 4, count 0 2006.245.07:56:43.31#ibcon#about to read 4, iclass 4, count 0 2006.245.07:56:43.31#ibcon#read 4, iclass 4, count 0 2006.245.07:56:43.31#ibcon#about to read 5, iclass 4, count 0 2006.245.07:56:43.31#ibcon#read 5, iclass 4, count 0 2006.245.07:56:43.31#ibcon#about to read 6, iclass 4, count 0 2006.245.07:56:43.31#ibcon#read 6, iclass 4, count 0 2006.245.07:56:43.31#ibcon#end of sib2, iclass 4, count 0 2006.245.07:56:43.31#ibcon#*after write, iclass 4, count 0 2006.245.07:56:43.31#ibcon#*before return 0, iclass 4, count 0 2006.245.07:56:43.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:43.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.07:56:43.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.07:56:43.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.07:56:43.31$vc4f8/vblo=2,640.99 2006.245.07:56:43.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.07:56:43.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.07:56:43.31#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:43.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:43.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:43.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:43.31#ibcon#enter wrdev, iclass 6, count 0 2006.245.07:56:43.31#ibcon#first serial, iclass 6, count 0 2006.245.07:56:43.31#ibcon#enter sib2, iclass 6, count 0 2006.245.07:56:43.31#ibcon#flushed, iclass 6, count 0 2006.245.07:56:43.31#ibcon#about to write, iclass 6, count 0 2006.245.07:56:43.31#ibcon#wrote, iclass 6, count 0 2006.245.07:56:43.31#ibcon#about to read 3, iclass 6, count 0 2006.245.07:56:43.33#ibcon#read 3, iclass 6, count 0 2006.245.07:56:43.33#ibcon#about to read 4, iclass 6, count 0 2006.245.07:56:43.33#ibcon#read 4, iclass 6, count 0 2006.245.07:56:43.33#ibcon#about to read 5, iclass 6, count 0 2006.245.07:56:43.33#ibcon#read 5, iclass 6, count 0 2006.245.07:56:43.33#ibcon#about to read 6, iclass 6, count 0 2006.245.07:56:43.33#ibcon#read 6, iclass 6, count 0 2006.245.07:56:43.33#ibcon#end of sib2, iclass 6, count 0 2006.245.07:56:43.33#ibcon#*mode == 0, iclass 6, count 0 2006.245.07:56:43.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.07:56:43.33#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.07:56:43.33#ibcon#*before write, iclass 6, count 0 2006.245.07:56:43.33#ibcon#enter sib2, iclass 6, count 0 2006.245.07:56:43.33#ibcon#flushed, iclass 6, count 0 2006.245.07:56:43.33#ibcon#about to write, iclass 6, count 0 2006.245.07:56:43.33#ibcon#wrote, iclass 6, count 0 2006.245.07:56:43.33#ibcon#about to read 3, iclass 6, count 0 2006.245.07:56:43.37#ibcon#read 3, iclass 6, count 0 2006.245.07:56:43.37#ibcon#about to read 4, iclass 6, count 0 2006.245.07:56:43.37#ibcon#read 4, iclass 6, count 0 2006.245.07:56:43.37#ibcon#about to read 5, iclass 6, count 0 2006.245.07:56:43.37#ibcon#read 5, iclass 6, count 0 2006.245.07:56:43.37#ibcon#about to read 6, iclass 6, count 0 2006.245.07:56:43.37#ibcon#read 6, iclass 6, count 0 2006.245.07:56:43.37#ibcon#end of sib2, iclass 6, count 0 2006.245.07:56:43.37#ibcon#*after write, iclass 6, count 0 2006.245.07:56:43.37#ibcon#*before return 0, iclass 6, count 0 2006.245.07:56:43.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:43.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.07:56:43.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.07:56:43.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.07:56:43.37$vc4f8/vb=2,4 2006.245.07:56:43.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.07:56:43.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.07:56:43.37#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:43.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:43.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:43.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:43.43#ibcon#enter wrdev, iclass 10, count 2 2006.245.07:56:43.43#ibcon#first serial, iclass 10, count 2 2006.245.07:56:43.43#ibcon#enter sib2, iclass 10, count 2 2006.245.07:56:43.43#ibcon#flushed, iclass 10, count 2 2006.245.07:56:43.43#ibcon#about to write, iclass 10, count 2 2006.245.07:56:43.43#ibcon#wrote, iclass 10, count 2 2006.245.07:56:43.43#ibcon#about to read 3, iclass 10, count 2 2006.245.07:56:43.45#ibcon#read 3, iclass 10, count 2 2006.245.07:56:43.45#ibcon#about to read 4, iclass 10, count 2 2006.245.07:56:43.45#ibcon#read 4, iclass 10, count 2 2006.245.07:56:43.45#ibcon#about to read 5, iclass 10, count 2 2006.245.07:56:43.45#ibcon#read 5, iclass 10, count 2 2006.245.07:56:43.45#ibcon#about to read 6, iclass 10, count 2 2006.245.07:56:43.45#ibcon#read 6, iclass 10, count 2 2006.245.07:56:43.45#ibcon#end of sib2, iclass 10, count 2 2006.245.07:56:43.45#ibcon#*mode == 0, iclass 10, count 2 2006.245.07:56:43.45#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.07:56:43.45#ibcon#[27=AT02-04\r\n] 2006.245.07:56:43.45#ibcon#*before write, iclass 10, count 2 2006.245.07:56:43.45#ibcon#enter sib2, iclass 10, count 2 2006.245.07:56:43.45#ibcon#flushed, iclass 10, count 2 2006.245.07:56:43.45#ibcon#about to write, iclass 10, count 2 2006.245.07:56:43.45#ibcon#wrote, iclass 10, count 2 2006.245.07:56:43.45#ibcon#about to read 3, iclass 10, count 2 2006.245.07:56:43.48#ibcon#read 3, iclass 10, count 2 2006.245.07:56:43.48#ibcon#about to read 4, iclass 10, count 2 2006.245.07:56:43.48#ibcon#read 4, iclass 10, count 2 2006.245.07:56:43.48#ibcon#about to read 5, iclass 10, count 2 2006.245.07:56:43.48#ibcon#read 5, iclass 10, count 2 2006.245.07:56:43.48#ibcon#about to read 6, iclass 10, count 2 2006.245.07:56:43.48#ibcon#read 6, iclass 10, count 2 2006.245.07:56:43.48#ibcon#end of sib2, iclass 10, count 2 2006.245.07:56:43.48#ibcon#*after write, iclass 10, count 2 2006.245.07:56:43.48#ibcon#*before return 0, iclass 10, count 2 2006.245.07:56:43.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:43.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.07:56:43.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.07:56:43.48#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:43.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:43.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:43.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:43.60#ibcon#enter wrdev, iclass 10, count 0 2006.245.07:56:43.60#ibcon#first serial, iclass 10, count 0 2006.245.07:56:43.60#ibcon#enter sib2, iclass 10, count 0 2006.245.07:56:43.60#ibcon#flushed, iclass 10, count 0 2006.245.07:56:43.60#ibcon#about to write, iclass 10, count 0 2006.245.07:56:43.60#ibcon#wrote, iclass 10, count 0 2006.245.07:56:43.60#ibcon#about to read 3, iclass 10, count 0 2006.245.07:56:43.62#ibcon#read 3, iclass 10, count 0 2006.245.07:56:43.62#ibcon#about to read 4, iclass 10, count 0 2006.245.07:56:43.62#ibcon#read 4, iclass 10, count 0 2006.245.07:56:43.62#ibcon#about to read 5, iclass 10, count 0 2006.245.07:56:43.62#ibcon#read 5, iclass 10, count 0 2006.245.07:56:43.62#ibcon#about to read 6, iclass 10, count 0 2006.245.07:56:43.62#ibcon#read 6, iclass 10, count 0 2006.245.07:56:43.62#ibcon#end of sib2, iclass 10, count 0 2006.245.07:56:43.62#ibcon#*mode == 0, iclass 10, count 0 2006.245.07:56:43.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.07:56:43.62#ibcon#[27=USB\r\n] 2006.245.07:56:43.62#ibcon#*before write, iclass 10, count 0 2006.245.07:56:43.62#ibcon#enter sib2, iclass 10, count 0 2006.245.07:56:43.62#ibcon#flushed, iclass 10, count 0 2006.245.07:56:43.62#ibcon#about to write, iclass 10, count 0 2006.245.07:56:43.62#ibcon#wrote, iclass 10, count 0 2006.245.07:56:43.62#ibcon#about to read 3, iclass 10, count 0 2006.245.07:56:43.65#ibcon#read 3, iclass 10, count 0 2006.245.07:56:43.65#ibcon#about to read 4, iclass 10, count 0 2006.245.07:56:43.65#ibcon#read 4, iclass 10, count 0 2006.245.07:56:43.65#ibcon#about to read 5, iclass 10, count 0 2006.245.07:56:43.65#ibcon#read 5, iclass 10, count 0 2006.245.07:56:43.65#ibcon#about to read 6, iclass 10, count 0 2006.245.07:56:43.65#ibcon#read 6, iclass 10, count 0 2006.245.07:56:43.65#ibcon#end of sib2, iclass 10, count 0 2006.245.07:56:43.65#ibcon#*after write, iclass 10, count 0 2006.245.07:56:43.65#ibcon#*before return 0, iclass 10, count 0 2006.245.07:56:43.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:43.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.07:56:43.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.07:56:43.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.07:56:43.65$vc4f8/vblo=3,656.99 2006.245.07:56:43.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.07:56:43.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.07:56:43.65#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:43.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:43.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:43.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:43.65#ibcon#enter wrdev, iclass 12, count 0 2006.245.07:56:43.65#ibcon#first serial, iclass 12, count 0 2006.245.07:56:43.65#ibcon#enter sib2, iclass 12, count 0 2006.245.07:56:43.65#ibcon#flushed, iclass 12, count 0 2006.245.07:56:43.65#ibcon#about to write, iclass 12, count 0 2006.245.07:56:43.65#ibcon#wrote, iclass 12, count 0 2006.245.07:56:43.65#ibcon#about to read 3, iclass 12, count 0 2006.245.07:56:43.67#ibcon#read 3, iclass 12, count 0 2006.245.07:56:43.67#ibcon#about to read 4, iclass 12, count 0 2006.245.07:56:43.67#ibcon#read 4, iclass 12, count 0 2006.245.07:56:43.67#ibcon#about to read 5, iclass 12, count 0 2006.245.07:56:43.67#ibcon#read 5, iclass 12, count 0 2006.245.07:56:43.67#ibcon#about to read 6, iclass 12, count 0 2006.245.07:56:43.67#ibcon#read 6, iclass 12, count 0 2006.245.07:56:43.67#ibcon#end of sib2, iclass 12, count 0 2006.245.07:56:43.67#ibcon#*mode == 0, iclass 12, count 0 2006.245.07:56:43.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.07:56:43.67#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.07:56:43.67#ibcon#*before write, iclass 12, count 0 2006.245.07:56:43.67#ibcon#enter sib2, iclass 12, count 0 2006.245.07:56:43.67#ibcon#flushed, iclass 12, count 0 2006.245.07:56:43.67#ibcon#about to write, iclass 12, count 0 2006.245.07:56:43.67#ibcon#wrote, iclass 12, count 0 2006.245.07:56:43.67#ibcon#about to read 3, iclass 12, count 0 2006.245.07:56:43.71#ibcon#read 3, iclass 12, count 0 2006.245.07:56:43.71#ibcon#about to read 4, iclass 12, count 0 2006.245.07:56:43.71#ibcon#read 4, iclass 12, count 0 2006.245.07:56:43.71#ibcon#about to read 5, iclass 12, count 0 2006.245.07:56:43.71#ibcon#read 5, iclass 12, count 0 2006.245.07:56:43.71#ibcon#about to read 6, iclass 12, count 0 2006.245.07:56:43.71#ibcon#read 6, iclass 12, count 0 2006.245.07:56:43.71#ibcon#end of sib2, iclass 12, count 0 2006.245.07:56:43.71#ibcon#*after write, iclass 12, count 0 2006.245.07:56:43.71#ibcon#*before return 0, iclass 12, count 0 2006.245.07:56:43.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:43.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.07:56:43.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.07:56:43.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.07:56:43.71$vc4f8/vb=3,4 2006.245.07:56:43.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.07:56:43.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.07:56:43.71#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:43.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:43.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:43.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:43.77#ibcon#enter wrdev, iclass 14, count 2 2006.245.07:56:43.77#ibcon#first serial, iclass 14, count 2 2006.245.07:56:43.77#ibcon#enter sib2, iclass 14, count 2 2006.245.07:56:43.77#ibcon#flushed, iclass 14, count 2 2006.245.07:56:43.77#ibcon#about to write, iclass 14, count 2 2006.245.07:56:43.77#ibcon#wrote, iclass 14, count 2 2006.245.07:56:43.77#ibcon#about to read 3, iclass 14, count 2 2006.245.07:56:43.79#ibcon#read 3, iclass 14, count 2 2006.245.07:56:43.79#ibcon#about to read 4, iclass 14, count 2 2006.245.07:56:43.79#ibcon#read 4, iclass 14, count 2 2006.245.07:56:43.79#ibcon#about to read 5, iclass 14, count 2 2006.245.07:56:43.79#ibcon#read 5, iclass 14, count 2 2006.245.07:56:43.79#ibcon#about to read 6, iclass 14, count 2 2006.245.07:56:43.79#ibcon#read 6, iclass 14, count 2 2006.245.07:56:43.79#ibcon#end of sib2, iclass 14, count 2 2006.245.07:56:43.79#ibcon#*mode == 0, iclass 14, count 2 2006.245.07:56:43.79#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.07:56:43.79#ibcon#[27=AT03-04\r\n] 2006.245.07:56:43.79#ibcon#*before write, iclass 14, count 2 2006.245.07:56:43.79#ibcon#enter sib2, iclass 14, count 2 2006.245.07:56:43.79#ibcon#flushed, iclass 14, count 2 2006.245.07:56:43.79#ibcon#about to write, iclass 14, count 2 2006.245.07:56:43.79#ibcon#wrote, iclass 14, count 2 2006.245.07:56:43.79#ibcon#about to read 3, iclass 14, count 2 2006.245.07:56:43.82#ibcon#read 3, iclass 14, count 2 2006.245.07:56:43.82#ibcon#about to read 4, iclass 14, count 2 2006.245.07:56:43.82#ibcon#read 4, iclass 14, count 2 2006.245.07:56:43.82#ibcon#about to read 5, iclass 14, count 2 2006.245.07:56:43.82#ibcon#read 5, iclass 14, count 2 2006.245.07:56:43.82#ibcon#about to read 6, iclass 14, count 2 2006.245.07:56:43.82#ibcon#read 6, iclass 14, count 2 2006.245.07:56:43.82#ibcon#end of sib2, iclass 14, count 2 2006.245.07:56:43.82#ibcon#*after write, iclass 14, count 2 2006.245.07:56:43.82#ibcon#*before return 0, iclass 14, count 2 2006.245.07:56:43.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:43.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.07:56:43.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.07:56:43.82#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:43.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:43.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:43.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:43.94#ibcon#enter wrdev, iclass 14, count 0 2006.245.07:56:43.94#ibcon#first serial, iclass 14, count 0 2006.245.07:56:43.94#ibcon#enter sib2, iclass 14, count 0 2006.245.07:56:43.94#ibcon#flushed, iclass 14, count 0 2006.245.07:56:43.94#ibcon#about to write, iclass 14, count 0 2006.245.07:56:43.94#ibcon#wrote, iclass 14, count 0 2006.245.07:56:43.94#ibcon#about to read 3, iclass 14, count 0 2006.245.07:56:43.96#ibcon#read 3, iclass 14, count 0 2006.245.07:56:43.96#ibcon#about to read 4, iclass 14, count 0 2006.245.07:56:43.96#ibcon#read 4, iclass 14, count 0 2006.245.07:56:43.96#ibcon#about to read 5, iclass 14, count 0 2006.245.07:56:43.96#ibcon#read 5, iclass 14, count 0 2006.245.07:56:43.96#ibcon#about to read 6, iclass 14, count 0 2006.245.07:56:43.96#ibcon#read 6, iclass 14, count 0 2006.245.07:56:43.96#ibcon#end of sib2, iclass 14, count 0 2006.245.07:56:43.96#ibcon#*mode == 0, iclass 14, count 0 2006.245.07:56:43.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.07:56:43.96#ibcon#[27=USB\r\n] 2006.245.07:56:43.96#ibcon#*before write, iclass 14, count 0 2006.245.07:56:43.96#ibcon#enter sib2, iclass 14, count 0 2006.245.07:56:43.96#ibcon#flushed, iclass 14, count 0 2006.245.07:56:43.96#ibcon#about to write, iclass 14, count 0 2006.245.07:56:43.96#ibcon#wrote, iclass 14, count 0 2006.245.07:56:43.96#ibcon#about to read 3, iclass 14, count 0 2006.245.07:56:43.99#ibcon#read 3, iclass 14, count 0 2006.245.07:56:43.99#ibcon#about to read 4, iclass 14, count 0 2006.245.07:56:43.99#ibcon#read 4, iclass 14, count 0 2006.245.07:56:43.99#ibcon#about to read 5, iclass 14, count 0 2006.245.07:56:43.99#ibcon#read 5, iclass 14, count 0 2006.245.07:56:43.99#ibcon#about to read 6, iclass 14, count 0 2006.245.07:56:43.99#ibcon#read 6, iclass 14, count 0 2006.245.07:56:43.99#ibcon#end of sib2, iclass 14, count 0 2006.245.07:56:43.99#ibcon#*after write, iclass 14, count 0 2006.245.07:56:43.99#ibcon#*before return 0, iclass 14, count 0 2006.245.07:56:43.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:43.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.07:56:43.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.07:56:43.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.07:56:43.99$vc4f8/vblo=4,712.99 2006.245.07:56:43.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.07:56:43.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.07:56:43.99#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:43.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:43.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:43.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:43.99#ibcon#enter wrdev, iclass 16, count 0 2006.245.07:56:43.99#ibcon#first serial, iclass 16, count 0 2006.245.07:56:43.99#ibcon#enter sib2, iclass 16, count 0 2006.245.07:56:43.99#ibcon#flushed, iclass 16, count 0 2006.245.07:56:43.99#ibcon#about to write, iclass 16, count 0 2006.245.07:56:43.99#ibcon#wrote, iclass 16, count 0 2006.245.07:56:43.99#ibcon#about to read 3, iclass 16, count 0 2006.245.07:56:44.02#ibcon#read 3, iclass 16, count 0 2006.245.07:56:44.02#ibcon#about to read 4, iclass 16, count 0 2006.245.07:56:44.02#ibcon#read 4, iclass 16, count 0 2006.245.07:56:44.02#ibcon#about to read 5, iclass 16, count 0 2006.245.07:56:44.02#ibcon#read 5, iclass 16, count 0 2006.245.07:56:44.02#ibcon#about to read 6, iclass 16, count 0 2006.245.07:56:44.02#ibcon#read 6, iclass 16, count 0 2006.245.07:56:44.02#ibcon#end of sib2, iclass 16, count 0 2006.245.07:56:44.02#ibcon#*mode == 0, iclass 16, count 0 2006.245.07:56:44.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.07:56:44.02#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.07:56:44.02#ibcon#*before write, iclass 16, count 0 2006.245.07:56:44.02#ibcon#enter sib2, iclass 16, count 0 2006.245.07:56:44.02#ibcon#flushed, iclass 16, count 0 2006.245.07:56:44.02#ibcon#about to write, iclass 16, count 0 2006.245.07:56:44.02#ibcon#wrote, iclass 16, count 0 2006.245.07:56:44.02#ibcon#about to read 3, iclass 16, count 0 2006.245.07:56:44.06#ibcon#read 3, iclass 16, count 0 2006.245.07:56:44.06#ibcon#about to read 4, iclass 16, count 0 2006.245.07:56:44.06#ibcon#read 4, iclass 16, count 0 2006.245.07:56:44.06#ibcon#about to read 5, iclass 16, count 0 2006.245.07:56:44.06#ibcon#read 5, iclass 16, count 0 2006.245.07:56:44.06#ibcon#about to read 6, iclass 16, count 0 2006.245.07:56:44.06#ibcon#read 6, iclass 16, count 0 2006.245.07:56:44.06#ibcon#end of sib2, iclass 16, count 0 2006.245.07:56:44.06#ibcon#*after write, iclass 16, count 0 2006.245.07:56:44.06#ibcon#*before return 0, iclass 16, count 0 2006.245.07:56:44.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:44.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.07:56:44.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.07:56:44.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.07:56:44.06$vc4f8/vb=4,4 2006.245.07:56:44.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.07:56:44.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.07:56:44.06#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:44.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:44.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:44.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:44.11#ibcon#enter wrdev, iclass 18, count 2 2006.245.07:56:44.11#ibcon#first serial, iclass 18, count 2 2006.245.07:56:44.11#ibcon#enter sib2, iclass 18, count 2 2006.245.07:56:44.11#ibcon#flushed, iclass 18, count 2 2006.245.07:56:44.11#ibcon#about to write, iclass 18, count 2 2006.245.07:56:44.11#ibcon#wrote, iclass 18, count 2 2006.245.07:56:44.11#ibcon#about to read 3, iclass 18, count 2 2006.245.07:56:44.13#ibcon#read 3, iclass 18, count 2 2006.245.07:56:44.13#ibcon#about to read 4, iclass 18, count 2 2006.245.07:56:44.13#ibcon#read 4, iclass 18, count 2 2006.245.07:56:44.13#ibcon#about to read 5, iclass 18, count 2 2006.245.07:56:44.13#ibcon#read 5, iclass 18, count 2 2006.245.07:56:44.13#ibcon#about to read 6, iclass 18, count 2 2006.245.07:56:44.13#ibcon#read 6, iclass 18, count 2 2006.245.07:56:44.13#ibcon#end of sib2, iclass 18, count 2 2006.245.07:56:44.13#ibcon#*mode == 0, iclass 18, count 2 2006.245.07:56:44.13#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.07:56:44.13#ibcon#[27=AT04-04\r\n] 2006.245.07:56:44.13#ibcon#*before write, iclass 18, count 2 2006.245.07:56:44.13#ibcon#enter sib2, iclass 18, count 2 2006.245.07:56:44.13#ibcon#flushed, iclass 18, count 2 2006.245.07:56:44.13#ibcon#about to write, iclass 18, count 2 2006.245.07:56:44.13#ibcon#wrote, iclass 18, count 2 2006.245.07:56:44.13#ibcon#about to read 3, iclass 18, count 2 2006.245.07:56:44.16#ibcon#read 3, iclass 18, count 2 2006.245.07:56:44.16#ibcon#about to read 4, iclass 18, count 2 2006.245.07:56:44.16#ibcon#read 4, iclass 18, count 2 2006.245.07:56:44.16#ibcon#about to read 5, iclass 18, count 2 2006.245.07:56:44.16#ibcon#read 5, iclass 18, count 2 2006.245.07:56:44.16#ibcon#about to read 6, iclass 18, count 2 2006.245.07:56:44.16#ibcon#read 6, iclass 18, count 2 2006.245.07:56:44.16#ibcon#end of sib2, iclass 18, count 2 2006.245.07:56:44.16#ibcon#*after write, iclass 18, count 2 2006.245.07:56:44.16#ibcon#*before return 0, iclass 18, count 2 2006.245.07:56:44.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:44.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.07:56:44.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.07:56:44.16#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:44.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:44.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:44.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:44.28#ibcon#enter wrdev, iclass 18, count 0 2006.245.07:56:44.28#ibcon#first serial, iclass 18, count 0 2006.245.07:56:44.28#ibcon#enter sib2, iclass 18, count 0 2006.245.07:56:44.28#ibcon#flushed, iclass 18, count 0 2006.245.07:56:44.28#ibcon#about to write, iclass 18, count 0 2006.245.07:56:44.28#ibcon#wrote, iclass 18, count 0 2006.245.07:56:44.28#ibcon#about to read 3, iclass 18, count 0 2006.245.07:56:44.30#ibcon#read 3, iclass 18, count 0 2006.245.07:56:44.30#ibcon#about to read 4, iclass 18, count 0 2006.245.07:56:44.30#ibcon#read 4, iclass 18, count 0 2006.245.07:56:44.30#ibcon#about to read 5, iclass 18, count 0 2006.245.07:56:44.30#ibcon#read 5, iclass 18, count 0 2006.245.07:56:44.30#ibcon#about to read 6, iclass 18, count 0 2006.245.07:56:44.30#ibcon#read 6, iclass 18, count 0 2006.245.07:56:44.30#ibcon#end of sib2, iclass 18, count 0 2006.245.07:56:44.30#ibcon#*mode == 0, iclass 18, count 0 2006.245.07:56:44.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.07:56:44.30#ibcon#[27=USB\r\n] 2006.245.07:56:44.30#ibcon#*before write, iclass 18, count 0 2006.245.07:56:44.30#ibcon#enter sib2, iclass 18, count 0 2006.245.07:56:44.30#ibcon#flushed, iclass 18, count 0 2006.245.07:56:44.30#ibcon#about to write, iclass 18, count 0 2006.245.07:56:44.30#ibcon#wrote, iclass 18, count 0 2006.245.07:56:44.30#ibcon#about to read 3, iclass 18, count 0 2006.245.07:56:44.33#ibcon#read 3, iclass 18, count 0 2006.245.07:56:44.33#ibcon#about to read 4, iclass 18, count 0 2006.245.07:56:44.33#ibcon#read 4, iclass 18, count 0 2006.245.07:56:44.33#ibcon#about to read 5, iclass 18, count 0 2006.245.07:56:44.33#ibcon#read 5, iclass 18, count 0 2006.245.07:56:44.33#ibcon#about to read 6, iclass 18, count 0 2006.245.07:56:44.33#ibcon#read 6, iclass 18, count 0 2006.245.07:56:44.33#ibcon#end of sib2, iclass 18, count 0 2006.245.07:56:44.33#ibcon#*after write, iclass 18, count 0 2006.245.07:56:44.33#ibcon#*before return 0, iclass 18, count 0 2006.245.07:56:44.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:44.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.07:56:44.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.07:56:44.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.07:56:44.33$vc4f8/vblo=5,744.99 2006.245.07:56:44.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.07:56:44.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.07:56:44.33#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:44.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:44.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:44.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:44.33#ibcon#enter wrdev, iclass 20, count 0 2006.245.07:56:44.33#ibcon#first serial, iclass 20, count 0 2006.245.07:56:44.33#ibcon#enter sib2, iclass 20, count 0 2006.245.07:56:44.33#ibcon#flushed, iclass 20, count 0 2006.245.07:56:44.33#ibcon#about to write, iclass 20, count 0 2006.245.07:56:44.33#ibcon#wrote, iclass 20, count 0 2006.245.07:56:44.33#ibcon#about to read 3, iclass 20, count 0 2006.245.07:56:44.35#ibcon#read 3, iclass 20, count 0 2006.245.07:56:44.35#ibcon#about to read 4, iclass 20, count 0 2006.245.07:56:44.35#ibcon#read 4, iclass 20, count 0 2006.245.07:56:44.35#ibcon#about to read 5, iclass 20, count 0 2006.245.07:56:44.35#ibcon#read 5, iclass 20, count 0 2006.245.07:56:44.35#ibcon#about to read 6, iclass 20, count 0 2006.245.07:56:44.35#ibcon#read 6, iclass 20, count 0 2006.245.07:56:44.35#ibcon#end of sib2, iclass 20, count 0 2006.245.07:56:44.35#ibcon#*mode == 0, iclass 20, count 0 2006.245.07:56:44.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.07:56:44.35#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.07:56:44.35#ibcon#*before write, iclass 20, count 0 2006.245.07:56:44.35#ibcon#enter sib2, iclass 20, count 0 2006.245.07:56:44.35#ibcon#flushed, iclass 20, count 0 2006.245.07:56:44.35#ibcon#about to write, iclass 20, count 0 2006.245.07:56:44.35#ibcon#wrote, iclass 20, count 0 2006.245.07:56:44.35#ibcon#about to read 3, iclass 20, count 0 2006.245.07:56:44.39#ibcon#read 3, iclass 20, count 0 2006.245.07:56:44.39#ibcon#about to read 4, iclass 20, count 0 2006.245.07:56:44.39#ibcon#read 4, iclass 20, count 0 2006.245.07:56:44.39#ibcon#about to read 5, iclass 20, count 0 2006.245.07:56:44.39#ibcon#read 5, iclass 20, count 0 2006.245.07:56:44.39#ibcon#about to read 6, iclass 20, count 0 2006.245.07:56:44.39#ibcon#read 6, iclass 20, count 0 2006.245.07:56:44.39#ibcon#end of sib2, iclass 20, count 0 2006.245.07:56:44.39#ibcon#*after write, iclass 20, count 0 2006.245.07:56:44.39#ibcon#*before return 0, iclass 20, count 0 2006.245.07:56:44.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:44.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.07:56:44.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.07:56:44.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.07:56:44.39$vc4f8/vb=5,3 2006.245.07:56:44.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.07:56:44.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.07:56:44.39#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:44.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:44.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:44.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:44.45#ibcon#enter wrdev, iclass 22, count 2 2006.245.07:56:44.45#ibcon#first serial, iclass 22, count 2 2006.245.07:56:44.45#ibcon#enter sib2, iclass 22, count 2 2006.245.07:56:44.45#ibcon#flushed, iclass 22, count 2 2006.245.07:56:44.45#ibcon#about to write, iclass 22, count 2 2006.245.07:56:44.45#ibcon#wrote, iclass 22, count 2 2006.245.07:56:44.45#ibcon#about to read 3, iclass 22, count 2 2006.245.07:56:44.47#ibcon#read 3, iclass 22, count 2 2006.245.07:56:44.47#ibcon#about to read 4, iclass 22, count 2 2006.245.07:56:44.47#ibcon#read 4, iclass 22, count 2 2006.245.07:56:44.47#ibcon#about to read 5, iclass 22, count 2 2006.245.07:56:44.47#ibcon#read 5, iclass 22, count 2 2006.245.07:56:44.47#ibcon#about to read 6, iclass 22, count 2 2006.245.07:56:44.47#ibcon#read 6, iclass 22, count 2 2006.245.07:56:44.47#ibcon#end of sib2, iclass 22, count 2 2006.245.07:56:44.47#ibcon#*mode == 0, iclass 22, count 2 2006.245.07:56:44.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.07:56:44.47#ibcon#[27=AT05-03\r\n] 2006.245.07:56:44.47#ibcon#*before write, iclass 22, count 2 2006.245.07:56:44.47#ibcon#enter sib2, iclass 22, count 2 2006.245.07:56:44.47#ibcon#flushed, iclass 22, count 2 2006.245.07:56:44.47#ibcon#about to write, iclass 22, count 2 2006.245.07:56:44.47#ibcon#wrote, iclass 22, count 2 2006.245.07:56:44.47#ibcon#about to read 3, iclass 22, count 2 2006.245.07:56:44.50#ibcon#read 3, iclass 22, count 2 2006.245.07:56:44.50#ibcon#about to read 4, iclass 22, count 2 2006.245.07:56:44.50#ibcon#read 4, iclass 22, count 2 2006.245.07:56:44.50#ibcon#about to read 5, iclass 22, count 2 2006.245.07:56:44.50#ibcon#read 5, iclass 22, count 2 2006.245.07:56:44.50#ibcon#about to read 6, iclass 22, count 2 2006.245.07:56:44.50#ibcon#read 6, iclass 22, count 2 2006.245.07:56:44.50#ibcon#end of sib2, iclass 22, count 2 2006.245.07:56:44.50#ibcon#*after write, iclass 22, count 2 2006.245.07:56:44.50#ibcon#*before return 0, iclass 22, count 2 2006.245.07:56:44.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:44.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.07:56:44.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.07:56:44.50#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:44.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:44.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:44.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:44.62#ibcon#enter wrdev, iclass 22, count 0 2006.245.07:56:44.62#ibcon#first serial, iclass 22, count 0 2006.245.07:56:44.62#ibcon#enter sib2, iclass 22, count 0 2006.245.07:56:44.62#ibcon#flushed, iclass 22, count 0 2006.245.07:56:44.62#ibcon#about to write, iclass 22, count 0 2006.245.07:56:44.62#ibcon#wrote, iclass 22, count 0 2006.245.07:56:44.62#ibcon#about to read 3, iclass 22, count 0 2006.245.07:56:44.64#ibcon#read 3, iclass 22, count 0 2006.245.07:56:44.64#ibcon#about to read 4, iclass 22, count 0 2006.245.07:56:44.64#ibcon#read 4, iclass 22, count 0 2006.245.07:56:44.64#ibcon#about to read 5, iclass 22, count 0 2006.245.07:56:44.64#ibcon#read 5, iclass 22, count 0 2006.245.07:56:44.64#ibcon#about to read 6, iclass 22, count 0 2006.245.07:56:44.64#ibcon#read 6, iclass 22, count 0 2006.245.07:56:44.64#ibcon#end of sib2, iclass 22, count 0 2006.245.07:56:44.64#ibcon#*mode == 0, iclass 22, count 0 2006.245.07:56:44.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.07:56:44.64#ibcon#[27=USB\r\n] 2006.245.07:56:44.64#ibcon#*before write, iclass 22, count 0 2006.245.07:56:44.64#ibcon#enter sib2, iclass 22, count 0 2006.245.07:56:44.64#ibcon#flushed, iclass 22, count 0 2006.245.07:56:44.64#ibcon#about to write, iclass 22, count 0 2006.245.07:56:44.64#ibcon#wrote, iclass 22, count 0 2006.245.07:56:44.64#ibcon#about to read 3, iclass 22, count 0 2006.245.07:56:44.67#ibcon#read 3, iclass 22, count 0 2006.245.07:56:44.67#ibcon#about to read 4, iclass 22, count 0 2006.245.07:56:44.67#ibcon#read 4, iclass 22, count 0 2006.245.07:56:44.67#ibcon#about to read 5, iclass 22, count 0 2006.245.07:56:44.67#ibcon#read 5, iclass 22, count 0 2006.245.07:56:44.67#ibcon#about to read 6, iclass 22, count 0 2006.245.07:56:44.67#ibcon#read 6, iclass 22, count 0 2006.245.07:56:44.67#ibcon#end of sib2, iclass 22, count 0 2006.245.07:56:44.67#ibcon#*after write, iclass 22, count 0 2006.245.07:56:44.67#ibcon#*before return 0, iclass 22, count 0 2006.245.07:56:44.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:44.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.07:56:44.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.07:56:44.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.07:56:44.67$vc4f8/vblo=6,752.99 2006.245.07:56:44.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.07:56:44.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.07:56:44.67#ibcon#ireg 17 cls_cnt 0 2006.245.07:56:44.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:44.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:44.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:44.67#ibcon#enter wrdev, iclass 24, count 0 2006.245.07:56:44.67#ibcon#first serial, iclass 24, count 0 2006.245.07:56:44.67#ibcon#enter sib2, iclass 24, count 0 2006.245.07:56:44.67#ibcon#flushed, iclass 24, count 0 2006.245.07:56:44.67#ibcon#about to write, iclass 24, count 0 2006.245.07:56:44.67#ibcon#wrote, iclass 24, count 0 2006.245.07:56:44.67#ibcon#about to read 3, iclass 24, count 0 2006.245.07:56:44.69#ibcon#read 3, iclass 24, count 0 2006.245.07:56:44.69#ibcon#about to read 4, iclass 24, count 0 2006.245.07:56:44.69#ibcon#read 4, iclass 24, count 0 2006.245.07:56:44.69#ibcon#about to read 5, iclass 24, count 0 2006.245.07:56:44.69#ibcon#read 5, iclass 24, count 0 2006.245.07:56:44.69#ibcon#about to read 6, iclass 24, count 0 2006.245.07:56:44.69#ibcon#read 6, iclass 24, count 0 2006.245.07:56:44.69#ibcon#end of sib2, iclass 24, count 0 2006.245.07:56:44.69#ibcon#*mode == 0, iclass 24, count 0 2006.245.07:56:44.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.07:56:44.69#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.07:56:44.69#ibcon#*before write, iclass 24, count 0 2006.245.07:56:44.69#ibcon#enter sib2, iclass 24, count 0 2006.245.07:56:44.69#ibcon#flushed, iclass 24, count 0 2006.245.07:56:44.69#ibcon#about to write, iclass 24, count 0 2006.245.07:56:44.69#ibcon#wrote, iclass 24, count 0 2006.245.07:56:44.69#ibcon#about to read 3, iclass 24, count 0 2006.245.07:56:44.73#ibcon#read 3, iclass 24, count 0 2006.245.07:56:44.73#ibcon#about to read 4, iclass 24, count 0 2006.245.07:56:44.73#ibcon#read 4, iclass 24, count 0 2006.245.07:56:44.73#ibcon#about to read 5, iclass 24, count 0 2006.245.07:56:44.73#ibcon#read 5, iclass 24, count 0 2006.245.07:56:44.73#ibcon#about to read 6, iclass 24, count 0 2006.245.07:56:44.73#ibcon#read 6, iclass 24, count 0 2006.245.07:56:44.73#ibcon#end of sib2, iclass 24, count 0 2006.245.07:56:44.73#ibcon#*after write, iclass 24, count 0 2006.245.07:56:44.73#ibcon#*before return 0, iclass 24, count 0 2006.245.07:56:44.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:44.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.07:56:44.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.07:56:44.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.07:56:44.73$vc4f8/vb=6,3 2006.245.07:56:44.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.07:56:44.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.07:56:44.73#ibcon#ireg 11 cls_cnt 2 2006.245.07:56:44.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:44.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:44.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:44.80#ibcon#enter wrdev, iclass 26, count 2 2006.245.07:56:44.80#ibcon#first serial, iclass 26, count 2 2006.245.07:56:44.80#ibcon#enter sib2, iclass 26, count 2 2006.245.07:56:44.80#ibcon#flushed, iclass 26, count 2 2006.245.07:56:44.80#ibcon#about to write, iclass 26, count 2 2006.245.07:56:44.80#ibcon#wrote, iclass 26, count 2 2006.245.07:56:44.80#ibcon#about to read 3, iclass 26, count 2 2006.245.07:56:44.81#ibcon#read 3, iclass 26, count 2 2006.245.07:56:44.81#ibcon#about to read 4, iclass 26, count 2 2006.245.07:56:44.81#ibcon#read 4, iclass 26, count 2 2006.245.07:56:44.81#ibcon#about to read 5, iclass 26, count 2 2006.245.07:56:44.81#ibcon#read 5, iclass 26, count 2 2006.245.07:56:44.81#ibcon#about to read 6, iclass 26, count 2 2006.245.07:56:44.81#ibcon#read 6, iclass 26, count 2 2006.245.07:56:44.81#ibcon#end of sib2, iclass 26, count 2 2006.245.07:56:44.81#ibcon#*mode == 0, iclass 26, count 2 2006.245.07:56:44.81#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.07:56:44.81#ibcon#[27=AT06-03\r\n] 2006.245.07:56:44.81#ibcon#*before write, iclass 26, count 2 2006.245.07:56:44.81#ibcon#enter sib2, iclass 26, count 2 2006.245.07:56:44.81#ibcon#flushed, iclass 26, count 2 2006.245.07:56:44.81#ibcon#about to write, iclass 26, count 2 2006.245.07:56:44.81#ibcon#wrote, iclass 26, count 2 2006.245.07:56:44.81#ibcon#about to read 3, iclass 26, count 2 2006.245.07:56:44.84#ibcon#read 3, iclass 26, count 2 2006.245.07:56:44.84#ibcon#about to read 4, iclass 26, count 2 2006.245.07:56:44.84#ibcon#read 4, iclass 26, count 2 2006.245.07:56:44.84#ibcon#about to read 5, iclass 26, count 2 2006.245.07:56:44.84#ibcon#read 5, iclass 26, count 2 2006.245.07:56:44.84#ibcon#about to read 6, iclass 26, count 2 2006.245.07:56:44.84#ibcon#read 6, iclass 26, count 2 2006.245.07:56:44.84#ibcon#end of sib2, iclass 26, count 2 2006.245.07:56:44.84#ibcon#*after write, iclass 26, count 2 2006.245.07:56:44.84#ibcon#*before return 0, iclass 26, count 2 2006.245.07:56:44.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:44.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.07:56:44.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.07:56:44.84#ibcon#ireg 7 cls_cnt 0 2006.245.07:56:44.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:44.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:44.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:44.96#ibcon#enter wrdev, iclass 26, count 0 2006.245.07:56:44.96#ibcon#first serial, iclass 26, count 0 2006.245.07:56:44.96#ibcon#enter sib2, iclass 26, count 0 2006.245.07:56:44.96#ibcon#flushed, iclass 26, count 0 2006.245.07:56:44.96#ibcon#about to write, iclass 26, count 0 2006.245.07:56:44.96#ibcon#wrote, iclass 26, count 0 2006.245.07:56:44.96#ibcon#about to read 3, iclass 26, count 0 2006.245.07:56:44.98#ibcon#read 3, iclass 26, count 0 2006.245.07:56:44.98#ibcon#about to read 4, iclass 26, count 0 2006.245.07:56:44.98#ibcon#read 4, iclass 26, count 0 2006.245.07:56:44.98#ibcon#about to read 5, iclass 26, count 0 2006.245.07:56:44.98#ibcon#read 5, iclass 26, count 0 2006.245.07:56:44.98#ibcon#about to read 6, iclass 26, count 0 2006.245.07:56:44.98#ibcon#read 6, iclass 26, count 0 2006.245.07:56:44.98#ibcon#end of sib2, iclass 26, count 0 2006.245.07:56:44.98#ibcon#*mode == 0, iclass 26, count 0 2006.245.07:56:44.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.07:56:44.98#ibcon#[27=USB\r\n] 2006.245.07:56:44.98#ibcon#*before write, iclass 26, count 0 2006.245.07:56:44.98#ibcon#enter sib2, iclass 26, count 0 2006.245.07:56:44.98#ibcon#flushed, iclass 26, count 0 2006.245.07:56:44.98#ibcon#about to write, iclass 26, count 0 2006.245.07:56:44.98#ibcon#wrote, iclass 26, count 0 2006.245.07:56:44.98#ibcon#about to read 3, iclass 26, count 0 2006.245.07:56:45.01#ibcon#read 3, iclass 26, count 0 2006.245.07:56:45.01#ibcon#about to read 4, iclass 26, count 0 2006.245.07:56:45.01#ibcon#read 4, iclass 26, count 0 2006.245.07:56:45.01#ibcon#about to read 5, iclass 26, count 0 2006.245.07:56:45.01#ibcon#read 5, iclass 26, count 0 2006.245.07:56:45.01#ibcon#about to read 6, iclass 26, count 0 2006.245.07:56:45.01#ibcon#read 6, iclass 26, count 0 2006.245.07:56:45.01#ibcon#end of sib2, iclass 26, count 0 2006.245.07:56:45.01#ibcon#*after write, iclass 26, count 0 2006.245.07:56:45.01#ibcon#*before return 0, iclass 26, count 0 2006.245.07:56:45.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:45.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.07:56:45.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.07:56:45.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.07:56:45.01$vc4f8/vabw=wide 2006.245.07:56:45.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.07:56:45.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.07:56:45.01#ibcon#ireg 8 cls_cnt 0 2006.245.07:56:45.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:45.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:45.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:45.01#ibcon#enter wrdev, iclass 28, count 0 2006.245.07:56:45.01#ibcon#first serial, iclass 28, count 0 2006.245.07:56:45.01#ibcon#enter sib2, iclass 28, count 0 2006.245.07:56:45.01#ibcon#flushed, iclass 28, count 0 2006.245.07:56:45.01#ibcon#about to write, iclass 28, count 0 2006.245.07:56:45.01#ibcon#wrote, iclass 28, count 0 2006.245.07:56:45.01#ibcon#about to read 3, iclass 28, count 0 2006.245.07:56:45.03#ibcon#read 3, iclass 28, count 0 2006.245.07:56:45.03#ibcon#about to read 4, iclass 28, count 0 2006.245.07:56:45.03#ibcon#read 4, iclass 28, count 0 2006.245.07:56:45.03#ibcon#about to read 5, iclass 28, count 0 2006.245.07:56:45.03#ibcon#read 5, iclass 28, count 0 2006.245.07:56:45.03#ibcon#about to read 6, iclass 28, count 0 2006.245.07:56:45.03#ibcon#read 6, iclass 28, count 0 2006.245.07:56:45.03#ibcon#end of sib2, iclass 28, count 0 2006.245.07:56:45.03#ibcon#*mode == 0, iclass 28, count 0 2006.245.07:56:45.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.07:56:45.03#ibcon#[25=BW32\r\n] 2006.245.07:56:45.03#ibcon#*before write, iclass 28, count 0 2006.245.07:56:45.03#ibcon#enter sib2, iclass 28, count 0 2006.245.07:56:45.03#ibcon#flushed, iclass 28, count 0 2006.245.07:56:45.03#ibcon#about to write, iclass 28, count 0 2006.245.07:56:45.03#ibcon#wrote, iclass 28, count 0 2006.245.07:56:45.03#ibcon#about to read 3, iclass 28, count 0 2006.245.07:56:45.06#ibcon#read 3, iclass 28, count 0 2006.245.07:56:45.06#ibcon#about to read 4, iclass 28, count 0 2006.245.07:56:45.06#ibcon#read 4, iclass 28, count 0 2006.245.07:56:45.06#ibcon#about to read 5, iclass 28, count 0 2006.245.07:56:45.06#ibcon#read 5, iclass 28, count 0 2006.245.07:56:45.06#ibcon#about to read 6, iclass 28, count 0 2006.245.07:56:45.06#ibcon#read 6, iclass 28, count 0 2006.245.07:56:45.06#ibcon#end of sib2, iclass 28, count 0 2006.245.07:56:45.06#ibcon#*after write, iclass 28, count 0 2006.245.07:56:45.06#ibcon#*before return 0, iclass 28, count 0 2006.245.07:56:45.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:45.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.07:56:45.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.07:56:45.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.07:56:45.06$vc4f8/vbbw=wide 2006.245.07:56:45.06#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.07:56:45.06#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.07:56:45.06#ibcon#ireg 8 cls_cnt 0 2006.245.07:56:45.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:56:45.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:56:45.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:56:45.13#ibcon#enter wrdev, iclass 30, count 0 2006.245.07:56:45.13#ibcon#first serial, iclass 30, count 0 2006.245.07:56:45.13#ibcon#enter sib2, iclass 30, count 0 2006.245.07:56:45.13#ibcon#flushed, iclass 30, count 0 2006.245.07:56:45.13#ibcon#about to write, iclass 30, count 0 2006.245.07:56:45.13#ibcon#wrote, iclass 30, count 0 2006.245.07:56:45.13#ibcon#about to read 3, iclass 30, count 0 2006.245.07:56:45.15#ibcon#read 3, iclass 30, count 0 2006.245.07:56:45.15#ibcon#about to read 4, iclass 30, count 0 2006.245.07:56:45.15#ibcon#read 4, iclass 30, count 0 2006.245.07:56:45.15#ibcon#about to read 5, iclass 30, count 0 2006.245.07:56:45.15#ibcon#read 5, iclass 30, count 0 2006.245.07:56:45.15#ibcon#about to read 6, iclass 30, count 0 2006.245.07:56:45.15#ibcon#read 6, iclass 30, count 0 2006.245.07:56:45.15#ibcon#end of sib2, iclass 30, count 0 2006.245.07:56:45.15#ibcon#*mode == 0, iclass 30, count 0 2006.245.07:56:45.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.07:56:45.15#ibcon#[27=BW32\r\n] 2006.245.07:56:45.15#ibcon#*before write, iclass 30, count 0 2006.245.07:56:45.15#ibcon#enter sib2, iclass 30, count 0 2006.245.07:56:45.15#ibcon#flushed, iclass 30, count 0 2006.245.07:56:45.15#ibcon#about to write, iclass 30, count 0 2006.245.07:56:45.15#ibcon#wrote, iclass 30, count 0 2006.245.07:56:45.15#ibcon#about to read 3, iclass 30, count 0 2006.245.07:56:45.18#ibcon#read 3, iclass 30, count 0 2006.245.07:56:45.18#ibcon#about to read 4, iclass 30, count 0 2006.245.07:56:45.18#ibcon#read 4, iclass 30, count 0 2006.245.07:56:45.18#ibcon#about to read 5, iclass 30, count 0 2006.245.07:56:45.18#ibcon#read 5, iclass 30, count 0 2006.245.07:56:45.18#ibcon#about to read 6, iclass 30, count 0 2006.245.07:56:45.18#ibcon#read 6, iclass 30, count 0 2006.245.07:56:45.18#ibcon#end of sib2, iclass 30, count 0 2006.245.07:56:45.18#ibcon#*after write, iclass 30, count 0 2006.245.07:56:45.18#ibcon#*before return 0, iclass 30, count 0 2006.245.07:56:45.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:56:45.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.07:56:45.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.07:56:45.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.07:56:45.18$4f8m12a/ifd4f 2006.245.07:56:45.18$ifd4f/lo= 2006.245.07:56:45.18$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.07:56:45.18$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.07:56:45.18$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.07:56:45.18$ifd4f/patch= 2006.245.07:56:45.19$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.07:56:45.19$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.07:56:45.19$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.07:56:45.19$4f8m12a/"form=m,16.000,1:2 2006.245.07:56:45.19$4f8m12a/"tpicd 2006.245.07:56:45.19$4f8m12a/echo=off 2006.245.07:56:45.19$4f8m12a/xlog=off 2006.245.07:56:45.19:!2006.245.07:58:50 2006.245.07:57:07.13#trakl#Source acquired 2006.245.07:57:07.13#flagr#flagr/antenna,acquired 2006.245.07:58:50.01:preob 2006.245.07:58:51.14/onsource/TRACKING 2006.245.07:58:51.14:!2006.245.07:59:00 2006.245.07:59:00.00:data_valid=on 2006.245.07:59:00.00:midob 2006.245.07:59:00.14/onsource/TRACKING 2006.245.07:59:00.14/wx/27.20,1004.5,70 2006.245.07:59:00.37/cable/+6.4097E-03 2006.245.07:59:01.46/va/01,08,usb,yes,31,32 2006.245.07:59:01.46/va/02,07,usb,yes,31,32 2006.245.07:59:01.46/va/03,06,usb,yes,33,33 2006.245.07:59:01.46/va/04,07,usb,yes,32,34 2006.245.07:59:01.46/va/05,07,usb,yes,33,35 2006.245.07:59:01.46/va/06,07,usb,yes,29,29 2006.245.07:59:01.46/va/07,07,usb,yes,29,29 2006.245.07:59:01.46/va/08,08,usb,yes,25,25 2006.245.07:59:01.69/valo/01,532.99,yes,locked 2006.245.07:59:01.69/valo/02,572.99,yes,locked 2006.245.07:59:01.69/valo/03,672.99,yes,locked 2006.245.07:59:01.69/valo/04,832.99,yes,locked 2006.245.07:59:01.69/valo/05,652.99,yes,locked 2006.245.07:59:01.69/valo/06,772.99,yes,locked 2006.245.07:59:01.69/valo/07,832.99,yes,locked 2006.245.07:59:01.69/valo/08,852.99,yes,locked 2006.245.07:59:02.78/vb/01,04,usb,yes,30,29 2006.245.07:59:02.78/vb/02,04,usb,yes,32,34 2006.245.07:59:02.78/vb/03,04,usb,yes,29,32 2006.245.07:59:02.78/vb/04,04,usb,yes,29,30 2006.245.07:59:02.78/vb/05,03,usb,yes,35,39 2006.245.07:59:02.78/vb/06,03,usb,yes,35,39 2006.245.07:59:02.78/vb/07,04,usb,yes,31,31 2006.245.07:59:02.78/vb/08,03,usb,yes,35,39 2006.245.07:59:03.02/vblo/01,632.99,yes,locked 2006.245.07:59:03.02/vblo/02,640.99,yes,locked 2006.245.07:59:03.02/vblo/03,656.99,yes,locked 2006.245.07:59:03.02/vblo/04,712.99,yes,locked 2006.245.07:59:03.02/vblo/05,744.99,yes,locked 2006.245.07:59:03.02/vblo/06,752.99,yes,locked 2006.245.07:59:03.02/vblo/07,734.99,yes,locked 2006.245.07:59:03.02/vblo/08,744.99,yes,locked 2006.245.07:59:03.17/vabw/8 2006.245.07:59:03.32/vbbw/8 2006.245.07:59:03.49/xfe/off,on,13.2 2006.245.07:59:03.88/ifatt/23,28,28,28 2006.245.07:59:04.07/fmout-gps/S +4.38E-07 2006.245.07:59:04.11:!2006.245.08:00:00 2006.245.08:00:00.01:data_valid=off 2006.245.08:00:00.02:postob 2006.245.08:00:00.14/cable/+6.4096E-03 2006.245.08:00:00.15/wx/27.17,1004.5,70 2006.245.08:00:01.07/fmout-gps/S +4.38E-07 2006.245.08:00:01.08:scan_name=245-0800,k06245,60 2006.245.08:00:01.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.245.08:00:02.14#flagr#flagr/antenna,new-source 2006.245.08:00:02.15:checkk5 2006.245.08:00:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:00:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:00:03.56/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:00:03.98/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:00:04.47/chk_obsdata//k5ts1/T2450759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:00:04.92/chk_obsdata//k5ts2/T2450759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:00:05.36/chk_obsdata//k5ts3/T2450759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:00:05.83/chk_obsdata//k5ts4/T2450759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:00:06.65/k5log//k5ts1_log_newline 2006.245.08:00:07.51/k5log//k5ts2_log_newline 2006.245.08:00:09.35/k5log//k5ts3_log_newline 2006.245.08:00:10.21/k5log//k5ts4_log_newline 2006.245.08:00:10.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:00:10.23:4f8m12a=2 2006.245.08:00:10.23$4f8m12a/echo=on 2006.245.08:00:10.23$4f8m12a/pcalon 2006.245.08:00:10.23$pcalon/"no phase cal control is implemented here 2006.245.08:00:10.23$4f8m12a/"tpicd=stop 2006.245.08:00:10.23$4f8m12a/vc4f8 2006.245.08:00:10.23$vc4f8/valo=1,532.99 2006.245.08:00:10.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:00:10.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:00:10.24#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:10.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:10.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:10.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:10.24#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:00:10.24#ibcon#first serial, iclass 3, count 0 2006.245.08:00:10.24#ibcon#enter sib2, iclass 3, count 0 2006.245.08:00:10.24#ibcon#flushed, iclass 3, count 0 2006.245.08:00:10.24#ibcon#about to write, iclass 3, count 0 2006.245.08:00:10.24#ibcon#wrote, iclass 3, count 0 2006.245.08:00:10.24#ibcon#about to read 3, iclass 3, count 0 2006.245.08:00:10.28#ibcon#read 3, iclass 3, count 0 2006.245.08:00:10.28#ibcon#about to read 4, iclass 3, count 0 2006.245.08:00:10.28#ibcon#read 4, iclass 3, count 0 2006.245.08:00:10.28#ibcon#about to read 5, iclass 3, count 0 2006.245.08:00:10.28#ibcon#read 5, iclass 3, count 0 2006.245.08:00:10.28#ibcon#about to read 6, iclass 3, count 0 2006.245.08:00:10.28#ibcon#read 6, iclass 3, count 0 2006.245.08:00:10.28#ibcon#end of sib2, iclass 3, count 0 2006.245.08:00:10.28#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:00:10.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:00:10.28#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:00:10.28#ibcon#*before write, iclass 3, count 0 2006.245.08:00:10.28#ibcon#enter sib2, iclass 3, count 0 2006.245.08:00:10.28#ibcon#flushed, iclass 3, count 0 2006.245.08:00:10.28#ibcon#about to write, iclass 3, count 0 2006.245.08:00:10.28#ibcon#wrote, iclass 3, count 0 2006.245.08:00:10.28#ibcon#about to read 3, iclass 3, count 0 2006.245.08:00:10.32#ibcon#read 3, iclass 3, count 0 2006.245.08:00:10.32#ibcon#about to read 4, iclass 3, count 0 2006.245.08:00:10.32#ibcon#read 4, iclass 3, count 0 2006.245.08:00:10.32#ibcon#about to read 5, iclass 3, count 0 2006.245.08:00:10.32#ibcon#read 5, iclass 3, count 0 2006.245.08:00:10.32#ibcon#about to read 6, iclass 3, count 0 2006.245.08:00:10.32#ibcon#read 6, iclass 3, count 0 2006.245.08:00:10.32#ibcon#end of sib2, iclass 3, count 0 2006.245.08:00:10.32#ibcon#*after write, iclass 3, count 0 2006.245.08:00:10.32#ibcon#*before return 0, iclass 3, count 0 2006.245.08:00:10.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:10.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:10.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:00:10.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:00:10.32$vc4f8/va=1,8 2006.245.08:00:10.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:00:10.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:00:10.32#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:10.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:10.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:10.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:10.32#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:00:10.32#ibcon#first serial, iclass 5, count 2 2006.245.08:00:10.32#ibcon#enter sib2, iclass 5, count 2 2006.245.08:00:10.32#ibcon#flushed, iclass 5, count 2 2006.245.08:00:10.32#ibcon#about to write, iclass 5, count 2 2006.245.08:00:10.32#ibcon#wrote, iclass 5, count 2 2006.245.08:00:10.32#ibcon#about to read 3, iclass 5, count 2 2006.245.08:00:10.34#ibcon#read 3, iclass 5, count 2 2006.245.08:00:10.34#ibcon#about to read 4, iclass 5, count 2 2006.245.08:00:10.34#ibcon#read 4, iclass 5, count 2 2006.245.08:00:10.34#ibcon#about to read 5, iclass 5, count 2 2006.245.08:00:10.34#ibcon#read 5, iclass 5, count 2 2006.245.08:00:10.34#ibcon#about to read 6, iclass 5, count 2 2006.245.08:00:10.34#ibcon#read 6, iclass 5, count 2 2006.245.08:00:10.34#ibcon#end of sib2, iclass 5, count 2 2006.245.08:00:10.34#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:00:10.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:00:10.34#ibcon#[25=AT01-08\r\n] 2006.245.08:00:10.34#ibcon#*before write, iclass 5, count 2 2006.245.08:00:10.34#ibcon#enter sib2, iclass 5, count 2 2006.245.08:00:10.34#ibcon#flushed, iclass 5, count 2 2006.245.08:00:10.34#ibcon#about to write, iclass 5, count 2 2006.245.08:00:10.34#ibcon#wrote, iclass 5, count 2 2006.245.08:00:10.34#ibcon#about to read 3, iclass 5, count 2 2006.245.08:00:10.37#ibcon#read 3, iclass 5, count 2 2006.245.08:00:10.37#ibcon#about to read 4, iclass 5, count 2 2006.245.08:00:10.37#ibcon#read 4, iclass 5, count 2 2006.245.08:00:10.37#ibcon#about to read 5, iclass 5, count 2 2006.245.08:00:10.37#ibcon#read 5, iclass 5, count 2 2006.245.08:00:10.37#ibcon#about to read 6, iclass 5, count 2 2006.245.08:00:10.37#ibcon#read 6, iclass 5, count 2 2006.245.08:00:10.37#ibcon#end of sib2, iclass 5, count 2 2006.245.08:00:10.37#ibcon#*after write, iclass 5, count 2 2006.245.08:00:10.37#ibcon#*before return 0, iclass 5, count 2 2006.245.08:00:10.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:10.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:10.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:00:10.37#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:10.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:10.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:10.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:10.49#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:00:10.49#ibcon#first serial, iclass 5, count 0 2006.245.08:00:10.49#ibcon#enter sib2, iclass 5, count 0 2006.245.08:00:10.49#ibcon#flushed, iclass 5, count 0 2006.245.08:00:10.49#ibcon#about to write, iclass 5, count 0 2006.245.08:00:10.49#ibcon#wrote, iclass 5, count 0 2006.245.08:00:10.49#ibcon#about to read 3, iclass 5, count 0 2006.245.08:00:10.51#ibcon#read 3, iclass 5, count 0 2006.245.08:00:10.51#ibcon#about to read 4, iclass 5, count 0 2006.245.08:00:10.51#ibcon#read 4, iclass 5, count 0 2006.245.08:00:10.51#ibcon#about to read 5, iclass 5, count 0 2006.245.08:00:10.51#ibcon#read 5, iclass 5, count 0 2006.245.08:00:10.51#ibcon#about to read 6, iclass 5, count 0 2006.245.08:00:10.51#ibcon#read 6, iclass 5, count 0 2006.245.08:00:10.51#ibcon#end of sib2, iclass 5, count 0 2006.245.08:00:10.51#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:00:10.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:00:10.51#ibcon#[25=USB\r\n] 2006.245.08:00:10.51#ibcon#*before write, iclass 5, count 0 2006.245.08:00:10.51#ibcon#enter sib2, iclass 5, count 0 2006.245.08:00:10.51#ibcon#flushed, iclass 5, count 0 2006.245.08:00:10.51#ibcon#about to write, iclass 5, count 0 2006.245.08:00:10.51#ibcon#wrote, iclass 5, count 0 2006.245.08:00:10.51#ibcon#about to read 3, iclass 5, count 0 2006.245.08:00:10.54#ibcon#read 3, iclass 5, count 0 2006.245.08:00:10.54#ibcon#about to read 4, iclass 5, count 0 2006.245.08:00:10.54#ibcon#read 4, iclass 5, count 0 2006.245.08:00:10.54#ibcon#about to read 5, iclass 5, count 0 2006.245.08:00:10.54#ibcon#read 5, iclass 5, count 0 2006.245.08:00:10.54#ibcon#about to read 6, iclass 5, count 0 2006.245.08:00:10.54#ibcon#read 6, iclass 5, count 0 2006.245.08:00:10.54#ibcon#end of sib2, iclass 5, count 0 2006.245.08:00:10.54#ibcon#*after write, iclass 5, count 0 2006.245.08:00:10.54#ibcon#*before return 0, iclass 5, count 0 2006.245.08:00:10.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:10.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:10.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:00:10.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:00:10.54$vc4f8/valo=2,572.99 2006.245.08:00:10.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:00:10.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:00:10.54#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:10.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:10.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:10.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:10.54#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:00:10.54#ibcon#first serial, iclass 7, count 0 2006.245.08:00:10.54#ibcon#enter sib2, iclass 7, count 0 2006.245.08:00:10.54#ibcon#flushed, iclass 7, count 0 2006.245.08:00:10.54#ibcon#about to write, iclass 7, count 0 2006.245.08:00:10.54#ibcon#wrote, iclass 7, count 0 2006.245.08:00:10.54#ibcon#about to read 3, iclass 7, count 0 2006.245.08:00:10.57#ibcon#read 3, iclass 7, count 0 2006.245.08:00:10.57#ibcon#about to read 4, iclass 7, count 0 2006.245.08:00:10.57#ibcon#read 4, iclass 7, count 0 2006.245.08:00:10.57#ibcon#about to read 5, iclass 7, count 0 2006.245.08:00:10.57#ibcon#read 5, iclass 7, count 0 2006.245.08:00:10.57#ibcon#about to read 6, iclass 7, count 0 2006.245.08:00:10.57#ibcon#read 6, iclass 7, count 0 2006.245.08:00:10.57#ibcon#end of sib2, iclass 7, count 0 2006.245.08:00:10.57#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:00:10.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:00:10.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:00:10.57#ibcon#*before write, iclass 7, count 0 2006.245.08:00:10.57#ibcon#enter sib2, iclass 7, count 0 2006.245.08:00:10.57#ibcon#flushed, iclass 7, count 0 2006.245.08:00:10.57#ibcon#about to write, iclass 7, count 0 2006.245.08:00:10.57#ibcon#wrote, iclass 7, count 0 2006.245.08:00:10.57#ibcon#about to read 3, iclass 7, count 0 2006.245.08:00:10.61#ibcon#read 3, iclass 7, count 0 2006.245.08:00:10.61#ibcon#about to read 4, iclass 7, count 0 2006.245.08:00:10.61#ibcon#read 4, iclass 7, count 0 2006.245.08:00:10.61#ibcon#about to read 5, iclass 7, count 0 2006.245.08:00:10.61#ibcon#read 5, iclass 7, count 0 2006.245.08:00:10.61#ibcon#about to read 6, iclass 7, count 0 2006.245.08:00:10.61#ibcon#read 6, iclass 7, count 0 2006.245.08:00:10.61#ibcon#end of sib2, iclass 7, count 0 2006.245.08:00:10.61#ibcon#*after write, iclass 7, count 0 2006.245.08:00:10.61#ibcon#*before return 0, iclass 7, count 0 2006.245.08:00:10.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:10.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:10.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:00:10.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:00:10.61$vc4f8/va=2,7 2006.245.08:00:10.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:00:10.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:00:10.61#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:10.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:10.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:10.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:10.66#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:00:10.66#ibcon#first serial, iclass 11, count 2 2006.245.08:00:10.66#ibcon#enter sib2, iclass 11, count 2 2006.245.08:00:10.66#ibcon#flushed, iclass 11, count 2 2006.245.08:00:10.66#ibcon#about to write, iclass 11, count 2 2006.245.08:00:10.66#ibcon#wrote, iclass 11, count 2 2006.245.08:00:10.66#ibcon#about to read 3, iclass 11, count 2 2006.245.08:00:10.68#ibcon#read 3, iclass 11, count 2 2006.245.08:00:10.68#ibcon#about to read 4, iclass 11, count 2 2006.245.08:00:10.68#ibcon#read 4, iclass 11, count 2 2006.245.08:00:10.68#ibcon#about to read 5, iclass 11, count 2 2006.245.08:00:10.68#ibcon#read 5, iclass 11, count 2 2006.245.08:00:10.68#ibcon#about to read 6, iclass 11, count 2 2006.245.08:00:10.68#ibcon#read 6, iclass 11, count 2 2006.245.08:00:10.68#ibcon#end of sib2, iclass 11, count 2 2006.245.08:00:10.68#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:00:10.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:00:10.68#ibcon#[25=AT02-07\r\n] 2006.245.08:00:10.68#ibcon#*before write, iclass 11, count 2 2006.245.08:00:10.68#ibcon#enter sib2, iclass 11, count 2 2006.245.08:00:10.68#ibcon#flushed, iclass 11, count 2 2006.245.08:00:10.68#ibcon#about to write, iclass 11, count 2 2006.245.08:00:10.68#ibcon#wrote, iclass 11, count 2 2006.245.08:00:10.68#ibcon#about to read 3, iclass 11, count 2 2006.245.08:00:10.71#ibcon#read 3, iclass 11, count 2 2006.245.08:00:10.71#ibcon#about to read 4, iclass 11, count 2 2006.245.08:00:10.71#ibcon#read 4, iclass 11, count 2 2006.245.08:00:10.71#ibcon#about to read 5, iclass 11, count 2 2006.245.08:00:10.71#ibcon#read 5, iclass 11, count 2 2006.245.08:00:10.71#ibcon#about to read 6, iclass 11, count 2 2006.245.08:00:10.71#ibcon#read 6, iclass 11, count 2 2006.245.08:00:10.71#ibcon#end of sib2, iclass 11, count 2 2006.245.08:00:10.71#ibcon#*after write, iclass 11, count 2 2006.245.08:00:10.71#ibcon#*before return 0, iclass 11, count 2 2006.245.08:00:10.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:10.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:10.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:00:10.71#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:10.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:10.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:10.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:10.83#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:00:10.83#ibcon#first serial, iclass 11, count 0 2006.245.08:00:10.83#ibcon#enter sib2, iclass 11, count 0 2006.245.08:00:10.83#ibcon#flushed, iclass 11, count 0 2006.245.08:00:10.83#ibcon#about to write, iclass 11, count 0 2006.245.08:00:10.83#ibcon#wrote, iclass 11, count 0 2006.245.08:00:10.83#ibcon#about to read 3, iclass 11, count 0 2006.245.08:00:10.85#ibcon#read 3, iclass 11, count 0 2006.245.08:00:10.85#ibcon#about to read 4, iclass 11, count 0 2006.245.08:00:10.85#ibcon#read 4, iclass 11, count 0 2006.245.08:00:10.85#ibcon#about to read 5, iclass 11, count 0 2006.245.08:00:10.85#ibcon#read 5, iclass 11, count 0 2006.245.08:00:10.85#ibcon#about to read 6, iclass 11, count 0 2006.245.08:00:10.85#ibcon#read 6, iclass 11, count 0 2006.245.08:00:10.85#ibcon#end of sib2, iclass 11, count 0 2006.245.08:00:10.85#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:00:10.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:00:10.85#ibcon#[25=USB\r\n] 2006.245.08:00:10.85#ibcon#*before write, iclass 11, count 0 2006.245.08:00:10.85#ibcon#enter sib2, iclass 11, count 0 2006.245.08:00:10.85#ibcon#flushed, iclass 11, count 0 2006.245.08:00:10.85#ibcon#about to write, iclass 11, count 0 2006.245.08:00:10.85#ibcon#wrote, iclass 11, count 0 2006.245.08:00:10.85#ibcon#about to read 3, iclass 11, count 0 2006.245.08:00:10.88#ibcon#read 3, iclass 11, count 0 2006.245.08:00:10.88#ibcon#about to read 4, iclass 11, count 0 2006.245.08:00:10.88#ibcon#read 4, iclass 11, count 0 2006.245.08:00:10.88#ibcon#about to read 5, iclass 11, count 0 2006.245.08:00:10.88#ibcon#read 5, iclass 11, count 0 2006.245.08:00:10.88#ibcon#about to read 6, iclass 11, count 0 2006.245.08:00:10.88#ibcon#read 6, iclass 11, count 0 2006.245.08:00:10.88#ibcon#end of sib2, iclass 11, count 0 2006.245.08:00:10.88#ibcon#*after write, iclass 11, count 0 2006.245.08:00:10.88#ibcon#*before return 0, iclass 11, count 0 2006.245.08:00:10.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:10.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:10.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:00:10.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:00:10.88$vc4f8/valo=3,672.99 2006.245.08:00:10.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:00:10.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:00:10.88#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:10.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:10.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:10.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:10.88#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:00:10.88#ibcon#first serial, iclass 13, count 0 2006.245.08:00:10.88#ibcon#enter sib2, iclass 13, count 0 2006.245.08:00:10.88#ibcon#flushed, iclass 13, count 0 2006.245.08:00:10.88#ibcon#about to write, iclass 13, count 0 2006.245.08:00:10.88#ibcon#wrote, iclass 13, count 0 2006.245.08:00:10.88#ibcon#about to read 3, iclass 13, count 0 2006.245.08:00:10.90#ibcon#read 3, iclass 13, count 0 2006.245.08:00:10.90#ibcon#about to read 4, iclass 13, count 0 2006.245.08:00:10.90#ibcon#read 4, iclass 13, count 0 2006.245.08:00:10.90#ibcon#about to read 5, iclass 13, count 0 2006.245.08:00:10.90#ibcon#read 5, iclass 13, count 0 2006.245.08:00:10.90#ibcon#about to read 6, iclass 13, count 0 2006.245.08:00:10.90#ibcon#read 6, iclass 13, count 0 2006.245.08:00:10.90#ibcon#end of sib2, iclass 13, count 0 2006.245.08:00:10.90#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:00:10.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:00:10.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:00:10.90#ibcon#*before write, iclass 13, count 0 2006.245.08:00:10.90#ibcon#enter sib2, iclass 13, count 0 2006.245.08:00:10.90#ibcon#flushed, iclass 13, count 0 2006.245.08:00:10.90#ibcon#about to write, iclass 13, count 0 2006.245.08:00:10.90#ibcon#wrote, iclass 13, count 0 2006.245.08:00:10.90#ibcon#about to read 3, iclass 13, count 0 2006.245.08:00:10.94#ibcon#read 3, iclass 13, count 0 2006.245.08:00:10.94#ibcon#about to read 4, iclass 13, count 0 2006.245.08:00:10.94#ibcon#read 4, iclass 13, count 0 2006.245.08:00:10.94#ibcon#about to read 5, iclass 13, count 0 2006.245.08:00:10.94#ibcon#read 5, iclass 13, count 0 2006.245.08:00:10.94#ibcon#about to read 6, iclass 13, count 0 2006.245.08:00:10.94#ibcon#read 6, iclass 13, count 0 2006.245.08:00:10.94#ibcon#end of sib2, iclass 13, count 0 2006.245.08:00:10.94#ibcon#*after write, iclass 13, count 0 2006.245.08:00:10.94#ibcon#*before return 0, iclass 13, count 0 2006.245.08:00:10.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:10.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:10.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:00:10.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:00:10.94$vc4f8/va=3,6 2006.245.08:00:10.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:00:10.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:00:10.94#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:10.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:11.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:11.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:11.01#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:00:11.01#ibcon#first serial, iclass 15, count 2 2006.245.08:00:11.01#ibcon#enter sib2, iclass 15, count 2 2006.245.08:00:11.01#ibcon#flushed, iclass 15, count 2 2006.245.08:00:11.01#ibcon#about to write, iclass 15, count 2 2006.245.08:00:11.01#ibcon#wrote, iclass 15, count 2 2006.245.08:00:11.01#ibcon#about to read 3, iclass 15, count 2 2006.245.08:00:11.02#ibcon#read 3, iclass 15, count 2 2006.245.08:00:11.03#ibcon#about to read 4, iclass 15, count 2 2006.245.08:00:11.03#ibcon#read 4, iclass 15, count 2 2006.245.08:00:11.03#ibcon#about to read 5, iclass 15, count 2 2006.245.08:00:11.03#ibcon#read 5, iclass 15, count 2 2006.245.08:00:11.03#ibcon#about to read 6, iclass 15, count 2 2006.245.08:00:11.03#ibcon#read 6, iclass 15, count 2 2006.245.08:00:11.03#ibcon#end of sib2, iclass 15, count 2 2006.245.08:00:11.03#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:00:11.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:00:11.03#ibcon#[25=AT03-06\r\n] 2006.245.08:00:11.03#ibcon#*before write, iclass 15, count 2 2006.245.08:00:11.03#ibcon#enter sib2, iclass 15, count 2 2006.245.08:00:11.03#ibcon#flushed, iclass 15, count 2 2006.245.08:00:11.03#ibcon#about to write, iclass 15, count 2 2006.245.08:00:11.03#ibcon#wrote, iclass 15, count 2 2006.245.08:00:11.03#ibcon#about to read 3, iclass 15, count 2 2006.245.08:00:11.05#ibcon#read 3, iclass 15, count 2 2006.245.08:00:11.05#ibcon#about to read 4, iclass 15, count 2 2006.245.08:00:11.05#ibcon#read 4, iclass 15, count 2 2006.245.08:00:11.05#ibcon#about to read 5, iclass 15, count 2 2006.245.08:00:11.05#ibcon#read 5, iclass 15, count 2 2006.245.08:00:11.05#ibcon#about to read 6, iclass 15, count 2 2006.245.08:00:11.05#ibcon#read 6, iclass 15, count 2 2006.245.08:00:11.05#ibcon#end of sib2, iclass 15, count 2 2006.245.08:00:11.05#ibcon#*after write, iclass 15, count 2 2006.245.08:00:11.05#ibcon#*before return 0, iclass 15, count 2 2006.245.08:00:11.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:11.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:11.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:00:11.05#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:11.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:11.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:11.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:11.17#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:00:11.17#ibcon#first serial, iclass 15, count 0 2006.245.08:00:11.17#ibcon#enter sib2, iclass 15, count 0 2006.245.08:00:11.17#ibcon#flushed, iclass 15, count 0 2006.245.08:00:11.17#ibcon#about to write, iclass 15, count 0 2006.245.08:00:11.17#ibcon#wrote, iclass 15, count 0 2006.245.08:00:11.17#ibcon#about to read 3, iclass 15, count 0 2006.245.08:00:11.21#ibcon#read 3, iclass 15, count 0 2006.245.08:00:11.21#ibcon#about to read 4, iclass 15, count 0 2006.245.08:00:11.21#ibcon#read 4, iclass 15, count 0 2006.245.08:00:11.21#ibcon#about to read 5, iclass 15, count 0 2006.245.08:00:11.21#ibcon#read 5, iclass 15, count 0 2006.245.08:00:11.21#ibcon#about to read 6, iclass 15, count 0 2006.245.08:00:11.21#ibcon#read 6, iclass 15, count 0 2006.245.08:00:11.21#ibcon#end of sib2, iclass 15, count 0 2006.245.08:00:11.21#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:00:11.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:00:11.21#ibcon#[25=USB\r\n] 2006.245.08:00:11.21#ibcon#*before write, iclass 15, count 0 2006.245.08:00:11.21#ibcon#enter sib2, iclass 15, count 0 2006.245.08:00:11.21#ibcon#flushed, iclass 15, count 0 2006.245.08:00:11.21#ibcon#about to write, iclass 15, count 0 2006.245.08:00:11.21#ibcon#wrote, iclass 15, count 0 2006.245.08:00:11.21#ibcon#about to read 3, iclass 15, count 0 2006.245.08:00:11.23#ibcon#read 3, iclass 15, count 0 2006.245.08:00:11.23#ibcon#about to read 4, iclass 15, count 0 2006.245.08:00:11.23#ibcon#read 4, iclass 15, count 0 2006.245.08:00:11.23#ibcon#about to read 5, iclass 15, count 0 2006.245.08:00:11.23#ibcon#read 5, iclass 15, count 0 2006.245.08:00:11.23#ibcon#about to read 6, iclass 15, count 0 2006.245.08:00:11.23#ibcon#read 6, iclass 15, count 0 2006.245.08:00:11.23#ibcon#end of sib2, iclass 15, count 0 2006.245.08:00:11.23#ibcon#*after write, iclass 15, count 0 2006.245.08:00:11.23#ibcon#*before return 0, iclass 15, count 0 2006.245.08:00:11.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:11.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:11.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:00:11.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:00:11.23$vc4f8/valo=4,832.99 2006.245.08:00:11.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:00:11.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:00:11.23#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:11.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:11.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:11.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:11.23#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:00:11.23#ibcon#first serial, iclass 17, count 0 2006.245.08:00:11.23#ibcon#enter sib2, iclass 17, count 0 2006.245.08:00:11.23#ibcon#flushed, iclass 17, count 0 2006.245.08:00:11.23#ibcon#about to write, iclass 17, count 0 2006.245.08:00:11.23#ibcon#wrote, iclass 17, count 0 2006.245.08:00:11.23#ibcon#about to read 3, iclass 17, count 0 2006.245.08:00:11.25#ibcon#read 3, iclass 17, count 0 2006.245.08:00:11.25#ibcon#about to read 4, iclass 17, count 0 2006.245.08:00:11.25#ibcon#read 4, iclass 17, count 0 2006.245.08:00:11.25#ibcon#about to read 5, iclass 17, count 0 2006.245.08:00:11.25#ibcon#read 5, iclass 17, count 0 2006.245.08:00:11.25#ibcon#about to read 6, iclass 17, count 0 2006.245.08:00:11.25#ibcon#read 6, iclass 17, count 0 2006.245.08:00:11.25#ibcon#end of sib2, iclass 17, count 0 2006.245.08:00:11.25#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:00:11.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:00:11.25#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:00:11.25#ibcon#*before write, iclass 17, count 0 2006.245.08:00:11.25#ibcon#enter sib2, iclass 17, count 0 2006.245.08:00:11.25#ibcon#flushed, iclass 17, count 0 2006.245.08:00:11.25#ibcon#about to write, iclass 17, count 0 2006.245.08:00:11.25#ibcon#wrote, iclass 17, count 0 2006.245.08:00:11.25#ibcon#about to read 3, iclass 17, count 0 2006.245.08:00:11.29#ibcon#read 3, iclass 17, count 0 2006.245.08:00:11.29#ibcon#about to read 4, iclass 17, count 0 2006.245.08:00:11.29#ibcon#read 4, iclass 17, count 0 2006.245.08:00:11.29#ibcon#about to read 5, iclass 17, count 0 2006.245.08:00:11.29#ibcon#read 5, iclass 17, count 0 2006.245.08:00:11.29#ibcon#about to read 6, iclass 17, count 0 2006.245.08:00:11.29#ibcon#read 6, iclass 17, count 0 2006.245.08:00:11.29#ibcon#end of sib2, iclass 17, count 0 2006.245.08:00:11.29#ibcon#*after write, iclass 17, count 0 2006.245.08:00:11.29#ibcon#*before return 0, iclass 17, count 0 2006.245.08:00:11.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:11.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:11.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:00:11.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:00:11.29$vc4f8/va=4,7 2006.245.08:00:11.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:00:11.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:00:11.29#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:11.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:11.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:11.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:11.35#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:00:11.35#ibcon#first serial, iclass 19, count 2 2006.245.08:00:11.35#ibcon#enter sib2, iclass 19, count 2 2006.245.08:00:11.35#ibcon#flushed, iclass 19, count 2 2006.245.08:00:11.35#ibcon#about to write, iclass 19, count 2 2006.245.08:00:11.35#ibcon#wrote, iclass 19, count 2 2006.245.08:00:11.35#ibcon#about to read 3, iclass 19, count 2 2006.245.08:00:11.37#ibcon#read 3, iclass 19, count 2 2006.245.08:00:11.37#ibcon#about to read 4, iclass 19, count 2 2006.245.08:00:11.37#ibcon#read 4, iclass 19, count 2 2006.245.08:00:11.37#ibcon#about to read 5, iclass 19, count 2 2006.245.08:00:11.37#ibcon#read 5, iclass 19, count 2 2006.245.08:00:11.37#ibcon#about to read 6, iclass 19, count 2 2006.245.08:00:11.37#ibcon#read 6, iclass 19, count 2 2006.245.08:00:11.37#ibcon#end of sib2, iclass 19, count 2 2006.245.08:00:11.37#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:00:11.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:00:11.37#ibcon#[25=AT04-07\r\n] 2006.245.08:00:11.37#ibcon#*before write, iclass 19, count 2 2006.245.08:00:11.37#ibcon#enter sib2, iclass 19, count 2 2006.245.08:00:11.37#ibcon#flushed, iclass 19, count 2 2006.245.08:00:11.37#ibcon#about to write, iclass 19, count 2 2006.245.08:00:11.37#ibcon#wrote, iclass 19, count 2 2006.245.08:00:11.37#ibcon#about to read 3, iclass 19, count 2 2006.245.08:00:11.40#ibcon#read 3, iclass 19, count 2 2006.245.08:00:11.40#ibcon#about to read 4, iclass 19, count 2 2006.245.08:00:11.40#ibcon#read 4, iclass 19, count 2 2006.245.08:00:11.40#ibcon#about to read 5, iclass 19, count 2 2006.245.08:00:11.40#ibcon#read 5, iclass 19, count 2 2006.245.08:00:11.40#ibcon#about to read 6, iclass 19, count 2 2006.245.08:00:11.40#ibcon#read 6, iclass 19, count 2 2006.245.08:00:11.40#ibcon#end of sib2, iclass 19, count 2 2006.245.08:00:11.40#ibcon#*after write, iclass 19, count 2 2006.245.08:00:11.40#ibcon#*before return 0, iclass 19, count 2 2006.245.08:00:11.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:11.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:11.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:00:11.40#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:11.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:11.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:11.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:11.52#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:00:11.52#ibcon#first serial, iclass 19, count 0 2006.245.08:00:11.52#ibcon#enter sib2, iclass 19, count 0 2006.245.08:00:11.52#ibcon#flushed, iclass 19, count 0 2006.245.08:00:11.52#ibcon#about to write, iclass 19, count 0 2006.245.08:00:11.52#ibcon#wrote, iclass 19, count 0 2006.245.08:00:11.52#ibcon#about to read 3, iclass 19, count 0 2006.245.08:00:11.54#ibcon#read 3, iclass 19, count 0 2006.245.08:00:11.54#ibcon#about to read 4, iclass 19, count 0 2006.245.08:00:11.54#ibcon#read 4, iclass 19, count 0 2006.245.08:00:11.54#ibcon#about to read 5, iclass 19, count 0 2006.245.08:00:11.54#ibcon#read 5, iclass 19, count 0 2006.245.08:00:11.54#ibcon#about to read 6, iclass 19, count 0 2006.245.08:00:11.54#ibcon#read 6, iclass 19, count 0 2006.245.08:00:11.54#ibcon#end of sib2, iclass 19, count 0 2006.245.08:00:11.54#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:00:11.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:00:11.54#ibcon#[25=USB\r\n] 2006.245.08:00:11.54#ibcon#*before write, iclass 19, count 0 2006.245.08:00:11.54#ibcon#enter sib2, iclass 19, count 0 2006.245.08:00:11.54#ibcon#flushed, iclass 19, count 0 2006.245.08:00:11.54#ibcon#about to write, iclass 19, count 0 2006.245.08:00:11.54#ibcon#wrote, iclass 19, count 0 2006.245.08:00:11.54#ibcon#about to read 3, iclass 19, count 0 2006.245.08:00:11.57#ibcon#read 3, iclass 19, count 0 2006.245.08:00:11.57#ibcon#about to read 4, iclass 19, count 0 2006.245.08:00:11.57#ibcon#read 4, iclass 19, count 0 2006.245.08:00:11.57#ibcon#about to read 5, iclass 19, count 0 2006.245.08:00:11.57#ibcon#read 5, iclass 19, count 0 2006.245.08:00:11.57#ibcon#about to read 6, iclass 19, count 0 2006.245.08:00:11.57#ibcon#read 6, iclass 19, count 0 2006.245.08:00:11.57#ibcon#end of sib2, iclass 19, count 0 2006.245.08:00:11.57#ibcon#*after write, iclass 19, count 0 2006.245.08:00:11.57#ibcon#*before return 0, iclass 19, count 0 2006.245.08:00:11.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:11.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:11.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:00:11.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:00:11.57$vc4f8/valo=5,652.99 2006.245.08:00:11.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:00:11.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:00:11.57#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:11.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:11.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:11.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:11.57#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:00:11.57#ibcon#first serial, iclass 21, count 0 2006.245.08:00:11.57#ibcon#enter sib2, iclass 21, count 0 2006.245.08:00:11.57#ibcon#flushed, iclass 21, count 0 2006.245.08:00:11.57#ibcon#about to write, iclass 21, count 0 2006.245.08:00:11.57#ibcon#wrote, iclass 21, count 0 2006.245.08:00:11.57#ibcon#about to read 3, iclass 21, count 0 2006.245.08:00:11.59#ibcon#read 3, iclass 21, count 0 2006.245.08:00:11.59#ibcon#about to read 4, iclass 21, count 0 2006.245.08:00:11.59#ibcon#read 4, iclass 21, count 0 2006.245.08:00:11.59#ibcon#about to read 5, iclass 21, count 0 2006.245.08:00:11.59#ibcon#read 5, iclass 21, count 0 2006.245.08:00:11.59#ibcon#about to read 6, iclass 21, count 0 2006.245.08:00:11.59#ibcon#read 6, iclass 21, count 0 2006.245.08:00:11.59#ibcon#end of sib2, iclass 21, count 0 2006.245.08:00:11.59#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:00:11.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:00:11.59#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:00:11.59#ibcon#*before write, iclass 21, count 0 2006.245.08:00:11.59#ibcon#enter sib2, iclass 21, count 0 2006.245.08:00:11.59#ibcon#flushed, iclass 21, count 0 2006.245.08:00:11.59#ibcon#about to write, iclass 21, count 0 2006.245.08:00:11.59#ibcon#wrote, iclass 21, count 0 2006.245.08:00:11.59#ibcon#about to read 3, iclass 21, count 0 2006.245.08:00:11.63#ibcon#read 3, iclass 21, count 0 2006.245.08:00:11.63#ibcon#about to read 4, iclass 21, count 0 2006.245.08:00:11.63#ibcon#read 4, iclass 21, count 0 2006.245.08:00:11.63#ibcon#about to read 5, iclass 21, count 0 2006.245.08:00:11.63#ibcon#read 5, iclass 21, count 0 2006.245.08:00:11.63#ibcon#about to read 6, iclass 21, count 0 2006.245.08:00:11.63#ibcon#read 6, iclass 21, count 0 2006.245.08:00:11.63#ibcon#end of sib2, iclass 21, count 0 2006.245.08:00:11.63#ibcon#*after write, iclass 21, count 0 2006.245.08:00:11.63#ibcon#*before return 0, iclass 21, count 0 2006.245.08:00:11.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:11.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:11.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:00:11.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:00:11.63$vc4f8/va=5,7 2006.245.08:00:11.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.08:00:11.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.08:00:11.63#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:11.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:11.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:11.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:11.69#ibcon#enter wrdev, iclass 23, count 2 2006.245.08:00:11.69#ibcon#first serial, iclass 23, count 2 2006.245.08:00:11.69#ibcon#enter sib2, iclass 23, count 2 2006.245.08:00:11.69#ibcon#flushed, iclass 23, count 2 2006.245.08:00:11.69#ibcon#about to write, iclass 23, count 2 2006.245.08:00:11.69#ibcon#wrote, iclass 23, count 2 2006.245.08:00:11.69#ibcon#about to read 3, iclass 23, count 2 2006.245.08:00:11.71#ibcon#read 3, iclass 23, count 2 2006.245.08:00:11.71#ibcon#about to read 4, iclass 23, count 2 2006.245.08:00:11.71#ibcon#read 4, iclass 23, count 2 2006.245.08:00:11.71#ibcon#about to read 5, iclass 23, count 2 2006.245.08:00:11.71#ibcon#read 5, iclass 23, count 2 2006.245.08:00:11.71#ibcon#about to read 6, iclass 23, count 2 2006.245.08:00:11.71#ibcon#read 6, iclass 23, count 2 2006.245.08:00:11.71#ibcon#end of sib2, iclass 23, count 2 2006.245.08:00:11.71#ibcon#*mode == 0, iclass 23, count 2 2006.245.08:00:11.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.08:00:11.71#ibcon#[25=AT05-07\r\n] 2006.245.08:00:11.71#ibcon#*before write, iclass 23, count 2 2006.245.08:00:11.71#ibcon#enter sib2, iclass 23, count 2 2006.245.08:00:11.71#ibcon#flushed, iclass 23, count 2 2006.245.08:00:11.71#ibcon#about to write, iclass 23, count 2 2006.245.08:00:11.71#ibcon#wrote, iclass 23, count 2 2006.245.08:00:11.71#ibcon#about to read 3, iclass 23, count 2 2006.245.08:00:11.74#ibcon#read 3, iclass 23, count 2 2006.245.08:00:11.74#ibcon#about to read 4, iclass 23, count 2 2006.245.08:00:11.74#ibcon#read 4, iclass 23, count 2 2006.245.08:00:11.74#ibcon#about to read 5, iclass 23, count 2 2006.245.08:00:11.74#ibcon#read 5, iclass 23, count 2 2006.245.08:00:11.74#ibcon#about to read 6, iclass 23, count 2 2006.245.08:00:11.74#ibcon#read 6, iclass 23, count 2 2006.245.08:00:11.74#ibcon#end of sib2, iclass 23, count 2 2006.245.08:00:11.74#ibcon#*after write, iclass 23, count 2 2006.245.08:00:11.74#ibcon#*before return 0, iclass 23, count 2 2006.245.08:00:11.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:11.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:11.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.08:00:11.74#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:11.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:11.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:11.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:11.86#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:00:11.86#ibcon#first serial, iclass 23, count 0 2006.245.08:00:11.86#ibcon#enter sib2, iclass 23, count 0 2006.245.08:00:11.86#ibcon#flushed, iclass 23, count 0 2006.245.08:00:11.86#ibcon#about to write, iclass 23, count 0 2006.245.08:00:11.86#ibcon#wrote, iclass 23, count 0 2006.245.08:00:11.86#ibcon#about to read 3, iclass 23, count 0 2006.245.08:00:11.88#ibcon#read 3, iclass 23, count 0 2006.245.08:00:11.88#ibcon#about to read 4, iclass 23, count 0 2006.245.08:00:11.88#ibcon#read 4, iclass 23, count 0 2006.245.08:00:11.88#ibcon#about to read 5, iclass 23, count 0 2006.245.08:00:11.88#ibcon#read 5, iclass 23, count 0 2006.245.08:00:11.88#ibcon#about to read 6, iclass 23, count 0 2006.245.08:00:11.88#ibcon#read 6, iclass 23, count 0 2006.245.08:00:11.88#ibcon#end of sib2, iclass 23, count 0 2006.245.08:00:11.88#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:00:11.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:00:11.88#ibcon#[25=USB\r\n] 2006.245.08:00:11.88#ibcon#*before write, iclass 23, count 0 2006.245.08:00:11.88#ibcon#enter sib2, iclass 23, count 0 2006.245.08:00:11.88#ibcon#flushed, iclass 23, count 0 2006.245.08:00:11.88#ibcon#about to write, iclass 23, count 0 2006.245.08:00:11.88#ibcon#wrote, iclass 23, count 0 2006.245.08:00:11.88#ibcon#about to read 3, iclass 23, count 0 2006.245.08:00:11.91#ibcon#read 3, iclass 23, count 0 2006.245.08:00:11.91#ibcon#about to read 4, iclass 23, count 0 2006.245.08:00:11.91#ibcon#read 4, iclass 23, count 0 2006.245.08:00:11.91#ibcon#about to read 5, iclass 23, count 0 2006.245.08:00:11.91#ibcon#read 5, iclass 23, count 0 2006.245.08:00:11.91#ibcon#about to read 6, iclass 23, count 0 2006.245.08:00:11.91#ibcon#read 6, iclass 23, count 0 2006.245.08:00:11.91#ibcon#end of sib2, iclass 23, count 0 2006.245.08:00:11.91#ibcon#*after write, iclass 23, count 0 2006.245.08:00:11.91#ibcon#*before return 0, iclass 23, count 0 2006.245.08:00:11.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:11.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:11.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:00:11.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:00:11.91$vc4f8/valo=6,772.99 2006.245.08:00:11.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.08:00:11.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.08:00:11.91#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:11.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:11.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:11.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:11.91#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:00:11.91#ibcon#first serial, iclass 25, count 0 2006.245.08:00:11.91#ibcon#enter sib2, iclass 25, count 0 2006.245.08:00:11.91#ibcon#flushed, iclass 25, count 0 2006.245.08:00:11.91#ibcon#about to write, iclass 25, count 0 2006.245.08:00:11.91#ibcon#wrote, iclass 25, count 0 2006.245.08:00:11.91#ibcon#about to read 3, iclass 25, count 0 2006.245.08:00:11.94#ibcon#read 3, iclass 25, count 0 2006.245.08:00:11.94#ibcon#about to read 4, iclass 25, count 0 2006.245.08:00:11.94#ibcon#read 4, iclass 25, count 0 2006.245.08:00:11.94#ibcon#about to read 5, iclass 25, count 0 2006.245.08:00:11.94#ibcon#read 5, iclass 25, count 0 2006.245.08:00:11.94#ibcon#about to read 6, iclass 25, count 0 2006.245.08:00:11.94#ibcon#read 6, iclass 25, count 0 2006.245.08:00:11.94#ibcon#end of sib2, iclass 25, count 0 2006.245.08:00:11.94#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:00:11.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:00:11.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:00:11.94#ibcon#*before write, iclass 25, count 0 2006.245.08:00:11.94#ibcon#enter sib2, iclass 25, count 0 2006.245.08:00:11.94#ibcon#flushed, iclass 25, count 0 2006.245.08:00:11.94#ibcon#about to write, iclass 25, count 0 2006.245.08:00:11.94#ibcon#wrote, iclass 25, count 0 2006.245.08:00:11.94#ibcon#about to read 3, iclass 25, count 0 2006.245.08:00:11.98#ibcon#read 3, iclass 25, count 0 2006.245.08:00:11.98#ibcon#about to read 4, iclass 25, count 0 2006.245.08:00:11.98#ibcon#read 4, iclass 25, count 0 2006.245.08:00:11.98#ibcon#about to read 5, iclass 25, count 0 2006.245.08:00:11.98#ibcon#read 5, iclass 25, count 0 2006.245.08:00:11.98#ibcon#about to read 6, iclass 25, count 0 2006.245.08:00:11.98#ibcon#read 6, iclass 25, count 0 2006.245.08:00:11.98#ibcon#end of sib2, iclass 25, count 0 2006.245.08:00:11.98#ibcon#*after write, iclass 25, count 0 2006.245.08:00:11.98#ibcon#*before return 0, iclass 25, count 0 2006.245.08:00:11.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:11.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:11.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:00:11.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:00:11.98$vc4f8/va=6,7 2006.245.08:00:11.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.08:00:11.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.08:00:11.98#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:11.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:00:12.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:00:12.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:00:12.04#ibcon#enter wrdev, iclass 27, count 2 2006.245.08:00:12.04#ibcon#first serial, iclass 27, count 2 2006.245.08:00:12.04#ibcon#enter sib2, iclass 27, count 2 2006.245.08:00:12.04#ibcon#flushed, iclass 27, count 2 2006.245.08:00:12.04#ibcon#about to write, iclass 27, count 2 2006.245.08:00:12.04#ibcon#wrote, iclass 27, count 2 2006.245.08:00:12.04#ibcon#about to read 3, iclass 27, count 2 2006.245.08:00:12.05#ibcon#read 3, iclass 27, count 2 2006.245.08:00:12.05#ibcon#about to read 4, iclass 27, count 2 2006.245.08:00:12.05#ibcon#read 4, iclass 27, count 2 2006.245.08:00:12.05#ibcon#about to read 5, iclass 27, count 2 2006.245.08:00:12.05#ibcon#read 5, iclass 27, count 2 2006.245.08:00:12.05#ibcon#about to read 6, iclass 27, count 2 2006.245.08:00:12.05#ibcon#read 6, iclass 27, count 2 2006.245.08:00:12.05#ibcon#end of sib2, iclass 27, count 2 2006.245.08:00:12.05#ibcon#*mode == 0, iclass 27, count 2 2006.245.08:00:12.05#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.08:00:12.05#ibcon#[25=AT06-07\r\n] 2006.245.08:00:12.05#ibcon#*before write, iclass 27, count 2 2006.245.08:00:12.05#ibcon#enter sib2, iclass 27, count 2 2006.245.08:00:12.05#ibcon#flushed, iclass 27, count 2 2006.245.08:00:12.05#ibcon#about to write, iclass 27, count 2 2006.245.08:00:12.05#ibcon#wrote, iclass 27, count 2 2006.245.08:00:12.05#ibcon#about to read 3, iclass 27, count 2 2006.245.08:00:12.08#ibcon#read 3, iclass 27, count 2 2006.245.08:00:12.08#ibcon#about to read 4, iclass 27, count 2 2006.245.08:00:12.08#ibcon#read 4, iclass 27, count 2 2006.245.08:00:12.08#ibcon#about to read 5, iclass 27, count 2 2006.245.08:00:12.08#ibcon#read 5, iclass 27, count 2 2006.245.08:00:12.08#ibcon#about to read 6, iclass 27, count 2 2006.245.08:00:12.08#ibcon#read 6, iclass 27, count 2 2006.245.08:00:12.08#ibcon#end of sib2, iclass 27, count 2 2006.245.08:00:12.08#ibcon#*after write, iclass 27, count 2 2006.245.08:00:12.08#ibcon#*before return 0, iclass 27, count 2 2006.245.08:00:12.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:00:12.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:00:12.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.08:00:12.08#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:12.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:00:12.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:00:12.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:00:12.20#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:00:12.20#ibcon#first serial, iclass 27, count 0 2006.245.08:00:12.20#ibcon#enter sib2, iclass 27, count 0 2006.245.08:00:12.20#ibcon#flushed, iclass 27, count 0 2006.245.08:00:12.20#ibcon#about to write, iclass 27, count 0 2006.245.08:00:12.20#ibcon#wrote, iclass 27, count 0 2006.245.08:00:12.20#ibcon#about to read 3, iclass 27, count 0 2006.245.08:00:12.22#ibcon#read 3, iclass 27, count 0 2006.245.08:00:12.22#ibcon#about to read 4, iclass 27, count 0 2006.245.08:00:12.22#ibcon#read 4, iclass 27, count 0 2006.245.08:00:12.22#ibcon#about to read 5, iclass 27, count 0 2006.245.08:00:12.22#ibcon#read 5, iclass 27, count 0 2006.245.08:00:12.22#ibcon#about to read 6, iclass 27, count 0 2006.245.08:00:12.22#ibcon#read 6, iclass 27, count 0 2006.245.08:00:12.22#ibcon#end of sib2, iclass 27, count 0 2006.245.08:00:12.22#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:00:12.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:00:12.22#ibcon#[25=USB\r\n] 2006.245.08:00:12.22#ibcon#*before write, iclass 27, count 0 2006.245.08:00:12.22#ibcon#enter sib2, iclass 27, count 0 2006.245.08:00:12.22#ibcon#flushed, iclass 27, count 0 2006.245.08:00:12.22#ibcon#about to write, iclass 27, count 0 2006.245.08:00:12.22#ibcon#wrote, iclass 27, count 0 2006.245.08:00:12.22#ibcon#about to read 3, iclass 27, count 0 2006.245.08:00:12.25#ibcon#read 3, iclass 27, count 0 2006.245.08:00:12.25#ibcon#about to read 4, iclass 27, count 0 2006.245.08:00:12.25#ibcon#read 4, iclass 27, count 0 2006.245.08:00:12.25#ibcon#about to read 5, iclass 27, count 0 2006.245.08:00:12.25#ibcon#read 5, iclass 27, count 0 2006.245.08:00:12.25#ibcon#about to read 6, iclass 27, count 0 2006.245.08:00:12.25#ibcon#read 6, iclass 27, count 0 2006.245.08:00:12.25#ibcon#end of sib2, iclass 27, count 0 2006.245.08:00:12.25#ibcon#*after write, iclass 27, count 0 2006.245.08:00:12.25#ibcon#*before return 0, iclass 27, count 0 2006.245.08:00:12.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:00:12.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:00:12.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:00:12.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:00:12.25$vc4f8/valo=7,832.99 2006.245.08:00:12.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.08:00:12.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.08:00:12.25#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:12.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:00:12.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:00:12.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:00:12.25#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:00:12.25#ibcon#first serial, iclass 29, count 0 2006.245.08:00:12.25#ibcon#enter sib2, iclass 29, count 0 2006.245.08:00:12.25#ibcon#flushed, iclass 29, count 0 2006.245.08:00:12.25#ibcon#about to write, iclass 29, count 0 2006.245.08:00:12.25#ibcon#wrote, iclass 29, count 0 2006.245.08:00:12.25#ibcon#about to read 3, iclass 29, count 0 2006.245.08:00:12.27#ibcon#read 3, iclass 29, count 0 2006.245.08:00:12.27#ibcon#about to read 4, iclass 29, count 0 2006.245.08:00:12.27#ibcon#read 4, iclass 29, count 0 2006.245.08:00:12.27#ibcon#about to read 5, iclass 29, count 0 2006.245.08:00:12.27#ibcon#read 5, iclass 29, count 0 2006.245.08:00:12.27#ibcon#about to read 6, iclass 29, count 0 2006.245.08:00:12.27#ibcon#read 6, iclass 29, count 0 2006.245.08:00:12.27#ibcon#end of sib2, iclass 29, count 0 2006.245.08:00:12.27#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:00:12.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:00:12.27#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:00:12.27#ibcon#*before write, iclass 29, count 0 2006.245.08:00:12.27#ibcon#enter sib2, iclass 29, count 0 2006.245.08:00:12.27#ibcon#flushed, iclass 29, count 0 2006.245.08:00:12.27#ibcon#about to write, iclass 29, count 0 2006.245.08:00:12.27#ibcon#wrote, iclass 29, count 0 2006.245.08:00:12.27#ibcon#about to read 3, iclass 29, count 0 2006.245.08:00:12.31#ibcon#read 3, iclass 29, count 0 2006.245.08:00:12.31#ibcon#about to read 4, iclass 29, count 0 2006.245.08:00:12.31#ibcon#read 4, iclass 29, count 0 2006.245.08:00:12.31#ibcon#about to read 5, iclass 29, count 0 2006.245.08:00:12.31#ibcon#read 5, iclass 29, count 0 2006.245.08:00:12.31#ibcon#about to read 6, iclass 29, count 0 2006.245.08:00:12.31#ibcon#read 6, iclass 29, count 0 2006.245.08:00:12.31#ibcon#end of sib2, iclass 29, count 0 2006.245.08:00:12.31#ibcon#*after write, iclass 29, count 0 2006.245.08:00:12.31#ibcon#*before return 0, iclass 29, count 0 2006.245.08:00:12.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:00:12.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:00:12.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:00:12.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:00:12.31$vc4f8/va=7,7 2006.245.08:00:12.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.08:00:12.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.08:00:12.31#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:12.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:00:12.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:00:12.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:00:12.37#ibcon#enter wrdev, iclass 31, count 2 2006.245.08:00:12.37#ibcon#first serial, iclass 31, count 2 2006.245.08:00:12.37#ibcon#enter sib2, iclass 31, count 2 2006.245.08:00:12.37#ibcon#flushed, iclass 31, count 2 2006.245.08:00:12.37#ibcon#about to write, iclass 31, count 2 2006.245.08:00:12.37#ibcon#wrote, iclass 31, count 2 2006.245.08:00:12.37#ibcon#about to read 3, iclass 31, count 2 2006.245.08:00:12.39#ibcon#read 3, iclass 31, count 2 2006.245.08:00:12.39#ibcon#about to read 4, iclass 31, count 2 2006.245.08:00:12.39#ibcon#read 4, iclass 31, count 2 2006.245.08:00:12.39#ibcon#about to read 5, iclass 31, count 2 2006.245.08:00:12.39#ibcon#read 5, iclass 31, count 2 2006.245.08:00:12.39#ibcon#about to read 6, iclass 31, count 2 2006.245.08:00:12.39#ibcon#read 6, iclass 31, count 2 2006.245.08:00:12.39#ibcon#end of sib2, iclass 31, count 2 2006.245.08:00:12.39#ibcon#*mode == 0, iclass 31, count 2 2006.245.08:00:12.39#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.08:00:12.39#ibcon#[25=AT07-07\r\n] 2006.245.08:00:12.39#ibcon#*before write, iclass 31, count 2 2006.245.08:00:12.39#ibcon#enter sib2, iclass 31, count 2 2006.245.08:00:12.39#ibcon#flushed, iclass 31, count 2 2006.245.08:00:12.39#ibcon#about to write, iclass 31, count 2 2006.245.08:00:12.39#ibcon#wrote, iclass 31, count 2 2006.245.08:00:12.39#ibcon#about to read 3, iclass 31, count 2 2006.245.08:00:12.42#ibcon#read 3, iclass 31, count 2 2006.245.08:00:12.42#ibcon#about to read 4, iclass 31, count 2 2006.245.08:00:12.42#ibcon#read 4, iclass 31, count 2 2006.245.08:00:12.42#ibcon#about to read 5, iclass 31, count 2 2006.245.08:00:12.42#ibcon#read 5, iclass 31, count 2 2006.245.08:00:12.42#ibcon#about to read 6, iclass 31, count 2 2006.245.08:00:12.42#ibcon#read 6, iclass 31, count 2 2006.245.08:00:12.42#ibcon#end of sib2, iclass 31, count 2 2006.245.08:00:12.42#ibcon#*after write, iclass 31, count 2 2006.245.08:00:12.42#ibcon#*before return 0, iclass 31, count 2 2006.245.08:00:12.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:00:12.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:00:12.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.08:00:12.42#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:12.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:00:12.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:00:12.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:00:12.54#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:00:12.54#ibcon#first serial, iclass 31, count 0 2006.245.08:00:12.54#ibcon#enter sib2, iclass 31, count 0 2006.245.08:00:12.54#ibcon#flushed, iclass 31, count 0 2006.245.08:00:12.54#ibcon#about to write, iclass 31, count 0 2006.245.08:00:12.54#ibcon#wrote, iclass 31, count 0 2006.245.08:00:12.54#ibcon#about to read 3, iclass 31, count 0 2006.245.08:00:12.56#ibcon#read 3, iclass 31, count 0 2006.245.08:00:12.56#ibcon#about to read 4, iclass 31, count 0 2006.245.08:00:12.56#ibcon#read 4, iclass 31, count 0 2006.245.08:00:12.56#ibcon#about to read 5, iclass 31, count 0 2006.245.08:00:12.56#ibcon#read 5, iclass 31, count 0 2006.245.08:00:12.56#ibcon#about to read 6, iclass 31, count 0 2006.245.08:00:12.56#ibcon#read 6, iclass 31, count 0 2006.245.08:00:12.56#ibcon#end of sib2, iclass 31, count 0 2006.245.08:00:12.56#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:00:12.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:00:12.56#ibcon#[25=USB\r\n] 2006.245.08:00:12.56#ibcon#*before write, iclass 31, count 0 2006.245.08:00:12.56#ibcon#enter sib2, iclass 31, count 0 2006.245.08:00:12.56#ibcon#flushed, iclass 31, count 0 2006.245.08:00:12.56#ibcon#about to write, iclass 31, count 0 2006.245.08:00:12.56#ibcon#wrote, iclass 31, count 0 2006.245.08:00:12.56#ibcon#about to read 3, iclass 31, count 0 2006.245.08:00:12.59#ibcon#read 3, iclass 31, count 0 2006.245.08:00:12.59#ibcon#about to read 4, iclass 31, count 0 2006.245.08:00:12.59#ibcon#read 4, iclass 31, count 0 2006.245.08:00:12.59#ibcon#about to read 5, iclass 31, count 0 2006.245.08:00:12.59#ibcon#read 5, iclass 31, count 0 2006.245.08:00:12.59#ibcon#about to read 6, iclass 31, count 0 2006.245.08:00:12.59#ibcon#read 6, iclass 31, count 0 2006.245.08:00:12.59#ibcon#end of sib2, iclass 31, count 0 2006.245.08:00:12.59#ibcon#*after write, iclass 31, count 0 2006.245.08:00:12.59#ibcon#*before return 0, iclass 31, count 0 2006.245.08:00:12.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:00:12.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:00:12.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:00:12.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:00:12.59$vc4f8/valo=8,852.99 2006.245.08:00:12.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:00:12.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:00:12.59#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:12.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:00:12.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:00:12.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:00:12.59#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:00:12.59#ibcon#first serial, iclass 33, count 0 2006.245.08:00:12.59#ibcon#enter sib2, iclass 33, count 0 2006.245.08:00:12.59#ibcon#flushed, iclass 33, count 0 2006.245.08:00:12.59#ibcon#about to write, iclass 33, count 0 2006.245.08:00:12.59#ibcon#wrote, iclass 33, count 0 2006.245.08:00:12.59#ibcon#about to read 3, iclass 33, count 0 2006.245.08:00:12.61#ibcon#read 3, iclass 33, count 0 2006.245.08:00:12.61#ibcon#about to read 4, iclass 33, count 0 2006.245.08:00:12.61#ibcon#read 4, iclass 33, count 0 2006.245.08:00:12.61#ibcon#about to read 5, iclass 33, count 0 2006.245.08:00:12.61#ibcon#read 5, iclass 33, count 0 2006.245.08:00:12.61#ibcon#about to read 6, iclass 33, count 0 2006.245.08:00:12.61#ibcon#read 6, iclass 33, count 0 2006.245.08:00:12.61#ibcon#end of sib2, iclass 33, count 0 2006.245.08:00:12.61#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:00:12.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:00:12.61#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:00:12.61#ibcon#*before write, iclass 33, count 0 2006.245.08:00:12.61#ibcon#enter sib2, iclass 33, count 0 2006.245.08:00:12.61#ibcon#flushed, iclass 33, count 0 2006.245.08:00:12.61#ibcon#about to write, iclass 33, count 0 2006.245.08:00:12.61#ibcon#wrote, iclass 33, count 0 2006.245.08:00:12.61#ibcon#about to read 3, iclass 33, count 0 2006.245.08:00:12.65#ibcon#read 3, iclass 33, count 0 2006.245.08:00:12.65#ibcon#about to read 4, iclass 33, count 0 2006.245.08:00:12.65#ibcon#read 4, iclass 33, count 0 2006.245.08:00:12.65#ibcon#about to read 5, iclass 33, count 0 2006.245.08:00:12.65#ibcon#read 5, iclass 33, count 0 2006.245.08:00:12.65#ibcon#about to read 6, iclass 33, count 0 2006.245.08:00:12.65#ibcon#read 6, iclass 33, count 0 2006.245.08:00:12.65#ibcon#end of sib2, iclass 33, count 0 2006.245.08:00:12.65#ibcon#*after write, iclass 33, count 0 2006.245.08:00:12.65#ibcon#*before return 0, iclass 33, count 0 2006.245.08:00:12.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:00:12.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:00:12.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:00:12.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:00:12.65$vc4f8/va=8,8 2006.245.08:00:12.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.08:00:12.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.08:00:12.65#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:12.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:00:12.71#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:00:12.71#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:00:12.71#ibcon#enter wrdev, iclass 35, count 2 2006.245.08:00:12.71#ibcon#first serial, iclass 35, count 2 2006.245.08:00:12.71#ibcon#enter sib2, iclass 35, count 2 2006.245.08:00:12.71#ibcon#flushed, iclass 35, count 2 2006.245.08:00:12.71#ibcon#about to write, iclass 35, count 2 2006.245.08:00:12.71#ibcon#wrote, iclass 35, count 2 2006.245.08:00:12.71#ibcon#about to read 3, iclass 35, count 2 2006.245.08:00:12.73#ibcon#read 3, iclass 35, count 2 2006.245.08:00:12.73#ibcon#about to read 4, iclass 35, count 2 2006.245.08:00:12.73#ibcon#read 4, iclass 35, count 2 2006.245.08:00:12.73#ibcon#about to read 5, iclass 35, count 2 2006.245.08:00:12.73#ibcon#read 5, iclass 35, count 2 2006.245.08:00:12.73#ibcon#about to read 6, iclass 35, count 2 2006.245.08:00:12.73#ibcon#read 6, iclass 35, count 2 2006.245.08:00:12.73#ibcon#end of sib2, iclass 35, count 2 2006.245.08:00:12.73#ibcon#*mode == 0, iclass 35, count 2 2006.245.08:00:12.73#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.08:00:12.73#ibcon#[25=AT08-08\r\n] 2006.245.08:00:12.73#ibcon#*before write, iclass 35, count 2 2006.245.08:00:12.73#ibcon#enter sib2, iclass 35, count 2 2006.245.08:00:12.73#ibcon#flushed, iclass 35, count 2 2006.245.08:00:12.73#ibcon#about to write, iclass 35, count 2 2006.245.08:00:12.73#ibcon#wrote, iclass 35, count 2 2006.245.08:00:12.73#ibcon#about to read 3, iclass 35, count 2 2006.245.08:00:12.76#ibcon#read 3, iclass 35, count 2 2006.245.08:00:12.76#ibcon#about to read 4, iclass 35, count 2 2006.245.08:00:12.76#ibcon#read 4, iclass 35, count 2 2006.245.08:00:12.76#ibcon#about to read 5, iclass 35, count 2 2006.245.08:00:12.76#ibcon#read 5, iclass 35, count 2 2006.245.08:00:12.76#ibcon#about to read 6, iclass 35, count 2 2006.245.08:00:12.76#ibcon#read 6, iclass 35, count 2 2006.245.08:00:12.76#ibcon#end of sib2, iclass 35, count 2 2006.245.08:00:12.76#ibcon#*after write, iclass 35, count 2 2006.245.08:00:12.76#ibcon#*before return 0, iclass 35, count 2 2006.245.08:00:12.76#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:00:12.76#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:00:12.76#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.08:00:12.76#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:12.76#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:00:12.88#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:00:12.88#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:00:12.88#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:00:12.88#ibcon#first serial, iclass 35, count 0 2006.245.08:00:12.88#ibcon#enter sib2, iclass 35, count 0 2006.245.08:00:12.88#ibcon#flushed, iclass 35, count 0 2006.245.08:00:12.88#ibcon#about to write, iclass 35, count 0 2006.245.08:00:12.88#ibcon#wrote, iclass 35, count 0 2006.245.08:00:12.88#ibcon#about to read 3, iclass 35, count 0 2006.245.08:00:12.90#ibcon#read 3, iclass 35, count 0 2006.245.08:00:12.90#ibcon#about to read 4, iclass 35, count 0 2006.245.08:00:12.90#ibcon#read 4, iclass 35, count 0 2006.245.08:00:12.90#ibcon#about to read 5, iclass 35, count 0 2006.245.08:00:12.90#ibcon#read 5, iclass 35, count 0 2006.245.08:00:12.90#ibcon#about to read 6, iclass 35, count 0 2006.245.08:00:12.90#ibcon#read 6, iclass 35, count 0 2006.245.08:00:12.90#ibcon#end of sib2, iclass 35, count 0 2006.245.08:00:12.90#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:00:12.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:00:12.90#ibcon#[25=USB\r\n] 2006.245.08:00:12.90#ibcon#*before write, iclass 35, count 0 2006.245.08:00:12.90#ibcon#enter sib2, iclass 35, count 0 2006.245.08:00:12.90#ibcon#flushed, iclass 35, count 0 2006.245.08:00:12.90#ibcon#about to write, iclass 35, count 0 2006.245.08:00:12.90#ibcon#wrote, iclass 35, count 0 2006.245.08:00:12.90#ibcon#about to read 3, iclass 35, count 0 2006.245.08:00:12.93#ibcon#read 3, iclass 35, count 0 2006.245.08:00:12.93#ibcon#about to read 4, iclass 35, count 0 2006.245.08:00:12.93#ibcon#read 4, iclass 35, count 0 2006.245.08:00:12.93#ibcon#about to read 5, iclass 35, count 0 2006.245.08:00:12.93#ibcon#read 5, iclass 35, count 0 2006.245.08:00:12.93#ibcon#about to read 6, iclass 35, count 0 2006.245.08:00:12.93#ibcon#read 6, iclass 35, count 0 2006.245.08:00:12.93#ibcon#end of sib2, iclass 35, count 0 2006.245.08:00:12.93#ibcon#*after write, iclass 35, count 0 2006.245.08:00:12.93#ibcon#*before return 0, iclass 35, count 0 2006.245.08:00:12.93#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:00:12.93#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:00:12.93#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:00:12.93#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:00:12.93$vc4f8/vblo=1,632.99 2006.245.08:00:12.93#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.08:00:12.93#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.08:00:12.93#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:12.93#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:00:12.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:00:12.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:00:12.93#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:00:12.93#ibcon#first serial, iclass 37, count 0 2006.245.08:00:12.93#ibcon#enter sib2, iclass 37, count 0 2006.245.08:00:12.93#ibcon#flushed, iclass 37, count 0 2006.245.08:00:12.93#ibcon#about to write, iclass 37, count 0 2006.245.08:00:12.93#ibcon#wrote, iclass 37, count 0 2006.245.08:00:12.93#ibcon#about to read 3, iclass 37, count 0 2006.245.08:00:12.95#ibcon#read 3, iclass 37, count 0 2006.245.08:00:12.95#ibcon#about to read 4, iclass 37, count 0 2006.245.08:00:12.95#ibcon#read 4, iclass 37, count 0 2006.245.08:00:12.95#ibcon#about to read 5, iclass 37, count 0 2006.245.08:00:12.95#ibcon#read 5, iclass 37, count 0 2006.245.08:00:12.95#ibcon#about to read 6, iclass 37, count 0 2006.245.08:00:12.95#ibcon#read 6, iclass 37, count 0 2006.245.08:00:12.95#ibcon#end of sib2, iclass 37, count 0 2006.245.08:00:12.95#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:00:12.95#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:00:12.95#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:00:12.95#ibcon#*before write, iclass 37, count 0 2006.245.08:00:12.95#ibcon#enter sib2, iclass 37, count 0 2006.245.08:00:12.95#ibcon#flushed, iclass 37, count 0 2006.245.08:00:12.95#ibcon#about to write, iclass 37, count 0 2006.245.08:00:12.95#ibcon#wrote, iclass 37, count 0 2006.245.08:00:12.95#ibcon#about to read 3, iclass 37, count 0 2006.245.08:00:12.99#ibcon#read 3, iclass 37, count 0 2006.245.08:00:12.99#ibcon#about to read 4, iclass 37, count 0 2006.245.08:00:12.99#ibcon#read 4, iclass 37, count 0 2006.245.08:00:12.99#ibcon#about to read 5, iclass 37, count 0 2006.245.08:00:12.99#ibcon#read 5, iclass 37, count 0 2006.245.08:00:12.99#ibcon#about to read 6, iclass 37, count 0 2006.245.08:00:12.99#ibcon#read 6, iclass 37, count 0 2006.245.08:00:12.99#ibcon#end of sib2, iclass 37, count 0 2006.245.08:00:12.99#ibcon#*after write, iclass 37, count 0 2006.245.08:00:12.99#ibcon#*before return 0, iclass 37, count 0 2006.245.08:00:12.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:00:12.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:00:12.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:00:12.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:00:12.99$vc4f8/vb=1,4 2006.245.08:00:12.99#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.08:00:12.99#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.08:00:12.99#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:12.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:00:12.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:00:12.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:00:12.99#ibcon#enter wrdev, iclass 39, count 2 2006.245.08:00:12.99#ibcon#first serial, iclass 39, count 2 2006.245.08:00:12.99#ibcon#enter sib2, iclass 39, count 2 2006.245.08:00:12.99#ibcon#flushed, iclass 39, count 2 2006.245.08:00:12.99#ibcon#about to write, iclass 39, count 2 2006.245.08:00:12.99#ibcon#wrote, iclass 39, count 2 2006.245.08:00:12.99#ibcon#about to read 3, iclass 39, count 2 2006.245.08:00:13.01#ibcon#read 3, iclass 39, count 2 2006.245.08:00:13.01#ibcon#about to read 4, iclass 39, count 2 2006.245.08:00:13.01#ibcon#read 4, iclass 39, count 2 2006.245.08:00:13.01#ibcon#about to read 5, iclass 39, count 2 2006.245.08:00:13.01#ibcon#read 5, iclass 39, count 2 2006.245.08:00:13.01#ibcon#about to read 6, iclass 39, count 2 2006.245.08:00:13.01#ibcon#read 6, iclass 39, count 2 2006.245.08:00:13.01#ibcon#end of sib2, iclass 39, count 2 2006.245.08:00:13.01#ibcon#*mode == 0, iclass 39, count 2 2006.245.08:00:13.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.08:00:13.01#ibcon#[27=AT01-04\r\n] 2006.245.08:00:13.01#ibcon#*before write, iclass 39, count 2 2006.245.08:00:13.01#ibcon#enter sib2, iclass 39, count 2 2006.245.08:00:13.01#ibcon#flushed, iclass 39, count 2 2006.245.08:00:13.01#ibcon#about to write, iclass 39, count 2 2006.245.08:00:13.01#ibcon#wrote, iclass 39, count 2 2006.245.08:00:13.01#ibcon#about to read 3, iclass 39, count 2 2006.245.08:00:13.04#ibcon#read 3, iclass 39, count 2 2006.245.08:00:13.04#ibcon#about to read 4, iclass 39, count 2 2006.245.08:00:13.04#ibcon#read 4, iclass 39, count 2 2006.245.08:00:13.04#ibcon#about to read 5, iclass 39, count 2 2006.245.08:00:13.04#ibcon#read 5, iclass 39, count 2 2006.245.08:00:13.04#ibcon#about to read 6, iclass 39, count 2 2006.245.08:00:13.04#ibcon#read 6, iclass 39, count 2 2006.245.08:00:13.04#ibcon#end of sib2, iclass 39, count 2 2006.245.08:00:13.04#ibcon#*after write, iclass 39, count 2 2006.245.08:00:13.04#ibcon#*before return 0, iclass 39, count 2 2006.245.08:00:13.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:00:13.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:00:13.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.08:00:13.04#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:13.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:00:13.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:00:13.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:00:13.16#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:00:13.16#ibcon#first serial, iclass 39, count 0 2006.245.08:00:13.16#ibcon#enter sib2, iclass 39, count 0 2006.245.08:00:13.16#ibcon#flushed, iclass 39, count 0 2006.245.08:00:13.16#ibcon#about to write, iclass 39, count 0 2006.245.08:00:13.16#ibcon#wrote, iclass 39, count 0 2006.245.08:00:13.16#ibcon#about to read 3, iclass 39, count 0 2006.245.08:00:13.18#ibcon#read 3, iclass 39, count 0 2006.245.08:00:13.18#ibcon#about to read 4, iclass 39, count 0 2006.245.08:00:13.18#ibcon#read 4, iclass 39, count 0 2006.245.08:00:13.18#ibcon#about to read 5, iclass 39, count 0 2006.245.08:00:13.18#ibcon#read 5, iclass 39, count 0 2006.245.08:00:13.18#ibcon#about to read 6, iclass 39, count 0 2006.245.08:00:13.18#ibcon#read 6, iclass 39, count 0 2006.245.08:00:13.18#ibcon#end of sib2, iclass 39, count 0 2006.245.08:00:13.18#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:00:13.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:00:13.18#ibcon#[27=USB\r\n] 2006.245.08:00:13.18#ibcon#*before write, iclass 39, count 0 2006.245.08:00:13.18#ibcon#enter sib2, iclass 39, count 0 2006.245.08:00:13.18#ibcon#flushed, iclass 39, count 0 2006.245.08:00:13.18#ibcon#about to write, iclass 39, count 0 2006.245.08:00:13.18#ibcon#wrote, iclass 39, count 0 2006.245.08:00:13.18#ibcon#about to read 3, iclass 39, count 0 2006.245.08:00:13.21#ibcon#read 3, iclass 39, count 0 2006.245.08:00:13.21#ibcon#about to read 4, iclass 39, count 0 2006.245.08:00:13.21#ibcon#read 4, iclass 39, count 0 2006.245.08:00:13.21#ibcon#about to read 5, iclass 39, count 0 2006.245.08:00:13.21#ibcon#read 5, iclass 39, count 0 2006.245.08:00:13.21#ibcon#about to read 6, iclass 39, count 0 2006.245.08:00:13.21#ibcon#read 6, iclass 39, count 0 2006.245.08:00:13.21#ibcon#end of sib2, iclass 39, count 0 2006.245.08:00:13.21#ibcon#*after write, iclass 39, count 0 2006.245.08:00:13.21#ibcon#*before return 0, iclass 39, count 0 2006.245.08:00:13.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:00:13.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:00:13.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:00:13.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:00:13.21$vc4f8/vblo=2,640.99 2006.245.08:00:13.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:00:13.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:00:13.21#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:13.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:13.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:13.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:13.21#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:00:13.21#ibcon#first serial, iclass 3, count 0 2006.245.08:00:13.21#ibcon#enter sib2, iclass 3, count 0 2006.245.08:00:13.21#ibcon#flushed, iclass 3, count 0 2006.245.08:00:13.21#ibcon#about to write, iclass 3, count 0 2006.245.08:00:13.21#ibcon#wrote, iclass 3, count 0 2006.245.08:00:13.21#ibcon#about to read 3, iclass 3, count 0 2006.245.08:00:13.23#ibcon#read 3, iclass 3, count 0 2006.245.08:00:13.23#ibcon#about to read 4, iclass 3, count 0 2006.245.08:00:13.23#ibcon#read 4, iclass 3, count 0 2006.245.08:00:13.23#ibcon#about to read 5, iclass 3, count 0 2006.245.08:00:13.23#ibcon#read 5, iclass 3, count 0 2006.245.08:00:13.23#ibcon#about to read 6, iclass 3, count 0 2006.245.08:00:13.23#ibcon#read 6, iclass 3, count 0 2006.245.08:00:13.23#ibcon#end of sib2, iclass 3, count 0 2006.245.08:00:13.23#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:00:13.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:00:13.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:00:13.23#ibcon#*before write, iclass 3, count 0 2006.245.08:00:13.23#ibcon#enter sib2, iclass 3, count 0 2006.245.08:00:13.23#ibcon#flushed, iclass 3, count 0 2006.245.08:00:13.23#ibcon#about to write, iclass 3, count 0 2006.245.08:00:13.23#ibcon#wrote, iclass 3, count 0 2006.245.08:00:13.23#ibcon#about to read 3, iclass 3, count 0 2006.245.08:00:13.27#ibcon#read 3, iclass 3, count 0 2006.245.08:00:13.27#ibcon#about to read 4, iclass 3, count 0 2006.245.08:00:13.27#ibcon#read 4, iclass 3, count 0 2006.245.08:00:13.27#ibcon#about to read 5, iclass 3, count 0 2006.245.08:00:13.27#ibcon#read 5, iclass 3, count 0 2006.245.08:00:13.27#ibcon#about to read 6, iclass 3, count 0 2006.245.08:00:13.27#ibcon#read 6, iclass 3, count 0 2006.245.08:00:13.27#ibcon#end of sib2, iclass 3, count 0 2006.245.08:00:13.27#ibcon#*after write, iclass 3, count 0 2006.245.08:00:13.27#ibcon#*before return 0, iclass 3, count 0 2006.245.08:00:13.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:13.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:00:13.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:00:13.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:00:13.27$vc4f8/vb=2,4 2006.245.08:00:13.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:00:13.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:00:13.27#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:13.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:13.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:13.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:13.33#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:00:13.33#ibcon#first serial, iclass 5, count 2 2006.245.08:00:13.33#ibcon#enter sib2, iclass 5, count 2 2006.245.08:00:13.33#ibcon#flushed, iclass 5, count 2 2006.245.08:00:13.33#ibcon#about to write, iclass 5, count 2 2006.245.08:00:13.33#ibcon#wrote, iclass 5, count 2 2006.245.08:00:13.33#ibcon#about to read 3, iclass 5, count 2 2006.245.08:00:13.35#ibcon#read 3, iclass 5, count 2 2006.245.08:00:13.35#ibcon#about to read 4, iclass 5, count 2 2006.245.08:00:13.35#ibcon#read 4, iclass 5, count 2 2006.245.08:00:13.35#ibcon#about to read 5, iclass 5, count 2 2006.245.08:00:13.35#ibcon#read 5, iclass 5, count 2 2006.245.08:00:13.35#ibcon#about to read 6, iclass 5, count 2 2006.245.08:00:13.35#ibcon#read 6, iclass 5, count 2 2006.245.08:00:13.35#ibcon#end of sib2, iclass 5, count 2 2006.245.08:00:13.35#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:00:13.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:00:13.35#ibcon#[27=AT02-04\r\n] 2006.245.08:00:13.35#ibcon#*before write, iclass 5, count 2 2006.245.08:00:13.35#ibcon#enter sib2, iclass 5, count 2 2006.245.08:00:13.35#ibcon#flushed, iclass 5, count 2 2006.245.08:00:13.35#ibcon#about to write, iclass 5, count 2 2006.245.08:00:13.35#ibcon#wrote, iclass 5, count 2 2006.245.08:00:13.35#ibcon#about to read 3, iclass 5, count 2 2006.245.08:00:13.38#ibcon#read 3, iclass 5, count 2 2006.245.08:00:13.38#ibcon#about to read 4, iclass 5, count 2 2006.245.08:00:13.38#ibcon#read 4, iclass 5, count 2 2006.245.08:00:13.38#ibcon#about to read 5, iclass 5, count 2 2006.245.08:00:13.38#ibcon#read 5, iclass 5, count 2 2006.245.08:00:13.38#ibcon#about to read 6, iclass 5, count 2 2006.245.08:00:13.38#ibcon#read 6, iclass 5, count 2 2006.245.08:00:13.38#ibcon#end of sib2, iclass 5, count 2 2006.245.08:00:13.38#ibcon#*after write, iclass 5, count 2 2006.245.08:00:13.38#ibcon#*before return 0, iclass 5, count 2 2006.245.08:00:13.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:13.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:00:13.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:00:13.38#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:13.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:13.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:13.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:13.50#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:00:13.50#ibcon#first serial, iclass 5, count 0 2006.245.08:00:13.50#ibcon#enter sib2, iclass 5, count 0 2006.245.08:00:13.50#ibcon#flushed, iclass 5, count 0 2006.245.08:00:13.50#ibcon#about to write, iclass 5, count 0 2006.245.08:00:13.50#ibcon#wrote, iclass 5, count 0 2006.245.08:00:13.50#ibcon#about to read 3, iclass 5, count 0 2006.245.08:00:13.52#ibcon#read 3, iclass 5, count 0 2006.245.08:00:13.52#ibcon#about to read 4, iclass 5, count 0 2006.245.08:00:13.52#ibcon#read 4, iclass 5, count 0 2006.245.08:00:13.52#ibcon#about to read 5, iclass 5, count 0 2006.245.08:00:13.52#ibcon#read 5, iclass 5, count 0 2006.245.08:00:13.52#ibcon#about to read 6, iclass 5, count 0 2006.245.08:00:13.52#ibcon#read 6, iclass 5, count 0 2006.245.08:00:13.52#ibcon#end of sib2, iclass 5, count 0 2006.245.08:00:13.52#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:00:13.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:00:13.52#ibcon#[27=USB\r\n] 2006.245.08:00:13.52#ibcon#*before write, iclass 5, count 0 2006.245.08:00:13.52#ibcon#enter sib2, iclass 5, count 0 2006.245.08:00:13.52#ibcon#flushed, iclass 5, count 0 2006.245.08:00:13.52#ibcon#about to write, iclass 5, count 0 2006.245.08:00:13.52#ibcon#wrote, iclass 5, count 0 2006.245.08:00:13.52#ibcon#about to read 3, iclass 5, count 0 2006.245.08:00:13.55#ibcon#read 3, iclass 5, count 0 2006.245.08:00:13.55#ibcon#about to read 4, iclass 5, count 0 2006.245.08:00:13.55#ibcon#read 4, iclass 5, count 0 2006.245.08:00:13.55#ibcon#about to read 5, iclass 5, count 0 2006.245.08:00:13.55#ibcon#read 5, iclass 5, count 0 2006.245.08:00:13.55#ibcon#about to read 6, iclass 5, count 0 2006.245.08:00:13.55#ibcon#read 6, iclass 5, count 0 2006.245.08:00:13.55#ibcon#end of sib2, iclass 5, count 0 2006.245.08:00:13.55#ibcon#*after write, iclass 5, count 0 2006.245.08:00:13.55#ibcon#*before return 0, iclass 5, count 0 2006.245.08:00:13.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:13.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:00:13.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:00:13.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:00:13.55$vc4f8/vblo=3,656.99 2006.245.08:00:13.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:00:13.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:00:13.55#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:13.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:13.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:13.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:13.55#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:00:13.55#ibcon#first serial, iclass 7, count 0 2006.245.08:00:13.55#ibcon#enter sib2, iclass 7, count 0 2006.245.08:00:13.55#ibcon#flushed, iclass 7, count 0 2006.245.08:00:13.55#ibcon#about to write, iclass 7, count 0 2006.245.08:00:13.55#ibcon#wrote, iclass 7, count 0 2006.245.08:00:13.55#ibcon#about to read 3, iclass 7, count 0 2006.245.08:00:13.57#ibcon#read 3, iclass 7, count 0 2006.245.08:00:13.57#ibcon#about to read 4, iclass 7, count 0 2006.245.08:00:13.57#ibcon#read 4, iclass 7, count 0 2006.245.08:00:13.57#ibcon#about to read 5, iclass 7, count 0 2006.245.08:00:13.57#ibcon#read 5, iclass 7, count 0 2006.245.08:00:13.57#ibcon#about to read 6, iclass 7, count 0 2006.245.08:00:13.57#ibcon#read 6, iclass 7, count 0 2006.245.08:00:13.57#ibcon#end of sib2, iclass 7, count 0 2006.245.08:00:13.57#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:00:13.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:00:13.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:00:13.57#ibcon#*before write, iclass 7, count 0 2006.245.08:00:13.57#ibcon#enter sib2, iclass 7, count 0 2006.245.08:00:13.57#ibcon#flushed, iclass 7, count 0 2006.245.08:00:13.57#ibcon#about to write, iclass 7, count 0 2006.245.08:00:13.57#ibcon#wrote, iclass 7, count 0 2006.245.08:00:13.57#ibcon#about to read 3, iclass 7, count 0 2006.245.08:00:13.61#ibcon#read 3, iclass 7, count 0 2006.245.08:00:13.61#ibcon#about to read 4, iclass 7, count 0 2006.245.08:00:13.61#ibcon#read 4, iclass 7, count 0 2006.245.08:00:13.61#ibcon#about to read 5, iclass 7, count 0 2006.245.08:00:13.61#ibcon#read 5, iclass 7, count 0 2006.245.08:00:13.61#ibcon#about to read 6, iclass 7, count 0 2006.245.08:00:13.61#ibcon#read 6, iclass 7, count 0 2006.245.08:00:13.61#ibcon#end of sib2, iclass 7, count 0 2006.245.08:00:13.61#ibcon#*after write, iclass 7, count 0 2006.245.08:00:13.61#ibcon#*before return 0, iclass 7, count 0 2006.245.08:00:13.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:13.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:00:13.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:00:13.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:00:13.61$vc4f8/vb=3,4 2006.245.08:00:13.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:00:13.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:00:13.61#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:13.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:13.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:13.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:13.67#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:00:13.67#ibcon#first serial, iclass 11, count 2 2006.245.08:00:13.67#ibcon#enter sib2, iclass 11, count 2 2006.245.08:00:13.67#ibcon#flushed, iclass 11, count 2 2006.245.08:00:13.67#ibcon#about to write, iclass 11, count 2 2006.245.08:00:13.67#ibcon#wrote, iclass 11, count 2 2006.245.08:00:13.67#ibcon#about to read 3, iclass 11, count 2 2006.245.08:00:13.69#ibcon#read 3, iclass 11, count 2 2006.245.08:00:13.69#ibcon#about to read 4, iclass 11, count 2 2006.245.08:00:13.69#ibcon#read 4, iclass 11, count 2 2006.245.08:00:13.69#ibcon#about to read 5, iclass 11, count 2 2006.245.08:00:13.69#ibcon#read 5, iclass 11, count 2 2006.245.08:00:13.69#ibcon#about to read 6, iclass 11, count 2 2006.245.08:00:13.69#ibcon#read 6, iclass 11, count 2 2006.245.08:00:13.69#ibcon#end of sib2, iclass 11, count 2 2006.245.08:00:13.69#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:00:13.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:00:13.69#ibcon#[27=AT03-04\r\n] 2006.245.08:00:13.69#ibcon#*before write, iclass 11, count 2 2006.245.08:00:13.69#ibcon#enter sib2, iclass 11, count 2 2006.245.08:00:13.69#ibcon#flushed, iclass 11, count 2 2006.245.08:00:13.69#ibcon#about to write, iclass 11, count 2 2006.245.08:00:13.69#ibcon#wrote, iclass 11, count 2 2006.245.08:00:13.69#ibcon#about to read 3, iclass 11, count 2 2006.245.08:00:13.72#ibcon#read 3, iclass 11, count 2 2006.245.08:00:13.72#ibcon#about to read 4, iclass 11, count 2 2006.245.08:00:13.72#ibcon#read 4, iclass 11, count 2 2006.245.08:00:13.72#ibcon#about to read 5, iclass 11, count 2 2006.245.08:00:13.72#ibcon#read 5, iclass 11, count 2 2006.245.08:00:13.72#ibcon#about to read 6, iclass 11, count 2 2006.245.08:00:13.72#ibcon#read 6, iclass 11, count 2 2006.245.08:00:13.72#ibcon#end of sib2, iclass 11, count 2 2006.245.08:00:13.72#ibcon#*after write, iclass 11, count 2 2006.245.08:00:13.72#ibcon#*before return 0, iclass 11, count 2 2006.245.08:00:13.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:13.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:00:13.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:00:13.72#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:13.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:13.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:13.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:13.84#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:00:13.84#ibcon#first serial, iclass 11, count 0 2006.245.08:00:13.84#ibcon#enter sib2, iclass 11, count 0 2006.245.08:00:13.84#ibcon#flushed, iclass 11, count 0 2006.245.08:00:13.84#ibcon#about to write, iclass 11, count 0 2006.245.08:00:13.84#ibcon#wrote, iclass 11, count 0 2006.245.08:00:13.84#ibcon#about to read 3, iclass 11, count 0 2006.245.08:00:13.86#ibcon#read 3, iclass 11, count 0 2006.245.08:00:13.86#ibcon#about to read 4, iclass 11, count 0 2006.245.08:00:13.86#ibcon#read 4, iclass 11, count 0 2006.245.08:00:13.86#ibcon#about to read 5, iclass 11, count 0 2006.245.08:00:13.86#ibcon#read 5, iclass 11, count 0 2006.245.08:00:13.86#ibcon#about to read 6, iclass 11, count 0 2006.245.08:00:13.86#ibcon#read 6, iclass 11, count 0 2006.245.08:00:13.86#ibcon#end of sib2, iclass 11, count 0 2006.245.08:00:13.86#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:00:13.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:00:13.86#ibcon#[27=USB\r\n] 2006.245.08:00:13.86#ibcon#*before write, iclass 11, count 0 2006.245.08:00:13.86#ibcon#enter sib2, iclass 11, count 0 2006.245.08:00:13.86#ibcon#flushed, iclass 11, count 0 2006.245.08:00:13.86#ibcon#about to write, iclass 11, count 0 2006.245.08:00:13.86#ibcon#wrote, iclass 11, count 0 2006.245.08:00:13.86#ibcon#about to read 3, iclass 11, count 0 2006.245.08:00:13.89#ibcon#read 3, iclass 11, count 0 2006.245.08:00:13.89#ibcon#about to read 4, iclass 11, count 0 2006.245.08:00:13.89#ibcon#read 4, iclass 11, count 0 2006.245.08:00:13.89#ibcon#about to read 5, iclass 11, count 0 2006.245.08:00:13.89#ibcon#read 5, iclass 11, count 0 2006.245.08:00:13.89#ibcon#about to read 6, iclass 11, count 0 2006.245.08:00:13.89#ibcon#read 6, iclass 11, count 0 2006.245.08:00:13.89#ibcon#end of sib2, iclass 11, count 0 2006.245.08:00:13.89#ibcon#*after write, iclass 11, count 0 2006.245.08:00:13.89#ibcon#*before return 0, iclass 11, count 0 2006.245.08:00:13.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:13.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:00:13.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:00:13.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:00:13.89$vc4f8/vblo=4,712.99 2006.245.08:00:13.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:00:13.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:00:13.89#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:13.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:13.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:13.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:13.89#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:00:13.89#ibcon#first serial, iclass 13, count 0 2006.245.08:00:13.89#ibcon#enter sib2, iclass 13, count 0 2006.245.08:00:13.89#ibcon#flushed, iclass 13, count 0 2006.245.08:00:13.89#ibcon#about to write, iclass 13, count 0 2006.245.08:00:13.89#ibcon#wrote, iclass 13, count 0 2006.245.08:00:13.89#ibcon#about to read 3, iclass 13, count 0 2006.245.08:00:13.91#ibcon#read 3, iclass 13, count 0 2006.245.08:00:13.91#ibcon#about to read 4, iclass 13, count 0 2006.245.08:00:13.91#ibcon#read 4, iclass 13, count 0 2006.245.08:00:13.91#ibcon#about to read 5, iclass 13, count 0 2006.245.08:00:13.91#ibcon#read 5, iclass 13, count 0 2006.245.08:00:13.91#ibcon#about to read 6, iclass 13, count 0 2006.245.08:00:13.91#ibcon#read 6, iclass 13, count 0 2006.245.08:00:13.91#ibcon#end of sib2, iclass 13, count 0 2006.245.08:00:13.91#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:00:13.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:00:13.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:00:13.91#ibcon#*before write, iclass 13, count 0 2006.245.08:00:13.91#ibcon#enter sib2, iclass 13, count 0 2006.245.08:00:13.91#ibcon#flushed, iclass 13, count 0 2006.245.08:00:13.91#ibcon#about to write, iclass 13, count 0 2006.245.08:00:13.91#ibcon#wrote, iclass 13, count 0 2006.245.08:00:13.91#ibcon#about to read 3, iclass 13, count 0 2006.245.08:00:13.95#ibcon#read 3, iclass 13, count 0 2006.245.08:00:13.95#ibcon#about to read 4, iclass 13, count 0 2006.245.08:00:13.95#ibcon#read 4, iclass 13, count 0 2006.245.08:00:13.95#ibcon#about to read 5, iclass 13, count 0 2006.245.08:00:13.95#ibcon#read 5, iclass 13, count 0 2006.245.08:00:13.95#ibcon#about to read 6, iclass 13, count 0 2006.245.08:00:13.95#ibcon#read 6, iclass 13, count 0 2006.245.08:00:13.95#ibcon#end of sib2, iclass 13, count 0 2006.245.08:00:13.95#ibcon#*after write, iclass 13, count 0 2006.245.08:00:13.95#ibcon#*before return 0, iclass 13, count 0 2006.245.08:00:13.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:13.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:00:13.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:00:13.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:00:13.95$vc4f8/vb=4,4 2006.245.08:00:13.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:00:13.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:00:13.95#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:13.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:14.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:14.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:14.01#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:00:14.01#ibcon#first serial, iclass 15, count 2 2006.245.08:00:14.01#ibcon#enter sib2, iclass 15, count 2 2006.245.08:00:14.01#ibcon#flushed, iclass 15, count 2 2006.245.08:00:14.01#ibcon#about to write, iclass 15, count 2 2006.245.08:00:14.01#ibcon#wrote, iclass 15, count 2 2006.245.08:00:14.01#ibcon#about to read 3, iclass 15, count 2 2006.245.08:00:14.03#ibcon#read 3, iclass 15, count 2 2006.245.08:00:14.03#ibcon#about to read 4, iclass 15, count 2 2006.245.08:00:14.03#ibcon#read 4, iclass 15, count 2 2006.245.08:00:14.03#ibcon#about to read 5, iclass 15, count 2 2006.245.08:00:14.03#ibcon#read 5, iclass 15, count 2 2006.245.08:00:14.03#ibcon#about to read 6, iclass 15, count 2 2006.245.08:00:14.03#ibcon#read 6, iclass 15, count 2 2006.245.08:00:14.03#ibcon#end of sib2, iclass 15, count 2 2006.245.08:00:14.03#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:00:14.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:00:14.03#ibcon#[27=AT04-04\r\n] 2006.245.08:00:14.03#ibcon#*before write, iclass 15, count 2 2006.245.08:00:14.03#ibcon#enter sib2, iclass 15, count 2 2006.245.08:00:14.03#ibcon#flushed, iclass 15, count 2 2006.245.08:00:14.03#ibcon#about to write, iclass 15, count 2 2006.245.08:00:14.03#ibcon#wrote, iclass 15, count 2 2006.245.08:00:14.03#ibcon#about to read 3, iclass 15, count 2 2006.245.08:00:14.06#ibcon#read 3, iclass 15, count 2 2006.245.08:00:14.06#ibcon#about to read 4, iclass 15, count 2 2006.245.08:00:14.06#ibcon#read 4, iclass 15, count 2 2006.245.08:00:14.06#ibcon#about to read 5, iclass 15, count 2 2006.245.08:00:14.06#ibcon#read 5, iclass 15, count 2 2006.245.08:00:14.06#ibcon#about to read 6, iclass 15, count 2 2006.245.08:00:14.06#ibcon#read 6, iclass 15, count 2 2006.245.08:00:14.06#ibcon#end of sib2, iclass 15, count 2 2006.245.08:00:14.06#ibcon#*after write, iclass 15, count 2 2006.245.08:00:14.06#ibcon#*before return 0, iclass 15, count 2 2006.245.08:00:14.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:14.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:00:14.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:00:14.06#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:14.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:14.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:14.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:14.18#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:00:14.18#ibcon#first serial, iclass 15, count 0 2006.245.08:00:14.18#ibcon#enter sib2, iclass 15, count 0 2006.245.08:00:14.18#ibcon#flushed, iclass 15, count 0 2006.245.08:00:14.18#ibcon#about to write, iclass 15, count 0 2006.245.08:00:14.18#ibcon#wrote, iclass 15, count 0 2006.245.08:00:14.18#ibcon#about to read 3, iclass 15, count 0 2006.245.08:00:14.20#ibcon#read 3, iclass 15, count 0 2006.245.08:00:14.20#ibcon#about to read 4, iclass 15, count 0 2006.245.08:00:14.20#ibcon#read 4, iclass 15, count 0 2006.245.08:00:14.20#ibcon#about to read 5, iclass 15, count 0 2006.245.08:00:14.20#ibcon#read 5, iclass 15, count 0 2006.245.08:00:14.20#ibcon#about to read 6, iclass 15, count 0 2006.245.08:00:14.20#ibcon#read 6, iclass 15, count 0 2006.245.08:00:14.20#ibcon#end of sib2, iclass 15, count 0 2006.245.08:00:14.20#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:00:14.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:00:14.20#ibcon#[27=USB\r\n] 2006.245.08:00:14.20#ibcon#*before write, iclass 15, count 0 2006.245.08:00:14.20#ibcon#enter sib2, iclass 15, count 0 2006.245.08:00:14.20#ibcon#flushed, iclass 15, count 0 2006.245.08:00:14.20#ibcon#about to write, iclass 15, count 0 2006.245.08:00:14.20#ibcon#wrote, iclass 15, count 0 2006.245.08:00:14.20#ibcon#about to read 3, iclass 15, count 0 2006.245.08:00:14.23#ibcon#read 3, iclass 15, count 0 2006.245.08:00:14.23#ibcon#about to read 4, iclass 15, count 0 2006.245.08:00:14.23#ibcon#read 4, iclass 15, count 0 2006.245.08:00:14.23#ibcon#about to read 5, iclass 15, count 0 2006.245.08:00:14.23#ibcon#read 5, iclass 15, count 0 2006.245.08:00:14.23#ibcon#about to read 6, iclass 15, count 0 2006.245.08:00:14.23#ibcon#read 6, iclass 15, count 0 2006.245.08:00:14.23#ibcon#end of sib2, iclass 15, count 0 2006.245.08:00:14.23#ibcon#*after write, iclass 15, count 0 2006.245.08:00:14.23#ibcon#*before return 0, iclass 15, count 0 2006.245.08:00:14.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:14.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:00:14.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:00:14.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:00:14.23$vc4f8/vblo=5,744.99 2006.245.08:00:14.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:00:14.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:00:14.23#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:14.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:14.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:14.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:14.23#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:00:14.23#ibcon#first serial, iclass 17, count 0 2006.245.08:00:14.23#ibcon#enter sib2, iclass 17, count 0 2006.245.08:00:14.23#ibcon#flushed, iclass 17, count 0 2006.245.08:00:14.23#ibcon#about to write, iclass 17, count 0 2006.245.08:00:14.23#ibcon#wrote, iclass 17, count 0 2006.245.08:00:14.23#ibcon#about to read 3, iclass 17, count 0 2006.245.08:00:14.25#ibcon#read 3, iclass 17, count 0 2006.245.08:00:14.25#ibcon#about to read 4, iclass 17, count 0 2006.245.08:00:14.25#ibcon#read 4, iclass 17, count 0 2006.245.08:00:14.25#ibcon#about to read 5, iclass 17, count 0 2006.245.08:00:14.25#ibcon#read 5, iclass 17, count 0 2006.245.08:00:14.25#ibcon#about to read 6, iclass 17, count 0 2006.245.08:00:14.25#ibcon#read 6, iclass 17, count 0 2006.245.08:00:14.25#ibcon#end of sib2, iclass 17, count 0 2006.245.08:00:14.25#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:00:14.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:00:14.25#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:00:14.25#ibcon#*before write, iclass 17, count 0 2006.245.08:00:14.25#ibcon#enter sib2, iclass 17, count 0 2006.245.08:00:14.25#ibcon#flushed, iclass 17, count 0 2006.245.08:00:14.25#ibcon#about to write, iclass 17, count 0 2006.245.08:00:14.25#ibcon#wrote, iclass 17, count 0 2006.245.08:00:14.25#ibcon#about to read 3, iclass 17, count 0 2006.245.08:00:14.29#ibcon#read 3, iclass 17, count 0 2006.245.08:00:14.29#ibcon#about to read 4, iclass 17, count 0 2006.245.08:00:14.29#ibcon#read 4, iclass 17, count 0 2006.245.08:00:14.29#ibcon#about to read 5, iclass 17, count 0 2006.245.08:00:14.29#ibcon#read 5, iclass 17, count 0 2006.245.08:00:14.29#ibcon#about to read 6, iclass 17, count 0 2006.245.08:00:14.29#ibcon#read 6, iclass 17, count 0 2006.245.08:00:14.29#ibcon#end of sib2, iclass 17, count 0 2006.245.08:00:14.29#ibcon#*after write, iclass 17, count 0 2006.245.08:00:14.29#ibcon#*before return 0, iclass 17, count 0 2006.245.08:00:14.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:14.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:00:14.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:00:14.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:00:14.29$vc4f8/vb=5,3 2006.245.08:00:14.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:00:14.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:00:14.29#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:14.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:14.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:14.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:14.35#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:00:14.35#ibcon#first serial, iclass 19, count 2 2006.245.08:00:14.35#ibcon#enter sib2, iclass 19, count 2 2006.245.08:00:14.35#ibcon#flushed, iclass 19, count 2 2006.245.08:00:14.35#ibcon#about to write, iclass 19, count 2 2006.245.08:00:14.35#ibcon#wrote, iclass 19, count 2 2006.245.08:00:14.35#ibcon#about to read 3, iclass 19, count 2 2006.245.08:00:14.37#ibcon#read 3, iclass 19, count 2 2006.245.08:00:14.37#ibcon#about to read 4, iclass 19, count 2 2006.245.08:00:14.37#ibcon#read 4, iclass 19, count 2 2006.245.08:00:14.37#ibcon#about to read 5, iclass 19, count 2 2006.245.08:00:14.37#ibcon#read 5, iclass 19, count 2 2006.245.08:00:14.37#ibcon#about to read 6, iclass 19, count 2 2006.245.08:00:14.37#ibcon#read 6, iclass 19, count 2 2006.245.08:00:14.37#ibcon#end of sib2, iclass 19, count 2 2006.245.08:00:14.37#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:00:14.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:00:14.37#ibcon#[27=AT05-03\r\n] 2006.245.08:00:14.37#ibcon#*before write, iclass 19, count 2 2006.245.08:00:14.37#ibcon#enter sib2, iclass 19, count 2 2006.245.08:00:14.37#ibcon#flushed, iclass 19, count 2 2006.245.08:00:14.37#ibcon#about to write, iclass 19, count 2 2006.245.08:00:14.37#ibcon#wrote, iclass 19, count 2 2006.245.08:00:14.37#ibcon#about to read 3, iclass 19, count 2 2006.245.08:00:14.40#ibcon#read 3, iclass 19, count 2 2006.245.08:00:14.40#ibcon#about to read 4, iclass 19, count 2 2006.245.08:00:14.40#ibcon#read 4, iclass 19, count 2 2006.245.08:00:14.40#ibcon#about to read 5, iclass 19, count 2 2006.245.08:00:14.40#ibcon#read 5, iclass 19, count 2 2006.245.08:00:14.40#ibcon#about to read 6, iclass 19, count 2 2006.245.08:00:14.40#ibcon#read 6, iclass 19, count 2 2006.245.08:00:14.40#ibcon#end of sib2, iclass 19, count 2 2006.245.08:00:14.40#ibcon#*after write, iclass 19, count 2 2006.245.08:00:14.40#ibcon#*before return 0, iclass 19, count 2 2006.245.08:00:14.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:14.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:00:14.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:00:14.40#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:14.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:14.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:14.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:14.52#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:00:14.52#ibcon#first serial, iclass 19, count 0 2006.245.08:00:14.52#ibcon#enter sib2, iclass 19, count 0 2006.245.08:00:14.52#ibcon#flushed, iclass 19, count 0 2006.245.08:00:14.52#ibcon#about to write, iclass 19, count 0 2006.245.08:00:14.52#ibcon#wrote, iclass 19, count 0 2006.245.08:00:14.52#ibcon#about to read 3, iclass 19, count 0 2006.245.08:00:14.54#ibcon#read 3, iclass 19, count 0 2006.245.08:00:14.54#ibcon#about to read 4, iclass 19, count 0 2006.245.08:00:14.54#ibcon#read 4, iclass 19, count 0 2006.245.08:00:14.54#ibcon#about to read 5, iclass 19, count 0 2006.245.08:00:14.54#ibcon#read 5, iclass 19, count 0 2006.245.08:00:14.54#ibcon#about to read 6, iclass 19, count 0 2006.245.08:00:14.54#ibcon#read 6, iclass 19, count 0 2006.245.08:00:14.54#ibcon#end of sib2, iclass 19, count 0 2006.245.08:00:14.54#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:00:14.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:00:14.54#ibcon#[27=USB\r\n] 2006.245.08:00:14.54#ibcon#*before write, iclass 19, count 0 2006.245.08:00:14.54#ibcon#enter sib2, iclass 19, count 0 2006.245.08:00:14.54#ibcon#flushed, iclass 19, count 0 2006.245.08:00:14.54#ibcon#about to write, iclass 19, count 0 2006.245.08:00:14.54#ibcon#wrote, iclass 19, count 0 2006.245.08:00:14.54#ibcon#about to read 3, iclass 19, count 0 2006.245.08:00:14.57#ibcon#read 3, iclass 19, count 0 2006.245.08:00:14.57#ibcon#about to read 4, iclass 19, count 0 2006.245.08:00:14.57#ibcon#read 4, iclass 19, count 0 2006.245.08:00:14.57#ibcon#about to read 5, iclass 19, count 0 2006.245.08:00:14.57#ibcon#read 5, iclass 19, count 0 2006.245.08:00:14.57#ibcon#about to read 6, iclass 19, count 0 2006.245.08:00:14.57#ibcon#read 6, iclass 19, count 0 2006.245.08:00:14.57#ibcon#end of sib2, iclass 19, count 0 2006.245.08:00:14.57#ibcon#*after write, iclass 19, count 0 2006.245.08:00:14.57#ibcon#*before return 0, iclass 19, count 0 2006.245.08:00:14.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:14.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:00:14.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:00:14.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:00:14.57$vc4f8/vblo=6,752.99 2006.245.08:00:14.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:00:14.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:00:14.57#ibcon#ireg 17 cls_cnt 0 2006.245.08:00:14.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:14.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:14.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:14.57#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:00:14.57#ibcon#first serial, iclass 21, count 0 2006.245.08:00:14.57#ibcon#enter sib2, iclass 21, count 0 2006.245.08:00:14.57#ibcon#flushed, iclass 21, count 0 2006.245.08:00:14.57#ibcon#about to write, iclass 21, count 0 2006.245.08:00:14.57#ibcon#wrote, iclass 21, count 0 2006.245.08:00:14.57#ibcon#about to read 3, iclass 21, count 0 2006.245.08:00:14.60#ibcon#read 3, iclass 21, count 0 2006.245.08:00:14.60#ibcon#about to read 4, iclass 21, count 0 2006.245.08:00:14.60#ibcon#read 4, iclass 21, count 0 2006.245.08:00:14.60#ibcon#about to read 5, iclass 21, count 0 2006.245.08:00:14.60#ibcon#read 5, iclass 21, count 0 2006.245.08:00:14.60#ibcon#about to read 6, iclass 21, count 0 2006.245.08:00:14.60#ibcon#read 6, iclass 21, count 0 2006.245.08:00:14.60#ibcon#end of sib2, iclass 21, count 0 2006.245.08:00:14.60#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:00:14.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:00:14.60#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:00:14.60#ibcon#*before write, iclass 21, count 0 2006.245.08:00:14.60#ibcon#enter sib2, iclass 21, count 0 2006.245.08:00:14.60#ibcon#flushed, iclass 21, count 0 2006.245.08:00:14.60#ibcon#about to write, iclass 21, count 0 2006.245.08:00:14.60#ibcon#wrote, iclass 21, count 0 2006.245.08:00:14.60#ibcon#about to read 3, iclass 21, count 0 2006.245.08:00:14.64#ibcon#read 3, iclass 21, count 0 2006.245.08:00:14.64#ibcon#about to read 4, iclass 21, count 0 2006.245.08:00:14.64#ibcon#read 4, iclass 21, count 0 2006.245.08:00:14.64#ibcon#about to read 5, iclass 21, count 0 2006.245.08:00:14.64#ibcon#read 5, iclass 21, count 0 2006.245.08:00:14.64#ibcon#about to read 6, iclass 21, count 0 2006.245.08:00:14.64#ibcon#read 6, iclass 21, count 0 2006.245.08:00:14.64#ibcon#end of sib2, iclass 21, count 0 2006.245.08:00:14.64#ibcon#*after write, iclass 21, count 0 2006.245.08:00:14.64#ibcon#*before return 0, iclass 21, count 0 2006.245.08:00:14.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:14.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:00:14.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:00:14.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:00:14.64$vc4f8/vb=6,3 2006.245.08:00:14.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.08:00:14.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.08:00:14.64#ibcon#ireg 11 cls_cnt 2 2006.245.08:00:14.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:14.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:14.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:14.69#ibcon#enter wrdev, iclass 23, count 2 2006.245.08:00:14.69#ibcon#first serial, iclass 23, count 2 2006.245.08:00:14.69#ibcon#enter sib2, iclass 23, count 2 2006.245.08:00:14.69#ibcon#flushed, iclass 23, count 2 2006.245.08:00:14.69#ibcon#about to write, iclass 23, count 2 2006.245.08:00:14.69#ibcon#wrote, iclass 23, count 2 2006.245.08:00:14.69#ibcon#about to read 3, iclass 23, count 2 2006.245.08:00:14.71#ibcon#read 3, iclass 23, count 2 2006.245.08:00:14.71#ibcon#about to read 4, iclass 23, count 2 2006.245.08:00:14.71#ibcon#read 4, iclass 23, count 2 2006.245.08:00:14.71#ibcon#about to read 5, iclass 23, count 2 2006.245.08:00:14.71#ibcon#read 5, iclass 23, count 2 2006.245.08:00:14.71#ibcon#about to read 6, iclass 23, count 2 2006.245.08:00:14.71#ibcon#read 6, iclass 23, count 2 2006.245.08:00:14.71#ibcon#end of sib2, iclass 23, count 2 2006.245.08:00:14.71#ibcon#*mode == 0, iclass 23, count 2 2006.245.08:00:14.71#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.08:00:14.71#ibcon#[27=AT06-03\r\n] 2006.245.08:00:14.71#ibcon#*before write, iclass 23, count 2 2006.245.08:00:14.71#ibcon#enter sib2, iclass 23, count 2 2006.245.08:00:14.71#ibcon#flushed, iclass 23, count 2 2006.245.08:00:14.71#ibcon#about to write, iclass 23, count 2 2006.245.08:00:14.71#ibcon#wrote, iclass 23, count 2 2006.245.08:00:14.71#ibcon#about to read 3, iclass 23, count 2 2006.245.08:00:14.74#ibcon#read 3, iclass 23, count 2 2006.245.08:00:14.74#ibcon#about to read 4, iclass 23, count 2 2006.245.08:00:14.74#ibcon#read 4, iclass 23, count 2 2006.245.08:00:14.74#ibcon#about to read 5, iclass 23, count 2 2006.245.08:00:14.74#ibcon#read 5, iclass 23, count 2 2006.245.08:00:14.74#ibcon#about to read 6, iclass 23, count 2 2006.245.08:00:14.74#ibcon#read 6, iclass 23, count 2 2006.245.08:00:14.74#ibcon#end of sib2, iclass 23, count 2 2006.245.08:00:14.74#ibcon#*after write, iclass 23, count 2 2006.245.08:00:14.74#ibcon#*before return 0, iclass 23, count 2 2006.245.08:00:14.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:14.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:00:14.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.08:00:14.74#ibcon#ireg 7 cls_cnt 0 2006.245.08:00:14.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:14.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:14.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:14.86#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:00:14.86#ibcon#first serial, iclass 23, count 0 2006.245.08:00:14.86#ibcon#enter sib2, iclass 23, count 0 2006.245.08:00:14.86#ibcon#flushed, iclass 23, count 0 2006.245.08:00:14.86#ibcon#about to write, iclass 23, count 0 2006.245.08:00:14.86#ibcon#wrote, iclass 23, count 0 2006.245.08:00:14.86#ibcon#about to read 3, iclass 23, count 0 2006.245.08:00:14.88#ibcon#read 3, iclass 23, count 0 2006.245.08:00:14.88#ibcon#about to read 4, iclass 23, count 0 2006.245.08:00:14.88#ibcon#read 4, iclass 23, count 0 2006.245.08:00:14.88#ibcon#about to read 5, iclass 23, count 0 2006.245.08:00:14.88#ibcon#read 5, iclass 23, count 0 2006.245.08:00:14.88#ibcon#about to read 6, iclass 23, count 0 2006.245.08:00:14.88#ibcon#read 6, iclass 23, count 0 2006.245.08:00:14.88#ibcon#end of sib2, iclass 23, count 0 2006.245.08:00:14.88#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:00:14.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:00:14.88#ibcon#[27=USB\r\n] 2006.245.08:00:14.88#ibcon#*before write, iclass 23, count 0 2006.245.08:00:14.88#ibcon#enter sib2, iclass 23, count 0 2006.245.08:00:14.88#ibcon#flushed, iclass 23, count 0 2006.245.08:00:14.88#ibcon#about to write, iclass 23, count 0 2006.245.08:00:14.88#ibcon#wrote, iclass 23, count 0 2006.245.08:00:14.88#ibcon#about to read 3, iclass 23, count 0 2006.245.08:00:14.91#ibcon#read 3, iclass 23, count 0 2006.245.08:00:14.91#ibcon#about to read 4, iclass 23, count 0 2006.245.08:00:14.91#ibcon#read 4, iclass 23, count 0 2006.245.08:00:14.91#ibcon#about to read 5, iclass 23, count 0 2006.245.08:00:14.91#ibcon#read 5, iclass 23, count 0 2006.245.08:00:14.91#ibcon#about to read 6, iclass 23, count 0 2006.245.08:00:14.91#ibcon#read 6, iclass 23, count 0 2006.245.08:00:14.91#ibcon#end of sib2, iclass 23, count 0 2006.245.08:00:14.91#ibcon#*after write, iclass 23, count 0 2006.245.08:00:14.91#ibcon#*before return 0, iclass 23, count 0 2006.245.08:00:14.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:14.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:00:14.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:00:14.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:00:14.91$vc4f8/vabw=wide 2006.245.08:00:14.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.08:00:14.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.08:00:14.91#ibcon#ireg 8 cls_cnt 0 2006.245.08:00:14.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:14.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:14.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:14.91#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:00:14.91#ibcon#first serial, iclass 25, count 0 2006.245.08:00:14.91#ibcon#enter sib2, iclass 25, count 0 2006.245.08:00:14.91#ibcon#flushed, iclass 25, count 0 2006.245.08:00:14.91#ibcon#about to write, iclass 25, count 0 2006.245.08:00:14.91#ibcon#wrote, iclass 25, count 0 2006.245.08:00:14.91#ibcon#about to read 3, iclass 25, count 0 2006.245.08:00:14.93#ibcon#read 3, iclass 25, count 0 2006.245.08:00:14.93#ibcon#about to read 4, iclass 25, count 0 2006.245.08:00:14.93#ibcon#read 4, iclass 25, count 0 2006.245.08:00:14.93#ibcon#about to read 5, iclass 25, count 0 2006.245.08:00:14.93#ibcon#read 5, iclass 25, count 0 2006.245.08:00:14.93#ibcon#about to read 6, iclass 25, count 0 2006.245.08:00:14.93#ibcon#read 6, iclass 25, count 0 2006.245.08:00:14.93#ibcon#end of sib2, iclass 25, count 0 2006.245.08:00:14.93#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:00:14.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:00:14.93#ibcon#[25=BW32\r\n] 2006.245.08:00:14.93#ibcon#*before write, iclass 25, count 0 2006.245.08:00:14.93#ibcon#enter sib2, iclass 25, count 0 2006.245.08:00:14.93#ibcon#flushed, iclass 25, count 0 2006.245.08:00:14.93#ibcon#about to write, iclass 25, count 0 2006.245.08:00:14.93#ibcon#wrote, iclass 25, count 0 2006.245.08:00:14.93#ibcon#about to read 3, iclass 25, count 0 2006.245.08:00:14.96#ibcon#read 3, iclass 25, count 0 2006.245.08:00:14.96#ibcon#about to read 4, iclass 25, count 0 2006.245.08:00:14.96#ibcon#read 4, iclass 25, count 0 2006.245.08:00:14.96#ibcon#about to read 5, iclass 25, count 0 2006.245.08:00:14.96#ibcon#read 5, iclass 25, count 0 2006.245.08:00:14.96#ibcon#about to read 6, iclass 25, count 0 2006.245.08:00:14.96#ibcon#read 6, iclass 25, count 0 2006.245.08:00:14.96#ibcon#end of sib2, iclass 25, count 0 2006.245.08:00:14.96#ibcon#*after write, iclass 25, count 0 2006.245.08:00:14.96#ibcon#*before return 0, iclass 25, count 0 2006.245.08:00:14.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:14.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:00:14.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:00:14.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:00:14.96$vc4f8/vbbw=wide 2006.245.08:00:14.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.08:00:14.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.08:00:14.96#ibcon#ireg 8 cls_cnt 0 2006.245.08:00:14.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:00:15.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:00:15.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:00:15.03#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:00:15.03#ibcon#first serial, iclass 27, count 0 2006.245.08:00:15.03#ibcon#enter sib2, iclass 27, count 0 2006.245.08:00:15.03#ibcon#flushed, iclass 27, count 0 2006.245.08:00:15.03#ibcon#about to write, iclass 27, count 0 2006.245.08:00:15.03#ibcon#wrote, iclass 27, count 0 2006.245.08:00:15.03#ibcon#about to read 3, iclass 27, count 0 2006.245.08:00:15.05#ibcon#read 3, iclass 27, count 0 2006.245.08:00:15.05#ibcon#about to read 4, iclass 27, count 0 2006.245.08:00:15.05#ibcon#read 4, iclass 27, count 0 2006.245.08:00:15.05#ibcon#about to read 5, iclass 27, count 0 2006.245.08:00:15.05#ibcon#read 5, iclass 27, count 0 2006.245.08:00:15.05#ibcon#about to read 6, iclass 27, count 0 2006.245.08:00:15.05#ibcon#read 6, iclass 27, count 0 2006.245.08:00:15.05#ibcon#end of sib2, iclass 27, count 0 2006.245.08:00:15.05#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:00:15.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:00:15.05#ibcon#[27=BW32\r\n] 2006.245.08:00:15.05#ibcon#*before write, iclass 27, count 0 2006.245.08:00:15.05#ibcon#enter sib2, iclass 27, count 0 2006.245.08:00:15.05#ibcon#flushed, iclass 27, count 0 2006.245.08:00:15.05#ibcon#about to write, iclass 27, count 0 2006.245.08:00:15.05#ibcon#wrote, iclass 27, count 0 2006.245.08:00:15.05#ibcon#about to read 3, iclass 27, count 0 2006.245.08:00:15.08#ibcon#read 3, iclass 27, count 0 2006.245.08:00:15.08#ibcon#about to read 4, iclass 27, count 0 2006.245.08:00:15.08#ibcon#read 4, iclass 27, count 0 2006.245.08:00:15.08#ibcon#about to read 5, iclass 27, count 0 2006.245.08:00:15.08#ibcon#read 5, iclass 27, count 0 2006.245.08:00:15.08#ibcon#about to read 6, iclass 27, count 0 2006.245.08:00:15.08#ibcon#read 6, iclass 27, count 0 2006.245.08:00:15.08#ibcon#end of sib2, iclass 27, count 0 2006.245.08:00:15.08#ibcon#*after write, iclass 27, count 0 2006.245.08:00:15.08#ibcon#*before return 0, iclass 27, count 0 2006.245.08:00:15.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:00:15.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:00:15.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:00:15.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:00:15.08$4f8m12a/ifd4f 2006.245.08:00:15.08$ifd4f/lo= 2006.245.08:00:15.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:00:15.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:00:15.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:00:15.08$ifd4f/patch= 2006.245.08:00:15.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:00:15.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:00:15.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:00:15.08$4f8m12a/"form=m,16.000,1:2 2006.245.08:00:15.08$4f8m12a/"tpicd 2006.245.08:00:15.08$4f8m12a/echo=off 2006.245.08:00:15.09$4f8m12a/xlog=off 2006.245.08:00:15.09:!2006.245.08:00:40 2006.245.08:00:25.14#trakl#Source acquired 2006.245.08:00:27.14#flagr#flagr/antenna,acquired 2006.245.08:00:40.01:preob 2006.245.08:00:41.14/onsource/TRACKING 2006.245.08:00:41.14:!2006.245.08:00:50 2006.245.08:00:50.00:data_valid=on 2006.245.08:00:50.00:midob 2006.245.08:00:50.14/onsource/TRACKING 2006.245.08:00:50.14/wx/27.15,1004.5,71 2006.245.08:00:50.29/cable/+6.4080E-03 2006.245.08:00:51.38/va/01,08,usb,yes,34,36 2006.245.08:00:51.38/va/02,07,usb,yes,34,36 2006.245.08:00:51.38/va/03,06,usb,yes,36,37 2006.245.08:00:51.38/va/04,07,usb,yes,35,38 2006.245.08:00:51.38/va/05,07,usb,yes,38,40 2006.245.08:00:51.38/va/06,07,usb,yes,33,33 2006.245.08:00:51.38/va/07,07,usb,yes,33,32 2006.245.08:00:51.38/va/08,08,usb,yes,29,28 2006.245.08:00:51.61/valo/01,532.99,yes,locked 2006.245.08:00:51.61/valo/02,572.99,yes,locked 2006.245.08:00:51.61/valo/03,672.99,yes,locked 2006.245.08:00:51.61/valo/04,832.99,yes,locked 2006.245.08:00:51.61/valo/05,652.99,yes,locked 2006.245.08:00:51.61/valo/06,772.99,yes,locked 2006.245.08:00:51.61/valo/07,832.99,yes,locked 2006.245.08:00:51.61/valo/08,852.99,yes,locked 2006.245.08:00:52.70/vb/01,04,usb,yes,33,32 2006.245.08:00:52.70/vb/02,04,usb,yes,35,37 2006.245.08:00:52.70/vb/03,04,usb,yes,31,35 2006.245.08:00:52.70/vb/04,04,usb,yes,34,33 2006.245.08:00:52.70/vb/05,03,usb,yes,38,43 2006.245.08:00:52.70/vb/06,03,usb,yes,39,43 2006.245.08:00:52.70/vb/07,04,usb,yes,34,35 2006.245.08:00:52.70/vb/08,03,usb,yes,39,43 2006.245.08:00:52.94/vblo/01,632.99,yes,locked 2006.245.08:00:52.94/vblo/02,640.99,yes,locked 2006.245.08:00:52.94/vblo/03,656.99,yes,locked 2006.245.08:00:52.94/vblo/04,712.99,yes,locked 2006.245.08:00:52.94/vblo/05,744.99,yes,locked 2006.245.08:00:52.94/vblo/06,752.99,yes,locked 2006.245.08:00:52.94/vblo/07,734.99,yes,locked 2006.245.08:00:52.94/vblo/08,744.99,yes,locked 2006.245.08:00:53.09/vabw/8 2006.245.08:00:53.24/vbbw/8 2006.245.08:00:53.33/xfe/off,on,13.5 2006.245.08:00:53.70/ifatt/23,28,28,28 2006.245.08:00:54.07/fmout-gps/S +4.39E-07 2006.245.08:00:54.11:!2006.245.08:01:50 2006.245.08:01:50.00:data_valid=off 2006.245.08:01:50.01:postob 2006.245.08:01:50.08/cable/+6.4081E-03 2006.245.08:01:50.08/wx/27.12,1004.5,71 2006.245.08:01:51.07/fmout-gps/S +4.39E-07 2006.245.08:01:51.08:scan_name=245-0802,k06245,60 2006.245.08:01:51.08:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.245.08:01:52.14#flagr#flagr/antenna,new-source 2006.245.08:01:52.15:checkk5 2006.245.08:01:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:01:53.01/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:01:53.48/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:01:53.92/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:01:54.37/chk_obsdata//k5ts1/T2450800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:01:54.80/chk_obsdata//k5ts2/T2450800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:01:55.24/chk_obsdata//k5ts3/T2450800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:01:55.96/chk_obsdata//k5ts4/T2450800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:01:56.85/k5log//k5ts1_log_newline 2006.245.08:01:58.01/k5log//k5ts2_log_newline 2006.245.08:01:59.07/k5log//k5ts3_log_newline 2006.245.08:02:00.02/k5log//k5ts4_log_newline 2006.245.08:02:00.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:02:00.04:4f8m12a=2 2006.245.08:02:00.04$4f8m12a/echo=on 2006.245.08:02:00.04$4f8m12a/pcalon 2006.245.08:02:00.04$pcalon/"no phase cal control is implemented here 2006.245.08:02:00.04$4f8m12a/"tpicd=stop 2006.245.08:02:00.04$4f8m12a/vc4f8 2006.245.08:02:00.04$vc4f8/valo=1,532.99 2006.245.08:02:00.04#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.08:02:00.04#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.08:02:00.04#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:00.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:00.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:00.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:00.04#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:02:00.04#ibcon#first serial, iclass 38, count 0 2006.245.08:02:00.04#ibcon#enter sib2, iclass 38, count 0 2006.245.08:02:00.04#ibcon#flushed, iclass 38, count 0 2006.245.08:02:00.04#ibcon#about to write, iclass 38, count 0 2006.245.08:02:00.04#ibcon#wrote, iclass 38, count 0 2006.245.08:02:00.04#ibcon#about to read 3, iclass 38, count 0 2006.245.08:02:00.08#ibcon#read 3, iclass 38, count 0 2006.245.08:02:00.08#ibcon#about to read 4, iclass 38, count 0 2006.245.08:02:00.08#ibcon#read 4, iclass 38, count 0 2006.245.08:02:00.08#ibcon#about to read 5, iclass 38, count 0 2006.245.08:02:00.08#ibcon#read 5, iclass 38, count 0 2006.245.08:02:00.08#ibcon#about to read 6, iclass 38, count 0 2006.245.08:02:00.08#ibcon#read 6, iclass 38, count 0 2006.245.08:02:00.08#ibcon#end of sib2, iclass 38, count 0 2006.245.08:02:00.08#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:02:00.08#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:02:00.08#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:02:00.08#ibcon#*before write, iclass 38, count 0 2006.245.08:02:00.08#ibcon#enter sib2, iclass 38, count 0 2006.245.08:02:00.08#ibcon#flushed, iclass 38, count 0 2006.245.08:02:00.08#ibcon#about to write, iclass 38, count 0 2006.245.08:02:00.08#ibcon#wrote, iclass 38, count 0 2006.245.08:02:00.08#ibcon#about to read 3, iclass 38, count 0 2006.245.08:02:00.13#ibcon#read 3, iclass 38, count 0 2006.245.08:02:00.13#ibcon#about to read 4, iclass 38, count 0 2006.245.08:02:00.13#ibcon#read 4, iclass 38, count 0 2006.245.08:02:00.13#ibcon#about to read 5, iclass 38, count 0 2006.245.08:02:00.13#ibcon#read 5, iclass 38, count 0 2006.245.08:02:00.13#ibcon#about to read 6, iclass 38, count 0 2006.245.08:02:00.13#ibcon#read 6, iclass 38, count 0 2006.245.08:02:00.13#ibcon#end of sib2, iclass 38, count 0 2006.245.08:02:00.13#ibcon#*after write, iclass 38, count 0 2006.245.08:02:00.13#ibcon#*before return 0, iclass 38, count 0 2006.245.08:02:00.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:00.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:00.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:02:00.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:02:00.13$vc4f8/va=1,8 2006.245.08:02:00.13#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.08:02:00.13#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.08:02:00.13#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:00.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:00.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:00.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:00.13#ibcon#enter wrdev, iclass 40, count 2 2006.245.08:02:00.13#ibcon#first serial, iclass 40, count 2 2006.245.08:02:00.13#ibcon#enter sib2, iclass 40, count 2 2006.245.08:02:00.13#ibcon#flushed, iclass 40, count 2 2006.245.08:02:00.13#ibcon#about to write, iclass 40, count 2 2006.245.08:02:00.13#ibcon#wrote, iclass 40, count 2 2006.245.08:02:00.13#ibcon#about to read 3, iclass 40, count 2 2006.245.08:02:00.16#ibcon#read 3, iclass 40, count 2 2006.245.08:02:00.16#ibcon#about to read 4, iclass 40, count 2 2006.245.08:02:00.16#ibcon#read 4, iclass 40, count 2 2006.245.08:02:00.16#ibcon#about to read 5, iclass 40, count 2 2006.245.08:02:00.16#ibcon#read 5, iclass 40, count 2 2006.245.08:02:00.16#ibcon#about to read 6, iclass 40, count 2 2006.245.08:02:00.16#ibcon#read 6, iclass 40, count 2 2006.245.08:02:00.16#ibcon#end of sib2, iclass 40, count 2 2006.245.08:02:00.16#ibcon#*mode == 0, iclass 40, count 2 2006.245.08:02:00.16#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.08:02:00.16#ibcon#[25=AT01-08\r\n] 2006.245.08:02:00.16#ibcon#*before write, iclass 40, count 2 2006.245.08:02:00.16#ibcon#enter sib2, iclass 40, count 2 2006.245.08:02:00.16#ibcon#flushed, iclass 40, count 2 2006.245.08:02:00.16#ibcon#about to write, iclass 40, count 2 2006.245.08:02:00.16#ibcon#wrote, iclass 40, count 2 2006.245.08:02:00.16#ibcon#about to read 3, iclass 40, count 2 2006.245.08:02:00.19#ibcon#read 3, iclass 40, count 2 2006.245.08:02:00.19#ibcon#about to read 4, iclass 40, count 2 2006.245.08:02:00.19#ibcon#read 4, iclass 40, count 2 2006.245.08:02:00.19#ibcon#about to read 5, iclass 40, count 2 2006.245.08:02:00.19#ibcon#read 5, iclass 40, count 2 2006.245.08:02:00.19#ibcon#about to read 6, iclass 40, count 2 2006.245.08:02:00.19#ibcon#read 6, iclass 40, count 2 2006.245.08:02:00.19#ibcon#end of sib2, iclass 40, count 2 2006.245.08:02:00.19#ibcon#*after write, iclass 40, count 2 2006.245.08:02:00.19#ibcon#*before return 0, iclass 40, count 2 2006.245.08:02:00.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:00.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:00.19#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.08:02:00.19#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:00.19#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:00.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:00.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:00.31#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:02:00.31#ibcon#first serial, iclass 40, count 0 2006.245.08:02:00.31#ibcon#enter sib2, iclass 40, count 0 2006.245.08:02:00.31#ibcon#flushed, iclass 40, count 0 2006.245.08:02:00.31#ibcon#about to write, iclass 40, count 0 2006.245.08:02:00.31#ibcon#wrote, iclass 40, count 0 2006.245.08:02:00.31#ibcon#about to read 3, iclass 40, count 0 2006.245.08:02:00.33#ibcon#read 3, iclass 40, count 0 2006.245.08:02:00.33#ibcon#about to read 4, iclass 40, count 0 2006.245.08:02:00.33#ibcon#read 4, iclass 40, count 0 2006.245.08:02:00.33#ibcon#about to read 5, iclass 40, count 0 2006.245.08:02:00.33#ibcon#read 5, iclass 40, count 0 2006.245.08:02:00.33#ibcon#about to read 6, iclass 40, count 0 2006.245.08:02:00.33#ibcon#read 6, iclass 40, count 0 2006.245.08:02:00.33#ibcon#end of sib2, iclass 40, count 0 2006.245.08:02:00.33#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:02:00.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:02:00.33#ibcon#[25=USB\r\n] 2006.245.08:02:00.33#ibcon#*before write, iclass 40, count 0 2006.245.08:02:00.33#ibcon#enter sib2, iclass 40, count 0 2006.245.08:02:00.33#ibcon#flushed, iclass 40, count 0 2006.245.08:02:00.33#ibcon#about to write, iclass 40, count 0 2006.245.08:02:00.33#ibcon#wrote, iclass 40, count 0 2006.245.08:02:00.33#ibcon#about to read 3, iclass 40, count 0 2006.245.08:02:00.36#ibcon#read 3, iclass 40, count 0 2006.245.08:02:00.36#ibcon#about to read 4, iclass 40, count 0 2006.245.08:02:00.36#ibcon#read 4, iclass 40, count 0 2006.245.08:02:00.36#ibcon#about to read 5, iclass 40, count 0 2006.245.08:02:00.36#ibcon#read 5, iclass 40, count 0 2006.245.08:02:00.36#ibcon#about to read 6, iclass 40, count 0 2006.245.08:02:00.36#ibcon#read 6, iclass 40, count 0 2006.245.08:02:00.36#ibcon#end of sib2, iclass 40, count 0 2006.245.08:02:00.36#ibcon#*after write, iclass 40, count 0 2006.245.08:02:00.36#ibcon#*before return 0, iclass 40, count 0 2006.245.08:02:00.36#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:00.36#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:00.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:02:00.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:02:00.36$vc4f8/valo=2,572.99 2006.245.08:02:00.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.08:02:00.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.08:02:00.36#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:00.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:00.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:00.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:00.36#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:02:00.36#ibcon#first serial, iclass 4, count 0 2006.245.08:02:00.36#ibcon#enter sib2, iclass 4, count 0 2006.245.08:02:00.36#ibcon#flushed, iclass 4, count 0 2006.245.08:02:00.36#ibcon#about to write, iclass 4, count 0 2006.245.08:02:00.36#ibcon#wrote, iclass 4, count 0 2006.245.08:02:00.36#ibcon#about to read 3, iclass 4, count 0 2006.245.08:02:00.39#ibcon#read 3, iclass 4, count 0 2006.245.08:02:00.39#ibcon#about to read 4, iclass 4, count 0 2006.245.08:02:00.39#ibcon#read 4, iclass 4, count 0 2006.245.08:02:00.39#ibcon#about to read 5, iclass 4, count 0 2006.245.08:02:00.39#ibcon#read 5, iclass 4, count 0 2006.245.08:02:00.39#ibcon#about to read 6, iclass 4, count 0 2006.245.08:02:00.39#ibcon#read 6, iclass 4, count 0 2006.245.08:02:00.39#ibcon#end of sib2, iclass 4, count 0 2006.245.08:02:00.39#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:02:00.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:02:00.39#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:02:00.39#ibcon#*before write, iclass 4, count 0 2006.245.08:02:00.39#ibcon#enter sib2, iclass 4, count 0 2006.245.08:02:00.39#ibcon#flushed, iclass 4, count 0 2006.245.08:02:00.39#ibcon#about to write, iclass 4, count 0 2006.245.08:02:00.39#ibcon#wrote, iclass 4, count 0 2006.245.08:02:00.39#ibcon#about to read 3, iclass 4, count 0 2006.245.08:02:00.43#ibcon#read 3, iclass 4, count 0 2006.245.08:02:00.43#ibcon#about to read 4, iclass 4, count 0 2006.245.08:02:00.43#ibcon#read 4, iclass 4, count 0 2006.245.08:02:00.43#ibcon#about to read 5, iclass 4, count 0 2006.245.08:02:00.43#ibcon#read 5, iclass 4, count 0 2006.245.08:02:00.43#ibcon#about to read 6, iclass 4, count 0 2006.245.08:02:00.43#ibcon#read 6, iclass 4, count 0 2006.245.08:02:00.43#ibcon#end of sib2, iclass 4, count 0 2006.245.08:02:00.43#ibcon#*after write, iclass 4, count 0 2006.245.08:02:00.43#ibcon#*before return 0, iclass 4, count 0 2006.245.08:02:00.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:00.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:00.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:02:00.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:02:00.43$vc4f8/va=2,7 2006.245.08:02:00.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.08:02:00.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.08:02:00.43#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:00.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:00.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:00.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:00.48#ibcon#enter wrdev, iclass 6, count 2 2006.245.08:02:00.48#ibcon#first serial, iclass 6, count 2 2006.245.08:02:00.48#ibcon#enter sib2, iclass 6, count 2 2006.245.08:02:00.48#ibcon#flushed, iclass 6, count 2 2006.245.08:02:00.48#ibcon#about to write, iclass 6, count 2 2006.245.08:02:00.48#ibcon#wrote, iclass 6, count 2 2006.245.08:02:00.48#ibcon#about to read 3, iclass 6, count 2 2006.245.08:02:00.50#ibcon#read 3, iclass 6, count 2 2006.245.08:02:00.50#ibcon#about to read 4, iclass 6, count 2 2006.245.08:02:00.50#ibcon#read 4, iclass 6, count 2 2006.245.08:02:00.50#ibcon#about to read 5, iclass 6, count 2 2006.245.08:02:00.50#ibcon#read 5, iclass 6, count 2 2006.245.08:02:00.50#ibcon#about to read 6, iclass 6, count 2 2006.245.08:02:00.50#ibcon#read 6, iclass 6, count 2 2006.245.08:02:00.50#ibcon#end of sib2, iclass 6, count 2 2006.245.08:02:00.50#ibcon#*mode == 0, iclass 6, count 2 2006.245.08:02:00.50#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.08:02:00.50#ibcon#[25=AT02-07\r\n] 2006.245.08:02:00.50#ibcon#*before write, iclass 6, count 2 2006.245.08:02:00.50#ibcon#enter sib2, iclass 6, count 2 2006.245.08:02:00.50#ibcon#flushed, iclass 6, count 2 2006.245.08:02:00.50#ibcon#about to write, iclass 6, count 2 2006.245.08:02:00.50#ibcon#wrote, iclass 6, count 2 2006.245.08:02:00.50#ibcon#about to read 3, iclass 6, count 2 2006.245.08:02:00.53#ibcon#read 3, iclass 6, count 2 2006.245.08:02:00.53#ibcon#about to read 4, iclass 6, count 2 2006.245.08:02:00.53#ibcon#read 4, iclass 6, count 2 2006.245.08:02:00.53#ibcon#about to read 5, iclass 6, count 2 2006.245.08:02:00.53#ibcon#read 5, iclass 6, count 2 2006.245.08:02:00.53#ibcon#about to read 6, iclass 6, count 2 2006.245.08:02:00.53#ibcon#read 6, iclass 6, count 2 2006.245.08:02:00.53#ibcon#end of sib2, iclass 6, count 2 2006.245.08:02:00.53#ibcon#*after write, iclass 6, count 2 2006.245.08:02:00.53#ibcon#*before return 0, iclass 6, count 2 2006.245.08:02:00.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:00.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:00.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.08:02:00.53#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:00.53#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:00.65#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:00.65#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:00.65#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:02:00.65#ibcon#first serial, iclass 6, count 0 2006.245.08:02:00.65#ibcon#enter sib2, iclass 6, count 0 2006.245.08:02:00.65#ibcon#flushed, iclass 6, count 0 2006.245.08:02:00.65#ibcon#about to write, iclass 6, count 0 2006.245.08:02:00.65#ibcon#wrote, iclass 6, count 0 2006.245.08:02:00.65#ibcon#about to read 3, iclass 6, count 0 2006.245.08:02:00.67#ibcon#read 3, iclass 6, count 0 2006.245.08:02:00.67#ibcon#about to read 4, iclass 6, count 0 2006.245.08:02:00.67#ibcon#read 4, iclass 6, count 0 2006.245.08:02:00.67#ibcon#about to read 5, iclass 6, count 0 2006.245.08:02:00.67#ibcon#read 5, iclass 6, count 0 2006.245.08:02:00.67#ibcon#about to read 6, iclass 6, count 0 2006.245.08:02:00.67#ibcon#read 6, iclass 6, count 0 2006.245.08:02:00.67#ibcon#end of sib2, iclass 6, count 0 2006.245.08:02:00.67#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:02:00.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:02:00.67#ibcon#[25=USB\r\n] 2006.245.08:02:00.67#ibcon#*before write, iclass 6, count 0 2006.245.08:02:00.67#ibcon#enter sib2, iclass 6, count 0 2006.245.08:02:00.67#ibcon#flushed, iclass 6, count 0 2006.245.08:02:00.67#ibcon#about to write, iclass 6, count 0 2006.245.08:02:00.67#ibcon#wrote, iclass 6, count 0 2006.245.08:02:00.67#ibcon#about to read 3, iclass 6, count 0 2006.245.08:02:00.70#ibcon#read 3, iclass 6, count 0 2006.245.08:02:00.70#ibcon#about to read 4, iclass 6, count 0 2006.245.08:02:00.70#ibcon#read 4, iclass 6, count 0 2006.245.08:02:00.70#ibcon#about to read 5, iclass 6, count 0 2006.245.08:02:00.70#ibcon#read 5, iclass 6, count 0 2006.245.08:02:00.70#ibcon#about to read 6, iclass 6, count 0 2006.245.08:02:00.70#ibcon#read 6, iclass 6, count 0 2006.245.08:02:00.70#ibcon#end of sib2, iclass 6, count 0 2006.245.08:02:00.70#ibcon#*after write, iclass 6, count 0 2006.245.08:02:00.70#ibcon#*before return 0, iclass 6, count 0 2006.245.08:02:00.70#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:00.70#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:00.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:02:00.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:02:00.70$vc4f8/valo=3,672.99 2006.245.08:02:00.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.08:02:00.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.08:02:00.70#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:00.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:00.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:00.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:00.70#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:02:00.70#ibcon#first serial, iclass 10, count 0 2006.245.08:02:00.70#ibcon#enter sib2, iclass 10, count 0 2006.245.08:02:00.70#ibcon#flushed, iclass 10, count 0 2006.245.08:02:00.70#ibcon#about to write, iclass 10, count 0 2006.245.08:02:00.70#ibcon#wrote, iclass 10, count 0 2006.245.08:02:00.70#ibcon#about to read 3, iclass 10, count 0 2006.245.08:02:00.73#ibcon#read 3, iclass 10, count 0 2006.245.08:02:00.73#ibcon#about to read 4, iclass 10, count 0 2006.245.08:02:00.73#ibcon#read 4, iclass 10, count 0 2006.245.08:02:00.73#ibcon#about to read 5, iclass 10, count 0 2006.245.08:02:00.73#ibcon#read 5, iclass 10, count 0 2006.245.08:02:00.73#ibcon#about to read 6, iclass 10, count 0 2006.245.08:02:00.73#ibcon#read 6, iclass 10, count 0 2006.245.08:02:00.73#ibcon#end of sib2, iclass 10, count 0 2006.245.08:02:00.73#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:02:00.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:02:00.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:02:00.73#ibcon#*before write, iclass 10, count 0 2006.245.08:02:00.73#ibcon#enter sib2, iclass 10, count 0 2006.245.08:02:00.73#ibcon#flushed, iclass 10, count 0 2006.245.08:02:00.73#ibcon#about to write, iclass 10, count 0 2006.245.08:02:00.73#ibcon#wrote, iclass 10, count 0 2006.245.08:02:00.73#ibcon#about to read 3, iclass 10, count 0 2006.245.08:02:00.77#ibcon#read 3, iclass 10, count 0 2006.245.08:02:00.77#ibcon#about to read 4, iclass 10, count 0 2006.245.08:02:00.77#ibcon#read 4, iclass 10, count 0 2006.245.08:02:00.77#ibcon#about to read 5, iclass 10, count 0 2006.245.08:02:00.77#ibcon#read 5, iclass 10, count 0 2006.245.08:02:00.77#ibcon#about to read 6, iclass 10, count 0 2006.245.08:02:00.77#ibcon#read 6, iclass 10, count 0 2006.245.08:02:00.77#ibcon#end of sib2, iclass 10, count 0 2006.245.08:02:00.77#ibcon#*after write, iclass 10, count 0 2006.245.08:02:00.77#ibcon#*before return 0, iclass 10, count 0 2006.245.08:02:00.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:00.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:00.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:02:00.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:02:00.77$vc4f8/va=3,6 2006.245.08:02:00.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.08:02:00.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.08:02:00.77#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:00.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:00.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:00.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:00.82#ibcon#enter wrdev, iclass 12, count 2 2006.245.08:02:00.82#ibcon#first serial, iclass 12, count 2 2006.245.08:02:00.82#ibcon#enter sib2, iclass 12, count 2 2006.245.08:02:00.82#ibcon#flushed, iclass 12, count 2 2006.245.08:02:00.82#ibcon#about to write, iclass 12, count 2 2006.245.08:02:00.82#ibcon#wrote, iclass 12, count 2 2006.245.08:02:00.82#ibcon#about to read 3, iclass 12, count 2 2006.245.08:02:00.84#ibcon#read 3, iclass 12, count 2 2006.245.08:02:00.84#ibcon#about to read 4, iclass 12, count 2 2006.245.08:02:00.84#ibcon#read 4, iclass 12, count 2 2006.245.08:02:00.84#ibcon#about to read 5, iclass 12, count 2 2006.245.08:02:00.84#ibcon#read 5, iclass 12, count 2 2006.245.08:02:00.84#ibcon#about to read 6, iclass 12, count 2 2006.245.08:02:00.84#ibcon#read 6, iclass 12, count 2 2006.245.08:02:00.84#ibcon#end of sib2, iclass 12, count 2 2006.245.08:02:00.84#ibcon#*mode == 0, iclass 12, count 2 2006.245.08:02:00.84#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.08:02:00.84#ibcon#[25=AT03-06\r\n] 2006.245.08:02:00.84#ibcon#*before write, iclass 12, count 2 2006.245.08:02:00.84#ibcon#enter sib2, iclass 12, count 2 2006.245.08:02:00.84#ibcon#flushed, iclass 12, count 2 2006.245.08:02:00.84#ibcon#about to write, iclass 12, count 2 2006.245.08:02:00.84#ibcon#wrote, iclass 12, count 2 2006.245.08:02:00.84#ibcon#about to read 3, iclass 12, count 2 2006.245.08:02:00.87#ibcon#read 3, iclass 12, count 2 2006.245.08:02:00.87#ibcon#about to read 4, iclass 12, count 2 2006.245.08:02:00.87#ibcon#read 4, iclass 12, count 2 2006.245.08:02:00.87#ibcon#about to read 5, iclass 12, count 2 2006.245.08:02:00.87#ibcon#read 5, iclass 12, count 2 2006.245.08:02:00.87#ibcon#about to read 6, iclass 12, count 2 2006.245.08:02:00.87#ibcon#read 6, iclass 12, count 2 2006.245.08:02:00.87#ibcon#end of sib2, iclass 12, count 2 2006.245.08:02:00.87#ibcon#*after write, iclass 12, count 2 2006.245.08:02:00.87#ibcon#*before return 0, iclass 12, count 2 2006.245.08:02:00.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:00.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:00.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.08:02:00.87#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:00.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:00.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:00.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:00.99#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:02:00.99#ibcon#first serial, iclass 12, count 0 2006.245.08:02:00.99#ibcon#enter sib2, iclass 12, count 0 2006.245.08:02:00.99#ibcon#flushed, iclass 12, count 0 2006.245.08:02:00.99#ibcon#about to write, iclass 12, count 0 2006.245.08:02:00.99#ibcon#wrote, iclass 12, count 0 2006.245.08:02:00.99#ibcon#about to read 3, iclass 12, count 0 2006.245.08:02:01.01#ibcon#read 3, iclass 12, count 0 2006.245.08:02:01.01#ibcon#about to read 4, iclass 12, count 0 2006.245.08:02:01.01#ibcon#read 4, iclass 12, count 0 2006.245.08:02:01.01#ibcon#about to read 5, iclass 12, count 0 2006.245.08:02:01.01#ibcon#read 5, iclass 12, count 0 2006.245.08:02:01.01#ibcon#about to read 6, iclass 12, count 0 2006.245.08:02:01.01#ibcon#read 6, iclass 12, count 0 2006.245.08:02:01.01#ibcon#end of sib2, iclass 12, count 0 2006.245.08:02:01.01#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:02:01.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:02:01.01#ibcon#[25=USB\r\n] 2006.245.08:02:01.01#ibcon#*before write, iclass 12, count 0 2006.245.08:02:01.01#ibcon#enter sib2, iclass 12, count 0 2006.245.08:02:01.01#ibcon#flushed, iclass 12, count 0 2006.245.08:02:01.01#ibcon#about to write, iclass 12, count 0 2006.245.08:02:01.01#ibcon#wrote, iclass 12, count 0 2006.245.08:02:01.01#ibcon#about to read 3, iclass 12, count 0 2006.245.08:02:01.04#ibcon#read 3, iclass 12, count 0 2006.245.08:02:01.04#ibcon#about to read 4, iclass 12, count 0 2006.245.08:02:01.04#ibcon#read 4, iclass 12, count 0 2006.245.08:02:01.04#ibcon#about to read 5, iclass 12, count 0 2006.245.08:02:01.04#ibcon#read 5, iclass 12, count 0 2006.245.08:02:01.04#ibcon#about to read 6, iclass 12, count 0 2006.245.08:02:01.04#ibcon#read 6, iclass 12, count 0 2006.245.08:02:01.04#ibcon#end of sib2, iclass 12, count 0 2006.245.08:02:01.04#ibcon#*after write, iclass 12, count 0 2006.245.08:02:01.04#ibcon#*before return 0, iclass 12, count 0 2006.245.08:02:01.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:01.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:01.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:02:01.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:02:01.04$vc4f8/valo=4,832.99 2006.245.08:02:01.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.08:02:01.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.08:02:01.04#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:01.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:01.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:01.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:01.04#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:02:01.04#ibcon#first serial, iclass 14, count 0 2006.245.08:02:01.04#ibcon#enter sib2, iclass 14, count 0 2006.245.08:02:01.04#ibcon#flushed, iclass 14, count 0 2006.245.08:02:01.04#ibcon#about to write, iclass 14, count 0 2006.245.08:02:01.04#ibcon#wrote, iclass 14, count 0 2006.245.08:02:01.04#ibcon#about to read 3, iclass 14, count 0 2006.245.08:02:01.06#ibcon#read 3, iclass 14, count 0 2006.245.08:02:01.06#ibcon#about to read 4, iclass 14, count 0 2006.245.08:02:01.06#ibcon#read 4, iclass 14, count 0 2006.245.08:02:01.06#ibcon#about to read 5, iclass 14, count 0 2006.245.08:02:01.06#ibcon#read 5, iclass 14, count 0 2006.245.08:02:01.06#ibcon#about to read 6, iclass 14, count 0 2006.245.08:02:01.06#ibcon#read 6, iclass 14, count 0 2006.245.08:02:01.06#ibcon#end of sib2, iclass 14, count 0 2006.245.08:02:01.06#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:02:01.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:02:01.06#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:02:01.06#ibcon#*before write, iclass 14, count 0 2006.245.08:02:01.06#ibcon#enter sib2, iclass 14, count 0 2006.245.08:02:01.06#ibcon#flushed, iclass 14, count 0 2006.245.08:02:01.06#ibcon#about to write, iclass 14, count 0 2006.245.08:02:01.06#ibcon#wrote, iclass 14, count 0 2006.245.08:02:01.06#ibcon#about to read 3, iclass 14, count 0 2006.245.08:02:01.10#ibcon#read 3, iclass 14, count 0 2006.245.08:02:01.10#ibcon#about to read 4, iclass 14, count 0 2006.245.08:02:01.10#ibcon#read 4, iclass 14, count 0 2006.245.08:02:01.10#ibcon#about to read 5, iclass 14, count 0 2006.245.08:02:01.10#ibcon#read 5, iclass 14, count 0 2006.245.08:02:01.10#ibcon#about to read 6, iclass 14, count 0 2006.245.08:02:01.10#ibcon#read 6, iclass 14, count 0 2006.245.08:02:01.10#ibcon#end of sib2, iclass 14, count 0 2006.245.08:02:01.10#ibcon#*after write, iclass 14, count 0 2006.245.08:02:01.10#ibcon#*before return 0, iclass 14, count 0 2006.245.08:02:01.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:01.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:01.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:02:01.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:02:01.10$vc4f8/va=4,7 2006.245.08:02:01.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:02:01.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:02:01.10#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:01.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:01.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:01.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:01.17#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:02:01.17#ibcon#first serial, iclass 16, count 2 2006.245.08:02:01.17#ibcon#enter sib2, iclass 16, count 2 2006.245.08:02:01.17#ibcon#flushed, iclass 16, count 2 2006.245.08:02:01.17#ibcon#about to write, iclass 16, count 2 2006.245.08:02:01.17#ibcon#wrote, iclass 16, count 2 2006.245.08:02:01.17#ibcon#about to read 3, iclass 16, count 2 2006.245.08:02:01.18#ibcon#read 3, iclass 16, count 2 2006.245.08:02:01.18#ibcon#about to read 4, iclass 16, count 2 2006.245.08:02:01.18#ibcon#read 4, iclass 16, count 2 2006.245.08:02:01.18#ibcon#about to read 5, iclass 16, count 2 2006.245.08:02:01.18#ibcon#read 5, iclass 16, count 2 2006.245.08:02:01.18#ibcon#about to read 6, iclass 16, count 2 2006.245.08:02:01.18#ibcon#read 6, iclass 16, count 2 2006.245.08:02:01.18#ibcon#end of sib2, iclass 16, count 2 2006.245.08:02:01.18#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:02:01.18#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:02:01.18#ibcon#[25=AT04-07\r\n] 2006.245.08:02:01.18#ibcon#*before write, iclass 16, count 2 2006.245.08:02:01.18#ibcon#enter sib2, iclass 16, count 2 2006.245.08:02:01.18#ibcon#flushed, iclass 16, count 2 2006.245.08:02:01.18#ibcon#about to write, iclass 16, count 2 2006.245.08:02:01.18#ibcon#wrote, iclass 16, count 2 2006.245.08:02:01.18#ibcon#about to read 3, iclass 16, count 2 2006.245.08:02:01.21#ibcon#read 3, iclass 16, count 2 2006.245.08:02:01.21#ibcon#about to read 4, iclass 16, count 2 2006.245.08:02:01.21#ibcon#read 4, iclass 16, count 2 2006.245.08:02:01.21#ibcon#about to read 5, iclass 16, count 2 2006.245.08:02:01.21#ibcon#read 5, iclass 16, count 2 2006.245.08:02:01.21#ibcon#about to read 6, iclass 16, count 2 2006.245.08:02:01.21#ibcon#read 6, iclass 16, count 2 2006.245.08:02:01.21#ibcon#end of sib2, iclass 16, count 2 2006.245.08:02:01.21#ibcon#*after write, iclass 16, count 2 2006.245.08:02:01.21#ibcon#*before return 0, iclass 16, count 2 2006.245.08:02:01.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:01.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:01.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:02:01.21#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:01.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:01.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:01.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:01.33#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:02:01.33#ibcon#first serial, iclass 16, count 0 2006.245.08:02:01.33#ibcon#enter sib2, iclass 16, count 0 2006.245.08:02:01.33#ibcon#flushed, iclass 16, count 0 2006.245.08:02:01.33#ibcon#about to write, iclass 16, count 0 2006.245.08:02:01.33#ibcon#wrote, iclass 16, count 0 2006.245.08:02:01.33#ibcon#about to read 3, iclass 16, count 0 2006.245.08:02:01.35#ibcon#read 3, iclass 16, count 0 2006.245.08:02:01.35#ibcon#about to read 4, iclass 16, count 0 2006.245.08:02:01.35#ibcon#read 4, iclass 16, count 0 2006.245.08:02:01.35#ibcon#about to read 5, iclass 16, count 0 2006.245.08:02:01.35#ibcon#read 5, iclass 16, count 0 2006.245.08:02:01.35#ibcon#about to read 6, iclass 16, count 0 2006.245.08:02:01.35#ibcon#read 6, iclass 16, count 0 2006.245.08:02:01.35#ibcon#end of sib2, iclass 16, count 0 2006.245.08:02:01.35#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:02:01.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:02:01.35#ibcon#[25=USB\r\n] 2006.245.08:02:01.35#ibcon#*before write, iclass 16, count 0 2006.245.08:02:01.35#ibcon#enter sib2, iclass 16, count 0 2006.245.08:02:01.35#ibcon#flushed, iclass 16, count 0 2006.245.08:02:01.35#ibcon#about to write, iclass 16, count 0 2006.245.08:02:01.35#ibcon#wrote, iclass 16, count 0 2006.245.08:02:01.35#ibcon#about to read 3, iclass 16, count 0 2006.245.08:02:01.38#ibcon#read 3, iclass 16, count 0 2006.245.08:02:01.38#ibcon#about to read 4, iclass 16, count 0 2006.245.08:02:01.38#ibcon#read 4, iclass 16, count 0 2006.245.08:02:01.38#ibcon#about to read 5, iclass 16, count 0 2006.245.08:02:01.38#ibcon#read 5, iclass 16, count 0 2006.245.08:02:01.38#ibcon#about to read 6, iclass 16, count 0 2006.245.08:02:01.38#ibcon#read 6, iclass 16, count 0 2006.245.08:02:01.38#ibcon#end of sib2, iclass 16, count 0 2006.245.08:02:01.38#ibcon#*after write, iclass 16, count 0 2006.245.08:02:01.38#ibcon#*before return 0, iclass 16, count 0 2006.245.08:02:01.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:01.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:01.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:02:01.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:02:01.38$vc4f8/valo=5,652.99 2006.245.08:02:01.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.08:02:01.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.08:02:01.38#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:01.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:01.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:01.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:01.38#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:02:01.38#ibcon#first serial, iclass 18, count 0 2006.245.08:02:01.38#ibcon#enter sib2, iclass 18, count 0 2006.245.08:02:01.38#ibcon#flushed, iclass 18, count 0 2006.245.08:02:01.38#ibcon#about to write, iclass 18, count 0 2006.245.08:02:01.38#ibcon#wrote, iclass 18, count 0 2006.245.08:02:01.38#ibcon#about to read 3, iclass 18, count 0 2006.245.08:02:01.40#ibcon#read 3, iclass 18, count 0 2006.245.08:02:01.40#ibcon#about to read 4, iclass 18, count 0 2006.245.08:02:01.40#ibcon#read 4, iclass 18, count 0 2006.245.08:02:01.40#ibcon#about to read 5, iclass 18, count 0 2006.245.08:02:01.40#ibcon#read 5, iclass 18, count 0 2006.245.08:02:01.40#ibcon#about to read 6, iclass 18, count 0 2006.245.08:02:01.40#ibcon#read 6, iclass 18, count 0 2006.245.08:02:01.40#ibcon#end of sib2, iclass 18, count 0 2006.245.08:02:01.40#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:02:01.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:02:01.40#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:02:01.40#ibcon#*before write, iclass 18, count 0 2006.245.08:02:01.40#ibcon#enter sib2, iclass 18, count 0 2006.245.08:02:01.40#ibcon#flushed, iclass 18, count 0 2006.245.08:02:01.40#ibcon#about to write, iclass 18, count 0 2006.245.08:02:01.40#ibcon#wrote, iclass 18, count 0 2006.245.08:02:01.40#ibcon#about to read 3, iclass 18, count 0 2006.245.08:02:01.44#ibcon#read 3, iclass 18, count 0 2006.245.08:02:01.44#ibcon#about to read 4, iclass 18, count 0 2006.245.08:02:01.44#ibcon#read 4, iclass 18, count 0 2006.245.08:02:01.44#ibcon#about to read 5, iclass 18, count 0 2006.245.08:02:01.44#ibcon#read 5, iclass 18, count 0 2006.245.08:02:01.44#ibcon#about to read 6, iclass 18, count 0 2006.245.08:02:01.44#ibcon#read 6, iclass 18, count 0 2006.245.08:02:01.44#ibcon#end of sib2, iclass 18, count 0 2006.245.08:02:01.44#ibcon#*after write, iclass 18, count 0 2006.245.08:02:01.44#ibcon#*before return 0, iclass 18, count 0 2006.245.08:02:01.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:01.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:01.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:02:01.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:02:01.44$vc4f8/va=5,7 2006.245.08:02:01.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.08:02:01.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.08:02:01.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:01.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:01.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:01.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:01.50#ibcon#enter wrdev, iclass 20, count 2 2006.245.08:02:01.50#ibcon#first serial, iclass 20, count 2 2006.245.08:02:01.50#ibcon#enter sib2, iclass 20, count 2 2006.245.08:02:01.50#ibcon#flushed, iclass 20, count 2 2006.245.08:02:01.50#ibcon#about to write, iclass 20, count 2 2006.245.08:02:01.50#ibcon#wrote, iclass 20, count 2 2006.245.08:02:01.50#ibcon#about to read 3, iclass 20, count 2 2006.245.08:02:01.52#ibcon#read 3, iclass 20, count 2 2006.245.08:02:01.52#ibcon#about to read 4, iclass 20, count 2 2006.245.08:02:01.52#ibcon#read 4, iclass 20, count 2 2006.245.08:02:01.52#ibcon#about to read 5, iclass 20, count 2 2006.245.08:02:01.52#ibcon#read 5, iclass 20, count 2 2006.245.08:02:01.52#ibcon#about to read 6, iclass 20, count 2 2006.245.08:02:01.52#ibcon#read 6, iclass 20, count 2 2006.245.08:02:01.52#ibcon#end of sib2, iclass 20, count 2 2006.245.08:02:01.52#ibcon#*mode == 0, iclass 20, count 2 2006.245.08:02:01.52#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.08:02:01.52#ibcon#[25=AT05-07\r\n] 2006.245.08:02:01.52#ibcon#*before write, iclass 20, count 2 2006.245.08:02:01.52#ibcon#enter sib2, iclass 20, count 2 2006.245.08:02:01.52#ibcon#flushed, iclass 20, count 2 2006.245.08:02:01.52#ibcon#about to write, iclass 20, count 2 2006.245.08:02:01.52#ibcon#wrote, iclass 20, count 2 2006.245.08:02:01.52#ibcon#about to read 3, iclass 20, count 2 2006.245.08:02:01.55#ibcon#read 3, iclass 20, count 2 2006.245.08:02:01.55#ibcon#about to read 4, iclass 20, count 2 2006.245.08:02:01.55#ibcon#read 4, iclass 20, count 2 2006.245.08:02:01.55#ibcon#about to read 5, iclass 20, count 2 2006.245.08:02:01.55#ibcon#read 5, iclass 20, count 2 2006.245.08:02:01.55#ibcon#about to read 6, iclass 20, count 2 2006.245.08:02:01.55#ibcon#read 6, iclass 20, count 2 2006.245.08:02:01.55#ibcon#end of sib2, iclass 20, count 2 2006.245.08:02:01.55#ibcon#*after write, iclass 20, count 2 2006.245.08:02:01.55#ibcon#*before return 0, iclass 20, count 2 2006.245.08:02:01.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:01.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:01.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.08:02:01.55#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:01.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:01.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:01.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:01.67#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:02:01.67#ibcon#first serial, iclass 20, count 0 2006.245.08:02:01.67#ibcon#enter sib2, iclass 20, count 0 2006.245.08:02:01.67#ibcon#flushed, iclass 20, count 0 2006.245.08:02:01.67#ibcon#about to write, iclass 20, count 0 2006.245.08:02:01.67#ibcon#wrote, iclass 20, count 0 2006.245.08:02:01.67#ibcon#about to read 3, iclass 20, count 0 2006.245.08:02:01.69#ibcon#read 3, iclass 20, count 0 2006.245.08:02:01.69#ibcon#about to read 4, iclass 20, count 0 2006.245.08:02:01.69#ibcon#read 4, iclass 20, count 0 2006.245.08:02:01.69#ibcon#about to read 5, iclass 20, count 0 2006.245.08:02:01.69#ibcon#read 5, iclass 20, count 0 2006.245.08:02:01.69#ibcon#about to read 6, iclass 20, count 0 2006.245.08:02:01.69#ibcon#read 6, iclass 20, count 0 2006.245.08:02:01.69#ibcon#end of sib2, iclass 20, count 0 2006.245.08:02:01.69#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:02:01.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:02:01.69#ibcon#[25=USB\r\n] 2006.245.08:02:01.69#ibcon#*before write, iclass 20, count 0 2006.245.08:02:01.69#ibcon#enter sib2, iclass 20, count 0 2006.245.08:02:01.69#ibcon#flushed, iclass 20, count 0 2006.245.08:02:01.69#ibcon#about to write, iclass 20, count 0 2006.245.08:02:01.69#ibcon#wrote, iclass 20, count 0 2006.245.08:02:01.69#ibcon#about to read 3, iclass 20, count 0 2006.245.08:02:01.72#ibcon#read 3, iclass 20, count 0 2006.245.08:02:01.72#ibcon#about to read 4, iclass 20, count 0 2006.245.08:02:01.72#ibcon#read 4, iclass 20, count 0 2006.245.08:02:01.72#ibcon#about to read 5, iclass 20, count 0 2006.245.08:02:01.72#ibcon#read 5, iclass 20, count 0 2006.245.08:02:01.72#ibcon#about to read 6, iclass 20, count 0 2006.245.08:02:01.72#ibcon#read 6, iclass 20, count 0 2006.245.08:02:01.72#ibcon#end of sib2, iclass 20, count 0 2006.245.08:02:01.72#ibcon#*after write, iclass 20, count 0 2006.245.08:02:01.72#ibcon#*before return 0, iclass 20, count 0 2006.245.08:02:01.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:01.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:01.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:02:01.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:02:01.72$vc4f8/valo=6,772.99 2006.245.08:02:01.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:02:01.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:02:01.72#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:01.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:01.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:01.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:01.72#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:02:01.72#ibcon#first serial, iclass 22, count 0 2006.245.08:02:01.72#ibcon#enter sib2, iclass 22, count 0 2006.245.08:02:01.72#ibcon#flushed, iclass 22, count 0 2006.245.08:02:01.72#ibcon#about to write, iclass 22, count 0 2006.245.08:02:01.72#ibcon#wrote, iclass 22, count 0 2006.245.08:02:01.72#ibcon#about to read 3, iclass 22, count 0 2006.245.08:02:01.75#ibcon#read 3, iclass 22, count 0 2006.245.08:02:01.75#ibcon#about to read 4, iclass 22, count 0 2006.245.08:02:01.75#ibcon#read 4, iclass 22, count 0 2006.245.08:02:01.75#ibcon#about to read 5, iclass 22, count 0 2006.245.08:02:01.75#ibcon#read 5, iclass 22, count 0 2006.245.08:02:01.75#ibcon#about to read 6, iclass 22, count 0 2006.245.08:02:01.75#ibcon#read 6, iclass 22, count 0 2006.245.08:02:01.75#ibcon#end of sib2, iclass 22, count 0 2006.245.08:02:01.75#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:02:01.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:02:01.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:02:01.75#ibcon#*before write, iclass 22, count 0 2006.245.08:02:01.75#ibcon#enter sib2, iclass 22, count 0 2006.245.08:02:01.75#ibcon#flushed, iclass 22, count 0 2006.245.08:02:01.75#ibcon#about to write, iclass 22, count 0 2006.245.08:02:01.75#ibcon#wrote, iclass 22, count 0 2006.245.08:02:01.75#ibcon#about to read 3, iclass 22, count 0 2006.245.08:02:01.79#ibcon#read 3, iclass 22, count 0 2006.245.08:02:01.79#ibcon#about to read 4, iclass 22, count 0 2006.245.08:02:01.79#ibcon#read 4, iclass 22, count 0 2006.245.08:02:01.79#ibcon#about to read 5, iclass 22, count 0 2006.245.08:02:01.79#ibcon#read 5, iclass 22, count 0 2006.245.08:02:01.79#ibcon#about to read 6, iclass 22, count 0 2006.245.08:02:01.79#ibcon#read 6, iclass 22, count 0 2006.245.08:02:01.79#ibcon#end of sib2, iclass 22, count 0 2006.245.08:02:01.79#ibcon#*after write, iclass 22, count 0 2006.245.08:02:01.79#ibcon#*before return 0, iclass 22, count 0 2006.245.08:02:01.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:01.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:01.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:02:01.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:02:01.79$vc4f8/va=6,7 2006.245.08:02:01.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.08:02:01.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.08:02:01.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:01.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:02:01.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:02:01.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:02:01.84#ibcon#enter wrdev, iclass 24, count 2 2006.245.08:02:01.84#ibcon#first serial, iclass 24, count 2 2006.245.08:02:01.84#ibcon#enter sib2, iclass 24, count 2 2006.245.08:02:01.84#ibcon#flushed, iclass 24, count 2 2006.245.08:02:01.84#ibcon#about to write, iclass 24, count 2 2006.245.08:02:01.84#ibcon#wrote, iclass 24, count 2 2006.245.08:02:01.84#ibcon#about to read 3, iclass 24, count 2 2006.245.08:02:01.86#ibcon#read 3, iclass 24, count 2 2006.245.08:02:01.86#ibcon#about to read 4, iclass 24, count 2 2006.245.08:02:01.86#ibcon#read 4, iclass 24, count 2 2006.245.08:02:01.86#ibcon#about to read 5, iclass 24, count 2 2006.245.08:02:01.86#ibcon#read 5, iclass 24, count 2 2006.245.08:02:01.86#ibcon#about to read 6, iclass 24, count 2 2006.245.08:02:01.86#ibcon#read 6, iclass 24, count 2 2006.245.08:02:01.86#ibcon#end of sib2, iclass 24, count 2 2006.245.08:02:01.86#ibcon#*mode == 0, iclass 24, count 2 2006.245.08:02:01.86#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.08:02:01.86#ibcon#[25=AT06-07\r\n] 2006.245.08:02:01.86#ibcon#*before write, iclass 24, count 2 2006.245.08:02:01.86#ibcon#enter sib2, iclass 24, count 2 2006.245.08:02:01.86#ibcon#flushed, iclass 24, count 2 2006.245.08:02:01.86#ibcon#about to write, iclass 24, count 2 2006.245.08:02:01.86#ibcon#wrote, iclass 24, count 2 2006.245.08:02:01.86#ibcon#about to read 3, iclass 24, count 2 2006.245.08:02:01.89#ibcon#read 3, iclass 24, count 2 2006.245.08:02:01.89#ibcon#about to read 4, iclass 24, count 2 2006.245.08:02:01.89#ibcon#read 4, iclass 24, count 2 2006.245.08:02:01.89#ibcon#about to read 5, iclass 24, count 2 2006.245.08:02:01.89#ibcon#read 5, iclass 24, count 2 2006.245.08:02:01.89#ibcon#about to read 6, iclass 24, count 2 2006.245.08:02:01.89#ibcon#read 6, iclass 24, count 2 2006.245.08:02:01.89#ibcon#end of sib2, iclass 24, count 2 2006.245.08:02:01.89#ibcon#*after write, iclass 24, count 2 2006.245.08:02:01.89#ibcon#*before return 0, iclass 24, count 2 2006.245.08:02:01.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:02:01.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:02:01.89#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.08:02:01.89#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:01.89#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:02:02.01#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:02:02.01#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:02:02.01#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:02:02.01#ibcon#first serial, iclass 24, count 0 2006.245.08:02:02.01#ibcon#enter sib2, iclass 24, count 0 2006.245.08:02:02.01#ibcon#flushed, iclass 24, count 0 2006.245.08:02:02.01#ibcon#about to write, iclass 24, count 0 2006.245.08:02:02.01#ibcon#wrote, iclass 24, count 0 2006.245.08:02:02.01#ibcon#about to read 3, iclass 24, count 0 2006.245.08:02:02.03#ibcon#read 3, iclass 24, count 0 2006.245.08:02:02.03#ibcon#about to read 4, iclass 24, count 0 2006.245.08:02:02.03#ibcon#read 4, iclass 24, count 0 2006.245.08:02:02.03#ibcon#about to read 5, iclass 24, count 0 2006.245.08:02:02.03#ibcon#read 5, iclass 24, count 0 2006.245.08:02:02.03#ibcon#about to read 6, iclass 24, count 0 2006.245.08:02:02.03#ibcon#read 6, iclass 24, count 0 2006.245.08:02:02.03#ibcon#end of sib2, iclass 24, count 0 2006.245.08:02:02.03#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:02:02.03#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:02:02.03#ibcon#[25=USB\r\n] 2006.245.08:02:02.03#ibcon#*before write, iclass 24, count 0 2006.245.08:02:02.03#ibcon#enter sib2, iclass 24, count 0 2006.245.08:02:02.03#ibcon#flushed, iclass 24, count 0 2006.245.08:02:02.03#ibcon#about to write, iclass 24, count 0 2006.245.08:02:02.03#ibcon#wrote, iclass 24, count 0 2006.245.08:02:02.03#ibcon#about to read 3, iclass 24, count 0 2006.245.08:02:02.06#ibcon#read 3, iclass 24, count 0 2006.245.08:02:02.06#ibcon#about to read 4, iclass 24, count 0 2006.245.08:02:02.06#ibcon#read 4, iclass 24, count 0 2006.245.08:02:02.06#ibcon#about to read 5, iclass 24, count 0 2006.245.08:02:02.06#ibcon#read 5, iclass 24, count 0 2006.245.08:02:02.06#ibcon#about to read 6, iclass 24, count 0 2006.245.08:02:02.06#ibcon#read 6, iclass 24, count 0 2006.245.08:02:02.06#ibcon#end of sib2, iclass 24, count 0 2006.245.08:02:02.06#ibcon#*after write, iclass 24, count 0 2006.245.08:02:02.06#ibcon#*before return 0, iclass 24, count 0 2006.245.08:02:02.06#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:02:02.06#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:02:02.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:02:02.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:02:02.06$vc4f8/valo=7,832.99 2006.245.08:02:02.06#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.08:02:02.06#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.08:02:02.06#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:02.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:02:02.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:02:02.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:02:02.06#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:02:02.06#ibcon#first serial, iclass 26, count 0 2006.245.08:02:02.06#ibcon#enter sib2, iclass 26, count 0 2006.245.08:02:02.06#ibcon#flushed, iclass 26, count 0 2006.245.08:02:02.06#ibcon#about to write, iclass 26, count 0 2006.245.08:02:02.06#ibcon#wrote, iclass 26, count 0 2006.245.08:02:02.06#ibcon#about to read 3, iclass 26, count 0 2006.245.08:02:02.08#ibcon#read 3, iclass 26, count 0 2006.245.08:02:02.08#ibcon#about to read 4, iclass 26, count 0 2006.245.08:02:02.08#ibcon#read 4, iclass 26, count 0 2006.245.08:02:02.08#ibcon#about to read 5, iclass 26, count 0 2006.245.08:02:02.08#ibcon#read 5, iclass 26, count 0 2006.245.08:02:02.08#ibcon#about to read 6, iclass 26, count 0 2006.245.08:02:02.08#ibcon#read 6, iclass 26, count 0 2006.245.08:02:02.08#ibcon#end of sib2, iclass 26, count 0 2006.245.08:02:02.08#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:02:02.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:02:02.08#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:02:02.08#ibcon#*before write, iclass 26, count 0 2006.245.08:02:02.08#ibcon#enter sib2, iclass 26, count 0 2006.245.08:02:02.08#ibcon#flushed, iclass 26, count 0 2006.245.08:02:02.08#ibcon#about to write, iclass 26, count 0 2006.245.08:02:02.08#ibcon#wrote, iclass 26, count 0 2006.245.08:02:02.08#ibcon#about to read 3, iclass 26, count 0 2006.245.08:02:02.12#ibcon#read 3, iclass 26, count 0 2006.245.08:02:02.12#ibcon#about to read 4, iclass 26, count 0 2006.245.08:02:02.12#ibcon#read 4, iclass 26, count 0 2006.245.08:02:02.12#ibcon#about to read 5, iclass 26, count 0 2006.245.08:02:02.12#ibcon#read 5, iclass 26, count 0 2006.245.08:02:02.12#ibcon#about to read 6, iclass 26, count 0 2006.245.08:02:02.12#ibcon#read 6, iclass 26, count 0 2006.245.08:02:02.12#ibcon#end of sib2, iclass 26, count 0 2006.245.08:02:02.12#ibcon#*after write, iclass 26, count 0 2006.245.08:02:02.12#ibcon#*before return 0, iclass 26, count 0 2006.245.08:02:02.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:02:02.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:02:02.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:02:02.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:02:02.12$vc4f8/va=7,7 2006.245.08:02:02.12#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.08:02:02.12#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.08:02:02.12#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:02.12#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:02:02.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:02:02.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:02:02.18#ibcon#enter wrdev, iclass 28, count 2 2006.245.08:02:02.18#ibcon#first serial, iclass 28, count 2 2006.245.08:02:02.18#ibcon#enter sib2, iclass 28, count 2 2006.245.08:02:02.18#ibcon#flushed, iclass 28, count 2 2006.245.08:02:02.18#ibcon#about to write, iclass 28, count 2 2006.245.08:02:02.18#ibcon#wrote, iclass 28, count 2 2006.245.08:02:02.18#ibcon#about to read 3, iclass 28, count 2 2006.245.08:02:02.20#ibcon#read 3, iclass 28, count 2 2006.245.08:02:02.20#ibcon#about to read 4, iclass 28, count 2 2006.245.08:02:02.20#ibcon#read 4, iclass 28, count 2 2006.245.08:02:02.20#ibcon#about to read 5, iclass 28, count 2 2006.245.08:02:02.20#ibcon#read 5, iclass 28, count 2 2006.245.08:02:02.20#ibcon#about to read 6, iclass 28, count 2 2006.245.08:02:02.20#ibcon#read 6, iclass 28, count 2 2006.245.08:02:02.20#ibcon#end of sib2, iclass 28, count 2 2006.245.08:02:02.20#ibcon#*mode == 0, iclass 28, count 2 2006.245.08:02:02.20#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.08:02:02.20#ibcon#[25=AT07-07\r\n] 2006.245.08:02:02.20#ibcon#*before write, iclass 28, count 2 2006.245.08:02:02.20#ibcon#enter sib2, iclass 28, count 2 2006.245.08:02:02.20#ibcon#flushed, iclass 28, count 2 2006.245.08:02:02.20#ibcon#about to write, iclass 28, count 2 2006.245.08:02:02.20#ibcon#wrote, iclass 28, count 2 2006.245.08:02:02.20#ibcon#about to read 3, iclass 28, count 2 2006.245.08:02:02.23#ibcon#read 3, iclass 28, count 2 2006.245.08:02:02.23#ibcon#about to read 4, iclass 28, count 2 2006.245.08:02:02.23#ibcon#read 4, iclass 28, count 2 2006.245.08:02:02.23#ibcon#about to read 5, iclass 28, count 2 2006.245.08:02:02.23#ibcon#read 5, iclass 28, count 2 2006.245.08:02:02.23#ibcon#about to read 6, iclass 28, count 2 2006.245.08:02:02.23#ibcon#read 6, iclass 28, count 2 2006.245.08:02:02.23#ibcon#end of sib2, iclass 28, count 2 2006.245.08:02:02.23#ibcon#*after write, iclass 28, count 2 2006.245.08:02:02.23#ibcon#*before return 0, iclass 28, count 2 2006.245.08:02:02.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:02:02.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:02:02.23#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.08:02:02.23#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:02.23#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:02:02.35#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:02:02.35#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:02:02.35#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:02:02.35#ibcon#first serial, iclass 28, count 0 2006.245.08:02:02.35#ibcon#enter sib2, iclass 28, count 0 2006.245.08:02:02.35#ibcon#flushed, iclass 28, count 0 2006.245.08:02:02.35#ibcon#about to write, iclass 28, count 0 2006.245.08:02:02.35#ibcon#wrote, iclass 28, count 0 2006.245.08:02:02.35#ibcon#about to read 3, iclass 28, count 0 2006.245.08:02:02.37#ibcon#read 3, iclass 28, count 0 2006.245.08:02:02.37#ibcon#about to read 4, iclass 28, count 0 2006.245.08:02:02.37#ibcon#read 4, iclass 28, count 0 2006.245.08:02:02.37#ibcon#about to read 5, iclass 28, count 0 2006.245.08:02:02.37#ibcon#read 5, iclass 28, count 0 2006.245.08:02:02.37#ibcon#about to read 6, iclass 28, count 0 2006.245.08:02:02.37#ibcon#read 6, iclass 28, count 0 2006.245.08:02:02.37#ibcon#end of sib2, iclass 28, count 0 2006.245.08:02:02.37#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:02:02.37#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:02:02.37#ibcon#[25=USB\r\n] 2006.245.08:02:02.37#ibcon#*before write, iclass 28, count 0 2006.245.08:02:02.37#ibcon#enter sib2, iclass 28, count 0 2006.245.08:02:02.37#ibcon#flushed, iclass 28, count 0 2006.245.08:02:02.37#ibcon#about to write, iclass 28, count 0 2006.245.08:02:02.37#ibcon#wrote, iclass 28, count 0 2006.245.08:02:02.37#ibcon#about to read 3, iclass 28, count 0 2006.245.08:02:02.40#ibcon#read 3, iclass 28, count 0 2006.245.08:02:02.40#ibcon#about to read 4, iclass 28, count 0 2006.245.08:02:02.40#ibcon#read 4, iclass 28, count 0 2006.245.08:02:02.40#ibcon#about to read 5, iclass 28, count 0 2006.245.08:02:02.40#ibcon#read 5, iclass 28, count 0 2006.245.08:02:02.40#ibcon#about to read 6, iclass 28, count 0 2006.245.08:02:02.40#ibcon#read 6, iclass 28, count 0 2006.245.08:02:02.40#ibcon#end of sib2, iclass 28, count 0 2006.245.08:02:02.40#ibcon#*after write, iclass 28, count 0 2006.245.08:02:02.40#ibcon#*before return 0, iclass 28, count 0 2006.245.08:02:02.40#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:02:02.40#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:02:02.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:02:02.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:02:02.40$vc4f8/valo=8,852.99 2006.245.08:02:02.40#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.08:02:02.40#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.08:02:02.40#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:02.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:02:02.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:02:02.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:02:02.40#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:02:02.40#ibcon#first serial, iclass 30, count 0 2006.245.08:02:02.40#ibcon#enter sib2, iclass 30, count 0 2006.245.08:02:02.40#ibcon#flushed, iclass 30, count 0 2006.245.08:02:02.40#ibcon#about to write, iclass 30, count 0 2006.245.08:02:02.40#ibcon#wrote, iclass 30, count 0 2006.245.08:02:02.40#ibcon#about to read 3, iclass 30, count 0 2006.245.08:02:02.43#ibcon#read 3, iclass 30, count 0 2006.245.08:02:02.43#ibcon#about to read 4, iclass 30, count 0 2006.245.08:02:02.43#ibcon#read 4, iclass 30, count 0 2006.245.08:02:02.43#ibcon#about to read 5, iclass 30, count 0 2006.245.08:02:02.43#ibcon#read 5, iclass 30, count 0 2006.245.08:02:02.43#ibcon#about to read 6, iclass 30, count 0 2006.245.08:02:02.43#ibcon#read 6, iclass 30, count 0 2006.245.08:02:02.43#ibcon#end of sib2, iclass 30, count 0 2006.245.08:02:02.43#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:02:02.43#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:02:02.43#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:02:02.43#ibcon#*before write, iclass 30, count 0 2006.245.08:02:02.43#ibcon#enter sib2, iclass 30, count 0 2006.245.08:02:02.43#ibcon#flushed, iclass 30, count 0 2006.245.08:02:02.43#ibcon#about to write, iclass 30, count 0 2006.245.08:02:02.43#ibcon#wrote, iclass 30, count 0 2006.245.08:02:02.43#ibcon#about to read 3, iclass 30, count 0 2006.245.08:02:02.47#ibcon#read 3, iclass 30, count 0 2006.245.08:02:02.47#ibcon#about to read 4, iclass 30, count 0 2006.245.08:02:02.47#ibcon#read 4, iclass 30, count 0 2006.245.08:02:02.47#ibcon#about to read 5, iclass 30, count 0 2006.245.08:02:02.47#ibcon#read 5, iclass 30, count 0 2006.245.08:02:02.47#ibcon#about to read 6, iclass 30, count 0 2006.245.08:02:02.47#ibcon#read 6, iclass 30, count 0 2006.245.08:02:02.47#ibcon#end of sib2, iclass 30, count 0 2006.245.08:02:02.47#ibcon#*after write, iclass 30, count 0 2006.245.08:02:02.47#ibcon#*before return 0, iclass 30, count 0 2006.245.08:02:02.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:02:02.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:02:02.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:02:02.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:02:02.47$vc4f8/va=8,8 2006.245.08:02:02.47#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.08:02:02.47#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.08:02:02.47#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:02.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:02:02.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:02:02.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:02:02.52#ibcon#enter wrdev, iclass 32, count 2 2006.245.08:02:02.52#ibcon#first serial, iclass 32, count 2 2006.245.08:02:02.52#ibcon#enter sib2, iclass 32, count 2 2006.245.08:02:02.52#ibcon#flushed, iclass 32, count 2 2006.245.08:02:02.52#ibcon#about to write, iclass 32, count 2 2006.245.08:02:02.52#ibcon#wrote, iclass 32, count 2 2006.245.08:02:02.52#ibcon#about to read 3, iclass 32, count 2 2006.245.08:02:02.54#ibcon#read 3, iclass 32, count 2 2006.245.08:02:02.54#ibcon#about to read 4, iclass 32, count 2 2006.245.08:02:02.54#ibcon#read 4, iclass 32, count 2 2006.245.08:02:02.54#ibcon#about to read 5, iclass 32, count 2 2006.245.08:02:02.54#ibcon#read 5, iclass 32, count 2 2006.245.08:02:02.54#ibcon#about to read 6, iclass 32, count 2 2006.245.08:02:02.54#ibcon#read 6, iclass 32, count 2 2006.245.08:02:02.54#ibcon#end of sib2, iclass 32, count 2 2006.245.08:02:02.54#ibcon#*mode == 0, iclass 32, count 2 2006.245.08:02:02.54#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.08:02:02.54#ibcon#[25=AT08-08\r\n] 2006.245.08:02:02.54#ibcon#*before write, iclass 32, count 2 2006.245.08:02:02.54#ibcon#enter sib2, iclass 32, count 2 2006.245.08:02:02.54#ibcon#flushed, iclass 32, count 2 2006.245.08:02:02.54#ibcon#about to write, iclass 32, count 2 2006.245.08:02:02.54#ibcon#wrote, iclass 32, count 2 2006.245.08:02:02.54#ibcon#about to read 3, iclass 32, count 2 2006.245.08:02:02.57#ibcon#read 3, iclass 32, count 2 2006.245.08:02:02.57#ibcon#about to read 4, iclass 32, count 2 2006.245.08:02:02.57#ibcon#read 4, iclass 32, count 2 2006.245.08:02:02.57#ibcon#about to read 5, iclass 32, count 2 2006.245.08:02:02.57#ibcon#read 5, iclass 32, count 2 2006.245.08:02:02.57#ibcon#about to read 6, iclass 32, count 2 2006.245.08:02:02.57#ibcon#read 6, iclass 32, count 2 2006.245.08:02:02.57#ibcon#end of sib2, iclass 32, count 2 2006.245.08:02:02.57#ibcon#*after write, iclass 32, count 2 2006.245.08:02:02.57#ibcon#*before return 0, iclass 32, count 2 2006.245.08:02:02.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:02:02.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:02:02.57#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.08:02:02.57#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:02.57#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:02:02.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:02:02.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:02:02.69#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:02:02.69#ibcon#first serial, iclass 32, count 0 2006.245.08:02:02.69#ibcon#enter sib2, iclass 32, count 0 2006.245.08:02:02.69#ibcon#flushed, iclass 32, count 0 2006.245.08:02:02.69#ibcon#about to write, iclass 32, count 0 2006.245.08:02:02.69#ibcon#wrote, iclass 32, count 0 2006.245.08:02:02.69#ibcon#about to read 3, iclass 32, count 0 2006.245.08:02:02.71#ibcon#read 3, iclass 32, count 0 2006.245.08:02:02.71#ibcon#about to read 4, iclass 32, count 0 2006.245.08:02:02.71#ibcon#read 4, iclass 32, count 0 2006.245.08:02:02.71#ibcon#about to read 5, iclass 32, count 0 2006.245.08:02:02.71#ibcon#read 5, iclass 32, count 0 2006.245.08:02:02.71#ibcon#about to read 6, iclass 32, count 0 2006.245.08:02:02.71#ibcon#read 6, iclass 32, count 0 2006.245.08:02:02.71#ibcon#end of sib2, iclass 32, count 0 2006.245.08:02:02.71#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:02:02.71#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:02:02.71#ibcon#[25=USB\r\n] 2006.245.08:02:02.71#ibcon#*before write, iclass 32, count 0 2006.245.08:02:02.71#ibcon#enter sib2, iclass 32, count 0 2006.245.08:02:02.71#ibcon#flushed, iclass 32, count 0 2006.245.08:02:02.71#ibcon#about to write, iclass 32, count 0 2006.245.08:02:02.71#ibcon#wrote, iclass 32, count 0 2006.245.08:02:02.71#ibcon#about to read 3, iclass 32, count 0 2006.245.08:02:02.74#ibcon#read 3, iclass 32, count 0 2006.245.08:02:02.74#ibcon#about to read 4, iclass 32, count 0 2006.245.08:02:02.74#ibcon#read 4, iclass 32, count 0 2006.245.08:02:02.74#ibcon#about to read 5, iclass 32, count 0 2006.245.08:02:02.74#ibcon#read 5, iclass 32, count 0 2006.245.08:02:02.74#ibcon#about to read 6, iclass 32, count 0 2006.245.08:02:02.74#ibcon#read 6, iclass 32, count 0 2006.245.08:02:02.74#ibcon#end of sib2, iclass 32, count 0 2006.245.08:02:02.74#ibcon#*after write, iclass 32, count 0 2006.245.08:02:02.74#ibcon#*before return 0, iclass 32, count 0 2006.245.08:02:02.74#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:02:02.74#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:02:02.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:02:02.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:02:02.74$vc4f8/vblo=1,632.99 2006.245.08:02:02.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.08:02:02.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.08:02:02.74#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:02.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:02:02.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:02:02.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:02:02.74#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:02:02.74#ibcon#first serial, iclass 34, count 0 2006.245.08:02:02.74#ibcon#enter sib2, iclass 34, count 0 2006.245.08:02:02.74#ibcon#flushed, iclass 34, count 0 2006.245.08:02:02.74#ibcon#about to write, iclass 34, count 0 2006.245.08:02:02.74#ibcon#wrote, iclass 34, count 0 2006.245.08:02:02.74#ibcon#about to read 3, iclass 34, count 0 2006.245.08:02:02.76#ibcon#read 3, iclass 34, count 0 2006.245.08:02:02.76#ibcon#about to read 4, iclass 34, count 0 2006.245.08:02:02.76#ibcon#read 4, iclass 34, count 0 2006.245.08:02:02.76#ibcon#about to read 5, iclass 34, count 0 2006.245.08:02:02.76#ibcon#read 5, iclass 34, count 0 2006.245.08:02:02.76#ibcon#about to read 6, iclass 34, count 0 2006.245.08:02:02.76#ibcon#read 6, iclass 34, count 0 2006.245.08:02:02.76#ibcon#end of sib2, iclass 34, count 0 2006.245.08:02:02.76#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:02:02.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:02:02.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:02:02.76#ibcon#*before write, iclass 34, count 0 2006.245.08:02:02.76#ibcon#enter sib2, iclass 34, count 0 2006.245.08:02:02.76#ibcon#flushed, iclass 34, count 0 2006.245.08:02:02.76#ibcon#about to write, iclass 34, count 0 2006.245.08:02:02.76#ibcon#wrote, iclass 34, count 0 2006.245.08:02:02.76#ibcon#about to read 3, iclass 34, count 0 2006.245.08:02:02.80#ibcon#read 3, iclass 34, count 0 2006.245.08:02:02.80#ibcon#about to read 4, iclass 34, count 0 2006.245.08:02:02.80#ibcon#read 4, iclass 34, count 0 2006.245.08:02:02.80#ibcon#about to read 5, iclass 34, count 0 2006.245.08:02:02.80#ibcon#read 5, iclass 34, count 0 2006.245.08:02:02.80#ibcon#about to read 6, iclass 34, count 0 2006.245.08:02:02.80#ibcon#read 6, iclass 34, count 0 2006.245.08:02:02.80#ibcon#end of sib2, iclass 34, count 0 2006.245.08:02:02.80#ibcon#*after write, iclass 34, count 0 2006.245.08:02:02.80#ibcon#*before return 0, iclass 34, count 0 2006.245.08:02:02.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:02:02.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:02:02.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:02:02.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:02:02.80$vc4f8/vb=1,4 2006.245.08:02:02.80#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.08:02:02.80#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.08:02:02.80#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:02.80#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:02:02.80#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:02:02.80#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:02:02.80#ibcon#enter wrdev, iclass 36, count 2 2006.245.08:02:02.80#ibcon#first serial, iclass 36, count 2 2006.245.08:02:02.80#ibcon#enter sib2, iclass 36, count 2 2006.245.08:02:02.80#ibcon#flushed, iclass 36, count 2 2006.245.08:02:02.80#ibcon#about to write, iclass 36, count 2 2006.245.08:02:02.80#ibcon#wrote, iclass 36, count 2 2006.245.08:02:02.80#ibcon#about to read 3, iclass 36, count 2 2006.245.08:02:02.82#ibcon#read 3, iclass 36, count 2 2006.245.08:02:02.82#ibcon#about to read 4, iclass 36, count 2 2006.245.08:02:02.82#ibcon#read 4, iclass 36, count 2 2006.245.08:02:02.82#ibcon#about to read 5, iclass 36, count 2 2006.245.08:02:02.82#ibcon#read 5, iclass 36, count 2 2006.245.08:02:02.82#ibcon#about to read 6, iclass 36, count 2 2006.245.08:02:02.82#ibcon#read 6, iclass 36, count 2 2006.245.08:02:02.82#ibcon#end of sib2, iclass 36, count 2 2006.245.08:02:02.82#ibcon#*mode == 0, iclass 36, count 2 2006.245.08:02:02.82#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.08:02:02.82#ibcon#[27=AT01-04\r\n] 2006.245.08:02:02.82#ibcon#*before write, iclass 36, count 2 2006.245.08:02:02.82#ibcon#enter sib2, iclass 36, count 2 2006.245.08:02:02.82#ibcon#flushed, iclass 36, count 2 2006.245.08:02:02.82#ibcon#about to write, iclass 36, count 2 2006.245.08:02:02.82#ibcon#wrote, iclass 36, count 2 2006.245.08:02:02.82#ibcon#about to read 3, iclass 36, count 2 2006.245.08:02:02.85#ibcon#read 3, iclass 36, count 2 2006.245.08:02:02.85#ibcon#about to read 4, iclass 36, count 2 2006.245.08:02:02.85#ibcon#read 4, iclass 36, count 2 2006.245.08:02:02.85#ibcon#about to read 5, iclass 36, count 2 2006.245.08:02:02.85#ibcon#read 5, iclass 36, count 2 2006.245.08:02:02.85#ibcon#about to read 6, iclass 36, count 2 2006.245.08:02:02.85#ibcon#read 6, iclass 36, count 2 2006.245.08:02:02.85#ibcon#end of sib2, iclass 36, count 2 2006.245.08:02:02.85#ibcon#*after write, iclass 36, count 2 2006.245.08:02:02.85#ibcon#*before return 0, iclass 36, count 2 2006.245.08:02:02.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:02:02.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:02:02.85#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.08:02:02.85#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:02.85#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:02:02.97#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:02:02.97#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:02:02.97#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:02:02.97#ibcon#first serial, iclass 36, count 0 2006.245.08:02:02.97#ibcon#enter sib2, iclass 36, count 0 2006.245.08:02:02.97#ibcon#flushed, iclass 36, count 0 2006.245.08:02:02.97#ibcon#about to write, iclass 36, count 0 2006.245.08:02:02.97#ibcon#wrote, iclass 36, count 0 2006.245.08:02:02.97#ibcon#about to read 3, iclass 36, count 0 2006.245.08:02:02.99#ibcon#read 3, iclass 36, count 0 2006.245.08:02:02.99#ibcon#about to read 4, iclass 36, count 0 2006.245.08:02:02.99#ibcon#read 4, iclass 36, count 0 2006.245.08:02:02.99#ibcon#about to read 5, iclass 36, count 0 2006.245.08:02:02.99#ibcon#read 5, iclass 36, count 0 2006.245.08:02:02.99#ibcon#about to read 6, iclass 36, count 0 2006.245.08:02:02.99#ibcon#read 6, iclass 36, count 0 2006.245.08:02:02.99#ibcon#end of sib2, iclass 36, count 0 2006.245.08:02:02.99#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:02:02.99#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:02:02.99#ibcon#[27=USB\r\n] 2006.245.08:02:02.99#ibcon#*before write, iclass 36, count 0 2006.245.08:02:02.99#ibcon#enter sib2, iclass 36, count 0 2006.245.08:02:02.99#ibcon#flushed, iclass 36, count 0 2006.245.08:02:02.99#ibcon#about to write, iclass 36, count 0 2006.245.08:02:02.99#ibcon#wrote, iclass 36, count 0 2006.245.08:02:02.99#ibcon#about to read 3, iclass 36, count 0 2006.245.08:02:03.02#ibcon#read 3, iclass 36, count 0 2006.245.08:02:03.02#ibcon#about to read 4, iclass 36, count 0 2006.245.08:02:03.02#ibcon#read 4, iclass 36, count 0 2006.245.08:02:03.02#ibcon#about to read 5, iclass 36, count 0 2006.245.08:02:03.02#ibcon#read 5, iclass 36, count 0 2006.245.08:02:03.02#ibcon#about to read 6, iclass 36, count 0 2006.245.08:02:03.02#ibcon#read 6, iclass 36, count 0 2006.245.08:02:03.02#ibcon#end of sib2, iclass 36, count 0 2006.245.08:02:03.02#ibcon#*after write, iclass 36, count 0 2006.245.08:02:03.02#ibcon#*before return 0, iclass 36, count 0 2006.245.08:02:03.02#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:02:03.02#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:02:03.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:02:03.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:02:03.02$vc4f8/vblo=2,640.99 2006.245.08:02:03.02#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.08:02:03.02#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.08:02:03.02#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:03.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:03.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:03.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:03.02#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:02:03.02#ibcon#first serial, iclass 38, count 0 2006.245.08:02:03.02#ibcon#enter sib2, iclass 38, count 0 2006.245.08:02:03.02#ibcon#flushed, iclass 38, count 0 2006.245.08:02:03.02#ibcon#about to write, iclass 38, count 0 2006.245.08:02:03.02#ibcon#wrote, iclass 38, count 0 2006.245.08:02:03.02#ibcon#about to read 3, iclass 38, count 0 2006.245.08:02:03.05#ibcon#read 3, iclass 38, count 0 2006.245.08:02:03.05#ibcon#about to read 4, iclass 38, count 0 2006.245.08:02:03.05#ibcon#read 4, iclass 38, count 0 2006.245.08:02:03.05#ibcon#about to read 5, iclass 38, count 0 2006.245.08:02:03.05#ibcon#read 5, iclass 38, count 0 2006.245.08:02:03.05#ibcon#about to read 6, iclass 38, count 0 2006.245.08:02:03.05#ibcon#read 6, iclass 38, count 0 2006.245.08:02:03.05#ibcon#end of sib2, iclass 38, count 0 2006.245.08:02:03.05#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:02:03.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:02:03.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:02:03.05#ibcon#*before write, iclass 38, count 0 2006.245.08:02:03.05#ibcon#enter sib2, iclass 38, count 0 2006.245.08:02:03.05#ibcon#flushed, iclass 38, count 0 2006.245.08:02:03.05#ibcon#about to write, iclass 38, count 0 2006.245.08:02:03.05#ibcon#wrote, iclass 38, count 0 2006.245.08:02:03.05#ibcon#about to read 3, iclass 38, count 0 2006.245.08:02:03.09#ibcon#read 3, iclass 38, count 0 2006.245.08:02:03.09#ibcon#about to read 4, iclass 38, count 0 2006.245.08:02:03.09#ibcon#read 4, iclass 38, count 0 2006.245.08:02:03.09#ibcon#about to read 5, iclass 38, count 0 2006.245.08:02:03.09#ibcon#read 5, iclass 38, count 0 2006.245.08:02:03.09#ibcon#about to read 6, iclass 38, count 0 2006.245.08:02:03.09#ibcon#read 6, iclass 38, count 0 2006.245.08:02:03.09#ibcon#end of sib2, iclass 38, count 0 2006.245.08:02:03.09#ibcon#*after write, iclass 38, count 0 2006.245.08:02:03.09#ibcon#*before return 0, iclass 38, count 0 2006.245.08:02:03.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:03.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:02:03.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:02:03.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:02:03.09$vc4f8/vb=2,4 2006.245.08:02:03.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.08:02:03.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.08:02:03.09#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:03.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:03.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:03.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:03.14#ibcon#enter wrdev, iclass 40, count 2 2006.245.08:02:03.14#ibcon#first serial, iclass 40, count 2 2006.245.08:02:03.14#ibcon#enter sib2, iclass 40, count 2 2006.245.08:02:03.14#ibcon#flushed, iclass 40, count 2 2006.245.08:02:03.14#ibcon#about to write, iclass 40, count 2 2006.245.08:02:03.14#ibcon#wrote, iclass 40, count 2 2006.245.08:02:03.14#ibcon#about to read 3, iclass 40, count 2 2006.245.08:02:03.16#ibcon#read 3, iclass 40, count 2 2006.245.08:02:03.16#ibcon#about to read 4, iclass 40, count 2 2006.245.08:02:03.16#ibcon#read 4, iclass 40, count 2 2006.245.08:02:03.16#ibcon#about to read 5, iclass 40, count 2 2006.245.08:02:03.16#ibcon#read 5, iclass 40, count 2 2006.245.08:02:03.16#ibcon#about to read 6, iclass 40, count 2 2006.245.08:02:03.16#ibcon#read 6, iclass 40, count 2 2006.245.08:02:03.16#ibcon#end of sib2, iclass 40, count 2 2006.245.08:02:03.16#ibcon#*mode == 0, iclass 40, count 2 2006.245.08:02:03.16#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.08:02:03.16#ibcon#[27=AT02-04\r\n] 2006.245.08:02:03.16#ibcon#*before write, iclass 40, count 2 2006.245.08:02:03.16#ibcon#enter sib2, iclass 40, count 2 2006.245.08:02:03.16#ibcon#flushed, iclass 40, count 2 2006.245.08:02:03.16#ibcon#about to write, iclass 40, count 2 2006.245.08:02:03.16#ibcon#wrote, iclass 40, count 2 2006.245.08:02:03.16#ibcon#about to read 3, iclass 40, count 2 2006.245.08:02:03.19#ibcon#read 3, iclass 40, count 2 2006.245.08:02:03.19#ibcon#about to read 4, iclass 40, count 2 2006.245.08:02:03.19#ibcon#read 4, iclass 40, count 2 2006.245.08:02:03.19#ibcon#about to read 5, iclass 40, count 2 2006.245.08:02:03.19#ibcon#read 5, iclass 40, count 2 2006.245.08:02:03.19#ibcon#about to read 6, iclass 40, count 2 2006.245.08:02:03.19#ibcon#read 6, iclass 40, count 2 2006.245.08:02:03.19#ibcon#end of sib2, iclass 40, count 2 2006.245.08:02:03.19#ibcon#*after write, iclass 40, count 2 2006.245.08:02:03.19#ibcon#*before return 0, iclass 40, count 2 2006.245.08:02:03.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:03.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:02:03.19#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.08:02:03.19#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:03.19#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:03.31#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:03.31#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:03.31#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:02:03.31#ibcon#first serial, iclass 40, count 0 2006.245.08:02:03.31#ibcon#enter sib2, iclass 40, count 0 2006.245.08:02:03.31#ibcon#flushed, iclass 40, count 0 2006.245.08:02:03.31#ibcon#about to write, iclass 40, count 0 2006.245.08:02:03.31#ibcon#wrote, iclass 40, count 0 2006.245.08:02:03.31#ibcon#about to read 3, iclass 40, count 0 2006.245.08:02:03.33#ibcon#read 3, iclass 40, count 0 2006.245.08:02:03.33#ibcon#about to read 4, iclass 40, count 0 2006.245.08:02:03.33#ibcon#read 4, iclass 40, count 0 2006.245.08:02:03.33#ibcon#about to read 5, iclass 40, count 0 2006.245.08:02:03.33#ibcon#read 5, iclass 40, count 0 2006.245.08:02:03.33#ibcon#about to read 6, iclass 40, count 0 2006.245.08:02:03.33#ibcon#read 6, iclass 40, count 0 2006.245.08:02:03.33#ibcon#end of sib2, iclass 40, count 0 2006.245.08:02:03.33#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:02:03.33#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:02:03.33#ibcon#[27=USB\r\n] 2006.245.08:02:03.33#ibcon#*before write, iclass 40, count 0 2006.245.08:02:03.33#ibcon#enter sib2, iclass 40, count 0 2006.245.08:02:03.33#ibcon#flushed, iclass 40, count 0 2006.245.08:02:03.33#ibcon#about to write, iclass 40, count 0 2006.245.08:02:03.33#ibcon#wrote, iclass 40, count 0 2006.245.08:02:03.33#ibcon#about to read 3, iclass 40, count 0 2006.245.08:02:03.36#ibcon#read 3, iclass 40, count 0 2006.245.08:02:03.36#ibcon#about to read 4, iclass 40, count 0 2006.245.08:02:03.36#ibcon#read 4, iclass 40, count 0 2006.245.08:02:03.36#ibcon#about to read 5, iclass 40, count 0 2006.245.08:02:03.36#ibcon#read 5, iclass 40, count 0 2006.245.08:02:03.36#ibcon#about to read 6, iclass 40, count 0 2006.245.08:02:03.36#ibcon#read 6, iclass 40, count 0 2006.245.08:02:03.36#ibcon#end of sib2, iclass 40, count 0 2006.245.08:02:03.36#ibcon#*after write, iclass 40, count 0 2006.245.08:02:03.36#ibcon#*before return 0, iclass 40, count 0 2006.245.08:02:03.36#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:03.36#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:02:03.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:02:03.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:02:03.36$vc4f8/vblo=3,656.99 2006.245.08:02:03.36#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.08:02:03.36#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.08:02:03.36#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:03.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:03.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:03.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:03.36#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:02:03.36#ibcon#first serial, iclass 4, count 0 2006.245.08:02:03.36#ibcon#enter sib2, iclass 4, count 0 2006.245.08:02:03.36#ibcon#flushed, iclass 4, count 0 2006.245.08:02:03.36#ibcon#about to write, iclass 4, count 0 2006.245.08:02:03.36#ibcon#wrote, iclass 4, count 0 2006.245.08:02:03.36#ibcon#about to read 3, iclass 4, count 0 2006.245.08:02:03.39#ibcon#read 3, iclass 4, count 0 2006.245.08:02:03.39#ibcon#about to read 4, iclass 4, count 0 2006.245.08:02:03.39#ibcon#read 4, iclass 4, count 0 2006.245.08:02:03.39#ibcon#about to read 5, iclass 4, count 0 2006.245.08:02:03.39#ibcon#read 5, iclass 4, count 0 2006.245.08:02:03.39#ibcon#about to read 6, iclass 4, count 0 2006.245.08:02:03.39#ibcon#read 6, iclass 4, count 0 2006.245.08:02:03.39#ibcon#end of sib2, iclass 4, count 0 2006.245.08:02:03.39#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:02:03.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:02:03.39#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:02:03.39#ibcon#*before write, iclass 4, count 0 2006.245.08:02:03.39#ibcon#enter sib2, iclass 4, count 0 2006.245.08:02:03.39#ibcon#flushed, iclass 4, count 0 2006.245.08:02:03.39#ibcon#about to write, iclass 4, count 0 2006.245.08:02:03.39#ibcon#wrote, iclass 4, count 0 2006.245.08:02:03.39#ibcon#about to read 3, iclass 4, count 0 2006.245.08:02:03.43#ibcon#read 3, iclass 4, count 0 2006.245.08:02:03.43#ibcon#about to read 4, iclass 4, count 0 2006.245.08:02:03.43#ibcon#read 4, iclass 4, count 0 2006.245.08:02:03.43#ibcon#about to read 5, iclass 4, count 0 2006.245.08:02:03.43#ibcon#read 5, iclass 4, count 0 2006.245.08:02:03.43#ibcon#about to read 6, iclass 4, count 0 2006.245.08:02:03.43#ibcon#read 6, iclass 4, count 0 2006.245.08:02:03.43#ibcon#end of sib2, iclass 4, count 0 2006.245.08:02:03.43#ibcon#*after write, iclass 4, count 0 2006.245.08:02:03.43#ibcon#*before return 0, iclass 4, count 0 2006.245.08:02:03.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:03.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:02:03.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:02:03.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:02:03.43$vc4f8/vb=3,4 2006.245.08:02:03.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.08:02:03.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.08:02:03.43#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:03.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:03.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:03.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:03.48#ibcon#enter wrdev, iclass 6, count 2 2006.245.08:02:03.48#ibcon#first serial, iclass 6, count 2 2006.245.08:02:03.48#ibcon#enter sib2, iclass 6, count 2 2006.245.08:02:03.48#ibcon#flushed, iclass 6, count 2 2006.245.08:02:03.48#ibcon#about to write, iclass 6, count 2 2006.245.08:02:03.48#ibcon#wrote, iclass 6, count 2 2006.245.08:02:03.48#ibcon#about to read 3, iclass 6, count 2 2006.245.08:02:03.50#ibcon#read 3, iclass 6, count 2 2006.245.08:02:03.50#ibcon#about to read 4, iclass 6, count 2 2006.245.08:02:03.50#ibcon#read 4, iclass 6, count 2 2006.245.08:02:03.50#ibcon#about to read 5, iclass 6, count 2 2006.245.08:02:03.50#ibcon#read 5, iclass 6, count 2 2006.245.08:02:03.50#ibcon#about to read 6, iclass 6, count 2 2006.245.08:02:03.50#ibcon#read 6, iclass 6, count 2 2006.245.08:02:03.50#ibcon#end of sib2, iclass 6, count 2 2006.245.08:02:03.50#ibcon#*mode == 0, iclass 6, count 2 2006.245.08:02:03.50#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.08:02:03.50#ibcon#[27=AT03-04\r\n] 2006.245.08:02:03.50#ibcon#*before write, iclass 6, count 2 2006.245.08:02:03.50#ibcon#enter sib2, iclass 6, count 2 2006.245.08:02:03.50#ibcon#flushed, iclass 6, count 2 2006.245.08:02:03.50#ibcon#about to write, iclass 6, count 2 2006.245.08:02:03.50#ibcon#wrote, iclass 6, count 2 2006.245.08:02:03.50#ibcon#about to read 3, iclass 6, count 2 2006.245.08:02:03.53#ibcon#read 3, iclass 6, count 2 2006.245.08:02:03.53#ibcon#about to read 4, iclass 6, count 2 2006.245.08:02:03.53#ibcon#read 4, iclass 6, count 2 2006.245.08:02:03.53#ibcon#about to read 5, iclass 6, count 2 2006.245.08:02:03.53#ibcon#read 5, iclass 6, count 2 2006.245.08:02:03.53#ibcon#about to read 6, iclass 6, count 2 2006.245.08:02:03.53#ibcon#read 6, iclass 6, count 2 2006.245.08:02:03.53#ibcon#end of sib2, iclass 6, count 2 2006.245.08:02:03.53#ibcon#*after write, iclass 6, count 2 2006.245.08:02:03.53#ibcon#*before return 0, iclass 6, count 2 2006.245.08:02:03.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:03.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:02:03.53#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.08:02:03.53#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:03.53#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:03.65#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:03.65#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:03.65#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:02:03.65#ibcon#first serial, iclass 6, count 0 2006.245.08:02:03.65#ibcon#enter sib2, iclass 6, count 0 2006.245.08:02:03.65#ibcon#flushed, iclass 6, count 0 2006.245.08:02:03.65#ibcon#about to write, iclass 6, count 0 2006.245.08:02:03.65#ibcon#wrote, iclass 6, count 0 2006.245.08:02:03.65#ibcon#about to read 3, iclass 6, count 0 2006.245.08:02:03.67#ibcon#read 3, iclass 6, count 0 2006.245.08:02:03.67#ibcon#about to read 4, iclass 6, count 0 2006.245.08:02:03.67#ibcon#read 4, iclass 6, count 0 2006.245.08:02:03.67#ibcon#about to read 5, iclass 6, count 0 2006.245.08:02:03.67#ibcon#read 5, iclass 6, count 0 2006.245.08:02:03.67#ibcon#about to read 6, iclass 6, count 0 2006.245.08:02:03.67#ibcon#read 6, iclass 6, count 0 2006.245.08:02:03.67#ibcon#end of sib2, iclass 6, count 0 2006.245.08:02:03.67#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:02:03.67#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:02:03.67#ibcon#[27=USB\r\n] 2006.245.08:02:03.67#ibcon#*before write, iclass 6, count 0 2006.245.08:02:03.67#ibcon#enter sib2, iclass 6, count 0 2006.245.08:02:03.67#ibcon#flushed, iclass 6, count 0 2006.245.08:02:03.67#ibcon#about to write, iclass 6, count 0 2006.245.08:02:03.67#ibcon#wrote, iclass 6, count 0 2006.245.08:02:03.67#ibcon#about to read 3, iclass 6, count 0 2006.245.08:02:03.70#ibcon#read 3, iclass 6, count 0 2006.245.08:02:03.70#ibcon#about to read 4, iclass 6, count 0 2006.245.08:02:03.70#ibcon#read 4, iclass 6, count 0 2006.245.08:02:03.70#ibcon#about to read 5, iclass 6, count 0 2006.245.08:02:03.70#ibcon#read 5, iclass 6, count 0 2006.245.08:02:03.70#ibcon#about to read 6, iclass 6, count 0 2006.245.08:02:03.70#ibcon#read 6, iclass 6, count 0 2006.245.08:02:03.70#ibcon#end of sib2, iclass 6, count 0 2006.245.08:02:03.70#ibcon#*after write, iclass 6, count 0 2006.245.08:02:03.70#ibcon#*before return 0, iclass 6, count 0 2006.245.08:02:03.70#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:03.70#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:02:03.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:02:03.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:02:03.70$vc4f8/vblo=4,712.99 2006.245.08:02:03.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.08:02:03.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.08:02:03.70#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:03.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:03.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:03.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:03.70#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:02:03.70#ibcon#first serial, iclass 10, count 0 2006.245.08:02:03.70#ibcon#enter sib2, iclass 10, count 0 2006.245.08:02:03.70#ibcon#flushed, iclass 10, count 0 2006.245.08:02:03.70#ibcon#about to write, iclass 10, count 0 2006.245.08:02:03.70#ibcon#wrote, iclass 10, count 0 2006.245.08:02:03.70#ibcon#about to read 3, iclass 10, count 0 2006.245.08:02:03.72#ibcon#read 3, iclass 10, count 0 2006.245.08:02:03.72#ibcon#about to read 4, iclass 10, count 0 2006.245.08:02:03.72#ibcon#read 4, iclass 10, count 0 2006.245.08:02:03.72#ibcon#about to read 5, iclass 10, count 0 2006.245.08:02:03.72#ibcon#read 5, iclass 10, count 0 2006.245.08:02:03.72#ibcon#about to read 6, iclass 10, count 0 2006.245.08:02:03.72#ibcon#read 6, iclass 10, count 0 2006.245.08:02:03.72#ibcon#end of sib2, iclass 10, count 0 2006.245.08:02:03.72#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:02:03.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:02:03.72#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:02:03.72#ibcon#*before write, iclass 10, count 0 2006.245.08:02:03.72#ibcon#enter sib2, iclass 10, count 0 2006.245.08:02:03.72#ibcon#flushed, iclass 10, count 0 2006.245.08:02:03.72#ibcon#about to write, iclass 10, count 0 2006.245.08:02:03.72#ibcon#wrote, iclass 10, count 0 2006.245.08:02:03.72#ibcon#about to read 3, iclass 10, count 0 2006.245.08:02:03.76#ibcon#read 3, iclass 10, count 0 2006.245.08:02:03.76#ibcon#about to read 4, iclass 10, count 0 2006.245.08:02:03.76#ibcon#read 4, iclass 10, count 0 2006.245.08:02:03.76#ibcon#about to read 5, iclass 10, count 0 2006.245.08:02:03.76#ibcon#read 5, iclass 10, count 0 2006.245.08:02:03.76#ibcon#about to read 6, iclass 10, count 0 2006.245.08:02:03.76#ibcon#read 6, iclass 10, count 0 2006.245.08:02:03.76#ibcon#end of sib2, iclass 10, count 0 2006.245.08:02:03.76#ibcon#*after write, iclass 10, count 0 2006.245.08:02:03.76#ibcon#*before return 0, iclass 10, count 0 2006.245.08:02:03.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:03.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:02:03.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:02:03.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:02:03.76$vc4f8/vb=4,4 2006.245.08:02:03.76#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.08:02:03.76#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.08:02:03.76#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:03.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:03.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:03.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:03.82#ibcon#enter wrdev, iclass 12, count 2 2006.245.08:02:03.82#ibcon#first serial, iclass 12, count 2 2006.245.08:02:03.82#ibcon#enter sib2, iclass 12, count 2 2006.245.08:02:03.82#ibcon#flushed, iclass 12, count 2 2006.245.08:02:03.82#ibcon#about to write, iclass 12, count 2 2006.245.08:02:03.82#ibcon#wrote, iclass 12, count 2 2006.245.08:02:03.82#ibcon#about to read 3, iclass 12, count 2 2006.245.08:02:03.84#ibcon#read 3, iclass 12, count 2 2006.245.08:02:03.84#ibcon#about to read 4, iclass 12, count 2 2006.245.08:02:03.84#ibcon#read 4, iclass 12, count 2 2006.245.08:02:03.84#ibcon#about to read 5, iclass 12, count 2 2006.245.08:02:03.84#ibcon#read 5, iclass 12, count 2 2006.245.08:02:03.84#ibcon#about to read 6, iclass 12, count 2 2006.245.08:02:03.84#ibcon#read 6, iclass 12, count 2 2006.245.08:02:03.84#ibcon#end of sib2, iclass 12, count 2 2006.245.08:02:03.84#ibcon#*mode == 0, iclass 12, count 2 2006.245.08:02:03.84#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.08:02:03.84#ibcon#[27=AT04-04\r\n] 2006.245.08:02:03.84#ibcon#*before write, iclass 12, count 2 2006.245.08:02:03.84#ibcon#enter sib2, iclass 12, count 2 2006.245.08:02:03.84#ibcon#flushed, iclass 12, count 2 2006.245.08:02:03.84#ibcon#about to write, iclass 12, count 2 2006.245.08:02:03.84#ibcon#wrote, iclass 12, count 2 2006.245.08:02:03.84#ibcon#about to read 3, iclass 12, count 2 2006.245.08:02:03.87#ibcon#read 3, iclass 12, count 2 2006.245.08:02:03.87#ibcon#about to read 4, iclass 12, count 2 2006.245.08:02:03.87#ibcon#read 4, iclass 12, count 2 2006.245.08:02:03.87#ibcon#about to read 5, iclass 12, count 2 2006.245.08:02:03.87#ibcon#read 5, iclass 12, count 2 2006.245.08:02:03.87#ibcon#about to read 6, iclass 12, count 2 2006.245.08:02:03.87#ibcon#read 6, iclass 12, count 2 2006.245.08:02:03.87#ibcon#end of sib2, iclass 12, count 2 2006.245.08:02:03.87#ibcon#*after write, iclass 12, count 2 2006.245.08:02:03.87#ibcon#*before return 0, iclass 12, count 2 2006.245.08:02:03.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:03.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:02:03.87#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.08:02:03.87#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:03.87#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:03.99#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:03.99#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:03.99#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:02:03.99#ibcon#first serial, iclass 12, count 0 2006.245.08:02:03.99#ibcon#enter sib2, iclass 12, count 0 2006.245.08:02:03.99#ibcon#flushed, iclass 12, count 0 2006.245.08:02:03.99#ibcon#about to write, iclass 12, count 0 2006.245.08:02:03.99#ibcon#wrote, iclass 12, count 0 2006.245.08:02:03.99#ibcon#about to read 3, iclass 12, count 0 2006.245.08:02:04.01#ibcon#read 3, iclass 12, count 0 2006.245.08:02:04.01#ibcon#about to read 4, iclass 12, count 0 2006.245.08:02:04.01#ibcon#read 4, iclass 12, count 0 2006.245.08:02:04.01#ibcon#about to read 5, iclass 12, count 0 2006.245.08:02:04.01#ibcon#read 5, iclass 12, count 0 2006.245.08:02:04.01#ibcon#about to read 6, iclass 12, count 0 2006.245.08:02:04.01#ibcon#read 6, iclass 12, count 0 2006.245.08:02:04.01#ibcon#end of sib2, iclass 12, count 0 2006.245.08:02:04.01#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:02:04.01#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:02:04.01#ibcon#[27=USB\r\n] 2006.245.08:02:04.01#ibcon#*before write, iclass 12, count 0 2006.245.08:02:04.01#ibcon#enter sib2, iclass 12, count 0 2006.245.08:02:04.01#ibcon#flushed, iclass 12, count 0 2006.245.08:02:04.01#ibcon#about to write, iclass 12, count 0 2006.245.08:02:04.01#ibcon#wrote, iclass 12, count 0 2006.245.08:02:04.01#ibcon#about to read 3, iclass 12, count 0 2006.245.08:02:04.04#ibcon#read 3, iclass 12, count 0 2006.245.08:02:04.04#ibcon#about to read 4, iclass 12, count 0 2006.245.08:02:04.04#ibcon#read 4, iclass 12, count 0 2006.245.08:02:04.04#ibcon#about to read 5, iclass 12, count 0 2006.245.08:02:04.04#ibcon#read 5, iclass 12, count 0 2006.245.08:02:04.04#ibcon#about to read 6, iclass 12, count 0 2006.245.08:02:04.04#ibcon#read 6, iclass 12, count 0 2006.245.08:02:04.04#ibcon#end of sib2, iclass 12, count 0 2006.245.08:02:04.04#ibcon#*after write, iclass 12, count 0 2006.245.08:02:04.04#ibcon#*before return 0, iclass 12, count 0 2006.245.08:02:04.04#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:04.04#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:02:04.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:02:04.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:02:04.04$vc4f8/vblo=5,744.99 2006.245.08:02:04.04#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.08:02:04.04#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.08:02:04.04#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:04.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:04.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:04.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:04.04#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:02:04.04#ibcon#first serial, iclass 14, count 0 2006.245.08:02:04.04#ibcon#enter sib2, iclass 14, count 0 2006.245.08:02:04.04#ibcon#flushed, iclass 14, count 0 2006.245.08:02:04.04#ibcon#about to write, iclass 14, count 0 2006.245.08:02:04.04#ibcon#wrote, iclass 14, count 0 2006.245.08:02:04.04#ibcon#about to read 3, iclass 14, count 0 2006.245.08:02:04.06#ibcon#read 3, iclass 14, count 0 2006.245.08:02:04.06#ibcon#about to read 4, iclass 14, count 0 2006.245.08:02:04.06#ibcon#read 4, iclass 14, count 0 2006.245.08:02:04.06#ibcon#about to read 5, iclass 14, count 0 2006.245.08:02:04.06#ibcon#read 5, iclass 14, count 0 2006.245.08:02:04.06#ibcon#about to read 6, iclass 14, count 0 2006.245.08:02:04.06#ibcon#read 6, iclass 14, count 0 2006.245.08:02:04.06#ibcon#end of sib2, iclass 14, count 0 2006.245.08:02:04.06#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:02:04.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:02:04.06#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:02:04.06#ibcon#*before write, iclass 14, count 0 2006.245.08:02:04.06#ibcon#enter sib2, iclass 14, count 0 2006.245.08:02:04.06#ibcon#flushed, iclass 14, count 0 2006.245.08:02:04.06#ibcon#about to write, iclass 14, count 0 2006.245.08:02:04.06#ibcon#wrote, iclass 14, count 0 2006.245.08:02:04.06#ibcon#about to read 3, iclass 14, count 0 2006.245.08:02:04.10#ibcon#read 3, iclass 14, count 0 2006.245.08:02:04.10#ibcon#about to read 4, iclass 14, count 0 2006.245.08:02:04.10#ibcon#read 4, iclass 14, count 0 2006.245.08:02:04.10#ibcon#about to read 5, iclass 14, count 0 2006.245.08:02:04.10#ibcon#read 5, iclass 14, count 0 2006.245.08:02:04.10#ibcon#about to read 6, iclass 14, count 0 2006.245.08:02:04.10#ibcon#read 6, iclass 14, count 0 2006.245.08:02:04.10#ibcon#end of sib2, iclass 14, count 0 2006.245.08:02:04.10#ibcon#*after write, iclass 14, count 0 2006.245.08:02:04.10#ibcon#*before return 0, iclass 14, count 0 2006.245.08:02:04.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:04.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:02:04.10#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:02:04.10#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:02:04.10$vc4f8/vb=5,3 2006.245.08:02:04.10#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:02:04.10#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:02:04.10#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:04.10#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:04.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:04.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:04.17#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:02:04.17#ibcon#first serial, iclass 16, count 2 2006.245.08:02:04.17#ibcon#enter sib2, iclass 16, count 2 2006.245.08:02:04.17#ibcon#flushed, iclass 16, count 2 2006.245.08:02:04.17#ibcon#about to write, iclass 16, count 2 2006.245.08:02:04.17#ibcon#wrote, iclass 16, count 2 2006.245.08:02:04.17#ibcon#about to read 3, iclass 16, count 2 2006.245.08:02:04.18#ibcon#read 3, iclass 16, count 2 2006.245.08:02:04.18#ibcon#about to read 4, iclass 16, count 2 2006.245.08:02:04.18#ibcon#read 4, iclass 16, count 2 2006.245.08:02:04.18#ibcon#about to read 5, iclass 16, count 2 2006.245.08:02:04.18#ibcon#read 5, iclass 16, count 2 2006.245.08:02:04.18#ibcon#about to read 6, iclass 16, count 2 2006.245.08:02:04.18#ibcon#read 6, iclass 16, count 2 2006.245.08:02:04.18#ibcon#end of sib2, iclass 16, count 2 2006.245.08:02:04.18#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:02:04.18#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:02:04.18#ibcon#[27=AT05-03\r\n] 2006.245.08:02:04.18#ibcon#*before write, iclass 16, count 2 2006.245.08:02:04.18#ibcon#enter sib2, iclass 16, count 2 2006.245.08:02:04.18#ibcon#flushed, iclass 16, count 2 2006.245.08:02:04.18#ibcon#about to write, iclass 16, count 2 2006.245.08:02:04.18#ibcon#wrote, iclass 16, count 2 2006.245.08:02:04.18#ibcon#about to read 3, iclass 16, count 2 2006.245.08:02:04.21#ibcon#read 3, iclass 16, count 2 2006.245.08:02:04.21#ibcon#about to read 4, iclass 16, count 2 2006.245.08:02:04.21#ibcon#read 4, iclass 16, count 2 2006.245.08:02:04.21#ibcon#about to read 5, iclass 16, count 2 2006.245.08:02:04.21#ibcon#read 5, iclass 16, count 2 2006.245.08:02:04.21#ibcon#about to read 6, iclass 16, count 2 2006.245.08:02:04.21#ibcon#read 6, iclass 16, count 2 2006.245.08:02:04.21#ibcon#end of sib2, iclass 16, count 2 2006.245.08:02:04.21#ibcon#*after write, iclass 16, count 2 2006.245.08:02:04.21#ibcon#*before return 0, iclass 16, count 2 2006.245.08:02:04.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:04.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:02:04.21#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:02:04.21#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:04.21#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:04.33#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:04.33#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:04.33#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:02:04.33#ibcon#first serial, iclass 16, count 0 2006.245.08:02:04.33#ibcon#enter sib2, iclass 16, count 0 2006.245.08:02:04.33#ibcon#flushed, iclass 16, count 0 2006.245.08:02:04.33#ibcon#about to write, iclass 16, count 0 2006.245.08:02:04.33#ibcon#wrote, iclass 16, count 0 2006.245.08:02:04.33#ibcon#about to read 3, iclass 16, count 0 2006.245.08:02:04.35#ibcon#read 3, iclass 16, count 0 2006.245.08:02:04.35#ibcon#about to read 4, iclass 16, count 0 2006.245.08:02:04.35#ibcon#read 4, iclass 16, count 0 2006.245.08:02:04.35#ibcon#about to read 5, iclass 16, count 0 2006.245.08:02:04.35#ibcon#read 5, iclass 16, count 0 2006.245.08:02:04.35#ibcon#about to read 6, iclass 16, count 0 2006.245.08:02:04.35#ibcon#read 6, iclass 16, count 0 2006.245.08:02:04.35#ibcon#end of sib2, iclass 16, count 0 2006.245.08:02:04.35#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:02:04.35#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:02:04.35#ibcon#[27=USB\r\n] 2006.245.08:02:04.35#ibcon#*before write, iclass 16, count 0 2006.245.08:02:04.35#ibcon#enter sib2, iclass 16, count 0 2006.245.08:02:04.35#ibcon#flushed, iclass 16, count 0 2006.245.08:02:04.35#ibcon#about to write, iclass 16, count 0 2006.245.08:02:04.35#ibcon#wrote, iclass 16, count 0 2006.245.08:02:04.35#ibcon#about to read 3, iclass 16, count 0 2006.245.08:02:04.38#ibcon#read 3, iclass 16, count 0 2006.245.08:02:04.38#ibcon#about to read 4, iclass 16, count 0 2006.245.08:02:04.38#ibcon#read 4, iclass 16, count 0 2006.245.08:02:04.38#ibcon#about to read 5, iclass 16, count 0 2006.245.08:02:04.38#ibcon#read 5, iclass 16, count 0 2006.245.08:02:04.38#ibcon#about to read 6, iclass 16, count 0 2006.245.08:02:04.38#ibcon#read 6, iclass 16, count 0 2006.245.08:02:04.38#ibcon#end of sib2, iclass 16, count 0 2006.245.08:02:04.38#ibcon#*after write, iclass 16, count 0 2006.245.08:02:04.38#ibcon#*before return 0, iclass 16, count 0 2006.245.08:02:04.38#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:04.38#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:02:04.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:02:04.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:02:04.38$vc4f8/vblo=6,752.99 2006.245.08:02:04.38#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.08:02:04.38#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.08:02:04.38#ibcon#ireg 17 cls_cnt 0 2006.245.08:02:04.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:04.38#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:04.38#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:04.38#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:02:04.38#ibcon#first serial, iclass 18, count 0 2006.245.08:02:04.38#ibcon#enter sib2, iclass 18, count 0 2006.245.08:02:04.38#ibcon#flushed, iclass 18, count 0 2006.245.08:02:04.38#ibcon#about to write, iclass 18, count 0 2006.245.08:02:04.38#ibcon#wrote, iclass 18, count 0 2006.245.08:02:04.38#ibcon#about to read 3, iclass 18, count 0 2006.245.08:02:04.40#ibcon#read 3, iclass 18, count 0 2006.245.08:02:04.40#ibcon#about to read 4, iclass 18, count 0 2006.245.08:02:04.40#ibcon#read 4, iclass 18, count 0 2006.245.08:02:04.40#ibcon#about to read 5, iclass 18, count 0 2006.245.08:02:04.40#ibcon#read 5, iclass 18, count 0 2006.245.08:02:04.40#ibcon#about to read 6, iclass 18, count 0 2006.245.08:02:04.40#ibcon#read 6, iclass 18, count 0 2006.245.08:02:04.40#ibcon#end of sib2, iclass 18, count 0 2006.245.08:02:04.40#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:02:04.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:02:04.40#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:02:04.40#ibcon#*before write, iclass 18, count 0 2006.245.08:02:04.40#ibcon#enter sib2, iclass 18, count 0 2006.245.08:02:04.40#ibcon#flushed, iclass 18, count 0 2006.245.08:02:04.40#ibcon#about to write, iclass 18, count 0 2006.245.08:02:04.40#ibcon#wrote, iclass 18, count 0 2006.245.08:02:04.40#ibcon#about to read 3, iclass 18, count 0 2006.245.08:02:04.44#ibcon#read 3, iclass 18, count 0 2006.245.08:02:04.44#ibcon#about to read 4, iclass 18, count 0 2006.245.08:02:04.44#ibcon#read 4, iclass 18, count 0 2006.245.08:02:04.44#ibcon#about to read 5, iclass 18, count 0 2006.245.08:02:04.44#ibcon#read 5, iclass 18, count 0 2006.245.08:02:04.44#ibcon#about to read 6, iclass 18, count 0 2006.245.08:02:04.44#ibcon#read 6, iclass 18, count 0 2006.245.08:02:04.44#ibcon#end of sib2, iclass 18, count 0 2006.245.08:02:04.44#ibcon#*after write, iclass 18, count 0 2006.245.08:02:04.44#ibcon#*before return 0, iclass 18, count 0 2006.245.08:02:04.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:04.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:02:04.44#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:02:04.44#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:02:04.44$vc4f8/vb=6,3 2006.245.08:02:04.44#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.08:02:04.44#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.08:02:04.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:02:04.44#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:04.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:04.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:04.50#ibcon#enter wrdev, iclass 20, count 2 2006.245.08:02:04.50#ibcon#first serial, iclass 20, count 2 2006.245.08:02:04.50#ibcon#enter sib2, iclass 20, count 2 2006.245.08:02:04.50#ibcon#flushed, iclass 20, count 2 2006.245.08:02:04.50#ibcon#about to write, iclass 20, count 2 2006.245.08:02:04.50#ibcon#wrote, iclass 20, count 2 2006.245.08:02:04.50#ibcon#about to read 3, iclass 20, count 2 2006.245.08:02:04.52#ibcon#read 3, iclass 20, count 2 2006.245.08:02:04.52#ibcon#about to read 4, iclass 20, count 2 2006.245.08:02:04.52#ibcon#read 4, iclass 20, count 2 2006.245.08:02:04.52#ibcon#about to read 5, iclass 20, count 2 2006.245.08:02:04.52#ibcon#read 5, iclass 20, count 2 2006.245.08:02:04.52#ibcon#about to read 6, iclass 20, count 2 2006.245.08:02:04.52#ibcon#read 6, iclass 20, count 2 2006.245.08:02:04.52#ibcon#end of sib2, iclass 20, count 2 2006.245.08:02:04.52#ibcon#*mode == 0, iclass 20, count 2 2006.245.08:02:04.52#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.08:02:04.52#ibcon#[27=AT06-03\r\n] 2006.245.08:02:04.52#ibcon#*before write, iclass 20, count 2 2006.245.08:02:04.52#ibcon#enter sib2, iclass 20, count 2 2006.245.08:02:04.52#ibcon#flushed, iclass 20, count 2 2006.245.08:02:04.52#ibcon#about to write, iclass 20, count 2 2006.245.08:02:04.52#ibcon#wrote, iclass 20, count 2 2006.245.08:02:04.52#ibcon#about to read 3, iclass 20, count 2 2006.245.08:02:04.55#ibcon#read 3, iclass 20, count 2 2006.245.08:02:04.55#ibcon#about to read 4, iclass 20, count 2 2006.245.08:02:04.55#ibcon#read 4, iclass 20, count 2 2006.245.08:02:04.55#ibcon#about to read 5, iclass 20, count 2 2006.245.08:02:04.55#ibcon#read 5, iclass 20, count 2 2006.245.08:02:04.55#ibcon#about to read 6, iclass 20, count 2 2006.245.08:02:04.55#ibcon#read 6, iclass 20, count 2 2006.245.08:02:04.55#ibcon#end of sib2, iclass 20, count 2 2006.245.08:02:04.55#ibcon#*after write, iclass 20, count 2 2006.245.08:02:04.55#ibcon#*before return 0, iclass 20, count 2 2006.245.08:02:04.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:04.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:02:04.55#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.08:02:04.55#ibcon#ireg 7 cls_cnt 0 2006.245.08:02:04.55#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:04.67#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:04.67#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:04.67#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:02:04.67#ibcon#first serial, iclass 20, count 0 2006.245.08:02:04.67#ibcon#enter sib2, iclass 20, count 0 2006.245.08:02:04.67#ibcon#flushed, iclass 20, count 0 2006.245.08:02:04.67#ibcon#about to write, iclass 20, count 0 2006.245.08:02:04.67#ibcon#wrote, iclass 20, count 0 2006.245.08:02:04.67#ibcon#about to read 3, iclass 20, count 0 2006.245.08:02:04.69#ibcon#read 3, iclass 20, count 0 2006.245.08:02:04.69#ibcon#about to read 4, iclass 20, count 0 2006.245.08:02:04.69#ibcon#read 4, iclass 20, count 0 2006.245.08:02:04.69#ibcon#about to read 5, iclass 20, count 0 2006.245.08:02:04.69#ibcon#read 5, iclass 20, count 0 2006.245.08:02:04.69#ibcon#about to read 6, iclass 20, count 0 2006.245.08:02:04.69#ibcon#read 6, iclass 20, count 0 2006.245.08:02:04.69#ibcon#end of sib2, iclass 20, count 0 2006.245.08:02:04.69#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:02:04.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:02:04.69#ibcon#[27=USB\r\n] 2006.245.08:02:04.69#ibcon#*before write, iclass 20, count 0 2006.245.08:02:04.69#ibcon#enter sib2, iclass 20, count 0 2006.245.08:02:04.69#ibcon#flushed, iclass 20, count 0 2006.245.08:02:04.69#ibcon#about to write, iclass 20, count 0 2006.245.08:02:04.69#ibcon#wrote, iclass 20, count 0 2006.245.08:02:04.69#ibcon#about to read 3, iclass 20, count 0 2006.245.08:02:04.72#ibcon#read 3, iclass 20, count 0 2006.245.08:02:04.72#ibcon#about to read 4, iclass 20, count 0 2006.245.08:02:04.72#ibcon#read 4, iclass 20, count 0 2006.245.08:02:04.72#ibcon#about to read 5, iclass 20, count 0 2006.245.08:02:04.72#ibcon#read 5, iclass 20, count 0 2006.245.08:02:04.72#ibcon#about to read 6, iclass 20, count 0 2006.245.08:02:04.72#ibcon#read 6, iclass 20, count 0 2006.245.08:02:04.72#ibcon#end of sib2, iclass 20, count 0 2006.245.08:02:04.72#ibcon#*after write, iclass 20, count 0 2006.245.08:02:04.72#ibcon#*before return 0, iclass 20, count 0 2006.245.08:02:04.72#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:04.72#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:02:04.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:02:04.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:02:04.72$vc4f8/vabw=wide 2006.245.08:02:04.72#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:02:04.72#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:02:04.72#ibcon#ireg 8 cls_cnt 0 2006.245.08:02:04.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:04.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:04.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:04.72#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:02:04.72#ibcon#first serial, iclass 22, count 0 2006.245.08:02:04.72#ibcon#enter sib2, iclass 22, count 0 2006.245.08:02:04.72#ibcon#flushed, iclass 22, count 0 2006.245.08:02:04.72#ibcon#about to write, iclass 22, count 0 2006.245.08:02:04.72#ibcon#wrote, iclass 22, count 0 2006.245.08:02:04.72#ibcon#about to read 3, iclass 22, count 0 2006.245.08:02:04.75#ibcon#read 3, iclass 22, count 0 2006.245.08:02:04.75#ibcon#about to read 4, iclass 22, count 0 2006.245.08:02:04.75#ibcon#read 4, iclass 22, count 0 2006.245.08:02:04.75#ibcon#about to read 5, iclass 22, count 0 2006.245.08:02:04.75#ibcon#read 5, iclass 22, count 0 2006.245.08:02:04.75#ibcon#about to read 6, iclass 22, count 0 2006.245.08:02:04.75#ibcon#read 6, iclass 22, count 0 2006.245.08:02:04.75#ibcon#end of sib2, iclass 22, count 0 2006.245.08:02:04.75#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:02:04.75#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:02:04.75#ibcon#[25=BW32\r\n] 2006.245.08:02:04.75#ibcon#*before write, iclass 22, count 0 2006.245.08:02:04.75#ibcon#enter sib2, iclass 22, count 0 2006.245.08:02:04.75#ibcon#flushed, iclass 22, count 0 2006.245.08:02:04.75#ibcon#about to write, iclass 22, count 0 2006.245.08:02:04.75#ibcon#wrote, iclass 22, count 0 2006.245.08:02:04.75#ibcon#about to read 3, iclass 22, count 0 2006.245.08:02:04.78#ibcon#read 3, iclass 22, count 0 2006.245.08:02:04.78#ibcon#about to read 4, iclass 22, count 0 2006.245.08:02:04.78#ibcon#read 4, iclass 22, count 0 2006.245.08:02:04.78#ibcon#about to read 5, iclass 22, count 0 2006.245.08:02:04.78#ibcon#read 5, iclass 22, count 0 2006.245.08:02:04.78#ibcon#about to read 6, iclass 22, count 0 2006.245.08:02:04.78#ibcon#read 6, iclass 22, count 0 2006.245.08:02:04.78#ibcon#end of sib2, iclass 22, count 0 2006.245.08:02:04.78#ibcon#*after write, iclass 22, count 0 2006.245.08:02:04.78#ibcon#*before return 0, iclass 22, count 0 2006.245.08:02:04.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:04.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:02:04.78#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:02:04.78#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:02:04.78$vc4f8/vbbw=wide 2006.245.08:02:04.78#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:02:04.78#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:02:04.78#ibcon#ireg 8 cls_cnt 0 2006.245.08:02:04.78#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:02:04.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:02:04.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:02:04.84#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:02:04.84#ibcon#first serial, iclass 24, count 0 2006.245.08:02:04.84#ibcon#enter sib2, iclass 24, count 0 2006.245.08:02:04.84#ibcon#flushed, iclass 24, count 0 2006.245.08:02:04.84#ibcon#about to write, iclass 24, count 0 2006.245.08:02:04.84#ibcon#wrote, iclass 24, count 0 2006.245.08:02:04.84#ibcon#about to read 3, iclass 24, count 0 2006.245.08:02:04.86#ibcon#read 3, iclass 24, count 0 2006.245.08:02:04.86#ibcon#about to read 4, iclass 24, count 0 2006.245.08:02:04.86#ibcon#read 4, iclass 24, count 0 2006.245.08:02:04.86#ibcon#about to read 5, iclass 24, count 0 2006.245.08:02:04.86#ibcon#read 5, iclass 24, count 0 2006.245.08:02:04.86#ibcon#about to read 6, iclass 24, count 0 2006.245.08:02:04.86#ibcon#read 6, iclass 24, count 0 2006.245.08:02:04.86#ibcon#end of sib2, iclass 24, count 0 2006.245.08:02:04.86#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:02:04.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:02:04.86#ibcon#[27=BW32\r\n] 2006.245.08:02:04.86#ibcon#*before write, iclass 24, count 0 2006.245.08:02:04.86#ibcon#enter sib2, iclass 24, count 0 2006.245.08:02:04.86#ibcon#flushed, iclass 24, count 0 2006.245.08:02:04.86#ibcon#about to write, iclass 24, count 0 2006.245.08:02:04.86#ibcon#wrote, iclass 24, count 0 2006.245.08:02:04.86#ibcon#about to read 3, iclass 24, count 0 2006.245.08:02:04.89#ibcon#read 3, iclass 24, count 0 2006.245.08:02:04.89#ibcon#about to read 4, iclass 24, count 0 2006.245.08:02:04.89#ibcon#read 4, iclass 24, count 0 2006.245.08:02:04.89#ibcon#about to read 5, iclass 24, count 0 2006.245.08:02:04.89#ibcon#read 5, iclass 24, count 0 2006.245.08:02:04.89#ibcon#about to read 6, iclass 24, count 0 2006.245.08:02:04.89#ibcon#read 6, iclass 24, count 0 2006.245.08:02:04.89#ibcon#end of sib2, iclass 24, count 0 2006.245.08:02:04.89#ibcon#*after write, iclass 24, count 0 2006.245.08:02:04.89#ibcon#*before return 0, iclass 24, count 0 2006.245.08:02:04.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:02:04.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:02:04.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:02:04.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:02:04.89$4f8m12a/ifd4f 2006.245.08:02:04.89$ifd4f/lo= 2006.245.08:02:04.89$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:02:04.89$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:02:04.89$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:02:04.89$ifd4f/patch= 2006.245.08:02:04.89$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:02:04.89$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:02:04.89$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:02:04.89$4f8m12a/"form=m,16.000,1:2 2006.245.08:02:04.89$4f8m12a/"tpicd 2006.245.08:02:04.89$4f8m12a/echo=off 2006.245.08:02:04.89$4f8m12a/xlog=off 2006.245.08:02:04.89:!2006.245.08:02:30 2006.245.08:02:14.14#trakl#Source acquired 2006.245.08:02:14.14#flagr#flagr/antenna,acquired 2006.245.08:02:30.00:preob 2006.245.08:02:30.14/onsource/TRACKING 2006.245.08:02:30.14:!2006.245.08:02:40 2006.245.08:02:40.00:data_valid=on 2006.245.08:02:40.00:midob 2006.245.08:02:41.14/onsource/TRACKING 2006.245.08:02:41.14/wx/27.10,1004.5,72 2006.245.08:02:41.33/cable/+6.4085E-03 2006.245.08:02:42.42/va/01,08,usb,yes,31,32 2006.245.08:02:42.42/va/02,07,usb,yes,31,32 2006.245.08:02:42.42/va/03,06,usb,yes,33,33 2006.245.08:02:42.42/va/04,07,usb,yes,32,34 2006.245.08:02:42.42/va/05,07,usb,yes,33,35 2006.245.08:02:42.42/va/06,07,usb,yes,29,29 2006.245.08:02:42.42/va/07,07,usb,yes,29,28 2006.245.08:02:42.42/va/08,08,usb,yes,25,25 2006.245.08:02:42.65/valo/01,532.99,yes,locked 2006.245.08:02:42.65/valo/02,572.99,yes,locked 2006.245.08:02:42.65/valo/03,672.99,yes,locked 2006.245.08:02:42.65/valo/04,832.99,yes,locked 2006.245.08:02:42.65/valo/05,652.99,yes,locked 2006.245.08:02:42.65/valo/06,772.99,yes,locked 2006.245.08:02:42.65/valo/07,832.99,yes,locked 2006.245.08:02:42.65/valo/08,852.99,yes,locked 2006.245.08:02:43.74/vb/01,04,usb,yes,30,29 2006.245.08:02:43.74/vb/02,04,usb,yes,32,34 2006.245.08:02:43.74/vb/03,04,usb,yes,28,32 2006.245.08:02:43.74/vb/04,04,usb,yes,29,29 2006.245.08:02:43.74/vb/05,03,usb,yes,35,39 2006.245.08:02:43.74/vb/06,03,usb,yes,35,39 2006.245.08:02:43.74/vb/07,04,usb,yes,31,31 2006.245.08:02:43.74/vb/08,03,usb,yes,35,39 2006.245.08:02:43.97/vblo/01,632.99,yes,locked 2006.245.08:02:43.97/vblo/02,640.99,yes,locked 2006.245.08:02:43.97/vblo/03,656.99,yes,locked 2006.245.08:02:43.97/vblo/04,712.99,yes,locked 2006.245.08:02:43.97/vblo/05,744.99,yes,locked 2006.245.08:02:43.97/vblo/06,752.99,yes,locked 2006.245.08:02:43.97/vblo/07,734.99,yes,locked 2006.245.08:02:43.97/vblo/08,744.99,yes,locked 2006.245.08:02:44.12/vabw/8 2006.245.08:02:44.27/vbbw/8 2006.245.08:02:44.36/xfe/off,on,13.2 2006.245.08:02:44.73/ifatt/23,28,28,28 2006.245.08:02:45.07/fmout-gps/S +4.39E-07 2006.245.08:02:45.11:!2006.245.08:03:40 2006.245.08:03:40.00:data_valid=off 2006.245.08:03:40.01:postob 2006.245.08:03:40.14/cable/+6.4111E-03 2006.245.08:03:40.15/wx/27.08,1004.5,72 2006.245.08:03:41.07/fmout-gps/S +4.39E-07 2006.245.08:03:41.08:scan_name=245-0804,k06245,60 2006.245.08:03:41.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.245.08:03:41.13#flagr#flagr/antenna,new-source 2006.245.08:03:42.13:checkk5 2006.245.08:03:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:03:43.02/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:03:43.46/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:03:43.91/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:03:44.52/chk_obsdata//k5ts1/T2450802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:03:45.25/chk_obsdata//k5ts2/T2450802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:03:45.68/chk_obsdata//k5ts3/T2450802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:03:46.19/chk_obsdata//k5ts4/T2450802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:03:47.02/k5log//k5ts1_log_newline 2006.245.08:03:48.48/k5log//k5ts2_log_newline 2006.245.08:03:49.59/k5log//k5ts3_log_newline 2006.245.08:03:50.35/k5log//k5ts4_log_newline 2006.245.08:03:50.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:03:50.37:4f8m12a=2 2006.245.08:03:50.37$4f8m12a/echo=on 2006.245.08:03:50.37$4f8m12a/pcalon 2006.245.08:03:50.37$pcalon/"no phase cal control is implemented here 2006.245.08:03:50.37$4f8m12a/"tpicd=stop 2006.245.08:03:50.37$4f8m12a/vc4f8 2006.245.08:03:50.37$vc4f8/valo=1,532.99 2006.245.08:03:50.37#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.08:03:50.37#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.08:03:50.37#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:50.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:50.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:50.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:50.37#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:03:50.37#ibcon#first serial, iclass 35, count 0 2006.245.08:03:50.37#ibcon#enter sib2, iclass 35, count 0 2006.245.08:03:50.37#ibcon#flushed, iclass 35, count 0 2006.245.08:03:50.37#ibcon#about to write, iclass 35, count 0 2006.245.08:03:50.37#ibcon#wrote, iclass 35, count 0 2006.245.08:03:50.37#ibcon#about to read 3, iclass 35, count 0 2006.245.08:03:50.39#ibcon#read 3, iclass 35, count 0 2006.245.08:03:50.39#ibcon#about to read 4, iclass 35, count 0 2006.245.08:03:50.39#ibcon#read 4, iclass 35, count 0 2006.245.08:03:50.39#ibcon#about to read 5, iclass 35, count 0 2006.245.08:03:50.39#ibcon#read 5, iclass 35, count 0 2006.245.08:03:50.39#ibcon#about to read 6, iclass 35, count 0 2006.245.08:03:50.39#ibcon#read 6, iclass 35, count 0 2006.245.08:03:50.39#ibcon#end of sib2, iclass 35, count 0 2006.245.08:03:50.39#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:03:50.39#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:03:50.39#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:03:50.39#ibcon#*before write, iclass 35, count 0 2006.245.08:03:50.39#ibcon#enter sib2, iclass 35, count 0 2006.245.08:03:50.39#ibcon#flushed, iclass 35, count 0 2006.245.08:03:50.39#ibcon#about to write, iclass 35, count 0 2006.245.08:03:50.39#ibcon#wrote, iclass 35, count 0 2006.245.08:03:50.39#ibcon#about to read 3, iclass 35, count 0 2006.245.08:03:50.44#ibcon#read 3, iclass 35, count 0 2006.245.08:03:50.44#ibcon#about to read 4, iclass 35, count 0 2006.245.08:03:50.44#ibcon#read 4, iclass 35, count 0 2006.245.08:03:50.44#ibcon#about to read 5, iclass 35, count 0 2006.245.08:03:50.44#ibcon#read 5, iclass 35, count 0 2006.245.08:03:50.44#ibcon#about to read 6, iclass 35, count 0 2006.245.08:03:50.44#ibcon#read 6, iclass 35, count 0 2006.245.08:03:50.44#ibcon#end of sib2, iclass 35, count 0 2006.245.08:03:50.44#ibcon#*after write, iclass 35, count 0 2006.245.08:03:50.44#ibcon#*before return 0, iclass 35, count 0 2006.245.08:03:50.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:50.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:50.44#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:03:50.44#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:03:50.44$vc4f8/va=1,8 2006.245.08:03:50.44#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.08:03:50.44#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.08:03:50.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:50.44#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:50.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:50.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:50.44#ibcon#enter wrdev, iclass 37, count 2 2006.245.08:03:50.44#ibcon#first serial, iclass 37, count 2 2006.245.08:03:50.44#ibcon#enter sib2, iclass 37, count 2 2006.245.08:03:50.44#ibcon#flushed, iclass 37, count 2 2006.245.08:03:50.44#ibcon#about to write, iclass 37, count 2 2006.245.08:03:50.44#ibcon#wrote, iclass 37, count 2 2006.245.08:03:50.44#ibcon#about to read 3, iclass 37, count 2 2006.245.08:03:50.46#ibcon#read 3, iclass 37, count 2 2006.245.08:03:50.46#ibcon#about to read 4, iclass 37, count 2 2006.245.08:03:50.46#ibcon#read 4, iclass 37, count 2 2006.245.08:03:50.46#ibcon#about to read 5, iclass 37, count 2 2006.245.08:03:50.46#ibcon#read 5, iclass 37, count 2 2006.245.08:03:50.46#ibcon#about to read 6, iclass 37, count 2 2006.245.08:03:50.46#ibcon#read 6, iclass 37, count 2 2006.245.08:03:50.46#ibcon#end of sib2, iclass 37, count 2 2006.245.08:03:50.46#ibcon#*mode == 0, iclass 37, count 2 2006.245.08:03:50.46#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.08:03:50.46#ibcon#[25=AT01-08\r\n] 2006.245.08:03:50.46#ibcon#*before write, iclass 37, count 2 2006.245.08:03:50.46#ibcon#enter sib2, iclass 37, count 2 2006.245.08:03:50.46#ibcon#flushed, iclass 37, count 2 2006.245.08:03:50.46#ibcon#about to write, iclass 37, count 2 2006.245.08:03:50.46#ibcon#wrote, iclass 37, count 2 2006.245.08:03:50.46#ibcon#about to read 3, iclass 37, count 2 2006.245.08:03:50.50#ibcon#read 3, iclass 37, count 2 2006.245.08:03:50.50#ibcon#about to read 4, iclass 37, count 2 2006.245.08:03:50.50#ibcon#read 4, iclass 37, count 2 2006.245.08:03:50.50#ibcon#about to read 5, iclass 37, count 2 2006.245.08:03:50.50#ibcon#read 5, iclass 37, count 2 2006.245.08:03:50.50#ibcon#about to read 6, iclass 37, count 2 2006.245.08:03:50.50#ibcon#read 6, iclass 37, count 2 2006.245.08:03:50.50#ibcon#end of sib2, iclass 37, count 2 2006.245.08:03:50.50#ibcon#*after write, iclass 37, count 2 2006.245.08:03:50.50#ibcon#*before return 0, iclass 37, count 2 2006.245.08:03:50.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:50.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:50.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.08:03:50.50#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:50.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:50.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:50.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:50.61#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:03:50.61#ibcon#first serial, iclass 37, count 0 2006.245.08:03:50.61#ibcon#enter sib2, iclass 37, count 0 2006.245.08:03:50.61#ibcon#flushed, iclass 37, count 0 2006.245.08:03:50.61#ibcon#about to write, iclass 37, count 0 2006.245.08:03:50.61#ibcon#wrote, iclass 37, count 0 2006.245.08:03:50.61#ibcon#about to read 3, iclass 37, count 0 2006.245.08:03:50.63#ibcon#read 3, iclass 37, count 0 2006.245.08:03:50.63#ibcon#about to read 4, iclass 37, count 0 2006.245.08:03:50.63#ibcon#read 4, iclass 37, count 0 2006.245.08:03:50.63#ibcon#about to read 5, iclass 37, count 0 2006.245.08:03:50.63#ibcon#read 5, iclass 37, count 0 2006.245.08:03:50.63#ibcon#about to read 6, iclass 37, count 0 2006.245.08:03:50.63#ibcon#read 6, iclass 37, count 0 2006.245.08:03:50.63#ibcon#end of sib2, iclass 37, count 0 2006.245.08:03:50.63#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:03:50.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:03:50.63#ibcon#[25=USB\r\n] 2006.245.08:03:50.63#ibcon#*before write, iclass 37, count 0 2006.245.08:03:50.63#ibcon#enter sib2, iclass 37, count 0 2006.245.08:03:50.63#ibcon#flushed, iclass 37, count 0 2006.245.08:03:50.63#ibcon#about to write, iclass 37, count 0 2006.245.08:03:50.63#ibcon#wrote, iclass 37, count 0 2006.245.08:03:50.63#ibcon#about to read 3, iclass 37, count 0 2006.245.08:03:50.66#ibcon#read 3, iclass 37, count 0 2006.245.08:03:50.66#ibcon#about to read 4, iclass 37, count 0 2006.245.08:03:50.66#ibcon#read 4, iclass 37, count 0 2006.245.08:03:50.66#ibcon#about to read 5, iclass 37, count 0 2006.245.08:03:50.66#ibcon#read 5, iclass 37, count 0 2006.245.08:03:50.66#ibcon#about to read 6, iclass 37, count 0 2006.245.08:03:50.66#ibcon#read 6, iclass 37, count 0 2006.245.08:03:50.66#ibcon#end of sib2, iclass 37, count 0 2006.245.08:03:50.66#ibcon#*after write, iclass 37, count 0 2006.245.08:03:50.66#ibcon#*before return 0, iclass 37, count 0 2006.245.08:03:50.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:50.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:50.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:03:50.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:03:50.66$vc4f8/valo=2,572.99 2006.245.08:03:50.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.08:03:50.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.08:03:50.66#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:50.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:50.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:50.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:50.66#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:03:50.66#ibcon#first serial, iclass 39, count 0 2006.245.08:03:50.66#ibcon#enter sib2, iclass 39, count 0 2006.245.08:03:50.66#ibcon#flushed, iclass 39, count 0 2006.245.08:03:50.66#ibcon#about to write, iclass 39, count 0 2006.245.08:03:50.66#ibcon#wrote, iclass 39, count 0 2006.245.08:03:50.66#ibcon#about to read 3, iclass 39, count 0 2006.245.08:03:50.69#ibcon#read 3, iclass 39, count 0 2006.245.08:03:50.69#ibcon#about to read 4, iclass 39, count 0 2006.245.08:03:50.69#ibcon#read 4, iclass 39, count 0 2006.245.08:03:50.69#ibcon#about to read 5, iclass 39, count 0 2006.245.08:03:50.69#ibcon#read 5, iclass 39, count 0 2006.245.08:03:50.69#ibcon#about to read 6, iclass 39, count 0 2006.245.08:03:50.69#ibcon#read 6, iclass 39, count 0 2006.245.08:03:50.69#ibcon#end of sib2, iclass 39, count 0 2006.245.08:03:50.69#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:03:50.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:03:50.69#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:03:50.69#ibcon#*before write, iclass 39, count 0 2006.245.08:03:50.69#ibcon#enter sib2, iclass 39, count 0 2006.245.08:03:50.69#ibcon#flushed, iclass 39, count 0 2006.245.08:03:50.69#ibcon#about to write, iclass 39, count 0 2006.245.08:03:50.69#ibcon#wrote, iclass 39, count 0 2006.245.08:03:50.69#ibcon#about to read 3, iclass 39, count 0 2006.245.08:03:50.73#ibcon#read 3, iclass 39, count 0 2006.245.08:03:50.73#ibcon#about to read 4, iclass 39, count 0 2006.245.08:03:50.73#ibcon#read 4, iclass 39, count 0 2006.245.08:03:50.73#ibcon#about to read 5, iclass 39, count 0 2006.245.08:03:50.73#ibcon#read 5, iclass 39, count 0 2006.245.08:03:50.73#ibcon#about to read 6, iclass 39, count 0 2006.245.08:03:50.73#ibcon#read 6, iclass 39, count 0 2006.245.08:03:50.73#ibcon#end of sib2, iclass 39, count 0 2006.245.08:03:50.73#ibcon#*after write, iclass 39, count 0 2006.245.08:03:50.73#ibcon#*before return 0, iclass 39, count 0 2006.245.08:03:50.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:50.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:50.73#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:03:50.73#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:03:50.73$vc4f8/va=2,7 2006.245.08:03:50.73#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.08:03:50.73#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.08:03:50.73#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:50.73#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:50.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:50.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:50.78#ibcon#enter wrdev, iclass 3, count 2 2006.245.08:03:50.78#ibcon#first serial, iclass 3, count 2 2006.245.08:03:50.78#ibcon#enter sib2, iclass 3, count 2 2006.245.08:03:50.78#ibcon#flushed, iclass 3, count 2 2006.245.08:03:50.78#ibcon#about to write, iclass 3, count 2 2006.245.08:03:50.78#ibcon#wrote, iclass 3, count 2 2006.245.08:03:50.78#ibcon#about to read 3, iclass 3, count 2 2006.245.08:03:50.80#ibcon#read 3, iclass 3, count 2 2006.245.08:03:50.80#ibcon#about to read 4, iclass 3, count 2 2006.245.08:03:50.80#ibcon#read 4, iclass 3, count 2 2006.245.08:03:50.80#ibcon#about to read 5, iclass 3, count 2 2006.245.08:03:50.80#ibcon#read 5, iclass 3, count 2 2006.245.08:03:50.80#ibcon#about to read 6, iclass 3, count 2 2006.245.08:03:50.80#ibcon#read 6, iclass 3, count 2 2006.245.08:03:50.80#ibcon#end of sib2, iclass 3, count 2 2006.245.08:03:50.80#ibcon#*mode == 0, iclass 3, count 2 2006.245.08:03:50.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.08:03:50.80#ibcon#[25=AT02-07\r\n] 2006.245.08:03:50.80#ibcon#*before write, iclass 3, count 2 2006.245.08:03:50.80#ibcon#enter sib2, iclass 3, count 2 2006.245.08:03:50.80#ibcon#flushed, iclass 3, count 2 2006.245.08:03:50.80#ibcon#about to write, iclass 3, count 2 2006.245.08:03:50.80#ibcon#wrote, iclass 3, count 2 2006.245.08:03:50.80#ibcon#about to read 3, iclass 3, count 2 2006.245.08:03:50.83#ibcon#read 3, iclass 3, count 2 2006.245.08:03:50.83#ibcon#about to read 4, iclass 3, count 2 2006.245.08:03:50.83#ibcon#read 4, iclass 3, count 2 2006.245.08:03:50.83#ibcon#about to read 5, iclass 3, count 2 2006.245.08:03:50.83#ibcon#read 5, iclass 3, count 2 2006.245.08:03:50.83#ibcon#about to read 6, iclass 3, count 2 2006.245.08:03:50.83#ibcon#read 6, iclass 3, count 2 2006.245.08:03:50.83#ibcon#end of sib2, iclass 3, count 2 2006.245.08:03:50.83#ibcon#*after write, iclass 3, count 2 2006.245.08:03:50.83#ibcon#*before return 0, iclass 3, count 2 2006.245.08:03:50.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:50.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:50.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.08:03:50.83#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:50.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:50.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:50.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:50.95#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:03:50.95#ibcon#first serial, iclass 3, count 0 2006.245.08:03:50.95#ibcon#enter sib2, iclass 3, count 0 2006.245.08:03:50.95#ibcon#flushed, iclass 3, count 0 2006.245.08:03:50.95#ibcon#about to write, iclass 3, count 0 2006.245.08:03:50.95#ibcon#wrote, iclass 3, count 0 2006.245.08:03:50.95#ibcon#about to read 3, iclass 3, count 0 2006.245.08:03:50.97#ibcon#read 3, iclass 3, count 0 2006.245.08:03:50.97#ibcon#about to read 4, iclass 3, count 0 2006.245.08:03:50.97#ibcon#read 4, iclass 3, count 0 2006.245.08:03:50.97#ibcon#about to read 5, iclass 3, count 0 2006.245.08:03:50.97#ibcon#read 5, iclass 3, count 0 2006.245.08:03:50.97#ibcon#about to read 6, iclass 3, count 0 2006.245.08:03:50.97#ibcon#read 6, iclass 3, count 0 2006.245.08:03:50.97#ibcon#end of sib2, iclass 3, count 0 2006.245.08:03:50.97#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:03:50.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:03:50.97#ibcon#[25=USB\r\n] 2006.245.08:03:50.97#ibcon#*before write, iclass 3, count 0 2006.245.08:03:50.97#ibcon#enter sib2, iclass 3, count 0 2006.245.08:03:50.97#ibcon#flushed, iclass 3, count 0 2006.245.08:03:50.97#ibcon#about to write, iclass 3, count 0 2006.245.08:03:50.97#ibcon#wrote, iclass 3, count 0 2006.245.08:03:50.97#ibcon#about to read 3, iclass 3, count 0 2006.245.08:03:51.00#ibcon#read 3, iclass 3, count 0 2006.245.08:03:51.00#ibcon#about to read 4, iclass 3, count 0 2006.245.08:03:51.00#ibcon#read 4, iclass 3, count 0 2006.245.08:03:51.00#ibcon#about to read 5, iclass 3, count 0 2006.245.08:03:51.00#ibcon#read 5, iclass 3, count 0 2006.245.08:03:51.00#ibcon#about to read 6, iclass 3, count 0 2006.245.08:03:51.00#ibcon#read 6, iclass 3, count 0 2006.245.08:03:51.00#ibcon#end of sib2, iclass 3, count 0 2006.245.08:03:51.00#ibcon#*after write, iclass 3, count 0 2006.245.08:03:51.00#ibcon#*before return 0, iclass 3, count 0 2006.245.08:03:51.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:51.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:51.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:03:51.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:03:51.00$vc4f8/valo=3,672.99 2006.245.08:03:51.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.08:03:51.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.08:03:51.00#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:51.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:51.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:51.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:51.00#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:03:51.00#ibcon#first serial, iclass 5, count 0 2006.245.08:03:51.00#ibcon#enter sib2, iclass 5, count 0 2006.245.08:03:51.00#ibcon#flushed, iclass 5, count 0 2006.245.08:03:51.00#ibcon#about to write, iclass 5, count 0 2006.245.08:03:51.00#ibcon#wrote, iclass 5, count 0 2006.245.08:03:51.00#ibcon#about to read 3, iclass 5, count 0 2006.245.08:03:51.03#ibcon#read 3, iclass 5, count 0 2006.245.08:03:51.03#ibcon#about to read 4, iclass 5, count 0 2006.245.08:03:51.03#ibcon#read 4, iclass 5, count 0 2006.245.08:03:51.03#ibcon#about to read 5, iclass 5, count 0 2006.245.08:03:51.03#ibcon#read 5, iclass 5, count 0 2006.245.08:03:51.03#ibcon#about to read 6, iclass 5, count 0 2006.245.08:03:51.03#ibcon#read 6, iclass 5, count 0 2006.245.08:03:51.03#ibcon#end of sib2, iclass 5, count 0 2006.245.08:03:51.03#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:03:51.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:03:51.03#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:03:51.03#ibcon#*before write, iclass 5, count 0 2006.245.08:03:51.03#ibcon#enter sib2, iclass 5, count 0 2006.245.08:03:51.03#ibcon#flushed, iclass 5, count 0 2006.245.08:03:51.03#ibcon#about to write, iclass 5, count 0 2006.245.08:03:51.03#ibcon#wrote, iclass 5, count 0 2006.245.08:03:51.03#ibcon#about to read 3, iclass 5, count 0 2006.245.08:03:51.07#ibcon#read 3, iclass 5, count 0 2006.245.08:03:51.07#ibcon#about to read 4, iclass 5, count 0 2006.245.08:03:51.07#ibcon#read 4, iclass 5, count 0 2006.245.08:03:51.07#ibcon#about to read 5, iclass 5, count 0 2006.245.08:03:51.07#ibcon#read 5, iclass 5, count 0 2006.245.08:03:51.07#ibcon#about to read 6, iclass 5, count 0 2006.245.08:03:51.07#ibcon#read 6, iclass 5, count 0 2006.245.08:03:51.07#ibcon#end of sib2, iclass 5, count 0 2006.245.08:03:51.07#ibcon#*after write, iclass 5, count 0 2006.245.08:03:51.07#ibcon#*before return 0, iclass 5, count 0 2006.245.08:03:51.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:51.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:51.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:03:51.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:03:51.07$vc4f8/va=3,6 2006.245.08:03:51.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.08:03:51.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.08:03:51.07#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:51.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:51.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:51.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:51.12#ibcon#enter wrdev, iclass 7, count 2 2006.245.08:03:51.12#ibcon#first serial, iclass 7, count 2 2006.245.08:03:51.12#ibcon#enter sib2, iclass 7, count 2 2006.245.08:03:51.12#ibcon#flushed, iclass 7, count 2 2006.245.08:03:51.12#ibcon#about to write, iclass 7, count 2 2006.245.08:03:51.12#ibcon#wrote, iclass 7, count 2 2006.245.08:03:51.12#ibcon#about to read 3, iclass 7, count 2 2006.245.08:03:51.14#ibcon#read 3, iclass 7, count 2 2006.245.08:03:51.14#ibcon#about to read 4, iclass 7, count 2 2006.245.08:03:51.14#ibcon#read 4, iclass 7, count 2 2006.245.08:03:51.14#ibcon#about to read 5, iclass 7, count 2 2006.245.08:03:51.14#ibcon#read 5, iclass 7, count 2 2006.245.08:03:51.14#ibcon#about to read 6, iclass 7, count 2 2006.245.08:03:51.14#ibcon#read 6, iclass 7, count 2 2006.245.08:03:51.14#ibcon#end of sib2, iclass 7, count 2 2006.245.08:03:51.14#ibcon#*mode == 0, iclass 7, count 2 2006.245.08:03:51.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.08:03:51.14#ibcon#[25=AT03-06\r\n] 2006.245.08:03:51.14#ibcon#*before write, iclass 7, count 2 2006.245.08:03:51.14#ibcon#enter sib2, iclass 7, count 2 2006.245.08:03:51.14#ibcon#flushed, iclass 7, count 2 2006.245.08:03:51.14#ibcon#about to write, iclass 7, count 2 2006.245.08:03:51.14#ibcon#wrote, iclass 7, count 2 2006.245.08:03:51.14#ibcon#about to read 3, iclass 7, count 2 2006.245.08:03:51.17#ibcon#read 3, iclass 7, count 2 2006.245.08:03:51.17#ibcon#about to read 4, iclass 7, count 2 2006.245.08:03:51.17#ibcon#read 4, iclass 7, count 2 2006.245.08:03:51.17#ibcon#about to read 5, iclass 7, count 2 2006.245.08:03:51.17#ibcon#read 5, iclass 7, count 2 2006.245.08:03:51.17#ibcon#about to read 6, iclass 7, count 2 2006.245.08:03:51.17#ibcon#read 6, iclass 7, count 2 2006.245.08:03:51.17#ibcon#end of sib2, iclass 7, count 2 2006.245.08:03:51.17#ibcon#*after write, iclass 7, count 2 2006.245.08:03:51.17#ibcon#*before return 0, iclass 7, count 2 2006.245.08:03:51.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:51.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:51.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.08:03:51.17#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:51.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:51.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:51.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:51.29#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:03:51.29#ibcon#first serial, iclass 7, count 0 2006.245.08:03:51.29#ibcon#enter sib2, iclass 7, count 0 2006.245.08:03:51.29#ibcon#flushed, iclass 7, count 0 2006.245.08:03:51.29#ibcon#about to write, iclass 7, count 0 2006.245.08:03:51.29#ibcon#wrote, iclass 7, count 0 2006.245.08:03:51.29#ibcon#about to read 3, iclass 7, count 0 2006.245.08:03:51.31#ibcon#read 3, iclass 7, count 0 2006.245.08:03:51.31#ibcon#about to read 4, iclass 7, count 0 2006.245.08:03:51.31#ibcon#read 4, iclass 7, count 0 2006.245.08:03:51.31#ibcon#about to read 5, iclass 7, count 0 2006.245.08:03:51.31#ibcon#read 5, iclass 7, count 0 2006.245.08:03:51.31#ibcon#about to read 6, iclass 7, count 0 2006.245.08:03:51.31#ibcon#read 6, iclass 7, count 0 2006.245.08:03:51.31#ibcon#end of sib2, iclass 7, count 0 2006.245.08:03:51.31#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:03:51.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:03:51.31#ibcon#[25=USB\r\n] 2006.245.08:03:51.31#ibcon#*before write, iclass 7, count 0 2006.245.08:03:51.31#ibcon#enter sib2, iclass 7, count 0 2006.245.08:03:51.31#ibcon#flushed, iclass 7, count 0 2006.245.08:03:51.31#ibcon#about to write, iclass 7, count 0 2006.245.08:03:51.31#ibcon#wrote, iclass 7, count 0 2006.245.08:03:51.31#ibcon#about to read 3, iclass 7, count 0 2006.245.08:03:51.34#ibcon#read 3, iclass 7, count 0 2006.245.08:03:51.34#ibcon#about to read 4, iclass 7, count 0 2006.245.08:03:51.34#ibcon#read 4, iclass 7, count 0 2006.245.08:03:51.34#ibcon#about to read 5, iclass 7, count 0 2006.245.08:03:51.34#ibcon#read 5, iclass 7, count 0 2006.245.08:03:51.34#ibcon#about to read 6, iclass 7, count 0 2006.245.08:03:51.34#ibcon#read 6, iclass 7, count 0 2006.245.08:03:51.34#ibcon#end of sib2, iclass 7, count 0 2006.245.08:03:51.34#ibcon#*after write, iclass 7, count 0 2006.245.08:03:51.34#ibcon#*before return 0, iclass 7, count 0 2006.245.08:03:51.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:51.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:51.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:03:51.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:03:51.34$vc4f8/valo=4,832.99 2006.245.08:03:51.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.08:03:51.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.08:03:51.34#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:51.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:51.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:51.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:51.34#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:03:51.34#ibcon#first serial, iclass 11, count 0 2006.245.08:03:51.34#ibcon#enter sib2, iclass 11, count 0 2006.245.08:03:51.34#ibcon#flushed, iclass 11, count 0 2006.245.08:03:51.34#ibcon#about to write, iclass 11, count 0 2006.245.08:03:51.34#ibcon#wrote, iclass 11, count 0 2006.245.08:03:51.34#ibcon#about to read 3, iclass 11, count 0 2006.245.08:03:51.37#ibcon#read 3, iclass 11, count 0 2006.245.08:03:51.37#ibcon#about to read 4, iclass 11, count 0 2006.245.08:03:51.37#ibcon#read 4, iclass 11, count 0 2006.245.08:03:51.37#ibcon#about to read 5, iclass 11, count 0 2006.245.08:03:51.37#ibcon#read 5, iclass 11, count 0 2006.245.08:03:51.37#ibcon#about to read 6, iclass 11, count 0 2006.245.08:03:51.37#ibcon#read 6, iclass 11, count 0 2006.245.08:03:51.37#ibcon#end of sib2, iclass 11, count 0 2006.245.08:03:51.37#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:03:51.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:03:51.37#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:03:51.37#ibcon#*before write, iclass 11, count 0 2006.245.08:03:51.37#ibcon#enter sib2, iclass 11, count 0 2006.245.08:03:51.37#ibcon#flushed, iclass 11, count 0 2006.245.08:03:51.37#ibcon#about to write, iclass 11, count 0 2006.245.08:03:51.37#ibcon#wrote, iclass 11, count 0 2006.245.08:03:51.37#ibcon#about to read 3, iclass 11, count 0 2006.245.08:03:51.41#ibcon#read 3, iclass 11, count 0 2006.245.08:03:51.41#ibcon#about to read 4, iclass 11, count 0 2006.245.08:03:51.41#ibcon#read 4, iclass 11, count 0 2006.245.08:03:51.41#ibcon#about to read 5, iclass 11, count 0 2006.245.08:03:51.41#ibcon#read 5, iclass 11, count 0 2006.245.08:03:51.41#ibcon#about to read 6, iclass 11, count 0 2006.245.08:03:51.41#ibcon#read 6, iclass 11, count 0 2006.245.08:03:51.41#ibcon#end of sib2, iclass 11, count 0 2006.245.08:03:51.41#ibcon#*after write, iclass 11, count 0 2006.245.08:03:51.41#ibcon#*before return 0, iclass 11, count 0 2006.245.08:03:51.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:51.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:51.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:03:51.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:03:51.41$vc4f8/va=4,7 2006.245.08:03:51.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:03:51.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:03:51.41#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:51.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:51.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:51.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:51.46#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:03:51.46#ibcon#first serial, iclass 13, count 2 2006.245.08:03:51.46#ibcon#enter sib2, iclass 13, count 2 2006.245.08:03:51.46#ibcon#flushed, iclass 13, count 2 2006.245.08:03:51.46#ibcon#about to write, iclass 13, count 2 2006.245.08:03:51.46#ibcon#wrote, iclass 13, count 2 2006.245.08:03:51.46#ibcon#about to read 3, iclass 13, count 2 2006.245.08:03:51.48#ibcon#read 3, iclass 13, count 2 2006.245.08:03:51.48#ibcon#about to read 4, iclass 13, count 2 2006.245.08:03:51.48#ibcon#read 4, iclass 13, count 2 2006.245.08:03:51.48#ibcon#about to read 5, iclass 13, count 2 2006.245.08:03:51.48#ibcon#read 5, iclass 13, count 2 2006.245.08:03:51.48#ibcon#about to read 6, iclass 13, count 2 2006.245.08:03:51.48#ibcon#read 6, iclass 13, count 2 2006.245.08:03:51.48#ibcon#end of sib2, iclass 13, count 2 2006.245.08:03:51.48#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:03:51.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:03:51.48#ibcon#[25=AT04-07\r\n] 2006.245.08:03:51.48#ibcon#*before write, iclass 13, count 2 2006.245.08:03:51.48#ibcon#enter sib2, iclass 13, count 2 2006.245.08:03:51.48#ibcon#flushed, iclass 13, count 2 2006.245.08:03:51.48#ibcon#about to write, iclass 13, count 2 2006.245.08:03:51.48#ibcon#wrote, iclass 13, count 2 2006.245.08:03:51.48#ibcon#about to read 3, iclass 13, count 2 2006.245.08:03:51.51#ibcon#read 3, iclass 13, count 2 2006.245.08:03:51.51#ibcon#about to read 4, iclass 13, count 2 2006.245.08:03:51.51#ibcon#read 4, iclass 13, count 2 2006.245.08:03:51.51#ibcon#about to read 5, iclass 13, count 2 2006.245.08:03:51.51#ibcon#read 5, iclass 13, count 2 2006.245.08:03:51.51#ibcon#about to read 6, iclass 13, count 2 2006.245.08:03:51.51#ibcon#read 6, iclass 13, count 2 2006.245.08:03:51.51#ibcon#end of sib2, iclass 13, count 2 2006.245.08:03:51.51#ibcon#*after write, iclass 13, count 2 2006.245.08:03:51.51#ibcon#*before return 0, iclass 13, count 2 2006.245.08:03:51.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:51.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:51.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:03:51.51#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:51.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:51.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:51.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:51.63#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:03:51.63#ibcon#first serial, iclass 13, count 0 2006.245.08:03:51.63#ibcon#enter sib2, iclass 13, count 0 2006.245.08:03:51.63#ibcon#flushed, iclass 13, count 0 2006.245.08:03:51.63#ibcon#about to write, iclass 13, count 0 2006.245.08:03:51.63#ibcon#wrote, iclass 13, count 0 2006.245.08:03:51.63#ibcon#about to read 3, iclass 13, count 0 2006.245.08:03:51.65#ibcon#read 3, iclass 13, count 0 2006.245.08:03:51.65#ibcon#about to read 4, iclass 13, count 0 2006.245.08:03:51.65#ibcon#read 4, iclass 13, count 0 2006.245.08:03:51.65#ibcon#about to read 5, iclass 13, count 0 2006.245.08:03:51.65#ibcon#read 5, iclass 13, count 0 2006.245.08:03:51.65#ibcon#about to read 6, iclass 13, count 0 2006.245.08:03:51.65#ibcon#read 6, iclass 13, count 0 2006.245.08:03:51.65#ibcon#end of sib2, iclass 13, count 0 2006.245.08:03:51.65#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:03:51.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:03:51.65#ibcon#[25=USB\r\n] 2006.245.08:03:51.65#ibcon#*before write, iclass 13, count 0 2006.245.08:03:51.65#ibcon#enter sib2, iclass 13, count 0 2006.245.08:03:51.65#ibcon#flushed, iclass 13, count 0 2006.245.08:03:51.65#ibcon#about to write, iclass 13, count 0 2006.245.08:03:51.65#ibcon#wrote, iclass 13, count 0 2006.245.08:03:51.65#ibcon#about to read 3, iclass 13, count 0 2006.245.08:03:51.68#ibcon#read 3, iclass 13, count 0 2006.245.08:03:51.68#ibcon#about to read 4, iclass 13, count 0 2006.245.08:03:51.68#ibcon#read 4, iclass 13, count 0 2006.245.08:03:51.68#ibcon#about to read 5, iclass 13, count 0 2006.245.08:03:51.68#ibcon#read 5, iclass 13, count 0 2006.245.08:03:51.68#ibcon#about to read 6, iclass 13, count 0 2006.245.08:03:51.68#ibcon#read 6, iclass 13, count 0 2006.245.08:03:51.68#ibcon#end of sib2, iclass 13, count 0 2006.245.08:03:51.68#ibcon#*after write, iclass 13, count 0 2006.245.08:03:51.68#ibcon#*before return 0, iclass 13, count 0 2006.245.08:03:51.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:51.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:51.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:03:51.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:03:51.68$vc4f8/valo=5,652.99 2006.245.08:03:51.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.08:03:51.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.08:03:51.68#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:51.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:51.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:51.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:51.68#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:03:51.68#ibcon#first serial, iclass 15, count 0 2006.245.08:03:51.68#ibcon#enter sib2, iclass 15, count 0 2006.245.08:03:51.68#ibcon#flushed, iclass 15, count 0 2006.245.08:03:51.68#ibcon#about to write, iclass 15, count 0 2006.245.08:03:51.68#ibcon#wrote, iclass 15, count 0 2006.245.08:03:51.68#ibcon#about to read 3, iclass 15, count 0 2006.245.08:03:51.70#ibcon#read 3, iclass 15, count 0 2006.245.08:03:51.70#ibcon#about to read 4, iclass 15, count 0 2006.245.08:03:51.70#ibcon#read 4, iclass 15, count 0 2006.245.08:03:51.70#ibcon#about to read 5, iclass 15, count 0 2006.245.08:03:51.70#ibcon#read 5, iclass 15, count 0 2006.245.08:03:51.70#ibcon#about to read 6, iclass 15, count 0 2006.245.08:03:51.70#ibcon#read 6, iclass 15, count 0 2006.245.08:03:51.70#ibcon#end of sib2, iclass 15, count 0 2006.245.08:03:51.70#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:03:51.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:03:51.70#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:03:51.70#ibcon#*before write, iclass 15, count 0 2006.245.08:03:51.70#ibcon#enter sib2, iclass 15, count 0 2006.245.08:03:51.70#ibcon#flushed, iclass 15, count 0 2006.245.08:03:51.70#ibcon#about to write, iclass 15, count 0 2006.245.08:03:51.70#ibcon#wrote, iclass 15, count 0 2006.245.08:03:51.70#ibcon#about to read 3, iclass 15, count 0 2006.245.08:03:51.74#ibcon#read 3, iclass 15, count 0 2006.245.08:03:51.74#ibcon#about to read 4, iclass 15, count 0 2006.245.08:03:51.74#ibcon#read 4, iclass 15, count 0 2006.245.08:03:51.74#ibcon#about to read 5, iclass 15, count 0 2006.245.08:03:51.74#ibcon#read 5, iclass 15, count 0 2006.245.08:03:51.74#ibcon#about to read 6, iclass 15, count 0 2006.245.08:03:51.74#ibcon#read 6, iclass 15, count 0 2006.245.08:03:51.74#ibcon#end of sib2, iclass 15, count 0 2006.245.08:03:51.74#ibcon#*after write, iclass 15, count 0 2006.245.08:03:51.74#ibcon#*before return 0, iclass 15, count 0 2006.245.08:03:51.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:51.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:51.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:03:51.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:03:51.74$vc4f8/va=5,7 2006.245.08:03:51.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.08:03:51.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.08:03:51.74#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:51.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:51.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:51.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:51.80#ibcon#enter wrdev, iclass 17, count 2 2006.245.08:03:51.80#ibcon#first serial, iclass 17, count 2 2006.245.08:03:51.80#ibcon#enter sib2, iclass 17, count 2 2006.245.08:03:51.80#ibcon#flushed, iclass 17, count 2 2006.245.08:03:51.80#ibcon#about to write, iclass 17, count 2 2006.245.08:03:51.80#ibcon#wrote, iclass 17, count 2 2006.245.08:03:51.80#ibcon#about to read 3, iclass 17, count 2 2006.245.08:03:51.82#ibcon#read 3, iclass 17, count 2 2006.245.08:03:51.82#ibcon#about to read 4, iclass 17, count 2 2006.245.08:03:51.82#ibcon#read 4, iclass 17, count 2 2006.245.08:03:51.82#ibcon#about to read 5, iclass 17, count 2 2006.245.08:03:51.82#ibcon#read 5, iclass 17, count 2 2006.245.08:03:51.82#ibcon#about to read 6, iclass 17, count 2 2006.245.08:03:51.82#ibcon#read 6, iclass 17, count 2 2006.245.08:03:51.82#ibcon#end of sib2, iclass 17, count 2 2006.245.08:03:51.82#ibcon#*mode == 0, iclass 17, count 2 2006.245.08:03:51.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.08:03:51.82#ibcon#[25=AT05-07\r\n] 2006.245.08:03:51.82#ibcon#*before write, iclass 17, count 2 2006.245.08:03:51.82#ibcon#enter sib2, iclass 17, count 2 2006.245.08:03:51.82#ibcon#flushed, iclass 17, count 2 2006.245.08:03:51.82#ibcon#about to write, iclass 17, count 2 2006.245.08:03:51.82#ibcon#wrote, iclass 17, count 2 2006.245.08:03:51.82#ibcon#about to read 3, iclass 17, count 2 2006.245.08:03:51.85#ibcon#read 3, iclass 17, count 2 2006.245.08:03:51.85#ibcon#about to read 4, iclass 17, count 2 2006.245.08:03:51.85#ibcon#read 4, iclass 17, count 2 2006.245.08:03:51.85#ibcon#about to read 5, iclass 17, count 2 2006.245.08:03:51.85#ibcon#read 5, iclass 17, count 2 2006.245.08:03:51.85#ibcon#about to read 6, iclass 17, count 2 2006.245.08:03:51.85#ibcon#read 6, iclass 17, count 2 2006.245.08:03:51.85#ibcon#end of sib2, iclass 17, count 2 2006.245.08:03:51.85#ibcon#*after write, iclass 17, count 2 2006.245.08:03:51.85#ibcon#*before return 0, iclass 17, count 2 2006.245.08:03:51.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:51.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:51.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.08:03:51.85#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:51.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:51.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:51.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:51.97#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:03:51.97#ibcon#first serial, iclass 17, count 0 2006.245.08:03:51.97#ibcon#enter sib2, iclass 17, count 0 2006.245.08:03:51.97#ibcon#flushed, iclass 17, count 0 2006.245.08:03:51.97#ibcon#about to write, iclass 17, count 0 2006.245.08:03:51.97#ibcon#wrote, iclass 17, count 0 2006.245.08:03:51.97#ibcon#about to read 3, iclass 17, count 0 2006.245.08:03:51.99#ibcon#read 3, iclass 17, count 0 2006.245.08:03:51.99#ibcon#about to read 4, iclass 17, count 0 2006.245.08:03:51.99#ibcon#read 4, iclass 17, count 0 2006.245.08:03:51.99#ibcon#about to read 5, iclass 17, count 0 2006.245.08:03:51.99#ibcon#read 5, iclass 17, count 0 2006.245.08:03:51.99#ibcon#about to read 6, iclass 17, count 0 2006.245.08:03:51.99#ibcon#read 6, iclass 17, count 0 2006.245.08:03:51.99#ibcon#end of sib2, iclass 17, count 0 2006.245.08:03:51.99#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:03:51.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:03:51.99#ibcon#[25=USB\r\n] 2006.245.08:03:51.99#ibcon#*before write, iclass 17, count 0 2006.245.08:03:51.99#ibcon#enter sib2, iclass 17, count 0 2006.245.08:03:51.99#ibcon#flushed, iclass 17, count 0 2006.245.08:03:51.99#ibcon#about to write, iclass 17, count 0 2006.245.08:03:51.99#ibcon#wrote, iclass 17, count 0 2006.245.08:03:51.99#ibcon#about to read 3, iclass 17, count 0 2006.245.08:03:52.02#ibcon#read 3, iclass 17, count 0 2006.245.08:03:52.02#ibcon#about to read 4, iclass 17, count 0 2006.245.08:03:52.02#ibcon#read 4, iclass 17, count 0 2006.245.08:03:52.02#ibcon#about to read 5, iclass 17, count 0 2006.245.08:03:52.02#ibcon#read 5, iclass 17, count 0 2006.245.08:03:52.02#ibcon#about to read 6, iclass 17, count 0 2006.245.08:03:52.02#ibcon#read 6, iclass 17, count 0 2006.245.08:03:52.02#ibcon#end of sib2, iclass 17, count 0 2006.245.08:03:52.02#ibcon#*after write, iclass 17, count 0 2006.245.08:03:52.02#ibcon#*before return 0, iclass 17, count 0 2006.245.08:03:52.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:52.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:52.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:03:52.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:03:52.02$vc4f8/valo=6,772.99 2006.245.08:03:52.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.08:03:52.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.08:03:52.02#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:52.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:52.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:52.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:52.02#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:03:52.02#ibcon#first serial, iclass 19, count 0 2006.245.08:03:52.02#ibcon#enter sib2, iclass 19, count 0 2006.245.08:03:52.02#ibcon#flushed, iclass 19, count 0 2006.245.08:03:52.02#ibcon#about to write, iclass 19, count 0 2006.245.08:03:52.02#ibcon#wrote, iclass 19, count 0 2006.245.08:03:52.02#ibcon#about to read 3, iclass 19, count 0 2006.245.08:03:52.04#ibcon#read 3, iclass 19, count 0 2006.245.08:03:52.04#ibcon#about to read 4, iclass 19, count 0 2006.245.08:03:52.04#ibcon#read 4, iclass 19, count 0 2006.245.08:03:52.04#ibcon#about to read 5, iclass 19, count 0 2006.245.08:03:52.04#ibcon#read 5, iclass 19, count 0 2006.245.08:03:52.04#ibcon#about to read 6, iclass 19, count 0 2006.245.08:03:52.04#ibcon#read 6, iclass 19, count 0 2006.245.08:03:52.04#ibcon#end of sib2, iclass 19, count 0 2006.245.08:03:52.04#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:03:52.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:03:52.04#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:03:52.04#ibcon#*before write, iclass 19, count 0 2006.245.08:03:52.04#ibcon#enter sib2, iclass 19, count 0 2006.245.08:03:52.04#ibcon#flushed, iclass 19, count 0 2006.245.08:03:52.04#ibcon#about to write, iclass 19, count 0 2006.245.08:03:52.04#ibcon#wrote, iclass 19, count 0 2006.245.08:03:52.04#ibcon#about to read 3, iclass 19, count 0 2006.245.08:03:52.08#ibcon#read 3, iclass 19, count 0 2006.245.08:03:52.08#ibcon#about to read 4, iclass 19, count 0 2006.245.08:03:52.08#ibcon#read 4, iclass 19, count 0 2006.245.08:03:52.08#ibcon#about to read 5, iclass 19, count 0 2006.245.08:03:52.08#ibcon#read 5, iclass 19, count 0 2006.245.08:03:52.08#ibcon#about to read 6, iclass 19, count 0 2006.245.08:03:52.08#ibcon#read 6, iclass 19, count 0 2006.245.08:03:52.08#ibcon#end of sib2, iclass 19, count 0 2006.245.08:03:52.08#ibcon#*after write, iclass 19, count 0 2006.245.08:03:52.08#ibcon#*before return 0, iclass 19, count 0 2006.245.08:03:52.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:52.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:52.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:03:52.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:03:52.08$vc4f8/va=6,7 2006.245.08:03:52.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.08:03:52.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.08:03:52.08#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:52.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:03:52.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:03:52.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:03:52.15#ibcon#enter wrdev, iclass 21, count 2 2006.245.08:03:52.15#ibcon#first serial, iclass 21, count 2 2006.245.08:03:52.15#ibcon#enter sib2, iclass 21, count 2 2006.245.08:03:52.15#ibcon#flushed, iclass 21, count 2 2006.245.08:03:52.15#ibcon#about to write, iclass 21, count 2 2006.245.08:03:52.15#ibcon#wrote, iclass 21, count 2 2006.245.08:03:52.15#ibcon#about to read 3, iclass 21, count 2 2006.245.08:03:52.16#ibcon#read 3, iclass 21, count 2 2006.245.08:03:52.16#ibcon#about to read 4, iclass 21, count 2 2006.245.08:03:52.16#ibcon#read 4, iclass 21, count 2 2006.245.08:03:52.16#ibcon#about to read 5, iclass 21, count 2 2006.245.08:03:52.16#ibcon#read 5, iclass 21, count 2 2006.245.08:03:52.16#ibcon#about to read 6, iclass 21, count 2 2006.245.08:03:52.16#ibcon#read 6, iclass 21, count 2 2006.245.08:03:52.16#ibcon#end of sib2, iclass 21, count 2 2006.245.08:03:52.16#ibcon#*mode == 0, iclass 21, count 2 2006.245.08:03:52.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.08:03:52.16#ibcon#[25=AT06-07\r\n] 2006.245.08:03:52.16#ibcon#*before write, iclass 21, count 2 2006.245.08:03:52.16#ibcon#enter sib2, iclass 21, count 2 2006.245.08:03:52.16#ibcon#flushed, iclass 21, count 2 2006.245.08:03:52.16#ibcon#about to write, iclass 21, count 2 2006.245.08:03:52.16#ibcon#wrote, iclass 21, count 2 2006.245.08:03:52.16#ibcon#about to read 3, iclass 21, count 2 2006.245.08:03:52.19#ibcon#read 3, iclass 21, count 2 2006.245.08:03:52.19#ibcon#about to read 4, iclass 21, count 2 2006.245.08:03:52.19#ibcon#read 4, iclass 21, count 2 2006.245.08:03:52.19#ibcon#about to read 5, iclass 21, count 2 2006.245.08:03:52.19#ibcon#read 5, iclass 21, count 2 2006.245.08:03:52.19#ibcon#about to read 6, iclass 21, count 2 2006.245.08:03:52.19#ibcon#read 6, iclass 21, count 2 2006.245.08:03:52.19#ibcon#end of sib2, iclass 21, count 2 2006.245.08:03:52.19#ibcon#*after write, iclass 21, count 2 2006.245.08:03:52.19#ibcon#*before return 0, iclass 21, count 2 2006.245.08:03:52.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:03:52.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:03:52.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.08:03:52.19#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:52.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:03:52.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:03:52.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:03:52.31#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:03:52.31#ibcon#first serial, iclass 21, count 0 2006.245.08:03:52.31#ibcon#enter sib2, iclass 21, count 0 2006.245.08:03:52.31#ibcon#flushed, iclass 21, count 0 2006.245.08:03:52.31#ibcon#about to write, iclass 21, count 0 2006.245.08:03:52.31#ibcon#wrote, iclass 21, count 0 2006.245.08:03:52.31#ibcon#about to read 3, iclass 21, count 0 2006.245.08:03:52.33#ibcon#read 3, iclass 21, count 0 2006.245.08:03:52.33#ibcon#about to read 4, iclass 21, count 0 2006.245.08:03:52.33#ibcon#read 4, iclass 21, count 0 2006.245.08:03:52.33#ibcon#about to read 5, iclass 21, count 0 2006.245.08:03:52.33#ibcon#read 5, iclass 21, count 0 2006.245.08:03:52.33#ibcon#about to read 6, iclass 21, count 0 2006.245.08:03:52.33#ibcon#read 6, iclass 21, count 0 2006.245.08:03:52.33#ibcon#end of sib2, iclass 21, count 0 2006.245.08:03:52.33#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:03:52.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:03:52.33#ibcon#[25=USB\r\n] 2006.245.08:03:52.33#ibcon#*before write, iclass 21, count 0 2006.245.08:03:52.33#ibcon#enter sib2, iclass 21, count 0 2006.245.08:03:52.33#ibcon#flushed, iclass 21, count 0 2006.245.08:03:52.33#ibcon#about to write, iclass 21, count 0 2006.245.08:03:52.33#ibcon#wrote, iclass 21, count 0 2006.245.08:03:52.33#ibcon#about to read 3, iclass 21, count 0 2006.245.08:03:52.36#ibcon#read 3, iclass 21, count 0 2006.245.08:03:52.36#ibcon#about to read 4, iclass 21, count 0 2006.245.08:03:52.36#ibcon#read 4, iclass 21, count 0 2006.245.08:03:52.36#ibcon#about to read 5, iclass 21, count 0 2006.245.08:03:52.36#ibcon#read 5, iclass 21, count 0 2006.245.08:03:52.36#ibcon#about to read 6, iclass 21, count 0 2006.245.08:03:52.36#ibcon#read 6, iclass 21, count 0 2006.245.08:03:52.36#ibcon#end of sib2, iclass 21, count 0 2006.245.08:03:52.36#ibcon#*after write, iclass 21, count 0 2006.245.08:03:52.36#ibcon#*before return 0, iclass 21, count 0 2006.245.08:03:52.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:03:52.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:03:52.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:03:52.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:03:52.36$vc4f8/valo=7,832.99 2006.245.08:03:52.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.08:03:52.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.08:03:52.36#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:52.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:03:52.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:03:52.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:03:52.36#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:03:52.36#ibcon#first serial, iclass 23, count 0 2006.245.08:03:52.36#ibcon#enter sib2, iclass 23, count 0 2006.245.08:03:52.36#ibcon#flushed, iclass 23, count 0 2006.245.08:03:52.36#ibcon#about to write, iclass 23, count 0 2006.245.08:03:52.36#ibcon#wrote, iclass 23, count 0 2006.245.08:03:52.36#ibcon#about to read 3, iclass 23, count 0 2006.245.08:03:52.38#ibcon#read 3, iclass 23, count 0 2006.245.08:03:52.38#ibcon#about to read 4, iclass 23, count 0 2006.245.08:03:52.38#ibcon#read 4, iclass 23, count 0 2006.245.08:03:52.38#ibcon#about to read 5, iclass 23, count 0 2006.245.08:03:52.38#ibcon#read 5, iclass 23, count 0 2006.245.08:03:52.38#ibcon#about to read 6, iclass 23, count 0 2006.245.08:03:52.38#ibcon#read 6, iclass 23, count 0 2006.245.08:03:52.38#ibcon#end of sib2, iclass 23, count 0 2006.245.08:03:52.38#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:03:52.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:03:52.38#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:03:52.38#ibcon#*before write, iclass 23, count 0 2006.245.08:03:52.38#ibcon#enter sib2, iclass 23, count 0 2006.245.08:03:52.38#ibcon#flushed, iclass 23, count 0 2006.245.08:03:52.38#ibcon#about to write, iclass 23, count 0 2006.245.08:03:52.38#ibcon#wrote, iclass 23, count 0 2006.245.08:03:52.38#ibcon#about to read 3, iclass 23, count 0 2006.245.08:03:52.42#ibcon#read 3, iclass 23, count 0 2006.245.08:03:52.42#ibcon#about to read 4, iclass 23, count 0 2006.245.08:03:52.42#ibcon#read 4, iclass 23, count 0 2006.245.08:03:52.42#ibcon#about to read 5, iclass 23, count 0 2006.245.08:03:52.42#ibcon#read 5, iclass 23, count 0 2006.245.08:03:52.42#ibcon#about to read 6, iclass 23, count 0 2006.245.08:03:52.42#ibcon#read 6, iclass 23, count 0 2006.245.08:03:52.42#ibcon#end of sib2, iclass 23, count 0 2006.245.08:03:52.42#ibcon#*after write, iclass 23, count 0 2006.245.08:03:52.42#ibcon#*before return 0, iclass 23, count 0 2006.245.08:03:52.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:03:52.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:03:52.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:03:52.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:03:52.42$vc4f8/va=7,7 2006.245.08:03:52.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.08:03:52.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.08:03:52.42#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:52.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:03:52.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:03:52.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:03:52.48#ibcon#enter wrdev, iclass 25, count 2 2006.245.08:03:52.48#ibcon#first serial, iclass 25, count 2 2006.245.08:03:52.48#ibcon#enter sib2, iclass 25, count 2 2006.245.08:03:52.48#ibcon#flushed, iclass 25, count 2 2006.245.08:03:52.48#ibcon#about to write, iclass 25, count 2 2006.245.08:03:52.48#ibcon#wrote, iclass 25, count 2 2006.245.08:03:52.48#ibcon#about to read 3, iclass 25, count 2 2006.245.08:03:52.50#ibcon#read 3, iclass 25, count 2 2006.245.08:03:52.50#ibcon#about to read 4, iclass 25, count 2 2006.245.08:03:52.50#ibcon#read 4, iclass 25, count 2 2006.245.08:03:52.50#ibcon#about to read 5, iclass 25, count 2 2006.245.08:03:52.50#ibcon#read 5, iclass 25, count 2 2006.245.08:03:52.50#ibcon#about to read 6, iclass 25, count 2 2006.245.08:03:52.50#ibcon#read 6, iclass 25, count 2 2006.245.08:03:52.50#ibcon#end of sib2, iclass 25, count 2 2006.245.08:03:52.50#ibcon#*mode == 0, iclass 25, count 2 2006.245.08:03:52.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.08:03:52.50#ibcon#[25=AT07-07\r\n] 2006.245.08:03:52.50#ibcon#*before write, iclass 25, count 2 2006.245.08:03:52.50#ibcon#enter sib2, iclass 25, count 2 2006.245.08:03:52.50#ibcon#flushed, iclass 25, count 2 2006.245.08:03:52.50#ibcon#about to write, iclass 25, count 2 2006.245.08:03:52.50#ibcon#wrote, iclass 25, count 2 2006.245.08:03:52.50#ibcon#about to read 3, iclass 25, count 2 2006.245.08:03:52.53#ibcon#read 3, iclass 25, count 2 2006.245.08:03:52.53#ibcon#about to read 4, iclass 25, count 2 2006.245.08:03:52.53#ibcon#read 4, iclass 25, count 2 2006.245.08:03:52.53#ibcon#about to read 5, iclass 25, count 2 2006.245.08:03:52.53#ibcon#read 5, iclass 25, count 2 2006.245.08:03:52.53#ibcon#about to read 6, iclass 25, count 2 2006.245.08:03:52.53#ibcon#read 6, iclass 25, count 2 2006.245.08:03:52.53#ibcon#end of sib2, iclass 25, count 2 2006.245.08:03:52.53#ibcon#*after write, iclass 25, count 2 2006.245.08:03:52.53#ibcon#*before return 0, iclass 25, count 2 2006.245.08:03:52.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:03:52.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:03:52.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.08:03:52.53#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:52.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:03:52.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:03:52.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:03:52.65#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:03:52.65#ibcon#first serial, iclass 25, count 0 2006.245.08:03:52.65#ibcon#enter sib2, iclass 25, count 0 2006.245.08:03:52.65#ibcon#flushed, iclass 25, count 0 2006.245.08:03:52.65#ibcon#about to write, iclass 25, count 0 2006.245.08:03:52.65#ibcon#wrote, iclass 25, count 0 2006.245.08:03:52.65#ibcon#about to read 3, iclass 25, count 0 2006.245.08:03:52.67#ibcon#read 3, iclass 25, count 0 2006.245.08:03:52.67#ibcon#about to read 4, iclass 25, count 0 2006.245.08:03:52.67#ibcon#read 4, iclass 25, count 0 2006.245.08:03:52.67#ibcon#about to read 5, iclass 25, count 0 2006.245.08:03:52.67#ibcon#read 5, iclass 25, count 0 2006.245.08:03:52.67#ibcon#about to read 6, iclass 25, count 0 2006.245.08:03:52.67#ibcon#read 6, iclass 25, count 0 2006.245.08:03:52.67#ibcon#end of sib2, iclass 25, count 0 2006.245.08:03:52.67#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:03:52.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:03:52.67#ibcon#[25=USB\r\n] 2006.245.08:03:52.67#ibcon#*before write, iclass 25, count 0 2006.245.08:03:52.67#ibcon#enter sib2, iclass 25, count 0 2006.245.08:03:52.67#ibcon#flushed, iclass 25, count 0 2006.245.08:03:52.67#ibcon#about to write, iclass 25, count 0 2006.245.08:03:52.67#ibcon#wrote, iclass 25, count 0 2006.245.08:03:52.67#ibcon#about to read 3, iclass 25, count 0 2006.245.08:03:52.70#ibcon#read 3, iclass 25, count 0 2006.245.08:03:52.70#ibcon#about to read 4, iclass 25, count 0 2006.245.08:03:52.70#ibcon#read 4, iclass 25, count 0 2006.245.08:03:52.70#ibcon#about to read 5, iclass 25, count 0 2006.245.08:03:52.70#ibcon#read 5, iclass 25, count 0 2006.245.08:03:52.70#ibcon#about to read 6, iclass 25, count 0 2006.245.08:03:52.70#ibcon#read 6, iclass 25, count 0 2006.245.08:03:52.70#ibcon#end of sib2, iclass 25, count 0 2006.245.08:03:52.70#ibcon#*after write, iclass 25, count 0 2006.245.08:03:52.70#ibcon#*before return 0, iclass 25, count 0 2006.245.08:03:52.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:03:52.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:03:52.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:03:52.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:03:52.70$vc4f8/valo=8,852.99 2006.245.08:03:52.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.08:03:52.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.08:03:52.70#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:52.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:03:52.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:03:52.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:03:52.70#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:03:52.70#ibcon#first serial, iclass 27, count 0 2006.245.08:03:52.70#ibcon#enter sib2, iclass 27, count 0 2006.245.08:03:52.70#ibcon#flushed, iclass 27, count 0 2006.245.08:03:52.70#ibcon#about to write, iclass 27, count 0 2006.245.08:03:52.70#ibcon#wrote, iclass 27, count 0 2006.245.08:03:52.70#ibcon#about to read 3, iclass 27, count 0 2006.245.08:03:52.72#ibcon#read 3, iclass 27, count 0 2006.245.08:03:52.72#ibcon#about to read 4, iclass 27, count 0 2006.245.08:03:52.72#ibcon#read 4, iclass 27, count 0 2006.245.08:03:52.72#ibcon#about to read 5, iclass 27, count 0 2006.245.08:03:52.72#ibcon#read 5, iclass 27, count 0 2006.245.08:03:52.72#ibcon#about to read 6, iclass 27, count 0 2006.245.08:03:52.72#ibcon#read 6, iclass 27, count 0 2006.245.08:03:52.72#ibcon#end of sib2, iclass 27, count 0 2006.245.08:03:52.72#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:03:52.72#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:03:52.72#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:03:52.72#ibcon#*before write, iclass 27, count 0 2006.245.08:03:52.72#ibcon#enter sib2, iclass 27, count 0 2006.245.08:03:52.72#ibcon#flushed, iclass 27, count 0 2006.245.08:03:52.72#ibcon#about to write, iclass 27, count 0 2006.245.08:03:52.72#ibcon#wrote, iclass 27, count 0 2006.245.08:03:52.72#ibcon#about to read 3, iclass 27, count 0 2006.245.08:03:52.76#ibcon#read 3, iclass 27, count 0 2006.245.08:03:52.76#ibcon#about to read 4, iclass 27, count 0 2006.245.08:03:52.76#ibcon#read 4, iclass 27, count 0 2006.245.08:03:52.76#ibcon#about to read 5, iclass 27, count 0 2006.245.08:03:52.76#ibcon#read 5, iclass 27, count 0 2006.245.08:03:52.76#ibcon#about to read 6, iclass 27, count 0 2006.245.08:03:52.76#ibcon#read 6, iclass 27, count 0 2006.245.08:03:52.76#ibcon#end of sib2, iclass 27, count 0 2006.245.08:03:52.76#ibcon#*after write, iclass 27, count 0 2006.245.08:03:52.76#ibcon#*before return 0, iclass 27, count 0 2006.245.08:03:52.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:03:52.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:03:52.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:03:52.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:03:52.76$vc4f8/va=8,8 2006.245.08:03:52.76#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.08:03:52.76#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.08:03:52.76#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:52.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:03:52.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:03:52.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:03:52.82#ibcon#enter wrdev, iclass 29, count 2 2006.245.08:03:52.82#ibcon#first serial, iclass 29, count 2 2006.245.08:03:52.82#ibcon#enter sib2, iclass 29, count 2 2006.245.08:03:52.82#ibcon#flushed, iclass 29, count 2 2006.245.08:03:52.82#ibcon#about to write, iclass 29, count 2 2006.245.08:03:52.82#ibcon#wrote, iclass 29, count 2 2006.245.08:03:52.82#ibcon#about to read 3, iclass 29, count 2 2006.245.08:03:52.84#ibcon#read 3, iclass 29, count 2 2006.245.08:03:52.84#ibcon#about to read 4, iclass 29, count 2 2006.245.08:03:52.84#ibcon#read 4, iclass 29, count 2 2006.245.08:03:52.84#ibcon#about to read 5, iclass 29, count 2 2006.245.08:03:52.84#ibcon#read 5, iclass 29, count 2 2006.245.08:03:52.84#ibcon#about to read 6, iclass 29, count 2 2006.245.08:03:52.84#ibcon#read 6, iclass 29, count 2 2006.245.08:03:52.84#ibcon#end of sib2, iclass 29, count 2 2006.245.08:03:52.84#ibcon#*mode == 0, iclass 29, count 2 2006.245.08:03:52.84#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.08:03:52.84#ibcon#[25=AT08-08\r\n] 2006.245.08:03:52.84#ibcon#*before write, iclass 29, count 2 2006.245.08:03:52.84#ibcon#enter sib2, iclass 29, count 2 2006.245.08:03:52.84#ibcon#flushed, iclass 29, count 2 2006.245.08:03:52.84#ibcon#about to write, iclass 29, count 2 2006.245.08:03:52.84#ibcon#wrote, iclass 29, count 2 2006.245.08:03:52.84#ibcon#about to read 3, iclass 29, count 2 2006.245.08:03:52.87#ibcon#read 3, iclass 29, count 2 2006.245.08:03:52.87#ibcon#about to read 4, iclass 29, count 2 2006.245.08:03:52.87#ibcon#read 4, iclass 29, count 2 2006.245.08:03:52.87#ibcon#about to read 5, iclass 29, count 2 2006.245.08:03:52.87#ibcon#read 5, iclass 29, count 2 2006.245.08:03:52.87#ibcon#about to read 6, iclass 29, count 2 2006.245.08:03:52.87#ibcon#read 6, iclass 29, count 2 2006.245.08:03:52.87#ibcon#end of sib2, iclass 29, count 2 2006.245.08:03:52.87#ibcon#*after write, iclass 29, count 2 2006.245.08:03:52.87#ibcon#*before return 0, iclass 29, count 2 2006.245.08:03:52.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:03:52.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:03:52.87#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.08:03:52.87#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:52.87#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:03:52.99#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:03:52.99#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:03:52.99#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:03:52.99#ibcon#first serial, iclass 29, count 0 2006.245.08:03:52.99#ibcon#enter sib2, iclass 29, count 0 2006.245.08:03:52.99#ibcon#flushed, iclass 29, count 0 2006.245.08:03:52.99#ibcon#about to write, iclass 29, count 0 2006.245.08:03:52.99#ibcon#wrote, iclass 29, count 0 2006.245.08:03:52.99#ibcon#about to read 3, iclass 29, count 0 2006.245.08:03:53.01#ibcon#read 3, iclass 29, count 0 2006.245.08:03:53.01#ibcon#about to read 4, iclass 29, count 0 2006.245.08:03:53.01#ibcon#read 4, iclass 29, count 0 2006.245.08:03:53.01#ibcon#about to read 5, iclass 29, count 0 2006.245.08:03:53.01#ibcon#read 5, iclass 29, count 0 2006.245.08:03:53.01#ibcon#about to read 6, iclass 29, count 0 2006.245.08:03:53.01#ibcon#read 6, iclass 29, count 0 2006.245.08:03:53.01#ibcon#end of sib2, iclass 29, count 0 2006.245.08:03:53.01#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:03:53.01#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:03:53.01#ibcon#[25=USB\r\n] 2006.245.08:03:53.01#ibcon#*before write, iclass 29, count 0 2006.245.08:03:53.01#ibcon#enter sib2, iclass 29, count 0 2006.245.08:03:53.01#ibcon#flushed, iclass 29, count 0 2006.245.08:03:53.01#ibcon#about to write, iclass 29, count 0 2006.245.08:03:53.01#ibcon#wrote, iclass 29, count 0 2006.245.08:03:53.01#ibcon#about to read 3, iclass 29, count 0 2006.245.08:03:53.04#ibcon#read 3, iclass 29, count 0 2006.245.08:03:53.04#ibcon#about to read 4, iclass 29, count 0 2006.245.08:03:53.04#ibcon#read 4, iclass 29, count 0 2006.245.08:03:53.04#ibcon#about to read 5, iclass 29, count 0 2006.245.08:03:53.04#ibcon#read 5, iclass 29, count 0 2006.245.08:03:53.04#ibcon#about to read 6, iclass 29, count 0 2006.245.08:03:53.04#ibcon#read 6, iclass 29, count 0 2006.245.08:03:53.04#ibcon#end of sib2, iclass 29, count 0 2006.245.08:03:53.04#ibcon#*after write, iclass 29, count 0 2006.245.08:03:53.04#ibcon#*before return 0, iclass 29, count 0 2006.245.08:03:53.04#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:03:53.04#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:03:53.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:03:53.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:03:53.04$vc4f8/vblo=1,632.99 2006.245.08:03:53.04#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.08:03:53.04#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.08:03:53.04#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:53.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:03:53.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:03:53.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:03:53.04#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:03:53.04#ibcon#first serial, iclass 31, count 0 2006.245.08:03:53.04#ibcon#enter sib2, iclass 31, count 0 2006.245.08:03:53.04#ibcon#flushed, iclass 31, count 0 2006.245.08:03:53.04#ibcon#about to write, iclass 31, count 0 2006.245.08:03:53.04#ibcon#wrote, iclass 31, count 0 2006.245.08:03:53.04#ibcon#about to read 3, iclass 31, count 0 2006.245.08:03:53.07#ibcon#read 3, iclass 31, count 0 2006.245.08:03:53.07#ibcon#about to read 4, iclass 31, count 0 2006.245.08:03:53.07#ibcon#read 4, iclass 31, count 0 2006.245.08:03:53.07#ibcon#about to read 5, iclass 31, count 0 2006.245.08:03:53.07#ibcon#read 5, iclass 31, count 0 2006.245.08:03:53.07#ibcon#about to read 6, iclass 31, count 0 2006.245.08:03:53.07#ibcon#read 6, iclass 31, count 0 2006.245.08:03:53.07#ibcon#end of sib2, iclass 31, count 0 2006.245.08:03:53.07#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:03:53.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:03:53.07#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:03:53.07#ibcon#*before write, iclass 31, count 0 2006.245.08:03:53.07#ibcon#enter sib2, iclass 31, count 0 2006.245.08:03:53.07#ibcon#flushed, iclass 31, count 0 2006.245.08:03:53.07#ibcon#about to write, iclass 31, count 0 2006.245.08:03:53.07#ibcon#wrote, iclass 31, count 0 2006.245.08:03:53.07#ibcon#about to read 3, iclass 31, count 0 2006.245.08:03:53.11#ibcon#read 3, iclass 31, count 0 2006.245.08:03:53.11#ibcon#about to read 4, iclass 31, count 0 2006.245.08:03:53.11#ibcon#read 4, iclass 31, count 0 2006.245.08:03:53.11#ibcon#about to read 5, iclass 31, count 0 2006.245.08:03:53.11#ibcon#read 5, iclass 31, count 0 2006.245.08:03:53.11#ibcon#about to read 6, iclass 31, count 0 2006.245.08:03:53.11#ibcon#read 6, iclass 31, count 0 2006.245.08:03:53.11#ibcon#end of sib2, iclass 31, count 0 2006.245.08:03:53.11#ibcon#*after write, iclass 31, count 0 2006.245.08:03:53.11#ibcon#*before return 0, iclass 31, count 0 2006.245.08:03:53.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:03:53.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:03:53.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:03:53.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:03:53.11$vc4f8/vb=1,4 2006.245.08:03:53.11#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.08:03:53.11#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.08:03:53.11#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:53.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:03:53.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:03:53.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:03:53.11#ibcon#enter wrdev, iclass 33, count 2 2006.245.08:03:53.11#ibcon#first serial, iclass 33, count 2 2006.245.08:03:53.11#ibcon#enter sib2, iclass 33, count 2 2006.245.08:03:53.11#ibcon#flushed, iclass 33, count 2 2006.245.08:03:53.11#ibcon#about to write, iclass 33, count 2 2006.245.08:03:53.11#ibcon#wrote, iclass 33, count 2 2006.245.08:03:53.11#ibcon#about to read 3, iclass 33, count 2 2006.245.08:03:53.13#ibcon#read 3, iclass 33, count 2 2006.245.08:03:53.13#ibcon#about to read 4, iclass 33, count 2 2006.245.08:03:53.13#ibcon#read 4, iclass 33, count 2 2006.245.08:03:53.13#ibcon#about to read 5, iclass 33, count 2 2006.245.08:03:53.13#ibcon#read 5, iclass 33, count 2 2006.245.08:03:53.13#ibcon#about to read 6, iclass 33, count 2 2006.245.08:03:53.13#ibcon#read 6, iclass 33, count 2 2006.245.08:03:53.13#ibcon#end of sib2, iclass 33, count 2 2006.245.08:03:53.13#ibcon#*mode == 0, iclass 33, count 2 2006.245.08:03:53.13#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.08:03:53.13#ibcon#[27=AT01-04\r\n] 2006.245.08:03:53.13#ibcon#*before write, iclass 33, count 2 2006.245.08:03:53.13#ibcon#enter sib2, iclass 33, count 2 2006.245.08:03:53.13#ibcon#flushed, iclass 33, count 2 2006.245.08:03:53.13#ibcon#about to write, iclass 33, count 2 2006.245.08:03:53.13#ibcon#wrote, iclass 33, count 2 2006.245.08:03:53.13#ibcon#about to read 3, iclass 33, count 2 2006.245.08:03:53.16#ibcon#read 3, iclass 33, count 2 2006.245.08:03:53.16#ibcon#about to read 4, iclass 33, count 2 2006.245.08:03:53.16#ibcon#read 4, iclass 33, count 2 2006.245.08:03:53.16#ibcon#about to read 5, iclass 33, count 2 2006.245.08:03:53.16#ibcon#read 5, iclass 33, count 2 2006.245.08:03:53.16#ibcon#about to read 6, iclass 33, count 2 2006.245.08:03:53.16#ibcon#read 6, iclass 33, count 2 2006.245.08:03:53.16#ibcon#end of sib2, iclass 33, count 2 2006.245.08:03:53.16#ibcon#*after write, iclass 33, count 2 2006.245.08:03:53.16#ibcon#*before return 0, iclass 33, count 2 2006.245.08:03:53.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:03:53.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:03:53.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.08:03:53.16#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:53.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:03:53.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:03:53.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:03:53.28#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:03:53.28#ibcon#first serial, iclass 33, count 0 2006.245.08:03:53.28#ibcon#enter sib2, iclass 33, count 0 2006.245.08:03:53.28#ibcon#flushed, iclass 33, count 0 2006.245.08:03:53.28#ibcon#about to write, iclass 33, count 0 2006.245.08:03:53.28#ibcon#wrote, iclass 33, count 0 2006.245.08:03:53.28#ibcon#about to read 3, iclass 33, count 0 2006.245.08:03:53.30#ibcon#read 3, iclass 33, count 0 2006.245.08:03:53.30#ibcon#about to read 4, iclass 33, count 0 2006.245.08:03:53.30#ibcon#read 4, iclass 33, count 0 2006.245.08:03:53.30#ibcon#about to read 5, iclass 33, count 0 2006.245.08:03:53.30#ibcon#read 5, iclass 33, count 0 2006.245.08:03:53.30#ibcon#about to read 6, iclass 33, count 0 2006.245.08:03:53.30#ibcon#read 6, iclass 33, count 0 2006.245.08:03:53.30#ibcon#end of sib2, iclass 33, count 0 2006.245.08:03:53.30#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:03:53.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:03:53.30#ibcon#[27=USB\r\n] 2006.245.08:03:53.30#ibcon#*before write, iclass 33, count 0 2006.245.08:03:53.30#ibcon#enter sib2, iclass 33, count 0 2006.245.08:03:53.30#ibcon#flushed, iclass 33, count 0 2006.245.08:03:53.30#ibcon#about to write, iclass 33, count 0 2006.245.08:03:53.30#ibcon#wrote, iclass 33, count 0 2006.245.08:03:53.30#ibcon#about to read 3, iclass 33, count 0 2006.245.08:03:53.33#ibcon#read 3, iclass 33, count 0 2006.245.08:03:53.33#ibcon#about to read 4, iclass 33, count 0 2006.245.08:03:53.33#ibcon#read 4, iclass 33, count 0 2006.245.08:03:53.33#ibcon#about to read 5, iclass 33, count 0 2006.245.08:03:53.33#ibcon#read 5, iclass 33, count 0 2006.245.08:03:53.33#ibcon#about to read 6, iclass 33, count 0 2006.245.08:03:53.33#ibcon#read 6, iclass 33, count 0 2006.245.08:03:53.33#ibcon#end of sib2, iclass 33, count 0 2006.245.08:03:53.33#ibcon#*after write, iclass 33, count 0 2006.245.08:03:53.33#ibcon#*before return 0, iclass 33, count 0 2006.245.08:03:53.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:03:53.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:03:53.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:03:53.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:03:53.33$vc4f8/vblo=2,640.99 2006.245.08:03:53.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.08:03:53.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.08:03:53.33#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:53.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:53.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:53.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:53.33#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:03:53.33#ibcon#first serial, iclass 35, count 0 2006.245.08:03:53.33#ibcon#enter sib2, iclass 35, count 0 2006.245.08:03:53.33#ibcon#flushed, iclass 35, count 0 2006.245.08:03:53.33#ibcon#about to write, iclass 35, count 0 2006.245.08:03:53.33#ibcon#wrote, iclass 35, count 0 2006.245.08:03:53.33#ibcon#about to read 3, iclass 35, count 0 2006.245.08:03:53.35#ibcon#read 3, iclass 35, count 0 2006.245.08:03:53.35#ibcon#about to read 4, iclass 35, count 0 2006.245.08:03:53.35#ibcon#read 4, iclass 35, count 0 2006.245.08:03:53.35#ibcon#about to read 5, iclass 35, count 0 2006.245.08:03:53.35#ibcon#read 5, iclass 35, count 0 2006.245.08:03:53.35#ibcon#about to read 6, iclass 35, count 0 2006.245.08:03:53.35#ibcon#read 6, iclass 35, count 0 2006.245.08:03:53.35#ibcon#end of sib2, iclass 35, count 0 2006.245.08:03:53.35#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:03:53.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:03:53.35#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:03:53.35#ibcon#*before write, iclass 35, count 0 2006.245.08:03:53.35#ibcon#enter sib2, iclass 35, count 0 2006.245.08:03:53.35#ibcon#flushed, iclass 35, count 0 2006.245.08:03:53.35#ibcon#about to write, iclass 35, count 0 2006.245.08:03:53.35#ibcon#wrote, iclass 35, count 0 2006.245.08:03:53.35#ibcon#about to read 3, iclass 35, count 0 2006.245.08:03:53.39#ibcon#read 3, iclass 35, count 0 2006.245.08:03:53.39#ibcon#about to read 4, iclass 35, count 0 2006.245.08:03:53.39#ibcon#read 4, iclass 35, count 0 2006.245.08:03:53.39#ibcon#about to read 5, iclass 35, count 0 2006.245.08:03:53.39#ibcon#read 5, iclass 35, count 0 2006.245.08:03:53.39#ibcon#about to read 6, iclass 35, count 0 2006.245.08:03:53.39#ibcon#read 6, iclass 35, count 0 2006.245.08:03:53.39#ibcon#end of sib2, iclass 35, count 0 2006.245.08:03:53.39#ibcon#*after write, iclass 35, count 0 2006.245.08:03:53.39#ibcon#*before return 0, iclass 35, count 0 2006.245.08:03:53.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:53.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:03:53.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:03:53.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:03:53.39$vc4f8/vb=2,4 2006.245.08:03:53.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.08:03:53.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.08:03:53.39#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:53.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:53.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:53.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:53.45#ibcon#enter wrdev, iclass 37, count 2 2006.245.08:03:53.45#ibcon#first serial, iclass 37, count 2 2006.245.08:03:53.45#ibcon#enter sib2, iclass 37, count 2 2006.245.08:03:53.45#ibcon#flushed, iclass 37, count 2 2006.245.08:03:53.45#ibcon#about to write, iclass 37, count 2 2006.245.08:03:53.45#ibcon#wrote, iclass 37, count 2 2006.245.08:03:53.45#ibcon#about to read 3, iclass 37, count 2 2006.245.08:03:53.47#ibcon#read 3, iclass 37, count 2 2006.245.08:03:53.47#ibcon#about to read 4, iclass 37, count 2 2006.245.08:03:53.47#ibcon#read 4, iclass 37, count 2 2006.245.08:03:53.47#ibcon#about to read 5, iclass 37, count 2 2006.245.08:03:53.47#ibcon#read 5, iclass 37, count 2 2006.245.08:03:53.47#ibcon#about to read 6, iclass 37, count 2 2006.245.08:03:53.47#ibcon#read 6, iclass 37, count 2 2006.245.08:03:53.47#ibcon#end of sib2, iclass 37, count 2 2006.245.08:03:53.47#ibcon#*mode == 0, iclass 37, count 2 2006.245.08:03:53.47#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.08:03:53.47#ibcon#[27=AT02-04\r\n] 2006.245.08:03:53.47#ibcon#*before write, iclass 37, count 2 2006.245.08:03:53.47#ibcon#enter sib2, iclass 37, count 2 2006.245.08:03:53.47#ibcon#flushed, iclass 37, count 2 2006.245.08:03:53.47#ibcon#about to write, iclass 37, count 2 2006.245.08:03:53.47#ibcon#wrote, iclass 37, count 2 2006.245.08:03:53.47#ibcon#about to read 3, iclass 37, count 2 2006.245.08:03:53.50#ibcon#read 3, iclass 37, count 2 2006.245.08:03:53.50#ibcon#about to read 4, iclass 37, count 2 2006.245.08:03:53.50#ibcon#read 4, iclass 37, count 2 2006.245.08:03:53.50#ibcon#about to read 5, iclass 37, count 2 2006.245.08:03:53.50#ibcon#read 5, iclass 37, count 2 2006.245.08:03:53.50#ibcon#about to read 6, iclass 37, count 2 2006.245.08:03:53.50#ibcon#read 6, iclass 37, count 2 2006.245.08:03:53.50#ibcon#end of sib2, iclass 37, count 2 2006.245.08:03:53.50#ibcon#*after write, iclass 37, count 2 2006.245.08:03:53.50#ibcon#*before return 0, iclass 37, count 2 2006.245.08:03:53.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:53.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:03:53.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.08:03:53.50#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:53.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:53.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:53.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:53.62#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:03:53.62#ibcon#first serial, iclass 37, count 0 2006.245.08:03:53.62#ibcon#enter sib2, iclass 37, count 0 2006.245.08:03:53.62#ibcon#flushed, iclass 37, count 0 2006.245.08:03:53.62#ibcon#about to write, iclass 37, count 0 2006.245.08:03:53.62#ibcon#wrote, iclass 37, count 0 2006.245.08:03:53.62#ibcon#about to read 3, iclass 37, count 0 2006.245.08:03:53.64#ibcon#read 3, iclass 37, count 0 2006.245.08:03:53.64#ibcon#about to read 4, iclass 37, count 0 2006.245.08:03:53.64#ibcon#read 4, iclass 37, count 0 2006.245.08:03:53.64#ibcon#about to read 5, iclass 37, count 0 2006.245.08:03:53.64#ibcon#read 5, iclass 37, count 0 2006.245.08:03:53.64#ibcon#about to read 6, iclass 37, count 0 2006.245.08:03:53.64#ibcon#read 6, iclass 37, count 0 2006.245.08:03:53.64#ibcon#end of sib2, iclass 37, count 0 2006.245.08:03:53.64#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:03:53.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:03:53.64#ibcon#[27=USB\r\n] 2006.245.08:03:53.64#ibcon#*before write, iclass 37, count 0 2006.245.08:03:53.64#ibcon#enter sib2, iclass 37, count 0 2006.245.08:03:53.64#ibcon#flushed, iclass 37, count 0 2006.245.08:03:53.64#ibcon#about to write, iclass 37, count 0 2006.245.08:03:53.64#ibcon#wrote, iclass 37, count 0 2006.245.08:03:53.64#ibcon#about to read 3, iclass 37, count 0 2006.245.08:03:53.67#ibcon#read 3, iclass 37, count 0 2006.245.08:03:53.67#ibcon#about to read 4, iclass 37, count 0 2006.245.08:03:53.67#ibcon#read 4, iclass 37, count 0 2006.245.08:03:53.67#ibcon#about to read 5, iclass 37, count 0 2006.245.08:03:53.67#ibcon#read 5, iclass 37, count 0 2006.245.08:03:53.67#ibcon#about to read 6, iclass 37, count 0 2006.245.08:03:53.67#ibcon#read 6, iclass 37, count 0 2006.245.08:03:53.67#ibcon#end of sib2, iclass 37, count 0 2006.245.08:03:53.67#ibcon#*after write, iclass 37, count 0 2006.245.08:03:53.67#ibcon#*before return 0, iclass 37, count 0 2006.245.08:03:53.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:53.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:03:53.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:03:53.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:03:53.67$vc4f8/vblo=3,656.99 2006.245.08:03:53.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.08:03:53.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.08:03:53.67#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:53.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:53.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:53.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:53.67#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:03:53.67#ibcon#first serial, iclass 39, count 0 2006.245.08:03:53.67#ibcon#enter sib2, iclass 39, count 0 2006.245.08:03:53.67#ibcon#flushed, iclass 39, count 0 2006.245.08:03:53.67#ibcon#about to write, iclass 39, count 0 2006.245.08:03:53.67#ibcon#wrote, iclass 39, count 0 2006.245.08:03:53.67#ibcon#about to read 3, iclass 39, count 0 2006.245.08:03:53.70#ibcon#read 3, iclass 39, count 0 2006.245.08:03:53.70#ibcon#about to read 4, iclass 39, count 0 2006.245.08:03:53.70#ibcon#read 4, iclass 39, count 0 2006.245.08:03:53.70#ibcon#about to read 5, iclass 39, count 0 2006.245.08:03:53.70#ibcon#read 5, iclass 39, count 0 2006.245.08:03:53.70#ibcon#about to read 6, iclass 39, count 0 2006.245.08:03:53.70#ibcon#read 6, iclass 39, count 0 2006.245.08:03:53.70#ibcon#end of sib2, iclass 39, count 0 2006.245.08:03:53.70#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:03:53.70#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:03:53.70#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:03:53.70#ibcon#*before write, iclass 39, count 0 2006.245.08:03:53.70#ibcon#enter sib2, iclass 39, count 0 2006.245.08:03:53.70#ibcon#flushed, iclass 39, count 0 2006.245.08:03:53.70#ibcon#about to write, iclass 39, count 0 2006.245.08:03:53.70#ibcon#wrote, iclass 39, count 0 2006.245.08:03:53.70#ibcon#about to read 3, iclass 39, count 0 2006.245.08:03:53.74#ibcon#read 3, iclass 39, count 0 2006.245.08:03:53.74#ibcon#about to read 4, iclass 39, count 0 2006.245.08:03:53.74#ibcon#read 4, iclass 39, count 0 2006.245.08:03:53.74#ibcon#about to read 5, iclass 39, count 0 2006.245.08:03:53.74#ibcon#read 5, iclass 39, count 0 2006.245.08:03:53.74#ibcon#about to read 6, iclass 39, count 0 2006.245.08:03:53.74#ibcon#read 6, iclass 39, count 0 2006.245.08:03:53.74#ibcon#end of sib2, iclass 39, count 0 2006.245.08:03:53.74#ibcon#*after write, iclass 39, count 0 2006.245.08:03:53.74#ibcon#*before return 0, iclass 39, count 0 2006.245.08:03:53.74#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:53.74#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:03:53.74#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:03:53.74#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:03:53.74$vc4f8/vb=3,4 2006.245.08:03:53.74#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.08:03:53.74#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.08:03:53.74#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:53.74#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:53.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:53.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:53.79#ibcon#enter wrdev, iclass 3, count 2 2006.245.08:03:53.79#ibcon#first serial, iclass 3, count 2 2006.245.08:03:53.79#ibcon#enter sib2, iclass 3, count 2 2006.245.08:03:53.79#ibcon#flushed, iclass 3, count 2 2006.245.08:03:53.79#ibcon#about to write, iclass 3, count 2 2006.245.08:03:53.79#ibcon#wrote, iclass 3, count 2 2006.245.08:03:53.79#ibcon#about to read 3, iclass 3, count 2 2006.245.08:03:53.81#ibcon#read 3, iclass 3, count 2 2006.245.08:03:53.81#ibcon#about to read 4, iclass 3, count 2 2006.245.08:03:53.81#ibcon#read 4, iclass 3, count 2 2006.245.08:03:53.81#ibcon#about to read 5, iclass 3, count 2 2006.245.08:03:53.81#ibcon#read 5, iclass 3, count 2 2006.245.08:03:53.81#ibcon#about to read 6, iclass 3, count 2 2006.245.08:03:53.81#ibcon#read 6, iclass 3, count 2 2006.245.08:03:53.81#ibcon#end of sib2, iclass 3, count 2 2006.245.08:03:53.81#ibcon#*mode == 0, iclass 3, count 2 2006.245.08:03:53.81#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.08:03:53.81#ibcon#[27=AT03-04\r\n] 2006.245.08:03:53.81#ibcon#*before write, iclass 3, count 2 2006.245.08:03:53.81#ibcon#enter sib2, iclass 3, count 2 2006.245.08:03:53.81#ibcon#flushed, iclass 3, count 2 2006.245.08:03:53.81#ibcon#about to write, iclass 3, count 2 2006.245.08:03:53.81#ibcon#wrote, iclass 3, count 2 2006.245.08:03:53.81#ibcon#about to read 3, iclass 3, count 2 2006.245.08:03:53.84#ibcon#read 3, iclass 3, count 2 2006.245.08:03:53.84#ibcon#about to read 4, iclass 3, count 2 2006.245.08:03:53.84#ibcon#read 4, iclass 3, count 2 2006.245.08:03:53.84#ibcon#about to read 5, iclass 3, count 2 2006.245.08:03:53.84#ibcon#read 5, iclass 3, count 2 2006.245.08:03:53.84#ibcon#about to read 6, iclass 3, count 2 2006.245.08:03:53.84#ibcon#read 6, iclass 3, count 2 2006.245.08:03:53.84#ibcon#end of sib2, iclass 3, count 2 2006.245.08:03:53.84#ibcon#*after write, iclass 3, count 2 2006.245.08:03:53.84#ibcon#*before return 0, iclass 3, count 2 2006.245.08:03:53.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:53.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:03:53.84#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.08:03:53.84#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:53.84#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:53.96#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:53.96#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:53.96#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:03:53.96#ibcon#first serial, iclass 3, count 0 2006.245.08:03:53.96#ibcon#enter sib2, iclass 3, count 0 2006.245.08:03:53.96#ibcon#flushed, iclass 3, count 0 2006.245.08:03:53.96#ibcon#about to write, iclass 3, count 0 2006.245.08:03:53.96#ibcon#wrote, iclass 3, count 0 2006.245.08:03:53.96#ibcon#about to read 3, iclass 3, count 0 2006.245.08:03:53.98#ibcon#read 3, iclass 3, count 0 2006.245.08:03:53.98#ibcon#about to read 4, iclass 3, count 0 2006.245.08:03:53.98#ibcon#read 4, iclass 3, count 0 2006.245.08:03:53.98#ibcon#about to read 5, iclass 3, count 0 2006.245.08:03:53.98#ibcon#read 5, iclass 3, count 0 2006.245.08:03:53.98#ibcon#about to read 6, iclass 3, count 0 2006.245.08:03:53.98#ibcon#read 6, iclass 3, count 0 2006.245.08:03:53.98#ibcon#end of sib2, iclass 3, count 0 2006.245.08:03:53.98#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:03:53.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:03:53.98#ibcon#[27=USB\r\n] 2006.245.08:03:53.98#ibcon#*before write, iclass 3, count 0 2006.245.08:03:53.98#ibcon#enter sib2, iclass 3, count 0 2006.245.08:03:53.98#ibcon#flushed, iclass 3, count 0 2006.245.08:03:53.98#ibcon#about to write, iclass 3, count 0 2006.245.08:03:53.98#ibcon#wrote, iclass 3, count 0 2006.245.08:03:53.98#ibcon#about to read 3, iclass 3, count 0 2006.245.08:03:54.01#ibcon#read 3, iclass 3, count 0 2006.245.08:03:54.01#ibcon#about to read 4, iclass 3, count 0 2006.245.08:03:54.01#ibcon#read 4, iclass 3, count 0 2006.245.08:03:54.01#ibcon#about to read 5, iclass 3, count 0 2006.245.08:03:54.01#ibcon#read 5, iclass 3, count 0 2006.245.08:03:54.01#ibcon#about to read 6, iclass 3, count 0 2006.245.08:03:54.01#ibcon#read 6, iclass 3, count 0 2006.245.08:03:54.01#ibcon#end of sib2, iclass 3, count 0 2006.245.08:03:54.01#ibcon#*after write, iclass 3, count 0 2006.245.08:03:54.01#ibcon#*before return 0, iclass 3, count 0 2006.245.08:03:54.01#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:54.01#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:03:54.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:03:54.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:03:54.01$vc4f8/vblo=4,712.99 2006.245.08:03:54.01#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.08:03:54.01#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.08:03:54.01#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:54.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:54.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:54.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:54.01#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:03:54.01#ibcon#first serial, iclass 5, count 0 2006.245.08:03:54.01#ibcon#enter sib2, iclass 5, count 0 2006.245.08:03:54.01#ibcon#flushed, iclass 5, count 0 2006.245.08:03:54.01#ibcon#about to write, iclass 5, count 0 2006.245.08:03:54.01#ibcon#wrote, iclass 5, count 0 2006.245.08:03:54.01#ibcon#about to read 3, iclass 5, count 0 2006.245.08:03:54.03#ibcon#read 3, iclass 5, count 0 2006.245.08:03:54.03#ibcon#about to read 4, iclass 5, count 0 2006.245.08:03:54.03#ibcon#read 4, iclass 5, count 0 2006.245.08:03:54.03#ibcon#about to read 5, iclass 5, count 0 2006.245.08:03:54.03#ibcon#read 5, iclass 5, count 0 2006.245.08:03:54.03#ibcon#about to read 6, iclass 5, count 0 2006.245.08:03:54.03#ibcon#read 6, iclass 5, count 0 2006.245.08:03:54.03#ibcon#end of sib2, iclass 5, count 0 2006.245.08:03:54.03#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:03:54.03#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:03:54.03#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:03:54.03#ibcon#*before write, iclass 5, count 0 2006.245.08:03:54.03#ibcon#enter sib2, iclass 5, count 0 2006.245.08:03:54.03#ibcon#flushed, iclass 5, count 0 2006.245.08:03:54.03#ibcon#about to write, iclass 5, count 0 2006.245.08:03:54.03#ibcon#wrote, iclass 5, count 0 2006.245.08:03:54.03#ibcon#about to read 3, iclass 5, count 0 2006.245.08:03:54.07#ibcon#read 3, iclass 5, count 0 2006.245.08:03:54.07#ibcon#about to read 4, iclass 5, count 0 2006.245.08:03:54.07#ibcon#read 4, iclass 5, count 0 2006.245.08:03:54.07#ibcon#about to read 5, iclass 5, count 0 2006.245.08:03:54.07#ibcon#read 5, iclass 5, count 0 2006.245.08:03:54.07#ibcon#about to read 6, iclass 5, count 0 2006.245.08:03:54.07#ibcon#read 6, iclass 5, count 0 2006.245.08:03:54.07#ibcon#end of sib2, iclass 5, count 0 2006.245.08:03:54.07#ibcon#*after write, iclass 5, count 0 2006.245.08:03:54.07#ibcon#*before return 0, iclass 5, count 0 2006.245.08:03:54.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:54.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:03:54.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:03:54.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:03:54.07$vc4f8/vb=4,4 2006.245.08:03:54.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.08:03:54.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.08:03:54.07#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:54.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:54.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:54.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:54.13#ibcon#enter wrdev, iclass 7, count 2 2006.245.08:03:54.13#ibcon#first serial, iclass 7, count 2 2006.245.08:03:54.13#ibcon#enter sib2, iclass 7, count 2 2006.245.08:03:54.13#ibcon#flushed, iclass 7, count 2 2006.245.08:03:54.13#ibcon#about to write, iclass 7, count 2 2006.245.08:03:54.13#ibcon#wrote, iclass 7, count 2 2006.245.08:03:54.13#ibcon#about to read 3, iclass 7, count 2 2006.245.08:03:54.15#ibcon#read 3, iclass 7, count 2 2006.245.08:03:54.15#ibcon#about to read 4, iclass 7, count 2 2006.245.08:03:54.15#ibcon#read 4, iclass 7, count 2 2006.245.08:03:54.15#ibcon#about to read 5, iclass 7, count 2 2006.245.08:03:54.15#ibcon#read 5, iclass 7, count 2 2006.245.08:03:54.15#ibcon#about to read 6, iclass 7, count 2 2006.245.08:03:54.15#ibcon#read 6, iclass 7, count 2 2006.245.08:03:54.15#ibcon#end of sib2, iclass 7, count 2 2006.245.08:03:54.15#ibcon#*mode == 0, iclass 7, count 2 2006.245.08:03:54.15#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.08:03:54.15#ibcon#[27=AT04-04\r\n] 2006.245.08:03:54.15#ibcon#*before write, iclass 7, count 2 2006.245.08:03:54.15#ibcon#enter sib2, iclass 7, count 2 2006.245.08:03:54.15#ibcon#flushed, iclass 7, count 2 2006.245.08:03:54.15#ibcon#about to write, iclass 7, count 2 2006.245.08:03:54.15#ibcon#wrote, iclass 7, count 2 2006.245.08:03:54.15#ibcon#about to read 3, iclass 7, count 2 2006.245.08:03:54.18#ibcon#read 3, iclass 7, count 2 2006.245.08:03:54.18#ibcon#about to read 4, iclass 7, count 2 2006.245.08:03:54.18#ibcon#read 4, iclass 7, count 2 2006.245.08:03:54.18#ibcon#about to read 5, iclass 7, count 2 2006.245.08:03:54.18#ibcon#read 5, iclass 7, count 2 2006.245.08:03:54.18#ibcon#about to read 6, iclass 7, count 2 2006.245.08:03:54.18#ibcon#read 6, iclass 7, count 2 2006.245.08:03:54.18#ibcon#end of sib2, iclass 7, count 2 2006.245.08:03:54.18#ibcon#*after write, iclass 7, count 2 2006.245.08:03:54.18#ibcon#*before return 0, iclass 7, count 2 2006.245.08:03:54.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:54.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:03:54.18#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.08:03:54.18#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:54.18#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:54.30#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:54.30#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:54.30#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:03:54.30#ibcon#first serial, iclass 7, count 0 2006.245.08:03:54.30#ibcon#enter sib2, iclass 7, count 0 2006.245.08:03:54.30#ibcon#flushed, iclass 7, count 0 2006.245.08:03:54.30#ibcon#about to write, iclass 7, count 0 2006.245.08:03:54.30#ibcon#wrote, iclass 7, count 0 2006.245.08:03:54.30#ibcon#about to read 3, iclass 7, count 0 2006.245.08:03:54.32#ibcon#read 3, iclass 7, count 0 2006.245.08:03:54.32#ibcon#about to read 4, iclass 7, count 0 2006.245.08:03:54.32#ibcon#read 4, iclass 7, count 0 2006.245.08:03:54.32#ibcon#about to read 5, iclass 7, count 0 2006.245.08:03:54.32#ibcon#read 5, iclass 7, count 0 2006.245.08:03:54.32#ibcon#about to read 6, iclass 7, count 0 2006.245.08:03:54.32#ibcon#read 6, iclass 7, count 0 2006.245.08:03:54.32#ibcon#end of sib2, iclass 7, count 0 2006.245.08:03:54.32#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:03:54.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:03:54.32#ibcon#[27=USB\r\n] 2006.245.08:03:54.32#ibcon#*before write, iclass 7, count 0 2006.245.08:03:54.32#ibcon#enter sib2, iclass 7, count 0 2006.245.08:03:54.32#ibcon#flushed, iclass 7, count 0 2006.245.08:03:54.32#ibcon#about to write, iclass 7, count 0 2006.245.08:03:54.32#ibcon#wrote, iclass 7, count 0 2006.245.08:03:54.32#ibcon#about to read 3, iclass 7, count 0 2006.245.08:03:54.35#ibcon#read 3, iclass 7, count 0 2006.245.08:03:54.35#ibcon#about to read 4, iclass 7, count 0 2006.245.08:03:54.35#ibcon#read 4, iclass 7, count 0 2006.245.08:03:54.35#ibcon#about to read 5, iclass 7, count 0 2006.245.08:03:54.35#ibcon#read 5, iclass 7, count 0 2006.245.08:03:54.35#ibcon#about to read 6, iclass 7, count 0 2006.245.08:03:54.35#ibcon#read 6, iclass 7, count 0 2006.245.08:03:54.35#ibcon#end of sib2, iclass 7, count 0 2006.245.08:03:54.35#ibcon#*after write, iclass 7, count 0 2006.245.08:03:54.35#ibcon#*before return 0, iclass 7, count 0 2006.245.08:03:54.35#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:54.35#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:03:54.35#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:03:54.35#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:03:54.35$vc4f8/vblo=5,744.99 2006.245.08:03:54.35#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.08:03:54.35#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.08:03:54.35#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:54.35#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:54.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:54.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:54.35#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:03:54.35#ibcon#first serial, iclass 11, count 0 2006.245.08:03:54.35#ibcon#enter sib2, iclass 11, count 0 2006.245.08:03:54.35#ibcon#flushed, iclass 11, count 0 2006.245.08:03:54.35#ibcon#about to write, iclass 11, count 0 2006.245.08:03:54.35#ibcon#wrote, iclass 11, count 0 2006.245.08:03:54.35#ibcon#about to read 3, iclass 11, count 0 2006.245.08:03:54.37#ibcon#read 3, iclass 11, count 0 2006.245.08:03:54.37#ibcon#about to read 4, iclass 11, count 0 2006.245.08:03:54.37#ibcon#read 4, iclass 11, count 0 2006.245.08:03:54.37#ibcon#about to read 5, iclass 11, count 0 2006.245.08:03:54.37#ibcon#read 5, iclass 11, count 0 2006.245.08:03:54.37#ibcon#about to read 6, iclass 11, count 0 2006.245.08:03:54.37#ibcon#read 6, iclass 11, count 0 2006.245.08:03:54.37#ibcon#end of sib2, iclass 11, count 0 2006.245.08:03:54.37#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:03:54.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:03:54.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:03:54.37#ibcon#*before write, iclass 11, count 0 2006.245.08:03:54.37#ibcon#enter sib2, iclass 11, count 0 2006.245.08:03:54.37#ibcon#flushed, iclass 11, count 0 2006.245.08:03:54.37#ibcon#about to write, iclass 11, count 0 2006.245.08:03:54.37#ibcon#wrote, iclass 11, count 0 2006.245.08:03:54.37#ibcon#about to read 3, iclass 11, count 0 2006.245.08:03:54.41#ibcon#read 3, iclass 11, count 0 2006.245.08:03:54.41#ibcon#about to read 4, iclass 11, count 0 2006.245.08:03:54.41#ibcon#read 4, iclass 11, count 0 2006.245.08:03:54.41#ibcon#about to read 5, iclass 11, count 0 2006.245.08:03:54.41#ibcon#read 5, iclass 11, count 0 2006.245.08:03:54.41#ibcon#about to read 6, iclass 11, count 0 2006.245.08:03:54.41#ibcon#read 6, iclass 11, count 0 2006.245.08:03:54.41#ibcon#end of sib2, iclass 11, count 0 2006.245.08:03:54.41#ibcon#*after write, iclass 11, count 0 2006.245.08:03:54.41#ibcon#*before return 0, iclass 11, count 0 2006.245.08:03:54.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:54.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:03:54.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:03:54.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:03:54.41$vc4f8/vb=5,3 2006.245.08:03:54.41#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:03:54.41#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:03:54.41#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:54.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:54.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:54.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:54.47#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:03:54.47#ibcon#first serial, iclass 13, count 2 2006.245.08:03:54.47#ibcon#enter sib2, iclass 13, count 2 2006.245.08:03:54.47#ibcon#flushed, iclass 13, count 2 2006.245.08:03:54.47#ibcon#about to write, iclass 13, count 2 2006.245.08:03:54.47#ibcon#wrote, iclass 13, count 2 2006.245.08:03:54.47#ibcon#about to read 3, iclass 13, count 2 2006.245.08:03:54.49#ibcon#read 3, iclass 13, count 2 2006.245.08:03:54.49#ibcon#about to read 4, iclass 13, count 2 2006.245.08:03:54.49#ibcon#read 4, iclass 13, count 2 2006.245.08:03:54.49#ibcon#about to read 5, iclass 13, count 2 2006.245.08:03:54.49#ibcon#read 5, iclass 13, count 2 2006.245.08:03:54.49#ibcon#about to read 6, iclass 13, count 2 2006.245.08:03:54.49#ibcon#read 6, iclass 13, count 2 2006.245.08:03:54.49#ibcon#end of sib2, iclass 13, count 2 2006.245.08:03:54.49#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:03:54.49#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:03:54.49#ibcon#[27=AT05-03\r\n] 2006.245.08:03:54.49#ibcon#*before write, iclass 13, count 2 2006.245.08:03:54.49#ibcon#enter sib2, iclass 13, count 2 2006.245.08:03:54.49#ibcon#flushed, iclass 13, count 2 2006.245.08:03:54.49#ibcon#about to write, iclass 13, count 2 2006.245.08:03:54.49#ibcon#wrote, iclass 13, count 2 2006.245.08:03:54.49#ibcon#about to read 3, iclass 13, count 2 2006.245.08:03:54.52#ibcon#read 3, iclass 13, count 2 2006.245.08:03:54.52#ibcon#about to read 4, iclass 13, count 2 2006.245.08:03:54.52#ibcon#read 4, iclass 13, count 2 2006.245.08:03:54.52#ibcon#about to read 5, iclass 13, count 2 2006.245.08:03:54.52#ibcon#read 5, iclass 13, count 2 2006.245.08:03:54.52#ibcon#about to read 6, iclass 13, count 2 2006.245.08:03:54.52#ibcon#read 6, iclass 13, count 2 2006.245.08:03:54.52#ibcon#end of sib2, iclass 13, count 2 2006.245.08:03:54.52#ibcon#*after write, iclass 13, count 2 2006.245.08:03:54.52#ibcon#*before return 0, iclass 13, count 2 2006.245.08:03:54.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:54.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:03:54.52#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:03:54.52#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:54.52#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:54.64#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:54.64#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:54.64#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:03:54.64#ibcon#first serial, iclass 13, count 0 2006.245.08:03:54.64#ibcon#enter sib2, iclass 13, count 0 2006.245.08:03:54.64#ibcon#flushed, iclass 13, count 0 2006.245.08:03:54.64#ibcon#about to write, iclass 13, count 0 2006.245.08:03:54.64#ibcon#wrote, iclass 13, count 0 2006.245.08:03:54.64#ibcon#about to read 3, iclass 13, count 0 2006.245.08:03:54.66#ibcon#read 3, iclass 13, count 0 2006.245.08:03:54.66#ibcon#about to read 4, iclass 13, count 0 2006.245.08:03:54.66#ibcon#read 4, iclass 13, count 0 2006.245.08:03:54.66#ibcon#about to read 5, iclass 13, count 0 2006.245.08:03:54.66#ibcon#read 5, iclass 13, count 0 2006.245.08:03:54.66#ibcon#about to read 6, iclass 13, count 0 2006.245.08:03:54.66#ibcon#read 6, iclass 13, count 0 2006.245.08:03:54.66#ibcon#end of sib2, iclass 13, count 0 2006.245.08:03:54.66#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:03:54.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:03:54.66#ibcon#[27=USB\r\n] 2006.245.08:03:54.66#ibcon#*before write, iclass 13, count 0 2006.245.08:03:54.66#ibcon#enter sib2, iclass 13, count 0 2006.245.08:03:54.66#ibcon#flushed, iclass 13, count 0 2006.245.08:03:54.66#ibcon#about to write, iclass 13, count 0 2006.245.08:03:54.66#ibcon#wrote, iclass 13, count 0 2006.245.08:03:54.66#ibcon#about to read 3, iclass 13, count 0 2006.245.08:03:54.69#ibcon#read 3, iclass 13, count 0 2006.245.08:03:54.69#ibcon#about to read 4, iclass 13, count 0 2006.245.08:03:54.69#ibcon#read 4, iclass 13, count 0 2006.245.08:03:54.69#ibcon#about to read 5, iclass 13, count 0 2006.245.08:03:54.69#ibcon#read 5, iclass 13, count 0 2006.245.08:03:54.69#ibcon#about to read 6, iclass 13, count 0 2006.245.08:03:54.69#ibcon#read 6, iclass 13, count 0 2006.245.08:03:54.69#ibcon#end of sib2, iclass 13, count 0 2006.245.08:03:54.69#ibcon#*after write, iclass 13, count 0 2006.245.08:03:54.69#ibcon#*before return 0, iclass 13, count 0 2006.245.08:03:54.69#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:54.69#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:03:54.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:03:54.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:03:54.69$vc4f8/vblo=6,752.99 2006.245.08:03:54.69#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.08:03:54.69#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.08:03:54.69#ibcon#ireg 17 cls_cnt 0 2006.245.08:03:54.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:54.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:54.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:54.69#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:03:54.69#ibcon#first serial, iclass 15, count 0 2006.245.08:03:54.69#ibcon#enter sib2, iclass 15, count 0 2006.245.08:03:54.69#ibcon#flushed, iclass 15, count 0 2006.245.08:03:54.69#ibcon#about to write, iclass 15, count 0 2006.245.08:03:54.69#ibcon#wrote, iclass 15, count 0 2006.245.08:03:54.69#ibcon#about to read 3, iclass 15, count 0 2006.245.08:03:54.72#ibcon#read 3, iclass 15, count 0 2006.245.08:03:54.72#ibcon#about to read 4, iclass 15, count 0 2006.245.08:03:54.72#ibcon#read 4, iclass 15, count 0 2006.245.08:03:54.72#ibcon#about to read 5, iclass 15, count 0 2006.245.08:03:54.72#ibcon#read 5, iclass 15, count 0 2006.245.08:03:54.72#ibcon#about to read 6, iclass 15, count 0 2006.245.08:03:54.72#ibcon#read 6, iclass 15, count 0 2006.245.08:03:54.72#ibcon#end of sib2, iclass 15, count 0 2006.245.08:03:54.72#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:03:54.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:03:54.72#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:03:54.72#ibcon#*before write, iclass 15, count 0 2006.245.08:03:54.72#ibcon#enter sib2, iclass 15, count 0 2006.245.08:03:54.72#ibcon#flushed, iclass 15, count 0 2006.245.08:03:54.72#ibcon#about to write, iclass 15, count 0 2006.245.08:03:54.72#ibcon#wrote, iclass 15, count 0 2006.245.08:03:54.72#ibcon#about to read 3, iclass 15, count 0 2006.245.08:03:54.76#ibcon#read 3, iclass 15, count 0 2006.245.08:03:54.76#ibcon#about to read 4, iclass 15, count 0 2006.245.08:03:54.76#ibcon#read 4, iclass 15, count 0 2006.245.08:03:54.76#ibcon#about to read 5, iclass 15, count 0 2006.245.08:03:54.76#ibcon#read 5, iclass 15, count 0 2006.245.08:03:54.76#ibcon#about to read 6, iclass 15, count 0 2006.245.08:03:54.76#ibcon#read 6, iclass 15, count 0 2006.245.08:03:54.76#ibcon#end of sib2, iclass 15, count 0 2006.245.08:03:54.76#ibcon#*after write, iclass 15, count 0 2006.245.08:03:54.76#ibcon#*before return 0, iclass 15, count 0 2006.245.08:03:54.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:54.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:03:54.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:03:54.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:03:54.76$vc4f8/vb=6,3 2006.245.08:03:54.76#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.08:03:54.76#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.08:03:54.76#ibcon#ireg 11 cls_cnt 2 2006.245.08:03:54.76#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:54.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:54.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:54.81#ibcon#enter wrdev, iclass 17, count 2 2006.245.08:03:54.81#ibcon#first serial, iclass 17, count 2 2006.245.08:03:54.81#ibcon#enter sib2, iclass 17, count 2 2006.245.08:03:54.81#ibcon#flushed, iclass 17, count 2 2006.245.08:03:54.81#ibcon#about to write, iclass 17, count 2 2006.245.08:03:54.81#ibcon#wrote, iclass 17, count 2 2006.245.08:03:54.81#ibcon#about to read 3, iclass 17, count 2 2006.245.08:03:54.83#ibcon#read 3, iclass 17, count 2 2006.245.08:03:54.83#ibcon#about to read 4, iclass 17, count 2 2006.245.08:03:54.83#ibcon#read 4, iclass 17, count 2 2006.245.08:03:54.83#ibcon#about to read 5, iclass 17, count 2 2006.245.08:03:54.83#ibcon#read 5, iclass 17, count 2 2006.245.08:03:54.83#ibcon#about to read 6, iclass 17, count 2 2006.245.08:03:54.83#ibcon#read 6, iclass 17, count 2 2006.245.08:03:54.83#ibcon#end of sib2, iclass 17, count 2 2006.245.08:03:54.83#ibcon#*mode == 0, iclass 17, count 2 2006.245.08:03:54.83#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.08:03:54.83#ibcon#[27=AT06-03\r\n] 2006.245.08:03:54.83#ibcon#*before write, iclass 17, count 2 2006.245.08:03:54.83#ibcon#enter sib2, iclass 17, count 2 2006.245.08:03:54.83#ibcon#flushed, iclass 17, count 2 2006.245.08:03:54.83#ibcon#about to write, iclass 17, count 2 2006.245.08:03:54.83#ibcon#wrote, iclass 17, count 2 2006.245.08:03:54.83#ibcon#about to read 3, iclass 17, count 2 2006.245.08:03:54.86#ibcon#read 3, iclass 17, count 2 2006.245.08:03:54.86#ibcon#about to read 4, iclass 17, count 2 2006.245.08:03:54.86#ibcon#read 4, iclass 17, count 2 2006.245.08:03:54.86#ibcon#about to read 5, iclass 17, count 2 2006.245.08:03:54.86#ibcon#read 5, iclass 17, count 2 2006.245.08:03:54.86#ibcon#about to read 6, iclass 17, count 2 2006.245.08:03:54.86#ibcon#read 6, iclass 17, count 2 2006.245.08:03:54.86#ibcon#end of sib2, iclass 17, count 2 2006.245.08:03:54.86#ibcon#*after write, iclass 17, count 2 2006.245.08:03:54.86#ibcon#*before return 0, iclass 17, count 2 2006.245.08:03:54.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:54.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:03:54.86#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.08:03:54.86#ibcon#ireg 7 cls_cnt 0 2006.245.08:03:54.86#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:54.98#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:54.98#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:54.98#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:03:54.98#ibcon#first serial, iclass 17, count 0 2006.245.08:03:54.98#ibcon#enter sib2, iclass 17, count 0 2006.245.08:03:54.98#ibcon#flushed, iclass 17, count 0 2006.245.08:03:54.98#ibcon#about to write, iclass 17, count 0 2006.245.08:03:54.98#ibcon#wrote, iclass 17, count 0 2006.245.08:03:54.98#ibcon#about to read 3, iclass 17, count 0 2006.245.08:03:55.00#ibcon#read 3, iclass 17, count 0 2006.245.08:03:55.00#ibcon#about to read 4, iclass 17, count 0 2006.245.08:03:55.00#ibcon#read 4, iclass 17, count 0 2006.245.08:03:55.00#ibcon#about to read 5, iclass 17, count 0 2006.245.08:03:55.00#ibcon#read 5, iclass 17, count 0 2006.245.08:03:55.00#ibcon#about to read 6, iclass 17, count 0 2006.245.08:03:55.00#ibcon#read 6, iclass 17, count 0 2006.245.08:03:55.00#ibcon#end of sib2, iclass 17, count 0 2006.245.08:03:55.00#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:03:55.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:03:55.00#ibcon#[27=USB\r\n] 2006.245.08:03:55.00#ibcon#*before write, iclass 17, count 0 2006.245.08:03:55.00#ibcon#enter sib2, iclass 17, count 0 2006.245.08:03:55.00#ibcon#flushed, iclass 17, count 0 2006.245.08:03:55.00#ibcon#about to write, iclass 17, count 0 2006.245.08:03:55.00#ibcon#wrote, iclass 17, count 0 2006.245.08:03:55.00#ibcon#about to read 3, iclass 17, count 0 2006.245.08:03:55.03#ibcon#read 3, iclass 17, count 0 2006.245.08:03:55.03#ibcon#about to read 4, iclass 17, count 0 2006.245.08:03:55.03#ibcon#read 4, iclass 17, count 0 2006.245.08:03:55.03#ibcon#about to read 5, iclass 17, count 0 2006.245.08:03:55.03#ibcon#read 5, iclass 17, count 0 2006.245.08:03:55.03#ibcon#about to read 6, iclass 17, count 0 2006.245.08:03:55.03#ibcon#read 6, iclass 17, count 0 2006.245.08:03:55.03#ibcon#end of sib2, iclass 17, count 0 2006.245.08:03:55.03#ibcon#*after write, iclass 17, count 0 2006.245.08:03:55.03#ibcon#*before return 0, iclass 17, count 0 2006.245.08:03:55.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:55.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:03:55.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:03:55.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:03:55.03$vc4f8/vabw=wide 2006.245.08:03:55.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.08:03:55.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.08:03:55.03#ibcon#ireg 8 cls_cnt 0 2006.245.08:03:55.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:55.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:55.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:55.03#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:03:55.03#ibcon#first serial, iclass 19, count 0 2006.245.08:03:55.03#ibcon#enter sib2, iclass 19, count 0 2006.245.08:03:55.03#ibcon#flushed, iclass 19, count 0 2006.245.08:03:55.03#ibcon#about to write, iclass 19, count 0 2006.245.08:03:55.03#ibcon#wrote, iclass 19, count 0 2006.245.08:03:55.03#ibcon#about to read 3, iclass 19, count 0 2006.245.08:03:55.05#ibcon#read 3, iclass 19, count 0 2006.245.08:03:55.05#ibcon#about to read 4, iclass 19, count 0 2006.245.08:03:55.05#ibcon#read 4, iclass 19, count 0 2006.245.08:03:55.05#ibcon#about to read 5, iclass 19, count 0 2006.245.08:03:55.05#ibcon#read 5, iclass 19, count 0 2006.245.08:03:55.05#ibcon#about to read 6, iclass 19, count 0 2006.245.08:03:55.05#ibcon#read 6, iclass 19, count 0 2006.245.08:03:55.05#ibcon#end of sib2, iclass 19, count 0 2006.245.08:03:55.05#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:03:55.05#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:03:55.05#ibcon#[25=BW32\r\n] 2006.245.08:03:55.05#ibcon#*before write, iclass 19, count 0 2006.245.08:03:55.05#ibcon#enter sib2, iclass 19, count 0 2006.245.08:03:55.05#ibcon#flushed, iclass 19, count 0 2006.245.08:03:55.05#ibcon#about to write, iclass 19, count 0 2006.245.08:03:55.05#ibcon#wrote, iclass 19, count 0 2006.245.08:03:55.05#ibcon#about to read 3, iclass 19, count 0 2006.245.08:03:55.08#ibcon#read 3, iclass 19, count 0 2006.245.08:03:55.08#ibcon#about to read 4, iclass 19, count 0 2006.245.08:03:55.08#ibcon#read 4, iclass 19, count 0 2006.245.08:03:55.08#ibcon#about to read 5, iclass 19, count 0 2006.245.08:03:55.08#ibcon#read 5, iclass 19, count 0 2006.245.08:03:55.08#ibcon#about to read 6, iclass 19, count 0 2006.245.08:03:55.08#ibcon#read 6, iclass 19, count 0 2006.245.08:03:55.08#ibcon#end of sib2, iclass 19, count 0 2006.245.08:03:55.08#ibcon#*after write, iclass 19, count 0 2006.245.08:03:55.08#ibcon#*before return 0, iclass 19, count 0 2006.245.08:03:55.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:55.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:03:55.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:03:55.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:03:55.08$vc4f8/vbbw=wide 2006.245.08:03:55.08#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:03:55.08#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:03:55.08#ibcon#ireg 8 cls_cnt 0 2006.245.08:03:55.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:03:55.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:03:55.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:03:55.15#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:03:55.15#ibcon#first serial, iclass 21, count 0 2006.245.08:03:55.15#ibcon#enter sib2, iclass 21, count 0 2006.245.08:03:55.15#ibcon#flushed, iclass 21, count 0 2006.245.08:03:55.15#ibcon#about to write, iclass 21, count 0 2006.245.08:03:55.15#ibcon#wrote, iclass 21, count 0 2006.245.08:03:55.15#ibcon#about to read 3, iclass 21, count 0 2006.245.08:03:55.17#ibcon#read 3, iclass 21, count 0 2006.245.08:03:55.17#ibcon#about to read 4, iclass 21, count 0 2006.245.08:03:55.17#ibcon#read 4, iclass 21, count 0 2006.245.08:03:55.17#ibcon#about to read 5, iclass 21, count 0 2006.245.08:03:55.17#ibcon#read 5, iclass 21, count 0 2006.245.08:03:55.17#ibcon#about to read 6, iclass 21, count 0 2006.245.08:03:55.17#ibcon#read 6, iclass 21, count 0 2006.245.08:03:55.17#ibcon#end of sib2, iclass 21, count 0 2006.245.08:03:55.17#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:03:55.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:03:55.17#ibcon#[27=BW32\r\n] 2006.245.08:03:55.17#ibcon#*before write, iclass 21, count 0 2006.245.08:03:55.17#ibcon#enter sib2, iclass 21, count 0 2006.245.08:03:55.17#ibcon#flushed, iclass 21, count 0 2006.245.08:03:55.17#ibcon#about to write, iclass 21, count 0 2006.245.08:03:55.17#ibcon#wrote, iclass 21, count 0 2006.245.08:03:55.17#ibcon#about to read 3, iclass 21, count 0 2006.245.08:03:55.20#ibcon#read 3, iclass 21, count 0 2006.245.08:03:55.20#ibcon#about to read 4, iclass 21, count 0 2006.245.08:03:55.20#ibcon#read 4, iclass 21, count 0 2006.245.08:03:55.20#ibcon#about to read 5, iclass 21, count 0 2006.245.08:03:55.20#ibcon#read 5, iclass 21, count 0 2006.245.08:03:55.20#ibcon#about to read 6, iclass 21, count 0 2006.245.08:03:55.20#ibcon#read 6, iclass 21, count 0 2006.245.08:03:55.20#ibcon#end of sib2, iclass 21, count 0 2006.245.08:03:55.20#ibcon#*after write, iclass 21, count 0 2006.245.08:03:55.20#ibcon#*before return 0, iclass 21, count 0 2006.245.08:03:55.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:03:55.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:03:55.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:03:55.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:03:55.20$4f8m12a/ifd4f 2006.245.08:03:55.20$ifd4f/lo= 2006.245.08:03:55.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:03:55.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:03:55.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:03:55.20$ifd4f/patch= 2006.245.08:03:55.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:03:55.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:03:55.20$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:03:55.20$4f8m12a/"form=m,16.000,1:2 2006.245.08:03:55.20$4f8m12a/"tpicd 2006.245.08:03:55.20$4f8m12a/echo=off 2006.245.08:03:55.20$4f8m12a/xlog=off 2006.245.08:03:55.20:!2006.245.08:04:20 2006.245.08:04:06.13#trakl#Source acquired 2006.245.08:04:08.13#flagr#flagr/antenna,acquired 2006.245.08:04:20.00:preob 2006.245.08:04:21.13/onsource/TRACKING 2006.245.08:04:21.13:!2006.245.08:04:30 2006.245.08:04:30.00:data_valid=on 2006.245.08:04:30.00:midob 2006.245.08:04:30.13/onsource/TRACKING 2006.245.08:04:30.13/wx/27.06,1004.5,71 2006.245.08:04:30.27/cable/+6.4115E-03 2006.245.08:04:31.36/va/01,08,usb,yes,35,36 2006.245.08:04:31.36/va/02,07,usb,yes,35,36 2006.245.08:04:31.36/va/03,06,usb,yes,37,37 2006.245.08:04:31.36/va/04,07,usb,yes,36,39 2006.245.08:04:31.36/va/05,07,usb,yes,38,40 2006.245.08:04:31.36/va/06,07,usb,yes,33,33 2006.245.08:04:31.36/va/07,07,usb,yes,33,33 2006.245.08:04:31.36/va/08,08,usb,yes,29,28 2006.245.08:04:31.59/valo/01,532.99,yes,locked 2006.245.08:04:31.59/valo/02,572.99,yes,locked 2006.245.08:04:31.59/valo/03,672.99,yes,locked 2006.245.08:04:31.59/valo/04,832.99,yes,locked 2006.245.08:04:31.59/valo/05,652.99,yes,locked 2006.245.08:04:31.59/valo/06,772.99,yes,locked 2006.245.08:04:31.59/valo/07,832.99,yes,locked 2006.245.08:04:31.59/valo/08,852.99,yes,locked 2006.245.08:04:32.68/vb/01,04,usb,yes,33,32 2006.245.08:04:32.68/vb/02,04,usb,yes,35,37 2006.245.08:04:32.68/vb/03,04,usb,yes,31,35 2006.245.08:04:32.68/vb/04,04,usb,yes,32,33 2006.245.08:04:32.68/vb/05,03,usb,yes,38,43 2006.245.08:04:32.68/vb/06,03,usb,yes,39,43 2006.245.08:04:32.68/vb/07,04,usb,yes,34,34 2006.245.08:04:32.68/vb/08,03,usb,yes,39,43 2006.245.08:04:32.91/vblo/01,632.99,yes,locked 2006.245.08:04:32.91/vblo/02,640.99,yes,locked 2006.245.08:04:32.91/vblo/03,656.99,yes,locked 2006.245.08:04:32.91/vblo/04,712.99,yes,locked 2006.245.08:04:32.91/vblo/05,744.99,yes,locked 2006.245.08:04:32.91/vblo/06,752.99,yes,locked 2006.245.08:04:32.91/vblo/07,734.99,yes,locked 2006.245.08:04:32.91/vblo/08,744.99,yes,locked 2006.245.08:04:33.06/vabw/8 2006.245.08:04:33.21/vbbw/8 2006.245.08:04:33.32/xfe/off,on,13.5 2006.245.08:04:33.69/ifatt/23,28,28,28 2006.245.08:04:34.07/fmout-gps/S +4.39E-07 2006.245.08:04:34.11:!2006.245.08:05:30 2006.245.08:05:30.00:data_valid=off 2006.245.08:05:30.01:postob 2006.245.08:05:30.08/cable/+6.4103E-03 2006.245.08:05:30.08/wx/27.04,1004.5,72 2006.245.08:05:31.08/fmout-gps/S +4.40E-07 2006.245.08:05:31.08:scan_name=245-0806,k06245,80 2006.245.08:05:31.09:source=1219+044,122222.55,041315.8,2000.0,ccw 2006.245.08:05:31.13#flagr#flagr/antenna,new-source 2006.245.08:05:32.13:checkk5 2006.245.08:05:32.61/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:05:33.23/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:05:33.68/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:05:34.11/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:05:34.53/chk_obsdata//k5ts1/T2450804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:05:35.22/chk_obsdata//k5ts2/T2450804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:05:35.67/chk_obsdata//k5ts3/T2450804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:05:36.08/chk_obsdata//k5ts4/T2450804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:05:37.29/k5log//k5ts1_log_newline 2006.245.08:05:38.28/k5log//k5ts2_log_newline 2006.245.08:05:39.21/k5log//k5ts3_log_newline 2006.245.08:05:40.36/k5log//k5ts4_log_newline 2006.245.08:05:40.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:05:40.39:4f8m12a=2 2006.245.08:05:40.39$4f8m12a/echo=on 2006.245.08:05:40.39$4f8m12a/pcalon 2006.245.08:05:40.39$pcalon/"no phase cal control is implemented here 2006.245.08:05:40.39$4f8m12a/"tpicd=stop 2006.245.08:05:40.39$4f8m12a/vc4f8 2006.245.08:05:40.39$vc4f8/valo=1,532.99 2006.245.08:05:40.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.08:05:40.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.08:05:40.39#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:40.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:40.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:40.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:40.39#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:05:40.39#ibcon#first serial, iclass 28, count 0 2006.245.08:05:40.39#ibcon#enter sib2, iclass 28, count 0 2006.245.08:05:40.39#ibcon#flushed, iclass 28, count 0 2006.245.08:05:40.39#ibcon#about to write, iclass 28, count 0 2006.245.08:05:40.39#ibcon#wrote, iclass 28, count 0 2006.245.08:05:40.39#ibcon#about to read 3, iclass 28, count 0 2006.245.08:05:40.43#ibcon#read 3, iclass 28, count 0 2006.245.08:05:40.43#ibcon#about to read 4, iclass 28, count 0 2006.245.08:05:40.43#ibcon#read 4, iclass 28, count 0 2006.245.08:05:40.43#ibcon#about to read 5, iclass 28, count 0 2006.245.08:05:40.43#ibcon#read 5, iclass 28, count 0 2006.245.08:05:40.43#ibcon#about to read 6, iclass 28, count 0 2006.245.08:05:40.43#ibcon#read 6, iclass 28, count 0 2006.245.08:05:40.43#ibcon#end of sib2, iclass 28, count 0 2006.245.08:05:40.43#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:05:40.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:05:40.43#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:05:40.43#ibcon#*before write, iclass 28, count 0 2006.245.08:05:40.43#ibcon#enter sib2, iclass 28, count 0 2006.245.08:05:40.43#ibcon#flushed, iclass 28, count 0 2006.245.08:05:40.43#ibcon#about to write, iclass 28, count 0 2006.245.08:05:40.43#ibcon#wrote, iclass 28, count 0 2006.245.08:05:40.43#ibcon#about to read 3, iclass 28, count 0 2006.245.08:05:40.48#ibcon#read 3, iclass 28, count 0 2006.245.08:05:40.48#ibcon#about to read 4, iclass 28, count 0 2006.245.08:05:40.48#ibcon#read 4, iclass 28, count 0 2006.245.08:05:40.48#ibcon#about to read 5, iclass 28, count 0 2006.245.08:05:40.48#ibcon#read 5, iclass 28, count 0 2006.245.08:05:40.48#ibcon#about to read 6, iclass 28, count 0 2006.245.08:05:40.48#ibcon#read 6, iclass 28, count 0 2006.245.08:05:40.48#ibcon#end of sib2, iclass 28, count 0 2006.245.08:05:40.48#ibcon#*after write, iclass 28, count 0 2006.245.08:05:40.48#ibcon#*before return 0, iclass 28, count 0 2006.245.08:05:40.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:40.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:40.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:05:40.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:05:40.48$vc4f8/va=1,8 2006.245.08:05:40.48#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.08:05:40.48#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.08:05:40.48#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:40.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:40.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:40.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:40.48#ibcon#enter wrdev, iclass 30, count 2 2006.245.08:05:40.48#ibcon#first serial, iclass 30, count 2 2006.245.08:05:40.48#ibcon#enter sib2, iclass 30, count 2 2006.245.08:05:40.48#ibcon#flushed, iclass 30, count 2 2006.245.08:05:40.48#ibcon#about to write, iclass 30, count 2 2006.245.08:05:40.48#ibcon#wrote, iclass 30, count 2 2006.245.08:05:40.48#ibcon#about to read 3, iclass 30, count 2 2006.245.08:05:40.51#ibcon#read 3, iclass 30, count 2 2006.245.08:05:40.51#ibcon#about to read 4, iclass 30, count 2 2006.245.08:05:40.51#ibcon#read 4, iclass 30, count 2 2006.245.08:05:40.51#ibcon#about to read 5, iclass 30, count 2 2006.245.08:05:40.51#ibcon#read 5, iclass 30, count 2 2006.245.08:05:40.51#ibcon#about to read 6, iclass 30, count 2 2006.245.08:05:40.51#ibcon#read 6, iclass 30, count 2 2006.245.08:05:40.51#ibcon#end of sib2, iclass 30, count 2 2006.245.08:05:40.51#ibcon#*mode == 0, iclass 30, count 2 2006.245.08:05:40.51#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.08:05:40.51#ibcon#[25=AT01-08\r\n] 2006.245.08:05:40.51#ibcon#*before write, iclass 30, count 2 2006.245.08:05:40.51#ibcon#enter sib2, iclass 30, count 2 2006.245.08:05:40.51#ibcon#flushed, iclass 30, count 2 2006.245.08:05:40.51#ibcon#about to write, iclass 30, count 2 2006.245.08:05:40.51#ibcon#wrote, iclass 30, count 2 2006.245.08:05:40.51#ibcon#about to read 3, iclass 30, count 2 2006.245.08:05:40.54#ibcon#read 3, iclass 30, count 2 2006.245.08:05:40.54#ibcon#about to read 4, iclass 30, count 2 2006.245.08:05:40.54#ibcon#read 4, iclass 30, count 2 2006.245.08:05:40.54#ibcon#about to read 5, iclass 30, count 2 2006.245.08:05:40.54#ibcon#read 5, iclass 30, count 2 2006.245.08:05:40.54#ibcon#about to read 6, iclass 30, count 2 2006.245.08:05:40.54#ibcon#read 6, iclass 30, count 2 2006.245.08:05:40.54#ibcon#end of sib2, iclass 30, count 2 2006.245.08:05:40.54#ibcon#*after write, iclass 30, count 2 2006.245.08:05:40.54#ibcon#*before return 0, iclass 30, count 2 2006.245.08:05:40.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:40.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:40.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.08:05:40.54#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:40.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:40.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:40.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:40.66#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:05:40.66#ibcon#first serial, iclass 30, count 0 2006.245.08:05:40.66#ibcon#enter sib2, iclass 30, count 0 2006.245.08:05:40.66#ibcon#flushed, iclass 30, count 0 2006.245.08:05:40.66#ibcon#about to write, iclass 30, count 0 2006.245.08:05:40.66#ibcon#wrote, iclass 30, count 0 2006.245.08:05:40.66#ibcon#about to read 3, iclass 30, count 0 2006.245.08:05:40.68#ibcon#read 3, iclass 30, count 0 2006.245.08:05:40.68#ibcon#about to read 4, iclass 30, count 0 2006.245.08:05:40.68#ibcon#read 4, iclass 30, count 0 2006.245.08:05:40.68#ibcon#about to read 5, iclass 30, count 0 2006.245.08:05:40.68#ibcon#read 5, iclass 30, count 0 2006.245.08:05:40.68#ibcon#about to read 6, iclass 30, count 0 2006.245.08:05:40.68#ibcon#read 6, iclass 30, count 0 2006.245.08:05:40.68#ibcon#end of sib2, iclass 30, count 0 2006.245.08:05:40.68#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:05:40.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:05:40.68#ibcon#[25=USB\r\n] 2006.245.08:05:40.68#ibcon#*before write, iclass 30, count 0 2006.245.08:05:40.68#ibcon#enter sib2, iclass 30, count 0 2006.245.08:05:40.68#ibcon#flushed, iclass 30, count 0 2006.245.08:05:40.68#ibcon#about to write, iclass 30, count 0 2006.245.08:05:40.68#ibcon#wrote, iclass 30, count 0 2006.245.08:05:40.68#ibcon#about to read 3, iclass 30, count 0 2006.245.08:05:40.71#ibcon#read 3, iclass 30, count 0 2006.245.08:05:40.71#ibcon#about to read 4, iclass 30, count 0 2006.245.08:05:40.71#ibcon#read 4, iclass 30, count 0 2006.245.08:05:40.71#ibcon#about to read 5, iclass 30, count 0 2006.245.08:05:40.71#ibcon#read 5, iclass 30, count 0 2006.245.08:05:40.71#ibcon#about to read 6, iclass 30, count 0 2006.245.08:05:40.71#ibcon#read 6, iclass 30, count 0 2006.245.08:05:40.71#ibcon#end of sib2, iclass 30, count 0 2006.245.08:05:40.71#ibcon#*after write, iclass 30, count 0 2006.245.08:05:40.71#ibcon#*before return 0, iclass 30, count 0 2006.245.08:05:40.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:40.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:40.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:05:40.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:05:40.71$vc4f8/valo=2,572.99 2006.245.08:05:40.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.08:05:40.71#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.08:05:40.71#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:40.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:40.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:40.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:40.71#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:05:40.71#ibcon#first serial, iclass 32, count 0 2006.245.08:05:40.71#ibcon#enter sib2, iclass 32, count 0 2006.245.08:05:40.71#ibcon#flushed, iclass 32, count 0 2006.245.08:05:40.71#ibcon#about to write, iclass 32, count 0 2006.245.08:05:40.71#ibcon#wrote, iclass 32, count 0 2006.245.08:05:40.71#ibcon#about to read 3, iclass 32, count 0 2006.245.08:05:40.74#ibcon#read 3, iclass 32, count 0 2006.245.08:05:40.74#ibcon#about to read 4, iclass 32, count 0 2006.245.08:05:40.74#ibcon#read 4, iclass 32, count 0 2006.245.08:05:40.74#ibcon#about to read 5, iclass 32, count 0 2006.245.08:05:40.74#ibcon#read 5, iclass 32, count 0 2006.245.08:05:40.74#ibcon#about to read 6, iclass 32, count 0 2006.245.08:05:40.74#ibcon#read 6, iclass 32, count 0 2006.245.08:05:40.74#ibcon#end of sib2, iclass 32, count 0 2006.245.08:05:40.74#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:05:40.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:05:40.74#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:05:40.74#ibcon#*before write, iclass 32, count 0 2006.245.08:05:40.74#ibcon#enter sib2, iclass 32, count 0 2006.245.08:05:40.74#ibcon#flushed, iclass 32, count 0 2006.245.08:05:40.74#ibcon#about to write, iclass 32, count 0 2006.245.08:05:40.74#ibcon#wrote, iclass 32, count 0 2006.245.08:05:40.74#ibcon#about to read 3, iclass 32, count 0 2006.245.08:05:40.78#ibcon#read 3, iclass 32, count 0 2006.245.08:05:40.78#ibcon#about to read 4, iclass 32, count 0 2006.245.08:05:40.78#ibcon#read 4, iclass 32, count 0 2006.245.08:05:40.78#ibcon#about to read 5, iclass 32, count 0 2006.245.08:05:40.78#ibcon#read 5, iclass 32, count 0 2006.245.08:05:40.78#ibcon#about to read 6, iclass 32, count 0 2006.245.08:05:40.78#ibcon#read 6, iclass 32, count 0 2006.245.08:05:40.78#ibcon#end of sib2, iclass 32, count 0 2006.245.08:05:40.78#ibcon#*after write, iclass 32, count 0 2006.245.08:05:40.78#ibcon#*before return 0, iclass 32, count 0 2006.245.08:05:40.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:40.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:40.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:05:40.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:05:40.78$vc4f8/va=2,7 2006.245.08:05:40.78#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.08:05:40.78#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.08:05:40.78#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:40.78#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:40.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:40.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:40.83#ibcon#enter wrdev, iclass 34, count 2 2006.245.08:05:40.83#ibcon#first serial, iclass 34, count 2 2006.245.08:05:40.83#ibcon#enter sib2, iclass 34, count 2 2006.245.08:05:40.83#ibcon#flushed, iclass 34, count 2 2006.245.08:05:40.83#ibcon#about to write, iclass 34, count 2 2006.245.08:05:40.83#ibcon#wrote, iclass 34, count 2 2006.245.08:05:40.83#ibcon#about to read 3, iclass 34, count 2 2006.245.08:05:40.85#ibcon#read 3, iclass 34, count 2 2006.245.08:05:40.85#ibcon#about to read 4, iclass 34, count 2 2006.245.08:05:40.85#ibcon#read 4, iclass 34, count 2 2006.245.08:05:40.85#ibcon#about to read 5, iclass 34, count 2 2006.245.08:05:40.85#ibcon#read 5, iclass 34, count 2 2006.245.08:05:40.85#ibcon#about to read 6, iclass 34, count 2 2006.245.08:05:40.85#ibcon#read 6, iclass 34, count 2 2006.245.08:05:40.85#ibcon#end of sib2, iclass 34, count 2 2006.245.08:05:40.85#ibcon#*mode == 0, iclass 34, count 2 2006.245.08:05:40.85#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.08:05:40.85#ibcon#[25=AT02-07\r\n] 2006.245.08:05:40.85#ibcon#*before write, iclass 34, count 2 2006.245.08:05:40.85#ibcon#enter sib2, iclass 34, count 2 2006.245.08:05:40.85#ibcon#flushed, iclass 34, count 2 2006.245.08:05:40.85#ibcon#about to write, iclass 34, count 2 2006.245.08:05:40.85#ibcon#wrote, iclass 34, count 2 2006.245.08:05:40.85#ibcon#about to read 3, iclass 34, count 2 2006.245.08:05:40.88#ibcon#read 3, iclass 34, count 2 2006.245.08:05:40.88#ibcon#about to read 4, iclass 34, count 2 2006.245.08:05:40.88#ibcon#read 4, iclass 34, count 2 2006.245.08:05:40.88#ibcon#about to read 5, iclass 34, count 2 2006.245.08:05:40.88#ibcon#read 5, iclass 34, count 2 2006.245.08:05:40.88#ibcon#about to read 6, iclass 34, count 2 2006.245.08:05:40.88#ibcon#read 6, iclass 34, count 2 2006.245.08:05:40.88#ibcon#end of sib2, iclass 34, count 2 2006.245.08:05:40.88#ibcon#*after write, iclass 34, count 2 2006.245.08:05:40.88#ibcon#*before return 0, iclass 34, count 2 2006.245.08:05:40.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:40.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:40.88#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.08:05:40.88#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:40.88#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:41.00#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:41.00#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:41.00#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:05:41.00#ibcon#first serial, iclass 34, count 0 2006.245.08:05:41.00#ibcon#enter sib2, iclass 34, count 0 2006.245.08:05:41.00#ibcon#flushed, iclass 34, count 0 2006.245.08:05:41.00#ibcon#about to write, iclass 34, count 0 2006.245.08:05:41.00#ibcon#wrote, iclass 34, count 0 2006.245.08:05:41.00#ibcon#about to read 3, iclass 34, count 0 2006.245.08:05:41.02#ibcon#read 3, iclass 34, count 0 2006.245.08:05:41.02#ibcon#about to read 4, iclass 34, count 0 2006.245.08:05:41.02#ibcon#read 4, iclass 34, count 0 2006.245.08:05:41.02#ibcon#about to read 5, iclass 34, count 0 2006.245.08:05:41.02#ibcon#read 5, iclass 34, count 0 2006.245.08:05:41.02#ibcon#about to read 6, iclass 34, count 0 2006.245.08:05:41.02#ibcon#read 6, iclass 34, count 0 2006.245.08:05:41.02#ibcon#end of sib2, iclass 34, count 0 2006.245.08:05:41.02#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:05:41.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:05:41.02#ibcon#[25=USB\r\n] 2006.245.08:05:41.02#ibcon#*before write, iclass 34, count 0 2006.245.08:05:41.02#ibcon#enter sib2, iclass 34, count 0 2006.245.08:05:41.02#ibcon#flushed, iclass 34, count 0 2006.245.08:05:41.02#ibcon#about to write, iclass 34, count 0 2006.245.08:05:41.02#ibcon#wrote, iclass 34, count 0 2006.245.08:05:41.02#ibcon#about to read 3, iclass 34, count 0 2006.245.08:05:41.05#ibcon#read 3, iclass 34, count 0 2006.245.08:05:41.05#ibcon#about to read 4, iclass 34, count 0 2006.245.08:05:41.05#ibcon#read 4, iclass 34, count 0 2006.245.08:05:41.05#ibcon#about to read 5, iclass 34, count 0 2006.245.08:05:41.05#ibcon#read 5, iclass 34, count 0 2006.245.08:05:41.05#ibcon#about to read 6, iclass 34, count 0 2006.245.08:05:41.05#ibcon#read 6, iclass 34, count 0 2006.245.08:05:41.05#ibcon#end of sib2, iclass 34, count 0 2006.245.08:05:41.05#ibcon#*after write, iclass 34, count 0 2006.245.08:05:41.05#ibcon#*before return 0, iclass 34, count 0 2006.245.08:05:41.05#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:41.05#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:41.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:05:41.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:05:41.05$vc4f8/valo=3,672.99 2006.245.08:05:41.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.08:05:41.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.08:05:41.05#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:41.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:41.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:41.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:41.05#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:05:41.05#ibcon#first serial, iclass 36, count 0 2006.245.08:05:41.05#ibcon#enter sib2, iclass 36, count 0 2006.245.08:05:41.05#ibcon#flushed, iclass 36, count 0 2006.245.08:05:41.05#ibcon#about to write, iclass 36, count 0 2006.245.08:05:41.05#ibcon#wrote, iclass 36, count 0 2006.245.08:05:41.05#ibcon#about to read 3, iclass 36, count 0 2006.245.08:05:41.07#ibcon#read 3, iclass 36, count 0 2006.245.08:05:41.07#ibcon#about to read 4, iclass 36, count 0 2006.245.08:05:41.07#ibcon#read 4, iclass 36, count 0 2006.245.08:05:41.07#ibcon#about to read 5, iclass 36, count 0 2006.245.08:05:41.07#ibcon#read 5, iclass 36, count 0 2006.245.08:05:41.07#ibcon#about to read 6, iclass 36, count 0 2006.245.08:05:41.07#ibcon#read 6, iclass 36, count 0 2006.245.08:05:41.07#ibcon#end of sib2, iclass 36, count 0 2006.245.08:05:41.07#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:05:41.07#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:05:41.07#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:05:41.07#ibcon#*before write, iclass 36, count 0 2006.245.08:05:41.07#ibcon#enter sib2, iclass 36, count 0 2006.245.08:05:41.07#ibcon#flushed, iclass 36, count 0 2006.245.08:05:41.07#ibcon#about to write, iclass 36, count 0 2006.245.08:05:41.07#ibcon#wrote, iclass 36, count 0 2006.245.08:05:41.07#ibcon#about to read 3, iclass 36, count 0 2006.245.08:05:41.11#ibcon#read 3, iclass 36, count 0 2006.245.08:05:41.11#ibcon#about to read 4, iclass 36, count 0 2006.245.08:05:41.11#ibcon#read 4, iclass 36, count 0 2006.245.08:05:41.11#ibcon#about to read 5, iclass 36, count 0 2006.245.08:05:41.11#ibcon#read 5, iclass 36, count 0 2006.245.08:05:41.11#ibcon#about to read 6, iclass 36, count 0 2006.245.08:05:41.11#ibcon#read 6, iclass 36, count 0 2006.245.08:05:41.11#ibcon#end of sib2, iclass 36, count 0 2006.245.08:05:41.11#ibcon#*after write, iclass 36, count 0 2006.245.08:05:41.11#ibcon#*before return 0, iclass 36, count 0 2006.245.08:05:41.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:41.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:41.11#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:05:41.11#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:05:41.11$vc4f8/va=3,6 2006.245.08:05:41.11#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.08:05:41.11#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.08:05:41.11#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:41.11#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:41.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:41.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:41.17#ibcon#enter wrdev, iclass 38, count 2 2006.245.08:05:41.17#ibcon#first serial, iclass 38, count 2 2006.245.08:05:41.17#ibcon#enter sib2, iclass 38, count 2 2006.245.08:05:41.17#ibcon#flushed, iclass 38, count 2 2006.245.08:05:41.17#ibcon#about to write, iclass 38, count 2 2006.245.08:05:41.17#ibcon#wrote, iclass 38, count 2 2006.245.08:05:41.17#ibcon#about to read 3, iclass 38, count 2 2006.245.08:05:41.19#ibcon#read 3, iclass 38, count 2 2006.245.08:05:41.19#ibcon#about to read 4, iclass 38, count 2 2006.245.08:05:41.19#ibcon#read 4, iclass 38, count 2 2006.245.08:05:41.19#ibcon#about to read 5, iclass 38, count 2 2006.245.08:05:41.19#ibcon#read 5, iclass 38, count 2 2006.245.08:05:41.19#ibcon#about to read 6, iclass 38, count 2 2006.245.08:05:41.19#ibcon#read 6, iclass 38, count 2 2006.245.08:05:41.19#ibcon#end of sib2, iclass 38, count 2 2006.245.08:05:41.19#ibcon#*mode == 0, iclass 38, count 2 2006.245.08:05:41.19#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.08:05:41.19#ibcon#[25=AT03-06\r\n] 2006.245.08:05:41.19#ibcon#*before write, iclass 38, count 2 2006.245.08:05:41.19#ibcon#enter sib2, iclass 38, count 2 2006.245.08:05:41.19#ibcon#flushed, iclass 38, count 2 2006.245.08:05:41.19#ibcon#about to write, iclass 38, count 2 2006.245.08:05:41.19#ibcon#wrote, iclass 38, count 2 2006.245.08:05:41.19#ibcon#about to read 3, iclass 38, count 2 2006.245.08:05:41.22#ibcon#read 3, iclass 38, count 2 2006.245.08:05:41.22#ibcon#about to read 4, iclass 38, count 2 2006.245.08:05:41.22#ibcon#read 4, iclass 38, count 2 2006.245.08:05:41.22#ibcon#about to read 5, iclass 38, count 2 2006.245.08:05:41.22#ibcon#read 5, iclass 38, count 2 2006.245.08:05:41.22#ibcon#about to read 6, iclass 38, count 2 2006.245.08:05:41.22#ibcon#read 6, iclass 38, count 2 2006.245.08:05:41.22#ibcon#end of sib2, iclass 38, count 2 2006.245.08:05:41.22#ibcon#*after write, iclass 38, count 2 2006.245.08:05:41.22#ibcon#*before return 0, iclass 38, count 2 2006.245.08:05:41.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:41.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:41.22#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.08:05:41.22#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:41.22#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:41.34#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:41.34#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:41.34#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:05:41.34#ibcon#first serial, iclass 38, count 0 2006.245.08:05:41.34#ibcon#enter sib2, iclass 38, count 0 2006.245.08:05:41.34#ibcon#flushed, iclass 38, count 0 2006.245.08:05:41.34#ibcon#about to write, iclass 38, count 0 2006.245.08:05:41.34#ibcon#wrote, iclass 38, count 0 2006.245.08:05:41.34#ibcon#about to read 3, iclass 38, count 0 2006.245.08:05:41.36#ibcon#read 3, iclass 38, count 0 2006.245.08:05:41.36#ibcon#about to read 4, iclass 38, count 0 2006.245.08:05:41.36#ibcon#read 4, iclass 38, count 0 2006.245.08:05:41.36#ibcon#about to read 5, iclass 38, count 0 2006.245.08:05:41.36#ibcon#read 5, iclass 38, count 0 2006.245.08:05:41.36#ibcon#about to read 6, iclass 38, count 0 2006.245.08:05:41.36#ibcon#read 6, iclass 38, count 0 2006.245.08:05:41.36#ibcon#end of sib2, iclass 38, count 0 2006.245.08:05:41.36#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:05:41.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:05:41.36#ibcon#[25=USB\r\n] 2006.245.08:05:41.36#ibcon#*before write, iclass 38, count 0 2006.245.08:05:41.36#ibcon#enter sib2, iclass 38, count 0 2006.245.08:05:41.36#ibcon#flushed, iclass 38, count 0 2006.245.08:05:41.36#ibcon#about to write, iclass 38, count 0 2006.245.08:05:41.36#ibcon#wrote, iclass 38, count 0 2006.245.08:05:41.36#ibcon#about to read 3, iclass 38, count 0 2006.245.08:05:41.39#ibcon#read 3, iclass 38, count 0 2006.245.08:05:41.39#ibcon#about to read 4, iclass 38, count 0 2006.245.08:05:41.39#ibcon#read 4, iclass 38, count 0 2006.245.08:05:41.39#ibcon#about to read 5, iclass 38, count 0 2006.245.08:05:41.39#ibcon#read 5, iclass 38, count 0 2006.245.08:05:41.39#ibcon#about to read 6, iclass 38, count 0 2006.245.08:05:41.39#ibcon#read 6, iclass 38, count 0 2006.245.08:05:41.39#ibcon#end of sib2, iclass 38, count 0 2006.245.08:05:41.39#ibcon#*after write, iclass 38, count 0 2006.245.08:05:41.39#ibcon#*before return 0, iclass 38, count 0 2006.245.08:05:41.39#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:41.39#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:41.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:05:41.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:05:41.39$vc4f8/valo=4,832.99 2006.245.08:05:41.39#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.08:05:41.39#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.08:05:41.39#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:41.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:41.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:41.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:41.39#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:05:41.39#ibcon#first serial, iclass 40, count 0 2006.245.08:05:41.39#ibcon#enter sib2, iclass 40, count 0 2006.245.08:05:41.39#ibcon#flushed, iclass 40, count 0 2006.245.08:05:41.39#ibcon#about to write, iclass 40, count 0 2006.245.08:05:41.39#ibcon#wrote, iclass 40, count 0 2006.245.08:05:41.39#ibcon#about to read 3, iclass 40, count 0 2006.245.08:05:41.41#ibcon#read 3, iclass 40, count 0 2006.245.08:05:41.41#ibcon#about to read 4, iclass 40, count 0 2006.245.08:05:41.41#ibcon#read 4, iclass 40, count 0 2006.245.08:05:41.41#ibcon#about to read 5, iclass 40, count 0 2006.245.08:05:41.41#ibcon#read 5, iclass 40, count 0 2006.245.08:05:41.41#ibcon#about to read 6, iclass 40, count 0 2006.245.08:05:41.41#ibcon#read 6, iclass 40, count 0 2006.245.08:05:41.41#ibcon#end of sib2, iclass 40, count 0 2006.245.08:05:41.41#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:05:41.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:05:41.41#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:05:41.41#ibcon#*before write, iclass 40, count 0 2006.245.08:05:41.41#ibcon#enter sib2, iclass 40, count 0 2006.245.08:05:41.41#ibcon#flushed, iclass 40, count 0 2006.245.08:05:41.41#ibcon#about to write, iclass 40, count 0 2006.245.08:05:41.41#ibcon#wrote, iclass 40, count 0 2006.245.08:05:41.41#ibcon#about to read 3, iclass 40, count 0 2006.245.08:05:41.45#ibcon#read 3, iclass 40, count 0 2006.245.08:05:41.45#ibcon#about to read 4, iclass 40, count 0 2006.245.08:05:41.45#ibcon#read 4, iclass 40, count 0 2006.245.08:05:41.45#ibcon#about to read 5, iclass 40, count 0 2006.245.08:05:41.45#ibcon#read 5, iclass 40, count 0 2006.245.08:05:41.45#ibcon#about to read 6, iclass 40, count 0 2006.245.08:05:41.45#ibcon#read 6, iclass 40, count 0 2006.245.08:05:41.45#ibcon#end of sib2, iclass 40, count 0 2006.245.08:05:41.45#ibcon#*after write, iclass 40, count 0 2006.245.08:05:41.45#ibcon#*before return 0, iclass 40, count 0 2006.245.08:05:41.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:41.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:41.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:05:41.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:05:41.45$vc4f8/va=4,7 2006.245.08:05:41.45#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.08:05:41.45#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.08:05:41.45#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:41.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:41.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:41.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:41.51#ibcon#enter wrdev, iclass 4, count 2 2006.245.08:05:41.51#ibcon#first serial, iclass 4, count 2 2006.245.08:05:41.51#ibcon#enter sib2, iclass 4, count 2 2006.245.08:05:41.51#ibcon#flushed, iclass 4, count 2 2006.245.08:05:41.51#ibcon#about to write, iclass 4, count 2 2006.245.08:05:41.51#ibcon#wrote, iclass 4, count 2 2006.245.08:05:41.51#ibcon#about to read 3, iclass 4, count 2 2006.245.08:05:41.53#ibcon#read 3, iclass 4, count 2 2006.245.08:05:41.53#ibcon#about to read 4, iclass 4, count 2 2006.245.08:05:41.53#ibcon#read 4, iclass 4, count 2 2006.245.08:05:41.53#ibcon#about to read 5, iclass 4, count 2 2006.245.08:05:41.53#ibcon#read 5, iclass 4, count 2 2006.245.08:05:41.53#ibcon#about to read 6, iclass 4, count 2 2006.245.08:05:41.53#ibcon#read 6, iclass 4, count 2 2006.245.08:05:41.53#ibcon#end of sib2, iclass 4, count 2 2006.245.08:05:41.53#ibcon#*mode == 0, iclass 4, count 2 2006.245.08:05:41.53#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.08:05:41.53#ibcon#[25=AT04-07\r\n] 2006.245.08:05:41.53#ibcon#*before write, iclass 4, count 2 2006.245.08:05:41.53#ibcon#enter sib2, iclass 4, count 2 2006.245.08:05:41.53#ibcon#flushed, iclass 4, count 2 2006.245.08:05:41.53#ibcon#about to write, iclass 4, count 2 2006.245.08:05:41.53#ibcon#wrote, iclass 4, count 2 2006.245.08:05:41.53#ibcon#about to read 3, iclass 4, count 2 2006.245.08:05:41.56#ibcon#read 3, iclass 4, count 2 2006.245.08:05:41.56#ibcon#about to read 4, iclass 4, count 2 2006.245.08:05:41.56#ibcon#read 4, iclass 4, count 2 2006.245.08:05:41.56#ibcon#about to read 5, iclass 4, count 2 2006.245.08:05:41.56#ibcon#read 5, iclass 4, count 2 2006.245.08:05:41.56#ibcon#about to read 6, iclass 4, count 2 2006.245.08:05:41.56#ibcon#read 6, iclass 4, count 2 2006.245.08:05:41.56#ibcon#end of sib2, iclass 4, count 2 2006.245.08:05:41.56#ibcon#*after write, iclass 4, count 2 2006.245.08:05:41.56#ibcon#*before return 0, iclass 4, count 2 2006.245.08:05:41.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:41.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:41.56#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.08:05:41.56#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:41.56#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:41.68#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:41.68#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:41.68#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:05:41.68#ibcon#first serial, iclass 4, count 0 2006.245.08:05:41.68#ibcon#enter sib2, iclass 4, count 0 2006.245.08:05:41.68#ibcon#flushed, iclass 4, count 0 2006.245.08:05:41.68#ibcon#about to write, iclass 4, count 0 2006.245.08:05:41.68#ibcon#wrote, iclass 4, count 0 2006.245.08:05:41.68#ibcon#about to read 3, iclass 4, count 0 2006.245.08:05:41.70#ibcon#read 3, iclass 4, count 0 2006.245.08:05:41.70#ibcon#about to read 4, iclass 4, count 0 2006.245.08:05:41.70#ibcon#read 4, iclass 4, count 0 2006.245.08:05:41.70#ibcon#about to read 5, iclass 4, count 0 2006.245.08:05:41.70#ibcon#read 5, iclass 4, count 0 2006.245.08:05:41.70#ibcon#about to read 6, iclass 4, count 0 2006.245.08:05:41.70#ibcon#read 6, iclass 4, count 0 2006.245.08:05:41.70#ibcon#end of sib2, iclass 4, count 0 2006.245.08:05:41.70#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:05:41.70#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:05:41.70#ibcon#[25=USB\r\n] 2006.245.08:05:41.70#ibcon#*before write, iclass 4, count 0 2006.245.08:05:41.70#ibcon#enter sib2, iclass 4, count 0 2006.245.08:05:41.70#ibcon#flushed, iclass 4, count 0 2006.245.08:05:41.70#ibcon#about to write, iclass 4, count 0 2006.245.08:05:41.70#ibcon#wrote, iclass 4, count 0 2006.245.08:05:41.70#ibcon#about to read 3, iclass 4, count 0 2006.245.08:05:41.73#ibcon#read 3, iclass 4, count 0 2006.245.08:05:41.73#ibcon#about to read 4, iclass 4, count 0 2006.245.08:05:41.73#ibcon#read 4, iclass 4, count 0 2006.245.08:05:41.73#ibcon#about to read 5, iclass 4, count 0 2006.245.08:05:41.73#ibcon#read 5, iclass 4, count 0 2006.245.08:05:41.73#ibcon#about to read 6, iclass 4, count 0 2006.245.08:05:41.73#ibcon#read 6, iclass 4, count 0 2006.245.08:05:41.73#ibcon#end of sib2, iclass 4, count 0 2006.245.08:05:41.73#ibcon#*after write, iclass 4, count 0 2006.245.08:05:41.73#ibcon#*before return 0, iclass 4, count 0 2006.245.08:05:41.73#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:41.73#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:41.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:05:41.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:05:41.73$vc4f8/valo=5,652.99 2006.245.08:05:41.73#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:05:41.73#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:05:41.73#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:41.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:05:41.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:05:41.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:05:41.73#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:05:41.73#ibcon#first serial, iclass 7, count 0 2006.245.08:05:41.73#ibcon#enter sib2, iclass 7, count 0 2006.245.08:05:41.73#ibcon#flushed, iclass 7, count 0 2006.245.08:05:41.73#ibcon#about to write, iclass 7, count 0 2006.245.08:05:41.73#ibcon#wrote, iclass 7, count 0 2006.245.08:05:41.73#ibcon#about to read 3, iclass 7, count 0 2006.245.08:05:41.74#abcon#<5=/05 3.5 5.9 27.04 721004.5\r\n> 2006.245.08:05:41.75#ibcon#read 3, iclass 7, count 0 2006.245.08:05:41.75#ibcon#about to read 4, iclass 7, count 0 2006.245.08:05:41.75#ibcon#read 4, iclass 7, count 0 2006.245.08:05:41.75#ibcon#about to read 5, iclass 7, count 0 2006.245.08:05:41.75#ibcon#read 5, iclass 7, count 0 2006.245.08:05:41.75#ibcon#about to read 6, iclass 7, count 0 2006.245.08:05:41.75#ibcon#read 6, iclass 7, count 0 2006.245.08:05:41.75#ibcon#end of sib2, iclass 7, count 0 2006.245.08:05:41.75#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:05:41.75#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:05:41.75#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:05:41.75#ibcon#*before write, iclass 7, count 0 2006.245.08:05:41.75#ibcon#enter sib2, iclass 7, count 0 2006.245.08:05:41.75#ibcon#flushed, iclass 7, count 0 2006.245.08:05:41.75#ibcon#about to write, iclass 7, count 0 2006.245.08:05:41.75#ibcon#wrote, iclass 7, count 0 2006.245.08:05:41.75#ibcon#about to read 3, iclass 7, count 0 2006.245.08:05:41.76#abcon#{5=INTERFACE CLEAR} 2006.245.08:05:41.79#ibcon#read 3, iclass 7, count 0 2006.245.08:05:41.79#ibcon#about to read 4, iclass 7, count 0 2006.245.08:05:41.79#ibcon#read 4, iclass 7, count 0 2006.245.08:05:41.79#ibcon#about to read 5, iclass 7, count 0 2006.245.08:05:41.79#ibcon#read 5, iclass 7, count 0 2006.245.08:05:41.79#ibcon#about to read 6, iclass 7, count 0 2006.245.08:05:41.79#ibcon#read 6, iclass 7, count 0 2006.245.08:05:41.79#ibcon#end of sib2, iclass 7, count 0 2006.245.08:05:41.79#ibcon#*after write, iclass 7, count 0 2006.245.08:05:41.79#ibcon#*before return 0, iclass 7, count 0 2006.245.08:05:41.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:05:41.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:05:41.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:05:41.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:05:41.79$vc4f8/va=5,7 2006.245.08:05:41.79#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:05:41.79#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:05:41.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:41.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:05:41.82#abcon#[5=S1D000X0/0*\r\n] 2006.245.08:05:41.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:05:41.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:05:41.85#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:05:41.85#ibcon#first serial, iclass 13, count 2 2006.245.08:05:41.85#ibcon#enter sib2, iclass 13, count 2 2006.245.08:05:41.85#ibcon#flushed, iclass 13, count 2 2006.245.08:05:41.85#ibcon#about to write, iclass 13, count 2 2006.245.08:05:41.85#ibcon#wrote, iclass 13, count 2 2006.245.08:05:41.85#ibcon#about to read 3, iclass 13, count 2 2006.245.08:05:41.87#ibcon#read 3, iclass 13, count 2 2006.245.08:05:41.87#ibcon#about to read 4, iclass 13, count 2 2006.245.08:05:41.87#ibcon#read 4, iclass 13, count 2 2006.245.08:05:41.87#ibcon#about to read 5, iclass 13, count 2 2006.245.08:05:41.87#ibcon#read 5, iclass 13, count 2 2006.245.08:05:41.87#ibcon#about to read 6, iclass 13, count 2 2006.245.08:05:41.87#ibcon#read 6, iclass 13, count 2 2006.245.08:05:41.87#ibcon#end of sib2, iclass 13, count 2 2006.245.08:05:41.87#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:05:41.87#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:05:41.87#ibcon#[25=AT05-07\r\n] 2006.245.08:05:41.87#ibcon#*before write, iclass 13, count 2 2006.245.08:05:41.87#ibcon#enter sib2, iclass 13, count 2 2006.245.08:05:41.87#ibcon#flushed, iclass 13, count 2 2006.245.08:05:41.87#ibcon#about to write, iclass 13, count 2 2006.245.08:05:41.87#ibcon#wrote, iclass 13, count 2 2006.245.08:05:41.87#ibcon#about to read 3, iclass 13, count 2 2006.245.08:05:41.90#ibcon#read 3, iclass 13, count 2 2006.245.08:05:41.90#ibcon#about to read 4, iclass 13, count 2 2006.245.08:05:41.90#ibcon#read 4, iclass 13, count 2 2006.245.08:05:41.90#ibcon#about to read 5, iclass 13, count 2 2006.245.08:05:41.90#ibcon#read 5, iclass 13, count 2 2006.245.08:05:41.90#ibcon#about to read 6, iclass 13, count 2 2006.245.08:05:41.90#ibcon#read 6, iclass 13, count 2 2006.245.08:05:41.90#ibcon#end of sib2, iclass 13, count 2 2006.245.08:05:41.90#ibcon#*after write, iclass 13, count 2 2006.245.08:05:41.90#ibcon#*before return 0, iclass 13, count 2 2006.245.08:05:41.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:05:41.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:05:41.90#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:05:41.90#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:41.90#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:05:42.02#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:05:42.02#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:05:42.02#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:05:42.02#ibcon#first serial, iclass 13, count 0 2006.245.08:05:42.02#ibcon#enter sib2, iclass 13, count 0 2006.245.08:05:42.02#ibcon#flushed, iclass 13, count 0 2006.245.08:05:42.02#ibcon#about to write, iclass 13, count 0 2006.245.08:05:42.02#ibcon#wrote, iclass 13, count 0 2006.245.08:05:42.02#ibcon#about to read 3, iclass 13, count 0 2006.245.08:05:42.04#ibcon#read 3, iclass 13, count 0 2006.245.08:05:42.04#ibcon#about to read 4, iclass 13, count 0 2006.245.08:05:42.04#ibcon#read 4, iclass 13, count 0 2006.245.08:05:42.04#ibcon#about to read 5, iclass 13, count 0 2006.245.08:05:42.04#ibcon#read 5, iclass 13, count 0 2006.245.08:05:42.04#ibcon#about to read 6, iclass 13, count 0 2006.245.08:05:42.04#ibcon#read 6, iclass 13, count 0 2006.245.08:05:42.04#ibcon#end of sib2, iclass 13, count 0 2006.245.08:05:42.04#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:05:42.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:05:42.04#ibcon#[25=USB\r\n] 2006.245.08:05:42.04#ibcon#*before write, iclass 13, count 0 2006.245.08:05:42.04#ibcon#enter sib2, iclass 13, count 0 2006.245.08:05:42.04#ibcon#flushed, iclass 13, count 0 2006.245.08:05:42.04#ibcon#about to write, iclass 13, count 0 2006.245.08:05:42.04#ibcon#wrote, iclass 13, count 0 2006.245.08:05:42.04#ibcon#about to read 3, iclass 13, count 0 2006.245.08:05:42.08#ibcon#read 3, iclass 13, count 0 2006.245.08:05:42.08#ibcon#about to read 4, iclass 13, count 0 2006.245.08:05:42.08#ibcon#read 4, iclass 13, count 0 2006.245.08:05:42.08#ibcon#about to read 5, iclass 13, count 0 2006.245.08:05:42.08#ibcon#read 5, iclass 13, count 0 2006.245.08:05:42.08#ibcon#about to read 6, iclass 13, count 0 2006.245.08:05:42.08#ibcon#read 6, iclass 13, count 0 2006.245.08:05:42.08#ibcon#end of sib2, iclass 13, count 0 2006.245.08:05:42.08#ibcon#*after write, iclass 13, count 0 2006.245.08:05:42.08#ibcon#*before return 0, iclass 13, count 0 2006.245.08:05:42.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:05:42.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:05:42.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:05:42.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:05:42.08$vc4f8/valo=6,772.99 2006.245.08:05:42.08#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.08:05:42.08#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.08:05:42.08#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:42.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:42.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:42.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:42.08#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:05:42.08#ibcon#first serial, iclass 16, count 0 2006.245.08:05:42.08#ibcon#enter sib2, iclass 16, count 0 2006.245.08:05:42.08#ibcon#flushed, iclass 16, count 0 2006.245.08:05:42.08#ibcon#about to write, iclass 16, count 0 2006.245.08:05:42.08#ibcon#wrote, iclass 16, count 0 2006.245.08:05:42.08#ibcon#about to read 3, iclass 16, count 0 2006.245.08:05:42.09#ibcon#read 3, iclass 16, count 0 2006.245.08:05:42.09#ibcon#about to read 4, iclass 16, count 0 2006.245.08:05:42.09#ibcon#read 4, iclass 16, count 0 2006.245.08:05:42.09#ibcon#about to read 5, iclass 16, count 0 2006.245.08:05:42.09#ibcon#read 5, iclass 16, count 0 2006.245.08:05:42.09#ibcon#about to read 6, iclass 16, count 0 2006.245.08:05:42.09#ibcon#read 6, iclass 16, count 0 2006.245.08:05:42.09#ibcon#end of sib2, iclass 16, count 0 2006.245.08:05:42.09#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:05:42.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:05:42.09#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:05:42.09#ibcon#*before write, iclass 16, count 0 2006.245.08:05:42.09#ibcon#enter sib2, iclass 16, count 0 2006.245.08:05:42.09#ibcon#flushed, iclass 16, count 0 2006.245.08:05:42.09#ibcon#about to write, iclass 16, count 0 2006.245.08:05:42.09#ibcon#wrote, iclass 16, count 0 2006.245.08:05:42.09#ibcon#about to read 3, iclass 16, count 0 2006.245.08:05:42.13#ibcon#read 3, iclass 16, count 0 2006.245.08:05:42.13#ibcon#about to read 4, iclass 16, count 0 2006.245.08:05:42.13#ibcon#read 4, iclass 16, count 0 2006.245.08:05:42.13#ibcon#about to read 5, iclass 16, count 0 2006.245.08:05:42.13#ibcon#read 5, iclass 16, count 0 2006.245.08:05:42.13#ibcon#about to read 6, iclass 16, count 0 2006.245.08:05:42.13#ibcon#read 6, iclass 16, count 0 2006.245.08:05:42.13#ibcon#end of sib2, iclass 16, count 0 2006.245.08:05:42.13#ibcon#*after write, iclass 16, count 0 2006.245.08:05:42.13#ibcon#*before return 0, iclass 16, count 0 2006.245.08:05:42.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:42.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:42.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:05:42.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:05:42.13$vc4f8/va=6,7 2006.245.08:05:42.13#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.08:05:42.13#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.08:05:42.13#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:42.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:05:42.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:05:42.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:05:42.20#ibcon#enter wrdev, iclass 18, count 2 2006.245.08:05:42.20#ibcon#first serial, iclass 18, count 2 2006.245.08:05:42.20#ibcon#enter sib2, iclass 18, count 2 2006.245.08:05:42.20#ibcon#flushed, iclass 18, count 2 2006.245.08:05:42.20#ibcon#about to write, iclass 18, count 2 2006.245.08:05:42.20#ibcon#wrote, iclass 18, count 2 2006.245.08:05:42.20#ibcon#about to read 3, iclass 18, count 2 2006.245.08:05:42.22#ibcon#read 3, iclass 18, count 2 2006.245.08:05:42.22#ibcon#about to read 4, iclass 18, count 2 2006.245.08:05:42.22#ibcon#read 4, iclass 18, count 2 2006.245.08:05:42.22#ibcon#about to read 5, iclass 18, count 2 2006.245.08:05:42.22#ibcon#read 5, iclass 18, count 2 2006.245.08:05:42.22#ibcon#about to read 6, iclass 18, count 2 2006.245.08:05:42.22#ibcon#read 6, iclass 18, count 2 2006.245.08:05:42.22#ibcon#end of sib2, iclass 18, count 2 2006.245.08:05:42.22#ibcon#*mode == 0, iclass 18, count 2 2006.245.08:05:42.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.08:05:42.22#ibcon#[25=AT06-07\r\n] 2006.245.08:05:42.22#ibcon#*before write, iclass 18, count 2 2006.245.08:05:42.22#ibcon#enter sib2, iclass 18, count 2 2006.245.08:05:42.22#ibcon#flushed, iclass 18, count 2 2006.245.08:05:42.22#ibcon#about to write, iclass 18, count 2 2006.245.08:05:42.22#ibcon#wrote, iclass 18, count 2 2006.245.08:05:42.22#ibcon#about to read 3, iclass 18, count 2 2006.245.08:05:42.25#ibcon#read 3, iclass 18, count 2 2006.245.08:05:42.25#ibcon#about to read 4, iclass 18, count 2 2006.245.08:05:42.25#ibcon#read 4, iclass 18, count 2 2006.245.08:05:42.25#ibcon#about to read 5, iclass 18, count 2 2006.245.08:05:42.25#ibcon#read 5, iclass 18, count 2 2006.245.08:05:42.25#ibcon#about to read 6, iclass 18, count 2 2006.245.08:05:42.25#ibcon#read 6, iclass 18, count 2 2006.245.08:05:42.25#ibcon#end of sib2, iclass 18, count 2 2006.245.08:05:42.25#ibcon#*after write, iclass 18, count 2 2006.245.08:05:42.25#ibcon#*before return 0, iclass 18, count 2 2006.245.08:05:42.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:05:42.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:05:42.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.08:05:42.25#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:42.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:05:42.37#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:05:42.37#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:05:42.37#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:05:42.37#ibcon#first serial, iclass 18, count 0 2006.245.08:05:42.37#ibcon#enter sib2, iclass 18, count 0 2006.245.08:05:42.37#ibcon#flushed, iclass 18, count 0 2006.245.08:05:42.37#ibcon#about to write, iclass 18, count 0 2006.245.08:05:42.37#ibcon#wrote, iclass 18, count 0 2006.245.08:05:42.37#ibcon#about to read 3, iclass 18, count 0 2006.245.08:05:42.39#ibcon#read 3, iclass 18, count 0 2006.245.08:05:42.39#ibcon#about to read 4, iclass 18, count 0 2006.245.08:05:42.39#ibcon#read 4, iclass 18, count 0 2006.245.08:05:42.39#ibcon#about to read 5, iclass 18, count 0 2006.245.08:05:42.39#ibcon#read 5, iclass 18, count 0 2006.245.08:05:42.39#ibcon#about to read 6, iclass 18, count 0 2006.245.08:05:42.39#ibcon#read 6, iclass 18, count 0 2006.245.08:05:42.39#ibcon#end of sib2, iclass 18, count 0 2006.245.08:05:42.39#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:05:42.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:05:42.39#ibcon#[25=USB\r\n] 2006.245.08:05:42.39#ibcon#*before write, iclass 18, count 0 2006.245.08:05:42.39#ibcon#enter sib2, iclass 18, count 0 2006.245.08:05:42.39#ibcon#flushed, iclass 18, count 0 2006.245.08:05:42.39#ibcon#about to write, iclass 18, count 0 2006.245.08:05:42.39#ibcon#wrote, iclass 18, count 0 2006.245.08:05:42.39#ibcon#about to read 3, iclass 18, count 0 2006.245.08:05:42.42#ibcon#read 3, iclass 18, count 0 2006.245.08:05:42.42#ibcon#about to read 4, iclass 18, count 0 2006.245.08:05:42.42#ibcon#read 4, iclass 18, count 0 2006.245.08:05:42.42#ibcon#about to read 5, iclass 18, count 0 2006.245.08:05:42.42#ibcon#read 5, iclass 18, count 0 2006.245.08:05:42.42#ibcon#about to read 6, iclass 18, count 0 2006.245.08:05:42.42#ibcon#read 6, iclass 18, count 0 2006.245.08:05:42.42#ibcon#end of sib2, iclass 18, count 0 2006.245.08:05:42.42#ibcon#*after write, iclass 18, count 0 2006.245.08:05:42.42#ibcon#*before return 0, iclass 18, count 0 2006.245.08:05:42.42#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:05:42.42#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:05:42.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:05:42.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:05:42.42$vc4f8/valo=7,832.99 2006.245.08:05:42.42#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.08:05:42.42#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.08:05:42.42#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:42.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:05:42.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:05:42.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:05:42.42#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:05:42.42#ibcon#first serial, iclass 20, count 0 2006.245.08:05:42.42#ibcon#enter sib2, iclass 20, count 0 2006.245.08:05:42.42#ibcon#flushed, iclass 20, count 0 2006.245.08:05:42.42#ibcon#about to write, iclass 20, count 0 2006.245.08:05:42.42#ibcon#wrote, iclass 20, count 0 2006.245.08:05:42.42#ibcon#about to read 3, iclass 20, count 0 2006.245.08:05:42.44#ibcon#read 3, iclass 20, count 0 2006.245.08:05:42.44#ibcon#about to read 4, iclass 20, count 0 2006.245.08:05:42.44#ibcon#read 4, iclass 20, count 0 2006.245.08:05:42.44#ibcon#about to read 5, iclass 20, count 0 2006.245.08:05:42.44#ibcon#read 5, iclass 20, count 0 2006.245.08:05:42.44#ibcon#about to read 6, iclass 20, count 0 2006.245.08:05:42.44#ibcon#read 6, iclass 20, count 0 2006.245.08:05:42.44#ibcon#end of sib2, iclass 20, count 0 2006.245.08:05:42.44#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:05:42.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:05:42.44#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:05:42.44#ibcon#*before write, iclass 20, count 0 2006.245.08:05:42.44#ibcon#enter sib2, iclass 20, count 0 2006.245.08:05:42.44#ibcon#flushed, iclass 20, count 0 2006.245.08:05:42.44#ibcon#about to write, iclass 20, count 0 2006.245.08:05:42.44#ibcon#wrote, iclass 20, count 0 2006.245.08:05:42.44#ibcon#about to read 3, iclass 20, count 0 2006.245.08:05:42.48#ibcon#read 3, iclass 20, count 0 2006.245.08:05:42.48#ibcon#about to read 4, iclass 20, count 0 2006.245.08:05:42.48#ibcon#read 4, iclass 20, count 0 2006.245.08:05:42.48#ibcon#about to read 5, iclass 20, count 0 2006.245.08:05:42.48#ibcon#read 5, iclass 20, count 0 2006.245.08:05:42.48#ibcon#about to read 6, iclass 20, count 0 2006.245.08:05:42.48#ibcon#read 6, iclass 20, count 0 2006.245.08:05:42.48#ibcon#end of sib2, iclass 20, count 0 2006.245.08:05:42.48#ibcon#*after write, iclass 20, count 0 2006.245.08:05:42.48#ibcon#*before return 0, iclass 20, count 0 2006.245.08:05:42.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:05:42.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:05:42.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:05:42.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:05:42.48$vc4f8/va=7,7 2006.245.08:05:42.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.08:05:42.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.08:05:42.48#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:42.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:05:42.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:05:42.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:05:42.54#ibcon#enter wrdev, iclass 22, count 2 2006.245.08:05:42.54#ibcon#first serial, iclass 22, count 2 2006.245.08:05:42.54#ibcon#enter sib2, iclass 22, count 2 2006.245.08:05:42.54#ibcon#flushed, iclass 22, count 2 2006.245.08:05:42.54#ibcon#about to write, iclass 22, count 2 2006.245.08:05:42.54#ibcon#wrote, iclass 22, count 2 2006.245.08:05:42.54#ibcon#about to read 3, iclass 22, count 2 2006.245.08:05:42.56#ibcon#read 3, iclass 22, count 2 2006.245.08:05:42.56#ibcon#about to read 4, iclass 22, count 2 2006.245.08:05:42.56#ibcon#read 4, iclass 22, count 2 2006.245.08:05:42.56#ibcon#about to read 5, iclass 22, count 2 2006.245.08:05:42.56#ibcon#read 5, iclass 22, count 2 2006.245.08:05:42.56#ibcon#about to read 6, iclass 22, count 2 2006.245.08:05:42.56#ibcon#read 6, iclass 22, count 2 2006.245.08:05:42.56#ibcon#end of sib2, iclass 22, count 2 2006.245.08:05:42.56#ibcon#*mode == 0, iclass 22, count 2 2006.245.08:05:42.56#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.08:05:42.56#ibcon#[25=AT07-07\r\n] 2006.245.08:05:42.56#ibcon#*before write, iclass 22, count 2 2006.245.08:05:42.56#ibcon#enter sib2, iclass 22, count 2 2006.245.08:05:42.56#ibcon#flushed, iclass 22, count 2 2006.245.08:05:42.56#ibcon#about to write, iclass 22, count 2 2006.245.08:05:42.56#ibcon#wrote, iclass 22, count 2 2006.245.08:05:42.56#ibcon#about to read 3, iclass 22, count 2 2006.245.08:05:42.59#ibcon#read 3, iclass 22, count 2 2006.245.08:05:42.59#ibcon#about to read 4, iclass 22, count 2 2006.245.08:05:42.59#ibcon#read 4, iclass 22, count 2 2006.245.08:05:42.59#ibcon#about to read 5, iclass 22, count 2 2006.245.08:05:42.59#ibcon#read 5, iclass 22, count 2 2006.245.08:05:42.59#ibcon#about to read 6, iclass 22, count 2 2006.245.08:05:42.59#ibcon#read 6, iclass 22, count 2 2006.245.08:05:42.59#ibcon#end of sib2, iclass 22, count 2 2006.245.08:05:42.59#ibcon#*after write, iclass 22, count 2 2006.245.08:05:42.59#ibcon#*before return 0, iclass 22, count 2 2006.245.08:05:42.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:05:42.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:05:42.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.08:05:42.59#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:42.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:05:42.71#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:05:42.71#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:05:42.71#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:05:42.71#ibcon#first serial, iclass 22, count 0 2006.245.08:05:42.71#ibcon#enter sib2, iclass 22, count 0 2006.245.08:05:42.71#ibcon#flushed, iclass 22, count 0 2006.245.08:05:42.71#ibcon#about to write, iclass 22, count 0 2006.245.08:05:42.71#ibcon#wrote, iclass 22, count 0 2006.245.08:05:42.71#ibcon#about to read 3, iclass 22, count 0 2006.245.08:05:42.73#ibcon#read 3, iclass 22, count 0 2006.245.08:05:42.73#ibcon#about to read 4, iclass 22, count 0 2006.245.08:05:42.73#ibcon#read 4, iclass 22, count 0 2006.245.08:05:42.73#ibcon#about to read 5, iclass 22, count 0 2006.245.08:05:42.73#ibcon#read 5, iclass 22, count 0 2006.245.08:05:42.73#ibcon#about to read 6, iclass 22, count 0 2006.245.08:05:42.73#ibcon#read 6, iclass 22, count 0 2006.245.08:05:42.73#ibcon#end of sib2, iclass 22, count 0 2006.245.08:05:42.73#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:05:42.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:05:42.73#ibcon#[25=USB\r\n] 2006.245.08:05:42.73#ibcon#*before write, iclass 22, count 0 2006.245.08:05:42.73#ibcon#enter sib2, iclass 22, count 0 2006.245.08:05:42.73#ibcon#flushed, iclass 22, count 0 2006.245.08:05:42.73#ibcon#about to write, iclass 22, count 0 2006.245.08:05:42.73#ibcon#wrote, iclass 22, count 0 2006.245.08:05:42.73#ibcon#about to read 3, iclass 22, count 0 2006.245.08:05:42.76#ibcon#read 3, iclass 22, count 0 2006.245.08:05:42.76#ibcon#about to read 4, iclass 22, count 0 2006.245.08:05:42.76#ibcon#read 4, iclass 22, count 0 2006.245.08:05:42.76#ibcon#about to read 5, iclass 22, count 0 2006.245.08:05:42.76#ibcon#read 5, iclass 22, count 0 2006.245.08:05:42.76#ibcon#about to read 6, iclass 22, count 0 2006.245.08:05:42.76#ibcon#read 6, iclass 22, count 0 2006.245.08:05:42.76#ibcon#end of sib2, iclass 22, count 0 2006.245.08:05:42.76#ibcon#*after write, iclass 22, count 0 2006.245.08:05:42.76#ibcon#*before return 0, iclass 22, count 0 2006.245.08:05:42.76#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:05:42.76#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:05:42.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:05:42.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:05:42.76$vc4f8/valo=8,852.99 2006.245.08:05:42.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:05:42.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:05:42.76#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:42.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:05:42.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:05:42.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:05:42.76#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:05:42.76#ibcon#first serial, iclass 24, count 0 2006.245.08:05:42.76#ibcon#enter sib2, iclass 24, count 0 2006.245.08:05:42.76#ibcon#flushed, iclass 24, count 0 2006.245.08:05:42.76#ibcon#about to write, iclass 24, count 0 2006.245.08:05:42.76#ibcon#wrote, iclass 24, count 0 2006.245.08:05:42.76#ibcon#about to read 3, iclass 24, count 0 2006.245.08:05:42.79#ibcon#read 3, iclass 24, count 0 2006.245.08:05:42.79#ibcon#about to read 4, iclass 24, count 0 2006.245.08:05:42.79#ibcon#read 4, iclass 24, count 0 2006.245.08:05:42.79#ibcon#about to read 5, iclass 24, count 0 2006.245.08:05:42.79#ibcon#read 5, iclass 24, count 0 2006.245.08:05:42.79#ibcon#about to read 6, iclass 24, count 0 2006.245.08:05:42.79#ibcon#read 6, iclass 24, count 0 2006.245.08:05:42.79#ibcon#end of sib2, iclass 24, count 0 2006.245.08:05:42.79#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:05:42.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:05:42.79#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:05:42.79#ibcon#*before write, iclass 24, count 0 2006.245.08:05:42.79#ibcon#enter sib2, iclass 24, count 0 2006.245.08:05:42.79#ibcon#flushed, iclass 24, count 0 2006.245.08:05:42.79#ibcon#about to write, iclass 24, count 0 2006.245.08:05:42.79#ibcon#wrote, iclass 24, count 0 2006.245.08:05:42.79#ibcon#about to read 3, iclass 24, count 0 2006.245.08:05:42.83#ibcon#read 3, iclass 24, count 0 2006.245.08:05:42.83#ibcon#about to read 4, iclass 24, count 0 2006.245.08:05:42.83#ibcon#read 4, iclass 24, count 0 2006.245.08:05:42.83#ibcon#about to read 5, iclass 24, count 0 2006.245.08:05:42.83#ibcon#read 5, iclass 24, count 0 2006.245.08:05:42.83#ibcon#about to read 6, iclass 24, count 0 2006.245.08:05:42.83#ibcon#read 6, iclass 24, count 0 2006.245.08:05:42.83#ibcon#end of sib2, iclass 24, count 0 2006.245.08:05:42.83#ibcon#*after write, iclass 24, count 0 2006.245.08:05:42.83#ibcon#*before return 0, iclass 24, count 0 2006.245.08:05:42.83#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:05:42.83#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:05:42.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:05:42.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:05:42.83$vc4f8/va=8,8 2006.245.08:05:42.83#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.08:05:42.83#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.08:05:42.83#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:42.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:05:42.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:05:42.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:05:42.88#ibcon#enter wrdev, iclass 26, count 2 2006.245.08:05:42.88#ibcon#first serial, iclass 26, count 2 2006.245.08:05:42.88#ibcon#enter sib2, iclass 26, count 2 2006.245.08:05:42.88#ibcon#flushed, iclass 26, count 2 2006.245.08:05:42.88#ibcon#about to write, iclass 26, count 2 2006.245.08:05:42.88#ibcon#wrote, iclass 26, count 2 2006.245.08:05:42.88#ibcon#about to read 3, iclass 26, count 2 2006.245.08:05:42.90#ibcon#read 3, iclass 26, count 2 2006.245.08:05:42.90#ibcon#about to read 4, iclass 26, count 2 2006.245.08:05:42.90#ibcon#read 4, iclass 26, count 2 2006.245.08:05:42.90#ibcon#about to read 5, iclass 26, count 2 2006.245.08:05:42.90#ibcon#read 5, iclass 26, count 2 2006.245.08:05:42.90#ibcon#about to read 6, iclass 26, count 2 2006.245.08:05:42.90#ibcon#read 6, iclass 26, count 2 2006.245.08:05:42.90#ibcon#end of sib2, iclass 26, count 2 2006.245.08:05:42.90#ibcon#*mode == 0, iclass 26, count 2 2006.245.08:05:42.90#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.08:05:42.90#ibcon#[25=AT08-08\r\n] 2006.245.08:05:42.90#ibcon#*before write, iclass 26, count 2 2006.245.08:05:42.90#ibcon#enter sib2, iclass 26, count 2 2006.245.08:05:42.90#ibcon#flushed, iclass 26, count 2 2006.245.08:05:42.90#ibcon#about to write, iclass 26, count 2 2006.245.08:05:42.90#ibcon#wrote, iclass 26, count 2 2006.245.08:05:42.90#ibcon#about to read 3, iclass 26, count 2 2006.245.08:05:42.93#ibcon#read 3, iclass 26, count 2 2006.245.08:05:42.93#ibcon#about to read 4, iclass 26, count 2 2006.245.08:05:42.93#ibcon#read 4, iclass 26, count 2 2006.245.08:05:42.93#ibcon#about to read 5, iclass 26, count 2 2006.245.08:05:42.93#ibcon#read 5, iclass 26, count 2 2006.245.08:05:42.93#ibcon#about to read 6, iclass 26, count 2 2006.245.08:05:42.93#ibcon#read 6, iclass 26, count 2 2006.245.08:05:42.93#ibcon#end of sib2, iclass 26, count 2 2006.245.08:05:42.93#ibcon#*after write, iclass 26, count 2 2006.245.08:05:42.93#ibcon#*before return 0, iclass 26, count 2 2006.245.08:05:42.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:05:42.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:05:42.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.08:05:42.93#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:42.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:05:43.05#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:05:43.05#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:05:43.05#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:05:43.05#ibcon#first serial, iclass 26, count 0 2006.245.08:05:43.05#ibcon#enter sib2, iclass 26, count 0 2006.245.08:05:43.05#ibcon#flushed, iclass 26, count 0 2006.245.08:05:43.05#ibcon#about to write, iclass 26, count 0 2006.245.08:05:43.05#ibcon#wrote, iclass 26, count 0 2006.245.08:05:43.05#ibcon#about to read 3, iclass 26, count 0 2006.245.08:05:43.07#ibcon#read 3, iclass 26, count 0 2006.245.08:05:43.07#ibcon#about to read 4, iclass 26, count 0 2006.245.08:05:43.07#ibcon#read 4, iclass 26, count 0 2006.245.08:05:43.07#ibcon#about to read 5, iclass 26, count 0 2006.245.08:05:43.07#ibcon#read 5, iclass 26, count 0 2006.245.08:05:43.07#ibcon#about to read 6, iclass 26, count 0 2006.245.08:05:43.07#ibcon#read 6, iclass 26, count 0 2006.245.08:05:43.07#ibcon#end of sib2, iclass 26, count 0 2006.245.08:05:43.07#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:05:43.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:05:43.07#ibcon#[25=USB\r\n] 2006.245.08:05:43.07#ibcon#*before write, iclass 26, count 0 2006.245.08:05:43.07#ibcon#enter sib2, iclass 26, count 0 2006.245.08:05:43.07#ibcon#flushed, iclass 26, count 0 2006.245.08:05:43.07#ibcon#about to write, iclass 26, count 0 2006.245.08:05:43.07#ibcon#wrote, iclass 26, count 0 2006.245.08:05:43.07#ibcon#about to read 3, iclass 26, count 0 2006.245.08:05:43.10#ibcon#read 3, iclass 26, count 0 2006.245.08:05:43.10#ibcon#about to read 4, iclass 26, count 0 2006.245.08:05:43.10#ibcon#read 4, iclass 26, count 0 2006.245.08:05:43.10#ibcon#about to read 5, iclass 26, count 0 2006.245.08:05:43.10#ibcon#read 5, iclass 26, count 0 2006.245.08:05:43.10#ibcon#about to read 6, iclass 26, count 0 2006.245.08:05:43.10#ibcon#read 6, iclass 26, count 0 2006.245.08:05:43.10#ibcon#end of sib2, iclass 26, count 0 2006.245.08:05:43.10#ibcon#*after write, iclass 26, count 0 2006.245.08:05:43.10#ibcon#*before return 0, iclass 26, count 0 2006.245.08:05:43.10#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:05:43.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:05:43.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:05:43.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:05:43.10$vc4f8/vblo=1,632.99 2006.245.08:05:43.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.08:05:43.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.08:05:43.10#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:43.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:43.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:43.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:43.10#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:05:43.10#ibcon#first serial, iclass 28, count 0 2006.245.08:05:43.10#ibcon#enter sib2, iclass 28, count 0 2006.245.08:05:43.10#ibcon#flushed, iclass 28, count 0 2006.245.08:05:43.10#ibcon#about to write, iclass 28, count 0 2006.245.08:05:43.10#ibcon#wrote, iclass 28, count 0 2006.245.08:05:43.10#ibcon#about to read 3, iclass 28, count 0 2006.245.08:05:43.12#ibcon#read 3, iclass 28, count 0 2006.245.08:05:43.12#ibcon#about to read 4, iclass 28, count 0 2006.245.08:05:43.12#ibcon#read 4, iclass 28, count 0 2006.245.08:05:43.12#ibcon#about to read 5, iclass 28, count 0 2006.245.08:05:43.12#ibcon#read 5, iclass 28, count 0 2006.245.08:05:43.12#ibcon#about to read 6, iclass 28, count 0 2006.245.08:05:43.12#ibcon#read 6, iclass 28, count 0 2006.245.08:05:43.12#ibcon#end of sib2, iclass 28, count 0 2006.245.08:05:43.12#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:05:43.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:05:43.12#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:05:43.12#ibcon#*before write, iclass 28, count 0 2006.245.08:05:43.12#ibcon#enter sib2, iclass 28, count 0 2006.245.08:05:43.12#ibcon#flushed, iclass 28, count 0 2006.245.08:05:43.12#ibcon#about to write, iclass 28, count 0 2006.245.08:05:43.12#ibcon#wrote, iclass 28, count 0 2006.245.08:05:43.12#ibcon#about to read 3, iclass 28, count 0 2006.245.08:05:43.16#ibcon#read 3, iclass 28, count 0 2006.245.08:05:43.16#ibcon#about to read 4, iclass 28, count 0 2006.245.08:05:43.16#ibcon#read 4, iclass 28, count 0 2006.245.08:05:43.16#ibcon#about to read 5, iclass 28, count 0 2006.245.08:05:43.16#ibcon#read 5, iclass 28, count 0 2006.245.08:05:43.16#ibcon#about to read 6, iclass 28, count 0 2006.245.08:05:43.16#ibcon#read 6, iclass 28, count 0 2006.245.08:05:43.16#ibcon#end of sib2, iclass 28, count 0 2006.245.08:05:43.16#ibcon#*after write, iclass 28, count 0 2006.245.08:05:43.16#ibcon#*before return 0, iclass 28, count 0 2006.245.08:05:43.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:43.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:05:43.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:05:43.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:05:43.16$vc4f8/vb=1,4 2006.245.08:05:43.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.08:05:43.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.08:05:43.16#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:43.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:43.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:43.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:43.16#ibcon#enter wrdev, iclass 30, count 2 2006.245.08:05:43.16#ibcon#first serial, iclass 30, count 2 2006.245.08:05:43.16#ibcon#enter sib2, iclass 30, count 2 2006.245.08:05:43.16#ibcon#flushed, iclass 30, count 2 2006.245.08:05:43.16#ibcon#about to write, iclass 30, count 2 2006.245.08:05:43.16#ibcon#wrote, iclass 30, count 2 2006.245.08:05:43.16#ibcon#about to read 3, iclass 30, count 2 2006.245.08:05:43.18#ibcon#read 3, iclass 30, count 2 2006.245.08:05:43.18#ibcon#about to read 4, iclass 30, count 2 2006.245.08:05:43.18#ibcon#read 4, iclass 30, count 2 2006.245.08:05:43.18#ibcon#about to read 5, iclass 30, count 2 2006.245.08:05:43.18#ibcon#read 5, iclass 30, count 2 2006.245.08:05:43.18#ibcon#about to read 6, iclass 30, count 2 2006.245.08:05:43.18#ibcon#read 6, iclass 30, count 2 2006.245.08:05:43.18#ibcon#end of sib2, iclass 30, count 2 2006.245.08:05:43.18#ibcon#*mode == 0, iclass 30, count 2 2006.245.08:05:43.18#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.08:05:43.18#ibcon#[27=AT01-04\r\n] 2006.245.08:05:43.18#ibcon#*before write, iclass 30, count 2 2006.245.08:05:43.18#ibcon#enter sib2, iclass 30, count 2 2006.245.08:05:43.18#ibcon#flushed, iclass 30, count 2 2006.245.08:05:43.18#ibcon#about to write, iclass 30, count 2 2006.245.08:05:43.18#ibcon#wrote, iclass 30, count 2 2006.245.08:05:43.18#ibcon#about to read 3, iclass 30, count 2 2006.245.08:05:43.21#ibcon#read 3, iclass 30, count 2 2006.245.08:05:43.21#ibcon#about to read 4, iclass 30, count 2 2006.245.08:05:43.21#ibcon#read 4, iclass 30, count 2 2006.245.08:05:43.21#ibcon#about to read 5, iclass 30, count 2 2006.245.08:05:43.21#ibcon#read 5, iclass 30, count 2 2006.245.08:05:43.21#ibcon#about to read 6, iclass 30, count 2 2006.245.08:05:43.21#ibcon#read 6, iclass 30, count 2 2006.245.08:05:43.21#ibcon#end of sib2, iclass 30, count 2 2006.245.08:05:43.21#ibcon#*after write, iclass 30, count 2 2006.245.08:05:43.21#ibcon#*before return 0, iclass 30, count 2 2006.245.08:05:43.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:43.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:05:43.21#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.08:05:43.21#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:43.21#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:43.33#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:43.33#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:43.33#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:05:43.33#ibcon#first serial, iclass 30, count 0 2006.245.08:05:43.33#ibcon#enter sib2, iclass 30, count 0 2006.245.08:05:43.33#ibcon#flushed, iclass 30, count 0 2006.245.08:05:43.33#ibcon#about to write, iclass 30, count 0 2006.245.08:05:43.33#ibcon#wrote, iclass 30, count 0 2006.245.08:05:43.33#ibcon#about to read 3, iclass 30, count 0 2006.245.08:05:43.35#ibcon#read 3, iclass 30, count 0 2006.245.08:05:43.35#ibcon#about to read 4, iclass 30, count 0 2006.245.08:05:43.35#ibcon#read 4, iclass 30, count 0 2006.245.08:05:43.35#ibcon#about to read 5, iclass 30, count 0 2006.245.08:05:43.35#ibcon#read 5, iclass 30, count 0 2006.245.08:05:43.35#ibcon#about to read 6, iclass 30, count 0 2006.245.08:05:43.35#ibcon#read 6, iclass 30, count 0 2006.245.08:05:43.35#ibcon#end of sib2, iclass 30, count 0 2006.245.08:05:43.35#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:05:43.35#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:05:43.35#ibcon#[27=USB\r\n] 2006.245.08:05:43.35#ibcon#*before write, iclass 30, count 0 2006.245.08:05:43.35#ibcon#enter sib2, iclass 30, count 0 2006.245.08:05:43.35#ibcon#flushed, iclass 30, count 0 2006.245.08:05:43.35#ibcon#about to write, iclass 30, count 0 2006.245.08:05:43.35#ibcon#wrote, iclass 30, count 0 2006.245.08:05:43.35#ibcon#about to read 3, iclass 30, count 0 2006.245.08:05:43.38#ibcon#read 3, iclass 30, count 0 2006.245.08:05:43.38#ibcon#about to read 4, iclass 30, count 0 2006.245.08:05:43.38#ibcon#read 4, iclass 30, count 0 2006.245.08:05:43.38#ibcon#about to read 5, iclass 30, count 0 2006.245.08:05:43.38#ibcon#read 5, iclass 30, count 0 2006.245.08:05:43.38#ibcon#about to read 6, iclass 30, count 0 2006.245.08:05:43.38#ibcon#read 6, iclass 30, count 0 2006.245.08:05:43.38#ibcon#end of sib2, iclass 30, count 0 2006.245.08:05:43.38#ibcon#*after write, iclass 30, count 0 2006.245.08:05:43.38#ibcon#*before return 0, iclass 30, count 0 2006.245.08:05:43.38#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:43.38#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:05:43.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:05:43.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:05:43.38$vc4f8/vblo=2,640.99 2006.245.08:05:43.38#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.08:05:43.38#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.08:05:43.38#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:43.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:43.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:43.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:43.38#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:05:43.38#ibcon#first serial, iclass 32, count 0 2006.245.08:05:43.38#ibcon#enter sib2, iclass 32, count 0 2006.245.08:05:43.38#ibcon#flushed, iclass 32, count 0 2006.245.08:05:43.38#ibcon#about to write, iclass 32, count 0 2006.245.08:05:43.38#ibcon#wrote, iclass 32, count 0 2006.245.08:05:43.38#ibcon#about to read 3, iclass 32, count 0 2006.245.08:05:43.40#ibcon#read 3, iclass 32, count 0 2006.245.08:05:43.40#ibcon#about to read 4, iclass 32, count 0 2006.245.08:05:43.40#ibcon#read 4, iclass 32, count 0 2006.245.08:05:43.40#ibcon#about to read 5, iclass 32, count 0 2006.245.08:05:43.40#ibcon#read 5, iclass 32, count 0 2006.245.08:05:43.40#ibcon#about to read 6, iclass 32, count 0 2006.245.08:05:43.40#ibcon#read 6, iclass 32, count 0 2006.245.08:05:43.40#ibcon#end of sib2, iclass 32, count 0 2006.245.08:05:43.40#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:05:43.40#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:05:43.40#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:05:43.40#ibcon#*before write, iclass 32, count 0 2006.245.08:05:43.40#ibcon#enter sib2, iclass 32, count 0 2006.245.08:05:43.40#ibcon#flushed, iclass 32, count 0 2006.245.08:05:43.40#ibcon#about to write, iclass 32, count 0 2006.245.08:05:43.40#ibcon#wrote, iclass 32, count 0 2006.245.08:05:43.40#ibcon#about to read 3, iclass 32, count 0 2006.245.08:05:43.44#ibcon#read 3, iclass 32, count 0 2006.245.08:05:43.44#ibcon#about to read 4, iclass 32, count 0 2006.245.08:05:43.44#ibcon#read 4, iclass 32, count 0 2006.245.08:05:43.44#ibcon#about to read 5, iclass 32, count 0 2006.245.08:05:43.44#ibcon#read 5, iclass 32, count 0 2006.245.08:05:43.44#ibcon#about to read 6, iclass 32, count 0 2006.245.08:05:43.44#ibcon#read 6, iclass 32, count 0 2006.245.08:05:43.44#ibcon#end of sib2, iclass 32, count 0 2006.245.08:05:43.44#ibcon#*after write, iclass 32, count 0 2006.245.08:05:43.44#ibcon#*before return 0, iclass 32, count 0 2006.245.08:05:43.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:43.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:05:43.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:05:43.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:05:43.44$vc4f8/vb=2,4 2006.245.08:05:43.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.08:05:43.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.08:05:43.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:43.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:43.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:43.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:43.50#ibcon#enter wrdev, iclass 34, count 2 2006.245.08:05:43.50#ibcon#first serial, iclass 34, count 2 2006.245.08:05:43.50#ibcon#enter sib2, iclass 34, count 2 2006.245.08:05:43.50#ibcon#flushed, iclass 34, count 2 2006.245.08:05:43.50#ibcon#about to write, iclass 34, count 2 2006.245.08:05:43.50#ibcon#wrote, iclass 34, count 2 2006.245.08:05:43.50#ibcon#about to read 3, iclass 34, count 2 2006.245.08:05:43.52#ibcon#read 3, iclass 34, count 2 2006.245.08:05:43.52#ibcon#about to read 4, iclass 34, count 2 2006.245.08:05:43.52#ibcon#read 4, iclass 34, count 2 2006.245.08:05:43.52#ibcon#about to read 5, iclass 34, count 2 2006.245.08:05:43.52#ibcon#read 5, iclass 34, count 2 2006.245.08:05:43.52#ibcon#about to read 6, iclass 34, count 2 2006.245.08:05:43.52#ibcon#read 6, iclass 34, count 2 2006.245.08:05:43.52#ibcon#end of sib2, iclass 34, count 2 2006.245.08:05:43.52#ibcon#*mode == 0, iclass 34, count 2 2006.245.08:05:43.52#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.08:05:43.52#ibcon#[27=AT02-04\r\n] 2006.245.08:05:43.52#ibcon#*before write, iclass 34, count 2 2006.245.08:05:43.52#ibcon#enter sib2, iclass 34, count 2 2006.245.08:05:43.52#ibcon#flushed, iclass 34, count 2 2006.245.08:05:43.52#ibcon#about to write, iclass 34, count 2 2006.245.08:05:43.52#ibcon#wrote, iclass 34, count 2 2006.245.08:05:43.52#ibcon#about to read 3, iclass 34, count 2 2006.245.08:05:43.55#ibcon#read 3, iclass 34, count 2 2006.245.08:05:43.55#ibcon#about to read 4, iclass 34, count 2 2006.245.08:05:43.55#ibcon#read 4, iclass 34, count 2 2006.245.08:05:43.55#ibcon#about to read 5, iclass 34, count 2 2006.245.08:05:43.55#ibcon#read 5, iclass 34, count 2 2006.245.08:05:43.55#ibcon#about to read 6, iclass 34, count 2 2006.245.08:05:43.55#ibcon#read 6, iclass 34, count 2 2006.245.08:05:43.55#ibcon#end of sib2, iclass 34, count 2 2006.245.08:05:43.55#ibcon#*after write, iclass 34, count 2 2006.245.08:05:43.55#ibcon#*before return 0, iclass 34, count 2 2006.245.08:05:43.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:43.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:05:43.55#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.08:05:43.55#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:43.55#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:43.67#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:43.67#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:43.67#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:05:43.67#ibcon#first serial, iclass 34, count 0 2006.245.08:05:43.67#ibcon#enter sib2, iclass 34, count 0 2006.245.08:05:43.67#ibcon#flushed, iclass 34, count 0 2006.245.08:05:43.67#ibcon#about to write, iclass 34, count 0 2006.245.08:05:43.67#ibcon#wrote, iclass 34, count 0 2006.245.08:05:43.67#ibcon#about to read 3, iclass 34, count 0 2006.245.08:05:43.69#ibcon#read 3, iclass 34, count 0 2006.245.08:05:43.69#ibcon#about to read 4, iclass 34, count 0 2006.245.08:05:43.69#ibcon#read 4, iclass 34, count 0 2006.245.08:05:43.69#ibcon#about to read 5, iclass 34, count 0 2006.245.08:05:43.69#ibcon#read 5, iclass 34, count 0 2006.245.08:05:43.69#ibcon#about to read 6, iclass 34, count 0 2006.245.08:05:43.69#ibcon#read 6, iclass 34, count 0 2006.245.08:05:43.69#ibcon#end of sib2, iclass 34, count 0 2006.245.08:05:43.69#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:05:43.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:05:43.69#ibcon#[27=USB\r\n] 2006.245.08:05:43.69#ibcon#*before write, iclass 34, count 0 2006.245.08:05:43.69#ibcon#enter sib2, iclass 34, count 0 2006.245.08:05:43.69#ibcon#flushed, iclass 34, count 0 2006.245.08:05:43.69#ibcon#about to write, iclass 34, count 0 2006.245.08:05:43.69#ibcon#wrote, iclass 34, count 0 2006.245.08:05:43.69#ibcon#about to read 3, iclass 34, count 0 2006.245.08:05:43.72#ibcon#read 3, iclass 34, count 0 2006.245.08:05:43.72#ibcon#about to read 4, iclass 34, count 0 2006.245.08:05:43.72#ibcon#read 4, iclass 34, count 0 2006.245.08:05:43.72#ibcon#about to read 5, iclass 34, count 0 2006.245.08:05:43.72#ibcon#read 5, iclass 34, count 0 2006.245.08:05:43.72#ibcon#about to read 6, iclass 34, count 0 2006.245.08:05:43.72#ibcon#read 6, iclass 34, count 0 2006.245.08:05:43.72#ibcon#end of sib2, iclass 34, count 0 2006.245.08:05:43.72#ibcon#*after write, iclass 34, count 0 2006.245.08:05:43.72#ibcon#*before return 0, iclass 34, count 0 2006.245.08:05:43.72#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:43.72#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:05:43.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:05:43.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:05:43.72$vc4f8/vblo=3,656.99 2006.245.08:05:43.72#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.08:05:43.72#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.08:05:43.72#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:43.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:43.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:43.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:43.72#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:05:43.72#ibcon#first serial, iclass 36, count 0 2006.245.08:05:43.72#ibcon#enter sib2, iclass 36, count 0 2006.245.08:05:43.72#ibcon#flushed, iclass 36, count 0 2006.245.08:05:43.72#ibcon#about to write, iclass 36, count 0 2006.245.08:05:43.72#ibcon#wrote, iclass 36, count 0 2006.245.08:05:43.72#ibcon#about to read 3, iclass 36, count 0 2006.245.08:05:43.75#ibcon#read 3, iclass 36, count 0 2006.245.08:05:43.75#ibcon#about to read 4, iclass 36, count 0 2006.245.08:05:43.75#ibcon#read 4, iclass 36, count 0 2006.245.08:05:43.75#ibcon#about to read 5, iclass 36, count 0 2006.245.08:05:43.75#ibcon#read 5, iclass 36, count 0 2006.245.08:05:43.75#ibcon#about to read 6, iclass 36, count 0 2006.245.08:05:43.75#ibcon#read 6, iclass 36, count 0 2006.245.08:05:43.75#ibcon#end of sib2, iclass 36, count 0 2006.245.08:05:43.75#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:05:43.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:05:43.75#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:05:43.75#ibcon#*before write, iclass 36, count 0 2006.245.08:05:43.75#ibcon#enter sib2, iclass 36, count 0 2006.245.08:05:43.75#ibcon#flushed, iclass 36, count 0 2006.245.08:05:43.75#ibcon#about to write, iclass 36, count 0 2006.245.08:05:43.75#ibcon#wrote, iclass 36, count 0 2006.245.08:05:43.75#ibcon#about to read 3, iclass 36, count 0 2006.245.08:05:43.79#ibcon#read 3, iclass 36, count 0 2006.245.08:05:43.79#ibcon#about to read 4, iclass 36, count 0 2006.245.08:05:43.79#ibcon#read 4, iclass 36, count 0 2006.245.08:05:43.79#ibcon#about to read 5, iclass 36, count 0 2006.245.08:05:43.79#ibcon#read 5, iclass 36, count 0 2006.245.08:05:43.79#ibcon#about to read 6, iclass 36, count 0 2006.245.08:05:43.79#ibcon#read 6, iclass 36, count 0 2006.245.08:05:43.79#ibcon#end of sib2, iclass 36, count 0 2006.245.08:05:43.79#ibcon#*after write, iclass 36, count 0 2006.245.08:05:43.79#ibcon#*before return 0, iclass 36, count 0 2006.245.08:05:43.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:43.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:05:43.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:05:43.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:05:43.79$vc4f8/vb=3,4 2006.245.08:05:43.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.08:05:43.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.08:05:43.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:43.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:43.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:43.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:43.84#ibcon#enter wrdev, iclass 38, count 2 2006.245.08:05:43.84#ibcon#first serial, iclass 38, count 2 2006.245.08:05:43.84#ibcon#enter sib2, iclass 38, count 2 2006.245.08:05:43.84#ibcon#flushed, iclass 38, count 2 2006.245.08:05:43.84#ibcon#about to write, iclass 38, count 2 2006.245.08:05:43.84#ibcon#wrote, iclass 38, count 2 2006.245.08:05:43.84#ibcon#about to read 3, iclass 38, count 2 2006.245.08:05:43.86#ibcon#read 3, iclass 38, count 2 2006.245.08:05:43.86#ibcon#about to read 4, iclass 38, count 2 2006.245.08:05:43.86#ibcon#read 4, iclass 38, count 2 2006.245.08:05:43.86#ibcon#about to read 5, iclass 38, count 2 2006.245.08:05:43.86#ibcon#read 5, iclass 38, count 2 2006.245.08:05:43.86#ibcon#about to read 6, iclass 38, count 2 2006.245.08:05:43.86#ibcon#read 6, iclass 38, count 2 2006.245.08:05:43.86#ibcon#end of sib2, iclass 38, count 2 2006.245.08:05:43.86#ibcon#*mode == 0, iclass 38, count 2 2006.245.08:05:43.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.08:05:43.86#ibcon#[27=AT03-04\r\n] 2006.245.08:05:43.86#ibcon#*before write, iclass 38, count 2 2006.245.08:05:43.86#ibcon#enter sib2, iclass 38, count 2 2006.245.08:05:43.86#ibcon#flushed, iclass 38, count 2 2006.245.08:05:43.86#ibcon#about to write, iclass 38, count 2 2006.245.08:05:43.86#ibcon#wrote, iclass 38, count 2 2006.245.08:05:43.86#ibcon#about to read 3, iclass 38, count 2 2006.245.08:05:43.89#ibcon#read 3, iclass 38, count 2 2006.245.08:05:43.89#ibcon#about to read 4, iclass 38, count 2 2006.245.08:05:43.89#ibcon#read 4, iclass 38, count 2 2006.245.08:05:43.89#ibcon#about to read 5, iclass 38, count 2 2006.245.08:05:43.89#ibcon#read 5, iclass 38, count 2 2006.245.08:05:43.89#ibcon#about to read 6, iclass 38, count 2 2006.245.08:05:43.89#ibcon#read 6, iclass 38, count 2 2006.245.08:05:43.89#ibcon#end of sib2, iclass 38, count 2 2006.245.08:05:43.89#ibcon#*after write, iclass 38, count 2 2006.245.08:05:43.89#ibcon#*before return 0, iclass 38, count 2 2006.245.08:05:43.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:43.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:05:43.89#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.08:05:43.89#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:43.89#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:44.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:44.01#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:44.01#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:05:44.01#ibcon#first serial, iclass 38, count 0 2006.245.08:05:44.01#ibcon#enter sib2, iclass 38, count 0 2006.245.08:05:44.01#ibcon#flushed, iclass 38, count 0 2006.245.08:05:44.01#ibcon#about to write, iclass 38, count 0 2006.245.08:05:44.01#ibcon#wrote, iclass 38, count 0 2006.245.08:05:44.01#ibcon#about to read 3, iclass 38, count 0 2006.245.08:05:44.03#ibcon#read 3, iclass 38, count 0 2006.245.08:05:44.03#ibcon#about to read 4, iclass 38, count 0 2006.245.08:05:44.03#ibcon#read 4, iclass 38, count 0 2006.245.08:05:44.03#ibcon#about to read 5, iclass 38, count 0 2006.245.08:05:44.03#ibcon#read 5, iclass 38, count 0 2006.245.08:05:44.03#ibcon#about to read 6, iclass 38, count 0 2006.245.08:05:44.03#ibcon#read 6, iclass 38, count 0 2006.245.08:05:44.03#ibcon#end of sib2, iclass 38, count 0 2006.245.08:05:44.03#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:05:44.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:05:44.03#ibcon#[27=USB\r\n] 2006.245.08:05:44.03#ibcon#*before write, iclass 38, count 0 2006.245.08:05:44.03#ibcon#enter sib2, iclass 38, count 0 2006.245.08:05:44.03#ibcon#flushed, iclass 38, count 0 2006.245.08:05:44.03#ibcon#about to write, iclass 38, count 0 2006.245.08:05:44.03#ibcon#wrote, iclass 38, count 0 2006.245.08:05:44.03#ibcon#about to read 3, iclass 38, count 0 2006.245.08:05:44.06#ibcon#read 3, iclass 38, count 0 2006.245.08:05:44.06#ibcon#about to read 4, iclass 38, count 0 2006.245.08:05:44.06#ibcon#read 4, iclass 38, count 0 2006.245.08:05:44.06#ibcon#about to read 5, iclass 38, count 0 2006.245.08:05:44.06#ibcon#read 5, iclass 38, count 0 2006.245.08:05:44.06#ibcon#about to read 6, iclass 38, count 0 2006.245.08:05:44.06#ibcon#read 6, iclass 38, count 0 2006.245.08:05:44.06#ibcon#end of sib2, iclass 38, count 0 2006.245.08:05:44.06#ibcon#*after write, iclass 38, count 0 2006.245.08:05:44.06#ibcon#*before return 0, iclass 38, count 0 2006.245.08:05:44.06#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:44.06#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:05:44.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:05:44.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:05:44.06$vc4f8/vblo=4,712.99 2006.245.08:05:44.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.08:05:44.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.08:05:44.06#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:44.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:44.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:44.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:44.06#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:05:44.06#ibcon#first serial, iclass 40, count 0 2006.245.08:05:44.06#ibcon#enter sib2, iclass 40, count 0 2006.245.08:05:44.06#ibcon#flushed, iclass 40, count 0 2006.245.08:05:44.06#ibcon#about to write, iclass 40, count 0 2006.245.08:05:44.06#ibcon#wrote, iclass 40, count 0 2006.245.08:05:44.06#ibcon#about to read 3, iclass 40, count 0 2006.245.08:05:44.08#ibcon#read 3, iclass 40, count 0 2006.245.08:05:44.08#ibcon#about to read 4, iclass 40, count 0 2006.245.08:05:44.08#ibcon#read 4, iclass 40, count 0 2006.245.08:05:44.08#ibcon#about to read 5, iclass 40, count 0 2006.245.08:05:44.08#ibcon#read 5, iclass 40, count 0 2006.245.08:05:44.08#ibcon#about to read 6, iclass 40, count 0 2006.245.08:05:44.08#ibcon#read 6, iclass 40, count 0 2006.245.08:05:44.08#ibcon#end of sib2, iclass 40, count 0 2006.245.08:05:44.08#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:05:44.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:05:44.08#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:05:44.08#ibcon#*before write, iclass 40, count 0 2006.245.08:05:44.08#ibcon#enter sib2, iclass 40, count 0 2006.245.08:05:44.08#ibcon#flushed, iclass 40, count 0 2006.245.08:05:44.08#ibcon#about to write, iclass 40, count 0 2006.245.08:05:44.08#ibcon#wrote, iclass 40, count 0 2006.245.08:05:44.08#ibcon#about to read 3, iclass 40, count 0 2006.245.08:05:44.12#ibcon#read 3, iclass 40, count 0 2006.245.08:05:44.12#ibcon#about to read 4, iclass 40, count 0 2006.245.08:05:44.12#ibcon#read 4, iclass 40, count 0 2006.245.08:05:44.12#ibcon#about to read 5, iclass 40, count 0 2006.245.08:05:44.12#ibcon#read 5, iclass 40, count 0 2006.245.08:05:44.12#ibcon#about to read 6, iclass 40, count 0 2006.245.08:05:44.12#ibcon#read 6, iclass 40, count 0 2006.245.08:05:44.12#ibcon#end of sib2, iclass 40, count 0 2006.245.08:05:44.12#ibcon#*after write, iclass 40, count 0 2006.245.08:05:44.12#ibcon#*before return 0, iclass 40, count 0 2006.245.08:05:44.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:44.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:05:44.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:05:44.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:05:44.12$vc4f8/vb=4,4 2006.245.08:05:44.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.08:05:44.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.08:05:44.12#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:44.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:44.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:44.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:44.18#ibcon#enter wrdev, iclass 4, count 2 2006.245.08:05:44.18#ibcon#first serial, iclass 4, count 2 2006.245.08:05:44.18#ibcon#enter sib2, iclass 4, count 2 2006.245.08:05:44.18#ibcon#flushed, iclass 4, count 2 2006.245.08:05:44.18#ibcon#about to write, iclass 4, count 2 2006.245.08:05:44.18#ibcon#wrote, iclass 4, count 2 2006.245.08:05:44.18#ibcon#about to read 3, iclass 4, count 2 2006.245.08:05:44.20#ibcon#read 3, iclass 4, count 2 2006.245.08:05:44.20#ibcon#about to read 4, iclass 4, count 2 2006.245.08:05:44.20#ibcon#read 4, iclass 4, count 2 2006.245.08:05:44.20#ibcon#about to read 5, iclass 4, count 2 2006.245.08:05:44.20#ibcon#read 5, iclass 4, count 2 2006.245.08:05:44.20#ibcon#about to read 6, iclass 4, count 2 2006.245.08:05:44.20#ibcon#read 6, iclass 4, count 2 2006.245.08:05:44.20#ibcon#end of sib2, iclass 4, count 2 2006.245.08:05:44.20#ibcon#*mode == 0, iclass 4, count 2 2006.245.08:05:44.20#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.08:05:44.20#ibcon#[27=AT04-04\r\n] 2006.245.08:05:44.20#ibcon#*before write, iclass 4, count 2 2006.245.08:05:44.20#ibcon#enter sib2, iclass 4, count 2 2006.245.08:05:44.20#ibcon#flushed, iclass 4, count 2 2006.245.08:05:44.20#ibcon#about to write, iclass 4, count 2 2006.245.08:05:44.20#ibcon#wrote, iclass 4, count 2 2006.245.08:05:44.20#ibcon#about to read 3, iclass 4, count 2 2006.245.08:05:44.23#ibcon#read 3, iclass 4, count 2 2006.245.08:05:44.23#ibcon#about to read 4, iclass 4, count 2 2006.245.08:05:44.23#ibcon#read 4, iclass 4, count 2 2006.245.08:05:44.23#ibcon#about to read 5, iclass 4, count 2 2006.245.08:05:44.23#ibcon#read 5, iclass 4, count 2 2006.245.08:05:44.23#ibcon#about to read 6, iclass 4, count 2 2006.245.08:05:44.23#ibcon#read 6, iclass 4, count 2 2006.245.08:05:44.23#ibcon#end of sib2, iclass 4, count 2 2006.245.08:05:44.23#ibcon#*after write, iclass 4, count 2 2006.245.08:05:44.23#ibcon#*before return 0, iclass 4, count 2 2006.245.08:05:44.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:44.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:05:44.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.08:05:44.23#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:44.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:44.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:44.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:44.35#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:05:44.35#ibcon#first serial, iclass 4, count 0 2006.245.08:05:44.35#ibcon#enter sib2, iclass 4, count 0 2006.245.08:05:44.35#ibcon#flushed, iclass 4, count 0 2006.245.08:05:44.35#ibcon#about to write, iclass 4, count 0 2006.245.08:05:44.35#ibcon#wrote, iclass 4, count 0 2006.245.08:05:44.35#ibcon#about to read 3, iclass 4, count 0 2006.245.08:05:44.37#ibcon#read 3, iclass 4, count 0 2006.245.08:05:44.37#ibcon#about to read 4, iclass 4, count 0 2006.245.08:05:44.37#ibcon#read 4, iclass 4, count 0 2006.245.08:05:44.37#ibcon#about to read 5, iclass 4, count 0 2006.245.08:05:44.37#ibcon#read 5, iclass 4, count 0 2006.245.08:05:44.37#ibcon#about to read 6, iclass 4, count 0 2006.245.08:05:44.37#ibcon#read 6, iclass 4, count 0 2006.245.08:05:44.37#ibcon#end of sib2, iclass 4, count 0 2006.245.08:05:44.37#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:05:44.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:05:44.37#ibcon#[27=USB\r\n] 2006.245.08:05:44.37#ibcon#*before write, iclass 4, count 0 2006.245.08:05:44.37#ibcon#enter sib2, iclass 4, count 0 2006.245.08:05:44.37#ibcon#flushed, iclass 4, count 0 2006.245.08:05:44.37#ibcon#about to write, iclass 4, count 0 2006.245.08:05:44.37#ibcon#wrote, iclass 4, count 0 2006.245.08:05:44.37#ibcon#about to read 3, iclass 4, count 0 2006.245.08:05:44.40#ibcon#read 3, iclass 4, count 0 2006.245.08:05:44.40#ibcon#about to read 4, iclass 4, count 0 2006.245.08:05:44.40#ibcon#read 4, iclass 4, count 0 2006.245.08:05:44.40#ibcon#about to read 5, iclass 4, count 0 2006.245.08:05:44.40#ibcon#read 5, iclass 4, count 0 2006.245.08:05:44.40#ibcon#about to read 6, iclass 4, count 0 2006.245.08:05:44.40#ibcon#read 6, iclass 4, count 0 2006.245.08:05:44.40#ibcon#end of sib2, iclass 4, count 0 2006.245.08:05:44.40#ibcon#*after write, iclass 4, count 0 2006.245.08:05:44.40#ibcon#*before return 0, iclass 4, count 0 2006.245.08:05:44.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:44.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:05:44.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:05:44.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:05:44.40$vc4f8/vblo=5,744.99 2006.245.08:05:44.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.08:05:44.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.08:05:44.40#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:44.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:05:44.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:05:44.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:05:44.40#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:05:44.40#ibcon#first serial, iclass 6, count 0 2006.245.08:05:44.40#ibcon#enter sib2, iclass 6, count 0 2006.245.08:05:44.40#ibcon#flushed, iclass 6, count 0 2006.245.08:05:44.40#ibcon#about to write, iclass 6, count 0 2006.245.08:05:44.40#ibcon#wrote, iclass 6, count 0 2006.245.08:05:44.40#ibcon#about to read 3, iclass 6, count 0 2006.245.08:05:44.42#ibcon#read 3, iclass 6, count 0 2006.245.08:05:44.42#ibcon#about to read 4, iclass 6, count 0 2006.245.08:05:44.42#ibcon#read 4, iclass 6, count 0 2006.245.08:05:44.42#ibcon#about to read 5, iclass 6, count 0 2006.245.08:05:44.42#ibcon#read 5, iclass 6, count 0 2006.245.08:05:44.42#ibcon#about to read 6, iclass 6, count 0 2006.245.08:05:44.42#ibcon#read 6, iclass 6, count 0 2006.245.08:05:44.42#ibcon#end of sib2, iclass 6, count 0 2006.245.08:05:44.42#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:05:44.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:05:44.42#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:05:44.42#ibcon#*before write, iclass 6, count 0 2006.245.08:05:44.42#ibcon#enter sib2, iclass 6, count 0 2006.245.08:05:44.42#ibcon#flushed, iclass 6, count 0 2006.245.08:05:44.42#ibcon#about to write, iclass 6, count 0 2006.245.08:05:44.42#ibcon#wrote, iclass 6, count 0 2006.245.08:05:44.42#ibcon#about to read 3, iclass 6, count 0 2006.245.08:05:44.46#ibcon#read 3, iclass 6, count 0 2006.245.08:05:44.46#ibcon#about to read 4, iclass 6, count 0 2006.245.08:05:44.46#ibcon#read 4, iclass 6, count 0 2006.245.08:05:44.46#ibcon#about to read 5, iclass 6, count 0 2006.245.08:05:44.46#ibcon#read 5, iclass 6, count 0 2006.245.08:05:44.46#ibcon#about to read 6, iclass 6, count 0 2006.245.08:05:44.46#ibcon#read 6, iclass 6, count 0 2006.245.08:05:44.46#ibcon#end of sib2, iclass 6, count 0 2006.245.08:05:44.46#ibcon#*after write, iclass 6, count 0 2006.245.08:05:44.46#ibcon#*before return 0, iclass 6, count 0 2006.245.08:05:44.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:05:44.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:05:44.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:05:44.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:05:44.46$vc4f8/vb=5,3 2006.245.08:05:44.46#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.08:05:44.46#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.08:05:44.46#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:44.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:05:44.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:05:44.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:05:44.52#ibcon#enter wrdev, iclass 10, count 2 2006.245.08:05:44.52#ibcon#first serial, iclass 10, count 2 2006.245.08:05:44.52#ibcon#enter sib2, iclass 10, count 2 2006.245.08:05:44.52#ibcon#flushed, iclass 10, count 2 2006.245.08:05:44.52#ibcon#about to write, iclass 10, count 2 2006.245.08:05:44.52#ibcon#wrote, iclass 10, count 2 2006.245.08:05:44.52#ibcon#about to read 3, iclass 10, count 2 2006.245.08:05:44.54#ibcon#read 3, iclass 10, count 2 2006.245.08:05:44.54#ibcon#about to read 4, iclass 10, count 2 2006.245.08:05:44.54#ibcon#read 4, iclass 10, count 2 2006.245.08:05:44.54#ibcon#about to read 5, iclass 10, count 2 2006.245.08:05:44.54#ibcon#read 5, iclass 10, count 2 2006.245.08:05:44.54#ibcon#about to read 6, iclass 10, count 2 2006.245.08:05:44.54#ibcon#read 6, iclass 10, count 2 2006.245.08:05:44.54#ibcon#end of sib2, iclass 10, count 2 2006.245.08:05:44.54#ibcon#*mode == 0, iclass 10, count 2 2006.245.08:05:44.54#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.08:05:44.54#ibcon#[27=AT05-03\r\n] 2006.245.08:05:44.54#ibcon#*before write, iclass 10, count 2 2006.245.08:05:44.54#ibcon#enter sib2, iclass 10, count 2 2006.245.08:05:44.54#ibcon#flushed, iclass 10, count 2 2006.245.08:05:44.54#ibcon#about to write, iclass 10, count 2 2006.245.08:05:44.54#ibcon#wrote, iclass 10, count 2 2006.245.08:05:44.54#ibcon#about to read 3, iclass 10, count 2 2006.245.08:05:44.57#ibcon#read 3, iclass 10, count 2 2006.245.08:05:44.57#ibcon#about to read 4, iclass 10, count 2 2006.245.08:05:44.57#ibcon#read 4, iclass 10, count 2 2006.245.08:05:44.57#ibcon#about to read 5, iclass 10, count 2 2006.245.08:05:44.57#ibcon#read 5, iclass 10, count 2 2006.245.08:05:44.57#ibcon#about to read 6, iclass 10, count 2 2006.245.08:05:44.57#ibcon#read 6, iclass 10, count 2 2006.245.08:05:44.57#ibcon#end of sib2, iclass 10, count 2 2006.245.08:05:44.57#ibcon#*after write, iclass 10, count 2 2006.245.08:05:44.57#ibcon#*before return 0, iclass 10, count 2 2006.245.08:05:44.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:05:44.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:05:44.57#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.08:05:44.57#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:44.57#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:05:44.69#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:05:44.69#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:05:44.69#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:05:44.69#ibcon#first serial, iclass 10, count 0 2006.245.08:05:44.69#ibcon#enter sib2, iclass 10, count 0 2006.245.08:05:44.69#ibcon#flushed, iclass 10, count 0 2006.245.08:05:44.69#ibcon#about to write, iclass 10, count 0 2006.245.08:05:44.69#ibcon#wrote, iclass 10, count 0 2006.245.08:05:44.69#ibcon#about to read 3, iclass 10, count 0 2006.245.08:05:44.71#ibcon#read 3, iclass 10, count 0 2006.245.08:05:44.71#ibcon#about to read 4, iclass 10, count 0 2006.245.08:05:44.71#ibcon#read 4, iclass 10, count 0 2006.245.08:05:44.71#ibcon#about to read 5, iclass 10, count 0 2006.245.08:05:44.71#ibcon#read 5, iclass 10, count 0 2006.245.08:05:44.71#ibcon#about to read 6, iclass 10, count 0 2006.245.08:05:44.71#ibcon#read 6, iclass 10, count 0 2006.245.08:05:44.71#ibcon#end of sib2, iclass 10, count 0 2006.245.08:05:44.71#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:05:44.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:05:44.71#ibcon#[27=USB\r\n] 2006.245.08:05:44.71#ibcon#*before write, iclass 10, count 0 2006.245.08:05:44.71#ibcon#enter sib2, iclass 10, count 0 2006.245.08:05:44.71#ibcon#flushed, iclass 10, count 0 2006.245.08:05:44.71#ibcon#about to write, iclass 10, count 0 2006.245.08:05:44.71#ibcon#wrote, iclass 10, count 0 2006.245.08:05:44.71#ibcon#about to read 3, iclass 10, count 0 2006.245.08:05:44.74#ibcon#read 3, iclass 10, count 0 2006.245.08:05:44.74#ibcon#about to read 4, iclass 10, count 0 2006.245.08:05:44.74#ibcon#read 4, iclass 10, count 0 2006.245.08:05:44.74#ibcon#about to read 5, iclass 10, count 0 2006.245.08:05:44.74#ibcon#read 5, iclass 10, count 0 2006.245.08:05:44.74#ibcon#about to read 6, iclass 10, count 0 2006.245.08:05:44.74#ibcon#read 6, iclass 10, count 0 2006.245.08:05:44.74#ibcon#end of sib2, iclass 10, count 0 2006.245.08:05:44.74#ibcon#*after write, iclass 10, count 0 2006.245.08:05:44.74#ibcon#*before return 0, iclass 10, count 0 2006.245.08:05:44.74#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:05:44.74#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:05:44.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:05:44.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:05:44.74$vc4f8/vblo=6,752.99 2006.245.08:05:44.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.08:05:44.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.08:05:44.74#ibcon#ireg 17 cls_cnt 0 2006.245.08:05:44.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:05:44.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:05:44.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:05:44.74#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:05:44.74#ibcon#first serial, iclass 12, count 0 2006.245.08:05:44.74#ibcon#enter sib2, iclass 12, count 0 2006.245.08:05:44.74#ibcon#flushed, iclass 12, count 0 2006.245.08:05:44.74#ibcon#about to write, iclass 12, count 0 2006.245.08:05:44.74#ibcon#wrote, iclass 12, count 0 2006.245.08:05:44.74#ibcon#about to read 3, iclass 12, count 0 2006.245.08:05:44.76#ibcon#read 3, iclass 12, count 0 2006.245.08:05:44.76#ibcon#about to read 4, iclass 12, count 0 2006.245.08:05:44.76#ibcon#read 4, iclass 12, count 0 2006.245.08:05:44.76#ibcon#about to read 5, iclass 12, count 0 2006.245.08:05:44.76#ibcon#read 5, iclass 12, count 0 2006.245.08:05:44.76#ibcon#about to read 6, iclass 12, count 0 2006.245.08:05:44.76#ibcon#read 6, iclass 12, count 0 2006.245.08:05:44.76#ibcon#end of sib2, iclass 12, count 0 2006.245.08:05:44.76#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:05:44.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:05:44.76#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:05:44.76#ibcon#*before write, iclass 12, count 0 2006.245.08:05:44.76#ibcon#enter sib2, iclass 12, count 0 2006.245.08:05:44.76#ibcon#flushed, iclass 12, count 0 2006.245.08:05:44.76#ibcon#about to write, iclass 12, count 0 2006.245.08:05:44.76#ibcon#wrote, iclass 12, count 0 2006.245.08:05:44.76#ibcon#about to read 3, iclass 12, count 0 2006.245.08:05:44.80#ibcon#read 3, iclass 12, count 0 2006.245.08:05:44.80#ibcon#about to read 4, iclass 12, count 0 2006.245.08:05:44.80#ibcon#read 4, iclass 12, count 0 2006.245.08:05:44.80#ibcon#about to read 5, iclass 12, count 0 2006.245.08:05:44.80#ibcon#read 5, iclass 12, count 0 2006.245.08:05:44.80#ibcon#about to read 6, iclass 12, count 0 2006.245.08:05:44.80#ibcon#read 6, iclass 12, count 0 2006.245.08:05:44.80#ibcon#end of sib2, iclass 12, count 0 2006.245.08:05:44.80#ibcon#*after write, iclass 12, count 0 2006.245.08:05:44.80#ibcon#*before return 0, iclass 12, count 0 2006.245.08:05:44.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:05:44.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:05:44.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:05:44.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:05:44.80$vc4f8/vb=6,3 2006.245.08:05:44.80#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.08:05:44.80#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.08:05:44.80#ibcon#ireg 11 cls_cnt 2 2006.245.08:05:44.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:05:44.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:05:44.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:05:44.86#ibcon#enter wrdev, iclass 14, count 2 2006.245.08:05:44.86#ibcon#first serial, iclass 14, count 2 2006.245.08:05:44.86#ibcon#enter sib2, iclass 14, count 2 2006.245.08:05:44.86#ibcon#flushed, iclass 14, count 2 2006.245.08:05:44.86#ibcon#about to write, iclass 14, count 2 2006.245.08:05:44.86#ibcon#wrote, iclass 14, count 2 2006.245.08:05:44.86#ibcon#about to read 3, iclass 14, count 2 2006.245.08:05:44.88#ibcon#read 3, iclass 14, count 2 2006.245.08:05:44.88#ibcon#about to read 4, iclass 14, count 2 2006.245.08:05:44.88#ibcon#read 4, iclass 14, count 2 2006.245.08:05:44.88#ibcon#about to read 5, iclass 14, count 2 2006.245.08:05:44.88#ibcon#read 5, iclass 14, count 2 2006.245.08:05:44.88#ibcon#about to read 6, iclass 14, count 2 2006.245.08:05:44.88#ibcon#read 6, iclass 14, count 2 2006.245.08:05:44.88#ibcon#end of sib2, iclass 14, count 2 2006.245.08:05:44.88#ibcon#*mode == 0, iclass 14, count 2 2006.245.08:05:44.88#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.08:05:44.88#ibcon#[27=AT06-03\r\n] 2006.245.08:05:44.88#ibcon#*before write, iclass 14, count 2 2006.245.08:05:44.88#ibcon#enter sib2, iclass 14, count 2 2006.245.08:05:44.88#ibcon#flushed, iclass 14, count 2 2006.245.08:05:44.88#ibcon#about to write, iclass 14, count 2 2006.245.08:05:44.88#ibcon#wrote, iclass 14, count 2 2006.245.08:05:44.88#ibcon#about to read 3, iclass 14, count 2 2006.245.08:05:44.91#ibcon#read 3, iclass 14, count 2 2006.245.08:05:44.91#ibcon#about to read 4, iclass 14, count 2 2006.245.08:05:44.91#ibcon#read 4, iclass 14, count 2 2006.245.08:05:44.91#ibcon#about to read 5, iclass 14, count 2 2006.245.08:05:44.91#ibcon#read 5, iclass 14, count 2 2006.245.08:05:44.91#ibcon#about to read 6, iclass 14, count 2 2006.245.08:05:44.91#ibcon#read 6, iclass 14, count 2 2006.245.08:05:44.91#ibcon#end of sib2, iclass 14, count 2 2006.245.08:05:44.91#ibcon#*after write, iclass 14, count 2 2006.245.08:05:44.91#ibcon#*before return 0, iclass 14, count 2 2006.245.08:05:44.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:05:44.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:05:44.91#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.08:05:44.91#ibcon#ireg 7 cls_cnt 0 2006.245.08:05:44.91#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:05:45.03#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:05:45.03#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:05:45.03#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:05:45.03#ibcon#first serial, iclass 14, count 0 2006.245.08:05:45.03#ibcon#enter sib2, iclass 14, count 0 2006.245.08:05:45.03#ibcon#flushed, iclass 14, count 0 2006.245.08:05:45.03#ibcon#about to write, iclass 14, count 0 2006.245.08:05:45.03#ibcon#wrote, iclass 14, count 0 2006.245.08:05:45.03#ibcon#about to read 3, iclass 14, count 0 2006.245.08:05:45.05#ibcon#read 3, iclass 14, count 0 2006.245.08:05:45.05#ibcon#about to read 4, iclass 14, count 0 2006.245.08:05:45.05#ibcon#read 4, iclass 14, count 0 2006.245.08:05:45.05#ibcon#about to read 5, iclass 14, count 0 2006.245.08:05:45.05#ibcon#read 5, iclass 14, count 0 2006.245.08:05:45.05#ibcon#about to read 6, iclass 14, count 0 2006.245.08:05:45.05#ibcon#read 6, iclass 14, count 0 2006.245.08:05:45.05#ibcon#end of sib2, iclass 14, count 0 2006.245.08:05:45.05#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:05:45.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:05:45.05#ibcon#[27=USB\r\n] 2006.245.08:05:45.05#ibcon#*before write, iclass 14, count 0 2006.245.08:05:45.05#ibcon#enter sib2, iclass 14, count 0 2006.245.08:05:45.05#ibcon#flushed, iclass 14, count 0 2006.245.08:05:45.05#ibcon#about to write, iclass 14, count 0 2006.245.08:05:45.05#ibcon#wrote, iclass 14, count 0 2006.245.08:05:45.05#ibcon#about to read 3, iclass 14, count 0 2006.245.08:05:45.08#ibcon#read 3, iclass 14, count 0 2006.245.08:05:45.08#ibcon#about to read 4, iclass 14, count 0 2006.245.08:05:45.08#ibcon#read 4, iclass 14, count 0 2006.245.08:05:45.08#ibcon#about to read 5, iclass 14, count 0 2006.245.08:05:45.08#ibcon#read 5, iclass 14, count 0 2006.245.08:05:45.08#ibcon#about to read 6, iclass 14, count 0 2006.245.08:05:45.08#ibcon#read 6, iclass 14, count 0 2006.245.08:05:45.08#ibcon#end of sib2, iclass 14, count 0 2006.245.08:05:45.08#ibcon#*after write, iclass 14, count 0 2006.245.08:05:45.08#ibcon#*before return 0, iclass 14, count 0 2006.245.08:05:45.08#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:05:45.08#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:05:45.08#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:05:45.08#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:05:45.08$vc4f8/vabw=wide 2006.245.08:05:45.08#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.08:05:45.08#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.08:05:45.08#ibcon#ireg 8 cls_cnt 0 2006.245.08:05:45.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:45.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:45.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:45.08#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:05:45.08#ibcon#first serial, iclass 16, count 0 2006.245.08:05:45.08#ibcon#enter sib2, iclass 16, count 0 2006.245.08:05:45.08#ibcon#flushed, iclass 16, count 0 2006.245.08:05:45.08#ibcon#about to write, iclass 16, count 0 2006.245.08:05:45.08#ibcon#wrote, iclass 16, count 0 2006.245.08:05:45.08#ibcon#about to read 3, iclass 16, count 0 2006.245.08:05:45.10#ibcon#read 3, iclass 16, count 0 2006.245.08:05:45.10#ibcon#about to read 4, iclass 16, count 0 2006.245.08:05:45.10#ibcon#read 4, iclass 16, count 0 2006.245.08:05:45.10#ibcon#about to read 5, iclass 16, count 0 2006.245.08:05:45.10#ibcon#read 5, iclass 16, count 0 2006.245.08:05:45.10#ibcon#about to read 6, iclass 16, count 0 2006.245.08:05:45.10#ibcon#read 6, iclass 16, count 0 2006.245.08:05:45.10#ibcon#end of sib2, iclass 16, count 0 2006.245.08:05:45.10#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:05:45.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:05:45.10#ibcon#[25=BW32\r\n] 2006.245.08:05:45.10#ibcon#*before write, iclass 16, count 0 2006.245.08:05:45.10#ibcon#enter sib2, iclass 16, count 0 2006.245.08:05:45.10#ibcon#flushed, iclass 16, count 0 2006.245.08:05:45.10#ibcon#about to write, iclass 16, count 0 2006.245.08:05:45.10#ibcon#wrote, iclass 16, count 0 2006.245.08:05:45.10#ibcon#about to read 3, iclass 16, count 0 2006.245.08:05:45.13#ibcon#read 3, iclass 16, count 0 2006.245.08:05:45.13#ibcon#about to read 4, iclass 16, count 0 2006.245.08:05:45.13#ibcon#read 4, iclass 16, count 0 2006.245.08:05:45.13#ibcon#about to read 5, iclass 16, count 0 2006.245.08:05:45.13#ibcon#read 5, iclass 16, count 0 2006.245.08:05:45.13#ibcon#about to read 6, iclass 16, count 0 2006.245.08:05:45.13#ibcon#read 6, iclass 16, count 0 2006.245.08:05:45.13#ibcon#end of sib2, iclass 16, count 0 2006.245.08:05:45.13#ibcon#*after write, iclass 16, count 0 2006.245.08:05:45.13#ibcon#*before return 0, iclass 16, count 0 2006.245.08:05:45.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:45.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:05:45.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:05:45.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:05:45.13$vc4f8/vbbw=wide 2006.245.08:05:45.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.08:05:45.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.08:05:45.13#ibcon#ireg 8 cls_cnt 0 2006.245.08:05:45.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:05:45.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:05:45.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:05:45.20#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:05:45.20#ibcon#first serial, iclass 18, count 0 2006.245.08:05:45.20#ibcon#enter sib2, iclass 18, count 0 2006.245.08:05:45.20#ibcon#flushed, iclass 18, count 0 2006.245.08:05:45.20#ibcon#about to write, iclass 18, count 0 2006.245.08:05:45.20#ibcon#wrote, iclass 18, count 0 2006.245.08:05:45.20#ibcon#about to read 3, iclass 18, count 0 2006.245.08:05:45.22#ibcon#read 3, iclass 18, count 0 2006.245.08:05:45.22#ibcon#about to read 4, iclass 18, count 0 2006.245.08:05:45.22#ibcon#read 4, iclass 18, count 0 2006.245.08:05:45.22#ibcon#about to read 5, iclass 18, count 0 2006.245.08:05:45.22#ibcon#read 5, iclass 18, count 0 2006.245.08:05:45.22#ibcon#about to read 6, iclass 18, count 0 2006.245.08:05:45.22#ibcon#read 6, iclass 18, count 0 2006.245.08:05:45.22#ibcon#end of sib2, iclass 18, count 0 2006.245.08:05:45.22#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:05:45.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:05:45.22#ibcon#[27=BW32\r\n] 2006.245.08:05:45.22#ibcon#*before write, iclass 18, count 0 2006.245.08:05:45.22#ibcon#enter sib2, iclass 18, count 0 2006.245.08:05:45.22#ibcon#flushed, iclass 18, count 0 2006.245.08:05:45.22#ibcon#about to write, iclass 18, count 0 2006.245.08:05:45.22#ibcon#wrote, iclass 18, count 0 2006.245.08:05:45.22#ibcon#about to read 3, iclass 18, count 0 2006.245.08:05:45.25#ibcon#read 3, iclass 18, count 0 2006.245.08:05:45.25#ibcon#about to read 4, iclass 18, count 0 2006.245.08:05:45.25#ibcon#read 4, iclass 18, count 0 2006.245.08:05:45.25#ibcon#about to read 5, iclass 18, count 0 2006.245.08:05:45.25#ibcon#read 5, iclass 18, count 0 2006.245.08:05:45.25#ibcon#about to read 6, iclass 18, count 0 2006.245.08:05:45.25#ibcon#read 6, iclass 18, count 0 2006.245.08:05:45.25#ibcon#end of sib2, iclass 18, count 0 2006.245.08:05:45.25#ibcon#*after write, iclass 18, count 0 2006.245.08:05:45.25#ibcon#*before return 0, iclass 18, count 0 2006.245.08:05:45.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:05:45.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:05:45.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:05:45.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:05:45.25$4f8m12a/ifd4f 2006.245.08:05:45.25$ifd4f/lo= 2006.245.08:05:45.25$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:05:45.25$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:05:45.25$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:05:45.25$ifd4f/patch= 2006.245.08:05:45.25$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:05:45.25$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:05:45.25$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:05:45.25$4f8m12a/"form=m,16.000,1:2 2006.245.08:05:45.25$4f8m12a/"tpicd 2006.245.08:05:45.25$4f8m12a/echo=off 2006.245.08:05:45.25$4f8m12a/xlog=off 2006.245.08:05:45.25:!2006.245.08:06:30 2006.245.08:06:04.14#trakl#Source acquired 2006.245.08:06:04.14#flagr#flagr/antenna,acquired 2006.245.08:06:30.00:preob 2006.245.08:06:30.14/onsource/TRACKING 2006.245.08:06:30.14:!2006.245.08:06:40 2006.245.08:06:40.00:data_valid=on 2006.245.08:06:40.00:midob 2006.245.08:06:40.14/onsource/TRACKING 2006.245.08:06:40.14/wx/27.02,1004.5,72 2006.245.08:06:40.29/cable/+6.4118E-03 2006.245.08:06:41.38/va/01,08,usb,yes,32,33 2006.245.08:06:41.38/va/02,07,usb,yes,31,33 2006.245.08:06:41.38/va/03,06,usb,yes,33,34 2006.245.08:06:41.38/va/04,07,usb,yes,32,35 2006.245.08:06:41.38/va/05,07,usb,yes,34,36 2006.245.08:06:41.38/va/06,07,usb,yes,29,29 2006.245.08:06:41.38/va/07,07,usb,yes,29,29 2006.245.08:06:41.38/va/08,08,usb,yes,26,25 2006.245.08:06:41.61/valo/01,532.99,yes,locked 2006.245.08:06:41.61/valo/02,572.99,yes,locked 2006.245.08:06:41.61/valo/03,672.99,yes,locked 2006.245.08:06:41.61/valo/04,832.99,yes,locked 2006.245.08:06:41.61/valo/05,652.99,yes,locked 2006.245.08:06:41.61/valo/06,772.99,yes,locked 2006.245.08:06:41.61/valo/07,832.99,yes,locked 2006.245.08:06:41.61/valo/08,852.99,yes,locked 2006.245.08:06:42.70/vb/01,04,usb,yes,31,30 2006.245.08:06:42.70/vb/02,04,usb,yes,33,34 2006.245.08:06:42.70/vb/03,04,usb,yes,29,33 2006.245.08:06:42.70/vb/04,04,usb,yes,30,30 2006.245.08:06:42.70/vb/05,03,usb,yes,35,40 2006.245.08:06:42.70/vb/06,03,usb,yes,36,40 2006.245.08:06:42.70/vb/07,04,usb,yes,32,31 2006.245.08:06:42.70/vb/08,03,usb,yes,36,40 2006.245.08:06:42.93/vblo/01,632.99,yes,locked 2006.245.08:06:42.93/vblo/02,640.99,yes,locked 2006.245.08:06:42.93/vblo/03,656.99,yes,locked 2006.245.08:06:42.93/vblo/04,712.99,yes,locked 2006.245.08:06:42.93/vblo/05,744.99,yes,locked 2006.245.08:06:42.93/vblo/06,752.99,yes,locked 2006.245.08:06:42.93/vblo/07,734.99,yes,locked 2006.245.08:06:42.93/vblo/08,744.99,yes,locked 2006.245.08:06:43.08/vabw/8 2006.245.08:06:43.23/vbbw/8 2006.245.08:06:43.32/xfe/off,on,14.0 2006.245.08:06:43.70/ifatt/23,28,28,28 2006.245.08:06:44.07/fmout-gps/S +4.38E-07 2006.245.08:06:44.11:!2006.245.08:08:00 2006.245.08:08:00.00:data_valid=off 2006.245.08:08:00.00:postob 2006.245.08:08:00.09/cable/+6.4097E-03 2006.245.08:08:00.09/wx/27.00,1004.5,73 2006.245.08:08:01.07/fmout-gps/S +4.38E-07 2006.245.08:08:01.07:scan_name=245-0809,k06245,60 2006.245.08:08:01.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.245.08:08:02.13#flagr#flagr/antenna,new-source 2006.245.08:08:02.14:checkk5 2006.245.08:08:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:08:03.00/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:08:03.43/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:08:04.02/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:08:04.46/chk_obsdata//k5ts1/T2450806??a.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.08:08:05.11/chk_obsdata//k5ts2/T2450806??b.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.08:08:05.64/chk_obsdata//k5ts3/T2450806??c.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.08:08:06.04/chk_obsdata//k5ts4/T2450806??d.dat file size is correct (nominal:640MB, actual:632MB). 2006.245.08:08:07.06/k5log//k5ts1_log_newline 2006.245.08:08:07.84/k5log//k5ts2_log_newline 2006.245.08:08:09.25/k5log//k5ts3_log_newline 2006.245.08:08:10.05/k5log//k5ts4_log_newline 2006.245.08:08:10.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:08:10.08:4f8m12a=2 2006.245.08:08:10.08$4f8m12a/echo=on 2006.245.08:08:10.08$4f8m12a/pcalon 2006.245.08:08:10.08$pcalon/"no phase cal control is implemented here 2006.245.08:08:10.08$4f8m12a/"tpicd=stop 2006.245.08:08:10.08$4f8m12a/vc4f8 2006.245.08:08:10.08$vc4f8/valo=1,532.99 2006.245.08:08:10.08#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:08:10.08#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:08:10.08#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:10.08#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:10.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:10.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:10.08#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:08:10.08#ibcon#first serial, iclass 3, count 0 2006.245.08:08:10.08#ibcon#enter sib2, iclass 3, count 0 2006.245.08:08:10.08#ibcon#flushed, iclass 3, count 0 2006.245.08:08:10.08#ibcon#about to write, iclass 3, count 0 2006.245.08:08:10.08#ibcon#wrote, iclass 3, count 0 2006.245.08:08:10.08#ibcon#about to read 3, iclass 3, count 0 2006.245.08:08:10.12#ibcon#read 3, iclass 3, count 0 2006.245.08:08:10.12#ibcon#about to read 4, iclass 3, count 0 2006.245.08:08:10.12#ibcon#read 4, iclass 3, count 0 2006.245.08:08:10.12#ibcon#about to read 5, iclass 3, count 0 2006.245.08:08:10.12#ibcon#read 5, iclass 3, count 0 2006.245.08:08:10.12#ibcon#about to read 6, iclass 3, count 0 2006.245.08:08:10.12#ibcon#read 6, iclass 3, count 0 2006.245.08:08:10.12#ibcon#end of sib2, iclass 3, count 0 2006.245.08:08:10.12#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:08:10.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:08:10.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:08:10.12#ibcon#*before write, iclass 3, count 0 2006.245.08:08:10.12#ibcon#enter sib2, iclass 3, count 0 2006.245.08:08:10.12#ibcon#flushed, iclass 3, count 0 2006.245.08:08:10.12#ibcon#about to write, iclass 3, count 0 2006.245.08:08:10.12#ibcon#wrote, iclass 3, count 0 2006.245.08:08:10.12#ibcon#about to read 3, iclass 3, count 0 2006.245.08:08:10.16#ibcon#read 3, iclass 3, count 0 2006.245.08:08:10.16#ibcon#about to read 4, iclass 3, count 0 2006.245.08:08:10.16#ibcon#read 4, iclass 3, count 0 2006.245.08:08:10.16#ibcon#about to read 5, iclass 3, count 0 2006.245.08:08:10.16#ibcon#read 5, iclass 3, count 0 2006.245.08:08:10.16#ibcon#about to read 6, iclass 3, count 0 2006.245.08:08:10.16#ibcon#read 6, iclass 3, count 0 2006.245.08:08:10.16#ibcon#end of sib2, iclass 3, count 0 2006.245.08:08:10.16#ibcon#*after write, iclass 3, count 0 2006.245.08:08:10.16#ibcon#*before return 0, iclass 3, count 0 2006.245.08:08:10.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:10.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:10.16#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:08:10.16#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:08:10.16$vc4f8/va=1,8 2006.245.08:08:10.16#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:08:10.16#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:08:10.16#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:10.16#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:10.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:10.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:10.16#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:08:10.16#ibcon#first serial, iclass 5, count 2 2006.245.08:08:10.16#ibcon#enter sib2, iclass 5, count 2 2006.245.08:08:10.16#ibcon#flushed, iclass 5, count 2 2006.245.08:08:10.16#ibcon#about to write, iclass 5, count 2 2006.245.08:08:10.16#ibcon#wrote, iclass 5, count 2 2006.245.08:08:10.16#ibcon#about to read 3, iclass 5, count 2 2006.245.08:08:10.18#ibcon#read 3, iclass 5, count 2 2006.245.08:08:10.18#ibcon#about to read 4, iclass 5, count 2 2006.245.08:08:10.18#ibcon#read 4, iclass 5, count 2 2006.245.08:08:10.18#ibcon#about to read 5, iclass 5, count 2 2006.245.08:08:10.18#ibcon#read 5, iclass 5, count 2 2006.245.08:08:10.18#ibcon#about to read 6, iclass 5, count 2 2006.245.08:08:10.18#ibcon#read 6, iclass 5, count 2 2006.245.08:08:10.18#ibcon#end of sib2, iclass 5, count 2 2006.245.08:08:10.18#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:08:10.18#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:08:10.18#ibcon#[25=AT01-08\r\n] 2006.245.08:08:10.18#ibcon#*before write, iclass 5, count 2 2006.245.08:08:10.18#ibcon#enter sib2, iclass 5, count 2 2006.245.08:08:10.18#ibcon#flushed, iclass 5, count 2 2006.245.08:08:10.18#ibcon#about to write, iclass 5, count 2 2006.245.08:08:10.18#ibcon#wrote, iclass 5, count 2 2006.245.08:08:10.18#ibcon#about to read 3, iclass 5, count 2 2006.245.08:08:10.21#ibcon#read 3, iclass 5, count 2 2006.245.08:08:10.21#ibcon#about to read 4, iclass 5, count 2 2006.245.08:08:10.21#ibcon#read 4, iclass 5, count 2 2006.245.08:08:10.21#ibcon#about to read 5, iclass 5, count 2 2006.245.08:08:10.21#ibcon#read 5, iclass 5, count 2 2006.245.08:08:10.21#ibcon#about to read 6, iclass 5, count 2 2006.245.08:08:10.21#ibcon#read 6, iclass 5, count 2 2006.245.08:08:10.21#ibcon#end of sib2, iclass 5, count 2 2006.245.08:08:10.21#ibcon#*after write, iclass 5, count 2 2006.245.08:08:10.21#ibcon#*before return 0, iclass 5, count 2 2006.245.08:08:10.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:10.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:10.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:08:10.21#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:10.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:10.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:10.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:10.33#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:08:10.33#ibcon#first serial, iclass 5, count 0 2006.245.08:08:10.33#ibcon#enter sib2, iclass 5, count 0 2006.245.08:08:10.33#ibcon#flushed, iclass 5, count 0 2006.245.08:08:10.33#ibcon#about to write, iclass 5, count 0 2006.245.08:08:10.33#ibcon#wrote, iclass 5, count 0 2006.245.08:08:10.33#ibcon#about to read 3, iclass 5, count 0 2006.245.08:08:10.35#ibcon#read 3, iclass 5, count 0 2006.245.08:08:10.35#ibcon#about to read 4, iclass 5, count 0 2006.245.08:08:10.35#ibcon#read 4, iclass 5, count 0 2006.245.08:08:10.35#ibcon#about to read 5, iclass 5, count 0 2006.245.08:08:10.35#ibcon#read 5, iclass 5, count 0 2006.245.08:08:10.35#ibcon#about to read 6, iclass 5, count 0 2006.245.08:08:10.35#ibcon#read 6, iclass 5, count 0 2006.245.08:08:10.35#ibcon#end of sib2, iclass 5, count 0 2006.245.08:08:10.35#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:08:10.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:08:10.35#ibcon#[25=USB\r\n] 2006.245.08:08:10.35#ibcon#*before write, iclass 5, count 0 2006.245.08:08:10.35#ibcon#enter sib2, iclass 5, count 0 2006.245.08:08:10.35#ibcon#flushed, iclass 5, count 0 2006.245.08:08:10.35#ibcon#about to write, iclass 5, count 0 2006.245.08:08:10.35#ibcon#wrote, iclass 5, count 0 2006.245.08:08:10.35#ibcon#about to read 3, iclass 5, count 0 2006.245.08:08:10.38#ibcon#read 3, iclass 5, count 0 2006.245.08:08:10.38#ibcon#about to read 4, iclass 5, count 0 2006.245.08:08:10.38#ibcon#read 4, iclass 5, count 0 2006.245.08:08:10.38#ibcon#about to read 5, iclass 5, count 0 2006.245.08:08:10.38#ibcon#read 5, iclass 5, count 0 2006.245.08:08:10.38#ibcon#about to read 6, iclass 5, count 0 2006.245.08:08:10.38#ibcon#read 6, iclass 5, count 0 2006.245.08:08:10.38#ibcon#end of sib2, iclass 5, count 0 2006.245.08:08:10.38#ibcon#*after write, iclass 5, count 0 2006.245.08:08:10.38#ibcon#*before return 0, iclass 5, count 0 2006.245.08:08:10.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:10.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:10.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:08:10.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:08:10.38$vc4f8/valo=2,572.99 2006.245.08:08:10.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:08:10.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:08:10.38#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:10.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:10.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:10.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:10.38#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:08:10.38#ibcon#first serial, iclass 7, count 0 2006.245.08:08:10.38#ibcon#enter sib2, iclass 7, count 0 2006.245.08:08:10.38#ibcon#flushed, iclass 7, count 0 2006.245.08:08:10.38#ibcon#about to write, iclass 7, count 0 2006.245.08:08:10.38#ibcon#wrote, iclass 7, count 0 2006.245.08:08:10.38#ibcon#about to read 3, iclass 7, count 0 2006.245.08:08:10.41#ibcon#read 3, iclass 7, count 0 2006.245.08:08:10.41#ibcon#about to read 4, iclass 7, count 0 2006.245.08:08:10.41#ibcon#read 4, iclass 7, count 0 2006.245.08:08:10.41#ibcon#about to read 5, iclass 7, count 0 2006.245.08:08:10.41#ibcon#read 5, iclass 7, count 0 2006.245.08:08:10.41#ibcon#about to read 6, iclass 7, count 0 2006.245.08:08:10.41#ibcon#read 6, iclass 7, count 0 2006.245.08:08:10.41#ibcon#end of sib2, iclass 7, count 0 2006.245.08:08:10.41#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:08:10.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:08:10.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:08:10.41#ibcon#*before write, iclass 7, count 0 2006.245.08:08:10.41#ibcon#enter sib2, iclass 7, count 0 2006.245.08:08:10.41#ibcon#flushed, iclass 7, count 0 2006.245.08:08:10.41#ibcon#about to write, iclass 7, count 0 2006.245.08:08:10.41#ibcon#wrote, iclass 7, count 0 2006.245.08:08:10.41#ibcon#about to read 3, iclass 7, count 0 2006.245.08:08:10.45#ibcon#read 3, iclass 7, count 0 2006.245.08:08:10.45#ibcon#about to read 4, iclass 7, count 0 2006.245.08:08:10.45#ibcon#read 4, iclass 7, count 0 2006.245.08:08:10.45#ibcon#about to read 5, iclass 7, count 0 2006.245.08:08:10.45#ibcon#read 5, iclass 7, count 0 2006.245.08:08:10.45#ibcon#about to read 6, iclass 7, count 0 2006.245.08:08:10.45#ibcon#read 6, iclass 7, count 0 2006.245.08:08:10.45#ibcon#end of sib2, iclass 7, count 0 2006.245.08:08:10.45#ibcon#*after write, iclass 7, count 0 2006.245.08:08:10.45#ibcon#*before return 0, iclass 7, count 0 2006.245.08:08:10.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:10.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:10.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:08:10.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:08:10.45$vc4f8/va=2,7 2006.245.08:08:10.45#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:08:10.45#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:08:10.45#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:10.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:10.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:10.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:10.50#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:08:10.50#ibcon#first serial, iclass 11, count 2 2006.245.08:08:10.50#ibcon#enter sib2, iclass 11, count 2 2006.245.08:08:10.50#ibcon#flushed, iclass 11, count 2 2006.245.08:08:10.50#ibcon#about to write, iclass 11, count 2 2006.245.08:08:10.50#ibcon#wrote, iclass 11, count 2 2006.245.08:08:10.50#ibcon#about to read 3, iclass 11, count 2 2006.245.08:08:10.52#ibcon#read 3, iclass 11, count 2 2006.245.08:08:10.52#ibcon#about to read 4, iclass 11, count 2 2006.245.08:08:10.52#ibcon#read 4, iclass 11, count 2 2006.245.08:08:10.52#ibcon#about to read 5, iclass 11, count 2 2006.245.08:08:10.52#ibcon#read 5, iclass 11, count 2 2006.245.08:08:10.52#ibcon#about to read 6, iclass 11, count 2 2006.245.08:08:10.52#ibcon#read 6, iclass 11, count 2 2006.245.08:08:10.52#ibcon#end of sib2, iclass 11, count 2 2006.245.08:08:10.52#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:08:10.52#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:08:10.52#ibcon#[25=AT02-07\r\n] 2006.245.08:08:10.52#ibcon#*before write, iclass 11, count 2 2006.245.08:08:10.52#ibcon#enter sib2, iclass 11, count 2 2006.245.08:08:10.52#ibcon#flushed, iclass 11, count 2 2006.245.08:08:10.52#ibcon#about to write, iclass 11, count 2 2006.245.08:08:10.52#ibcon#wrote, iclass 11, count 2 2006.245.08:08:10.52#ibcon#about to read 3, iclass 11, count 2 2006.245.08:08:10.55#ibcon#read 3, iclass 11, count 2 2006.245.08:08:10.55#ibcon#about to read 4, iclass 11, count 2 2006.245.08:08:10.55#ibcon#read 4, iclass 11, count 2 2006.245.08:08:10.55#ibcon#about to read 5, iclass 11, count 2 2006.245.08:08:10.55#ibcon#read 5, iclass 11, count 2 2006.245.08:08:10.55#ibcon#about to read 6, iclass 11, count 2 2006.245.08:08:10.55#ibcon#read 6, iclass 11, count 2 2006.245.08:08:10.55#ibcon#end of sib2, iclass 11, count 2 2006.245.08:08:10.55#ibcon#*after write, iclass 11, count 2 2006.245.08:08:10.55#ibcon#*before return 0, iclass 11, count 2 2006.245.08:08:10.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:10.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:10.55#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:08:10.55#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:10.55#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:10.67#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:10.67#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:10.67#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:08:10.67#ibcon#first serial, iclass 11, count 0 2006.245.08:08:10.67#ibcon#enter sib2, iclass 11, count 0 2006.245.08:08:10.67#ibcon#flushed, iclass 11, count 0 2006.245.08:08:10.67#ibcon#about to write, iclass 11, count 0 2006.245.08:08:10.67#ibcon#wrote, iclass 11, count 0 2006.245.08:08:10.67#ibcon#about to read 3, iclass 11, count 0 2006.245.08:08:10.69#ibcon#read 3, iclass 11, count 0 2006.245.08:08:10.69#ibcon#about to read 4, iclass 11, count 0 2006.245.08:08:10.69#ibcon#read 4, iclass 11, count 0 2006.245.08:08:10.69#ibcon#about to read 5, iclass 11, count 0 2006.245.08:08:10.69#ibcon#read 5, iclass 11, count 0 2006.245.08:08:10.69#ibcon#about to read 6, iclass 11, count 0 2006.245.08:08:10.69#ibcon#read 6, iclass 11, count 0 2006.245.08:08:10.69#ibcon#end of sib2, iclass 11, count 0 2006.245.08:08:10.69#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:08:10.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:08:10.69#ibcon#[25=USB\r\n] 2006.245.08:08:10.69#ibcon#*before write, iclass 11, count 0 2006.245.08:08:10.69#ibcon#enter sib2, iclass 11, count 0 2006.245.08:08:10.69#ibcon#flushed, iclass 11, count 0 2006.245.08:08:10.69#ibcon#about to write, iclass 11, count 0 2006.245.08:08:10.69#ibcon#wrote, iclass 11, count 0 2006.245.08:08:10.69#ibcon#about to read 3, iclass 11, count 0 2006.245.08:08:10.72#ibcon#read 3, iclass 11, count 0 2006.245.08:08:10.72#ibcon#about to read 4, iclass 11, count 0 2006.245.08:08:10.72#ibcon#read 4, iclass 11, count 0 2006.245.08:08:10.72#ibcon#about to read 5, iclass 11, count 0 2006.245.08:08:10.72#ibcon#read 5, iclass 11, count 0 2006.245.08:08:10.72#ibcon#about to read 6, iclass 11, count 0 2006.245.08:08:10.72#ibcon#read 6, iclass 11, count 0 2006.245.08:08:10.72#ibcon#end of sib2, iclass 11, count 0 2006.245.08:08:10.72#ibcon#*after write, iclass 11, count 0 2006.245.08:08:10.72#ibcon#*before return 0, iclass 11, count 0 2006.245.08:08:10.72#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:10.72#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:10.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:08:10.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:08:10.72$vc4f8/valo=3,672.99 2006.245.08:08:10.72#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:08:10.72#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:08:10.72#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:10.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:10.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:10.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:10.72#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:08:10.72#ibcon#first serial, iclass 13, count 0 2006.245.08:08:10.72#ibcon#enter sib2, iclass 13, count 0 2006.245.08:08:10.72#ibcon#flushed, iclass 13, count 0 2006.245.08:08:10.72#ibcon#about to write, iclass 13, count 0 2006.245.08:08:10.72#ibcon#wrote, iclass 13, count 0 2006.245.08:08:10.72#ibcon#about to read 3, iclass 13, count 0 2006.245.08:08:10.74#ibcon#read 3, iclass 13, count 0 2006.245.08:08:10.74#ibcon#about to read 4, iclass 13, count 0 2006.245.08:08:10.74#ibcon#read 4, iclass 13, count 0 2006.245.08:08:10.74#ibcon#about to read 5, iclass 13, count 0 2006.245.08:08:10.74#ibcon#read 5, iclass 13, count 0 2006.245.08:08:10.74#ibcon#about to read 6, iclass 13, count 0 2006.245.08:08:10.74#ibcon#read 6, iclass 13, count 0 2006.245.08:08:10.74#ibcon#end of sib2, iclass 13, count 0 2006.245.08:08:10.74#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:08:10.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:08:10.74#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:08:10.74#ibcon#*before write, iclass 13, count 0 2006.245.08:08:10.74#ibcon#enter sib2, iclass 13, count 0 2006.245.08:08:10.74#ibcon#flushed, iclass 13, count 0 2006.245.08:08:10.74#ibcon#about to write, iclass 13, count 0 2006.245.08:08:10.74#ibcon#wrote, iclass 13, count 0 2006.245.08:08:10.74#ibcon#about to read 3, iclass 13, count 0 2006.245.08:08:10.78#ibcon#read 3, iclass 13, count 0 2006.245.08:08:10.78#ibcon#about to read 4, iclass 13, count 0 2006.245.08:08:10.78#ibcon#read 4, iclass 13, count 0 2006.245.08:08:10.78#ibcon#about to read 5, iclass 13, count 0 2006.245.08:08:10.78#ibcon#read 5, iclass 13, count 0 2006.245.08:08:10.78#ibcon#about to read 6, iclass 13, count 0 2006.245.08:08:10.78#ibcon#read 6, iclass 13, count 0 2006.245.08:08:10.78#ibcon#end of sib2, iclass 13, count 0 2006.245.08:08:10.78#ibcon#*after write, iclass 13, count 0 2006.245.08:08:10.78#ibcon#*before return 0, iclass 13, count 0 2006.245.08:08:10.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:10.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:10.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:08:10.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:08:10.78$vc4f8/va=3,6 2006.245.08:08:10.78#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:08:10.78#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:08:10.78#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:10.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:10.85#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:10.85#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:10.85#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:08:10.85#ibcon#first serial, iclass 15, count 2 2006.245.08:08:10.85#ibcon#enter sib2, iclass 15, count 2 2006.245.08:08:10.85#ibcon#flushed, iclass 15, count 2 2006.245.08:08:10.85#ibcon#about to write, iclass 15, count 2 2006.245.08:08:10.85#ibcon#wrote, iclass 15, count 2 2006.245.08:08:10.85#ibcon#about to read 3, iclass 15, count 2 2006.245.08:08:10.86#ibcon#read 3, iclass 15, count 2 2006.245.08:08:10.86#ibcon#about to read 4, iclass 15, count 2 2006.245.08:08:10.86#ibcon#read 4, iclass 15, count 2 2006.245.08:08:10.86#ibcon#about to read 5, iclass 15, count 2 2006.245.08:08:10.86#ibcon#read 5, iclass 15, count 2 2006.245.08:08:10.86#ibcon#about to read 6, iclass 15, count 2 2006.245.08:08:10.86#ibcon#read 6, iclass 15, count 2 2006.245.08:08:10.86#ibcon#end of sib2, iclass 15, count 2 2006.245.08:08:10.86#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:08:10.86#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:08:10.86#ibcon#[25=AT03-06\r\n] 2006.245.08:08:10.86#ibcon#*before write, iclass 15, count 2 2006.245.08:08:10.86#ibcon#enter sib2, iclass 15, count 2 2006.245.08:08:10.86#ibcon#flushed, iclass 15, count 2 2006.245.08:08:10.86#ibcon#about to write, iclass 15, count 2 2006.245.08:08:10.86#ibcon#wrote, iclass 15, count 2 2006.245.08:08:10.86#ibcon#about to read 3, iclass 15, count 2 2006.245.08:08:10.89#ibcon#read 3, iclass 15, count 2 2006.245.08:08:10.89#ibcon#about to read 4, iclass 15, count 2 2006.245.08:08:10.89#ibcon#read 4, iclass 15, count 2 2006.245.08:08:10.89#ibcon#about to read 5, iclass 15, count 2 2006.245.08:08:10.89#ibcon#read 5, iclass 15, count 2 2006.245.08:08:10.89#ibcon#about to read 6, iclass 15, count 2 2006.245.08:08:10.89#ibcon#read 6, iclass 15, count 2 2006.245.08:08:10.89#ibcon#end of sib2, iclass 15, count 2 2006.245.08:08:10.89#ibcon#*after write, iclass 15, count 2 2006.245.08:08:10.89#ibcon#*before return 0, iclass 15, count 2 2006.245.08:08:10.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:10.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:10.89#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:08:10.89#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:10.89#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:11.01#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:11.01#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:11.01#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:08:11.01#ibcon#first serial, iclass 15, count 0 2006.245.08:08:11.01#ibcon#enter sib2, iclass 15, count 0 2006.245.08:08:11.01#ibcon#flushed, iclass 15, count 0 2006.245.08:08:11.01#ibcon#about to write, iclass 15, count 0 2006.245.08:08:11.01#ibcon#wrote, iclass 15, count 0 2006.245.08:08:11.01#ibcon#about to read 3, iclass 15, count 0 2006.245.08:08:11.03#ibcon#read 3, iclass 15, count 0 2006.245.08:08:11.03#ibcon#about to read 4, iclass 15, count 0 2006.245.08:08:11.03#ibcon#read 4, iclass 15, count 0 2006.245.08:08:11.03#ibcon#about to read 5, iclass 15, count 0 2006.245.08:08:11.03#ibcon#read 5, iclass 15, count 0 2006.245.08:08:11.03#ibcon#about to read 6, iclass 15, count 0 2006.245.08:08:11.03#ibcon#read 6, iclass 15, count 0 2006.245.08:08:11.03#ibcon#end of sib2, iclass 15, count 0 2006.245.08:08:11.03#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:08:11.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:08:11.03#ibcon#[25=USB\r\n] 2006.245.08:08:11.03#ibcon#*before write, iclass 15, count 0 2006.245.08:08:11.03#ibcon#enter sib2, iclass 15, count 0 2006.245.08:08:11.03#ibcon#flushed, iclass 15, count 0 2006.245.08:08:11.03#ibcon#about to write, iclass 15, count 0 2006.245.08:08:11.03#ibcon#wrote, iclass 15, count 0 2006.245.08:08:11.03#ibcon#about to read 3, iclass 15, count 0 2006.245.08:08:11.06#ibcon#read 3, iclass 15, count 0 2006.245.08:08:11.06#ibcon#about to read 4, iclass 15, count 0 2006.245.08:08:11.06#ibcon#read 4, iclass 15, count 0 2006.245.08:08:11.06#ibcon#about to read 5, iclass 15, count 0 2006.245.08:08:11.06#ibcon#read 5, iclass 15, count 0 2006.245.08:08:11.06#ibcon#about to read 6, iclass 15, count 0 2006.245.08:08:11.06#ibcon#read 6, iclass 15, count 0 2006.245.08:08:11.06#ibcon#end of sib2, iclass 15, count 0 2006.245.08:08:11.06#ibcon#*after write, iclass 15, count 0 2006.245.08:08:11.06#ibcon#*before return 0, iclass 15, count 0 2006.245.08:08:11.06#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:11.06#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:11.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:08:11.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:08:11.06$vc4f8/valo=4,832.99 2006.245.08:08:11.06#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:08:11.06#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:08:11.06#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:11.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:11.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:11.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:11.06#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:08:11.06#ibcon#first serial, iclass 17, count 0 2006.245.08:08:11.06#ibcon#enter sib2, iclass 17, count 0 2006.245.08:08:11.06#ibcon#flushed, iclass 17, count 0 2006.245.08:08:11.06#ibcon#about to write, iclass 17, count 0 2006.245.08:08:11.06#ibcon#wrote, iclass 17, count 0 2006.245.08:08:11.06#ibcon#about to read 3, iclass 17, count 0 2006.245.08:08:11.09#ibcon#read 3, iclass 17, count 0 2006.245.08:08:11.09#ibcon#about to read 4, iclass 17, count 0 2006.245.08:08:11.09#ibcon#read 4, iclass 17, count 0 2006.245.08:08:11.09#ibcon#about to read 5, iclass 17, count 0 2006.245.08:08:11.09#ibcon#read 5, iclass 17, count 0 2006.245.08:08:11.09#ibcon#about to read 6, iclass 17, count 0 2006.245.08:08:11.09#ibcon#read 6, iclass 17, count 0 2006.245.08:08:11.09#ibcon#end of sib2, iclass 17, count 0 2006.245.08:08:11.09#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:08:11.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:08:11.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:08:11.09#ibcon#*before write, iclass 17, count 0 2006.245.08:08:11.09#ibcon#enter sib2, iclass 17, count 0 2006.245.08:08:11.09#ibcon#flushed, iclass 17, count 0 2006.245.08:08:11.09#ibcon#about to write, iclass 17, count 0 2006.245.08:08:11.09#ibcon#wrote, iclass 17, count 0 2006.245.08:08:11.09#ibcon#about to read 3, iclass 17, count 0 2006.245.08:08:11.13#ibcon#read 3, iclass 17, count 0 2006.245.08:08:11.13#ibcon#about to read 4, iclass 17, count 0 2006.245.08:08:11.13#ibcon#read 4, iclass 17, count 0 2006.245.08:08:11.13#ibcon#about to read 5, iclass 17, count 0 2006.245.08:08:11.13#ibcon#read 5, iclass 17, count 0 2006.245.08:08:11.13#ibcon#about to read 6, iclass 17, count 0 2006.245.08:08:11.13#ibcon#read 6, iclass 17, count 0 2006.245.08:08:11.13#ibcon#end of sib2, iclass 17, count 0 2006.245.08:08:11.13#ibcon#*after write, iclass 17, count 0 2006.245.08:08:11.13#ibcon#*before return 0, iclass 17, count 0 2006.245.08:08:11.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:11.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:11.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:08:11.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:08:11.13$vc4f8/va=4,7 2006.245.08:08:11.13#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:08:11.13#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:08:11.13#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:11.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:11.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:11.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:11.18#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:08:11.18#ibcon#first serial, iclass 19, count 2 2006.245.08:08:11.18#ibcon#enter sib2, iclass 19, count 2 2006.245.08:08:11.18#ibcon#flushed, iclass 19, count 2 2006.245.08:08:11.18#ibcon#about to write, iclass 19, count 2 2006.245.08:08:11.18#ibcon#wrote, iclass 19, count 2 2006.245.08:08:11.18#ibcon#about to read 3, iclass 19, count 2 2006.245.08:08:11.20#ibcon#read 3, iclass 19, count 2 2006.245.08:08:11.20#ibcon#about to read 4, iclass 19, count 2 2006.245.08:08:11.20#ibcon#read 4, iclass 19, count 2 2006.245.08:08:11.20#ibcon#about to read 5, iclass 19, count 2 2006.245.08:08:11.20#ibcon#read 5, iclass 19, count 2 2006.245.08:08:11.20#ibcon#about to read 6, iclass 19, count 2 2006.245.08:08:11.20#ibcon#read 6, iclass 19, count 2 2006.245.08:08:11.20#ibcon#end of sib2, iclass 19, count 2 2006.245.08:08:11.20#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:08:11.20#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:08:11.20#ibcon#[25=AT04-07\r\n] 2006.245.08:08:11.20#ibcon#*before write, iclass 19, count 2 2006.245.08:08:11.20#ibcon#enter sib2, iclass 19, count 2 2006.245.08:08:11.20#ibcon#flushed, iclass 19, count 2 2006.245.08:08:11.20#ibcon#about to write, iclass 19, count 2 2006.245.08:08:11.20#ibcon#wrote, iclass 19, count 2 2006.245.08:08:11.20#ibcon#about to read 3, iclass 19, count 2 2006.245.08:08:11.23#ibcon#read 3, iclass 19, count 2 2006.245.08:08:11.23#ibcon#about to read 4, iclass 19, count 2 2006.245.08:08:11.23#ibcon#read 4, iclass 19, count 2 2006.245.08:08:11.23#ibcon#about to read 5, iclass 19, count 2 2006.245.08:08:11.23#ibcon#read 5, iclass 19, count 2 2006.245.08:08:11.23#ibcon#about to read 6, iclass 19, count 2 2006.245.08:08:11.23#ibcon#read 6, iclass 19, count 2 2006.245.08:08:11.23#ibcon#end of sib2, iclass 19, count 2 2006.245.08:08:11.23#ibcon#*after write, iclass 19, count 2 2006.245.08:08:11.23#ibcon#*before return 0, iclass 19, count 2 2006.245.08:08:11.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:11.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:11.23#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:08:11.23#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:11.23#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:11.35#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:11.35#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:11.35#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:08:11.35#ibcon#first serial, iclass 19, count 0 2006.245.08:08:11.35#ibcon#enter sib2, iclass 19, count 0 2006.245.08:08:11.35#ibcon#flushed, iclass 19, count 0 2006.245.08:08:11.35#ibcon#about to write, iclass 19, count 0 2006.245.08:08:11.35#ibcon#wrote, iclass 19, count 0 2006.245.08:08:11.35#ibcon#about to read 3, iclass 19, count 0 2006.245.08:08:11.37#ibcon#read 3, iclass 19, count 0 2006.245.08:08:11.37#ibcon#about to read 4, iclass 19, count 0 2006.245.08:08:11.37#ibcon#read 4, iclass 19, count 0 2006.245.08:08:11.37#ibcon#about to read 5, iclass 19, count 0 2006.245.08:08:11.37#ibcon#read 5, iclass 19, count 0 2006.245.08:08:11.37#ibcon#about to read 6, iclass 19, count 0 2006.245.08:08:11.37#ibcon#read 6, iclass 19, count 0 2006.245.08:08:11.37#ibcon#end of sib2, iclass 19, count 0 2006.245.08:08:11.37#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:08:11.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:08:11.37#ibcon#[25=USB\r\n] 2006.245.08:08:11.37#ibcon#*before write, iclass 19, count 0 2006.245.08:08:11.37#ibcon#enter sib2, iclass 19, count 0 2006.245.08:08:11.37#ibcon#flushed, iclass 19, count 0 2006.245.08:08:11.37#ibcon#about to write, iclass 19, count 0 2006.245.08:08:11.37#ibcon#wrote, iclass 19, count 0 2006.245.08:08:11.37#ibcon#about to read 3, iclass 19, count 0 2006.245.08:08:11.40#ibcon#read 3, iclass 19, count 0 2006.245.08:08:11.40#ibcon#about to read 4, iclass 19, count 0 2006.245.08:08:11.40#ibcon#read 4, iclass 19, count 0 2006.245.08:08:11.40#ibcon#about to read 5, iclass 19, count 0 2006.245.08:08:11.40#ibcon#read 5, iclass 19, count 0 2006.245.08:08:11.40#ibcon#about to read 6, iclass 19, count 0 2006.245.08:08:11.40#ibcon#read 6, iclass 19, count 0 2006.245.08:08:11.40#ibcon#end of sib2, iclass 19, count 0 2006.245.08:08:11.40#ibcon#*after write, iclass 19, count 0 2006.245.08:08:11.40#ibcon#*before return 0, iclass 19, count 0 2006.245.08:08:11.40#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:11.40#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:11.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:08:11.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:08:11.40$vc4f8/valo=5,652.99 2006.245.08:08:11.40#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:08:11.40#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:08:11.40#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:11.40#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:08:11.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:08:11.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:08:11.40#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:08:11.40#ibcon#first serial, iclass 21, count 0 2006.245.08:08:11.40#ibcon#enter sib2, iclass 21, count 0 2006.245.08:08:11.40#ibcon#flushed, iclass 21, count 0 2006.245.08:08:11.40#ibcon#about to write, iclass 21, count 0 2006.245.08:08:11.40#ibcon#wrote, iclass 21, count 0 2006.245.08:08:11.40#ibcon#about to read 3, iclass 21, count 0 2006.245.08:08:11.42#ibcon#read 3, iclass 21, count 0 2006.245.08:08:11.42#ibcon#about to read 4, iclass 21, count 0 2006.245.08:08:11.42#ibcon#read 4, iclass 21, count 0 2006.245.08:08:11.42#ibcon#about to read 5, iclass 21, count 0 2006.245.08:08:11.42#ibcon#read 5, iclass 21, count 0 2006.245.08:08:11.42#ibcon#about to read 6, iclass 21, count 0 2006.245.08:08:11.42#ibcon#read 6, iclass 21, count 0 2006.245.08:08:11.42#ibcon#end of sib2, iclass 21, count 0 2006.245.08:08:11.42#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:08:11.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:08:11.42#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:08:11.42#ibcon#*before write, iclass 21, count 0 2006.245.08:08:11.42#ibcon#enter sib2, iclass 21, count 0 2006.245.08:08:11.42#ibcon#flushed, iclass 21, count 0 2006.245.08:08:11.42#ibcon#about to write, iclass 21, count 0 2006.245.08:08:11.42#ibcon#wrote, iclass 21, count 0 2006.245.08:08:11.42#ibcon#about to read 3, iclass 21, count 0 2006.245.08:08:11.46#ibcon#read 3, iclass 21, count 0 2006.245.08:08:11.46#ibcon#about to read 4, iclass 21, count 0 2006.245.08:08:11.46#ibcon#read 4, iclass 21, count 0 2006.245.08:08:11.46#ibcon#about to read 5, iclass 21, count 0 2006.245.08:08:11.46#ibcon#read 5, iclass 21, count 0 2006.245.08:08:11.46#ibcon#about to read 6, iclass 21, count 0 2006.245.08:08:11.46#ibcon#read 6, iclass 21, count 0 2006.245.08:08:11.46#ibcon#end of sib2, iclass 21, count 0 2006.245.08:08:11.46#ibcon#*after write, iclass 21, count 0 2006.245.08:08:11.46#ibcon#*before return 0, iclass 21, count 0 2006.245.08:08:11.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:08:11.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:08:11.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:08:11.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:08:11.46$vc4f8/va=5,7 2006.245.08:08:11.46#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.08:08:11.46#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.08:08:11.46#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:11.46#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:08:11.53#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:08:11.53#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:08:11.53#ibcon#enter wrdev, iclass 23, count 2 2006.245.08:08:11.53#ibcon#first serial, iclass 23, count 2 2006.245.08:08:11.53#ibcon#enter sib2, iclass 23, count 2 2006.245.08:08:11.53#ibcon#flushed, iclass 23, count 2 2006.245.08:08:11.53#ibcon#about to write, iclass 23, count 2 2006.245.08:08:11.53#ibcon#wrote, iclass 23, count 2 2006.245.08:08:11.53#ibcon#about to read 3, iclass 23, count 2 2006.245.08:08:11.54#ibcon#read 3, iclass 23, count 2 2006.245.08:08:11.54#ibcon#about to read 4, iclass 23, count 2 2006.245.08:08:11.54#ibcon#read 4, iclass 23, count 2 2006.245.08:08:11.54#ibcon#about to read 5, iclass 23, count 2 2006.245.08:08:11.54#ibcon#read 5, iclass 23, count 2 2006.245.08:08:11.54#ibcon#about to read 6, iclass 23, count 2 2006.245.08:08:11.54#ibcon#read 6, iclass 23, count 2 2006.245.08:08:11.54#ibcon#end of sib2, iclass 23, count 2 2006.245.08:08:11.54#ibcon#*mode == 0, iclass 23, count 2 2006.245.08:08:11.54#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.08:08:11.54#ibcon#[25=AT05-07\r\n] 2006.245.08:08:11.54#ibcon#*before write, iclass 23, count 2 2006.245.08:08:11.54#ibcon#enter sib2, iclass 23, count 2 2006.245.08:08:11.54#ibcon#flushed, iclass 23, count 2 2006.245.08:08:11.54#ibcon#about to write, iclass 23, count 2 2006.245.08:08:11.54#ibcon#wrote, iclass 23, count 2 2006.245.08:08:11.54#ibcon#about to read 3, iclass 23, count 2 2006.245.08:08:11.57#ibcon#read 3, iclass 23, count 2 2006.245.08:08:11.57#ibcon#about to read 4, iclass 23, count 2 2006.245.08:08:11.57#ibcon#read 4, iclass 23, count 2 2006.245.08:08:11.57#ibcon#about to read 5, iclass 23, count 2 2006.245.08:08:11.57#ibcon#read 5, iclass 23, count 2 2006.245.08:08:11.57#ibcon#about to read 6, iclass 23, count 2 2006.245.08:08:11.57#ibcon#read 6, iclass 23, count 2 2006.245.08:08:11.57#ibcon#end of sib2, iclass 23, count 2 2006.245.08:08:11.57#ibcon#*after write, iclass 23, count 2 2006.245.08:08:11.57#ibcon#*before return 0, iclass 23, count 2 2006.245.08:08:11.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:08:11.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:08:11.57#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.08:08:11.57#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:11.57#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:08:11.69#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:08:11.69#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:08:11.69#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:08:11.69#ibcon#first serial, iclass 23, count 0 2006.245.08:08:11.69#ibcon#enter sib2, iclass 23, count 0 2006.245.08:08:11.69#ibcon#flushed, iclass 23, count 0 2006.245.08:08:11.69#ibcon#about to write, iclass 23, count 0 2006.245.08:08:11.69#ibcon#wrote, iclass 23, count 0 2006.245.08:08:11.69#ibcon#about to read 3, iclass 23, count 0 2006.245.08:08:11.71#ibcon#read 3, iclass 23, count 0 2006.245.08:08:11.71#ibcon#about to read 4, iclass 23, count 0 2006.245.08:08:11.71#ibcon#read 4, iclass 23, count 0 2006.245.08:08:11.71#ibcon#about to read 5, iclass 23, count 0 2006.245.08:08:11.71#ibcon#read 5, iclass 23, count 0 2006.245.08:08:11.71#ibcon#about to read 6, iclass 23, count 0 2006.245.08:08:11.71#ibcon#read 6, iclass 23, count 0 2006.245.08:08:11.71#ibcon#end of sib2, iclass 23, count 0 2006.245.08:08:11.71#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:08:11.71#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:08:11.71#ibcon#[25=USB\r\n] 2006.245.08:08:11.71#ibcon#*before write, iclass 23, count 0 2006.245.08:08:11.71#ibcon#enter sib2, iclass 23, count 0 2006.245.08:08:11.71#ibcon#flushed, iclass 23, count 0 2006.245.08:08:11.71#ibcon#about to write, iclass 23, count 0 2006.245.08:08:11.71#ibcon#wrote, iclass 23, count 0 2006.245.08:08:11.71#ibcon#about to read 3, iclass 23, count 0 2006.245.08:08:11.74#ibcon#read 3, iclass 23, count 0 2006.245.08:08:11.74#ibcon#about to read 4, iclass 23, count 0 2006.245.08:08:11.74#ibcon#read 4, iclass 23, count 0 2006.245.08:08:11.74#ibcon#about to read 5, iclass 23, count 0 2006.245.08:08:11.74#ibcon#read 5, iclass 23, count 0 2006.245.08:08:11.74#ibcon#about to read 6, iclass 23, count 0 2006.245.08:08:11.74#ibcon#read 6, iclass 23, count 0 2006.245.08:08:11.74#ibcon#end of sib2, iclass 23, count 0 2006.245.08:08:11.74#ibcon#*after write, iclass 23, count 0 2006.245.08:08:11.74#ibcon#*before return 0, iclass 23, count 0 2006.245.08:08:11.74#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:08:11.74#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:08:11.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:08:11.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:08:11.74$vc4f8/valo=6,772.99 2006.245.08:08:11.74#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.08:08:11.74#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.08:08:11.74#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:11.74#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:08:11.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:08:11.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:08:11.74#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:08:11.74#ibcon#first serial, iclass 25, count 0 2006.245.08:08:11.74#ibcon#enter sib2, iclass 25, count 0 2006.245.08:08:11.74#ibcon#flushed, iclass 25, count 0 2006.245.08:08:11.74#ibcon#about to write, iclass 25, count 0 2006.245.08:08:11.74#ibcon#wrote, iclass 25, count 0 2006.245.08:08:11.74#ibcon#about to read 3, iclass 25, count 0 2006.245.08:08:11.76#ibcon#read 3, iclass 25, count 0 2006.245.08:08:11.76#ibcon#about to read 4, iclass 25, count 0 2006.245.08:08:11.76#ibcon#read 4, iclass 25, count 0 2006.245.08:08:11.76#ibcon#about to read 5, iclass 25, count 0 2006.245.08:08:11.76#ibcon#read 5, iclass 25, count 0 2006.245.08:08:11.76#ibcon#about to read 6, iclass 25, count 0 2006.245.08:08:11.76#ibcon#read 6, iclass 25, count 0 2006.245.08:08:11.76#ibcon#end of sib2, iclass 25, count 0 2006.245.08:08:11.76#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:08:11.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:08:11.76#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:08:11.76#ibcon#*before write, iclass 25, count 0 2006.245.08:08:11.76#ibcon#enter sib2, iclass 25, count 0 2006.245.08:08:11.76#ibcon#flushed, iclass 25, count 0 2006.245.08:08:11.76#ibcon#about to write, iclass 25, count 0 2006.245.08:08:11.76#ibcon#wrote, iclass 25, count 0 2006.245.08:08:11.76#ibcon#about to read 3, iclass 25, count 0 2006.245.08:08:11.80#ibcon#read 3, iclass 25, count 0 2006.245.08:08:11.80#ibcon#about to read 4, iclass 25, count 0 2006.245.08:08:11.80#ibcon#read 4, iclass 25, count 0 2006.245.08:08:11.80#ibcon#about to read 5, iclass 25, count 0 2006.245.08:08:11.80#ibcon#read 5, iclass 25, count 0 2006.245.08:08:11.80#ibcon#about to read 6, iclass 25, count 0 2006.245.08:08:11.80#ibcon#read 6, iclass 25, count 0 2006.245.08:08:11.80#ibcon#end of sib2, iclass 25, count 0 2006.245.08:08:11.80#ibcon#*after write, iclass 25, count 0 2006.245.08:08:11.80#ibcon#*before return 0, iclass 25, count 0 2006.245.08:08:11.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:08:11.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:08:11.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:08:11.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:08:11.80$vc4f8/va=6,7 2006.245.08:08:11.80#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.08:08:11.80#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.08:08:11.80#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:11.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:11.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:11.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:11.87#ibcon#enter wrdev, iclass 27, count 2 2006.245.08:08:11.87#ibcon#first serial, iclass 27, count 2 2006.245.08:08:11.87#ibcon#enter sib2, iclass 27, count 2 2006.245.08:08:11.87#ibcon#flushed, iclass 27, count 2 2006.245.08:08:11.87#ibcon#about to write, iclass 27, count 2 2006.245.08:08:11.87#ibcon#wrote, iclass 27, count 2 2006.245.08:08:11.87#ibcon#about to read 3, iclass 27, count 2 2006.245.08:08:11.88#ibcon#read 3, iclass 27, count 2 2006.245.08:08:11.88#ibcon#about to read 4, iclass 27, count 2 2006.245.08:08:11.88#ibcon#read 4, iclass 27, count 2 2006.245.08:08:11.88#ibcon#about to read 5, iclass 27, count 2 2006.245.08:08:11.88#ibcon#read 5, iclass 27, count 2 2006.245.08:08:11.88#ibcon#about to read 6, iclass 27, count 2 2006.245.08:08:11.88#ibcon#read 6, iclass 27, count 2 2006.245.08:08:11.88#ibcon#end of sib2, iclass 27, count 2 2006.245.08:08:11.88#ibcon#*mode == 0, iclass 27, count 2 2006.245.08:08:11.88#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.08:08:11.88#ibcon#[25=AT06-07\r\n] 2006.245.08:08:11.88#ibcon#*before write, iclass 27, count 2 2006.245.08:08:11.88#ibcon#enter sib2, iclass 27, count 2 2006.245.08:08:11.88#ibcon#flushed, iclass 27, count 2 2006.245.08:08:11.88#ibcon#about to write, iclass 27, count 2 2006.245.08:08:11.88#ibcon#wrote, iclass 27, count 2 2006.245.08:08:11.88#ibcon#about to read 3, iclass 27, count 2 2006.245.08:08:11.91#ibcon#read 3, iclass 27, count 2 2006.245.08:08:11.91#ibcon#about to read 4, iclass 27, count 2 2006.245.08:08:11.91#ibcon#read 4, iclass 27, count 2 2006.245.08:08:11.91#ibcon#about to read 5, iclass 27, count 2 2006.245.08:08:11.91#ibcon#read 5, iclass 27, count 2 2006.245.08:08:11.91#ibcon#about to read 6, iclass 27, count 2 2006.245.08:08:11.91#ibcon#read 6, iclass 27, count 2 2006.245.08:08:11.91#ibcon#end of sib2, iclass 27, count 2 2006.245.08:08:11.91#ibcon#*after write, iclass 27, count 2 2006.245.08:08:11.91#ibcon#*before return 0, iclass 27, count 2 2006.245.08:08:11.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:11.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:11.91#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.08:08:11.91#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:11.91#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:12.03#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:12.03#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:12.03#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:08:12.03#ibcon#first serial, iclass 27, count 0 2006.245.08:08:12.03#ibcon#enter sib2, iclass 27, count 0 2006.245.08:08:12.03#ibcon#flushed, iclass 27, count 0 2006.245.08:08:12.03#ibcon#about to write, iclass 27, count 0 2006.245.08:08:12.03#ibcon#wrote, iclass 27, count 0 2006.245.08:08:12.03#ibcon#about to read 3, iclass 27, count 0 2006.245.08:08:12.05#ibcon#read 3, iclass 27, count 0 2006.245.08:08:12.05#ibcon#about to read 4, iclass 27, count 0 2006.245.08:08:12.05#ibcon#read 4, iclass 27, count 0 2006.245.08:08:12.05#ibcon#about to read 5, iclass 27, count 0 2006.245.08:08:12.05#ibcon#read 5, iclass 27, count 0 2006.245.08:08:12.05#ibcon#about to read 6, iclass 27, count 0 2006.245.08:08:12.05#ibcon#read 6, iclass 27, count 0 2006.245.08:08:12.05#ibcon#end of sib2, iclass 27, count 0 2006.245.08:08:12.05#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:08:12.05#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:08:12.05#ibcon#[25=USB\r\n] 2006.245.08:08:12.05#ibcon#*before write, iclass 27, count 0 2006.245.08:08:12.05#ibcon#enter sib2, iclass 27, count 0 2006.245.08:08:12.05#ibcon#flushed, iclass 27, count 0 2006.245.08:08:12.05#ibcon#about to write, iclass 27, count 0 2006.245.08:08:12.05#ibcon#wrote, iclass 27, count 0 2006.245.08:08:12.05#ibcon#about to read 3, iclass 27, count 0 2006.245.08:08:12.08#ibcon#read 3, iclass 27, count 0 2006.245.08:08:12.08#ibcon#about to read 4, iclass 27, count 0 2006.245.08:08:12.08#ibcon#read 4, iclass 27, count 0 2006.245.08:08:12.08#ibcon#about to read 5, iclass 27, count 0 2006.245.08:08:12.08#ibcon#read 5, iclass 27, count 0 2006.245.08:08:12.08#ibcon#about to read 6, iclass 27, count 0 2006.245.08:08:12.08#ibcon#read 6, iclass 27, count 0 2006.245.08:08:12.08#ibcon#end of sib2, iclass 27, count 0 2006.245.08:08:12.08#ibcon#*after write, iclass 27, count 0 2006.245.08:08:12.08#ibcon#*before return 0, iclass 27, count 0 2006.245.08:08:12.08#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:12.08#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:12.08#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:08:12.08#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:08:12.08$vc4f8/valo=7,832.99 2006.245.08:08:12.08#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.08:08:12.08#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.08:08:12.08#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:12.08#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:12.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:12.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:12.08#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:08:12.08#ibcon#first serial, iclass 29, count 0 2006.245.08:08:12.08#ibcon#enter sib2, iclass 29, count 0 2006.245.08:08:12.08#ibcon#flushed, iclass 29, count 0 2006.245.08:08:12.08#ibcon#about to write, iclass 29, count 0 2006.245.08:08:12.08#ibcon#wrote, iclass 29, count 0 2006.245.08:08:12.08#ibcon#about to read 3, iclass 29, count 0 2006.245.08:08:12.10#ibcon#read 3, iclass 29, count 0 2006.245.08:08:12.10#ibcon#about to read 4, iclass 29, count 0 2006.245.08:08:12.10#ibcon#read 4, iclass 29, count 0 2006.245.08:08:12.10#ibcon#about to read 5, iclass 29, count 0 2006.245.08:08:12.10#ibcon#read 5, iclass 29, count 0 2006.245.08:08:12.10#ibcon#about to read 6, iclass 29, count 0 2006.245.08:08:12.10#ibcon#read 6, iclass 29, count 0 2006.245.08:08:12.10#ibcon#end of sib2, iclass 29, count 0 2006.245.08:08:12.10#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:08:12.10#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:08:12.10#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:08:12.10#ibcon#*before write, iclass 29, count 0 2006.245.08:08:12.10#ibcon#enter sib2, iclass 29, count 0 2006.245.08:08:12.10#ibcon#flushed, iclass 29, count 0 2006.245.08:08:12.10#ibcon#about to write, iclass 29, count 0 2006.245.08:08:12.10#ibcon#wrote, iclass 29, count 0 2006.245.08:08:12.10#ibcon#about to read 3, iclass 29, count 0 2006.245.08:08:12.14#ibcon#read 3, iclass 29, count 0 2006.245.08:08:12.14#ibcon#about to read 4, iclass 29, count 0 2006.245.08:08:12.14#ibcon#read 4, iclass 29, count 0 2006.245.08:08:12.14#ibcon#about to read 5, iclass 29, count 0 2006.245.08:08:12.14#ibcon#read 5, iclass 29, count 0 2006.245.08:08:12.14#ibcon#about to read 6, iclass 29, count 0 2006.245.08:08:12.14#ibcon#read 6, iclass 29, count 0 2006.245.08:08:12.14#ibcon#end of sib2, iclass 29, count 0 2006.245.08:08:12.14#ibcon#*after write, iclass 29, count 0 2006.245.08:08:12.14#ibcon#*before return 0, iclass 29, count 0 2006.245.08:08:12.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:12.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:12.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:08:12.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:08:12.14$vc4f8/va=7,7 2006.245.08:08:12.14#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.08:08:12.14#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.08:08:12.14#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:12.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:08:12.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:08:12.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:08:12.20#ibcon#enter wrdev, iclass 31, count 2 2006.245.08:08:12.20#ibcon#first serial, iclass 31, count 2 2006.245.08:08:12.20#ibcon#enter sib2, iclass 31, count 2 2006.245.08:08:12.20#ibcon#flushed, iclass 31, count 2 2006.245.08:08:12.20#ibcon#about to write, iclass 31, count 2 2006.245.08:08:12.20#ibcon#wrote, iclass 31, count 2 2006.245.08:08:12.20#ibcon#about to read 3, iclass 31, count 2 2006.245.08:08:12.22#ibcon#read 3, iclass 31, count 2 2006.245.08:08:12.22#ibcon#about to read 4, iclass 31, count 2 2006.245.08:08:12.22#ibcon#read 4, iclass 31, count 2 2006.245.08:08:12.22#ibcon#about to read 5, iclass 31, count 2 2006.245.08:08:12.22#ibcon#read 5, iclass 31, count 2 2006.245.08:08:12.22#ibcon#about to read 6, iclass 31, count 2 2006.245.08:08:12.22#ibcon#read 6, iclass 31, count 2 2006.245.08:08:12.22#ibcon#end of sib2, iclass 31, count 2 2006.245.08:08:12.22#ibcon#*mode == 0, iclass 31, count 2 2006.245.08:08:12.22#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.08:08:12.22#ibcon#[25=AT07-07\r\n] 2006.245.08:08:12.22#ibcon#*before write, iclass 31, count 2 2006.245.08:08:12.22#ibcon#enter sib2, iclass 31, count 2 2006.245.08:08:12.22#ibcon#flushed, iclass 31, count 2 2006.245.08:08:12.22#ibcon#about to write, iclass 31, count 2 2006.245.08:08:12.22#ibcon#wrote, iclass 31, count 2 2006.245.08:08:12.22#ibcon#about to read 3, iclass 31, count 2 2006.245.08:08:12.25#ibcon#read 3, iclass 31, count 2 2006.245.08:08:12.25#ibcon#about to read 4, iclass 31, count 2 2006.245.08:08:12.25#ibcon#read 4, iclass 31, count 2 2006.245.08:08:12.25#ibcon#about to read 5, iclass 31, count 2 2006.245.08:08:12.25#ibcon#read 5, iclass 31, count 2 2006.245.08:08:12.25#ibcon#about to read 6, iclass 31, count 2 2006.245.08:08:12.25#ibcon#read 6, iclass 31, count 2 2006.245.08:08:12.25#ibcon#end of sib2, iclass 31, count 2 2006.245.08:08:12.25#ibcon#*after write, iclass 31, count 2 2006.245.08:08:12.25#ibcon#*before return 0, iclass 31, count 2 2006.245.08:08:12.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:08:12.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:08:12.25#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.08:08:12.25#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:12.25#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:08:12.37#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:08:12.37#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:08:12.37#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:08:12.37#ibcon#first serial, iclass 31, count 0 2006.245.08:08:12.37#ibcon#enter sib2, iclass 31, count 0 2006.245.08:08:12.37#ibcon#flushed, iclass 31, count 0 2006.245.08:08:12.37#ibcon#about to write, iclass 31, count 0 2006.245.08:08:12.37#ibcon#wrote, iclass 31, count 0 2006.245.08:08:12.37#ibcon#about to read 3, iclass 31, count 0 2006.245.08:08:12.39#ibcon#read 3, iclass 31, count 0 2006.245.08:08:12.39#ibcon#about to read 4, iclass 31, count 0 2006.245.08:08:12.39#ibcon#read 4, iclass 31, count 0 2006.245.08:08:12.39#ibcon#about to read 5, iclass 31, count 0 2006.245.08:08:12.39#ibcon#read 5, iclass 31, count 0 2006.245.08:08:12.39#ibcon#about to read 6, iclass 31, count 0 2006.245.08:08:12.39#ibcon#read 6, iclass 31, count 0 2006.245.08:08:12.39#ibcon#end of sib2, iclass 31, count 0 2006.245.08:08:12.39#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:08:12.39#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:08:12.39#ibcon#[25=USB\r\n] 2006.245.08:08:12.39#ibcon#*before write, iclass 31, count 0 2006.245.08:08:12.39#ibcon#enter sib2, iclass 31, count 0 2006.245.08:08:12.39#ibcon#flushed, iclass 31, count 0 2006.245.08:08:12.39#ibcon#about to write, iclass 31, count 0 2006.245.08:08:12.39#ibcon#wrote, iclass 31, count 0 2006.245.08:08:12.39#ibcon#about to read 3, iclass 31, count 0 2006.245.08:08:12.42#ibcon#read 3, iclass 31, count 0 2006.245.08:08:12.42#ibcon#about to read 4, iclass 31, count 0 2006.245.08:08:12.42#ibcon#read 4, iclass 31, count 0 2006.245.08:08:12.42#ibcon#about to read 5, iclass 31, count 0 2006.245.08:08:12.42#ibcon#read 5, iclass 31, count 0 2006.245.08:08:12.42#ibcon#about to read 6, iclass 31, count 0 2006.245.08:08:12.42#ibcon#read 6, iclass 31, count 0 2006.245.08:08:12.42#ibcon#end of sib2, iclass 31, count 0 2006.245.08:08:12.42#ibcon#*after write, iclass 31, count 0 2006.245.08:08:12.42#ibcon#*before return 0, iclass 31, count 0 2006.245.08:08:12.42#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:08:12.42#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:08:12.42#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:08:12.42#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:08:12.42$vc4f8/valo=8,852.99 2006.245.08:08:12.42#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:08:12.42#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:08:12.42#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:12.42#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:08:12.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:08:12.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:08:12.42#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:08:12.42#ibcon#first serial, iclass 33, count 0 2006.245.08:08:12.42#ibcon#enter sib2, iclass 33, count 0 2006.245.08:08:12.42#ibcon#flushed, iclass 33, count 0 2006.245.08:08:12.42#ibcon#about to write, iclass 33, count 0 2006.245.08:08:12.42#ibcon#wrote, iclass 33, count 0 2006.245.08:08:12.42#ibcon#about to read 3, iclass 33, count 0 2006.245.08:08:12.45#ibcon#read 3, iclass 33, count 0 2006.245.08:08:12.45#ibcon#about to read 4, iclass 33, count 0 2006.245.08:08:12.45#ibcon#read 4, iclass 33, count 0 2006.245.08:08:12.45#ibcon#about to read 5, iclass 33, count 0 2006.245.08:08:12.45#ibcon#read 5, iclass 33, count 0 2006.245.08:08:12.45#ibcon#about to read 6, iclass 33, count 0 2006.245.08:08:12.45#ibcon#read 6, iclass 33, count 0 2006.245.08:08:12.45#ibcon#end of sib2, iclass 33, count 0 2006.245.08:08:12.45#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:08:12.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:08:12.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:08:12.45#ibcon#*before write, iclass 33, count 0 2006.245.08:08:12.45#ibcon#enter sib2, iclass 33, count 0 2006.245.08:08:12.45#ibcon#flushed, iclass 33, count 0 2006.245.08:08:12.45#ibcon#about to write, iclass 33, count 0 2006.245.08:08:12.45#ibcon#wrote, iclass 33, count 0 2006.245.08:08:12.45#ibcon#about to read 3, iclass 33, count 0 2006.245.08:08:12.49#ibcon#read 3, iclass 33, count 0 2006.245.08:08:12.49#ibcon#about to read 4, iclass 33, count 0 2006.245.08:08:12.49#ibcon#read 4, iclass 33, count 0 2006.245.08:08:12.49#ibcon#about to read 5, iclass 33, count 0 2006.245.08:08:12.49#ibcon#read 5, iclass 33, count 0 2006.245.08:08:12.49#ibcon#about to read 6, iclass 33, count 0 2006.245.08:08:12.49#ibcon#read 6, iclass 33, count 0 2006.245.08:08:12.49#ibcon#end of sib2, iclass 33, count 0 2006.245.08:08:12.49#ibcon#*after write, iclass 33, count 0 2006.245.08:08:12.49#ibcon#*before return 0, iclass 33, count 0 2006.245.08:08:12.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:08:12.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:08:12.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:08:12.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:08:12.49$vc4f8/va=8,8 2006.245.08:08:12.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.08:08:12.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.08:08:12.49#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:12.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:08:12.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:08:12.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:08:12.54#ibcon#enter wrdev, iclass 35, count 2 2006.245.08:08:12.54#ibcon#first serial, iclass 35, count 2 2006.245.08:08:12.54#ibcon#enter sib2, iclass 35, count 2 2006.245.08:08:12.54#ibcon#flushed, iclass 35, count 2 2006.245.08:08:12.54#ibcon#about to write, iclass 35, count 2 2006.245.08:08:12.54#ibcon#wrote, iclass 35, count 2 2006.245.08:08:12.54#ibcon#about to read 3, iclass 35, count 2 2006.245.08:08:12.56#ibcon#read 3, iclass 35, count 2 2006.245.08:08:12.56#ibcon#about to read 4, iclass 35, count 2 2006.245.08:08:12.56#ibcon#read 4, iclass 35, count 2 2006.245.08:08:12.56#ibcon#about to read 5, iclass 35, count 2 2006.245.08:08:12.56#ibcon#read 5, iclass 35, count 2 2006.245.08:08:12.56#ibcon#about to read 6, iclass 35, count 2 2006.245.08:08:12.56#ibcon#read 6, iclass 35, count 2 2006.245.08:08:12.56#ibcon#end of sib2, iclass 35, count 2 2006.245.08:08:12.56#ibcon#*mode == 0, iclass 35, count 2 2006.245.08:08:12.56#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.08:08:12.56#ibcon#[25=AT08-08\r\n] 2006.245.08:08:12.56#ibcon#*before write, iclass 35, count 2 2006.245.08:08:12.56#ibcon#enter sib2, iclass 35, count 2 2006.245.08:08:12.56#ibcon#flushed, iclass 35, count 2 2006.245.08:08:12.56#ibcon#about to write, iclass 35, count 2 2006.245.08:08:12.56#ibcon#wrote, iclass 35, count 2 2006.245.08:08:12.56#ibcon#about to read 3, iclass 35, count 2 2006.245.08:08:12.59#ibcon#read 3, iclass 35, count 2 2006.245.08:08:12.59#ibcon#about to read 4, iclass 35, count 2 2006.245.08:08:12.59#ibcon#read 4, iclass 35, count 2 2006.245.08:08:12.59#ibcon#about to read 5, iclass 35, count 2 2006.245.08:08:12.59#ibcon#read 5, iclass 35, count 2 2006.245.08:08:12.59#ibcon#about to read 6, iclass 35, count 2 2006.245.08:08:12.59#ibcon#read 6, iclass 35, count 2 2006.245.08:08:12.59#ibcon#end of sib2, iclass 35, count 2 2006.245.08:08:12.59#ibcon#*after write, iclass 35, count 2 2006.245.08:08:12.59#ibcon#*before return 0, iclass 35, count 2 2006.245.08:08:12.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:08:12.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:08:12.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.08:08:12.59#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:12.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:08:12.71#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:08:12.71#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:08:12.71#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:08:12.71#ibcon#first serial, iclass 35, count 0 2006.245.08:08:12.71#ibcon#enter sib2, iclass 35, count 0 2006.245.08:08:12.71#ibcon#flushed, iclass 35, count 0 2006.245.08:08:12.71#ibcon#about to write, iclass 35, count 0 2006.245.08:08:12.71#ibcon#wrote, iclass 35, count 0 2006.245.08:08:12.71#ibcon#about to read 3, iclass 35, count 0 2006.245.08:08:12.73#ibcon#read 3, iclass 35, count 0 2006.245.08:08:12.73#ibcon#about to read 4, iclass 35, count 0 2006.245.08:08:12.73#ibcon#read 4, iclass 35, count 0 2006.245.08:08:12.73#ibcon#about to read 5, iclass 35, count 0 2006.245.08:08:12.73#ibcon#read 5, iclass 35, count 0 2006.245.08:08:12.73#ibcon#about to read 6, iclass 35, count 0 2006.245.08:08:12.73#ibcon#read 6, iclass 35, count 0 2006.245.08:08:12.73#ibcon#end of sib2, iclass 35, count 0 2006.245.08:08:12.73#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:08:12.73#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:08:12.73#ibcon#[25=USB\r\n] 2006.245.08:08:12.73#ibcon#*before write, iclass 35, count 0 2006.245.08:08:12.73#ibcon#enter sib2, iclass 35, count 0 2006.245.08:08:12.73#ibcon#flushed, iclass 35, count 0 2006.245.08:08:12.73#ibcon#about to write, iclass 35, count 0 2006.245.08:08:12.73#ibcon#wrote, iclass 35, count 0 2006.245.08:08:12.73#ibcon#about to read 3, iclass 35, count 0 2006.245.08:08:12.76#ibcon#read 3, iclass 35, count 0 2006.245.08:08:12.76#ibcon#about to read 4, iclass 35, count 0 2006.245.08:08:12.76#ibcon#read 4, iclass 35, count 0 2006.245.08:08:12.76#ibcon#about to read 5, iclass 35, count 0 2006.245.08:08:12.76#ibcon#read 5, iclass 35, count 0 2006.245.08:08:12.76#ibcon#about to read 6, iclass 35, count 0 2006.245.08:08:12.76#ibcon#read 6, iclass 35, count 0 2006.245.08:08:12.76#ibcon#end of sib2, iclass 35, count 0 2006.245.08:08:12.76#ibcon#*after write, iclass 35, count 0 2006.245.08:08:12.76#ibcon#*before return 0, iclass 35, count 0 2006.245.08:08:12.76#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:08:12.76#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:08:12.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:08:12.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:08:12.76$vc4f8/vblo=1,632.99 2006.245.08:08:12.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.08:08:12.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.08:08:12.76#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:12.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:08:12.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:08:12.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:08:12.76#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:08:12.76#ibcon#first serial, iclass 37, count 0 2006.245.08:08:12.76#ibcon#enter sib2, iclass 37, count 0 2006.245.08:08:12.76#ibcon#flushed, iclass 37, count 0 2006.245.08:08:12.76#ibcon#about to write, iclass 37, count 0 2006.245.08:08:12.76#ibcon#wrote, iclass 37, count 0 2006.245.08:08:12.76#ibcon#about to read 3, iclass 37, count 0 2006.245.08:08:12.78#ibcon#read 3, iclass 37, count 0 2006.245.08:08:12.78#ibcon#about to read 4, iclass 37, count 0 2006.245.08:08:12.78#ibcon#read 4, iclass 37, count 0 2006.245.08:08:12.78#ibcon#about to read 5, iclass 37, count 0 2006.245.08:08:12.78#ibcon#read 5, iclass 37, count 0 2006.245.08:08:12.78#ibcon#about to read 6, iclass 37, count 0 2006.245.08:08:12.78#ibcon#read 6, iclass 37, count 0 2006.245.08:08:12.78#ibcon#end of sib2, iclass 37, count 0 2006.245.08:08:12.78#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:08:12.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:08:12.78#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:08:12.78#ibcon#*before write, iclass 37, count 0 2006.245.08:08:12.78#ibcon#enter sib2, iclass 37, count 0 2006.245.08:08:12.78#ibcon#flushed, iclass 37, count 0 2006.245.08:08:12.78#ibcon#about to write, iclass 37, count 0 2006.245.08:08:12.78#ibcon#wrote, iclass 37, count 0 2006.245.08:08:12.78#ibcon#about to read 3, iclass 37, count 0 2006.245.08:08:12.82#ibcon#read 3, iclass 37, count 0 2006.245.08:08:12.82#ibcon#about to read 4, iclass 37, count 0 2006.245.08:08:12.82#ibcon#read 4, iclass 37, count 0 2006.245.08:08:12.82#ibcon#about to read 5, iclass 37, count 0 2006.245.08:08:12.82#ibcon#read 5, iclass 37, count 0 2006.245.08:08:12.82#ibcon#about to read 6, iclass 37, count 0 2006.245.08:08:12.82#ibcon#read 6, iclass 37, count 0 2006.245.08:08:12.82#ibcon#end of sib2, iclass 37, count 0 2006.245.08:08:12.82#ibcon#*after write, iclass 37, count 0 2006.245.08:08:12.82#ibcon#*before return 0, iclass 37, count 0 2006.245.08:08:12.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:08:12.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:08:12.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:08:12.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:08:12.82$vc4f8/vb=1,4 2006.245.08:08:12.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.08:08:12.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.08:08:12.82#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:12.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:08:12.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:08:12.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:08:12.82#ibcon#enter wrdev, iclass 39, count 2 2006.245.08:08:12.82#ibcon#first serial, iclass 39, count 2 2006.245.08:08:12.82#ibcon#enter sib2, iclass 39, count 2 2006.245.08:08:12.82#ibcon#flushed, iclass 39, count 2 2006.245.08:08:12.82#ibcon#about to write, iclass 39, count 2 2006.245.08:08:12.82#ibcon#wrote, iclass 39, count 2 2006.245.08:08:12.82#ibcon#about to read 3, iclass 39, count 2 2006.245.08:08:12.84#ibcon#read 3, iclass 39, count 2 2006.245.08:08:12.84#ibcon#about to read 4, iclass 39, count 2 2006.245.08:08:12.84#ibcon#read 4, iclass 39, count 2 2006.245.08:08:12.84#ibcon#about to read 5, iclass 39, count 2 2006.245.08:08:12.84#ibcon#read 5, iclass 39, count 2 2006.245.08:08:12.84#ibcon#about to read 6, iclass 39, count 2 2006.245.08:08:12.84#ibcon#read 6, iclass 39, count 2 2006.245.08:08:12.84#ibcon#end of sib2, iclass 39, count 2 2006.245.08:08:12.84#ibcon#*mode == 0, iclass 39, count 2 2006.245.08:08:12.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.08:08:12.84#ibcon#[27=AT01-04\r\n] 2006.245.08:08:12.84#ibcon#*before write, iclass 39, count 2 2006.245.08:08:12.84#ibcon#enter sib2, iclass 39, count 2 2006.245.08:08:12.84#ibcon#flushed, iclass 39, count 2 2006.245.08:08:12.84#ibcon#about to write, iclass 39, count 2 2006.245.08:08:12.84#ibcon#wrote, iclass 39, count 2 2006.245.08:08:12.84#ibcon#about to read 3, iclass 39, count 2 2006.245.08:08:12.87#ibcon#read 3, iclass 39, count 2 2006.245.08:08:12.87#ibcon#about to read 4, iclass 39, count 2 2006.245.08:08:12.87#ibcon#read 4, iclass 39, count 2 2006.245.08:08:12.87#ibcon#about to read 5, iclass 39, count 2 2006.245.08:08:12.87#ibcon#read 5, iclass 39, count 2 2006.245.08:08:12.87#ibcon#about to read 6, iclass 39, count 2 2006.245.08:08:12.87#ibcon#read 6, iclass 39, count 2 2006.245.08:08:12.87#ibcon#end of sib2, iclass 39, count 2 2006.245.08:08:12.87#ibcon#*after write, iclass 39, count 2 2006.245.08:08:12.87#ibcon#*before return 0, iclass 39, count 2 2006.245.08:08:12.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:08:12.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:08:12.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.08:08:12.87#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:12.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:08:12.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:08:12.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:08:12.99#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:08:12.99#ibcon#first serial, iclass 39, count 0 2006.245.08:08:12.99#ibcon#enter sib2, iclass 39, count 0 2006.245.08:08:12.99#ibcon#flushed, iclass 39, count 0 2006.245.08:08:12.99#ibcon#about to write, iclass 39, count 0 2006.245.08:08:12.99#ibcon#wrote, iclass 39, count 0 2006.245.08:08:12.99#ibcon#about to read 3, iclass 39, count 0 2006.245.08:08:13.01#ibcon#read 3, iclass 39, count 0 2006.245.08:08:13.01#ibcon#about to read 4, iclass 39, count 0 2006.245.08:08:13.01#ibcon#read 4, iclass 39, count 0 2006.245.08:08:13.01#ibcon#about to read 5, iclass 39, count 0 2006.245.08:08:13.01#ibcon#read 5, iclass 39, count 0 2006.245.08:08:13.01#ibcon#about to read 6, iclass 39, count 0 2006.245.08:08:13.01#ibcon#read 6, iclass 39, count 0 2006.245.08:08:13.01#ibcon#end of sib2, iclass 39, count 0 2006.245.08:08:13.01#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:08:13.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:08:13.01#ibcon#[27=USB\r\n] 2006.245.08:08:13.01#ibcon#*before write, iclass 39, count 0 2006.245.08:08:13.01#ibcon#enter sib2, iclass 39, count 0 2006.245.08:08:13.01#ibcon#flushed, iclass 39, count 0 2006.245.08:08:13.01#ibcon#about to write, iclass 39, count 0 2006.245.08:08:13.01#ibcon#wrote, iclass 39, count 0 2006.245.08:08:13.01#ibcon#about to read 3, iclass 39, count 0 2006.245.08:08:13.04#ibcon#read 3, iclass 39, count 0 2006.245.08:08:13.04#ibcon#about to read 4, iclass 39, count 0 2006.245.08:08:13.04#ibcon#read 4, iclass 39, count 0 2006.245.08:08:13.04#ibcon#about to read 5, iclass 39, count 0 2006.245.08:08:13.04#ibcon#read 5, iclass 39, count 0 2006.245.08:08:13.04#ibcon#about to read 6, iclass 39, count 0 2006.245.08:08:13.04#ibcon#read 6, iclass 39, count 0 2006.245.08:08:13.04#ibcon#end of sib2, iclass 39, count 0 2006.245.08:08:13.04#ibcon#*after write, iclass 39, count 0 2006.245.08:08:13.04#ibcon#*before return 0, iclass 39, count 0 2006.245.08:08:13.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:08:13.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:08:13.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:08:13.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:08:13.04$vc4f8/vblo=2,640.99 2006.245.08:08:13.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:08:13.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:08:13.04#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:13.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:13.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:13.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:13.04#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:08:13.04#ibcon#first serial, iclass 3, count 0 2006.245.08:08:13.04#ibcon#enter sib2, iclass 3, count 0 2006.245.08:08:13.04#ibcon#flushed, iclass 3, count 0 2006.245.08:08:13.04#ibcon#about to write, iclass 3, count 0 2006.245.08:08:13.04#ibcon#wrote, iclass 3, count 0 2006.245.08:08:13.04#ibcon#about to read 3, iclass 3, count 0 2006.245.08:08:13.06#ibcon#read 3, iclass 3, count 0 2006.245.08:08:13.06#ibcon#about to read 4, iclass 3, count 0 2006.245.08:08:13.06#ibcon#read 4, iclass 3, count 0 2006.245.08:08:13.06#ibcon#about to read 5, iclass 3, count 0 2006.245.08:08:13.06#ibcon#read 5, iclass 3, count 0 2006.245.08:08:13.06#ibcon#about to read 6, iclass 3, count 0 2006.245.08:08:13.06#ibcon#read 6, iclass 3, count 0 2006.245.08:08:13.06#ibcon#end of sib2, iclass 3, count 0 2006.245.08:08:13.06#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:08:13.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:08:13.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:08:13.06#ibcon#*before write, iclass 3, count 0 2006.245.08:08:13.06#ibcon#enter sib2, iclass 3, count 0 2006.245.08:08:13.06#ibcon#flushed, iclass 3, count 0 2006.245.08:08:13.06#ibcon#about to write, iclass 3, count 0 2006.245.08:08:13.06#ibcon#wrote, iclass 3, count 0 2006.245.08:08:13.06#ibcon#about to read 3, iclass 3, count 0 2006.245.08:08:13.10#ibcon#read 3, iclass 3, count 0 2006.245.08:08:13.10#ibcon#about to read 4, iclass 3, count 0 2006.245.08:08:13.10#ibcon#read 4, iclass 3, count 0 2006.245.08:08:13.10#ibcon#about to read 5, iclass 3, count 0 2006.245.08:08:13.10#ibcon#read 5, iclass 3, count 0 2006.245.08:08:13.10#ibcon#about to read 6, iclass 3, count 0 2006.245.08:08:13.10#ibcon#read 6, iclass 3, count 0 2006.245.08:08:13.10#ibcon#end of sib2, iclass 3, count 0 2006.245.08:08:13.10#ibcon#*after write, iclass 3, count 0 2006.245.08:08:13.10#ibcon#*before return 0, iclass 3, count 0 2006.245.08:08:13.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:13.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:08:13.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:08:13.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:08:13.10$vc4f8/vb=2,4 2006.245.08:08:13.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:08:13.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:08:13.10#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:13.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:13.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:13.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:13.16#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:08:13.16#ibcon#first serial, iclass 5, count 2 2006.245.08:08:13.16#ibcon#enter sib2, iclass 5, count 2 2006.245.08:08:13.16#ibcon#flushed, iclass 5, count 2 2006.245.08:08:13.16#ibcon#about to write, iclass 5, count 2 2006.245.08:08:13.16#ibcon#wrote, iclass 5, count 2 2006.245.08:08:13.16#ibcon#about to read 3, iclass 5, count 2 2006.245.08:08:13.18#ibcon#read 3, iclass 5, count 2 2006.245.08:08:13.18#ibcon#about to read 4, iclass 5, count 2 2006.245.08:08:13.18#ibcon#read 4, iclass 5, count 2 2006.245.08:08:13.18#ibcon#about to read 5, iclass 5, count 2 2006.245.08:08:13.18#ibcon#read 5, iclass 5, count 2 2006.245.08:08:13.18#ibcon#about to read 6, iclass 5, count 2 2006.245.08:08:13.18#ibcon#read 6, iclass 5, count 2 2006.245.08:08:13.18#ibcon#end of sib2, iclass 5, count 2 2006.245.08:08:13.18#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:08:13.18#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:08:13.18#ibcon#[27=AT02-04\r\n] 2006.245.08:08:13.18#ibcon#*before write, iclass 5, count 2 2006.245.08:08:13.18#ibcon#enter sib2, iclass 5, count 2 2006.245.08:08:13.18#ibcon#flushed, iclass 5, count 2 2006.245.08:08:13.18#ibcon#about to write, iclass 5, count 2 2006.245.08:08:13.18#ibcon#wrote, iclass 5, count 2 2006.245.08:08:13.18#ibcon#about to read 3, iclass 5, count 2 2006.245.08:08:13.21#ibcon#read 3, iclass 5, count 2 2006.245.08:08:13.21#ibcon#about to read 4, iclass 5, count 2 2006.245.08:08:13.21#ibcon#read 4, iclass 5, count 2 2006.245.08:08:13.21#ibcon#about to read 5, iclass 5, count 2 2006.245.08:08:13.21#ibcon#read 5, iclass 5, count 2 2006.245.08:08:13.21#ibcon#about to read 6, iclass 5, count 2 2006.245.08:08:13.21#ibcon#read 6, iclass 5, count 2 2006.245.08:08:13.21#ibcon#end of sib2, iclass 5, count 2 2006.245.08:08:13.21#ibcon#*after write, iclass 5, count 2 2006.245.08:08:13.21#ibcon#*before return 0, iclass 5, count 2 2006.245.08:08:13.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:13.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:08:13.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:08:13.21#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:13.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:13.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:13.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:13.33#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:08:13.33#ibcon#first serial, iclass 5, count 0 2006.245.08:08:13.33#ibcon#enter sib2, iclass 5, count 0 2006.245.08:08:13.33#ibcon#flushed, iclass 5, count 0 2006.245.08:08:13.33#ibcon#about to write, iclass 5, count 0 2006.245.08:08:13.33#ibcon#wrote, iclass 5, count 0 2006.245.08:08:13.33#ibcon#about to read 3, iclass 5, count 0 2006.245.08:08:13.35#ibcon#read 3, iclass 5, count 0 2006.245.08:08:13.35#ibcon#about to read 4, iclass 5, count 0 2006.245.08:08:13.35#ibcon#read 4, iclass 5, count 0 2006.245.08:08:13.35#ibcon#about to read 5, iclass 5, count 0 2006.245.08:08:13.35#ibcon#read 5, iclass 5, count 0 2006.245.08:08:13.35#ibcon#about to read 6, iclass 5, count 0 2006.245.08:08:13.35#ibcon#read 6, iclass 5, count 0 2006.245.08:08:13.35#ibcon#end of sib2, iclass 5, count 0 2006.245.08:08:13.35#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:08:13.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:08:13.35#ibcon#[27=USB\r\n] 2006.245.08:08:13.35#ibcon#*before write, iclass 5, count 0 2006.245.08:08:13.35#ibcon#enter sib2, iclass 5, count 0 2006.245.08:08:13.35#ibcon#flushed, iclass 5, count 0 2006.245.08:08:13.35#ibcon#about to write, iclass 5, count 0 2006.245.08:08:13.35#ibcon#wrote, iclass 5, count 0 2006.245.08:08:13.35#ibcon#about to read 3, iclass 5, count 0 2006.245.08:08:13.38#ibcon#read 3, iclass 5, count 0 2006.245.08:08:13.38#ibcon#about to read 4, iclass 5, count 0 2006.245.08:08:13.38#ibcon#read 4, iclass 5, count 0 2006.245.08:08:13.38#ibcon#about to read 5, iclass 5, count 0 2006.245.08:08:13.38#ibcon#read 5, iclass 5, count 0 2006.245.08:08:13.38#ibcon#about to read 6, iclass 5, count 0 2006.245.08:08:13.38#ibcon#read 6, iclass 5, count 0 2006.245.08:08:13.38#ibcon#end of sib2, iclass 5, count 0 2006.245.08:08:13.38#ibcon#*after write, iclass 5, count 0 2006.245.08:08:13.38#ibcon#*before return 0, iclass 5, count 0 2006.245.08:08:13.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:13.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:08:13.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:08:13.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:08:13.38$vc4f8/vblo=3,656.99 2006.245.08:08:13.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:08:13.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:08:13.38#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:13.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:13.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:13.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:13.38#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:08:13.38#ibcon#first serial, iclass 7, count 0 2006.245.08:08:13.38#ibcon#enter sib2, iclass 7, count 0 2006.245.08:08:13.38#ibcon#flushed, iclass 7, count 0 2006.245.08:08:13.38#ibcon#about to write, iclass 7, count 0 2006.245.08:08:13.38#ibcon#wrote, iclass 7, count 0 2006.245.08:08:13.38#ibcon#about to read 3, iclass 7, count 0 2006.245.08:08:13.40#ibcon#read 3, iclass 7, count 0 2006.245.08:08:13.40#ibcon#about to read 4, iclass 7, count 0 2006.245.08:08:13.40#ibcon#read 4, iclass 7, count 0 2006.245.08:08:13.40#ibcon#about to read 5, iclass 7, count 0 2006.245.08:08:13.40#ibcon#read 5, iclass 7, count 0 2006.245.08:08:13.40#ibcon#about to read 6, iclass 7, count 0 2006.245.08:08:13.40#ibcon#read 6, iclass 7, count 0 2006.245.08:08:13.40#ibcon#end of sib2, iclass 7, count 0 2006.245.08:08:13.40#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:08:13.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:08:13.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:08:13.40#ibcon#*before write, iclass 7, count 0 2006.245.08:08:13.40#ibcon#enter sib2, iclass 7, count 0 2006.245.08:08:13.40#ibcon#flushed, iclass 7, count 0 2006.245.08:08:13.40#ibcon#about to write, iclass 7, count 0 2006.245.08:08:13.40#ibcon#wrote, iclass 7, count 0 2006.245.08:08:13.40#ibcon#about to read 3, iclass 7, count 0 2006.245.08:08:13.44#ibcon#read 3, iclass 7, count 0 2006.245.08:08:13.44#ibcon#about to read 4, iclass 7, count 0 2006.245.08:08:13.44#ibcon#read 4, iclass 7, count 0 2006.245.08:08:13.44#ibcon#about to read 5, iclass 7, count 0 2006.245.08:08:13.44#ibcon#read 5, iclass 7, count 0 2006.245.08:08:13.44#ibcon#about to read 6, iclass 7, count 0 2006.245.08:08:13.44#ibcon#read 6, iclass 7, count 0 2006.245.08:08:13.44#ibcon#end of sib2, iclass 7, count 0 2006.245.08:08:13.44#ibcon#*after write, iclass 7, count 0 2006.245.08:08:13.44#ibcon#*before return 0, iclass 7, count 0 2006.245.08:08:13.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:13.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:08:13.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:08:13.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:08:13.44$vc4f8/vb=3,4 2006.245.08:08:13.44#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:08:13.44#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:08:13.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:13.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:13.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:13.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:13.50#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:08:13.50#ibcon#first serial, iclass 11, count 2 2006.245.08:08:13.50#ibcon#enter sib2, iclass 11, count 2 2006.245.08:08:13.50#ibcon#flushed, iclass 11, count 2 2006.245.08:08:13.50#ibcon#about to write, iclass 11, count 2 2006.245.08:08:13.50#ibcon#wrote, iclass 11, count 2 2006.245.08:08:13.50#ibcon#about to read 3, iclass 11, count 2 2006.245.08:08:13.52#ibcon#read 3, iclass 11, count 2 2006.245.08:08:13.52#ibcon#about to read 4, iclass 11, count 2 2006.245.08:08:13.52#ibcon#read 4, iclass 11, count 2 2006.245.08:08:13.52#ibcon#about to read 5, iclass 11, count 2 2006.245.08:08:13.52#ibcon#read 5, iclass 11, count 2 2006.245.08:08:13.52#ibcon#about to read 6, iclass 11, count 2 2006.245.08:08:13.52#ibcon#read 6, iclass 11, count 2 2006.245.08:08:13.52#ibcon#end of sib2, iclass 11, count 2 2006.245.08:08:13.52#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:08:13.52#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:08:13.52#ibcon#[27=AT03-04\r\n] 2006.245.08:08:13.52#ibcon#*before write, iclass 11, count 2 2006.245.08:08:13.52#ibcon#enter sib2, iclass 11, count 2 2006.245.08:08:13.52#ibcon#flushed, iclass 11, count 2 2006.245.08:08:13.52#ibcon#about to write, iclass 11, count 2 2006.245.08:08:13.52#ibcon#wrote, iclass 11, count 2 2006.245.08:08:13.52#ibcon#about to read 3, iclass 11, count 2 2006.245.08:08:13.55#ibcon#read 3, iclass 11, count 2 2006.245.08:08:13.55#ibcon#about to read 4, iclass 11, count 2 2006.245.08:08:13.55#ibcon#read 4, iclass 11, count 2 2006.245.08:08:13.55#ibcon#about to read 5, iclass 11, count 2 2006.245.08:08:13.55#ibcon#read 5, iclass 11, count 2 2006.245.08:08:13.55#ibcon#about to read 6, iclass 11, count 2 2006.245.08:08:13.55#ibcon#read 6, iclass 11, count 2 2006.245.08:08:13.55#ibcon#end of sib2, iclass 11, count 2 2006.245.08:08:13.55#ibcon#*after write, iclass 11, count 2 2006.245.08:08:13.55#ibcon#*before return 0, iclass 11, count 2 2006.245.08:08:13.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:13.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:08:13.55#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:08:13.55#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:13.55#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:13.67#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:13.67#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:13.67#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:08:13.67#ibcon#first serial, iclass 11, count 0 2006.245.08:08:13.67#ibcon#enter sib2, iclass 11, count 0 2006.245.08:08:13.67#ibcon#flushed, iclass 11, count 0 2006.245.08:08:13.67#ibcon#about to write, iclass 11, count 0 2006.245.08:08:13.67#ibcon#wrote, iclass 11, count 0 2006.245.08:08:13.67#ibcon#about to read 3, iclass 11, count 0 2006.245.08:08:13.69#ibcon#read 3, iclass 11, count 0 2006.245.08:08:13.69#ibcon#about to read 4, iclass 11, count 0 2006.245.08:08:13.69#ibcon#read 4, iclass 11, count 0 2006.245.08:08:13.69#ibcon#about to read 5, iclass 11, count 0 2006.245.08:08:13.69#ibcon#read 5, iclass 11, count 0 2006.245.08:08:13.69#ibcon#about to read 6, iclass 11, count 0 2006.245.08:08:13.69#ibcon#read 6, iclass 11, count 0 2006.245.08:08:13.69#ibcon#end of sib2, iclass 11, count 0 2006.245.08:08:13.69#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:08:13.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:08:13.69#ibcon#[27=USB\r\n] 2006.245.08:08:13.69#ibcon#*before write, iclass 11, count 0 2006.245.08:08:13.69#ibcon#enter sib2, iclass 11, count 0 2006.245.08:08:13.69#ibcon#flushed, iclass 11, count 0 2006.245.08:08:13.69#ibcon#about to write, iclass 11, count 0 2006.245.08:08:13.69#ibcon#wrote, iclass 11, count 0 2006.245.08:08:13.69#ibcon#about to read 3, iclass 11, count 0 2006.245.08:08:13.72#ibcon#read 3, iclass 11, count 0 2006.245.08:08:13.72#ibcon#about to read 4, iclass 11, count 0 2006.245.08:08:13.72#ibcon#read 4, iclass 11, count 0 2006.245.08:08:13.72#ibcon#about to read 5, iclass 11, count 0 2006.245.08:08:13.72#ibcon#read 5, iclass 11, count 0 2006.245.08:08:13.72#ibcon#about to read 6, iclass 11, count 0 2006.245.08:08:13.72#ibcon#read 6, iclass 11, count 0 2006.245.08:08:13.72#ibcon#end of sib2, iclass 11, count 0 2006.245.08:08:13.72#ibcon#*after write, iclass 11, count 0 2006.245.08:08:13.72#ibcon#*before return 0, iclass 11, count 0 2006.245.08:08:13.72#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:13.72#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:08:13.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:08:13.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:08:13.72$vc4f8/vblo=4,712.99 2006.245.08:08:13.72#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:08:13.72#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:08:13.72#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:13.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:13.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:13.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:13.72#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:08:13.72#ibcon#first serial, iclass 13, count 0 2006.245.08:08:13.72#ibcon#enter sib2, iclass 13, count 0 2006.245.08:08:13.72#ibcon#flushed, iclass 13, count 0 2006.245.08:08:13.72#ibcon#about to write, iclass 13, count 0 2006.245.08:08:13.72#ibcon#wrote, iclass 13, count 0 2006.245.08:08:13.72#ibcon#about to read 3, iclass 13, count 0 2006.245.08:08:13.74#ibcon#read 3, iclass 13, count 0 2006.245.08:08:13.74#ibcon#about to read 4, iclass 13, count 0 2006.245.08:08:13.74#ibcon#read 4, iclass 13, count 0 2006.245.08:08:13.74#ibcon#about to read 5, iclass 13, count 0 2006.245.08:08:13.74#ibcon#read 5, iclass 13, count 0 2006.245.08:08:13.74#ibcon#about to read 6, iclass 13, count 0 2006.245.08:08:13.74#ibcon#read 6, iclass 13, count 0 2006.245.08:08:13.74#ibcon#end of sib2, iclass 13, count 0 2006.245.08:08:13.74#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:08:13.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:08:13.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:08:13.74#ibcon#*before write, iclass 13, count 0 2006.245.08:08:13.74#ibcon#enter sib2, iclass 13, count 0 2006.245.08:08:13.74#ibcon#flushed, iclass 13, count 0 2006.245.08:08:13.74#ibcon#about to write, iclass 13, count 0 2006.245.08:08:13.74#ibcon#wrote, iclass 13, count 0 2006.245.08:08:13.74#ibcon#about to read 3, iclass 13, count 0 2006.245.08:08:13.78#ibcon#read 3, iclass 13, count 0 2006.245.08:08:13.78#ibcon#about to read 4, iclass 13, count 0 2006.245.08:08:13.78#ibcon#read 4, iclass 13, count 0 2006.245.08:08:13.78#ibcon#about to read 5, iclass 13, count 0 2006.245.08:08:13.78#ibcon#read 5, iclass 13, count 0 2006.245.08:08:13.78#ibcon#about to read 6, iclass 13, count 0 2006.245.08:08:13.78#ibcon#read 6, iclass 13, count 0 2006.245.08:08:13.78#ibcon#end of sib2, iclass 13, count 0 2006.245.08:08:13.78#ibcon#*after write, iclass 13, count 0 2006.245.08:08:13.78#ibcon#*before return 0, iclass 13, count 0 2006.245.08:08:13.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:13.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:08:13.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:08:13.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:08:13.78$vc4f8/vb=4,4 2006.245.08:08:13.78#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:08:13.78#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:08:13.78#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:13.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:13.84#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:13.84#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:13.84#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:08:13.84#ibcon#first serial, iclass 15, count 2 2006.245.08:08:13.84#ibcon#enter sib2, iclass 15, count 2 2006.245.08:08:13.84#ibcon#flushed, iclass 15, count 2 2006.245.08:08:13.84#ibcon#about to write, iclass 15, count 2 2006.245.08:08:13.84#ibcon#wrote, iclass 15, count 2 2006.245.08:08:13.84#ibcon#about to read 3, iclass 15, count 2 2006.245.08:08:13.86#ibcon#read 3, iclass 15, count 2 2006.245.08:08:13.86#ibcon#about to read 4, iclass 15, count 2 2006.245.08:08:13.86#ibcon#read 4, iclass 15, count 2 2006.245.08:08:13.86#ibcon#about to read 5, iclass 15, count 2 2006.245.08:08:13.86#ibcon#read 5, iclass 15, count 2 2006.245.08:08:13.86#ibcon#about to read 6, iclass 15, count 2 2006.245.08:08:13.86#ibcon#read 6, iclass 15, count 2 2006.245.08:08:13.86#ibcon#end of sib2, iclass 15, count 2 2006.245.08:08:13.86#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:08:13.86#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:08:13.86#ibcon#[27=AT04-04\r\n] 2006.245.08:08:13.86#ibcon#*before write, iclass 15, count 2 2006.245.08:08:13.86#ibcon#enter sib2, iclass 15, count 2 2006.245.08:08:13.86#ibcon#flushed, iclass 15, count 2 2006.245.08:08:13.86#ibcon#about to write, iclass 15, count 2 2006.245.08:08:13.86#ibcon#wrote, iclass 15, count 2 2006.245.08:08:13.86#ibcon#about to read 3, iclass 15, count 2 2006.245.08:08:13.89#ibcon#read 3, iclass 15, count 2 2006.245.08:08:13.89#ibcon#about to read 4, iclass 15, count 2 2006.245.08:08:13.89#ibcon#read 4, iclass 15, count 2 2006.245.08:08:13.89#ibcon#about to read 5, iclass 15, count 2 2006.245.08:08:13.89#ibcon#read 5, iclass 15, count 2 2006.245.08:08:13.89#ibcon#about to read 6, iclass 15, count 2 2006.245.08:08:13.89#ibcon#read 6, iclass 15, count 2 2006.245.08:08:13.89#ibcon#end of sib2, iclass 15, count 2 2006.245.08:08:13.89#ibcon#*after write, iclass 15, count 2 2006.245.08:08:13.89#ibcon#*before return 0, iclass 15, count 2 2006.245.08:08:13.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:13.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:08:13.89#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:08:13.89#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:13.89#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:14.01#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:14.01#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:14.01#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:08:14.01#ibcon#first serial, iclass 15, count 0 2006.245.08:08:14.01#ibcon#enter sib2, iclass 15, count 0 2006.245.08:08:14.01#ibcon#flushed, iclass 15, count 0 2006.245.08:08:14.01#ibcon#about to write, iclass 15, count 0 2006.245.08:08:14.01#ibcon#wrote, iclass 15, count 0 2006.245.08:08:14.01#ibcon#about to read 3, iclass 15, count 0 2006.245.08:08:14.03#ibcon#read 3, iclass 15, count 0 2006.245.08:08:14.03#ibcon#about to read 4, iclass 15, count 0 2006.245.08:08:14.03#ibcon#read 4, iclass 15, count 0 2006.245.08:08:14.03#ibcon#about to read 5, iclass 15, count 0 2006.245.08:08:14.03#ibcon#read 5, iclass 15, count 0 2006.245.08:08:14.03#ibcon#about to read 6, iclass 15, count 0 2006.245.08:08:14.03#ibcon#read 6, iclass 15, count 0 2006.245.08:08:14.03#ibcon#end of sib2, iclass 15, count 0 2006.245.08:08:14.03#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:08:14.03#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:08:14.03#ibcon#[27=USB\r\n] 2006.245.08:08:14.03#ibcon#*before write, iclass 15, count 0 2006.245.08:08:14.03#ibcon#enter sib2, iclass 15, count 0 2006.245.08:08:14.03#ibcon#flushed, iclass 15, count 0 2006.245.08:08:14.03#ibcon#about to write, iclass 15, count 0 2006.245.08:08:14.03#ibcon#wrote, iclass 15, count 0 2006.245.08:08:14.03#ibcon#about to read 3, iclass 15, count 0 2006.245.08:08:14.06#ibcon#read 3, iclass 15, count 0 2006.245.08:08:14.06#ibcon#about to read 4, iclass 15, count 0 2006.245.08:08:14.06#ibcon#read 4, iclass 15, count 0 2006.245.08:08:14.06#ibcon#about to read 5, iclass 15, count 0 2006.245.08:08:14.06#ibcon#read 5, iclass 15, count 0 2006.245.08:08:14.06#ibcon#about to read 6, iclass 15, count 0 2006.245.08:08:14.06#ibcon#read 6, iclass 15, count 0 2006.245.08:08:14.06#ibcon#end of sib2, iclass 15, count 0 2006.245.08:08:14.06#ibcon#*after write, iclass 15, count 0 2006.245.08:08:14.06#ibcon#*before return 0, iclass 15, count 0 2006.245.08:08:14.06#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:14.06#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:08:14.06#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:08:14.06#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:08:14.06$vc4f8/vblo=5,744.99 2006.245.08:08:14.06#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:08:14.06#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:08:14.06#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:14.06#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:14.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:14.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:14.06#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:08:14.06#ibcon#first serial, iclass 17, count 0 2006.245.08:08:14.06#ibcon#enter sib2, iclass 17, count 0 2006.245.08:08:14.06#ibcon#flushed, iclass 17, count 0 2006.245.08:08:14.06#ibcon#about to write, iclass 17, count 0 2006.245.08:08:14.06#ibcon#wrote, iclass 17, count 0 2006.245.08:08:14.06#ibcon#about to read 3, iclass 17, count 0 2006.245.08:08:14.08#ibcon#read 3, iclass 17, count 0 2006.245.08:08:14.08#ibcon#about to read 4, iclass 17, count 0 2006.245.08:08:14.08#ibcon#read 4, iclass 17, count 0 2006.245.08:08:14.08#ibcon#about to read 5, iclass 17, count 0 2006.245.08:08:14.08#ibcon#read 5, iclass 17, count 0 2006.245.08:08:14.08#ibcon#about to read 6, iclass 17, count 0 2006.245.08:08:14.08#ibcon#read 6, iclass 17, count 0 2006.245.08:08:14.08#ibcon#end of sib2, iclass 17, count 0 2006.245.08:08:14.08#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:08:14.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:08:14.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:08:14.08#ibcon#*before write, iclass 17, count 0 2006.245.08:08:14.08#ibcon#enter sib2, iclass 17, count 0 2006.245.08:08:14.08#ibcon#flushed, iclass 17, count 0 2006.245.08:08:14.08#ibcon#about to write, iclass 17, count 0 2006.245.08:08:14.08#ibcon#wrote, iclass 17, count 0 2006.245.08:08:14.08#ibcon#about to read 3, iclass 17, count 0 2006.245.08:08:14.12#ibcon#read 3, iclass 17, count 0 2006.245.08:08:14.12#ibcon#about to read 4, iclass 17, count 0 2006.245.08:08:14.12#ibcon#read 4, iclass 17, count 0 2006.245.08:08:14.12#ibcon#about to read 5, iclass 17, count 0 2006.245.08:08:14.12#ibcon#read 5, iclass 17, count 0 2006.245.08:08:14.12#ibcon#about to read 6, iclass 17, count 0 2006.245.08:08:14.12#ibcon#read 6, iclass 17, count 0 2006.245.08:08:14.12#ibcon#end of sib2, iclass 17, count 0 2006.245.08:08:14.12#ibcon#*after write, iclass 17, count 0 2006.245.08:08:14.12#ibcon#*before return 0, iclass 17, count 0 2006.245.08:08:14.12#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:14.12#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:08:14.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:08:14.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:08:14.12$vc4f8/vb=5,3 2006.245.08:08:14.12#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:08:14.12#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:08:14.12#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:14.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:14.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:14.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:14.18#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:08:14.18#ibcon#first serial, iclass 19, count 2 2006.245.08:08:14.18#ibcon#enter sib2, iclass 19, count 2 2006.245.08:08:14.18#ibcon#flushed, iclass 19, count 2 2006.245.08:08:14.18#ibcon#about to write, iclass 19, count 2 2006.245.08:08:14.18#ibcon#wrote, iclass 19, count 2 2006.245.08:08:14.18#ibcon#about to read 3, iclass 19, count 2 2006.245.08:08:14.20#ibcon#read 3, iclass 19, count 2 2006.245.08:08:14.20#ibcon#about to read 4, iclass 19, count 2 2006.245.08:08:14.20#ibcon#read 4, iclass 19, count 2 2006.245.08:08:14.20#ibcon#about to read 5, iclass 19, count 2 2006.245.08:08:14.20#ibcon#read 5, iclass 19, count 2 2006.245.08:08:14.20#ibcon#about to read 6, iclass 19, count 2 2006.245.08:08:14.20#ibcon#read 6, iclass 19, count 2 2006.245.08:08:14.20#ibcon#end of sib2, iclass 19, count 2 2006.245.08:08:14.20#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:08:14.20#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:08:14.20#ibcon#[27=AT05-03\r\n] 2006.245.08:08:14.20#ibcon#*before write, iclass 19, count 2 2006.245.08:08:14.20#ibcon#enter sib2, iclass 19, count 2 2006.245.08:08:14.20#ibcon#flushed, iclass 19, count 2 2006.245.08:08:14.20#ibcon#about to write, iclass 19, count 2 2006.245.08:08:14.20#ibcon#wrote, iclass 19, count 2 2006.245.08:08:14.20#ibcon#about to read 3, iclass 19, count 2 2006.245.08:08:14.23#ibcon#read 3, iclass 19, count 2 2006.245.08:08:14.23#ibcon#about to read 4, iclass 19, count 2 2006.245.08:08:14.23#ibcon#read 4, iclass 19, count 2 2006.245.08:08:14.23#ibcon#about to read 5, iclass 19, count 2 2006.245.08:08:14.23#ibcon#read 5, iclass 19, count 2 2006.245.08:08:14.23#ibcon#about to read 6, iclass 19, count 2 2006.245.08:08:14.23#ibcon#read 6, iclass 19, count 2 2006.245.08:08:14.23#ibcon#end of sib2, iclass 19, count 2 2006.245.08:08:14.23#ibcon#*after write, iclass 19, count 2 2006.245.08:08:14.23#ibcon#*before return 0, iclass 19, count 2 2006.245.08:08:14.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:14.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:08:14.23#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:08:14.23#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:14.23#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:14.35#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:14.35#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:14.35#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:08:14.35#ibcon#first serial, iclass 19, count 0 2006.245.08:08:14.35#ibcon#enter sib2, iclass 19, count 0 2006.245.08:08:14.35#ibcon#flushed, iclass 19, count 0 2006.245.08:08:14.35#ibcon#about to write, iclass 19, count 0 2006.245.08:08:14.35#ibcon#wrote, iclass 19, count 0 2006.245.08:08:14.35#ibcon#about to read 3, iclass 19, count 0 2006.245.08:08:14.37#ibcon#read 3, iclass 19, count 0 2006.245.08:08:14.37#ibcon#about to read 4, iclass 19, count 0 2006.245.08:08:14.37#ibcon#read 4, iclass 19, count 0 2006.245.08:08:14.37#ibcon#about to read 5, iclass 19, count 0 2006.245.08:08:14.37#ibcon#read 5, iclass 19, count 0 2006.245.08:08:14.37#ibcon#about to read 6, iclass 19, count 0 2006.245.08:08:14.37#ibcon#read 6, iclass 19, count 0 2006.245.08:08:14.37#ibcon#end of sib2, iclass 19, count 0 2006.245.08:08:14.37#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:08:14.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:08:14.37#ibcon#[27=USB\r\n] 2006.245.08:08:14.37#ibcon#*before write, iclass 19, count 0 2006.245.08:08:14.37#ibcon#enter sib2, iclass 19, count 0 2006.245.08:08:14.37#ibcon#flushed, iclass 19, count 0 2006.245.08:08:14.37#ibcon#about to write, iclass 19, count 0 2006.245.08:08:14.37#ibcon#wrote, iclass 19, count 0 2006.245.08:08:14.37#ibcon#about to read 3, iclass 19, count 0 2006.245.08:08:14.38#abcon#<5=/05 3.3 5.9 26.99 731004.5\r\n> 2006.245.08:08:14.40#abcon#{5=INTERFACE CLEAR} 2006.245.08:08:14.40#ibcon#read 3, iclass 19, count 0 2006.245.08:08:14.40#ibcon#about to read 4, iclass 19, count 0 2006.245.08:08:14.40#ibcon#read 4, iclass 19, count 0 2006.245.08:08:14.40#ibcon#about to read 5, iclass 19, count 0 2006.245.08:08:14.40#ibcon#read 5, iclass 19, count 0 2006.245.08:08:14.40#ibcon#about to read 6, iclass 19, count 0 2006.245.08:08:14.40#ibcon#read 6, iclass 19, count 0 2006.245.08:08:14.40#ibcon#end of sib2, iclass 19, count 0 2006.245.08:08:14.40#ibcon#*after write, iclass 19, count 0 2006.245.08:08:14.40#ibcon#*before return 0, iclass 19, count 0 2006.245.08:08:14.40#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:14.40#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:08:14.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:08:14.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:08:14.40$vc4f8/vblo=6,752.99 2006.245.08:08:14.40#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:08:14.40#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:08:14.40#ibcon#ireg 17 cls_cnt 0 2006.245.08:08:14.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:08:14.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:08:14.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:08:14.40#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:08:14.40#ibcon#first serial, iclass 24, count 0 2006.245.08:08:14.40#ibcon#enter sib2, iclass 24, count 0 2006.245.08:08:14.40#ibcon#flushed, iclass 24, count 0 2006.245.08:08:14.40#ibcon#about to write, iclass 24, count 0 2006.245.08:08:14.40#ibcon#wrote, iclass 24, count 0 2006.245.08:08:14.40#ibcon#about to read 3, iclass 24, count 0 2006.245.08:08:14.42#ibcon#read 3, iclass 24, count 0 2006.245.08:08:14.42#ibcon#about to read 4, iclass 24, count 0 2006.245.08:08:14.42#ibcon#read 4, iclass 24, count 0 2006.245.08:08:14.42#ibcon#about to read 5, iclass 24, count 0 2006.245.08:08:14.42#ibcon#read 5, iclass 24, count 0 2006.245.08:08:14.42#ibcon#about to read 6, iclass 24, count 0 2006.245.08:08:14.42#ibcon#read 6, iclass 24, count 0 2006.245.08:08:14.42#ibcon#end of sib2, iclass 24, count 0 2006.245.08:08:14.42#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:08:14.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:08:14.42#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:08:14.42#ibcon#*before write, iclass 24, count 0 2006.245.08:08:14.42#ibcon#enter sib2, iclass 24, count 0 2006.245.08:08:14.42#ibcon#flushed, iclass 24, count 0 2006.245.08:08:14.42#ibcon#about to write, iclass 24, count 0 2006.245.08:08:14.42#ibcon#wrote, iclass 24, count 0 2006.245.08:08:14.42#ibcon#about to read 3, iclass 24, count 0 2006.245.08:08:14.46#abcon#[5=S1D000X0/0*\r\n] 2006.245.08:08:14.46#ibcon#read 3, iclass 24, count 0 2006.245.08:08:14.46#ibcon#about to read 4, iclass 24, count 0 2006.245.08:08:14.46#ibcon#read 4, iclass 24, count 0 2006.245.08:08:14.46#ibcon#about to read 5, iclass 24, count 0 2006.245.08:08:14.46#ibcon#read 5, iclass 24, count 0 2006.245.08:08:14.46#ibcon#about to read 6, iclass 24, count 0 2006.245.08:08:14.46#ibcon#read 6, iclass 24, count 0 2006.245.08:08:14.46#ibcon#end of sib2, iclass 24, count 0 2006.245.08:08:14.46#ibcon#*after write, iclass 24, count 0 2006.245.08:08:14.46#ibcon#*before return 0, iclass 24, count 0 2006.245.08:08:14.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:08:14.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:08:14.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:08:14.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:08:14.46$vc4f8/vb=6,3 2006.245.08:08:14.46#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.08:08:14.46#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.08:08:14.46#ibcon#ireg 11 cls_cnt 2 2006.245.08:08:14.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:14.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:14.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:14.52#ibcon#enter wrdev, iclass 27, count 2 2006.245.08:08:14.52#ibcon#first serial, iclass 27, count 2 2006.245.08:08:14.52#ibcon#enter sib2, iclass 27, count 2 2006.245.08:08:14.52#ibcon#flushed, iclass 27, count 2 2006.245.08:08:14.52#ibcon#about to write, iclass 27, count 2 2006.245.08:08:14.52#ibcon#wrote, iclass 27, count 2 2006.245.08:08:14.52#ibcon#about to read 3, iclass 27, count 2 2006.245.08:08:14.54#ibcon#read 3, iclass 27, count 2 2006.245.08:08:14.54#ibcon#about to read 4, iclass 27, count 2 2006.245.08:08:14.54#ibcon#read 4, iclass 27, count 2 2006.245.08:08:14.54#ibcon#about to read 5, iclass 27, count 2 2006.245.08:08:14.54#ibcon#read 5, iclass 27, count 2 2006.245.08:08:14.54#ibcon#about to read 6, iclass 27, count 2 2006.245.08:08:14.54#ibcon#read 6, iclass 27, count 2 2006.245.08:08:14.54#ibcon#end of sib2, iclass 27, count 2 2006.245.08:08:14.54#ibcon#*mode == 0, iclass 27, count 2 2006.245.08:08:14.54#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.08:08:14.54#ibcon#[27=AT06-03\r\n] 2006.245.08:08:14.54#ibcon#*before write, iclass 27, count 2 2006.245.08:08:14.54#ibcon#enter sib2, iclass 27, count 2 2006.245.08:08:14.54#ibcon#flushed, iclass 27, count 2 2006.245.08:08:14.54#ibcon#about to write, iclass 27, count 2 2006.245.08:08:14.54#ibcon#wrote, iclass 27, count 2 2006.245.08:08:14.54#ibcon#about to read 3, iclass 27, count 2 2006.245.08:08:14.57#ibcon#read 3, iclass 27, count 2 2006.245.08:08:14.57#ibcon#about to read 4, iclass 27, count 2 2006.245.08:08:14.57#ibcon#read 4, iclass 27, count 2 2006.245.08:08:14.57#ibcon#about to read 5, iclass 27, count 2 2006.245.08:08:14.57#ibcon#read 5, iclass 27, count 2 2006.245.08:08:14.57#ibcon#about to read 6, iclass 27, count 2 2006.245.08:08:14.57#ibcon#read 6, iclass 27, count 2 2006.245.08:08:14.57#ibcon#end of sib2, iclass 27, count 2 2006.245.08:08:14.57#ibcon#*after write, iclass 27, count 2 2006.245.08:08:14.57#ibcon#*before return 0, iclass 27, count 2 2006.245.08:08:14.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:14.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:08:14.57#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.08:08:14.57#ibcon#ireg 7 cls_cnt 0 2006.245.08:08:14.57#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:14.69#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:14.69#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:14.69#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:08:14.69#ibcon#first serial, iclass 27, count 0 2006.245.08:08:14.69#ibcon#enter sib2, iclass 27, count 0 2006.245.08:08:14.69#ibcon#flushed, iclass 27, count 0 2006.245.08:08:14.69#ibcon#about to write, iclass 27, count 0 2006.245.08:08:14.69#ibcon#wrote, iclass 27, count 0 2006.245.08:08:14.69#ibcon#about to read 3, iclass 27, count 0 2006.245.08:08:14.71#ibcon#read 3, iclass 27, count 0 2006.245.08:08:14.71#ibcon#about to read 4, iclass 27, count 0 2006.245.08:08:14.71#ibcon#read 4, iclass 27, count 0 2006.245.08:08:14.71#ibcon#about to read 5, iclass 27, count 0 2006.245.08:08:14.71#ibcon#read 5, iclass 27, count 0 2006.245.08:08:14.71#ibcon#about to read 6, iclass 27, count 0 2006.245.08:08:14.71#ibcon#read 6, iclass 27, count 0 2006.245.08:08:14.71#ibcon#end of sib2, iclass 27, count 0 2006.245.08:08:14.71#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:08:14.71#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:08:14.71#ibcon#[27=USB\r\n] 2006.245.08:08:14.71#ibcon#*before write, iclass 27, count 0 2006.245.08:08:14.71#ibcon#enter sib2, iclass 27, count 0 2006.245.08:08:14.71#ibcon#flushed, iclass 27, count 0 2006.245.08:08:14.71#ibcon#about to write, iclass 27, count 0 2006.245.08:08:14.71#ibcon#wrote, iclass 27, count 0 2006.245.08:08:14.71#ibcon#about to read 3, iclass 27, count 0 2006.245.08:08:14.74#ibcon#read 3, iclass 27, count 0 2006.245.08:08:14.74#ibcon#about to read 4, iclass 27, count 0 2006.245.08:08:14.74#ibcon#read 4, iclass 27, count 0 2006.245.08:08:14.74#ibcon#about to read 5, iclass 27, count 0 2006.245.08:08:14.74#ibcon#read 5, iclass 27, count 0 2006.245.08:08:14.74#ibcon#about to read 6, iclass 27, count 0 2006.245.08:08:14.74#ibcon#read 6, iclass 27, count 0 2006.245.08:08:14.74#ibcon#end of sib2, iclass 27, count 0 2006.245.08:08:14.74#ibcon#*after write, iclass 27, count 0 2006.245.08:08:14.74#ibcon#*before return 0, iclass 27, count 0 2006.245.08:08:14.74#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:14.74#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:08:14.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:08:14.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:08:14.74$vc4f8/vabw=wide 2006.245.08:08:14.74#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.08:08:14.74#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.08:08:14.74#ibcon#ireg 8 cls_cnt 0 2006.245.08:08:14.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:14.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:14.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:14.74#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:08:14.74#ibcon#first serial, iclass 29, count 0 2006.245.08:08:14.74#ibcon#enter sib2, iclass 29, count 0 2006.245.08:08:14.74#ibcon#flushed, iclass 29, count 0 2006.245.08:08:14.74#ibcon#about to write, iclass 29, count 0 2006.245.08:08:14.74#ibcon#wrote, iclass 29, count 0 2006.245.08:08:14.74#ibcon#about to read 3, iclass 29, count 0 2006.245.08:08:14.76#ibcon#read 3, iclass 29, count 0 2006.245.08:08:14.76#ibcon#about to read 4, iclass 29, count 0 2006.245.08:08:14.76#ibcon#read 4, iclass 29, count 0 2006.245.08:08:14.76#ibcon#about to read 5, iclass 29, count 0 2006.245.08:08:14.76#ibcon#read 5, iclass 29, count 0 2006.245.08:08:14.76#ibcon#about to read 6, iclass 29, count 0 2006.245.08:08:14.76#ibcon#read 6, iclass 29, count 0 2006.245.08:08:14.76#ibcon#end of sib2, iclass 29, count 0 2006.245.08:08:14.76#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:08:14.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:08:14.76#ibcon#[25=BW32\r\n] 2006.245.08:08:14.76#ibcon#*before write, iclass 29, count 0 2006.245.08:08:14.76#ibcon#enter sib2, iclass 29, count 0 2006.245.08:08:14.76#ibcon#flushed, iclass 29, count 0 2006.245.08:08:14.76#ibcon#about to write, iclass 29, count 0 2006.245.08:08:14.76#ibcon#wrote, iclass 29, count 0 2006.245.08:08:14.76#ibcon#about to read 3, iclass 29, count 0 2006.245.08:08:14.79#ibcon#read 3, iclass 29, count 0 2006.245.08:08:14.79#ibcon#about to read 4, iclass 29, count 0 2006.245.08:08:14.79#ibcon#read 4, iclass 29, count 0 2006.245.08:08:14.79#ibcon#about to read 5, iclass 29, count 0 2006.245.08:08:14.79#ibcon#read 5, iclass 29, count 0 2006.245.08:08:14.79#ibcon#about to read 6, iclass 29, count 0 2006.245.08:08:14.79#ibcon#read 6, iclass 29, count 0 2006.245.08:08:14.79#ibcon#end of sib2, iclass 29, count 0 2006.245.08:08:14.79#ibcon#*after write, iclass 29, count 0 2006.245.08:08:14.79#ibcon#*before return 0, iclass 29, count 0 2006.245.08:08:14.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:14.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:08:14.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:08:14.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:08:14.79$vc4f8/vbbw=wide 2006.245.08:08:14.79#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.08:08:14.79#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.08:08:14.79#ibcon#ireg 8 cls_cnt 0 2006.245.08:08:14.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:08:14.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:08:14.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:08:14.87#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:08:14.87#ibcon#first serial, iclass 31, count 0 2006.245.08:08:14.87#ibcon#enter sib2, iclass 31, count 0 2006.245.08:08:14.87#ibcon#flushed, iclass 31, count 0 2006.245.08:08:14.87#ibcon#about to write, iclass 31, count 0 2006.245.08:08:14.87#ibcon#wrote, iclass 31, count 0 2006.245.08:08:14.87#ibcon#about to read 3, iclass 31, count 0 2006.245.08:08:14.88#ibcon#read 3, iclass 31, count 0 2006.245.08:08:14.88#ibcon#about to read 4, iclass 31, count 0 2006.245.08:08:14.88#ibcon#read 4, iclass 31, count 0 2006.245.08:08:14.88#ibcon#about to read 5, iclass 31, count 0 2006.245.08:08:14.88#ibcon#read 5, iclass 31, count 0 2006.245.08:08:14.88#ibcon#about to read 6, iclass 31, count 0 2006.245.08:08:14.88#ibcon#read 6, iclass 31, count 0 2006.245.08:08:14.88#ibcon#end of sib2, iclass 31, count 0 2006.245.08:08:14.88#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:08:14.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:08:14.88#ibcon#[27=BW32\r\n] 2006.245.08:08:14.88#ibcon#*before write, iclass 31, count 0 2006.245.08:08:14.88#ibcon#enter sib2, iclass 31, count 0 2006.245.08:08:14.88#ibcon#flushed, iclass 31, count 0 2006.245.08:08:14.88#ibcon#about to write, iclass 31, count 0 2006.245.08:08:14.88#ibcon#wrote, iclass 31, count 0 2006.245.08:08:14.88#ibcon#about to read 3, iclass 31, count 0 2006.245.08:08:14.91#ibcon#read 3, iclass 31, count 0 2006.245.08:08:14.91#ibcon#about to read 4, iclass 31, count 0 2006.245.08:08:14.91#ibcon#read 4, iclass 31, count 0 2006.245.08:08:14.91#ibcon#about to read 5, iclass 31, count 0 2006.245.08:08:14.91#ibcon#read 5, iclass 31, count 0 2006.245.08:08:14.91#ibcon#about to read 6, iclass 31, count 0 2006.245.08:08:14.91#ibcon#read 6, iclass 31, count 0 2006.245.08:08:14.91#ibcon#end of sib2, iclass 31, count 0 2006.245.08:08:14.91#ibcon#*after write, iclass 31, count 0 2006.245.08:08:14.91#ibcon#*before return 0, iclass 31, count 0 2006.245.08:08:14.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:08:14.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:08:14.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:08:14.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:08:14.91$4f8m12a/ifd4f 2006.245.08:08:14.91$ifd4f/lo= 2006.245.08:08:14.91$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:08:14.91$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:08:14.91$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:08:14.91$ifd4f/patch= 2006.245.08:08:14.91$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:08:14.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:08:14.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:08:14.91$4f8m12a/"form=m,16.000,1:2 2006.245.08:08:14.91$4f8m12a/"tpicd 2006.245.08:08:14.91$4f8m12a/echo=off 2006.245.08:08:14.91$4f8m12a/xlog=off 2006.245.08:08:14.91:!2006.245.08:09:00 2006.245.08:08:37.14#trakl#Source acquired 2006.245.08:08:39.14#flagr#flagr/antenna,acquired 2006.245.08:09:00.00:preob 2006.245.08:09:01.14/onsource/TRACKING 2006.245.08:09:01.14:!2006.245.08:09:10 2006.245.08:09:10.00:data_valid=on 2006.245.08:09:10.00:midob 2006.245.08:09:10.14/onsource/TRACKING 2006.245.08:09:10.14/wx/26.98,1004.5,73 2006.245.08:09:10.26/cable/+6.4099E-03 2006.245.08:09:11.35/va/01,08,usb,yes,31,33 2006.245.08:09:11.35/va/02,07,usb,yes,31,32 2006.245.08:09:11.35/va/03,06,usb,yes,33,33 2006.245.08:09:11.35/va/04,07,usb,yes,32,35 2006.245.08:09:11.35/va/05,07,usb,yes,34,36 2006.245.08:09:11.35/va/06,07,usb,yes,29,29 2006.245.08:09:11.35/va/07,07,usb,yes,29,29 2006.245.08:09:11.35/va/08,08,usb,yes,26,25 2006.245.08:09:11.58/valo/01,532.99,yes,locked 2006.245.08:09:11.58/valo/02,572.99,yes,locked 2006.245.08:09:11.58/valo/03,672.99,yes,locked 2006.245.08:09:11.58/valo/04,832.99,yes,locked 2006.245.08:09:11.58/valo/05,652.99,yes,locked 2006.245.08:09:11.58/valo/06,772.99,yes,locked 2006.245.08:09:11.58/valo/07,832.99,yes,locked 2006.245.08:09:11.58/valo/08,852.99,yes,locked 2006.245.08:09:12.67/vb/01,04,usb,yes,31,29 2006.245.08:09:12.67/vb/02,04,usb,yes,32,34 2006.245.08:09:12.67/vb/03,04,usb,yes,29,32 2006.245.08:09:12.67/vb/04,04,usb,yes,30,30 2006.245.08:09:12.67/vb/05,03,usb,yes,35,40 2006.245.08:09:12.67/vb/06,03,usb,yes,36,39 2006.245.08:09:12.67/vb/07,04,usb,yes,31,31 2006.245.08:09:12.67/vb/08,03,usb,yes,36,39 2006.245.08:09:12.90/vblo/01,632.99,yes,locked 2006.245.08:09:12.90/vblo/02,640.99,yes,locked 2006.245.08:09:12.90/vblo/03,656.99,yes,locked 2006.245.08:09:12.90/vblo/04,712.99,yes,locked 2006.245.08:09:12.90/vblo/05,744.99,yes,locked 2006.245.08:09:12.90/vblo/06,752.99,yes,locked 2006.245.08:09:12.90/vblo/07,734.99,yes,locked 2006.245.08:09:12.90/vblo/08,744.99,yes,locked 2006.245.08:09:13.05/vabw/8 2006.245.08:09:13.20/vbbw/8 2006.245.08:09:13.29/xfe/off,on,13.2 2006.245.08:09:13.66/ifatt/23,28,28,28 2006.245.08:09:14.08/fmout-gps/S +4.40E-07 2006.245.08:09:14.12:!2006.245.08:10:10 2006.245.08:10:10.00:data_valid=off 2006.245.08:10:10.00:postob 2006.245.08:10:10.10/cable/+6.4106E-03 2006.245.08:10:10.10/wx/26.96,1004.5,73 2006.245.08:10:11.07/fmout-gps/S +4.40E-07 2006.245.08:10:11.07:scan_name=245-0811,k06245,60 2006.245.08:10:11.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.245.08:10:11.14#flagr#flagr/antenna,new-source 2006.245.08:10:12.14:checkk5 2006.245.08:10:12.72/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:10:13.15/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:10:13.61/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:10:14.04/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:10:14.42/chk_obsdata//k5ts1/T2450809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:10:14.86/chk_obsdata//k5ts2/T2450809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:10:15.48/chk_obsdata//k5ts3/T2450809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:10:15.93/chk_obsdata//k5ts4/T2450809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:10:16.85/k5log//k5ts1_log_newline 2006.245.08:10:17.65/k5log//k5ts2_log_newline 2006.245.08:10:18.50/k5log//k5ts3_log_newline 2006.245.08:10:19.61/k5log//k5ts4_log_newline 2006.245.08:10:19.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:10:19.63:4f8m12a=2 2006.245.08:10:19.63$4f8m12a/echo=on 2006.245.08:10:19.63$4f8m12a/pcalon 2006.245.08:10:19.63$pcalon/"no phase cal control is implemented here 2006.245.08:10:19.63$4f8m12a/"tpicd=stop 2006.245.08:10:19.63$4f8m12a/vc4f8 2006.245.08:10:19.63$vc4f8/valo=1,532.99 2006.245.08:10:19.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.08:10:19.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.08:10:19.63#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:19.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:19.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:19.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:19.63#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:10:19.63#ibcon#first serial, iclass 10, count 0 2006.245.08:10:19.63#ibcon#enter sib2, iclass 10, count 0 2006.245.08:10:19.63#ibcon#flushed, iclass 10, count 0 2006.245.08:10:19.63#ibcon#about to write, iclass 10, count 0 2006.245.08:10:19.63#ibcon#wrote, iclass 10, count 0 2006.245.08:10:19.63#ibcon#about to read 3, iclass 10, count 0 2006.245.08:10:19.68#ibcon#read 3, iclass 10, count 0 2006.245.08:10:19.68#ibcon#about to read 4, iclass 10, count 0 2006.245.08:10:19.68#ibcon#read 4, iclass 10, count 0 2006.245.08:10:19.68#ibcon#about to read 5, iclass 10, count 0 2006.245.08:10:19.68#ibcon#read 5, iclass 10, count 0 2006.245.08:10:19.68#ibcon#about to read 6, iclass 10, count 0 2006.245.08:10:19.68#ibcon#read 6, iclass 10, count 0 2006.245.08:10:19.68#ibcon#end of sib2, iclass 10, count 0 2006.245.08:10:19.68#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:10:19.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:10:19.68#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:10:19.68#ibcon#*before write, iclass 10, count 0 2006.245.08:10:19.68#ibcon#enter sib2, iclass 10, count 0 2006.245.08:10:19.68#ibcon#flushed, iclass 10, count 0 2006.245.08:10:19.68#ibcon#about to write, iclass 10, count 0 2006.245.08:10:19.68#ibcon#wrote, iclass 10, count 0 2006.245.08:10:19.68#ibcon#about to read 3, iclass 10, count 0 2006.245.08:10:19.72#ibcon#read 3, iclass 10, count 0 2006.245.08:10:19.72#ibcon#about to read 4, iclass 10, count 0 2006.245.08:10:19.72#ibcon#read 4, iclass 10, count 0 2006.245.08:10:19.72#ibcon#about to read 5, iclass 10, count 0 2006.245.08:10:19.72#ibcon#read 5, iclass 10, count 0 2006.245.08:10:19.72#ibcon#about to read 6, iclass 10, count 0 2006.245.08:10:19.72#ibcon#read 6, iclass 10, count 0 2006.245.08:10:19.72#ibcon#end of sib2, iclass 10, count 0 2006.245.08:10:19.72#ibcon#*after write, iclass 10, count 0 2006.245.08:10:19.72#ibcon#*before return 0, iclass 10, count 0 2006.245.08:10:19.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:19.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:19.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:10:19.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:10:19.72$vc4f8/va=1,8 2006.245.08:10:19.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.08:10:19.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.08:10:19.72#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:19.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:19.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:19.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:19.72#ibcon#enter wrdev, iclass 12, count 2 2006.245.08:10:19.72#ibcon#first serial, iclass 12, count 2 2006.245.08:10:19.72#ibcon#enter sib2, iclass 12, count 2 2006.245.08:10:19.72#ibcon#flushed, iclass 12, count 2 2006.245.08:10:19.72#ibcon#about to write, iclass 12, count 2 2006.245.08:10:19.72#ibcon#wrote, iclass 12, count 2 2006.245.08:10:19.72#ibcon#about to read 3, iclass 12, count 2 2006.245.08:10:19.74#ibcon#read 3, iclass 12, count 2 2006.245.08:10:19.74#ibcon#about to read 4, iclass 12, count 2 2006.245.08:10:19.74#ibcon#read 4, iclass 12, count 2 2006.245.08:10:19.74#ibcon#about to read 5, iclass 12, count 2 2006.245.08:10:19.74#ibcon#read 5, iclass 12, count 2 2006.245.08:10:19.74#ibcon#about to read 6, iclass 12, count 2 2006.245.08:10:19.74#ibcon#read 6, iclass 12, count 2 2006.245.08:10:19.74#ibcon#end of sib2, iclass 12, count 2 2006.245.08:10:19.74#ibcon#*mode == 0, iclass 12, count 2 2006.245.08:10:19.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.08:10:19.74#ibcon#[25=AT01-08\r\n] 2006.245.08:10:19.74#ibcon#*before write, iclass 12, count 2 2006.245.08:10:19.74#ibcon#enter sib2, iclass 12, count 2 2006.245.08:10:19.74#ibcon#flushed, iclass 12, count 2 2006.245.08:10:19.74#ibcon#about to write, iclass 12, count 2 2006.245.08:10:19.74#ibcon#wrote, iclass 12, count 2 2006.245.08:10:19.74#ibcon#about to read 3, iclass 12, count 2 2006.245.08:10:19.77#ibcon#read 3, iclass 12, count 2 2006.245.08:10:19.77#ibcon#about to read 4, iclass 12, count 2 2006.245.08:10:19.77#ibcon#read 4, iclass 12, count 2 2006.245.08:10:19.77#ibcon#about to read 5, iclass 12, count 2 2006.245.08:10:19.77#ibcon#read 5, iclass 12, count 2 2006.245.08:10:19.77#ibcon#about to read 6, iclass 12, count 2 2006.245.08:10:19.77#ibcon#read 6, iclass 12, count 2 2006.245.08:10:19.77#ibcon#end of sib2, iclass 12, count 2 2006.245.08:10:19.77#ibcon#*after write, iclass 12, count 2 2006.245.08:10:19.77#ibcon#*before return 0, iclass 12, count 2 2006.245.08:10:19.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:19.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:19.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.08:10:19.77#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:19.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:19.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:19.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:19.89#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:10:19.89#ibcon#first serial, iclass 12, count 0 2006.245.08:10:19.89#ibcon#enter sib2, iclass 12, count 0 2006.245.08:10:19.89#ibcon#flushed, iclass 12, count 0 2006.245.08:10:19.89#ibcon#about to write, iclass 12, count 0 2006.245.08:10:19.89#ibcon#wrote, iclass 12, count 0 2006.245.08:10:19.89#ibcon#about to read 3, iclass 12, count 0 2006.245.08:10:19.91#ibcon#read 3, iclass 12, count 0 2006.245.08:10:19.91#ibcon#about to read 4, iclass 12, count 0 2006.245.08:10:19.91#ibcon#read 4, iclass 12, count 0 2006.245.08:10:19.91#ibcon#about to read 5, iclass 12, count 0 2006.245.08:10:19.91#ibcon#read 5, iclass 12, count 0 2006.245.08:10:19.91#ibcon#about to read 6, iclass 12, count 0 2006.245.08:10:19.91#ibcon#read 6, iclass 12, count 0 2006.245.08:10:19.91#ibcon#end of sib2, iclass 12, count 0 2006.245.08:10:19.91#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:10:19.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:10:19.91#ibcon#[25=USB\r\n] 2006.245.08:10:19.91#ibcon#*before write, iclass 12, count 0 2006.245.08:10:19.91#ibcon#enter sib2, iclass 12, count 0 2006.245.08:10:19.91#ibcon#flushed, iclass 12, count 0 2006.245.08:10:19.91#ibcon#about to write, iclass 12, count 0 2006.245.08:10:19.91#ibcon#wrote, iclass 12, count 0 2006.245.08:10:19.91#ibcon#about to read 3, iclass 12, count 0 2006.245.08:10:19.94#ibcon#read 3, iclass 12, count 0 2006.245.08:10:19.94#ibcon#about to read 4, iclass 12, count 0 2006.245.08:10:19.94#ibcon#read 4, iclass 12, count 0 2006.245.08:10:19.94#ibcon#about to read 5, iclass 12, count 0 2006.245.08:10:19.94#ibcon#read 5, iclass 12, count 0 2006.245.08:10:19.94#ibcon#about to read 6, iclass 12, count 0 2006.245.08:10:19.94#ibcon#read 6, iclass 12, count 0 2006.245.08:10:19.94#ibcon#end of sib2, iclass 12, count 0 2006.245.08:10:19.94#ibcon#*after write, iclass 12, count 0 2006.245.08:10:19.94#ibcon#*before return 0, iclass 12, count 0 2006.245.08:10:19.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:19.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:19.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:10:19.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:10:19.94$vc4f8/valo=2,572.99 2006.245.08:10:19.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.08:10:19.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.08:10:19.94#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:19.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:19.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:19.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:19.94#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:10:19.94#ibcon#first serial, iclass 14, count 0 2006.245.08:10:19.94#ibcon#enter sib2, iclass 14, count 0 2006.245.08:10:19.94#ibcon#flushed, iclass 14, count 0 2006.245.08:10:19.94#ibcon#about to write, iclass 14, count 0 2006.245.08:10:19.94#ibcon#wrote, iclass 14, count 0 2006.245.08:10:19.94#ibcon#about to read 3, iclass 14, count 0 2006.245.08:10:19.97#ibcon#read 3, iclass 14, count 0 2006.245.08:10:19.97#ibcon#about to read 4, iclass 14, count 0 2006.245.08:10:19.97#ibcon#read 4, iclass 14, count 0 2006.245.08:10:19.97#ibcon#about to read 5, iclass 14, count 0 2006.245.08:10:19.97#ibcon#read 5, iclass 14, count 0 2006.245.08:10:19.97#ibcon#about to read 6, iclass 14, count 0 2006.245.08:10:19.97#ibcon#read 6, iclass 14, count 0 2006.245.08:10:19.97#ibcon#end of sib2, iclass 14, count 0 2006.245.08:10:19.97#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:10:19.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:10:19.97#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:10:19.97#ibcon#*before write, iclass 14, count 0 2006.245.08:10:19.97#ibcon#enter sib2, iclass 14, count 0 2006.245.08:10:19.97#ibcon#flushed, iclass 14, count 0 2006.245.08:10:19.97#ibcon#about to write, iclass 14, count 0 2006.245.08:10:19.97#ibcon#wrote, iclass 14, count 0 2006.245.08:10:19.97#ibcon#about to read 3, iclass 14, count 0 2006.245.08:10:20.01#ibcon#read 3, iclass 14, count 0 2006.245.08:10:20.01#ibcon#about to read 4, iclass 14, count 0 2006.245.08:10:20.01#ibcon#read 4, iclass 14, count 0 2006.245.08:10:20.01#ibcon#about to read 5, iclass 14, count 0 2006.245.08:10:20.01#ibcon#read 5, iclass 14, count 0 2006.245.08:10:20.01#ibcon#about to read 6, iclass 14, count 0 2006.245.08:10:20.01#ibcon#read 6, iclass 14, count 0 2006.245.08:10:20.01#ibcon#end of sib2, iclass 14, count 0 2006.245.08:10:20.01#ibcon#*after write, iclass 14, count 0 2006.245.08:10:20.01#ibcon#*before return 0, iclass 14, count 0 2006.245.08:10:20.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:20.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:20.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:10:20.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:10:20.01$vc4f8/va=2,7 2006.245.08:10:20.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:10:20.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:10:20.01#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:20.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:20.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:20.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:20.06#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:10:20.06#ibcon#first serial, iclass 16, count 2 2006.245.08:10:20.06#ibcon#enter sib2, iclass 16, count 2 2006.245.08:10:20.06#ibcon#flushed, iclass 16, count 2 2006.245.08:10:20.06#ibcon#about to write, iclass 16, count 2 2006.245.08:10:20.06#ibcon#wrote, iclass 16, count 2 2006.245.08:10:20.06#ibcon#about to read 3, iclass 16, count 2 2006.245.08:10:20.08#ibcon#read 3, iclass 16, count 2 2006.245.08:10:20.08#ibcon#about to read 4, iclass 16, count 2 2006.245.08:10:20.08#ibcon#read 4, iclass 16, count 2 2006.245.08:10:20.08#ibcon#about to read 5, iclass 16, count 2 2006.245.08:10:20.08#ibcon#read 5, iclass 16, count 2 2006.245.08:10:20.08#ibcon#about to read 6, iclass 16, count 2 2006.245.08:10:20.08#ibcon#read 6, iclass 16, count 2 2006.245.08:10:20.08#ibcon#end of sib2, iclass 16, count 2 2006.245.08:10:20.08#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:10:20.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:10:20.08#ibcon#[25=AT02-07\r\n] 2006.245.08:10:20.08#ibcon#*before write, iclass 16, count 2 2006.245.08:10:20.08#ibcon#enter sib2, iclass 16, count 2 2006.245.08:10:20.08#ibcon#flushed, iclass 16, count 2 2006.245.08:10:20.08#ibcon#about to write, iclass 16, count 2 2006.245.08:10:20.08#ibcon#wrote, iclass 16, count 2 2006.245.08:10:20.08#ibcon#about to read 3, iclass 16, count 2 2006.245.08:10:20.11#ibcon#read 3, iclass 16, count 2 2006.245.08:10:20.11#ibcon#about to read 4, iclass 16, count 2 2006.245.08:10:20.11#ibcon#read 4, iclass 16, count 2 2006.245.08:10:20.11#ibcon#about to read 5, iclass 16, count 2 2006.245.08:10:20.11#ibcon#read 5, iclass 16, count 2 2006.245.08:10:20.11#ibcon#about to read 6, iclass 16, count 2 2006.245.08:10:20.11#ibcon#read 6, iclass 16, count 2 2006.245.08:10:20.11#ibcon#end of sib2, iclass 16, count 2 2006.245.08:10:20.11#ibcon#*after write, iclass 16, count 2 2006.245.08:10:20.11#ibcon#*before return 0, iclass 16, count 2 2006.245.08:10:20.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:20.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:20.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:10:20.11#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:20.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:20.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:20.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:20.23#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:10:20.23#ibcon#first serial, iclass 16, count 0 2006.245.08:10:20.23#ibcon#enter sib2, iclass 16, count 0 2006.245.08:10:20.23#ibcon#flushed, iclass 16, count 0 2006.245.08:10:20.23#ibcon#about to write, iclass 16, count 0 2006.245.08:10:20.23#ibcon#wrote, iclass 16, count 0 2006.245.08:10:20.23#ibcon#about to read 3, iclass 16, count 0 2006.245.08:10:20.25#ibcon#read 3, iclass 16, count 0 2006.245.08:10:20.25#ibcon#about to read 4, iclass 16, count 0 2006.245.08:10:20.25#ibcon#read 4, iclass 16, count 0 2006.245.08:10:20.25#ibcon#about to read 5, iclass 16, count 0 2006.245.08:10:20.25#ibcon#read 5, iclass 16, count 0 2006.245.08:10:20.25#ibcon#about to read 6, iclass 16, count 0 2006.245.08:10:20.25#ibcon#read 6, iclass 16, count 0 2006.245.08:10:20.25#ibcon#end of sib2, iclass 16, count 0 2006.245.08:10:20.25#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:10:20.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:10:20.25#ibcon#[25=USB\r\n] 2006.245.08:10:20.25#ibcon#*before write, iclass 16, count 0 2006.245.08:10:20.25#ibcon#enter sib2, iclass 16, count 0 2006.245.08:10:20.25#ibcon#flushed, iclass 16, count 0 2006.245.08:10:20.25#ibcon#about to write, iclass 16, count 0 2006.245.08:10:20.25#ibcon#wrote, iclass 16, count 0 2006.245.08:10:20.25#ibcon#about to read 3, iclass 16, count 0 2006.245.08:10:20.28#ibcon#read 3, iclass 16, count 0 2006.245.08:10:20.28#ibcon#about to read 4, iclass 16, count 0 2006.245.08:10:20.28#ibcon#read 4, iclass 16, count 0 2006.245.08:10:20.28#ibcon#about to read 5, iclass 16, count 0 2006.245.08:10:20.28#ibcon#read 5, iclass 16, count 0 2006.245.08:10:20.28#ibcon#about to read 6, iclass 16, count 0 2006.245.08:10:20.28#ibcon#read 6, iclass 16, count 0 2006.245.08:10:20.28#ibcon#end of sib2, iclass 16, count 0 2006.245.08:10:20.28#ibcon#*after write, iclass 16, count 0 2006.245.08:10:20.28#ibcon#*before return 0, iclass 16, count 0 2006.245.08:10:20.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:20.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:20.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:10:20.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:10:20.28$vc4f8/valo=3,672.99 2006.245.08:10:20.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.08:10:20.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.08:10:20.28#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:20.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:20.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:20.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:20.28#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:10:20.28#ibcon#first serial, iclass 18, count 0 2006.245.08:10:20.28#ibcon#enter sib2, iclass 18, count 0 2006.245.08:10:20.28#ibcon#flushed, iclass 18, count 0 2006.245.08:10:20.28#ibcon#about to write, iclass 18, count 0 2006.245.08:10:20.28#ibcon#wrote, iclass 18, count 0 2006.245.08:10:20.28#ibcon#about to read 3, iclass 18, count 0 2006.245.08:10:20.31#ibcon#read 3, iclass 18, count 0 2006.245.08:10:20.31#ibcon#about to read 4, iclass 18, count 0 2006.245.08:10:20.31#ibcon#read 4, iclass 18, count 0 2006.245.08:10:20.31#ibcon#about to read 5, iclass 18, count 0 2006.245.08:10:20.31#ibcon#read 5, iclass 18, count 0 2006.245.08:10:20.31#ibcon#about to read 6, iclass 18, count 0 2006.245.08:10:20.31#ibcon#read 6, iclass 18, count 0 2006.245.08:10:20.31#ibcon#end of sib2, iclass 18, count 0 2006.245.08:10:20.31#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:10:20.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:10:20.31#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:10:20.31#ibcon#*before write, iclass 18, count 0 2006.245.08:10:20.31#ibcon#enter sib2, iclass 18, count 0 2006.245.08:10:20.31#ibcon#flushed, iclass 18, count 0 2006.245.08:10:20.31#ibcon#about to write, iclass 18, count 0 2006.245.08:10:20.31#ibcon#wrote, iclass 18, count 0 2006.245.08:10:20.31#ibcon#about to read 3, iclass 18, count 0 2006.245.08:10:20.35#ibcon#read 3, iclass 18, count 0 2006.245.08:10:20.35#ibcon#about to read 4, iclass 18, count 0 2006.245.08:10:20.35#ibcon#read 4, iclass 18, count 0 2006.245.08:10:20.35#ibcon#about to read 5, iclass 18, count 0 2006.245.08:10:20.35#ibcon#read 5, iclass 18, count 0 2006.245.08:10:20.35#ibcon#about to read 6, iclass 18, count 0 2006.245.08:10:20.35#ibcon#read 6, iclass 18, count 0 2006.245.08:10:20.35#ibcon#end of sib2, iclass 18, count 0 2006.245.08:10:20.35#ibcon#*after write, iclass 18, count 0 2006.245.08:10:20.35#ibcon#*before return 0, iclass 18, count 0 2006.245.08:10:20.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:20.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:20.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:10:20.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:10:20.35$vc4f8/va=3,6 2006.245.08:10:20.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.08:10:20.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.08:10:20.35#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:20.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:20.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:20.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:20.40#ibcon#enter wrdev, iclass 20, count 2 2006.245.08:10:20.40#ibcon#first serial, iclass 20, count 2 2006.245.08:10:20.40#ibcon#enter sib2, iclass 20, count 2 2006.245.08:10:20.40#ibcon#flushed, iclass 20, count 2 2006.245.08:10:20.40#ibcon#about to write, iclass 20, count 2 2006.245.08:10:20.40#ibcon#wrote, iclass 20, count 2 2006.245.08:10:20.40#ibcon#about to read 3, iclass 20, count 2 2006.245.08:10:20.42#ibcon#read 3, iclass 20, count 2 2006.245.08:10:20.42#ibcon#about to read 4, iclass 20, count 2 2006.245.08:10:20.42#ibcon#read 4, iclass 20, count 2 2006.245.08:10:20.42#ibcon#about to read 5, iclass 20, count 2 2006.245.08:10:20.42#ibcon#read 5, iclass 20, count 2 2006.245.08:10:20.42#ibcon#about to read 6, iclass 20, count 2 2006.245.08:10:20.42#ibcon#read 6, iclass 20, count 2 2006.245.08:10:20.42#ibcon#end of sib2, iclass 20, count 2 2006.245.08:10:20.42#ibcon#*mode == 0, iclass 20, count 2 2006.245.08:10:20.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.08:10:20.42#ibcon#[25=AT03-06\r\n] 2006.245.08:10:20.42#ibcon#*before write, iclass 20, count 2 2006.245.08:10:20.42#ibcon#enter sib2, iclass 20, count 2 2006.245.08:10:20.42#ibcon#flushed, iclass 20, count 2 2006.245.08:10:20.42#ibcon#about to write, iclass 20, count 2 2006.245.08:10:20.42#ibcon#wrote, iclass 20, count 2 2006.245.08:10:20.42#ibcon#about to read 3, iclass 20, count 2 2006.245.08:10:20.45#ibcon#read 3, iclass 20, count 2 2006.245.08:10:20.45#ibcon#about to read 4, iclass 20, count 2 2006.245.08:10:20.45#ibcon#read 4, iclass 20, count 2 2006.245.08:10:20.45#ibcon#about to read 5, iclass 20, count 2 2006.245.08:10:20.45#ibcon#read 5, iclass 20, count 2 2006.245.08:10:20.45#ibcon#about to read 6, iclass 20, count 2 2006.245.08:10:20.45#ibcon#read 6, iclass 20, count 2 2006.245.08:10:20.45#ibcon#end of sib2, iclass 20, count 2 2006.245.08:10:20.45#ibcon#*after write, iclass 20, count 2 2006.245.08:10:20.45#ibcon#*before return 0, iclass 20, count 2 2006.245.08:10:20.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:20.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:20.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.08:10:20.45#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:20.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:20.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:20.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:20.57#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:10:20.57#ibcon#first serial, iclass 20, count 0 2006.245.08:10:20.57#ibcon#enter sib2, iclass 20, count 0 2006.245.08:10:20.57#ibcon#flushed, iclass 20, count 0 2006.245.08:10:20.57#ibcon#about to write, iclass 20, count 0 2006.245.08:10:20.57#ibcon#wrote, iclass 20, count 0 2006.245.08:10:20.57#ibcon#about to read 3, iclass 20, count 0 2006.245.08:10:20.59#ibcon#read 3, iclass 20, count 0 2006.245.08:10:20.59#ibcon#about to read 4, iclass 20, count 0 2006.245.08:10:20.59#ibcon#read 4, iclass 20, count 0 2006.245.08:10:20.59#ibcon#about to read 5, iclass 20, count 0 2006.245.08:10:20.59#ibcon#read 5, iclass 20, count 0 2006.245.08:10:20.59#ibcon#about to read 6, iclass 20, count 0 2006.245.08:10:20.59#ibcon#read 6, iclass 20, count 0 2006.245.08:10:20.59#ibcon#end of sib2, iclass 20, count 0 2006.245.08:10:20.59#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:10:20.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:10:20.59#ibcon#[25=USB\r\n] 2006.245.08:10:20.59#ibcon#*before write, iclass 20, count 0 2006.245.08:10:20.59#ibcon#enter sib2, iclass 20, count 0 2006.245.08:10:20.59#ibcon#flushed, iclass 20, count 0 2006.245.08:10:20.59#ibcon#about to write, iclass 20, count 0 2006.245.08:10:20.59#ibcon#wrote, iclass 20, count 0 2006.245.08:10:20.59#ibcon#about to read 3, iclass 20, count 0 2006.245.08:10:20.62#ibcon#read 3, iclass 20, count 0 2006.245.08:10:20.62#ibcon#about to read 4, iclass 20, count 0 2006.245.08:10:20.62#ibcon#read 4, iclass 20, count 0 2006.245.08:10:20.62#ibcon#about to read 5, iclass 20, count 0 2006.245.08:10:20.62#ibcon#read 5, iclass 20, count 0 2006.245.08:10:20.62#ibcon#about to read 6, iclass 20, count 0 2006.245.08:10:20.62#ibcon#read 6, iclass 20, count 0 2006.245.08:10:20.62#ibcon#end of sib2, iclass 20, count 0 2006.245.08:10:20.62#ibcon#*after write, iclass 20, count 0 2006.245.08:10:20.62#ibcon#*before return 0, iclass 20, count 0 2006.245.08:10:20.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:20.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:20.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:10:20.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:10:20.62$vc4f8/valo=4,832.99 2006.245.08:10:20.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:10:20.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:10:20.62#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:20.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:20.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:20.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:20.62#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:10:20.62#ibcon#first serial, iclass 22, count 0 2006.245.08:10:20.62#ibcon#enter sib2, iclass 22, count 0 2006.245.08:10:20.62#ibcon#flushed, iclass 22, count 0 2006.245.08:10:20.62#ibcon#about to write, iclass 22, count 0 2006.245.08:10:20.62#ibcon#wrote, iclass 22, count 0 2006.245.08:10:20.62#ibcon#about to read 3, iclass 22, count 0 2006.245.08:10:20.65#ibcon#read 3, iclass 22, count 0 2006.245.08:10:20.65#ibcon#about to read 4, iclass 22, count 0 2006.245.08:10:20.65#ibcon#read 4, iclass 22, count 0 2006.245.08:10:20.65#ibcon#about to read 5, iclass 22, count 0 2006.245.08:10:20.65#ibcon#read 5, iclass 22, count 0 2006.245.08:10:20.65#ibcon#about to read 6, iclass 22, count 0 2006.245.08:10:20.65#ibcon#read 6, iclass 22, count 0 2006.245.08:10:20.65#ibcon#end of sib2, iclass 22, count 0 2006.245.08:10:20.65#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:10:20.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:10:20.65#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:10:20.65#ibcon#*before write, iclass 22, count 0 2006.245.08:10:20.65#ibcon#enter sib2, iclass 22, count 0 2006.245.08:10:20.65#ibcon#flushed, iclass 22, count 0 2006.245.08:10:20.65#ibcon#about to write, iclass 22, count 0 2006.245.08:10:20.65#ibcon#wrote, iclass 22, count 0 2006.245.08:10:20.65#ibcon#about to read 3, iclass 22, count 0 2006.245.08:10:20.69#ibcon#read 3, iclass 22, count 0 2006.245.08:10:20.69#ibcon#about to read 4, iclass 22, count 0 2006.245.08:10:20.69#ibcon#read 4, iclass 22, count 0 2006.245.08:10:20.69#ibcon#about to read 5, iclass 22, count 0 2006.245.08:10:20.69#ibcon#read 5, iclass 22, count 0 2006.245.08:10:20.69#ibcon#about to read 6, iclass 22, count 0 2006.245.08:10:20.69#ibcon#read 6, iclass 22, count 0 2006.245.08:10:20.69#ibcon#end of sib2, iclass 22, count 0 2006.245.08:10:20.69#ibcon#*after write, iclass 22, count 0 2006.245.08:10:20.69#ibcon#*before return 0, iclass 22, count 0 2006.245.08:10:20.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:20.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:20.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:10:20.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:10:20.69$vc4f8/va=4,7 2006.245.08:10:20.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.08:10:20.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.08:10:20.69#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:20.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:20.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:20.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:20.74#ibcon#enter wrdev, iclass 24, count 2 2006.245.08:10:20.74#ibcon#first serial, iclass 24, count 2 2006.245.08:10:20.74#ibcon#enter sib2, iclass 24, count 2 2006.245.08:10:20.74#ibcon#flushed, iclass 24, count 2 2006.245.08:10:20.74#ibcon#about to write, iclass 24, count 2 2006.245.08:10:20.74#ibcon#wrote, iclass 24, count 2 2006.245.08:10:20.74#ibcon#about to read 3, iclass 24, count 2 2006.245.08:10:20.76#ibcon#read 3, iclass 24, count 2 2006.245.08:10:20.76#ibcon#about to read 4, iclass 24, count 2 2006.245.08:10:20.76#ibcon#read 4, iclass 24, count 2 2006.245.08:10:20.76#ibcon#about to read 5, iclass 24, count 2 2006.245.08:10:20.76#ibcon#read 5, iclass 24, count 2 2006.245.08:10:20.76#ibcon#about to read 6, iclass 24, count 2 2006.245.08:10:20.76#ibcon#read 6, iclass 24, count 2 2006.245.08:10:20.76#ibcon#end of sib2, iclass 24, count 2 2006.245.08:10:20.76#ibcon#*mode == 0, iclass 24, count 2 2006.245.08:10:20.76#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.08:10:20.76#ibcon#[25=AT04-07\r\n] 2006.245.08:10:20.76#ibcon#*before write, iclass 24, count 2 2006.245.08:10:20.76#ibcon#enter sib2, iclass 24, count 2 2006.245.08:10:20.76#ibcon#flushed, iclass 24, count 2 2006.245.08:10:20.76#ibcon#about to write, iclass 24, count 2 2006.245.08:10:20.76#ibcon#wrote, iclass 24, count 2 2006.245.08:10:20.76#ibcon#about to read 3, iclass 24, count 2 2006.245.08:10:20.79#ibcon#read 3, iclass 24, count 2 2006.245.08:10:20.79#ibcon#about to read 4, iclass 24, count 2 2006.245.08:10:20.79#ibcon#read 4, iclass 24, count 2 2006.245.08:10:20.79#ibcon#about to read 5, iclass 24, count 2 2006.245.08:10:20.79#ibcon#read 5, iclass 24, count 2 2006.245.08:10:20.79#ibcon#about to read 6, iclass 24, count 2 2006.245.08:10:20.79#ibcon#read 6, iclass 24, count 2 2006.245.08:10:20.79#ibcon#end of sib2, iclass 24, count 2 2006.245.08:10:20.79#ibcon#*after write, iclass 24, count 2 2006.245.08:10:20.79#ibcon#*before return 0, iclass 24, count 2 2006.245.08:10:20.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:20.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:20.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.08:10:20.79#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:20.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:20.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:20.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:20.91#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:10:20.91#ibcon#first serial, iclass 24, count 0 2006.245.08:10:20.91#ibcon#enter sib2, iclass 24, count 0 2006.245.08:10:20.91#ibcon#flushed, iclass 24, count 0 2006.245.08:10:20.91#ibcon#about to write, iclass 24, count 0 2006.245.08:10:20.91#ibcon#wrote, iclass 24, count 0 2006.245.08:10:20.91#ibcon#about to read 3, iclass 24, count 0 2006.245.08:10:20.93#ibcon#read 3, iclass 24, count 0 2006.245.08:10:20.93#ibcon#about to read 4, iclass 24, count 0 2006.245.08:10:20.93#ibcon#read 4, iclass 24, count 0 2006.245.08:10:20.93#ibcon#about to read 5, iclass 24, count 0 2006.245.08:10:20.93#ibcon#read 5, iclass 24, count 0 2006.245.08:10:20.93#ibcon#about to read 6, iclass 24, count 0 2006.245.08:10:20.93#ibcon#read 6, iclass 24, count 0 2006.245.08:10:20.93#ibcon#end of sib2, iclass 24, count 0 2006.245.08:10:20.93#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:10:20.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:10:20.93#ibcon#[25=USB\r\n] 2006.245.08:10:20.93#ibcon#*before write, iclass 24, count 0 2006.245.08:10:20.93#ibcon#enter sib2, iclass 24, count 0 2006.245.08:10:20.93#ibcon#flushed, iclass 24, count 0 2006.245.08:10:20.93#ibcon#about to write, iclass 24, count 0 2006.245.08:10:20.93#ibcon#wrote, iclass 24, count 0 2006.245.08:10:20.93#ibcon#about to read 3, iclass 24, count 0 2006.245.08:10:20.96#ibcon#read 3, iclass 24, count 0 2006.245.08:10:20.96#ibcon#about to read 4, iclass 24, count 0 2006.245.08:10:20.96#ibcon#read 4, iclass 24, count 0 2006.245.08:10:20.96#ibcon#about to read 5, iclass 24, count 0 2006.245.08:10:20.96#ibcon#read 5, iclass 24, count 0 2006.245.08:10:20.96#ibcon#about to read 6, iclass 24, count 0 2006.245.08:10:20.96#ibcon#read 6, iclass 24, count 0 2006.245.08:10:20.96#ibcon#end of sib2, iclass 24, count 0 2006.245.08:10:20.96#ibcon#*after write, iclass 24, count 0 2006.245.08:10:20.96#ibcon#*before return 0, iclass 24, count 0 2006.245.08:10:20.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:20.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:20.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:10:20.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:10:20.96$vc4f8/valo=5,652.99 2006.245.08:10:20.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.08:10:20.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.08:10:20.96#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:20.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:20.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:20.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:20.96#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:10:20.96#ibcon#first serial, iclass 26, count 0 2006.245.08:10:20.96#ibcon#enter sib2, iclass 26, count 0 2006.245.08:10:20.96#ibcon#flushed, iclass 26, count 0 2006.245.08:10:20.96#ibcon#about to write, iclass 26, count 0 2006.245.08:10:20.96#ibcon#wrote, iclass 26, count 0 2006.245.08:10:20.96#ibcon#about to read 3, iclass 26, count 0 2006.245.08:10:20.98#ibcon#read 3, iclass 26, count 0 2006.245.08:10:20.98#ibcon#about to read 4, iclass 26, count 0 2006.245.08:10:20.98#ibcon#read 4, iclass 26, count 0 2006.245.08:10:20.98#ibcon#about to read 5, iclass 26, count 0 2006.245.08:10:20.98#ibcon#read 5, iclass 26, count 0 2006.245.08:10:20.98#ibcon#about to read 6, iclass 26, count 0 2006.245.08:10:20.98#ibcon#read 6, iclass 26, count 0 2006.245.08:10:20.98#ibcon#end of sib2, iclass 26, count 0 2006.245.08:10:20.98#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:10:20.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:10:20.98#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:10:20.98#ibcon#*before write, iclass 26, count 0 2006.245.08:10:20.98#ibcon#enter sib2, iclass 26, count 0 2006.245.08:10:20.98#ibcon#flushed, iclass 26, count 0 2006.245.08:10:20.98#ibcon#about to write, iclass 26, count 0 2006.245.08:10:20.98#ibcon#wrote, iclass 26, count 0 2006.245.08:10:20.98#ibcon#about to read 3, iclass 26, count 0 2006.245.08:10:21.02#ibcon#read 3, iclass 26, count 0 2006.245.08:10:21.02#ibcon#about to read 4, iclass 26, count 0 2006.245.08:10:21.02#ibcon#read 4, iclass 26, count 0 2006.245.08:10:21.02#ibcon#about to read 5, iclass 26, count 0 2006.245.08:10:21.02#ibcon#read 5, iclass 26, count 0 2006.245.08:10:21.02#ibcon#about to read 6, iclass 26, count 0 2006.245.08:10:21.02#ibcon#read 6, iclass 26, count 0 2006.245.08:10:21.02#ibcon#end of sib2, iclass 26, count 0 2006.245.08:10:21.02#ibcon#*after write, iclass 26, count 0 2006.245.08:10:21.02#ibcon#*before return 0, iclass 26, count 0 2006.245.08:10:21.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:21.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:21.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:10:21.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:10:21.02$vc4f8/va=5,7 2006.245.08:10:21.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.08:10:21.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.08:10:21.02#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:21.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:21.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:21.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:21.08#ibcon#enter wrdev, iclass 28, count 2 2006.245.08:10:21.08#ibcon#first serial, iclass 28, count 2 2006.245.08:10:21.08#ibcon#enter sib2, iclass 28, count 2 2006.245.08:10:21.08#ibcon#flushed, iclass 28, count 2 2006.245.08:10:21.08#ibcon#about to write, iclass 28, count 2 2006.245.08:10:21.08#ibcon#wrote, iclass 28, count 2 2006.245.08:10:21.08#ibcon#about to read 3, iclass 28, count 2 2006.245.08:10:21.10#ibcon#read 3, iclass 28, count 2 2006.245.08:10:21.10#ibcon#about to read 4, iclass 28, count 2 2006.245.08:10:21.10#ibcon#read 4, iclass 28, count 2 2006.245.08:10:21.10#ibcon#about to read 5, iclass 28, count 2 2006.245.08:10:21.10#ibcon#read 5, iclass 28, count 2 2006.245.08:10:21.10#ibcon#about to read 6, iclass 28, count 2 2006.245.08:10:21.10#ibcon#read 6, iclass 28, count 2 2006.245.08:10:21.10#ibcon#end of sib2, iclass 28, count 2 2006.245.08:10:21.10#ibcon#*mode == 0, iclass 28, count 2 2006.245.08:10:21.10#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.08:10:21.10#ibcon#[25=AT05-07\r\n] 2006.245.08:10:21.10#ibcon#*before write, iclass 28, count 2 2006.245.08:10:21.10#ibcon#enter sib2, iclass 28, count 2 2006.245.08:10:21.10#ibcon#flushed, iclass 28, count 2 2006.245.08:10:21.10#ibcon#about to write, iclass 28, count 2 2006.245.08:10:21.10#ibcon#wrote, iclass 28, count 2 2006.245.08:10:21.10#ibcon#about to read 3, iclass 28, count 2 2006.245.08:10:21.13#ibcon#read 3, iclass 28, count 2 2006.245.08:10:21.13#ibcon#about to read 4, iclass 28, count 2 2006.245.08:10:21.13#ibcon#read 4, iclass 28, count 2 2006.245.08:10:21.13#ibcon#about to read 5, iclass 28, count 2 2006.245.08:10:21.13#ibcon#read 5, iclass 28, count 2 2006.245.08:10:21.13#ibcon#about to read 6, iclass 28, count 2 2006.245.08:10:21.13#ibcon#read 6, iclass 28, count 2 2006.245.08:10:21.13#ibcon#end of sib2, iclass 28, count 2 2006.245.08:10:21.13#ibcon#*after write, iclass 28, count 2 2006.245.08:10:21.13#ibcon#*before return 0, iclass 28, count 2 2006.245.08:10:21.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:21.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:21.13#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.08:10:21.13#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:21.13#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:21.25#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:21.25#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:21.25#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:10:21.25#ibcon#first serial, iclass 28, count 0 2006.245.08:10:21.25#ibcon#enter sib2, iclass 28, count 0 2006.245.08:10:21.25#ibcon#flushed, iclass 28, count 0 2006.245.08:10:21.25#ibcon#about to write, iclass 28, count 0 2006.245.08:10:21.25#ibcon#wrote, iclass 28, count 0 2006.245.08:10:21.25#ibcon#about to read 3, iclass 28, count 0 2006.245.08:10:21.27#ibcon#read 3, iclass 28, count 0 2006.245.08:10:21.27#ibcon#about to read 4, iclass 28, count 0 2006.245.08:10:21.27#ibcon#read 4, iclass 28, count 0 2006.245.08:10:21.27#ibcon#about to read 5, iclass 28, count 0 2006.245.08:10:21.27#ibcon#read 5, iclass 28, count 0 2006.245.08:10:21.27#ibcon#about to read 6, iclass 28, count 0 2006.245.08:10:21.27#ibcon#read 6, iclass 28, count 0 2006.245.08:10:21.27#ibcon#end of sib2, iclass 28, count 0 2006.245.08:10:21.27#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:10:21.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:10:21.27#ibcon#[25=USB\r\n] 2006.245.08:10:21.27#ibcon#*before write, iclass 28, count 0 2006.245.08:10:21.27#ibcon#enter sib2, iclass 28, count 0 2006.245.08:10:21.27#ibcon#flushed, iclass 28, count 0 2006.245.08:10:21.27#ibcon#about to write, iclass 28, count 0 2006.245.08:10:21.27#ibcon#wrote, iclass 28, count 0 2006.245.08:10:21.27#ibcon#about to read 3, iclass 28, count 0 2006.245.08:10:21.30#ibcon#read 3, iclass 28, count 0 2006.245.08:10:21.30#ibcon#about to read 4, iclass 28, count 0 2006.245.08:10:21.30#ibcon#read 4, iclass 28, count 0 2006.245.08:10:21.30#ibcon#about to read 5, iclass 28, count 0 2006.245.08:10:21.30#ibcon#read 5, iclass 28, count 0 2006.245.08:10:21.30#ibcon#about to read 6, iclass 28, count 0 2006.245.08:10:21.30#ibcon#read 6, iclass 28, count 0 2006.245.08:10:21.30#ibcon#end of sib2, iclass 28, count 0 2006.245.08:10:21.30#ibcon#*after write, iclass 28, count 0 2006.245.08:10:21.30#ibcon#*before return 0, iclass 28, count 0 2006.245.08:10:21.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:21.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:21.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:10:21.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:10:21.30$vc4f8/valo=6,772.99 2006.245.08:10:21.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.08:10:21.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.08:10:21.30#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:21.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:21.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:21.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:21.30#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:10:21.30#ibcon#first serial, iclass 30, count 0 2006.245.08:10:21.30#ibcon#enter sib2, iclass 30, count 0 2006.245.08:10:21.30#ibcon#flushed, iclass 30, count 0 2006.245.08:10:21.30#ibcon#about to write, iclass 30, count 0 2006.245.08:10:21.30#ibcon#wrote, iclass 30, count 0 2006.245.08:10:21.30#ibcon#about to read 3, iclass 30, count 0 2006.245.08:10:21.33#ibcon#read 3, iclass 30, count 0 2006.245.08:10:21.33#ibcon#about to read 4, iclass 30, count 0 2006.245.08:10:21.33#ibcon#read 4, iclass 30, count 0 2006.245.08:10:21.33#ibcon#about to read 5, iclass 30, count 0 2006.245.08:10:21.33#ibcon#read 5, iclass 30, count 0 2006.245.08:10:21.33#ibcon#about to read 6, iclass 30, count 0 2006.245.08:10:21.33#ibcon#read 6, iclass 30, count 0 2006.245.08:10:21.33#ibcon#end of sib2, iclass 30, count 0 2006.245.08:10:21.33#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:10:21.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:10:21.33#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:10:21.33#ibcon#*before write, iclass 30, count 0 2006.245.08:10:21.33#ibcon#enter sib2, iclass 30, count 0 2006.245.08:10:21.33#ibcon#flushed, iclass 30, count 0 2006.245.08:10:21.33#ibcon#about to write, iclass 30, count 0 2006.245.08:10:21.33#ibcon#wrote, iclass 30, count 0 2006.245.08:10:21.33#ibcon#about to read 3, iclass 30, count 0 2006.245.08:10:21.37#ibcon#read 3, iclass 30, count 0 2006.245.08:10:21.37#ibcon#about to read 4, iclass 30, count 0 2006.245.08:10:21.37#ibcon#read 4, iclass 30, count 0 2006.245.08:10:21.37#ibcon#about to read 5, iclass 30, count 0 2006.245.08:10:21.37#ibcon#read 5, iclass 30, count 0 2006.245.08:10:21.37#ibcon#about to read 6, iclass 30, count 0 2006.245.08:10:21.37#ibcon#read 6, iclass 30, count 0 2006.245.08:10:21.37#ibcon#end of sib2, iclass 30, count 0 2006.245.08:10:21.37#ibcon#*after write, iclass 30, count 0 2006.245.08:10:21.37#ibcon#*before return 0, iclass 30, count 0 2006.245.08:10:21.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:21.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:21.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:10:21.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:10:21.37$vc4f8/va=6,7 2006.245.08:10:21.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.08:10:21.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.08:10:21.37#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:21.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:10:21.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:10:21.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:10:21.42#ibcon#enter wrdev, iclass 32, count 2 2006.245.08:10:21.42#ibcon#first serial, iclass 32, count 2 2006.245.08:10:21.42#ibcon#enter sib2, iclass 32, count 2 2006.245.08:10:21.42#ibcon#flushed, iclass 32, count 2 2006.245.08:10:21.42#ibcon#about to write, iclass 32, count 2 2006.245.08:10:21.42#ibcon#wrote, iclass 32, count 2 2006.245.08:10:21.42#ibcon#about to read 3, iclass 32, count 2 2006.245.08:10:21.44#ibcon#read 3, iclass 32, count 2 2006.245.08:10:21.44#ibcon#about to read 4, iclass 32, count 2 2006.245.08:10:21.44#ibcon#read 4, iclass 32, count 2 2006.245.08:10:21.44#ibcon#about to read 5, iclass 32, count 2 2006.245.08:10:21.44#ibcon#read 5, iclass 32, count 2 2006.245.08:10:21.44#ibcon#about to read 6, iclass 32, count 2 2006.245.08:10:21.44#ibcon#read 6, iclass 32, count 2 2006.245.08:10:21.44#ibcon#end of sib2, iclass 32, count 2 2006.245.08:10:21.44#ibcon#*mode == 0, iclass 32, count 2 2006.245.08:10:21.44#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.08:10:21.44#ibcon#[25=AT06-07\r\n] 2006.245.08:10:21.44#ibcon#*before write, iclass 32, count 2 2006.245.08:10:21.44#ibcon#enter sib2, iclass 32, count 2 2006.245.08:10:21.44#ibcon#flushed, iclass 32, count 2 2006.245.08:10:21.44#ibcon#about to write, iclass 32, count 2 2006.245.08:10:21.44#ibcon#wrote, iclass 32, count 2 2006.245.08:10:21.44#ibcon#about to read 3, iclass 32, count 2 2006.245.08:10:21.47#ibcon#read 3, iclass 32, count 2 2006.245.08:10:21.47#ibcon#about to read 4, iclass 32, count 2 2006.245.08:10:21.47#ibcon#read 4, iclass 32, count 2 2006.245.08:10:21.47#ibcon#about to read 5, iclass 32, count 2 2006.245.08:10:21.47#ibcon#read 5, iclass 32, count 2 2006.245.08:10:21.47#ibcon#about to read 6, iclass 32, count 2 2006.245.08:10:21.47#ibcon#read 6, iclass 32, count 2 2006.245.08:10:21.47#ibcon#end of sib2, iclass 32, count 2 2006.245.08:10:21.47#ibcon#*after write, iclass 32, count 2 2006.245.08:10:21.47#ibcon#*before return 0, iclass 32, count 2 2006.245.08:10:21.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:10:21.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:10:21.47#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.08:10:21.47#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:21.47#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:10:21.59#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:10:21.59#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:10:21.59#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:10:21.59#ibcon#first serial, iclass 32, count 0 2006.245.08:10:21.59#ibcon#enter sib2, iclass 32, count 0 2006.245.08:10:21.59#ibcon#flushed, iclass 32, count 0 2006.245.08:10:21.59#ibcon#about to write, iclass 32, count 0 2006.245.08:10:21.59#ibcon#wrote, iclass 32, count 0 2006.245.08:10:21.59#ibcon#about to read 3, iclass 32, count 0 2006.245.08:10:21.61#ibcon#read 3, iclass 32, count 0 2006.245.08:10:21.61#ibcon#about to read 4, iclass 32, count 0 2006.245.08:10:21.61#ibcon#read 4, iclass 32, count 0 2006.245.08:10:21.61#ibcon#about to read 5, iclass 32, count 0 2006.245.08:10:21.61#ibcon#read 5, iclass 32, count 0 2006.245.08:10:21.61#ibcon#about to read 6, iclass 32, count 0 2006.245.08:10:21.61#ibcon#read 6, iclass 32, count 0 2006.245.08:10:21.61#ibcon#end of sib2, iclass 32, count 0 2006.245.08:10:21.61#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:10:21.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:10:21.61#ibcon#[25=USB\r\n] 2006.245.08:10:21.61#ibcon#*before write, iclass 32, count 0 2006.245.08:10:21.61#ibcon#enter sib2, iclass 32, count 0 2006.245.08:10:21.61#ibcon#flushed, iclass 32, count 0 2006.245.08:10:21.61#ibcon#about to write, iclass 32, count 0 2006.245.08:10:21.61#ibcon#wrote, iclass 32, count 0 2006.245.08:10:21.61#ibcon#about to read 3, iclass 32, count 0 2006.245.08:10:21.64#ibcon#read 3, iclass 32, count 0 2006.245.08:10:21.64#ibcon#about to read 4, iclass 32, count 0 2006.245.08:10:21.64#ibcon#read 4, iclass 32, count 0 2006.245.08:10:21.64#ibcon#about to read 5, iclass 32, count 0 2006.245.08:10:21.64#ibcon#read 5, iclass 32, count 0 2006.245.08:10:21.64#ibcon#about to read 6, iclass 32, count 0 2006.245.08:10:21.64#ibcon#read 6, iclass 32, count 0 2006.245.08:10:21.64#ibcon#end of sib2, iclass 32, count 0 2006.245.08:10:21.64#ibcon#*after write, iclass 32, count 0 2006.245.08:10:21.64#ibcon#*before return 0, iclass 32, count 0 2006.245.08:10:21.64#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:10:21.64#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:10:21.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:10:21.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:10:21.64$vc4f8/valo=7,832.99 2006.245.08:10:21.64#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.08:10:21.64#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.08:10:21.64#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:21.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:10:21.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:10:21.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:10:21.64#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:10:21.64#ibcon#first serial, iclass 34, count 0 2006.245.08:10:21.64#ibcon#enter sib2, iclass 34, count 0 2006.245.08:10:21.64#ibcon#flushed, iclass 34, count 0 2006.245.08:10:21.64#ibcon#about to write, iclass 34, count 0 2006.245.08:10:21.64#ibcon#wrote, iclass 34, count 0 2006.245.08:10:21.64#ibcon#about to read 3, iclass 34, count 0 2006.245.08:10:21.66#ibcon#read 3, iclass 34, count 0 2006.245.08:10:21.66#ibcon#about to read 4, iclass 34, count 0 2006.245.08:10:21.66#ibcon#read 4, iclass 34, count 0 2006.245.08:10:21.66#ibcon#about to read 5, iclass 34, count 0 2006.245.08:10:21.66#ibcon#read 5, iclass 34, count 0 2006.245.08:10:21.66#ibcon#about to read 6, iclass 34, count 0 2006.245.08:10:21.66#ibcon#read 6, iclass 34, count 0 2006.245.08:10:21.66#ibcon#end of sib2, iclass 34, count 0 2006.245.08:10:21.66#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:10:21.66#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:10:21.66#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:10:21.66#ibcon#*before write, iclass 34, count 0 2006.245.08:10:21.66#ibcon#enter sib2, iclass 34, count 0 2006.245.08:10:21.66#ibcon#flushed, iclass 34, count 0 2006.245.08:10:21.66#ibcon#about to write, iclass 34, count 0 2006.245.08:10:21.66#ibcon#wrote, iclass 34, count 0 2006.245.08:10:21.66#ibcon#about to read 3, iclass 34, count 0 2006.245.08:10:21.70#ibcon#read 3, iclass 34, count 0 2006.245.08:10:21.70#ibcon#about to read 4, iclass 34, count 0 2006.245.08:10:21.70#ibcon#read 4, iclass 34, count 0 2006.245.08:10:21.70#ibcon#about to read 5, iclass 34, count 0 2006.245.08:10:21.70#ibcon#read 5, iclass 34, count 0 2006.245.08:10:21.70#ibcon#about to read 6, iclass 34, count 0 2006.245.08:10:21.70#ibcon#read 6, iclass 34, count 0 2006.245.08:10:21.70#ibcon#end of sib2, iclass 34, count 0 2006.245.08:10:21.70#ibcon#*after write, iclass 34, count 0 2006.245.08:10:21.70#ibcon#*before return 0, iclass 34, count 0 2006.245.08:10:21.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:10:21.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:10:21.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:10:21.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:10:21.70$vc4f8/va=7,7 2006.245.08:10:21.70#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.08:10:21.70#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.08:10:21.70#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:21.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:10:21.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:10:21.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:10:21.76#ibcon#enter wrdev, iclass 36, count 2 2006.245.08:10:21.76#ibcon#first serial, iclass 36, count 2 2006.245.08:10:21.76#ibcon#enter sib2, iclass 36, count 2 2006.245.08:10:21.76#ibcon#flushed, iclass 36, count 2 2006.245.08:10:21.76#ibcon#about to write, iclass 36, count 2 2006.245.08:10:21.76#ibcon#wrote, iclass 36, count 2 2006.245.08:10:21.76#ibcon#about to read 3, iclass 36, count 2 2006.245.08:10:21.78#ibcon#read 3, iclass 36, count 2 2006.245.08:10:21.78#ibcon#about to read 4, iclass 36, count 2 2006.245.08:10:21.78#ibcon#read 4, iclass 36, count 2 2006.245.08:10:21.78#ibcon#about to read 5, iclass 36, count 2 2006.245.08:10:21.78#ibcon#read 5, iclass 36, count 2 2006.245.08:10:21.78#ibcon#about to read 6, iclass 36, count 2 2006.245.08:10:21.78#ibcon#read 6, iclass 36, count 2 2006.245.08:10:21.78#ibcon#end of sib2, iclass 36, count 2 2006.245.08:10:21.78#ibcon#*mode == 0, iclass 36, count 2 2006.245.08:10:21.78#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.08:10:21.78#ibcon#[25=AT07-07\r\n] 2006.245.08:10:21.78#ibcon#*before write, iclass 36, count 2 2006.245.08:10:21.78#ibcon#enter sib2, iclass 36, count 2 2006.245.08:10:21.78#ibcon#flushed, iclass 36, count 2 2006.245.08:10:21.78#ibcon#about to write, iclass 36, count 2 2006.245.08:10:21.78#ibcon#wrote, iclass 36, count 2 2006.245.08:10:21.78#ibcon#about to read 3, iclass 36, count 2 2006.245.08:10:21.81#ibcon#read 3, iclass 36, count 2 2006.245.08:10:21.81#ibcon#about to read 4, iclass 36, count 2 2006.245.08:10:21.81#ibcon#read 4, iclass 36, count 2 2006.245.08:10:21.81#ibcon#about to read 5, iclass 36, count 2 2006.245.08:10:21.81#ibcon#read 5, iclass 36, count 2 2006.245.08:10:21.81#ibcon#about to read 6, iclass 36, count 2 2006.245.08:10:21.81#ibcon#read 6, iclass 36, count 2 2006.245.08:10:21.81#ibcon#end of sib2, iclass 36, count 2 2006.245.08:10:21.81#ibcon#*after write, iclass 36, count 2 2006.245.08:10:21.81#ibcon#*before return 0, iclass 36, count 2 2006.245.08:10:21.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:10:21.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:10:21.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.08:10:21.81#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:21.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:10:21.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:10:21.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:10:21.93#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:10:21.93#ibcon#first serial, iclass 36, count 0 2006.245.08:10:21.93#ibcon#enter sib2, iclass 36, count 0 2006.245.08:10:21.93#ibcon#flushed, iclass 36, count 0 2006.245.08:10:21.93#ibcon#about to write, iclass 36, count 0 2006.245.08:10:21.93#ibcon#wrote, iclass 36, count 0 2006.245.08:10:21.93#ibcon#about to read 3, iclass 36, count 0 2006.245.08:10:21.95#ibcon#read 3, iclass 36, count 0 2006.245.08:10:21.95#ibcon#about to read 4, iclass 36, count 0 2006.245.08:10:21.95#ibcon#read 4, iclass 36, count 0 2006.245.08:10:21.95#ibcon#about to read 5, iclass 36, count 0 2006.245.08:10:21.95#ibcon#read 5, iclass 36, count 0 2006.245.08:10:21.95#ibcon#about to read 6, iclass 36, count 0 2006.245.08:10:21.95#ibcon#read 6, iclass 36, count 0 2006.245.08:10:21.95#ibcon#end of sib2, iclass 36, count 0 2006.245.08:10:21.95#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:10:21.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:10:21.95#ibcon#[25=USB\r\n] 2006.245.08:10:21.95#ibcon#*before write, iclass 36, count 0 2006.245.08:10:21.95#ibcon#enter sib2, iclass 36, count 0 2006.245.08:10:21.95#ibcon#flushed, iclass 36, count 0 2006.245.08:10:21.95#ibcon#about to write, iclass 36, count 0 2006.245.08:10:21.95#ibcon#wrote, iclass 36, count 0 2006.245.08:10:21.95#ibcon#about to read 3, iclass 36, count 0 2006.245.08:10:21.98#ibcon#read 3, iclass 36, count 0 2006.245.08:10:21.98#ibcon#about to read 4, iclass 36, count 0 2006.245.08:10:21.98#ibcon#read 4, iclass 36, count 0 2006.245.08:10:21.98#ibcon#about to read 5, iclass 36, count 0 2006.245.08:10:21.98#ibcon#read 5, iclass 36, count 0 2006.245.08:10:21.98#ibcon#about to read 6, iclass 36, count 0 2006.245.08:10:21.98#ibcon#read 6, iclass 36, count 0 2006.245.08:10:21.98#ibcon#end of sib2, iclass 36, count 0 2006.245.08:10:21.98#ibcon#*after write, iclass 36, count 0 2006.245.08:10:21.98#ibcon#*before return 0, iclass 36, count 0 2006.245.08:10:21.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:10:21.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:10:21.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:10:21.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:10:21.98$vc4f8/valo=8,852.99 2006.245.08:10:21.98#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.08:10:21.98#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.08:10:21.98#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:21.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:10:21.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:10:21.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:10:21.98#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:10:21.98#ibcon#first serial, iclass 38, count 0 2006.245.08:10:21.98#ibcon#enter sib2, iclass 38, count 0 2006.245.08:10:21.98#ibcon#flushed, iclass 38, count 0 2006.245.08:10:21.98#ibcon#about to write, iclass 38, count 0 2006.245.08:10:21.98#ibcon#wrote, iclass 38, count 0 2006.245.08:10:21.98#ibcon#about to read 3, iclass 38, count 0 2006.245.08:10:22.01#ibcon#read 3, iclass 38, count 0 2006.245.08:10:22.01#ibcon#about to read 4, iclass 38, count 0 2006.245.08:10:22.01#ibcon#read 4, iclass 38, count 0 2006.245.08:10:22.01#ibcon#about to read 5, iclass 38, count 0 2006.245.08:10:22.01#ibcon#read 5, iclass 38, count 0 2006.245.08:10:22.01#ibcon#about to read 6, iclass 38, count 0 2006.245.08:10:22.01#ibcon#read 6, iclass 38, count 0 2006.245.08:10:22.01#ibcon#end of sib2, iclass 38, count 0 2006.245.08:10:22.01#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:10:22.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:10:22.01#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:10:22.01#ibcon#*before write, iclass 38, count 0 2006.245.08:10:22.01#ibcon#enter sib2, iclass 38, count 0 2006.245.08:10:22.01#ibcon#flushed, iclass 38, count 0 2006.245.08:10:22.01#ibcon#about to write, iclass 38, count 0 2006.245.08:10:22.01#ibcon#wrote, iclass 38, count 0 2006.245.08:10:22.01#ibcon#about to read 3, iclass 38, count 0 2006.245.08:10:22.05#ibcon#read 3, iclass 38, count 0 2006.245.08:10:22.05#ibcon#about to read 4, iclass 38, count 0 2006.245.08:10:22.05#ibcon#read 4, iclass 38, count 0 2006.245.08:10:22.05#ibcon#about to read 5, iclass 38, count 0 2006.245.08:10:22.05#ibcon#read 5, iclass 38, count 0 2006.245.08:10:22.05#ibcon#about to read 6, iclass 38, count 0 2006.245.08:10:22.05#ibcon#read 6, iclass 38, count 0 2006.245.08:10:22.05#ibcon#end of sib2, iclass 38, count 0 2006.245.08:10:22.05#ibcon#*after write, iclass 38, count 0 2006.245.08:10:22.05#ibcon#*before return 0, iclass 38, count 0 2006.245.08:10:22.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:10:22.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:10:22.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:10:22.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:10:22.05$vc4f8/va=8,8 2006.245.08:10:22.05#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.08:10:22.05#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.08:10:22.05#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:22.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:10:22.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:10:22.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:10:22.10#ibcon#enter wrdev, iclass 40, count 2 2006.245.08:10:22.10#ibcon#first serial, iclass 40, count 2 2006.245.08:10:22.10#ibcon#enter sib2, iclass 40, count 2 2006.245.08:10:22.10#ibcon#flushed, iclass 40, count 2 2006.245.08:10:22.10#ibcon#about to write, iclass 40, count 2 2006.245.08:10:22.10#ibcon#wrote, iclass 40, count 2 2006.245.08:10:22.10#ibcon#about to read 3, iclass 40, count 2 2006.245.08:10:22.12#ibcon#read 3, iclass 40, count 2 2006.245.08:10:22.12#ibcon#about to read 4, iclass 40, count 2 2006.245.08:10:22.12#ibcon#read 4, iclass 40, count 2 2006.245.08:10:22.12#ibcon#about to read 5, iclass 40, count 2 2006.245.08:10:22.12#ibcon#read 5, iclass 40, count 2 2006.245.08:10:22.12#ibcon#about to read 6, iclass 40, count 2 2006.245.08:10:22.12#ibcon#read 6, iclass 40, count 2 2006.245.08:10:22.12#ibcon#end of sib2, iclass 40, count 2 2006.245.08:10:22.12#ibcon#*mode == 0, iclass 40, count 2 2006.245.08:10:22.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.08:10:22.12#ibcon#[25=AT08-08\r\n] 2006.245.08:10:22.12#ibcon#*before write, iclass 40, count 2 2006.245.08:10:22.12#ibcon#enter sib2, iclass 40, count 2 2006.245.08:10:22.12#ibcon#flushed, iclass 40, count 2 2006.245.08:10:22.12#ibcon#about to write, iclass 40, count 2 2006.245.08:10:22.12#ibcon#wrote, iclass 40, count 2 2006.245.08:10:22.12#ibcon#about to read 3, iclass 40, count 2 2006.245.08:10:22.15#ibcon#read 3, iclass 40, count 2 2006.245.08:10:22.15#ibcon#about to read 4, iclass 40, count 2 2006.245.08:10:22.15#ibcon#read 4, iclass 40, count 2 2006.245.08:10:22.15#ibcon#about to read 5, iclass 40, count 2 2006.245.08:10:22.15#ibcon#read 5, iclass 40, count 2 2006.245.08:10:22.15#ibcon#about to read 6, iclass 40, count 2 2006.245.08:10:22.15#ibcon#read 6, iclass 40, count 2 2006.245.08:10:22.15#ibcon#end of sib2, iclass 40, count 2 2006.245.08:10:22.15#ibcon#*after write, iclass 40, count 2 2006.245.08:10:22.15#ibcon#*before return 0, iclass 40, count 2 2006.245.08:10:22.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:10:22.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:10:22.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.08:10:22.15#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:22.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:10:22.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:10:22.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:10:22.27#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:10:22.27#ibcon#first serial, iclass 40, count 0 2006.245.08:10:22.27#ibcon#enter sib2, iclass 40, count 0 2006.245.08:10:22.27#ibcon#flushed, iclass 40, count 0 2006.245.08:10:22.27#ibcon#about to write, iclass 40, count 0 2006.245.08:10:22.27#ibcon#wrote, iclass 40, count 0 2006.245.08:10:22.27#ibcon#about to read 3, iclass 40, count 0 2006.245.08:10:22.29#ibcon#read 3, iclass 40, count 0 2006.245.08:10:22.29#ibcon#about to read 4, iclass 40, count 0 2006.245.08:10:22.29#ibcon#read 4, iclass 40, count 0 2006.245.08:10:22.29#ibcon#about to read 5, iclass 40, count 0 2006.245.08:10:22.29#ibcon#read 5, iclass 40, count 0 2006.245.08:10:22.29#ibcon#about to read 6, iclass 40, count 0 2006.245.08:10:22.29#ibcon#read 6, iclass 40, count 0 2006.245.08:10:22.29#ibcon#end of sib2, iclass 40, count 0 2006.245.08:10:22.29#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:10:22.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:10:22.29#ibcon#[25=USB\r\n] 2006.245.08:10:22.29#ibcon#*before write, iclass 40, count 0 2006.245.08:10:22.29#ibcon#enter sib2, iclass 40, count 0 2006.245.08:10:22.29#ibcon#flushed, iclass 40, count 0 2006.245.08:10:22.29#ibcon#about to write, iclass 40, count 0 2006.245.08:10:22.29#ibcon#wrote, iclass 40, count 0 2006.245.08:10:22.29#ibcon#about to read 3, iclass 40, count 0 2006.245.08:10:22.32#ibcon#read 3, iclass 40, count 0 2006.245.08:10:22.32#ibcon#about to read 4, iclass 40, count 0 2006.245.08:10:22.32#ibcon#read 4, iclass 40, count 0 2006.245.08:10:22.32#ibcon#about to read 5, iclass 40, count 0 2006.245.08:10:22.32#ibcon#read 5, iclass 40, count 0 2006.245.08:10:22.32#ibcon#about to read 6, iclass 40, count 0 2006.245.08:10:22.32#ibcon#read 6, iclass 40, count 0 2006.245.08:10:22.32#ibcon#end of sib2, iclass 40, count 0 2006.245.08:10:22.32#ibcon#*after write, iclass 40, count 0 2006.245.08:10:22.32#ibcon#*before return 0, iclass 40, count 0 2006.245.08:10:22.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:10:22.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:10:22.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:10:22.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:10:22.32$vc4f8/vblo=1,632.99 2006.245.08:10:22.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.08:10:22.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.08:10:22.32#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:22.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:10:22.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:10:22.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:10:22.32#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:10:22.32#ibcon#first serial, iclass 4, count 0 2006.245.08:10:22.32#ibcon#enter sib2, iclass 4, count 0 2006.245.08:10:22.32#ibcon#flushed, iclass 4, count 0 2006.245.08:10:22.32#ibcon#about to write, iclass 4, count 0 2006.245.08:10:22.32#ibcon#wrote, iclass 4, count 0 2006.245.08:10:22.32#ibcon#about to read 3, iclass 4, count 0 2006.245.08:10:22.34#ibcon#read 3, iclass 4, count 0 2006.245.08:10:22.34#ibcon#about to read 4, iclass 4, count 0 2006.245.08:10:22.34#ibcon#read 4, iclass 4, count 0 2006.245.08:10:22.34#ibcon#about to read 5, iclass 4, count 0 2006.245.08:10:22.34#ibcon#read 5, iclass 4, count 0 2006.245.08:10:22.34#ibcon#about to read 6, iclass 4, count 0 2006.245.08:10:22.34#ibcon#read 6, iclass 4, count 0 2006.245.08:10:22.34#ibcon#end of sib2, iclass 4, count 0 2006.245.08:10:22.34#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:10:22.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:10:22.34#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:10:22.34#ibcon#*before write, iclass 4, count 0 2006.245.08:10:22.34#ibcon#enter sib2, iclass 4, count 0 2006.245.08:10:22.34#ibcon#flushed, iclass 4, count 0 2006.245.08:10:22.34#ibcon#about to write, iclass 4, count 0 2006.245.08:10:22.34#ibcon#wrote, iclass 4, count 0 2006.245.08:10:22.34#ibcon#about to read 3, iclass 4, count 0 2006.245.08:10:22.38#ibcon#read 3, iclass 4, count 0 2006.245.08:10:22.38#ibcon#about to read 4, iclass 4, count 0 2006.245.08:10:22.38#ibcon#read 4, iclass 4, count 0 2006.245.08:10:22.38#ibcon#about to read 5, iclass 4, count 0 2006.245.08:10:22.38#ibcon#read 5, iclass 4, count 0 2006.245.08:10:22.38#ibcon#about to read 6, iclass 4, count 0 2006.245.08:10:22.38#ibcon#read 6, iclass 4, count 0 2006.245.08:10:22.38#ibcon#end of sib2, iclass 4, count 0 2006.245.08:10:22.38#ibcon#*after write, iclass 4, count 0 2006.245.08:10:22.38#ibcon#*before return 0, iclass 4, count 0 2006.245.08:10:22.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:10:22.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:10:22.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:10:22.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:10:22.38$vc4f8/vb=1,4 2006.245.08:10:22.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.08:10:22.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.08:10:22.38#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:22.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:10:22.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:10:22.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:10:22.38#ibcon#enter wrdev, iclass 6, count 2 2006.245.08:10:22.38#ibcon#first serial, iclass 6, count 2 2006.245.08:10:22.38#ibcon#enter sib2, iclass 6, count 2 2006.245.08:10:22.38#ibcon#flushed, iclass 6, count 2 2006.245.08:10:22.38#ibcon#about to write, iclass 6, count 2 2006.245.08:10:22.38#ibcon#wrote, iclass 6, count 2 2006.245.08:10:22.38#ibcon#about to read 3, iclass 6, count 2 2006.245.08:10:22.40#ibcon#read 3, iclass 6, count 2 2006.245.08:10:22.40#ibcon#about to read 4, iclass 6, count 2 2006.245.08:10:22.40#ibcon#read 4, iclass 6, count 2 2006.245.08:10:22.40#ibcon#about to read 5, iclass 6, count 2 2006.245.08:10:22.40#ibcon#read 5, iclass 6, count 2 2006.245.08:10:22.40#ibcon#about to read 6, iclass 6, count 2 2006.245.08:10:22.40#ibcon#read 6, iclass 6, count 2 2006.245.08:10:22.40#ibcon#end of sib2, iclass 6, count 2 2006.245.08:10:22.40#ibcon#*mode == 0, iclass 6, count 2 2006.245.08:10:22.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.08:10:22.40#ibcon#[27=AT01-04\r\n] 2006.245.08:10:22.40#ibcon#*before write, iclass 6, count 2 2006.245.08:10:22.40#ibcon#enter sib2, iclass 6, count 2 2006.245.08:10:22.40#ibcon#flushed, iclass 6, count 2 2006.245.08:10:22.40#ibcon#about to write, iclass 6, count 2 2006.245.08:10:22.40#ibcon#wrote, iclass 6, count 2 2006.245.08:10:22.40#ibcon#about to read 3, iclass 6, count 2 2006.245.08:10:22.43#ibcon#read 3, iclass 6, count 2 2006.245.08:10:22.43#ibcon#about to read 4, iclass 6, count 2 2006.245.08:10:22.43#ibcon#read 4, iclass 6, count 2 2006.245.08:10:22.43#ibcon#about to read 5, iclass 6, count 2 2006.245.08:10:22.43#ibcon#read 5, iclass 6, count 2 2006.245.08:10:22.43#ibcon#about to read 6, iclass 6, count 2 2006.245.08:10:22.43#ibcon#read 6, iclass 6, count 2 2006.245.08:10:22.43#ibcon#end of sib2, iclass 6, count 2 2006.245.08:10:22.43#ibcon#*after write, iclass 6, count 2 2006.245.08:10:22.43#ibcon#*before return 0, iclass 6, count 2 2006.245.08:10:22.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:10:22.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:10:22.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.08:10:22.43#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:22.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:10:22.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:10:22.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:10:22.55#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:10:22.55#ibcon#first serial, iclass 6, count 0 2006.245.08:10:22.55#ibcon#enter sib2, iclass 6, count 0 2006.245.08:10:22.55#ibcon#flushed, iclass 6, count 0 2006.245.08:10:22.55#ibcon#about to write, iclass 6, count 0 2006.245.08:10:22.55#ibcon#wrote, iclass 6, count 0 2006.245.08:10:22.55#ibcon#about to read 3, iclass 6, count 0 2006.245.08:10:22.57#ibcon#read 3, iclass 6, count 0 2006.245.08:10:22.57#ibcon#about to read 4, iclass 6, count 0 2006.245.08:10:22.57#ibcon#read 4, iclass 6, count 0 2006.245.08:10:22.57#ibcon#about to read 5, iclass 6, count 0 2006.245.08:10:22.57#ibcon#read 5, iclass 6, count 0 2006.245.08:10:22.57#ibcon#about to read 6, iclass 6, count 0 2006.245.08:10:22.57#ibcon#read 6, iclass 6, count 0 2006.245.08:10:22.57#ibcon#end of sib2, iclass 6, count 0 2006.245.08:10:22.57#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:10:22.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:10:22.57#ibcon#[27=USB\r\n] 2006.245.08:10:22.57#ibcon#*before write, iclass 6, count 0 2006.245.08:10:22.57#ibcon#enter sib2, iclass 6, count 0 2006.245.08:10:22.57#ibcon#flushed, iclass 6, count 0 2006.245.08:10:22.57#ibcon#about to write, iclass 6, count 0 2006.245.08:10:22.57#ibcon#wrote, iclass 6, count 0 2006.245.08:10:22.57#ibcon#about to read 3, iclass 6, count 0 2006.245.08:10:22.60#ibcon#read 3, iclass 6, count 0 2006.245.08:10:22.60#ibcon#about to read 4, iclass 6, count 0 2006.245.08:10:22.60#ibcon#read 4, iclass 6, count 0 2006.245.08:10:22.60#ibcon#about to read 5, iclass 6, count 0 2006.245.08:10:22.60#ibcon#read 5, iclass 6, count 0 2006.245.08:10:22.60#ibcon#about to read 6, iclass 6, count 0 2006.245.08:10:22.60#ibcon#read 6, iclass 6, count 0 2006.245.08:10:22.60#ibcon#end of sib2, iclass 6, count 0 2006.245.08:10:22.60#ibcon#*after write, iclass 6, count 0 2006.245.08:10:22.60#ibcon#*before return 0, iclass 6, count 0 2006.245.08:10:22.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:10:22.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:10:22.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:10:22.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:10:22.60$vc4f8/vblo=2,640.99 2006.245.08:10:22.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.08:10:22.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.08:10:22.60#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:22.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:22.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:22.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:22.60#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:10:22.60#ibcon#first serial, iclass 10, count 0 2006.245.08:10:22.60#ibcon#enter sib2, iclass 10, count 0 2006.245.08:10:22.60#ibcon#flushed, iclass 10, count 0 2006.245.08:10:22.60#ibcon#about to write, iclass 10, count 0 2006.245.08:10:22.60#ibcon#wrote, iclass 10, count 0 2006.245.08:10:22.60#ibcon#about to read 3, iclass 10, count 0 2006.245.08:10:22.62#ibcon#read 3, iclass 10, count 0 2006.245.08:10:22.62#ibcon#about to read 4, iclass 10, count 0 2006.245.08:10:22.62#ibcon#read 4, iclass 10, count 0 2006.245.08:10:22.62#ibcon#about to read 5, iclass 10, count 0 2006.245.08:10:22.62#ibcon#read 5, iclass 10, count 0 2006.245.08:10:22.62#ibcon#about to read 6, iclass 10, count 0 2006.245.08:10:22.62#ibcon#read 6, iclass 10, count 0 2006.245.08:10:22.62#ibcon#end of sib2, iclass 10, count 0 2006.245.08:10:22.62#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:10:22.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:10:22.62#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:10:22.62#ibcon#*before write, iclass 10, count 0 2006.245.08:10:22.62#ibcon#enter sib2, iclass 10, count 0 2006.245.08:10:22.62#ibcon#flushed, iclass 10, count 0 2006.245.08:10:22.62#ibcon#about to write, iclass 10, count 0 2006.245.08:10:22.62#ibcon#wrote, iclass 10, count 0 2006.245.08:10:22.62#ibcon#about to read 3, iclass 10, count 0 2006.245.08:10:22.66#ibcon#read 3, iclass 10, count 0 2006.245.08:10:22.66#ibcon#about to read 4, iclass 10, count 0 2006.245.08:10:22.66#ibcon#read 4, iclass 10, count 0 2006.245.08:10:22.66#ibcon#about to read 5, iclass 10, count 0 2006.245.08:10:22.66#ibcon#read 5, iclass 10, count 0 2006.245.08:10:22.66#ibcon#about to read 6, iclass 10, count 0 2006.245.08:10:22.66#ibcon#read 6, iclass 10, count 0 2006.245.08:10:22.66#ibcon#end of sib2, iclass 10, count 0 2006.245.08:10:22.66#ibcon#*after write, iclass 10, count 0 2006.245.08:10:22.66#ibcon#*before return 0, iclass 10, count 0 2006.245.08:10:22.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:22.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:10:22.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:10:22.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:10:22.66$vc4f8/vb=2,4 2006.245.08:10:22.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.08:10:22.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.08:10:22.66#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:22.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:22.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:22.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:22.72#ibcon#enter wrdev, iclass 12, count 2 2006.245.08:10:22.72#ibcon#first serial, iclass 12, count 2 2006.245.08:10:22.72#ibcon#enter sib2, iclass 12, count 2 2006.245.08:10:22.72#ibcon#flushed, iclass 12, count 2 2006.245.08:10:22.72#ibcon#about to write, iclass 12, count 2 2006.245.08:10:22.72#ibcon#wrote, iclass 12, count 2 2006.245.08:10:22.72#ibcon#about to read 3, iclass 12, count 2 2006.245.08:10:22.74#ibcon#read 3, iclass 12, count 2 2006.245.08:10:22.74#ibcon#about to read 4, iclass 12, count 2 2006.245.08:10:22.74#ibcon#read 4, iclass 12, count 2 2006.245.08:10:22.74#ibcon#about to read 5, iclass 12, count 2 2006.245.08:10:22.74#ibcon#read 5, iclass 12, count 2 2006.245.08:10:22.74#ibcon#about to read 6, iclass 12, count 2 2006.245.08:10:22.74#ibcon#read 6, iclass 12, count 2 2006.245.08:10:22.74#ibcon#end of sib2, iclass 12, count 2 2006.245.08:10:22.74#ibcon#*mode == 0, iclass 12, count 2 2006.245.08:10:22.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.08:10:22.74#ibcon#[27=AT02-04\r\n] 2006.245.08:10:22.74#ibcon#*before write, iclass 12, count 2 2006.245.08:10:22.74#ibcon#enter sib2, iclass 12, count 2 2006.245.08:10:22.74#ibcon#flushed, iclass 12, count 2 2006.245.08:10:22.74#ibcon#about to write, iclass 12, count 2 2006.245.08:10:22.74#ibcon#wrote, iclass 12, count 2 2006.245.08:10:22.74#ibcon#about to read 3, iclass 12, count 2 2006.245.08:10:22.77#ibcon#read 3, iclass 12, count 2 2006.245.08:10:22.77#ibcon#about to read 4, iclass 12, count 2 2006.245.08:10:22.77#ibcon#read 4, iclass 12, count 2 2006.245.08:10:22.77#ibcon#about to read 5, iclass 12, count 2 2006.245.08:10:22.77#ibcon#read 5, iclass 12, count 2 2006.245.08:10:22.77#ibcon#about to read 6, iclass 12, count 2 2006.245.08:10:22.77#ibcon#read 6, iclass 12, count 2 2006.245.08:10:22.77#ibcon#end of sib2, iclass 12, count 2 2006.245.08:10:22.77#ibcon#*after write, iclass 12, count 2 2006.245.08:10:22.77#ibcon#*before return 0, iclass 12, count 2 2006.245.08:10:22.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:22.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:10:22.77#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.08:10:22.77#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:22.77#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:22.89#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:22.89#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:22.89#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:10:22.89#ibcon#first serial, iclass 12, count 0 2006.245.08:10:22.89#ibcon#enter sib2, iclass 12, count 0 2006.245.08:10:22.89#ibcon#flushed, iclass 12, count 0 2006.245.08:10:22.89#ibcon#about to write, iclass 12, count 0 2006.245.08:10:22.89#ibcon#wrote, iclass 12, count 0 2006.245.08:10:22.89#ibcon#about to read 3, iclass 12, count 0 2006.245.08:10:22.91#ibcon#read 3, iclass 12, count 0 2006.245.08:10:22.91#ibcon#about to read 4, iclass 12, count 0 2006.245.08:10:22.91#ibcon#read 4, iclass 12, count 0 2006.245.08:10:22.91#ibcon#about to read 5, iclass 12, count 0 2006.245.08:10:22.91#ibcon#read 5, iclass 12, count 0 2006.245.08:10:22.91#ibcon#about to read 6, iclass 12, count 0 2006.245.08:10:22.91#ibcon#read 6, iclass 12, count 0 2006.245.08:10:22.91#ibcon#end of sib2, iclass 12, count 0 2006.245.08:10:22.91#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:10:22.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:10:22.91#ibcon#[27=USB\r\n] 2006.245.08:10:22.91#ibcon#*before write, iclass 12, count 0 2006.245.08:10:22.91#ibcon#enter sib2, iclass 12, count 0 2006.245.08:10:22.91#ibcon#flushed, iclass 12, count 0 2006.245.08:10:22.91#ibcon#about to write, iclass 12, count 0 2006.245.08:10:22.91#ibcon#wrote, iclass 12, count 0 2006.245.08:10:22.91#ibcon#about to read 3, iclass 12, count 0 2006.245.08:10:22.94#ibcon#read 3, iclass 12, count 0 2006.245.08:10:22.94#ibcon#about to read 4, iclass 12, count 0 2006.245.08:10:22.94#ibcon#read 4, iclass 12, count 0 2006.245.08:10:22.94#ibcon#about to read 5, iclass 12, count 0 2006.245.08:10:22.94#ibcon#read 5, iclass 12, count 0 2006.245.08:10:22.94#ibcon#about to read 6, iclass 12, count 0 2006.245.08:10:22.94#ibcon#read 6, iclass 12, count 0 2006.245.08:10:22.94#ibcon#end of sib2, iclass 12, count 0 2006.245.08:10:22.94#ibcon#*after write, iclass 12, count 0 2006.245.08:10:22.94#ibcon#*before return 0, iclass 12, count 0 2006.245.08:10:22.94#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:22.94#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:10:22.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:10:22.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:10:22.94$vc4f8/vblo=3,656.99 2006.245.08:10:22.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.08:10:22.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.08:10:22.94#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:22.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:22.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:22.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:22.94#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:10:22.94#ibcon#first serial, iclass 14, count 0 2006.245.08:10:22.94#ibcon#enter sib2, iclass 14, count 0 2006.245.08:10:22.94#ibcon#flushed, iclass 14, count 0 2006.245.08:10:22.94#ibcon#about to write, iclass 14, count 0 2006.245.08:10:22.94#ibcon#wrote, iclass 14, count 0 2006.245.08:10:22.94#ibcon#about to read 3, iclass 14, count 0 2006.245.08:10:22.97#ibcon#read 3, iclass 14, count 0 2006.245.08:10:22.97#ibcon#about to read 4, iclass 14, count 0 2006.245.08:10:22.97#ibcon#read 4, iclass 14, count 0 2006.245.08:10:22.97#ibcon#about to read 5, iclass 14, count 0 2006.245.08:10:22.97#ibcon#read 5, iclass 14, count 0 2006.245.08:10:22.97#ibcon#about to read 6, iclass 14, count 0 2006.245.08:10:22.97#ibcon#read 6, iclass 14, count 0 2006.245.08:10:22.97#ibcon#end of sib2, iclass 14, count 0 2006.245.08:10:22.97#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:10:22.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:10:22.97#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:10:22.97#ibcon#*before write, iclass 14, count 0 2006.245.08:10:22.97#ibcon#enter sib2, iclass 14, count 0 2006.245.08:10:22.97#ibcon#flushed, iclass 14, count 0 2006.245.08:10:22.97#ibcon#about to write, iclass 14, count 0 2006.245.08:10:22.97#ibcon#wrote, iclass 14, count 0 2006.245.08:10:22.97#ibcon#about to read 3, iclass 14, count 0 2006.245.08:10:23.01#ibcon#read 3, iclass 14, count 0 2006.245.08:10:23.01#ibcon#about to read 4, iclass 14, count 0 2006.245.08:10:23.01#ibcon#read 4, iclass 14, count 0 2006.245.08:10:23.01#ibcon#about to read 5, iclass 14, count 0 2006.245.08:10:23.01#ibcon#read 5, iclass 14, count 0 2006.245.08:10:23.01#ibcon#about to read 6, iclass 14, count 0 2006.245.08:10:23.01#ibcon#read 6, iclass 14, count 0 2006.245.08:10:23.01#ibcon#end of sib2, iclass 14, count 0 2006.245.08:10:23.01#ibcon#*after write, iclass 14, count 0 2006.245.08:10:23.01#ibcon#*before return 0, iclass 14, count 0 2006.245.08:10:23.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:23.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:10:23.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:10:23.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:10:23.01$vc4f8/vb=3,4 2006.245.08:10:23.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:10:23.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:10:23.01#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:23.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:23.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:23.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:23.06#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:10:23.06#ibcon#first serial, iclass 16, count 2 2006.245.08:10:23.06#ibcon#enter sib2, iclass 16, count 2 2006.245.08:10:23.06#ibcon#flushed, iclass 16, count 2 2006.245.08:10:23.06#ibcon#about to write, iclass 16, count 2 2006.245.08:10:23.06#ibcon#wrote, iclass 16, count 2 2006.245.08:10:23.06#ibcon#about to read 3, iclass 16, count 2 2006.245.08:10:23.08#ibcon#read 3, iclass 16, count 2 2006.245.08:10:23.08#ibcon#about to read 4, iclass 16, count 2 2006.245.08:10:23.08#ibcon#read 4, iclass 16, count 2 2006.245.08:10:23.08#ibcon#about to read 5, iclass 16, count 2 2006.245.08:10:23.08#ibcon#read 5, iclass 16, count 2 2006.245.08:10:23.08#ibcon#about to read 6, iclass 16, count 2 2006.245.08:10:23.08#ibcon#read 6, iclass 16, count 2 2006.245.08:10:23.08#ibcon#end of sib2, iclass 16, count 2 2006.245.08:10:23.08#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:10:23.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:10:23.08#ibcon#[27=AT03-04\r\n] 2006.245.08:10:23.08#ibcon#*before write, iclass 16, count 2 2006.245.08:10:23.08#ibcon#enter sib2, iclass 16, count 2 2006.245.08:10:23.08#ibcon#flushed, iclass 16, count 2 2006.245.08:10:23.08#ibcon#about to write, iclass 16, count 2 2006.245.08:10:23.08#ibcon#wrote, iclass 16, count 2 2006.245.08:10:23.08#ibcon#about to read 3, iclass 16, count 2 2006.245.08:10:23.11#ibcon#read 3, iclass 16, count 2 2006.245.08:10:23.11#ibcon#about to read 4, iclass 16, count 2 2006.245.08:10:23.11#ibcon#read 4, iclass 16, count 2 2006.245.08:10:23.11#ibcon#about to read 5, iclass 16, count 2 2006.245.08:10:23.11#ibcon#read 5, iclass 16, count 2 2006.245.08:10:23.11#ibcon#about to read 6, iclass 16, count 2 2006.245.08:10:23.11#ibcon#read 6, iclass 16, count 2 2006.245.08:10:23.11#ibcon#end of sib2, iclass 16, count 2 2006.245.08:10:23.11#ibcon#*after write, iclass 16, count 2 2006.245.08:10:23.11#ibcon#*before return 0, iclass 16, count 2 2006.245.08:10:23.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:23.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:10:23.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:10:23.11#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:23.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:23.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:23.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:23.23#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:10:23.23#ibcon#first serial, iclass 16, count 0 2006.245.08:10:23.23#ibcon#enter sib2, iclass 16, count 0 2006.245.08:10:23.23#ibcon#flushed, iclass 16, count 0 2006.245.08:10:23.23#ibcon#about to write, iclass 16, count 0 2006.245.08:10:23.23#ibcon#wrote, iclass 16, count 0 2006.245.08:10:23.23#ibcon#about to read 3, iclass 16, count 0 2006.245.08:10:23.25#ibcon#read 3, iclass 16, count 0 2006.245.08:10:23.25#ibcon#about to read 4, iclass 16, count 0 2006.245.08:10:23.25#ibcon#read 4, iclass 16, count 0 2006.245.08:10:23.25#ibcon#about to read 5, iclass 16, count 0 2006.245.08:10:23.25#ibcon#read 5, iclass 16, count 0 2006.245.08:10:23.25#ibcon#about to read 6, iclass 16, count 0 2006.245.08:10:23.25#ibcon#read 6, iclass 16, count 0 2006.245.08:10:23.25#ibcon#end of sib2, iclass 16, count 0 2006.245.08:10:23.25#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:10:23.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:10:23.25#ibcon#[27=USB\r\n] 2006.245.08:10:23.25#ibcon#*before write, iclass 16, count 0 2006.245.08:10:23.25#ibcon#enter sib2, iclass 16, count 0 2006.245.08:10:23.25#ibcon#flushed, iclass 16, count 0 2006.245.08:10:23.25#ibcon#about to write, iclass 16, count 0 2006.245.08:10:23.25#ibcon#wrote, iclass 16, count 0 2006.245.08:10:23.25#ibcon#about to read 3, iclass 16, count 0 2006.245.08:10:23.28#ibcon#read 3, iclass 16, count 0 2006.245.08:10:23.28#ibcon#about to read 4, iclass 16, count 0 2006.245.08:10:23.28#ibcon#read 4, iclass 16, count 0 2006.245.08:10:23.28#ibcon#about to read 5, iclass 16, count 0 2006.245.08:10:23.28#ibcon#read 5, iclass 16, count 0 2006.245.08:10:23.28#ibcon#about to read 6, iclass 16, count 0 2006.245.08:10:23.28#ibcon#read 6, iclass 16, count 0 2006.245.08:10:23.28#ibcon#end of sib2, iclass 16, count 0 2006.245.08:10:23.28#ibcon#*after write, iclass 16, count 0 2006.245.08:10:23.28#ibcon#*before return 0, iclass 16, count 0 2006.245.08:10:23.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:23.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:10:23.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:10:23.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:10:23.28$vc4f8/vblo=4,712.99 2006.245.08:10:23.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.08:10:23.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.08:10:23.28#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:23.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:23.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:23.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:23.28#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:10:23.28#ibcon#first serial, iclass 18, count 0 2006.245.08:10:23.28#ibcon#enter sib2, iclass 18, count 0 2006.245.08:10:23.28#ibcon#flushed, iclass 18, count 0 2006.245.08:10:23.28#ibcon#about to write, iclass 18, count 0 2006.245.08:10:23.28#ibcon#wrote, iclass 18, count 0 2006.245.08:10:23.28#ibcon#about to read 3, iclass 18, count 0 2006.245.08:10:23.30#ibcon#read 3, iclass 18, count 0 2006.245.08:10:23.30#ibcon#about to read 4, iclass 18, count 0 2006.245.08:10:23.30#ibcon#read 4, iclass 18, count 0 2006.245.08:10:23.30#ibcon#about to read 5, iclass 18, count 0 2006.245.08:10:23.30#ibcon#read 5, iclass 18, count 0 2006.245.08:10:23.30#ibcon#about to read 6, iclass 18, count 0 2006.245.08:10:23.30#ibcon#read 6, iclass 18, count 0 2006.245.08:10:23.30#ibcon#end of sib2, iclass 18, count 0 2006.245.08:10:23.30#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:10:23.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:10:23.30#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:10:23.30#ibcon#*before write, iclass 18, count 0 2006.245.08:10:23.30#ibcon#enter sib2, iclass 18, count 0 2006.245.08:10:23.30#ibcon#flushed, iclass 18, count 0 2006.245.08:10:23.30#ibcon#about to write, iclass 18, count 0 2006.245.08:10:23.30#ibcon#wrote, iclass 18, count 0 2006.245.08:10:23.30#ibcon#about to read 3, iclass 18, count 0 2006.245.08:10:23.34#ibcon#read 3, iclass 18, count 0 2006.245.08:10:23.34#ibcon#about to read 4, iclass 18, count 0 2006.245.08:10:23.34#ibcon#read 4, iclass 18, count 0 2006.245.08:10:23.34#ibcon#about to read 5, iclass 18, count 0 2006.245.08:10:23.34#ibcon#read 5, iclass 18, count 0 2006.245.08:10:23.34#ibcon#about to read 6, iclass 18, count 0 2006.245.08:10:23.34#ibcon#read 6, iclass 18, count 0 2006.245.08:10:23.34#ibcon#end of sib2, iclass 18, count 0 2006.245.08:10:23.34#ibcon#*after write, iclass 18, count 0 2006.245.08:10:23.34#ibcon#*before return 0, iclass 18, count 0 2006.245.08:10:23.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:23.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:10:23.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:10:23.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:10:23.34$vc4f8/vb=4,4 2006.245.08:10:23.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.08:10:23.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.08:10:23.34#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:23.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:23.40#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:23.40#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:23.40#ibcon#enter wrdev, iclass 20, count 2 2006.245.08:10:23.40#ibcon#first serial, iclass 20, count 2 2006.245.08:10:23.40#ibcon#enter sib2, iclass 20, count 2 2006.245.08:10:23.40#ibcon#flushed, iclass 20, count 2 2006.245.08:10:23.40#ibcon#about to write, iclass 20, count 2 2006.245.08:10:23.40#ibcon#wrote, iclass 20, count 2 2006.245.08:10:23.40#ibcon#about to read 3, iclass 20, count 2 2006.245.08:10:23.42#ibcon#read 3, iclass 20, count 2 2006.245.08:10:23.42#ibcon#about to read 4, iclass 20, count 2 2006.245.08:10:23.42#ibcon#read 4, iclass 20, count 2 2006.245.08:10:23.42#ibcon#about to read 5, iclass 20, count 2 2006.245.08:10:23.42#ibcon#read 5, iclass 20, count 2 2006.245.08:10:23.42#ibcon#about to read 6, iclass 20, count 2 2006.245.08:10:23.42#ibcon#read 6, iclass 20, count 2 2006.245.08:10:23.42#ibcon#end of sib2, iclass 20, count 2 2006.245.08:10:23.42#ibcon#*mode == 0, iclass 20, count 2 2006.245.08:10:23.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.08:10:23.42#ibcon#[27=AT04-04\r\n] 2006.245.08:10:23.42#ibcon#*before write, iclass 20, count 2 2006.245.08:10:23.42#ibcon#enter sib2, iclass 20, count 2 2006.245.08:10:23.42#ibcon#flushed, iclass 20, count 2 2006.245.08:10:23.42#ibcon#about to write, iclass 20, count 2 2006.245.08:10:23.42#ibcon#wrote, iclass 20, count 2 2006.245.08:10:23.42#ibcon#about to read 3, iclass 20, count 2 2006.245.08:10:23.45#ibcon#read 3, iclass 20, count 2 2006.245.08:10:23.45#ibcon#about to read 4, iclass 20, count 2 2006.245.08:10:23.45#ibcon#read 4, iclass 20, count 2 2006.245.08:10:23.45#ibcon#about to read 5, iclass 20, count 2 2006.245.08:10:23.45#ibcon#read 5, iclass 20, count 2 2006.245.08:10:23.45#ibcon#about to read 6, iclass 20, count 2 2006.245.08:10:23.45#ibcon#read 6, iclass 20, count 2 2006.245.08:10:23.45#ibcon#end of sib2, iclass 20, count 2 2006.245.08:10:23.45#ibcon#*after write, iclass 20, count 2 2006.245.08:10:23.45#ibcon#*before return 0, iclass 20, count 2 2006.245.08:10:23.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:23.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:10:23.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.08:10:23.45#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:23.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:23.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:23.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:23.57#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:10:23.57#ibcon#first serial, iclass 20, count 0 2006.245.08:10:23.57#ibcon#enter sib2, iclass 20, count 0 2006.245.08:10:23.57#ibcon#flushed, iclass 20, count 0 2006.245.08:10:23.57#ibcon#about to write, iclass 20, count 0 2006.245.08:10:23.57#ibcon#wrote, iclass 20, count 0 2006.245.08:10:23.57#ibcon#about to read 3, iclass 20, count 0 2006.245.08:10:23.59#ibcon#read 3, iclass 20, count 0 2006.245.08:10:23.59#ibcon#about to read 4, iclass 20, count 0 2006.245.08:10:23.59#ibcon#read 4, iclass 20, count 0 2006.245.08:10:23.59#ibcon#about to read 5, iclass 20, count 0 2006.245.08:10:23.59#ibcon#read 5, iclass 20, count 0 2006.245.08:10:23.59#ibcon#about to read 6, iclass 20, count 0 2006.245.08:10:23.59#ibcon#read 6, iclass 20, count 0 2006.245.08:10:23.59#ibcon#end of sib2, iclass 20, count 0 2006.245.08:10:23.59#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:10:23.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:10:23.59#ibcon#[27=USB\r\n] 2006.245.08:10:23.59#ibcon#*before write, iclass 20, count 0 2006.245.08:10:23.59#ibcon#enter sib2, iclass 20, count 0 2006.245.08:10:23.59#ibcon#flushed, iclass 20, count 0 2006.245.08:10:23.59#ibcon#about to write, iclass 20, count 0 2006.245.08:10:23.59#ibcon#wrote, iclass 20, count 0 2006.245.08:10:23.59#ibcon#about to read 3, iclass 20, count 0 2006.245.08:10:23.62#ibcon#read 3, iclass 20, count 0 2006.245.08:10:23.62#ibcon#about to read 4, iclass 20, count 0 2006.245.08:10:23.62#ibcon#read 4, iclass 20, count 0 2006.245.08:10:23.62#ibcon#about to read 5, iclass 20, count 0 2006.245.08:10:23.62#ibcon#read 5, iclass 20, count 0 2006.245.08:10:23.62#ibcon#about to read 6, iclass 20, count 0 2006.245.08:10:23.62#ibcon#read 6, iclass 20, count 0 2006.245.08:10:23.62#ibcon#end of sib2, iclass 20, count 0 2006.245.08:10:23.62#ibcon#*after write, iclass 20, count 0 2006.245.08:10:23.62#ibcon#*before return 0, iclass 20, count 0 2006.245.08:10:23.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:23.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:10:23.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:10:23.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:10:23.62$vc4f8/vblo=5,744.99 2006.245.08:10:23.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:10:23.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:10:23.62#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:23.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:23.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:23.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:23.62#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:10:23.62#ibcon#first serial, iclass 22, count 0 2006.245.08:10:23.62#ibcon#enter sib2, iclass 22, count 0 2006.245.08:10:23.62#ibcon#flushed, iclass 22, count 0 2006.245.08:10:23.62#ibcon#about to write, iclass 22, count 0 2006.245.08:10:23.62#ibcon#wrote, iclass 22, count 0 2006.245.08:10:23.62#ibcon#about to read 3, iclass 22, count 0 2006.245.08:10:23.65#ibcon#read 3, iclass 22, count 0 2006.245.08:10:23.65#ibcon#about to read 4, iclass 22, count 0 2006.245.08:10:23.65#ibcon#read 4, iclass 22, count 0 2006.245.08:10:23.65#ibcon#about to read 5, iclass 22, count 0 2006.245.08:10:23.65#ibcon#read 5, iclass 22, count 0 2006.245.08:10:23.65#ibcon#about to read 6, iclass 22, count 0 2006.245.08:10:23.65#ibcon#read 6, iclass 22, count 0 2006.245.08:10:23.65#ibcon#end of sib2, iclass 22, count 0 2006.245.08:10:23.65#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:10:23.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:10:23.65#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:10:23.65#ibcon#*before write, iclass 22, count 0 2006.245.08:10:23.65#ibcon#enter sib2, iclass 22, count 0 2006.245.08:10:23.65#ibcon#flushed, iclass 22, count 0 2006.245.08:10:23.65#ibcon#about to write, iclass 22, count 0 2006.245.08:10:23.65#ibcon#wrote, iclass 22, count 0 2006.245.08:10:23.65#ibcon#about to read 3, iclass 22, count 0 2006.245.08:10:23.69#ibcon#read 3, iclass 22, count 0 2006.245.08:10:23.69#ibcon#about to read 4, iclass 22, count 0 2006.245.08:10:23.69#ibcon#read 4, iclass 22, count 0 2006.245.08:10:23.69#ibcon#about to read 5, iclass 22, count 0 2006.245.08:10:23.69#ibcon#read 5, iclass 22, count 0 2006.245.08:10:23.69#ibcon#about to read 6, iclass 22, count 0 2006.245.08:10:23.69#ibcon#read 6, iclass 22, count 0 2006.245.08:10:23.69#ibcon#end of sib2, iclass 22, count 0 2006.245.08:10:23.69#ibcon#*after write, iclass 22, count 0 2006.245.08:10:23.69#ibcon#*before return 0, iclass 22, count 0 2006.245.08:10:23.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:23.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:10:23.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:10:23.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:10:23.69$vc4f8/vb=5,3 2006.245.08:10:23.69#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.08:10:23.69#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.08:10:23.69#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:23.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:23.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:23.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:23.74#ibcon#enter wrdev, iclass 24, count 2 2006.245.08:10:23.74#ibcon#first serial, iclass 24, count 2 2006.245.08:10:23.74#ibcon#enter sib2, iclass 24, count 2 2006.245.08:10:23.74#ibcon#flushed, iclass 24, count 2 2006.245.08:10:23.74#ibcon#about to write, iclass 24, count 2 2006.245.08:10:23.74#ibcon#wrote, iclass 24, count 2 2006.245.08:10:23.74#ibcon#about to read 3, iclass 24, count 2 2006.245.08:10:23.76#ibcon#read 3, iclass 24, count 2 2006.245.08:10:23.76#ibcon#about to read 4, iclass 24, count 2 2006.245.08:10:23.76#ibcon#read 4, iclass 24, count 2 2006.245.08:10:23.76#ibcon#about to read 5, iclass 24, count 2 2006.245.08:10:23.76#ibcon#read 5, iclass 24, count 2 2006.245.08:10:23.76#ibcon#about to read 6, iclass 24, count 2 2006.245.08:10:23.76#ibcon#read 6, iclass 24, count 2 2006.245.08:10:23.76#ibcon#end of sib2, iclass 24, count 2 2006.245.08:10:23.76#ibcon#*mode == 0, iclass 24, count 2 2006.245.08:10:23.76#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.08:10:23.76#ibcon#[27=AT05-03\r\n] 2006.245.08:10:23.76#ibcon#*before write, iclass 24, count 2 2006.245.08:10:23.76#ibcon#enter sib2, iclass 24, count 2 2006.245.08:10:23.76#ibcon#flushed, iclass 24, count 2 2006.245.08:10:23.76#ibcon#about to write, iclass 24, count 2 2006.245.08:10:23.76#ibcon#wrote, iclass 24, count 2 2006.245.08:10:23.76#ibcon#about to read 3, iclass 24, count 2 2006.245.08:10:23.79#ibcon#read 3, iclass 24, count 2 2006.245.08:10:23.79#ibcon#about to read 4, iclass 24, count 2 2006.245.08:10:23.79#ibcon#read 4, iclass 24, count 2 2006.245.08:10:23.79#ibcon#about to read 5, iclass 24, count 2 2006.245.08:10:23.79#ibcon#read 5, iclass 24, count 2 2006.245.08:10:23.79#ibcon#about to read 6, iclass 24, count 2 2006.245.08:10:23.79#ibcon#read 6, iclass 24, count 2 2006.245.08:10:23.79#ibcon#end of sib2, iclass 24, count 2 2006.245.08:10:23.79#ibcon#*after write, iclass 24, count 2 2006.245.08:10:23.79#ibcon#*before return 0, iclass 24, count 2 2006.245.08:10:23.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:23.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:10:23.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.08:10:23.79#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:23.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:23.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:23.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:23.91#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:10:23.91#ibcon#first serial, iclass 24, count 0 2006.245.08:10:23.91#ibcon#enter sib2, iclass 24, count 0 2006.245.08:10:23.91#ibcon#flushed, iclass 24, count 0 2006.245.08:10:23.91#ibcon#about to write, iclass 24, count 0 2006.245.08:10:23.91#ibcon#wrote, iclass 24, count 0 2006.245.08:10:23.91#ibcon#about to read 3, iclass 24, count 0 2006.245.08:10:23.93#ibcon#read 3, iclass 24, count 0 2006.245.08:10:23.93#ibcon#about to read 4, iclass 24, count 0 2006.245.08:10:23.93#ibcon#read 4, iclass 24, count 0 2006.245.08:10:23.93#ibcon#about to read 5, iclass 24, count 0 2006.245.08:10:23.93#ibcon#read 5, iclass 24, count 0 2006.245.08:10:23.93#ibcon#about to read 6, iclass 24, count 0 2006.245.08:10:23.93#ibcon#read 6, iclass 24, count 0 2006.245.08:10:23.93#ibcon#end of sib2, iclass 24, count 0 2006.245.08:10:23.93#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:10:23.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:10:23.93#ibcon#[27=USB\r\n] 2006.245.08:10:23.93#ibcon#*before write, iclass 24, count 0 2006.245.08:10:23.93#ibcon#enter sib2, iclass 24, count 0 2006.245.08:10:23.93#ibcon#flushed, iclass 24, count 0 2006.245.08:10:23.93#ibcon#about to write, iclass 24, count 0 2006.245.08:10:23.93#ibcon#wrote, iclass 24, count 0 2006.245.08:10:23.93#ibcon#about to read 3, iclass 24, count 0 2006.245.08:10:23.96#ibcon#read 3, iclass 24, count 0 2006.245.08:10:23.96#ibcon#about to read 4, iclass 24, count 0 2006.245.08:10:23.96#ibcon#read 4, iclass 24, count 0 2006.245.08:10:23.96#ibcon#about to read 5, iclass 24, count 0 2006.245.08:10:23.96#ibcon#read 5, iclass 24, count 0 2006.245.08:10:23.96#ibcon#about to read 6, iclass 24, count 0 2006.245.08:10:23.96#ibcon#read 6, iclass 24, count 0 2006.245.08:10:23.96#ibcon#end of sib2, iclass 24, count 0 2006.245.08:10:23.96#ibcon#*after write, iclass 24, count 0 2006.245.08:10:23.96#ibcon#*before return 0, iclass 24, count 0 2006.245.08:10:23.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:23.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:10:23.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:10:23.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:10:23.96$vc4f8/vblo=6,752.99 2006.245.08:10:23.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.08:10:23.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.08:10:23.96#ibcon#ireg 17 cls_cnt 0 2006.245.08:10:23.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:23.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:23.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:23.96#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:10:23.96#ibcon#first serial, iclass 26, count 0 2006.245.08:10:23.96#ibcon#enter sib2, iclass 26, count 0 2006.245.08:10:23.96#ibcon#flushed, iclass 26, count 0 2006.245.08:10:23.96#ibcon#about to write, iclass 26, count 0 2006.245.08:10:23.96#ibcon#wrote, iclass 26, count 0 2006.245.08:10:23.96#ibcon#about to read 3, iclass 26, count 0 2006.245.08:10:23.98#ibcon#read 3, iclass 26, count 0 2006.245.08:10:23.98#ibcon#about to read 4, iclass 26, count 0 2006.245.08:10:23.98#ibcon#read 4, iclass 26, count 0 2006.245.08:10:23.98#ibcon#about to read 5, iclass 26, count 0 2006.245.08:10:23.98#ibcon#read 5, iclass 26, count 0 2006.245.08:10:23.98#ibcon#about to read 6, iclass 26, count 0 2006.245.08:10:23.98#ibcon#read 6, iclass 26, count 0 2006.245.08:10:23.98#ibcon#end of sib2, iclass 26, count 0 2006.245.08:10:23.98#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:10:23.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:10:23.98#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:10:23.98#ibcon#*before write, iclass 26, count 0 2006.245.08:10:23.98#ibcon#enter sib2, iclass 26, count 0 2006.245.08:10:23.98#ibcon#flushed, iclass 26, count 0 2006.245.08:10:23.98#ibcon#about to write, iclass 26, count 0 2006.245.08:10:23.98#ibcon#wrote, iclass 26, count 0 2006.245.08:10:23.98#ibcon#about to read 3, iclass 26, count 0 2006.245.08:10:24.02#ibcon#read 3, iclass 26, count 0 2006.245.08:10:24.02#ibcon#about to read 4, iclass 26, count 0 2006.245.08:10:24.02#ibcon#read 4, iclass 26, count 0 2006.245.08:10:24.02#ibcon#about to read 5, iclass 26, count 0 2006.245.08:10:24.02#ibcon#read 5, iclass 26, count 0 2006.245.08:10:24.02#ibcon#about to read 6, iclass 26, count 0 2006.245.08:10:24.02#ibcon#read 6, iclass 26, count 0 2006.245.08:10:24.02#ibcon#end of sib2, iclass 26, count 0 2006.245.08:10:24.02#ibcon#*after write, iclass 26, count 0 2006.245.08:10:24.02#ibcon#*before return 0, iclass 26, count 0 2006.245.08:10:24.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:24.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:10:24.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:10:24.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:10:24.02$vc4f8/vb=6,3 2006.245.08:10:24.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.08:10:24.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.08:10:24.02#ibcon#ireg 11 cls_cnt 2 2006.245.08:10:24.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:24.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:24.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:24.08#ibcon#enter wrdev, iclass 28, count 2 2006.245.08:10:24.08#ibcon#first serial, iclass 28, count 2 2006.245.08:10:24.08#ibcon#enter sib2, iclass 28, count 2 2006.245.08:10:24.08#ibcon#flushed, iclass 28, count 2 2006.245.08:10:24.08#ibcon#about to write, iclass 28, count 2 2006.245.08:10:24.08#ibcon#wrote, iclass 28, count 2 2006.245.08:10:24.08#ibcon#about to read 3, iclass 28, count 2 2006.245.08:10:24.10#ibcon#read 3, iclass 28, count 2 2006.245.08:10:24.10#ibcon#about to read 4, iclass 28, count 2 2006.245.08:10:24.10#ibcon#read 4, iclass 28, count 2 2006.245.08:10:24.10#ibcon#about to read 5, iclass 28, count 2 2006.245.08:10:24.10#ibcon#read 5, iclass 28, count 2 2006.245.08:10:24.10#ibcon#about to read 6, iclass 28, count 2 2006.245.08:10:24.10#ibcon#read 6, iclass 28, count 2 2006.245.08:10:24.10#ibcon#end of sib2, iclass 28, count 2 2006.245.08:10:24.10#ibcon#*mode == 0, iclass 28, count 2 2006.245.08:10:24.10#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.08:10:24.10#ibcon#[27=AT06-03\r\n] 2006.245.08:10:24.10#ibcon#*before write, iclass 28, count 2 2006.245.08:10:24.10#ibcon#enter sib2, iclass 28, count 2 2006.245.08:10:24.10#ibcon#flushed, iclass 28, count 2 2006.245.08:10:24.10#ibcon#about to write, iclass 28, count 2 2006.245.08:10:24.10#ibcon#wrote, iclass 28, count 2 2006.245.08:10:24.10#ibcon#about to read 3, iclass 28, count 2 2006.245.08:10:24.13#ibcon#read 3, iclass 28, count 2 2006.245.08:10:24.13#ibcon#about to read 4, iclass 28, count 2 2006.245.08:10:24.13#ibcon#read 4, iclass 28, count 2 2006.245.08:10:24.13#ibcon#about to read 5, iclass 28, count 2 2006.245.08:10:24.13#ibcon#read 5, iclass 28, count 2 2006.245.08:10:24.13#ibcon#about to read 6, iclass 28, count 2 2006.245.08:10:24.13#ibcon#read 6, iclass 28, count 2 2006.245.08:10:24.13#ibcon#end of sib2, iclass 28, count 2 2006.245.08:10:24.13#ibcon#*after write, iclass 28, count 2 2006.245.08:10:24.13#ibcon#*before return 0, iclass 28, count 2 2006.245.08:10:24.13#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:24.13#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:10:24.13#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.08:10:24.13#ibcon#ireg 7 cls_cnt 0 2006.245.08:10:24.13#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:24.25#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:24.25#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:24.25#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:10:24.25#ibcon#first serial, iclass 28, count 0 2006.245.08:10:24.25#ibcon#enter sib2, iclass 28, count 0 2006.245.08:10:24.25#ibcon#flushed, iclass 28, count 0 2006.245.08:10:24.25#ibcon#about to write, iclass 28, count 0 2006.245.08:10:24.25#ibcon#wrote, iclass 28, count 0 2006.245.08:10:24.25#ibcon#about to read 3, iclass 28, count 0 2006.245.08:10:24.27#ibcon#read 3, iclass 28, count 0 2006.245.08:10:24.27#ibcon#about to read 4, iclass 28, count 0 2006.245.08:10:24.27#ibcon#read 4, iclass 28, count 0 2006.245.08:10:24.27#ibcon#about to read 5, iclass 28, count 0 2006.245.08:10:24.27#ibcon#read 5, iclass 28, count 0 2006.245.08:10:24.27#ibcon#about to read 6, iclass 28, count 0 2006.245.08:10:24.27#ibcon#read 6, iclass 28, count 0 2006.245.08:10:24.27#ibcon#end of sib2, iclass 28, count 0 2006.245.08:10:24.27#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:10:24.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:10:24.27#ibcon#[27=USB\r\n] 2006.245.08:10:24.27#ibcon#*before write, iclass 28, count 0 2006.245.08:10:24.27#ibcon#enter sib2, iclass 28, count 0 2006.245.08:10:24.27#ibcon#flushed, iclass 28, count 0 2006.245.08:10:24.27#ibcon#about to write, iclass 28, count 0 2006.245.08:10:24.27#ibcon#wrote, iclass 28, count 0 2006.245.08:10:24.27#ibcon#about to read 3, iclass 28, count 0 2006.245.08:10:24.30#ibcon#read 3, iclass 28, count 0 2006.245.08:10:24.30#ibcon#about to read 4, iclass 28, count 0 2006.245.08:10:24.30#ibcon#read 4, iclass 28, count 0 2006.245.08:10:24.30#ibcon#about to read 5, iclass 28, count 0 2006.245.08:10:24.30#ibcon#read 5, iclass 28, count 0 2006.245.08:10:24.30#ibcon#about to read 6, iclass 28, count 0 2006.245.08:10:24.30#ibcon#read 6, iclass 28, count 0 2006.245.08:10:24.30#ibcon#end of sib2, iclass 28, count 0 2006.245.08:10:24.30#ibcon#*after write, iclass 28, count 0 2006.245.08:10:24.30#ibcon#*before return 0, iclass 28, count 0 2006.245.08:10:24.30#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:24.30#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:10:24.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:10:24.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:10:24.30$vc4f8/vabw=wide 2006.245.08:10:24.30#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.08:10:24.30#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.08:10:24.30#ibcon#ireg 8 cls_cnt 0 2006.245.08:10:24.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:24.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:24.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:24.30#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:10:24.30#ibcon#first serial, iclass 30, count 0 2006.245.08:10:24.30#ibcon#enter sib2, iclass 30, count 0 2006.245.08:10:24.30#ibcon#flushed, iclass 30, count 0 2006.245.08:10:24.30#ibcon#about to write, iclass 30, count 0 2006.245.08:10:24.30#ibcon#wrote, iclass 30, count 0 2006.245.08:10:24.30#ibcon#about to read 3, iclass 30, count 0 2006.245.08:10:24.32#ibcon#read 3, iclass 30, count 0 2006.245.08:10:24.32#ibcon#about to read 4, iclass 30, count 0 2006.245.08:10:24.32#ibcon#read 4, iclass 30, count 0 2006.245.08:10:24.32#ibcon#about to read 5, iclass 30, count 0 2006.245.08:10:24.32#ibcon#read 5, iclass 30, count 0 2006.245.08:10:24.32#ibcon#about to read 6, iclass 30, count 0 2006.245.08:10:24.32#ibcon#read 6, iclass 30, count 0 2006.245.08:10:24.32#ibcon#end of sib2, iclass 30, count 0 2006.245.08:10:24.32#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:10:24.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:10:24.32#ibcon#[25=BW32\r\n] 2006.245.08:10:24.32#ibcon#*before write, iclass 30, count 0 2006.245.08:10:24.32#ibcon#enter sib2, iclass 30, count 0 2006.245.08:10:24.32#ibcon#flushed, iclass 30, count 0 2006.245.08:10:24.32#ibcon#about to write, iclass 30, count 0 2006.245.08:10:24.32#ibcon#wrote, iclass 30, count 0 2006.245.08:10:24.32#ibcon#about to read 3, iclass 30, count 0 2006.245.08:10:24.35#ibcon#read 3, iclass 30, count 0 2006.245.08:10:24.35#ibcon#about to read 4, iclass 30, count 0 2006.245.08:10:24.35#ibcon#read 4, iclass 30, count 0 2006.245.08:10:24.35#ibcon#about to read 5, iclass 30, count 0 2006.245.08:10:24.35#ibcon#read 5, iclass 30, count 0 2006.245.08:10:24.35#ibcon#about to read 6, iclass 30, count 0 2006.245.08:10:24.35#ibcon#read 6, iclass 30, count 0 2006.245.08:10:24.35#ibcon#end of sib2, iclass 30, count 0 2006.245.08:10:24.35#ibcon#*after write, iclass 30, count 0 2006.245.08:10:24.35#ibcon#*before return 0, iclass 30, count 0 2006.245.08:10:24.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:24.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:10:24.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:10:24.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:10:24.35$vc4f8/vbbw=wide 2006.245.08:10:24.35#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.08:10:24.35#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.08:10:24.35#ibcon#ireg 8 cls_cnt 0 2006.245.08:10:24.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:10:24.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:10:24.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:10:24.42#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:10:24.42#ibcon#first serial, iclass 32, count 0 2006.245.08:10:24.42#ibcon#enter sib2, iclass 32, count 0 2006.245.08:10:24.42#ibcon#flushed, iclass 32, count 0 2006.245.08:10:24.42#ibcon#about to write, iclass 32, count 0 2006.245.08:10:24.42#ibcon#wrote, iclass 32, count 0 2006.245.08:10:24.42#ibcon#about to read 3, iclass 32, count 0 2006.245.08:10:24.44#ibcon#read 3, iclass 32, count 0 2006.245.08:10:24.44#ibcon#about to read 4, iclass 32, count 0 2006.245.08:10:24.44#ibcon#read 4, iclass 32, count 0 2006.245.08:10:24.44#ibcon#about to read 5, iclass 32, count 0 2006.245.08:10:24.44#ibcon#read 5, iclass 32, count 0 2006.245.08:10:24.44#ibcon#about to read 6, iclass 32, count 0 2006.245.08:10:24.44#ibcon#read 6, iclass 32, count 0 2006.245.08:10:24.44#ibcon#end of sib2, iclass 32, count 0 2006.245.08:10:24.44#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:10:24.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:10:24.44#ibcon#[27=BW32\r\n] 2006.245.08:10:24.44#ibcon#*before write, iclass 32, count 0 2006.245.08:10:24.44#ibcon#enter sib2, iclass 32, count 0 2006.245.08:10:24.44#ibcon#flushed, iclass 32, count 0 2006.245.08:10:24.44#ibcon#about to write, iclass 32, count 0 2006.245.08:10:24.44#ibcon#wrote, iclass 32, count 0 2006.245.08:10:24.44#ibcon#about to read 3, iclass 32, count 0 2006.245.08:10:24.47#ibcon#read 3, iclass 32, count 0 2006.245.08:10:24.47#ibcon#about to read 4, iclass 32, count 0 2006.245.08:10:24.47#ibcon#read 4, iclass 32, count 0 2006.245.08:10:24.47#ibcon#about to read 5, iclass 32, count 0 2006.245.08:10:24.47#ibcon#read 5, iclass 32, count 0 2006.245.08:10:24.47#ibcon#about to read 6, iclass 32, count 0 2006.245.08:10:24.47#ibcon#read 6, iclass 32, count 0 2006.245.08:10:24.47#ibcon#end of sib2, iclass 32, count 0 2006.245.08:10:24.47#ibcon#*after write, iclass 32, count 0 2006.245.08:10:24.47#ibcon#*before return 0, iclass 32, count 0 2006.245.08:10:24.47#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:10:24.47#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:10:24.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:10:24.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:10:24.47$4f8m12a/ifd4f 2006.245.08:10:24.47$ifd4f/lo= 2006.245.08:10:24.47$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:10:24.47$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:10:24.47$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:10:24.47$ifd4f/patch= 2006.245.08:10:24.47$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:10:24.47$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:10:24.47$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:10:24.47$4f8m12a/"form=m,16.000,1:2 2006.245.08:10:24.47$4f8m12a/"tpicd 2006.245.08:10:24.47$4f8m12a/echo=off 2006.245.08:10:24.47$4f8m12a/xlog=off 2006.245.08:10:24.47:!2006.245.08:10:50 2006.245.08:10:33.14#trakl#Source acquired 2006.245.08:10:35.14#flagr#flagr/antenna,acquired 2006.245.08:10:50.00:preob 2006.245.08:10:51.14/onsource/TRACKING 2006.245.08:10:51.14:!2006.245.08:11:00 2006.245.08:11:00.00:data_valid=on 2006.245.08:11:00.00:midob 2006.245.08:11:00.14/onsource/TRACKING 2006.245.08:11:00.14/wx/26.94,1004.5,73 2006.245.08:11:00.30/cable/+6.4105E-03 2006.245.08:11:01.39/va/01,08,usb,yes,31,32 2006.245.08:11:01.39/va/02,07,usb,yes,30,32 2006.245.08:11:01.39/va/03,06,usb,yes,32,33 2006.245.08:11:01.39/va/04,07,usb,yes,32,34 2006.245.08:11:01.39/va/05,07,usb,yes,33,35 2006.245.08:11:01.39/va/06,07,usb,yes,29,29 2006.245.08:11:01.39/va/07,07,usb,yes,29,29 2006.245.08:11:01.39/va/08,08,usb,yes,25,25 2006.245.08:11:01.62/valo/01,532.99,yes,locked 2006.245.08:11:01.62/valo/02,572.99,yes,locked 2006.245.08:11:01.62/valo/03,672.99,yes,locked 2006.245.08:11:01.62/valo/04,832.99,yes,locked 2006.245.08:11:01.62/valo/05,652.99,yes,locked 2006.245.08:11:01.62/valo/06,772.99,yes,locked 2006.245.08:11:01.62/valo/07,832.99,yes,locked 2006.245.08:11:01.62/valo/08,852.99,yes,locked 2006.245.08:11:02.71/vb/01,04,usb,yes,30,29 2006.245.08:11:02.71/vb/02,04,usb,yes,32,33 2006.245.08:11:02.71/vb/03,04,usb,yes,28,32 2006.245.08:11:02.71/vb/04,04,usb,yes,29,29 2006.245.08:11:02.71/vb/05,03,usb,yes,34,39 2006.245.08:11:02.71/vb/06,03,usb,yes,35,39 2006.245.08:11:02.71/vb/07,04,usb,yes,31,30 2006.245.08:11:02.71/vb/08,03,usb,yes,35,39 2006.245.08:11:02.95/vblo/01,632.99,yes,locked 2006.245.08:11:02.95/vblo/02,640.99,yes,locked 2006.245.08:11:02.95/vblo/03,656.99,yes,locked 2006.245.08:11:02.95/vblo/04,712.99,yes,locked 2006.245.08:11:02.95/vblo/05,744.99,yes,locked 2006.245.08:11:02.95/vblo/06,752.99,yes,locked 2006.245.08:11:02.95/vblo/07,734.99,yes,locked 2006.245.08:11:02.95/vblo/08,744.99,yes,locked 2006.245.08:11:03.10/vabw/8 2006.245.08:11:03.25/vbbw/8 2006.245.08:11:03.36/xfe/off,on,13.7 2006.245.08:11:03.75/ifatt/23,28,28,28 2006.245.08:11:04.08/fmout-gps/S +4.39E-07 2006.245.08:11:04.12:!2006.245.08:12:00 2006.245.08:12:00.00:data_valid=off 2006.245.08:12:00.00:postob 2006.245.08:12:00.11/cable/+6.4106E-03 2006.245.08:12:00.11/wx/26.92,1004.5,73 2006.245.08:12:01.07/fmout-gps/S +4.40E-07 2006.245.08:12:01.07:scan_name=245-0812,k06245,60 2006.245.08:12:01.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.245.08:12:01.14#flagr#flagr/antenna,new-source 2006.245.08:12:02.14:checkk5 2006.245.08:12:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:12:03.02/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:12:03.45/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:12:03.87/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:12:04.27/chk_obsdata//k5ts1/T2450811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:12:04.72/chk_obsdata//k5ts2/T2450811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:12:05.15/chk_obsdata//k5ts3/T2450811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:12:05.80/chk_obsdata//k5ts4/T2450811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:12:06.89/k5log//k5ts1_log_newline 2006.245.08:12:07.89/k5log//k5ts2_log_newline 2006.245.08:12:08.69/k5log//k5ts3_log_newline 2006.245.08:12:14.50/k5log//k5ts4_log_newline 2006.245.08:12:14.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:12:14.52:4f8m12a=2 2006.245.08:12:14.52$4f8m12a/echo=on 2006.245.08:12:14.52$4f8m12a/pcalon 2006.245.08:12:14.52$pcalon/"no phase cal control is implemented here 2006.245.08:12:14.52$4f8m12a/"tpicd=stop 2006.245.08:12:14.52$4f8m12a/vc4f8 2006.245.08:12:14.52$vc4f8/valo=1,532.99 2006.245.08:12:14.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.08:12:14.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.08:12:14.53#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:14.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:14.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:14.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:14.53#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:12:14.53#ibcon#first serial, iclass 5, count 0 2006.245.08:12:14.53#ibcon#enter sib2, iclass 5, count 0 2006.245.08:12:14.53#ibcon#flushed, iclass 5, count 0 2006.245.08:12:14.53#ibcon#about to write, iclass 5, count 0 2006.245.08:12:14.53#ibcon#wrote, iclass 5, count 0 2006.245.08:12:14.53#ibcon#about to read 3, iclass 5, count 0 2006.245.08:12:14.57#ibcon#read 3, iclass 5, count 0 2006.245.08:12:14.57#ibcon#about to read 4, iclass 5, count 0 2006.245.08:12:14.57#ibcon#read 4, iclass 5, count 0 2006.245.08:12:14.57#ibcon#about to read 5, iclass 5, count 0 2006.245.08:12:14.57#ibcon#read 5, iclass 5, count 0 2006.245.08:12:14.57#ibcon#about to read 6, iclass 5, count 0 2006.245.08:12:14.57#ibcon#read 6, iclass 5, count 0 2006.245.08:12:14.57#ibcon#end of sib2, iclass 5, count 0 2006.245.08:12:14.57#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:12:14.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:12:14.57#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:12:14.57#ibcon#*before write, iclass 5, count 0 2006.245.08:12:14.57#ibcon#enter sib2, iclass 5, count 0 2006.245.08:12:14.57#ibcon#flushed, iclass 5, count 0 2006.245.08:12:14.57#ibcon#about to write, iclass 5, count 0 2006.245.08:12:14.57#ibcon#wrote, iclass 5, count 0 2006.245.08:12:14.57#ibcon#about to read 3, iclass 5, count 0 2006.245.08:12:14.62#ibcon#read 3, iclass 5, count 0 2006.245.08:12:14.62#ibcon#about to read 4, iclass 5, count 0 2006.245.08:12:14.62#ibcon#read 4, iclass 5, count 0 2006.245.08:12:14.62#ibcon#about to read 5, iclass 5, count 0 2006.245.08:12:14.62#ibcon#read 5, iclass 5, count 0 2006.245.08:12:14.62#ibcon#about to read 6, iclass 5, count 0 2006.245.08:12:14.62#ibcon#read 6, iclass 5, count 0 2006.245.08:12:14.62#ibcon#end of sib2, iclass 5, count 0 2006.245.08:12:14.62#ibcon#*after write, iclass 5, count 0 2006.245.08:12:14.62#ibcon#*before return 0, iclass 5, count 0 2006.245.08:12:14.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:14.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:14.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:12:14.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:12:14.62$vc4f8/va=1,8 2006.245.08:12:14.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.08:12:14.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.08:12:14.62#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:14.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:14.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:14.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:14.62#ibcon#enter wrdev, iclass 7, count 2 2006.245.08:12:14.62#ibcon#first serial, iclass 7, count 2 2006.245.08:12:14.62#ibcon#enter sib2, iclass 7, count 2 2006.245.08:12:14.62#ibcon#flushed, iclass 7, count 2 2006.245.08:12:14.62#ibcon#about to write, iclass 7, count 2 2006.245.08:12:14.62#ibcon#wrote, iclass 7, count 2 2006.245.08:12:14.62#ibcon#about to read 3, iclass 7, count 2 2006.245.08:12:14.64#ibcon#read 3, iclass 7, count 2 2006.245.08:12:14.64#ibcon#about to read 4, iclass 7, count 2 2006.245.08:12:14.64#ibcon#read 4, iclass 7, count 2 2006.245.08:12:14.64#ibcon#about to read 5, iclass 7, count 2 2006.245.08:12:14.64#ibcon#read 5, iclass 7, count 2 2006.245.08:12:14.64#ibcon#about to read 6, iclass 7, count 2 2006.245.08:12:14.64#ibcon#read 6, iclass 7, count 2 2006.245.08:12:14.64#ibcon#end of sib2, iclass 7, count 2 2006.245.08:12:14.64#ibcon#*mode == 0, iclass 7, count 2 2006.245.08:12:14.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.08:12:14.64#ibcon#[25=AT01-08\r\n] 2006.245.08:12:14.64#ibcon#*before write, iclass 7, count 2 2006.245.08:12:14.64#ibcon#enter sib2, iclass 7, count 2 2006.245.08:12:14.64#ibcon#flushed, iclass 7, count 2 2006.245.08:12:14.64#ibcon#about to write, iclass 7, count 2 2006.245.08:12:14.64#ibcon#wrote, iclass 7, count 2 2006.245.08:12:14.64#ibcon#about to read 3, iclass 7, count 2 2006.245.08:12:14.67#ibcon#read 3, iclass 7, count 2 2006.245.08:12:14.67#ibcon#about to read 4, iclass 7, count 2 2006.245.08:12:14.67#ibcon#read 4, iclass 7, count 2 2006.245.08:12:14.67#ibcon#about to read 5, iclass 7, count 2 2006.245.08:12:14.67#ibcon#read 5, iclass 7, count 2 2006.245.08:12:14.67#ibcon#about to read 6, iclass 7, count 2 2006.245.08:12:14.67#ibcon#read 6, iclass 7, count 2 2006.245.08:12:14.67#ibcon#end of sib2, iclass 7, count 2 2006.245.08:12:14.67#ibcon#*after write, iclass 7, count 2 2006.245.08:12:14.67#ibcon#*before return 0, iclass 7, count 2 2006.245.08:12:14.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:14.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:14.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.08:12:14.67#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:14.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:14.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:14.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:14.79#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:12:14.79#ibcon#first serial, iclass 7, count 0 2006.245.08:12:14.79#ibcon#enter sib2, iclass 7, count 0 2006.245.08:12:14.79#ibcon#flushed, iclass 7, count 0 2006.245.08:12:14.79#ibcon#about to write, iclass 7, count 0 2006.245.08:12:14.79#ibcon#wrote, iclass 7, count 0 2006.245.08:12:14.79#ibcon#about to read 3, iclass 7, count 0 2006.245.08:12:14.81#ibcon#read 3, iclass 7, count 0 2006.245.08:12:14.81#ibcon#about to read 4, iclass 7, count 0 2006.245.08:12:14.81#ibcon#read 4, iclass 7, count 0 2006.245.08:12:14.81#ibcon#about to read 5, iclass 7, count 0 2006.245.08:12:14.81#ibcon#read 5, iclass 7, count 0 2006.245.08:12:14.81#ibcon#about to read 6, iclass 7, count 0 2006.245.08:12:14.81#ibcon#read 6, iclass 7, count 0 2006.245.08:12:14.81#ibcon#end of sib2, iclass 7, count 0 2006.245.08:12:14.81#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:12:14.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:12:14.81#ibcon#[25=USB\r\n] 2006.245.08:12:14.81#ibcon#*before write, iclass 7, count 0 2006.245.08:12:14.81#ibcon#enter sib2, iclass 7, count 0 2006.245.08:12:14.81#ibcon#flushed, iclass 7, count 0 2006.245.08:12:14.81#ibcon#about to write, iclass 7, count 0 2006.245.08:12:14.81#ibcon#wrote, iclass 7, count 0 2006.245.08:12:14.81#ibcon#about to read 3, iclass 7, count 0 2006.245.08:12:14.84#ibcon#read 3, iclass 7, count 0 2006.245.08:12:14.84#ibcon#about to read 4, iclass 7, count 0 2006.245.08:12:14.84#ibcon#read 4, iclass 7, count 0 2006.245.08:12:14.84#ibcon#about to read 5, iclass 7, count 0 2006.245.08:12:14.84#ibcon#read 5, iclass 7, count 0 2006.245.08:12:14.84#ibcon#about to read 6, iclass 7, count 0 2006.245.08:12:14.84#ibcon#read 6, iclass 7, count 0 2006.245.08:12:14.84#ibcon#end of sib2, iclass 7, count 0 2006.245.08:12:14.84#ibcon#*after write, iclass 7, count 0 2006.245.08:12:14.84#ibcon#*before return 0, iclass 7, count 0 2006.245.08:12:14.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:14.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:14.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:12:14.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:12:14.84$vc4f8/valo=2,572.99 2006.245.08:12:14.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.08:12:14.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.08:12:14.84#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:14.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:14.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:14.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:14.84#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:12:14.84#ibcon#first serial, iclass 11, count 0 2006.245.08:12:14.84#ibcon#enter sib2, iclass 11, count 0 2006.245.08:12:14.84#ibcon#flushed, iclass 11, count 0 2006.245.08:12:14.84#ibcon#about to write, iclass 11, count 0 2006.245.08:12:14.84#ibcon#wrote, iclass 11, count 0 2006.245.08:12:14.84#ibcon#about to read 3, iclass 11, count 0 2006.245.08:12:14.86#ibcon#read 3, iclass 11, count 0 2006.245.08:12:14.86#ibcon#about to read 4, iclass 11, count 0 2006.245.08:12:14.86#ibcon#read 4, iclass 11, count 0 2006.245.08:12:14.86#ibcon#about to read 5, iclass 11, count 0 2006.245.08:12:14.86#ibcon#read 5, iclass 11, count 0 2006.245.08:12:14.86#ibcon#about to read 6, iclass 11, count 0 2006.245.08:12:14.86#ibcon#read 6, iclass 11, count 0 2006.245.08:12:14.86#ibcon#end of sib2, iclass 11, count 0 2006.245.08:12:14.86#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:12:14.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:12:14.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:12:14.86#ibcon#*before write, iclass 11, count 0 2006.245.08:12:14.86#ibcon#enter sib2, iclass 11, count 0 2006.245.08:12:14.86#ibcon#flushed, iclass 11, count 0 2006.245.08:12:14.86#ibcon#about to write, iclass 11, count 0 2006.245.08:12:14.86#ibcon#wrote, iclass 11, count 0 2006.245.08:12:14.86#ibcon#about to read 3, iclass 11, count 0 2006.245.08:12:14.90#ibcon#read 3, iclass 11, count 0 2006.245.08:12:14.90#ibcon#about to read 4, iclass 11, count 0 2006.245.08:12:14.90#ibcon#read 4, iclass 11, count 0 2006.245.08:12:14.90#ibcon#about to read 5, iclass 11, count 0 2006.245.08:12:14.90#ibcon#read 5, iclass 11, count 0 2006.245.08:12:14.90#ibcon#about to read 6, iclass 11, count 0 2006.245.08:12:14.90#ibcon#read 6, iclass 11, count 0 2006.245.08:12:14.90#ibcon#end of sib2, iclass 11, count 0 2006.245.08:12:14.90#ibcon#*after write, iclass 11, count 0 2006.245.08:12:14.90#ibcon#*before return 0, iclass 11, count 0 2006.245.08:12:14.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:14.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:14.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:12:14.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:12:14.90$vc4f8/va=2,7 2006.245.08:12:14.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:12:14.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:12:14.90#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:14.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:14.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:14.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:14.97#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:12:14.97#ibcon#first serial, iclass 13, count 2 2006.245.08:12:14.97#ibcon#enter sib2, iclass 13, count 2 2006.245.08:12:14.97#ibcon#flushed, iclass 13, count 2 2006.245.08:12:14.97#ibcon#about to write, iclass 13, count 2 2006.245.08:12:14.97#ibcon#wrote, iclass 13, count 2 2006.245.08:12:14.97#ibcon#about to read 3, iclass 13, count 2 2006.245.08:12:14.98#ibcon#read 3, iclass 13, count 2 2006.245.08:12:14.98#ibcon#about to read 4, iclass 13, count 2 2006.245.08:12:14.98#ibcon#read 4, iclass 13, count 2 2006.245.08:12:14.98#ibcon#about to read 5, iclass 13, count 2 2006.245.08:12:14.98#ibcon#read 5, iclass 13, count 2 2006.245.08:12:14.98#ibcon#about to read 6, iclass 13, count 2 2006.245.08:12:14.98#ibcon#read 6, iclass 13, count 2 2006.245.08:12:14.98#ibcon#end of sib2, iclass 13, count 2 2006.245.08:12:14.98#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:12:14.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:12:14.98#ibcon#[25=AT02-07\r\n] 2006.245.08:12:14.98#ibcon#*before write, iclass 13, count 2 2006.245.08:12:14.98#ibcon#enter sib2, iclass 13, count 2 2006.245.08:12:14.98#ibcon#flushed, iclass 13, count 2 2006.245.08:12:14.98#ibcon#about to write, iclass 13, count 2 2006.245.08:12:14.98#ibcon#wrote, iclass 13, count 2 2006.245.08:12:14.98#ibcon#about to read 3, iclass 13, count 2 2006.245.08:12:15.01#ibcon#read 3, iclass 13, count 2 2006.245.08:12:15.01#ibcon#about to read 4, iclass 13, count 2 2006.245.08:12:15.01#ibcon#read 4, iclass 13, count 2 2006.245.08:12:15.01#ibcon#about to read 5, iclass 13, count 2 2006.245.08:12:15.01#ibcon#read 5, iclass 13, count 2 2006.245.08:12:15.01#ibcon#about to read 6, iclass 13, count 2 2006.245.08:12:15.01#ibcon#read 6, iclass 13, count 2 2006.245.08:12:15.01#ibcon#end of sib2, iclass 13, count 2 2006.245.08:12:15.01#ibcon#*after write, iclass 13, count 2 2006.245.08:12:15.01#ibcon#*before return 0, iclass 13, count 2 2006.245.08:12:15.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:15.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:15.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:12:15.01#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:15.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:15.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:15.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:15.13#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:12:15.13#ibcon#first serial, iclass 13, count 0 2006.245.08:12:15.13#ibcon#enter sib2, iclass 13, count 0 2006.245.08:12:15.13#ibcon#flushed, iclass 13, count 0 2006.245.08:12:15.13#ibcon#about to write, iclass 13, count 0 2006.245.08:12:15.13#ibcon#wrote, iclass 13, count 0 2006.245.08:12:15.13#ibcon#about to read 3, iclass 13, count 0 2006.245.08:12:15.15#ibcon#read 3, iclass 13, count 0 2006.245.08:12:15.15#ibcon#about to read 4, iclass 13, count 0 2006.245.08:12:15.15#ibcon#read 4, iclass 13, count 0 2006.245.08:12:15.15#ibcon#about to read 5, iclass 13, count 0 2006.245.08:12:15.15#ibcon#read 5, iclass 13, count 0 2006.245.08:12:15.15#ibcon#about to read 6, iclass 13, count 0 2006.245.08:12:15.15#ibcon#read 6, iclass 13, count 0 2006.245.08:12:15.15#ibcon#end of sib2, iclass 13, count 0 2006.245.08:12:15.15#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:12:15.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:12:15.15#ibcon#[25=USB\r\n] 2006.245.08:12:15.15#ibcon#*before write, iclass 13, count 0 2006.245.08:12:15.15#ibcon#enter sib2, iclass 13, count 0 2006.245.08:12:15.15#ibcon#flushed, iclass 13, count 0 2006.245.08:12:15.15#ibcon#about to write, iclass 13, count 0 2006.245.08:12:15.15#ibcon#wrote, iclass 13, count 0 2006.245.08:12:15.15#ibcon#about to read 3, iclass 13, count 0 2006.245.08:12:15.18#ibcon#read 3, iclass 13, count 0 2006.245.08:12:15.18#ibcon#about to read 4, iclass 13, count 0 2006.245.08:12:15.18#ibcon#read 4, iclass 13, count 0 2006.245.08:12:15.18#ibcon#about to read 5, iclass 13, count 0 2006.245.08:12:15.18#ibcon#read 5, iclass 13, count 0 2006.245.08:12:15.18#ibcon#about to read 6, iclass 13, count 0 2006.245.08:12:15.18#ibcon#read 6, iclass 13, count 0 2006.245.08:12:15.18#ibcon#end of sib2, iclass 13, count 0 2006.245.08:12:15.18#ibcon#*after write, iclass 13, count 0 2006.245.08:12:15.18#ibcon#*before return 0, iclass 13, count 0 2006.245.08:12:15.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:15.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:15.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:12:15.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:12:15.18$vc4f8/valo=3,672.99 2006.245.08:12:15.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.08:12:15.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.08:12:15.18#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:15.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:15.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:15.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:15.18#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:12:15.18#ibcon#first serial, iclass 15, count 0 2006.245.08:12:15.18#ibcon#enter sib2, iclass 15, count 0 2006.245.08:12:15.18#ibcon#flushed, iclass 15, count 0 2006.245.08:12:15.18#ibcon#about to write, iclass 15, count 0 2006.245.08:12:15.18#ibcon#wrote, iclass 15, count 0 2006.245.08:12:15.18#ibcon#about to read 3, iclass 15, count 0 2006.245.08:12:15.21#ibcon#read 3, iclass 15, count 0 2006.245.08:12:15.21#ibcon#about to read 4, iclass 15, count 0 2006.245.08:12:15.21#ibcon#read 4, iclass 15, count 0 2006.245.08:12:15.21#ibcon#about to read 5, iclass 15, count 0 2006.245.08:12:15.21#ibcon#read 5, iclass 15, count 0 2006.245.08:12:15.21#ibcon#about to read 6, iclass 15, count 0 2006.245.08:12:15.21#ibcon#read 6, iclass 15, count 0 2006.245.08:12:15.21#ibcon#end of sib2, iclass 15, count 0 2006.245.08:12:15.21#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:12:15.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:12:15.21#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:12:15.21#ibcon#*before write, iclass 15, count 0 2006.245.08:12:15.21#ibcon#enter sib2, iclass 15, count 0 2006.245.08:12:15.21#ibcon#flushed, iclass 15, count 0 2006.245.08:12:15.21#ibcon#about to write, iclass 15, count 0 2006.245.08:12:15.21#ibcon#wrote, iclass 15, count 0 2006.245.08:12:15.21#ibcon#about to read 3, iclass 15, count 0 2006.245.08:12:15.25#ibcon#read 3, iclass 15, count 0 2006.245.08:12:15.25#ibcon#about to read 4, iclass 15, count 0 2006.245.08:12:15.25#ibcon#read 4, iclass 15, count 0 2006.245.08:12:15.25#ibcon#about to read 5, iclass 15, count 0 2006.245.08:12:15.25#ibcon#read 5, iclass 15, count 0 2006.245.08:12:15.25#ibcon#about to read 6, iclass 15, count 0 2006.245.08:12:15.25#ibcon#read 6, iclass 15, count 0 2006.245.08:12:15.25#ibcon#end of sib2, iclass 15, count 0 2006.245.08:12:15.25#ibcon#*after write, iclass 15, count 0 2006.245.08:12:15.25#ibcon#*before return 0, iclass 15, count 0 2006.245.08:12:15.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:15.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:15.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:12:15.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:12:15.25$vc4f8/va=3,6 2006.245.08:12:15.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.08:12:15.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.08:12:15.25#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:15.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:15.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:15.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:15.30#ibcon#enter wrdev, iclass 17, count 2 2006.245.08:12:15.30#ibcon#first serial, iclass 17, count 2 2006.245.08:12:15.30#ibcon#enter sib2, iclass 17, count 2 2006.245.08:12:15.30#ibcon#flushed, iclass 17, count 2 2006.245.08:12:15.30#ibcon#about to write, iclass 17, count 2 2006.245.08:12:15.30#ibcon#wrote, iclass 17, count 2 2006.245.08:12:15.30#ibcon#about to read 3, iclass 17, count 2 2006.245.08:12:15.32#ibcon#read 3, iclass 17, count 2 2006.245.08:12:15.32#ibcon#about to read 4, iclass 17, count 2 2006.245.08:12:15.32#ibcon#read 4, iclass 17, count 2 2006.245.08:12:15.32#ibcon#about to read 5, iclass 17, count 2 2006.245.08:12:15.32#ibcon#read 5, iclass 17, count 2 2006.245.08:12:15.32#ibcon#about to read 6, iclass 17, count 2 2006.245.08:12:15.32#ibcon#read 6, iclass 17, count 2 2006.245.08:12:15.32#ibcon#end of sib2, iclass 17, count 2 2006.245.08:12:15.32#ibcon#*mode == 0, iclass 17, count 2 2006.245.08:12:15.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.08:12:15.32#ibcon#[25=AT03-06\r\n] 2006.245.08:12:15.32#ibcon#*before write, iclass 17, count 2 2006.245.08:12:15.32#ibcon#enter sib2, iclass 17, count 2 2006.245.08:12:15.32#ibcon#flushed, iclass 17, count 2 2006.245.08:12:15.32#ibcon#about to write, iclass 17, count 2 2006.245.08:12:15.32#ibcon#wrote, iclass 17, count 2 2006.245.08:12:15.32#ibcon#about to read 3, iclass 17, count 2 2006.245.08:12:15.35#ibcon#read 3, iclass 17, count 2 2006.245.08:12:15.35#ibcon#about to read 4, iclass 17, count 2 2006.245.08:12:15.35#ibcon#read 4, iclass 17, count 2 2006.245.08:12:15.35#ibcon#about to read 5, iclass 17, count 2 2006.245.08:12:15.35#ibcon#read 5, iclass 17, count 2 2006.245.08:12:15.35#ibcon#about to read 6, iclass 17, count 2 2006.245.08:12:15.35#ibcon#read 6, iclass 17, count 2 2006.245.08:12:15.35#ibcon#end of sib2, iclass 17, count 2 2006.245.08:12:15.35#ibcon#*after write, iclass 17, count 2 2006.245.08:12:15.35#ibcon#*before return 0, iclass 17, count 2 2006.245.08:12:15.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:15.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:15.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.08:12:15.35#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:15.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:15.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:15.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:15.47#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:12:15.47#ibcon#first serial, iclass 17, count 0 2006.245.08:12:15.47#ibcon#enter sib2, iclass 17, count 0 2006.245.08:12:15.47#ibcon#flushed, iclass 17, count 0 2006.245.08:12:15.47#ibcon#about to write, iclass 17, count 0 2006.245.08:12:15.47#ibcon#wrote, iclass 17, count 0 2006.245.08:12:15.47#ibcon#about to read 3, iclass 17, count 0 2006.245.08:12:15.49#ibcon#read 3, iclass 17, count 0 2006.245.08:12:15.49#ibcon#about to read 4, iclass 17, count 0 2006.245.08:12:15.49#ibcon#read 4, iclass 17, count 0 2006.245.08:12:15.49#ibcon#about to read 5, iclass 17, count 0 2006.245.08:12:15.49#ibcon#read 5, iclass 17, count 0 2006.245.08:12:15.49#ibcon#about to read 6, iclass 17, count 0 2006.245.08:12:15.49#ibcon#read 6, iclass 17, count 0 2006.245.08:12:15.49#ibcon#end of sib2, iclass 17, count 0 2006.245.08:12:15.49#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:12:15.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:12:15.49#ibcon#[25=USB\r\n] 2006.245.08:12:15.49#ibcon#*before write, iclass 17, count 0 2006.245.08:12:15.49#ibcon#enter sib2, iclass 17, count 0 2006.245.08:12:15.49#ibcon#flushed, iclass 17, count 0 2006.245.08:12:15.49#ibcon#about to write, iclass 17, count 0 2006.245.08:12:15.49#ibcon#wrote, iclass 17, count 0 2006.245.08:12:15.49#ibcon#about to read 3, iclass 17, count 0 2006.245.08:12:15.52#ibcon#read 3, iclass 17, count 0 2006.245.08:12:15.52#ibcon#about to read 4, iclass 17, count 0 2006.245.08:12:15.52#ibcon#read 4, iclass 17, count 0 2006.245.08:12:15.52#ibcon#about to read 5, iclass 17, count 0 2006.245.08:12:15.52#ibcon#read 5, iclass 17, count 0 2006.245.08:12:15.52#ibcon#about to read 6, iclass 17, count 0 2006.245.08:12:15.52#ibcon#read 6, iclass 17, count 0 2006.245.08:12:15.52#ibcon#end of sib2, iclass 17, count 0 2006.245.08:12:15.52#ibcon#*after write, iclass 17, count 0 2006.245.08:12:15.52#ibcon#*before return 0, iclass 17, count 0 2006.245.08:12:15.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:15.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:15.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:12:15.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:12:15.52$vc4f8/valo=4,832.99 2006.245.08:12:15.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.08:12:15.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.08:12:15.52#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:15.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:12:15.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:12:15.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:12:15.52#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:12:15.52#ibcon#first serial, iclass 19, count 0 2006.245.08:12:15.52#ibcon#enter sib2, iclass 19, count 0 2006.245.08:12:15.52#ibcon#flushed, iclass 19, count 0 2006.245.08:12:15.52#ibcon#about to write, iclass 19, count 0 2006.245.08:12:15.52#ibcon#wrote, iclass 19, count 0 2006.245.08:12:15.52#ibcon#about to read 3, iclass 19, count 0 2006.245.08:12:15.54#ibcon#read 3, iclass 19, count 0 2006.245.08:12:15.54#ibcon#about to read 4, iclass 19, count 0 2006.245.08:12:15.54#ibcon#read 4, iclass 19, count 0 2006.245.08:12:15.54#ibcon#about to read 5, iclass 19, count 0 2006.245.08:12:15.54#ibcon#read 5, iclass 19, count 0 2006.245.08:12:15.54#ibcon#about to read 6, iclass 19, count 0 2006.245.08:12:15.54#ibcon#read 6, iclass 19, count 0 2006.245.08:12:15.54#ibcon#end of sib2, iclass 19, count 0 2006.245.08:12:15.54#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:12:15.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:12:15.54#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:12:15.54#ibcon#*before write, iclass 19, count 0 2006.245.08:12:15.54#ibcon#enter sib2, iclass 19, count 0 2006.245.08:12:15.54#ibcon#flushed, iclass 19, count 0 2006.245.08:12:15.54#ibcon#about to write, iclass 19, count 0 2006.245.08:12:15.54#ibcon#wrote, iclass 19, count 0 2006.245.08:12:15.54#ibcon#about to read 3, iclass 19, count 0 2006.245.08:12:15.58#ibcon#read 3, iclass 19, count 0 2006.245.08:12:15.58#ibcon#about to read 4, iclass 19, count 0 2006.245.08:12:15.58#ibcon#read 4, iclass 19, count 0 2006.245.08:12:15.58#ibcon#about to read 5, iclass 19, count 0 2006.245.08:12:15.58#ibcon#read 5, iclass 19, count 0 2006.245.08:12:15.58#ibcon#about to read 6, iclass 19, count 0 2006.245.08:12:15.58#ibcon#read 6, iclass 19, count 0 2006.245.08:12:15.58#ibcon#end of sib2, iclass 19, count 0 2006.245.08:12:15.58#ibcon#*after write, iclass 19, count 0 2006.245.08:12:15.58#ibcon#*before return 0, iclass 19, count 0 2006.245.08:12:15.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:12:15.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:12:15.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:12:15.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:12:15.58$vc4f8/va=4,7 2006.245.08:12:15.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.08:12:15.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.08:12:15.58#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:15.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:12:15.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:12:15.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:12:15.64#ibcon#enter wrdev, iclass 21, count 2 2006.245.08:12:15.64#ibcon#first serial, iclass 21, count 2 2006.245.08:12:15.64#ibcon#enter sib2, iclass 21, count 2 2006.245.08:12:15.64#ibcon#flushed, iclass 21, count 2 2006.245.08:12:15.64#ibcon#about to write, iclass 21, count 2 2006.245.08:12:15.64#ibcon#wrote, iclass 21, count 2 2006.245.08:12:15.64#ibcon#about to read 3, iclass 21, count 2 2006.245.08:12:15.66#ibcon#read 3, iclass 21, count 2 2006.245.08:12:15.66#ibcon#about to read 4, iclass 21, count 2 2006.245.08:12:15.66#ibcon#read 4, iclass 21, count 2 2006.245.08:12:15.66#ibcon#about to read 5, iclass 21, count 2 2006.245.08:12:15.66#ibcon#read 5, iclass 21, count 2 2006.245.08:12:15.66#ibcon#about to read 6, iclass 21, count 2 2006.245.08:12:15.66#ibcon#read 6, iclass 21, count 2 2006.245.08:12:15.66#ibcon#end of sib2, iclass 21, count 2 2006.245.08:12:15.66#ibcon#*mode == 0, iclass 21, count 2 2006.245.08:12:15.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.08:12:15.66#ibcon#[25=AT04-07\r\n] 2006.245.08:12:15.66#ibcon#*before write, iclass 21, count 2 2006.245.08:12:15.66#ibcon#enter sib2, iclass 21, count 2 2006.245.08:12:15.66#ibcon#flushed, iclass 21, count 2 2006.245.08:12:15.66#ibcon#about to write, iclass 21, count 2 2006.245.08:12:15.66#ibcon#wrote, iclass 21, count 2 2006.245.08:12:15.66#ibcon#about to read 3, iclass 21, count 2 2006.245.08:12:15.69#ibcon#read 3, iclass 21, count 2 2006.245.08:12:15.69#ibcon#about to read 4, iclass 21, count 2 2006.245.08:12:15.69#ibcon#read 4, iclass 21, count 2 2006.245.08:12:15.69#ibcon#about to read 5, iclass 21, count 2 2006.245.08:12:15.69#ibcon#read 5, iclass 21, count 2 2006.245.08:12:15.69#ibcon#about to read 6, iclass 21, count 2 2006.245.08:12:15.69#ibcon#read 6, iclass 21, count 2 2006.245.08:12:15.69#ibcon#end of sib2, iclass 21, count 2 2006.245.08:12:15.69#ibcon#*after write, iclass 21, count 2 2006.245.08:12:15.69#ibcon#*before return 0, iclass 21, count 2 2006.245.08:12:15.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:12:15.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:12:15.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.08:12:15.69#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:15.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:12:15.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:12:15.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:12:15.81#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:12:15.81#ibcon#first serial, iclass 21, count 0 2006.245.08:12:15.81#ibcon#enter sib2, iclass 21, count 0 2006.245.08:12:15.81#ibcon#flushed, iclass 21, count 0 2006.245.08:12:15.81#ibcon#about to write, iclass 21, count 0 2006.245.08:12:15.81#ibcon#wrote, iclass 21, count 0 2006.245.08:12:15.81#ibcon#about to read 3, iclass 21, count 0 2006.245.08:12:15.83#ibcon#read 3, iclass 21, count 0 2006.245.08:12:15.83#ibcon#about to read 4, iclass 21, count 0 2006.245.08:12:15.83#ibcon#read 4, iclass 21, count 0 2006.245.08:12:15.83#ibcon#about to read 5, iclass 21, count 0 2006.245.08:12:15.83#ibcon#read 5, iclass 21, count 0 2006.245.08:12:15.83#ibcon#about to read 6, iclass 21, count 0 2006.245.08:12:15.83#ibcon#read 6, iclass 21, count 0 2006.245.08:12:15.83#ibcon#end of sib2, iclass 21, count 0 2006.245.08:12:15.83#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:12:15.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:12:15.83#ibcon#[25=USB\r\n] 2006.245.08:12:15.83#ibcon#*before write, iclass 21, count 0 2006.245.08:12:15.83#ibcon#enter sib2, iclass 21, count 0 2006.245.08:12:15.83#ibcon#flushed, iclass 21, count 0 2006.245.08:12:15.83#ibcon#about to write, iclass 21, count 0 2006.245.08:12:15.83#ibcon#wrote, iclass 21, count 0 2006.245.08:12:15.83#ibcon#about to read 3, iclass 21, count 0 2006.245.08:12:15.86#ibcon#read 3, iclass 21, count 0 2006.245.08:12:15.86#ibcon#about to read 4, iclass 21, count 0 2006.245.08:12:15.86#ibcon#read 4, iclass 21, count 0 2006.245.08:12:15.86#ibcon#about to read 5, iclass 21, count 0 2006.245.08:12:15.86#ibcon#read 5, iclass 21, count 0 2006.245.08:12:15.86#ibcon#about to read 6, iclass 21, count 0 2006.245.08:12:15.86#ibcon#read 6, iclass 21, count 0 2006.245.08:12:15.86#ibcon#end of sib2, iclass 21, count 0 2006.245.08:12:15.86#ibcon#*after write, iclass 21, count 0 2006.245.08:12:15.86#ibcon#*before return 0, iclass 21, count 0 2006.245.08:12:15.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:12:15.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:12:15.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:12:15.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:12:15.86$vc4f8/valo=5,652.99 2006.245.08:12:15.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.08:12:15.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.08:12:15.86#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:15.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:12:15.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:12:15.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:12:15.86#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:12:15.86#ibcon#first serial, iclass 23, count 0 2006.245.08:12:15.86#ibcon#enter sib2, iclass 23, count 0 2006.245.08:12:15.86#ibcon#flushed, iclass 23, count 0 2006.245.08:12:15.86#ibcon#about to write, iclass 23, count 0 2006.245.08:12:15.86#ibcon#wrote, iclass 23, count 0 2006.245.08:12:15.86#ibcon#about to read 3, iclass 23, count 0 2006.245.08:12:15.88#ibcon#read 3, iclass 23, count 0 2006.245.08:12:15.88#ibcon#about to read 4, iclass 23, count 0 2006.245.08:12:15.88#ibcon#read 4, iclass 23, count 0 2006.245.08:12:15.88#ibcon#about to read 5, iclass 23, count 0 2006.245.08:12:15.88#ibcon#read 5, iclass 23, count 0 2006.245.08:12:15.88#ibcon#about to read 6, iclass 23, count 0 2006.245.08:12:15.88#ibcon#read 6, iclass 23, count 0 2006.245.08:12:15.88#ibcon#end of sib2, iclass 23, count 0 2006.245.08:12:15.88#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:12:15.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:12:15.88#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:12:15.88#ibcon#*before write, iclass 23, count 0 2006.245.08:12:15.88#ibcon#enter sib2, iclass 23, count 0 2006.245.08:12:15.88#ibcon#flushed, iclass 23, count 0 2006.245.08:12:15.88#ibcon#about to write, iclass 23, count 0 2006.245.08:12:15.88#ibcon#wrote, iclass 23, count 0 2006.245.08:12:15.88#ibcon#about to read 3, iclass 23, count 0 2006.245.08:12:15.92#ibcon#read 3, iclass 23, count 0 2006.245.08:12:15.92#ibcon#about to read 4, iclass 23, count 0 2006.245.08:12:15.92#ibcon#read 4, iclass 23, count 0 2006.245.08:12:15.92#ibcon#about to read 5, iclass 23, count 0 2006.245.08:12:15.92#ibcon#read 5, iclass 23, count 0 2006.245.08:12:15.92#ibcon#about to read 6, iclass 23, count 0 2006.245.08:12:15.92#ibcon#read 6, iclass 23, count 0 2006.245.08:12:15.92#ibcon#end of sib2, iclass 23, count 0 2006.245.08:12:15.92#ibcon#*after write, iclass 23, count 0 2006.245.08:12:15.92#ibcon#*before return 0, iclass 23, count 0 2006.245.08:12:15.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:12:15.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:12:15.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:12:15.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:12:15.92$vc4f8/va=5,7 2006.245.08:12:15.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.08:12:15.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.08:12:15.92#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:15.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:15.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:15.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:15.98#ibcon#enter wrdev, iclass 25, count 2 2006.245.08:12:15.98#ibcon#first serial, iclass 25, count 2 2006.245.08:12:15.98#ibcon#enter sib2, iclass 25, count 2 2006.245.08:12:15.98#ibcon#flushed, iclass 25, count 2 2006.245.08:12:15.98#ibcon#about to write, iclass 25, count 2 2006.245.08:12:15.98#ibcon#wrote, iclass 25, count 2 2006.245.08:12:15.98#ibcon#about to read 3, iclass 25, count 2 2006.245.08:12:16.00#ibcon#read 3, iclass 25, count 2 2006.245.08:12:16.00#ibcon#about to read 4, iclass 25, count 2 2006.245.08:12:16.00#ibcon#read 4, iclass 25, count 2 2006.245.08:12:16.00#ibcon#about to read 5, iclass 25, count 2 2006.245.08:12:16.00#ibcon#read 5, iclass 25, count 2 2006.245.08:12:16.00#ibcon#about to read 6, iclass 25, count 2 2006.245.08:12:16.00#ibcon#read 6, iclass 25, count 2 2006.245.08:12:16.00#ibcon#end of sib2, iclass 25, count 2 2006.245.08:12:16.00#ibcon#*mode == 0, iclass 25, count 2 2006.245.08:12:16.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.08:12:16.00#ibcon#[25=AT05-07\r\n] 2006.245.08:12:16.00#ibcon#*before write, iclass 25, count 2 2006.245.08:12:16.00#ibcon#enter sib2, iclass 25, count 2 2006.245.08:12:16.00#ibcon#flushed, iclass 25, count 2 2006.245.08:12:16.00#ibcon#about to write, iclass 25, count 2 2006.245.08:12:16.00#ibcon#wrote, iclass 25, count 2 2006.245.08:12:16.00#ibcon#about to read 3, iclass 25, count 2 2006.245.08:12:16.03#ibcon#read 3, iclass 25, count 2 2006.245.08:12:16.03#ibcon#about to read 4, iclass 25, count 2 2006.245.08:12:16.03#ibcon#read 4, iclass 25, count 2 2006.245.08:12:16.03#ibcon#about to read 5, iclass 25, count 2 2006.245.08:12:16.03#ibcon#read 5, iclass 25, count 2 2006.245.08:12:16.03#ibcon#about to read 6, iclass 25, count 2 2006.245.08:12:16.03#ibcon#read 6, iclass 25, count 2 2006.245.08:12:16.03#ibcon#end of sib2, iclass 25, count 2 2006.245.08:12:16.03#ibcon#*after write, iclass 25, count 2 2006.245.08:12:16.03#ibcon#*before return 0, iclass 25, count 2 2006.245.08:12:16.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:16.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:16.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.08:12:16.03#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:16.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:16.13#trakl#Source acquired 2006.245.08:12:16.13#flagr#flagr/antenna,acquired 2006.245.08:12:16.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:16.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:16.15#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:12:16.15#ibcon#first serial, iclass 25, count 0 2006.245.08:12:16.15#ibcon#enter sib2, iclass 25, count 0 2006.245.08:12:16.15#ibcon#flushed, iclass 25, count 0 2006.245.08:12:16.15#ibcon#about to write, iclass 25, count 0 2006.245.08:12:16.15#ibcon#wrote, iclass 25, count 0 2006.245.08:12:16.15#ibcon#about to read 3, iclass 25, count 0 2006.245.08:12:16.17#ibcon#read 3, iclass 25, count 0 2006.245.08:12:16.17#ibcon#about to read 4, iclass 25, count 0 2006.245.08:12:16.17#ibcon#read 4, iclass 25, count 0 2006.245.08:12:16.17#ibcon#about to read 5, iclass 25, count 0 2006.245.08:12:16.17#ibcon#read 5, iclass 25, count 0 2006.245.08:12:16.17#ibcon#about to read 6, iclass 25, count 0 2006.245.08:12:16.17#ibcon#read 6, iclass 25, count 0 2006.245.08:12:16.17#ibcon#end of sib2, iclass 25, count 0 2006.245.08:12:16.17#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:12:16.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:12:16.17#ibcon#[25=USB\r\n] 2006.245.08:12:16.17#ibcon#*before write, iclass 25, count 0 2006.245.08:12:16.17#ibcon#enter sib2, iclass 25, count 0 2006.245.08:12:16.17#ibcon#flushed, iclass 25, count 0 2006.245.08:12:16.17#ibcon#about to write, iclass 25, count 0 2006.245.08:12:16.17#ibcon#wrote, iclass 25, count 0 2006.245.08:12:16.17#ibcon#about to read 3, iclass 25, count 0 2006.245.08:12:16.20#ibcon#read 3, iclass 25, count 0 2006.245.08:12:16.20#ibcon#about to read 4, iclass 25, count 0 2006.245.08:12:16.20#ibcon#read 4, iclass 25, count 0 2006.245.08:12:16.20#ibcon#about to read 5, iclass 25, count 0 2006.245.08:12:16.20#ibcon#read 5, iclass 25, count 0 2006.245.08:12:16.20#ibcon#about to read 6, iclass 25, count 0 2006.245.08:12:16.20#ibcon#read 6, iclass 25, count 0 2006.245.08:12:16.20#ibcon#end of sib2, iclass 25, count 0 2006.245.08:12:16.20#ibcon#*after write, iclass 25, count 0 2006.245.08:12:16.20#ibcon#*before return 0, iclass 25, count 0 2006.245.08:12:16.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:16.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:16.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:12:16.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:12:16.20$vc4f8/valo=6,772.99 2006.245.08:12:16.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.08:12:16.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.08:12:16.20#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:16.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:16.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:16.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:16.20#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:12:16.20#ibcon#first serial, iclass 27, count 0 2006.245.08:12:16.20#ibcon#enter sib2, iclass 27, count 0 2006.245.08:12:16.20#ibcon#flushed, iclass 27, count 0 2006.245.08:12:16.20#ibcon#about to write, iclass 27, count 0 2006.245.08:12:16.20#ibcon#wrote, iclass 27, count 0 2006.245.08:12:16.20#ibcon#about to read 3, iclass 27, count 0 2006.245.08:12:16.22#ibcon#read 3, iclass 27, count 0 2006.245.08:12:16.22#ibcon#about to read 4, iclass 27, count 0 2006.245.08:12:16.22#ibcon#read 4, iclass 27, count 0 2006.245.08:12:16.22#ibcon#about to read 5, iclass 27, count 0 2006.245.08:12:16.22#ibcon#read 5, iclass 27, count 0 2006.245.08:12:16.22#ibcon#about to read 6, iclass 27, count 0 2006.245.08:12:16.22#ibcon#read 6, iclass 27, count 0 2006.245.08:12:16.22#ibcon#end of sib2, iclass 27, count 0 2006.245.08:12:16.22#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:12:16.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:12:16.22#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:12:16.22#ibcon#*before write, iclass 27, count 0 2006.245.08:12:16.22#ibcon#enter sib2, iclass 27, count 0 2006.245.08:12:16.22#ibcon#flushed, iclass 27, count 0 2006.245.08:12:16.22#ibcon#about to write, iclass 27, count 0 2006.245.08:12:16.22#ibcon#wrote, iclass 27, count 0 2006.245.08:12:16.22#ibcon#about to read 3, iclass 27, count 0 2006.245.08:12:16.26#ibcon#read 3, iclass 27, count 0 2006.245.08:12:16.26#ibcon#about to read 4, iclass 27, count 0 2006.245.08:12:16.26#ibcon#read 4, iclass 27, count 0 2006.245.08:12:16.26#ibcon#about to read 5, iclass 27, count 0 2006.245.08:12:16.26#ibcon#read 5, iclass 27, count 0 2006.245.08:12:16.26#ibcon#about to read 6, iclass 27, count 0 2006.245.08:12:16.26#ibcon#read 6, iclass 27, count 0 2006.245.08:12:16.26#ibcon#end of sib2, iclass 27, count 0 2006.245.08:12:16.26#ibcon#*after write, iclass 27, count 0 2006.245.08:12:16.26#ibcon#*before return 0, iclass 27, count 0 2006.245.08:12:16.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:16.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:16.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:12:16.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:12:16.26$vc4f8/va=6,7 2006.245.08:12:16.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.08:12:16.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.08:12:16.26#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:16.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:16.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:16.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:16.32#ibcon#enter wrdev, iclass 29, count 2 2006.245.08:12:16.32#ibcon#first serial, iclass 29, count 2 2006.245.08:12:16.32#ibcon#enter sib2, iclass 29, count 2 2006.245.08:12:16.32#ibcon#flushed, iclass 29, count 2 2006.245.08:12:16.32#ibcon#about to write, iclass 29, count 2 2006.245.08:12:16.32#ibcon#wrote, iclass 29, count 2 2006.245.08:12:16.32#ibcon#about to read 3, iclass 29, count 2 2006.245.08:12:16.34#ibcon#read 3, iclass 29, count 2 2006.245.08:12:16.34#ibcon#about to read 4, iclass 29, count 2 2006.245.08:12:16.34#ibcon#read 4, iclass 29, count 2 2006.245.08:12:16.34#ibcon#about to read 5, iclass 29, count 2 2006.245.08:12:16.34#ibcon#read 5, iclass 29, count 2 2006.245.08:12:16.34#ibcon#about to read 6, iclass 29, count 2 2006.245.08:12:16.34#ibcon#read 6, iclass 29, count 2 2006.245.08:12:16.34#ibcon#end of sib2, iclass 29, count 2 2006.245.08:12:16.34#ibcon#*mode == 0, iclass 29, count 2 2006.245.08:12:16.34#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.08:12:16.34#ibcon#[25=AT06-07\r\n] 2006.245.08:12:16.34#ibcon#*before write, iclass 29, count 2 2006.245.08:12:16.34#ibcon#enter sib2, iclass 29, count 2 2006.245.08:12:16.34#ibcon#flushed, iclass 29, count 2 2006.245.08:12:16.34#ibcon#about to write, iclass 29, count 2 2006.245.08:12:16.34#ibcon#wrote, iclass 29, count 2 2006.245.08:12:16.34#ibcon#about to read 3, iclass 29, count 2 2006.245.08:12:16.37#ibcon#read 3, iclass 29, count 2 2006.245.08:12:16.37#ibcon#about to read 4, iclass 29, count 2 2006.245.08:12:16.37#ibcon#read 4, iclass 29, count 2 2006.245.08:12:16.37#ibcon#about to read 5, iclass 29, count 2 2006.245.08:12:16.37#ibcon#read 5, iclass 29, count 2 2006.245.08:12:16.37#ibcon#about to read 6, iclass 29, count 2 2006.245.08:12:16.37#ibcon#read 6, iclass 29, count 2 2006.245.08:12:16.37#ibcon#end of sib2, iclass 29, count 2 2006.245.08:12:16.37#ibcon#*after write, iclass 29, count 2 2006.245.08:12:16.37#ibcon#*before return 0, iclass 29, count 2 2006.245.08:12:16.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:16.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:16.37#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.08:12:16.37#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:16.37#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:16.49#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:16.49#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:16.49#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:12:16.49#ibcon#first serial, iclass 29, count 0 2006.245.08:12:16.49#ibcon#enter sib2, iclass 29, count 0 2006.245.08:12:16.49#ibcon#flushed, iclass 29, count 0 2006.245.08:12:16.49#ibcon#about to write, iclass 29, count 0 2006.245.08:12:16.49#ibcon#wrote, iclass 29, count 0 2006.245.08:12:16.49#ibcon#about to read 3, iclass 29, count 0 2006.245.08:12:16.51#ibcon#read 3, iclass 29, count 0 2006.245.08:12:16.51#ibcon#about to read 4, iclass 29, count 0 2006.245.08:12:16.51#ibcon#read 4, iclass 29, count 0 2006.245.08:12:16.51#ibcon#about to read 5, iclass 29, count 0 2006.245.08:12:16.51#ibcon#read 5, iclass 29, count 0 2006.245.08:12:16.51#ibcon#about to read 6, iclass 29, count 0 2006.245.08:12:16.51#ibcon#read 6, iclass 29, count 0 2006.245.08:12:16.51#ibcon#end of sib2, iclass 29, count 0 2006.245.08:12:16.51#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:12:16.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:12:16.51#ibcon#[25=USB\r\n] 2006.245.08:12:16.51#ibcon#*before write, iclass 29, count 0 2006.245.08:12:16.51#ibcon#enter sib2, iclass 29, count 0 2006.245.08:12:16.51#ibcon#flushed, iclass 29, count 0 2006.245.08:12:16.51#ibcon#about to write, iclass 29, count 0 2006.245.08:12:16.51#ibcon#wrote, iclass 29, count 0 2006.245.08:12:16.51#ibcon#about to read 3, iclass 29, count 0 2006.245.08:12:16.54#ibcon#read 3, iclass 29, count 0 2006.245.08:12:16.54#ibcon#about to read 4, iclass 29, count 0 2006.245.08:12:16.54#ibcon#read 4, iclass 29, count 0 2006.245.08:12:16.54#ibcon#about to read 5, iclass 29, count 0 2006.245.08:12:16.54#ibcon#read 5, iclass 29, count 0 2006.245.08:12:16.54#ibcon#about to read 6, iclass 29, count 0 2006.245.08:12:16.54#ibcon#read 6, iclass 29, count 0 2006.245.08:12:16.54#ibcon#end of sib2, iclass 29, count 0 2006.245.08:12:16.54#ibcon#*after write, iclass 29, count 0 2006.245.08:12:16.54#ibcon#*before return 0, iclass 29, count 0 2006.245.08:12:16.54#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:16.54#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:16.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:12:16.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:12:16.54$vc4f8/valo=7,832.99 2006.245.08:12:16.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.08:12:16.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.08:12:16.54#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:16.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:16.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:16.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:16.54#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:12:16.54#ibcon#first serial, iclass 31, count 0 2006.245.08:12:16.54#ibcon#enter sib2, iclass 31, count 0 2006.245.08:12:16.54#ibcon#flushed, iclass 31, count 0 2006.245.08:12:16.54#ibcon#about to write, iclass 31, count 0 2006.245.08:12:16.54#ibcon#wrote, iclass 31, count 0 2006.245.08:12:16.54#ibcon#about to read 3, iclass 31, count 0 2006.245.08:12:16.56#ibcon#read 3, iclass 31, count 0 2006.245.08:12:16.56#ibcon#about to read 4, iclass 31, count 0 2006.245.08:12:16.56#ibcon#read 4, iclass 31, count 0 2006.245.08:12:16.56#ibcon#about to read 5, iclass 31, count 0 2006.245.08:12:16.56#ibcon#read 5, iclass 31, count 0 2006.245.08:12:16.56#ibcon#about to read 6, iclass 31, count 0 2006.245.08:12:16.56#ibcon#read 6, iclass 31, count 0 2006.245.08:12:16.56#ibcon#end of sib2, iclass 31, count 0 2006.245.08:12:16.56#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:12:16.56#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:12:16.56#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:12:16.56#ibcon#*before write, iclass 31, count 0 2006.245.08:12:16.56#ibcon#enter sib2, iclass 31, count 0 2006.245.08:12:16.56#ibcon#flushed, iclass 31, count 0 2006.245.08:12:16.56#ibcon#about to write, iclass 31, count 0 2006.245.08:12:16.56#ibcon#wrote, iclass 31, count 0 2006.245.08:12:16.56#ibcon#about to read 3, iclass 31, count 0 2006.245.08:12:16.60#ibcon#read 3, iclass 31, count 0 2006.245.08:12:16.60#ibcon#about to read 4, iclass 31, count 0 2006.245.08:12:16.60#ibcon#read 4, iclass 31, count 0 2006.245.08:12:16.60#ibcon#about to read 5, iclass 31, count 0 2006.245.08:12:16.60#ibcon#read 5, iclass 31, count 0 2006.245.08:12:16.60#ibcon#about to read 6, iclass 31, count 0 2006.245.08:12:16.60#ibcon#read 6, iclass 31, count 0 2006.245.08:12:16.60#ibcon#end of sib2, iclass 31, count 0 2006.245.08:12:16.60#ibcon#*after write, iclass 31, count 0 2006.245.08:12:16.60#ibcon#*before return 0, iclass 31, count 0 2006.245.08:12:16.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:16.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:16.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:12:16.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:12:16.60$vc4f8/va=7,7 2006.245.08:12:16.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.08:12:16.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.08:12:16.60#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:16.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:12:16.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:12:16.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:12:16.66#ibcon#enter wrdev, iclass 33, count 2 2006.245.08:12:16.66#ibcon#first serial, iclass 33, count 2 2006.245.08:12:16.66#ibcon#enter sib2, iclass 33, count 2 2006.245.08:12:16.66#ibcon#flushed, iclass 33, count 2 2006.245.08:12:16.66#ibcon#about to write, iclass 33, count 2 2006.245.08:12:16.66#ibcon#wrote, iclass 33, count 2 2006.245.08:12:16.66#ibcon#about to read 3, iclass 33, count 2 2006.245.08:12:16.68#ibcon#read 3, iclass 33, count 2 2006.245.08:12:16.68#ibcon#about to read 4, iclass 33, count 2 2006.245.08:12:16.68#ibcon#read 4, iclass 33, count 2 2006.245.08:12:16.68#ibcon#about to read 5, iclass 33, count 2 2006.245.08:12:16.68#ibcon#read 5, iclass 33, count 2 2006.245.08:12:16.68#ibcon#about to read 6, iclass 33, count 2 2006.245.08:12:16.68#ibcon#read 6, iclass 33, count 2 2006.245.08:12:16.68#ibcon#end of sib2, iclass 33, count 2 2006.245.08:12:16.68#ibcon#*mode == 0, iclass 33, count 2 2006.245.08:12:16.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.08:12:16.68#ibcon#[25=AT07-07\r\n] 2006.245.08:12:16.68#ibcon#*before write, iclass 33, count 2 2006.245.08:12:16.68#ibcon#enter sib2, iclass 33, count 2 2006.245.08:12:16.68#ibcon#flushed, iclass 33, count 2 2006.245.08:12:16.68#ibcon#about to write, iclass 33, count 2 2006.245.08:12:16.68#ibcon#wrote, iclass 33, count 2 2006.245.08:12:16.68#ibcon#about to read 3, iclass 33, count 2 2006.245.08:12:16.71#ibcon#read 3, iclass 33, count 2 2006.245.08:12:16.71#ibcon#about to read 4, iclass 33, count 2 2006.245.08:12:16.71#ibcon#read 4, iclass 33, count 2 2006.245.08:12:16.71#ibcon#about to read 5, iclass 33, count 2 2006.245.08:12:16.71#ibcon#read 5, iclass 33, count 2 2006.245.08:12:16.71#ibcon#about to read 6, iclass 33, count 2 2006.245.08:12:16.71#ibcon#read 6, iclass 33, count 2 2006.245.08:12:16.71#ibcon#end of sib2, iclass 33, count 2 2006.245.08:12:16.71#ibcon#*after write, iclass 33, count 2 2006.245.08:12:16.71#ibcon#*before return 0, iclass 33, count 2 2006.245.08:12:16.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:12:16.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:12:16.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.08:12:16.71#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:16.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:12:16.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:12:16.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:12:16.83#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:12:16.83#ibcon#first serial, iclass 33, count 0 2006.245.08:12:16.83#ibcon#enter sib2, iclass 33, count 0 2006.245.08:12:16.83#ibcon#flushed, iclass 33, count 0 2006.245.08:12:16.83#ibcon#about to write, iclass 33, count 0 2006.245.08:12:16.83#ibcon#wrote, iclass 33, count 0 2006.245.08:12:16.83#ibcon#about to read 3, iclass 33, count 0 2006.245.08:12:16.85#ibcon#read 3, iclass 33, count 0 2006.245.08:12:16.85#ibcon#about to read 4, iclass 33, count 0 2006.245.08:12:16.85#ibcon#read 4, iclass 33, count 0 2006.245.08:12:16.85#ibcon#about to read 5, iclass 33, count 0 2006.245.08:12:16.85#ibcon#read 5, iclass 33, count 0 2006.245.08:12:16.85#ibcon#about to read 6, iclass 33, count 0 2006.245.08:12:16.85#ibcon#read 6, iclass 33, count 0 2006.245.08:12:16.85#ibcon#end of sib2, iclass 33, count 0 2006.245.08:12:16.85#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:12:16.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:12:16.85#ibcon#[25=USB\r\n] 2006.245.08:12:16.85#ibcon#*before write, iclass 33, count 0 2006.245.08:12:16.85#ibcon#enter sib2, iclass 33, count 0 2006.245.08:12:16.85#ibcon#flushed, iclass 33, count 0 2006.245.08:12:16.85#ibcon#about to write, iclass 33, count 0 2006.245.08:12:16.85#ibcon#wrote, iclass 33, count 0 2006.245.08:12:16.85#ibcon#about to read 3, iclass 33, count 0 2006.245.08:12:16.88#ibcon#read 3, iclass 33, count 0 2006.245.08:12:16.88#ibcon#about to read 4, iclass 33, count 0 2006.245.08:12:16.88#ibcon#read 4, iclass 33, count 0 2006.245.08:12:16.88#ibcon#about to read 5, iclass 33, count 0 2006.245.08:12:16.88#ibcon#read 5, iclass 33, count 0 2006.245.08:12:16.88#ibcon#about to read 6, iclass 33, count 0 2006.245.08:12:16.88#ibcon#read 6, iclass 33, count 0 2006.245.08:12:16.88#ibcon#end of sib2, iclass 33, count 0 2006.245.08:12:16.88#ibcon#*after write, iclass 33, count 0 2006.245.08:12:16.88#ibcon#*before return 0, iclass 33, count 0 2006.245.08:12:16.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:12:16.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:12:16.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:12:16.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:12:16.88$vc4f8/valo=8,852.99 2006.245.08:12:16.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.08:12:16.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.08:12:16.88#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:16.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:12:16.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:12:16.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:12:16.88#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:12:16.88#ibcon#first serial, iclass 35, count 0 2006.245.08:12:16.88#ibcon#enter sib2, iclass 35, count 0 2006.245.08:12:16.88#ibcon#flushed, iclass 35, count 0 2006.245.08:12:16.88#ibcon#about to write, iclass 35, count 0 2006.245.08:12:16.88#ibcon#wrote, iclass 35, count 0 2006.245.08:12:16.88#ibcon#about to read 3, iclass 35, count 0 2006.245.08:12:16.90#ibcon#read 3, iclass 35, count 0 2006.245.08:12:16.90#ibcon#about to read 4, iclass 35, count 0 2006.245.08:12:16.90#ibcon#read 4, iclass 35, count 0 2006.245.08:12:16.90#ibcon#about to read 5, iclass 35, count 0 2006.245.08:12:16.90#ibcon#read 5, iclass 35, count 0 2006.245.08:12:16.90#ibcon#about to read 6, iclass 35, count 0 2006.245.08:12:16.90#ibcon#read 6, iclass 35, count 0 2006.245.08:12:16.90#ibcon#end of sib2, iclass 35, count 0 2006.245.08:12:16.90#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:12:16.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:12:16.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:12:16.90#ibcon#*before write, iclass 35, count 0 2006.245.08:12:16.90#ibcon#enter sib2, iclass 35, count 0 2006.245.08:12:16.90#ibcon#flushed, iclass 35, count 0 2006.245.08:12:16.90#ibcon#about to write, iclass 35, count 0 2006.245.08:12:16.90#ibcon#wrote, iclass 35, count 0 2006.245.08:12:16.90#ibcon#about to read 3, iclass 35, count 0 2006.245.08:12:16.94#ibcon#read 3, iclass 35, count 0 2006.245.08:12:16.94#ibcon#about to read 4, iclass 35, count 0 2006.245.08:12:16.94#ibcon#read 4, iclass 35, count 0 2006.245.08:12:16.94#ibcon#about to read 5, iclass 35, count 0 2006.245.08:12:16.94#ibcon#read 5, iclass 35, count 0 2006.245.08:12:16.94#ibcon#about to read 6, iclass 35, count 0 2006.245.08:12:16.94#ibcon#read 6, iclass 35, count 0 2006.245.08:12:16.94#ibcon#end of sib2, iclass 35, count 0 2006.245.08:12:16.94#ibcon#*after write, iclass 35, count 0 2006.245.08:12:16.94#ibcon#*before return 0, iclass 35, count 0 2006.245.08:12:16.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:12:16.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:12:16.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:12:16.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:12:16.94$vc4f8/va=8,8 2006.245.08:12:16.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.08:12:16.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.08:12:16.94#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:16.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:12:17.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:12:17.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:12:17.00#ibcon#enter wrdev, iclass 37, count 2 2006.245.08:12:17.00#ibcon#first serial, iclass 37, count 2 2006.245.08:12:17.00#ibcon#enter sib2, iclass 37, count 2 2006.245.08:12:17.00#ibcon#flushed, iclass 37, count 2 2006.245.08:12:17.00#ibcon#about to write, iclass 37, count 2 2006.245.08:12:17.00#ibcon#wrote, iclass 37, count 2 2006.245.08:12:17.00#ibcon#about to read 3, iclass 37, count 2 2006.245.08:12:17.02#ibcon#read 3, iclass 37, count 2 2006.245.08:12:17.02#ibcon#about to read 4, iclass 37, count 2 2006.245.08:12:17.02#ibcon#read 4, iclass 37, count 2 2006.245.08:12:17.02#ibcon#about to read 5, iclass 37, count 2 2006.245.08:12:17.02#ibcon#read 5, iclass 37, count 2 2006.245.08:12:17.02#ibcon#about to read 6, iclass 37, count 2 2006.245.08:12:17.02#ibcon#read 6, iclass 37, count 2 2006.245.08:12:17.02#ibcon#end of sib2, iclass 37, count 2 2006.245.08:12:17.02#ibcon#*mode == 0, iclass 37, count 2 2006.245.08:12:17.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.08:12:17.02#ibcon#[25=AT08-08\r\n] 2006.245.08:12:17.02#ibcon#*before write, iclass 37, count 2 2006.245.08:12:17.02#ibcon#enter sib2, iclass 37, count 2 2006.245.08:12:17.02#ibcon#flushed, iclass 37, count 2 2006.245.08:12:17.02#ibcon#about to write, iclass 37, count 2 2006.245.08:12:17.02#ibcon#wrote, iclass 37, count 2 2006.245.08:12:17.02#ibcon#about to read 3, iclass 37, count 2 2006.245.08:12:17.05#ibcon#read 3, iclass 37, count 2 2006.245.08:12:17.05#ibcon#about to read 4, iclass 37, count 2 2006.245.08:12:17.05#ibcon#read 4, iclass 37, count 2 2006.245.08:12:17.05#ibcon#about to read 5, iclass 37, count 2 2006.245.08:12:17.05#ibcon#read 5, iclass 37, count 2 2006.245.08:12:17.05#ibcon#about to read 6, iclass 37, count 2 2006.245.08:12:17.05#ibcon#read 6, iclass 37, count 2 2006.245.08:12:17.05#ibcon#end of sib2, iclass 37, count 2 2006.245.08:12:17.05#ibcon#*after write, iclass 37, count 2 2006.245.08:12:17.05#ibcon#*before return 0, iclass 37, count 2 2006.245.08:12:17.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:12:17.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:12:17.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.08:12:17.05#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:17.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:12:17.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:12:17.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:12:17.17#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:12:17.17#ibcon#first serial, iclass 37, count 0 2006.245.08:12:17.17#ibcon#enter sib2, iclass 37, count 0 2006.245.08:12:17.17#ibcon#flushed, iclass 37, count 0 2006.245.08:12:17.17#ibcon#about to write, iclass 37, count 0 2006.245.08:12:17.17#ibcon#wrote, iclass 37, count 0 2006.245.08:12:17.17#ibcon#about to read 3, iclass 37, count 0 2006.245.08:12:17.19#ibcon#read 3, iclass 37, count 0 2006.245.08:12:17.19#ibcon#about to read 4, iclass 37, count 0 2006.245.08:12:17.19#ibcon#read 4, iclass 37, count 0 2006.245.08:12:17.19#ibcon#about to read 5, iclass 37, count 0 2006.245.08:12:17.19#ibcon#read 5, iclass 37, count 0 2006.245.08:12:17.19#ibcon#about to read 6, iclass 37, count 0 2006.245.08:12:17.19#ibcon#read 6, iclass 37, count 0 2006.245.08:12:17.19#ibcon#end of sib2, iclass 37, count 0 2006.245.08:12:17.19#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:12:17.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:12:17.19#ibcon#[25=USB\r\n] 2006.245.08:12:17.19#ibcon#*before write, iclass 37, count 0 2006.245.08:12:17.19#ibcon#enter sib2, iclass 37, count 0 2006.245.08:12:17.19#ibcon#flushed, iclass 37, count 0 2006.245.08:12:17.19#ibcon#about to write, iclass 37, count 0 2006.245.08:12:17.19#ibcon#wrote, iclass 37, count 0 2006.245.08:12:17.19#ibcon#about to read 3, iclass 37, count 0 2006.245.08:12:17.22#ibcon#read 3, iclass 37, count 0 2006.245.08:12:17.22#ibcon#about to read 4, iclass 37, count 0 2006.245.08:12:17.22#ibcon#read 4, iclass 37, count 0 2006.245.08:12:17.22#ibcon#about to read 5, iclass 37, count 0 2006.245.08:12:17.22#ibcon#read 5, iclass 37, count 0 2006.245.08:12:17.22#ibcon#about to read 6, iclass 37, count 0 2006.245.08:12:17.22#ibcon#read 6, iclass 37, count 0 2006.245.08:12:17.22#ibcon#end of sib2, iclass 37, count 0 2006.245.08:12:17.22#ibcon#*after write, iclass 37, count 0 2006.245.08:12:17.22#ibcon#*before return 0, iclass 37, count 0 2006.245.08:12:17.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:12:17.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:12:17.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:12:17.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:12:17.22$vc4f8/vblo=1,632.99 2006.245.08:12:17.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.08:12:17.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.08:12:17.22#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:17.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:12:17.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:12:17.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:12:17.22#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:12:17.22#ibcon#first serial, iclass 39, count 0 2006.245.08:12:17.22#ibcon#enter sib2, iclass 39, count 0 2006.245.08:12:17.22#ibcon#flushed, iclass 39, count 0 2006.245.08:12:17.22#ibcon#about to write, iclass 39, count 0 2006.245.08:12:17.22#ibcon#wrote, iclass 39, count 0 2006.245.08:12:17.22#ibcon#about to read 3, iclass 39, count 0 2006.245.08:12:17.24#ibcon#read 3, iclass 39, count 0 2006.245.08:12:17.24#ibcon#about to read 4, iclass 39, count 0 2006.245.08:12:17.24#ibcon#read 4, iclass 39, count 0 2006.245.08:12:17.24#ibcon#about to read 5, iclass 39, count 0 2006.245.08:12:17.24#ibcon#read 5, iclass 39, count 0 2006.245.08:12:17.24#ibcon#about to read 6, iclass 39, count 0 2006.245.08:12:17.24#ibcon#read 6, iclass 39, count 0 2006.245.08:12:17.24#ibcon#end of sib2, iclass 39, count 0 2006.245.08:12:17.24#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:12:17.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:12:17.24#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:12:17.24#ibcon#*before write, iclass 39, count 0 2006.245.08:12:17.24#ibcon#enter sib2, iclass 39, count 0 2006.245.08:12:17.24#ibcon#flushed, iclass 39, count 0 2006.245.08:12:17.24#ibcon#about to write, iclass 39, count 0 2006.245.08:12:17.24#ibcon#wrote, iclass 39, count 0 2006.245.08:12:17.24#ibcon#about to read 3, iclass 39, count 0 2006.245.08:12:17.28#ibcon#read 3, iclass 39, count 0 2006.245.08:12:17.28#ibcon#about to read 4, iclass 39, count 0 2006.245.08:12:17.28#ibcon#read 4, iclass 39, count 0 2006.245.08:12:17.28#ibcon#about to read 5, iclass 39, count 0 2006.245.08:12:17.28#ibcon#read 5, iclass 39, count 0 2006.245.08:12:17.28#ibcon#about to read 6, iclass 39, count 0 2006.245.08:12:17.28#ibcon#read 6, iclass 39, count 0 2006.245.08:12:17.28#ibcon#end of sib2, iclass 39, count 0 2006.245.08:12:17.28#ibcon#*after write, iclass 39, count 0 2006.245.08:12:17.28#ibcon#*before return 0, iclass 39, count 0 2006.245.08:12:17.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:12:17.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:12:17.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:12:17.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:12:17.28$vc4f8/vb=1,4 2006.245.08:12:17.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.08:12:17.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.08:12:17.28#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:17.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:12:17.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:12:17.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:12:17.28#ibcon#enter wrdev, iclass 3, count 2 2006.245.08:12:17.28#ibcon#first serial, iclass 3, count 2 2006.245.08:12:17.28#ibcon#enter sib2, iclass 3, count 2 2006.245.08:12:17.28#ibcon#flushed, iclass 3, count 2 2006.245.08:12:17.28#ibcon#about to write, iclass 3, count 2 2006.245.08:12:17.28#ibcon#wrote, iclass 3, count 2 2006.245.08:12:17.28#ibcon#about to read 3, iclass 3, count 2 2006.245.08:12:17.30#ibcon#read 3, iclass 3, count 2 2006.245.08:12:17.30#ibcon#about to read 4, iclass 3, count 2 2006.245.08:12:17.30#ibcon#read 4, iclass 3, count 2 2006.245.08:12:17.30#ibcon#about to read 5, iclass 3, count 2 2006.245.08:12:17.30#ibcon#read 5, iclass 3, count 2 2006.245.08:12:17.30#ibcon#about to read 6, iclass 3, count 2 2006.245.08:12:17.30#ibcon#read 6, iclass 3, count 2 2006.245.08:12:17.30#ibcon#end of sib2, iclass 3, count 2 2006.245.08:12:17.30#ibcon#*mode == 0, iclass 3, count 2 2006.245.08:12:17.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.08:12:17.30#ibcon#[27=AT01-04\r\n] 2006.245.08:12:17.30#ibcon#*before write, iclass 3, count 2 2006.245.08:12:17.30#ibcon#enter sib2, iclass 3, count 2 2006.245.08:12:17.30#ibcon#flushed, iclass 3, count 2 2006.245.08:12:17.30#ibcon#about to write, iclass 3, count 2 2006.245.08:12:17.30#ibcon#wrote, iclass 3, count 2 2006.245.08:12:17.30#ibcon#about to read 3, iclass 3, count 2 2006.245.08:12:17.33#ibcon#read 3, iclass 3, count 2 2006.245.08:12:17.33#ibcon#about to read 4, iclass 3, count 2 2006.245.08:12:17.33#ibcon#read 4, iclass 3, count 2 2006.245.08:12:17.33#ibcon#about to read 5, iclass 3, count 2 2006.245.08:12:17.33#ibcon#read 5, iclass 3, count 2 2006.245.08:12:17.33#ibcon#about to read 6, iclass 3, count 2 2006.245.08:12:17.33#ibcon#read 6, iclass 3, count 2 2006.245.08:12:17.33#ibcon#end of sib2, iclass 3, count 2 2006.245.08:12:17.33#ibcon#*after write, iclass 3, count 2 2006.245.08:12:17.33#ibcon#*before return 0, iclass 3, count 2 2006.245.08:12:17.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:12:17.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:12:17.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.08:12:17.33#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:17.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:12:17.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:12:17.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:12:17.45#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:12:17.45#ibcon#first serial, iclass 3, count 0 2006.245.08:12:17.45#ibcon#enter sib2, iclass 3, count 0 2006.245.08:12:17.45#ibcon#flushed, iclass 3, count 0 2006.245.08:12:17.45#ibcon#about to write, iclass 3, count 0 2006.245.08:12:17.45#ibcon#wrote, iclass 3, count 0 2006.245.08:12:17.45#ibcon#about to read 3, iclass 3, count 0 2006.245.08:12:17.47#ibcon#read 3, iclass 3, count 0 2006.245.08:12:17.47#ibcon#about to read 4, iclass 3, count 0 2006.245.08:12:17.47#ibcon#read 4, iclass 3, count 0 2006.245.08:12:17.47#ibcon#about to read 5, iclass 3, count 0 2006.245.08:12:17.47#ibcon#read 5, iclass 3, count 0 2006.245.08:12:17.47#ibcon#about to read 6, iclass 3, count 0 2006.245.08:12:17.47#ibcon#read 6, iclass 3, count 0 2006.245.08:12:17.47#ibcon#end of sib2, iclass 3, count 0 2006.245.08:12:17.47#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:12:17.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:12:17.47#ibcon#[27=USB\r\n] 2006.245.08:12:17.47#ibcon#*before write, iclass 3, count 0 2006.245.08:12:17.47#ibcon#enter sib2, iclass 3, count 0 2006.245.08:12:17.47#ibcon#flushed, iclass 3, count 0 2006.245.08:12:17.47#ibcon#about to write, iclass 3, count 0 2006.245.08:12:17.47#ibcon#wrote, iclass 3, count 0 2006.245.08:12:17.47#ibcon#about to read 3, iclass 3, count 0 2006.245.08:12:17.50#ibcon#read 3, iclass 3, count 0 2006.245.08:12:17.50#ibcon#about to read 4, iclass 3, count 0 2006.245.08:12:17.50#ibcon#read 4, iclass 3, count 0 2006.245.08:12:17.50#ibcon#about to read 5, iclass 3, count 0 2006.245.08:12:17.50#ibcon#read 5, iclass 3, count 0 2006.245.08:12:17.50#ibcon#about to read 6, iclass 3, count 0 2006.245.08:12:17.50#ibcon#read 6, iclass 3, count 0 2006.245.08:12:17.50#ibcon#end of sib2, iclass 3, count 0 2006.245.08:12:17.50#ibcon#*after write, iclass 3, count 0 2006.245.08:12:17.50#ibcon#*before return 0, iclass 3, count 0 2006.245.08:12:17.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:12:17.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:12:17.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:12:17.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:12:17.50$vc4f8/vblo=2,640.99 2006.245.08:12:17.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.08:12:17.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.08:12:17.50#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:17.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:17.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:17.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:17.50#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:12:17.50#ibcon#first serial, iclass 5, count 0 2006.245.08:12:17.50#ibcon#enter sib2, iclass 5, count 0 2006.245.08:12:17.50#ibcon#flushed, iclass 5, count 0 2006.245.08:12:17.50#ibcon#about to write, iclass 5, count 0 2006.245.08:12:17.50#ibcon#wrote, iclass 5, count 0 2006.245.08:12:17.50#ibcon#about to read 3, iclass 5, count 0 2006.245.08:12:17.52#ibcon#read 3, iclass 5, count 0 2006.245.08:12:17.52#ibcon#about to read 4, iclass 5, count 0 2006.245.08:12:17.52#ibcon#read 4, iclass 5, count 0 2006.245.08:12:17.52#ibcon#about to read 5, iclass 5, count 0 2006.245.08:12:17.52#ibcon#read 5, iclass 5, count 0 2006.245.08:12:17.52#ibcon#about to read 6, iclass 5, count 0 2006.245.08:12:17.52#ibcon#read 6, iclass 5, count 0 2006.245.08:12:17.52#ibcon#end of sib2, iclass 5, count 0 2006.245.08:12:17.52#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:12:17.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:12:17.52#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:12:17.52#ibcon#*before write, iclass 5, count 0 2006.245.08:12:17.52#ibcon#enter sib2, iclass 5, count 0 2006.245.08:12:17.52#ibcon#flushed, iclass 5, count 0 2006.245.08:12:17.52#ibcon#about to write, iclass 5, count 0 2006.245.08:12:17.52#ibcon#wrote, iclass 5, count 0 2006.245.08:12:17.52#ibcon#about to read 3, iclass 5, count 0 2006.245.08:12:17.56#ibcon#read 3, iclass 5, count 0 2006.245.08:12:17.56#ibcon#about to read 4, iclass 5, count 0 2006.245.08:12:17.56#ibcon#read 4, iclass 5, count 0 2006.245.08:12:17.56#ibcon#about to read 5, iclass 5, count 0 2006.245.08:12:17.56#ibcon#read 5, iclass 5, count 0 2006.245.08:12:17.56#ibcon#about to read 6, iclass 5, count 0 2006.245.08:12:17.56#ibcon#read 6, iclass 5, count 0 2006.245.08:12:17.56#ibcon#end of sib2, iclass 5, count 0 2006.245.08:12:17.56#ibcon#*after write, iclass 5, count 0 2006.245.08:12:17.56#ibcon#*before return 0, iclass 5, count 0 2006.245.08:12:17.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:17.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:12:17.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:12:17.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:12:17.56$vc4f8/vb=2,4 2006.245.08:12:17.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.08:12:17.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.08:12:17.56#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:17.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:17.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:17.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:17.62#ibcon#enter wrdev, iclass 7, count 2 2006.245.08:12:17.62#ibcon#first serial, iclass 7, count 2 2006.245.08:12:17.62#ibcon#enter sib2, iclass 7, count 2 2006.245.08:12:17.62#ibcon#flushed, iclass 7, count 2 2006.245.08:12:17.62#ibcon#about to write, iclass 7, count 2 2006.245.08:12:17.62#ibcon#wrote, iclass 7, count 2 2006.245.08:12:17.62#ibcon#about to read 3, iclass 7, count 2 2006.245.08:12:17.64#ibcon#read 3, iclass 7, count 2 2006.245.08:12:17.64#ibcon#about to read 4, iclass 7, count 2 2006.245.08:12:17.64#ibcon#read 4, iclass 7, count 2 2006.245.08:12:17.64#ibcon#about to read 5, iclass 7, count 2 2006.245.08:12:17.64#ibcon#read 5, iclass 7, count 2 2006.245.08:12:17.64#ibcon#about to read 6, iclass 7, count 2 2006.245.08:12:17.64#ibcon#read 6, iclass 7, count 2 2006.245.08:12:17.64#ibcon#end of sib2, iclass 7, count 2 2006.245.08:12:17.64#ibcon#*mode == 0, iclass 7, count 2 2006.245.08:12:17.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.08:12:17.64#ibcon#[27=AT02-04\r\n] 2006.245.08:12:17.64#ibcon#*before write, iclass 7, count 2 2006.245.08:12:17.64#ibcon#enter sib2, iclass 7, count 2 2006.245.08:12:17.64#ibcon#flushed, iclass 7, count 2 2006.245.08:12:17.64#ibcon#about to write, iclass 7, count 2 2006.245.08:12:17.64#ibcon#wrote, iclass 7, count 2 2006.245.08:12:17.64#ibcon#about to read 3, iclass 7, count 2 2006.245.08:12:17.67#ibcon#read 3, iclass 7, count 2 2006.245.08:12:17.67#ibcon#about to read 4, iclass 7, count 2 2006.245.08:12:17.67#ibcon#read 4, iclass 7, count 2 2006.245.08:12:17.67#ibcon#about to read 5, iclass 7, count 2 2006.245.08:12:17.67#ibcon#read 5, iclass 7, count 2 2006.245.08:12:17.67#ibcon#about to read 6, iclass 7, count 2 2006.245.08:12:17.67#ibcon#read 6, iclass 7, count 2 2006.245.08:12:17.67#ibcon#end of sib2, iclass 7, count 2 2006.245.08:12:17.67#ibcon#*after write, iclass 7, count 2 2006.245.08:12:17.67#ibcon#*before return 0, iclass 7, count 2 2006.245.08:12:17.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:17.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:12:17.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.08:12:17.67#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:17.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:17.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:17.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:17.79#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:12:17.79#ibcon#first serial, iclass 7, count 0 2006.245.08:12:17.79#ibcon#enter sib2, iclass 7, count 0 2006.245.08:12:17.79#ibcon#flushed, iclass 7, count 0 2006.245.08:12:17.79#ibcon#about to write, iclass 7, count 0 2006.245.08:12:17.79#ibcon#wrote, iclass 7, count 0 2006.245.08:12:17.79#ibcon#about to read 3, iclass 7, count 0 2006.245.08:12:17.81#ibcon#read 3, iclass 7, count 0 2006.245.08:12:17.81#ibcon#about to read 4, iclass 7, count 0 2006.245.08:12:17.81#ibcon#read 4, iclass 7, count 0 2006.245.08:12:17.81#ibcon#about to read 5, iclass 7, count 0 2006.245.08:12:17.81#ibcon#read 5, iclass 7, count 0 2006.245.08:12:17.81#ibcon#about to read 6, iclass 7, count 0 2006.245.08:12:17.81#ibcon#read 6, iclass 7, count 0 2006.245.08:12:17.81#ibcon#end of sib2, iclass 7, count 0 2006.245.08:12:17.81#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:12:17.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:12:17.81#ibcon#[27=USB\r\n] 2006.245.08:12:17.81#ibcon#*before write, iclass 7, count 0 2006.245.08:12:17.81#ibcon#enter sib2, iclass 7, count 0 2006.245.08:12:17.81#ibcon#flushed, iclass 7, count 0 2006.245.08:12:17.81#ibcon#about to write, iclass 7, count 0 2006.245.08:12:17.81#ibcon#wrote, iclass 7, count 0 2006.245.08:12:17.81#ibcon#about to read 3, iclass 7, count 0 2006.245.08:12:17.84#ibcon#read 3, iclass 7, count 0 2006.245.08:12:17.84#ibcon#about to read 4, iclass 7, count 0 2006.245.08:12:17.84#ibcon#read 4, iclass 7, count 0 2006.245.08:12:17.84#ibcon#about to read 5, iclass 7, count 0 2006.245.08:12:17.84#ibcon#read 5, iclass 7, count 0 2006.245.08:12:17.84#ibcon#about to read 6, iclass 7, count 0 2006.245.08:12:17.84#ibcon#read 6, iclass 7, count 0 2006.245.08:12:17.84#ibcon#end of sib2, iclass 7, count 0 2006.245.08:12:17.84#ibcon#*after write, iclass 7, count 0 2006.245.08:12:17.84#ibcon#*before return 0, iclass 7, count 0 2006.245.08:12:17.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:17.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:12:17.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:12:17.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:12:17.84$vc4f8/vblo=3,656.99 2006.245.08:12:17.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.08:12:17.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.08:12:17.84#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:17.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:17.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:17.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:17.84#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:12:17.84#ibcon#first serial, iclass 11, count 0 2006.245.08:12:17.84#ibcon#enter sib2, iclass 11, count 0 2006.245.08:12:17.84#ibcon#flushed, iclass 11, count 0 2006.245.08:12:17.84#ibcon#about to write, iclass 11, count 0 2006.245.08:12:17.84#ibcon#wrote, iclass 11, count 0 2006.245.08:12:17.84#ibcon#about to read 3, iclass 11, count 0 2006.245.08:12:17.86#ibcon#read 3, iclass 11, count 0 2006.245.08:12:17.86#ibcon#about to read 4, iclass 11, count 0 2006.245.08:12:17.86#ibcon#read 4, iclass 11, count 0 2006.245.08:12:17.86#ibcon#about to read 5, iclass 11, count 0 2006.245.08:12:17.86#ibcon#read 5, iclass 11, count 0 2006.245.08:12:17.86#ibcon#about to read 6, iclass 11, count 0 2006.245.08:12:17.86#ibcon#read 6, iclass 11, count 0 2006.245.08:12:17.86#ibcon#end of sib2, iclass 11, count 0 2006.245.08:12:17.86#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:12:17.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:12:17.86#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:12:17.86#ibcon#*before write, iclass 11, count 0 2006.245.08:12:17.86#ibcon#enter sib2, iclass 11, count 0 2006.245.08:12:17.86#ibcon#flushed, iclass 11, count 0 2006.245.08:12:17.86#ibcon#about to write, iclass 11, count 0 2006.245.08:12:17.86#ibcon#wrote, iclass 11, count 0 2006.245.08:12:17.86#ibcon#about to read 3, iclass 11, count 0 2006.245.08:12:17.90#ibcon#read 3, iclass 11, count 0 2006.245.08:12:17.90#ibcon#about to read 4, iclass 11, count 0 2006.245.08:12:17.90#ibcon#read 4, iclass 11, count 0 2006.245.08:12:17.90#ibcon#about to read 5, iclass 11, count 0 2006.245.08:12:17.90#ibcon#read 5, iclass 11, count 0 2006.245.08:12:17.90#ibcon#about to read 6, iclass 11, count 0 2006.245.08:12:17.90#ibcon#read 6, iclass 11, count 0 2006.245.08:12:17.90#ibcon#end of sib2, iclass 11, count 0 2006.245.08:12:17.90#ibcon#*after write, iclass 11, count 0 2006.245.08:12:17.90#ibcon#*before return 0, iclass 11, count 0 2006.245.08:12:17.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:17.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:12:17.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:12:17.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:12:17.90$vc4f8/vb=3,4 2006.245.08:12:17.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:12:17.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:12:17.90#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:17.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:17.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:17.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:17.97#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:12:17.97#ibcon#first serial, iclass 13, count 2 2006.245.08:12:17.97#ibcon#enter sib2, iclass 13, count 2 2006.245.08:12:17.97#ibcon#flushed, iclass 13, count 2 2006.245.08:12:17.97#ibcon#about to write, iclass 13, count 2 2006.245.08:12:17.97#ibcon#wrote, iclass 13, count 2 2006.245.08:12:17.97#ibcon#about to read 3, iclass 13, count 2 2006.245.08:12:17.98#ibcon#read 3, iclass 13, count 2 2006.245.08:12:17.98#ibcon#about to read 4, iclass 13, count 2 2006.245.08:12:17.98#ibcon#read 4, iclass 13, count 2 2006.245.08:12:17.98#ibcon#about to read 5, iclass 13, count 2 2006.245.08:12:17.98#ibcon#read 5, iclass 13, count 2 2006.245.08:12:17.98#ibcon#about to read 6, iclass 13, count 2 2006.245.08:12:17.98#ibcon#read 6, iclass 13, count 2 2006.245.08:12:17.98#ibcon#end of sib2, iclass 13, count 2 2006.245.08:12:17.98#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:12:17.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:12:17.98#ibcon#[27=AT03-04\r\n] 2006.245.08:12:17.98#ibcon#*before write, iclass 13, count 2 2006.245.08:12:17.98#ibcon#enter sib2, iclass 13, count 2 2006.245.08:12:17.98#ibcon#flushed, iclass 13, count 2 2006.245.08:12:17.98#ibcon#about to write, iclass 13, count 2 2006.245.08:12:17.98#ibcon#wrote, iclass 13, count 2 2006.245.08:12:17.98#ibcon#about to read 3, iclass 13, count 2 2006.245.08:12:18.01#ibcon#read 3, iclass 13, count 2 2006.245.08:12:18.01#ibcon#about to read 4, iclass 13, count 2 2006.245.08:12:18.01#ibcon#read 4, iclass 13, count 2 2006.245.08:12:18.01#ibcon#about to read 5, iclass 13, count 2 2006.245.08:12:18.01#ibcon#read 5, iclass 13, count 2 2006.245.08:12:18.01#ibcon#about to read 6, iclass 13, count 2 2006.245.08:12:18.01#ibcon#read 6, iclass 13, count 2 2006.245.08:12:18.01#ibcon#end of sib2, iclass 13, count 2 2006.245.08:12:18.01#ibcon#*after write, iclass 13, count 2 2006.245.08:12:18.01#ibcon#*before return 0, iclass 13, count 2 2006.245.08:12:18.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:18.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:12:18.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:12:18.01#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:18.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:18.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:18.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:18.13#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:12:18.13#ibcon#first serial, iclass 13, count 0 2006.245.08:12:18.13#ibcon#enter sib2, iclass 13, count 0 2006.245.08:12:18.13#ibcon#flushed, iclass 13, count 0 2006.245.08:12:18.13#ibcon#about to write, iclass 13, count 0 2006.245.08:12:18.13#ibcon#wrote, iclass 13, count 0 2006.245.08:12:18.13#ibcon#about to read 3, iclass 13, count 0 2006.245.08:12:18.15#ibcon#read 3, iclass 13, count 0 2006.245.08:12:18.15#ibcon#about to read 4, iclass 13, count 0 2006.245.08:12:18.15#ibcon#read 4, iclass 13, count 0 2006.245.08:12:18.15#ibcon#about to read 5, iclass 13, count 0 2006.245.08:12:18.15#ibcon#read 5, iclass 13, count 0 2006.245.08:12:18.15#ibcon#about to read 6, iclass 13, count 0 2006.245.08:12:18.15#ibcon#read 6, iclass 13, count 0 2006.245.08:12:18.15#ibcon#end of sib2, iclass 13, count 0 2006.245.08:12:18.15#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:12:18.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:12:18.15#ibcon#[27=USB\r\n] 2006.245.08:12:18.15#ibcon#*before write, iclass 13, count 0 2006.245.08:12:18.15#ibcon#enter sib2, iclass 13, count 0 2006.245.08:12:18.15#ibcon#flushed, iclass 13, count 0 2006.245.08:12:18.15#ibcon#about to write, iclass 13, count 0 2006.245.08:12:18.15#ibcon#wrote, iclass 13, count 0 2006.245.08:12:18.15#ibcon#about to read 3, iclass 13, count 0 2006.245.08:12:18.18#ibcon#read 3, iclass 13, count 0 2006.245.08:12:18.18#ibcon#about to read 4, iclass 13, count 0 2006.245.08:12:18.18#ibcon#read 4, iclass 13, count 0 2006.245.08:12:18.18#ibcon#about to read 5, iclass 13, count 0 2006.245.08:12:18.18#ibcon#read 5, iclass 13, count 0 2006.245.08:12:18.18#ibcon#about to read 6, iclass 13, count 0 2006.245.08:12:18.18#ibcon#read 6, iclass 13, count 0 2006.245.08:12:18.18#ibcon#end of sib2, iclass 13, count 0 2006.245.08:12:18.18#ibcon#*after write, iclass 13, count 0 2006.245.08:12:18.18#ibcon#*before return 0, iclass 13, count 0 2006.245.08:12:18.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:18.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:12:18.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:12:18.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:12:18.18$vc4f8/vblo=4,712.99 2006.245.08:12:18.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.08:12:18.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.08:12:18.18#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:18.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:18.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:18.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:18.18#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:12:18.18#ibcon#first serial, iclass 15, count 0 2006.245.08:12:18.18#ibcon#enter sib2, iclass 15, count 0 2006.245.08:12:18.18#ibcon#flushed, iclass 15, count 0 2006.245.08:12:18.18#ibcon#about to write, iclass 15, count 0 2006.245.08:12:18.18#ibcon#wrote, iclass 15, count 0 2006.245.08:12:18.18#ibcon#about to read 3, iclass 15, count 0 2006.245.08:12:18.20#ibcon#read 3, iclass 15, count 0 2006.245.08:12:18.20#ibcon#about to read 4, iclass 15, count 0 2006.245.08:12:18.20#ibcon#read 4, iclass 15, count 0 2006.245.08:12:18.20#ibcon#about to read 5, iclass 15, count 0 2006.245.08:12:18.20#ibcon#read 5, iclass 15, count 0 2006.245.08:12:18.20#ibcon#about to read 6, iclass 15, count 0 2006.245.08:12:18.20#ibcon#read 6, iclass 15, count 0 2006.245.08:12:18.20#ibcon#end of sib2, iclass 15, count 0 2006.245.08:12:18.20#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:12:18.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:12:18.20#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:12:18.20#ibcon#*before write, iclass 15, count 0 2006.245.08:12:18.20#ibcon#enter sib2, iclass 15, count 0 2006.245.08:12:18.20#ibcon#flushed, iclass 15, count 0 2006.245.08:12:18.20#ibcon#about to write, iclass 15, count 0 2006.245.08:12:18.20#ibcon#wrote, iclass 15, count 0 2006.245.08:12:18.20#ibcon#about to read 3, iclass 15, count 0 2006.245.08:12:18.24#ibcon#read 3, iclass 15, count 0 2006.245.08:12:18.24#ibcon#about to read 4, iclass 15, count 0 2006.245.08:12:18.24#ibcon#read 4, iclass 15, count 0 2006.245.08:12:18.24#ibcon#about to read 5, iclass 15, count 0 2006.245.08:12:18.24#ibcon#read 5, iclass 15, count 0 2006.245.08:12:18.24#ibcon#about to read 6, iclass 15, count 0 2006.245.08:12:18.24#ibcon#read 6, iclass 15, count 0 2006.245.08:12:18.24#ibcon#end of sib2, iclass 15, count 0 2006.245.08:12:18.24#ibcon#*after write, iclass 15, count 0 2006.245.08:12:18.24#ibcon#*before return 0, iclass 15, count 0 2006.245.08:12:18.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:18.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:12:18.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:12:18.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:12:18.24$vc4f8/vb=4,4 2006.245.08:12:18.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.08:12:18.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.08:12:18.24#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:18.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:18.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:18.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:18.30#ibcon#enter wrdev, iclass 17, count 2 2006.245.08:12:18.30#ibcon#first serial, iclass 17, count 2 2006.245.08:12:18.30#ibcon#enter sib2, iclass 17, count 2 2006.245.08:12:18.30#ibcon#flushed, iclass 17, count 2 2006.245.08:12:18.30#ibcon#about to write, iclass 17, count 2 2006.245.08:12:18.30#ibcon#wrote, iclass 17, count 2 2006.245.08:12:18.30#ibcon#about to read 3, iclass 17, count 2 2006.245.08:12:18.32#ibcon#read 3, iclass 17, count 2 2006.245.08:12:18.32#ibcon#about to read 4, iclass 17, count 2 2006.245.08:12:18.32#ibcon#read 4, iclass 17, count 2 2006.245.08:12:18.32#ibcon#about to read 5, iclass 17, count 2 2006.245.08:12:18.32#ibcon#read 5, iclass 17, count 2 2006.245.08:12:18.32#ibcon#about to read 6, iclass 17, count 2 2006.245.08:12:18.32#ibcon#read 6, iclass 17, count 2 2006.245.08:12:18.32#ibcon#end of sib2, iclass 17, count 2 2006.245.08:12:18.32#ibcon#*mode == 0, iclass 17, count 2 2006.245.08:12:18.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.08:12:18.32#ibcon#[27=AT04-04\r\n] 2006.245.08:12:18.32#ibcon#*before write, iclass 17, count 2 2006.245.08:12:18.32#ibcon#enter sib2, iclass 17, count 2 2006.245.08:12:18.32#ibcon#flushed, iclass 17, count 2 2006.245.08:12:18.32#ibcon#about to write, iclass 17, count 2 2006.245.08:12:18.32#ibcon#wrote, iclass 17, count 2 2006.245.08:12:18.32#ibcon#about to read 3, iclass 17, count 2 2006.245.08:12:18.35#ibcon#read 3, iclass 17, count 2 2006.245.08:12:18.35#ibcon#about to read 4, iclass 17, count 2 2006.245.08:12:18.35#ibcon#read 4, iclass 17, count 2 2006.245.08:12:18.35#ibcon#about to read 5, iclass 17, count 2 2006.245.08:12:18.35#ibcon#read 5, iclass 17, count 2 2006.245.08:12:18.35#ibcon#about to read 6, iclass 17, count 2 2006.245.08:12:18.35#ibcon#read 6, iclass 17, count 2 2006.245.08:12:18.35#ibcon#end of sib2, iclass 17, count 2 2006.245.08:12:18.35#ibcon#*after write, iclass 17, count 2 2006.245.08:12:18.35#ibcon#*before return 0, iclass 17, count 2 2006.245.08:12:18.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:18.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:12:18.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.08:12:18.35#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:18.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:18.47#abcon#<5=/05 3.0 5.1 26.91 741004.5\r\n> 2006.245.08:12:18.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:18.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:18.47#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:12:18.47#ibcon#first serial, iclass 17, count 0 2006.245.08:12:18.47#ibcon#enter sib2, iclass 17, count 0 2006.245.08:12:18.47#ibcon#flushed, iclass 17, count 0 2006.245.08:12:18.47#ibcon#about to write, iclass 17, count 0 2006.245.08:12:18.47#ibcon#wrote, iclass 17, count 0 2006.245.08:12:18.47#ibcon#about to read 3, iclass 17, count 0 2006.245.08:12:18.49#ibcon#read 3, iclass 17, count 0 2006.245.08:12:18.49#ibcon#about to read 4, iclass 17, count 0 2006.245.08:12:18.49#ibcon#read 4, iclass 17, count 0 2006.245.08:12:18.49#ibcon#about to read 5, iclass 17, count 0 2006.245.08:12:18.49#ibcon#read 5, iclass 17, count 0 2006.245.08:12:18.49#ibcon#about to read 6, iclass 17, count 0 2006.245.08:12:18.49#ibcon#read 6, iclass 17, count 0 2006.245.08:12:18.49#ibcon#end of sib2, iclass 17, count 0 2006.245.08:12:18.49#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:12:18.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:12:18.49#ibcon#[27=USB\r\n] 2006.245.08:12:18.49#ibcon#*before write, iclass 17, count 0 2006.245.08:12:18.49#ibcon#enter sib2, iclass 17, count 0 2006.245.08:12:18.49#ibcon#flushed, iclass 17, count 0 2006.245.08:12:18.49#ibcon#about to write, iclass 17, count 0 2006.245.08:12:18.49#ibcon#wrote, iclass 17, count 0 2006.245.08:12:18.49#ibcon#about to read 3, iclass 17, count 0 2006.245.08:12:18.49#abcon#{5=INTERFACE CLEAR} 2006.245.08:12:18.52#ibcon#read 3, iclass 17, count 0 2006.245.08:12:18.52#ibcon#about to read 4, iclass 17, count 0 2006.245.08:12:18.52#ibcon#read 4, iclass 17, count 0 2006.245.08:12:18.52#ibcon#about to read 5, iclass 17, count 0 2006.245.08:12:18.52#ibcon#read 5, iclass 17, count 0 2006.245.08:12:18.52#ibcon#about to read 6, iclass 17, count 0 2006.245.08:12:18.52#ibcon#read 6, iclass 17, count 0 2006.245.08:12:18.52#ibcon#end of sib2, iclass 17, count 0 2006.245.08:12:18.52#ibcon#*after write, iclass 17, count 0 2006.245.08:12:18.52#ibcon#*before return 0, iclass 17, count 0 2006.245.08:12:18.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:18.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:12:18.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:12:18.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:12:18.52$vc4f8/vblo=5,744.99 2006.245.08:12:18.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:12:18.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:12:18.52#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:18.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:12:18.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:12:18.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:12:18.52#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:12:18.52#ibcon#first serial, iclass 22, count 0 2006.245.08:12:18.52#ibcon#enter sib2, iclass 22, count 0 2006.245.08:12:18.52#ibcon#flushed, iclass 22, count 0 2006.245.08:12:18.52#ibcon#about to write, iclass 22, count 0 2006.245.08:12:18.52#ibcon#wrote, iclass 22, count 0 2006.245.08:12:18.52#ibcon#about to read 3, iclass 22, count 0 2006.245.08:12:18.54#ibcon#read 3, iclass 22, count 0 2006.245.08:12:18.54#ibcon#about to read 4, iclass 22, count 0 2006.245.08:12:18.54#ibcon#read 4, iclass 22, count 0 2006.245.08:12:18.54#ibcon#about to read 5, iclass 22, count 0 2006.245.08:12:18.54#ibcon#read 5, iclass 22, count 0 2006.245.08:12:18.54#ibcon#about to read 6, iclass 22, count 0 2006.245.08:12:18.54#ibcon#read 6, iclass 22, count 0 2006.245.08:12:18.54#ibcon#end of sib2, iclass 22, count 0 2006.245.08:12:18.54#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:12:18.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:12:18.54#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:12:18.54#ibcon#*before write, iclass 22, count 0 2006.245.08:12:18.54#ibcon#enter sib2, iclass 22, count 0 2006.245.08:12:18.54#ibcon#flushed, iclass 22, count 0 2006.245.08:12:18.54#ibcon#about to write, iclass 22, count 0 2006.245.08:12:18.54#ibcon#wrote, iclass 22, count 0 2006.245.08:12:18.54#ibcon#about to read 3, iclass 22, count 0 2006.245.08:12:18.55#abcon#[5=S1D000X0/0*\r\n] 2006.245.08:12:18.58#ibcon#read 3, iclass 22, count 0 2006.245.08:12:18.58#ibcon#about to read 4, iclass 22, count 0 2006.245.08:12:18.58#ibcon#read 4, iclass 22, count 0 2006.245.08:12:18.58#ibcon#about to read 5, iclass 22, count 0 2006.245.08:12:18.58#ibcon#read 5, iclass 22, count 0 2006.245.08:12:18.58#ibcon#about to read 6, iclass 22, count 0 2006.245.08:12:18.58#ibcon#read 6, iclass 22, count 0 2006.245.08:12:18.58#ibcon#end of sib2, iclass 22, count 0 2006.245.08:12:18.58#ibcon#*after write, iclass 22, count 0 2006.245.08:12:18.58#ibcon#*before return 0, iclass 22, count 0 2006.245.08:12:18.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:12:18.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:12:18.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:12:18.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:12:18.58$vc4f8/vb=5,3 2006.245.08:12:18.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.08:12:18.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.08:12:18.58#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:18.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:18.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:18.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:18.64#ibcon#enter wrdev, iclass 25, count 2 2006.245.08:12:18.64#ibcon#first serial, iclass 25, count 2 2006.245.08:12:18.64#ibcon#enter sib2, iclass 25, count 2 2006.245.08:12:18.64#ibcon#flushed, iclass 25, count 2 2006.245.08:12:18.64#ibcon#about to write, iclass 25, count 2 2006.245.08:12:18.64#ibcon#wrote, iclass 25, count 2 2006.245.08:12:18.64#ibcon#about to read 3, iclass 25, count 2 2006.245.08:12:18.66#ibcon#read 3, iclass 25, count 2 2006.245.08:12:18.66#ibcon#about to read 4, iclass 25, count 2 2006.245.08:12:18.66#ibcon#read 4, iclass 25, count 2 2006.245.08:12:18.66#ibcon#about to read 5, iclass 25, count 2 2006.245.08:12:18.66#ibcon#read 5, iclass 25, count 2 2006.245.08:12:18.66#ibcon#about to read 6, iclass 25, count 2 2006.245.08:12:18.66#ibcon#read 6, iclass 25, count 2 2006.245.08:12:18.66#ibcon#end of sib2, iclass 25, count 2 2006.245.08:12:18.66#ibcon#*mode == 0, iclass 25, count 2 2006.245.08:12:18.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.08:12:18.66#ibcon#[27=AT05-03\r\n] 2006.245.08:12:18.66#ibcon#*before write, iclass 25, count 2 2006.245.08:12:18.66#ibcon#enter sib2, iclass 25, count 2 2006.245.08:12:18.66#ibcon#flushed, iclass 25, count 2 2006.245.08:12:18.66#ibcon#about to write, iclass 25, count 2 2006.245.08:12:18.66#ibcon#wrote, iclass 25, count 2 2006.245.08:12:18.66#ibcon#about to read 3, iclass 25, count 2 2006.245.08:12:18.69#ibcon#read 3, iclass 25, count 2 2006.245.08:12:18.69#ibcon#about to read 4, iclass 25, count 2 2006.245.08:12:18.69#ibcon#read 4, iclass 25, count 2 2006.245.08:12:18.69#ibcon#about to read 5, iclass 25, count 2 2006.245.08:12:18.69#ibcon#read 5, iclass 25, count 2 2006.245.08:12:18.69#ibcon#about to read 6, iclass 25, count 2 2006.245.08:12:18.69#ibcon#read 6, iclass 25, count 2 2006.245.08:12:18.69#ibcon#end of sib2, iclass 25, count 2 2006.245.08:12:18.69#ibcon#*after write, iclass 25, count 2 2006.245.08:12:18.69#ibcon#*before return 0, iclass 25, count 2 2006.245.08:12:18.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:18.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:12:18.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.08:12:18.69#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:18.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:18.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:18.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:18.81#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:12:18.81#ibcon#first serial, iclass 25, count 0 2006.245.08:12:18.81#ibcon#enter sib2, iclass 25, count 0 2006.245.08:12:18.81#ibcon#flushed, iclass 25, count 0 2006.245.08:12:18.81#ibcon#about to write, iclass 25, count 0 2006.245.08:12:18.81#ibcon#wrote, iclass 25, count 0 2006.245.08:12:18.81#ibcon#about to read 3, iclass 25, count 0 2006.245.08:12:18.83#ibcon#read 3, iclass 25, count 0 2006.245.08:12:18.83#ibcon#about to read 4, iclass 25, count 0 2006.245.08:12:18.83#ibcon#read 4, iclass 25, count 0 2006.245.08:12:18.83#ibcon#about to read 5, iclass 25, count 0 2006.245.08:12:18.83#ibcon#read 5, iclass 25, count 0 2006.245.08:12:18.83#ibcon#about to read 6, iclass 25, count 0 2006.245.08:12:18.83#ibcon#read 6, iclass 25, count 0 2006.245.08:12:18.83#ibcon#end of sib2, iclass 25, count 0 2006.245.08:12:18.83#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:12:18.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:12:18.83#ibcon#[27=USB\r\n] 2006.245.08:12:18.83#ibcon#*before write, iclass 25, count 0 2006.245.08:12:18.83#ibcon#enter sib2, iclass 25, count 0 2006.245.08:12:18.83#ibcon#flushed, iclass 25, count 0 2006.245.08:12:18.83#ibcon#about to write, iclass 25, count 0 2006.245.08:12:18.83#ibcon#wrote, iclass 25, count 0 2006.245.08:12:18.83#ibcon#about to read 3, iclass 25, count 0 2006.245.08:12:18.86#ibcon#read 3, iclass 25, count 0 2006.245.08:12:18.86#ibcon#about to read 4, iclass 25, count 0 2006.245.08:12:18.86#ibcon#read 4, iclass 25, count 0 2006.245.08:12:18.86#ibcon#about to read 5, iclass 25, count 0 2006.245.08:12:18.86#ibcon#read 5, iclass 25, count 0 2006.245.08:12:18.86#ibcon#about to read 6, iclass 25, count 0 2006.245.08:12:18.86#ibcon#read 6, iclass 25, count 0 2006.245.08:12:18.86#ibcon#end of sib2, iclass 25, count 0 2006.245.08:12:18.86#ibcon#*after write, iclass 25, count 0 2006.245.08:12:18.86#ibcon#*before return 0, iclass 25, count 0 2006.245.08:12:18.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:18.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:12:18.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:12:18.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:12:18.86$vc4f8/vblo=6,752.99 2006.245.08:12:18.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.08:12:18.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.08:12:18.86#ibcon#ireg 17 cls_cnt 0 2006.245.08:12:18.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:18.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:18.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:18.86#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:12:18.86#ibcon#first serial, iclass 27, count 0 2006.245.08:12:18.86#ibcon#enter sib2, iclass 27, count 0 2006.245.08:12:18.86#ibcon#flushed, iclass 27, count 0 2006.245.08:12:18.86#ibcon#about to write, iclass 27, count 0 2006.245.08:12:18.86#ibcon#wrote, iclass 27, count 0 2006.245.08:12:18.86#ibcon#about to read 3, iclass 27, count 0 2006.245.08:12:18.88#ibcon#read 3, iclass 27, count 0 2006.245.08:12:18.88#ibcon#about to read 4, iclass 27, count 0 2006.245.08:12:18.88#ibcon#read 4, iclass 27, count 0 2006.245.08:12:18.88#ibcon#about to read 5, iclass 27, count 0 2006.245.08:12:18.88#ibcon#read 5, iclass 27, count 0 2006.245.08:12:18.88#ibcon#about to read 6, iclass 27, count 0 2006.245.08:12:18.88#ibcon#read 6, iclass 27, count 0 2006.245.08:12:18.88#ibcon#end of sib2, iclass 27, count 0 2006.245.08:12:18.88#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:12:18.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:12:18.88#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:12:18.88#ibcon#*before write, iclass 27, count 0 2006.245.08:12:18.88#ibcon#enter sib2, iclass 27, count 0 2006.245.08:12:18.88#ibcon#flushed, iclass 27, count 0 2006.245.08:12:18.88#ibcon#about to write, iclass 27, count 0 2006.245.08:12:18.88#ibcon#wrote, iclass 27, count 0 2006.245.08:12:18.88#ibcon#about to read 3, iclass 27, count 0 2006.245.08:12:18.92#ibcon#read 3, iclass 27, count 0 2006.245.08:12:18.92#ibcon#about to read 4, iclass 27, count 0 2006.245.08:12:18.92#ibcon#read 4, iclass 27, count 0 2006.245.08:12:18.92#ibcon#about to read 5, iclass 27, count 0 2006.245.08:12:18.92#ibcon#read 5, iclass 27, count 0 2006.245.08:12:18.92#ibcon#about to read 6, iclass 27, count 0 2006.245.08:12:18.92#ibcon#read 6, iclass 27, count 0 2006.245.08:12:18.92#ibcon#end of sib2, iclass 27, count 0 2006.245.08:12:18.92#ibcon#*after write, iclass 27, count 0 2006.245.08:12:18.92#ibcon#*before return 0, iclass 27, count 0 2006.245.08:12:18.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:18.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:12:18.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:12:18.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:12:18.92$vc4f8/vb=6,3 2006.245.08:12:18.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.08:12:18.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.08:12:18.92#ibcon#ireg 11 cls_cnt 2 2006.245.08:12:18.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:18.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:18.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:18.99#ibcon#enter wrdev, iclass 29, count 2 2006.245.08:12:18.99#ibcon#first serial, iclass 29, count 2 2006.245.08:12:18.99#ibcon#enter sib2, iclass 29, count 2 2006.245.08:12:18.99#ibcon#flushed, iclass 29, count 2 2006.245.08:12:18.99#ibcon#about to write, iclass 29, count 2 2006.245.08:12:18.99#ibcon#wrote, iclass 29, count 2 2006.245.08:12:18.99#ibcon#about to read 3, iclass 29, count 2 2006.245.08:12:19.00#ibcon#read 3, iclass 29, count 2 2006.245.08:12:19.00#ibcon#about to read 4, iclass 29, count 2 2006.245.08:12:19.00#ibcon#read 4, iclass 29, count 2 2006.245.08:12:19.00#ibcon#about to read 5, iclass 29, count 2 2006.245.08:12:19.00#ibcon#read 5, iclass 29, count 2 2006.245.08:12:19.00#ibcon#about to read 6, iclass 29, count 2 2006.245.08:12:19.00#ibcon#read 6, iclass 29, count 2 2006.245.08:12:19.00#ibcon#end of sib2, iclass 29, count 2 2006.245.08:12:19.00#ibcon#*mode == 0, iclass 29, count 2 2006.245.08:12:19.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.08:12:19.00#ibcon#[27=AT06-03\r\n] 2006.245.08:12:19.00#ibcon#*before write, iclass 29, count 2 2006.245.08:12:19.00#ibcon#enter sib2, iclass 29, count 2 2006.245.08:12:19.00#ibcon#flushed, iclass 29, count 2 2006.245.08:12:19.00#ibcon#about to write, iclass 29, count 2 2006.245.08:12:19.00#ibcon#wrote, iclass 29, count 2 2006.245.08:12:19.00#ibcon#about to read 3, iclass 29, count 2 2006.245.08:12:19.03#ibcon#read 3, iclass 29, count 2 2006.245.08:12:19.03#ibcon#about to read 4, iclass 29, count 2 2006.245.08:12:19.03#ibcon#read 4, iclass 29, count 2 2006.245.08:12:19.03#ibcon#about to read 5, iclass 29, count 2 2006.245.08:12:19.03#ibcon#read 5, iclass 29, count 2 2006.245.08:12:19.03#ibcon#about to read 6, iclass 29, count 2 2006.245.08:12:19.03#ibcon#read 6, iclass 29, count 2 2006.245.08:12:19.03#ibcon#end of sib2, iclass 29, count 2 2006.245.08:12:19.03#ibcon#*after write, iclass 29, count 2 2006.245.08:12:19.03#ibcon#*before return 0, iclass 29, count 2 2006.245.08:12:19.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:19.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:12:19.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.08:12:19.03#ibcon#ireg 7 cls_cnt 0 2006.245.08:12:19.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:19.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:19.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:19.15#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:12:19.15#ibcon#first serial, iclass 29, count 0 2006.245.08:12:19.15#ibcon#enter sib2, iclass 29, count 0 2006.245.08:12:19.15#ibcon#flushed, iclass 29, count 0 2006.245.08:12:19.15#ibcon#about to write, iclass 29, count 0 2006.245.08:12:19.15#ibcon#wrote, iclass 29, count 0 2006.245.08:12:19.15#ibcon#about to read 3, iclass 29, count 0 2006.245.08:12:19.17#ibcon#read 3, iclass 29, count 0 2006.245.08:12:19.17#ibcon#about to read 4, iclass 29, count 0 2006.245.08:12:19.17#ibcon#read 4, iclass 29, count 0 2006.245.08:12:19.17#ibcon#about to read 5, iclass 29, count 0 2006.245.08:12:19.17#ibcon#read 5, iclass 29, count 0 2006.245.08:12:19.17#ibcon#about to read 6, iclass 29, count 0 2006.245.08:12:19.17#ibcon#read 6, iclass 29, count 0 2006.245.08:12:19.17#ibcon#end of sib2, iclass 29, count 0 2006.245.08:12:19.17#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:12:19.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:12:19.17#ibcon#[27=USB\r\n] 2006.245.08:12:19.17#ibcon#*before write, iclass 29, count 0 2006.245.08:12:19.17#ibcon#enter sib2, iclass 29, count 0 2006.245.08:12:19.17#ibcon#flushed, iclass 29, count 0 2006.245.08:12:19.17#ibcon#about to write, iclass 29, count 0 2006.245.08:12:19.17#ibcon#wrote, iclass 29, count 0 2006.245.08:12:19.17#ibcon#about to read 3, iclass 29, count 0 2006.245.08:12:19.20#ibcon#read 3, iclass 29, count 0 2006.245.08:12:19.20#ibcon#about to read 4, iclass 29, count 0 2006.245.08:12:19.20#ibcon#read 4, iclass 29, count 0 2006.245.08:12:19.20#ibcon#about to read 5, iclass 29, count 0 2006.245.08:12:19.20#ibcon#read 5, iclass 29, count 0 2006.245.08:12:19.20#ibcon#about to read 6, iclass 29, count 0 2006.245.08:12:19.20#ibcon#read 6, iclass 29, count 0 2006.245.08:12:19.20#ibcon#end of sib2, iclass 29, count 0 2006.245.08:12:19.20#ibcon#*after write, iclass 29, count 0 2006.245.08:12:19.20#ibcon#*before return 0, iclass 29, count 0 2006.245.08:12:19.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:19.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:12:19.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:12:19.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:12:19.20$vc4f8/vabw=wide 2006.245.08:12:19.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.08:12:19.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.08:12:19.20#ibcon#ireg 8 cls_cnt 0 2006.245.08:12:19.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:19.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:19.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:19.20#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:12:19.20#ibcon#first serial, iclass 31, count 0 2006.245.08:12:19.20#ibcon#enter sib2, iclass 31, count 0 2006.245.08:12:19.20#ibcon#flushed, iclass 31, count 0 2006.245.08:12:19.20#ibcon#about to write, iclass 31, count 0 2006.245.08:12:19.20#ibcon#wrote, iclass 31, count 0 2006.245.08:12:19.20#ibcon#about to read 3, iclass 31, count 0 2006.245.08:12:19.22#ibcon#read 3, iclass 31, count 0 2006.245.08:12:19.22#ibcon#about to read 4, iclass 31, count 0 2006.245.08:12:19.22#ibcon#read 4, iclass 31, count 0 2006.245.08:12:19.22#ibcon#about to read 5, iclass 31, count 0 2006.245.08:12:19.22#ibcon#read 5, iclass 31, count 0 2006.245.08:12:19.22#ibcon#about to read 6, iclass 31, count 0 2006.245.08:12:19.22#ibcon#read 6, iclass 31, count 0 2006.245.08:12:19.22#ibcon#end of sib2, iclass 31, count 0 2006.245.08:12:19.22#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:12:19.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:12:19.22#ibcon#[25=BW32\r\n] 2006.245.08:12:19.22#ibcon#*before write, iclass 31, count 0 2006.245.08:12:19.22#ibcon#enter sib2, iclass 31, count 0 2006.245.08:12:19.22#ibcon#flushed, iclass 31, count 0 2006.245.08:12:19.22#ibcon#about to write, iclass 31, count 0 2006.245.08:12:19.22#ibcon#wrote, iclass 31, count 0 2006.245.08:12:19.22#ibcon#about to read 3, iclass 31, count 0 2006.245.08:12:19.25#ibcon#read 3, iclass 31, count 0 2006.245.08:12:19.25#ibcon#about to read 4, iclass 31, count 0 2006.245.08:12:19.25#ibcon#read 4, iclass 31, count 0 2006.245.08:12:19.25#ibcon#about to read 5, iclass 31, count 0 2006.245.08:12:19.25#ibcon#read 5, iclass 31, count 0 2006.245.08:12:19.25#ibcon#about to read 6, iclass 31, count 0 2006.245.08:12:19.25#ibcon#read 6, iclass 31, count 0 2006.245.08:12:19.25#ibcon#end of sib2, iclass 31, count 0 2006.245.08:12:19.25#ibcon#*after write, iclass 31, count 0 2006.245.08:12:19.25#ibcon#*before return 0, iclass 31, count 0 2006.245.08:12:19.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:19.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:12:19.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:12:19.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:12:19.25$vc4f8/vbbw=wide 2006.245.08:12:19.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:12:19.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:12:19.25#ibcon#ireg 8 cls_cnt 0 2006.245.08:12:19.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:12:19.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:12:19.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:12:19.32#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:12:19.32#ibcon#first serial, iclass 33, count 0 2006.245.08:12:19.32#ibcon#enter sib2, iclass 33, count 0 2006.245.08:12:19.32#ibcon#flushed, iclass 33, count 0 2006.245.08:12:19.32#ibcon#about to write, iclass 33, count 0 2006.245.08:12:19.32#ibcon#wrote, iclass 33, count 0 2006.245.08:12:19.32#ibcon#about to read 3, iclass 33, count 0 2006.245.08:12:19.34#ibcon#read 3, iclass 33, count 0 2006.245.08:12:19.34#ibcon#about to read 4, iclass 33, count 0 2006.245.08:12:19.34#ibcon#read 4, iclass 33, count 0 2006.245.08:12:19.34#ibcon#about to read 5, iclass 33, count 0 2006.245.08:12:19.34#ibcon#read 5, iclass 33, count 0 2006.245.08:12:19.34#ibcon#about to read 6, iclass 33, count 0 2006.245.08:12:19.34#ibcon#read 6, iclass 33, count 0 2006.245.08:12:19.34#ibcon#end of sib2, iclass 33, count 0 2006.245.08:12:19.34#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:12:19.34#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:12:19.34#ibcon#[27=BW32\r\n] 2006.245.08:12:19.34#ibcon#*before write, iclass 33, count 0 2006.245.08:12:19.34#ibcon#enter sib2, iclass 33, count 0 2006.245.08:12:19.34#ibcon#flushed, iclass 33, count 0 2006.245.08:12:19.34#ibcon#about to write, iclass 33, count 0 2006.245.08:12:19.34#ibcon#wrote, iclass 33, count 0 2006.245.08:12:19.34#ibcon#about to read 3, iclass 33, count 0 2006.245.08:12:19.37#ibcon#read 3, iclass 33, count 0 2006.245.08:12:19.37#ibcon#about to read 4, iclass 33, count 0 2006.245.08:12:19.37#ibcon#read 4, iclass 33, count 0 2006.245.08:12:19.37#ibcon#about to read 5, iclass 33, count 0 2006.245.08:12:19.37#ibcon#read 5, iclass 33, count 0 2006.245.08:12:19.37#ibcon#about to read 6, iclass 33, count 0 2006.245.08:12:19.37#ibcon#read 6, iclass 33, count 0 2006.245.08:12:19.37#ibcon#end of sib2, iclass 33, count 0 2006.245.08:12:19.37#ibcon#*after write, iclass 33, count 0 2006.245.08:12:19.37#ibcon#*before return 0, iclass 33, count 0 2006.245.08:12:19.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:12:19.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:12:19.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:12:19.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:12:19.37$4f8m12a/ifd4f 2006.245.08:12:19.37$ifd4f/lo= 2006.245.08:12:19.37$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:12:19.37$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:12:19.37$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:12:19.37$ifd4f/patch= 2006.245.08:12:19.37$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:12:19.37$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:12:19.37$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:12:19.37$4f8m12a/"form=m,16.000,1:2 2006.245.08:12:19.37$4f8m12a/"tpicd 2006.245.08:12:19.37$4f8m12a/echo=off 2006.245.08:12:19.37$4f8m12a/xlog=off 2006.245.08:12:19.37:!2006.245.08:12:40 2006.245.08:12:40.00:preob 2006.245.08:12:41.13/onsource/TRACKING 2006.245.08:12:41.13:!2006.245.08:12:50 2006.245.08:12:50.00:data_valid=on 2006.245.08:12:50.00:midob 2006.245.08:12:50.13/onsource/TRACKING 2006.245.08:12:50.13/wx/26.89,1004.5,74 2006.245.08:12:50.29/cable/+6.4091E-03 2006.245.08:12:51.38/va/01,08,usb,yes,31,32 2006.245.08:12:51.38/va/02,07,usb,yes,31,32 2006.245.08:12:51.38/va/03,06,usb,yes,33,33 2006.245.08:12:51.38/va/04,07,usb,yes,32,34 2006.245.08:12:51.38/va/05,07,usb,yes,33,35 2006.245.08:12:51.38/va/06,07,usb,yes,29,29 2006.245.08:12:51.38/va/07,07,usb,yes,29,29 2006.245.08:12:51.38/va/08,08,usb,yes,25,25 2006.245.08:12:51.61/valo/01,532.99,yes,locked 2006.245.08:12:51.61/valo/02,572.99,yes,locked 2006.245.08:12:51.61/valo/03,672.99,yes,locked 2006.245.08:12:51.61/valo/04,832.99,yes,locked 2006.245.08:12:51.61/valo/05,652.99,yes,locked 2006.245.08:12:51.61/valo/06,772.99,yes,locked 2006.245.08:12:51.61/valo/07,832.99,yes,locked 2006.245.08:12:51.61/valo/08,852.99,yes,locked 2006.245.08:12:52.70/vb/01,04,usb,yes,30,29 2006.245.08:12:52.70/vb/02,04,usb,yes,32,33 2006.245.08:12:52.70/vb/03,04,usb,yes,28,32 2006.245.08:12:52.70/vb/04,04,usb,yes,29,29 2006.245.08:12:52.70/vb/05,03,usb,yes,35,39 2006.245.08:12:52.70/vb/06,03,usb,yes,35,39 2006.245.08:12:52.70/vb/07,04,usb,yes,31,31 2006.245.08:12:52.70/vb/08,03,usb,yes,35,39 2006.245.08:12:52.93/vblo/01,632.99,yes,locked 2006.245.08:12:52.93/vblo/02,640.99,yes,locked 2006.245.08:12:52.93/vblo/03,656.99,yes,locked 2006.245.08:12:52.93/vblo/04,712.99,yes,locked 2006.245.08:12:52.93/vblo/05,744.99,yes,locked 2006.245.08:12:52.93/vblo/06,752.99,yes,locked 2006.245.08:12:52.93/vblo/07,734.99,yes,locked 2006.245.08:12:52.93/vblo/08,744.99,yes,locked 2006.245.08:12:53.08/vabw/8 2006.245.08:12:53.23/vbbw/8 2006.245.08:12:53.32/xfe/off,on,13.5 2006.245.08:12:53.70/ifatt/23,28,28,28 2006.245.08:12:54.08/fmout-gps/S +4.39E-07 2006.245.08:12:54.12:!2006.245.08:13:50 2006.245.08:13:50.00:data_valid=off 2006.245.08:13:50.00:postob 2006.245.08:13:50.13/cable/+6.4107E-03 2006.245.08:13:50.13/wx/26.87,1004.5,74 2006.245.08:13:51.07/fmout-gps/S +4.40E-07 2006.245.08:13:51.07:scan_name=245-0814,k06245,60 2006.245.08:13:51.07:source=nrao512,164029.63,394646.0,2000.0,cw 2006.245.08:13:51.13#flagr#flagr/antenna,new-source 2006.245.08:13:52.13:checkk5 2006.245.08:13:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:13:53.00/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:13:53.47/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:13:54.56/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:13:54.99/chk_obsdata//k5ts1/T2450812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:13:55.56/chk_obsdata//k5ts2/T2450812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:13:56.35/chk_obsdata//k5ts3/T2450812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:13:56.77/chk_obsdata//k5ts4/T2450812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:13:57.80/k5log//k5ts1_log_newline 2006.245.08:13:58.58/k5log//k5ts2_log_newline 2006.245.08:13:59.65/k5log//k5ts3_log_newline 2006.245.08:14:00.69/k5log//k5ts4_log_newline 2006.245.08:14:00.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:14:00.72:4f8m12a=2 2006.245.08:14:00.72$4f8m12a/echo=on 2006.245.08:14:00.72$4f8m12a/pcalon 2006.245.08:14:00.72$pcalon/"no phase cal control is implemented here 2006.245.08:14:00.72$4f8m12a/"tpicd=stop 2006.245.08:14:00.72$4f8m12a/vc4f8 2006.245.08:14:00.72$vc4f8/valo=1,532.99 2006.245.08:14:00.73#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.08:14:00.73#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.08:14:00.73#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:00.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:00.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:00.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:00.73#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:14:00.73#ibcon#first serial, iclass 40, count 0 2006.245.08:14:00.73#ibcon#enter sib2, iclass 40, count 0 2006.245.08:14:00.73#ibcon#flushed, iclass 40, count 0 2006.245.08:14:00.73#ibcon#about to write, iclass 40, count 0 2006.245.08:14:00.73#ibcon#wrote, iclass 40, count 0 2006.245.08:14:00.73#ibcon#about to read 3, iclass 40, count 0 2006.245.08:14:00.76#ibcon#read 3, iclass 40, count 0 2006.245.08:14:00.76#ibcon#about to read 4, iclass 40, count 0 2006.245.08:14:00.76#ibcon#read 4, iclass 40, count 0 2006.245.08:14:00.76#ibcon#about to read 5, iclass 40, count 0 2006.245.08:14:00.76#ibcon#read 5, iclass 40, count 0 2006.245.08:14:00.76#ibcon#about to read 6, iclass 40, count 0 2006.245.08:14:00.76#ibcon#read 6, iclass 40, count 0 2006.245.08:14:00.76#ibcon#end of sib2, iclass 40, count 0 2006.245.08:14:00.76#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:14:00.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:14:00.76#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:14:00.76#ibcon#*before write, iclass 40, count 0 2006.245.08:14:00.76#ibcon#enter sib2, iclass 40, count 0 2006.245.08:14:00.76#ibcon#flushed, iclass 40, count 0 2006.245.08:14:00.76#ibcon#about to write, iclass 40, count 0 2006.245.08:14:00.76#ibcon#wrote, iclass 40, count 0 2006.245.08:14:00.76#ibcon#about to read 3, iclass 40, count 0 2006.245.08:14:00.81#ibcon#read 3, iclass 40, count 0 2006.245.08:14:00.81#ibcon#about to read 4, iclass 40, count 0 2006.245.08:14:00.81#ibcon#read 4, iclass 40, count 0 2006.245.08:14:00.81#ibcon#about to read 5, iclass 40, count 0 2006.245.08:14:00.81#ibcon#read 5, iclass 40, count 0 2006.245.08:14:00.81#ibcon#about to read 6, iclass 40, count 0 2006.245.08:14:00.81#ibcon#read 6, iclass 40, count 0 2006.245.08:14:00.81#ibcon#end of sib2, iclass 40, count 0 2006.245.08:14:00.81#ibcon#*after write, iclass 40, count 0 2006.245.08:14:00.81#ibcon#*before return 0, iclass 40, count 0 2006.245.08:14:00.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:00.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:00.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:14:00.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:14:00.81$vc4f8/va=1,8 2006.245.08:14:00.81#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.08:14:00.81#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.08:14:00.81#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:00.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:00.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:00.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:00.81#ibcon#enter wrdev, iclass 4, count 2 2006.245.08:14:00.81#ibcon#first serial, iclass 4, count 2 2006.245.08:14:00.81#ibcon#enter sib2, iclass 4, count 2 2006.245.08:14:00.81#ibcon#flushed, iclass 4, count 2 2006.245.08:14:00.81#ibcon#about to write, iclass 4, count 2 2006.245.08:14:00.81#ibcon#wrote, iclass 4, count 2 2006.245.08:14:00.81#ibcon#about to read 3, iclass 4, count 2 2006.245.08:14:00.83#ibcon#read 3, iclass 4, count 2 2006.245.08:14:00.83#ibcon#about to read 4, iclass 4, count 2 2006.245.08:14:00.83#ibcon#read 4, iclass 4, count 2 2006.245.08:14:00.83#ibcon#about to read 5, iclass 4, count 2 2006.245.08:14:00.83#ibcon#read 5, iclass 4, count 2 2006.245.08:14:00.83#ibcon#about to read 6, iclass 4, count 2 2006.245.08:14:00.83#ibcon#read 6, iclass 4, count 2 2006.245.08:14:00.83#ibcon#end of sib2, iclass 4, count 2 2006.245.08:14:00.83#ibcon#*mode == 0, iclass 4, count 2 2006.245.08:14:00.83#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.08:14:00.83#ibcon#[25=AT01-08\r\n] 2006.245.08:14:00.83#ibcon#*before write, iclass 4, count 2 2006.245.08:14:00.83#ibcon#enter sib2, iclass 4, count 2 2006.245.08:14:00.83#ibcon#flushed, iclass 4, count 2 2006.245.08:14:00.83#ibcon#about to write, iclass 4, count 2 2006.245.08:14:00.83#ibcon#wrote, iclass 4, count 2 2006.245.08:14:00.83#ibcon#about to read 3, iclass 4, count 2 2006.245.08:14:00.86#ibcon#read 3, iclass 4, count 2 2006.245.08:14:00.86#ibcon#about to read 4, iclass 4, count 2 2006.245.08:14:00.86#ibcon#read 4, iclass 4, count 2 2006.245.08:14:00.86#ibcon#about to read 5, iclass 4, count 2 2006.245.08:14:00.86#ibcon#read 5, iclass 4, count 2 2006.245.08:14:00.86#ibcon#about to read 6, iclass 4, count 2 2006.245.08:14:00.86#ibcon#read 6, iclass 4, count 2 2006.245.08:14:00.86#ibcon#end of sib2, iclass 4, count 2 2006.245.08:14:00.86#ibcon#*after write, iclass 4, count 2 2006.245.08:14:00.86#ibcon#*before return 0, iclass 4, count 2 2006.245.08:14:00.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:00.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:00.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.08:14:00.86#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:00.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:00.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:00.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:00.98#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:14:00.98#ibcon#first serial, iclass 4, count 0 2006.245.08:14:00.98#ibcon#enter sib2, iclass 4, count 0 2006.245.08:14:00.98#ibcon#flushed, iclass 4, count 0 2006.245.08:14:00.98#ibcon#about to write, iclass 4, count 0 2006.245.08:14:00.98#ibcon#wrote, iclass 4, count 0 2006.245.08:14:00.98#ibcon#about to read 3, iclass 4, count 0 2006.245.08:14:01.00#ibcon#read 3, iclass 4, count 0 2006.245.08:14:01.00#ibcon#about to read 4, iclass 4, count 0 2006.245.08:14:01.00#ibcon#read 4, iclass 4, count 0 2006.245.08:14:01.00#ibcon#about to read 5, iclass 4, count 0 2006.245.08:14:01.00#ibcon#read 5, iclass 4, count 0 2006.245.08:14:01.00#ibcon#about to read 6, iclass 4, count 0 2006.245.08:14:01.00#ibcon#read 6, iclass 4, count 0 2006.245.08:14:01.00#ibcon#end of sib2, iclass 4, count 0 2006.245.08:14:01.00#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:14:01.00#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:14:01.00#ibcon#[25=USB\r\n] 2006.245.08:14:01.00#ibcon#*before write, iclass 4, count 0 2006.245.08:14:01.00#ibcon#enter sib2, iclass 4, count 0 2006.245.08:14:01.00#ibcon#flushed, iclass 4, count 0 2006.245.08:14:01.00#ibcon#about to write, iclass 4, count 0 2006.245.08:14:01.00#ibcon#wrote, iclass 4, count 0 2006.245.08:14:01.00#ibcon#about to read 3, iclass 4, count 0 2006.245.08:14:01.03#ibcon#read 3, iclass 4, count 0 2006.245.08:14:01.03#ibcon#about to read 4, iclass 4, count 0 2006.245.08:14:01.03#ibcon#read 4, iclass 4, count 0 2006.245.08:14:01.03#ibcon#about to read 5, iclass 4, count 0 2006.245.08:14:01.03#ibcon#read 5, iclass 4, count 0 2006.245.08:14:01.03#ibcon#about to read 6, iclass 4, count 0 2006.245.08:14:01.03#ibcon#read 6, iclass 4, count 0 2006.245.08:14:01.03#ibcon#end of sib2, iclass 4, count 0 2006.245.08:14:01.03#ibcon#*after write, iclass 4, count 0 2006.245.08:14:01.03#ibcon#*before return 0, iclass 4, count 0 2006.245.08:14:01.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:01.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:01.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:14:01.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:14:01.03$vc4f8/valo=2,572.99 2006.245.08:14:01.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.08:14:01.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.08:14:01.03#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:01.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:01.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:01.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:01.03#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:14:01.03#ibcon#first serial, iclass 6, count 0 2006.245.08:14:01.03#ibcon#enter sib2, iclass 6, count 0 2006.245.08:14:01.03#ibcon#flushed, iclass 6, count 0 2006.245.08:14:01.03#ibcon#about to write, iclass 6, count 0 2006.245.08:14:01.03#ibcon#wrote, iclass 6, count 0 2006.245.08:14:01.03#ibcon#about to read 3, iclass 6, count 0 2006.245.08:14:01.06#ibcon#read 3, iclass 6, count 0 2006.245.08:14:01.06#ibcon#about to read 4, iclass 6, count 0 2006.245.08:14:01.06#ibcon#read 4, iclass 6, count 0 2006.245.08:14:01.06#ibcon#about to read 5, iclass 6, count 0 2006.245.08:14:01.06#ibcon#read 5, iclass 6, count 0 2006.245.08:14:01.06#ibcon#about to read 6, iclass 6, count 0 2006.245.08:14:01.06#ibcon#read 6, iclass 6, count 0 2006.245.08:14:01.06#ibcon#end of sib2, iclass 6, count 0 2006.245.08:14:01.06#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:14:01.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:14:01.06#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:14:01.06#ibcon#*before write, iclass 6, count 0 2006.245.08:14:01.06#ibcon#enter sib2, iclass 6, count 0 2006.245.08:14:01.06#ibcon#flushed, iclass 6, count 0 2006.245.08:14:01.06#ibcon#about to write, iclass 6, count 0 2006.245.08:14:01.06#ibcon#wrote, iclass 6, count 0 2006.245.08:14:01.06#ibcon#about to read 3, iclass 6, count 0 2006.245.08:14:01.10#ibcon#read 3, iclass 6, count 0 2006.245.08:14:01.10#ibcon#about to read 4, iclass 6, count 0 2006.245.08:14:01.10#ibcon#read 4, iclass 6, count 0 2006.245.08:14:01.10#ibcon#about to read 5, iclass 6, count 0 2006.245.08:14:01.10#ibcon#read 5, iclass 6, count 0 2006.245.08:14:01.10#ibcon#about to read 6, iclass 6, count 0 2006.245.08:14:01.10#ibcon#read 6, iclass 6, count 0 2006.245.08:14:01.10#ibcon#end of sib2, iclass 6, count 0 2006.245.08:14:01.10#ibcon#*after write, iclass 6, count 0 2006.245.08:14:01.10#ibcon#*before return 0, iclass 6, count 0 2006.245.08:14:01.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:01.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:01.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:14:01.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:14:01.10$vc4f8/va=2,7 2006.245.08:14:01.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.08:14:01.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.08:14:01.10#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:01.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:01.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:01.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:01.15#ibcon#enter wrdev, iclass 10, count 2 2006.245.08:14:01.15#ibcon#first serial, iclass 10, count 2 2006.245.08:14:01.15#ibcon#enter sib2, iclass 10, count 2 2006.245.08:14:01.15#ibcon#flushed, iclass 10, count 2 2006.245.08:14:01.15#ibcon#about to write, iclass 10, count 2 2006.245.08:14:01.15#ibcon#wrote, iclass 10, count 2 2006.245.08:14:01.15#ibcon#about to read 3, iclass 10, count 2 2006.245.08:14:01.17#ibcon#read 3, iclass 10, count 2 2006.245.08:14:01.17#ibcon#about to read 4, iclass 10, count 2 2006.245.08:14:01.17#ibcon#read 4, iclass 10, count 2 2006.245.08:14:01.17#ibcon#about to read 5, iclass 10, count 2 2006.245.08:14:01.17#ibcon#read 5, iclass 10, count 2 2006.245.08:14:01.17#ibcon#about to read 6, iclass 10, count 2 2006.245.08:14:01.17#ibcon#read 6, iclass 10, count 2 2006.245.08:14:01.17#ibcon#end of sib2, iclass 10, count 2 2006.245.08:14:01.17#ibcon#*mode == 0, iclass 10, count 2 2006.245.08:14:01.17#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.08:14:01.17#ibcon#[25=AT02-07\r\n] 2006.245.08:14:01.17#ibcon#*before write, iclass 10, count 2 2006.245.08:14:01.17#ibcon#enter sib2, iclass 10, count 2 2006.245.08:14:01.17#ibcon#flushed, iclass 10, count 2 2006.245.08:14:01.17#ibcon#about to write, iclass 10, count 2 2006.245.08:14:01.17#ibcon#wrote, iclass 10, count 2 2006.245.08:14:01.17#ibcon#about to read 3, iclass 10, count 2 2006.245.08:14:01.20#ibcon#read 3, iclass 10, count 2 2006.245.08:14:01.20#ibcon#about to read 4, iclass 10, count 2 2006.245.08:14:01.20#ibcon#read 4, iclass 10, count 2 2006.245.08:14:01.20#ibcon#about to read 5, iclass 10, count 2 2006.245.08:14:01.20#ibcon#read 5, iclass 10, count 2 2006.245.08:14:01.20#ibcon#about to read 6, iclass 10, count 2 2006.245.08:14:01.20#ibcon#read 6, iclass 10, count 2 2006.245.08:14:01.20#ibcon#end of sib2, iclass 10, count 2 2006.245.08:14:01.20#ibcon#*after write, iclass 10, count 2 2006.245.08:14:01.20#ibcon#*before return 0, iclass 10, count 2 2006.245.08:14:01.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:01.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:01.20#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.08:14:01.20#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:01.20#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:01.32#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:01.32#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:01.32#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:14:01.32#ibcon#first serial, iclass 10, count 0 2006.245.08:14:01.32#ibcon#enter sib2, iclass 10, count 0 2006.245.08:14:01.32#ibcon#flushed, iclass 10, count 0 2006.245.08:14:01.32#ibcon#about to write, iclass 10, count 0 2006.245.08:14:01.32#ibcon#wrote, iclass 10, count 0 2006.245.08:14:01.32#ibcon#about to read 3, iclass 10, count 0 2006.245.08:14:01.34#ibcon#read 3, iclass 10, count 0 2006.245.08:14:01.34#ibcon#about to read 4, iclass 10, count 0 2006.245.08:14:01.34#ibcon#read 4, iclass 10, count 0 2006.245.08:14:01.34#ibcon#about to read 5, iclass 10, count 0 2006.245.08:14:01.34#ibcon#read 5, iclass 10, count 0 2006.245.08:14:01.34#ibcon#about to read 6, iclass 10, count 0 2006.245.08:14:01.34#ibcon#read 6, iclass 10, count 0 2006.245.08:14:01.34#ibcon#end of sib2, iclass 10, count 0 2006.245.08:14:01.34#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:14:01.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:14:01.34#ibcon#[25=USB\r\n] 2006.245.08:14:01.34#ibcon#*before write, iclass 10, count 0 2006.245.08:14:01.34#ibcon#enter sib2, iclass 10, count 0 2006.245.08:14:01.34#ibcon#flushed, iclass 10, count 0 2006.245.08:14:01.34#ibcon#about to write, iclass 10, count 0 2006.245.08:14:01.34#ibcon#wrote, iclass 10, count 0 2006.245.08:14:01.34#ibcon#about to read 3, iclass 10, count 0 2006.245.08:14:01.37#ibcon#read 3, iclass 10, count 0 2006.245.08:14:01.37#ibcon#about to read 4, iclass 10, count 0 2006.245.08:14:01.37#ibcon#read 4, iclass 10, count 0 2006.245.08:14:01.37#ibcon#about to read 5, iclass 10, count 0 2006.245.08:14:01.37#ibcon#read 5, iclass 10, count 0 2006.245.08:14:01.37#ibcon#about to read 6, iclass 10, count 0 2006.245.08:14:01.37#ibcon#read 6, iclass 10, count 0 2006.245.08:14:01.37#ibcon#end of sib2, iclass 10, count 0 2006.245.08:14:01.37#ibcon#*after write, iclass 10, count 0 2006.245.08:14:01.37#ibcon#*before return 0, iclass 10, count 0 2006.245.08:14:01.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:01.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:01.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:14:01.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:14:01.37$vc4f8/valo=3,672.99 2006.245.08:14:01.37#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.08:14:01.37#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.08:14:01.37#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:01.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:01.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:01.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:01.37#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:14:01.37#ibcon#first serial, iclass 12, count 0 2006.245.08:14:01.37#ibcon#enter sib2, iclass 12, count 0 2006.245.08:14:01.37#ibcon#flushed, iclass 12, count 0 2006.245.08:14:01.37#ibcon#about to write, iclass 12, count 0 2006.245.08:14:01.37#ibcon#wrote, iclass 12, count 0 2006.245.08:14:01.37#ibcon#about to read 3, iclass 12, count 0 2006.245.08:14:01.40#ibcon#read 3, iclass 12, count 0 2006.245.08:14:01.40#ibcon#about to read 4, iclass 12, count 0 2006.245.08:14:01.40#ibcon#read 4, iclass 12, count 0 2006.245.08:14:01.40#ibcon#about to read 5, iclass 12, count 0 2006.245.08:14:01.40#ibcon#read 5, iclass 12, count 0 2006.245.08:14:01.40#ibcon#about to read 6, iclass 12, count 0 2006.245.08:14:01.40#ibcon#read 6, iclass 12, count 0 2006.245.08:14:01.40#ibcon#end of sib2, iclass 12, count 0 2006.245.08:14:01.40#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:14:01.40#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:14:01.40#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:14:01.40#ibcon#*before write, iclass 12, count 0 2006.245.08:14:01.40#ibcon#enter sib2, iclass 12, count 0 2006.245.08:14:01.40#ibcon#flushed, iclass 12, count 0 2006.245.08:14:01.40#ibcon#about to write, iclass 12, count 0 2006.245.08:14:01.40#ibcon#wrote, iclass 12, count 0 2006.245.08:14:01.40#ibcon#about to read 3, iclass 12, count 0 2006.245.08:14:01.44#ibcon#read 3, iclass 12, count 0 2006.245.08:14:01.44#ibcon#about to read 4, iclass 12, count 0 2006.245.08:14:01.44#ibcon#read 4, iclass 12, count 0 2006.245.08:14:01.44#ibcon#about to read 5, iclass 12, count 0 2006.245.08:14:01.44#ibcon#read 5, iclass 12, count 0 2006.245.08:14:01.44#ibcon#about to read 6, iclass 12, count 0 2006.245.08:14:01.44#ibcon#read 6, iclass 12, count 0 2006.245.08:14:01.44#ibcon#end of sib2, iclass 12, count 0 2006.245.08:14:01.44#ibcon#*after write, iclass 12, count 0 2006.245.08:14:01.44#ibcon#*before return 0, iclass 12, count 0 2006.245.08:14:01.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:01.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:01.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:14:01.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:14:01.44$vc4f8/va=3,6 2006.245.08:14:01.44#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.08:14:01.44#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.08:14:01.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:01.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:01.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:01.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:01.49#ibcon#enter wrdev, iclass 14, count 2 2006.245.08:14:01.49#ibcon#first serial, iclass 14, count 2 2006.245.08:14:01.49#ibcon#enter sib2, iclass 14, count 2 2006.245.08:14:01.49#ibcon#flushed, iclass 14, count 2 2006.245.08:14:01.49#ibcon#about to write, iclass 14, count 2 2006.245.08:14:01.49#ibcon#wrote, iclass 14, count 2 2006.245.08:14:01.49#ibcon#about to read 3, iclass 14, count 2 2006.245.08:14:01.51#ibcon#read 3, iclass 14, count 2 2006.245.08:14:01.51#ibcon#about to read 4, iclass 14, count 2 2006.245.08:14:01.51#ibcon#read 4, iclass 14, count 2 2006.245.08:14:01.51#ibcon#about to read 5, iclass 14, count 2 2006.245.08:14:01.51#ibcon#read 5, iclass 14, count 2 2006.245.08:14:01.51#ibcon#about to read 6, iclass 14, count 2 2006.245.08:14:01.51#ibcon#read 6, iclass 14, count 2 2006.245.08:14:01.51#ibcon#end of sib2, iclass 14, count 2 2006.245.08:14:01.51#ibcon#*mode == 0, iclass 14, count 2 2006.245.08:14:01.51#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.08:14:01.51#ibcon#[25=AT03-06\r\n] 2006.245.08:14:01.51#ibcon#*before write, iclass 14, count 2 2006.245.08:14:01.51#ibcon#enter sib2, iclass 14, count 2 2006.245.08:14:01.51#ibcon#flushed, iclass 14, count 2 2006.245.08:14:01.51#ibcon#about to write, iclass 14, count 2 2006.245.08:14:01.51#ibcon#wrote, iclass 14, count 2 2006.245.08:14:01.51#ibcon#about to read 3, iclass 14, count 2 2006.245.08:14:01.54#ibcon#read 3, iclass 14, count 2 2006.245.08:14:01.54#ibcon#about to read 4, iclass 14, count 2 2006.245.08:14:01.54#ibcon#read 4, iclass 14, count 2 2006.245.08:14:01.54#ibcon#about to read 5, iclass 14, count 2 2006.245.08:14:01.54#ibcon#read 5, iclass 14, count 2 2006.245.08:14:01.54#ibcon#about to read 6, iclass 14, count 2 2006.245.08:14:01.54#ibcon#read 6, iclass 14, count 2 2006.245.08:14:01.54#ibcon#end of sib2, iclass 14, count 2 2006.245.08:14:01.54#ibcon#*after write, iclass 14, count 2 2006.245.08:14:01.54#ibcon#*before return 0, iclass 14, count 2 2006.245.08:14:01.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:01.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:01.54#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.08:14:01.54#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:01.54#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:01.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:01.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:01.66#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:14:01.66#ibcon#first serial, iclass 14, count 0 2006.245.08:14:01.66#ibcon#enter sib2, iclass 14, count 0 2006.245.08:14:01.66#ibcon#flushed, iclass 14, count 0 2006.245.08:14:01.66#ibcon#about to write, iclass 14, count 0 2006.245.08:14:01.66#ibcon#wrote, iclass 14, count 0 2006.245.08:14:01.66#ibcon#about to read 3, iclass 14, count 0 2006.245.08:14:01.68#ibcon#read 3, iclass 14, count 0 2006.245.08:14:01.68#ibcon#about to read 4, iclass 14, count 0 2006.245.08:14:01.68#ibcon#read 4, iclass 14, count 0 2006.245.08:14:01.68#ibcon#about to read 5, iclass 14, count 0 2006.245.08:14:01.68#ibcon#read 5, iclass 14, count 0 2006.245.08:14:01.68#ibcon#about to read 6, iclass 14, count 0 2006.245.08:14:01.68#ibcon#read 6, iclass 14, count 0 2006.245.08:14:01.68#ibcon#end of sib2, iclass 14, count 0 2006.245.08:14:01.68#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:14:01.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:14:01.68#ibcon#[25=USB\r\n] 2006.245.08:14:01.68#ibcon#*before write, iclass 14, count 0 2006.245.08:14:01.68#ibcon#enter sib2, iclass 14, count 0 2006.245.08:14:01.68#ibcon#flushed, iclass 14, count 0 2006.245.08:14:01.68#ibcon#about to write, iclass 14, count 0 2006.245.08:14:01.68#ibcon#wrote, iclass 14, count 0 2006.245.08:14:01.68#ibcon#about to read 3, iclass 14, count 0 2006.245.08:14:01.71#ibcon#read 3, iclass 14, count 0 2006.245.08:14:01.71#ibcon#about to read 4, iclass 14, count 0 2006.245.08:14:01.71#ibcon#read 4, iclass 14, count 0 2006.245.08:14:01.71#ibcon#about to read 5, iclass 14, count 0 2006.245.08:14:01.71#ibcon#read 5, iclass 14, count 0 2006.245.08:14:01.71#ibcon#about to read 6, iclass 14, count 0 2006.245.08:14:01.71#ibcon#read 6, iclass 14, count 0 2006.245.08:14:01.71#ibcon#end of sib2, iclass 14, count 0 2006.245.08:14:01.71#ibcon#*after write, iclass 14, count 0 2006.245.08:14:01.71#ibcon#*before return 0, iclass 14, count 0 2006.245.08:14:01.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:01.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:01.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:14:01.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:14:01.71$vc4f8/valo=4,832.99 2006.245.08:14:01.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.08:14:01.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.08:14:01.71#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:01.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:01.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:01.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:01.71#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:14:01.71#ibcon#first serial, iclass 16, count 0 2006.245.08:14:01.71#ibcon#enter sib2, iclass 16, count 0 2006.245.08:14:01.71#ibcon#flushed, iclass 16, count 0 2006.245.08:14:01.71#ibcon#about to write, iclass 16, count 0 2006.245.08:14:01.71#ibcon#wrote, iclass 16, count 0 2006.245.08:14:01.71#ibcon#about to read 3, iclass 16, count 0 2006.245.08:14:01.73#ibcon#read 3, iclass 16, count 0 2006.245.08:14:01.73#ibcon#about to read 4, iclass 16, count 0 2006.245.08:14:01.73#ibcon#read 4, iclass 16, count 0 2006.245.08:14:01.73#ibcon#about to read 5, iclass 16, count 0 2006.245.08:14:01.73#ibcon#read 5, iclass 16, count 0 2006.245.08:14:01.73#ibcon#about to read 6, iclass 16, count 0 2006.245.08:14:01.73#ibcon#read 6, iclass 16, count 0 2006.245.08:14:01.73#ibcon#end of sib2, iclass 16, count 0 2006.245.08:14:01.73#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:14:01.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:14:01.73#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:14:01.73#ibcon#*before write, iclass 16, count 0 2006.245.08:14:01.73#ibcon#enter sib2, iclass 16, count 0 2006.245.08:14:01.73#ibcon#flushed, iclass 16, count 0 2006.245.08:14:01.73#ibcon#about to write, iclass 16, count 0 2006.245.08:14:01.73#ibcon#wrote, iclass 16, count 0 2006.245.08:14:01.73#ibcon#about to read 3, iclass 16, count 0 2006.245.08:14:01.77#ibcon#read 3, iclass 16, count 0 2006.245.08:14:01.77#ibcon#about to read 4, iclass 16, count 0 2006.245.08:14:01.77#ibcon#read 4, iclass 16, count 0 2006.245.08:14:01.77#ibcon#about to read 5, iclass 16, count 0 2006.245.08:14:01.77#ibcon#read 5, iclass 16, count 0 2006.245.08:14:01.77#ibcon#about to read 6, iclass 16, count 0 2006.245.08:14:01.77#ibcon#read 6, iclass 16, count 0 2006.245.08:14:01.77#ibcon#end of sib2, iclass 16, count 0 2006.245.08:14:01.77#ibcon#*after write, iclass 16, count 0 2006.245.08:14:01.77#ibcon#*before return 0, iclass 16, count 0 2006.245.08:14:01.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:01.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:01.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:14:01.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:14:01.77$vc4f8/va=4,7 2006.245.08:14:01.77#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.08:14:01.77#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.08:14:01.77#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:01.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:01.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:01.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:01.83#ibcon#enter wrdev, iclass 18, count 2 2006.245.08:14:01.83#ibcon#first serial, iclass 18, count 2 2006.245.08:14:01.83#ibcon#enter sib2, iclass 18, count 2 2006.245.08:14:01.83#ibcon#flushed, iclass 18, count 2 2006.245.08:14:01.83#ibcon#about to write, iclass 18, count 2 2006.245.08:14:01.83#ibcon#wrote, iclass 18, count 2 2006.245.08:14:01.83#ibcon#about to read 3, iclass 18, count 2 2006.245.08:14:01.85#ibcon#read 3, iclass 18, count 2 2006.245.08:14:01.85#ibcon#about to read 4, iclass 18, count 2 2006.245.08:14:01.85#ibcon#read 4, iclass 18, count 2 2006.245.08:14:01.85#ibcon#about to read 5, iclass 18, count 2 2006.245.08:14:01.85#ibcon#read 5, iclass 18, count 2 2006.245.08:14:01.85#ibcon#about to read 6, iclass 18, count 2 2006.245.08:14:01.85#ibcon#read 6, iclass 18, count 2 2006.245.08:14:01.85#ibcon#end of sib2, iclass 18, count 2 2006.245.08:14:01.85#ibcon#*mode == 0, iclass 18, count 2 2006.245.08:14:01.85#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.08:14:01.85#ibcon#[25=AT04-07\r\n] 2006.245.08:14:01.85#ibcon#*before write, iclass 18, count 2 2006.245.08:14:01.85#ibcon#enter sib2, iclass 18, count 2 2006.245.08:14:01.85#ibcon#flushed, iclass 18, count 2 2006.245.08:14:01.85#ibcon#about to write, iclass 18, count 2 2006.245.08:14:01.85#ibcon#wrote, iclass 18, count 2 2006.245.08:14:01.85#ibcon#about to read 3, iclass 18, count 2 2006.245.08:14:01.88#ibcon#read 3, iclass 18, count 2 2006.245.08:14:01.88#ibcon#about to read 4, iclass 18, count 2 2006.245.08:14:01.88#ibcon#read 4, iclass 18, count 2 2006.245.08:14:01.88#ibcon#about to read 5, iclass 18, count 2 2006.245.08:14:01.88#ibcon#read 5, iclass 18, count 2 2006.245.08:14:01.88#ibcon#about to read 6, iclass 18, count 2 2006.245.08:14:01.88#ibcon#read 6, iclass 18, count 2 2006.245.08:14:01.88#ibcon#end of sib2, iclass 18, count 2 2006.245.08:14:01.88#ibcon#*after write, iclass 18, count 2 2006.245.08:14:01.88#ibcon#*before return 0, iclass 18, count 2 2006.245.08:14:01.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:01.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:01.88#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.08:14:01.88#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:01.88#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:02.00#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:02.00#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:02.00#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:14:02.00#ibcon#first serial, iclass 18, count 0 2006.245.08:14:02.00#ibcon#enter sib2, iclass 18, count 0 2006.245.08:14:02.00#ibcon#flushed, iclass 18, count 0 2006.245.08:14:02.00#ibcon#about to write, iclass 18, count 0 2006.245.08:14:02.00#ibcon#wrote, iclass 18, count 0 2006.245.08:14:02.00#ibcon#about to read 3, iclass 18, count 0 2006.245.08:14:02.02#ibcon#read 3, iclass 18, count 0 2006.245.08:14:02.02#ibcon#about to read 4, iclass 18, count 0 2006.245.08:14:02.02#ibcon#read 4, iclass 18, count 0 2006.245.08:14:02.02#ibcon#about to read 5, iclass 18, count 0 2006.245.08:14:02.02#ibcon#read 5, iclass 18, count 0 2006.245.08:14:02.02#ibcon#about to read 6, iclass 18, count 0 2006.245.08:14:02.02#ibcon#read 6, iclass 18, count 0 2006.245.08:14:02.02#ibcon#end of sib2, iclass 18, count 0 2006.245.08:14:02.02#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:14:02.02#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:14:02.02#ibcon#[25=USB\r\n] 2006.245.08:14:02.02#ibcon#*before write, iclass 18, count 0 2006.245.08:14:02.02#ibcon#enter sib2, iclass 18, count 0 2006.245.08:14:02.02#ibcon#flushed, iclass 18, count 0 2006.245.08:14:02.02#ibcon#about to write, iclass 18, count 0 2006.245.08:14:02.02#ibcon#wrote, iclass 18, count 0 2006.245.08:14:02.02#ibcon#about to read 3, iclass 18, count 0 2006.245.08:14:02.05#ibcon#read 3, iclass 18, count 0 2006.245.08:14:02.05#ibcon#about to read 4, iclass 18, count 0 2006.245.08:14:02.05#ibcon#read 4, iclass 18, count 0 2006.245.08:14:02.05#ibcon#about to read 5, iclass 18, count 0 2006.245.08:14:02.05#ibcon#read 5, iclass 18, count 0 2006.245.08:14:02.05#ibcon#about to read 6, iclass 18, count 0 2006.245.08:14:02.05#ibcon#read 6, iclass 18, count 0 2006.245.08:14:02.05#ibcon#end of sib2, iclass 18, count 0 2006.245.08:14:02.05#ibcon#*after write, iclass 18, count 0 2006.245.08:14:02.05#ibcon#*before return 0, iclass 18, count 0 2006.245.08:14:02.05#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:02.05#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:02.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:14:02.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:14:02.05$vc4f8/valo=5,652.99 2006.245.08:14:02.05#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.08:14:02.05#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.08:14:02.05#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:02.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:02.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:02.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:02.05#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:14:02.05#ibcon#first serial, iclass 20, count 0 2006.245.08:14:02.05#ibcon#enter sib2, iclass 20, count 0 2006.245.08:14:02.05#ibcon#flushed, iclass 20, count 0 2006.245.08:14:02.05#ibcon#about to write, iclass 20, count 0 2006.245.08:14:02.05#ibcon#wrote, iclass 20, count 0 2006.245.08:14:02.05#ibcon#about to read 3, iclass 20, count 0 2006.245.08:14:02.07#ibcon#read 3, iclass 20, count 0 2006.245.08:14:02.07#ibcon#about to read 4, iclass 20, count 0 2006.245.08:14:02.07#ibcon#read 4, iclass 20, count 0 2006.245.08:14:02.07#ibcon#about to read 5, iclass 20, count 0 2006.245.08:14:02.07#ibcon#read 5, iclass 20, count 0 2006.245.08:14:02.07#ibcon#about to read 6, iclass 20, count 0 2006.245.08:14:02.07#ibcon#read 6, iclass 20, count 0 2006.245.08:14:02.07#ibcon#end of sib2, iclass 20, count 0 2006.245.08:14:02.07#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:14:02.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:14:02.07#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:14:02.07#ibcon#*before write, iclass 20, count 0 2006.245.08:14:02.07#ibcon#enter sib2, iclass 20, count 0 2006.245.08:14:02.07#ibcon#flushed, iclass 20, count 0 2006.245.08:14:02.07#ibcon#about to write, iclass 20, count 0 2006.245.08:14:02.07#ibcon#wrote, iclass 20, count 0 2006.245.08:14:02.07#ibcon#about to read 3, iclass 20, count 0 2006.245.08:14:02.11#ibcon#read 3, iclass 20, count 0 2006.245.08:14:02.11#ibcon#about to read 4, iclass 20, count 0 2006.245.08:14:02.11#ibcon#read 4, iclass 20, count 0 2006.245.08:14:02.11#ibcon#about to read 5, iclass 20, count 0 2006.245.08:14:02.11#ibcon#read 5, iclass 20, count 0 2006.245.08:14:02.11#ibcon#about to read 6, iclass 20, count 0 2006.245.08:14:02.11#ibcon#read 6, iclass 20, count 0 2006.245.08:14:02.11#ibcon#end of sib2, iclass 20, count 0 2006.245.08:14:02.11#ibcon#*after write, iclass 20, count 0 2006.245.08:14:02.11#ibcon#*before return 0, iclass 20, count 0 2006.245.08:14:02.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:02.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:02.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:14:02.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:14:02.11$vc4f8/va=5,7 2006.245.08:14:02.11#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.08:14:02.11#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.08:14:02.11#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:02.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:02.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:02.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:02.17#ibcon#enter wrdev, iclass 22, count 2 2006.245.08:14:02.17#ibcon#first serial, iclass 22, count 2 2006.245.08:14:02.17#ibcon#enter sib2, iclass 22, count 2 2006.245.08:14:02.17#ibcon#flushed, iclass 22, count 2 2006.245.08:14:02.17#ibcon#about to write, iclass 22, count 2 2006.245.08:14:02.17#ibcon#wrote, iclass 22, count 2 2006.245.08:14:02.17#ibcon#about to read 3, iclass 22, count 2 2006.245.08:14:02.19#ibcon#read 3, iclass 22, count 2 2006.245.08:14:02.19#ibcon#about to read 4, iclass 22, count 2 2006.245.08:14:02.19#ibcon#read 4, iclass 22, count 2 2006.245.08:14:02.19#ibcon#about to read 5, iclass 22, count 2 2006.245.08:14:02.19#ibcon#read 5, iclass 22, count 2 2006.245.08:14:02.19#ibcon#about to read 6, iclass 22, count 2 2006.245.08:14:02.19#ibcon#read 6, iclass 22, count 2 2006.245.08:14:02.19#ibcon#end of sib2, iclass 22, count 2 2006.245.08:14:02.19#ibcon#*mode == 0, iclass 22, count 2 2006.245.08:14:02.19#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.08:14:02.19#ibcon#[25=AT05-07\r\n] 2006.245.08:14:02.19#ibcon#*before write, iclass 22, count 2 2006.245.08:14:02.19#ibcon#enter sib2, iclass 22, count 2 2006.245.08:14:02.19#ibcon#flushed, iclass 22, count 2 2006.245.08:14:02.19#ibcon#about to write, iclass 22, count 2 2006.245.08:14:02.19#ibcon#wrote, iclass 22, count 2 2006.245.08:14:02.19#ibcon#about to read 3, iclass 22, count 2 2006.245.08:14:02.22#ibcon#read 3, iclass 22, count 2 2006.245.08:14:02.22#ibcon#about to read 4, iclass 22, count 2 2006.245.08:14:02.22#ibcon#read 4, iclass 22, count 2 2006.245.08:14:02.22#ibcon#about to read 5, iclass 22, count 2 2006.245.08:14:02.22#ibcon#read 5, iclass 22, count 2 2006.245.08:14:02.22#ibcon#about to read 6, iclass 22, count 2 2006.245.08:14:02.22#ibcon#read 6, iclass 22, count 2 2006.245.08:14:02.22#ibcon#end of sib2, iclass 22, count 2 2006.245.08:14:02.22#ibcon#*after write, iclass 22, count 2 2006.245.08:14:02.22#ibcon#*before return 0, iclass 22, count 2 2006.245.08:14:02.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:02.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:02.22#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.08:14:02.22#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:02.22#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:02.34#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:02.34#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:02.34#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:14:02.34#ibcon#first serial, iclass 22, count 0 2006.245.08:14:02.34#ibcon#enter sib2, iclass 22, count 0 2006.245.08:14:02.34#ibcon#flushed, iclass 22, count 0 2006.245.08:14:02.34#ibcon#about to write, iclass 22, count 0 2006.245.08:14:02.34#ibcon#wrote, iclass 22, count 0 2006.245.08:14:02.34#ibcon#about to read 3, iclass 22, count 0 2006.245.08:14:02.36#ibcon#read 3, iclass 22, count 0 2006.245.08:14:02.36#ibcon#about to read 4, iclass 22, count 0 2006.245.08:14:02.36#ibcon#read 4, iclass 22, count 0 2006.245.08:14:02.36#ibcon#about to read 5, iclass 22, count 0 2006.245.08:14:02.36#ibcon#read 5, iclass 22, count 0 2006.245.08:14:02.36#ibcon#about to read 6, iclass 22, count 0 2006.245.08:14:02.36#ibcon#read 6, iclass 22, count 0 2006.245.08:14:02.36#ibcon#end of sib2, iclass 22, count 0 2006.245.08:14:02.36#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:14:02.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:14:02.36#ibcon#[25=USB\r\n] 2006.245.08:14:02.36#ibcon#*before write, iclass 22, count 0 2006.245.08:14:02.36#ibcon#enter sib2, iclass 22, count 0 2006.245.08:14:02.36#ibcon#flushed, iclass 22, count 0 2006.245.08:14:02.36#ibcon#about to write, iclass 22, count 0 2006.245.08:14:02.36#ibcon#wrote, iclass 22, count 0 2006.245.08:14:02.36#ibcon#about to read 3, iclass 22, count 0 2006.245.08:14:02.39#ibcon#read 3, iclass 22, count 0 2006.245.08:14:02.39#ibcon#about to read 4, iclass 22, count 0 2006.245.08:14:02.39#ibcon#read 4, iclass 22, count 0 2006.245.08:14:02.39#ibcon#about to read 5, iclass 22, count 0 2006.245.08:14:02.39#ibcon#read 5, iclass 22, count 0 2006.245.08:14:02.39#ibcon#about to read 6, iclass 22, count 0 2006.245.08:14:02.39#ibcon#read 6, iclass 22, count 0 2006.245.08:14:02.39#ibcon#end of sib2, iclass 22, count 0 2006.245.08:14:02.39#ibcon#*after write, iclass 22, count 0 2006.245.08:14:02.39#ibcon#*before return 0, iclass 22, count 0 2006.245.08:14:02.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:02.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:02.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:14:02.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:14:02.39$vc4f8/valo=6,772.99 2006.245.08:14:02.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:14:02.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:14:02.39#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:02.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:02.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:02.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:02.39#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:14:02.39#ibcon#first serial, iclass 24, count 0 2006.245.08:14:02.39#ibcon#enter sib2, iclass 24, count 0 2006.245.08:14:02.39#ibcon#flushed, iclass 24, count 0 2006.245.08:14:02.39#ibcon#about to write, iclass 24, count 0 2006.245.08:14:02.39#ibcon#wrote, iclass 24, count 0 2006.245.08:14:02.39#ibcon#about to read 3, iclass 24, count 0 2006.245.08:14:02.42#ibcon#read 3, iclass 24, count 0 2006.245.08:14:02.42#ibcon#about to read 4, iclass 24, count 0 2006.245.08:14:02.42#ibcon#read 4, iclass 24, count 0 2006.245.08:14:02.42#ibcon#about to read 5, iclass 24, count 0 2006.245.08:14:02.42#ibcon#read 5, iclass 24, count 0 2006.245.08:14:02.42#ibcon#about to read 6, iclass 24, count 0 2006.245.08:14:02.42#ibcon#read 6, iclass 24, count 0 2006.245.08:14:02.42#ibcon#end of sib2, iclass 24, count 0 2006.245.08:14:02.42#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:14:02.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:14:02.42#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:14:02.42#ibcon#*before write, iclass 24, count 0 2006.245.08:14:02.42#ibcon#enter sib2, iclass 24, count 0 2006.245.08:14:02.42#ibcon#flushed, iclass 24, count 0 2006.245.08:14:02.42#ibcon#about to write, iclass 24, count 0 2006.245.08:14:02.42#ibcon#wrote, iclass 24, count 0 2006.245.08:14:02.42#ibcon#about to read 3, iclass 24, count 0 2006.245.08:14:02.46#ibcon#read 3, iclass 24, count 0 2006.245.08:14:02.46#ibcon#about to read 4, iclass 24, count 0 2006.245.08:14:02.46#ibcon#read 4, iclass 24, count 0 2006.245.08:14:02.46#ibcon#about to read 5, iclass 24, count 0 2006.245.08:14:02.46#ibcon#read 5, iclass 24, count 0 2006.245.08:14:02.46#ibcon#about to read 6, iclass 24, count 0 2006.245.08:14:02.46#ibcon#read 6, iclass 24, count 0 2006.245.08:14:02.46#ibcon#end of sib2, iclass 24, count 0 2006.245.08:14:02.46#ibcon#*after write, iclass 24, count 0 2006.245.08:14:02.46#ibcon#*before return 0, iclass 24, count 0 2006.245.08:14:02.46#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:02.46#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:02.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:14:02.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:14:02.46$vc4f8/va=6,7 2006.245.08:14:02.46#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.08:14:02.46#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.08:14:02.46#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:02.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:14:02.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:14:02.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:14:02.51#ibcon#enter wrdev, iclass 26, count 2 2006.245.08:14:02.51#ibcon#first serial, iclass 26, count 2 2006.245.08:14:02.51#ibcon#enter sib2, iclass 26, count 2 2006.245.08:14:02.51#ibcon#flushed, iclass 26, count 2 2006.245.08:14:02.51#ibcon#about to write, iclass 26, count 2 2006.245.08:14:02.51#ibcon#wrote, iclass 26, count 2 2006.245.08:14:02.51#ibcon#about to read 3, iclass 26, count 2 2006.245.08:14:02.53#ibcon#read 3, iclass 26, count 2 2006.245.08:14:02.53#ibcon#about to read 4, iclass 26, count 2 2006.245.08:14:02.53#ibcon#read 4, iclass 26, count 2 2006.245.08:14:02.53#ibcon#about to read 5, iclass 26, count 2 2006.245.08:14:02.53#ibcon#read 5, iclass 26, count 2 2006.245.08:14:02.53#ibcon#about to read 6, iclass 26, count 2 2006.245.08:14:02.53#ibcon#read 6, iclass 26, count 2 2006.245.08:14:02.53#ibcon#end of sib2, iclass 26, count 2 2006.245.08:14:02.53#ibcon#*mode == 0, iclass 26, count 2 2006.245.08:14:02.53#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.08:14:02.53#ibcon#[25=AT06-07\r\n] 2006.245.08:14:02.53#ibcon#*before write, iclass 26, count 2 2006.245.08:14:02.53#ibcon#enter sib2, iclass 26, count 2 2006.245.08:14:02.53#ibcon#flushed, iclass 26, count 2 2006.245.08:14:02.53#ibcon#about to write, iclass 26, count 2 2006.245.08:14:02.53#ibcon#wrote, iclass 26, count 2 2006.245.08:14:02.53#ibcon#about to read 3, iclass 26, count 2 2006.245.08:14:02.56#ibcon#read 3, iclass 26, count 2 2006.245.08:14:02.56#ibcon#about to read 4, iclass 26, count 2 2006.245.08:14:02.56#ibcon#read 4, iclass 26, count 2 2006.245.08:14:02.56#ibcon#about to read 5, iclass 26, count 2 2006.245.08:14:02.56#ibcon#read 5, iclass 26, count 2 2006.245.08:14:02.56#ibcon#about to read 6, iclass 26, count 2 2006.245.08:14:02.56#ibcon#read 6, iclass 26, count 2 2006.245.08:14:02.56#ibcon#end of sib2, iclass 26, count 2 2006.245.08:14:02.56#ibcon#*after write, iclass 26, count 2 2006.245.08:14:02.56#ibcon#*before return 0, iclass 26, count 2 2006.245.08:14:02.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:14:02.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:14:02.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.08:14:02.56#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:02.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:14:02.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:14:02.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:14:02.68#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:14:02.68#ibcon#first serial, iclass 26, count 0 2006.245.08:14:02.68#ibcon#enter sib2, iclass 26, count 0 2006.245.08:14:02.68#ibcon#flushed, iclass 26, count 0 2006.245.08:14:02.68#ibcon#about to write, iclass 26, count 0 2006.245.08:14:02.68#ibcon#wrote, iclass 26, count 0 2006.245.08:14:02.68#ibcon#about to read 3, iclass 26, count 0 2006.245.08:14:02.70#ibcon#read 3, iclass 26, count 0 2006.245.08:14:02.70#ibcon#about to read 4, iclass 26, count 0 2006.245.08:14:02.70#ibcon#read 4, iclass 26, count 0 2006.245.08:14:02.70#ibcon#about to read 5, iclass 26, count 0 2006.245.08:14:02.70#ibcon#read 5, iclass 26, count 0 2006.245.08:14:02.70#ibcon#about to read 6, iclass 26, count 0 2006.245.08:14:02.70#ibcon#read 6, iclass 26, count 0 2006.245.08:14:02.70#ibcon#end of sib2, iclass 26, count 0 2006.245.08:14:02.70#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:14:02.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:14:02.70#ibcon#[25=USB\r\n] 2006.245.08:14:02.70#ibcon#*before write, iclass 26, count 0 2006.245.08:14:02.70#ibcon#enter sib2, iclass 26, count 0 2006.245.08:14:02.70#ibcon#flushed, iclass 26, count 0 2006.245.08:14:02.70#ibcon#about to write, iclass 26, count 0 2006.245.08:14:02.70#ibcon#wrote, iclass 26, count 0 2006.245.08:14:02.70#ibcon#about to read 3, iclass 26, count 0 2006.245.08:14:02.73#ibcon#read 3, iclass 26, count 0 2006.245.08:14:02.73#ibcon#about to read 4, iclass 26, count 0 2006.245.08:14:02.73#ibcon#read 4, iclass 26, count 0 2006.245.08:14:02.73#ibcon#about to read 5, iclass 26, count 0 2006.245.08:14:02.73#ibcon#read 5, iclass 26, count 0 2006.245.08:14:02.73#ibcon#about to read 6, iclass 26, count 0 2006.245.08:14:02.73#ibcon#read 6, iclass 26, count 0 2006.245.08:14:02.73#ibcon#end of sib2, iclass 26, count 0 2006.245.08:14:02.73#ibcon#*after write, iclass 26, count 0 2006.245.08:14:02.73#ibcon#*before return 0, iclass 26, count 0 2006.245.08:14:02.73#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:14:02.73#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:14:02.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:14:02.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:14:02.73$vc4f8/valo=7,832.99 2006.245.08:14:02.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.08:14:02.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.08:14:02.73#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:02.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:14:02.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:14:02.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:14:02.73#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:14:02.73#ibcon#first serial, iclass 28, count 0 2006.245.08:14:02.73#ibcon#enter sib2, iclass 28, count 0 2006.245.08:14:02.73#ibcon#flushed, iclass 28, count 0 2006.245.08:14:02.73#ibcon#about to write, iclass 28, count 0 2006.245.08:14:02.73#ibcon#wrote, iclass 28, count 0 2006.245.08:14:02.73#ibcon#about to read 3, iclass 28, count 0 2006.245.08:14:02.75#ibcon#read 3, iclass 28, count 0 2006.245.08:14:02.75#ibcon#about to read 4, iclass 28, count 0 2006.245.08:14:02.75#ibcon#read 4, iclass 28, count 0 2006.245.08:14:02.75#ibcon#about to read 5, iclass 28, count 0 2006.245.08:14:02.75#ibcon#read 5, iclass 28, count 0 2006.245.08:14:02.75#ibcon#about to read 6, iclass 28, count 0 2006.245.08:14:02.75#ibcon#read 6, iclass 28, count 0 2006.245.08:14:02.75#ibcon#end of sib2, iclass 28, count 0 2006.245.08:14:02.75#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:14:02.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:14:02.75#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:14:02.75#ibcon#*before write, iclass 28, count 0 2006.245.08:14:02.75#ibcon#enter sib2, iclass 28, count 0 2006.245.08:14:02.75#ibcon#flushed, iclass 28, count 0 2006.245.08:14:02.75#ibcon#about to write, iclass 28, count 0 2006.245.08:14:02.75#ibcon#wrote, iclass 28, count 0 2006.245.08:14:02.75#ibcon#about to read 3, iclass 28, count 0 2006.245.08:14:02.79#ibcon#read 3, iclass 28, count 0 2006.245.08:14:02.79#ibcon#about to read 4, iclass 28, count 0 2006.245.08:14:02.79#ibcon#read 4, iclass 28, count 0 2006.245.08:14:02.79#ibcon#about to read 5, iclass 28, count 0 2006.245.08:14:02.79#ibcon#read 5, iclass 28, count 0 2006.245.08:14:02.79#ibcon#about to read 6, iclass 28, count 0 2006.245.08:14:02.79#ibcon#read 6, iclass 28, count 0 2006.245.08:14:02.79#ibcon#end of sib2, iclass 28, count 0 2006.245.08:14:02.79#ibcon#*after write, iclass 28, count 0 2006.245.08:14:02.79#ibcon#*before return 0, iclass 28, count 0 2006.245.08:14:02.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:14:02.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:14:02.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:14:02.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:14:02.79$vc4f8/va=7,7 2006.245.08:14:02.79#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.08:14:02.79#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.08:14:02.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:02.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:14:02.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:14:02.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:14:02.85#ibcon#enter wrdev, iclass 30, count 2 2006.245.08:14:02.85#ibcon#first serial, iclass 30, count 2 2006.245.08:14:02.85#ibcon#enter sib2, iclass 30, count 2 2006.245.08:14:02.85#ibcon#flushed, iclass 30, count 2 2006.245.08:14:02.85#ibcon#about to write, iclass 30, count 2 2006.245.08:14:02.85#ibcon#wrote, iclass 30, count 2 2006.245.08:14:02.85#ibcon#about to read 3, iclass 30, count 2 2006.245.08:14:02.87#ibcon#read 3, iclass 30, count 2 2006.245.08:14:02.87#ibcon#about to read 4, iclass 30, count 2 2006.245.08:14:02.87#ibcon#read 4, iclass 30, count 2 2006.245.08:14:02.87#ibcon#about to read 5, iclass 30, count 2 2006.245.08:14:02.87#ibcon#read 5, iclass 30, count 2 2006.245.08:14:02.87#ibcon#about to read 6, iclass 30, count 2 2006.245.08:14:02.87#ibcon#read 6, iclass 30, count 2 2006.245.08:14:02.87#ibcon#end of sib2, iclass 30, count 2 2006.245.08:14:02.87#ibcon#*mode == 0, iclass 30, count 2 2006.245.08:14:02.87#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.08:14:02.87#ibcon#[25=AT07-07\r\n] 2006.245.08:14:02.87#ibcon#*before write, iclass 30, count 2 2006.245.08:14:02.87#ibcon#enter sib2, iclass 30, count 2 2006.245.08:14:02.87#ibcon#flushed, iclass 30, count 2 2006.245.08:14:02.87#ibcon#about to write, iclass 30, count 2 2006.245.08:14:02.87#ibcon#wrote, iclass 30, count 2 2006.245.08:14:02.87#ibcon#about to read 3, iclass 30, count 2 2006.245.08:14:02.90#ibcon#read 3, iclass 30, count 2 2006.245.08:14:02.90#ibcon#about to read 4, iclass 30, count 2 2006.245.08:14:02.90#ibcon#read 4, iclass 30, count 2 2006.245.08:14:02.90#ibcon#about to read 5, iclass 30, count 2 2006.245.08:14:02.90#ibcon#read 5, iclass 30, count 2 2006.245.08:14:02.90#ibcon#about to read 6, iclass 30, count 2 2006.245.08:14:02.90#ibcon#read 6, iclass 30, count 2 2006.245.08:14:02.90#ibcon#end of sib2, iclass 30, count 2 2006.245.08:14:02.90#ibcon#*after write, iclass 30, count 2 2006.245.08:14:02.90#ibcon#*before return 0, iclass 30, count 2 2006.245.08:14:02.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:14:02.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:14:02.90#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.08:14:02.90#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:02.90#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:14:03.02#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:14:03.02#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:14:03.02#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:14:03.02#ibcon#first serial, iclass 30, count 0 2006.245.08:14:03.02#ibcon#enter sib2, iclass 30, count 0 2006.245.08:14:03.02#ibcon#flushed, iclass 30, count 0 2006.245.08:14:03.02#ibcon#about to write, iclass 30, count 0 2006.245.08:14:03.02#ibcon#wrote, iclass 30, count 0 2006.245.08:14:03.02#ibcon#about to read 3, iclass 30, count 0 2006.245.08:14:03.04#ibcon#read 3, iclass 30, count 0 2006.245.08:14:03.04#ibcon#about to read 4, iclass 30, count 0 2006.245.08:14:03.04#ibcon#read 4, iclass 30, count 0 2006.245.08:14:03.04#ibcon#about to read 5, iclass 30, count 0 2006.245.08:14:03.04#ibcon#read 5, iclass 30, count 0 2006.245.08:14:03.04#ibcon#about to read 6, iclass 30, count 0 2006.245.08:14:03.04#ibcon#read 6, iclass 30, count 0 2006.245.08:14:03.04#ibcon#end of sib2, iclass 30, count 0 2006.245.08:14:03.04#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:14:03.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:14:03.04#ibcon#[25=USB\r\n] 2006.245.08:14:03.04#ibcon#*before write, iclass 30, count 0 2006.245.08:14:03.04#ibcon#enter sib2, iclass 30, count 0 2006.245.08:14:03.04#ibcon#flushed, iclass 30, count 0 2006.245.08:14:03.04#ibcon#about to write, iclass 30, count 0 2006.245.08:14:03.04#ibcon#wrote, iclass 30, count 0 2006.245.08:14:03.04#ibcon#about to read 3, iclass 30, count 0 2006.245.08:14:03.08#ibcon#read 3, iclass 30, count 0 2006.245.08:14:03.08#ibcon#about to read 4, iclass 30, count 0 2006.245.08:14:03.08#ibcon#read 4, iclass 30, count 0 2006.245.08:14:03.08#ibcon#about to read 5, iclass 30, count 0 2006.245.08:14:03.08#ibcon#read 5, iclass 30, count 0 2006.245.08:14:03.08#ibcon#about to read 6, iclass 30, count 0 2006.245.08:14:03.08#ibcon#read 6, iclass 30, count 0 2006.245.08:14:03.08#ibcon#end of sib2, iclass 30, count 0 2006.245.08:14:03.08#ibcon#*after write, iclass 30, count 0 2006.245.08:14:03.08#ibcon#*before return 0, iclass 30, count 0 2006.245.08:14:03.08#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:14:03.08#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:14:03.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:14:03.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:14:03.08$vc4f8/valo=8,852.99 2006.245.08:14:03.08#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.08:14:03.08#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.08:14:03.08#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:03.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:14:03.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:14:03.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:14:03.08#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:14:03.08#ibcon#first serial, iclass 32, count 0 2006.245.08:14:03.08#ibcon#enter sib2, iclass 32, count 0 2006.245.08:14:03.08#ibcon#flushed, iclass 32, count 0 2006.245.08:14:03.08#ibcon#about to write, iclass 32, count 0 2006.245.08:14:03.08#ibcon#wrote, iclass 32, count 0 2006.245.08:14:03.08#ibcon#about to read 3, iclass 32, count 0 2006.245.08:14:03.09#ibcon#read 3, iclass 32, count 0 2006.245.08:14:03.09#ibcon#about to read 4, iclass 32, count 0 2006.245.08:14:03.09#ibcon#read 4, iclass 32, count 0 2006.245.08:14:03.09#ibcon#about to read 5, iclass 32, count 0 2006.245.08:14:03.09#ibcon#read 5, iclass 32, count 0 2006.245.08:14:03.09#ibcon#about to read 6, iclass 32, count 0 2006.245.08:14:03.09#ibcon#read 6, iclass 32, count 0 2006.245.08:14:03.09#ibcon#end of sib2, iclass 32, count 0 2006.245.08:14:03.09#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:14:03.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:14:03.09#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:14:03.09#ibcon#*before write, iclass 32, count 0 2006.245.08:14:03.09#ibcon#enter sib2, iclass 32, count 0 2006.245.08:14:03.09#ibcon#flushed, iclass 32, count 0 2006.245.08:14:03.09#ibcon#about to write, iclass 32, count 0 2006.245.08:14:03.09#ibcon#wrote, iclass 32, count 0 2006.245.08:14:03.09#ibcon#about to read 3, iclass 32, count 0 2006.245.08:14:03.13#ibcon#read 3, iclass 32, count 0 2006.245.08:14:03.13#ibcon#about to read 4, iclass 32, count 0 2006.245.08:14:03.13#ibcon#read 4, iclass 32, count 0 2006.245.08:14:03.13#ibcon#about to read 5, iclass 32, count 0 2006.245.08:14:03.13#ibcon#read 5, iclass 32, count 0 2006.245.08:14:03.13#ibcon#about to read 6, iclass 32, count 0 2006.245.08:14:03.13#ibcon#read 6, iclass 32, count 0 2006.245.08:14:03.13#ibcon#end of sib2, iclass 32, count 0 2006.245.08:14:03.13#ibcon#*after write, iclass 32, count 0 2006.245.08:14:03.13#ibcon#*before return 0, iclass 32, count 0 2006.245.08:14:03.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:14:03.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:14:03.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:14:03.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:14:03.13$vc4f8/va=8,8 2006.245.08:14:03.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.08:14:03.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.08:14:03.13#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:03.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:14:03.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:14:03.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:14:03.20#ibcon#enter wrdev, iclass 34, count 2 2006.245.08:14:03.20#ibcon#first serial, iclass 34, count 2 2006.245.08:14:03.20#ibcon#enter sib2, iclass 34, count 2 2006.245.08:14:03.20#ibcon#flushed, iclass 34, count 2 2006.245.08:14:03.20#ibcon#about to write, iclass 34, count 2 2006.245.08:14:03.20#ibcon#wrote, iclass 34, count 2 2006.245.08:14:03.20#ibcon#about to read 3, iclass 34, count 2 2006.245.08:14:03.22#ibcon#read 3, iclass 34, count 2 2006.245.08:14:03.22#ibcon#about to read 4, iclass 34, count 2 2006.245.08:14:03.22#ibcon#read 4, iclass 34, count 2 2006.245.08:14:03.22#ibcon#about to read 5, iclass 34, count 2 2006.245.08:14:03.22#ibcon#read 5, iclass 34, count 2 2006.245.08:14:03.22#ibcon#about to read 6, iclass 34, count 2 2006.245.08:14:03.22#ibcon#read 6, iclass 34, count 2 2006.245.08:14:03.22#ibcon#end of sib2, iclass 34, count 2 2006.245.08:14:03.22#ibcon#*mode == 0, iclass 34, count 2 2006.245.08:14:03.22#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.08:14:03.22#ibcon#[25=AT08-08\r\n] 2006.245.08:14:03.22#ibcon#*before write, iclass 34, count 2 2006.245.08:14:03.22#ibcon#enter sib2, iclass 34, count 2 2006.245.08:14:03.22#ibcon#flushed, iclass 34, count 2 2006.245.08:14:03.22#ibcon#about to write, iclass 34, count 2 2006.245.08:14:03.22#ibcon#wrote, iclass 34, count 2 2006.245.08:14:03.22#ibcon#about to read 3, iclass 34, count 2 2006.245.08:14:03.25#ibcon#read 3, iclass 34, count 2 2006.245.08:14:03.25#ibcon#about to read 4, iclass 34, count 2 2006.245.08:14:03.25#ibcon#read 4, iclass 34, count 2 2006.245.08:14:03.25#ibcon#about to read 5, iclass 34, count 2 2006.245.08:14:03.25#ibcon#read 5, iclass 34, count 2 2006.245.08:14:03.25#ibcon#about to read 6, iclass 34, count 2 2006.245.08:14:03.25#ibcon#read 6, iclass 34, count 2 2006.245.08:14:03.25#ibcon#end of sib2, iclass 34, count 2 2006.245.08:14:03.25#ibcon#*after write, iclass 34, count 2 2006.245.08:14:03.25#ibcon#*before return 0, iclass 34, count 2 2006.245.08:14:03.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:14:03.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:14:03.25#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.08:14:03.25#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:03.25#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:14:03.37#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:14:03.37#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:14:03.37#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:14:03.37#ibcon#first serial, iclass 34, count 0 2006.245.08:14:03.37#ibcon#enter sib2, iclass 34, count 0 2006.245.08:14:03.37#ibcon#flushed, iclass 34, count 0 2006.245.08:14:03.37#ibcon#about to write, iclass 34, count 0 2006.245.08:14:03.37#ibcon#wrote, iclass 34, count 0 2006.245.08:14:03.37#ibcon#about to read 3, iclass 34, count 0 2006.245.08:14:03.39#ibcon#read 3, iclass 34, count 0 2006.245.08:14:03.39#ibcon#about to read 4, iclass 34, count 0 2006.245.08:14:03.39#ibcon#read 4, iclass 34, count 0 2006.245.08:14:03.39#ibcon#about to read 5, iclass 34, count 0 2006.245.08:14:03.39#ibcon#read 5, iclass 34, count 0 2006.245.08:14:03.39#ibcon#about to read 6, iclass 34, count 0 2006.245.08:14:03.39#ibcon#read 6, iclass 34, count 0 2006.245.08:14:03.39#ibcon#end of sib2, iclass 34, count 0 2006.245.08:14:03.39#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:14:03.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:14:03.39#ibcon#[25=USB\r\n] 2006.245.08:14:03.39#ibcon#*before write, iclass 34, count 0 2006.245.08:14:03.39#ibcon#enter sib2, iclass 34, count 0 2006.245.08:14:03.39#ibcon#flushed, iclass 34, count 0 2006.245.08:14:03.39#ibcon#about to write, iclass 34, count 0 2006.245.08:14:03.39#ibcon#wrote, iclass 34, count 0 2006.245.08:14:03.39#ibcon#about to read 3, iclass 34, count 0 2006.245.08:14:03.42#ibcon#read 3, iclass 34, count 0 2006.245.08:14:03.42#ibcon#about to read 4, iclass 34, count 0 2006.245.08:14:03.42#ibcon#read 4, iclass 34, count 0 2006.245.08:14:03.42#ibcon#about to read 5, iclass 34, count 0 2006.245.08:14:03.42#ibcon#read 5, iclass 34, count 0 2006.245.08:14:03.42#ibcon#about to read 6, iclass 34, count 0 2006.245.08:14:03.42#ibcon#read 6, iclass 34, count 0 2006.245.08:14:03.42#ibcon#end of sib2, iclass 34, count 0 2006.245.08:14:03.42#ibcon#*after write, iclass 34, count 0 2006.245.08:14:03.42#ibcon#*before return 0, iclass 34, count 0 2006.245.08:14:03.42#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:14:03.42#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:14:03.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:14:03.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:14:03.42$vc4f8/vblo=1,632.99 2006.245.08:14:03.42#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.08:14:03.42#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.08:14:03.42#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:03.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:14:03.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:14:03.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:14:03.42#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:14:03.42#ibcon#first serial, iclass 36, count 0 2006.245.08:14:03.42#ibcon#enter sib2, iclass 36, count 0 2006.245.08:14:03.42#ibcon#flushed, iclass 36, count 0 2006.245.08:14:03.42#ibcon#about to write, iclass 36, count 0 2006.245.08:14:03.42#ibcon#wrote, iclass 36, count 0 2006.245.08:14:03.42#ibcon#about to read 3, iclass 36, count 0 2006.245.08:14:03.44#ibcon#read 3, iclass 36, count 0 2006.245.08:14:03.44#ibcon#about to read 4, iclass 36, count 0 2006.245.08:14:03.44#ibcon#read 4, iclass 36, count 0 2006.245.08:14:03.44#ibcon#about to read 5, iclass 36, count 0 2006.245.08:14:03.44#ibcon#read 5, iclass 36, count 0 2006.245.08:14:03.44#ibcon#about to read 6, iclass 36, count 0 2006.245.08:14:03.44#ibcon#read 6, iclass 36, count 0 2006.245.08:14:03.44#ibcon#end of sib2, iclass 36, count 0 2006.245.08:14:03.44#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:14:03.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:14:03.44#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:14:03.44#ibcon#*before write, iclass 36, count 0 2006.245.08:14:03.44#ibcon#enter sib2, iclass 36, count 0 2006.245.08:14:03.44#ibcon#flushed, iclass 36, count 0 2006.245.08:14:03.44#ibcon#about to write, iclass 36, count 0 2006.245.08:14:03.44#ibcon#wrote, iclass 36, count 0 2006.245.08:14:03.44#ibcon#about to read 3, iclass 36, count 0 2006.245.08:14:03.48#ibcon#read 3, iclass 36, count 0 2006.245.08:14:03.48#ibcon#about to read 4, iclass 36, count 0 2006.245.08:14:03.48#ibcon#read 4, iclass 36, count 0 2006.245.08:14:03.48#ibcon#about to read 5, iclass 36, count 0 2006.245.08:14:03.48#ibcon#read 5, iclass 36, count 0 2006.245.08:14:03.48#ibcon#about to read 6, iclass 36, count 0 2006.245.08:14:03.48#ibcon#read 6, iclass 36, count 0 2006.245.08:14:03.48#ibcon#end of sib2, iclass 36, count 0 2006.245.08:14:03.48#ibcon#*after write, iclass 36, count 0 2006.245.08:14:03.48#ibcon#*before return 0, iclass 36, count 0 2006.245.08:14:03.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:14:03.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:14:03.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:14:03.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:14:03.48$vc4f8/vb=1,4 2006.245.08:14:03.48#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.08:14:03.48#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.08:14:03.48#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:03.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:14:03.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:14:03.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:14:03.48#ibcon#enter wrdev, iclass 38, count 2 2006.245.08:14:03.48#ibcon#first serial, iclass 38, count 2 2006.245.08:14:03.48#ibcon#enter sib2, iclass 38, count 2 2006.245.08:14:03.48#ibcon#flushed, iclass 38, count 2 2006.245.08:14:03.48#ibcon#about to write, iclass 38, count 2 2006.245.08:14:03.48#ibcon#wrote, iclass 38, count 2 2006.245.08:14:03.48#ibcon#about to read 3, iclass 38, count 2 2006.245.08:14:03.50#ibcon#read 3, iclass 38, count 2 2006.245.08:14:03.50#ibcon#about to read 4, iclass 38, count 2 2006.245.08:14:03.50#ibcon#read 4, iclass 38, count 2 2006.245.08:14:03.50#ibcon#about to read 5, iclass 38, count 2 2006.245.08:14:03.50#ibcon#read 5, iclass 38, count 2 2006.245.08:14:03.50#ibcon#about to read 6, iclass 38, count 2 2006.245.08:14:03.50#ibcon#read 6, iclass 38, count 2 2006.245.08:14:03.50#ibcon#end of sib2, iclass 38, count 2 2006.245.08:14:03.50#ibcon#*mode == 0, iclass 38, count 2 2006.245.08:14:03.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.08:14:03.50#ibcon#[27=AT01-04\r\n] 2006.245.08:14:03.50#ibcon#*before write, iclass 38, count 2 2006.245.08:14:03.50#ibcon#enter sib2, iclass 38, count 2 2006.245.08:14:03.50#ibcon#flushed, iclass 38, count 2 2006.245.08:14:03.50#ibcon#about to write, iclass 38, count 2 2006.245.08:14:03.50#ibcon#wrote, iclass 38, count 2 2006.245.08:14:03.50#ibcon#about to read 3, iclass 38, count 2 2006.245.08:14:03.53#ibcon#read 3, iclass 38, count 2 2006.245.08:14:03.53#ibcon#about to read 4, iclass 38, count 2 2006.245.08:14:03.53#ibcon#read 4, iclass 38, count 2 2006.245.08:14:03.53#ibcon#about to read 5, iclass 38, count 2 2006.245.08:14:03.53#ibcon#read 5, iclass 38, count 2 2006.245.08:14:03.53#ibcon#about to read 6, iclass 38, count 2 2006.245.08:14:03.53#ibcon#read 6, iclass 38, count 2 2006.245.08:14:03.53#ibcon#end of sib2, iclass 38, count 2 2006.245.08:14:03.53#ibcon#*after write, iclass 38, count 2 2006.245.08:14:03.53#ibcon#*before return 0, iclass 38, count 2 2006.245.08:14:03.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:14:03.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:14:03.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.08:14:03.53#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:03.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:14:03.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:14:03.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:14:03.65#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:14:03.65#ibcon#first serial, iclass 38, count 0 2006.245.08:14:03.65#ibcon#enter sib2, iclass 38, count 0 2006.245.08:14:03.65#ibcon#flushed, iclass 38, count 0 2006.245.08:14:03.65#ibcon#about to write, iclass 38, count 0 2006.245.08:14:03.65#ibcon#wrote, iclass 38, count 0 2006.245.08:14:03.65#ibcon#about to read 3, iclass 38, count 0 2006.245.08:14:03.67#ibcon#read 3, iclass 38, count 0 2006.245.08:14:03.67#ibcon#about to read 4, iclass 38, count 0 2006.245.08:14:03.67#ibcon#read 4, iclass 38, count 0 2006.245.08:14:03.67#ibcon#about to read 5, iclass 38, count 0 2006.245.08:14:03.67#ibcon#read 5, iclass 38, count 0 2006.245.08:14:03.67#ibcon#about to read 6, iclass 38, count 0 2006.245.08:14:03.67#ibcon#read 6, iclass 38, count 0 2006.245.08:14:03.67#ibcon#end of sib2, iclass 38, count 0 2006.245.08:14:03.67#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:14:03.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:14:03.67#ibcon#[27=USB\r\n] 2006.245.08:14:03.67#ibcon#*before write, iclass 38, count 0 2006.245.08:14:03.67#ibcon#enter sib2, iclass 38, count 0 2006.245.08:14:03.67#ibcon#flushed, iclass 38, count 0 2006.245.08:14:03.67#ibcon#about to write, iclass 38, count 0 2006.245.08:14:03.67#ibcon#wrote, iclass 38, count 0 2006.245.08:14:03.67#ibcon#about to read 3, iclass 38, count 0 2006.245.08:14:03.70#ibcon#read 3, iclass 38, count 0 2006.245.08:14:03.70#ibcon#about to read 4, iclass 38, count 0 2006.245.08:14:03.70#ibcon#read 4, iclass 38, count 0 2006.245.08:14:03.70#ibcon#about to read 5, iclass 38, count 0 2006.245.08:14:03.70#ibcon#read 5, iclass 38, count 0 2006.245.08:14:03.70#ibcon#about to read 6, iclass 38, count 0 2006.245.08:14:03.70#ibcon#read 6, iclass 38, count 0 2006.245.08:14:03.70#ibcon#end of sib2, iclass 38, count 0 2006.245.08:14:03.70#ibcon#*after write, iclass 38, count 0 2006.245.08:14:03.70#ibcon#*before return 0, iclass 38, count 0 2006.245.08:14:03.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:14:03.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:14:03.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:14:03.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:14:03.70$vc4f8/vblo=2,640.99 2006.245.08:14:03.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.08:14:03.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.08:14:03.70#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:03.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:03.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:03.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:03.70#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:14:03.70#ibcon#first serial, iclass 40, count 0 2006.245.08:14:03.70#ibcon#enter sib2, iclass 40, count 0 2006.245.08:14:03.70#ibcon#flushed, iclass 40, count 0 2006.245.08:14:03.70#ibcon#about to write, iclass 40, count 0 2006.245.08:14:03.70#ibcon#wrote, iclass 40, count 0 2006.245.08:14:03.70#ibcon#about to read 3, iclass 40, count 0 2006.245.08:14:03.72#ibcon#read 3, iclass 40, count 0 2006.245.08:14:03.72#ibcon#about to read 4, iclass 40, count 0 2006.245.08:14:03.72#ibcon#read 4, iclass 40, count 0 2006.245.08:14:03.72#ibcon#about to read 5, iclass 40, count 0 2006.245.08:14:03.72#ibcon#read 5, iclass 40, count 0 2006.245.08:14:03.72#ibcon#about to read 6, iclass 40, count 0 2006.245.08:14:03.72#ibcon#read 6, iclass 40, count 0 2006.245.08:14:03.72#ibcon#end of sib2, iclass 40, count 0 2006.245.08:14:03.72#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:14:03.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:14:03.72#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:14:03.72#ibcon#*before write, iclass 40, count 0 2006.245.08:14:03.72#ibcon#enter sib2, iclass 40, count 0 2006.245.08:14:03.72#ibcon#flushed, iclass 40, count 0 2006.245.08:14:03.72#ibcon#about to write, iclass 40, count 0 2006.245.08:14:03.72#ibcon#wrote, iclass 40, count 0 2006.245.08:14:03.72#ibcon#about to read 3, iclass 40, count 0 2006.245.08:14:03.76#ibcon#read 3, iclass 40, count 0 2006.245.08:14:03.76#ibcon#about to read 4, iclass 40, count 0 2006.245.08:14:03.76#ibcon#read 4, iclass 40, count 0 2006.245.08:14:03.76#ibcon#about to read 5, iclass 40, count 0 2006.245.08:14:03.76#ibcon#read 5, iclass 40, count 0 2006.245.08:14:03.76#ibcon#about to read 6, iclass 40, count 0 2006.245.08:14:03.76#ibcon#read 6, iclass 40, count 0 2006.245.08:14:03.76#ibcon#end of sib2, iclass 40, count 0 2006.245.08:14:03.76#ibcon#*after write, iclass 40, count 0 2006.245.08:14:03.76#ibcon#*before return 0, iclass 40, count 0 2006.245.08:14:03.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:03.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:14:03.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:14:03.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:14:03.76$vc4f8/vb=2,4 2006.245.08:14:03.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.08:14:03.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.08:14:03.76#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:03.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:03.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:03.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:03.82#ibcon#enter wrdev, iclass 4, count 2 2006.245.08:14:03.82#ibcon#first serial, iclass 4, count 2 2006.245.08:14:03.82#ibcon#enter sib2, iclass 4, count 2 2006.245.08:14:03.82#ibcon#flushed, iclass 4, count 2 2006.245.08:14:03.82#ibcon#about to write, iclass 4, count 2 2006.245.08:14:03.82#ibcon#wrote, iclass 4, count 2 2006.245.08:14:03.82#ibcon#about to read 3, iclass 4, count 2 2006.245.08:14:03.84#ibcon#read 3, iclass 4, count 2 2006.245.08:14:03.84#ibcon#about to read 4, iclass 4, count 2 2006.245.08:14:03.84#ibcon#read 4, iclass 4, count 2 2006.245.08:14:03.84#ibcon#about to read 5, iclass 4, count 2 2006.245.08:14:03.84#ibcon#read 5, iclass 4, count 2 2006.245.08:14:03.84#ibcon#about to read 6, iclass 4, count 2 2006.245.08:14:03.84#ibcon#read 6, iclass 4, count 2 2006.245.08:14:03.84#ibcon#end of sib2, iclass 4, count 2 2006.245.08:14:03.84#ibcon#*mode == 0, iclass 4, count 2 2006.245.08:14:03.84#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.08:14:03.84#ibcon#[27=AT02-04\r\n] 2006.245.08:14:03.84#ibcon#*before write, iclass 4, count 2 2006.245.08:14:03.84#ibcon#enter sib2, iclass 4, count 2 2006.245.08:14:03.84#ibcon#flushed, iclass 4, count 2 2006.245.08:14:03.84#ibcon#about to write, iclass 4, count 2 2006.245.08:14:03.84#ibcon#wrote, iclass 4, count 2 2006.245.08:14:03.84#ibcon#about to read 3, iclass 4, count 2 2006.245.08:14:03.87#ibcon#read 3, iclass 4, count 2 2006.245.08:14:03.87#ibcon#about to read 4, iclass 4, count 2 2006.245.08:14:03.87#ibcon#read 4, iclass 4, count 2 2006.245.08:14:03.87#ibcon#about to read 5, iclass 4, count 2 2006.245.08:14:03.87#ibcon#read 5, iclass 4, count 2 2006.245.08:14:03.87#ibcon#about to read 6, iclass 4, count 2 2006.245.08:14:03.87#ibcon#read 6, iclass 4, count 2 2006.245.08:14:03.87#ibcon#end of sib2, iclass 4, count 2 2006.245.08:14:03.87#ibcon#*after write, iclass 4, count 2 2006.245.08:14:03.87#ibcon#*before return 0, iclass 4, count 2 2006.245.08:14:03.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:03.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:14:03.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.08:14:03.87#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:03.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:03.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:03.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:03.99#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:14:03.99#ibcon#first serial, iclass 4, count 0 2006.245.08:14:03.99#ibcon#enter sib2, iclass 4, count 0 2006.245.08:14:03.99#ibcon#flushed, iclass 4, count 0 2006.245.08:14:03.99#ibcon#about to write, iclass 4, count 0 2006.245.08:14:03.99#ibcon#wrote, iclass 4, count 0 2006.245.08:14:03.99#ibcon#about to read 3, iclass 4, count 0 2006.245.08:14:04.01#ibcon#read 3, iclass 4, count 0 2006.245.08:14:04.01#ibcon#about to read 4, iclass 4, count 0 2006.245.08:14:04.01#ibcon#read 4, iclass 4, count 0 2006.245.08:14:04.01#ibcon#about to read 5, iclass 4, count 0 2006.245.08:14:04.01#ibcon#read 5, iclass 4, count 0 2006.245.08:14:04.01#ibcon#about to read 6, iclass 4, count 0 2006.245.08:14:04.01#ibcon#read 6, iclass 4, count 0 2006.245.08:14:04.01#ibcon#end of sib2, iclass 4, count 0 2006.245.08:14:04.01#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:14:04.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:14:04.01#ibcon#[27=USB\r\n] 2006.245.08:14:04.01#ibcon#*before write, iclass 4, count 0 2006.245.08:14:04.01#ibcon#enter sib2, iclass 4, count 0 2006.245.08:14:04.01#ibcon#flushed, iclass 4, count 0 2006.245.08:14:04.01#ibcon#about to write, iclass 4, count 0 2006.245.08:14:04.01#ibcon#wrote, iclass 4, count 0 2006.245.08:14:04.01#ibcon#about to read 3, iclass 4, count 0 2006.245.08:14:04.04#ibcon#read 3, iclass 4, count 0 2006.245.08:14:04.04#ibcon#about to read 4, iclass 4, count 0 2006.245.08:14:04.04#ibcon#read 4, iclass 4, count 0 2006.245.08:14:04.04#ibcon#about to read 5, iclass 4, count 0 2006.245.08:14:04.04#ibcon#read 5, iclass 4, count 0 2006.245.08:14:04.04#ibcon#about to read 6, iclass 4, count 0 2006.245.08:14:04.04#ibcon#read 6, iclass 4, count 0 2006.245.08:14:04.04#ibcon#end of sib2, iclass 4, count 0 2006.245.08:14:04.04#ibcon#*after write, iclass 4, count 0 2006.245.08:14:04.04#ibcon#*before return 0, iclass 4, count 0 2006.245.08:14:04.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:04.04#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:14:04.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:14:04.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:14:04.04$vc4f8/vblo=3,656.99 2006.245.08:14:04.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.08:14:04.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.08:14:04.04#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:04.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:04.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:04.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:04.04#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:14:04.04#ibcon#first serial, iclass 6, count 0 2006.245.08:14:04.04#ibcon#enter sib2, iclass 6, count 0 2006.245.08:14:04.04#ibcon#flushed, iclass 6, count 0 2006.245.08:14:04.04#ibcon#about to write, iclass 6, count 0 2006.245.08:14:04.04#ibcon#wrote, iclass 6, count 0 2006.245.08:14:04.04#ibcon#about to read 3, iclass 6, count 0 2006.245.08:14:04.06#ibcon#read 3, iclass 6, count 0 2006.245.08:14:04.06#ibcon#about to read 4, iclass 6, count 0 2006.245.08:14:04.06#ibcon#read 4, iclass 6, count 0 2006.245.08:14:04.06#ibcon#about to read 5, iclass 6, count 0 2006.245.08:14:04.06#ibcon#read 5, iclass 6, count 0 2006.245.08:14:04.06#ibcon#about to read 6, iclass 6, count 0 2006.245.08:14:04.06#ibcon#read 6, iclass 6, count 0 2006.245.08:14:04.06#ibcon#end of sib2, iclass 6, count 0 2006.245.08:14:04.06#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:14:04.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:14:04.06#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:14:04.06#ibcon#*before write, iclass 6, count 0 2006.245.08:14:04.06#ibcon#enter sib2, iclass 6, count 0 2006.245.08:14:04.06#ibcon#flushed, iclass 6, count 0 2006.245.08:14:04.06#ibcon#about to write, iclass 6, count 0 2006.245.08:14:04.06#ibcon#wrote, iclass 6, count 0 2006.245.08:14:04.06#ibcon#about to read 3, iclass 6, count 0 2006.245.08:14:04.10#ibcon#read 3, iclass 6, count 0 2006.245.08:14:04.10#ibcon#about to read 4, iclass 6, count 0 2006.245.08:14:04.10#ibcon#read 4, iclass 6, count 0 2006.245.08:14:04.10#ibcon#about to read 5, iclass 6, count 0 2006.245.08:14:04.10#ibcon#read 5, iclass 6, count 0 2006.245.08:14:04.10#ibcon#about to read 6, iclass 6, count 0 2006.245.08:14:04.10#ibcon#read 6, iclass 6, count 0 2006.245.08:14:04.10#ibcon#end of sib2, iclass 6, count 0 2006.245.08:14:04.10#ibcon#*after write, iclass 6, count 0 2006.245.08:14:04.10#ibcon#*before return 0, iclass 6, count 0 2006.245.08:14:04.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:04.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:14:04.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:14:04.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:14:04.10$vc4f8/vb=3,4 2006.245.08:14:04.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.08:14:04.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.08:14:04.10#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:04.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:04.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:04.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:04.16#ibcon#enter wrdev, iclass 10, count 2 2006.245.08:14:04.16#ibcon#first serial, iclass 10, count 2 2006.245.08:14:04.16#ibcon#enter sib2, iclass 10, count 2 2006.245.08:14:04.16#ibcon#flushed, iclass 10, count 2 2006.245.08:14:04.16#ibcon#about to write, iclass 10, count 2 2006.245.08:14:04.16#ibcon#wrote, iclass 10, count 2 2006.245.08:14:04.16#ibcon#about to read 3, iclass 10, count 2 2006.245.08:14:04.18#ibcon#read 3, iclass 10, count 2 2006.245.08:14:04.18#ibcon#about to read 4, iclass 10, count 2 2006.245.08:14:04.18#ibcon#read 4, iclass 10, count 2 2006.245.08:14:04.18#ibcon#about to read 5, iclass 10, count 2 2006.245.08:14:04.18#ibcon#read 5, iclass 10, count 2 2006.245.08:14:04.18#ibcon#about to read 6, iclass 10, count 2 2006.245.08:14:04.18#ibcon#read 6, iclass 10, count 2 2006.245.08:14:04.18#ibcon#end of sib2, iclass 10, count 2 2006.245.08:14:04.18#ibcon#*mode == 0, iclass 10, count 2 2006.245.08:14:04.18#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.08:14:04.18#ibcon#[27=AT03-04\r\n] 2006.245.08:14:04.18#ibcon#*before write, iclass 10, count 2 2006.245.08:14:04.18#ibcon#enter sib2, iclass 10, count 2 2006.245.08:14:04.18#ibcon#flushed, iclass 10, count 2 2006.245.08:14:04.18#ibcon#about to write, iclass 10, count 2 2006.245.08:14:04.18#ibcon#wrote, iclass 10, count 2 2006.245.08:14:04.18#ibcon#about to read 3, iclass 10, count 2 2006.245.08:14:04.21#ibcon#read 3, iclass 10, count 2 2006.245.08:14:04.21#ibcon#about to read 4, iclass 10, count 2 2006.245.08:14:04.21#ibcon#read 4, iclass 10, count 2 2006.245.08:14:04.21#ibcon#about to read 5, iclass 10, count 2 2006.245.08:14:04.21#ibcon#read 5, iclass 10, count 2 2006.245.08:14:04.21#ibcon#about to read 6, iclass 10, count 2 2006.245.08:14:04.21#ibcon#read 6, iclass 10, count 2 2006.245.08:14:04.21#ibcon#end of sib2, iclass 10, count 2 2006.245.08:14:04.21#ibcon#*after write, iclass 10, count 2 2006.245.08:14:04.21#ibcon#*before return 0, iclass 10, count 2 2006.245.08:14:04.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:04.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:14:04.21#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.08:14:04.21#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:04.21#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:04.33#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:04.33#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:04.33#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:14:04.33#ibcon#first serial, iclass 10, count 0 2006.245.08:14:04.33#ibcon#enter sib2, iclass 10, count 0 2006.245.08:14:04.33#ibcon#flushed, iclass 10, count 0 2006.245.08:14:04.33#ibcon#about to write, iclass 10, count 0 2006.245.08:14:04.33#ibcon#wrote, iclass 10, count 0 2006.245.08:14:04.33#ibcon#about to read 3, iclass 10, count 0 2006.245.08:14:04.35#ibcon#read 3, iclass 10, count 0 2006.245.08:14:04.35#ibcon#about to read 4, iclass 10, count 0 2006.245.08:14:04.35#ibcon#read 4, iclass 10, count 0 2006.245.08:14:04.35#ibcon#about to read 5, iclass 10, count 0 2006.245.08:14:04.35#ibcon#read 5, iclass 10, count 0 2006.245.08:14:04.35#ibcon#about to read 6, iclass 10, count 0 2006.245.08:14:04.35#ibcon#read 6, iclass 10, count 0 2006.245.08:14:04.35#ibcon#end of sib2, iclass 10, count 0 2006.245.08:14:04.35#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:14:04.35#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:14:04.35#ibcon#[27=USB\r\n] 2006.245.08:14:04.35#ibcon#*before write, iclass 10, count 0 2006.245.08:14:04.35#ibcon#enter sib2, iclass 10, count 0 2006.245.08:14:04.35#ibcon#flushed, iclass 10, count 0 2006.245.08:14:04.35#ibcon#about to write, iclass 10, count 0 2006.245.08:14:04.35#ibcon#wrote, iclass 10, count 0 2006.245.08:14:04.35#ibcon#about to read 3, iclass 10, count 0 2006.245.08:14:04.38#ibcon#read 3, iclass 10, count 0 2006.245.08:14:04.38#ibcon#about to read 4, iclass 10, count 0 2006.245.08:14:04.38#ibcon#read 4, iclass 10, count 0 2006.245.08:14:04.38#ibcon#about to read 5, iclass 10, count 0 2006.245.08:14:04.38#ibcon#read 5, iclass 10, count 0 2006.245.08:14:04.38#ibcon#about to read 6, iclass 10, count 0 2006.245.08:14:04.38#ibcon#read 6, iclass 10, count 0 2006.245.08:14:04.38#ibcon#end of sib2, iclass 10, count 0 2006.245.08:14:04.38#ibcon#*after write, iclass 10, count 0 2006.245.08:14:04.38#ibcon#*before return 0, iclass 10, count 0 2006.245.08:14:04.38#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:04.38#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:14:04.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:14:04.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:14:04.38$vc4f8/vblo=4,712.99 2006.245.08:14:04.38#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.08:14:04.38#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.08:14:04.38#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:04.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:04.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:04.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:04.38#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:14:04.38#ibcon#first serial, iclass 12, count 0 2006.245.08:14:04.38#ibcon#enter sib2, iclass 12, count 0 2006.245.08:14:04.38#ibcon#flushed, iclass 12, count 0 2006.245.08:14:04.38#ibcon#about to write, iclass 12, count 0 2006.245.08:14:04.38#ibcon#wrote, iclass 12, count 0 2006.245.08:14:04.38#ibcon#about to read 3, iclass 12, count 0 2006.245.08:14:04.40#ibcon#read 3, iclass 12, count 0 2006.245.08:14:04.40#ibcon#about to read 4, iclass 12, count 0 2006.245.08:14:04.40#ibcon#read 4, iclass 12, count 0 2006.245.08:14:04.40#ibcon#about to read 5, iclass 12, count 0 2006.245.08:14:04.40#ibcon#read 5, iclass 12, count 0 2006.245.08:14:04.40#ibcon#about to read 6, iclass 12, count 0 2006.245.08:14:04.40#ibcon#read 6, iclass 12, count 0 2006.245.08:14:04.40#ibcon#end of sib2, iclass 12, count 0 2006.245.08:14:04.40#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:14:04.40#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:14:04.40#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:14:04.40#ibcon#*before write, iclass 12, count 0 2006.245.08:14:04.40#ibcon#enter sib2, iclass 12, count 0 2006.245.08:14:04.40#ibcon#flushed, iclass 12, count 0 2006.245.08:14:04.40#ibcon#about to write, iclass 12, count 0 2006.245.08:14:04.40#ibcon#wrote, iclass 12, count 0 2006.245.08:14:04.40#ibcon#about to read 3, iclass 12, count 0 2006.245.08:14:04.44#ibcon#read 3, iclass 12, count 0 2006.245.08:14:04.44#ibcon#about to read 4, iclass 12, count 0 2006.245.08:14:04.44#ibcon#read 4, iclass 12, count 0 2006.245.08:14:04.44#ibcon#about to read 5, iclass 12, count 0 2006.245.08:14:04.44#ibcon#read 5, iclass 12, count 0 2006.245.08:14:04.44#ibcon#about to read 6, iclass 12, count 0 2006.245.08:14:04.44#ibcon#read 6, iclass 12, count 0 2006.245.08:14:04.44#ibcon#end of sib2, iclass 12, count 0 2006.245.08:14:04.44#ibcon#*after write, iclass 12, count 0 2006.245.08:14:04.44#ibcon#*before return 0, iclass 12, count 0 2006.245.08:14:04.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:04.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:14:04.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:14:04.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:14:04.44$vc4f8/vb=4,4 2006.245.08:14:04.44#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.08:14:04.44#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.08:14:04.44#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:04.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:04.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:04.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:04.50#ibcon#enter wrdev, iclass 14, count 2 2006.245.08:14:04.50#ibcon#first serial, iclass 14, count 2 2006.245.08:14:04.50#ibcon#enter sib2, iclass 14, count 2 2006.245.08:14:04.50#ibcon#flushed, iclass 14, count 2 2006.245.08:14:04.50#ibcon#about to write, iclass 14, count 2 2006.245.08:14:04.50#ibcon#wrote, iclass 14, count 2 2006.245.08:14:04.50#ibcon#about to read 3, iclass 14, count 2 2006.245.08:14:04.52#ibcon#read 3, iclass 14, count 2 2006.245.08:14:04.52#ibcon#about to read 4, iclass 14, count 2 2006.245.08:14:04.52#ibcon#read 4, iclass 14, count 2 2006.245.08:14:04.52#ibcon#about to read 5, iclass 14, count 2 2006.245.08:14:04.52#ibcon#read 5, iclass 14, count 2 2006.245.08:14:04.52#ibcon#about to read 6, iclass 14, count 2 2006.245.08:14:04.52#ibcon#read 6, iclass 14, count 2 2006.245.08:14:04.52#ibcon#end of sib2, iclass 14, count 2 2006.245.08:14:04.52#ibcon#*mode == 0, iclass 14, count 2 2006.245.08:14:04.52#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.08:14:04.52#ibcon#[27=AT04-04\r\n] 2006.245.08:14:04.52#ibcon#*before write, iclass 14, count 2 2006.245.08:14:04.52#ibcon#enter sib2, iclass 14, count 2 2006.245.08:14:04.52#ibcon#flushed, iclass 14, count 2 2006.245.08:14:04.52#ibcon#about to write, iclass 14, count 2 2006.245.08:14:04.52#ibcon#wrote, iclass 14, count 2 2006.245.08:14:04.52#ibcon#about to read 3, iclass 14, count 2 2006.245.08:14:04.55#ibcon#read 3, iclass 14, count 2 2006.245.08:14:04.55#ibcon#about to read 4, iclass 14, count 2 2006.245.08:14:04.55#ibcon#read 4, iclass 14, count 2 2006.245.08:14:04.55#ibcon#about to read 5, iclass 14, count 2 2006.245.08:14:04.55#ibcon#read 5, iclass 14, count 2 2006.245.08:14:04.55#ibcon#about to read 6, iclass 14, count 2 2006.245.08:14:04.55#ibcon#read 6, iclass 14, count 2 2006.245.08:14:04.55#ibcon#end of sib2, iclass 14, count 2 2006.245.08:14:04.55#ibcon#*after write, iclass 14, count 2 2006.245.08:14:04.55#ibcon#*before return 0, iclass 14, count 2 2006.245.08:14:04.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:04.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:14:04.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.08:14:04.55#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:04.55#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:04.67#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:04.67#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:04.67#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:14:04.67#ibcon#first serial, iclass 14, count 0 2006.245.08:14:04.67#ibcon#enter sib2, iclass 14, count 0 2006.245.08:14:04.67#ibcon#flushed, iclass 14, count 0 2006.245.08:14:04.67#ibcon#about to write, iclass 14, count 0 2006.245.08:14:04.67#ibcon#wrote, iclass 14, count 0 2006.245.08:14:04.67#ibcon#about to read 3, iclass 14, count 0 2006.245.08:14:04.69#ibcon#read 3, iclass 14, count 0 2006.245.08:14:04.69#ibcon#about to read 4, iclass 14, count 0 2006.245.08:14:04.69#ibcon#read 4, iclass 14, count 0 2006.245.08:14:04.69#ibcon#about to read 5, iclass 14, count 0 2006.245.08:14:04.69#ibcon#read 5, iclass 14, count 0 2006.245.08:14:04.69#ibcon#about to read 6, iclass 14, count 0 2006.245.08:14:04.69#ibcon#read 6, iclass 14, count 0 2006.245.08:14:04.69#ibcon#end of sib2, iclass 14, count 0 2006.245.08:14:04.69#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:14:04.69#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:14:04.69#ibcon#[27=USB\r\n] 2006.245.08:14:04.69#ibcon#*before write, iclass 14, count 0 2006.245.08:14:04.69#ibcon#enter sib2, iclass 14, count 0 2006.245.08:14:04.69#ibcon#flushed, iclass 14, count 0 2006.245.08:14:04.69#ibcon#about to write, iclass 14, count 0 2006.245.08:14:04.69#ibcon#wrote, iclass 14, count 0 2006.245.08:14:04.69#ibcon#about to read 3, iclass 14, count 0 2006.245.08:14:04.72#ibcon#read 3, iclass 14, count 0 2006.245.08:14:04.72#ibcon#about to read 4, iclass 14, count 0 2006.245.08:14:04.72#ibcon#read 4, iclass 14, count 0 2006.245.08:14:04.72#ibcon#about to read 5, iclass 14, count 0 2006.245.08:14:04.72#ibcon#read 5, iclass 14, count 0 2006.245.08:14:04.72#ibcon#about to read 6, iclass 14, count 0 2006.245.08:14:04.72#ibcon#read 6, iclass 14, count 0 2006.245.08:14:04.72#ibcon#end of sib2, iclass 14, count 0 2006.245.08:14:04.72#ibcon#*after write, iclass 14, count 0 2006.245.08:14:04.72#ibcon#*before return 0, iclass 14, count 0 2006.245.08:14:04.72#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:04.72#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:14:04.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:14:04.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:14:04.72$vc4f8/vblo=5,744.99 2006.245.08:14:04.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.08:14:04.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.08:14:04.72#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:04.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:04.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:04.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:04.72#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:14:04.72#ibcon#first serial, iclass 16, count 0 2006.245.08:14:04.72#ibcon#enter sib2, iclass 16, count 0 2006.245.08:14:04.72#ibcon#flushed, iclass 16, count 0 2006.245.08:14:04.72#ibcon#about to write, iclass 16, count 0 2006.245.08:14:04.72#ibcon#wrote, iclass 16, count 0 2006.245.08:14:04.72#ibcon#about to read 3, iclass 16, count 0 2006.245.08:14:04.75#ibcon#read 3, iclass 16, count 0 2006.245.08:14:04.75#ibcon#about to read 4, iclass 16, count 0 2006.245.08:14:04.75#ibcon#read 4, iclass 16, count 0 2006.245.08:14:04.75#ibcon#about to read 5, iclass 16, count 0 2006.245.08:14:04.75#ibcon#read 5, iclass 16, count 0 2006.245.08:14:04.75#ibcon#about to read 6, iclass 16, count 0 2006.245.08:14:04.75#ibcon#read 6, iclass 16, count 0 2006.245.08:14:04.75#ibcon#end of sib2, iclass 16, count 0 2006.245.08:14:04.75#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:14:04.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:14:04.75#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:14:04.75#ibcon#*before write, iclass 16, count 0 2006.245.08:14:04.75#ibcon#enter sib2, iclass 16, count 0 2006.245.08:14:04.75#ibcon#flushed, iclass 16, count 0 2006.245.08:14:04.75#ibcon#about to write, iclass 16, count 0 2006.245.08:14:04.75#ibcon#wrote, iclass 16, count 0 2006.245.08:14:04.75#ibcon#about to read 3, iclass 16, count 0 2006.245.08:14:04.79#ibcon#read 3, iclass 16, count 0 2006.245.08:14:04.79#ibcon#about to read 4, iclass 16, count 0 2006.245.08:14:04.79#ibcon#read 4, iclass 16, count 0 2006.245.08:14:04.79#ibcon#about to read 5, iclass 16, count 0 2006.245.08:14:04.79#ibcon#read 5, iclass 16, count 0 2006.245.08:14:04.79#ibcon#about to read 6, iclass 16, count 0 2006.245.08:14:04.79#ibcon#read 6, iclass 16, count 0 2006.245.08:14:04.79#ibcon#end of sib2, iclass 16, count 0 2006.245.08:14:04.79#ibcon#*after write, iclass 16, count 0 2006.245.08:14:04.79#ibcon#*before return 0, iclass 16, count 0 2006.245.08:14:04.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:04.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:14:04.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:14:04.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:14:04.79$vc4f8/vb=5,3 2006.245.08:14:04.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.08:14:04.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.08:14:04.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:04.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:04.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:04.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:04.84#ibcon#enter wrdev, iclass 18, count 2 2006.245.08:14:04.84#ibcon#first serial, iclass 18, count 2 2006.245.08:14:04.84#ibcon#enter sib2, iclass 18, count 2 2006.245.08:14:04.84#ibcon#flushed, iclass 18, count 2 2006.245.08:14:04.84#ibcon#about to write, iclass 18, count 2 2006.245.08:14:04.84#ibcon#wrote, iclass 18, count 2 2006.245.08:14:04.84#ibcon#about to read 3, iclass 18, count 2 2006.245.08:14:04.86#ibcon#read 3, iclass 18, count 2 2006.245.08:14:04.86#ibcon#about to read 4, iclass 18, count 2 2006.245.08:14:04.86#ibcon#read 4, iclass 18, count 2 2006.245.08:14:04.86#ibcon#about to read 5, iclass 18, count 2 2006.245.08:14:04.86#ibcon#read 5, iclass 18, count 2 2006.245.08:14:04.86#ibcon#about to read 6, iclass 18, count 2 2006.245.08:14:04.86#ibcon#read 6, iclass 18, count 2 2006.245.08:14:04.86#ibcon#end of sib2, iclass 18, count 2 2006.245.08:14:04.86#ibcon#*mode == 0, iclass 18, count 2 2006.245.08:14:04.86#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.08:14:04.86#ibcon#[27=AT05-03\r\n] 2006.245.08:14:04.86#ibcon#*before write, iclass 18, count 2 2006.245.08:14:04.86#ibcon#enter sib2, iclass 18, count 2 2006.245.08:14:04.86#ibcon#flushed, iclass 18, count 2 2006.245.08:14:04.86#ibcon#about to write, iclass 18, count 2 2006.245.08:14:04.86#ibcon#wrote, iclass 18, count 2 2006.245.08:14:04.86#ibcon#about to read 3, iclass 18, count 2 2006.245.08:14:04.89#ibcon#read 3, iclass 18, count 2 2006.245.08:14:04.89#ibcon#about to read 4, iclass 18, count 2 2006.245.08:14:04.89#ibcon#read 4, iclass 18, count 2 2006.245.08:14:04.89#ibcon#about to read 5, iclass 18, count 2 2006.245.08:14:04.89#ibcon#read 5, iclass 18, count 2 2006.245.08:14:04.89#ibcon#about to read 6, iclass 18, count 2 2006.245.08:14:04.89#ibcon#read 6, iclass 18, count 2 2006.245.08:14:04.89#ibcon#end of sib2, iclass 18, count 2 2006.245.08:14:04.89#ibcon#*after write, iclass 18, count 2 2006.245.08:14:04.89#ibcon#*before return 0, iclass 18, count 2 2006.245.08:14:04.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:04.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:14:04.89#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.08:14:04.89#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:04.89#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:05.01#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:05.01#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:05.01#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:14:05.01#ibcon#first serial, iclass 18, count 0 2006.245.08:14:05.01#ibcon#enter sib2, iclass 18, count 0 2006.245.08:14:05.01#ibcon#flushed, iclass 18, count 0 2006.245.08:14:05.01#ibcon#about to write, iclass 18, count 0 2006.245.08:14:05.01#ibcon#wrote, iclass 18, count 0 2006.245.08:14:05.01#ibcon#about to read 3, iclass 18, count 0 2006.245.08:14:05.03#ibcon#read 3, iclass 18, count 0 2006.245.08:14:05.03#ibcon#about to read 4, iclass 18, count 0 2006.245.08:14:05.03#ibcon#read 4, iclass 18, count 0 2006.245.08:14:05.03#ibcon#about to read 5, iclass 18, count 0 2006.245.08:14:05.03#ibcon#read 5, iclass 18, count 0 2006.245.08:14:05.03#ibcon#about to read 6, iclass 18, count 0 2006.245.08:14:05.03#ibcon#read 6, iclass 18, count 0 2006.245.08:14:05.03#ibcon#end of sib2, iclass 18, count 0 2006.245.08:14:05.03#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:14:05.03#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:14:05.03#ibcon#[27=USB\r\n] 2006.245.08:14:05.03#ibcon#*before write, iclass 18, count 0 2006.245.08:14:05.03#ibcon#enter sib2, iclass 18, count 0 2006.245.08:14:05.03#ibcon#flushed, iclass 18, count 0 2006.245.08:14:05.03#ibcon#about to write, iclass 18, count 0 2006.245.08:14:05.03#ibcon#wrote, iclass 18, count 0 2006.245.08:14:05.03#ibcon#about to read 3, iclass 18, count 0 2006.245.08:14:05.06#ibcon#read 3, iclass 18, count 0 2006.245.08:14:05.06#ibcon#about to read 4, iclass 18, count 0 2006.245.08:14:05.06#ibcon#read 4, iclass 18, count 0 2006.245.08:14:05.06#ibcon#about to read 5, iclass 18, count 0 2006.245.08:14:05.06#ibcon#read 5, iclass 18, count 0 2006.245.08:14:05.06#ibcon#about to read 6, iclass 18, count 0 2006.245.08:14:05.06#ibcon#read 6, iclass 18, count 0 2006.245.08:14:05.06#ibcon#end of sib2, iclass 18, count 0 2006.245.08:14:05.06#ibcon#*after write, iclass 18, count 0 2006.245.08:14:05.06#ibcon#*before return 0, iclass 18, count 0 2006.245.08:14:05.06#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:05.06#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:14:05.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:14:05.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:14:05.06$vc4f8/vblo=6,752.99 2006.245.08:14:05.06#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.08:14:05.06#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.08:14:05.06#ibcon#ireg 17 cls_cnt 0 2006.245.08:14:05.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:05.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:05.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:05.06#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:14:05.06#ibcon#first serial, iclass 20, count 0 2006.245.08:14:05.06#ibcon#enter sib2, iclass 20, count 0 2006.245.08:14:05.06#ibcon#flushed, iclass 20, count 0 2006.245.08:14:05.06#ibcon#about to write, iclass 20, count 0 2006.245.08:14:05.06#ibcon#wrote, iclass 20, count 0 2006.245.08:14:05.06#ibcon#about to read 3, iclass 20, count 0 2006.245.08:14:05.08#ibcon#read 3, iclass 20, count 0 2006.245.08:14:05.08#ibcon#about to read 4, iclass 20, count 0 2006.245.08:14:05.08#ibcon#read 4, iclass 20, count 0 2006.245.08:14:05.08#ibcon#about to read 5, iclass 20, count 0 2006.245.08:14:05.08#ibcon#read 5, iclass 20, count 0 2006.245.08:14:05.08#ibcon#about to read 6, iclass 20, count 0 2006.245.08:14:05.08#ibcon#read 6, iclass 20, count 0 2006.245.08:14:05.08#ibcon#end of sib2, iclass 20, count 0 2006.245.08:14:05.08#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:14:05.08#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:14:05.08#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:14:05.08#ibcon#*before write, iclass 20, count 0 2006.245.08:14:05.08#ibcon#enter sib2, iclass 20, count 0 2006.245.08:14:05.08#ibcon#flushed, iclass 20, count 0 2006.245.08:14:05.08#ibcon#about to write, iclass 20, count 0 2006.245.08:14:05.08#ibcon#wrote, iclass 20, count 0 2006.245.08:14:05.08#ibcon#about to read 3, iclass 20, count 0 2006.245.08:14:05.12#ibcon#read 3, iclass 20, count 0 2006.245.08:14:05.12#ibcon#about to read 4, iclass 20, count 0 2006.245.08:14:05.12#ibcon#read 4, iclass 20, count 0 2006.245.08:14:05.12#ibcon#about to read 5, iclass 20, count 0 2006.245.08:14:05.12#ibcon#read 5, iclass 20, count 0 2006.245.08:14:05.12#ibcon#about to read 6, iclass 20, count 0 2006.245.08:14:05.12#ibcon#read 6, iclass 20, count 0 2006.245.08:14:05.12#ibcon#end of sib2, iclass 20, count 0 2006.245.08:14:05.12#ibcon#*after write, iclass 20, count 0 2006.245.08:14:05.12#ibcon#*before return 0, iclass 20, count 0 2006.245.08:14:05.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:05.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:14:05.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:14:05.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:14:05.12$vc4f8/vb=6,3 2006.245.08:14:05.12#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.08:14:05.12#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.08:14:05.12#ibcon#ireg 11 cls_cnt 2 2006.245.08:14:05.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:05.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:05.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:05.18#ibcon#enter wrdev, iclass 22, count 2 2006.245.08:14:05.18#ibcon#first serial, iclass 22, count 2 2006.245.08:14:05.18#ibcon#enter sib2, iclass 22, count 2 2006.245.08:14:05.18#ibcon#flushed, iclass 22, count 2 2006.245.08:14:05.18#ibcon#about to write, iclass 22, count 2 2006.245.08:14:05.18#ibcon#wrote, iclass 22, count 2 2006.245.08:14:05.18#ibcon#about to read 3, iclass 22, count 2 2006.245.08:14:05.20#ibcon#read 3, iclass 22, count 2 2006.245.08:14:05.20#ibcon#about to read 4, iclass 22, count 2 2006.245.08:14:05.20#ibcon#read 4, iclass 22, count 2 2006.245.08:14:05.20#ibcon#about to read 5, iclass 22, count 2 2006.245.08:14:05.20#ibcon#read 5, iclass 22, count 2 2006.245.08:14:05.20#ibcon#about to read 6, iclass 22, count 2 2006.245.08:14:05.20#ibcon#read 6, iclass 22, count 2 2006.245.08:14:05.20#ibcon#end of sib2, iclass 22, count 2 2006.245.08:14:05.20#ibcon#*mode == 0, iclass 22, count 2 2006.245.08:14:05.20#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.08:14:05.20#ibcon#[27=AT06-03\r\n] 2006.245.08:14:05.20#ibcon#*before write, iclass 22, count 2 2006.245.08:14:05.20#ibcon#enter sib2, iclass 22, count 2 2006.245.08:14:05.20#ibcon#flushed, iclass 22, count 2 2006.245.08:14:05.20#ibcon#about to write, iclass 22, count 2 2006.245.08:14:05.20#ibcon#wrote, iclass 22, count 2 2006.245.08:14:05.20#ibcon#about to read 3, iclass 22, count 2 2006.245.08:14:05.23#ibcon#read 3, iclass 22, count 2 2006.245.08:14:05.23#ibcon#about to read 4, iclass 22, count 2 2006.245.08:14:05.23#ibcon#read 4, iclass 22, count 2 2006.245.08:14:05.23#ibcon#about to read 5, iclass 22, count 2 2006.245.08:14:05.23#ibcon#read 5, iclass 22, count 2 2006.245.08:14:05.23#ibcon#about to read 6, iclass 22, count 2 2006.245.08:14:05.23#ibcon#read 6, iclass 22, count 2 2006.245.08:14:05.23#ibcon#end of sib2, iclass 22, count 2 2006.245.08:14:05.23#ibcon#*after write, iclass 22, count 2 2006.245.08:14:05.23#ibcon#*before return 0, iclass 22, count 2 2006.245.08:14:05.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:05.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:14:05.23#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.08:14:05.23#ibcon#ireg 7 cls_cnt 0 2006.245.08:14:05.23#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:05.35#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:05.35#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:05.35#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:14:05.35#ibcon#first serial, iclass 22, count 0 2006.245.08:14:05.35#ibcon#enter sib2, iclass 22, count 0 2006.245.08:14:05.35#ibcon#flushed, iclass 22, count 0 2006.245.08:14:05.35#ibcon#about to write, iclass 22, count 0 2006.245.08:14:05.35#ibcon#wrote, iclass 22, count 0 2006.245.08:14:05.35#ibcon#about to read 3, iclass 22, count 0 2006.245.08:14:05.37#ibcon#read 3, iclass 22, count 0 2006.245.08:14:05.37#ibcon#about to read 4, iclass 22, count 0 2006.245.08:14:05.37#ibcon#read 4, iclass 22, count 0 2006.245.08:14:05.37#ibcon#about to read 5, iclass 22, count 0 2006.245.08:14:05.37#ibcon#read 5, iclass 22, count 0 2006.245.08:14:05.37#ibcon#about to read 6, iclass 22, count 0 2006.245.08:14:05.37#ibcon#read 6, iclass 22, count 0 2006.245.08:14:05.37#ibcon#end of sib2, iclass 22, count 0 2006.245.08:14:05.37#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:14:05.37#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:14:05.37#ibcon#[27=USB\r\n] 2006.245.08:14:05.37#ibcon#*before write, iclass 22, count 0 2006.245.08:14:05.37#ibcon#enter sib2, iclass 22, count 0 2006.245.08:14:05.37#ibcon#flushed, iclass 22, count 0 2006.245.08:14:05.37#ibcon#about to write, iclass 22, count 0 2006.245.08:14:05.37#ibcon#wrote, iclass 22, count 0 2006.245.08:14:05.37#ibcon#about to read 3, iclass 22, count 0 2006.245.08:14:05.40#ibcon#read 3, iclass 22, count 0 2006.245.08:14:05.40#ibcon#about to read 4, iclass 22, count 0 2006.245.08:14:05.40#ibcon#read 4, iclass 22, count 0 2006.245.08:14:05.40#ibcon#about to read 5, iclass 22, count 0 2006.245.08:14:05.40#ibcon#read 5, iclass 22, count 0 2006.245.08:14:05.40#ibcon#about to read 6, iclass 22, count 0 2006.245.08:14:05.40#ibcon#read 6, iclass 22, count 0 2006.245.08:14:05.40#ibcon#end of sib2, iclass 22, count 0 2006.245.08:14:05.40#ibcon#*after write, iclass 22, count 0 2006.245.08:14:05.40#ibcon#*before return 0, iclass 22, count 0 2006.245.08:14:05.40#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:05.40#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:14:05.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:14:05.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:14:05.40$vc4f8/vabw=wide 2006.245.08:14:05.40#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:14:05.40#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:14:05.40#ibcon#ireg 8 cls_cnt 0 2006.245.08:14:05.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:05.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:05.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:05.40#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:14:05.40#ibcon#first serial, iclass 24, count 0 2006.245.08:14:05.40#ibcon#enter sib2, iclass 24, count 0 2006.245.08:14:05.40#ibcon#flushed, iclass 24, count 0 2006.245.08:14:05.40#ibcon#about to write, iclass 24, count 0 2006.245.08:14:05.40#ibcon#wrote, iclass 24, count 0 2006.245.08:14:05.40#ibcon#about to read 3, iclass 24, count 0 2006.245.08:14:05.42#ibcon#read 3, iclass 24, count 0 2006.245.08:14:05.42#ibcon#about to read 4, iclass 24, count 0 2006.245.08:14:05.42#ibcon#read 4, iclass 24, count 0 2006.245.08:14:05.42#ibcon#about to read 5, iclass 24, count 0 2006.245.08:14:05.42#ibcon#read 5, iclass 24, count 0 2006.245.08:14:05.42#ibcon#about to read 6, iclass 24, count 0 2006.245.08:14:05.42#ibcon#read 6, iclass 24, count 0 2006.245.08:14:05.42#ibcon#end of sib2, iclass 24, count 0 2006.245.08:14:05.42#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:14:05.42#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:14:05.42#ibcon#[25=BW32\r\n] 2006.245.08:14:05.42#ibcon#*before write, iclass 24, count 0 2006.245.08:14:05.42#ibcon#enter sib2, iclass 24, count 0 2006.245.08:14:05.42#ibcon#flushed, iclass 24, count 0 2006.245.08:14:05.42#ibcon#about to write, iclass 24, count 0 2006.245.08:14:05.42#ibcon#wrote, iclass 24, count 0 2006.245.08:14:05.42#ibcon#about to read 3, iclass 24, count 0 2006.245.08:14:05.45#ibcon#read 3, iclass 24, count 0 2006.245.08:14:05.45#ibcon#about to read 4, iclass 24, count 0 2006.245.08:14:05.45#ibcon#read 4, iclass 24, count 0 2006.245.08:14:05.45#ibcon#about to read 5, iclass 24, count 0 2006.245.08:14:05.45#ibcon#read 5, iclass 24, count 0 2006.245.08:14:05.45#ibcon#about to read 6, iclass 24, count 0 2006.245.08:14:05.45#ibcon#read 6, iclass 24, count 0 2006.245.08:14:05.45#ibcon#end of sib2, iclass 24, count 0 2006.245.08:14:05.45#ibcon#*after write, iclass 24, count 0 2006.245.08:14:05.45#ibcon#*before return 0, iclass 24, count 0 2006.245.08:14:05.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:05.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:14:05.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:14:05.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:14:05.45$vc4f8/vbbw=wide 2006.245.08:14:05.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.08:14:05.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.08:14:05.45#ibcon#ireg 8 cls_cnt 0 2006.245.08:14:05.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:14:05.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:14:05.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:14:05.52#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:14:05.52#ibcon#first serial, iclass 26, count 0 2006.245.08:14:05.52#ibcon#enter sib2, iclass 26, count 0 2006.245.08:14:05.52#ibcon#flushed, iclass 26, count 0 2006.245.08:14:05.52#ibcon#about to write, iclass 26, count 0 2006.245.08:14:05.52#ibcon#wrote, iclass 26, count 0 2006.245.08:14:05.52#ibcon#about to read 3, iclass 26, count 0 2006.245.08:14:05.54#ibcon#read 3, iclass 26, count 0 2006.245.08:14:05.54#ibcon#about to read 4, iclass 26, count 0 2006.245.08:14:05.54#ibcon#read 4, iclass 26, count 0 2006.245.08:14:05.54#ibcon#about to read 5, iclass 26, count 0 2006.245.08:14:05.54#ibcon#read 5, iclass 26, count 0 2006.245.08:14:05.54#ibcon#about to read 6, iclass 26, count 0 2006.245.08:14:05.54#ibcon#read 6, iclass 26, count 0 2006.245.08:14:05.54#ibcon#end of sib2, iclass 26, count 0 2006.245.08:14:05.54#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:14:05.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:14:05.54#ibcon#[27=BW32\r\n] 2006.245.08:14:05.54#ibcon#*before write, iclass 26, count 0 2006.245.08:14:05.54#ibcon#enter sib2, iclass 26, count 0 2006.245.08:14:05.54#ibcon#flushed, iclass 26, count 0 2006.245.08:14:05.54#ibcon#about to write, iclass 26, count 0 2006.245.08:14:05.54#ibcon#wrote, iclass 26, count 0 2006.245.08:14:05.54#ibcon#about to read 3, iclass 26, count 0 2006.245.08:14:05.57#ibcon#read 3, iclass 26, count 0 2006.245.08:14:05.57#ibcon#about to read 4, iclass 26, count 0 2006.245.08:14:05.57#ibcon#read 4, iclass 26, count 0 2006.245.08:14:05.57#ibcon#about to read 5, iclass 26, count 0 2006.245.08:14:05.57#ibcon#read 5, iclass 26, count 0 2006.245.08:14:05.57#ibcon#about to read 6, iclass 26, count 0 2006.245.08:14:05.57#ibcon#read 6, iclass 26, count 0 2006.245.08:14:05.57#ibcon#end of sib2, iclass 26, count 0 2006.245.08:14:05.57#ibcon#*after write, iclass 26, count 0 2006.245.08:14:05.57#ibcon#*before return 0, iclass 26, count 0 2006.245.08:14:05.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:14:05.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:14:05.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:14:05.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:14:05.57$4f8m12a/ifd4f 2006.245.08:14:05.57$ifd4f/lo= 2006.245.08:14:05.57$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:14:05.57$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:14:05.57$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:14:05.57$ifd4f/patch= 2006.245.08:14:05.57$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:14:05.57$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:14:05.57$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:14:05.57$4f8m12a/"form=m,16.000,1:2 2006.245.08:14:05.57$4f8m12a/"tpicd 2006.245.08:14:05.57$4f8m12a/echo=off 2006.245.08:14:05.57$4f8m12a/xlog=off 2006.245.08:14:05.57:!2006.245.08:14:30 2006.245.08:14:16.14#trakl#Source acquired 2006.245.08:14:18.14#flagr#flagr/antenna,acquired 2006.245.08:14:30.00:preob 2006.245.08:14:31.14/onsource/TRACKING 2006.245.08:14:31.14:!2006.245.08:14:40 2006.245.08:14:40.00:data_valid=on 2006.245.08:14:40.00:midob 2006.245.08:14:40.14/onsource/TRACKING 2006.245.08:14:40.14/wx/26.86,1004.5,75 2006.245.08:14:40.29/cable/+6.4094E-03 2006.245.08:14:41.38/va/01,08,usb,yes,30,32 2006.245.08:14:41.38/va/02,07,usb,yes,30,32 2006.245.08:14:41.38/va/03,06,usb,yes,32,32 2006.245.08:14:41.38/va/04,07,usb,yes,31,34 2006.245.08:14:41.38/va/05,07,usb,yes,34,36 2006.245.08:14:41.38/va/06,07,usb,yes,29,29 2006.245.08:14:41.38/va/07,07,usb,yes,29,29 2006.245.08:14:41.38/va/08,08,usb,yes,26,25 2006.245.08:14:41.61/valo/01,532.99,yes,locked 2006.245.08:14:41.61/valo/02,572.99,yes,locked 2006.245.08:14:41.61/valo/03,672.99,yes,locked 2006.245.08:14:41.61/valo/04,832.99,yes,locked 2006.245.08:14:41.61/valo/05,652.99,yes,locked 2006.245.08:14:41.61/valo/06,772.99,yes,locked 2006.245.08:14:41.61/valo/07,832.99,yes,locked 2006.245.08:14:41.61/valo/08,852.99,yes,locked 2006.245.08:14:42.70/vb/01,04,usb,yes,30,29 2006.245.08:14:42.70/vb/02,04,usb,yes,32,34 2006.245.08:14:42.70/vb/03,04,usb,yes,28,32 2006.245.08:14:42.70/vb/04,04,usb,yes,29,29 2006.245.08:14:42.70/vb/05,03,usb,yes,35,39 2006.245.08:14:42.70/vb/06,03,usb,yes,35,39 2006.245.08:14:42.70/vb/07,04,usb,yes,31,31 2006.245.08:14:42.70/vb/08,03,usb,yes,35,39 2006.245.08:14:42.94/vblo/01,632.99,yes,locked 2006.245.08:14:42.94/vblo/02,640.99,yes,locked 2006.245.08:14:42.94/vblo/03,656.99,yes,locked 2006.245.08:14:42.94/vblo/04,712.99,yes,locked 2006.245.08:14:42.94/vblo/05,744.99,yes,locked 2006.245.08:14:42.94/vblo/06,752.99,yes,locked 2006.245.08:14:42.94/vblo/07,734.99,yes,locked 2006.245.08:14:42.94/vblo/08,744.99,yes,locked 2006.245.08:14:43.09/vabw/8 2006.245.08:14:43.24/vbbw/8 2006.245.08:14:43.35/xfe/off,on,13.2 2006.245.08:14:43.73/ifatt/23,28,28,28 2006.245.08:14:44.08/fmout-gps/S +4.39E-07 2006.245.08:14:44.12:!2006.245.08:15:40 2006.245.08:15:40.00:data_valid=off 2006.245.08:15:40.00:postob 2006.245.08:15:40.07/cable/+6.4098E-03 2006.245.08:15:40.08/wx/26.83,1004.5,75 2006.245.08:15:41.08/fmout-gps/S +4.38E-07 2006.245.08:15:41.08:scan_name=245-0816,k06245,60 2006.245.08:15:41.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.245.08:15:41.14#flagr#flagr/antenna,new-source 2006.245.08:15:42.14:checkk5 2006.245.08:15:43.45/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:15:43.91/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:15:44.33/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:15:44.89/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:15:45.54/chk_obsdata//k5ts1/T2450814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:15:46.16/chk_obsdata//k5ts2/T2450814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:15:46.56/chk_obsdata//k5ts3/T2450814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:15:46.97/chk_obsdata//k5ts4/T2450814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:15:48.02/k5log//k5ts1_log_newline 2006.245.08:15:48.88/k5log//k5ts2_log_newline 2006.245.08:15:49.71/k5log//k5ts3_log_newline 2006.245.08:15:50.79/k5log//k5ts4_log_newline 2006.245.08:15:50.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:15:50.82:4f8m12a=2 2006.245.08:15:50.82$4f8m12a/echo=on 2006.245.08:15:50.82$4f8m12a/pcalon 2006.245.08:15:50.82$pcalon/"no phase cal control is implemented here 2006.245.08:15:50.82$4f8m12a/"tpicd=stop 2006.245.08:15:50.82$4f8m12a/vc4f8 2006.245.08:15:50.82$vc4f8/valo=1,532.99 2006.245.08:15:50.82#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:15:50.82#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:15:50.82#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:50.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:50.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:50.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:50.82#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:15:50.82#ibcon#first serial, iclass 33, count 0 2006.245.08:15:50.82#ibcon#enter sib2, iclass 33, count 0 2006.245.08:15:50.82#ibcon#flushed, iclass 33, count 0 2006.245.08:15:50.82#ibcon#about to write, iclass 33, count 0 2006.245.08:15:50.82#ibcon#wrote, iclass 33, count 0 2006.245.08:15:50.82#ibcon#about to read 3, iclass 33, count 0 2006.245.08:15:50.86#ibcon#read 3, iclass 33, count 0 2006.245.08:15:50.86#ibcon#about to read 4, iclass 33, count 0 2006.245.08:15:50.86#ibcon#read 4, iclass 33, count 0 2006.245.08:15:50.86#ibcon#about to read 5, iclass 33, count 0 2006.245.08:15:50.86#ibcon#read 5, iclass 33, count 0 2006.245.08:15:50.86#ibcon#about to read 6, iclass 33, count 0 2006.245.08:15:50.86#ibcon#read 6, iclass 33, count 0 2006.245.08:15:50.86#ibcon#end of sib2, iclass 33, count 0 2006.245.08:15:50.86#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:15:50.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:15:50.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:15:50.86#ibcon#*before write, iclass 33, count 0 2006.245.08:15:50.86#ibcon#enter sib2, iclass 33, count 0 2006.245.08:15:50.86#ibcon#flushed, iclass 33, count 0 2006.245.08:15:50.86#ibcon#about to write, iclass 33, count 0 2006.245.08:15:50.86#ibcon#wrote, iclass 33, count 0 2006.245.08:15:50.86#ibcon#about to read 3, iclass 33, count 0 2006.245.08:15:50.91#ibcon#read 3, iclass 33, count 0 2006.245.08:15:50.91#ibcon#about to read 4, iclass 33, count 0 2006.245.08:15:50.91#ibcon#read 4, iclass 33, count 0 2006.245.08:15:50.91#ibcon#about to read 5, iclass 33, count 0 2006.245.08:15:50.91#ibcon#read 5, iclass 33, count 0 2006.245.08:15:50.91#ibcon#about to read 6, iclass 33, count 0 2006.245.08:15:50.91#ibcon#read 6, iclass 33, count 0 2006.245.08:15:50.91#ibcon#end of sib2, iclass 33, count 0 2006.245.08:15:50.91#ibcon#*after write, iclass 33, count 0 2006.245.08:15:50.91#ibcon#*before return 0, iclass 33, count 0 2006.245.08:15:50.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:50.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:50.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:15:50.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:15:50.91$vc4f8/va=1,8 2006.245.08:15:50.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.08:15:50.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.08:15:50.91#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:50.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:50.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:50.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:50.91#ibcon#enter wrdev, iclass 35, count 2 2006.245.08:15:50.91#ibcon#first serial, iclass 35, count 2 2006.245.08:15:50.91#ibcon#enter sib2, iclass 35, count 2 2006.245.08:15:50.91#ibcon#flushed, iclass 35, count 2 2006.245.08:15:50.91#ibcon#about to write, iclass 35, count 2 2006.245.08:15:50.91#ibcon#wrote, iclass 35, count 2 2006.245.08:15:50.91#ibcon#about to read 3, iclass 35, count 2 2006.245.08:15:50.93#ibcon#read 3, iclass 35, count 2 2006.245.08:15:50.93#ibcon#about to read 4, iclass 35, count 2 2006.245.08:15:50.93#ibcon#read 4, iclass 35, count 2 2006.245.08:15:50.93#ibcon#about to read 5, iclass 35, count 2 2006.245.08:15:50.93#ibcon#read 5, iclass 35, count 2 2006.245.08:15:50.93#ibcon#about to read 6, iclass 35, count 2 2006.245.08:15:50.93#ibcon#read 6, iclass 35, count 2 2006.245.08:15:50.93#ibcon#end of sib2, iclass 35, count 2 2006.245.08:15:50.93#ibcon#*mode == 0, iclass 35, count 2 2006.245.08:15:50.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.08:15:50.93#ibcon#[25=AT01-08\r\n] 2006.245.08:15:50.93#ibcon#*before write, iclass 35, count 2 2006.245.08:15:50.93#ibcon#enter sib2, iclass 35, count 2 2006.245.08:15:50.93#ibcon#flushed, iclass 35, count 2 2006.245.08:15:50.93#ibcon#about to write, iclass 35, count 2 2006.245.08:15:50.93#ibcon#wrote, iclass 35, count 2 2006.245.08:15:50.93#ibcon#about to read 3, iclass 35, count 2 2006.245.08:15:50.97#ibcon#read 3, iclass 35, count 2 2006.245.08:15:50.97#ibcon#about to read 4, iclass 35, count 2 2006.245.08:15:50.97#ibcon#read 4, iclass 35, count 2 2006.245.08:15:50.97#ibcon#about to read 5, iclass 35, count 2 2006.245.08:15:50.97#ibcon#read 5, iclass 35, count 2 2006.245.08:15:50.97#ibcon#about to read 6, iclass 35, count 2 2006.245.08:15:50.97#ibcon#read 6, iclass 35, count 2 2006.245.08:15:50.97#ibcon#end of sib2, iclass 35, count 2 2006.245.08:15:50.97#ibcon#*after write, iclass 35, count 2 2006.245.08:15:50.97#ibcon#*before return 0, iclass 35, count 2 2006.245.08:15:50.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:50.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:50.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.08:15:50.97#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:50.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:51.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:51.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:51.09#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:15:51.09#ibcon#first serial, iclass 35, count 0 2006.245.08:15:51.09#ibcon#enter sib2, iclass 35, count 0 2006.245.08:15:51.09#ibcon#flushed, iclass 35, count 0 2006.245.08:15:51.09#ibcon#about to write, iclass 35, count 0 2006.245.08:15:51.09#ibcon#wrote, iclass 35, count 0 2006.245.08:15:51.09#ibcon#about to read 3, iclass 35, count 0 2006.245.08:15:51.11#ibcon#read 3, iclass 35, count 0 2006.245.08:15:51.11#ibcon#about to read 4, iclass 35, count 0 2006.245.08:15:51.11#ibcon#read 4, iclass 35, count 0 2006.245.08:15:51.11#ibcon#about to read 5, iclass 35, count 0 2006.245.08:15:51.11#ibcon#read 5, iclass 35, count 0 2006.245.08:15:51.11#ibcon#about to read 6, iclass 35, count 0 2006.245.08:15:51.11#ibcon#read 6, iclass 35, count 0 2006.245.08:15:51.11#ibcon#end of sib2, iclass 35, count 0 2006.245.08:15:51.11#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:15:51.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:15:51.11#ibcon#[25=USB\r\n] 2006.245.08:15:51.11#ibcon#*before write, iclass 35, count 0 2006.245.08:15:51.11#ibcon#enter sib2, iclass 35, count 0 2006.245.08:15:51.11#ibcon#flushed, iclass 35, count 0 2006.245.08:15:51.11#ibcon#about to write, iclass 35, count 0 2006.245.08:15:51.11#ibcon#wrote, iclass 35, count 0 2006.245.08:15:51.11#ibcon#about to read 3, iclass 35, count 0 2006.245.08:15:51.14#ibcon#read 3, iclass 35, count 0 2006.245.08:15:51.14#ibcon#about to read 4, iclass 35, count 0 2006.245.08:15:51.14#ibcon#read 4, iclass 35, count 0 2006.245.08:15:51.14#ibcon#about to read 5, iclass 35, count 0 2006.245.08:15:51.14#ibcon#read 5, iclass 35, count 0 2006.245.08:15:51.14#ibcon#about to read 6, iclass 35, count 0 2006.245.08:15:51.14#ibcon#read 6, iclass 35, count 0 2006.245.08:15:51.14#ibcon#end of sib2, iclass 35, count 0 2006.245.08:15:51.14#ibcon#*after write, iclass 35, count 0 2006.245.08:15:51.14#ibcon#*before return 0, iclass 35, count 0 2006.245.08:15:51.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:51.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:51.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:15:51.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:15:51.14$vc4f8/valo=2,572.99 2006.245.08:15:51.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.08:15:51.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.08:15:51.14#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:51.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:51.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:51.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:51.14#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:15:51.14#ibcon#first serial, iclass 37, count 0 2006.245.08:15:51.14#ibcon#enter sib2, iclass 37, count 0 2006.245.08:15:51.14#ibcon#flushed, iclass 37, count 0 2006.245.08:15:51.14#ibcon#about to write, iclass 37, count 0 2006.245.08:15:51.14#ibcon#wrote, iclass 37, count 0 2006.245.08:15:51.14#ibcon#about to read 3, iclass 37, count 0 2006.245.08:15:51.16#ibcon#read 3, iclass 37, count 0 2006.245.08:15:51.16#ibcon#about to read 4, iclass 37, count 0 2006.245.08:15:51.16#ibcon#read 4, iclass 37, count 0 2006.245.08:15:51.16#ibcon#about to read 5, iclass 37, count 0 2006.245.08:15:51.16#ibcon#read 5, iclass 37, count 0 2006.245.08:15:51.16#ibcon#about to read 6, iclass 37, count 0 2006.245.08:15:51.16#ibcon#read 6, iclass 37, count 0 2006.245.08:15:51.16#ibcon#end of sib2, iclass 37, count 0 2006.245.08:15:51.16#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:15:51.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:15:51.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:15:51.16#ibcon#*before write, iclass 37, count 0 2006.245.08:15:51.16#ibcon#enter sib2, iclass 37, count 0 2006.245.08:15:51.16#ibcon#flushed, iclass 37, count 0 2006.245.08:15:51.16#ibcon#about to write, iclass 37, count 0 2006.245.08:15:51.16#ibcon#wrote, iclass 37, count 0 2006.245.08:15:51.16#ibcon#about to read 3, iclass 37, count 0 2006.245.08:15:51.20#ibcon#read 3, iclass 37, count 0 2006.245.08:15:51.20#ibcon#about to read 4, iclass 37, count 0 2006.245.08:15:51.20#ibcon#read 4, iclass 37, count 0 2006.245.08:15:51.20#ibcon#about to read 5, iclass 37, count 0 2006.245.08:15:51.20#ibcon#read 5, iclass 37, count 0 2006.245.08:15:51.20#ibcon#about to read 6, iclass 37, count 0 2006.245.08:15:51.20#ibcon#read 6, iclass 37, count 0 2006.245.08:15:51.20#ibcon#end of sib2, iclass 37, count 0 2006.245.08:15:51.20#ibcon#*after write, iclass 37, count 0 2006.245.08:15:51.20#ibcon#*before return 0, iclass 37, count 0 2006.245.08:15:51.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:51.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:51.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:15:51.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:15:51.20$vc4f8/va=2,7 2006.245.08:15:51.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.08:15:51.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.08:15:51.20#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:51.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:51.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:51.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:51.26#ibcon#enter wrdev, iclass 39, count 2 2006.245.08:15:51.26#ibcon#first serial, iclass 39, count 2 2006.245.08:15:51.26#ibcon#enter sib2, iclass 39, count 2 2006.245.08:15:51.26#ibcon#flushed, iclass 39, count 2 2006.245.08:15:51.26#ibcon#about to write, iclass 39, count 2 2006.245.08:15:51.26#ibcon#wrote, iclass 39, count 2 2006.245.08:15:51.26#ibcon#about to read 3, iclass 39, count 2 2006.245.08:15:51.28#ibcon#read 3, iclass 39, count 2 2006.245.08:15:51.28#ibcon#about to read 4, iclass 39, count 2 2006.245.08:15:51.28#ibcon#read 4, iclass 39, count 2 2006.245.08:15:51.28#ibcon#about to read 5, iclass 39, count 2 2006.245.08:15:51.28#ibcon#read 5, iclass 39, count 2 2006.245.08:15:51.28#ibcon#about to read 6, iclass 39, count 2 2006.245.08:15:51.28#ibcon#read 6, iclass 39, count 2 2006.245.08:15:51.28#ibcon#end of sib2, iclass 39, count 2 2006.245.08:15:51.28#ibcon#*mode == 0, iclass 39, count 2 2006.245.08:15:51.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.08:15:51.28#ibcon#[25=AT02-07\r\n] 2006.245.08:15:51.28#ibcon#*before write, iclass 39, count 2 2006.245.08:15:51.28#ibcon#enter sib2, iclass 39, count 2 2006.245.08:15:51.28#ibcon#flushed, iclass 39, count 2 2006.245.08:15:51.28#ibcon#about to write, iclass 39, count 2 2006.245.08:15:51.28#ibcon#wrote, iclass 39, count 2 2006.245.08:15:51.28#ibcon#about to read 3, iclass 39, count 2 2006.245.08:15:51.31#ibcon#read 3, iclass 39, count 2 2006.245.08:15:51.31#ibcon#about to read 4, iclass 39, count 2 2006.245.08:15:51.31#ibcon#read 4, iclass 39, count 2 2006.245.08:15:51.31#ibcon#about to read 5, iclass 39, count 2 2006.245.08:15:51.31#ibcon#read 5, iclass 39, count 2 2006.245.08:15:51.31#ibcon#about to read 6, iclass 39, count 2 2006.245.08:15:51.31#ibcon#read 6, iclass 39, count 2 2006.245.08:15:51.31#ibcon#end of sib2, iclass 39, count 2 2006.245.08:15:51.31#ibcon#*after write, iclass 39, count 2 2006.245.08:15:51.31#ibcon#*before return 0, iclass 39, count 2 2006.245.08:15:51.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:51.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:51.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.08:15:51.31#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:51.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:51.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:51.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:51.43#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:15:51.43#ibcon#first serial, iclass 39, count 0 2006.245.08:15:51.43#ibcon#enter sib2, iclass 39, count 0 2006.245.08:15:51.43#ibcon#flushed, iclass 39, count 0 2006.245.08:15:51.43#ibcon#about to write, iclass 39, count 0 2006.245.08:15:51.43#ibcon#wrote, iclass 39, count 0 2006.245.08:15:51.43#ibcon#about to read 3, iclass 39, count 0 2006.245.08:15:51.45#ibcon#read 3, iclass 39, count 0 2006.245.08:15:51.45#ibcon#about to read 4, iclass 39, count 0 2006.245.08:15:51.45#ibcon#read 4, iclass 39, count 0 2006.245.08:15:51.45#ibcon#about to read 5, iclass 39, count 0 2006.245.08:15:51.45#ibcon#read 5, iclass 39, count 0 2006.245.08:15:51.45#ibcon#about to read 6, iclass 39, count 0 2006.245.08:15:51.45#ibcon#read 6, iclass 39, count 0 2006.245.08:15:51.45#ibcon#end of sib2, iclass 39, count 0 2006.245.08:15:51.45#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:15:51.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:15:51.45#ibcon#[25=USB\r\n] 2006.245.08:15:51.45#ibcon#*before write, iclass 39, count 0 2006.245.08:15:51.45#ibcon#enter sib2, iclass 39, count 0 2006.245.08:15:51.45#ibcon#flushed, iclass 39, count 0 2006.245.08:15:51.45#ibcon#about to write, iclass 39, count 0 2006.245.08:15:51.45#ibcon#wrote, iclass 39, count 0 2006.245.08:15:51.45#ibcon#about to read 3, iclass 39, count 0 2006.245.08:15:51.48#ibcon#read 3, iclass 39, count 0 2006.245.08:15:51.48#ibcon#about to read 4, iclass 39, count 0 2006.245.08:15:51.48#ibcon#read 4, iclass 39, count 0 2006.245.08:15:51.48#ibcon#about to read 5, iclass 39, count 0 2006.245.08:15:51.48#ibcon#read 5, iclass 39, count 0 2006.245.08:15:51.48#ibcon#about to read 6, iclass 39, count 0 2006.245.08:15:51.48#ibcon#read 6, iclass 39, count 0 2006.245.08:15:51.48#ibcon#end of sib2, iclass 39, count 0 2006.245.08:15:51.48#ibcon#*after write, iclass 39, count 0 2006.245.08:15:51.48#ibcon#*before return 0, iclass 39, count 0 2006.245.08:15:51.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:51.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:51.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:15:51.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:15:51.48$vc4f8/valo=3,672.99 2006.245.08:15:51.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:15:51.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:15:51.48#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:51.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:51.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:51.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:51.48#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:15:51.48#ibcon#first serial, iclass 3, count 0 2006.245.08:15:51.48#ibcon#enter sib2, iclass 3, count 0 2006.245.08:15:51.48#ibcon#flushed, iclass 3, count 0 2006.245.08:15:51.48#ibcon#about to write, iclass 3, count 0 2006.245.08:15:51.48#ibcon#wrote, iclass 3, count 0 2006.245.08:15:51.48#ibcon#about to read 3, iclass 3, count 0 2006.245.08:15:51.50#ibcon#read 3, iclass 3, count 0 2006.245.08:15:51.50#ibcon#about to read 4, iclass 3, count 0 2006.245.08:15:51.50#ibcon#read 4, iclass 3, count 0 2006.245.08:15:51.50#ibcon#about to read 5, iclass 3, count 0 2006.245.08:15:51.50#ibcon#read 5, iclass 3, count 0 2006.245.08:15:51.50#ibcon#about to read 6, iclass 3, count 0 2006.245.08:15:51.50#ibcon#read 6, iclass 3, count 0 2006.245.08:15:51.50#ibcon#end of sib2, iclass 3, count 0 2006.245.08:15:51.50#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:15:51.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:15:51.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:15:51.50#ibcon#*before write, iclass 3, count 0 2006.245.08:15:51.50#ibcon#enter sib2, iclass 3, count 0 2006.245.08:15:51.50#ibcon#flushed, iclass 3, count 0 2006.245.08:15:51.50#ibcon#about to write, iclass 3, count 0 2006.245.08:15:51.50#ibcon#wrote, iclass 3, count 0 2006.245.08:15:51.50#ibcon#about to read 3, iclass 3, count 0 2006.245.08:15:51.54#ibcon#read 3, iclass 3, count 0 2006.245.08:15:51.54#ibcon#about to read 4, iclass 3, count 0 2006.245.08:15:51.54#ibcon#read 4, iclass 3, count 0 2006.245.08:15:51.54#ibcon#about to read 5, iclass 3, count 0 2006.245.08:15:51.54#ibcon#read 5, iclass 3, count 0 2006.245.08:15:51.54#ibcon#about to read 6, iclass 3, count 0 2006.245.08:15:51.54#ibcon#read 6, iclass 3, count 0 2006.245.08:15:51.54#ibcon#end of sib2, iclass 3, count 0 2006.245.08:15:51.54#ibcon#*after write, iclass 3, count 0 2006.245.08:15:51.54#ibcon#*before return 0, iclass 3, count 0 2006.245.08:15:51.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:51.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:51.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:15:51.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:15:51.54$vc4f8/va=3,6 2006.245.08:15:51.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:15:51.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:15:51.54#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:51.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:51.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:51.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:51.60#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:15:51.60#ibcon#first serial, iclass 5, count 2 2006.245.08:15:51.60#ibcon#enter sib2, iclass 5, count 2 2006.245.08:15:51.60#ibcon#flushed, iclass 5, count 2 2006.245.08:15:51.60#ibcon#about to write, iclass 5, count 2 2006.245.08:15:51.61#ibcon#wrote, iclass 5, count 2 2006.245.08:15:51.61#ibcon#about to read 3, iclass 5, count 2 2006.245.08:15:51.62#ibcon#read 3, iclass 5, count 2 2006.245.08:15:51.62#ibcon#about to read 4, iclass 5, count 2 2006.245.08:15:51.62#ibcon#read 4, iclass 5, count 2 2006.245.08:15:51.62#ibcon#about to read 5, iclass 5, count 2 2006.245.08:15:51.62#ibcon#read 5, iclass 5, count 2 2006.245.08:15:51.62#ibcon#about to read 6, iclass 5, count 2 2006.245.08:15:51.62#ibcon#read 6, iclass 5, count 2 2006.245.08:15:51.62#ibcon#end of sib2, iclass 5, count 2 2006.245.08:15:51.62#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:15:51.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:15:51.62#ibcon#[25=AT03-06\r\n] 2006.245.08:15:51.62#ibcon#*before write, iclass 5, count 2 2006.245.08:15:51.62#ibcon#enter sib2, iclass 5, count 2 2006.245.08:15:51.62#ibcon#flushed, iclass 5, count 2 2006.245.08:15:51.62#ibcon#about to write, iclass 5, count 2 2006.245.08:15:51.62#ibcon#wrote, iclass 5, count 2 2006.245.08:15:51.62#ibcon#about to read 3, iclass 5, count 2 2006.245.08:15:51.65#ibcon#read 3, iclass 5, count 2 2006.245.08:15:51.65#ibcon#about to read 4, iclass 5, count 2 2006.245.08:15:51.65#ibcon#read 4, iclass 5, count 2 2006.245.08:15:51.65#ibcon#about to read 5, iclass 5, count 2 2006.245.08:15:51.65#ibcon#read 5, iclass 5, count 2 2006.245.08:15:51.65#ibcon#about to read 6, iclass 5, count 2 2006.245.08:15:51.65#ibcon#read 6, iclass 5, count 2 2006.245.08:15:51.65#ibcon#end of sib2, iclass 5, count 2 2006.245.08:15:51.65#ibcon#*after write, iclass 5, count 2 2006.245.08:15:51.65#ibcon#*before return 0, iclass 5, count 2 2006.245.08:15:51.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:51.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:51.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:15:51.65#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:51.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:51.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:51.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:51.77#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:15:51.77#ibcon#first serial, iclass 5, count 0 2006.245.08:15:51.77#ibcon#enter sib2, iclass 5, count 0 2006.245.08:15:51.77#ibcon#flushed, iclass 5, count 0 2006.245.08:15:51.77#ibcon#about to write, iclass 5, count 0 2006.245.08:15:51.77#ibcon#wrote, iclass 5, count 0 2006.245.08:15:51.77#ibcon#about to read 3, iclass 5, count 0 2006.245.08:15:51.79#ibcon#read 3, iclass 5, count 0 2006.245.08:15:51.79#ibcon#about to read 4, iclass 5, count 0 2006.245.08:15:51.79#ibcon#read 4, iclass 5, count 0 2006.245.08:15:51.79#ibcon#about to read 5, iclass 5, count 0 2006.245.08:15:51.79#ibcon#read 5, iclass 5, count 0 2006.245.08:15:51.79#ibcon#about to read 6, iclass 5, count 0 2006.245.08:15:51.79#ibcon#read 6, iclass 5, count 0 2006.245.08:15:51.79#ibcon#end of sib2, iclass 5, count 0 2006.245.08:15:51.79#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:15:51.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:15:51.79#ibcon#[25=USB\r\n] 2006.245.08:15:51.79#ibcon#*before write, iclass 5, count 0 2006.245.08:15:51.79#ibcon#enter sib2, iclass 5, count 0 2006.245.08:15:51.79#ibcon#flushed, iclass 5, count 0 2006.245.08:15:51.79#ibcon#about to write, iclass 5, count 0 2006.245.08:15:51.79#ibcon#wrote, iclass 5, count 0 2006.245.08:15:51.79#ibcon#about to read 3, iclass 5, count 0 2006.245.08:15:51.82#ibcon#read 3, iclass 5, count 0 2006.245.08:15:51.82#ibcon#about to read 4, iclass 5, count 0 2006.245.08:15:51.82#ibcon#read 4, iclass 5, count 0 2006.245.08:15:51.82#ibcon#about to read 5, iclass 5, count 0 2006.245.08:15:51.82#ibcon#read 5, iclass 5, count 0 2006.245.08:15:51.82#ibcon#about to read 6, iclass 5, count 0 2006.245.08:15:51.82#ibcon#read 6, iclass 5, count 0 2006.245.08:15:51.82#ibcon#end of sib2, iclass 5, count 0 2006.245.08:15:51.82#ibcon#*after write, iclass 5, count 0 2006.245.08:15:51.82#ibcon#*before return 0, iclass 5, count 0 2006.245.08:15:51.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:51.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:51.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:15:51.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:15:51.82$vc4f8/valo=4,832.99 2006.245.08:15:51.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:15:51.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:15:51.82#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:51.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:51.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:51.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:51.82#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:15:51.82#ibcon#first serial, iclass 7, count 0 2006.245.08:15:51.82#ibcon#enter sib2, iclass 7, count 0 2006.245.08:15:51.82#ibcon#flushed, iclass 7, count 0 2006.245.08:15:51.82#ibcon#about to write, iclass 7, count 0 2006.245.08:15:51.82#ibcon#wrote, iclass 7, count 0 2006.245.08:15:51.82#ibcon#about to read 3, iclass 7, count 0 2006.245.08:15:51.84#ibcon#read 3, iclass 7, count 0 2006.245.08:15:51.84#ibcon#about to read 4, iclass 7, count 0 2006.245.08:15:51.84#ibcon#read 4, iclass 7, count 0 2006.245.08:15:51.84#ibcon#about to read 5, iclass 7, count 0 2006.245.08:15:51.84#ibcon#read 5, iclass 7, count 0 2006.245.08:15:51.84#ibcon#about to read 6, iclass 7, count 0 2006.245.08:15:51.84#ibcon#read 6, iclass 7, count 0 2006.245.08:15:51.84#ibcon#end of sib2, iclass 7, count 0 2006.245.08:15:51.84#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:15:51.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:15:51.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:15:51.84#ibcon#*before write, iclass 7, count 0 2006.245.08:15:51.84#ibcon#enter sib2, iclass 7, count 0 2006.245.08:15:51.84#ibcon#flushed, iclass 7, count 0 2006.245.08:15:51.84#ibcon#about to write, iclass 7, count 0 2006.245.08:15:51.84#ibcon#wrote, iclass 7, count 0 2006.245.08:15:51.84#ibcon#about to read 3, iclass 7, count 0 2006.245.08:15:51.88#ibcon#read 3, iclass 7, count 0 2006.245.08:15:51.88#ibcon#about to read 4, iclass 7, count 0 2006.245.08:15:51.88#ibcon#read 4, iclass 7, count 0 2006.245.08:15:51.88#ibcon#about to read 5, iclass 7, count 0 2006.245.08:15:51.88#ibcon#read 5, iclass 7, count 0 2006.245.08:15:51.88#ibcon#about to read 6, iclass 7, count 0 2006.245.08:15:51.88#ibcon#read 6, iclass 7, count 0 2006.245.08:15:51.88#ibcon#end of sib2, iclass 7, count 0 2006.245.08:15:51.88#ibcon#*after write, iclass 7, count 0 2006.245.08:15:51.88#ibcon#*before return 0, iclass 7, count 0 2006.245.08:15:51.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:51.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:51.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:15:51.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:15:51.88$vc4f8/va=4,7 2006.245.08:15:51.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:15:51.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:15:51.88#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:51.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:51.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:51.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:51.94#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:15:51.94#ibcon#first serial, iclass 11, count 2 2006.245.08:15:51.94#ibcon#enter sib2, iclass 11, count 2 2006.245.08:15:51.94#ibcon#flushed, iclass 11, count 2 2006.245.08:15:51.94#ibcon#about to write, iclass 11, count 2 2006.245.08:15:51.94#ibcon#wrote, iclass 11, count 2 2006.245.08:15:51.94#ibcon#about to read 3, iclass 11, count 2 2006.245.08:15:51.96#ibcon#read 3, iclass 11, count 2 2006.245.08:15:51.96#ibcon#about to read 4, iclass 11, count 2 2006.245.08:15:51.96#ibcon#read 4, iclass 11, count 2 2006.245.08:15:51.96#ibcon#about to read 5, iclass 11, count 2 2006.245.08:15:51.96#ibcon#read 5, iclass 11, count 2 2006.245.08:15:51.96#ibcon#about to read 6, iclass 11, count 2 2006.245.08:15:51.96#ibcon#read 6, iclass 11, count 2 2006.245.08:15:51.96#ibcon#end of sib2, iclass 11, count 2 2006.245.08:15:51.96#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:15:51.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:15:51.96#ibcon#[25=AT04-07\r\n] 2006.245.08:15:51.96#ibcon#*before write, iclass 11, count 2 2006.245.08:15:51.96#ibcon#enter sib2, iclass 11, count 2 2006.245.08:15:51.96#ibcon#flushed, iclass 11, count 2 2006.245.08:15:51.96#ibcon#about to write, iclass 11, count 2 2006.245.08:15:51.96#ibcon#wrote, iclass 11, count 2 2006.245.08:15:51.96#ibcon#about to read 3, iclass 11, count 2 2006.245.08:15:51.99#ibcon#read 3, iclass 11, count 2 2006.245.08:15:51.99#ibcon#about to read 4, iclass 11, count 2 2006.245.08:15:51.99#ibcon#read 4, iclass 11, count 2 2006.245.08:15:51.99#ibcon#about to read 5, iclass 11, count 2 2006.245.08:15:51.99#ibcon#read 5, iclass 11, count 2 2006.245.08:15:51.99#ibcon#about to read 6, iclass 11, count 2 2006.245.08:15:51.99#ibcon#read 6, iclass 11, count 2 2006.245.08:15:51.99#ibcon#end of sib2, iclass 11, count 2 2006.245.08:15:51.99#ibcon#*after write, iclass 11, count 2 2006.245.08:15:51.99#ibcon#*before return 0, iclass 11, count 2 2006.245.08:15:51.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:51.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:51.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:15:51.99#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:51.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:52.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:52.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:52.11#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:15:52.11#ibcon#first serial, iclass 11, count 0 2006.245.08:15:52.11#ibcon#enter sib2, iclass 11, count 0 2006.245.08:15:52.11#ibcon#flushed, iclass 11, count 0 2006.245.08:15:52.11#ibcon#about to write, iclass 11, count 0 2006.245.08:15:52.11#ibcon#wrote, iclass 11, count 0 2006.245.08:15:52.11#ibcon#about to read 3, iclass 11, count 0 2006.245.08:15:52.13#ibcon#read 3, iclass 11, count 0 2006.245.08:15:52.13#ibcon#about to read 4, iclass 11, count 0 2006.245.08:15:52.13#ibcon#read 4, iclass 11, count 0 2006.245.08:15:52.13#ibcon#about to read 5, iclass 11, count 0 2006.245.08:15:52.13#ibcon#read 5, iclass 11, count 0 2006.245.08:15:52.13#ibcon#about to read 6, iclass 11, count 0 2006.245.08:15:52.13#ibcon#read 6, iclass 11, count 0 2006.245.08:15:52.13#ibcon#end of sib2, iclass 11, count 0 2006.245.08:15:52.13#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:15:52.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:15:52.13#ibcon#[25=USB\r\n] 2006.245.08:15:52.13#ibcon#*before write, iclass 11, count 0 2006.245.08:15:52.13#ibcon#enter sib2, iclass 11, count 0 2006.245.08:15:52.13#ibcon#flushed, iclass 11, count 0 2006.245.08:15:52.13#ibcon#about to write, iclass 11, count 0 2006.245.08:15:52.13#ibcon#wrote, iclass 11, count 0 2006.245.08:15:52.13#ibcon#about to read 3, iclass 11, count 0 2006.245.08:15:52.16#ibcon#read 3, iclass 11, count 0 2006.245.08:15:52.16#ibcon#about to read 4, iclass 11, count 0 2006.245.08:15:52.16#ibcon#read 4, iclass 11, count 0 2006.245.08:15:52.16#ibcon#about to read 5, iclass 11, count 0 2006.245.08:15:52.16#ibcon#read 5, iclass 11, count 0 2006.245.08:15:52.16#ibcon#about to read 6, iclass 11, count 0 2006.245.08:15:52.16#ibcon#read 6, iclass 11, count 0 2006.245.08:15:52.16#ibcon#end of sib2, iclass 11, count 0 2006.245.08:15:52.16#ibcon#*after write, iclass 11, count 0 2006.245.08:15:52.16#ibcon#*before return 0, iclass 11, count 0 2006.245.08:15:52.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:52.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:52.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:15:52.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:15:52.16$vc4f8/valo=5,652.99 2006.245.08:15:52.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:15:52.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:15:52.16#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:52.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:52.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:52.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:52.16#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:15:52.16#ibcon#first serial, iclass 13, count 0 2006.245.08:15:52.16#ibcon#enter sib2, iclass 13, count 0 2006.245.08:15:52.16#ibcon#flushed, iclass 13, count 0 2006.245.08:15:52.16#ibcon#about to write, iclass 13, count 0 2006.245.08:15:52.16#ibcon#wrote, iclass 13, count 0 2006.245.08:15:52.16#ibcon#about to read 3, iclass 13, count 0 2006.245.08:15:52.18#ibcon#read 3, iclass 13, count 0 2006.245.08:15:52.18#ibcon#about to read 4, iclass 13, count 0 2006.245.08:15:52.18#ibcon#read 4, iclass 13, count 0 2006.245.08:15:52.18#ibcon#about to read 5, iclass 13, count 0 2006.245.08:15:52.18#ibcon#read 5, iclass 13, count 0 2006.245.08:15:52.18#ibcon#about to read 6, iclass 13, count 0 2006.245.08:15:52.18#ibcon#read 6, iclass 13, count 0 2006.245.08:15:52.18#ibcon#end of sib2, iclass 13, count 0 2006.245.08:15:52.18#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:15:52.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:15:52.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:15:52.18#ibcon#*before write, iclass 13, count 0 2006.245.08:15:52.18#ibcon#enter sib2, iclass 13, count 0 2006.245.08:15:52.18#ibcon#flushed, iclass 13, count 0 2006.245.08:15:52.18#ibcon#about to write, iclass 13, count 0 2006.245.08:15:52.18#ibcon#wrote, iclass 13, count 0 2006.245.08:15:52.18#ibcon#about to read 3, iclass 13, count 0 2006.245.08:15:52.22#ibcon#read 3, iclass 13, count 0 2006.245.08:15:52.22#ibcon#about to read 4, iclass 13, count 0 2006.245.08:15:52.22#ibcon#read 4, iclass 13, count 0 2006.245.08:15:52.22#ibcon#about to read 5, iclass 13, count 0 2006.245.08:15:52.22#ibcon#read 5, iclass 13, count 0 2006.245.08:15:52.22#ibcon#about to read 6, iclass 13, count 0 2006.245.08:15:52.22#ibcon#read 6, iclass 13, count 0 2006.245.08:15:52.22#ibcon#end of sib2, iclass 13, count 0 2006.245.08:15:52.22#ibcon#*after write, iclass 13, count 0 2006.245.08:15:52.22#ibcon#*before return 0, iclass 13, count 0 2006.245.08:15:52.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:52.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:52.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:15:52.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:15:52.22$vc4f8/va=5,7 2006.245.08:15:52.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:15:52.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:15:52.22#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:52.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:15:52.25#abcon#<5=/05 3.4 5.1 26.83 751004.5\r\n> 2006.245.08:15:52.27#abcon#{5=INTERFACE CLEAR} 2006.245.08:15:52.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:15:52.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:15:52.28#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:15:52.28#ibcon#first serial, iclass 16, count 2 2006.245.08:15:52.28#ibcon#enter sib2, iclass 16, count 2 2006.245.08:15:52.28#ibcon#flushed, iclass 16, count 2 2006.245.08:15:52.28#ibcon#about to write, iclass 16, count 2 2006.245.08:15:52.28#ibcon#wrote, iclass 16, count 2 2006.245.08:15:52.28#ibcon#about to read 3, iclass 16, count 2 2006.245.08:15:52.30#ibcon#read 3, iclass 16, count 2 2006.245.08:15:52.30#ibcon#about to read 4, iclass 16, count 2 2006.245.08:15:52.30#ibcon#read 4, iclass 16, count 2 2006.245.08:15:52.30#ibcon#about to read 5, iclass 16, count 2 2006.245.08:15:52.30#ibcon#read 5, iclass 16, count 2 2006.245.08:15:52.30#ibcon#about to read 6, iclass 16, count 2 2006.245.08:15:52.30#ibcon#read 6, iclass 16, count 2 2006.245.08:15:52.30#ibcon#end of sib2, iclass 16, count 2 2006.245.08:15:52.30#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:15:52.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:15:52.30#ibcon#[25=AT05-07\r\n] 2006.245.08:15:52.30#ibcon#*before write, iclass 16, count 2 2006.245.08:15:52.30#ibcon#enter sib2, iclass 16, count 2 2006.245.08:15:52.30#ibcon#flushed, iclass 16, count 2 2006.245.08:15:52.30#ibcon#about to write, iclass 16, count 2 2006.245.08:15:52.30#ibcon#wrote, iclass 16, count 2 2006.245.08:15:52.30#ibcon#about to read 3, iclass 16, count 2 2006.245.08:15:52.33#abcon#[5=S1D000X0/0*\r\n] 2006.245.08:15:52.33#ibcon#read 3, iclass 16, count 2 2006.245.08:15:52.33#ibcon#about to read 4, iclass 16, count 2 2006.245.08:15:52.33#ibcon#read 4, iclass 16, count 2 2006.245.08:15:52.33#ibcon#about to read 5, iclass 16, count 2 2006.245.08:15:52.33#ibcon#read 5, iclass 16, count 2 2006.245.08:15:52.33#ibcon#about to read 6, iclass 16, count 2 2006.245.08:15:52.33#ibcon#read 6, iclass 16, count 2 2006.245.08:15:52.33#ibcon#end of sib2, iclass 16, count 2 2006.245.08:15:52.33#ibcon#*after write, iclass 16, count 2 2006.245.08:15:52.33#ibcon#*before return 0, iclass 16, count 2 2006.245.08:15:52.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:15:52.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:15:52.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:15:52.33#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:52.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:15:52.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:15:52.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:15:52.45#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:15:52.45#ibcon#first serial, iclass 16, count 0 2006.245.08:15:52.45#ibcon#enter sib2, iclass 16, count 0 2006.245.08:15:52.45#ibcon#flushed, iclass 16, count 0 2006.245.08:15:52.45#ibcon#about to write, iclass 16, count 0 2006.245.08:15:52.45#ibcon#wrote, iclass 16, count 0 2006.245.08:15:52.45#ibcon#about to read 3, iclass 16, count 0 2006.245.08:15:52.47#ibcon#read 3, iclass 16, count 0 2006.245.08:15:52.47#ibcon#about to read 4, iclass 16, count 0 2006.245.08:15:52.47#ibcon#read 4, iclass 16, count 0 2006.245.08:15:52.47#ibcon#about to read 5, iclass 16, count 0 2006.245.08:15:52.47#ibcon#read 5, iclass 16, count 0 2006.245.08:15:52.47#ibcon#about to read 6, iclass 16, count 0 2006.245.08:15:52.47#ibcon#read 6, iclass 16, count 0 2006.245.08:15:52.47#ibcon#end of sib2, iclass 16, count 0 2006.245.08:15:52.47#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:15:52.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:15:52.47#ibcon#[25=USB\r\n] 2006.245.08:15:52.47#ibcon#*before write, iclass 16, count 0 2006.245.08:15:52.47#ibcon#enter sib2, iclass 16, count 0 2006.245.08:15:52.47#ibcon#flushed, iclass 16, count 0 2006.245.08:15:52.47#ibcon#about to write, iclass 16, count 0 2006.245.08:15:52.47#ibcon#wrote, iclass 16, count 0 2006.245.08:15:52.47#ibcon#about to read 3, iclass 16, count 0 2006.245.08:15:52.50#ibcon#read 3, iclass 16, count 0 2006.245.08:15:52.50#ibcon#about to read 4, iclass 16, count 0 2006.245.08:15:52.50#ibcon#read 4, iclass 16, count 0 2006.245.08:15:52.50#ibcon#about to read 5, iclass 16, count 0 2006.245.08:15:52.50#ibcon#read 5, iclass 16, count 0 2006.245.08:15:52.50#ibcon#about to read 6, iclass 16, count 0 2006.245.08:15:52.50#ibcon#read 6, iclass 16, count 0 2006.245.08:15:52.50#ibcon#end of sib2, iclass 16, count 0 2006.245.08:15:52.50#ibcon#*after write, iclass 16, count 0 2006.245.08:15:52.50#ibcon#*before return 0, iclass 16, count 0 2006.245.08:15:52.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:15:52.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:15:52.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:15:52.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:15:52.50$vc4f8/valo=6,772.99 2006.245.08:15:52.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:15:52.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:15:52.50#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:52.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:52.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:52.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:52.50#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:15:52.50#ibcon#first serial, iclass 21, count 0 2006.245.08:15:52.50#ibcon#enter sib2, iclass 21, count 0 2006.245.08:15:52.50#ibcon#flushed, iclass 21, count 0 2006.245.08:15:52.50#ibcon#about to write, iclass 21, count 0 2006.245.08:15:52.50#ibcon#wrote, iclass 21, count 0 2006.245.08:15:52.50#ibcon#about to read 3, iclass 21, count 0 2006.245.08:15:52.52#ibcon#read 3, iclass 21, count 0 2006.245.08:15:52.52#ibcon#about to read 4, iclass 21, count 0 2006.245.08:15:52.52#ibcon#read 4, iclass 21, count 0 2006.245.08:15:52.52#ibcon#about to read 5, iclass 21, count 0 2006.245.08:15:52.52#ibcon#read 5, iclass 21, count 0 2006.245.08:15:52.52#ibcon#about to read 6, iclass 21, count 0 2006.245.08:15:52.52#ibcon#read 6, iclass 21, count 0 2006.245.08:15:52.52#ibcon#end of sib2, iclass 21, count 0 2006.245.08:15:52.52#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:15:52.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:15:52.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:15:52.52#ibcon#*before write, iclass 21, count 0 2006.245.08:15:52.52#ibcon#enter sib2, iclass 21, count 0 2006.245.08:15:52.52#ibcon#flushed, iclass 21, count 0 2006.245.08:15:52.52#ibcon#about to write, iclass 21, count 0 2006.245.08:15:52.52#ibcon#wrote, iclass 21, count 0 2006.245.08:15:52.52#ibcon#about to read 3, iclass 21, count 0 2006.245.08:15:52.56#ibcon#read 3, iclass 21, count 0 2006.245.08:15:52.56#ibcon#about to read 4, iclass 21, count 0 2006.245.08:15:52.56#ibcon#read 4, iclass 21, count 0 2006.245.08:15:52.56#ibcon#about to read 5, iclass 21, count 0 2006.245.08:15:52.56#ibcon#read 5, iclass 21, count 0 2006.245.08:15:52.56#ibcon#about to read 6, iclass 21, count 0 2006.245.08:15:52.56#ibcon#read 6, iclass 21, count 0 2006.245.08:15:52.56#ibcon#end of sib2, iclass 21, count 0 2006.245.08:15:52.56#ibcon#*after write, iclass 21, count 0 2006.245.08:15:52.56#ibcon#*before return 0, iclass 21, count 0 2006.245.08:15:52.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:52.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:52.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:15:52.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:15:52.56$vc4f8/va=6,7 2006.245.08:15:52.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.08:15:52.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.08:15:52.56#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:52.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:15:52.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:15:52.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:15:52.62#ibcon#enter wrdev, iclass 23, count 2 2006.245.08:15:52.62#ibcon#first serial, iclass 23, count 2 2006.245.08:15:52.62#ibcon#enter sib2, iclass 23, count 2 2006.245.08:15:52.62#ibcon#flushed, iclass 23, count 2 2006.245.08:15:52.62#ibcon#about to write, iclass 23, count 2 2006.245.08:15:52.63#ibcon#wrote, iclass 23, count 2 2006.245.08:15:52.63#ibcon#about to read 3, iclass 23, count 2 2006.245.08:15:52.64#ibcon#read 3, iclass 23, count 2 2006.245.08:15:52.64#ibcon#about to read 4, iclass 23, count 2 2006.245.08:15:52.64#ibcon#read 4, iclass 23, count 2 2006.245.08:15:52.64#ibcon#about to read 5, iclass 23, count 2 2006.245.08:15:52.64#ibcon#read 5, iclass 23, count 2 2006.245.08:15:52.64#ibcon#about to read 6, iclass 23, count 2 2006.245.08:15:52.64#ibcon#read 6, iclass 23, count 2 2006.245.08:15:52.64#ibcon#end of sib2, iclass 23, count 2 2006.245.08:15:52.64#ibcon#*mode == 0, iclass 23, count 2 2006.245.08:15:52.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.08:15:52.64#ibcon#[25=AT06-07\r\n] 2006.245.08:15:52.64#ibcon#*before write, iclass 23, count 2 2006.245.08:15:52.64#ibcon#enter sib2, iclass 23, count 2 2006.245.08:15:52.64#ibcon#flushed, iclass 23, count 2 2006.245.08:15:52.64#ibcon#about to write, iclass 23, count 2 2006.245.08:15:52.64#ibcon#wrote, iclass 23, count 2 2006.245.08:15:52.64#ibcon#about to read 3, iclass 23, count 2 2006.245.08:15:52.67#ibcon#read 3, iclass 23, count 2 2006.245.08:15:52.67#ibcon#about to read 4, iclass 23, count 2 2006.245.08:15:52.67#ibcon#read 4, iclass 23, count 2 2006.245.08:15:52.67#ibcon#about to read 5, iclass 23, count 2 2006.245.08:15:52.67#ibcon#read 5, iclass 23, count 2 2006.245.08:15:52.67#ibcon#about to read 6, iclass 23, count 2 2006.245.08:15:52.67#ibcon#read 6, iclass 23, count 2 2006.245.08:15:52.67#ibcon#end of sib2, iclass 23, count 2 2006.245.08:15:52.67#ibcon#*after write, iclass 23, count 2 2006.245.08:15:52.67#ibcon#*before return 0, iclass 23, count 2 2006.245.08:15:52.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:15:52.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:15:52.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.08:15:52.67#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:52.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:15:52.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:15:52.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:15:52.79#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:15:52.79#ibcon#first serial, iclass 23, count 0 2006.245.08:15:52.79#ibcon#enter sib2, iclass 23, count 0 2006.245.08:15:52.79#ibcon#flushed, iclass 23, count 0 2006.245.08:15:52.79#ibcon#about to write, iclass 23, count 0 2006.245.08:15:52.79#ibcon#wrote, iclass 23, count 0 2006.245.08:15:52.79#ibcon#about to read 3, iclass 23, count 0 2006.245.08:15:52.81#ibcon#read 3, iclass 23, count 0 2006.245.08:15:52.81#ibcon#about to read 4, iclass 23, count 0 2006.245.08:15:52.81#ibcon#read 4, iclass 23, count 0 2006.245.08:15:52.81#ibcon#about to read 5, iclass 23, count 0 2006.245.08:15:52.81#ibcon#read 5, iclass 23, count 0 2006.245.08:15:52.81#ibcon#about to read 6, iclass 23, count 0 2006.245.08:15:52.81#ibcon#read 6, iclass 23, count 0 2006.245.08:15:52.81#ibcon#end of sib2, iclass 23, count 0 2006.245.08:15:52.81#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:15:52.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:15:52.81#ibcon#[25=USB\r\n] 2006.245.08:15:52.81#ibcon#*before write, iclass 23, count 0 2006.245.08:15:52.81#ibcon#enter sib2, iclass 23, count 0 2006.245.08:15:52.81#ibcon#flushed, iclass 23, count 0 2006.245.08:15:52.81#ibcon#about to write, iclass 23, count 0 2006.245.08:15:52.81#ibcon#wrote, iclass 23, count 0 2006.245.08:15:52.81#ibcon#about to read 3, iclass 23, count 0 2006.245.08:15:52.84#ibcon#read 3, iclass 23, count 0 2006.245.08:15:52.84#ibcon#about to read 4, iclass 23, count 0 2006.245.08:15:52.84#ibcon#read 4, iclass 23, count 0 2006.245.08:15:52.84#ibcon#about to read 5, iclass 23, count 0 2006.245.08:15:52.84#ibcon#read 5, iclass 23, count 0 2006.245.08:15:52.84#ibcon#about to read 6, iclass 23, count 0 2006.245.08:15:52.84#ibcon#read 6, iclass 23, count 0 2006.245.08:15:52.84#ibcon#end of sib2, iclass 23, count 0 2006.245.08:15:52.84#ibcon#*after write, iclass 23, count 0 2006.245.08:15:52.84#ibcon#*before return 0, iclass 23, count 0 2006.245.08:15:52.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:15:52.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:15:52.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:15:52.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:15:52.84$vc4f8/valo=7,832.99 2006.245.08:15:52.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.08:15:52.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.08:15:52.84#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:52.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:15:52.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:15:52.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:15:52.84#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:15:52.84#ibcon#first serial, iclass 25, count 0 2006.245.08:15:52.84#ibcon#enter sib2, iclass 25, count 0 2006.245.08:15:52.84#ibcon#flushed, iclass 25, count 0 2006.245.08:15:52.84#ibcon#about to write, iclass 25, count 0 2006.245.08:15:52.84#ibcon#wrote, iclass 25, count 0 2006.245.08:15:52.84#ibcon#about to read 3, iclass 25, count 0 2006.245.08:15:52.86#ibcon#read 3, iclass 25, count 0 2006.245.08:15:52.86#ibcon#about to read 4, iclass 25, count 0 2006.245.08:15:52.86#ibcon#read 4, iclass 25, count 0 2006.245.08:15:52.86#ibcon#about to read 5, iclass 25, count 0 2006.245.08:15:52.86#ibcon#read 5, iclass 25, count 0 2006.245.08:15:52.86#ibcon#about to read 6, iclass 25, count 0 2006.245.08:15:52.86#ibcon#read 6, iclass 25, count 0 2006.245.08:15:52.86#ibcon#end of sib2, iclass 25, count 0 2006.245.08:15:52.86#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:15:52.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:15:52.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:15:52.86#ibcon#*before write, iclass 25, count 0 2006.245.08:15:52.86#ibcon#enter sib2, iclass 25, count 0 2006.245.08:15:52.86#ibcon#flushed, iclass 25, count 0 2006.245.08:15:52.86#ibcon#about to write, iclass 25, count 0 2006.245.08:15:52.86#ibcon#wrote, iclass 25, count 0 2006.245.08:15:52.86#ibcon#about to read 3, iclass 25, count 0 2006.245.08:15:52.90#ibcon#read 3, iclass 25, count 0 2006.245.08:15:52.90#ibcon#about to read 4, iclass 25, count 0 2006.245.08:15:52.90#ibcon#read 4, iclass 25, count 0 2006.245.08:15:52.90#ibcon#about to read 5, iclass 25, count 0 2006.245.08:15:52.90#ibcon#read 5, iclass 25, count 0 2006.245.08:15:52.90#ibcon#about to read 6, iclass 25, count 0 2006.245.08:15:52.90#ibcon#read 6, iclass 25, count 0 2006.245.08:15:52.90#ibcon#end of sib2, iclass 25, count 0 2006.245.08:15:52.90#ibcon#*after write, iclass 25, count 0 2006.245.08:15:52.90#ibcon#*before return 0, iclass 25, count 0 2006.245.08:15:52.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:15:52.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:15:52.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:15:52.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:15:52.90$vc4f8/va=7,7 2006.245.08:15:52.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.08:15:52.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.08:15:52.90#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:52.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:15:52.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:15:52.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:15:52.96#ibcon#enter wrdev, iclass 27, count 2 2006.245.08:15:52.96#ibcon#first serial, iclass 27, count 2 2006.245.08:15:52.96#ibcon#enter sib2, iclass 27, count 2 2006.245.08:15:52.96#ibcon#flushed, iclass 27, count 2 2006.245.08:15:52.96#ibcon#about to write, iclass 27, count 2 2006.245.08:15:52.96#ibcon#wrote, iclass 27, count 2 2006.245.08:15:52.96#ibcon#about to read 3, iclass 27, count 2 2006.245.08:15:52.98#ibcon#read 3, iclass 27, count 2 2006.245.08:15:52.98#ibcon#about to read 4, iclass 27, count 2 2006.245.08:15:52.98#ibcon#read 4, iclass 27, count 2 2006.245.08:15:52.98#ibcon#about to read 5, iclass 27, count 2 2006.245.08:15:52.98#ibcon#read 5, iclass 27, count 2 2006.245.08:15:52.98#ibcon#about to read 6, iclass 27, count 2 2006.245.08:15:52.98#ibcon#read 6, iclass 27, count 2 2006.245.08:15:52.98#ibcon#end of sib2, iclass 27, count 2 2006.245.08:15:52.98#ibcon#*mode == 0, iclass 27, count 2 2006.245.08:15:52.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.08:15:52.98#ibcon#[25=AT07-07\r\n] 2006.245.08:15:52.98#ibcon#*before write, iclass 27, count 2 2006.245.08:15:52.98#ibcon#enter sib2, iclass 27, count 2 2006.245.08:15:52.98#ibcon#flushed, iclass 27, count 2 2006.245.08:15:52.98#ibcon#about to write, iclass 27, count 2 2006.245.08:15:52.98#ibcon#wrote, iclass 27, count 2 2006.245.08:15:52.98#ibcon#about to read 3, iclass 27, count 2 2006.245.08:15:53.01#ibcon#read 3, iclass 27, count 2 2006.245.08:15:53.01#ibcon#about to read 4, iclass 27, count 2 2006.245.08:15:53.01#ibcon#read 4, iclass 27, count 2 2006.245.08:15:53.01#ibcon#about to read 5, iclass 27, count 2 2006.245.08:15:53.01#ibcon#read 5, iclass 27, count 2 2006.245.08:15:53.01#ibcon#about to read 6, iclass 27, count 2 2006.245.08:15:53.01#ibcon#read 6, iclass 27, count 2 2006.245.08:15:53.01#ibcon#end of sib2, iclass 27, count 2 2006.245.08:15:53.01#ibcon#*after write, iclass 27, count 2 2006.245.08:15:53.01#ibcon#*before return 0, iclass 27, count 2 2006.245.08:15:53.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:15:53.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:15:53.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.08:15:53.01#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:53.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:15:53.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:15:53.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:15:53.13#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:15:53.13#ibcon#first serial, iclass 27, count 0 2006.245.08:15:53.13#ibcon#enter sib2, iclass 27, count 0 2006.245.08:15:53.13#ibcon#flushed, iclass 27, count 0 2006.245.08:15:53.13#ibcon#about to write, iclass 27, count 0 2006.245.08:15:53.13#ibcon#wrote, iclass 27, count 0 2006.245.08:15:53.13#ibcon#about to read 3, iclass 27, count 0 2006.245.08:15:53.15#ibcon#read 3, iclass 27, count 0 2006.245.08:15:53.15#ibcon#about to read 4, iclass 27, count 0 2006.245.08:15:53.15#ibcon#read 4, iclass 27, count 0 2006.245.08:15:53.15#ibcon#about to read 5, iclass 27, count 0 2006.245.08:15:53.15#ibcon#read 5, iclass 27, count 0 2006.245.08:15:53.15#ibcon#about to read 6, iclass 27, count 0 2006.245.08:15:53.15#ibcon#read 6, iclass 27, count 0 2006.245.08:15:53.15#ibcon#end of sib2, iclass 27, count 0 2006.245.08:15:53.15#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:15:53.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:15:53.15#ibcon#[25=USB\r\n] 2006.245.08:15:53.15#ibcon#*before write, iclass 27, count 0 2006.245.08:15:53.15#ibcon#enter sib2, iclass 27, count 0 2006.245.08:15:53.15#ibcon#flushed, iclass 27, count 0 2006.245.08:15:53.15#ibcon#about to write, iclass 27, count 0 2006.245.08:15:53.15#ibcon#wrote, iclass 27, count 0 2006.245.08:15:53.15#ibcon#about to read 3, iclass 27, count 0 2006.245.08:15:53.18#ibcon#read 3, iclass 27, count 0 2006.245.08:15:53.18#ibcon#about to read 4, iclass 27, count 0 2006.245.08:15:53.18#ibcon#read 4, iclass 27, count 0 2006.245.08:15:53.18#ibcon#about to read 5, iclass 27, count 0 2006.245.08:15:53.18#ibcon#read 5, iclass 27, count 0 2006.245.08:15:53.18#ibcon#about to read 6, iclass 27, count 0 2006.245.08:15:53.18#ibcon#read 6, iclass 27, count 0 2006.245.08:15:53.18#ibcon#end of sib2, iclass 27, count 0 2006.245.08:15:53.18#ibcon#*after write, iclass 27, count 0 2006.245.08:15:53.18#ibcon#*before return 0, iclass 27, count 0 2006.245.08:15:53.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:15:53.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:15:53.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:15:53.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:15:53.18$vc4f8/valo=8,852.99 2006.245.08:15:53.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.08:15:53.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.08:15:53.18#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:53.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:15:53.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:15:53.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:15:53.18#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:15:53.18#ibcon#first serial, iclass 29, count 0 2006.245.08:15:53.18#ibcon#enter sib2, iclass 29, count 0 2006.245.08:15:53.18#ibcon#flushed, iclass 29, count 0 2006.245.08:15:53.18#ibcon#about to write, iclass 29, count 0 2006.245.08:15:53.18#ibcon#wrote, iclass 29, count 0 2006.245.08:15:53.18#ibcon#about to read 3, iclass 29, count 0 2006.245.08:15:53.20#ibcon#read 3, iclass 29, count 0 2006.245.08:15:53.20#ibcon#about to read 4, iclass 29, count 0 2006.245.08:15:53.20#ibcon#read 4, iclass 29, count 0 2006.245.08:15:53.20#ibcon#about to read 5, iclass 29, count 0 2006.245.08:15:53.20#ibcon#read 5, iclass 29, count 0 2006.245.08:15:53.20#ibcon#about to read 6, iclass 29, count 0 2006.245.08:15:53.20#ibcon#read 6, iclass 29, count 0 2006.245.08:15:53.20#ibcon#end of sib2, iclass 29, count 0 2006.245.08:15:53.20#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:15:53.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:15:53.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:15:53.20#ibcon#*before write, iclass 29, count 0 2006.245.08:15:53.20#ibcon#enter sib2, iclass 29, count 0 2006.245.08:15:53.20#ibcon#flushed, iclass 29, count 0 2006.245.08:15:53.20#ibcon#about to write, iclass 29, count 0 2006.245.08:15:53.20#ibcon#wrote, iclass 29, count 0 2006.245.08:15:53.20#ibcon#about to read 3, iclass 29, count 0 2006.245.08:15:53.24#ibcon#read 3, iclass 29, count 0 2006.245.08:15:53.24#ibcon#about to read 4, iclass 29, count 0 2006.245.08:15:53.24#ibcon#read 4, iclass 29, count 0 2006.245.08:15:53.24#ibcon#about to read 5, iclass 29, count 0 2006.245.08:15:53.24#ibcon#read 5, iclass 29, count 0 2006.245.08:15:53.24#ibcon#about to read 6, iclass 29, count 0 2006.245.08:15:53.24#ibcon#read 6, iclass 29, count 0 2006.245.08:15:53.24#ibcon#end of sib2, iclass 29, count 0 2006.245.08:15:53.24#ibcon#*after write, iclass 29, count 0 2006.245.08:15:53.24#ibcon#*before return 0, iclass 29, count 0 2006.245.08:15:53.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:15:53.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:15:53.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:15:53.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:15:53.24$vc4f8/va=8,8 2006.245.08:15:53.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.08:15:53.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.08:15:53.24#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:53.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:15:53.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:15:53.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:15:53.30#ibcon#enter wrdev, iclass 31, count 2 2006.245.08:15:53.30#ibcon#first serial, iclass 31, count 2 2006.245.08:15:53.30#ibcon#enter sib2, iclass 31, count 2 2006.245.08:15:53.30#ibcon#flushed, iclass 31, count 2 2006.245.08:15:53.30#ibcon#about to write, iclass 31, count 2 2006.245.08:15:53.31#ibcon#wrote, iclass 31, count 2 2006.245.08:15:53.31#ibcon#about to read 3, iclass 31, count 2 2006.245.08:15:53.32#ibcon#read 3, iclass 31, count 2 2006.245.08:15:53.32#ibcon#about to read 4, iclass 31, count 2 2006.245.08:15:53.32#ibcon#read 4, iclass 31, count 2 2006.245.08:15:53.32#ibcon#about to read 5, iclass 31, count 2 2006.245.08:15:53.32#ibcon#read 5, iclass 31, count 2 2006.245.08:15:53.32#ibcon#about to read 6, iclass 31, count 2 2006.245.08:15:53.32#ibcon#read 6, iclass 31, count 2 2006.245.08:15:53.32#ibcon#end of sib2, iclass 31, count 2 2006.245.08:15:53.32#ibcon#*mode == 0, iclass 31, count 2 2006.245.08:15:53.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.08:15:53.32#ibcon#[25=AT08-08\r\n] 2006.245.08:15:53.32#ibcon#*before write, iclass 31, count 2 2006.245.08:15:53.32#ibcon#enter sib2, iclass 31, count 2 2006.245.08:15:53.32#ibcon#flushed, iclass 31, count 2 2006.245.08:15:53.32#ibcon#about to write, iclass 31, count 2 2006.245.08:15:53.32#ibcon#wrote, iclass 31, count 2 2006.245.08:15:53.32#ibcon#about to read 3, iclass 31, count 2 2006.245.08:15:53.35#ibcon#read 3, iclass 31, count 2 2006.245.08:15:53.35#ibcon#about to read 4, iclass 31, count 2 2006.245.08:15:53.35#ibcon#read 4, iclass 31, count 2 2006.245.08:15:53.35#ibcon#about to read 5, iclass 31, count 2 2006.245.08:15:53.35#ibcon#read 5, iclass 31, count 2 2006.245.08:15:53.35#ibcon#about to read 6, iclass 31, count 2 2006.245.08:15:53.35#ibcon#read 6, iclass 31, count 2 2006.245.08:15:53.35#ibcon#end of sib2, iclass 31, count 2 2006.245.08:15:53.35#ibcon#*after write, iclass 31, count 2 2006.245.08:15:53.35#ibcon#*before return 0, iclass 31, count 2 2006.245.08:15:53.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:15:53.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:15:53.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.08:15:53.35#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:53.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:15:53.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:15:53.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:15:53.47#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:15:53.47#ibcon#first serial, iclass 31, count 0 2006.245.08:15:53.47#ibcon#enter sib2, iclass 31, count 0 2006.245.08:15:53.47#ibcon#flushed, iclass 31, count 0 2006.245.08:15:53.47#ibcon#about to write, iclass 31, count 0 2006.245.08:15:53.47#ibcon#wrote, iclass 31, count 0 2006.245.08:15:53.47#ibcon#about to read 3, iclass 31, count 0 2006.245.08:15:53.49#ibcon#read 3, iclass 31, count 0 2006.245.08:15:53.49#ibcon#about to read 4, iclass 31, count 0 2006.245.08:15:53.49#ibcon#read 4, iclass 31, count 0 2006.245.08:15:53.49#ibcon#about to read 5, iclass 31, count 0 2006.245.08:15:53.49#ibcon#read 5, iclass 31, count 0 2006.245.08:15:53.49#ibcon#about to read 6, iclass 31, count 0 2006.245.08:15:53.49#ibcon#read 6, iclass 31, count 0 2006.245.08:15:53.49#ibcon#end of sib2, iclass 31, count 0 2006.245.08:15:53.49#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:15:53.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:15:53.49#ibcon#[25=USB\r\n] 2006.245.08:15:53.49#ibcon#*before write, iclass 31, count 0 2006.245.08:15:53.49#ibcon#enter sib2, iclass 31, count 0 2006.245.08:15:53.49#ibcon#flushed, iclass 31, count 0 2006.245.08:15:53.49#ibcon#about to write, iclass 31, count 0 2006.245.08:15:53.49#ibcon#wrote, iclass 31, count 0 2006.245.08:15:53.49#ibcon#about to read 3, iclass 31, count 0 2006.245.08:15:53.52#ibcon#read 3, iclass 31, count 0 2006.245.08:15:53.52#ibcon#about to read 4, iclass 31, count 0 2006.245.08:15:53.52#ibcon#read 4, iclass 31, count 0 2006.245.08:15:53.52#ibcon#about to read 5, iclass 31, count 0 2006.245.08:15:53.52#ibcon#read 5, iclass 31, count 0 2006.245.08:15:53.52#ibcon#about to read 6, iclass 31, count 0 2006.245.08:15:53.52#ibcon#read 6, iclass 31, count 0 2006.245.08:15:53.52#ibcon#end of sib2, iclass 31, count 0 2006.245.08:15:53.52#ibcon#*after write, iclass 31, count 0 2006.245.08:15:53.52#ibcon#*before return 0, iclass 31, count 0 2006.245.08:15:53.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:15:53.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:15:53.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:15:53.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:15:53.52$vc4f8/vblo=1,632.99 2006.245.08:15:53.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:15:53.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:15:53.52#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:53.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:53.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:53.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:53.52#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:15:53.52#ibcon#first serial, iclass 33, count 0 2006.245.08:15:53.52#ibcon#enter sib2, iclass 33, count 0 2006.245.08:15:53.52#ibcon#flushed, iclass 33, count 0 2006.245.08:15:53.52#ibcon#about to write, iclass 33, count 0 2006.245.08:15:53.52#ibcon#wrote, iclass 33, count 0 2006.245.08:15:53.52#ibcon#about to read 3, iclass 33, count 0 2006.245.08:15:53.54#ibcon#read 3, iclass 33, count 0 2006.245.08:15:53.54#ibcon#about to read 4, iclass 33, count 0 2006.245.08:15:53.54#ibcon#read 4, iclass 33, count 0 2006.245.08:15:53.54#ibcon#about to read 5, iclass 33, count 0 2006.245.08:15:53.54#ibcon#read 5, iclass 33, count 0 2006.245.08:15:53.54#ibcon#about to read 6, iclass 33, count 0 2006.245.08:15:53.54#ibcon#read 6, iclass 33, count 0 2006.245.08:15:53.54#ibcon#end of sib2, iclass 33, count 0 2006.245.08:15:53.54#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:15:53.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:15:53.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:15:53.54#ibcon#*before write, iclass 33, count 0 2006.245.08:15:53.54#ibcon#enter sib2, iclass 33, count 0 2006.245.08:15:53.54#ibcon#flushed, iclass 33, count 0 2006.245.08:15:53.54#ibcon#about to write, iclass 33, count 0 2006.245.08:15:53.54#ibcon#wrote, iclass 33, count 0 2006.245.08:15:53.54#ibcon#about to read 3, iclass 33, count 0 2006.245.08:15:53.58#ibcon#read 3, iclass 33, count 0 2006.245.08:15:53.58#ibcon#about to read 4, iclass 33, count 0 2006.245.08:15:53.58#ibcon#read 4, iclass 33, count 0 2006.245.08:15:53.58#ibcon#about to read 5, iclass 33, count 0 2006.245.08:15:53.58#ibcon#read 5, iclass 33, count 0 2006.245.08:15:53.58#ibcon#about to read 6, iclass 33, count 0 2006.245.08:15:53.58#ibcon#read 6, iclass 33, count 0 2006.245.08:15:53.58#ibcon#end of sib2, iclass 33, count 0 2006.245.08:15:53.58#ibcon#*after write, iclass 33, count 0 2006.245.08:15:53.58#ibcon#*before return 0, iclass 33, count 0 2006.245.08:15:53.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:53.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:15:53.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:15:53.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:15:53.58$vc4f8/vb=1,4 2006.245.08:15:53.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.245.08:15:53.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.245.08:15:53.58#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:53.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:53.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:53.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:53.58#ibcon#enter wrdev, iclass 35, count 2 2006.245.08:15:53.58#ibcon#first serial, iclass 35, count 2 2006.245.08:15:53.58#ibcon#enter sib2, iclass 35, count 2 2006.245.08:15:53.58#ibcon#flushed, iclass 35, count 2 2006.245.08:15:53.58#ibcon#about to write, iclass 35, count 2 2006.245.08:15:53.58#ibcon#wrote, iclass 35, count 2 2006.245.08:15:53.58#ibcon#about to read 3, iclass 35, count 2 2006.245.08:15:53.60#ibcon#read 3, iclass 35, count 2 2006.245.08:15:53.60#ibcon#about to read 4, iclass 35, count 2 2006.245.08:15:53.60#ibcon#read 4, iclass 35, count 2 2006.245.08:15:53.60#ibcon#about to read 5, iclass 35, count 2 2006.245.08:15:53.60#ibcon#read 5, iclass 35, count 2 2006.245.08:15:53.60#ibcon#about to read 6, iclass 35, count 2 2006.245.08:15:53.60#ibcon#read 6, iclass 35, count 2 2006.245.08:15:53.60#ibcon#end of sib2, iclass 35, count 2 2006.245.08:15:53.60#ibcon#*mode == 0, iclass 35, count 2 2006.245.08:15:53.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.245.08:15:53.60#ibcon#[27=AT01-04\r\n] 2006.245.08:15:53.60#ibcon#*before write, iclass 35, count 2 2006.245.08:15:53.60#ibcon#enter sib2, iclass 35, count 2 2006.245.08:15:53.60#ibcon#flushed, iclass 35, count 2 2006.245.08:15:53.60#ibcon#about to write, iclass 35, count 2 2006.245.08:15:53.60#ibcon#wrote, iclass 35, count 2 2006.245.08:15:53.60#ibcon#about to read 3, iclass 35, count 2 2006.245.08:15:53.63#ibcon#read 3, iclass 35, count 2 2006.245.08:15:53.63#ibcon#about to read 4, iclass 35, count 2 2006.245.08:15:53.63#ibcon#read 4, iclass 35, count 2 2006.245.08:15:53.63#ibcon#about to read 5, iclass 35, count 2 2006.245.08:15:53.63#ibcon#read 5, iclass 35, count 2 2006.245.08:15:53.63#ibcon#about to read 6, iclass 35, count 2 2006.245.08:15:53.63#ibcon#read 6, iclass 35, count 2 2006.245.08:15:53.63#ibcon#end of sib2, iclass 35, count 2 2006.245.08:15:53.63#ibcon#*after write, iclass 35, count 2 2006.245.08:15:53.63#ibcon#*before return 0, iclass 35, count 2 2006.245.08:15:53.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:53.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.245.08:15:53.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.245.08:15:53.63#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:53.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:53.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:53.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:53.75#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:15:53.75#ibcon#first serial, iclass 35, count 0 2006.245.08:15:53.75#ibcon#enter sib2, iclass 35, count 0 2006.245.08:15:53.75#ibcon#flushed, iclass 35, count 0 2006.245.08:15:53.75#ibcon#about to write, iclass 35, count 0 2006.245.08:15:53.75#ibcon#wrote, iclass 35, count 0 2006.245.08:15:53.75#ibcon#about to read 3, iclass 35, count 0 2006.245.08:15:53.77#ibcon#read 3, iclass 35, count 0 2006.245.08:15:53.77#ibcon#about to read 4, iclass 35, count 0 2006.245.08:15:53.77#ibcon#read 4, iclass 35, count 0 2006.245.08:15:53.77#ibcon#about to read 5, iclass 35, count 0 2006.245.08:15:53.77#ibcon#read 5, iclass 35, count 0 2006.245.08:15:53.77#ibcon#about to read 6, iclass 35, count 0 2006.245.08:15:53.77#ibcon#read 6, iclass 35, count 0 2006.245.08:15:53.77#ibcon#end of sib2, iclass 35, count 0 2006.245.08:15:53.77#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:15:53.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:15:53.77#ibcon#[27=USB\r\n] 2006.245.08:15:53.77#ibcon#*before write, iclass 35, count 0 2006.245.08:15:53.77#ibcon#enter sib2, iclass 35, count 0 2006.245.08:15:53.77#ibcon#flushed, iclass 35, count 0 2006.245.08:15:53.77#ibcon#about to write, iclass 35, count 0 2006.245.08:15:53.77#ibcon#wrote, iclass 35, count 0 2006.245.08:15:53.77#ibcon#about to read 3, iclass 35, count 0 2006.245.08:15:53.80#ibcon#read 3, iclass 35, count 0 2006.245.08:15:53.80#ibcon#about to read 4, iclass 35, count 0 2006.245.08:15:53.80#ibcon#read 4, iclass 35, count 0 2006.245.08:15:53.80#ibcon#about to read 5, iclass 35, count 0 2006.245.08:15:53.80#ibcon#read 5, iclass 35, count 0 2006.245.08:15:53.80#ibcon#about to read 6, iclass 35, count 0 2006.245.08:15:53.80#ibcon#read 6, iclass 35, count 0 2006.245.08:15:53.80#ibcon#end of sib2, iclass 35, count 0 2006.245.08:15:53.80#ibcon#*after write, iclass 35, count 0 2006.245.08:15:53.80#ibcon#*before return 0, iclass 35, count 0 2006.245.08:15:53.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:53.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.245.08:15:53.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:15:53.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:15:53.80$vc4f8/vblo=2,640.99 2006.245.08:15:53.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.245.08:15:53.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.245.08:15:53.80#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:53.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:53.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:53.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:53.80#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:15:53.80#ibcon#first serial, iclass 37, count 0 2006.245.08:15:53.80#ibcon#enter sib2, iclass 37, count 0 2006.245.08:15:53.80#ibcon#flushed, iclass 37, count 0 2006.245.08:15:53.80#ibcon#about to write, iclass 37, count 0 2006.245.08:15:53.80#ibcon#wrote, iclass 37, count 0 2006.245.08:15:53.80#ibcon#about to read 3, iclass 37, count 0 2006.245.08:15:53.82#ibcon#read 3, iclass 37, count 0 2006.245.08:15:53.82#ibcon#about to read 4, iclass 37, count 0 2006.245.08:15:53.82#ibcon#read 4, iclass 37, count 0 2006.245.08:15:53.82#ibcon#about to read 5, iclass 37, count 0 2006.245.08:15:53.82#ibcon#read 5, iclass 37, count 0 2006.245.08:15:53.82#ibcon#about to read 6, iclass 37, count 0 2006.245.08:15:53.82#ibcon#read 6, iclass 37, count 0 2006.245.08:15:53.82#ibcon#end of sib2, iclass 37, count 0 2006.245.08:15:53.82#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:15:53.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:15:53.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:15:53.82#ibcon#*before write, iclass 37, count 0 2006.245.08:15:53.82#ibcon#enter sib2, iclass 37, count 0 2006.245.08:15:53.82#ibcon#flushed, iclass 37, count 0 2006.245.08:15:53.82#ibcon#about to write, iclass 37, count 0 2006.245.08:15:53.82#ibcon#wrote, iclass 37, count 0 2006.245.08:15:53.82#ibcon#about to read 3, iclass 37, count 0 2006.245.08:15:53.86#ibcon#read 3, iclass 37, count 0 2006.245.08:15:53.86#ibcon#about to read 4, iclass 37, count 0 2006.245.08:15:53.86#ibcon#read 4, iclass 37, count 0 2006.245.08:15:53.86#ibcon#about to read 5, iclass 37, count 0 2006.245.08:15:53.86#ibcon#read 5, iclass 37, count 0 2006.245.08:15:53.86#ibcon#about to read 6, iclass 37, count 0 2006.245.08:15:53.86#ibcon#read 6, iclass 37, count 0 2006.245.08:15:53.86#ibcon#end of sib2, iclass 37, count 0 2006.245.08:15:53.86#ibcon#*after write, iclass 37, count 0 2006.245.08:15:53.86#ibcon#*before return 0, iclass 37, count 0 2006.245.08:15:53.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:53.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.245.08:15:53.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:15:53.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:15:53.86$vc4f8/vb=2,4 2006.245.08:15:53.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.245.08:15:53.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.245.08:15:53.86#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:53.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:53.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:53.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:53.92#ibcon#enter wrdev, iclass 39, count 2 2006.245.08:15:53.92#ibcon#first serial, iclass 39, count 2 2006.245.08:15:53.92#ibcon#enter sib2, iclass 39, count 2 2006.245.08:15:53.92#ibcon#flushed, iclass 39, count 2 2006.245.08:15:53.92#ibcon#about to write, iclass 39, count 2 2006.245.08:15:53.92#ibcon#wrote, iclass 39, count 2 2006.245.08:15:53.92#ibcon#about to read 3, iclass 39, count 2 2006.245.08:15:53.94#ibcon#read 3, iclass 39, count 2 2006.245.08:15:53.94#ibcon#about to read 4, iclass 39, count 2 2006.245.08:15:53.94#ibcon#read 4, iclass 39, count 2 2006.245.08:15:53.94#ibcon#about to read 5, iclass 39, count 2 2006.245.08:15:53.94#ibcon#read 5, iclass 39, count 2 2006.245.08:15:53.94#ibcon#about to read 6, iclass 39, count 2 2006.245.08:15:53.94#ibcon#read 6, iclass 39, count 2 2006.245.08:15:53.94#ibcon#end of sib2, iclass 39, count 2 2006.245.08:15:53.94#ibcon#*mode == 0, iclass 39, count 2 2006.245.08:15:53.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.245.08:15:53.94#ibcon#[27=AT02-04\r\n] 2006.245.08:15:53.94#ibcon#*before write, iclass 39, count 2 2006.245.08:15:53.94#ibcon#enter sib2, iclass 39, count 2 2006.245.08:15:53.94#ibcon#flushed, iclass 39, count 2 2006.245.08:15:53.94#ibcon#about to write, iclass 39, count 2 2006.245.08:15:53.94#ibcon#wrote, iclass 39, count 2 2006.245.08:15:53.94#ibcon#about to read 3, iclass 39, count 2 2006.245.08:15:53.97#ibcon#read 3, iclass 39, count 2 2006.245.08:15:53.97#ibcon#about to read 4, iclass 39, count 2 2006.245.08:15:53.97#ibcon#read 4, iclass 39, count 2 2006.245.08:15:53.97#ibcon#about to read 5, iclass 39, count 2 2006.245.08:15:53.97#ibcon#read 5, iclass 39, count 2 2006.245.08:15:53.97#ibcon#about to read 6, iclass 39, count 2 2006.245.08:15:53.97#ibcon#read 6, iclass 39, count 2 2006.245.08:15:53.97#ibcon#end of sib2, iclass 39, count 2 2006.245.08:15:53.97#ibcon#*after write, iclass 39, count 2 2006.245.08:15:53.97#ibcon#*before return 0, iclass 39, count 2 2006.245.08:15:53.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:53.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.245.08:15:53.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.245.08:15:53.97#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:53.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:54.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:54.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:54.09#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:15:54.09#ibcon#first serial, iclass 39, count 0 2006.245.08:15:54.09#ibcon#enter sib2, iclass 39, count 0 2006.245.08:15:54.09#ibcon#flushed, iclass 39, count 0 2006.245.08:15:54.09#ibcon#about to write, iclass 39, count 0 2006.245.08:15:54.09#ibcon#wrote, iclass 39, count 0 2006.245.08:15:54.09#ibcon#about to read 3, iclass 39, count 0 2006.245.08:15:54.12#ibcon#read 3, iclass 39, count 0 2006.245.08:15:54.12#ibcon#about to read 4, iclass 39, count 0 2006.245.08:15:54.12#ibcon#read 4, iclass 39, count 0 2006.245.08:15:54.12#ibcon#about to read 5, iclass 39, count 0 2006.245.08:15:54.12#ibcon#read 5, iclass 39, count 0 2006.245.08:15:54.12#ibcon#about to read 6, iclass 39, count 0 2006.245.08:15:54.12#ibcon#read 6, iclass 39, count 0 2006.245.08:15:54.12#ibcon#end of sib2, iclass 39, count 0 2006.245.08:15:54.12#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:15:54.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:15:54.12#ibcon#[27=USB\r\n] 2006.245.08:15:54.12#ibcon#*before write, iclass 39, count 0 2006.245.08:15:54.12#ibcon#enter sib2, iclass 39, count 0 2006.245.08:15:54.12#ibcon#flushed, iclass 39, count 0 2006.245.08:15:54.12#ibcon#about to write, iclass 39, count 0 2006.245.08:15:54.12#ibcon#wrote, iclass 39, count 0 2006.245.08:15:54.12#ibcon#about to read 3, iclass 39, count 0 2006.245.08:15:54.15#ibcon#read 3, iclass 39, count 0 2006.245.08:15:54.15#ibcon#about to read 4, iclass 39, count 0 2006.245.08:15:54.15#ibcon#read 4, iclass 39, count 0 2006.245.08:15:54.15#ibcon#about to read 5, iclass 39, count 0 2006.245.08:15:54.15#ibcon#read 5, iclass 39, count 0 2006.245.08:15:54.15#ibcon#about to read 6, iclass 39, count 0 2006.245.08:15:54.15#ibcon#read 6, iclass 39, count 0 2006.245.08:15:54.15#ibcon#end of sib2, iclass 39, count 0 2006.245.08:15:54.15#ibcon#*after write, iclass 39, count 0 2006.245.08:15:54.15#ibcon#*before return 0, iclass 39, count 0 2006.245.08:15:54.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:54.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.245.08:15:54.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:15:54.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:15:54.15$vc4f8/vblo=3,656.99 2006.245.08:15:54.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:15:54.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:15:54.15#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:54.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:54.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:54.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:54.15#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:15:54.15#ibcon#first serial, iclass 3, count 0 2006.245.08:15:54.15#ibcon#enter sib2, iclass 3, count 0 2006.245.08:15:54.15#ibcon#flushed, iclass 3, count 0 2006.245.08:15:54.15#ibcon#about to write, iclass 3, count 0 2006.245.08:15:54.15#ibcon#wrote, iclass 3, count 0 2006.245.08:15:54.15#ibcon#about to read 3, iclass 3, count 0 2006.245.08:15:54.17#ibcon#read 3, iclass 3, count 0 2006.245.08:15:54.17#ibcon#about to read 4, iclass 3, count 0 2006.245.08:15:54.17#ibcon#read 4, iclass 3, count 0 2006.245.08:15:54.17#ibcon#about to read 5, iclass 3, count 0 2006.245.08:15:54.17#ibcon#read 5, iclass 3, count 0 2006.245.08:15:54.17#ibcon#about to read 6, iclass 3, count 0 2006.245.08:15:54.17#ibcon#read 6, iclass 3, count 0 2006.245.08:15:54.17#ibcon#end of sib2, iclass 3, count 0 2006.245.08:15:54.17#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:15:54.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:15:54.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:15:54.17#ibcon#*before write, iclass 3, count 0 2006.245.08:15:54.17#ibcon#enter sib2, iclass 3, count 0 2006.245.08:15:54.17#ibcon#flushed, iclass 3, count 0 2006.245.08:15:54.17#ibcon#about to write, iclass 3, count 0 2006.245.08:15:54.17#ibcon#wrote, iclass 3, count 0 2006.245.08:15:54.17#ibcon#about to read 3, iclass 3, count 0 2006.245.08:15:54.21#ibcon#read 3, iclass 3, count 0 2006.245.08:15:54.21#ibcon#about to read 4, iclass 3, count 0 2006.245.08:15:54.21#ibcon#read 4, iclass 3, count 0 2006.245.08:15:54.21#ibcon#about to read 5, iclass 3, count 0 2006.245.08:15:54.21#ibcon#read 5, iclass 3, count 0 2006.245.08:15:54.21#ibcon#about to read 6, iclass 3, count 0 2006.245.08:15:54.21#ibcon#read 6, iclass 3, count 0 2006.245.08:15:54.21#ibcon#end of sib2, iclass 3, count 0 2006.245.08:15:54.21#ibcon#*after write, iclass 3, count 0 2006.245.08:15:54.21#ibcon#*before return 0, iclass 3, count 0 2006.245.08:15:54.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:54.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:15:54.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:15:54.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:15:54.21$vc4f8/vb=3,4 2006.245.08:15:54.21#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:15:54.21#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:15:54.21#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:54.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:54.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:54.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:54.27#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:15:54.27#ibcon#first serial, iclass 5, count 2 2006.245.08:15:54.27#ibcon#enter sib2, iclass 5, count 2 2006.245.08:15:54.27#ibcon#flushed, iclass 5, count 2 2006.245.08:15:54.27#ibcon#about to write, iclass 5, count 2 2006.245.08:15:54.27#ibcon#wrote, iclass 5, count 2 2006.245.08:15:54.27#ibcon#about to read 3, iclass 5, count 2 2006.245.08:15:54.29#ibcon#read 3, iclass 5, count 2 2006.245.08:15:54.29#ibcon#about to read 4, iclass 5, count 2 2006.245.08:15:54.29#ibcon#read 4, iclass 5, count 2 2006.245.08:15:54.29#ibcon#about to read 5, iclass 5, count 2 2006.245.08:15:54.29#ibcon#read 5, iclass 5, count 2 2006.245.08:15:54.29#ibcon#about to read 6, iclass 5, count 2 2006.245.08:15:54.29#ibcon#read 6, iclass 5, count 2 2006.245.08:15:54.29#ibcon#end of sib2, iclass 5, count 2 2006.245.08:15:54.29#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:15:54.29#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:15:54.29#ibcon#[27=AT03-04\r\n] 2006.245.08:15:54.29#ibcon#*before write, iclass 5, count 2 2006.245.08:15:54.29#ibcon#enter sib2, iclass 5, count 2 2006.245.08:15:54.29#ibcon#flushed, iclass 5, count 2 2006.245.08:15:54.29#ibcon#about to write, iclass 5, count 2 2006.245.08:15:54.29#ibcon#wrote, iclass 5, count 2 2006.245.08:15:54.29#ibcon#about to read 3, iclass 5, count 2 2006.245.08:15:54.32#ibcon#read 3, iclass 5, count 2 2006.245.08:15:54.32#ibcon#about to read 4, iclass 5, count 2 2006.245.08:15:54.32#ibcon#read 4, iclass 5, count 2 2006.245.08:15:54.32#ibcon#about to read 5, iclass 5, count 2 2006.245.08:15:54.32#ibcon#read 5, iclass 5, count 2 2006.245.08:15:54.32#ibcon#about to read 6, iclass 5, count 2 2006.245.08:15:54.32#ibcon#read 6, iclass 5, count 2 2006.245.08:15:54.32#ibcon#end of sib2, iclass 5, count 2 2006.245.08:15:54.32#ibcon#*after write, iclass 5, count 2 2006.245.08:15:54.32#ibcon#*before return 0, iclass 5, count 2 2006.245.08:15:54.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:54.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:15:54.32#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:15:54.32#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:54.32#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:54.44#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:54.44#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:54.44#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:15:54.44#ibcon#first serial, iclass 5, count 0 2006.245.08:15:54.44#ibcon#enter sib2, iclass 5, count 0 2006.245.08:15:54.44#ibcon#flushed, iclass 5, count 0 2006.245.08:15:54.44#ibcon#about to write, iclass 5, count 0 2006.245.08:15:54.44#ibcon#wrote, iclass 5, count 0 2006.245.08:15:54.44#ibcon#about to read 3, iclass 5, count 0 2006.245.08:15:54.46#ibcon#read 3, iclass 5, count 0 2006.245.08:15:54.46#ibcon#about to read 4, iclass 5, count 0 2006.245.08:15:54.46#ibcon#read 4, iclass 5, count 0 2006.245.08:15:54.46#ibcon#about to read 5, iclass 5, count 0 2006.245.08:15:54.46#ibcon#read 5, iclass 5, count 0 2006.245.08:15:54.46#ibcon#about to read 6, iclass 5, count 0 2006.245.08:15:54.46#ibcon#read 6, iclass 5, count 0 2006.245.08:15:54.46#ibcon#end of sib2, iclass 5, count 0 2006.245.08:15:54.46#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:15:54.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:15:54.46#ibcon#[27=USB\r\n] 2006.245.08:15:54.46#ibcon#*before write, iclass 5, count 0 2006.245.08:15:54.46#ibcon#enter sib2, iclass 5, count 0 2006.245.08:15:54.46#ibcon#flushed, iclass 5, count 0 2006.245.08:15:54.46#ibcon#about to write, iclass 5, count 0 2006.245.08:15:54.46#ibcon#wrote, iclass 5, count 0 2006.245.08:15:54.46#ibcon#about to read 3, iclass 5, count 0 2006.245.08:15:54.49#ibcon#read 3, iclass 5, count 0 2006.245.08:15:54.49#ibcon#about to read 4, iclass 5, count 0 2006.245.08:15:54.49#ibcon#read 4, iclass 5, count 0 2006.245.08:15:54.49#ibcon#about to read 5, iclass 5, count 0 2006.245.08:15:54.49#ibcon#read 5, iclass 5, count 0 2006.245.08:15:54.49#ibcon#about to read 6, iclass 5, count 0 2006.245.08:15:54.49#ibcon#read 6, iclass 5, count 0 2006.245.08:15:54.49#ibcon#end of sib2, iclass 5, count 0 2006.245.08:15:54.49#ibcon#*after write, iclass 5, count 0 2006.245.08:15:54.49#ibcon#*before return 0, iclass 5, count 0 2006.245.08:15:54.49#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:54.49#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:15:54.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:15:54.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:15:54.49$vc4f8/vblo=4,712.99 2006.245.08:15:54.49#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:15:54.49#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:15:54.49#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:54.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:54.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:54.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:54.49#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:15:54.49#ibcon#first serial, iclass 7, count 0 2006.245.08:15:54.49#ibcon#enter sib2, iclass 7, count 0 2006.245.08:15:54.49#ibcon#flushed, iclass 7, count 0 2006.245.08:15:54.49#ibcon#about to write, iclass 7, count 0 2006.245.08:15:54.49#ibcon#wrote, iclass 7, count 0 2006.245.08:15:54.49#ibcon#about to read 3, iclass 7, count 0 2006.245.08:15:54.51#ibcon#read 3, iclass 7, count 0 2006.245.08:15:54.51#ibcon#about to read 4, iclass 7, count 0 2006.245.08:15:54.51#ibcon#read 4, iclass 7, count 0 2006.245.08:15:54.51#ibcon#about to read 5, iclass 7, count 0 2006.245.08:15:54.51#ibcon#read 5, iclass 7, count 0 2006.245.08:15:54.51#ibcon#about to read 6, iclass 7, count 0 2006.245.08:15:54.51#ibcon#read 6, iclass 7, count 0 2006.245.08:15:54.51#ibcon#end of sib2, iclass 7, count 0 2006.245.08:15:54.51#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:15:54.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:15:54.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:15:54.51#ibcon#*before write, iclass 7, count 0 2006.245.08:15:54.51#ibcon#enter sib2, iclass 7, count 0 2006.245.08:15:54.51#ibcon#flushed, iclass 7, count 0 2006.245.08:15:54.51#ibcon#about to write, iclass 7, count 0 2006.245.08:15:54.51#ibcon#wrote, iclass 7, count 0 2006.245.08:15:54.51#ibcon#about to read 3, iclass 7, count 0 2006.245.08:15:54.55#ibcon#read 3, iclass 7, count 0 2006.245.08:15:54.55#ibcon#about to read 4, iclass 7, count 0 2006.245.08:15:54.55#ibcon#read 4, iclass 7, count 0 2006.245.08:15:54.55#ibcon#about to read 5, iclass 7, count 0 2006.245.08:15:54.55#ibcon#read 5, iclass 7, count 0 2006.245.08:15:54.55#ibcon#about to read 6, iclass 7, count 0 2006.245.08:15:54.55#ibcon#read 6, iclass 7, count 0 2006.245.08:15:54.55#ibcon#end of sib2, iclass 7, count 0 2006.245.08:15:54.55#ibcon#*after write, iclass 7, count 0 2006.245.08:15:54.55#ibcon#*before return 0, iclass 7, count 0 2006.245.08:15:54.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:54.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:15:54.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:15:54.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:15:54.55$vc4f8/vb=4,4 2006.245.08:15:54.55#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:15:54.55#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:15:54.55#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:54.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:54.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:54.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:54.61#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:15:54.61#ibcon#first serial, iclass 11, count 2 2006.245.08:15:54.61#ibcon#enter sib2, iclass 11, count 2 2006.245.08:15:54.61#ibcon#flushed, iclass 11, count 2 2006.245.08:15:54.61#ibcon#about to write, iclass 11, count 2 2006.245.08:15:54.61#ibcon#wrote, iclass 11, count 2 2006.245.08:15:54.61#ibcon#about to read 3, iclass 11, count 2 2006.245.08:15:54.63#ibcon#read 3, iclass 11, count 2 2006.245.08:15:54.63#ibcon#about to read 4, iclass 11, count 2 2006.245.08:15:54.63#ibcon#read 4, iclass 11, count 2 2006.245.08:15:54.63#ibcon#about to read 5, iclass 11, count 2 2006.245.08:15:54.63#ibcon#read 5, iclass 11, count 2 2006.245.08:15:54.63#ibcon#about to read 6, iclass 11, count 2 2006.245.08:15:54.63#ibcon#read 6, iclass 11, count 2 2006.245.08:15:54.63#ibcon#end of sib2, iclass 11, count 2 2006.245.08:15:54.63#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:15:54.63#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:15:54.63#ibcon#[27=AT04-04\r\n] 2006.245.08:15:54.63#ibcon#*before write, iclass 11, count 2 2006.245.08:15:54.63#ibcon#enter sib2, iclass 11, count 2 2006.245.08:15:54.63#ibcon#flushed, iclass 11, count 2 2006.245.08:15:54.63#ibcon#about to write, iclass 11, count 2 2006.245.08:15:54.63#ibcon#wrote, iclass 11, count 2 2006.245.08:15:54.63#ibcon#about to read 3, iclass 11, count 2 2006.245.08:15:54.66#ibcon#read 3, iclass 11, count 2 2006.245.08:15:54.66#ibcon#about to read 4, iclass 11, count 2 2006.245.08:15:54.66#ibcon#read 4, iclass 11, count 2 2006.245.08:15:54.66#ibcon#about to read 5, iclass 11, count 2 2006.245.08:15:54.66#ibcon#read 5, iclass 11, count 2 2006.245.08:15:54.66#ibcon#about to read 6, iclass 11, count 2 2006.245.08:15:54.66#ibcon#read 6, iclass 11, count 2 2006.245.08:15:54.66#ibcon#end of sib2, iclass 11, count 2 2006.245.08:15:54.66#ibcon#*after write, iclass 11, count 2 2006.245.08:15:54.66#ibcon#*before return 0, iclass 11, count 2 2006.245.08:15:54.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:54.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:15:54.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:15:54.66#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:54.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:54.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:54.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:54.78#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:15:54.78#ibcon#first serial, iclass 11, count 0 2006.245.08:15:54.78#ibcon#enter sib2, iclass 11, count 0 2006.245.08:15:54.78#ibcon#flushed, iclass 11, count 0 2006.245.08:15:54.78#ibcon#about to write, iclass 11, count 0 2006.245.08:15:54.78#ibcon#wrote, iclass 11, count 0 2006.245.08:15:54.78#ibcon#about to read 3, iclass 11, count 0 2006.245.08:15:54.80#ibcon#read 3, iclass 11, count 0 2006.245.08:15:54.80#ibcon#about to read 4, iclass 11, count 0 2006.245.08:15:54.80#ibcon#read 4, iclass 11, count 0 2006.245.08:15:54.80#ibcon#about to read 5, iclass 11, count 0 2006.245.08:15:54.80#ibcon#read 5, iclass 11, count 0 2006.245.08:15:54.80#ibcon#about to read 6, iclass 11, count 0 2006.245.08:15:54.80#ibcon#read 6, iclass 11, count 0 2006.245.08:15:54.80#ibcon#end of sib2, iclass 11, count 0 2006.245.08:15:54.80#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:15:54.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:15:54.80#ibcon#[27=USB\r\n] 2006.245.08:15:54.80#ibcon#*before write, iclass 11, count 0 2006.245.08:15:54.80#ibcon#enter sib2, iclass 11, count 0 2006.245.08:15:54.80#ibcon#flushed, iclass 11, count 0 2006.245.08:15:54.80#ibcon#about to write, iclass 11, count 0 2006.245.08:15:54.80#ibcon#wrote, iclass 11, count 0 2006.245.08:15:54.80#ibcon#about to read 3, iclass 11, count 0 2006.245.08:15:54.83#ibcon#read 3, iclass 11, count 0 2006.245.08:15:54.83#ibcon#about to read 4, iclass 11, count 0 2006.245.08:15:54.83#ibcon#read 4, iclass 11, count 0 2006.245.08:15:54.83#ibcon#about to read 5, iclass 11, count 0 2006.245.08:15:54.83#ibcon#read 5, iclass 11, count 0 2006.245.08:15:54.83#ibcon#about to read 6, iclass 11, count 0 2006.245.08:15:54.83#ibcon#read 6, iclass 11, count 0 2006.245.08:15:54.83#ibcon#end of sib2, iclass 11, count 0 2006.245.08:15:54.83#ibcon#*after write, iclass 11, count 0 2006.245.08:15:54.83#ibcon#*before return 0, iclass 11, count 0 2006.245.08:15:54.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:54.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:15:54.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:15:54.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:15:54.83$vc4f8/vblo=5,744.99 2006.245.08:15:54.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:15:54.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:15:54.83#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:54.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:54.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:54.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:54.83#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:15:54.83#ibcon#first serial, iclass 13, count 0 2006.245.08:15:54.83#ibcon#enter sib2, iclass 13, count 0 2006.245.08:15:54.83#ibcon#flushed, iclass 13, count 0 2006.245.08:15:54.83#ibcon#about to write, iclass 13, count 0 2006.245.08:15:54.83#ibcon#wrote, iclass 13, count 0 2006.245.08:15:54.83#ibcon#about to read 3, iclass 13, count 0 2006.245.08:15:54.85#ibcon#read 3, iclass 13, count 0 2006.245.08:15:54.85#ibcon#about to read 4, iclass 13, count 0 2006.245.08:15:54.85#ibcon#read 4, iclass 13, count 0 2006.245.08:15:54.85#ibcon#about to read 5, iclass 13, count 0 2006.245.08:15:54.85#ibcon#read 5, iclass 13, count 0 2006.245.08:15:54.85#ibcon#about to read 6, iclass 13, count 0 2006.245.08:15:54.85#ibcon#read 6, iclass 13, count 0 2006.245.08:15:54.85#ibcon#end of sib2, iclass 13, count 0 2006.245.08:15:54.85#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:15:54.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:15:54.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:15:54.85#ibcon#*before write, iclass 13, count 0 2006.245.08:15:54.85#ibcon#enter sib2, iclass 13, count 0 2006.245.08:15:54.85#ibcon#flushed, iclass 13, count 0 2006.245.08:15:54.85#ibcon#about to write, iclass 13, count 0 2006.245.08:15:54.85#ibcon#wrote, iclass 13, count 0 2006.245.08:15:54.85#ibcon#about to read 3, iclass 13, count 0 2006.245.08:15:54.89#ibcon#read 3, iclass 13, count 0 2006.245.08:15:54.89#ibcon#about to read 4, iclass 13, count 0 2006.245.08:15:54.89#ibcon#read 4, iclass 13, count 0 2006.245.08:15:54.89#ibcon#about to read 5, iclass 13, count 0 2006.245.08:15:54.89#ibcon#read 5, iclass 13, count 0 2006.245.08:15:54.89#ibcon#about to read 6, iclass 13, count 0 2006.245.08:15:54.89#ibcon#read 6, iclass 13, count 0 2006.245.08:15:54.89#ibcon#end of sib2, iclass 13, count 0 2006.245.08:15:54.89#ibcon#*after write, iclass 13, count 0 2006.245.08:15:54.89#ibcon#*before return 0, iclass 13, count 0 2006.245.08:15:54.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:54.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:15:54.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:15:54.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:15:54.89$vc4f8/vb=5,3 2006.245.08:15:54.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:15:54.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:15:54.89#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:54.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:15:54.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:15:54.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:15:54.95#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:15:54.95#ibcon#first serial, iclass 15, count 2 2006.245.08:15:54.95#ibcon#enter sib2, iclass 15, count 2 2006.245.08:15:54.95#ibcon#flushed, iclass 15, count 2 2006.245.08:15:54.95#ibcon#about to write, iclass 15, count 2 2006.245.08:15:54.95#ibcon#wrote, iclass 15, count 2 2006.245.08:15:54.95#ibcon#about to read 3, iclass 15, count 2 2006.245.08:15:54.97#ibcon#read 3, iclass 15, count 2 2006.245.08:15:54.97#ibcon#about to read 4, iclass 15, count 2 2006.245.08:15:54.97#ibcon#read 4, iclass 15, count 2 2006.245.08:15:54.97#ibcon#about to read 5, iclass 15, count 2 2006.245.08:15:54.97#ibcon#read 5, iclass 15, count 2 2006.245.08:15:54.97#ibcon#about to read 6, iclass 15, count 2 2006.245.08:15:54.97#ibcon#read 6, iclass 15, count 2 2006.245.08:15:54.97#ibcon#end of sib2, iclass 15, count 2 2006.245.08:15:54.97#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:15:54.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:15:54.97#ibcon#[27=AT05-03\r\n] 2006.245.08:15:54.97#ibcon#*before write, iclass 15, count 2 2006.245.08:15:54.97#ibcon#enter sib2, iclass 15, count 2 2006.245.08:15:54.97#ibcon#flushed, iclass 15, count 2 2006.245.08:15:54.97#ibcon#about to write, iclass 15, count 2 2006.245.08:15:54.97#ibcon#wrote, iclass 15, count 2 2006.245.08:15:54.97#ibcon#about to read 3, iclass 15, count 2 2006.245.08:15:55.00#ibcon#read 3, iclass 15, count 2 2006.245.08:15:55.00#ibcon#about to read 4, iclass 15, count 2 2006.245.08:15:55.00#ibcon#read 4, iclass 15, count 2 2006.245.08:15:55.00#ibcon#about to read 5, iclass 15, count 2 2006.245.08:15:55.00#ibcon#read 5, iclass 15, count 2 2006.245.08:15:55.00#ibcon#about to read 6, iclass 15, count 2 2006.245.08:15:55.00#ibcon#read 6, iclass 15, count 2 2006.245.08:15:55.00#ibcon#end of sib2, iclass 15, count 2 2006.245.08:15:55.00#ibcon#*after write, iclass 15, count 2 2006.245.08:15:55.00#ibcon#*before return 0, iclass 15, count 2 2006.245.08:15:55.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:15:55.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:15:55.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:15:55.00#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:55.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:15:55.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:15:55.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:15:55.12#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:15:55.12#ibcon#first serial, iclass 15, count 0 2006.245.08:15:55.12#ibcon#enter sib2, iclass 15, count 0 2006.245.08:15:55.12#ibcon#flushed, iclass 15, count 0 2006.245.08:15:55.12#ibcon#about to write, iclass 15, count 0 2006.245.08:15:55.12#ibcon#wrote, iclass 15, count 0 2006.245.08:15:55.12#ibcon#about to read 3, iclass 15, count 0 2006.245.08:15:55.14#ibcon#read 3, iclass 15, count 0 2006.245.08:15:55.14#ibcon#about to read 4, iclass 15, count 0 2006.245.08:15:55.14#ibcon#read 4, iclass 15, count 0 2006.245.08:15:55.14#ibcon#about to read 5, iclass 15, count 0 2006.245.08:15:55.14#ibcon#read 5, iclass 15, count 0 2006.245.08:15:55.14#ibcon#about to read 6, iclass 15, count 0 2006.245.08:15:55.14#ibcon#read 6, iclass 15, count 0 2006.245.08:15:55.14#ibcon#end of sib2, iclass 15, count 0 2006.245.08:15:55.14#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:15:55.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:15:55.14#ibcon#[27=USB\r\n] 2006.245.08:15:55.14#ibcon#*before write, iclass 15, count 0 2006.245.08:15:55.14#ibcon#enter sib2, iclass 15, count 0 2006.245.08:15:55.14#ibcon#flushed, iclass 15, count 0 2006.245.08:15:55.14#ibcon#about to write, iclass 15, count 0 2006.245.08:15:55.14#ibcon#wrote, iclass 15, count 0 2006.245.08:15:55.14#ibcon#about to read 3, iclass 15, count 0 2006.245.08:15:55.17#ibcon#read 3, iclass 15, count 0 2006.245.08:15:55.17#ibcon#about to read 4, iclass 15, count 0 2006.245.08:15:55.17#ibcon#read 4, iclass 15, count 0 2006.245.08:15:55.17#ibcon#about to read 5, iclass 15, count 0 2006.245.08:15:55.17#ibcon#read 5, iclass 15, count 0 2006.245.08:15:55.17#ibcon#about to read 6, iclass 15, count 0 2006.245.08:15:55.17#ibcon#read 6, iclass 15, count 0 2006.245.08:15:55.17#ibcon#end of sib2, iclass 15, count 0 2006.245.08:15:55.17#ibcon#*after write, iclass 15, count 0 2006.245.08:15:55.17#ibcon#*before return 0, iclass 15, count 0 2006.245.08:15:55.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:15:55.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:15:55.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:15:55.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:15:55.17$vc4f8/vblo=6,752.99 2006.245.08:15:55.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:15:55.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:15:55.17#ibcon#ireg 17 cls_cnt 0 2006.245.08:15:55.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:15:55.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:15:55.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:15:55.17#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:15:55.17#ibcon#first serial, iclass 17, count 0 2006.245.08:15:55.17#ibcon#enter sib2, iclass 17, count 0 2006.245.08:15:55.17#ibcon#flushed, iclass 17, count 0 2006.245.08:15:55.17#ibcon#about to write, iclass 17, count 0 2006.245.08:15:55.17#ibcon#wrote, iclass 17, count 0 2006.245.08:15:55.17#ibcon#about to read 3, iclass 17, count 0 2006.245.08:15:55.19#ibcon#read 3, iclass 17, count 0 2006.245.08:15:55.19#ibcon#about to read 4, iclass 17, count 0 2006.245.08:15:55.19#ibcon#read 4, iclass 17, count 0 2006.245.08:15:55.19#ibcon#about to read 5, iclass 17, count 0 2006.245.08:15:55.19#ibcon#read 5, iclass 17, count 0 2006.245.08:15:55.19#ibcon#about to read 6, iclass 17, count 0 2006.245.08:15:55.19#ibcon#read 6, iclass 17, count 0 2006.245.08:15:55.19#ibcon#end of sib2, iclass 17, count 0 2006.245.08:15:55.19#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:15:55.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:15:55.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:15:55.19#ibcon#*before write, iclass 17, count 0 2006.245.08:15:55.19#ibcon#enter sib2, iclass 17, count 0 2006.245.08:15:55.19#ibcon#flushed, iclass 17, count 0 2006.245.08:15:55.19#ibcon#about to write, iclass 17, count 0 2006.245.08:15:55.19#ibcon#wrote, iclass 17, count 0 2006.245.08:15:55.19#ibcon#about to read 3, iclass 17, count 0 2006.245.08:15:55.23#ibcon#read 3, iclass 17, count 0 2006.245.08:15:55.23#ibcon#about to read 4, iclass 17, count 0 2006.245.08:15:55.23#ibcon#read 4, iclass 17, count 0 2006.245.08:15:55.23#ibcon#about to read 5, iclass 17, count 0 2006.245.08:15:55.23#ibcon#read 5, iclass 17, count 0 2006.245.08:15:55.23#ibcon#about to read 6, iclass 17, count 0 2006.245.08:15:55.23#ibcon#read 6, iclass 17, count 0 2006.245.08:15:55.23#ibcon#end of sib2, iclass 17, count 0 2006.245.08:15:55.23#ibcon#*after write, iclass 17, count 0 2006.245.08:15:55.23#ibcon#*before return 0, iclass 17, count 0 2006.245.08:15:55.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:15:55.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:15:55.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:15:55.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:15:55.23$vc4f8/vb=6,3 2006.245.08:15:55.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:15:55.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:15:55.23#ibcon#ireg 11 cls_cnt 2 2006.245.08:15:55.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:15:55.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:15:55.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:15:55.29#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:15:55.29#ibcon#first serial, iclass 19, count 2 2006.245.08:15:55.29#ibcon#enter sib2, iclass 19, count 2 2006.245.08:15:55.29#ibcon#flushed, iclass 19, count 2 2006.245.08:15:55.29#ibcon#about to write, iclass 19, count 2 2006.245.08:15:55.29#ibcon#wrote, iclass 19, count 2 2006.245.08:15:55.29#ibcon#about to read 3, iclass 19, count 2 2006.245.08:15:55.31#ibcon#read 3, iclass 19, count 2 2006.245.08:15:55.31#ibcon#about to read 4, iclass 19, count 2 2006.245.08:15:55.31#ibcon#read 4, iclass 19, count 2 2006.245.08:15:55.31#ibcon#about to read 5, iclass 19, count 2 2006.245.08:15:55.31#ibcon#read 5, iclass 19, count 2 2006.245.08:15:55.31#ibcon#about to read 6, iclass 19, count 2 2006.245.08:15:55.31#ibcon#read 6, iclass 19, count 2 2006.245.08:15:55.31#ibcon#end of sib2, iclass 19, count 2 2006.245.08:15:55.31#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:15:55.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:15:55.31#ibcon#[27=AT06-03\r\n] 2006.245.08:15:55.31#ibcon#*before write, iclass 19, count 2 2006.245.08:15:55.31#ibcon#enter sib2, iclass 19, count 2 2006.245.08:15:55.31#ibcon#flushed, iclass 19, count 2 2006.245.08:15:55.31#ibcon#about to write, iclass 19, count 2 2006.245.08:15:55.31#ibcon#wrote, iclass 19, count 2 2006.245.08:15:55.31#ibcon#about to read 3, iclass 19, count 2 2006.245.08:15:55.34#ibcon#read 3, iclass 19, count 2 2006.245.08:15:55.34#ibcon#about to read 4, iclass 19, count 2 2006.245.08:15:55.34#ibcon#read 4, iclass 19, count 2 2006.245.08:15:55.34#ibcon#about to read 5, iclass 19, count 2 2006.245.08:15:55.34#ibcon#read 5, iclass 19, count 2 2006.245.08:15:55.34#ibcon#about to read 6, iclass 19, count 2 2006.245.08:15:55.34#ibcon#read 6, iclass 19, count 2 2006.245.08:15:55.34#ibcon#end of sib2, iclass 19, count 2 2006.245.08:15:55.34#ibcon#*after write, iclass 19, count 2 2006.245.08:15:55.34#ibcon#*before return 0, iclass 19, count 2 2006.245.08:15:55.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:15:55.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:15:55.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:15:55.34#ibcon#ireg 7 cls_cnt 0 2006.245.08:15:55.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:15:55.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:15:55.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:15:55.46#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:15:55.46#ibcon#first serial, iclass 19, count 0 2006.245.08:15:55.46#ibcon#enter sib2, iclass 19, count 0 2006.245.08:15:55.46#ibcon#flushed, iclass 19, count 0 2006.245.08:15:55.46#ibcon#about to write, iclass 19, count 0 2006.245.08:15:55.46#ibcon#wrote, iclass 19, count 0 2006.245.08:15:55.46#ibcon#about to read 3, iclass 19, count 0 2006.245.08:15:55.48#ibcon#read 3, iclass 19, count 0 2006.245.08:15:55.48#ibcon#about to read 4, iclass 19, count 0 2006.245.08:15:55.48#ibcon#read 4, iclass 19, count 0 2006.245.08:15:55.48#ibcon#about to read 5, iclass 19, count 0 2006.245.08:15:55.48#ibcon#read 5, iclass 19, count 0 2006.245.08:15:55.48#ibcon#about to read 6, iclass 19, count 0 2006.245.08:15:55.48#ibcon#read 6, iclass 19, count 0 2006.245.08:15:55.48#ibcon#end of sib2, iclass 19, count 0 2006.245.08:15:55.48#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:15:55.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:15:55.48#ibcon#[27=USB\r\n] 2006.245.08:15:55.48#ibcon#*before write, iclass 19, count 0 2006.245.08:15:55.48#ibcon#enter sib2, iclass 19, count 0 2006.245.08:15:55.48#ibcon#flushed, iclass 19, count 0 2006.245.08:15:55.48#ibcon#about to write, iclass 19, count 0 2006.245.08:15:55.48#ibcon#wrote, iclass 19, count 0 2006.245.08:15:55.48#ibcon#about to read 3, iclass 19, count 0 2006.245.08:15:55.51#ibcon#read 3, iclass 19, count 0 2006.245.08:15:55.51#ibcon#about to read 4, iclass 19, count 0 2006.245.08:15:55.51#ibcon#read 4, iclass 19, count 0 2006.245.08:15:55.51#ibcon#about to read 5, iclass 19, count 0 2006.245.08:15:55.51#ibcon#read 5, iclass 19, count 0 2006.245.08:15:55.51#ibcon#about to read 6, iclass 19, count 0 2006.245.08:15:55.51#ibcon#read 6, iclass 19, count 0 2006.245.08:15:55.51#ibcon#end of sib2, iclass 19, count 0 2006.245.08:15:55.51#ibcon#*after write, iclass 19, count 0 2006.245.08:15:55.51#ibcon#*before return 0, iclass 19, count 0 2006.245.08:15:55.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:15:55.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:15:55.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:15:55.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:15:55.51$vc4f8/vabw=wide 2006.245.08:15:55.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:15:55.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:15:55.51#ibcon#ireg 8 cls_cnt 0 2006.245.08:15:55.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:55.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:55.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:55.51#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:15:55.51#ibcon#first serial, iclass 21, count 0 2006.245.08:15:55.51#ibcon#enter sib2, iclass 21, count 0 2006.245.08:15:55.51#ibcon#flushed, iclass 21, count 0 2006.245.08:15:55.51#ibcon#about to write, iclass 21, count 0 2006.245.08:15:55.51#ibcon#wrote, iclass 21, count 0 2006.245.08:15:55.51#ibcon#about to read 3, iclass 21, count 0 2006.245.08:15:55.53#ibcon#read 3, iclass 21, count 0 2006.245.08:15:55.53#ibcon#about to read 4, iclass 21, count 0 2006.245.08:15:55.53#ibcon#read 4, iclass 21, count 0 2006.245.08:15:55.53#ibcon#about to read 5, iclass 21, count 0 2006.245.08:15:55.53#ibcon#read 5, iclass 21, count 0 2006.245.08:15:55.53#ibcon#about to read 6, iclass 21, count 0 2006.245.08:15:55.53#ibcon#read 6, iclass 21, count 0 2006.245.08:15:55.53#ibcon#end of sib2, iclass 21, count 0 2006.245.08:15:55.53#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:15:55.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:15:55.53#ibcon#[25=BW32\r\n] 2006.245.08:15:55.53#ibcon#*before write, iclass 21, count 0 2006.245.08:15:55.53#ibcon#enter sib2, iclass 21, count 0 2006.245.08:15:55.53#ibcon#flushed, iclass 21, count 0 2006.245.08:15:55.53#ibcon#about to write, iclass 21, count 0 2006.245.08:15:55.53#ibcon#wrote, iclass 21, count 0 2006.245.08:15:55.53#ibcon#about to read 3, iclass 21, count 0 2006.245.08:15:55.56#ibcon#read 3, iclass 21, count 0 2006.245.08:15:55.56#ibcon#about to read 4, iclass 21, count 0 2006.245.08:15:55.56#ibcon#read 4, iclass 21, count 0 2006.245.08:15:55.56#ibcon#about to read 5, iclass 21, count 0 2006.245.08:15:55.56#ibcon#read 5, iclass 21, count 0 2006.245.08:15:55.56#ibcon#about to read 6, iclass 21, count 0 2006.245.08:15:55.56#ibcon#read 6, iclass 21, count 0 2006.245.08:15:55.56#ibcon#end of sib2, iclass 21, count 0 2006.245.08:15:55.56#ibcon#*after write, iclass 21, count 0 2006.245.08:15:55.56#ibcon#*before return 0, iclass 21, count 0 2006.245.08:15:55.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:55.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:15:55.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:15:55.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:15:55.56$vc4f8/vbbw=wide 2006.245.08:15:55.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.08:15:55.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.08:15:55.56#ibcon#ireg 8 cls_cnt 0 2006.245.08:15:55.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:15:55.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:15:55.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:15:55.63#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:15:55.63#ibcon#first serial, iclass 23, count 0 2006.245.08:15:55.63#ibcon#enter sib2, iclass 23, count 0 2006.245.08:15:55.63#ibcon#flushed, iclass 23, count 0 2006.245.08:15:55.63#ibcon#about to write, iclass 23, count 0 2006.245.08:15:55.63#ibcon#wrote, iclass 23, count 0 2006.245.08:15:55.63#ibcon#about to read 3, iclass 23, count 0 2006.245.08:15:55.65#ibcon#read 3, iclass 23, count 0 2006.245.08:15:55.65#ibcon#about to read 4, iclass 23, count 0 2006.245.08:15:55.65#ibcon#read 4, iclass 23, count 0 2006.245.08:15:55.65#ibcon#about to read 5, iclass 23, count 0 2006.245.08:15:55.65#ibcon#read 5, iclass 23, count 0 2006.245.08:15:55.65#ibcon#about to read 6, iclass 23, count 0 2006.245.08:15:55.65#ibcon#read 6, iclass 23, count 0 2006.245.08:15:55.65#ibcon#end of sib2, iclass 23, count 0 2006.245.08:15:55.65#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:15:55.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:15:55.65#ibcon#[27=BW32\r\n] 2006.245.08:15:55.65#ibcon#*before write, iclass 23, count 0 2006.245.08:15:55.65#ibcon#enter sib2, iclass 23, count 0 2006.245.08:15:55.65#ibcon#flushed, iclass 23, count 0 2006.245.08:15:55.65#ibcon#about to write, iclass 23, count 0 2006.245.08:15:55.65#ibcon#wrote, iclass 23, count 0 2006.245.08:15:55.65#ibcon#about to read 3, iclass 23, count 0 2006.245.08:15:55.68#ibcon#read 3, iclass 23, count 0 2006.245.08:15:55.68#ibcon#about to read 4, iclass 23, count 0 2006.245.08:15:55.68#ibcon#read 4, iclass 23, count 0 2006.245.08:15:55.68#ibcon#about to read 5, iclass 23, count 0 2006.245.08:15:55.68#ibcon#read 5, iclass 23, count 0 2006.245.08:15:55.68#ibcon#about to read 6, iclass 23, count 0 2006.245.08:15:55.68#ibcon#read 6, iclass 23, count 0 2006.245.08:15:55.68#ibcon#end of sib2, iclass 23, count 0 2006.245.08:15:55.68#ibcon#*after write, iclass 23, count 0 2006.245.08:15:55.68#ibcon#*before return 0, iclass 23, count 0 2006.245.08:15:55.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:15:55.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:15:55.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:15:55.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:15:55.68$4f8m12a/ifd4f 2006.245.08:15:55.68$ifd4f/lo= 2006.245.08:15:55.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:15:55.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:15:55.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:15:55.68$ifd4f/patch= 2006.245.08:15:55.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:15:55.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:15:55.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:15:55.68$4f8m12a/"form=m,16.000,1:2 2006.245.08:15:55.68$4f8m12a/"tpicd 2006.245.08:15:55.68$4f8m12a/echo=off 2006.245.08:15:55.68$4f8m12a/xlog=off 2006.245.08:15:55.68:!2006.245.08:16:30 2006.245.08:16:17.14#trakl#Source acquired 2006.245.08:16:17.14#flagr#flagr/antenna,acquired 2006.245.08:16:30.00:preob 2006.245.08:16:30.14/onsource/TRACKING 2006.245.08:16:30.14:!2006.245.08:16:40 2006.245.08:16:40.00:data_valid=on 2006.245.08:16:40.00:midob 2006.245.08:16:41.14/onsource/TRACKING 2006.245.08:16:41.14/wx/26.81,1004.5,75 2006.245.08:16:41.21/cable/+6.4119E-03 2006.245.08:16:42.30/va/01,08,usb,yes,34,36 2006.245.08:16:42.30/va/02,07,usb,yes,34,35 2006.245.08:16:42.30/va/03,06,usb,yes,36,36 2006.245.08:16:42.30/va/04,07,usb,yes,35,38 2006.245.08:16:42.30/va/05,07,usb,yes,37,39 2006.245.08:16:42.30/va/06,07,usb,yes,33,33 2006.245.08:16:42.30/va/07,07,usb,yes,33,32 2006.245.08:16:42.30/va/08,08,usb,yes,28,28 2006.245.08:16:42.53/valo/01,532.99,yes,locked 2006.245.08:16:42.53/valo/02,572.99,yes,locked 2006.245.08:16:42.53/valo/03,672.99,yes,locked 2006.245.08:16:42.53/valo/04,832.99,yes,locked 2006.245.08:16:42.53/valo/05,652.99,yes,locked 2006.245.08:16:42.53/valo/06,772.99,yes,locked 2006.245.08:16:42.53/valo/07,832.99,yes,locked 2006.245.08:16:42.53/valo/08,852.99,yes,locked 2006.245.08:16:43.62/vb/01,04,usb,yes,33,32 2006.245.08:16:43.62/vb/02,04,usb,yes,35,36 2006.245.08:16:43.62/vb/03,04,usb,yes,31,35 2006.245.08:16:43.62/vb/04,04,usb,yes,33,32 2006.245.08:16:43.62/vb/05,03,usb,yes,38,43 2006.245.08:16:43.62/vb/06,03,usb,yes,39,42 2006.245.08:16:43.62/vb/07,04,usb,yes,34,34 2006.245.08:16:43.62/vb/08,03,usb,yes,38,43 2006.245.08:16:43.85/vblo/01,632.99,yes,locked 2006.245.08:16:43.85/vblo/02,640.99,yes,locked 2006.245.08:16:43.85/vblo/03,656.99,yes,locked 2006.245.08:16:43.85/vblo/04,712.99,yes,locked 2006.245.08:16:43.85/vblo/05,744.99,yes,locked 2006.245.08:16:43.85/vblo/06,752.99,yes,locked 2006.245.08:16:43.85/vblo/07,734.99,yes,locked 2006.245.08:16:43.85/vblo/08,744.99,yes,locked 2006.245.08:16:44.00/vabw/8 2006.245.08:16:44.15/vbbw/8 2006.245.08:16:44.24/xfe/off,on,14.0 2006.245.08:16:44.62/ifatt/23,28,28,28 2006.245.08:16:45.08/fmout-gps/S +4.37E-07 2006.245.08:16:45.12:!2006.245.08:17:40 2006.245.08:17:40.00:data_valid=off 2006.245.08:17:40.00:postob 2006.245.08:17:40.21/cable/+6.4100E-03 2006.245.08:17:40.21/wx/26.79,1004.6,75 2006.245.08:17:41.08/fmout-gps/S +4.37E-07 2006.245.08:17:41.08:scan_name=245-0818,k06245,60 2006.245.08:17:41.09:source=1357+769,135755.37,764321.1,2000.0,ccw 2006.245.08:17:41.14#flagr#flagr/antenna,new-source 2006.245.08:17:42.14:checkk5 2006.245.08:17:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:17:42.99/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:17:43.41/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:17:44.03/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:17:44.44/chk_obsdata//k5ts1/T2450816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:17:44.85/chk_obsdata//k5ts2/T2450816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:17:45.28/chk_obsdata//k5ts3/T2450816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:17:45.78/chk_obsdata//k5ts4/T2450816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:17:46.70/k5log//k5ts1_log_newline 2006.245.08:17:47.55/k5log//k5ts2_log_newline 2006.245.08:17:48.39/k5log//k5ts3_log_newline 2006.245.08:17:49.71/k5log//k5ts4_log_newline 2006.245.08:17:49.74/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:17:49.74:4f8m12a=2 2006.245.08:17:49.74$4f8m12a/echo=on 2006.245.08:17:49.74$4f8m12a/pcalon 2006.245.08:17:49.74$pcalon/"no phase cal control is implemented here 2006.245.08:17:49.74$4f8m12a/"tpicd=stop 2006.245.08:17:49.74$4f8m12a/vc4f8 2006.245.08:17:49.74$vc4f8/valo=1,532.99 2006.245.08:17:49.74#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.08:17:49.74#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.08:17:49.74#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:49.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:49.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:49.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:49.74#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:17:49.74#ibcon#first serial, iclass 34, count 0 2006.245.08:17:49.74#ibcon#enter sib2, iclass 34, count 0 2006.245.08:17:49.74#ibcon#flushed, iclass 34, count 0 2006.245.08:17:49.74#ibcon#about to write, iclass 34, count 0 2006.245.08:17:49.74#ibcon#wrote, iclass 34, count 0 2006.245.08:17:49.74#ibcon#about to read 3, iclass 34, count 0 2006.245.08:17:49.78#ibcon#read 3, iclass 34, count 0 2006.245.08:17:49.78#ibcon#about to read 4, iclass 34, count 0 2006.245.08:17:49.78#ibcon#read 4, iclass 34, count 0 2006.245.08:17:49.78#ibcon#about to read 5, iclass 34, count 0 2006.245.08:17:49.78#ibcon#read 5, iclass 34, count 0 2006.245.08:17:49.78#ibcon#about to read 6, iclass 34, count 0 2006.245.08:17:49.78#ibcon#read 6, iclass 34, count 0 2006.245.08:17:49.78#ibcon#end of sib2, iclass 34, count 0 2006.245.08:17:49.78#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:17:49.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:17:49.78#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:17:49.78#ibcon#*before write, iclass 34, count 0 2006.245.08:17:49.78#ibcon#enter sib2, iclass 34, count 0 2006.245.08:17:49.78#ibcon#flushed, iclass 34, count 0 2006.245.08:17:49.78#ibcon#about to write, iclass 34, count 0 2006.245.08:17:49.78#ibcon#wrote, iclass 34, count 0 2006.245.08:17:49.78#ibcon#about to read 3, iclass 34, count 0 2006.245.08:17:49.83#ibcon#read 3, iclass 34, count 0 2006.245.08:17:49.83#ibcon#about to read 4, iclass 34, count 0 2006.245.08:17:49.83#ibcon#read 4, iclass 34, count 0 2006.245.08:17:49.83#ibcon#about to read 5, iclass 34, count 0 2006.245.08:17:49.83#ibcon#read 5, iclass 34, count 0 2006.245.08:17:49.83#ibcon#about to read 6, iclass 34, count 0 2006.245.08:17:49.83#ibcon#read 6, iclass 34, count 0 2006.245.08:17:49.83#ibcon#end of sib2, iclass 34, count 0 2006.245.08:17:49.83#ibcon#*after write, iclass 34, count 0 2006.245.08:17:49.83#ibcon#*before return 0, iclass 34, count 0 2006.245.08:17:49.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:49.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:49.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:17:49.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:17:49.83$vc4f8/va=1,8 2006.245.08:17:49.83#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.08:17:49.83#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.08:17:49.83#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:49.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:49.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:49.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:49.83#ibcon#enter wrdev, iclass 36, count 2 2006.245.08:17:49.83#ibcon#first serial, iclass 36, count 2 2006.245.08:17:49.83#ibcon#enter sib2, iclass 36, count 2 2006.245.08:17:49.83#ibcon#flushed, iclass 36, count 2 2006.245.08:17:49.83#ibcon#about to write, iclass 36, count 2 2006.245.08:17:49.83#ibcon#wrote, iclass 36, count 2 2006.245.08:17:49.83#ibcon#about to read 3, iclass 36, count 2 2006.245.08:17:49.85#ibcon#read 3, iclass 36, count 2 2006.245.08:17:49.85#ibcon#about to read 4, iclass 36, count 2 2006.245.08:17:49.85#ibcon#read 4, iclass 36, count 2 2006.245.08:17:49.85#ibcon#about to read 5, iclass 36, count 2 2006.245.08:17:49.85#ibcon#read 5, iclass 36, count 2 2006.245.08:17:49.85#ibcon#about to read 6, iclass 36, count 2 2006.245.08:17:49.85#ibcon#read 6, iclass 36, count 2 2006.245.08:17:49.85#ibcon#end of sib2, iclass 36, count 2 2006.245.08:17:49.85#ibcon#*mode == 0, iclass 36, count 2 2006.245.08:17:49.85#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.08:17:49.85#ibcon#[25=AT01-08\r\n] 2006.245.08:17:49.85#ibcon#*before write, iclass 36, count 2 2006.245.08:17:49.85#ibcon#enter sib2, iclass 36, count 2 2006.245.08:17:49.85#ibcon#flushed, iclass 36, count 2 2006.245.08:17:49.85#ibcon#about to write, iclass 36, count 2 2006.245.08:17:49.85#ibcon#wrote, iclass 36, count 2 2006.245.08:17:49.85#ibcon#about to read 3, iclass 36, count 2 2006.245.08:17:49.88#ibcon#read 3, iclass 36, count 2 2006.245.08:17:49.88#ibcon#about to read 4, iclass 36, count 2 2006.245.08:17:49.88#ibcon#read 4, iclass 36, count 2 2006.245.08:17:49.88#ibcon#about to read 5, iclass 36, count 2 2006.245.08:17:49.88#ibcon#read 5, iclass 36, count 2 2006.245.08:17:49.88#ibcon#about to read 6, iclass 36, count 2 2006.245.08:17:49.88#ibcon#read 6, iclass 36, count 2 2006.245.08:17:49.88#ibcon#end of sib2, iclass 36, count 2 2006.245.08:17:49.88#ibcon#*after write, iclass 36, count 2 2006.245.08:17:49.88#ibcon#*before return 0, iclass 36, count 2 2006.245.08:17:49.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:49.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:49.88#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.08:17:49.88#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:49.88#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:50.00#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:50.00#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:50.00#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:17:50.00#ibcon#first serial, iclass 36, count 0 2006.245.08:17:50.00#ibcon#enter sib2, iclass 36, count 0 2006.245.08:17:50.00#ibcon#flushed, iclass 36, count 0 2006.245.08:17:50.00#ibcon#about to write, iclass 36, count 0 2006.245.08:17:50.00#ibcon#wrote, iclass 36, count 0 2006.245.08:17:50.00#ibcon#about to read 3, iclass 36, count 0 2006.245.08:17:50.02#ibcon#read 3, iclass 36, count 0 2006.245.08:17:50.02#ibcon#about to read 4, iclass 36, count 0 2006.245.08:17:50.02#ibcon#read 4, iclass 36, count 0 2006.245.08:17:50.02#ibcon#about to read 5, iclass 36, count 0 2006.245.08:17:50.02#ibcon#read 5, iclass 36, count 0 2006.245.08:17:50.02#ibcon#about to read 6, iclass 36, count 0 2006.245.08:17:50.02#ibcon#read 6, iclass 36, count 0 2006.245.08:17:50.02#ibcon#end of sib2, iclass 36, count 0 2006.245.08:17:50.02#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:17:50.02#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:17:50.02#ibcon#[25=USB\r\n] 2006.245.08:17:50.02#ibcon#*before write, iclass 36, count 0 2006.245.08:17:50.02#ibcon#enter sib2, iclass 36, count 0 2006.245.08:17:50.02#ibcon#flushed, iclass 36, count 0 2006.245.08:17:50.02#ibcon#about to write, iclass 36, count 0 2006.245.08:17:50.02#ibcon#wrote, iclass 36, count 0 2006.245.08:17:50.02#ibcon#about to read 3, iclass 36, count 0 2006.245.08:17:50.05#ibcon#read 3, iclass 36, count 0 2006.245.08:17:50.05#ibcon#about to read 4, iclass 36, count 0 2006.245.08:17:50.05#ibcon#read 4, iclass 36, count 0 2006.245.08:17:50.05#ibcon#about to read 5, iclass 36, count 0 2006.245.08:17:50.05#ibcon#read 5, iclass 36, count 0 2006.245.08:17:50.05#ibcon#about to read 6, iclass 36, count 0 2006.245.08:17:50.05#ibcon#read 6, iclass 36, count 0 2006.245.08:17:50.05#ibcon#end of sib2, iclass 36, count 0 2006.245.08:17:50.05#ibcon#*after write, iclass 36, count 0 2006.245.08:17:50.05#ibcon#*before return 0, iclass 36, count 0 2006.245.08:17:50.05#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:50.05#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:50.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:17:50.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:17:50.05$vc4f8/valo=2,572.99 2006.245.08:17:50.05#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.08:17:50.05#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.08:17:50.05#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:50.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:50.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:50.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:50.05#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:17:50.05#ibcon#first serial, iclass 38, count 0 2006.245.08:17:50.05#ibcon#enter sib2, iclass 38, count 0 2006.245.08:17:50.05#ibcon#flushed, iclass 38, count 0 2006.245.08:17:50.05#ibcon#about to write, iclass 38, count 0 2006.245.08:17:50.05#ibcon#wrote, iclass 38, count 0 2006.245.08:17:50.05#ibcon#about to read 3, iclass 38, count 0 2006.245.08:17:50.07#ibcon#read 3, iclass 38, count 0 2006.245.08:17:50.07#ibcon#about to read 4, iclass 38, count 0 2006.245.08:17:50.07#ibcon#read 4, iclass 38, count 0 2006.245.08:17:50.07#ibcon#about to read 5, iclass 38, count 0 2006.245.08:17:50.07#ibcon#read 5, iclass 38, count 0 2006.245.08:17:50.07#ibcon#about to read 6, iclass 38, count 0 2006.245.08:17:50.07#ibcon#read 6, iclass 38, count 0 2006.245.08:17:50.07#ibcon#end of sib2, iclass 38, count 0 2006.245.08:17:50.07#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:17:50.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:17:50.07#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:17:50.07#ibcon#*before write, iclass 38, count 0 2006.245.08:17:50.07#ibcon#enter sib2, iclass 38, count 0 2006.245.08:17:50.07#ibcon#flushed, iclass 38, count 0 2006.245.08:17:50.07#ibcon#about to write, iclass 38, count 0 2006.245.08:17:50.07#ibcon#wrote, iclass 38, count 0 2006.245.08:17:50.07#ibcon#about to read 3, iclass 38, count 0 2006.245.08:17:50.12#ibcon#read 3, iclass 38, count 0 2006.245.08:17:50.12#ibcon#about to read 4, iclass 38, count 0 2006.245.08:17:50.12#ibcon#read 4, iclass 38, count 0 2006.245.08:17:50.12#ibcon#about to read 5, iclass 38, count 0 2006.245.08:17:50.12#ibcon#read 5, iclass 38, count 0 2006.245.08:17:50.12#ibcon#about to read 6, iclass 38, count 0 2006.245.08:17:50.12#ibcon#read 6, iclass 38, count 0 2006.245.08:17:50.12#ibcon#end of sib2, iclass 38, count 0 2006.245.08:17:50.12#ibcon#*after write, iclass 38, count 0 2006.245.08:17:50.12#ibcon#*before return 0, iclass 38, count 0 2006.245.08:17:50.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:50.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:50.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:17:50.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:17:50.12$vc4f8/va=2,7 2006.245.08:17:50.12#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.08:17:50.12#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.08:17:50.12#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:50.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:50.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:50.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:50.17#ibcon#enter wrdev, iclass 40, count 2 2006.245.08:17:50.17#ibcon#first serial, iclass 40, count 2 2006.245.08:17:50.17#ibcon#enter sib2, iclass 40, count 2 2006.245.08:17:50.17#ibcon#flushed, iclass 40, count 2 2006.245.08:17:50.17#ibcon#about to write, iclass 40, count 2 2006.245.08:17:50.17#ibcon#wrote, iclass 40, count 2 2006.245.08:17:50.17#ibcon#about to read 3, iclass 40, count 2 2006.245.08:17:50.19#ibcon#read 3, iclass 40, count 2 2006.245.08:17:50.19#ibcon#about to read 4, iclass 40, count 2 2006.245.08:17:50.19#ibcon#read 4, iclass 40, count 2 2006.245.08:17:50.19#ibcon#about to read 5, iclass 40, count 2 2006.245.08:17:50.19#ibcon#read 5, iclass 40, count 2 2006.245.08:17:50.19#ibcon#about to read 6, iclass 40, count 2 2006.245.08:17:50.19#ibcon#read 6, iclass 40, count 2 2006.245.08:17:50.19#ibcon#end of sib2, iclass 40, count 2 2006.245.08:17:50.19#ibcon#*mode == 0, iclass 40, count 2 2006.245.08:17:50.19#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.08:17:50.19#ibcon#[25=AT02-07\r\n] 2006.245.08:17:50.19#ibcon#*before write, iclass 40, count 2 2006.245.08:17:50.19#ibcon#enter sib2, iclass 40, count 2 2006.245.08:17:50.19#ibcon#flushed, iclass 40, count 2 2006.245.08:17:50.19#ibcon#about to write, iclass 40, count 2 2006.245.08:17:50.19#ibcon#wrote, iclass 40, count 2 2006.245.08:17:50.19#ibcon#about to read 3, iclass 40, count 2 2006.245.08:17:50.22#ibcon#read 3, iclass 40, count 2 2006.245.08:17:50.22#ibcon#about to read 4, iclass 40, count 2 2006.245.08:17:50.22#ibcon#read 4, iclass 40, count 2 2006.245.08:17:50.22#ibcon#about to read 5, iclass 40, count 2 2006.245.08:17:50.22#ibcon#read 5, iclass 40, count 2 2006.245.08:17:50.22#ibcon#about to read 6, iclass 40, count 2 2006.245.08:17:50.22#ibcon#read 6, iclass 40, count 2 2006.245.08:17:50.22#ibcon#end of sib2, iclass 40, count 2 2006.245.08:17:50.22#ibcon#*after write, iclass 40, count 2 2006.245.08:17:50.22#ibcon#*before return 0, iclass 40, count 2 2006.245.08:17:50.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:50.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:50.22#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.08:17:50.22#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:50.22#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:50.34#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:50.34#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:50.34#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:17:50.34#ibcon#first serial, iclass 40, count 0 2006.245.08:17:50.34#ibcon#enter sib2, iclass 40, count 0 2006.245.08:17:50.34#ibcon#flushed, iclass 40, count 0 2006.245.08:17:50.34#ibcon#about to write, iclass 40, count 0 2006.245.08:17:50.34#ibcon#wrote, iclass 40, count 0 2006.245.08:17:50.34#ibcon#about to read 3, iclass 40, count 0 2006.245.08:17:50.36#ibcon#read 3, iclass 40, count 0 2006.245.08:17:50.36#ibcon#about to read 4, iclass 40, count 0 2006.245.08:17:50.36#ibcon#read 4, iclass 40, count 0 2006.245.08:17:50.36#ibcon#about to read 5, iclass 40, count 0 2006.245.08:17:50.36#ibcon#read 5, iclass 40, count 0 2006.245.08:17:50.36#ibcon#about to read 6, iclass 40, count 0 2006.245.08:17:50.36#ibcon#read 6, iclass 40, count 0 2006.245.08:17:50.36#ibcon#end of sib2, iclass 40, count 0 2006.245.08:17:50.36#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:17:50.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:17:50.36#ibcon#[25=USB\r\n] 2006.245.08:17:50.36#ibcon#*before write, iclass 40, count 0 2006.245.08:17:50.36#ibcon#enter sib2, iclass 40, count 0 2006.245.08:17:50.36#ibcon#flushed, iclass 40, count 0 2006.245.08:17:50.36#ibcon#about to write, iclass 40, count 0 2006.245.08:17:50.36#ibcon#wrote, iclass 40, count 0 2006.245.08:17:50.36#ibcon#about to read 3, iclass 40, count 0 2006.245.08:17:50.39#ibcon#read 3, iclass 40, count 0 2006.245.08:17:50.39#ibcon#about to read 4, iclass 40, count 0 2006.245.08:17:50.39#ibcon#read 4, iclass 40, count 0 2006.245.08:17:50.39#ibcon#about to read 5, iclass 40, count 0 2006.245.08:17:50.39#ibcon#read 5, iclass 40, count 0 2006.245.08:17:50.39#ibcon#about to read 6, iclass 40, count 0 2006.245.08:17:50.39#ibcon#read 6, iclass 40, count 0 2006.245.08:17:50.39#ibcon#end of sib2, iclass 40, count 0 2006.245.08:17:50.39#ibcon#*after write, iclass 40, count 0 2006.245.08:17:50.39#ibcon#*before return 0, iclass 40, count 0 2006.245.08:17:50.39#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:50.39#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:50.39#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:17:50.39#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:17:50.39$vc4f8/valo=3,672.99 2006.245.08:17:50.39#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.08:17:50.39#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.08:17:50.39#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:50.39#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:50.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:50.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:50.39#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:17:50.39#ibcon#first serial, iclass 4, count 0 2006.245.08:17:50.39#ibcon#enter sib2, iclass 4, count 0 2006.245.08:17:50.39#ibcon#flushed, iclass 4, count 0 2006.245.08:17:50.39#ibcon#about to write, iclass 4, count 0 2006.245.08:17:50.39#ibcon#wrote, iclass 4, count 0 2006.245.08:17:50.39#ibcon#about to read 3, iclass 4, count 0 2006.245.08:17:50.41#ibcon#read 3, iclass 4, count 0 2006.245.08:17:50.41#ibcon#about to read 4, iclass 4, count 0 2006.245.08:17:50.41#ibcon#read 4, iclass 4, count 0 2006.245.08:17:50.41#ibcon#about to read 5, iclass 4, count 0 2006.245.08:17:50.41#ibcon#read 5, iclass 4, count 0 2006.245.08:17:50.41#ibcon#about to read 6, iclass 4, count 0 2006.245.08:17:50.41#ibcon#read 6, iclass 4, count 0 2006.245.08:17:50.41#ibcon#end of sib2, iclass 4, count 0 2006.245.08:17:50.41#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:17:50.41#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:17:50.41#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:17:50.41#ibcon#*before write, iclass 4, count 0 2006.245.08:17:50.41#ibcon#enter sib2, iclass 4, count 0 2006.245.08:17:50.41#ibcon#flushed, iclass 4, count 0 2006.245.08:17:50.41#ibcon#about to write, iclass 4, count 0 2006.245.08:17:50.41#ibcon#wrote, iclass 4, count 0 2006.245.08:17:50.41#ibcon#about to read 3, iclass 4, count 0 2006.245.08:17:50.46#ibcon#read 3, iclass 4, count 0 2006.245.08:17:50.46#ibcon#about to read 4, iclass 4, count 0 2006.245.08:17:50.46#ibcon#read 4, iclass 4, count 0 2006.245.08:17:50.46#ibcon#about to read 5, iclass 4, count 0 2006.245.08:17:50.46#ibcon#read 5, iclass 4, count 0 2006.245.08:17:50.46#ibcon#about to read 6, iclass 4, count 0 2006.245.08:17:50.46#ibcon#read 6, iclass 4, count 0 2006.245.08:17:50.46#ibcon#end of sib2, iclass 4, count 0 2006.245.08:17:50.46#ibcon#*after write, iclass 4, count 0 2006.245.08:17:50.46#ibcon#*before return 0, iclass 4, count 0 2006.245.08:17:50.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:50.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:50.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:17:50.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:17:50.46$vc4f8/va=3,6 2006.245.08:17:50.46#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.08:17:50.46#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.08:17:50.46#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:50.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:50.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:50.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:50.51#ibcon#enter wrdev, iclass 6, count 2 2006.245.08:17:50.51#ibcon#first serial, iclass 6, count 2 2006.245.08:17:50.51#ibcon#enter sib2, iclass 6, count 2 2006.245.08:17:50.51#ibcon#flushed, iclass 6, count 2 2006.245.08:17:50.51#ibcon#about to write, iclass 6, count 2 2006.245.08:17:50.51#ibcon#wrote, iclass 6, count 2 2006.245.08:17:50.51#ibcon#about to read 3, iclass 6, count 2 2006.245.08:17:50.53#ibcon#read 3, iclass 6, count 2 2006.245.08:17:50.53#ibcon#about to read 4, iclass 6, count 2 2006.245.08:17:50.53#ibcon#read 4, iclass 6, count 2 2006.245.08:17:50.53#ibcon#about to read 5, iclass 6, count 2 2006.245.08:17:50.53#ibcon#read 5, iclass 6, count 2 2006.245.08:17:50.53#ibcon#about to read 6, iclass 6, count 2 2006.245.08:17:50.53#ibcon#read 6, iclass 6, count 2 2006.245.08:17:50.53#ibcon#end of sib2, iclass 6, count 2 2006.245.08:17:50.53#ibcon#*mode == 0, iclass 6, count 2 2006.245.08:17:50.53#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.08:17:50.53#ibcon#[25=AT03-06\r\n] 2006.245.08:17:50.53#ibcon#*before write, iclass 6, count 2 2006.245.08:17:50.53#ibcon#enter sib2, iclass 6, count 2 2006.245.08:17:50.53#ibcon#flushed, iclass 6, count 2 2006.245.08:17:50.53#ibcon#about to write, iclass 6, count 2 2006.245.08:17:50.53#ibcon#wrote, iclass 6, count 2 2006.245.08:17:50.53#ibcon#about to read 3, iclass 6, count 2 2006.245.08:17:50.56#ibcon#read 3, iclass 6, count 2 2006.245.08:17:50.56#ibcon#about to read 4, iclass 6, count 2 2006.245.08:17:50.56#ibcon#read 4, iclass 6, count 2 2006.245.08:17:50.56#ibcon#about to read 5, iclass 6, count 2 2006.245.08:17:50.56#ibcon#read 5, iclass 6, count 2 2006.245.08:17:50.56#ibcon#about to read 6, iclass 6, count 2 2006.245.08:17:50.56#ibcon#read 6, iclass 6, count 2 2006.245.08:17:50.56#ibcon#end of sib2, iclass 6, count 2 2006.245.08:17:50.56#ibcon#*after write, iclass 6, count 2 2006.245.08:17:50.56#ibcon#*before return 0, iclass 6, count 2 2006.245.08:17:50.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:50.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:50.56#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.08:17:50.56#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:50.56#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:50.68#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:50.68#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:50.68#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:17:50.68#ibcon#first serial, iclass 6, count 0 2006.245.08:17:50.68#ibcon#enter sib2, iclass 6, count 0 2006.245.08:17:50.68#ibcon#flushed, iclass 6, count 0 2006.245.08:17:50.68#ibcon#about to write, iclass 6, count 0 2006.245.08:17:50.68#ibcon#wrote, iclass 6, count 0 2006.245.08:17:50.68#ibcon#about to read 3, iclass 6, count 0 2006.245.08:17:50.70#ibcon#read 3, iclass 6, count 0 2006.245.08:17:50.70#ibcon#about to read 4, iclass 6, count 0 2006.245.08:17:50.70#ibcon#read 4, iclass 6, count 0 2006.245.08:17:50.70#ibcon#about to read 5, iclass 6, count 0 2006.245.08:17:50.70#ibcon#read 5, iclass 6, count 0 2006.245.08:17:50.70#ibcon#about to read 6, iclass 6, count 0 2006.245.08:17:50.70#ibcon#read 6, iclass 6, count 0 2006.245.08:17:50.70#ibcon#end of sib2, iclass 6, count 0 2006.245.08:17:50.70#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:17:50.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:17:50.70#ibcon#[25=USB\r\n] 2006.245.08:17:50.70#ibcon#*before write, iclass 6, count 0 2006.245.08:17:50.70#ibcon#enter sib2, iclass 6, count 0 2006.245.08:17:50.70#ibcon#flushed, iclass 6, count 0 2006.245.08:17:50.70#ibcon#about to write, iclass 6, count 0 2006.245.08:17:50.70#ibcon#wrote, iclass 6, count 0 2006.245.08:17:50.70#ibcon#about to read 3, iclass 6, count 0 2006.245.08:17:50.73#ibcon#read 3, iclass 6, count 0 2006.245.08:17:50.73#ibcon#about to read 4, iclass 6, count 0 2006.245.08:17:50.73#ibcon#read 4, iclass 6, count 0 2006.245.08:17:50.73#ibcon#about to read 5, iclass 6, count 0 2006.245.08:17:50.73#ibcon#read 5, iclass 6, count 0 2006.245.08:17:50.73#ibcon#about to read 6, iclass 6, count 0 2006.245.08:17:50.73#ibcon#read 6, iclass 6, count 0 2006.245.08:17:50.73#ibcon#end of sib2, iclass 6, count 0 2006.245.08:17:50.73#ibcon#*after write, iclass 6, count 0 2006.245.08:17:50.73#ibcon#*before return 0, iclass 6, count 0 2006.245.08:17:50.73#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:50.73#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:50.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:17:50.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:17:50.73$vc4f8/valo=4,832.99 2006.245.08:17:50.73#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.08:17:50.73#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.08:17:50.73#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:50.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:50.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:50.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:50.73#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:17:50.73#ibcon#first serial, iclass 10, count 0 2006.245.08:17:50.73#ibcon#enter sib2, iclass 10, count 0 2006.245.08:17:50.73#ibcon#flushed, iclass 10, count 0 2006.245.08:17:50.73#ibcon#about to write, iclass 10, count 0 2006.245.08:17:50.73#ibcon#wrote, iclass 10, count 0 2006.245.08:17:50.73#ibcon#about to read 3, iclass 10, count 0 2006.245.08:17:50.75#ibcon#read 3, iclass 10, count 0 2006.245.08:17:50.75#ibcon#about to read 4, iclass 10, count 0 2006.245.08:17:50.75#ibcon#read 4, iclass 10, count 0 2006.245.08:17:50.75#ibcon#about to read 5, iclass 10, count 0 2006.245.08:17:50.75#ibcon#read 5, iclass 10, count 0 2006.245.08:17:50.75#ibcon#about to read 6, iclass 10, count 0 2006.245.08:17:50.75#ibcon#read 6, iclass 10, count 0 2006.245.08:17:50.75#ibcon#end of sib2, iclass 10, count 0 2006.245.08:17:50.75#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:17:50.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:17:50.75#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:17:50.75#ibcon#*before write, iclass 10, count 0 2006.245.08:17:50.75#ibcon#enter sib2, iclass 10, count 0 2006.245.08:17:50.75#ibcon#flushed, iclass 10, count 0 2006.245.08:17:50.75#ibcon#about to write, iclass 10, count 0 2006.245.08:17:50.75#ibcon#wrote, iclass 10, count 0 2006.245.08:17:50.75#ibcon#about to read 3, iclass 10, count 0 2006.245.08:17:50.79#ibcon#read 3, iclass 10, count 0 2006.245.08:17:50.79#ibcon#about to read 4, iclass 10, count 0 2006.245.08:17:50.79#ibcon#read 4, iclass 10, count 0 2006.245.08:17:50.79#ibcon#about to read 5, iclass 10, count 0 2006.245.08:17:50.79#ibcon#read 5, iclass 10, count 0 2006.245.08:17:50.79#ibcon#about to read 6, iclass 10, count 0 2006.245.08:17:50.79#ibcon#read 6, iclass 10, count 0 2006.245.08:17:50.79#ibcon#end of sib2, iclass 10, count 0 2006.245.08:17:50.79#ibcon#*after write, iclass 10, count 0 2006.245.08:17:50.79#ibcon#*before return 0, iclass 10, count 0 2006.245.08:17:50.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:50.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:50.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:17:50.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:17:50.79$vc4f8/va=4,7 2006.245.08:17:50.79#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.08:17:50.79#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.08:17:50.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:50.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:50.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:50.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:50.85#ibcon#enter wrdev, iclass 12, count 2 2006.245.08:17:50.85#ibcon#first serial, iclass 12, count 2 2006.245.08:17:50.85#ibcon#enter sib2, iclass 12, count 2 2006.245.08:17:50.85#ibcon#flushed, iclass 12, count 2 2006.245.08:17:50.85#ibcon#about to write, iclass 12, count 2 2006.245.08:17:50.85#ibcon#wrote, iclass 12, count 2 2006.245.08:17:50.85#ibcon#about to read 3, iclass 12, count 2 2006.245.08:17:50.87#ibcon#read 3, iclass 12, count 2 2006.245.08:17:50.87#ibcon#about to read 4, iclass 12, count 2 2006.245.08:17:50.87#ibcon#read 4, iclass 12, count 2 2006.245.08:17:50.87#ibcon#about to read 5, iclass 12, count 2 2006.245.08:17:50.87#ibcon#read 5, iclass 12, count 2 2006.245.08:17:50.87#ibcon#about to read 6, iclass 12, count 2 2006.245.08:17:50.87#ibcon#read 6, iclass 12, count 2 2006.245.08:17:50.87#ibcon#end of sib2, iclass 12, count 2 2006.245.08:17:50.87#ibcon#*mode == 0, iclass 12, count 2 2006.245.08:17:50.87#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.08:17:50.87#ibcon#[25=AT04-07\r\n] 2006.245.08:17:50.87#ibcon#*before write, iclass 12, count 2 2006.245.08:17:50.87#ibcon#enter sib2, iclass 12, count 2 2006.245.08:17:50.87#ibcon#flushed, iclass 12, count 2 2006.245.08:17:50.87#ibcon#about to write, iclass 12, count 2 2006.245.08:17:50.87#ibcon#wrote, iclass 12, count 2 2006.245.08:17:50.87#ibcon#about to read 3, iclass 12, count 2 2006.245.08:17:50.90#ibcon#read 3, iclass 12, count 2 2006.245.08:17:50.90#ibcon#about to read 4, iclass 12, count 2 2006.245.08:17:50.90#ibcon#read 4, iclass 12, count 2 2006.245.08:17:50.90#ibcon#about to read 5, iclass 12, count 2 2006.245.08:17:50.90#ibcon#read 5, iclass 12, count 2 2006.245.08:17:50.90#ibcon#about to read 6, iclass 12, count 2 2006.245.08:17:50.90#ibcon#read 6, iclass 12, count 2 2006.245.08:17:50.90#ibcon#end of sib2, iclass 12, count 2 2006.245.08:17:50.90#ibcon#*after write, iclass 12, count 2 2006.245.08:17:50.90#ibcon#*before return 0, iclass 12, count 2 2006.245.08:17:50.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:50.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:50.90#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.08:17:50.90#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:50.90#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:51.02#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:51.02#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:51.02#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:17:51.02#ibcon#first serial, iclass 12, count 0 2006.245.08:17:51.02#ibcon#enter sib2, iclass 12, count 0 2006.245.08:17:51.02#ibcon#flushed, iclass 12, count 0 2006.245.08:17:51.02#ibcon#about to write, iclass 12, count 0 2006.245.08:17:51.02#ibcon#wrote, iclass 12, count 0 2006.245.08:17:51.02#ibcon#about to read 3, iclass 12, count 0 2006.245.08:17:51.04#ibcon#read 3, iclass 12, count 0 2006.245.08:17:51.04#ibcon#about to read 4, iclass 12, count 0 2006.245.08:17:51.04#ibcon#read 4, iclass 12, count 0 2006.245.08:17:51.04#ibcon#about to read 5, iclass 12, count 0 2006.245.08:17:51.04#ibcon#read 5, iclass 12, count 0 2006.245.08:17:51.04#ibcon#about to read 6, iclass 12, count 0 2006.245.08:17:51.04#ibcon#read 6, iclass 12, count 0 2006.245.08:17:51.04#ibcon#end of sib2, iclass 12, count 0 2006.245.08:17:51.04#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:17:51.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:17:51.04#ibcon#[25=USB\r\n] 2006.245.08:17:51.04#ibcon#*before write, iclass 12, count 0 2006.245.08:17:51.04#ibcon#enter sib2, iclass 12, count 0 2006.245.08:17:51.04#ibcon#flushed, iclass 12, count 0 2006.245.08:17:51.04#ibcon#about to write, iclass 12, count 0 2006.245.08:17:51.04#ibcon#wrote, iclass 12, count 0 2006.245.08:17:51.04#ibcon#about to read 3, iclass 12, count 0 2006.245.08:17:51.07#ibcon#read 3, iclass 12, count 0 2006.245.08:17:51.07#ibcon#about to read 4, iclass 12, count 0 2006.245.08:17:51.07#ibcon#read 4, iclass 12, count 0 2006.245.08:17:51.07#ibcon#about to read 5, iclass 12, count 0 2006.245.08:17:51.07#ibcon#read 5, iclass 12, count 0 2006.245.08:17:51.07#ibcon#about to read 6, iclass 12, count 0 2006.245.08:17:51.07#ibcon#read 6, iclass 12, count 0 2006.245.08:17:51.07#ibcon#end of sib2, iclass 12, count 0 2006.245.08:17:51.07#ibcon#*after write, iclass 12, count 0 2006.245.08:17:51.07#ibcon#*before return 0, iclass 12, count 0 2006.245.08:17:51.07#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:51.07#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:51.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:17:51.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:17:51.07$vc4f8/valo=5,652.99 2006.245.08:17:51.07#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.08:17:51.07#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.08:17:51.07#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:51.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:51.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:51.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:51.07#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:17:51.07#ibcon#first serial, iclass 14, count 0 2006.245.08:17:51.07#ibcon#enter sib2, iclass 14, count 0 2006.245.08:17:51.07#ibcon#flushed, iclass 14, count 0 2006.245.08:17:51.07#ibcon#about to write, iclass 14, count 0 2006.245.08:17:51.07#ibcon#wrote, iclass 14, count 0 2006.245.08:17:51.07#ibcon#about to read 3, iclass 14, count 0 2006.245.08:17:51.09#ibcon#read 3, iclass 14, count 0 2006.245.08:17:51.09#ibcon#about to read 4, iclass 14, count 0 2006.245.08:17:51.09#ibcon#read 4, iclass 14, count 0 2006.245.08:17:51.09#ibcon#about to read 5, iclass 14, count 0 2006.245.08:17:51.09#ibcon#read 5, iclass 14, count 0 2006.245.08:17:51.09#ibcon#about to read 6, iclass 14, count 0 2006.245.08:17:51.09#ibcon#read 6, iclass 14, count 0 2006.245.08:17:51.09#ibcon#end of sib2, iclass 14, count 0 2006.245.08:17:51.09#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:17:51.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:17:51.09#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:17:51.09#ibcon#*before write, iclass 14, count 0 2006.245.08:17:51.09#ibcon#enter sib2, iclass 14, count 0 2006.245.08:17:51.09#ibcon#flushed, iclass 14, count 0 2006.245.08:17:51.09#ibcon#about to write, iclass 14, count 0 2006.245.08:17:51.09#ibcon#wrote, iclass 14, count 0 2006.245.08:17:51.09#ibcon#about to read 3, iclass 14, count 0 2006.245.08:17:51.13#ibcon#read 3, iclass 14, count 0 2006.245.08:17:51.13#ibcon#about to read 4, iclass 14, count 0 2006.245.08:17:51.13#ibcon#read 4, iclass 14, count 0 2006.245.08:17:51.13#ibcon#about to read 5, iclass 14, count 0 2006.245.08:17:51.13#ibcon#read 5, iclass 14, count 0 2006.245.08:17:51.13#ibcon#about to read 6, iclass 14, count 0 2006.245.08:17:51.13#ibcon#read 6, iclass 14, count 0 2006.245.08:17:51.13#ibcon#end of sib2, iclass 14, count 0 2006.245.08:17:51.13#ibcon#*after write, iclass 14, count 0 2006.245.08:17:51.13#ibcon#*before return 0, iclass 14, count 0 2006.245.08:17:51.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:51.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:51.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:17:51.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:17:51.13$vc4f8/va=5,7 2006.245.08:17:51.13#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:17:51.13#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:17:51.13#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:51.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:51.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:51.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:51.19#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:17:51.19#ibcon#first serial, iclass 16, count 2 2006.245.08:17:51.19#ibcon#enter sib2, iclass 16, count 2 2006.245.08:17:51.19#ibcon#flushed, iclass 16, count 2 2006.245.08:17:51.19#ibcon#about to write, iclass 16, count 2 2006.245.08:17:51.19#ibcon#wrote, iclass 16, count 2 2006.245.08:17:51.19#ibcon#about to read 3, iclass 16, count 2 2006.245.08:17:51.21#ibcon#read 3, iclass 16, count 2 2006.245.08:17:51.21#ibcon#about to read 4, iclass 16, count 2 2006.245.08:17:51.21#ibcon#read 4, iclass 16, count 2 2006.245.08:17:51.21#ibcon#about to read 5, iclass 16, count 2 2006.245.08:17:51.21#ibcon#read 5, iclass 16, count 2 2006.245.08:17:51.21#ibcon#about to read 6, iclass 16, count 2 2006.245.08:17:51.21#ibcon#read 6, iclass 16, count 2 2006.245.08:17:51.21#ibcon#end of sib2, iclass 16, count 2 2006.245.08:17:51.21#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:17:51.21#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:17:51.21#ibcon#[25=AT05-07\r\n] 2006.245.08:17:51.21#ibcon#*before write, iclass 16, count 2 2006.245.08:17:51.21#ibcon#enter sib2, iclass 16, count 2 2006.245.08:17:51.21#ibcon#flushed, iclass 16, count 2 2006.245.08:17:51.21#ibcon#about to write, iclass 16, count 2 2006.245.08:17:51.21#ibcon#wrote, iclass 16, count 2 2006.245.08:17:51.21#ibcon#about to read 3, iclass 16, count 2 2006.245.08:17:51.24#ibcon#read 3, iclass 16, count 2 2006.245.08:17:51.24#ibcon#about to read 4, iclass 16, count 2 2006.245.08:17:51.24#ibcon#read 4, iclass 16, count 2 2006.245.08:17:51.24#ibcon#about to read 5, iclass 16, count 2 2006.245.08:17:51.24#ibcon#read 5, iclass 16, count 2 2006.245.08:17:51.24#ibcon#about to read 6, iclass 16, count 2 2006.245.08:17:51.24#ibcon#read 6, iclass 16, count 2 2006.245.08:17:51.24#ibcon#end of sib2, iclass 16, count 2 2006.245.08:17:51.24#ibcon#*after write, iclass 16, count 2 2006.245.08:17:51.24#ibcon#*before return 0, iclass 16, count 2 2006.245.08:17:51.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:51.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:51.24#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:17:51.24#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:51.24#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:51.36#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:51.36#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:51.36#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:17:51.36#ibcon#first serial, iclass 16, count 0 2006.245.08:17:51.36#ibcon#enter sib2, iclass 16, count 0 2006.245.08:17:51.36#ibcon#flushed, iclass 16, count 0 2006.245.08:17:51.36#ibcon#about to write, iclass 16, count 0 2006.245.08:17:51.36#ibcon#wrote, iclass 16, count 0 2006.245.08:17:51.36#ibcon#about to read 3, iclass 16, count 0 2006.245.08:17:51.38#ibcon#read 3, iclass 16, count 0 2006.245.08:17:51.38#ibcon#about to read 4, iclass 16, count 0 2006.245.08:17:51.38#ibcon#read 4, iclass 16, count 0 2006.245.08:17:51.38#ibcon#about to read 5, iclass 16, count 0 2006.245.08:17:51.38#ibcon#read 5, iclass 16, count 0 2006.245.08:17:51.38#ibcon#about to read 6, iclass 16, count 0 2006.245.08:17:51.38#ibcon#read 6, iclass 16, count 0 2006.245.08:17:51.38#ibcon#end of sib2, iclass 16, count 0 2006.245.08:17:51.38#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:17:51.38#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:17:51.38#ibcon#[25=USB\r\n] 2006.245.08:17:51.38#ibcon#*before write, iclass 16, count 0 2006.245.08:17:51.38#ibcon#enter sib2, iclass 16, count 0 2006.245.08:17:51.38#ibcon#flushed, iclass 16, count 0 2006.245.08:17:51.38#ibcon#about to write, iclass 16, count 0 2006.245.08:17:51.38#ibcon#wrote, iclass 16, count 0 2006.245.08:17:51.38#ibcon#about to read 3, iclass 16, count 0 2006.245.08:17:51.41#ibcon#read 3, iclass 16, count 0 2006.245.08:17:51.41#ibcon#about to read 4, iclass 16, count 0 2006.245.08:17:51.41#ibcon#read 4, iclass 16, count 0 2006.245.08:17:51.41#ibcon#about to read 5, iclass 16, count 0 2006.245.08:17:51.41#ibcon#read 5, iclass 16, count 0 2006.245.08:17:51.41#ibcon#about to read 6, iclass 16, count 0 2006.245.08:17:51.41#ibcon#read 6, iclass 16, count 0 2006.245.08:17:51.41#ibcon#end of sib2, iclass 16, count 0 2006.245.08:17:51.41#ibcon#*after write, iclass 16, count 0 2006.245.08:17:51.41#ibcon#*before return 0, iclass 16, count 0 2006.245.08:17:51.41#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:51.41#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:51.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:17:51.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:17:51.41$vc4f8/valo=6,772.99 2006.245.08:17:51.41#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.245.08:17:51.41#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.245.08:17:51.41#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:51.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:17:51.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:17:51.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:17:51.41#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:17:51.41#ibcon#first serial, iclass 18, count 0 2006.245.08:17:51.41#ibcon#enter sib2, iclass 18, count 0 2006.245.08:17:51.41#ibcon#flushed, iclass 18, count 0 2006.245.08:17:51.41#ibcon#about to write, iclass 18, count 0 2006.245.08:17:51.41#ibcon#wrote, iclass 18, count 0 2006.245.08:17:51.41#ibcon#about to read 3, iclass 18, count 0 2006.245.08:17:51.43#ibcon#read 3, iclass 18, count 0 2006.245.08:17:51.43#ibcon#about to read 4, iclass 18, count 0 2006.245.08:17:51.43#ibcon#read 4, iclass 18, count 0 2006.245.08:17:51.43#ibcon#about to read 5, iclass 18, count 0 2006.245.08:17:51.43#ibcon#read 5, iclass 18, count 0 2006.245.08:17:51.43#ibcon#about to read 6, iclass 18, count 0 2006.245.08:17:51.43#ibcon#read 6, iclass 18, count 0 2006.245.08:17:51.43#ibcon#end of sib2, iclass 18, count 0 2006.245.08:17:51.43#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:17:51.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:17:51.43#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:17:51.43#ibcon#*before write, iclass 18, count 0 2006.245.08:17:51.43#ibcon#enter sib2, iclass 18, count 0 2006.245.08:17:51.43#ibcon#flushed, iclass 18, count 0 2006.245.08:17:51.43#ibcon#about to write, iclass 18, count 0 2006.245.08:17:51.43#ibcon#wrote, iclass 18, count 0 2006.245.08:17:51.43#ibcon#about to read 3, iclass 18, count 0 2006.245.08:17:51.47#ibcon#read 3, iclass 18, count 0 2006.245.08:17:51.47#ibcon#about to read 4, iclass 18, count 0 2006.245.08:17:51.47#ibcon#read 4, iclass 18, count 0 2006.245.08:17:51.47#ibcon#about to read 5, iclass 18, count 0 2006.245.08:17:51.47#ibcon#read 5, iclass 18, count 0 2006.245.08:17:51.47#ibcon#about to read 6, iclass 18, count 0 2006.245.08:17:51.47#ibcon#read 6, iclass 18, count 0 2006.245.08:17:51.47#ibcon#end of sib2, iclass 18, count 0 2006.245.08:17:51.47#ibcon#*after write, iclass 18, count 0 2006.245.08:17:51.47#ibcon#*before return 0, iclass 18, count 0 2006.245.08:17:51.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:17:51.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.245.08:17:51.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:17:51.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:17:51.47$vc4f8/va=6,7 2006.245.08:17:51.47#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.245.08:17:51.47#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.245.08:17:51.47#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:51.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:17:51.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:17:51.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:17:51.53#ibcon#enter wrdev, iclass 20, count 2 2006.245.08:17:51.53#ibcon#first serial, iclass 20, count 2 2006.245.08:17:51.53#ibcon#enter sib2, iclass 20, count 2 2006.245.08:17:51.53#ibcon#flushed, iclass 20, count 2 2006.245.08:17:51.53#ibcon#about to write, iclass 20, count 2 2006.245.08:17:51.53#ibcon#wrote, iclass 20, count 2 2006.245.08:17:51.53#ibcon#about to read 3, iclass 20, count 2 2006.245.08:17:51.55#ibcon#read 3, iclass 20, count 2 2006.245.08:17:51.55#ibcon#about to read 4, iclass 20, count 2 2006.245.08:17:51.55#ibcon#read 4, iclass 20, count 2 2006.245.08:17:51.55#ibcon#about to read 5, iclass 20, count 2 2006.245.08:17:51.55#ibcon#read 5, iclass 20, count 2 2006.245.08:17:51.55#ibcon#about to read 6, iclass 20, count 2 2006.245.08:17:51.55#ibcon#read 6, iclass 20, count 2 2006.245.08:17:51.55#ibcon#end of sib2, iclass 20, count 2 2006.245.08:17:51.55#ibcon#*mode == 0, iclass 20, count 2 2006.245.08:17:51.55#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.245.08:17:51.55#ibcon#[25=AT06-07\r\n] 2006.245.08:17:51.55#ibcon#*before write, iclass 20, count 2 2006.245.08:17:51.55#ibcon#enter sib2, iclass 20, count 2 2006.245.08:17:51.55#ibcon#flushed, iclass 20, count 2 2006.245.08:17:51.55#ibcon#about to write, iclass 20, count 2 2006.245.08:17:51.55#ibcon#wrote, iclass 20, count 2 2006.245.08:17:51.55#ibcon#about to read 3, iclass 20, count 2 2006.245.08:17:51.58#ibcon#read 3, iclass 20, count 2 2006.245.08:17:51.58#ibcon#about to read 4, iclass 20, count 2 2006.245.08:17:51.58#ibcon#read 4, iclass 20, count 2 2006.245.08:17:51.58#ibcon#about to read 5, iclass 20, count 2 2006.245.08:17:51.58#ibcon#read 5, iclass 20, count 2 2006.245.08:17:51.58#ibcon#about to read 6, iclass 20, count 2 2006.245.08:17:51.58#ibcon#read 6, iclass 20, count 2 2006.245.08:17:51.58#ibcon#end of sib2, iclass 20, count 2 2006.245.08:17:51.58#ibcon#*after write, iclass 20, count 2 2006.245.08:17:51.58#ibcon#*before return 0, iclass 20, count 2 2006.245.08:17:51.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:17:51.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.245.08:17:51.58#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.245.08:17:51.58#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:51.58#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:17:51.70#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:17:51.70#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:17:51.70#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:17:51.70#ibcon#first serial, iclass 20, count 0 2006.245.08:17:51.70#ibcon#enter sib2, iclass 20, count 0 2006.245.08:17:51.70#ibcon#flushed, iclass 20, count 0 2006.245.08:17:51.70#ibcon#about to write, iclass 20, count 0 2006.245.08:17:51.70#ibcon#wrote, iclass 20, count 0 2006.245.08:17:51.70#ibcon#about to read 3, iclass 20, count 0 2006.245.08:17:51.72#ibcon#read 3, iclass 20, count 0 2006.245.08:17:51.72#ibcon#about to read 4, iclass 20, count 0 2006.245.08:17:51.72#ibcon#read 4, iclass 20, count 0 2006.245.08:17:51.72#ibcon#about to read 5, iclass 20, count 0 2006.245.08:17:51.72#ibcon#read 5, iclass 20, count 0 2006.245.08:17:51.72#ibcon#about to read 6, iclass 20, count 0 2006.245.08:17:51.72#ibcon#read 6, iclass 20, count 0 2006.245.08:17:51.72#ibcon#end of sib2, iclass 20, count 0 2006.245.08:17:51.72#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:17:51.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:17:51.72#ibcon#[25=USB\r\n] 2006.245.08:17:51.72#ibcon#*before write, iclass 20, count 0 2006.245.08:17:51.72#ibcon#enter sib2, iclass 20, count 0 2006.245.08:17:51.72#ibcon#flushed, iclass 20, count 0 2006.245.08:17:51.72#ibcon#about to write, iclass 20, count 0 2006.245.08:17:51.72#ibcon#wrote, iclass 20, count 0 2006.245.08:17:51.72#ibcon#about to read 3, iclass 20, count 0 2006.245.08:17:51.75#ibcon#read 3, iclass 20, count 0 2006.245.08:17:51.75#ibcon#about to read 4, iclass 20, count 0 2006.245.08:17:51.75#ibcon#read 4, iclass 20, count 0 2006.245.08:17:51.75#ibcon#about to read 5, iclass 20, count 0 2006.245.08:17:51.75#ibcon#read 5, iclass 20, count 0 2006.245.08:17:51.75#ibcon#about to read 6, iclass 20, count 0 2006.245.08:17:51.75#ibcon#read 6, iclass 20, count 0 2006.245.08:17:51.75#ibcon#end of sib2, iclass 20, count 0 2006.245.08:17:51.75#ibcon#*after write, iclass 20, count 0 2006.245.08:17:51.75#ibcon#*before return 0, iclass 20, count 0 2006.245.08:17:51.75#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:17:51.75#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.245.08:17:51.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:17:51.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:17:51.75$vc4f8/valo=7,832.99 2006.245.08:17:51.75#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:17:51.75#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:17:51.75#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:51.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:51.75#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:51.75#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:51.75#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:17:51.75#ibcon#first serial, iclass 22, count 0 2006.245.08:17:51.75#ibcon#enter sib2, iclass 22, count 0 2006.245.08:17:51.75#ibcon#flushed, iclass 22, count 0 2006.245.08:17:51.75#ibcon#about to write, iclass 22, count 0 2006.245.08:17:51.75#ibcon#wrote, iclass 22, count 0 2006.245.08:17:51.75#ibcon#about to read 3, iclass 22, count 0 2006.245.08:17:51.77#ibcon#read 3, iclass 22, count 0 2006.245.08:17:51.77#ibcon#about to read 4, iclass 22, count 0 2006.245.08:17:51.77#ibcon#read 4, iclass 22, count 0 2006.245.08:17:51.77#ibcon#about to read 5, iclass 22, count 0 2006.245.08:17:51.77#ibcon#read 5, iclass 22, count 0 2006.245.08:17:51.77#ibcon#about to read 6, iclass 22, count 0 2006.245.08:17:51.77#ibcon#read 6, iclass 22, count 0 2006.245.08:17:51.77#ibcon#end of sib2, iclass 22, count 0 2006.245.08:17:51.77#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:17:51.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:17:51.77#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:17:51.77#ibcon#*before write, iclass 22, count 0 2006.245.08:17:51.77#ibcon#enter sib2, iclass 22, count 0 2006.245.08:17:51.77#ibcon#flushed, iclass 22, count 0 2006.245.08:17:51.77#ibcon#about to write, iclass 22, count 0 2006.245.08:17:51.77#ibcon#wrote, iclass 22, count 0 2006.245.08:17:51.77#ibcon#about to read 3, iclass 22, count 0 2006.245.08:17:51.81#ibcon#read 3, iclass 22, count 0 2006.245.08:17:51.81#ibcon#about to read 4, iclass 22, count 0 2006.245.08:17:51.81#ibcon#read 4, iclass 22, count 0 2006.245.08:17:51.81#ibcon#about to read 5, iclass 22, count 0 2006.245.08:17:51.81#ibcon#read 5, iclass 22, count 0 2006.245.08:17:51.81#ibcon#about to read 6, iclass 22, count 0 2006.245.08:17:51.81#ibcon#read 6, iclass 22, count 0 2006.245.08:17:51.81#ibcon#end of sib2, iclass 22, count 0 2006.245.08:17:51.81#ibcon#*after write, iclass 22, count 0 2006.245.08:17:51.81#ibcon#*before return 0, iclass 22, count 0 2006.245.08:17:51.81#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:51.81#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:51.81#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:17:51.81#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:17:51.81$vc4f8/va=7,7 2006.245.08:17:51.81#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.245.08:17:51.81#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.245.08:17:51.81#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:51.81#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:17:51.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:17:51.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:17:51.87#ibcon#enter wrdev, iclass 24, count 2 2006.245.08:17:51.87#ibcon#first serial, iclass 24, count 2 2006.245.08:17:51.87#ibcon#enter sib2, iclass 24, count 2 2006.245.08:17:51.87#ibcon#flushed, iclass 24, count 2 2006.245.08:17:51.87#ibcon#about to write, iclass 24, count 2 2006.245.08:17:51.87#ibcon#wrote, iclass 24, count 2 2006.245.08:17:51.87#ibcon#about to read 3, iclass 24, count 2 2006.245.08:17:51.89#ibcon#read 3, iclass 24, count 2 2006.245.08:17:51.89#ibcon#about to read 4, iclass 24, count 2 2006.245.08:17:51.89#ibcon#read 4, iclass 24, count 2 2006.245.08:17:51.89#ibcon#about to read 5, iclass 24, count 2 2006.245.08:17:51.89#ibcon#read 5, iclass 24, count 2 2006.245.08:17:51.89#ibcon#about to read 6, iclass 24, count 2 2006.245.08:17:51.89#ibcon#read 6, iclass 24, count 2 2006.245.08:17:51.89#ibcon#end of sib2, iclass 24, count 2 2006.245.08:17:51.89#ibcon#*mode == 0, iclass 24, count 2 2006.245.08:17:51.89#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.245.08:17:51.89#ibcon#[25=AT07-07\r\n] 2006.245.08:17:51.89#ibcon#*before write, iclass 24, count 2 2006.245.08:17:51.89#ibcon#enter sib2, iclass 24, count 2 2006.245.08:17:51.89#ibcon#flushed, iclass 24, count 2 2006.245.08:17:51.89#ibcon#about to write, iclass 24, count 2 2006.245.08:17:51.89#ibcon#wrote, iclass 24, count 2 2006.245.08:17:51.89#ibcon#about to read 3, iclass 24, count 2 2006.245.08:17:51.92#ibcon#read 3, iclass 24, count 2 2006.245.08:17:51.92#ibcon#about to read 4, iclass 24, count 2 2006.245.08:17:51.92#ibcon#read 4, iclass 24, count 2 2006.245.08:17:51.92#ibcon#about to read 5, iclass 24, count 2 2006.245.08:17:51.92#ibcon#read 5, iclass 24, count 2 2006.245.08:17:51.92#ibcon#about to read 6, iclass 24, count 2 2006.245.08:17:51.92#ibcon#read 6, iclass 24, count 2 2006.245.08:17:51.92#ibcon#end of sib2, iclass 24, count 2 2006.245.08:17:51.92#ibcon#*after write, iclass 24, count 2 2006.245.08:17:51.92#ibcon#*before return 0, iclass 24, count 2 2006.245.08:17:51.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:17:51.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.245.08:17:51.92#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.245.08:17:51.92#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:51.92#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:17:52.04#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:17:52.04#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:17:52.04#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:17:52.04#ibcon#first serial, iclass 24, count 0 2006.245.08:17:52.04#ibcon#enter sib2, iclass 24, count 0 2006.245.08:17:52.04#ibcon#flushed, iclass 24, count 0 2006.245.08:17:52.04#ibcon#about to write, iclass 24, count 0 2006.245.08:17:52.04#ibcon#wrote, iclass 24, count 0 2006.245.08:17:52.04#ibcon#about to read 3, iclass 24, count 0 2006.245.08:17:52.06#ibcon#read 3, iclass 24, count 0 2006.245.08:17:52.06#ibcon#about to read 4, iclass 24, count 0 2006.245.08:17:52.06#ibcon#read 4, iclass 24, count 0 2006.245.08:17:52.06#ibcon#about to read 5, iclass 24, count 0 2006.245.08:17:52.06#ibcon#read 5, iclass 24, count 0 2006.245.08:17:52.06#ibcon#about to read 6, iclass 24, count 0 2006.245.08:17:52.06#ibcon#read 6, iclass 24, count 0 2006.245.08:17:52.06#ibcon#end of sib2, iclass 24, count 0 2006.245.08:17:52.06#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:17:52.06#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:17:52.06#ibcon#[25=USB\r\n] 2006.245.08:17:52.06#ibcon#*before write, iclass 24, count 0 2006.245.08:17:52.06#ibcon#enter sib2, iclass 24, count 0 2006.245.08:17:52.06#ibcon#flushed, iclass 24, count 0 2006.245.08:17:52.06#ibcon#about to write, iclass 24, count 0 2006.245.08:17:52.06#ibcon#wrote, iclass 24, count 0 2006.245.08:17:52.06#ibcon#about to read 3, iclass 24, count 0 2006.245.08:17:52.09#ibcon#read 3, iclass 24, count 0 2006.245.08:17:52.09#ibcon#about to read 4, iclass 24, count 0 2006.245.08:17:52.09#ibcon#read 4, iclass 24, count 0 2006.245.08:17:52.09#ibcon#about to read 5, iclass 24, count 0 2006.245.08:17:52.09#ibcon#read 5, iclass 24, count 0 2006.245.08:17:52.09#ibcon#about to read 6, iclass 24, count 0 2006.245.08:17:52.09#ibcon#read 6, iclass 24, count 0 2006.245.08:17:52.09#ibcon#end of sib2, iclass 24, count 0 2006.245.08:17:52.09#ibcon#*after write, iclass 24, count 0 2006.245.08:17:52.09#ibcon#*before return 0, iclass 24, count 0 2006.245.08:17:52.09#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:17:52.09#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.245.08:17:52.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:17:52.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:17:52.09$vc4f8/valo=8,852.99 2006.245.08:17:52.09#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.245.08:17:52.09#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.245.08:17:52.09#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:52.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:17:52.09#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:17:52.09#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:17:52.09#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:17:52.09#ibcon#first serial, iclass 26, count 0 2006.245.08:17:52.09#ibcon#enter sib2, iclass 26, count 0 2006.245.08:17:52.09#ibcon#flushed, iclass 26, count 0 2006.245.08:17:52.09#ibcon#about to write, iclass 26, count 0 2006.245.08:17:52.09#ibcon#wrote, iclass 26, count 0 2006.245.08:17:52.09#ibcon#about to read 3, iclass 26, count 0 2006.245.08:17:52.11#ibcon#read 3, iclass 26, count 0 2006.245.08:17:52.11#ibcon#about to read 4, iclass 26, count 0 2006.245.08:17:52.11#ibcon#read 4, iclass 26, count 0 2006.245.08:17:52.11#ibcon#about to read 5, iclass 26, count 0 2006.245.08:17:52.11#ibcon#read 5, iclass 26, count 0 2006.245.08:17:52.11#ibcon#about to read 6, iclass 26, count 0 2006.245.08:17:52.11#ibcon#read 6, iclass 26, count 0 2006.245.08:17:52.11#ibcon#end of sib2, iclass 26, count 0 2006.245.08:17:52.11#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:17:52.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:17:52.11#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:17:52.11#ibcon#*before write, iclass 26, count 0 2006.245.08:17:52.11#ibcon#enter sib2, iclass 26, count 0 2006.245.08:17:52.11#ibcon#flushed, iclass 26, count 0 2006.245.08:17:52.11#ibcon#about to write, iclass 26, count 0 2006.245.08:17:52.11#ibcon#wrote, iclass 26, count 0 2006.245.08:17:52.11#ibcon#about to read 3, iclass 26, count 0 2006.245.08:17:52.15#ibcon#read 3, iclass 26, count 0 2006.245.08:17:52.15#ibcon#about to read 4, iclass 26, count 0 2006.245.08:17:52.15#ibcon#read 4, iclass 26, count 0 2006.245.08:17:52.15#ibcon#about to read 5, iclass 26, count 0 2006.245.08:17:52.15#ibcon#read 5, iclass 26, count 0 2006.245.08:17:52.15#ibcon#about to read 6, iclass 26, count 0 2006.245.08:17:52.15#ibcon#read 6, iclass 26, count 0 2006.245.08:17:52.15#ibcon#end of sib2, iclass 26, count 0 2006.245.08:17:52.15#ibcon#*after write, iclass 26, count 0 2006.245.08:17:52.15#ibcon#*before return 0, iclass 26, count 0 2006.245.08:17:52.15#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:17:52.15#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.245.08:17:52.15#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:17:52.15#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:17:52.15$vc4f8/va=8,8 2006.245.08:17:52.15#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.245.08:17:52.15#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.245.08:17:52.15#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:52.15#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:17:52.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:17:52.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:17:52.21#ibcon#enter wrdev, iclass 28, count 2 2006.245.08:17:52.21#ibcon#first serial, iclass 28, count 2 2006.245.08:17:52.21#ibcon#enter sib2, iclass 28, count 2 2006.245.08:17:52.21#ibcon#flushed, iclass 28, count 2 2006.245.08:17:52.21#ibcon#about to write, iclass 28, count 2 2006.245.08:17:52.21#ibcon#wrote, iclass 28, count 2 2006.245.08:17:52.21#ibcon#about to read 3, iclass 28, count 2 2006.245.08:17:52.23#ibcon#read 3, iclass 28, count 2 2006.245.08:17:52.23#ibcon#about to read 4, iclass 28, count 2 2006.245.08:17:52.23#ibcon#read 4, iclass 28, count 2 2006.245.08:17:52.23#ibcon#about to read 5, iclass 28, count 2 2006.245.08:17:52.23#ibcon#read 5, iclass 28, count 2 2006.245.08:17:52.23#ibcon#about to read 6, iclass 28, count 2 2006.245.08:17:52.23#ibcon#read 6, iclass 28, count 2 2006.245.08:17:52.23#ibcon#end of sib2, iclass 28, count 2 2006.245.08:17:52.23#ibcon#*mode == 0, iclass 28, count 2 2006.245.08:17:52.23#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.245.08:17:52.23#ibcon#[25=AT08-08\r\n] 2006.245.08:17:52.23#ibcon#*before write, iclass 28, count 2 2006.245.08:17:52.23#ibcon#enter sib2, iclass 28, count 2 2006.245.08:17:52.23#ibcon#flushed, iclass 28, count 2 2006.245.08:17:52.23#ibcon#about to write, iclass 28, count 2 2006.245.08:17:52.23#ibcon#wrote, iclass 28, count 2 2006.245.08:17:52.23#ibcon#about to read 3, iclass 28, count 2 2006.245.08:17:52.26#ibcon#read 3, iclass 28, count 2 2006.245.08:17:52.26#ibcon#about to read 4, iclass 28, count 2 2006.245.08:17:52.26#ibcon#read 4, iclass 28, count 2 2006.245.08:17:52.26#ibcon#about to read 5, iclass 28, count 2 2006.245.08:17:52.26#ibcon#read 5, iclass 28, count 2 2006.245.08:17:52.26#ibcon#about to read 6, iclass 28, count 2 2006.245.08:17:52.26#ibcon#read 6, iclass 28, count 2 2006.245.08:17:52.26#ibcon#end of sib2, iclass 28, count 2 2006.245.08:17:52.26#ibcon#*after write, iclass 28, count 2 2006.245.08:17:52.26#ibcon#*before return 0, iclass 28, count 2 2006.245.08:17:52.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:17:52.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.245.08:17:52.26#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.245.08:17:52.26#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:52.26#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:17:52.38#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:17:52.38#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:17:52.38#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:17:52.38#ibcon#first serial, iclass 28, count 0 2006.245.08:17:52.38#ibcon#enter sib2, iclass 28, count 0 2006.245.08:17:52.38#ibcon#flushed, iclass 28, count 0 2006.245.08:17:52.38#ibcon#about to write, iclass 28, count 0 2006.245.08:17:52.38#ibcon#wrote, iclass 28, count 0 2006.245.08:17:52.38#ibcon#about to read 3, iclass 28, count 0 2006.245.08:17:52.40#ibcon#read 3, iclass 28, count 0 2006.245.08:17:52.40#ibcon#about to read 4, iclass 28, count 0 2006.245.08:17:52.40#ibcon#read 4, iclass 28, count 0 2006.245.08:17:52.40#ibcon#about to read 5, iclass 28, count 0 2006.245.08:17:52.40#ibcon#read 5, iclass 28, count 0 2006.245.08:17:52.40#ibcon#about to read 6, iclass 28, count 0 2006.245.08:17:52.40#ibcon#read 6, iclass 28, count 0 2006.245.08:17:52.40#ibcon#end of sib2, iclass 28, count 0 2006.245.08:17:52.40#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:17:52.40#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:17:52.40#ibcon#[25=USB\r\n] 2006.245.08:17:52.40#ibcon#*before write, iclass 28, count 0 2006.245.08:17:52.40#ibcon#enter sib2, iclass 28, count 0 2006.245.08:17:52.40#ibcon#flushed, iclass 28, count 0 2006.245.08:17:52.40#ibcon#about to write, iclass 28, count 0 2006.245.08:17:52.40#ibcon#wrote, iclass 28, count 0 2006.245.08:17:52.40#ibcon#about to read 3, iclass 28, count 0 2006.245.08:17:52.43#ibcon#read 3, iclass 28, count 0 2006.245.08:17:52.43#ibcon#about to read 4, iclass 28, count 0 2006.245.08:17:52.43#ibcon#read 4, iclass 28, count 0 2006.245.08:17:52.43#ibcon#about to read 5, iclass 28, count 0 2006.245.08:17:52.43#ibcon#read 5, iclass 28, count 0 2006.245.08:17:52.43#ibcon#about to read 6, iclass 28, count 0 2006.245.08:17:52.43#ibcon#read 6, iclass 28, count 0 2006.245.08:17:52.43#ibcon#end of sib2, iclass 28, count 0 2006.245.08:17:52.43#ibcon#*after write, iclass 28, count 0 2006.245.08:17:52.43#ibcon#*before return 0, iclass 28, count 0 2006.245.08:17:52.43#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:17:52.43#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.245.08:17:52.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:17:52.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:17:52.43$vc4f8/vblo=1,632.99 2006.245.08:17:52.43#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.245.08:17:52.43#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.245.08:17:52.43#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:52.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:17:52.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:17:52.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:17:52.43#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:17:52.43#ibcon#first serial, iclass 30, count 0 2006.245.08:17:52.43#ibcon#enter sib2, iclass 30, count 0 2006.245.08:17:52.43#ibcon#flushed, iclass 30, count 0 2006.245.08:17:52.43#ibcon#about to write, iclass 30, count 0 2006.245.08:17:52.43#ibcon#wrote, iclass 30, count 0 2006.245.08:17:52.43#ibcon#about to read 3, iclass 30, count 0 2006.245.08:17:52.45#ibcon#read 3, iclass 30, count 0 2006.245.08:17:52.45#ibcon#about to read 4, iclass 30, count 0 2006.245.08:17:52.45#ibcon#read 4, iclass 30, count 0 2006.245.08:17:52.45#ibcon#about to read 5, iclass 30, count 0 2006.245.08:17:52.45#ibcon#read 5, iclass 30, count 0 2006.245.08:17:52.45#ibcon#about to read 6, iclass 30, count 0 2006.245.08:17:52.45#ibcon#read 6, iclass 30, count 0 2006.245.08:17:52.45#ibcon#end of sib2, iclass 30, count 0 2006.245.08:17:52.45#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:17:52.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:17:52.45#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:17:52.45#ibcon#*before write, iclass 30, count 0 2006.245.08:17:52.45#ibcon#enter sib2, iclass 30, count 0 2006.245.08:17:52.45#ibcon#flushed, iclass 30, count 0 2006.245.08:17:52.45#ibcon#about to write, iclass 30, count 0 2006.245.08:17:52.45#ibcon#wrote, iclass 30, count 0 2006.245.08:17:52.45#ibcon#about to read 3, iclass 30, count 0 2006.245.08:17:52.49#ibcon#read 3, iclass 30, count 0 2006.245.08:17:52.49#ibcon#about to read 4, iclass 30, count 0 2006.245.08:17:52.49#ibcon#read 4, iclass 30, count 0 2006.245.08:17:52.49#ibcon#about to read 5, iclass 30, count 0 2006.245.08:17:52.49#ibcon#read 5, iclass 30, count 0 2006.245.08:17:52.49#ibcon#about to read 6, iclass 30, count 0 2006.245.08:17:52.49#ibcon#read 6, iclass 30, count 0 2006.245.08:17:52.49#ibcon#end of sib2, iclass 30, count 0 2006.245.08:17:52.49#ibcon#*after write, iclass 30, count 0 2006.245.08:17:52.49#ibcon#*before return 0, iclass 30, count 0 2006.245.08:17:52.49#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:17:52.49#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.245.08:17:52.49#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:17:52.49#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:17:52.49$vc4f8/vb=1,4 2006.245.08:17:52.49#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.245.08:17:52.49#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.245.08:17:52.49#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:52.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:17:52.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:17:52.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:17:52.49#ibcon#enter wrdev, iclass 32, count 2 2006.245.08:17:52.49#ibcon#first serial, iclass 32, count 2 2006.245.08:17:52.49#ibcon#enter sib2, iclass 32, count 2 2006.245.08:17:52.49#ibcon#flushed, iclass 32, count 2 2006.245.08:17:52.49#ibcon#about to write, iclass 32, count 2 2006.245.08:17:52.49#ibcon#wrote, iclass 32, count 2 2006.245.08:17:52.49#ibcon#about to read 3, iclass 32, count 2 2006.245.08:17:52.51#ibcon#read 3, iclass 32, count 2 2006.245.08:17:52.51#ibcon#about to read 4, iclass 32, count 2 2006.245.08:17:52.51#ibcon#read 4, iclass 32, count 2 2006.245.08:17:52.51#ibcon#about to read 5, iclass 32, count 2 2006.245.08:17:52.51#ibcon#read 5, iclass 32, count 2 2006.245.08:17:52.51#ibcon#about to read 6, iclass 32, count 2 2006.245.08:17:52.51#ibcon#read 6, iclass 32, count 2 2006.245.08:17:52.51#ibcon#end of sib2, iclass 32, count 2 2006.245.08:17:52.51#ibcon#*mode == 0, iclass 32, count 2 2006.245.08:17:52.51#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.245.08:17:52.51#ibcon#[27=AT01-04\r\n] 2006.245.08:17:52.51#ibcon#*before write, iclass 32, count 2 2006.245.08:17:52.51#ibcon#enter sib2, iclass 32, count 2 2006.245.08:17:52.51#ibcon#flushed, iclass 32, count 2 2006.245.08:17:52.51#ibcon#about to write, iclass 32, count 2 2006.245.08:17:52.51#ibcon#wrote, iclass 32, count 2 2006.245.08:17:52.51#ibcon#about to read 3, iclass 32, count 2 2006.245.08:17:52.54#ibcon#read 3, iclass 32, count 2 2006.245.08:17:52.54#ibcon#about to read 4, iclass 32, count 2 2006.245.08:17:52.54#ibcon#read 4, iclass 32, count 2 2006.245.08:17:52.54#ibcon#about to read 5, iclass 32, count 2 2006.245.08:17:52.54#ibcon#read 5, iclass 32, count 2 2006.245.08:17:52.54#ibcon#about to read 6, iclass 32, count 2 2006.245.08:17:52.54#ibcon#read 6, iclass 32, count 2 2006.245.08:17:52.54#ibcon#end of sib2, iclass 32, count 2 2006.245.08:17:52.54#ibcon#*after write, iclass 32, count 2 2006.245.08:17:52.54#ibcon#*before return 0, iclass 32, count 2 2006.245.08:17:52.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:17:52.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.245.08:17:52.54#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.245.08:17:52.54#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:52.54#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:17:52.66#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:17:52.66#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:17:52.66#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:17:52.66#ibcon#first serial, iclass 32, count 0 2006.245.08:17:52.66#ibcon#enter sib2, iclass 32, count 0 2006.245.08:17:52.66#ibcon#flushed, iclass 32, count 0 2006.245.08:17:52.66#ibcon#about to write, iclass 32, count 0 2006.245.08:17:52.66#ibcon#wrote, iclass 32, count 0 2006.245.08:17:52.66#ibcon#about to read 3, iclass 32, count 0 2006.245.08:17:52.68#ibcon#read 3, iclass 32, count 0 2006.245.08:17:52.68#ibcon#about to read 4, iclass 32, count 0 2006.245.08:17:52.68#ibcon#read 4, iclass 32, count 0 2006.245.08:17:52.68#ibcon#about to read 5, iclass 32, count 0 2006.245.08:17:52.68#ibcon#read 5, iclass 32, count 0 2006.245.08:17:52.68#ibcon#about to read 6, iclass 32, count 0 2006.245.08:17:52.68#ibcon#read 6, iclass 32, count 0 2006.245.08:17:52.68#ibcon#end of sib2, iclass 32, count 0 2006.245.08:17:52.68#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:17:52.68#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:17:52.68#ibcon#[27=USB\r\n] 2006.245.08:17:52.68#ibcon#*before write, iclass 32, count 0 2006.245.08:17:52.68#ibcon#enter sib2, iclass 32, count 0 2006.245.08:17:52.68#ibcon#flushed, iclass 32, count 0 2006.245.08:17:52.68#ibcon#about to write, iclass 32, count 0 2006.245.08:17:52.68#ibcon#wrote, iclass 32, count 0 2006.245.08:17:52.68#ibcon#about to read 3, iclass 32, count 0 2006.245.08:17:52.71#ibcon#read 3, iclass 32, count 0 2006.245.08:17:52.71#ibcon#about to read 4, iclass 32, count 0 2006.245.08:17:52.71#ibcon#read 4, iclass 32, count 0 2006.245.08:17:52.71#ibcon#about to read 5, iclass 32, count 0 2006.245.08:17:52.71#ibcon#read 5, iclass 32, count 0 2006.245.08:17:52.71#ibcon#about to read 6, iclass 32, count 0 2006.245.08:17:52.71#ibcon#read 6, iclass 32, count 0 2006.245.08:17:52.71#ibcon#end of sib2, iclass 32, count 0 2006.245.08:17:52.71#ibcon#*after write, iclass 32, count 0 2006.245.08:17:52.71#ibcon#*before return 0, iclass 32, count 0 2006.245.08:17:52.71#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:17:52.71#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.245.08:17:52.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:17:52.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:17:52.71$vc4f8/vblo=2,640.99 2006.245.08:17:52.71#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.08:17:52.71#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.08:17:52.71#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:52.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:52.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:52.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:52.71#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:17:52.71#ibcon#first serial, iclass 34, count 0 2006.245.08:17:52.71#ibcon#enter sib2, iclass 34, count 0 2006.245.08:17:52.71#ibcon#flushed, iclass 34, count 0 2006.245.08:17:52.71#ibcon#about to write, iclass 34, count 0 2006.245.08:17:52.71#ibcon#wrote, iclass 34, count 0 2006.245.08:17:52.71#ibcon#about to read 3, iclass 34, count 0 2006.245.08:17:52.73#ibcon#read 3, iclass 34, count 0 2006.245.08:17:52.73#ibcon#about to read 4, iclass 34, count 0 2006.245.08:17:52.73#ibcon#read 4, iclass 34, count 0 2006.245.08:17:52.73#ibcon#about to read 5, iclass 34, count 0 2006.245.08:17:52.73#ibcon#read 5, iclass 34, count 0 2006.245.08:17:52.73#ibcon#about to read 6, iclass 34, count 0 2006.245.08:17:52.73#ibcon#read 6, iclass 34, count 0 2006.245.08:17:52.73#ibcon#end of sib2, iclass 34, count 0 2006.245.08:17:52.73#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:17:52.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:17:52.73#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:17:52.73#ibcon#*before write, iclass 34, count 0 2006.245.08:17:52.73#ibcon#enter sib2, iclass 34, count 0 2006.245.08:17:52.73#ibcon#flushed, iclass 34, count 0 2006.245.08:17:52.73#ibcon#about to write, iclass 34, count 0 2006.245.08:17:52.73#ibcon#wrote, iclass 34, count 0 2006.245.08:17:52.73#ibcon#about to read 3, iclass 34, count 0 2006.245.08:17:52.77#ibcon#read 3, iclass 34, count 0 2006.245.08:17:52.77#ibcon#about to read 4, iclass 34, count 0 2006.245.08:17:52.77#ibcon#read 4, iclass 34, count 0 2006.245.08:17:52.77#ibcon#about to read 5, iclass 34, count 0 2006.245.08:17:52.77#ibcon#read 5, iclass 34, count 0 2006.245.08:17:52.77#ibcon#about to read 6, iclass 34, count 0 2006.245.08:17:52.77#ibcon#read 6, iclass 34, count 0 2006.245.08:17:52.77#ibcon#end of sib2, iclass 34, count 0 2006.245.08:17:52.77#ibcon#*after write, iclass 34, count 0 2006.245.08:17:52.77#ibcon#*before return 0, iclass 34, count 0 2006.245.08:17:52.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:52.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:17:52.77#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:17:52.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:17:52.77$vc4f8/vb=2,4 2006.245.08:17:52.77#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.08:17:52.77#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.08:17:52.77#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:52.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:52.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:52.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:52.83#ibcon#enter wrdev, iclass 36, count 2 2006.245.08:17:52.83#ibcon#first serial, iclass 36, count 2 2006.245.08:17:52.83#ibcon#enter sib2, iclass 36, count 2 2006.245.08:17:52.83#ibcon#flushed, iclass 36, count 2 2006.245.08:17:52.83#ibcon#about to write, iclass 36, count 2 2006.245.08:17:52.83#ibcon#wrote, iclass 36, count 2 2006.245.08:17:52.83#ibcon#about to read 3, iclass 36, count 2 2006.245.08:17:52.85#ibcon#read 3, iclass 36, count 2 2006.245.08:17:52.85#ibcon#about to read 4, iclass 36, count 2 2006.245.08:17:52.85#ibcon#read 4, iclass 36, count 2 2006.245.08:17:52.85#ibcon#about to read 5, iclass 36, count 2 2006.245.08:17:52.85#ibcon#read 5, iclass 36, count 2 2006.245.08:17:52.85#ibcon#about to read 6, iclass 36, count 2 2006.245.08:17:52.85#ibcon#read 6, iclass 36, count 2 2006.245.08:17:52.85#ibcon#end of sib2, iclass 36, count 2 2006.245.08:17:52.85#ibcon#*mode == 0, iclass 36, count 2 2006.245.08:17:52.85#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.08:17:52.85#ibcon#[27=AT02-04\r\n] 2006.245.08:17:52.85#ibcon#*before write, iclass 36, count 2 2006.245.08:17:52.85#ibcon#enter sib2, iclass 36, count 2 2006.245.08:17:52.85#ibcon#flushed, iclass 36, count 2 2006.245.08:17:52.85#ibcon#about to write, iclass 36, count 2 2006.245.08:17:52.85#ibcon#wrote, iclass 36, count 2 2006.245.08:17:52.85#ibcon#about to read 3, iclass 36, count 2 2006.245.08:17:52.88#ibcon#read 3, iclass 36, count 2 2006.245.08:17:52.88#ibcon#about to read 4, iclass 36, count 2 2006.245.08:17:52.88#ibcon#read 4, iclass 36, count 2 2006.245.08:17:52.88#ibcon#about to read 5, iclass 36, count 2 2006.245.08:17:52.88#ibcon#read 5, iclass 36, count 2 2006.245.08:17:52.88#ibcon#about to read 6, iclass 36, count 2 2006.245.08:17:52.88#ibcon#read 6, iclass 36, count 2 2006.245.08:17:52.88#ibcon#end of sib2, iclass 36, count 2 2006.245.08:17:52.88#ibcon#*after write, iclass 36, count 2 2006.245.08:17:52.88#ibcon#*before return 0, iclass 36, count 2 2006.245.08:17:52.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:52.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:17:52.88#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.08:17:52.88#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:52.88#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:53.00#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:53.00#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:53.00#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:17:53.00#ibcon#first serial, iclass 36, count 0 2006.245.08:17:53.00#ibcon#enter sib2, iclass 36, count 0 2006.245.08:17:53.00#ibcon#flushed, iclass 36, count 0 2006.245.08:17:53.00#ibcon#about to write, iclass 36, count 0 2006.245.08:17:53.00#ibcon#wrote, iclass 36, count 0 2006.245.08:17:53.00#ibcon#about to read 3, iclass 36, count 0 2006.245.08:17:53.02#ibcon#read 3, iclass 36, count 0 2006.245.08:17:53.02#ibcon#about to read 4, iclass 36, count 0 2006.245.08:17:53.02#ibcon#read 4, iclass 36, count 0 2006.245.08:17:53.02#ibcon#about to read 5, iclass 36, count 0 2006.245.08:17:53.02#ibcon#read 5, iclass 36, count 0 2006.245.08:17:53.02#ibcon#about to read 6, iclass 36, count 0 2006.245.08:17:53.02#ibcon#read 6, iclass 36, count 0 2006.245.08:17:53.02#ibcon#end of sib2, iclass 36, count 0 2006.245.08:17:53.02#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:17:53.02#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:17:53.02#ibcon#[27=USB\r\n] 2006.245.08:17:53.02#ibcon#*before write, iclass 36, count 0 2006.245.08:17:53.02#ibcon#enter sib2, iclass 36, count 0 2006.245.08:17:53.02#ibcon#flushed, iclass 36, count 0 2006.245.08:17:53.02#ibcon#about to write, iclass 36, count 0 2006.245.08:17:53.02#ibcon#wrote, iclass 36, count 0 2006.245.08:17:53.02#ibcon#about to read 3, iclass 36, count 0 2006.245.08:17:53.05#ibcon#read 3, iclass 36, count 0 2006.245.08:17:53.05#ibcon#about to read 4, iclass 36, count 0 2006.245.08:17:53.05#ibcon#read 4, iclass 36, count 0 2006.245.08:17:53.05#ibcon#about to read 5, iclass 36, count 0 2006.245.08:17:53.05#ibcon#read 5, iclass 36, count 0 2006.245.08:17:53.05#ibcon#about to read 6, iclass 36, count 0 2006.245.08:17:53.05#ibcon#read 6, iclass 36, count 0 2006.245.08:17:53.05#ibcon#end of sib2, iclass 36, count 0 2006.245.08:17:53.05#ibcon#*after write, iclass 36, count 0 2006.245.08:17:53.05#ibcon#*before return 0, iclass 36, count 0 2006.245.08:17:53.05#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:53.05#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:17:53.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:17:53.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:17:53.05$vc4f8/vblo=3,656.99 2006.245.08:17:53.05#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.245.08:17:53.05#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.245.08:17:53.05#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:53.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:53.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:53.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:53.05#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:17:53.05#ibcon#first serial, iclass 38, count 0 2006.245.08:17:53.05#ibcon#enter sib2, iclass 38, count 0 2006.245.08:17:53.05#ibcon#flushed, iclass 38, count 0 2006.245.08:17:53.05#ibcon#about to write, iclass 38, count 0 2006.245.08:17:53.05#ibcon#wrote, iclass 38, count 0 2006.245.08:17:53.05#ibcon#about to read 3, iclass 38, count 0 2006.245.08:17:53.07#ibcon#read 3, iclass 38, count 0 2006.245.08:17:53.07#ibcon#about to read 4, iclass 38, count 0 2006.245.08:17:53.07#ibcon#read 4, iclass 38, count 0 2006.245.08:17:53.07#ibcon#about to read 5, iclass 38, count 0 2006.245.08:17:53.07#ibcon#read 5, iclass 38, count 0 2006.245.08:17:53.07#ibcon#about to read 6, iclass 38, count 0 2006.245.08:17:53.07#ibcon#read 6, iclass 38, count 0 2006.245.08:17:53.07#ibcon#end of sib2, iclass 38, count 0 2006.245.08:17:53.07#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:17:53.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:17:53.07#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:17:53.07#ibcon#*before write, iclass 38, count 0 2006.245.08:17:53.07#ibcon#enter sib2, iclass 38, count 0 2006.245.08:17:53.07#ibcon#flushed, iclass 38, count 0 2006.245.08:17:53.07#ibcon#about to write, iclass 38, count 0 2006.245.08:17:53.07#ibcon#wrote, iclass 38, count 0 2006.245.08:17:53.07#ibcon#about to read 3, iclass 38, count 0 2006.245.08:17:53.12#ibcon#read 3, iclass 38, count 0 2006.245.08:17:53.12#ibcon#about to read 4, iclass 38, count 0 2006.245.08:17:53.12#ibcon#read 4, iclass 38, count 0 2006.245.08:17:53.12#ibcon#about to read 5, iclass 38, count 0 2006.245.08:17:53.12#ibcon#read 5, iclass 38, count 0 2006.245.08:17:53.12#ibcon#about to read 6, iclass 38, count 0 2006.245.08:17:53.12#ibcon#read 6, iclass 38, count 0 2006.245.08:17:53.12#ibcon#end of sib2, iclass 38, count 0 2006.245.08:17:53.12#ibcon#*after write, iclass 38, count 0 2006.245.08:17:53.12#ibcon#*before return 0, iclass 38, count 0 2006.245.08:17:53.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:53.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.245.08:17:53.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:17:53.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:17:53.12$vc4f8/vb=3,4 2006.245.08:17:53.12#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.245.08:17:53.12#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.245.08:17:53.12#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:53.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:53.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:53.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:53.17#ibcon#enter wrdev, iclass 40, count 2 2006.245.08:17:53.17#ibcon#first serial, iclass 40, count 2 2006.245.08:17:53.17#ibcon#enter sib2, iclass 40, count 2 2006.245.08:17:53.17#ibcon#flushed, iclass 40, count 2 2006.245.08:17:53.17#ibcon#about to write, iclass 40, count 2 2006.245.08:17:53.17#ibcon#wrote, iclass 40, count 2 2006.245.08:17:53.17#ibcon#about to read 3, iclass 40, count 2 2006.245.08:17:53.19#ibcon#read 3, iclass 40, count 2 2006.245.08:17:53.19#ibcon#about to read 4, iclass 40, count 2 2006.245.08:17:53.19#ibcon#read 4, iclass 40, count 2 2006.245.08:17:53.19#ibcon#about to read 5, iclass 40, count 2 2006.245.08:17:53.19#ibcon#read 5, iclass 40, count 2 2006.245.08:17:53.19#ibcon#about to read 6, iclass 40, count 2 2006.245.08:17:53.19#ibcon#read 6, iclass 40, count 2 2006.245.08:17:53.19#ibcon#end of sib2, iclass 40, count 2 2006.245.08:17:53.19#ibcon#*mode == 0, iclass 40, count 2 2006.245.08:17:53.19#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.245.08:17:53.19#ibcon#[27=AT03-04\r\n] 2006.245.08:17:53.19#ibcon#*before write, iclass 40, count 2 2006.245.08:17:53.19#ibcon#enter sib2, iclass 40, count 2 2006.245.08:17:53.19#ibcon#flushed, iclass 40, count 2 2006.245.08:17:53.19#ibcon#about to write, iclass 40, count 2 2006.245.08:17:53.19#ibcon#wrote, iclass 40, count 2 2006.245.08:17:53.19#ibcon#about to read 3, iclass 40, count 2 2006.245.08:17:53.22#ibcon#read 3, iclass 40, count 2 2006.245.08:17:53.22#ibcon#about to read 4, iclass 40, count 2 2006.245.08:17:53.22#ibcon#read 4, iclass 40, count 2 2006.245.08:17:53.22#ibcon#about to read 5, iclass 40, count 2 2006.245.08:17:53.22#ibcon#read 5, iclass 40, count 2 2006.245.08:17:53.22#ibcon#about to read 6, iclass 40, count 2 2006.245.08:17:53.22#ibcon#read 6, iclass 40, count 2 2006.245.08:17:53.22#ibcon#end of sib2, iclass 40, count 2 2006.245.08:17:53.22#ibcon#*after write, iclass 40, count 2 2006.245.08:17:53.22#ibcon#*before return 0, iclass 40, count 2 2006.245.08:17:53.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:53.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.245.08:17:53.22#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.245.08:17:53.22#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:53.22#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:53.34#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:53.34#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:53.34#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:17:53.34#ibcon#first serial, iclass 40, count 0 2006.245.08:17:53.34#ibcon#enter sib2, iclass 40, count 0 2006.245.08:17:53.34#ibcon#flushed, iclass 40, count 0 2006.245.08:17:53.34#ibcon#about to write, iclass 40, count 0 2006.245.08:17:53.34#ibcon#wrote, iclass 40, count 0 2006.245.08:17:53.34#ibcon#about to read 3, iclass 40, count 0 2006.245.08:17:53.36#ibcon#read 3, iclass 40, count 0 2006.245.08:17:53.36#ibcon#about to read 4, iclass 40, count 0 2006.245.08:17:53.36#ibcon#read 4, iclass 40, count 0 2006.245.08:17:53.36#ibcon#about to read 5, iclass 40, count 0 2006.245.08:17:53.36#ibcon#read 5, iclass 40, count 0 2006.245.08:17:53.36#ibcon#about to read 6, iclass 40, count 0 2006.245.08:17:53.36#ibcon#read 6, iclass 40, count 0 2006.245.08:17:53.36#ibcon#end of sib2, iclass 40, count 0 2006.245.08:17:53.36#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:17:53.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:17:53.36#ibcon#[27=USB\r\n] 2006.245.08:17:53.36#ibcon#*before write, iclass 40, count 0 2006.245.08:17:53.36#ibcon#enter sib2, iclass 40, count 0 2006.245.08:17:53.36#ibcon#flushed, iclass 40, count 0 2006.245.08:17:53.36#ibcon#about to write, iclass 40, count 0 2006.245.08:17:53.36#ibcon#wrote, iclass 40, count 0 2006.245.08:17:53.36#ibcon#about to read 3, iclass 40, count 0 2006.245.08:17:53.39#ibcon#read 3, iclass 40, count 0 2006.245.08:17:53.39#ibcon#about to read 4, iclass 40, count 0 2006.245.08:17:53.39#ibcon#read 4, iclass 40, count 0 2006.245.08:17:53.39#ibcon#about to read 5, iclass 40, count 0 2006.245.08:17:53.39#ibcon#read 5, iclass 40, count 0 2006.245.08:17:53.39#ibcon#about to read 6, iclass 40, count 0 2006.245.08:17:53.39#ibcon#read 6, iclass 40, count 0 2006.245.08:17:53.39#ibcon#end of sib2, iclass 40, count 0 2006.245.08:17:53.39#ibcon#*after write, iclass 40, count 0 2006.245.08:17:53.39#ibcon#*before return 0, iclass 40, count 0 2006.245.08:17:53.39#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:53.39#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.245.08:17:53.39#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:17:53.39#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:17:53.39$vc4f8/vblo=4,712.99 2006.245.08:17:53.39#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.245.08:17:53.39#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.245.08:17:53.39#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:53.39#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:53.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:53.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:53.39#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:17:53.39#ibcon#first serial, iclass 4, count 0 2006.245.08:17:53.39#ibcon#enter sib2, iclass 4, count 0 2006.245.08:17:53.39#ibcon#flushed, iclass 4, count 0 2006.245.08:17:53.39#ibcon#about to write, iclass 4, count 0 2006.245.08:17:53.39#ibcon#wrote, iclass 4, count 0 2006.245.08:17:53.39#ibcon#about to read 3, iclass 4, count 0 2006.245.08:17:53.41#ibcon#read 3, iclass 4, count 0 2006.245.08:17:53.41#ibcon#about to read 4, iclass 4, count 0 2006.245.08:17:53.41#ibcon#read 4, iclass 4, count 0 2006.245.08:17:53.41#ibcon#about to read 5, iclass 4, count 0 2006.245.08:17:53.41#ibcon#read 5, iclass 4, count 0 2006.245.08:17:53.41#ibcon#about to read 6, iclass 4, count 0 2006.245.08:17:53.41#ibcon#read 6, iclass 4, count 0 2006.245.08:17:53.41#ibcon#end of sib2, iclass 4, count 0 2006.245.08:17:53.41#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:17:53.41#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:17:53.41#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:17:53.41#ibcon#*before write, iclass 4, count 0 2006.245.08:17:53.41#ibcon#enter sib2, iclass 4, count 0 2006.245.08:17:53.41#ibcon#flushed, iclass 4, count 0 2006.245.08:17:53.41#ibcon#about to write, iclass 4, count 0 2006.245.08:17:53.41#ibcon#wrote, iclass 4, count 0 2006.245.08:17:53.41#ibcon#about to read 3, iclass 4, count 0 2006.245.08:17:53.45#ibcon#read 3, iclass 4, count 0 2006.245.08:17:53.45#ibcon#about to read 4, iclass 4, count 0 2006.245.08:17:53.45#ibcon#read 4, iclass 4, count 0 2006.245.08:17:53.45#ibcon#about to read 5, iclass 4, count 0 2006.245.08:17:53.45#ibcon#read 5, iclass 4, count 0 2006.245.08:17:53.45#ibcon#about to read 6, iclass 4, count 0 2006.245.08:17:53.45#ibcon#read 6, iclass 4, count 0 2006.245.08:17:53.45#ibcon#end of sib2, iclass 4, count 0 2006.245.08:17:53.45#ibcon#*after write, iclass 4, count 0 2006.245.08:17:53.45#ibcon#*before return 0, iclass 4, count 0 2006.245.08:17:53.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:53.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.245.08:17:53.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:17:53.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:17:53.45$vc4f8/vb=4,4 2006.245.08:17:53.45#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.245.08:17:53.45#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.245.08:17:53.45#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:53.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:53.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:53.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:53.51#ibcon#enter wrdev, iclass 6, count 2 2006.245.08:17:53.51#ibcon#first serial, iclass 6, count 2 2006.245.08:17:53.51#ibcon#enter sib2, iclass 6, count 2 2006.245.08:17:53.51#ibcon#flushed, iclass 6, count 2 2006.245.08:17:53.51#ibcon#about to write, iclass 6, count 2 2006.245.08:17:53.51#ibcon#wrote, iclass 6, count 2 2006.245.08:17:53.51#ibcon#about to read 3, iclass 6, count 2 2006.245.08:17:53.53#ibcon#read 3, iclass 6, count 2 2006.245.08:17:53.53#ibcon#about to read 4, iclass 6, count 2 2006.245.08:17:53.53#ibcon#read 4, iclass 6, count 2 2006.245.08:17:53.53#ibcon#about to read 5, iclass 6, count 2 2006.245.08:17:53.53#ibcon#read 5, iclass 6, count 2 2006.245.08:17:53.53#ibcon#about to read 6, iclass 6, count 2 2006.245.08:17:53.53#ibcon#read 6, iclass 6, count 2 2006.245.08:17:53.53#ibcon#end of sib2, iclass 6, count 2 2006.245.08:17:53.53#ibcon#*mode == 0, iclass 6, count 2 2006.245.08:17:53.53#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.245.08:17:53.53#ibcon#[27=AT04-04\r\n] 2006.245.08:17:53.53#ibcon#*before write, iclass 6, count 2 2006.245.08:17:53.53#ibcon#enter sib2, iclass 6, count 2 2006.245.08:17:53.53#ibcon#flushed, iclass 6, count 2 2006.245.08:17:53.53#ibcon#about to write, iclass 6, count 2 2006.245.08:17:53.53#ibcon#wrote, iclass 6, count 2 2006.245.08:17:53.53#ibcon#about to read 3, iclass 6, count 2 2006.245.08:17:53.56#ibcon#read 3, iclass 6, count 2 2006.245.08:17:53.56#ibcon#about to read 4, iclass 6, count 2 2006.245.08:17:53.56#ibcon#read 4, iclass 6, count 2 2006.245.08:17:53.56#ibcon#about to read 5, iclass 6, count 2 2006.245.08:17:53.56#ibcon#read 5, iclass 6, count 2 2006.245.08:17:53.56#ibcon#about to read 6, iclass 6, count 2 2006.245.08:17:53.56#ibcon#read 6, iclass 6, count 2 2006.245.08:17:53.56#ibcon#end of sib2, iclass 6, count 2 2006.245.08:17:53.56#ibcon#*after write, iclass 6, count 2 2006.245.08:17:53.56#ibcon#*before return 0, iclass 6, count 2 2006.245.08:17:53.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:53.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.245.08:17:53.56#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.245.08:17:53.56#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:53.56#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:53.68#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:53.68#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:53.68#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:17:53.68#ibcon#first serial, iclass 6, count 0 2006.245.08:17:53.68#ibcon#enter sib2, iclass 6, count 0 2006.245.08:17:53.68#ibcon#flushed, iclass 6, count 0 2006.245.08:17:53.68#ibcon#about to write, iclass 6, count 0 2006.245.08:17:53.68#ibcon#wrote, iclass 6, count 0 2006.245.08:17:53.68#ibcon#about to read 3, iclass 6, count 0 2006.245.08:17:53.70#ibcon#read 3, iclass 6, count 0 2006.245.08:17:53.70#ibcon#about to read 4, iclass 6, count 0 2006.245.08:17:53.70#ibcon#read 4, iclass 6, count 0 2006.245.08:17:53.70#ibcon#about to read 5, iclass 6, count 0 2006.245.08:17:53.70#ibcon#read 5, iclass 6, count 0 2006.245.08:17:53.70#ibcon#about to read 6, iclass 6, count 0 2006.245.08:17:53.70#ibcon#read 6, iclass 6, count 0 2006.245.08:17:53.70#ibcon#end of sib2, iclass 6, count 0 2006.245.08:17:53.70#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:17:53.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:17:53.70#ibcon#[27=USB\r\n] 2006.245.08:17:53.70#ibcon#*before write, iclass 6, count 0 2006.245.08:17:53.70#ibcon#enter sib2, iclass 6, count 0 2006.245.08:17:53.70#ibcon#flushed, iclass 6, count 0 2006.245.08:17:53.70#ibcon#about to write, iclass 6, count 0 2006.245.08:17:53.70#ibcon#wrote, iclass 6, count 0 2006.245.08:17:53.70#ibcon#about to read 3, iclass 6, count 0 2006.245.08:17:53.73#ibcon#read 3, iclass 6, count 0 2006.245.08:17:53.73#ibcon#about to read 4, iclass 6, count 0 2006.245.08:17:53.73#ibcon#read 4, iclass 6, count 0 2006.245.08:17:53.73#ibcon#about to read 5, iclass 6, count 0 2006.245.08:17:53.73#ibcon#read 5, iclass 6, count 0 2006.245.08:17:53.73#ibcon#about to read 6, iclass 6, count 0 2006.245.08:17:53.73#ibcon#read 6, iclass 6, count 0 2006.245.08:17:53.73#ibcon#end of sib2, iclass 6, count 0 2006.245.08:17:53.73#ibcon#*after write, iclass 6, count 0 2006.245.08:17:53.73#ibcon#*before return 0, iclass 6, count 0 2006.245.08:17:53.73#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:53.73#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.245.08:17:53.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:17:53.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:17:53.73$vc4f8/vblo=5,744.99 2006.245.08:17:53.73#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.245.08:17:53.73#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.245.08:17:53.73#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:53.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:53.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:53.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:53.73#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:17:53.73#ibcon#first serial, iclass 10, count 0 2006.245.08:17:53.73#ibcon#enter sib2, iclass 10, count 0 2006.245.08:17:53.73#ibcon#flushed, iclass 10, count 0 2006.245.08:17:53.73#ibcon#about to write, iclass 10, count 0 2006.245.08:17:53.73#ibcon#wrote, iclass 10, count 0 2006.245.08:17:53.73#ibcon#about to read 3, iclass 10, count 0 2006.245.08:17:53.75#ibcon#read 3, iclass 10, count 0 2006.245.08:17:53.75#ibcon#about to read 4, iclass 10, count 0 2006.245.08:17:53.75#ibcon#read 4, iclass 10, count 0 2006.245.08:17:53.75#ibcon#about to read 5, iclass 10, count 0 2006.245.08:17:53.75#ibcon#read 5, iclass 10, count 0 2006.245.08:17:53.75#ibcon#about to read 6, iclass 10, count 0 2006.245.08:17:53.75#ibcon#read 6, iclass 10, count 0 2006.245.08:17:53.75#ibcon#end of sib2, iclass 10, count 0 2006.245.08:17:53.75#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:17:53.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:17:53.75#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:17:53.75#ibcon#*before write, iclass 10, count 0 2006.245.08:17:53.75#ibcon#enter sib2, iclass 10, count 0 2006.245.08:17:53.75#ibcon#flushed, iclass 10, count 0 2006.245.08:17:53.75#ibcon#about to write, iclass 10, count 0 2006.245.08:17:53.75#ibcon#wrote, iclass 10, count 0 2006.245.08:17:53.75#ibcon#about to read 3, iclass 10, count 0 2006.245.08:17:53.79#ibcon#read 3, iclass 10, count 0 2006.245.08:17:53.79#ibcon#about to read 4, iclass 10, count 0 2006.245.08:17:53.79#ibcon#read 4, iclass 10, count 0 2006.245.08:17:53.79#ibcon#about to read 5, iclass 10, count 0 2006.245.08:17:53.79#ibcon#read 5, iclass 10, count 0 2006.245.08:17:53.79#ibcon#about to read 6, iclass 10, count 0 2006.245.08:17:53.79#ibcon#read 6, iclass 10, count 0 2006.245.08:17:53.79#ibcon#end of sib2, iclass 10, count 0 2006.245.08:17:53.79#ibcon#*after write, iclass 10, count 0 2006.245.08:17:53.79#ibcon#*before return 0, iclass 10, count 0 2006.245.08:17:53.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:53.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.245.08:17:53.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:17:53.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:17:53.79$vc4f8/vb=5,3 2006.245.08:17:53.79#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.245.08:17:53.79#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.245.08:17:53.79#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:53.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:53.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:53.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:53.85#ibcon#enter wrdev, iclass 12, count 2 2006.245.08:17:53.85#ibcon#first serial, iclass 12, count 2 2006.245.08:17:53.85#ibcon#enter sib2, iclass 12, count 2 2006.245.08:17:53.85#ibcon#flushed, iclass 12, count 2 2006.245.08:17:53.85#ibcon#about to write, iclass 12, count 2 2006.245.08:17:53.85#ibcon#wrote, iclass 12, count 2 2006.245.08:17:53.85#ibcon#about to read 3, iclass 12, count 2 2006.245.08:17:53.87#ibcon#read 3, iclass 12, count 2 2006.245.08:17:53.87#ibcon#about to read 4, iclass 12, count 2 2006.245.08:17:53.87#ibcon#read 4, iclass 12, count 2 2006.245.08:17:53.87#ibcon#about to read 5, iclass 12, count 2 2006.245.08:17:53.87#ibcon#read 5, iclass 12, count 2 2006.245.08:17:53.87#ibcon#about to read 6, iclass 12, count 2 2006.245.08:17:53.87#ibcon#read 6, iclass 12, count 2 2006.245.08:17:53.87#ibcon#end of sib2, iclass 12, count 2 2006.245.08:17:53.87#ibcon#*mode == 0, iclass 12, count 2 2006.245.08:17:53.87#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.245.08:17:53.87#ibcon#[27=AT05-03\r\n] 2006.245.08:17:53.87#ibcon#*before write, iclass 12, count 2 2006.245.08:17:53.87#ibcon#enter sib2, iclass 12, count 2 2006.245.08:17:53.87#ibcon#flushed, iclass 12, count 2 2006.245.08:17:53.87#ibcon#about to write, iclass 12, count 2 2006.245.08:17:53.87#ibcon#wrote, iclass 12, count 2 2006.245.08:17:53.87#ibcon#about to read 3, iclass 12, count 2 2006.245.08:17:53.90#ibcon#read 3, iclass 12, count 2 2006.245.08:17:53.90#ibcon#about to read 4, iclass 12, count 2 2006.245.08:17:53.90#ibcon#read 4, iclass 12, count 2 2006.245.08:17:53.90#ibcon#about to read 5, iclass 12, count 2 2006.245.08:17:53.90#ibcon#read 5, iclass 12, count 2 2006.245.08:17:53.90#ibcon#about to read 6, iclass 12, count 2 2006.245.08:17:53.90#ibcon#read 6, iclass 12, count 2 2006.245.08:17:53.90#ibcon#end of sib2, iclass 12, count 2 2006.245.08:17:53.90#ibcon#*after write, iclass 12, count 2 2006.245.08:17:53.90#ibcon#*before return 0, iclass 12, count 2 2006.245.08:17:53.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:53.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.245.08:17:53.90#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.245.08:17:53.90#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:53.90#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:54.02#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:54.02#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:54.02#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:17:54.02#ibcon#first serial, iclass 12, count 0 2006.245.08:17:54.02#ibcon#enter sib2, iclass 12, count 0 2006.245.08:17:54.02#ibcon#flushed, iclass 12, count 0 2006.245.08:17:54.02#ibcon#about to write, iclass 12, count 0 2006.245.08:17:54.02#ibcon#wrote, iclass 12, count 0 2006.245.08:17:54.02#ibcon#about to read 3, iclass 12, count 0 2006.245.08:17:54.04#ibcon#read 3, iclass 12, count 0 2006.245.08:17:54.04#ibcon#about to read 4, iclass 12, count 0 2006.245.08:17:54.04#ibcon#read 4, iclass 12, count 0 2006.245.08:17:54.04#ibcon#about to read 5, iclass 12, count 0 2006.245.08:17:54.04#ibcon#read 5, iclass 12, count 0 2006.245.08:17:54.04#ibcon#about to read 6, iclass 12, count 0 2006.245.08:17:54.04#ibcon#read 6, iclass 12, count 0 2006.245.08:17:54.04#ibcon#end of sib2, iclass 12, count 0 2006.245.08:17:54.04#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:17:54.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:17:54.04#ibcon#[27=USB\r\n] 2006.245.08:17:54.04#ibcon#*before write, iclass 12, count 0 2006.245.08:17:54.04#ibcon#enter sib2, iclass 12, count 0 2006.245.08:17:54.04#ibcon#flushed, iclass 12, count 0 2006.245.08:17:54.04#ibcon#about to write, iclass 12, count 0 2006.245.08:17:54.04#ibcon#wrote, iclass 12, count 0 2006.245.08:17:54.04#ibcon#about to read 3, iclass 12, count 0 2006.245.08:17:54.07#ibcon#read 3, iclass 12, count 0 2006.245.08:17:54.07#ibcon#about to read 4, iclass 12, count 0 2006.245.08:17:54.07#ibcon#read 4, iclass 12, count 0 2006.245.08:17:54.07#ibcon#about to read 5, iclass 12, count 0 2006.245.08:17:54.07#ibcon#read 5, iclass 12, count 0 2006.245.08:17:54.07#ibcon#about to read 6, iclass 12, count 0 2006.245.08:17:54.07#ibcon#read 6, iclass 12, count 0 2006.245.08:17:54.07#ibcon#end of sib2, iclass 12, count 0 2006.245.08:17:54.07#ibcon#*after write, iclass 12, count 0 2006.245.08:17:54.07#ibcon#*before return 0, iclass 12, count 0 2006.245.08:17:54.07#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:54.07#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.245.08:17:54.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:17:54.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:17:54.07$vc4f8/vblo=6,752.99 2006.245.08:17:54.07#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.245.08:17:54.07#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.245.08:17:54.07#ibcon#ireg 17 cls_cnt 0 2006.245.08:17:54.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:54.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:54.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:54.07#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:17:54.07#ibcon#first serial, iclass 14, count 0 2006.245.08:17:54.07#ibcon#enter sib2, iclass 14, count 0 2006.245.08:17:54.07#ibcon#flushed, iclass 14, count 0 2006.245.08:17:54.07#ibcon#about to write, iclass 14, count 0 2006.245.08:17:54.07#ibcon#wrote, iclass 14, count 0 2006.245.08:17:54.07#ibcon#about to read 3, iclass 14, count 0 2006.245.08:17:54.09#ibcon#read 3, iclass 14, count 0 2006.245.08:17:54.09#ibcon#about to read 4, iclass 14, count 0 2006.245.08:17:54.09#ibcon#read 4, iclass 14, count 0 2006.245.08:17:54.09#ibcon#about to read 5, iclass 14, count 0 2006.245.08:17:54.09#ibcon#read 5, iclass 14, count 0 2006.245.08:17:54.09#ibcon#about to read 6, iclass 14, count 0 2006.245.08:17:54.09#ibcon#read 6, iclass 14, count 0 2006.245.08:17:54.09#ibcon#end of sib2, iclass 14, count 0 2006.245.08:17:54.09#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:17:54.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:17:54.09#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:17:54.09#ibcon#*before write, iclass 14, count 0 2006.245.08:17:54.09#ibcon#enter sib2, iclass 14, count 0 2006.245.08:17:54.09#ibcon#flushed, iclass 14, count 0 2006.245.08:17:54.09#ibcon#about to write, iclass 14, count 0 2006.245.08:17:54.09#ibcon#wrote, iclass 14, count 0 2006.245.08:17:54.09#ibcon#about to read 3, iclass 14, count 0 2006.245.08:17:54.13#ibcon#read 3, iclass 14, count 0 2006.245.08:17:54.13#ibcon#about to read 4, iclass 14, count 0 2006.245.08:17:54.13#ibcon#read 4, iclass 14, count 0 2006.245.08:17:54.13#ibcon#about to read 5, iclass 14, count 0 2006.245.08:17:54.13#ibcon#read 5, iclass 14, count 0 2006.245.08:17:54.13#ibcon#about to read 6, iclass 14, count 0 2006.245.08:17:54.13#ibcon#read 6, iclass 14, count 0 2006.245.08:17:54.13#ibcon#end of sib2, iclass 14, count 0 2006.245.08:17:54.13#ibcon#*after write, iclass 14, count 0 2006.245.08:17:54.13#ibcon#*before return 0, iclass 14, count 0 2006.245.08:17:54.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:54.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.245.08:17:54.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:17:54.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:17:54.13$vc4f8/vb=6,3 2006.245.08:17:54.13#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.245.08:17:54.13#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.245.08:17:54.13#ibcon#ireg 11 cls_cnt 2 2006.245.08:17:54.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:54.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:54.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:54.19#ibcon#enter wrdev, iclass 16, count 2 2006.245.08:17:54.19#ibcon#first serial, iclass 16, count 2 2006.245.08:17:54.19#ibcon#enter sib2, iclass 16, count 2 2006.245.08:17:54.19#ibcon#flushed, iclass 16, count 2 2006.245.08:17:54.19#ibcon#about to write, iclass 16, count 2 2006.245.08:17:54.19#ibcon#wrote, iclass 16, count 2 2006.245.08:17:54.19#ibcon#about to read 3, iclass 16, count 2 2006.245.08:17:54.21#ibcon#read 3, iclass 16, count 2 2006.245.08:17:54.21#ibcon#about to read 4, iclass 16, count 2 2006.245.08:17:54.21#ibcon#read 4, iclass 16, count 2 2006.245.08:17:54.21#ibcon#about to read 5, iclass 16, count 2 2006.245.08:17:54.21#ibcon#read 5, iclass 16, count 2 2006.245.08:17:54.21#ibcon#about to read 6, iclass 16, count 2 2006.245.08:17:54.21#ibcon#read 6, iclass 16, count 2 2006.245.08:17:54.21#ibcon#end of sib2, iclass 16, count 2 2006.245.08:17:54.21#ibcon#*mode == 0, iclass 16, count 2 2006.245.08:17:54.21#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.245.08:17:54.21#ibcon#[27=AT06-03\r\n] 2006.245.08:17:54.21#ibcon#*before write, iclass 16, count 2 2006.245.08:17:54.21#ibcon#enter sib2, iclass 16, count 2 2006.245.08:17:54.21#ibcon#flushed, iclass 16, count 2 2006.245.08:17:54.21#ibcon#about to write, iclass 16, count 2 2006.245.08:17:54.21#ibcon#wrote, iclass 16, count 2 2006.245.08:17:54.21#ibcon#about to read 3, iclass 16, count 2 2006.245.08:17:54.24#ibcon#read 3, iclass 16, count 2 2006.245.08:17:54.24#ibcon#about to read 4, iclass 16, count 2 2006.245.08:17:54.24#ibcon#read 4, iclass 16, count 2 2006.245.08:17:54.24#ibcon#about to read 5, iclass 16, count 2 2006.245.08:17:54.24#ibcon#read 5, iclass 16, count 2 2006.245.08:17:54.24#ibcon#about to read 6, iclass 16, count 2 2006.245.08:17:54.24#ibcon#read 6, iclass 16, count 2 2006.245.08:17:54.24#ibcon#end of sib2, iclass 16, count 2 2006.245.08:17:54.24#ibcon#*after write, iclass 16, count 2 2006.245.08:17:54.24#ibcon#*before return 0, iclass 16, count 2 2006.245.08:17:54.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:54.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.245.08:17:54.24#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.245.08:17:54.24#ibcon#ireg 7 cls_cnt 0 2006.245.08:17:54.24#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:54.30#abcon#<5=/05 3.3 5.2 26.79 751004.5\r\n> 2006.245.08:17:54.32#abcon#{5=INTERFACE CLEAR} 2006.245.08:17:54.36#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:54.36#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:54.36#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:17:54.36#ibcon#first serial, iclass 16, count 0 2006.245.08:17:54.36#ibcon#enter sib2, iclass 16, count 0 2006.245.08:17:54.36#ibcon#flushed, iclass 16, count 0 2006.245.08:17:54.36#ibcon#about to write, iclass 16, count 0 2006.245.08:17:54.36#ibcon#wrote, iclass 16, count 0 2006.245.08:17:54.36#ibcon#about to read 3, iclass 16, count 0 2006.245.08:17:54.38#ibcon#read 3, iclass 16, count 0 2006.245.08:17:54.38#ibcon#about to read 4, iclass 16, count 0 2006.245.08:17:54.38#ibcon#read 4, iclass 16, count 0 2006.245.08:17:54.38#ibcon#about to read 5, iclass 16, count 0 2006.245.08:17:54.38#ibcon#read 5, iclass 16, count 0 2006.245.08:17:54.38#ibcon#about to read 6, iclass 16, count 0 2006.245.08:17:54.38#ibcon#read 6, iclass 16, count 0 2006.245.08:17:54.38#ibcon#end of sib2, iclass 16, count 0 2006.245.08:17:54.38#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:17:54.38#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:17:54.38#ibcon#[27=USB\r\n] 2006.245.08:17:54.38#ibcon#*before write, iclass 16, count 0 2006.245.08:17:54.38#ibcon#enter sib2, iclass 16, count 0 2006.245.08:17:54.38#ibcon#flushed, iclass 16, count 0 2006.245.08:17:54.38#ibcon#about to write, iclass 16, count 0 2006.245.08:17:54.38#ibcon#wrote, iclass 16, count 0 2006.245.08:17:54.38#ibcon#about to read 3, iclass 16, count 0 2006.245.08:17:54.38#abcon#[5=S1D000X0/0*\r\n] 2006.245.08:17:54.41#ibcon#read 3, iclass 16, count 0 2006.245.08:17:54.41#ibcon#about to read 4, iclass 16, count 0 2006.245.08:17:54.41#ibcon#read 4, iclass 16, count 0 2006.245.08:17:54.41#ibcon#about to read 5, iclass 16, count 0 2006.245.08:17:54.41#ibcon#read 5, iclass 16, count 0 2006.245.08:17:54.41#ibcon#about to read 6, iclass 16, count 0 2006.245.08:17:54.41#ibcon#read 6, iclass 16, count 0 2006.245.08:17:54.41#ibcon#end of sib2, iclass 16, count 0 2006.245.08:17:54.41#ibcon#*after write, iclass 16, count 0 2006.245.08:17:54.41#ibcon#*before return 0, iclass 16, count 0 2006.245.08:17:54.41#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:54.41#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.245.08:17:54.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:17:54.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:17:54.41$vc4f8/vabw=wide 2006.245.08:17:54.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.245.08:17:54.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.245.08:17:54.41#ibcon#ireg 8 cls_cnt 0 2006.245.08:17:54.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:54.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:54.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:54.41#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:17:54.41#ibcon#first serial, iclass 22, count 0 2006.245.08:17:54.41#ibcon#enter sib2, iclass 22, count 0 2006.245.08:17:54.41#ibcon#flushed, iclass 22, count 0 2006.245.08:17:54.41#ibcon#about to write, iclass 22, count 0 2006.245.08:17:54.41#ibcon#wrote, iclass 22, count 0 2006.245.08:17:54.41#ibcon#about to read 3, iclass 22, count 0 2006.245.08:17:54.43#ibcon#read 3, iclass 22, count 0 2006.245.08:17:54.43#ibcon#about to read 4, iclass 22, count 0 2006.245.08:17:54.43#ibcon#read 4, iclass 22, count 0 2006.245.08:17:54.43#ibcon#about to read 5, iclass 22, count 0 2006.245.08:17:54.43#ibcon#read 5, iclass 22, count 0 2006.245.08:17:54.43#ibcon#about to read 6, iclass 22, count 0 2006.245.08:17:54.43#ibcon#read 6, iclass 22, count 0 2006.245.08:17:54.43#ibcon#end of sib2, iclass 22, count 0 2006.245.08:17:54.43#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:17:54.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:17:54.43#ibcon#[25=BW32\r\n] 2006.245.08:17:54.43#ibcon#*before write, iclass 22, count 0 2006.245.08:17:54.43#ibcon#enter sib2, iclass 22, count 0 2006.245.08:17:54.43#ibcon#flushed, iclass 22, count 0 2006.245.08:17:54.43#ibcon#about to write, iclass 22, count 0 2006.245.08:17:54.43#ibcon#wrote, iclass 22, count 0 2006.245.08:17:54.43#ibcon#about to read 3, iclass 22, count 0 2006.245.08:17:54.46#ibcon#read 3, iclass 22, count 0 2006.245.08:17:54.46#ibcon#about to read 4, iclass 22, count 0 2006.245.08:17:54.46#ibcon#read 4, iclass 22, count 0 2006.245.08:17:54.46#ibcon#about to read 5, iclass 22, count 0 2006.245.08:17:54.46#ibcon#read 5, iclass 22, count 0 2006.245.08:17:54.46#ibcon#about to read 6, iclass 22, count 0 2006.245.08:17:54.46#ibcon#read 6, iclass 22, count 0 2006.245.08:17:54.46#ibcon#end of sib2, iclass 22, count 0 2006.245.08:17:54.46#ibcon#*after write, iclass 22, count 0 2006.245.08:17:54.46#ibcon#*before return 0, iclass 22, count 0 2006.245.08:17:54.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:54.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.245.08:17:54.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:17:54.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:17:54.46$vc4f8/vbbw=wide 2006.245.08:17:54.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:17:54.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:17:54.46#ibcon#ireg 8 cls_cnt 0 2006.245.08:17:54.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:17:54.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:17:54.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:17:54.53#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:17:54.53#ibcon#first serial, iclass 24, count 0 2006.245.08:17:54.53#ibcon#enter sib2, iclass 24, count 0 2006.245.08:17:54.53#ibcon#flushed, iclass 24, count 0 2006.245.08:17:54.53#ibcon#about to write, iclass 24, count 0 2006.245.08:17:54.53#ibcon#wrote, iclass 24, count 0 2006.245.08:17:54.53#ibcon#about to read 3, iclass 24, count 0 2006.245.08:17:54.55#ibcon#read 3, iclass 24, count 0 2006.245.08:17:54.55#ibcon#about to read 4, iclass 24, count 0 2006.245.08:17:54.55#ibcon#read 4, iclass 24, count 0 2006.245.08:17:54.55#ibcon#about to read 5, iclass 24, count 0 2006.245.08:17:54.55#ibcon#read 5, iclass 24, count 0 2006.245.08:17:54.55#ibcon#about to read 6, iclass 24, count 0 2006.245.08:17:54.55#ibcon#read 6, iclass 24, count 0 2006.245.08:17:54.55#ibcon#end of sib2, iclass 24, count 0 2006.245.08:17:54.55#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:17:54.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:17:54.55#ibcon#[27=BW32\r\n] 2006.245.08:17:54.55#ibcon#*before write, iclass 24, count 0 2006.245.08:17:54.55#ibcon#enter sib2, iclass 24, count 0 2006.245.08:17:54.55#ibcon#flushed, iclass 24, count 0 2006.245.08:17:54.55#ibcon#about to write, iclass 24, count 0 2006.245.08:17:54.55#ibcon#wrote, iclass 24, count 0 2006.245.08:17:54.55#ibcon#about to read 3, iclass 24, count 0 2006.245.08:17:54.58#ibcon#read 3, iclass 24, count 0 2006.245.08:17:54.58#ibcon#about to read 4, iclass 24, count 0 2006.245.08:17:54.58#ibcon#read 4, iclass 24, count 0 2006.245.08:17:54.58#ibcon#about to read 5, iclass 24, count 0 2006.245.08:17:54.58#ibcon#read 5, iclass 24, count 0 2006.245.08:17:54.58#ibcon#about to read 6, iclass 24, count 0 2006.245.08:17:54.58#ibcon#read 6, iclass 24, count 0 2006.245.08:17:54.58#ibcon#end of sib2, iclass 24, count 0 2006.245.08:17:54.58#ibcon#*after write, iclass 24, count 0 2006.245.08:17:54.58#ibcon#*before return 0, iclass 24, count 0 2006.245.08:17:54.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:17:54.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:17:54.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:17:54.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:17:54.58$4f8m12a/ifd4f 2006.245.08:17:54.58$ifd4f/lo= 2006.245.08:17:54.58$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:17:54.58$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:17:54.58$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:17:54.58$ifd4f/patch= 2006.245.08:17:54.58$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:17:54.58$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:17:54.58$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:17:54.58$4f8m12a/"form=m,16.000,1:2 2006.245.08:17:54.58$4f8m12a/"tpicd 2006.245.08:17:54.58$4f8m12a/echo=off 2006.245.08:17:54.58$4f8m12a/xlog=off 2006.245.08:17:54.58:!2006.245.08:18:20 2006.245.08:18:03.14#trakl#Source acquired 2006.245.08:18:05.14#flagr#flagr/antenna,acquired 2006.245.08:18:20.00:preob 2006.245.08:18:21.14/onsource/TRACKING 2006.245.08:18:21.14:!2006.245.08:18:30 2006.245.08:18:30.00:data_valid=on 2006.245.08:18:30.00:midob 2006.245.08:18:30.14/onsource/TRACKING 2006.245.08:18:30.14/wx/26.78,1004.6,75 2006.245.08:18:30.30/cable/+6.4118E-03 2006.245.08:18:31.39/va/01,08,usb,yes,31,32 2006.245.08:18:31.39/va/02,07,usb,yes,31,32 2006.245.08:18:31.39/va/03,06,usb,yes,33,33 2006.245.08:18:31.39/va/04,07,usb,yes,32,34 2006.245.08:18:31.39/va/05,07,usb,yes,33,35 2006.245.08:18:31.39/va/06,07,usb,yes,29,29 2006.245.08:18:31.39/va/07,07,usb,yes,29,29 2006.245.08:18:31.39/va/08,08,usb,yes,25,25 2006.245.08:18:31.62/valo/01,532.99,yes,locked 2006.245.08:18:31.62/valo/02,572.99,yes,locked 2006.245.08:18:31.62/valo/03,672.99,yes,locked 2006.245.08:18:31.62/valo/04,832.99,yes,locked 2006.245.08:18:31.62/valo/05,652.99,yes,locked 2006.245.08:18:31.62/valo/06,772.99,yes,locked 2006.245.08:18:31.62/valo/07,832.99,yes,locked 2006.245.08:18:31.62/valo/08,852.99,yes,locked 2006.245.08:18:32.71/vb/01,04,usb,yes,30,29 2006.245.08:18:32.71/vb/02,04,usb,yes,32,34 2006.245.08:18:32.71/vb/03,04,usb,yes,28,32 2006.245.08:18:32.71/vb/04,04,usb,yes,29,29 2006.245.08:18:32.71/vb/05,03,usb,yes,35,39 2006.245.08:18:32.71/vb/06,03,usb,yes,35,39 2006.245.08:18:32.71/vb/07,04,usb,yes,31,31 2006.245.08:18:32.71/vb/08,03,usb,yes,35,39 2006.245.08:18:32.95/vblo/01,632.99,yes,locked 2006.245.08:18:32.95/vblo/02,640.99,yes,locked 2006.245.08:18:32.95/vblo/03,656.99,yes,locked 2006.245.08:18:32.95/vblo/04,712.99,yes,locked 2006.245.08:18:32.95/vblo/05,744.99,yes,locked 2006.245.08:18:32.95/vblo/06,752.99,yes,locked 2006.245.08:18:32.95/vblo/07,734.99,yes,locked 2006.245.08:18:32.95/vblo/08,744.99,yes,locked 2006.245.08:18:33.10/vabw/8 2006.245.08:18:33.25/vbbw/8 2006.245.08:18:33.34/xfe/off,on,13.7 2006.245.08:18:33.71/ifatt/23,28,28,28 2006.245.08:18:34.08/fmout-gps/S +4.37E-07 2006.245.08:18:34.12:!2006.245.08:19:30 2006.245.08:19:30.00:data_valid=off 2006.245.08:19:30.00:postob 2006.245.08:19:30.10/cable/+6.4104E-03 2006.245.08:19:30.10/wx/26.75,1004.5,75 2006.245.08:19:31.08/fmout-gps/S +4.36E-07 2006.245.08:19:31.08:scan_name=245-0821,k06245,60 2006.245.08:19:31.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.245.08:19:31.14#flagr#flagr/antenna,new-source 2006.245.08:19:32.14:checkk5 2006.245.08:19:32.72/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:19:33.24/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:19:33.69/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:19:34.29/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:19:34.71/chk_obsdata//k5ts1/T2450818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:19:35.13/chk_obsdata//k5ts2/T2450818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:19:35.57/chk_obsdata//k5ts3/T2450818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:19:35.99/chk_obsdata//k5ts4/T2450818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:19:36.86/k5log//k5ts1_log_newline 2006.245.08:19:37.94/k5log//k5ts2_log_newline 2006.245.08:19:38.74/k5log//k5ts3_log_newline 2006.245.08:19:39.59/k5log//k5ts4_log_newline 2006.245.08:19:39.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:19:39.62:4f8m12a=3 2006.245.08:19:39.62$4f8m12a/echo=on 2006.245.08:19:39.62$4f8m12a/pcalon 2006.245.08:19:39.62$pcalon/"no phase cal control is implemented here 2006.245.08:19:39.62$4f8m12a/"tpicd=stop 2006.245.08:19:39.62$4f8m12a/vc4f8 2006.245.08:19:39.62$vc4f8/valo=1,532.99 2006.245.08:19:39.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.08:19:39.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.08:19:39.62#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:39.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:39.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:39.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:39.62#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:19:39.62#ibcon#first serial, iclass 31, count 0 2006.245.08:19:39.62#ibcon#enter sib2, iclass 31, count 0 2006.245.08:19:39.62#ibcon#flushed, iclass 31, count 0 2006.245.08:19:39.62#ibcon#about to write, iclass 31, count 0 2006.245.08:19:39.62#ibcon#wrote, iclass 31, count 0 2006.245.08:19:39.62#ibcon#about to read 3, iclass 31, count 0 2006.245.08:19:39.66#ibcon#read 3, iclass 31, count 0 2006.245.08:19:39.66#ibcon#about to read 4, iclass 31, count 0 2006.245.08:19:39.66#ibcon#read 4, iclass 31, count 0 2006.245.08:19:39.66#ibcon#about to read 5, iclass 31, count 0 2006.245.08:19:39.66#ibcon#read 5, iclass 31, count 0 2006.245.08:19:39.66#ibcon#about to read 6, iclass 31, count 0 2006.245.08:19:39.66#ibcon#read 6, iclass 31, count 0 2006.245.08:19:39.66#ibcon#end of sib2, iclass 31, count 0 2006.245.08:19:39.66#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:19:39.66#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:19:39.66#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:19:39.66#ibcon#*before write, iclass 31, count 0 2006.245.08:19:39.66#ibcon#enter sib2, iclass 31, count 0 2006.245.08:19:39.66#ibcon#flushed, iclass 31, count 0 2006.245.08:19:39.66#ibcon#about to write, iclass 31, count 0 2006.245.08:19:39.66#ibcon#wrote, iclass 31, count 0 2006.245.08:19:39.66#ibcon#about to read 3, iclass 31, count 0 2006.245.08:19:39.71#ibcon#read 3, iclass 31, count 0 2006.245.08:19:39.71#ibcon#about to read 4, iclass 31, count 0 2006.245.08:19:39.71#ibcon#read 4, iclass 31, count 0 2006.245.08:19:39.71#ibcon#about to read 5, iclass 31, count 0 2006.245.08:19:39.71#ibcon#read 5, iclass 31, count 0 2006.245.08:19:39.71#ibcon#about to read 6, iclass 31, count 0 2006.245.08:19:39.71#ibcon#read 6, iclass 31, count 0 2006.245.08:19:39.71#ibcon#end of sib2, iclass 31, count 0 2006.245.08:19:39.71#ibcon#*after write, iclass 31, count 0 2006.245.08:19:39.71#ibcon#*before return 0, iclass 31, count 0 2006.245.08:19:39.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:39.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:39.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:19:39.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:19:39.71$vc4f8/va=1,8 2006.245.08:19:39.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.08:19:39.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.08:19:39.71#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:39.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:39.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:39.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:39.71#ibcon#enter wrdev, iclass 33, count 2 2006.245.08:19:39.71#ibcon#first serial, iclass 33, count 2 2006.245.08:19:39.71#ibcon#enter sib2, iclass 33, count 2 2006.245.08:19:39.71#ibcon#flushed, iclass 33, count 2 2006.245.08:19:39.71#ibcon#about to write, iclass 33, count 2 2006.245.08:19:39.71#ibcon#wrote, iclass 33, count 2 2006.245.08:19:39.71#ibcon#about to read 3, iclass 33, count 2 2006.245.08:19:39.73#ibcon#read 3, iclass 33, count 2 2006.245.08:19:39.73#ibcon#about to read 4, iclass 33, count 2 2006.245.08:19:39.73#ibcon#read 4, iclass 33, count 2 2006.245.08:19:39.73#ibcon#about to read 5, iclass 33, count 2 2006.245.08:19:39.73#ibcon#read 5, iclass 33, count 2 2006.245.08:19:39.73#ibcon#about to read 6, iclass 33, count 2 2006.245.08:19:39.73#ibcon#read 6, iclass 33, count 2 2006.245.08:19:39.73#ibcon#end of sib2, iclass 33, count 2 2006.245.08:19:39.73#ibcon#*mode == 0, iclass 33, count 2 2006.245.08:19:39.73#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.08:19:39.73#ibcon#[25=AT01-08\r\n] 2006.245.08:19:39.73#ibcon#*before write, iclass 33, count 2 2006.245.08:19:39.73#ibcon#enter sib2, iclass 33, count 2 2006.245.08:19:39.73#ibcon#flushed, iclass 33, count 2 2006.245.08:19:39.73#ibcon#about to write, iclass 33, count 2 2006.245.08:19:39.73#ibcon#wrote, iclass 33, count 2 2006.245.08:19:39.73#ibcon#about to read 3, iclass 33, count 2 2006.245.08:19:39.76#ibcon#read 3, iclass 33, count 2 2006.245.08:19:39.76#ibcon#about to read 4, iclass 33, count 2 2006.245.08:19:39.76#ibcon#read 4, iclass 33, count 2 2006.245.08:19:39.76#ibcon#about to read 5, iclass 33, count 2 2006.245.08:19:39.76#ibcon#read 5, iclass 33, count 2 2006.245.08:19:39.76#ibcon#about to read 6, iclass 33, count 2 2006.245.08:19:39.76#ibcon#read 6, iclass 33, count 2 2006.245.08:19:39.76#ibcon#end of sib2, iclass 33, count 2 2006.245.08:19:39.76#ibcon#*after write, iclass 33, count 2 2006.245.08:19:39.76#ibcon#*before return 0, iclass 33, count 2 2006.245.08:19:39.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:39.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:39.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.08:19:39.76#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:39.76#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:39.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:39.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:39.88#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:19:39.88#ibcon#first serial, iclass 33, count 0 2006.245.08:19:39.88#ibcon#enter sib2, iclass 33, count 0 2006.245.08:19:39.88#ibcon#flushed, iclass 33, count 0 2006.245.08:19:39.88#ibcon#about to write, iclass 33, count 0 2006.245.08:19:39.88#ibcon#wrote, iclass 33, count 0 2006.245.08:19:39.88#ibcon#about to read 3, iclass 33, count 0 2006.245.08:19:39.90#ibcon#read 3, iclass 33, count 0 2006.245.08:19:39.90#ibcon#about to read 4, iclass 33, count 0 2006.245.08:19:39.90#ibcon#read 4, iclass 33, count 0 2006.245.08:19:39.90#ibcon#about to read 5, iclass 33, count 0 2006.245.08:19:39.90#ibcon#read 5, iclass 33, count 0 2006.245.08:19:39.90#ibcon#about to read 6, iclass 33, count 0 2006.245.08:19:39.90#ibcon#read 6, iclass 33, count 0 2006.245.08:19:39.90#ibcon#end of sib2, iclass 33, count 0 2006.245.08:19:39.90#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:19:39.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:19:39.90#ibcon#[25=USB\r\n] 2006.245.08:19:39.90#ibcon#*before write, iclass 33, count 0 2006.245.08:19:39.90#ibcon#enter sib2, iclass 33, count 0 2006.245.08:19:39.90#ibcon#flushed, iclass 33, count 0 2006.245.08:19:39.90#ibcon#about to write, iclass 33, count 0 2006.245.08:19:39.90#ibcon#wrote, iclass 33, count 0 2006.245.08:19:39.90#ibcon#about to read 3, iclass 33, count 0 2006.245.08:19:39.93#ibcon#read 3, iclass 33, count 0 2006.245.08:19:39.93#ibcon#about to read 4, iclass 33, count 0 2006.245.08:19:39.93#ibcon#read 4, iclass 33, count 0 2006.245.08:19:39.93#ibcon#about to read 5, iclass 33, count 0 2006.245.08:19:39.93#ibcon#read 5, iclass 33, count 0 2006.245.08:19:39.93#ibcon#about to read 6, iclass 33, count 0 2006.245.08:19:39.93#ibcon#read 6, iclass 33, count 0 2006.245.08:19:39.93#ibcon#end of sib2, iclass 33, count 0 2006.245.08:19:39.93#ibcon#*after write, iclass 33, count 0 2006.245.08:19:39.93#ibcon#*before return 0, iclass 33, count 0 2006.245.08:19:39.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:39.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:39.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:19:39.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:19:39.93$vc4f8/valo=2,572.99 2006.245.08:19:39.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.08:19:39.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.08:19:39.93#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:39.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:39.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:39.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:39.93#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:19:39.93#ibcon#first serial, iclass 35, count 0 2006.245.08:19:39.93#ibcon#enter sib2, iclass 35, count 0 2006.245.08:19:39.93#ibcon#flushed, iclass 35, count 0 2006.245.08:19:39.93#ibcon#about to write, iclass 35, count 0 2006.245.08:19:39.93#ibcon#wrote, iclass 35, count 0 2006.245.08:19:39.93#ibcon#about to read 3, iclass 35, count 0 2006.245.08:19:39.95#ibcon#read 3, iclass 35, count 0 2006.245.08:19:39.95#ibcon#about to read 4, iclass 35, count 0 2006.245.08:19:39.95#ibcon#read 4, iclass 35, count 0 2006.245.08:19:39.95#ibcon#about to read 5, iclass 35, count 0 2006.245.08:19:39.95#ibcon#read 5, iclass 35, count 0 2006.245.08:19:39.95#ibcon#about to read 6, iclass 35, count 0 2006.245.08:19:39.95#ibcon#read 6, iclass 35, count 0 2006.245.08:19:39.95#ibcon#end of sib2, iclass 35, count 0 2006.245.08:19:39.95#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:19:39.95#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:19:39.95#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:19:39.95#ibcon#*before write, iclass 35, count 0 2006.245.08:19:39.95#ibcon#enter sib2, iclass 35, count 0 2006.245.08:19:39.95#ibcon#flushed, iclass 35, count 0 2006.245.08:19:39.95#ibcon#about to write, iclass 35, count 0 2006.245.08:19:39.95#ibcon#wrote, iclass 35, count 0 2006.245.08:19:39.95#ibcon#about to read 3, iclass 35, count 0 2006.245.08:19:39.99#ibcon#read 3, iclass 35, count 0 2006.245.08:19:39.99#ibcon#about to read 4, iclass 35, count 0 2006.245.08:19:39.99#ibcon#read 4, iclass 35, count 0 2006.245.08:19:39.99#ibcon#about to read 5, iclass 35, count 0 2006.245.08:19:39.99#ibcon#read 5, iclass 35, count 0 2006.245.08:19:39.99#ibcon#about to read 6, iclass 35, count 0 2006.245.08:19:39.99#ibcon#read 6, iclass 35, count 0 2006.245.08:19:39.99#ibcon#end of sib2, iclass 35, count 0 2006.245.08:19:39.99#ibcon#*after write, iclass 35, count 0 2006.245.08:19:39.99#ibcon#*before return 0, iclass 35, count 0 2006.245.08:19:39.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:39.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:39.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:19:39.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:19:39.99$vc4f8/va=2,7 2006.245.08:19:39.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.08:19:39.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.08:19:39.99#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:39.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:40.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:40.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:40.05#ibcon#enter wrdev, iclass 37, count 2 2006.245.08:19:40.05#ibcon#first serial, iclass 37, count 2 2006.245.08:19:40.05#ibcon#enter sib2, iclass 37, count 2 2006.245.08:19:40.05#ibcon#flushed, iclass 37, count 2 2006.245.08:19:40.05#ibcon#about to write, iclass 37, count 2 2006.245.08:19:40.05#ibcon#wrote, iclass 37, count 2 2006.245.08:19:40.05#ibcon#about to read 3, iclass 37, count 2 2006.245.08:19:40.07#ibcon#read 3, iclass 37, count 2 2006.245.08:19:40.07#ibcon#about to read 4, iclass 37, count 2 2006.245.08:19:40.07#ibcon#read 4, iclass 37, count 2 2006.245.08:19:40.07#ibcon#about to read 5, iclass 37, count 2 2006.245.08:19:40.07#ibcon#read 5, iclass 37, count 2 2006.245.08:19:40.07#ibcon#about to read 6, iclass 37, count 2 2006.245.08:19:40.07#ibcon#read 6, iclass 37, count 2 2006.245.08:19:40.07#ibcon#end of sib2, iclass 37, count 2 2006.245.08:19:40.07#ibcon#*mode == 0, iclass 37, count 2 2006.245.08:19:40.07#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.08:19:40.07#ibcon#[25=AT02-07\r\n] 2006.245.08:19:40.07#ibcon#*before write, iclass 37, count 2 2006.245.08:19:40.07#ibcon#enter sib2, iclass 37, count 2 2006.245.08:19:40.07#ibcon#flushed, iclass 37, count 2 2006.245.08:19:40.07#ibcon#about to write, iclass 37, count 2 2006.245.08:19:40.07#ibcon#wrote, iclass 37, count 2 2006.245.08:19:40.07#ibcon#about to read 3, iclass 37, count 2 2006.245.08:19:40.10#ibcon#read 3, iclass 37, count 2 2006.245.08:19:40.10#ibcon#about to read 4, iclass 37, count 2 2006.245.08:19:40.10#ibcon#read 4, iclass 37, count 2 2006.245.08:19:40.10#ibcon#about to read 5, iclass 37, count 2 2006.245.08:19:40.10#ibcon#read 5, iclass 37, count 2 2006.245.08:19:40.10#ibcon#about to read 6, iclass 37, count 2 2006.245.08:19:40.10#ibcon#read 6, iclass 37, count 2 2006.245.08:19:40.10#ibcon#end of sib2, iclass 37, count 2 2006.245.08:19:40.10#ibcon#*after write, iclass 37, count 2 2006.245.08:19:40.10#ibcon#*before return 0, iclass 37, count 2 2006.245.08:19:40.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:40.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:40.10#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.08:19:40.10#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:40.10#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:40.22#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:40.22#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:40.22#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:19:40.22#ibcon#first serial, iclass 37, count 0 2006.245.08:19:40.22#ibcon#enter sib2, iclass 37, count 0 2006.245.08:19:40.22#ibcon#flushed, iclass 37, count 0 2006.245.08:19:40.22#ibcon#about to write, iclass 37, count 0 2006.245.08:19:40.22#ibcon#wrote, iclass 37, count 0 2006.245.08:19:40.22#ibcon#about to read 3, iclass 37, count 0 2006.245.08:19:40.25#ibcon#read 3, iclass 37, count 0 2006.245.08:19:40.25#ibcon#about to read 4, iclass 37, count 0 2006.245.08:19:40.25#ibcon#read 4, iclass 37, count 0 2006.245.08:19:40.25#ibcon#about to read 5, iclass 37, count 0 2006.245.08:19:40.25#ibcon#read 5, iclass 37, count 0 2006.245.08:19:40.25#ibcon#about to read 6, iclass 37, count 0 2006.245.08:19:40.25#ibcon#read 6, iclass 37, count 0 2006.245.08:19:40.25#ibcon#end of sib2, iclass 37, count 0 2006.245.08:19:40.25#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:19:40.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:19:40.25#ibcon#[25=USB\r\n] 2006.245.08:19:40.25#ibcon#*before write, iclass 37, count 0 2006.245.08:19:40.25#ibcon#enter sib2, iclass 37, count 0 2006.245.08:19:40.25#ibcon#flushed, iclass 37, count 0 2006.245.08:19:40.25#ibcon#about to write, iclass 37, count 0 2006.245.08:19:40.25#ibcon#wrote, iclass 37, count 0 2006.245.08:19:40.25#ibcon#about to read 3, iclass 37, count 0 2006.245.08:19:40.28#ibcon#read 3, iclass 37, count 0 2006.245.08:19:40.28#ibcon#about to read 4, iclass 37, count 0 2006.245.08:19:40.28#ibcon#read 4, iclass 37, count 0 2006.245.08:19:40.28#ibcon#about to read 5, iclass 37, count 0 2006.245.08:19:40.28#ibcon#read 5, iclass 37, count 0 2006.245.08:19:40.28#ibcon#about to read 6, iclass 37, count 0 2006.245.08:19:40.28#ibcon#read 6, iclass 37, count 0 2006.245.08:19:40.28#ibcon#end of sib2, iclass 37, count 0 2006.245.08:19:40.28#ibcon#*after write, iclass 37, count 0 2006.245.08:19:40.28#ibcon#*before return 0, iclass 37, count 0 2006.245.08:19:40.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:40.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:40.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:19:40.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:19:40.28$vc4f8/valo=3,672.99 2006.245.08:19:40.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.08:19:40.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.08:19:40.28#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:40.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:40.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:40.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:40.28#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:19:40.28#ibcon#first serial, iclass 39, count 0 2006.245.08:19:40.28#ibcon#enter sib2, iclass 39, count 0 2006.245.08:19:40.28#ibcon#flushed, iclass 39, count 0 2006.245.08:19:40.28#ibcon#about to write, iclass 39, count 0 2006.245.08:19:40.28#ibcon#wrote, iclass 39, count 0 2006.245.08:19:40.28#ibcon#about to read 3, iclass 39, count 0 2006.245.08:19:40.30#ibcon#read 3, iclass 39, count 0 2006.245.08:19:40.30#ibcon#about to read 4, iclass 39, count 0 2006.245.08:19:40.30#ibcon#read 4, iclass 39, count 0 2006.245.08:19:40.30#ibcon#about to read 5, iclass 39, count 0 2006.245.08:19:40.30#ibcon#read 5, iclass 39, count 0 2006.245.08:19:40.30#ibcon#about to read 6, iclass 39, count 0 2006.245.08:19:40.30#ibcon#read 6, iclass 39, count 0 2006.245.08:19:40.30#ibcon#end of sib2, iclass 39, count 0 2006.245.08:19:40.30#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:19:40.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:19:40.30#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:19:40.30#ibcon#*before write, iclass 39, count 0 2006.245.08:19:40.30#ibcon#enter sib2, iclass 39, count 0 2006.245.08:19:40.30#ibcon#flushed, iclass 39, count 0 2006.245.08:19:40.30#ibcon#about to write, iclass 39, count 0 2006.245.08:19:40.30#ibcon#wrote, iclass 39, count 0 2006.245.08:19:40.30#ibcon#about to read 3, iclass 39, count 0 2006.245.08:19:40.34#ibcon#read 3, iclass 39, count 0 2006.245.08:19:40.34#ibcon#about to read 4, iclass 39, count 0 2006.245.08:19:40.34#ibcon#read 4, iclass 39, count 0 2006.245.08:19:40.34#ibcon#about to read 5, iclass 39, count 0 2006.245.08:19:40.34#ibcon#read 5, iclass 39, count 0 2006.245.08:19:40.34#ibcon#about to read 6, iclass 39, count 0 2006.245.08:19:40.34#ibcon#read 6, iclass 39, count 0 2006.245.08:19:40.34#ibcon#end of sib2, iclass 39, count 0 2006.245.08:19:40.34#ibcon#*after write, iclass 39, count 0 2006.245.08:19:40.34#ibcon#*before return 0, iclass 39, count 0 2006.245.08:19:40.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:40.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:40.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:19:40.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:19:40.34$vc4f8/va=3,6 2006.245.08:19:40.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.08:19:40.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.08:19:40.34#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:40.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:40.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:40.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:40.40#ibcon#enter wrdev, iclass 3, count 2 2006.245.08:19:40.40#ibcon#first serial, iclass 3, count 2 2006.245.08:19:40.40#ibcon#enter sib2, iclass 3, count 2 2006.245.08:19:40.40#ibcon#flushed, iclass 3, count 2 2006.245.08:19:40.40#ibcon#about to write, iclass 3, count 2 2006.245.08:19:40.40#ibcon#wrote, iclass 3, count 2 2006.245.08:19:40.40#ibcon#about to read 3, iclass 3, count 2 2006.245.08:19:40.42#ibcon#read 3, iclass 3, count 2 2006.245.08:19:40.42#ibcon#about to read 4, iclass 3, count 2 2006.245.08:19:40.42#ibcon#read 4, iclass 3, count 2 2006.245.08:19:40.42#ibcon#about to read 5, iclass 3, count 2 2006.245.08:19:40.42#ibcon#read 5, iclass 3, count 2 2006.245.08:19:40.42#ibcon#about to read 6, iclass 3, count 2 2006.245.08:19:40.42#ibcon#read 6, iclass 3, count 2 2006.245.08:19:40.42#ibcon#end of sib2, iclass 3, count 2 2006.245.08:19:40.42#ibcon#*mode == 0, iclass 3, count 2 2006.245.08:19:40.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.08:19:40.42#ibcon#[25=AT03-06\r\n] 2006.245.08:19:40.42#ibcon#*before write, iclass 3, count 2 2006.245.08:19:40.42#ibcon#enter sib2, iclass 3, count 2 2006.245.08:19:40.42#ibcon#flushed, iclass 3, count 2 2006.245.08:19:40.42#ibcon#about to write, iclass 3, count 2 2006.245.08:19:40.42#ibcon#wrote, iclass 3, count 2 2006.245.08:19:40.42#ibcon#about to read 3, iclass 3, count 2 2006.245.08:19:40.46#ibcon#read 3, iclass 3, count 2 2006.245.08:19:40.46#ibcon#about to read 4, iclass 3, count 2 2006.245.08:19:40.46#ibcon#read 4, iclass 3, count 2 2006.245.08:19:40.46#ibcon#about to read 5, iclass 3, count 2 2006.245.08:19:40.46#ibcon#read 5, iclass 3, count 2 2006.245.08:19:40.46#ibcon#about to read 6, iclass 3, count 2 2006.245.08:19:40.46#ibcon#read 6, iclass 3, count 2 2006.245.08:19:40.46#ibcon#end of sib2, iclass 3, count 2 2006.245.08:19:40.46#ibcon#*after write, iclass 3, count 2 2006.245.08:19:40.46#ibcon#*before return 0, iclass 3, count 2 2006.245.08:19:40.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:40.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:40.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.08:19:40.46#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:40.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:40.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:40.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:40.58#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:19:40.58#ibcon#first serial, iclass 3, count 0 2006.245.08:19:40.58#ibcon#enter sib2, iclass 3, count 0 2006.245.08:19:40.58#ibcon#flushed, iclass 3, count 0 2006.245.08:19:40.58#ibcon#about to write, iclass 3, count 0 2006.245.08:19:40.58#ibcon#wrote, iclass 3, count 0 2006.245.08:19:40.58#ibcon#about to read 3, iclass 3, count 0 2006.245.08:19:40.60#ibcon#read 3, iclass 3, count 0 2006.245.08:19:40.60#ibcon#about to read 4, iclass 3, count 0 2006.245.08:19:40.60#ibcon#read 4, iclass 3, count 0 2006.245.08:19:40.60#ibcon#about to read 5, iclass 3, count 0 2006.245.08:19:40.60#ibcon#read 5, iclass 3, count 0 2006.245.08:19:40.60#ibcon#about to read 6, iclass 3, count 0 2006.245.08:19:40.60#ibcon#read 6, iclass 3, count 0 2006.245.08:19:40.60#ibcon#end of sib2, iclass 3, count 0 2006.245.08:19:40.60#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:19:40.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:19:40.60#ibcon#[25=USB\r\n] 2006.245.08:19:40.60#ibcon#*before write, iclass 3, count 0 2006.245.08:19:40.60#ibcon#enter sib2, iclass 3, count 0 2006.245.08:19:40.60#ibcon#flushed, iclass 3, count 0 2006.245.08:19:40.60#ibcon#about to write, iclass 3, count 0 2006.245.08:19:40.60#ibcon#wrote, iclass 3, count 0 2006.245.08:19:40.60#ibcon#about to read 3, iclass 3, count 0 2006.245.08:19:40.63#ibcon#read 3, iclass 3, count 0 2006.245.08:19:40.63#ibcon#about to read 4, iclass 3, count 0 2006.245.08:19:40.63#ibcon#read 4, iclass 3, count 0 2006.245.08:19:40.63#ibcon#about to read 5, iclass 3, count 0 2006.245.08:19:40.63#ibcon#read 5, iclass 3, count 0 2006.245.08:19:40.63#ibcon#about to read 6, iclass 3, count 0 2006.245.08:19:40.63#ibcon#read 6, iclass 3, count 0 2006.245.08:19:40.63#ibcon#end of sib2, iclass 3, count 0 2006.245.08:19:40.63#ibcon#*after write, iclass 3, count 0 2006.245.08:19:40.63#ibcon#*before return 0, iclass 3, count 0 2006.245.08:19:40.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:40.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:40.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:19:40.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:19:40.63$vc4f8/valo=4,832.99 2006.245.08:19:40.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.08:19:40.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.08:19:40.63#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:40.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:40.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:40.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:40.63#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:19:40.63#ibcon#first serial, iclass 5, count 0 2006.245.08:19:40.63#ibcon#enter sib2, iclass 5, count 0 2006.245.08:19:40.63#ibcon#flushed, iclass 5, count 0 2006.245.08:19:40.63#ibcon#about to write, iclass 5, count 0 2006.245.08:19:40.63#ibcon#wrote, iclass 5, count 0 2006.245.08:19:40.63#ibcon#about to read 3, iclass 5, count 0 2006.245.08:19:40.65#ibcon#read 3, iclass 5, count 0 2006.245.08:19:40.65#ibcon#about to read 4, iclass 5, count 0 2006.245.08:19:40.65#ibcon#read 4, iclass 5, count 0 2006.245.08:19:40.65#ibcon#about to read 5, iclass 5, count 0 2006.245.08:19:40.65#ibcon#read 5, iclass 5, count 0 2006.245.08:19:40.65#ibcon#about to read 6, iclass 5, count 0 2006.245.08:19:40.65#ibcon#read 6, iclass 5, count 0 2006.245.08:19:40.65#ibcon#end of sib2, iclass 5, count 0 2006.245.08:19:40.65#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:19:40.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:19:40.65#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:19:40.65#ibcon#*before write, iclass 5, count 0 2006.245.08:19:40.65#ibcon#enter sib2, iclass 5, count 0 2006.245.08:19:40.65#ibcon#flushed, iclass 5, count 0 2006.245.08:19:40.65#ibcon#about to write, iclass 5, count 0 2006.245.08:19:40.65#ibcon#wrote, iclass 5, count 0 2006.245.08:19:40.65#ibcon#about to read 3, iclass 5, count 0 2006.245.08:19:40.69#ibcon#read 3, iclass 5, count 0 2006.245.08:19:40.69#ibcon#about to read 4, iclass 5, count 0 2006.245.08:19:40.69#ibcon#read 4, iclass 5, count 0 2006.245.08:19:40.69#ibcon#about to read 5, iclass 5, count 0 2006.245.08:19:40.69#ibcon#read 5, iclass 5, count 0 2006.245.08:19:40.69#ibcon#about to read 6, iclass 5, count 0 2006.245.08:19:40.69#ibcon#read 6, iclass 5, count 0 2006.245.08:19:40.69#ibcon#end of sib2, iclass 5, count 0 2006.245.08:19:40.69#ibcon#*after write, iclass 5, count 0 2006.245.08:19:40.69#ibcon#*before return 0, iclass 5, count 0 2006.245.08:19:40.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:40.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:40.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:19:40.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:19:40.69$vc4f8/va=4,7 2006.245.08:19:40.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.08:19:40.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.08:19:40.69#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:40.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:40.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:40.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:40.75#ibcon#enter wrdev, iclass 7, count 2 2006.245.08:19:40.75#ibcon#first serial, iclass 7, count 2 2006.245.08:19:40.75#ibcon#enter sib2, iclass 7, count 2 2006.245.08:19:40.75#ibcon#flushed, iclass 7, count 2 2006.245.08:19:40.75#ibcon#about to write, iclass 7, count 2 2006.245.08:19:40.75#ibcon#wrote, iclass 7, count 2 2006.245.08:19:40.75#ibcon#about to read 3, iclass 7, count 2 2006.245.08:19:40.77#ibcon#read 3, iclass 7, count 2 2006.245.08:19:40.77#ibcon#about to read 4, iclass 7, count 2 2006.245.08:19:40.77#ibcon#read 4, iclass 7, count 2 2006.245.08:19:40.77#ibcon#about to read 5, iclass 7, count 2 2006.245.08:19:40.77#ibcon#read 5, iclass 7, count 2 2006.245.08:19:40.77#ibcon#about to read 6, iclass 7, count 2 2006.245.08:19:40.77#ibcon#read 6, iclass 7, count 2 2006.245.08:19:40.77#ibcon#end of sib2, iclass 7, count 2 2006.245.08:19:40.77#ibcon#*mode == 0, iclass 7, count 2 2006.245.08:19:40.77#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.08:19:40.77#ibcon#[25=AT04-07\r\n] 2006.245.08:19:40.77#ibcon#*before write, iclass 7, count 2 2006.245.08:19:40.77#ibcon#enter sib2, iclass 7, count 2 2006.245.08:19:40.77#ibcon#flushed, iclass 7, count 2 2006.245.08:19:40.77#ibcon#about to write, iclass 7, count 2 2006.245.08:19:40.77#ibcon#wrote, iclass 7, count 2 2006.245.08:19:40.77#ibcon#about to read 3, iclass 7, count 2 2006.245.08:19:40.80#ibcon#read 3, iclass 7, count 2 2006.245.08:19:40.80#ibcon#about to read 4, iclass 7, count 2 2006.245.08:19:40.80#ibcon#read 4, iclass 7, count 2 2006.245.08:19:40.80#ibcon#about to read 5, iclass 7, count 2 2006.245.08:19:40.80#ibcon#read 5, iclass 7, count 2 2006.245.08:19:40.80#ibcon#about to read 6, iclass 7, count 2 2006.245.08:19:40.80#ibcon#read 6, iclass 7, count 2 2006.245.08:19:40.80#ibcon#end of sib2, iclass 7, count 2 2006.245.08:19:40.80#ibcon#*after write, iclass 7, count 2 2006.245.08:19:40.80#ibcon#*before return 0, iclass 7, count 2 2006.245.08:19:40.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:40.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:40.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.08:19:40.80#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:40.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:40.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:40.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:40.92#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:19:40.92#ibcon#first serial, iclass 7, count 0 2006.245.08:19:40.92#ibcon#enter sib2, iclass 7, count 0 2006.245.08:19:40.92#ibcon#flushed, iclass 7, count 0 2006.245.08:19:40.92#ibcon#about to write, iclass 7, count 0 2006.245.08:19:40.92#ibcon#wrote, iclass 7, count 0 2006.245.08:19:40.92#ibcon#about to read 3, iclass 7, count 0 2006.245.08:19:40.94#ibcon#read 3, iclass 7, count 0 2006.245.08:19:40.94#ibcon#about to read 4, iclass 7, count 0 2006.245.08:19:40.94#ibcon#read 4, iclass 7, count 0 2006.245.08:19:40.94#ibcon#about to read 5, iclass 7, count 0 2006.245.08:19:40.94#ibcon#read 5, iclass 7, count 0 2006.245.08:19:40.94#ibcon#about to read 6, iclass 7, count 0 2006.245.08:19:40.94#ibcon#read 6, iclass 7, count 0 2006.245.08:19:40.94#ibcon#end of sib2, iclass 7, count 0 2006.245.08:19:40.94#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:19:40.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:19:40.94#ibcon#[25=USB\r\n] 2006.245.08:19:40.94#ibcon#*before write, iclass 7, count 0 2006.245.08:19:40.94#ibcon#enter sib2, iclass 7, count 0 2006.245.08:19:40.94#ibcon#flushed, iclass 7, count 0 2006.245.08:19:40.94#ibcon#about to write, iclass 7, count 0 2006.245.08:19:40.94#ibcon#wrote, iclass 7, count 0 2006.245.08:19:40.94#ibcon#about to read 3, iclass 7, count 0 2006.245.08:19:40.97#ibcon#read 3, iclass 7, count 0 2006.245.08:19:40.97#ibcon#about to read 4, iclass 7, count 0 2006.245.08:19:40.97#ibcon#read 4, iclass 7, count 0 2006.245.08:19:40.97#ibcon#about to read 5, iclass 7, count 0 2006.245.08:19:40.97#ibcon#read 5, iclass 7, count 0 2006.245.08:19:40.97#ibcon#about to read 6, iclass 7, count 0 2006.245.08:19:40.97#ibcon#read 6, iclass 7, count 0 2006.245.08:19:40.97#ibcon#end of sib2, iclass 7, count 0 2006.245.08:19:40.97#ibcon#*after write, iclass 7, count 0 2006.245.08:19:40.97#ibcon#*before return 0, iclass 7, count 0 2006.245.08:19:40.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:40.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:40.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:19:40.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:19:40.97$vc4f8/valo=5,652.99 2006.245.08:19:40.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.08:19:40.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.08:19:40.97#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:40.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:40.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:40.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:40.97#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:19:40.97#ibcon#first serial, iclass 11, count 0 2006.245.08:19:40.97#ibcon#enter sib2, iclass 11, count 0 2006.245.08:19:40.97#ibcon#flushed, iclass 11, count 0 2006.245.08:19:40.97#ibcon#about to write, iclass 11, count 0 2006.245.08:19:40.97#ibcon#wrote, iclass 11, count 0 2006.245.08:19:40.97#ibcon#about to read 3, iclass 11, count 0 2006.245.08:19:40.99#ibcon#read 3, iclass 11, count 0 2006.245.08:19:40.99#ibcon#about to read 4, iclass 11, count 0 2006.245.08:19:40.99#ibcon#read 4, iclass 11, count 0 2006.245.08:19:40.99#ibcon#about to read 5, iclass 11, count 0 2006.245.08:19:40.99#ibcon#read 5, iclass 11, count 0 2006.245.08:19:40.99#ibcon#about to read 6, iclass 11, count 0 2006.245.08:19:40.99#ibcon#read 6, iclass 11, count 0 2006.245.08:19:40.99#ibcon#end of sib2, iclass 11, count 0 2006.245.08:19:40.99#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:19:40.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:19:40.99#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:19:40.99#ibcon#*before write, iclass 11, count 0 2006.245.08:19:40.99#ibcon#enter sib2, iclass 11, count 0 2006.245.08:19:40.99#ibcon#flushed, iclass 11, count 0 2006.245.08:19:40.99#ibcon#about to write, iclass 11, count 0 2006.245.08:19:40.99#ibcon#wrote, iclass 11, count 0 2006.245.08:19:40.99#ibcon#about to read 3, iclass 11, count 0 2006.245.08:19:41.03#ibcon#read 3, iclass 11, count 0 2006.245.08:19:41.03#ibcon#about to read 4, iclass 11, count 0 2006.245.08:19:41.03#ibcon#read 4, iclass 11, count 0 2006.245.08:19:41.03#ibcon#about to read 5, iclass 11, count 0 2006.245.08:19:41.03#ibcon#read 5, iclass 11, count 0 2006.245.08:19:41.03#ibcon#about to read 6, iclass 11, count 0 2006.245.08:19:41.03#ibcon#read 6, iclass 11, count 0 2006.245.08:19:41.03#ibcon#end of sib2, iclass 11, count 0 2006.245.08:19:41.03#ibcon#*after write, iclass 11, count 0 2006.245.08:19:41.03#ibcon#*before return 0, iclass 11, count 0 2006.245.08:19:41.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:41.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:41.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:19:41.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:19:41.03$vc4f8/va=5,7 2006.245.08:19:41.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:19:41.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:19:41.03#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:41.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:41.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:41.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:41.09#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:19:41.09#ibcon#first serial, iclass 13, count 2 2006.245.08:19:41.09#ibcon#enter sib2, iclass 13, count 2 2006.245.08:19:41.09#ibcon#flushed, iclass 13, count 2 2006.245.08:19:41.09#ibcon#about to write, iclass 13, count 2 2006.245.08:19:41.09#ibcon#wrote, iclass 13, count 2 2006.245.08:19:41.09#ibcon#about to read 3, iclass 13, count 2 2006.245.08:19:41.11#ibcon#read 3, iclass 13, count 2 2006.245.08:19:41.11#ibcon#about to read 4, iclass 13, count 2 2006.245.08:19:41.11#ibcon#read 4, iclass 13, count 2 2006.245.08:19:41.11#ibcon#about to read 5, iclass 13, count 2 2006.245.08:19:41.11#ibcon#read 5, iclass 13, count 2 2006.245.08:19:41.11#ibcon#about to read 6, iclass 13, count 2 2006.245.08:19:41.11#ibcon#read 6, iclass 13, count 2 2006.245.08:19:41.11#ibcon#end of sib2, iclass 13, count 2 2006.245.08:19:41.11#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:19:41.11#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:19:41.11#ibcon#[25=AT05-07\r\n] 2006.245.08:19:41.11#ibcon#*before write, iclass 13, count 2 2006.245.08:19:41.11#ibcon#enter sib2, iclass 13, count 2 2006.245.08:19:41.11#ibcon#flushed, iclass 13, count 2 2006.245.08:19:41.11#ibcon#about to write, iclass 13, count 2 2006.245.08:19:41.11#ibcon#wrote, iclass 13, count 2 2006.245.08:19:41.11#ibcon#about to read 3, iclass 13, count 2 2006.245.08:19:41.14#ibcon#read 3, iclass 13, count 2 2006.245.08:19:41.14#ibcon#about to read 4, iclass 13, count 2 2006.245.08:19:41.14#ibcon#read 4, iclass 13, count 2 2006.245.08:19:41.14#ibcon#about to read 5, iclass 13, count 2 2006.245.08:19:41.14#ibcon#read 5, iclass 13, count 2 2006.245.08:19:41.14#ibcon#about to read 6, iclass 13, count 2 2006.245.08:19:41.14#ibcon#read 6, iclass 13, count 2 2006.245.08:19:41.14#ibcon#end of sib2, iclass 13, count 2 2006.245.08:19:41.14#ibcon#*after write, iclass 13, count 2 2006.245.08:19:41.14#ibcon#*before return 0, iclass 13, count 2 2006.245.08:19:41.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:41.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:41.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:19:41.14#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:41.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:41.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:41.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:41.26#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:19:41.26#ibcon#first serial, iclass 13, count 0 2006.245.08:19:41.26#ibcon#enter sib2, iclass 13, count 0 2006.245.08:19:41.26#ibcon#flushed, iclass 13, count 0 2006.245.08:19:41.26#ibcon#about to write, iclass 13, count 0 2006.245.08:19:41.26#ibcon#wrote, iclass 13, count 0 2006.245.08:19:41.26#ibcon#about to read 3, iclass 13, count 0 2006.245.08:19:41.28#ibcon#read 3, iclass 13, count 0 2006.245.08:19:41.28#ibcon#about to read 4, iclass 13, count 0 2006.245.08:19:41.28#ibcon#read 4, iclass 13, count 0 2006.245.08:19:41.28#ibcon#about to read 5, iclass 13, count 0 2006.245.08:19:41.28#ibcon#read 5, iclass 13, count 0 2006.245.08:19:41.28#ibcon#about to read 6, iclass 13, count 0 2006.245.08:19:41.28#ibcon#read 6, iclass 13, count 0 2006.245.08:19:41.28#ibcon#end of sib2, iclass 13, count 0 2006.245.08:19:41.28#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:19:41.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:19:41.28#ibcon#[25=USB\r\n] 2006.245.08:19:41.28#ibcon#*before write, iclass 13, count 0 2006.245.08:19:41.28#ibcon#enter sib2, iclass 13, count 0 2006.245.08:19:41.28#ibcon#flushed, iclass 13, count 0 2006.245.08:19:41.28#ibcon#about to write, iclass 13, count 0 2006.245.08:19:41.28#ibcon#wrote, iclass 13, count 0 2006.245.08:19:41.28#ibcon#about to read 3, iclass 13, count 0 2006.245.08:19:41.31#ibcon#read 3, iclass 13, count 0 2006.245.08:19:41.31#ibcon#about to read 4, iclass 13, count 0 2006.245.08:19:41.31#ibcon#read 4, iclass 13, count 0 2006.245.08:19:41.31#ibcon#about to read 5, iclass 13, count 0 2006.245.08:19:41.31#ibcon#read 5, iclass 13, count 0 2006.245.08:19:41.31#ibcon#about to read 6, iclass 13, count 0 2006.245.08:19:41.31#ibcon#read 6, iclass 13, count 0 2006.245.08:19:41.31#ibcon#end of sib2, iclass 13, count 0 2006.245.08:19:41.31#ibcon#*after write, iclass 13, count 0 2006.245.08:19:41.31#ibcon#*before return 0, iclass 13, count 0 2006.245.08:19:41.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:41.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:41.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:19:41.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:19:41.31$vc4f8/valo=6,772.99 2006.245.08:19:41.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.08:19:41.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.08:19:41.31#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:41.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:41.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:41.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:41.31#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:19:41.31#ibcon#first serial, iclass 15, count 0 2006.245.08:19:41.31#ibcon#enter sib2, iclass 15, count 0 2006.245.08:19:41.31#ibcon#flushed, iclass 15, count 0 2006.245.08:19:41.31#ibcon#about to write, iclass 15, count 0 2006.245.08:19:41.31#ibcon#wrote, iclass 15, count 0 2006.245.08:19:41.31#ibcon#about to read 3, iclass 15, count 0 2006.245.08:19:41.33#ibcon#read 3, iclass 15, count 0 2006.245.08:19:41.33#ibcon#about to read 4, iclass 15, count 0 2006.245.08:19:41.33#ibcon#read 4, iclass 15, count 0 2006.245.08:19:41.33#ibcon#about to read 5, iclass 15, count 0 2006.245.08:19:41.33#ibcon#read 5, iclass 15, count 0 2006.245.08:19:41.33#ibcon#about to read 6, iclass 15, count 0 2006.245.08:19:41.33#ibcon#read 6, iclass 15, count 0 2006.245.08:19:41.33#ibcon#end of sib2, iclass 15, count 0 2006.245.08:19:41.33#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:19:41.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:19:41.33#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:19:41.33#ibcon#*before write, iclass 15, count 0 2006.245.08:19:41.33#ibcon#enter sib2, iclass 15, count 0 2006.245.08:19:41.33#ibcon#flushed, iclass 15, count 0 2006.245.08:19:41.33#ibcon#about to write, iclass 15, count 0 2006.245.08:19:41.33#ibcon#wrote, iclass 15, count 0 2006.245.08:19:41.33#ibcon#about to read 3, iclass 15, count 0 2006.245.08:19:41.37#ibcon#read 3, iclass 15, count 0 2006.245.08:19:41.37#ibcon#about to read 4, iclass 15, count 0 2006.245.08:19:41.37#ibcon#read 4, iclass 15, count 0 2006.245.08:19:41.37#ibcon#about to read 5, iclass 15, count 0 2006.245.08:19:41.37#ibcon#read 5, iclass 15, count 0 2006.245.08:19:41.37#ibcon#about to read 6, iclass 15, count 0 2006.245.08:19:41.37#ibcon#read 6, iclass 15, count 0 2006.245.08:19:41.37#ibcon#end of sib2, iclass 15, count 0 2006.245.08:19:41.37#ibcon#*after write, iclass 15, count 0 2006.245.08:19:41.37#ibcon#*before return 0, iclass 15, count 0 2006.245.08:19:41.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:41.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:41.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:19:41.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:19:41.37$vc4f8/va=6,7 2006.245.08:19:41.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.245.08:19:41.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.245.08:19:41.37#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:41.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:19:41.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:19:41.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:19:41.43#ibcon#enter wrdev, iclass 17, count 2 2006.245.08:19:41.43#ibcon#first serial, iclass 17, count 2 2006.245.08:19:41.43#ibcon#enter sib2, iclass 17, count 2 2006.245.08:19:41.43#ibcon#flushed, iclass 17, count 2 2006.245.08:19:41.43#ibcon#about to write, iclass 17, count 2 2006.245.08:19:41.43#ibcon#wrote, iclass 17, count 2 2006.245.08:19:41.43#ibcon#about to read 3, iclass 17, count 2 2006.245.08:19:41.45#ibcon#read 3, iclass 17, count 2 2006.245.08:19:41.45#ibcon#about to read 4, iclass 17, count 2 2006.245.08:19:41.45#ibcon#read 4, iclass 17, count 2 2006.245.08:19:41.45#ibcon#about to read 5, iclass 17, count 2 2006.245.08:19:41.45#ibcon#read 5, iclass 17, count 2 2006.245.08:19:41.45#ibcon#about to read 6, iclass 17, count 2 2006.245.08:19:41.45#ibcon#read 6, iclass 17, count 2 2006.245.08:19:41.45#ibcon#end of sib2, iclass 17, count 2 2006.245.08:19:41.45#ibcon#*mode == 0, iclass 17, count 2 2006.245.08:19:41.45#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.245.08:19:41.45#ibcon#[25=AT06-07\r\n] 2006.245.08:19:41.45#ibcon#*before write, iclass 17, count 2 2006.245.08:19:41.45#ibcon#enter sib2, iclass 17, count 2 2006.245.08:19:41.45#ibcon#flushed, iclass 17, count 2 2006.245.08:19:41.45#ibcon#about to write, iclass 17, count 2 2006.245.08:19:41.45#ibcon#wrote, iclass 17, count 2 2006.245.08:19:41.45#ibcon#about to read 3, iclass 17, count 2 2006.245.08:19:41.48#ibcon#read 3, iclass 17, count 2 2006.245.08:19:41.48#ibcon#about to read 4, iclass 17, count 2 2006.245.08:19:41.48#ibcon#read 4, iclass 17, count 2 2006.245.08:19:41.48#ibcon#about to read 5, iclass 17, count 2 2006.245.08:19:41.48#ibcon#read 5, iclass 17, count 2 2006.245.08:19:41.48#ibcon#about to read 6, iclass 17, count 2 2006.245.08:19:41.48#ibcon#read 6, iclass 17, count 2 2006.245.08:19:41.48#ibcon#end of sib2, iclass 17, count 2 2006.245.08:19:41.48#ibcon#*after write, iclass 17, count 2 2006.245.08:19:41.48#ibcon#*before return 0, iclass 17, count 2 2006.245.08:19:41.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:19:41.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.245.08:19:41.48#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.245.08:19:41.48#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:41.48#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:19:41.60#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:19:41.60#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:19:41.60#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:19:41.60#ibcon#first serial, iclass 17, count 0 2006.245.08:19:41.60#ibcon#enter sib2, iclass 17, count 0 2006.245.08:19:41.60#ibcon#flushed, iclass 17, count 0 2006.245.08:19:41.60#ibcon#about to write, iclass 17, count 0 2006.245.08:19:41.60#ibcon#wrote, iclass 17, count 0 2006.245.08:19:41.60#ibcon#about to read 3, iclass 17, count 0 2006.245.08:19:41.62#ibcon#read 3, iclass 17, count 0 2006.245.08:19:41.62#ibcon#about to read 4, iclass 17, count 0 2006.245.08:19:41.62#ibcon#read 4, iclass 17, count 0 2006.245.08:19:41.62#ibcon#about to read 5, iclass 17, count 0 2006.245.08:19:41.62#ibcon#read 5, iclass 17, count 0 2006.245.08:19:41.62#ibcon#about to read 6, iclass 17, count 0 2006.245.08:19:41.62#ibcon#read 6, iclass 17, count 0 2006.245.08:19:41.62#ibcon#end of sib2, iclass 17, count 0 2006.245.08:19:41.62#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:19:41.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:19:41.62#ibcon#[25=USB\r\n] 2006.245.08:19:41.62#ibcon#*before write, iclass 17, count 0 2006.245.08:19:41.62#ibcon#enter sib2, iclass 17, count 0 2006.245.08:19:41.62#ibcon#flushed, iclass 17, count 0 2006.245.08:19:41.62#ibcon#about to write, iclass 17, count 0 2006.245.08:19:41.62#ibcon#wrote, iclass 17, count 0 2006.245.08:19:41.62#ibcon#about to read 3, iclass 17, count 0 2006.245.08:19:41.65#ibcon#read 3, iclass 17, count 0 2006.245.08:19:41.65#ibcon#about to read 4, iclass 17, count 0 2006.245.08:19:41.65#ibcon#read 4, iclass 17, count 0 2006.245.08:19:41.65#ibcon#about to read 5, iclass 17, count 0 2006.245.08:19:41.65#ibcon#read 5, iclass 17, count 0 2006.245.08:19:41.65#ibcon#about to read 6, iclass 17, count 0 2006.245.08:19:41.65#ibcon#read 6, iclass 17, count 0 2006.245.08:19:41.65#ibcon#end of sib2, iclass 17, count 0 2006.245.08:19:41.65#ibcon#*after write, iclass 17, count 0 2006.245.08:19:41.65#ibcon#*before return 0, iclass 17, count 0 2006.245.08:19:41.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:19:41.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.245.08:19:41.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:19:41.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:19:41.65$vc4f8/valo=7,832.99 2006.245.08:19:41.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.245.08:19:41.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.245.08:19:41.65#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:41.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:19:41.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:19:41.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:19:41.65#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:19:41.65#ibcon#first serial, iclass 19, count 0 2006.245.08:19:41.65#ibcon#enter sib2, iclass 19, count 0 2006.245.08:19:41.65#ibcon#flushed, iclass 19, count 0 2006.245.08:19:41.65#ibcon#about to write, iclass 19, count 0 2006.245.08:19:41.65#ibcon#wrote, iclass 19, count 0 2006.245.08:19:41.65#ibcon#about to read 3, iclass 19, count 0 2006.245.08:19:41.67#ibcon#read 3, iclass 19, count 0 2006.245.08:19:41.67#ibcon#about to read 4, iclass 19, count 0 2006.245.08:19:41.67#ibcon#read 4, iclass 19, count 0 2006.245.08:19:41.67#ibcon#about to read 5, iclass 19, count 0 2006.245.08:19:41.67#ibcon#read 5, iclass 19, count 0 2006.245.08:19:41.67#ibcon#about to read 6, iclass 19, count 0 2006.245.08:19:41.67#ibcon#read 6, iclass 19, count 0 2006.245.08:19:41.67#ibcon#end of sib2, iclass 19, count 0 2006.245.08:19:41.67#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:19:41.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:19:41.67#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:19:41.67#ibcon#*before write, iclass 19, count 0 2006.245.08:19:41.67#ibcon#enter sib2, iclass 19, count 0 2006.245.08:19:41.67#ibcon#flushed, iclass 19, count 0 2006.245.08:19:41.67#ibcon#about to write, iclass 19, count 0 2006.245.08:19:41.67#ibcon#wrote, iclass 19, count 0 2006.245.08:19:41.67#ibcon#about to read 3, iclass 19, count 0 2006.245.08:19:41.71#ibcon#read 3, iclass 19, count 0 2006.245.08:19:41.71#ibcon#about to read 4, iclass 19, count 0 2006.245.08:19:41.71#ibcon#read 4, iclass 19, count 0 2006.245.08:19:41.71#ibcon#about to read 5, iclass 19, count 0 2006.245.08:19:41.71#ibcon#read 5, iclass 19, count 0 2006.245.08:19:41.71#ibcon#about to read 6, iclass 19, count 0 2006.245.08:19:41.71#ibcon#read 6, iclass 19, count 0 2006.245.08:19:41.71#ibcon#end of sib2, iclass 19, count 0 2006.245.08:19:41.71#ibcon#*after write, iclass 19, count 0 2006.245.08:19:41.71#ibcon#*before return 0, iclass 19, count 0 2006.245.08:19:41.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:19:41.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.245.08:19:41.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:19:41.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:19:41.71$vc4f8/va=7,7 2006.245.08:19:41.71#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.245.08:19:41.71#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.245.08:19:41.71#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:41.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:19:41.77#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:19:41.77#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:19:41.77#ibcon#enter wrdev, iclass 21, count 2 2006.245.08:19:41.77#ibcon#first serial, iclass 21, count 2 2006.245.08:19:41.77#ibcon#enter sib2, iclass 21, count 2 2006.245.08:19:41.77#ibcon#flushed, iclass 21, count 2 2006.245.08:19:41.77#ibcon#about to write, iclass 21, count 2 2006.245.08:19:41.77#ibcon#wrote, iclass 21, count 2 2006.245.08:19:41.77#ibcon#about to read 3, iclass 21, count 2 2006.245.08:19:41.79#ibcon#read 3, iclass 21, count 2 2006.245.08:19:41.79#ibcon#about to read 4, iclass 21, count 2 2006.245.08:19:41.79#ibcon#read 4, iclass 21, count 2 2006.245.08:19:41.79#ibcon#about to read 5, iclass 21, count 2 2006.245.08:19:41.79#ibcon#read 5, iclass 21, count 2 2006.245.08:19:41.79#ibcon#about to read 6, iclass 21, count 2 2006.245.08:19:41.79#ibcon#read 6, iclass 21, count 2 2006.245.08:19:41.79#ibcon#end of sib2, iclass 21, count 2 2006.245.08:19:41.79#ibcon#*mode == 0, iclass 21, count 2 2006.245.08:19:41.79#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.245.08:19:41.79#ibcon#[25=AT07-07\r\n] 2006.245.08:19:41.79#ibcon#*before write, iclass 21, count 2 2006.245.08:19:41.79#ibcon#enter sib2, iclass 21, count 2 2006.245.08:19:41.79#ibcon#flushed, iclass 21, count 2 2006.245.08:19:41.79#ibcon#about to write, iclass 21, count 2 2006.245.08:19:41.79#ibcon#wrote, iclass 21, count 2 2006.245.08:19:41.79#ibcon#about to read 3, iclass 21, count 2 2006.245.08:19:41.82#ibcon#read 3, iclass 21, count 2 2006.245.08:19:41.82#ibcon#about to read 4, iclass 21, count 2 2006.245.08:19:41.82#ibcon#read 4, iclass 21, count 2 2006.245.08:19:41.82#ibcon#about to read 5, iclass 21, count 2 2006.245.08:19:41.82#ibcon#read 5, iclass 21, count 2 2006.245.08:19:41.82#ibcon#about to read 6, iclass 21, count 2 2006.245.08:19:41.82#ibcon#read 6, iclass 21, count 2 2006.245.08:19:41.82#ibcon#end of sib2, iclass 21, count 2 2006.245.08:19:41.82#ibcon#*after write, iclass 21, count 2 2006.245.08:19:41.82#ibcon#*before return 0, iclass 21, count 2 2006.245.08:19:41.82#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:19:41.82#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.245.08:19:41.82#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.245.08:19:41.82#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:41.82#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:19:41.94#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:19:41.94#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:19:41.94#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:19:41.94#ibcon#first serial, iclass 21, count 0 2006.245.08:19:41.94#ibcon#enter sib2, iclass 21, count 0 2006.245.08:19:41.94#ibcon#flushed, iclass 21, count 0 2006.245.08:19:41.94#ibcon#about to write, iclass 21, count 0 2006.245.08:19:41.94#ibcon#wrote, iclass 21, count 0 2006.245.08:19:41.94#ibcon#about to read 3, iclass 21, count 0 2006.245.08:19:41.96#ibcon#read 3, iclass 21, count 0 2006.245.08:19:41.96#ibcon#about to read 4, iclass 21, count 0 2006.245.08:19:41.96#ibcon#read 4, iclass 21, count 0 2006.245.08:19:41.96#ibcon#about to read 5, iclass 21, count 0 2006.245.08:19:41.96#ibcon#read 5, iclass 21, count 0 2006.245.08:19:41.96#ibcon#about to read 6, iclass 21, count 0 2006.245.08:19:41.96#ibcon#read 6, iclass 21, count 0 2006.245.08:19:41.96#ibcon#end of sib2, iclass 21, count 0 2006.245.08:19:41.96#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:19:41.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:19:41.96#ibcon#[25=USB\r\n] 2006.245.08:19:41.96#ibcon#*before write, iclass 21, count 0 2006.245.08:19:41.96#ibcon#enter sib2, iclass 21, count 0 2006.245.08:19:41.96#ibcon#flushed, iclass 21, count 0 2006.245.08:19:41.96#ibcon#about to write, iclass 21, count 0 2006.245.08:19:41.96#ibcon#wrote, iclass 21, count 0 2006.245.08:19:41.96#ibcon#about to read 3, iclass 21, count 0 2006.245.08:19:41.99#ibcon#read 3, iclass 21, count 0 2006.245.08:19:41.99#ibcon#about to read 4, iclass 21, count 0 2006.245.08:19:41.99#ibcon#read 4, iclass 21, count 0 2006.245.08:19:41.99#ibcon#about to read 5, iclass 21, count 0 2006.245.08:19:41.99#ibcon#read 5, iclass 21, count 0 2006.245.08:19:41.99#ibcon#about to read 6, iclass 21, count 0 2006.245.08:19:41.99#ibcon#read 6, iclass 21, count 0 2006.245.08:19:41.99#ibcon#end of sib2, iclass 21, count 0 2006.245.08:19:41.99#ibcon#*after write, iclass 21, count 0 2006.245.08:19:41.99#ibcon#*before return 0, iclass 21, count 0 2006.245.08:19:41.99#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:19:41.99#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.245.08:19:41.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:19:41.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:19:41.99$vc4f8/valo=8,852.99 2006.245.08:19:41.99#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.245.08:19:41.99#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.245.08:19:41.99#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:41.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:19:41.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:19:41.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:19:41.99#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:19:41.99#ibcon#first serial, iclass 23, count 0 2006.245.08:19:41.99#ibcon#enter sib2, iclass 23, count 0 2006.245.08:19:41.99#ibcon#flushed, iclass 23, count 0 2006.245.08:19:41.99#ibcon#about to write, iclass 23, count 0 2006.245.08:19:41.99#ibcon#wrote, iclass 23, count 0 2006.245.08:19:41.99#ibcon#about to read 3, iclass 23, count 0 2006.245.08:19:42.01#ibcon#read 3, iclass 23, count 0 2006.245.08:19:42.01#ibcon#about to read 4, iclass 23, count 0 2006.245.08:19:42.01#ibcon#read 4, iclass 23, count 0 2006.245.08:19:42.01#ibcon#about to read 5, iclass 23, count 0 2006.245.08:19:42.01#ibcon#read 5, iclass 23, count 0 2006.245.08:19:42.01#ibcon#about to read 6, iclass 23, count 0 2006.245.08:19:42.01#ibcon#read 6, iclass 23, count 0 2006.245.08:19:42.01#ibcon#end of sib2, iclass 23, count 0 2006.245.08:19:42.01#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:19:42.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:19:42.01#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:19:42.01#ibcon#*before write, iclass 23, count 0 2006.245.08:19:42.01#ibcon#enter sib2, iclass 23, count 0 2006.245.08:19:42.01#ibcon#flushed, iclass 23, count 0 2006.245.08:19:42.01#ibcon#about to write, iclass 23, count 0 2006.245.08:19:42.01#ibcon#wrote, iclass 23, count 0 2006.245.08:19:42.01#ibcon#about to read 3, iclass 23, count 0 2006.245.08:19:42.05#ibcon#read 3, iclass 23, count 0 2006.245.08:19:42.05#ibcon#about to read 4, iclass 23, count 0 2006.245.08:19:42.05#ibcon#read 4, iclass 23, count 0 2006.245.08:19:42.05#ibcon#about to read 5, iclass 23, count 0 2006.245.08:19:42.05#ibcon#read 5, iclass 23, count 0 2006.245.08:19:42.05#ibcon#about to read 6, iclass 23, count 0 2006.245.08:19:42.05#ibcon#read 6, iclass 23, count 0 2006.245.08:19:42.05#ibcon#end of sib2, iclass 23, count 0 2006.245.08:19:42.05#ibcon#*after write, iclass 23, count 0 2006.245.08:19:42.05#ibcon#*before return 0, iclass 23, count 0 2006.245.08:19:42.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:19:42.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.245.08:19:42.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:19:42.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:19:42.05$vc4f8/va=8,8 2006.245.08:19:42.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.245.08:19:42.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.245.08:19:42.05#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:42.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:19:42.11#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:19:42.11#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:19:42.11#ibcon#enter wrdev, iclass 25, count 2 2006.245.08:19:42.11#ibcon#first serial, iclass 25, count 2 2006.245.08:19:42.11#ibcon#enter sib2, iclass 25, count 2 2006.245.08:19:42.11#ibcon#flushed, iclass 25, count 2 2006.245.08:19:42.11#ibcon#about to write, iclass 25, count 2 2006.245.08:19:42.11#ibcon#wrote, iclass 25, count 2 2006.245.08:19:42.11#ibcon#about to read 3, iclass 25, count 2 2006.245.08:19:42.13#ibcon#read 3, iclass 25, count 2 2006.245.08:19:42.13#ibcon#about to read 4, iclass 25, count 2 2006.245.08:19:42.13#ibcon#read 4, iclass 25, count 2 2006.245.08:19:42.13#ibcon#about to read 5, iclass 25, count 2 2006.245.08:19:42.13#ibcon#read 5, iclass 25, count 2 2006.245.08:19:42.13#ibcon#about to read 6, iclass 25, count 2 2006.245.08:19:42.13#ibcon#read 6, iclass 25, count 2 2006.245.08:19:42.13#ibcon#end of sib2, iclass 25, count 2 2006.245.08:19:42.13#ibcon#*mode == 0, iclass 25, count 2 2006.245.08:19:42.13#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.245.08:19:42.13#ibcon#[25=AT08-08\r\n] 2006.245.08:19:42.13#ibcon#*before write, iclass 25, count 2 2006.245.08:19:42.13#ibcon#enter sib2, iclass 25, count 2 2006.245.08:19:42.13#ibcon#flushed, iclass 25, count 2 2006.245.08:19:42.13#ibcon#about to write, iclass 25, count 2 2006.245.08:19:42.13#ibcon#wrote, iclass 25, count 2 2006.245.08:19:42.13#ibcon#about to read 3, iclass 25, count 2 2006.245.08:19:42.16#ibcon#read 3, iclass 25, count 2 2006.245.08:19:42.16#ibcon#about to read 4, iclass 25, count 2 2006.245.08:19:42.16#ibcon#read 4, iclass 25, count 2 2006.245.08:19:42.16#ibcon#about to read 5, iclass 25, count 2 2006.245.08:19:42.16#ibcon#read 5, iclass 25, count 2 2006.245.08:19:42.16#ibcon#about to read 6, iclass 25, count 2 2006.245.08:19:42.16#ibcon#read 6, iclass 25, count 2 2006.245.08:19:42.16#ibcon#end of sib2, iclass 25, count 2 2006.245.08:19:42.16#ibcon#*after write, iclass 25, count 2 2006.245.08:19:42.16#ibcon#*before return 0, iclass 25, count 2 2006.245.08:19:42.16#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:19:42.16#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.245.08:19:42.16#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.245.08:19:42.16#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:42.16#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:19:42.28#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:19:42.28#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:19:42.28#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:19:42.28#ibcon#first serial, iclass 25, count 0 2006.245.08:19:42.28#ibcon#enter sib2, iclass 25, count 0 2006.245.08:19:42.28#ibcon#flushed, iclass 25, count 0 2006.245.08:19:42.28#ibcon#about to write, iclass 25, count 0 2006.245.08:19:42.28#ibcon#wrote, iclass 25, count 0 2006.245.08:19:42.28#ibcon#about to read 3, iclass 25, count 0 2006.245.08:19:42.30#ibcon#read 3, iclass 25, count 0 2006.245.08:19:42.30#ibcon#about to read 4, iclass 25, count 0 2006.245.08:19:42.30#ibcon#read 4, iclass 25, count 0 2006.245.08:19:42.30#ibcon#about to read 5, iclass 25, count 0 2006.245.08:19:42.30#ibcon#read 5, iclass 25, count 0 2006.245.08:19:42.30#ibcon#about to read 6, iclass 25, count 0 2006.245.08:19:42.30#ibcon#read 6, iclass 25, count 0 2006.245.08:19:42.30#ibcon#end of sib2, iclass 25, count 0 2006.245.08:19:42.30#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:19:42.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:19:42.30#ibcon#[25=USB\r\n] 2006.245.08:19:42.30#ibcon#*before write, iclass 25, count 0 2006.245.08:19:42.30#ibcon#enter sib2, iclass 25, count 0 2006.245.08:19:42.30#ibcon#flushed, iclass 25, count 0 2006.245.08:19:42.30#ibcon#about to write, iclass 25, count 0 2006.245.08:19:42.30#ibcon#wrote, iclass 25, count 0 2006.245.08:19:42.30#ibcon#about to read 3, iclass 25, count 0 2006.245.08:19:42.33#ibcon#read 3, iclass 25, count 0 2006.245.08:19:42.33#ibcon#about to read 4, iclass 25, count 0 2006.245.08:19:42.33#ibcon#read 4, iclass 25, count 0 2006.245.08:19:42.33#ibcon#about to read 5, iclass 25, count 0 2006.245.08:19:42.33#ibcon#read 5, iclass 25, count 0 2006.245.08:19:42.33#ibcon#about to read 6, iclass 25, count 0 2006.245.08:19:42.33#ibcon#read 6, iclass 25, count 0 2006.245.08:19:42.33#ibcon#end of sib2, iclass 25, count 0 2006.245.08:19:42.33#ibcon#*after write, iclass 25, count 0 2006.245.08:19:42.33#ibcon#*before return 0, iclass 25, count 0 2006.245.08:19:42.33#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:19:42.33#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.245.08:19:42.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:19:42.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:19:42.33$vc4f8/vblo=1,632.99 2006.245.08:19:42.33#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.245.08:19:42.33#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.245.08:19:42.33#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:42.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:19:42.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:19:42.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:19:42.33#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:19:42.33#ibcon#first serial, iclass 27, count 0 2006.245.08:19:42.33#ibcon#enter sib2, iclass 27, count 0 2006.245.08:19:42.33#ibcon#flushed, iclass 27, count 0 2006.245.08:19:42.33#ibcon#about to write, iclass 27, count 0 2006.245.08:19:42.33#ibcon#wrote, iclass 27, count 0 2006.245.08:19:42.33#ibcon#about to read 3, iclass 27, count 0 2006.245.08:19:42.35#ibcon#read 3, iclass 27, count 0 2006.245.08:19:42.35#ibcon#about to read 4, iclass 27, count 0 2006.245.08:19:42.35#ibcon#read 4, iclass 27, count 0 2006.245.08:19:42.35#ibcon#about to read 5, iclass 27, count 0 2006.245.08:19:42.35#ibcon#read 5, iclass 27, count 0 2006.245.08:19:42.35#ibcon#about to read 6, iclass 27, count 0 2006.245.08:19:42.35#ibcon#read 6, iclass 27, count 0 2006.245.08:19:42.35#ibcon#end of sib2, iclass 27, count 0 2006.245.08:19:42.35#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:19:42.35#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:19:42.35#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:19:42.35#ibcon#*before write, iclass 27, count 0 2006.245.08:19:42.35#ibcon#enter sib2, iclass 27, count 0 2006.245.08:19:42.35#ibcon#flushed, iclass 27, count 0 2006.245.08:19:42.35#ibcon#about to write, iclass 27, count 0 2006.245.08:19:42.35#ibcon#wrote, iclass 27, count 0 2006.245.08:19:42.35#ibcon#about to read 3, iclass 27, count 0 2006.245.08:19:42.39#ibcon#read 3, iclass 27, count 0 2006.245.08:19:42.39#ibcon#about to read 4, iclass 27, count 0 2006.245.08:19:42.39#ibcon#read 4, iclass 27, count 0 2006.245.08:19:42.39#ibcon#about to read 5, iclass 27, count 0 2006.245.08:19:42.39#ibcon#read 5, iclass 27, count 0 2006.245.08:19:42.39#ibcon#about to read 6, iclass 27, count 0 2006.245.08:19:42.39#ibcon#read 6, iclass 27, count 0 2006.245.08:19:42.39#ibcon#end of sib2, iclass 27, count 0 2006.245.08:19:42.39#ibcon#*after write, iclass 27, count 0 2006.245.08:19:42.39#ibcon#*before return 0, iclass 27, count 0 2006.245.08:19:42.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:19:42.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.245.08:19:42.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:19:42.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:19:42.39$vc4f8/vb=1,4 2006.245.08:19:42.39#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.245.08:19:42.39#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.245.08:19:42.39#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:42.39#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:19:42.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:19:42.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:19:42.39#ibcon#enter wrdev, iclass 29, count 2 2006.245.08:19:42.39#ibcon#first serial, iclass 29, count 2 2006.245.08:19:42.39#ibcon#enter sib2, iclass 29, count 2 2006.245.08:19:42.39#ibcon#flushed, iclass 29, count 2 2006.245.08:19:42.39#ibcon#about to write, iclass 29, count 2 2006.245.08:19:42.39#ibcon#wrote, iclass 29, count 2 2006.245.08:19:42.39#ibcon#about to read 3, iclass 29, count 2 2006.245.08:19:42.41#ibcon#read 3, iclass 29, count 2 2006.245.08:19:42.41#ibcon#about to read 4, iclass 29, count 2 2006.245.08:19:42.41#ibcon#read 4, iclass 29, count 2 2006.245.08:19:42.41#ibcon#about to read 5, iclass 29, count 2 2006.245.08:19:42.41#ibcon#read 5, iclass 29, count 2 2006.245.08:19:42.41#ibcon#about to read 6, iclass 29, count 2 2006.245.08:19:42.41#ibcon#read 6, iclass 29, count 2 2006.245.08:19:42.41#ibcon#end of sib2, iclass 29, count 2 2006.245.08:19:42.41#ibcon#*mode == 0, iclass 29, count 2 2006.245.08:19:42.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.245.08:19:42.41#ibcon#[27=AT01-04\r\n] 2006.245.08:19:42.41#ibcon#*before write, iclass 29, count 2 2006.245.08:19:42.41#ibcon#enter sib2, iclass 29, count 2 2006.245.08:19:42.41#ibcon#flushed, iclass 29, count 2 2006.245.08:19:42.41#ibcon#about to write, iclass 29, count 2 2006.245.08:19:42.41#ibcon#wrote, iclass 29, count 2 2006.245.08:19:42.41#ibcon#about to read 3, iclass 29, count 2 2006.245.08:19:42.44#ibcon#read 3, iclass 29, count 2 2006.245.08:19:42.44#ibcon#about to read 4, iclass 29, count 2 2006.245.08:19:42.44#ibcon#read 4, iclass 29, count 2 2006.245.08:19:42.44#ibcon#about to read 5, iclass 29, count 2 2006.245.08:19:42.44#ibcon#read 5, iclass 29, count 2 2006.245.08:19:42.44#ibcon#about to read 6, iclass 29, count 2 2006.245.08:19:42.44#ibcon#read 6, iclass 29, count 2 2006.245.08:19:42.44#ibcon#end of sib2, iclass 29, count 2 2006.245.08:19:42.44#ibcon#*after write, iclass 29, count 2 2006.245.08:19:42.44#ibcon#*before return 0, iclass 29, count 2 2006.245.08:19:42.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:19:42.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.245.08:19:42.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.245.08:19:42.44#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:42.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:19:42.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:19:42.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:19:42.56#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:19:42.56#ibcon#first serial, iclass 29, count 0 2006.245.08:19:42.56#ibcon#enter sib2, iclass 29, count 0 2006.245.08:19:42.56#ibcon#flushed, iclass 29, count 0 2006.245.08:19:42.56#ibcon#about to write, iclass 29, count 0 2006.245.08:19:42.56#ibcon#wrote, iclass 29, count 0 2006.245.08:19:42.56#ibcon#about to read 3, iclass 29, count 0 2006.245.08:19:42.58#ibcon#read 3, iclass 29, count 0 2006.245.08:19:42.58#ibcon#about to read 4, iclass 29, count 0 2006.245.08:19:42.58#ibcon#read 4, iclass 29, count 0 2006.245.08:19:42.58#ibcon#about to read 5, iclass 29, count 0 2006.245.08:19:42.58#ibcon#read 5, iclass 29, count 0 2006.245.08:19:42.58#ibcon#about to read 6, iclass 29, count 0 2006.245.08:19:42.58#ibcon#read 6, iclass 29, count 0 2006.245.08:19:42.58#ibcon#end of sib2, iclass 29, count 0 2006.245.08:19:42.58#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:19:42.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:19:42.58#ibcon#[27=USB\r\n] 2006.245.08:19:42.58#ibcon#*before write, iclass 29, count 0 2006.245.08:19:42.58#ibcon#enter sib2, iclass 29, count 0 2006.245.08:19:42.58#ibcon#flushed, iclass 29, count 0 2006.245.08:19:42.58#ibcon#about to write, iclass 29, count 0 2006.245.08:19:42.58#ibcon#wrote, iclass 29, count 0 2006.245.08:19:42.58#ibcon#about to read 3, iclass 29, count 0 2006.245.08:19:42.61#ibcon#read 3, iclass 29, count 0 2006.245.08:19:42.61#ibcon#about to read 4, iclass 29, count 0 2006.245.08:19:42.61#ibcon#read 4, iclass 29, count 0 2006.245.08:19:42.61#ibcon#about to read 5, iclass 29, count 0 2006.245.08:19:42.61#ibcon#read 5, iclass 29, count 0 2006.245.08:19:42.61#ibcon#about to read 6, iclass 29, count 0 2006.245.08:19:42.61#ibcon#read 6, iclass 29, count 0 2006.245.08:19:42.61#ibcon#end of sib2, iclass 29, count 0 2006.245.08:19:42.61#ibcon#*after write, iclass 29, count 0 2006.245.08:19:42.61#ibcon#*before return 0, iclass 29, count 0 2006.245.08:19:42.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:19:42.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.245.08:19:42.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:19:42.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:19:42.61$vc4f8/vblo=2,640.99 2006.245.08:19:42.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.245.08:19:42.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.245.08:19:42.61#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:42.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:42.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:42.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:42.61#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:19:42.61#ibcon#first serial, iclass 31, count 0 2006.245.08:19:42.61#ibcon#enter sib2, iclass 31, count 0 2006.245.08:19:42.61#ibcon#flushed, iclass 31, count 0 2006.245.08:19:42.61#ibcon#about to write, iclass 31, count 0 2006.245.08:19:42.61#ibcon#wrote, iclass 31, count 0 2006.245.08:19:42.61#ibcon#about to read 3, iclass 31, count 0 2006.245.08:19:42.63#ibcon#read 3, iclass 31, count 0 2006.245.08:19:42.63#ibcon#about to read 4, iclass 31, count 0 2006.245.08:19:42.63#ibcon#read 4, iclass 31, count 0 2006.245.08:19:42.63#ibcon#about to read 5, iclass 31, count 0 2006.245.08:19:42.63#ibcon#read 5, iclass 31, count 0 2006.245.08:19:42.63#ibcon#about to read 6, iclass 31, count 0 2006.245.08:19:42.63#ibcon#read 6, iclass 31, count 0 2006.245.08:19:42.63#ibcon#end of sib2, iclass 31, count 0 2006.245.08:19:42.63#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:19:42.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:19:42.63#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:19:42.63#ibcon#*before write, iclass 31, count 0 2006.245.08:19:42.63#ibcon#enter sib2, iclass 31, count 0 2006.245.08:19:42.63#ibcon#flushed, iclass 31, count 0 2006.245.08:19:42.63#ibcon#about to write, iclass 31, count 0 2006.245.08:19:42.63#ibcon#wrote, iclass 31, count 0 2006.245.08:19:42.63#ibcon#about to read 3, iclass 31, count 0 2006.245.08:19:42.67#ibcon#read 3, iclass 31, count 0 2006.245.08:19:42.67#ibcon#about to read 4, iclass 31, count 0 2006.245.08:19:42.67#ibcon#read 4, iclass 31, count 0 2006.245.08:19:42.67#ibcon#about to read 5, iclass 31, count 0 2006.245.08:19:42.67#ibcon#read 5, iclass 31, count 0 2006.245.08:19:42.67#ibcon#about to read 6, iclass 31, count 0 2006.245.08:19:42.67#ibcon#read 6, iclass 31, count 0 2006.245.08:19:42.67#ibcon#end of sib2, iclass 31, count 0 2006.245.08:19:42.67#ibcon#*after write, iclass 31, count 0 2006.245.08:19:42.67#ibcon#*before return 0, iclass 31, count 0 2006.245.08:19:42.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:42.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.245.08:19:42.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:19:42.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:19:42.67$vc4f8/vb=2,4 2006.245.08:19:42.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.245.08:19:42.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.245.08:19:42.67#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:42.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:42.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:42.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:42.73#ibcon#enter wrdev, iclass 33, count 2 2006.245.08:19:42.73#ibcon#first serial, iclass 33, count 2 2006.245.08:19:42.73#ibcon#enter sib2, iclass 33, count 2 2006.245.08:19:42.73#ibcon#flushed, iclass 33, count 2 2006.245.08:19:42.73#ibcon#about to write, iclass 33, count 2 2006.245.08:19:42.73#ibcon#wrote, iclass 33, count 2 2006.245.08:19:42.73#ibcon#about to read 3, iclass 33, count 2 2006.245.08:19:42.75#ibcon#read 3, iclass 33, count 2 2006.245.08:19:42.75#ibcon#about to read 4, iclass 33, count 2 2006.245.08:19:42.75#ibcon#read 4, iclass 33, count 2 2006.245.08:19:42.75#ibcon#about to read 5, iclass 33, count 2 2006.245.08:19:42.75#ibcon#read 5, iclass 33, count 2 2006.245.08:19:42.75#ibcon#about to read 6, iclass 33, count 2 2006.245.08:19:42.75#ibcon#read 6, iclass 33, count 2 2006.245.08:19:42.75#ibcon#end of sib2, iclass 33, count 2 2006.245.08:19:42.75#ibcon#*mode == 0, iclass 33, count 2 2006.245.08:19:42.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.245.08:19:42.75#ibcon#[27=AT02-04\r\n] 2006.245.08:19:42.75#ibcon#*before write, iclass 33, count 2 2006.245.08:19:42.75#ibcon#enter sib2, iclass 33, count 2 2006.245.08:19:42.75#ibcon#flushed, iclass 33, count 2 2006.245.08:19:42.75#ibcon#about to write, iclass 33, count 2 2006.245.08:19:42.75#ibcon#wrote, iclass 33, count 2 2006.245.08:19:42.75#ibcon#about to read 3, iclass 33, count 2 2006.245.08:19:42.78#ibcon#read 3, iclass 33, count 2 2006.245.08:19:42.78#ibcon#about to read 4, iclass 33, count 2 2006.245.08:19:42.78#ibcon#read 4, iclass 33, count 2 2006.245.08:19:42.78#ibcon#about to read 5, iclass 33, count 2 2006.245.08:19:42.78#ibcon#read 5, iclass 33, count 2 2006.245.08:19:42.78#ibcon#about to read 6, iclass 33, count 2 2006.245.08:19:42.78#ibcon#read 6, iclass 33, count 2 2006.245.08:19:42.78#ibcon#end of sib2, iclass 33, count 2 2006.245.08:19:42.78#ibcon#*after write, iclass 33, count 2 2006.245.08:19:42.78#ibcon#*before return 0, iclass 33, count 2 2006.245.08:19:42.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:42.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.245.08:19:42.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.245.08:19:42.78#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:42.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:42.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:42.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:42.90#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:19:42.90#ibcon#first serial, iclass 33, count 0 2006.245.08:19:42.90#ibcon#enter sib2, iclass 33, count 0 2006.245.08:19:42.90#ibcon#flushed, iclass 33, count 0 2006.245.08:19:42.90#ibcon#about to write, iclass 33, count 0 2006.245.08:19:42.90#ibcon#wrote, iclass 33, count 0 2006.245.08:19:42.90#ibcon#about to read 3, iclass 33, count 0 2006.245.08:19:42.92#ibcon#read 3, iclass 33, count 0 2006.245.08:19:42.92#ibcon#about to read 4, iclass 33, count 0 2006.245.08:19:42.92#ibcon#read 4, iclass 33, count 0 2006.245.08:19:42.92#ibcon#about to read 5, iclass 33, count 0 2006.245.08:19:42.92#ibcon#read 5, iclass 33, count 0 2006.245.08:19:42.92#ibcon#about to read 6, iclass 33, count 0 2006.245.08:19:42.92#ibcon#read 6, iclass 33, count 0 2006.245.08:19:42.92#ibcon#end of sib2, iclass 33, count 0 2006.245.08:19:42.92#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:19:42.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:19:42.92#ibcon#[27=USB\r\n] 2006.245.08:19:42.92#ibcon#*before write, iclass 33, count 0 2006.245.08:19:42.92#ibcon#enter sib2, iclass 33, count 0 2006.245.08:19:42.92#ibcon#flushed, iclass 33, count 0 2006.245.08:19:42.92#ibcon#about to write, iclass 33, count 0 2006.245.08:19:42.92#ibcon#wrote, iclass 33, count 0 2006.245.08:19:42.92#ibcon#about to read 3, iclass 33, count 0 2006.245.08:19:42.95#ibcon#read 3, iclass 33, count 0 2006.245.08:19:42.95#ibcon#about to read 4, iclass 33, count 0 2006.245.08:19:42.95#ibcon#read 4, iclass 33, count 0 2006.245.08:19:42.95#ibcon#about to read 5, iclass 33, count 0 2006.245.08:19:42.95#ibcon#read 5, iclass 33, count 0 2006.245.08:19:42.95#ibcon#about to read 6, iclass 33, count 0 2006.245.08:19:42.95#ibcon#read 6, iclass 33, count 0 2006.245.08:19:42.95#ibcon#end of sib2, iclass 33, count 0 2006.245.08:19:42.95#ibcon#*after write, iclass 33, count 0 2006.245.08:19:42.95#ibcon#*before return 0, iclass 33, count 0 2006.245.08:19:42.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:42.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.245.08:19:42.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:19:42.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:19:42.95$vc4f8/vblo=3,656.99 2006.245.08:19:42.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.08:19:42.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.08:19:42.95#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:42.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:42.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:42.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:42.95#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:19:42.95#ibcon#first serial, iclass 35, count 0 2006.245.08:19:42.95#ibcon#enter sib2, iclass 35, count 0 2006.245.08:19:42.95#ibcon#flushed, iclass 35, count 0 2006.245.08:19:42.95#ibcon#about to write, iclass 35, count 0 2006.245.08:19:42.95#ibcon#wrote, iclass 35, count 0 2006.245.08:19:42.95#ibcon#about to read 3, iclass 35, count 0 2006.245.08:19:42.97#ibcon#read 3, iclass 35, count 0 2006.245.08:19:42.97#ibcon#about to read 4, iclass 35, count 0 2006.245.08:19:42.97#ibcon#read 4, iclass 35, count 0 2006.245.08:19:42.97#ibcon#about to read 5, iclass 35, count 0 2006.245.08:19:42.97#ibcon#read 5, iclass 35, count 0 2006.245.08:19:42.97#ibcon#about to read 6, iclass 35, count 0 2006.245.08:19:42.97#ibcon#read 6, iclass 35, count 0 2006.245.08:19:42.97#ibcon#end of sib2, iclass 35, count 0 2006.245.08:19:42.97#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:19:42.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:19:42.97#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:19:42.97#ibcon#*before write, iclass 35, count 0 2006.245.08:19:42.97#ibcon#enter sib2, iclass 35, count 0 2006.245.08:19:42.97#ibcon#flushed, iclass 35, count 0 2006.245.08:19:42.97#ibcon#about to write, iclass 35, count 0 2006.245.08:19:42.97#ibcon#wrote, iclass 35, count 0 2006.245.08:19:42.97#ibcon#about to read 3, iclass 35, count 0 2006.245.08:19:43.01#ibcon#read 3, iclass 35, count 0 2006.245.08:19:43.01#ibcon#about to read 4, iclass 35, count 0 2006.245.08:19:43.01#ibcon#read 4, iclass 35, count 0 2006.245.08:19:43.01#ibcon#about to read 5, iclass 35, count 0 2006.245.08:19:43.01#ibcon#read 5, iclass 35, count 0 2006.245.08:19:43.01#ibcon#about to read 6, iclass 35, count 0 2006.245.08:19:43.01#ibcon#read 6, iclass 35, count 0 2006.245.08:19:43.01#ibcon#end of sib2, iclass 35, count 0 2006.245.08:19:43.01#ibcon#*after write, iclass 35, count 0 2006.245.08:19:43.01#ibcon#*before return 0, iclass 35, count 0 2006.245.08:19:43.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:43.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:19:43.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:19:43.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:19:43.01$vc4f8/vb=3,4 2006.245.08:19:43.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.245.08:19:43.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.245.08:19:43.01#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:43.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:43.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:43.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:43.07#ibcon#enter wrdev, iclass 37, count 2 2006.245.08:19:43.07#ibcon#first serial, iclass 37, count 2 2006.245.08:19:43.07#ibcon#enter sib2, iclass 37, count 2 2006.245.08:19:43.07#ibcon#flushed, iclass 37, count 2 2006.245.08:19:43.07#ibcon#about to write, iclass 37, count 2 2006.245.08:19:43.07#ibcon#wrote, iclass 37, count 2 2006.245.08:19:43.07#ibcon#about to read 3, iclass 37, count 2 2006.245.08:19:43.09#ibcon#read 3, iclass 37, count 2 2006.245.08:19:43.09#ibcon#about to read 4, iclass 37, count 2 2006.245.08:19:43.09#ibcon#read 4, iclass 37, count 2 2006.245.08:19:43.09#ibcon#about to read 5, iclass 37, count 2 2006.245.08:19:43.09#ibcon#read 5, iclass 37, count 2 2006.245.08:19:43.09#ibcon#about to read 6, iclass 37, count 2 2006.245.08:19:43.09#ibcon#read 6, iclass 37, count 2 2006.245.08:19:43.09#ibcon#end of sib2, iclass 37, count 2 2006.245.08:19:43.09#ibcon#*mode == 0, iclass 37, count 2 2006.245.08:19:43.09#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.245.08:19:43.09#ibcon#[27=AT03-04\r\n] 2006.245.08:19:43.09#ibcon#*before write, iclass 37, count 2 2006.245.08:19:43.09#ibcon#enter sib2, iclass 37, count 2 2006.245.08:19:43.09#ibcon#flushed, iclass 37, count 2 2006.245.08:19:43.09#ibcon#about to write, iclass 37, count 2 2006.245.08:19:43.09#ibcon#wrote, iclass 37, count 2 2006.245.08:19:43.09#ibcon#about to read 3, iclass 37, count 2 2006.245.08:19:43.12#ibcon#read 3, iclass 37, count 2 2006.245.08:19:43.12#ibcon#about to read 4, iclass 37, count 2 2006.245.08:19:43.12#ibcon#read 4, iclass 37, count 2 2006.245.08:19:43.12#ibcon#about to read 5, iclass 37, count 2 2006.245.08:19:43.12#ibcon#read 5, iclass 37, count 2 2006.245.08:19:43.12#ibcon#about to read 6, iclass 37, count 2 2006.245.08:19:43.12#ibcon#read 6, iclass 37, count 2 2006.245.08:19:43.12#ibcon#end of sib2, iclass 37, count 2 2006.245.08:19:43.12#ibcon#*after write, iclass 37, count 2 2006.245.08:19:43.12#ibcon#*before return 0, iclass 37, count 2 2006.245.08:19:43.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:43.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.245.08:19:43.12#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.245.08:19:43.12#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:43.12#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:43.24#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:43.24#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:43.24#ibcon#enter wrdev, iclass 37, count 0 2006.245.08:19:43.24#ibcon#first serial, iclass 37, count 0 2006.245.08:19:43.24#ibcon#enter sib2, iclass 37, count 0 2006.245.08:19:43.24#ibcon#flushed, iclass 37, count 0 2006.245.08:19:43.24#ibcon#about to write, iclass 37, count 0 2006.245.08:19:43.24#ibcon#wrote, iclass 37, count 0 2006.245.08:19:43.24#ibcon#about to read 3, iclass 37, count 0 2006.245.08:19:43.26#ibcon#read 3, iclass 37, count 0 2006.245.08:19:43.26#ibcon#about to read 4, iclass 37, count 0 2006.245.08:19:43.26#ibcon#read 4, iclass 37, count 0 2006.245.08:19:43.26#ibcon#about to read 5, iclass 37, count 0 2006.245.08:19:43.26#ibcon#read 5, iclass 37, count 0 2006.245.08:19:43.26#ibcon#about to read 6, iclass 37, count 0 2006.245.08:19:43.26#ibcon#read 6, iclass 37, count 0 2006.245.08:19:43.26#ibcon#end of sib2, iclass 37, count 0 2006.245.08:19:43.26#ibcon#*mode == 0, iclass 37, count 0 2006.245.08:19:43.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.245.08:19:43.26#ibcon#[27=USB\r\n] 2006.245.08:19:43.26#ibcon#*before write, iclass 37, count 0 2006.245.08:19:43.26#ibcon#enter sib2, iclass 37, count 0 2006.245.08:19:43.26#ibcon#flushed, iclass 37, count 0 2006.245.08:19:43.26#ibcon#about to write, iclass 37, count 0 2006.245.08:19:43.26#ibcon#wrote, iclass 37, count 0 2006.245.08:19:43.26#ibcon#about to read 3, iclass 37, count 0 2006.245.08:19:43.29#ibcon#read 3, iclass 37, count 0 2006.245.08:19:43.29#ibcon#about to read 4, iclass 37, count 0 2006.245.08:19:43.29#ibcon#read 4, iclass 37, count 0 2006.245.08:19:43.29#ibcon#about to read 5, iclass 37, count 0 2006.245.08:19:43.29#ibcon#read 5, iclass 37, count 0 2006.245.08:19:43.29#ibcon#about to read 6, iclass 37, count 0 2006.245.08:19:43.29#ibcon#read 6, iclass 37, count 0 2006.245.08:19:43.29#ibcon#end of sib2, iclass 37, count 0 2006.245.08:19:43.29#ibcon#*after write, iclass 37, count 0 2006.245.08:19:43.29#ibcon#*before return 0, iclass 37, count 0 2006.245.08:19:43.29#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:43.29#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.245.08:19:43.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.245.08:19:43.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.245.08:19:43.29$vc4f8/vblo=4,712.99 2006.245.08:19:43.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.245.08:19:43.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.245.08:19:43.29#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:43.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:43.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:43.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:43.29#ibcon#enter wrdev, iclass 39, count 0 2006.245.08:19:43.29#ibcon#first serial, iclass 39, count 0 2006.245.08:19:43.29#ibcon#enter sib2, iclass 39, count 0 2006.245.08:19:43.29#ibcon#flushed, iclass 39, count 0 2006.245.08:19:43.29#ibcon#about to write, iclass 39, count 0 2006.245.08:19:43.29#ibcon#wrote, iclass 39, count 0 2006.245.08:19:43.29#ibcon#about to read 3, iclass 39, count 0 2006.245.08:19:43.31#ibcon#read 3, iclass 39, count 0 2006.245.08:19:43.31#ibcon#about to read 4, iclass 39, count 0 2006.245.08:19:43.31#ibcon#read 4, iclass 39, count 0 2006.245.08:19:43.31#ibcon#about to read 5, iclass 39, count 0 2006.245.08:19:43.31#ibcon#read 5, iclass 39, count 0 2006.245.08:19:43.31#ibcon#about to read 6, iclass 39, count 0 2006.245.08:19:43.31#ibcon#read 6, iclass 39, count 0 2006.245.08:19:43.31#ibcon#end of sib2, iclass 39, count 0 2006.245.08:19:43.31#ibcon#*mode == 0, iclass 39, count 0 2006.245.08:19:43.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.245.08:19:43.31#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:19:43.31#ibcon#*before write, iclass 39, count 0 2006.245.08:19:43.31#ibcon#enter sib2, iclass 39, count 0 2006.245.08:19:43.31#ibcon#flushed, iclass 39, count 0 2006.245.08:19:43.31#ibcon#about to write, iclass 39, count 0 2006.245.08:19:43.31#ibcon#wrote, iclass 39, count 0 2006.245.08:19:43.31#ibcon#about to read 3, iclass 39, count 0 2006.245.08:19:43.35#ibcon#read 3, iclass 39, count 0 2006.245.08:19:43.35#ibcon#about to read 4, iclass 39, count 0 2006.245.08:19:43.35#ibcon#read 4, iclass 39, count 0 2006.245.08:19:43.35#ibcon#about to read 5, iclass 39, count 0 2006.245.08:19:43.35#ibcon#read 5, iclass 39, count 0 2006.245.08:19:43.35#ibcon#about to read 6, iclass 39, count 0 2006.245.08:19:43.35#ibcon#read 6, iclass 39, count 0 2006.245.08:19:43.35#ibcon#end of sib2, iclass 39, count 0 2006.245.08:19:43.35#ibcon#*after write, iclass 39, count 0 2006.245.08:19:43.35#ibcon#*before return 0, iclass 39, count 0 2006.245.08:19:43.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:43.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.245.08:19:43.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.245.08:19:43.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.245.08:19:43.35$vc4f8/vb=4,4 2006.245.08:19:43.35#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.245.08:19:43.35#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.245.08:19:43.35#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:43.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:43.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:43.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:43.41#ibcon#enter wrdev, iclass 3, count 2 2006.245.08:19:43.41#ibcon#first serial, iclass 3, count 2 2006.245.08:19:43.41#ibcon#enter sib2, iclass 3, count 2 2006.245.08:19:43.41#ibcon#flushed, iclass 3, count 2 2006.245.08:19:43.41#ibcon#about to write, iclass 3, count 2 2006.245.08:19:43.41#ibcon#wrote, iclass 3, count 2 2006.245.08:19:43.41#ibcon#about to read 3, iclass 3, count 2 2006.245.08:19:43.43#ibcon#read 3, iclass 3, count 2 2006.245.08:19:43.43#ibcon#about to read 4, iclass 3, count 2 2006.245.08:19:43.43#ibcon#read 4, iclass 3, count 2 2006.245.08:19:43.43#ibcon#about to read 5, iclass 3, count 2 2006.245.08:19:43.43#ibcon#read 5, iclass 3, count 2 2006.245.08:19:43.43#ibcon#about to read 6, iclass 3, count 2 2006.245.08:19:43.43#ibcon#read 6, iclass 3, count 2 2006.245.08:19:43.43#ibcon#end of sib2, iclass 3, count 2 2006.245.08:19:43.43#ibcon#*mode == 0, iclass 3, count 2 2006.245.08:19:43.43#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.245.08:19:43.43#ibcon#[27=AT04-04\r\n] 2006.245.08:19:43.43#ibcon#*before write, iclass 3, count 2 2006.245.08:19:43.43#ibcon#enter sib2, iclass 3, count 2 2006.245.08:19:43.43#ibcon#flushed, iclass 3, count 2 2006.245.08:19:43.43#ibcon#about to write, iclass 3, count 2 2006.245.08:19:43.43#ibcon#wrote, iclass 3, count 2 2006.245.08:19:43.43#ibcon#about to read 3, iclass 3, count 2 2006.245.08:19:43.46#ibcon#read 3, iclass 3, count 2 2006.245.08:19:43.46#ibcon#about to read 4, iclass 3, count 2 2006.245.08:19:43.46#ibcon#read 4, iclass 3, count 2 2006.245.08:19:43.46#ibcon#about to read 5, iclass 3, count 2 2006.245.08:19:43.46#ibcon#read 5, iclass 3, count 2 2006.245.08:19:43.46#ibcon#about to read 6, iclass 3, count 2 2006.245.08:19:43.46#ibcon#read 6, iclass 3, count 2 2006.245.08:19:43.46#ibcon#end of sib2, iclass 3, count 2 2006.245.08:19:43.46#ibcon#*after write, iclass 3, count 2 2006.245.08:19:43.46#ibcon#*before return 0, iclass 3, count 2 2006.245.08:19:43.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:43.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.245.08:19:43.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.245.08:19:43.46#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:43.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:43.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:43.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:43.58#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:19:43.58#ibcon#first serial, iclass 3, count 0 2006.245.08:19:43.58#ibcon#enter sib2, iclass 3, count 0 2006.245.08:19:43.58#ibcon#flushed, iclass 3, count 0 2006.245.08:19:43.58#ibcon#about to write, iclass 3, count 0 2006.245.08:19:43.58#ibcon#wrote, iclass 3, count 0 2006.245.08:19:43.58#ibcon#about to read 3, iclass 3, count 0 2006.245.08:19:43.60#ibcon#read 3, iclass 3, count 0 2006.245.08:19:43.60#ibcon#about to read 4, iclass 3, count 0 2006.245.08:19:43.60#ibcon#read 4, iclass 3, count 0 2006.245.08:19:43.60#ibcon#about to read 5, iclass 3, count 0 2006.245.08:19:43.60#ibcon#read 5, iclass 3, count 0 2006.245.08:19:43.60#ibcon#about to read 6, iclass 3, count 0 2006.245.08:19:43.60#ibcon#read 6, iclass 3, count 0 2006.245.08:19:43.60#ibcon#end of sib2, iclass 3, count 0 2006.245.08:19:43.60#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:19:43.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:19:43.60#ibcon#[27=USB\r\n] 2006.245.08:19:43.60#ibcon#*before write, iclass 3, count 0 2006.245.08:19:43.60#ibcon#enter sib2, iclass 3, count 0 2006.245.08:19:43.60#ibcon#flushed, iclass 3, count 0 2006.245.08:19:43.60#ibcon#about to write, iclass 3, count 0 2006.245.08:19:43.60#ibcon#wrote, iclass 3, count 0 2006.245.08:19:43.60#ibcon#about to read 3, iclass 3, count 0 2006.245.08:19:43.63#ibcon#read 3, iclass 3, count 0 2006.245.08:19:43.63#ibcon#about to read 4, iclass 3, count 0 2006.245.08:19:43.63#ibcon#read 4, iclass 3, count 0 2006.245.08:19:43.63#ibcon#about to read 5, iclass 3, count 0 2006.245.08:19:43.63#ibcon#read 5, iclass 3, count 0 2006.245.08:19:43.63#ibcon#about to read 6, iclass 3, count 0 2006.245.08:19:43.63#ibcon#read 6, iclass 3, count 0 2006.245.08:19:43.63#ibcon#end of sib2, iclass 3, count 0 2006.245.08:19:43.63#ibcon#*after write, iclass 3, count 0 2006.245.08:19:43.63#ibcon#*before return 0, iclass 3, count 0 2006.245.08:19:43.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:43.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.245.08:19:43.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:19:43.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:19:43.63$vc4f8/vblo=5,744.99 2006.245.08:19:43.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.245.08:19:43.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.245.08:19:43.63#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:43.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:43.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:43.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:43.63#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:19:43.63#ibcon#first serial, iclass 5, count 0 2006.245.08:19:43.63#ibcon#enter sib2, iclass 5, count 0 2006.245.08:19:43.63#ibcon#flushed, iclass 5, count 0 2006.245.08:19:43.63#ibcon#about to write, iclass 5, count 0 2006.245.08:19:43.63#ibcon#wrote, iclass 5, count 0 2006.245.08:19:43.63#ibcon#about to read 3, iclass 5, count 0 2006.245.08:19:43.65#ibcon#read 3, iclass 5, count 0 2006.245.08:19:43.65#ibcon#about to read 4, iclass 5, count 0 2006.245.08:19:43.65#ibcon#read 4, iclass 5, count 0 2006.245.08:19:43.65#ibcon#about to read 5, iclass 5, count 0 2006.245.08:19:43.65#ibcon#read 5, iclass 5, count 0 2006.245.08:19:43.65#ibcon#about to read 6, iclass 5, count 0 2006.245.08:19:43.65#ibcon#read 6, iclass 5, count 0 2006.245.08:19:43.65#ibcon#end of sib2, iclass 5, count 0 2006.245.08:19:43.65#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:19:43.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:19:43.65#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:19:43.65#ibcon#*before write, iclass 5, count 0 2006.245.08:19:43.65#ibcon#enter sib2, iclass 5, count 0 2006.245.08:19:43.65#ibcon#flushed, iclass 5, count 0 2006.245.08:19:43.65#ibcon#about to write, iclass 5, count 0 2006.245.08:19:43.65#ibcon#wrote, iclass 5, count 0 2006.245.08:19:43.65#ibcon#about to read 3, iclass 5, count 0 2006.245.08:19:43.69#ibcon#read 3, iclass 5, count 0 2006.245.08:19:43.69#ibcon#about to read 4, iclass 5, count 0 2006.245.08:19:43.69#ibcon#read 4, iclass 5, count 0 2006.245.08:19:43.69#ibcon#about to read 5, iclass 5, count 0 2006.245.08:19:43.69#ibcon#read 5, iclass 5, count 0 2006.245.08:19:43.69#ibcon#about to read 6, iclass 5, count 0 2006.245.08:19:43.69#ibcon#read 6, iclass 5, count 0 2006.245.08:19:43.69#ibcon#end of sib2, iclass 5, count 0 2006.245.08:19:43.69#ibcon#*after write, iclass 5, count 0 2006.245.08:19:43.69#ibcon#*before return 0, iclass 5, count 0 2006.245.08:19:43.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:43.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.245.08:19:43.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:19:43.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:19:43.69$vc4f8/vb=5,3 2006.245.08:19:43.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.245.08:19:43.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.245.08:19:43.69#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:43.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:43.75#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:43.75#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:43.75#ibcon#enter wrdev, iclass 7, count 2 2006.245.08:19:43.75#ibcon#first serial, iclass 7, count 2 2006.245.08:19:43.75#ibcon#enter sib2, iclass 7, count 2 2006.245.08:19:43.75#ibcon#flushed, iclass 7, count 2 2006.245.08:19:43.75#ibcon#about to write, iclass 7, count 2 2006.245.08:19:43.75#ibcon#wrote, iclass 7, count 2 2006.245.08:19:43.75#ibcon#about to read 3, iclass 7, count 2 2006.245.08:19:43.77#ibcon#read 3, iclass 7, count 2 2006.245.08:19:43.77#ibcon#about to read 4, iclass 7, count 2 2006.245.08:19:43.77#ibcon#read 4, iclass 7, count 2 2006.245.08:19:43.77#ibcon#about to read 5, iclass 7, count 2 2006.245.08:19:43.77#ibcon#read 5, iclass 7, count 2 2006.245.08:19:43.77#ibcon#about to read 6, iclass 7, count 2 2006.245.08:19:43.77#ibcon#read 6, iclass 7, count 2 2006.245.08:19:43.77#ibcon#end of sib2, iclass 7, count 2 2006.245.08:19:43.77#ibcon#*mode == 0, iclass 7, count 2 2006.245.08:19:43.77#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.245.08:19:43.77#ibcon#[27=AT05-03\r\n] 2006.245.08:19:43.77#ibcon#*before write, iclass 7, count 2 2006.245.08:19:43.77#ibcon#enter sib2, iclass 7, count 2 2006.245.08:19:43.77#ibcon#flushed, iclass 7, count 2 2006.245.08:19:43.77#ibcon#about to write, iclass 7, count 2 2006.245.08:19:43.77#ibcon#wrote, iclass 7, count 2 2006.245.08:19:43.77#ibcon#about to read 3, iclass 7, count 2 2006.245.08:19:43.80#ibcon#read 3, iclass 7, count 2 2006.245.08:19:43.80#ibcon#about to read 4, iclass 7, count 2 2006.245.08:19:43.80#ibcon#read 4, iclass 7, count 2 2006.245.08:19:43.80#ibcon#about to read 5, iclass 7, count 2 2006.245.08:19:43.80#ibcon#read 5, iclass 7, count 2 2006.245.08:19:43.80#ibcon#about to read 6, iclass 7, count 2 2006.245.08:19:43.80#ibcon#read 6, iclass 7, count 2 2006.245.08:19:43.80#ibcon#end of sib2, iclass 7, count 2 2006.245.08:19:43.80#ibcon#*after write, iclass 7, count 2 2006.245.08:19:43.80#ibcon#*before return 0, iclass 7, count 2 2006.245.08:19:43.80#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:43.80#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.245.08:19:43.80#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.245.08:19:43.80#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:43.80#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:43.92#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:43.92#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:43.92#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:19:43.92#ibcon#first serial, iclass 7, count 0 2006.245.08:19:43.92#ibcon#enter sib2, iclass 7, count 0 2006.245.08:19:43.92#ibcon#flushed, iclass 7, count 0 2006.245.08:19:43.92#ibcon#about to write, iclass 7, count 0 2006.245.08:19:43.92#ibcon#wrote, iclass 7, count 0 2006.245.08:19:43.92#ibcon#about to read 3, iclass 7, count 0 2006.245.08:19:43.94#ibcon#read 3, iclass 7, count 0 2006.245.08:19:43.94#ibcon#about to read 4, iclass 7, count 0 2006.245.08:19:43.94#ibcon#read 4, iclass 7, count 0 2006.245.08:19:43.94#ibcon#about to read 5, iclass 7, count 0 2006.245.08:19:43.94#ibcon#read 5, iclass 7, count 0 2006.245.08:19:43.94#ibcon#about to read 6, iclass 7, count 0 2006.245.08:19:43.94#ibcon#read 6, iclass 7, count 0 2006.245.08:19:43.94#ibcon#end of sib2, iclass 7, count 0 2006.245.08:19:43.94#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:19:43.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:19:43.94#ibcon#[27=USB\r\n] 2006.245.08:19:43.94#ibcon#*before write, iclass 7, count 0 2006.245.08:19:43.94#ibcon#enter sib2, iclass 7, count 0 2006.245.08:19:43.94#ibcon#flushed, iclass 7, count 0 2006.245.08:19:43.94#ibcon#about to write, iclass 7, count 0 2006.245.08:19:43.94#ibcon#wrote, iclass 7, count 0 2006.245.08:19:43.94#ibcon#about to read 3, iclass 7, count 0 2006.245.08:19:43.97#ibcon#read 3, iclass 7, count 0 2006.245.08:19:43.97#ibcon#about to read 4, iclass 7, count 0 2006.245.08:19:43.97#ibcon#read 4, iclass 7, count 0 2006.245.08:19:43.97#ibcon#about to read 5, iclass 7, count 0 2006.245.08:19:43.97#ibcon#read 5, iclass 7, count 0 2006.245.08:19:43.97#ibcon#about to read 6, iclass 7, count 0 2006.245.08:19:43.97#ibcon#read 6, iclass 7, count 0 2006.245.08:19:43.97#ibcon#end of sib2, iclass 7, count 0 2006.245.08:19:43.97#ibcon#*after write, iclass 7, count 0 2006.245.08:19:43.97#ibcon#*before return 0, iclass 7, count 0 2006.245.08:19:43.97#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:43.97#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.245.08:19:43.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:19:43.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:19:43.97$vc4f8/vblo=6,752.99 2006.245.08:19:43.97#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.245.08:19:43.97#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.245.08:19:43.97#ibcon#ireg 17 cls_cnt 0 2006.245.08:19:43.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:43.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:43.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:43.97#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:19:43.97#ibcon#first serial, iclass 11, count 0 2006.245.08:19:43.97#ibcon#enter sib2, iclass 11, count 0 2006.245.08:19:43.97#ibcon#flushed, iclass 11, count 0 2006.245.08:19:43.97#ibcon#about to write, iclass 11, count 0 2006.245.08:19:43.97#ibcon#wrote, iclass 11, count 0 2006.245.08:19:43.97#ibcon#about to read 3, iclass 11, count 0 2006.245.08:19:43.99#ibcon#read 3, iclass 11, count 0 2006.245.08:19:43.99#ibcon#about to read 4, iclass 11, count 0 2006.245.08:19:43.99#ibcon#read 4, iclass 11, count 0 2006.245.08:19:43.99#ibcon#about to read 5, iclass 11, count 0 2006.245.08:19:43.99#ibcon#read 5, iclass 11, count 0 2006.245.08:19:43.99#ibcon#about to read 6, iclass 11, count 0 2006.245.08:19:43.99#ibcon#read 6, iclass 11, count 0 2006.245.08:19:43.99#ibcon#end of sib2, iclass 11, count 0 2006.245.08:19:43.99#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:19:43.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:19:43.99#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:19:43.99#ibcon#*before write, iclass 11, count 0 2006.245.08:19:43.99#ibcon#enter sib2, iclass 11, count 0 2006.245.08:19:43.99#ibcon#flushed, iclass 11, count 0 2006.245.08:19:43.99#ibcon#about to write, iclass 11, count 0 2006.245.08:19:43.99#ibcon#wrote, iclass 11, count 0 2006.245.08:19:43.99#ibcon#about to read 3, iclass 11, count 0 2006.245.08:19:44.03#ibcon#read 3, iclass 11, count 0 2006.245.08:19:44.03#ibcon#about to read 4, iclass 11, count 0 2006.245.08:19:44.03#ibcon#read 4, iclass 11, count 0 2006.245.08:19:44.03#ibcon#about to read 5, iclass 11, count 0 2006.245.08:19:44.03#ibcon#read 5, iclass 11, count 0 2006.245.08:19:44.03#ibcon#about to read 6, iclass 11, count 0 2006.245.08:19:44.03#ibcon#read 6, iclass 11, count 0 2006.245.08:19:44.03#ibcon#end of sib2, iclass 11, count 0 2006.245.08:19:44.03#ibcon#*after write, iclass 11, count 0 2006.245.08:19:44.03#ibcon#*before return 0, iclass 11, count 0 2006.245.08:19:44.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:44.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.245.08:19:44.03#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:19:44.03#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:19:44.03$vc4f8/vb=6,3 2006.245.08:19:44.03#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.245.08:19:44.03#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.245.08:19:44.03#ibcon#ireg 11 cls_cnt 2 2006.245.08:19:44.03#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:44.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:44.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:44.09#ibcon#enter wrdev, iclass 13, count 2 2006.245.08:19:44.09#ibcon#first serial, iclass 13, count 2 2006.245.08:19:44.09#ibcon#enter sib2, iclass 13, count 2 2006.245.08:19:44.09#ibcon#flushed, iclass 13, count 2 2006.245.08:19:44.09#ibcon#about to write, iclass 13, count 2 2006.245.08:19:44.09#ibcon#wrote, iclass 13, count 2 2006.245.08:19:44.09#ibcon#about to read 3, iclass 13, count 2 2006.245.08:19:44.11#ibcon#read 3, iclass 13, count 2 2006.245.08:19:44.11#ibcon#about to read 4, iclass 13, count 2 2006.245.08:19:44.11#ibcon#read 4, iclass 13, count 2 2006.245.08:19:44.11#ibcon#about to read 5, iclass 13, count 2 2006.245.08:19:44.11#ibcon#read 5, iclass 13, count 2 2006.245.08:19:44.11#ibcon#about to read 6, iclass 13, count 2 2006.245.08:19:44.11#ibcon#read 6, iclass 13, count 2 2006.245.08:19:44.11#ibcon#end of sib2, iclass 13, count 2 2006.245.08:19:44.11#ibcon#*mode == 0, iclass 13, count 2 2006.245.08:19:44.11#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.245.08:19:44.11#ibcon#[27=AT06-03\r\n] 2006.245.08:19:44.11#ibcon#*before write, iclass 13, count 2 2006.245.08:19:44.11#ibcon#enter sib2, iclass 13, count 2 2006.245.08:19:44.11#ibcon#flushed, iclass 13, count 2 2006.245.08:19:44.11#ibcon#about to write, iclass 13, count 2 2006.245.08:19:44.11#ibcon#wrote, iclass 13, count 2 2006.245.08:19:44.11#ibcon#about to read 3, iclass 13, count 2 2006.245.08:19:44.14#ibcon#read 3, iclass 13, count 2 2006.245.08:19:44.14#ibcon#about to read 4, iclass 13, count 2 2006.245.08:19:44.14#ibcon#read 4, iclass 13, count 2 2006.245.08:19:44.14#ibcon#about to read 5, iclass 13, count 2 2006.245.08:19:44.14#ibcon#read 5, iclass 13, count 2 2006.245.08:19:44.14#ibcon#about to read 6, iclass 13, count 2 2006.245.08:19:44.14#ibcon#read 6, iclass 13, count 2 2006.245.08:19:44.14#ibcon#end of sib2, iclass 13, count 2 2006.245.08:19:44.14#ibcon#*after write, iclass 13, count 2 2006.245.08:19:44.14#ibcon#*before return 0, iclass 13, count 2 2006.245.08:19:44.14#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:44.14#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.245.08:19:44.14#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.245.08:19:44.14#ibcon#ireg 7 cls_cnt 0 2006.245.08:19:44.14#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:44.26#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:44.26#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:44.26#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:19:44.26#ibcon#first serial, iclass 13, count 0 2006.245.08:19:44.26#ibcon#enter sib2, iclass 13, count 0 2006.245.08:19:44.26#ibcon#flushed, iclass 13, count 0 2006.245.08:19:44.26#ibcon#about to write, iclass 13, count 0 2006.245.08:19:44.26#ibcon#wrote, iclass 13, count 0 2006.245.08:19:44.26#ibcon#about to read 3, iclass 13, count 0 2006.245.08:19:44.28#ibcon#read 3, iclass 13, count 0 2006.245.08:19:44.28#ibcon#about to read 4, iclass 13, count 0 2006.245.08:19:44.28#ibcon#read 4, iclass 13, count 0 2006.245.08:19:44.28#ibcon#about to read 5, iclass 13, count 0 2006.245.08:19:44.28#ibcon#read 5, iclass 13, count 0 2006.245.08:19:44.28#ibcon#about to read 6, iclass 13, count 0 2006.245.08:19:44.28#ibcon#read 6, iclass 13, count 0 2006.245.08:19:44.28#ibcon#end of sib2, iclass 13, count 0 2006.245.08:19:44.28#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:19:44.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:19:44.28#ibcon#[27=USB\r\n] 2006.245.08:19:44.28#ibcon#*before write, iclass 13, count 0 2006.245.08:19:44.28#ibcon#enter sib2, iclass 13, count 0 2006.245.08:19:44.28#ibcon#flushed, iclass 13, count 0 2006.245.08:19:44.28#ibcon#about to write, iclass 13, count 0 2006.245.08:19:44.28#ibcon#wrote, iclass 13, count 0 2006.245.08:19:44.28#ibcon#about to read 3, iclass 13, count 0 2006.245.08:19:44.31#ibcon#read 3, iclass 13, count 0 2006.245.08:19:44.31#ibcon#about to read 4, iclass 13, count 0 2006.245.08:19:44.31#ibcon#read 4, iclass 13, count 0 2006.245.08:19:44.31#ibcon#about to read 5, iclass 13, count 0 2006.245.08:19:44.31#ibcon#read 5, iclass 13, count 0 2006.245.08:19:44.31#ibcon#about to read 6, iclass 13, count 0 2006.245.08:19:44.31#ibcon#read 6, iclass 13, count 0 2006.245.08:19:44.31#ibcon#end of sib2, iclass 13, count 0 2006.245.08:19:44.31#ibcon#*after write, iclass 13, count 0 2006.245.08:19:44.31#ibcon#*before return 0, iclass 13, count 0 2006.245.08:19:44.31#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:44.31#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.245.08:19:44.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:19:44.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:19:44.31$vc4f8/vabw=wide 2006.245.08:19:44.31#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.245.08:19:44.31#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.245.08:19:44.31#ibcon#ireg 8 cls_cnt 0 2006.245.08:19:44.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:44.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:44.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:44.31#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:19:44.31#ibcon#first serial, iclass 15, count 0 2006.245.08:19:44.31#ibcon#enter sib2, iclass 15, count 0 2006.245.08:19:44.31#ibcon#flushed, iclass 15, count 0 2006.245.08:19:44.31#ibcon#about to write, iclass 15, count 0 2006.245.08:19:44.31#ibcon#wrote, iclass 15, count 0 2006.245.08:19:44.31#ibcon#about to read 3, iclass 15, count 0 2006.245.08:19:44.33#ibcon#read 3, iclass 15, count 0 2006.245.08:19:44.33#ibcon#about to read 4, iclass 15, count 0 2006.245.08:19:44.33#ibcon#read 4, iclass 15, count 0 2006.245.08:19:44.33#ibcon#about to read 5, iclass 15, count 0 2006.245.08:19:44.33#ibcon#read 5, iclass 15, count 0 2006.245.08:19:44.33#ibcon#about to read 6, iclass 15, count 0 2006.245.08:19:44.33#ibcon#read 6, iclass 15, count 0 2006.245.08:19:44.33#ibcon#end of sib2, iclass 15, count 0 2006.245.08:19:44.33#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:19:44.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:19:44.33#ibcon#[25=BW32\r\n] 2006.245.08:19:44.33#ibcon#*before write, iclass 15, count 0 2006.245.08:19:44.33#ibcon#enter sib2, iclass 15, count 0 2006.245.08:19:44.33#ibcon#flushed, iclass 15, count 0 2006.245.08:19:44.33#ibcon#about to write, iclass 15, count 0 2006.245.08:19:44.33#ibcon#wrote, iclass 15, count 0 2006.245.08:19:44.33#ibcon#about to read 3, iclass 15, count 0 2006.245.08:19:44.37#ibcon#read 3, iclass 15, count 0 2006.245.08:19:44.37#ibcon#about to read 4, iclass 15, count 0 2006.245.08:19:44.37#ibcon#read 4, iclass 15, count 0 2006.245.08:19:44.37#ibcon#about to read 5, iclass 15, count 0 2006.245.08:19:44.37#ibcon#read 5, iclass 15, count 0 2006.245.08:19:44.37#ibcon#about to read 6, iclass 15, count 0 2006.245.08:19:44.37#ibcon#read 6, iclass 15, count 0 2006.245.08:19:44.37#ibcon#end of sib2, iclass 15, count 0 2006.245.08:19:44.37#ibcon#*after write, iclass 15, count 0 2006.245.08:19:44.37#ibcon#*before return 0, iclass 15, count 0 2006.245.08:19:44.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:44.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.245.08:19:44.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:19:44.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:19:44.37$vc4f8/vbbw=wide 2006.245.08:19:44.37#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:19:44.37#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:19:44.37#ibcon#ireg 8 cls_cnt 0 2006.245.08:19:44.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:19:44.43#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:19:44.43#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:19:44.43#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:19:44.43#ibcon#first serial, iclass 17, count 0 2006.245.08:19:44.43#ibcon#enter sib2, iclass 17, count 0 2006.245.08:19:44.43#ibcon#flushed, iclass 17, count 0 2006.245.08:19:44.43#ibcon#about to write, iclass 17, count 0 2006.245.08:19:44.43#ibcon#wrote, iclass 17, count 0 2006.245.08:19:44.43#ibcon#about to read 3, iclass 17, count 0 2006.245.08:19:44.45#ibcon#read 3, iclass 17, count 0 2006.245.08:19:44.45#ibcon#about to read 4, iclass 17, count 0 2006.245.08:19:44.45#ibcon#read 4, iclass 17, count 0 2006.245.08:19:44.45#ibcon#about to read 5, iclass 17, count 0 2006.245.08:19:44.45#ibcon#read 5, iclass 17, count 0 2006.245.08:19:44.45#ibcon#about to read 6, iclass 17, count 0 2006.245.08:19:44.45#ibcon#read 6, iclass 17, count 0 2006.245.08:19:44.45#ibcon#end of sib2, iclass 17, count 0 2006.245.08:19:44.45#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:19:44.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:19:44.45#ibcon#[27=BW32\r\n] 2006.245.08:19:44.45#ibcon#*before write, iclass 17, count 0 2006.245.08:19:44.45#ibcon#enter sib2, iclass 17, count 0 2006.245.08:19:44.45#ibcon#flushed, iclass 17, count 0 2006.245.08:19:44.45#ibcon#about to write, iclass 17, count 0 2006.245.08:19:44.45#ibcon#wrote, iclass 17, count 0 2006.245.08:19:44.45#ibcon#about to read 3, iclass 17, count 0 2006.245.08:19:44.48#ibcon#read 3, iclass 17, count 0 2006.245.08:19:44.48#ibcon#about to read 4, iclass 17, count 0 2006.245.08:19:44.48#ibcon#read 4, iclass 17, count 0 2006.245.08:19:44.48#ibcon#about to read 5, iclass 17, count 0 2006.245.08:19:44.48#ibcon#read 5, iclass 17, count 0 2006.245.08:19:44.48#ibcon#about to read 6, iclass 17, count 0 2006.245.08:19:44.48#ibcon#read 6, iclass 17, count 0 2006.245.08:19:44.48#ibcon#end of sib2, iclass 17, count 0 2006.245.08:19:44.48#ibcon#*after write, iclass 17, count 0 2006.245.08:19:44.48#ibcon#*before return 0, iclass 17, count 0 2006.245.08:19:44.48#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:19:44.48#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:19:44.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:19:44.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:19:44.48$4f8m12a/ifd4f 2006.245.08:19:44.48$ifd4f/lo= 2006.245.08:19:44.48$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:19:44.48$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:19:44.48$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:19:44.48$ifd4f/patch= 2006.245.08:19:44.48$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:19:44.48$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:19:44.48$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:19:44.48$4f8m12a/"form=m,16.000,1:2 2006.245.08:19:44.48$4f8m12a/"tpicd 2006.245.08:19:44.48$4f8m12a/echo=off 2006.245.08:19:44.48$4f8m12a/xlog=off 2006.245.08:19:44.48:!2006.245.08:21:00 2006.245.08:19:56.14#trakl#Source acquired 2006.245.08:19:58.14#flagr#flagr/antenna,acquired 2006.245.08:21:00.00:preob 2006.245.08:21:00.13/onsource/TRACKING 2006.245.08:21:00.13:!2006.245.08:21:10 2006.245.08:21:10.00:data_valid=on 2006.245.08:21:10.00:midob 2006.245.08:21:10.13/onsource/TRACKING 2006.245.08:21:10.13/wx/26.72,1004.5,76 2006.245.08:21:10.27/cable/+6.4113E-03 2006.245.08:21:11.36/va/01,08,usb,yes,44,46 2006.245.08:21:11.36/va/02,07,usb,yes,43,45 2006.245.08:21:11.36/va/03,06,usb,yes,45,46 2006.245.08:21:11.36/va/04,07,usb,yes,44,47 2006.245.08:21:11.36/va/05,07,usb,yes,48,51 2006.245.08:21:11.36/va/06,07,usb,yes,42,41 2006.245.08:21:11.36/va/07,07,usb,yes,41,41 2006.245.08:21:11.36/va/08,08,usb,yes,36,36 2006.245.08:21:11.59/valo/01,532.99,yes,locked 2006.245.08:21:11.59/valo/02,572.99,yes,locked 2006.245.08:21:11.59/valo/03,672.99,yes,locked 2006.245.08:21:11.59/valo/04,832.99,yes,locked 2006.245.08:21:11.59/valo/05,652.99,yes,locked 2006.245.08:21:11.59/valo/06,772.99,yes,locked 2006.245.08:21:11.59/valo/07,832.99,yes,locked 2006.245.08:21:11.59/valo/08,852.99,yes,locked 2006.245.08:21:12.68/vb/01,04,usb,yes,40,38 2006.245.08:21:12.68/vb/02,04,usb,yes,42,44 2006.245.08:21:12.68/vb/03,04,usb,yes,38,43 2006.245.08:21:12.68/vb/04,04,usb,yes,39,39 2006.245.08:21:12.68/vb/05,03,usb,yes,45,51 2006.245.08:21:12.68/vb/06,03,usb,yes,46,51 2006.245.08:21:12.68/vb/07,04,usb,yes,41,41 2006.245.08:21:12.68/vb/08,03,usb,yes,46,51 2006.245.08:21:12.92/vblo/01,632.99,yes,locked 2006.245.08:21:12.92/vblo/02,640.99,yes,locked 2006.245.08:21:12.92/vblo/03,656.99,yes,locked 2006.245.08:21:12.92/vblo/04,712.99,yes,locked 2006.245.08:21:12.92/vblo/05,744.99,yes,locked 2006.245.08:21:12.92/vblo/06,752.99,yes,locked 2006.245.08:21:12.92/vblo/07,734.99,yes,locked 2006.245.08:21:12.92/vblo/08,744.99,yes,locked 2006.245.08:21:13.07/vabw/8 2006.245.08:21:13.22/vbbw/8 2006.245.08:21:13.43/xfe/off,on,13.5 2006.245.08:21:13.81/ifatt/23,28,28,28 2006.245.08:21:14.08/fmout-gps/S +4.35E-07 2006.245.08:21:14.12:!2006.245.08:22:10 2006.245.08:22:10.00:data_valid=off 2006.245.08:22:10.00:postob 2006.245.08:22:10.22/cable/+6.4124E-03 2006.245.08:22:10.22/wx/26.70,1004.5,75 2006.245.08:22:11.08/fmout-gps/S +4.34E-07 2006.245.08:22:11.08:scan_name=245-0824,k06245,60 2006.245.08:22:11.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.245.08:22:11.13#flagr#flagr/antenna,new-source 2006.245.08:22:12.13:checkk5 2006.245.08:22:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:22:13.02/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:22:13.41/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:22:13.83/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:22:14.27/chk_obsdata//k5ts1/T2450821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:22:14.71/chk_obsdata//k5ts2/T2450821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:22:15.16/chk_obsdata//k5ts3/T2450821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:22:15.59/chk_obsdata//k5ts4/T2450821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:22:16.45/k5log//k5ts1_log_newline 2006.245.08:22:17.29/k5log//k5ts2_log_newline 2006.245.08:22:18.11/k5log//k5ts3_log_newline 2006.245.08:22:22.06/k5log//k5ts4_log_newline 2006.245.08:22:22.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:22:22.08:4f8m12a=3 2006.245.08:22:22.08$4f8m12a/echo=on 2006.245.08:22:22.08$4f8m12a/pcalon 2006.245.08:22:22.08$pcalon/"no phase cal control is implemented here 2006.245.08:22:22.08$4f8m12a/"tpicd=stop 2006.245.08:22:22.08$4f8m12a/vc4f8 2006.245.08:22:22.08$vc4f8/valo=1,532.99 2006.245.08:22:22.09#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.08:22:22.09#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.08:22:22.09#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:22.09#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:22.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:22.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:22.09#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:22:22.09#ibcon#first serial, iclass 12, count 0 2006.245.08:22:22.09#ibcon#enter sib2, iclass 12, count 0 2006.245.08:22:22.09#ibcon#flushed, iclass 12, count 0 2006.245.08:22:22.09#ibcon#about to write, iclass 12, count 0 2006.245.08:22:22.09#ibcon#wrote, iclass 12, count 0 2006.245.08:22:22.09#ibcon#about to read 3, iclass 12, count 0 2006.245.08:22:22.13#ibcon#read 3, iclass 12, count 0 2006.245.08:22:22.13#ibcon#about to read 4, iclass 12, count 0 2006.245.08:22:22.13#ibcon#read 4, iclass 12, count 0 2006.245.08:22:22.13#ibcon#about to read 5, iclass 12, count 0 2006.245.08:22:22.13#ibcon#read 5, iclass 12, count 0 2006.245.08:22:22.13#ibcon#about to read 6, iclass 12, count 0 2006.245.08:22:22.13#ibcon#read 6, iclass 12, count 0 2006.245.08:22:22.13#ibcon#end of sib2, iclass 12, count 0 2006.245.08:22:22.13#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:22:22.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:22:22.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:22:22.13#ibcon#*before write, iclass 12, count 0 2006.245.08:22:22.13#ibcon#enter sib2, iclass 12, count 0 2006.245.08:22:22.13#ibcon#flushed, iclass 12, count 0 2006.245.08:22:22.13#ibcon#about to write, iclass 12, count 0 2006.245.08:22:22.13#ibcon#wrote, iclass 12, count 0 2006.245.08:22:22.13#ibcon#about to read 3, iclass 12, count 0 2006.245.08:22:22.18#ibcon#read 3, iclass 12, count 0 2006.245.08:22:22.18#ibcon#about to read 4, iclass 12, count 0 2006.245.08:22:22.18#ibcon#read 4, iclass 12, count 0 2006.245.08:22:22.18#ibcon#about to read 5, iclass 12, count 0 2006.245.08:22:22.18#ibcon#read 5, iclass 12, count 0 2006.245.08:22:22.18#ibcon#about to read 6, iclass 12, count 0 2006.245.08:22:22.18#ibcon#read 6, iclass 12, count 0 2006.245.08:22:22.18#ibcon#end of sib2, iclass 12, count 0 2006.245.08:22:22.18#ibcon#*after write, iclass 12, count 0 2006.245.08:22:22.18#ibcon#*before return 0, iclass 12, count 0 2006.245.08:22:22.18#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:22.18#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:22.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:22:22.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:22:22.18$vc4f8/va=1,8 2006.245.08:22:22.18#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.08:22:22.18#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.08:22:22.18#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:22.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:22.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:22.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:22.18#ibcon#enter wrdev, iclass 14, count 2 2006.245.08:22:22.18#ibcon#first serial, iclass 14, count 2 2006.245.08:22:22.18#ibcon#enter sib2, iclass 14, count 2 2006.245.08:22:22.18#ibcon#flushed, iclass 14, count 2 2006.245.08:22:22.18#ibcon#about to write, iclass 14, count 2 2006.245.08:22:22.18#ibcon#wrote, iclass 14, count 2 2006.245.08:22:22.18#ibcon#about to read 3, iclass 14, count 2 2006.245.08:22:22.20#ibcon#read 3, iclass 14, count 2 2006.245.08:22:22.20#ibcon#about to read 4, iclass 14, count 2 2006.245.08:22:22.20#ibcon#read 4, iclass 14, count 2 2006.245.08:22:22.20#ibcon#about to read 5, iclass 14, count 2 2006.245.08:22:22.20#ibcon#read 5, iclass 14, count 2 2006.245.08:22:22.20#ibcon#about to read 6, iclass 14, count 2 2006.245.08:22:22.20#ibcon#read 6, iclass 14, count 2 2006.245.08:22:22.20#ibcon#end of sib2, iclass 14, count 2 2006.245.08:22:22.20#ibcon#*mode == 0, iclass 14, count 2 2006.245.08:22:22.20#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.08:22:22.20#ibcon#[25=AT01-08\r\n] 2006.245.08:22:22.20#ibcon#*before write, iclass 14, count 2 2006.245.08:22:22.20#ibcon#enter sib2, iclass 14, count 2 2006.245.08:22:22.20#ibcon#flushed, iclass 14, count 2 2006.245.08:22:22.20#ibcon#about to write, iclass 14, count 2 2006.245.08:22:22.20#ibcon#wrote, iclass 14, count 2 2006.245.08:22:22.20#ibcon#about to read 3, iclass 14, count 2 2006.245.08:22:22.24#ibcon#read 3, iclass 14, count 2 2006.245.08:22:22.24#ibcon#about to read 4, iclass 14, count 2 2006.245.08:22:22.24#ibcon#read 4, iclass 14, count 2 2006.245.08:22:22.24#ibcon#about to read 5, iclass 14, count 2 2006.245.08:22:22.24#ibcon#read 5, iclass 14, count 2 2006.245.08:22:22.24#ibcon#about to read 6, iclass 14, count 2 2006.245.08:22:22.24#ibcon#read 6, iclass 14, count 2 2006.245.08:22:22.24#ibcon#end of sib2, iclass 14, count 2 2006.245.08:22:22.24#ibcon#*after write, iclass 14, count 2 2006.245.08:22:22.24#ibcon#*before return 0, iclass 14, count 2 2006.245.08:22:22.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:22.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:22.24#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.08:22:22.24#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:22.24#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:22.36#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:22.36#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:22.36#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:22:22.36#ibcon#first serial, iclass 14, count 0 2006.245.08:22:22.36#ibcon#enter sib2, iclass 14, count 0 2006.245.08:22:22.36#ibcon#flushed, iclass 14, count 0 2006.245.08:22:22.36#ibcon#about to write, iclass 14, count 0 2006.245.08:22:22.36#ibcon#wrote, iclass 14, count 0 2006.245.08:22:22.36#ibcon#about to read 3, iclass 14, count 0 2006.245.08:22:22.38#ibcon#read 3, iclass 14, count 0 2006.245.08:22:22.38#ibcon#about to read 4, iclass 14, count 0 2006.245.08:22:22.38#ibcon#read 4, iclass 14, count 0 2006.245.08:22:22.38#ibcon#about to read 5, iclass 14, count 0 2006.245.08:22:22.38#ibcon#read 5, iclass 14, count 0 2006.245.08:22:22.38#ibcon#about to read 6, iclass 14, count 0 2006.245.08:22:22.38#ibcon#read 6, iclass 14, count 0 2006.245.08:22:22.38#ibcon#end of sib2, iclass 14, count 0 2006.245.08:22:22.38#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:22:22.38#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:22:22.38#ibcon#[25=USB\r\n] 2006.245.08:22:22.38#ibcon#*before write, iclass 14, count 0 2006.245.08:22:22.38#ibcon#enter sib2, iclass 14, count 0 2006.245.08:22:22.38#ibcon#flushed, iclass 14, count 0 2006.245.08:22:22.38#ibcon#about to write, iclass 14, count 0 2006.245.08:22:22.38#ibcon#wrote, iclass 14, count 0 2006.245.08:22:22.38#ibcon#about to read 3, iclass 14, count 0 2006.245.08:22:22.41#ibcon#read 3, iclass 14, count 0 2006.245.08:22:22.41#ibcon#about to read 4, iclass 14, count 0 2006.245.08:22:22.41#ibcon#read 4, iclass 14, count 0 2006.245.08:22:22.41#ibcon#about to read 5, iclass 14, count 0 2006.245.08:22:22.41#ibcon#read 5, iclass 14, count 0 2006.245.08:22:22.41#ibcon#about to read 6, iclass 14, count 0 2006.245.08:22:22.41#ibcon#read 6, iclass 14, count 0 2006.245.08:22:22.41#ibcon#end of sib2, iclass 14, count 0 2006.245.08:22:22.41#ibcon#*after write, iclass 14, count 0 2006.245.08:22:22.41#ibcon#*before return 0, iclass 14, count 0 2006.245.08:22:22.41#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:22.41#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:22.41#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:22:22.41#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:22:22.41$vc4f8/valo=2,572.99 2006.245.08:22:22.41#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.08:22:22.41#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.08:22:22.41#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:22.41#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:22.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:22.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:22.41#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:22:22.41#ibcon#first serial, iclass 16, count 0 2006.245.08:22:22.41#ibcon#enter sib2, iclass 16, count 0 2006.245.08:22:22.41#ibcon#flushed, iclass 16, count 0 2006.245.08:22:22.41#ibcon#about to write, iclass 16, count 0 2006.245.08:22:22.41#ibcon#wrote, iclass 16, count 0 2006.245.08:22:22.41#ibcon#about to read 3, iclass 16, count 0 2006.245.08:22:22.43#ibcon#read 3, iclass 16, count 0 2006.245.08:22:22.43#ibcon#about to read 4, iclass 16, count 0 2006.245.08:22:22.43#ibcon#read 4, iclass 16, count 0 2006.245.08:22:22.43#ibcon#about to read 5, iclass 16, count 0 2006.245.08:22:22.43#ibcon#read 5, iclass 16, count 0 2006.245.08:22:22.43#ibcon#about to read 6, iclass 16, count 0 2006.245.08:22:22.43#ibcon#read 6, iclass 16, count 0 2006.245.08:22:22.43#ibcon#end of sib2, iclass 16, count 0 2006.245.08:22:22.43#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:22:22.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:22:22.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:22:22.43#ibcon#*before write, iclass 16, count 0 2006.245.08:22:22.43#ibcon#enter sib2, iclass 16, count 0 2006.245.08:22:22.43#ibcon#flushed, iclass 16, count 0 2006.245.08:22:22.43#ibcon#about to write, iclass 16, count 0 2006.245.08:22:22.43#ibcon#wrote, iclass 16, count 0 2006.245.08:22:22.43#ibcon#about to read 3, iclass 16, count 0 2006.245.08:22:22.48#ibcon#read 3, iclass 16, count 0 2006.245.08:22:22.48#ibcon#about to read 4, iclass 16, count 0 2006.245.08:22:22.48#ibcon#read 4, iclass 16, count 0 2006.245.08:22:22.48#ibcon#about to read 5, iclass 16, count 0 2006.245.08:22:22.48#ibcon#read 5, iclass 16, count 0 2006.245.08:22:22.48#ibcon#about to read 6, iclass 16, count 0 2006.245.08:22:22.48#ibcon#read 6, iclass 16, count 0 2006.245.08:22:22.48#ibcon#end of sib2, iclass 16, count 0 2006.245.08:22:22.48#ibcon#*after write, iclass 16, count 0 2006.245.08:22:22.48#ibcon#*before return 0, iclass 16, count 0 2006.245.08:22:22.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:22.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:22.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:22:22.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:22:22.48$vc4f8/va=2,7 2006.245.08:22:22.48#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.08:22:22.48#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.08:22:22.48#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:22.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:22.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:22.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:22.53#ibcon#enter wrdev, iclass 18, count 2 2006.245.08:22:22.53#ibcon#first serial, iclass 18, count 2 2006.245.08:22:22.53#ibcon#enter sib2, iclass 18, count 2 2006.245.08:22:22.53#ibcon#flushed, iclass 18, count 2 2006.245.08:22:22.53#ibcon#about to write, iclass 18, count 2 2006.245.08:22:22.53#ibcon#wrote, iclass 18, count 2 2006.245.08:22:22.53#ibcon#about to read 3, iclass 18, count 2 2006.245.08:22:22.55#ibcon#read 3, iclass 18, count 2 2006.245.08:22:22.55#ibcon#about to read 4, iclass 18, count 2 2006.245.08:22:22.55#ibcon#read 4, iclass 18, count 2 2006.245.08:22:22.55#ibcon#about to read 5, iclass 18, count 2 2006.245.08:22:22.55#ibcon#read 5, iclass 18, count 2 2006.245.08:22:22.55#ibcon#about to read 6, iclass 18, count 2 2006.245.08:22:22.55#ibcon#read 6, iclass 18, count 2 2006.245.08:22:22.55#ibcon#end of sib2, iclass 18, count 2 2006.245.08:22:22.55#ibcon#*mode == 0, iclass 18, count 2 2006.245.08:22:22.55#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.08:22:22.55#ibcon#[25=AT02-07\r\n] 2006.245.08:22:22.55#ibcon#*before write, iclass 18, count 2 2006.245.08:22:22.55#ibcon#enter sib2, iclass 18, count 2 2006.245.08:22:22.55#ibcon#flushed, iclass 18, count 2 2006.245.08:22:22.55#ibcon#about to write, iclass 18, count 2 2006.245.08:22:22.55#ibcon#wrote, iclass 18, count 2 2006.245.08:22:22.55#ibcon#about to read 3, iclass 18, count 2 2006.245.08:22:22.58#ibcon#read 3, iclass 18, count 2 2006.245.08:22:22.58#ibcon#about to read 4, iclass 18, count 2 2006.245.08:22:22.58#ibcon#read 4, iclass 18, count 2 2006.245.08:22:22.58#ibcon#about to read 5, iclass 18, count 2 2006.245.08:22:22.58#ibcon#read 5, iclass 18, count 2 2006.245.08:22:22.58#ibcon#about to read 6, iclass 18, count 2 2006.245.08:22:22.58#ibcon#read 6, iclass 18, count 2 2006.245.08:22:22.58#ibcon#end of sib2, iclass 18, count 2 2006.245.08:22:22.58#ibcon#*after write, iclass 18, count 2 2006.245.08:22:22.58#ibcon#*before return 0, iclass 18, count 2 2006.245.08:22:22.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:22.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:22.58#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.08:22:22.58#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:22.58#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:22.70#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:22.70#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:22.70#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:22:22.70#ibcon#first serial, iclass 18, count 0 2006.245.08:22:22.70#ibcon#enter sib2, iclass 18, count 0 2006.245.08:22:22.70#ibcon#flushed, iclass 18, count 0 2006.245.08:22:22.70#ibcon#about to write, iclass 18, count 0 2006.245.08:22:22.70#ibcon#wrote, iclass 18, count 0 2006.245.08:22:22.70#ibcon#about to read 3, iclass 18, count 0 2006.245.08:22:22.72#ibcon#read 3, iclass 18, count 0 2006.245.08:22:22.72#ibcon#about to read 4, iclass 18, count 0 2006.245.08:22:22.72#ibcon#read 4, iclass 18, count 0 2006.245.08:22:22.72#ibcon#about to read 5, iclass 18, count 0 2006.245.08:22:22.72#ibcon#read 5, iclass 18, count 0 2006.245.08:22:22.72#ibcon#about to read 6, iclass 18, count 0 2006.245.08:22:22.72#ibcon#read 6, iclass 18, count 0 2006.245.08:22:22.72#ibcon#end of sib2, iclass 18, count 0 2006.245.08:22:22.72#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:22:22.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:22:22.72#ibcon#[25=USB\r\n] 2006.245.08:22:22.72#ibcon#*before write, iclass 18, count 0 2006.245.08:22:22.72#ibcon#enter sib2, iclass 18, count 0 2006.245.08:22:22.72#ibcon#flushed, iclass 18, count 0 2006.245.08:22:22.72#ibcon#about to write, iclass 18, count 0 2006.245.08:22:22.72#ibcon#wrote, iclass 18, count 0 2006.245.08:22:22.72#ibcon#about to read 3, iclass 18, count 0 2006.245.08:22:22.75#ibcon#read 3, iclass 18, count 0 2006.245.08:22:22.75#ibcon#about to read 4, iclass 18, count 0 2006.245.08:22:22.75#ibcon#read 4, iclass 18, count 0 2006.245.08:22:22.75#ibcon#about to read 5, iclass 18, count 0 2006.245.08:22:22.75#ibcon#read 5, iclass 18, count 0 2006.245.08:22:22.75#ibcon#about to read 6, iclass 18, count 0 2006.245.08:22:22.75#ibcon#read 6, iclass 18, count 0 2006.245.08:22:22.75#ibcon#end of sib2, iclass 18, count 0 2006.245.08:22:22.75#ibcon#*after write, iclass 18, count 0 2006.245.08:22:22.75#ibcon#*before return 0, iclass 18, count 0 2006.245.08:22:22.75#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:22.75#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:22.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:22:22.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:22:22.75$vc4f8/valo=3,672.99 2006.245.08:22:22.75#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.08:22:22.75#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.08:22:22.75#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:22.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:22.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:22.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:22.75#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:22:22.75#ibcon#first serial, iclass 20, count 0 2006.245.08:22:22.75#ibcon#enter sib2, iclass 20, count 0 2006.245.08:22:22.75#ibcon#flushed, iclass 20, count 0 2006.245.08:22:22.75#ibcon#about to write, iclass 20, count 0 2006.245.08:22:22.75#ibcon#wrote, iclass 20, count 0 2006.245.08:22:22.75#ibcon#about to read 3, iclass 20, count 0 2006.245.08:22:22.77#ibcon#read 3, iclass 20, count 0 2006.245.08:22:22.77#ibcon#about to read 4, iclass 20, count 0 2006.245.08:22:22.77#ibcon#read 4, iclass 20, count 0 2006.245.08:22:22.77#ibcon#about to read 5, iclass 20, count 0 2006.245.08:22:22.77#ibcon#read 5, iclass 20, count 0 2006.245.08:22:22.77#ibcon#about to read 6, iclass 20, count 0 2006.245.08:22:22.77#ibcon#read 6, iclass 20, count 0 2006.245.08:22:22.77#ibcon#end of sib2, iclass 20, count 0 2006.245.08:22:22.77#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:22:22.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:22:22.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:22:22.77#ibcon#*before write, iclass 20, count 0 2006.245.08:22:22.77#ibcon#enter sib2, iclass 20, count 0 2006.245.08:22:22.77#ibcon#flushed, iclass 20, count 0 2006.245.08:22:22.77#ibcon#about to write, iclass 20, count 0 2006.245.08:22:22.77#ibcon#wrote, iclass 20, count 0 2006.245.08:22:22.77#ibcon#about to read 3, iclass 20, count 0 2006.245.08:22:22.82#ibcon#read 3, iclass 20, count 0 2006.245.08:22:22.82#ibcon#about to read 4, iclass 20, count 0 2006.245.08:22:22.82#ibcon#read 4, iclass 20, count 0 2006.245.08:22:22.82#ibcon#about to read 5, iclass 20, count 0 2006.245.08:22:22.82#ibcon#read 5, iclass 20, count 0 2006.245.08:22:22.82#ibcon#about to read 6, iclass 20, count 0 2006.245.08:22:22.82#ibcon#read 6, iclass 20, count 0 2006.245.08:22:22.82#ibcon#end of sib2, iclass 20, count 0 2006.245.08:22:22.82#ibcon#*after write, iclass 20, count 0 2006.245.08:22:22.82#ibcon#*before return 0, iclass 20, count 0 2006.245.08:22:22.82#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:22.82#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:22.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:22:22.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:22:22.82$vc4f8/va=3,6 2006.245.08:22:22.82#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.08:22:22.82#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.08:22:22.82#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:22.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:22.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:22.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:22.87#ibcon#enter wrdev, iclass 22, count 2 2006.245.08:22:22.87#ibcon#first serial, iclass 22, count 2 2006.245.08:22:22.87#ibcon#enter sib2, iclass 22, count 2 2006.245.08:22:22.87#ibcon#flushed, iclass 22, count 2 2006.245.08:22:22.87#ibcon#about to write, iclass 22, count 2 2006.245.08:22:22.87#ibcon#wrote, iclass 22, count 2 2006.245.08:22:22.87#ibcon#about to read 3, iclass 22, count 2 2006.245.08:22:22.89#ibcon#read 3, iclass 22, count 2 2006.245.08:22:22.89#ibcon#about to read 4, iclass 22, count 2 2006.245.08:22:22.89#ibcon#read 4, iclass 22, count 2 2006.245.08:22:22.89#ibcon#about to read 5, iclass 22, count 2 2006.245.08:22:22.89#ibcon#read 5, iclass 22, count 2 2006.245.08:22:22.89#ibcon#about to read 6, iclass 22, count 2 2006.245.08:22:22.89#ibcon#read 6, iclass 22, count 2 2006.245.08:22:22.89#ibcon#end of sib2, iclass 22, count 2 2006.245.08:22:22.89#ibcon#*mode == 0, iclass 22, count 2 2006.245.08:22:22.89#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.08:22:22.89#ibcon#[25=AT03-06\r\n] 2006.245.08:22:22.89#ibcon#*before write, iclass 22, count 2 2006.245.08:22:22.89#ibcon#enter sib2, iclass 22, count 2 2006.245.08:22:22.89#ibcon#flushed, iclass 22, count 2 2006.245.08:22:22.89#ibcon#about to write, iclass 22, count 2 2006.245.08:22:22.89#ibcon#wrote, iclass 22, count 2 2006.245.08:22:22.89#ibcon#about to read 3, iclass 22, count 2 2006.245.08:22:22.92#ibcon#read 3, iclass 22, count 2 2006.245.08:22:22.92#ibcon#about to read 4, iclass 22, count 2 2006.245.08:22:22.92#ibcon#read 4, iclass 22, count 2 2006.245.08:22:22.92#ibcon#about to read 5, iclass 22, count 2 2006.245.08:22:22.92#ibcon#read 5, iclass 22, count 2 2006.245.08:22:22.92#ibcon#about to read 6, iclass 22, count 2 2006.245.08:22:22.92#ibcon#read 6, iclass 22, count 2 2006.245.08:22:22.92#ibcon#end of sib2, iclass 22, count 2 2006.245.08:22:22.92#ibcon#*after write, iclass 22, count 2 2006.245.08:22:22.92#ibcon#*before return 0, iclass 22, count 2 2006.245.08:22:22.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:22.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:22.92#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.08:22:22.92#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:22.92#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:23.04#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:23.04#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:23.04#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:22:23.04#ibcon#first serial, iclass 22, count 0 2006.245.08:22:23.04#ibcon#enter sib2, iclass 22, count 0 2006.245.08:22:23.04#ibcon#flushed, iclass 22, count 0 2006.245.08:22:23.04#ibcon#about to write, iclass 22, count 0 2006.245.08:22:23.04#ibcon#wrote, iclass 22, count 0 2006.245.08:22:23.04#ibcon#about to read 3, iclass 22, count 0 2006.245.08:22:23.07#ibcon#read 3, iclass 22, count 0 2006.245.08:22:23.07#ibcon#about to read 4, iclass 22, count 0 2006.245.08:22:23.07#ibcon#read 4, iclass 22, count 0 2006.245.08:22:23.07#ibcon#about to read 5, iclass 22, count 0 2006.245.08:22:23.07#ibcon#read 5, iclass 22, count 0 2006.245.08:22:23.07#ibcon#about to read 6, iclass 22, count 0 2006.245.08:22:23.07#ibcon#read 6, iclass 22, count 0 2006.245.08:22:23.07#ibcon#end of sib2, iclass 22, count 0 2006.245.08:22:23.07#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:22:23.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:22:23.07#ibcon#[25=USB\r\n] 2006.245.08:22:23.07#ibcon#*before write, iclass 22, count 0 2006.245.08:22:23.07#ibcon#enter sib2, iclass 22, count 0 2006.245.08:22:23.07#ibcon#flushed, iclass 22, count 0 2006.245.08:22:23.07#ibcon#about to write, iclass 22, count 0 2006.245.08:22:23.07#ibcon#wrote, iclass 22, count 0 2006.245.08:22:23.07#ibcon#about to read 3, iclass 22, count 0 2006.245.08:22:23.10#ibcon#read 3, iclass 22, count 0 2006.245.08:22:23.10#ibcon#about to read 4, iclass 22, count 0 2006.245.08:22:23.10#ibcon#read 4, iclass 22, count 0 2006.245.08:22:23.10#ibcon#about to read 5, iclass 22, count 0 2006.245.08:22:23.10#ibcon#read 5, iclass 22, count 0 2006.245.08:22:23.10#ibcon#about to read 6, iclass 22, count 0 2006.245.08:22:23.10#ibcon#read 6, iclass 22, count 0 2006.245.08:22:23.10#ibcon#end of sib2, iclass 22, count 0 2006.245.08:22:23.10#ibcon#*after write, iclass 22, count 0 2006.245.08:22:23.10#ibcon#*before return 0, iclass 22, count 0 2006.245.08:22:23.10#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:23.10#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:23.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:22:23.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:22:23.10$vc4f8/valo=4,832.99 2006.245.08:22:23.10#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:22:23.10#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:22:23.10#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:23.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:23.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:23.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:23.10#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:22:23.10#ibcon#first serial, iclass 24, count 0 2006.245.08:22:23.10#ibcon#enter sib2, iclass 24, count 0 2006.245.08:22:23.10#ibcon#flushed, iclass 24, count 0 2006.245.08:22:23.10#ibcon#about to write, iclass 24, count 0 2006.245.08:22:23.10#ibcon#wrote, iclass 24, count 0 2006.245.08:22:23.10#ibcon#about to read 3, iclass 24, count 0 2006.245.08:22:23.12#ibcon#read 3, iclass 24, count 0 2006.245.08:22:23.12#ibcon#about to read 4, iclass 24, count 0 2006.245.08:22:23.12#ibcon#read 4, iclass 24, count 0 2006.245.08:22:23.12#ibcon#about to read 5, iclass 24, count 0 2006.245.08:22:23.12#ibcon#read 5, iclass 24, count 0 2006.245.08:22:23.12#ibcon#about to read 6, iclass 24, count 0 2006.245.08:22:23.12#ibcon#read 6, iclass 24, count 0 2006.245.08:22:23.12#ibcon#end of sib2, iclass 24, count 0 2006.245.08:22:23.12#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:22:23.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:22:23.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:22:23.12#ibcon#*before write, iclass 24, count 0 2006.245.08:22:23.12#ibcon#enter sib2, iclass 24, count 0 2006.245.08:22:23.12#ibcon#flushed, iclass 24, count 0 2006.245.08:22:23.12#ibcon#about to write, iclass 24, count 0 2006.245.08:22:23.12#ibcon#wrote, iclass 24, count 0 2006.245.08:22:23.12#ibcon#about to read 3, iclass 24, count 0 2006.245.08:22:23.16#ibcon#read 3, iclass 24, count 0 2006.245.08:22:23.16#ibcon#about to read 4, iclass 24, count 0 2006.245.08:22:23.16#ibcon#read 4, iclass 24, count 0 2006.245.08:22:23.16#ibcon#about to read 5, iclass 24, count 0 2006.245.08:22:23.16#ibcon#read 5, iclass 24, count 0 2006.245.08:22:23.16#ibcon#about to read 6, iclass 24, count 0 2006.245.08:22:23.16#ibcon#read 6, iclass 24, count 0 2006.245.08:22:23.16#ibcon#end of sib2, iclass 24, count 0 2006.245.08:22:23.16#ibcon#*after write, iclass 24, count 0 2006.245.08:22:23.16#ibcon#*before return 0, iclass 24, count 0 2006.245.08:22:23.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:23.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:23.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:22:23.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:22:23.16$vc4f8/va=4,7 2006.245.08:22:23.16#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.08:22:23.16#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.08:22:23.16#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:23.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:23.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:23.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:23.22#ibcon#enter wrdev, iclass 26, count 2 2006.245.08:22:23.22#ibcon#first serial, iclass 26, count 2 2006.245.08:22:23.22#ibcon#enter sib2, iclass 26, count 2 2006.245.08:22:23.22#ibcon#flushed, iclass 26, count 2 2006.245.08:22:23.22#ibcon#about to write, iclass 26, count 2 2006.245.08:22:23.22#ibcon#wrote, iclass 26, count 2 2006.245.08:22:23.22#ibcon#about to read 3, iclass 26, count 2 2006.245.08:22:23.24#ibcon#read 3, iclass 26, count 2 2006.245.08:22:23.24#ibcon#about to read 4, iclass 26, count 2 2006.245.08:22:23.24#ibcon#read 4, iclass 26, count 2 2006.245.08:22:23.24#ibcon#about to read 5, iclass 26, count 2 2006.245.08:22:23.24#ibcon#read 5, iclass 26, count 2 2006.245.08:22:23.24#ibcon#about to read 6, iclass 26, count 2 2006.245.08:22:23.24#ibcon#read 6, iclass 26, count 2 2006.245.08:22:23.24#ibcon#end of sib2, iclass 26, count 2 2006.245.08:22:23.24#ibcon#*mode == 0, iclass 26, count 2 2006.245.08:22:23.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.08:22:23.24#ibcon#[25=AT04-07\r\n] 2006.245.08:22:23.24#ibcon#*before write, iclass 26, count 2 2006.245.08:22:23.24#ibcon#enter sib2, iclass 26, count 2 2006.245.08:22:23.24#ibcon#flushed, iclass 26, count 2 2006.245.08:22:23.24#ibcon#about to write, iclass 26, count 2 2006.245.08:22:23.24#ibcon#wrote, iclass 26, count 2 2006.245.08:22:23.24#ibcon#about to read 3, iclass 26, count 2 2006.245.08:22:23.27#ibcon#read 3, iclass 26, count 2 2006.245.08:22:23.27#ibcon#about to read 4, iclass 26, count 2 2006.245.08:22:23.27#ibcon#read 4, iclass 26, count 2 2006.245.08:22:23.27#ibcon#about to read 5, iclass 26, count 2 2006.245.08:22:23.27#ibcon#read 5, iclass 26, count 2 2006.245.08:22:23.27#ibcon#about to read 6, iclass 26, count 2 2006.245.08:22:23.27#ibcon#read 6, iclass 26, count 2 2006.245.08:22:23.27#ibcon#end of sib2, iclass 26, count 2 2006.245.08:22:23.27#ibcon#*after write, iclass 26, count 2 2006.245.08:22:23.27#ibcon#*before return 0, iclass 26, count 2 2006.245.08:22:23.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:23.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:23.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.08:22:23.27#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:23.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:23.39#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:23.39#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:23.39#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:22:23.39#ibcon#first serial, iclass 26, count 0 2006.245.08:22:23.39#ibcon#enter sib2, iclass 26, count 0 2006.245.08:22:23.39#ibcon#flushed, iclass 26, count 0 2006.245.08:22:23.39#ibcon#about to write, iclass 26, count 0 2006.245.08:22:23.39#ibcon#wrote, iclass 26, count 0 2006.245.08:22:23.39#ibcon#about to read 3, iclass 26, count 0 2006.245.08:22:23.41#ibcon#read 3, iclass 26, count 0 2006.245.08:22:23.41#ibcon#about to read 4, iclass 26, count 0 2006.245.08:22:23.41#ibcon#read 4, iclass 26, count 0 2006.245.08:22:23.41#ibcon#about to read 5, iclass 26, count 0 2006.245.08:22:23.41#ibcon#read 5, iclass 26, count 0 2006.245.08:22:23.41#ibcon#about to read 6, iclass 26, count 0 2006.245.08:22:23.41#ibcon#read 6, iclass 26, count 0 2006.245.08:22:23.41#ibcon#end of sib2, iclass 26, count 0 2006.245.08:22:23.41#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:22:23.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:22:23.41#ibcon#[25=USB\r\n] 2006.245.08:22:23.41#ibcon#*before write, iclass 26, count 0 2006.245.08:22:23.41#ibcon#enter sib2, iclass 26, count 0 2006.245.08:22:23.41#ibcon#flushed, iclass 26, count 0 2006.245.08:22:23.41#ibcon#about to write, iclass 26, count 0 2006.245.08:22:23.41#ibcon#wrote, iclass 26, count 0 2006.245.08:22:23.41#ibcon#about to read 3, iclass 26, count 0 2006.245.08:22:23.44#ibcon#read 3, iclass 26, count 0 2006.245.08:22:23.44#ibcon#about to read 4, iclass 26, count 0 2006.245.08:22:23.44#ibcon#read 4, iclass 26, count 0 2006.245.08:22:23.44#ibcon#about to read 5, iclass 26, count 0 2006.245.08:22:23.44#ibcon#read 5, iclass 26, count 0 2006.245.08:22:23.44#ibcon#about to read 6, iclass 26, count 0 2006.245.08:22:23.44#ibcon#read 6, iclass 26, count 0 2006.245.08:22:23.44#ibcon#end of sib2, iclass 26, count 0 2006.245.08:22:23.44#ibcon#*after write, iclass 26, count 0 2006.245.08:22:23.44#ibcon#*before return 0, iclass 26, count 0 2006.245.08:22:23.44#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:23.44#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:23.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:22:23.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:22:23.44$vc4f8/valo=5,652.99 2006.245.08:22:23.44#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.08:22:23.44#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.08:22:23.44#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:23.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:23.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:23.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:23.44#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:22:23.44#ibcon#first serial, iclass 28, count 0 2006.245.08:22:23.44#ibcon#enter sib2, iclass 28, count 0 2006.245.08:22:23.44#ibcon#flushed, iclass 28, count 0 2006.245.08:22:23.44#ibcon#about to write, iclass 28, count 0 2006.245.08:22:23.44#ibcon#wrote, iclass 28, count 0 2006.245.08:22:23.44#ibcon#about to read 3, iclass 28, count 0 2006.245.08:22:23.46#ibcon#read 3, iclass 28, count 0 2006.245.08:22:23.46#ibcon#about to read 4, iclass 28, count 0 2006.245.08:22:23.46#ibcon#read 4, iclass 28, count 0 2006.245.08:22:23.46#ibcon#about to read 5, iclass 28, count 0 2006.245.08:22:23.46#ibcon#read 5, iclass 28, count 0 2006.245.08:22:23.46#ibcon#about to read 6, iclass 28, count 0 2006.245.08:22:23.46#ibcon#read 6, iclass 28, count 0 2006.245.08:22:23.46#ibcon#end of sib2, iclass 28, count 0 2006.245.08:22:23.46#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:22:23.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:22:23.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:22:23.46#ibcon#*before write, iclass 28, count 0 2006.245.08:22:23.46#ibcon#enter sib2, iclass 28, count 0 2006.245.08:22:23.46#ibcon#flushed, iclass 28, count 0 2006.245.08:22:23.46#ibcon#about to write, iclass 28, count 0 2006.245.08:22:23.46#ibcon#wrote, iclass 28, count 0 2006.245.08:22:23.46#ibcon#about to read 3, iclass 28, count 0 2006.245.08:22:23.50#ibcon#read 3, iclass 28, count 0 2006.245.08:22:23.50#ibcon#about to read 4, iclass 28, count 0 2006.245.08:22:23.50#ibcon#read 4, iclass 28, count 0 2006.245.08:22:23.50#ibcon#about to read 5, iclass 28, count 0 2006.245.08:22:23.50#ibcon#read 5, iclass 28, count 0 2006.245.08:22:23.50#ibcon#about to read 6, iclass 28, count 0 2006.245.08:22:23.50#ibcon#read 6, iclass 28, count 0 2006.245.08:22:23.50#ibcon#end of sib2, iclass 28, count 0 2006.245.08:22:23.50#ibcon#*after write, iclass 28, count 0 2006.245.08:22:23.50#ibcon#*before return 0, iclass 28, count 0 2006.245.08:22:23.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:23.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:23.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:22:23.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:22:23.50$vc4f8/va=5,7 2006.245.08:22:23.50#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.08:22:23.50#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.08:22:23.50#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:23.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:23.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:23.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:23.56#ibcon#enter wrdev, iclass 30, count 2 2006.245.08:22:23.56#ibcon#first serial, iclass 30, count 2 2006.245.08:22:23.56#ibcon#enter sib2, iclass 30, count 2 2006.245.08:22:23.56#ibcon#flushed, iclass 30, count 2 2006.245.08:22:23.56#ibcon#about to write, iclass 30, count 2 2006.245.08:22:23.56#ibcon#wrote, iclass 30, count 2 2006.245.08:22:23.56#ibcon#about to read 3, iclass 30, count 2 2006.245.08:22:23.58#ibcon#read 3, iclass 30, count 2 2006.245.08:22:23.58#ibcon#about to read 4, iclass 30, count 2 2006.245.08:22:23.58#ibcon#read 4, iclass 30, count 2 2006.245.08:22:23.58#ibcon#about to read 5, iclass 30, count 2 2006.245.08:22:23.58#ibcon#read 5, iclass 30, count 2 2006.245.08:22:23.58#ibcon#about to read 6, iclass 30, count 2 2006.245.08:22:23.58#ibcon#read 6, iclass 30, count 2 2006.245.08:22:23.58#ibcon#end of sib2, iclass 30, count 2 2006.245.08:22:23.58#ibcon#*mode == 0, iclass 30, count 2 2006.245.08:22:23.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.08:22:23.58#ibcon#[25=AT05-07\r\n] 2006.245.08:22:23.58#ibcon#*before write, iclass 30, count 2 2006.245.08:22:23.58#ibcon#enter sib2, iclass 30, count 2 2006.245.08:22:23.58#ibcon#flushed, iclass 30, count 2 2006.245.08:22:23.58#ibcon#about to write, iclass 30, count 2 2006.245.08:22:23.58#ibcon#wrote, iclass 30, count 2 2006.245.08:22:23.58#ibcon#about to read 3, iclass 30, count 2 2006.245.08:22:23.61#ibcon#read 3, iclass 30, count 2 2006.245.08:22:23.61#ibcon#about to read 4, iclass 30, count 2 2006.245.08:22:23.61#ibcon#read 4, iclass 30, count 2 2006.245.08:22:23.61#ibcon#about to read 5, iclass 30, count 2 2006.245.08:22:23.61#ibcon#read 5, iclass 30, count 2 2006.245.08:22:23.61#ibcon#about to read 6, iclass 30, count 2 2006.245.08:22:23.61#ibcon#read 6, iclass 30, count 2 2006.245.08:22:23.61#ibcon#end of sib2, iclass 30, count 2 2006.245.08:22:23.61#ibcon#*after write, iclass 30, count 2 2006.245.08:22:23.61#ibcon#*before return 0, iclass 30, count 2 2006.245.08:22:23.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:23.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:23.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.08:22:23.61#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:23.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:23.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:23.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:23.73#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:22:23.73#ibcon#first serial, iclass 30, count 0 2006.245.08:22:23.73#ibcon#enter sib2, iclass 30, count 0 2006.245.08:22:23.73#ibcon#flushed, iclass 30, count 0 2006.245.08:22:23.73#ibcon#about to write, iclass 30, count 0 2006.245.08:22:23.73#ibcon#wrote, iclass 30, count 0 2006.245.08:22:23.73#ibcon#about to read 3, iclass 30, count 0 2006.245.08:22:23.75#ibcon#read 3, iclass 30, count 0 2006.245.08:22:23.75#ibcon#about to read 4, iclass 30, count 0 2006.245.08:22:23.75#ibcon#read 4, iclass 30, count 0 2006.245.08:22:23.75#ibcon#about to read 5, iclass 30, count 0 2006.245.08:22:23.75#ibcon#read 5, iclass 30, count 0 2006.245.08:22:23.75#ibcon#about to read 6, iclass 30, count 0 2006.245.08:22:23.75#ibcon#read 6, iclass 30, count 0 2006.245.08:22:23.75#ibcon#end of sib2, iclass 30, count 0 2006.245.08:22:23.75#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:22:23.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:22:23.75#ibcon#[25=USB\r\n] 2006.245.08:22:23.75#ibcon#*before write, iclass 30, count 0 2006.245.08:22:23.75#ibcon#enter sib2, iclass 30, count 0 2006.245.08:22:23.75#ibcon#flushed, iclass 30, count 0 2006.245.08:22:23.75#ibcon#about to write, iclass 30, count 0 2006.245.08:22:23.75#ibcon#wrote, iclass 30, count 0 2006.245.08:22:23.75#ibcon#about to read 3, iclass 30, count 0 2006.245.08:22:23.78#ibcon#read 3, iclass 30, count 0 2006.245.08:22:23.78#ibcon#about to read 4, iclass 30, count 0 2006.245.08:22:23.78#ibcon#read 4, iclass 30, count 0 2006.245.08:22:23.78#ibcon#about to read 5, iclass 30, count 0 2006.245.08:22:23.78#ibcon#read 5, iclass 30, count 0 2006.245.08:22:23.78#ibcon#about to read 6, iclass 30, count 0 2006.245.08:22:23.78#ibcon#read 6, iclass 30, count 0 2006.245.08:22:23.78#ibcon#end of sib2, iclass 30, count 0 2006.245.08:22:23.78#ibcon#*after write, iclass 30, count 0 2006.245.08:22:23.78#ibcon#*before return 0, iclass 30, count 0 2006.245.08:22:23.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:23.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:23.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:22:23.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:22:23.78$vc4f8/valo=6,772.99 2006.245.08:22:23.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.08:22:23.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.08:22:23.78#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:23.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:23.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:23.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:23.78#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:22:23.78#ibcon#first serial, iclass 32, count 0 2006.245.08:22:23.78#ibcon#enter sib2, iclass 32, count 0 2006.245.08:22:23.78#ibcon#flushed, iclass 32, count 0 2006.245.08:22:23.78#ibcon#about to write, iclass 32, count 0 2006.245.08:22:23.78#ibcon#wrote, iclass 32, count 0 2006.245.08:22:23.78#ibcon#about to read 3, iclass 32, count 0 2006.245.08:22:23.80#ibcon#read 3, iclass 32, count 0 2006.245.08:22:23.80#ibcon#about to read 4, iclass 32, count 0 2006.245.08:22:23.80#ibcon#read 4, iclass 32, count 0 2006.245.08:22:23.80#ibcon#about to read 5, iclass 32, count 0 2006.245.08:22:23.80#ibcon#read 5, iclass 32, count 0 2006.245.08:22:23.80#ibcon#about to read 6, iclass 32, count 0 2006.245.08:22:23.80#ibcon#read 6, iclass 32, count 0 2006.245.08:22:23.80#ibcon#end of sib2, iclass 32, count 0 2006.245.08:22:23.80#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:22:23.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:22:23.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:22:23.80#ibcon#*before write, iclass 32, count 0 2006.245.08:22:23.80#ibcon#enter sib2, iclass 32, count 0 2006.245.08:22:23.80#ibcon#flushed, iclass 32, count 0 2006.245.08:22:23.80#ibcon#about to write, iclass 32, count 0 2006.245.08:22:23.80#ibcon#wrote, iclass 32, count 0 2006.245.08:22:23.80#ibcon#about to read 3, iclass 32, count 0 2006.245.08:22:23.84#ibcon#read 3, iclass 32, count 0 2006.245.08:22:23.84#ibcon#about to read 4, iclass 32, count 0 2006.245.08:22:23.84#ibcon#read 4, iclass 32, count 0 2006.245.08:22:23.84#ibcon#about to read 5, iclass 32, count 0 2006.245.08:22:23.84#ibcon#read 5, iclass 32, count 0 2006.245.08:22:23.84#ibcon#about to read 6, iclass 32, count 0 2006.245.08:22:23.84#ibcon#read 6, iclass 32, count 0 2006.245.08:22:23.84#ibcon#end of sib2, iclass 32, count 0 2006.245.08:22:23.84#ibcon#*after write, iclass 32, count 0 2006.245.08:22:23.84#ibcon#*before return 0, iclass 32, count 0 2006.245.08:22:23.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:23.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:23.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:22:23.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:22:23.84$vc4f8/va=6,7 2006.245.08:22:23.84#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.245.08:22:23.84#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.245.08:22:23.84#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:23.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:22:23.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:22:23.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:22:23.90#ibcon#enter wrdev, iclass 34, count 2 2006.245.08:22:23.90#ibcon#first serial, iclass 34, count 2 2006.245.08:22:23.90#ibcon#enter sib2, iclass 34, count 2 2006.245.08:22:23.90#ibcon#flushed, iclass 34, count 2 2006.245.08:22:23.90#ibcon#about to write, iclass 34, count 2 2006.245.08:22:23.90#ibcon#wrote, iclass 34, count 2 2006.245.08:22:23.90#ibcon#about to read 3, iclass 34, count 2 2006.245.08:22:23.92#ibcon#read 3, iclass 34, count 2 2006.245.08:22:23.92#ibcon#about to read 4, iclass 34, count 2 2006.245.08:22:23.92#ibcon#read 4, iclass 34, count 2 2006.245.08:22:23.92#ibcon#about to read 5, iclass 34, count 2 2006.245.08:22:23.92#ibcon#read 5, iclass 34, count 2 2006.245.08:22:23.92#ibcon#about to read 6, iclass 34, count 2 2006.245.08:22:23.92#ibcon#read 6, iclass 34, count 2 2006.245.08:22:23.92#ibcon#end of sib2, iclass 34, count 2 2006.245.08:22:23.92#ibcon#*mode == 0, iclass 34, count 2 2006.245.08:22:23.92#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.245.08:22:23.92#ibcon#[25=AT06-07\r\n] 2006.245.08:22:23.92#ibcon#*before write, iclass 34, count 2 2006.245.08:22:23.92#ibcon#enter sib2, iclass 34, count 2 2006.245.08:22:23.92#ibcon#flushed, iclass 34, count 2 2006.245.08:22:23.92#ibcon#about to write, iclass 34, count 2 2006.245.08:22:23.92#ibcon#wrote, iclass 34, count 2 2006.245.08:22:23.92#ibcon#about to read 3, iclass 34, count 2 2006.245.08:22:23.95#ibcon#read 3, iclass 34, count 2 2006.245.08:22:23.95#ibcon#about to read 4, iclass 34, count 2 2006.245.08:22:23.95#ibcon#read 4, iclass 34, count 2 2006.245.08:22:23.95#ibcon#about to read 5, iclass 34, count 2 2006.245.08:22:23.95#ibcon#read 5, iclass 34, count 2 2006.245.08:22:23.95#ibcon#about to read 6, iclass 34, count 2 2006.245.08:22:23.95#ibcon#read 6, iclass 34, count 2 2006.245.08:22:23.95#ibcon#end of sib2, iclass 34, count 2 2006.245.08:22:23.95#ibcon#*after write, iclass 34, count 2 2006.245.08:22:23.95#ibcon#*before return 0, iclass 34, count 2 2006.245.08:22:23.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:22:23.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.245.08:22:23.95#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.245.08:22:23.95#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:23.95#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:22:24.07#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:22:24.07#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:22:24.07#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:22:24.07#ibcon#first serial, iclass 34, count 0 2006.245.08:22:24.07#ibcon#enter sib2, iclass 34, count 0 2006.245.08:22:24.07#ibcon#flushed, iclass 34, count 0 2006.245.08:22:24.07#ibcon#about to write, iclass 34, count 0 2006.245.08:22:24.07#ibcon#wrote, iclass 34, count 0 2006.245.08:22:24.07#ibcon#about to read 3, iclass 34, count 0 2006.245.08:22:24.09#ibcon#read 3, iclass 34, count 0 2006.245.08:22:24.09#ibcon#about to read 4, iclass 34, count 0 2006.245.08:22:24.09#ibcon#read 4, iclass 34, count 0 2006.245.08:22:24.09#ibcon#about to read 5, iclass 34, count 0 2006.245.08:22:24.09#ibcon#read 5, iclass 34, count 0 2006.245.08:22:24.09#ibcon#about to read 6, iclass 34, count 0 2006.245.08:22:24.09#ibcon#read 6, iclass 34, count 0 2006.245.08:22:24.09#ibcon#end of sib2, iclass 34, count 0 2006.245.08:22:24.09#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:22:24.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:22:24.09#ibcon#[25=USB\r\n] 2006.245.08:22:24.09#ibcon#*before write, iclass 34, count 0 2006.245.08:22:24.09#ibcon#enter sib2, iclass 34, count 0 2006.245.08:22:24.09#ibcon#flushed, iclass 34, count 0 2006.245.08:22:24.09#ibcon#about to write, iclass 34, count 0 2006.245.08:22:24.09#ibcon#wrote, iclass 34, count 0 2006.245.08:22:24.09#ibcon#about to read 3, iclass 34, count 0 2006.245.08:22:24.12#ibcon#read 3, iclass 34, count 0 2006.245.08:22:24.12#ibcon#about to read 4, iclass 34, count 0 2006.245.08:22:24.12#ibcon#read 4, iclass 34, count 0 2006.245.08:22:24.12#ibcon#about to read 5, iclass 34, count 0 2006.245.08:22:24.12#ibcon#read 5, iclass 34, count 0 2006.245.08:22:24.12#ibcon#about to read 6, iclass 34, count 0 2006.245.08:22:24.12#ibcon#read 6, iclass 34, count 0 2006.245.08:22:24.12#ibcon#end of sib2, iclass 34, count 0 2006.245.08:22:24.12#ibcon#*after write, iclass 34, count 0 2006.245.08:22:24.12#ibcon#*before return 0, iclass 34, count 0 2006.245.08:22:24.12#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:22:24.12#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.245.08:22:24.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:22:24.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:22:24.12$vc4f8/valo=7,832.99 2006.245.08:22:24.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.245.08:22:24.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.245.08:22:24.12#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:24.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:22:24.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:22:24.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:22:24.12#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:22:24.12#ibcon#first serial, iclass 36, count 0 2006.245.08:22:24.12#ibcon#enter sib2, iclass 36, count 0 2006.245.08:22:24.12#ibcon#flushed, iclass 36, count 0 2006.245.08:22:24.12#ibcon#about to write, iclass 36, count 0 2006.245.08:22:24.12#ibcon#wrote, iclass 36, count 0 2006.245.08:22:24.12#ibcon#about to read 3, iclass 36, count 0 2006.245.08:22:24.14#ibcon#read 3, iclass 36, count 0 2006.245.08:22:24.14#ibcon#about to read 4, iclass 36, count 0 2006.245.08:22:24.14#ibcon#read 4, iclass 36, count 0 2006.245.08:22:24.14#ibcon#about to read 5, iclass 36, count 0 2006.245.08:22:24.14#ibcon#read 5, iclass 36, count 0 2006.245.08:22:24.14#ibcon#about to read 6, iclass 36, count 0 2006.245.08:22:24.14#ibcon#read 6, iclass 36, count 0 2006.245.08:22:24.14#ibcon#end of sib2, iclass 36, count 0 2006.245.08:22:24.14#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:22:24.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:22:24.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:22:24.14#ibcon#*before write, iclass 36, count 0 2006.245.08:22:24.14#ibcon#enter sib2, iclass 36, count 0 2006.245.08:22:24.14#ibcon#flushed, iclass 36, count 0 2006.245.08:22:24.14#ibcon#about to write, iclass 36, count 0 2006.245.08:22:24.14#ibcon#wrote, iclass 36, count 0 2006.245.08:22:24.14#ibcon#about to read 3, iclass 36, count 0 2006.245.08:22:24.18#ibcon#read 3, iclass 36, count 0 2006.245.08:22:24.18#ibcon#about to read 4, iclass 36, count 0 2006.245.08:22:24.18#ibcon#read 4, iclass 36, count 0 2006.245.08:22:24.18#ibcon#about to read 5, iclass 36, count 0 2006.245.08:22:24.18#ibcon#read 5, iclass 36, count 0 2006.245.08:22:24.18#ibcon#about to read 6, iclass 36, count 0 2006.245.08:22:24.18#ibcon#read 6, iclass 36, count 0 2006.245.08:22:24.18#ibcon#end of sib2, iclass 36, count 0 2006.245.08:22:24.18#ibcon#*after write, iclass 36, count 0 2006.245.08:22:24.18#ibcon#*before return 0, iclass 36, count 0 2006.245.08:22:24.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:22:24.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.245.08:22:24.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:22:24.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:22:24.18$vc4f8/va=7,7 2006.245.08:22:24.18#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.245.08:22:24.18#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.245.08:22:24.18#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:24.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:22:24.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:22:24.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:22:24.24#ibcon#enter wrdev, iclass 38, count 2 2006.245.08:22:24.24#ibcon#first serial, iclass 38, count 2 2006.245.08:22:24.24#ibcon#enter sib2, iclass 38, count 2 2006.245.08:22:24.24#ibcon#flushed, iclass 38, count 2 2006.245.08:22:24.24#ibcon#about to write, iclass 38, count 2 2006.245.08:22:24.24#ibcon#wrote, iclass 38, count 2 2006.245.08:22:24.24#ibcon#about to read 3, iclass 38, count 2 2006.245.08:22:24.26#ibcon#read 3, iclass 38, count 2 2006.245.08:22:24.26#ibcon#about to read 4, iclass 38, count 2 2006.245.08:22:24.26#ibcon#read 4, iclass 38, count 2 2006.245.08:22:24.26#ibcon#about to read 5, iclass 38, count 2 2006.245.08:22:24.26#ibcon#read 5, iclass 38, count 2 2006.245.08:22:24.26#ibcon#about to read 6, iclass 38, count 2 2006.245.08:22:24.26#ibcon#read 6, iclass 38, count 2 2006.245.08:22:24.26#ibcon#end of sib2, iclass 38, count 2 2006.245.08:22:24.26#ibcon#*mode == 0, iclass 38, count 2 2006.245.08:22:24.26#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.245.08:22:24.26#ibcon#[25=AT07-07\r\n] 2006.245.08:22:24.26#ibcon#*before write, iclass 38, count 2 2006.245.08:22:24.26#ibcon#enter sib2, iclass 38, count 2 2006.245.08:22:24.26#ibcon#flushed, iclass 38, count 2 2006.245.08:22:24.26#ibcon#about to write, iclass 38, count 2 2006.245.08:22:24.26#ibcon#wrote, iclass 38, count 2 2006.245.08:22:24.26#ibcon#about to read 3, iclass 38, count 2 2006.245.08:22:24.29#ibcon#read 3, iclass 38, count 2 2006.245.08:22:24.29#ibcon#about to read 4, iclass 38, count 2 2006.245.08:22:24.29#ibcon#read 4, iclass 38, count 2 2006.245.08:22:24.29#ibcon#about to read 5, iclass 38, count 2 2006.245.08:22:24.29#ibcon#read 5, iclass 38, count 2 2006.245.08:22:24.29#ibcon#about to read 6, iclass 38, count 2 2006.245.08:22:24.29#ibcon#read 6, iclass 38, count 2 2006.245.08:22:24.29#ibcon#end of sib2, iclass 38, count 2 2006.245.08:22:24.29#ibcon#*after write, iclass 38, count 2 2006.245.08:22:24.29#ibcon#*before return 0, iclass 38, count 2 2006.245.08:22:24.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:22:24.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.245.08:22:24.29#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.245.08:22:24.29#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:24.29#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:22:24.41#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:22:24.41#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:22:24.41#ibcon#enter wrdev, iclass 38, count 0 2006.245.08:22:24.41#ibcon#first serial, iclass 38, count 0 2006.245.08:22:24.41#ibcon#enter sib2, iclass 38, count 0 2006.245.08:22:24.41#ibcon#flushed, iclass 38, count 0 2006.245.08:22:24.41#ibcon#about to write, iclass 38, count 0 2006.245.08:22:24.41#ibcon#wrote, iclass 38, count 0 2006.245.08:22:24.41#ibcon#about to read 3, iclass 38, count 0 2006.245.08:22:24.43#ibcon#read 3, iclass 38, count 0 2006.245.08:22:24.43#ibcon#about to read 4, iclass 38, count 0 2006.245.08:22:24.43#ibcon#read 4, iclass 38, count 0 2006.245.08:22:24.43#ibcon#about to read 5, iclass 38, count 0 2006.245.08:22:24.43#ibcon#read 5, iclass 38, count 0 2006.245.08:22:24.43#ibcon#about to read 6, iclass 38, count 0 2006.245.08:22:24.43#ibcon#read 6, iclass 38, count 0 2006.245.08:22:24.43#ibcon#end of sib2, iclass 38, count 0 2006.245.08:22:24.43#ibcon#*mode == 0, iclass 38, count 0 2006.245.08:22:24.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.245.08:22:24.43#ibcon#[25=USB\r\n] 2006.245.08:22:24.43#ibcon#*before write, iclass 38, count 0 2006.245.08:22:24.43#ibcon#enter sib2, iclass 38, count 0 2006.245.08:22:24.43#ibcon#flushed, iclass 38, count 0 2006.245.08:22:24.43#ibcon#about to write, iclass 38, count 0 2006.245.08:22:24.43#ibcon#wrote, iclass 38, count 0 2006.245.08:22:24.43#ibcon#about to read 3, iclass 38, count 0 2006.245.08:22:24.46#ibcon#read 3, iclass 38, count 0 2006.245.08:22:24.46#ibcon#about to read 4, iclass 38, count 0 2006.245.08:22:24.46#ibcon#read 4, iclass 38, count 0 2006.245.08:22:24.46#ibcon#about to read 5, iclass 38, count 0 2006.245.08:22:24.46#ibcon#read 5, iclass 38, count 0 2006.245.08:22:24.46#ibcon#about to read 6, iclass 38, count 0 2006.245.08:22:24.46#ibcon#read 6, iclass 38, count 0 2006.245.08:22:24.46#ibcon#end of sib2, iclass 38, count 0 2006.245.08:22:24.46#ibcon#*after write, iclass 38, count 0 2006.245.08:22:24.46#ibcon#*before return 0, iclass 38, count 0 2006.245.08:22:24.46#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:22:24.46#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.245.08:22:24.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.245.08:22:24.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.245.08:22:24.46$vc4f8/valo=8,852.99 2006.245.08:22:24.46#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.245.08:22:24.46#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.245.08:22:24.46#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:24.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:22:24.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:22:24.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:22:24.46#ibcon#enter wrdev, iclass 40, count 0 2006.245.08:22:24.46#ibcon#first serial, iclass 40, count 0 2006.245.08:22:24.46#ibcon#enter sib2, iclass 40, count 0 2006.245.08:22:24.46#ibcon#flushed, iclass 40, count 0 2006.245.08:22:24.46#ibcon#about to write, iclass 40, count 0 2006.245.08:22:24.46#ibcon#wrote, iclass 40, count 0 2006.245.08:22:24.46#ibcon#about to read 3, iclass 40, count 0 2006.245.08:22:24.48#ibcon#read 3, iclass 40, count 0 2006.245.08:22:24.48#ibcon#about to read 4, iclass 40, count 0 2006.245.08:22:24.48#ibcon#read 4, iclass 40, count 0 2006.245.08:22:24.48#ibcon#about to read 5, iclass 40, count 0 2006.245.08:22:24.48#ibcon#read 5, iclass 40, count 0 2006.245.08:22:24.48#ibcon#about to read 6, iclass 40, count 0 2006.245.08:22:24.48#ibcon#read 6, iclass 40, count 0 2006.245.08:22:24.48#ibcon#end of sib2, iclass 40, count 0 2006.245.08:22:24.48#ibcon#*mode == 0, iclass 40, count 0 2006.245.08:22:24.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.245.08:22:24.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:22:24.48#ibcon#*before write, iclass 40, count 0 2006.245.08:22:24.48#ibcon#enter sib2, iclass 40, count 0 2006.245.08:22:24.48#ibcon#flushed, iclass 40, count 0 2006.245.08:22:24.48#ibcon#about to write, iclass 40, count 0 2006.245.08:22:24.48#ibcon#wrote, iclass 40, count 0 2006.245.08:22:24.48#ibcon#about to read 3, iclass 40, count 0 2006.245.08:22:24.52#ibcon#read 3, iclass 40, count 0 2006.245.08:22:24.52#ibcon#about to read 4, iclass 40, count 0 2006.245.08:22:24.52#ibcon#read 4, iclass 40, count 0 2006.245.08:22:24.52#ibcon#about to read 5, iclass 40, count 0 2006.245.08:22:24.52#ibcon#read 5, iclass 40, count 0 2006.245.08:22:24.52#ibcon#about to read 6, iclass 40, count 0 2006.245.08:22:24.52#ibcon#read 6, iclass 40, count 0 2006.245.08:22:24.52#ibcon#end of sib2, iclass 40, count 0 2006.245.08:22:24.52#ibcon#*after write, iclass 40, count 0 2006.245.08:22:24.52#ibcon#*before return 0, iclass 40, count 0 2006.245.08:22:24.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:22:24.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.245.08:22:24.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.245.08:22:24.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.245.08:22:24.52$vc4f8/va=8,8 2006.245.08:22:24.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.245.08:22:24.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.245.08:22:24.52#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:24.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:22:24.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:22:24.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:22:24.58#ibcon#enter wrdev, iclass 4, count 2 2006.245.08:22:24.58#ibcon#first serial, iclass 4, count 2 2006.245.08:22:24.58#ibcon#enter sib2, iclass 4, count 2 2006.245.08:22:24.58#ibcon#flushed, iclass 4, count 2 2006.245.08:22:24.58#ibcon#about to write, iclass 4, count 2 2006.245.08:22:24.58#ibcon#wrote, iclass 4, count 2 2006.245.08:22:24.58#ibcon#about to read 3, iclass 4, count 2 2006.245.08:22:24.60#ibcon#read 3, iclass 4, count 2 2006.245.08:22:24.60#ibcon#about to read 4, iclass 4, count 2 2006.245.08:22:24.60#ibcon#read 4, iclass 4, count 2 2006.245.08:22:24.60#ibcon#about to read 5, iclass 4, count 2 2006.245.08:22:24.60#ibcon#read 5, iclass 4, count 2 2006.245.08:22:24.60#ibcon#about to read 6, iclass 4, count 2 2006.245.08:22:24.60#ibcon#read 6, iclass 4, count 2 2006.245.08:22:24.60#ibcon#end of sib2, iclass 4, count 2 2006.245.08:22:24.60#ibcon#*mode == 0, iclass 4, count 2 2006.245.08:22:24.60#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.245.08:22:24.60#ibcon#[25=AT08-08\r\n] 2006.245.08:22:24.60#ibcon#*before write, iclass 4, count 2 2006.245.08:22:24.60#ibcon#enter sib2, iclass 4, count 2 2006.245.08:22:24.60#ibcon#flushed, iclass 4, count 2 2006.245.08:22:24.60#ibcon#about to write, iclass 4, count 2 2006.245.08:22:24.60#ibcon#wrote, iclass 4, count 2 2006.245.08:22:24.60#ibcon#about to read 3, iclass 4, count 2 2006.245.08:22:24.63#ibcon#read 3, iclass 4, count 2 2006.245.08:22:24.63#ibcon#about to read 4, iclass 4, count 2 2006.245.08:22:24.63#ibcon#read 4, iclass 4, count 2 2006.245.08:22:24.63#ibcon#about to read 5, iclass 4, count 2 2006.245.08:22:24.63#ibcon#read 5, iclass 4, count 2 2006.245.08:22:24.63#ibcon#about to read 6, iclass 4, count 2 2006.245.08:22:24.63#ibcon#read 6, iclass 4, count 2 2006.245.08:22:24.63#ibcon#end of sib2, iclass 4, count 2 2006.245.08:22:24.63#ibcon#*after write, iclass 4, count 2 2006.245.08:22:24.63#ibcon#*before return 0, iclass 4, count 2 2006.245.08:22:24.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:22:24.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.245.08:22:24.63#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.245.08:22:24.63#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:24.63#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:22:24.75#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:22:24.75#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:22:24.75#ibcon#enter wrdev, iclass 4, count 0 2006.245.08:22:24.75#ibcon#first serial, iclass 4, count 0 2006.245.08:22:24.75#ibcon#enter sib2, iclass 4, count 0 2006.245.08:22:24.75#ibcon#flushed, iclass 4, count 0 2006.245.08:22:24.75#ibcon#about to write, iclass 4, count 0 2006.245.08:22:24.75#ibcon#wrote, iclass 4, count 0 2006.245.08:22:24.75#ibcon#about to read 3, iclass 4, count 0 2006.245.08:22:24.77#ibcon#read 3, iclass 4, count 0 2006.245.08:22:24.77#ibcon#about to read 4, iclass 4, count 0 2006.245.08:22:24.77#ibcon#read 4, iclass 4, count 0 2006.245.08:22:24.77#ibcon#about to read 5, iclass 4, count 0 2006.245.08:22:24.77#ibcon#read 5, iclass 4, count 0 2006.245.08:22:24.77#ibcon#about to read 6, iclass 4, count 0 2006.245.08:22:24.77#ibcon#read 6, iclass 4, count 0 2006.245.08:22:24.77#ibcon#end of sib2, iclass 4, count 0 2006.245.08:22:24.77#ibcon#*mode == 0, iclass 4, count 0 2006.245.08:22:24.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.245.08:22:24.77#ibcon#[25=USB\r\n] 2006.245.08:22:24.77#ibcon#*before write, iclass 4, count 0 2006.245.08:22:24.77#ibcon#enter sib2, iclass 4, count 0 2006.245.08:22:24.77#ibcon#flushed, iclass 4, count 0 2006.245.08:22:24.77#ibcon#about to write, iclass 4, count 0 2006.245.08:22:24.77#ibcon#wrote, iclass 4, count 0 2006.245.08:22:24.77#ibcon#about to read 3, iclass 4, count 0 2006.245.08:22:24.80#ibcon#read 3, iclass 4, count 0 2006.245.08:22:24.80#ibcon#about to read 4, iclass 4, count 0 2006.245.08:22:24.80#ibcon#read 4, iclass 4, count 0 2006.245.08:22:24.80#ibcon#about to read 5, iclass 4, count 0 2006.245.08:22:24.80#ibcon#read 5, iclass 4, count 0 2006.245.08:22:24.80#ibcon#about to read 6, iclass 4, count 0 2006.245.08:22:24.80#ibcon#read 6, iclass 4, count 0 2006.245.08:22:24.80#ibcon#end of sib2, iclass 4, count 0 2006.245.08:22:24.80#ibcon#*after write, iclass 4, count 0 2006.245.08:22:24.80#ibcon#*before return 0, iclass 4, count 0 2006.245.08:22:24.80#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:22:24.80#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.245.08:22:24.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.245.08:22:24.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.245.08:22:24.80$vc4f8/vblo=1,632.99 2006.245.08:22:24.80#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.245.08:22:24.80#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.245.08:22:24.80#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:24.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:22:24.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:22:24.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:22:24.80#ibcon#enter wrdev, iclass 6, count 0 2006.245.08:22:24.80#ibcon#first serial, iclass 6, count 0 2006.245.08:22:24.80#ibcon#enter sib2, iclass 6, count 0 2006.245.08:22:24.80#ibcon#flushed, iclass 6, count 0 2006.245.08:22:24.80#ibcon#about to write, iclass 6, count 0 2006.245.08:22:24.80#ibcon#wrote, iclass 6, count 0 2006.245.08:22:24.80#ibcon#about to read 3, iclass 6, count 0 2006.245.08:22:24.82#ibcon#read 3, iclass 6, count 0 2006.245.08:22:24.82#ibcon#about to read 4, iclass 6, count 0 2006.245.08:22:24.82#ibcon#read 4, iclass 6, count 0 2006.245.08:22:24.82#ibcon#about to read 5, iclass 6, count 0 2006.245.08:22:24.82#ibcon#read 5, iclass 6, count 0 2006.245.08:22:24.82#ibcon#about to read 6, iclass 6, count 0 2006.245.08:22:24.82#ibcon#read 6, iclass 6, count 0 2006.245.08:22:24.82#ibcon#end of sib2, iclass 6, count 0 2006.245.08:22:24.82#ibcon#*mode == 0, iclass 6, count 0 2006.245.08:22:24.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.245.08:22:24.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:22:24.82#ibcon#*before write, iclass 6, count 0 2006.245.08:22:24.82#ibcon#enter sib2, iclass 6, count 0 2006.245.08:22:24.82#ibcon#flushed, iclass 6, count 0 2006.245.08:22:24.82#ibcon#about to write, iclass 6, count 0 2006.245.08:22:24.82#ibcon#wrote, iclass 6, count 0 2006.245.08:22:24.82#ibcon#about to read 3, iclass 6, count 0 2006.245.08:22:24.86#ibcon#read 3, iclass 6, count 0 2006.245.08:22:24.86#ibcon#about to read 4, iclass 6, count 0 2006.245.08:22:24.86#ibcon#read 4, iclass 6, count 0 2006.245.08:22:24.86#ibcon#about to read 5, iclass 6, count 0 2006.245.08:22:24.86#ibcon#read 5, iclass 6, count 0 2006.245.08:22:24.86#ibcon#about to read 6, iclass 6, count 0 2006.245.08:22:24.86#ibcon#read 6, iclass 6, count 0 2006.245.08:22:24.86#ibcon#end of sib2, iclass 6, count 0 2006.245.08:22:24.86#ibcon#*after write, iclass 6, count 0 2006.245.08:22:24.86#ibcon#*before return 0, iclass 6, count 0 2006.245.08:22:24.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:22:24.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.245.08:22:24.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.245.08:22:24.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.245.08:22:24.86$vc4f8/vb=1,4 2006.245.08:22:24.86#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.245.08:22:24.86#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.245.08:22:24.86#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:24.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:22:24.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:22:24.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:22:24.86#ibcon#enter wrdev, iclass 10, count 2 2006.245.08:22:24.86#ibcon#first serial, iclass 10, count 2 2006.245.08:22:24.86#ibcon#enter sib2, iclass 10, count 2 2006.245.08:22:24.86#ibcon#flushed, iclass 10, count 2 2006.245.08:22:24.86#ibcon#about to write, iclass 10, count 2 2006.245.08:22:24.86#ibcon#wrote, iclass 10, count 2 2006.245.08:22:24.86#ibcon#about to read 3, iclass 10, count 2 2006.245.08:22:24.88#ibcon#read 3, iclass 10, count 2 2006.245.08:22:24.88#ibcon#about to read 4, iclass 10, count 2 2006.245.08:22:24.88#ibcon#read 4, iclass 10, count 2 2006.245.08:22:24.88#ibcon#about to read 5, iclass 10, count 2 2006.245.08:22:24.88#ibcon#read 5, iclass 10, count 2 2006.245.08:22:24.88#ibcon#about to read 6, iclass 10, count 2 2006.245.08:22:24.88#ibcon#read 6, iclass 10, count 2 2006.245.08:22:24.88#ibcon#end of sib2, iclass 10, count 2 2006.245.08:22:24.88#ibcon#*mode == 0, iclass 10, count 2 2006.245.08:22:24.88#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.245.08:22:24.88#ibcon#[27=AT01-04\r\n] 2006.245.08:22:24.88#ibcon#*before write, iclass 10, count 2 2006.245.08:22:24.88#ibcon#enter sib2, iclass 10, count 2 2006.245.08:22:24.88#ibcon#flushed, iclass 10, count 2 2006.245.08:22:24.88#ibcon#about to write, iclass 10, count 2 2006.245.08:22:24.88#ibcon#wrote, iclass 10, count 2 2006.245.08:22:24.88#ibcon#about to read 3, iclass 10, count 2 2006.245.08:22:24.91#ibcon#read 3, iclass 10, count 2 2006.245.08:22:24.91#ibcon#about to read 4, iclass 10, count 2 2006.245.08:22:24.91#ibcon#read 4, iclass 10, count 2 2006.245.08:22:24.91#ibcon#about to read 5, iclass 10, count 2 2006.245.08:22:24.91#ibcon#read 5, iclass 10, count 2 2006.245.08:22:24.91#ibcon#about to read 6, iclass 10, count 2 2006.245.08:22:24.91#ibcon#read 6, iclass 10, count 2 2006.245.08:22:24.91#ibcon#end of sib2, iclass 10, count 2 2006.245.08:22:24.91#ibcon#*after write, iclass 10, count 2 2006.245.08:22:24.91#ibcon#*before return 0, iclass 10, count 2 2006.245.08:22:24.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:22:24.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.245.08:22:24.91#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.245.08:22:24.91#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:24.91#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:22:25.03#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:22:25.03#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:22:25.03#ibcon#enter wrdev, iclass 10, count 0 2006.245.08:22:25.03#ibcon#first serial, iclass 10, count 0 2006.245.08:22:25.03#ibcon#enter sib2, iclass 10, count 0 2006.245.08:22:25.03#ibcon#flushed, iclass 10, count 0 2006.245.08:22:25.03#ibcon#about to write, iclass 10, count 0 2006.245.08:22:25.03#ibcon#wrote, iclass 10, count 0 2006.245.08:22:25.03#ibcon#about to read 3, iclass 10, count 0 2006.245.08:22:25.05#ibcon#read 3, iclass 10, count 0 2006.245.08:22:25.05#ibcon#about to read 4, iclass 10, count 0 2006.245.08:22:25.05#ibcon#read 4, iclass 10, count 0 2006.245.08:22:25.05#ibcon#about to read 5, iclass 10, count 0 2006.245.08:22:25.05#ibcon#read 5, iclass 10, count 0 2006.245.08:22:25.05#ibcon#about to read 6, iclass 10, count 0 2006.245.08:22:25.05#ibcon#read 6, iclass 10, count 0 2006.245.08:22:25.05#ibcon#end of sib2, iclass 10, count 0 2006.245.08:22:25.05#ibcon#*mode == 0, iclass 10, count 0 2006.245.08:22:25.05#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.245.08:22:25.05#ibcon#[27=USB\r\n] 2006.245.08:22:25.05#ibcon#*before write, iclass 10, count 0 2006.245.08:22:25.05#ibcon#enter sib2, iclass 10, count 0 2006.245.08:22:25.05#ibcon#flushed, iclass 10, count 0 2006.245.08:22:25.05#ibcon#about to write, iclass 10, count 0 2006.245.08:22:25.05#ibcon#wrote, iclass 10, count 0 2006.245.08:22:25.05#ibcon#about to read 3, iclass 10, count 0 2006.245.08:22:25.08#ibcon#read 3, iclass 10, count 0 2006.245.08:22:25.08#ibcon#about to read 4, iclass 10, count 0 2006.245.08:22:25.08#ibcon#read 4, iclass 10, count 0 2006.245.08:22:25.08#ibcon#about to read 5, iclass 10, count 0 2006.245.08:22:25.08#ibcon#read 5, iclass 10, count 0 2006.245.08:22:25.08#ibcon#about to read 6, iclass 10, count 0 2006.245.08:22:25.08#ibcon#read 6, iclass 10, count 0 2006.245.08:22:25.08#ibcon#end of sib2, iclass 10, count 0 2006.245.08:22:25.08#ibcon#*after write, iclass 10, count 0 2006.245.08:22:25.08#ibcon#*before return 0, iclass 10, count 0 2006.245.08:22:25.08#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:22:25.08#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.245.08:22:25.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.245.08:22:25.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.245.08:22:25.08$vc4f8/vblo=2,640.99 2006.245.08:22:25.08#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.245.08:22:25.08#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.245.08:22:25.08#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:25.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:25.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:25.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:25.08#ibcon#enter wrdev, iclass 12, count 0 2006.245.08:22:25.08#ibcon#first serial, iclass 12, count 0 2006.245.08:22:25.08#ibcon#enter sib2, iclass 12, count 0 2006.245.08:22:25.08#ibcon#flushed, iclass 12, count 0 2006.245.08:22:25.08#ibcon#about to write, iclass 12, count 0 2006.245.08:22:25.08#ibcon#wrote, iclass 12, count 0 2006.245.08:22:25.08#ibcon#about to read 3, iclass 12, count 0 2006.245.08:22:25.10#ibcon#read 3, iclass 12, count 0 2006.245.08:22:25.10#ibcon#about to read 4, iclass 12, count 0 2006.245.08:22:25.10#ibcon#read 4, iclass 12, count 0 2006.245.08:22:25.10#ibcon#about to read 5, iclass 12, count 0 2006.245.08:22:25.10#ibcon#read 5, iclass 12, count 0 2006.245.08:22:25.10#ibcon#about to read 6, iclass 12, count 0 2006.245.08:22:25.10#ibcon#read 6, iclass 12, count 0 2006.245.08:22:25.10#ibcon#end of sib2, iclass 12, count 0 2006.245.08:22:25.10#ibcon#*mode == 0, iclass 12, count 0 2006.245.08:22:25.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.245.08:22:25.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:22:25.10#ibcon#*before write, iclass 12, count 0 2006.245.08:22:25.10#ibcon#enter sib2, iclass 12, count 0 2006.245.08:22:25.10#ibcon#flushed, iclass 12, count 0 2006.245.08:22:25.10#ibcon#about to write, iclass 12, count 0 2006.245.08:22:25.10#ibcon#wrote, iclass 12, count 0 2006.245.08:22:25.10#ibcon#about to read 3, iclass 12, count 0 2006.245.08:22:25.14#ibcon#read 3, iclass 12, count 0 2006.245.08:22:25.14#ibcon#about to read 4, iclass 12, count 0 2006.245.08:22:25.14#ibcon#read 4, iclass 12, count 0 2006.245.08:22:25.14#ibcon#about to read 5, iclass 12, count 0 2006.245.08:22:25.14#ibcon#read 5, iclass 12, count 0 2006.245.08:22:25.14#ibcon#about to read 6, iclass 12, count 0 2006.245.08:22:25.14#ibcon#read 6, iclass 12, count 0 2006.245.08:22:25.14#ibcon#end of sib2, iclass 12, count 0 2006.245.08:22:25.14#ibcon#*after write, iclass 12, count 0 2006.245.08:22:25.14#ibcon#*before return 0, iclass 12, count 0 2006.245.08:22:25.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:25.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.245.08:22:25.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.245.08:22:25.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.245.08:22:25.14$vc4f8/vb=2,4 2006.245.08:22:25.14#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.245.08:22:25.14#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.245.08:22:25.14#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:25.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:25.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:25.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:25.20#ibcon#enter wrdev, iclass 14, count 2 2006.245.08:22:25.20#ibcon#first serial, iclass 14, count 2 2006.245.08:22:25.20#ibcon#enter sib2, iclass 14, count 2 2006.245.08:22:25.20#ibcon#flushed, iclass 14, count 2 2006.245.08:22:25.20#ibcon#about to write, iclass 14, count 2 2006.245.08:22:25.20#ibcon#wrote, iclass 14, count 2 2006.245.08:22:25.20#ibcon#about to read 3, iclass 14, count 2 2006.245.08:22:25.22#ibcon#read 3, iclass 14, count 2 2006.245.08:22:25.22#ibcon#about to read 4, iclass 14, count 2 2006.245.08:22:25.22#ibcon#read 4, iclass 14, count 2 2006.245.08:22:25.22#ibcon#about to read 5, iclass 14, count 2 2006.245.08:22:25.22#ibcon#read 5, iclass 14, count 2 2006.245.08:22:25.22#ibcon#about to read 6, iclass 14, count 2 2006.245.08:22:25.22#ibcon#read 6, iclass 14, count 2 2006.245.08:22:25.22#ibcon#end of sib2, iclass 14, count 2 2006.245.08:22:25.22#ibcon#*mode == 0, iclass 14, count 2 2006.245.08:22:25.22#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.245.08:22:25.22#ibcon#[27=AT02-04\r\n] 2006.245.08:22:25.22#ibcon#*before write, iclass 14, count 2 2006.245.08:22:25.22#ibcon#enter sib2, iclass 14, count 2 2006.245.08:22:25.22#ibcon#flushed, iclass 14, count 2 2006.245.08:22:25.22#ibcon#about to write, iclass 14, count 2 2006.245.08:22:25.22#ibcon#wrote, iclass 14, count 2 2006.245.08:22:25.22#ibcon#about to read 3, iclass 14, count 2 2006.245.08:22:25.25#ibcon#read 3, iclass 14, count 2 2006.245.08:22:25.25#ibcon#about to read 4, iclass 14, count 2 2006.245.08:22:25.25#ibcon#read 4, iclass 14, count 2 2006.245.08:22:25.25#ibcon#about to read 5, iclass 14, count 2 2006.245.08:22:25.25#ibcon#read 5, iclass 14, count 2 2006.245.08:22:25.25#ibcon#about to read 6, iclass 14, count 2 2006.245.08:22:25.25#ibcon#read 6, iclass 14, count 2 2006.245.08:22:25.25#ibcon#end of sib2, iclass 14, count 2 2006.245.08:22:25.25#ibcon#*after write, iclass 14, count 2 2006.245.08:22:25.25#ibcon#*before return 0, iclass 14, count 2 2006.245.08:22:25.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:25.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.245.08:22:25.25#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.245.08:22:25.25#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:25.25#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:25.37#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:25.37#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:25.37#ibcon#enter wrdev, iclass 14, count 0 2006.245.08:22:25.37#ibcon#first serial, iclass 14, count 0 2006.245.08:22:25.37#ibcon#enter sib2, iclass 14, count 0 2006.245.08:22:25.37#ibcon#flushed, iclass 14, count 0 2006.245.08:22:25.37#ibcon#about to write, iclass 14, count 0 2006.245.08:22:25.37#ibcon#wrote, iclass 14, count 0 2006.245.08:22:25.37#ibcon#about to read 3, iclass 14, count 0 2006.245.08:22:25.39#ibcon#read 3, iclass 14, count 0 2006.245.08:22:25.39#ibcon#about to read 4, iclass 14, count 0 2006.245.08:22:25.39#ibcon#read 4, iclass 14, count 0 2006.245.08:22:25.39#ibcon#about to read 5, iclass 14, count 0 2006.245.08:22:25.39#ibcon#read 5, iclass 14, count 0 2006.245.08:22:25.39#ibcon#about to read 6, iclass 14, count 0 2006.245.08:22:25.39#ibcon#read 6, iclass 14, count 0 2006.245.08:22:25.39#ibcon#end of sib2, iclass 14, count 0 2006.245.08:22:25.39#ibcon#*mode == 0, iclass 14, count 0 2006.245.08:22:25.39#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.245.08:22:25.39#ibcon#[27=USB\r\n] 2006.245.08:22:25.39#ibcon#*before write, iclass 14, count 0 2006.245.08:22:25.39#ibcon#enter sib2, iclass 14, count 0 2006.245.08:22:25.39#ibcon#flushed, iclass 14, count 0 2006.245.08:22:25.39#ibcon#about to write, iclass 14, count 0 2006.245.08:22:25.39#ibcon#wrote, iclass 14, count 0 2006.245.08:22:25.39#ibcon#about to read 3, iclass 14, count 0 2006.245.08:22:25.42#ibcon#read 3, iclass 14, count 0 2006.245.08:22:25.42#ibcon#about to read 4, iclass 14, count 0 2006.245.08:22:25.42#ibcon#read 4, iclass 14, count 0 2006.245.08:22:25.42#ibcon#about to read 5, iclass 14, count 0 2006.245.08:22:25.42#ibcon#read 5, iclass 14, count 0 2006.245.08:22:25.42#ibcon#about to read 6, iclass 14, count 0 2006.245.08:22:25.42#ibcon#read 6, iclass 14, count 0 2006.245.08:22:25.42#ibcon#end of sib2, iclass 14, count 0 2006.245.08:22:25.42#ibcon#*after write, iclass 14, count 0 2006.245.08:22:25.42#ibcon#*before return 0, iclass 14, count 0 2006.245.08:22:25.42#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:25.42#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.245.08:22:25.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.245.08:22:25.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.245.08:22:25.42$vc4f8/vblo=3,656.99 2006.245.08:22:25.42#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.245.08:22:25.42#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.245.08:22:25.42#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:25.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:25.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:25.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:25.42#ibcon#enter wrdev, iclass 16, count 0 2006.245.08:22:25.42#ibcon#first serial, iclass 16, count 0 2006.245.08:22:25.42#ibcon#enter sib2, iclass 16, count 0 2006.245.08:22:25.42#ibcon#flushed, iclass 16, count 0 2006.245.08:22:25.42#ibcon#about to write, iclass 16, count 0 2006.245.08:22:25.42#ibcon#wrote, iclass 16, count 0 2006.245.08:22:25.42#ibcon#about to read 3, iclass 16, count 0 2006.245.08:22:25.44#ibcon#read 3, iclass 16, count 0 2006.245.08:22:25.44#ibcon#about to read 4, iclass 16, count 0 2006.245.08:22:25.44#ibcon#read 4, iclass 16, count 0 2006.245.08:22:25.44#ibcon#about to read 5, iclass 16, count 0 2006.245.08:22:25.44#ibcon#read 5, iclass 16, count 0 2006.245.08:22:25.44#ibcon#about to read 6, iclass 16, count 0 2006.245.08:22:25.44#ibcon#read 6, iclass 16, count 0 2006.245.08:22:25.44#ibcon#end of sib2, iclass 16, count 0 2006.245.08:22:25.44#ibcon#*mode == 0, iclass 16, count 0 2006.245.08:22:25.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.245.08:22:25.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:22:25.44#ibcon#*before write, iclass 16, count 0 2006.245.08:22:25.44#ibcon#enter sib2, iclass 16, count 0 2006.245.08:22:25.44#ibcon#flushed, iclass 16, count 0 2006.245.08:22:25.44#ibcon#about to write, iclass 16, count 0 2006.245.08:22:25.44#ibcon#wrote, iclass 16, count 0 2006.245.08:22:25.44#ibcon#about to read 3, iclass 16, count 0 2006.245.08:22:25.48#ibcon#read 3, iclass 16, count 0 2006.245.08:22:25.48#ibcon#about to read 4, iclass 16, count 0 2006.245.08:22:25.48#ibcon#read 4, iclass 16, count 0 2006.245.08:22:25.48#ibcon#about to read 5, iclass 16, count 0 2006.245.08:22:25.48#ibcon#read 5, iclass 16, count 0 2006.245.08:22:25.48#ibcon#about to read 6, iclass 16, count 0 2006.245.08:22:25.48#ibcon#read 6, iclass 16, count 0 2006.245.08:22:25.48#ibcon#end of sib2, iclass 16, count 0 2006.245.08:22:25.48#ibcon#*after write, iclass 16, count 0 2006.245.08:22:25.48#ibcon#*before return 0, iclass 16, count 0 2006.245.08:22:25.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:25.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.245.08:22:25.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.245.08:22:25.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.245.08:22:25.48$vc4f8/vb=3,4 2006.245.08:22:25.48#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.245.08:22:25.48#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.245.08:22:25.48#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:25.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:25.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:25.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:25.54#ibcon#enter wrdev, iclass 18, count 2 2006.245.08:22:25.54#ibcon#first serial, iclass 18, count 2 2006.245.08:22:25.54#ibcon#enter sib2, iclass 18, count 2 2006.245.08:22:25.54#ibcon#flushed, iclass 18, count 2 2006.245.08:22:25.54#ibcon#about to write, iclass 18, count 2 2006.245.08:22:25.54#ibcon#wrote, iclass 18, count 2 2006.245.08:22:25.54#ibcon#about to read 3, iclass 18, count 2 2006.245.08:22:25.56#ibcon#read 3, iclass 18, count 2 2006.245.08:22:25.56#ibcon#about to read 4, iclass 18, count 2 2006.245.08:22:25.56#ibcon#read 4, iclass 18, count 2 2006.245.08:22:25.56#ibcon#about to read 5, iclass 18, count 2 2006.245.08:22:25.56#ibcon#read 5, iclass 18, count 2 2006.245.08:22:25.56#ibcon#about to read 6, iclass 18, count 2 2006.245.08:22:25.56#ibcon#read 6, iclass 18, count 2 2006.245.08:22:25.56#ibcon#end of sib2, iclass 18, count 2 2006.245.08:22:25.56#ibcon#*mode == 0, iclass 18, count 2 2006.245.08:22:25.56#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.245.08:22:25.56#ibcon#[27=AT03-04\r\n] 2006.245.08:22:25.56#ibcon#*before write, iclass 18, count 2 2006.245.08:22:25.56#ibcon#enter sib2, iclass 18, count 2 2006.245.08:22:25.56#ibcon#flushed, iclass 18, count 2 2006.245.08:22:25.56#ibcon#about to write, iclass 18, count 2 2006.245.08:22:25.56#ibcon#wrote, iclass 18, count 2 2006.245.08:22:25.56#ibcon#about to read 3, iclass 18, count 2 2006.245.08:22:25.59#ibcon#read 3, iclass 18, count 2 2006.245.08:22:25.59#ibcon#about to read 4, iclass 18, count 2 2006.245.08:22:25.59#ibcon#read 4, iclass 18, count 2 2006.245.08:22:25.59#ibcon#about to read 5, iclass 18, count 2 2006.245.08:22:25.59#ibcon#read 5, iclass 18, count 2 2006.245.08:22:25.59#ibcon#about to read 6, iclass 18, count 2 2006.245.08:22:25.59#ibcon#read 6, iclass 18, count 2 2006.245.08:22:25.59#ibcon#end of sib2, iclass 18, count 2 2006.245.08:22:25.59#ibcon#*after write, iclass 18, count 2 2006.245.08:22:25.59#ibcon#*before return 0, iclass 18, count 2 2006.245.08:22:25.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:25.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.245.08:22:25.59#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.245.08:22:25.59#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:25.59#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:25.71#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:25.71#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:25.71#ibcon#enter wrdev, iclass 18, count 0 2006.245.08:22:25.71#ibcon#first serial, iclass 18, count 0 2006.245.08:22:25.71#ibcon#enter sib2, iclass 18, count 0 2006.245.08:22:25.71#ibcon#flushed, iclass 18, count 0 2006.245.08:22:25.71#ibcon#about to write, iclass 18, count 0 2006.245.08:22:25.71#ibcon#wrote, iclass 18, count 0 2006.245.08:22:25.71#ibcon#about to read 3, iclass 18, count 0 2006.245.08:22:25.73#ibcon#read 3, iclass 18, count 0 2006.245.08:22:25.73#ibcon#about to read 4, iclass 18, count 0 2006.245.08:22:25.73#ibcon#read 4, iclass 18, count 0 2006.245.08:22:25.73#ibcon#about to read 5, iclass 18, count 0 2006.245.08:22:25.73#ibcon#read 5, iclass 18, count 0 2006.245.08:22:25.73#ibcon#about to read 6, iclass 18, count 0 2006.245.08:22:25.73#ibcon#read 6, iclass 18, count 0 2006.245.08:22:25.73#ibcon#end of sib2, iclass 18, count 0 2006.245.08:22:25.73#ibcon#*mode == 0, iclass 18, count 0 2006.245.08:22:25.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.245.08:22:25.73#ibcon#[27=USB\r\n] 2006.245.08:22:25.73#ibcon#*before write, iclass 18, count 0 2006.245.08:22:25.73#ibcon#enter sib2, iclass 18, count 0 2006.245.08:22:25.73#ibcon#flushed, iclass 18, count 0 2006.245.08:22:25.73#ibcon#about to write, iclass 18, count 0 2006.245.08:22:25.73#ibcon#wrote, iclass 18, count 0 2006.245.08:22:25.73#ibcon#about to read 3, iclass 18, count 0 2006.245.08:22:25.76#ibcon#read 3, iclass 18, count 0 2006.245.08:22:25.76#ibcon#about to read 4, iclass 18, count 0 2006.245.08:22:25.76#ibcon#read 4, iclass 18, count 0 2006.245.08:22:25.76#ibcon#about to read 5, iclass 18, count 0 2006.245.08:22:25.76#ibcon#read 5, iclass 18, count 0 2006.245.08:22:25.76#ibcon#about to read 6, iclass 18, count 0 2006.245.08:22:25.76#ibcon#read 6, iclass 18, count 0 2006.245.08:22:25.76#ibcon#end of sib2, iclass 18, count 0 2006.245.08:22:25.76#ibcon#*after write, iclass 18, count 0 2006.245.08:22:25.76#ibcon#*before return 0, iclass 18, count 0 2006.245.08:22:25.76#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:25.76#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.245.08:22:25.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.245.08:22:25.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.245.08:22:25.76$vc4f8/vblo=4,712.99 2006.245.08:22:25.76#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.245.08:22:25.76#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.245.08:22:25.76#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:25.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:25.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:25.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:25.76#ibcon#enter wrdev, iclass 20, count 0 2006.245.08:22:25.76#ibcon#first serial, iclass 20, count 0 2006.245.08:22:25.76#ibcon#enter sib2, iclass 20, count 0 2006.245.08:22:25.76#ibcon#flushed, iclass 20, count 0 2006.245.08:22:25.76#ibcon#about to write, iclass 20, count 0 2006.245.08:22:25.76#ibcon#wrote, iclass 20, count 0 2006.245.08:22:25.76#ibcon#about to read 3, iclass 20, count 0 2006.245.08:22:25.78#ibcon#read 3, iclass 20, count 0 2006.245.08:22:25.78#ibcon#about to read 4, iclass 20, count 0 2006.245.08:22:25.78#ibcon#read 4, iclass 20, count 0 2006.245.08:22:25.78#ibcon#about to read 5, iclass 20, count 0 2006.245.08:22:25.78#ibcon#read 5, iclass 20, count 0 2006.245.08:22:25.78#ibcon#about to read 6, iclass 20, count 0 2006.245.08:22:25.78#ibcon#read 6, iclass 20, count 0 2006.245.08:22:25.78#ibcon#end of sib2, iclass 20, count 0 2006.245.08:22:25.78#ibcon#*mode == 0, iclass 20, count 0 2006.245.08:22:25.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.245.08:22:25.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:22:25.78#ibcon#*before write, iclass 20, count 0 2006.245.08:22:25.78#ibcon#enter sib2, iclass 20, count 0 2006.245.08:22:25.78#ibcon#flushed, iclass 20, count 0 2006.245.08:22:25.78#ibcon#about to write, iclass 20, count 0 2006.245.08:22:25.78#ibcon#wrote, iclass 20, count 0 2006.245.08:22:25.78#ibcon#about to read 3, iclass 20, count 0 2006.245.08:22:25.83#ibcon#read 3, iclass 20, count 0 2006.245.08:22:25.83#ibcon#about to read 4, iclass 20, count 0 2006.245.08:22:25.83#ibcon#read 4, iclass 20, count 0 2006.245.08:22:25.83#ibcon#about to read 5, iclass 20, count 0 2006.245.08:22:25.83#ibcon#read 5, iclass 20, count 0 2006.245.08:22:25.83#ibcon#about to read 6, iclass 20, count 0 2006.245.08:22:25.83#ibcon#read 6, iclass 20, count 0 2006.245.08:22:25.83#ibcon#end of sib2, iclass 20, count 0 2006.245.08:22:25.83#ibcon#*after write, iclass 20, count 0 2006.245.08:22:25.83#ibcon#*before return 0, iclass 20, count 0 2006.245.08:22:25.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:25.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.245.08:22:25.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.245.08:22:25.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.245.08:22:25.83$vc4f8/vb=4,4 2006.245.08:22:25.83#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.245.08:22:25.83#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.245.08:22:25.83#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:25.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:25.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:25.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:25.88#ibcon#enter wrdev, iclass 22, count 2 2006.245.08:22:25.88#ibcon#first serial, iclass 22, count 2 2006.245.08:22:25.88#ibcon#enter sib2, iclass 22, count 2 2006.245.08:22:25.88#ibcon#flushed, iclass 22, count 2 2006.245.08:22:25.88#ibcon#about to write, iclass 22, count 2 2006.245.08:22:25.88#ibcon#wrote, iclass 22, count 2 2006.245.08:22:25.88#ibcon#about to read 3, iclass 22, count 2 2006.245.08:22:25.90#ibcon#read 3, iclass 22, count 2 2006.245.08:22:25.90#ibcon#about to read 4, iclass 22, count 2 2006.245.08:22:25.90#ibcon#read 4, iclass 22, count 2 2006.245.08:22:25.90#ibcon#about to read 5, iclass 22, count 2 2006.245.08:22:25.90#ibcon#read 5, iclass 22, count 2 2006.245.08:22:25.90#ibcon#about to read 6, iclass 22, count 2 2006.245.08:22:25.90#ibcon#read 6, iclass 22, count 2 2006.245.08:22:25.90#ibcon#end of sib2, iclass 22, count 2 2006.245.08:22:25.90#ibcon#*mode == 0, iclass 22, count 2 2006.245.08:22:25.90#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.245.08:22:25.90#ibcon#[27=AT04-04\r\n] 2006.245.08:22:25.90#ibcon#*before write, iclass 22, count 2 2006.245.08:22:25.90#ibcon#enter sib2, iclass 22, count 2 2006.245.08:22:25.90#ibcon#flushed, iclass 22, count 2 2006.245.08:22:25.90#ibcon#about to write, iclass 22, count 2 2006.245.08:22:25.90#ibcon#wrote, iclass 22, count 2 2006.245.08:22:25.90#ibcon#about to read 3, iclass 22, count 2 2006.245.08:22:25.93#ibcon#read 3, iclass 22, count 2 2006.245.08:22:25.93#ibcon#about to read 4, iclass 22, count 2 2006.245.08:22:25.93#ibcon#read 4, iclass 22, count 2 2006.245.08:22:25.93#ibcon#about to read 5, iclass 22, count 2 2006.245.08:22:25.93#ibcon#read 5, iclass 22, count 2 2006.245.08:22:25.93#ibcon#about to read 6, iclass 22, count 2 2006.245.08:22:25.93#ibcon#read 6, iclass 22, count 2 2006.245.08:22:25.93#ibcon#end of sib2, iclass 22, count 2 2006.245.08:22:25.93#ibcon#*after write, iclass 22, count 2 2006.245.08:22:25.93#ibcon#*before return 0, iclass 22, count 2 2006.245.08:22:25.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:25.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.245.08:22:25.93#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.245.08:22:25.93#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:25.93#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:26.05#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:26.05#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:26.05#ibcon#enter wrdev, iclass 22, count 0 2006.245.08:22:26.05#ibcon#first serial, iclass 22, count 0 2006.245.08:22:26.05#ibcon#enter sib2, iclass 22, count 0 2006.245.08:22:26.05#ibcon#flushed, iclass 22, count 0 2006.245.08:22:26.05#ibcon#about to write, iclass 22, count 0 2006.245.08:22:26.05#ibcon#wrote, iclass 22, count 0 2006.245.08:22:26.05#ibcon#about to read 3, iclass 22, count 0 2006.245.08:22:26.07#ibcon#read 3, iclass 22, count 0 2006.245.08:22:26.07#ibcon#about to read 4, iclass 22, count 0 2006.245.08:22:26.07#ibcon#read 4, iclass 22, count 0 2006.245.08:22:26.07#ibcon#about to read 5, iclass 22, count 0 2006.245.08:22:26.07#ibcon#read 5, iclass 22, count 0 2006.245.08:22:26.07#ibcon#about to read 6, iclass 22, count 0 2006.245.08:22:26.07#ibcon#read 6, iclass 22, count 0 2006.245.08:22:26.07#ibcon#end of sib2, iclass 22, count 0 2006.245.08:22:26.07#ibcon#*mode == 0, iclass 22, count 0 2006.245.08:22:26.07#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.245.08:22:26.07#ibcon#[27=USB\r\n] 2006.245.08:22:26.07#ibcon#*before write, iclass 22, count 0 2006.245.08:22:26.07#ibcon#enter sib2, iclass 22, count 0 2006.245.08:22:26.07#ibcon#flushed, iclass 22, count 0 2006.245.08:22:26.07#ibcon#about to write, iclass 22, count 0 2006.245.08:22:26.07#ibcon#wrote, iclass 22, count 0 2006.245.08:22:26.07#ibcon#about to read 3, iclass 22, count 0 2006.245.08:22:26.10#ibcon#read 3, iclass 22, count 0 2006.245.08:22:26.10#ibcon#about to read 4, iclass 22, count 0 2006.245.08:22:26.10#ibcon#read 4, iclass 22, count 0 2006.245.08:22:26.10#ibcon#about to read 5, iclass 22, count 0 2006.245.08:22:26.10#ibcon#read 5, iclass 22, count 0 2006.245.08:22:26.10#ibcon#about to read 6, iclass 22, count 0 2006.245.08:22:26.10#ibcon#read 6, iclass 22, count 0 2006.245.08:22:26.10#ibcon#end of sib2, iclass 22, count 0 2006.245.08:22:26.10#ibcon#*after write, iclass 22, count 0 2006.245.08:22:26.10#ibcon#*before return 0, iclass 22, count 0 2006.245.08:22:26.10#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:26.10#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.245.08:22:26.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.245.08:22:26.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.245.08:22:26.10$vc4f8/vblo=5,744.99 2006.245.08:22:26.10#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.245.08:22:26.10#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.245.08:22:26.10#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:26.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:26.10#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:26.10#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:26.10#ibcon#enter wrdev, iclass 24, count 0 2006.245.08:22:26.10#ibcon#first serial, iclass 24, count 0 2006.245.08:22:26.10#ibcon#enter sib2, iclass 24, count 0 2006.245.08:22:26.10#ibcon#flushed, iclass 24, count 0 2006.245.08:22:26.10#ibcon#about to write, iclass 24, count 0 2006.245.08:22:26.10#ibcon#wrote, iclass 24, count 0 2006.245.08:22:26.10#ibcon#about to read 3, iclass 24, count 0 2006.245.08:22:26.12#ibcon#read 3, iclass 24, count 0 2006.245.08:22:26.12#ibcon#about to read 4, iclass 24, count 0 2006.245.08:22:26.12#ibcon#read 4, iclass 24, count 0 2006.245.08:22:26.12#ibcon#about to read 5, iclass 24, count 0 2006.245.08:22:26.12#ibcon#read 5, iclass 24, count 0 2006.245.08:22:26.12#ibcon#about to read 6, iclass 24, count 0 2006.245.08:22:26.12#ibcon#read 6, iclass 24, count 0 2006.245.08:22:26.12#ibcon#end of sib2, iclass 24, count 0 2006.245.08:22:26.12#ibcon#*mode == 0, iclass 24, count 0 2006.245.08:22:26.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.245.08:22:26.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:22:26.12#ibcon#*before write, iclass 24, count 0 2006.245.08:22:26.12#ibcon#enter sib2, iclass 24, count 0 2006.245.08:22:26.12#ibcon#flushed, iclass 24, count 0 2006.245.08:22:26.12#ibcon#about to write, iclass 24, count 0 2006.245.08:22:26.12#ibcon#wrote, iclass 24, count 0 2006.245.08:22:26.12#ibcon#about to read 3, iclass 24, count 0 2006.245.08:22:26.16#ibcon#read 3, iclass 24, count 0 2006.245.08:22:26.16#ibcon#about to read 4, iclass 24, count 0 2006.245.08:22:26.16#ibcon#read 4, iclass 24, count 0 2006.245.08:22:26.16#ibcon#about to read 5, iclass 24, count 0 2006.245.08:22:26.16#ibcon#read 5, iclass 24, count 0 2006.245.08:22:26.16#ibcon#about to read 6, iclass 24, count 0 2006.245.08:22:26.16#ibcon#read 6, iclass 24, count 0 2006.245.08:22:26.16#ibcon#end of sib2, iclass 24, count 0 2006.245.08:22:26.16#ibcon#*after write, iclass 24, count 0 2006.245.08:22:26.16#ibcon#*before return 0, iclass 24, count 0 2006.245.08:22:26.16#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:26.16#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.245.08:22:26.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.245.08:22:26.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.245.08:22:26.16$vc4f8/vb=5,3 2006.245.08:22:26.16#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.245.08:22:26.16#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.245.08:22:26.16#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:26.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:26.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:26.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:26.22#ibcon#enter wrdev, iclass 26, count 2 2006.245.08:22:26.22#ibcon#first serial, iclass 26, count 2 2006.245.08:22:26.22#ibcon#enter sib2, iclass 26, count 2 2006.245.08:22:26.22#ibcon#flushed, iclass 26, count 2 2006.245.08:22:26.22#ibcon#about to write, iclass 26, count 2 2006.245.08:22:26.22#ibcon#wrote, iclass 26, count 2 2006.245.08:22:26.22#ibcon#about to read 3, iclass 26, count 2 2006.245.08:22:26.24#ibcon#read 3, iclass 26, count 2 2006.245.08:22:26.24#ibcon#about to read 4, iclass 26, count 2 2006.245.08:22:26.24#ibcon#read 4, iclass 26, count 2 2006.245.08:22:26.24#ibcon#about to read 5, iclass 26, count 2 2006.245.08:22:26.24#ibcon#read 5, iclass 26, count 2 2006.245.08:22:26.24#ibcon#about to read 6, iclass 26, count 2 2006.245.08:22:26.24#ibcon#read 6, iclass 26, count 2 2006.245.08:22:26.24#ibcon#end of sib2, iclass 26, count 2 2006.245.08:22:26.24#ibcon#*mode == 0, iclass 26, count 2 2006.245.08:22:26.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.245.08:22:26.24#ibcon#[27=AT05-03\r\n] 2006.245.08:22:26.24#ibcon#*before write, iclass 26, count 2 2006.245.08:22:26.24#ibcon#enter sib2, iclass 26, count 2 2006.245.08:22:26.24#ibcon#flushed, iclass 26, count 2 2006.245.08:22:26.24#ibcon#about to write, iclass 26, count 2 2006.245.08:22:26.24#ibcon#wrote, iclass 26, count 2 2006.245.08:22:26.24#ibcon#about to read 3, iclass 26, count 2 2006.245.08:22:26.27#ibcon#read 3, iclass 26, count 2 2006.245.08:22:26.27#ibcon#about to read 4, iclass 26, count 2 2006.245.08:22:26.27#ibcon#read 4, iclass 26, count 2 2006.245.08:22:26.27#ibcon#about to read 5, iclass 26, count 2 2006.245.08:22:26.27#ibcon#read 5, iclass 26, count 2 2006.245.08:22:26.27#ibcon#about to read 6, iclass 26, count 2 2006.245.08:22:26.27#ibcon#read 6, iclass 26, count 2 2006.245.08:22:26.27#ibcon#end of sib2, iclass 26, count 2 2006.245.08:22:26.27#ibcon#*after write, iclass 26, count 2 2006.245.08:22:26.27#ibcon#*before return 0, iclass 26, count 2 2006.245.08:22:26.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:26.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.245.08:22:26.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.245.08:22:26.27#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:26.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:26.39#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:26.39#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:26.39#ibcon#enter wrdev, iclass 26, count 0 2006.245.08:22:26.39#ibcon#first serial, iclass 26, count 0 2006.245.08:22:26.39#ibcon#enter sib2, iclass 26, count 0 2006.245.08:22:26.39#ibcon#flushed, iclass 26, count 0 2006.245.08:22:26.39#ibcon#about to write, iclass 26, count 0 2006.245.08:22:26.39#ibcon#wrote, iclass 26, count 0 2006.245.08:22:26.39#ibcon#about to read 3, iclass 26, count 0 2006.245.08:22:26.41#ibcon#read 3, iclass 26, count 0 2006.245.08:22:26.41#ibcon#about to read 4, iclass 26, count 0 2006.245.08:22:26.41#ibcon#read 4, iclass 26, count 0 2006.245.08:22:26.41#ibcon#about to read 5, iclass 26, count 0 2006.245.08:22:26.41#ibcon#read 5, iclass 26, count 0 2006.245.08:22:26.41#ibcon#about to read 6, iclass 26, count 0 2006.245.08:22:26.41#ibcon#read 6, iclass 26, count 0 2006.245.08:22:26.41#ibcon#end of sib2, iclass 26, count 0 2006.245.08:22:26.41#ibcon#*mode == 0, iclass 26, count 0 2006.245.08:22:26.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.245.08:22:26.41#ibcon#[27=USB\r\n] 2006.245.08:22:26.41#ibcon#*before write, iclass 26, count 0 2006.245.08:22:26.41#ibcon#enter sib2, iclass 26, count 0 2006.245.08:22:26.41#ibcon#flushed, iclass 26, count 0 2006.245.08:22:26.41#ibcon#about to write, iclass 26, count 0 2006.245.08:22:26.41#ibcon#wrote, iclass 26, count 0 2006.245.08:22:26.41#ibcon#about to read 3, iclass 26, count 0 2006.245.08:22:26.44#ibcon#read 3, iclass 26, count 0 2006.245.08:22:26.44#ibcon#about to read 4, iclass 26, count 0 2006.245.08:22:26.44#ibcon#read 4, iclass 26, count 0 2006.245.08:22:26.44#ibcon#about to read 5, iclass 26, count 0 2006.245.08:22:26.44#ibcon#read 5, iclass 26, count 0 2006.245.08:22:26.44#ibcon#about to read 6, iclass 26, count 0 2006.245.08:22:26.44#ibcon#read 6, iclass 26, count 0 2006.245.08:22:26.44#ibcon#end of sib2, iclass 26, count 0 2006.245.08:22:26.44#ibcon#*after write, iclass 26, count 0 2006.245.08:22:26.44#ibcon#*before return 0, iclass 26, count 0 2006.245.08:22:26.44#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:26.44#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.245.08:22:26.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.245.08:22:26.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.245.08:22:26.44$vc4f8/vblo=6,752.99 2006.245.08:22:26.44#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.245.08:22:26.44#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.245.08:22:26.44#ibcon#ireg 17 cls_cnt 0 2006.245.08:22:26.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:26.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:26.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:26.44#ibcon#enter wrdev, iclass 28, count 0 2006.245.08:22:26.44#ibcon#first serial, iclass 28, count 0 2006.245.08:22:26.44#ibcon#enter sib2, iclass 28, count 0 2006.245.08:22:26.44#ibcon#flushed, iclass 28, count 0 2006.245.08:22:26.44#ibcon#about to write, iclass 28, count 0 2006.245.08:22:26.44#ibcon#wrote, iclass 28, count 0 2006.245.08:22:26.44#ibcon#about to read 3, iclass 28, count 0 2006.245.08:22:26.46#ibcon#read 3, iclass 28, count 0 2006.245.08:22:26.46#ibcon#about to read 4, iclass 28, count 0 2006.245.08:22:26.46#ibcon#read 4, iclass 28, count 0 2006.245.08:22:26.46#ibcon#about to read 5, iclass 28, count 0 2006.245.08:22:26.46#ibcon#read 5, iclass 28, count 0 2006.245.08:22:26.46#ibcon#about to read 6, iclass 28, count 0 2006.245.08:22:26.46#ibcon#read 6, iclass 28, count 0 2006.245.08:22:26.46#ibcon#end of sib2, iclass 28, count 0 2006.245.08:22:26.46#ibcon#*mode == 0, iclass 28, count 0 2006.245.08:22:26.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.245.08:22:26.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:22:26.46#ibcon#*before write, iclass 28, count 0 2006.245.08:22:26.46#ibcon#enter sib2, iclass 28, count 0 2006.245.08:22:26.46#ibcon#flushed, iclass 28, count 0 2006.245.08:22:26.46#ibcon#about to write, iclass 28, count 0 2006.245.08:22:26.46#ibcon#wrote, iclass 28, count 0 2006.245.08:22:26.46#ibcon#about to read 3, iclass 28, count 0 2006.245.08:22:26.50#ibcon#read 3, iclass 28, count 0 2006.245.08:22:26.50#ibcon#about to read 4, iclass 28, count 0 2006.245.08:22:26.50#ibcon#read 4, iclass 28, count 0 2006.245.08:22:26.50#ibcon#about to read 5, iclass 28, count 0 2006.245.08:22:26.50#ibcon#read 5, iclass 28, count 0 2006.245.08:22:26.50#ibcon#about to read 6, iclass 28, count 0 2006.245.08:22:26.50#ibcon#read 6, iclass 28, count 0 2006.245.08:22:26.50#ibcon#end of sib2, iclass 28, count 0 2006.245.08:22:26.50#ibcon#*after write, iclass 28, count 0 2006.245.08:22:26.50#ibcon#*before return 0, iclass 28, count 0 2006.245.08:22:26.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:26.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.245.08:22:26.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.245.08:22:26.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.245.08:22:26.50$vc4f8/vb=6,3 2006.245.08:22:26.50#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.245.08:22:26.50#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.245.08:22:26.50#ibcon#ireg 11 cls_cnt 2 2006.245.08:22:26.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:26.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:26.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:26.56#ibcon#enter wrdev, iclass 30, count 2 2006.245.08:22:26.56#ibcon#first serial, iclass 30, count 2 2006.245.08:22:26.56#ibcon#enter sib2, iclass 30, count 2 2006.245.08:22:26.56#ibcon#flushed, iclass 30, count 2 2006.245.08:22:26.56#ibcon#about to write, iclass 30, count 2 2006.245.08:22:26.56#ibcon#wrote, iclass 30, count 2 2006.245.08:22:26.56#ibcon#about to read 3, iclass 30, count 2 2006.245.08:22:26.58#ibcon#read 3, iclass 30, count 2 2006.245.08:22:26.58#ibcon#about to read 4, iclass 30, count 2 2006.245.08:22:26.58#ibcon#read 4, iclass 30, count 2 2006.245.08:22:26.58#ibcon#about to read 5, iclass 30, count 2 2006.245.08:22:26.58#ibcon#read 5, iclass 30, count 2 2006.245.08:22:26.58#ibcon#about to read 6, iclass 30, count 2 2006.245.08:22:26.58#ibcon#read 6, iclass 30, count 2 2006.245.08:22:26.58#ibcon#end of sib2, iclass 30, count 2 2006.245.08:22:26.58#ibcon#*mode == 0, iclass 30, count 2 2006.245.08:22:26.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.245.08:22:26.58#ibcon#[27=AT06-03\r\n] 2006.245.08:22:26.58#ibcon#*before write, iclass 30, count 2 2006.245.08:22:26.58#ibcon#enter sib2, iclass 30, count 2 2006.245.08:22:26.58#ibcon#flushed, iclass 30, count 2 2006.245.08:22:26.58#ibcon#about to write, iclass 30, count 2 2006.245.08:22:26.58#ibcon#wrote, iclass 30, count 2 2006.245.08:22:26.58#ibcon#about to read 3, iclass 30, count 2 2006.245.08:22:26.61#ibcon#read 3, iclass 30, count 2 2006.245.08:22:26.61#ibcon#about to read 4, iclass 30, count 2 2006.245.08:22:26.61#ibcon#read 4, iclass 30, count 2 2006.245.08:22:26.61#ibcon#about to read 5, iclass 30, count 2 2006.245.08:22:26.61#ibcon#read 5, iclass 30, count 2 2006.245.08:22:26.61#ibcon#about to read 6, iclass 30, count 2 2006.245.08:22:26.61#ibcon#read 6, iclass 30, count 2 2006.245.08:22:26.61#ibcon#end of sib2, iclass 30, count 2 2006.245.08:22:26.61#ibcon#*after write, iclass 30, count 2 2006.245.08:22:26.61#ibcon#*before return 0, iclass 30, count 2 2006.245.08:22:26.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:26.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.245.08:22:26.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.245.08:22:26.61#ibcon#ireg 7 cls_cnt 0 2006.245.08:22:26.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:26.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:26.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:26.73#ibcon#enter wrdev, iclass 30, count 0 2006.245.08:22:26.73#ibcon#first serial, iclass 30, count 0 2006.245.08:22:26.73#ibcon#enter sib2, iclass 30, count 0 2006.245.08:22:26.73#ibcon#flushed, iclass 30, count 0 2006.245.08:22:26.73#ibcon#about to write, iclass 30, count 0 2006.245.08:22:26.73#ibcon#wrote, iclass 30, count 0 2006.245.08:22:26.73#ibcon#about to read 3, iclass 30, count 0 2006.245.08:22:26.75#ibcon#read 3, iclass 30, count 0 2006.245.08:22:26.75#ibcon#about to read 4, iclass 30, count 0 2006.245.08:22:26.75#ibcon#read 4, iclass 30, count 0 2006.245.08:22:26.75#ibcon#about to read 5, iclass 30, count 0 2006.245.08:22:26.75#ibcon#read 5, iclass 30, count 0 2006.245.08:22:26.75#ibcon#about to read 6, iclass 30, count 0 2006.245.08:22:26.75#ibcon#read 6, iclass 30, count 0 2006.245.08:22:26.75#ibcon#end of sib2, iclass 30, count 0 2006.245.08:22:26.75#ibcon#*mode == 0, iclass 30, count 0 2006.245.08:22:26.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.245.08:22:26.75#ibcon#[27=USB\r\n] 2006.245.08:22:26.75#ibcon#*before write, iclass 30, count 0 2006.245.08:22:26.75#ibcon#enter sib2, iclass 30, count 0 2006.245.08:22:26.75#ibcon#flushed, iclass 30, count 0 2006.245.08:22:26.75#ibcon#about to write, iclass 30, count 0 2006.245.08:22:26.75#ibcon#wrote, iclass 30, count 0 2006.245.08:22:26.75#ibcon#about to read 3, iclass 30, count 0 2006.245.08:22:26.78#ibcon#read 3, iclass 30, count 0 2006.245.08:22:26.78#ibcon#about to read 4, iclass 30, count 0 2006.245.08:22:26.78#ibcon#read 4, iclass 30, count 0 2006.245.08:22:26.78#ibcon#about to read 5, iclass 30, count 0 2006.245.08:22:26.78#ibcon#read 5, iclass 30, count 0 2006.245.08:22:26.78#ibcon#about to read 6, iclass 30, count 0 2006.245.08:22:26.78#ibcon#read 6, iclass 30, count 0 2006.245.08:22:26.78#ibcon#end of sib2, iclass 30, count 0 2006.245.08:22:26.78#ibcon#*after write, iclass 30, count 0 2006.245.08:22:26.78#ibcon#*before return 0, iclass 30, count 0 2006.245.08:22:26.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:26.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.245.08:22:26.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.245.08:22:26.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.245.08:22:26.78$vc4f8/vabw=wide 2006.245.08:22:26.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.245.08:22:26.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.245.08:22:26.78#ibcon#ireg 8 cls_cnt 0 2006.245.08:22:26.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:26.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:26.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:26.78#ibcon#enter wrdev, iclass 32, count 0 2006.245.08:22:26.78#ibcon#first serial, iclass 32, count 0 2006.245.08:22:26.78#ibcon#enter sib2, iclass 32, count 0 2006.245.08:22:26.78#ibcon#flushed, iclass 32, count 0 2006.245.08:22:26.78#ibcon#about to write, iclass 32, count 0 2006.245.08:22:26.78#ibcon#wrote, iclass 32, count 0 2006.245.08:22:26.78#ibcon#about to read 3, iclass 32, count 0 2006.245.08:22:26.80#ibcon#read 3, iclass 32, count 0 2006.245.08:22:26.80#ibcon#about to read 4, iclass 32, count 0 2006.245.08:22:26.80#ibcon#read 4, iclass 32, count 0 2006.245.08:22:26.80#ibcon#about to read 5, iclass 32, count 0 2006.245.08:22:26.80#ibcon#read 5, iclass 32, count 0 2006.245.08:22:26.80#ibcon#about to read 6, iclass 32, count 0 2006.245.08:22:26.80#ibcon#read 6, iclass 32, count 0 2006.245.08:22:26.80#ibcon#end of sib2, iclass 32, count 0 2006.245.08:22:26.80#ibcon#*mode == 0, iclass 32, count 0 2006.245.08:22:26.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.245.08:22:26.80#ibcon#[25=BW32\r\n] 2006.245.08:22:26.80#ibcon#*before write, iclass 32, count 0 2006.245.08:22:26.80#ibcon#enter sib2, iclass 32, count 0 2006.245.08:22:26.80#ibcon#flushed, iclass 32, count 0 2006.245.08:22:26.80#ibcon#about to write, iclass 32, count 0 2006.245.08:22:26.80#ibcon#wrote, iclass 32, count 0 2006.245.08:22:26.80#ibcon#about to read 3, iclass 32, count 0 2006.245.08:22:26.83#ibcon#read 3, iclass 32, count 0 2006.245.08:22:26.83#ibcon#about to read 4, iclass 32, count 0 2006.245.08:22:26.83#ibcon#read 4, iclass 32, count 0 2006.245.08:22:26.83#ibcon#about to read 5, iclass 32, count 0 2006.245.08:22:26.83#ibcon#read 5, iclass 32, count 0 2006.245.08:22:26.83#ibcon#about to read 6, iclass 32, count 0 2006.245.08:22:26.83#ibcon#read 6, iclass 32, count 0 2006.245.08:22:26.83#ibcon#end of sib2, iclass 32, count 0 2006.245.08:22:26.83#ibcon#*after write, iclass 32, count 0 2006.245.08:22:26.83#ibcon#*before return 0, iclass 32, count 0 2006.245.08:22:26.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:26.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.245.08:22:26.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.245.08:22:26.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.245.08:22:26.83$vc4f8/vbbw=wide 2006.245.08:22:26.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.245.08:22:26.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.245.08:22:26.83#ibcon#ireg 8 cls_cnt 0 2006.245.08:22:26.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:22:26.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:22:26.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:22:26.90#ibcon#enter wrdev, iclass 34, count 0 2006.245.08:22:26.90#ibcon#first serial, iclass 34, count 0 2006.245.08:22:26.90#ibcon#enter sib2, iclass 34, count 0 2006.245.08:22:26.90#ibcon#flushed, iclass 34, count 0 2006.245.08:22:26.90#ibcon#about to write, iclass 34, count 0 2006.245.08:22:26.90#ibcon#wrote, iclass 34, count 0 2006.245.08:22:26.90#ibcon#about to read 3, iclass 34, count 0 2006.245.08:22:26.92#ibcon#read 3, iclass 34, count 0 2006.245.08:22:26.92#ibcon#about to read 4, iclass 34, count 0 2006.245.08:22:26.92#ibcon#read 4, iclass 34, count 0 2006.245.08:22:26.92#ibcon#about to read 5, iclass 34, count 0 2006.245.08:22:26.92#ibcon#read 5, iclass 34, count 0 2006.245.08:22:26.92#ibcon#about to read 6, iclass 34, count 0 2006.245.08:22:26.92#ibcon#read 6, iclass 34, count 0 2006.245.08:22:26.92#ibcon#end of sib2, iclass 34, count 0 2006.245.08:22:26.92#ibcon#*mode == 0, iclass 34, count 0 2006.245.08:22:26.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.245.08:22:26.92#ibcon#[27=BW32\r\n] 2006.245.08:22:26.92#ibcon#*before write, iclass 34, count 0 2006.245.08:22:26.92#ibcon#enter sib2, iclass 34, count 0 2006.245.08:22:26.92#ibcon#flushed, iclass 34, count 0 2006.245.08:22:26.92#ibcon#about to write, iclass 34, count 0 2006.245.08:22:26.92#ibcon#wrote, iclass 34, count 0 2006.245.08:22:26.92#ibcon#about to read 3, iclass 34, count 0 2006.245.08:22:26.95#ibcon#read 3, iclass 34, count 0 2006.245.08:22:26.95#ibcon#about to read 4, iclass 34, count 0 2006.245.08:22:26.95#ibcon#read 4, iclass 34, count 0 2006.245.08:22:26.95#ibcon#about to read 5, iclass 34, count 0 2006.245.08:22:26.95#ibcon#read 5, iclass 34, count 0 2006.245.08:22:26.95#ibcon#about to read 6, iclass 34, count 0 2006.245.08:22:26.95#ibcon#read 6, iclass 34, count 0 2006.245.08:22:26.95#ibcon#end of sib2, iclass 34, count 0 2006.245.08:22:26.95#ibcon#*after write, iclass 34, count 0 2006.245.08:22:26.95#ibcon#*before return 0, iclass 34, count 0 2006.245.08:22:26.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:22:26.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.245.08:22:26.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.245.08:22:26.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.245.08:22:26.95$4f8m12a/ifd4f 2006.245.08:22:26.95$ifd4f/lo= 2006.245.08:22:26.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:22:26.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:22:26.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:22:26.95$ifd4f/patch= 2006.245.08:22:26.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:22:26.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:22:26.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:22:26.95$4f8m12a/"form=m,16.000,1:2 2006.245.08:22:26.95$4f8m12a/"tpicd 2006.245.08:22:26.95$4f8m12a/echo=off 2006.245.08:22:26.95$4f8m12a/xlog=off 2006.245.08:22:26.95:!2006.245.08:24:30 2006.245.08:22:29.13#trakl#Source acquired 2006.245.08:22:29.13#flagr#flagr/antenna,acquired 2006.245.08:24:30.00:preob 2006.245.08:24:30.14/onsource/TRACKING 2006.245.08:24:30.14:!2006.245.08:24:40 2006.245.08:24:40.00:data_valid=on 2006.245.08:24:40.00:midob 2006.245.08:24:41.14/onsource/TRACKING 2006.245.08:24:41.14/wx/26.65,1004.5,76 2006.245.08:24:41.26/cable/+6.4124E-03 2006.245.08:24:42.35/va/01,08,usb,yes,31,33 2006.245.08:24:42.35/va/02,07,usb,yes,31,32 2006.245.08:24:42.35/va/03,06,usb,yes,33,33 2006.245.08:24:42.35/va/04,07,usb,yes,32,35 2006.245.08:24:42.35/va/05,07,usb,yes,35,36 2006.245.08:24:42.35/va/06,07,usb,yes,30,30 2006.245.08:24:42.35/va/07,07,usb,yes,30,30 2006.245.08:24:42.35/va/08,08,usb,yes,26,26 2006.245.08:24:42.58/valo/01,532.99,yes,locked 2006.245.08:24:42.58/valo/02,572.99,yes,locked 2006.245.08:24:42.58/valo/03,672.99,yes,locked 2006.245.08:24:42.58/valo/04,832.99,yes,locked 2006.245.08:24:42.58/valo/05,652.99,yes,locked 2006.245.08:24:42.58/valo/06,772.99,yes,locked 2006.245.08:24:42.58/valo/07,832.99,yes,locked 2006.245.08:24:42.58/valo/08,852.99,yes,locked 2006.245.08:24:43.67/vb/01,04,usb,yes,31,29 2006.245.08:24:43.67/vb/02,04,usb,yes,33,34 2006.245.08:24:43.67/vb/03,04,usb,yes,29,33 2006.245.08:24:43.67/vb/04,04,usb,yes,30,30 2006.245.08:24:43.67/vb/05,03,usb,yes,35,40 2006.245.08:24:43.67/vb/06,03,usb,yes,36,39 2006.245.08:24:43.67/vb/07,04,usb,yes,31,31 2006.245.08:24:43.67/vb/08,03,usb,yes,36,40 2006.245.08:24:43.91/vblo/01,632.99,yes,locked 2006.245.08:24:43.91/vblo/02,640.99,yes,locked 2006.245.08:24:43.91/vblo/03,656.99,yes,locked 2006.245.08:24:43.91/vblo/04,712.99,yes,locked 2006.245.08:24:43.91/vblo/05,744.99,yes,locked 2006.245.08:24:43.91/vblo/06,752.99,yes,locked 2006.245.08:24:43.91/vblo/07,734.99,yes,locked 2006.245.08:24:43.91/vblo/08,744.99,yes,locked 2006.245.08:24:44.06/vabw/8 2006.245.08:24:44.21/vbbw/8 2006.245.08:24:44.30/xfe/off,on,13.2 2006.245.08:24:44.67/ifatt/23,28,28,28 2006.245.08:24:45.08/fmout-gps/S +4.33E-07 2006.245.08:24:45.12:!2006.245.08:25:40 2006.245.08:25:40.00:data_valid=off 2006.245.08:25:40.00:postob 2006.245.08:25:40.10/cable/+6.4105E-03 2006.245.08:25:40.10/wx/26.63,1004.5,76 2006.245.08:25:41.08/fmout-gps/S +4.30E-07 2006.245.08:25:41.08:scan_name=245-0826,k06245,60 2006.245.08:25:41.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.245.08:25:41.14#flagr#flagr/antenna,new-source 2006.245.08:25:42.14:checkk5 2006.245.08:25:42.73/chk_autoobs//k5ts1/ autoobs is running! 2006.245.08:25:43.15/chk_autoobs//k5ts2/ autoobs is running! 2006.245.08:25:43.55/chk_autoobs//k5ts3/ autoobs is running! 2006.245.08:25:43.96/chk_autoobs//k5ts4/ autoobs is running! 2006.245.08:25:45.15/chk_obsdata//k5ts1/T2450824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:25:45.58/chk_obsdata//k5ts2/T2450824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:25:46.23/chk_obsdata//k5ts3/T2450824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:25:46.65/chk_obsdata//k5ts4/T2450824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.245.08:25:47.65/k5log//k5ts1_log_newline 2006.245.08:25:48.65/k5log//k5ts2_log_newline 2006.245.08:25:49.51/k5log//k5ts3_log_newline 2006.245.08:25:50.31/k5log//k5ts4_log_newline 2006.245.08:25:50.33/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:25:50.33:4f8m12a=3 2006.245.08:25:50.33$4f8m12a/echo=on 2006.245.08:25:50.33$4f8m12a/pcalon 2006.245.08:25:50.33$pcalon/"no phase cal control is implemented here 2006.245.08:25:50.33$4f8m12a/"tpicd=stop 2006.245.08:25:50.33$4f8m12a/vc4f8 2006.245.08:25:50.33$vc4f8/valo=1,532.99 2006.245.08:25:50.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:25:50.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:25:50.34#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:50.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:50.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:50.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:50.34#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:25:50.34#ibcon#first serial, iclass 7, count 0 2006.245.08:25:50.34#ibcon#enter sib2, iclass 7, count 0 2006.245.08:25:50.34#ibcon#flushed, iclass 7, count 0 2006.245.08:25:50.34#ibcon#about to write, iclass 7, count 0 2006.245.08:25:50.34#ibcon#wrote, iclass 7, count 0 2006.245.08:25:50.34#ibcon#about to read 3, iclass 7, count 0 2006.245.08:25:50.38#ibcon#read 3, iclass 7, count 0 2006.245.08:25:50.38#ibcon#about to read 4, iclass 7, count 0 2006.245.08:25:50.38#ibcon#read 4, iclass 7, count 0 2006.245.08:25:50.38#ibcon#about to read 5, iclass 7, count 0 2006.245.08:25:50.38#ibcon#read 5, iclass 7, count 0 2006.245.08:25:50.38#ibcon#about to read 6, iclass 7, count 0 2006.245.08:25:50.38#ibcon#read 6, iclass 7, count 0 2006.245.08:25:50.38#ibcon#end of sib2, iclass 7, count 0 2006.245.08:25:50.38#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:25:50.38#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:25:50.38#ibcon#[26=FRQ=01,532.99\r\n] 2006.245.08:25:50.38#ibcon#*before write, iclass 7, count 0 2006.245.08:25:50.38#ibcon#enter sib2, iclass 7, count 0 2006.245.08:25:50.38#ibcon#flushed, iclass 7, count 0 2006.245.08:25:50.38#ibcon#about to write, iclass 7, count 0 2006.245.08:25:50.38#ibcon#wrote, iclass 7, count 0 2006.245.08:25:50.38#ibcon#about to read 3, iclass 7, count 0 2006.245.08:25:50.43#ibcon#read 3, iclass 7, count 0 2006.245.08:25:50.43#ibcon#about to read 4, iclass 7, count 0 2006.245.08:25:50.43#ibcon#read 4, iclass 7, count 0 2006.245.08:25:50.43#ibcon#about to read 5, iclass 7, count 0 2006.245.08:25:50.43#ibcon#read 5, iclass 7, count 0 2006.245.08:25:50.43#ibcon#about to read 6, iclass 7, count 0 2006.245.08:25:50.43#ibcon#read 6, iclass 7, count 0 2006.245.08:25:50.43#ibcon#end of sib2, iclass 7, count 0 2006.245.08:25:50.43#ibcon#*after write, iclass 7, count 0 2006.245.08:25:50.43#ibcon#*before return 0, iclass 7, count 0 2006.245.08:25:50.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:50.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:50.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:25:50.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:25:50.43$vc4f8/va=1,8 2006.245.08:25:50.43#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:25:50.43#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:25:50.43#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:50.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:50.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:50.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:50.43#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:25:50.43#ibcon#first serial, iclass 11, count 2 2006.245.08:25:50.43#ibcon#enter sib2, iclass 11, count 2 2006.245.08:25:50.43#ibcon#flushed, iclass 11, count 2 2006.245.08:25:50.43#ibcon#about to write, iclass 11, count 2 2006.245.08:25:50.43#ibcon#wrote, iclass 11, count 2 2006.245.08:25:50.43#ibcon#about to read 3, iclass 11, count 2 2006.245.08:25:50.45#ibcon#read 3, iclass 11, count 2 2006.245.08:25:50.45#ibcon#about to read 4, iclass 11, count 2 2006.245.08:25:50.45#ibcon#read 4, iclass 11, count 2 2006.245.08:25:50.45#ibcon#about to read 5, iclass 11, count 2 2006.245.08:25:50.45#ibcon#read 5, iclass 11, count 2 2006.245.08:25:50.45#ibcon#about to read 6, iclass 11, count 2 2006.245.08:25:50.45#ibcon#read 6, iclass 11, count 2 2006.245.08:25:50.45#ibcon#end of sib2, iclass 11, count 2 2006.245.08:25:50.45#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:25:50.45#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:25:50.45#ibcon#[25=AT01-08\r\n] 2006.245.08:25:50.45#ibcon#*before write, iclass 11, count 2 2006.245.08:25:50.45#ibcon#enter sib2, iclass 11, count 2 2006.245.08:25:50.45#ibcon#flushed, iclass 11, count 2 2006.245.08:25:50.45#ibcon#about to write, iclass 11, count 2 2006.245.08:25:50.45#ibcon#wrote, iclass 11, count 2 2006.245.08:25:50.45#ibcon#about to read 3, iclass 11, count 2 2006.245.08:25:50.48#ibcon#read 3, iclass 11, count 2 2006.245.08:25:50.48#ibcon#about to read 4, iclass 11, count 2 2006.245.08:25:50.48#ibcon#read 4, iclass 11, count 2 2006.245.08:25:50.48#ibcon#about to read 5, iclass 11, count 2 2006.245.08:25:50.48#ibcon#read 5, iclass 11, count 2 2006.245.08:25:50.48#ibcon#about to read 6, iclass 11, count 2 2006.245.08:25:50.48#ibcon#read 6, iclass 11, count 2 2006.245.08:25:50.48#ibcon#end of sib2, iclass 11, count 2 2006.245.08:25:50.48#ibcon#*after write, iclass 11, count 2 2006.245.08:25:50.48#ibcon#*before return 0, iclass 11, count 2 2006.245.08:25:50.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:50.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:50.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:25:50.48#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:50.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:50.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:50.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:50.60#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:25:50.60#ibcon#first serial, iclass 11, count 0 2006.245.08:25:50.60#ibcon#enter sib2, iclass 11, count 0 2006.245.08:25:50.60#ibcon#flushed, iclass 11, count 0 2006.245.08:25:50.60#ibcon#about to write, iclass 11, count 0 2006.245.08:25:50.60#ibcon#wrote, iclass 11, count 0 2006.245.08:25:50.60#ibcon#about to read 3, iclass 11, count 0 2006.245.08:25:50.62#ibcon#read 3, iclass 11, count 0 2006.245.08:25:50.62#ibcon#about to read 4, iclass 11, count 0 2006.245.08:25:50.62#ibcon#read 4, iclass 11, count 0 2006.245.08:25:50.62#ibcon#about to read 5, iclass 11, count 0 2006.245.08:25:50.62#ibcon#read 5, iclass 11, count 0 2006.245.08:25:50.62#ibcon#about to read 6, iclass 11, count 0 2006.245.08:25:50.62#ibcon#read 6, iclass 11, count 0 2006.245.08:25:50.62#ibcon#end of sib2, iclass 11, count 0 2006.245.08:25:50.62#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:25:50.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:25:50.62#ibcon#[25=USB\r\n] 2006.245.08:25:50.62#ibcon#*before write, iclass 11, count 0 2006.245.08:25:50.62#ibcon#enter sib2, iclass 11, count 0 2006.245.08:25:50.62#ibcon#flushed, iclass 11, count 0 2006.245.08:25:50.62#ibcon#about to write, iclass 11, count 0 2006.245.08:25:50.62#ibcon#wrote, iclass 11, count 0 2006.245.08:25:50.62#ibcon#about to read 3, iclass 11, count 0 2006.245.08:25:50.65#ibcon#read 3, iclass 11, count 0 2006.245.08:25:50.65#ibcon#about to read 4, iclass 11, count 0 2006.245.08:25:50.65#ibcon#read 4, iclass 11, count 0 2006.245.08:25:50.65#ibcon#about to read 5, iclass 11, count 0 2006.245.08:25:50.65#ibcon#read 5, iclass 11, count 0 2006.245.08:25:50.65#ibcon#about to read 6, iclass 11, count 0 2006.245.08:25:50.65#ibcon#read 6, iclass 11, count 0 2006.245.08:25:50.65#ibcon#end of sib2, iclass 11, count 0 2006.245.08:25:50.65#ibcon#*after write, iclass 11, count 0 2006.245.08:25:50.65#ibcon#*before return 0, iclass 11, count 0 2006.245.08:25:50.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:50.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:50.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:25:50.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:25:50.65$vc4f8/valo=2,572.99 2006.245.08:25:50.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:25:50.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:25:50.65#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:50.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:50.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:50.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:50.65#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:25:50.65#ibcon#first serial, iclass 13, count 0 2006.245.08:25:50.65#ibcon#enter sib2, iclass 13, count 0 2006.245.08:25:50.65#ibcon#flushed, iclass 13, count 0 2006.245.08:25:50.65#ibcon#about to write, iclass 13, count 0 2006.245.08:25:50.65#ibcon#wrote, iclass 13, count 0 2006.245.08:25:50.65#ibcon#about to read 3, iclass 13, count 0 2006.245.08:25:50.67#ibcon#read 3, iclass 13, count 0 2006.245.08:25:50.67#ibcon#about to read 4, iclass 13, count 0 2006.245.08:25:50.67#ibcon#read 4, iclass 13, count 0 2006.245.08:25:50.67#ibcon#about to read 5, iclass 13, count 0 2006.245.08:25:50.67#ibcon#read 5, iclass 13, count 0 2006.245.08:25:50.67#ibcon#about to read 6, iclass 13, count 0 2006.245.08:25:50.67#ibcon#read 6, iclass 13, count 0 2006.245.08:25:50.67#ibcon#end of sib2, iclass 13, count 0 2006.245.08:25:50.67#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:25:50.67#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:25:50.67#ibcon#[26=FRQ=02,572.99\r\n] 2006.245.08:25:50.67#ibcon#*before write, iclass 13, count 0 2006.245.08:25:50.67#ibcon#enter sib2, iclass 13, count 0 2006.245.08:25:50.67#ibcon#flushed, iclass 13, count 0 2006.245.08:25:50.67#ibcon#about to write, iclass 13, count 0 2006.245.08:25:50.67#ibcon#wrote, iclass 13, count 0 2006.245.08:25:50.67#ibcon#about to read 3, iclass 13, count 0 2006.245.08:25:50.72#ibcon#read 3, iclass 13, count 0 2006.245.08:25:50.72#ibcon#about to read 4, iclass 13, count 0 2006.245.08:25:50.72#ibcon#read 4, iclass 13, count 0 2006.245.08:25:50.72#ibcon#about to read 5, iclass 13, count 0 2006.245.08:25:50.72#ibcon#read 5, iclass 13, count 0 2006.245.08:25:50.72#ibcon#about to read 6, iclass 13, count 0 2006.245.08:25:50.72#ibcon#read 6, iclass 13, count 0 2006.245.08:25:50.72#ibcon#end of sib2, iclass 13, count 0 2006.245.08:25:50.72#ibcon#*after write, iclass 13, count 0 2006.245.08:25:50.72#ibcon#*before return 0, iclass 13, count 0 2006.245.08:25:50.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:50.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:50.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:25:50.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:25:50.72$vc4f8/va=2,7 2006.245.08:25:50.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:25:50.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:25:50.72#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:50.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:50.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:50.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:50.77#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:25:50.77#ibcon#first serial, iclass 15, count 2 2006.245.08:25:50.77#ibcon#enter sib2, iclass 15, count 2 2006.245.08:25:50.77#ibcon#flushed, iclass 15, count 2 2006.245.08:25:50.77#ibcon#about to write, iclass 15, count 2 2006.245.08:25:50.77#ibcon#wrote, iclass 15, count 2 2006.245.08:25:50.77#ibcon#about to read 3, iclass 15, count 2 2006.245.08:25:50.79#ibcon#read 3, iclass 15, count 2 2006.245.08:25:50.79#ibcon#about to read 4, iclass 15, count 2 2006.245.08:25:50.79#ibcon#read 4, iclass 15, count 2 2006.245.08:25:50.79#ibcon#about to read 5, iclass 15, count 2 2006.245.08:25:50.79#ibcon#read 5, iclass 15, count 2 2006.245.08:25:50.79#ibcon#about to read 6, iclass 15, count 2 2006.245.08:25:50.79#ibcon#read 6, iclass 15, count 2 2006.245.08:25:50.79#ibcon#end of sib2, iclass 15, count 2 2006.245.08:25:50.79#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:25:50.79#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:25:50.79#ibcon#[25=AT02-07\r\n] 2006.245.08:25:50.79#ibcon#*before write, iclass 15, count 2 2006.245.08:25:50.79#ibcon#enter sib2, iclass 15, count 2 2006.245.08:25:50.79#ibcon#flushed, iclass 15, count 2 2006.245.08:25:50.79#ibcon#about to write, iclass 15, count 2 2006.245.08:25:50.79#ibcon#wrote, iclass 15, count 2 2006.245.08:25:50.79#ibcon#about to read 3, iclass 15, count 2 2006.245.08:25:50.82#ibcon#read 3, iclass 15, count 2 2006.245.08:25:50.82#ibcon#about to read 4, iclass 15, count 2 2006.245.08:25:50.82#ibcon#read 4, iclass 15, count 2 2006.245.08:25:50.82#ibcon#about to read 5, iclass 15, count 2 2006.245.08:25:50.82#ibcon#read 5, iclass 15, count 2 2006.245.08:25:50.82#ibcon#about to read 6, iclass 15, count 2 2006.245.08:25:50.82#ibcon#read 6, iclass 15, count 2 2006.245.08:25:50.82#ibcon#end of sib2, iclass 15, count 2 2006.245.08:25:50.82#ibcon#*after write, iclass 15, count 2 2006.245.08:25:50.82#ibcon#*before return 0, iclass 15, count 2 2006.245.08:25:50.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:50.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:50.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:25:50.82#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:50.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:50.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:50.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:50.94#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:25:50.94#ibcon#first serial, iclass 15, count 0 2006.245.08:25:50.94#ibcon#enter sib2, iclass 15, count 0 2006.245.08:25:50.94#ibcon#flushed, iclass 15, count 0 2006.245.08:25:50.94#ibcon#about to write, iclass 15, count 0 2006.245.08:25:50.94#ibcon#wrote, iclass 15, count 0 2006.245.08:25:50.94#ibcon#about to read 3, iclass 15, count 0 2006.245.08:25:50.96#ibcon#read 3, iclass 15, count 0 2006.245.08:25:50.96#ibcon#about to read 4, iclass 15, count 0 2006.245.08:25:50.96#ibcon#read 4, iclass 15, count 0 2006.245.08:25:50.96#ibcon#about to read 5, iclass 15, count 0 2006.245.08:25:50.96#ibcon#read 5, iclass 15, count 0 2006.245.08:25:50.96#ibcon#about to read 6, iclass 15, count 0 2006.245.08:25:50.96#ibcon#read 6, iclass 15, count 0 2006.245.08:25:50.96#ibcon#end of sib2, iclass 15, count 0 2006.245.08:25:50.96#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:25:50.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:25:50.96#ibcon#[25=USB\r\n] 2006.245.08:25:50.96#ibcon#*before write, iclass 15, count 0 2006.245.08:25:50.96#ibcon#enter sib2, iclass 15, count 0 2006.245.08:25:50.96#ibcon#flushed, iclass 15, count 0 2006.245.08:25:50.96#ibcon#about to write, iclass 15, count 0 2006.245.08:25:50.96#ibcon#wrote, iclass 15, count 0 2006.245.08:25:50.96#ibcon#about to read 3, iclass 15, count 0 2006.245.08:25:50.99#ibcon#read 3, iclass 15, count 0 2006.245.08:25:50.99#ibcon#about to read 4, iclass 15, count 0 2006.245.08:25:50.99#ibcon#read 4, iclass 15, count 0 2006.245.08:25:50.99#ibcon#about to read 5, iclass 15, count 0 2006.245.08:25:50.99#ibcon#read 5, iclass 15, count 0 2006.245.08:25:50.99#ibcon#about to read 6, iclass 15, count 0 2006.245.08:25:50.99#ibcon#read 6, iclass 15, count 0 2006.245.08:25:50.99#ibcon#end of sib2, iclass 15, count 0 2006.245.08:25:50.99#ibcon#*after write, iclass 15, count 0 2006.245.08:25:50.99#ibcon#*before return 0, iclass 15, count 0 2006.245.08:25:50.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:50.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:50.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:25:50.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:25:50.99$vc4f8/valo=3,672.99 2006.245.08:25:50.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:25:50.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:25:50.99#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:50.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:50.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:50.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:50.99#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:25:50.99#ibcon#first serial, iclass 17, count 0 2006.245.08:25:50.99#ibcon#enter sib2, iclass 17, count 0 2006.245.08:25:50.99#ibcon#flushed, iclass 17, count 0 2006.245.08:25:50.99#ibcon#about to write, iclass 17, count 0 2006.245.08:25:50.99#ibcon#wrote, iclass 17, count 0 2006.245.08:25:50.99#ibcon#about to read 3, iclass 17, count 0 2006.245.08:25:51.01#ibcon#read 3, iclass 17, count 0 2006.245.08:25:51.01#ibcon#about to read 4, iclass 17, count 0 2006.245.08:25:51.01#ibcon#read 4, iclass 17, count 0 2006.245.08:25:51.01#ibcon#about to read 5, iclass 17, count 0 2006.245.08:25:51.01#ibcon#read 5, iclass 17, count 0 2006.245.08:25:51.01#ibcon#about to read 6, iclass 17, count 0 2006.245.08:25:51.01#ibcon#read 6, iclass 17, count 0 2006.245.08:25:51.01#ibcon#end of sib2, iclass 17, count 0 2006.245.08:25:51.01#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:25:51.01#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:25:51.01#ibcon#[26=FRQ=03,672.99\r\n] 2006.245.08:25:51.01#ibcon#*before write, iclass 17, count 0 2006.245.08:25:51.01#ibcon#enter sib2, iclass 17, count 0 2006.245.08:25:51.01#ibcon#flushed, iclass 17, count 0 2006.245.08:25:51.01#ibcon#about to write, iclass 17, count 0 2006.245.08:25:51.01#ibcon#wrote, iclass 17, count 0 2006.245.08:25:51.01#ibcon#about to read 3, iclass 17, count 0 2006.245.08:25:51.06#ibcon#read 3, iclass 17, count 0 2006.245.08:25:51.06#ibcon#about to read 4, iclass 17, count 0 2006.245.08:25:51.06#ibcon#read 4, iclass 17, count 0 2006.245.08:25:51.06#ibcon#about to read 5, iclass 17, count 0 2006.245.08:25:51.06#ibcon#read 5, iclass 17, count 0 2006.245.08:25:51.06#ibcon#about to read 6, iclass 17, count 0 2006.245.08:25:51.06#ibcon#read 6, iclass 17, count 0 2006.245.08:25:51.06#ibcon#end of sib2, iclass 17, count 0 2006.245.08:25:51.06#ibcon#*after write, iclass 17, count 0 2006.245.08:25:51.06#ibcon#*before return 0, iclass 17, count 0 2006.245.08:25:51.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:51.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:51.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:25:51.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:25:51.06$vc4f8/va=3,6 2006.245.08:25:51.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:25:51.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:25:51.06#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:51.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:51.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:51.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:51.11#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:25:51.11#ibcon#first serial, iclass 19, count 2 2006.245.08:25:51.11#ibcon#enter sib2, iclass 19, count 2 2006.245.08:25:51.11#ibcon#flushed, iclass 19, count 2 2006.245.08:25:51.11#ibcon#about to write, iclass 19, count 2 2006.245.08:25:51.11#ibcon#wrote, iclass 19, count 2 2006.245.08:25:51.11#ibcon#about to read 3, iclass 19, count 2 2006.245.08:25:51.13#ibcon#read 3, iclass 19, count 2 2006.245.08:25:51.13#ibcon#about to read 4, iclass 19, count 2 2006.245.08:25:51.13#ibcon#read 4, iclass 19, count 2 2006.245.08:25:51.13#ibcon#about to read 5, iclass 19, count 2 2006.245.08:25:51.13#ibcon#read 5, iclass 19, count 2 2006.245.08:25:51.13#ibcon#about to read 6, iclass 19, count 2 2006.245.08:25:51.13#ibcon#read 6, iclass 19, count 2 2006.245.08:25:51.13#ibcon#end of sib2, iclass 19, count 2 2006.245.08:25:51.13#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:25:51.13#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:25:51.13#ibcon#[25=AT03-06\r\n] 2006.245.08:25:51.13#ibcon#*before write, iclass 19, count 2 2006.245.08:25:51.13#ibcon#enter sib2, iclass 19, count 2 2006.245.08:25:51.13#ibcon#flushed, iclass 19, count 2 2006.245.08:25:51.13#ibcon#about to write, iclass 19, count 2 2006.245.08:25:51.13#ibcon#wrote, iclass 19, count 2 2006.245.08:25:51.13#ibcon#about to read 3, iclass 19, count 2 2006.245.08:25:51.16#ibcon#read 3, iclass 19, count 2 2006.245.08:25:51.16#ibcon#about to read 4, iclass 19, count 2 2006.245.08:25:51.16#ibcon#read 4, iclass 19, count 2 2006.245.08:25:51.16#ibcon#about to read 5, iclass 19, count 2 2006.245.08:25:51.16#ibcon#read 5, iclass 19, count 2 2006.245.08:25:51.16#ibcon#about to read 6, iclass 19, count 2 2006.245.08:25:51.16#ibcon#read 6, iclass 19, count 2 2006.245.08:25:51.16#ibcon#end of sib2, iclass 19, count 2 2006.245.08:25:51.16#ibcon#*after write, iclass 19, count 2 2006.245.08:25:51.16#ibcon#*before return 0, iclass 19, count 2 2006.245.08:25:51.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:51.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:51.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:25:51.16#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:51.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:51.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:51.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:51.28#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:25:51.28#ibcon#first serial, iclass 19, count 0 2006.245.08:25:51.28#ibcon#enter sib2, iclass 19, count 0 2006.245.08:25:51.28#ibcon#flushed, iclass 19, count 0 2006.245.08:25:51.28#ibcon#about to write, iclass 19, count 0 2006.245.08:25:51.28#ibcon#wrote, iclass 19, count 0 2006.245.08:25:51.28#ibcon#about to read 3, iclass 19, count 0 2006.245.08:25:51.30#ibcon#read 3, iclass 19, count 0 2006.245.08:25:51.30#ibcon#about to read 4, iclass 19, count 0 2006.245.08:25:51.30#ibcon#read 4, iclass 19, count 0 2006.245.08:25:51.30#ibcon#about to read 5, iclass 19, count 0 2006.245.08:25:51.30#ibcon#read 5, iclass 19, count 0 2006.245.08:25:51.30#ibcon#about to read 6, iclass 19, count 0 2006.245.08:25:51.30#ibcon#read 6, iclass 19, count 0 2006.245.08:25:51.30#ibcon#end of sib2, iclass 19, count 0 2006.245.08:25:51.30#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:25:51.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:25:51.30#ibcon#[25=USB\r\n] 2006.245.08:25:51.30#ibcon#*before write, iclass 19, count 0 2006.245.08:25:51.30#ibcon#enter sib2, iclass 19, count 0 2006.245.08:25:51.30#ibcon#flushed, iclass 19, count 0 2006.245.08:25:51.30#ibcon#about to write, iclass 19, count 0 2006.245.08:25:51.30#ibcon#wrote, iclass 19, count 0 2006.245.08:25:51.30#ibcon#about to read 3, iclass 19, count 0 2006.245.08:25:51.33#ibcon#read 3, iclass 19, count 0 2006.245.08:25:51.33#ibcon#about to read 4, iclass 19, count 0 2006.245.08:25:51.33#ibcon#read 4, iclass 19, count 0 2006.245.08:25:51.33#ibcon#about to read 5, iclass 19, count 0 2006.245.08:25:51.33#ibcon#read 5, iclass 19, count 0 2006.245.08:25:51.33#ibcon#about to read 6, iclass 19, count 0 2006.245.08:25:51.33#ibcon#read 6, iclass 19, count 0 2006.245.08:25:51.33#ibcon#end of sib2, iclass 19, count 0 2006.245.08:25:51.33#ibcon#*after write, iclass 19, count 0 2006.245.08:25:51.33#ibcon#*before return 0, iclass 19, count 0 2006.245.08:25:51.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:51.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:51.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:25:51.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:25:51.33$vc4f8/valo=4,832.99 2006.245.08:25:51.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:25:51.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:25:51.33#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:51.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:51.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:51.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:51.33#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:25:51.33#ibcon#first serial, iclass 21, count 0 2006.245.08:25:51.33#ibcon#enter sib2, iclass 21, count 0 2006.245.08:25:51.33#ibcon#flushed, iclass 21, count 0 2006.245.08:25:51.33#ibcon#about to write, iclass 21, count 0 2006.245.08:25:51.33#ibcon#wrote, iclass 21, count 0 2006.245.08:25:51.33#ibcon#about to read 3, iclass 21, count 0 2006.245.08:25:51.35#ibcon#read 3, iclass 21, count 0 2006.245.08:25:51.35#ibcon#about to read 4, iclass 21, count 0 2006.245.08:25:51.35#ibcon#read 4, iclass 21, count 0 2006.245.08:25:51.35#ibcon#about to read 5, iclass 21, count 0 2006.245.08:25:51.35#ibcon#read 5, iclass 21, count 0 2006.245.08:25:51.35#ibcon#about to read 6, iclass 21, count 0 2006.245.08:25:51.35#ibcon#read 6, iclass 21, count 0 2006.245.08:25:51.35#ibcon#end of sib2, iclass 21, count 0 2006.245.08:25:51.35#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:25:51.35#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:25:51.35#ibcon#[26=FRQ=04,832.99\r\n] 2006.245.08:25:51.35#ibcon#*before write, iclass 21, count 0 2006.245.08:25:51.35#ibcon#enter sib2, iclass 21, count 0 2006.245.08:25:51.35#ibcon#flushed, iclass 21, count 0 2006.245.08:25:51.35#ibcon#about to write, iclass 21, count 0 2006.245.08:25:51.35#ibcon#wrote, iclass 21, count 0 2006.245.08:25:51.35#ibcon#about to read 3, iclass 21, count 0 2006.245.08:25:51.40#ibcon#read 3, iclass 21, count 0 2006.245.08:25:51.40#ibcon#about to read 4, iclass 21, count 0 2006.245.08:25:51.40#ibcon#read 4, iclass 21, count 0 2006.245.08:25:51.40#ibcon#about to read 5, iclass 21, count 0 2006.245.08:25:51.40#ibcon#read 5, iclass 21, count 0 2006.245.08:25:51.40#ibcon#about to read 6, iclass 21, count 0 2006.245.08:25:51.40#ibcon#read 6, iclass 21, count 0 2006.245.08:25:51.40#ibcon#end of sib2, iclass 21, count 0 2006.245.08:25:51.40#ibcon#*after write, iclass 21, count 0 2006.245.08:25:51.40#ibcon#*before return 0, iclass 21, count 0 2006.245.08:25:51.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:51.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:51.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:25:51.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:25:51.40$vc4f8/va=4,7 2006.245.08:25:51.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.08:25:51.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.08:25:51.40#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:51.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:51.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:51.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:51.45#ibcon#enter wrdev, iclass 23, count 2 2006.245.08:25:51.45#ibcon#first serial, iclass 23, count 2 2006.245.08:25:51.45#ibcon#enter sib2, iclass 23, count 2 2006.245.08:25:51.45#ibcon#flushed, iclass 23, count 2 2006.245.08:25:51.45#ibcon#about to write, iclass 23, count 2 2006.245.08:25:51.45#ibcon#wrote, iclass 23, count 2 2006.245.08:25:51.45#ibcon#about to read 3, iclass 23, count 2 2006.245.08:25:51.47#ibcon#read 3, iclass 23, count 2 2006.245.08:25:51.47#ibcon#about to read 4, iclass 23, count 2 2006.245.08:25:51.47#ibcon#read 4, iclass 23, count 2 2006.245.08:25:51.47#ibcon#about to read 5, iclass 23, count 2 2006.245.08:25:51.47#ibcon#read 5, iclass 23, count 2 2006.245.08:25:51.47#ibcon#about to read 6, iclass 23, count 2 2006.245.08:25:51.47#ibcon#read 6, iclass 23, count 2 2006.245.08:25:51.47#ibcon#end of sib2, iclass 23, count 2 2006.245.08:25:51.47#ibcon#*mode == 0, iclass 23, count 2 2006.245.08:25:51.47#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.08:25:51.47#ibcon#[25=AT04-07\r\n] 2006.245.08:25:51.47#ibcon#*before write, iclass 23, count 2 2006.245.08:25:51.47#ibcon#enter sib2, iclass 23, count 2 2006.245.08:25:51.47#ibcon#flushed, iclass 23, count 2 2006.245.08:25:51.47#ibcon#about to write, iclass 23, count 2 2006.245.08:25:51.47#ibcon#wrote, iclass 23, count 2 2006.245.08:25:51.47#ibcon#about to read 3, iclass 23, count 2 2006.245.08:25:51.50#ibcon#read 3, iclass 23, count 2 2006.245.08:25:51.50#ibcon#about to read 4, iclass 23, count 2 2006.245.08:25:51.50#ibcon#read 4, iclass 23, count 2 2006.245.08:25:51.50#ibcon#about to read 5, iclass 23, count 2 2006.245.08:25:51.50#ibcon#read 5, iclass 23, count 2 2006.245.08:25:51.50#ibcon#about to read 6, iclass 23, count 2 2006.245.08:25:51.50#ibcon#read 6, iclass 23, count 2 2006.245.08:25:51.50#ibcon#end of sib2, iclass 23, count 2 2006.245.08:25:51.50#ibcon#*after write, iclass 23, count 2 2006.245.08:25:51.50#ibcon#*before return 0, iclass 23, count 2 2006.245.08:25:51.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:51.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:51.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.08:25:51.50#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:51.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:51.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:51.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:51.62#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:25:51.62#ibcon#first serial, iclass 23, count 0 2006.245.08:25:51.62#ibcon#enter sib2, iclass 23, count 0 2006.245.08:25:51.62#ibcon#flushed, iclass 23, count 0 2006.245.08:25:51.62#ibcon#about to write, iclass 23, count 0 2006.245.08:25:51.62#ibcon#wrote, iclass 23, count 0 2006.245.08:25:51.62#ibcon#about to read 3, iclass 23, count 0 2006.245.08:25:51.64#ibcon#read 3, iclass 23, count 0 2006.245.08:25:51.64#ibcon#about to read 4, iclass 23, count 0 2006.245.08:25:51.64#ibcon#read 4, iclass 23, count 0 2006.245.08:25:51.64#ibcon#about to read 5, iclass 23, count 0 2006.245.08:25:51.64#ibcon#read 5, iclass 23, count 0 2006.245.08:25:51.64#ibcon#about to read 6, iclass 23, count 0 2006.245.08:25:51.64#ibcon#read 6, iclass 23, count 0 2006.245.08:25:51.64#ibcon#end of sib2, iclass 23, count 0 2006.245.08:25:51.64#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:25:51.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:25:51.64#ibcon#[25=USB\r\n] 2006.245.08:25:51.64#ibcon#*before write, iclass 23, count 0 2006.245.08:25:51.64#ibcon#enter sib2, iclass 23, count 0 2006.245.08:25:51.64#ibcon#flushed, iclass 23, count 0 2006.245.08:25:51.64#ibcon#about to write, iclass 23, count 0 2006.245.08:25:51.64#ibcon#wrote, iclass 23, count 0 2006.245.08:25:51.64#ibcon#about to read 3, iclass 23, count 0 2006.245.08:25:51.67#ibcon#read 3, iclass 23, count 0 2006.245.08:25:51.67#ibcon#about to read 4, iclass 23, count 0 2006.245.08:25:51.67#ibcon#read 4, iclass 23, count 0 2006.245.08:25:51.67#ibcon#about to read 5, iclass 23, count 0 2006.245.08:25:51.67#ibcon#read 5, iclass 23, count 0 2006.245.08:25:51.67#ibcon#about to read 6, iclass 23, count 0 2006.245.08:25:51.67#ibcon#read 6, iclass 23, count 0 2006.245.08:25:51.67#ibcon#end of sib2, iclass 23, count 0 2006.245.08:25:51.67#ibcon#*after write, iclass 23, count 0 2006.245.08:25:51.67#ibcon#*before return 0, iclass 23, count 0 2006.245.08:25:51.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:51.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:51.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:25:51.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:25:51.67$vc4f8/valo=5,652.99 2006.245.08:25:51.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.08:25:51.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.08:25:51.67#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:51.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:51.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:51.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:51.67#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:25:51.67#ibcon#first serial, iclass 25, count 0 2006.245.08:25:51.67#ibcon#enter sib2, iclass 25, count 0 2006.245.08:25:51.67#ibcon#flushed, iclass 25, count 0 2006.245.08:25:51.67#ibcon#about to write, iclass 25, count 0 2006.245.08:25:51.67#ibcon#wrote, iclass 25, count 0 2006.245.08:25:51.67#ibcon#about to read 3, iclass 25, count 0 2006.245.08:25:51.69#ibcon#read 3, iclass 25, count 0 2006.245.08:25:51.69#ibcon#about to read 4, iclass 25, count 0 2006.245.08:25:51.69#ibcon#read 4, iclass 25, count 0 2006.245.08:25:51.69#ibcon#about to read 5, iclass 25, count 0 2006.245.08:25:51.69#ibcon#read 5, iclass 25, count 0 2006.245.08:25:51.69#ibcon#about to read 6, iclass 25, count 0 2006.245.08:25:51.69#ibcon#read 6, iclass 25, count 0 2006.245.08:25:51.69#ibcon#end of sib2, iclass 25, count 0 2006.245.08:25:51.69#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:25:51.69#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:25:51.69#ibcon#[26=FRQ=05,652.99\r\n] 2006.245.08:25:51.69#ibcon#*before write, iclass 25, count 0 2006.245.08:25:51.69#ibcon#enter sib2, iclass 25, count 0 2006.245.08:25:51.69#ibcon#flushed, iclass 25, count 0 2006.245.08:25:51.69#ibcon#about to write, iclass 25, count 0 2006.245.08:25:51.69#ibcon#wrote, iclass 25, count 0 2006.245.08:25:51.69#ibcon#about to read 3, iclass 25, count 0 2006.245.08:25:51.73#ibcon#read 3, iclass 25, count 0 2006.245.08:25:51.73#ibcon#about to read 4, iclass 25, count 0 2006.245.08:25:51.73#ibcon#read 4, iclass 25, count 0 2006.245.08:25:51.73#ibcon#about to read 5, iclass 25, count 0 2006.245.08:25:51.73#ibcon#read 5, iclass 25, count 0 2006.245.08:25:51.73#ibcon#about to read 6, iclass 25, count 0 2006.245.08:25:51.73#ibcon#read 6, iclass 25, count 0 2006.245.08:25:51.73#ibcon#end of sib2, iclass 25, count 0 2006.245.08:25:51.73#ibcon#*after write, iclass 25, count 0 2006.245.08:25:51.73#ibcon#*before return 0, iclass 25, count 0 2006.245.08:25:51.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:51.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:51.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:25:51.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:25:51.73$vc4f8/va=5,7 2006.245.08:25:51.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.08:25:51.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.08:25:51.73#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:51.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:51.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:51.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:51.79#ibcon#enter wrdev, iclass 27, count 2 2006.245.08:25:51.79#ibcon#first serial, iclass 27, count 2 2006.245.08:25:51.79#ibcon#enter sib2, iclass 27, count 2 2006.245.08:25:51.79#ibcon#flushed, iclass 27, count 2 2006.245.08:25:51.79#ibcon#about to write, iclass 27, count 2 2006.245.08:25:51.79#ibcon#wrote, iclass 27, count 2 2006.245.08:25:51.79#ibcon#about to read 3, iclass 27, count 2 2006.245.08:25:51.81#ibcon#read 3, iclass 27, count 2 2006.245.08:25:51.81#ibcon#about to read 4, iclass 27, count 2 2006.245.08:25:51.81#ibcon#read 4, iclass 27, count 2 2006.245.08:25:51.81#ibcon#about to read 5, iclass 27, count 2 2006.245.08:25:51.81#ibcon#read 5, iclass 27, count 2 2006.245.08:25:51.81#ibcon#about to read 6, iclass 27, count 2 2006.245.08:25:51.81#ibcon#read 6, iclass 27, count 2 2006.245.08:25:51.81#ibcon#end of sib2, iclass 27, count 2 2006.245.08:25:51.81#ibcon#*mode == 0, iclass 27, count 2 2006.245.08:25:51.81#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.08:25:51.81#ibcon#[25=AT05-07\r\n] 2006.245.08:25:51.81#ibcon#*before write, iclass 27, count 2 2006.245.08:25:51.81#ibcon#enter sib2, iclass 27, count 2 2006.245.08:25:51.81#ibcon#flushed, iclass 27, count 2 2006.245.08:25:51.81#ibcon#about to write, iclass 27, count 2 2006.245.08:25:51.81#ibcon#wrote, iclass 27, count 2 2006.245.08:25:51.81#ibcon#about to read 3, iclass 27, count 2 2006.245.08:25:51.84#ibcon#read 3, iclass 27, count 2 2006.245.08:25:51.84#ibcon#about to read 4, iclass 27, count 2 2006.245.08:25:51.84#ibcon#read 4, iclass 27, count 2 2006.245.08:25:51.84#ibcon#about to read 5, iclass 27, count 2 2006.245.08:25:51.84#ibcon#read 5, iclass 27, count 2 2006.245.08:25:51.84#ibcon#about to read 6, iclass 27, count 2 2006.245.08:25:51.84#ibcon#read 6, iclass 27, count 2 2006.245.08:25:51.84#ibcon#end of sib2, iclass 27, count 2 2006.245.08:25:51.84#ibcon#*after write, iclass 27, count 2 2006.245.08:25:51.84#ibcon#*before return 0, iclass 27, count 2 2006.245.08:25:51.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:51.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:51.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.08:25:51.84#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:51.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:51.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:51.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:51.96#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:25:51.96#ibcon#first serial, iclass 27, count 0 2006.245.08:25:51.96#ibcon#enter sib2, iclass 27, count 0 2006.245.08:25:51.96#ibcon#flushed, iclass 27, count 0 2006.245.08:25:51.96#ibcon#about to write, iclass 27, count 0 2006.245.08:25:51.96#ibcon#wrote, iclass 27, count 0 2006.245.08:25:51.96#ibcon#about to read 3, iclass 27, count 0 2006.245.08:25:51.98#ibcon#read 3, iclass 27, count 0 2006.245.08:25:51.98#ibcon#about to read 4, iclass 27, count 0 2006.245.08:25:51.98#ibcon#read 4, iclass 27, count 0 2006.245.08:25:51.98#ibcon#about to read 5, iclass 27, count 0 2006.245.08:25:51.98#ibcon#read 5, iclass 27, count 0 2006.245.08:25:51.98#ibcon#about to read 6, iclass 27, count 0 2006.245.08:25:51.98#ibcon#read 6, iclass 27, count 0 2006.245.08:25:51.98#ibcon#end of sib2, iclass 27, count 0 2006.245.08:25:51.98#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:25:51.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:25:51.98#ibcon#[25=USB\r\n] 2006.245.08:25:51.98#ibcon#*before write, iclass 27, count 0 2006.245.08:25:51.98#ibcon#enter sib2, iclass 27, count 0 2006.245.08:25:51.98#ibcon#flushed, iclass 27, count 0 2006.245.08:25:51.98#ibcon#about to write, iclass 27, count 0 2006.245.08:25:51.98#ibcon#wrote, iclass 27, count 0 2006.245.08:25:51.98#ibcon#about to read 3, iclass 27, count 0 2006.245.08:25:52.01#ibcon#read 3, iclass 27, count 0 2006.245.08:25:52.01#ibcon#about to read 4, iclass 27, count 0 2006.245.08:25:52.01#ibcon#read 4, iclass 27, count 0 2006.245.08:25:52.01#ibcon#about to read 5, iclass 27, count 0 2006.245.08:25:52.01#ibcon#read 5, iclass 27, count 0 2006.245.08:25:52.01#ibcon#about to read 6, iclass 27, count 0 2006.245.08:25:52.01#ibcon#read 6, iclass 27, count 0 2006.245.08:25:52.01#ibcon#end of sib2, iclass 27, count 0 2006.245.08:25:52.01#ibcon#*after write, iclass 27, count 0 2006.245.08:25:52.01#ibcon#*before return 0, iclass 27, count 0 2006.245.08:25:52.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:52.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:52.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:25:52.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:25:52.01$vc4f8/valo=6,772.99 2006.245.08:25:52.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.08:25:52.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.08:25:52.01#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:52.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:52.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:52.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:52.01#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:25:52.01#ibcon#first serial, iclass 29, count 0 2006.245.08:25:52.01#ibcon#enter sib2, iclass 29, count 0 2006.245.08:25:52.01#ibcon#flushed, iclass 29, count 0 2006.245.08:25:52.01#ibcon#about to write, iclass 29, count 0 2006.245.08:25:52.01#ibcon#wrote, iclass 29, count 0 2006.245.08:25:52.01#ibcon#about to read 3, iclass 29, count 0 2006.245.08:25:52.03#ibcon#read 3, iclass 29, count 0 2006.245.08:25:52.03#ibcon#about to read 4, iclass 29, count 0 2006.245.08:25:52.03#ibcon#read 4, iclass 29, count 0 2006.245.08:25:52.03#ibcon#about to read 5, iclass 29, count 0 2006.245.08:25:52.03#ibcon#read 5, iclass 29, count 0 2006.245.08:25:52.03#ibcon#about to read 6, iclass 29, count 0 2006.245.08:25:52.03#ibcon#read 6, iclass 29, count 0 2006.245.08:25:52.03#ibcon#end of sib2, iclass 29, count 0 2006.245.08:25:52.03#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:25:52.03#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:25:52.03#ibcon#[26=FRQ=06,772.99\r\n] 2006.245.08:25:52.03#ibcon#*before write, iclass 29, count 0 2006.245.08:25:52.03#ibcon#enter sib2, iclass 29, count 0 2006.245.08:25:52.03#ibcon#flushed, iclass 29, count 0 2006.245.08:25:52.03#ibcon#about to write, iclass 29, count 0 2006.245.08:25:52.03#ibcon#wrote, iclass 29, count 0 2006.245.08:25:52.03#ibcon#about to read 3, iclass 29, count 0 2006.245.08:25:52.08#ibcon#read 3, iclass 29, count 0 2006.245.08:25:52.08#ibcon#about to read 4, iclass 29, count 0 2006.245.08:25:52.08#ibcon#read 4, iclass 29, count 0 2006.245.08:25:52.08#ibcon#about to read 5, iclass 29, count 0 2006.245.08:25:52.08#ibcon#read 5, iclass 29, count 0 2006.245.08:25:52.08#ibcon#about to read 6, iclass 29, count 0 2006.245.08:25:52.08#ibcon#read 6, iclass 29, count 0 2006.245.08:25:52.08#ibcon#end of sib2, iclass 29, count 0 2006.245.08:25:52.08#ibcon#*after write, iclass 29, count 0 2006.245.08:25:52.08#ibcon#*before return 0, iclass 29, count 0 2006.245.08:25:52.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:52.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:52.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:25:52.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:25:52.08$vc4f8/va=6,7 2006.245.08:25:52.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.08:25:52.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.08:25:52.08#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:52.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:52.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:52.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:52.13#ibcon#enter wrdev, iclass 31, count 2 2006.245.08:25:52.13#ibcon#first serial, iclass 31, count 2 2006.245.08:25:52.13#ibcon#enter sib2, iclass 31, count 2 2006.245.08:25:52.13#ibcon#flushed, iclass 31, count 2 2006.245.08:25:52.13#ibcon#about to write, iclass 31, count 2 2006.245.08:25:52.13#ibcon#wrote, iclass 31, count 2 2006.245.08:25:52.13#ibcon#about to read 3, iclass 31, count 2 2006.245.08:25:52.15#ibcon#read 3, iclass 31, count 2 2006.245.08:25:52.15#ibcon#about to read 4, iclass 31, count 2 2006.245.08:25:52.15#ibcon#read 4, iclass 31, count 2 2006.245.08:25:52.15#ibcon#about to read 5, iclass 31, count 2 2006.245.08:25:52.15#ibcon#read 5, iclass 31, count 2 2006.245.08:25:52.15#ibcon#about to read 6, iclass 31, count 2 2006.245.08:25:52.15#ibcon#read 6, iclass 31, count 2 2006.245.08:25:52.15#ibcon#end of sib2, iclass 31, count 2 2006.245.08:25:52.15#ibcon#*mode == 0, iclass 31, count 2 2006.245.08:25:52.15#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.08:25:52.15#ibcon#[25=AT06-07\r\n] 2006.245.08:25:52.15#ibcon#*before write, iclass 31, count 2 2006.245.08:25:52.15#ibcon#enter sib2, iclass 31, count 2 2006.245.08:25:52.15#ibcon#flushed, iclass 31, count 2 2006.245.08:25:52.15#ibcon#about to write, iclass 31, count 2 2006.245.08:25:52.15#ibcon#wrote, iclass 31, count 2 2006.245.08:25:52.15#ibcon#about to read 3, iclass 31, count 2 2006.245.08:25:52.18#ibcon#read 3, iclass 31, count 2 2006.245.08:25:52.18#ibcon#about to read 4, iclass 31, count 2 2006.245.08:25:52.18#ibcon#read 4, iclass 31, count 2 2006.245.08:25:52.18#ibcon#about to read 5, iclass 31, count 2 2006.245.08:25:52.18#ibcon#read 5, iclass 31, count 2 2006.245.08:25:52.18#ibcon#about to read 6, iclass 31, count 2 2006.245.08:25:52.18#ibcon#read 6, iclass 31, count 2 2006.245.08:25:52.18#ibcon#end of sib2, iclass 31, count 2 2006.245.08:25:52.18#ibcon#*after write, iclass 31, count 2 2006.245.08:25:52.18#ibcon#*before return 0, iclass 31, count 2 2006.245.08:25:52.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:52.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:52.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.08:25:52.18#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:52.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:52.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:52.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:52.30#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:25:52.30#ibcon#first serial, iclass 31, count 0 2006.245.08:25:52.30#ibcon#enter sib2, iclass 31, count 0 2006.245.08:25:52.30#ibcon#flushed, iclass 31, count 0 2006.245.08:25:52.30#ibcon#about to write, iclass 31, count 0 2006.245.08:25:52.30#ibcon#wrote, iclass 31, count 0 2006.245.08:25:52.30#ibcon#about to read 3, iclass 31, count 0 2006.245.08:25:52.32#ibcon#read 3, iclass 31, count 0 2006.245.08:25:52.32#ibcon#about to read 4, iclass 31, count 0 2006.245.08:25:52.32#ibcon#read 4, iclass 31, count 0 2006.245.08:25:52.32#ibcon#about to read 5, iclass 31, count 0 2006.245.08:25:52.32#ibcon#read 5, iclass 31, count 0 2006.245.08:25:52.32#ibcon#about to read 6, iclass 31, count 0 2006.245.08:25:52.32#ibcon#read 6, iclass 31, count 0 2006.245.08:25:52.32#ibcon#end of sib2, iclass 31, count 0 2006.245.08:25:52.32#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:25:52.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:25:52.32#ibcon#[25=USB\r\n] 2006.245.08:25:52.32#ibcon#*before write, iclass 31, count 0 2006.245.08:25:52.32#ibcon#enter sib2, iclass 31, count 0 2006.245.08:25:52.32#ibcon#flushed, iclass 31, count 0 2006.245.08:25:52.32#ibcon#about to write, iclass 31, count 0 2006.245.08:25:52.32#ibcon#wrote, iclass 31, count 0 2006.245.08:25:52.32#ibcon#about to read 3, iclass 31, count 0 2006.245.08:25:52.35#ibcon#read 3, iclass 31, count 0 2006.245.08:25:52.35#ibcon#about to read 4, iclass 31, count 0 2006.245.08:25:52.35#ibcon#read 4, iclass 31, count 0 2006.245.08:25:52.35#ibcon#about to read 5, iclass 31, count 0 2006.245.08:25:52.35#ibcon#read 5, iclass 31, count 0 2006.245.08:25:52.35#ibcon#about to read 6, iclass 31, count 0 2006.245.08:25:52.35#ibcon#read 6, iclass 31, count 0 2006.245.08:25:52.35#ibcon#end of sib2, iclass 31, count 0 2006.245.08:25:52.35#ibcon#*after write, iclass 31, count 0 2006.245.08:25:52.35#ibcon#*before return 0, iclass 31, count 0 2006.245.08:25:52.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:52.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:52.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:25:52.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:25:52.35$vc4f8/valo=7,832.99 2006.245.08:25:52.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:25:52.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:25:52.35#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:52.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:52.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:52.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:52.35#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:25:52.35#ibcon#first serial, iclass 33, count 0 2006.245.08:25:52.35#ibcon#enter sib2, iclass 33, count 0 2006.245.08:25:52.35#ibcon#flushed, iclass 33, count 0 2006.245.08:25:52.35#ibcon#about to write, iclass 33, count 0 2006.245.08:25:52.35#ibcon#wrote, iclass 33, count 0 2006.245.08:25:52.35#ibcon#about to read 3, iclass 33, count 0 2006.245.08:25:52.37#ibcon#read 3, iclass 33, count 0 2006.245.08:25:52.37#ibcon#about to read 4, iclass 33, count 0 2006.245.08:25:52.37#ibcon#read 4, iclass 33, count 0 2006.245.08:25:52.37#ibcon#about to read 5, iclass 33, count 0 2006.245.08:25:52.37#ibcon#read 5, iclass 33, count 0 2006.245.08:25:52.37#ibcon#about to read 6, iclass 33, count 0 2006.245.08:25:52.37#ibcon#read 6, iclass 33, count 0 2006.245.08:25:52.37#ibcon#end of sib2, iclass 33, count 0 2006.245.08:25:52.37#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:25:52.37#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:25:52.37#ibcon#[26=FRQ=07,832.99\r\n] 2006.245.08:25:52.37#ibcon#*before write, iclass 33, count 0 2006.245.08:25:52.37#ibcon#enter sib2, iclass 33, count 0 2006.245.08:25:52.37#ibcon#flushed, iclass 33, count 0 2006.245.08:25:52.37#ibcon#about to write, iclass 33, count 0 2006.245.08:25:52.37#ibcon#wrote, iclass 33, count 0 2006.245.08:25:52.37#ibcon#about to read 3, iclass 33, count 0 2006.245.08:25:52.41#ibcon#read 3, iclass 33, count 0 2006.245.08:25:52.41#ibcon#about to read 4, iclass 33, count 0 2006.245.08:25:52.41#ibcon#read 4, iclass 33, count 0 2006.245.08:25:52.41#ibcon#about to read 5, iclass 33, count 0 2006.245.08:25:52.41#ibcon#read 5, iclass 33, count 0 2006.245.08:25:52.41#ibcon#about to read 6, iclass 33, count 0 2006.245.08:25:52.41#ibcon#read 6, iclass 33, count 0 2006.245.08:25:52.41#ibcon#end of sib2, iclass 33, count 0 2006.245.08:25:52.41#ibcon#*after write, iclass 33, count 0 2006.245.08:25:52.41#ibcon#*before return 0, iclass 33, count 0 2006.245.08:25:52.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:52.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:52.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:25:52.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:25:52.41$vc4f8/va=7,7 2006.245.08:25:52.41#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.245.08:25:52.41#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.245.08:25:52.41#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:52.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:25:52.43#abcon#<5=/05 3.3 5.3 26.62 761004.5\r\n> 2006.245.08:25:52.45#abcon#{5=INTERFACE CLEAR} 2006.245.08:25:52.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:25:52.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:25:52.47#ibcon#enter wrdev, iclass 36, count 2 2006.245.08:25:52.47#ibcon#first serial, iclass 36, count 2 2006.245.08:25:52.47#ibcon#enter sib2, iclass 36, count 2 2006.245.08:25:52.47#ibcon#flushed, iclass 36, count 2 2006.245.08:25:52.47#ibcon#about to write, iclass 36, count 2 2006.245.08:25:52.47#ibcon#wrote, iclass 36, count 2 2006.245.08:25:52.47#ibcon#about to read 3, iclass 36, count 2 2006.245.08:25:52.49#ibcon#read 3, iclass 36, count 2 2006.245.08:25:52.49#ibcon#about to read 4, iclass 36, count 2 2006.245.08:25:52.49#ibcon#read 4, iclass 36, count 2 2006.245.08:25:52.49#ibcon#about to read 5, iclass 36, count 2 2006.245.08:25:52.49#ibcon#read 5, iclass 36, count 2 2006.245.08:25:52.49#ibcon#about to read 6, iclass 36, count 2 2006.245.08:25:52.49#ibcon#read 6, iclass 36, count 2 2006.245.08:25:52.49#ibcon#end of sib2, iclass 36, count 2 2006.245.08:25:52.49#ibcon#*mode == 0, iclass 36, count 2 2006.245.08:25:52.49#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.245.08:25:52.49#ibcon#[25=AT07-07\r\n] 2006.245.08:25:52.49#ibcon#*before write, iclass 36, count 2 2006.245.08:25:52.49#ibcon#enter sib2, iclass 36, count 2 2006.245.08:25:52.49#ibcon#flushed, iclass 36, count 2 2006.245.08:25:52.49#ibcon#about to write, iclass 36, count 2 2006.245.08:25:52.49#ibcon#wrote, iclass 36, count 2 2006.245.08:25:52.49#ibcon#about to read 3, iclass 36, count 2 2006.245.08:25:52.51#abcon#[5=S1D000X0/0*\r\n] 2006.245.08:25:52.52#ibcon#read 3, iclass 36, count 2 2006.245.08:25:52.52#ibcon#about to read 4, iclass 36, count 2 2006.245.08:25:52.52#ibcon#read 4, iclass 36, count 2 2006.245.08:25:52.52#ibcon#about to read 5, iclass 36, count 2 2006.245.08:25:52.52#ibcon#read 5, iclass 36, count 2 2006.245.08:25:52.52#ibcon#about to read 6, iclass 36, count 2 2006.245.08:25:52.52#ibcon#read 6, iclass 36, count 2 2006.245.08:25:52.52#ibcon#end of sib2, iclass 36, count 2 2006.245.08:25:52.52#ibcon#*after write, iclass 36, count 2 2006.245.08:25:52.52#ibcon#*before return 0, iclass 36, count 2 2006.245.08:25:52.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:25:52.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.245.08:25:52.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.245.08:25:52.52#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:52.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:25:52.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:25:52.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:25:52.64#ibcon#enter wrdev, iclass 36, count 0 2006.245.08:25:52.64#ibcon#first serial, iclass 36, count 0 2006.245.08:25:52.64#ibcon#enter sib2, iclass 36, count 0 2006.245.08:25:52.64#ibcon#flushed, iclass 36, count 0 2006.245.08:25:52.64#ibcon#about to write, iclass 36, count 0 2006.245.08:25:52.64#ibcon#wrote, iclass 36, count 0 2006.245.08:25:52.64#ibcon#about to read 3, iclass 36, count 0 2006.245.08:25:52.66#ibcon#read 3, iclass 36, count 0 2006.245.08:25:52.66#ibcon#about to read 4, iclass 36, count 0 2006.245.08:25:52.66#ibcon#read 4, iclass 36, count 0 2006.245.08:25:52.66#ibcon#about to read 5, iclass 36, count 0 2006.245.08:25:52.66#ibcon#read 5, iclass 36, count 0 2006.245.08:25:52.66#ibcon#about to read 6, iclass 36, count 0 2006.245.08:25:52.66#ibcon#read 6, iclass 36, count 0 2006.245.08:25:52.66#ibcon#end of sib2, iclass 36, count 0 2006.245.08:25:52.66#ibcon#*mode == 0, iclass 36, count 0 2006.245.08:25:52.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.245.08:25:52.66#ibcon#[25=USB\r\n] 2006.245.08:25:52.66#ibcon#*before write, iclass 36, count 0 2006.245.08:25:52.66#ibcon#enter sib2, iclass 36, count 0 2006.245.08:25:52.66#ibcon#flushed, iclass 36, count 0 2006.245.08:25:52.66#ibcon#about to write, iclass 36, count 0 2006.245.08:25:52.66#ibcon#wrote, iclass 36, count 0 2006.245.08:25:52.66#ibcon#about to read 3, iclass 36, count 0 2006.245.08:25:52.69#ibcon#read 3, iclass 36, count 0 2006.245.08:25:52.69#ibcon#about to read 4, iclass 36, count 0 2006.245.08:25:52.69#ibcon#read 4, iclass 36, count 0 2006.245.08:25:52.69#ibcon#about to read 5, iclass 36, count 0 2006.245.08:25:52.69#ibcon#read 5, iclass 36, count 0 2006.245.08:25:52.69#ibcon#about to read 6, iclass 36, count 0 2006.245.08:25:52.69#ibcon#read 6, iclass 36, count 0 2006.245.08:25:52.69#ibcon#end of sib2, iclass 36, count 0 2006.245.08:25:52.69#ibcon#*after write, iclass 36, count 0 2006.245.08:25:52.69#ibcon#*before return 0, iclass 36, count 0 2006.245.08:25:52.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:25:52.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.245.08:25:52.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.245.08:25:52.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.245.08:25:52.69$vc4f8/valo=8,852.99 2006.245.08:25:52.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.245.08:25:52.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.245.08:25:52.69#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:52.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:25:52.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:25:52.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:25:52.69#ibcon#enter wrdev, iclass 3, count 0 2006.245.08:25:52.69#ibcon#first serial, iclass 3, count 0 2006.245.08:25:52.69#ibcon#enter sib2, iclass 3, count 0 2006.245.08:25:52.69#ibcon#flushed, iclass 3, count 0 2006.245.08:25:52.69#ibcon#about to write, iclass 3, count 0 2006.245.08:25:52.69#ibcon#wrote, iclass 3, count 0 2006.245.08:25:52.69#ibcon#about to read 3, iclass 3, count 0 2006.245.08:25:52.71#ibcon#read 3, iclass 3, count 0 2006.245.08:25:52.71#ibcon#about to read 4, iclass 3, count 0 2006.245.08:25:52.71#ibcon#read 4, iclass 3, count 0 2006.245.08:25:52.71#ibcon#about to read 5, iclass 3, count 0 2006.245.08:25:52.71#ibcon#read 5, iclass 3, count 0 2006.245.08:25:52.71#ibcon#about to read 6, iclass 3, count 0 2006.245.08:25:52.71#ibcon#read 6, iclass 3, count 0 2006.245.08:25:52.71#ibcon#end of sib2, iclass 3, count 0 2006.245.08:25:52.71#ibcon#*mode == 0, iclass 3, count 0 2006.245.08:25:52.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.245.08:25:52.71#ibcon#[26=FRQ=08,852.99\r\n] 2006.245.08:25:52.71#ibcon#*before write, iclass 3, count 0 2006.245.08:25:52.71#ibcon#enter sib2, iclass 3, count 0 2006.245.08:25:52.71#ibcon#flushed, iclass 3, count 0 2006.245.08:25:52.71#ibcon#about to write, iclass 3, count 0 2006.245.08:25:52.71#ibcon#wrote, iclass 3, count 0 2006.245.08:25:52.71#ibcon#about to read 3, iclass 3, count 0 2006.245.08:25:52.75#ibcon#read 3, iclass 3, count 0 2006.245.08:25:52.75#ibcon#about to read 4, iclass 3, count 0 2006.245.08:25:52.75#ibcon#read 4, iclass 3, count 0 2006.245.08:25:52.75#ibcon#about to read 5, iclass 3, count 0 2006.245.08:25:52.75#ibcon#read 5, iclass 3, count 0 2006.245.08:25:52.75#ibcon#about to read 6, iclass 3, count 0 2006.245.08:25:52.75#ibcon#read 6, iclass 3, count 0 2006.245.08:25:52.75#ibcon#end of sib2, iclass 3, count 0 2006.245.08:25:52.75#ibcon#*after write, iclass 3, count 0 2006.245.08:25:52.75#ibcon#*before return 0, iclass 3, count 0 2006.245.08:25:52.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:25:52.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.245.08:25:52.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.245.08:25:52.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.245.08:25:52.75$vc4f8/va=8,8 2006.245.08:25:52.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.245.08:25:52.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.245.08:25:52.75#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:52.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:25:52.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:25:52.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:25:52.81#ibcon#enter wrdev, iclass 5, count 2 2006.245.08:25:52.81#ibcon#first serial, iclass 5, count 2 2006.245.08:25:52.81#ibcon#enter sib2, iclass 5, count 2 2006.245.08:25:52.81#ibcon#flushed, iclass 5, count 2 2006.245.08:25:52.81#ibcon#about to write, iclass 5, count 2 2006.245.08:25:52.81#ibcon#wrote, iclass 5, count 2 2006.245.08:25:52.81#ibcon#about to read 3, iclass 5, count 2 2006.245.08:25:52.83#ibcon#read 3, iclass 5, count 2 2006.245.08:25:52.83#ibcon#about to read 4, iclass 5, count 2 2006.245.08:25:52.83#ibcon#read 4, iclass 5, count 2 2006.245.08:25:52.83#ibcon#about to read 5, iclass 5, count 2 2006.245.08:25:52.83#ibcon#read 5, iclass 5, count 2 2006.245.08:25:52.83#ibcon#about to read 6, iclass 5, count 2 2006.245.08:25:52.83#ibcon#read 6, iclass 5, count 2 2006.245.08:25:52.83#ibcon#end of sib2, iclass 5, count 2 2006.245.08:25:52.83#ibcon#*mode == 0, iclass 5, count 2 2006.245.08:25:52.83#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.245.08:25:52.83#ibcon#[25=AT08-08\r\n] 2006.245.08:25:52.83#ibcon#*before write, iclass 5, count 2 2006.245.08:25:52.83#ibcon#enter sib2, iclass 5, count 2 2006.245.08:25:52.83#ibcon#flushed, iclass 5, count 2 2006.245.08:25:52.83#ibcon#about to write, iclass 5, count 2 2006.245.08:25:52.83#ibcon#wrote, iclass 5, count 2 2006.245.08:25:52.83#ibcon#about to read 3, iclass 5, count 2 2006.245.08:25:52.86#ibcon#read 3, iclass 5, count 2 2006.245.08:25:52.86#ibcon#about to read 4, iclass 5, count 2 2006.245.08:25:52.86#ibcon#read 4, iclass 5, count 2 2006.245.08:25:52.86#ibcon#about to read 5, iclass 5, count 2 2006.245.08:25:52.86#ibcon#read 5, iclass 5, count 2 2006.245.08:25:52.86#ibcon#about to read 6, iclass 5, count 2 2006.245.08:25:52.86#ibcon#read 6, iclass 5, count 2 2006.245.08:25:52.86#ibcon#end of sib2, iclass 5, count 2 2006.245.08:25:52.86#ibcon#*after write, iclass 5, count 2 2006.245.08:25:52.86#ibcon#*before return 0, iclass 5, count 2 2006.245.08:25:52.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:25:52.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.245.08:25:52.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.245.08:25:52.86#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:52.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:25:52.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:25:52.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:25:52.98#ibcon#enter wrdev, iclass 5, count 0 2006.245.08:25:52.98#ibcon#first serial, iclass 5, count 0 2006.245.08:25:52.98#ibcon#enter sib2, iclass 5, count 0 2006.245.08:25:52.98#ibcon#flushed, iclass 5, count 0 2006.245.08:25:52.98#ibcon#about to write, iclass 5, count 0 2006.245.08:25:52.98#ibcon#wrote, iclass 5, count 0 2006.245.08:25:52.98#ibcon#about to read 3, iclass 5, count 0 2006.245.08:25:53.00#ibcon#read 3, iclass 5, count 0 2006.245.08:25:53.00#ibcon#about to read 4, iclass 5, count 0 2006.245.08:25:53.00#ibcon#read 4, iclass 5, count 0 2006.245.08:25:53.00#ibcon#about to read 5, iclass 5, count 0 2006.245.08:25:53.00#ibcon#read 5, iclass 5, count 0 2006.245.08:25:53.00#ibcon#about to read 6, iclass 5, count 0 2006.245.08:25:53.00#ibcon#read 6, iclass 5, count 0 2006.245.08:25:53.00#ibcon#end of sib2, iclass 5, count 0 2006.245.08:25:53.00#ibcon#*mode == 0, iclass 5, count 0 2006.245.08:25:53.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.245.08:25:53.00#ibcon#[25=USB\r\n] 2006.245.08:25:53.00#ibcon#*before write, iclass 5, count 0 2006.245.08:25:53.00#ibcon#enter sib2, iclass 5, count 0 2006.245.08:25:53.00#ibcon#flushed, iclass 5, count 0 2006.245.08:25:53.00#ibcon#about to write, iclass 5, count 0 2006.245.08:25:53.00#ibcon#wrote, iclass 5, count 0 2006.245.08:25:53.00#ibcon#about to read 3, iclass 5, count 0 2006.245.08:25:53.03#ibcon#read 3, iclass 5, count 0 2006.245.08:25:53.03#ibcon#about to read 4, iclass 5, count 0 2006.245.08:25:53.03#ibcon#read 4, iclass 5, count 0 2006.245.08:25:53.03#ibcon#about to read 5, iclass 5, count 0 2006.245.08:25:53.03#ibcon#read 5, iclass 5, count 0 2006.245.08:25:53.03#ibcon#about to read 6, iclass 5, count 0 2006.245.08:25:53.03#ibcon#read 6, iclass 5, count 0 2006.245.08:25:53.03#ibcon#end of sib2, iclass 5, count 0 2006.245.08:25:53.03#ibcon#*after write, iclass 5, count 0 2006.245.08:25:53.03#ibcon#*before return 0, iclass 5, count 0 2006.245.08:25:53.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:25:53.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.245.08:25:53.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.245.08:25:53.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.245.08:25:53.03$vc4f8/vblo=1,632.99 2006.245.08:25:53.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.245.08:25:53.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.245.08:25:53.03#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:53.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:53.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:53.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:53.03#ibcon#enter wrdev, iclass 7, count 0 2006.245.08:25:53.03#ibcon#first serial, iclass 7, count 0 2006.245.08:25:53.03#ibcon#enter sib2, iclass 7, count 0 2006.245.08:25:53.03#ibcon#flushed, iclass 7, count 0 2006.245.08:25:53.03#ibcon#about to write, iclass 7, count 0 2006.245.08:25:53.03#ibcon#wrote, iclass 7, count 0 2006.245.08:25:53.03#ibcon#about to read 3, iclass 7, count 0 2006.245.08:25:53.05#ibcon#read 3, iclass 7, count 0 2006.245.08:25:53.05#ibcon#about to read 4, iclass 7, count 0 2006.245.08:25:53.05#ibcon#read 4, iclass 7, count 0 2006.245.08:25:53.05#ibcon#about to read 5, iclass 7, count 0 2006.245.08:25:53.05#ibcon#read 5, iclass 7, count 0 2006.245.08:25:53.05#ibcon#about to read 6, iclass 7, count 0 2006.245.08:25:53.05#ibcon#read 6, iclass 7, count 0 2006.245.08:25:53.05#ibcon#end of sib2, iclass 7, count 0 2006.245.08:25:53.05#ibcon#*mode == 0, iclass 7, count 0 2006.245.08:25:53.05#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.245.08:25:53.05#ibcon#[28=FRQ=01,632.99\r\n] 2006.245.08:25:53.05#ibcon#*before write, iclass 7, count 0 2006.245.08:25:53.05#ibcon#enter sib2, iclass 7, count 0 2006.245.08:25:53.05#ibcon#flushed, iclass 7, count 0 2006.245.08:25:53.05#ibcon#about to write, iclass 7, count 0 2006.245.08:25:53.05#ibcon#wrote, iclass 7, count 0 2006.245.08:25:53.05#ibcon#about to read 3, iclass 7, count 0 2006.245.08:25:53.09#ibcon#read 3, iclass 7, count 0 2006.245.08:25:53.09#ibcon#about to read 4, iclass 7, count 0 2006.245.08:25:53.09#ibcon#read 4, iclass 7, count 0 2006.245.08:25:53.09#ibcon#about to read 5, iclass 7, count 0 2006.245.08:25:53.09#ibcon#read 5, iclass 7, count 0 2006.245.08:25:53.09#ibcon#about to read 6, iclass 7, count 0 2006.245.08:25:53.09#ibcon#read 6, iclass 7, count 0 2006.245.08:25:53.09#ibcon#end of sib2, iclass 7, count 0 2006.245.08:25:53.09#ibcon#*after write, iclass 7, count 0 2006.245.08:25:53.09#ibcon#*before return 0, iclass 7, count 0 2006.245.08:25:53.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:53.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.245.08:25:53.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.245.08:25:53.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.245.08:25:53.09$vc4f8/vb=1,4 2006.245.08:25:53.09#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.245.08:25:53.09#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.245.08:25:53.09#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:53.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:53.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:53.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:53.09#ibcon#enter wrdev, iclass 11, count 2 2006.245.08:25:53.09#ibcon#first serial, iclass 11, count 2 2006.245.08:25:53.09#ibcon#enter sib2, iclass 11, count 2 2006.245.08:25:53.09#ibcon#flushed, iclass 11, count 2 2006.245.08:25:53.09#ibcon#about to write, iclass 11, count 2 2006.245.08:25:53.09#ibcon#wrote, iclass 11, count 2 2006.245.08:25:53.09#ibcon#about to read 3, iclass 11, count 2 2006.245.08:25:53.11#ibcon#read 3, iclass 11, count 2 2006.245.08:25:53.11#ibcon#about to read 4, iclass 11, count 2 2006.245.08:25:53.11#ibcon#read 4, iclass 11, count 2 2006.245.08:25:53.11#ibcon#about to read 5, iclass 11, count 2 2006.245.08:25:53.11#ibcon#read 5, iclass 11, count 2 2006.245.08:25:53.11#ibcon#about to read 6, iclass 11, count 2 2006.245.08:25:53.11#ibcon#read 6, iclass 11, count 2 2006.245.08:25:53.11#ibcon#end of sib2, iclass 11, count 2 2006.245.08:25:53.11#ibcon#*mode == 0, iclass 11, count 2 2006.245.08:25:53.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.245.08:25:53.11#ibcon#[27=AT01-04\r\n] 2006.245.08:25:53.11#ibcon#*before write, iclass 11, count 2 2006.245.08:25:53.11#ibcon#enter sib2, iclass 11, count 2 2006.245.08:25:53.11#ibcon#flushed, iclass 11, count 2 2006.245.08:25:53.11#ibcon#about to write, iclass 11, count 2 2006.245.08:25:53.11#ibcon#wrote, iclass 11, count 2 2006.245.08:25:53.11#ibcon#about to read 3, iclass 11, count 2 2006.245.08:25:53.14#ibcon#read 3, iclass 11, count 2 2006.245.08:25:53.14#ibcon#about to read 4, iclass 11, count 2 2006.245.08:25:53.14#ibcon#read 4, iclass 11, count 2 2006.245.08:25:53.14#ibcon#about to read 5, iclass 11, count 2 2006.245.08:25:53.14#ibcon#read 5, iclass 11, count 2 2006.245.08:25:53.14#ibcon#about to read 6, iclass 11, count 2 2006.245.08:25:53.14#ibcon#read 6, iclass 11, count 2 2006.245.08:25:53.14#ibcon#end of sib2, iclass 11, count 2 2006.245.08:25:53.14#ibcon#*after write, iclass 11, count 2 2006.245.08:25:53.14#ibcon#*before return 0, iclass 11, count 2 2006.245.08:25:53.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:53.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.245.08:25:53.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.245.08:25:53.14#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:53.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:53.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:53.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:53.26#ibcon#enter wrdev, iclass 11, count 0 2006.245.08:25:53.26#ibcon#first serial, iclass 11, count 0 2006.245.08:25:53.26#ibcon#enter sib2, iclass 11, count 0 2006.245.08:25:53.26#ibcon#flushed, iclass 11, count 0 2006.245.08:25:53.26#ibcon#about to write, iclass 11, count 0 2006.245.08:25:53.26#ibcon#wrote, iclass 11, count 0 2006.245.08:25:53.26#ibcon#about to read 3, iclass 11, count 0 2006.245.08:25:53.28#ibcon#read 3, iclass 11, count 0 2006.245.08:25:53.28#ibcon#about to read 4, iclass 11, count 0 2006.245.08:25:53.28#ibcon#read 4, iclass 11, count 0 2006.245.08:25:53.28#ibcon#about to read 5, iclass 11, count 0 2006.245.08:25:53.28#ibcon#read 5, iclass 11, count 0 2006.245.08:25:53.28#ibcon#about to read 6, iclass 11, count 0 2006.245.08:25:53.28#ibcon#read 6, iclass 11, count 0 2006.245.08:25:53.28#ibcon#end of sib2, iclass 11, count 0 2006.245.08:25:53.28#ibcon#*mode == 0, iclass 11, count 0 2006.245.08:25:53.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.245.08:25:53.28#ibcon#[27=USB\r\n] 2006.245.08:25:53.28#ibcon#*before write, iclass 11, count 0 2006.245.08:25:53.28#ibcon#enter sib2, iclass 11, count 0 2006.245.08:25:53.28#ibcon#flushed, iclass 11, count 0 2006.245.08:25:53.28#ibcon#about to write, iclass 11, count 0 2006.245.08:25:53.28#ibcon#wrote, iclass 11, count 0 2006.245.08:25:53.28#ibcon#about to read 3, iclass 11, count 0 2006.245.08:25:53.31#ibcon#read 3, iclass 11, count 0 2006.245.08:25:53.31#ibcon#about to read 4, iclass 11, count 0 2006.245.08:25:53.31#ibcon#read 4, iclass 11, count 0 2006.245.08:25:53.31#ibcon#about to read 5, iclass 11, count 0 2006.245.08:25:53.31#ibcon#read 5, iclass 11, count 0 2006.245.08:25:53.31#ibcon#about to read 6, iclass 11, count 0 2006.245.08:25:53.31#ibcon#read 6, iclass 11, count 0 2006.245.08:25:53.31#ibcon#end of sib2, iclass 11, count 0 2006.245.08:25:53.31#ibcon#*after write, iclass 11, count 0 2006.245.08:25:53.31#ibcon#*before return 0, iclass 11, count 0 2006.245.08:25:53.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:53.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.245.08:25:53.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.245.08:25:53.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.245.08:25:53.31$vc4f8/vblo=2,640.99 2006.245.08:25:53.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.245.08:25:53.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.245.08:25:53.31#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:53.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:53.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:53.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:53.31#ibcon#enter wrdev, iclass 13, count 0 2006.245.08:25:53.31#ibcon#first serial, iclass 13, count 0 2006.245.08:25:53.31#ibcon#enter sib2, iclass 13, count 0 2006.245.08:25:53.31#ibcon#flushed, iclass 13, count 0 2006.245.08:25:53.31#ibcon#about to write, iclass 13, count 0 2006.245.08:25:53.31#ibcon#wrote, iclass 13, count 0 2006.245.08:25:53.31#ibcon#about to read 3, iclass 13, count 0 2006.245.08:25:53.33#ibcon#read 3, iclass 13, count 0 2006.245.08:25:53.33#ibcon#about to read 4, iclass 13, count 0 2006.245.08:25:53.33#ibcon#read 4, iclass 13, count 0 2006.245.08:25:53.33#ibcon#about to read 5, iclass 13, count 0 2006.245.08:25:53.33#ibcon#read 5, iclass 13, count 0 2006.245.08:25:53.33#ibcon#about to read 6, iclass 13, count 0 2006.245.08:25:53.33#ibcon#read 6, iclass 13, count 0 2006.245.08:25:53.33#ibcon#end of sib2, iclass 13, count 0 2006.245.08:25:53.33#ibcon#*mode == 0, iclass 13, count 0 2006.245.08:25:53.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.245.08:25:53.33#ibcon#[28=FRQ=02,640.99\r\n] 2006.245.08:25:53.33#ibcon#*before write, iclass 13, count 0 2006.245.08:25:53.33#ibcon#enter sib2, iclass 13, count 0 2006.245.08:25:53.33#ibcon#flushed, iclass 13, count 0 2006.245.08:25:53.33#ibcon#about to write, iclass 13, count 0 2006.245.08:25:53.33#ibcon#wrote, iclass 13, count 0 2006.245.08:25:53.33#ibcon#about to read 3, iclass 13, count 0 2006.245.08:25:53.37#ibcon#read 3, iclass 13, count 0 2006.245.08:25:53.37#ibcon#about to read 4, iclass 13, count 0 2006.245.08:25:53.37#ibcon#read 4, iclass 13, count 0 2006.245.08:25:53.37#ibcon#about to read 5, iclass 13, count 0 2006.245.08:25:53.37#ibcon#read 5, iclass 13, count 0 2006.245.08:25:53.37#ibcon#about to read 6, iclass 13, count 0 2006.245.08:25:53.37#ibcon#read 6, iclass 13, count 0 2006.245.08:25:53.37#ibcon#end of sib2, iclass 13, count 0 2006.245.08:25:53.37#ibcon#*after write, iclass 13, count 0 2006.245.08:25:53.37#ibcon#*before return 0, iclass 13, count 0 2006.245.08:25:53.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:53.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.245.08:25:53.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.245.08:25:53.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.245.08:25:53.37$vc4f8/vb=2,4 2006.245.08:25:53.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.245.08:25:53.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.245.08:25:53.37#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:53.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:53.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:53.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:53.43#ibcon#enter wrdev, iclass 15, count 2 2006.245.08:25:53.43#ibcon#first serial, iclass 15, count 2 2006.245.08:25:53.43#ibcon#enter sib2, iclass 15, count 2 2006.245.08:25:53.43#ibcon#flushed, iclass 15, count 2 2006.245.08:25:53.43#ibcon#about to write, iclass 15, count 2 2006.245.08:25:53.43#ibcon#wrote, iclass 15, count 2 2006.245.08:25:53.43#ibcon#about to read 3, iclass 15, count 2 2006.245.08:25:53.45#ibcon#read 3, iclass 15, count 2 2006.245.08:25:53.45#ibcon#about to read 4, iclass 15, count 2 2006.245.08:25:53.45#ibcon#read 4, iclass 15, count 2 2006.245.08:25:53.45#ibcon#about to read 5, iclass 15, count 2 2006.245.08:25:53.45#ibcon#read 5, iclass 15, count 2 2006.245.08:25:53.45#ibcon#about to read 6, iclass 15, count 2 2006.245.08:25:53.45#ibcon#read 6, iclass 15, count 2 2006.245.08:25:53.45#ibcon#end of sib2, iclass 15, count 2 2006.245.08:25:53.45#ibcon#*mode == 0, iclass 15, count 2 2006.245.08:25:53.45#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.245.08:25:53.45#ibcon#[27=AT02-04\r\n] 2006.245.08:25:53.45#ibcon#*before write, iclass 15, count 2 2006.245.08:25:53.45#ibcon#enter sib2, iclass 15, count 2 2006.245.08:25:53.45#ibcon#flushed, iclass 15, count 2 2006.245.08:25:53.45#ibcon#about to write, iclass 15, count 2 2006.245.08:25:53.45#ibcon#wrote, iclass 15, count 2 2006.245.08:25:53.45#ibcon#about to read 3, iclass 15, count 2 2006.245.08:25:53.48#ibcon#read 3, iclass 15, count 2 2006.245.08:25:53.48#ibcon#about to read 4, iclass 15, count 2 2006.245.08:25:53.48#ibcon#read 4, iclass 15, count 2 2006.245.08:25:53.48#ibcon#about to read 5, iclass 15, count 2 2006.245.08:25:53.48#ibcon#read 5, iclass 15, count 2 2006.245.08:25:53.48#ibcon#about to read 6, iclass 15, count 2 2006.245.08:25:53.48#ibcon#read 6, iclass 15, count 2 2006.245.08:25:53.48#ibcon#end of sib2, iclass 15, count 2 2006.245.08:25:53.48#ibcon#*after write, iclass 15, count 2 2006.245.08:25:53.48#ibcon#*before return 0, iclass 15, count 2 2006.245.08:25:53.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:53.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.245.08:25:53.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.245.08:25:53.48#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:53.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:53.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:53.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:53.60#ibcon#enter wrdev, iclass 15, count 0 2006.245.08:25:53.60#ibcon#first serial, iclass 15, count 0 2006.245.08:25:53.60#ibcon#enter sib2, iclass 15, count 0 2006.245.08:25:53.60#ibcon#flushed, iclass 15, count 0 2006.245.08:25:53.60#ibcon#about to write, iclass 15, count 0 2006.245.08:25:53.60#ibcon#wrote, iclass 15, count 0 2006.245.08:25:53.60#ibcon#about to read 3, iclass 15, count 0 2006.245.08:25:53.62#ibcon#read 3, iclass 15, count 0 2006.245.08:25:53.62#ibcon#about to read 4, iclass 15, count 0 2006.245.08:25:53.62#ibcon#read 4, iclass 15, count 0 2006.245.08:25:53.62#ibcon#about to read 5, iclass 15, count 0 2006.245.08:25:53.62#ibcon#read 5, iclass 15, count 0 2006.245.08:25:53.62#ibcon#about to read 6, iclass 15, count 0 2006.245.08:25:53.62#ibcon#read 6, iclass 15, count 0 2006.245.08:25:53.62#ibcon#end of sib2, iclass 15, count 0 2006.245.08:25:53.62#ibcon#*mode == 0, iclass 15, count 0 2006.245.08:25:53.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.245.08:25:53.62#ibcon#[27=USB\r\n] 2006.245.08:25:53.62#ibcon#*before write, iclass 15, count 0 2006.245.08:25:53.62#ibcon#enter sib2, iclass 15, count 0 2006.245.08:25:53.62#ibcon#flushed, iclass 15, count 0 2006.245.08:25:53.62#ibcon#about to write, iclass 15, count 0 2006.245.08:25:53.62#ibcon#wrote, iclass 15, count 0 2006.245.08:25:53.62#ibcon#about to read 3, iclass 15, count 0 2006.245.08:25:53.65#ibcon#read 3, iclass 15, count 0 2006.245.08:25:53.65#ibcon#about to read 4, iclass 15, count 0 2006.245.08:25:53.65#ibcon#read 4, iclass 15, count 0 2006.245.08:25:53.65#ibcon#about to read 5, iclass 15, count 0 2006.245.08:25:53.65#ibcon#read 5, iclass 15, count 0 2006.245.08:25:53.65#ibcon#about to read 6, iclass 15, count 0 2006.245.08:25:53.65#ibcon#read 6, iclass 15, count 0 2006.245.08:25:53.65#ibcon#end of sib2, iclass 15, count 0 2006.245.08:25:53.65#ibcon#*after write, iclass 15, count 0 2006.245.08:25:53.65#ibcon#*before return 0, iclass 15, count 0 2006.245.08:25:53.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:53.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.245.08:25:53.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.245.08:25:53.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.245.08:25:53.65$vc4f8/vblo=3,656.99 2006.245.08:25:53.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.245.08:25:53.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.245.08:25:53.65#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:53.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:53.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:53.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:53.65#ibcon#enter wrdev, iclass 17, count 0 2006.245.08:25:53.65#ibcon#first serial, iclass 17, count 0 2006.245.08:25:53.65#ibcon#enter sib2, iclass 17, count 0 2006.245.08:25:53.65#ibcon#flushed, iclass 17, count 0 2006.245.08:25:53.65#ibcon#about to write, iclass 17, count 0 2006.245.08:25:53.65#ibcon#wrote, iclass 17, count 0 2006.245.08:25:53.65#ibcon#about to read 3, iclass 17, count 0 2006.245.08:25:53.67#ibcon#read 3, iclass 17, count 0 2006.245.08:25:53.67#ibcon#about to read 4, iclass 17, count 0 2006.245.08:25:53.67#ibcon#read 4, iclass 17, count 0 2006.245.08:25:53.67#ibcon#about to read 5, iclass 17, count 0 2006.245.08:25:53.67#ibcon#read 5, iclass 17, count 0 2006.245.08:25:53.67#ibcon#about to read 6, iclass 17, count 0 2006.245.08:25:53.67#ibcon#read 6, iclass 17, count 0 2006.245.08:25:53.67#ibcon#end of sib2, iclass 17, count 0 2006.245.08:25:53.67#ibcon#*mode == 0, iclass 17, count 0 2006.245.08:25:53.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.245.08:25:53.67#ibcon#[28=FRQ=03,656.99\r\n] 2006.245.08:25:53.67#ibcon#*before write, iclass 17, count 0 2006.245.08:25:53.67#ibcon#enter sib2, iclass 17, count 0 2006.245.08:25:53.67#ibcon#flushed, iclass 17, count 0 2006.245.08:25:53.67#ibcon#about to write, iclass 17, count 0 2006.245.08:25:53.67#ibcon#wrote, iclass 17, count 0 2006.245.08:25:53.67#ibcon#about to read 3, iclass 17, count 0 2006.245.08:25:53.71#ibcon#read 3, iclass 17, count 0 2006.245.08:25:53.71#ibcon#about to read 4, iclass 17, count 0 2006.245.08:25:53.71#ibcon#read 4, iclass 17, count 0 2006.245.08:25:53.71#ibcon#about to read 5, iclass 17, count 0 2006.245.08:25:53.71#ibcon#read 5, iclass 17, count 0 2006.245.08:25:53.71#ibcon#about to read 6, iclass 17, count 0 2006.245.08:25:53.71#ibcon#read 6, iclass 17, count 0 2006.245.08:25:53.71#ibcon#end of sib2, iclass 17, count 0 2006.245.08:25:53.71#ibcon#*after write, iclass 17, count 0 2006.245.08:25:53.71#ibcon#*before return 0, iclass 17, count 0 2006.245.08:25:53.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:53.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.245.08:25:53.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.245.08:25:53.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.245.08:25:53.71$vc4f8/vb=3,4 2006.245.08:25:53.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.245.08:25:53.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.245.08:25:53.71#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:53.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:53.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:53.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:53.77#ibcon#enter wrdev, iclass 19, count 2 2006.245.08:25:53.77#ibcon#first serial, iclass 19, count 2 2006.245.08:25:53.77#ibcon#enter sib2, iclass 19, count 2 2006.245.08:25:53.77#ibcon#flushed, iclass 19, count 2 2006.245.08:25:53.77#ibcon#about to write, iclass 19, count 2 2006.245.08:25:53.77#ibcon#wrote, iclass 19, count 2 2006.245.08:25:53.77#ibcon#about to read 3, iclass 19, count 2 2006.245.08:25:53.79#ibcon#read 3, iclass 19, count 2 2006.245.08:25:53.79#ibcon#about to read 4, iclass 19, count 2 2006.245.08:25:53.79#ibcon#read 4, iclass 19, count 2 2006.245.08:25:53.79#ibcon#about to read 5, iclass 19, count 2 2006.245.08:25:53.79#ibcon#read 5, iclass 19, count 2 2006.245.08:25:53.79#ibcon#about to read 6, iclass 19, count 2 2006.245.08:25:53.79#ibcon#read 6, iclass 19, count 2 2006.245.08:25:53.79#ibcon#end of sib2, iclass 19, count 2 2006.245.08:25:53.79#ibcon#*mode == 0, iclass 19, count 2 2006.245.08:25:53.79#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.245.08:25:53.79#ibcon#[27=AT03-04\r\n] 2006.245.08:25:53.79#ibcon#*before write, iclass 19, count 2 2006.245.08:25:53.79#ibcon#enter sib2, iclass 19, count 2 2006.245.08:25:53.79#ibcon#flushed, iclass 19, count 2 2006.245.08:25:53.79#ibcon#about to write, iclass 19, count 2 2006.245.08:25:53.79#ibcon#wrote, iclass 19, count 2 2006.245.08:25:53.79#ibcon#about to read 3, iclass 19, count 2 2006.245.08:25:53.82#ibcon#read 3, iclass 19, count 2 2006.245.08:25:53.82#ibcon#about to read 4, iclass 19, count 2 2006.245.08:25:53.82#ibcon#read 4, iclass 19, count 2 2006.245.08:25:53.82#ibcon#about to read 5, iclass 19, count 2 2006.245.08:25:53.82#ibcon#read 5, iclass 19, count 2 2006.245.08:25:53.82#ibcon#about to read 6, iclass 19, count 2 2006.245.08:25:53.82#ibcon#read 6, iclass 19, count 2 2006.245.08:25:53.82#ibcon#end of sib2, iclass 19, count 2 2006.245.08:25:53.82#ibcon#*after write, iclass 19, count 2 2006.245.08:25:53.82#ibcon#*before return 0, iclass 19, count 2 2006.245.08:25:53.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:53.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.245.08:25:53.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.245.08:25:53.82#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:53.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:53.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:53.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:53.94#ibcon#enter wrdev, iclass 19, count 0 2006.245.08:25:53.94#ibcon#first serial, iclass 19, count 0 2006.245.08:25:53.94#ibcon#enter sib2, iclass 19, count 0 2006.245.08:25:53.94#ibcon#flushed, iclass 19, count 0 2006.245.08:25:53.94#ibcon#about to write, iclass 19, count 0 2006.245.08:25:53.94#ibcon#wrote, iclass 19, count 0 2006.245.08:25:53.94#ibcon#about to read 3, iclass 19, count 0 2006.245.08:25:53.96#ibcon#read 3, iclass 19, count 0 2006.245.08:25:53.96#ibcon#about to read 4, iclass 19, count 0 2006.245.08:25:53.96#ibcon#read 4, iclass 19, count 0 2006.245.08:25:53.96#ibcon#about to read 5, iclass 19, count 0 2006.245.08:25:53.96#ibcon#read 5, iclass 19, count 0 2006.245.08:25:53.96#ibcon#about to read 6, iclass 19, count 0 2006.245.08:25:53.96#ibcon#read 6, iclass 19, count 0 2006.245.08:25:53.96#ibcon#end of sib2, iclass 19, count 0 2006.245.08:25:53.96#ibcon#*mode == 0, iclass 19, count 0 2006.245.08:25:53.96#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.245.08:25:53.96#ibcon#[27=USB\r\n] 2006.245.08:25:53.96#ibcon#*before write, iclass 19, count 0 2006.245.08:25:53.96#ibcon#enter sib2, iclass 19, count 0 2006.245.08:25:53.96#ibcon#flushed, iclass 19, count 0 2006.245.08:25:53.96#ibcon#about to write, iclass 19, count 0 2006.245.08:25:53.96#ibcon#wrote, iclass 19, count 0 2006.245.08:25:53.96#ibcon#about to read 3, iclass 19, count 0 2006.245.08:25:53.99#ibcon#read 3, iclass 19, count 0 2006.245.08:25:53.99#ibcon#about to read 4, iclass 19, count 0 2006.245.08:25:53.99#ibcon#read 4, iclass 19, count 0 2006.245.08:25:53.99#ibcon#about to read 5, iclass 19, count 0 2006.245.08:25:53.99#ibcon#read 5, iclass 19, count 0 2006.245.08:25:53.99#ibcon#about to read 6, iclass 19, count 0 2006.245.08:25:53.99#ibcon#read 6, iclass 19, count 0 2006.245.08:25:53.99#ibcon#end of sib2, iclass 19, count 0 2006.245.08:25:53.99#ibcon#*after write, iclass 19, count 0 2006.245.08:25:53.99#ibcon#*before return 0, iclass 19, count 0 2006.245.08:25:53.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:53.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.245.08:25:53.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.245.08:25:53.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.245.08:25:53.99$vc4f8/vblo=4,712.99 2006.245.08:25:53.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.245.08:25:53.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.245.08:25:53.99#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:53.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:53.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:53.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:53.99#ibcon#enter wrdev, iclass 21, count 0 2006.245.08:25:53.99#ibcon#first serial, iclass 21, count 0 2006.245.08:25:53.99#ibcon#enter sib2, iclass 21, count 0 2006.245.08:25:53.99#ibcon#flushed, iclass 21, count 0 2006.245.08:25:53.99#ibcon#about to write, iclass 21, count 0 2006.245.08:25:53.99#ibcon#wrote, iclass 21, count 0 2006.245.08:25:53.99#ibcon#about to read 3, iclass 21, count 0 2006.245.08:25:54.01#ibcon#read 3, iclass 21, count 0 2006.245.08:25:54.01#ibcon#about to read 4, iclass 21, count 0 2006.245.08:25:54.01#ibcon#read 4, iclass 21, count 0 2006.245.08:25:54.01#ibcon#about to read 5, iclass 21, count 0 2006.245.08:25:54.01#ibcon#read 5, iclass 21, count 0 2006.245.08:25:54.01#ibcon#about to read 6, iclass 21, count 0 2006.245.08:25:54.01#ibcon#read 6, iclass 21, count 0 2006.245.08:25:54.01#ibcon#end of sib2, iclass 21, count 0 2006.245.08:25:54.01#ibcon#*mode == 0, iclass 21, count 0 2006.245.08:25:54.01#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.245.08:25:54.01#ibcon#[28=FRQ=04,712.99\r\n] 2006.245.08:25:54.01#ibcon#*before write, iclass 21, count 0 2006.245.08:25:54.01#ibcon#enter sib2, iclass 21, count 0 2006.245.08:25:54.01#ibcon#flushed, iclass 21, count 0 2006.245.08:25:54.01#ibcon#about to write, iclass 21, count 0 2006.245.08:25:54.01#ibcon#wrote, iclass 21, count 0 2006.245.08:25:54.01#ibcon#about to read 3, iclass 21, count 0 2006.245.08:25:54.05#ibcon#read 3, iclass 21, count 0 2006.245.08:25:54.05#ibcon#about to read 4, iclass 21, count 0 2006.245.08:25:54.05#ibcon#read 4, iclass 21, count 0 2006.245.08:25:54.05#ibcon#about to read 5, iclass 21, count 0 2006.245.08:25:54.05#ibcon#read 5, iclass 21, count 0 2006.245.08:25:54.05#ibcon#about to read 6, iclass 21, count 0 2006.245.08:25:54.05#ibcon#read 6, iclass 21, count 0 2006.245.08:25:54.05#ibcon#end of sib2, iclass 21, count 0 2006.245.08:25:54.05#ibcon#*after write, iclass 21, count 0 2006.245.08:25:54.05#ibcon#*before return 0, iclass 21, count 0 2006.245.08:25:54.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:54.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.245.08:25:54.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.245.08:25:54.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.245.08:25:54.05$vc4f8/vb=4,4 2006.245.08:25:54.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.245.08:25:54.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.245.08:25:54.05#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:54.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:54.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:54.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:54.11#ibcon#enter wrdev, iclass 23, count 2 2006.245.08:25:54.11#ibcon#first serial, iclass 23, count 2 2006.245.08:25:54.11#ibcon#enter sib2, iclass 23, count 2 2006.245.08:25:54.11#ibcon#flushed, iclass 23, count 2 2006.245.08:25:54.11#ibcon#about to write, iclass 23, count 2 2006.245.08:25:54.11#ibcon#wrote, iclass 23, count 2 2006.245.08:25:54.11#ibcon#about to read 3, iclass 23, count 2 2006.245.08:25:54.13#ibcon#read 3, iclass 23, count 2 2006.245.08:25:54.13#ibcon#about to read 4, iclass 23, count 2 2006.245.08:25:54.13#ibcon#read 4, iclass 23, count 2 2006.245.08:25:54.13#ibcon#about to read 5, iclass 23, count 2 2006.245.08:25:54.13#ibcon#read 5, iclass 23, count 2 2006.245.08:25:54.13#ibcon#about to read 6, iclass 23, count 2 2006.245.08:25:54.13#ibcon#read 6, iclass 23, count 2 2006.245.08:25:54.13#ibcon#end of sib2, iclass 23, count 2 2006.245.08:25:54.13#ibcon#*mode == 0, iclass 23, count 2 2006.245.08:25:54.13#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.245.08:25:54.13#ibcon#[27=AT04-04\r\n] 2006.245.08:25:54.13#ibcon#*before write, iclass 23, count 2 2006.245.08:25:54.13#ibcon#enter sib2, iclass 23, count 2 2006.245.08:25:54.13#ibcon#flushed, iclass 23, count 2 2006.245.08:25:54.13#ibcon#about to write, iclass 23, count 2 2006.245.08:25:54.13#ibcon#wrote, iclass 23, count 2 2006.245.08:25:54.13#ibcon#about to read 3, iclass 23, count 2 2006.245.08:25:54.16#ibcon#read 3, iclass 23, count 2 2006.245.08:25:54.16#ibcon#about to read 4, iclass 23, count 2 2006.245.08:25:54.16#ibcon#read 4, iclass 23, count 2 2006.245.08:25:54.16#ibcon#about to read 5, iclass 23, count 2 2006.245.08:25:54.16#ibcon#read 5, iclass 23, count 2 2006.245.08:25:54.16#ibcon#about to read 6, iclass 23, count 2 2006.245.08:25:54.16#ibcon#read 6, iclass 23, count 2 2006.245.08:25:54.16#ibcon#end of sib2, iclass 23, count 2 2006.245.08:25:54.16#ibcon#*after write, iclass 23, count 2 2006.245.08:25:54.16#ibcon#*before return 0, iclass 23, count 2 2006.245.08:25:54.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:54.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.245.08:25:54.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.245.08:25:54.16#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:54.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:54.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:54.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:54.28#ibcon#enter wrdev, iclass 23, count 0 2006.245.08:25:54.28#ibcon#first serial, iclass 23, count 0 2006.245.08:25:54.28#ibcon#enter sib2, iclass 23, count 0 2006.245.08:25:54.28#ibcon#flushed, iclass 23, count 0 2006.245.08:25:54.28#ibcon#about to write, iclass 23, count 0 2006.245.08:25:54.28#ibcon#wrote, iclass 23, count 0 2006.245.08:25:54.28#ibcon#about to read 3, iclass 23, count 0 2006.245.08:25:54.30#ibcon#read 3, iclass 23, count 0 2006.245.08:25:54.30#ibcon#about to read 4, iclass 23, count 0 2006.245.08:25:54.30#ibcon#read 4, iclass 23, count 0 2006.245.08:25:54.30#ibcon#about to read 5, iclass 23, count 0 2006.245.08:25:54.30#ibcon#read 5, iclass 23, count 0 2006.245.08:25:54.30#ibcon#about to read 6, iclass 23, count 0 2006.245.08:25:54.30#ibcon#read 6, iclass 23, count 0 2006.245.08:25:54.30#ibcon#end of sib2, iclass 23, count 0 2006.245.08:25:54.30#ibcon#*mode == 0, iclass 23, count 0 2006.245.08:25:54.30#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.245.08:25:54.30#ibcon#[27=USB\r\n] 2006.245.08:25:54.30#ibcon#*before write, iclass 23, count 0 2006.245.08:25:54.30#ibcon#enter sib2, iclass 23, count 0 2006.245.08:25:54.30#ibcon#flushed, iclass 23, count 0 2006.245.08:25:54.30#ibcon#about to write, iclass 23, count 0 2006.245.08:25:54.30#ibcon#wrote, iclass 23, count 0 2006.245.08:25:54.30#ibcon#about to read 3, iclass 23, count 0 2006.245.08:25:54.33#ibcon#read 3, iclass 23, count 0 2006.245.08:25:54.33#ibcon#about to read 4, iclass 23, count 0 2006.245.08:25:54.33#ibcon#read 4, iclass 23, count 0 2006.245.08:25:54.33#ibcon#about to read 5, iclass 23, count 0 2006.245.08:25:54.33#ibcon#read 5, iclass 23, count 0 2006.245.08:25:54.33#ibcon#about to read 6, iclass 23, count 0 2006.245.08:25:54.33#ibcon#read 6, iclass 23, count 0 2006.245.08:25:54.33#ibcon#end of sib2, iclass 23, count 0 2006.245.08:25:54.33#ibcon#*after write, iclass 23, count 0 2006.245.08:25:54.33#ibcon#*before return 0, iclass 23, count 0 2006.245.08:25:54.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:54.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.245.08:25:54.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.245.08:25:54.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.245.08:25:54.33$vc4f8/vblo=5,744.99 2006.245.08:25:54.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.245.08:25:54.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.245.08:25:54.33#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:54.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:54.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:54.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:54.33#ibcon#enter wrdev, iclass 25, count 0 2006.245.08:25:54.33#ibcon#first serial, iclass 25, count 0 2006.245.08:25:54.33#ibcon#enter sib2, iclass 25, count 0 2006.245.08:25:54.33#ibcon#flushed, iclass 25, count 0 2006.245.08:25:54.33#ibcon#about to write, iclass 25, count 0 2006.245.08:25:54.33#ibcon#wrote, iclass 25, count 0 2006.245.08:25:54.33#ibcon#about to read 3, iclass 25, count 0 2006.245.08:25:54.35#ibcon#read 3, iclass 25, count 0 2006.245.08:25:54.35#ibcon#about to read 4, iclass 25, count 0 2006.245.08:25:54.35#ibcon#read 4, iclass 25, count 0 2006.245.08:25:54.35#ibcon#about to read 5, iclass 25, count 0 2006.245.08:25:54.35#ibcon#read 5, iclass 25, count 0 2006.245.08:25:54.35#ibcon#about to read 6, iclass 25, count 0 2006.245.08:25:54.35#ibcon#read 6, iclass 25, count 0 2006.245.08:25:54.35#ibcon#end of sib2, iclass 25, count 0 2006.245.08:25:54.35#ibcon#*mode == 0, iclass 25, count 0 2006.245.08:25:54.35#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.245.08:25:54.35#ibcon#[28=FRQ=05,744.99\r\n] 2006.245.08:25:54.35#ibcon#*before write, iclass 25, count 0 2006.245.08:25:54.35#ibcon#enter sib2, iclass 25, count 0 2006.245.08:25:54.35#ibcon#flushed, iclass 25, count 0 2006.245.08:25:54.35#ibcon#about to write, iclass 25, count 0 2006.245.08:25:54.35#ibcon#wrote, iclass 25, count 0 2006.245.08:25:54.35#ibcon#about to read 3, iclass 25, count 0 2006.245.08:25:54.39#ibcon#read 3, iclass 25, count 0 2006.245.08:25:54.39#ibcon#about to read 4, iclass 25, count 0 2006.245.08:25:54.39#ibcon#read 4, iclass 25, count 0 2006.245.08:25:54.39#ibcon#about to read 5, iclass 25, count 0 2006.245.08:25:54.39#ibcon#read 5, iclass 25, count 0 2006.245.08:25:54.39#ibcon#about to read 6, iclass 25, count 0 2006.245.08:25:54.39#ibcon#read 6, iclass 25, count 0 2006.245.08:25:54.39#ibcon#end of sib2, iclass 25, count 0 2006.245.08:25:54.39#ibcon#*after write, iclass 25, count 0 2006.245.08:25:54.39#ibcon#*before return 0, iclass 25, count 0 2006.245.08:25:54.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:54.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.245.08:25:54.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.245.08:25:54.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.245.08:25:54.39$vc4f8/vb=5,3 2006.245.08:25:54.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.245.08:25:54.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.245.08:25:54.39#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:54.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:54.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:54.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:54.45#ibcon#enter wrdev, iclass 27, count 2 2006.245.08:25:54.45#ibcon#first serial, iclass 27, count 2 2006.245.08:25:54.45#ibcon#enter sib2, iclass 27, count 2 2006.245.08:25:54.45#ibcon#flushed, iclass 27, count 2 2006.245.08:25:54.45#ibcon#about to write, iclass 27, count 2 2006.245.08:25:54.45#ibcon#wrote, iclass 27, count 2 2006.245.08:25:54.45#ibcon#about to read 3, iclass 27, count 2 2006.245.08:25:54.47#ibcon#read 3, iclass 27, count 2 2006.245.08:25:54.47#ibcon#about to read 4, iclass 27, count 2 2006.245.08:25:54.47#ibcon#read 4, iclass 27, count 2 2006.245.08:25:54.47#ibcon#about to read 5, iclass 27, count 2 2006.245.08:25:54.47#ibcon#read 5, iclass 27, count 2 2006.245.08:25:54.47#ibcon#about to read 6, iclass 27, count 2 2006.245.08:25:54.47#ibcon#read 6, iclass 27, count 2 2006.245.08:25:54.47#ibcon#end of sib2, iclass 27, count 2 2006.245.08:25:54.47#ibcon#*mode == 0, iclass 27, count 2 2006.245.08:25:54.47#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.245.08:25:54.47#ibcon#[27=AT05-03\r\n] 2006.245.08:25:54.47#ibcon#*before write, iclass 27, count 2 2006.245.08:25:54.47#ibcon#enter sib2, iclass 27, count 2 2006.245.08:25:54.47#ibcon#flushed, iclass 27, count 2 2006.245.08:25:54.47#ibcon#about to write, iclass 27, count 2 2006.245.08:25:54.47#ibcon#wrote, iclass 27, count 2 2006.245.08:25:54.47#ibcon#about to read 3, iclass 27, count 2 2006.245.08:25:54.50#ibcon#read 3, iclass 27, count 2 2006.245.08:25:54.50#ibcon#about to read 4, iclass 27, count 2 2006.245.08:25:54.50#ibcon#read 4, iclass 27, count 2 2006.245.08:25:54.50#ibcon#about to read 5, iclass 27, count 2 2006.245.08:25:54.50#ibcon#read 5, iclass 27, count 2 2006.245.08:25:54.50#ibcon#about to read 6, iclass 27, count 2 2006.245.08:25:54.50#ibcon#read 6, iclass 27, count 2 2006.245.08:25:54.50#ibcon#end of sib2, iclass 27, count 2 2006.245.08:25:54.50#ibcon#*after write, iclass 27, count 2 2006.245.08:25:54.50#ibcon#*before return 0, iclass 27, count 2 2006.245.08:25:54.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:54.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.245.08:25:54.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.245.08:25:54.50#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:54.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:54.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:54.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:54.62#ibcon#enter wrdev, iclass 27, count 0 2006.245.08:25:54.62#ibcon#first serial, iclass 27, count 0 2006.245.08:25:54.62#ibcon#enter sib2, iclass 27, count 0 2006.245.08:25:54.62#ibcon#flushed, iclass 27, count 0 2006.245.08:25:54.62#ibcon#about to write, iclass 27, count 0 2006.245.08:25:54.62#ibcon#wrote, iclass 27, count 0 2006.245.08:25:54.62#ibcon#about to read 3, iclass 27, count 0 2006.245.08:25:54.64#ibcon#read 3, iclass 27, count 0 2006.245.08:25:54.64#ibcon#about to read 4, iclass 27, count 0 2006.245.08:25:54.64#ibcon#read 4, iclass 27, count 0 2006.245.08:25:54.64#ibcon#about to read 5, iclass 27, count 0 2006.245.08:25:54.64#ibcon#read 5, iclass 27, count 0 2006.245.08:25:54.64#ibcon#about to read 6, iclass 27, count 0 2006.245.08:25:54.64#ibcon#read 6, iclass 27, count 0 2006.245.08:25:54.64#ibcon#end of sib2, iclass 27, count 0 2006.245.08:25:54.64#ibcon#*mode == 0, iclass 27, count 0 2006.245.08:25:54.64#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.245.08:25:54.64#ibcon#[27=USB\r\n] 2006.245.08:25:54.64#ibcon#*before write, iclass 27, count 0 2006.245.08:25:54.64#ibcon#enter sib2, iclass 27, count 0 2006.245.08:25:54.64#ibcon#flushed, iclass 27, count 0 2006.245.08:25:54.64#ibcon#about to write, iclass 27, count 0 2006.245.08:25:54.64#ibcon#wrote, iclass 27, count 0 2006.245.08:25:54.64#ibcon#about to read 3, iclass 27, count 0 2006.245.08:25:54.67#ibcon#read 3, iclass 27, count 0 2006.245.08:25:54.67#ibcon#about to read 4, iclass 27, count 0 2006.245.08:25:54.67#ibcon#read 4, iclass 27, count 0 2006.245.08:25:54.67#ibcon#about to read 5, iclass 27, count 0 2006.245.08:25:54.67#ibcon#read 5, iclass 27, count 0 2006.245.08:25:54.67#ibcon#about to read 6, iclass 27, count 0 2006.245.08:25:54.67#ibcon#read 6, iclass 27, count 0 2006.245.08:25:54.67#ibcon#end of sib2, iclass 27, count 0 2006.245.08:25:54.67#ibcon#*after write, iclass 27, count 0 2006.245.08:25:54.67#ibcon#*before return 0, iclass 27, count 0 2006.245.08:25:54.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:54.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.245.08:25:54.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.245.08:25:54.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.245.08:25:54.67$vc4f8/vblo=6,752.99 2006.245.08:25:54.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.245.08:25:54.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.245.08:25:54.67#ibcon#ireg 17 cls_cnt 0 2006.245.08:25:54.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:54.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:54.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:54.67#ibcon#enter wrdev, iclass 29, count 0 2006.245.08:25:54.67#ibcon#first serial, iclass 29, count 0 2006.245.08:25:54.67#ibcon#enter sib2, iclass 29, count 0 2006.245.08:25:54.67#ibcon#flushed, iclass 29, count 0 2006.245.08:25:54.67#ibcon#about to write, iclass 29, count 0 2006.245.08:25:54.67#ibcon#wrote, iclass 29, count 0 2006.245.08:25:54.67#ibcon#about to read 3, iclass 29, count 0 2006.245.08:25:54.69#ibcon#read 3, iclass 29, count 0 2006.245.08:25:54.69#ibcon#about to read 4, iclass 29, count 0 2006.245.08:25:54.69#ibcon#read 4, iclass 29, count 0 2006.245.08:25:54.69#ibcon#about to read 5, iclass 29, count 0 2006.245.08:25:54.69#ibcon#read 5, iclass 29, count 0 2006.245.08:25:54.69#ibcon#about to read 6, iclass 29, count 0 2006.245.08:25:54.69#ibcon#read 6, iclass 29, count 0 2006.245.08:25:54.69#ibcon#end of sib2, iclass 29, count 0 2006.245.08:25:54.69#ibcon#*mode == 0, iclass 29, count 0 2006.245.08:25:54.69#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.245.08:25:54.69#ibcon#[28=FRQ=06,752.99\r\n] 2006.245.08:25:54.69#ibcon#*before write, iclass 29, count 0 2006.245.08:25:54.69#ibcon#enter sib2, iclass 29, count 0 2006.245.08:25:54.69#ibcon#flushed, iclass 29, count 0 2006.245.08:25:54.69#ibcon#about to write, iclass 29, count 0 2006.245.08:25:54.69#ibcon#wrote, iclass 29, count 0 2006.245.08:25:54.69#ibcon#about to read 3, iclass 29, count 0 2006.245.08:25:54.73#ibcon#read 3, iclass 29, count 0 2006.245.08:25:54.73#ibcon#about to read 4, iclass 29, count 0 2006.245.08:25:54.73#ibcon#read 4, iclass 29, count 0 2006.245.08:25:54.73#ibcon#about to read 5, iclass 29, count 0 2006.245.08:25:54.73#ibcon#read 5, iclass 29, count 0 2006.245.08:25:54.73#ibcon#about to read 6, iclass 29, count 0 2006.245.08:25:54.73#ibcon#read 6, iclass 29, count 0 2006.245.08:25:54.73#ibcon#end of sib2, iclass 29, count 0 2006.245.08:25:54.73#ibcon#*after write, iclass 29, count 0 2006.245.08:25:54.73#ibcon#*before return 0, iclass 29, count 0 2006.245.08:25:54.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:54.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.245.08:25:54.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.245.08:25:54.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.245.08:25:54.73$vc4f8/vb=6,3 2006.245.08:25:54.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.245.08:25:54.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.245.08:25:54.73#ibcon#ireg 11 cls_cnt 2 2006.245.08:25:54.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:54.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:54.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:54.79#ibcon#enter wrdev, iclass 31, count 2 2006.245.08:25:54.79#ibcon#first serial, iclass 31, count 2 2006.245.08:25:54.79#ibcon#enter sib2, iclass 31, count 2 2006.245.08:25:54.79#ibcon#flushed, iclass 31, count 2 2006.245.08:25:54.79#ibcon#about to write, iclass 31, count 2 2006.245.08:25:54.79#ibcon#wrote, iclass 31, count 2 2006.245.08:25:54.79#ibcon#about to read 3, iclass 31, count 2 2006.245.08:25:54.81#ibcon#read 3, iclass 31, count 2 2006.245.08:25:54.81#ibcon#about to read 4, iclass 31, count 2 2006.245.08:25:54.81#ibcon#read 4, iclass 31, count 2 2006.245.08:25:54.81#ibcon#about to read 5, iclass 31, count 2 2006.245.08:25:54.81#ibcon#read 5, iclass 31, count 2 2006.245.08:25:54.81#ibcon#about to read 6, iclass 31, count 2 2006.245.08:25:54.81#ibcon#read 6, iclass 31, count 2 2006.245.08:25:54.81#ibcon#end of sib2, iclass 31, count 2 2006.245.08:25:54.81#ibcon#*mode == 0, iclass 31, count 2 2006.245.08:25:54.81#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.245.08:25:54.81#ibcon#[27=AT06-03\r\n] 2006.245.08:25:54.81#ibcon#*before write, iclass 31, count 2 2006.245.08:25:54.81#ibcon#enter sib2, iclass 31, count 2 2006.245.08:25:54.81#ibcon#flushed, iclass 31, count 2 2006.245.08:25:54.81#ibcon#about to write, iclass 31, count 2 2006.245.08:25:54.81#ibcon#wrote, iclass 31, count 2 2006.245.08:25:54.81#ibcon#about to read 3, iclass 31, count 2 2006.245.08:25:54.84#ibcon#read 3, iclass 31, count 2 2006.245.08:25:54.84#ibcon#about to read 4, iclass 31, count 2 2006.245.08:25:54.84#ibcon#read 4, iclass 31, count 2 2006.245.08:25:54.84#ibcon#about to read 5, iclass 31, count 2 2006.245.08:25:54.84#ibcon#read 5, iclass 31, count 2 2006.245.08:25:54.84#ibcon#about to read 6, iclass 31, count 2 2006.245.08:25:54.84#ibcon#read 6, iclass 31, count 2 2006.245.08:25:54.84#ibcon#end of sib2, iclass 31, count 2 2006.245.08:25:54.84#ibcon#*after write, iclass 31, count 2 2006.245.08:25:54.84#ibcon#*before return 0, iclass 31, count 2 2006.245.08:25:54.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:54.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.245.08:25:54.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.245.08:25:54.84#ibcon#ireg 7 cls_cnt 0 2006.245.08:25:54.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:54.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:54.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:54.96#ibcon#enter wrdev, iclass 31, count 0 2006.245.08:25:54.96#ibcon#first serial, iclass 31, count 0 2006.245.08:25:54.96#ibcon#enter sib2, iclass 31, count 0 2006.245.08:25:54.96#ibcon#flushed, iclass 31, count 0 2006.245.08:25:54.96#ibcon#about to write, iclass 31, count 0 2006.245.08:25:54.96#ibcon#wrote, iclass 31, count 0 2006.245.08:25:54.96#ibcon#about to read 3, iclass 31, count 0 2006.245.08:25:54.98#ibcon#read 3, iclass 31, count 0 2006.245.08:25:54.98#ibcon#about to read 4, iclass 31, count 0 2006.245.08:25:54.98#ibcon#read 4, iclass 31, count 0 2006.245.08:25:54.98#ibcon#about to read 5, iclass 31, count 0 2006.245.08:25:54.98#ibcon#read 5, iclass 31, count 0 2006.245.08:25:54.98#ibcon#about to read 6, iclass 31, count 0 2006.245.08:25:54.98#ibcon#read 6, iclass 31, count 0 2006.245.08:25:54.98#ibcon#end of sib2, iclass 31, count 0 2006.245.08:25:54.98#ibcon#*mode == 0, iclass 31, count 0 2006.245.08:25:54.98#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.245.08:25:54.98#ibcon#[27=USB\r\n] 2006.245.08:25:54.98#ibcon#*before write, iclass 31, count 0 2006.245.08:25:54.98#ibcon#enter sib2, iclass 31, count 0 2006.245.08:25:54.98#ibcon#flushed, iclass 31, count 0 2006.245.08:25:54.98#ibcon#about to write, iclass 31, count 0 2006.245.08:25:54.98#ibcon#wrote, iclass 31, count 0 2006.245.08:25:54.98#ibcon#about to read 3, iclass 31, count 0 2006.245.08:25:55.01#ibcon#read 3, iclass 31, count 0 2006.245.08:25:55.01#ibcon#about to read 4, iclass 31, count 0 2006.245.08:25:55.01#ibcon#read 4, iclass 31, count 0 2006.245.08:25:55.01#ibcon#about to read 5, iclass 31, count 0 2006.245.08:25:55.01#ibcon#read 5, iclass 31, count 0 2006.245.08:25:55.01#ibcon#about to read 6, iclass 31, count 0 2006.245.08:25:55.01#ibcon#read 6, iclass 31, count 0 2006.245.08:25:55.01#ibcon#end of sib2, iclass 31, count 0 2006.245.08:25:55.01#ibcon#*after write, iclass 31, count 0 2006.245.08:25:55.01#ibcon#*before return 0, iclass 31, count 0 2006.245.08:25:55.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:55.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.245.08:25:55.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.245.08:25:55.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.245.08:25:55.01$vc4f8/vabw=wide 2006.245.08:25:55.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.245.08:25:55.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.245.08:25:55.01#ibcon#ireg 8 cls_cnt 0 2006.245.08:25:55.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:55.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:55.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:55.01#ibcon#enter wrdev, iclass 33, count 0 2006.245.08:25:55.01#ibcon#first serial, iclass 33, count 0 2006.245.08:25:55.01#ibcon#enter sib2, iclass 33, count 0 2006.245.08:25:55.01#ibcon#flushed, iclass 33, count 0 2006.245.08:25:55.01#ibcon#about to write, iclass 33, count 0 2006.245.08:25:55.01#ibcon#wrote, iclass 33, count 0 2006.245.08:25:55.01#ibcon#about to read 3, iclass 33, count 0 2006.245.08:25:55.03#ibcon#read 3, iclass 33, count 0 2006.245.08:25:55.03#ibcon#about to read 4, iclass 33, count 0 2006.245.08:25:55.03#ibcon#read 4, iclass 33, count 0 2006.245.08:25:55.03#ibcon#about to read 5, iclass 33, count 0 2006.245.08:25:55.03#ibcon#read 5, iclass 33, count 0 2006.245.08:25:55.03#ibcon#about to read 6, iclass 33, count 0 2006.245.08:25:55.03#ibcon#read 6, iclass 33, count 0 2006.245.08:25:55.03#ibcon#end of sib2, iclass 33, count 0 2006.245.08:25:55.03#ibcon#*mode == 0, iclass 33, count 0 2006.245.08:25:55.03#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.245.08:25:55.03#ibcon#[25=BW32\r\n] 2006.245.08:25:55.03#ibcon#*before write, iclass 33, count 0 2006.245.08:25:55.03#ibcon#enter sib2, iclass 33, count 0 2006.245.08:25:55.03#ibcon#flushed, iclass 33, count 0 2006.245.08:25:55.03#ibcon#about to write, iclass 33, count 0 2006.245.08:25:55.03#ibcon#wrote, iclass 33, count 0 2006.245.08:25:55.03#ibcon#about to read 3, iclass 33, count 0 2006.245.08:25:55.07#ibcon#read 3, iclass 33, count 0 2006.245.08:25:55.07#ibcon#about to read 4, iclass 33, count 0 2006.245.08:25:55.07#ibcon#read 4, iclass 33, count 0 2006.245.08:25:55.07#ibcon#about to read 5, iclass 33, count 0 2006.245.08:25:55.07#ibcon#read 5, iclass 33, count 0 2006.245.08:25:55.07#ibcon#about to read 6, iclass 33, count 0 2006.245.08:25:55.07#ibcon#read 6, iclass 33, count 0 2006.245.08:25:55.07#ibcon#end of sib2, iclass 33, count 0 2006.245.08:25:55.07#ibcon#*after write, iclass 33, count 0 2006.245.08:25:55.07#ibcon#*before return 0, iclass 33, count 0 2006.245.08:25:55.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:55.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.245.08:25:55.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.245.08:25:55.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.245.08:25:55.07$vc4f8/vbbw=wide 2006.245.08:25:55.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.245.08:25:55.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.245.08:25:55.07#ibcon#ireg 8 cls_cnt 0 2006.245.08:25:55.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:25:55.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:25:55.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:25:55.13#ibcon#enter wrdev, iclass 35, count 0 2006.245.08:25:55.13#ibcon#first serial, iclass 35, count 0 2006.245.08:25:55.13#ibcon#enter sib2, iclass 35, count 0 2006.245.08:25:55.13#ibcon#flushed, iclass 35, count 0 2006.245.08:25:55.13#ibcon#about to write, iclass 35, count 0 2006.245.08:25:55.13#ibcon#wrote, iclass 35, count 0 2006.245.08:25:55.13#ibcon#about to read 3, iclass 35, count 0 2006.245.08:25:55.15#ibcon#read 3, iclass 35, count 0 2006.245.08:25:55.15#ibcon#about to read 4, iclass 35, count 0 2006.245.08:25:55.15#ibcon#read 4, iclass 35, count 0 2006.245.08:25:55.15#ibcon#about to read 5, iclass 35, count 0 2006.245.08:25:55.15#ibcon#read 5, iclass 35, count 0 2006.245.08:25:55.15#ibcon#about to read 6, iclass 35, count 0 2006.245.08:25:55.15#ibcon#read 6, iclass 35, count 0 2006.245.08:25:55.15#ibcon#end of sib2, iclass 35, count 0 2006.245.08:25:55.15#ibcon#*mode == 0, iclass 35, count 0 2006.245.08:25:55.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.245.08:25:55.15#ibcon#[27=BW32\r\n] 2006.245.08:25:55.15#ibcon#*before write, iclass 35, count 0 2006.245.08:25:55.15#ibcon#enter sib2, iclass 35, count 0 2006.245.08:25:55.15#ibcon#flushed, iclass 35, count 0 2006.245.08:25:55.15#ibcon#about to write, iclass 35, count 0 2006.245.08:25:55.15#ibcon#wrote, iclass 35, count 0 2006.245.08:25:55.15#ibcon#about to read 3, iclass 35, count 0 2006.245.08:25:55.18#ibcon#read 3, iclass 35, count 0 2006.245.08:25:55.18#ibcon#about to read 4, iclass 35, count 0 2006.245.08:25:55.18#ibcon#read 4, iclass 35, count 0 2006.245.08:25:55.18#ibcon#about to read 5, iclass 35, count 0 2006.245.08:25:55.18#ibcon#read 5, iclass 35, count 0 2006.245.08:25:55.18#ibcon#about to read 6, iclass 35, count 0 2006.245.08:25:55.18#ibcon#read 6, iclass 35, count 0 2006.245.08:25:55.18#ibcon#end of sib2, iclass 35, count 0 2006.245.08:25:55.18#ibcon#*after write, iclass 35, count 0 2006.245.08:25:55.18#ibcon#*before return 0, iclass 35, count 0 2006.245.08:25:55.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:25:55.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.245.08:25:55.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.245.08:25:55.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.245.08:25:55.18$4f8m12a/ifd4f 2006.245.08:25:55.18$ifd4f/lo= 2006.245.08:25:55.18$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.245.08:25:55.18$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.245.08:25:55.18$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.245.08:25:55.18$ifd4f/patch= 2006.245.08:25:55.18$ifd4f/patch=lo1,a1,a2,a3,a4 2006.245.08:25:55.18$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.245.08:25:55.18$ifd4f/patch=lo3,a5,a6,a7,a8 2006.245.08:25:55.18$4f8m12a/"form=m,16.000,1:2 2006.245.08:25:55.18$4f8m12a/"tpicd 2006.245.08:25:55.18$4f8m12a/echo=off 2006.245.08:25:55.18$4f8m12a/xlog=off 2006.245.08:25:55.18:!2006.245.08:26:20 2006.245.08:26:04.14#trakl#Source acquired 2006.245.08:26:05.14#flagr#flagr/antenna,acquired 2006.245.08:26:20.00:preob 2006.245.08:26:21.14/onsource/TRACKING 2006.245.08:26:21.14:!2006.245.08:26:30 2006.245.08:26:30.00:data_valid=on 2006.245.08:26:30.00:midob 2006.245.08:26:30.14/onsource/TRACKING 2006.245.08:26:30.14/wx/26.61,1004.5,76 2006.245.08:26:30.27/cable/+6.4113E-03 2006.245.08:26:31.36/va/01,08,usb,yes,31,33 2006.245.08:26:31.36/va/02,07,usb,yes,31,32 2006.245.08:26:31.36/va/03,06,usb,yes,33,33 2006.245.08:26:31.36/va/04,07,usb,yes,32,35 2006.245.08:26:31.36/va/05,07,usb,yes,34,36 2006.245.08:26:31.36/va/06,07,usb,yes,30,30 2006.245.08:26:31.36/va/07,07,usb,yes,30,30 2006.245.08:26:31.36/va/08,08,usb,yes,26,26 2006.245.08:26:31.59/valo/01,532.99,yes,locked 2006.245.08:26:31.59/valo/02,572.99,yes,locked 2006.245.08:26:31.59/valo/03,672.99,yes,locked 2006.245.08:26:31.59/valo/04,832.99,yes,locked 2006.245.08:26:31.59/valo/05,652.99,yes,locked 2006.245.08:26:31.59/valo/06,772.99,yes,locked 2006.245.08:26:31.59/valo/07,832.99,yes,locked 2006.245.08:26:31.59/valo/08,852.99,yes,locked 2006.245.08:26:32.68/vb/01,04,usb,yes,31,29 2006.245.08:26:32.68/vb/02,04,usb,yes,33,34 2006.245.08:26:32.68/vb/03,04,usb,yes,29,33 2006.245.08:26:32.68/vb/04,04,usb,yes,30,30 2006.245.08:26:32.68/vb/05,03,usb,yes,35,40 2006.245.08:26:32.68/vb/06,03,usb,yes,36,39 2006.245.08:26:32.68/vb/07,04,usb,yes,31,31 2006.245.08:26:32.68/vb/08,03,usb,yes,36,40 2006.245.08:26:32.92/vblo/01,632.99,yes,locked 2006.245.08:26:32.92/vblo/02,640.99,yes,locked 2006.245.08:26:32.92/vblo/03,656.99,yes,locked 2006.245.08:26:32.92/vblo/04,712.99,yes,locked 2006.245.08:26:32.92/vblo/05,744.99,yes,locked 2006.245.08:26:32.92/vblo/06,752.99,yes,locked 2006.245.08:26:32.92/vblo/07,734.99,yes,locked 2006.245.08:26:32.92/vblo/08,744.99,yes,locked 2006.245.08:26:33.07/vabw/8 2006.245.08:26:33.22/vbbw/8 2006.245.08:26:33.34/xfe/off,on,13.2 2006.245.08:26:33.71/ifatt/23,28,28,28 2006.245.08:26:34.08/fmout-gps/S +4.29E-07 2006.245.08:26:34.12:!2006.245.08:27:30 2006.245.08:27:30.00:data_valid=off 2006.245.08:27:30.00:postob 2006.245.08:27:30.14/cable/+6.4109E-03 2006.245.08:27:30.14/wx/26.59,1004.4,76 2006.245.08:27:31.08/fmout-gps/S +4.30E-07 2006.245.08:27:31.08:checkk5last 2006.245.08:27:31.08&checkk5last/chk_obsdata=1 2006.245.08:27:31.08&checkk5last/chk_obsdata=2 2006.245.08:27:31.08&checkk5last/chk_obsdata=3 2006.245.08:27:31.08&checkk5last/chk_obsdata=4 2006.245.08:27:31.08&checkk5last/k5log=1 2006.245.08:27:31.08&checkk5last/k5log=2 2006.245.08:27:31.08&checkk5last/k5log=3 2006.245.08:27:31.08&checkk5last/k5log=4 2006.245.08:27:31.08&checkk5last/obsinfo 2006.245.08:27:31.49/chk_obsdata//k5ts1/T2450826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:27:31.86/chk_obsdata//k5ts2/T2450826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:27:32.26/chk_obsdata//k5ts3/T2450826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:27:32.65/chk_obsdata//k5ts4/T2450826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.245.08:27:33.34/k5log//k5ts1_log_newline 2006.245.08:27:34.04/k5log//k5ts2_log_newline 2006.245.08:27:34.73/k5log//k5ts3_log_newline 2006.245.08:27:35.41/k5log//k5ts4_log_newline 2006.245.08:27:35.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.245.08:27:35.44:"sched_end 2006.245.08:27:35.44:source=idle 2006.245.08:27:36.14:stow 2006.245.08:27:36.14&stow/source=idle 2006.245.08:27:36.14&stow/"this is stow command. 2006.245.08:27:36.14&stow/antenna=m3 2006.245.08:27:36.14#flagr#flagr/antenna,new-source 2006.245.08:27:39.01:!+10m 2006.245.08:37:39.02:standby 2006.245.08:37:39.02&standby/"this is standby command. 2006.245.08:37:39.02&standby/antenna=m0 2006.245.08:37:40.01:checkk5hdd 2006.245.08:37:40.01&checkk5hdd/chk_hdd=1 2006.245.08:37:40.01&checkk5hdd/chk_hdd=2 2006.245.08:37:40.01&checkk5hdd/chk_hdd=3 2006.245.08:37:40.01&checkk5hdd/chk_hdd=4 2006.245.08:37:42.84/chk_hdd//k5ts1/GSI00161:T245073000a.dat~T245082630a.dat[13089439744Byte] 2006.245.08:37:45.65/chk_hdd//k5ts2/GSI00255:T245073000b.dat~T245082630b.dat[13089439744Byte] 2006.245.08:37:48.45/chk_hdd//k5ts3/GSI00278:T245073000c.dat~T245082630c.dat[13089439744Byte] 2006.245.08:37:51.25/chk_hdd//k5ts4/GSI00141:T245073000d.dat~T245082630d.dat[13089439744Byte] 2006.245.08:37:51.25:sy=cp /usr2/log/k06245ts.log /usr2/log_backup/ 2006.245.08:37:51.34:log=k06246ts