2006.238.08:36:32.29:Log Opened: Mark IV Field System Version 9.7.7 2006.238.08:36:32.30:location,TSUKUB32,-140.09,36.10,61.0 2006.238.08:36:32.30:horizon1,0.,5.,360. 2006.238.08:36:32.30:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.238.08:36:32.31:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.238.08:36:32.31:drivev11,330,270,no 2006.238.08:36:32.31:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.238.08:36:32.32:drivev13,15.000,268,10.000,10.000,10.000 2006.238.08:36:32.32:drivev21,330,270,no 2006.238.08:36:32.33:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.238.08:36:32.37:drivev23,15.000,268,10.000,10.000,10.000 2006.238.08:36:32.38:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.238.08:36:32.38:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.238.08:36:32.39:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.238.08:36:32.39:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.238.08:36:32.39:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.238.08:36:32.40:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.238.08:36:32.40:time,-0.364,101.533,rate 2006.238.08:36:32.41:flagr,200 2006.238.08:36:32.41:proc=k06239ts 2006.238.08:36:32.41:" k06239 2006 tsukub32 t ts 2006.238.08:36:32.46:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.238.08:36:32.47:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.238.08:36:32.47:" 108 tsukub32 14 17400 2006.238.08:36:32.47:" drudg version 050216 compiled under fs 9.7.07 2006.238.08:36:32.48:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.238.08:36:32.48:!2006.239.06:29:50 2006.239.01:36:25.75?ERROR st -97 Trouble decoding pressure data 2006.239.01:36:25.75#wxget#04 1.4 2.8 25.70 851013.1 2006.239.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.239.06:29:50.03:!2006.239.07:19:50 2006.239.07:19:50.00:unstow 2006.239.07:19:50.00&unstow/antenna=e 2006.239.07:19:50.00&unstow/!+10s 2006.239.07:19:50.00&unstow/antenna=m2 2006.239.07:20:02.01:scan_name=239-0730,k06239,60 2006.239.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.239.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.239.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.239.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.239.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.239.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.239.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.239.07:20:03.14:ready_k5 2006.239.07:20:03.14&ready_k5/obsinfo=st 2006.239.07:20:03.14&ready_k5/autoobs=1 2006.239.07:20:03.14&ready_k5/autoobs=2 2006.239.07:20:03.14&ready_k5/autoobs=3 2006.239.07:20:03.14&ready_k5/autoobs=4 2006.239.07:20:03.14&ready_k5/obsinfo 2006.239.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.239.07:20:03.14#flagr#flagr/antenna,new-source 2006.239.07:20:06.32/autoobs//k5ts1/ autoobs started! 2006.239.07:20:09.43/autoobs//k5ts2/ autoobs started! 2006.239.07:20:12.57/autoobs//k5ts3/ autoobs started! 2006.239.07:20:15.69/autoobs//k5ts4/ autoobs started! 2006.239.07:20:15.72/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:20:15.72:4f8m12a=1 2006.239.07:20:15.72&4f8m12a/xlog=on 2006.239.07:20:15.72&4f8m12a/echo=on 2006.239.07:20:15.72&4f8m12a/pcalon 2006.239.07:20:15.72&4f8m12a/"tpicd=stop 2006.239.07:20:15.72&4f8m12a/vc4f8 2006.239.07:20:15.72&4f8m12a/ifd4f 2006.239.07:20:15.72&4f8m12a/"form=m,16.000,1:2 2006.239.07:20:15.72&4f8m12a/"tpicd 2006.239.07:20:15.72&4f8m12a/echo=off 2006.239.07:20:15.72&4f8m12a/xlog=off 2006.239.07:20:15.72$4f8m12a/echo=on 2006.239.07:20:15.72$4f8m12a/pcalon 2006.239.07:20:15.72&pcalon/"no phase cal control is implemented here 2006.239.07:20:15.72$pcalon/"no phase cal control is implemented here 2006.239.07:20:15.72$4f8m12a/"tpicd=stop 2006.239.07:20:15.72$4f8m12a/vc4f8 2006.239.07:20:15.72&vc4f8/valo=1,532.99 2006.239.07:20:15.72&vc4f8/va=1,8 2006.239.07:20:15.72&vc4f8/valo=2,572.99 2006.239.07:20:15.72&vc4f8/va=2,7 2006.239.07:20:15.72&vc4f8/valo=3,672.99 2006.239.07:20:15.72&vc4f8/va=3,7 2006.239.07:20:15.72&vc4f8/valo=4,832.99 2006.239.07:20:15.72&vc4f8/va=4,7 2006.239.07:20:15.72&vc4f8/valo=5,652.99 2006.239.07:20:15.72&vc4f8/va=5,8 2006.239.07:20:15.72&vc4f8/valo=6,772.99 2006.239.07:20:15.72&vc4f8/va=6,7 2006.239.07:20:15.72&vc4f8/valo=7,832.99 2006.239.07:20:15.72&vc4f8/va=7,7 2006.239.07:20:15.72&vc4f8/valo=8,852.99 2006.239.07:20:15.72&vc4f8/va=8,7 2006.239.07:20:15.72&vc4f8/vblo=1,632.99 2006.239.07:20:15.72&vc4f8/vb=1,4 2006.239.07:20:15.72&vc4f8/vblo=2,640.99 2006.239.07:20:15.72&vc4f8/vb=2,4 2006.239.07:20:15.72&vc4f8/vblo=3,656.99 2006.239.07:20:15.72&vc4f8/vb=3,4 2006.239.07:20:15.72&vc4f8/vblo=4,712.99 2006.239.07:20:15.72&vc4f8/vb=4,4 2006.239.07:20:15.72&vc4f8/vblo=5,744.99 2006.239.07:20:15.72&vc4f8/vb=5,4 2006.239.07:20:15.72&vc4f8/vblo=6,752.99 2006.239.07:20:15.72&vc4f8/vb=6,4 2006.239.07:20:15.72&vc4f8/vabw=wide 2006.239.07:20:15.72&vc4f8/vbbw=wide 2006.239.07:20:15.72$vc4f8/valo=1,532.99 2006.239.07:20:15.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:20:15.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:20:15.76#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:15.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:15.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:15.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:15.76#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:20:15.76#ibcon#first serial, iclass 40, count 0 2006.239.07:20:15.76#ibcon#enter sib2, iclass 40, count 0 2006.239.07:20:15.76#ibcon#flushed, iclass 40, count 0 2006.239.07:20:15.76#ibcon#about to write, iclass 40, count 0 2006.239.07:20:15.76#ibcon#wrote, iclass 40, count 0 2006.239.07:20:15.76#ibcon#about to read 3, iclass 40, count 0 2006.239.07:20:15.78#ibcon#read 3, iclass 40, count 0 2006.239.07:20:15.78#ibcon#about to read 4, iclass 40, count 0 2006.239.07:20:15.78#ibcon#read 4, iclass 40, count 0 2006.239.07:20:15.78#ibcon#about to read 5, iclass 40, count 0 2006.239.07:20:15.78#ibcon#read 5, iclass 40, count 0 2006.239.07:20:15.78#ibcon#about to read 6, iclass 40, count 0 2006.239.07:20:15.78#ibcon#read 6, iclass 40, count 0 2006.239.07:20:15.78#ibcon#end of sib2, iclass 40, count 0 2006.239.07:20:15.78#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:20:15.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:20:15.78#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:20:15.78#ibcon#*before write, iclass 40, count 0 2006.239.07:20:15.78#ibcon#enter sib2, iclass 40, count 0 2006.239.07:20:15.78#ibcon#flushed, iclass 40, count 0 2006.239.07:20:15.78#ibcon#about to write, iclass 40, count 0 2006.239.07:20:15.78#ibcon#wrote, iclass 40, count 0 2006.239.07:20:15.78#ibcon#about to read 3, iclass 40, count 0 2006.239.07:20:15.83#ibcon#read 3, iclass 40, count 0 2006.239.07:20:15.83#ibcon#about to read 4, iclass 40, count 0 2006.239.07:20:15.83#ibcon#read 4, iclass 40, count 0 2006.239.07:20:15.83#ibcon#about to read 5, iclass 40, count 0 2006.239.07:20:15.83#ibcon#read 5, iclass 40, count 0 2006.239.07:20:15.83#ibcon#about to read 6, iclass 40, count 0 2006.239.07:20:15.83#ibcon#read 6, iclass 40, count 0 2006.239.07:20:15.83#ibcon#end of sib2, iclass 40, count 0 2006.239.07:20:15.83#ibcon#*after write, iclass 40, count 0 2006.239.07:20:15.83#ibcon#*before return 0, iclass 40, count 0 2006.239.07:20:15.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:15.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:15.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:20:15.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:20:15.83$vc4f8/va=1,8 2006.239.07:20:15.83#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:20:15.83#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:20:15.83#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:15.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:15.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:15.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:15.83#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:20:15.83#ibcon#first serial, iclass 4, count 2 2006.239.07:20:15.83#ibcon#enter sib2, iclass 4, count 2 2006.239.07:20:15.83#ibcon#flushed, iclass 4, count 2 2006.239.07:20:15.83#ibcon#about to write, iclass 4, count 2 2006.239.07:20:15.83#ibcon#wrote, iclass 4, count 2 2006.239.07:20:15.83#ibcon#about to read 3, iclass 4, count 2 2006.239.07:20:15.85#ibcon#read 3, iclass 4, count 2 2006.239.07:20:15.85#ibcon#about to read 4, iclass 4, count 2 2006.239.07:20:15.85#ibcon#read 4, iclass 4, count 2 2006.239.07:20:15.85#ibcon#about to read 5, iclass 4, count 2 2006.239.07:20:15.85#ibcon#read 5, iclass 4, count 2 2006.239.07:20:15.85#ibcon#about to read 6, iclass 4, count 2 2006.239.07:20:15.85#ibcon#read 6, iclass 4, count 2 2006.239.07:20:15.85#ibcon#end of sib2, iclass 4, count 2 2006.239.07:20:15.85#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:20:15.85#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:20:15.85#ibcon#[25=AT01-08\r\n] 2006.239.07:20:15.85#ibcon#*before write, iclass 4, count 2 2006.239.07:20:15.85#ibcon#enter sib2, iclass 4, count 2 2006.239.07:20:15.85#ibcon#flushed, iclass 4, count 2 2006.239.07:20:15.85#ibcon#about to write, iclass 4, count 2 2006.239.07:20:15.85#ibcon#wrote, iclass 4, count 2 2006.239.07:20:15.85#ibcon#about to read 3, iclass 4, count 2 2006.239.07:20:15.88#ibcon#read 3, iclass 4, count 2 2006.239.07:20:15.88#ibcon#about to read 4, iclass 4, count 2 2006.239.07:20:15.88#ibcon#read 4, iclass 4, count 2 2006.239.07:20:15.88#ibcon#about to read 5, iclass 4, count 2 2006.239.07:20:15.88#ibcon#read 5, iclass 4, count 2 2006.239.07:20:15.88#ibcon#about to read 6, iclass 4, count 2 2006.239.07:20:15.88#ibcon#read 6, iclass 4, count 2 2006.239.07:20:15.88#ibcon#end of sib2, iclass 4, count 2 2006.239.07:20:15.88#ibcon#*after write, iclass 4, count 2 2006.239.07:20:15.88#ibcon#*before return 0, iclass 4, count 2 2006.239.07:20:15.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:15.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:15.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:20:15.88#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:15.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:16.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:16.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:16.00#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:20:16.00#ibcon#first serial, iclass 4, count 0 2006.239.07:20:16.00#ibcon#enter sib2, iclass 4, count 0 2006.239.07:20:16.00#ibcon#flushed, iclass 4, count 0 2006.239.07:20:16.00#ibcon#about to write, iclass 4, count 0 2006.239.07:20:16.00#ibcon#wrote, iclass 4, count 0 2006.239.07:20:16.00#ibcon#about to read 3, iclass 4, count 0 2006.239.07:20:16.02#ibcon#read 3, iclass 4, count 0 2006.239.07:20:16.02#ibcon#about to read 4, iclass 4, count 0 2006.239.07:20:16.02#ibcon#read 4, iclass 4, count 0 2006.239.07:20:16.02#ibcon#about to read 5, iclass 4, count 0 2006.239.07:20:16.02#ibcon#read 5, iclass 4, count 0 2006.239.07:20:16.02#ibcon#about to read 6, iclass 4, count 0 2006.239.07:20:16.02#ibcon#read 6, iclass 4, count 0 2006.239.07:20:16.02#ibcon#end of sib2, iclass 4, count 0 2006.239.07:20:16.02#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:20:16.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:20:16.02#ibcon#[25=USB\r\n] 2006.239.07:20:16.02#ibcon#*before write, iclass 4, count 0 2006.239.07:20:16.02#ibcon#enter sib2, iclass 4, count 0 2006.239.07:20:16.02#ibcon#flushed, iclass 4, count 0 2006.239.07:20:16.02#ibcon#about to write, iclass 4, count 0 2006.239.07:20:16.02#ibcon#wrote, iclass 4, count 0 2006.239.07:20:16.02#ibcon#about to read 3, iclass 4, count 0 2006.239.07:20:16.05#ibcon#read 3, iclass 4, count 0 2006.239.07:20:16.05#ibcon#about to read 4, iclass 4, count 0 2006.239.07:20:16.05#ibcon#read 4, iclass 4, count 0 2006.239.07:20:16.05#ibcon#about to read 5, iclass 4, count 0 2006.239.07:20:16.05#ibcon#read 5, iclass 4, count 0 2006.239.07:20:16.05#ibcon#about to read 6, iclass 4, count 0 2006.239.07:20:16.05#ibcon#read 6, iclass 4, count 0 2006.239.07:20:16.05#ibcon#end of sib2, iclass 4, count 0 2006.239.07:20:16.05#ibcon#*after write, iclass 4, count 0 2006.239.07:20:16.05#ibcon#*before return 0, iclass 4, count 0 2006.239.07:20:16.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:16.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:16.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:20:16.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:20:16.05$vc4f8/valo=2,572.99 2006.239.07:20:16.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:20:16.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:20:16.05#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:16.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:16.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:16.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:16.05#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:20:16.05#ibcon#first serial, iclass 6, count 0 2006.239.07:20:16.05#ibcon#enter sib2, iclass 6, count 0 2006.239.07:20:16.05#ibcon#flushed, iclass 6, count 0 2006.239.07:20:16.05#ibcon#about to write, iclass 6, count 0 2006.239.07:20:16.05#ibcon#wrote, iclass 6, count 0 2006.239.07:20:16.05#ibcon#about to read 3, iclass 6, count 0 2006.239.07:20:16.07#ibcon#read 3, iclass 6, count 0 2006.239.07:20:16.07#ibcon#about to read 4, iclass 6, count 0 2006.239.07:20:16.07#ibcon#read 4, iclass 6, count 0 2006.239.07:20:16.07#ibcon#about to read 5, iclass 6, count 0 2006.239.07:20:16.07#ibcon#read 5, iclass 6, count 0 2006.239.07:20:16.07#ibcon#about to read 6, iclass 6, count 0 2006.239.07:20:16.07#ibcon#read 6, iclass 6, count 0 2006.239.07:20:16.07#ibcon#end of sib2, iclass 6, count 0 2006.239.07:20:16.07#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:20:16.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:20:16.07#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:20:16.07#ibcon#*before write, iclass 6, count 0 2006.239.07:20:16.07#ibcon#enter sib2, iclass 6, count 0 2006.239.07:20:16.07#ibcon#flushed, iclass 6, count 0 2006.239.07:20:16.07#ibcon#about to write, iclass 6, count 0 2006.239.07:20:16.07#ibcon#wrote, iclass 6, count 0 2006.239.07:20:16.07#ibcon#about to read 3, iclass 6, count 0 2006.239.07:20:16.11#ibcon#read 3, iclass 6, count 0 2006.239.07:20:16.11#ibcon#about to read 4, iclass 6, count 0 2006.239.07:20:16.11#ibcon#read 4, iclass 6, count 0 2006.239.07:20:16.11#ibcon#about to read 5, iclass 6, count 0 2006.239.07:20:16.11#ibcon#read 5, iclass 6, count 0 2006.239.07:20:16.11#ibcon#about to read 6, iclass 6, count 0 2006.239.07:20:16.11#ibcon#read 6, iclass 6, count 0 2006.239.07:20:16.11#ibcon#end of sib2, iclass 6, count 0 2006.239.07:20:16.11#ibcon#*after write, iclass 6, count 0 2006.239.07:20:16.11#ibcon#*before return 0, iclass 6, count 0 2006.239.07:20:16.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:16.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:16.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:20:16.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:20:16.11$vc4f8/va=2,7 2006.239.07:20:16.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:20:16.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:20:16.11#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:16.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:16.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:16.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:16.17#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:20:16.17#ibcon#first serial, iclass 10, count 2 2006.239.07:20:16.17#ibcon#enter sib2, iclass 10, count 2 2006.239.07:20:16.17#ibcon#flushed, iclass 10, count 2 2006.239.07:20:16.17#ibcon#about to write, iclass 10, count 2 2006.239.07:20:16.17#ibcon#wrote, iclass 10, count 2 2006.239.07:20:16.17#ibcon#about to read 3, iclass 10, count 2 2006.239.07:20:16.19#ibcon#read 3, iclass 10, count 2 2006.239.07:20:16.19#ibcon#about to read 4, iclass 10, count 2 2006.239.07:20:16.19#ibcon#read 4, iclass 10, count 2 2006.239.07:20:16.19#ibcon#about to read 5, iclass 10, count 2 2006.239.07:20:16.19#ibcon#read 5, iclass 10, count 2 2006.239.07:20:16.19#ibcon#about to read 6, iclass 10, count 2 2006.239.07:20:16.19#ibcon#read 6, iclass 10, count 2 2006.239.07:20:16.19#ibcon#end of sib2, iclass 10, count 2 2006.239.07:20:16.19#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:20:16.19#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:20:16.19#ibcon#[25=AT02-07\r\n] 2006.239.07:20:16.19#ibcon#*before write, iclass 10, count 2 2006.239.07:20:16.19#ibcon#enter sib2, iclass 10, count 2 2006.239.07:20:16.19#ibcon#flushed, iclass 10, count 2 2006.239.07:20:16.19#ibcon#about to write, iclass 10, count 2 2006.239.07:20:16.19#ibcon#wrote, iclass 10, count 2 2006.239.07:20:16.19#ibcon#about to read 3, iclass 10, count 2 2006.239.07:20:16.22#ibcon#read 3, iclass 10, count 2 2006.239.07:20:16.22#ibcon#about to read 4, iclass 10, count 2 2006.239.07:20:16.22#ibcon#read 4, iclass 10, count 2 2006.239.07:20:16.22#ibcon#about to read 5, iclass 10, count 2 2006.239.07:20:16.22#ibcon#read 5, iclass 10, count 2 2006.239.07:20:16.22#ibcon#about to read 6, iclass 10, count 2 2006.239.07:20:16.22#ibcon#read 6, iclass 10, count 2 2006.239.07:20:16.22#ibcon#end of sib2, iclass 10, count 2 2006.239.07:20:16.22#ibcon#*after write, iclass 10, count 2 2006.239.07:20:16.22#ibcon#*before return 0, iclass 10, count 2 2006.239.07:20:16.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:16.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:16.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:20:16.22#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:16.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:16.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:16.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:16.34#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:20:16.34#ibcon#first serial, iclass 10, count 0 2006.239.07:20:16.34#ibcon#enter sib2, iclass 10, count 0 2006.239.07:20:16.34#ibcon#flushed, iclass 10, count 0 2006.239.07:20:16.34#ibcon#about to write, iclass 10, count 0 2006.239.07:20:16.34#ibcon#wrote, iclass 10, count 0 2006.239.07:20:16.34#ibcon#about to read 3, iclass 10, count 0 2006.239.07:20:16.36#ibcon#read 3, iclass 10, count 0 2006.239.07:20:16.36#ibcon#about to read 4, iclass 10, count 0 2006.239.07:20:16.36#ibcon#read 4, iclass 10, count 0 2006.239.07:20:16.36#ibcon#about to read 5, iclass 10, count 0 2006.239.07:20:16.36#ibcon#read 5, iclass 10, count 0 2006.239.07:20:16.36#ibcon#about to read 6, iclass 10, count 0 2006.239.07:20:16.36#ibcon#read 6, iclass 10, count 0 2006.239.07:20:16.36#ibcon#end of sib2, iclass 10, count 0 2006.239.07:20:16.36#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:20:16.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:20:16.36#ibcon#[25=USB\r\n] 2006.239.07:20:16.36#ibcon#*before write, iclass 10, count 0 2006.239.07:20:16.36#ibcon#enter sib2, iclass 10, count 0 2006.239.07:20:16.36#ibcon#flushed, iclass 10, count 0 2006.239.07:20:16.36#ibcon#about to write, iclass 10, count 0 2006.239.07:20:16.36#ibcon#wrote, iclass 10, count 0 2006.239.07:20:16.36#ibcon#about to read 3, iclass 10, count 0 2006.239.07:20:16.39#ibcon#read 3, iclass 10, count 0 2006.239.07:20:16.39#ibcon#about to read 4, iclass 10, count 0 2006.239.07:20:16.39#ibcon#read 4, iclass 10, count 0 2006.239.07:20:16.39#ibcon#about to read 5, iclass 10, count 0 2006.239.07:20:16.39#ibcon#read 5, iclass 10, count 0 2006.239.07:20:16.39#ibcon#about to read 6, iclass 10, count 0 2006.239.07:20:16.39#ibcon#read 6, iclass 10, count 0 2006.239.07:20:16.39#ibcon#end of sib2, iclass 10, count 0 2006.239.07:20:16.39#ibcon#*after write, iclass 10, count 0 2006.239.07:20:16.39#ibcon#*before return 0, iclass 10, count 0 2006.239.07:20:16.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:16.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:16.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:20:16.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:20:16.39$vc4f8/valo=3,672.99 2006.239.07:20:16.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:20:16.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:20:16.39#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:16.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:16.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:16.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:16.39#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:20:16.39#ibcon#first serial, iclass 12, count 0 2006.239.07:20:16.39#ibcon#enter sib2, iclass 12, count 0 2006.239.07:20:16.39#ibcon#flushed, iclass 12, count 0 2006.239.07:20:16.39#ibcon#about to write, iclass 12, count 0 2006.239.07:20:16.39#ibcon#wrote, iclass 12, count 0 2006.239.07:20:16.39#ibcon#about to read 3, iclass 12, count 0 2006.239.07:20:16.41#ibcon#read 3, iclass 12, count 0 2006.239.07:20:16.41#ibcon#about to read 4, iclass 12, count 0 2006.239.07:20:16.41#ibcon#read 4, iclass 12, count 0 2006.239.07:20:16.41#ibcon#about to read 5, iclass 12, count 0 2006.239.07:20:16.41#ibcon#read 5, iclass 12, count 0 2006.239.07:20:16.41#ibcon#about to read 6, iclass 12, count 0 2006.239.07:20:16.41#ibcon#read 6, iclass 12, count 0 2006.239.07:20:16.41#ibcon#end of sib2, iclass 12, count 0 2006.239.07:20:16.41#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:20:16.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:20:16.41#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:20:16.41#ibcon#*before write, iclass 12, count 0 2006.239.07:20:16.41#ibcon#enter sib2, iclass 12, count 0 2006.239.07:20:16.41#ibcon#flushed, iclass 12, count 0 2006.239.07:20:16.41#ibcon#about to write, iclass 12, count 0 2006.239.07:20:16.41#ibcon#wrote, iclass 12, count 0 2006.239.07:20:16.41#ibcon#about to read 3, iclass 12, count 0 2006.239.07:20:16.45#ibcon#read 3, iclass 12, count 0 2006.239.07:20:16.45#ibcon#about to read 4, iclass 12, count 0 2006.239.07:20:16.45#ibcon#read 4, iclass 12, count 0 2006.239.07:20:16.45#ibcon#about to read 5, iclass 12, count 0 2006.239.07:20:16.45#ibcon#read 5, iclass 12, count 0 2006.239.07:20:16.45#ibcon#about to read 6, iclass 12, count 0 2006.239.07:20:16.45#ibcon#read 6, iclass 12, count 0 2006.239.07:20:16.45#ibcon#end of sib2, iclass 12, count 0 2006.239.07:20:16.45#ibcon#*after write, iclass 12, count 0 2006.239.07:20:16.45#ibcon#*before return 0, iclass 12, count 0 2006.239.07:20:16.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:16.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:16.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:20:16.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:20:16.45$vc4f8/va=3,7 2006.239.07:20:16.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.07:20:16.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.07:20:16.45#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:16.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:16.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:16.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:16.51#ibcon#enter wrdev, iclass 14, count 2 2006.239.07:20:16.51#ibcon#first serial, iclass 14, count 2 2006.239.07:20:16.51#ibcon#enter sib2, iclass 14, count 2 2006.239.07:20:16.51#ibcon#flushed, iclass 14, count 2 2006.239.07:20:16.51#ibcon#about to write, iclass 14, count 2 2006.239.07:20:16.51#ibcon#wrote, iclass 14, count 2 2006.239.07:20:16.51#ibcon#about to read 3, iclass 14, count 2 2006.239.07:20:16.53#ibcon#read 3, iclass 14, count 2 2006.239.07:20:16.53#ibcon#about to read 4, iclass 14, count 2 2006.239.07:20:16.53#ibcon#read 4, iclass 14, count 2 2006.239.07:20:16.53#ibcon#about to read 5, iclass 14, count 2 2006.239.07:20:16.53#ibcon#read 5, iclass 14, count 2 2006.239.07:20:16.53#ibcon#about to read 6, iclass 14, count 2 2006.239.07:20:16.53#ibcon#read 6, iclass 14, count 2 2006.239.07:20:16.53#ibcon#end of sib2, iclass 14, count 2 2006.239.07:20:16.53#ibcon#*mode == 0, iclass 14, count 2 2006.239.07:20:16.53#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.07:20:16.53#ibcon#[25=AT03-07\r\n] 2006.239.07:20:16.53#ibcon#*before write, iclass 14, count 2 2006.239.07:20:16.53#ibcon#enter sib2, iclass 14, count 2 2006.239.07:20:16.53#ibcon#flushed, iclass 14, count 2 2006.239.07:20:16.53#ibcon#about to write, iclass 14, count 2 2006.239.07:20:16.53#ibcon#wrote, iclass 14, count 2 2006.239.07:20:16.53#ibcon#about to read 3, iclass 14, count 2 2006.239.07:20:16.56#ibcon#read 3, iclass 14, count 2 2006.239.07:20:16.56#ibcon#about to read 4, iclass 14, count 2 2006.239.07:20:16.56#ibcon#read 4, iclass 14, count 2 2006.239.07:20:16.56#ibcon#about to read 5, iclass 14, count 2 2006.239.07:20:16.56#ibcon#read 5, iclass 14, count 2 2006.239.07:20:16.56#ibcon#about to read 6, iclass 14, count 2 2006.239.07:20:16.56#ibcon#read 6, iclass 14, count 2 2006.239.07:20:16.56#ibcon#end of sib2, iclass 14, count 2 2006.239.07:20:16.56#ibcon#*after write, iclass 14, count 2 2006.239.07:20:16.56#ibcon#*before return 0, iclass 14, count 2 2006.239.07:20:16.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:16.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:16.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.07:20:16.56#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:16.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:16.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:16.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:16.68#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:20:16.68#ibcon#first serial, iclass 14, count 0 2006.239.07:20:16.68#ibcon#enter sib2, iclass 14, count 0 2006.239.07:20:16.68#ibcon#flushed, iclass 14, count 0 2006.239.07:20:16.68#ibcon#about to write, iclass 14, count 0 2006.239.07:20:16.68#ibcon#wrote, iclass 14, count 0 2006.239.07:20:16.68#ibcon#about to read 3, iclass 14, count 0 2006.239.07:20:16.70#ibcon#read 3, iclass 14, count 0 2006.239.07:20:16.70#ibcon#about to read 4, iclass 14, count 0 2006.239.07:20:16.70#ibcon#read 4, iclass 14, count 0 2006.239.07:20:16.70#ibcon#about to read 5, iclass 14, count 0 2006.239.07:20:16.70#ibcon#read 5, iclass 14, count 0 2006.239.07:20:16.70#ibcon#about to read 6, iclass 14, count 0 2006.239.07:20:16.70#ibcon#read 6, iclass 14, count 0 2006.239.07:20:16.70#ibcon#end of sib2, iclass 14, count 0 2006.239.07:20:16.70#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:20:16.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:20:16.70#ibcon#[25=USB\r\n] 2006.239.07:20:16.70#ibcon#*before write, iclass 14, count 0 2006.239.07:20:16.70#ibcon#enter sib2, iclass 14, count 0 2006.239.07:20:16.70#ibcon#flushed, iclass 14, count 0 2006.239.07:20:16.70#ibcon#about to write, iclass 14, count 0 2006.239.07:20:16.70#ibcon#wrote, iclass 14, count 0 2006.239.07:20:16.70#ibcon#about to read 3, iclass 14, count 0 2006.239.07:20:16.74#ibcon#read 3, iclass 14, count 0 2006.239.07:20:16.74#ibcon#about to read 4, iclass 14, count 0 2006.239.07:20:16.74#ibcon#read 4, iclass 14, count 0 2006.239.07:20:16.74#ibcon#about to read 5, iclass 14, count 0 2006.239.07:20:16.74#ibcon#read 5, iclass 14, count 0 2006.239.07:20:16.74#ibcon#about to read 6, iclass 14, count 0 2006.239.07:20:16.74#ibcon#read 6, iclass 14, count 0 2006.239.07:20:16.74#ibcon#end of sib2, iclass 14, count 0 2006.239.07:20:16.74#ibcon#*after write, iclass 14, count 0 2006.239.07:20:16.74#ibcon#*before return 0, iclass 14, count 0 2006.239.07:20:16.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:16.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:16.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:20:16.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:20:16.74$vc4f8/valo=4,832.99 2006.239.07:20:16.74#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:20:16.74#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:20:16.74#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:16.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:16.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:16.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:16.74#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:20:16.74#ibcon#first serial, iclass 16, count 0 2006.239.07:20:16.74#ibcon#enter sib2, iclass 16, count 0 2006.239.07:20:16.74#ibcon#flushed, iclass 16, count 0 2006.239.07:20:16.74#ibcon#about to write, iclass 16, count 0 2006.239.07:20:16.74#ibcon#wrote, iclass 16, count 0 2006.239.07:20:16.74#ibcon#about to read 3, iclass 16, count 0 2006.239.07:20:16.76#ibcon#read 3, iclass 16, count 0 2006.239.07:20:16.76#ibcon#about to read 4, iclass 16, count 0 2006.239.07:20:16.76#ibcon#read 4, iclass 16, count 0 2006.239.07:20:16.76#ibcon#about to read 5, iclass 16, count 0 2006.239.07:20:16.76#ibcon#read 5, iclass 16, count 0 2006.239.07:20:16.76#ibcon#about to read 6, iclass 16, count 0 2006.239.07:20:16.76#ibcon#read 6, iclass 16, count 0 2006.239.07:20:16.76#ibcon#end of sib2, iclass 16, count 0 2006.239.07:20:16.76#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:20:16.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:20:16.76#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:20:16.76#ibcon#*before write, iclass 16, count 0 2006.239.07:20:16.76#ibcon#enter sib2, iclass 16, count 0 2006.239.07:20:16.76#ibcon#flushed, iclass 16, count 0 2006.239.07:20:16.76#ibcon#about to write, iclass 16, count 0 2006.239.07:20:16.76#ibcon#wrote, iclass 16, count 0 2006.239.07:20:16.76#ibcon#about to read 3, iclass 16, count 0 2006.239.07:20:16.81#ibcon#read 3, iclass 16, count 0 2006.239.07:20:16.81#ibcon#about to read 4, iclass 16, count 0 2006.239.07:20:16.81#ibcon#read 4, iclass 16, count 0 2006.239.07:20:16.81#ibcon#about to read 5, iclass 16, count 0 2006.239.07:20:16.81#ibcon#read 5, iclass 16, count 0 2006.239.07:20:16.81#ibcon#about to read 6, iclass 16, count 0 2006.239.07:20:16.81#ibcon#read 6, iclass 16, count 0 2006.239.07:20:16.81#ibcon#end of sib2, iclass 16, count 0 2006.239.07:20:16.81#ibcon#*after write, iclass 16, count 0 2006.239.07:20:16.81#ibcon#*before return 0, iclass 16, count 0 2006.239.07:20:16.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:16.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:16.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:20:16.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:20:16.81$vc4f8/va=4,7 2006.239.07:20:16.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:20:16.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:20:16.81#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:16.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:16.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:16.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:16.85#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:20:16.85#ibcon#first serial, iclass 18, count 2 2006.239.07:20:16.85#ibcon#enter sib2, iclass 18, count 2 2006.239.07:20:16.85#ibcon#flushed, iclass 18, count 2 2006.239.07:20:16.85#ibcon#about to write, iclass 18, count 2 2006.239.07:20:16.85#ibcon#wrote, iclass 18, count 2 2006.239.07:20:16.85#ibcon#about to read 3, iclass 18, count 2 2006.239.07:20:16.87#ibcon#read 3, iclass 18, count 2 2006.239.07:20:16.87#ibcon#about to read 4, iclass 18, count 2 2006.239.07:20:16.87#ibcon#read 4, iclass 18, count 2 2006.239.07:20:16.87#ibcon#about to read 5, iclass 18, count 2 2006.239.07:20:16.87#ibcon#read 5, iclass 18, count 2 2006.239.07:20:16.87#ibcon#about to read 6, iclass 18, count 2 2006.239.07:20:16.87#ibcon#read 6, iclass 18, count 2 2006.239.07:20:16.87#ibcon#end of sib2, iclass 18, count 2 2006.239.07:20:16.87#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:20:16.87#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:20:16.87#ibcon#[25=AT04-07\r\n] 2006.239.07:20:16.87#ibcon#*before write, iclass 18, count 2 2006.239.07:20:16.87#ibcon#enter sib2, iclass 18, count 2 2006.239.07:20:16.87#ibcon#flushed, iclass 18, count 2 2006.239.07:20:16.87#ibcon#about to write, iclass 18, count 2 2006.239.07:20:16.87#ibcon#wrote, iclass 18, count 2 2006.239.07:20:16.87#ibcon#about to read 3, iclass 18, count 2 2006.239.07:20:16.90#ibcon#read 3, iclass 18, count 2 2006.239.07:20:16.90#ibcon#about to read 4, iclass 18, count 2 2006.239.07:20:16.90#ibcon#read 4, iclass 18, count 2 2006.239.07:20:16.90#ibcon#about to read 5, iclass 18, count 2 2006.239.07:20:16.90#ibcon#read 5, iclass 18, count 2 2006.239.07:20:16.90#ibcon#about to read 6, iclass 18, count 2 2006.239.07:20:16.90#ibcon#read 6, iclass 18, count 2 2006.239.07:20:16.90#ibcon#end of sib2, iclass 18, count 2 2006.239.07:20:16.90#ibcon#*after write, iclass 18, count 2 2006.239.07:20:16.90#ibcon#*before return 0, iclass 18, count 2 2006.239.07:20:16.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:16.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:16.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:20:16.90#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:16.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:17.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:17.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:17.02#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:20:17.02#ibcon#first serial, iclass 18, count 0 2006.239.07:20:17.02#ibcon#enter sib2, iclass 18, count 0 2006.239.07:20:17.02#ibcon#flushed, iclass 18, count 0 2006.239.07:20:17.02#ibcon#about to write, iclass 18, count 0 2006.239.07:20:17.02#ibcon#wrote, iclass 18, count 0 2006.239.07:20:17.02#ibcon#about to read 3, iclass 18, count 0 2006.239.07:20:17.04#ibcon#read 3, iclass 18, count 0 2006.239.07:20:17.04#ibcon#about to read 4, iclass 18, count 0 2006.239.07:20:17.04#ibcon#read 4, iclass 18, count 0 2006.239.07:20:17.04#ibcon#about to read 5, iclass 18, count 0 2006.239.07:20:17.04#ibcon#read 5, iclass 18, count 0 2006.239.07:20:17.04#ibcon#about to read 6, iclass 18, count 0 2006.239.07:20:17.04#ibcon#read 6, iclass 18, count 0 2006.239.07:20:17.04#ibcon#end of sib2, iclass 18, count 0 2006.239.07:20:17.04#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:20:17.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:20:17.04#ibcon#[25=USB\r\n] 2006.239.07:20:17.04#ibcon#*before write, iclass 18, count 0 2006.239.07:20:17.04#ibcon#enter sib2, iclass 18, count 0 2006.239.07:20:17.04#ibcon#flushed, iclass 18, count 0 2006.239.07:20:17.04#ibcon#about to write, iclass 18, count 0 2006.239.07:20:17.04#ibcon#wrote, iclass 18, count 0 2006.239.07:20:17.04#ibcon#about to read 3, iclass 18, count 0 2006.239.07:20:17.08#ibcon#read 3, iclass 18, count 0 2006.239.07:20:17.08#ibcon#about to read 4, iclass 18, count 0 2006.239.07:20:17.08#ibcon#read 4, iclass 18, count 0 2006.239.07:20:17.08#ibcon#about to read 5, iclass 18, count 0 2006.239.07:20:17.08#ibcon#read 5, iclass 18, count 0 2006.239.07:20:17.08#ibcon#about to read 6, iclass 18, count 0 2006.239.07:20:17.08#ibcon#read 6, iclass 18, count 0 2006.239.07:20:17.08#ibcon#end of sib2, iclass 18, count 0 2006.239.07:20:17.08#ibcon#*after write, iclass 18, count 0 2006.239.07:20:17.08#ibcon#*before return 0, iclass 18, count 0 2006.239.07:20:17.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:17.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:17.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:20:17.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:20:17.08$vc4f8/valo=5,652.99 2006.239.07:20:17.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:20:17.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:20:17.08#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:17.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:17.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:17.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:17.08#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:20:17.08#ibcon#first serial, iclass 20, count 0 2006.239.07:20:17.08#ibcon#enter sib2, iclass 20, count 0 2006.239.07:20:17.08#ibcon#flushed, iclass 20, count 0 2006.239.07:20:17.08#ibcon#about to write, iclass 20, count 0 2006.239.07:20:17.08#ibcon#wrote, iclass 20, count 0 2006.239.07:20:17.08#ibcon#about to read 3, iclass 20, count 0 2006.239.07:20:17.10#ibcon#read 3, iclass 20, count 0 2006.239.07:20:17.10#ibcon#about to read 4, iclass 20, count 0 2006.239.07:20:17.10#ibcon#read 4, iclass 20, count 0 2006.239.07:20:17.10#ibcon#about to read 5, iclass 20, count 0 2006.239.07:20:17.10#ibcon#read 5, iclass 20, count 0 2006.239.07:20:17.10#ibcon#about to read 6, iclass 20, count 0 2006.239.07:20:17.10#ibcon#read 6, iclass 20, count 0 2006.239.07:20:17.10#ibcon#end of sib2, iclass 20, count 0 2006.239.07:20:17.10#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:20:17.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:20:17.10#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:20:17.10#ibcon#*before write, iclass 20, count 0 2006.239.07:20:17.10#ibcon#enter sib2, iclass 20, count 0 2006.239.07:20:17.10#ibcon#flushed, iclass 20, count 0 2006.239.07:20:17.10#ibcon#about to write, iclass 20, count 0 2006.239.07:20:17.10#ibcon#wrote, iclass 20, count 0 2006.239.07:20:17.10#ibcon#about to read 3, iclass 20, count 0 2006.239.07:20:17.14#ibcon#read 3, iclass 20, count 0 2006.239.07:20:17.14#ibcon#about to read 4, iclass 20, count 0 2006.239.07:20:17.14#ibcon#read 4, iclass 20, count 0 2006.239.07:20:17.14#ibcon#about to read 5, iclass 20, count 0 2006.239.07:20:17.14#ibcon#read 5, iclass 20, count 0 2006.239.07:20:17.14#ibcon#about to read 6, iclass 20, count 0 2006.239.07:20:17.14#ibcon#read 6, iclass 20, count 0 2006.239.07:20:17.14#ibcon#end of sib2, iclass 20, count 0 2006.239.07:20:17.14#ibcon#*after write, iclass 20, count 0 2006.239.07:20:17.14#ibcon#*before return 0, iclass 20, count 0 2006.239.07:20:17.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:17.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:17.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:20:17.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:20:17.14$vc4f8/va=5,8 2006.239.07:20:17.14#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:20:17.14#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:20:17.14#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:17.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:17.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:17.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:17.20#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:20:17.20#ibcon#first serial, iclass 22, count 2 2006.239.07:20:17.20#ibcon#enter sib2, iclass 22, count 2 2006.239.07:20:17.20#ibcon#flushed, iclass 22, count 2 2006.239.07:20:17.20#ibcon#about to write, iclass 22, count 2 2006.239.07:20:17.20#ibcon#wrote, iclass 22, count 2 2006.239.07:20:17.20#ibcon#about to read 3, iclass 22, count 2 2006.239.07:20:17.22#ibcon#read 3, iclass 22, count 2 2006.239.07:20:17.22#ibcon#about to read 4, iclass 22, count 2 2006.239.07:20:17.22#ibcon#read 4, iclass 22, count 2 2006.239.07:20:17.22#ibcon#about to read 5, iclass 22, count 2 2006.239.07:20:17.22#ibcon#read 5, iclass 22, count 2 2006.239.07:20:17.22#ibcon#about to read 6, iclass 22, count 2 2006.239.07:20:17.22#ibcon#read 6, iclass 22, count 2 2006.239.07:20:17.22#ibcon#end of sib2, iclass 22, count 2 2006.239.07:20:17.22#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:20:17.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:20:17.22#ibcon#[25=AT05-08\r\n] 2006.239.07:20:17.22#ibcon#*before write, iclass 22, count 2 2006.239.07:20:17.22#ibcon#enter sib2, iclass 22, count 2 2006.239.07:20:17.22#ibcon#flushed, iclass 22, count 2 2006.239.07:20:17.22#ibcon#about to write, iclass 22, count 2 2006.239.07:20:17.22#ibcon#wrote, iclass 22, count 2 2006.239.07:20:17.22#ibcon#about to read 3, iclass 22, count 2 2006.239.07:20:17.25#ibcon#read 3, iclass 22, count 2 2006.239.07:20:17.25#ibcon#about to read 4, iclass 22, count 2 2006.239.07:20:17.25#ibcon#read 4, iclass 22, count 2 2006.239.07:20:17.25#ibcon#about to read 5, iclass 22, count 2 2006.239.07:20:17.25#ibcon#read 5, iclass 22, count 2 2006.239.07:20:17.25#ibcon#about to read 6, iclass 22, count 2 2006.239.07:20:17.25#ibcon#read 6, iclass 22, count 2 2006.239.07:20:17.25#ibcon#end of sib2, iclass 22, count 2 2006.239.07:20:17.25#ibcon#*after write, iclass 22, count 2 2006.239.07:20:17.25#ibcon#*before return 0, iclass 22, count 2 2006.239.07:20:17.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:17.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:17.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:20:17.25#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:17.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:17.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:17.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:17.37#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:20:17.37#ibcon#first serial, iclass 22, count 0 2006.239.07:20:17.37#ibcon#enter sib2, iclass 22, count 0 2006.239.07:20:17.37#ibcon#flushed, iclass 22, count 0 2006.239.07:20:17.37#ibcon#about to write, iclass 22, count 0 2006.239.07:20:17.37#ibcon#wrote, iclass 22, count 0 2006.239.07:20:17.37#ibcon#about to read 3, iclass 22, count 0 2006.239.07:20:17.39#ibcon#read 3, iclass 22, count 0 2006.239.07:20:17.39#ibcon#about to read 4, iclass 22, count 0 2006.239.07:20:17.39#ibcon#read 4, iclass 22, count 0 2006.239.07:20:17.39#ibcon#about to read 5, iclass 22, count 0 2006.239.07:20:17.39#ibcon#read 5, iclass 22, count 0 2006.239.07:20:17.39#ibcon#about to read 6, iclass 22, count 0 2006.239.07:20:17.39#ibcon#read 6, iclass 22, count 0 2006.239.07:20:17.39#ibcon#end of sib2, iclass 22, count 0 2006.239.07:20:17.39#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:20:17.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:20:17.39#ibcon#[25=USB\r\n] 2006.239.07:20:17.39#ibcon#*before write, iclass 22, count 0 2006.239.07:20:17.39#ibcon#enter sib2, iclass 22, count 0 2006.239.07:20:17.39#ibcon#flushed, iclass 22, count 0 2006.239.07:20:17.39#ibcon#about to write, iclass 22, count 0 2006.239.07:20:17.39#ibcon#wrote, iclass 22, count 0 2006.239.07:20:17.39#ibcon#about to read 3, iclass 22, count 0 2006.239.07:20:17.42#ibcon#read 3, iclass 22, count 0 2006.239.07:20:17.42#ibcon#about to read 4, iclass 22, count 0 2006.239.07:20:17.42#ibcon#read 4, iclass 22, count 0 2006.239.07:20:17.42#ibcon#about to read 5, iclass 22, count 0 2006.239.07:20:17.42#ibcon#read 5, iclass 22, count 0 2006.239.07:20:17.42#ibcon#about to read 6, iclass 22, count 0 2006.239.07:20:17.42#ibcon#read 6, iclass 22, count 0 2006.239.07:20:17.42#ibcon#end of sib2, iclass 22, count 0 2006.239.07:20:17.42#ibcon#*after write, iclass 22, count 0 2006.239.07:20:17.42#ibcon#*before return 0, iclass 22, count 0 2006.239.07:20:17.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:17.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:17.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:20:17.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:20:17.42$vc4f8/valo=6,772.99 2006.239.07:20:17.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:20:17.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:20:17.42#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:17.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:17.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:17.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:17.42#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:20:17.42#ibcon#first serial, iclass 24, count 0 2006.239.07:20:17.42#ibcon#enter sib2, iclass 24, count 0 2006.239.07:20:17.42#ibcon#flushed, iclass 24, count 0 2006.239.07:20:17.42#ibcon#about to write, iclass 24, count 0 2006.239.07:20:17.42#ibcon#wrote, iclass 24, count 0 2006.239.07:20:17.42#ibcon#about to read 3, iclass 24, count 0 2006.239.07:20:17.44#ibcon#read 3, iclass 24, count 0 2006.239.07:20:17.44#ibcon#about to read 4, iclass 24, count 0 2006.239.07:20:17.44#ibcon#read 4, iclass 24, count 0 2006.239.07:20:17.44#ibcon#about to read 5, iclass 24, count 0 2006.239.07:20:17.44#ibcon#read 5, iclass 24, count 0 2006.239.07:20:17.44#ibcon#about to read 6, iclass 24, count 0 2006.239.07:20:17.44#ibcon#read 6, iclass 24, count 0 2006.239.07:20:17.44#ibcon#end of sib2, iclass 24, count 0 2006.239.07:20:17.44#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:20:17.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:20:17.44#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:20:17.44#ibcon#*before write, iclass 24, count 0 2006.239.07:20:17.44#ibcon#enter sib2, iclass 24, count 0 2006.239.07:20:17.44#ibcon#flushed, iclass 24, count 0 2006.239.07:20:17.44#ibcon#about to write, iclass 24, count 0 2006.239.07:20:17.44#ibcon#wrote, iclass 24, count 0 2006.239.07:20:17.44#ibcon#about to read 3, iclass 24, count 0 2006.239.07:20:17.48#ibcon#read 3, iclass 24, count 0 2006.239.07:20:17.48#ibcon#about to read 4, iclass 24, count 0 2006.239.07:20:17.48#ibcon#read 4, iclass 24, count 0 2006.239.07:20:17.48#ibcon#about to read 5, iclass 24, count 0 2006.239.07:20:17.48#ibcon#read 5, iclass 24, count 0 2006.239.07:20:17.48#ibcon#about to read 6, iclass 24, count 0 2006.239.07:20:17.48#ibcon#read 6, iclass 24, count 0 2006.239.07:20:17.48#ibcon#end of sib2, iclass 24, count 0 2006.239.07:20:17.48#ibcon#*after write, iclass 24, count 0 2006.239.07:20:17.48#ibcon#*before return 0, iclass 24, count 0 2006.239.07:20:17.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:17.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:17.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:20:17.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:20:17.48$vc4f8/va=6,7 2006.239.07:20:17.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.07:20:17.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.07:20:17.48#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:17.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:20:17.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:20:17.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:20:17.54#ibcon#enter wrdev, iclass 26, count 2 2006.239.07:20:17.54#ibcon#first serial, iclass 26, count 2 2006.239.07:20:17.54#ibcon#enter sib2, iclass 26, count 2 2006.239.07:20:17.54#ibcon#flushed, iclass 26, count 2 2006.239.07:20:17.54#ibcon#about to write, iclass 26, count 2 2006.239.07:20:17.54#ibcon#wrote, iclass 26, count 2 2006.239.07:20:17.54#ibcon#about to read 3, iclass 26, count 2 2006.239.07:20:17.56#ibcon#read 3, iclass 26, count 2 2006.239.07:20:17.56#ibcon#about to read 4, iclass 26, count 2 2006.239.07:20:17.56#ibcon#read 4, iclass 26, count 2 2006.239.07:20:17.56#ibcon#about to read 5, iclass 26, count 2 2006.239.07:20:17.56#ibcon#read 5, iclass 26, count 2 2006.239.07:20:17.56#ibcon#about to read 6, iclass 26, count 2 2006.239.07:20:17.56#ibcon#read 6, iclass 26, count 2 2006.239.07:20:17.56#ibcon#end of sib2, iclass 26, count 2 2006.239.07:20:17.56#ibcon#*mode == 0, iclass 26, count 2 2006.239.07:20:17.56#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.07:20:17.56#ibcon#[25=AT06-07\r\n] 2006.239.07:20:17.56#ibcon#*before write, iclass 26, count 2 2006.239.07:20:17.56#ibcon#enter sib2, iclass 26, count 2 2006.239.07:20:17.56#ibcon#flushed, iclass 26, count 2 2006.239.07:20:17.56#ibcon#about to write, iclass 26, count 2 2006.239.07:20:17.56#ibcon#wrote, iclass 26, count 2 2006.239.07:20:17.56#ibcon#about to read 3, iclass 26, count 2 2006.239.07:20:17.59#ibcon#read 3, iclass 26, count 2 2006.239.07:20:17.59#ibcon#about to read 4, iclass 26, count 2 2006.239.07:20:17.59#ibcon#read 4, iclass 26, count 2 2006.239.07:20:17.59#ibcon#about to read 5, iclass 26, count 2 2006.239.07:20:17.59#ibcon#read 5, iclass 26, count 2 2006.239.07:20:17.59#ibcon#about to read 6, iclass 26, count 2 2006.239.07:20:17.59#ibcon#read 6, iclass 26, count 2 2006.239.07:20:17.59#ibcon#end of sib2, iclass 26, count 2 2006.239.07:20:17.59#ibcon#*after write, iclass 26, count 2 2006.239.07:20:17.59#ibcon#*before return 0, iclass 26, count 2 2006.239.07:20:17.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:20:17.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:20:17.59#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.07:20:17.59#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:17.59#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:20:17.71#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:20:17.71#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:20:17.71#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:20:17.71#ibcon#first serial, iclass 26, count 0 2006.239.07:20:17.71#ibcon#enter sib2, iclass 26, count 0 2006.239.07:20:17.71#ibcon#flushed, iclass 26, count 0 2006.239.07:20:17.71#ibcon#about to write, iclass 26, count 0 2006.239.07:20:17.71#ibcon#wrote, iclass 26, count 0 2006.239.07:20:17.71#ibcon#about to read 3, iclass 26, count 0 2006.239.07:20:17.73#ibcon#read 3, iclass 26, count 0 2006.239.07:20:17.73#ibcon#about to read 4, iclass 26, count 0 2006.239.07:20:17.73#ibcon#read 4, iclass 26, count 0 2006.239.07:20:17.73#ibcon#about to read 5, iclass 26, count 0 2006.239.07:20:17.73#ibcon#read 5, iclass 26, count 0 2006.239.07:20:17.73#ibcon#about to read 6, iclass 26, count 0 2006.239.07:20:17.73#ibcon#read 6, iclass 26, count 0 2006.239.07:20:17.73#ibcon#end of sib2, iclass 26, count 0 2006.239.07:20:17.73#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:20:17.73#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:20:17.73#ibcon#[25=USB\r\n] 2006.239.07:20:17.73#ibcon#*before write, iclass 26, count 0 2006.239.07:20:17.73#ibcon#enter sib2, iclass 26, count 0 2006.239.07:20:17.73#ibcon#flushed, iclass 26, count 0 2006.239.07:20:17.73#ibcon#about to write, iclass 26, count 0 2006.239.07:20:17.73#ibcon#wrote, iclass 26, count 0 2006.239.07:20:17.73#ibcon#about to read 3, iclass 26, count 0 2006.239.07:20:17.76#ibcon#read 3, iclass 26, count 0 2006.239.07:20:17.76#ibcon#about to read 4, iclass 26, count 0 2006.239.07:20:17.76#ibcon#read 4, iclass 26, count 0 2006.239.07:20:17.76#ibcon#about to read 5, iclass 26, count 0 2006.239.07:20:17.76#ibcon#read 5, iclass 26, count 0 2006.239.07:20:17.76#ibcon#about to read 6, iclass 26, count 0 2006.239.07:20:17.76#ibcon#read 6, iclass 26, count 0 2006.239.07:20:17.76#ibcon#end of sib2, iclass 26, count 0 2006.239.07:20:17.76#ibcon#*after write, iclass 26, count 0 2006.239.07:20:17.76#ibcon#*before return 0, iclass 26, count 0 2006.239.07:20:17.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:20:17.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:20:17.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:20:17.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:20:17.76$vc4f8/valo=7,832.99 2006.239.07:20:17.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.07:20:17.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.07:20:17.76#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:17.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:20:17.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:20:17.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:20:17.76#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:20:17.76#ibcon#first serial, iclass 28, count 0 2006.239.07:20:17.76#ibcon#enter sib2, iclass 28, count 0 2006.239.07:20:17.76#ibcon#flushed, iclass 28, count 0 2006.239.07:20:17.76#ibcon#about to write, iclass 28, count 0 2006.239.07:20:17.76#ibcon#wrote, iclass 28, count 0 2006.239.07:20:17.76#ibcon#about to read 3, iclass 28, count 0 2006.239.07:20:17.78#ibcon#read 3, iclass 28, count 0 2006.239.07:20:17.78#ibcon#about to read 4, iclass 28, count 0 2006.239.07:20:17.78#ibcon#read 4, iclass 28, count 0 2006.239.07:20:17.78#ibcon#about to read 5, iclass 28, count 0 2006.239.07:20:17.78#ibcon#read 5, iclass 28, count 0 2006.239.07:20:17.78#ibcon#about to read 6, iclass 28, count 0 2006.239.07:20:17.78#ibcon#read 6, iclass 28, count 0 2006.239.07:20:17.78#ibcon#end of sib2, iclass 28, count 0 2006.239.07:20:17.78#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:20:17.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:20:17.78#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:20:17.78#ibcon#*before write, iclass 28, count 0 2006.239.07:20:17.78#ibcon#enter sib2, iclass 28, count 0 2006.239.07:20:17.78#ibcon#flushed, iclass 28, count 0 2006.239.07:20:17.78#ibcon#about to write, iclass 28, count 0 2006.239.07:20:17.78#ibcon#wrote, iclass 28, count 0 2006.239.07:20:17.78#ibcon#about to read 3, iclass 28, count 0 2006.239.07:20:17.83#ibcon#read 3, iclass 28, count 0 2006.239.07:20:17.83#ibcon#about to read 4, iclass 28, count 0 2006.239.07:20:17.83#ibcon#read 4, iclass 28, count 0 2006.239.07:20:17.83#ibcon#about to read 5, iclass 28, count 0 2006.239.07:20:17.83#ibcon#read 5, iclass 28, count 0 2006.239.07:20:17.83#ibcon#about to read 6, iclass 28, count 0 2006.239.07:20:17.83#ibcon#read 6, iclass 28, count 0 2006.239.07:20:17.83#ibcon#end of sib2, iclass 28, count 0 2006.239.07:20:17.83#ibcon#*after write, iclass 28, count 0 2006.239.07:20:17.83#ibcon#*before return 0, iclass 28, count 0 2006.239.07:20:17.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:20:17.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:20:17.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:20:17.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:20:17.83$vc4f8/va=7,7 2006.239.07:20:17.83#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.07:20:17.83#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.07:20:17.83#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:17.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:20:17.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:20:17.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:20:17.87#ibcon#enter wrdev, iclass 30, count 2 2006.239.07:20:17.87#ibcon#first serial, iclass 30, count 2 2006.239.07:20:17.87#ibcon#enter sib2, iclass 30, count 2 2006.239.07:20:17.87#ibcon#flushed, iclass 30, count 2 2006.239.07:20:17.87#ibcon#about to write, iclass 30, count 2 2006.239.07:20:17.87#ibcon#wrote, iclass 30, count 2 2006.239.07:20:17.87#ibcon#about to read 3, iclass 30, count 2 2006.239.07:20:17.89#ibcon#read 3, iclass 30, count 2 2006.239.07:20:17.89#ibcon#about to read 4, iclass 30, count 2 2006.239.07:20:17.89#ibcon#read 4, iclass 30, count 2 2006.239.07:20:17.89#ibcon#about to read 5, iclass 30, count 2 2006.239.07:20:17.89#ibcon#read 5, iclass 30, count 2 2006.239.07:20:17.89#ibcon#about to read 6, iclass 30, count 2 2006.239.07:20:17.89#ibcon#read 6, iclass 30, count 2 2006.239.07:20:17.89#ibcon#end of sib2, iclass 30, count 2 2006.239.07:20:17.89#ibcon#*mode == 0, iclass 30, count 2 2006.239.07:20:17.89#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.07:20:17.89#ibcon#[25=AT07-07\r\n] 2006.239.07:20:17.89#ibcon#*before write, iclass 30, count 2 2006.239.07:20:17.89#ibcon#enter sib2, iclass 30, count 2 2006.239.07:20:17.89#ibcon#flushed, iclass 30, count 2 2006.239.07:20:17.89#ibcon#about to write, iclass 30, count 2 2006.239.07:20:17.89#ibcon#wrote, iclass 30, count 2 2006.239.07:20:17.89#ibcon#about to read 3, iclass 30, count 2 2006.239.07:20:17.92#ibcon#read 3, iclass 30, count 2 2006.239.07:20:17.92#ibcon#about to read 4, iclass 30, count 2 2006.239.07:20:17.92#ibcon#read 4, iclass 30, count 2 2006.239.07:20:17.92#ibcon#about to read 5, iclass 30, count 2 2006.239.07:20:17.92#ibcon#read 5, iclass 30, count 2 2006.239.07:20:17.92#ibcon#about to read 6, iclass 30, count 2 2006.239.07:20:17.92#ibcon#read 6, iclass 30, count 2 2006.239.07:20:17.92#ibcon#end of sib2, iclass 30, count 2 2006.239.07:20:17.92#ibcon#*after write, iclass 30, count 2 2006.239.07:20:17.92#ibcon#*before return 0, iclass 30, count 2 2006.239.07:20:17.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:20:17.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:20:17.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.07:20:17.92#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:17.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:20:18.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:20:18.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:20:18.04#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:20:18.04#ibcon#first serial, iclass 30, count 0 2006.239.07:20:18.04#ibcon#enter sib2, iclass 30, count 0 2006.239.07:20:18.04#ibcon#flushed, iclass 30, count 0 2006.239.07:20:18.04#ibcon#about to write, iclass 30, count 0 2006.239.07:20:18.04#ibcon#wrote, iclass 30, count 0 2006.239.07:20:18.04#ibcon#about to read 3, iclass 30, count 0 2006.239.07:20:18.06#ibcon#read 3, iclass 30, count 0 2006.239.07:20:18.06#ibcon#about to read 4, iclass 30, count 0 2006.239.07:20:18.06#ibcon#read 4, iclass 30, count 0 2006.239.07:20:18.06#ibcon#about to read 5, iclass 30, count 0 2006.239.07:20:18.06#ibcon#read 5, iclass 30, count 0 2006.239.07:20:18.06#ibcon#about to read 6, iclass 30, count 0 2006.239.07:20:18.06#ibcon#read 6, iclass 30, count 0 2006.239.07:20:18.06#ibcon#end of sib2, iclass 30, count 0 2006.239.07:20:18.06#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:20:18.06#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:20:18.06#ibcon#[25=USB\r\n] 2006.239.07:20:18.06#ibcon#*before write, iclass 30, count 0 2006.239.07:20:18.06#ibcon#enter sib2, iclass 30, count 0 2006.239.07:20:18.06#ibcon#flushed, iclass 30, count 0 2006.239.07:20:18.06#ibcon#about to write, iclass 30, count 0 2006.239.07:20:18.06#ibcon#wrote, iclass 30, count 0 2006.239.07:20:18.06#ibcon#about to read 3, iclass 30, count 0 2006.239.07:20:18.09#ibcon#read 3, iclass 30, count 0 2006.239.07:20:18.09#ibcon#about to read 4, iclass 30, count 0 2006.239.07:20:18.09#ibcon#read 4, iclass 30, count 0 2006.239.07:20:18.09#ibcon#about to read 5, iclass 30, count 0 2006.239.07:20:18.09#ibcon#read 5, iclass 30, count 0 2006.239.07:20:18.09#ibcon#about to read 6, iclass 30, count 0 2006.239.07:20:18.09#ibcon#read 6, iclass 30, count 0 2006.239.07:20:18.09#ibcon#end of sib2, iclass 30, count 0 2006.239.07:20:18.09#ibcon#*after write, iclass 30, count 0 2006.239.07:20:18.09#ibcon#*before return 0, iclass 30, count 0 2006.239.07:20:18.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:20:18.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:20:18.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:20:18.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:20:18.09$vc4f8/valo=8,852.99 2006.239.07:20:18.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.07:20:18.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.07:20:18.09#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:18.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:20:18.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:20:18.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:20:18.09#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:20:18.09#ibcon#first serial, iclass 32, count 0 2006.239.07:20:18.09#ibcon#enter sib2, iclass 32, count 0 2006.239.07:20:18.09#ibcon#flushed, iclass 32, count 0 2006.239.07:20:18.09#ibcon#about to write, iclass 32, count 0 2006.239.07:20:18.09#ibcon#wrote, iclass 32, count 0 2006.239.07:20:18.09#ibcon#about to read 3, iclass 32, count 0 2006.239.07:20:18.11#ibcon#read 3, iclass 32, count 0 2006.239.07:20:18.11#ibcon#about to read 4, iclass 32, count 0 2006.239.07:20:18.11#ibcon#read 4, iclass 32, count 0 2006.239.07:20:18.11#ibcon#about to read 5, iclass 32, count 0 2006.239.07:20:18.11#ibcon#read 5, iclass 32, count 0 2006.239.07:20:18.11#ibcon#about to read 6, iclass 32, count 0 2006.239.07:20:18.11#ibcon#read 6, iclass 32, count 0 2006.239.07:20:18.11#ibcon#end of sib2, iclass 32, count 0 2006.239.07:20:18.11#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:20:18.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:20:18.11#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:20:18.11#ibcon#*before write, iclass 32, count 0 2006.239.07:20:18.11#ibcon#enter sib2, iclass 32, count 0 2006.239.07:20:18.11#ibcon#flushed, iclass 32, count 0 2006.239.07:20:18.11#ibcon#about to write, iclass 32, count 0 2006.239.07:20:18.11#ibcon#wrote, iclass 32, count 0 2006.239.07:20:18.11#ibcon#about to read 3, iclass 32, count 0 2006.239.07:20:18.15#ibcon#read 3, iclass 32, count 0 2006.239.07:20:18.15#ibcon#about to read 4, iclass 32, count 0 2006.239.07:20:18.15#ibcon#read 4, iclass 32, count 0 2006.239.07:20:18.15#ibcon#about to read 5, iclass 32, count 0 2006.239.07:20:18.15#ibcon#read 5, iclass 32, count 0 2006.239.07:20:18.15#ibcon#about to read 6, iclass 32, count 0 2006.239.07:20:18.15#ibcon#read 6, iclass 32, count 0 2006.239.07:20:18.15#ibcon#end of sib2, iclass 32, count 0 2006.239.07:20:18.15#ibcon#*after write, iclass 32, count 0 2006.239.07:20:18.15#ibcon#*before return 0, iclass 32, count 0 2006.239.07:20:18.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:20:18.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:20:18.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:20:18.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:20:18.15$vc4f8/va=8,7 2006.239.07:20:18.15#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.07:20:18.15#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.07:20:18.15#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:18.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:20:18.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:20:18.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:20:18.21#ibcon#enter wrdev, iclass 34, count 2 2006.239.07:20:18.21#ibcon#first serial, iclass 34, count 2 2006.239.07:20:18.21#ibcon#enter sib2, iclass 34, count 2 2006.239.07:20:18.21#ibcon#flushed, iclass 34, count 2 2006.239.07:20:18.21#ibcon#about to write, iclass 34, count 2 2006.239.07:20:18.21#ibcon#wrote, iclass 34, count 2 2006.239.07:20:18.21#ibcon#about to read 3, iclass 34, count 2 2006.239.07:20:18.23#ibcon#read 3, iclass 34, count 2 2006.239.07:20:18.23#ibcon#about to read 4, iclass 34, count 2 2006.239.07:20:18.23#ibcon#read 4, iclass 34, count 2 2006.239.07:20:18.23#ibcon#about to read 5, iclass 34, count 2 2006.239.07:20:18.23#ibcon#read 5, iclass 34, count 2 2006.239.07:20:18.23#ibcon#about to read 6, iclass 34, count 2 2006.239.07:20:18.23#ibcon#read 6, iclass 34, count 2 2006.239.07:20:18.23#ibcon#end of sib2, iclass 34, count 2 2006.239.07:20:18.23#ibcon#*mode == 0, iclass 34, count 2 2006.239.07:20:18.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.07:20:18.23#ibcon#[25=AT08-07\r\n] 2006.239.07:20:18.23#ibcon#*before write, iclass 34, count 2 2006.239.07:20:18.23#ibcon#enter sib2, iclass 34, count 2 2006.239.07:20:18.23#ibcon#flushed, iclass 34, count 2 2006.239.07:20:18.23#ibcon#about to write, iclass 34, count 2 2006.239.07:20:18.23#ibcon#wrote, iclass 34, count 2 2006.239.07:20:18.23#ibcon#about to read 3, iclass 34, count 2 2006.239.07:20:18.26#ibcon#read 3, iclass 34, count 2 2006.239.07:20:18.26#ibcon#about to read 4, iclass 34, count 2 2006.239.07:20:18.26#ibcon#read 4, iclass 34, count 2 2006.239.07:20:18.26#ibcon#about to read 5, iclass 34, count 2 2006.239.07:20:18.26#ibcon#read 5, iclass 34, count 2 2006.239.07:20:18.26#ibcon#about to read 6, iclass 34, count 2 2006.239.07:20:18.26#ibcon#read 6, iclass 34, count 2 2006.239.07:20:18.26#ibcon#end of sib2, iclass 34, count 2 2006.239.07:20:18.26#ibcon#*after write, iclass 34, count 2 2006.239.07:20:18.26#ibcon#*before return 0, iclass 34, count 2 2006.239.07:20:18.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:20:18.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:20:18.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.07:20:18.26#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:18.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:20:18.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:20:18.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:20:18.38#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:20:18.38#ibcon#first serial, iclass 34, count 0 2006.239.07:20:18.38#ibcon#enter sib2, iclass 34, count 0 2006.239.07:20:18.38#ibcon#flushed, iclass 34, count 0 2006.239.07:20:18.38#ibcon#about to write, iclass 34, count 0 2006.239.07:20:18.38#ibcon#wrote, iclass 34, count 0 2006.239.07:20:18.38#ibcon#about to read 3, iclass 34, count 0 2006.239.07:20:18.40#ibcon#read 3, iclass 34, count 0 2006.239.07:20:18.40#ibcon#about to read 4, iclass 34, count 0 2006.239.07:20:18.40#ibcon#read 4, iclass 34, count 0 2006.239.07:20:18.40#ibcon#about to read 5, iclass 34, count 0 2006.239.07:20:18.40#ibcon#read 5, iclass 34, count 0 2006.239.07:20:18.40#ibcon#about to read 6, iclass 34, count 0 2006.239.07:20:18.40#ibcon#read 6, iclass 34, count 0 2006.239.07:20:18.40#ibcon#end of sib2, iclass 34, count 0 2006.239.07:20:18.40#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:20:18.40#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:20:18.40#ibcon#[25=USB\r\n] 2006.239.07:20:18.40#ibcon#*before write, iclass 34, count 0 2006.239.07:20:18.40#ibcon#enter sib2, iclass 34, count 0 2006.239.07:20:18.40#ibcon#flushed, iclass 34, count 0 2006.239.07:20:18.40#ibcon#about to write, iclass 34, count 0 2006.239.07:20:18.40#ibcon#wrote, iclass 34, count 0 2006.239.07:20:18.40#ibcon#about to read 3, iclass 34, count 0 2006.239.07:20:18.43#ibcon#read 3, iclass 34, count 0 2006.239.07:20:18.43#ibcon#about to read 4, iclass 34, count 0 2006.239.07:20:18.43#ibcon#read 4, iclass 34, count 0 2006.239.07:20:18.43#ibcon#about to read 5, iclass 34, count 0 2006.239.07:20:18.43#ibcon#read 5, iclass 34, count 0 2006.239.07:20:18.43#ibcon#about to read 6, iclass 34, count 0 2006.239.07:20:18.43#ibcon#read 6, iclass 34, count 0 2006.239.07:20:18.43#ibcon#end of sib2, iclass 34, count 0 2006.239.07:20:18.43#ibcon#*after write, iclass 34, count 0 2006.239.07:20:18.43#ibcon#*before return 0, iclass 34, count 0 2006.239.07:20:18.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:20:18.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:20:18.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:20:18.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:20:18.43$vc4f8/vblo=1,632.99 2006.239.07:20:18.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.07:20:18.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.07:20:18.43#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:18.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:20:18.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:20:18.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:20:18.43#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:20:18.43#ibcon#first serial, iclass 36, count 0 2006.239.07:20:18.43#ibcon#enter sib2, iclass 36, count 0 2006.239.07:20:18.43#ibcon#flushed, iclass 36, count 0 2006.239.07:20:18.43#ibcon#about to write, iclass 36, count 0 2006.239.07:20:18.43#ibcon#wrote, iclass 36, count 0 2006.239.07:20:18.43#ibcon#about to read 3, iclass 36, count 0 2006.239.07:20:18.45#ibcon#read 3, iclass 36, count 0 2006.239.07:20:18.45#ibcon#about to read 4, iclass 36, count 0 2006.239.07:20:18.45#ibcon#read 4, iclass 36, count 0 2006.239.07:20:18.45#ibcon#about to read 5, iclass 36, count 0 2006.239.07:20:18.45#ibcon#read 5, iclass 36, count 0 2006.239.07:20:18.45#ibcon#about to read 6, iclass 36, count 0 2006.239.07:20:18.45#ibcon#read 6, iclass 36, count 0 2006.239.07:20:18.45#ibcon#end of sib2, iclass 36, count 0 2006.239.07:20:18.45#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:20:18.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:20:18.45#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:20:18.45#ibcon#*before write, iclass 36, count 0 2006.239.07:20:18.45#ibcon#enter sib2, iclass 36, count 0 2006.239.07:20:18.45#ibcon#flushed, iclass 36, count 0 2006.239.07:20:18.45#ibcon#about to write, iclass 36, count 0 2006.239.07:20:18.45#ibcon#wrote, iclass 36, count 0 2006.239.07:20:18.45#ibcon#about to read 3, iclass 36, count 0 2006.239.07:20:18.49#ibcon#read 3, iclass 36, count 0 2006.239.07:20:18.49#ibcon#about to read 4, iclass 36, count 0 2006.239.07:20:18.49#ibcon#read 4, iclass 36, count 0 2006.239.07:20:18.49#ibcon#about to read 5, iclass 36, count 0 2006.239.07:20:18.49#ibcon#read 5, iclass 36, count 0 2006.239.07:20:18.49#ibcon#about to read 6, iclass 36, count 0 2006.239.07:20:18.49#ibcon#read 6, iclass 36, count 0 2006.239.07:20:18.49#ibcon#end of sib2, iclass 36, count 0 2006.239.07:20:18.49#ibcon#*after write, iclass 36, count 0 2006.239.07:20:18.49#ibcon#*before return 0, iclass 36, count 0 2006.239.07:20:18.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:20:18.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:20:18.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:20:18.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:20:18.49$vc4f8/vb=1,4 2006.239.07:20:18.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.07:20:18.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.07:20:18.49#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:18.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:20:18.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:20:18.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:20:18.49#ibcon#enter wrdev, iclass 38, count 2 2006.239.07:20:18.49#ibcon#first serial, iclass 38, count 2 2006.239.07:20:18.49#ibcon#enter sib2, iclass 38, count 2 2006.239.07:20:18.49#ibcon#flushed, iclass 38, count 2 2006.239.07:20:18.49#ibcon#about to write, iclass 38, count 2 2006.239.07:20:18.49#ibcon#wrote, iclass 38, count 2 2006.239.07:20:18.49#ibcon#about to read 3, iclass 38, count 2 2006.239.07:20:18.51#ibcon#read 3, iclass 38, count 2 2006.239.07:20:18.51#ibcon#about to read 4, iclass 38, count 2 2006.239.07:20:18.51#ibcon#read 4, iclass 38, count 2 2006.239.07:20:18.51#ibcon#about to read 5, iclass 38, count 2 2006.239.07:20:18.51#ibcon#read 5, iclass 38, count 2 2006.239.07:20:18.51#ibcon#about to read 6, iclass 38, count 2 2006.239.07:20:18.51#ibcon#read 6, iclass 38, count 2 2006.239.07:20:18.51#ibcon#end of sib2, iclass 38, count 2 2006.239.07:20:18.51#ibcon#*mode == 0, iclass 38, count 2 2006.239.07:20:18.51#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.07:20:18.51#ibcon#[27=AT01-04\r\n] 2006.239.07:20:18.51#ibcon#*before write, iclass 38, count 2 2006.239.07:20:18.51#ibcon#enter sib2, iclass 38, count 2 2006.239.07:20:18.51#ibcon#flushed, iclass 38, count 2 2006.239.07:20:18.51#ibcon#about to write, iclass 38, count 2 2006.239.07:20:18.51#ibcon#wrote, iclass 38, count 2 2006.239.07:20:18.51#ibcon#about to read 3, iclass 38, count 2 2006.239.07:20:18.54#ibcon#read 3, iclass 38, count 2 2006.239.07:20:18.54#ibcon#about to read 4, iclass 38, count 2 2006.239.07:20:18.54#ibcon#read 4, iclass 38, count 2 2006.239.07:20:18.54#ibcon#about to read 5, iclass 38, count 2 2006.239.07:20:18.54#ibcon#read 5, iclass 38, count 2 2006.239.07:20:18.54#ibcon#about to read 6, iclass 38, count 2 2006.239.07:20:18.54#ibcon#read 6, iclass 38, count 2 2006.239.07:20:18.54#ibcon#end of sib2, iclass 38, count 2 2006.239.07:20:18.54#ibcon#*after write, iclass 38, count 2 2006.239.07:20:18.54#ibcon#*before return 0, iclass 38, count 2 2006.239.07:20:18.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:20:18.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:20:18.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.07:20:18.54#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:18.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:20:18.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:20:18.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:20:18.66#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:20:18.66#ibcon#first serial, iclass 38, count 0 2006.239.07:20:18.66#ibcon#enter sib2, iclass 38, count 0 2006.239.07:20:18.66#ibcon#flushed, iclass 38, count 0 2006.239.07:20:18.66#ibcon#about to write, iclass 38, count 0 2006.239.07:20:18.66#ibcon#wrote, iclass 38, count 0 2006.239.07:20:18.66#ibcon#about to read 3, iclass 38, count 0 2006.239.07:20:18.68#ibcon#read 3, iclass 38, count 0 2006.239.07:20:18.68#ibcon#about to read 4, iclass 38, count 0 2006.239.07:20:18.68#ibcon#read 4, iclass 38, count 0 2006.239.07:20:18.68#ibcon#about to read 5, iclass 38, count 0 2006.239.07:20:18.68#ibcon#read 5, iclass 38, count 0 2006.239.07:20:18.68#ibcon#about to read 6, iclass 38, count 0 2006.239.07:20:18.68#ibcon#read 6, iclass 38, count 0 2006.239.07:20:18.68#ibcon#end of sib2, iclass 38, count 0 2006.239.07:20:18.68#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:20:18.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:20:18.68#ibcon#[27=USB\r\n] 2006.239.07:20:18.68#ibcon#*before write, iclass 38, count 0 2006.239.07:20:18.68#ibcon#enter sib2, iclass 38, count 0 2006.239.07:20:18.68#ibcon#flushed, iclass 38, count 0 2006.239.07:20:18.68#ibcon#about to write, iclass 38, count 0 2006.239.07:20:18.68#ibcon#wrote, iclass 38, count 0 2006.239.07:20:18.68#ibcon#about to read 3, iclass 38, count 0 2006.239.07:20:18.71#ibcon#read 3, iclass 38, count 0 2006.239.07:20:18.71#ibcon#about to read 4, iclass 38, count 0 2006.239.07:20:18.71#ibcon#read 4, iclass 38, count 0 2006.239.07:20:18.71#ibcon#about to read 5, iclass 38, count 0 2006.239.07:20:18.71#ibcon#read 5, iclass 38, count 0 2006.239.07:20:18.71#ibcon#about to read 6, iclass 38, count 0 2006.239.07:20:18.71#ibcon#read 6, iclass 38, count 0 2006.239.07:20:18.71#ibcon#end of sib2, iclass 38, count 0 2006.239.07:20:18.71#ibcon#*after write, iclass 38, count 0 2006.239.07:20:18.71#ibcon#*before return 0, iclass 38, count 0 2006.239.07:20:18.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:20:18.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:20:18.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:20:18.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:20:18.71$vc4f8/vblo=2,640.99 2006.239.07:20:18.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:20:18.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:20:18.71#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:18.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:18.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:18.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:18.71#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:20:18.71#ibcon#first serial, iclass 40, count 0 2006.239.07:20:18.71#ibcon#enter sib2, iclass 40, count 0 2006.239.07:20:18.71#ibcon#flushed, iclass 40, count 0 2006.239.07:20:18.71#ibcon#about to write, iclass 40, count 0 2006.239.07:20:18.71#ibcon#wrote, iclass 40, count 0 2006.239.07:20:18.71#ibcon#about to read 3, iclass 40, count 0 2006.239.07:20:18.73#ibcon#read 3, iclass 40, count 0 2006.239.07:20:18.73#ibcon#about to read 4, iclass 40, count 0 2006.239.07:20:18.73#ibcon#read 4, iclass 40, count 0 2006.239.07:20:18.73#ibcon#about to read 5, iclass 40, count 0 2006.239.07:20:18.73#ibcon#read 5, iclass 40, count 0 2006.239.07:20:18.73#ibcon#about to read 6, iclass 40, count 0 2006.239.07:20:18.73#ibcon#read 6, iclass 40, count 0 2006.239.07:20:18.73#ibcon#end of sib2, iclass 40, count 0 2006.239.07:20:18.73#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:20:18.73#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:20:18.73#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:20:18.73#ibcon#*before write, iclass 40, count 0 2006.239.07:20:18.73#ibcon#enter sib2, iclass 40, count 0 2006.239.07:20:18.73#ibcon#flushed, iclass 40, count 0 2006.239.07:20:18.73#ibcon#about to write, iclass 40, count 0 2006.239.07:20:18.73#ibcon#wrote, iclass 40, count 0 2006.239.07:20:18.73#ibcon#about to read 3, iclass 40, count 0 2006.239.07:20:18.77#ibcon#read 3, iclass 40, count 0 2006.239.07:20:18.77#ibcon#about to read 4, iclass 40, count 0 2006.239.07:20:18.77#ibcon#read 4, iclass 40, count 0 2006.239.07:20:18.77#ibcon#about to read 5, iclass 40, count 0 2006.239.07:20:18.77#ibcon#read 5, iclass 40, count 0 2006.239.07:20:18.77#ibcon#about to read 6, iclass 40, count 0 2006.239.07:20:18.77#ibcon#read 6, iclass 40, count 0 2006.239.07:20:18.77#ibcon#end of sib2, iclass 40, count 0 2006.239.07:20:18.77#ibcon#*after write, iclass 40, count 0 2006.239.07:20:18.77#ibcon#*before return 0, iclass 40, count 0 2006.239.07:20:18.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:18.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:20:18.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:20:18.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:20:18.77$vc4f8/vb=2,4 2006.239.07:20:18.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:20:18.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:20:18.77#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:18.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:18.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:18.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:18.83#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:20:18.83#ibcon#first serial, iclass 4, count 2 2006.239.07:20:18.83#ibcon#enter sib2, iclass 4, count 2 2006.239.07:20:18.83#ibcon#flushed, iclass 4, count 2 2006.239.07:20:18.83#ibcon#about to write, iclass 4, count 2 2006.239.07:20:18.83#ibcon#wrote, iclass 4, count 2 2006.239.07:20:18.83#ibcon#about to read 3, iclass 4, count 2 2006.239.07:20:18.85#ibcon#read 3, iclass 4, count 2 2006.239.07:20:18.85#ibcon#about to read 4, iclass 4, count 2 2006.239.07:20:18.85#ibcon#read 4, iclass 4, count 2 2006.239.07:20:18.85#ibcon#about to read 5, iclass 4, count 2 2006.239.07:20:18.85#ibcon#read 5, iclass 4, count 2 2006.239.07:20:18.85#ibcon#about to read 6, iclass 4, count 2 2006.239.07:20:18.85#ibcon#read 6, iclass 4, count 2 2006.239.07:20:18.85#ibcon#end of sib2, iclass 4, count 2 2006.239.07:20:18.85#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:20:18.85#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:20:18.85#ibcon#[27=AT02-04\r\n] 2006.239.07:20:18.85#ibcon#*before write, iclass 4, count 2 2006.239.07:20:18.85#ibcon#enter sib2, iclass 4, count 2 2006.239.07:20:18.85#ibcon#flushed, iclass 4, count 2 2006.239.07:20:18.85#ibcon#about to write, iclass 4, count 2 2006.239.07:20:18.85#ibcon#wrote, iclass 4, count 2 2006.239.07:20:18.85#ibcon#about to read 3, iclass 4, count 2 2006.239.07:20:18.88#ibcon#read 3, iclass 4, count 2 2006.239.07:20:18.88#ibcon#about to read 4, iclass 4, count 2 2006.239.07:20:18.88#ibcon#read 4, iclass 4, count 2 2006.239.07:20:18.88#ibcon#about to read 5, iclass 4, count 2 2006.239.07:20:18.88#ibcon#read 5, iclass 4, count 2 2006.239.07:20:18.88#ibcon#about to read 6, iclass 4, count 2 2006.239.07:20:18.88#ibcon#read 6, iclass 4, count 2 2006.239.07:20:18.88#ibcon#end of sib2, iclass 4, count 2 2006.239.07:20:18.88#ibcon#*after write, iclass 4, count 2 2006.239.07:20:18.88#ibcon#*before return 0, iclass 4, count 2 2006.239.07:20:18.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:18.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:20:18.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:20:18.88#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:18.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:19.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:19.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:19.00#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:20:19.00#ibcon#first serial, iclass 4, count 0 2006.239.07:20:19.00#ibcon#enter sib2, iclass 4, count 0 2006.239.07:20:19.00#ibcon#flushed, iclass 4, count 0 2006.239.07:20:19.00#ibcon#about to write, iclass 4, count 0 2006.239.07:20:19.00#ibcon#wrote, iclass 4, count 0 2006.239.07:20:19.00#ibcon#about to read 3, iclass 4, count 0 2006.239.07:20:19.02#ibcon#read 3, iclass 4, count 0 2006.239.07:20:19.02#ibcon#about to read 4, iclass 4, count 0 2006.239.07:20:19.02#ibcon#read 4, iclass 4, count 0 2006.239.07:20:19.02#ibcon#about to read 5, iclass 4, count 0 2006.239.07:20:19.02#ibcon#read 5, iclass 4, count 0 2006.239.07:20:19.02#ibcon#about to read 6, iclass 4, count 0 2006.239.07:20:19.02#ibcon#read 6, iclass 4, count 0 2006.239.07:20:19.02#ibcon#end of sib2, iclass 4, count 0 2006.239.07:20:19.02#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:20:19.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:20:19.02#ibcon#[27=USB\r\n] 2006.239.07:20:19.02#ibcon#*before write, iclass 4, count 0 2006.239.07:20:19.02#ibcon#enter sib2, iclass 4, count 0 2006.239.07:20:19.02#ibcon#flushed, iclass 4, count 0 2006.239.07:20:19.02#ibcon#about to write, iclass 4, count 0 2006.239.07:20:19.02#ibcon#wrote, iclass 4, count 0 2006.239.07:20:19.02#ibcon#about to read 3, iclass 4, count 0 2006.239.07:20:19.05#ibcon#read 3, iclass 4, count 0 2006.239.07:20:19.05#ibcon#about to read 4, iclass 4, count 0 2006.239.07:20:19.05#ibcon#read 4, iclass 4, count 0 2006.239.07:20:19.05#ibcon#about to read 5, iclass 4, count 0 2006.239.07:20:19.05#ibcon#read 5, iclass 4, count 0 2006.239.07:20:19.05#ibcon#about to read 6, iclass 4, count 0 2006.239.07:20:19.05#ibcon#read 6, iclass 4, count 0 2006.239.07:20:19.05#ibcon#end of sib2, iclass 4, count 0 2006.239.07:20:19.05#ibcon#*after write, iclass 4, count 0 2006.239.07:20:19.05#ibcon#*before return 0, iclass 4, count 0 2006.239.07:20:19.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:19.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:20:19.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:20:19.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:20:19.05$vc4f8/vblo=3,656.99 2006.239.07:20:19.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:20:19.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:20:19.05#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:19.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:19.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:19.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:19.05#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:20:19.05#ibcon#first serial, iclass 6, count 0 2006.239.07:20:19.05#ibcon#enter sib2, iclass 6, count 0 2006.239.07:20:19.05#ibcon#flushed, iclass 6, count 0 2006.239.07:20:19.05#ibcon#about to write, iclass 6, count 0 2006.239.07:20:19.05#ibcon#wrote, iclass 6, count 0 2006.239.07:20:19.05#ibcon#about to read 3, iclass 6, count 0 2006.239.07:20:19.07#ibcon#read 3, iclass 6, count 0 2006.239.07:20:19.07#ibcon#about to read 4, iclass 6, count 0 2006.239.07:20:19.07#ibcon#read 4, iclass 6, count 0 2006.239.07:20:19.07#ibcon#about to read 5, iclass 6, count 0 2006.239.07:20:19.07#ibcon#read 5, iclass 6, count 0 2006.239.07:20:19.07#ibcon#about to read 6, iclass 6, count 0 2006.239.07:20:19.07#ibcon#read 6, iclass 6, count 0 2006.239.07:20:19.07#ibcon#end of sib2, iclass 6, count 0 2006.239.07:20:19.07#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:20:19.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:20:19.07#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:20:19.07#ibcon#*before write, iclass 6, count 0 2006.239.07:20:19.07#ibcon#enter sib2, iclass 6, count 0 2006.239.07:20:19.07#ibcon#flushed, iclass 6, count 0 2006.239.07:20:19.07#ibcon#about to write, iclass 6, count 0 2006.239.07:20:19.07#ibcon#wrote, iclass 6, count 0 2006.239.07:20:19.07#ibcon#about to read 3, iclass 6, count 0 2006.239.07:20:19.11#ibcon#read 3, iclass 6, count 0 2006.239.07:20:19.11#ibcon#about to read 4, iclass 6, count 0 2006.239.07:20:19.11#ibcon#read 4, iclass 6, count 0 2006.239.07:20:19.11#ibcon#about to read 5, iclass 6, count 0 2006.239.07:20:19.11#ibcon#read 5, iclass 6, count 0 2006.239.07:20:19.11#ibcon#about to read 6, iclass 6, count 0 2006.239.07:20:19.11#ibcon#read 6, iclass 6, count 0 2006.239.07:20:19.11#ibcon#end of sib2, iclass 6, count 0 2006.239.07:20:19.11#ibcon#*after write, iclass 6, count 0 2006.239.07:20:19.11#ibcon#*before return 0, iclass 6, count 0 2006.239.07:20:19.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:19.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:20:19.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:20:19.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:20:19.11$vc4f8/vb=3,4 2006.239.07:20:19.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:20:19.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:20:19.11#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:19.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:19.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:19.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:19.17#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:20:19.17#ibcon#first serial, iclass 10, count 2 2006.239.07:20:19.17#ibcon#enter sib2, iclass 10, count 2 2006.239.07:20:19.17#ibcon#flushed, iclass 10, count 2 2006.239.07:20:19.17#ibcon#about to write, iclass 10, count 2 2006.239.07:20:19.17#ibcon#wrote, iclass 10, count 2 2006.239.07:20:19.17#ibcon#about to read 3, iclass 10, count 2 2006.239.07:20:19.19#ibcon#read 3, iclass 10, count 2 2006.239.07:20:19.19#ibcon#about to read 4, iclass 10, count 2 2006.239.07:20:19.19#ibcon#read 4, iclass 10, count 2 2006.239.07:20:19.19#ibcon#about to read 5, iclass 10, count 2 2006.239.07:20:19.19#ibcon#read 5, iclass 10, count 2 2006.239.07:20:19.19#ibcon#about to read 6, iclass 10, count 2 2006.239.07:20:19.19#ibcon#read 6, iclass 10, count 2 2006.239.07:20:19.19#ibcon#end of sib2, iclass 10, count 2 2006.239.07:20:19.19#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:20:19.19#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:20:19.19#ibcon#[27=AT03-04\r\n] 2006.239.07:20:19.19#ibcon#*before write, iclass 10, count 2 2006.239.07:20:19.19#ibcon#enter sib2, iclass 10, count 2 2006.239.07:20:19.19#ibcon#flushed, iclass 10, count 2 2006.239.07:20:19.19#ibcon#about to write, iclass 10, count 2 2006.239.07:20:19.19#ibcon#wrote, iclass 10, count 2 2006.239.07:20:19.19#ibcon#about to read 3, iclass 10, count 2 2006.239.07:20:19.22#ibcon#read 3, iclass 10, count 2 2006.239.07:20:19.22#ibcon#about to read 4, iclass 10, count 2 2006.239.07:20:19.22#ibcon#read 4, iclass 10, count 2 2006.239.07:20:19.22#ibcon#about to read 5, iclass 10, count 2 2006.239.07:20:19.22#ibcon#read 5, iclass 10, count 2 2006.239.07:20:19.22#ibcon#about to read 6, iclass 10, count 2 2006.239.07:20:19.22#ibcon#read 6, iclass 10, count 2 2006.239.07:20:19.22#ibcon#end of sib2, iclass 10, count 2 2006.239.07:20:19.22#ibcon#*after write, iclass 10, count 2 2006.239.07:20:19.22#ibcon#*before return 0, iclass 10, count 2 2006.239.07:20:19.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:19.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:20:19.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:20:19.22#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:19.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:19.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:19.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:19.34#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:20:19.34#ibcon#first serial, iclass 10, count 0 2006.239.07:20:19.34#ibcon#enter sib2, iclass 10, count 0 2006.239.07:20:19.34#ibcon#flushed, iclass 10, count 0 2006.239.07:20:19.34#ibcon#about to write, iclass 10, count 0 2006.239.07:20:19.34#ibcon#wrote, iclass 10, count 0 2006.239.07:20:19.34#ibcon#about to read 3, iclass 10, count 0 2006.239.07:20:19.36#ibcon#read 3, iclass 10, count 0 2006.239.07:20:19.36#ibcon#about to read 4, iclass 10, count 0 2006.239.07:20:19.36#ibcon#read 4, iclass 10, count 0 2006.239.07:20:19.36#ibcon#about to read 5, iclass 10, count 0 2006.239.07:20:19.36#ibcon#read 5, iclass 10, count 0 2006.239.07:20:19.36#ibcon#about to read 6, iclass 10, count 0 2006.239.07:20:19.36#ibcon#read 6, iclass 10, count 0 2006.239.07:20:19.36#ibcon#end of sib2, iclass 10, count 0 2006.239.07:20:19.36#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:20:19.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:20:19.36#ibcon#[27=USB\r\n] 2006.239.07:20:19.36#ibcon#*before write, iclass 10, count 0 2006.239.07:20:19.36#ibcon#enter sib2, iclass 10, count 0 2006.239.07:20:19.36#ibcon#flushed, iclass 10, count 0 2006.239.07:20:19.36#ibcon#about to write, iclass 10, count 0 2006.239.07:20:19.36#ibcon#wrote, iclass 10, count 0 2006.239.07:20:19.36#ibcon#about to read 3, iclass 10, count 0 2006.239.07:20:19.39#ibcon#read 3, iclass 10, count 0 2006.239.07:20:19.39#ibcon#about to read 4, iclass 10, count 0 2006.239.07:20:19.39#ibcon#read 4, iclass 10, count 0 2006.239.07:20:19.39#ibcon#about to read 5, iclass 10, count 0 2006.239.07:20:19.39#ibcon#read 5, iclass 10, count 0 2006.239.07:20:19.39#ibcon#about to read 6, iclass 10, count 0 2006.239.07:20:19.39#ibcon#read 6, iclass 10, count 0 2006.239.07:20:19.39#ibcon#end of sib2, iclass 10, count 0 2006.239.07:20:19.39#ibcon#*after write, iclass 10, count 0 2006.239.07:20:19.39#ibcon#*before return 0, iclass 10, count 0 2006.239.07:20:19.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:19.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:20:19.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:20:19.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:20:19.39$vc4f8/vblo=4,712.99 2006.239.07:20:19.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:20:19.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:20:19.39#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:19.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:19.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:19.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:19.39#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:20:19.39#ibcon#first serial, iclass 12, count 0 2006.239.07:20:19.39#ibcon#enter sib2, iclass 12, count 0 2006.239.07:20:19.39#ibcon#flushed, iclass 12, count 0 2006.239.07:20:19.39#ibcon#about to write, iclass 12, count 0 2006.239.07:20:19.39#ibcon#wrote, iclass 12, count 0 2006.239.07:20:19.39#ibcon#about to read 3, iclass 12, count 0 2006.239.07:20:19.41#ibcon#read 3, iclass 12, count 0 2006.239.07:20:19.41#ibcon#about to read 4, iclass 12, count 0 2006.239.07:20:19.41#ibcon#read 4, iclass 12, count 0 2006.239.07:20:19.41#ibcon#about to read 5, iclass 12, count 0 2006.239.07:20:19.41#ibcon#read 5, iclass 12, count 0 2006.239.07:20:19.41#ibcon#about to read 6, iclass 12, count 0 2006.239.07:20:19.41#ibcon#read 6, iclass 12, count 0 2006.239.07:20:19.41#ibcon#end of sib2, iclass 12, count 0 2006.239.07:20:19.41#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:20:19.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:20:19.41#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:20:19.41#ibcon#*before write, iclass 12, count 0 2006.239.07:20:19.41#ibcon#enter sib2, iclass 12, count 0 2006.239.07:20:19.41#ibcon#flushed, iclass 12, count 0 2006.239.07:20:19.41#ibcon#about to write, iclass 12, count 0 2006.239.07:20:19.41#ibcon#wrote, iclass 12, count 0 2006.239.07:20:19.41#ibcon#about to read 3, iclass 12, count 0 2006.239.07:20:19.45#ibcon#read 3, iclass 12, count 0 2006.239.07:20:19.45#ibcon#about to read 4, iclass 12, count 0 2006.239.07:20:19.45#ibcon#read 4, iclass 12, count 0 2006.239.07:20:19.45#ibcon#about to read 5, iclass 12, count 0 2006.239.07:20:19.45#ibcon#read 5, iclass 12, count 0 2006.239.07:20:19.45#ibcon#about to read 6, iclass 12, count 0 2006.239.07:20:19.45#ibcon#read 6, iclass 12, count 0 2006.239.07:20:19.45#ibcon#end of sib2, iclass 12, count 0 2006.239.07:20:19.45#ibcon#*after write, iclass 12, count 0 2006.239.07:20:19.45#ibcon#*before return 0, iclass 12, count 0 2006.239.07:20:19.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:19.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:20:19.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:20:19.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:20:19.45$vc4f8/vb=4,4 2006.239.07:20:19.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.07:20:19.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.07:20:19.45#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:19.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:19.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:19.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:19.51#ibcon#enter wrdev, iclass 14, count 2 2006.239.07:20:19.51#ibcon#first serial, iclass 14, count 2 2006.239.07:20:19.51#ibcon#enter sib2, iclass 14, count 2 2006.239.07:20:19.51#ibcon#flushed, iclass 14, count 2 2006.239.07:20:19.51#ibcon#about to write, iclass 14, count 2 2006.239.07:20:19.51#ibcon#wrote, iclass 14, count 2 2006.239.07:20:19.51#ibcon#about to read 3, iclass 14, count 2 2006.239.07:20:19.53#ibcon#read 3, iclass 14, count 2 2006.239.07:20:19.53#ibcon#about to read 4, iclass 14, count 2 2006.239.07:20:19.53#ibcon#read 4, iclass 14, count 2 2006.239.07:20:19.53#ibcon#about to read 5, iclass 14, count 2 2006.239.07:20:19.53#ibcon#read 5, iclass 14, count 2 2006.239.07:20:19.53#ibcon#about to read 6, iclass 14, count 2 2006.239.07:20:19.53#ibcon#read 6, iclass 14, count 2 2006.239.07:20:19.53#ibcon#end of sib2, iclass 14, count 2 2006.239.07:20:19.53#ibcon#*mode == 0, iclass 14, count 2 2006.239.07:20:19.53#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.07:20:19.53#ibcon#[27=AT04-04\r\n] 2006.239.07:20:19.53#ibcon#*before write, iclass 14, count 2 2006.239.07:20:19.53#ibcon#enter sib2, iclass 14, count 2 2006.239.07:20:19.53#ibcon#flushed, iclass 14, count 2 2006.239.07:20:19.53#ibcon#about to write, iclass 14, count 2 2006.239.07:20:19.53#ibcon#wrote, iclass 14, count 2 2006.239.07:20:19.53#ibcon#about to read 3, iclass 14, count 2 2006.239.07:20:19.56#ibcon#read 3, iclass 14, count 2 2006.239.07:20:19.56#ibcon#about to read 4, iclass 14, count 2 2006.239.07:20:19.56#ibcon#read 4, iclass 14, count 2 2006.239.07:20:19.56#ibcon#about to read 5, iclass 14, count 2 2006.239.07:20:19.56#ibcon#read 5, iclass 14, count 2 2006.239.07:20:19.56#ibcon#about to read 6, iclass 14, count 2 2006.239.07:20:19.56#ibcon#read 6, iclass 14, count 2 2006.239.07:20:19.56#ibcon#end of sib2, iclass 14, count 2 2006.239.07:20:19.56#ibcon#*after write, iclass 14, count 2 2006.239.07:20:19.56#ibcon#*before return 0, iclass 14, count 2 2006.239.07:20:19.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:19.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:20:19.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.07:20:19.56#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:19.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:19.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:19.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:19.68#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:20:19.68#ibcon#first serial, iclass 14, count 0 2006.239.07:20:19.68#ibcon#enter sib2, iclass 14, count 0 2006.239.07:20:19.68#ibcon#flushed, iclass 14, count 0 2006.239.07:20:19.68#ibcon#about to write, iclass 14, count 0 2006.239.07:20:19.68#ibcon#wrote, iclass 14, count 0 2006.239.07:20:19.68#ibcon#about to read 3, iclass 14, count 0 2006.239.07:20:19.70#ibcon#read 3, iclass 14, count 0 2006.239.07:20:19.70#ibcon#about to read 4, iclass 14, count 0 2006.239.07:20:19.70#ibcon#read 4, iclass 14, count 0 2006.239.07:20:19.70#ibcon#about to read 5, iclass 14, count 0 2006.239.07:20:19.70#ibcon#read 5, iclass 14, count 0 2006.239.07:20:19.70#ibcon#about to read 6, iclass 14, count 0 2006.239.07:20:19.70#ibcon#read 6, iclass 14, count 0 2006.239.07:20:19.70#ibcon#end of sib2, iclass 14, count 0 2006.239.07:20:19.70#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:20:19.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:20:19.70#ibcon#[27=USB\r\n] 2006.239.07:20:19.70#ibcon#*before write, iclass 14, count 0 2006.239.07:20:19.70#ibcon#enter sib2, iclass 14, count 0 2006.239.07:20:19.70#ibcon#flushed, iclass 14, count 0 2006.239.07:20:19.70#ibcon#about to write, iclass 14, count 0 2006.239.07:20:19.70#ibcon#wrote, iclass 14, count 0 2006.239.07:20:19.70#ibcon#about to read 3, iclass 14, count 0 2006.239.07:20:19.73#ibcon#read 3, iclass 14, count 0 2006.239.07:20:19.73#ibcon#about to read 4, iclass 14, count 0 2006.239.07:20:19.73#ibcon#read 4, iclass 14, count 0 2006.239.07:20:19.73#ibcon#about to read 5, iclass 14, count 0 2006.239.07:20:19.73#ibcon#read 5, iclass 14, count 0 2006.239.07:20:19.73#ibcon#about to read 6, iclass 14, count 0 2006.239.07:20:19.73#ibcon#read 6, iclass 14, count 0 2006.239.07:20:19.73#ibcon#end of sib2, iclass 14, count 0 2006.239.07:20:19.73#ibcon#*after write, iclass 14, count 0 2006.239.07:20:19.73#ibcon#*before return 0, iclass 14, count 0 2006.239.07:20:19.73#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:19.73#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:20:19.73#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:20:19.73#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:20:19.73$vc4f8/vblo=5,744.99 2006.239.07:20:19.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:20:19.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:20:19.73#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:19.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:19.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:19.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:19.73#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:20:19.73#ibcon#first serial, iclass 16, count 0 2006.239.07:20:19.73#ibcon#enter sib2, iclass 16, count 0 2006.239.07:20:19.73#ibcon#flushed, iclass 16, count 0 2006.239.07:20:19.73#ibcon#about to write, iclass 16, count 0 2006.239.07:20:19.73#ibcon#wrote, iclass 16, count 0 2006.239.07:20:19.73#ibcon#about to read 3, iclass 16, count 0 2006.239.07:20:19.75#ibcon#read 3, iclass 16, count 0 2006.239.07:20:19.75#ibcon#about to read 4, iclass 16, count 0 2006.239.07:20:19.75#ibcon#read 4, iclass 16, count 0 2006.239.07:20:19.75#ibcon#about to read 5, iclass 16, count 0 2006.239.07:20:19.75#ibcon#read 5, iclass 16, count 0 2006.239.07:20:19.75#ibcon#about to read 6, iclass 16, count 0 2006.239.07:20:19.75#ibcon#read 6, iclass 16, count 0 2006.239.07:20:19.75#ibcon#end of sib2, iclass 16, count 0 2006.239.07:20:19.75#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:20:19.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:20:19.75#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:20:19.75#ibcon#*before write, iclass 16, count 0 2006.239.07:20:19.75#ibcon#enter sib2, iclass 16, count 0 2006.239.07:20:19.75#ibcon#flushed, iclass 16, count 0 2006.239.07:20:19.75#ibcon#about to write, iclass 16, count 0 2006.239.07:20:19.75#ibcon#wrote, iclass 16, count 0 2006.239.07:20:19.75#ibcon#about to read 3, iclass 16, count 0 2006.239.07:20:19.79#ibcon#read 3, iclass 16, count 0 2006.239.07:20:19.79#ibcon#about to read 4, iclass 16, count 0 2006.239.07:20:19.79#ibcon#read 4, iclass 16, count 0 2006.239.07:20:19.79#ibcon#about to read 5, iclass 16, count 0 2006.239.07:20:19.79#ibcon#read 5, iclass 16, count 0 2006.239.07:20:19.79#ibcon#about to read 6, iclass 16, count 0 2006.239.07:20:19.79#ibcon#read 6, iclass 16, count 0 2006.239.07:20:19.79#ibcon#end of sib2, iclass 16, count 0 2006.239.07:20:19.79#ibcon#*after write, iclass 16, count 0 2006.239.07:20:19.79#ibcon#*before return 0, iclass 16, count 0 2006.239.07:20:19.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:19.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:20:19.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:20:19.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:20:19.79$vc4f8/vb=5,4 2006.239.07:20:19.79#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:20:19.79#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:20:19.79#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:19.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:19.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:19.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:19.85#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:20:19.85#ibcon#first serial, iclass 18, count 2 2006.239.07:20:19.85#ibcon#enter sib2, iclass 18, count 2 2006.239.07:20:19.85#ibcon#flushed, iclass 18, count 2 2006.239.07:20:19.85#ibcon#about to write, iclass 18, count 2 2006.239.07:20:19.85#ibcon#wrote, iclass 18, count 2 2006.239.07:20:19.85#ibcon#about to read 3, iclass 18, count 2 2006.239.07:20:19.87#ibcon#read 3, iclass 18, count 2 2006.239.07:20:19.87#ibcon#about to read 4, iclass 18, count 2 2006.239.07:20:19.87#ibcon#read 4, iclass 18, count 2 2006.239.07:20:19.87#ibcon#about to read 5, iclass 18, count 2 2006.239.07:20:19.87#ibcon#read 5, iclass 18, count 2 2006.239.07:20:19.87#ibcon#about to read 6, iclass 18, count 2 2006.239.07:20:19.87#ibcon#read 6, iclass 18, count 2 2006.239.07:20:19.87#ibcon#end of sib2, iclass 18, count 2 2006.239.07:20:19.87#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:20:19.87#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:20:19.87#ibcon#[27=AT05-04\r\n] 2006.239.07:20:19.87#ibcon#*before write, iclass 18, count 2 2006.239.07:20:19.87#ibcon#enter sib2, iclass 18, count 2 2006.239.07:20:19.87#ibcon#flushed, iclass 18, count 2 2006.239.07:20:19.87#ibcon#about to write, iclass 18, count 2 2006.239.07:20:19.87#ibcon#wrote, iclass 18, count 2 2006.239.07:20:19.87#ibcon#about to read 3, iclass 18, count 2 2006.239.07:20:19.90#ibcon#read 3, iclass 18, count 2 2006.239.07:20:19.90#ibcon#about to read 4, iclass 18, count 2 2006.239.07:20:19.90#ibcon#read 4, iclass 18, count 2 2006.239.07:20:19.90#ibcon#about to read 5, iclass 18, count 2 2006.239.07:20:19.90#ibcon#read 5, iclass 18, count 2 2006.239.07:20:19.90#ibcon#about to read 6, iclass 18, count 2 2006.239.07:20:19.90#ibcon#read 6, iclass 18, count 2 2006.239.07:20:19.90#ibcon#end of sib2, iclass 18, count 2 2006.239.07:20:19.90#ibcon#*after write, iclass 18, count 2 2006.239.07:20:19.90#ibcon#*before return 0, iclass 18, count 2 2006.239.07:20:19.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:19.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:20:19.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:20:19.90#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:19.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:20.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:20.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:20.02#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:20:20.02#ibcon#first serial, iclass 18, count 0 2006.239.07:20:20.02#ibcon#enter sib2, iclass 18, count 0 2006.239.07:20:20.02#ibcon#flushed, iclass 18, count 0 2006.239.07:20:20.02#ibcon#about to write, iclass 18, count 0 2006.239.07:20:20.02#ibcon#wrote, iclass 18, count 0 2006.239.07:20:20.02#ibcon#about to read 3, iclass 18, count 0 2006.239.07:20:20.04#ibcon#read 3, iclass 18, count 0 2006.239.07:20:20.04#ibcon#about to read 4, iclass 18, count 0 2006.239.07:20:20.04#ibcon#read 4, iclass 18, count 0 2006.239.07:20:20.04#ibcon#about to read 5, iclass 18, count 0 2006.239.07:20:20.04#ibcon#read 5, iclass 18, count 0 2006.239.07:20:20.04#ibcon#about to read 6, iclass 18, count 0 2006.239.07:20:20.04#ibcon#read 6, iclass 18, count 0 2006.239.07:20:20.04#ibcon#end of sib2, iclass 18, count 0 2006.239.07:20:20.04#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:20:20.04#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:20:20.04#ibcon#[27=USB\r\n] 2006.239.07:20:20.04#ibcon#*before write, iclass 18, count 0 2006.239.07:20:20.04#ibcon#enter sib2, iclass 18, count 0 2006.239.07:20:20.04#ibcon#flushed, iclass 18, count 0 2006.239.07:20:20.04#ibcon#about to write, iclass 18, count 0 2006.239.07:20:20.04#ibcon#wrote, iclass 18, count 0 2006.239.07:20:20.04#ibcon#about to read 3, iclass 18, count 0 2006.239.07:20:20.08#ibcon#read 3, iclass 18, count 0 2006.239.07:20:20.08#ibcon#about to read 4, iclass 18, count 0 2006.239.07:20:20.08#ibcon#read 4, iclass 18, count 0 2006.239.07:20:20.08#ibcon#about to read 5, iclass 18, count 0 2006.239.07:20:20.08#ibcon#read 5, iclass 18, count 0 2006.239.07:20:20.08#ibcon#about to read 6, iclass 18, count 0 2006.239.07:20:20.08#ibcon#read 6, iclass 18, count 0 2006.239.07:20:20.08#ibcon#end of sib2, iclass 18, count 0 2006.239.07:20:20.08#ibcon#*after write, iclass 18, count 0 2006.239.07:20:20.08#ibcon#*before return 0, iclass 18, count 0 2006.239.07:20:20.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:20.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:20:20.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:20:20.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:20:20.08$vc4f8/vblo=6,752.99 2006.239.07:20:20.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:20:20.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:20:20.08#ibcon#ireg 17 cls_cnt 0 2006.239.07:20:20.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:20.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:20.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:20.08#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:20:20.08#ibcon#first serial, iclass 20, count 0 2006.239.07:20:20.08#ibcon#enter sib2, iclass 20, count 0 2006.239.07:20:20.08#ibcon#flushed, iclass 20, count 0 2006.239.07:20:20.08#ibcon#about to write, iclass 20, count 0 2006.239.07:20:20.08#ibcon#wrote, iclass 20, count 0 2006.239.07:20:20.08#ibcon#about to read 3, iclass 20, count 0 2006.239.07:20:20.09#ibcon#read 3, iclass 20, count 0 2006.239.07:20:20.09#ibcon#about to read 4, iclass 20, count 0 2006.239.07:20:20.09#ibcon#read 4, iclass 20, count 0 2006.239.07:20:20.09#ibcon#about to read 5, iclass 20, count 0 2006.239.07:20:20.09#ibcon#read 5, iclass 20, count 0 2006.239.07:20:20.09#ibcon#about to read 6, iclass 20, count 0 2006.239.07:20:20.09#ibcon#read 6, iclass 20, count 0 2006.239.07:20:20.09#ibcon#end of sib2, iclass 20, count 0 2006.239.07:20:20.09#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:20:20.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:20:20.09#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:20:20.09#ibcon#*before write, iclass 20, count 0 2006.239.07:20:20.09#ibcon#enter sib2, iclass 20, count 0 2006.239.07:20:20.09#ibcon#flushed, iclass 20, count 0 2006.239.07:20:20.09#ibcon#about to write, iclass 20, count 0 2006.239.07:20:20.09#ibcon#wrote, iclass 20, count 0 2006.239.07:20:20.09#ibcon#about to read 3, iclass 20, count 0 2006.239.07:20:20.13#ibcon#read 3, iclass 20, count 0 2006.239.07:20:20.13#ibcon#about to read 4, iclass 20, count 0 2006.239.07:20:20.13#ibcon#read 4, iclass 20, count 0 2006.239.07:20:20.13#ibcon#about to read 5, iclass 20, count 0 2006.239.07:20:20.13#ibcon#read 5, iclass 20, count 0 2006.239.07:20:20.13#ibcon#about to read 6, iclass 20, count 0 2006.239.07:20:20.13#ibcon#read 6, iclass 20, count 0 2006.239.07:20:20.13#ibcon#end of sib2, iclass 20, count 0 2006.239.07:20:20.13#ibcon#*after write, iclass 20, count 0 2006.239.07:20:20.13#ibcon#*before return 0, iclass 20, count 0 2006.239.07:20:20.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:20.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:20:20.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:20:20.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:20:20.13$vc4f8/vb=6,4 2006.239.07:20:20.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:20:20.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:20:20.13#ibcon#ireg 11 cls_cnt 2 2006.239.07:20:20.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:20.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:20.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:20.20#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:20:20.20#ibcon#first serial, iclass 22, count 2 2006.239.07:20:20.20#ibcon#enter sib2, iclass 22, count 2 2006.239.07:20:20.20#ibcon#flushed, iclass 22, count 2 2006.239.07:20:20.20#ibcon#about to write, iclass 22, count 2 2006.239.07:20:20.20#ibcon#wrote, iclass 22, count 2 2006.239.07:20:20.20#ibcon#about to read 3, iclass 22, count 2 2006.239.07:20:20.22#ibcon#read 3, iclass 22, count 2 2006.239.07:20:20.22#ibcon#about to read 4, iclass 22, count 2 2006.239.07:20:20.22#ibcon#read 4, iclass 22, count 2 2006.239.07:20:20.22#ibcon#about to read 5, iclass 22, count 2 2006.239.07:20:20.22#ibcon#read 5, iclass 22, count 2 2006.239.07:20:20.22#ibcon#about to read 6, iclass 22, count 2 2006.239.07:20:20.22#ibcon#read 6, iclass 22, count 2 2006.239.07:20:20.22#ibcon#end of sib2, iclass 22, count 2 2006.239.07:20:20.22#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:20:20.22#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:20:20.22#ibcon#[27=AT06-04\r\n] 2006.239.07:20:20.22#ibcon#*before write, iclass 22, count 2 2006.239.07:20:20.22#ibcon#enter sib2, iclass 22, count 2 2006.239.07:20:20.22#ibcon#flushed, iclass 22, count 2 2006.239.07:20:20.22#ibcon#about to write, iclass 22, count 2 2006.239.07:20:20.22#ibcon#wrote, iclass 22, count 2 2006.239.07:20:20.22#ibcon#about to read 3, iclass 22, count 2 2006.239.07:20:20.25#ibcon#read 3, iclass 22, count 2 2006.239.07:20:20.25#ibcon#about to read 4, iclass 22, count 2 2006.239.07:20:20.25#ibcon#read 4, iclass 22, count 2 2006.239.07:20:20.25#ibcon#about to read 5, iclass 22, count 2 2006.239.07:20:20.25#ibcon#read 5, iclass 22, count 2 2006.239.07:20:20.25#ibcon#about to read 6, iclass 22, count 2 2006.239.07:20:20.25#ibcon#read 6, iclass 22, count 2 2006.239.07:20:20.25#ibcon#end of sib2, iclass 22, count 2 2006.239.07:20:20.25#ibcon#*after write, iclass 22, count 2 2006.239.07:20:20.25#ibcon#*before return 0, iclass 22, count 2 2006.239.07:20:20.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:20.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:20:20.25#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:20:20.25#ibcon#ireg 7 cls_cnt 0 2006.239.07:20:20.25#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:20.37#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:20.37#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:20.37#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:20:20.37#ibcon#first serial, iclass 22, count 0 2006.239.07:20:20.37#ibcon#enter sib2, iclass 22, count 0 2006.239.07:20:20.37#ibcon#flushed, iclass 22, count 0 2006.239.07:20:20.37#ibcon#about to write, iclass 22, count 0 2006.239.07:20:20.37#ibcon#wrote, iclass 22, count 0 2006.239.07:20:20.37#ibcon#about to read 3, iclass 22, count 0 2006.239.07:20:20.39#ibcon#read 3, iclass 22, count 0 2006.239.07:20:20.39#ibcon#about to read 4, iclass 22, count 0 2006.239.07:20:20.39#ibcon#read 4, iclass 22, count 0 2006.239.07:20:20.39#ibcon#about to read 5, iclass 22, count 0 2006.239.07:20:20.39#ibcon#read 5, iclass 22, count 0 2006.239.07:20:20.39#ibcon#about to read 6, iclass 22, count 0 2006.239.07:20:20.39#ibcon#read 6, iclass 22, count 0 2006.239.07:20:20.39#ibcon#end of sib2, iclass 22, count 0 2006.239.07:20:20.39#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:20:20.39#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:20:20.39#ibcon#[27=USB\r\n] 2006.239.07:20:20.39#ibcon#*before write, iclass 22, count 0 2006.239.07:20:20.39#ibcon#enter sib2, iclass 22, count 0 2006.239.07:20:20.39#ibcon#flushed, iclass 22, count 0 2006.239.07:20:20.39#ibcon#about to write, iclass 22, count 0 2006.239.07:20:20.39#ibcon#wrote, iclass 22, count 0 2006.239.07:20:20.39#ibcon#about to read 3, iclass 22, count 0 2006.239.07:20:20.42#ibcon#read 3, iclass 22, count 0 2006.239.07:20:20.42#ibcon#about to read 4, iclass 22, count 0 2006.239.07:20:20.42#ibcon#read 4, iclass 22, count 0 2006.239.07:20:20.42#ibcon#about to read 5, iclass 22, count 0 2006.239.07:20:20.42#ibcon#read 5, iclass 22, count 0 2006.239.07:20:20.42#ibcon#about to read 6, iclass 22, count 0 2006.239.07:20:20.42#ibcon#read 6, iclass 22, count 0 2006.239.07:20:20.42#ibcon#end of sib2, iclass 22, count 0 2006.239.07:20:20.42#ibcon#*after write, iclass 22, count 0 2006.239.07:20:20.42#ibcon#*before return 0, iclass 22, count 0 2006.239.07:20:20.42#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:20.42#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:20:20.42#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:20:20.42#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:20:20.42$vc4f8/vabw=wide 2006.239.07:20:20.42#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:20:20.42#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:20:20.42#ibcon#ireg 8 cls_cnt 0 2006.239.07:20:20.42#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:20.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:20.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:20.42#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:20:20.42#ibcon#first serial, iclass 24, count 0 2006.239.07:20:20.42#ibcon#enter sib2, iclass 24, count 0 2006.239.07:20:20.42#ibcon#flushed, iclass 24, count 0 2006.239.07:20:20.42#ibcon#about to write, iclass 24, count 0 2006.239.07:20:20.42#ibcon#wrote, iclass 24, count 0 2006.239.07:20:20.42#ibcon#about to read 3, iclass 24, count 0 2006.239.07:20:20.44#ibcon#read 3, iclass 24, count 0 2006.239.07:20:20.44#ibcon#about to read 4, iclass 24, count 0 2006.239.07:20:20.44#ibcon#read 4, iclass 24, count 0 2006.239.07:20:20.44#ibcon#about to read 5, iclass 24, count 0 2006.239.07:20:20.44#ibcon#read 5, iclass 24, count 0 2006.239.07:20:20.44#ibcon#about to read 6, iclass 24, count 0 2006.239.07:20:20.44#ibcon#read 6, iclass 24, count 0 2006.239.07:20:20.44#ibcon#end of sib2, iclass 24, count 0 2006.239.07:20:20.44#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:20:20.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:20:20.44#ibcon#[25=BW32\r\n] 2006.239.07:20:20.44#ibcon#*before write, iclass 24, count 0 2006.239.07:20:20.44#ibcon#enter sib2, iclass 24, count 0 2006.239.07:20:20.44#ibcon#flushed, iclass 24, count 0 2006.239.07:20:20.44#ibcon#about to write, iclass 24, count 0 2006.239.07:20:20.44#ibcon#wrote, iclass 24, count 0 2006.239.07:20:20.44#ibcon#about to read 3, iclass 24, count 0 2006.239.07:20:20.47#ibcon#read 3, iclass 24, count 0 2006.239.07:20:20.47#ibcon#about to read 4, iclass 24, count 0 2006.239.07:20:20.47#ibcon#read 4, iclass 24, count 0 2006.239.07:20:20.47#ibcon#about to read 5, iclass 24, count 0 2006.239.07:20:20.47#ibcon#read 5, iclass 24, count 0 2006.239.07:20:20.47#ibcon#about to read 6, iclass 24, count 0 2006.239.07:20:20.47#ibcon#read 6, iclass 24, count 0 2006.239.07:20:20.47#ibcon#end of sib2, iclass 24, count 0 2006.239.07:20:20.47#ibcon#*after write, iclass 24, count 0 2006.239.07:20:20.47#ibcon#*before return 0, iclass 24, count 0 2006.239.07:20:20.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:20.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:20:20.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:20:20.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:20:20.47$vc4f8/vbbw=wide 2006.239.07:20:20.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:20:20.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:20:20.47#ibcon#ireg 8 cls_cnt 0 2006.239.07:20:20.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:20:20.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:20:20.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:20:20.54#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:20:20.54#ibcon#first serial, iclass 26, count 0 2006.239.07:20:20.54#ibcon#enter sib2, iclass 26, count 0 2006.239.07:20:20.54#ibcon#flushed, iclass 26, count 0 2006.239.07:20:20.54#ibcon#about to write, iclass 26, count 0 2006.239.07:20:20.54#ibcon#wrote, iclass 26, count 0 2006.239.07:20:20.54#ibcon#about to read 3, iclass 26, count 0 2006.239.07:20:20.56#ibcon#read 3, iclass 26, count 0 2006.239.07:20:20.56#ibcon#about to read 4, iclass 26, count 0 2006.239.07:20:20.56#ibcon#read 4, iclass 26, count 0 2006.239.07:20:20.57#ibcon#about to read 5, iclass 26, count 0 2006.239.07:20:20.57#ibcon#read 5, iclass 26, count 0 2006.239.07:20:20.57#ibcon#about to read 6, iclass 26, count 0 2006.239.07:20:20.57#ibcon#read 6, iclass 26, count 0 2006.239.07:20:20.57#ibcon#end of sib2, iclass 26, count 0 2006.239.07:20:20.57#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:20:20.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:20:20.57#ibcon#[27=BW32\r\n] 2006.239.07:20:20.57#ibcon#*before write, iclass 26, count 0 2006.239.07:20:20.57#ibcon#enter sib2, iclass 26, count 0 2006.239.07:20:20.57#ibcon#flushed, iclass 26, count 0 2006.239.07:20:20.57#ibcon#about to write, iclass 26, count 0 2006.239.07:20:20.57#ibcon#wrote, iclass 26, count 0 2006.239.07:20:20.57#ibcon#about to read 3, iclass 26, count 0 2006.239.07:20:20.60#ibcon#read 3, iclass 26, count 0 2006.239.07:20:20.60#ibcon#about to read 4, iclass 26, count 0 2006.239.07:20:20.60#ibcon#read 4, iclass 26, count 0 2006.239.07:20:20.60#ibcon#about to read 5, iclass 26, count 0 2006.239.07:20:20.60#ibcon#read 5, iclass 26, count 0 2006.239.07:20:20.60#ibcon#about to read 6, iclass 26, count 0 2006.239.07:20:20.60#ibcon#read 6, iclass 26, count 0 2006.239.07:20:20.60#ibcon#end of sib2, iclass 26, count 0 2006.239.07:20:20.60#ibcon#*after write, iclass 26, count 0 2006.239.07:20:20.60#ibcon#*before return 0, iclass 26, count 0 2006.239.07:20:20.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:20:20.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:20:20.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:20:20.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:20:20.60$4f8m12a/ifd4f 2006.239.07:20:20.60&ifd4f/lo= 2006.239.07:20:20.60&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:20:20.60&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:20:20.60&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:20:20.60&ifd4f/patch= 2006.239.07:20:20.60&ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:20:20.60&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:20:20.60&ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:20:20.60$ifd4f/lo= 2006.239.07:20:20.60$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:20:20.60$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:20:20.60$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:20:20.60$ifd4f/patch= 2006.239.07:20:20.60$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:20:20.60$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:20:20.60$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:20:20.60$4f8m12a/"form=m,16.000,1:2 2006.239.07:20:20.60$4f8m12a/"tpicd 2006.239.07:20:20.60$4f8m12a/echo=off 2006.239.07:20:20.60$4f8m12a/xlog=off 2006.239.07:20:20.60:!2006.239.07:29:50 2006.239.07:20:34.14#trakl#Source acquired 2006.239.07:20:35.14#flagr#flagr/antenna,acquired 2006.239.07:29:50.00:preob 2006.239.07:29:50.00&preob/onsource 2006.239.07:29:51.14/onsource/TRACKING 2006.239.07:29:51.14:!2006.239.07:30:00 2006.239.07:30:00.00:data_valid=on 2006.239.07:30:00.00:midob 2006.239.07:30:00.00&midob/onsource 2006.239.07:30:00.00&midob/wx 2006.239.07:30:00.00&midob/cable 2006.239.07:30:00.00&midob/va 2006.239.07:30:00.00&midob/valo 2006.239.07:30:00.00&midob/vb 2006.239.07:30:00.00&midob/vblo 2006.239.07:30:00.00&midob/vabw 2006.239.07:30:00.00&midob/vbbw 2006.239.07:30:00.00&midob/"form 2006.239.07:30:00.00&midob/xfe 2006.239.07:30:00.00&midob/ifatt 2006.239.07:30:00.00&midob/clockoff 2006.239.07:30:00.00&midob/sy=logmail 2006.239.07:30:00.00&midob/"sy=run setcl adapt & 2006.239.07:30:00.14/onsource/TRACKING 2006.239.07:30:00.14/wx/25.41,1011.4,80 2006.239.07:30:00.35/cable/+6.4116E-03 2006.239.07:30:01.44/va/01,08,usb,yes,32,33 2006.239.07:30:01.44/va/02,07,usb,yes,31,33 2006.239.07:30:01.44/va/03,07,usb,yes,30,30 2006.239.07:30:01.44/va/04,07,usb,yes,33,36 2006.239.07:30:01.44/va/05,08,usb,yes,30,32 2006.239.07:30:01.44/va/06,07,usb,yes,33,33 2006.239.07:30:01.44/va/07,07,usb,yes,33,33 2006.239.07:30:01.44/va/08,07,usb,yes,36,35 2006.239.07:30:01.67/valo/01,532.99,yes,locked 2006.239.07:30:01.67/valo/02,572.99,yes,locked 2006.239.07:30:01.67/valo/03,672.99,yes,locked 2006.239.07:30:01.67/valo/04,832.99,yes,locked 2006.239.07:30:01.67/valo/05,652.99,yes,locked 2006.239.07:30:01.67/valo/06,772.99,yes,locked 2006.239.07:30:01.67/valo/07,832.99,yes,locked 2006.239.07:30:01.67/valo/08,852.99,yes,locked 2006.239.07:30:02.76/vb/01,04,usb,yes,31,30 2006.239.07:30:02.76/vb/02,04,usb,yes,33,35 2006.239.07:30:02.76/vb/03,04,usb,yes,29,33 2006.239.07:30:02.76/vb/04,04,usb,yes,30,30 2006.239.07:30:02.76/vb/05,04,usb,yes,28,33 2006.239.07:30:02.76/vb/06,04,usb,yes,29,32 2006.239.07:30:02.76/vb/07,04,usb,yes,32,32 2006.239.07:30:02.76/vb/08,04,usb,yes,29,33 2006.239.07:30:03.00/vblo/01,632.99,yes,locked 2006.239.07:30:03.00/vblo/02,640.99,yes,locked 2006.239.07:30:03.00/vblo/03,656.99,yes,locked 2006.239.07:30:03.00/vblo/04,712.99,yes,locked 2006.239.07:30:03.00/vblo/05,744.99,yes,locked 2006.239.07:30:03.00/vblo/06,752.99,yes,locked 2006.239.07:30:03.00/vblo/07,734.99,yes,locked 2006.239.07:30:03.00/vblo/08,744.99,yes,locked 2006.239.07:30:03.15/vabw/8 2006.239.07:30:03.30/vbbw/8 2006.239.07:30:03.39/xfe/off,on,13.2 2006.239.07:30:03.77/ifatt/23,28,28,28 2006.239.07:30:03.77&clockoff/"gps-fmout=1p 2006.239.07:30:03.77&clockoff/fmout-gps=1p 2006.239.07:30:04.08/fmout-gps/S +4.34E-07 2006.239.07:30:04.16:!2006.239.07:31:00 2006.239.07:31:00.00:data_valid=off 2006.239.07:31:00.00:postob 2006.239.07:31:00.00&postob/cable 2006.239.07:31:00.01&postob/wx 2006.239.07:31:00.01&postob/clockoff 2006.239.07:31:00.22/cable/+6.4121E-03 2006.239.07:31:00.22/wx/25.40,1011.4,80 2006.239.07:31:01.08/fmout-gps/S +4.34E-07 2006.239.07:31:01.08:scan_name=239-0733,k06239,60 2006.239.07:31:01.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.239.07:31:01.14#flagr#flagr/antenna,new-source 2006.239.07:31:02.14:checkk5 2006.239.07:31:02.14&checkk5/chk_autoobs=1 2006.239.07:31:02.14&checkk5/chk_autoobs=2 2006.239.07:31:02.15&checkk5/chk_autoobs=3 2006.239.07:31:02.15&checkk5/chk_autoobs=4 2006.239.07:31:02.16&checkk5/chk_obsdata=1 2006.239.07:31:02.16&checkk5/chk_obsdata=2 2006.239.07:31:02.16&checkk5/chk_obsdata=3 2006.239.07:31:02.17&checkk5/chk_obsdata=4 2006.239.07:31:02.17&checkk5/k5log=1 2006.239.07:31:02.18&checkk5/k5log=2 2006.239.07:31:02.20&checkk5/k5log=3 2006.239.07:31:02.20&checkk5/k5log=4 2006.239.07:31:02.20&checkk5/obsinfo 2006.239.07:31:02.58/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:31:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:31:03.34/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:31:03.72/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:31:04.10/chk_obsdata//k5ts1/T2390730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:31:04.48/chk_obsdata//k5ts2/T2390730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:31:04.85/chk_obsdata//k5ts3/T2390730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:31:05.22/chk_obsdata//k5ts4/T2390730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:31:05.93/k5log//k5ts1_log_newline 2006.239.07:31:06.64/k5log//k5ts2_log_newline 2006.239.07:31:07.32/k5log//k5ts3_log_newline 2006.239.07:31:08.01/k5log//k5ts4_log_newline 2006.239.07:31:08.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:31:08.04:4f8m12a=1 2006.239.07:31:08.04$4f8m12a/echo=on 2006.239.07:31:08.04$4f8m12a/pcalon 2006.239.07:31:08.04$pcalon/"no phase cal control is implemented here 2006.239.07:31:08.04$4f8m12a/"tpicd=stop 2006.239.07:31:08.04$4f8m12a/vc4f8 2006.239.07:31:08.04$vc4f8/valo=1,532.99 2006.239.07:31:08.04#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:31:08.04#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:31:08.04#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:08.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:08.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:08.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:08.04#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:31:08.04#ibcon#first serial, iclass 33, count 0 2006.239.07:31:08.04#ibcon#enter sib2, iclass 33, count 0 2006.239.07:31:08.04#ibcon#flushed, iclass 33, count 0 2006.239.07:31:08.04#ibcon#about to write, iclass 33, count 0 2006.239.07:31:08.04#ibcon#wrote, iclass 33, count 0 2006.239.07:31:08.04#ibcon#about to read 3, iclass 33, count 0 2006.239.07:31:08.08#ibcon#read 3, iclass 33, count 0 2006.239.07:31:08.08#ibcon#about to read 4, iclass 33, count 0 2006.239.07:31:08.08#ibcon#read 4, iclass 33, count 0 2006.239.07:31:08.08#ibcon#about to read 5, iclass 33, count 0 2006.239.07:31:08.08#ibcon#read 5, iclass 33, count 0 2006.239.07:31:08.08#ibcon#about to read 6, iclass 33, count 0 2006.239.07:31:08.08#ibcon#read 6, iclass 33, count 0 2006.239.07:31:08.08#ibcon#end of sib2, iclass 33, count 0 2006.239.07:31:08.08#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:31:08.08#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:31:08.08#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:31:08.08#ibcon#*before write, iclass 33, count 0 2006.239.07:31:08.08#ibcon#enter sib2, iclass 33, count 0 2006.239.07:31:08.08#ibcon#flushed, iclass 33, count 0 2006.239.07:31:08.08#ibcon#about to write, iclass 33, count 0 2006.239.07:31:08.08#ibcon#wrote, iclass 33, count 0 2006.239.07:31:08.08#ibcon#about to read 3, iclass 33, count 0 2006.239.07:31:08.13#ibcon#read 3, iclass 33, count 0 2006.239.07:31:08.13#ibcon#about to read 4, iclass 33, count 0 2006.239.07:31:08.13#ibcon#read 4, iclass 33, count 0 2006.239.07:31:08.13#ibcon#about to read 5, iclass 33, count 0 2006.239.07:31:08.13#ibcon#read 5, iclass 33, count 0 2006.239.07:31:08.13#ibcon#about to read 6, iclass 33, count 0 2006.239.07:31:08.13#ibcon#read 6, iclass 33, count 0 2006.239.07:31:08.13#ibcon#end of sib2, iclass 33, count 0 2006.239.07:31:08.13#ibcon#*after write, iclass 33, count 0 2006.239.07:31:08.13#ibcon#*before return 0, iclass 33, count 0 2006.239.07:31:08.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:08.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:08.13#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:31:08.13#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:31:08.13$vc4f8/va=1,8 2006.239.07:31:08.13#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:31:08.13#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:31:08.13#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:08.13#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:08.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:08.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:08.13#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:31:08.13#ibcon#first serial, iclass 35, count 2 2006.239.07:31:08.13#ibcon#enter sib2, iclass 35, count 2 2006.239.07:31:08.13#ibcon#flushed, iclass 35, count 2 2006.239.07:31:08.13#ibcon#about to write, iclass 35, count 2 2006.239.07:31:08.13#ibcon#wrote, iclass 35, count 2 2006.239.07:31:08.13#ibcon#about to read 3, iclass 35, count 2 2006.239.07:31:08.15#ibcon#read 3, iclass 35, count 2 2006.239.07:31:08.15#ibcon#about to read 4, iclass 35, count 2 2006.239.07:31:08.15#ibcon#read 4, iclass 35, count 2 2006.239.07:31:08.15#ibcon#about to read 5, iclass 35, count 2 2006.239.07:31:08.15#ibcon#read 5, iclass 35, count 2 2006.239.07:31:08.15#ibcon#about to read 6, iclass 35, count 2 2006.239.07:31:08.15#ibcon#read 6, iclass 35, count 2 2006.239.07:31:08.15#ibcon#end of sib2, iclass 35, count 2 2006.239.07:31:08.15#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:31:08.15#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:31:08.15#ibcon#[25=AT01-08\r\n] 2006.239.07:31:08.15#ibcon#*before write, iclass 35, count 2 2006.239.07:31:08.15#ibcon#enter sib2, iclass 35, count 2 2006.239.07:31:08.15#ibcon#flushed, iclass 35, count 2 2006.239.07:31:08.15#ibcon#about to write, iclass 35, count 2 2006.239.07:31:08.15#ibcon#wrote, iclass 35, count 2 2006.239.07:31:08.15#ibcon#about to read 3, iclass 35, count 2 2006.239.07:31:08.19#ibcon#read 3, iclass 35, count 2 2006.239.07:31:08.19#ibcon#about to read 4, iclass 35, count 2 2006.239.07:31:08.19#ibcon#read 4, iclass 35, count 2 2006.239.07:31:08.19#ibcon#about to read 5, iclass 35, count 2 2006.239.07:31:08.19#ibcon#read 5, iclass 35, count 2 2006.239.07:31:08.19#ibcon#about to read 6, iclass 35, count 2 2006.239.07:31:08.19#ibcon#read 6, iclass 35, count 2 2006.239.07:31:08.19#ibcon#end of sib2, iclass 35, count 2 2006.239.07:31:08.19#ibcon#*after write, iclass 35, count 2 2006.239.07:31:08.19#ibcon#*before return 0, iclass 35, count 2 2006.239.07:31:08.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:08.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:08.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:31:08.19#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:08.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:08.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:08.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:08.31#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:31:08.31#ibcon#first serial, iclass 35, count 0 2006.239.07:31:08.31#ibcon#enter sib2, iclass 35, count 0 2006.239.07:31:08.31#ibcon#flushed, iclass 35, count 0 2006.239.07:31:08.31#ibcon#about to write, iclass 35, count 0 2006.239.07:31:08.31#ibcon#wrote, iclass 35, count 0 2006.239.07:31:08.31#ibcon#about to read 3, iclass 35, count 0 2006.239.07:31:08.33#ibcon#read 3, iclass 35, count 0 2006.239.07:31:08.33#ibcon#about to read 4, iclass 35, count 0 2006.239.07:31:08.33#ibcon#read 4, iclass 35, count 0 2006.239.07:31:08.33#ibcon#about to read 5, iclass 35, count 0 2006.239.07:31:08.33#ibcon#read 5, iclass 35, count 0 2006.239.07:31:08.33#ibcon#about to read 6, iclass 35, count 0 2006.239.07:31:08.33#ibcon#read 6, iclass 35, count 0 2006.239.07:31:08.33#ibcon#end of sib2, iclass 35, count 0 2006.239.07:31:08.33#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:31:08.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:31:08.33#ibcon#[25=USB\r\n] 2006.239.07:31:08.33#ibcon#*before write, iclass 35, count 0 2006.239.07:31:08.33#ibcon#enter sib2, iclass 35, count 0 2006.239.07:31:08.33#ibcon#flushed, iclass 35, count 0 2006.239.07:31:08.33#ibcon#about to write, iclass 35, count 0 2006.239.07:31:08.33#ibcon#wrote, iclass 35, count 0 2006.239.07:31:08.33#ibcon#about to read 3, iclass 35, count 0 2006.239.07:31:08.36#ibcon#read 3, iclass 35, count 0 2006.239.07:31:08.36#ibcon#about to read 4, iclass 35, count 0 2006.239.07:31:08.36#ibcon#read 4, iclass 35, count 0 2006.239.07:31:08.36#ibcon#about to read 5, iclass 35, count 0 2006.239.07:31:08.36#ibcon#read 5, iclass 35, count 0 2006.239.07:31:08.36#ibcon#about to read 6, iclass 35, count 0 2006.239.07:31:08.36#ibcon#read 6, iclass 35, count 0 2006.239.07:31:08.36#ibcon#end of sib2, iclass 35, count 0 2006.239.07:31:08.36#ibcon#*after write, iclass 35, count 0 2006.239.07:31:08.36#ibcon#*before return 0, iclass 35, count 0 2006.239.07:31:08.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:08.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:08.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:31:08.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:31:08.36$vc4f8/valo=2,572.99 2006.239.07:31:08.36#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:31:08.36#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:31:08.36#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:08.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:08.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:08.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:08.36#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:31:08.36#ibcon#first serial, iclass 37, count 0 2006.239.07:31:08.36#ibcon#enter sib2, iclass 37, count 0 2006.239.07:31:08.36#ibcon#flushed, iclass 37, count 0 2006.239.07:31:08.36#ibcon#about to write, iclass 37, count 0 2006.239.07:31:08.36#ibcon#wrote, iclass 37, count 0 2006.239.07:31:08.36#ibcon#about to read 3, iclass 37, count 0 2006.239.07:31:08.38#ibcon#read 3, iclass 37, count 0 2006.239.07:31:08.38#ibcon#about to read 4, iclass 37, count 0 2006.239.07:31:08.38#ibcon#read 4, iclass 37, count 0 2006.239.07:31:08.38#ibcon#about to read 5, iclass 37, count 0 2006.239.07:31:08.38#ibcon#read 5, iclass 37, count 0 2006.239.07:31:08.38#ibcon#about to read 6, iclass 37, count 0 2006.239.07:31:08.38#ibcon#read 6, iclass 37, count 0 2006.239.07:31:08.38#ibcon#end of sib2, iclass 37, count 0 2006.239.07:31:08.38#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:31:08.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:31:08.38#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:31:08.38#ibcon#*before write, iclass 37, count 0 2006.239.07:31:08.38#ibcon#enter sib2, iclass 37, count 0 2006.239.07:31:08.38#ibcon#flushed, iclass 37, count 0 2006.239.07:31:08.38#ibcon#about to write, iclass 37, count 0 2006.239.07:31:08.38#ibcon#wrote, iclass 37, count 0 2006.239.07:31:08.38#ibcon#about to read 3, iclass 37, count 0 2006.239.07:31:08.42#ibcon#read 3, iclass 37, count 0 2006.239.07:31:08.42#ibcon#about to read 4, iclass 37, count 0 2006.239.07:31:08.42#ibcon#read 4, iclass 37, count 0 2006.239.07:31:08.42#ibcon#about to read 5, iclass 37, count 0 2006.239.07:31:08.42#ibcon#read 5, iclass 37, count 0 2006.239.07:31:08.42#ibcon#about to read 6, iclass 37, count 0 2006.239.07:31:08.42#ibcon#read 6, iclass 37, count 0 2006.239.07:31:08.42#ibcon#end of sib2, iclass 37, count 0 2006.239.07:31:08.42#ibcon#*after write, iclass 37, count 0 2006.239.07:31:08.42#ibcon#*before return 0, iclass 37, count 0 2006.239.07:31:08.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:08.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:08.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:31:08.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:31:08.42$vc4f8/va=2,7 2006.239.07:31:08.42#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:31:08.42#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:31:08.42#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:08.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:08.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:08.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:08.48#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:31:08.48#ibcon#first serial, iclass 39, count 2 2006.239.07:31:08.48#ibcon#enter sib2, iclass 39, count 2 2006.239.07:31:08.48#ibcon#flushed, iclass 39, count 2 2006.239.07:31:08.48#ibcon#about to write, iclass 39, count 2 2006.239.07:31:08.48#ibcon#wrote, iclass 39, count 2 2006.239.07:31:08.48#ibcon#about to read 3, iclass 39, count 2 2006.239.07:31:08.50#ibcon#read 3, iclass 39, count 2 2006.239.07:31:08.50#ibcon#about to read 4, iclass 39, count 2 2006.239.07:31:08.50#ibcon#read 4, iclass 39, count 2 2006.239.07:31:08.50#ibcon#about to read 5, iclass 39, count 2 2006.239.07:31:08.50#ibcon#read 5, iclass 39, count 2 2006.239.07:31:08.50#ibcon#about to read 6, iclass 39, count 2 2006.239.07:31:08.50#ibcon#read 6, iclass 39, count 2 2006.239.07:31:08.50#ibcon#end of sib2, iclass 39, count 2 2006.239.07:31:08.50#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:31:08.50#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:31:08.50#ibcon#[25=AT02-07\r\n] 2006.239.07:31:08.50#ibcon#*before write, iclass 39, count 2 2006.239.07:31:08.50#ibcon#enter sib2, iclass 39, count 2 2006.239.07:31:08.50#ibcon#flushed, iclass 39, count 2 2006.239.07:31:08.50#ibcon#about to write, iclass 39, count 2 2006.239.07:31:08.50#ibcon#wrote, iclass 39, count 2 2006.239.07:31:08.50#ibcon#about to read 3, iclass 39, count 2 2006.239.07:31:08.53#ibcon#read 3, iclass 39, count 2 2006.239.07:31:08.53#ibcon#about to read 4, iclass 39, count 2 2006.239.07:31:08.53#ibcon#read 4, iclass 39, count 2 2006.239.07:31:08.53#ibcon#about to read 5, iclass 39, count 2 2006.239.07:31:08.53#ibcon#read 5, iclass 39, count 2 2006.239.07:31:08.53#ibcon#about to read 6, iclass 39, count 2 2006.239.07:31:08.53#ibcon#read 6, iclass 39, count 2 2006.239.07:31:08.53#ibcon#end of sib2, iclass 39, count 2 2006.239.07:31:08.53#ibcon#*after write, iclass 39, count 2 2006.239.07:31:08.53#ibcon#*before return 0, iclass 39, count 2 2006.239.07:31:08.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:08.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:08.53#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:31:08.53#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:08.53#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:08.65#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:08.65#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:08.65#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:31:08.65#ibcon#first serial, iclass 39, count 0 2006.239.07:31:08.65#ibcon#enter sib2, iclass 39, count 0 2006.239.07:31:08.65#ibcon#flushed, iclass 39, count 0 2006.239.07:31:08.65#ibcon#about to write, iclass 39, count 0 2006.239.07:31:08.65#ibcon#wrote, iclass 39, count 0 2006.239.07:31:08.65#ibcon#about to read 3, iclass 39, count 0 2006.239.07:31:08.67#ibcon#read 3, iclass 39, count 0 2006.239.07:31:08.67#ibcon#about to read 4, iclass 39, count 0 2006.239.07:31:08.67#ibcon#read 4, iclass 39, count 0 2006.239.07:31:08.67#ibcon#about to read 5, iclass 39, count 0 2006.239.07:31:08.67#ibcon#read 5, iclass 39, count 0 2006.239.07:31:08.67#ibcon#about to read 6, iclass 39, count 0 2006.239.07:31:08.67#ibcon#read 6, iclass 39, count 0 2006.239.07:31:08.67#ibcon#end of sib2, iclass 39, count 0 2006.239.07:31:08.67#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:31:08.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:31:08.67#ibcon#[25=USB\r\n] 2006.239.07:31:08.67#ibcon#*before write, iclass 39, count 0 2006.239.07:31:08.67#ibcon#enter sib2, iclass 39, count 0 2006.239.07:31:08.67#ibcon#flushed, iclass 39, count 0 2006.239.07:31:08.67#ibcon#about to write, iclass 39, count 0 2006.239.07:31:08.67#ibcon#wrote, iclass 39, count 0 2006.239.07:31:08.67#ibcon#about to read 3, iclass 39, count 0 2006.239.07:31:08.70#ibcon#read 3, iclass 39, count 0 2006.239.07:31:08.70#ibcon#about to read 4, iclass 39, count 0 2006.239.07:31:08.70#ibcon#read 4, iclass 39, count 0 2006.239.07:31:08.70#ibcon#about to read 5, iclass 39, count 0 2006.239.07:31:08.70#ibcon#read 5, iclass 39, count 0 2006.239.07:31:08.70#ibcon#about to read 6, iclass 39, count 0 2006.239.07:31:08.70#ibcon#read 6, iclass 39, count 0 2006.239.07:31:08.70#ibcon#end of sib2, iclass 39, count 0 2006.239.07:31:08.70#ibcon#*after write, iclass 39, count 0 2006.239.07:31:08.70#ibcon#*before return 0, iclass 39, count 0 2006.239.07:31:08.70#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:08.70#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:08.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:31:08.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:31:08.70$vc4f8/valo=3,672.99 2006.239.07:31:08.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:31:08.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:31:08.70#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:08.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:08.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:08.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:08.70#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:31:08.70#ibcon#first serial, iclass 3, count 0 2006.239.07:31:08.70#ibcon#enter sib2, iclass 3, count 0 2006.239.07:31:08.70#ibcon#flushed, iclass 3, count 0 2006.239.07:31:08.70#ibcon#about to write, iclass 3, count 0 2006.239.07:31:08.70#ibcon#wrote, iclass 3, count 0 2006.239.07:31:08.70#ibcon#about to read 3, iclass 3, count 0 2006.239.07:31:08.72#ibcon#read 3, iclass 3, count 0 2006.239.07:31:08.72#ibcon#about to read 4, iclass 3, count 0 2006.239.07:31:08.72#ibcon#read 4, iclass 3, count 0 2006.239.07:31:08.72#ibcon#about to read 5, iclass 3, count 0 2006.239.07:31:08.72#ibcon#read 5, iclass 3, count 0 2006.239.07:31:08.72#ibcon#about to read 6, iclass 3, count 0 2006.239.07:31:08.72#ibcon#read 6, iclass 3, count 0 2006.239.07:31:08.72#ibcon#end of sib2, iclass 3, count 0 2006.239.07:31:08.72#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:31:08.72#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:31:08.72#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:31:08.72#ibcon#*before write, iclass 3, count 0 2006.239.07:31:08.72#ibcon#enter sib2, iclass 3, count 0 2006.239.07:31:08.72#ibcon#flushed, iclass 3, count 0 2006.239.07:31:08.72#ibcon#about to write, iclass 3, count 0 2006.239.07:31:08.72#ibcon#wrote, iclass 3, count 0 2006.239.07:31:08.72#ibcon#about to read 3, iclass 3, count 0 2006.239.07:31:08.76#ibcon#read 3, iclass 3, count 0 2006.239.07:31:08.76#ibcon#about to read 4, iclass 3, count 0 2006.239.07:31:08.76#ibcon#read 4, iclass 3, count 0 2006.239.07:31:08.76#ibcon#about to read 5, iclass 3, count 0 2006.239.07:31:08.76#ibcon#read 5, iclass 3, count 0 2006.239.07:31:08.76#ibcon#about to read 6, iclass 3, count 0 2006.239.07:31:08.76#ibcon#read 6, iclass 3, count 0 2006.239.07:31:08.76#ibcon#end of sib2, iclass 3, count 0 2006.239.07:31:08.76#ibcon#*after write, iclass 3, count 0 2006.239.07:31:08.76#ibcon#*before return 0, iclass 3, count 0 2006.239.07:31:08.76#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:08.76#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:08.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:31:08.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:31:08.76$vc4f8/va=3,7 2006.239.07:31:08.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.07:31:08.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.07:31:08.76#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:08.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:08.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:08.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:08.82#ibcon#enter wrdev, iclass 5, count 2 2006.239.07:31:08.82#ibcon#first serial, iclass 5, count 2 2006.239.07:31:08.82#ibcon#enter sib2, iclass 5, count 2 2006.239.07:31:08.82#ibcon#flushed, iclass 5, count 2 2006.239.07:31:08.82#ibcon#about to write, iclass 5, count 2 2006.239.07:31:08.82#ibcon#wrote, iclass 5, count 2 2006.239.07:31:08.82#ibcon#about to read 3, iclass 5, count 2 2006.239.07:31:08.84#ibcon#read 3, iclass 5, count 2 2006.239.07:31:08.84#ibcon#about to read 4, iclass 5, count 2 2006.239.07:31:08.84#ibcon#read 4, iclass 5, count 2 2006.239.07:31:08.84#ibcon#about to read 5, iclass 5, count 2 2006.239.07:31:08.84#ibcon#read 5, iclass 5, count 2 2006.239.07:31:08.84#ibcon#about to read 6, iclass 5, count 2 2006.239.07:31:08.84#ibcon#read 6, iclass 5, count 2 2006.239.07:31:08.84#ibcon#end of sib2, iclass 5, count 2 2006.239.07:31:08.84#ibcon#*mode == 0, iclass 5, count 2 2006.239.07:31:08.84#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.07:31:08.84#ibcon#[25=AT03-07\r\n] 2006.239.07:31:08.84#ibcon#*before write, iclass 5, count 2 2006.239.07:31:08.84#ibcon#enter sib2, iclass 5, count 2 2006.239.07:31:08.84#ibcon#flushed, iclass 5, count 2 2006.239.07:31:08.84#ibcon#about to write, iclass 5, count 2 2006.239.07:31:08.84#ibcon#wrote, iclass 5, count 2 2006.239.07:31:08.84#ibcon#about to read 3, iclass 5, count 2 2006.239.07:31:08.87#ibcon#read 3, iclass 5, count 2 2006.239.07:31:08.87#ibcon#about to read 4, iclass 5, count 2 2006.239.07:31:08.87#ibcon#read 4, iclass 5, count 2 2006.239.07:31:08.87#ibcon#about to read 5, iclass 5, count 2 2006.239.07:31:08.87#ibcon#read 5, iclass 5, count 2 2006.239.07:31:08.87#ibcon#about to read 6, iclass 5, count 2 2006.239.07:31:08.87#ibcon#read 6, iclass 5, count 2 2006.239.07:31:08.87#ibcon#end of sib2, iclass 5, count 2 2006.239.07:31:08.87#ibcon#*after write, iclass 5, count 2 2006.239.07:31:08.87#ibcon#*before return 0, iclass 5, count 2 2006.239.07:31:08.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:08.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:08.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.07:31:08.87#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:08.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:08.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:08.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:08.99#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:31:08.99#ibcon#first serial, iclass 5, count 0 2006.239.07:31:08.99#ibcon#enter sib2, iclass 5, count 0 2006.239.07:31:08.99#ibcon#flushed, iclass 5, count 0 2006.239.07:31:08.99#ibcon#about to write, iclass 5, count 0 2006.239.07:31:08.99#ibcon#wrote, iclass 5, count 0 2006.239.07:31:08.99#ibcon#about to read 3, iclass 5, count 0 2006.239.07:31:09.01#ibcon#read 3, iclass 5, count 0 2006.239.07:31:09.01#ibcon#about to read 4, iclass 5, count 0 2006.239.07:31:09.01#ibcon#read 4, iclass 5, count 0 2006.239.07:31:09.01#ibcon#about to read 5, iclass 5, count 0 2006.239.07:31:09.01#ibcon#read 5, iclass 5, count 0 2006.239.07:31:09.01#ibcon#about to read 6, iclass 5, count 0 2006.239.07:31:09.01#ibcon#read 6, iclass 5, count 0 2006.239.07:31:09.01#ibcon#end of sib2, iclass 5, count 0 2006.239.07:31:09.01#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:31:09.01#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:31:09.01#ibcon#[25=USB\r\n] 2006.239.07:31:09.01#ibcon#*before write, iclass 5, count 0 2006.239.07:31:09.01#ibcon#enter sib2, iclass 5, count 0 2006.239.07:31:09.01#ibcon#flushed, iclass 5, count 0 2006.239.07:31:09.01#ibcon#about to write, iclass 5, count 0 2006.239.07:31:09.01#ibcon#wrote, iclass 5, count 0 2006.239.07:31:09.01#ibcon#about to read 3, iclass 5, count 0 2006.239.07:31:09.04#ibcon#read 3, iclass 5, count 0 2006.239.07:31:09.04#ibcon#about to read 4, iclass 5, count 0 2006.239.07:31:09.04#ibcon#read 4, iclass 5, count 0 2006.239.07:31:09.04#ibcon#about to read 5, iclass 5, count 0 2006.239.07:31:09.04#ibcon#read 5, iclass 5, count 0 2006.239.07:31:09.04#ibcon#about to read 6, iclass 5, count 0 2006.239.07:31:09.04#ibcon#read 6, iclass 5, count 0 2006.239.07:31:09.04#ibcon#end of sib2, iclass 5, count 0 2006.239.07:31:09.04#ibcon#*after write, iclass 5, count 0 2006.239.07:31:09.04#ibcon#*before return 0, iclass 5, count 0 2006.239.07:31:09.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:09.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:09.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:31:09.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:31:09.04$vc4f8/valo=4,832.99 2006.239.07:31:09.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:31:09.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:31:09.04#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:09.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:09.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:09.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:09.04#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:31:09.04#ibcon#first serial, iclass 7, count 0 2006.239.07:31:09.04#ibcon#enter sib2, iclass 7, count 0 2006.239.07:31:09.04#ibcon#flushed, iclass 7, count 0 2006.239.07:31:09.04#ibcon#about to write, iclass 7, count 0 2006.239.07:31:09.04#ibcon#wrote, iclass 7, count 0 2006.239.07:31:09.04#ibcon#about to read 3, iclass 7, count 0 2006.239.07:31:09.06#ibcon#read 3, iclass 7, count 0 2006.239.07:31:09.06#ibcon#about to read 4, iclass 7, count 0 2006.239.07:31:09.06#ibcon#read 4, iclass 7, count 0 2006.239.07:31:09.06#ibcon#about to read 5, iclass 7, count 0 2006.239.07:31:09.06#ibcon#read 5, iclass 7, count 0 2006.239.07:31:09.06#ibcon#about to read 6, iclass 7, count 0 2006.239.07:31:09.06#ibcon#read 6, iclass 7, count 0 2006.239.07:31:09.06#ibcon#end of sib2, iclass 7, count 0 2006.239.07:31:09.06#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:31:09.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:31:09.06#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:31:09.06#ibcon#*before write, iclass 7, count 0 2006.239.07:31:09.06#ibcon#enter sib2, iclass 7, count 0 2006.239.07:31:09.06#ibcon#flushed, iclass 7, count 0 2006.239.07:31:09.06#ibcon#about to write, iclass 7, count 0 2006.239.07:31:09.06#ibcon#wrote, iclass 7, count 0 2006.239.07:31:09.06#ibcon#about to read 3, iclass 7, count 0 2006.239.07:31:09.10#ibcon#read 3, iclass 7, count 0 2006.239.07:31:09.10#ibcon#about to read 4, iclass 7, count 0 2006.239.07:31:09.10#ibcon#read 4, iclass 7, count 0 2006.239.07:31:09.10#ibcon#about to read 5, iclass 7, count 0 2006.239.07:31:09.10#ibcon#read 5, iclass 7, count 0 2006.239.07:31:09.10#ibcon#about to read 6, iclass 7, count 0 2006.239.07:31:09.10#ibcon#read 6, iclass 7, count 0 2006.239.07:31:09.10#ibcon#end of sib2, iclass 7, count 0 2006.239.07:31:09.10#ibcon#*after write, iclass 7, count 0 2006.239.07:31:09.10#ibcon#*before return 0, iclass 7, count 0 2006.239.07:31:09.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:09.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:09.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:31:09.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:31:09.10$vc4f8/va=4,7 2006.239.07:31:09.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.07:31:09.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.07:31:09.10#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:09.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:09.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:09.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:09.16#ibcon#enter wrdev, iclass 11, count 2 2006.239.07:31:09.16#ibcon#first serial, iclass 11, count 2 2006.239.07:31:09.16#ibcon#enter sib2, iclass 11, count 2 2006.239.07:31:09.16#ibcon#flushed, iclass 11, count 2 2006.239.07:31:09.16#ibcon#about to write, iclass 11, count 2 2006.239.07:31:09.16#ibcon#wrote, iclass 11, count 2 2006.239.07:31:09.16#ibcon#about to read 3, iclass 11, count 2 2006.239.07:31:09.18#ibcon#read 3, iclass 11, count 2 2006.239.07:31:09.18#ibcon#about to read 4, iclass 11, count 2 2006.239.07:31:09.18#ibcon#read 4, iclass 11, count 2 2006.239.07:31:09.18#ibcon#about to read 5, iclass 11, count 2 2006.239.07:31:09.18#ibcon#read 5, iclass 11, count 2 2006.239.07:31:09.18#ibcon#about to read 6, iclass 11, count 2 2006.239.07:31:09.18#ibcon#read 6, iclass 11, count 2 2006.239.07:31:09.18#ibcon#end of sib2, iclass 11, count 2 2006.239.07:31:09.18#ibcon#*mode == 0, iclass 11, count 2 2006.239.07:31:09.18#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.07:31:09.18#ibcon#[25=AT04-07\r\n] 2006.239.07:31:09.18#ibcon#*before write, iclass 11, count 2 2006.239.07:31:09.18#ibcon#enter sib2, iclass 11, count 2 2006.239.07:31:09.18#ibcon#flushed, iclass 11, count 2 2006.239.07:31:09.18#ibcon#about to write, iclass 11, count 2 2006.239.07:31:09.18#ibcon#wrote, iclass 11, count 2 2006.239.07:31:09.18#ibcon#about to read 3, iclass 11, count 2 2006.239.07:31:09.21#ibcon#read 3, iclass 11, count 2 2006.239.07:31:09.21#ibcon#about to read 4, iclass 11, count 2 2006.239.07:31:09.21#ibcon#read 4, iclass 11, count 2 2006.239.07:31:09.21#ibcon#about to read 5, iclass 11, count 2 2006.239.07:31:09.21#ibcon#read 5, iclass 11, count 2 2006.239.07:31:09.21#ibcon#about to read 6, iclass 11, count 2 2006.239.07:31:09.21#ibcon#read 6, iclass 11, count 2 2006.239.07:31:09.21#ibcon#end of sib2, iclass 11, count 2 2006.239.07:31:09.21#ibcon#*after write, iclass 11, count 2 2006.239.07:31:09.21#ibcon#*before return 0, iclass 11, count 2 2006.239.07:31:09.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:09.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:09.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.07:31:09.21#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:09.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:09.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:09.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:09.33#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:31:09.33#ibcon#first serial, iclass 11, count 0 2006.239.07:31:09.33#ibcon#enter sib2, iclass 11, count 0 2006.239.07:31:09.33#ibcon#flushed, iclass 11, count 0 2006.239.07:31:09.33#ibcon#about to write, iclass 11, count 0 2006.239.07:31:09.33#ibcon#wrote, iclass 11, count 0 2006.239.07:31:09.33#ibcon#about to read 3, iclass 11, count 0 2006.239.07:31:09.35#ibcon#read 3, iclass 11, count 0 2006.239.07:31:09.35#ibcon#about to read 4, iclass 11, count 0 2006.239.07:31:09.35#ibcon#read 4, iclass 11, count 0 2006.239.07:31:09.35#ibcon#about to read 5, iclass 11, count 0 2006.239.07:31:09.35#ibcon#read 5, iclass 11, count 0 2006.239.07:31:09.35#ibcon#about to read 6, iclass 11, count 0 2006.239.07:31:09.35#ibcon#read 6, iclass 11, count 0 2006.239.07:31:09.35#ibcon#end of sib2, iclass 11, count 0 2006.239.07:31:09.35#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:31:09.35#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:31:09.35#ibcon#[25=USB\r\n] 2006.239.07:31:09.35#ibcon#*before write, iclass 11, count 0 2006.239.07:31:09.35#ibcon#enter sib2, iclass 11, count 0 2006.239.07:31:09.35#ibcon#flushed, iclass 11, count 0 2006.239.07:31:09.35#ibcon#about to write, iclass 11, count 0 2006.239.07:31:09.35#ibcon#wrote, iclass 11, count 0 2006.239.07:31:09.35#ibcon#about to read 3, iclass 11, count 0 2006.239.07:31:09.38#ibcon#read 3, iclass 11, count 0 2006.239.07:31:09.38#ibcon#about to read 4, iclass 11, count 0 2006.239.07:31:09.38#ibcon#read 4, iclass 11, count 0 2006.239.07:31:09.38#ibcon#about to read 5, iclass 11, count 0 2006.239.07:31:09.38#ibcon#read 5, iclass 11, count 0 2006.239.07:31:09.38#ibcon#about to read 6, iclass 11, count 0 2006.239.07:31:09.38#ibcon#read 6, iclass 11, count 0 2006.239.07:31:09.38#ibcon#end of sib2, iclass 11, count 0 2006.239.07:31:09.38#ibcon#*after write, iclass 11, count 0 2006.239.07:31:09.38#ibcon#*before return 0, iclass 11, count 0 2006.239.07:31:09.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:09.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:09.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:31:09.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:31:09.38$vc4f8/valo=5,652.99 2006.239.07:31:09.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.07:31:09.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.07:31:09.38#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:09.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:09.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:09.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:09.38#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:31:09.38#ibcon#first serial, iclass 13, count 0 2006.239.07:31:09.38#ibcon#enter sib2, iclass 13, count 0 2006.239.07:31:09.38#ibcon#flushed, iclass 13, count 0 2006.239.07:31:09.38#ibcon#about to write, iclass 13, count 0 2006.239.07:31:09.38#ibcon#wrote, iclass 13, count 0 2006.239.07:31:09.38#ibcon#about to read 3, iclass 13, count 0 2006.239.07:31:09.40#ibcon#read 3, iclass 13, count 0 2006.239.07:31:09.40#ibcon#about to read 4, iclass 13, count 0 2006.239.07:31:09.40#ibcon#read 4, iclass 13, count 0 2006.239.07:31:09.40#ibcon#about to read 5, iclass 13, count 0 2006.239.07:31:09.40#ibcon#read 5, iclass 13, count 0 2006.239.07:31:09.40#ibcon#about to read 6, iclass 13, count 0 2006.239.07:31:09.40#ibcon#read 6, iclass 13, count 0 2006.239.07:31:09.40#ibcon#end of sib2, iclass 13, count 0 2006.239.07:31:09.40#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:31:09.40#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:31:09.40#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:31:09.40#ibcon#*before write, iclass 13, count 0 2006.239.07:31:09.40#ibcon#enter sib2, iclass 13, count 0 2006.239.07:31:09.40#ibcon#flushed, iclass 13, count 0 2006.239.07:31:09.40#ibcon#about to write, iclass 13, count 0 2006.239.07:31:09.40#ibcon#wrote, iclass 13, count 0 2006.239.07:31:09.40#ibcon#about to read 3, iclass 13, count 0 2006.239.07:31:09.44#ibcon#read 3, iclass 13, count 0 2006.239.07:31:09.44#ibcon#about to read 4, iclass 13, count 0 2006.239.07:31:09.44#ibcon#read 4, iclass 13, count 0 2006.239.07:31:09.44#ibcon#about to read 5, iclass 13, count 0 2006.239.07:31:09.44#ibcon#read 5, iclass 13, count 0 2006.239.07:31:09.44#ibcon#about to read 6, iclass 13, count 0 2006.239.07:31:09.44#ibcon#read 6, iclass 13, count 0 2006.239.07:31:09.44#ibcon#end of sib2, iclass 13, count 0 2006.239.07:31:09.44#ibcon#*after write, iclass 13, count 0 2006.239.07:31:09.44#ibcon#*before return 0, iclass 13, count 0 2006.239.07:31:09.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:09.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:09.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:31:09.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:31:09.44$vc4f8/va=5,8 2006.239.07:31:09.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.07:31:09.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.07:31:09.44#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:09.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:09.50#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:09.50#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:09.50#ibcon#enter wrdev, iclass 15, count 2 2006.239.07:31:09.50#ibcon#first serial, iclass 15, count 2 2006.239.07:31:09.50#ibcon#enter sib2, iclass 15, count 2 2006.239.07:31:09.50#ibcon#flushed, iclass 15, count 2 2006.239.07:31:09.50#ibcon#about to write, iclass 15, count 2 2006.239.07:31:09.50#ibcon#wrote, iclass 15, count 2 2006.239.07:31:09.50#ibcon#about to read 3, iclass 15, count 2 2006.239.07:31:09.52#ibcon#read 3, iclass 15, count 2 2006.239.07:31:09.52#ibcon#about to read 4, iclass 15, count 2 2006.239.07:31:09.52#ibcon#read 4, iclass 15, count 2 2006.239.07:31:09.52#ibcon#about to read 5, iclass 15, count 2 2006.239.07:31:09.52#ibcon#read 5, iclass 15, count 2 2006.239.07:31:09.52#ibcon#about to read 6, iclass 15, count 2 2006.239.07:31:09.52#ibcon#read 6, iclass 15, count 2 2006.239.07:31:09.52#ibcon#end of sib2, iclass 15, count 2 2006.239.07:31:09.52#ibcon#*mode == 0, iclass 15, count 2 2006.239.07:31:09.52#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.07:31:09.52#ibcon#[25=AT05-08\r\n] 2006.239.07:31:09.52#ibcon#*before write, iclass 15, count 2 2006.239.07:31:09.52#ibcon#enter sib2, iclass 15, count 2 2006.239.07:31:09.52#ibcon#flushed, iclass 15, count 2 2006.239.07:31:09.52#ibcon#about to write, iclass 15, count 2 2006.239.07:31:09.52#ibcon#wrote, iclass 15, count 2 2006.239.07:31:09.52#ibcon#about to read 3, iclass 15, count 2 2006.239.07:31:09.55#ibcon#read 3, iclass 15, count 2 2006.239.07:31:09.55#ibcon#about to read 4, iclass 15, count 2 2006.239.07:31:09.55#ibcon#read 4, iclass 15, count 2 2006.239.07:31:09.55#ibcon#about to read 5, iclass 15, count 2 2006.239.07:31:09.55#ibcon#read 5, iclass 15, count 2 2006.239.07:31:09.55#ibcon#about to read 6, iclass 15, count 2 2006.239.07:31:09.55#ibcon#read 6, iclass 15, count 2 2006.239.07:31:09.55#ibcon#end of sib2, iclass 15, count 2 2006.239.07:31:09.55#ibcon#*after write, iclass 15, count 2 2006.239.07:31:09.55#ibcon#*before return 0, iclass 15, count 2 2006.239.07:31:09.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:09.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:09.55#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.07:31:09.55#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:09.55#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:09.67#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:09.67#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:09.67#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:31:09.67#ibcon#first serial, iclass 15, count 0 2006.239.07:31:09.67#ibcon#enter sib2, iclass 15, count 0 2006.239.07:31:09.67#ibcon#flushed, iclass 15, count 0 2006.239.07:31:09.67#ibcon#about to write, iclass 15, count 0 2006.239.07:31:09.67#ibcon#wrote, iclass 15, count 0 2006.239.07:31:09.67#ibcon#about to read 3, iclass 15, count 0 2006.239.07:31:09.69#ibcon#read 3, iclass 15, count 0 2006.239.07:31:09.69#ibcon#about to read 4, iclass 15, count 0 2006.239.07:31:09.69#ibcon#read 4, iclass 15, count 0 2006.239.07:31:09.69#ibcon#about to read 5, iclass 15, count 0 2006.239.07:31:09.69#ibcon#read 5, iclass 15, count 0 2006.239.07:31:09.69#ibcon#about to read 6, iclass 15, count 0 2006.239.07:31:09.69#ibcon#read 6, iclass 15, count 0 2006.239.07:31:09.69#ibcon#end of sib2, iclass 15, count 0 2006.239.07:31:09.69#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:31:09.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:31:09.69#ibcon#[25=USB\r\n] 2006.239.07:31:09.69#ibcon#*before write, iclass 15, count 0 2006.239.07:31:09.69#ibcon#enter sib2, iclass 15, count 0 2006.239.07:31:09.69#ibcon#flushed, iclass 15, count 0 2006.239.07:31:09.69#ibcon#about to write, iclass 15, count 0 2006.239.07:31:09.69#ibcon#wrote, iclass 15, count 0 2006.239.07:31:09.69#ibcon#about to read 3, iclass 15, count 0 2006.239.07:31:09.74#ibcon#read 3, iclass 15, count 0 2006.239.07:31:09.74#ibcon#about to read 4, iclass 15, count 0 2006.239.07:31:09.74#ibcon#read 4, iclass 15, count 0 2006.239.07:31:09.74#ibcon#about to read 5, iclass 15, count 0 2006.239.07:31:09.74#ibcon#read 5, iclass 15, count 0 2006.239.07:31:09.74#ibcon#about to read 6, iclass 15, count 0 2006.239.07:31:09.74#ibcon#read 6, iclass 15, count 0 2006.239.07:31:09.74#ibcon#end of sib2, iclass 15, count 0 2006.239.07:31:09.74#ibcon#*after write, iclass 15, count 0 2006.239.07:31:09.74#ibcon#*before return 0, iclass 15, count 0 2006.239.07:31:09.74#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:09.74#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:09.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:31:09.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:31:09.74$vc4f8/valo=6,772.99 2006.239.07:31:09.74#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.07:31:09.74#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.07:31:09.74#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:09.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:09.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:09.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:09.74#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:31:09.74#ibcon#first serial, iclass 17, count 0 2006.239.07:31:09.74#ibcon#enter sib2, iclass 17, count 0 2006.239.07:31:09.74#ibcon#flushed, iclass 17, count 0 2006.239.07:31:09.74#ibcon#about to write, iclass 17, count 0 2006.239.07:31:09.74#ibcon#wrote, iclass 17, count 0 2006.239.07:31:09.74#ibcon#about to read 3, iclass 17, count 0 2006.239.07:31:09.76#ibcon#read 3, iclass 17, count 0 2006.239.07:31:09.76#ibcon#about to read 4, iclass 17, count 0 2006.239.07:31:09.76#ibcon#read 4, iclass 17, count 0 2006.239.07:31:09.76#ibcon#about to read 5, iclass 17, count 0 2006.239.07:31:09.76#ibcon#read 5, iclass 17, count 0 2006.239.07:31:09.76#ibcon#about to read 6, iclass 17, count 0 2006.239.07:31:09.76#ibcon#read 6, iclass 17, count 0 2006.239.07:31:09.76#ibcon#end of sib2, iclass 17, count 0 2006.239.07:31:09.76#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:31:09.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:31:09.76#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:31:09.76#ibcon#*before write, iclass 17, count 0 2006.239.07:31:09.76#ibcon#enter sib2, iclass 17, count 0 2006.239.07:31:09.76#ibcon#flushed, iclass 17, count 0 2006.239.07:31:09.76#ibcon#about to write, iclass 17, count 0 2006.239.07:31:09.76#ibcon#wrote, iclass 17, count 0 2006.239.07:31:09.76#ibcon#about to read 3, iclass 17, count 0 2006.239.07:31:09.80#ibcon#read 3, iclass 17, count 0 2006.239.07:31:09.80#ibcon#about to read 4, iclass 17, count 0 2006.239.07:31:09.80#ibcon#read 4, iclass 17, count 0 2006.239.07:31:09.80#ibcon#about to read 5, iclass 17, count 0 2006.239.07:31:09.80#ibcon#read 5, iclass 17, count 0 2006.239.07:31:09.80#ibcon#about to read 6, iclass 17, count 0 2006.239.07:31:09.80#ibcon#read 6, iclass 17, count 0 2006.239.07:31:09.80#ibcon#end of sib2, iclass 17, count 0 2006.239.07:31:09.80#ibcon#*after write, iclass 17, count 0 2006.239.07:31:09.80#ibcon#*before return 0, iclass 17, count 0 2006.239.07:31:09.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:09.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:09.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:31:09.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:31:09.80$vc4f8/va=6,7 2006.239.07:31:09.80#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.07:31:09.80#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.07:31:09.80#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:09.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:31:09.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:31:09.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:31:09.86#ibcon#enter wrdev, iclass 19, count 2 2006.239.07:31:09.86#ibcon#first serial, iclass 19, count 2 2006.239.07:31:09.86#ibcon#enter sib2, iclass 19, count 2 2006.239.07:31:09.86#ibcon#flushed, iclass 19, count 2 2006.239.07:31:09.86#ibcon#about to write, iclass 19, count 2 2006.239.07:31:09.86#ibcon#wrote, iclass 19, count 2 2006.239.07:31:09.86#ibcon#about to read 3, iclass 19, count 2 2006.239.07:31:09.88#ibcon#read 3, iclass 19, count 2 2006.239.07:31:09.88#ibcon#about to read 4, iclass 19, count 2 2006.239.07:31:09.88#ibcon#read 4, iclass 19, count 2 2006.239.07:31:09.88#ibcon#about to read 5, iclass 19, count 2 2006.239.07:31:09.88#ibcon#read 5, iclass 19, count 2 2006.239.07:31:09.88#ibcon#about to read 6, iclass 19, count 2 2006.239.07:31:09.88#ibcon#read 6, iclass 19, count 2 2006.239.07:31:09.88#ibcon#end of sib2, iclass 19, count 2 2006.239.07:31:09.88#ibcon#*mode == 0, iclass 19, count 2 2006.239.07:31:09.88#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.07:31:09.88#ibcon#[25=AT06-07\r\n] 2006.239.07:31:09.88#ibcon#*before write, iclass 19, count 2 2006.239.07:31:09.88#ibcon#enter sib2, iclass 19, count 2 2006.239.07:31:09.88#ibcon#flushed, iclass 19, count 2 2006.239.07:31:09.88#ibcon#about to write, iclass 19, count 2 2006.239.07:31:09.88#ibcon#wrote, iclass 19, count 2 2006.239.07:31:09.88#ibcon#about to read 3, iclass 19, count 2 2006.239.07:31:09.91#ibcon#read 3, iclass 19, count 2 2006.239.07:31:09.91#ibcon#about to read 4, iclass 19, count 2 2006.239.07:31:09.91#ibcon#read 4, iclass 19, count 2 2006.239.07:31:09.91#ibcon#about to read 5, iclass 19, count 2 2006.239.07:31:09.91#ibcon#read 5, iclass 19, count 2 2006.239.07:31:09.91#ibcon#about to read 6, iclass 19, count 2 2006.239.07:31:09.91#ibcon#read 6, iclass 19, count 2 2006.239.07:31:09.91#ibcon#end of sib2, iclass 19, count 2 2006.239.07:31:09.91#ibcon#*after write, iclass 19, count 2 2006.239.07:31:09.91#ibcon#*before return 0, iclass 19, count 2 2006.239.07:31:09.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:31:09.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:31:09.91#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.07:31:09.91#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:09.91#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:31:10.03#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:31:10.03#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:31:10.03#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:31:10.03#ibcon#first serial, iclass 19, count 0 2006.239.07:31:10.03#ibcon#enter sib2, iclass 19, count 0 2006.239.07:31:10.03#ibcon#flushed, iclass 19, count 0 2006.239.07:31:10.03#ibcon#about to write, iclass 19, count 0 2006.239.07:31:10.03#ibcon#wrote, iclass 19, count 0 2006.239.07:31:10.03#ibcon#about to read 3, iclass 19, count 0 2006.239.07:31:10.05#ibcon#read 3, iclass 19, count 0 2006.239.07:31:10.05#ibcon#about to read 4, iclass 19, count 0 2006.239.07:31:10.05#ibcon#read 4, iclass 19, count 0 2006.239.07:31:10.05#ibcon#about to read 5, iclass 19, count 0 2006.239.07:31:10.05#ibcon#read 5, iclass 19, count 0 2006.239.07:31:10.05#ibcon#about to read 6, iclass 19, count 0 2006.239.07:31:10.05#ibcon#read 6, iclass 19, count 0 2006.239.07:31:10.05#ibcon#end of sib2, iclass 19, count 0 2006.239.07:31:10.05#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:31:10.05#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:31:10.05#ibcon#[25=USB\r\n] 2006.239.07:31:10.05#ibcon#*before write, iclass 19, count 0 2006.239.07:31:10.05#ibcon#enter sib2, iclass 19, count 0 2006.239.07:31:10.05#ibcon#flushed, iclass 19, count 0 2006.239.07:31:10.05#ibcon#about to write, iclass 19, count 0 2006.239.07:31:10.05#ibcon#wrote, iclass 19, count 0 2006.239.07:31:10.05#ibcon#about to read 3, iclass 19, count 0 2006.239.07:31:10.08#ibcon#read 3, iclass 19, count 0 2006.239.07:31:10.08#ibcon#about to read 4, iclass 19, count 0 2006.239.07:31:10.08#ibcon#read 4, iclass 19, count 0 2006.239.07:31:10.08#ibcon#about to read 5, iclass 19, count 0 2006.239.07:31:10.08#ibcon#read 5, iclass 19, count 0 2006.239.07:31:10.08#ibcon#about to read 6, iclass 19, count 0 2006.239.07:31:10.08#ibcon#read 6, iclass 19, count 0 2006.239.07:31:10.08#ibcon#end of sib2, iclass 19, count 0 2006.239.07:31:10.08#ibcon#*after write, iclass 19, count 0 2006.239.07:31:10.08#ibcon#*before return 0, iclass 19, count 0 2006.239.07:31:10.08#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:31:10.08#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:31:10.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:31:10.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:31:10.08$vc4f8/valo=7,832.99 2006.239.07:31:10.08#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.07:31:10.08#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.07:31:10.08#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:10.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:31:10.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:31:10.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:31:10.08#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:31:10.08#ibcon#first serial, iclass 21, count 0 2006.239.07:31:10.08#ibcon#enter sib2, iclass 21, count 0 2006.239.07:31:10.08#ibcon#flushed, iclass 21, count 0 2006.239.07:31:10.08#ibcon#about to write, iclass 21, count 0 2006.239.07:31:10.08#ibcon#wrote, iclass 21, count 0 2006.239.07:31:10.08#ibcon#about to read 3, iclass 21, count 0 2006.239.07:31:10.10#ibcon#read 3, iclass 21, count 0 2006.239.07:31:10.10#ibcon#about to read 4, iclass 21, count 0 2006.239.07:31:10.10#ibcon#read 4, iclass 21, count 0 2006.239.07:31:10.10#ibcon#about to read 5, iclass 21, count 0 2006.239.07:31:10.10#ibcon#read 5, iclass 21, count 0 2006.239.07:31:10.10#ibcon#about to read 6, iclass 21, count 0 2006.239.07:31:10.10#ibcon#read 6, iclass 21, count 0 2006.239.07:31:10.10#ibcon#end of sib2, iclass 21, count 0 2006.239.07:31:10.10#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:31:10.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:31:10.10#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:31:10.10#ibcon#*before write, iclass 21, count 0 2006.239.07:31:10.10#ibcon#enter sib2, iclass 21, count 0 2006.239.07:31:10.10#ibcon#flushed, iclass 21, count 0 2006.239.07:31:10.10#ibcon#about to write, iclass 21, count 0 2006.239.07:31:10.10#ibcon#wrote, iclass 21, count 0 2006.239.07:31:10.10#ibcon#about to read 3, iclass 21, count 0 2006.239.07:31:10.14#ibcon#read 3, iclass 21, count 0 2006.239.07:31:10.14#ibcon#about to read 4, iclass 21, count 0 2006.239.07:31:10.14#ibcon#read 4, iclass 21, count 0 2006.239.07:31:10.14#ibcon#about to read 5, iclass 21, count 0 2006.239.07:31:10.14#ibcon#read 5, iclass 21, count 0 2006.239.07:31:10.14#ibcon#about to read 6, iclass 21, count 0 2006.239.07:31:10.14#ibcon#read 6, iclass 21, count 0 2006.239.07:31:10.14#ibcon#end of sib2, iclass 21, count 0 2006.239.07:31:10.14#ibcon#*after write, iclass 21, count 0 2006.239.07:31:10.14#ibcon#*before return 0, iclass 21, count 0 2006.239.07:31:10.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:31:10.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:31:10.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:31:10.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:31:10.14$vc4f8/va=7,7 2006.239.07:31:10.14#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.07:31:10.14#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.07:31:10.14#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:10.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:31:10.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:31:10.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:31:10.20#ibcon#enter wrdev, iclass 23, count 2 2006.239.07:31:10.20#ibcon#first serial, iclass 23, count 2 2006.239.07:31:10.20#ibcon#enter sib2, iclass 23, count 2 2006.239.07:31:10.20#ibcon#flushed, iclass 23, count 2 2006.239.07:31:10.20#ibcon#about to write, iclass 23, count 2 2006.239.07:31:10.20#ibcon#wrote, iclass 23, count 2 2006.239.07:31:10.20#ibcon#about to read 3, iclass 23, count 2 2006.239.07:31:10.22#ibcon#read 3, iclass 23, count 2 2006.239.07:31:10.22#ibcon#about to read 4, iclass 23, count 2 2006.239.07:31:10.22#ibcon#read 4, iclass 23, count 2 2006.239.07:31:10.22#ibcon#about to read 5, iclass 23, count 2 2006.239.07:31:10.22#ibcon#read 5, iclass 23, count 2 2006.239.07:31:10.22#ibcon#about to read 6, iclass 23, count 2 2006.239.07:31:10.22#ibcon#read 6, iclass 23, count 2 2006.239.07:31:10.22#ibcon#end of sib2, iclass 23, count 2 2006.239.07:31:10.22#ibcon#*mode == 0, iclass 23, count 2 2006.239.07:31:10.22#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.07:31:10.22#ibcon#[25=AT07-07\r\n] 2006.239.07:31:10.22#ibcon#*before write, iclass 23, count 2 2006.239.07:31:10.22#ibcon#enter sib2, iclass 23, count 2 2006.239.07:31:10.22#ibcon#flushed, iclass 23, count 2 2006.239.07:31:10.22#ibcon#about to write, iclass 23, count 2 2006.239.07:31:10.22#ibcon#wrote, iclass 23, count 2 2006.239.07:31:10.22#ibcon#about to read 3, iclass 23, count 2 2006.239.07:31:10.25#ibcon#read 3, iclass 23, count 2 2006.239.07:31:10.25#ibcon#about to read 4, iclass 23, count 2 2006.239.07:31:10.25#ibcon#read 4, iclass 23, count 2 2006.239.07:31:10.25#ibcon#about to read 5, iclass 23, count 2 2006.239.07:31:10.25#ibcon#read 5, iclass 23, count 2 2006.239.07:31:10.25#ibcon#about to read 6, iclass 23, count 2 2006.239.07:31:10.25#ibcon#read 6, iclass 23, count 2 2006.239.07:31:10.25#ibcon#end of sib2, iclass 23, count 2 2006.239.07:31:10.25#ibcon#*after write, iclass 23, count 2 2006.239.07:31:10.25#ibcon#*before return 0, iclass 23, count 2 2006.239.07:31:10.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:31:10.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:31:10.25#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.07:31:10.25#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:10.25#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:31:10.37#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:31:10.37#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:31:10.37#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:31:10.37#ibcon#first serial, iclass 23, count 0 2006.239.07:31:10.37#ibcon#enter sib2, iclass 23, count 0 2006.239.07:31:10.37#ibcon#flushed, iclass 23, count 0 2006.239.07:31:10.37#ibcon#about to write, iclass 23, count 0 2006.239.07:31:10.37#ibcon#wrote, iclass 23, count 0 2006.239.07:31:10.37#ibcon#about to read 3, iclass 23, count 0 2006.239.07:31:10.39#ibcon#read 3, iclass 23, count 0 2006.239.07:31:10.39#ibcon#about to read 4, iclass 23, count 0 2006.239.07:31:10.39#ibcon#read 4, iclass 23, count 0 2006.239.07:31:10.39#ibcon#about to read 5, iclass 23, count 0 2006.239.07:31:10.39#ibcon#read 5, iclass 23, count 0 2006.239.07:31:10.39#ibcon#about to read 6, iclass 23, count 0 2006.239.07:31:10.39#ibcon#read 6, iclass 23, count 0 2006.239.07:31:10.39#ibcon#end of sib2, iclass 23, count 0 2006.239.07:31:10.39#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:31:10.39#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:31:10.39#ibcon#[25=USB\r\n] 2006.239.07:31:10.39#ibcon#*before write, iclass 23, count 0 2006.239.07:31:10.39#ibcon#enter sib2, iclass 23, count 0 2006.239.07:31:10.39#ibcon#flushed, iclass 23, count 0 2006.239.07:31:10.39#ibcon#about to write, iclass 23, count 0 2006.239.07:31:10.39#ibcon#wrote, iclass 23, count 0 2006.239.07:31:10.39#ibcon#about to read 3, iclass 23, count 0 2006.239.07:31:10.42#ibcon#read 3, iclass 23, count 0 2006.239.07:31:10.42#ibcon#about to read 4, iclass 23, count 0 2006.239.07:31:10.42#ibcon#read 4, iclass 23, count 0 2006.239.07:31:10.42#ibcon#about to read 5, iclass 23, count 0 2006.239.07:31:10.42#ibcon#read 5, iclass 23, count 0 2006.239.07:31:10.42#ibcon#about to read 6, iclass 23, count 0 2006.239.07:31:10.42#ibcon#read 6, iclass 23, count 0 2006.239.07:31:10.42#ibcon#end of sib2, iclass 23, count 0 2006.239.07:31:10.42#ibcon#*after write, iclass 23, count 0 2006.239.07:31:10.42#ibcon#*before return 0, iclass 23, count 0 2006.239.07:31:10.42#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:31:10.42#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:31:10.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:31:10.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:31:10.42$vc4f8/valo=8,852.99 2006.239.07:31:10.42#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:31:10.42#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:31:10.42#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:10.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:31:10.42#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:31:10.42#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:31:10.42#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:31:10.42#ibcon#first serial, iclass 25, count 0 2006.239.07:31:10.42#ibcon#enter sib2, iclass 25, count 0 2006.239.07:31:10.42#ibcon#flushed, iclass 25, count 0 2006.239.07:31:10.42#ibcon#about to write, iclass 25, count 0 2006.239.07:31:10.42#ibcon#wrote, iclass 25, count 0 2006.239.07:31:10.42#ibcon#about to read 3, iclass 25, count 0 2006.239.07:31:10.44#ibcon#read 3, iclass 25, count 0 2006.239.07:31:10.44#ibcon#about to read 4, iclass 25, count 0 2006.239.07:31:10.44#ibcon#read 4, iclass 25, count 0 2006.239.07:31:10.44#ibcon#about to read 5, iclass 25, count 0 2006.239.07:31:10.44#ibcon#read 5, iclass 25, count 0 2006.239.07:31:10.44#ibcon#about to read 6, iclass 25, count 0 2006.239.07:31:10.44#ibcon#read 6, iclass 25, count 0 2006.239.07:31:10.44#ibcon#end of sib2, iclass 25, count 0 2006.239.07:31:10.44#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:31:10.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:31:10.44#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:31:10.44#ibcon#*before write, iclass 25, count 0 2006.239.07:31:10.44#ibcon#enter sib2, iclass 25, count 0 2006.239.07:31:10.44#ibcon#flushed, iclass 25, count 0 2006.239.07:31:10.44#ibcon#about to write, iclass 25, count 0 2006.239.07:31:10.44#ibcon#wrote, iclass 25, count 0 2006.239.07:31:10.44#ibcon#about to read 3, iclass 25, count 0 2006.239.07:31:10.48#ibcon#read 3, iclass 25, count 0 2006.239.07:31:10.48#ibcon#about to read 4, iclass 25, count 0 2006.239.07:31:10.48#ibcon#read 4, iclass 25, count 0 2006.239.07:31:10.48#ibcon#about to read 5, iclass 25, count 0 2006.239.07:31:10.48#ibcon#read 5, iclass 25, count 0 2006.239.07:31:10.48#ibcon#about to read 6, iclass 25, count 0 2006.239.07:31:10.48#ibcon#read 6, iclass 25, count 0 2006.239.07:31:10.48#ibcon#end of sib2, iclass 25, count 0 2006.239.07:31:10.48#ibcon#*after write, iclass 25, count 0 2006.239.07:31:10.48#ibcon#*before return 0, iclass 25, count 0 2006.239.07:31:10.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:31:10.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:31:10.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:31:10.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:31:10.48$vc4f8/va=8,7 2006.239.07:31:10.48#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:31:10.48#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:31:10.48#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:10.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:31:10.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:31:10.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:31:10.54#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:31:10.54#ibcon#first serial, iclass 27, count 2 2006.239.07:31:10.54#ibcon#enter sib2, iclass 27, count 2 2006.239.07:31:10.54#ibcon#flushed, iclass 27, count 2 2006.239.07:31:10.54#ibcon#about to write, iclass 27, count 2 2006.239.07:31:10.54#ibcon#wrote, iclass 27, count 2 2006.239.07:31:10.54#ibcon#about to read 3, iclass 27, count 2 2006.239.07:31:10.56#ibcon#read 3, iclass 27, count 2 2006.239.07:31:10.56#ibcon#about to read 4, iclass 27, count 2 2006.239.07:31:10.56#ibcon#read 4, iclass 27, count 2 2006.239.07:31:10.56#ibcon#about to read 5, iclass 27, count 2 2006.239.07:31:10.56#ibcon#read 5, iclass 27, count 2 2006.239.07:31:10.56#ibcon#about to read 6, iclass 27, count 2 2006.239.07:31:10.56#ibcon#read 6, iclass 27, count 2 2006.239.07:31:10.56#ibcon#end of sib2, iclass 27, count 2 2006.239.07:31:10.56#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:31:10.56#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:31:10.56#ibcon#[25=AT08-07\r\n] 2006.239.07:31:10.56#ibcon#*before write, iclass 27, count 2 2006.239.07:31:10.56#ibcon#enter sib2, iclass 27, count 2 2006.239.07:31:10.56#ibcon#flushed, iclass 27, count 2 2006.239.07:31:10.56#ibcon#about to write, iclass 27, count 2 2006.239.07:31:10.56#ibcon#wrote, iclass 27, count 2 2006.239.07:31:10.56#ibcon#about to read 3, iclass 27, count 2 2006.239.07:31:10.59#ibcon#read 3, iclass 27, count 2 2006.239.07:31:10.59#ibcon#about to read 4, iclass 27, count 2 2006.239.07:31:10.59#ibcon#read 4, iclass 27, count 2 2006.239.07:31:10.59#ibcon#about to read 5, iclass 27, count 2 2006.239.07:31:10.59#ibcon#read 5, iclass 27, count 2 2006.239.07:31:10.59#ibcon#about to read 6, iclass 27, count 2 2006.239.07:31:10.59#ibcon#read 6, iclass 27, count 2 2006.239.07:31:10.59#ibcon#end of sib2, iclass 27, count 2 2006.239.07:31:10.59#ibcon#*after write, iclass 27, count 2 2006.239.07:31:10.59#ibcon#*before return 0, iclass 27, count 2 2006.239.07:31:10.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:31:10.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:31:10.59#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:31:10.59#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:10.59#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:31:10.71#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:31:10.71#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:31:10.71#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:31:10.71#ibcon#first serial, iclass 27, count 0 2006.239.07:31:10.71#ibcon#enter sib2, iclass 27, count 0 2006.239.07:31:10.71#ibcon#flushed, iclass 27, count 0 2006.239.07:31:10.71#ibcon#about to write, iclass 27, count 0 2006.239.07:31:10.71#ibcon#wrote, iclass 27, count 0 2006.239.07:31:10.71#ibcon#about to read 3, iclass 27, count 0 2006.239.07:31:10.73#ibcon#read 3, iclass 27, count 0 2006.239.07:31:10.73#ibcon#about to read 4, iclass 27, count 0 2006.239.07:31:10.73#ibcon#read 4, iclass 27, count 0 2006.239.07:31:10.73#ibcon#about to read 5, iclass 27, count 0 2006.239.07:31:10.73#ibcon#read 5, iclass 27, count 0 2006.239.07:31:10.73#ibcon#about to read 6, iclass 27, count 0 2006.239.07:31:10.73#ibcon#read 6, iclass 27, count 0 2006.239.07:31:10.73#ibcon#end of sib2, iclass 27, count 0 2006.239.07:31:10.73#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:31:10.73#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:31:10.73#ibcon#[25=USB\r\n] 2006.239.07:31:10.73#ibcon#*before write, iclass 27, count 0 2006.239.07:31:10.73#ibcon#enter sib2, iclass 27, count 0 2006.239.07:31:10.73#ibcon#flushed, iclass 27, count 0 2006.239.07:31:10.73#ibcon#about to write, iclass 27, count 0 2006.239.07:31:10.73#ibcon#wrote, iclass 27, count 0 2006.239.07:31:10.73#ibcon#about to read 3, iclass 27, count 0 2006.239.07:31:10.76#ibcon#read 3, iclass 27, count 0 2006.239.07:31:10.76#ibcon#about to read 4, iclass 27, count 0 2006.239.07:31:10.76#ibcon#read 4, iclass 27, count 0 2006.239.07:31:10.76#ibcon#about to read 5, iclass 27, count 0 2006.239.07:31:10.76#ibcon#read 5, iclass 27, count 0 2006.239.07:31:10.76#ibcon#about to read 6, iclass 27, count 0 2006.239.07:31:10.76#ibcon#read 6, iclass 27, count 0 2006.239.07:31:10.76#ibcon#end of sib2, iclass 27, count 0 2006.239.07:31:10.76#ibcon#*after write, iclass 27, count 0 2006.239.07:31:10.76#ibcon#*before return 0, iclass 27, count 0 2006.239.07:31:10.76#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:31:10.76#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:31:10.76#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:31:10.76#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:31:10.76$vc4f8/vblo=1,632.99 2006.239.07:31:10.76#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:31:10.76#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:31:10.76#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:10.76#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:31:10.76#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:31:10.76#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:31:10.76#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:31:10.76#ibcon#first serial, iclass 29, count 0 2006.239.07:31:10.76#ibcon#enter sib2, iclass 29, count 0 2006.239.07:31:10.76#ibcon#flushed, iclass 29, count 0 2006.239.07:31:10.76#ibcon#about to write, iclass 29, count 0 2006.239.07:31:10.76#ibcon#wrote, iclass 29, count 0 2006.239.07:31:10.76#ibcon#about to read 3, iclass 29, count 0 2006.239.07:31:10.78#ibcon#read 3, iclass 29, count 0 2006.239.07:31:10.78#ibcon#about to read 4, iclass 29, count 0 2006.239.07:31:10.78#ibcon#read 4, iclass 29, count 0 2006.239.07:31:10.78#ibcon#about to read 5, iclass 29, count 0 2006.239.07:31:10.78#ibcon#read 5, iclass 29, count 0 2006.239.07:31:10.78#ibcon#about to read 6, iclass 29, count 0 2006.239.07:31:10.78#ibcon#read 6, iclass 29, count 0 2006.239.07:31:10.78#ibcon#end of sib2, iclass 29, count 0 2006.239.07:31:10.78#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:31:10.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:31:10.78#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:31:10.78#ibcon#*before write, iclass 29, count 0 2006.239.07:31:10.78#ibcon#enter sib2, iclass 29, count 0 2006.239.07:31:10.78#ibcon#flushed, iclass 29, count 0 2006.239.07:31:10.78#ibcon#about to write, iclass 29, count 0 2006.239.07:31:10.78#ibcon#wrote, iclass 29, count 0 2006.239.07:31:10.78#ibcon#about to read 3, iclass 29, count 0 2006.239.07:31:10.82#ibcon#read 3, iclass 29, count 0 2006.239.07:31:10.82#ibcon#about to read 4, iclass 29, count 0 2006.239.07:31:10.82#ibcon#read 4, iclass 29, count 0 2006.239.07:31:10.82#ibcon#about to read 5, iclass 29, count 0 2006.239.07:31:10.82#ibcon#read 5, iclass 29, count 0 2006.239.07:31:10.82#ibcon#about to read 6, iclass 29, count 0 2006.239.07:31:10.82#ibcon#read 6, iclass 29, count 0 2006.239.07:31:10.82#ibcon#end of sib2, iclass 29, count 0 2006.239.07:31:10.82#ibcon#*after write, iclass 29, count 0 2006.239.07:31:10.82#ibcon#*before return 0, iclass 29, count 0 2006.239.07:31:10.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:31:10.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:31:10.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:31:10.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:31:10.82$vc4f8/vb=1,4 2006.239.07:31:10.82#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:31:10.82#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:31:10.82#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:10.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:31:10.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:31:10.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:31:10.82#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:31:10.82#ibcon#first serial, iclass 31, count 2 2006.239.07:31:10.82#ibcon#enter sib2, iclass 31, count 2 2006.239.07:31:10.82#ibcon#flushed, iclass 31, count 2 2006.239.07:31:10.82#ibcon#about to write, iclass 31, count 2 2006.239.07:31:10.82#ibcon#wrote, iclass 31, count 2 2006.239.07:31:10.82#ibcon#about to read 3, iclass 31, count 2 2006.239.07:31:10.84#ibcon#read 3, iclass 31, count 2 2006.239.07:31:10.84#ibcon#about to read 4, iclass 31, count 2 2006.239.07:31:10.84#ibcon#read 4, iclass 31, count 2 2006.239.07:31:10.84#ibcon#about to read 5, iclass 31, count 2 2006.239.07:31:10.84#ibcon#read 5, iclass 31, count 2 2006.239.07:31:10.84#ibcon#about to read 6, iclass 31, count 2 2006.239.07:31:10.84#ibcon#read 6, iclass 31, count 2 2006.239.07:31:10.84#ibcon#end of sib2, iclass 31, count 2 2006.239.07:31:10.84#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:31:10.84#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:31:10.84#ibcon#[27=AT01-04\r\n] 2006.239.07:31:10.84#ibcon#*before write, iclass 31, count 2 2006.239.07:31:10.84#ibcon#enter sib2, iclass 31, count 2 2006.239.07:31:10.84#ibcon#flushed, iclass 31, count 2 2006.239.07:31:10.84#ibcon#about to write, iclass 31, count 2 2006.239.07:31:10.84#ibcon#wrote, iclass 31, count 2 2006.239.07:31:10.84#ibcon#about to read 3, iclass 31, count 2 2006.239.07:31:10.87#ibcon#read 3, iclass 31, count 2 2006.239.07:31:10.87#ibcon#about to read 4, iclass 31, count 2 2006.239.07:31:10.87#ibcon#read 4, iclass 31, count 2 2006.239.07:31:10.87#ibcon#about to read 5, iclass 31, count 2 2006.239.07:31:10.87#ibcon#read 5, iclass 31, count 2 2006.239.07:31:10.87#ibcon#about to read 6, iclass 31, count 2 2006.239.07:31:10.87#ibcon#read 6, iclass 31, count 2 2006.239.07:31:10.87#ibcon#end of sib2, iclass 31, count 2 2006.239.07:31:10.87#ibcon#*after write, iclass 31, count 2 2006.239.07:31:10.87#ibcon#*before return 0, iclass 31, count 2 2006.239.07:31:10.87#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:31:10.87#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:31:10.87#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:31:10.87#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:10.87#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:31:10.99#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:31:10.99#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:31:10.99#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:31:10.99#ibcon#first serial, iclass 31, count 0 2006.239.07:31:10.99#ibcon#enter sib2, iclass 31, count 0 2006.239.07:31:10.99#ibcon#flushed, iclass 31, count 0 2006.239.07:31:10.99#ibcon#about to write, iclass 31, count 0 2006.239.07:31:10.99#ibcon#wrote, iclass 31, count 0 2006.239.07:31:10.99#ibcon#about to read 3, iclass 31, count 0 2006.239.07:31:11.01#ibcon#read 3, iclass 31, count 0 2006.239.07:31:11.01#ibcon#about to read 4, iclass 31, count 0 2006.239.07:31:11.01#ibcon#read 4, iclass 31, count 0 2006.239.07:31:11.01#ibcon#about to read 5, iclass 31, count 0 2006.239.07:31:11.01#ibcon#read 5, iclass 31, count 0 2006.239.07:31:11.01#ibcon#about to read 6, iclass 31, count 0 2006.239.07:31:11.01#ibcon#read 6, iclass 31, count 0 2006.239.07:31:11.01#ibcon#end of sib2, iclass 31, count 0 2006.239.07:31:11.01#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:31:11.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:31:11.01#ibcon#[27=USB\r\n] 2006.239.07:31:11.01#ibcon#*before write, iclass 31, count 0 2006.239.07:31:11.01#ibcon#enter sib2, iclass 31, count 0 2006.239.07:31:11.01#ibcon#flushed, iclass 31, count 0 2006.239.07:31:11.01#ibcon#about to write, iclass 31, count 0 2006.239.07:31:11.01#ibcon#wrote, iclass 31, count 0 2006.239.07:31:11.01#ibcon#about to read 3, iclass 31, count 0 2006.239.07:31:11.04#ibcon#read 3, iclass 31, count 0 2006.239.07:31:11.04#ibcon#about to read 4, iclass 31, count 0 2006.239.07:31:11.04#ibcon#read 4, iclass 31, count 0 2006.239.07:31:11.04#ibcon#about to read 5, iclass 31, count 0 2006.239.07:31:11.04#ibcon#read 5, iclass 31, count 0 2006.239.07:31:11.04#ibcon#about to read 6, iclass 31, count 0 2006.239.07:31:11.04#ibcon#read 6, iclass 31, count 0 2006.239.07:31:11.04#ibcon#end of sib2, iclass 31, count 0 2006.239.07:31:11.04#ibcon#*after write, iclass 31, count 0 2006.239.07:31:11.04#ibcon#*before return 0, iclass 31, count 0 2006.239.07:31:11.04#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:31:11.04#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:31:11.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:31:11.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:31:11.04$vc4f8/vblo=2,640.99 2006.239.07:31:11.04#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:31:11.04#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:31:11.04#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:11.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:11.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:11.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:11.04#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:31:11.04#ibcon#first serial, iclass 33, count 0 2006.239.07:31:11.04#ibcon#enter sib2, iclass 33, count 0 2006.239.07:31:11.04#ibcon#flushed, iclass 33, count 0 2006.239.07:31:11.04#ibcon#about to write, iclass 33, count 0 2006.239.07:31:11.04#ibcon#wrote, iclass 33, count 0 2006.239.07:31:11.04#ibcon#about to read 3, iclass 33, count 0 2006.239.07:31:11.06#ibcon#read 3, iclass 33, count 0 2006.239.07:31:11.06#ibcon#about to read 4, iclass 33, count 0 2006.239.07:31:11.06#ibcon#read 4, iclass 33, count 0 2006.239.07:31:11.06#ibcon#about to read 5, iclass 33, count 0 2006.239.07:31:11.06#ibcon#read 5, iclass 33, count 0 2006.239.07:31:11.06#ibcon#about to read 6, iclass 33, count 0 2006.239.07:31:11.06#ibcon#read 6, iclass 33, count 0 2006.239.07:31:11.06#ibcon#end of sib2, iclass 33, count 0 2006.239.07:31:11.06#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:31:11.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:31:11.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:31:11.06#ibcon#*before write, iclass 33, count 0 2006.239.07:31:11.06#ibcon#enter sib2, iclass 33, count 0 2006.239.07:31:11.06#ibcon#flushed, iclass 33, count 0 2006.239.07:31:11.06#ibcon#about to write, iclass 33, count 0 2006.239.07:31:11.06#ibcon#wrote, iclass 33, count 0 2006.239.07:31:11.06#ibcon#about to read 3, iclass 33, count 0 2006.239.07:31:11.10#ibcon#read 3, iclass 33, count 0 2006.239.07:31:11.10#ibcon#about to read 4, iclass 33, count 0 2006.239.07:31:11.10#ibcon#read 4, iclass 33, count 0 2006.239.07:31:11.10#ibcon#about to read 5, iclass 33, count 0 2006.239.07:31:11.10#ibcon#read 5, iclass 33, count 0 2006.239.07:31:11.10#ibcon#about to read 6, iclass 33, count 0 2006.239.07:31:11.10#ibcon#read 6, iclass 33, count 0 2006.239.07:31:11.10#ibcon#end of sib2, iclass 33, count 0 2006.239.07:31:11.10#ibcon#*after write, iclass 33, count 0 2006.239.07:31:11.10#ibcon#*before return 0, iclass 33, count 0 2006.239.07:31:11.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:11.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:31:11.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:31:11.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:31:11.10$vc4f8/vb=2,4 2006.239.07:31:11.10#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:31:11.10#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:31:11.10#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:11.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:11.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:11.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:11.16#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:31:11.16#ibcon#first serial, iclass 35, count 2 2006.239.07:31:11.16#ibcon#enter sib2, iclass 35, count 2 2006.239.07:31:11.16#ibcon#flushed, iclass 35, count 2 2006.239.07:31:11.16#ibcon#about to write, iclass 35, count 2 2006.239.07:31:11.16#ibcon#wrote, iclass 35, count 2 2006.239.07:31:11.16#ibcon#about to read 3, iclass 35, count 2 2006.239.07:31:11.18#ibcon#read 3, iclass 35, count 2 2006.239.07:31:11.18#ibcon#about to read 4, iclass 35, count 2 2006.239.07:31:11.18#ibcon#read 4, iclass 35, count 2 2006.239.07:31:11.18#ibcon#about to read 5, iclass 35, count 2 2006.239.07:31:11.18#ibcon#read 5, iclass 35, count 2 2006.239.07:31:11.18#ibcon#about to read 6, iclass 35, count 2 2006.239.07:31:11.18#ibcon#read 6, iclass 35, count 2 2006.239.07:31:11.18#ibcon#end of sib2, iclass 35, count 2 2006.239.07:31:11.18#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:31:11.18#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:31:11.18#ibcon#[27=AT02-04\r\n] 2006.239.07:31:11.18#ibcon#*before write, iclass 35, count 2 2006.239.07:31:11.18#ibcon#enter sib2, iclass 35, count 2 2006.239.07:31:11.18#ibcon#flushed, iclass 35, count 2 2006.239.07:31:11.18#ibcon#about to write, iclass 35, count 2 2006.239.07:31:11.18#ibcon#wrote, iclass 35, count 2 2006.239.07:31:11.18#ibcon#about to read 3, iclass 35, count 2 2006.239.07:31:11.21#ibcon#read 3, iclass 35, count 2 2006.239.07:31:11.21#ibcon#about to read 4, iclass 35, count 2 2006.239.07:31:11.21#ibcon#read 4, iclass 35, count 2 2006.239.07:31:11.21#ibcon#about to read 5, iclass 35, count 2 2006.239.07:31:11.21#ibcon#read 5, iclass 35, count 2 2006.239.07:31:11.21#ibcon#about to read 6, iclass 35, count 2 2006.239.07:31:11.21#ibcon#read 6, iclass 35, count 2 2006.239.07:31:11.21#ibcon#end of sib2, iclass 35, count 2 2006.239.07:31:11.21#ibcon#*after write, iclass 35, count 2 2006.239.07:31:11.21#ibcon#*before return 0, iclass 35, count 2 2006.239.07:31:11.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:11.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:31:11.21#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:31:11.21#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:11.21#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:11.33#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:11.33#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:11.33#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:31:11.33#ibcon#first serial, iclass 35, count 0 2006.239.07:31:11.33#ibcon#enter sib2, iclass 35, count 0 2006.239.07:31:11.33#ibcon#flushed, iclass 35, count 0 2006.239.07:31:11.33#ibcon#about to write, iclass 35, count 0 2006.239.07:31:11.33#ibcon#wrote, iclass 35, count 0 2006.239.07:31:11.33#ibcon#about to read 3, iclass 35, count 0 2006.239.07:31:11.35#ibcon#read 3, iclass 35, count 0 2006.239.07:31:11.35#ibcon#about to read 4, iclass 35, count 0 2006.239.07:31:11.35#ibcon#read 4, iclass 35, count 0 2006.239.07:31:11.35#ibcon#about to read 5, iclass 35, count 0 2006.239.07:31:11.35#ibcon#read 5, iclass 35, count 0 2006.239.07:31:11.35#ibcon#about to read 6, iclass 35, count 0 2006.239.07:31:11.35#ibcon#read 6, iclass 35, count 0 2006.239.07:31:11.35#ibcon#end of sib2, iclass 35, count 0 2006.239.07:31:11.35#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:31:11.35#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:31:11.35#ibcon#[27=USB\r\n] 2006.239.07:31:11.35#ibcon#*before write, iclass 35, count 0 2006.239.07:31:11.35#ibcon#enter sib2, iclass 35, count 0 2006.239.07:31:11.35#ibcon#flushed, iclass 35, count 0 2006.239.07:31:11.35#ibcon#about to write, iclass 35, count 0 2006.239.07:31:11.35#ibcon#wrote, iclass 35, count 0 2006.239.07:31:11.35#ibcon#about to read 3, iclass 35, count 0 2006.239.07:31:11.38#ibcon#read 3, iclass 35, count 0 2006.239.07:31:11.38#ibcon#about to read 4, iclass 35, count 0 2006.239.07:31:11.38#ibcon#read 4, iclass 35, count 0 2006.239.07:31:11.38#ibcon#about to read 5, iclass 35, count 0 2006.239.07:31:11.38#ibcon#read 5, iclass 35, count 0 2006.239.07:31:11.38#ibcon#about to read 6, iclass 35, count 0 2006.239.07:31:11.38#ibcon#read 6, iclass 35, count 0 2006.239.07:31:11.38#ibcon#end of sib2, iclass 35, count 0 2006.239.07:31:11.38#ibcon#*after write, iclass 35, count 0 2006.239.07:31:11.38#ibcon#*before return 0, iclass 35, count 0 2006.239.07:31:11.38#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:11.38#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:31:11.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:31:11.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:31:11.38$vc4f8/vblo=3,656.99 2006.239.07:31:11.38#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:31:11.38#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:31:11.38#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:11.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:11.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:11.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:11.38#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:31:11.38#ibcon#first serial, iclass 37, count 0 2006.239.07:31:11.38#ibcon#enter sib2, iclass 37, count 0 2006.239.07:31:11.38#ibcon#flushed, iclass 37, count 0 2006.239.07:31:11.38#ibcon#about to write, iclass 37, count 0 2006.239.07:31:11.38#ibcon#wrote, iclass 37, count 0 2006.239.07:31:11.38#ibcon#about to read 3, iclass 37, count 0 2006.239.07:31:11.40#ibcon#read 3, iclass 37, count 0 2006.239.07:31:11.40#ibcon#about to read 4, iclass 37, count 0 2006.239.07:31:11.40#ibcon#read 4, iclass 37, count 0 2006.239.07:31:11.40#ibcon#about to read 5, iclass 37, count 0 2006.239.07:31:11.40#ibcon#read 5, iclass 37, count 0 2006.239.07:31:11.40#ibcon#about to read 6, iclass 37, count 0 2006.239.07:31:11.40#ibcon#read 6, iclass 37, count 0 2006.239.07:31:11.40#ibcon#end of sib2, iclass 37, count 0 2006.239.07:31:11.40#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:31:11.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:31:11.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:31:11.40#ibcon#*before write, iclass 37, count 0 2006.239.07:31:11.40#ibcon#enter sib2, iclass 37, count 0 2006.239.07:31:11.40#ibcon#flushed, iclass 37, count 0 2006.239.07:31:11.40#ibcon#about to write, iclass 37, count 0 2006.239.07:31:11.40#ibcon#wrote, iclass 37, count 0 2006.239.07:31:11.40#ibcon#about to read 3, iclass 37, count 0 2006.239.07:31:11.44#ibcon#read 3, iclass 37, count 0 2006.239.07:31:11.44#ibcon#about to read 4, iclass 37, count 0 2006.239.07:31:11.44#ibcon#read 4, iclass 37, count 0 2006.239.07:31:11.44#ibcon#about to read 5, iclass 37, count 0 2006.239.07:31:11.44#ibcon#read 5, iclass 37, count 0 2006.239.07:31:11.44#ibcon#about to read 6, iclass 37, count 0 2006.239.07:31:11.44#ibcon#read 6, iclass 37, count 0 2006.239.07:31:11.44#ibcon#end of sib2, iclass 37, count 0 2006.239.07:31:11.44#ibcon#*after write, iclass 37, count 0 2006.239.07:31:11.44#ibcon#*before return 0, iclass 37, count 0 2006.239.07:31:11.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:11.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:31:11.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:31:11.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:31:11.44$vc4f8/vb=3,4 2006.239.07:31:11.44#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:31:11.44#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:31:11.44#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:11.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:11.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:11.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:11.50#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:31:11.50#ibcon#first serial, iclass 39, count 2 2006.239.07:31:11.50#ibcon#enter sib2, iclass 39, count 2 2006.239.07:31:11.50#ibcon#flushed, iclass 39, count 2 2006.239.07:31:11.50#ibcon#about to write, iclass 39, count 2 2006.239.07:31:11.50#ibcon#wrote, iclass 39, count 2 2006.239.07:31:11.50#ibcon#about to read 3, iclass 39, count 2 2006.239.07:31:11.52#ibcon#read 3, iclass 39, count 2 2006.239.07:31:11.52#ibcon#about to read 4, iclass 39, count 2 2006.239.07:31:11.52#ibcon#read 4, iclass 39, count 2 2006.239.07:31:11.52#ibcon#about to read 5, iclass 39, count 2 2006.239.07:31:11.52#ibcon#read 5, iclass 39, count 2 2006.239.07:31:11.52#ibcon#about to read 6, iclass 39, count 2 2006.239.07:31:11.52#ibcon#read 6, iclass 39, count 2 2006.239.07:31:11.52#ibcon#end of sib2, iclass 39, count 2 2006.239.07:31:11.52#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:31:11.52#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:31:11.52#ibcon#[27=AT03-04\r\n] 2006.239.07:31:11.52#ibcon#*before write, iclass 39, count 2 2006.239.07:31:11.52#ibcon#enter sib2, iclass 39, count 2 2006.239.07:31:11.52#ibcon#flushed, iclass 39, count 2 2006.239.07:31:11.52#ibcon#about to write, iclass 39, count 2 2006.239.07:31:11.52#ibcon#wrote, iclass 39, count 2 2006.239.07:31:11.52#ibcon#about to read 3, iclass 39, count 2 2006.239.07:31:11.55#ibcon#read 3, iclass 39, count 2 2006.239.07:31:11.55#ibcon#about to read 4, iclass 39, count 2 2006.239.07:31:11.55#ibcon#read 4, iclass 39, count 2 2006.239.07:31:11.55#ibcon#about to read 5, iclass 39, count 2 2006.239.07:31:11.55#ibcon#read 5, iclass 39, count 2 2006.239.07:31:11.55#ibcon#about to read 6, iclass 39, count 2 2006.239.07:31:11.55#ibcon#read 6, iclass 39, count 2 2006.239.07:31:11.55#ibcon#end of sib2, iclass 39, count 2 2006.239.07:31:11.55#ibcon#*after write, iclass 39, count 2 2006.239.07:31:11.55#ibcon#*before return 0, iclass 39, count 2 2006.239.07:31:11.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:11.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:31:11.55#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:31:11.55#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:11.55#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:11.67#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:11.67#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:11.67#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:31:11.67#ibcon#first serial, iclass 39, count 0 2006.239.07:31:11.67#ibcon#enter sib2, iclass 39, count 0 2006.239.07:31:11.67#ibcon#flushed, iclass 39, count 0 2006.239.07:31:11.67#ibcon#about to write, iclass 39, count 0 2006.239.07:31:11.67#ibcon#wrote, iclass 39, count 0 2006.239.07:31:11.67#ibcon#about to read 3, iclass 39, count 0 2006.239.07:31:11.69#ibcon#read 3, iclass 39, count 0 2006.239.07:31:11.69#ibcon#about to read 4, iclass 39, count 0 2006.239.07:31:11.69#ibcon#read 4, iclass 39, count 0 2006.239.07:31:11.69#ibcon#about to read 5, iclass 39, count 0 2006.239.07:31:11.69#ibcon#read 5, iclass 39, count 0 2006.239.07:31:11.69#ibcon#about to read 6, iclass 39, count 0 2006.239.07:31:11.69#ibcon#read 6, iclass 39, count 0 2006.239.07:31:11.69#ibcon#end of sib2, iclass 39, count 0 2006.239.07:31:11.69#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:31:11.69#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:31:11.69#ibcon#[27=USB\r\n] 2006.239.07:31:11.69#ibcon#*before write, iclass 39, count 0 2006.239.07:31:11.69#ibcon#enter sib2, iclass 39, count 0 2006.239.07:31:11.69#ibcon#flushed, iclass 39, count 0 2006.239.07:31:11.69#ibcon#about to write, iclass 39, count 0 2006.239.07:31:11.69#ibcon#wrote, iclass 39, count 0 2006.239.07:31:11.69#ibcon#about to read 3, iclass 39, count 0 2006.239.07:31:11.72#ibcon#read 3, iclass 39, count 0 2006.239.07:31:11.72#ibcon#about to read 4, iclass 39, count 0 2006.239.07:31:11.72#ibcon#read 4, iclass 39, count 0 2006.239.07:31:11.72#ibcon#about to read 5, iclass 39, count 0 2006.239.07:31:11.72#ibcon#read 5, iclass 39, count 0 2006.239.07:31:11.72#ibcon#about to read 6, iclass 39, count 0 2006.239.07:31:11.72#ibcon#read 6, iclass 39, count 0 2006.239.07:31:11.72#ibcon#end of sib2, iclass 39, count 0 2006.239.07:31:11.72#ibcon#*after write, iclass 39, count 0 2006.239.07:31:11.72#ibcon#*before return 0, iclass 39, count 0 2006.239.07:31:11.72#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:11.72#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:31:11.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:31:11.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:31:11.72$vc4f8/vblo=4,712.99 2006.239.07:31:11.72#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:31:11.72#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:31:11.72#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:11.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:11.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:11.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:11.72#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:31:11.72#ibcon#first serial, iclass 3, count 0 2006.239.07:31:11.72#ibcon#enter sib2, iclass 3, count 0 2006.239.07:31:11.72#ibcon#flushed, iclass 3, count 0 2006.239.07:31:11.72#ibcon#about to write, iclass 3, count 0 2006.239.07:31:11.72#ibcon#wrote, iclass 3, count 0 2006.239.07:31:11.72#ibcon#about to read 3, iclass 3, count 0 2006.239.07:31:11.74#ibcon#read 3, iclass 3, count 0 2006.239.07:31:11.74#ibcon#about to read 4, iclass 3, count 0 2006.239.07:31:11.74#ibcon#read 4, iclass 3, count 0 2006.239.07:31:11.74#ibcon#about to read 5, iclass 3, count 0 2006.239.07:31:11.74#ibcon#read 5, iclass 3, count 0 2006.239.07:31:11.74#ibcon#about to read 6, iclass 3, count 0 2006.239.07:31:11.74#ibcon#read 6, iclass 3, count 0 2006.239.07:31:11.74#ibcon#end of sib2, iclass 3, count 0 2006.239.07:31:11.74#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:31:11.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:31:11.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:31:11.74#ibcon#*before write, iclass 3, count 0 2006.239.07:31:11.74#ibcon#enter sib2, iclass 3, count 0 2006.239.07:31:11.74#ibcon#flushed, iclass 3, count 0 2006.239.07:31:11.74#ibcon#about to write, iclass 3, count 0 2006.239.07:31:11.74#ibcon#wrote, iclass 3, count 0 2006.239.07:31:11.74#ibcon#about to read 3, iclass 3, count 0 2006.239.07:31:11.78#ibcon#read 3, iclass 3, count 0 2006.239.07:31:11.78#ibcon#about to read 4, iclass 3, count 0 2006.239.07:31:11.78#ibcon#read 4, iclass 3, count 0 2006.239.07:31:11.78#ibcon#about to read 5, iclass 3, count 0 2006.239.07:31:11.78#ibcon#read 5, iclass 3, count 0 2006.239.07:31:11.78#ibcon#about to read 6, iclass 3, count 0 2006.239.07:31:11.78#ibcon#read 6, iclass 3, count 0 2006.239.07:31:11.78#ibcon#end of sib2, iclass 3, count 0 2006.239.07:31:11.78#ibcon#*after write, iclass 3, count 0 2006.239.07:31:11.78#ibcon#*before return 0, iclass 3, count 0 2006.239.07:31:11.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:11.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:31:11.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:31:11.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:31:11.78$vc4f8/vb=4,4 2006.239.07:31:11.78#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.07:31:11.78#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.07:31:11.78#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:11.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:11.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:11.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:11.84#ibcon#enter wrdev, iclass 5, count 2 2006.239.07:31:11.84#ibcon#first serial, iclass 5, count 2 2006.239.07:31:11.84#ibcon#enter sib2, iclass 5, count 2 2006.239.07:31:11.84#ibcon#flushed, iclass 5, count 2 2006.239.07:31:11.84#ibcon#about to write, iclass 5, count 2 2006.239.07:31:11.84#ibcon#wrote, iclass 5, count 2 2006.239.07:31:11.84#ibcon#about to read 3, iclass 5, count 2 2006.239.07:31:11.86#ibcon#read 3, iclass 5, count 2 2006.239.07:31:11.86#ibcon#about to read 4, iclass 5, count 2 2006.239.07:31:11.86#ibcon#read 4, iclass 5, count 2 2006.239.07:31:11.86#ibcon#about to read 5, iclass 5, count 2 2006.239.07:31:11.86#ibcon#read 5, iclass 5, count 2 2006.239.07:31:11.86#ibcon#about to read 6, iclass 5, count 2 2006.239.07:31:11.86#ibcon#read 6, iclass 5, count 2 2006.239.07:31:11.86#ibcon#end of sib2, iclass 5, count 2 2006.239.07:31:11.86#ibcon#*mode == 0, iclass 5, count 2 2006.239.07:31:11.86#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.07:31:11.86#ibcon#[27=AT04-04\r\n] 2006.239.07:31:11.86#ibcon#*before write, iclass 5, count 2 2006.239.07:31:11.86#ibcon#enter sib2, iclass 5, count 2 2006.239.07:31:11.86#ibcon#flushed, iclass 5, count 2 2006.239.07:31:11.86#ibcon#about to write, iclass 5, count 2 2006.239.07:31:11.86#ibcon#wrote, iclass 5, count 2 2006.239.07:31:11.86#ibcon#about to read 3, iclass 5, count 2 2006.239.07:31:11.90#ibcon#read 3, iclass 5, count 2 2006.239.07:31:11.90#ibcon#about to read 4, iclass 5, count 2 2006.239.07:31:11.90#ibcon#read 4, iclass 5, count 2 2006.239.07:31:11.90#ibcon#about to read 5, iclass 5, count 2 2006.239.07:31:11.90#ibcon#read 5, iclass 5, count 2 2006.239.07:31:11.90#ibcon#about to read 6, iclass 5, count 2 2006.239.07:31:11.90#ibcon#read 6, iclass 5, count 2 2006.239.07:31:11.90#ibcon#end of sib2, iclass 5, count 2 2006.239.07:31:11.90#ibcon#*after write, iclass 5, count 2 2006.239.07:31:11.90#ibcon#*before return 0, iclass 5, count 2 2006.239.07:31:11.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:11.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:31:11.90#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.07:31:11.90#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:11.90#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:12.02#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:12.02#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:12.02#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:31:12.02#ibcon#first serial, iclass 5, count 0 2006.239.07:31:12.02#ibcon#enter sib2, iclass 5, count 0 2006.239.07:31:12.02#ibcon#flushed, iclass 5, count 0 2006.239.07:31:12.02#ibcon#about to write, iclass 5, count 0 2006.239.07:31:12.02#ibcon#wrote, iclass 5, count 0 2006.239.07:31:12.02#ibcon#about to read 3, iclass 5, count 0 2006.239.07:31:12.04#ibcon#read 3, iclass 5, count 0 2006.239.07:31:12.04#ibcon#about to read 4, iclass 5, count 0 2006.239.07:31:12.04#ibcon#read 4, iclass 5, count 0 2006.239.07:31:12.04#ibcon#about to read 5, iclass 5, count 0 2006.239.07:31:12.04#ibcon#read 5, iclass 5, count 0 2006.239.07:31:12.04#ibcon#about to read 6, iclass 5, count 0 2006.239.07:31:12.04#ibcon#read 6, iclass 5, count 0 2006.239.07:31:12.04#ibcon#end of sib2, iclass 5, count 0 2006.239.07:31:12.04#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:31:12.04#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:31:12.04#ibcon#[27=USB\r\n] 2006.239.07:31:12.04#ibcon#*before write, iclass 5, count 0 2006.239.07:31:12.04#ibcon#enter sib2, iclass 5, count 0 2006.239.07:31:12.04#ibcon#flushed, iclass 5, count 0 2006.239.07:31:12.04#ibcon#about to write, iclass 5, count 0 2006.239.07:31:12.04#ibcon#wrote, iclass 5, count 0 2006.239.07:31:12.04#ibcon#about to read 3, iclass 5, count 0 2006.239.07:31:12.07#ibcon#read 3, iclass 5, count 0 2006.239.07:31:12.07#ibcon#about to read 4, iclass 5, count 0 2006.239.07:31:12.07#ibcon#read 4, iclass 5, count 0 2006.239.07:31:12.07#ibcon#about to read 5, iclass 5, count 0 2006.239.07:31:12.07#ibcon#read 5, iclass 5, count 0 2006.239.07:31:12.07#ibcon#about to read 6, iclass 5, count 0 2006.239.07:31:12.07#ibcon#read 6, iclass 5, count 0 2006.239.07:31:12.07#ibcon#end of sib2, iclass 5, count 0 2006.239.07:31:12.07#ibcon#*after write, iclass 5, count 0 2006.239.07:31:12.07#ibcon#*before return 0, iclass 5, count 0 2006.239.07:31:12.07#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:12.07#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:31:12.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:31:12.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:31:12.07$vc4f8/vblo=5,744.99 2006.239.07:31:12.07#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:31:12.07#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:31:12.07#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:12.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:12.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:12.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:12.07#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:31:12.07#ibcon#first serial, iclass 7, count 0 2006.239.07:31:12.07#ibcon#enter sib2, iclass 7, count 0 2006.239.07:31:12.07#ibcon#flushed, iclass 7, count 0 2006.239.07:31:12.07#ibcon#about to write, iclass 7, count 0 2006.239.07:31:12.07#ibcon#wrote, iclass 7, count 0 2006.239.07:31:12.07#ibcon#about to read 3, iclass 7, count 0 2006.239.07:31:12.09#ibcon#read 3, iclass 7, count 0 2006.239.07:31:12.09#ibcon#about to read 4, iclass 7, count 0 2006.239.07:31:12.09#ibcon#read 4, iclass 7, count 0 2006.239.07:31:12.09#ibcon#about to read 5, iclass 7, count 0 2006.239.07:31:12.09#ibcon#read 5, iclass 7, count 0 2006.239.07:31:12.09#ibcon#about to read 6, iclass 7, count 0 2006.239.07:31:12.09#ibcon#read 6, iclass 7, count 0 2006.239.07:31:12.09#ibcon#end of sib2, iclass 7, count 0 2006.239.07:31:12.09#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:31:12.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:31:12.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:31:12.09#ibcon#*before write, iclass 7, count 0 2006.239.07:31:12.09#ibcon#enter sib2, iclass 7, count 0 2006.239.07:31:12.09#ibcon#flushed, iclass 7, count 0 2006.239.07:31:12.09#ibcon#about to write, iclass 7, count 0 2006.239.07:31:12.09#ibcon#wrote, iclass 7, count 0 2006.239.07:31:12.09#ibcon#about to read 3, iclass 7, count 0 2006.239.07:31:12.13#ibcon#read 3, iclass 7, count 0 2006.239.07:31:12.13#ibcon#about to read 4, iclass 7, count 0 2006.239.07:31:12.13#ibcon#read 4, iclass 7, count 0 2006.239.07:31:12.13#ibcon#about to read 5, iclass 7, count 0 2006.239.07:31:12.13#ibcon#read 5, iclass 7, count 0 2006.239.07:31:12.13#ibcon#about to read 6, iclass 7, count 0 2006.239.07:31:12.13#ibcon#read 6, iclass 7, count 0 2006.239.07:31:12.13#ibcon#end of sib2, iclass 7, count 0 2006.239.07:31:12.13#ibcon#*after write, iclass 7, count 0 2006.239.07:31:12.13#ibcon#*before return 0, iclass 7, count 0 2006.239.07:31:12.13#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:12.13#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:31:12.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:31:12.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:31:12.13$vc4f8/vb=5,4 2006.239.07:31:12.13#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.07:31:12.13#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.07:31:12.13#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:12.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:12.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:12.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:12.19#ibcon#enter wrdev, iclass 11, count 2 2006.239.07:31:12.19#ibcon#first serial, iclass 11, count 2 2006.239.07:31:12.19#ibcon#enter sib2, iclass 11, count 2 2006.239.07:31:12.19#ibcon#flushed, iclass 11, count 2 2006.239.07:31:12.19#ibcon#about to write, iclass 11, count 2 2006.239.07:31:12.19#ibcon#wrote, iclass 11, count 2 2006.239.07:31:12.19#ibcon#about to read 3, iclass 11, count 2 2006.239.07:31:12.21#ibcon#read 3, iclass 11, count 2 2006.239.07:31:12.21#ibcon#about to read 4, iclass 11, count 2 2006.239.07:31:12.21#ibcon#read 4, iclass 11, count 2 2006.239.07:31:12.21#ibcon#about to read 5, iclass 11, count 2 2006.239.07:31:12.21#ibcon#read 5, iclass 11, count 2 2006.239.07:31:12.21#ibcon#about to read 6, iclass 11, count 2 2006.239.07:31:12.21#ibcon#read 6, iclass 11, count 2 2006.239.07:31:12.21#ibcon#end of sib2, iclass 11, count 2 2006.239.07:31:12.21#ibcon#*mode == 0, iclass 11, count 2 2006.239.07:31:12.21#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.07:31:12.21#ibcon#[27=AT05-04\r\n] 2006.239.07:31:12.21#ibcon#*before write, iclass 11, count 2 2006.239.07:31:12.21#ibcon#enter sib2, iclass 11, count 2 2006.239.07:31:12.21#ibcon#flushed, iclass 11, count 2 2006.239.07:31:12.21#ibcon#about to write, iclass 11, count 2 2006.239.07:31:12.21#ibcon#wrote, iclass 11, count 2 2006.239.07:31:12.21#ibcon#about to read 3, iclass 11, count 2 2006.239.07:31:12.24#ibcon#read 3, iclass 11, count 2 2006.239.07:31:12.24#ibcon#about to read 4, iclass 11, count 2 2006.239.07:31:12.24#ibcon#read 4, iclass 11, count 2 2006.239.07:31:12.24#ibcon#about to read 5, iclass 11, count 2 2006.239.07:31:12.24#ibcon#read 5, iclass 11, count 2 2006.239.07:31:12.24#ibcon#about to read 6, iclass 11, count 2 2006.239.07:31:12.24#ibcon#read 6, iclass 11, count 2 2006.239.07:31:12.24#ibcon#end of sib2, iclass 11, count 2 2006.239.07:31:12.24#ibcon#*after write, iclass 11, count 2 2006.239.07:31:12.24#ibcon#*before return 0, iclass 11, count 2 2006.239.07:31:12.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:12.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:31:12.24#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.07:31:12.24#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:12.24#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:12.36#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:12.36#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:12.36#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:31:12.36#ibcon#first serial, iclass 11, count 0 2006.239.07:31:12.36#ibcon#enter sib2, iclass 11, count 0 2006.239.07:31:12.36#ibcon#flushed, iclass 11, count 0 2006.239.07:31:12.36#ibcon#about to write, iclass 11, count 0 2006.239.07:31:12.36#ibcon#wrote, iclass 11, count 0 2006.239.07:31:12.36#ibcon#about to read 3, iclass 11, count 0 2006.239.07:31:12.38#ibcon#read 3, iclass 11, count 0 2006.239.07:31:12.38#ibcon#about to read 4, iclass 11, count 0 2006.239.07:31:12.38#ibcon#read 4, iclass 11, count 0 2006.239.07:31:12.38#ibcon#about to read 5, iclass 11, count 0 2006.239.07:31:12.38#ibcon#read 5, iclass 11, count 0 2006.239.07:31:12.38#ibcon#about to read 6, iclass 11, count 0 2006.239.07:31:12.38#ibcon#read 6, iclass 11, count 0 2006.239.07:31:12.38#ibcon#end of sib2, iclass 11, count 0 2006.239.07:31:12.38#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:31:12.38#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:31:12.38#ibcon#[27=USB\r\n] 2006.239.07:31:12.38#ibcon#*before write, iclass 11, count 0 2006.239.07:31:12.38#ibcon#enter sib2, iclass 11, count 0 2006.239.07:31:12.38#ibcon#flushed, iclass 11, count 0 2006.239.07:31:12.38#ibcon#about to write, iclass 11, count 0 2006.239.07:31:12.38#ibcon#wrote, iclass 11, count 0 2006.239.07:31:12.38#ibcon#about to read 3, iclass 11, count 0 2006.239.07:31:12.41#ibcon#read 3, iclass 11, count 0 2006.239.07:31:12.41#ibcon#about to read 4, iclass 11, count 0 2006.239.07:31:12.41#ibcon#read 4, iclass 11, count 0 2006.239.07:31:12.41#ibcon#about to read 5, iclass 11, count 0 2006.239.07:31:12.41#ibcon#read 5, iclass 11, count 0 2006.239.07:31:12.41#ibcon#about to read 6, iclass 11, count 0 2006.239.07:31:12.41#ibcon#read 6, iclass 11, count 0 2006.239.07:31:12.41#ibcon#end of sib2, iclass 11, count 0 2006.239.07:31:12.41#ibcon#*after write, iclass 11, count 0 2006.239.07:31:12.41#ibcon#*before return 0, iclass 11, count 0 2006.239.07:31:12.41#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:12.41#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:31:12.41#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:31:12.41#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:31:12.41$vc4f8/vblo=6,752.99 2006.239.07:31:12.41#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.07:31:12.41#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.07:31:12.41#ibcon#ireg 17 cls_cnt 0 2006.239.07:31:12.41#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:12.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:12.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:12.41#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:31:12.41#ibcon#first serial, iclass 13, count 0 2006.239.07:31:12.41#ibcon#enter sib2, iclass 13, count 0 2006.239.07:31:12.41#ibcon#flushed, iclass 13, count 0 2006.239.07:31:12.41#ibcon#about to write, iclass 13, count 0 2006.239.07:31:12.41#ibcon#wrote, iclass 13, count 0 2006.239.07:31:12.41#ibcon#about to read 3, iclass 13, count 0 2006.239.07:31:12.43#ibcon#read 3, iclass 13, count 0 2006.239.07:31:12.43#ibcon#about to read 4, iclass 13, count 0 2006.239.07:31:12.43#ibcon#read 4, iclass 13, count 0 2006.239.07:31:12.43#ibcon#about to read 5, iclass 13, count 0 2006.239.07:31:12.43#ibcon#read 5, iclass 13, count 0 2006.239.07:31:12.43#ibcon#about to read 6, iclass 13, count 0 2006.239.07:31:12.43#ibcon#read 6, iclass 13, count 0 2006.239.07:31:12.43#ibcon#end of sib2, iclass 13, count 0 2006.239.07:31:12.43#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:31:12.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:31:12.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:31:12.43#ibcon#*before write, iclass 13, count 0 2006.239.07:31:12.43#ibcon#enter sib2, iclass 13, count 0 2006.239.07:31:12.43#ibcon#flushed, iclass 13, count 0 2006.239.07:31:12.43#ibcon#about to write, iclass 13, count 0 2006.239.07:31:12.43#ibcon#wrote, iclass 13, count 0 2006.239.07:31:12.43#ibcon#about to read 3, iclass 13, count 0 2006.239.07:31:12.47#ibcon#read 3, iclass 13, count 0 2006.239.07:31:12.47#ibcon#about to read 4, iclass 13, count 0 2006.239.07:31:12.47#ibcon#read 4, iclass 13, count 0 2006.239.07:31:12.47#ibcon#about to read 5, iclass 13, count 0 2006.239.07:31:12.47#ibcon#read 5, iclass 13, count 0 2006.239.07:31:12.47#ibcon#about to read 6, iclass 13, count 0 2006.239.07:31:12.47#ibcon#read 6, iclass 13, count 0 2006.239.07:31:12.47#ibcon#end of sib2, iclass 13, count 0 2006.239.07:31:12.47#ibcon#*after write, iclass 13, count 0 2006.239.07:31:12.47#ibcon#*before return 0, iclass 13, count 0 2006.239.07:31:12.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:12.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:31:12.47#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:31:12.47#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:31:12.47$vc4f8/vb=6,4 2006.239.07:31:12.47#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.07:31:12.47#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.07:31:12.47#ibcon#ireg 11 cls_cnt 2 2006.239.07:31:12.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:12.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:12.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:12.53#ibcon#enter wrdev, iclass 15, count 2 2006.239.07:31:12.53#ibcon#first serial, iclass 15, count 2 2006.239.07:31:12.53#ibcon#enter sib2, iclass 15, count 2 2006.239.07:31:12.53#ibcon#flushed, iclass 15, count 2 2006.239.07:31:12.53#ibcon#about to write, iclass 15, count 2 2006.239.07:31:12.53#ibcon#wrote, iclass 15, count 2 2006.239.07:31:12.53#ibcon#about to read 3, iclass 15, count 2 2006.239.07:31:12.55#ibcon#read 3, iclass 15, count 2 2006.239.07:31:12.55#ibcon#about to read 4, iclass 15, count 2 2006.239.07:31:12.55#ibcon#read 4, iclass 15, count 2 2006.239.07:31:12.55#ibcon#about to read 5, iclass 15, count 2 2006.239.07:31:12.55#ibcon#read 5, iclass 15, count 2 2006.239.07:31:12.55#ibcon#about to read 6, iclass 15, count 2 2006.239.07:31:12.55#ibcon#read 6, iclass 15, count 2 2006.239.07:31:12.55#ibcon#end of sib2, iclass 15, count 2 2006.239.07:31:12.55#ibcon#*mode == 0, iclass 15, count 2 2006.239.07:31:12.55#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.07:31:12.55#ibcon#[27=AT06-04\r\n] 2006.239.07:31:12.55#ibcon#*before write, iclass 15, count 2 2006.239.07:31:12.55#ibcon#enter sib2, iclass 15, count 2 2006.239.07:31:12.55#ibcon#flushed, iclass 15, count 2 2006.239.07:31:12.55#ibcon#about to write, iclass 15, count 2 2006.239.07:31:12.55#ibcon#wrote, iclass 15, count 2 2006.239.07:31:12.55#ibcon#about to read 3, iclass 15, count 2 2006.239.07:31:12.58#ibcon#read 3, iclass 15, count 2 2006.239.07:31:12.58#ibcon#about to read 4, iclass 15, count 2 2006.239.07:31:12.58#ibcon#read 4, iclass 15, count 2 2006.239.07:31:12.58#ibcon#about to read 5, iclass 15, count 2 2006.239.07:31:12.58#ibcon#read 5, iclass 15, count 2 2006.239.07:31:12.58#ibcon#about to read 6, iclass 15, count 2 2006.239.07:31:12.58#ibcon#read 6, iclass 15, count 2 2006.239.07:31:12.58#ibcon#end of sib2, iclass 15, count 2 2006.239.07:31:12.58#ibcon#*after write, iclass 15, count 2 2006.239.07:31:12.58#ibcon#*before return 0, iclass 15, count 2 2006.239.07:31:12.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:12.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:31:12.58#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.07:31:12.58#ibcon#ireg 7 cls_cnt 0 2006.239.07:31:12.58#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:12.70#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:12.70#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:12.70#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:31:12.70#ibcon#first serial, iclass 15, count 0 2006.239.07:31:12.70#ibcon#enter sib2, iclass 15, count 0 2006.239.07:31:12.70#ibcon#flushed, iclass 15, count 0 2006.239.07:31:12.70#ibcon#about to write, iclass 15, count 0 2006.239.07:31:12.70#ibcon#wrote, iclass 15, count 0 2006.239.07:31:12.70#ibcon#about to read 3, iclass 15, count 0 2006.239.07:31:12.72#ibcon#read 3, iclass 15, count 0 2006.239.07:31:12.72#ibcon#about to read 4, iclass 15, count 0 2006.239.07:31:12.72#ibcon#read 4, iclass 15, count 0 2006.239.07:31:12.72#ibcon#about to read 5, iclass 15, count 0 2006.239.07:31:12.72#ibcon#read 5, iclass 15, count 0 2006.239.07:31:12.72#ibcon#about to read 6, iclass 15, count 0 2006.239.07:31:12.72#ibcon#read 6, iclass 15, count 0 2006.239.07:31:12.72#ibcon#end of sib2, iclass 15, count 0 2006.239.07:31:12.72#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:31:12.72#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:31:12.72#ibcon#[27=USB\r\n] 2006.239.07:31:12.72#ibcon#*before write, iclass 15, count 0 2006.239.07:31:12.72#ibcon#enter sib2, iclass 15, count 0 2006.239.07:31:12.72#ibcon#flushed, iclass 15, count 0 2006.239.07:31:12.72#ibcon#about to write, iclass 15, count 0 2006.239.07:31:12.72#ibcon#wrote, iclass 15, count 0 2006.239.07:31:12.72#ibcon#about to read 3, iclass 15, count 0 2006.239.07:31:12.75#ibcon#read 3, iclass 15, count 0 2006.239.07:31:12.75#ibcon#about to read 4, iclass 15, count 0 2006.239.07:31:12.75#ibcon#read 4, iclass 15, count 0 2006.239.07:31:12.75#ibcon#about to read 5, iclass 15, count 0 2006.239.07:31:12.75#ibcon#read 5, iclass 15, count 0 2006.239.07:31:12.75#ibcon#about to read 6, iclass 15, count 0 2006.239.07:31:12.75#ibcon#read 6, iclass 15, count 0 2006.239.07:31:12.75#ibcon#end of sib2, iclass 15, count 0 2006.239.07:31:12.75#ibcon#*after write, iclass 15, count 0 2006.239.07:31:12.75#ibcon#*before return 0, iclass 15, count 0 2006.239.07:31:12.75#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:12.75#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:31:12.75#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:31:12.75#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:31:12.75$vc4f8/vabw=wide 2006.239.07:31:12.75#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.07:31:12.75#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.07:31:12.75#ibcon#ireg 8 cls_cnt 0 2006.239.07:31:12.75#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:12.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:12.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:12.75#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:31:12.75#ibcon#first serial, iclass 17, count 0 2006.239.07:31:12.75#ibcon#enter sib2, iclass 17, count 0 2006.239.07:31:12.75#ibcon#flushed, iclass 17, count 0 2006.239.07:31:12.75#ibcon#about to write, iclass 17, count 0 2006.239.07:31:12.75#ibcon#wrote, iclass 17, count 0 2006.239.07:31:12.75#ibcon#about to read 3, iclass 17, count 0 2006.239.07:31:12.77#ibcon#read 3, iclass 17, count 0 2006.239.07:31:12.77#ibcon#about to read 4, iclass 17, count 0 2006.239.07:31:12.77#ibcon#read 4, iclass 17, count 0 2006.239.07:31:12.77#ibcon#about to read 5, iclass 17, count 0 2006.239.07:31:12.77#ibcon#read 5, iclass 17, count 0 2006.239.07:31:12.77#ibcon#about to read 6, iclass 17, count 0 2006.239.07:31:12.77#ibcon#read 6, iclass 17, count 0 2006.239.07:31:12.77#ibcon#end of sib2, iclass 17, count 0 2006.239.07:31:12.77#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:31:12.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:31:12.77#ibcon#[25=BW32\r\n] 2006.239.07:31:12.77#ibcon#*before write, iclass 17, count 0 2006.239.07:31:12.77#ibcon#enter sib2, iclass 17, count 0 2006.239.07:31:12.77#ibcon#flushed, iclass 17, count 0 2006.239.07:31:12.77#ibcon#about to write, iclass 17, count 0 2006.239.07:31:12.77#ibcon#wrote, iclass 17, count 0 2006.239.07:31:12.77#ibcon#about to read 3, iclass 17, count 0 2006.239.07:31:12.80#ibcon#read 3, iclass 17, count 0 2006.239.07:31:12.80#ibcon#about to read 4, iclass 17, count 0 2006.239.07:31:12.80#ibcon#read 4, iclass 17, count 0 2006.239.07:31:12.80#ibcon#about to read 5, iclass 17, count 0 2006.239.07:31:12.80#ibcon#read 5, iclass 17, count 0 2006.239.07:31:12.80#ibcon#about to read 6, iclass 17, count 0 2006.239.07:31:12.80#ibcon#read 6, iclass 17, count 0 2006.239.07:31:12.80#ibcon#end of sib2, iclass 17, count 0 2006.239.07:31:12.80#ibcon#*after write, iclass 17, count 0 2006.239.07:31:12.80#ibcon#*before return 0, iclass 17, count 0 2006.239.07:31:12.80#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:12.80#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:31:12.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:31:12.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:31:12.80$vc4f8/vbbw=wide 2006.239.07:31:12.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.07:31:12.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.07:31:12.80#ibcon#ireg 8 cls_cnt 0 2006.239.07:31:12.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:31:12.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:31:12.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:31:12.87#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:31:12.87#ibcon#first serial, iclass 19, count 0 2006.239.07:31:12.87#ibcon#enter sib2, iclass 19, count 0 2006.239.07:31:12.87#ibcon#flushed, iclass 19, count 0 2006.239.07:31:12.87#ibcon#about to write, iclass 19, count 0 2006.239.07:31:12.87#ibcon#wrote, iclass 19, count 0 2006.239.07:31:12.87#ibcon#about to read 3, iclass 19, count 0 2006.239.07:31:12.89#ibcon#read 3, iclass 19, count 0 2006.239.07:31:12.89#ibcon#about to read 4, iclass 19, count 0 2006.239.07:31:12.89#ibcon#read 4, iclass 19, count 0 2006.239.07:31:12.89#ibcon#about to read 5, iclass 19, count 0 2006.239.07:31:12.89#ibcon#read 5, iclass 19, count 0 2006.239.07:31:12.89#ibcon#about to read 6, iclass 19, count 0 2006.239.07:31:12.89#ibcon#read 6, iclass 19, count 0 2006.239.07:31:12.89#ibcon#end of sib2, iclass 19, count 0 2006.239.07:31:12.89#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:31:12.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:31:12.89#ibcon#[27=BW32\r\n] 2006.239.07:31:12.89#ibcon#*before write, iclass 19, count 0 2006.239.07:31:12.89#ibcon#enter sib2, iclass 19, count 0 2006.239.07:31:12.89#ibcon#flushed, iclass 19, count 0 2006.239.07:31:12.89#ibcon#about to write, iclass 19, count 0 2006.239.07:31:12.89#ibcon#wrote, iclass 19, count 0 2006.239.07:31:12.89#ibcon#about to read 3, iclass 19, count 0 2006.239.07:31:12.92#ibcon#read 3, iclass 19, count 0 2006.239.07:31:12.92#ibcon#about to read 4, iclass 19, count 0 2006.239.07:31:12.92#ibcon#read 4, iclass 19, count 0 2006.239.07:31:12.92#ibcon#about to read 5, iclass 19, count 0 2006.239.07:31:12.92#ibcon#read 5, iclass 19, count 0 2006.239.07:31:12.92#ibcon#about to read 6, iclass 19, count 0 2006.239.07:31:12.92#ibcon#read 6, iclass 19, count 0 2006.239.07:31:12.92#ibcon#end of sib2, iclass 19, count 0 2006.239.07:31:12.92#ibcon#*after write, iclass 19, count 0 2006.239.07:31:12.92#ibcon#*before return 0, iclass 19, count 0 2006.239.07:31:12.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:31:12.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:31:12.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:31:12.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:31:12.92$4f8m12a/ifd4f 2006.239.07:31:12.92$ifd4f/lo= 2006.239.07:31:12.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:31:12.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:31:12.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:31:12.92$ifd4f/patch= 2006.239.07:31:12.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:31:12.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:31:12.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:31:12.92$4f8m12a/"form=m,16.000,1:2 2006.239.07:31:12.92$4f8m12a/"tpicd 2006.239.07:31:12.92$4f8m12a/echo=off 2006.239.07:31:12.92$4f8m12a/xlog=off 2006.239.07:31:12.92:!2006.239.07:33:20 2006.239.07:31:44.13#trakl#Source acquired 2006.239.07:31:46.13#flagr#flagr/antenna,acquired 2006.239.07:33:20.02:preob 2006.239.07:33:21.14/onsource/TRACKING 2006.239.07:33:21.14:!2006.239.07:33:30 2006.239.07:33:30.02:data_valid=on 2006.239.07:33:30.02:midob 2006.239.07:33:31.14/onsource/TRACKING 2006.239.07:33:31.14/wx/25.39,1011.4,80 2006.239.07:33:31.33/cable/+6.4150E-03 2006.239.07:33:32.42/va/01,08,usb,yes,33,34 2006.239.07:33:32.42/va/02,07,usb,yes,33,34 2006.239.07:33:32.42/va/03,07,usb,yes,31,31 2006.239.07:33:32.42/va/04,07,usb,yes,34,37 2006.239.07:33:32.42/va/05,08,usb,yes,32,33 2006.239.07:33:32.42/va/06,07,usb,yes,34,34 2006.239.07:33:32.42/va/07,07,usb,yes,34,34 2006.239.07:33:32.42/va/08,07,usb,yes,37,36 2006.239.07:33:32.65/valo/01,532.99,yes,locked 2006.239.07:33:32.65/valo/02,572.99,yes,locked 2006.239.07:33:32.65/valo/03,672.99,yes,locked 2006.239.07:33:32.65/valo/04,832.99,yes,locked 2006.239.07:33:32.65/valo/05,652.99,yes,locked 2006.239.07:33:32.65/valo/06,772.99,yes,locked 2006.239.07:33:32.65/valo/07,832.99,yes,locked 2006.239.07:33:32.65/valo/08,852.99,yes,locked 2006.239.07:33:33.74/vb/01,04,usb,yes,31,30 2006.239.07:33:33.74/vb/02,04,usb,yes,33,35 2006.239.07:33:33.74/vb/03,04,usb,yes,30,34 2006.239.07:33:33.74/vb/04,04,usb,yes,31,31 2006.239.07:33:33.74/vb/05,04,usb,yes,29,33 2006.239.07:33:33.74/vb/06,04,usb,yes,30,33 2006.239.07:33:33.74/vb/07,04,usb,yes,32,32 2006.239.07:33:33.74/vb/08,04,usb,yes,29,33 2006.239.07:33:33.97/vblo/01,632.99,yes,locked 2006.239.07:33:33.97/vblo/02,640.99,yes,locked 2006.239.07:33:33.97/vblo/03,656.99,yes,locked 2006.239.07:33:33.97/vblo/04,712.99,yes,locked 2006.239.07:33:33.97/vblo/05,744.99,yes,locked 2006.239.07:33:33.97/vblo/06,752.99,yes,locked 2006.239.07:33:33.97/vblo/07,734.99,yes,locked 2006.239.07:33:33.98/vblo/08,744.99,yes,locked 2006.239.07:33:34.12/vabw/8 2006.239.07:33:34.27/vbbw/8 2006.239.07:33:34.36/xfe/off,on,13.7 2006.239.07:33:34.73/ifatt/23,28,28,28 2006.239.07:33:35.07/fmout-gps/S +4.34E-07 2006.239.07:33:35.12:!2006.239.07:34:30 2006.239.07:34:30.02:data_valid=off 2006.239.07:34:30.02:postob 2006.239.07:34:30.13/cable/+6.4160E-03 2006.239.07:34:30.14/wx/25.38,1011.5,81 2006.239.07:34:30.22/fmout-gps/S +4.34E-07 2006.239.07:34:30.22:scan_name=239-0735,k06239,60 2006.239.07:34:30.22:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.239.07:34:31.15#flagr#flagr/antenna,new-source 2006.239.07:34:31.15:checkk5 2006.239.07:34:31.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:34:31.91/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:34:32.29/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:34:32.67/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:34:33.04/chk_obsdata//k5ts1/T2390733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:34:33.41/chk_obsdata//k5ts2/T2390733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:34:33.78/chk_obsdata//k5ts3/T2390733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:34:34.16/chk_obsdata//k5ts4/T2390733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:34:34.85/k5log//k5ts1_log_newline 2006.239.07:34:35.55/k5log//k5ts2_log_newline 2006.239.07:34:36.24/k5log//k5ts3_log_newline 2006.239.07:34:36.92/k5log//k5ts4_log_newline 2006.239.07:34:36.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:34:36.95:4f8m12a=1 2006.239.07:34:36.95$4f8m12a/echo=on 2006.239.07:34:36.95$4f8m12a/pcalon 2006.239.07:34:36.95$pcalon/"no phase cal control is implemented here 2006.239.07:34:36.95$4f8m12a/"tpicd=stop 2006.239.07:34:36.95$4f8m12a/vc4f8 2006.239.07:34:36.95$vc4f8/valo=1,532.99 2006.239.07:34:36.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:34:36.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:34:36.95#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:36.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:36.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:36.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:36.95#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:34:36.95#ibcon#first serial, iclass 30, count 0 2006.239.07:34:36.95#ibcon#enter sib2, iclass 30, count 0 2006.239.07:34:36.95#ibcon#flushed, iclass 30, count 0 2006.239.07:34:36.95#ibcon#about to write, iclass 30, count 0 2006.239.07:34:36.95#ibcon#wrote, iclass 30, count 0 2006.239.07:34:36.95#ibcon#about to read 3, iclass 30, count 0 2006.239.07:34:36.96#ibcon#read 3, iclass 30, count 0 2006.239.07:34:36.96#ibcon#about to read 4, iclass 30, count 0 2006.239.07:34:36.96#ibcon#read 4, iclass 30, count 0 2006.239.07:34:36.96#ibcon#about to read 5, iclass 30, count 0 2006.239.07:34:36.96#ibcon#read 5, iclass 30, count 0 2006.239.07:34:36.96#ibcon#about to read 6, iclass 30, count 0 2006.239.07:34:36.96#ibcon#read 6, iclass 30, count 0 2006.239.07:34:36.96#ibcon#end of sib2, iclass 30, count 0 2006.239.07:34:36.96#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:34:36.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:34:36.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:34:36.96#ibcon#*before write, iclass 30, count 0 2006.239.07:34:36.96#ibcon#enter sib2, iclass 30, count 0 2006.239.07:34:36.96#ibcon#flushed, iclass 30, count 0 2006.239.07:34:36.96#ibcon#about to write, iclass 30, count 0 2006.239.07:34:36.96#ibcon#wrote, iclass 30, count 0 2006.239.07:34:36.96#ibcon#about to read 3, iclass 30, count 0 2006.239.07:34:37.01#ibcon#read 3, iclass 30, count 0 2006.239.07:34:37.01#ibcon#about to read 4, iclass 30, count 0 2006.239.07:34:37.01#ibcon#read 4, iclass 30, count 0 2006.239.07:34:37.01#ibcon#about to read 5, iclass 30, count 0 2006.239.07:34:37.01#ibcon#read 5, iclass 30, count 0 2006.239.07:34:37.01#ibcon#about to read 6, iclass 30, count 0 2006.239.07:34:37.01#ibcon#read 6, iclass 30, count 0 2006.239.07:34:37.01#ibcon#end of sib2, iclass 30, count 0 2006.239.07:34:37.01#ibcon#*after write, iclass 30, count 0 2006.239.07:34:37.01#ibcon#*before return 0, iclass 30, count 0 2006.239.07:34:37.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:37.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:37.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:34:37.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:34:37.02$vc4f8/va=1,8 2006.239.07:34:37.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:34:37.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:34:37.02#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:37.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:37.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:37.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:37.02#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:34:37.02#ibcon#first serial, iclass 32, count 2 2006.239.07:34:37.02#ibcon#enter sib2, iclass 32, count 2 2006.239.07:34:37.02#ibcon#flushed, iclass 32, count 2 2006.239.07:34:37.02#ibcon#about to write, iclass 32, count 2 2006.239.07:34:37.02#ibcon#wrote, iclass 32, count 2 2006.239.07:34:37.02#ibcon#about to read 3, iclass 32, count 2 2006.239.07:34:37.03#ibcon#read 3, iclass 32, count 2 2006.239.07:34:37.03#ibcon#about to read 4, iclass 32, count 2 2006.239.07:34:37.03#ibcon#read 4, iclass 32, count 2 2006.239.07:34:37.03#ibcon#about to read 5, iclass 32, count 2 2006.239.07:34:37.03#ibcon#read 5, iclass 32, count 2 2006.239.07:34:37.03#ibcon#about to read 6, iclass 32, count 2 2006.239.07:34:37.03#ibcon#read 6, iclass 32, count 2 2006.239.07:34:37.03#ibcon#end of sib2, iclass 32, count 2 2006.239.07:34:37.03#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:34:37.03#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:34:37.03#ibcon#[25=AT01-08\r\n] 2006.239.07:34:37.03#ibcon#*before write, iclass 32, count 2 2006.239.07:34:37.03#ibcon#enter sib2, iclass 32, count 2 2006.239.07:34:37.03#ibcon#flushed, iclass 32, count 2 2006.239.07:34:37.03#ibcon#about to write, iclass 32, count 2 2006.239.07:34:37.03#ibcon#wrote, iclass 32, count 2 2006.239.07:34:37.03#ibcon#about to read 3, iclass 32, count 2 2006.239.07:34:37.06#ibcon#read 3, iclass 32, count 2 2006.239.07:34:37.06#ibcon#about to read 4, iclass 32, count 2 2006.239.07:34:37.06#ibcon#read 4, iclass 32, count 2 2006.239.07:34:37.06#ibcon#about to read 5, iclass 32, count 2 2006.239.07:34:37.06#ibcon#read 5, iclass 32, count 2 2006.239.07:34:37.06#ibcon#about to read 6, iclass 32, count 2 2006.239.07:34:37.06#ibcon#read 6, iclass 32, count 2 2006.239.07:34:37.06#ibcon#end of sib2, iclass 32, count 2 2006.239.07:34:37.06#ibcon#*after write, iclass 32, count 2 2006.239.07:34:37.06#ibcon#*before return 0, iclass 32, count 2 2006.239.07:34:37.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:37.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:37.06#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:34:37.06#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:37.06#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:37.18#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:37.18#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:37.18#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:34:37.18#ibcon#first serial, iclass 32, count 0 2006.239.07:34:37.18#ibcon#enter sib2, iclass 32, count 0 2006.239.07:34:37.18#ibcon#flushed, iclass 32, count 0 2006.239.07:34:37.18#ibcon#about to write, iclass 32, count 0 2006.239.07:34:37.18#ibcon#wrote, iclass 32, count 0 2006.239.07:34:37.18#ibcon#about to read 3, iclass 32, count 0 2006.239.07:34:37.21#ibcon#read 3, iclass 32, count 0 2006.239.07:34:37.21#ibcon#about to read 4, iclass 32, count 0 2006.239.07:34:37.21#ibcon#read 4, iclass 32, count 0 2006.239.07:34:37.21#ibcon#about to read 5, iclass 32, count 0 2006.239.07:34:37.21#ibcon#read 5, iclass 32, count 0 2006.239.07:34:37.21#ibcon#about to read 6, iclass 32, count 0 2006.239.07:34:37.21#ibcon#read 6, iclass 32, count 0 2006.239.07:34:37.21#ibcon#end of sib2, iclass 32, count 0 2006.239.07:34:37.21#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:34:37.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:34:37.21#ibcon#[25=USB\r\n] 2006.239.07:34:37.21#ibcon#*before write, iclass 32, count 0 2006.239.07:34:37.21#ibcon#enter sib2, iclass 32, count 0 2006.239.07:34:37.21#ibcon#flushed, iclass 32, count 0 2006.239.07:34:37.21#ibcon#about to write, iclass 32, count 0 2006.239.07:34:37.21#ibcon#wrote, iclass 32, count 0 2006.239.07:34:37.21#ibcon#about to read 3, iclass 32, count 0 2006.239.07:34:37.23#ibcon#read 3, iclass 32, count 0 2006.239.07:34:37.23#ibcon#about to read 4, iclass 32, count 0 2006.239.07:34:37.23#ibcon#read 4, iclass 32, count 0 2006.239.07:34:37.23#ibcon#about to read 5, iclass 32, count 0 2006.239.07:34:37.23#ibcon#read 5, iclass 32, count 0 2006.239.07:34:37.23#ibcon#about to read 6, iclass 32, count 0 2006.239.07:34:37.23#ibcon#read 6, iclass 32, count 0 2006.239.07:34:37.23#ibcon#end of sib2, iclass 32, count 0 2006.239.07:34:37.23#ibcon#*after write, iclass 32, count 0 2006.239.07:34:37.23#ibcon#*before return 0, iclass 32, count 0 2006.239.07:34:37.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:37.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:37.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:34:37.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:34:37.24$vc4f8/valo=2,572.99 2006.239.07:34:37.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:34:37.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:34:37.24#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:37.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:37.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:37.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:37.24#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:34:37.24#ibcon#first serial, iclass 34, count 0 2006.239.07:34:37.24#ibcon#enter sib2, iclass 34, count 0 2006.239.07:34:37.24#ibcon#flushed, iclass 34, count 0 2006.239.07:34:37.24#ibcon#about to write, iclass 34, count 0 2006.239.07:34:37.24#ibcon#wrote, iclass 34, count 0 2006.239.07:34:37.24#ibcon#about to read 3, iclass 34, count 0 2006.239.07:34:37.25#ibcon#read 3, iclass 34, count 0 2006.239.07:34:37.25#ibcon#about to read 4, iclass 34, count 0 2006.239.07:34:37.25#ibcon#read 4, iclass 34, count 0 2006.239.07:34:37.25#ibcon#about to read 5, iclass 34, count 0 2006.239.07:34:37.25#ibcon#read 5, iclass 34, count 0 2006.239.07:34:37.25#ibcon#about to read 6, iclass 34, count 0 2006.239.07:34:37.25#ibcon#read 6, iclass 34, count 0 2006.239.07:34:37.25#ibcon#end of sib2, iclass 34, count 0 2006.239.07:34:37.25#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:34:37.25#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:34:37.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:34:37.25#ibcon#*before write, iclass 34, count 0 2006.239.07:34:37.25#ibcon#enter sib2, iclass 34, count 0 2006.239.07:34:37.25#ibcon#flushed, iclass 34, count 0 2006.239.07:34:37.25#ibcon#about to write, iclass 34, count 0 2006.239.07:34:37.25#ibcon#wrote, iclass 34, count 0 2006.239.07:34:37.25#ibcon#about to read 3, iclass 34, count 0 2006.239.07:34:37.29#ibcon#read 3, iclass 34, count 0 2006.239.07:34:37.29#ibcon#about to read 4, iclass 34, count 0 2006.239.07:34:37.29#ibcon#read 4, iclass 34, count 0 2006.239.07:34:37.29#ibcon#about to read 5, iclass 34, count 0 2006.239.07:34:37.29#ibcon#read 5, iclass 34, count 0 2006.239.07:34:37.29#ibcon#about to read 6, iclass 34, count 0 2006.239.07:34:37.29#ibcon#read 6, iclass 34, count 0 2006.239.07:34:37.29#ibcon#end of sib2, iclass 34, count 0 2006.239.07:34:37.29#ibcon#*after write, iclass 34, count 0 2006.239.07:34:37.29#ibcon#*before return 0, iclass 34, count 0 2006.239.07:34:37.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:37.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:37.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:34:37.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:34:37.30$vc4f8/va=2,7 2006.239.07:34:37.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:34:37.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:34:37.30#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:37.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:37.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:37.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:37.34#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:34:37.34#ibcon#first serial, iclass 36, count 2 2006.239.07:34:37.34#ibcon#enter sib2, iclass 36, count 2 2006.239.07:34:37.34#ibcon#flushed, iclass 36, count 2 2006.239.07:34:37.34#ibcon#about to write, iclass 36, count 2 2006.239.07:34:37.34#ibcon#wrote, iclass 36, count 2 2006.239.07:34:37.34#ibcon#about to read 3, iclass 36, count 2 2006.239.07:34:37.37#ibcon#read 3, iclass 36, count 2 2006.239.07:34:37.37#ibcon#about to read 4, iclass 36, count 2 2006.239.07:34:37.37#ibcon#read 4, iclass 36, count 2 2006.239.07:34:37.37#ibcon#about to read 5, iclass 36, count 2 2006.239.07:34:37.37#ibcon#read 5, iclass 36, count 2 2006.239.07:34:37.37#ibcon#about to read 6, iclass 36, count 2 2006.239.07:34:37.37#ibcon#read 6, iclass 36, count 2 2006.239.07:34:37.37#ibcon#end of sib2, iclass 36, count 2 2006.239.07:34:37.37#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:34:37.37#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:34:37.37#ibcon#[25=AT02-07\r\n] 2006.239.07:34:37.37#ibcon#*before write, iclass 36, count 2 2006.239.07:34:37.37#ibcon#enter sib2, iclass 36, count 2 2006.239.07:34:37.37#ibcon#flushed, iclass 36, count 2 2006.239.07:34:37.37#ibcon#about to write, iclass 36, count 2 2006.239.07:34:37.37#ibcon#wrote, iclass 36, count 2 2006.239.07:34:37.37#ibcon#about to read 3, iclass 36, count 2 2006.239.07:34:37.40#ibcon#read 3, iclass 36, count 2 2006.239.07:34:37.40#ibcon#about to read 4, iclass 36, count 2 2006.239.07:34:37.40#ibcon#read 4, iclass 36, count 2 2006.239.07:34:37.40#ibcon#about to read 5, iclass 36, count 2 2006.239.07:34:37.40#ibcon#read 5, iclass 36, count 2 2006.239.07:34:37.40#ibcon#about to read 6, iclass 36, count 2 2006.239.07:34:37.40#ibcon#read 6, iclass 36, count 2 2006.239.07:34:37.40#ibcon#end of sib2, iclass 36, count 2 2006.239.07:34:37.40#ibcon#*after write, iclass 36, count 2 2006.239.07:34:37.40#ibcon#*before return 0, iclass 36, count 2 2006.239.07:34:37.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:37.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:37.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:34:37.40#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:37.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:37.43#abcon#<5=/04 2.2 4.2 25.38 811011.4\r\n> 2006.239.07:34:37.44#abcon#{5=INTERFACE CLEAR} 2006.239.07:34:37.50#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:34:37.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:37.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:37.55#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:34:37.55#ibcon#first serial, iclass 36, count 0 2006.239.07:34:37.55#ibcon#enter sib2, iclass 36, count 0 2006.239.07:34:37.55#ibcon#flushed, iclass 36, count 0 2006.239.07:34:37.55#ibcon#about to write, iclass 36, count 0 2006.239.07:34:37.55#ibcon#wrote, iclass 36, count 0 2006.239.07:34:37.55#ibcon#about to read 3, iclass 36, count 0 2006.239.07:34:37.56#ibcon#read 3, iclass 36, count 0 2006.239.07:34:37.56#ibcon#about to read 4, iclass 36, count 0 2006.239.07:34:37.56#ibcon#read 4, iclass 36, count 0 2006.239.07:34:37.56#ibcon#about to read 5, iclass 36, count 0 2006.239.07:34:37.56#ibcon#read 5, iclass 36, count 0 2006.239.07:34:37.56#ibcon#about to read 6, iclass 36, count 0 2006.239.07:34:37.56#ibcon#read 6, iclass 36, count 0 2006.239.07:34:37.56#ibcon#end of sib2, iclass 36, count 0 2006.239.07:34:37.56#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:34:37.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:34:37.56#ibcon#[25=USB\r\n] 2006.239.07:34:37.56#ibcon#*before write, iclass 36, count 0 2006.239.07:34:37.56#ibcon#enter sib2, iclass 36, count 0 2006.239.07:34:37.56#ibcon#flushed, iclass 36, count 0 2006.239.07:34:37.56#ibcon#about to write, iclass 36, count 0 2006.239.07:34:37.56#ibcon#wrote, iclass 36, count 0 2006.239.07:34:37.56#ibcon#about to read 3, iclass 36, count 0 2006.239.07:34:37.59#ibcon#read 3, iclass 36, count 0 2006.239.07:34:37.59#ibcon#about to read 4, iclass 36, count 0 2006.239.07:34:37.59#ibcon#read 4, iclass 36, count 0 2006.239.07:34:37.59#ibcon#about to read 5, iclass 36, count 0 2006.239.07:34:37.59#ibcon#read 5, iclass 36, count 0 2006.239.07:34:37.59#ibcon#about to read 6, iclass 36, count 0 2006.239.07:34:37.59#ibcon#read 6, iclass 36, count 0 2006.239.07:34:37.59#ibcon#end of sib2, iclass 36, count 0 2006.239.07:34:37.59#ibcon#*after write, iclass 36, count 0 2006.239.07:34:37.59#ibcon#*before return 0, iclass 36, count 0 2006.239.07:34:37.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:37.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:37.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:34:37.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:34:37.60$vc4f8/valo=3,672.99 2006.239.07:34:37.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:34:37.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:34:37.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:37.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:37.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:37.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:37.60#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:34:37.60#ibcon#first serial, iclass 4, count 0 2006.239.07:34:37.60#ibcon#enter sib2, iclass 4, count 0 2006.239.07:34:37.60#ibcon#flushed, iclass 4, count 0 2006.239.07:34:37.60#ibcon#about to write, iclass 4, count 0 2006.239.07:34:37.60#ibcon#wrote, iclass 4, count 0 2006.239.07:34:37.60#ibcon#about to read 3, iclass 4, count 0 2006.239.07:34:37.61#ibcon#read 3, iclass 4, count 0 2006.239.07:34:37.61#ibcon#about to read 4, iclass 4, count 0 2006.239.07:34:37.61#ibcon#read 4, iclass 4, count 0 2006.239.07:34:37.61#ibcon#about to read 5, iclass 4, count 0 2006.239.07:34:37.61#ibcon#read 5, iclass 4, count 0 2006.239.07:34:37.61#ibcon#about to read 6, iclass 4, count 0 2006.239.07:34:37.61#ibcon#read 6, iclass 4, count 0 2006.239.07:34:37.61#ibcon#end of sib2, iclass 4, count 0 2006.239.07:34:37.61#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:34:37.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:34:37.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:34:37.61#ibcon#*before write, iclass 4, count 0 2006.239.07:34:37.61#ibcon#enter sib2, iclass 4, count 0 2006.239.07:34:37.61#ibcon#flushed, iclass 4, count 0 2006.239.07:34:37.61#ibcon#about to write, iclass 4, count 0 2006.239.07:34:37.61#ibcon#wrote, iclass 4, count 0 2006.239.07:34:37.61#ibcon#about to read 3, iclass 4, count 0 2006.239.07:34:37.66#ibcon#read 3, iclass 4, count 0 2006.239.07:34:37.66#ibcon#about to read 4, iclass 4, count 0 2006.239.07:34:37.66#ibcon#read 4, iclass 4, count 0 2006.239.07:34:37.66#ibcon#about to read 5, iclass 4, count 0 2006.239.07:34:37.66#ibcon#read 5, iclass 4, count 0 2006.239.07:34:37.66#ibcon#about to read 6, iclass 4, count 0 2006.239.07:34:37.66#ibcon#read 6, iclass 4, count 0 2006.239.07:34:37.66#ibcon#end of sib2, iclass 4, count 0 2006.239.07:34:37.66#ibcon#*after write, iclass 4, count 0 2006.239.07:34:37.66#ibcon#*before return 0, iclass 4, count 0 2006.239.07:34:37.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:37.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:37.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:34:37.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:34:37.66$vc4f8/va=3,7 2006.239.07:34:37.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:34:37.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:34:37.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:37.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:37.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:37.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:37.70#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:34:37.70#ibcon#first serial, iclass 6, count 2 2006.239.07:34:37.70#ibcon#enter sib2, iclass 6, count 2 2006.239.07:34:37.70#ibcon#flushed, iclass 6, count 2 2006.239.07:34:37.70#ibcon#about to write, iclass 6, count 2 2006.239.07:34:37.70#ibcon#wrote, iclass 6, count 2 2006.239.07:34:37.70#ibcon#about to read 3, iclass 6, count 2 2006.239.07:34:37.72#ibcon#read 3, iclass 6, count 2 2006.239.07:34:37.72#ibcon#about to read 4, iclass 6, count 2 2006.239.07:34:37.72#ibcon#read 4, iclass 6, count 2 2006.239.07:34:37.72#ibcon#about to read 5, iclass 6, count 2 2006.239.07:34:37.72#ibcon#read 5, iclass 6, count 2 2006.239.07:34:37.72#ibcon#about to read 6, iclass 6, count 2 2006.239.07:34:37.72#ibcon#read 6, iclass 6, count 2 2006.239.07:34:37.72#ibcon#end of sib2, iclass 6, count 2 2006.239.07:34:37.72#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:34:37.72#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:34:37.72#ibcon#[25=AT03-07\r\n] 2006.239.07:34:37.72#ibcon#*before write, iclass 6, count 2 2006.239.07:34:37.72#ibcon#enter sib2, iclass 6, count 2 2006.239.07:34:37.72#ibcon#flushed, iclass 6, count 2 2006.239.07:34:37.72#ibcon#about to write, iclass 6, count 2 2006.239.07:34:37.72#ibcon#wrote, iclass 6, count 2 2006.239.07:34:37.72#ibcon#about to read 3, iclass 6, count 2 2006.239.07:34:37.75#ibcon#read 3, iclass 6, count 2 2006.239.07:34:37.75#ibcon#about to read 4, iclass 6, count 2 2006.239.07:34:37.75#ibcon#read 4, iclass 6, count 2 2006.239.07:34:37.75#ibcon#about to read 5, iclass 6, count 2 2006.239.07:34:37.75#ibcon#read 5, iclass 6, count 2 2006.239.07:34:37.75#ibcon#about to read 6, iclass 6, count 2 2006.239.07:34:37.75#ibcon#read 6, iclass 6, count 2 2006.239.07:34:37.75#ibcon#end of sib2, iclass 6, count 2 2006.239.07:34:37.75#ibcon#*after write, iclass 6, count 2 2006.239.07:34:37.75#ibcon#*before return 0, iclass 6, count 2 2006.239.07:34:37.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:37.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:37.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:34:37.75#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:37.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:37.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:37.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:37.87#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:34:37.87#ibcon#first serial, iclass 6, count 0 2006.239.07:34:37.87#ibcon#enter sib2, iclass 6, count 0 2006.239.07:34:37.87#ibcon#flushed, iclass 6, count 0 2006.239.07:34:37.87#ibcon#about to write, iclass 6, count 0 2006.239.07:34:37.87#ibcon#wrote, iclass 6, count 0 2006.239.07:34:37.87#ibcon#about to read 3, iclass 6, count 0 2006.239.07:34:37.89#ibcon#read 3, iclass 6, count 0 2006.239.07:34:37.89#ibcon#about to read 4, iclass 6, count 0 2006.239.07:34:37.89#ibcon#read 4, iclass 6, count 0 2006.239.07:34:37.89#ibcon#about to read 5, iclass 6, count 0 2006.239.07:34:37.89#ibcon#read 5, iclass 6, count 0 2006.239.07:34:37.89#ibcon#about to read 6, iclass 6, count 0 2006.239.07:34:37.89#ibcon#read 6, iclass 6, count 0 2006.239.07:34:37.89#ibcon#end of sib2, iclass 6, count 0 2006.239.07:34:37.89#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:34:37.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:34:37.89#ibcon#[25=USB\r\n] 2006.239.07:34:37.89#ibcon#*before write, iclass 6, count 0 2006.239.07:34:37.89#ibcon#enter sib2, iclass 6, count 0 2006.239.07:34:37.89#ibcon#flushed, iclass 6, count 0 2006.239.07:34:37.89#ibcon#about to write, iclass 6, count 0 2006.239.07:34:37.89#ibcon#wrote, iclass 6, count 0 2006.239.07:34:37.89#ibcon#about to read 3, iclass 6, count 0 2006.239.07:34:37.92#ibcon#read 3, iclass 6, count 0 2006.239.07:34:37.92#ibcon#about to read 4, iclass 6, count 0 2006.239.07:34:37.92#ibcon#read 4, iclass 6, count 0 2006.239.07:34:37.92#ibcon#about to read 5, iclass 6, count 0 2006.239.07:34:37.92#ibcon#read 5, iclass 6, count 0 2006.239.07:34:37.92#ibcon#about to read 6, iclass 6, count 0 2006.239.07:34:37.92#ibcon#read 6, iclass 6, count 0 2006.239.07:34:37.92#ibcon#end of sib2, iclass 6, count 0 2006.239.07:34:37.92#ibcon#*after write, iclass 6, count 0 2006.239.07:34:37.92#ibcon#*before return 0, iclass 6, count 0 2006.239.07:34:37.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:37.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:37.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:34:37.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:34:37.93$vc4f8/valo=4,832.99 2006.239.07:34:37.93#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:34:37.93#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:34:37.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:37.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:37.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:37.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:37.93#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:34:37.93#ibcon#first serial, iclass 10, count 0 2006.239.07:34:37.93#ibcon#enter sib2, iclass 10, count 0 2006.239.07:34:37.93#ibcon#flushed, iclass 10, count 0 2006.239.07:34:37.93#ibcon#about to write, iclass 10, count 0 2006.239.07:34:37.93#ibcon#wrote, iclass 10, count 0 2006.239.07:34:37.93#ibcon#about to read 3, iclass 10, count 0 2006.239.07:34:37.94#ibcon#read 3, iclass 10, count 0 2006.239.07:34:37.94#ibcon#about to read 4, iclass 10, count 0 2006.239.07:34:37.94#ibcon#read 4, iclass 10, count 0 2006.239.07:34:37.94#ibcon#about to read 5, iclass 10, count 0 2006.239.07:34:37.94#ibcon#read 5, iclass 10, count 0 2006.239.07:34:37.94#ibcon#about to read 6, iclass 10, count 0 2006.239.07:34:37.94#ibcon#read 6, iclass 10, count 0 2006.239.07:34:37.94#ibcon#end of sib2, iclass 10, count 0 2006.239.07:34:37.94#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:34:37.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:34:37.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:34:37.94#ibcon#*before write, iclass 10, count 0 2006.239.07:34:37.94#ibcon#enter sib2, iclass 10, count 0 2006.239.07:34:37.94#ibcon#flushed, iclass 10, count 0 2006.239.07:34:37.94#ibcon#about to write, iclass 10, count 0 2006.239.07:34:37.94#ibcon#wrote, iclass 10, count 0 2006.239.07:34:37.94#ibcon#about to read 3, iclass 10, count 0 2006.239.07:34:37.98#ibcon#read 3, iclass 10, count 0 2006.239.07:34:37.98#ibcon#about to read 4, iclass 10, count 0 2006.239.07:34:37.98#ibcon#read 4, iclass 10, count 0 2006.239.07:34:37.98#ibcon#about to read 5, iclass 10, count 0 2006.239.07:34:37.98#ibcon#read 5, iclass 10, count 0 2006.239.07:34:37.98#ibcon#about to read 6, iclass 10, count 0 2006.239.07:34:37.98#ibcon#read 6, iclass 10, count 0 2006.239.07:34:37.98#ibcon#end of sib2, iclass 10, count 0 2006.239.07:34:37.98#ibcon#*after write, iclass 10, count 0 2006.239.07:34:37.98#ibcon#*before return 0, iclass 10, count 0 2006.239.07:34:37.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:37.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:37.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:34:37.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:34:37.99$vc4f8/va=4,7 2006.239.07:34:37.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.07:34:37.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.07:34:37.99#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:37.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:38.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:38.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:38.03#ibcon#enter wrdev, iclass 12, count 2 2006.239.07:34:38.03#ibcon#first serial, iclass 12, count 2 2006.239.07:34:38.03#ibcon#enter sib2, iclass 12, count 2 2006.239.07:34:38.03#ibcon#flushed, iclass 12, count 2 2006.239.07:34:38.03#ibcon#about to write, iclass 12, count 2 2006.239.07:34:38.03#ibcon#wrote, iclass 12, count 2 2006.239.07:34:38.03#ibcon#about to read 3, iclass 12, count 2 2006.239.07:34:38.05#ibcon#read 3, iclass 12, count 2 2006.239.07:34:38.05#ibcon#about to read 4, iclass 12, count 2 2006.239.07:34:38.05#ibcon#read 4, iclass 12, count 2 2006.239.07:34:38.05#ibcon#about to read 5, iclass 12, count 2 2006.239.07:34:38.05#ibcon#read 5, iclass 12, count 2 2006.239.07:34:38.05#ibcon#about to read 6, iclass 12, count 2 2006.239.07:34:38.05#ibcon#read 6, iclass 12, count 2 2006.239.07:34:38.05#ibcon#end of sib2, iclass 12, count 2 2006.239.07:34:38.05#ibcon#*mode == 0, iclass 12, count 2 2006.239.07:34:38.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.07:34:38.05#ibcon#[25=AT04-07\r\n] 2006.239.07:34:38.05#ibcon#*before write, iclass 12, count 2 2006.239.07:34:38.05#ibcon#enter sib2, iclass 12, count 2 2006.239.07:34:38.05#ibcon#flushed, iclass 12, count 2 2006.239.07:34:38.05#ibcon#about to write, iclass 12, count 2 2006.239.07:34:38.05#ibcon#wrote, iclass 12, count 2 2006.239.07:34:38.05#ibcon#about to read 3, iclass 12, count 2 2006.239.07:34:38.08#ibcon#read 3, iclass 12, count 2 2006.239.07:34:38.08#ibcon#about to read 4, iclass 12, count 2 2006.239.07:34:38.08#ibcon#read 4, iclass 12, count 2 2006.239.07:34:38.08#ibcon#about to read 5, iclass 12, count 2 2006.239.07:34:38.08#ibcon#read 5, iclass 12, count 2 2006.239.07:34:38.08#ibcon#about to read 6, iclass 12, count 2 2006.239.07:34:38.08#ibcon#read 6, iclass 12, count 2 2006.239.07:34:38.08#ibcon#end of sib2, iclass 12, count 2 2006.239.07:34:38.08#ibcon#*after write, iclass 12, count 2 2006.239.07:34:38.08#ibcon#*before return 0, iclass 12, count 2 2006.239.07:34:38.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:38.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:38.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.07:34:38.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:38.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:38.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:38.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:38.20#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:34:38.20#ibcon#first serial, iclass 12, count 0 2006.239.07:34:38.20#ibcon#enter sib2, iclass 12, count 0 2006.239.07:34:38.20#ibcon#flushed, iclass 12, count 0 2006.239.07:34:38.20#ibcon#about to write, iclass 12, count 0 2006.239.07:34:38.20#ibcon#wrote, iclass 12, count 0 2006.239.07:34:38.20#ibcon#about to read 3, iclass 12, count 0 2006.239.07:34:38.22#ibcon#read 3, iclass 12, count 0 2006.239.07:34:38.22#ibcon#about to read 4, iclass 12, count 0 2006.239.07:34:38.22#ibcon#read 4, iclass 12, count 0 2006.239.07:34:38.22#ibcon#about to read 5, iclass 12, count 0 2006.239.07:34:38.22#ibcon#read 5, iclass 12, count 0 2006.239.07:34:38.22#ibcon#about to read 6, iclass 12, count 0 2006.239.07:34:38.22#ibcon#read 6, iclass 12, count 0 2006.239.07:34:38.22#ibcon#end of sib2, iclass 12, count 0 2006.239.07:34:38.22#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:34:38.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:34:38.22#ibcon#[25=USB\r\n] 2006.239.07:34:38.22#ibcon#*before write, iclass 12, count 0 2006.239.07:34:38.22#ibcon#enter sib2, iclass 12, count 0 2006.239.07:34:38.22#ibcon#flushed, iclass 12, count 0 2006.239.07:34:38.22#ibcon#about to write, iclass 12, count 0 2006.239.07:34:38.22#ibcon#wrote, iclass 12, count 0 2006.239.07:34:38.22#ibcon#about to read 3, iclass 12, count 0 2006.239.07:34:38.25#ibcon#read 3, iclass 12, count 0 2006.239.07:34:38.25#ibcon#about to read 4, iclass 12, count 0 2006.239.07:34:38.25#ibcon#read 4, iclass 12, count 0 2006.239.07:34:38.25#ibcon#about to read 5, iclass 12, count 0 2006.239.07:34:38.25#ibcon#read 5, iclass 12, count 0 2006.239.07:34:38.25#ibcon#about to read 6, iclass 12, count 0 2006.239.07:34:38.25#ibcon#read 6, iclass 12, count 0 2006.239.07:34:38.25#ibcon#end of sib2, iclass 12, count 0 2006.239.07:34:38.25#ibcon#*after write, iclass 12, count 0 2006.239.07:34:38.25#ibcon#*before return 0, iclass 12, count 0 2006.239.07:34:38.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:38.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:38.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:34:38.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:34:38.26$vc4f8/valo=5,652.99 2006.239.07:34:38.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:34:38.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:34:38.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:38.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:38.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:38.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:38.26#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:34:38.26#ibcon#first serial, iclass 14, count 0 2006.239.07:34:38.26#ibcon#enter sib2, iclass 14, count 0 2006.239.07:34:38.26#ibcon#flushed, iclass 14, count 0 2006.239.07:34:38.26#ibcon#about to write, iclass 14, count 0 2006.239.07:34:38.26#ibcon#wrote, iclass 14, count 0 2006.239.07:34:38.26#ibcon#about to read 3, iclass 14, count 0 2006.239.07:34:38.27#ibcon#read 3, iclass 14, count 0 2006.239.07:34:38.27#ibcon#about to read 4, iclass 14, count 0 2006.239.07:34:38.27#ibcon#read 4, iclass 14, count 0 2006.239.07:34:38.27#ibcon#about to read 5, iclass 14, count 0 2006.239.07:34:38.27#ibcon#read 5, iclass 14, count 0 2006.239.07:34:38.27#ibcon#about to read 6, iclass 14, count 0 2006.239.07:34:38.27#ibcon#read 6, iclass 14, count 0 2006.239.07:34:38.27#ibcon#end of sib2, iclass 14, count 0 2006.239.07:34:38.27#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:34:38.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:34:38.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:34:38.27#ibcon#*before write, iclass 14, count 0 2006.239.07:34:38.27#ibcon#enter sib2, iclass 14, count 0 2006.239.07:34:38.27#ibcon#flushed, iclass 14, count 0 2006.239.07:34:38.27#ibcon#about to write, iclass 14, count 0 2006.239.07:34:38.27#ibcon#wrote, iclass 14, count 0 2006.239.07:34:38.27#ibcon#about to read 3, iclass 14, count 0 2006.239.07:34:38.31#ibcon#read 3, iclass 14, count 0 2006.239.07:34:38.31#ibcon#about to read 4, iclass 14, count 0 2006.239.07:34:38.31#ibcon#read 4, iclass 14, count 0 2006.239.07:34:38.31#ibcon#about to read 5, iclass 14, count 0 2006.239.07:34:38.31#ibcon#read 5, iclass 14, count 0 2006.239.07:34:38.31#ibcon#about to read 6, iclass 14, count 0 2006.239.07:34:38.31#ibcon#read 6, iclass 14, count 0 2006.239.07:34:38.31#ibcon#end of sib2, iclass 14, count 0 2006.239.07:34:38.31#ibcon#*after write, iclass 14, count 0 2006.239.07:34:38.31#ibcon#*before return 0, iclass 14, count 0 2006.239.07:34:38.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:38.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:38.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:34:38.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:34:38.32$vc4f8/va=5,8 2006.239.07:34:38.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:34:38.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:34:38.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:38.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:38.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:38.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:38.36#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:34:38.36#ibcon#first serial, iclass 16, count 2 2006.239.07:34:38.36#ibcon#enter sib2, iclass 16, count 2 2006.239.07:34:38.36#ibcon#flushed, iclass 16, count 2 2006.239.07:34:38.36#ibcon#about to write, iclass 16, count 2 2006.239.07:34:38.36#ibcon#wrote, iclass 16, count 2 2006.239.07:34:38.36#ibcon#about to read 3, iclass 16, count 2 2006.239.07:34:38.38#ibcon#read 3, iclass 16, count 2 2006.239.07:34:38.38#ibcon#about to read 4, iclass 16, count 2 2006.239.07:34:38.38#ibcon#read 4, iclass 16, count 2 2006.239.07:34:38.38#ibcon#about to read 5, iclass 16, count 2 2006.239.07:34:38.38#ibcon#read 5, iclass 16, count 2 2006.239.07:34:38.38#ibcon#about to read 6, iclass 16, count 2 2006.239.07:34:38.38#ibcon#read 6, iclass 16, count 2 2006.239.07:34:38.38#ibcon#end of sib2, iclass 16, count 2 2006.239.07:34:38.38#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:34:38.38#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:34:38.38#ibcon#[25=AT05-08\r\n] 2006.239.07:34:38.38#ibcon#*before write, iclass 16, count 2 2006.239.07:34:38.38#ibcon#enter sib2, iclass 16, count 2 2006.239.07:34:38.38#ibcon#flushed, iclass 16, count 2 2006.239.07:34:38.38#ibcon#about to write, iclass 16, count 2 2006.239.07:34:38.38#ibcon#wrote, iclass 16, count 2 2006.239.07:34:38.38#ibcon#about to read 3, iclass 16, count 2 2006.239.07:34:38.41#ibcon#read 3, iclass 16, count 2 2006.239.07:34:38.41#ibcon#about to read 4, iclass 16, count 2 2006.239.07:34:38.41#ibcon#read 4, iclass 16, count 2 2006.239.07:34:38.41#ibcon#about to read 5, iclass 16, count 2 2006.239.07:34:38.41#ibcon#read 5, iclass 16, count 2 2006.239.07:34:38.41#ibcon#about to read 6, iclass 16, count 2 2006.239.07:34:38.41#ibcon#read 6, iclass 16, count 2 2006.239.07:34:38.41#ibcon#end of sib2, iclass 16, count 2 2006.239.07:34:38.41#ibcon#*after write, iclass 16, count 2 2006.239.07:34:38.41#ibcon#*before return 0, iclass 16, count 2 2006.239.07:34:38.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:38.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:38.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:34:38.41#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:38.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:38.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:38.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:38.53#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:34:38.53#ibcon#first serial, iclass 16, count 0 2006.239.07:34:38.53#ibcon#enter sib2, iclass 16, count 0 2006.239.07:34:38.53#ibcon#flushed, iclass 16, count 0 2006.239.07:34:38.53#ibcon#about to write, iclass 16, count 0 2006.239.07:34:38.53#ibcon#wrote, iclass 16, count 0 2006.239.07:34:38.53#ibcon#about to read 3, iclass 16, count 0 2006.239.07:34:38.55#ibcon#read 3, iclass 16, count 0 2006.239.07:34:38.55#ibcon#about to read 4, iclass 16, count 0 2006.239.07:34:38.55#ibcon#read 4, iclass 16, count 0 2006.239.07:34:38.55#ibcon#about to read 5, iclass 16, count 0 2006.239.07:34:38.55#ibcon#read 5, iclass 16, count 0 2006.239.07:34:38.55#ibcon#about to read 6, iclass 16, count 0 2006.239.07:34:38.55#ibcon#read 6, iclass 16, count 0 2006.239.07:34:38.55#ibcon#end of sib2, iclass 16, count 0 2006.239.07:34:38.55#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:34:38.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:34:38.55#ibcon#[25=USB\r\n] 2006.239.07:34:38.55#ibcon#*before write, iclass 16, count 0 2006.239.07:34:38.55#ibcon#enter sib2, iclass 16, count 0 2006.239.07:34:38.55#ibcon#flushed, iclass 16, count 0 2006.239.07:34:38.55#ibcon#about to write, iclass 16, count 0 2006.239.07:34:38.55#ibcon#wrote, iclass 16, count 0 2006.239.07:34:38.55#ibcon#about to read 3, iclass 16, count 0 2006.239.07:34:38.58#ibcon#read 3, iclass 16, count 0 2006.239.07:34:38.58#ibcon#about to read 4, iclass 16, count 0 2006.239.07:34:38.58#ibcon#read 4, iclass 16, count 0 2006.239.07:34:38.58#ibcon#about to read 5, iclass 16, count 0 2006.239.07:34:38.58#ibcon#read 5, iclass 16, count 0 2006.239.07:34:38.58#ibcon#about to read 6, iclass 16, count 0 2006.239.07:34:38.58#ibcon#read 6, iclass 16, count 0 2006.239.07:34:38.58#ibcon#end of sib2, iclass 16, count 0 2006.239.07:34:38.58#ibcon#*after write, iclass 16, count 0 2006.239.07:34:38.58#ibcon#*before return 0, iclass 16, count 0 2006.239.07:34:38.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:38.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:38.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:34:38.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:34:38.59$vc4f8/valo=6,772.99 2006.239.07:34:38.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.07:34:38.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.07:34:38.59#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:38.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:38.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:38.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:38.59#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:34:38.59#ibcon#first serial, iclass 18, count 0 2006.239.07:34:38.59#ibcon#enter sib2, iclass 18, count 0 2006.239.07:34:38.59#ibcon#flushed, iclass 18, count 0 2006.239.07:34:38.59#ibcon#about to write, iclass 18, count 0 2006.239.07:34:38.59#ibcon#wrote, iclass 18, count 0 2006.239.07:34:38.59#ibcon#about to read 3, iclass 18, count 0 2006.239.07:34:38.60#ibcon#read 3, iclass 18, count 0 2006.239.07:34:38.60#ibcon#about to read 4, iclass 18, count 0 2006.239.07:34:38.60#ibcon#read 4, iclass 18, count 0 2006.239.07:34:38.60#ibcon#about to read 5, iclass 18, count 0 2006.239.07:34:38.60#ibcon#read 5, iclass 18, count 0 2006.239.07:34:38.60#ibcon#about to read 6, iclass 18, count 0 2006.239.07:34:38.60#ibcon#read 6, iclass 18, count 0 2006.239.07:34:38.60#ibcon#end of sib2, iclass 18, count 0 2006.239.07:34:38.60#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:34:38.60#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:34:38.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:34:38.60#ibcon#*before write, iclass 18, count 0 2006.239.07:34:38.60#ibcon#enter sib2, iclass 18, count 0 2006.239.07:34:38.60#ibcon#flushed, iclass 18, count 0 2006.239.07:34:38.60#ibcon#about to write, iclass 18, count 0 2006.239.07:34:38.60#ibcon#wrote, iclass 18, count 0 2006.239.07:34:38.60#ibcon#about to read 3, iclass 18, count 0 2006.239.07:34:38.64#ibcon#read 3, iclass 18, count 0 2006.239.07:34:38.64#ibcon#about to read 4, iclass 18, count 0 2006.239.07:34:38.64#ibcon#read 4, iclass 18, count 0 2006.239.07:34:38.64#ibcon#about to read 5, iclass 18, count 0 2006.239.07:34:38.64#ibcon#read 5, iclass 18, count 0 2006.239.07:34:38.64#ibcon#about to read 6, iclass 18, count 0 2006.239.07:34:38.64#ibcon#read 6, iclass 18, count 0 2006.239.07:34:38.64#ibcon#end of sib2, iclass 18, count 0 2006.239.07:34:38.64#ibcon#*after write, iclass 18, count 0 2006.239.07:34:38.64#ibcon#*before return 0, iclass 18, count 0 2006.239.07:34:38.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:38.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:38.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:34:38.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:34:38.65$vc4f8/va=6,7 2006.239.07:34:38.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.07:34:38.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.07:34:38.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:38.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:34:38.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:34:38.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:34:38.69#ibcon#enter wrdev, iclass 20, count 2 2006.239.07:34:38.69#ibcon#first serial, iclass 20, count 2 2006.239.07:34:38.69#ibcon#enter sib2, iclass 20, count 2 2006.239.07:34:38.69#ibcon#flushed, iclass 20, count 2 2006.239.07:34:38.69#ibcon#about to write, iclass 20, count 2 2006.239.07:34:38.69#ibcon#wrote, iclass 20, count 2 2006.239.07:34:38.69#ibcon#about to read 3, iclass 20, count 2 2006.239.07:34:38.71#ibcon#read 3, iclass 20, count 2 2006.239.07:34:38.71#ibcon#about to read 4, iclass 20, count 2 2006.239.07:34:38.71#ibcon#read 4, iclass 20, count 2 2006.239.07:34:38.71#ibcon#about to read 5, iclass 20, count 2 2006.239.07:34:38.71#ibcon#read 5, iclass 20, count 2 2006.239.07:34:38.71#ibcon#about to read 6, iclass 20, count 2 2006.239.07:34:38.71#ibcon#read 6, iclass 20, count 2 2006.239.07:34:38.71#ibcon#end of sib2, iclass 20, count 2 2006.239.07:34:38.71#ibcon#*mode == 0, iclass 20, count 2 2006.239.07:34:38.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.07:34:38.71#ibcon#[25=AT06-07\r\n] 2006.239.07:34:38.71#ibcon#*before write, iclass 20, count 2 2006.239.07:34:38.71#ibcon#enter sib2, iclass 20, count 2 2006.239.07:34:38.71#ibcon#flushed, iclass 20, count 2 2006.239.07:34:38.71#ibcon#about to write, iclass 20, count 2 2006.239.07:34:38.71#ibcon#wrote, iclass 20, count 2 2006.239.07:34:38.71#ibcon#about to read 3, iclass 20, count 2 2006.239.07:34:38.74#ibcon#read 3, iclass 20, count 2 2006.239.07:34:38.74#ibcon#about to read 4, iclass 20, count 2 2006.239.07:34:38.74#ibcon#read 4, iclass 20, count 2 2006.239.07:34:38.74#ibcon#about to read 5, iclass 20, count 2 2006.239.07:34:38.74#ibcon#read 5, iclass 20, count 2 2006.239.07:34:38.74#ibcon#about to read 6, iclass 20, count 2 2006.239.07:34:38.74#ibcon#read 6, iclass 20, count 2 2006.239.07:34:38.74#ibcon#end of sib2, iclass 20, count 2 2006.239.07:34:38.74#ibcon#*after write, iclass 20, count 2 2006.239.07:34:38.74#ibcon#*before return 0, iclass 20, count 2 2006.239.07:34:38.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:34:38.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:34:38.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.07:34:38.74#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:38.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:34:38.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:34:38.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:34:38.86#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:34:38.86#ibcon#first serial, iclass 20, count 0 2006.239.07:34:38.86#ibcon#enter sib2, iclass 20, count 0 2006.239.07:34:38.86#ibcon#flushed, iclass 20, count 0 2006.239.07:34:38.86#ibcon#about to write, iclass 20, count 0 2006.239.07:34:38.86#ibcon#wrote, iclass 20, count 0 2006.239.07:34:38.86#ibcon#about to read 3, iclass 20, count 0 2006.239.07:34:38.88#ibcon#read 3, iclass 20, count 0 2006.239.07:34:38.88#ibcon#about to read 4, iclass 20, count 0 2006.239.07:34:38.88#ibcon#read 4, iclass 20, count 0 2006.239.07:34:38.88#ibcon#about to read 5, iclass 20, count 0 2006.239.07:34:38.88#ibcon#read 5, iclass 20, count 0 2006.239.07:34:38.88#ibcon#about to read 6, iclass 20, count 0 2006.239.07:34:38.88#ibcon#read 6, iclass 20, count 0 2006.239.07:34:38.88#ibcon#end of sib2, iclass 20, count 0 2006.239.07:34:38.88#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:34:38.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:34:38.88#ibcon#[25=USB\r\n] 2006.239.07:34:38.88#ibcon#*before write, iclass 20, count 0 2006.239.07:34:38.88#ibcon#enter sib2, iclass 20, count 0 2006.239.07:34:38.88#ibcon#flushed, iclass 20, count 0 2006.239.07:34:38.88#ibcon#about to write, iclass 20, count 0 2006.239.07:34:38.88#ibcon#wrote, iclass 20, count 0 2006.239.07:34:38.88#ibcon#about to read 3, iclass 20, count 0 2006.239.07:34:38.91#ibcon#read 3, iclass 20, count 0 2006.239.07:34:38.91#ibcon#about to read 4, iclass 20, count 0 2006.239.07:34:38.91#ibcon#read 4, iclass 20, count 0 2006.239.07:34:38.91#ibcon#about to read 5, iclass 20, count 0 2006.239.07:34:38.91#ibcon#read 5, iclass 20, count 0 2006.239.07:34:38.91#ibcon#about to read 6, iclass 20, count 0 2006.239.07:34:38.91#ibcon#read 6, iclass 20, count 0 2006.239.07:34:38.91#ibcon#end of sib2, iclass 20, count 0 2006.239.07:34:38.91#ibcon#*after write, iclass 20, count 0 2006.239.07:34:38.91#ibcon#*before return 0, iclass 20, count 0 2006.239.07:34:38.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:34:38.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:34:38.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:34:38.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:34:38.91$vc4f8/valo=7,832.99 2006.239.07:34:38.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.07:34:38.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.07:34:38.92#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:38.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:34:38.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:34:38.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:34:38.92#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:34:38.92#ibcon#first serial, iclass 22, count 0 2006.239.07:34:38.92#ibcon#enter sib2, iclass 22, count 0 2006.239.07:34:38.92#ibcon#flushed, iclass 22, count 0 2006.239.07:34:38.92#ibcon#about to write, iclass 22, count 0 2006.239.07:34:38.92#ibcon#wrote, iclass 22, count 0 2006.239.07:34:38.92#ibcon#about to read 3, iclass 22, count 0 2006.239.07:34:38.93#ibcon#read 3, iclass 22, count 0 2006.239.07:34:38.93#ibcon#about to read 4, iclass 22, count 0 2006.239.07:34:38.93#ibcon#read 4, iclass 22, count 0 2006.239.07:34:38.93#ibcon#about to read 5, iclass 22, count 0 2006.239.07:34:38.93#ibcon#read 5, iclass 22, count 0 2006.239.07:34:38.93#ibcon#about to read 6, iclass 22, count 0 2006.239.07:34:38.93#ibcon#read 6, iclass 22, count 0 2006.239.07:34:38.93#ibcon#end of sib2, iclass 22, count 0 2006.239.07:34:38.93#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:34:38.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:34:38.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:34:38.93#ibcon#*before write, iclass 22, count 0 2006.239.07:34:38.93#ibcon#enter sib2, iclass 22, count 0 2006.239.07:34:38.93#ibcon#flushed, iclass 22, count 0 2006.239.07:34:38.93#ibcon#about to write, iclass 22, count 0 2006.239.07:34:38.93#ibcon#wrote, iclass 22, count 0 2006.239.07:34:38.93#ibcon#about to read 3, iclass 22, count 0 2006.239.07:34:38.97#ibcon#read 3, iclass 22, count 0 2006.239.07:34:38.97#ibcon#about to read 4, iclass 22, count 0 2006.239.07:34:38.97#ibcon#read 4, iclass 22, count 0 2006.239.07:34:38.97#ibcon#about to read 5, iclass 22, count 0 2006.239.07:34:38.97#ibcon#read 5, iclass 22, count 0 2006.239.07:34:38.97#ibcon#about to read 6, iclass 22, count 0 2006.239.07:34:38.97#ibcon#read 6, iclass 22, count 0 2006.239.07:34:38.97#ibcon#end of sib2, iclass 22, count 0 2006.239.07:34:38.97#ibcon#*after write, iclass 22, count 0 2006.239.07:34:38.97#ibcon#*before return 0, iclass 22, count 0 2006.239.07:34:38.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:34:38.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:34:38.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:34:38.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:34:38.98$vc4f8/va=7,7 2006.239.07:34:38.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.07:34:38.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.07:34:38.98#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:38.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:34:39.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:34:39.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:34:39.02#ibcon#enter wrdev, iclass 24, count 2 2006.239.07:34:39.02#ibcon#first serial, iclass 24, count 2 2006.239.07:34:39.02#ibcon#enter sib2, iclass 24, count 2 2006.239.07:34:39.02#ibcon#flushed, iclass 24, count 2 2006.239.07:34:39.02#ibcon#about to write, iclass 24, count 2 2006.239.07:34:39.02#ibcon#wrote, iclass 24, count 2 2006.239.07:34:39.02#ibcon#about to read 3, iclass 24, count 2 2006.239.07:34:39.04#ibcon#read 3, iclass 24, count 2 2006.239.07:34:39.04#ibcon#about to read 4, iclass 24, count 2 2006.239.07:34:39.04#ibcon#read 4, iclass 24, count 2 2006.239.07:34:39.04#ibcon#about to read 5, iclass 24, count 2 2006.239.07:34:39.04#ibcon#read 5, iclass 24, count 2 2006.239.07:34:39.04#ibcon#about to read 6, iclass 24, count 2 2006.239.07:34:39.04#ibcon#read 6, iclass 24, count 2 2006.239.07:34:39.04#ibcon#end of sib2, iclass 24, count 2 2006.239.07:34:39.04#ibcon#*mode == 0, iclass 24, count 2 2006.239.07:34:39.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.07:34:39.04#ibcon#[25=AT07-07\r\n] 2006.239.07:34:39.04#ibcon#*before write, iclass 24, count 2 2006.239.07:34:39.04#ibcon#enter sib2, iclass 24, count 2 2006.239.07:34:39.04#ibcon#flushed, iclass 24, count 2 2006.239.07:34:39.04#ibcon#about to write, iclass 24, count 2 2006.239.07:34:39.04#ibcon#wrote, iclass 24, count 2 2006.239.07:34:39.04#ibcon#about to read 3, iclass 24, count 2 2006.239.07:34:39.08#ibcon#read 3, iclass 24, count 2 2006.239.07:34:39.08#ibcon#about to read 4, iclass 24, count 2 2006.239.07:34:39.08#ibcon#read 4, iclass 24, count 2 2006.239.07:34:39.08#ibcon#about to read 5, iclass 24, count 2 2006.239.07:34:39.08#ibcon#read 5, iclass 24, count 2 2006.239.07:34:39.08#ibcon#about to read 6, iclass 24, count 2 2006.239.07:34:39.08#ibcon#read 6, iclass 24, count 2 2006.239.07:34:39.08#ibcon#end of sib2, iclass 24, count 2 2006.239.07:34:39.08#ibcon#*after write, iclass 24, count 2 2006.239.07:34:39.08#ibcon#*before return 0, iclass 24, count 2 2006.239.07:34:39.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:34:39.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:34:39.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.07:34:39.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:39.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:34:39.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:34:39.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:34:39.19#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:34:39.19#ibcon#first serial, iclass 24, count 0 2006.239.07:34:39.19#ibcon#enter sib2, iclass 24, count 0 2006.239.07:34:39.19#ibcon#flushed, iclass 24, count 0 2006.239.07:34:39.19#ibcon#about to write, iclass 24, count 0 2006.239.07:34:39.19#ibcon#wrote, iclass 24, count 0 2006.239.07:34:39.19#ibcon#about to read 3, iclass 24, count 0 2006.239.07:34:39.21#ibcon#read 3, iclass 24, count 0 2006.239.07:34:39.21#ibcon#about to read 4, iclass 24, count 0 2006.239.07:34:39.21#ibcon#read 4, iclass 24, count 0 2006.239.07:34:39.21#ibcon#about to read 5, iclass 24, count 0 2006.239.07:34:39.21#ibcon#read 5, iclass 24, count 0 2006.239.07:34:39.21#ibcon#about to read 6, iclass 24, count 0 2006.239.07:34:39.21#ibcon#read 6, iclass 24, count 0 2006.239.07:34:39.21#ibcon#end of sib2, iclass 24, count 0 2006.239.07:34:39.21#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:34:39.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:34:39.21#ibcon#[25=USB\r\n] 2006.239.07:34:39.21#ibcon#*before write, iclass 24, count 0 2006.239.07:34:39.21#ibcon#enter sib2, iclass 24, count 0 2006.239.07:34:39.21#ibcon#flushed, iclass 24, count 0 2006.239.07:34:39.21#ibcon#about to write, iclass 24, count 0 2006.239.07:34:39.21#ibcon#wrote, iclass 24, count 0 2006.239.07:34:39.21#ibcon#about to read 3, iclass 24, count 0 2006.239.07:34:39.24#ibcon#read 3, iclass 24, count 0 2006.239.07:34:39.24#ibcon#about to read 4, iclass 24, count 0 2006.239.07:34:39.24#ibcon#read 4, iclass 24, count 0 2006.239.07:34:39.24#ibcon#about to read 5, iclass 24, count 0 2006.239.07:34:39.24#ibcon#read 5, iclass 24, count 0 2006.239.07:34:39.24#ibcon#about to read 6, iclass 24, count 0 2006.239.07:34:39.24#ibcon#read 6, iclass 24, count 0 2006.239.07:34:39.24#ibcon#end of sib2, iclass 24, count 0 2006.239.07:34:39.24#ibcon#*after write, iclass 24, count 0 2006.239.07:34:39.24#ibcon#*before return 0, iclass 24, count 0 2006.239.07:34:39.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:34:39.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:34:39.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:34:39.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:34:39.24$vc4f8/valo=8,852.99 2006.239.07:34:39.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:34:39.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:34:39.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:39.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:34:39.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:34:39.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:34:39.25#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:34:39.25#ibcon#first serial, iclass 26, count 0 2006.239.07:34:39.25#ibcon#enter sib2, iclass 26, count 0 2006.239.07:34:39.25#ibcon#flushed, iclass 26, count 0 2006.239.07:34:39.25#ibcon#about to write, iclass 26, count 0 2006.239.07:34:39.25#ibcon#wrote, iclass 26, count 0 2006.239.07:34:39.25#ibcon#about to read 3, iclass 26, count 0 2006.239.07:34:39.26#ibcon#read 3, iclass 26, count 0 2006.239.07:34:39.26#ibcon#about to read 4, iclass 26, count 0 2006.239.07:34:39.26#ibcon#read 4, iclass 26, count 0 2006.239.07:34:39.26#ibcon#about to read 5, iclass 26, count 0 2006.239.07:34:39.26#ibcon#read 5, iclass 26, count 0 2006.239.07:34:39.26#ibcon#about to read 6, iclass 26, count 0 2006.239.07:34:39.26#ibcon#read 6, iclass 26, count 0 2006.239.07:34:39.26#ibcon#end of sib2, iclass 26, count 0 2006.239.07:34:39.26#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:34:39.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:34:39.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:34:39.26#ibcon#*before write, iclass 26, count 0 2006.239.07:34:39.26#ibcon#enter sib2, iclass 26, count 0 2006.239.07:34:39.26#ibcon#flushed, iclass 26, count 0 2006.239.07:34:39.26#ibcon#about to write, iclass 26, count 0 2006.239.07:34:39.26#ibcon#wrote, iclass 26, count 0 2006.239.07:34:39.26#ibcon#about to read 3, iclass 26, count 0 2006.239.07:34:39.30#ibcon#read 3, iclass 26, count 0 2006.239.07:34:39.30#ibcon#about to read 4, iclass 26, count 0 2006.239.07:34:39.30#ibcon#read 4, iclass 26, count 0 2006.239.07:34:39.30#ibcon#about to read 5, iclass 26, count 0 2006.239.07:34:39.30#ibcon#read 5, iclass 26, count 0 2006.239.07:34:39.30#ibcon#about to read 6, iclass 26, count 0 2006.239.07:34:39.30#ibcon#read 6, iclass 26, count 0 2006.239.07:34:39.30#ibcon#end of sib2, iclass 26, count 0 2006.239.07:34:39.30#ibcon#*after write, iclass 26, count 0 2006.239.07:34:39.30#ibcon#*before return 0, iclass 26, count 0 2006.239.07:34:39.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:34:39.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:34:39.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:34:39.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:34:39.30$vc4f8/va=8,7 2006.239.07:34:39.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:34:39.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:34:39.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:39.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:34:39.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:34:39.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:34:39.35#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:34:39.35#ibcon#first serial, iclass 28, count 2 2006.239.07:34:39.35#ibcon#enter sib2, iclass 28, count 2 2006.239.07:34:39.35#ibcon#flushed, iclass 28, count 2 2006.239.07:34:39.35#ibcon#about to write, iclass 28, count 2 2006.239.07:34:39.35#ibcon#wrote, iclass 28, count 2 2006.239.07:34:39.35#ibcon#about to read 3, iclass 28, count 2 2006.239.07:34:39.37#ibcon#read 3, iclass 28, count 2 2006.239.07:34:39.37#ibcon#about to read 4, iclass 28, count 2 2006.239.07:34:39.37#ibcon#read 4, iclass 28, count 2 2006.239.07:34:39.37#ibcon#about to read 5, iclass 28, count 2 2006.239.07:34:39.37#ibcon#read 5, iclass 28, count 2 2006.239.07:34:39.37#ibcon#about to read 6, iclass 28, count 2 2006.239.07:34:39.37#ibcon#read 6, iclass 28, count 2 2006.239.07:34:39.37#ibcon#end of sib2, iclass 28, count 2 2006.239.07:34:39.37#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:34:39.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:34:39.37#ibcon#[25=AT08-07\r\n] 2006.239.07:34:39.37#ibcon#*before write, iclass 28, count 2 2006.239.07:34:39.37#ibcon#enter sib2, iclass 28, count 2 2006.239.07:34:39.37#ibcon#flushed, iclass 28, count 2 2006.239.07:34:39.37#ibcon#about to write, iclass 28, count 2 2006.239.07:34:39.37#ibcon#wrote, iclass 28, count 2 2006.239.07:34:39.37#ibcon#about to read 3, iclass 28, count 2 2006.239.07:34:39.40#ibcon#read 3, iclass 28, count 2 2006.239.07:34:39.40#ibcon#about to read 4, iclass 28, count 2 2006.239.07:34:39.40#ibcon#read 4, iclass 28, count 2 2006.239.07:34:39.40#ibcon#about to read 5, iclass 28, count 2 2006.239.07:34:39.40#ibcon#read 5, iclass 28, count 2 2006.239.07:34:39.40#ibcon#about to read 6, iclass 28, count 2 2006.239.07:34:39.40#ibcon#read 6, iclass 28, count 2 2006.239.07:34:39.40#ibcon#end of sib2, iclass 28, count 2 2006.239.07:34:39.40#ibcon#*after write, iclass 28, count 2 2006.239.07:34:39.40#ibcon#*before return 0, iclass 28, count 2 2006.239.07:34:39.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:34:39.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:34:39.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:34:39.40#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:39.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:34:39.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:34:39.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:34:39.52#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:34:39.52#ibcon#first serial, iclass 28, count 0 2006.239.07:34:39.52#ibcon#enter sib2, iclass 28, count 0 2006.239.07:34:39.52#ibcon#flushed, iclass 28, count 0 2006.239.07:34:39.52#ibcon#about to write, iclass 28, count 0 2006.239.07:34:39.52#ibcon#wrote, iclass 28, count 0 2006.239.07:34:39.52#ibcon#about to read 3, iclass 28, count 0 2006.239.07:34:39.54#ibcon#read 3, iclass 28, count 0 2006.239.07:34:39.54#ibcon#about to read 4, iclass 28, count 0 2006.239.07:34:39.54#ibcon#read 4, iclass 28, count 0 2006.239.07:34:39.54#ibcon#about to read 5, iclass 28, count 0 2006.239.07:34:39.54#ibcon#read 5, iclass 28, count 0 2006.239.07:34:39.54#ibcon#about to read 6, iclass 28, count 0 2006.239.07:34:39.54#ibcon#read 6, iclass 28, count 0 2006.239.07:34:39.54#ibcon#end of sib2, iclass 28, count 0 2006.239.07:34:39.54#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:34:39.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:34:39.54#ibcon#[25=USB\r\n] 2006.239.07:34:39.54#ibcon#*before write, iclass 28, count 0 2006.239.07:34:39.54#ibcon#enter sib2, iclass 28, count 0 2006.239.07:34:39.54#ibcon#flushed, iclass 28, count 0 2006.239.07:34:39.54#ibcon#about to write, iclass 28, count 0 2006.239.07:34:39.54#ibcon#wrote, iclass 28, count 0 2006.239.07:34:39.54#ibcon#about to read 3, iclass 28, count 0 2006.239.07:34:39.57#ibcon#read 3, iclass 28, count 0 2006.239.07:34:39.57#ibcon#about to read 4, iclass 28, count 0 2006.239.07:34:39.57#ibcon#read 4, iclass 28, count 0 2006.239.07:34:39.57#ibcon#about to read 5, iclass 28, count 0 2006.239.07:34:39.57#ibcon#read 5, iclass 28, count 0 2006.239.07:34:39.57#ibcon#about to read 6, iclass 28, count 0 2006.239.07:34:39.57#ibcon#read 6, iclass 28, count 0 2006.239.07:34:39.57#ibcon#end of sib2, iclass 28, count 0 2006.239.07:34:39.57#ibcon#*after write, iclass 28, count 0 2006.239.07:34:39.57#ibcon#*before return 0, iclass 28, count 0 2006.239.07:34:39.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:34:39.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:34:39.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:34:39.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:34:39.57$vc4f8/vblo=1,632.99 2006.239.07:34:39.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:34:39.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:34:39.58#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:39.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:39.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:39.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:39.58#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:34:39.58#ibcon#first serial, iclass 30, count 0 2006.239.07:34:39.58#ibcon#enter sib2, iclass 30, count 0 2006.239.07:34:39.58#ibcon#flushed, iclass 30, count 0 2006.239.07:34:39.58#ibcon#about to write, iclass 30, count 0 2006.239.07:34:39.58#ibcon#wrote, iclass 30, count 0 2006.239.07:34:39.58#ibcon#about to read 3, iclass 30, count 0 2006.239.07:34:39.59#ibcon#read 3, iclass 30, count 0 2006.239.07:34:39.59#ibcon#about to read 4, iclass 30, count 0 2006.239.07:34:39.59#ibcon#read 4, iclass 30, count 0 2006.239.07:34:39.59#ibcon#about to read 5, iclass 30, count 0 2006.239.07:34:39.59#ibcon#read 5, iclass 30, count 0 2006.239.07:34:39.59#ibcon#about to read 6, iclass 30, count 0 2006.239.07:34:39.59#ibcon#read 6, iclass 30, count 0 2006.239.07:34:39.59#ibcon#end of sib2, iclass 30, count 0 2006.239.07:34:39.59#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:34:39.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:34:39.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:34:39.59#ibcon#*before write, iclass 30, count 0 2006.239.07:34:39.59#ibcon#enter sib2, iclass 30, count 0 2006.239.07:34:39.59#ibcon#flushed, iclass 30, count 0 2006.239.07:34:39.59#ibcon#about to write, iclass 30, count 0 2006.239.07:34:39.59#ibcon#wrote, iclass 30, count 0 2006.239.07:34:39.59#ibcon#about to read 3, iclass 30, count 0 2006.239.07:34:39.63#ibcon#read 3, iclass 30, count 0 2006.239.07:34:39.63#ibcon#about to read 4, iclass 30, count 0 2006.239.07:34:39.63#ibcon#read 4, iclass 30, count 0 2006.239.07:34:39.63#ibcon#about to read 5, iclass 30, count 0 2006.239.07:34:39.63#ibcon#read 5, iclass 30, count 0 2006.239.07:34:39.63#ibcon#about to read 6, iclass 30, count 0 2006.239.07:34:39.63#ibcon#read 6, iclass 30, count 0 2006.239.07:34:39.63#ibcon#end of sib2, iclass 30, count 0 2006.239.07:34:39.63#ibcon#*after write, iclass 30, count 0 2006.239.07:34:39.63#ibcon#*before return 0, iclass 30, count 0 2006.239.07:34:39.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:39.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:34:39.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:34:39.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:34:39.63$vc4f8/vb=1,4 2006.239.07:34:39.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:34:39.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:34:39.64#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:39.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:39.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:39.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:39.64#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:34:39.64#ibcon#first serial, iclass 32, count 2 2006.239.07:34:39.64#ibcon#enter sib2, iclass 32, count 2 2006.239.07:34:39.64#ibcon#flushed, iclass 32, count 2 2006.239.07:34:39.64#ibcon#about to write, iclass 32, count 2 2006.239.07:34:39.64#ibcon#wrote, iclass 32, count 2 2006.239.07:34:39.64#ibcon#about to read 3, iclass 32, count 2 2006.239.07:34:39.65#ibcon#read 3, iclass 32, count 2 2006.239.07:34:39.65#ibcon#about to read 4, iclass 32, count 2 2006.239.07:34:39.65#ibcon#read 4, iclass 32, count 2 2006.239.07:34:39.65#ibcon#about to read 5, iclass 32, count 2 2006.239.07:34:39.65#ibcon#read 5, iclass 32, count 2 2006.239.07:34:39.65#ibcon#about to read 6, iclass 32, count 2 2006.239.07:34:39.65#ibcon#read 6, iclass 32, count 2 2006.239.07:34:39.65#ibcon#end of sib2, iclass 32, count 2 2006.239.07:34:39.65#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:34:39.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:34:39.65#ibcon#[27=AT01-04\r\n] 2006.239.07:34:39.65#ibcon#*before write, iclass 32, count 2 2006.239.07:34:39.65#ibcon#enter sib2, iclass 32, count 2 2006.239.07:34:39.65#ibcon#flushed, iclass 32, count 2 2006.239.07:34:39.65#ibcon#about to write, iclass 32, count 2 2006.239.07:34:39.65#ibcon#wrote, iclass 32, count 2 2006.239.07:34:39.65#ibcon#about to read 3, iclass 32, count 2 2006.239.07:34:39.68#ibcon#read 3, iclass 32, count 2 2006.239.07:34:39.68#ibcon#about to read 4, iclass 32, count 2 2006.239.07:34:39.68#ibcon#read 4, iclass 32, count 2 2006.239.07:34:39.68#ibcon#about to read 5, iclass 32, count 2 2006.239.07:34:39.68#ibcon#read 5, iclass 32, count 2 2006.239.07:34:39.68#ibcon#about to read 6, iclass 32, count 2 2006.239.07:34:39.68#ibcon#read 6, iclass 32, count 2 2006.239.07:34:39.68#ibcon#end of sib2, iclass 32, count 2 2006.239.07:34:39.68#ibcon#*after write, iclass 32, count 2 2006.239.07:34:39.68#ibcon#*before return 0, iclass 32, count 2 2006.239.07:34:39.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:39.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:34:39.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:34:39.68#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:39.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:39.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:39.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:39.81#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:34:39.81#ibcon#first serial, iclass 32, count 0 2006.239.07:34:39.81#ibcon#enter sib2, iclass 32, count 0 2006.239.07:34:39.81#ibcon#flushed, iclass 32, count 0 2006.239.07:34:39.81#ibcon#about to write, iclass 32, count 0 2006.239.07:34:39.81#ibcon#wrote, iclass 32, count 0 2006.239.07:34:39.81#ibcon#about to read 3, iclass 32, count 0 2006.239.07:34:39.82#ibcon#read 3, iclass 32, count 0 2006.239.07:34:39.82#ibcon#about to read 4, iclass 32, count 0 2006.239.07:34:39.82#ibcon#read 4, iclass 32, count 0 2006.239.07:34:39.82#ibcon#about to read 5, iclass 32, count 0 2006.239.07:34:39.82#ibcon#read 5, iclass 32, count 0 2006.239.07:34:39.82#ibcon#about to read 6, iclass 32, count 0 2006.239.07:34:39.82#ibcon#read 6, iclass 32, count 0 2006.239.07:34:39.82#ibcon#end of sib2, iclass 32, count 0 2006.239.07:34:39.82#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:34:39.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:34:39.82#ibcon#[27=USB\r\n] 2006.239.07:34:39.82#ibcon#*before write, iclass 32, count 0 2006.239.07:34:39.82#ibcon#enter sib2, iclass 32, count 0 2006.239.07:34:39.82#ibcon#flushed, iclass 32, count 0 2006.239.07:34:39.82#ibcon#about to write, iclass 32, count 0 2006.239.07:34:39.82#ibcon#wrote, iclass 32, count 0 2006.239.07:34:39.82#ibcon#about to read 3, iclass 32, count 0 2006.239.07:34:39.85#ibcon#read 3, iclass 32, count 0 2006.239.07:34:39.85#ibcon#about to read 4, iclass 32, count 0 2006.239.07:34:39.85#ibcon#read 4, iclass 32, count 0 2006.239.07:34:39.85#ibcon#about to read 5, iclass 32, count 0 2006.239.07:34:39.85#ibcon#read 5, iclass 32, count 0 2006.239.07:34:39.85#ibcon#about to read 6, iclass 32, count 0 2006.239.07:34:39.85#ibcon#read 6, iclass 32, count 0 2006.239.07:34:39.85#ibcon#end of sib2, iclass 32, count 0 2006.239.07:34:39.85#ibcon#*after write, iclass 32, count 0 2006.239.07:34:39.85#ibcon#*before return 0, iclass 32, count 0 2006.239.07:34:39.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:39.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:34:39.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:34:39.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:34:39.85$vc4f8/vblo=2,640.99 2006.239.07:34:39.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:34:39.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:34:39.86#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:39.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:39.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:39.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:39.86#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:34:39.86#ibcon#first serial, iclass 34, count 0 2006.239.07:34:39.86#ibcon#enter sib2, iclass 34, count 0 2006.239.07:34:39.86#ibcon#flushed, iclass 34, count 0 2006.239.07:34:39.86#ibcon#about to write, iclass 34, count 0 2006.239.07:34:39.86#ibcon#wrote, iclass 34, count 0 2006.239.07:34:39.86#ibcon#about to read 3, iclass 34, count 0 2006.239.07:34:39.87#ibcon#read 3, iclass 34, count 0 2006.239.07:34:39.87#ibcon#about to read 4, iclass 34, count 0 2006.239.07:34:39.87#ibcon#read 4, iclass 34, count 0 2006.239.07:34:39.87#ibcon#about to read 5, iclass 34, count 0 2006.239.07:34:39.87#ibcon#read 5, iclass 34, count 0 2006.239.07:34:39.87#ibcon#about to read 6, iclass 34, count 0 2006.239.07:34:39.87#ibcon#read 6, iclass 34, count 0 2006.239.07:34:39.87#ibcon#end of sib2, iclass 34, count 0 2006.239.07:34:39.87#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:34:39.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:34:39.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:34:39.87#ibcon#*before write, iclass 34, count 0 2006.239.07:34:39.87#ibcon#enter sib2, iclass 34, count 0 2006.239.07:34:39.87#ibcon#flushed, iclass 34, count 0 2006.239.07:34:39.87#ibcon#about to write, iclass 34, count 0 2006.239.07:34:39.87#ibcon#wrote, iclass 34, count 0 2006.239.07:34:39.87#ibcon#about to read 3, iclass 34, count 0 2006.239.07:34:39.91#ibcon#read 3, iclass 34, count 0 2006.239.07:34:39.91#ibcon#about to read 4, iclass 34, count 0 2006.239.07:34:39.91#ibcon#read 4, iclass 34, count 0 2006.239.07:34:39.91#ibcon#about to read 5, iclass 34, count 0 2006.239.07:34:39.91#ibcon#read 5, iclass 34, count 0 2006.239.07:34:39.91#ibcon#about to read 6, iclass 34, count 0 2006.239.07:34:39.91#ibcon#read 6, iclass 34, count 0 2006.239.07:34:39.91#ibcon#end of sib2, iclass 34, count 0 2006.239.07:34:39.91#ibcon#*after write, iclass 34, count 0 2006.239.07:34:39.91#ibcon#*before return 0, iclass 34, count 0 2006.239.07:34:39.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:39.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:34:39.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:34:39.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:34:39.92$vc4f8/vb=2,4 2006.239.07:34:39.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:34:39.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:34:39.92#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:39.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:39.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:39.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:39.96#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:34:39.96#ibcon#first serial, iclass 36, count 2 2006.239.07:34:39.96#ibcon#enter sib2, iclass 36, count 2 2006.239.07:34:39.96#ibcon#flushed, iclass 36, count 2 2006.239.07:34:39.96#ibcon#about to write, iclass 36, count 2 2006.239.07:34:39.96#ibcon#wrote, iclass 36, count 2 2006.239.07:34:39.96#ibcon#about to read 3, iclass 36, count 2 2006.239.07:34:39.98#ibcon#read 3, iclass 36, count 2 2006.239.07:34:39.98#ibcon#about to read 4, iclass 36, count 2 2006.239.07:34:39.98#ibcon#read 4, iclass 36, count 2 2006.239.07:34:39.98#ibcon#about to read 5, iclass 36, count 2 2006.239.07:34:39.98#ibcon#read 5, iclass 36, count 2 2006.239.07:34:39.98#ibcon#about to read 6, iclass 36, count 2 2006.239.07:34:39.98#ibcon#read 6, iclass 36, count 2 2006.239.07:34:39.98#ibcon#end of sib2, iclass 36, count 2 2006.239.07:34:39.98#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:34:39.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:34:39.98#ibcon#[27=AT02-04\r\n] 2006.239.07:34:39.98#ibcon#*before write, iclass 36, count 2 2006.239.07:34:39.98#ibcon#enter sib2, iclass 36, count 2 2006.239.07:34:39.98#ibcon#flushed, iclass 36, count 2 2006.239.07:34:39.98#ibcon#about to write, iclass 36, count 2 2006.239.07:34:39.98#ibcon#wrote, iclass 36, count 2 2006.239.07:34:39.98#ibcon#about to read 3, iclass 36, count 2 2006.239.07:34:40.02#ibcon#read 3, iclass 36, count 2 2006.239.07:34:40.02#ibcon#about to read 4, iclass 36, count 2 2006.239.07:34:40.02#ibcon#read 4, iclass 36, count 2 2006.239.07:34:40.02#ibcon#about to read 5, iclass 36, count 2 2006.239.07:34:40.02#ibcon#read 5, iclass 36, count 2 2006.239.07:34:40.02#ibcon#about to read 6, iclass 36, count 2 2006.239.07:34:40.02#ibcon#read 6, iclass 36, count 2 2006.239.07:34:40.02#ibcon#end of sib2, iclass 36, count 2 2006.239.07:34:40.02#ibcon#*after write, iclass 36, count 2 2006.239.07:34:40.02#ibcon#*before return 0, iclass 36, count 2 2006.239.07:34:40.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:40.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:34:40.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:34:40.02#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:40.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:40.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:40.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:40.14#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:34:40.14#ibcon#first serial, iclass 36, count 0 2006.239.07:34:40.14#ibcon#enter sib2, iclass 36, count 0 2006.239.07:34:40.14#ibcon#flushed, iclass 36, count 0 2006.239.07:34:40.14#ibcon#about to write, iclass 36, count 0 2006.239.07:34:40.14#ibcon#wrote, iclass 36, count 0 2006.239.07:34:40.14#ibcon#about to read 3, iclass 36, count 0 2006.239.07:34:40.15#ibcon#read 3, iclass 36, count 0 2006.239.07:34:40.15#ibcon#about to read 4, iclass 36, count 0 2006.239.07:34:40.15#ibcon#read 4, iclass 36, count 0 2006.239.07:34:40.15#ibcon#about to read 5, iclass 36, count 0 2006.239.07:34:40.15#ibcon#read 5, iclass 36, count 0 2006.239.07:34:40.15#ibcon#about to read 6, iclass 36, count 0 2006.239.07:34:40.15#ibcon#read 6, iclass 36, count 0 2006.239.07:34:40.15#ibcon#end of sib2, iclass 36, count 0 2006.239.07:34:40.15#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:34:40.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:34:40.15#ibcon#[27=USB\r\n] 2006.239.07:34:40.15#ibcon#*before write, iclass 36, count 0 2006.239.07:34:40.15#ibcon#enter sib2, iclass 36, count 0 2006.239.07:34:40.15#ibcon#flushed, iclass 36, count 0 2006.239.07:34:40.15#ibcon#about to write, iclass 36, count 0 2006.239.07:34:40.15#ibcon#wrote, iclass 36, count 0 2006.239.07:34:40.15#ibcon#about to read 3, iclass 36, count 0 2006.239.07:34:40.18#ibcon#read 3, iclass 36, count 0 2006.239.07:34:40.18#ibcon#about to read 4, iclass 36, count 0 2006.239.07:34:40.18#ibcon#read 4, iclass 36, count 0 2006.239.07:34:40.18#ibcon#about to read 5, iclass 36, count 0 2006.239.07:34:40.18#ibcon#read 5, iclass 36, count 0 2006.239.07:34:40.18#ibcon#about to read 6, iclass 36, count 0 2006.239.07:34:40.18#ibcon#read 6, iclass 36, count 0 2006.239.07:34:40.18#ibcon#end of sib2, iclass 36, count 0 2006.239.07:34:40.18#ibcon#*after write, iclass 36, count 0 2006.239.07:34:40.18#ibcon#*before return 0, iclass 36, count 0 2006.239.07:34:40.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:40.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:34:40.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:34:40.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:34:40.19$vc4f8/vblo=3,656.99 2006.239.07:34:40.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.07:34:40.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.07:34:40.19#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:40.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:34:40.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:34:40.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:34:40.19#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:34:40.19#ibcon#first serial, iclass 38, count 0 2006.239.07:34:40.19#ibcon#enter sib2, iclass 38, count 0 2006.239.07:34:40.19#ibcon#flushed, iclass 38, count 0 2006.239.07:34:40.19#ibcon#about to write, iclass 38, count 0 2006.239.07:34:40.19#ibcon#wrote, iclass 38, count 0 2006.239.07:34:40.19#ibcon#about to read 3, iclass 38, count 0 2006.239.07:34:40.20#ibcon#read 3, iclass 38, count 0 2006.239.07:34:40.20#ibcon#about to read 4, iclass 38, count 0 2006.239.07:34:40.20#ibcon#read 4, iclass 38, count 0 2006.239.07:34:40.20#ibcon#about to read 5, iclass 38, count 0 2006.239.07:34:40.20#ibcon#read 5, iclass 38, count 0 2006.239.07:34:40.20#ibcon#about to read 6, iclass 38, count 0 2006.239.07:34:40.20#ibcon#read 6, iclass 38, count 0 2006.239.07:34:40.20#ibcon#end of sib2, iclass 38, count 0 2006.239.07:34:40.20#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:34:40.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:34:40.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:34:40.20#ibcon#*before write, iclass 38, count 0 2006.239.07:34:40.20#ibcon#enter sib2, iclass 38, count 0 2006.239.07:34:40.20#ibcon#flushed, iclass 38, count 0 2006.239.07:34:40.20#ibcon#about to write, iclass 38, count 0 2006.239.07:34:40.20#ibcon#wrote, iclass 38, count 0 2006.239.07:34:40.20#ibcon#about to read 3, iclass 38, count 0 2006.239.07:34:40.24#ibcon#read 3, iclass 38, count 0 2006.239.07:34:40.24#ibcon#about to read 4, iclass 38, count 0 2006.239.07:34:40.24#ibcon#read 4, iclass 38, count 0 2006.239.07:34:40.24#ibcon#about to read 5, iclass 38, count 0 2006.239.07:34:40.24#ibcon#read 5, iclass 38, count 0 2006.239.07:34:40.24#ibcon#about to read 6, iclass 38, count 0 2006.239.07:34:40.24#ibcon#read 6, iclass 38, count 0 2006.239.07:34:40.24#ibcon#end of sib2, iclass 38, count 0 2006.239.07:34:40.24#ibcon#*after write, iclass 38, count 0 2006.239.07:34:40.24#ibcon#*before return 0, iclass 38, count 0 2006.239.07:34:40.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:34:40.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:34:40.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:34:40.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:34:40.24$vc4f8/vb=3,4 2006.239.07:34:40.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.07:34:40.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.07:34:40.25#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:40.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:34:40.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:34:40.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:34:40.29#ibcon#enter wrdev, iclass 40, count 2 2006.239.07:34:40.29#ibcon#first serial, iclass 40, count 2 2006.239.07:34:40.29#ibcon#enter sib2, iclass 40, count 2 2006.239.07:34:40.29#ibcon#flushed, iclass 40, count 2 2006.239.07:34:40.29#ibcon#about to write, iclass 40, count 2 2006.239.07:34:40.29#ibcon#wrote, iclass 40, count 2 2006.239.07:34:40.29#ibcon#about to read 3, iclass 40, count 2 2006.239.07:34:40.31#ibcon#read 3, iclass 40, count 2 2006.239.07:34:40.31#ibcon#about to read 4, iclass 40, count 2 2006.239.07:34:40.31#ibcon#read 4, iclass 40, count 2 2006.239.07:34:40.31#ibcon#about to read 5, iclass 40, count 2 2006.239.07:34:40.31#ibcon#read 5, iclass 40, count 2 2006.239.07:34:40.31#ibcon#about to read 6, iclass 40, count 2 2006.239.07:34:40.31#ibcon#read 6, iclass 40, count 2 2006.239.07:34:40.31#ibcon#end of sib2, iclass 40, count 2 2006.239.07:34:40.31#ibcon#*mode == 0, iclass 40, count 2 2006.239.07:34:40.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.07:34:40.31#ibcon#[27=AT03-04\r\n] 2006.239.07:34:40.31#ibcon#*before write, iclass 40, count 2 2006.239.07:34:40.31#ibcon#enter sib2, iclass 40, count 2 2006.239.07:34:40.31#ibcon#flushed, iclass 40, count 2 2006.239.07:34:40.31#ibcon#about to write, iclass 40, count 2 2006.239.07:34:40.31#ibcon#wrote, iclass 40, count 2 2006.239.07:34:40.31#ibcon#about to read 3, iclass 40, count 2 2006.239.07:34:40.34#ibcon#read 3, iclass 40, count 2 2006.239.07:34:40.34#ibcon#about to read 4, iclass 40, count 2 2006.239.07:34:40.34#ibcon#read 4, iclass 40, count 2 2006.239.07:34:40.34#ibcon#about to read 5, iclass 40, count 2 2006.239.07:34:40.34#ibcon#read 5, iclass 40, count 2 2006.239.07:34:40.34#ibcon#about to read 6, iclass 40, count 2 2006.239.07:34:40.34#ibcon#read 6, iclass 40, count 2 2006.239.07:34:40.34#ibcon#end of sib2, iclass 40, count 2 2006.239.07:34:40.34#ibcon#*after write, iclass 40, count 2 2006.239.07:34:40.34#ibcon#*before return 0, iclass 40, count 2 2006.239.07:34:40.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:34:40.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:34:40.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.07:34:40.34#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:40.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:34:40.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:34:40.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:34:40.46#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:34:40.46#ibcon#first serial, iclass 40, count 0 2006.239.07:34:40.46#ibcon#enter sib2, iclass 40, count 0 2006.239.07:34:40.46#ibcon#flushed, iclass 40, count 0 2006.239.07:34:40.46#ibcon#about to write, iclass 40, count 0 2006.239.07:34:40.46#ibcon#wrote, iclass 40, count 0 2006.239.07:34:40.46#ibcon#about to read 3, iclass 40, count 0 2006.239.07:34:40.48#ibcon#read 3, iclass 40, count 0 2006.239.07:34:40.48#ibcon#about to read 4, iclass 40, count 0 2006.239.07:34:40.48#ibcon#read 4, iclass 40, count 0 2006.239.07:34:40.48#ibcon#about to read 5, iclass 40, count 0 2006.239.07:34:40.48#ibcon#read 5, iclass 40, count 0 2006.239.07:34:40.48#ibcon#about to read 6, iclass 40, count 0 2006.239.07:34:40.48#ibcon#read 6, iclass 40, count 0 2006.239.07:34:40.48#ibcon#end of sib2, iclass 40, count 0 2006.239.07:34:40.48#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:34:40.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:34:40.48#ibcon#[27=USB\r\n] 2006.239.07:34:40.48#ibcon#*before write, iclass 40, count 0 2006.239.07:34:40.48#ibcon#enter sib2, iclass 40, count 0 2006.239.07:34:40.48#ibcon#flushed, iclass 40, count 0 2006.239.07:34:40.48#ibcon#about to write, iclass 40, count 0 2006.239.07:34:40.48#ibcon#wrote, iclass 40, count 0 2006.239.07:34:40.48#ibcon#about to read 3, iclass 40, count 0 2006.239.07:34:40.51#ibcon#read 3, iclass 40, count 0 2006.239.07:34:40.51#ibcon#about to read 4, iclass 40, count 0 2006.239.07:34:40.51#ibcon#read 4, iclass 40, count 0 2006.239.07:34:40.51#ibcon#about to read 5, iclass 40, count 0 2006.239.07:34:40.51#ibcon#read 5, iclass 40, count 0 2006.239.07:34:40.51#ibcon#about to read 6, iclass 40, count 0 2006.239.07:34:40.51#ibcon#read 6, iclass 40, count 0 2006.239.07:34:40.51#ibcon#end of sib2, iclass 40, count 0 2006.239.07:34:40.51#ibcon#*after write, iclass 40, count 0 2006.239.07:34:40.51#ibcon#*before return 0, iclass 40, count 0 2006.239.07:34:40.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:34:40.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:34:40.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:34:40.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:34:40.51$vc4f8/vblo=4,712.99 2006.239.07:34:40.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:34:40.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:34:40.52#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:40.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:40.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:40.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:40.52#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:34:40.52#ibcon#first serial, iclass 4, count 0 2006.239.07:34:40.52#ibcon#enter sib2, iclass 4, count 0 2006.239.07:34:40.52#ibcon#flushed, iclass 4, count 0 2006.239.07:34:40.52#ibcon#about to write, iclass 4, count 0 2006.239.07:34:40.52#ibcon#wrote, iclass 4, count 0 2006.239.07:34:40.52#ibcon#about to read 3, iclass 4, count 0 2006.239.07:34:40.53#ibcon#read 3, iclass 4, count 0 2006.239.07:34:40.53#ibcon#about to read 4, iclass 4, count 0 2006.239.07:34:40.53#ibcon#read 4, iclass 4, count 0 2006.239.07:34:40.53#ibcon#about to read 5, iclass 4, count 0 2006.239.07:34:40.53#ibcon#read 5, iclass 4, count 0 2006.239.07:34:40.53#ibcon#about to read 6, iclass 4, count 0 2006.239.07:34:40.53#ibcon#read 6, iclass 4, count 0 2006.239.07:34:40.53#ibcon#end of sib2, iclass 4, count 0 2006.239.07:34:40.53#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:34:40.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:34:40.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:34:40.53#ibcon#*before write, iclass 4, count 0 2006.239.07:34:40.53#ibcon#enter sib2, iclass 4, count 0 2006.239.07:34:40.53#ibcon#flushed, iclass 4, count 0 2006.239.07:34:40.53#ibcon#about to write, iclass 4, count 0 2006.239.07:34:40.53#ibcon#wrote, iclass 4, count 0 2006.239.07:34:40.53#ibcon#about to read 3, iclass 4, count 0 2006.239.07:34:40.57#ibcon#read 3, iclass 4, count 0 2006.239.07:34:40.57#ibcon#about to read 4, iclass 4, count 0 2006.239.07:34:40.57#ibcon#read 4, iclass 4, count 0 2006.239.07:34:40.57#ibcon#about to read 5, iclass 4, count 0 2006.239.07:34:40.57#ibcon#read 5, iclass 4, count 0 2006.239.07:34:40.57#ibcon#about to read 6, iclass 4, count 0 2006.239.07:34:40.57#ibcon#read 6, iclass 4, count 0 2006.239.07:34:40.57#ibcon#end of sib2, iclass 4, count 0 2006.239.07:34:40.57#ibcon#*after write, iclass 4, count 0 2006.239.07:34:40.57#ibcon#*before return 0, iclass 4, count 0 2006.239.07:34:40.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:40.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:34:40.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:34:40.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:34:40.57$vc4f8/vb=4,4 2006.239.07:34:40.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:34:40.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:34:40.58#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:40.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:40.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:40.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:40.62#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:34:40.62#ibcon#first serial, iclass 6, count 2 2006.239.07:34:40.62#ibcon#enter sib2, iclass 6, count 2 2006.239.07:34:40.62#ibcon#flushed, iclass 6, count 2 2006.239.07:34:40.62#ibcon#about to write, iclass 6, count 2 2006.239.07:34:40.62#ibcon#wrote, iclass 6, count 2 2006.239.07:34:40.62#ibcon#about to read 3, iclass 6, count 2 2006.239.07:34:40.64#ibcon#read 3, iclass 6, count 2 2006.239.07:34:40.64#ibcon#about to read 4, iclass 6, count 2 2006.239.07:34:40.64#ibcon#read 4, iclass 6, count 2 2006.239.07:34:40.64#ibcon#about to read 5, iclass 6, count 2 2006.239.07:34:40.64#ibcon#read 5, iclass 6, count 2 2006.239.07:34:40.64#ibcon#about to read 6, iclass 6, count 2 2006.239.07:34:40.64#ibcon#read 6, iclass 6, count 2 2006.239.07:34:40.64#ibcon#end of sib2, iclass 6, count 2 2006.239.07:34:40.64#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:34:40.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:34:40.64#ibcon#[27=AT04-04\r\n] 2006.239.07:34:40.64#ibcon#*before write, iclass 6, count 2 2006.239.07:34:40.64#ibcon#enter sib2, iclass 6, count 2 2006.239.07:34:40.64#ibcon#flushed, iclass 6, count 2 2006.239.07:34:40.64#ibcon#about to write, iclass 6, count 2 2006.239.07:34:40.64#ibcon#wrote, iclass 6, count 2 2006.239.07:34:40.64#ibcon#about to read 3, iclass 6, count 2 2006.239.07:34:40.67#ibcon#read 3, iclass 6, count 2 2006.239.07:34:40.67#ibcon#about to read 4, iclass 6, count 2 2006.239.07:34:40.67#ibcon#read 4, iclass 6, count 2 2006.239.07:34:40.67#ibcon#about to read 5, iclass 6, count 2 2006.239.07:34:40.67#ibcon#read 5, iclass 6, count 2 2006.239.07:34:40.67#ibcon#about to read 6, iclass 6, count 2 2006.239.07:34:40.67#ibcon#read 6, iclass 6, count 2 2006.239.07:34:40.67#ibcon#end of sib2, iclass 6, count 2 2006.239.07:34:40.67#ibcon#*after write, iclass 6, count 2 2006.239.07:34:40.67#ibcon#*before return 0, iclass 6, count 2 2006.239.07:34:40.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:40.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:34:40.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:34:40.67#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:40.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:40.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:40.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:40.79#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:34:40.79#ibcon#first serial, iclass 6, count 0 2006.239.07:34:40.79#ibcon#enter sib2, iclass 6, count 0 2006.239.07:34:40.79#ibcon#flushed, iclass 6, count 0 2006.239.07:34:40.79#ibcon#about to write, iclass 6, count 0 2006.239.07:34:40.79#ibcon#wrote, iclass 6, count 0 2006.239.07:34:40.79#ibcon#about to read 3, iclass 6, count 0 2006.239.07:34:40.81#ibcon#read 3, iclass 6, count 0 2006.239.07:34:40.81#ibcon#about to read 4, iclass 6, count 0 2006.239.07:34:40.81#ibcon#read 4, iclass 6, count 0 2006.239.07:34:40.81#ibcon#about to read 5, iclass 6, count 0 2006.239.07:34:40.81#ibcon#read 5, iclass 6, count 0 2006.239.07:34:40.81#ibcon#about to read 6, iclass 6, count 0 2006.239.07:34:40.81#ibcon#read 6, iclass 6, count 0 2006.239.07:34:40.81#ibcon#end of sib2, iclass 6, count 0 2006.239.07:34:40.81#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:34:40.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:34:40.81#ibcon#[27=USB\r\n] 2006.239.07:34:40.81#ibcon#*before write, iclass 6, count 0 2006.239.07:34:40.81#ibcon#enter sib2, iclass 6, count 0 2006.239.07:34:40.81#ibcon#flushed, iclass 6, count 0 2006.239.07:34:40.81#ibcon#about to write, iclass 6, count 0 2006.239.07:34:40.81#ibcon#wrote, iclass 6, count 0 2006.239.07:34:40.81#ibcon#about to read 3, iclass 6, count 0 2006.239.07:34:40.84#ibcon#read 3, iclass 6, count 0 2006.239.07:34:40.84#ibcon#about to read 4, iclass 6, count 0 2006.239.07:34:40.84#ibcon#read 4, iclass 6, count 0 2006.239.07:34:40.84#ibcon#about to read 5, iclass 6, count 0 2006.239.07:34:40.84#ibcon#read 5, iclass 6, count 0 2006.239.07:34:40.84#ibcon#about to read 6, iclass 6, count 0 2006.239.07:34:40.84#ibcon#read 6, iclass 6, count 0 2006.239.07:34:40.84#ibcon#end of sib2, iclass 6, count 0 2006.239.07:34:40.84#ibcon#*after write, iclass 6, count 0 2006.239.07:34:40.84#ibcon#*before return 0, iclass 6, count 0 2006.239.07:34:40.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:40.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:34:40.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:34:40.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:34:40.84$vc4f8/vblo=5,744.99 2006.239.07:34:40.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:34:40.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:34:40.85#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:40.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:40.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:40.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:40.85#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:34:40.85#ibcon#first serial, iclass 10, count 0 2006.239.07:34:40.85#ibcon#enter sib2, iclass 10, count 0 2006.239.07:34:40.85#ibcon#flushed, iclass 10, count 0 2006.239.07:34:40.85#ibcon#about to write, iclass 10, count 0 2006.239.07:34:40.85#ibcon#wrote, iclass 10, count 0 2006.239.07:34:40.85#ibcon#about to read 3, iclass 10, count 0 2006.239.07:34:40.87#ibcon#read 3, iclass 10, count 0 2006.239.07:34:40.87#ibcon#about to read 4, iclass 10, count 0 2006.239.07:34:40.87#ibcon#read 4, iclass 10, count 0 2006.239.07:34:40.87#ibcon#about to read 5, iclass 10, count 0 2006.239.07:34:40.87#ibcon#read 5, iclass 10, count 0 2006.239.07:34:40.87#ibcon#about to read 6, iclass 10, count 0 2006.239.07:34:40.87#ibcon#read 6, iclass 10, count 0 2006.239.07:34:40.87#ibcon#end of sib2, iclass 10, count 0 2006.239.07:34:40.87#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:34:40.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:34:40.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:34:40.87#ibcon#*before write, iclass 10, count 0 2006.239.07:34:40.87#ibcon#enter sib2, iclass 10, count 0 2006.239.07:34:40.87#ibcon#flushed, iclass 10, count 0 2006.239.07:34:40.87#ibcon#about to write, iclass 10, count 0 2006.239.07:34:40.87#ibcon#wrote, iclass 10, count 0 2006.239.07:34:40.87#ibcon#about to read 3, iclass 10, count 0 2006.239.07:34:40.91#ibcon#read 3, iclass 10, count 0 2006.239.07:34:40.91#ibcon#about to read 4, iclass 10, count 0 2006.239.07:34:40.91#ibcon#read 4, iclass 10, count 0 2006.239.07:34:40.91#ibcon#about to read 5, iclass 10, count 0 2006.239.07:34:40.91#ibcon#read 5, iclass 10, count 0 2006.239.07:34:40.91#ibcon#about to read 6, iclass 10, count 0 2006.239.07:34:40.91#ibcon#read 6, iclass 10, count 0 2006.239.07:34:40.91#ibcon#end of sib2, iclass 10, count 0 2006.239.07:34:40.91#ibcon#*after write, iclass 10, count 0 2006.239.07:34:40.91#ibcon#*before return 0, iclass 10, count 0 2006.239.07:34:40.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:40.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:34:40.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:34:40.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:34:40.91$vc4f8/vb=5,4 2006.239.07:34:40.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.07:34:40.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.07:34:40.92#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:40.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:40.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:40.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:40.95#ibcon#enter wrdev, iclass 12, count 2 2006.239.07:34:40.95#ibcon#first serial, iclass 12, count 2 2006.239.07:34:40.95#ibcon#enter sib2, iclass 12, count 2 2006.239.07:34:40.95#ibcon#flushed, iclass 12, count 2 2006.239.07:34:40.95#ibcon#about to write, iclass 12, count 2 2006.239.07:34:40.95#ibcon#wrote, iclass 12, count 2 2006.239.07:34:40.95#ibcon#about to read 3, iclass 12, count 2 2006.239.07:34:40.97#ibcon#read 3, iclass 12, count 2 2006.239.07:34:40.97#ibcon#about to read 4, iclass 12, count 2 2006.239.07:34:40.97#ibcon#read 4, iclass 12, count 2 2006.239.07:34:40.97#ibcon#about to read 5, iclass 12, count 2 2006.239.07:34:40.97#ibcon#read 5, iclass 12, count 2 2006.239.07:34:40.97#ibcon#about to read 6, iclass 12, count 2 2006.239.07:34:40.97#ibcon#read 6, iclass 12, count 2 2006.239.07:34:40.97#ibcon#end of sib2, iclass 12, count 2 2006.239.07:34:40.97#ibcon#*mode == 0, iclass 12, count 2 2006.239.07:34:40.97#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.07:34:40.97#ibcon#[27=AT05-04\r\n] 2006.239.07:34:40.97#ibcon#*before write, iclass 12, count 2 2006.239.07:34:40.97#ibcon#enter sib2, iclass 12, count 2 2006.239.07:34:40.97#ibcon#flushed, iclass 12, count 2 2006.239.07:34:40.97#ibcon#about to write, iclass 12, count 2 2006.239.07:34:40.97#ibcon#wrote, iclass 12, count 2 2006.239.07:34:40.97#ibcon#about to read 3, iclass 12, count 2 2006.239.07:34:41.00#ibcon#read 3, iclass 12, count 2 2006.239.07:34:41.00#ibcon#about to read 4, iclass 12, count 2 2006.239.07:34:41.00#ibcon#read 4, iclass 12, count 2 2006.239.07:34:41.00#ibcon#about to read 5, iclass 12, count 2 2006.239.07:34:41.00#ibcon#read 5, iclass 12, count 2 2006.239.07:34:41.00#ibcon#about to read 6, iclass 12, count 2 2006.239.07:34:41.00#ibcon#read 6, iclass 12, count 2 2006.239.07:34:41.00#ibcon#end of sib2, iclass 12, count 2 2006.239.07:34:41.00#ibcon#*after write, iclass 12, count 2 2006.239.07:34:41.00#ibcon#*before return 0, iclass 12, count 2 2006.239.07:34:41.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:41.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:34:41.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.07:34:41.00#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:41.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:41.12#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:41.12#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:41.12#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:34:41.12#ibcon#first serial, iclass 12, count 0 2006.239.07:34:41.12#ibcon#enter sib2, iclass 12, count 0 2006.239.07:34:41.12#ibcon#flushed, iclass 12, count 0 2006.239.07:34:41.12#ibcon#about to write, iclass 12, count 0 2006.239.07:34:41.12#ibcon#wrote, iclass 12, count 0 2006.239.07:34:41.12#ibcon#about to read 3, iclass 12, count 0 2006.239.07:34:41.14#ibcon#read 3, iclass 12, count 0 2006.239.07:34:41.14#ibcon#about to read 4, iclass 12, count 0 2006.239.07:34:41.14#ibcon#read 4, iclass 12, count 0 2006.239.07:34:41.14#ibcon#about to read 5, iclass 12, count 0 2006.239.07:34:41.14#ibcon#read 5, iclass 12, count 0 2006.239.07:34:41.14#ibcon#about to read 6, iclass 12, count 0 2006.239.07:34:41.14#ibcon#read 6, iclass 12, count 0 2006.239.07:34:41.14#ibcon#end of sib2, iclass 12, count 0 2006.239.07:34:41.14#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:34:41.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:34:41.14#ibcon#[27=USB\r\n] 2006.239.07:34:41.14#ibcon#*before write, iclass 12, count 0 2006.239.07:34:41.14#ibcon#enter sib2, iclass 12, count 0 2006.239.07:34:41.14#ibcon#flushed, iclass 12, count 0 2006.239.07:34:41.14#ibcon#about to write, iclass 12, count 0 2006.239.07:34:41.14#ibcon#wrote, iclass 12, count 0 2006.239.07:34:41.14#ibcon#about to read 3, iclass 12, count 0 2006.239.07:34:41.17#ibcon#read 3, iclass 12, count 0 2006.239.07:34:41.17#ibcon#about to read 4, iclass 12, count 0 2006.239.07:34:41.17#ibcon#read 4, iclass 12, count 0 2006.239.07:34:41.17#ibcon#about to read 5, iclass 12, count 0 2006.239.07:34:41.17#ibcon#read 5, iclass 12, count 0 2006.239.07:34:41.17#ibcon#about to read 6, iclass 12, count 0 2006.239.07:34:41.17#ibcon#read 6, iclass 12, count 0 2006.239.07:34:41.17#ibcon#end of sib2, iclass 12, count 0 2006.239.07:34:41.17#ibcon#*after write, iclass 12, count 0 2006.239.07:34:41.17#ibcon#*before return 0, iclass 12, count 0 2006.239.07:34:41.17#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:41.17#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:34:41.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:34:41.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:34:41.17$vc4f8/vblo=6,752.99 2006.239.07:34:41.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:34:41.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:34:41.18#ibcon#ireg 17 cls_cnt 0 2006.239.07:34:41.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:41.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:41.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:41.18#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:34:41.18#ibcon#first serial, iclass 14, count 0 2006.239.07:34:41.18#ibcon#enter sib2, iclass 14, count 0 2006.239.07:34:41.18#ibcon#flushed, iclass 14, count 0 2006.239.07:34:41.18#ibcon#about to write, iclass 14, count 0 2006.239.07:34:41.18#ibcon#wrote, iclass 14, count 0 2006.239.07:34:41.18#ibcon#about to read 3, iclass 14, count 0 2006.239.07:34:41.19#ibcon#read 3, iclass 14, count 0 2006.239.07:34:41.19#ibcon#about to read 4, iclass 14, count 0 2006.239.07:34:41.19#ibcon#read 4, iclass 14, count 0 2006.239.07:34:41.19#ibcon#about to read 5, iclass 14, count 0 2006.239.07:34:41.19#ibcon#read 5, iclass 14, count 0 2006.239.07:34:41.19#ibcon#about to read 6, iclass 14, count 0 2006.239.07:34:41.19#ibcon#read 6, iclass 14, count 0 2006.239.07:34:41.19#ibcon#end of sib2, iclass 14, count 0 2006.239.07:34:41.19#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:34:41.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:34:41.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:34:41.19#ibcon#*before write, iclass 14, count 0 2006.239.07:34:41.19#ibcon#enter sib2, iclass 14, count 0 2006.239.07:34:41.19#ibcon#flushed, iclass 14, count 0 2006.239.07:34:41.19#ibcon#about to write, iclass 14, count 0 2006.239.07:34:41.19#ibcon#wrote, iclass 14, count 0 2006.239.07:34:41.19#ibcon#about to read 3, iclass 14, count 0 2006.239.07:34:41.23#ibcon#read 3, iclass 14, count 0 2006.239.07:34:41.23#ibcon#about to read 4, iclass 14, count 0 2006.239.07:34:41.23#ibcon#read 4, iclass 14, count 0 2006.239.07:34:41.23#ibcon#about to read 5, iclass 14, count 0 2006.239.07:34:41.23#ibcon#read 5, iclass 14, count 0 2006.239.07:34:41.23#ibcon#about to read 6, iclass 14, count 0 2006.239.07:34:41.23#ibcon#read 6, iclass 14, count 0 2006.239.07:34:41.23#ibcon#end of sib2, iclass 14, count 0 2006.239.07:34:41.23#ibcon#*after write, iclass 14, count 0 2006.239.07:34:41.23#ibcon#*before return 0, iclass 14, count 0 2006.239.07:34:41.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:41.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:34:41.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:34:41.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:34:41.23$vc4f8/vb=6,4 2006.239.07:34:41.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:34:41.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:34:41.24#ibcon#ireg 11 cls_cnt 2 2006.239.07:34:41.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:41.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:41.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:41.28#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:34:41.28#ibcon#first serial, iclass 16, count 2 2006.239.07:34:41.28#ibcon#enter sib2, iclass 16, count 2 2006.239.07:34:41.28#ibcon#flushed, iclass 16, count 2 2006.239.07:34:41.28#ibcon#about to write, iclass 16, count 2 2006.239.07:34:41.28#ibcon#wrote, iclass 16, count 2 2006.239.07:34:41.28#ibcon#about to read 3, iclass 16, count 2 2006.239.07:34:41.30#ibcon#read 3, iclass 16, count 2 2006.239.07:34:41.30#ibcon#about to read 4, iclass 16, count 2 2006.239.07:34:41.30#ibcon#read 4, iclass 16, count 2 2006.239.07:34:41.30#ibcon#about to read 5, iclass 16, count 2 2006.239.07:34:41.30#ibcon#read 5, iclass 16, count 2 2006.239.07:34:41.30#ibcon#about to read 6, iclass 16, count 2 2006.239.07:34:41.30#ibcon#read 6, iclass 16, count 2 2006.239.07:34:41.30#ibcon#end of sib2, iclass 16, count 2 2006.239.07:34:41.30#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:34:41.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:34:41.30#ibcon#[27=AT06-04\r\n] 2006.239.07:34:41.30#ibcon#*before write, iclass 16, count 2 2006.239.07:34:41.30#ibcon#enter sib2, iclass 16, count 2 2006.239.07:34:41.30#ibcon#flushed, iclass 16, count 2 2006.239.07:34:41.30#ibcon#about to write, iclass 16, count 2 2006.239.07:34:41.30#ibcon#wrote, iclass 16, count 2 2006.239.07:34:41.30#ibcon#about to read 3, iclass 16, count 2 2006.239.07:34:41.33#ibcon#read 3, iclass 16, count 2 2006.239.07:34:41.33#ibcon#about to read 4, iclass 16, count 2 2006.239.07:34:41.33#ibcon#read 4, iclass 16, count 2 2006.239.07:34:41.33#ibcon#about to read 5, iclass 16, count 2 2006.239.07:34:41.33#ibcon#read 5, iclass 16, count 2 2006.239.07:34:41.33#ibcon#about to read 6, iclass 16, count 2 2006.239.07:34:41.33#ibcon#read 6, iclass 16, count 2 2006.239.07:34:41.33#ibcon#end of sib2, iclass 16, count 2 2006.239.07:34:41.33#ibcon#*after write, iclass 16, count 2 2006.239.07:34:41.33#ibcon#*before return 0, iclass 16, count 2 2006.239.07:34:41.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:41.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:34:41.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:34:41.33#ibcon#ireg 7 cls_cnt 0 2006.239.07:34:41.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:41.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:41.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:41.45#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:34:41.46#ibcon#first serial, iclass 16, count 0 2006.239.07:34:41.46#ibcon#enter sib2, iclass 16, count 0 2006.239.07:34:41.46#ibcon#flushed, iclass 16, count 0 2006.239.07:34:41.46#ibcon#about to write, iclass 16, count 0 2006.239.07:34:41.46#ibcon#wrote, iclass 16, count 0 2006.239.07:34:41.46#ibcon#about to read 3, iclass 16, count 0 2006.239.07:34:41.47#ibcon#read 3, iclass 16, count 0 2006.239.07:34:41.47#ibcon#about to read 4, iclass 16, count 0 2006.239.07:34:41.47#ibcon#read 4, iclass 16, count 0 2006.239.07:34:41.47#ibcon#about to read 5, iclass 16, count 0 2006.239.07:34:41.47#ibcon#read 5, iclass 16, count 0 2006.239.07:34:41.47#ibcon#about to read 6, iclass 16, count 0 2006.239.07:34:41.47#ibcon#read 6, iclass 16, count 0 2006.239.07:34:41.47#ibcon#end of sib2, iclass 16, count 0 2006.239.07:34:41.47#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:34:41.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:34:41.47#ibcon#[27=USB\r\n] 2006.239.07:34:41.47#ibcon#*before write, iclass 16, count 0 2006.239.07:34:41.47#ibcon#enter sib2, iclass 16, count 0 2006.239.07:34:41.47#ibcon#flushed, iclass 16, count 0 2006.239.07:34:41.47#ibcon#about to write, iclass 16, count 0 2006.239.07:34:41.47#ibcon#wrote, iclass 16, count 0 2006.239.07:34:41.47#ibcon#about to read 3, iclass 16, count 0 2006.239.07:34:41.50#ibcon#read 3, iclass 16, count 0 2006.239.07:34:41.50#ibcon#about to read 4, iclass 16, count 0 2006.239.07:34:41.50#ibcon#read 4, iclass 16, count 0 2006.239.07:34:41.50#ibcon#about to read 5, iclass 16, count 0 2006.239.07:34:41.50#ibcon#read 5, iclass 16, count 0 2006.239.07:34:41.50#ibcon#about to read 6, iclass 16, count 0 2006.239.07:34:41.50#ibcon#read 6, iclass 16, count 0 2006.239.07:34:41.50#ibcon#end of sib2, iclass 16, count 0 2006.239.07:34:41.50#ibcon#*after write, iclass 16, count 0 2006.239.07:34:41.50#ibcon#*before return 0, iclass 16, count 0 2006.239.07:34:41.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:41.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:34:41.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:34:41.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:34:41.50$vc4f8/vabw=wide 2006.239.07:34:41.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.07:34:41.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.07:34:41.51#ibcon#ireg 8 cls_cnt 0 2006.239.07:34:41.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:41.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:41.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:41.51#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:34:41.51#ibcon#first serial, iclass 18, count 0 2006.239.07:34:41.51#ibcon#enter sib2, iclass 18, count 0 2006.239.07:34:41.51#ibcon#flushed, iclass 18, count 0 2006.239.07:34:41.51#ibcon#about to write, iclass 18, count 0 2006.239.07:34:41.51#ibcon#wrote, iclass 18, count 0 2006.239.07:34:41.51#ibcon#about to read 3, iclass 18, count 0 2006.239.07:34:41.52#ibcon#read 3, iclass 18, count 0 2006.239.07:34:41.52#ibcon#about to read 4, iclass 18, count 0 2006.239.07:34:41.52#ibcon#read 4, iclass 18, count 0 2006.239.07:34:41.52#ibcon#about to read 5, iclass 18, count 0 2006.239.07:34:41.52#ibcon#read 5, iclass 18, count 0 2006.239.07:34:41.52#ibcon#about to read 6, iclass 18, count 0 2006.239.07:34:41.52#ibcon#read 6, iclass 18, count 0 2006.239.07:34:41.52#ibcon#end of sib2, iclass 18, count 0 2006.239.07:34:41.52#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:34:41.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:34:41.52#ibcon#[25=BW32\r\n] 2006.239.07:34:41.52#ibcon#*before write, iclass 18, count 0 2006.239.07:34:41.52#ibcon#enter sib2, iclass 18, count 0 2006.239.07:34:41.52#ibcon#flushed, iclass 18, count 0 2006.239.07:34:41.52#ibcon#about to write, iclass 18, count 0 2006.239.07:34:41.52#ibcon#wrote, iclass 18, count 0 2006.239.07:34:41.52#ibcon#about to read 3, iclass 18, count 0 2006.239.07:34:41.55#ibcon#read 3, iclass 18, count 0 2006.239.07:34:41.55#ibcon#about to read 4, iclass 18, count 0 2006.239.07:34:41.55#ibcon#read 4, iclass 18, count 0 2006.239.07:34:41.55#ibcon#about to read 5, iclass 18, count 0 2006.239.07:34:41.55#ibcon#read 5, iclass 18, count 0 2006.239.07:34:41.55#ibcon#about to read 6, iclass 18, count 0 2006.239.07:34:41.55#ibcon#read 6, iclass 18, count 0 2006.239.07:34:41.55#ibcon#end of sib2, iclass 18, count 0 2006.239.07:34:41.55#ibcon#*after write, iclass 18, count 0 2006.239.07:34:41.55#ibcon#*before return 0, iclass 18, count 0 2006.239.07:34:41.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:41.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:34:41.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:34:41.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:34:41.55$vc4f8/vbbw=wide 2006.239.07:34:41.56#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:34:41.56#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:34:41.56#ibcon#ireg 8 cls_cnt 0 2006.239.07:34:41.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:34:41.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:34:41.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:34:41.61#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:34:41.61#ibcon#first serial, iclass 20, count 0 2006.239.07:34:41.61#ibcon#enter sib2, iclass 20, count 0 2006.239.07:34:41.61#ibcon#flushed, iclass 20, count 0 2006.239.07:34:41.61#ibcon#about to write, iclass 20, count 0 2006.239.07:34:41.61#ibcon#wrote, iclass 20, count 0 2006.239.07:34:41.61#ibcon#about to read 3, iclass 20, count 0 2006.239.07:34:41.63#ibcon#read 3, iclass 20, count 0 2006.239.07:34:41.63#ibcon#about to read 4, iclass 20, count 0 2006.239.07:34:41.63#ibcon#read 4, iclass 20, count 0 2006.239.07:34:41.63#ibcon#about to read 5, iclass 20, count 0 2006.239.07:34:41.63#ibcon#read 5, iclass 20, count 0 2006.239.07:34:41.63#ibcon#about to read 6, iclass 20, count 0 2006.239.07:34:41.63#ibcon#read 6, iclass 20, count 0 2006.239.07:34:41.63#ibcon#end of sib2, iclass 20, count 0 2006.239.07:34:41.63#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:34:41.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:34:41.63#ibcon#[27=BW32\r\n] 2006.239.07:34:41.63#ibcon#*before write, iclass 20, count 0 2006.239.07:34:41.63#ibcon#enter sib2, iclass 20, count 0 2006.239.07:34:41.63#ibcon#flushed, iclass 20, count 0 2006.239.07:34:41.63#ibcon#about to write, iclass 20, count 0 2006.239.07:34:41.63#ibcon#wrote, iclass 20, count 0 2006.239.07:34:41.63#ibcon#about to read 3, iclass 20, count 0 2006.239.07:34:41.66#ibcon#read 3, iclass 20, count 0 2006.239.07:34:41.66#ibcon#about to read 4, iclass 20, count 0 2006.239.07:34:41.66#ibcon#read 4, iclass 20, count 0 2006.239.07:34:41.66#ibcon#about to read 5, iclass 20, count 0 2006.239.07:34:41.66#ibcon#read 5, iclass 20, count 0 2006.239.07:34:41.66#ibcon#about to read 6, iclass 20, count 0 2006.239.07:34:41.66#ibcon#read 6, iclass 20, count 0 2006.239.07:34:41.66#ibcon#end of sib2, iclass 20, count 0 2006.239.07:34:41.66#ibcon#*after write, iclass 20, count 0 2006.239.07:34:41.66#ibcon#*before return 0, iclass 20, count 0 2006.239.07:34:41.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:34:41.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:34:41.66#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:34:41.66#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:34:41.66$4f8m12a/ifd4f 2006.239.07:34:41.67$ifd4f/lo= 2006.239.07:34:41.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:34:41.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:34:41.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:34:41.67$ifd4f/patch= 2006.239.07:34:41.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:34:41.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:34:41.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:34:41.67$4f8m12a/"form=m,16.000,1:2 2006.239.07:34:41.67$4f8m12a/"tpicd 2006.239.07:34:41.67$4f8m12a/echo=off 2006.239.07:34:41.67$4f8m12a/xlog=off 2006.239.07:34:41.67:!2006.239.07:35:10 2006.239.07:34:53.14#trakl#Source acquired 2006.239.07:34:53.15#flagr#flagr/antenna,acquired 2006.239.07:35:10.01:preob 2006.239.07:35:11.14/onsource/TRACKING 2006.239.07:35:11.15:!2006.239.07:35:20 2006.239.07:35:20.01:data_valid=on 2006.239.07:35:20.02:midob 2006.239.07:35:21.14/onsource/TRACKING 2006.239.07:35:21.15/wx/25.38,1011.4,80 2006.239.07:35:21.25/cable/+6.4144E-03 2006.239.07:35:22.34/va/01,08,usb,yes,30,32 2006.239.07:35:22.34/va/02,07,usb,yes,30,32 2006.239.07:35:22.34/va/03,07,usb,yes,29,29 2006.239.07:35:22.34/va/04,07,usb,yes,32,35 2006.239.07:35:22.34/va/05,08,usb,yes,29,31 2006.239.07:35:22.34/va/06,07,usb,yes,32,31 2006.239.07:35:22.34/va/07,07,usb,yes,31,31 2006.239.07:35:22.34/va/08,07,usb,yes,34,34 2006.239.07:35:22.57/valo/01,532.99,yes,locked 2006.239.07:35:22.57/valo/02,572.99,yes,locked 2006.239.07:35:22.57/valo/03,672.99,yes,locked 2006.239.07:35:22.57/valo/04,832.99,yes,locked 2006.239.07:35:22.57/valo/05,652.99,yes,locked 2006.239.07:35:22.57/valo/06,772.99,yes,locked 2006.239.07:35:22.57/valo/07,832.99,yes,locked 2006.239.07:35:22.57/valo/08,852.99,yes,locked 2006.239.07:35:23.66/vb/01,04,usb,yes,30,29 2006.239.07:35:23.66/vb/02,04,usb,yes,32,33 2006.239.07:35:23.66/vb/03,04,usb,yes,28,32 2006.239.07:35:23.66/vb/04,04,usb,yes,29,29 2006.239.07:35:23.66/vb/05,04,usb,yes,27,31 2006.239.07:35:23.66/vb/06,04,usb,yes,28,31 2006.239.07:35:23.66/vb/07,04,usb,yes,30,30 2006.239.07:35:23.66/vb/08,04,usb,yes,28,31 2006.239.07:35:23.90/vblo/01,632.99,yes,locked 2006.239.07:35:23.90/vblo/02,640.99,yes,locked 2006.239.07:35:23.90/vblo/03,656.99,yes,locked 2006.239.07:35:23.90/vblo/04,712.99,yes,locked 2006.239.07:35:23.90/vblo/05,744.99,yes,locked 2006.239.07:35:23.90/vblo/06,752.99,yes,locked 2006.239.07:35:23.90/vblo/07,734.99,yes,locked 2006.239.07:35:23.90/vblo/08,744.99,yes,locked 2006.239.07:35:24.05/vabw/8 2006.239.07:35:24.20/vbbw/8 2006.239.07:35:24.29/xfe/off,on,13.7 2006.239.07:35:24.69/ifatt/23,28,28,28 2006.239.07:35:25.07/fmout-gps/S +4.35E-07 2006.239.07:35:25.12:!2006.239.07:36:20 2006.239.07:36:20.01:data_valid=off 2006.239.07:36:20.02:postob 2006.239.07:36:20.15/cable/+6.4151E-03 2006.239.07:36:20.15/wx/25.38,1011.5,81 2006.239.07:36:20.23/fmout-gps/S +4.34E-07 2006.239.07:36:20.24:scan_name=239-0737,k06239,60 2006.239.07:36:20.24:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.239.07:36:21.14#flagr#flagr/antenna,new-source 2006.239.07:36:21.15:checkk5 2006.239.07:36:21.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:36:21.91/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:36:22.33/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:36:22.70/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:36:23.07/chk_obsdata//k5ts1/T2390735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:36:23.44/chk_obsdata//k5ts2/T2390735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:36:23.82/chk_obsdata//k5ts3/T2390735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:36:24.19/chk_obsdata//k5ts4/T2390735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:36:24.88/k5log//k5ts1_log_newline 2006.239.07:36:25.58/k5log//k5ts2_log_newline 2006.239.07:36:26.27/k5log//k5ts3_log_newline 2006.239.07:36:26.95/k5log//k5ts4_log_newline 2006.239.07:36:26.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:36:26.98:4f8m12a=1 2006.239.07:36:26.98$4f8m12a/echo=on 2006.239.07:36:26.98$4f8m12a/pcalon 2006.239.07:36:26.98$pcalon/"no phase cal control is implemented here 2006.239.07:36:26.98$4f8m12a/"tpicd=stop 2006.239.07:36:26.98$4f8m12a/vc4f8 2006.239.07:36:26.98$vc4f8/valo=1,532.99 2006.239.07:36:26.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.07:36:26.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.07:36:26.98#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:26.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:26.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:26.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:26.98#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:36:26.98#ibcon#first serial, iclass 27, count 0 2006.239.07:36:26.98#ibcon#enter sib2, iclass 27, count 0 2006.239.07:36:26.98#ibcon#flushed, iclass 27, count 0 2006.239.07:36:26.98#ibcon#about to write, iclass 27, count 0 2006.239.07:36:26.98#ibcon#wrote, iclass 27, count 0 2006.239.07:36:26.98#ibcon#about to read 3, iclass 27, count 0 2006.239.07:36:27.03#ibcon#read 3, iclass 27, count 0 2006.239.07:36:27.03#ibcon#about to read 4, iclass 27, count 0 2006.239.07:36:27.03#ibcon#read 4, iclass 27, count 0 2006.239.07:36:27.03#ibcon#about to read 5, iclass 27, count 0 2006.239.07:36:27.03#ibcon#read 5, iclass 27, count 0 2006.239.07:36:27.03#ibcon#about to read 6, iclass 27, count 0 2006.239.07:36:27.03#ibcon#read 6, iclass 27, count 0 2006.239.07:36:27.03#ibcon#end of sib2, iclass 27, count 0 2006.239.07:36:27.03#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:36:27.03#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:36:27.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:36:27.03#ibcon#*before write, iclass 27, count 0 2006.239.07:36:27.03#ibcon#enter sib2, iclass 27, count 0 2006.239.07:36:27.03#ibcon#flushed, iclass 27, count 0 2006.239.07:36:27.03#ibcon#about to write, iclass 27, count 0 2006.239.07:36:27.03#ibcon#wrote, iclass 27, count 0 2006.239.07:36:27.03#ibcon#about to read 3, iclass 27, count 0 2006.239.07:36:27.07#ibcon#read 3, iclass 27, count 0 2006.239.07:36:27.07#ibcon#about to read 4, iclass 27, count 0 2006.239.07:36:27.07#ibcon#read 4, iclass 27, count 0 2006.239.07:36:27.07#ibcon#about to read 5, iclass 27, count 0 2006.239.07:36:27.07#ibcon#read 5, iclass 27, count 0 2006.239.07:36:27.07#ibcon#about to read 6, iclass 27, count 0 2006.239.07:36:27.07#ibcon#read 6, iclass 27, count 0 2006.239.07:36:27.07#ibcon#end of sib2, iclass 27, count 0 2006.239.07:36:27.07#ibcon#*after write, iclass 27, count 0 2006.239.07:36:27.07#ibcon#*before return 0, iclass 27, count 0 2006.239.07:36:27.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:27.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:27.07#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:36:27.07#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:36:27.07$vc4f8/va=1,8 2006.239.07:36:27.07#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.07:36:27.07#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.07:36:27.07#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:27.07#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:27.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:27.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:27.07#ibcon#enter wrdev, iclass 29, count 2 2006.239.07:36:27.07#ibcon#first serial, iclass 29, count 2 2006.239.07:36:27.07#ibcon#enter sib2, iclass 29, count 2 2006.239.07:36:27.07#ibcon#flushed, iclass 29, count 2 2006.239.07:36:27.07#ibcon#about to write, iclass 29, count 2 2006.239.07:36:27.07#ibcon#wrote, iclass 29, count 2 2006.239.07:36:27.07#ibcon#about to read 3, iclass 29, count 2 2006.239.07:36:27.09#ibcon#read 3, iclass 29, count 2 2006.239.07:36:27.09#ibcon#about to read 4, iclass 29, count 2 2006.239.07:36:27.09#ibcon#read 4, iclass 29, count 2 2006.239.07:36:27.09#ibcon#about to read 5, iclass 29, count 2 2006.239.07:36:27.09#ibcon#read 5, iclass 29, count 2 2006.239.07:36:27.09#ibcon#about to read 6, iclass 29, count 2 2006.239.07:36:27.09#ibcon#read 6, iclass 29, count 2 2006.239.07:36:27.09#ibcon#end of sib2, iclass 29, count 2 2006.239.07:36:27.09#ibcon#*mode == 0, iclass 29, count 2 2006.239.07:36:27.09#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.07:36:27.10#ibcon#[25=AT01-08\r\n] 2006.239.07:36:27.10#ibcon#*before write, iclass 29, count 2 2006.239.07:36:27.10#ibcon#enter sib2, iclass 29, count 2 2006.239.07:36:27.10#ibcon#flushed, iclass 29, count 2 2006.239.07:36:27.10#ibcon#about to write, iclass 29, count 2 2006.239.07:36:27.10#ibcon#wrote, iclass 29, count 2 2006.239.07:36:27.10#ibcon#about to read 3, iclass 29, count 2 2006.239.07:36:27.12#ibcon#read 3, iclass 29, count 2 2006.239.07:36:27.12#ibcon#about to read 4, iclass 29, count 2 2006.239.07:36:27.12#ibcon#read 4, iclass 29, count 2 2006.239.07:36:27.12#ibcon#about to read 5, iclass 29, count 2 2006.239.07:36:27.12#ibcon#read 5, iclass 29, count 2 2006.239.07:36:27.12#ibcon#about to read 6, iclass 29, count 2 2006.239.07:36:27.12#ibcon#read 6, iclass 29, count 2 2006.239.07:36:27.12#ibcon#end of sib2, iclass 29, count 2 2006.239.07:36:27.12#ibcon#*after write, iclass 29, count 2 2006.239.07:36:27.12#ibcon#*before return 0, iclass 29, count 2 2006.239.07:36:27.12#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:27.12#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:27.12#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.07:36:27.12#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:27.12#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:27.24#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:27.24#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:27.24#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:36:27.24#ibcon#first serial, iclass 29, count 0 2006.239.07:36:27.24#ibcon#enter sib2, iclass 29, count 0 2006.239.07:36:27.24#ibcon#flushed, iclass 29, count 0 2006.239.07:36:27.24#ibcon#about to write, iclass 29, count 0 2006.239.07:36:27.24#ibcon#wrote, iclass 29, count 0 2006.239.07:36:27.24#ibcon#about to read 3, iclass 29, count 0 2006.239.07:36:27.26#ibcon#read 3, iclass 29, count 0 2006.239.07:36:27.26#ibcon#about to read 4, iclass 29, count 0 2006.239.07:36:27.26#ibcon#read 4, iclass 29, count 0 2006.239.07:36:27.26#ibcon#about to read 5, iclass 29, count 0 2006.239.07:36:27.26#ibcon#read 5, iclass 29, count 0 2006.239.07:36:27.26#ibcon#about to read 6, iclass 29, count 0 2006.239.07:36:27.26#ibcon#read 6, iclass 29, count 0 2006.239.07:36:27.26#ibcon#end of sib2, iclass 29, count 0 2006.239.07:36:27.26#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:36:27.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:36:27.26#ibcon#[25=USB\r\n] 2006.239.07:36:27.26#ibcon#*before write, iclass 29, count 0 2006.239.07:36:27.26#ibcon#enter sib2, iclass 29, count 0 2006.239.07:36:27.26#ibcon#flushed, iclass 29, count 0 2006.239.07:36:27.26#ibcon#about to write, iclass 29, count 0 2006.239.07:36:27.26#ibcon#wrote, iclass 29, count 0 2006.239.07:36:27.26#ibcon#about to read 3, iclass 29, count 0 2006.239.07:36:27.29#ibcon#read 3, iclass 29, count 0 2006.239.07:36:27.29#ibcon#about to read 4, iclass 29, count 0 2006.239.07:36:27.29#ibcon#read 4, iclass 29, count 0 2006.239.07:36:27.29#ibcon#about to read 5, iclass 29, count 0 2006.239.07:36:27.29#ibcon#read 5, iclass 29, count 0 2006.239.07:36:27.29#ibcon#about to read 6, iclass 29, count 0 2006.239.07:36:27.29#ibcon#read 6, iclass 29, count 0 2006.239.07:36:27.29#ibcon#end of sib2, iclass 29, count 0 2006.239.07:36:27.29#ibcon#*after write, iclass 29, count 0 2006.239.07:36:27.29#ibcon#*before return 0, iclass 29, count 0 2006.239.07:36:27.29#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:27.29#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:27.29#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:36:27.29#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:36:27.29$vc4f8/valo=2,572.99 2006.239.07:36:27.29#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.07:36:27.29#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.07:36:27.29#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:27.29#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:27.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:27.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:27.29#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:36:27.29#ibcon#first serial, iclass 31, count 0 2006.239.07:36:27.29#ibcon#enter sib2, iclass 31, count 0 2006.239.07:36:27.29#ibcon#flushed, iclass 31, count 0 2006.239.07:36:27.29#ibcon#about to write, iclass 31, count 0 2006.239.07:36:27.29#ibcon#wrote, iclass 31, count 0 2006.239.07:36:27.29#ibcon#about to read 3, iclass 31, count 0 2006.239.07:36:27.31#ibcon#read 3, iclass 31, count 0 2006.239.07:36:27.31#ibcon#about to read 4, iclass 31, count 0 2006.239.07:36:27.31#ibcon#read 4, iclass 31, count 0 2006.239.07:36:27.31#ibcon#about to read 5, iclass 31, count 0 2006.239.07:36:27.31#ibcon#read 5, iclass 31, count 0 2006.239.07:36:27.31#ibcon#about to read 6, iclass 31, count 0 2006.239.07:36:27.31#ibcon#read 6, iclass 31, count 0 2006.239.07:36:27.31#ibcon#end of sib2, iclass 31, count 0 2006.239.07:36:27.31#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:36:27.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:36:27.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:36:27.31#ibcon#*before write, iclass 31, count 0 2006.239.07:36:27.31#ibcon#enter sib2, iclass 31, count 0 2006.239.07:36:27.31#ibcon#flushed, iclass 31, count 0 2006.239.07:36:27.31#ibcon#about to write, iclass 31, count 0 2006.239.07:36:27.31#ibcon#wrote, iclass 31, count 0 2006.239.07:36:27.31#ibcon#about to read 3, iclass 31, count 0 2006.239.07:36:27.35#ibcon#read 3, iclass 31, count 0 2006.239.07:36:27.35#ibcon#about to read 4, iclass 31, count 0 2006.239.07:36:27.35#ibcon#read 4, iclass 31, count 0 2006.239.07:36:27.35#ibcon#about to read 5, iclass 31, count 0 2006.239.07:36:27.35#ibcon#read 5, iclass 31, count 0 2006.239.07:36:27.35#ibcon#about to read 6, iclass 31, count 0 2006.239.07:36:27.35#ibcon#read 6, iclass 31, count 0 2006.239.07:36:27.35#ibcon#end of sib2, iclass 31, count 0 2006.239.07:36:27.35#ibcon#*after write, iclass 31, count 0 2006.239.07:36:27.35#ibcon#*before return 0, iclass 31, count 0 2006.239.07:36:27.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:27.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:27.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:36:27.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:36:27.35$vc4f8/va=2,7 2006.239.07:36:27.35#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.07:36:27.35#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.07:36:27.35#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:27.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:27.41#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:27.41#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:27.41#ibcon#enter wrdev, iclass 33, count 2 2006.239.07:36:27.41#ibcon#first serial, iclass 33, count 2 2006.239.07:36:27.41#ibcon#enter sib2, iclass 33, count 2 2006.239.07:36:27.41#ibcon#flushed, iclass 33, count 2 2006.239.07:36:27.41#ibcon#about to write, iclass 33, count 2 2006.239.07:36:27.41#ibcon#wrote, iclass 33, count 2 2006.239.07:36:27.41#ibcon#about to read 3, iclass 33, count 2 2006.239.07:36:27.43#ibcon#read 3, iclass 33, count 2 2006.239.07:36:27.43#ibcon#about to read 4, iclass 33, count 2 2006.239.07:36:27.43#ibcon#read 4, iclass 33, count 2 2006.239.07:36:27.43#ibcon#about to read 5, iclass 33, count 2 2006.239.07:36:27.43#ibcon#read 5, iclass 33, count 2 2006.239.07:36:27.43#ibcon#about to read 6, iclass 33, count 2 2006.239.07:36:27.43#ibcon#read 6, iclass 33, count 2 2006.239.07:36:27.43#ibcon#end of sib2, iclass 33, count 2 2006.239.07:36:27.43#ibcon#*mode == 0, iclass 33, count 2 2006.239.07:36:27.43#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.07:36:27.43#ibcon#[25=AT02-07\r\n] 2006.239.07:36:27.43#ibcon#*before write, iclass 33, count 2 2006.239.07:36:27.43#ibcon#enter sib2, iclass 33, count 2 2006.239.07:36:27.43#ibcon#flushed, iclass 33, count 2 2006.239.07:36:27.43#ibcon#about to write, iclass 33, count 2 2006.239.07:36:27.43#ibcon#wrote, iclass 33, count 2 2006.239.07:36:27.43#ibcon#about to read 3, iclass 33, count 2 2006.239.07:36:27.46#ibcon#read 3, iclass 33, count 2 2006.239.07:36:27.46#ibcon#about to read 4, iclass 33, count 2 2006.239.07:36:27.46#ibcon#read 4, iclass 33, count 2 2006.239.07:36:27.46#ibcon#about to read 5, iclass 33, count 2 2006.239.07:36:27.46#ibcon#read 5, iclass 33, count 2 2006.239.07:36:27.46#ibcon#about to read 6, iclass 33, count 2 2006.239.07:36:27.46#ibcon#read 6, iclass 33, count 2 2006.239.07:36:27.46#ibcon#end of sib2, iclass 33, count 2 2006.239.07:36:27.46#ibcon#*after write, iclass 33, count 2 2006.239.07:36:27.46#ibcon#*before return 0, iclass 33, count 2 2006.239.07:36:27.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:27.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:27.46#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.07:36:27.46#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:27.46#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:27.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:27.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:27.59#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:36:27.59#ibcon#first serial, iclass 33, count 0 2006.239.07:36:27.59#ibcon#enter sib2, iclass 33, count 0 2006.239.07:36:27.59#ibcon#flushed, iclass 33, count 0 2006.239.07:36:27.59#ibcon#about to write, iclass 33, count 0 2006.239.07:36:27.59#ibcon#wrote, iclass 33, count 0 2006.239.07:36:27.59#ibcon#about to read 3, iclass 33, count 0 2006.239.07:36:27.60#ibcon#read 3, iclass 33, count 0 2006.239.07:36:27.60#ibcon#about to read 4, iclass 33, count 0 2006.239.07:36:27.60#ibcon#read 4, iclass 33, count 0 2006.239.07:36:27.60#ibcon#about to read 5, iclass 33, count 0 2006.239.07:36:27.60#ibcon#read 5, iclass 33, count 0 2006.239.07:36:27.60#ibcon#about to read 6, iclass 33, count 0 2006.239.07:36:27.60#ibcon#read 6, iclass 33, count 0 2006.239.07:36:27.60#ibcon#end of sib2, iclass 33, count 0 2006.239.07:36:27.60#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:36:27.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:36:27.61#ibcon#[25=USB\r\n] 2006.239.07:36:27.61#ibcon#*before write, iclass 33, count 0 2006.239.07:36:27.61#ibcon#enter sib2, iclass 33, count 0 2006.239.07:36:27.61#ibcon#flushed, iclass 33, count 0 2006.239.07:36:27.61#ibcon#about to write, iclass 33, count 0 2006.239.07:36:27.61#ibcon#wrote, iclass 33, count 0 2006.239.07:36:27.61#ibcon#about to read 3, iclass 33, count 0 2006.239.07:36:27.63#ibcon#read 3, iclass 33, count 0 2006.239.07:36:27.63#ibcon#about to read 4, iclass 33, count 0 2006.239.07:36:27.63#ibcon#read 4, iclass 33, count 0 2006.239.07:36:27.63#ibcon#about to read 5, iclass 33, count 0 2006.239.07:36:27.63#ibcon#read 5, iclass 33, count 0 2006.239.07:36:27.63#ibcon#about to read 6, iclass 33, count 0 2006.239.07:36:27.63#ibcon#read 6, iclass 33, count 0 2006.239.07:36:27.63#ibcon#end of sib2, iclass 33, count 0 2006.239.07:36:27.63#ibcon#*after write, iclass 33, count 0 2006.239.07:36:27.63#ibcon#*before return 0, iclass 33, count 0 2006.239.07:36:27.63#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:27.63#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:27.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:36:27.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:36:27.63$vc4f8/valo=3,672.99 2006.239.07:36:27.63#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.07:36:27.63#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.07:36:27.63#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:27.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:27.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:27.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:27.63#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:36:27.63#ibcon#first serial, iclass 35, count 0 2006.239.07:36:27.63#ibcon#enter sib2, iclass 35, count 0 2006.239.07:36:27.63#ibcon#flushed, iclass 35, count 0 2006.239.07:36:27.63#ibcon#about to write, iclass 35, count 0 2006.239.07:36:27.63#ibcon#wrote, iclass 35, count 0 2006.239.07:36:27.63#ibcon#about to read 3, iclass 35, count 0 2006.239.07:36:27.65#ibcon#read 3, iclass 35, count 0 2006.239.07:36:27.65#ibcon#about to read 4, iclass 35, count 0 2006.239.07:36:27.65#ibcon#read 4, iclass 35, count 0 2006.239.07:36:27.65#ibcon#about to read 5, iclass 35, count 0 2006.239.07:36:27.65#ibcon#read 5, iclass 35, count 0 2006.239.07:36:27.65#ibcon#about to read 6, iclass 35, count 0 2006.239.07:36:27.65#ibcon#read 6, iclass 35, count 0 2006.239.07:36:27.65#ibcon#end of sib2, iclass 35, count 0 2006.239.07:36:27.65#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:36:27.65#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:36:27.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:36:27.65#ibcon#*before write, iclass 35, count 0 2006.239.07:36:27.65#ibcon#enter sib2, iclass 35, count 0 2006.239.07:36:27.65#ibcon#flushed, iclass 35, count 0 2006.239.07:36:27.65#ibcon#about to write, iclass 35, count 0 2006.239.07:36:27.65#ibcon#wrote, iclass 35, count 0 2006.239.07:36:27.65#ibcon#about to read 3, iclass 35, count 0 2006.239.07:36:27.69#ibcon#read 3, iclass 35, count 0 2006.239.07:36:27.69#ibcon#about to read 4, iclass 35, count 0 2006.239.07:36:27.69#ibcon#read 4, iclass 35, count 0 2006.239.07:36:27.69#ibcon#about to read 5, iclass 35, count 0 2006.239.07:36:27.69#ibcon#read 5, iclass 35, count 0 2006.239.07:36:27.69#ibcon#about to read 6, iclass 35, count 0 2006.239.07:36:27.69#ibcon#read 6, iclass 35, count 0 2006.239.07:36:27.69#ibcon#end of sib2, iclass 35, count 0 2006.239.07:36:27.69#ibcon#*after write, iclass 35, count 0 2006.239.07:36:27.69#ibcon#*before return 0, iclass 35, count 0 2006.239.07:36:27.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:27.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:27.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:36:27.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:36:27.69$vc4f8/va=3,7 2006.239.07:36:27.69#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.07:36:27.69#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.07:36:27.69#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:27.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:27.75#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:27.75#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:27.75#ibcon#enter wrdev, iclass 37, count 2 2006.239.07:36:27.75#ibcon#first serial, iclass 37, count 2 2006.239.07:36:27.75#ibcon#enter sib2, iclass 37, count 2 2006.239.07:36:27.75#ibcon#flushed, iclass 37, count 2 2006.239.07:36:27.75#ibcon#about to write, iclass 37, count 2 2006.239.07:36:27.75#ibcon#wrote, iclass 37, count 2 2006.239.07:36:27.75#ibcon#about to read 3, iclass 37, count 2 2006.239.07:36:27.77#ibcon#read 3, iclass 37, count 2 2006.239.07:36:27.77#ibcon#about to read 4, iclass 37, count 2 2006.239.07:36:27.77#ibcon#read 4, iclass 37, count 2 2006.239.07:36:27.77#ibcon#about to read 5, iclass 37, count 2 2006.239.07:36:27.77#ibcon#read 5, iclass 37, count 2 2006.239.07:36:27.77#ibcon#about to read 6, iclass 37, count 2 2006.239.07:36:27.77#ibcon#read 6, iclass 37, count 2 2006.239.07:36:27.77#ibcon#end of sib2, iclass 37, count 2 2006.239.07:36:27.77#ibcon#*mode == 0, iclass 37, count 2 2006.239.07:36:27.77#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.07:36:27.77#ibcon#[25=AT03-07\r\n] 2006.239.07:36:27.77#ibcon#*before write, iclass 37, count 2 2006.239.07:36:27.77#ibcon#enter sib2, iclass 37, count 2 2006.239.07:36:27.77#ibcon#flushed, iclass 37, count 2 2006.239.07:36:27.77#ibcon#about to write, iclass 37, count 2 2006.239.07:36:27.77#ibcon#wrote, iclass 37, count 2 2006.239.07:36:27.77#ibcon#about to read 3, iclass 37, count 2 2006.239.07:36:27.80#ibcon#read 3, iclass 37, count 2 2006.239.07:36:27.80#ibcon#about to read 4, iclass 37, count 2 2006.239.07:36:27.80#ibcon#read 4, iclass 37, count 2 2006.239.07:36:27.80#ibcon#about to read 5, iclass 37, count 2 2006.239.07:36:27.80#ibcon#read 5, iclass 37, count 2 2006.239.07:36:27.80#ibcon#about to read 6, iclass 37, count 2 2006.239.07:36:27.80#ibcon#read 6, iclass 37, count 2 2006.239.07:36:27.80#ibcon#end of sib2, iclass 37, count 2 2006.239.07:36:27.80#ibcon#*after write, iclass 37, count 2 2006.239.07:36:27.80#ibcon#*before return 0, iclass 37, count 2 2006.239.07:36:27.80#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:27.80#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:27.80#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.07:36:27.80#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:27.80#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:27.92#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:27.92#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:27.92#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:36:27.92#ibcon#first serial, iclass 37, count 0 2006.239.07:36:27.92#ibcon#enter sib2, iclass 37, count 0 2006.239.07:36:27.92#ibcon#flushed, iclass 37, count 0 2006.239.07:36:27.92#ibcon#about to write, iclass 37, count 0 2006.239.07:36:27.92#ibcon#wrote, iclass 37, count 0 2006.239.07:36:27.92#ibcon#about to read 3, iclass 37, count 0 2006.239.07:36:27.94#ibcon#read 3, iclass 37, count 0 2006.239.07:36:27.94#ibcon#about to read 4, iclass 37, count 0 2006.239.07:36:27.94#ibcon#read 4, iclass 37, count 0 2006.239.07:36:27.94#ibcon#about to read 5, iclass 37, count 0 2006.239.07:36:27.94#ibcon#read 5, iclass 37, count 0 2006.239.07:36:27.94#ibcon#about to read 6, iclass 37, count 0 2006.239.07:36:27.94#ibcon#read 6, iclass 37, count 0 2006.239.07:36:27.94#ibcon#end of sib2, iclass 37, count 0 2006.239.07:36:27.94#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:36:27.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:36:27.94#ibcon#[25=USB\r\n] 2006.239.07:36:27.94#ibcon#*before write, iclass 37, count 0 2006.239.07:36:27.94#ibcon#enter sib2, iclass 37, count 0 2006.239.07:36:27.94#ibcon#flushed, iclass 37, count 0 2006.239.07:36:27.94#ibcon#about to write, iclass 37, count 0 2006.239.07:36:27.94#ibcon#wrote, iclass 37, count 0 2006.239.07:36:27.94#ibcon#about to read 3, iclass 37, count 0 2006.239.07:36:27.97#ibcon#read 3, iclass 37, count 0 2006.239.07:36:27.97#ibcon#about to read 4, iclass 37, count 0 2006.239.07:36:27.97#ibcon#read 4, iclass 37, count 0 2006.239.07:36:27.97#ibcon#about to read 5, iclass 37, count 0 2006.239.07:36:27.97#ibcon#read 5, iclass 37, count 0 2006.239.07:36:27.97#ibcon#about to read 6, iclass 37, count 0 2006.239.07:36:27.97#ibcon#read 6, iclass 37, count 0 2006.239.07:36:27.97#ibcon#end of sib2, iclass 37, count 0 2006.239.07:36:27.97#ibcon#*after write, iclass 37, count 0 2006.239.07:36:27.97#ibcon#*before return 0, iclass 37, count 0 2006.239.07:36:27.97#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:27.97#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:27.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:36:27.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:36:27.97$vc4f8/valo=4,832.99 2006.239.07:36:27.97#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.07:36:27.97#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.07:36:27.97#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:27.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:27.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:27.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:27.97#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:36:27.97#ibcon#first serial, iclass 39, count 0 2006.239.07:36:27.97#ibcon#enter sib2, iclass 39, count 0 2006.239.07:36:27.97#ibcon#flushed, iclass 39, count 0 2006.239.07:36:27.97#ibcon#about to write, iclass 39, count 0 2006.239.07:36:27.97#ibcon#wrote, iclass 39, count 0 2006.239.07:36:27.97#ibcon#about to read 3, iclass 39, count 0 2006.239.07:36:27.99#ibcon#read 3, iclass 39, count 0 2006.239.07:36:27.99#ibcon#about to read 4, iclass 39, count 0 2006.239.07:36:27.99#ibcon#read 4, iclass 39, count 0 2006.239.07:36:27.99#ibcon#about to read 5, iclass 39, count 0 2006.239.07:36:27.99#ibcon#read 5, iclass 39, count 0 2006.239.07:36:27.99#ibcon#about to read 6, iclass 39, count 0 2006.239.07:36:27.99#ibcon#read 6, iclass 39, count 0 2006.239.07:36:27.99#ibcon#end of sib2, iclass 39, count 0 2006.239.07:36:27.99#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:36:27.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:36:27.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:36:27.99#ibcon#*before write, iclass 39, count 0 2006.239.07:36:27.99#ibcon#enter sib2, iclass 39, count 0 2006.239.07:36:27.99#ibcon#flushed, iclass 39, count 0 2006.239.07:36:27.99#ibcon#about to write, iclass 39, count 0 2006.239.07:36:27.99#ibcon#wrote, iclass 39, count 0 2006.239.07:36:27.99#ibcon#about to read 3, iclass 39, count 0 2006.239.07:36:28.03#ibcon#read 3, iclass 39, count 0 2006.239.07:36:28.03#ibcon#about to read 4, iclass 39, count 0 2006.239.07:36:28.03#ibcon#read 4, iclass 39, count 0 2006.239.07:36:28.03#ibcon#about to read 5, iclass 39, count 0 2006.239.07:36:28.03#ibcon#read 5, iclass 39, count 0 2006.239.07:36:28.03#ibcon#about to read 6, iclass 39, count 0 2006.239.07:36:28.03#ibcon#read 6, iclass 39, count 0 2006.239.07:36:28.03#ibcon#end of sib2, iclass 39, count 0 2006.239.07:36:28.03#ibcon#*after write, iclass 39, count 0 2006.239.07:36:28.03#ibcon#*before return 0, iclass 39, count 0 2006.239.07:36:28.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:28.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:28.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:36:28.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:36:28.03$vc4f8/va=4,7 2006.239.07:36:28.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.07:36:28.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.07:36:28.03#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:28.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:28.09#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:28.09#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:28.09#ibcon#enter wrdev, iclass 3, count 2 2006.239.07:36:28.09#ibcon#first serial, iclass 3, count 2 2006.239.07:36:28.09#ibcon#enter sib2, iclass 3, count 2 2006.239.07:36:28.09#ibcon#flushed, iclass 3, count 2 2006.239.07:36:28.09#ibcon#about to write, iclass 3, count 2 2006.239.07:36:28.09#ibcon#wrote, iclass 3, count 2 2006.239.07:36:28.09#ibcon#about to read 3, iclass 3, count 2 2006.239.07:36:28.11#ibcon#read 3, iclass 3, count 2 2006.239.07:36:28.11#ibcon#about to read 4, iclass 3, count 2 2006.239.07:36:28.11#ibcon#read 4, iclass 3, count 2 2006.239.07:36:28.11#ibcon#about to read 5, iclass 3, count 2 2006.239.07:36:28.11#ibcon#read 5, iclass 3, count 2 2006.239.07:36:28.11#ibcon#about to read 6, iclass 3, count 2 2006.239.07:36:28.11#ibcon#read 6, iclass 3, count 2 2006.239.07:36:28.11#ibcon#end of sib2, iclass 3, count 2 2006.239.07:36:28.11#ibcon#*mode == 0, iclass 3, count 2 2006.239.07:36:28.11#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.07:36:28.11#ibcon#[25=AT04-07\r\n] 2006.239.07:36:28.11#ibcon#*before write, iclass 3, count 2 2006.239.07:36:28.11#ibcon#enter sib2, iclass 3, count 2 2006.239.07:36:28.11#ibcon#flushed, iclass 3, count 2 2006.239.07:36:28.11#ibcon#about to write, iclass 3, count 2 2006.239.07:36:28.11#ibcon#wrote, iclass 3, count 2 2006.239.07:36:28.11#ibcon#about to read 3, iclass 3, count 2 2006.239.07:36:28.14#ibcon#read 3, iclass 3, count 2 2006.239.07:36:28.14#ibcon#about to read 4, iclass 3, count 2 2006.239.07:36:28.14#ibcon#read 4, iclass 3, count 2 2006.239.07:36:28.14#ibcon#about to read 5, iclass 3, count 2 2006.239.07:36:28.14#ibcon#read 5, iclass 3, count 2 2006.239.07:36:28.14#ibcon#about to read 6, iclass 3, count 2 2006.239.07:36:28.14#ibcon#read 6, iclass 3, count 2 2006.239.07:36:28.14#ibcon#end of sib2, iclass 3, count 2 2006.239.07:36:28.14#ibcon#*after write, iclass 3, count 2 2006.239.07:36:28.14#ibcon#*before return 0, iclass 3, count 2 2006.239.07:36:28.14#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:28.14#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:28.14#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.07:36:28.14#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:28.14#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:28.26#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:28.26#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:28.26#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:36:28.26#ibcon#first serial, iclass 3, count 0 2006.239.07:36:28.26#ibcon#enter sib2, iclass 3, count 0 2006.239.07:36:28.26#ibcon#flushed, iclass 3, count 0 2006.239.07:36:28.26#ibcon#about to write, iclass 3, count 0 2006.239.07:36:28.26#ibcon#wrote, iclass 3, count 0 2006.239.07:36:28.26#ibcon#about to read 3, iclass 3, count 0 2006.239.07:36:28.28#ibcon#read 3, iclass 3, count 0 2006.239.07:36:28.28#ibcon#about to read 4, iclass 3, count 0 2006.239.07:36:28.28#ibcon#read 4, iclass 3, count 0 2006.239.07:36:28.28#ibcon#about to read 5, iclass 3, count 0 2006.239.07:36:28.28#ibcon#read 5, iclass 3, count 0 2006.239.07:36:28.28#ibcon#about to read 6, iclass 3, count 0 2006.239.07:36:28.28#ibcon#read 6, iclass 3, count 0 2006.239.07:36:28.28#ibcon#end of sib2, iclass 3, count 0 2006.239.07:36:28.28#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:36:28.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:36:28.28#ibcon#[25=USB\r\n] 2006.239.07:36:28.28#ibcon#*before write, iclass 3, count 0 2006.239.07:36:28.28#ibcon#enter sib2, iclass 3, count 0 2006.239.07:36:28.28#ibcon#flushed, iclass 3, count 0 2006.239.07:36:28.28#ibcon#about to write, iclass 3, count 0 2006.239.07:36:28.28#ibcon#wrote, iclass 3, count 0 2006.239.07:36:28.28#ibcon#about to read 3, iclass 3, count 0 2006.239.07:36:28.31#ibcon#read 3, iclass 3, count 0 2006.239.07:36:28.31#ibcon#about to read 4, iclass 3, count 0 2006.239.07:36:28.31#ibcon#read 4, iclass 3, count 0 2006.239.07:36:28.31#ibcon#about to read 5, iclass 3, count 0 2006.239.07:36:28.31#ibcon#read 5, iclass 3, count 0 2006.239.07:36:28.31#ibcon#about to read 6, iclass 3, count 0 2006.239.07:36:28.31#ibcon#read 6, iclass 3, count 0 2006.239.07:36:28.31#ibcon#end of sib2, iclass 3, count 0 2006.239.07:36:28.31#ibcon#*after write, iclass 3, count 0 2006.239.07:36:28.31#ibcon#*before return 0, iclass 3, count 0 2006.239.07:36:28.31#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:28.31#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:28.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:36:28.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:36:28.31$vc4f8/valo=5,652.99 2006.239.07:36:28.31#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:36:28.31#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:36:28.31#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:28.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:28.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:28.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:28.31#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:36:28.31#ibcon#first serial, iclass 5, count 0 2006.239.07:36:28.31#ibcon#enter sib2, iclass 5, count 0 2006.239.07:36:28.31#ibcon#flushed, iclass 5, count 0 2006.239.07:36:28.31#ibcon#about to write, iclass 5, count 0 2006.239.07:36:28.31#ibcon#wrote, iclass 5, count 0 2006.239.07:36:28.31#ibcon#about to read 3, iclass 5, count 0 2006.239.07:36:28.33#ibcon#read 3, iclass 5, count 0 2006.239.07:36:28.33#ibcon#about to read 4, iclass 5, count 0 2006.239.07:36:28.33#ibcon#read 4, iclass 5, count 0 2006.239.07:36:28.33#ibcon#about to read 5, iclass 5, count 0 2006.239.07:36:28.33#ibcon#read 5, iclass 5, count 0 2006.239.07:36:28.33#ibcon#about to read 6, iclass 5, count 0 2006.239.07:36:28.33#ibcon#read 6, iclass 5, count 0 2006.239.07:36:28.33#ibcon#end of sib2, iclass 5, count 0 2006.239.07:36:28.33#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:36:28.33#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:36:28.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:36:28.33#ibcon#*before write, iclass 5, count 0 2006.239.07:36:28.33#ibcon#enter sib2, iclass 5, count 0 2006.239.07:36:28.33#ibcon#flushed, iclass 5, count 0 2006.239.07:36:28.33#ibcon#about to write, iclass 5, count 0 2006.239.07:36:28.33#ibcon#wrote, iclass 5, count 0 2006.239.07:36:28.33#ibcon#about to read 3, iclass 5, count 0 2006.239.07:36:28.37#ibcon#read 3, iclass 5, count 0 2006.239.07:36:28.37#ibcon#about to read 4, iclass 5, count 0 2006.239.07:36:28.37#ibcon#read 4, iclass 5, count 0 2006.239.07:36:28.37#ibcon#about to read 5, iclass 5, count 0 2006.239.07:36:28.37#ibcon#read 5, iclass 5, count 0 2006.239.07:36:28.37#ibcon#about to read 6, iclass 5, count 0 2006.239.07:36:28.37#ibcon#read 6, iclass 5, count 0 2006.239.07:36:28.37#ibcon#end of sib2, iclass 5, count 0 2006.239.07:36:28.37#ibcon#*after write, iclass 5, count 0 2006.239.07:36:28.37#ibcon#*before return 0, iclass 5, count 0 2006.239.07:36:28.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:28.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:28.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:36:28.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:36:28.37$vc4f8/va=5,8 2006.239.07:36:28.37#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.07:36:28.37#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.07:36:28.37#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:28.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:28.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:28.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:28.44#ibcon#enter wrdev, iclass 7, count 2 2006.239.07:36:28.44#ibcon#first serial, iclass 7, count 2 2006.239.07:36:28.44#ibcon#enter sib2, iclass 7, count 2 2006.239.07:36:28.44#ibcon#flushed, iclass 7, count 2 2006.239.07:36:28.44#ibcon#about to write, iclass 7, count 2 2006.239.07:36:28.44#ibcon#wrote, iclass 7, count 2 2006.239.07:36:28.44#ibcon#about to read 3, iclass 7, count 2 2006.239.07:36:28.46#ibcon#read 3, iclass 7, count 2 2006.239.07:36:28.46#ibcon#about to read 4, iclass 7, count 2 2006.239.07:36:28.46#ibcon#read 4, iclass 7, count 2 2006.239.07:36:28.46#ibcon#about to read 5, iclass 7, count 2 2006.239.07:36:28.46#ibcon#read 5, iclass 7, count 2 2006.239.07:36:28.46#ibcon#about to read 6, iclass 7, count 2 2006.239.07:36:28.46#ibcon#read 6, iclass 7, count 2 2006.239.07:36:28.46#ibcon#end of sib2, iclass 7, count 2 2006.239.07:36:28.46#ibcon#*mode == 0, iclass 7, count 2 2006.239.07:36:28.46#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.07:36:28.46#ibcon#[25=AT05-08\r\n] 2006.239.07:36:28.46#ibcon#*before write, iclass 7, count 2 2006.239.07:36:28.46#ibcon#enter sib2, iclass 7, count 2 2006.239.07:36:28.46#ibcon#flushed, iclass 7, count 2 2006.239.07:36:28.46#ibcon#about to write, iclass 7, count 2 2006.239.07:36:28.46#ibcon#wrote, iclass 7, count 2 2006.239.07:36:28.46#ibcon#about to read 3, iclass 7, count 2 2006.239.07:36:28.48#ibcon#read 3, iclass 7, count 2 2006.239.07:36:28.48#ibcon#about to read 4, iclass 7, count 2 2006.239.07:36:28.48#ibcon#read 4, iclass 7, count 2 2006.239.07:36:28.48#ibcon#about to read 5, iclass 7, count 2 2006.239.07:36:28.48#ibcon#read 5, iclass 7, count 2 2006.239.07:36:28.48#ibcon#about to read 6, iclass 7, count 2 2006.239.07:36:28.48#ibcon#read 6, iclass 7, count 2 2006.239.07:36:28.48#ibcon#end of sib2, iclass 7, count 2 2006.239.07:36:28.48#ibcon#*after write, iclass 7, count 2 2006.239.07:36:28.48#ibcon#*before return 0, iclass 7, count 2 2006.239.07:36:28.48#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:28.48#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:28.48#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.07:36:28.48#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:28.48#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:28.60#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:28.60#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:28.60#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:36:28.60#ibcon#first serial, iclass 7, count 0 2006.239.07:36:28.60#ibcon#enter sib2, iclass 7, count 0 2006.239.07:36:28.60#ibcon#flushed, iclass 7, count 0 2006.239.07:36:28.60#ibcon#about to write, iclass 7, count 0 2006.239.07:36:28.60#ibcon#wrote, iclass 7, count 0 2006.239.07:36:28.60#ibcon#about to read 3, iclass 7, count 0 2006.239.07:36:28.62#ibcon#read 3, iclass 7, count 0 2006.239.07:36:28.62#ibcon#about to read 4, iclass 7, count 0 2006.239.07:36:28.62#ibcon#read 4, iclass 7, count 0 2006.239.07:36:28.62#ibcon#about to read 5, iclass 7, count 0 2006.239.07:36:28.62#ibcon#read 5, iclass 7, count 0 2006.239.07:36:28.62#ibcon#about to read 6, iclass 7, count 0 2006.239.07:36:28.62#ibcon#read 6, iclass 7, count 0 2006.239.07:36:28.62#ibcon#end of sib2, iclass 7, count 0 2006.239.07:36:28.62#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:36:28.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:36:28.62#ibcon#[25=USB\r\n] 2006.239.07:36:28.62#ibcon#*before write, iclass 7, count 0 2006.239.07:36:28.62#ibcon#enter sib2, iclass 7, count 0 2006.239.07:36:28.62#ibcon#flushed, iclass 7, count 0 2006.239.07:36:28.62#ibcon#about to write, iclass 7, count 0 2006.239.07:36:28.62#ibcon#wrote, iclass 7, count 0 2006.239.07:36:28.62#ibcon#about to read 3, iclass 7, count 0 2006.239.07:36:28.65#ibcon#read 3, iclass 7, count 0 2006.239.07:36:28.65#ibcon#about to read 4, iclass 7, count 0 2006.239.07:36:28.65#ibcon#read 4, iclass 7, count 0 2006.239.07:36:28.65#ibcon#about to read 5, iclass 7, count 0 2006.239.07:36:28.65#ibcon#read 5, iclass 7, count 0 2006.239.07:36:28.65#ibcon#about to read 6, iclass 7, count 0 2006.239.07:36:28.65#ibcon#read 6, iclass 7, count 0 2006.239.07:36:28.65#ibcon#end of sib2, iclass 7, count 0 2006.239.07:36:28.65#ibcon#*after write, iclass 7, count 0 2006.239.07:36:28.65#ibcon#*before return 0, iclass 7, count 0 2006.239.07:36:28.65#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:28.65#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:28.65#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:36:28.65#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:36:28.65$vc4f8/valo=6,772.99 2006.239.07:36:28.65#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.07:36:28.65#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.07:36:28.65#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:28.65#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:28.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:28.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:28.65#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:36:28.65#ibcon#first serial, iclass 11, count 0 2006.239.07:36:28.65#ibcon#enter sib2, iclass 11, count 0 2006.239.07:36:28.65#ibcon#flushed, iclass 11, count 0 2006.239.07:36:28.65#ibcon#about to write, iclass 11, count 0 2006.239.07:36:28.65#ibcon#wrote, iclass 11, count 0 2006.239.07:36:28.65#ibcon#about to read 3, iclass 11, count 0 2006.239.07:36:28.67#ibcon#read 3, iclass 11, count 0 2006.239.07:36:28.67#ibcon#about to read 4, iclass 11, count 0 2006.239.07:36:28.67#ibcon#read 4, iclass 11, count 0 2006.239.07:36:28.67#ibcon#about to read 5, iclass 11, count 0 2006.239.07:36:28.67#ibcon#read 5, iclass 11, count 0 2006.239.07:36:28.67#ibcon#about to read 6, iclass 11, count 0 2006.239.07:36:28.67#ibcon#read 6, iclass 11, count 0 2006.239.07:36:28.67#ibcon#end of sib2, iclass 11, count 0 2006.239.07:36:28.67#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:36:28.67#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:36:28.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:36:28.67#ibcon#*before write, iclass 11, count 0 2006.239.07:36:28.67#ibcon#enter sib2, iclass 11, count 0 2006.239.07:36:28.67#ibcon#flushed, iclass 11, count 0 2006.239.07:36:28.67#ibcon#about to write, iclass 11, count 0 2006.239.07:36:28.67#ibcon#wrote, iclass 11, count 0 2006.239.07:36:28.67#ibcon#about to read 3, iclass 11, count 0 2006.239.07:36:28.71#ibcon#read 3, iclass 11, count 0 2006.239.07:36:28.71#ibcon#about to read 4, iclass 11, count 0 2006.239.07:36:28.71#ibcon#read 4, iclass 11, count 0 2006.239.07:36:28.71#ibcon#about to read 5, iclass 11, count 0 2006.239.07:36:28.71#ibcon#read 5, iclass 11, count 0 2006.239.07:36:28.71#ibcon#about to read 6, iclass 11, count 0 2006.239.07:36:28.71#ibcon#read 6, iclass 11, count 0 2006.239.07:36:28.71#ibcon#end of sib2, iclass 11, count 0 2006.239.07:36:28.71#ibcon#*after write, iclass 11, count 0 2006.239.07:36:28.71#ibcon#*before return 0, iclass 11, count 0 2006.239.07:36:28.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:28.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:28.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:36:28.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:36:28.71$vc4f8/va=6,7 2006.239.07:36:28.71#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.07:36:28.71#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.07:36:28.71#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:28.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:28.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:28.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:28.77#ibcon#enter wrdev, iclass 13, count 2 2006.239.07:36:28.77#ibcon#first serial, iclass 13, count 2 2006.239.07:36:28.77#ibcon#enter sib2, iclass 13, count 2 2006.239.07:36:28.77#ibcon#flushed, iclass 13, count 2 2006.239.07:36:28.77#ibcon#about to write, iclass 13, count 2 2006.239.07:36:28.77#ibcon#wrote, iclass 13, count 2 2006.239.07:36:28.77#ibcon#about to read 3, iclass 13, count 2 2006.239.07:36:28.79#ibcon#read 3, iclass 13, count 2 2006.239.07:36:28.79#ibcon#about to read 4, iclass 13, count 2 2006.239.07:36:28.79#ibcon#read 4, iclass 13, count 2 2006.239.07:36:28.79#ibcon#about to read 5, iclass 13, count 2 2006.239.07:36:28.79#ibcon#read 5, iclass 13, count 2 2006.239.07:36:28.79#ibcon#about to read 6, iclass 13, count 2 2006.239.07:36:28.79#ibcon#read 6, iclass 13, count 2 2006.239.07:36:28.79#ibcon#end of sib2, iclass 13, count 2 2006.239.07:36:28.79#ibcon#*mode == 0, iclass 13, count 2 2006.239.07:36:28.79#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.07:36:28.79#ibcon#[25=AT06-07\r\n] 2006.239.07:36:28.79#ibcon#*before write, iclass 13, count 2 2006.239.07:36:28.79#ibcon#enter sib2, iclass 13, count 2 2006.239.07:36:28.79#ibcon#flushed, iclass 13, count 2 2006.239.07:36:28.79#ibcon#about to write, iclass 13, count 2 2006.239.07:36:28.79#ibcon#wrote, iclass 13, count 2 2006.239.07:36:28.79#ibcon#about to read 3, iclass 13, count 2 2006.239.07:36:28.82#ibcon#read 3, iclass 13, count 2 2006.239.07:36:28.82#ibcon#about to read 4, iclass 13, count 2 2006.239.07:36:28.82#ibcon#read 4, iclass 13, count 2 2006.239.07:36:28.82#ibcon#about to read 5, iclass 13, count 2 2006.239.07:36:28.82#ibcon#read 5, iclass 13, count 2 2006.239.07:36:28.82#ibcon#about to read 6, iclass 13, count 2 2006.239.07:36:28.82#ibcon#read 6, iclass 13, count 2 2006.239.07:36:28.82#ibcon#end of sib2, iclass 13, count 2 2006.239.07:36:28.82#ibcon#*after write, iclass 13, count 2 2006.239.07:36:28.82#ibcon#*before return 0, iclass 13, count 2 2006.239.07:36:28.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:28.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:28.82#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.07:36:28.82#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:28.82#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:28.94#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:28.94#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:28.94#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:36:28.94#ibcon#first serial, iclass 13, count 0 2006.239.07:36:28.94#ibcon#enter sib2, iclass 13, count 0 2006.239.07:36:28.94#ibcon#flushed, iclass 13, count 0 2006.239.07:36:28.94#ibcon#about to write, iclass 13, count 0 2006.239.07:36:28.94#ibcon#wrote, iclass 13, count 0 2006.239.07:36:28.94#ibcon#about to read 3, iclass 13, count 0 2006.239.07:36:28.96#ibcon#read 3, iclass 13, count 0 2006.239.07:36:28.96#ibcon#about to read 4, iclass 13, count 0 2006.239.07:36:28.96#ibcon#read 4, iclass 13, count 0 2006.239.07:36:28.96#ibcon#about to read 5, iclass 13, count 0 2006.239.07:36:28.96#ibcon#read 5, iclass 13, count 0 2006.239.07:36:28.96#ibcon#about to read 6, iclass 13, count 0 2006.239.07:36:28.96#ibcon#read 6, iclass 13, count 0 2006.239.07:36:28.96#ibcon#end of sib2, iclass 13, count 0 2006.239.07:36:28.96#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:36:28.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:36:28.96#ibcon#[25=USB\r\n] 2006.239.07:36:28.96#ibcon#*before write, iclass 13, count 0 2006.239.07:36:28.96#ibcon#enter sib2, iclass 13, count 0 2006.239.07:36:28.96#ibcon#flushed, iclass 13, count 0 2006.239.07:36:28.96#ibcon#about to write, iclass 13, count 0 2006.239.07:36:28.96#ibcon#wrote, iclass 13, count 0 2006.239.07:36:28.96#ibcon#about to read 3, iclass 13, count 0 2006.239.07:36:28.99#ibcon#read 3, iclass 13, count 0 2006.239.07:36:28.99#ibcon#about to read 4, iclass 13, count 0 2006.239.07:36:28.99#ibcon#read 4, iclass 13, count 0 2006.239.07:36:28.99#ibcon#about to read 5, iclass 13, count 0 2006.239.07:36:28.99#ibcon#read 5, iclass 13, count 0 2006.239.07:36:28.99#ibcon#about to read 6, iclass 13, count 0 2006.239.07:36:28.99#ibcon#read 6, iclass 13, count 0 2006.239.07:36:28.99#ibcon#end of sib2, iclass 13, count 0 2006.239.07:36:28.99#ibcon#*after write, iclass 13, count 0 2006.239.07:36:28.99#ibcon#*before return 0, iclass 13, count 0 2006.239.07:36:28.99#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:28.99#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:28.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:36:28.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:36:28.99$vc4f8/valo=7,832.99 2006.239.07:36:28.99#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.07:36:28.99#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.07:36:28.99#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:28.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:28.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:28.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:28.99#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:36:28.99#ibcon#first serial, iclass 15, count 0 2006.239.07:36:28.99#ibcon#enter sib2, iclass 15, count 0 2006.239.07:36:28.99#ibcon#flushed, iclass 15, count 0 2006.239.07:36:28.99#ibcon#about to write, iclass 15, count 0 2006.239.07:36:28.99#ibcon#wrote, iclass 15, count 0 2006.239.07:36:28.99#ibcon#about to read 3, iclass 15, count 0 2006.239.07:36:29.01#ibcon#read 3, iclass 15, count 0 2006.239.07:36:29.01#ibcon#about to read 4, iclass 15, count 0 2006.239.07:36:29.01#ibcon#read 4, iclass 15, count 0 2006.239.07:36:29.01#ibcon#about to read 5, iclass 15, count 0 2006.239.07:36:29.01#ibcon#read 5, iclass 15, count 0 2006.239.07:36:29.01#ibcon#about to read 6, iclass 15, count 0 2006.239.07:36:29.01#ibcon#read 6, iclass 15, count 0 2006.239.07:36:29.01#ibcon#end of sib2, iclass 15, count 0 2006.239.07:36:29.01#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:36:29.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:36:29.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:36:29.01#ibcon#*before write, iclass 15, count 0 2006.239.07:36:29.01#ibcon#enter sib2, iclass 15, count 0 2006.239.07:36:29.01#ibcon#flushed, iclass 15, count 0 2006.239.07:36:29.01#ibcon#about to write, iclass 15, count 0 2006.239.07:36:29.01#ibcon#wrote, iclass 15, count 0 2006.239.07:36:29.01#ibcon#about to read 3, iclass 15, count 0 2006.239.07:36:29.05#ibcon#read 3, iclass 15, count 0 2006.239.07:36:29.05#ibcon#about to read 4, iclass 15, count 0 2006.239.07:36:29.05#ibcon#read 4, iclass 15, count 0 2006.239.07:36:29.05#ibcon#about to read 5, iclass 15, count 0 2006.239.07:36:29.05#ibcon#read 5, iclass 15, count 0 2006.239.07:36:29.05#ibcon#about to read 6, iclass 15, count 0 2006.239.07:36:29.05#ibcon#read 6, iclass 15, count 0 2006.239.07:36:29.05#ibcon#end of sib2, iclass 15, count 0 2006.239.07:36:29.05#ibcon#*after write, iclass 15, count 0 2006.239.07:36:29.05#ibcon#*before return 0, iclass 15, count 0 2006.239.07:36:29.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:29.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:29.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:36:29.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:36:29.05$vc4f8/va=7,7 2006.239.07:36:29.05#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.07:36:29.05#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.07:36:29.05#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:29.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:36:29.11#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:36:29.11#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:36:29.11#ibcon#enter wrdev, iclass 17, count 2 2006.239.07:36:29.11#ibcon#first serial, iclass 17, count 2 2006.239.07:36:29.11#ibcon#enter sib2, iclass 17, count 2 2006.239.07:36:29.11#ibcon#flushed, iclass 17, count 2 2006.239.07:36:29.11#ibcon#about to write, iclass 17, count 2 2006.239.07:36:29.11#ibcon#wrote, iclass 17, count 2 2006.239.07:36:29.11#ibcon#about to read 3, iclass 17, count 2 2006.239.07:36:29.13#ibcon#read 3, iclass 17, count 2 2006.239.07:36:29.13#ibcon#about to read 4, iclass 17, count 2 2006.239.07:36:29.13#ibcon#read 4, iclass 17, count 2 2006.239.07:36:29.13#ibcon#about to read 5, iclass 17, count 2 2006.239.07:36:29.13#ibcon#read 5, iclass 17, count 2 2006.239.07:36:29.13#ibcon#about to read 6, iclass 17, count 2 2006.239.07:36:29.13#ibcon#read 6, iclass 17, count 2 2006.239.07:36:29.13#ibcon#end of sib2, iclass 17, count 2 2006.239.07:36:29.13#ibcon#*mode == 0, iclass 17, count 2 2006.239.07:36:29.13#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.07:36:29.13#ibcon#[25=AT07-07\r\n] 2006.239.07:36:29.13#ibcon#*before write, iclass 17, count 2 2006.239.07:36:29.13#ibcon#enter sib2, iclass 17, count 2 2006.239.07:36:29.13#ibcon#flushed, iclass 17, count 2 2006.239.07:36:29.13#ibcon#about to write, iclass 17, count 2 2006.239.07:36:29.13#ibcon#wrote, iclass 17, count 2 2006.239.07:36:29.13#ibcon#about to read 3, iclass 17, count 2 2006.239.07:36:29.16#ibcon#read 3, iclass 17, count 2 2006.239.07:36:29.16#ibcon#about to read 4, iclass 17, count 2 2006.239.07:36:29.16#ibcon#read 4, iclass 17, count 2 2006.239.07:36:29.16#ibcon#about to read 5, iclass 17, count 2 2006.239.07:36:29.16#ibcon#read 5, iclass 17, count 2 2006.239.07:36:29.16#ibcon#about to read 6, iclass 17, count 2 2006.239.07:36:29.16#ibcon#read 6, iclass 17, count 2 2006.239.07:36:29.16#ibcon#end of sib2, iclass 17, count 2 2006.239.07:36:29.16#ibcon#*after write, iclass 17, count 2 2006.239.07:36:29.16#ibcon#*before return 0, iclass 17, count 2 2006.239.07:36:29.16#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:36:29.16#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:36:29.16#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.07:36:29.16#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:29.16#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:36:29.29#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:36:29.29#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:36:29.29#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:36:29.29#ibcon#first serial, iclass 17, count 0 2006.239.07:36:29.29#ibcon#enter sib2, iclass 17, count 0 2006.239.07:36:29.29#ibcon#flushed, iclass 17, count 0 2006.239.07:36:29.29#ibcon#about to write, iclass 17, count 0 2006.239.07:36:29.29#ibcon#wrote, iclass 17, count 0 2006.239.07:36:29.29#ibcon#about to read 3, iclass 17, count 0 2006.239.07:36:29.30#ibcon#read 3, iclass 17, count 0 2006.239.07:36:29.30#ibcon#about to read 4, iclass 17, count 0 2006.239.07:36:29.30#ibcon#read 4, iclass 17, count 0 2006.239.07:36:29.30#ibcon#about to read 5, iclass 17, count 0 2006.239.07:36:29.30#ibcon#read 5, iclass 17, count 0 2006.239.07:36:29.30#ibcon#about to read 6, iclass 17, count 0 2006.239.07:36:29.30#ibcon#read 6, iclass 17, count 0 2006.239.07:36:29.30#ibcon#end of sib2, iclass 17, count 0 2006.239.07:36:29.30#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:36:29.30#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:36:29.30#ibcon#[25=USB\r\n] 2006.239.07:36:29.30#ibcon#*before write, iclass 17, count 0 2006.239.07:36:29.30#ibcon#enter sib2, iclass 17, count 0 2006.239.07:36:29.30#ibcon#flushed, iclass 17, count 0 2006.239.07:36:29.30#ibcon#about to write, iclass 17, count 0 2006.239.07:36:29.30#ibcon#wrote, iclass 17, count 0 2006.239.07:36:29.30#ibcon#about to read 3, iclass 17, count 0 2006.239.07:36:29.33#ibcon#read 3, iclass 17, count 0 2006.239.07:36:29.33#ibcon#about to read 4, iclass 17, count 0 2006.239.07:36:29.33#ibcon#read 4, iclass 17, count 0 2006.239.07:36:29.33#ibcon#about to read 5, iclass 17, count 0 2006.239.07:36:29.33#ibcon#read 5, iclass 17, count 0 2006.239.07:36:29.33#ibcon#about to read 6, iclass 17, count 0 2006.239.07:36:29.33#ibcon#read 6, iclass 17, count 0 2006.239.07:36:29.33#ibcon#end of sib2, iclass 17, count 0 2006.239.07:36:29.33#ibcon#*after write, iclass 17, count 0 2006.239.07:36:29.33#ibcon#*before return 0, iclass 17, count 0 2006.239.07:36:29.33#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:36:29.33#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:36:29.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:36:29.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:36:29.33$vc4f8/valo=8,852.99 2006.239.07:36:29.33#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.07:36:29.33#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.07:36:29.33#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:29.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:36:29.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:36:29.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:36:29.33#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:36:29.33#ibcon#first serial, iclass 19, count 0 2006.239.07:36:29.33#ibcon#enter sib2, iclass 19, count 0 2006.239.07:36:29.33#ibcon#flushed, iclass 19, count 0 2006.239.07:36:29.33#ibcon#about to write, iclass 19, count 0 2006.239.07:36:29.33#ibcon#wrote, iclass 19, count 0 2006.239.07:36:29.33#ibcon#about to read 3, iclass 19, count 0 2006.239.07:36:29.35#ibcon#read 3, iclass 19, count 0 2006.239.07:36:29.35#ibcon#about to read 4, iclass 19, count 0 2006.239.07:36:29.35#ibcon#read 4, iclass 19, count 0 2006.239.07:36:29.35#ibcon#about to read 5, iclass 19, count 0 2006.239.07:36:29.35#ibcon#read 5, iclass 19, count 0 2006.239.07:36:29.35#ibcon#about to read 6, iclass 19, count 0 2006.239.07:36:29.35#ibcon#read 6, iclass 19, count 0 2006.239.07:36:29.35#ibcon#end of sib2, iclass 19, count 0 2006.239.07:36:29.35#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:36:29.35#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:36:29.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:36:29.35#ibcon#*before write, iclass 19, count 0 2006.239.07:36:29.35#ibcon#enter sib2, iclass 19, count 0 2006.239.07:36:29.35#ibcon#flushed, iclass 19, count 0 2006.239.07:36:29.35#ibcon#about to write, iclass 19, count 0 2006.239.07:36:29.35#ibcon#wrote, iclass 19, count 0 2006.239.07:36:29.35#ibcon#about to read 3, iclass 19, count 0 2006.239.07:36:29.39#ibcon#read 3, iclass 19, count 0 2006.239.07:36:29.39#ibcon#about to read 4, iclass 19, count 0 2006.239.07:36:29.39#ibcon#read 4, iclass 19, count 0 2006.239.07:36:29.39#ibcon#about to read 5, iclass 19, count 0 2006.239.07:36:29.39#ibcon#read 5, iclass 19, count 0 2006.239.07:36:29.39#ibcon#about to read 6, iclass 19, count 0 2006.239.07:36:29.39#ibcon#read 6, iclass 19, count 0 2006.239.07:36:29.39#ibcon#end of sib2, iclass 19, count 0 2006.239.07:36:29.39#ibcon#*after write, iclass 19, count 0 2006.239.07:36:29.39#ibcon#*before return 0, iclass 19, count 0 2006.239.07:36:29.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:36:29.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:36:29.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:36:29.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:36:29.39$vc4f8/va=8,7 2006.239.07:36:29.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:36:29.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:36:29.39#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:29.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:36:29.40#abcon#<5=/04 2.1 4.2 25.38 811011.4\r\n> 2006.239.07:36:29.42#abcon#{5=INTERFACE CLEAR} 2006.239.07:36:29.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:36:29.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:36:29.45#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:36:29.45#ibcon#first serial, iclass 22, count 2 2006.239.07:36:29.45#ibcon#enter sib2, iclass 22, count 2 2006.239.07:36:29.45#ibcon#flushed, iclass 22, count 2 2006.239.07:36:29.45#ibcon#about to write, iclass 22, count 2 2006.239.07:36:29.45#ibcon#wrote, iclass 22, count 2 2006.239.07:36:29.45#ibcon#about to read 3, iclass 22, count 2 2006.239.07:36:29.47#ibcon#read 3, iclass 22, count 2 2006.239.07:36:29.47#ibcon#about to read 4, iclass 22, count 2 2006.239.07:36:29.47#ibcon#read 4, iclass 22, count 2 2006.239.07:36:29.47#ibcon#about to read 5, iclass 22, count 2 2006.239.07:36:29.47#ibcon#read 5, iclass 22, count 2 2006.239.07:36:29.47#ibcon#about to read 6, iclass 22, count 2 2006.239.07:36:29.47#ibcon#read 6, iclass 22, count 2 2006.239.07:36:29.47#ibcon#end of sib2, iclass 22, count 2 2006.239.07:36:29.47#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:36:29.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:36:29.47#ibcon#[25=AT08-07\r\n] 2006.239.07:36:29.47#ibcon#*before write, iclass 22, count 2 2006.239.07:36:29.47#ibcon#enter sib2, iclass 22, count 2 2006.239.07:36:29.47#ibcon#flushed, iclass 22, count 2 2006.239.07:36:29.47#ibcon#about to write, iclass 22, count 2 2006.239.07:36:29.47#ibcon#wrote, iclass 22, count 2 2006.239.07:36:29.47#ibcon#about to read 3, iclass 22, count 2 2006.239.07:36:29.48#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:36:29.50#ibcon#read 3, iclass 22, count 2 2006.239.07:36:29.50#ibcon#about to read 4, iclass 22, count 2 2006.239.07:36:29.50#ibcon#read 4, iclass 22, count 2 2006.239.07:36:29.50#ibcon#about to read 5, iclass 22, count 2 2006.239.07:36:29.50#ibcon#read 5, iclass 22, count 2 2006.239.07:36:29.50#ibcon#about to read 6, iclass 22, count 2 2006.239.07:36:29.50#ibcon#read 6, iclass 22, count 2 2006.239.07:36:29.50#ibcon#end of sib2, iclass 22, count 2 2006.239.07:36:29.50#ibcon#*after write, iclass 22, count 2 2006.239.07:36:29.50#ibcon#*before return 0, iclass 22, count 2 2006.239.07:36:29.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:36:29.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:36:29.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:36:29.50#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:29.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:36:29.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:36:29.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:36:29.62#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:36:29.62#ibcon#first serial, iclass 22, count 0 2006.239.07:36:29.62#ibcon#enter sib2, iclass 22, count 0 2006.239.07:36:29.62#ibcon#flushed, iclass 22, count 0 2006.239.07:36:29.62#ibcon#about to write, iclass 22, count 0 2006.239.07:36:29.62#ibcon#wrote, iclass 22, count 0 2006.239.07:36:29.62#ibcon#about to read 3, iclass 22, count 0 2006.239.07:36:29.64#ibcon#read 3, iclass 22, count 0 2006.239.07:36:29.64#ibcon#about to read 4, iclass 22, count 0 2006.239.07:36:29.64#ibcon#read 4, iclass 22, count 0 2006.239.07:36:29.64#ibcon#about to read 5, iclass 22, count 0 2006.239.07:36:29.64#ibcon#read 5, iclass 22, count 0 2006.239.07:36:29.64#ibcon#about to read 6, iclass 22, count 0 2006.239.07:36:29.64#ibcon#read 6, iclass 22, count 0 2006.239.07:36:29.64#ibcon#end of sib2, iclass 22, count 0 2006.239.07:36:29.64#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:36:29.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:36:29.64#ibcon#[25=USB\r\n] 2006.239.07:36:29.64#ibcon#*before write, iclass 22, count 0 2006.239.07:36:29.64#ibcon#enter sib2, iclass 22, count 0 2006.239.07:36:29.64#ibcon#flushed, iclass 22, count 0 2006.239.07:36:29.64#ibcon#about to write, iclass 22, count 0 2006.239.07:36:29.64#ibcon#wrote, iclass 22, count 0 2006.239.07:36:29.64#ibcon#about to read 3, iclass 22, count 0 2006.239.07:36:29.67#ibcon#read 3, iclass 22, count 0 2006.239.07:36:29.67#ibcon#about to read 4, iclass 22, count 0 2006.239.07:36:29.67#ibcon#read 4, iclass 22, count 0 2006.239.07:36:29.67#ibcon#about to read 5, iclass 22, count 0 2006.239.07:36:29.67#ibcon#read 5, iclass 22, count 0 2006.239.07:36:29.67#ibcon#about to read 6, iclass 22, count 0 2006.239.07:36:29.67#ibcon#read 6, iclass 22, count 0 2006.239.07:36:29.67#ibcon#end of sib2, iclass 22, count 0 2006.239.07:36:29.67#ibcon#*after write, iclass 22, count 0 2006.239.07:36:29.67#ibcon#*before return 0, iclass 22, count 0 2006.239.07:36:29.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:36:29.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:36:29.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:36:29.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:36:29.67$vc4f8/vblo=1,632.99 2006.239.07:36:29.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.07:36:29.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.07:36:29.67#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:29.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:29.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:29.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:29.67#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:36:29.67#ibcon#first serial, iclass 27, count 0 2006.239.07:36:29.67#ibcon#enter sib2, iclass 27, count 0 2006.239.07:36:29.67#ibcon#flushed, iclass 27, count 0 2006.239.07:36:29.67#ibcon#about to write, iclass 27, count 0 2006.239.07:36:29.67#ibcon#wrote, iclass 27, count 0 2006.239.07:36:29.67#ibcon#about to read 3, iclass 27, count 0 2006.239.07:36:29.69#ibcon#read 3, iclass 27, count 0 2006.239.07:36:29.69#ibcon#about to read 4, iclass 27, count 0 2006.239.07:36:29.69#ibcon#read 4, iclass 27, count 0 2006.239.07:36:29.69#ibcon#about to read 5, iclass 27, count 0 2006.239.07:36:29.69#ibcon#read 5, iclass 27, count 0 2006.239.07:36:29.69#ibcon#about to read 6, iclass 27, count 0 2006.239.07:36:29.69#ibcon#read 6, iclass 27, count 0 2006.239.07:36:29.69#ibcon#end of sib2, iclass 27, count 0 2006.239.07:36:29.69#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:36:29.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:36:29.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:36:29.69#ibcon#*before write, iclass 27, count 0 2006.239.07:36:29.69#ibcon#enter sib2, iclass 27, count 0 2006.239.07:36:29.69#ibcon#flushed, iclass 27, count 0 2006.239.07:36:29.69#ibcon#about to write, iclass 27, count 0 2006.239.07:36:29.69#ibcon#wrote, iclass 27, count 0 2006.239.07:36:29.69#ibcon#about to read 3, iclass 27, count 0 2006.239.07:36:29.73#ibcon#read 3, iclass 27, count 0 2006.239.07:36:29.73#ibcon#about to read 4, iclass 27, count 0 2006.239.07:36:29.73#ibcon#read 4, iclass 27, count 0 2006.239.07:36:29.73#ibcon#about to read 5, iclass 27, count 0 2006.239.07:36:29.73#ibcon#read 5, iclass 27, count 0 2006.239.07:36:29.73#ibcon#about to read 6, iclass 27, count 0 2006.239.07:36:29.73#ibcon#read 6, iclass 27, count 0 2006.239.07:36:29.73#ibcon#end of sib2, iclass 27, count 0 2006.239.07:36:29.73#ibcon#*after write, iclass 27, count 0 2006.239.07:36:29.73#ibcon#*before return 0, iclass 27, count 0 2006.239.07:36:29.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:29.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:36:29.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:36:29.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:36:29.73$vc4f8/vb=1,4 2006.239.07:36:29.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.07:36:29.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.07:36:29.73#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:29.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:29.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:29.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:29.73#ibcon#enter wrdev, iclass 29, count 2 2006.239.07:36:29.73#ibcon#first serial, iclass 29, count 2 2006.239.07:36:29.73#ibcon#enter sib2, iclass 29, count 2 2006.239.07:36:29.73#ibcon#flushed, iclass 29, count 2 2006.239.07:36:29.73#ibcon#about to write, iclass 29, count 2 2006.239.07:36:29.73#ibcon#wrote, iclass 29, count 2 2006.239.07:36:29.73#ibcon#about to read 3, iclass 29, count 2 2006.239.07:36:29.75#ibcon#read 3, iclass 29, count 2 2006.239.07:36:29.75#ibcon#about to read 4, iclass 29, count 2 2006.239.07:36:29.75#ibcon#read 4, iclass 29, count 2 2006.239.07:36:29.75#ibcon#about to read 5, iclass 29, count 2 2006.239.07:36:29.75#ibcon#read 5, iclass 29, count 2 2006.239.07:36:29.75#ibcon#about to read 6, iclass 29, count 2 2006.239.07:36:29.75#ibcon#read 6, iclass 29, count 2 2006.239.07:36:29.75#ibcon#end of sib2, iclass 29, count 2 2006.239.07:36:29.75#ibcon#*mode == 0, iclass 29, count 2 2006.239.07:36:29.75#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.07:36:29.75#ibcon#[27=AT01-04\r\n] 2006.239.07:36:29.75#ibcon#*before write, iclass 29, count 2 2006.239.07:36:29.75#ibcon#enter sib2, iclass 29, count 2 2006.239.07:36:29.75#ibcon#flushed, iclass 29, count 2 2006.239.07:36:29.75#ibcon#about to write, iclass 29, count 2 2006.239.07:36:29.75#ibcon#wrote, iclass 29, count 2 2006.239.07:36:29.75#ibcon#about to read 3, iclass 29, count 2 2006.239.07:36:29.78#ibcon#read 3, iclass 29, count 2 2006.239.07:36:29.78#ibcon#about to read 4, iclass 29, count 2 2006.239.07:36:29.78#ibcon#read 4, iclass 29, count 2 2006.239.07:36:29.78#ibcon#about to read 5, iclass 29, count 2 2006.239.07:36:29.78#ibcon#read 5, iclass 29, count 2 2006.239.07:36:29.78#ibcon#about to read 6, iclass 29, count 2 2006.239.07:36:29.78#ibcon#read 6, iclass 29, count 2 2006.239.07:36:29.78#ibcon#end of sib2, iclass 29, count 2 2006.239.07:36:29.78#ibcon#*after write, iclass 29, count 2 2006.239.07:36:29.78#ibcon#*before return 0, iclass 29, count 2 2006.239.07:36:29.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:29.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:36:29.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.07:36:29.78#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:29.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:29.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:29.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:29.90#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:36:29.90#ibcon#first serial, iclass 29, count 0 2006.239.07:36:29.90#ibcon#enter sib2, iclass 29, count 0 2006.239.07:36:29.90#ibcon#flushed, iclass 29, count 0 2006.239.07:36:29.90#ibcon#about to write, iclass 29, count 0 2006.239.07:36:29.90#ibcon#wrote, iclass 29, count 0 2006.239.07:36:29.90#ibcon#about to read 3, iclass 29, count 0 2006.239.07:36:29.92#ibcon#read 3, iclass 29, count 0 2006.239.07:36:29.92#ibcon#about to read 4, iclass 29, count 0 2006.239.07:36:29.92#ibcon#read 4, iclass 29, count 0 2006.239.07:36:29.92#ibcon#about to read 5, iclass 29, count 0 2006.239.07:36:29.92#ibcon#read 5, iclass 29, count 0 2006.239.07:36:29.92#ibcon#about to read 6, iclass 29, count 0 2006.239.07:36:29.92#ibcon#read 6, iclass 29, count 0 2006.239.07:36:29.92#ibcon#end of sib2, iclass 29, count 0 2006.239.07:36:29.92#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:36:29.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:36:29.92#ibcon#[27=USB\r\n] 2006.239.07:36:29.92#ibcon#*before write, iclass 29, count 0 2006.239.07:36:29.92#ibcon#enter sib2, iclass 29, count 0 2006.239.07:36:29.92#ibcon#flushed, iclass 29, count 0 2006.239.07:36:29.92#ibcon#about to write, iclass 29, count 0 2006.239.07:36:29.92#ibcon#wrote, iclass 29, count 0 2006.239.07:36:29.92#ibcon#about to read 3, iclass 29, count 0 2006.239.07:36:29.95#ibcon#read 3, iclass 29, count 0 2006.239.07:36:29.95#ibcon#about to read 4, iclass 29, count 0 2006.239.07:36:29.95#ibcon#read 4, iclass 29, count 0 2006.239.07:36:29.95#ibcon#about to read 5, iclass 29, count 0 2006.239.07:36:29.95#ibcon#read 5, iclass 29, count 0 2006.239.07:36:29.95#ibcon#about to read 6, iclass 29, count 0 2006.239.07:36:29.95#ibcon#read 6, iclass 29, count 0 2006.239.07:36:29.95#ibcon#end of sib2, iclass 29, count 0 2006.239.07:36:29.95#ibcon#*after write, iclass 29, count 0 2006.239.07:36:29.95#ibcon#*before return 0, iclass 29, count 0 2006.239.07:36:29.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:29.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:36:29.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:36:29.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:36:29.95$vc4f8/vblo=2,640.99 2006.239.07:36:29.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.07:36:29.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.07:36:29.95#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:29.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:29.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:29.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:29.95#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:36:29.95#ibcon#first serial, iclass 31, count 0 2006.239.07:36:29.95#ibcon#enter sib2, iclass 31, count 0 2006.239.07:36:29.95#ibcon#flushed, iclass 31, count 0 2006.239.07:36:29.95#ibcon#about to write, iclass 31, count 0 2006.239.07:36:29.95#ibcon#wrote, iclass 31, count 0 2006.239.07:36:29.95#ibcon#about to read 3, iclass 31, count 0 2006.239.07:36:29.97#ibcon#read 3, iclass 31, count 0 2006.239.07:36:29.97#ibcon#about to read 4, iclass 31, count 0 2006.239.07:36:29.97#ibcon#read 4, iclass 31, count 0 2006.239.07:36:29.97#ibcon#about to read 5, iclass 31, count 0 2006.239.07:36:29.97#ibcon#read 5, iclass 31, count 0 2006.239.07:36:29.97#ibcon#about to read 6, iclass 31, count 0 2006.239.07:36:29.97#ibcon#read 6, iclass 31, count 0 2006.239.07:36:29.97#ibcon#end of sib2, iclass 31, count 0 2006.239.07:36:29.97#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:36:29.97#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:36:29.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:36:29.97#ibcon#*before write, iclass 31, count 0 2006.239.07:36:29.97#ibcon#enter sib2, iclass 31, count 0 2006.239.07:36:29.97#ibcon#flushed, iclass 31, count 0 2006.239.07:36:29.97#ibcon#about to write, iclass 31, count 0 2006.239.07:36:29.97#ibcon#wrote, iclass 31, count 0 2006.239.07:36:29.97#ibcon#about to read 3, iclass 31, count 0 2006.239.07:36:30.01#ibcon#read 3, iclass 31, count 0 2006.239.07:36:30.01#ibcon#about to read 4, iclass 31, count 0 2006.239.07:36:30.01#ibcon#read 4, iclass 31, count 0 2006.239.07:36:30.01#ibcon#about to read 5, iclass 31, count 0 2006.239.07:36:30.01#ibcon#read 5, iclass 31, count 0 2006.239.07:36:30.01#ibcon#about to read 6, iclass 31, count 0 2006.239.07:36:30.01#ibcon#read 6, iclass 31, count 0 2006.239.07:36:30.01#ibcon#end of sib2, iclass 31, count 0 2006.239.07:36:30.01#ibcon#*after write, iclass 31, count 0 2006.239.07:36:30.01#ibcon#*before return 0, iclass 31, count 0 2006.239.07:36:30.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:30.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:36:30.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:36:30.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:36:30.01$vc4f8/vb=2,4 2006.239.07:36:30.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.07:36:30.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.07:36:30.01#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:30.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:30.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:30.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:30.07#ibcon#enter wrdev, iclass 33, count 2 2006.239.07:36:30.07#ibcon#first serial, iclass 33, count 2 2006.239.07:36:30.07#ibcon#enter sib2, iclass 33, count 2 2006.239.07:36:30.07#ibcon#flushed, iclass 33, count 2 2006.239.07:36:30.07#ibcon#about to write, iclass 33, count 2 2006.239.07:36:30.07#ibcon#wrote, iclass 33, count 2 2006.239.07:36:30.07#ibcon#about to read 3, iclass 33, count 2 2006.239.07:36:30.09#ibcon#read 3, iclass 33, count 2 2006.239.07:36:30.09#ibcon#about to read 4, iclass 33, count 2 2006.239.07:36:30.09#ibcon#read 4, iclass 33, count 2 2006.239.07:36:30.09#ibcon#about to read 5, iclass 33, count 2 2006.239.07:36:30.09#ibcon#read 5, iclass 33, count 2 2006.239.07:36:30.09#ibcon#about to read 6, iclass 33, count 2 2006.239.07:36:30.09#ibcon#read 6, iclass 33, count 2 2006.239.07:36:30.09#ibcon#end of sib2, iclass 33, count 2 2006.239.07:36:30.09#ibcon#*mode == 0, iclass 33, count 2 2006.239.07:36:30.09#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.07:36:30.09#ibcon#[27=AT02-04\r\n] 2006.239.07:36:30.09#ibcon#*before write, iclass 33, count 2 2006.239.07:36:30.09#ibcon#enter sib2, iclass 33, count 2 2006.239.07:36:30.09#ibcon#flushed, iclass 33, count 2 2006.239.07:36:30.09#ibcon#about to write, iclass 33, count 2 2006.239.07:36:30.09#ibcon#wrote, iclass 33, count 2 2006.239.07:36:30.09#ibcon#about to read 3, iclass 33, count 2 2006.239.07:36:30.12#ibcon#read 3, iclass 33, count 2 2006.239.07:36:30.12#ibcon#about to read 4, iclass 33, count 2 2006.239.07:36:30.12#ibcon#read 4, iclass 33, count 2 2006.239.07:36:30.12#ibcon#about to read 5, iclass 33, count 2 2006.239.07:36:30.12#ibcon#read 5, iclass 33, count 2 2006.239.07:36:30.12#ibcon#about to read 6, iclass 33, count 2 2006.239.07:36:30.12#ibcon#read 6, iclass 33, count 2 2006.239.07:36:30.12#ibcon#end of sib2, iclass 33, count 2 2006.239.07:36:30.12#ibcon#*after write, iclass 33, count 2 2006.239.07:36:30.12#ibcon#*before return 0, iclass 33, count 2 2006.239.07:36:30.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:30.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:36:30.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.07:36:30.12#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:30.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:30.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:30.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:30.26#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:36:30.26#ibcon#first serial, iclass 33, count 0 2006.239.07:36:30.26#ibcon#enter sib2, iclass 33, count 0 2006.239.07:36:30.26#ibcon#flushed, iclass 33, count 0 2006.239.07:36:30.26#ibcon#about to write, iclass 33, count 0 2006.239.07:36:30.26#ibcon#wrote, iclass 33, count 0 2006.239.07:36:30.26#ibcon#about to read 3, iclass 33, count 0 2006.239.07:36:30.27#ibcon#read 3, iclass 33, count 0 2006.239.07:36:30.27#ibcon#about to read 4, iclass 33, count 0 2006.239.07:36:30.27#ibcon#read 4, iclass 33, count 0 2006.239.07:36:30.27#ibcon#about to read 5, iclass 33, count 0 2006.239.07:36:30.27#ibcon#read 5, iclass 33, count 0 2006.239.07:36:30.27#ibcon#about to read 6, iclass 33, count 0 2006.239.07:36:30.27#ibcon#read 6, iclass 33, count 0 2006.239.07:36:30.27#ibcon#end of sib2, iclass 33, count 0 2006.239.07:36:30.27#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:36:30.27#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:36:30.27#ibcon#[27=USB\r\n] 2006.239.07:36:30.27#ibcon#*before write, iclass 33, count 0 2006.239.07:36:30.27#ibcon#enter sib2, iclass 33, count 0 2006.239.07:36:30.27#ibcon#flushed, iclass 33, count 0 2006.239.07:36:30.27#ibcon#about to write, iclass 33, count 0 2006.239.07:36:30.27#ibcon#wrote, iclass 33, count 0 2006.239.07:36:30.27#ibcon#about to read 3, iclass 33, count 0 2006.239.07:36:30.30#ibcon#read 3, iclass 33, count 0 2006.239.07:36:30.30#ibcon#about to read 4, iclass 33, count 0 2006.239.07:36:30.30#ibcon#read 4, iclass 33, count 0 2006.239.07:36:30.30#ibcon#about to read 5, iclass 33, count 0 2006.239.07:36:30.30#ibcon#read 5, iclass 33, count 0 2006.239.07:36:30.30#ibcon#about to read 6, iclass 33, count 0 2006.239.07:36:30.30#ibcon#read 6, iclass 33, count 0 2006.239.07:36:30.30#ibcon#end of sib2, iclass 33, count 0 2006.239.07:36:30.30#ibcon#*after write, iclass 33, count 0 2006.239.07:36:30.30#ibcon#*before return 0, iclass 33, count 0 2006.239.07:36:30.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:30.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:36:30.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:36:30.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:36:30.30$vc4f8/vblo=3,656.99 2006.239.07:36:30.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.07:36:30.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.07:36:30.30#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:30.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:30.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:30.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:30.30#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:36:30.30#ibcon#first serial, iclass 35, count 0 2006.239.07:36:30.30#ibcon#enter sib2, iclass 35, count 0 2006.239.07:36:30.30#ibcon#flushed, iclass 35, count 0 2006.239.07:36:30.30#ibcon#about to write, iclass 35, count 0 2006.239.07:36:30.30#ibcon#wrote, iclass 35, count 0 2006.239.07:36:30.30#ibcon#about to read 3, iclass 35, count 0 2006.239.07:36:30.32#ibcon#read 3, iclass 35, count 0 2006.239.07:36:30.32#ibcon#about to read 4, iclass 35, count 0 2006.239.07:36:30.32#ibcon#read 4, iclass 35, count 0 2006.239.07:36:30.32#ibcon#about to read 5, iclass 35, count 0 2006.239.07:36:30.32#ibcon#read 5, iclass 35, count 0 2006.239.07:36:30.32#ibcon#about to read 6, iclass 35, count 0 2006.239.07:36:30.32#ibcon#read 6, iclass 35, count 0 2006.239.07:36:30.32#ibcon#end of sib2, iclass 35, count 0 2006.239.07:36:30.32#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:36:30.32#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:36:30.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:36:30.32#ibcon#*before write, iclass 35, count 0 2006.239.07:36:30.32#ibcon#enter sib2, iclass 35, count 0 2006.239.07:36:30.32#ibcon#flushed, iclass 35, count 0 2006.239.07:36:30.32#ibcon#about to write, iclass 35, count 0 2006.239.07:36:30.32#ibcon#wrote, iclass 35, count 0 2006.239.07:36:30.32#ibcon#about to read 3, iclass 35, count 0 2006.239.07:36:30.36#ibcon#read 3, iclass 35, count 0 2006.239.07:36:30.36#ibcon#about to read 4, iclass 35, count 0 2006.239.07:36:30.36#ibcon#read 4, iclass 35, count 0 2006.239.07:36:30.36#ibcon#about to read 5, iclass 35, count 0 2006.239.07:36:30.36#ibcon#read 5, iclass 35, count 0 2006.239.07:36:30.36#ibcon#about to read 6, iclass 35, count 0 2006.239.07:36:30.36#ibcon#read 6, iclass 35, count 0 2006.239.07:36:30.36#ibcon#end of sib2, iclass 35, count 0 2006.239.07:36:30.36#ibcon#*after write, iclass 35, count 0 2006.239.07:36:30.36#ibcon#*before return 0, iclass 35, count 0 2006.239.07:36:30.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:30.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:36:30.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:36:30.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:36:30.36$vc4f8/vb=3,4 2006.239.07:36:30.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.07:36:30.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.07:36:30.36#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:30.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:30.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:30.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:30.42#ibcon#enter wrdev, iclass 37, count 2 2006.239.07:36:30.42#ibcon#first serial, iclass 37, count 2 2006.239.07:36:30.42#ibcon#enter sib2, iclass 37, count 2 2006.239.07:36:30.42#ibcon#flushed, iclass 37, count 2 2006.239.07:36:30.42#ibcon#about to write, iclass 37, count 2 2006.239.07:36:30.42#ibcon#wrote, iclass 37, count 2 2006.239.07:36:30.42#ibcon#about to read 3, iclass 37, count 2 2006.239.07:36:30.44#ibcon#read 3, iclass 37, count 2 2006.239.07:36:30.44#ibcon#about to read 4, iclass 37, count 2 2006.239.07:36:30.44#ibcon#read 4, iclass 37, count 2 2006.239.07:36:30.44#ibcon#about to read 5, iclass 37, count 2 2006.239.07:36:30.44#ibcon#read 5, iclass 37, count 2 2006.239.07:36:30.44#ibcon#about to read 6, iclass 37, count 2 2006.239.07:36:30.44#ibcon#read 6, iclass 37, count 2 2006.239.07:36:30.44#ibcon#end of sib2, iclass 37, count 2 2006.239.07:36:30.44#ibcon#*mode == 0, iclass 37, count 2 2006.239.07:36:30.44#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.07:36:30.44#ibcon#[27=AT03-04\r\n] 2006.239.07:36:30.44#ibcon#*before write, iclass 37, count 2 2006.239.07:36:30.44#ibcon#enter sib2, iclass 37, count 2 2006.239.07:36:30.44#ibcon#flushed, iclass 37, count 2 2006.239.07:36:30.44#ibcon#about to write, iclass 37, count 2 2006.239.07:36:30.44#ibcon#wrote, iclass 37, count 2 2006.239.07:36:30.44#ibcon#about to read 3, iclass 37, count 2 2006.239.07:36:30.47#ibcon#read 3, iclass 37, count 2 2006.239.07:36:30.47#ibcon#about to read 4, iclass 37, count 2 2006.239.07:36:30.47#ibcon#read 4, iclass 37, count 2 2006.239.07:36:30.47#ibcon#about to read 5, iclass 37, count 2 2006.239.07:36:30.47#ibcon#read 5, iclass 37, count 2 2006.239.07:36:30.47#ibcon#about to read 6, iclass 37, count 2 2006.239.07:36:30.47#ibcon#read 6, iclass 37, count 2 2006.239.07:36:30.47#ibcon#end of sib2, iclass 37, count 2 2006.239.07:36:30.47#ibcon#*after write, iclass 37, count 2 2006.239.07:36:30.47#ibcon#*before return 0, iclass 37, count 2 2006.239.07:36:30.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:30.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:36:30.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.07:36:30.47#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:30.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:30.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:30.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:30.59#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:36:30.59#ibcon#first serial, iclass 37, count 0 2006.239.07:36:30.59#ibcon#enter sib2, iclass 37, count 0 2006.239.07:36:30.59#ibcon#flushed, iclass 37, count 0 2006.239.07:36:30.59#ibcon#about to write, iclass 37, count 0 2006.239.07:36:30.59#ibcon#wrote, iclass 37, count 0 2006.239.07:36:30.59#ibcon#about to read 3, iclass 37, count 0 2006.239.07:36:30.61#ibcon#read 3, iclass 37, count 0 2006.239.07:36:30.61#ibcon#about to read 4, iclass 37, count 0 2006.239.07:36:30.61#ibcon#read 4, iclass 37, count 0 2006.239.07:36:30.61#ibcon#about to read 5, iclass 37, count 0 2006.239.07:36:30.61#ibcon#read 5, iclass 37, count 0 2006.239.07:36:30.61#ibcon#about to read 6, iclass 37, count 0 2006.239.07:36:30.61#ibcon#read 6, iclass 37, count 0 2006.239.07:36:30.61#ibcon#end of sib2, iclass 37, count 0 2006.239.07:36:30.61#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:36:30.61#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:36:30.61#ibcon#[27=USB\r\n] 2006.239.07:36:30.61#ibcon#*before write, iclass 37, count 0 2006.239.07:36:30.61#ibcon#enter sib2, iclass 37, count 0 2006.239.07:36:30.61#ibcon#flushed, iclass 37, count 0 2006.239.07:36:30.61#ibcon#about to write, iclass 37, count 0 2006.239.07:36:30.61#ibcon#wrote, iclass 37, count 0 2006.239.07:36:30.61#ibcon#about to read 3, iclass 37, count 0 2006.239.07:36:30.64#ibcon#read 3, iclass 37, count 0 2006.239.07:36:30.64#ibcon#about to read 4, iclass 37, count 0 2006.239.07:36:30.64#ibcon#read 4, iclass 37, count 0 2006.239.07:36:30.64#ibcon#about to read 5, iclass 37, count 0 2006.239.07:36:30.64#ibcon#read 5, iclass 37, count 0 2006.239.07:36:30.64#ibcon#about to read 6, iclass 37, count 0 2006.239.07:36:30.64#ibcon#read 6, iclass 37, count 0 2006.239.07:36:30.64#ibcon#end of sib2, iclass 37, count 0 2006.239.07:36:30.64#ibcon#*after write, iclass 37, count 0 2006.239.07:36:30.64#ibcon#*before return 0, iclass 37, count 0 2006.239.07:36:30.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:30.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:36:30.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:36:30.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:36:30.64$vc4f8/vblo=4,712.99 2006.239.07:36:30.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.07:36:30.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.07:36:30.64#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:30.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:30.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:30.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:30.64#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:36:30.64#ibcon#first serial, iclass 39, count 0 2006.239.07:36:30.64#ibcon#enter sib2, iclass 39, count 0 2006.239.07:36:30.64#ibcon#flushed, iclass 39, count 0 2006.239.07:36:30.64#ibcon#about to write, iclass 39, count 0 2006.239.07:36:30.64#ibcon#wrote, iclass 39, count 0 2006.239.07:36:30.64#ibcon#about to read 3, iclass 39, count 0 2006.239.07:36:30.66#ibcon#read 3, iclass 39, count 0 2006.239.07:36:30.66#ibcon#about to read 4, iclass 39, count 0 2006.239.07:36:30.66#ibcon#read 4, iclass 39, count 0 2006.239.07:36:30.66#ibcon#about to read 5, iclass 39, count 0 2006.239.07:36:30.66#ibcon#read 5, iclass 39, count 0 2006.239.07:36:30.66#ibcon#about to read 6, iclass 39, count 0 2006.239.07:36:30.66#ibcon#read 6, iclass 39, count 0 2006.239.07:36:30.66#ibcon#end of sib2, iclass 39, count 0 2006.239.07:36:30.66#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:36:30.66#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:36:30.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:36:30.66#ibcon#*before write, iclass 39, count 0 2006.239.07:36:30.66#ibcon#enter sib2, iclass 39, count 0 2006.239.07:36:30.66#ibcon#flushed, iclass 39, count 0 2006.239.07:36:30.66#ibcon#about to write, iclass 39, count 0 2006.239.07:36:30.66#ibcon#wrote, iclass 39, count 0 2006.239.07:36:30.66#ibcon#about to read 3, iclass 39, count 0 2006.239.07:36:30.70#ibcon#read 3, iclass 39, count 0 2006.239.07:36:30.70#ibcon#about to read 4, iclass 39, count 0 2006.239.07:36:30.70#ibcon#read 4, iclass 39, count 0 2006.239.07:36:30.70#ibcon#about to read 5, iclass 39, count 0 2006.239.07:36:30.70#ibcon#read 5, iclass 39, count 0 2006.239.07:36:30.70#ibcon#about to read 6, iclass 39, count 0 2006.239.07:36:30.70#ibcon#read 6, iclass 39, count 0 2006.239.07:36:30.70#ibcon#end of sib2, iclass 39, count 0 2006.239.07:36:30.70#ibcon#*after write, iclass 39, count 0 2006.239.07:36:30.70#ibcon#*before return 0, iclass 39, count 0 2006.239.07:36:30.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:30.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:36:30.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:36:30.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:36:30.70$vc4f8/vb=4,4 2006.239.07:36:30.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.07:36:30.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.07:36:30.70#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:30.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:30.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:30.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:30.77#ibcon#enter wrdev, iclass 3, count 2 2006.239.07:36:30.77#ibcon#first serial, iclass 3, count 2 2006.239.07:36:30.77#ibcon#enter sib2, iclass 3, count 2 2006.239.07:36:30.77#ibcon#flushed, iclass 3, count 2 2006.239.07:36:30.77#ibcon#about to write, iclass 3, count 2 2006.239.07:36:30.77#ibcon#wrote, iclass 3, count 2 2006.239.07:36:30.77#ibcon#about to read 3, iclass 3, count 2 2006.239.07:36:30.78#ibcon#read 3, iclass 3, count 2 2006.239.07:36:30.78#ibcon#about to read 4, iclass 3, count 2 2006.239.07:36:30.78#ibcon#read 4, iclass 3, count 2 2006.239.07:36:30.78#ibcon#about to read 5, iclass 3, count 2 2006.239.07:36:30.78#ibcon#read 5, iclass 3, count 2 2006.239.07:36:30.78#ibcon#about to read 6, iclass 3, count 2 2006.239.07:36:30.78#ibcon#read 6, iclass 3, count 2 2006.239.07:36:30.78#ibcon#end of sib2, iclass 3, count 2 2006.239.07:36:30.78#ibcon#*mode == 0, iclass 3, count 2 2006.239.07:36:30.78#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.07:36:30.78#ibcon#[27=AT04-04\r\n] 2006.239.07:36:30.78#ibcon#*before write, iclass 3, count 2 2006.239.07:36:30.78#ibcon#enter sib2, iclass 3, count 2 2006.239.07:36:30.78#ibcon#flushed, iclass 3, count 2 2006.239.07:36:30.78#ibcon#about to write, iclass 3, count 2 2006.239.07:36:30.78#ibcon#wrote, iclass 3, count 2 2006.239.07:36:30.78#ibcon#about to read 3, iclass 3, count 2 2006.239.07:36:30.81#ibcon#read 3, iclass 3, count 2 2006.239.07:36:30.81#ibcon#about to read 4, iclass 3, count 2 2006.239.07:36:30.81#ibcon#read 4, iclass 3, count 2 2006.239.07:36:30.81#ibcon#about to read 5, iclass 3, count 2 2006.239.07:36:30.81#ibcon#read 5, iclass 3, count 2 2006.239.07:36:30.81#ibcon#about to read 6, iclass 3, count 2 2006.239.07:36:30.81#ibcon#read 6, iclass 3, count 2 2006.239.07:36:30.81#ibcon#end of sib2, iclass 3, count 2 2006.239.07:36:30.81#ibcon#*after write, iclass 3, count 2 2006.239.07:36:30.81#ibcon#*before return 0, iclass 3, count 2 2006.239.07:36:30.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:30.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:36:30.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.07:36:30.81#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:30.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:30.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:30.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:30.93#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:36:30.93#ibcon#first serial, iclass 3, count 0 2006.239.07:36:30.93#ibcon#enter sib2, iclass 3, count 0 2006.239.07:36:30.93#ibcon#flushed, iclass 3, count 0 2006.239.07:36:30.93#ibcon#about to write, iclass 3, count 0 2006.239.07:36:30.93#ibcon#wrote, iclass 3, count 0 2006.239.07:36:30.93#ibcon#about to read 3, iclass 3, count 0 2006.239.07:36:30.95#ibcon#read 3, iclass 3, count 0 2006.239.07:36:30.95#ibcon#about to read 4, iclass 3, count 0 2006.239.07:36:30.95#ibcon#read 4, iclass 3, count 0 2006.239.07:36:30.95#ibcon#about to read 5, iclass 3, count 0 2006.239.07:36:30.95#ibcon#read 5, iclass 3, count 0 2006.239.07:36:30.95#ibcon#about to read 6, iclass 3, count 0 2006.239.07:36:30.95#ibcon#read 6, iclass 3, count 0 2006.239.07:36:30.95#ibcon#end of sib2, iclass 3, count 0 2006.239.07:36:30.95#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:36:30.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:36:30.95#ibcon#[27=USB\r\n] 2006.239.07:36:30.95#ibcon#*before write, iclass 3, count 0 2006.239.07:36:30.95#ibcon#enter sib2, iclass 3, count 0 2006.239.07:36:30.95#ibcon#flushed, iclass 3, count 0 2006.239.07:36:30.95#ibcon#about to write, iclass 3, count 0 2006.239.07:36:30.95#ibcon#wrote, iclass 3, count 0 2006.239.07:36:30.95#ibcon#about to read 3, iclass 3, count 0 2006.239.07:36:30.98#ibcon#read 3, iclass 3, count 0 2006.239.07:36:30.98#ibcon#about to read 4, iclass 3, count 0 2006.239.07:36:30.98#ibcon#read 4, iclass 3, count 0 2006.239.07:36:30.98#ibcon#about to read 5, iclass 3, count 0 2006.239.07:36:30.98#ibcon#read 5, iclass 3, count 0 2006.239.07:36:30.98#ibcon#about to read 6, iclass 3, count 0 2006.239.07:36:30.98#ibcon#read 6, iclass 3, count 0 2006.239.07:36:30.98#ibcon#end of sib2, iclass 3, count 0 2006.239.07:36:30.98#ibcon#*after write, iclass 3, count 0 2006.239.07:36:30.98#ibcon#*before return 0, iclass 3, count 0 2006.239.07:36:30.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:30.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:36:30.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:36:30.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:36:30.98$vc4f8/vblo=5,744.99 2006.239.07:36:30.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:36:30.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:36:30.98#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:30.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:30.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:30.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:30.98#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:36:30.98#ibcon#first serial, iclass 5, count 0 2006.239.07:36:30.98#ibcon#enter sib2, iclass 5, count 0 2006.239.07:36:30.98#ibcon#flushed, iclass 5, count 0 2006.239.07:36:30.98#ibcon#about to write, iclass 5, count 0 2006.239.07:36:30.98#ibcon#wrote, iclass 5, count 0 2006.239.07:36:30.98#ibcon#about to read 3, iclass 5, count 0 2006.239.07:36:31.00#ibcon#read 3, iclass 5, count 0 2006.239.07:36:31.00#ibcon#about to read 4, iclass 5, count 0 2006.239.07:36:31.00#ibcon#read 4, iclass 5, count 0 2006.239.07:36:31.00#ibcon#about to read 5, iclass 5, count 0 2006.239.07:36:31.00#ibcon#read 5, iclass 5, count 0 2006.239.07:36:31.00#ibcon#about to read 6, iclass 5, count 0 2006.239.07:36:31.00#ibcon#read 6, iclass 5, count 0 2006.239.07:36:31.00#ibcon#end of sib2, iclass 5, count 0 2006.239.07:36:31.00#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:36:31.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:36:31.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:36:31.00#ibcon#*before write, iclass 5, count 0 2006.239.07:36:31.00#ibcon#enter sib2, iclass 5, count 0 2006.239.07:36:31.00#ibcon#flushed, iclass 5, count 0 2006.239.07:36:31.00#ibcon#about to write, iclass 5, count 0 2006.239.07:36:31.00#ibcon#wrote, iclass 5, count 0 2006.239.07:36:31.00#ibcon#about to read 3, iclass 5, count 0 2006.239.07:36:31.04#ibcon#read 3, iclass 5, count 0 2006.239.07:36:31.04#ibcon#about to read 4, iclass 5, count 0 2006.239.07:36:31.04#ibcon#read 4, iclass 5, count 0 2006.239.07:36:31.04#ibcon#about to read 5, iclass 5, count 0 2006.239.07:36:31.04#ibcon#read 5, iclass 5, count 0 2006.239.07:36:31.04#ibcon#about to read 6, iclass 5, count 0 2006.239.07:36:31.04#ibcon#read 6, iclass 5, count 0 2006.239.07:36:31.04#ibcon#end of sib2, iclass 5, count 0 2006.239.07:36:31.04#ibcon#*after write, iclass 5, count 0 2006.239.07:36:31.04#ibcon#*before return 0, iclass 5, count 0 2006.239.07:36:31.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:31.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:36:31.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:36:31.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:36:31.04$vc4f8/vb=5,4 2006.239.07:36:31.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.07:36:31.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.07:36:31.04#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:31.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:31.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:31.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:31.10#ibcon#enter wrdev, iclass 7, count 2 2006.239.07:36:31.10#ibcon#first serial, iclass 7, count 2 2006.239.07:36:31.10#ibcon#enter sib2, iclass 7, count 2 2006.239.07:36:31.10#ibcon#flushed, iclass 7, count 2 2006.239.07:36:31.10#ibcon#about to write, iclass 7, count 2 2006.239.07:36:31.10#ibcon#wrote, iclass 7, count 2 2006.239.07:36:31.10#ibcon#about to read 3, iclass 7, count 2 2006.239.07:36:31.12#ibcon#read 3, iclass 7, count 2 2006.239.07:36:31.12#ibcon#about to read 4, iclass 7, count 2 2006.239.07:36:31.12#ibcon#read 4, iclass 7, count 2 2006.239.07:36:31.12#ibcon#about to read 5, iclass 7, count 2 2006.239.07:36:31.12#ibcon#read 5, iclass 7, count 2 2006.239.07:36:31.12#ibcon#about to read 6, iclass 7, count 2 2006.239.07:36:31.12#ibcon#read 6, iclass 7, count 2 2006.239.07:36:31.12#ibcon#end of sib2, iclass 7, count 2 2006.239.07:36:31.12#ibcon#*mode == 0, iclass 7, count 2 2006.239.07:36:31.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.07:36:31.12#ibcon#[27=AT05-04\r\n] 2006.239.07:36:31.12#ibcon#*before write, iclass 7, count 2 2006.239.07:36:31.12#ibcon#enter sib2, iclass 7, count 2 2006.239.07:36:31.12#ibcon#flushed, iclass 7, count 2 2006.239.07:36:31.12#ibcon#about to write, iclass 7, count 2 2006.239.07:36:31.12#ibcon#wrote, iclass 7, count 2 2006.239.07:36:31.12#ibcon#about to read 3, iclass 7, count 2 2006.239.07:36:31.15#ibcon#read 3, iclass 7, count 2 2006.239.07:36:31.15#ibcon#about to read 4, iclass 7, count 2 2006.239.07:36:31.15#ibcon#read 4, iclass 7, count 2 2006.239.07:36:31.15#ibcon#about to read 5, iclass 7, count 2 2006.239.07:36:31.15#ibcon#read 5, iclass 7, count 2 2006.239.07:36:31.15#ibcon#about to read 6, iclass 7, count 2 2006.239.07:36:31.15#ibcon#read 6, iclass 7, count 2 2006.239.07:36:31.15#ibcon#end of sib2, iclass 7, count 2 2006.239.07:36:31.15#ibcon#*after write, iclass 7, count 2 2006.239.07:36:31.15#ibcon#*before return 0, iclass 7, count 2 2006.239.07:36:31.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:31.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:36:31.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.07:36:31.15#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:31.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:31.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:31.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:31.27#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:36:31.27#ibcon#first serial, iclass 7, count 0 2006.239.07:36:31.27#ibcon#enter sib2, iclass 7, count 0 2006.239.07:36:31.27#ibcon#flushed, iclass 7, count 0 2006.239.07:36:31.27#ibcon#about to write, iclass 7, count 0 2006.239.07:36:31.27#ibcon#wrote, iclass 7, count 0 2006.239.07:36:31.27#ibcon#about to read 3, iclass 7, count 0 2006.239.07:36:31.29#ibcon#read 3, iclass 7, count 0 2006.239.07:36:31.29#ibcon#about to read 4, iclass 7, count 0 2006.239.07:36:31.29#ibcon#read 4, iclass 7, count 0 2006.239.07:36:31.29#ibcon#about to read 5, iclass 7, count 0 2006.239.07:36:31.29#ibcon#read 5, iclass 7, count 0 2006.239.07:36:31.29#ibcon#about to read 6, iclass 7, count 0 2006.239.07:36:31.29#ibcon#read 6, iclass 7, count 0 2006.239.07:36:31.29#ibcon#end of sib2, iclass 7, count 0 2006.239.07:36:31.29#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:36:31.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:36:31.29#ibcon#[27=USB\r\n] 2006.239.07:36:31.29#ibcon#*before write, iclass 7, count 0 2006.239.07:36:31.29#ibcon#enter sib2, iclass 7, count 0 2006.239.07:36:31.29#ibcon#flushed, iclass 7, count 0 2006.239.07:36:31.29#ibcon#about to write, iclass 7, count 0 2006.239.07:36:31.29#ibcon#wrote, iclass 7, count 0 2006.239.07:36:31.29#ibcon#about to read 3, iclass 7, count 0 2006.239.07:36:31.32#ibcon#read 3, iclass 7, count 0 2006.239.07:36:31.32#ibcon#about to read 4, iclass 7, count 0 2006.239.07:36:31.32#ibcon#read 4, iclass 7, count 0 2006.239.07:36:31.32#ibcon#about to read 5, iclass 7, count 0 2006.239.07:36:31.32#ibcon#read 5, iclass 7, count 0 2006.239.07:36:31.32#ibcon#about to read 6, iclass 7, count 0 2006.239.07:36:31.32#ibcon#read 6, iclass 7, count 0 2006.239.07:36:31.32#ibcon#end of sib2, iclass 7, count 0 2006.239.07:36:31.32#ibcon#*after write, iclass 7, count 0 2006.239.07:36:31.32#ibcon#*before return 0, iclass 7, count 0 2006.239.07:36:31.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:31.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:36:31.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:36:31.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:36:31.32$vc4f8/vblo=6,752.99 2006.239.07:36:31.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.07:36:31.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.07:36:31.32#ibcon#ireg 17 cls_cnt 0 2006.239.07:36:31.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:31.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:31.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:31.32#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:36:31.32#ibcon#first serial, iclass 11, count 0 2006.239.07:36:31.32#ibcon#enter sib2, iclass 11, count 0 2006.239.07:36:31.32#ibcon#flushed, iclass 11, count 0 2006.239.07:36:31.32#ibcon#about to write, iclass 11, count 0 2006.239.07:36:31.32#ibcon#wrote, iclass 11, count 0 2006.239.07:36:31.32#ibcon#about to read 3, iclass 11, count 0 2006.239.07:36:31.34#ibcon#read 3, iclass 11, count 0 2006.239.07:36:31.34#ibcon#about to read 4, iclass 11, count 0 2006.239.07:36:31.34#ibcon#read 4, iclass 11, count 0 2006.239.07:36:31.34#ibcon#about to read 5, iclass 11, count 0 2006.239.07:36:31.34#ibcon#read 5, iclass 11, count 0 2006.239.07:36:31.34#ibcon#about to read 6, iclass 11, count 0 2006.239.07:36:31.34#ibcon#read 6, iclass 11, count 0 2006.239.07:36:31.34#ibcon#end of sib2, iclass 11, count 0 2006.239.07:36:31.34#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:36:31.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:36:31.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:36:31.34#ibcon#*before write, iclass 11, count 0 2006.239.07:36:31.34#ibcon#enter sib2, iclass 11, count 0 2006.239.07:36:31.34#ibcon#flushed, iclass 11, count 0 2006.239.07:36:31.34#ibcon#about to write, iclass 11, count 0 2006.239.07:36:31.34#ibcon#wrote, iclass 11, count 0 2006.239.07:36:31.34#ibcon#about to read 3, iclass 11, count 0 2006.239.07:36:31.38#ibcon#read 3, iclass 11, count 0 2006.239.07:36:31.38#ibcon#about to read 4, iclass 11, count 0 2006.239.07:36:31.38#ibcon#read 4, iclass 11, count 0 2006.239.07:36:31.38#ibcon#about to read 5, iclass 11, count 0 2006.239.07:36:31.38#ibcon#read 5, iclass 11, count 0 2006.239.07:36:31.38#ibcon#about to read 6, iclass 11, count 0 2006.239.07:36:31.38#ibcon#read 6, iclass 11, count 0 2006.239.07:36:31.38#ibcon#end of sib2, iclass 11, count 0 2006.239.07:36:31.38#ibcon#*after write, iclass 11, count 0 2006.239.07:36:31.38#ibcon#*before return 0, iclass 11, count 0 2006.239.07:36:31.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:31.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:36:31.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:36:31.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:36:31.38$vc4f8/vb=6,4 2006.239.07:36:31.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.07:36:31.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.07:36:31.38#ibcon#ireg 11 cls_cnt 2 2006.239.07:36:31.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:31.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:31.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:31.44#ibcon#enter wrdev, iclass 13, count 2 2006.239.07:36:31.44#ibcon#first serial, iclass 13, count 2 2006.239.07:36:31.44#ibcon#enter sib2, iclass 13, count 2 2006.239.07:36:31.44#ibcon#flushed, iclass 13, count 2 2006.239.07:36:31.44#ibcon#about to write, iclass 13, count 2 2006.239.07:36:31.44#ibcon#wrote, iclass 13, count 2 2006.239.07:36:31.44#ibcon#about to read 3, iclass 13, count 2 2006.239.07:36:31.46#ibcon#read 3, iclass 13, count 2 2006.239.07:36:31.46#ibcon#about to read 4, iclass 13, count 2 2006.239.07:36:31.46#ibcon#read 4, iclass 13, count 2 2006.239.07:36:31.46#ibcon#about to read 5, iclass 13, count 2 2006.239.07:36:31.46#ibcon#read 5, iclass 13, count 2 2006.239.07:36:31.46#ibcon#about to read 6, iclass 13, count 2 2006.239.07:36:31.46#ibcon#read 6, iclass 13, count 2 2006.239.07:36:31.46#ibcon#end of sib2, iclass 13, count 2 2006.239.07:36:31.46#ibcon#*mode == 0, iclass 13, count 2 2006.239.07:36:31.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.07:36:31.46#ibcon#[27=AT06-04\r\n] 2006.239.07:36:31.46#ibcon#*before write, iclass 13, count 2 2006.239.07:36:31.46#ibcon#enter sib2, iclass 13, count 2 2006.239.07:36:31.46#ibcon#flushed, iclass 13, count 2 2006.239.07:36:31.46#ibcon#about to write, iclass 13, count 2 2006.239.07:36:31.46#ibcon#wrote, iclass 13, count 2 2006.239.07:36:31.46#ibcon#about to read 3, iclass 13, count 2 2006.239.07:36:31.49#ibcon#read 3, iclass 13, count 2 2006.239.07:36:31.49#ibcon#about to read 4, iclass 13, count 2 2006.239.07:36:31.49#ibcon#read 4, iclass 13, count 2 2006.239.07:36:31.49#ibcon#about to read 5, iclass 13, count 2 2006.239.07:36:31.49#ibcon#read 5, iclass 13, count 2 2006.239.07:36:31.49#ibcon#about to read 6, iclass 13, count 2 2006.239.07:36:31.49#ibcon#read 6, iclass 13, count 2 2006.239.07:36:31.49#ibcon#end of sib2, iclass 13, count 2 2006.239.07:36:31.49#ibcon#*after write, iclass 13, count 2 2006.239.07:36:31.49#ibcon#*before return 0, iclass 13, count 2 2006.239.07:36:31.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:31.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:36:31.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.07:36:31.49#ibcon#ireg 7 cls_cnt 0 2006.239.07:36:31.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:31.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:31.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:31.63#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:36:31.63#ibcon#first serial, iclass 13, count 0 2006.239.07:36:31.63#ibcon#enter sib2, iclass 13, count 0 2006.239.07:36:31.63#ibcon#flushed, iclass 13, count 0 2006.239.07:36:31.63#ibcon#about to write, iclass 13, count 0 2006.239.07:36:31.63#ibcon#wrote, iclass 13, count 0 2006.239.07:36:31.63#ibcon#about to read 3, iclass 13, count 0 2006.239.07:36:31.64#ibcon#read 3, iclass 13, count 0 2006.239.07:36:31.64#ibcon#about to read 4, iclass 13, count 0 2006.239.07:36:31.64#ibcon#read 4, iclass 13, count 0 2006.239.07:36:31.64#ibcon#about to read 5, iclass 13, count 0 2006.239.07:36:31.64#ibcon#read 5, iclass 13, count 0 2006.239.07:36:31.64#ibcon#about to read 6, iclass 13, count 0 2006.239.07:36:31.64#ibcon#read 6, iclass 13, count 0 2006.239.07:36:31.64#ibcon#end of sib2, iclass 13, count 0 2006.239.07:36:31.64#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:36:31.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:36:31.64#ibcon#[27=USB\r\n] 2006.239.07:36:31.64#ibcon#*before write, iclass 13, count 0 2006.239.07:36:31.64#ibcon#enter sib2, iclass 13, count 0 2006.239.07:36:31.64#ibcon#flushed, iclass 13, count 0 2006.239.07:36:31.64#ibcon#about to write, iclass 13, count 0 2006.239.07:36:31.64#ibcon#wrote, iclass 13, count 0 2006.239.07:36:31.64#ibcon#about to read 3, iclass 13, count 0 2006.239.07:36:31.67#ibcon#read 3, iclass 13, count 0 2006.239.07:36:31.67#ibcon#about to read 4, iclass 13, count 0 2006.239.07:36:31.67#ibcon#read 4, iclass 13, count 0 2006.239.07:36:31.67#ibcon#about to read 5, iclass 13, count 0 2006.239.07:36:31.67#ibcon#read 5, iclass 13, count 0 2006.239.07:36:31.67#ibcon#about to read 6, iclass 13, count 0 2006.239.07:36:31.67#ibcon#read 6, iclass 13, count 0 2006.239.07:36:31.67#ibcon#end of sib2, iclass 13, count 0 2006.239.07:36:31.67#ibcon#*after write, iclass 13, count 0 2006.239.07:36:31.67#ibcon#*before return 0, iclass 13, count 0 2006.239.07:36:31.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:31.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:36:31.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:36:31.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:36:31.67$vc4f8/vabw=wide 2006.239.07:36:31.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.07:36:31.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.07:36:31.67#ibcon#ireg 8 cls_cnt 0 2006.239.07:36:31.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:31.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:31.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:31.67#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:36:31.67#ibcon#first serial, iclass 15, count 0 2006.239.07:36:31.67#ibcon#enter sib2, iclass 15, count 0 2006.239.07:36:31.67#ibcon#flushed, iclass 15, count 0 2006.239.07:36:31.67#ibcon#about to write, iclass 15, count 0 2006.239.07:36:31.67#ibcon#wrote, iclass 15, count 0 2006.239.07:36:31.67#ibcon#about to read 3, iclass 15, count 0 2006.239.07:36:31.69#ibcon#read 3, iclass 15, count 0 2006.239.07:36:31.69#ibcon#about to read 4, iclass 15, count 0 2006.239.07:36:31.69#ibcon#read 4, iclass 15, count 0 2006.239.07:36:31.69#ibcon#about to read 5, iclass 15, count 0 2006.239.07:36:31.69#ibcon#read 5, iclass 15, count 0 2006.239.07:36:31.69#ibcon#about to read 6, iclass 15, count 0 2006.239.07:36:31.69#ibcon#read 6, iclass 15, count 0 2006.239.07:36:31.69#ibcon#end of sib2, iclass 15, count 0 2006.239.07:36:31.69#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:36:31.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:36:31.69#ibcon#[25=BW32\r\n] 2006.239.07:36:31.69#ibcon#*before write, iclass 15, count 0 2006.239.07:36:31.69#ibcon#enter sib2, iclass 15, count 0 2006.239.07:36:31.69#ibcon#flushed, iclass 15, count 0 2006.239.07:36:31.69#ibcon#about to write, iclass 15, count 0 2006.239.07:36:31.69#ibcon#wrote, iclass 15, count 0 2006.239.07:36:31.69#ibcon#about to read 3, iclass 15, count 0 2006.239.07:36:31.72#ibcon#read 3, iclass 15, count 0 2006.239.07:36:31.72#ibcon#about to read 4, iclass 15, count 0 2006.239.07:36:31.72#ibcon#read 4, iclass 15, count 0 2006.239.07:36:31.72#ibcon#about to read 5, iclass 15, count 0 2006.239.07:36:31.72#ibcon#read 5, iclass 15, count 0 2006.239.07:36:31.72#ibcon#about to read 6, iclass 15, count 0 2006.239.07:36:31.72#ibcon#read 6, iclass 15, count 0 2006.239.07:36:31.72#ibcon#end of sib2, iclass 15, count 0 2006.239.07:36:31.72#ibcon#*after write, iclass 15, count 0 2006.239.07:36:31.72#ibcon#*before return 0, iclass 15, count 0 2006.239.07:36:31.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:31.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:36:31.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:36:31.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:36:31.72$vc4f8/vbbw=wide 2006.239.07:36:31.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.07:36:31.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.07:36:31.72#ibcon#ireg 8 cls_cnt 0 2006.239.07:36:31.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:36:31.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:36:31.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:36:31.79#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:36:31.79#ibcon#first serial, iclass 17, count 0 2006.239.07:36:31.79#ibcon#enter sib2, iclass 17, count 0 2006.239.07:36:31.79#ibcon#flushed, iclass 17, count 0 2006.239.07:36:31.79#ibcon#about to write, iclass 17, count 0 2006.239.07:36:31.79#ibcon#wrote, iclass 17, count 0 2006.239.07:36:31.79#ibcon#about to read 3, iclass 17, count 0 2006.239.07:36:31.81#ibcon#read 3, iclass 17, count 0 2006.239.07:36:31.81#ibcon#about to read 4, iclass 17, count 0 2006.239.07:36:31.81#ibcon#read 4, iclass 17, count 0 2006.239.07:36:31.81#ibcon#about to read 5, iclass 17, count 0 2006.239.07:36:31.81#ibcon#read 5, iclass 17, count 0 2006.239.07:36:31.81#ibcon#about to read 6, iclass 17, count 0 2006.239.07:36:31.81#ibcon#read 6, iclass 17, count 0 2006.239.07:36:31.81#ibcon#end of sib2, iclass 17, count 0 2006.239.07:36:31.81#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:36:31.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:36:31.81#ibcon#[27=BW32\r\n] 2006.239.07:36:31.81#ibcon#*before write, iclass 17, count 0 2006.239.07:36:31.81#ibcon#enter sib2, iclass 17, count 0 2006.239.07:36:31.81#ibcon#flushed, iclass 17, count 0 2006.239.07:36:31.81#ibcon#about to write, iclass 17, count 0 2006.239.07:36:31.81#ibcon#wrote, iclass 17, count 0 2006.239.07:36:31.81#ibcon#about to read 3, iclass 17, count 0 2006.239.07:36:31.84#ibcon#read 3, iclass 17, count 0 2006.239.07:36:31.84#ibcon#about to read 4, iclass 17, count 0 2006.239.07:36:31.84#ibcon#read 4, iclass 17, count 0 2006.239.07:36:31.84#ibcon#about to read 5, iclass 17, count 0 2006.239.07:36:31.84#ibcon#read 5, iclass 17, count 0 2006.239.07:36:31.84#ibcon#about to read 6, iclass 17, count 0 2006.239.07:36:31.84#ibcon#read 6, iclass 17, count 0 2006.239.07:36:31.84#ibcon#end of sib2, iclass 17, count 0 2006.239.07:36:31.84#ibcon#*after write, iclass 17, count 0 2006.239.07:36:31.84#ibcon#*before return 0, iclass 17, count 0 2006.239.07:36:31.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:36:31.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:36:31.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:36:31.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:36:31.84$4f8m12a/ifd4f 2006.239.07:36:31.84$ifd4f/lo= 2006.239.07:36:31.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:36:31.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:36:31.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:36:31.85$ifd4f/patch= 2006.239.07:36:31.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:36:31.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:36:31.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:36:31.85$4f8m12a/"form=m,16.000,1:2 2006.239.07:36:31.85$4f8m12a/"tpicd 2006.239.07:36:31.85$4f8m12a/echo=off 2006.239.07:36:31.85$4f8m12a/xlog=off 2006.239.07:36:31.85:!2006.239.07:37:00 2006.239.07:36:41.14#trakl#Source acquired 2006.239.07:36:43.14#flagr#flagr/antenna,acquired 2006.239.07:37:00.01:preob 2006.239.07:37:01.14/onsource/TRACKING 2006.239.07:37:01.14:!2006.239.07:37:10 2006.239.07:37:10.00:data_valid=on 2006.239.07:37:10.00:midob 2006.239.07:37:10.14/onsource/TRACKING 2006.239.07:37:10.14/wx/25.37,1011.5,81 2006.239.07:37:10.29/cable/+6.4154E-03 2006.239.07:37:11.38/va/01,08,usb,yes,31,32 2006.239.07:37:11.38/va/02,07,usb,yes,31,32 2006.239.07:37:11.38/va/03,07,usb,yes,29,29 2006.239.07:37:11.38/va/04,07,usb,yes,32,35 2006.239.07:37:11.38/va/05,08,usb,yes,30,31 2006.239.07:37:11.38/va/06,07,usb,yes,32,32 2006.239.07:37:11.38/va/07,07,usb,yes,32,32 2006.239.07:37:11.38/va/08,07,usb,yes,35,34 2006.239.07:37:11.61/valo/01,532.99,yes,locked 2006.239.07:37:11.61/valo/02,572.99,yes,locked 2006.239.07:37:11.61/valo/03,672.99,yes,locked 2006.239.07:37:11.61/valo/04,832.99,yes,locked 2006.239.07:37:11.61/valo/05,652.99,yes,locked 2006.239.07:37:11.61/valo/06,772.99,yes,locked 2006.239.07:37:11.61/valo/07,832.99,yes,locked 2006.239.07:37:11.61/valo/08,852.99,yes,locked 2006.239.07:37:12.70/vb/01,04,usb,yes,30,29 2006.239.07:37:12.70/vb/02,04,usb,yes,32,33 2006.239.07:37:12.70/vb/03,04,usb,yes,28,32 2006.239.07:37:12.70/vb/04,04,usb,yes,29,29 2006.239.07:37:12.70/vb/05,04,usb,yes,28,32 2006.239.07:37:12.70/vb/06,04,usb,yes,28,31 2006.239.07:37:12.70/vb/07,04,usb,yes,31,31 2006.239.07:37:12.70/vb/08,04,usb,yes,28,32 2006.239.07:37:12.93/vblo/01,632.99,yes,locked 2006.239.07:37:12.93/vblo/02,640.99,yes,locked 2006.239.07:37:12.93/vblo/03,656.99,yes,locked 2006.239.07:37:12.93/vblo/04,712.99,yes,locked 2006.239.07:37:12.93/vblo/05,744.99,yes,locked 2006.239.07:37:12.93/vblo/06,752.99,yes,locked 2006.239.07:37:12.93/vblo/07,734.99,yes,locked 2006.239.07:37:12.93/vblo/08,744.99,yes,locked 2006.239.07:37:13.08/vabw/8 2006.239.07:37:13.23/vbbw/8 2006.239.07:37:13.38/xfe/off,on,13.7 2006.239.07:37:13.77/ifatt/23,28,28,28 2006.239.07:37:14.07/fmout-gps/S +4.35E-07 2006.239.07:37:14.12:!2006.239.07:38:10 2006.239.07:38:10.01:data_valid=off 2006.239.07:38:10.02:postob 2006.239.07:38:10.10/cable/+6.4144E-03 2006.239.07:38:10.11/wx/25.37,1011.5,81 2006.239.07:38:10.18/fmout-gps/S +4.35E-07 2006.239.07:38:10.19:scan_name=239-0739,k06239,60 2006.239.07:38:10.19:source=oq208,140700.39,282714.7,2000.0,ccw 2006.239.07:38:12.14#flagr#flagr/antenna,new-source 2006.239.07:38:12.15:checkk5 2006.239.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:38:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:38:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:38:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:38:14.02/chk_obsdata//k5ts1/T2390737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:38:14.39/chk_obsdata//k5ts2/T2390737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:38:14.77/chk_obsdata//k5ts3/T2390737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:38:15.14/chk_obsdata//k5ts4/T2390737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:38:15.84/k5log//k5ts1_log_newline 2006.239.07:38:16.53/k5log//k5ts2_log_newline 2006.239.07:38:17.22/k5log//k5ts3_log_newline 2006.239.07:38:17.91/k5log//k5ts4_log_newline 2006.239.07:38:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:38:17.93:4f8m12a=1 2006.239.07:38:17.93$4f8m12a/echo=on 2006.239.07:38:17.93$4f8m12a/pcalon 2006.239.07:38:17.93$pcalon/"no phase cal control is implemented here 2006.239.07:38:17.93$4f8m12a/"tpicd=stop 2006.239.07:38:17.93$4f8m12a/vc4f8 2006.239.07:38:17.93$vc4f8/valo=1,532.99 2006.239.07:38:17.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:38:17.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:38:17.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:17.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:17.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:17.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:17.94#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:38:17.94#ibcon#first serial, iclass 24, count 0 2006.239.07:38:17.94#ibcon#enter sib2, iclass 24, count 0 2006.239.07:38:17.94#ibcon#flushed, iclass 24, count 0 2006.239.07:38:17.94#ibcon#about to write, iclass 24, count 0 2006.239.07:38:17.94#ibcon#wrote, iclass 24, count 0 2006.239.07:38:17.94#ibcon#about to read 3, iclass 24, count 0 2006.239.07:38:17.98#ibcon#read 3, iclass 24, count 0 2006.239.07:38:17.98#ibcon#about to read 4, iclass 24, count 0 2006.239.07:38:17.98#ibcon#read 4, iclass 24, count 0 2006.239.07:38:17.98#ibcon#about to read 5, iclass 24, count 0 2006.239.07:38:17.98#ibcon#read 5, iclass 24, count 0 2006.239.07:38:17.98#ibcon#about to read 6, iclass 24, count 0 2006.239.07:38:17.98#ibcon#read 6, iclass 24, count 0 2006.239.07:38:17.98#ibcon#end of sib2, iclass 24, count 0 2006.239.07:38:17.98#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:38:17.98#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:38:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:38:17.98#ibcon#*before write, iclass 24, count 0 2006.239.07:38:17.98#ibcon#enter sib2, iclass 24, count 0 2006.239.07:38:17.98#ibcon#flushed, iclass 24, count 0 2006.239.07:38:17.98#ibcon#about to write, iclass 24, count 0 2006.239.07:38:17.98#ibcon#wrote, iclass 24, count 0 2006.239.07:38:17.98#ibcon#about to read 3, iclass 24, count 0 2006.239.07:38:18.02#ibcon#read 3, iclass 24, count 0 2006.239.07:38:18.02#ibcon#about to read 4, iclass 24, count 0 2006.239.07:38:18.02#ibcon#read 4, iclass 24, count 0 2006.239.07:38:18.02#ibcon#about to read 5, iclass 24, count 0 2006.239.07:38:18.02#ibcon#read 5, iclass 24, count 0 2006.239.07:38:18.02#ibcon#about to read 6, iclass 24, count 0 2006.239.07:38:18.02#ibcon#read 6, iclass 24, count 0 2006.239.07:38:18.02#ibcon#end of sib2, iclass 24, count 0 2006.239.07:38:18.02#ibcon#*after write, iclass 24, count 0 2006.239.07:38:18.02#ibcon#*before return 0, iclass 24, count 0 2006.239.07:38:18.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:18.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:18.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:38:18.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:38:18.02$vc4f8/va=1,8 2006.239.07:38:18.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.07:38:18.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.07:38:18.02#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:18.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:18.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:18.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:18.02#ibcon#enter wrdev, iclass 26, count 2 2006.239.07:38:18.02#ibcon#first serial, iclass 26, count 2 2006.239.07:38:18.02#ibcon#enter sib2, iclass 26, count 2 2006.239.07:38:18.02#ibcon#flushed, iclass 26, count 2 2006.239.07:38:18.02#ibcon#about to write, iclass 26, count 2 2006.239.07:38:18.02#ibcon#wrote, iclass 26, count 2 2006.239.07:38:18.02#ibcon#about to read 3, iclass 26, count 2 2006.239.07:38:18.04#ibcon#read 3, iclass 26, count 2 2006.239.07:38:18.04#ibcon#about to read 4, iclass 26, count 2 2006.239.07:38:18.04#ibcon#read 4, iclass 26, count 2 2006.239.07:38:18.04#ibcon#about to read 5, iclass 26, count 2 2006.239.07:38:18.04#ibcon#read 5, iclass 26, count 2 2006.239.07:38:18.04#ibcon#about to read 6, iclass 26, count 2 2006.239.07:38:18.04#ibcon#read 6, iclass 26, count 2 2006.239.07:38:18.04#ibcon#end of sib2, iclass 26, count 2 2006.239.07:38:18.04#ibcon#*mode == 0, iclass 26, count 2 2006.239.07:38:18.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.07:38:18.04#ibcon#[25=AT01-08\r\n] 2006.239.07:38:18.04#ibcon#*before write, iclass 26, count 2 2006.239.07:38:18.04#ibcon#enter sib2, iclass 26, count 2 2006.239.07:38:18.04#ibcon#flushed, iclass 26, count 2 2006.239.07:38:18.04#ibcon#about to write, iclass 26, count 2 2006.239.07:38:18.04#ibcon#wrote, iclass 26, count 2 2006.239.07:38:18.04#ibcon#about to read 3, iclass 26, count 2 2006.239.07:38:18.07#ibcon#read 3, iclass 26, count 2 2006.239.07:38:18.07#ibcon#about to read 4, iclass 26, count 2 2006.239.07:38:18.07#ibcon#read 4, iclass 26, count 2 2006.239.07:38:18.07#ibcon#about to read 5, iclass 26, count 2 2006.239.07:38:18.07#ibcon#read 5, iclass 26, count 2 2006.239.07:38:18.07#ibcon#about to read 6, iclass 26, count 2 2006.239.07:38:18.07#ibcon#read 6, iclass 26, count 2 2006.239.07:38:18.07#ibcon#end of sib2, iclass 26, count 2 2006.239.07:38:18.07#ibcon#*after write, iclass 26, count 2 2006.239.07:38:18.07#ibcon#*before return 0, iclass 26, count 2 2006.239.07:38:18.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:18.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:18.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.07:38:18.07#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:18.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:18.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:18.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:18.19#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:38:18.19#ibcon#first serial, iclass 26, count 0 2006.239.07:38:18.19#ibcon#enter sib2, iclass 26, count 0 2006.239.07:38:18.19#ibcon#flushed, iclass 26, count 0 2006.239.07:38:18.19#ibcon#about to write, iclass 26, count 0 2006.239.07:38:18.19#ibcon#wrote, iclass 26, count 0 2006.239.07:38:18.19#ibcon#about to read 3, iclass 26, count 0 2006.239.07:38:18.21#ibcon#read 3, iclass 26, count 0 2006.239.07:38:18.21#ibcon#about to read 4, iclass 26, count 0 2006.239.07:38:18.21#ibcon#read 4, iclass 26, count 0 2006.239.07:38:18.21#ibcon#about to read 5, iclass 26, count 0 2006.239.07:38:18.21#ibcon#read 5, iclass 26, count 0 2006.239.07:38:18.21#ibcon#about to read 6, iclass 26, count 0 2006.239.07:38:18.21#ibcon#read 6, iclass 26, count 0 2006.239.07:38:18.21#ibcon#end of sib2, iclass 26, count 0 2006.239.07:38:18.21#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:38:18.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:38:18.21#ibcon#[25=USB\r\n] 2006.239.07:38:18.21#ibcon#*before write, iclass 26, count 0 2006.239.07:38:18.21#ibcon#enter sib2, iclass 26, count 0 2006.239.07:38:18.21#ibcon#flushed, iclass 26, count 0 2006.239.07:38:18.21#ibcon#about to write, iclass 26, count 0 2006.239.07:38:18.21#ibcon#wrote, iclass 26, count 0 2006.239.07:38:18.21#ibcon#about to read 3, iclass 26, count 0 2006.239.07:38:18.24#ibcon#read 3, iclass 26, count 0 2006.239.07:38:18.24#ibcon#about to read 4, iclass 26, count 0 2006.239.07:38:18.24#ibcon#read 4, iclass 26, count 0 2006.239.07:38:18.24#ibcon#about to read 5, iclass 26, count 0 2006.239.07:38:18.24#ibcon#read 5, iclass 26, count 0 2006.239.07:38:18.24#ibcon#about to read 6, iclass 26, count 0 2006.239.07:38:18.24#ibcon#read 6, iclass 26, count 0 2006.239.07:38:18.24#ibcon#end of sib2, iclass 26, count 0 2006.239.07:38:18.24#ibcon#*after write, iclass 26, count 0 2006.239.07:38:18.24#ibcon#*before return 0, iclass 26, count 0 2006.239.07:38:18.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:18.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:18.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:38:18.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:38:18.24$vc4f8/valo=2,572.99 2006.239.07:38:18.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.07:38:18.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.07:38:18.24#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:18.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:38:18.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:38:18.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:38:18.24#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:38:18.24#ibcon#first serial, iclass 28, count 0 2006.239.07:38:18.24#ibcon#enter sib2, iclass 28, count 0 2006.239.07:38:18.24#ibcon#flushed, iclass 28, count 0 2006.239.07:38:18.24#ibcon#about to write, iclass 28, count 0 2006.239.07:38:18.24#ibcon#wrote, iclass 28, count 0 2006.239.07:38:18.24#ibcon#about to read 3, iclass 28, count 0 2006.239.07:38:18.26#ibcon#read 3, iclass 28, count 0 2006.239.07:38:18.26#ibcon#about to read 4, iclass 28, count 0 2006.239.07:38:18.26#ibcon#read 4, iclass 28, count 0 2006.239.07:38:18.26#ibcon#about to read 5, iclass 28, count 0 2006.239.07:38:18.26#ibcon#read 5, iclass 28, count 0 2006.239.07:38:18.26#ibcon#about to read 6, iclass 28, count 0 2006.239.07:38:18.26#ibcon#read 6, iclass 28, count 0 2006.239.07:38:18.26#ibcon#end of sib2, iclass 28, count 0 2006.239.07:38:18.26#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:38:18.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:38:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:38:18.26#ibcon#*before write, iclass 28, count 0 2006.239.07:38:18.26#ibcon#enter sib2, iclass 28, count 0 2006.239.07:38:18.26#ibcon#flushed, iclass 28, count 0 2006.239.07:38:18.26#ibcon#about to write, iclass 28, count 0 2006.239.07:38:18.26#ibcon#wrote, iclass 28, count 0 2006.239.07:38:18.26#ibcon#about to read 3, iclass 28, count 0 2006.239.07:38:18.30#ibcon#read 3, iclass 28, count 0 2006.239.07:38:18.30#ibcon#about to read 4, iclass 28, count 0 2006.239.07:38:18.30#ibcon#read 4, iclass 28, count 0 2006.239.07:38:18.30#ibcon#about to read 5, iclass 28, count 0 2006.239.07:38:18.30#ibcon#read 5, iclass 28, count 0 2006.239.07:38:18.30#ibcon#about to read 6, iclass 28, count 0 2006.239.07:38:18.30#ibcon#read 6, iclass 28, count 0 2006.239.07:38:18.30#ibcon#end of sib2, iclass 28, count 0 2006.239.07:38:18.30#ibcon#*after write, iclass 28, count 0 2006.239.07:38:18.30#ibcon#*before return 0, iclass 28, count 0 2006.239.07:38:18.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:38:18.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:38:18.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:38:18.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:38:18.30$vc4f8/va=2,7 2006.239.07:38:18.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.07:38:18.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.07:38:18.30#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:18.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:38:18.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:38:18.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:38:18.36#ibcon#enter wrdev, iclass 30, count 2 2006.239.07:38:18.36#ibcon#first serial, iclass 30, count 2 2006.239.07:38:18.36#ibcon#enter sib2, iclass 30, count 2 2006.239.07:38:18.36#ibcon#flushed, iclass 30, count 2 2006.239.07:38:18.36#ibcon#about to write, iclass 30, count 2 2006.239.07:38:18.36#ibcon#wrote, iclass 30, count 2 2006.239.07:38:18.36#ibcon#about to read 3, iclass 30, count 2 2006.239.07:38:18.38#ibcon#read 3, iclass 30, count 2 2006.239.07:38:18.38#ibcon#about to read 4, iclass 30, count 2 2006.239.07:38:18.38#ibcon#read 4, iclass 30, count 2 2006.239.07:38:18.38#ibcon#about to read 5, iclass 30, count 2 2006.239.07:38:18.38#ibcon#read 5, iclass 30, count 2 2006.239.07:38:18.38#ibcon#about to read 6, iclass 30, count 2 2006.239.07:38:18.38#ibcon#read 6, iclass 30, count 2 2006.239.07:38:18.38#ibcon#end of sib2, iclass 30, count 2 2006.239.07:38:18.38#ibcon#*mode == 0, iclass 30, count 2 2006.239.07:38:18.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.07:38:18.38#ibcon#[25=AT02-07\r\n] 2006.239.07:38:18.38#ibcon#*before write, iclass 30, count 2 2006.239.07:38:18.38#ibcon#enter sib2, iclass 30, count 2 2006.239.07:38:18.38#ibcon#flushed, iclass 30, count 2 2006.239.07:38:18.38#ibcon#about to write, iclass 30, count 2 2006.239.07:38:18.38#ibcon#wrote, iclass 30, count 2 2006.239.07:38:18.38#ibcon#about to read 3, iclass 30, count 2 2006.239.07:38:18.41#ibcon#read 3, iclass 30, count 2 2006.239.07:38:18.41#ibcon#about to read 4, iclass 30, count 2 2006.239.07:38:18.41#ibcon#read 4, iclass 30, count 2 2006.239.07:38:18.41#ibcon#about to read 5, iclass 30, count 2 2006.239.07:38:18.41#ibcon#read 5, iclass 30, count 2 2006.239.07:38:18.41#ibcon#about to read 6, iclass 30, count 2 2006.239.07:38:18.41#ibcon#read 6, iclass 30, count 2 2006.239.07:38:18.41#ibcon#end of sib2, iclass 30, count 2 2006.239.07:38:18.41#ibcon#*after write, iclass 30, count 2 2006.239.07:38:18.41#ibcon#*before return 0, iclass 30, count 2 2006.239.07:38:18.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:38:18.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:38:18.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.07:38:18.41#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:18.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:38:18.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:38:18.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:38:18.53#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:38:18.53#ibcon#first serial, iclass 30, count 0 2006.239.07:38:18.53#ibcon#enter sib2, iclass 30, count 0 2006.239.07:38:18.53#ibcon#flushed, iclass 30, count 0 2006.239.07:38:18.53#ibcon#about to write, iclass 30, count 0 2006.239.07:38:18.53#ibcon#wrote, iclass 30, count 0 2006.239.07:38:18.53#ibcon#about to read 3, iclass 30, count 0 2006.239.07:38:18.55#ibcon#read 3, iclass 30, count 0 2006.239.07:38:18.55#ibcon#about to read 4, iclass 30, count 0 2006.239.07:38:18.55#ibcon#read 4, iclass 30, count 0 2006.239.07:38:18.55#ibcon#about to read 5, iclass 30, count 0 2006.239.07:38:18.55#ibcon#read 5, iclass 30, count 0 2006.239.07:38:18.55#ibcon#about to read 6, iclass 30, count 0 2006.239.07:38:18.55#ibcon#read 6, iclass 30, count 0 2006.239.07:38:18.55#ibcon#end of sib2, iclass 30, count 0 2006.239.07:38:18.55#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:38:18.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:38:18.55#ibcon#[25=USB\r\n] 2006.239.07:38:18.55#ibcon#*before write, iclass 30, count 0 2006.239.07:38:18.55#ibcon#enter sib2, iclass 30, count 0 2006.239.07:38:18.55#ibcon#flushed, iclass 30, count 0 2006.239.07:38:18.55#ibcon#about to write, iclass 30, count 0 2006.239.07:38:18.55#ibcon#wrote, iclass 30, count 0 2006.239.07:38:18.55#ibcon#about to read 3, iclass 30, count 0 2006.239.07:38:18.58#ibcon#read 3, iclass 30, count 0 2006.239.07:38:18.58#ibcon#about to read 4, iclass 30, count 0 2006.239.07:38:18.58#ibcon#read 4, iclass 30, count 0 2006.239.07:38:18.58#ibcon#about to read 5, iclass 30, count 0 2006.239.07:38:18.58#ibcon#read 5, iclass 30, count 0 2006.239.07:38:18.58#ibcon#about to read 6, iclass 30, count 0 2006.239.07:38:18.58#ibcon#read 6, iclass 30, count 0 2006.239.07:38:18.58#ibcon#end of sib2, iclass 30, count 0 2006.239.07:38:18.58#ibcon#*after write, iclass 30, count 0 2006.239.07:38:18.58#ibcon#*before return 0, iclass 30, count 0 2006.239.07:38:18.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:38:18.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:38:18.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:38:18.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:38:18.58$vc4f8/valo=3,672.99 2006.239.07:38:18.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.07:38:18.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.07:38:18.58#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:18.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:38:18.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:38:18.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:38:18.58#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:38:18.58#ibcon#first serial, iclass 32, count 0 2006.239.07:38:18.58#ibcon#enter sib2, iclass 32, count 0 2006.239.07:38:18.58#ibcon#flushed, iclass 32, count 0 2006.239.07:38:18.58#ibcon#about to write, iclass 32, count 0 2006.239.07:38:18.58#ibcon#wrote, iclass 32, count 0 2006.239.07:38:18.58#ibcon#about to read 3, iclass 32, count 0 2006.239.07:38:18.60#ibcon#read 3, iclass 32, count 0 2006.239.07:38:18.60#ibcon#about to read 4, iclass 32, count 0 2006.239.07:38:18.60#ibcon#read 4, iclass 32, count 0 2006.239.07:38:18.60#ibcon#about to read 5, iclass 32, count 0 2006.239.07:38:18.60#ibcon#read 5, iclass 32, count 0 2006.239.07:38:18.60#ibcon#about to read 6, iclass 32, count 0 2006.239.07:38:18.60#ibcon#read 6, iclass 32, count 0 2006.239.07:38:18.60#ibcon#end of sib2, iclass 32, count 0 2006.239.07:38:18.60#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:38:18.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:38:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:38:18.60#ibcon#*before write, iclass 32, count 0 2006.239.07:38:18.60#ibcon#enter sib2, iclass 32, count 0 2006.239.07:38:18.60#ibcon#flushed, iclass 32, count 0 2006.239.07:38:18.60#ibcon#about to write, iclass 32, count 0 2006.239.07:38:18.60#ibcon#wrote, iclass 32, count 0 2006.239.07:38:18.60#ibcon#about to read 3, iclass 32, count 0 2006.239.07:38:18.64#ibcon#read 3, iclass 32, count 0 2006.239.07:38:18.64#ibcon#about to read 4, iclass 32, count 0 2006.239.07:38:18.64#ibcon#read 4, iclass 32, count 0 2006.239.07:38:18.64#ibcon#about to read 5, iclass 32, count 0 2006.239.07:38:18.64#ibcon#read 5, iclass 32, count 0 2006.239.07:38:18.64#ibcon#about to read 6, iclass 32, count 0 2006.239.07:38:18.64#ibcon#read 6, iclass 32, count 0 2006.239.07:38:18.64#ibcon#end of sib2, iclass 32, count 0 2006.239.07:38:18.64#ibcon#*after write, iclass 32, count 0 2006.239.07:38:18.64#ibcon#*before return 0, iclass 32, count 0 2006.239.07:38:18.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:38:18.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:38:18.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:38:18.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:38:18.64$vc4f8/va=3,7 2006.239.07:38:18.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.07:38:18.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.07:38:18.64#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:18.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:38:18.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:38:18.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:38:18.70#ibcon#enter wrdev, iclass 34, count 2 2006.239.07:38:18.70#ibcon#first serial, iclass 34, count 2 2006.239.07:38:18.70#ibcon#enter sib2, iclass 34, count 2 2006.239.07:38:18.70#ibcon#flushed, iclass 34, count 2 2006.239.07:38:18.70#ibcon#about to write, iclass 34, count 2 2006.239.07:38:18.70#ibcon#wrote, iclass 34, count 2 2006.239.07:38:18.70#ibcon#about to read 3, iclass 34, count 2 2006.239.07:38:18.72#ibcon#read 3, iclass 34, count 2 2006.239.07:38:18.72#ibcon#about to read 4, iclass 34, count 2 2006.239.07:38:18.72#ibcon#read 4, iclass 34, count 2 2006.239.07:38:18.72#ibcon#about to read 5, iclass 34, count 2 2006.239.07:38:18.72#ibcon#read 5, iclass 34, count 2 2006.239.07:38:18.72#ibcon#about to read 6, iclass 34, count 2 2006.239.07:38:18.72#ibcon#read 6, iclass 34, count 2 2006.239.07:38:18.72#ibcon#end of sib2, iclass 34, count 2 2006.239.07:38:18.72#ibcon#*mode == 0, iclass 34, count 2 2006.239.07:38:18.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.07:38:18.72#ibcon#[25=AT03-07\r\n] 2006.239.07:38:18.72#ibcon#*before write, iclass 34, count 2 2006.239.07:38:18.72#ibcon#enter sib2, iclass 34, count 2 2006.239.07:38:18.72#ibcon#flushed, iclass 34, count 2 2006.239.07:38:18.72#ibcon#about to write, iclass 34, count 2 2006.239.07:38:18.72#ibcon#wrote, iclass 34, count 2 2006.239.07:38:18.72#ibcon#about to read 3, iclass 34, count 2 2006.239.07:38:18.76#ibcon#read 3, iclass 34, count 2 2006.239.07:38:18.76#ibcon#about to read 4, iclass 34, count 2 2006.239.07:38:18.76#ibcon#read 4, iclass 34, count 2 2006.239.07:38:18.76#ibcon#about to read 5, iclass 34, count 2 2006.239.07:38:18.76#ibcon#read 5, iclass 34, count 2 2006.239.07:38:18.76#ibcon#about to read 6, iclass 34, count 2 2006.239.07:38:18.76#ibcon#read 6, iclass 34, count 2 2006.239.07:38:18.76#ibcon#end of sib2, iclass 34, count 2 2006.239.07:38:18.76#ibcon#*after write, iclass 34, count 2 2006.239.07:38:18.76#ibcon#*before return 0, iclass 34, count 2 2006.239.07:38:18.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:38:18.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:38:18.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.07:38:18.76#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:18.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:38:18.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:38:18.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:38:18.87#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:38:18.87#ibcon#first serial, iclass 34, count 0 2006.239.07:38:18.87#ibcon#enter sib2, iclass 34, count 0 2006.239.07:38:18.87#ibcon#flushed, iclass 34, count 0 2006.239.07:38:18.87#ibcon#about to write, iclass 34, count 0 2006.239.07:38:18.87#ibcon#wrote, iclass 34, count 0 2006.239.07:38:18.87#ibcon#about to read 3, iclass 34, count 0 2006.239.07:38:18.89#ibcon#read 3, iclass 34, count 0 2006.239.07:38:18.89#ibcon#about to read 4, iclass 34, count 0 2006.239.07:38:18.89#ibcon#read 4, iclass 34, count 0 2006.239.07:38:18.89#ibcon#about to read 5, iclass 34, count 0 2006.239.07:38:18.89#ibcon#read 5, iclass 34, count 0 2006.239.07:38:18.89#ibcon#about to read 6, iclass 34, count 0 2006.239.07:38:18.89#ibcon#read 6, iclass 34, count 0 2006.239.07:38:18.89#ibcon#end of sib2, iclass 34, count 0 2006.239.07:38:18.89#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:38:18.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:38:18.89#ibcon#[25=USB\r\n] 2006.239.07:38:18.89#ibcon#*before write, iclass 34, count 0 2006.239.07:38:18.89#ibcon#enter sib2, iclass 34, count 0 2006.239.07:38:18.89#ibcon#flushed, iclass 34, count 0 2006.239.07:38:18.89#ibcon#about to write, iclass 34, count 0 2006.239.07:38:18.89#ibcon#wrote, iclass 34, count 0 2006.239.07:38:18.89#ibcon#about to read 3, iclass 34, count 0 2006.239.07:38:18.92#ibcon#read 3, iclass 34, count 0 2006.239.07:38:18.92#ibcon#about to read 4, iclass 34, count 0 2006.239.07:38:18.92#ibcon#read 4, iclass 34, count 0 2006.239.07:38:18.92#ibcon#about to read 5, iclass 34, count 0 2006.239.07:38:18.92#ibcon#read 5, iclass 34, count 0 2006.239.07:38:18.92#ibcon#about to read 6, iclass 34, count 0 2006.239.07:38:18.92#ibcon#read 6, iclass 34, count 0 2006.239.07:38:18.92#ibcon#end of sib2, iclass 34, count 0 2006.239.07:38:18.92#ibcon#*after write, iclass 34, count 0 2006.239.07:38:18.92#ibcon#*before return 0, iclass 34, count 0 2006.239.07:38:18.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:38:18.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:38:18.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:38:18.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:38:18.92$vc4f8/valo=4,832.99 2006.239.07:38:18.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.07:38:18.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.07:38:18.92#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:18.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:18.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:18.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:18.92#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:38:18.92#ibcon#first serial, iclass 36, count 0 2006.239.07:38:18.92#ibcon#enter sib2, iclass 36, count 0 2006.239.07:38:18.92#ibcon#flushed, iclass 36, count 0 2006.239.07:38:18.92#ibcon#about to write, iclass 36, count 0 2006.239.07:38:18.92#ibcon#wrote, iclass 36, count 0 2006.239.07:38:18.92#ibcon#about to read 3, iclass 36, count 0 2006.239.07:38:18.94#ibcon#read 3, iclass 36, count 0 2006.239.07:38:18.94#ibcon#about to read 4, iclass 36, count 0 2006.239.07:38:18.94#ibcon#read 4, iclass 36, count 0 2006.239.07:38:18.94#ibcon#about to read 5, iclass 36, count 0 2006.239.07:38:18.94#ibcon#read 5, iclass 36, count 0 2006.239.07:38:18.94#ibcon#about to read 6, iclass 36, count 0 2006.239.07:38:18.94#ibcon#read 6, iclass 36, count 0 2006.239.07:38:18.94#ibcon#end of sib2, iclass 36, count 0 2006.239.07:38:18.94#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:38:18.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:38:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:38:18.94#ibcon#*before write, iclass 36, count 0 2006.239.07:38:18.94#ibcon#enter sib2, iclass 36, count 0 2006.239.07:38:18.94#ibcon#flushed, iclass 36, count 0 2006.239.07:38:18.94#ibcon#about to write, iclass 36, count 0 2006.239.07:38:18.94#ibcon#wrote, iclass 36, count 0 2006.239.07:38:18.94#ibcon#about to read 3, iclass 36, count 0 2006.239.07:38:18.98#ibcon#read 3, iclass 36, count 0 2006.239.07:38:18.98#ibcon#about to read 4, iclass 36, count 0 2006.239.07:38:18.98#ibcon#read 4, iclass 36, count 0 2006.239.07:38:18.98#ibcon#about to read 5, iclass 36, count 0 2006.239.07:38:18.98#ibcon#read 5, iclass 36, count 0 2006.239.07:38:18.98#ibcon#about to read 6, iclass 36, count 0 2006.239.07:38:18.98#ibcon#read 6, iclass 36, count 0 2006.239.07:38:18.98#ibcon#end of sib2, iclass 36, count 0 2006.239.07:38:18.98#ibcon#*after write, iclass 36, count 0 2006.239.07:38:18.98#ibcon#*before return 0, iclass 36, count 0 2006.239.07:38:18.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:18.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:18.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:38:18.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:38:18.98$vc4f8/va=4,7 2006.239.07:38:18.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.07:38:18.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.07:38:18.98#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:18.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:19.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:19.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:19.04#ibcon#enter wrdev, iclass 38, count 2 2006.239.07:38:19.04#ibcon#first serial, iclass 38, count 2 2006.239.07:38:19.04#ibcon#enter sib2, iclass 38, count 2 2006.239.07:38:19.04#ibcon#flushed, iclass 38, count 2 2006.239.07:38:19.04#ibcon#about to write, iclass 38, count 2 2006.239.07:38:19.04#ibcon#wrote, iclass 38, count 2 2006.239.07:38:19.04#ibcon#about to read 3, iclass 38, count 2 2006.239.07:38:19.06#ibcon#read 3, iclass 38, count 2 2006.239.07:38:19.06#ibcon#about to read 4, iclass 38, count 2 2006.239.07:38:19.06#ibcon#read 4, iclass 38, count 2 2006.239.07:38:19.06#ibcon#about to read 5, iclass 38, count 2 2006.239.07:38:19.06#ibcon#read 5, iclass 38, count 2 2006.239.07:38:19.06#ibcon#about to read 6, iclass 38, count 2 2006.239.07:38:19.06#ibcon#read 6, iclass 38, count 2 2006.239.07:38:19.06#ibcon#end of sib2, iclass 38, count 2 2006.239.07:38:19.06#ibcon#*mode == 0, iclass 38, count 2 2006.239.07:38:19.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.07:38:19.06#ibcon#[25=AT04-07\r\n] 2006.239.07:38:19.06#ibcon#*before write, iclass 38, count 2 2006.239.07:38:19.06#ibcon#enter sib2, iclass 38, count 2 2006.239.07:38:19.06#ibcon#flushed, iclass 38, count 2 2006.239.07:38:19.06#ibcon#about to write, iclass 38, count 2 2006.239.07:38:19.06#ibcon#wrote, iclass 38, count 2 2006.239.07:38:19.06#ibcon#about to read 3, iclass 38, count 2 2006.239.07:38:19.09#ibcon#read 3, iclass 38, count 2 2006.239.07:38:19.09#ibcon#about to read 4, iclass 38, count 2 2006.239.07:38:19.09#ibcon#read 4, iclass 38, count 2 2006.239.07:38:19.09#ibcon#about to read 5, iclass 38, count 2 2006.239.07:38:19.09#ibcon#read 5, iclass 38, count 2 2006.239.07:38:19.09#ibcon#about to read 6, iclass 38, count 2 2006.239.07:38:19.09#ibcon#read 6, iclass 38, count 2 2006.239.07:38:19.09#ibcon#end of sib2, iclass 38, count 2 2006.239.07:38:19.09#ibcon#*after write, iclass 38, count 2 2006.239.07:38:19.09#ibcon#*before return 0, iclass 38, count 2 2006.239.07:38:19.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:19.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:19.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.07:38:19.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:19.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:19.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:19.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:19.21#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:38:19.21#ibcon#first serial, iclass 38, count 0 2006.239.07:38:19.21#ibcon#enter sib2, iclass 38, count 0 2006.239.07:38:19.21#ibcon#flushed, iclass 38, count 0 2006.239.07:38:19.21#ibcon#about to write, iclass 38, count 0 2006.239.07:38:19.21#ibcon#wrote, iclass 38, count 0 2006.239.07:38:19.21#ibcon#about to read 3, iclass 38, count 0 2006.239.07:38:19.23#ibcon#read 3, iclass 38, count 0 2006.239.07:38:19.23#ibcon#about to read 4, iclass 38, count 0 2006.239.07:38:19.23#ibcon#read 4, iclass 38, count 0 2006.239.07:38:19.23#ibcon#about to read 5, iclass 38, count 0 2006.239.07:38:19.23#ibcon#read 5, iclass 38, count 0 2006.239.07:38:19.23#ibcon#about to read 6, iclass 38, count 0 2006.239.07:38:19.23#ibcon#read 6, iclass 38, count 0 2006.239.07:38:19.23#ibcon#end of sib2, iclass 38, count 0 2006.239.07:38:19.23#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:38:19.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:38:19.23#ibcon#[25=USB\r\n] 2006.239.07:38:19.23#ibcon#*before write, iclass 38, count 0 2006.239.07:38:19.23#ibcon#enter sib2, iclass 38, count 0 2006.239.07:38:19.23#ibcon#flushed, iclass 38, count 0 2006.239.07:38:19.23#ibcon#about to write, iclass 38, count 0 2006.239.07:38:19.23#ibcon#wrote, iclass 38, count 0 2006.239.07:38:19.23#ibcon#about to read 3, iclass 38, count 0 2006.239.07:38:19.26#ibcon#read 3, iclass 38, count 0 2006.239.07:38:19.26#ibcon#about to read 4, iclass 38, count 0 2006.239.07:38:19.26#ibcon#read 4, iclass 38, count 0 2006.239.07:38:19.26#ibcon#about to read 5, iclass 38, count 0 2006.239.07:38:19.26#ibcon#read 5, iclass 38, count 0 2006.239.07:38:19.26#ibcon#about to read 6, iclass 38, count 0 2006.239.07:38:19.26#ibcon#read 6, iclass 38, count 0 2006.239.07:38:19.26#ibcon#end of sib2, iclass 38, count 0 2006.239.07:38:19.26#ibcon#*after write, iclass 38, count 0 2006.239.07:38:19.26#ibcon#*before return 0, iclass 38, count 0 2006.239.07:38:19.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:19.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:19.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:38:19.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:38:19.26$vc4f8/valo=5,652.99 2006.239.07:38:19.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:38:19.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:38:19.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:19.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:19.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:19.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:19.26#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:38:19.26#ibcon#first serial, iclass 40, count 0 2006.239.07:38:19.26#ibcon#enter sib2, iclass 40, count 0 2006.239.07:38:19.26#ibcon#flushed, iclass 40, count 0 2006.239.07:38:19.26#ibcon#about to write, iclass 40, count 0 2006.239.07:38:19.26#ibcon#wrote, iclass 40, count 0 2006.239.07:38:19.26#ibcon#about to read 3, iclass 40, count 0 2006.239.07:38:19.28#ibcon#read 3, iclass 40, count 0 2006.239.07:38:19.28#ibcon#about to read 4, iclass 40, count 0 2006.239.07:38:19.28#ibcon#read 4, iclass 40, count 0 2006.239.07:38:19.28#ibcon#about to read 5, iclass 40, count 0 2006.239.07:38:19.28#ibcon#read 5, iclass 40, count 0 2006.239.07:38:19.28#ibcon#about to read 6, iclass 40, count 0 2006.239.07:38:19.28#ibcon#read 6, iclass 40, count 0 2006.239.07:38:19.28#ibcon#end of sib2, iclass 40, count 0 2006.239.07:38:19.28#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:38:19.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:38:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:38:19.28#ibcon#*before write, iclass 40, count 0 2006.239.07:38:19.28#ibcon#enter sib2, iclass 40, count 0 2006.239.07:38:19.28#ibcon#flushed, iclass 40, count 0 2006.239.07:38:19.28#ibcon#about to write, iclass 40, count 0 2006.239.07:38:19.28#ibcon#wrote, iclass 40, count 0 2006.239.07:38:19.28#ibcon#about to read 3, iclass 40, count 0 2006.239.07:38:19.32#ibcon#read 3, iclass 40, count 0 2006.239.07:38:19.32#ibcon#about to read 4, iclass 40, count 0 2006.239.07:38:19.32#ibcon#read 4, iclass 40, count 0 2006.239.07:38:19.32#ibcon#about to read 5, iclass 40, count 0 2006.239.07:38:19.32#ibcon#read 5, iclass 40, count 0 2006.239.07:38:19.32#ibcon#about to read 6, iclass 40, count 0 2006.239.07:38:19.32#ibcon#read 6, iclass 40, count 0 2006.239.07:38:19.32#ibcon#end of sib2, iclass 40, count 0 2006.239.07:38:19.32#ibcon#*after write, iclass 40, count 0 2006.239.07:38:19.32#ibcon#*before return 0, iclass 40, count 0 2006.239.07:38:19.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:19.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:19.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:38:19.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:38:19.32$vc4f8/va=5,8 2006.239.07:38:19.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:38:19.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:38:19.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:19.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:19.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:19.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:19.38#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:38:19.38#ibcon#first serial, iclass 4, count 2 2006.239.07:38:19.38#ibcon#enter sib2, iclass 4, count 2 2006.239.07:38:19.38#ibcon#flushed, iclass 4, count 2 2006.239.07:38:19.38#ibcon#about to write, iclass 4, count 2 2006.239.07:38:19.38#ibcon#wrote, iclass 4, count 2 2006.239.07:38:19.38#ibcon#about to read 3, iclass 4, count 2 2006.239.07:38:19.40#ibcon#read 3, iclass 4, count 2 2006.239.07:38:19.40#ibcon#about to read 4, iclass 4, count 2 2006.239.07:38:19.40#ibcon#read 4, iclass 4, count 2 2006.239.07:38:19.40#ibcon#about to read 5, iclass 4, count 2 2006.239.07:38:19.40#ibcon#read 5, iclass 4, count 2 2006.239.07:38:19.40#ibcon#about to read 6, iclass 4, count 2 2006.239.07:38:19.40#ibcon#read 6, iclass 4, count 2 2006.239.07:38:19.40#ibcon#end of sib2, iclass 4, count 2 2006.239.07:38:19.40#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:38:19.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:38:19.40#ibcon#[25=AT05-08\r\n] 2006.239.07:38:19.40#ibcon#*before write, iclass 4, count 2 2006.239.07:38:19.40#ibcon#enter sib2, iclass 4, count 2 2006.239.07:38:19.40#ibcon#flushed, iclass 4, count 2 2006.239.07:38:19.40#ibcon#about to write, iclass 4, count 2 2006.239.07:38:19.40#ibcon#wrote, iclass 4, count 2 2006.239.07:38:19.40#ibcon#about to read 3, iclass 4, count 2 2006.239.07:38:19.43#ibcon#read 3, iclass 4, count 2 2006.239.07:38:19.43#ibcon#about to read 4, iclass 4, count 2 2006.239.07:38:19.43#ibcon#read 4, iclass 4, count 2 2006.239.07:38:19.43#ibcon#about to read 5, iclass 4, count 2 2006.239.07:38:19.43#ibcon#read 5, iclass 4, count 2 2006.239.07:38:19.43#ibcon#about to read 6, iclass 4, count 2 2006.239.07:38:19.43#ibcon#read 6, iclass 4, count 2 2006.239.07:38:19.43#ibcon#end of sib2, iclass 4, count 2 2006.239.07:38:19.43#ibcon#*after write, iclass 4, count 2 2006.239.07:38:19.43#ibcon#*before return 0, iclass 4, count 2 2006.239.07:38:19.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:19.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:19.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:38:19.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:19.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:19.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:19.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:19.55#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:38:19.55#ibcon#first serial, iclass 4, count 0 2006.239.07:38:19.55#ibcon#enter sib2, iclass 4, count 0 2006.239.07:38:19.55#ibcon#flushed, iclass 4, count 0 2006.239.07:38:19.55#ibcon#about to write, iclass 4, count 0 2006.239.07:38:19.55#ibcon#wrote, iclass 4, count 0 2006.239.07:38:19.55#ibcon#about to read 3, iclass 4, count 0 2006.239.07:38:19.57#ibcon#read 3, iclass 4, count 0 2006.239.07:38:19.57#ibcon#about to read 4, iclass 4, count 0 2006.239.07:38:19.57#ibcon#read 4, iclass 4, count 0 2006.239.07:38:19.57#ibcon#about to read 5, iclass 4, count 0 2006.239.07:38:19.57#ibcon#read 5, iclass 4, count 0 2006.239.07:38:19.57#ibcon#about to read 6, iclass 4, count 0 2006.239.07:38:19.57#ibcon#read 6, iclass 4, count 0 2006.239.07:38:19.57#ibcon#end of sib2, iclass 4, count 0 2006.239.07:38:19.57#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:38:19.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:38:19.57#ibcon#[25=USB\r\n] 2006.239.07:38:19.57#ibcon#*before write, iclass 4, count 0 2006.239.07:38:19.57#ibcon#enter sib2, iclass 4, count 0 2006.239.07:38:19.57#ibcon#flushed, iclass 4, count 0 2006.239.07:38:19.57#ibcon#about to write, iclass 4, count 0 2006.239.07:38:19.57#ibcon#wrote, iclass 4, count 0 2006.239.07:38:19.57#ibcon#about to read 3, iclass 4, count 0 2006.239.07:38:19.60#ibcon#read 3, iclass 4, count 0 2006.239.07:38:19.60#ibcon#about to read 4, iclass 4, count 0 2006.239.07:38:19.60#ibcon#read 4, iclass 4, count 0 2006.239.07:38:19.60#ibcon#about to read 5, iclass 4, count 0 2006.239.07:38:19.60#ibcon#read 5, iclass 4, count 0 2006.239.07:38:19.60#ibcon#about to read 6, iclass 4, count 0 2006.239.07:38:19.60#ibcon#read 6, iclass 4, count 0 2006.239.07:38:19.60#ibcon#end of sib2, iclass 4, count 0 2006.239.07:38:19.60#ibcon#*after write, iclass 4, count 0 2006.239.07:38:19.60#ibcon#*before return 0, iclass 4, count 0 2006.239.07:38:19.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:19.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:19.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:38:19.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:38:19.60$vc4f8/valo=6,772.99 2006.239.07:38:19.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:38:19.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:38:19.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:19.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:19.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:19.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:19.60#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:38:19.60#ibcon#first serial, iclass 6, count 0 2006.239.07:38:19.60#ibcon#enter sib2, iclass 6, count 0 2006.239.07:38:19.60#ibcon#flushed, iclass 6, count 0 2006.239.07:38:19.60#ibcon#about to write, iclass 6, count 0 2006.239.07:38:19.60#ibcon#wrote, iclass 6, count 0 2006.239.07:38:19.60#ibcon#about to read 3, iclass 6, count 0 2006.239.07:38:19.62#ibcon#read 3, iclass 6, count 0 2006.239.07:38:19.62#ibcon#about to read 4, iclass 6, count 0 2006.239.07:38:19.62#ibcon#read 4, iclass 6, count 0 2006.239.07:38:19.62#ibcon#about to read 5, iclass 6, count 0 2006.239.07:38:19.62#ibcon#read 5, iclass 6, count 0 2006.239.07:38:19.62#ibcon#about to read 6, iclass 6, count 0 2006.239.07:38:19.62#ibcon#read 6, iclass 6, count 0 2006.239.07:38:19.62#ibcon#end of sib2, iclass 6, count 0 2006.239.07:38:19.62#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:38:19.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:38:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:38:19.62#ibcon#*before write, iclass 6, count 0 2006.239.07:38:19.62#ibcon#enter sib2, iclass 6, count 0 2006.239.07:38:19.62#ibcon#flushed, iclass 6, count 0 2006.239.07:38:19.62#ibcon#about to write, iclass 6, count 0 2006.239.07:38:19.62#ibcon#wrote, iclass 6, count 0 2006.239.07:38:19.62#ibcon#about to read 3, iclass 6, count 0 2006.239.07:38:19.66#ibcon#read 3, iclass 6, count 0 2006.239.07:38:19.66#ibcon#about to read 4, iclass 6, count 0 2006.239.07:38:19.66#ibcon#read 4, iclass 6, count 0 2006.239.07:38:19.66#ibcon#about to read 5, iclass 6, count 0 2006.239.07:38:19.66#ibcon#read 5, iclass 6, count 0 2006.239.07:38:19.66#ibcon#about to read 6, iclass 6, count 0 2006.239.07:38:19.66#ibcon#read 6, iclass 6, count 0 2006.239.07:38:19.66#ibcon#end of sib2, iclass 6, count 0 2006.239.07:38:19.66#ibcon#*after write, iclass 6, count 0 2006.239.07:38:19.66#ibcon#*before return 0, iclass 6, count 0 2006.239.07:38:19.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:19.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:19.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:38:19.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:38:19.66$vc4f8/va=6,7 2006.239.07:38:19.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:38:19.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:38:19.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:19.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:19.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:19.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:19.72#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:38:19.72#ibcon#first serial, iclass 10, count 2 2006.239.07:38:19.72#ibcon#enter sib2, iclass 10, count 2 2006.239.07:38:19.72#ibcon#flushed, iclass 10, count 2 2006.239.07:38:19.72#ibcon#about to write, iclass 10, count 2 2006.239.07:38:19.72#ibcon#wrote, iclass 10, count 2 2006.239.07:38:19.72#ibcon#about to read 3, iclass 10, count 2 2006.239.07:38:19.74#ibcon#read 3, iclass 10, count 2 2006.239.07:38:19.74#ibcon#about to read 4, iclass 10, count 2 2006.239.07:38:19.74#ibcon#read 4, iclass 10, count 2 2006.239.07:38:19.74#ibcon#about to read 5, iclass 10, count 2 2006.239.07:38:19.74#ibcon#read 5, iclass 10, count 2 2006.239.07:38:19.74#ibcon#about to read 6, iclass 10, count 2 2006.239.07:38:19.74#ibcon#read 6, iclass 10, count 2 2006.239.07:38:19.74#ibcon#end of sib2, iclass 10, count 2 2006.239.07:38:19.74#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:38:19.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:38:19.74#ibcon#[25=AT06-07\r\n] 2006.239.07:38:19.74#ibcon#*before write, iclass 10, count 2 2006.239.07:38:19.74#ibcon#enter sib2, iclass 10, count 2 2006.239.07:38:19.74#ibcon#flushed, iclass 10, count 2 2006.239.07:38:19.74#ibcon#about to write, iclass 10, count 2 2006.239.07:38:19.74#ibcon#wrote, iclass 10, count 2 2006.239.07:38:19.74#ibcon#about to read 3, iclass 10, count 2 2006.239.07:38:19.77#ibcon#read 3, iclass 10, count 2 2006.239.07:38:19.77#ibcon#about to read 4, iclass 10, count 2 2006.239.07:38:19.77#ibcon#read 4, iclass 10, count 2 2006.239.07:38:19.77#ibcon#about to read 5, iclass 10, count 2 2006.239.07:38:19.77#ibcon#read 5, iclass 10, count 2 2006.239.07:38:19.77#ibcon#about to read 6, iclass 10, count 2 2006.239.07:38:19.77#ibcon#read 6, iclass 10, count 2 2006.239.07:38:19.77#ibcon#end of sib2, iclass 10, count 2 2006.239.07:38:19.77#ibcon#*after write, iclass 10, count 2 2006.239.07:38:19.77#ibcon#*before return 0, iclass 10, count 2 2006.239.07:38:19.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:19.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:19.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:38:19.77#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:19.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:19.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:19.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:19.89#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:38:19.89#ibcon#first serial, iclass 10, count 0 2006.239.07:38:19.89#ibcon#enter sib2, iclass 10, count 0 2006.239.07:38:19.89#ibcon#flushed, iclass 10, count 0 2006.239.07:38:19.89#ibcon#about to write, iclass 10, count 0 2006.239.07:38:19.89#ibcon#wrote, iclass 10, count 0 2006.239.07:38:19.89#ibcon#about to read 3, iclass 10, count 0 2006.239.07:38:19.91#ibcon#read 3, iclass 10, count 0 2006.239.07:38:19.91#ibcon#about to read 4, iclass 10, count 0 2006.239.07:38:19.91#ibcon#read 4, iclass 10, count 0 2006.239.07:38:19.91#ibcon#about to read 5, iclass 10, count 0 2006.239.07:38:19.91#ibcon#read 5, iclass 10, count 0 2006.239.07:38:19.91#ibcon#about to read 6, iclass 10, count 0 2006.239.07:38:19.91#ibcon#read 6, iclass 10, count 0 2006.239.07:38:19.91#ibcon#end of sib2, iclass 10, count 0 2006.239.07:38:19.91#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:38:19.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:38:19.91#ibcon#[25=USB\r\n] 2006.239.07:38:19.91#ibcon#*before write, iclass 10, count 0 2006.239.07:38:19.91#ibcon#enter sib2, iclass 10, count 0 2006.239.07:38:19.91#ibcon#flushed, iclass 10, count 0 2006.239.07:38:19.91#ibcon#about to write, iclass 10, count 0 2006.239.07:38:19.91#ibcon#wrote, iclass 10, count 0 2006.239.07:38:19.91#ibcon#about to read 3, iclass 10, count 0 2006.239.07:38:19.94#ibcon#read 3, iclass 10, count 0 2006.239.07:38:19.94#ibcon#about to read 4, iclass 10, count 0 2006.239.07:38:19.94#ibcon#read 4, iclass 10, count 0 2006.239.07:38:19.94#ibcon#about to read 5, iclass 10, count 0 2006.239.07:38:19.94#ibcon#read 5, iclass 10, count 0 2006.239.07:38:19.94#ibcon#about to read 6, iclass 10, count 0 2006.239.07:38:19.94#ibcon#read 6, iclass 10, count 0 2006.239.07:38:19.94#ibcon#end of sib2, iclass 10, count 0 2006.239.07:38:19.94#ibcon#*after write, iclass 10, count 0 2006.239.07:38:19.94#ibcon#*before return 0, iclass 10, count 0 2006.239.07:38:19.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:19.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:19.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:38:19.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:38:19.94$vc4f8/valo=7,832.99 2006.239.07:38:19.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:38:19.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:38:19.94#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:19.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:19.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:19.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:19.94#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:38:19.94#ibcon#first serial, iclass 12, count 0 2006.239.07:38:19.94#ibcon#enter sib2, iclass 12, count 0 2006.239.07:38:19.94#ibcon#flushed, iclass 12, count 0 2006.239.07:38:19.94#ibcon#about to write, iclass 12, count 0 2006.239.07:38:19.94#ibcon#wrote, iclass 12, count 0 2006.239.07:38:19.94#ibcon#about to read 3, iclass 12, count 0 2006.239.07:38:19.96#ibcon#read 3, iclass 12, count 0 2006.239.07:38:19.96#ibcon#about to read 4, iclass 12, count 0 2006.239.07:38:19.96#ibcon#read 4, iclass 12, count 0 2006.239.07:38:19.96#ibcon#about to read 5, iclass 12, count 0 2006.239.07:38:19.96#ibcon#read 5, iclass 12, count 0 2006.239.07:38:19.96#ibcon#about to read 6, iclass 12, count 0 2006.239.07:38:19.96#ibcon#read 6, iclass 12, count 0 2006.239.07:38:19.96#ibcon#end of sib2, iclass 12, count 0 2006.239.07:38:19.96#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:38:19.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:38:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:38:19.96#ibcon#*before write, iclass 12, count 0 2006.239.07:38:19.96#ibcon#enter sib2, iclass 12, count 0 2006.239.07:38:19.96#ibcon#flushed, iclass 12, count 0 2006.239.07:38:19.96#ibcon#about to write, iclass 12, count 0 2006.239.07:38:19.96#ibcon#wrote, iclass 12, count 0 2006.239.07:38:19.96#ibcon#about to read 3, iclass 12, count 0 2006.239.07:38:20.00#ibcon#read 3, iclass 12, count 0 2006.239.07:38:20.00#ibcon#about to read 4, iclass 12, count 0 2006.239.07:38:20.00#ibcon#read 4, iclass 12, count 0 2006.239.07:38:20.00#ibcon#about to read 5, iclass 12, count 0 2006.239.07:38:20.00#ibcon#read 5, iclass 12, count 0 2006.239.07:38:20.00#ibcon#about to read 6, iclass 12, count 0 2006.239.07:38:20.00#ibcon#read 6, iclass 12, count 0 2006.239.07:38:20.00#ibcon#end of sib2, iclass 12, count 0 2006.239.07:38:20.00#ibcon#*after write, iclass 12, count 0 2006.239.07:38:20.00#ibcon#*before return 0, iclass 12, count 0 2006.239.07:38:20.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:20.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:20.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:38:20.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:38:20.00$vc4f8/va=7,7 2006.239.07:38:20.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.07:38:20.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.07:38:20.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:20.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:38:20.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:38:20.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:38:20.06#ibcon#enter wrdev, iclass 14, count 2 2006.239.07:38:20.06#ibcon#first serial, iclass 14, count 2 2006.239.07:38:20.06#ibcon#enter sib2, iclass 14, count 2 2006.239.07:38:20.06#ibcon#flushed, iclass 14, count 2 2006.239.07:38:20.06#ibcon#about to write, iclass 14, count 2 2006.239.07:38:20.06#ibcon#wrote, iclass 14, count 2 2006.239.07:38:20.06#ibcon#about to read 3, iclass 14, count 2 2006.239.07:38:20.08#ibcon#read 3, iclass 14, count 2 2006.239.07:38:20.08#ibcon#about to read 4, iclass 14, count 2 2006.239.07:38:20.08#ibcon#read 4, iclass 14, count 2 2006.239.07:38:20.08#ibcon#about to read 5, iclass 14, count 2 2006.239.07:38:20.08#ibcon#read 5, iclass 14, count 2 2006.239.07:38:20.08#ibcon#about to read 6, iclass 14, count 2 2006.239.07:38:20.08#ibcon#read 6, iclass 14, count 2 2006.239.07:38:20.08#ibcon#end of sib2, iclass 14, count 2 2006.239.07:38:20.08#ibcon#*mode == 0, iclass 14, count 2 2006.239.07:38:20.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.07:38:20.08#ibcon#[25=AT07-07\r\n] 2006.239.07:38:20.08#ibcon#*before write, iclass 14, count 2 2006.239.07:38:20.08#ibcon#enter sib2, iclass 14, count 2 2006.239.07:38:20.08#ibcon#flushed, iclass 14, count 2 2006.239.07:38:20.08#ibcon#about to write, iclass 14, count 2 2006.239.07:38:20.08#ibcon#wrote, iclass 14, count 2 2006.239.07:38:20.08#ibcon#about to read 3, iclass 14, count 2 2006.239.07:38:20.11#ibcon#read 3, iclass 14, count 2 2006.239.07:38:20.11#ibcon#about to read 4, iclass 14, count 2 2006.239.07:38:20.11#ibcon#read 4, iclass 14, count 2 2006.239.07:38:20.11#ibcon#about to read 5, iclass 14, count 2 2006.239.07:38:20.11#ibcon#read 5, iclass 14, count 2 2006.239.07:38:20.11#ibcon#about to read 6, iclass 14, count 2 2006.239.07:38:20.11#ibcon#read 6, iclass 14, count 2 2006.239.07:38:20.11#ibcon#end of sib2, iclass 14, count 2 2006.239.07:38:20.11#ibcon#*after write, iclass 14, count 2 2006.239.07:38:20.11#ibcon#*before return 0, iclass 14, count 2 2006.239.07:38:20.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:38:20.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:38:20.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.07:38:20.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:20.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:38:20.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:38:20.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:38:20.23#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:38:20.23#ibcon#first serial, iclass 14, count 0 2006.239.07:38:20.23#ibcon#enter sib2, iclass 14, count 0 2006.239.07:38:20.23#ibcon#flushed, iclass 14, count 0 2006.239.07:38:20.23#ibcon#about to write, iclass 14, count 0 2006.239.07:38:20.23#ibcon#wrote, iclass 14, count 0 2006.239.07:38:20.23#ibcon#about to read 3, iclass 14, count 0 2006.239.07:38:20.25#ibcon#read 3, iclass 14, count 0 2006.239.07:38:20.25#ibcon#about to read 4, iclass 14, count 0 2006.239.07:38:20.25#ibcon#read 4, iclass 14, count 0 2006.239.07:38:20.25#ibcon#about to read 5, iclass 14, count 0 2006.239.07:38:20.25#ibcon#read 5, iclass 14, count 0 2006.239.07:38:20.25#ibcon#about to read 6, iclass 14, count 0 2006.239.07:38:20.25#ibcon#read 6, iclass 14, count 0 2006.239.07:38:20.25#ibcon#end of sib2, iclass 14, count 0 2006.239.07:38:20.25#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:38:20.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:38:20.25#ibcon#[25=USB\r\n] 2006.239.07:38:20.25#ibcon#*before write, iclass 14, count 0 2006.239.07:38:20.25#ibcon#enter sib2, iclass 14, count 0 2006.239.07:38:20.25#ibcon#flushed, iclass 14, count 0 2006.239.07:38:20.25#ibcon#about to write, iclass 14, count 0 2006.239.07:38:20.25#ibcon#wrote, iclass 14, count 0 2006.239.07:38:20.25#ibcon#about to read 3, iclass 14, count 0 2006.239.07:38:20.28#ibcon#read 3, iclass 14, count 0 2006.239.07:38:20.28#ibcon#about to read 4, iclass 14, count 0 2006.239.07:38:20.28#ibcon#read 4, iclass 14, count 0 2006.239.07:38:20.28#ibcon#about to read 5, iclass 14, count 0 2006.239.07:38:20.28#ibcon#read 5, iclass 14, count 0 2006.239.07:38:20.28#ibcon#about to read 6, iclass 14, count 0 2006.239.07:38:20.28#ibcon#read 6, iclass 14, count 0 2006.239.07:38:20.28#ibcon#end of sib2, iclass 14, count 0 2006.239.07:38:20.28#ibcon#*after write, iclass 14, count 0 2006.239.07:38:20.28#ibcon#*before return 0, iclass 14, count 0 2006.239.07:38:20.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:38:20.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:38:20.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:38:20.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:38:20.28$vc4f8/valo=8,852.99 2006.239.07:38:20.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:38:20.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:38:20.28#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:20.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:38:20.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:38:20.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:38:20.28#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:38:20.28#ibcon#first serial, iclass 16, count 0 2006.239.07:38:20.28#ibcon#enter sib2, iclass 16, count 0 2006.239.07:38:20.28#ibcon#flushed, iclass 16, count 0 2006.239.07:38:20.28#ibcon#about to write, iclass 16, count 0 2006.239.07:38:20.28#ibcon#wrote, iclass 16, count 0 2006.239.07:38:20.28#ibcon#about to read 3, iclass 16, count 0 2006.239.07:38:20.30#ibcon#read 3, iclass 16, count 0 2006.239.07:38:20.30#ibcon#about to read 4, iclass 16, count 0 2006.239.07:38:20.30#ibcon#read 4, iclass 16, count 0 2006.239.07:38:20.30#ibcon#about to read 5, iclass 16, count 0 2006.239.07:38:20.30#ibcon#read 5, iclass 16, count 0 2006.239.07:38:20.30#ibcon#about to read 6, iclass 16, count 0 2006.239.07:38:20.30#ibcon#read 6, iclass 16, count 0 2006.239.07:38:20.30#ibcon#end of sib2, iclass 16, count 0 2006.239.07:38:20.30#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:38:20.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:38:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:38:20.30#ibcon#*before write, iclass 16, count 0 2006.239.07:38:20.30#ibcon#enter sib2, iclass 16, count 0 2006.239.07:38:20.30#ibcon#flushed, iclass 16, count 0 2006.239.07:38:20.30#ibcon#about to write, iclass 16, count 0 2006.239.07:38:20.30#ibcon#wrote, iclass 16, count 0 2006.239.07:38:20.30#ibcon#about to read 3, iclass 16, count 0 2006.239.07:38:20.34#ibcon#read 3, iclass 16, count 0 2006.239.07:38:20.34#ibcon#about to read 4, iclass 16, count 0 2006.239.07:38:20.34#ibcon#read 4, iclass 16, count 0 2006.239.07:38:20.34#ibcon#about to read 5, iclass 16, count 0 2006.239.07:38:20.34#ibcon#read 5, iclass 16, count 0 2006.239.07:38:20.34#ibcon#about to read 6, iclass 16, count 0 2006.239.07:38:20.34#ibcon#read 6, iclass 16, count 0 2006.239.07:38:20.34#ibcon#end of sib2, iclass 16, count 0 2006.239.07:38:20.34#ibcon#*after write, iclass 16, count 0 2006.239.07:38:20.34#ibcon#*before return 0, iclass 16, count 0 2006.239.07:38:20.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:38:20.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:38:20.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:38:20.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:38:20.34$vc4f8/va=8,7 2006.239.07:38:20.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:38:20.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:38:20.34#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:20.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:38:20.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:38:20.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:38:20.40#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:38:20.40#ibcon#first serial, iclass 18, count 2 2006.239.07:38:20.40#ibcon#enter sib2, iclass 18, count 2 2006.239.07:38:20.40#ibcon#flushed, iclass 18, count 2 2006.239.07:38:20.40#ibcon#about to write, iclass 18, count 2 2006.239.07:38:20.40#ibcon#wrote, iclass 18, count 2 2006.239.07:38:20.40#ibcon#about to read 3, iclass 18, count 2 2006.239.07:38:20.42#ibcon#read 3, iclass 18, count 2 2006.239.07:38:20.42#ibcon#about to read 4, iclass 18, count 2 2006.239.07:38:20.42#ibcon#read 4, iclass 18, count 2 2006.239.07:38:20.42#ibcon#about to read 5, iclass 18, count 2 2006.239.07:38:20.42#ibcon#read 5, iclass 18, count 2 2006.239.07:38:20.42#ibcon#about to read 6, iclass 18, count 2 2006.239.07:38:20.42#ibcon#read 6, iclass 18, count 2 2006.239.07:38:20.42#ibcon#end of sib2, iclass 18, count 2 2006.239.07:38:20.42#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:38:20.42#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:38:20.42#ibcon#[25=AT08-07\r\n] 2006.239.07:38:20.42#ibcon#*before write, iclass 18, count 2 2006.239.07:38:20.42#ibcon#enter sib2, iclass 18, count 2 2006.239.07:38:20.42#ibcon#flushed, iclass 18, count 2 2006.239.07:38:20.42#ibcon#about to write, iclass 18, count 2 2006.239.07:38:20.42#ibcon#wrote, iclass 18, count 2 2006.239.07:38:20.42#ibcon#about to read 3, iclass 18, count 2 2006.239.07:38:20.45#ibcon#read 3, iclass 18, count 2 2006.239.07:38:20.45#ibcon#about to read 4, iclass 18, count 2 2006.239.07:38:20.45#ibcon#read 4, iclass 18, count 2 2006.239.07:38:20.45#ibcon#about to read 5, iclass 18, count 2 2006.239.07:38:20.45#ibcon#read 5, iclass 18, count 2 2006.239.07:38:20.45#ibcon#about to read 6, iclass 18, count 2 2006.239.07:38:20.45#ibcon#read 6, iclass 18, count 2 2006.239.07:38:20.45#ibcon#end of sib2, iclass 18, count 2 2006.239.07:38:20.45#ibcon#*after write, iclass 18, count 2 2006.239.07:38:20.45#ibcon#*before return 0, iclass 18, count 2 2006.239.07:38:20.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:38:20.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:38:20.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:38:20.45#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:20.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:38:20.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:38:20.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:38:20.57#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:38:20.57#ibcon#first serial, iclass 18, count 0 2006.239.07:38:20.57#ibcon#enter sib2, iclass 18, count 0 2006.239.07:38:20.57#ibcon#flushed, iclass 18, count 0 2006.239.07:38:20.57#ibcon#about to write, iclass 18, count 0 2006.239.07:38:20.57#ibcon#wrote, iclass 18, count 0 2006.239.07:38:20.57#ibcon#about to read 3, iclass 18, count 0 2006.239.07:38:20.59#ibcon#read 3, iclass 18, count 0 2006.239.07:38:20.59#ibcon#about to read 4, iclass 18, count 0 2006.239.07:38:20.59#ibcon#read 4, iclass 18, count 0 2006.239.07:38:20.59#ibcon#about to read 5, iclass 18, count 0 2006.239.07:38:20.59#ibcon#read 5, iclass 18, count 0 2006.239.07:38:20.59#ibcon#about to read 6, iclass 18, count 0 2006.239.07:38:20.59#ibcon#read 6, iclass 18, count 0 2006.239.07:38:20.59#ibcon#end of sib2, iclass 18, count 0 2006.239.07:38:20.59#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:38:20.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:38:20.59#ibcon#[25=USB\r\n] 2006.239.07:38:20.59#ibcon#*before write, iclass 18, count 0 2006.239.07:38:20.59#ibcon#enter sib2, iclass 18, count 0 2006.239.07:38:20.59#ibcon#flushed, iclass 18, count 0 2006.239.07:38:20.59#ibcon#about to write, iclass 18, count 0 2006.239.07:38:20.59#ibcon#wrote, iclass 18, count 0 2006.239.07:38:20.59#ibcon#about to read 3, iclass 18, count 0 2006.239.07:38:20.62#ibcon#read 3, iclass 18, count 0 2006.239.07:38:20.62#ibcon#about to read 4, iclass 18, count 0 2006.239.07:38:20.62#ibcon#read 4, iclass 18, count 0 2006.239.07:38:20.62#ibcon#about to read 5, iclass 18, count 0 2006.239.07:38:20.62#ibcon#read 5, iclass 18, count 0 2006.239.07:38:20.62#ibcon#about to read 6, iclass 18, count 0 2006.239.07:38:20.62#ibcon#read 6, iclass 18, count 0 2006.239.07:38:20.62#ibcon#end of sib2, iclass 18, count 0 2006.239.07:38:20.62#ibcon#*after write, iclass 18, count 0 2006.239.07:38:20.62#ibcon#*before return 0, iclass 18, count 0 2006.239.07:38:20.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:38:20.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:38:20.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:38:20.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:38:20.62$vc4f8/vblo=1,632.99 2006.239.07:38:20.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:38:20.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:38:20.62#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:20.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:38:20.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:38:20.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:38:20.62#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:38:20.62#ibcon#first serial, iclass 20, count 0 2006.239.07:38:20.62#ibcon#enter sib2, iclass 20, count 0 2006.239.07:38:20.62#ibcon#flushed, iclass 20, count 0 2006.239.07:38:20.62#ibcon#about to write, iclass 20, count 0 2006.239.07:38:20.62#ibcon#wrote, iclass 20, count 0 2006.239.07:38:20.62#ibcon#about to read 3, iclass 20, count 0 2006.239.07:38:20.64#ibcon#read 3, iclass 20, count 0 2006.239.07:38:20.64#ibcon#about to read 4, iclass 20, count 0 2006.239.07:38:20.64#ibcon#read 4, iclass 20, count 0 2006.239.07:38:20.64#ibcon#about to read 5, iclass 20, count 0 2006.239.07:38:20.64#ibcon#read 5, iclass 20, count 0 2006.239.07:38:20.64#ibcon#about to read 6, iclass 20, count 0 2006.239.07:38:20.64#ibcon#read 6, iclass 20, count 0 2006.239.07:38:20.64#ibcon#end of sib2, iclass 20, count 0 2006.239.07:38:20.64#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:38:20.64#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:38:20.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:38:20.64#ibcon#*before write, iclass 20, count 0 2006.239.07:38:20.64#ibcon#enter sib2, iclass 20, count 0 2006.239.07:38:20.64#ibcon#flushed, iclass 20, count 0 2006.239.07:38:20.64#ibcon#about to write, iclass 20, count 0 2006.239.07:38:20.64#ibcon#wrote, iclass 20, count 0 2006.239.07:38:20.64#ibcon#about to read 3, iclass 20, count 0 2006.239.07:38:20.68#ibcon#read 3, iclass 20, count 0 2006.239.07:38:20.68#ibcon#about to read 4, iclass 20, count 0 2006.239.07:38:20.68#ibcon#read 4, iclass 20, count 0 2006.239.07:38:20.68#ibcon#about to read 5, iclass 20, count 0 2006.239.07:38:20.68#ibcon#read 5, iclass 20, count 0 2006.239.07:38:20.68#ibcon#about to read 6, iclass 20, count 0 2006.239.07:38:20.68#ibcon#read 6, iclass 20, count 0 2006.239.07:38:20.68#ibcon#end of sib2, iclass 20, count 0 2006.239.07:38:20.68#ibcon#*after write, iclass 20, count 0 2006.239.07:38:20.68#ibcon#*before return 0, iclass 20, count 0 2006.239.07:38:20.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:38:20.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:38:20.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:38:20.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:38:20.68$vc4f8/vb=1,4 2006.239.07:38:20.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:38:20.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:38:20.68#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:20.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:38:20.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:38:20.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:38:20.68#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:38:20.68#ibcon#first serial, iclass 22, count 2 2006.239.07:38:20.68#ibcon#enter sib2, iclass 22, count 2 2006.239.07:38:20.68#ibcon#flushed, iclass 22, count 2 2006.239.07:38:20.68#ibcon#about to write, iclass 22, count 2 2006.239.07:38:20.68#ibcon#wrote, iclass 22, count 2 2006.239.07:38:20.68#ibcon#about to read 3, iclass 22, count 2 2006.239.07:38:20.70#ibcon#read 3, iclass 22, count 2 2006.239.07:38:20.70#ibcon#about to read 4, iclass 22, count 2 2006.239.07:38:20.70#ibcon#read 4, iclass 22, count 2 2006.239.07:38:20.70#ibcon#about to read 5, iclass 22, count 2 2006.239.07:38:20.70#ibcon#read 5, iclass 22, count 2 2006.239.07:38:20.70#ibcon#about to read 6, iclass 22, count 2 2006.239.07:38:20.70#ibcon#read 6, iclass 22, count 2 2006.239.07:38:20.70#ibcon#end of sib2, iclass 22, count 2 2006.239.07:38:20.70#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:38:20.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:38:20.70#ibcon#[27=AT01-04\r\n] 2006.239.07:38:20.70#ibcon#*before write, iclass 22, count 2 2006.239.07:38:20.70#ibcon#enter sib2, iclass 22, count 2 2006.239.07:38:20.70#ibcon#flushed, iclass 22, count 2 2006.239.07:38:20.70#ibcon#about to write, iclass 22, count 2 2006.239.07:38:20.70#ibcon#wrote, iclass 22, count 2 2006.239.07:38:20.70#ibcon#about to read 3, iclass 22, count 2 2006.239.07:38:20.73#ibcon#read 3, iclass 22, count 2 2006.239.07:38:20.73#ibcon#about to read 4, iclass 22, count 2 2006.239.07:38:20.73#ibcon#read 4, iclass 22, count 2 2006.239.07:38:20.73#ibcon#about to read 5, iclass 22, count 2 2006.239.07:38:20.73#ibcon#read 5, iclass 22, count 2 2006.239.07:38:20.73#ibcon#about to read 6, iclass 22, count 2 2006.239.07:38:20.73#ibcon#read 6, iclass 22, count 2 2006.239.07:38:20.73#ibcon#end of sib2, iclass 22, count 2 2006.239.07:38:20.73#ibcon#*after write, iclass 22, count 2 2006.239.07:38:20.73#ibcon#*before return 0, iclass 22, count 2 2006.239.07:38:20.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:38:20.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:38:20.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:38:20.73#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:20.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:38:20.85#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:38:20.85#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:38:20.85#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:38:20.85#ibcon#first serial, iclass 22, count 0 2006.239.07:38:20.85#ibcon#enter sib2, iclass 22, count 0 2006.239.07:38:20.85#ibcon#flushed, iclass 22, count 0 2006.239.07:38:20.85#ibcon#about to write, iclass 22, count 0 2006.239.07:38:20.85#ibcon#wrote, iclass 22, count 0 2006.239.07:38:20.85#ibcon#about to read 3, iclass 22, count 0 2006.239.07:38:20.87#ibcon#read 3, iclass 22, count 0 2006.239.07:38:20.87#ibcon#about to read 4, iclass 22, count 0 2006.239.07:38:20.87#ibcon#read 4, iclass 22, count 0 2006.239.07:38:20.87#ibcon#about to read 5, iclass 22, count 0 2006.239.07:38:20.87#ibcon#read 5, iclass 22, count 0 2006.239.07:38:20.87#ibcon#about to read 6, iclass 22, count 0 2006.239.07:38:20.87#ibcon#read 6, iclass 22, count 0 2006.239.07:38:20.87#ibcon#end of sib2, iclass 22, count 0 2006.239.07:38:20.87#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:38:20.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:38:20.87#ibcon#[27=USB\r\n] 2006.239.07:38:20.87#ibcon#*before write, iclass 22, count 0 2006.239.07:38:20.87#ibcon#enter sib2, iclass 22, count 0 2006.239.07:38:20.87#ibcon#flushed, iclass 22, count 0 2006.239.07:38:20.87#ibcon#about to write, iclass 22, count 0 2006.239.07:38:20.87#ibcon#wrote, iclass 22, count 0 2006.239.07:38:20.87#ibcon#about to read 3, iclass 22, count 0 2006.239.07:38:20.90#ibcon#read 3, iclass 22, count 0 2006.239.07:38:20.90#ibcon#about to read 4, iclass 22, count 0 2006.239.07:38:20.90#ibcon#read 4, iclass 22, count 0 2006.239.07:38:20.90#ibcon#about to read 5, iclass 22, count 0 2006.239.07:38:20.90#ibcon#read 5, iclass 22, count 0 2006.239.07:38:20.90#ibcon#about to read 6, iclass 22, count 0 2006.239.07:38:20.90#ibcon#read 6, iclass 22, count 0 2006.239.07:38:20.90#ibcon#end of sib2, iclass 22, count 0 2006.239.07:38:20.90#ibcon#*after write, iclass 22, count 0 2006.239.07:38:20.90#ibcon#*before return 0, iclass 22, count 0 2006.239.07:38:20.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:38:20.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:38:20.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:38:20.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:38:20.90$vc4f8/vblo=2,640.99 2006.239.07:38:20.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:38:20.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:38:20.90#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:20.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:20.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:20.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:20.90#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:38:20.90#ibcon#first serial, iclass 24, count 0 2006.239.07:38:20.90#ibcon#enter sib2, iclass 24, count 0 2006.239.07:38:20.90#ibcon#flushed, iclass 24, count 0 2006.239.07:38:20.90#ibcon#about to write, iclass 24, count 0 2006.239.07:38:20.90#ibcon#wrote, iclass 24, count 0 2006.239.07:38:20.90#ibcon#about to read 3, iclass 24, count 0 2006.239.07:38:20.92#ibcon#read 3, iclass 24, count 0 2006.239.07:38:20.92#ibcon#about to read 4, iclass 24, count 0 2006.239.07:38:20.92#ibcon#read 4, iclass 24, count 0 2006.239.07:38:20.92#ibcon#about to read 5, iclass 24, count 0 2006.239.07:38:20.92#ibcon#read 5, iclass 24, count 0 2006.239.07:38:20.92#ibcon#about to read 6, iclass 24, count 0 2006.239.07:38:20.92#ibcon#read 6, iclass 24, count 0 2006.239.07:38:20.92#ibcon#end of sib2, iclass 24, count 0 2006.239.07:38:20.92#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:38:20.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:38:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:38:20.92#ibcon#*before write, iclass 24, count 0 2006.239.07:38:20.92#ibcon#enter sib2, iclass 24, count 0 2006.239.07:38:20.92#ibcon#flushed, iclass 24, count 0 2006.239.07:38:20.92#ibcon#about to write, iclass 24, count 0 2006.239.07:38:20.92#ibcon#wrote, iclass 24, count 0 2006.239.07:38:20.92#ibcon#about to read 3, iclass 24, count 0 2006.239.07:38:20.96#ibcon#read 3, iclass 24, count 0 2006.239.07:38:20.96#ibcon#about to read 4, iclass 24, count 0 2006.239.07:38:20.96#ibcon#read 4, iclass 24, count 0 2006.239.07:38:20.96#ibcon#about to read 5, iclass 24, count 0 2006.239.07:38:20.96#ibcon#read 5, iclass 24, count 0 2006.239.07:38:20.96#ibcon#about to read 6, iclass 24, count 0 2006.239.07:38:20.96#ibcon#read 6, iclass 24, count 0 2006.239.07:38:20.96#ibcon#end of sib2, iclass 24, count 0 2006.239.07:38:20.96#ibcon#*after write, iclass 24, count 0 2006.239.07:38:20.96#ibcon#*before return 0, iclass 24, count 0 2006.239.07:38:20.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:20.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:38:20.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:38:20.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:38:20.96$vc4f8/vb=2,4 2006.239.07:38:20.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.07:38:20.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.07:38:20.96#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:20.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:21.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:21.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:21.02#ibcon#enter wrdev, iclass 26, count 2 2006.239.07:38:21.02#ibcon#first serial, iclass 26, count 2 2006.239.07:38:21.02#ibcon#enter sib2, iclass 26, count 2 2006.239.07:38:21.02#ibcon#flushed, iclass 26, count 2 2006.239.07:38:21.02#ibcon#about to write, iclass 26, count 2 2006.239.07:38:21.02#ibcon#wrote, iclass 26, count 2 2006.239.07:38:21.02#ibcon#about to read 3, iclass 26, count 2 2006.239.07:38:21.04#ibcon#read 3, iclass 26, count 2 2006.239.07:38:21.04#ibcon#about to read 4, iclass 26, count 2 2006.239.07:38:21.04#ibcon#read 4, iclass 26, count 2 2006.239.07:38:21.04#ibcon#about to read 5, iclass 26, count 2 2006.239.07:38:21.04#ibcon#read 5, iclass 26, count 2 2006.239.07:38:21.04#ibcon#about to read 6, iclass 26, count 2 2006.239.07:38:21.04#ibcon#read 6, iclass 26, count 2 2006.239.07:38:21.04#ibcon#end of sib2, iclass 26, count 2 2006.239.07:38:21.04#ibcon#*mode == 0, iclass 26, count 2 2006.239.07:38:21.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.07:38:21.04#ibcon#[27=AT02-04\r\n] 2006.239.07:38:21.04#ibcon#*before write, iclass 26, count 2 2006.239.07:38:21.04#ibcon#enter sib2, iclass 26, count 2 2006.239.07:38:21.04#ibcon#flushed, iclass 26, count 2 2006.239.07:38:21.04#ibcon#about to write, iclass 26, count 2 2006.239.07:38:21.04#ibcon#wrote, iclass 26, count 2 2006.239.07:38:21.04#ibcon#about to read 3, iclass 26, count 2 2006.239.07:38:21.07#ibcon#read 3, iclass 26, count 2 2006.239.07:38:21.07#ibcon#about to read 4, iclass 26, count 2 2006.239.07:38:21.07#ibcon#read 4, iclass 26, count 2 2006.239.07:38:21.07#ibcon#about to read 5, iclass 26, count 2 2006.239.07:38:21.07#ibcon#read 5, iclass 26, count 2 2006.239.07:38:21.07#ibcon#about to read 6, iclass 26, count 2 2006.239.07:38:21.07#ibcon#read 6, iclass 26, count 2 2006.239.07:38:21.07#ibcon#end of sib2, iclass 26, count 2 2006.239.07:38:21.07#ibcon#*after write, iclass 26, count 2 2006.239.07:38:21.07#ibcon#*before return 0, iclass 26, count 2 2006.239.07:38:21.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:21.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:38:21.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.07:38:21.07#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:21.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:21.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:21.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:21.19#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:38:21.19#ibcon#first serial, iclass 26, count 0 2006.239.07:38:21.19#ibcon#enter sib2, iclass 26, count 0 2006.239.07:38:21.19#ibcon#flushed, iclass 26, count 0 2006.239.07:38:21.19#ibcon#about to write, iclass 26, count 0 2006.239.07:38:21.19#ibcon#wrote, iclass 26, count 0 2006.239.07:38:21.19#ibcon#about to read 3, iclass 26, count 0 2006.239.07:38:21.21#ibcon#read 3, iclass 26, count 0 2006.239.07:38:21.21#ibcon#about to read 4, iclass 26, count 0 2006.239.07:38:21.21#ibcon#read 4, iclass 26, count 0 2006.239.07:38:21.21#ibcon#about to read 5, iclass 26, count 0 2006.239.07:38:21.21#ibcon#read 5, iclass 26, count 0 2006.239.07:38:21.21#ibcon#about to read 6, iclass 26, count 0 2006.239.07:38:21.21#ibcon#read 6, iclass 26, count 0 2006.239.07:38:21.21#ibcon#end of sib2, iclass 26, count 0 2006.239.07:38:21.21#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:38:21.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:38:21.21#ibcon#[27=USB\r\n] 2006.239.07:38:21.21#ibcon#*before write, iclass 26, count 0 2006.239.07:38:21.21#ibcon#enter sib2, iclass 26, count 0 2006.239.07:38:21.21#ibcon#flushed, iclass 26, count 0 2006.239.07:38:21.21#ibcon#about to write, iclass 26, count 0 2006.239.07:38:21.21#ibcon#wrote, iclass 26, count 0 2006.239.07:38:21.21#ibcon#about to read 3, iclass 26, count 0 2006.239.07:38:21.25#ibcon#read 3, iclass 26, count 0 2006.239.07:38:21.25#ibcon#about to read 4, iclass 26, count 0 2006.239.07:38:21.25#ibcon#read 4, iclass 26, count 0 2006.239.07:38:21.25#ibcon#about to read 5, iclass 26, count 0 2006.239.07:38:21.25#ibcon#read 5, iclass 26, count 0 2006.239.07:38:21.25#ibcon#about to read 6, iclass 26, count 0 2006.239.07:38:21.25#ibcon#read 6, iclass 26, count 0 2006.239.07:38:21.25#ibcon#end of sib2, iclass 26, count 0 2006.239.07:38:21.25#ibcon#*after write, iclass 26, count 0 2006.239.07:38:21.25#ibcon#*before return 0, iclass 26, count 0 2006.239.07:38:21.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:21.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:38:21.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:38:21.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:38:21.25$vc4f8/vblo=3,656.99 2006.239.07:38:21.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:38:21.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:38:21.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:21.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:38:21.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:38:21.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:38:21.25#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:38:21.25#ibcon#first serial, iclass 29, count 0 2006.239.07:38:21.25#ibcon#enter sib2, iclass 29, count 0 2006.239.07:38:21.25#ibcon#flushed, iclass 29, count 0 2006.239.07:38:21.25#ibcon#about to write, iclass 29, count 0 2006.239.07:38:21.25#ibcon#wrote, iclass 29, count 0 2006.239.07:38:21.25#ibcon#about to read 3, iclass 29, count 0 2006.239.07:38:21.26#ibcon#read 3, iclass 29, count 0 2006.239.07:38:21.26#ibcon#about to read 4, iclass 29, count 0 2006.239.07:38:21.26#ibcon#read 4, iclass 29, count 0 2006.239.07:38:21.26#ibcon#about to read 5, iclass 29, count 0 2006.239.07:38:21.26#ibcon#read 5, iclass 29, count 0 2006.239.07:38:21.26#ibcon#about to read 6, iclass 29, count 0 2006.239.07:38:21.26#ibcon#read 6, iclass 29, count 0 2006.239.07:38:21.26#ibcon#end of sib2, iclass 29, count 0 2006.239.07:38:21.26#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:38:21.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:38:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:38:21.26#ibcon#*before write, iclass 29, count 0 2006.239.07:38:21.26#ibcon#enter sib2, iclass 29, count 0 2006.239.07:38:21.26#ibcon#flushed, iclass 29, count 0 2006.239.07:38:21.26#ibcon#about to write, iclass 29, count 0 2006.239.07:38:21.26#ibcon#wrote, iclass 29, count 0 2006.239.07:38:21.26#ibcon#about to read 3, iclass 29, count 0 2006.239.07:38:21.27#abcon#<5=/04 1.9 3.4 25.37 821011.5\r\n> 2006.239.07:38:21.29#abcon#{5=INTERFACE CLEAR} 2006.239.07:38:21.30#ibcon#read 3, iclass 29, count 0 2006.239.07:38:21.30#ibcon#about to read 4, iclass 29, count 0 2006.239.07:38:21.30#ibcon#read 4, iclass 29, count 0 2006.239.07:38:21.30#ibcon#about to read 5, iclass 29, count 0 2006.239.07:38:21.30#ibcon#read 5, iclass 29, count 0 2006.239.07:38:21.30#ibcon#about to read 6, iclass 29, count 0 2006.239.07:38:21.30#ibcon#read 6, iclass 29, count 0 2006.239.07:38:21.30#ibcon#end of sib2, iclass 29, count 0 2006.239.07:38:21.30#ibcon#*after write, iclass 29, count 0 2006.239.07:38:21.30#ibcon#*before return 0, iclass 29, count 0 2006.239.07:38:21.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:38:21.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:38:21.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:38:21.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:38:21.30$vc4f8/vb=3,4 2006.239.07:38:21.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.07:38:21.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.07:38:21.30#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:21.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:38:21.35#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:38:21.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:38:21.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:38:21.37#ibcon#enter wrdev, iclass 33, count 2 2006.239.07:38:21.37#ibcon#first serial, iclass 33, count 2 2006.239.07:38:21.37#ibcon#enter sib2, iclass 33, count 2 2006.239.07:38:21.37#ibcon#flushed, iclass 33, count 2 2006.239.07:38:21.37#ibcon#about to write, iclass 33, count 2 2006.239.07:38:21.37#ibcon#wrote, iclass 33, count 2 2006.239.07:38:21.37#ibcon#about to read 3, iclass 33, count 2 2006.239.07:38:21.39#ibcon#read 3, iclass 33, count 2 2006.239.07:38:21.39#ibcon#about to read 4, iclass 33, count 2 2006.239.07:38:21.39#ibcon#read 4, iclass 33, count 2 2006.239.07:38:21.39#ibcon#about to read 5, iclass 33, count 2 2006.239.07:38:21.39#ibcon#read 5, iclass 33, count 2 2006.239.07:38:21.39#ibcon#about to read 6, iclass 33, count 2 2006.239.07:38:21.39#ibcon#read 6, iclass 33, count 2 2006.239.07:38:21.39#ibcon#end of sib2, iclass 33, count 2 2006.239.07:38:21.39#ibcon#*mode == 0, iclass 33, count 2 2006.239.07:38:21.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.07:38:21.39#ibcon#[27=AT03-04\r\n] 2006.239.07:38:21.39#ibcon#*before write, iclass 33, count 2 2006.239.07:38:21.39#ibcon#enter sib2, iclass 33, count 2 2006.239.07:38:21.39#ibcon#flushed, iclass 33, count 2 2006.239.07:38:21.39#ibcon#about to write, iclass 33, count 2 2006.239.07:38:21.39#ibcon#wrote, iclass 33, count 2 2006.239.07:38:21.39#ibcon#about to read 3, iclass 33, count 2 2006.239.07:38:21.42#ibcon#read 3, iclass 33, count 2 2006.239.07:38:21.42#ibcon#about to read 4, iclass 33, count 2 2006.239.07:38:21.42#ibcon#read 4, iclass 33, count 2 2006.239.07:38:21.42#ibcon#about to read 5, iclass 33, count 2 2006.239.07:38:21.42#ibcon#read 5, iclass 33, count 2 2006.239.07:38:21.42#ibcon#about to read 6, iclass 33, count 2 2006.239.07:38:21.42#ibcon#read 6, iclass 33, count 2 2006.239.07:38:21.42#ibcon#end of sib2, iclass 33, count 2 2006.239.07:38:21.42#ibcon#*after write, iclass 33, count 2 2006.239.07:38:21.42#ibcon#*before return 0, iclass 33, count 2 2006.239.07:38:21.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:38:21.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:38:21.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.07:38:21.42#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:21.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:38:21.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:38:21.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:38:21.54#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:38:21.54#ibcon#first serial, iclass 33, count 0 2006.239.07:38:21.54#ibcon#enter sib2, iclass 33, count 0 2006.239.07:38:21.54#ibcon#flushed, iclass 33, count 0 2006.239.07:38:21.54#ibcon#about to write, iclass 33, count 0 2006.239.07:38:21.54#ibcon#wrote, iclass 33, count 0 2006.239.07:38:21.54#ibcon#about to read 3, iclass 33, count 0 2006.239.07:38:21.56#ibcon#read 3, iclass 33, count 0 2006.239.07:38:21.56#ibcon#about to read 4, iclass 33, count 0 2006.239.07:38:21.56#ibcon#read 4, iclass 33, count 0 2006.239.07:38:21.56#ibcon#about to read 5, iclass 33, count 0 2006.239.07:38:21.56#ibcon#read 5, iclass 33, count 0 2006.239.07:38:21.56#ibcon#about to read 6, iclass 33, count 0 2006.239.07:38:21.56#ibcon#read 6, iclass 33, count 0 2006.239.07:38:21.56#ibcon#end of sib2, iclass 33, count 0 2006.239.07:38:21.56#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:38:21.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:38:21.56#ibcon#[27=USB\r\n] 2006.239.07:38:21.56#ibcon#*before write, iclass 33, count 0 2006.239.07:38:21.56#ibcon#enter sib2, iclass 33, count 0 2006.239.07:38:21.56#ibcon#flushed, iclass 33, count 0 2006.239.07:38:21.56#ibcon#about to write, iclass 33, count 0 2006.239.07:38:21.56#ibcon#wrote, iclass 33, count 0 2006.239.07:38:21.56#ibcon#about to read 3, iclass 33, count 0 2006.239.07:38:21.59#ibcon#read 3, iclass 33, count 0 2006.239.07:38:21.59#ibcon#about to read 4, iclass 33, count 0 2006.239.07:38:21.59#ibcon#read 4, iclass 33, count 0 2006.239.07:38:21.59#ibcon#about to read 5, iclass 33, count 0 2006.239.07:38:21.59#ibcon#read 5, iclass 33, count 0 2006.239.07:38:21.59#ibcon#about to read 6, iclass 33, count 0 2006.239.07:38:21.59#ibcon#read 6, iclass 33, count 0 2006.239.07:38:21.59#ibcon#end of sib2, iclass 33, count 0 2006.239.07:38:21.59#ibcon#*after write, iclass 33, count 0 2006.239.07:38:21.59#ibcon#*before return 0, iclass 33, count 0 2006.239.07:38:21.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:38:21.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:38:21.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:38:21.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:38:21.59$vc4f8/vblo=4,712.99 2006.239.07:38:21.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.07:38:21.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.07:38:21.59#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:21.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:21.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:21.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:21.59#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:38:21.59#ibcon#first serial, iclass 36, count 0 2006.239.07:38:21.59#ibcon#enter sib2, iclass 36, count 0 2006.239.07:38:21.59#ibcon#flushed, iclass 36, count 0 2006.239.07:38:21.59#ibcon#about to write, iclass 36, count 0 2006.239.07:38:21.59#ibcon#wrote, iclass 36, count 0 2006.239.07:38:21.59#ibcon#about to read 3, iclass 36, count 0 2006.239.07:38:21.61#ibcon#read 3, iclass 36, count 0 2006.239.07:38:21.61#ibcon#about to read 4, iclass 36, count 0 2006.239.07:38:21.61#ibcon#read 4, iclass 36, count 0 2006.239.07:38:21.61#ibcon#about to read 5, iclass 36, count 0 2006.239.07:38:21.61#ibcon#read 5, iclass 36, count 0 2006.239.07:38:21.61#ibcon#about to read 6, iclass 36, count 0 2006.239.07:38:21.61#ibcon#read 6, iclass 36, count 0 2006.239.07:38:21.61#ibcon#end of sib2, iclass 36, count 0 2006.239.07:38:21.61#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:38:21.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:38:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:38:21.61#ibcon#*before write, iclass 36, count 0 2006.239.07:38:21.61#ibcon#enter sib2, iclass 36, count 0 2006.239.07:38:21.61#ibcon#flushed, iclass 36, count 0 2006.239.07:38:21.61#ibcon#about to write, iclass 36, count 0 2006.239.07:38:21.61#ibcon#wrote, iclass 36, count 0 2006.239.07:38:21.61#ibcon#about to read 3, iclass 36, count 0 2006.239.07:38:21.65#ibcon#read 3, iclass 36, count 0 2006.239.07:38:21.65#ibcon#about to read 4, iclass 36, count 0 2006.239.07:38:21.65#ibcon#read 4, iclass 36, count 0 2006.239.07:38:21.65#ibcon#about to read 5, iclass 36, count 0 2006.239.07:38:21.65#ibcon#read 5, iclass 36, count 0 2006.239.07:38:21.65#ibcon#about to read 6, iclass 36, count 0 2006.239.07:38:21.65#ibcon#read 6, iclass 36, count 0 2006.239.07:38:21.65#ibcon#end of sib2, iclass 36, count 0 2006.239.07:38:21.65#ibcon#*after write, iclass 36, count 0 2006.239.07:38:21.65#ibcon#*before return 0, iclass 36, count 0 2006.239.07:38:21.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:21.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:38:21.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:38:21.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:38:21.65$vc4f8/vb=4,4 2006.239.07:38:21.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.07:38:21.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.07:38:21.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:21.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:21.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:21.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:21.71#ibcon#enter wrdev, iclass 38, count 2 2006.239.07:38:21.71#ibcon#first serial, iclass 38, count 2 2006.239.07:38:21.71#ibcon#enter sib2, iclass 38, count 2 2006.239.07:38:21.71#ibcon#flushed, iclass 38, count 2 2006.239.07:38:21.71#ibcon#about to write, iclass 38, count 2 2006.239.07:38:21.71#ibcon#wrote, iclass 38, count 2 2006.239.07:38:21.71#ibcon#about to read 3, iclass 38, count 2 2006.239.07:38:21.73#ibcon#read 3, iclass 38, count 2 2006.239.07:38:21.73#ibcon#about to read 4, iclass 38, count 2 2006.239.07:38:21.73#ibcon#read 4, iclass 38, count 2 2006.239.07:38:21.73#ibcon#about to read 5, iclass 38, count 2 2006.239.07:38:21.73#ibcon#read 5, iclass 38, count 2 2006.239.07:38:21.73#ibcon#about to read 6, iclass 38, count 2 2006.239.07:38:21.73#ibcon#read 6, iclass 38, count 2 2006.239.07:38:21.73#ibcon#end of sib2, iclass 38, count 2 2006.239.07:38:21.73#ibcon#*mode == 0, iclass 38, count 2 2006.239.07:38:21.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.07:38:21.73#ibcon#[27=AT04-04\r\n] 2006.239.07:38:21.73#ibcon#*before write, iclass 38, count 2 2006.239.07:38:21.73#ibcon#enter sib2, iclass 38, count 2 2006.239.07:38:21.73#ibcon#flushed, iclass 38, count 2 2006.239.07:38:21.73#ibcon#about to write, iclass 38, count 2 2006.239.07:38:21.73#ibcon#wrote, iclass 38, count 2 2006.239.07:38:21.73#ibcon#about to read 3, iclass 38, count 2 2006.239.07:38:21.76#ibcon#read 3, iclass 38, count 2 2006.239.07:38:21.76#ibcon#about to read 4, iclass 38, count 2 2006.239.07:38:21.76#ibcon#read 4, iclass 38, count 2 2006.239.07:38:21.76#ibcon#about to read 5, iclass 38, count 2 2006.239.07:38:21.76#ibcon#read 5, iclass 38, count 2 2006.239.07:38:21.76#ibcon#about to read 6, iclass 38, count 2 2006.239.07:38:21.76#ibcon#read 6, iclass 38, count 2 2006.239.07:38:21.76#ibcon#end of sib2, iclass 38, count 2 2006.239.07:38:21.76#ibcon#*after write, iclass 38, count 2 2006.239.07:38:21.76#ibcon#*before return 0, iclass 38, count 2 2006.239.07:38:21.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:21.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:38:21.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.07:38:21.76#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:21.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:21.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:21.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:21.88#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:38:21.88#ibcon#first serial, iclass 38, count 0 2006.239.07:38:21.88#ibcon#enter sib2, iclass 38, count 0 2006.239.07:38:21.88#ibcon#flushed, iclass 38, count 0 2006.239.07:38:21.88#ibcon#about to write, iclass 38, count 0 2006.239.07:38:21.88#ibcon#wrote, iclass 38, count 0 2006.239.07:38:21.88#ibcon#about to read 3, iclass 38, count 0 2006.239.07:38:21.90#ibcon#read 3, iclass 38, count 0 2006.239.07:38:21.90#ibcon#about to read 4, iclass 38, count 0 2006.239.07:38:21.90#ibcon#read 4, iclass 38, count 0 2006.239.07:38:21.90#ibcon#about to read 5, iclass 38, count 0 2006.239.07:38:21.90#ibcon#read 5, iclass 38, count 0 2006.239.07:38:21.90#ibcon#about to read 6, iclass 38, count 0 2006.239.07:38:21.90#ibcon#read 6, iclass 38, count 0 2006.239.07:38:21.90#ibcon#end of sib2, iclass 38, count 0 2006.239.07:38:21.90#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:38:21.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:38:21.90#ibcon#[27=USB\r\n] 2006.239.07:38:21.90#ibcon#*before write, iclass 38, count 0 2006.239.07:38:21.90#ibcon#enter sib2, iclass 38, count 0 2006.239.07:38:21.90#ibcon#flushed, iclass 38, count 0 2006.239.07:38:21.90#ibcon#about to write, iclass 38, count 0 2006.239.07:38:21.90#ibcon#wrote, iclass 38, count 0 2006.239.07:38:21.90#ibcon#about to read 3, iclass 38, count 0 2006.239.07:38:21.93#ibcon#read 3, iclass 38, count 0 2006.239.07:38:21.93#ibcon#about to read 4, iclass 38, count 0 2006.239.07:38:21.93#ibcon#read 4, iclass 38, count 0 2006.239.07:38:21.93#ibcon#about to read 5, iclass 38, count 0 2006.239.07:38:21.93#ibcon#read 5, iclass 38, count 0 2006.239.07:38:21.93#ibcon#about to read 6, iclass 38, count 0 2006.239.07:38:21.93#ibcon#read 6, iclass 38, count 0 2006.239.07:38:21.93#ibcon#end of sib2, iclass 38, count 0 2006.239.07:38:21.93#ibcon#*after write, iclass 38, count 0 2006.239.07:38:21.93#ibcon#*before return 0, iclass 38, count 0 2006.239.07:38:21.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:21.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:38:21.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:38:21.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:38:21.93$vc4f8/vblo=5,744.99 2006.239.07:38:21.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:38:21.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:38:21.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:21.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:21.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:21.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:21.93#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:38:21.93#ibcon#first serial, iclass 40, count 0 2006.239.07:38:21.93#ibcon#enter sib2, iclass 40, count 0 2006.239.07:38:21.93#ibcon#flushed, iclass 40, count 0 2006.239.07:38:21.93#ibcon#about to write, iclass 40, count 0 2006.239.07:38:21.93#ibcon#wrote, iclass 40, count 0 2006.239.07:38:21.93#ibcon#about to read 3, iclass 40, count 0 2006.239.07:38:21.95#ibcon#read 3, iclass 40, count 0 2006.239.07:38:21.95#ibcon#about to read 4, iclass 40, count 0 2006.239.07:38:21.95#ibcon#read 4, iclass 40, count 0 2006.239.07:38:21.95#ibcon#about to read 5, iclass 40, count 0 2006.239.07:38:21.95#ibcon#read 5, iclass 40, count 0 2006.239.07:38:21.95#ibcon#about to read 6, iclass 40, count 0 2006.239.07:38:21.95#ibcon#read 6, iclass 40, count 0 2006.239.07:38:21.95#ibcon#end of sib2, iclass 40, count 0 2006.239.07:38:21.95#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:38:21.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:38:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:38:21.95#ibcon#*before write, iclass 40, count 0 2006.239.07:38:21.95#ibcon#enter sib2, iclass 40, count 0 2006.239.07:38:21.95#ibcon#flushed, iclass 40, count 0 2006.239.07:38:21.95#ibcon#about to write, iclass 40, count 0 2006.239.07:38:21.95#ibcon#wrote, iclass 40, count 0 2006.239.07:38:21.95#ibcon#about to read 3, iclass 40, count 0 2006.239.07:38:22.00#ibcon#read 3, iclass 40, count 0 2006.239.07:38:22.00#ibcon#about to read 4, iclass 40, count 0 2006.239.07:38:22.00#ibcon#read 4, iclass 40, count 0 2006.239.07:38:22.00#ibcon#about to read 5, iclass 40, count 0 2006.239.07:38:22.00#ibcon#read 5, iclass 40, count 0 2006.239.07:38:22.00#ibcon#about to read 6, iclass 40, count 0 2006.239.07:38:22.00#ibcon#read 6, iclass 40, count 0 2006.239.07:38:22.00#ibcon#end of sib2, iclass 40, count 0 2006.239.07:38:22.00#ibcon#*after write, iclass 40, count 0 2006.239.07:38:22.00#ibcon#*before return 0, iclass 40, count 0 2006.239.07:38:22.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:22.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:38:22.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:38:22.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:38:22.00$vc4f8/vb=5,4 2006.239.07:38:22.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:38:22.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:38:22.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:22.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:22.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:22.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:22.04#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:38:22.04#ibcon#first serial, iclass 4, count 2 2006.239.07:38:22.04#ibcon#enter sib2, iclass 4, count 2 2006.239.07:38:22.04#ibcon#flushed, iclass 4, count 2 2006.239.07:38:22.04#ibcon#about to write, iclass 4, count 2 2006.239.07:38:22.04#ibcon#wrote, iclass 4, count 2 2006.239.07:38:22.04#ibcon#about to read 3, iclass 4, count 2 2006.239.07:38:22.06#ibcon#read 3, iclass 4, count 2 2006.239.07:38:22.06#ibcon#about to read 4, iclass 4, count 2 2006.239.07:38:22.06#ibcon#read 4, iclass 4, count 2 2006.239.07:38:22.06#ibcon#about to read 5, iclass 4, count 2 2006.239.07:38:22.06#ibcon#read 5, iclass 4, count 2 2006.239.07:38:22.06#ibcon#about to read 6, iclass 4, count 2 2006.239.07:38:22.06#ibcon#read 6, iclass 4, count 2 2006.239.07:38:22.06#ibcon#end of sib2, iclass 4, count 2 2006.239.07:38:22.06#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:38:22.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:38:22.06#ibcon#[27=AT05-04\r\n] 2006.239.07:38:22.06#ibcon#*before write, iclass 4, count 2 2006.239.07:38:22.06#ibcon#enter sib2, iclass 4, count 2 2006.239.07:38:22.06#ibcon#flushed, iclass 4, count 2 2006.239.07:38:22.06#ibcon#about to write, iclass 4, count 2 2006.239.07:38:22.06#ibcon#wrote, iclass 4, count 2 2006.239.07:38:22.06#ibcon#about to read 3, iclass 4, count 2 2006.239.07:38:22.09#ibcon#read 3, iclass 4, count 2 2006.239.07:38:22.09#ibcon#about to read 4, iclass 4, count 2 2006.239.07:38:22.09#ibcon#read 4, iclass 4, count 2 2006.239.07:38:22.09#ibcon#about to read 5, iclass 4, count 2 2006.239.07:38:22.09#ibcon#read 5, iclass 4, count 2 2006.239.07:38:22.09#ibcon#about to read 6, iclass 4, count 2 2006.239.07:38:22.09#ibcon#read 6, iclass 4, count 2 2006.239.07:38:22.09#ibcon#end of sib2, iclass 4, count 2 2006.239.07:38:22.09#ibcon#*after write, iclass 4, count 2 2006.239.07:38:22.09#ibcon#*before return 0, iclass 4, count 2 2006.239.07:38:22.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:22.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:38:22.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:38:22.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:22.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:22.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:22.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:22.21#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:38:22.21#ibcon#first serial, iclass 4, count 0 2006.239.07:38:22.21#ibcon#enter sib2, iclass 4, count 0 2006.239.07:38:22.21#ibcon#flushed, iclass 4, count 0 2006.239.07:38:22.21#ibcon#about to write, iclass 4, count 0 2006.239.07:38:22.21#ibcon#wrote, iclass 4, count 0 2006.239.07:38:22.21#ibcon#about to read 3, iclass 4, count 0 2006.239.07:38:22.23#ibcon#read 3, iclass 4, count 0 2006.239.07:38:22.23#ibcon#about to read 4, iclass 4, count 0 2006.239.07:38:22.23#ibcon#read 4, iclass 4, count 0 2006.239.07:38:22.23#ibcon#about to read 5, iclass 4, count 0 2006.239.07:38:22.23#ibcon#read 5, iclass 4, count 0 2006.239.07:38:22.23#ibcon#about to read 6, iclass 4, count 0 2006.239.07:38:22.23#ibcon#read 6, iclass 4, count 0 2006.239.07:38:22.23#ibcon#end of sib2, iclass 4, count 0 2006.239.07:38:22.23#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:38:22.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:38:22.23#ibcon#[27=USB\r\n] 2006.239.07:38:22.23#ibcon#*before write, iclass 4, count 0 2006.239.07:38:22.23#ibcon#enter sib2, iclass 4, count 0 2006.239.07:38:22.23#ibcon#flushed, iclass 4, count 0 2006.239.07:38:22.23#ibcon#about to write, iclass 4, count 0 2006.239.07:38:22.23#ibcon#wrote, iclass 4, count 0 2006.239.07:38:22.23#ibcon#about to read 3, iclass 4, count 0 2006.239.07:38:22.26#ibcon#read 3, iclass 4, count 0 2006.239.07:38:22.26#ibcon#about to read 4, iclass 4, count 0 2006.239.07:38:22.26#ibcon#read 4, iclass 4, count 0 2006.239.07:38:22.26#ibcon#about to read 5, iclass 4, count 0 2006.239.07:38:22.26#ibcon#read 5, iclass 4, count 0 2006.239.07:38:22.26#ibcon#about to read 6, iclass 4, count 0 2006.239.07:38:22.26#ibcon#read 6, iclass 4, count 0 2006.239.07:38:22.26#ibcon#end of sib2, iclass 4, count 0 2006.239.07:38:22.26#ibcon#*after write, iclass 4, count 0 2006.239.07:38:22.26#ibcon#*before return 0, iclass 4, count 0 2006.239.07:38:22.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:22.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:38:22.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:38:22.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:38:22.26$vc4f8/vblo=6,752.99 2006.239.07:38:22.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:38:22.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:38:22.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:38:22.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:22.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:22.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:22.26#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:38:22.26#ibcon#first serial, iclass 6, count 0 2006.239.07:38:22.26#ibcon#enter sib2, iclass 6, count 0 2006.239.07:38:22.26#ibcon#flushed, iclass 6, count 0 2006.239.07:38:22.26#ibcon#about to write, iclass 6, count 0 2006.239.07:38:22.26#ibcon#wrote, iclass 6, count 0 2006.239.07:38:22.26#ibcon#about to read 3, iclass 6, count 0 2006.239.07:38:22.28#ibcon#read 3, iclass 6, count 0 2006.239.07:38:22.28#ibcon#about to read 4, iclass 6, count 0 2006.239.07:38:22.28#ibcon#read 4, iclass 6, count 0 2006.239.07:38:22.28#ibcon#about to read 5, iclass 6, count 0 2006.239.07:38:22.28#ibcon#read 5, iclass 6, count 0 2006.239.07:38:22.28#ibcon#about to read 6, iclass 6, count 0 2006.239.07:38:22.28#ibcon#read 6, iclass 6, count 0 2006.239.07:38:22.28#ibcon#end of sib2, iclass 6, count 0 2006.239.07:38:22.28#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:38:22.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:38:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:38:22.28#ibcon#*before write, iclass 6, count 0 2006.239.07:38:22.28#ibcon#enter sib2, iclass 6, count 0 2006.239.07:38:22.28#ibcon#flushed, iclass 6, count 0 2006.239.07:38:22.28#ibcon#about to write, iclass 6, count 0 2006.239.07:38:22.28#ibcon#wrote, iclass 6, count 0 2006.239.07:38:22.28#ibcon#about to read 3, iclass 6, count 0 2006.239.07:38:22.32#ibcon#read 3, iclass 6, count 0 2006.239.07:38:22.32#ibcon#about to read 4, iclass 6, count 0 2006.239.07:38:22.32#ibcon#read 4, iclass 6, count 0 2006.239.07:38:22.32#ibcon#about to read 5, iclass 6, count 0 2006.239.07:38:22.32#ibcon#read 5, iclass 6, count 0 2006.239.07:38:22.32#ibcon#about to read 6, iclass 6, count 0 2006.239.07:38:22.32#ibcon#read 6, iclass 6, count 0 2006.239.07:38:22.32#ibcon#end of sib2, iclass 6, count 0 2006.239.07:38:22.32#ibcon#*after write, iclass 6, count 0 2006.239.07:38:22.32#ibcon#*before return 0, iclass 6, count 0 2006.239.07:38:22.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:22.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:38:22.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:38:22.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:38:22.32$vc4f8/vb=6,4 2006.239.07:38:22.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:38:22.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:38:22.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:38:22.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:22.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:22.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:22.38#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:38:22.38#ibcon#first serial, iclass 10, count 2 2006.239.07:38:22.38#ibcon#enter sib2, iclass 10, count 2 2006.239.07:38:22.38#ibcon#flushed, iclass 10, count 2 2006.239.07:38:22.38#ibcon#about to write, iclass 10, count 2 2006.239.07:38:22.38#ibcon#wrote, iclass 10, count 2 2006.239.07:38:22.38#ibcon#about to read 3, iclass 10, count 2 2006.239.07:38:22.40#ibcon#read 3, iclass 10, count 2 2006.239.07:38:22.40#ibcon#about to read 4, iclass 10, count 2 2006.239.07:38:22.40#ibcon#read 4, iclass 10, count 2 2006.239.07:38:22.40#ibcon#about to read 5, iclass 10, count 2 2006.239.07:38:22.40#ibcon#read 5, iclass 10, count 2 2006.239.07:38:22.40#ibcon#about to read 6, iclass 10, count 2 2006.239.07:38:22.40#ibcon#read 6, iclass 10, count 2 2006.239.07:38:22.40#ibcon#end of sib2, iclass 10, count 2 2006.239.07:38:22.40#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:38:22.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:38:22.40#ibcon#[27=AT06-04\r\n] 2006.239.07:38:22.40#ibcon#*before write, iclass 10, count 2 2006.239.07:38:22.40#ibcon#enter sib2, iclass 10, count 2 2006.239.07:38:22.40#ibcon#flushed, iclass 10, count 2 2006.239.07:38:22.40#ibcon#about to write, iclass 10, count 2 2006.239.07:38:22.40#ibcon#wrote, iclass 10, count 2 2006.239.07:38:22.40#ibcon#about to read 3, iclass 10, count 2 2006.239.07:38:22.43#ibcon#read 3, iclass 10, count 2 2006.239.07:38:22.43#ibcon#about to read 4, iclass 10, count 2 2006.239.07:38:22.43#ibcon#read 4, iclass 10, count 2 2006.239.07:38:22.43#ibcon#about to read 5, iclass 10, count 2 2006.239.07:38:22.43#ibcon#read 5, iclass 10, count 2 2006.239.07:38:22.43#ibcon#about to read 6, iclass 10, count 2 2006.239.07:38:22.43#ibcon#read 6, iclass 10, count 2 2006.239.07:38:22.43#ibcon#end of sib2, iclass 10, count 2 2006.239.07:38:22.43#ibcon#*after write, iclass 10, count 2 2006.239.07:38:22.43#ibcon#*before return 0, iclass 10, count 2 2006.239.07:38:22.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:22.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:38:22.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:38:22.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:38:22.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:22.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:22.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:22.55#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:38:22.55#ibcon#first serial, iclass 10, count 0 2006.239.07:38:22.55#ibcon#enter sib2, iclass 10, count 0 2006.239.07:38:22.55#ibcon#flushed, iclass 10, count 0 2006.239.07:38:22.55#ibcon#about to write, iclass 10, count 0 2006.239.07:38:22.55#ibcon#wrote, iclass 10, count 0 2006.239.07:38:22.55#ibcon#about to read 3, iclass 10, count 0 2006.239.07:38:22.57#ibcon#read 3, iclass 10, count 0 2006.239.07:38:22.57#ibcon#about to read 4, iclass 10, count 0 2006.239.07:38:22.57#ibcon#read 4, iclass 10, count 0 2006.239.07:38:22.57#ibcon#about to read 5, iclass 10, count 0 2006.239.07:38:22.57#ibcon#read 5, iclass 10, count 0 2006.239.07:38:22.57#ibcon#about to read 6, iclass 10, count 0 2006.239.07:38:22.57#ibcon#read 6, iclass 10, count 0 2006.239.07:38:22.57#ibcon#end of sib2, iclass 10, count 0 2006.239.07:38:22.57#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:38:22.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:38:22.57#ibcon#[27=USB\r\n] 2006.239.07:38:22.57#ibcon#*before write, iclass 10, count 0 2006.239.07:38:22.57#ibcon#enter sib2, iclass 10, count 0 2006.239.07:38:22.57#ibcon#flushed, iclass 10, count 0 2006.239.07:38:22.57#ibcon#about to write, iclass 10, count 0 2006.239.07:38:22.57#ibcon#wrote, iclass 10, count 0 2006.239.07:38:22.57#ibcon#about to read 3, iclass 10, count 0 2006.239.07:38:22.60#ibcon#read 3, iclass 10, count 0 2006.239.07:38:22.60#ibcon#about to read 4, iclass 10, count 0 2006.239.07:38:22.60#ibcon#read 4, iclass 10, count 0 2006.239.07:38:22.60#ibcon#about to read 5, iclass 10, count 0 2006.239.07:38:22.60#ibcon#read 5, iclass 10, count 0 2006.239.07:38:22.60#ibcon#about to read 6, iclass 10, count 0 2006.239.07:38:22.60#ibcon#read 6, iclass 10, count 0 2006.239.07:38:22.60#ibcon#end of sib2, iclass 10, count 0 2006.239.07:38:22.60#ibcon#*after write, iclass 10, count 0 2006.239.07:38:22.60#ibcon#*before return 0, iclass 10, count 0 2006.239.07:38:22.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:22.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:38:22.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:38:22.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:38:22.60$vc4f8/vabw=wide 2006.239.07:38:22.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:38:22.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:38:22.60#ibcon#ireg 8 cls_cnt 0 2006.239.07:38:22.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:22.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:22.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:22.60#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:38:22.60#ibcon#first serial, iclass 12, count 0 2006.239.07:38:22.60#ibcon#enter sib2, iclass 12, count 0 2006.239.07:38:22.60#ibcon#flushed, iclass 12, count 0 2006.239.07:38:22.60#ibcon#about to write, iclass 12, count 0 2006.239.07:38:22.60#ibcon#wrote, iclass 12, count 0 2006.239.07:38:22.60#ibcon#about to read 3, iclass 12, count 0 2006.239.07:38:22.62#ibcon#read 3, iclass 12, count 0 2006.239.07:38:22.62#ibcon#about to read 4, iclass 12, count 0 2006.239.07:38:22.62#ibcon#read 4, iclass 12, count 0 2006.239.07:38:22.62#ibcon#about to read 5, iclass 12, count 0 2006.239.07:38:22.62#ibcon#read 5, iclass 12, count 0 2006.239.07:38:22.62#ibcon#about to read 6, iclass 12, count 0 2006.239.07:38:22.62#ibcon#read 6, iclass 12, count 0 2006.239.07:38:22.62#ibcon#end of sib2, iclass 12, count 0 2006.239.07:38:22.62#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:38:22.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:38:22.62#ibcon#[25=BW32\r\n] 2006.239.07:38:22.62#ibcon#*before write, iclass 12, count 0 2006.239.07:38:22.62#ibcon#enter sib2, iclass 12, count 0 2006.239.07:38:22.62#ibcon#flushed, iclass 12, count 0 2006.239.07:38:22.62#ibcon#about to write, iclass 12, count 0 2006.239.07:38:22.62#ibcon#wrote, iclass 12, count 0 2006.239.07:38:22.62#ibcon#about to read 3, iclass 12, count 0 2006.239.07:38:22.65#ibcon#read 3, iclass 12, count 0 2006.239.07:38:22.65#ibcon#about to read 4, iclass 12, count 0 2006.239.07:38:22.65#ibcon#read 4, iclass 12, count 0 2006.239.07:38:22.65#ibcon#about to read 5, iclass 12, count 0 2006.239.07:38:22.65#ibcon#read 5, iclass 12, count 0 2006.239.07:38:22.65#ibcon#about to read 6, iclass 12, count 0 2006.239.07:38:22.65#ibcon#read 6, iclass 12, count 0 2006.239.07:38:22.65#ibcon#end of sib2, iclass 12, count 0 2006.239.07:38:22.65#ibcon#*after write, iclass 12, count 0 2006.239.07:38:22.65#ibcon#*before return 0, iclass 12, count 0 2006.239.07:38:22.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:22.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:38:22.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:38:22.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:38:22.65$vc4f8/vbbw=wide 2006.239.07:38:22.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:38:22.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:38:22.65#ibcon#ireg 8 cls_cnt 0 2006.239.07:38:22.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:38:22.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:38:22.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:38:22.73#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:38:22.73#ibcon#first serial, iclass 14, count 0 2006.239.07:38:22.73#ibcon#enter sib2, iclass 14, count 0 2006.239.07:38:22.73#ibcon#flushed, iclass 14, count 0 2006.239.07:38:22.73#ibcon#about to write, iclass 14, count 0 2006.239.07:38:22.73#ibcon#wrote, iclass 14, count 0 2006.239.07:38:22.73#ibcon#about to read 3, iclass 14, count 0 2006.239.07:38:22.75#ibcon#read 3, iclass 14, count 0 2006.239.07:38:22.75#ibcon#about to read 4, iclass 14, count 0 2006.239.07:38:22.75#ibcon#read 4, iclass 14, count 0 2006.239.07:38:22.75#ibcon#about to read 5, iclass 14, count 0 2006.239.07:38:22.75#ibcon#read 5, iclass 14, count 0 2006.239.07:38:22.75#ibcon#about to read 6, iclass 14, count 0 2006.239.07:38:22.75#ibcon#read 6, iclass 14, count 0 2006.239.07:38:22.75#ibcon#end of sib2, iclass 14, count 0 2006.239.07:38:22.75#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:38:22.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:38:22.75#ibcon#[27=BW32\r\n] 2006.239.07:38:22.75#ibcon#*before write, iclass 14, count 0 2006.239.07:38:22.75#ibcon#enter sib2, iclass 14, count 0 2006.239.07:38:22.75#ibcon#flushed, iclass 14, count 0 2006.239.07:38:22.75#ibcon#about to write, iclass 14, count 0 2006.239.07:38:22.75#ibcon#wrote, iclass 14, count 0 2006.239.07:38:22.75#ibcon#about to read 3, iclass 14, count 0 2006.239.07:38:22.77#ibcon#read 3, iclass 14, count 0 2006.239.07:38:22.77#ibcon#about to read 4, iclass 14, count 0 2006.239.07:38:22.77#ibcon#read 4, iclass 14, count 0 2006.239.07:38:22.77#ibcon#about to read 5, iclass 14, count 0 2006.239.07:38:22.77#ibcon#read 5, iclass 14, count 0 2006.239.07:38:22.77#ibcon#about to read 6, iclass 14, count 0 2006.239.07:38:22.77#ibcon#read 6, iclass 14, count 0 2006.239.07:38:22.77#ibcon#end of sib2, iclass 14, count 0 2006.239.07:38:22.77#ibcon#*after write, iclass 14, count 0 2006.239.07:38:22.77#ibcon#*before return 0, iclass 14, count 0 2006.239.07:38:22.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:38:22.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:38:22.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:38:22.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:38:22.77$4f8m12a/ifd4f 2006.239.07:38:22.77$ifd4f/lo= 2006.239.07:38:22.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:38:22.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:38:22.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:38:22.77$ifd4f/patch= 2006.239.07:38:22.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:38:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:38:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:38:22.78$4f8m12a/"form=m,16.000,1:2 2006.239.07:38:22.78$4f8m12a/"tpicd 2006.239.07:38:22.78$4f8m12a/echo=off 2006.239.07:38:22.78$4f8m12a/xlog=off 2006.239.07:38:22.78:!2006.239.07:38:50 2006.239.07:38:35.14#trakl#Source acquired 2006.239.07:38:37.14#flagr#flagr/antenna,acquired 2006.239.07:38:50.01:preob 2006.239.07:38:51.14/onsource/TRACKING 2006.239.07:38:51.14:!2006.239.07:39:00 2006.239.07:39:00.00:data_valid=on 2006.239.07:39:00.00:midob 2006.239.07:39:00.14/onsource/TRACKING 2006.239.07:39:00.14/wx/25.37,1011.4,81 2006.239.07:39:00.26/cable/+6.4157E-03 2006.239.07:39:01.35/va/01,08,usb,yes,30,32 2006.239.07:39:01.35/va/02,07,usb,yes,30,32 2006.239.07:39:01.35/va/03,07,usb,yes,29,29 2006.239.07:39:01.35/va/04,07,usb,yes,32,35 2006.239.07:39:01.35/va/05,08,usb,yes,29,30 2006.239.07:39:01.35/va/06,07,usb,yes,31,31 2006.239.07:39:01.35/va/07,07,usb,yes,31,31 2006.239.07:39:01.35/va/08,07,usb,yes,34,33 2006.239.07:39:01.58/valo/01,532.99,yes,locked 2006.239.07:39:01.58/valo/02,572.99,yes,locked 2006.239.07:39:01.58/valo/03,672.99,yes,locked 2006.239.07:39:01.58/valo/04,832.99,yes,locked 2006.239.07:39:01.58/valo/05,652.99,yes,locked 2006.239.07:39:01.58/valo/06,772.99,yes,locked 2006.239.07:39:01.58/valo/07,832.99,yes,locked 2006.239.07:39:01.58/valo/08,852.99,yes,locked 2006.239.07:39:02.67/vb/01,04,usb,yes,30,29 2006.239.07:39:02.67/vb/02,04,usb,yes,32,33 2006.239.07:39:02.67/vb/03,04,usb,yes,28,32 2006.239.07:39:02.67/vb/04,04,usb,yes,29,29 2006.239.07:39:02.67/vb/05,04,usb,yes,27,31 2006.239.07:39:02.67/vb/06,04,usb,yes,28,31 2006.239.07:39:02.67/vb/07,04,usb,yes,30,30 2006.239.07:39:02.67/vb/08,04,usb,yes,28,31 2006.239.07:39:02.91/vblo/01,632.99,yes,locked 2006.239.07:39:02.91/vblo/02,640.99,yes,locked 2006.239.07:39:02.91/vblo/03,656.99,yes,locked 2006.239.07:39:02.91/vblo/04,712.99,yes,locked 2006.239.07:39:02.91/vblo/05,744.99,yes,locked 2006.239.07:39:02.91/vblo/06,752.99,yes,locked 2006.239.07:39:02.91/vblo/07,734.99,yes,locked 2006.239.07:39:02.91/vblo/08,744.99,yes,locked 2006.239.07:39:03.06/vabw/8 2006.239.07:39:03.21/vbbw/8 2006.239.07:39:03.30/xfe/off,on,14.0 2006.239.07:39:03.67/ifatt/23,28,28,28 2006.239.07:39:04.07/fmout-gps/S +4.36E-07 2006.239.07:39:04.12:!2006.239.07:40:00 2006.239.07:40:00.01:data_valid=off 2006.239.07:40:00.02:postob 2006.239.07:40:00.13/cable/+6.4160E-03 2006.239.07:40:00.14/wx/25.37,1011.4,80 2006.239.07:40:00.19/fmout-gps/S +4.37E-07 2006.239.07:40:00.20:scan_name=239-0741,k06239,60 2006.239.07:40:00.20:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.239.07:40:02.13#flagr#flagr/antenna,new-source 2006.239.07:40:02.14:checkk5 2006.239.07:40:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:40:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:40:04.01/chk_obsdata//k5ts1/T2390739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:40:04.39/chk_obsdata//k5ts2/T2390739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:40:04.77/chk_obsdata//k5ts3/T2390739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:40:05.14/chk_obsdata//k5ts4/T2390739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:40:05.83/k5log//k5ts1_log_newline 2006.239.07:40:06.54/k5log//k5ts2_log_newline 2006.239.07:40:07.23/k5log//k5ts3_log_newline 2006.239.07:40:07.92/k5log//k5ts4_log_newline 2006.239.07:40:07.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:40:07.94:4f8m12a=1 2006.239.07:40:07.94$4f8m12a/echo=on 2006.239.07:40:07.94$4f8m12a/pcalon 2006.239.07:40:07.94$pcalon/"no phase cal control is implemented here 2006.239.07:40:07.94$4f8m12a/"tpicd=stop 2006.239.07:40:07.94$4f8m12a/vc4f8 2006.239.07:40:07.94$vc4f8/valo=1,532.99 2006.239.07:40:07.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.07:40:07.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.07:40:07.95#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:07.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:07.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:07.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:07.95#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:40:07.95#ibcon#first serial, iclass 21, count 0 2006.239.07:40:07.95#ibcon#enter sib2, iclass 21, count 0 2006.239.07:40:07.95#ibcon#flushed, iclass 21, count 0 2006.239.07:40:07.95#ibcon#about to write, iclass 21, count 0 2006.239.07:40:07.95#ibcon#wrote, iclass 21, count 0 2006.239.07:40:07.95#ibcon#about to read 3, iclass 21, count 0 2006.239.07:40:07.99#ibcon#read 3, iclass 21, count 0 2006.239.07:40:07.99#ibcon#about to read 4, iclass 21, count 0 2006.239.07:40:07.99#ibcon#read 4, iclass 21, count 0 2006.239.07:40:07.99#ibcon#about to read 5, iclass 21, count 0 2006.239.07:40:07.99#ibcon#read 5, iclass 21, count 0 2006.239.07:40:07.99#ibcon#about to read 6, iclass 21, count 0 2006.239.07:40:07.99#ibcon#read 6, iclass 21, count 0 2006.239.07:40:07.99#ibcon#end of sib2, iclass 21, count 0 2006.239.07:40:07.99#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:40:07.99#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:40:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:40:07.99#ibcon#*before write, iclass 21, count 0 2006.239.07:40:07.99#ibcon#enter sib2, iclass 21, count 0 2006.239.07:40:07.99#ibcon#flushed, iclass 21, count 0 2006.239.07:40:07.99#ibcon#about to write, iclass 21, count 0 2006.239.07:40:07.99#ibcon#wrote, iclass 21, count 0 2006.239.07:40:07.99#ibcon#about to read 3, iclass 21, count 0 2006.239.07:40:08.03#ibcon#read 3, iclass 21, count 0 2006.239.07:40:08.03#ibcon#about to read 4, iclass 21, count 0 2006.239.07:40:08.03#ibcon#read 4, iclass 21, count 0 2006.239.07:40:08.03#ibcon#about to read 5, iclass 21, count 0 2006.239.07:40:08.03#ibcon#read 5, iclass 21, count 0 2006.239.07:40:08.03#ibcon#about to read 6, iclass 21, count 0 2006.239.07:40:08.03#ibcon#read 6, iclass 21, count 0 2006.239.07:40:08.03#ibcon#end of sib2, iclass 21, count 0 2006.239.07:40:08.03#ibcon#*after write, iclass 21, count 0 2006.239.07:40:08.03#ibcon#*before return 0, iclass 21, count 0 2006.239.07:40:08.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:08.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:08.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:40:08.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:40:08.03$vc4f8/va=1,8 2006.239.07:40:08.03#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.07:40:08.03#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.07:40:08.03#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:08.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:08.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:08.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:08.03#ibcon#enter wrdev, iclass 23, count 2 2006.239.07:40:08.03#ibcon#first serial, iclass 23, count 2 2006.239.07:40:08.03#ibcon#enter sib2, iclass 23, count 2 2006.239.07:40:08.03#ibcon#flushed, iclass 23, count 2 2006.239.07:40:08.03#ibcon#about to write, iclass 23, count 2 2006.239.07:40:08.03#ibcon#wrote, iclass 23, count 2 2006.239.07:40:08.03#ibcon#about to read 3, iclass 23, count 2 2006.239.07:40:08.05#ibcon#read 3, iclass 23, count 2 2006.239.07:40:08.05#ibcon#about to read 4, iclass 23, count 2 2006.239.07:40:08.05#ibcon#read 4, iclass 23, count 2 2006.239.07:40:08.05#ibcon#about to read 5, iclass 23, count 2 2006.239.07:40:08.05#ibcon#read 5, iclass 23, count 2 2006.239.07:40:08.05#ibcon#about to read 6, iclass 23, count 2 2006.239.07:40:08.05#ibcon#read 6, iclass 23, count 2 2006.239.07:40:08.05#ibcon#end of sib2, iclass 23, count 2 2006.239.07:40:08.05#ibcon#*mode == 0, iclass 23, count 2 2006.239.07:40:08.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.07:40:08.05#ibcon#[25=AT01-08\r\n] 2006.239.07:40:08.05#ibcon#*before write, iclass 23, count 2 2006.239.07:40:08.05#ibcon#enter sib2, iclass 23, count 2 2006.239.07:40:08.05#ibcon#flushed, iclass 23, count 2 2006.239.07:40:08.05#ibcon#about to write, iclass 23, count 2 2006.239.07:40:08.05#ibcon#wrote, iclass 23, count 2 2006.239.07:40:08.05#ibcon#about to read 3, iclass 23, count 2 2006.239.07:40:08.09#ibcon#read 3, iclass 23, count 2 2006.239.07:40:08.09#ibcon#about to read 4, iclass 23, count 2 2006.239.07:40:08.09#ibcon#read 4, iclass 23, count 2 2006.239.07:40:08.09#ibcon#about to read 5, iclass 23, count 2 2006.239.07:40:08.09#ibcon#read 5, iclass 23, count 2 2006.239.07:40:08.09#ibcon#about to read 6, iclass 23, count 2 2006.239.07:40:08.09#ibcon#read 6, iclass 23, count 2 2006.239.07:40:08.09#ibcon#end of sib2, iclass 23, count 2 2006.239.07:40:08.09#ibcon#*after write, iclass 23, count 2 2006.239.07:40:08.09#ibcon#*before return 0, iclass 23, count 2 2006.239.07:40:08.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:08.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:08.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.07:40:08.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:08.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:08.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:08.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:08.20#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:40:08.20#ibcon#first serial, iclass 23, count 0 2006.239.07:40:08.20#ibcon#enter sib2, iclass 23, count 0 2006.239.07:40:08.20#ibcon#flushed, iclass 23, count 0 2006.239.07:40:08.20#ibcon#about to write, iclass 23, count 0 2006.239.07:40:08.20#ibcon#wrote, iclass 23, count 0 2006.239.07:40:08.20#ibcon#about to read 3, iclass 23, count 0 2006.239.07:40:08.22#ibcon#read 3, iclass 23, count 0 2006.239.07:40:08.22#ibcon#about to read 4, iclass 23, count 0 2006.239.07:40:08.22#ibcon#read 4, iclass 23, count 0 2006.239.07:40:08.22#ibcon#about to read 5, iclass 23, count 0 2006.239.07:40:08.22#ibcon#read 5, iclass 23, count 0 2006.239.07:40:08.22#ibcon#about to read 6, iclass 23, count 0 2006.239.07:40:08.22#ibcon#read 6, iclass 23, count 0 2006.239.07:40:08.22#ibcon#end of sib2, iclass 23, count 0 2006.239.07:40:08.22#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:40:08.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:40:08.22#ibcon#[25=USB\r\n] 2006.239.07:40:08.22#ibcon#*before write, iclass 23, count 0 2006.239.07:40:08.22#ibcon#enter sib2, iclass 23, count 0 2006.239.07:40:08.22#ibcon#flushed, iclass 23, count 0 2006.239.07:40:08.22#ibcon#about to write, iclass 23, count 0 2006.239.07:40:08.22#ibcon#wrote, iclass 23, count 0 2006.239.07:40:08.22#ibcon#about to read 3, iclass 23, count 0 2006.239.07:40:08.25#ibcon#read 3, iclass 23, count 0 2006.239.07:40:08.25#ibcon#about to read 4, iclass 23, count 0 2006.239.07:40:08.25#ibcon#read 4, iclass 23, count 0 2006.239.07:40:08.25#ibcon#about to read 5, iclass 23, count 0 2006.239.07:40:08.25#ibcon#read 5, iclass 23, count 0 2006.239.07:40:08.25#ibcon#about to read 6, iclass 23, count 0 2006.239.07:40:08.25#ibcon#read 6, iclass 23, count 0 2006.239.07:40:08.25#ibcon#end of sib2, iclass 23, count 0 2006.239.07:40:08.25#ibcon#*after write, iclass 23, count 0 2006.239.07:40:08.25#ibcon#*before return 0, iclass 23, count 0 2006.239.07:40:08.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:08.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:08.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:40:08.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:40:08.25$vc4f8/valo=2,572.99 2006.239.07:40:08.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:40:08.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:40:08.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:08.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:08.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:08.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:08.25#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:40:08.25#ibcon#first serial, iclass 25, count 0 2006.239.07:40:08.25#ibcon#enter sib2, iclass 25, count 0 2006.239.07:40:08.25#ibcon#flushed, iclass 25, count 0 2006.239.07:40:08.25#ibcon#about to write, iclass 25, count 0 2006.239.07:40:08.25#ibcon#wrote, iclass 25, count 0 2006.239.07:40:08.25#ibcon#about to read 3, iclass 25, count 0 2006.239.07:40:08.27#ibcon#read 3, iclass 25, count 0 2006.239.07:40:08.27#ibcon#about to read 4, iclass 25, count 0 2006.239.07:40:08.27#ibcon#read 4, iclass 25, count 0 2006.239.07:40:08.27#ibcon#about to read 5, iclass 25, count 0 2006.239.07:40:08.27#ibcon#read 5, iclass 25, count 0 2006.239.07:40:08.27#ibcon#about to read 6, iclass 25, count 0 2006.239.07:40:08.27#ibcon#read 6, iclass 25, count 0 2006.239.07:40:08.27#ibcon#end of sib2, iclass 25, count 0 2006.239.07:40:08.27#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:40:08.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:40:08.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:40:08.27#ibcon#*before write, iclass 25, count 0 2006.239.07:40:08.27#ibcon#enter sib2, iclass 25, count 0 2006.239.07:40:08.27#ibcon#flushed, iclass 25, count 0 2006.239.07:40:08.27#ibcon#about to write, iclass 25, count 0 2006.239.07:40:08.27#ibcon#wrote, iclass 25, count 0 2006.239.07:40:08.27#ibcon#about to read 3, iclass 25, count 0 2006.239.07:40:08.31#ibcon#read 3, iclass 25, count 0 2006.239.07:40:08.31#ibcon#about to read 4, iclass 25, count 0 2006.239.07:40:08.31#ibcon#read 4, iclass 25, count 0 2006.239.07:40:08.31#ibcon#about to read 5, iclass 25, count 0 2006.239.07:40:08.31#ibcon#read 5, iclass 25, count 0 2006.239.07:40:08.31#ibcon#about to read 6, iclass 25, count 0 2006.239.07:40:08.31#ibcon#read 6, iclass 25, count 0 2006.239.07:40:08.31#ibcon#end of sib2, iclass 25, count 0 2006.239.07:40:08.31#ibcon#*after write, iclass 25, count 0 2006.239.07:40:08.31#ibcon#*before return 0, iclass 25, count 0 2006.239.07:40:08.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:08.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:08.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:40:08.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:40:08.31$vc4f8/va=2,7 2006.239.07:40:08.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:40:08.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:40:08.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:08.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:08.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:08.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:08.37#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:40:08.37#ibcon#first serial, iclass 27, count 2 2006.239.07:40:08.37#ibcon#enter sib2, iclass 27, count 2 2006.239.07:40:08.37#ibcon#flushed, iclass 27, count 2 2006.239.07:40:08.37#ibcon#about to write, iclass 27, count 2 2006.239.07:40:08.37#ibcon#wrote, iclass 27, count 2 2006.239.07:40:08.37#ibcon#about to read 3, iclass 27, count 2 2006.239.07:40:08.39#ibcon#read 3, iclass 27, count 2 2006.239.07:40:08.39#ibcon#about to read 4, iclass 27, count 2 2006.239.07:40:08.39#ibcon#read 4, iclass 27, count 2 2006.239.07:40:08.39#ibcon#about to read 5, iclass 27, count 2 2006.239.07:40:08.39#ibcon#read 5, iclass 27, count 2 2006.239.07:40:08.39#ibcon#about to read 6, iclass 27, count 2 2006.239.07:40:08.39#ibcon#read 6, iclass 27, count 2 2006.239.07:40:08.39#ibcon#end of sib2, iclass 27, count 2 2006.239.07:40:08.39#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:40:08.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:40:08.39#ibcon#[25=AT02-07\r\n] 2006.239.07:40:08.39#ibcon#*before write, iclass 27, count 2 2006.239.07:40:08.39#ibcon#enter sib2, iclass 27, count 2 2006.239.07:40:08.39#ibcon#flushed, iclass 27, count 2 2006.239.07:40:08.39#ibcon#about to write, iclass 27, count 2 2006.239.07:40:08.39#ibcon#wrote, iclass 27, count 2 2006.239.07:40:08.39#ibcon#about to read 3, iclass 27, count 2 2006.239.07:40:08.42#ibcon#read 3, iclass 27, count 2 2006.239.07:40:08.42#ibcon#about to read 4, iclass 27, count 2 2006.239.07:40:08.42#ibcon#read 4, iclass 27, count 2 2006.239.07:40:08.42#ibcon#about to read 5, iclass 27, count 2 2006.239.07:40:08.42#ibcon#read 5, iclass 27, count 2 2006.239.07:40:08.42#ibcon#about to read 6, iclass 27, count 2 2006.239.07:40:08.42#ibcon#read 6, iclass 27, count 2 2006.239.07:40:08.42#ibcon#end of sib2, iclass 27, count 2 2006.239.07:40:08.42#ibcon#*after write, iclass 27, count 2 2006.239.07:40:08.42#ibcon#*before return 0, iclass 27, count 2 2006.239.07:40:08.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:08.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:08.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:40:08.42#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:08.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:08.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:08.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:08.54#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:40:08.54#ibcon#first serial, iclass 27, count 0 2006.239.07:40:08.54#ibcon#enter sib2, iclass 27, count 0 2006.239.07:40:08.54#ibcon#flushed, iclass 27, count 0 2006.239.07:40:08.54#ibcon#about to write, iclass 27, count 0 2006.239.07:40:08.54#ibcon#wrote, iclass 27, count 0 2006.239.07:40:08.54#ibcon#about to read 3, iclass 27, count 0 2006.239.07:40:08.56#ibcon#read 3, iclass 27, count 0 2006.239.07:40:08.56#ibcon#about to read 4, iclass 27, count 0 2006.239.07:40:08.56#ibcon#read 4, iclass 27, count 0 2006.239.07:40:08.56#ibcon#about to read 5, iclass 27, count 0 2006.239.07:40:08.56#ibcon#read 5, iclass 27, count 0 2006.239.07:40:08.56#ibcon#about to read 6, iclass 27, count 0 2006.239.07:40:08.56#ibcon#read 6, iclass 27, count 0 2006.239.07:40:08.56#ibcon#end of sib2, iclass 27, count 0 2006.239.07:40:08.56#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:40:08.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:40:08.56#ibcon#[25=USB\r\n] 2006.239.07:40:08.56#ibcon#*before write, iclass 27, count 0 2006.239.07:40:08.56#ibcon#enter sib2, iclass 27, count 0 2006.239.07:40:08.56#ibcon#flushed, iclass 27, count 0 2006.239.07:40:08.56#ibcon#about to write, iclass 27, count 0 2006.239.07:40:08.56#ibcon#wrote, iclass 27, count 0 2006.239.07:40:08.56#ibcon#about to read 3, iclass 27, count 0 2006.239.07:40:08.59#ibcon#read 3, iclass 27, count 0 2006.239.07:40:08.59#ibcon#about to read 4, iclass 27, count 0 2006.239.07:40:08.59#ibcon#read 4, iclass 27, count 0 2006.239.07:40:08.59#ibcon#about to read 5, iclass 27, count 0 2006.239.07:40:08.59#ibcon#read 5, iclass 27, count 0 2006.239.07:40:08.59#ibcon#about to read 6, iclass 27, count 0 2006.239.07:40:08.59#ibcon#read 6, iclass 27, count 0 2006.239.07:40:08.59#ibcon#end of sib2, iclass 27, count 0 2006.239.07:40:08.59#ibcon#*after write, iclass 27, count 0 2006.239.07:40:08.59#ibcon#*before return 0, iclass 27, count 0 2006.239.07:40:08.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:08.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:08.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:40:08.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:40:08.59$vc4f8/valo=3,672.99 2006.239.07:40:08.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:40:08.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:40:08.59#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:08.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:08.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:08.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:08.59#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:40:08.59#ibcon#first serial, iclass 29, count 0 2006.239.07:40:08.59#ibcon#enter sib2, iclass 29, count 0 2006.239.07:40:08.59#ibcon#flushed, iclass 29, count 0 2006.239.07:40:08.59#ibcon#about to write, iclass 29, count 0 2006.239.07:40:08.59#ibcon#wrote, iclass 29, count 0 2006.239.07:40:08.59#ibcon#about to read 3, iclass 29, count 0 2006.239.07:40:08.61#ibcon#read 3, iclass 29, count 0 2006.239.07:40:08.61#ibcon#about to read 4, iclass 29, count 0 2006.239.07:40:08.61#ibcon#read 4, iclass 29, count 0 2006.239.07:40:08.61#ibcon#about to read 5, iclass 29, count 0 2006.239.07:40:08.61#ibcon#read 5, iclass 29, count 0 2006.239.07:40:08.61#ibcon#about to read 6, iclass 29, count 0 2006.239.07:40:08.61#ibcon#read 6, iclass 29, count 0 2006.239.07:40:08.61#ibcon#end of sib2, iclass 29, count 0 2006.239.07:40:08.61#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:40:08.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:40:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:40:08.61#ibcon#*before write, iclass 29, count 0 2006.239.07:40:08.61#ibcon#enter sib2, iclass 29, count 0 2006.239.07:40:08.61#ibcon#flushed, iclass 29, count 0 2006.239.07:40:08.61#ibcon#about to write, iclass 29, count 0 2006.239.07:40:08.61#ibcon#wrote, iclass 29, count 0 2006.239.07:40:08.61#ibcon#about to read 3, iclass 29, count 0 2006.239.07:40:08.65#ibcon#read 3, iclass 29, count 0 2006.239.07:40:08.65#ibcon#about to read 4, iclass 29, count 0 2006.239.07:40:08.65#ibcon#read 4, iclass 29, count 0 2006.239.07:40:08.65#ibcon#about to read 5, iclass 29, count 0 2006.239.07:40:08.65#ibcon#read 5, iclass 29, count 0 2006.239.07:40:08.65#ibcon#about to read 6, iclass 29, count 0 2006.239.07:40:08.65#ibcon#read 6, iclass 29, count 0 2006.239.07:40:08.65#ibcon#end of sib2, iclass 29, count 0 2006.239.07:40:08.65#ibcon#*after write, iclass 29, count 0 2006.239.07:40:08.65#ibcon#*before return 0, iclass 29, count 0 2006.239.07:40:08.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:08.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:08.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:40:08.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:40:08.65$vc4f8/va=3,7 2006.239.07:40:08.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:40:08.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:40:08.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:08.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:08.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:08.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:08.71#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:40:08.71#ibcon#first serial, iclass 31, count 2 2006.239.07:40:08.71#ibcon#enter sib2, iclass 31, count 2 2006.239.07:40:08.71#ibcon#flushed, iclass 31, count 2 2006.239.07:40:08.71#ibcon#about to write, iclass 31, count 2 2006.239.07:40:08.71#ibcon#wrote, iclass 31, count 2 2006.239.07:40:08.71#ibcon#about to read 3, iclass 31, count 2 2006.239.07:40:08.73#ibcon#read 3, iclass 31, count 2 2006.239.07:40:08.73#ibcon#about to read 4, iclass 31, count 2 2006.239.07:40:08.73#ibcon#read 4, iclass 31, count 2 2006.239.07:40:08.73#ibcon#about to read 5, iclass 31, count 2 2006.239.07:40:08.73#ibcon#read 5, iclass 31, count 2 2006.239.07:40:08.73#ibcon#about to read 6, iclass 31, count 2 2006.239.07:40:08.73#ibcon#read 6, iclass 31, count 2 2006.239.07:40:08.73#ibcon#end of sib2, iclass 31, count 2 2006.239.07:40:08.73#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:40:08.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:40:08.73#ibcon#[25=AT03-07\r\n] 2006.239.07:40:08.73#ibcon#*before write, iclass 31, count 2 2006.239.07:40:08.73#ibcon#enter sib2, iclass 31, count 2 2006.239.07:40:08.73#ibcon#flushed, iclass 31, count 2 2006.239.07:40:08.73#ibcon#about to write, iclass 31, count 2 2006.239.07:40:08.73#ibcon#wrote, iclass 31, count 2 2006.239.07:40:08.73#ibcon#about to read 3, iclass 31, count 2 2006.239.07:40:08.77#ibcon#read 3, iclass 31, count 2 2006.239.07:40:08.77#ibcon#about to read 4, iclass 31, count 2 2006.239.07:40:08.77#ibcon#read 4, iclass 31, count 2 2006.239.07:40:08.77#ibcon#about to read 5, iclass 31, count 2 2006.239.07:40:08.77#ibcon#read 5, iclass 31, count 2 2006.239.07:40:08.77#ibcon#about to read 6, iclass 31, count 2 2006.239.07:40:08.77#ibcon#read 6, iclass 31, count 2 2006.239.07:40:08.77#ibcon#end of sib2, iclass 31, count 2 2006.239.07:40:08.77#ibcon#*after write, iclass 31, count 2 2006.239.07:40:08.77#ibcon#*before return 0, iclass 31, count 2 2006.239.07:40:08.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:08.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:08.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:40:08.77#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:08.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:08.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:08.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:08.88#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:40:08.88#ibcon#first serial, iclass 31, count 0 2006.239.07:40:08.88#ibcon#enter sib2, iclass 31, count 0 2006.239.07:40:08.88#ibcon#flushed, iclass 31, count 0 2006.239.07:40:08.88#ibcon#about to write, iclass 31, count 0 2006.239.07:40:08.88#ibcon#wrote, iclass 31, count 0 2006.239.07:40:08.88#ibcon#about to read 3, iclass 31, count 0 2006.239.07:40:08.90#ibcon#read 3, iclass 31, count 0 2006.239.07:40:08.90#ibcon#about to read 4, iclass 31, count 0 2006.239.07:40:08.90#ibcon#read 4, iclass 31, count 0 2006.239.07:40:08.90#ibcon#about to read 5, iclass 31, count 0 2006.239.07:40:08.90#ibcon#read 5, iclass 31, count 0 2006.239.07:40:08.90#ibcon#about to read 6, iclass 31, count 0 2006.239.07:40:08.90#ibcon#read 6, iclass 31, count 0 2006.239.07:40:08.90#ibcon#end of sib2, iclass 31, count 0 2006.239.07:40:08.90#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:40:08.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:40:08.90#ibcon#[25=USB\r\n] 2006.239.07:40:08.90#ibcon#*before write, iclass 31, count 0 2006.239.07:40:08.90#ibcon#enter sib2, iclass 31, count 0 2006.239.07:40:08.90#ibcon#flushed, iclass 31, count 0 2006.239.07:40:08.90#ibcon#about to write, iclass 31, count 0 2006.239.07:40:08.90#ibcon#wrote, iclass 31, count 0 2006.239.07:40:08.90#ibcon#about to read 3, iclass 31, count 0 2006.239.07:40:08.93#ibcon#read 3, iclass 31, count 0 2006.239.07:40:08.93#ibcon#about to read 4, iclass 31, count 0 2006.239.07:40:08.93#ibcon#read 4, iclass 31, count 0 2006.239.07:40:08.93#ibcon#about to read 5, iclass 31, count 0 2006.239.07:40:08.93#ibcon#read 5, iclass 31, count 0 2006.239.07:40:08.93#ibcon#about to read 6, iclass 31, count 0 2006.239.07:40:08.93#ibcon#read 6, iclass 31, count 0 2006.239.07:40:08.93#ibcon#end of sib2, iclass 31, count 0 2006.239.07:40:08.93#ibcon#*after write, iclass 31, count 0 2006.239.07:40:08.93#ibcon#*before return 0, iclass 31, count 0 2006.239.07:40:08.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:08.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:08.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:40:08.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:40:08.93$vc4f8/valo=4,832.99 2006.239.07:40:08.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:40:08.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:40:08.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:08.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:08.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:08.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:08.93#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:40:08.93#ibcon#first serial, iclass 33, count 0 2006.239.07:40:08.93#ibcon#enter sib2, iclass 33, count 0 2006.239.07:40:08.93#ibcon#flushed, iclass 33, count 0 2006.239.07:40:08.93#ibcon#about to write, iclass 33, count 0 2006.239.07:40:08.93#ibcon#wrote, iclass 33, count 0 2006.239.07:40:08.93#ibcon#about to read 3, iclass 33, count 0 2006.239.07:40:08.95#ibcon#read 3, iclass 33, count 0 2006.239.07:40:08.95#ibcon#about to read 4, iclass 33, count 0 2006.239.07:40:08.95#ibcon#read 4, iclass 33, count 0 2006.239.07:40:08.95#ibcon#about to read 5, iclass 33, count 0 2006.239.07:40:08.95#ibcon#read 5, iclass 33, count 0 2006.239.07:40:08.95#ibcon#about to read 6, iclass 33, count 0 2006.239.07:40:08.95#ibcon#read 6, iclass 33, count 0 2006.239.07:40:08.95#ibcon#end of sib2, iclass 33, count 0 2006.239.07:40:08.95#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:40:08.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:40:08.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:40:08.95#ibcon#*before write, iclass 33, count 0 2006.239.07:40:08.95#ibcon#enter sib2, iclass 33, count 0 2006.239.07:40:08.95#ibcon#flushed, iclass 33, count 0 2006.239.07:40:08.95#ibcon#about to write, iclass 33, count 0 2006.239.07:40:08.95#ibcon#wrote, iclass 33, count 0 2006.239.07:40:08.95#ibcon#about to read 3, iclass 33, count 0 2006.239.07:40:08.99#ibcon#read 3, iclass 33, count 0 2006.239.07:40:08.99#ibcon#about to read 4, iclass 33, count 0 2006.239.07:40:08.99#ibcon#read 4, iclass 33, count 0 2006.239.07:40:08.99#ibcon#about to read 5, iclass 33, count 0 2006.239.07:40:08.99#ibcon#read 5, iclass 33, count 0 2006.239.07:40:08.99#ibcon#about to read 6, iclass 33, count 0 2006.239.07:40:08.99#ibcon#read 6, iclass 33, count 0 2006.239.07:40:08.99#ibcon#end of sib2, iclass 33, count 0 2006.239.07:40:08.99#ibcon#*after write, iclass 33, count 0 2006.239.07:40:08.99#ibcon#*before return 0, iclass 33, count 0 2006.239.07:40:08.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:08.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:08.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:40:08.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:40:08.99$vc4f8/va=4,7 2006.239.07:40:08.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:40:08.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:40:08.99#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:08.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:09.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:09.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:09.05#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:40:09.05#ibcon#first serial, iclass 35, count 2 2006.239.07:40:09.05#ibcon#enter sib2, iclass 35, count 2 2006.239.07:40:09.05#ibcon#flushed, iclass 35, count 2 2006.239.07:40:09.05#ibcon#about to write, iclass 35, count 2 2006.239.07:40:09.05#ibcon#wrote, iclass 35, count 2 2006.239.07:40:09.05#ibcon#about to read 3, iclass 35, count 2 2006.239.07:40:09.07#ibcon#read 3, iclass 35, count 2 2006.239.07:40:09.07#ibcon#about to read 4, iclass 35, count 2 2006.239.07:40:09.07#ibcon#read 4, iclass 35, count 2 2006.239.07:40:09.07#ibcon#about to read 5, iclass 35, count 2 2006.239.07:40:09.07#ibcon#read 5, iclass 35, count 2 2006.239.07:40:09.07#ibcon#about to read 6, iclass 35, count 2 2006.239.07:40:09.07#ibcon#read 6, iclass 35, count 2 2006.239.07:40:09.07#ibcon#end of sib2, iclass 35, count 2 2006.239.07:40:09.07#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:40:09.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:40:09.07#ibcon#[25=AT04-07\r\n] 2006.239.07:40:09.07#ibcon#*before write, iclass 35, count 2 2006.239.07:40:09.07#ibcon#enter sib2, iclass 35, count 2 2006.239.07:40:09.07#ibcon#flushed, iclass 35, count 2 2006.239.07:40:09.07#ibcon#about to write, iclass 35, count 2 2006.239.07:40:09.07#ibcon#wrote, iclass 35, count 2 2006.239.07:40:09.07#ibcon#about to read 3, iclass 35, count 2 2006.239.07:40:09.10#ibcon#read 3, iclass 35, count 2 2006.239.07:40:09.10#ibcon#about to read 4, iclass 35, count 2 2006.239.07:40:09.10#ibcon#read 4, iclass 35, count 2 2006.239.07:40:09.10#ibcon#about to read 5, iclass 35, count 2 2006.239.07:40:09.10#ibcon#read 5, iclass 35, count 2 2006.239.07:40:09.10#ibcon#about to read 6, iclass 35, count 2 2006.239.07:40:09.10#ibcon#read 6, iclass 35, count 2 2006.239.07:40:09.10#ibcon#end of sib2, iclass 35, count 2 2006.239.07:40:09.10#ibcon#*after write, iclass 35, count 2 2006.239.07:40:09.10#ibcon#*before return 0, iclass 35, count 2 2006.239.07:40:09.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:09.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:09.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:40:09.10#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:09.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:09.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:09.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:09.22#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:40:09.22#ibcon#first serial, iclass 35, count 0 2006.239.07:40:09.22#ibcon#enter sib2, iclass 35, count 0 2006.239.07:40:09.22#ibcon#flushed, iclass 35, count 0 2006.239.07:40:09.22#ibcon#about to write, iclass 35, count 0 2006.239.07:40:09.22#ibcon#wrote, iclass 35, count 0 2006.239.07:40:09.22#ibcon#about to read 3, iclass 35, count 0 2006.239.07:40:09.24#ibcon#read 3, iclass 35, count 0 2006.239.07:40:09.24#ibcon#about to read 4, iclass 35, count 0 2006.239.07:40:09.24#ibcon#read 4, iclass 35, count 0 2006.239.07:40:09.24#ibcon#about to read 5, iclass 35, count 0 2006.239.07:40:09.24#ibcon#read 5, iclass 35, count 0 2006.239.07:40:09.24#ibcon#about to read 6, iclass 35, count 0 2006.239.07:40:09.24#ibcon#read 6, iclass 35, count 0 2006.239.07:40:09.24#ibcon#end of sib2, iclass 35, count 0 2006.239.07:40:09.24#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:40:09.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:40:09.24#ibcon#[25=USB\r\n] 2006.239.07:40:09.24#ibcon#*before write, iclass 35, count 0 2006.239.07:40:09.24#ibcon#enter sib2, iclass 35, count 0 2006.239.07:40:09.24#ibcon#flushed, iclass 35, count 0 2006.239.07:40:09.24#ibcon#about to write, iclass 35, count 0 2006.239.07:40:09.24#ibcon#wrote, iclass 35, count 0 2006.239.07:40:09.24#ibcon#about to read 3, iclass 35, count 0 2006.239.07:40:09.27#ibcon#read 3, iclass 35, count 0 2006.239.07:40:09.27#ibcon#about to read 4, iclass 35, count 0 2006.239.07:40:09.27#ibcon#read 4, iclass 35, count 0 2006.239.07:40:09.27#ibcon#about to read 5, iclass 35, count 0 2006.239.07:40:09.27#ibcon#read 5, iclass 35, count 0 2006.239.07:40:09.27#ibcon#about to read 6, iclass 35, count 0 2006.239.07:40:09.27#ibcon#read 6, iclass 35, count 0 2006.239.07:40:09.27#ibcon#end of sib2, iclass 35, count 0 2006.239.07:40:09.27#ibcon#*after write, iclass 35, count 0 2006.239.07:40:09.27#ibcon#*before return 0, iclass 35, count 0 2006.239.07:40:09.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:09.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:09.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:40:09.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:40:09.27$vc4f8/valo=5,652.99 2006.239.07:40:09.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:40:09.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:40:09.27#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:09.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:09.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:09.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:09.27#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:40:09.27#ibcon#first serial, iclass 37, count 0 2006.239.07:40:09.27#ibcon#enter sib2, iclass 37, count 0 2006.239.07:40:09.27#ibcon#flushed, iclass 37, count 0 2006.239.07:40:09.27#ibcon#about to write, iclass 37, count 0 2006.239.07:40:09.27#ibcon#wrote, iclass 37, count 0 2006.239.07:40:09.27#ibcon#about to read 3, iclass 37, count 0 2006.239.07:40:09.29#ibcon#read 3, iclass 37, count 0 2006.239.07:40:09.29#ibcon#about to read 4, iclass 37, count 0 2006.239.07:40:09.29#ibcon#read 4, iclass 37, count 0 2006.239.07:40:09.29#ibcon#about to read 5, iclass 37, count 0 2006.239.07:40:09.29#ibcon#read 5, iclass 37, count 0 2006.239.07:40:09.29#ibcon#about to read 6, iclass 37, count 0 2006.239.07:40:09.29#ibcon#read 6, iclass 37, count 0 2006.239.07:40:09.29#ibcon#end of sib2, iclass 37, count 0 2006.239.07:40:09.29#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:40:09.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:40:09.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:40:09.29#ibcon#*before write, iclass 37, count 0 2006.239.07:40:09.29#ibcon#enter sib2, iclass 37, count 0 2006.239.07:40:09.29#ibcon#flushed, iclass 37, count 0 2006.239.07:40:09.29#ibcon#about to write, iclass 37, count 0 2006.239.07:40:09.29#ibcon#wrote, iclass 37, count 0 2006.239.07:40:09.29#ibcon#about to read 3, iclass 37, count 0 2006.239.07:40:09.33#ibcon#read 3, iclass 37, count 0 2006.239.07:40:09.33#ibcon#about to read 4, iclass 37, count 0 2006.239.07:40:09.33#ibcon#read 4, iclass 37, count 0 2006.239.07:40:09.33#ibcon#about to read 5, iclass 37, count 0 2006.239.07:40:09.33#ibcon#read 5, iclass 37, count 0 2006.239.07:40:09.33#ibcon#about to read 6, iclass 37, count 0 2006.239.07:40:09.33#ibcon#read 6, iclass 37, count 0 2006.239.07:40:09.33#ibcon#end of sib2, iclass 37, count 0 2006.239.07:40:09.33#ibcon#*after write, iclass 37, count 0 2006.239.07:40:09.33#ibcon#*before return 0, iclass 37, count 0 2006.239.07:40:09.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:09.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:09.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:40:09.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:40:09.33$vc4f8/va=5,8 2006.239.07:40:09.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:40:09.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:40:09.33#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:09.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:09.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:09.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:09.40#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:40:09.40#ibcon#first serial, iclass 39, count 2 2006.239.07:40:09.40#ibcon#enter sib2, iclass 39, count 2 2006.239.07:40:09.40#ibcon#flushed, iclass 39, count 2 2006.239.07:40:09.40#ibcon#about to write, iclass 39, count 2 2006.239.07:40:09.40#ibcon#wrote, iclass 39, count 2 2006.239.07:40:09.40#ibcon#about to read 3, iclass 39, count 2 2006.239.07:40:09.41#ibcon#read 3, iclass 39, count 2 2006.239.07:40:09.41#ibcon#about to read 4, iclass 39, count 2 2006.239.07:40:09.41#ibcon#read 4, iclass 39, count 2 2006.239.07:40:09.41#ibcon#about to read 5, iclass 39, count 2 2006.239.07:40:09.41#ibcon#read 5, iclass 39, count 2 2006.239.07:40:09.41#ibcon#about to read 6, iclass 39, count 2 2006.239.07:40:09.41#ibcon#read 6, iclass 39, count 2 2006.239.07:40:09.41#ibcon#end of sib2, iclass 39, count 2 2006.239.07:40:09.41#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:40:09.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:40:09.41#ibcon#[25=AT05-08\r\n] 2006.239.07:40:09.41#ibcon#*before write, iclass 39, count 2 2006.239.07:40:09.41#ibcon#enter sib2, iclass 39, count 2 2006.239.07:40:09.41#ibcon#flushed, iclass 39, count 2 2006.239.07:40:09.41#ibcon#about to write, iclass 39, count 2 2006.239.07:40:09.41#ibcon#wrote, iclass 39, count 2 2006.239.07:40:09.41#ibcon#about to read 3, iclass 39, count 2 2006.239.07:40:09.44#ibcon#read 3, iclass 39, count 2 2006.239.07:40:09.44#ibcon#about to read 4, iclass 39, count 2 2006.239.07:40:09.44#ibcon#read 4, iclass 39, count 2 2006.239.07:40:09.44#ibcon#about to read 5, iclass 39, count 2 2006.239.07:40:09.44#ibcon#read 5, iclass 39, count 2 2006.239.07:40:09.44#ibcon#about to read 6, iclass 39, count 2 2006.239.07:40:09.44#ibcon#read 6, iclass 39, count 2 2006.239.07:40:09.44#ibcon#end of sib2, iclass 39, count 2 2006.239.07:40:09.44#ibcon#*after write, iclass 39, count 2 2006.239.07:40:09.44#ibcon#*before return 0, iclass 39, count 2 2006.239.07:40:09.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:09.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:09.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:40:09.44#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:09.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:09.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:09.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:09.56#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:40:09.56#ibcon#first serial, iclass 39, count 0 2006.239.07:40:09.56#ibcon#enter sib2, iclass 39, count 0 2006.239.07:40:09.56#ibcon#flushed, iclass 39, count 0 2006.239.07:40:09.56#ibcon#about to write, iclass 39, count 0 2006.239.07:40:09.56#ibcon#wrote, iclass 39, count 0 2006.239.07:40:09.56#ibcon#about to read 3, iclass 39, count 0 2006.239.07:40:09.58#ibcon#read 3, iclass 39, count 0 2006.239.07:40:09.58#ibcon#about to read 4, iclass 39, count 0 2006.239.07:40:09.58#ibcon#read 4, iclass 39, count 0 2006.239.07:40:09.58#ibcon#about to read 5, iclass 39, count 0 2006.239.07:40:09.58#ibcon#read 5, iclass 39, count 0 2006.239.07:40:09.58#ibcon#about to read 6, iclass 39, count 0 2006.239.07:40:09.58#ibcon#read 6, iclass 39, count 0 2006.239.07:40:09.58#ibcon#end of sib2, iclass 39, count 0 2006.239.07:40:09.58#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:40:09.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:40:09.58#ibcon#[25=USB\r\n] 2006.239.07:40:09.58#ibcon#*before write, iclass 39, count 0 2006.239.07:40:09.58#ibcon#enter sib2, iclass 39, count 0 2006.239.07:40:09.58#ibcon#flushed, iclass 39, count 0 2006.239.07:40:09.58#ibcon#about to write, iclass 39, count 0 2006.239.07:40:09.58#ibcon#wrote, iclass 39, count 0 2006.239.07:40:09.58#ibcon#about to read 3, iclass 39, count 0 2006.239.07:40:09.61#ibcon#read 3, iclass 39, count 0 2006.239.07:40:09.61#ibcon#about to read 4, iclass 39, count 0 2006.239.07:40:09.61#ibcon#read 4, iclass 39, count 0 2006.239.07:40:09.61#ibcon#about to read 5, iclass 39, count 0 2006.239.07:40:09.61#ibcon#read 5, iclass 39, count 0 2006.239.07:40:09.61#ibcon#about to read 6, iclass 39, count 0 2006.239.07:40:09.61#ibcon#read 6, iclass 39, count 0 2006.239.07:40:09.61#ibcon#end of sib2, iclass 39, count 0 2006.239.07:40:09.61#ibcon#*after write, iclass 39, count 0 2006.239.07:40:09.61#ibcon#*before return 0, iclass 39, count 0 2006.239.07:40:09.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:09.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:09.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:40:09.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:40:09.61$vc4f8/valo=6,772.99 2006.239.07:40:09.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:40:09.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:40:09.61#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:09.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:09.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:09.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:09.61#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:40:09.61#ibcon#first serial, iclass 3, count 0 2006.239.07:40:09.61#ibcon#enter sib2, iclass 3, count 0 2006.239.07:40:09.61#ibcon#flushed, iclass 3, count 0 2006.239.07:40:09.61#ibcon#about to write, iclass 3, count 0 2006.239.07:40:09.61#ibcon#wrote, iclass 3, count 0 2006.239.07:40:09.61#ibcon#about to read 3, iclass 3, count 0 2006.239.07:40:09.63#ibcon#read 3, iclass 3, count 0 2006.239.07:40:09.63#ibcon#about to read 4, iclass 3, count 0 2006.239.07:40:09.63#ibcon#read 4, iclass 3, count 0 2006.239.07:40:09.63#ibcon#about to read 5, iclass 3, count 0 2006.239.07:40:09.63#ibcon#read 5, iclass 3, count 0 2006.239.07:40:09.63#ibcon#about to read 6, iclass 3, count 0 2006.239.07:40:09.63#ibcon#read 6, iclass 3, count 0 2006.239.07:40:09.63#ibcon#end of sib2, iclass 3, count 0 2006.239.07:40:09.63#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:40:09.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:40:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:40:09.63#ibcon#*before write, iclass 3, count 0 2006.239.07:40:09.63#ibcon#enter sib2, iclass 3, count 0 2006.239.07:40:09.63#ibcon#flushed, iclass 3, count 0 2006.239.07:40:09.63#ibcon#about to write, iclass 3, count 0 2006.239.07:40:09.63#ibcon#wrote, iclass 3, count 0 2006.239.07:40:09.63#ibcon#about to read 3, iclass 3, count 0 2006.239.07:40:09.67#ibcon#read 3, iclass 3, count 0 2006.239.07:40:09.67#ibcon#about to read 4, iclass 3, count 0 2006.239.07:40:09.67#ibcon#read 4, iclass 3, count 0 2006.239.07:40:09.67#ibcon#about to read 5, iclass 3, count 0 2006.239.07:40:09.67#ibcon#read 5, iclass 3, count 0 2006.239.07:40:09.67#ibcon#about to read 6, iclass 3, count 0 2006.239.07:40:09.67#ibcon#read 6, iclass 3, count 0 2006.239.07:40:09.67#ibcon#end of sib2, iclass 3, count 0 2006.239.07:40:09.67#ibcon#*after write, iclass 3, count 0 2006.239.07:40:09.67#ibcon#*before return 0, iclass 3, count 0 2006.239.07:40:09.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:09.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:09.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:40:09.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:40:09.67$vc4f8/va=6,7 2006.239.07:40:09.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.07:40:09.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.07:40:09.67#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:09.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:40:09.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:40:09.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:40:09.73#ibcon#enter wrdev, iclass 5, count 2 2006.239.07:40:09.73#ibcon#first serial, iclass 5, count 2 2006.239.07:40:09.73#ibcon#enter sib2, iclass 5, count 2 2006.239.07:40:09.73#ibcon#flushed, iclass 5, count 2 2006.239.07:40:09.73#ibcon#about to write, iclass 5, count 2 2006.239.07:40:09.73#ibcon#wrote, iclass 5, count 2 2006.239.07:40:09.73#ibcon#about to read 3, iclass 5, count 2 2006.239.07:40:09.75#ibcon#read 3, iclass 5, count 2 2006.239.07:40:09.75#ibcon#about to read 4, iclass 5, count 2 2006.239.07:40:09.75#ibcon#read 4, iclass 5, count 2 2006.239.07:40:09.75#ibcon#about to read 5, iclass 5, count 2 2006.239.07:40:09.75#ibcon#read 5, iclass 5, count 2 2006.239.07:40:09.75#ibcon#about to read 6, iclass 5, count 2 2006.239.07:40:09.75#ibcon#read 6, iclass 5, count 2 2006.239.07:40:09.75#ibcon#end of sib2, iclass 5, count 2 2006.239.07:40:09.75#ibcon#*mode == 0, iclass 5, count 2 2006.239.07:40:09.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.07:40:09.75#ibcon#[25=AT06-07\r\n] 2006.239.07:40:09.75#ibcon#*before write, iclass 5, count 2 2006.239.07:40:09.75#ibcon#enter sib2, iclass 5, count 2 2006.239.07:40:09.75#ibcon#flushed, iclass 5, count 2 2006.239.07:40:09.75#ibcon#about to write, iclass 5, count 2 2006.239.07:40:09.75#ibcon#wrote, iclass 5, count 2 2006.239.07:40:09.75#ibcon#about to read 3, iclass 5, count 2 2006.239.07:40:09.78#ibcon#read 3, iclass 5, count 2 2006.239.07:40:09.78#ibcon#about to read 4, iclass 5, count 2 2006.239.07:40:09.78#ibcon#read 4, iclass 5, count 2 2006.239.07:40:09.78#ibcon#about to read 5, iclass 5, count 2 2006.239.07:40:09.78#ibcon#read 5, iclass 5, count 2 2006.239.07:40:09.78#ibcon#about to read 6, iclass 5, count 2 2006.239.07:40:09.78#ibcon#read 6, iclass 5, count 2 2006.239.07:40:09.78#ibcon#end of sib2, iclass 5, count 2 2006.239.07:40:09.78#ibcon#*after write, iclass 5, count 2 2006.239.07:40:09.78#ibcon#*before return 0, iclass 5, count 2 2006.239.07:40:09.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:40:09.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:40:09.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.07:40:09.78#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:09.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:40:09.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:40:09.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:40:09.90#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:40:09.90#ibcon#first serial, iclass 5, count 0 2006.239.07:40:09.90#ibcon#enter sib2, iclass 5, count 0 2006.239.07:40:09.90#ibcon#flushed, iclass 5, count 0 2006.239.07:40:09.90#ibcon#about to write, iclass 5, count 0 2006.239.07:40:09.90#ibcon#wrote, iclass 5, count 0 2006.239.07:40:09.90#ibcon#about to read 3, iclass 5, count 0 2006.239.07:40:09.92#ibcon#read 3, iclass 5, count 0 2006.239.07:40:09.92#ibcon#about to read 4, iclass 5, count 0 2006.239.07:40:09.92#ibcon#read 4, iclass 5, count 0 2006.239.07:40:09.92#ibcon#about to read 5, iclass 5, count 0 2006.239.07:40:09.92#ibcon#read 5, iclass 5, count 0 2006.239.07:40:09.92#ibcon#about to read 6, iclass 5, count 0 2006.239.07:40:09.92#ibcon#read 6, iclass 5, count 0 2006.239.07:40:09.92#ibcon#end of sib2, iclass 5, count 0 2006.239.07:40:09.92#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:40:09.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:40:09.92#ibcon#[25=USB\r\n] 2006.239.07:40:09.92#ibcon#*before write, iclass 5, count 0 2006.239.07:40:09.92#ibcon#enter sib2, iclass 5, count 0 2006.239.07:40:09.92#ibcon#flushed, iclass 5, count 0 2006.239.07:40:09.92#ibcon#about to write, iclass 5, count 0 2006.239.07:40:09.92#ibcon#wrote, iclass 5, count 0 2006.239.07:40:09.92#ibcon#about to read 3, iclass 5, count 0 2006.239.07:40:09.95#ibcon#read 3, iclass 5, count 0 2006.239.07:40:09.95#ibcon#about to read 4, iclass 5, count 0 2006.239.07:40:09.95#ibcon#read 4, iclass 5, count 0 2006.239.07:40:09.95#ibcon#about to read 5, iclass 5, count 0 2006.239.07:40:09.95#ibcon#read 5, iclass 5, count 0 2006.239.07:40:09.95#ibcon#about to read 6, iclass 5, count 0 2006.239.07:40:09.95#ibcon#read 6, iclass 5, count 0 2006.239.07:40:09.95#ibcon#end of sib2, iclass 5, count 0 2006.239.07:40:09.95#ibcon#*after write, iclass 5, count 0 2006.239.07:40:09.95#ibcon#*before return 0, iclass 5, count 0 2006.239.07:40:09.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:40:09.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:40:09.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:40:09.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:40:09.95$vc4f8/valo=7,832.99 2006.239.07:40:09.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:40:09.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:40:09.95#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:09.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:40:09.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:40:09.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:40:09.95#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:40:09.95#ibcon#first serial, iclass 7, count 0 2006.239.07:40:09.95#ibcon#enter sib2, iclass 7, count 0 2006.239.07:40:09.95#ibcon#flushed, iclass 7, count 0 2006.239.07:40:09.95#ibcon#about to write, iclass 7, count 0 2006.239.07:40:09.95#ibcon#wrote, iclass 7, count 0 2006.239.07:40:09.95#ibcon#about to read 3, iclass 7, count 0 2006.239.07:40:09.97#ibcon#read 3, iclass 7, count 0 2006.239.07:40:09.97#ibcon#about to read 4, iclass 7, count 0 2006.239.07:40:09.97#ibcon#read 4, iclass 7, count 0 2006.239.07:40:09.97#ibcon#about to read 5, iclass 7, count 0 2006.239.07:40:09.97#ibcon#read 5, iclass 7, count 0 2006.239.07:40:09.97#ibcon#about to read 6, iclass 7, count 0 2006.239.07:40:09.97#ibcon#read 6, iclass 7, count 0 2006.239.07:40:09.97#ibcon#end of sib2, iclass 7, count 0 2006.239.07:40:09.97#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:40:09.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:40:09.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:40:09.97#ibcon#*before write, iclass 7, count 0 2006.239.07:40:09.97#ibcon#enter sib2, iclass 7, count 0 2006.239.07:40:09.97#ibcon#flushed, iclass 7, count 0 2006.239.07:40:09.97#ibcon#about to write, iclass 7, count 0 2006.239.07:40:09.97#ibcon#wrote, iclass 7, count 0 2006.239.07:40:09.97#ibcon#about to read 3, iclass 7, count 0 2006.239.07:40:10.01#ibcon#read 3, iclass 7, count 0 2006.239.07:40:10.01#ibcon#about to read 4, iclass 7, count 0 2006.239.07:40:10.01#ibcon#read 4, iclass 7, count 0 2006.239.07:40:10.01#ibcon#about to read 5, iclass 7, count 0 2006.239.07:40:10.01#ibcon#read 5, iclass 7, count 0 2006.239.07:40:10.01#ibcon#about to read 6, iclass 7, count 0 2006.239.07:40:10.01#ibcon#read 6, iclass 7, count 0 2006.239.07:40:10.01#ibcon#end of sib2, iclass 7, count 0 2006.239.07:40:10.01#ibcon#*after write, iclass 7, count 0 2006.239.07:40:10.01#ibcon#*before return 0, iclass 7, count 0 2006.239.07:40:10.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:40:10.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:40:10.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:40:10.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:40:10.01$vc4f8/va=7,7 2006.239.07:40:10.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.07:40:10.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.07:40:10.01#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:10.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:40:10.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:40:10.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:40:10.07#ibcon#enter wrdev, iclass 11, count 2 2006.239.07:40:10.07#ibcon#first serial, iclass 11, count 2 2006.239.07:40:10.07#ibcon#enter sib2, iclass 11, count 2 2006.239.07:40:10.07#ibcon#flushed, iclass 11, count 2 2006.239.07:40:10.07#ibcon#about to write, iclass 11, count 2 2006.239.07:40:10.07#ibcon#wrote, iclass 11, count 2 2006.239.07:40:10.07#ibcon#about to read 3, iclass 11, count 2 2006.239.07:40:10.09#ibcon#read 3, iclass 11, count 2 2006.239.07:40:10.09#ibcon#about to read 4, iclass 11, count 2 2006.239.07:40:10.09#ibcon#read 4, iclass 11, count 2 2006.239.07:40:10.09#ibcon#about to read 5, iclass 11, count 2 2006.239.07:40:10.09#ibcon#read 5, iclass 11, count 2 2006.239.07:40:10.09#ibcon#about to read 6, iclass 11, count 2 2006.239.07:40:10.09#ibcon#read 6, iclass 11, count 2 2006.239.07:40:10.09#ibcon#end of sib2, iclass 11, count 2 2006.239.07:40:10.09#ibcon#*mode == 0, iclass 11, count 2 2006.239.07:40:10.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.07:40:10.09#ibcon#[25=AT07-07\r\n] 2006.239.07:40:10.09#ibcon#*before write, iclass 11, count 2 2006.239.07:40:10.09#ibcon#enter sib2, iclass 11, count 2 2006.239.07:40:10.09#ibcon#flushed, iclass 11, count 2 2006.239.07:40:10.09#ibcon#about to write, iclass 11, count 2 2006.239.07:40:10.09#ibcon#wrote, iclass 11, count 2 2006.239.07:40:10.09#ibcon#about to read 3, iclass 11, count 2 2006.239.07:40:10.12#ibcon#read 3, iclass 11, count 2 2006.239.07:40:10.12#ibcon#about to read 4, iclass 11, count 2 2006.239.07:40:10.12#ibcon#read 4, iclass 11, count 2 2006.239.07:40:10.12#ibcon#about to read 5, iclass 11, count 2 2006.239.07:40:10.12#ibcon#read 5, iclass 11, count 2 2006.239.07:40:10.12#ibcon#about to read 6, iclass 11, count 2 2006.239.07:40:10.12#ibcon#read 6, iclass 11, count 2 2006.239.07:40:10.12#ibcon#end of sib2, iclass 11, count 2 2006.239.07:40:10.12#ibcon#*after write, iclass 11, count 2 2006.239.07:40:10.12#ibcon#*before return 0, iclass 11, count 2 2006.239.07:40:10.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:40:10.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:40:10.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.07:40:10.12#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:10.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:40:10.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:40:10.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:40:10.24#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:40:10.24#ibcon#first serial, iclass 11, count 0 2006.239.07:40:10.24#ibcon#enter sib2, iclass 11, count 0 2006.239.07:40:10.24#ibcon#flushed, iclass 11, count 0 2006.239.07:40:10.24#ibcon#about to write, iclass 11, count 0 2006.239.07:40:10.24#ibcon#wrote, iclass 11, count 0 2006.239.07:40:10.24#ibcon#about to read 3, iclass 11, count 0 2006.239.07:40:10.26#ibcon#read 3, iclass 11, count 0 2006.239.07:40:10.26#ibcon#about to read 4, iclass 11, count 0 2006.239.07:40:10.26#ibcon#read 4, iclass 11, count 0 2006.239.07:40:10.26#ibcon#about to read 5, iclass 11, count 0 2006.239.07:40:10.26#ibcon#read 5, iclass 11, count 0 2006.239.07:40:10.26#ibcon#about to read 6, iclass 11, count 0 2006.239.07:40:10.26#ibcon#read 6, iclass 11, count 0 2006.239.07:40:10.26#ibcon#end of sib2, iclass 11, count 0 2006.239.07:40:10.26#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:40:10.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:40:10.26#ibcon#[25=USB\r\n] 2006.239.07:40:10.26#ibcon#*before write, iclass 11, count 0 2006.239.07:40:10.26#ibcon#enter sib2, iclass 11, count 0 2006.239.07:40:10.26#ibcon#flushed, iclass 11, count 0 2006.239.07:40:10.26#ibcon#about to write, iclass 11, count 0 2006.239.07:40:10.26#ibcon#wrote, iclass 11, count 0 2006.239.07:40:10.26#ibcon#about to read 3, iclass 11, count 0 2006.239.07:40:10.29#ibcon#read 3, iclass 11, count 0 2006.239.07:40:10.29#ibcon#about to read 4, iclass 11, count 0 2006.239.07:40:10.29#ibcon#read 4, iclass 11, count 0 2006.239.07:40:10.29#ibcon#about to read 5, iclass 11, count 0 2006.239.07:40:10.29#ibcon#read 5, iclass 11, count 0 2006.239.07:40:10.29#ibcon#about to read 6, iclass 11, count 0 2006.239.07:40:10.29#ibcon#read 6, iclass 11, count 0 2006.239.07:40:10.29#ibcon#end of sib2, iclass 11, count 0 2006.239.07:40:10.29#ibcon#*after write, iclass 11, count 0 2006.239.07:40:10.29#ibcon#*before return 0, iclass 11, count 0 2006.239.07:40:10.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:40:10.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:40:10.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:40:10.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:40:10.29$vc4f8/valo=8,852.99 2006.239.07:40:10.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.07:40:10.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.07:40:10.29#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:10.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:40:10.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:40:10.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:40:10.29#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:40:10.29#ibcon#first serial, iclass 13, count 0 2006.239.07:40:10.29#ibcon#enter sib2, iclass 13, count 0 2006.239.07:40:10.29#ibcon#flushed, iclass 13, count 0 2006.239.07:40:10.29#ibcon#about to write, iclass 13, count 0 2006.239.07:40:10.29#ibcon#wrote, iclass 13, count 0 2006.239.07:40:10.29#ibcon#about to read 3, iclass 13, count 0 2006.239.07:40:10.31#ibcon#read 3, iclass 13, count 0 2006.239.07:40:10.31#ibcon#about to read 4, iclass 13, count 0 2006.239.07:40:10.31#ibcon#read 4, iclass 13, count 0 2006.239.07:40:10.31#ibcon#about to read 5, iclass 13, count 0 2006.239.07:40:10.31#ibcon#read 5, iclass 13, count 0 2006.239.07:40:10.31#ibcon#about to read 6, iclass 13, count 0 2006.239.07:40:10.31#ibcon#read 6, iclass 13, count 0 2006.239.07:40:10.31#ibcon#end of sib2, iclass 13, count 0 2006.239.07:40:10.31#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:40:10.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:40:10.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:40:10.31#ibcon#*before write, iclass 13, count 0 2006.239.07:40:10.31#ibcon#enter sib2, iclass 13, count 0 2006.239.07:40:10.31#ibcon#flushed, iclass 13, count 0 2006.239.07:40:10.31#ibcon#about to write, iclass 13, count 0 2006.239.07:40:10.31#ibcon#wrote, iclass 13, count 0 2006.239.07:40:10.31#ibcon#about to read 3, iclass 13, count 0 2006.239.07:40:10.35#ibcon#read 3, iclass 13, count 0 2006.239.07:40:10.35#ibcon#about to read 4, iclass 13, count 0 2006.239.07:40:10.35#ibcon#read 4, iclass 13, count 0 2006.239.07:40:10.35#ibcon#about to read 5, iclass 13, count 0 2006.239.07:40:10.35#ibcon#read 5, iclass 13, count 0 2006.239.07:40:10.35#ibcon#about to read 6, iclass 13, count 0 2006.239.07:40:10.35#ibcon#read 6, iclass 13, count 0 2006.239.07:40:10.35#ibcon#end of sib2, iclass 13, count 0 2006.239.07:40:10.35#ibcon#*after write, iclass 13, count 0 2006.239.07:40:10.35#ibcon#*before return 0, iclass 13, count 0 2006.239.07:40:10.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:40:10.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:40:10.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:40:10.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:40:10.35$vc4f8/va=8,7 2006.239.07:40:10.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.07:40:10.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.07:40:10.35#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:10.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:40:10.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:40:10.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:40:10.41#ibcon#enter wrdev, iclass 15, count 2 2006.239.07:40:10.41#ibcon#first serial, iclass 15, count 2 2006.239.07:40:10.41#ibcon#enter sib2, iclass 15, count 2 2006.239.07:40:10.41#ibcon#flushed, iclass 15, count 2 2006.239.07:40:10.41#ibcon#about to write, iclass 15, count 2 2006.239.07:40:10.41#ibcon#wrote, iclass 15, count 2 2006.239.07:40:10.41#ibcon#about to read 3, iclass 15, count 2 2006.239.07:40:10.43#ibcon#read 3, iclass 15, count 2 2006.239.07:40:10.43#ibcon#about to read 4, iclass 15, count 2 2006.239.07:40:10.43#ibcon#read 4, iclass 15, count 2 2006.239.07:40:10.43#ibcon#about to read 5, iclass 15, count 2 2006.239.07:40:10.43#ibcon#read 5, iclass 15, count 2 2006.239.07:40:10.43#ibcon#about to read 6, iclass 15, count 2 2006.239.07:40:10.43#ibcon#read 6, iclass 15, count 2 2006.239.07:40:10.43#ibcon#end of sib2, iclass 15, count 2 2006.239.07:40:10.43#ibcon#*mode == 0, iclass 15, count 2 2006.239.07:40:10.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.07:40:10.43#ibcon#[25=AT08-07\r\n] 2006.239.07:40:10.43#ibcon#*before write, iclass 15, count 2 2006.239.07:40:10.43#ibcon#enter sib2, iclass 15, count 2 2006.239.07:40:10.43#ibcon#flushed, iclass 15, count 2 2006.239.07:40:10.43#ibcon#about to write, iclass 15, count 2 2006.239.07:40:10.43#ibcon#wrote, iclass 15, count 2 2006.239.07:40:10.43#ibcon#about to read 3, iclass 15, count 2 2006.239.07:40:10.46#ibcon#read 3, iclass 15, count 2 2006.239.07:40:10.46#ibcon#about to read 4, iclass 15, count 2 2006.239.07:40:10.46#ibcon#read 4, iclass 15, count 2 2006.239.07:40:10.46#ibcon#about to read 5, iclass 15, count 2 2006.239.07:40:10.46#ibcon#read 5, iclass 15, count 2 2006.239.07:40:10.46#ibcon#about to read 6, iclass 15, count 2 2006.239.07:40:10.46#ibcon#read 6, iclass 15, count 2 2006.239.07:40:10.46#ibcon#end of sib2, iclass 15, count 2 2006.239.07:40:10.46#ibcon#*after write, iclass 15, count 2 2006.239.07:40:10.46#ibcon#*before return 0, iclass 15, count 2 2006.239.07:40:10.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:40:10.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:40:10.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.07:40:10.46#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:10.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:40:10.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:40:10.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:40:10.58#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:40:10.58#ibcon#first serial, iclass 15, count 0 2006.239.07:40:10.58#ibcon#enter sib2, iclass 15, count 0 2006.239.07:40:10.58#ibcon#flushed, iclass 15, count 0 2006.239.07:40:10.58#ibcon#about to write, iclass 15, count 0 2006.239.07:40:10.58#ibcon#wrote, iclass 15, count 0 2006.239.07:40:10.58#ibcon#about to read 3, iclass 15, count 0 2006.239.07:40:10.60#ibcon#read 3, iclass 15, count 0 2006.239.07:40:10.60#ibcon#about to read 4, iclass 15, count 0 2006.239.07:40:10.60#ibcon#read 4, iclass 15, count 0 2006.239.07:40:10.60#ibcon#about to read 5, iclass 15, count 0 2006.239.07:40:10.60#ibcon#read 5, iclass 15, count 0 2006.239.07:40:10.60#ibcon#about to read 6, iclass 15, count 0 2006.239.07:40:10.60#ibcon#read 6, iclass 15, count 0 2006.239.07:40:10.60#ibcon#end of sib2, iclass 15, count 0 2006.239.07:40:10.60#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:40:10.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:40:10.60#ibcon#[25=USB\r\n] 2006.239.07:40:10.60#ibcon#*before write, iclass 15, count 0 2006.239.07:40:10.60#ibcon#enter sib2, iclass 15, count 0 2006.239.07:40:10.60#ibcon#flushed, iclass 15, count 0 2006.239.07:40:10.60#ibcon#about to write, iclass 15, count 0 2006.239.07:40:10.60#ibcon#wrote, iclass 15, count 0 2006.239.07:40:10.60#ibcon#about to read 3, iclass 15, count 0 2006.239.07:40:10.63#ibcon#read 3, iclass 15, count 0 2006.239.07:40:10.63#ibcon#about to read 4, iclass 15, count 0 2006.239.07:40:10.63#ibcon#read 4, iclass 15, count 0 2006.239.07:40:10.63#ibcon#about to read 5, iclass 15, count 0 2006.239.07:40:10.63#ibcon#read 5, iclass 15, count 0 2006.239.07:40:10.63#ibcon#about to read 6, iclass 15, count 0 2006.239.07:40:10.63#ibcon#read 6, iclass 15, count 0 2006.239.07:40:10.63#ibcon#end of sib2, iclass 15, count 0 2006.239.07:40:10.63#ibcon#*after write, iclass 15, count 0 2006.239.07:40:10.63#ibcon#*before return 0, iclass 15, count 0 2006.239.07:40:10.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:40:10.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:40:10.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:40:10.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:40:10.63$vc4f8/vblo=1,632.99 2006.239.07:40:10.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.07:40:10.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.07:40:10.63#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:10.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:40:10.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:40:10.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:40:10.63#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:40:10.63#ibcon#first serial, iclass 17, count 0 2006.239.07:40:10.63#ibcon#enter sib2, iclass 17, count 0 2006.239.07:40:10.63#ibcon#flushed, iclass 17, count 0 2006.239.07:40:10.63#ibcon#about to write, iclass 17, count 0 2006.239.07:40:10.63#ibcon#wrote, iclass 17, count 0 2006.239.07:40:10.63#ibcon#about to read 3, iclass 17, count 0 2006.239.07:40:10.65#ibcon#read 3, iclass 17, count 0 2006.239.07:40:10.65#ibcon#about to read 4, iclass 17, count 0 2006.239.07:40:10.65#ibcon#read 4, iclass 17, count 0 2006.239.07:40:10.65#ibcon#about to read 5, iclass 17, count 0 2006.239.07:40:10.65#ibcon#read 5, iclass 17, count 0 2006.239.07:40:10.65#ibcon#about to read 6, iclass 17, count 0 2006.239.07:40:10.65#ibcon#read 6, iclass 17, count 0 2006.239.07:40:10.65#ibcon#end of sib2, iclass 17, count 0 2006.239.07:40:10.65#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:40:10.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:40:10.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:40:10.65#ibcon#*before write, iclass 17, count 0 2006.239.07:40:10.65#ibcon#enter sib2, iclass 17, count 0 2006.239.07:40:10.65#ibcon#flushed, iclass 17, count 0 2006.239.07:40:10.65#ibcon#about to write, iclass 17, count 0 2006.239.07:40:10.65#ibcon#wrote, iclass 17, count 0 2006.239.07:40:10.65#ibcon#about to read 3, iclass 17, count 0 2006.239.07:40:10.69#ibcon#read 3, iclass 17, count 0 2006.239.07:40:10.69#ibcon#about to read 4, iclass 17, count 0 2006.239.07:40:10.69#ibcon#read 4, iclass 17, count 0 2006.239.07:40:10.69#ibcon#about to read 5, iclass 17, count 0 2006.239.07:40:10.69#ibcon#read 5, iclass 17, count 0 2006.239.07:40:10.69#ibcon#about to read 6, iclass 17, count 0 2006.239.07:40:10.69#ibcon#read 6, iclass 17, count 0 2006.239.07:40:10.69#ibcon#end of sib2, iclass 17, count 0 2006.239.07:40:10.69#ibcon#*after write, iclass 17, count 0 2006.239.07:40:10.69#ibcon#*before return 0, iclass 17, count 0 2006.239.07:40:10.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:40:10.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:40:10.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:40:10.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:40:10.69$vc4f8/vb=1,4 2006.239.07:40:10.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.07:40:10.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.07:40:10.69#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:10.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:40:10.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:40:10.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:40:10.69#ibcon#enter wrdev, iclass 19, count 2 2006.239.07:40:10.69#ibcon#first serial, iclass 19, count 2 2006.239.07:40:10.69#ibcon#enter sib2, iclass 19, count 2 2006.239.07:40:10.69#ibcon#flushed, iclass 19, count 2 2006.239.07:40:10.69#ibcon#about to write, iclass 19, count 2 2006.239.07:40:10.69#ibcon#wrote, iclass 19, count 2 2006.239.07:40:10.69#ibcon#about to read 3, iclass 19, count 2 2006.239.07:40:10.71#ibcon#read 3, iclass 19, count 2 2006.239.07:40:10.71#ibcon#about to read 4, iclass 19, count 2 2006.239.07:40:10.71#ibcon#read 4, iclass 19, count 2 2006.239.07:40:10.71#ibcon#about to read 5, iclass 19, count 2 2006.239.07:40:10.71#ibcon#read 5, iclass 19, count 2 2006.239.07:40:10.71#ibcon#about to read 6, iclass 19, count 2 2006.239.07:40:10.71#ibcon#read 6, iclass 19, count 2 2006.239.07:40:10.71#ibcon#end of sib2, iclass 19, count 2 2006.239.07:40:10.71#ibcon#*mode == 0, iclass 19, count 2 2006.239.07:40:10.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.07:40:10.71#ibcon#[27=AT01-04\r\n] 2006.239.07:40:10.71#ibcon#*before write, iclass 19, count 2 2006.239.07:40:10.71#ibcon#enter sib2, iclass 19, count 2 2006.239.07:40:10.71#ibcon#flushed, iclass 19, count 2 2006.239.07:40:10.71#ibcon#about to write, iclass 19, count 2 2006.239.07:40:10.71#ibcon#wrote, iclass 19, count 2 2006.239.07:40:10.71#ibcon#about to read 3, iclass 19, count 2 2006.239.07:40:10.74#ibcon#read 3, iclass 19, count 2 2006.239.07:40:10.74#ibcon#about to read 4, iclass 19, count 2 2006.239.07:40:10.74#ibcon#read 4, iclass 19, count 2 2006.239.07:40:10.74#ibcon#about to read 5, iclass 19, count 2 2006.239.07:40:10.74#ibcon#read 5, iclass 19, count 2 2006.239.07:40:10.74#ibcon#about to read 6, iclass 19, count 2 2006.239.07:40:10.74#ibcon#read 6, iclass 19, count 2 2006.239.07:40:10.74#ibcon#end of sib2, iclass 19, count 2 2006.239.07:40:10.74#ibcon#*after write, iclass 19, count 2 2006.239.07:40:10.74#ibcon#*before return 0, iclass 19, count 2 2006.239.07:40:10.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:40:10.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:40:10.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.07:40:10.74#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:10.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:40:10.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:40:10.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:40:10.86#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:40:10.86#ibcon#first serial, iclass 19, count 0 2006.239.07:40:10.86#ibcon#enter sib2, iclass 19, count 0 2006.239.07:40:10.86#ibcon#flushed, iclass 19, count 0 2006.239.07:40:10.86#ibcon#about to write, iclass 19, count 0 2006.239.07:40:10.86#ibcon#wrote, iclass 19, count 0 2006.239.07:40:10.86#ibcon#about to read 3, iclass 19, count 0 2006.239.07:40:10.88#ibcon#read 3, iclass 19, count 0 2006.239.07:40:10.88#ibcon#about to read 4, iclass 19, count 0 2006.239.07:40:10.88#ibcon#read 4, iclass 19, count 0 2006.239.07:40:10.88#ibcon#about to read 5, iclass 19, count 0 2006.239.07:40:10.88#ibcon#read 5, iclass 19, count 0 2006.239.07:40:10.88#ibcon#about to read 6, iclass 19, count 0 2006.239.07:40:10.88#ibcon#read 6, iclass 19, count 0 2006.239.07:40:10.88#ibcon#end of sib2, iclass 19, count 0 2006.239.07:40:10.88#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:40:10.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:40:10.88#ibcon#[27=USB\r\n] 2006.239.07:40:10.88#ibcon#*before write, iclass 19, count 0 2006.239.07:40:10.88#ibcon#enter sib2, iclass 19, count 0 2006.239.07:40:10.88#ibcon#flushed, iclass 19, count 0 2006.239.07:40:10.88#ibcon#about to write, iclass 19, count 0 2006.239.07:40:10.88#ibcon#wrote, iclass 19, count 0 2006.239.07:40:10.88#ibcon#about to read 3, iclass 19, count 0 2006.239.07:40:10.91#ibcon#read 3, iclass 19, count 0 2006.239.07:40:10.91#ibcon#about to read 4, iclass 19, count 0 2006.239.07:40:10.91#ibcon#read 4, iclass 19, count 0 2006.239.07:40:10.91#ibcon#about to read 5, iclass 19, count 0 2006.239.07:40:10.91#ibcon#read 5, iclass 19, count 0 2006.239.07:40:10.91#ibcon#about to read 6, iclass 19, count 0 2006.239.07:40:10.91#ibcon#read 6, iclass 19, count 0 2006.239.07:40:10.91#ibcon#end of sib2, iclass 19, count 0 2006.239.07:40:10.91#ibcon#*after write, iclass 19, count 0 2006.239.07:40:10.91#ibcon#*before return 0, iclass 19, count 0 2006.239.07:40:10.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:40:10.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:40:10.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:40:10.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:40:10.91$vc4f8/vblo=2,640.99 2006.239.07:40:10.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.07:40:10.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.07:40:10.91#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:10.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:10.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:10.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:10.91#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:40:10.91#ibcon#first serial, iclass 21, count 0 2006.239.07:40:10.91#ibcon#enter sib2, iclass 21, count 0 2006.239.07:40:10.91#ibcon#flushed, iclass 21, count 0 2006.239.07:40:10.91#ibcon#about to write, iclass 21, count 0 2006.239.07:40:10.91#ibcon#wrote, iclass 21, count 0 2006.239.07:40:10.91#ibcon#about to read 3, iclass 21, count 0 2006.239.07:40:10.93#ibcon#read 3, iclass 21, count 0 2006.239.07:40:10.93#ibcon#about to read 4, iclass 21, count 0 2006.239.07:40:10.93#ibcon#read 4, iclass 21, count 0 2006.239.07:40:10.93#ibcon#about to read 5, iclass 21, count 0 2006.239.07:40:10.93#ibcon#read 5, iclass 21, count 0 2006.239.07:40:10.93#ibcon#about to read 6, iclass 21, count 0 2006.239.07:40:10.93#ibcon#read 6, iclass 21, count 0 2006.239.07:40:10.93#ibcon#end of sib2, iclass 21, count 0 2006.239.07:40:10.93#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:40:10.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:40:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:40:10.93#ibcon#*before write, iclass 21, count 0 2006.239.07:40:10.93#ibcon#enter sib2, iclass 21, count 0 2006.239.07:40:10.93#ibcon#flushed, iclass 21, count 0 2006.239.07:40:10.93#ibcon#about to write, iclass 21, count 0 2006.239.07:40:10.93#ibcon#wrote, iclass 21, count 0 2006.239.07:40:10.93#ibcon#about to read 3, iclass 21, count 0 2006.239.07:40:10.97#ibcon#read 3, iclass 21, count 0 2006.239.07:40:10.97#ibcon#about to read 4, iclass 21, count 0 2006.239.07:40:10.97#ibcon#read 4, iclass 21, count 0 2006.239.07:40:10.97#ibcon#about to read 5, iclass 21, count 0 2006.239.07:40:10.97#ibcon#read 5, iclass 21, count 0 2006.239.07:40:10.97#ibcon#about to read 6, iclass 21, count 0 2006.239.07:40:10.97#ibcon#read 6, iclass 21, count 0 2006.239.07:40:10.97#ibcon#end of sib2, iclass 21, count 0 2006.239.07:40:10.97#ibcon#*after write, iclass 21, count 0 2006.239.07:40:10.97#ibcon#*before return 0, iclass 21, count 0 2006.239.07:40:10.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:10.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:40:10.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:40:10.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:40:10.97$vc4f8/vb=2,4 2006.239.07:40:10.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.07:40:10.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.07:40:10.97#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:10.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:11.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:11.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:11.03#ibcon#enter wrdev, iclass 23, count 2 2006.239.07:40:11.03#ibcon#first serial, iclass 23, count 2 2006.239.07:40:11.03#ibcon#enter sib2, iclass 23, count 2 2006.239.07:40:11.03#ibcon#flushed, iclass 23, count 2 2006.239.07:40:11.03#ibcon#about to write, iclass 23, count 2 2006.239.07:40:11.03#ibcon#wrote, iclass 23, count 2 2006.239.07:40:11.03#ibcon#about to read 3, iclass 23, count 2 2006.239.07:40:11.05#ibcon#read 3, iclass 23, count 2 2006.239.07:40:11.05#ibcon#about to read 4, iclass 23, count 2 2006.239.07:40:11.05#ibcon#read 4, iclass 23, count 2 2006.239.07:40:11.05#ibcon#about to read 5, iclass 23, count 2 2006.239.07:40:11.05#ibcon#read 5, iclass 23, count 2 2006.239.07:40:11.05#ibcon#about to read 6, iclass 23, count 2 2006.239.07:40:11.05#ibcon#read 6, iclass 23, count 2 2006.239.07:40:11.05#ibcon#end of sib2, iclass 23, count 2 2006.239.07:40:11.05#ibcon#*mode == 0, iclass 23, count 2 2006.239.07:40:11.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.07:40:11.05#ibcon#[27=AT02-04\r\n] 2006.239.07:40:11.05#ibcon#*before write, iclass 23, count 2 2006.239.07:40:11.05#ibcon#enter sib2, iclass 23, count 2 2006.239.07:40:11.05#ibcon#flushed, iclass 23, count 2 2006.239.07:40:11.05#ibcon#about to write, iclass 23, count 2 2006.239.07:40:11.05#ibcon#wrote, iclass 23, count 2 2006.239.07:40:11.05#ibcon#about to read 3, iclass 23, count 2 2006.239.07:40:11.08#ibcon#read 3, iclass 23, count 2 2006.239.07:40:11.08#ibcon#about to read 4, iclass 23, count 2 2006.239.07:40:11.08#ibcon#read 4, iclass 23, count 2 2006.239.07:40:11.08#ibcon#about to read 5, iclass 23, count 2 2006.239.07:40:11.08#ibcon#read 5, iclass 23, count 2 2006.239.07:40:11.08#ibcon#about to read 6, iclass 23, count 2 2006.239.07:40:11.08#ibcon#read 6, iclass 23, count 2 2006.239.07:40:11.08#ibcon#end of sib2, iclass 23, count 2 2006.239.07:40:11.08#ibcon#*after write, iclass 23, count 2 2006.239.07:40:11.08#ibcon#*before return 0, iclass 23, count 2 2006.239.07:40:11.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:11.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:40:11.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.07:40:11.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:11.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:11.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:11.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:11.20#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:40:11.20#ibcon#first serial, iclass 23, count 0 2006.239.07:40:11.20#ibcon#enter sib2, iclass 23, count 0 2006.239.07:40:11.20#ibcon#flushed, iclass 23, count 0 2006.239.07:40:11.20#ibcon#about to write, iclass 23, count 0 2006.239.07:40:11.20#ibcon#wrote, iclass 23, count 0 2006.239.07:40:11.20#ibcon#about to read 3, iclass 23, count 0 2006.239.07:40:11.22#ibcon#read 3, iclass 23, count 0 2006.239.07:40:11.22#ibcon#about to read 4, iclass 23, count 0 2006.239.07:40:11.22#ibcon#read 4, iclass 23, count 0 2006.239.07:40:11.22#ibcon#about to read 5, iclass 23, count 0 2006.239.07:40:11.22#ibcon#read 5, iclass 23, count 0 2006.239.07:40:11.22#ibcon#about to read 6, iclass 23, count 0 2006.239.07:40:11.22#ibcon#read 6, iclass 23, count 0 2006.239.07:40:11.22#ibcon#end of sib2, iclass 23, count 0 2006.239.07:40:11.22#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:40:11.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:40:11.22#ibcon#[27=USB\r\n] 2006.239.07:40:11.22#ibcon#*before write, iclass 23, count 0 2006.239.07:40:11.22#ibcon#enter sib2, iclass 23, count 0 2006.239.07:40:11.22#ibcon#flushed, iclass 23, count 0 2006.239.07:40:11.22#ibcon#about to write, iclass 23, count 0 2006.239.07:40:11.22#ibcon#wrote, iclass 23, count 0 2006.239.07:40:11.22#ibcon#about to read 3, iclass 23, count 0 2006.239.07:40:11.25#ibcon#read 3, iclass 23, count 0 2006.239.07:40:11.25#ibcon#about to read 4, iclass 23, count 0 2006.239.07:40:11.25#ibcon#read 4, iclass 23, count 0 2006.239.07:40:11.25#ibcon#about to read 5, iclass 23, count 0 2006.239.07:40:11.25#ibcon#read 5, iclass 23, count 0 2006.239.07:40:11.25#ibcon#about to read 6, iclass 23, count 0 2006.239.07:40:11.25#ibcon#read 6, iclass 23, count 0 2006.239.07:40:11.25#ibcon#end of sib2, iclass 23, count 0 2006.239.07:40:11.25#ibcon#*after write, iclass 23, count 0 2006.239.07:40:11.25#ibcon#*before return 0, iclass 23, count 0 2006.239.07:40:11.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:11.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:40:11.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:40:11.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:40:11.25$vc4f8/vblo=3,656.99 2006.239.07:40:11.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:40:11.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:40:11.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:11.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:11.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:11.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:11.25#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:40:11.25#ibcon#first serial, iclass 25, count 0 2006.239.07:40:11.25#ibcon#enter sib2, iclass 25, count 0 2006.239.07:40:11.25#ibcon#flushed, iclass 25, count 0 2006.239.07:40:11.25#ibcon#about to write, iclass 25, count 0 2006.239.07:40:11.25#ibcon#wrote, iclass 25, count 0 2006.239.07:40:11.25#ibcon#about to read 3, iclass 25, count 0 2006.239.07:40:11.27#ibcon#read 3, iclass 25, count 0 2006.239.07:40:11.27#ibcon#about to read 4, iclass 25, count 0 2006.239.07:40:11.27#ibcon#read 4, iclass 25, count 0 2006.239.07:40:11.27#ibcon#about to read 5, iclass 25, count 0 2006.239.07:40:11.27#ibcon#read 5, iclass 25, count 0 2006.239.07:40:11.27#ibcon#about to read 6, iclass 25, count 0 2006.239.07:40:11.27#ibcon#read 6, iclass 25, count 0 2006.239.07:40:11.27#ibcon#end of sib2, iclass 25, count 0 2006.239.07:40:11.27#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:40:11.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:40:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:40:11.27#ibcon#*before write, iclass 25, count 0 2006.239.07:40:11.27#ibcon#enter sib2, iclass 25, count 0 2006.239.07:40:11.27#ibcon#flushed, iclass 25, count 0 2006.239.07:40:11.27#ibcon#about to write, iclass 25, count 0 2006.239.07:40:11.27#ibcon#wrote, iclass 25, count 0 2006.239.07:40:11.27#ibcon#about to read 3, iclass 25, count 0 2006.239.07:40:11.31#ibcon#read 3, iclass 25, count 0 2006.239.07:40:11.31#ibcon#about to read 4, iclass 25, count 0 2006.239.07:40:11.31#ibcon#read 4, iclass 25, count 0 2006.239.07:40:11.31#ibcon#about to read 5, iclass 25, count 0 2006.239.07:40:11.31#ibcon#read 5, iclass 25, count 0 2006.239.07:40:11.31#ibcon#about to read 6, iclass 25, count 0 2006.239.07:40:11.31#ibcon#read 6, iclass 25, count 0 2006.239.07:40:11.31#ibcon#end of sib2, iclass 25, count 0 2006.239.07:40:11.31#ibcon#*after write, iclass 25, count 0 2006.239.07:40:11.31#ibcon#*before return 0, iclass 25, count 0 2006.239.07:40:11.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:11.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:40:11.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:40:11.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:40:11.31$vc4f8/vb=3,4 2006.239.07:40:11.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:40:11.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:40:11.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:11.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:11.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:11.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:11.37#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:40:11.37#ibcon#first serial, iclass 27, count 2 2006.239.07:40:11.37#ibcon#enter sib2, iclass 27, count 2 2006.239.07:40:11.37#ibcon#flushed, iclass 27, count 2 2006.239.07:40:11.37#ibcon#about to write, iclass 27, count 2 2006.239.07:40:11.37#ibcon#wrote, iclass 27, count 2 2006.239.07:40:11.37#ibcon#about to read 3, iclass 27, count 2 2006.239.07:40:11.39#ibcon#read 3, iclass 27, count 2 2006.239.07:40:11.39#ibcon#about to read 4, iclass 27, count 2 2006.239.07:40:11.39#ibcon#read 4, iclass 27, count 2 2006.239.07:40:11.39#ibcon#about to read 5, iclass 27, count 2 2006.239.07:40:11.39#ibcon#read 5, iclass 27, count 2 2006.239.07:40:11.39#ibcon#about to read 6, iclass 27, count 2 2006.239.07:40:11.39#ibcon#read 6, iclass 27, count 2 2006.239.07:40:11.39#ibcon#end of sib2, iclass 27, count 2 2006.239.07:40:11.39#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:40:11.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:40:11.39#ibcon#[27=AT03-04\r\n] 2006.239.07:40:11.39#ibcon#*before write, iclass 27, count 2 2006.239.07:40:11.39#ibcon#enter sib2, iclass 27, count 2 2006.239.07:40:11.39#ibcon#flushed, iclass 27, count 2 2006.239.07:40:11.39#ibcon#about to write, iclass 27, count 2 2006.239.07:40:11.39#ibcon#wrote, iclass 27, count 2 2006.239.07:40:11.39#ibcon#about to read 3, iclass 27, count 2 2006.239.07:40:11.42#ibcon#read 3, iclass 27, count 2 2006.239.07:40:11.42#ibcon#about to read 4, iclass 27, count 2 2006.239.07:40:11.42#ibcon#read 4, iclass 27, count 2 2006.239.07:40:11.42#ibcon#about to read 5, iclass 27, count 2 2006.239.07:40:11.42#ibcon#read 5, iclass 27, count 2 2006.239.07:40:11.42#ibcon#about to read 6, iclass 27, count 2 2006.239.07:40:11.42#ibcon#read 6, iclass 27, count 2 2006.239.07:40:11.42#ibcon#end of sib2, iclass 27, count 2 2006.239.07:40:11.42#ibcon#*after write, iclass 27, count 2 2006.239.07:40:11.42#ibcon#*before return 0, iclass 27, count 2 2006.239.07:40:11.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:11.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:40:11.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:40:11.42#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:11.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:11.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:11.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:11.54#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:40:11.54#ibcon#first serial, iclass 27, count 0 2006.239.07:40:11.54#ibcon#enter sib2, iclass 27, count 0 2006.239.07:40:11.54#ibcon#flushed, iclass 27, count 0 2006.239.07:40:11.54#ibcon#about to write, iclass 27, count 0 2006.239.07:40:11.54#ibcon#wrote, iclass 27, count 0 2006.239.07:40:11.54#ibcon#about to read 3, iclass 27, count 0 2006.239.07:40:11.56#ibcon#read 3, iclass 27, count 0 2006.239.07:40:11.56#ibcon#about to read 4, iclass 27, count 0 2006.239.07:40:11.56#ibcon#read 4, iclass 27, count 0 2006.239.07:40:11.56#ibcon#about to read 5, iclass 27, count 0 2006.239.07:40:11.56#ibcon#read 5, iclass 27, count 0 2006.239.07:40:11.56#ibcon#about to read 6, iclass 27, count 0 2006.239.07:40:11.56#ibcon#read 6, iclass 27, count 0 2006.239.07:40:11.56#ibcon#end of sib2, iclass 27, count 0 2006.239.07:40:11.56#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:40:11.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:40:11.56#ibcon#[27=USB\r\n] 2006.239.07:40:11.56#ibcon#*before write, iclass 27, count 0 2006.239.07:40:11.56#ibcon#enter sib2, iclass 27, count 0 2006.239.07:40:11.56#ibcon#flushed, iclass 27, count 0 2006.239.07:40:11.56#ibcon#about to write, iclass 27, count 0 2006.239.07:40:11.56#ibcon#wrote, iclass 27, count 0 2006.239.07:40:11.56#ibcon#about to read 3, iclass 27, count 0 2006.239.07:40:11.59#ibcon#read 3, iclass 27, count 0 2006.239.07:40:11.59#ibcon#about to read 4, iclass 27, count 0 2006.239.07:40:11.59#ibcon#read 4, iclass 27, count 0 2006.239.07:40:11.59#ibcon#about to read 5, iclass 27, count 0 2006.239.07:40:11.59#ibcon#read 5, iclass 27, count 0 2006.239.07:40:11.59#ibcon#about to read 6, iclass 27, count 0 2006.239.07:40:11.59#ibcon#read 6, iclass 27, count 0 2006.239.07:40:11.59#ibcon#end of sib2, iclass 27, count 0 2006.239.07:40:11.59#ibcon#*after write, iclass 27, count 0 2006.239.07:40:11.59#ibcon#*before return 0, iclass 27, count 0 2006.239.07:40:11.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:11.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:40:11.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:40:11.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:40:11.59$vc4f8/vblo=4,712.99 2006.239.07:40:11.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:40:11.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:40:11.59#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:11.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:11.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:11.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:11.59#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:40:11.59#ibcon#first serial, iclass 29, count 0 2006.239.07:40:11.59#ibcon#enter sib2, iclass 29, count 0 2006.239.07:40:11.59#ibcon#flushed, iclass 29, count 0 2006.239.07:40:11.59#ibcon#about to write, iclass 29, count 0 2006.239.07:40:11.59#ibcon#wrote, iclass 29, count 0 2006.239.07:40:11.59#ibcon#about to read 3, iclass 29, count 0 2006.239.07:40:11.61#ibcon#read 3, iclass 29, count 0 2006.239.07:40:11.61#ibcon#about to read 4, iclass 29, count 0 2006.239.07:40:11.61#ibcon#read 4, iclass 29, count 0 2006.239.07:40:11.61#ibcon#about to read 5, iclass 29, count 0 2006.239.07:40:11.61#ibcon#read 5, iclass 29, count 0 2006.239.07:40:11.61#ibcon#about to read 6, iclass 29, count 0 2006.239.07:40:11.61#ibcon#read 6, iclass 29, count 0 2006.239.07:40:11.61#ibcon#end of sib2, iclass 29, count 0 2006.239.07:40:11.61#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:40:11.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:40:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:40:11.61#ibcon#*before write, iclass 29, count 0 2006.239.07:40:11.61#ibcon#enter sib2, iclass 29, count 0 2006.239.07:40:11.61#ibcon#flushed, iclass 29, count 0 2006.239.07:40:11.61#ibcon#about to write, iclass 29, count 0 2006.239.07:40:11.61#ibcon#wrote, iclass 29, count 0 2006.239.07:40:11.61#ibcon#about to read 3, iclass 29, count 0 2006.239.07:40:11.65#ibcon#read 3, iclass 29, count 0 2006.239.07:40:11.65#ibcon#about to read 4, iclass 29, count 0 2006.239.07:40:11.65#ibcon#read 4, iclass 29, count 0 2006.239.07:40:11.65#ibcon#about to read 5, iclass 29, count 0 2006.239.07:40:11.65#ibcon#read 5, iclass 29, count 0 2006.239.07:40:11.65#ibcon#about to read 6, iclass 29, count 0 2006.239.07:40:11.65#ibcon#read 6, iclass 29, count 0 2006.239.07:40:11.65#ibcon#end of sib2, iclass 29, count 0 2006.239.07:40:11.65#ibcon#*after write, iclass 29, count 0 2006.239.07:40:11.65#ibcon#*before return 0, iclass 29, count 0 2006.239.07:40:11.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:11.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:40:11.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:40:11.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:40:11.65$vc4f8/vb=4,4 2006.239.07:40:11.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:40:11.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:40:11.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:11.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:11.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:11.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:11.72#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:40:11.72#ibcon#first serial, iclass 31, count 2 2006.239.07:40:11.72#ibcon#enter sib2, iclass 31, count 2 2006.239.07:40:11.72#ibcon#flushed, iclass 31, count 2 2006.239.07:40:11.72#ibcon#about to write, iclass 31, count 2 2006.239.07:40:11.72#ibcon#wrote, iclass 31, count 2 2006.239.07:40:11.72#ibcon#about to read 3, iclass 31, count 2 2006.239.07:40:11.73#ibcon#read 3, iclass 31, count 2 2006.239.07:40:11.73#ibcon#about to read 4, iclass 31, count 2 2006.239.07:40:11.73#ibcon#read 4, iclass 31, count 2 2006.239.07:40:11.73#ibcon#about to read 5, iclass 31, count 2 2006.239.07:40:11.73#ibcon#read 5, iclass 31, count 2 2006.239.07:40:11.73#ibcon#about to read 6, iclass 31, count 2 2006.239.07:40:11.73#ibcon#read 6, iclass 31, count 2 2006.239.07:40:11.73#ibcon#end of sib2, iclass 31, count 2 2006.239.07:40:11.73#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:40:11.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:40:11.73#ibcon#[27=AT04-04\r\n] 2006.239.07:40:11.73#ibcon#*before write, iclass 31, count 2 2006.239.07:40:11.73#ibcon#enter sib2, iclass 31, count 2 2006.239.07:40:11.73#ibcon#flushed, iclass 31, count 2 2006.239.07:40:11.73#ibcon#about to write, iclass 31, count 2 2006.239.07:40:11.73#ibcon#wrote, iclass 31, count 2 2006.239.07:40:11.73#ibcon#about to read 3, iclass 31, count 2 2006.239.07:40:11.76#ibcon#read 3, iclass 31, count 2 2006.239.07:40:11.76#ibcon#about to read 4, iclass 31, count 2 2006.239.07:40:11.76#ibcon#read 4, iclass 31, count 2 2006.239.07:40:11.76#ibcon#about to read 5, iclass 31, count 2 2006.239.07:40:11.76#ibcon#read 5, iclass 31, count 2 2006.239.07:40:11.76#ibcon#about to read 6, iclass 31, count 2 2006.239.07:40:11.76#ibcon#read 6, iclass 31, count 2 2006.239.07:40:11.76#ibcon#end of sib2, iclass 31, count 2 2006.239.07:40:11.76#ibcon#*after write, iclass 31, count 2 2006.239.07:40:11.76#ibcon#*before return 0, iclass 31, count 2 2006.239.07:40:11.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:11.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:40:11.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:40:11.76#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:11.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:11.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:11.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:11.89#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:40:11.89#ibcon#first serial, iclass 31, count 0 2006.239.07:40:11.89#ibcon#enter sib2, iclass 31, count 0 2006.239.07:40:11.89#ibcon#flushed, iclass 31, count 0 2006.239.07:40:11.89#ibcon#about to write, iclass 31, count 0 2006.239.07:40:11.89#ibcon#wrote, iclass 31, count 0 2006.239.07:40:11.89#ibcon#about to read 3, iclass 31, count 0 2006.239.07:40:11.90#ibcon#read 3, iclass 31, count 0 2006.239.07:40:11.90#ibcon#about to read 4, iclass 31, count 0 2006.239.07:40:11.90#ibcon#read 4, iclass 31, count 0 2006.239.07:40:11.90#ibcon#about to read 5, iclass 31, count 0 2006.239.07:40:11.90#ibcon#read 5, iclass 31, count 0 2006.239.07:40:11.90#ibcon#about to read 6, iclass 31, count 0 2006.239.07:40:11.90#ibcon#read 6, iclass 31, count 0 2006.239.07:40:11.90#ibcon#end of sib2, iclass 31, count 0 2006.239.07:40:11.90#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:40:11.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:40:11.90#ibcon#[27=USB\r\n] 2006.239.07:40:11.90#ibcon#*before write, iclass 31, count 0 2006.239.07:40:11.90#ibcon#enter sib2, iclass 31, count 0 2006.239.07:40:11.90#ibcon#flushed, iclass 31, count 0 2006.239.07:40:11.90#ibcon#about to write, iclass 31, count 0 2006.239.07:40:11.90#ibcon#wrote, iclass 31, count 0 2006.239.07:40:11.90#ibcon#about to read 3, iclass 31, count 0 2006.239.07:40:11.93#ibcon#read 3, iclass 31, count 0 2006.239.07:40:11.93#ibcon#about to read 4, iclass 31, count 0 2006.239.07:40:11.93#ibcon#read 4, iclass 31, count 0 2006.239.07:40:11.93#ibcon#about to read 5, iclass 31, count 0 2006.239.07:40:11.93#ibcon#read 5, iclass 31, count 0 2006.239.07:40:11.93#ibcon#about to read 6, iclass 31, count 0 2006.239.07:40:11.93#ibcon#read 6, iclass 31, count 0 2006.239.07:40:11.93#ibcon#end of sib2, iclass 31, count 0 2006.239.07:40:11.93#ibcon#*after write, iclass 31, count 0 2006.239.07:40:11.93#ibcon#*before return 0, iclass 31, count 0 2006.239.07:40:11.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:11.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:40:11.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:40:11.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:40:11.93$vc4f8/vblo=5,744.99 2006.239.07:40:11.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:40:11.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:40:11.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:11.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:11.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:11.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:11.93#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:40:11.93#ibcon#first serial, iclass 33, count 0 2006.239.07:40:11.93#ibcon#enter sib2, iclass 33, count 0 2006.239.07:40:11.93#ibcon#flushed, iclass 33, count 0 2006.239.07:40:11.93#ibcon#about to write, iclass 33, count 0 2006.239.07:40:11.93#ibcon#wrote, iclass 33, count 0 2006.239.07:40:11.93#ibcon#about to read 3, iclass 33, count 0 2006.239.07:40:11.95#ibcon#read 3, iclass 33, count 0 2006.239.07:40:11.95#ibcon#about to read 4, iclass 33, count 0 2006.239.07:40:11.95#ibcon#read 4, iclass 33, count 0 2006.239.07:40:11.95#ibcon#about to read 5, iclass 33, count 0 2006.239.07:40:11.95#ibcon#read 5, iclass 33, count 0 2006.239.07:40:11.95#ibcon#about to read 6, iclass 33, count 0 2006.239.07:40:11.95#ibcon#read 6, iclass 33, count 0 2006.239.07:40:11.95#ibcon#end of sib2, iclass 33, count 0 2006.239.07:40:11.95#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:40:11.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:40:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:40:11.95#ibcon#*before write, iclass 33, count 0 2006.239.07:40:11.95#ibcon#enter sib2, iclass 33, count 0 2006.239.07:40:11.95#ibcon#flushed, iclass 33, count 0 2006.239.07:40:11.95#ibcon#about to write, iclass 33, count 0 2006.239.07:40:11.95#ibcon#wrote, iclass 33, count 0 2006.239.07:40:11.95#ibcon#about to read 3, iclass 33, count 0 2006.239.07:40:11.99#ibcon#read 3, iclass 33, count 0 2006.239.07:40:11.99#ibcon#about to read 4, iclass 33, count 0 2006.239.07:40:11.99#ibcon#read 4, iclass 33, count 0 2006.239.07:40:11.99#ibcon#about to read 5, iclass 33, count 0 2006.239.07:40:11.99#ibcon#read 5, iclass 33, count 0 2006.239.07:40:11.99#ibcon#about to read 6, iclass 33, count 0 2006.239.07:40:11.99#ibcon#read 6, iclass 33, count 0 2006.239.07:40:11.99#ibcon#end of sib2, iclass 33, count 0 2006.239.07:40:11.99#ibcon#*after write, iclass 33, count 0 2006.239.07:40:11.99#ibcon#*before return 0, iclass 33, count 0 2006.239.07:40:11.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:11.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:40:11.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:40:11.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:40:11.99$vc4f8/vb=5,4 2006.239.07:40:11.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:40:11.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:40:11.99#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:11.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:12.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:12.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:12.05#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:40:12.05#ibcon#first serial, iclass 35, count 2 2006.239.07:40:12.05#ibcon#enter sib2, iclass 35, count 2 2006.239.07:40:12.05#ibcon#flushed, iclass 35, count 2 2006.239.07:40:12.05#ibcon#about to write, iclass 35, count 2 2006.239.07:40:12.05#ibcon#wrote, iclass 35, count 2 2006.239.07:40:12.05#ibcon#about to read 3, iclass 35, count 2 2006.239.07:40:12.07#ibcon#read 3, iclass 35, count 2 2006.239.07:40:12.07#ibcon#about to read 4, iclass 35, count 2 2006.239.07:40:12.07#ibcon#read 4, iclass 35, count 2 2006.239.07:40:12.07#ibcon#about to read 5, iclass 35, count 2 2006.239.07:40:12.07#ibcon#read 5, iclass 35, count 2 2006.239.07:40:12.07#ibcon#about to read 6, iclass 35, count 2 2006.239.07:40:12.07#ibcon#read 6, iclass 35, count 2 2006.239.07:40:12.07#ibcon#end of sib2, iclass 35, count 2 2006.239.07:40:12.07#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:40:12.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:40:12.07#ibcon#[27=AT05-04\r\n] 2006.239.07:40:12.07#ibcon#*before write, iclass 35, count 2 2006.239.07:40:12.07#ibcon#enter sib2, iclass 35, count 2 2006.239.07:40:12.07#ibcon#flushed, iclass 35, count 2 2006.239.07:40:12.07#ibcon#about to write, iclass 35, count 2 2006.239.07:40:12.07#ibcon#wrote, iclass 35, count 2 2006.239.07:40:12.07#ibcon#about to read 3, iclass 35, count 2 2006.239.07:40:12.10#ibcon#read 3, iclass 35, count 2 2006.239.07:40:12.10#ibcon#about to read 4, iclass 35, count 2 2006.239.07:40:12.10#ibcon#read 4, iclass 35, count 2 2006.239.07:40:12.10#ibcon#about to read 5, iclass 35, count 2 2006.239.07:40:12.10#ibcon#read 5, iclass 35, count 2 2006.239.07:40:12.10#ibcon#about to read 6, iclass 35, count 2 2006.239.07:40:12.10#ibcon#read 6, iclass 35, count 2 2006.239.07:40:12.10#ibcon#end of sib2, iclass 35, count 2 2006.239.07:40:12.10#ibcon#*after write, iclass 35, count 2 2006.239.07:40:12.10#ibcon#*before return 0, iclass 35, count 2 2006.239.07:40:12.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:12.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:40:12.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:40:12.10#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:12.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:12.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:12.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:12.22#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:40:12.22#ibcon#first serial, iclass 35, count 0 2006.239.07:40:12.22#ibcon#enter sib2, iclass 35, count 0 2006.239.07:40:12.22#ibcon#flushed, iclass 35, count 0 2006.239.07:40:12.22#ibcon#about to write, iclass 35, count 0 2006.239.07:40:12.22#ibcon#wrote, iclass 35, count 0 2006.239.07:40:12.22#ibcon#about to read 3, iclass 35, count 0 2006.239.07:40:12.24#ibcon#read 3, iclass 35, count 0 2006.239.07:40:12.24#ibcon#about to read 4, iclass 35, count 0 2006.239.07:40:12.24#ibcon#read 4, iclass 35, count 0 2006.239.07:40:12.24#ibcon#about to read 5, iclass 35, count 0 2006.239.07:40:12.24#ibcon#read 5, iclass 35, count 0 2006.239.07:40:12.24#ibcon#about to read 6, iclass 35, count 0 2006.239.07:40:12.24#ibcon#read 6, iclass 35, count 0 2006.239.07:40:12.24#ibcon#end of sib2, iclass 35, count 0 2006.239.07:40:12.24#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:40:12.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:40:12.24#ibcon#[27=USB\r\n] 2006.239.07:40:12.24#ibcon#*before write, iclass 35, count 0 2006.239.07:40:12.24#ibcon#enter sib2, iclass 35, count 0 2006.239.07:40:12.24#ibcon#flushed, iclass 35, count 0 2006.239.07:40:12.24#ibcon#about to write, iclass 35, count 0 2006.239.07:40:12.24#ibcon#wrote, iclass 35, count 0 2006.239.07:40:12.24#ibcon#about to read 3, iclass 35, count 0 2006.239.07:40:12.27#ibcon#read 3, iclass 35, count 0 2006.239.07:40:12.27#ibcon#about to read 4, iclass 35, count 0 2006.239.07:40:12.27#ibcon#read 4, iclass 35, count 0 2006.239.07:40:12.27#ibcon#about to read 5, iclass 35, count 0 2006.239.07:40:12.27#ibcon#read 5, iclass 35, count 0 2006.239.07:40:12.27#ibcon#about to read 6, iclass 35, count 0 2006.239.07:40:12.27#ibcon#read 6, iclass 35, count 0 2006.239.07:40:12.27#ibcon#end of sib2, iclass 35, count 0 2006.239.07:40:12.27#ibcon#*after write, iclass 35, count 0 2006.239.07:40:12.27#ibcon#*before return 0, iclass 35, count 0 2006.239.07:40:12.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:12.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:40:12.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:40:12.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:40:12.27$vc4f8/vblo=6,752.99 2006.239.07:40:12.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:40:12.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:40:12.27#ibcon#ireg 17 cls_cnt 0 2006.239.07:40:12.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:12.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:12.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:12.27#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:40:12.27#ibcon#first serial, iclass 37, count 0 2006.239.07:40:12.27#ibcon#enter sib2, iclass 37, count 0 2006.239.07:40:12.27#ibcon#flushed, iclass 37, count 0 2006.239.07:40:12.27#ibcon#about to write, iclass 37, count 0 2006.239.07:40:12.27#ibcon#wrote, iclass 37, count 0 2006.239.07:40:12.27#ibcon#about to read 3, iclass 37, count 0 2006.239.07:40:12.29#ibcon#read 3, iclass 37, count 0 2006.239.07:40:12.29#ibcon#about to read 4, iclass 37, count 0 2006.239.07:40:12.29#ibcon#read 4, iclass 37, count 0 2006.239.07:40:12.29#ibcon#about to read 5, iclass 37, count 0 2006.239.07:40:12.29#ibcon#read 5, iclass 37, count 0 2006.239.07:40:12.29#ibcon#about to read 6, iclass 37, count 0 2006.239.07:40:12.29#ibcon#read 6, iclass 37, count 0 2006.239.07:40:12.29#ibcon#end of sib2, iclass 37, count 0 2006.239.07:40:12.29#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:40:12.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:40:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:40:12.29#ibcon#*before write, iclass 37, count 0 2006.239.07:40:12.29#ibcon#enter sib2, iclass 37, count 0 2006.239.07:40:12.29#ibcon#flushed, iclass 37, count 0 2006.239.07:40:12.29#ibcon#about to write, iclass 37, count 0 2006.239.07:40:12.29#ibcon#wrote, iclass 37, count 0 2006.239.07:40:12.29#ibcon#about to read 3, iclass 37, count 0 2006.239.07:40:12.33#ibcon#read 3, iclass 37, count 0 2006.239.07:40:12.33#ibcon#about to read 4, iclass 37, count 0 2006.239.07:40:12.33#ibcon#read 4, iclass 37, count 0 2006.239.07:40:12.33#ibcon#about to read 5, iclass 37, count 0 2006.239.07:40:12.33#ibcon#read 5, iclass 37, count 0 2006.239.07:40:12.33#ibcon#about to read 6, iclass 37, count 0 2006.239.07:40:12.33#ibcon#read 6, iclass 37, count 0 2006.239.07:40:12.33#ibcon#end of sib2, iclass 37, count 0 2006.239.07:40:12.33#ibcon#*after write, iclass 37, count 0 2006.239.07:40:12.33#ibcon#*before return 0, iclass 37, count 0 2006.239.07:40:12.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:12.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:40:12.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:40:12.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:40:12.33$vc4f8/vb=6,4 2006.239.07:40:12.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:40:12.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:40:12.33#ibcon#ireg 11 cls_cnt 2 2006.239.07:40:12.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:12.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:12.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:12.39#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:40:12.39#ibcon#first serial, iclass 39, count 2 2006.239.07:40:12.39#ibcon#enter sib2, iclass 39, count 2 2006.239.07:40:12.39#ibcon#flushed, iclass 39, count 2 2006.239.07:40:12.39#ibcon#about to write, iclass 39, count 2 2006.239.07:40:12.39#ibcon#wrote, iclass 39, count 2 2006.239.07:40:12.39#ibcon#about to read 3, iclass 39, count 2 2006.239.07:40:12.41#ibcon#read 3, iclass 39, count 2 2006.239.07:40:12.41#ibcon#about to read 4, iclass 39, count 2 2006.239.07:40:12.41#ibcon#read 4, iclass 39, count 2 2006.239.07:40:12.41#ibcon#about to read 5, iclass 39, count 2 2006.239.07:40:12.41#ibcon#read 5, iclass 39, count 2 2006.239.07:40:12.41#ibcon#about to read 6, iclass 39, count 2 2006.239.07:40:12.41#ibcon#read 6, iclass 39, count 2 2006.239.07:40:12.41#ibcon#end of sib2, iclass 39, count 2 2006.239.07:40:12.41#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:40:12.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:40:12.41#ibcon#[27=AT06-04\r\n] 2006.239.07:40:12.41#ibcon#*before write, iclass 39, count 2 2006.239.07:40:12.41#ibcon#enter sib2, iclass 39, count 2 2006.239.07:40:12.41#ibcon#flushed, iclass 39, count 2 2006.239.07:40:12.41#ibcon#about to write, iclass 39, count 2 2006.239.07:40:12.41#ibcon#wrote, iclass 39, count 2 2006.239.07:40:12.41#ibcon#about to read 3, iclass 39, count 2 2006.239.07:40:12.45#ibcon#read 3, iclass 39, count 2 2006.239.07:40:12.45#ibcon#about to read 4, iclass 39, count 2 2006.239.07:40:12.45#ibcon#read 4, iclass 39, count 2 2006.239.07:40:12.45#ibcon#about to read 5, iclass 39, count 2 2006.239.07:40:12.45#ibcon#read 5, iclass 39, count 2 2006.239.07:40:12.45#ibcon#about to read 6, iclass 39, count 2 2006.239.07:40:12.45#ibcon#read 6, iclass 39, count 2 2006.239.07:40:12.45#ibcon#end of sib2, iclass 39, count 2 2006.239.07:40:12.45#ibcon#*after write, iclass 39, count 2 2006.239.07:40:12.45#ibcon#*before return 0, iclass 39, count 2 2006.239.07:40:12.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:12.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:40:12.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:40:12.45#ibcon#ireg 7 cls_cnt 0 2006.239.07:40:12.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:12.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:12.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:12.56#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:40:12.56#ibcon#first serial, iclass 39, count 0 2006.239.07:40:12.56#ibcon#enter sib2, iclass 39, count 0 2006.239.07:40:12.56#ibcon#flushed, iclass 39, count 0 2006.239.07:40:12.56#ibcon#about to write, iclass 39, count 0 2006.239.07:40:12.56#ibcon#wrote, iclass 39, count 0 2006.239.07:40:12.56#ibcon#about to read 3, iclass 39, count 0 2006.239.07:40:12.59#ibcon#read 3, iclass 39, count 0 2006.239.07:40:12.59#ibcon#about to read 4, iclass 39, count 0 2006.239.07:40:12.59#ibcon#read 4, iclass 39, count 0 2006.239.07:40:12.59#ibcon#about to read 5, iclass 39, count 0 2006.239.07:40:12.59#ibcon#read 5, iclass 39, count 0 2006.239.07:40:12.59#ibcon#about to read 6, iclass 39, count 0 2006.239.07:40:12.59#ibcon#read 6, iclass 39, count 0 2006.239.07:40:12.59#ibcon#end of sib2, iclass 39, count 0 2006.239.07:40:12.59#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:40:12.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:40:12.59#ibcon#[27=USB\r\n] 2006.239.07:40:12.59#ibcon#*before write, iclass 39, count 0 2006.239.07:40:12.59#ibcon#enter sib2, iclass 39, count 0 2006.239.07:40:12.59#ibcon#flushed, iclass 39, count 0 2006.239.07:40:12.59#ibcon#about to write, iclass 39, count 0 2006.239.07:40:12.59#ibcon#wrote, iclass 39, count 0 2006.239.07:40:12.59#ibcon#about to read 3, iclass 39, count 0 2006.239.07:40:12.61#ibcon#read 3, iclass 39, count 0 2006.239.07:40:12.61#ibcon#about to read 4, iclass 39, count 0 2006.239.07:40:12.61#ibcon#read 4, iclass 39, count 0 2006.239.07:40:12.61#ibcon#about to read 5, iclass 39, count 0 2006.239.07:40:12.61#ibcon#read 5, iclass 39, count 0 2006.239.07:40:12.61#ibcon#about to read 6, iclass 39, count 0 2006.239.07:40:12.61#ibcon#read 6, iclass 39, count 0 2006.239.07:40:12.61#ibcon#end of sib2, iclass 39, count 0 2006.239.07:40:12.61#ibcon#*after write, iclass 39, count 0 2006.239.07:40:12.61#ibcon#*before return 0, iclass 39, count 0 2006.239.07:40:12.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:12.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:40:12.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:40:12.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:40:12.61$vc4f8/vabw=wide 2006.239.07:40:12.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:40:12.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:40:12.61#ibcon#ireg 8 cls_cnt 0 2006.239.07:40:12.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:12.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:12.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:12.61#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:40:12.61#ibcon#first serial, iclass 3, count 0 2006.239.07:40:12.61#ibcon#enter sib2, iclass 3, count 0 2006.239.07:40:12.61#ibcon#flushed, iclass 3, count 0 2006.239.07:40:12.61#ibcon#about to write, iclass 3, count 0 2006.239.07:40:12.61#ibcon#wrote, iclass 3, count 0 2006.239.07:40:12.61#ibcon#about to read 3, iclass 3, count 0 2006.239.07:40:12.63#ibcon#read 3, iclass 3, count 0 2006.239.07:40:12.63#ibcon#about to read 4, iclass 3, count 0 2006.239.07:40:12.63#ibcon#read 4, iclass 3, count 0 2006.239.07:40:12.63#ibcon#about to read 5, iclass 3, count 0 2006.239.07:40:12.63#ibcon#read 5, iclass 3, count 0 2006.239.07:40:12.63#ibcon#about to read 6, iclass 3, count 0 2006.239.07:40:12.63#ibcon#read 6, iclass 3, count 0 2006.239.07:40:12.63#ibcon#end of sib2, iclass 3, count 0 2006.239.07:40:12.63#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:40:12.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:40:12.63#ibcon#[25=BW32\r\n] 2006.239.07:40:12.63#ibcon#*before write, iclass 3, count 0 2006.239.07:40:12.63#ibcon#enter sib2, iclass 3, count 0 2006.239.07:40:12.63#ibcon#flushed, iclass 3, count 0 2006.239.07:40:12.63#ibcon#about to write, iclass 3, count 0 2006.239.07:40:12.63#ibcon#wrote, iclass 3, count 0 2006.239.07:40:12.63#ibcon#about to read 3, iclass 3, count 0 2006.239.07:40:12.66#ibcon#read 3, iclass 3, count 0 2006.239.07:40:12.66#ibcon#about to read 4, iclass 3, count 0 2006.239.07:40:12.66#ibcon#read 4, iclass 3, count 0 2006.239.07:40:12.66#ibcon#about to read 5, iclass 3, count 0 2006.239.07:40:12.66#ibcon#read 5, iclass 3, count 0 2006.239.07:40:12.66#ibcon#about to read 6, iclass 3, count 0 2006.239.07:40:12.66#ibcon#read 6, iclass 3, count 0 2006.239.07:40:12.66#ibcon#end of sib2, iclass 3, count 0 2006.239.07:40:12.66#ibcon#*after write, iclass 3, count 0 2006.239.07:40:12.66#ibcon#*before return 0, iclass 3, count 0 2006.239.07:40:12.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:12.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:40:12.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:40:12.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:40:12.66$vc4f8/vbbw=wide 2006.239.07:40:12.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:40:12.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:40:12.66#ibcon#ireg 8 cls_cnt 0 2006.239.07:40:12.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:40:12.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:40:12.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:40:12.73#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:40:12.73#ibcon#first serial, iclass 5, count 0 2006.239.07:40:12.73#ibcon#enter sib2, iclass 5, count 0 2006.239.07:40:12.73#ibcon#flushed, iclass 5, count 0 2006.239.07:40:12.73#ibcon#about to write, iclass 5, count 0 2006.239.07:40:12.73#ibcon#wrote, iclass 5, count 0 2006.239.07:40:12.73#ibcon#about to read 3, iclass 5, count 0 2006.239.07:40:12.75#ibcon#read 3, iclass 5, count 0 2006.239.07:40:12.75#ibcon#about to read 4, iclass 5, count 0 2006.239.07:40:12.75#ibcon#read 4, iclass 5, count 0 2006.239.07:40:12.75#ibcon#about to read 5, iclass 5, count 0 2006.239.07:40:12.75#ibcon#read 5, iclass 5, count 0 2006.239.07:40:12.75#ibcon#about to read 6, iclass 5, count 0 2006.239.07:40:12.75#ibcon#read 6, iclass 5, count 0 2006.239.07:40:12.75#ibcon#end of sib2, iclass 5, count 0 2006.239.07:40:12.75#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:40:12.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:40:12.75#ibcon#[27=BW32\r\n] 2006.239.07:40:12.75#ibcon#*before write, iclass 5, count 0 2006.239.07:40:12.75#ibcon#enter sib2, iclass 5, count 0 2006.239.07:40:12.75#ibcon#flushed, iclass 5, count 0 2006.239.07:40:12.75#ibcon#about to write, iclass 5, count 0 2006.239.07:40:12.75#ibcon#wrote, iclass 5, count 0 2006.239.07:40:12.75#ibcon#about to read 3, iclass 5, count 0 2006.239.07:40:12.78#ibcon#read 3, iclass 5, count 0 2006.239.07:40:12.78#ibcon#about to read 4, iclass 5, count 0 2006.239.07:40:12.78#ibcon#read 4, iclass 5, count 0 2006.239.07:40:12.78#ibcon#about to read 5, iclass 5, count 0 2006.239.07:40:12.78#ibcon#read 5, iclass 5, count 0 2006.239.07:40:12.78#ibcon#about to read 6, iclass 5, count 0 2006.239.07:40:12.78#ibcon#read 6, iclass 5, count 0 2006.239.07:40:12.78#ibcon#end of sib2, iclass 5, count 0 2006.239.07:40:12.78#ibcon#*after write, iclass 5, count 0 2006.239.07:40:12.78#ibcon#*before return 0, iclass 5, count 0 2006.239.07:40:12.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:40:12.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:40:12.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:40:12.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:40:12.78$4f8m12a/ifd4f 2006.239.07:40:12.78$ifd4f/lo= 2006.239.07:40:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:40:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:40:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:40:12.78$ifd4f/patch= 2006.239.07:40:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:40:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:40:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:40:12.78$4f8m12a/"form=m,16.000,1:2 2006.239.07:40:12.79$4f8m12a/"tpicd 2006.239.07:40:12.79$4f8m12a/echo=off 2006.239.07:40:12.79$4f8m12a/xlog=off 2006.239.07:40:12.79:!2006.239.07:41:00 2006.239.07:40:39.13#trakl#Source acquired 2006.239.07:40:39.13#flagr#flagr/antenna,acquired 2006.239.07:41:00.01:preob 2006.239.07:41:01.13/onsource/TRACKING 2006.239.07:41:01.13:!2006.239.07:41:10 2006.239.07:41:10.00:data_valid=on 2006.239.07:41:10.00:midob 2006.239.07:41:10.13/onsource/TRACKING 2006.239.07:41:10.13/wx/25.36,1011.5,80 2006.239.07:41:10.33/cable/+6.4159E-03 2006.239.07:41:11.42/va/01,08,usb,yes,31,32 2006.239.07:41:11.42/va/02,07,usb,yes,31,33 2006.239.07:41:11.42/va/03,07,usb,yes,29,29 2006.239.07:41:11.42/va/04,07,usb,yes,32,35 2006.239.07:41:11.42/va/05,08,usb,yes,29,31 2006.239.07:41:11.42/va/06,07,usb,yes,32,32 2006.239.07:41:11.42/va/07,07,usb,yes,32,32 2006.239.07:41:11.42/va/08,07,usb,yes,34,34 2006.239.07:41:11.65/valo/01,532.99,yes,locked 2006.239.07:41:11.65/valo/02,572.99,yes,locked 2006.239.07:41:11.65/valo/03,672.99,yes,locked 2006.239.07:41:11.65/valo/04,832.99,yes,locked 2006.239.07:41:11.65/valo/05,652.99,yes,locked 2006.239.07:41:11.65/valo/06,772.99,yes,locked 2006.239.07:41:11.65/valo/07,832.99,yes,locked 2006.239.07:41:11.65/valo/08,852.99,yes,locked 2006.239.07:41:12.74/vb/01,04,usb,yes,30,29 2006.239.07:41:12.74/vb/02,04,usb,yes,32,34 2006.239.07:41:12.74/vb/03,04,usb,yes,29,32 2006.239.07:41:12.74/vb/04,04,usb,yes,29,30 2006.239.07:41:12.74/vb/05,04,usb,yes,28,32 2006.239.07:41:12.74/vb/06,04,usb,yes,29,32 2006.239.07:41:12.74/vb/07,04,usb,yes,31,31 2006.239.07:41:12.74/vb/08,04,usb,yes,28,32 2006.239.07:41:12.98/vblo/01,632.99,yes,locked 2006.239.07:41:12.98/vblo/02,640.99,yes,locked 2006.239.07:41:12.98/vblo/03,656.99,yes,locked 2006.239.07:41:12.98/vblo/04,712.99,yes,locked 2006.239.07:41:12.98/vblo/05,744.99,yes,locked 2006.239.07:41:12.98/vblo/06,752.99,yes,locked 2006.239.07:41:12.98/vblo/07,734.99,yes,locked 2006.239.07:41:12.98/vblo/08,744.99,yes,locked 2006.239.07:41:13.13/vabw/8 2006.239.07:41:13.28/vbbw/8 2006.239.07:41:13.37/xfe/off,on,13.2 2006.239.07:41:13.74/ifatt/23,28,28,28 2006.239.07:41:14.07/fmout-gps/S +4.37E-07 2006.239.07:41:14.11:!2006.239.07:42:10 2006.239.07:42:10.00:data_valid=off 2006.239.07:42:10.00:postob 2006.239.07:42:10.17/cable/+6.4130E-03 2006.239.07:42:10.17/wx/25.35,1011.5,80 2006.239.07:42:11.07/fmout-gps/S +4.37E-07 2006.239.07:42:11.07:scan_name=239-0743,k06239,60 2006.239.07:42:11.07:source=0059+581,010245.76,582411.1,2000.0,cw 2006.239.07:42:11.13#flagr#flagr/antenna,new-source 2006.239.07:42:12.14:checkk5 2006.239.07:42:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:42:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:42:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:42:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:42:14.02/chk_obsdata//k5ts1/T2390741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:42:14.39/chk_obsdata//k5ts2/T2390741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:42:14.77/chk_obsdata//k5ts3/T2390741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:42:15.14/chk_obsdata//k5ts4/T2390741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:42:15.84/k5log//k5ts1_log_newline 2006.239.07:42:16.53/k5log//k5ts2_log_newline 2006.239.07:42:17.22/k5log//k5ts3_log_newline 2006.239.07:42:17.90/k5log//k5ts4_log_newline 2006.239.07:42:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:42:17.93:4f8m12a=1 2006.239.07:42:17.93$4f8m12a/echo=on 2006.239.07:42:17.93$4f8m12a/pcalon 2006.239.07:42:17.93$pcalon/"no phase cal control is implemented here 2006.239.07:42:17.93$4f8m12a/"tpicd=stop 2006.239.07:42:17.93$4f8m12a/vc4f8 2006.239.07:42:17.93$vc4f8/valo=1,532.99 2006.239.07:42:17.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:42:17.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:42:17.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:17.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:17.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:17.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:17.93#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:42:17.93#ibcon#first serial, iclass 26, count 0 2006.239.07:42:17.93#ibcon#enter sib2, iclass 26, count 0 2006.239.07:42:17.93#ibcon#flushed, iclass 26, count 0 2006.239.07:42:17.93#ibcon#about to write, iclass 26, count 0 2006.239.07:42:17.93#ibcon#wrote, iclass 26, count 0 2006.239.07:42:17.94#ibcon#about to read 3, iclass 26, count 0 2006.239.07:42:17.98#ibcon#read 3, iclass 26, count 0 2006.239.07:42:17.98#ibcon#about to read 4, iclass 26, count 0 2006.239.07:42:17.98#ibcon#read 4, iclass 26, count 0 2006.239.07:42:17.98#ibcon#about to read 5, iclass 26, count 0 2006.239.07:42:17.98#ibcon#read 5, iclass 26, count 0 2006.239.07:42:17.98#ibcon#about to read 6, iclass 26, count 0 2006.239.07:42:17.98#ibcon#read 6, iclass 26, count 0 2006.239.07:42:17.98#ibcon#end of sib2, iclass 26, count 0 2006.239.07:42:17.98#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:42:17.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:42:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:42:17.98#ibcon#*before write, iclass 26, count 0 2006.239.07:42:17.98#ibcon#enter sib2, iclass 26, count 0 2006.239.07:42:17.98#ibcon#flushed, iclass 26, count 0 2006.239.07:42:17.98#ibcon#about to write, iclass 26, count 0 2006.239.07:42:17.98#ibcon#wrote, iclass 26, count 0 2006.239.07:42:17.98#ibcon#about to read 3, iclass 26, count 0 2006.239.07:42:18.02#ibcon#read 3, iclass 26, count 0 2006.239.07:42:18.02#ibcon#about to read 4, iclass 26, count 0 2006.239.07:42:18.02#ibcon#read 4, iclass 26, count 0 2006.239.07:42:18.02#ibcon#about to read 5, iclass 26, count 0 2006.239.07:42:18.02#ibcon#read 5, iclass 26, count 0 2006.239.07:42:18.02#ibcon#about to read 6, iclass 26, count 0 2006.239.07:42:18.02#ibcon#read 6, iclass 26, count 0 2006.239.07:42:18.02#ibcon#end of sib2, iclass 26, count 0 2006.239.07:42:18.02#ibcon#*after write, iclass 26, count 0 2006.239.07:42:18.02#ibcon#*before return 0, iclass 26, count 0 2006.239.07:42:18.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:18.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:18.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:42:18.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:42:18.02$vc4f8/va=1,8 2006.239.07:42:18.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:42:18.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:42:18.02#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:18.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:18.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:18.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:18.02#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:42:18.02#ibcon#first serial, iclass 28, count 2 2006.239.07:42:18.02#ibcon#enter sib2, iclass 28, count 2 2006.239.07:42:18.02#ibcon#flushed, iclass 28, count 2 2006.239.07:42:18.02#ibcon#about to write, iclass 28, count 2 2006.239.07:42:18.02#ibcon#wrote, iclass 28, count 2 2006.239.07:42:18.02#ibcon#about to read 3, iclass 28, count 2 2006.239.07:42:18.04#ibcon#read 3, iclass 28, count 2 2006.239.07:42:18.04#ibcon#about to read 4, iclass 28, count 2 2006.239.07:42:18.04#ibcon#read 4, iclass 28, count 2 2006.239.07:42:18.04#ibcon#about to read 5, iclass 28, count 2 2006.239.07:42:18.04#ibcon#read 5, iclass 28, count 2 2006.239.07:42:18.04#ibcon#about to read 6, iclass 28, count 2 2006.239.07:42:18.04#ibcon#read 6, iclass 28, count 2 2006.239.07:42:18.04#ibcon#end of sib2, iclass 28, count 2 2006.239.07:42:18.04#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:42:18.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:42:18.04#ibcon#[25=AT01-08\r\n] 2006.239.07:42:18.04#ibcon#*before write, iclass 28, count 2 2006.239.07:42:18.04#ibcon#enter sib2, iclass 28, count 2 2006.239.07:42:18.04#ibcon#flushed, iclass 28, count 2 2006.239.07:42:18.04#ibcon#about to write, iclass 28, count 2 2006.239.07:42:18.04#ibcon#wrote, iclass 28, count 2 2006.239.07:42:18.04#ibcon#about to read 3, iclass 28, count 2 2006.239.07:42:18.08#ibcon#read 3, iclass 28, count 2 2006.239.07:42:18.08#ibcon#about to read 4, iclass 28, count 2 2006.239.07:42:18.08#ibcon#read 4, iclass 28, count 2 2006.239.07:42:18.08#ibcon#about to read 5, iclass 28, count 2 2006.239.07:42:18.08#ibcon#read 5, iclass 28, count 2 2006.239.07:42:18.08#ibcon#about to read 6, iclass 28, count 2 2006.239.07:42:18.08#ibcon#read 6, iclass 28, count 2 2006.239.07:42:18.08#ibcon#end of sib2, iclass 28, count 2 2006.239.07:42:18.08#ibcon#*after write, iclass 28, count 2 2006.239.07:42:18.08#ibcon#*before return 0, iclass 28, count 2 2006.239.07:42:18.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:18.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:18.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:42:18.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:18.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:18.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:18.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:18.19#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:42:18.19#ibcon#first serial, iclass 28, count 0 2006.239.07:42:18.19#ibcon#enter sib2, iclass 28, count 0 2006.239.07:42:18.19#ibcon#flushed, iclass 28, count 0 2006.239.07:42:18.19#ibcon#about to write, iclass 28, count 0 2006.239.07:42:18.19#ibcon#wrote, iclass 28, count 0 2006.239.07:42:18.19#ibcon#about to read 3, iclass 28, count 0 2006.239.07:42:18.21#ibcon#read 3, iclass 28, count 0 2006.239.07:42:18.21#ibcon#about to read 4, iclass 28, count 0 2006.239.07:42:18.21#ibcon#read 4, iclass 28, count 0 2006.239.07:42:18.21#ibcon#about to read 5, iclass 28, count 0 2006.239.07:42:18.21#ibcon#read 5, iclass 28, count 0 2006.239.07:42:18.21#ibcon#about to read 6, iclass 28, count 0 2006.239.07:42:18.21#ibcon#read 6, iclass 28, count 0 2006.239.07:42:18.21#ibcon#end of sib2, iclass 28, count 0 2006.239.07:42:18.21#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:42:18.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:42:18.21#ibcon#[25=USB\r\n] 2006.239.07:42:18.21#ibcon#*before write, iclass 28, count 0 2006.239.07:42:18.21#ibcon#enter sib2, iclass 28, count 0 2006.239.07:42:18.21#ibcon#flushed, iclass 28, count 0 2006.239.07:42:18.21#ibcon#about to write, iclass 28, count 0 2006.239.07:42:18.21#ibcon#wrote, iclass 28, count 0 2006.239.07:42:18.21#ibcon#about to read 3, iclass 28, count 0 2006.239.07:42:18.24#ibcon#read 3, iclass 28, count 0 2006.239.07:42:18.24#ibcon#about to read 4, iclass 28, count 0 2006.239.07:42:18.24#ibcon#read 4, iclass 28, count 0 2006.239.07:42:18.24#ibcon#about to read 5, iclass 28, count 0 2006.239.07:42:18.24#ibcon#read 5, iclass 28, count 0 2006.239.07:42:18.24#ibcon#about to read 6, iclass 28, count 0 2006.239.07:42:18.24#ibcon#read 6, iclass 28, count 0 2006.239.07:42:18.24#ibcon#end of sib2, iclass 28, count 0 2006.239.07:42:18.24#ibcon#*after write, iclass 28, count 0 2006.239.07:42:18.24#ibcon#*before return 0, iclass 28, count 0 2006.239.07:42:18.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:18.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:18.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:42:18.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:42:18.24$vc4f8/valo=2,572.99 2006.239.07:42:18.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:42:18.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:42:18.24#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:18.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:18.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:18.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:18.24#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:42:18.24#ibcon#first serial, iclass 30, count 0 2006.239.07:42:18.24#ibcon#enter sib2, iclass 30, count 0 2006.239.07:42:18.24#ibcon#flushed, iclass 30, count 0 2006.239.07:42:18.24#ibcon#about to write, iclass 30, count 0 2006.239.07:42:18.24#ibcon#wrote, iclass 30, count 0 2006.239.07:42:18.24#ibcon#about to read 3, iclass 30, count 0 2006.239.07:42:18.26#ibcon#read 3, iclass 30, count 0 2006.239.07:42:18.26#ibcon#about to read 4, iclass 30, count 0 2006.239.07:42:18.26#ibcon#read 4, iclass 30, count 0 2006.239.07:42:18.26#ibcon#about to read 5, iclass 30, count 0 2006.239.07:42:18.26#ibcon#read 5, iclass 30, count 0 2006.239.07:42:18.26#ibcon#about to read 6, iclass 30, count 0 2006.239.07:42:18.26#ibcon#read 6, iclass 30, count 0 2006.239.07:42:18.26#ibcon#end of sib2, iclass 30, count 0 2006.239.07:42:18.26#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:42:18.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:42:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:42:18.26#ibcon#*before write, iclass 30, count 0 2006.239.07:42:18.26#ibcon#enter sib2, iclass 30, count 0 2006.239.07:42:18.26#ibcon#flushed, iclass 30, count 0 2006.239.07:42:18.26#ibcon#about to write, iclass 30, count 0 2006.239.07:42:18.26#ibcon#wrote, iclass 30, count 0 2006.239.07:42:18.26#ibcon#about to read 3, iclass 30, count 0 2006.239.07:42:18.30#ibcon#read 3, iclass 30, count 0 2006.239.07:42:18.30#ibcon#about to read 4, iclass 30, count 0 2006.239.07:42:18.30#ibcon#read 4, iclass 30, count 0 2006.239.07:42:18.30#ibcon#about to read 5, iclass 30, count 0 2006.239.07:42:18.30#ibcon#read 5, iclass 30, count 0 2006.239.07:42:18.30#ibcon#about to read 6, iclass 30, count 0 2006.239.07:42:18.30#ibcon#read 6, iclass 30, count 0 2006.239.07:42:18.30#ibcon#end of sib2, iclass 30, count 0 2006.239.07:42:18.30#ibcon#*after write, iclass 30, count 0 2006.239.07:42:18.30#ibcon#*before return 0, iclass 30, count 0 2006.239.07:42:18.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:18.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:18.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:42:18.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:42:18.30$vc4f8/va=2,7 2006.239.07:42:18.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:42:18.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:42:18.30#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:18.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:18.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:18.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:18.36#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:42:18.36#ibcon#first serial, iclass 32, count 2 2006.239.07:42:18.36#ibcon#enter sib2, iclass 32, count 2 2006.239.07:42:18.36#ibcon#flushed, iclass 32, count 2 2006.239.07:42:18.36#ibcon#about to write, iclass 32, count 2 2006.239.07:42:18.36#ibcon#wrote, iclass 32, count 2 2006.239.07:42:18.36#ibcon#about to read 3, iclass 32, count 2 2006.239.07:42:18.38#ibcon#read 3, iclass 32, count 2 2006.239.07:42:18.38#ibcon#about to read 4, iclass 32, count 2 2006.239.07:42:18.38#ibcon#read 4, iclass 32, count 2 2006.239.07:42:18.38#ibcon#about to read 5, iclass 32, count 2 2006.239.07:42:18.38#ibcon#read 5, iclass 32, count 2 2006.239.07:42:18.38#ibcon#about to read 6, iclass 32, count 2 2006.239.07:42:18.38#ibcon#read 6, iclass 32, count 2 2006.239.07:42:18.38#ibcon#end of sib2, iclass 32, count 2 2006.239.07:42:18.38#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:42:18.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:42:18.38#ibcon#[25=AT02-07\r\n] 2006.239.07:42:18.38#ibcon#*before write, iclass 32, count 2 2006.239.07:42:18.38#ibcon#enter sib2, iclass 32, count 2 2006.239.07:42:18.38#ibcon#flushed, iclass 32, count 2 2006.239.07:42:18.38#ibcon#about to write, iclass 32, count 2 2006.239.07:42:18.38#ibcon#wrote, iclass 32, count 2 2006.239.07:42:18.38#ibcon#about to read 3, iclass 32, count 2 2006.239.07:42:18.41#ibcon#read 3, iclass 32, count 2 2006.239.07:42:18.41#ibcon#about to read 4, iclass 32, count 2 2006.239.07:42:18.41#ibcon#read 4, iclass 32, count 2 2006.239.07:42:18.41#ibcon#about to read 5, iclass 32, count 2 2006.239.07:42:18.41#ibcon#read 5, iclass 32, count 2 2006.239.07:42:18.41#ibcon#about to read 6, iclass 32, count 2 2006.239.07:42:18.41#ibcon#read 6, iclass 32, count 2 2006.239.07:42:18.41#ibcon#end of sib2, iclass 32, count 2 2006.239.07:42:18.41#ibcon#*after write, iclass 32, count 2 2006.239.07:42:18.41#ibcon#*before return 0, iclass 32, count 2 2006.239.07:42:18.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:18.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:18.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:42:18.41#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:18.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:18.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:18.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:18.53#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:42:18.53#ibcon#first serial, iclass 32, count 0 2006.239.07:42:18.53#ibcon#enter sib2, iclass 32, count 0 2006.239.07:42:18.53#ibcon#flushed, iclass 32, count 0 2006.239.07:42:18.53#ibcon#about to write, iclass 32, count 0 2006.239.07:42:18.53#ibcon#wrote, iclass 32, count 0 2006.239.07:42:18.53#ibcon#about to read 3, iclass 32, count 0 2006.239.07:42:18.55#ibcon#read 3, iclass 32, count 0 2006.239.07:42:18.55#ibcon#about to read 4, iclass 32, count 0 2006.239.07:42:18.55#ibcon#read 4, iclass 32, count 0 2006.239.07:42:18.55#ibcon#about to read 5, iclass 32, count 0 2006.239.07:42:18.55#ibcon#read 5, iclass 32, count 0 2006.239.07:42:18.55#ibcon#about to read 6, iclass 32, count 0 2006.239.07:42:18.55#ibcon#read 6, iclass 32, count 0 2006.239.07:42:18.55#ibcon#end of sib2, iclass 32, count 0 2006.239.07:42:18.55#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:42:18.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:42:18.55#ibcon#[25=USB\r\n] 2006.239.07:42:18.55#ibcon#*before write, iclass 32, count 0 2006.239.07:42:18.55#ibcon#enter sib2, iclass 32, count 0 2006.239.07:42:18.55#ibcon#flushed, iclass 32, count 0 2006.239.07:42:18.55#ibcon#about to write, iclass 32, count 0 2006.239.07:42:18.55#ibcon#wrote, iclass 32, count 0 2006.239.07:42:18.55#ibcon#about to read 3, iclass 32, count 0 2006.239.07:42:18.58#ibcon#read 3, iclass 32, count 0 2006.239.07:42:18.58#ibcon#about to read 4, iclass 32, count 0 2006.239.07:42:18.58#ibcon#read 4, iclass 32, count 0 2006.239.07:42:18.58#ibcon#about to read 5, iclass 32, count 0 2006.239.07:42:18.58#ibcon#read 5, iclass 32, count 0 2006.239.07:42:18.58#ibcon#about to read 6, iclass 32, count 0 2006.239.07:42:18.58#ibcon#read 6, iclass 32, count 0 2006.239.07:42:18.58#ibcon#end of sib2, iclass 32, count 0 2006.239.07:42:18.58#ibcon#*after write, iclass 32, count 0 2006.239.07:42:18.58#ibcon#*before return 0, iclass 32, count 0 2006.239.07:42:18.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:18.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:18.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:42:18.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:42:18.58$vc4f8/valo=3,672.99 2006.239.07:42:18.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:42:18.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:42:18.58#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:18.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:18.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:18.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:18.58#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:42:18.58#ibcon#first serial, iclass 34, count 0 2006.239.07:42:18.58#ibcon#enter sib2, iclass 34, count 0 2006.239.07:42:18.58#ibcon#flushed, iclass 34, count 0 2006.239.07:42:18.58#ibcon#about to write, iclass 34, count 0 2006.239.07:42:18.58#ibcon#wrote, iclass 34, count 0 2006.239.07:42:18.58#ibcon#about to read 3, iclass 34, count 0 2006.239.07:42:18.60#ibcon#read 3, iclass 34, count 0 2006.239.07:42:18.60#ibcon#about to read 4, iclass 34, count 0 2006.239.07:42:18.60#ibcon#read 4, iclass 34, count 0 2006.239.07:42:18.60#ibcon#about to read 5, iclass 34, count 0 2006.239.07:42:18.60#ibcon#read 5, iclass 34, count 0 2006.239.07:42:18.60#ibcon#about to read 6, iclass 34, count 0 2006.239.07:42:18.60#ibcon#read 6, iclass 34, count 0 2006.239.07:42:18.60#ibcon#end of sib2, iclass 34, count 0 2006.239.07:42:18.60#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:42:18.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:42:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:42:18.60#ibcon#*before write, iclass 34, count 0 2006.239.07:42:18.60#ibcon#enter sib2, iclass 34, count 0 2006.239.07:42:18.60#ibcon#flushed, iclass 34, count 0 2006.239.07:42:18.60#ibcon#about to write, iclass 34, count 0 2006.239.07:42:18.60#ibcon#wrote, iclass 34, count 0 2006.239.07:42:18.60#ibcon#about to read 3, iclass 34, count 0 2006.239.07:42:18.64#ibcon#read 3, iclass 34, count 0 2006.239.07:42:18.64#ibcon#about to read 4, iclass 34, count 0 2006.239.07:42:18.64#ibcon#read 4, iclass 34, count 0 2006.239.07:42:18.64#ibcon#about to read 5, iclass 34, count 0 2006.239.07:42:18.64#ibcon#read 5, iclass 34, count 0 2006.239.07:42:18.64#ibcon#about to read 6, iclass 34, count 0 2006.239.07:42:18.64#ibcon#read 6, iclass 34, count 0 2006.239.07:42:18.64#ibcon#end of sib2, iclass 34, count 0 2006.239.07:42:18.64#ibcon#*after write, iclass 34, count 0 2006.239.07:42:18.64#ibcon#*before return 0, iclass 34, count 0 2006.239.07:42:18.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:18.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:18.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:42:18.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:42:18.64$vc4f8/va=3,7 2006.239.07:42:18.65#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:42:18.65#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:42:18.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:18.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:18.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:18.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:18.69#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:42:18.69#ibcon#first serial, iclass 36, count 2 2006.239.07:42:18.69#ibcon#enter sib2, iclass 36, count 2 2006.239.07:42:18.69#ibcon#flushed, iclass 36, count 2 2006.239.07:42:18.69#ibcon#about to write, iclass 36, count 2 2006.239.07:42:18.69#ibcon#wrote, iclass 36, count 2 2006.239.07:42:18.69#ibcon#about to read 3, iclass 36, count 2 2006.239.07:42:18.71#ibcon#read 3, iclass 36, count 2 2006.239.07:42:18.71#ibcon#about to read 4, iclass 36, count 2 2006.239.07:42:18.71#ibcon#read 4, iclass 36, count 2 2006.239.07:42:18.71#ibcon#about to read 5, iclass 36, count 2 2006.239.07:42:18.71#ibcon#read 5, iclass 36, count 2 2006.239.07:42:18.71#ibcon#about to read 6, iclass 36, count 2 2006.239.07:42:18.71#ibcon#read 6, iclass 36, count 2 2006.239.07:42:18.71#ibcon#end of sib2, iclass 36, count 2 2006.239.07:42:18.71#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:42:18.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:42:18.71#ibcon#[25=AT03-07\r\n] 2006.239.07:42:18.71#ibcon#*before write, iclass 36, count 2 2006.239.07:42:18.71#ibcon#enter sib2, iclass 36, count 2 2006.239.07:42:18.71#ibcon#flushed, iclass 36, count 2 2006.239.07:42:18.71#ibcon#about to write, iclass 36, count 2 2006.239.07:42:18.71#ibcon#wrote, iclass 36, count 2 2006.239.07:42:18.71#ibcon#about to read 3, iclass 36, count 2 2006.239.07:42:18.75#ibcon#read 3, iclass 36, count 2 2006.239.07:42:18.75#ibcon#about to read 4, iclass 36, count 2 2006.239.07:42:18.75#ibcon#read 4, iclass 36, count 2 2006.239.07:42:18.75#ibcon#about to read 5, iclass 36, count 2 2006.239.07:42:18.75#ibcon#read 5, iclass 36, count 2 2006.239.07:42:18.75#ibcon#about to read 6, iclass 36, count 2 2006.239.07:42:18.75#ibcon#read 6, iclass 36, count 2 2006.239.07:42:18.75#ibcon#end of sib2, iclass 36, count 2 2006.239.07:42:18.75#ibcon#*after write, iclass 36, count 2 2006.239.07:42:18.75#ibcon#*before return 0, iclass 36, count 2 2006.239.07:42:18.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:18.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:18.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:42:18.75#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:18.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:18.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:18.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:18.86#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:42:18.86#ibcon#first serial, iclass 36, count 0 2006.239.07:42:18.86#ibcon#enter sib2, iclass 36, count 0 2006.239.07:42:18.86#ibcon#flushed, iclass 36, count 0 2006.239.07:42:18.86#ibcon#about to write, iclass 36, count 0 2006.239.07:42:18.86#ibcon#wrote, iclass 36, count 0 2006.239.07:42:18.86#ibcon#about to read 3, iclass 36, count 0 2006.239.07:42:18.88#ibcon#read 3, iclass 36, count 0 2006.239.07:42:18.88#ibcon#about to read 4, iclass 36, count 0 2006.239.07:42:18.88#ibcon#read 4, iclass 36, count 0 2006.239.07:42:18.88#ibcon#about to read 5, iclass 36, count 0 2006.239.07:42:18.88#ibcon#read 5, iclass 36, count 0 2006.239.07:42:18.88#ibcon#about to read 6, iclass 36, count 0 2006.239.07:42:18.88#ibcon#read 6, iclass 36, count 0 2006.239.07:42:18.88#ibcon#end of sib2, iclass 36, count 0 2006.239.07:42:18.88#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:42:18.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:42:18.88#ibcon#[25=USB\r\n] 2006.239.07:42:18.88#ibcon#*before write, iclass 36, count 0 2006.239.07:42:18.88#ibcon#enter sib2, iclass 36, count 0 2006.239.07:42:18.88#ibcon#flushed, iclass 36, count 0 2006.239.07:42:18.88#ibcon#about to write, iclass 36, count 0 2006.239.07:42:18.88#ibcon#wrote, iclass 36, count 0 2006.239.07:42:18.88#ibcon#about to read 3, iclass 36, count 0 2006.239.07:42:18.91#ibcon#read 3, iclass 36, count 0 2006.239.07:42:18.91#ibcon#about to read 4, iclass 36, count 0 2006.239.07:42:18.91#ibcon#read 4, iclass 36, count 0 2006.239.07:42:18.91#ibcon#about to read 5, iclass 36, count 0 2006.239.07:42:18.91#ibcon#read 5, iclass 36, count 0 2006.239.07:42:18.91#ibcon#about to read 6, iclass 36, count 0 2006.239.07:42:18.91#ibcon#read 6, iclass 36, count 0 2006.239.07:42:18.91#ibcon#end of sib2, iclass 36, count 0 2006.239.07:42:18.91#ibcon#*after write, iclass 36, count 0 2006.239.07:42:18.91#ibcon#*before return 0, iclass 36, count 0 2006.239.07:42:18.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:18.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:18.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:42:18.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:42:18.91$vc4f8/valo=4,832.99 2006.239.07:42:18.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.07:42:18.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.07:42:18.91#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:18.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:18.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:18.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:18.91#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:42:18.91#ibcon#first serial, iclass 38, count 0 2006.239.07:42:18.91#ibcon#enter sib2, iclass 38, count 0 2006.239.07:42:18.91#ibcon#flushed, iclass 38, count 0 2006.239.07:42:18.91#ibcon#about to write, iclass 38, count 0 2006.239.07:42:18.91#ibcon#wrote, iclass 38, count 0 2006.239.07:42:18.91#ibcon#about to read 3, iclass 38, count 0 2006.239.07:42:18.93#ibcon#read 3, iclass 38, count 0 2006.239.07:42:18.93#ibcon#about to read 4, iclass 38, count 0 2006.239.07:42:18.93#ibcon#read 4, iclass 38, count 0 2006.239.07:42:18.93#ibcon#about to read 5, iclass 38, count 0 2006.239.07:42:18.93#ibcon#read 5, iclass 38, count 0 2006.239.07:42:18.93#ibcon#about to read 6, iclass 38, count 0 2006.239.07:42:18.93#ibcon#read 6, iclass 38, count 0 2006.239.07:42:18.93#ibcon#end of sib2, iclass 38, count 0 2006.239.07:42:18.93#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:42:18.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:42:18.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:42:18.93#ibcon#*before write, iclass 38, count 0 2006.239.07:42:18.93#ibcon#enter sib2, iclass 38, count 0 2006.239.07:42:18.93#ibcon#flushed, iclass 38, count 0 2006.239.07:42:18.93#ibcon#about to write, iclass 38, count 0 2006.239.07:42:18.93#ibcon#wrote, iclass 38, count 0 2006.239.07:42:18.93#ibcon#about to read 3, iclass 38, count 0 2006.239.07:42:18.97#ibcon#read 3, iclass 38, count 0 2006.239.07:42:18.97#ibcon#about to read 4, iclass 38, count 0 2006.239.07:42:18.97#ibcon#read 4, iclass 38, count 0 2006.239.07:42:18.97#ibcon#about to read 5, iclass 38, count 0 2006.239.07:42:18.97#ibcon#read 5, iclass 38, count 0 2006.239.07:42:18.97#ibcon#about to read 6, iclass 38, count 0 2006.239.07:42:18.97#ibcon#read 6, iclass 38, count 0 2006.239.07:42:18.97#ibcon#end of sib2, iclass 38, count 0 2006.239.07:42:18.97#ibcon#*after write, iclass 38, count 0 2006.239.07:42:18.97#ibcon#*before return 0, iclass 38, count 0 2006.239.07:42:18.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:18.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:18.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:42:18.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:42:18.97$vc4f8/va=4,7 2006.239.07:42:18.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.07:42:18.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.07:42:18.97#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:18.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:19.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:19.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:19.03#ibcon#enter wrdev, iclass 40, count 2 2006.239.07:42:19.03#ibcon#first serial, iclass 40, count 2 2006.239.07:42:19.03#ibcon#enter sib2, iclass 40, count 2 2006.239.07:42:19.03#ibcon#flushed, iclass 40, count 2 2006.239.07:42:19.03#ibcon#about to write, iclass 40, count 2 2006.239.07:42:19.03#ibcon#wrote, iclass 40, count 2 2006.239.07:42:19.03#ibcon#about to read 3, iclass 40, count 2 2006.239.07:42:19.05#ibcon#read 3, iclass 40, count 2 2006.239.07:42:19.05#ibcon#about to read 4, iclass 40, count 2 2006.239.07:42:19.05#ibcon#read 4, iclass 40, count 2 2006.239.07:42:19.05#ibcon#about to read 5, iclass 40, count 2 2006.239.07:42:19.05#ibcon#read 5, iclass 40, count 2 2006.239.07:42:19.05#ibcon#about to read 6, iclass 40, count 2 2006.239.07:42:19.05#ibcon#read 6, iclass 40, count 2 2006.239.07:42:19.05#ibcon#end of sib2, iclass 40, count 2 2006.239.07:42:19.05#ibcon#*mode == 0, iclass 40, count 2 2006.239.07:42:19.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.07:42:19.05#ibcon#[25=AT04-07\r\n] 2006.239.07:42:19.05#ibcon#*before write, iclass 40, count 2 2006.239.07:42:19.05#ibcon#enter sib2, iclass 40, count 2 2006.239.07:42:19.05#ibcon#flushed, iclass 40, count 2 2006.239.07:42:19.05#ibcon#about to write, iclass 40, count 2 2006.239.07:42:19.05#ibcon#wrote, iclass 40, count 2 2006.239.07:42:19.05#ibcon#about to read 3, iclass 40, count 2 2006.239.07:42:19.08#ibcon#read 3, iclass 40, count 2 2006.239.07:42:19.08#ibcon#about to read 4, iclass 40, count 2 2006.239.07:42:19.08#ibcon#read 4, iclass 40, count 2 2006.239.07:42:19.08#ibcon#about to read 5, iclass 40, count 2 2006.239.07:42:19.08#ibcon#read 5, iclass 40, count 2 2006.239.07:42:19.08#ibcon#about to read 6, iclass 40, count 2 2006.239.07:42:19.08#ibcon#read 6, iclass 40, count 2 2006.239.07:42:19.08#ibcon#end of sib2, iclass 40, count 2 2006.239.07:42:19.08#ibcon#*after write, iclass 40, count 2 2006.239.07:42:19.08#ibcon#*before return 0, iclass 40, count 2 2006.239.07:42:19.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:19.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:19.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.07:42:19.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:19.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:19.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:19.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:19.20#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:42:19.20#ibcon#first serial, iclass 40, count 0 2006.239.07:42:19.20#ibcon#enter sib2, iclass 40, count 0 2006.239.07:42:19.20#ibcon#flushed, iclass 40, count 0 2006.239.07:42:19.20#ibcon#about to write, iclass 40, count 0 2006.239.07:42:19.20#ibcon#wrote, iclass 40, count 0 2006.239.07:42:19.20#ibcon#about to read 3, iclass 40, count 0 2006.239.07:42:19.22#ibcon#read 3, iclass 40, count 0 2006.239.07:42:19.22#ibcon#about to read 4, iclass 40, count 0 2006.239.07:42:19.22#ibcon#read 4, iclass 40, count 0 2006.239.07:42:19.22#ibcon#about to read 5, iclass 40, count 0 2006.239.07:42:19.22#ibcon#read 5, iclass 40, count 0 2006.239.07:42:19.22#ibcon#about to read 6, iclass 40, count 0 2006.239.07:42:19.22#ibcon#read 6, iclass 40, count 0 2006.239.07:42:19.22#ibcon#end of sib2, iclass 40, count 0 2006.239.07:42:19.22#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:42:19.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:42:19.22#ibcon#[25=USB\r\n] 2006.239.07:42:19.22#ibcon#*before write, iclass 40, count 0 2006.239.07:42:19.22#ibcon#enter sib2, iclass 40, count 0 2006.239.07:42:19.22#ibcon#flushed, iclass 40, count 0 2006.239.07:42:19.22#ibcon#about to write, iclass 40, count 0 2006.239.07:42:19.22#ibcon#wrote, iclass 40, count 0 2006.239.07:42:19.22#ibcon#about to read 3, iclass 40, count 0 2006.239.07:42:19.25#ibcon#read 3, iclass 40, count 0 2006.239.07:42:19.25#ibcon#about to read 4, iclass 40, count 0 2006.239.07:42:19.25#ibcon#read 4, iclass 40, count 0 2006.239.07:42:19.25#ibcon#about to read 5, iclass 40, count 0 2006.239.07:42:19.25#ibcon#read 5, iclass 40, count 0 2006.239.07:42:19.25#ibcon#about to read 6, iclass 40, count 0 2006.239.07:42:19.25#ibcon#read 6, iclass 40, count 0 2006.239.07:42:19.25#ibcon#end of sib2, iclass 40, count 0 2006.239.07:42:19.25#ibcon#*after write, iclass 40, count 0 2006.239.07:42:19.25#ibcon#*before return 0, iclass 40, count 0 2006.239.07:42:19.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:19.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:19.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:42:19.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:42:19.25$vc4f8/valo=5,652.99 2006.239.07:42:19.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:42:19.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:42:19.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:19.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:19.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:19.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:19.25#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:42:19.25#ibcon#first serial, iclass 4, count 0 2006.239.07:42:19.25#ibcon#enter sib2, iclass 4, count 0 2006.239.07:42:19.25#ibcon#flushed, iclass 4, count 0 2006.239.07:42:19.25#ibcon#about to write, iclass 4, count 0 2006.239.07:42:19.25#ibcon#wrote, iclass 4, count 0 2006.239.07:42:19.25#ibcon#about to read 3, iclass 4, count 0 2006.239.07:42:19.27#ibcon#read 3, iclass 4, count 0 2006.239.07:42:19.27#ibcon#about to read 4, iclass 4, count 0 2006.239.07:42:19.27#ibcon#read 4, iclass 4, count 0 2006.239.07:42:19.27#ibcon#about to read 5, iclass 4, count 0 2006.239.07:42:19.27#ibcon#read 5, iclass 4, count 0 2006.239.07:42:19.27#ibcon#about to read 6, iclass 4, count 0 2006.239.07:42:19.27#ibcon#read 6, iclass 4, count 0 2006.239.07:42:19.27#ibcon#end of sib2, iclass 4, count 0 2006.239.07:42:19.27#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:42:19.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:42:19.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:42:19.27#ibcon#*before write, iclass 4, count 0 2006.239.07:42:19.27#ibcon#enter sib2, iclass 4, count 0 2006.239.07:42:19.27#ibcon#flushed, iclass 4, count 0 2006.239.07:42:19.27#ibcon#about to write, iclass 4, count 0 2006.239.07:42:19.27#ibcon#wrote, iclass 4, count 0 2006.239.07:42:19.27#ibcon#about to read 3, iclass 4, count 0 2006.239.07:42:19.31#ibcon#read 3, iclass 4, count 0 2006.239.07:42:19.31#ibcon#about to read 4, iclass 4, count 0 2006.239.07:42:19.31#ibcon#read 4, iclass 4, count 0 2006.239.07:42:19.31#ibcon#about to read 5, iclass 4, count 0 2006.239.07:42:19.31#ibcon#read 5, iclass 4, count 0 2006.239.07:42:19.31#ibcon#about to read 6, iclass 4, count 0 2006.239.07:42:19.31#ibcon#read 6, iclass 4, count 0 2006.239.07:42:19.31#ibcon#end of sib2, iclass 4, count 0 2006.239.07:42:19.31#ibcon#*after write, iclass 4, count 0 2006.239.07:42:19.31#ibcon#*before return 0, iclass 4, count 0 2006.239.07:42:19.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:19.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:19.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:42:19.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:42:19.31$vc4f8/va=5,8 2006.239.07:42:19.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:42:19.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:42:19.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:19.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:19.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:19.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:19.37#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:42:19.37#ibcon#first serial, iclass 6, count 2 2006.239.07:42:19.37#ibcon#enter sib2, iclass 6, count 2 2006.239.07:42:19.37#ibcon#flushed, iclass 6, count 2 2006.239.07:42:19.37#ibcon#about to write, iclass 6, count 2 2006.239.07:42:19.37#ibcon#wrote, iclass 6, count 2 2006.239.07:42:19.37#ibcon#about to read 3, iclass 6, count 2 2006.239.07:42:19.39#ibcon#read 3, iclass 6, count 2 2006.239.07:42:19.39#ibcon#about to read 4, iclass 6, count 2 2006.239.07:42:19.39#ibcon#read 4, iclass 6, count 2 2006.239.07:42:19.39#ibcon#about to read 5, iclass 6, count 2 2006.239.07:42:19.39#ibcon#read 5, iclass 6, count 2 2006.239.07:42:19.39#ibcon#about to read 6, iclass 6, count 2 2006.239.07:42:19.39#ibcon#read 6, iclass 6, count 2 2006.239.07:42:19.39#ibcon#end of sib2, iclass 6, count 2 2006.239.07:42:19.39#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:42:19.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:42:19.39#ibcon#[25=AT05-08\r\n] 2006.239.07:42:19.39#ibcon#*before write, iclass 6, count 2 2006.239.07:42:19.39#ibcon#enter sib2, iclass 6, count 2 2006.239.07:42:19.39#ibcon#flushed, iclass 6, count 2 2006.239.07:42:19.39#ibcon#about to write, iclass 6, count 2 2006.239.07:42:19.39#ibcon#wrote, iclass 6, count 2 2006.239.07:42:19.39#ibcon#about to read 3, iclass 6, count 2 2006.239.07:42:19.42#ibcon#read 3, iclass 6, count 2 2006.239.07:42:19.42#ibcon#about to read 4, iclass 6, count 2 2006.239.07:42:19.42#ibcon#read 4, iclass 6, count 2 2006.239.07:42:19.42#ibcon#about to read 5, iclass 6, count 2 2006.239.07:42:19.42#ibcon#read 5, iclass 6, count 2 2006.239.07:42:19.42#ibcon#about to read 6, iclass 6, count 2 2006.239.07:42:19.42#ibcon#read 6, iclass 6, count 2 2006.239.07:42:19.42#ibcon#end of sib2, iclass 6, count 2 2006.239.07:42:19.42#ibcon#*after write, iclass 6, count 2 2006.239.07:42:19.42#ibcon#*before return 0, iclass 6, count 2 2006.239.07:42:19.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:19.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:19.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:42:19.42#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:19.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:19.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:19.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:19.54#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:42:19.54#ibcon#first serial, iclass 6, count 0 2006.239.07:42:19.54#ibcon#enter sib2, iclass 6, count 0 2006.239.07:42:19.54#ibcon#flushed, iclass 6, count 0 2006.239.07:42:19.54#ibcon#about to write, iclass 6, count 0 2006.239.07:42:19.54#ibcon#wrote, iclass 6, count 0 2006.239.07:42:19.54#ibcon#about to read 3, iclass 6, count 0 2006.239.07:42:19.56#ibcon#read 3, iclass 6, count 0 2006.239.07:42:19.56#ibcon#about to read 4, iclass 6, count 0 2006.239.07:42:19.56#ibcon#read 4, iclass 6, count 0 2006.239.07:42:19.56#ibcon#about to read 5, iclass 6, count 0 2006.239.07:42:19.56#ibcon#read 5, iclass 6, count 0 2006.239.07:42:19.56#ibcon#about to read 6, iclass 6, count 0 2006.239.07:42:19.56#ibcon#read 6, iclass 6, count 0 2006.239.07:42:19.56#ibcon#end of sib2, iclass 6, count 0 2006.239.07:42:19.56#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:42:19.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:42:19.56#ibcon#[25=USB\r\n] 2006.239.07:42:19.56#ibcon#*before write, iclass 6, count 0 2006.239.07:42:19.56#ibcon#enter sib2, iclass 6, count 0 2006.239.07:42:19.56#ibcon#flushed, iclass 6, count 0 2006.239.07:42:19.56#ibcon#about to write, iclass 6, count 0 2006.239.07:42:19.56#ibcon#wrote, iclass 6, count 0 2006.239.07:42:19.56#ibcon#about to read 3, iclass 6, count 0 2006.239.07:42:19.59#ibcon#read 3, iclass 6, count 0 2006.239.07:42:19.59#ibcon#about to read 4, iclass 6, count 0 2006.239.07:42:19.59#ibcon#read 4, iclass 6, count 0 2006.239.07:42:19.59#ibcon#about to read 5, iclass 6, count 0 2006.239.07:42:19.59#ibcon#read 5, iclass 6, count 0 2006.239.07:42:19.59#ibcon#about to read 6, iclass 6, count 0 2006.239.07:42:19.59#ibcon#read 6, iclass 6, count 0 2006.239.07:42:19.59#ibcon#end of sib2, iclass 6, count 0 2006.239.07:42:19.59#ibcon#*after write, iclass 6, count 0 2006.239.07:42:19.59#ibcon#*before return 0, iclass 6, count 0 2006.239.07:42:19.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:19.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:19.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:42:19.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:42:19.59$vc4f8/valo=6,772.99 2006.239.07:42:19.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:42:19.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:42:19.59#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:19.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:19.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:19.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:19.59#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:42:19.59#ibcon#first serial, iclass 10, count 0 2006.239.07:42:19.59#ibcon#enter sib2, iclass 10, count 0 2006.239.07:42:19.59#ibcon#flushed, iclass 10, count 0 2006.239.07:42:19.59#ibcon#about to write, iclass 10, count 0 2006.239.07:42:19.59#ibcon#wrote, iclass 10, count 0 2006.239.07:42:19.59#ibcon#about to read 3, iclass 10, count 0 2006.239.07:42:19.61#ibcon#read 3, iclass 10, count 0 2006.239.07:42:19.61#ibcon#about to read 4, iclass 10, count 0 2006.239.07:42:19.61#ibcon#read 4, iclass 10, count 0 2006.239.07:42:19.61#ibcon#about to read 5, iclass 10, count 0 2006.239.07:42:19.61#ibcon#read 5, iclass 10, count 0 2006.239.07:42:19.61#ibcon#about to read 6, iclass 10, count 0 2006.239.07:42:19.61#ibcon#read 6, iclass 10, count 0 2006.239.07:42:19.61#ibcon#end of sib2, iclass 10, count 0 2006.239.07:42:19.61#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:42:19.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:42:19.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:42:19.61#ibcon#*before write, iclass 10, count 0 2006.239.07:42:19.61#ibcon#enter sib2, iclass 10, count 0 2006.239.07:42:19.61#ibcon#flushed, iclass 10, count 0 2006.239.07:42:19.61#ibcon#about to write, iclass 10, count 0 2006.239.07:42:19.61#ibcon#wrote, iclass 10, count 0 2006.239.07:42:19.61#ibcon#about to read 3, iclass 10, count 0 2006.239.07:42:19.65#ibcon#read 3, iclass 10, count 0 2006.239.07:42:19.65#ibcon#about to read 4, iclass 10, count 0 2006.239.07:42:19.65#ibcon#read 4, iclass 10, count 0 2006.239.07:42:19.65#ibcon#about to read 5, iclass 10, count 0 2006.239.07:42:19.65#ibcon#read 5, iclass 10, count 0 2006.239.07:42:19.65#ibcon#about to read 6, iclass 10, count 0 2006.239.07:42:19.65#ibcon#read 6, iclass 10, count 0 2006.239.07:42:19.65#ibcon#end of sib2, iclass 10, count 0 2006.239.07:42:19.65#ibcon#*after write, iclass 10, count 0 2006.239.07:42:19.65#ibcon#*before return 0, iclass 10, count 0 2006.239.07:42:19.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:19.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:19.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:42:19.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:42:19.65$vc4f8/va=6,7 2006.239.07:42:19.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.07:42:19.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.07:42:19.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:19.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:42:19.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:42:19.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:42:19.71#ibcon#enter wrdev, iclass 12, count 2 2006.239.07:42:19.71#ibcon#first serial, iclass 12, count 2 2006.239.07:42:19.71#ibcon#enter sib2, iclass 12, count 2 2006.239.07:42:19.71#ibcon#flushed, iclass 12, count 2 2006.239.07:42:19.71#ibcon#about to write, iclass 12, count 2 2006.239.07:42:19.71#ibcon#wrote, iclass 12, count 2 2006.239.07:42:19.71#ibcon#about to read 3, iclass 12, count 2 2006.239.07:42:19.73#ibcon#read 3, iclass 12, count 2 2006.239.07:42:19.73#ibcon#about to read 4, iclass 12, count 2 2006.239.07:42:19.73#ibcon#read 4, iclass 12, count 2 2006.239.07:42:19.73#ibcon#about to read 5, iclass 12, count 2 2006.239.07:42:19.73#ibcon#read 5, iclass 12, count 2 2006.239.07:42:19.73#ibcon#about to read 6, iclass 12, count 2 2006.239.07:42:19.73#ibcon#read 6, iclass 12, count 2 2006.239.07:42:19.73#ibcon#end of sib2, iclass 12, count 2 2006.239.07:42:19.73#ibcon#*mode == 0, iclass 12, count 2 2006.239.07:42:19.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.07:42:19.73#ibcon#[25=AT06-07\r\n] 2006.239.07:42:19.73#ibcon#*before write, iclass 12, count 2 2006.239.07:42:19.73#ibcon#enter sib2, iclass 12, count 2 2006.239.07:42:19.73#ibcon#flushed, iclass 12, count 2 2006.239.07:42:19.73#ibcon#about to write, iclass 12, count 2 2006.239.07:42:19.73#ibcon#wrote, iclass 12, count 2 2006.239.07:42:19.73#ibcon#about to read 3, iclass 12, count 2 2006.239.07:42:19.76#ibcon#read 3, iclass 12, count 2 2006.239.07:42:19.76#ibcon#about to read 4, iclass 12, count 2 2006.239.07:42:19.76#ibcon#read 4, iclass 12, count 2 2006.239.07:42:19.76#ibcon#about to read 5, iclass 12, count 2 2006.239.07:42:19.76#ibcon#read 5, iclass 12, count 2 2006.239.07:42:19.76#ibcon#about to read 6, iclass 12, count 2 2006.239.07:42:19.76#ibcon#read 6, iclass 12, count 2 2006.239.07:42:19.76#ibcon#end of sib2, iclass 12, count 2 2006.239.07:42:19.76#ibcon#*after write, iclass 12, count 2 2006.239.07:42:19.76#ibcon#*before return 0, iclass 12, count 2 2006.239.07:42:19.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:42:19.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:42:19.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.07:42:19.76#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:19.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:42:19.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:42:19.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:42:19.88#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:42:19.88#ibcon#first serial, iclass 12, count 0 2006.239.07:42:19.88#ibcon#enter sib2, iclass 12, count 0 2006.239.07:42:19.88#ibcon#flushed, iclass 12, count 0 2006.239.07:42:19.88#ibcon#about to write, iclass 12, count 0 2006.239.07:42:19.88#ibcon#wrote, iclass 12, count 0 2006.239.07:42:19.88#ibcon#about to read 3, iclass 12, count 0 2006.239.07:42:19.90#ibcon#read 3, iclass 12, count 0 2006.239.07:42:19.90#ibcon#about to read 4, iclass 12, count 0 2006.239.07:42:19.90#ibcon#read 4, iclass 12, count 0 2006.239.07:42:19.90#ibcon#about to read 5, iclass 12, count 0 2006.239.07:42:19.90#ibcon#read 5, iclass 12, count 0 2006.239.07:42:19.90#ibcon#about to read 6, iclass 12, count 0 2006.239.07:42:19.90#ibcon#read 6, iclass 12, count 0 2006.239.07:42:19.90#ibcon#end of sib2, iclass 12, count 0 2006.239.07:42:19.90#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:42:19.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:42:19.90#ibcon#[25=USB\r\n] 2006.239.07:42:19.90#ibcon#*before write, iclass 12, count 0 2006.239.07:42:19.90#ibcon#enter sib2, iclass 12, count 0 2006.239.07:42:19.90#ibcon#flushed, iclass 12, count 0 2006.239.07:42:19.90#ibcon#about to write, iclass 12, count 0 2006.239.07:42:19.90#ibcon#wrote, iclass 12, count 0 2006.239.07:42:19.90#ibcon#about to read 3, iclass 12, count 0 2006.239.07:42:19.93#ibcon#read 3, iclass 12, count 0 2006.239.07:42:19.93#ibcon#about to read 4, iclass 12, count 0 2006.239.07:42:19.93#ibcon#read 4, iclass 12, count 0 2006.239.07:42:19.93#ibcon#about to read 5, iclass 12, count 0 2006.239.07:42:19.93#ibcon#read 5, iclass 12, count 0 2006.239.07:42:19.93#ibcon#about to read 6, iclass 12, count 0 2006.239.07:42:19.93#ibcon#read 6, iclass 12, count 0 2006.239.07:42:19.93#ibcon#end of sib2, iclass 12, count 0 2006.239.07:42:19.93#ibcon#*after write, iclass 12, count 0 2006.239.07:42:19.93#ibcon#*before return 0, iclass 12, count 0 2006.239.07:42:19.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:42:19.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:42:19.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:42:19.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:42:19.93$vc4f8/valo=7,832.99 2006.239.07:42:19.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:42:19.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:42:19.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:19.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:42:19.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:42:19.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:42:19.93#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:42:19.93#ibcon#first serial, iclass 14, count 0 2006.239.07:42:19.93#ibcon#enter sib2, iclass 14, count 0 2006.239.07:42:19.93#ibcon#flushed, iclass 14, count 0 2006.239.07:42:19.93#ibcon#about to write, iclass 14, count 0 2006.239.07:42:19.93#ibcon#wrote, iclass 14, count 0 2006.239.07:42:19.93#ibcon#about to read 3, iclass 14, count 0 2006.239.07:42:19.95#ibcon#read 3, iclass 14, count 0 2006.239.07:42:19.95#ibcon#about to read 4, iclass 14, count 0 2006.239.07:42:19.95#ibcon#read 4, iclass 14, count 0 2006.239.07:42:19.95#ibcon#about to read 5, iclass 14, count 0 2006.239.07:42:19.95#ibcon#read 5, iclass 14, count 0 2006.239.07:42:19.95#ibcon#about to read 6, iclass 14, count 0 2006.239.07:42:19.95#ibcon#read 6, iclass 14, count 0 2006.239.07:42:19.95#ibcon#end of sib2, iclass 14, count 0 2006.239.07:42:19.95#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:42:19.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:42:19.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:42:19.95#ibcon#*before write, iclass 14, count 0 2006.239.07:42:19.95#ibcon#enter sib2, iclass 14, count 0 2006.239.07:42:19.95#ibcon#flushed, iclass 14, count 0 2006.239.07:42:19.95#ibcon#about to write, iclass 14, count 0 2006.239.07:42:19.95#ibcon#wrote, iclass 14, count 0 2006.239.07:42:19.95#ibcon#about to read 3, iclass 14, count 0 2006.239.07:42:19.99#ibcon#read 3, iclass 14, count 0 2006.239.07:42:19.99#ibcon#about to read 4, iclass 14, count 0 2006.239.07:42:19.99#ibcon#read 4, iclass 14, count 0 2006.239.07:42:19.99#ibcon#about to read 5, iclass 14, count 0 2006.239.07:42:19.99#ibcon#read 5, iclass 14, count 0 2006.239.07:42:19.99#ibcon#about to read 6, iclass 14, count 0 2006.239.07:42:19.99#ibcon#read 6, iclass 14, count 0 2006.239.07:42:19.99#ibcon#end of sib2, iclass 14, count 0 2006.239.07:42:19.99#ibcon#*after write, iclass 14, count 0 2006.239.07:42:19.99#ibcon#*before return 0, iclass 14, count 0 2006.239.07:42:19.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:42:19.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:42:19.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:42:19.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:42:19.99$vc4f8/va=7,7 2006.239.07:42:19.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:42:19.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:42:19.99#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:19.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:42:20.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:42:20.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:42:20.05#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:42:20.05#ibcon#first serial, iclass 16, count 2 2006.239.07:42:20.05#ibcon#enter sib2, iclass 16, count 2 2006.239.07:42:20.05#ibcon#flushed, iclass 16, count 2 2006.239.07:42:20.05#ibcon#about to write, iclass 16, count 2 2006.239.07:42:20.05#ibcon#wrote, iclass 16, count 2 2006.239.07:42:20.05#ibcon#about to read 3, iclass 16, count 2 2006.239.07:42:20.07#ibcon#read 3, iclass 16, count 2 2006.239.07:42:20.07#ibcon#about to read 4, iclass 16, count 2 2006.239.07:42:20.07#ibcon#read 4, iclass 16, count 2 2006.239.07:42:20.07#ibcon#about to read 5, iclass 16, count 2 2006.239.07:42:20.07#ibcon#read 5, iclass 16, count 2 2006.239.07:42:20.07#ibcon#about to read 6, iclass 16, count 2 2006.239.07:42:20.07#ibcon#read 6, iclass 16, count 2 2006.239.07:42:20.07#ibcon#end of sib2, iclass 16, count 2 2006.239.07:42:20.07#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:42:20.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:42:20.07#ibcon#[25=AT07-07\r\n] 2006.239.07:42:20.07#ibcon#*before write, iclass 16, count 2 2006.239.07:42:20.07#ibcon#enter sib2, iclass 16, count 2 2006.239.07:42:20.07#ibcon#flushed, iclass 16, count 2 2006.239.07:42:20.07#ibcon#about to write, iclass 16, count 2 2006.239.07:42:20.07#ibcon#wrote, iclass 16, count 2 2006.239.07:42:20.07#ibcon#about to read 3, iclass 16, count 2 2006.239.07:42:20.11#ibcon#read 3, iclass 16, count 2 2006.239.07:42:20.11#ibcon#about to read 4, iclass 16, count 2 2006.239.07:42:20.11#ibcon#read 4, iclass 16, count 2 2006.239.07:42:20.11#ibcon#about to read 5, iclass 16, count 2 2006.239.07:42:20.11#ibcon#read 5, iclass 16, count 2 2006.239.07:42:20.11#ibcon#about to read 6, iclass 16, count 2 2006.239.07:42:20.11#ibcon#read 6, iclass 16, count 2 2006.239.07:42:20.11#ibcon#end of sib2, iclass 16, count 2 2006.239.07:42:20.11#ibcon#*after write, iclass 16, count 2 2006.239.07:42:20.11#ibcon#*before return 0, iclass 16, count 2 2006.239.07:42:20.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:42:20.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:42:20.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:42:20.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:20.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:42:20.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:42:20.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:42:20.22#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:42:20.22#ibcon#first serial, iclass 16, count 0 2006.239.07:42:20.22#ibcon#enter sib2, iclass 16, count 0 2006.239.07:42:20.22#ibcon#flushed, iclass 16, count 0 2006.239.07:42:20.22#ibcon#about to write, iclass 16, count 0 2006.239.07:42:20.22#ibcon#wrote, iclass 16, count 0 2006.239.07:42:20.22#ibcon#about to read 3, iclass 16, count 0 2006.239.07:42:20.25#ibcon#read 3, iclass 16, count 0 2006.239.07:42:20.25#ibcon#about to read 4, iclass 16, count 0 2006.239.07:42:20.25#ibcon#read 4, iclass 16, count 0 2006.239.07:42:20.25#ibcon#about to read 5, iclass 16, count 0 2006.239.07:42:20.25#ibcon#read 5, iclass 16, count 0 2006.239.07:42:20.25#ibcon#about to read 6, iclass 16, count 0 2006.239.07:42:20.25#ibcon#read 6, iclass 16, count 0 2006.239.07:42:20.25#ibcon#end of sib2, iclass 16, count 0 2006.239.07:42:20.25#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:42:20.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:42:20.25#ibcon#[25=USB\r\n] 2006.239.07:42:20.25#ibcon#*before write, iclass 16, count 0 2006.239.07:42:20.25#ibcon#enter sib2, iclass 16, count 0 2006.239.07:42:20.25#ibcon#flushed, iclass 16, count 0 2006.239.07:42:20.25#ibcon#about to write, iclass 16, count 0 2006.239.07:42:20.25#ibcon#wrote, iclass 16, count 0 2006.239.07:42:20.25#ibcon#about to read 3, iclass 16, count 0 2006.239.07:42:20.27#ibcon#read 3, iclass 16, count 0 2006.239.07:42:20.27#ibcon#about to read 4, iclass 16, count 0 2006.239.07:42:20.27#ibcon#read 4, iclass 16, count 0 2006.239.07:42:20.27#ibcon#about to read 5, iclass 16, count 0 2006.239.07:42:20.27#ibcon#read 5, iclass 16, count 0 2006.239.07:42:20.27#ibcon#about to read 6, iclass 16, count 0 2006.239.07:42:20.27#ibcon#read 6, iclass 16, count 0 2006.239.07:42:20.27#ibcon#end of sib2, iclass 16, count 0 2006.239.07:42:20.27#ibcon#*after write, iclass 16, count 0 2006.239.07:42:20.27#ibcon#*before return 0, iclass 16, count 0 2006.239.07:42:20.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:42:20.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:42:20.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:42:20.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:42:20.27$vc4f8/valo=8,852.99 2006.239.07:42:20.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.07:42:20.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.07:42:20.27#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:20.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:42:20.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:42:20.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:42:20.27#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:42:20.27#ibcon#first serial, iclass 18, count 0 2006.239.07:42:20.27#ibcon#enter sib2, iclass 18, count 0 2006.239.07:42:20.27#ibcon#flushed, iclass 18, count 0 2006.239.07:42:20.27#ibcon#about to write, iclass 18, count 0 2006.239.07:42:20.27#ibcon#wrote, iclass 18, count 0 2006.239.07:42:20.27#ibcon#about to read 3, iclass 18, count 0 2006.239.07:42:20.29#ibcon#read 3, iclass 18, count 0 2006.239.07:42:20.29#ibcon#about to read 4, iclass 18, count 0 2006.239.07:42:20.29#ibcon#read 4, iclass 18, count 0 2006.239.07:42:20.29#ibcon#about to read 5, iclass 18, count 0 2006.239.07:42:20.29#ibcon#read 5, iclass 18, count 0 2006.239.07:42:20.29#ibcon#about to read 6, iclass 18, count 0 2006.239.07:42:20.29#ibcon#read 6, iclass 18, count 0 2006.239.07:42:20.29#ibcon#end of sib2, iclass 18, count 0 2006.239.07:42:20.29#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:42:20.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:42:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:42:20.29#ibcon#*before write, iclass 18, count 0 2006.239.07:42:20.29#ibcon#enter sib2, iclass 18, count 0 2006.239.07:42:20.29#ibcon#flushed, iclass 18, count 0 2006.239.07:42:20.29#ibcon#about to write, iclass 18, count 0 2006.239.07:42:20.29#ibcon#wrote, iclass 18, count 0 2006.239.07:42:20.29#ibcon#about to read 3, iclass 18, count 0 2006.239.07:42:20.33#ibcon#read 3, iclass 18, count 0 2006.239.07:42:20.33#ibcon#about to read 4, iclass 18, count 0 2006.239.07:42:20.33#ibcon#read 4, iclass 18, count 0 2006.239.07:42:20.33#ibcon#about to read 5, iclass 18, count 0 2006.239.07:42:20.33#ibcon#read 5, iclass 18, count 0 2006.239.07:42:20.33#ibcon#about to read 6, iclass 18, count 0 2006.239.07:42:20.33#ibcon#read 6, iclass 18, count 0 2006.239.07:42:20.33#ibcon#end of sib2, iclass 18, count 0 2006.239.07:42:20.33#ibcon#*after write, iclass 18, count 0 2006.239.07:42:20.33#ibcon#*before return 0, iclass 18, count 0 2006.239.07:42:20.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:42:20.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:42:20.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:42:20.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:42:20.33$vc4f8/va=8,7 2006.239.07:42:20.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.07:42:20.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.07:42:20.33#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:20.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:42:20.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:42:20.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:42:20.39#ibcon#enter wrdev, iclass 20, count 2 2006.239.07:42:20.39#ibcon#first serial, iclass 20, count 2 2006.239.07:42:20.39#ibcon#enter sib2, iclass 20, count 2 2006.239.07:42:20.39#ibcon#flushed, iclass 20, count 2 2006.239.07:42:20.39#ibcon#about to write, iclass 20, count 2 2006.239.07:42:20.39#ibcon#wrote, iclass 20, count 2 2006.239.07:42:20.39#ibcon#about to read 3, iclass 20, count 2 2006.239.07:42:20.41#ibcon#read 3, iclass 20, count 2 2006.239.07:42:20.41#ibcon#about to read 4, iclass 20, count 2 2006.239.07:42:20.41#ibcon#read 4, iclass 20, count 2 2006.239.07:42:20.41#ibcon#about to read 5, iclass 20, count 2 2006.239.07:42:20.41#ibcon#read 5, iclass 20, count 2 2006.239.07:42:20.41#ibcon#about to read 6, iclass 20, count 2 2006.239.07:42:20.41#ibcon#read 6, iclass 20, count 2 2006.239.07:42:20.41#ibcon#end of sib2, iclass 20, count 2 2006.239.07:42:20.41#ibcon#*mode == 0, iclass 20, count 2 2006.239.07:42:20.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.07:42:20.41#ibcon#[25=AT08-07\r\n] 2006.239.07:42:20.41#ibcon#*before write, iclass 20, count 2 2006.239.07:42:20.41#ibcon#enter sib2, iclass 20, count 2 2006.239.07:42:20.41#ibcon#flushed, iclass 20, count 2 2006.239.07:42:20.41#ibcon#about to write, iclass 20, count 2 2006.239.07:42:20.41#ibcon#wrote, iclass 20, count 2 2006.239.07:42:20.41#ibcon#about to read 3, iclass 20, count 2 2006.239.07:42:20.44#ibcon#read 3, iclass 20, count 2 2006.239.07:42:20.44#ibcon#about to read 4, iclass 20, count 2 2006.239.07:42:20.44#ibcon#read 4, iclass 20, count 2 2006.239.07:42:20.44#ibcon#about to read 5, iclass 20, count 2 2006.239.07:42:20.44#ibcon#read 5, iclass 20, count 2 2006.239.07:42:20.44#ibcon#about to read 6, iclass 20, count 2 2006.239.07:42:20.44#ibcon#read 6, iclass 20, count 2 2006.239.07:42:20.44#ibcon#end of sib2, iclass 20, count 2 2006.239.07:42:20.44#ibcon#*after write, iclass 20, count 2 2006.239.07:42:20.44#ibcon#*before return 0, iclass 20, count 2 2006.239.07:42:20.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:42:20.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:42:20.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.07:42:20.44#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:20.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:42:20.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:42:20.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:42:20.56#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:42:20.56#ibcon#first serial, iclass 20, count 0 2006.239.07:42:20.56#ibcon#enter sib2, iclass 20, count 0 2006.239.07:42:20.56#ibcon#flushed, iclass 20, count 0 2006.239.07:42:20.56#ibcon#about to write, iclass 20, count 0 2006.239.07:42:20.56#ibcon#wrote, iclass 20, count 0 2006.239.07:42:20.56#ibcon#about to read 3, iclass 20, count 0 2006.239.07:42:20.58#ibcon#read 3, iclass 20, count 0 2006.239.07:42:20.58#ibcon#about to read 4, iclass 20, count 0 2006.239.07:42:20.58#ibcon#read 4, iclass 20, count 0 2006.239.07:42:20.58#ibcon#about to read 5, iclass 20, count 0 2006.239.07:42:20.58#ibcon#read 5, iclass 20, count 0 2006.239.07:42:20.58#ibcon#about to read 6, iclass 20, count 0 2006.239.07:42:20.58#ibcon#read 6, iclass 20, count 0 2006.239.07:42:20.58#ibcon#end of sib2, iclass 20, count 0 2006.239.07:42:20.58#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:42:20.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:42:20.58#ibcon#[25=USB\r\n] 2006.239.07:42:20.58#ibcon#*before write, iclass 20, count 0 2006.239.07:42:20.58#ibcon#enter sib2, iclass 20, count 0 2006.239.07:42:20.58#ibcon#flushed, iclass 20, count 0 2006.239.07:42:20.58#ibcon#about to write, iclass 20, count 0 2006.239.07:42:20.58#ibcon#wrote, iclass 20, count 0 2006.239.07:42:20.58#ibcon#about to read 3, iclass 20, count 0 2006.239.07:42:20.61#ibcon#read 3, iclass 20, count 0 2006.239.07:42:20.61#ibcon#about to read 4, iclass 20, count 0 2006.239.07:42:20.61#ibcon#read 4, iclass 20, count 0 2006.239.07:42:20.61#ibcon#about to read 5, iclass 20, count 0 2006.239.07:42:20.61#ibcon#read 5, iclass 20, count 0 2006.239.07:42:20.61#ibcon#about to read 6, iclass 20, count 0 2006.239.07:42:20.61#ibcon#read 6, iclass 20, count 0 2006.239.07:42:20.61#ibcon#end of sib2, iclass 20, count 0 2006.239.07:42:20.61#ibcon#*after write, iclass 20, count 0 2006.239.07:42:20.61#ibcon#*before return 0, iclass 20, count 0 2006.239.07:42:20.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:42:20.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:42:20.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:42:20.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:42:20.61$vc4f8/vblo=1,632.99 2006.239.07:42:20.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.07:42:20.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.07:42:20.61#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:20.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:42:20.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:42:20.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:42:20.61#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:42:20.61#ibcon#first serial, iclass 22, count 0 2006.239.07:42:20.61#ibcon#enter sib2, iclass 22, count 0 2006.239.07:42:20.61#ibcon#flushed, iclass 22, count 0 2006.239.07:42:20.61#ibcon#about to write, iclass 22, count 0 2006.239.07:42:20.61#ibcon#wrote, iclass 22, count 0 2006.239.07:42:20.61#ibcon#about to read 3, iclass 22, count 0 2006.239.07:42:20.63#ibcon#read 3, iclass 22, count 0 2006.239.07:42:20.63#ibcon#about to read 4, iclass 22, count 0 2006.239.07:42:20.63#ibcon#read 4, iclass 22, count 0 2006.239.07:42:20.63#ibcon#about to read 5, iclass 22, count 0 2006.239.07:42:20.63#ibcon#read 5, iclass 22, count 0 2006.239.07:42:20.63#ibcon#about to read 6, iclass 22, count 0 2006.239.07:42:20.63#ibcon#read 6, iclass 22, count 0 2006.239.07:42:20.63#ibcon#end of sib2, iclass 22, count 0 2006.239.07:42:20.63#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:42:20.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:42:20.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:42:20.63#ibcon#*before write, iclass 22, count 0 2006.239.07:42:20.63#ibcon#enter sib2, iclass 22, count 0 2006.239.07:42:20.63#ibcon#flushed, iclass 22, count 0 2006.239.07:42:20.63#ibcon#about to write, iclass 22, count 0 2006.239.07:42:20.63#ibcon#wrote, iclass 22, count 0 2006.239.07:42:20.63#ibcon#about to read 3, iclass 22, count 0 2006.239.07:42:20.67#ibcon#read 3, iclass 22, count 0 2006.239.07:42:20.67#ibcon#about to read 4, iclass 22, count 0 2006.239.07:42:20.67#ibcon#read 4, iclass 22, count 0 2006.239.07:42:20.67#ibcon#about to read 5, iclass 22, count 0 2006.239.07:42:20.67#ibcon#read 5, iclass 22, count 0 2006.239.07:42:20.67#ibcon#about to read 6, iclass 22, count 0 2006.239.07:42:20.67#ibcon#read 6, iclass 22, count 0 2006.239.07:42:20.67#ibcon#end of sib2, iclass 22, count 0 2006.239.07:42:20.67#ibcon#*after write, iclass 22, count 0 2006.239.07:42:20.67#ibcon#*before return 0, iclass 22, count 0 2006.239.07:42:20.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:42:20.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:42:20.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:42:20.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:42:20.67$vc4f8/vb=1,4 2006.239.07:42:20.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.07:42:20.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.07:42:20.67#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:20.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:42:20.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:42:20.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:42:20.67#ibcon#enter wrdev, iclass 24, count 2 2006.239.07:42:20.67#ibcon#first serial, iclass 24, count 2 2006.239.07:42:20.67#ibcon#enter sib2, iclass 24, count 2 2006.239.07:42:20.67#ibcon#flushed, iclass 24, count 2 2006.239.07:42:20.67#ibcon#about to write, iclass 24, count 2 2006.239.07:42:20.67#ibcon#wrote, iclass 24, count 2 2006.239.07:42:20.67#ibcon#about to read 3, iclass 24, count 2 2006.239.07:42:20.69#ibcon#read 3, iclass 24, count 2 2006.239.07:42:20.69#ibcon#about to read 4, iclass 24, count 2 2006.239.07:42:20.69#ibcon#read 4, iclass 24, count 2 2006.239.07:42:20.69#ibcon#about to read 5, iclass 24, count 2 2006.239.07:42:20.69#ibcon#read 5, iclass 24, count 2 2006.239.07:42:20.69#ibcon#about to read 6, iclass 24, count 2 2006.239.07:42:20.69#ibcon#read 6, iclass 24, count 2 2006.239.07:42:20.69#ibcon#end of sib2, iclass 24, count 2 2006.239.07:42:20.69#ibcon#*mode == 0, iclass 24, count 2 2006.239.07:42:20.69#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.07:42:20.69#ibcon#[27=AT01-04\r\n] 2006.239.07:42:20.69#ibcon#*before write, iclass 24, count 2 2006.239.07:42:20.69#ibcon#enter sib2, iclass 24, count 2 2006.239.07:42:20.69#ibcon#flushed, iclass 24, count 2 2006.239.07:42:20.69#ibcon#about to write, iclass 24, count 2 2006.239.07:42:20.69#ibcon#wrote, iclass 24, count 2 2006.239.07:42:20.69#ibcon#about to read 3, iclass 24, count 2 2006.239.07:42:20.72#ibcon#read 3, iclass 24, count 2 2006.239.07:42:20.72#ibcon#about to read 4, iclass 24, count 2 2006.239.07:42:20.72#ibcon#read 4, iclass 24, count 2 2006.239.07:42:20.72#ibcon#about to read 5, iclass 24, count 2 2006.239.07:42:20.72#ibcon#read 5, iclass 24, count 2 2006.239.07:42:20.72#ibcon#about to read 6, iclass 24, count 2 2006.239.07:42:20.72#ibcon#read 6, iclass 24, count 2 2006.239.07:42:20.72#ibcon#end of sib2, iclass 24, count 2 2006.239.07:42:20.72#ibcon#*after write, iclass 24, count 2 2006.239.07:42:20.72#ibcon#*before return 0, iclass 24, count 2 2006.239.07:42:20.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:42:20.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:42:20.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.07:42:20.72#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:20.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:42:20.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:42:20.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:42:20.84#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:42:20.84#ibcon#first serial, iclass 24, count 0 2006.239.07:42:20.84#ibcon#enter sib2, iclass 24, count 0 2006.239.07:42:20.84#ibcon#flushed, iclass 24, count 0 2006.239.07:42:20.84#ibcon#about to write, iclass 24, count 0 2006.239.07:42:20.84#ibcon#wrote, iclass 24, count 0 2006.239.07:42:20.84#ibcon#about to read 3, iclass 24, count 0 2006.239.07:42:20.86#ibcon#read 3, iclass 24, count 0 2006.239.07:42:20.86#ibcon#about to read 4, iclass 24, count 0 2006.239.07:42:20.86#ibcon#read 4, iclass 24, count 0 2006.239.07:42:20.86#ibcon#about to read 5, iclass 24, count 0 2006.239.07:42:20.86#ibcon#read 5, iclass 24, count 0 2006.239.07:42:20.86#ibcon#about to read 6, iclass 24, count 0 2006.239.07:42:20.86#ibcon#read 6, iclass 24, count 0 2006.239.07:42:20.86#ibcon#end of sib2, iclass 24, count 0 2006.239.07:42:20.86#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:42:20.86#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:42:20.86#ibcon#[27=USB\r\n] 2006.239.07:42:20.86#ibcon#*before write, iclass 24, count 0 2006.239.07:42:20.86#ibcon#enter sib2, iclass 24, count 0 2006.239.07:42:20.86#ibcon#flushed, iclass 24, count 0 2006.239.07:42:20.86#ibcon#about to write, iclass 24, count 0 2006.239.07:42:20.86#ibcon#wrote, iclass 24, count 0 2006.239.07:42:20.86#ibcon#about to read 3, iclass 24, count 0 2006.239.07:42:20.89#ibcon#read 3, iclass 24, count 0 2006.239.07:42:20.89#ibcon#about to read 4, iclass 24, count 0 2006.239.07:42:20.89#ibcon#read 4, iclass 24, count 0 2006.239.07:42:20.89#ibcon#about to read 5, iclass 24, count 0 2006.239.07:42:20.89#ibcon#read 5, iclass 24, count 0 2006.239.07:42:20.89#ibcon#about to read 6, iclass 24, count 0 2006.239.07:42:20.89#ibcon#read 6, iclass 24, count 0 2006.239.07:42:20.89#ibcon#end of sib2, iclass 24, count 0 2006.239.07:42:20.89#ibcon#*after write, iclass 24, count 0 2006.239.07:42:20.89#ibcon#*before return 0, iclass 24, count 0 2006.239.07:42:20.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:42:20.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:42:20.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:42:20.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:42:20.89$vc4f8/vblo=2,640.99 2006.239.07:42:20.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:42:20.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:42:20.89#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:20.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:20.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:20.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:20.89#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:42:20.89#ibcon#first serial, iclass 26, count 0 2006.239.07:42:20.89#ibcon#enter sib2, iclass 26, count 0 2006.239.07:42:20.89#ibcon#flushed, iclass 26, count 0 2006.239.07:42:20.89#ibcon#about to write, iclass 26, count 0 2006.239.07:42:20.89#ibcon#wrote, iclass 26, count 0 2006.239.07:42:20.89#ibcon#about to read 3, iclass 26, count 0 2006.239.07:42:20.91#ibcon#read 3, iclass 26, count 0 2006.239.07:42:20.91#ibcon#about to read 4, iclass 26, count 0 2006.239.07:42:20.91#ibcon#read 4, iclass 26, count 0 2006.239.07:42:20.91#ibcon#about to read 5, iclass 26, count 0 2006.239.07:42:20.91#ibcon#read 5, iclass 26, count 0 2006.239.07:42:20.91#ibcon#about to read 6, iclass 26, count 0 2006.239.07:42:20.91#ibcon#read 6, iclass 26, count 0 2006.239.07:42:20.91#ibcon#end of sib2, iclass 26, count 0 2006.239.07:42:20.91#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:42:20.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:42:20.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:42:20.91#ibcon#*before write, iclass 26, count 0 2006.239.07:42:20.91#ibcon#enter sib2, iclass 26, count 0 2006.239.07:42:20.91#ibcon#flushed, iclass 26, count 0 2006.239.07:42:20.91#ibcon#about to write, iclass 26, count 0 2006.239.07:42:20.91#ibcon#wrote, iclass 26, count 0 2006.239.07:42:20.91#ibcon#about to read 3, iclass 26, count 0 2006.239.07:42:20.95#ibcon#read 3, iclass 26, count 0 2006.239.07:42:20.95#ibcon#about to read 4, iclass 26, count 0 2006.239.07:42:20.95#ibcon#read 4, iclass 26, count 0 2006.239.07:42:20.95#ibcon#about to read 5, iclass 26, count 0 2006.239.07:42:20.95#ibcon#read 5, iclass 26, count 0 2006.239.07:42:20.95#ibcon#about to read 6, iclass 26, count 0 2006.239.07:42:20.95#ibcon#read 6, iclass 26, count 0 2006.239.07:42:20.95#ibcon#end of sib2, iclass 26, count 0 2006.239.07:42:20.95#ibcon#*after write, iclass 26, count 0 2006.239.07:42:20.95#ibcon#*before return 0, iclass 26, count 0 2006.239.07:42:20.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:20.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:42:20.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:42:20.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:42:20.95$vc4f8/vb=2,4 2006.239.07:42:20.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:42:20.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:42:20.95#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:20.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:21.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:21.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:21.01#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:42:21.01#ibcon#first serial, iclass 28, count 2 2006.239.07:42:21.01#ibcon#enter sib2, iclass 28, count 2 2006.239.07:42:21.01#ibcon#flushed, iclass 28, count 2 2006.239.07:42:21.01#ibcon#about to write, iclass 28, count 2 2006.239.07:42:21.01#ibcon#wrote, iclass 28, count 2 2006.239.07:42:21.01#ibcon#about to read 3, iclass 28, count 2 2006.239.07:42:21.03#ibcon#read 3, iclass 28, count 2 2006.239.07:42:21.03#ibcon#about to read 4, iclass 28, count 2 2006.239.07:42:21.03#ibcon#read 4, iclass 28, count 2 2006.239.07:42:21.03#ibcon#about to read 5, iclass 28, count 2 2006.239.07:42:21.03#ibcon#read 5, iclass 28, count 2 2006.239.07:42:21.03#ibcon#about to read 6, iclass 28, count 2 2006.239.07:42:21.03#ibcon#read 6, iclass 28, count 2 2006.239.07:42:21.03#ibcon#end of sib2, iclass 28, count 2 2006.239.07:42:21.03#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:42:21.03#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:42:21.03#ibcon#[27=AT02-04\r\n] 2006.239.07:42:21.03#ibcon#*before write, iclass 28, count 2 2006.239.07:42:21.03#ibcon#enter sib2, iclass 28, count 2 2006.239.07:42:21.03#ibcon#flushed, iclass 28, count 2 2006.239.07:42:21.03#ibcon#about to write, iclass 28, count 2 2006.239.07:42:21.03#ibcon#wrote, iclass 28, count 2 2006.239.07:42:21.03#ibcon#about to read 3, iclass 28, count 2 2006.239.07:42:21.06#ibcon#read 3, iclass 28, count 2 2006.239.07:42:21.06#ibcon#about to read 4, iclass 28, count 2 2006.239.07:42:21.06#ibcon#read 4, iclass 28, count 2 2006.239.07:42:21.06#ibcon#about to read 5, iclass 28, count 2 2006.239.07:42:21.06#ibcon#read 5, iclass 28, count 2 2006.239.07:42:21.06#ibcon#about to read 6, iclass 28, count 2 2006.239.07:42:21.06#ibcon#read 6, iclass 28, count 2 2006.239.07:42:21.06#ibcon#end of sib2, iclass 28, count 2 2006.239.07:42:21.06#ibcon#*after write, iclass 28, count 2 2006.239.07:42:21.06#ibcon#*before return 0, iclass 28, count 2 2006.239.07:42:21.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:21.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:42:21.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:42:21.06#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:21.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:21.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:21.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:21.18#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:42:21.18#ibcon#first serial, iclass 28, count 0 2006.239.07:42:21.18#ibcon#enter sib2, iclass 28, count 0 2006.239.07:42:21.18#ibcon#flushed, iclass 28, count 0 2006.239.07:42:21.18#ibcon#about to write, iclass 28, count 0 2006.239.07:42:21.18#ibcon#wrote, iclass 28, count 0 2006.239.07:42:21.18#ibcon#about to read 3, iclass 28, count 0 2006.239.07:42:21.20#ibcon#read 3, iclass 28, count 0 2006.239.07:42:21.20#ibcon#about to read 4, iclass 28, count 0 2006.239.07:42:21.20#ibcon#read 4, iclass 28, count 0 2006.239.07:42:21.20#ibcon#about to read 5, iclass 28, count 0 2006.239.07:42:21.20#ibcon#read 5, iclass 28, count 0 2006.239.07:42:21.20#ibcon#about to read 6, iclass 28, count 0 2006.239.07:42:21.20#ibcon#read 6, iclass 28, count 0 2006.239.07:42:21.20#ibcon#end of sib2, iclass 28, count 0 2006.239.07:42:21.20#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:42:21.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:42:21.20#ibcon#[27=USB\r\n] 2006.239.07:42:21.20#ibcon#*before write, iclass 28, count 0 2006.239.07:42:21.20#ibcon#enter sib2, iclass 28, count 0 2006.239.07:42:21.20#ibcon#flushed, iclass 28, count 0 2006.239.07:42:21.20#ibcon#about to write, iclass 28, count 0 2006.239.07:42:21.20#ibcon#wrote, iclass 28, count 0 2006.239.07:42:21.20#ibcon#about to read 3, iclass 28, count 0 2006.239.07:42:21.23#ibcon#read 3, iclass 28, count 0 2006.239.07:42:21.23#ibcon#about to read 4, iclass 28, count 0 2006.239.07:42:21.23#ibcon#read 4, iclass 28, count 0 2006.239.07:42:21.23#ibcon#about to read 5, iclass 28, count 0 2006.239.07:42:21.23#ibcon#read 5, iclass 28, count 0 2006.239.07:42:21.23#ibcon#about to read 6, iclass 28, count 0 2006.239.07:42:21.23#ibcon#read 6, iclass 28, count 0 2006.239.07:42:21.23#ibcon#end of sib2, iclass 28, count 0 2006.239.07:42:21.23#ibcon#*after write, iclass 28, count 0 2006.239.07:42:21.23#ibcon#*before return 0, iclass 28, count 0 2006.239.07:42:21.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:21.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:42:21.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:42:21.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:42:21.23$vc4f8/vblo=3,656.99 2006.239.07:42:21.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:42:21.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:42:21.23#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:21.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:21.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:21.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:21.23#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:42:21.23#ibcon#first serial, iclass 30, count 0 2006.239.07:42:21.23#ibcon#enter sib2, iclass 30, count 0 2006.239.07:42:21.23#ibcon#flushed, iclass 30, count 0 2006.239.07:42:21.23#ibcon#about to write, iclass 30, count 0 2006.239.07:42:21.23#ibcon#wrote, iclass 30, count 0 2006.239.07:42:21.23#ibcon#about to read 3, iclass 30, count 0 2006.239.07:42:21.25#ibcon#read 3, iclass 30, count 0 2006.239.07:42:21.25#ibcon#about to read 4, iclass 30, count 0 2006.239.07:42:21.25#ibcon#read 4, iclass 30, count 0 2006.239.07:42:21.25#ibcon#about to read 5, iclass 30, count 0 2006.239.07:42:21.25#ibcon#read 5, iclass 30, count 0 2006.239.07:42:21.25#ibcon#about to read 6, iclass 30, count 0 2006.239.07:42:21.25#ibcon#read 6, iclass 30, count 0 2006.239.07:42:21.25#ibcon#end of sib2, iclass 30, count 0 2006.239.07:42:21.25#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:42:21.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:42:21.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:42:21.25#ibcon#*before write, iclass 30, count 0 2006.239.07:42:21.25#ibcon#enter sib2, iclass 30, count 0 2006.239.07:42:21.25#ibcon#flushed, iclass 30, count 0 2006.239.07:42:21.25#ibcon#about to write, iclass 30, count 0 2006.239.07:42:21.25#ibcon#wrote, iclass 30, count 0 2006.239.07:42:21.25#ibcon#about to read 3, iclass 30, count 0 2006.239.07:42:21.29#ibcon#read 3, iclass 30, count 0 2006.239.07:42:21.29#ibcon#about to read 4, iclass 30, count 0 2006.239.07:42:21.29#ibcon#read 4, iclass 30, count 0 2006.239.07:42:21.29#ibcon#about to read 5, iclass 30, count 0 2006.239.07:42:21.29#ibcon#read 5, iclass 30, count 0 2006.239.07:42:21.29#ibcon#about to read 6, iclass 30, count 0 2006.239.07:42:21.29#ibcon#read 6, iclass 30, count 0 2006.239.07:42:21.29#ibcon#end of sib2, iclass 30, count 0 2006.239.07:42:21.29#ibcon#*after write, iclass 30, count 0 2006.239.07:42:21.29#ibcon#*before return 0, iclass 30, count 0 2006.239.07:42:21.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:21.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:42:21.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:42:21.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:42:21.29$vc4f8/vb=3,4 2006.239.07:42:21.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:42:21.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:42:21.29#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:21.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:21.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:21.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:21.35#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:42:21.35#ibcon#first serial, iclass 32, count 2 2006.239.07:42:21.35#ibcon#enter sib2, iclass 32, count 2 2006.239.07:42:21.35#ibcon#flushed, iclass 32, count 2 2006.239.07:42:21.35#ibcon#about to write, iclass 32, count 2 2006.239.07:42:21.35#ibcon#wrote, iclass 32, count 2 2006.239.07:42:21.35#ibcon#about to read 3, iclass 32, count 2 2006.239.07:42:21.37#ibcon#read 3, iclass 32, count 2 2006.239.07:42:21.37#ibcon#about to read 4, iclass 32, count 2 2006.239.07:42:21.37#ibcon#read 4, iclass 32, count 2 2006.239.07:42:21.37#ibcon#about to read 5, iclass 32, count 2 2006.239.07:42:21.37#ibcon#read 5, iclass 32, count 2 2006.239.07:42:21.37#ibcon#about to read 6, iclass 32, count 2 2006.239.07:42:21.37#ibcon#read 6, iclass 32, count 2 2006.239.07:42:21.37#ibcon#end of sib2, iclass 32, count 2 2006.239.07:42:21.37#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:42:21.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:42:21.37#ibcon#[27=AT03-04\r\n] 2006.239.07:42:21.37#ibcon#*before write, iclass 32, count 2 2006.239.07:42:21.37#ibcon#enter sib2, iclass 32, count 2 2006.239.07:42:21.37#ibcon#flushed, iclass 32, count 2 2006.239.07:42:21.37#ibcon#about to write, iclass 32, count 2 2006.239.07:42:21.37#ibcon#wrote, iclass 32, count 2 2006.239.07:42:21.37#ibcon#about to read 3, iclass 32, count 2 2006.239.07:42:21.40#ibcon#read 3, iclass 32, count 2 2006.239.07:42:21.40#ibcon#about to read 4, iclass 32, count 2 2006.239.07:42:21.40#ibcon#read 4, iclass 32, count 2 2006.239.07:42:21.40#ibcon#about to read 5, iclass 32, count 2 2006.239.07:42:21.40#ibcon#read 5, iclass 32, count 2 2006.239.07:42:21.40#ibcon#about to read 6, iclass 32, count 2 2006.239.07:42:21.40#ibcon#read 6, iclass 32, count 2 2006.239.07:42:21.40#ibcon#end of sib2, iclass 32, count 2 2006.239.07:42:21.40#ibcon#*after write, iclass 32, count 2 2006.239.07:42:21.40#ibcon#*before return 0, iclass 32, count 2 2006.239.07:42:21.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:21.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:42:21.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:42:21.40#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:21.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:21.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:21.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:21.52#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:42:21.52#ibcon#first serial, iclass 32, count 0 2006.239.07:42:21.52#ibcon#enter sib2, iclass 32, count 0 2006.239.07:42:21.52#ibcon#flushed, iclass 32, count 0 2006.239.07:42:21.52#ibcon#about to write, iclass 32, count 0 2006.239.07:42:21.52#ibcon#wrote, iclass 32, count 0 2006.239.07:42:21.52#ibcon#about to read 3, iclass 32, count 0 2006.239.07:42:21.54#ibcon#read 3, iclass 32, count 0 2006.239.07:42:21.54#ibcon#about to read 4, iclass 32, count 0 2006.239.07:42:21.54#ibcon#read 4, iclass 32, count 0 2006.239.07:42:21.54#ibcon#about to read 5, iclass 32, count 0 2006.239.07:42:21.54#ibcon#read 5, iclass 32, count 0 2006.239.07:42:21.54#ibcon#about to read 6, iclass 32, count 0 2006.239.07:42:21.54#ibcon#read 6, iclass 32, count 0 2006.239.07:42:21.54#ibcon#end of sib2, iclass 32, count 0 2006.239.07:42:21.54#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:42:21.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:42:21.54#ibcon#[27=USB\r\n] 2006.239.07:42:21.54#ibcon#*before write, iclass 32, count 0 2006.239.07:42:21.54#ibcon#enter sib2, iclass 32, count 0 2006.239.07:42:21.54#ibcon#flushed, iclass 32, count 0 2006.239.07:42:21.54#ibcon#about to write, iclass 32, count 0 2006.239.07:42:21.54#ibcon#wrote, iclass 32, count 0 2006.239.07:42:21.54#ibcon#about to read 3, iclass 32, count 0 2006.239.07:42:21.57#ibcon#read 3, iclass 32, count 0 2006.239.07:42:21.57#ibcon#about to read 4, iclass 32, count 0 2006.239.07:42:21.57#ibcon#read 4, iclass 32, count 0 2006.239.07:42:21.57#ibcon#about to read 5, iclass 32, count 0 2006.239.07:42:21.57#ibcon#read 5, iclass 32, count 0 2006.239.07:42:21.57#ibcon#about to read 6, iclass 32, count 0 2006.239.07:42:21.57#ibcon#read 6, iclass 32, count 0 2006.239.07:42:21.57#ibcon#end of sib2, iclass 32, count 0 2006.239.07:42:21.57#ibcon#*after write, iclass 32, count 0 2006.239.07:42:21.57#ibcon#*before return 0, iclass 32, count 0 2006.239.07:42:21.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:21.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:42:21.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:42:21.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:42:21.57$vc4f8/vblo=4,712.99 2006.239.07:42:21.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:42:21.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:42:21.57#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:21.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:21.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:21.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:21.57#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:42:21.57#ibcon#first serial, iclass 34, count 0 2006.239.07:42:21.57#ibcon#enter sib2, iclass 34, count 0 2006.239.07:42:21.57#ibcon#flushed, iclass 34, count 0 2006.239.07:42:21.57#ibcon#about to write, iclass 34, count 0 2006.239.07:42:21.57#ibcon#wrote, iclass 34, count 0 2006.239.07:42:21.57#ibcon#about to read 3, iclass 34, count 0 2006.239.07:42:21.60#ibcon#read 3, iclass 34, count 0 2006.239.07:42:21.60#ibcon#about to read 4, iclass 34, count 0 2006.239.07:42:21.60#ibcon#read 4, iclass 34, count 0 2006.239.07:42:21.60#ibcon#about to read 5, iclass 34, count 0 2006.239.07:42:21.60#ibcon#read 5, iclass 34, count 0 2006.239.07:42:21.60#ibcon#about to read 6, iclass 34, count 0 2006.239.07:42:21.60#ibcon#read 6, iclass 34, count 0 2006.239.07:42:21.60#ibcon#end of sib2, iclass 34, count 0 2006.239.07:42:21.60#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:42:21.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:42:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:42:21.60#ibcon#*before write, iclass 34, count 0 2006.239.07:42:21.60#ibcon#enter sib2, iclass 34, count 0 2006.239.07:42:21.60#ibcon#flushed, iclass 34, count 0 2006.239.07:42:21.60#ibcon#about to write, iclass 34, count 0 2006.239.07:42:21.60#ibcon#wrote, iclass 34, count 0 2006.239.07:42:21.60#ibcon#about to read 3, iclass 34, count 0 2006.239.07:42:21.63#ibcon#read 3, iclass 34, count 0 2006.239.07:42:21.63#ibcon#about to read 4, iclass 34, count 0 2006.239.07:42:21.63#ibcon#read 4, iclass 34, count 0 2006.239.07:42:21.63#ibcon#about to read 5, iclass 34, count 0 2006.239.07:42:21.63#ibcon#read 5, iclass 34, count 0 2006.239.07:42:21.63#ibcon#about to read 6, iclass 34, count 0 2006.239.07:42:21.63#ibcon#read 6, iclass 34, count 0 2006.239.07:42:21.63#ibcon#end of sib2, iclass 34, count 0 2006.239.07:42:21.63#ibcon#*after write, iclass 34, count 0 2006.239.07:42:21.63#ibcon#*before return 0, iclass 34, count 0 2006.239.07:42:21.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:21.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:42:21.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:42:21.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:42:21.63$vc4f8/vb=4,4 2006.239.07:42:21.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:42:21.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:42:21.63#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:21.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:21.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:21.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:21.69#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:42:21.69#ibcon#first serial, iclass 36, count 2 2006.239.07:42:21.69#ibcon#enter sib2, iclass 36, count 2 2006.239.07:42:21.69#ibcon#flushed, iclass 36, count 2 2006.239.07:42:21.69#ibcon#about to write, iclass 36, count 2 2006.239.07:42:21.69#ibcon#wrote, iclass 36, count 2 2006.239.07:42:21.69#ibcon#about to read 3, iclass 36, count 2 2006.239.07:42:21.71#ibcon#read 3, iclass 36, count 2 2006.239.07:42:21.71#ibcon#about to read 4, iclass 36, count 2 2006.239.07:42:21.71#ibcon#read 4, iclass 36, count 2 2006.239.07:42:21.71#ibcon#about to read 5, iclass 36, count 2 2006.239.07:42:21.71#ibcon#read 5, iclass 36, count 2 2006.239.07:42:21.71#ibcon#about to read 6, iclass 36, count 2 2006.239.07:42:21.71#ibcon#read 6, iclass 36, count 2 2006.239.07:42:21.71#ibcon#end of sib2, iclass 36, count 2 2006.239.07:42:21.71#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:42:21.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:42:21.71#ibcon#[27=AT04-04\r\n] 2006.239.07:42:21.71#ibcon#*before write, iclass 36, count 2 2006.239.07:42:21.71#ibcon#enter sib2, iclass 36, count 2 2006.239.07:42:21.71#ibcon#flushed, iclass 36, count 2 2006.239.07:42:21.71#ibcon#about to write, iclass 36, count 2 2006.239.07:42:21.71#ibcon#wrote, iclass 36, count 2 2006.239.07:42:21.71#ibcon#about to read 3, iclass 36, count 2 2006.239.07:42:21.74#ibcon#read 3, iclass 36, count 2 2006.239.07:42:21.74#ibcon#about to read 4, iclass 36, count 2 2006.239.07:42:21.74#ibcon#read 4, iclass 36, count 2 2006.239.07:42:21.74#ibcon#about to read 5, iclass 36, count 2 2006.239.07:42:21.74#ibcon#read 5, iclass 36, count 2 2006.239.07:42:21.74#ibcon#about to read 6, iclass 36, count 2 2006.239.07:42:21.74#ibcon#read 6, iclass 36, count 2 2006.239.07:42:21.74#ibcon#end of sib2, iclass 36, count 2 2006.239.07:42:21.74#ibcon#*after write, iclass 36, count 2 2006.239.07:42:21.74#ibcon#*before return 0, iclass 36, count 2 2006.239.07:42:21.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:21.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:42:21.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:42:21.74#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:21.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:21.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:21.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:21.86#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:42:21.86#ibcon#first serial, iclass 36, count 0 2006.239.07:42:21.86#ibcon#enter sib2, iclass 36, count 0 2006.239.07:42:21.86#ibcon#flushed, iclass 36, count 0 2006.239.07:42:21.86#ibcon#about to write, iclass 36, count 0 2006.239.07:42:21.86#ibcon#wrote, iclass 36, count 0 2006.239.07:42:21.86#ibcon#about to read 3, iclass 36, count 0 2006.239.07:42:21.88#ibcon#read 3, iclass 36, count 0 2006.239.07:42:21.88#ibcon#about to read 4, iclass 36, count 0 2006.239.07:42:21.88#ibcon#read 4, iclass 36, count 0 2006.239.07:42:21.88#ibcon#about to read 5, iclass 36, count 0 2006.239.07:42:21.88#ibcon#read 5, iclass 36, count 0 2006.239.07:42:21.88#ibcon#about to read 6, iclass 36, count 0 2006.239.07:42:21.88#ibcon#read 6, iclass 36, count 0 2006.239.07:42:21.88#ibcon#end of sib2, iclass 36, count 0 2006.239.07:42:21.88#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:42:21.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:42:21.88#ibcon#[27=USB\r\n] 2006.239.07:42:21.88#ibcon#*before write, iclass 36, count 0 2006.239.07:42:21.88#ibcon#enter sib2, iclass 36, count 0 2006.239.07:42:21.88#ibcon#flushed, iclass 36, count 0 2006.239.07:42:21.88#ibcon#about to write, iclass 36, count 0 2006.239.07:42:21.88#ibcon#wrote, iclass 36, count 0 2006.239.07:42:21.88#ibcon#about to read 3, iclass 36, count 0 2006.239.07:42:21.91#ibcon#read 3, iclass 36, count 0 2006.239.07:42:21.91#ibcon#about to read 4, iclass 36, count 0 2006.239.07:42:21.91#ibcon#read 4, iclass 36, count 0 2006.239.07:42:21.91#ibcon#about to read 5, iclass 36, count 0 2006.239.07:42:21.91#ibcon#read 5, iclass 36, count 0 2006.239.07:42:21.91#ibcon#about to read 6, iclass 36, count 0 2006.239.07:42:21.91#ibcon#read 6, iclass 36, count 0 2006.239.07:42:21.91#ibcon#end of sib2, iclass 36, count 0 2006.239.07:42:21.91#ibcon#*after write, iclass 36, count 0 2006.239.07:42:21.91#ibcon#*before return 0, iclass 36, count 0 2006.239.07:42:21.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:21.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:42:21.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:42:21.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:42:21.91$vc4f8/vblo=5,744.99 2006.239.07:42:21.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.07:42:21.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.07:42:21.91#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:21.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:21.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:21.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:21.91#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:42:21.91#ibcon#first serial, iclass 38, count 0 2006.239.07:42:21.91#ibcon#enter sib2, iclass 38, count 0 2006.239.07:42:21.91#ibcon#flushed, iclass 38, count 0 2006.239.07:42:21.91#ibcon#about to write, iclass 38, count 0 2006.239.07:42:21.91#ibcon#wrote, iclass 38, count 0 2006.239.07:42:21.91#ibcon#about to read 3, iclass 38, count 0 2006.239.07:42:21.93#ibcon#read 3, iclass 38, count 0 2006.239.07:42:21.93#ibcon#about to read 4, iclass 38, count 0 2006.239.07:42:21.93#ibcon#read 4, iclass 38, count 0 2006.239.07:42:21.93#ibcon#about to read 5, iclass 38, count 0 2006.239.07:42:21.93#ibcon#read 5, iclass 38, count 0 2006.239.07:42:21.93#ibcon#about to read 6, iclass 38, count 0 2006.239.07:42:21.93#ibcon#read 6, iclass 38, count 0 2006.239.07:42:21.93#ibcon#end of sib2, iclass 38, count 0 2006.239.07:42:21.93#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:42:21.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:42:21.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:42:21.93#ibcon#*before write, iclass 38, count 0 2006.239.07:42:21.93#ibcon#enter sib2, iclass 38, count 0 2006.239.07:42:21.93#ibcon#flushed, iclass 38, count 0 2006.239.07:42:21.93#ibcon#about to write, iclass 38, count 0 2006.239.07:42:21.93#ibcon#wrote, iclass 38, count 0 2006.239.07:42:21.93#ibcon#about to read 3, iclass 38, count 0 2006.239.07:42:21.97#ibcon#read 3, iclass 38, count 0 2006.239.07:42:21.97#ibcon#about to read 4, iclass 38, count 0 2006.239.07:42:21.97#ibcon#read 4, iclass 38, count 0 2006.239.07:42:21.97#ibcon#about to read 5, iclass 38, count 0 2006.239.07:42:21.97#ibcon#read 5, iclass 38, count 0 2006.239.07:42:21.97#ibcon#about to read 6, iclass 38, count 0 2006.239.07:42:21.97#ibcon#read 6, iclass 38, count 0 2006.239.07:42:21.97#ibcon#end of sib2, iclass 38, count 0 2006.239.07:42:21.97#ibcon#*after write, iclass 38, count 0 2006.239.07:42:21.97#ibcon#*before return 0, iclass 38, count 0 2006.239.07:42:21.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:21.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:42:21.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:42:21.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:42:21.97$vc4f8/vb=5,4 2006.239.07:42:21.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.07:42:21.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.07:42:21.97#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:21.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:22.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:22.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:22.03#ibcon#enter wrdev, iclass 40, count 2 2006.239.07:42:22.03#ibcon#first serial, iclass 40, count 2 2006.239.07:42:22.03#ibcon#enter sib2, iclass 40, count 2 2006.239.07:42:22.03#ibcon#flushed, iclass 40, count 2 2006.239.07:42:22.03#ibcon#about to write, iclass 40, count 2 2006.239.07:42:22.03#ibcon#wrote, iclass 40, count 2 2006.239.07:42:22.03#ibcon#about to read 3, iclass 40, count 2 2006.239.07:42:22.05#ibcon#read 3, iclass 40, count 2 2006.239.07:42:22.05#ibcon#about to read 4, iclass 40, count 2 2006.239.07:42:22.05#ibcon#read 4, iclass 40, count 2 2006.239.07:42:22.05#ibcon#about to read 5, iclass 40, count 2 2006.239.07:42:22.05#ibcon#read 5, iclass 40, count 2 2006.239.07:42:22.05#ibcon#about to read 6, iclass 40, count 2 2006.239.07:42:22.05#ibcon#read 6, iclass 40, count 2 2006.239.07:42:22.05#ibcon#end of sib2, iclass 40, count 2 2006.239.07:42:22.05#ibcon#*mode == 0, iclass 40, count 2 2006.239.07:42:22.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.07:42:22.05#ibcon#[27=AT05-04\r\n] 2006.239.07:42:22.05#ibcon#*before write, iclass 40, count 2 2006.239.07:42:22.05#ibcon#enter sib2, iclass 40, count 2 2006.239.07:42:22.05#ibcon#flushed, iclass 40, count 2 2006.239.07:42:22.05#ibcon#about to write, iclass 40, count 2 2006.239.07:42:22.05#ibcon#wrote, iclass 40, count 2 2006.239.07:42:22.05#ibcon#about to read 3, iclass 40, count 2 2006.239.07:42:22.08#ibcon#read 3, iclass 40, count 2 2006.239.07:42:22.08#ibcon#about to read 4, iclass 40, count 2 2006.239.07:42:22.08#ibcon#read 4, iclass 40, count 2 2006.239.07:42:22.08#ibcon#about to read 5, iclass 40, count 2 2006.239.07:42:22.08#ibcon#read 5, iclass 40, count 2 2006.239.07:42:22.08#ibcon#about to read 6, iclass 40, count 2 2006.239.07:42:22.08#ibcon#read 6, iclass 40, count 2 2006.239.07:42:22.08#ibcon#end of sib2, iclass 40, count 2 2006.239.07:42:22.08#ibcon#*after write, iclass 40, count 2 2006.239.07:42:22.08#ibcon#*before return 0, iclass 40, count 2 2006.239.07:42:22.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:22.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:42:22.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.07:42:22.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:22.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:22.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:22.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:22.20#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:42:22.20#ibcon#first serial, iclass 40, count 0 2006.239.07:42:22.20#ibcon#enter sib2, iclass 40, count 0 2006.239.07:42:22.20#ibcon#flushed, iclass 40, count 0 2006.239.07:42:22.20#ibcon#about to write, iclass 40, count 0 2006.239.07:42:22.20#ibcon#wrote, iclass 40, count 0 2006.239.07:42:22.20#ibcon#about to read 3, iclass 40, count 0 2006.239.07:42:22.22#ibcon#read 3, iclass 40, count 0 2006.239.07:42:22.22#ibcon#about to read 4, iclass 40, count 0 2006.239.07:42:22.22#ibcon#read 4, iclass 40, count 0 2006.239.07:42:22.22#ibcon#about to read 5, iclass 40, count 0 2006.239.07:42:22.22#ibcon#read 5, iclass 40, count 0 2006.239.07:42:22.22#ibcon#about to read 6, iclass 40, count 0 2006.239.07:42:22.22#ibcon#read 6, iclass 40, count 0 2006.239.07:42:22.22#ibcon#end of sib2, iclass 40, count 0 2006.239.07:42:22.22#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:42:22.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:42:22.22#ibcon#[27=USB\r\n] 2006.239.07:42:22.22#ibcon#*before write, iclass 40, count 0 2006.239.07:42:22.22#ibcon#enter sib2, iclass 40, count 0 2006.239.07:42:22.22#ibcon#flushed, iclass 40, count 0 2006.239.07:42:22.22#ibcon#about to write, iclass 40, count 0 2006.239.07:42:22.22#ibcon#wrote, iclass 40, count 0 2006.239.07:42:22.22#ibcon#about to read 3, iclass 40, count 0 2006.239.07:42:22.25#ibcon#read 3, iclass 40, count 0 2006.239.07:42:22.25#ibcon#about to read 4, iclass 40, count 0 2006.239.07:42:22.25#ibcon#read 4, iclass 40, count 0 2006.239.07:42:22.25#ibcon#about to read 5, iclass 40, count 0 2006.239.07:42:22.25#ibcon#read 5, iclass 40, count 0 2006.239.07:42:22.25#ibcon#about to read 6, iclass 40, count 0 2006.239.07:42:22.25#ibcon#read 6, iclass 40, count 0 2006.239.07:42:22.25#ibcon#end of sib2, iclass 40, count 0 2006.239.07:42:22.25#ibcon#*after write, iclass 40, count 0 2006.239.07:42:22.25#ibcon#*before return 0, iclass 40, count 0 2006.239.07:42:22.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:22.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:42:22.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:42:22.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:42:22.25$vc4f8/vblo=6,752.99 2006.239.07:42:22.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:42:22.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:42:22.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:42:22.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:22.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:22.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:22.25#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:42:22.25#ibcon#first serial, iclass 4, count 0 2006.239.07:42:22.25#ibcon#enter sib2, iclass 4, count 0 2006.239.07:42:22.25#ibcon#flushed, iclass 4, count 0 2006.239.07:42:22.25#ibcon#about to write, iclass 4, count 0 2006.239.07:42:22.25#ibcon#wrote, iclass 4, count 0 2006.239.07:42:22.25#ibcon#about to read 3, iclass 4, count 0 2006.239.07:42:22.27#ibcon#read 3, iclass 4, count 0 2006.239.07:42:22.27#ibcon#about to read 4, iclass 4, count 0 2006.239.07:42:22.27#ibcon#read 4, iclass 4, count 0 2006.239.07:42:22.27#ibcon#about to read 5, iclass 4, count 0 2006.239.07:42:22.27#ibcon#read 5, iclass 4, count 0 2006.239.07:42:22.27#ibcon#about to read 6, iclass 4, count 0 2006.239.07:42:22.27#ibcon#read 6, iclass 4, count 0 2006.239.07:42:22.27#ibcon#end of sib2, iclass 4, count 0 2006.239.07:42:22.27#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:42:22.27#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:42:22.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:42:22.27#ibcon#*before write, iclass 4, count 0 2006.239.07:42:22.27#ibcon#enter sib2, iclass 4, count 0 2006.239.07:42:22.27#ibcon#flushed, iclass 4, count 0 2006.239.07:42:22.27#ibcon#about to write, iclass 4, count 0 2006.239.07:42:22.27#ibcon#wrote, iclass 4, count 0 2006.239.07:42:22.27#ibcon#about to read 3, iclass 4, count 0 2006.239.07:42:22.31#ibcon#read 3, iclass 4, count 0 2006.239.07:42:22.31#ibcon#about to read 4, iclass 4, count 0 2006.239.07:42:22.31#ibcon#read 4, iclass 4, count 0 2006.239.07:42:22.31#ibcon#about to read 5, iclass 4, count 0 2006.239.07:42:22.31#ibcon#read 5, iclass 4, count 0 2006.239.07:42:22.31#ibcon#about to read 6, iclass 4, count 0 2006.239.07:42:22.31#ibcon#read 6, iclass 4, count 0 2006.239.07:42:22.31#ibcon#end of sib2, iclass 4, count 0 2006.239.07:42:22.31#ibcon#*after write, iclass 4, count 0 2006.239.07:42:22.31#ibcon#*before return 0, iclass 4, count 0 2006.239.07:42:22.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:22.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:42:22.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:42:22.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:42:22.31$vc4f8/vb=6,4 2006.239.07:42:22.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:42:22.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:42:22.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:42:22.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:22.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:22.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:22.37#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:42:22.37#ibcon#first serial, iclass 6, count 2 2006.239.07:42:22.37#ibcon#enter sib2, iclass 6, count 2 2006.239.07:42:22.37#ibcon#flushed, iclass 6, count 2 2006.239.07:42:22.37#ibcon#about to write, iclass 6, count 2 2006.239.07:42:22.37#ibcon#wrote, iclass 6, count 2 2006.239.07:42:22.37#ibcon#about to read 3, iclass 6, count 2 2006.239.07:42:22.39#ibcon#read 3, iclass 6, count 2 2006.239.07:42:22.39#ibcon#about to read 4, iclass 6, count 2 2006.239.07:42:22.39#ibcon#read 4, iclass 6, count 2 2006.239.07:42:22.39#ibcon#about to read 5, iclass 6, count 2 2006.239.07:42:22.39#ibcon#read 5, iclass 6, count 2 2006.239.07:42:22.39#ibcon#about to read 6, iclass 6, count 2 2006.239.07:42:22.39#ibcon#read 6, iclass 6, count 2 2006.239.07:42:22.39#ibcon#end of sib2, iclass 6, count 2 2006.239.07:42:22.39#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:42:22.39#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:42:22.39#ibcon#[27=AT06-04\r\n] 2006.239.07:42:22.39#ibcon#*before write, iclass 6, count 2 2006.239.07:42:22.39#ibcon#enter sib2, iclass 6, count 2 2006.239.07:42:22.39#ibcon#flushed, iclass 6, count 2 2006.239.07:42:22.39#ibcon#about to write, iclass 6, count 2 2006.239.07:42:22.39#ibcon#wrote, iclass 6, count 2 2006.239.07:42:22.39#ibcon#about to read 3, iclass 6, count 2 2006.239.07:42:22.43#ibcon#read 3, iclass 6, count 2 2006.239.07:42:22.43#ibcon#about to read 4, iclass 6, count 2 2006.239.07:42:22.43#ibcon#read 4, iclass 6, count 2 2006.239.07:42:22.43#ibcon#about to read 5, iclass 6, count 2 2006.239.07:42:22.43#ibcon#read 5, iclass 6, count 2 2006.239.07:42:22.43#ibcon#about to read 6, iclass 6, count 2 2006.239.07:42:22.43#ibcon#read 6, iclass 6, count 2 2006.239.07:42:22.43#ibcon#end of sib2, iclass 6, count 2 2006.239.07:42:22.43#ibcon#*after write, iclass 6, count 2 2006.239.07:42:22.43#ibcon#*before return 0, iclass 6, count 2 2006.239.07:42:22.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:22.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:42:22.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:42:22.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:42:22.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:22.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:22.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:22.54#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:42:22.54#ibcon#first serial, iclass 6, count 0 2006.239.07:42:22.54#ibcon#enter sib2, iclass 6, count 0 2006.239.07:42:22.54#ibcon#flushed, iclass 6, count 0 2006.239.07:42:22.54#ibcon#about to write, iclass 6, count 0 2006.239.07:42:22.54#ibcon#wrote, iclass 6, count 0 2006.239.07:42:22.54#ibcon#about to read 3, iclass 6, count 0 2006.239.07:42:22.56#ibcon#read 3, iclass 6, count 0 2006.239.07:42:22.56#ibcon#about to read 4, iclass 6, count 0 2006.239.07:42:22.56#ibcon#read 4, iclass 6, count 0 2006.239.07:42:22.56#ibcon#about to read 5, iclass 6, count 0 2006.239.07:42:22.56#ibcon#read 5, iclass 6, count 0 2006.239.07:42:22.56#ibcon#about to read 6, iclass 6, count 0 2006.239.07:42:22.56#ibcon#read 6, iclass 6, count 0 2006.239.07:42:22.56#ibcon#end of sib2, iclass 6, count 0 2006.239.07:42:22.56#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:42:22.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:42:22.56#ibcon#[27=USB\r\n] 2006.239.07:42:22.56#ibcon#*before write, iclass 6, count 0 2006.239.07:42:22.56#ibcon#enter sib2, iclass 6, count 0 2006.239.07:42:22.56#ibcon#flushed, iclass 6, count 0 2006.239.07:42:22.56#ibcon#about to write, iclass 6, count 0 2006.239.07:42:22.56#ibcon#wrote, iclass 6, count 0 2006.239.07:42:22.56#ibcon#about to read 3, iclass 6, count 0 2006.239.07:42:22.59#ibcon#read 3, iclass 6, count 0 2006.239.07:42:22.59#ibcon#about to read 4, iclass 6, count 0 2006.239.07:42:22.59#ibcon#read 4, iclass 6, count 0 2006.239.07:42:22.59#ibcon#about to read 5, iclass 6, count 0 2006.239.07:42:22.59#ibcon#read 5, iclass 6, count 0 2006.239.07:42:22.59#ibcon#about to read 6, iclass 6, count 0 2006.239.07:42:22.59#ibcon#read 6, iclass 6, count 0 2006.239.07:42:22.59#ibcon#end of sib2, iclass 6, count 0 2006.239.07:42:22.59#ibcon#*after write, iclass 6, count 0 2006.239.07:42:22.59#ibcon#*before return 0, iclass 6, count 0 2006.239.07:42:22.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:22.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:42:22.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:42:22.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:42:22.59$vc4f8/vabw=wide 2006.239.07:42:22.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:42:22.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:42:22.59#ibcon#ireg 8 cls_cnt 0 2006.239.07:42:22.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:22.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:22.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:22.59#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:42:22.59#ibcon#first serial, iclass 10, count 0 2006.239.07:42:22.59#ibcon#enter sib2, iclass 10, count 0 2006.239.07:42:22.59#ibcon#flushed, iclass 10, count 0 2006.239.07:42:22.59#ibcon#about to write, iclass 10, count 0 2006.239.07:42:22.59#ibcon#wrote, iclass 10, count 0 2006.239.07:42:22.59#ibcon#about to read 3, iclass 10, count 0 2006.239.07:42:22.61#ibcon#read 3, iclass 10, count 0 2006.239.07:42:22.61#ibcon#about to read 4, iclass 10, count 0 2006.239.07:42:22.61#ibcon#read 4, iclass 10, count 0 2006.239.07:42:22.61#ibcon#about to read 5, iclass 10, count 0 2006.239.07:42:22.61#ibcon#read 5, iclass 10, count 0 2006.239.07:42:22.61#ibcon#about to read 6, iclass 10, count 0 2006.239.07:42:22.61#ibcon#read 6, iclass 10, count 0 2006.239.07:42:22.61#ibcon#end of sib2, iclass 10, count 0 2006.239.07:42:22.61#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:42:22.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:42:22.61#ibcon#[25=BW32\r\n] 2006.239.07:42:22.61#ibcon#*before write, iclass 10, count 0 2006.239.07:42:22.61#ibcon#enter sib2, iclass 10, count 0 2006.239.07:42:22.61#ibcon#flushed, iclass 10, count 0 2006.239.07:42:22.61#ibcon#about to write, iclass 10, count 0 2006.239.07:42:22.61#ibcon#wrote, iclass 10, count 0 2006.239.07:42:22.61#ibcon#about to read 3, iclass 10, count 0 2006.239.07:42:22.64#ibcon#read 3, iclass 10, count 0 2006.239.07:42:22.64#ibcon#about to read 4, iclass 10, count 0 2006.239.07:42:22.64#ibcon#read 4, iclass 10, count 0 2006.239.07:42:22.64#ibcon#about to read 5, iclass 10, count 0 2006.239.07:42:22.64#ibcon#read 5, iclass 10, count 0 2006.239.07:42:22.64#ibcon#about to read 6, iclass 10, count 0 2006.239.07:42:22.64#ibcon#read 6, iclass 10, count 0 2006.239.07:42:22.64#ibcon#end of sib2, iclass 10, count 0 2006.239.07:42:22.64#ibcon#*after write, iclass 10, count 0 2006.239.07:42:22.64#ibcon#*before return 0, iclass 10, count 0 2006.239.07:42:22.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:22.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:42:22.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:42:22.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:42:22.64$vc4f8/vbbw=wide 2006.239.07:42:22.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:42:22.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:42:22.64#ibcon#ireg 8 cls_cnt 0 2006.239.07:42:22.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:42:22.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:42:22.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:42:22.71#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:42:22.71#ibcon#first serial, iclass 12, count 0 2006.239.07:42:22.71#ibcon#enter sib2, iclass 12, count 0 2006.239.07:42:22.71#ibcon#flushed, iclass 12, count 0 2006.239.07:42:22.71#ibcon#about to write, iclass 12, count 0 2006.239.07:42:22.71#ibcon#wrote, iclass 12, count 0 2006.239.07:42:22.71#ibcon#about to read 3, iclass 12, count 0 2006.239.07:42:22.73#ibcon#read 3, iclass 12, count 0 2006.239.07:42:22.73#ibcon#about to read 4, iclass 12, count 0 2006.239.07:42:22.73#ibcon#read 4, iclass 12, count 0 2006.239.07:42:22.73#ibcon#about to read 5, iclass 12, count 0 2006.239.07:42:22.73#ibcon#read 5, iclass 12, count 0 2006.239.07:42:22.73#ibcon#about to read 6, iclass 12, count 0 2006.239.07:42:22.73#ibcon#read 6, iclass 12, count 0 2006.239.07:42:22.73#ibcon#end of sib2, iclass 12, count 0 2006.239.07:42:22.73#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:42:22.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:42:22.73#ibcon#[27=BW32\r\n] 2006.239.07:42:22.73#ibcon#*before write, iclass 12, count 0 2006.239.07:42:22.73#ibcon#enter sib2, iclass 12, count 0 2006.239.07:42:22.73#ibcon#flushed, iclass 12, count 0 2006.239.07:42:22.73#ibcon#about to write, iclass 12, count 0 2006.239.07:42:22.73#ibcon#wrote, iclass 12, count 0 2006.239.07:42:22.73#ibcon#about to read 3, iclass 12, count 0 2006.239.07:42:22.76#ibcon#read 3, iclass 12, count 0 2006.239.07:42:22.76#ibcon#about to read 4, iclass 12, count 0 2006.239.07:42:22.76#ibcon#read 4, iclass 12, count 0 2006.239.07:42:22.76#ibcon#about to read 5, iclass 12, count 0 2006.239.07:42:22.76#ibcon#read 5, iclass 12, count 0 2006.239.07:42:22.76#ibcon#about to read 6, iclass 12, count 0 2006.239.07:42:22.76#ibcon#read 6, iclass 12, count 0 2006.239.07:42:22.76#ibcon#end of sib2, iclass 12, count 0 2006.239.07:42:22.76#ibcon#*after write, iclass 12, count 0 2006.239.07:42:22.76#ibcon#*before return 0, iclass 12, count 0 2006.239.07:42:22.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:42:22.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:42:22.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:42:22.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:42:22.76$4f8m12a/ifd4f 2006.239.07:42:22.76$ifd4f/lo= 2006.239.07:42:22.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:42:22.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:42:22.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:42:22.76$ifd4f/patch= 2006.239.07:42:22.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:42:22.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:42:22.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:42:22.76$4f8m12a/"form=m,16.000,1:2 2006.239.07:42:22.76$4f8m12a/"tpicd 2006.239.07:42:22.76$4f8m12a/echo=off 2006.239.07:42:22.76$4f8m12a/xlog=off 2006.239.07:42:22.76:!2006.239.07:42:50 2006.239.07:42:34.14#trakl#Source acquired 2006.239.07:42:35.14#flagr#flagr/antenna,acquired 2006.239.07:42:50.00:preob 2006.239.07:42:51.14/onsource/TRACKING 2006.239.07:42:51.14:!2006.239.07:43:00 2006.239.07:43:00.00:data_valid=on 2006.239.07:43:00.00:midob 2006.239.07:43:00.14/onsource/TRACKING 2006.239.07:43:00.14/wx/25.34,1011.5,80 2006.239.07:43:00.22/cable/+6.4148E-03 2006.239.07:43:01.31/va/01,08,usb,yes,37,39 2006.239.07:43:01.31/va/02,07,usb,yes,37,39 2006.239.07:43:01.31/va/03,07,usb,yes,35,35 2006.239.07:43:01.31/va/04,07,usb,yes,39,42 2006.239.07:43:01.31/va/05,08,usb,yes,36,38 2006.239.07:43:01.31/va/06,07,usb,yes,39,39 2006.239.07:43:01.31/va/07,07,usb,yes,39,38 2006.239.07:43:01.31/va/08,07,usb,yes,42,41 2006.239.07:43:01.54/valo/01,532.99,yes,locked 2006.239.07:43:01.54/valo/02,572.99,yes,locked 2006.239.07:43:01.54/valo/03,672.99,yes,locked 2006.239.07:43:01.54/valo/04,832.99,yes,locked 2006.239.07:43:01.54/valo/05,652.99,yes,locked 2006.239.07:43:01.54/valo/06,772.99,yes,locked 2006.239.07:43:01.54/valo/07,832.99,yes,locked 2006.239.07:43:01.54/valo/08,852.99,yes,locked 2006.239.07:43:02.63/vb/01,04,usb,yes,34,54 2006.239.07:43:02.63/vb/02,04,usb,yes,36,54 2006.239.07:43:02.63/vb/03,04,usb,yes,32,38 2006.239.07:43:02.63/vb/04,04,usb,yes,34,33 2006.239.07:43:02.63/vb/05,04,usb,yes,32,36 2006.239.07:43:02.63/vb/06,04,usb,yes,33,36 2006.239.07:43:02.63/vb/07,04,usb,yes,35,36 2006.239.07:43:02.63/vb/08,04,usb,yes,32,36 2006.239.07:43:02.87/vblo/01,632.99,yes,locked 2006.239.07:43:02.87/vblo/02,640.99,yes,locked 2006.239.07:43:02.87/vblo/03,656.99,yes,locked 2006.239.07:43:02.87/vblo/04,712.99,yes,locked 2006.239.07:43:02.87/vblo/05,744.99,yes,locked 2006.239.07:43:02.87/vblo/06,752.99,yes,locked 2006.239.07:43:02.87/vblo/07,734.99,yes,locked 2006.239.07:43:02.87/vblo/08,744.99,yes,locked 2006.239.07:43:03.02/vabw/8 2006.239.07:43:03.17/vbbw/8 2006.239.07:43:03.26/xfe/off,on,13.0 2006.239.07:43:03.63/ifatt/23,28,28,28 2006.239.07:43:04.07/fmout-gps/S +4.37E-07 2006.239.07:43:04.11:!2006.239.07:44:00 2006.239.07:44:00.01:data_valid=off 2006.239.07:44:00.02:postob 2006.239.07:44:00.21/cable/+6.4127E-03 2006.239.07:44:00.22/wx/25.32,1011.5,80 2006.239.07:44:00.30/fmout-gps/S +4.38E-07 2006.239.07:44:00.30:scan_name=239-0744,k06239,60 2006.239.07:44:00.31:source=3c371,180650.68,694928.1,2000.0,cw 2006.239.07:44:01.14#flagr#flagr/antenna,new-source 2006.239.07:44:01.15:checkk5 2006.239.07:44:01.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:44:01.91/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:44:02.55/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:44:02.94/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:44:03.30/chk_obsdata//k5ts1/T2390743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:44:03.67/chk_obsdata//k5ts2/T2390743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:44:04.04/chk_obsdata//k5ts3/T2390743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:44:04.42/chk_obsdata//k5ts4/T2390743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:44:05.12/k5log//k5ts1_log_newline 2006.239.07:44:05.81/k5log//k5ts2_log_newline 2006.239.07:44:06.51/k5log//k5ts3_log_newline 2006.239.07:44:07.21/k5log//k5ts4_log_newline 2006.239.07:44:07.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:44:07.23:4f8m12a=1 2006.239.07:44:07.23$4f8m12a/echo=on 2006.239.07:44:07.23$4f8m12a/pcalon 2006.239.07:44:07.23$pcalon/"no phase cal control is implemented here 2006.239.07:44:07.23$4f8m12a/"tpicd=stop 2006.239.07:44:07.23$4f8m12a/vc4f8 2006.239.07:44:07.23$vc4f8/valo=1,532.99 2006.239.07:44:07.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.07:44:07.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.07:44:07.24#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:07.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:44:07.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:44:07.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:44:07.24#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:44:07.24#ibcon#first serial, iclass 22, count 0 2006.239.07:44:07.24#ibcon#enter sib2, iclass 22, count 0 2006.239.07:44:07.24#ibcon#flushed, iclass 22, count 0 2006.239.07:44:07.24#ibcon#about to write, iclass 22, count 0 2006.239.07:44:07.24#ibcon#wrote, iclass 22, count 0 2006.239.07:44:07.24#ibcon#about to read 3, iclass 22, count 0 2006.239.07:44:07.28#ibcon#read 3, iclass 22, count 0 2006.239.07:44:07.28#ibcon#about to read 4, iclass 22, count 0 2006.239.07:44:07.28#ibcon#read 4, iclass 22, count 0 2006.239.07:44:07.28#ibcon#about to read 5, iclass 22, count 0 2006.239.07:44:07.28#ibcon#read 5, iclass 22, count 0 2006.239.07:44:07.28#ibcon#about to read 6, iclass 22, count 0 2006.239.07:44:07.28#ibcon#read 6, iclass 22, count 0 2006.239.07:44:07.28#ibcon#end of sib2, iclass 22, count 0 2006.239.07:44:07.28#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:44:07.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:44:07.28#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:44:07.28#ibcon#*before write, iclass 22, count 0 2006.239.07:44:07.28#ibcon#enter sib2, iclass 22, count 0 2006.239.07:44:07.28#ibcon#flushed, iclass 22, count 0 2006.239.07:44:07.28#ibcon#about to write, iclass 22, count 0 2006.239.07:44:07.28#ibcon#wrote, iclass 22, count 0 2006.239.07:44:07.28#ibcon#about to read 3, iclass 22, count 0 2006.239.07:44:07.28#abcon#{5=INTERFACE CLEAR} 2006.239.07:44:07.32#ibcon#read 3, iclass 22, count 0 2006.239.07:44:07.32#ibcon#about to read 4, iclass 22, count 0 2006.239.07:44:07.32#ibcon#read 4, iclass 22, count 0 2006.239.07:44:07.32#ibcon#about to read 5, iclass 22, count 0 2006.239.07:44:07.32#ibcon#read 5, iclass 22, count 0 2006.239.07:44:07.32#ibcon#about to read 6, iclass 22, count 0 2006.239.07:44:07.32#ibcon#read 6, iclass 22, count 0 2006.239.07:44:07.32#ibcon#end of sib2, iclass 22, count 0 2006.239.07:44:07.32#ibcon#*after write, iclass 22, count 0 2006.239.07:44:07.32#ibcon#*before return 0, iclass 22, count 0 2006.239.07:44:07.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:44:07.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:44:07.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:44:07.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:44:07.32$vc4f8/va=1,8 2006.239.07:44:07.32#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.07:44:07.32#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.07:44:07.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:07.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:07.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:07.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:07.32#ibcon#enter wrdev, iclass 25, count 2 2006.239.07:44:07.32#ibcon#first serial, iclass 25, count 2 2006.239.07:44:07.32#ibcon#enter sib2, iclass 25, count 2 2006.239.07:44:07.32#ibcon#flushed, iclass 25, count 2 2006.239.07:44:07.32#ibcon#about to write, iclass 25, count 2 2006.239.07:44:07.32#ibcon#wrote, iclass 25, count 2 2006.239.07:44:07.32#ibcon#about to read 3, iclass 25, count 2 2006.239.07:44:07.33#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:44:07.34#ibcon#read 3, iclass 25, count 2 2006.239.07:44:07.34#ibcon#about to read 4, iclass 25, count 2 2006.239.07:44:07.34#ibcon#read 4, iclass 25, count 2 2006.239.07:44:07.34#ibcon#about to read 5, iclass 25, count 2 2006.239.07:44:07.34#ibcon#read 5, iclass 25, count 2 2006.239.07:44:07.34#ibcon#about to read 6, iclass 25, count 2 2006.239.07:44:07.34#ibcon#read 6, iclass 25, count 2 2006.239.07:44:07.34#ibcon#end of sib2, iclass 25, count 2 2006.239.07:44:07.34#ibcon#*mode == 0, iclass 25, count 2 2006.239.07:44:07.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.07:44:07.34#ibcon#[25=AT01-08\r\n] 2006.239.07:44:07.34#ibcon#*before write, iclass 25, count 2 2006.239.07:44:07.34#ibcon#enter sib2, iclass 25, count 2 2006.239.07:44:07.34#ibcon#flushed, iclass 25, count 2 2006.239.07:44:07.34#ibcon#about to write, iclass 25, count 2 2006.239.07:44:07.34#ibcon#wrote, iclass 25, count 2 2006.239.07:44:07.34#ibcon#about to read 3, iclass 25, count 2 2006.239.07:44:07.38#ibcon#read 3, iclass 25, count 2 2006.239.07:44:07.38#ibcon#about to read 4, iclass 25, count 2 2006.239.07:44:07.38#ibcon#read 4, iclass 25, count 2 2006.239.07:44:07.38#ibcon#about to read 5, iclass 25, count 2 2006.239.07:44:07.38#ibcon#read 5, iclass 25, count 2 2006.239.07:44:07.38#ibcon#about to read 6, iclass 25, count 2 2006.239.07:44:07.38#ibcon#read 6, iclass 25, count 2 2006.239.07:44:07.38#ibcon#end of sib2, iclass 25, count 2 2006.239.07:44:07.38#ibcon#*after write, iclass 25, count 2 2006.239.07:44:07.38#ibcon#*before return 0, iclass 25, count 2 2006.239.07:44:07.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:07.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:07.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.07:44:07.38#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:07.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:07.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:07.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:07.50#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:44:07.50#ibcon#first serial, iclass 25, count 0 2006.239.07:44:07.50#ibcon#enter sib2, iclass 25, count 0 2006.239.07:44:07.50#ibcon#flushed, iclass 25, count 0 2006.239.07:44:07.50#ibcon#about to write, iclass 25, count 0 2006.239.07:44:07.50#ibcon#wrote, iclass 25, count 0 2006.239.07:44:07.50#ibcon#about to read 3, iclass 25, count 0 2006.239.07:44:07.51#ibcon#read 3, iclass 25, count 0 2006.239.07:44:07.51#ibcon#about to read 4, iclass 25, count 0 2006.239.07:44:07.51#ibcon#read 4, iclass 25, count 0 2006.239.07:44:07.51#ibcon#about to read 5, iclass 25, count 0 2006.239.07:44:07.51#ibcon#read 5, iclass 25, count 0 2006.239.07:44:07.51#ibcon#about to read 6, iclass 25, count 0 2006.239.07:44:07.51#ibcon#read 6, iclass 25, count 0 2006.239.07:44:07.51#ibcon#end of sib2, iclass 25, count 0 2006.239.07:44:07.51#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:44:07.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:44:07.51#ibcon#[25=USB\r\n] 2006.239.07:44:07.51#ibcon#*before write, iclass 25, count 0 2006.239.07:44:07.51#ibcon#enter sib2, iclass 25, count 0 2006.239.07:44:07.51#ibcon#flushed, iclass 25, count 0 2006.239.07:44:07.51#ibcon#about to write, iclass 25, count 0 2006.239.07:44:07.51#ibcon#wrote, iclass 25, count 0 2006.239.07:44:07.51#ibcon#about to read 3, iclass 25, count 0 2006.239.07:44:07.54#ibcon#read 3, iclass 25, count 0 2006.239.07:44:07.54#ibcon#about to read 4, iclass 25, count 0 2006.239.07:44:07.54#ibcon#read 4, iclass 25, count 0 2006.239.07:44:07.54#ibcon#about to read 5, iclass 25, count 0 2006.239.07:44:07.54#ibcon#read 5, iclass 25, count 0 2006.239.07:44:07.54#ibcon#about to read 6, iclass 25, count 0 2006.239.07:44:07.54#ibcon#read 6, iclass 25, count 0 2006.239.07:44:07.54#ibcon#end of sib2, iclass 25, count 0 2006.239.07:44:07.54#ibcon#*after write, iclass 25, count 0 2006.239.07:44:07.54#ibcon#*before return 0, iclass 25, count 0 2006.239.07:44:07.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:07.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:07.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:44:07.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:44:07.54$vc4f8/valo=2,572.99 2006.239.07:44:07.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.07:44:07.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.07:44:07.54#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:07.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:07.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:07.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:07.54#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:44:07.54#ibcon#first serial, iclass 27, count 0 2006.239.07:44:07.54#ibcon#enter sib2, iclass 27, count 0 2006.239.07:44:07.54#ibcon#flushed, iclass 27, count 0 2006.239.07:44:07.54#ibcon#about to write, iclass 27, count 0 2006.239.07:44:07.54#ibcon#wrote, iclass 27, count 0 2006.239.07:44:07.54#ibcon#about to read 3, iclass 27, count 0 2006.239.07:44:07.56#ibcon#read 3, iclass 27, count 0 2006.239.07:44:07.56#ibcon#about to read 4, iclass 27, count 0 2006.239.07:44:07.56#ibcon#read 4, iclass 27, count 0 2006.239.07:44:07.56#ibcon#about to read 5, iclass 27, count 0 2006.239.07:44:07.56#ibcon#read 5, iclass 27, count 0 2006.239.07:44:07.56#ibcon#about to read 6, iclass 27, count 0 2006.239.07:44:07.56#ibcon#read 6, iclass 27, count 0 2006.239.07:44:07.56#ibcon#end of sib2, iclass 27, count 0 2006.239.07:44:07.56#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:44:07.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:44:07.56#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:44:07.56#ibcon#*before write, iclass 27, count 0 2006.239.07:44:07.56#ibcon#enter sib2, iclass 27, count 0 2006.239.07:44:07.56#ibcon#flushed, iclass 27, count 0 2006.239.07:44:07.56#ibcon#about to write, iclass 27, count 0 2006.239.07:44:07.56#ibcon#wrote, iclass 27, count 0 2006.239.07:44:07.56#ibcon#about to read 3, iclass 27, count 0 2006.239.07:44:07.60#ibcon#read 3, iclass 27, count 0 2006.239.07:44:07.60#ibcon#about to read 4, iclass 27, count 0 2006.239.07:44:07.60#ibcon#read 4, iclass 27, count 0 2006.239.07:44:07.60#ibcon#about to read 5, iclass 27, count 0 2006.239.07:44:07.60#ibcon#read 5, iclass 27, count 0 2006.239.07:44:07.60#ibcon#about to read 6, iclass 27, count 0 2006.239.07:44:07.60#ibcon#read 6, iclass 27, count 0 2006.239.07:44:07.60#ibcon#end of sib2, iclass 27, count 0 2006.239.07:44:07.60#ibcon#*after write, iclass 27, count 0 2006.239.07:44:07.60#ibcon#*before return 0, iclass 27, count 0 2006.239.07:44:07.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:07.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:07.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:44:07.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:44:07.60$vc4f8/va=2,7 2006.239.07:44:07.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.07:44:07.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.07:44:07.60#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:07.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:07.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:07.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:07.66#ibcon#enter wrdev, iclass 29, count 2 2006.239.07:44:07.66#ibcon#first serial, iclass 29, count 2 2006.239.07:44:07.66#ibcon#enter sib2, iclass 29, count 2 2006.239.07:44:07.66#ibcon#flushed, iclass 29, count 2 2006.239.07:44:07.66#ibcon#about to write, iclass 29, count 2 2006.239.07:44:07.66#ibcon#wrote, iclass 29, count 2 2006.239.07:44:07.66#ibcon#about to read 3, iclass 29, count 2 2006.239.07:44:07.68#ibcon#read 3, iclass 29, count 2 2006.239.07:44:07.68#ibcon#about to read 4, iclass 29, count 2 2006.239.07:44:07.68#ibcon#read 4, iclass 29, count 2 2006.239.07:44:07.68#ibcon#about to read 5, iclass 29, count 2 2006.239.07:44:07.68#ibcon#read 5, iclass 29, count 2 2006.239.07:44:07.68#ibcon#about to read 6, iclass 29, count 2 2006.239.07:44:07.68#ibcon#read 6, iclass 29, count 2 2006.239.07:44:07.68#ibcon#end of sib2, iclass 29, count 2 2006.239.07:44:07.68#ibcon#*mode == 0, iclass 29, count 2 2006.239.07:44:07.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.07:44:07.68#ibcon#[25=AT02-07\r\n] 2006.239.07:44:07.68#ibcon#*before write, iclass 29, count 2 2006.239.07:44:07.68#ibcon#enter sib2, iclass 29, count 2 2006.239.07:44:07.68#ibcon#flushed, iclass 29, count 2 2006.239.07:44:07.68#ibcon#about to write, iclass 29, count 2 2006.239.07:44:07.68#ibcon#wrote, iclass 29, count 2 2006.239.07:44:07.68#ibcon#about to read 3, iclass 29, count 2 2006.239.07:44:07.71#ibcon#read 3, iclass 29, count 2 2006.239.07:44:07.71#ibcon#about to read 4, iclass 29, count 2 2006.239.07:44:07.71#ibcon#read 4, iclass 29, count 2 2006.239.07:44:07.71#ibcon#about to read 5, iclass 29, count 2 2006.239.07:44:07.71#ibcon#read 5, iclass 29, count 2 2006.239.07:44:07.71#ibcon#about to read 6, iclass 29, count 2 2006.239.07:44:07.71#ibcon#read 6, iclass 29, count 2 2006.239.07:44:07.71#ibcon#end of sib2, iclass 29, count 2 2006.239.07:44:07.71#ibcon#*after write, iclass 29, count 2 2006.239.07:44:07.71#ibcon#*before return 0, iclass 29, count 2 2006.239.07:44:07.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:07.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:07.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.07:44:07.71#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:07.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:07.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:07.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:07.83#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:44:07.83#ibcon#first serial, iclass 29, count 0 2006.239.07:44:07.83#ibcon#enter sib2, iclass 29, count 0 2006.239.07:44:07.83#ibcon#flushed, iclass 29, count 0 2006.239.07:44:07.83#ibcon#about to write, iclass 29, count 0 2006.239.07:44:07.83#ibcon#wrote, iclass 29, count 0 2006.239.07:44:07.83#ibcon#about to read 3, iclass 29, count 0 2006.239.07:44:07.85#ibcon#read 3, iclass 29, count 0 2006.239.07:44:07.85#ibcon#about to read 4, iclass 29, count 0 2006.239.07:44:07.85#ibcon#read 4, iclass 29, count 0 2006.239.07:44:07.85#ibcon#about to read 5, iclass 29, count 0 2006.239.07:44:07.85#ibcon#read 5, iclass 29, count 0 2006.239.07:44:07.85#ibcon#about to read 6, iclass 29, count 0 2006.239.07:44:07.85#ibcon#read 6, iclass 29, count 0 2006.239.07:44:07.85#ibcon#end of sib2, iclass 29, count 0 2006.239.07:44:07.85#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:44:07.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:44:07.85#ibcon#[25=USB\r\n] 2006.239.07:44:07.85#ibcon#*before write, iclass 29, count 0 2006.239.07:44:07.85#ibcon#enter sib2, iclass 29, count 0 2006.239.07:44:07.85#ibcon#flushed, iclass 29, count 0 2006.239.07:44:07.85#ibcon#about to write, iclass 29, count 0 2006.239.07:44:07.85#ibcon#wrote, iclass 29, count 0 2006.239.07:44:07.85#ibcon#about to read 3, iclass 29, count 0 2006.239.07:44:07.88#ibcon#read 3, iclass 29, count 0 2006.239.07:44:07.88#ibcon#about to read 4, iclass 29, count 0 2006.239.07:44:07.88#ibcon#read 4, iclass 29, count 0 2006.239.07:44:07.88#ibcon#about to read 5, iclass 29, count 0 2006.239.07:44:07.88#ibcon#read 5, iclass 29, count 0 2006.239.07:44:07.88#ibcon#about to read 6, iclass 29, count 0 2006.239.07:44:07.88#ibcon#read 6, iclass 29, count 0 2006.239.07:44:07.88#ibcon#end of sib2, iclass 29, count 0 2006.239.07:44:07.88#ibcon#*after write, iclass 29, count 0 2006.239.07:44:07.88#ibcon#*before return 0, iclass 29, count 0 2006.239.07:44:07.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:07.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:07.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:44:07.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:44:07.88$vc4f8/valo=3,672.99 2006.239.07:44:07.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.07:44:07.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.07:44:07.88#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:07.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:07.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:07.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:07.88#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:44:07.88#ibcon#first serial, iclass 31, count 0 2006.239.07:44:07.88#ibcon#enter sib2, iclass 31, count 0 2006.239.07:44:07.88#ibcon#flushed, iclass 31, count 0 2006.239.07:44:07.88#ibcon#about to write, iclass 31, count 0 2006.239.07:44:07.88#ibcon#wrote, iclass 31, count 0 2006.239.07:44:07.88#ibcon#about to read 3, iclass 31, count 0 2006.239.07:44:07.90#ibcon#read 3, iclass 31, count 0 2006.239.07:44:07.90#ibcon#about to read 4, iclass 31, count 0 2006.239.07:44:07.90#ibcon#read 4, iclass 31, count 0 2006.239.07:44:07.90#ibcon#about to read 5, iclass 31, count 0 2006.239.07:44:07.90#ibcon#read 5, iclass 31, count 0 2006.239.07:44:07.90#ibcon#about to read 6, iclass 31, count 0 2006.239.07:44:07.90#ibcon#read 6, iclass 31, count 0 2006.239.07:44:07.90#ibcon#end of sib2, iclass 31, count 0 2006.239.07:44:07.90#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:44:07.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:44:07.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:44:07.90#ibcon#*before write, iclass 31, count 0 2006.239.07:44:07.90#ibcon#enter sib2, iclass 31, count 0 2006.239.07:44:07.90#ibcon#flushed, iclass 31, count 0 2006.239.07:44:07.90#ibcon#about to write, iclass 31, count 0 2006.239.07:44:07.90#ibcon#wrote, iclass 31, count 0 2006.239.07:44:07.90#ibcon#about to read 3, iclass 31, count 0 2006.239.07:44:07.94#ibcon#read 3, iclass 31, count 0 2006.239.07:44:07.94#ibcon#about to read 4, iclass 31, count 0 2006.239.07:44:07.94#ibcon#read 4, iclass 31, count 0 2006.239.07:44:07.94#ibcon#about to read 5, iclass 31, count 0 2006.239.07:44:07.94#ibcon#read 5, iclass 31, count 0 2006.239.07:44:07.94#ibcon#about to read 6, iclass 31, count 0 2006.239.07:44:07.94#ibcon#read 6, iclass 31, count 0 2006.239.07:44:07.94#ibcon#end of sib2, iclass 31, count 0 2006.239.07:44:07.94#ibcon#*after write, iclass 31, count 0 2006.239.07:44:07.94#ibcon#*before return 0, iclass 31, count 0 2006.239.07:44:07.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:07.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:07.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:44:07.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:44:07.94$vc4f8/va=3,7 2006.239.07:44:07.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.07:44:07.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.07:44:07.94#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:07.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:08.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:08.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:08.00#ibcon#enter wrdev, iclass 33, count 2 2006.239.07:44:08.00#ibcon#first serial, iclass 33, count 2 2006.239.07:44:08.00#ibcon#enter sib2, iclass 33, count 2 2006.239.07:44:08.00#ibcon#flushed, iclass 33, count 2 2006.239.07:44:08.00#ibcon#about to write, iclass 33, count 2 2006.239.07:44:08.00#ibcon#wrote, iclass 33, count 2 2006.239.07:44:08.00#ibcon#about to read 3, iclass 33, count 2 2006.239.07:44:08.02#ibcon#read 3, iclass 33, count 2 2006.239.07:44:08.02#ibcon#about to read 4, iclass 33, count 2 2006.239.07:44:08.02#ibcon#read 4, iclass 33, count 2 2006.239.07:44:08.02#ibcon#about to read 5, iclass 33, count 2 2006.239.07:44:08.02#ibcon#read 5, iclass 33, count 2 2006.239.07:44:08.02#ibcon#about to read 6, iclass 33, count 2 2006.239.07:44:08.02#ibcon#read 6, iclass 33, count 2 2006.239.07:44:08.02#ibcon#end of sib2, iclass 33, count 2 2006.239.07:44:08.02#ibcon#*mode == 0, iclass 33, count 2 2006.239.07:44:08.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.07:44:08.02#ibcon#[25=AT03-07\r\n] 2006.239.07:44:08.02#ibcon#*before write, iclass 33, count 2 2006.239.07:44:08.02#ibcon#enter sib2, iclass 33, count 2 2006.239.07:44:08.02#ibcon#flushed, iclass 33, count 2 2006.239.07:44:08.02#ibcon#about to write, iclass 33, count 2 2006.239.07:44:08.02#ibcon#wrote, iclass 33, count 2 2006.239.07:44:08.02#ibcon#about to read 3, iclass 33, count 2 2006.239.07:44:08.07#ibcon#read 3, iclass 33, count 2 2006.239.07:44:08.07#ibcon#about to read 4, iclass 33, count 2 2006.239.07:44:08.07#ibcon#read 4, iclass 33, count 2 2006.239.07:44:08.07#ibcon#about to read 5, iclass 33, count 2 2006.239.07:44:08.07#ibcon#read 5, iclass 33, count 2 2006.239.07:44:08.07#ibcon#about to read 6, iclass 33, count 2 2006.239.07:44:08.07#ibcon#read 6, iclass 33, count 2 2006.239.07:44:08.07#ibcon#end of sib2, iclass 33, count 2 2006.239.07:44:08.07#ibcon#*after write, iclass 33, count 2 2006.239.07:44:08.07#ibcon#*before return 0, iclass 33, count 2 2006.239.07:44:08.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:08.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:08.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.07:44:08.07#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:08.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:08.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:08.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:08.18#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:44:08.18#ibcon#first serial, iclass 33, count 0 2006.239.07:44:08.18#ibcon#enter sib2, iclass 33, count 0 2006.239.07:44:08.18#ibcon#flushed, iclass 33, count 0 2006.239.07:44:08.18#ibcon#about to write, iclass 33, count 0 2006.239.07:44:08.18#ibcon#wrote, iclass 33, count 0 2006.239.07:44:08.18#ibcon#about to read 3, iclass 33, count 0 2006.239.07:44:08.20#ibcon#read 3, iclass 33, count 0 2006.239.07:44:08.20#ibcon#about to read 4, iclass 33, count 0 2006.239.07:44:08.20#ibcon#read 4, iclass 33, count 0 2006.239.07:44:08.20#ibcon#about to read 5, iclass 33, count 0 2006.239.07:44:08.20#ibcon#read 5, iclass 33, count 0 2006.239.07:44:08.20#ibcon#about to read 6, iclass 33, count 0 2006.239.07:44:08.20#ibcon#read 6, iclass 33, count 0 2006.239.07:44:08.20#ibcon#end of sib2, iclass 33, count 0 2006.239.07:44:08.20#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:44:08.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:44:08.20#ibcon#[25=USB\r\n] 2006.239.07:44:08.20#ibcon#*before write, iclass 33, count 0 2006.239.07:44:08.20#ibcon#enter sib2, iclass 33, count 0 2006.239.07:44:08.20#ibcon#flushed, iclass 33, count 0 2006.239.07:44:08.20#ibcon#about to write, iclass 33, count 0 2006.239.07:44:08.20#ibcon#wrote, iclass 33, count 0 2006.239.07:44:08.20#ibcon#about to read 3, iclass 33, count 0 2006.239.07:44:08.23#ibcon#read 3, iclass 33, count 0 2006.239.07:44:08.23#ibcon#about to read 4, iclass 33, count 0 2006.239.07:44:08.23#ibcon#read 4, iclass 33, count 0 2006.239.07:44:08.23#ibcon#about to read 5, iclass 33, count 0 2006.239.07:44:08.23#ibcon#read 5, iclass 33, count 0 2006.239.07:44:08.23#ibcon#about to read 6, iclass 33, count 0 2006.239.07:44:08.23#ibcon#read 6, iclass 33, count 0 2006.239.07:44:08.23#ibcon#end of sib2, iclass 33, count 0 2006.239.07:44:08.23#ibcon#*after write, iclass 33, count 0 2006.239.07:44:08.23#ibcon#*before return 0, iclass 33, count 0 2006.239.07:44:08.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:08.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:08.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:44:08.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:44:08.23$vc4f8/valo=4,832.99 2006.239.07:44:08.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.07:44:08.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.07:44:08.23#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:08.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:08.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:08.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:08.23#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:44:08.23#ibcon#first serial, iclass 35, count 0 2006.239.07:44:08.23#ibcon#enter sib2, iclass 35, count 0 2006.239.07:44:08.23#ibcon#flushed, iclass 35, count 0 2006.239.07:44:08.23#ibcon#about to write, iclass 35, count 0 2006.239.07:44:08.23#ibcon#wrote, iclass 35, count 0 2006.239.07:44:08.23#ibcon#about to read 3, iclass 35, count 0 2006.239.07:44:08.25#ibcon#read 3, iclass 35, count 0 2006.239.07:44:08.25#ibcon#about to read 4, iclass 35, count 0 2006.239.07:44:08.25#ibcon#read 4, iclass 35, count 0 2006.239.07:44:08.25#ibcon#about to read 5, iclass 35, count 0 2006.239.07:44:08.25#ibcon#read 5, iclass 35, count 0 2006.239.07:44:08.25#ibcon#about to read 6, iclass 35, count 0 2006.239.07:44:08.25#ibcon#read 6, iclass 35, count 0 2006.239.07:44:08.25#ibcon#end of sib2, iclass 35, count 0 2006.239.07:44:08.25#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:44:08.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:44:08.25#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:44:08.25#ibcon#*before write, iclass 35, count 0 2006.239.07:44:08.25#ibcon#enter sib2, iclass 35, count 0 2006.239.07:44:08.25#ibcon#flushed, iclass 35, count 0 2006.239.07:44:08.25#ibcon#about to write, iclass 35, count 0 2006.239.07:44:08.25#ibcon#wrote, iclass 35, count 0 2006.239.07:44:08.25#ibcon#about to read 3, iclass 35, count 0 2006.239.07:44:08.29#ibcon#read 3, iclass 35, count 0 2006.239.07:44:08.29#ibcon#about to read 4, iclass 35, count 0 2006.239.07:44:08.29#ibcon#read 4, iclass 35, count 0 2006.239.07:44:08.29#ibcon#about to read 5, iclass 35, count 0 2006.239.07:44:08.29#ibcon#read 5, iclass 35, count 0 2006.239.07:44:08.29#ibcon#about to read 6, iclass 35, count 0 2006.239.07:44:08.29#ibcon#read 6, iclass 35, count 0 2006.239.07:44:08.29#ibcon#end of sib2, iclass 35, count 0 2006.239.07:44:08.29#ibcon#*after write, iclass 35, count 0 2006.239.07:44:08.29#ibcon#*before return 0, iclass 35, count 0 2006.239.07:44:08.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:08.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:08.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:44:08.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:44:08.29$vc4f8/va=4,7 2006.239.07:44:08.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.07:44:08.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.07:44:08.29#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:08.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:08.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:08.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:08.35#ibcon#enter wrdev, iclass 37, count 2 2006.239.07:44:08.35#ibcon#first serial, iclass 37, count 2 2006.239.07:44:08.35#ibcon#enter sib2, iclass 37, count 2 2006.239.07:44:08.35#ibcon#flushed, iclass 37, count 2 2006.239.07:44:08.35#ibcon#about to write, iclass 37, count 2 2006.239.07:44:08.35#ibcon#wrote, iclass 37, count 2 2006.239.07:44:08.35#ibcon#about to read 3, iclass 37, count 2 2006.239.07:44:08.37#ibcon#read 3, iclass 37, count 2 2006.239.07:44:08.37#ibcon#about to read 4, iclass 37, count 2 2006.239.07:44:08.37#ibcon#read 4, iclass 37, count 2 2006.239.07:44:08.37#ibcon#about to read 5, iclass 37, count 2 2006.239.07:44:08.37#ibcon#read 5, iclass 37, count 2 2006.239.07:44:08.37#ibcon#about to read 6, iclass 37, count 2 2006.239.07:44:08.37#ibcon#read 6, iclass 37, count 2 2006.239.07:44:08.37#ibcon#end of sib2, iclass 37, count 2 2006.239.07:44:08.37#ibcon#*mode == 0, iclass 37, count 2 2006.239.07:44:08.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.07:44:08.37#ibcon#[25=AT04-07\r\n] 2006.239.07:44:08.37#ibcon#*before write, iclass 37, count 2 2006.239.07:44:08.37#ibcon#enter sib2, iclass 37, count 2 2006.239.07:44:08.37#ibcon#flushed, iclass 37, count 2 2006.239.07:44:08.37#ibcon#about to write, iclass 37, count 2 2006.239.07:44:08.37#ibcon#wrote, iclass 37, count 2 2006.239.07:44:08.37#ibcon#about to read 3, iclass 37, count 2 2006.239.07:44:08.40#ibcon#read 3, iclass 37, count 2 2006.239.07:44:08.40#ibcon#about to read 4, iclass 37, count 2 2006.239.07:44:08.40#ibcon#read 4, iclass 37, count 2 2006.239.07:44:08.40#ibcon#about to read 5, iclass 37, count 2 2006.239.07:44:08.40#ibcon#read 5, iclass 37, count 2 2006.239.07:44:08.40#ibcon#about to read 6, iclass 37, count 2 2006.239.07:44:08.40#ibcon#read 6, iclass 37, count 2 2006.239.07:44:08.40#ibcon#end of sib2, iclass 37, count 2 2006.239.07:44:08.40#ibcon#*after write, iclass 37, count 2 2006.239.07:44:08.40#ibcon#*before return 0, iclass 37, count 2 2006.239.07:44:08.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:08.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:08.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.07:44:08.40#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:08.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:08.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:08.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:08.52#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:44:08.52#ibcon#first serial, iclass 37, count 0 2006.239.07:44:08.52#ibcon#enter sib2, iclass 37, count 0 2006.239.07:44:08.52#ibcon#flushed, iclass 37, count 0 2006.239.07:44:08.52#ibcon#about to write, iclass 37, count 0 2006.239.07:44:08.52#ibcon#wrote, iclass 37, count 0 2006.239.07:44:08.52#ibcon#about to read 3, iclass 37, count 0 2006.239.07:44:08.54#ibcon#read 3, iclass 37, count 0 2006.239.07:44:08.54#ibcon#about to read 4, iclass 37, count 0 2006.239.07:44:08.54#ibcon#read 4, iclass 37, count 0 2006.239.07:44:08.54#ibcon#about to read 5, iclass 37, count 0 2006.239.07:44:08.54#ibcon#read 5, iclass 37, count 0 2006.239.07:44:08.54#ibcon#about to read 6, iclass 37, count 0 2006.239.07:44:08.54#ibcon#read 6, iclass 37, count 0 2006.239.07:44:08.54#ibcon#end of sib2, iclass 37, count 0 2006.239.07:44:08.54#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:44:08.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:44:08.54#ibcon#[25=USB\r\n] 2006.239.07:44:08.54#ibcon#*before write, iclass 37, count 0 2006.239.07:44:08.54#ibcon#enter sib2, iclass 37, count 0 2006.239.07:44:08.54#ibcon#flushed, iclass 37, count 0 2006.239.07:44:08.54#ibcon#about to write, iclass 37, count 0 2006.239.07:44:08.54#ibcon#wrote, iclass 37, count 0 2006.239.07:44:08.54#ibcon#about to read 3, iclass 37, count 0 2006.239.07:44:08.57#ibcon#read 3, iclass 37, count 0 2006.239.07:44:08.57#ibcon#about to read 4, iclass 37, count 0 2006.239.07:44:08.57#ibcon#read 4, iclass 37, count 0 2006.239.07:44:08.57#ibcon#about to read 5, iclass 37, count 0 2006.239.07:44:08.57#ibcon#read 5, iclass 37, count 0 2006.239.07:44:08.57#ibcon#about to read 6, iclass 37, count 0 2006.239.07:44:08.57#ibcon#read 6, iclass 37, count 0 2006.239.07:44:08.57#ibcon#end of sib2, iclass 37, count 0 2006.239.07:44:08.57#ibcon#*after write, iclass 37, count 0 2006.239.07:44:08.57#ibcon#*before return 0, iclass 37, count 0 2006.239.07:44:08.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:08.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:08.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:44:08.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:44:08.57$vc4f8/valo=5,652.99 2006.239.07:44:08.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.07:44:08.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.07:44:08.57#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:08.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:08.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:08.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:08.57#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:44:08.57#ibcon#first serial, iclass 39, count 0 2006.239.07:44:08.57#ibcon#enter sib2, iclass 39, count 0 2006.239.07:44:08.57#ibcon#flushed, iclass 39, count 0 2006.239.07:44:08.57#ibcon#about to write, iclass 39, count 0 2006.239.07:44:08.57#ibcon#wrote, iclass 39, count 0 2006.239.07:44:08.57#ibcon#about to read 3, iclass 39, count 0 2006.239.07:44:08.59#ibcon#read 3, iclass 39, count 0 2006.239.07:44:08.59#ibcon#about to read 4, iclass 39, count 0 2006.239.07:44:08.59#ibcon#read 4, iclass 39, count 0 2006.239.07:44:08.59#ibcon#about to read 5, iclass 39, count 0 2006.239.07:44:08.59#ibcon#read 5, iclass 39, count 0 2006.239.07:44:08.59#ibcon#about to read 6, iclass 39, count 0 2006.239.07:44:08.59#ibcon#read 6, iclass 39, count 0 2006.239.07:44:08.59#ibcon#end of sib2, iclass 39, count 0 2006.239.07:44:08.59#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:44:08.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:44:08.59#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:44:08.59#ibcon#*before write, iclass 39, count 0 2006.239.07:44:08.59#ibcon#enter sib2, iclass 39, count 0 2006.239.07:44:08.59#ibcon#flushed, iclass 39, count 0 2006.239.07:44:08.59#ibcon#about to write, iclass 39, count 0 2006.239.07:44:08.59#ibcon#wrote, iclass 39, count 0 2006.239.07:44:08.59#ibcon#about to read 3, iclass 39, count 0 2006.239.07:44:08.63#ibcon#read 3, iclass 39, count 0 2006.239.07:44:08.63#ibcon#about to read 4, iclass 39, count 0 2006.239.07:44:08.63#ibcon#read 4, iclass 39, count 0 2006.239.07:44:08.63#ibcon#about to read 5, iclass 39, count 0 2006.239.07:44:08.63#ibcon#read 5, iclass 39, count 0 2006.239.07:44:08.63#ibcon#about to read 6, iclass 39, count 0 2006.239.07:44:08.63#ibcon#read 6, iclass 39, count 0 2006.239.07:44:08.63#ibcon#end of sib2, iclass 39, count 0 2006.239.07:44:08.63#ibcon#*after write, iclass 39, count 0 2006.239.07:44:08.63#ibcon#*before return 0, iclass 39, count 0 2006.239.07:44:08.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:08.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:08.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:44:08.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:44:08.63$vc4f8/va=5,8 2006.239.07:44:08.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.07:44:08.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.07:44:08.63#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:08.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:08.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:08.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:08.69#ibcon#enter wrdev, iclass 3, count 2 2006.239.07:44:08.69#ibcon#first serial, iclass 3, count 2 2006.239.07:44:08.69#ibcon#enter sib2, iclass 3, count 2 2006.239.07:44:08.69#ibcon#flushed, iclass 3, count 2 2006.239.07:44:08.69#ibcon#about to write, iclass 3, count 2 2006.239.07:44:08.69#ibcon#wrote, iclass 3, count 2 2006.239.07:44:08.69#ibcon#about to read 3, iclass 3, count 2 2006.239.07:44:08.71#ibcon#read 3, iclass 3, count 2 2006.239.07:44:08.71#ibcon#about to read 4, iclass 3, count 2 2006.239.07:44:08.71#ibcon#read 4, iclass 3, count 2 2006.239.07:44:08.71#ibcon#about to read 5, iclass 3, count 2 2006.239.07:44:08.71#ibcon#read 5, iclass 3, count 2 2006.239.07:44:08.71#ibcon#about to read 6, iclass 3, count 2 2006.239.07:44:08.71#ibcon#read 6, iclass 3, count 2 2006.239.07:44:08.71#ibcon#end of sib2, iclass 3, count 2 2006.239.07:44:08.71#ibcon#*mode == 0, iclass 3, count 2 2006.239.07:44:08.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.07:44:08.71#ibcon#[25=AT05-08\r\n] 2006.239.07:44:08.71#ibcon#*before write, iclass 3, count 2 2006.239.07:44:08.71#ibcon#enter sib2, iclass 3, count 2 2006.239.07:44:08.71#ibcon#flushed, iclass 3, count 2 2006.239.07:44:08.71#ibcon#about to write, iclass 3, count 2 2006.239.07:44:08.71#ibcon#wrote, iclass 3, count 2 2006.239.07:44:08.71#ibcon#about to read 3, iclass 3, count 2 2006.239.07:44:08.74#ibcon#read 3, iclass 3, count 2 2006.239.07:44:08.74#ibcon#about to read 4, iclass 3, count 2 2006.239.07:44:08.74#ibcon#read 4, iclass 3, count 2 2006.239.07:44:08.74#ibcon#about to read 5, iclass 3, count 2 2006.239.07:44:08.74#ibcon#read 5, iclass 3, count 2 2006.239.07:44:08.74#ibcon#about to read 6, iclass 3, count 2 2006.239.07:44:08.74#ibcon#read 6, iclass 3, count 2 2006.239.07:44:08.74#ibcon#end of sib2, iclass 3, count 2 2006.239.07:44:08.74#ibcon#*after write, iclass 3, count 2 2006.239.07:44:08.74#ibcon#*before return 0, iclass 3, count 2 2006.239.07:44:08.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:08.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:08.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.07:44:08.74#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:08.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:08.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:08.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:08.86#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:44:08.86#ibcon#first serial, iclass 3, count 0 2006.239.07:44:08.86#ibcon#enter sib2, iclass 3, count 0 2006.239.07:44:08.86#ibcon#flushed, iclass 3, count 0 2006.239.07:44:08.86#ibcon#about to write, iclass 3, count 0 2006.239.07:44:08.86#ibcon#wrote, iclass 3, count 0 2006.239.07:44:08.86#ibcon#about to read 3, iclass 3, count 0 2006.239.07:44:08.88#ibcon#read 3, iclass 3, count 0 2006.239.07:44:08.88#ibcon#about to read 4, iclass 3, count 0 2006.239.07:44:08.88#ibcon#read 4, iclass 3, count 0 2006.239.07:44:08.88#ibcon#about to read 5, iclass 3, count 0 2006.239.07:44:08.88#ibcon#read 5, iclass 3, count 0 2006.239.07:44:08.88#ibcon#about to read 6, iclass 3, count 0 2006.239.07:44:08.88#ibcon#read 6, iclass 3, count 0 2006.239.07:44:08.88#ibcon#end of sib2, iclass 3, count 0 2006.239.07:44:08.88#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:44:08.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:44:08.88#ibcon#[25=USB\r\n] 2006.239.07:44:08.88#ibcon#*before write, iclass 3, count 0 2006.239.07:44:08.88#ibcon#enter sib2, iclass 3, count 0 2006.239.07:44:08.88#ibcon#flushed, iclass 3, count 0 2006.239.07:44:08.88#ibcon#about to write, iclass 3, count 0 2006.239.07:44:08.88#ibcon#wrote, iclass 3, count 0 2006.239.07:44:08.88#ibcon#about to read 3, iclass 3, count 0 2006.239.07:44:08.91#ibcon#read 3, iclass 3, count 0 2006.239.07:44:08.91#ibcon#about to read 4, iclass 3, count 0 2006.239.07:44:08.91#ibcon#read 4, iclass 3, count 0 2006.239.07:44:08.91#ibcon#about to read 5, iclass 3, count 0 2006.239.07:44:08.91#ibcon#read 5, iclass 3, count 0 2006.239.07:44:08.91#ibcon#about to read 6, iclass 3, count 0 2006.239.07:44:08.91#ibcon#read 6, iclass 3, count 0 2006.239.07:44:08.91#ibcon#end of sib2, iclass 3, count 0 2006.239.07:44:08.91#ibcon#*after write, iclass 3, count 0 2006.239.07:44:08.91#ibcon#*before return 0, iclass 3, count 0 2006.239.07:44:08.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:08.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:08.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:44:08.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:44:08.91$vc4f8/valo=6,772.99 2006.239.07:44:08.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:44:08.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:44:08.91#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:08.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:08.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:08.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:08.91#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:44:08.91#ibcon#first serial, iclass 5, count 0 2006.239.07:44:08.91#ibcon#enter sib2, iclass 5, count 0 2006.239.07:44:08.91#ibcon#flushed, iclass 5, count 0 2006.239.07:44:08.91#ibcon#about to write, iclass 5, count 0 2006.239.07:44:08.91#ibcon#wrote, iclass 5, count 0 2006.239.07:44:08.91#ibcon#about to read 3, iclass 5, count 0 2006.239.07:44:08.93#ibcon#read 3, iclass 5, count 0 2006.239.07:44:08.93#ibcon#about to read 4, iclass 5, count 0 2006.239.07:44:08.93#ibcon#read 4, iclass 5, count 0 2006.239.07:44:08.93#ibcon#about to read 5, iclass 5, count 0 2006.239.07:44:08.93#ibcon#read 5, iclass 5, count 0 2006.239.07:44:08.93#ibcon#about to read 6, iclass 5, count 0 2006.239.07:44:08.93#ibcon#read 6, iclass 5, count 0 2006.239.07:44:08.93#ibcon#end of sib2, iclass 5, count 0 2006.239.07:44:08.93#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:44:08.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:44:08.93#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:44:08.93#ibcon#*before write, iclass 5, count 0 2006.239.07:44:08.93#ibcon#enter sib2, iclass 5, count 0 2006.239.07:44:08.93#ibcon#flushed, iclass 5, count 0 2006.239.07:44:08.93#ibcon#about to write, iclass 5, count 0 2006.239.07:44:08.93#ibcon#wrote, iclass 5, count 0 2006.239.07:44:08.93#ibcon#about to read 3, iclass 5, count 0 2006.239.07:44:08.97#ibcon#read 3, iclass 5, count 0 2006.239.07:44:08.97#ibcon#about to read 4, iclass 5, count 0 2006.239.07:44:08.97#ibcon#read 4, iclass 5, count 0 2006.239.07:44:08.97#ibcon#about to read 5, iclass 5, count 0 2006.239.07:44:08.97#ibcon#read 5, iclass 5, count 0 2006.239.07:44:08.97#ibcon#about to read 6, iclass 5, count 0 2006.239.07:44:08.97#ibcon#read 6, iclass 5, count 0 2006.239.07:44:08.97#ibcon#end of sib2, iclass 5, count 0 2006.239.07:44:08.97#ibcon#*after write, iclass 5, count 0 2006.239.07:44:08.97#ibcon#*before return 0, iclass 5, count 0 2006.239.07:44:08.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:08.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:08.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:44:08.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:44:08.97$vc4f8/va=6,7 2006.239.07:44:08.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.07:44:08.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.07:44:08.97#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:08.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:44:09.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:44:09.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:44:09.03#ibcon#enter wrdev, iclass 7, count 2 2006.239.07:44:09.03#ibcon#first serial, iclass 7, count 2 2006.239.07:44:09.03#ibcon#enter sib2, iclass 7, count 2 2006.239.07:44:09.03#ibcon#flushed, iclass 7, count 2 2006.239.07:44:09.03#ibcon#about to write, iclass 7, count 2 2006.239.07:44:09.03#ibcon#wrote, iclass 7, count 2 2006.239.07:44:09.03#ibcon#about to read 3, iclass 7, count 2 2006.239.07:44:09.05#ibcon#read 3, iclass 7, count 2 2006.239.07:44:09.05#ibcon#about to read 4, iclass 7, count 2 2006.239.07:44:09.05#ibcon#read 4, iclass 7, count 2 2006.239.07:44:09.05#ibcon#about to read 5, iclass 7, count 2 2006.239.07:44:09.05#ibcon#read 5, iclass 7, count 2 2006.239.07:44:09.05#ibcon#about to read 6, iclass 7, count 2 2006.239.07:44:09.05#ibcon#read 6, iclass 7, count 2 2006.239.07:44:09.05#ibcon#end of sib2, iclass 7, count 2 2006.239.07:44:09.05#ibcon#*mode == 0, iclass 7, count 2 2006.239.07:44:09.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.07:44:09.05#ibcon#[25=AT06-07\r\n] 2006.239.07:44:09.05#ibcon#*before write, iclass 7, count 2 2006.239.07:44:09.05#ibcon#enter sib2, iclass 7, count 2 2006.239.07:44:09.05#ibcon#flushed, iclass 7, count 2 2006.239.07:44:09.05#ibcon#about to write, iclass 7, count 2 2006.239.07:44:09.05#ibcon#wrote, iclass 7, count 2 2006.239.07:44:09.05#ibcon#about to read 3, iclass 7, count 2 2006.239.07:44:09.08#ibcon#read 3, iclass 7, count 2 2006.239.07:44:09.08#ibcon#about to read 4, iclass 7, count 2 2006.239.07:44:09.08#ibcon#read 4, iclass 7, count 2 2006.239.07:44:09.08#ibcon#about to read 5, iclass 7, count 2 2006.239.07:44:09.08#ibcon#read 5, iclass 7, count 2 2006.239.07:44:09.08#ibcon#about to read 6, iclass 7, count 2 2006.239.07:44:09.08#ibcon#read 6, iclass 7, count 2 2006.239.07:44:09.08#ibcon#end of sib2, iclass 7, count 2 2006.239.07:44:09.08#ibcon#*after write, iclass 7, count 2 2006.239.07:44:09.08#ibcon#*before return 0, iclass 7, count 2 2006.239.07:44:09.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:44:09.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:44:09.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.07:44:09.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:09.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:44:09.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:44:09.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:44:09.20#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:44:09.20#ibcon#first serial, iclass 7, count 0 2006.239.07:44:09.20#ibcon#enter sib2, iclass 7, count 0 2006.239.07:44:09.20#ibcon#flushed, iclass 7, count 0 2006.239.07:44:09.20#ibcon#about to write, iclass 7, count 0 2006.239.07:44:09.20#ibcon#wrote, iclass 7, count 0 2006.239.07:44:09.20#ibcon#about to read 3, iclass 7, count 0 2006.239.07:44:09.22#ibcon#read 3, iclass 7, count 0 2006.239.07:44:09.22#ibcon#about to read 4, iclass 7, count 0 2006.239.07:44:09.22#ibcon#read 4, iclass 7, count 0 2006.239.07:44:09.22#ibcon#about to read 5, iclass 7, count 0 2006.239.07:44:09.22#ibcon#read 5, iclass 7, count 0 2006.239.07:44:09.22#ibcon#about to read 6, iclass 7, count 0 2006.239.07:44:09.22#ibcon#read 6, iclass 7, count 0 2006.239.07:44:09.22#ibcon#end of sib2, iclass 7, count 0 2006.239.07:44:09.22#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:44:09.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:44:09.22#ibcon#[25=USB\r\n] 2006.239.07:44:09.22#ibcon#*before write, iclass 7, count 0 2006.239.07:44:09.22#ibcon#enter sib2, iclass 7, count 0 2006.239.07:44:09.22#ibcon#flushed, iclass 7, count 0 2006.239.07:44:09.22#ibcon#about to write, iclass 7, count 0 2006.239.07:44:09.22#ibcon#wrote, iclass 7, count 0 2006.239.07:44:09.22#ibcon#about to read 3, iclass 7, count 0 2006.239.07:44:09.25#ibcon#read 3, iclass 7, count 0 2006.239.07:44:09.25#ibcon#about to read 4, iclass 7, count 0 2006.239.07:44:09.25#ibcon#read 4, iclass 7, count 0 2006.239.07:44:09.25#ibcon#about to read 5, iclass 7, count 0 2006.239.07:44:09.25#ibcon#read 5, iclass 7, count 0 2006.239.07:44:09.25#ibcon#about to read 6, iclass 7, count 0 2006.239.07:44:09.25#ibcon#read 6, iclass 7, count 0 2006.239.07:44:09.25#ibcon#end of sib2, iclass 7, count 0 2006.239.07:44:09.25#ibcon#*after write, iclass 7, count 0 2006.239.07:44:09.25#ibcon#*before return 0, iclass 7, count 0 2006.239.07:44:09.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:44:09.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:44:09.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:44:09.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:44:09.25$vc4f8/valo=7,832.99 2006.239.07:44:09.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.07:44:09.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.07:44:09.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:09.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:44:09.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:44:09.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:44:09.25#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:44:09.25#ibcon#first serial, iclass 11, count 0 2006.239.07:44:09.25#ibcon#enter sib2, iclass 11, count 0 2006.239.07:44:09.25#ibcon#flushed, iclass 11, count 0 2006.239.07:44:09.25#ibcon#about to write, iclass 11, count 0 2006.239.07:44:09.25#ibcon#wrote, iclass 11, count 0 2006.239.07:44:09.25#ibcon#about to read 3, iclass 11, count 0 2006.239.07:44:09.27#ibcon#read 3, iclass 11, count 0 2006.239.07:44:09.27#ibcon#about to read 4, iclass 11, count 0 2006.239.07:44:09.27#ibcon#read 4, iclass 11, count 0 2006.239.07:44:09.27#ibcon#about to read 5, iclass 11, count 0 2006.239.07:44:09.27#ibcon#read 5, iclass 11, count 0 2006.239.07:44:09.27#ibcon#about to read 6, iclass 11, count 0 2006.239.07:44:09.27#ibcon#read 6, iclass 11, count 0 2006.239.07:44:09.27#ibcon#end of sib2, iclass 11, count 0 2006.239.07:44:09.27#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:44:09.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:44:09.27#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:44:09.27#ibcon#*before write, iclass 11, count 0 2006.239.07:44:09.27#ibcon#enter sib2, iclass 11, count 0 2006.239.07:44:09.27#ibcon#flushed, iclass 11, count 0 2006.239.07:44:09.27#ibcon#about to write, iclass 11, count 0 2006.239.07:44:09.27#ibcon#wrote, iclass 11, count 0 2006.239.07:44:09.27#ibcon#about to read 3, iclass 11, count 0 2006.239.07:44:09.31#ibcon#read 3, iclass 11, count 0 2006.239.07:44:09.31#ibcon#about to read 4, iclass 11, count 0 2006.239.07:44:09.31#ibcon#read 4, iclass 11, count 0 2006.239.07:44:09.31#ibcon#about to read 5, iclass 11, count 0 2006.239.07:44:09.31#ibcon#read 5, iclass 11, count 0 2006.239.07:44:09.31#ibcon#about to read 6, iclass 11, count 0 2006.239.07:44:09.31#ibcon#read 6, iclass 11, count 0 2006.239.07:44:09.31#ibcon#end of sib2, iclass 11, count 0 2006.239.07:44:09.31#ibcon#*after write, iclass 11, count 0 2006.239.07:44:09.31#ibcon#*before return 0, iclass 11, count 0 2006.239.07:44:09.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:44:09.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:44:09.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:44:09.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:44:09.31$vc4f8/va=7,7 2006.239.07:44:09.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.07:44:09.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.07:44:09.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:09.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:44:09.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:44:09.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:44:09.37#ibcon#enter wrdev, iclass 13, count 2 2006.239.07:44:09.37#ibcon#first serial, iclass 13, count 2 2006.239.07:44:09.37#ibcon#enter sib2, iclass 13, count 2 2006.239.07:44:09.37#ibcon#flushed, iclass 13, count 2 2006.239.07:44:09.37#ibcon#about to write, iclass 13, count 2 2006.239.07:44:09.37#ibcon#wrote, iclass 13, count 2 2006.239.07:44:09.37#ibcon#about to read 3, iclass 13, count 2 2006.239.07:44:09.39#ibcon#read 3, iclass 13, count 2 2006.239.07:44:09.39#ibcon#about to read 4, iclass 13, count 2 2006.239.07:44:09.39#ibcon#read 4, iclass 13, count 2 2006.239.07:44:09.39#ibcon#about to read 5, iclass 13, count 2 2006.239.07:44:09.39#ibcon#read 5, iclass 13, count 2 2006.239.07:44:09.39#ibcon#about to read 6, iclass 13, count 2 2006.239.07:44:09.39#ibcon#read 6, iclass 13, count 2 2006.239.07:44:09.39#ibcon#end of sib2, iclass 13, count 2 2006.239.07:44:09.39#ibcon#*mode == 0, iclass 13, count 2 2006.239.07:44:09.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.07:44:09.39#ibcon#[25=AT07-07\r\n] 2006.239.07:44:09.39#ibcon#*before write, iclass 13, count 2 2006.239.07:44:09.39#ibcon#enter sib2, iclass 13, count 2 2006.239.07:44:09.39#ibcon#flushed, iclass 13, count 2 2006.239.07:44:09.39#ibcon#about to write, iclass 13, count 2 2006.239.07:44:09.39#ibcon#wrote, iclass 13, count 2 2006.239.07:44:09.39#ibcon#about to read 3, iclass 13, count 2 2006.239.07:44:09.42#ibcon#read 3, iclass 13, count 2 2006.239.07:44:09.42#ibcon#about to read 4, iclass 13, count 2 2006.239.07:44:09.42#ibcon#read 4, iclass 13, count 2 2006.239.07:44:09.42#ibcon#about to read 5, iclass 13, count 2 2006.239.07:44:09.42#ibcon#read 5, iclass 13, count 2 2006.239.07:44:09.42#ibcon#about to read 6, iclass 13, count 2 2006.239.07:44:09.42#ibcon#read 6, iclass 13, count 2 2006.239.07:44:09.42#ibcon#end of sib2, iclass 13, count 2 2006.239.07:44:09.42#ibcon#*after write, iclass 13, count 2 2006.239.07:44:09.42#ibcon#*before return 0, iclass 13, count 2 2006.239.07:44:09.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:44:09.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:44:09.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.07:44:09.42#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:09.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:44:09.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:44:09.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:44:09.54#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:44:09.54#ibcon#first serial, iclass 13, count 0 2006.239.07:44:09.54#ibcon#enter sib2, iclass 13, count 0 2006.239.07:44:09.54#ibcon#flushed, iclass 13, count 0 2006.239.07:44:09.54#ibcon#about to write, iclass 13, count 0 2006.239.07:44:09.54#ibcon#wrote, iclass 13, count 0 2006.239.07:44:09.54#ibcon#about to read 3, iclass 13, count 0 2006.239.07:44:09.56#ibcon#read 3, iclass 13, count 0 2006.239.07:44:09.56#ibcon#about to read 4, iclass 13, count 0 2006.239.07:44:09.56#ibcon#read 4, iclass 13, count 0 2006.239.07:44:09.56#ibcon#about to read 5, iclass 13, count 0 2006.239.07:44:09.56#ibcon#read 5, iclass 13, count 0 2006.239.07:44:09.56#ibcon#about to read 6, iclass 13, count 0 2006.239.07:44:09.56#ibcon#read 6, iclass 13, count 0 2006.239.07:44:09.56#ibcon#end of sib2, iclass 13, count 0 2006.239.07:44:09.56#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:44:09.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:44:09.56#ibcon#[25=USB\r\n] 2006.239.07:44:09.56#ibcon#*before write, iclass 13, count 0 2006.239.07:44:09.56#ibcon#enter sib2, iclass 13, count 0 2006.239.07:44:09.56#ibcon#flushed, iclass 13, count 0 2006.239.07:44:09.56#ibcon#about to write, iclass 13, count 0 2006.239.07:44:09.56#ibcon#wrote, iclass 13, count 0 2006.239.07:44:09.56#ibcon#about to read 3, iclass 13, count 0 2006.239.07:44:09.62#ibcon#read 3, iclass 13, count 0 2006.239.07:44:09.62#ibcon#about to read 4, iclass 13, count 0 2006.239.07:44:09.62#ibcon#read 4, iclass 13, count 0 2006.239.07:44:09.62#ibcon#about to read 5, iclass 13, count 0 2006.239.07:44:09.62#ibcon#read 5, iclass 13, count 0 2006.239.07:44:09.62#ibcon#about to read 6, iclass 13, count 0 2006.239.07:44:09.62#ibcon#read 6, iclass 13, count 0 2006.239.07:44:09.62#ibcon#end of sib2, iclass 13, count 0 2006.239.07:44:09.62#ibcon#*after write, iclass 13, count 0 2006.239.07:44:09.62#ibcon#*before return 0, iclass 13, count 0 2006.239.07:44:09.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:44:09.62#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:44:09.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:44:09.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:44:09.62$vc4f8/valo=8,852.99 2006.239.07:44:09.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.07:44:09.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.07:44:09.62#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:09.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:44:09.62#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:44:09.62#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:44:09.62#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:44:09.62#ibcon#first serial, iclass 15, count 0 2006.239.07:44:09.62#ibcon#enter sib2, iclass 15, count 0 2006.239.07:44:09.62#ibcon#flushed, iclass 15, count 0 2006.239.07:44:09.62#ibcon#about to write, iclass 15, count 0 2006.239.07:44:09.62#ibcon#wrote, iclass 15, count 0 2006.239.07:44:09.62#ibcon#about to read 3, iclass 15, count 0 2006.239.07:44:09.63#ibcon#read 3, iclass 15, count 0 2006.239.07:44:09.63#ibcon#about to read 4, iclass 15, count 0 2006.239.07:44:09.63#ibcon#read 4, iclass 15, count 0 2006.239.07:44:09.63#ibcon#about to read 5, iclass 15, count 0 2006.239.07:44:09.63#ibcon#read 5, iclass 15, count 0 2006.239.07:44:09.63#ibcon#about to read 6, iclass 15, count 0 2006.239.07:44:09.63#ibcon#read 6, iclass 15, count 0 2006.239.07:44:09.63#ibcon#end of sib2, iclass 15, count 0 2006.239.07:44:09.63#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:44:09.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:44:09.63#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:44:09.63#ibcon#*before write, iclass 15, count 0 2006.239.07:44:09.63#ibcon#enter sib2, iclass 15, count 0 2006.239.07:44:09.63#ibcon#flushed, iclass 15, count 0 2006.239.07:44:09.63#ibcon#about to write, iclass 15, count 0 2006.239.07:44:09.63#ibcon#wrote, iclass 15, count 0 2006.239.07:44:09.63#ibcon#about to read 3, iclass 15, count 0 2006.239.07:44:09.67#ibcon#read 3, iclass 15, count 0 2006.239.07:44:09.67#ibcon#about to read 4, iclass 15, count 0 2006.239.07:44:09.67#ibcon#read 4, iclass 15, count 0 2006.239.07:44:09.67#ibcon#about to read 5, iclass 15, count 0 2006.239.07:44:09.67#ibcon#read 5, iclass 15, count 0 2006.239.07:44:09.67#ibcon#about to read 6, iclass 15, count 0 2006.239.07:44:09.67#ibcon#read 6, iclass 15, count 0 2006.239.07:44:09.67#ibcon#end of sib2, iclass 15, count 0 2006.239.07:44:09.67#ibcon#*after write, iclass 15, count 0 2006.239.07:44:09.67#ibcon#*before return 0, iclass 15, count 0 2006.239.07:44:09.67#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:44:09.67#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:44:09.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:44:09.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:44:09.67$vc4f8/va=8,7 2006.239.07:44:09.67#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.07:44:09.67#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.07:44:09.67#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:09.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:44:09.74#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:44:09.74#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:44:09.74#ibcon#enter wrdev, iclass 17, count 2 2006.239.07:44:09.74#ibcon#first serial, iclass 17, count 2 2006.239.07:44:09.74#ibcon#enter sib2, iclass 17, count 2 2006.239.07:44:09.74#ibcon#flushed, iclass 17, count 2 2006.239.07:44:09.74#ibcon#about to write, iclass 17, count 2 2006.239.07:44:09.74#ibcon#wrote, iclass 17, count 2 2006.239.07:44:09.74#ibcon#about to read 3, iclass 17, count 2 2006.239.07:44:09.76#ibcon#read 3, iclass 17, count 2 2006.239.07:44:09.76#ibcon#about to read 4, iclass 17, count 2 2006.239.07:44:09.76#ibcon#read 4, iclass 17, count 2 2006.239.07:44:09.76#ibcon#about to read 5, iclass 17, count 2 2006.239.07:44:09.76#ibcon#read 5, iclass 17, count 2 2006.239.07:44:09.76#ibcon#about to read 6, iclass 17, count 2 2006.239.07:44:09.76#ibcon#read 6, iclass 17, count 2 2006.239.07:44:09.76#ibcon#end of sib2, iclass 17, count 2 2006.239.07:44:09.76#ibcon#*mode == 0, iclass 17, count 2 2006.239.07:44:09.76#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.07:44:09.76#ibcon#[25=AT08-07\r\n] 2006.239.07:44:09.76#ibcon#*before write, iclass 17, count 2 2006.239.07:44:09.76#ibcon#enter sib2, iclass 17, count 2 2006.239.07:44:09.76#ibcon#flushed, iclass 17, count 2 2006.239.07:44:09.76#ibcon#about to write, iclass 17, count 2 2006.239.07:44:09.76#ibcon#wrote, iclass 17, count 2 2006.239.07:44:09.76#ibcon#about to read 3, iclass 17, count 2 2006.239.07:44:09.79#ibcon#read 3, iclass 17, count 2 2006.239.07:44:09.79#ibcon#about to read 4, iclass 17, count 2 2006.239.07:44:09.79#ibcon#read 4, iclass 17, count 2 2006.239.07:44:09.79#ibcon#about to read 5, iclass 17, count 2 2006.239.07:44:09.79#ibcon#read 5, iclass 17, count 2 2006.239.07:44:09.79#ibcon#about to read 6, iclass 17, count 2 2006.239.07:44:09.79#ibcon#read 6, iclass 17, count 2 2006.239.07:44:09.79#ibcon#end of sib2, iclass 17, count 2 2006.239.07:44:09.79#ibcon#*after write, iclass 17, count 2 2006.239.07:44:09.79#ibcon#*before return 0, iclass 17, count 2 2006.239.07:44:09.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:44:09.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:44:09.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.07:44:09.79#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:09.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:44:09.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:44:09.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:44:09.91#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:44:09.91#ibcon#first serial, iclass 17, count 0 2006.239.07:44:09.91#ibcon#enter sib2, iclass 17, count 0 2006.239.07:44:09.91#ibcon#flushed, iclass 17, count 0 2006.239.07:44:09.91#ibcon#about to write, iclass 17, count 0 2006.239.07:44:09.91#ibcon#wrote, iclass 17, count 0 2006.239.07:44:09.91#ibcon#about to read 3, iclass 17, count 0 2006.239.07:44:09.93#ibcon#read 3, iclass 17, count 0 2006.239.07:44:09.93#ibcon#about to read 4, iclass 17, count 0 2006.239.07:44:09.93#ibcon#read 4, iclass 17, count 0 2006.239.07:44:09.93#ibcon#about to read 5, iclass 17, count 0 2006.239.07:44:09.93#ibcon#read 5, iclass 17, count 0 2006.239.07:44:09.93#ibcon#about to read 6, iclass 17, count 0 2006.239.07:44:09.93#ibcon#read 6, iclass 17, count 0 2006.239.07:44:09.93#ibcon#end of sib2, iclass 17, count 0 2006.239.07:44:09.93#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:44:09.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:44:09.93#ibcon#[25=USB\r\n] 2006.239.07:44:09.93#ibcon#*before write, iclass 17, count 0 2006.239.07:44:09.93#ibcon#enter sib2, iclass 17, count 0 2006.239.07:44:09.93#ibcon#flushed, iclass 17, count 0 2006.239.07:44:09.93#ibcon#about to write, iclass 17, count 0 2006.239.07:44:09.93#ibcon#wrote, iclass 17, count 0 2006.239.07:44:09.93#ibcon#about to read 3, iclass 17, count 0 2006.239.07:44:09.96#ibcon#read 3, iclass 17, count 0 2006.239.07:44:09.96#ibcon#about to read 4, iclass 17, count 0 2006.239.07:44:09.96#ibcon#read 4, iclass 17, count 0 2006.239.07:44:09.96#ibcon#about to read 5, iclass 17, count 0 2006.239.07:44:09.96#ibcon#read 5, iclass 17, count 0 2006.239.07:44:09.96#ibcon#about to read 6, iclass 17, count 0 2006.239.07:44:09.96#ibcon#read 6, iclass 17, count 0 2006.239.07:44:09.96#ibcon#end of sib2, iclass 17, count 0 2006.239.07:44:09.96#ibcon#*after write, iclass 17, count 0 2006.239.07:44:09.96#ibcon#*before return 0, iclass 17, count 0 2006.239.07:44:09.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:44:09.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:44:09.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:44:09.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:44:09.96$vc4f8/vblo=1,632.99 2006.239.07:44:09.96#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.07:44:09.96#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.07:44:09.96#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:09.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:44:09.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:44:09.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:44:09.96#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:44:09.96#ibcon#first serial, iclass 19, count 0 2006.239.07:44:09.96#ibcon#enter sib2, iclass 19, count 0 2006.239.07:44:09.96#ibcon#flushed, iclass 19, count 0 2006.239.07:44:09.96#ibcon#about to write, iclass 19, count 0 2006.239.07:44:09.96#ibcon#wrote, iclass 19, count 0 2006.239.07:44:09.96#ibcon#about to read 3, iclass 19, count 0 2006.239.07:44:09.98#ibcon#read 3, iclass 19, count 0 2006.239.07:44:09.98#ibcon#about to read 4, iclass 19, count 0 2006.239.07:44:09.98#ibcon#read 4, iclass 19, count 0 2006.239.07:44:09.98#ibcon#about to read 5, iclass 19, count 0 2006.239.07:44:09.98#ibcon#read 5, iclass 19, count 0 2006.239.07:44:09.98#ibcon#about to read 6, iclass 19, count 0 2006.239.07:44:09.98#ibcon#read 6, iclass 19, count 0 2006.239.07:44:09.98#ibcon#end of sib2, iclass 19, count 0 2006.239.07:44:09.98#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:44:09.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:44:09.98#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:44:09.98#ibcon#*before write, iclass 19, count 0 2006.239.07:44:09.98#ibcon#enter sib2, iclass 19, count 0 2006.239.07:44:09.98#ibcon#flushed, iclass 19, count 0 2006.239.07:44:09.98#ibcon#about to write, iclass 19, count 0 2006.239.07:44:09.98#ibcon#wrote, iclass 19, count 0 2006.239.07:44:09.98#ibcon#about to read 3, iclass 19, count 0 2006.239.07:44:10.02#ibcon#read 3, iclass 19, count 0 2006.239.07:44:10.02#ibcon#about to read 4, iclass 19, count 0 2006.239.07:44:10.02#ibcon#read 4, iclass 19, count 0 2006.239.07:44:10.02#ibcon#about to read 5, iclass 19, count 0 2006.239.07:44:10.02#ibcon#read 5, iclass 19, count 0 2006.239.07:44:10.02#ibcon#about to read 6, iclass 19, count 0 2006.239.07:44:10.02#ibcon#read 6, iclass 19, count 0 2006.239.07:44:10.02#ibcon#end of sib2, iclass 19, count 0 2006.239.07:44:10.02#ibcon#*after write, iclass 19, count 0 2006.239.07:44:10.02#ibcon#*before return 0, iclass 19, count 0 2006.239.07:44:10.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:44:10.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:44:10.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:44:10.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:44:10.02$vc4f8/vb=1,4 2006.239.07:44:10.02#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.07:44:10.02#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.07:44:10.02#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:10.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:44:10.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:44:10.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:44:10.02#ibcon#enter wrdev, iclass 21, count 2 2006.239.07:44:10.02#ibcon#first serial, iclass 21, count 2 2006.239.07:44:10.02#ibcon#enter sib2, iclass 21, count 2 2006.239.07:44:10.02#ibcon#flushed, iclass 21, count 2 2006.239.07:44:10.02#ibcon#about to write, iclass 21, count 2 2006.239.07:44:10.02#ibcon#wrote, iclass 21, count 2 2006.239.07:44:10.02#ibcon#about to read 3, iclass 21, count 2 2006.239.07:44:10.04#ibcon#read 3, iclass 21, count 2 2006.239.07:44:10.04#ibcon#about to read 4, iclass 21, count 2 2006.239.07:44:10.04#ibcon#read 4, iclass 21, count 2 2006.239.07:44:10.04#ibcon#about to read 5, iclass 21, count 2 2006.239.07:44:10.04#ibcon#read 5, iclass 21, count 2 2006.239.07:44:10.04#ibcon#about to read 6, iclass 21, count 2 2006.239.07:44:10.04#ibcon#read 6, iclass 21, count 2 2006.239.07:44:10.04#ibcon#end of sib2, iclass 21, count 2 2006.239.07:44:10.04#ibcon#*mode == 0, iclass 21, count 2 2006.239.07:44:10.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.07:44:10.04#ibcon#[27=AT01-04\r\n] 2006.239.07:44:10.04#ibcon#*before write, iclass 21, count 2 2006.239.07:44:10.04#ibcon#enter sib2, iclass 21, count 2 2006.239.07:44:10.04#ibcon#flushed, iclass 21, count 2 2006.239.07:44:10.04#ibcon#about to write, iclass 21, count 2 2006.239.07:44:10.04#ibcon#wrote, iclass 21, count 2 2006.239.07:44:10.04#ibcon#about to read 3, iclass 21, count 2 2006.239.07:44:10.07#ibcon#read 3, iclass 21, count 2 2006.239.07:44:10.07#ibcon#about to read 4, iclass 21, count 2 2006.239.07:44:10.07#ibcon#read 4, iclass 21, count 2 2006.239.07:44:10.07#ibcon#about to read 5, iclass 21, count 2 2006.239.07:44:10.07#ibcon#read 5, iclass 21, count 2 2006.239.07:44:10.07#ibcon#about to read 6, iclass 21, count 2 2006.239.07:44:10.07#ibcon#read 6, iclass 21, count 2 2006.239.07:44:10.07#ibcon#end of sib2, iclass 21, count 2 2006.239.07:44:10.07#ibcon#*after write, iclass 21, count 2 2006.239.07:44:10.07#ibcon#*before return 0, iclass 21, count 2 2006.239.07:44:10.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:44:10.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:44:10.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.07:44:10.07#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:10.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:44:10.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:44:10.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:44:10.19#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:44:10.19#ibcon#first serial, iclass 21, count 0 2006.239.07:44:10.19#ibcon#enter sib2, iclass 21, count 0 2006.239.07:44:10.19#ibcon#flushed, iclass 21, count 0 2006.239.07:44:10.19#ibcon#about to write, iclass 21, count 0 2006.239.07:44:10.19#ibcon#wrote, iclass 21, count 0 2006.239.07:44:10.19#ibcon#about to read 3, iclass 21, count 0 2006.239.07:44:10.21#ibcon#read 3, iclass 21, count 0 2006.239.07:44:10.21#ibcon#about to read 4, iclass 21, count 0 2006.239.07:44:10.21#ibcon#read 4, iclass 21, count 0 2006.239.07:44:10.21#ibcon#about to read 5, iclass 21, count 0 2006.239.07:44:10.21#ibcon#read 5, iclass 21, count 0 2006.239.07:44:10.21#ibcon#about to read 6, iclass 21, count 0 2006.239.07:44:10.21#ibcon#read 6, iclass 21, count 0 2006.239.07:44:10.21#ibcon#end of sib2, iclass 21, count 0 2006.239.07:44:10.21#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:44:10.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:44:10.21#ibcon#[27=USB\r\n] 2006.239.07:44:10.21#ibcon#*before write, iclass 21, count 0 2006.239.07:44:10.21#ibcon#enter sib2, iclass 21, count 0 2006.239.07:44:10.21#ibcon#flushed, iclass 21, count 0 2006.239.07:44:10.21#ibcon#about to write, iclass 21, count 0 2006.239.07:44:10.21#ibcon#wrote, iclass 21, count 0 2006.239.07:44:10.21#ibcon#about to read 3, iclass 21, count 0 2006.239.07:44:10.24#ibcon#read 3, iclass 21, count 0 2006.239.07:44:10.24#ibcon#about to read 4, iclass 21, count 0 2006.239.07:44:10.24#ibcon#read 4, iclass 21, count 0 2006.239.07:44:10.24#ibcon#about to read 5, iclass 21, count 0 2006.239.07:44:10.24#ibcon#read 5, iclass 21, count 0 2006.239.07:44:10.24#ibcon#about to read 6, iclass 21, count 0 2006.239.07:44:10.24#ibcon#read 6, iclass 21, count 0 2006.239.07:44:10.24#ibcon#end of sib2, iclass 21, count 0 2006.239.07:44:10.24#ibcon#*after write, iclass 21, count 0 2006.239.07:44:10.24#ibcon#*before return 0, iclass 21, count 0 2006.239.07:44:10.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:44:10.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:44:10.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:44:10.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:44:10.24$vc4f8/vblo=2,640.99 2006.239.07:44:10.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.07:44:10.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.07:44:10.24#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:10.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:44:10.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:44:10.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:44:10.24#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:44:10.24#ibcon#first serial, iclass 23, count 0 2006.239.07:44:10.24#ibcon#enter sib2, iclass 23, count 0 2006.239.07:44:10.24#ibcon#flushed, iclass 23, count 0 2006.239.07:44:10.24#ibcon#about to write, iclass 23, count 0 2006.239.07:44:10.24#ibcon#wrote, iclass 23, count 0 2006.239.07:44:10.24#ibcon#about to read 3, iclass 23, count 0 2006.239.07:44:10.26#ibcon#read 3, iclass 23, count 0 2006.239.07:44:10.26#ibcon#about to read 4, iclass 23, count 0 2006.239.07:44:10.26#ibcon#read 4, iclass 23, count 0 2006.239.07:44:10.26#ibcon#about to read 5, iclass 23, count 0 2006.239.07:44:10.26#ibcon#read 5, iclass 23, count 0 2006.239.07:44:10.26#ibcon#about to read 6, iclass 23, count 0 2006.239.07:44:10.26#ibcon#read 6, iclass 23, count 0 2006.239.07:44:10.26#ibcon#end of sib2, iclass 23, count 0 2006.239.07:44:10.26#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:44:10.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:44:10.26#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:44:10.26#ibcon#*before write, iclass 23, count 0 2006.239.07:44:10.26#ibcon#enter sib2, iclass 23, count 0 2006.239.07:44:10.26#ibcon#flushed, iclass 23, count 0 2006.239.07:44:10.26#ibcon#about to write, iclass 23, count 0 2006.239.07:44:10.26#ibcon#wrote, iclass 23, count 0 2006.239.07:44:10.26#ibcon#about to read 3, iclass 23, count 0 2006.239.07:44:10.30#ibcon#read 3, iclass 23, count 0 2006.239.07:44:10.30#ibcon#about to read 4, iclass 23, count 0 2006.239.07:44:10.30#ibcon#read 4, iclass 23, count 0 2006.239.07:44:10.30#ibcon#about to read 5, iclass 23, count 0 2006.239.07:44:10.30#ibcon#read 5, iclass 23, count 0 2006.239.07:44:10.30#ibcon#about to read 6, iclass 23, count 0 2006.239.07:44:10.30#ibcon#read 6, iclass 23, count 0 2006.239.07:44:10.30#ibcon#end of sib2, iclass 23, count 0 2006.239.07:44:10.30#ibcon#*after write, iclass 23, count 0 2006.239.07:44:10.30#ibcon#*before return 0, iclass 23, count 0 2006.239.07:44:10.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:44:10.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:44:10.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:44:10.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:44:10.30$vc4f8/vb=2,4 2006.239.07:44:10.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.07:44:10.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.07:44:10.30#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:10.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:10.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:10.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:10.36#ibcon#enter wrdev, iclass 25, count 2 2006.239.07:44:10.36#ibcon#first serial, iclass 25, count 2 2006.239.07:44:10.36#ibcon#enter sib2, iclass 25, count 2 2006.239.07:44:10.36#ibcon#flushed, iclass 25, count 2 2006.239.07:44:10.36#ibcon#about to write, iclass 25, count 2 2006.239.07:44:10.36#ibcon#wrote, iclass 25, count 2 2006.239.07:44:10.36#ibcon#about to read 3, iclass 25, count 2 2006.239.07:44:10.38#ibcon#read 3, iclass 25, count 2 2006.239.07:44:10.38#ibcon#about to read 4, iclass 25, count 2 2006.239.07:44:10.38#ibcon#read 4, iclass 25, count 2 2006.239.07:44:10.38#ibcon#about to read 5, iclass 25, count 2 2006.239.07:44:10.38#ibcon#read 5, iclass 25, count 2 2006.239.07:44:10.38#ibcon#about to read 6, iclass 25, count 2 2006.239.07:44:10.38#ibcon#read 6, iclass 25, count 2 2006.239.07:44:10.38#ibcon#end of sib2, iclass 25, count 2 2006.239.07:44:10.38#ibcon#*mode == 0, iclass 25, count 2 2006.239.07:44:10.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.07:44:10.38#ibcon#[27=AT02-04\r\n] 2006.239.07:44:10.38#ibcon#*before write, iclass 25, count 2 2006.239.07:44:10.38#ibcon#enter sib2, iclass 25, count 2 2006.239.07:44:10.38#ibcon#flushed, iclass 25, count 2 2006.239.07:44:10.38#ibcon#about to write, iclass 25, count 2 2006.239.07:44:10.38#ibcon#wrote, iclass 25, count 2 2006.239.07:44:10.38#ibcon#about to read 3, iclass 25, count 2 2006.239.07:44:10.41#ibcon#read 3, iclass 25, count 2 2006.239.07:44:10.41#ibcon#about to read 4, iclass 25, count 2 2006.239.07:44:10.41#ibcon#read 4, iclass 25, count 2 2006.239.07:44:10.41#ibcon#about to read 5, iclass 25, count 2 2006.239.07:44:10.41#ibcon#read 5, iclass 25, count 2 2006.239.07:44:10.41#ibcon#about to read 6, iclass 25, count 2 2006.239.07:44:10.41#ibcon#read 6, iclass 25, count 2 2006.239.07:44:10.41#ibcon#end of sib2, iclass 25, count 2 2006.239.07:44:10.41#ibcon#*after write, iclass 25, count 2 2006.239.07:44:10.41#ibcon#*before return 0, iclass 25, count 2 2006.239.07:44:10.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:10.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:44:10.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.07:44:10.41#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:10.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:10.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:10.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:10.53#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:44:10.53#ibcon#first serial, iclass 25, count 0 2006.239.07:44:10.53#ibcon#enter sib2, iclass 25, count 0 2006.239.07:44:10.53#ibcon#flushed, iclass 25, count 0 2006.239.07:44:10.53#ibcon#about to write, iclass 25, count 0 2006.239.07:44:10.53#ibcon#wrote, iclass 25, count 0 2006.239.07:44:10.53#ibcon#about to read 3, iclass 25, count 0 2006.239.07:44:10.55#ibcon#read 3, iclass 25, count 0 2006.239.07:44:10.55#ibcon#about to read 4, iclass 25, count 0 2006.239.07:44:10.55#ibcon#read 4, iclass 25, count 0 2006.239.07:44:10.55#ibcon#about to read 5, iclass 25, count 0 2006.239.07:44:10.55#ibcon#read 5, iclass 25, count 0 2006.239.07:44:10.55#ibcon#about to read 6, iclass 25, count 0 2006.239.07:44:10.55#ibcon#read 6, iclass 25, count 0 2006.239.07:44:10.55#ibcon#end of sib2, iclass 25, count 0 2006.239.07:44:10.55#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:44:10.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:44:10.55#ibcon#[27=USB\r\n] 2006.239.07:44:10.55#ibcon#*before write, iclass 25, count 0 2006.239.07:44:10.55#ibcon#enter sib2, iclass 25, count 0 2006.239.07:44:10.55#ibcon#flushed, iclass 25, count 0 2006.239.07:44:10.55#ibcon#about to write, iclass 25, count 0 2006.239.07:44:10.55#ibcon#wrote, iclass 25, count 0 2006.239.07:44:10.55#ibcon#about to read 3, iclass 25, count 0 2006.239.07:44:10.58#ibcon#read 3, iclass 25, count 0 2006.239.07:44:10.58#ibcon#about to read 4, iclass 25, count 0 2006.239.07:44:10.58#ibcon#read 4, iclass 25, count 0 2006.239.07:44:10.58#ibcon#about to read 5, iclass 25, count 0 2006.239.07:44:10.58#ibcon#read 5, iclass 25, count 0 2006.239.07:44:10.58#ibcon#about to read 6, iclass 25, count 0 2006.239.07:44:10.58#ibcon#read 6, iclass 25, count 0 2006.239.07:44:10.58#ibcon#end of sib2, iclass 25, count 0 2006.239.07:44:10.58#ibcon#*after write, iclass 25, count 0 2006.239.07:44:10.58#ibcon#*before return 0, iclass 25, count 0 2006.239.07:44:10.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:10.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:44:10.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:44:10.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:44:10.58$vc4f8/vblo=3,656.99 2006.239.07:44:10.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.07:44:10.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.07:44:10.58#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:10.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:10.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:10.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:10.58#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:44:10.58#ibcon#first serial, iclass 27, count 0 2006.239.07:44:10.58#ibcon#enter sib2, iclass 27, count 0 2006.239.07:44:10.58#ibcon#flushed, iclass 27, count 0 2006.239.07:44:10.58#ibcon#about to write, iclass 27, count 0 2006.239.07:44:10.58#ibcon#wrote, iclass 27, count 0 2006.239.07:44:10.58#ibcon#about to read 3, iclass 27, count 0 2006.239.07:44:10.60#ibcon#read 3, iclass 27, count 0 2006.239.07:44:10.60#ibcon#about to read 4, iclass 27, count 0 2006.239.07:44:10.60#ibcon#read 4, iclass 27, count 0 2006.239.07:44:10.60#ibcon#about to read 5, iclass 27, count 0 2006.239.07:44:10.60#ibcon#read 5, iclass 27, count 0 2006.239.07:44:10.60#ibcon#about to read 6, iclass 27, count 0 2006.239.07:44:10.60#ibcon#read 6, iclass 27, count 0 2006.239.07:44:10.60#ibcon#end of sib2, iclass 27, count 0 2006.239.07:44:10.60#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:44:10.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:44:10.60#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:44:10.60#ibcon#*before write, iclass 27, count 0 2006.239.07:44:10.60#ibcon#enter sib2, iclass 27, count 0 2006.239.07:44:10.60#ibcon#flushed, iclass 27, count 0 2006.239.07:44:10.60#ibcon#about to write, iclass 27, count 0 2006.239.07:44:10.60#ibcon#wrote, iclass 27, count 0 2006.239.07:44:10.60#ibcon#about to read 3, iclass 27, count 0 2006.239.07:44:10.64#ibcon#read 3, iclass 27, count 0 2006.239.07:44:10.64#ibcon#about to read 4, iclass 27, count 0 2006.239.07:44:10.64#ibcon#read 4, iclass 27, count 0 2006.239.07:44:10.64#ibcon#about to read 5, iclass 27, count 0 2006.239.07:44:10.64#ibcon#read 5, iclass 27, count 0 2006.239.07:44:10.64#ibcon#about to read 6, iclass 27, count 0 2006.239.07:44:10.64#ibcon#read 6, iclass 27, count 0 2006.239.07:44:10.64#ibcon#end of sib2, iclass 27, count 0 2006.239.07:44:10.64#ibcon#*after write, iclass 27, count 0 2006.239.07:44:10.64#ibcon#*before return 0, iclass 27, count 0 2006.239.07:44:10.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:10.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:44:10.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:44:10.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:44:10.64$vc4f8/vb=3,4 2006.239.07:44:10.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.07:44:10.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.07:44:10.64#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:10.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:10.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:10.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:10.70#ibcon#enter wrdev, iclass 29, count 2 2006.239.07:44:10.70#ibcon#first serial, iclass 29, count 2 2006.239.07:44:10.70#ibcon#enter sib2, iclass 29, count 2 2006.239.07:44:10.70#ibcon#flushed, iclass 29, count 2 2006.239.07:44:10.70#ibcon#about to write, iclass 29, count 2 2006.239.07:44:10.70#ibcon#wrote, iclass 29, count 2 2006.239.07:44:10.70#ibcon#about to read 3, iclass 29, count 2 2006.239.07:44:10.72#ibcon#read 3, iclass 29, count 2 2006.239.07:44:10.72#ibcon#about to read 4, iclass 29, count 2 2006.239.07:44:10.72#ibcon#read 4, iclass 29, count 2 2006.239.07:44:10.72#ibcon#about to read 5, iclass 29, count 2 2006.239.07:44:10.72#ibcon#read 5, iclass 29, count 2 2006.239.07:44:10.72#ibcon#about to read 6, iclass 29, count 2 2006.239.07:44:10.72#ibcon#read 6, iclass 29, count 2 2006.239.07:44:10.72#ibcon#end of sib2, iclass 29, count 2 2006.239.07:44:10.72#ibcon#*mode == 0, iclass 29, count 2 2006.239.07:44:10.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.07:44:10.72#ibcon#[27=AT03-04\r\n] 2006.239.07:44:10.72#ibcon#*before write, iclass 29, count 2 2006.239.07:44:10.72#ibcon#enter sib2, iclass 29, count 2 2006.239.07:44:10.72#ibcon#flushed, iclass 29, count 2 2006.239.07:44:10.72#ibcon#about to write, iclass 29, count 2 2006.239.07:44:10.72#ibcon#wrote, iclass 29, count 2 2006.239.07:44:10.72#ibcon#about to read 3, iclass 29, count 2 2006.239.07:44:10.75#ibcon#read 3, iclass 29, count 2 2006.239.07:44:10.75#ibcon#about to read 4, iclass 29, count 2 2006.239.07:44:10.75#ibcon#read 4, iclass 29, count 2 2006.239.07:44:10.75#ibcon#about to read 5, iclass 29, count 2 2006.239.07:44:10.75#ibcon#read 5, iclass 29, count 2 2006.239.07:44:10.75#ibcon#about to read 6, iclass 29, count 2 2006.239.07:44:10.75#ibcon#read 6, iclass 29, count 2 2006.239.07:44:10.75#ibcon#end of sib2, iclass 29, count 2 2006.239.07:44:10.75#ibcon#*after write, iclass 29, count 2 2006.239.07:44:10.75#ibcon#*before return 0, iclass 29, count 2 2006.239.07:44:10.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:10.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:44:10.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.07:44:10.75#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:10.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:10.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:10.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:10.87#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:44:10.87#ibcon#first serial, iclass 29, count 0 2006.239.07:44:10.87#ibcon#enter sib2, iclass 29, count 0 2006.239.07:44:10.87#ibcon#flushed, iclass 29, count 0 2006.239.07:44:10.87#ibcon#about to write, iclass 29, count 0 2006.239.07:44:10.87#ibcon#wrote, iclass 29, count 0 2006.239.07:44:10.87#ibcon#about to read 3, iclass 29, count 0 2006.239.07:44:10.89#ibcon#read 3, iclass 29, count 0 2006.239.07:44:10.89#ibcon#about to read 4, iclass 29, count 0 2006.239.07:44:10.89#ibcon#read 4, iclass 29, count 0 2006.239.07:44:10.89#ibcon#about to read 5, iclass 29, count 0 2006.239.07:44:10.89#ibcon#read 5, iclass 29, count 0 2006.239.07:44:10.89#ibcon#about to read 6, iclass 29, count 0 2006.239.07:44:10.89#ibcon#read 6, iclass 29, count 0 2006.239.07:44:10.89#ibcon#end of sib2, iclass 29, count 0 2006.239.07:44:10.89#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:44:10.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:44:10.89#ibcon#[27=USB\r\n] 2006.239.07:44:10.89#ibcon#*before write, iclass 29, count 0 2006.239.07:44:10.89#ibcon#enter sib2, iclass 29, count 0 2006.239.07:44:10.89#ibcon#flushed, iclass 29, count 0 2006.239.07:44:10.89#ibcon#about to write, iclass 29, count 0 2006.239.07:44:10.89#ibcon#wrote, iclass 29, count 0 2006.239.07:44:10.89#ibcon#about to read 3, iclass 29, count 0 2006.239.07:44:10.92#ibcon#read 3, iclass 29, count 0 2006.239.07:44:10.92#ibcon#about to read 4, iclass 29, count 0 2006.239.07:44:10.92#ibcon#read 4, iclass 29, count 0 2006.239.07:44:10.92#ibcon#about to read 5, iclass 29, count 0 2006.239.07:44:10.92#ibcon#read 5, iclass 29, count 0 2006.239.07:44:10.92#ibcon#about to read 6, iclass 29, count 0 2006.239.07:44:10.92#ibcon#read 6, iclass 29, count 0 2006.239.07:44:10.92#ibcon#end of sib2, iclass 29, count 0 2006.239.07:44:10.92#ibcon#*after write, iclass 29, count 0 2006.239.07:44:10.92#ibcon#*before return 0, iclass 29, count 0 2006.239.07:44:10.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:10.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:44:10.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:44:10.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:44:10.92$vc4f8/vblo=4,712.99 2006.239.07:44:10.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.07:44:10.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.07:44:10.92#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:10.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:10.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:10.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:10.92#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:44:10.92#ibcon#first serial, iclass 31, count 0 2006.239.07:44:10.92#ibcon#enter sib2, iclass 31, count 0 2006.239.07:44:10.92#ibcon#flushed, iclass 31, count 0 2006.239.07:44:10.92#ibcon#about to write, iclass 31, count 0 2006.239.07:44:10.92#ibcon#wrote, iclass 31, count 0 2006.239.07:44:10.92#ibcon#about to read 3, iclass 31, count 0 2006.239.07:44:10.94#ibcon#read 3, iclass 31, count 0 2006.239.07:44:10.94#ibcon#about to read 4, iclass 31, count 0 2006.239.07:44:10.94#ibcon#read 4, iclass 31, count 0 2006.239.07:44:10.94#ibcon#about to read 5, iclass 31, count 0 2006.239.07:44:10.94#ibcon#read 5, iclass 31, count 0 2006.239.07:44:10.94#ibcon#about to read 6, iclass 31, count 0 2006.239.07:44:10.94#ibcon#read 6, iclass 31, count 0 2006.239.07:44:10.94#ibcon#end of sib2, iclass 31, count 0 2006.239.07:44:10.94#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:44:10.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:44:10.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:44:10.94#ibcon#*before write, iclass 31, count 0 2006.239.07:44:10.94#ibcon#enter sib2, iclass 31, count 0 2006.239.07:44:10.94#ibcon#flushed, iclass 31, count 0 2006.239.07:44:10.94#ibcon#about to write, iclass 31, count 0 2006.239.07:44:10.94#ibcon#wrote, iclass 31, count 0 2006.239.07:44:10.94#ibcon#about to read 3, iclass 31, count 0 2006.239.07:44:10.98#ibcon#read 3, iclass 31, count 0 2006.239.07:44:10.98#ibcon#about to read 4, iclass 31, count 0 2006.239.07:44:10.98#ibcon#read 4, iclass 31, count 0 2006.239.07:44:10.98#ibcon#about to read 5, iclass 31, count 0 2006.239.07:44:10.98#ibcon#read 5, iclass 31, count 0 2006.239.07:44:10.98#ibcon#about to read 6, iclass 31, count 0 2006.239.07:44:10.98#ibcon#read 6, iclass 31, count 0 2006.239.07:44:10.98#ibcon#end of sib2, iclass 31, count 0 2006.239.07:44:10.98#ibcon#*after write, iclass 31, count 0 2006.239.07:44:10.98#ibcon#*before return 0, iclass 31, count 0 2006.239.07:44:10.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:10.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:44:10.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:44:10.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:44:10.98$vc4f8/vb=4,4 2006.239.07:44:10.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.07:44:10.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.07:44:10.98#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:10.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:11.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:11.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:11.04#ibcon#enter wrdev, iclass 33, count 2 2006.239.07:44:11.04#ibcon#first serial, iclass 33, count 2 2006.239.07:44:11.04#ibcon#enter sib2, iclass 33, count 2 2006.239.07:44:11.04#ibcon#flushed, iclass 33, count 2 2006.239.07:44:11.04#ibcon#about to write, iclass 33, count 2 2006.239.07:44:11.04#ibcon#wrote, iclass 33, count 2 2006.239.07:44:11.04#ibcon#about to read 3, iclass 33, count 2 2006.239.07:44:11.06#ibcon#read 3, iclass 33, count 2 2006.239.07:44:11.06#ibcon#about to read 4, iclass 33, count 2 2006.239.07:44:11.06#ibcon#read 4, iclass 33, count 2 2006.239.07:44:11.06#ibcon#about to read 5, iclass 33, count 2 2006.239.07:44:11.06#ibcon#read 5, iclass 33, count 2 2006.239.07:44:11.06#ibcon#about to read 6, iclass 33, count 2 2006.239.07:44:11.06#ibcon#read 6, iclass 33, count 2 2006.239.07:44:11.06#ibcon#end of sib2, iclass 33, count 2 2006.239.07:44:11.06#ibcon#*mode == 0, iclass 33, count 2 2006.239.07:44:11.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.07:44:11.06#ibcon#[27=AT04-04\r\n] 2006.239.07:44:11.06#ibcon#*before write, iclass 33, count 2 2006.239.07:44:11.06#ibcon#enter sib2, iclass 33, count 2 2006.239.07:44:11.06#ibcon#flushed, iclass 33, count 2 2006.239.07:44:11.06#ibcon#about to write, iclass 33, count 2 2006.239.07:44:11.06#ibcon#wrote, iclass 33, count 2 2006.239.07:44:11.06#ibcon#about to read 3, iclass 33, count 2 2006.239.07:44:11.09#ibcon#read 3, iclass 33, count 2 2006.239.07:44:11.09#ibcon#about to read 4, iclass 33, count 2 2006.239.07:44:11.09#ibcon#read 4, iclass 33, count 2 2006.239.07:44:11.09#ibcon#about to read 5, iclass 33, count 2 2006.239.07:44:11.09#ibcon#read 5, iclass 33, count 2 2006.239.07:44:11.09#ibcon#about to read 6, iclass 33, count 2 2006.239.07:44:11.09#ibcon#read 6, iclass 33, count 2 2006.239.07:44:11.09#ibcon#end of sib2, iclass 33, count 2 2006.239.07:44:11.09#ibcon#*after write, iclass 33, count 2 2006.239.07:44:11.09#ibcon#*before return 0, iclass 33, count 2 2006.239.07:44:11.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:11.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:44:11.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.07:44:11.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:11.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:11.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:11.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:11.21#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:44:11.21#ibcon#first serial, iclass 33, count 0 2006.239.07:44:11.21#ibcon#enter sib2, iclass 33, count 0 2006.239.07:44:11.21#ibcon#flushed, iclass 33, count 0 2006.239.07:44:11.21#ibcon#about to write, iclass 33, count 0 2006.239.07:44:11.21#ibcon#wrote, iclass 33, count 0 2006.239.07:44:11.21#ibcon#about to read 3, iclass 33, count 0 2006.239.07:44:11.23#ibcon#read 3, iclass 33, count 0 2006.239.07:44:11.23#ibcon#about to read 4, iclass 33, count 0 2006.239.07:44:11.23#ibcon#read 4, iclass 33, count 0 2006.239.07:44:11.23#ibcon#about to read 5, iclass 33, count 0 2006.239.07:44:11.23#ibcon#read 5, iclass 33, count 0 2006.239.07:44:11.23#ibcon#about to read 6, iclass 33, count 0 2006.239.07:44:11.23#ibcon#read 6, iclass 33, count 0 2006.239.07:44:11.23#ibcon#end of sib2, iclass 33, count 0 2006.239.07:44:11.23#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:44:11.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:44:11.23#ibcon#[27=USB\r\n] 2006.239.07:44:11.23#ibcon#*before write, iclass 33, count 0 2006.239.07:44:11.23#ibcon#enter sib2, iclass 33, count 0 2006.239.07:44:11.23#ibcon#flushed, iclass 33, count 0 2006.239.07:44:11.23#ibcon#about to write, iclass 33, count 0 2006.239.07:44:11.23#ibcon#wrote, iclass 33, count 0 2006.239.07:44:11.23#ibcon#about to read 3, iclass 33, count 0 2006.239.07:44:11.26#ibcon#read 3, iclass 33, count 0 2006.239.07:44:11.26#ibcon#about to read 4, iclass 33, count 0 2006.239.07:44:11.26#ibcon#read 4, iclass 33, count 0 2006.239.07:44:11.26#ibcon#about to read 5, iclass 33, count 0 2006.239.07:44:11.26#ibcon#read 5, iclass 33, count 0 2006.239.07:44:11.26#ibcon#about to read 6, iclass 33, count 0 2006.239.07:44:11.26#ibcon#read 6, iclass 33, count 0 2006.239.07:44:11.26#ibcon#end of sib2, iclass 33, count 0 2006.239.07:44:11.26#ibcon#*after write, iclass 33, count 0 2006.239.07:44:11.26#ibcon#*before return 0, iclass 33, count 0 2006.239.07:44:11.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:11.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:44:11.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:44:11.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:44:11.26$vc4f8/vblo=5,744.99 2006.239.07:44:11.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.07:44:11.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.07:44:11.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:11.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:11.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:11.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:11.26#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:44:11.26#ibcon#first serial, iclass 35, count 0 2006.239.07:44:11.26#ibcon#enter sib2, iclass 35, count 0 2006.239.07:44:11.26#ibcon#flushed, iclass 35, count 0 2006.239.07:44:11.26#ibcon#about to write, iclass 35, count 0 2006.239.07:44:11.26#ibcon#wrote, iclass 35, count 0 2006.239.07:44:11.26#ibcon#about to read 3, iclass 35, count 0 2006.239.07:44:11.28#ibcon#read 3, iclass 35, count 0 2006.239.07:44:11.28#ibcon#about to read 4, iclass 35, count 0 2006.239.07:44:11.28#ibcon#read 4, iclass 35, count 0 2006.239.07:44:11.28#ibcon#about to read 5, iclass 35, count 0 2006.239.07:44:11.28#ibcon#read 5, iclass 35, count 0 2006.239.07:44:11.28#ibcon#about to read 6, iclass 35, count 0 2006.239.07:44:11.28#ibcon#read 6, iclass 35, count 0 2006.239.07:44:11.28#ibcon#end of sib2, iclass 35, count 0 2006.239.07:44:11.28#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:44:11.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:44:11.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:44:11.28#ibcon#*before write, iclass 35, count 0 2006.239.07:44:11.28#ibcon#enter sib2, iclass 35, count 0 2006.239.07:44:11.28#ibcon#flushed, iclass 35, count 0 2006.239.07:44:11.28#ibcon#about to write, iclass 35, count 0 2006.239.07:44:11.28#ibcon#wrote, iclass 35, count 0 2006.239.07:44:11.28#ibcon#about to read 3, iclass 35, count 0 2006.239.07:44:11.32#ibcon#read 3, iclass 35, count 0 2006.239.07:44:11.32#ibcon#about to read 4, iclass 35, count 0 2006.239.07:44:11.32#ibcon#read 4, iclass 35, count 0 2006.239.07:44:11.32#ibcon#about to read 5, iclass 35, count 0 2006.239.07:44:11.32#ibcon#read 5, iclass 35, count 0 2006.239.07:44:11.32#ibcon#about to read 6, iclass 35, count 0 2006.239.07:44:11.32#ibcon#read 6, iclass 35, count 0 2006.239.07:44:11.32#ibcon#end of sib2, iclass 35, count 0 2006.239.07:44:11.32#ibcon#*after write, iclass 35, count 0 2006.239.07:44:11.32#ibcon#*before return 0, iclass 35, count 0 2006.239.07:44:11.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:11.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:44:11.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:44:11.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:44:11.32$vc4f8/vb=5,4 2006.239.07:44:11.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.07:44:11.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.07:44:11.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:11.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:11.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:11.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:11.38#ibcon#enter wrdev, iclass 37, count 2 2006.239.07:44:11.38#ibcon#first serial, iclass 37, count 2 2006.239.07:44:11.38#ibcon#enter sib2, iclass 37, count 2 2006.239.07:44:11.38#ibcon#flushed, iclass 37, count 2 2006.239.07:44:11.38#ibcon#about to write, iclass 37, count 2 2006.239.07:44:11.38#ibcon#wrote, iclass 37, count 2 2006.239.07:44:11.38#ibcon#about to read 3, iclass 37, count 2 2006.239.07:44:11.40#ibcon#read 3, iclass 37, count 2 2006.239.07:44:11.40#ibcon#about to read 4, iclass 37, count 2 2006.239.07:44:11.40#ibcon#read 4, iclass 37, count 2 2006.239.07:44:11.40#ibcon#about to read 5, iclass 37, count 2 2006.239.07:44:11.40#ibcon#read 5, iclass 37, count 2 2006.239.07:44:11.40#ibcon#about to read 6, iclass 37, count 2 2006.239.07:44:11.40#ibcon#read 6, iclass 37, count 2 2006.239.07:44:11.40#ibcon#end of sib2, iclass 37, count 2 2006.239.07:44:11.40#ibcon#*mode == 0, iclass 37, count 2 2006.239.07:44:11.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.07:44:11.40#ibcon#[27=AT05-04\r\n] 2006.239.07:44:11.40#ibcon#*before write, iclass 37, count 2 2006.239.07:44:11.40#ibcon#enter sib2, iclass 37, count 2 2006.239.07:44:11.40#ibcon#flushed, iclass 37, count 2 2006.239.07:44:11.40#ibcon#about to write, iclass 37, count 2 2006.239.07:44:11.40#ibcon#wrote, iclass 37, count 2 2006.239.07:44:11.40#ibcon#about to read 3, iclass 37, count 2 2006.239.07:44:11.43#ibcon#read 3, iclass 37, count 2 2006.239.07:44:11.43#ibcon#about to read 4, iclass 37, count 2 2006.239.07:44:11.43#ibcon#read 4, iclass 37, count 2 2006.239.07:44:11.43#ibcon#about to read 5, iclass 37, count 2 2006.239.07:44:11.43#ibcon#read 5, iclass 37, count 2 2006.239.07:44:11.43#ibcon#about to read 6, iclass 37, count 2 2006.239.07:44:11.43#ibcon#read 6, iclass 37, count 2 2006.239.07:44:11.43#ibcon#end of sib2, iclass 37, count 2 2006.239.07:44:11.43#ibcon#*after write, iclass 37, count 2 2006.239.07:44:11.43#ibcon#*before return 0, iclass 37, count 2 2006.239.07:44:11.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:11.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:44:11.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.07:44:11.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:11.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:11.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:11.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:11.55#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:44:11.55#ibcon#first serial, iclass 37, count 0 2006.239.07:44:11.55#ibcon#enter sib2, iclass 37, count 0 2006.239.07:44:11.55#ibcon#flushed, iclass 37, count 0 2006.239.07:44:11.55#ibcon#about to write, iclass 37, count 0 2006.239.07:44:11.55#ibcon#wrote, iclass 37, count 0 2006.239.07:44:11.55#ibcon#about to read 3, iclass 37, count 0 2006.239.07:44:11.57#ibcon#read 3, iclass 37, count 0 2006.239.07:44:11.57#ibcon#about to read 4, iclass 37, count 0 2006.239.07:44:11.57#ibcon#read 4, iclass 37, count 0 2006.239.07:44:11.57#ibcon#about to read 5, iclass 37, count 0 2006.239.07:44:11.57#ibcon#read 5, iclass 37, count 0 2006.239.07:44:11.57#ibcon#about to read 6, iclass 37, count 0 2006.239.07:44:11.57#ibcon#read 6, iclass 37, count 0 2006.239.07:44:11.57#ibcon#end of sib2, iclass 37, count 0 2006.239.07:44:11.57#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:44:11.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:44:11.57#ibcon#[27=USB\r\n] 2006.239.07:44:11.57#ibcon#*before write, iclass 37, count 0 2006.239.07:44:11.57#ibcon#enter sib2, iclass 37, count 0 2006.239.07:44:11.57#ibcon#flushed, iclass 37, count 0 2006.239.07:44:11.57#ibcon#about to write, iclass 37, count 0 2006.239.07:44:11.57#ibcon#wrote, iclass 37, count 0 2006.239.07:44:11.57#ibcon#about to read 3, iclass 37, count 0 2006.239.07:44:11.60#ibcon#read 3, iclass 37, count 0 2006.239.07:44:11.60#ibcon#about to read 4, iclass 37, count 0 2006.239.07:44:11.60#ibcon#read 4, iclass 37, count 0 2006.239.07:44:11.60#ibcon#about to read 5, iclass 37, count 0 2006.239.07:44:11.60#ibcon#read 5, iclass 37, count 0 2006.239.07:44:11.60#ibcon#about to read 6, iclass 37, count 0 2006.239.07:44:11.60#ibcon#read 6, iclass 37, count 0 2006.239.07:44:11.60#ibcon#end of sib2, iclass 37, count 0 2006.239.07:44:11.60#ibcon#*after write, iclass 37, count 0 2006.239.07:44:11.60#ibcon#*before return 0, iclass 37, count 0 2006.239.07:44:11.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:11.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:44:11.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:44:11.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:44:11.60$vc4f8/vblo=6,752.99 2006.239.07:44:11.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.07:44:11.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.07:44:11.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:44:11.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:11.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:11.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:11.60#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:44:11.60#ibcon#first serial, iclass 39, count 0 2006.239.07:44:11.60#ibcon#enter sib2, iclass 39, count 0 2006.239.07:44:11.60#ibcon#flushed, iclass 39, count 0 2006.239.07:44:11.60#ibcon#about to write, iclass 39, count 0 2006.239.07:44:11.60#ibcon#wrote, iclass 39, count 0 2006.239.07:44:11.60#ibcon#about to read 3, iclass 39, count 0 2006.239.07:44:11.62#ibcon#read 3, iclass 39, count 0 2006.239.07:44:11.62#ibcon#about to read 4, iclass 39, count 0 2006.239.07:44:11.62#ibcon#read 4, iclass 39, count 0 2006.239.07:44:11.62#ibcon#about to read 5, iclass 39, count 0 2006.239.07:44:11.62#ibcon#read 5, iclass 39, count 0 2006.239.07:44:11.62#ibcon#about to read 6, iclass 39, count 0 2006.239.07:44:11.62#ibcon#read 6, iclass 39, count 0 2006.239.07:44:11.62#ibcon#end of sib2, iclass 39, count 0 2006.239.07:44:11.62#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:44:11.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:44:11.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:44:11.62#ibcon#*before write, iclass 39, count 0 2006.239.07:44:11.62#ibcon#enter sib2, iclass 39, count 0 2006.239.07:44:11.62#ibcon#flushed, iclass 39, count 0 2006.239.07:44:11.62#ibcon#about to write, iclass 39, count 0 2006.239.07:44:11.62#ibcon#wrote, iclass 39, count 0 2006.239.07:44:11.62#ibcon#about to read 3, iclass 39, count 0 2006.239.07:44:11.66#ibcon#read 3, iclass 39, count 0 2006.239.07:44:11.66#ibcon#about to read 4, iclass 39, count 0 2006.239.07:44:11.66#ibcon#read 4, iclass 39, count 0 2006.239.07:44:11.66#ibcon#about to read 5, iclass 39, count 0 2006.239.07:44:11.66#ibcon#read 5, iclass 39, count 0 2006.239.07:44:11.66#ibcon#about to read 6, iclass 39, count 0 2006.239.07:44:11.66#ibcon#read 6, iclass 39, count 0 2006.239.07:44:11.66#ibcon#end of sib2, iclass 39, count 0 2006.239.07:44:11.66#ibcon#*after write, iclass 39, count 0 2006.239.07:44:11.66#ibcon#*before return 0, iclass 39, count 0 2006.239.07:44:11.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:11.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:44:11.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:44:11.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:44:11.66$vc4f8/vb=6,4 2006.239.07:44:11.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.07:44:11.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.07:44:11.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:44:11.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:11.72#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:11.72#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:11.72#ibcon#enter wrdev, iclass 3, count 2 2006.239.07:44:11.72#ibcon#first serial, iclass 3, count 2 2006.239.07:44:11.72#ibcon#enter sib2, iclass 3, count 2 2006.239.07:44:11.72#ibcon#flushed, iclass 3, count 2 2006.239.07:44:11.72#ibcon#about to write, iclass 3, count 2 2006.239.07:44:11.72#ibcon#wrote, iclass 3, count 2 2006.239.07:44:11.72#ibcon#about to read 3, iclass 3, count 2 2006.239.07:44:11.75#ibcon#read 3, iclass 3, count 2 2006.239.07:44:11.75#ibcon#about to read 4, iclass 3, count 2 2006.239.07:44:11.75#ibcon#read 4, iclass 3, count 2 2006.239.07:44:11.75#ibcon#about to read 5, iclass 3, count 2 2006.239.07:44:11.75#ibcon#read 5, iclass 3, count 2 2006.239.07:44:11.75#ibcon#about to read 6, iclass 3, count 2 2006.239.07:44:11.75#ibcon#read 6, iclass 3, count 2 2006.239.07:44:11.75#ibcon#end of sib2, iclass 3, count 2 2006.239.07:44:11.75#ibcon#*mode == 0, iclass 3, count 2 2006.239.07:44:11.75#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.07:44:11.75#ibcon#[27=AT06-04\r\n] 2006.239.07:44:11.75#ibcon#*before write, iclass 3, count 2 2006.239.07:44:11.75#ibcon#enter sib2, iclass 3, count 2 2006.239.07:44:11.75#ibcon#flushed, iclass 3, count 2 2006.239.07:44:11.75#ibcon#about to write, iclass 3, count 2 2006.239.07:44:11.75#ibcon#wrote, iclass 3, count 2 2006.239.07:44:11.75#ibcon#about to read 3, iclass 3, count 2 2006.239.07:44:11.78#ibcon#read 3, iclass 3, count 2 2006.239.07:44:11.78#ibcon#about to read 4, iclass 3, count 2 2006.239.07:44:11.78#ibcon#read 4, iclass 3, count 2 2006.239.07:44:11.78#ibcon#about to read 5, iclass 3, count 2 2006.239.07:44:11.78#ibcon#read 5, iclass 3, count 2 2006.239.07:44:11.78#ibcon#about to read 6, iclass 3, count 2 2006.239.07:44:11.78#ibcon#read 6, iclass 3, count 2 2006.239.07:44:11.78#ibcon#end of sib2, iclass 3, count 2 2006.239.07:44:11.78#ibcon#*after write, iclass 3, count 2 2006.239.07:44:11.78#ibcon#*before return 0, iclass 3, count 2 2006.239.07:44:11.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:11.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:44:11.78#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.07:44:11.78#ibcon#ireg 7 cls_cnt 0 2006.239.07:44:11.78#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:11.90#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:11.90#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:11.90#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:44:11.90#ibcon#first serial, iclass 3, count 0 2006.239.07:44:11.90#ibcon#enter sib2, iclass 3, count 0 2006.239.07:44:11.90#ibcon#flushed, iclass 3, count 0 2006.239.07:44:11.90#ibcon#about to write, iclass 3, count 0 2006.239.07:44:11.90#ibcon#wrote, iclass 3, count 0 2006.239.07:44:11.90#ibcon#about to read 3, iclass 3, count 0 2006.239.07:44:11.92#ibcon#read 3, iclass 3, count 0 2006.239.07:44:11.92#ibcon#about to read 4, iclass 3, count 0 2006.239.07:44:11.92#ibcon#read 4, iclass 3, count 0 2006.239.07:44:11.92#ibcon#about to read 5, iclass 3, count 0 2006.239.07:44:11.92#ibcon#read 5, iclass 3, count 0 2006.239.07:44:11.92#ibcon#about to read 6, iclass 3, count 0 2006.239.07:44:11.92#ibcon#read 6, iclass 3, count 0 2006.239.07:44:11.92#ibcon#end of sib2, iclass 3, count 0 2006.239.07:44:11.92#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:44:11.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:44:11.92#ibcon#[27=USB\r\n] 2006.239.07:44:11.92#ibcon#*before write, iclass 3, count 0 2006.239.07:44:11.92#ibcon#enter sib2, iclass 3, count 0 2006.239.07:44:11.92#ibcon#flushed, iclass 3, count 0 2006.239.07:44:11.92#ibcon#about to write, iclass 3, count 0 2006.239.07:44:11.92#ibcon#wrote, iclass 3, count 0 2006.239.07:44:11.92#ibcon#about to read 3, iclass 3, count 0 2006.239.07:44:11.95#ibcon#read 3, iclass 3, count 0 2006.239.07:44:11.95#ibcon#about to read 4, iclass 3, count 0 2006.239.07:44:11.95#ibcon#read 4, iclass 3, count 0 2006.239.07:44:11.95#ibcon#about to read 5, iclass 3, count 0 2006.239.07:44:11.95#ibcon#read 5, iclass 3, count 0 2006.239.07:44:11.95#ibcon#about to read 6, iclass 3, count 0 2006.239.07:44:11.95#ibcon#read 6, iclass 3, count 0 2006.239.07:44:11.95#ibcon#end of sib2, iclass 3, count 0 2006.239.07:44:11.95#ibcon#*after write, iclass 3, count 0 2006.239.07:44:11.95#ibcon#*before return 0, iclass 3, count 0 2006.239.07:44:11.95#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:11.95#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:44:11.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:44:11.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:44:11.95$vc4f8/vabw=wide 2006.239.07:44:11.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:44:11.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:44:11.95#ibcon#ireg 8 cls_cnt 0 2006.239.07:44:11.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:11.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:11.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:11.95#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:44:11.95#ibcon#first serial, iclass 5, count 0 2006.239.07:44:11.95#ibcon#enter sib2, iclass 5, count 0 2006.239.07:44:11.95#ibcon#flushed, iclass 5, count 0 2006.239.07:44:11.95#ibcon#about to write, iclass 5, count 0 2006.239.07:44:11.95#ibcon#wrote, iclass 5, count 0 2006.239.07:44:11.95#ibcon#about to read 3, iclass 5, count 0 2006.239.07:44:11.97#ibcon#read 3, iclass 5, count 0 2006.239.07:44:11.97#ibcon#about to read 4, iclass 5, count 0 2006.239.07:44:11.97#ibcon#read 4, iclass 5, count 0 2006.239.07:44:11.97#ibcon#about to read 5, iclass 5, count 0 2006.239.07:44:11.97#ibcon#read 5, iclass 5, count 0 2006.239.07:44:11.97#ibcon#about to read 6, iclass 5, count 0 2006.239.07:44:11.97#ibcon#read 6, iclass 5, count 0 2006.239.07:44:11.97#ibcon#end of sib2, iclass 5, count 0 2006.239.07:44:11.97#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:44:11.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:44:11.97#ibcon#[25=BW32\r\n] 2006.239.07:44:11.97#ibcon#*before write, iclass 5, count 0 2006.239.07:44:11.97#ibcon#enter sib2, iclass 5, count 0 2006.239.07:44:11.97#ibcon#flushed, iclass 5, count 0 2006.239.07:44:11.97#ibcon#about to write, iclass 5, count 0 2006.239.07:44:11.97#ibcon#wrote, iclass 5, count 0 2006.239.07:44:11.97#ibcon#about to read 3, iclass 5, count 0 2006.239.07:44:12.00#ibcon#read 3, iclass 5, count 0 2006.239.07:44:12.00#ibcon#about to read 4, iclass 5, count 0 2006.239.07:44:12.00#ibcon#read 4, iclass 5, count 0 2006.239.07:44:12.00#ibcon#about to read 5, iclass 5, count 0 2006.239.07:44:12.00#ibcon#read 5, iclass 5, count 0 2006.239.07:44:12.00#ibcon#about to read 6, iclass 5, count 0 2006.239.07:44:12.00#ibcon#read 6, iclass 5, count 0 2006.239.07:44:12.00#ibcon#end of sib2, iclass 5, count 0 2006.239.07:44:12.00#ibcon#*after write, iclass 5, count 0 2006.239.07:44:12.00#ibcon#*before return 0, iclass 5, count 0 2006.239.07:44:12.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:12.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:44:12.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:44:12.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:44:12.00$vc4f8/vbbw=wide 2006.239.07:44:12.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:44:12.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:44:12.00#ibcon#ireg 8 cls_cnt 0 2006.239.07:44:12.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:44:12.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:44:12.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:44:12.07#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:44:12.07#ibcon#first serial, iclass 7, count 0 2006.239.07:44:12.07#ibcon#enter sib2, iclass 7, count 0 2006.239.07:44:12.07#ibcon#flushed, iclass 7, count 0 2006.239.07:44:12.07#ibcon#about to write, iclass 7, count 0 2006.239.07:44:12.07#ibcon#wrote, iclass 7, count 0 2006.239.07:44:12.07#ibcon#about to read 3, iclass 7, count 0 2006.239.07:44:12.09#ibcon#read 3, iclass 7, count 0 2006.239.07:44:12.09#ibcon#about to read 4, iclass 7, count 0 2006.239.07:44:12.09#ibcon#read 4, iclass 7, count 0 2006.239.07:44:12.09#ibcon#about to read 5, iclass 7, count 0 2006.239.07:44:12.09#ibcon#read 5, iclass 7, count 0 2006.239.07:44:12.09#ibcon#about to read 6, iclass 7, count 0 2006.239.07:44:12.09#ibcon#read 6, iclass 7, count 0 2006.239.07:44:12.09#ibcon#end of sib2, iclass 7, count 0 2006.239.07:44:12.09#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:44:12.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:44:12.09#ibcon#[27=BW32\r\n] 2006.239.07:44:12.09#ibcon#*before write, iclass 7, count 0 2006.239.07:44:12.09#ibcon#enter sib2, iclass 7, count 0 2006.239.07:44:12.09#ibcon#flushed, iclass 7, count 0 2006.239.07:44:12.09#ibcon#about to write, iclass 7, count 0 2006.239.07:44:12.09#ibcon#wrote, iclass 7, count 0 2006.239.07:44:12.09#ibcon#about to read 3, iclass 7, count 0 2006.239.07:44:12.12#ibcon#read 3, iclass 7, count 0 2006.239.07:44:12.12#ibcon#about to read 4, iclass 7, count 0 2006.239.07:44:12.12#ibcon#read 4, iclass 7, count 0 2006.239.07:44:12.12#ibcon#about to read 5, iclass 7, count 0 2006.239.07:44:12.12#ibcon#read 5, iclass 7, count 0 2006.239.07:44:12.12#ibcon#about to read 6, iclass 7, count 0 2006.239.07:44:12.12#ibcon#read 6, iclass 7, count 0 2006.239.07:44:12.12#ibcon#end of sib2, iclass 7, count 0 2006.239.07:44:12.12#ibcon#*after write, iclass 7, count 0 2006.239.07:44:12.12#ibcon#*before return 0, iclass 7, count 0 2006.239.07:44:12.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:44:12.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:44:12.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:44:12.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:44:12.12$4f8m12a/ifd4f 2006.239.07:44:12.12$ifd4f/lo= 2006.239.07:44:12.12$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:44:12.12$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:44:12.12$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:44:12.12$ifd4f/patch= 2006.239.07:44:12.12$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:44:12.12$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:44:12.12$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:44:12.12$4f8m12a/"form=m,16.000,1:2 2006.239.07:44:12.12$4f8m12a/"tpicd 2006.239.07:44:12.12$4f8m12a/echo=off 2006.239.07:44:12.12$4f8m12a/xlog=off 2006.239.07:44:12.12:!2006.239.07:44:40 2006.239.07:44:26.14#trakl#Source acquired 2006.239.07:44:27.14#flagr#flagr/antenna,acquired 2006.239.07:44:40.00:preob 2006.239.07:44:40.14/onsource/TRACKING 2006.239.07:44:40.14:!2006.239.07:44:50 2006.239.07:44:50.00:data_valid=on 2006.239.07:44:50.00:midob 2006.239.07:44:51.14/onsource/TRACKING 2006.239.07:44:51.14/wx/25.31,1011.5,80 2006.239.07:44:51.21/cable/+6.4154E-03 2006.239.07:44:52.30/va/01,08,usb,yes,31,32 2006.239.07:44:52.30/va/02,07,usb,yes,31,32 2006.239.07:44:52.30/va/03,07,usb,yes,29,29 2006.239.07:44:52.30/va/04,07,usb,yes,32,35 2006.239.07:44:52.30/va/05,08,usb,yes,29,31 2006.239.07:44:52.30/va/06,07,usb,yes,32,31 2006.239.07:44:52.30/va/07,07,usb,yes,31,31 2006.239.07:44:52.30/va/08,07,usb,yes,34,34 2006.239.07:44:52.53/valo/01,532.99,yes,locked 2006.239.07:44:52.53/valo/02,572.99,yes,locked 2006.239.07:44:52.53/valo/03,672.99,yes,locked 2006.239.07:44:52.53/valo/04,832.99,yes,locked 2006.239.07:44:52.53/valo/05,652.99,yes,locked 2006.239.07:44:52.53/valo/06,772.99,yes,locked 2006.239.07:44:52.53/valo/07,832.99,yes,locked 2006.239.07:44:52.53/valo/08,852.99,yes,locked 2006.239.07:44:53.62/vb/01,04,usb,yes,30,29 2006.239.07:44:53.62/vb/02,04,usb,yes,32,33 2006.239.07:44:53.62/vb/03,04,usb,yes,28,32 2006.239.07:44:53.62/vb/04,04,usb,yes,29,29 2006.239.07:44:53.62/vb/05,04,usb,yes,28,32 2006.239.07:44:53.62/vb/06,04,usb,yes,28,31 2006.239.07:44:53.62/vb/07,04,usb,yes,31,31 2006.239.07:44:53.62/vb/08,04,usb,yes,28,32 2006.239.07:44:53.86/vblo/01,632.99,yes,locked 2006.239.07:44:53.86/vblo/02,640.99,yes,locked 2006.239.07:44:53.86/vblo/03,656.99,yes,locked 2006.239.07:44:53.86/vblo/04,712.99,yes,locked 2006.239.07:44:53.86/vblo/05,744.99,yes,locked 2006.239.07:44:53.86/vblo/06,752.99,yes,locked 2006.239.07:44:53.86/vblo/07,734.99,yes,locked 2006.239.07:44:53.86/vblo/08,744.99,yes,locked 2006.239.07:44:54.01/vabw/8 2006.239.07:44:54.16/vbbw/8 2006.239.07:44:54.25/xfe/off,on,14.0 2006.239.07:44:54.62/ifatt/23,28,28,28 2006.239.07:44:55.07/fmout-gps/S +4.38E-07 2006.239.07:44:55.11:!2006.239.07:45:50 2006.239.07:45:50.00:data_valid=off 2006.239.07:45:50.00:postob 2006.239.07:45:50.19/cable/+6.4147E-03 2006.239.07:45:50.19/wx/25.30,1011.5,80 2006.239.07:45:51.07/fmout-gps/S +4.38E-07 2006.239.07:45:51.07:scan_name=239-0746,k06239,60 2006.239.07:45:51.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.239.07:45:51.14#flagr#flagr/antenna,new-source 2006.239.07:45:52.14:checkk5 2006.239.07:45:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:45:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:45:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:45:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:45:54.04/chk_obsdata//k5ts1/T2390744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:45:54.41/chk_obsdata//k5ts2/T2390744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:45:54.78/chk_obsdata//k5ts3/T2390744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:45:55.16/chk_obsdata//k5ts4/T2390744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:45:55.86/k5log//k5ts1_log_newline 2006.239.07:45:56.58/k5log//k5ts2_log_newline 2006.239.07:45:57.29/k5log//k5ts3_log_newline 2006.239.07:45:57.98/k5log//k5ts4_log_newline 2006.239.07:45:58.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:45:58.01:4f8m12a=1 2006.239.07:45:58.01$4f8m12a/echo=on 2006.239.07:45:58.01$4f8m12a/pcalon 2006.239.07:45:58.01$pcalon/"no phase cal control is implemented here 2006.239.07:45:58.01$4f8m12a/"tpicd=stop 2006.239.07:45:58.01$4f8m12a/vc4f8 2006.239.07:45:58.01$vc4f8/valo=1,532.99 2006.239.07:45:58.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:45:58.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:45:58.01#ibcon#ireg 17 cls_cnt 0 2006.239.07:45:58.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:45:58.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:45:58.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:45:58.01#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:45:58.01#ibcon#first serial, iclass 16, count 0 2006.239.07:45:58.01#ibcon#enter sib2, iclass 16, count 0 2006.239.07:45:58.01#ibcon#flushed, iclass 16, count 0 2006.239.07:45:58.01#ibcon#about to write, iclass 16, count 0 2006.239.07:45:58.01#ibcon#wrote, iclass 16, count 0 2006.239.07:45:58.01#ibcon#about to read 3, iclass 16, count 0 2006.239.07:45:58.02#ibcon#read 3, iclass 16, count 0 2006.239.07:45:58.02#ibcon#about to read 4, iclass 16, count 0 2006.239.07:45:58.02#ibcon#read 4, iclass 16, count 0 2006.239.07:45:58.02#ibcon#about to read 5, iclass 16, count 0 2006.239.07:45:58.02#ibcon#read 5, iclass 16, count 0 2006.239.07:45:58.02#ibcon#about to read 6, iclass 16, count 0 2006.239.07:45:58.02#ibcon#read 6, iclass 16, count 0 2006.239.07:45:58.02#ibcon#end of sib2, iclass 16, count 0 2006.239.07:45:58.02#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:45:58.02#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:45:58.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:45:58.02#ibcon#*before write, iclass 16, count 0 2006.239.07:45:58.02#ibcon#enter sib2, iclass 16, count 0 2006.239.07:45:58.02#ibcon#flushed, iclass 16, count 0 2006.239.07:45:58.02#ibcon#about to write, iclass 16, count 0 2006.239.07:45:58.02#ibcon#wrote, iclass 16, count 0 2006.239.07:45:58.02#ibcon#about to read 3, iclass 16, count 0 2006.239.07:45:58.07#ibcon#read 3, iclass 16, count 0 2006.239.07:45:58.07#ibcon#about to read 4, iclass 16, count 0 2006.239.07:45:58.07#ibcon#read 4, iclass 16, count 0 2006.239.07:45:58.07#ibcon#about to read 5, iclass 16, count 0 2006.239.07:45:58.07#ibcon#read 5, iclass 16, count 0 2006.239.07:45:58.07#ibcon#about to read 6, iclass 16, count 0 2006.239.07:45:58.07#ibcon#read 6, iclass 16, count 0 2006.239.07:45:58.07#ibcon#end of sib2, iclass 16, count 0 2006.239.07:45:58.07#ibcon#*after write, iclass 16, count 0 2006.239.07:45:58.07#ibcon#*before return 0, iclass 16, count 0 2006.239.07:45:58.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:45:58.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:45:58.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:45:58.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:45:58.07$vc4f8/va=1,8 2006.239.07:45:58.07#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:45:58.07#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:45:58.07#ibcon#ireg 11 cls_cnt 2 2006.239.07:45:58.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:45:58.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:45:58.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:45:58.07#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:45:58.07#ibcon#first serial, iclass 18, count 2 2006.239.07:45:58.07#ibcon#enter sib2, iclass 18, count 2 2006.239.07:45:58.07#ibcon#flushed, iclass 18, count 2 2006.239.07:45:58.07#ibcon#about to write, iclass 18, count 2 2006.239.07:45:58.07#ibcon#wrote, iclass 18, count 2 2006.239.07:45:58.07#ibcon#about to read 3, iclass 18, count 2 2006.239.07:45:58.09#ibcon#read 3, iclass 18, count 2 2006.239.07:45:58.09#ibcon#about to read 4, iclass 18, count 2 2006.239.07:45:58.09#ibcon#read 4, iclass 18, count 2 2006.239.07:45:58.09#ibcon#about to read 5, iclass 18, count 2 2006.239.07:45:58.09#ibcon#read 5, iclass 18, count 2 2006.239.07:45:58.09#ibcon#about to read 6, iclass 18, count 2 2006.239.07:45:58.09#ibcon#read 6, iclass 18, count 2 2006.239.07:45:58.09#ibcon#end of sib2, iclass 18, count 2 2006.239.07:45:58.09#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:45:58.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:45:58.09#ibcon#[25=AT01-08\r\n] 2006.239.07:45:58.09#ibcon#*before write, iclass 18, count 2 2006.239.07:45:58.09#ibcon#enter sib2, iclass 18, count 2 2006.239.07:45:58.09#ibcon#flushed, iclass 18, count 2 2006.239.07:45:58.09#ibcon#about to write, iclass 18, count 2 2006.239.07:45:58.09#ibcon#wrote, iclass 18, count 2 2006.239.07:45:58.09#ibcon#about to read 3, iclass 18, count 2 2006.239.07:45:58.12#ibcon#read 3, iclass 18, count 2 2006.239.07:45:58.12#ibcon#about to read 4, iclass 18, count 2 2006.239.07:45:58.12#ibcon#read 4, iclass 18, count 2 2006.239.07:45:58.12#ibcon#about to read 5, iclass 18, count 2 2006.239.07:45:58.12#ibcon#read 5, iclass 18, count 2 2006.239.07:45:58.12#ibcon#about to read 6, iclass 18, count 2 2006.239.07:45:58.12#ibcon#read 6, iclass 18, count 2 2006.239.07:45:58.12#ibcon#end of sib2, iclass 18, count 2 2006.239.07:45:58.12#ibcon#*after write, iclass 18, count 2 2006.239.07:45:58.12#ibcon#*before return 0, iclass 18, count 2 2006.239.07:45:58.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:45:58.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:45:58.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:45:58.12#ibcon#ireg 7 cls_cnt 0 2006.239.07:45:58.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:45:58.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:45:58.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:45:58.25#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:45:58.25#ibcon#first serial, iclass 18, count 0 2006.239.07:45:58.25#ibcon#enter sib2, iclass 18, count 0 2006.239.07:45:58.25#ibcon#flushed, iclass 18, count 0 2006.239.07:45:58.25#ibcon#about to write, iclass 18, count 0 2006.239.07:45:58.25#ibcon#wrote, iclass 18, count 0 2006.239.07:45:58.25#ibcon#about to read 3, iclass 18, count 0 2006.239.07:45:58.27#ibcon#read 3, iclass 18, count 0 2006.239.07:45:58.27#ibcon#about to read 4, iclass 18, count 0 2006.239.07:45:58.27#ibcon#read 4, iclass 18, count 0 2006.239.07:45:58.27#ibcon#about to read 5, iclass 18, count 0 2006.239.07:45:58.27#ibcon#read 5, iclass 18, count 0 2006.239.07:45:58.27#ibcon#about to read 6, iclass 18, count 0 2006.239.07:45:58.27#ibcon#read 6, iclass 18, count 0 2006.239.07:45:58.27#ibcon#end of sib2, iclass 18, count 0 2006.239.07:45:58.27#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:45:58.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:45:58.27#ibcon#[25=USB\r\n] 2006.239.07:45:58.27#ibcon#*before write, iclass 18, count 0 2006.239.07:45:58.27#ibcon#enter sib2, iclass 18, count 0 2006.239.07:45:58.27#ibcon#flushed, iclass 18, count 0 2006.239.07:45:58.27#ibcon#about to write, iclass 18, count 0 2006.239.07:45:58.27#ibcon#wrote, iclass 18, count 0 2006.239.07:45:58.27#ibcon#about to read 3, iclass 18, count 0 2006.239.07:45:58.30#ibcon#read 3, iclass 18, count 0 2006.239.07:45:58.30#ibcon#about to read 4, iclass 18, count 0 2006.239.07:45:58.30#ibcon#read 4, iclass 18, count 0 2006.239.07:45:58.30#ibcon#about to read 5, iclass 18, count 0 2006.239.07:45:58.30#ibcon#read 5, iclass 18, count 0 2006.239.07:45:58.30#ibcon#about to read 6, iclass 18, count 0 2006.239.07:45:58.30#ibcon#read 6, iclass 18, count 0 2006.239.07:45:58.30#ibcon#end of sib2, iclass 18, count 0 2006.239.07:45:58.30#ibcon#*after write, iclass 18, count 0 2006.239.07:45:58.30#ibcon#*before return 0, iclass 18, count 0 2006.239.07:45:58.30#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:45:58.30#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:45:58.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:45:58.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:45:58.30$vc4f8/valo=2,572.99 2006.239.07:45:58.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:45:58.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:45:58.30#ibcon#ireg 17 cls_cnt 0 2006.239.07:45:58.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:45:58.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:45:58.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:45:58.30#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:45:58.30#ibcon#first serial, iclass 20, count 0 2006.239.07:45:58.30#ibcon#enter sib2, iclass 20, count 0 2006.239.07:45:58.30#ibcon#flushed, iclass 20, count 0 2006.239.07:45:58.30#ibcon#about to write, iclass 20, count 0 2006.239.07:45:58.30#ibcon#wrote, iclass 20, count 0 2006.239.07:45:58.30#ibcon#about to read 3, iclass 20, count 0 2006.239.07:45:58.32#ibcon#read 3, iclass 20, count 0 2006.239.07:45:58.32#ibcon#about to read 4, iclass 20, count 0 2006.239.07:45:58.32#ibcon#read 4, iclass 20, count 0 2006.239.07:45:58.32#ibcon#about to read 5, iclass 20, count 0 2006.239.07:45:58.32#ibcon#read 5, iclass 20, count 0 2006.239.07:45:58.32#ibcon#about to read 6, iclass 20, count 0 2006.239.07:45:58.32#ibcon#read 6, iclass 20, count 0 2006.239.07:45:58.32#ibcon#end of sib2, iclass 20, count 0 2006.239.07:45:58.32#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:45:58.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:45:58.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:45:58.32#ibcon#*before write, iclass 20, count 0 2006.239.07:45:58.32#ibcon#enter sib2, iclass 20, count 0 2006.239.07:45:58.32#ibcon#flushed, iclass 20, count 0 2006.239.07:45:58.32#ibcon#about to write, iclass 20, count 0 2006.239.07:45:58.32#ibcon#wrote, iclass 20, count 0 2006.239.07:45:58.32#ibcon#about to read 3, iclass 20, count 0 2006.239.07:45:58.36#ibcon#read 3, iclass 20, count 0 2006.239.07:45:58.36#ibcon#about to read 4, iclass 20, count 0 2006.239.07:45:58.36#ibcon#read 4, iclass 20, count 0 2006.239.07:45:58.36#ibcon#about to read 5, iclass 20, count 0 2006.239.07:45:58.36#ibcon#read 5, iclass 20, count 0 2006.239.07:45:58.36#ibcon#about to read 6, iclass 20, count 0 2006.239.07:45:58.36#ibcon#read 6, iclass 20, count 0 2006.239.07:45:58.36#ibcon#end of sib2, iclass 20, count 0 2006.239.07:45:58.36#ibcon#*after write, iclass 20, count 0 2006.239.07:45:58.36#ibcon#*before return 0, iclass 20, count 0 2006.239.07:45:58.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:45:58.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:45:58.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:45:58.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:45:58.36$vc4f8/va=2,7 2006.239.07:45:58.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:45:58.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:45:58.36#ibcon#ireg 11 cls_cnt 2 2006.239.07:45:58.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:45:58.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:45:58.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:45:58.42#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:45:58.42#ibcon#first serial, iclass 22, count 2 2006.239.07:45:58.42#ibcon#enter sib2, iclass 22, count 2 2006.239.07:45:58.42#ibcon#flushed, iclass 22, count 2 2006.239.07:45:58.42#ibcon#about to write, iclass 22, count 2 2006.239.07:45:58.42#ibcon#wrote, iclass 22, count 2 2006.239.07:45:58.42#ibcon#about to read 3, iclass 22, count 2 2006.239.07:45:58.46#ibcon#read 3, iclass 22, count 2 2006.239.07:45:58.46#ibcon#about to read 4, iclass 22, count 2 2006.239.07:45:58.46#ibcon#read 4, iclass 22, count 2 2006.239.07:45:58.46#ibcon#about to read 5, iclass 22, count 2 2006.239.07:45:58.46#ibcon#read 5, iclass 22, count 2 2006.239.07:45:58.46#ibcon#about to read 6, iclass 22, count 2 2006.239.07:45:58.46#ibcon#read 6, iclass 22, count 2 2006.239.07:45:58.46#ibcon#end of sib2, iclass 22, count 2 2006.239.07:45:58.46#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:45:58.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:45:58.46#ibcon#[25=AT02-07\r\n] 2006.239.07:45:58.46#ibcon#*before write, iclass 22, count 2 2006.239.07:45:58.46#ibcon#enter sib2, iclass 22, count 2 2006.239.07:45:58.46#ibcon#flushed, iclass 22, count 2 2006.239.07:45:58.46#ibcon#about to write, iclass 22, count 2 2006.239.07:45:58.46#ibcon#wrote, iclass 22, count 2 2006.239.07:45:58.46#ibcon#about to read 3, iclass 22, count 2 2006.239.07:45:58.49#ibcon#read 3, iclass 22, count 2 2006.239.07:45:58.49#ibcon#about to read 4, iclass 22, count 2 2006.239.07:45:58.49#ibcon#read 4, iclass 22, count 2 2006.239.07:45:58.49#ibcon#about to read 5, iclass 22, count 2 2006.239.07:45:58.49#ibcon#read 5, iclass 22, count 2 2006.239.07:45:58.49#ibcon#about to read 6, iclass 22, count 2 2006.239.07:45:58.49#ibcon#read 6, iclass 22, count 2 2006.239.07:45:58.49#ibcon#end of sib2, iclass 22, count 2 2006.239.07:45:58.49#ibcon#*after write, iclass 22, count 2 2006.239.07:45:58.49#ibcon#*before return 0, iclass 22, count 2 2006.239.07:45:58.49#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:45:58.49#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:45:58.49#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:45:58.49#ibcon#ireg 7 cls_cnt 0 2006.239.07:45:58.49#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:45:58.61#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:45:58.61#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:45:58.61#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:45:58.61#ibcon#first serial, iclass 22, count 0 2006.239.07:45:58.61#ibcon#enter sib2, iclass 22, count 0 2006.239.07:45:58.61#ibcon#flushed, iclass 22, count 0 2006.239.07:45:58.61#ibcon#about to write, iclass 22, count 0 2006.239.07:45:58.61#ibcon#wrote, iclass 22, count 0 2006.239.07:45:58.61#ibcon#about to read 3, iclass 22, count 0 2006.239.07:45:58.63#ibcon#read 3, iclass 22, count 0 2006.239.07:45:58.63#ibcon#about to read 4, iclass 22, count 0 2006.239.07:45:58.63#ibcon#read 4, iclass 22, count 0 2006.239.07:45:58.63#ibcon#about to read 5, iclass 22, count 0 2006.239.07:45:58.63#ibcon#read 5, iclass 22, count 0 2006.239.07:45:58.63#ibcon#about to read 6, iclass 22, count 0 2006.239.07:45:58.63#ibcon#read 6, iclass 22, count 0 2006.239.07:45:58.63#ibcon#end of sib2, iclass 22, count 0 2006.239.07:45:58.63#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:45:58.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:45:58.63#ibcon#[25=USB\r\n] 2006.239.07:45:58.63#ibcon#*before write, iclass 22, count 0 2006.239.07:45:58.63#ibcon#enter sib2, iclass 22, count 0 2006.239.07:45:58.63#ibcon#flushed, iclass 22, count 0 2006.239.07:45:58.63#ibcon#about to write, iclass 22, count 0 2006.239.07:45:58.63#ibcon#wrote, iclass 22, count 0 2006.239.07:45:58.63#ibcon#about to read 3, iclass 22, count 0 2006.239.07:45:58.66#ibcon#read 3, iclass 22, count 0 2006.239.07:45:58.66#ibcon#about to read 4, iclass 22, count 0 2006.239.07:45:58.66#ibcon#read 4, iclass 22, count 0 2006.239.07:45:58.66#ibcon#about to read 5, iclass 22, count 0 2006.239.07:45:58.66#ibcon#read 5, iclass 22, count 0 2006.239.07:45:58.66#ibcon#about to read 6, iclass 22, count 0 2006.239.07:45:58.66#ibcon#read 6, iclass 22, count 0 2006.239.07:45:58.66#ibcon#end of sib2, iclass 22, count 0 2006.239.07:45:58.66#ibcon#*after write, iclass 22, count 0 2006.239.07:45:58.66#ibcon#*before return 0, iclass 22, count 0 2006.239.07:45:58.66#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:45:58.66#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:45:58.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:45:58.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:45:58.66$vc4f8/valo=3,672.99 2006.239.07:45:58.66#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:45:58.66#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:45:58.66#ibcon#ireg 17 cls_cnt 0 2006.239.07:45:58.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:45:58.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:45:58.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:45:58.66#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:45:58.66#ibcon#first serial, iclass 24, count 0 2006.239.07:45:58.66#ibcon#enter sib2, iclass 24, count 0 2006.239.07:45:58.66#ibcon#flushed, iclass 24, count 0 2006.239.07:45:58.66#ibcon#about to write, iclass 24, count 0 2006.239.07:45:58.66#ibcon#wrote, iclass 24, count 0 2006.239.07:45:58.66#ibcon#about to read 3, iclass 24, count 0 2006.239.07:45:58.68#ibcon#read 3, iclass 24, count 0 2006.239.07:45:58.68#ibcon#about to read 4, iclass 24, count 0 2006.239.07:45:58.68#ibcon#read 4, iclass 24, count 0 2006.239.07:45:58.68#ibcon#about to read 5, iclass 24, count 0 2006.239.07:45:58.68#ibcon#read 5, iclass 24, count 0 2006.239.07:45:58.68#ibcon#about to read 6, iclass 24, count 0 2006.239.07:45:58.68#ibcon#read 6, iclass 24, count 0 2006.239.07:45:58.68#ibcon#end of sib2, iclass 24, count 0 2006.239.07:45:58.68#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:45:58.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:45:58.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:45:58.68#ibcon#*before write, iclass 24, count 0 2006.239.07:45:58.68#ibcon#enter sib2, iclass 24, count 0 2006.239.07:45:58.68#ibcon#flushed, iclass 24, count 0 2006.239.07:45:58.68#ibcon#about to write, iclass 24, count 0 2006.239.07:45:58.68#ibcon#wrote, iclass 24, count 0 2006.239.07:45:58.68#ibcon#about to read 3, iclass 24, count 0 2006.239.07:45:58.72#ibcon#read 3, iclass 24, count 0 2006.239.07:45:58.72#ibcon#about to read 4, iclass 24, count 0 2006.239.07:45:58.72#ibcon#read 4, iclass 24, count 0 2006.239.07:45:58.72#ibcon#about to read 5, iclass 24, count 0 2006.239.07:45:58.72#ibcon#read 5, iclass 24, count 0 2006.239.07:45:58.72#ibcon#about to read 6, iclass 24, count 0 2006.239.07:45:58.72#ibcon#read 6, iclass 24, count 0 2006.239.07:45:58.72#ibcon#end of sib2, iclass 24, count 0 2006.239.07:45:58.72#ibcon#*after write, iclass 24, count 0 2006.239.07:45:58.72#ibcon#*before return 0, iclass 24, count 0 2006.239.07:45:58.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:45:58.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:45:58.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:45:58.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:45:58.72$vc4f8/va=3,7 2006.239.07:45:58.72#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.07:45:58.72#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.07:45:58.72#ibcon#ireg 11 cls_cnt 2 2006.239.07:45:58.72#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:45:58.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:45:58.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:45:58.78#ibcon#enter wrdev, iclass 26, count 2 2006.239.07:45:58.78#ibcon#first serial, iclass 26, count 2 2006.239.07:45:58.78#ibcon#enter sib2, iclass 26, count 2 2006.239.07:45:58.78#ibcon#flushed, iclass 26, count 2 2006.239.07:45:58.78#ibcon#about to write, iclass 26, count 2 2006.239.07:45:58.78#ibcon#wrote, iclass 26, count 2 2006.239.07:45:58.78#ibcon#about to read 3, iclass 26, count 2 2006.239.07:45:58.81#ibcon#read 3, iclass 26, count 2 2006.239.07:45:58.81#ibcon#about to read 4, iclass 26, count 2 2006.239.07:45:58.81#ibcon#read 4, iclass 26, count 2 2006.239.07:45:58.81#ibcon#about to read 5, iclass 26, count 2 2006.239.07:45:58.81#ibcon#read 5, iclass 26, count 2 2006.239.07:45:58.81#ibcon#about to read 6, iclass 26, count 2 2006.239.07:45:58.81#ibcon#read 6, iclass 26, count 2 2006.239.07:45:58.81#ibcon#end of sib2, iclass 26, count 2 2006.239.07:45:58.81#ibcon#*mode == 0, iclass 26, count 2 2006.239.07:45:58.81#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.07:45:58.81#ibcon#[25=AT03-07\r\n] 2006.239.07:45:58.81#ibcon#*before write, iclass 26, count 2 2006.239.07:45:58.81#ibcon#enter sib2, iclass 26, count 2 2006.239.07:45:58.81#ibcon#flushed, iclass 26, count 2 2006.239.07:45:58.81#ibcon#about to write, iclass 26, count 2 2006.239.07:45:58.81#ibcon#wrote, iclass 26, count 2 2006.239.07:45:58.81#ibcon#about to read 3, iclass 26, count 2 2006.239.07:45:58.84#ibcon#read 3, iclass 26, count 2 2006.239.07:45:58.84#ibcon#about to read 4, iclass 26, count 2 2006.239.07:45:58.84#ibcon#read 4, iclass 26, count 2 2006.239.07:45:58.84#ibcon#about to read 5, iclass 26, count 2 2006.239.07:45:58.84#ibcon#read 5, iclass 26, count 2 2006.239.07:45:58.84#ibcon#about to read 6, iclass 26, count 2 2006.239.07:45:58.84#ibcon#read 6, iclass 26, count 2 2006.239.07:45:58.84#ibcon#end of sib2, iclass 26, count 2 2006.239.07:45:58.84#ibcon#*after write, iclass 26, count 2 2006.239.07:45:58.84#ibcon#*before return 0, iclass 26, count 2 2006.239.07:45:58.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:45:58.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:45:58.84#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.07:45:58.84#ibcon#ireg 7 cls_cnt 0 2006.239.07:45:58.84#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:45:58.96#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:45:58.96#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:45:58.96#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:45:58.96#ibcon#first serial, iclass 26, count 0 2006.239.07:45:58.96#ibcon#enter sib2, iclass 26, count 0 2006.239.07:45:58.96#ibcon#flushed, iclass 26, count 0 2006.239.07:45:58.96#ibcon#about to write, iclass 26, count 0 2006.239.07:45:58.96#ibcon#wrote, iclass 26, count 0 2006.239.07:45:58.96#ibcon#about to read 3, iclass 26, count 0 2006.239.07:45:58.98#ibcon#read 3, iclass 26, count 0 2006.239.07:45:58.98#ibcon#about to read 4, iclass 26, count 0 2006.239.07:45:58.98#ibcon#read 4, iclass 26, count 0 2006.239.07:45:58.98#ibcon#about to read 5, iclass 26, count 0 2006.239.07:45:58.98#ibcon#read 5, iclass 26, count 0 2006.239.07:45:58.98#ibcon#about to read 6, iclass 26, count 0 2006.239.07:45:58.98#ibcon#read 6, iclass 26, count 0 2006.239.07:45:58.98#ibcon#end of sib2, iclass 26, count 0 2006.239.07:45:58.98#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:45:58.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:45:58.98#ibcon#[25=USB\r\n] 2006.239.07:45:58.98#ibcon#*before write, iclass 26, count 0 2006.239.07:45:58.98#ibcon#enter sib2, iclass 26, count 0 2006.239.07:45:58.98#ibcon#flushed, iclass 26, count 0 2006.239.07:45:58.98#ibcon#about to write, iclass 26, count 0 2006.239.07:45:58.98#ibcon#wrote, iclass 26, count 0 2006.239.07:45:58.98#ibcon#about to read 3, iclass 26, count 0 2006.239.07:45:59.01#ibcon#read 3, iclass 26, count 0 2006.239.07:45:59.01#ibcon#about to read 4, iclass 26, count 0 2006.239.07:45:59.01#ibcon#read 4, iclass 26, count 0 2006.239.07:45:59.01#ibcon#about to read 5, iclass 26, count 0 2006.239.07:45:59.01#ibcon#read 5, iclass 26, count 0 2006.239.07:45:59.01#ibcon#about to read 6, iclass 26, count 0 2006.239.07:45:59.01#ibcon#read 6, iclass 26, count 0 2006.239.07:45:59.01#ibcon#end of sib2, iclass 26, count 0 2006.239.07:45:59.01#ibcon#*after write, iclass 26, count 0 2006.239.07:45:59.01#ibcon#*before return 0, iclass 26, count 0 2006.239.07:45:59.01#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:45:59.01#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:45:59.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:45:59.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:45:59.01$vc4f8/valo=4,832.99 2006.239.07:45:59.01#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.07:45:59.01#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.07:45:59.01#ibcon#ireg 17 cls_cnt 0 2006.239.07:45:59.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:45:59.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:45:59.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:45:59.01#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:45:59.01#ibcon#first serial, iclass 28, count 0 2006.239.07:45:59.01#ibcon#enter sib2, iclass 28, count 0 2006.239.07:45:59.01#ibcon#flushed, iclass 28, count 0 2006.239.07:45:59.01#ibcon#about to write, iclass 28, count 0 2006.239.07:45:59.01#ibcon#wrote, iclass 28, count 0 2006.239.07:45:59.01#ibcon#about to read 3, iclass 28, count 0 2006.239.07:45:59.03#ibcon#read 3, iclass 28, count 0 2006.239.07:45:59.03#ibcon#about to read 4, iclass 28, count 0 2006.239.07:45:59.03#ibcon#read 4, iclass 28, count 0 2006.239.07:45:59.03#ibcon#about to read 5, iclass 28, count 0 2006.239.07:45:59.03#ibcon#read 5, iclass 28, count 0 2006.239.07:45:59.03#ibcon#about to read 6, iclass 28, count 0 2006.239.07:45:59.03#ibcon#read 6, iclass 28, count 0 2006.239.07:45:59.03#ibcon#end of sib2, iclass 28, count 0 2006.239.07:45:59.03#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:45:59.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:45:59.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:45:59.03#ibcon#*before write, iclass 28, count 0 2006.239.07:45:59.03#ibcon#enter sib2, iclass 28, count 0 2006.239.07:45:59.03#ibcon#flushed, iclass 28, count 0 2006.239.07:45:59.03#ibcon#about to write, iclass 28, count 0 2006.239.07:45:59.03#ibcon#wrote, iclass 28, count 0 2006.239.07:45:59.03#ibcon#about to read 3, iclass 28, count 0 2006.239.07:45:59.07#ibcon#read 3, iclass 28, count 0 2006.239.07:45:59.07#ibcon#about to read 4, iclass 28, count 0 2006.239.07:45:59.07#ibcon#read 4, iclass 28, count 0 2006.239.07:45:59.07#ibcon#about to read 5, iclass 28, count 0 2006.239.07:45:59.07#ibcon#read 5, iclass 28, count 0 2006.239.07:45:59.07#ibcon#about to read 6, iclass 28, count 0 2006.239.07:45:59.07#ibcon#read 6, iclass 28, count 0 2006.239.07:45:59.07#ibcon#end of sib2, iclass 28, count 0 2006.239.07:45:59.07#ibcon#*after write, iclass 28, count 0 2006.239.07:45:59.07#ibcon#*before return 0, iclass 28, count 0 2006.239.07:45:59.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:45:59.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:45:59.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:45:59.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:45:59.07$vc4f8/va=4,7 2006.239.07:45:59.07#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.07:45:59.07#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.07:45:59.07#ibcon#ireg 11 cls_cnt 2 2006.239.07:45:59.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:45:59.12#abcon#<5=/05 2.0 3.6 25.30 801011.5\r\n> 2006.239.07:45:59.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:45:59.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:45:59.13#ibcon#enter wrdev, iclass 30, count 2 2006.239.07:45:59.13#ibcon#first serial, iclass 30, count 2 2006.239.07:45:59.13#ibcon#enter sib2, iclass 30, count 2 2006.239.07:45:59.13#ibcon#flushed, iclass 30, count 2 2006.239.07:45:59.13#ibcon#about to write, iclass 30, count 2 2006.239.07:45:59.13#ibcon#wrote, iclass 30, count 2 2006.239.07:45:59.13#ibcon#about to read 3, iclass 30, count 2 2006.239.07:45:59.14#abcon#{5=INTERFACE CLEAR} 2006.239.07:45:59.15#ibcon#read 3, iclass 30, count 2 2006.239.07:45:59.15#ibcon#about to read 4, iclass 30, count 2 2006.239.07:45:59.15#ibcon#read 4, iclass 30, count 2 2006.239.07:45:59.15#ibcon#about to read 5, iclass 30, count 2 2006.239.07:45:59.15#ibcon#read 5, iclass 30, count 2 2006.239.07:45:59.15#ibcon#about to read 6, iclass 30, count 2 2006.239.07:45:59.15#ibcon#read 6, iclass 30, count 2 2006.239.07:45:59.15#ibcon#end of sib2, iclass 30, count 2 2006.239.07:45:59.15#ibcon#*mode == 0, iclass 30, count 2 2006.239.07:45:59.15#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.07:45:59.15#ibcon#[25=AT04-07\r\n] 2006.239.07:45:59.15#ibcon#*before write, iclass 30, count 2 2006.239.07:45:59.15#ibcon#enter sib2, iclass 30, count 2 2006.239.07:45:59.15#ibcon#flushed, iclass 30, count 2 2006.239.07:45:59.15#ibcon#about to write, iclass 30, count 2 2006.239.07:45:59.15#ibcon#wrote, iclass 30, count 2 2006.239.07:45:59.15#ibcon#about to read 3, iclass 30, count 2 2006.239.07:45:59.18#ibcon#read 3, iclass 30, count 2 2006.239.07:45:59.18#ibcon#about to read 4, iclass 30, count 2 2006.239.07:45:59.18#ibcon#read 4, iclass 30, count 2 2006.239.07:45:59.18#ibcon#about to read 5, iclass 30, count 2 2006.239.07:45:59.18#ibcon#read 5, iclass 30, count 2 2006.239.07:45:59.18#ibcon#about to read 6, iclass 30, count 2 2006.239.07:45:59.18#ibcon#read 6, iclass 30, count 2 2006.239.07:45:59.18#ibcon#end of sib2, iclass 30, count 2 2006.239.07:45:59.18#ibcon#*after write, iclass 30, count 2 2006.239.07:45:59.18#ibcon#*before return 0, iclass 30, count 2 2006.239.07:45:59.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:45:59.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:45:59.18#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.07:45:59.18#ibcon#ireg 7 cls_cnt 0 2006.239.07:45:59.18#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:45:59.20#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:45:59.30#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:45:59.30#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:45:59.30#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:45:59.30#ibcon#first serial, iclass 30, count 0 2006.239.07:45:59.30#ibcon#enter sib2, iclass 30, count 0 2006.239.07:45:59.30#ibcon#flushed, iclass 30, count 0 2006.239.07:45:59.30#ibcon#about to write, iclass 30, count 0 2006.239.07:45:59.30#ibcon#wrote, iclass 30, count 0 2006.239.07:45:59.30#ibcon#about to read 3, iclass 30, count 0 2006.239.07:45:59.32#ibcon#read 3, iclass 30, count 0 2006.239.07:45:59.32#ibcon#about to read 4, iclass 30, count 0 2006.239.07:45:59.32#ibcon#read 4, iclass 30, count 0 2006.239.07:45:59.32#ibcon#about to read 5, iclass 30, count 0 2006.239.07:45:59.32#ibcon#read 5, iclass 30, count 0 2006.239.07:45:59.32#ibcon#about to read 6, iclass 30, count 0 2006.239.07:45:59.32#ibcon#read 6, iclass 30, count 0 2006.239.07:45:59.32#ibcon#end of sib2, iclass 30, count 0 2006.239.07:45:59.32#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:45:59.32#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:45:59.32#ibcon#[25=USB\r\n] 2006.239.07:45:59.32#ibcon#*before write, iclass 30, count 0 2006.239.07:45:59.32#ibcon#enter sib2, iclass 30, count 0 2006.239.07:45:59.32#ibcon#flushed, iclass 30, count 0 2006.239.07:45:59.32#ibcon#about to write, iclass 30, count 0 2006.239.07:45:59.32#ibcon#wrote, iclass 30, count 0 2006.239.07:45:59.32#ibcon#about to read 3, iclass 30, count 0 2006.239.07:45:59.36#ibcon#read 3, iclass 30, count 0 2006.239.07:45:59.36#ibcon#about to read 4, iclass 30, count 0 2006.239.07:45:59.36#ibcon#read 4, iclass 30, count 0 2006.239.07:45:59.36#ibcon#about to read 5, iclass 30, count 0 2006.239.07:45:59.36#ibcon#read 5, iclass 30, count 0 2006.239.07:45:59.36#ibcon#about to read 6, iclass 30, count 0 2006.239.07:45:59.36#ibcon#read 6, iclass 30, count 0 2006.239.07:45:59.36#ibcon#end of sib2, iclass 30, count 0 2006.239.07:45:59.36#ibcon#*after write, iclass 30, count 0 2006.239.07:45:59.36#ibcon#*before return 0, iclass 30, count 0 2006.239.07:45:59.36#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:45:59.36#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:45:59.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:45:59.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:45:59.36$vc4f8/valo=5,652.99 2006.239.07:45:59.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.07:45:59.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.07:45:59.36#ibcon#ireg 17 cls_cnt 0 2006.239.07:45:59.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:45:59.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:45:59.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:45:59.36#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:45:59.36#ibcon#first serial, iclass 36, count 0 2006.239.07:45:59.36#ibcon#enter sib2, iclass 36, count 0 2006.239.07:45:59.36#ibcon#flushed, iclass 36, count 0 2006.239.07:45:59.36#ibcon#about to write, iclass 36, count 0 2006.239.07:45:59.36#ibcon#wrote, iclass 36, count 0 2006.239.07:45:59.36#ibcon#about to read 3, iclass 36, count 0 2006.239.07:45:59.37#ibcon#read 3, iclass 36, count 0 2006.239.07:45:59.37#ibcon#about to read 4, iclass 36, count 0 2006.239.07:45:59.37#ibcon#read 4, iclass 36, count 0 2006.239.07:45:59.37#ibcon#about to read 5, iclass 36, count 0 2006.239.07:45:59.37#ibcon#read 5, iclass 36, count 0 2006.239.07:45:59.37#ibcon#about to read 6, iclass 36, count 0 2006.239.07:45:59.37#ibcon#read 6, iclass 36, count 0 2006.239.07:45:59.37#ibcon#end of sib2, iclass 36, count 0 2006.239.07:45:59.37#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:45:59.37#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:45:59.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:45:59.37#ibcon#*before write, iclass 36, count 0 2006.239.07:45:59.37#ibcon#enter sib2, iclass 36, count 0 2006.239.07:45:59.37#ibcon#flushed, iclass 36, count 0 2006.239.07:45:59.37#ibcon#about to write, iclass 36, count 0 2006.239.07:45:59.37#ibcon#wrote, iclass 36, count 0 2006.239.07:45:59.37#ibcon#about to read 3, iclass 36, count 0 2006.239.07:45:59.41#ibcon#read 3, iclass 36, count 0 2006.239.07:45:59.41#ibcon#about to read 4, iclass 36, count 0 2006.239.07:45:59.41#ibcon#read 4, iclass 36, count 0 2006.239.07:45:59.41#ibcon#about to read 5, iclass 36, count 0 2006.239.07:45:59.41#ibcon#read 5, iclass 36, count 0 2006.239.07:45:59.41#ibcon#about to read 6, iclass 36, count 0 2006.239.07:45:59.41#ibcon#read 6, iclass 36, count 0 2006.239.07:45:59.41#ibcon#end of sib2, iclass 36, count 0 2006.239.07:45:59.41#ibcon#*after write, iclass 36, count 0 2006.239.07:45:59.41#ibcon#*before return 0, iclass 36, count 0 2006.239.07:45:59.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:45:59.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:45:59.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:45:59.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:45:59.41$vc4f8/va=5,8 2006.239.07:45:59.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.07:45:59.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.07:45:59.41#ibcon#ireg 11 cls_cnt 2 2006.239.07:45:59.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:45:59.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:45:59.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:45:59.48#ibcon#enter wrdev, iclass 38, count 2 2006.239.07:45:59.48#ibcon#first serial, iclass 38, count 2 2006.239.07:45:59.48#ibcon#enter sib2, iclass 38, count 2 2006.239.07:45:59.48#ibcon#flushed, iclass 38, count 2 2006.239.07:45:59.48#ibcon#about to write, iclass 38, count 2 2006.239.07:45:59.48#ibcon#wrote, iclass 38, count 2 2006.239.07:45:59.48#ibcon#about to read 3, iclass 38, count 2 2006.239.07:45:59.50#ibcon#read 3, iclass 38, count 2 2006.239.07:45:59.50#ibcon#about to read 4, iclass 38, count 2 2006.239.07:45:59.50#ibcon#read 4, iclass 38, count 2 2006.239.07:45:59.50#ibcon#about to read 5, iclass 38, count 2 2006.239.07:45:59.50#ibcon#read 5, iclass 38, count 2 2006.239.07:45:59.50#ibcon#about to read 6, iclass 38, count 2 2006.239.07:45:59.50#ibcon#read 6, iclass 38, count 2 2006.239.07:45:59.50#ibcon#end of sib2, iclass 38, count 2 2006.239.07:45:59.50#ibcon#*mode == 0, iclass 38, count 2 2006.239.07:45:59.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.07:45:59.50#ibcon#[25=AT05-08\r\n] 2006.239.07:45:59.50#ibcon#*before write, iclass 38, count 2 2006.239.07:45:59.50#ibcon#enter sib2, iclass 38, count 2 2006.239.07:45:59.50#ibcon#flushed, iclass 38, count 2 2006.239.07:45:59.50#ibcon#about to write, iclass 38, count 2 2006.239.07:45:59.50#ibcon#wrote, iclass 38, count 2 2006.239.07:45:59.50#ibcon#about to read 3, iclass 38, count 2 2006.239.07:45:59.53#ibcon#read 3, iclass 38, count 2 2006.239.07:45:59.53#ibcon#about to read 4, iclass 38, count 2 2006.239.07:45:59.53#ibcon#read 4, iclass 38, count 2 2006.239.07:45:59.53#ibcon#about to read 5, iclass 38, count 2 2006.239.07:45:59.53#ibcon#read 5, iclass 38, count 2 2006.239.07:45:59.53#ibcon#about to read 6, iclass 38, count 2 2006.239.07:45:59.53#ibcon#read 6, iclass 38, count 2 2006.239.07:45:59.53#ibcon#end of sib2, iclass 38, count 2 2006.239.07:45:59.53#ibcon#*after write, iclass 38, count 2 2006.239.07:45:59.53#ibcon#*before return 0, iclass 38, count 2 2006.239.07:45:59.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:45:59.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:45:59.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.07:45:59.53#ibcon#ireg 7 cls_cnt 0 2006.239.07:45:59.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:45:59.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:45:59.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:45:59.65#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:45:59.65#ibcon#first serial, iclass 38, count 0 2006.239.07:45:59.65#ibcon#enter sib2, iclass 38, count 0 2006.239.07:45:59.65#ibcon#flushed, iclass 38, count 0 2006.239.07:45:59.65#ibcon#about to write, iclass 38, count 0 2006.239.07:45:59.65#ibcon#wrote, iclass 38, count 0 2006.239.07:45:59.65#ibcon#about to read 3, iclass 38, count 0 2006.239.07:45:59.67#ibcon#read 3, iclass 38, count 0 2006.239.07:45:59.67#ibcon#about to read 4, iclass 38, count 0 2006.239.07:45:59.67#ibcon#read 4, iclass 38, count 0 2006.239.07:45:59.67#ibcon#about to read 5, iclass 38, count 0 2006.239.07:45:59.67#ibcon#read 5, iclass 38, count 0 2006.239.07:45:59.67#ibcon#about to read 6, iclass 38, count 0 2006.239.07:45:59.67#ibcon#read 6, iclass 38, count 0 2006.239.07:45:59.67#ibcon#end of sib2, iclass 38, count 0 2006.239.07:45:59.67#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:45:59.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:45:59.67#ibcon#[25=USB\r\n] 2006.239.07:45:59.67#ibcon#*before write, iclass 38, count 0 2006.239.07:45:59.67#ibcon#enter sib2, iclass 38, count 0 2006.239.07:45:59.67#ibcon#flushed, iclass 38, count 0 2006.239.07:45:59.67#ibcon#about to write, iclass 38, count 0 2006.239.07:45:59.67#ibcon#wrote, iclass 38, count 0 2006.239.07:45:59.67#ibcon#about to read 3, iclass 38, count 0 2006.239.07:45:59.70#ibcon#read 3, iclass 38, count 0 2006.239.07:45:59.70#ibcon#about to read 4, iclass 38, count 0 2006.239.07:45:59.70#ibcon#read 4, iclass 38, count 0 2006.239.07:45:59.70#ibcon#about to read 5, iclass 38, count 0 2006.239.07:45:59.70#ibcon#read 5, iclass 38, count 0 2006.239.07:45:59.70#ibcon#about to read 6, iclass 38, count 0 2006.239.07:45:59.70#ibcon#read 6, iclass 38, count 0 2006.239.07:45:59.70#ibcon#end of sib2, iclass 38, count 0 2006.239.07:45:59.70#ibcon#*after write, iclass 38, count 0 2006.239.07:45:59.70#ibcon#*before return 0, iclass 38, count 0 2006.239.07:45:59.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:45:59.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:45:59.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:45:59.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:45:59.70$vc4f8/valo=6,772.99 2006.239.07:45:59.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:45:59.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:45:59.70#ibcon#ireg 17 cls_cnt 0 2006.239.07:45:59.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:45:59.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:45:59.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:45:59.70#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:45:59.70#ibcon#first serial, iclass 40, count 0 2006.239.07:45:59.70#ibcon#enter sib2, iclass 40, count 0 2006.239.07:45:59.70#ibcon#flushed, iclass 40, count 0 2006.239.07:45:59.70#ibcon#about to write, iclass 40, count 0 2006.239.07:45:59.70#ibcon#wrote, iclass 40, count 0 2006.239.07:45:59.70#ibcon#about to read 3, iclass 40, count 0 2006.239.07:45:59.72#ibcon#read 3, iclass 40, count 0 2006.239.07:45:59.72#ibcon#about to read 4, iclass 40, count 0 2006.239.07:45:59.72#ibcon#read 4, iclass 40, count 0 2006.239.07:45:59.72#ibcon#about to read 5, iclass 40, count 0 2006.239.07:45:59.72#ibcon#read 5, iclass 40, count 0 2006.239.07:45:59.72#ibcon#about to read 6, iclass 40, count 0 2006.239.07:45:59.72#ibcon#read 6, iclass 40, count 0 2006.239.07:45:59.72#ibcon#end of sib2, iclass 40, count 0 2006.239.07:45:59.72#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:45:59.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:45:59.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:45:59.72#ibcon#*before write, iclass 40, count 0 2006.239.07:45:59.72#ibcon#enter sib2, iclass 40, count 0 2006.239.07:45:59.72#ibcon#flushed, iclass 40, count 0 2006.239.07:45:59.72#ibcon#about to write, iclass 40, count 0 2006.239.07:45:59.72#ibcon#wrote, iclass 40, count 0 2006.239.07:45:59.72#ibcon#about to read 3, iclass 40, count 0 2006.239.07:45:59.76#ibcon#read 3, iclass 40, count 0 2006.239.07:45:59.76#ibcon#about to read 4, iclass 40, count 0 2006.239.07:45:59.76#ibcon#read 4, iclass 40, count 0 2006.239.07:45:59.76#ibcon#about to read 5, iclass 40, count 0 2006.239.07:45:59.76#ibcon#read 5, iclass 40, count 0 2006.239.07:45:59.76#ibcon#about to read 6, iclass 40, count 0 2006.239.07:45:59.76#ibcon#read 6, iclass 40, count 0 2006.239.07:45:59.76#ibcon#end of sib2, iclass 40, count 0 2006.239.07:45:59.76#ibcon#*after write, iclass 40, count 0 2006.239.07:45:59.76#ibcon#*before return 0, iclass 40, count 0 2006.239.07:45:59.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:45:59.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:45:59.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:45:59.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:45:59.76$vc4f8/va=6,7 2006.239.07:45:59.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:45:59.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:45:59.76#ibcon#ireg 11 cls_cnt 2 2006.239.07:45:59.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:45:59.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:45:59.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:45:59.82#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:45:59.82#ibcon#first serial, iclass 4, count 2 2006.239.07:45:59.82#ibcon#enter sib2, iclass 4, count 2 2006.239.07:45:59.82#ibcon#flushed, iclass 4, count 2 2006.239.07:45:59.82#ibcon#about to write, iclass 4, count 2 2006.239.07:45:59.82#ibcon#wrote, iclass 4, count 2 2006.239.07:45:59.82#ibcon#about to read 3, iclass 4, count 2 2006.239.07:45:59.84#ibcon#read 3, iclass 4, count 2 2006.239.07:45:59.84#ibcon#about to read 4, iclass 4, count 2 2006.239.07:45:59.84#ibcon#read 4, iclass 4, count 2 2006.239.07:45:59.84#ibcon#about to read 5, iclass 4, count 2 2006.239.07:45:59.84#ibcon#read 5, iclass 4, count 2 2006.239.07:45:59.84#ibcon#about to read 6, iclass 4, count 2 2006.239.07:45:59.84#ibcon#read 6, iclass 4, count 2 2006.239.07:45:59.84#ibcon#end of sib2, iclass 4, count 2 2006.239.07:45:59.84#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:45:59.84#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:45:59.84#ibcon#[25=AT06-07\r\n] 2006.239.07:45:59.84#ibcon#*before write, iclass 4, count 2 2006.239.07:45:59.84#ibcon#enter sib2, iclass 4, count 2 2006.239.07:45:59.84#ibcon#flushed, iclass 4, count 2 2006.239.07:45:59.84#ibcon#about to write, iclass 4, count 2 2006.239.07:45:59.84#ibcon#wrote, iclass 4, count 2 2006.239.07:45:59.84#ibcon#about to read 3, iclass 4, count 2 2006.239.07:45:59.87#ibcon#read 3, iclass 4, count 2 2006.239.07:45:59.87#ibcon#about to read 4, iclass 4, count 2 2006.239.07:45:59.87#ibcon#read 4, iclass 4, count 2 2006.239.07:45:59.87#ibcon#about to read 5, iclass 4, count 2 2006.239.07:45:59.87#ibcon#read 5, iclass 4, count 2 2006.239.07:45:59.87#ibcon#about to read 6, iclass 4, count 2 2006.239.07:45:59.87#ibcon#read 6, iclass 4, count 2 2006.239.07:45:59.87#ibcon#end of sib2, iclass 4, count 2 2006.239.07:45:59.87#ibcon#*after write, iclass 4, count 2 2006.239.07:45:59.87#ibcon#*before return 0, iclass 4, count 2 2006.239.07:45:59.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:45:59.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:45:59.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:45:59.87#ibcon#ireg 7 cls_cnt 0 2006.239.07:45:59.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:45:59.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:45:59.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:45:59.99#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:45:59.99#ibcon#first serial, iclass 4, count 0 2006.239.07:45:59.99#ibcon#enter sib2, iclass 4, count 0 2006.239.07:45:59.99#ibcon#flushed, iclass 4, count 0 2006.239.07:45:59.99#ibcon#about to write, iclass 4, count 0 2006.239.07:45:59.99#ibcon#wrote, iclass 4, count 0 2006.239.07:45:59.99#ibcon#about to read 3, iclass 4, count 0 2006.239.07:46:00.01#ibcon#read 3, iclass 4, count 0 2006.239.07:46:00.01#ibcon#about to read 4, iclass 4, count 0 2006.239.07:46:00.01#ibcon#read 4, iclass 4, count 0 2006.239.07:46:00.01#ibcon#about to read 5, iclass 4, count 0 2006.239.07:46:00.01#ibcon#read 5, iclass 4, count 0 2006.239.07:46:00.01#ibcon#about to read 6, iclass 4, count 0 2006.239.07:46:00.01#ibcon#read 6, iclass 4, count 0 2006.239.07:46:00.01#ibcon#end of sib2, iclass 4, count 0 2006.239.07:46:00.01#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:46:00.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:46:00.01#ibcon#[25=USB\r\n] 2006.239.07:46:00.01#ibcon#*before write, iclass 4, count 0 2006.239.07:46:00.01#ibcon#enter sib2, iclass 4, count 0 2006.239.07:46:00.01#ibcon#flushed, iclass 4, count 0 2006.239.07:46:00.01#ibcon#about to write, iclass 4, count 0 2006.239.07:46:00.01#ibcon#wrote, iclass 4, count 0 2006.239.07:46:00.01#ibcon#about to read 3, iclass 4, count 0 2006.239.07:46:00.04#ibcon#read 3, iclass 4, count 0 2006.239.07:46:00.04#ibcon#about to read 4, iclass 4, count 0 2006.239.07:46:00.04#ibcon#read 4, iclass 4, count 0 2006.239.07:46:00.04#ibcon#about to read 5, iclass 4, count 0 2006.239.07:46:00.04#ibcon#read 5, iclass 4, count 0 2006.239.07:46:00.04#ibcon#about to read 6, iclass 4, count 0 2006.239.07:46:00.04#ibcon#read 6, iclass 4, count 0 2006.239.07:46:00.04#ibcon#end of sib2, iclass 4, count 0 2006.239.07:46:00.04#ibcon#*after write, iclass 4, count 0 2006.239.07:46:00.04#ibcon#*before return 0, iclass 4, count 0 2006.239.07:46:00.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:46:00.04#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:46:00.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:46:00.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:46:00.04$vc4f8/valo=7,832.99 2006.239.07:46:00.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:46:00.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:46:00.04#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:00.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:46:00.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:46:00.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:46:00.04#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:46:00.04#ibcon#first serial, iclass 6, count 0 2006.239.07:46:00.04#ibcon#enter sib2, iclass 6, count 0 2006.239.07:46:00.04#ibcon#flushed, iclass 6, count 0 2006.239.07:46:00.04#ibcon#about to write, iclass 6, count 0 2006.239.07:46:00.04#ibcon#wrote, iclass 6, count 0 2006.239.07:46:00.04#ibcon#about to read 3, iclass 6, count 0 2006.239.07:46:00.06#ibcon#read 3, iclass 6, count 0 2006.239.07:46:00.06#ibcon#about to read 4, iclass 6, count 0 2006.239.07:46:00.06#ibcon#read 4, iclass 6, count 0 2006.239.07:46:00.06#ibcon#about to read 5, iclass 6, count 0 2006.239.07:46:00.06#ibcon#read 5, iclass 6, count 0 2006.239.07:46:00.06#ibcon#about to read 6, iclass 6, count 0 2006.239.07:46:00.06#ibcon#read 6, iclass 6, count 0 2006.239.07:46:00.06#ibcon#end of sib2, iclass 6, count 0 2006.239.07:46:00.06#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:46:00.06#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:46:00.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:46:00.06#ibcon#*before write, iclass 6, count 0 2006.239.07:46:00.06#ibcon#enter sib2, iclass 6, count 0 2006.239.07:46:00.06#ibcon#flushed, iclass 6, count 0 2006.239.07:46:00.06#ibcon#about to write, iclass 6, count 0 2006.239.07:46:00.06#ibcon#wrote, iclass 6, count 0 2006.239.07:46:00.06#ibcon#about to read 3, iclass 6, count 0 2006.239.07:46:00.10#ibcon#read 3, iclass 6, count 0 2006.239.07:46:00.10#ibcon#about to read 4, iclass 6, count 0 2006.239.07:46:00.10#ibcon#read 4, iclass 6, count 0 2006.239.07:46:00.10#ibcon#about to read 5, iclass 6, count 0 2006.239.07:46:00.10#ibcon#read 5, iclass 6, count 0 2006.239.07:46:00.10#ibcon#about to read 6, iclass 6, count 0 2006.239.07:46:00.10#ibcon#read 6, iclass 6, count 0 2006.239.07:46:00.10#ibcon#end of sib2, iclass 6, count 0 2006.239.07:46:00.10#ibcon#*after write, iclass 6, count 0 2006.239.07:46:00.10#ibcon#*before return 0, iclass 6, count 0 2006.239.07:46:00.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:46:00.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:46:00.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:46:00.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:46:00.10$vc4f8/va=7,7 2006.239.07:46:00.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:46:00.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:46:00.10#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:00.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:46:00.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:46:00.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:46:00.16#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:46:00.16#ibcon#first serial, iclass 10, count 2 2006.239.07:46:00.16#ibcon#enter sib2, iclass 10, count 2 2006.239.07:46:00.16#ibcon#flushed, iclass 10, count 2 2006.239.07:46:00.16#ibcon#about to write, iclass 10, count 2 2006.239.07:46:00.16#ibcon#wrote, iclass 10, count 2 2006.239.07:46:00.16#ibcon#about to read 3, iclass 10, count 2 2006.239.07:46:00.18#ibcon#read 3, iclass 10, count 2 2006.239.07:46:00.18#ibcon#about to read 4, iclass 10, count 2 2006.239.07:46:00.18#ibcon#read 4, iclass 10, count 2 2006.239.07:46:00.18#ibcon#about to read 5, iclass 10, count 2 2006.239.07:46:00.18#ibcon#read 5, iclass 10, count 2 2006.239.07:46:00.18#ibcon#about to read 6, iclass 10, count 2 2006.239.07:46:00.18#ibcon#read 6, iclass 10, count 2 2006.239.07:46:00.18#ibcon#end of sib2, iclass 10, count 2 2006.239.07:46:00.18#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:46:00.18#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:46:00.18#ibcon#[25=AT07-07\r\n] 2006.239.07:46:00.18#ibcon#*before write, iclass 10, count 2 2006.239.07:46:00.18#ibcon#enter sib2, iclass 10, count 2 2006.239.07:46:00.18#ibcon#flushed, iclass 10, count 2 2006.239.07:46:00.18#ibcon#about to write, iclass 10, count 2 2006.239.07:46:00.18#ibcon#wrote, iclass 10, count 2 2006.239.07:46:00.18#ibcon#about to read 3, iclass 10, count 2 2006.239.07:46:00.24#ibcon#read 3, iclass 10, count 2 2006.239.07:46:00.24#ibcon#about to read 4, iclass 10, count 2 2006.239.07:46:00.24#ibcon#read 4, iclass 10, count 2 2006.239.07:46:00.24#ibcon#about to read 5, iclass 10, count 2 2006.239.07:46:00.24#ibcon#read 5, iclass 10, count 2 2006.239.07:46:00.24#ibcon#about to read 6, iclass 10, count 2 2006.239.07:46:00.24#ibcon#read 6, iclass 10, count 2 2006.239.07:46:00.24#ibcon#end of sib2, iclass 10, count 2 2006.239.07:46:00.24#ibcon#*after write, iclass 10, count 2 2006.239.07:46:00.24#ibcon#*before return 0, iclass 10, count 2 2006.239.07:46:00.24#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:46:00.24#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:46:00.24#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:46:00.24#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:00.24#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:46:00.35#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:46:00.35#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:46:00.35#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:46:00.35#ibcon#first serial, iclass 10, count 0 2006.239.07:46:00.35#ibcon#enter sib2, iclass 10, count 0 2006.239.07:46:00.35#ibcon#flushed, iclass 10, count 0 2006.239.07:46:00.35#ibcon#about to write, iclass 10, count 0 2006.239.07:46:00.35#ibcon#wrote, iclass 10, count 0 2006.239.07:46:00.35#ibcon#about to read 3, iclass 10, count 0 2006.239.07:46:00.37#ibcon#read 3, iclass 10, count 0 2006.239.07:46:00.37#ibcon#about to read 4, iclass 10, count 0 2006.239.07:46:00.37#ibcon#read 4, iclass 10, count 0 2006.239.07:46:00.37#ibcon#about to read 5, iclass 10, count 0 2006.239.07:46:00.37#ibcon#read 5, iclass 10, count 0 2006.239.07:46:00.37#ibcon#about to read 6, iclass 10, count 0 2006.239.07:46:00.37#ibcon#read 6, iclass 10, count 0 2006.239.07:46:00.37#ibcon#end of sib2, iclass 10, count 0 2006.239.07:46:00.37#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:46:00.37#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:46:00.37#ibcon#[25=USB\r\n] 2006.239.07:46:00.37#ibcon#*before write, iclass 10, count 0 2006.239.07:46:00.37#ibcon#enter sib2, iclass 10, count 0 2006.239.07:46:00.37#ibcon#flushed, iclass 10, count 0 2006.239.07:46:00.37#ibcon#about to write, iclass 10, count 0 2006.239.07:46:00.37#ibcon#wrote, iclass 10, count 0 2006.239.07:46:00.37#ibcon#about to read 3, iclass 10, count 0 2006.239.07:46:00.40#ibcon#read 3, iclass 10, count 0 2006.239.07:46:00.40#ibcon#about to read 4, iclass 10, count 0 2006.239.07:46:00.40#ibcon#read 4, iclass 10, count 0 2006.239.07:46:00.40#ibcon#about to read 5, iclass 10, count 0 2006.239.07:46:00.40#ibcon#read 5, iclass 10, count 0 2006.239.07:46:00.40#ibcon#about to read 6, iclass 10, count 0 2006.239.07:46:00.40#ibcon#read 6, iclass 10, count 0 2006.239.07:46:00.40#ibcon#end of sib2, iclass 10, count 0 2006.239.07:46:00.40#ibcon#*after write, iclass 10, count 0 2006.239.07:46:00.40#ibcon#*before return 0, iclass 10, count 0 2006.239.07:46:00.40#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:46:00.40#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:46:00.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:46:00.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:46:00.40$vc4f8/valo=8,852.99 2006.239.07:46:00.40#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:46:00.40#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:46:00.40#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:00.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:46:00.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:46:00.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:46:00.40#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:46:00.40#ibcon#first serial, iclass 12, count 0 2006.239.07:46:00.40#ibcon#enter sib2, iclass 12, count 0 2006.239.07:46:00.40#ibcon#flushed, iclass 12, count 0 2006.239.07:46:00.40#ibcon#about to write, iclass 12, count 0 2006.239.07:46:00.40#ibcon#wrote, iclass 12, count 0 2006.239.07:46:00.40#ibcon#about to read 3, iclass 12, count 0 2006.239.07:46:00.42#ibcon#read 3, iclass 12, count 0 2006.239.07:46:00.42#ibcon#about to read 4, iclass 12, count 0 2006.239.07:46:00.42#ibcon#read 4, iclass 12, count 0 2006.239.07:46:00.42#ibcon#about to read 5, iclass 12, count 0 2006.239.07:46:00.42#ibcon#read 5, iclass 12, count 0 2006.239.07:46:00.42#ibcon#about to read 6, iclass 12, count 0 2006.239.07:46:00.42#ibcon#read 6, iclass 12, count 0 2006.239.07:46:00.42#ibcon#end of sib2, iclass 12, count 0 2006.239.07:46:00.42#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:46:00.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:46:00.42#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:46:00.42#ibcon#*before write, iclass 12, count 0 2006.239.07:46:00.42#ibcon#enter sib2, iclass 12, count 0 2006.239.07:46:00.42#ibcon#flushed, iclass 12, count 0 2006.239.07:46:00.42#ibcon#about to write, iclass 12, count 0 2006.239.07:46:00.42#ibcon#wrote, iclass 12, count 0 2006.239.07:46:00.42#ibcon#about to read 3, iclass 12, count 0 2006.239.07:46:00.46#ibcon#read 3, iclass 12, count 0 2006.239.07:46:00.46#ibcon#about to read 4, iclass 12, count 0 2006.239.07:46:00.46#ibcon#read 4, iclass 12, count 0 2006.239.07:46:00.46#ibcon#about to read 5, iclass 12, count 0 2006.239.07:46:00.46#ibcon#read 5, iclass 12, count 0 2006.239.07:46:00.46#ibcon#about to read 6, iclass 12, count 0 2006.239.07:46:00.46#ibcon#read 6, iclass 12, count 0 2006.239.07:46:00.46#ibcon#end of sib2, iclass 12, count 0 2006.239.07:46:00.46#ibcon#*after write, iclass 12, count 0 2006.239.07:46:00.46#ibcon#*before return 0, iclass 12, count 0 2006.239.07:46:00.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:46:00.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:46:00.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:46:00.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:46:00.46$vc4f8/va=8,7 2006.239.07:46:00.46#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.07:46:00.46#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.07:46:00.46#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:00.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:46:00.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:46:00.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:46:00.52#ibcon#enter wrdev, iclass 14, count 2 2006.239.07:46:00.52#ibcon#first serial, iclass 14, count 2 2006.239.07:46:00.52#ibcon#enter sib2, iclass 14, count 2 2006.239.07:46:00.52#ibcon#flushed, iclass 14, count 2 2006.239.07:46:00.52#ibcon#about to write, iclass 14, count 2 2006.239.07:46:00.52#ibcon#wrote, iclass 14, count 2 2006.239.07:46:00.52#ibcon#about to read 3, iclass 14, count 2 2006.239.07:46:00.54#ibcon#read 3, iclass 14, count 2 2006.239.07:46:00.54#ibcon#about to read 4, iclass 14, count 2 2006.239.07:46:00.54#ibcon#read 4, iclass 14, count 2 2006.239.07:46:00.54#ibcon#about to read 5, iclass 14, count 2 2006.239.07:46:00.54#ibcon#read 5, iclass 14, count 2 2006.239.07:46:00.54#ibcon#about to read 6, iclass 14, count 2 2006.239.07:46:00.54#ibcon#read 6, iclass 14, count 2 2006.239.07:46:00.54#ibcon#end of sib2, iclass 14, count 2 2006.239.07:46:00.54#ibcon#*mode == 0, iclass 14, count 2 2006.239.07:46:00.54#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.07:46:00.54#ibcon#[25=AT08-07\r\n] 2006.239.07:46:00.54#ibcon#*before write, iclass 14, count 2 2006.239.07:46:00.54#ibcon#enter sib2, iclass 14, count 2 2006.239.07:46:00.54#ibcon#flushed, iclass 14, count 2 2006.239.07:46:00.54#ibcon#about to write, iclass 14, count 2 2006.239.07:46:00.54#ibcon#wrote, iclass 14, count 2 2006.239.07:46:00.54#ibcon#about to read 3, iclass 14, count 2 2006.239.07:46:00.57#ibcon#read 3, iclass 14, count 2 2006.239.07:46:00.57#ibcon#about to read 4, iclass 14, count 2 2006.239.07:46:00.57#ibcon#read 4, iclass 14, count 2 2006.239.07:46:00.57#ibcon#about to read 5, iclass 14, count 2 2006.239.07:46:00.57#ibcon#read 5, iclass 14, count 2 2006.239.07:46:00.57#ibcon#about to read 6, iclass 14, count 2 2006.239.07:46:00.57#ibcon#read 6, iclass 14, count 2 2006.239.07:46:00.57#ibcon#end of sib2, iclass 14, count 2 2006.239.07:46:00.57#ibcon#*after write, iclass 14, count 2 2006.239.07:46:00.57#ibcon#*before return 0, iclass 14, count 2 2006.239.07:46:00.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:46:00.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:46:00.57#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.07:46:00.57#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:00.57#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:46:00.69#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:46:00.69#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:46:00.69#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:46:00.69#ibcon#first serial, iclass 14, count 0 2006.239.07:46:00.69#ibcon#enter sib2, iclass 14, count 0 2006.239.07:46:00.69#ibcon#flushed, iclass 14, count 0 2006.239.07:46:00.69#ibcon#about to write, iclass 14, count 0 2006.239.07:46:00.69#ibcon#wrote, iclass 14, count 0 2006.239.07:46:00.69#ibcon#about to read 3, iclass 14, count 0 2006.239.07:46:00.71#ibcon#read 3, iclass 14, count 0 2006.239.07:46:00.71#ibcon#about to read 4, iclass 14, count 0 2006.239.07:46:00.71#ibcon#read 4, iclass 14, count 0 2006.239.07:46:00.71#ibcon#about to read 5, iclass 14, count 0 2006.239.07:46:00.71#ibcon#read 5, iclass 14, count 0 2006.239.07:46:00.71#ibcon#about to read 6, iclass 14, count 0 2006.239.07:46:00.71#ibcon#read 6, iclass 14, count 0 2006.239.07:46:00.71#ibcon#end of sib2, iclass 14, count 0 2006.239.07:46:00.71#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:46:00.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:46:00.71#ibcon#[25=USB\r\n] 2006.239.07:46:00.71#ibcon#*before write, iclass 14, count 0 2006.239.07:46:00.71#ibcon#enter sib2, iclass 14, count 0 2006.239.07:46:00.71#ibcon#flushed, iclass 14, count 0 2006.239.07:46:00.71#ibcon#about to write, iclass 14, count 0 2006.239.07:46:00.71#ibcon#wrote, iclass 14, count 0 2006.239.07:46:00.71#ibcon#about to read 3, iclass 14, count 0 2006.239.07:46:00.74#ibcon#read 3, iclass 14, count 0 2006.239.07:46:00.74#ibcon#about to read 4, iclass 14, count 0 2006.239.07:46:00.74#ibcon#read 4, iclass 14, count 0 2006.239.07:46:00.74#ibcon#about to read 5, iclass 14, count 0 2006.239.07:46:00.74#ibcon#read 5, iclass 14, count 0 2006.239.07:46:00.74#ibcon#about to read 6, iclass 14, count 0 2006.239.07:46:00.74#ibcon#read 6, iclass 14, count 0 2006.239.07:46:00.74#ibcon#end of sib2, iclass 14, count 0 2006.239.07:46:00.74#ibcon#*after write, iclass 14, count 0 2006.239.07:46:00.74#ibcon#*before return 0, iclass 14, count 0 2006.239.07:46:00.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:46:00.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:46:00.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:46:00.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:46:00.74$vc4f8/vblo=1,632.99 2006.239.07:46:00.74#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:46:00.74#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:46:00.74#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:00.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:46:00.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:46:00.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:46:00.74#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:46:00.74#ibcon#first serial, iclass 16, count 0 2006.239.07:46:00.74#ibcon#enter sib2, iclass 16, count 0 2006.239.07:46:00.74#ibcon#flushed, iclass 16, count 0 2006.239.07:46:00.74#ibcon#about to write, iclass 16, count 0 2006.239.07:46:00.74#ibcon#wrote, iclass 16, count 0 2006.239.07:46:00.74#ibcon#about to read 3, iclass 16, count 0 2006.239.07:46:00.76#ibcon#read 3, iclass 16, count 0 2006.239.07:46:00.76#ibcon#about to read 4, iclass 16, count 0 2006.239.07:46:00.76#ibcon#read 4, iclass 16, count 0 2006.239.07:46:00.76#ibcon#about to read 5, iclass 16, count 0 2006.239.07:46:00.76#ibcon#read 5, iclass 16, count 0 2006.239.07:46:00.76#ibcon#about to read 6, iclass 16, count 0 2006.239.07:46:00.76#ibcon#read 6, iclass 16, count 0 2006.239.07:46:00.76#ibcon#end of sib2, iclass 16, count 0 2006.239.07:46:00.76#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:46:00.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:46:00.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:46:00.76#ibcon#*before write, iclass 16, count 0 2006.239.07:46:00.76#ibcon#enter sib2, iclass 16, count 0 2006.239.07:46:00.76#ibcon#flushed, iclass 16, count 0 2006.239.07:46:00.76#ibcon#about to write, iclass 16, count 0 2006.239.07:46:00.76#ibcon#wrote, iclass 16, count 0 2006.239.07:46:00.76#ibcon#about to read 3, iclass 16, count 0 2006.239.07:46:00.80#ibcon#read 3, iclass 16, count 0 2006.239.07:46:00.80#ibcon#about to read 4, iclass 16, count 0 2006.239.07:46:00.80#ibcon#read 4, iclass 16, count 0 2006.239.07:46:00.80#ibcon#about to read 5, iclass 16, count 0 2006.239.07:46:00.80#ibcon#read 5, iclass 16, count 0 2006.239.07:46:00.80#ibcon#about to read 6, iclass 16, count 0 2006.239.07:46:00.80#ibcon#read 6, iclass 16, count 0 2006.239.07:46:00.80#ibcon#end of sib2, iclass 16, count 0 2006.239.07:46:00.80#ibcon#*after write, iclass 16, count 0 2006.239.07:46:00.80#ibcon#*before return 0, iclass 16, count 0 2006.239.07:46:00.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:46:00.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:46:00.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:46:00.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:46:00.80$vc4f8/vb=1,4 2006.239.07:46:00.80#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:46:00.80#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:46:00.80#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:00.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:46:00.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:46:00.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:46:00.80#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:46:00.80#ibcon#first serial, iclass 18, count 2 2006.239.07:46:00.80#ibcon#enter sib2, iclass 18, count 2 2006.239.07:46:00.80#ibcon#flushed, iclass 18, count 2 2006.239.07:46:00.80#ibcon#about to write, iclass 18, count 2 2006.239.07:46:00.80#ibcon#wrote, iclass 18, count 2 2006.239.07:46:00.80#ibcon#about to read 3, iclass 18, count 2 2006.239.07:46:00.82#ibcon#read 3, iclass 18, count 2 2006.239.07:46:00.82#ibcon#about to read 4, iclass 18, count 2 2006.239.07:46:00.82#ibcon#read 4, iclass 18, count 2 2006.239.07:46:00.82#ibcon#about to read 5, iclass 18, count 2 2006.239.07:46:00.82#ibcon#read 5, iclass 18, count 2 2006.239.07:46:00.82#ibcon#about to read 6, iclass 18, count 2 2006.239.07:46:00.82#ibcon#read 6, iclass 18, count 2 2006.239.07:46:00.82#ibcon#end of sib2, iclass 18, count 2 2006.239.07:46:00.82#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:46:00.82#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:46:00.82#ibcon#[27=AT01-04\r\n] 2006.239.07:46:00.82#ibcon#*before write, iclass 18, count 2 2006.239.07:46:00.82#ibcon#enter sib2, iclass 18, count 2 2006.239.07:46:00.82#ibcon#flushed, iclass 18, count 2 2006.239.07:46:00.82#ibcon#about to write, iclass 18, count 2 2006.239.07:46:00.82#ibcon#wrote, iclass 18, count 2 2006.239.07:46:00.82#ibcon#about to read 3, iclass 18, count 2 2006.239.07:46:00.85#ibcon#read 3, iclass 18, count 2 2006.239.07:46:00.85#ibcon#about to read 4, iclass 18, count 2 2006.239.07:46:00.85#ibcon#read 4, iclass 18, count 2 2006.239.07:46:00.85#ibcon#about to read 5, iclass 18, count 2 2006.239.07:46:00.85#ibcon#read 5, iclass 18, count 2 2006.239.07:46:00.85#ibcon#about to read 6, iclass 18, count 2 2006.239.07:46:00.85#ibcon#read 6, iclass 18, count 2 2006.239.07:46:00.85#ibcon#end of sib2, iclass 18, count 2 2006.239.07:46:00.85#ibcon#*after write, iclass 18, count 2 2006.239.07:46:00.85#ibcon#*before return 0, iclass 18, count 2 2006.239.07:46:00.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:46:00.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:46:00.85#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:46:00.85#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:00.85#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:46:00.97#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:46:00.97#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:46:00.97#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:46:00.97#ibcon#first serial, iclass 18, count 0 2006.239.07:46:00.97#ibcon#enter sib2, iclass 18, count 0 2006.239.07:46:00.97#ibcon#flushed, iclass 18, count 0 2006.239.07:46:00.97#ibcon#about to write, iclass 18, count 0 2006.239.07:46:00.97#ibcon#wrote, iclass 18, count 0 2006.239.07:46:00.97#ibcon#about to read 3, iclass 18, count 0 2006.239.07:46:00.99#ibcon#read 3, iclass 18, count 0 2006.239.07:46:00.99#ibcon#about to read 4, iclass 18, count 0 2006.239.07:46:00.99#ibcon#read 4, iclass 18, count 0 2006.239.07:46:00.99#ibcon#about to read 5, iclass 18, count 0 2006.239.07:46:00.99#ibcon#read 5, iclass 18, count 0 2006.239.07:46:00.99#ibcon#about to read 6, iclass 18, count 0 2006.239.07:46:00.99#ibcon#read 6, iclass 18, count 0 2006.239.07:46:00.99#ibcon#end of sib2, iclass 18, count 0 2006.239.07:46:00.99#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:46:00.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:46:00.99#ibcon#[27=USB\r\n] 2006.239.07:46:00.99#ibcon#*before write, iclass 18, count 0 2006.239.07:46:00.99#ibcon#enter sib2, iclass 18, count 0 2006.239.07:46:00.99#ibcon#flushed, iclass 18, count 0 2006.239.07:46:00.99#ibcon#about to write, iclass 18, count 0 2006.239.07:46:00.99#ibcon#wrote, iclass 18, count 0 2006.239.07:46:00.99#ibcon#about to read 3, iclass 18, count 0 2006.239.07:46:01.02#ibcon#read 3, iclass 18, count 0 2006.239.07:46:01.02#ibcon#about to read 4, iclass 18, count 0 2006.239.07:46:01.02#ibcon#read 4, iclass 18, count 0 2006.239.07:46:01.02#ibcon#about to read 5, iclass 18, count 0 2006.239.07:46:01.02#ibcon#read 5, iclass 18, count 0 2006.239.07:46:01.02#ibcon#about to read 6, iclass 18, count 0 2006.239.07:46:01.02#ibcon#read 6, iclass 18, count 0 2006.239.07:46:01.02#ibcon#end of sib2, iclass 18, count 0 2006.239.07:46:01.02#ibcon#*after write, iclass 18, count 0 2006.239.07:46:01.02#ibcon#*before return 0, iclass 18, count 0 2006.239.07:46:01.02#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:46:01.02#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:46:01.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:46:01.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:46:01.02$vc4f8/vblo=2,640.99 2006.239.07:46:01.02#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:46:01.02#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:46:01.02#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:01.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:46:01.02#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:46:01.02#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:46:01.02#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:46:01.02#ibcon#first serial, iclass 20, count 0 2006.239.07:46:01.02#ibcon#enter sib2, iclass 20, count 0 2006.239.07:46:01.02#ibcon#flushed, iclass 20, count 0 2006.239.07:46:01.02#ibcon#about to write, iclass 20, count 0 2006.239.07:46:01.02#ibcon#wrote, iclass 20, count 0 2006.239.07:46:01.02#ibcon#about to read 3, iclass 20, count 0 2006.239.07:46:01.04#ibcon#read 3, iclass 20, count 0 2006.239.07:46:01.04#ibcon#about to read 4, iclass 20, count 0 2006.239.07:46:01.04#ibcon#read 4, iclass 20, count 0 2006.239.07:46:01.04#ibcon#about to read 5, iclass 20, count 0 2006.239.07:46:01.04#ibcon#read 5, iclass 20, count 0 2006.239.07:46:01.04#ibcon#about to read 6, iclass 20, count 0 2006.239.07:46:01.04#ibcon#read 6, iclass 20, count 0 2006.239.07:46:01.04#ibcon#end of sib2, iclass 20, count 0 2006.239.07:46:01.04#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:46:01.04#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:46:01.04#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:46:01.04#ibcon#*before write, iclass 20, count 0 2006.239.07:46:01.04#ibcon#enter sib2, iclass 20, count 0 2006.239.07:46:01.04#ibcon#flushed, iclass 20, count 0 2006.239.07:46:01.04#ibcon#about to write, iclass 20, count 0 2006.239.07:46:01.04#ibcon#wrote, iclass 20, count 0 2006.239.07:46:01.04#ibcon#about to read 3, iclass 20, count 0 2006.239.07:46:01.08#ibcon#read 3, iclass 20, count 0 2006.239.07:46:01.08#ibcon#about to read 4, iclass 20, count 0 2006.239.07:46:01.08#ibcon#read 4, iclass 20, count 0 2006.239.07:46:01.08#ibcon#about to read 5, iclass 20, count 0 2006.239.07:46:01.08#ibcon#read 5, iclass 20, count 0 2006.239.07:46:01.08#ibcon#about to read 6, iclass 20, count 0 2006.239.07:46:01.08#ibcon#read 6, iclass 20, count 0 2006.239.07:46:01.08#ibcon#end of sib2, iclass 20, count 0 2006.239.07:46:01.08#ibcon#*after write, iclass 20, count 0 2006.239.07:46:01.08#ibcon#*before return 0, iclass 20, count 0 2006.239.07:46:01.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:46:01.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:46:01.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:46:01.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:46:01.08$vc4f8/vb=2,4 2006.239.07:46:01.08#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:46:01.08#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:46:01.08#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:01.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:46:01.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:46:01.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:46:01.14#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:46:01.14#ibcon#first serial, iclass 22, count 2 2006.239.07:46:01.14#ibcon#enter sib2, iclass 22, count 2 2006.239.07:46:01.14#ibcon#flushed, iclass 22, count 2 2006.239.07:46:01.14#ibcon#about to write, iclass 22, count 2 2006.239.07:46:01.14#ibcon#wrote, iclass 22, count 2 2006.239.07:46:01.14#ibcon#about to read 3, iclass 22, count 2 2006.239.07:46:01.16#ibcon#read 3, iclass 22, count 2 2006.239.07:46:01.16#ibcon#about to read 4, iclass 22, count 2 2006.239.07:46:01.16#ibcon#read 4, iclass 22, count 2 2006.239.07:46:01.16#ibcon#about to read 5, iclass 22, count 2 2006.239.07:46:01.16#ibcon#read 5, iclass 22, count 2 2006.239.07:46:01.16#ibcon#about to read 6, iclass 22, count 2 2006.239.07:46:01.16#ibcon#read 6, iclass 22, count 2 2006.239.07:46:01.16#ibcon#end of sib2, iclass 22, count 2 2006.239.07:46:01.16#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:46:01.16#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:46:01.16#ibcon#[27=AT02-04\r\n] 2006.239.07:46:01.16#ibcon#*before write, iclass 22, count 2 2006.239.07:46:01.16#ibcon#enter sib2, iclass 22, count 2 2006.239.07:46:01.16#ibcon#flushed, iclass 22, count 2 2006.239.07:46:01.16#ibcon#about to write, iclass 22, count 2 2006.239.07:46:01.16#ibcon#wrote, iclass 22, count 2 2006.239.07:46:01.16#ibcon#about to read 3, iclass 22, count 2 2006.239.07:46:01.19#ibcon#read 3, iclass 22, count 2 2006.239.07:46:01.19#ibcon#about to read 4, iclass 22, count 2 2006.239.07:46:01.19#ibcon#read 4, iclass 22, count 2 2006.239.07:46:01.19#ibcon#about to read 5, iclass 22, count 2 2006.239.07:46:01.19#ibcon#read 5, iclass 22, count 2 2006.239.07:46:01.19#ibcon#about to read 6, iclass 22, count 2 2006.239.07:46:01.19#ibcon#read 6, iclass 22, count 2 2006.239.07:46:01.19#ibcon#end of sib2, iclass 22, count 2 2006.239.07:46:01.19#ibcon#*after write, iclass 22, count 2 2006.239.07:46:01.19#ibcon#*before return 0, iclass 22, count 2 2006.239.07:46:01.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:46:01.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:46:01.19#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:46:01.19#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:01.19#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:46:01.31#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:46:01.31#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:46:01.31#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:46:01.31#ibcon#first serial, iclass 22, count 0 2006.239.07:46:01.31#ibcon#enter sib2, iclass 22, count 0 2006.239.07:46:01.31#ibcon#flushed, iclass 22, count 0 2006.239.07:46:01.31#ibcon#about to write, iclass 22, count 0 2006.239.07:46:01.31#ibcon#wrote, iclass 22, count 0 2006.239.07:46:01.31#ibcon#about to read 3, iclass 22, count 0 2006.239.07:46:01.33#ibcon#read 3, iclass 22, count 0 2006.239.07:46:01.33#ibcon#about to read 4, iclass 22, count 0 2006.239.07:46:01.33#ibcon#read 4, iclass 22, count 0 2006.239.07:46:01.33#ibcon#about to read 5, iclass 22, count 0 2006.239.07:46:01.33#ibcon#read 5, iclass 22, count 0 2006.239.07:46:01.33#ibcon#about to read 6, iclass 22, count 0 2006.239.07:46:01.33#ibcon#read 6, iclass 22, count 0 2006.239.07:46:01.33#ibcon#end of sib2, iclass 22, count 0 2006.239.07:46:01.33#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:46:01.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:46:01.33#ibcon#[27=USB\r\n] 2006.239.07:46:01.33#ibcon#*before write, iclass 22, count 0 2006.239.07:46:01.33#ibcon#enter sib2, iclass 22, count 0 2006.239.07:46:01.33#ibcon#flushed, iclass 22, count 0 2006.239.07:46:01.33#ibcon#about to write, iclass 22, count 0 2006.239.07:46:01.33#ibcon#wrote, iclass 22, count 0 2006.239.07:46:01.33#ibcon#about to read 3, iclass 22, count 0 2006.239.07:46:01.36#ibcon#read 3, iclass 22, count 0 2006.239.07:46:01.36#ibcon#about to read 4, iclass 22, count 0 2006.239.07:46:01.36#ibcon#read 4, iclass 22, count 0 2006.239.07:46:01.36#ibcon#about to read 5, iclass 22, count 0 2006.239.07:46:01.36#ibcon#read 5, iclass 22, count 0 2006.239.07:46:01.36#ibcon#about to read 6, iclass 22, count 0 2006.239.07:46:01.36#ibcon#read 6, iclass 22, count 0 2006.239.07:46:01.36#ibcon#end of sib2, iclass 22, count 0 2006.239.07:46:01.36#ibcon#*after write, iclass 22, count 0 2006.239.07:46:01.36#ibcon#*before return 0, iclass 22, count 0 2006.239.07:46:01.36#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:46:01.36#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:46:01.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:46:01.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:46:01.36$vc4f8/vblo=3,656.99 2006.239.07:46:01.36#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:46:01.36#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:46:01.36#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:01.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:46:01.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:46:01.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:46:01.36#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:46:01.36#ibcon#first serial, iclass 24, count 0 2006.239.07:46:01.36#ibcon#enter sib2, iclass 24, count 0 2006.239.07:46:01.36#ibcon#flushed, iclass 24, count 0 2006.239.07:46:01.36#ibcon#about to write, iclass 24, count 0 2006.239.07:46:01.36#ibcon#wrote, iclass 24, count 0 2006.239.07:46:01.36#ibcon#about to read 3, iclass 24, count 0 2006.239.07:46:01.38#ibcon#read 3, iclass 24, count 0 2006.239.07:46:01.38#ibcon#about to read 4, iclass 24, count 0 2006.239.07:46:01.38#ibcon#read 4, iclass 24, count 0 2006.239.07:46:01.38#ibcon#about to read 5, iclass 24, count 0 2006.239.07:46:01.38#ibcon#read 5, iclass 24, count 0 2006.239.07:46:01.38#ibcon#about to read 6, iclass 24, count 0 2006.239.07:46:01.38#ibcon#read 6, iclass 24, count 0 2006.239.07:46:01.38#ibcon#end of sib2, iclass 24, count 0 2006.239.07:46:01.38#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:46:01.38#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:46:01.38#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:46:01.38#ibcon#*before write, iclass 24, count 0 2006.239.07:46:01.38#ibcon#enter sib2, iclass 24, count 0 2006.239.07:46:01.38#ibcon#flushed, iclass 24, count 0 2006.239.07:46:01.38#ibcon#about to write, iclass 24, count 0 2006.239.07:46:01.38#ibcon#wrote, iclass 24, count 0 2006.239.07:46:01.38#ibcon#about to read 3, iclass 24, count 0 2006.239.07:46:01.42#ibcon#read 3, iclass 24, count 0 2006.239.07:46:01.42#ibcon#about to read 4, iclass 24, count 0 2006.239.07:46:01.42#ibcon#read 4, iclass 24, count 0 2006.239.07:46:01.42#ibcon#about to read 5, iclass 24, count 0 2006.239.07:46:01.42#ibcon#read 5, iclass 24, count 0 2006.239.07:46:01.42#ibcon#about to read 6, iclass 24, count 0 2006.239.07:46:01.42#ibcon#read 6, iclass 24, count 0 2006.239.07:46:01.42#ibcon#end of sib2, iclass 24, count 0 2006.239.07:46:01.42#ibcon#*after write, iclass 24, count 0 2006.239.07:46:01.42#ibcon#*before return 0, iclass 24, count 0 2006.239.07:46:01.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:46:01.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:46:01.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:46:01.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:46:01.42$vc4f8/vb=3,4 2006.239.07:46:01.42#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.07:46:01.42#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.07:46:01.42#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:01.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:46:01.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:46:01.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:46:01.48#ibcon#enter wrdev, iclass 26, count 2 2006.239.07:46:01.48#ibcon#first serial, iclass 26, count 2 2006.239.07:46:01.48#ibcon#enter sib2, iclass 26, count 2 2006.239.07:46:01.48#ibcon#flushed, iclass 26, count 2 2006.239.07:46:01.48#ibcon#about to write, iclass 26, count 2 2006.239.07:46:01.48#ibcon#wrote, iclass 26, count 2 2006.239.07:46:01.48#ibcon#about to read 3, iclass 26, count 2 2006.239.07:46:01.50#ibcon#read 3, iclass 26, count 2 2006.239.07:46:01.50#ibcon#about to read 4, iclass 26, count 2 2006.239.07:46:01.50#ibcon#read 4, iclass 26, count 2 2006.239.07:46:01.50#ibcon#about to read 5, iclass 26, count 2 2006.239.07:46:01.50#ibcon#read 5, iclass 26, count 2 2006.239.07:46:01.50#ibcon#about to read 6, iclass 26, count 2 2006.239.07:46:01.50#ibcon#read 6, iclass 26, count 2 2006.239.07:46:01.50#ibcon#end of sib2, iclass 26, count 2 2006.239.07:46:01.50#ibcon#*mode == 0, iclass 26, count 2 2006.239.07:46:01.50#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.07:46:01.50#ibcon#[27=AT03-04\r\n] 2006.239.07:46:01.50#ibcon#*before write, iclass 26, count 2 2006.239.07:46:01.50#ibcon#enter sib2, iclass 26, count 2 2006.239.07:46:01.50#ibcon#flushed, iclass 26, count 2 2006.239.07:46:01.50#ibcon#about to write, iclass 26, count 2 2006.239.07:46:01.50#ibcon#wrote, iclass 26, count 2 2006.239.07:46:01.50#ibcon#about to read 3, iclass 26, count 2 2006.239.07:46:01.53#ibcon#read 3, iclass 26, count 2 2006.239.07:46:01.53#ibcon#about to read 4, iclass 26, count 2 2006.239.07:46:01.53#ibcon#read 4, iclass 26, count 2 2006.239.07:46:01.53#ibcon#about to read 5, iclass 26, count 2 2006.239.07:46:01.53#ibcon#read 5, iclass 26, count 2 2006.239.07:46:01.53#ibcon#about to read 6, iclass 26, count 2 2006.239.07:46:01.53#ibcon#read 6, iclass 26, count 2 2006.239.07:46:01.53#ibcon#end of sib2, iclass 26, count 2 2006.239.07:46:01.53#ibcon#*after write, iclass 26, count 2 2006.239.07:46:01.53#ibcon#*before return 0, iclass 26, count 2 2006.239.07:46:01.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:46:01.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:46:01.53#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.07:46:01.53#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:01.53#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:46:01.65#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:46:01.65#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:46:01.65#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:46:01.65#ibcon#first serial, iclass 26, count 0 2006.239.07:46:01.65#ibcon#enter sib2, iclass 26, count 0 2006.239.07:46:01.65#ibcon#flushed, iclass 26, count 0 2006.239.07:46:01.65#ibcon#about to write, iclass 26, count 0 2006.239.07:46:01.65#ibcon#wrote, iclass 26, count 0 2006.239.07:46:01.65#ibcon#about to read 3, iclass 26, count 0 2006.239.07:46:01.67#ibcon#read 3, iclass 26, count 0 2006.239.07:46:01.67#ibcon#about to read 4, iclass 26, count 0 2006.239.07:46:01.67#ibcon#read 4, iclass 26, count 0 2006.239.07:46:01.67#ibcon#about to read 5, iclass 26, count 0 2006.239.07:46:01.67#ibcon#read 5, iclass 26, count 0 2006.239.07:46:01.67#ibcon#about to read 6, iclass 26, count 0 2006.239.07:46:01.67#ibcon#read 6, iclass 26, count 0 2006.239.07:46:01.67#ibcon#end of sib2, iclass 26, count 0 2006.239.07:46:01.67#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:46:01.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:46:01.67#ibcon#[27=USB\r\n] 2006.239.07:46:01.67#ibcon#*before write, iclass 26, count 0 2006.239.07:46:01.67#ibcon#enter sib2, iclass 26, count 0 2006.239.07:46:01.67#ibcon#flushed, iclass 26, count 0 2006.239.07:46:01.67#ibcon#about to write, iclass 26, count 0 2006.239.07:46:01.67#ibcon#wrote, iclass 26, count 0 2006.239.07:46:01.67#ibcon#about to read 3, iclass 26, count 0 2006.239.07:46:01.72#ibcon#read 3, iclass 26, count 0 2006.239.07:46:01.72#ibcon#about to read 4, iclass 26, count 0 2006.239.07:46:01.72#ibcon#read 4, iclass 26, count 0 2006.239.07:46:01.72#ibcon#about to read 5, iclass 26, count 0 2006.239.07:46:01.72#ibcon#read 5, iclass 26, count 0 2006.239.07:46:01.72#ibcon#about to read 6, iclass 26, count 0 2006.239.07:46:01.72#ibcon#read 6, iclass 26, count 0 2006.239.07:46:01.72#ibcon#end of sib2, iclass 26, count 0 2006.239.07:46:01.72#ibcon#*after write, iclass 26, count 0 2006.239.07:46:01.72#ibcon#*before return 0, iclass 26, count 0 2006.239.07:46:01.72#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:46:01.72#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:46:01.72#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:46:01.72#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:46:01.72$vc4f8/vblo=4,712.99 2006.239.07:46:01.72#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.07:46:01.72#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.07:46:01.72#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:01.72#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:46:01.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:46:01.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:46:01.72#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:46:01.72#ibcon#first serial, iclass 28, count 0 2006.239.07:46:01.72#ibcon#enter sib2, iclass 28, count 0 2006.239.07:46:01.72#ibcon#flushed, iclass 28, count 0 2006.239.07:46:01.72#ibcon#about to write, iclass 28, count 0 2006.239.07:46:01.72#ibcon#wrote, iclass 28, count 0 2006.239.07:46:01.72#ibcon#about to read 3, iclass 28, count 0 2006.239.07:46:01.74#ibcon#read 3, iclass 28, count 0 2006.239.07:46:01.74#ibcon#about to read 4, iclass 28, count 0 2006.239.07:46:01.74#ibcon#read 4, iclass 28, count 0 2006.239.07:46:01.74#ibcon#about to read 5, iclass 28, count 0 2006.239.07:46:01.74#ibcon#read 5, iclass 28, count 0 2006.239.07:46:01.74#ibcon#about to read 6, iclass 28, count 0 2006.239.07:46:01.74#ibcon#read 6, iclass 28, count 0 2006.239.07:46:01.74#ibcon#end of sib2, iclass 28, count 0 2006.239.07:46:01.74#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:46:01.74#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:46:01.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:46:01.74#ibcon#*before write, iclass 28, count 0 2006.239.07:46:01.74#ibcon#enter sib2, iclass 28, count 0 2006.239.07:46:01.74#ibcon#flushed, iclass 28, count 0 2006.239.07:46:01.74#ibcon#about to write, iclass 28, count 0 2006.239.07:46:01.74#ibcon#wrote, iclass 28, count 0 2006.239.07:46:01.74#ibcon#about to read 3, iclass 28, count 0 2006.239.07:46:01.78#ibcon#read 3, iclass 28, count 0 2006.239.07:46:01.78#ibcon#about to read 4, iclass 28, count 0 2006.239.07:46:01.78#ibcon#read 4, iclass 28, count 0 2006.239.07:46:01.78#ibcon#about to read 5, iclass 28, count 0 2006.239.07:46:01.78#ibcon#read 5, iclass 28, count 0 2006.239.07:46:01.78#ibcon#about to read 6, iclass 28, count 0 2006.239.07:46:01.78#ibcon#read 6, iclass 28, count 0 2006.239.07:46:01.78#ibcon#end of sib2, iclass 28, count 0 2006.239.07:46:01.78#ibcon#*after write, iclass 28, count 0 2006.239.07:46:01.78#ibcon#*before return 0, iclass 28, count 0 2006.239.07:46:01.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:46:01.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:46:01.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:46:01.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:46:01.78$vc4f8/vb=4,4 2006.239.07:46:01.78#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.07:46:01.78#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.07:46:01.78#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:01.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:46:01.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:46:01.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:46:01.84#ibcon#enter wrdev, iclass 30, count 2 2006.239.07:46:01.84#ibcon#first serial, iclass 30, count 2 2006.239.07:46:01.84#ibcon#enter sib2, iclass 30, count 2 2006.239.07:46:01.84#ibcon#flushed, iclass 30, count 2 2006.239.07:46:01.84#ibcon#about to write, iclass 30, count 2 2006.239.07:46:01.84#ibcon#wrote, iclass 30, count 2 2006.239.07:46:01.84#ibcon#about to read 3, iclass 30, count 2 2006.239.07:46:01.86#ibcon#read 3, iclass 30, count 2 2006.239.07:46:01.86#ibcon#about to read 4, iclass 30, count 2 2006.239.07:46:01.86#ibcon#read 4, iclass 30, count 2 2006.239.07:46:01.86#ibcon#about to read 5, iclass 30, count 2 2006.239.07:46:01.86#ibcon#read 5, iclass 30, count 2 2006.239.07:46:01.86#ibcon#about to read 6, iclass 30, count 2 2006.239.07:46:01.86#ibcon#read 6, iclass 30, count 2 2006.239.07:46:01.86#ibcon#end of sib2, iclass 30, count 2 2006.239.07:46:01.86#ibcon#*mode == 0, iclass 30, count 2 2006.239.07:46:01.86#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.07:46:01.86#ibcon#[27=AT04-04\r\n] 2006.239.07:46:01.86#ibcon#*before write, iclass 30, count 2 2006.239.07:46:01.86#ibcon#enter sib2, iclass 30, count 2 2006.239.07:46:01.86#ibcon#flushed, iclass 30, count 2 2006.239.07:46:01.86#ibcon#about to write, iclass 30, count 2 2006.239.07:46:01.86#ibcon#wrote, iclass 30, count 2 2006.239.07:46:01.86#ibcon#about to read 3, iclass 30, count 2 2006.239.07:46:01.89#ibcon#read 3, iclass 30, count 2 2006.239.07:46:01.89#ibcon#about to read 4, iclass 30, count 2 2006.239.07:46:01.89#ibcon#read 4, iclass 30, count 2 2006.239.07:46:01.89#ibcon#about to read 5, iclass 30, count 2 2006.239.07:46:01.89#ibcon#read 5, iclass 30, count 2 2006.239.07:46:01.89#ibcon#about to read 6, iclass 30, count 2 2006.239.07:46:01.89#ibcon#read 6, iclass 30, count 2 2006.239.07:46:01.89#ibcon#end of sib2, iclass 30, count 2 2006.239.07:46:01.89#ibcon#*after write, iclass 30, count 2 2006.239.07:46:01.89#ibcon#*before return 0, iclass 30, count 2 2006.239.07:46:01.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:46:01.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:46:01.89#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.07:46:01.89#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:01.89#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:46:02.01#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:46:02.01#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:46:02.01#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:46:02.01#ibcon#first serial, iclass 30, count 0 2006.239.07:46:02.01#ibcon#enter sib2, iclass 30, count 0 2006.239.07:46:02.01#ibcon#flushed, iclass 30, count 0 2006.239.07:46:02.01#ibcon#about to write, iclass 30, count 0 2006.239.07:46:02.01#ibcon#wrote, iclass 30, count 0 2006.239.07:46:02.01#ibcon#about to read 3, iclass 30, count 0 2006.239.07:46:02.03#ibcon#read 3, iclass 30, count 0 2006.239.07:46:02.03#ibcon#about to read 4, iclass 30, count 0 2006.239.07:46:02.03#ibcon#read 4, iclass 30, count 0 2006.239.07:46:02.03#ibcon#about to read 5, iclass 30, count 0 2006.239.07:46:02.03#ibcon#read 5, iclass 30, count 0 2006.239.07:46:02.03#ibcon#about to read 6, iclass 30, count 0 2006.239.07:46:02.03#ibcon#read 6, iclass 30, count 0 2006.239.07:46:02.03#ibcon#end of sib2, iclass 30, count 0 2006.239.07:46:02.03#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:46:02.03#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:46:02.03#ibcon#[27=USB\r\n] 2006.239.07:46:02.03#ibcon#*before write, iclass 30, count 0 2006.239.07:46:02.03#ibcon#enter sib2, iclass 30, count 0 2006.239.07:46:02.03#ibcon#flushed, iclass 30, count 0 2006.239.07:46:02.03#ibcon#about to write, iclass 30, count 0 2006.239.07:46:02.03#ibcon#wrote, iclass 30, count 0 2006.239.07:46:02.03#ibcon#about to read 3, iclass 30, count 0 2006.239.07:46:02.06#ibcon#read 3, iclass 30, count 0 2006.239.07:46:02.06#ibcon#about to read 4, iclass 30, count 0 2006.239.07:46:02.06#ibcon#read 4, iclass 30, count 0 2006.239.07:46:02.06#ibcon#about to read 5, iclass 30, count 0 2006.239.07:46:02.06#ibcon#read 5, iclass 30, count 0 2006.239.07:46:02.06#ibcon#about to read 6, iclass 30, count 0 2006.239.07:46:02.06#ibcon#read 6, iclass 30, count 0 2006.239.07:46:02.06#ibcon#end of sib2, iclass 30, count 0 2006.239.07:46:02.06#ibcon#*after write, iclass 30, count 0 2006.239.07:46:02.06#ibcon#*before return 0, iclass 30, count 0 2006.239.07:46:02.06#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:46:02.06#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:46:02.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:46:02.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:46:02.06$vc4f8/vblo=5,744.99 2006.239.07:46:02.06#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.07:46:02.06#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.07:46:02.06#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:02.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:46:02.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:46:02.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:46:02.06#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:46:02.06#ibcon#first serial, iclass 32, count 0 2006.239.07:46:02.06#ibcon#enter sib2, iclass 32, count 0 2006.239.07:46:02.06#ibcon#flushed, iclass 32, count 0 2006.239.07:46:02.06#ibcon#about to write, iclass 32, count 0 2006.239.07:46:02.06#ibcon#wrote, iclass 32, count 0 2006.239.07:46:02.06#ibcon#about to read 3, iclass 32, count 0 2006.239.07:46:02.08#ibcon#read 3, iclass 32, count 0 2006.239.07:46:02.08#ibcon#about to read 4, iclass 32, count 0 2006.239.07:46:02.08#ibcon#read 4, iclass 32, count 0 2006.239.07:46:02.08#ibcon#about to read 5, iclass 32, count 0 2006.239.07:46:02.08#ibcon#read 5, iclass 32, count 0 2006.239.07:46:02.08#ibcon#about to read 6, iclass 32, count 0 2006.239.07:46:02.08#ibcon#read 6, iclass 32, count 0 2006.239.07:46:02.08#ibcon#end of sib2, iclass 32, count 0 2006.239.07:46:02.08#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:46:02.08#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:46:02.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:46:02.08#ibcon#*before write, iclass 32, count 0 2006.239.07:46:02.08#ibcon#enter sib2, iclass 32, count 0 2006.239.07:46:02.08#ibcon#flushed, iclass 32, count 0 2006.239.07:46:02.08#ibcon#about to write, iclass 32, count 0 2006.239.07:46:02.08#ibcon#wrote, iclass 32, count 0 2006.239.07:46:02.08#ibcon#about to read 3, iclass 32, count 0 2006.239.07:46:02.12#ibcon#read 3, iclass 32, count 0 2006.239.07:46:02.12#ibcon#about to read 4, iclass 32, count 0 2006.239.07:46:02.12#ibcon#read 4, iclass 32, count 0 2006.239.07:46:02.12#ibcon#about to read 5, iclass 32, count 0 2006.239.07:46:02.12#ibcon#read 5, iclass 32, count 0 2006.239.07:46:02.12#ibcon#about to read 6, iclass 32, count 0 2006.239.07:46:02.12#ibcon#read 6, iclass 32, count 0 2006.239.07:46:02.12#ibcon#end of sib2, iclass 32, count 0 2006.239.07:46:02.12#ibcon#*after write, iclass 32, count 0 2006.239.07:46:02.12#ibcon#*before return 0, iclass 32, count 0 2006.239.07:46:02.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:46:02.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:46:02.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:46:02.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:46:02.12$vc4f8/vb=5,4 2006.239.07:46:02.12#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.07:46:02.12#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.07:46:02.12#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:02.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:46:02.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:46:02.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:46:02.18#ibcon#enter wrdev, iclass 34, count 2 2006.239.07:46:02.18#ibcon#first serial, iclass 34, count 2 2006.239.07:46:02.18#ibcon#enter sib2, iclass 34, count 2 2006.239.07:46:02.18#ibcon#flushed, iclass 34, count 2 2006.239.07:46:02.18#ibcon#about to write, iclass 34, count 2 2006.239.07:46:02.18#ibcon#wrote, iclass 34, count 2 2006.239.07:46:02.18#ibcon#about to read 3, iclass 34, count 2 2006.239.07:46:02.20#ibcon#read 3, iclass 34, count 2 2006.239.07:46:02.20#ibcon#about to read 4, iclass 34, count 2 2006.239.07:46:02.20#ibcon#read 4, iclass 34, count 2 2006.239.07:46:02.20#ibcon#about to read 5, iclass 34, count 2 2006.239.07:46:02.20#ibcon#read 5, iclass 34, count 2 2006.239.07:46:02.20#ibcon#about to read 6, iclass 34, count 2 2006.239.07:46:02.20#ibcon#read 6, iclass 34, count 2 2006.239.07:46:02.20#ibcon#end of sib2, iclass 34, count 2 2006.239.07:46:02.20#ibcon#*mode == 0, iclass 34, count 2 2006.239.07:46:02.20#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.07:46:02.20#ibcon#[27=AT05-04\r\n] 2006.239.07:46:02.20#ibcon#*before write, iclass 34, count 2 2006.239.07:46:02.20#ibcon#enter sib2, iclass 34, count 2 2006.239.07:46:02.20#ibcon#flushed, iclass 34, count 2 2006.239.07:46:02.20#ibcon#about to write, iclass 34, count 2 2006.239.07:46:02.20#ibcon#wrote, iclass 34, count 2 2006.239.07:46:02.20#ibcon#about to read 3, iclass 34, count 2 2006.239.07:46:02.23#ibcon#read 3, iclass 34, count 2 2006.239.07:46:02.23#ibcon#about to read 4, iclass 34, count 2 2006.239.07:46:02.23#ibcon#read 4, iclass 34, count 2 2006.239.07:46:02.23#ibcon#about to read 5, iclass 34, count 2 2006.239.07:46:02.23#ibcon#read 5, iclass 34, count 2 2006.239.07:46:02.23#ibcon#about to read 6, iclass 34, count 2 2006.239.07:46:02.23#ibcon#read 6, iclass 34, count 2 2006.239.07:46:02.23#ibcon#end of sib2, iclass 34, count 2 2006.239.07:46:02.23#ibcon#*after write, iclass 34, count 2 2006.239.07:46:02.23#ibcon#*before return 0, iclass 34, count 2 2006.239.07:46:02.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:46:02.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:46:02.23#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.07:46:02.23#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:02.23#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:46:02.35#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:46:02.35#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:46:02.35#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:46:02.35#ibcon#first serial, iclass 34, count 0 2006.239.07:46:02.35#ibcon#enter sib2, iclass 34, count 0 2006.239.07:46:02.35#ibcon#flushed, iclass 34, count 0 2006.239.07:46:02.35#ibcon#about to write, iclass 34, count 0 2006.239.07:46:02.35#ibcon#wrote, iclass 34, count 0 2006.239.07:46:02.35#ibcon#about to read 3, iclass 34, count 0 2006.239.07:46:02.37#ibcon#read 3, iclass 34, count 0 2006.239.07:46:02.37#ibcon#about to read 4, iclass 34, count 0 2006.239.07:46:02.37#ibcon#read 4, iclass 34, count 0 2006.239.07:46:02.37#ibcon#about to read 5, iclass 34, count 0 2006.239.07:46:02.37#ibcon#read 5, iclass 34, count 0 2006.239.07:46:02.37#ibcon#about to read 6, iclass 34, count 0 2006.239.07:46:02.37#ibcon#read 6, iclass 34, count 0 2006.239.07:46:02.37#ibcon#end of sib2, iclass 34, count 0 2006.239.07:46:02.37#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:46:02.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:46:02.37#ibcon#[27=USB\r\n] 2006.239.07:46:02.37#ibcon#*before write, iclass 34, count 0 2006.239.07:46:02.37#ibcon#enter sib2, iclass 34, count 0 2006.239.07:46:02.37#ibcon#flushed, iclass 34, count 0 2006.239.07:46:02.37#ibcon#about to write, iclass 34, count 0 2006.239.07:46:02.37#ibcon#wrote, iclass 34, count 0 2006.239.07:46:02.37#ibcon#about to read 3, iclass 34, count 0 2006.239.07:46:02.40#ibcon#read 3, iclass 34, count 0 2006.239.07:46:02.40#ibcon#about to read 4, iclass 34, count 0 2006.239.07:46:02.40#ibcon#read 4, iclass 34, count 0 2006.239.07:46:02.40#ibcon#about to read 5, iclass 34, count 0 2006.239.07:46:02.40#ibcon#read 5, iclass 34, count 0 2006.239.07:46:02.40#ibcon#about to read 6, iclass 34, count 0 2006.239.07:46:02.40#ibcon#read 6, iclass 34, count 0 2006.239.07:46:02.40#ibcon#end of sib2, iclass 34, count 0 2006.239.07:46:02.40#ibcon#*after write, iclass 34, count 0 2006.239.07:46:02.40#ibcon#*before return 0, iclass 34, count 0 2006.239.07:46:02.40#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:46:02.40#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:46:02.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:46:02.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:46:02.40$vc4f8/vblo=6,752.99 2006.239.07:46:02.40#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.07:46:02.40#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.07:46:02.40#ibcon#ireg 17 cls_cnt 0 2006.239.07:46:02.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:46:02.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:46:02.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:46:02.40#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:46:02.40#ibcon#first serial, iclass 36, count 0 2006.239.07:46:02.40#ibcon#enter sib2, iclass 36, count 0 2006.239.07:46:02.40#ibcon#flushed, iclass 36, count 0 2006.239.07:46:02.40#ibcon#about to write, iclass 36, count 0 2006.239.07:46:02.40#ibcon#wrote, iclass 36, count 0 2006.239.07:46:02.40#ibcon#about to read 3, iclass 36, count 0 2006.239.07:46:02.43#ibcon#read 3, iclass 36, count 0 2006.239.07:46:02.43#ibcon#about to read 4, iclass 36, count 0 2006.239.07:46:02.43#ibcon#read 4, iclass 36, count 0 2006.239.07:46:02.43#ibcon#about to read 5, iclass 36, count 0 2006.239.07:46:02.43#ibcon#read 5, iclass 36, count 0 2006.239.07:46:02.43#ibcon#about to read 6, iclass 36, count 0 2006.239.07:46:02.43#ibcon#read 6, iclass 36, count 0 2006.239.07:46:02.43#ibcon#end of sib2, iclass 36, count 0 2006.239.07:46:02.43#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:46:02.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:46:02.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:46:02.43#ibcon#*before write, iclass 36, count 0 2006.239.07:46:02.43#ibcon#enter sib2, iclass 36, count 0 2006.239.07:46:02.43#ibcon#flushed, iclass 36, count 0 2006.239.07:46:02.43#ibcon#about to write, iclass 36, count 0 2006.239.07:46:02.43#ibcon#wrote, iclass 36, count 0 2006.239.07:46:02.43#ibcon#about to read 3, iclass 36, count 0 2006.239.07:46:02.47#ibcon#read 3, iclass 36, count 0 2006.239.07:46:02.47#ibcon#about to read 4, iclass 36, count 0 2006.239.07:46:02.47#ibcon#read 4, iclass 36, count 0 2006.239.07:46:02.47#ibcon#about to read 5, iclass 36, count 0 2006.239.07:46:02.47#ibcon#read 5, iclass 36, count 0 2006.239.07:46:02.47#ibcon#about to read 6, iclass 36, count 0 2006.239.07:46:02.47#ibcon#read 6, iclass 36, count 0 2006.239.07:46:02.47#ibcon#end of sib2, iclass 36, count 0 2006.239.07:46:02.47#ibcon#*after write, iclass 36, count 0 2006.239.07:46:02.47#ibcon#*before return 0, iclass 36, count 0 2006.239.07:46:02.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:46:02.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:46:02.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:46:02.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:46:02.47$vc4f8/vb=6,4 2006.239.07:46:02.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.07:46:02.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.07:46:02.47#ibcon#ireg 11 cls_cnt 2 2006.239.07:46:02.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:46:02.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:46:02.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:46:02.52#ibcon#enter wrdev, iclass 38, count 2 2006.239.07:46:02.52#ibcon#first serial, iclass 38, count 2 2006.239.07:46:02.52#ibcon#enter sib2, iclass 38, count 2 2006.239.07:46:02.52#ibcon#flushed, iclass 38, count 2 2006.239.07:46:02.52#ibcon#about to write, iclass 38, count 2 2006.239.07:46:02.52#ibcon#wrote, iclass 38, count 2 2006.239.07:46:02.52#ibcon#about to read 3, iclass 38, count 2 2006.239.07:46:02.55#ibcon#read 3, iclass 38, count 2 2006.239.07:46:02.55#ibcon#about to read 4, iclass 38, count 2 2006.239.07:46:02.55#ibcon#read 4, iclass 38, count 2 2006.239.07:46:02.55#ibcon#about to read 5, iclass 38, count 2 2006.239.07:46:02.55#ibcon#read 5, iclass 38, count 2 2006.239.07:46:02.55#ibcon#about to read 6, iclass 38, count 2 2006.239.07:46:02.55#ibcon#read 6, iclass 38, count 2 2006.239.07:46:02.55#ibcon#end of sib2, iclass 38, count 2 2006.239.07:46:02.55#ibcon#*mode == 0, iclass 38, count 2 2006.239.07:46:02.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.07:46:02.55#ibcon#[27=AT06-04\r\n] 2006.239.07:46:02.55#ibcon#*before write, iclass 38, count 2 2006.239.07:46:02.55#ibcon#enter sib2, iclass 38, count 2 2006.239.07:46:02.55#ibcon#flushed, iclass 38, count 2 2006.239.07:46:02.55#ibcon#about to write, iclass 38, count 2 2006.239.07:46:02.55#ibcon#wrote, iclass 38, count 2 2006.239.07:46:02.55#ibcon#about to read 3, iclass 38, count 2 2006.239.07:46:02.57#ibcon#read 3, iclass 38, count 2 2006.239.07:46:02.57#ibcon#about to read 4, iclass 38, count 2 2006.239.07:46:02.57#ibcon#read 4, iclass 38, count 2 2006.239.07:46:02.57#ibcon#about to read 5, iclass 38, count 2 2006.239.07:46:02.57#ibcon#read 5, iclass 38, count 2 2006.239.07:46:02.57#ibcon#about to read 6, iclass 38, count 2 2006.239.07:46:02.57#ibcon#read 6, iclass 38, count 2 2006.239.07:46:02.57#ibcon#end of sib2, iclass 38, count 2 2006.239.07:46:02.57#ibcon#*after write, iclass 38, count 2 2006.239.07:46:02.57#ibcon#*before return 0, iclass 38, count 2 2006.239.07:46:02.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:46:02.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:46:02.57#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.07:46:02.58#ibcon#ireg 7 cls_cnt 0 2006.239.07:46:02.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:46:02.68#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:46:02.68#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:46:02.68#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:46:02.68#ibcon#first serial, iclass 38, count 0 2006.239.07:46:02.68#ibcon#enter sib2, iclass 38, count 0 2006.239.07:46:02.68#ibcon#flushed, iclass 38, count 0 2006.239.07:46:02.68#ibcon#about to write, iclass 38, count 0 2006.239.07:46:02.68#ibcon#wrote, iclass 38, count 0 2006.239.07:46:02.68#ibcon#about to read 3, iclass 38, count 0 2006.239.07:46:02.70#ibcon#read 3, iclass 38, count 0 2006.239.07:46:02.70#ibcon#about to read 4, iclass 38, count 0 2006.239.07:46:02.70#ibcon#read 4, iclass 38, count 0 2006.239.07:46:02.70#ibcon#about to read 5, iclass 38, count 0 2006.239.07:46:02.70#ibcon#read 5, iclass 38, count 0 2006.239.07:46:02.70#ibcon#about to read 6, iclass 38, count 0 2006.239.07:46:02.70#ibcon#read 6, iclass 38, count 0 2006.239.07:46:02.70#ibcon#end of sib2, iclass 38, count 0 2006.239.07:46:02.70#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:46:02.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:46:02.70#ibcon#[27=USB\r\n] 2006.239.07:46:02.70#ibcon#*before write, iclass 38, count 0 2006.239.07:46:02.70#ibcon#enter sib2, iclass 38, count 0 2006.239.07:46:02.70#ibcon#flushed, iclass 38, count 0 2006.239.07:46:02.70#ibcon#about to write, iclass 38, count 0 2006.239.07:46:02.70#ibcon#wrote, iclass 38, count 0 2006.239.07:46:02.70#ibcon#about to read 3, iclass 38, count 0 2006.239.07:46:02.73#ibcon#read 3, iclass 38, count 0 2006.239.07:46:02.73#ibcon#about to read 4, iclass 38, count 0 2006.239.07:46:02.73#ibcon#read 4, iclass 38, count 0 2006.239.07:46:02.73#ibcon#about to read 5, iclass 38, count 0 2006.239.07:46:02.73#ibcon#read 5, iclass 38, count 0 2006.239.07:46:02.73#ibcon#about to read 6, iclass 38, count 0 2006.239.07:46:02.73#ibcon#read 6, iclass 38, count 0 2006.239.07:46:02.73#ibcon#end of sib2, iclass 38, count 0 2006.239.07:46:02.73#ibcon#*after write, iclass 38, count 0 2006.239.07:46:02.73#ibcon#*before return 0, iclass 38, count 0 2006.239.07:46:02.73#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:46:02.73#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:46:02.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:46:02.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:46:02.73$vc4f8/vabw=wide 2006.239.07:46:02.73#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:46:02.73#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:46:02.73#ibcon#ireg 8 cls_cnt 0 2006.239.07:46:02.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:46:02.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:46:02.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:46:02.73#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:46:02.73#ibcon#first serial, iclass 40, count 0 2006.239.07:46:02.73#ibcon#enter sib2, iclass 40, count 0 2006.239.07:46:02.73#ibcon#flushed, iclass 40, count 0 2006.239.07:46:02.73#ibcon#about to write, iclass 40, count 0 2006.239.07:46:02.73#ibcon#wrote, iclass 40, count 0 2006.239.07:46:02.73#ibcon#about to read 3, iclass 40, count 0 2006.239.07:46:02.75#ibcon#read 3, iclass 40, count 0 2006.239.07:46:02.75#ibcon#about to read 4, iclass 40, count 0 2006.239.07:46:02.75#ibcon#read 4, iclass 40, count 0 2006.239.07:46:02.75#ibcon#about to read 5, iclass 40, count 0 2006.239.07:46:02.75#ibcon#read 5, iclass 40, count 0 2006.239.07:46:02.75#ibcon#about to read 6, iclass 40, count 0 2006.239.07:46:02.75#ibcon#read 6, iclass 40, count 0 2006.239.07:46:02.75#ibcon#end of sib2, iclass 40, count 0 2006.239.07:46:02.75#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:46:02.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:46:02.75#ibcon#[25=BW32\r\n] 2006.239.07:46:02.75#ibcon#*before write, iclass 40, count 0 2006.239.07:46:02.75#ibcon#enter sib2, iclass 40, count 0 2006.239.07:46:02.75#ibcon#flushed, iclass 40, count 0 2006.239.07:46:02.75#ibcon#about to write, iclass 40, count 0 2006.239.07:46:02.75#ibcon#wrote, iclass 40, count 0 2006.239.07:46:02.75#ibcon#about to read 3, iclass 40, count 0 2006.239.07:46:02.78#ibcon#read 3, iclass 40, count 0 2006.239.07:46:02.78#ibcon#about to read 4, iclass 40, count 0 2006.239.07:46:02.78#ibcon#read 4, iclass 40, count 0 2006.239.07:46:02.78#ibcon#about to read 5, iclass 40, count 0 2006.239.07:46:02.78#ibcon#read 5, iclass 40, count 0 2006.239.07:46:02.78#ibcon#about to read 6, iclass 40, count 0 2006.239.07:46:02.78#ibcon#read 6, iclass 40, count 0 2006.239.07:46:02.78#ibcon#end of sib2, iclass 40, count 0 2006.239.07:46:02.78#ibcon#*after write, iclass 40, count 0 2006.239.07:46:02.78#ibcon#*before return 0, iclass 40, count 0 2006.239.07:46:02.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:46:02.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:46:02.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:46:02.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:46:02.78$vc4f8/vbbw=wide 2006.239.07:46:02.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:46:02.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:46:02.78#ibcon#ireg 8 cls_cnt 0 2006.239.07:46:02.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:46:02.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:46:02.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:46:02.85#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:46:02.85#ibcon#first serial, iclass 4, count 0 2006.239.07:46:02.85#ibcon#enter sib2, iclass 4, count 0 2006.239.07:46:02.85#ibcon#flushed, iclass 4, count 0 2006.239.07:46:02.85#ibcon#about to write, iclass 4, count 0 2006.239.07:46:02.85#ibcon#wrote, iclass 4, count 0 2006.239.07:46:02.85#ibcon#about to read 3, iclass 4, count 0 2006.239.07:46:02.87#ibcon#read 3, iclass 4, count 0 2006.239.07:46:02.87#ibcon#about to read 4, iclass 4, count 0 2006.239.07:46:02.87#ibcon#read 4, iclass 4, count 0 2006.239.07:46:02.87#ibcon#about to read 5, iclass 4, count 0 2006.239.07:46:02.87#ibcon#read 5, iclass 4, count 0 2006.239.07:46:02.87#ibcon#about to read 6, iclass 4, count 0 2006.239.07:46:02.87#ibcon#read 6, iclass 4, count 0 2006.239.07:46:02.87#ibcon#end of sib2, iclass 4, count 0 2006.239.07:46:02.87#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:46:02.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:46:02.87#ibcon#[27=BW32\r\n] 2006.239.07:46:02.87#ibcon#*before write, iclass 4, count 0 2006.239.07:46:02.87#ibcon#enter sib2, iclass 4, count 0 2006.239.07:46:02.87#ibcon#flushed, iclass 4, count 0 2006.239.07:46:02.87#ibcon#about to write, iclass 4, count 0 2006.239.07:46:02.87#ibcon#wrote, iclass 4, count 0 2006.239.07:46:02.87#ibcon#about to read 3, iclass 4, count 0 2006.239.07:46:02.90#ibcon#read 3, iclass 4, count 0 2006.239.07:46:02.90#ibcon#about to read 4, iclass 4, count 0 2006.239.07:46:02.90#ibcon#read 4, iclass 4, count 0 2006.239.07:46:02.90#ibcon#about to read 5, iclass 4, count 0 2006.239.07:46:02.90#ibcon#read 5, iclass 4, count 0 2006.239.07:46:02.90#ibcon#about to read 6, iclass 4, count 0 2006.239.07:46:02.90#ibcon#read 6, iclass 4, count 0 2006.239.07:46:02.90#ibcon#end of sib2, iclass 4, count 0 2006.239.07:46:02.90#ibcon#*after write, iclass 4, count 0 2006.239.07:46:02.90#ibcon#*before return 0, iclass 4, count 0 2006.239.07:46:02.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:46:02.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:46:02.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:46:02.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:46:02.90$4f8m12a/ifd4f 2006.239.07:46:02.90$ifd4f/lo= 2006.239.07:46:02.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:46:02.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:46:02.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:46:02.90$ifd4f/patch= 2006.239.07:46:02.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:46:02.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:46:02.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:46:02.90$4f8m12a/"form=m,16.000,1:2 2006.239.07:46:02.90$4f8m12a/"tpicd 2006.239.07:46:02.90$4f8m12a/echo=off 2006.239.07:46:02.90$4f8m12a/xlog=off 2006.239.07:46:02.90:!2006.239.07:46:30 2006.239.07:46:09.14#trakl#Source acquired 2006.239.07:46:09.14#flagr#flagr/antenna,acquired 2006.239.07:46:30.00:preob 2006.239.07:46:31.14/onsource/TRACKING 2006.239.07:46:31.14:!2006.239.07:46:40 2006.239.07:46:40.00:data_valid=on 2006.239.07:46:40.00:midob 2006.239.07:46:40.14/onsource/TRACKING 2006.239.07:46:40.14/wx/25.30,1011.5,80 2006.239.07:46:40.30/cable/+6.4135E-03 2006.239.07:46:41.39/va/01,08,usb,yes,30,32 2006.239.07:46:41.39/va/02,07,usb,yes,30,32 2006.239.07:46:41.39/va/03,07,usb,yes,29,29 2006.239.07:46:41.39/va/04,07,usb,yes,32,35 2006.239.07:46:41.39/va/05,08,usb,yes,29,31 2006.239.07:46:41.39/va/06,07,usb,yes,32,32 2006.239.07:46:41.39/va/07,07,usb,yes,32,31 2006.239.07:46:41.39/va/08,07,usb,yes,34,34 2006.239.07:46:41.62/valo/01,532.99,yes,locked 2006.239.07:46:41.62/valo/02,572.99,yes,locked 2006.239.07:46:41.62/valo/03,672.99,yes,locked 2006.239.07:46:41.62/valo/04,832.99,yes,locked 2006.239.07:46:41.62/valo/05,652.99,yes,locked 2006.239.07:46:41.62/valo/06,772.99,yes,locked 2006.239.07:46:41.62/valo/07,832.99,yes,locked 2006.239.07:46:41.62/valo/08,852.99,yes,locked 2006.239.07:46:42.71/vb/01,04,usb,yes,39,30 2006.239.07:46:42.71/vb/02,04,usb,yes,45,35 2006.239.07:46:42.71/vb/03,04,usb,yes,29,41 2006.239.07:46:42.71/vb/04,04,usb,yes,29,29 2006.239.07:46:42.71/vb/05,04,usb,yes,28,32 2006.239.07:46:42.71/vb/06,04,usb,yes,28,31 2006.239.07:46:42.71/vb/07,04,usb,yes,31,31 2006.239.07:46:42.71/vb/08,04,usb,yes,28,32 2006.239.07:46:42.94/vblo/01,632.99,yes,locked 2006.239.07:46:42.94/vblo/02,640.99,yes,locked 2006.239.07:46:42.94/vblo/03,656.99,yes,locked 2006.239.07:46:42.94/vblo/04,712.99,yes,locked 2006.239.07:46:42.94/vblo/05,744.99,yes,locked 2006.239.07:46:42.94/vblo/06,752.99,yes,locked 2006.239.07:46:42.94/vblo/07,734.99,yes,locked 2006.239.07:46:42.94/vblo/08,744.99,yes,locked 2006.239.07:46:43.09/vabw/8 2006.239.07:46:43.24/vbbw/8 2006.239.07:46:43.33/xfe/off,on,14.0 2006.239.07:46:43.70/ifatt/23,28,28,28 2006.239.07:46:44.07/fmout-gps/S +4.40E-07 2006.239.07:46:44.11:!2006.239.07:47:40 2006.239.07:47:40.00:data_valid=off 2006.239.07:47:40.00:postob 2006.239.07:47:40.18/cable/+6.4129E-03 2006.239.07:47:40.18/wx/25.29,1011.5,80 2006.239.07:47:41.07/fmout-gps/S +4.40E-07 2006.239.07:47:41.07:scan_name=239-0748,k06239,60 2006.239.07:47:41.07:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.239.07:47:41.14#flagr#flagr/antenna,new-source 2006.239.07:47:42.14:checkk5 2006.239.07:47:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:47:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:47:43.29/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:47:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:47:44.04/chk_obsdata//k5ts1/T2390746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:47:44.42/chk_obsdata//k5ts2/T2390746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:47:44.78/chk_obsdata//k5ts3/T2390746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:47:45.16/chk_obsdata//k5ts4/T2390746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:47:45.85/k5log//k5ts1_log_newline 2006.239.07:47:46.55/k5log//k5ts2_log_newline 2006.239.07:47:47.24/k5log//k5ts3_log_newline 2006.239.07:47:47.94/k5log//k5ts4_log_newline 2006.239.07:47:47.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:47:47.96:4f8m12a=1 2006.239.07:47:47.96$4f8m12a/echo=on 2006.239.07:47:47.96$4f8m12a/pcalon 2006.239.07:47:47.96$pcalon/"no phase cal control is implemented here 2006.239.07:47:47.96$4f8m12a/"tpicd=stop 2006.239.07:47:47.96$4f8m12a/vc4f8 2006.239.07:47:47.96$vc4f8/valo=1,532.99 2006.239.07:47:47.97#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.07:47:47.97#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.07:47:47.97#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:47.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:47.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:47.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:47.97#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:47:47.97#ibcon#first serial, iclass 13, count 0 2006.239.07:47:47.97#ibcon#enter sib2, iclass 13, count 0 2006.239.07:47:47.97#ibcon#flushed, iclass 13, count 0 2006.239.07:47:47.97#ibcon#about to write, iclass 13, count 0 2006.239.07:47:47.97#ibcon#wrote, iclass 13, count 0 2006.239.07:47:47.97#ibcon#about to read 3, iclass 13, count 0 2006.239.07:47:48.01#ibcon#read 3, iclass 13, count 0 2006.239.07:47:48.01#ibcon#about to read 4, iclass 13, count 0 2006.239.07:47:48.01#ibcon#read 4, iclass 13, count 0 2006.239.07:47:48.01#ibcon#about to read 5, iclass 13, count 0 2006.239.07:47:48.01#ibcon#read 5, iclass 13, count 0 2006.239.07:47:48.01#ibcon#about to read 6, iclass 13, count 0 2006.239.07:47:48.01#ibcon#read 6, iclass 13, count 0 2006.239.07:47:48.01#ibcon#end of sib2, iclass 13, count 0 2006.239.07:47:48.01#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:47:48.01#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:47:48.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:47:48.01#ibcon#*before write, iclass 13, count 0 2006.239.07:47:48.01#ibcon#enter sib2, iclass 13, count 0 2006.239.07:47:48.01#ibcon#flushed, iclass 13, count 0 2006.239.07:47:48.01#ibcon#about to write, iclass 13, count 0 2006.239.07:47:48.01#ibcon#wrote, iclass 13, count 0 2006.239.07:47:48.01#ibcon#about to read 3, iclass 13, count 0 2006.239.07:47:48.05#ibcon#read 3, iclass 13, count 0 2006.239.07:47:48.05#ibcon#about to read 4, iclass 13, count 0 2006.239.07:47:48.05#ibcon#read 4, iclass 13, count 0 2006.239.07:47:48.05#ibcon#about to read 5, iclass 13, count 0 2006.239.07:47:48.05#ibcon#read 5, iclass 13, count 0 2006.239.07:47:48.05#ibcon#about to read 6, iclass 13, count 0 2006.239.07:47:48.05#ibcon#read 6, iclass 13, count 0 2006.239.07:47:48.05#ibcon#end of sib2, iclass 13, count 0 2006.239.07:47:48.05#ibcon#*after write, iclass 13, count 0 2006.239.07:47:48.05#ibcon#*before return 0, iclass 13, count 0 2006.239.07:47:48.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:48.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:48.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:47:48.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:47:48.05$vc4f8/va=1,8 2006.239.07:47:48.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.07:47:48.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.07:47:48.05#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:48.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:47:48.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:47:48.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:47:48.05#ibcon#enter wrdev, iclass 15, count 2 2006.239.07:47:48.05#ibcon#first serial, iclass 15, count 2 2006.239.07:47:48.05#ibcon#enter sib2, iclass 15, count 2 2006.239.07:47:48.05#ibcon#flushed, iclass 15, count 2 2006.239.07:47:48.05#ibcon#about to write, iclass 15, count 2 2006.239.07:47:48.05#ibcon#wrote, iclass 15, count 2 2006.239.07:47:48.05#ibcon#about to read 3, iclass 15, count 2 2006.239.07:47:48.07#ibcon#read 3, iclass 15, count 2 2006.239.07:47:48.07#ibcon#about to read 4, iclass 15, count 2 2006.239.07:47:48.07#ibcon#read 4, iclass 15, count 2 2006.239.07:47:48.07#ibcon#about to read 5, iclass 15, count 2 2006.239.07:47:48.07#ibcon#read 5, iclass 15, count 2 2006.239.07:47:48.07#ibcon#about to read 6, iclass 15, count 2 2006.239.07:47:48.07#ibcon#read 6, iclass 15, count 2 2006.239.07:47:48.07#ibcon#end of sib2, iclass 15, count 2 2006.239.07:47:48.07#ibcon#*mode == 0, iclass 15, count 2 2006.239.07:47:48.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.07:47:48.07#ibcon#[25=AT01-08\r\n] 2006.239.07:47:48.07#ibcon#*before write, iclass 15, count 2 2006.239.07:47:48.07#ibcon#enter sib2, iclass 15, count 2 2006.239.07:47:48.07#ibcon#flushed, iclass 15, count 2 2006.239.07:47:48.07#ibcon#about to write, iclass 15, count 2 2006.239.07:47:48.07#ibcon#wrote, iclass 15, count 2 2006.239.07:47:48.07#ibcon#about to read 3, iclass 15, count 2 2006.239.07:47:48.10#ibcon#read 3, iclass 15, count 2 2006.239.07:47:48.10#ibcon#about to read 4, iclass 15, count 2 2006.239.07:47:48.10#ibcon#read 4, iclass 15, count 2 2006.239.07:47:48.10#ibcon#about to read 5, iclass 15, count 2 2006.239.07:47:48.10#ibcon#read 5, iclass 15, count 2 2006.239.07:47:48.10#ibcon#about to read 6, iclass 15, count 2 2006.239.07:47:48.10#ibcon#read 6, iclass 15, count 2 2006.239.07:47:48.10#ibcon#end of sib2, iclass 15, count 2 2006.239.07:47:48.10#ibcon#*after write, iclass 15, count 2 2006.239.07:47:48.10#ibcon#*before return 0, iclass 15, count 2 2006.239.07:47:48.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:47:48.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.07:47:48.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.07:47:48.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:48.11#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:47:48.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:47:48.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:47:48.21#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:47:48.21#ibcon#first serial, iclass 15, count 0 2006.239.07:47:48.21#ibcon#enter sib2, iclass 15, count 0 2006.239.07:47:48.21#ibcon#flushed, iclass 15, count 0 2006.239.07:47:48.21#ibcon#about to write, iclass 15, count 0 2006.239.07:47:48.21#ibcon#wrote, iclass 15, count 0 2006.239.07:47:48.21#ibcon#about to read 3, iclass 15, count 0 2006.239.07:47:48.23#ibcon#read 3, iclass 15, count 0 2006.239.07:47:48.23#ibcon#about to read 4, iclass 15, count 0 2006.239.07:47:48.23#ibcon#read 4, iclass 15, count 0 2006.239.07:47:48.23#ibcon#about to read 5, iclass 15, count 0 2006.239.07:47:48.23#ibcon#read 5, iclass 15, count 0 2006.239.07:47:48.23#ibcon#about to read 6, iclass 15, count 0 2006.239.07:47:48.23#ibcon#read 6, iclass 15, count 0 2006.239.07:47:48.23#ibcon#end of sib2, iclass 15, count 0 2006.239.07:47:48.23#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:47:48.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:47:48.23#ibcon#[25=USB\r\n] 2006.239.07:47:48.23#ibcon#*before write, iclass 15, count 0 2006.239.07:47:48.23#ibcon#enter sib2, iclass 15, count 0 2006.239.07:47:48.23#ibcon#flushed, iclass 15, count 0 2006.239.07:47:48.23#ibcon#about to write, iclass 15, count 0 2006.239.07:47:48.23#ibcon#wrote, iclass 15, count 0 2006.239.07:47:48.23#ibcon#about to read 3, iclass 15, count 0 2006.239.07:47:48.26#ibcon#read 3, iclass 15, count 0 2006.239.07:47:48.26#ibcon#about to read 4, iclass 15, count 0 2006.239.07:47:48.26#ibcon#read 4, iclass 15, count 0 2006.239.07:47:48.26#ibcon#about to read 5, iclass 15, count 0 2006.239.07:47:48.26#ibcon#read 5, iclass 15, count 0 2006.239.07:47:48.26#ibcon#about to read 6, iclass 15, count 0 2006.239.07:47:48.26#ibcon#read 6, iclass 15, count 0 2006.239.07:47:48.26#ibcon#end of sib2, iclass 15, count 0 2006.239.07:47:48.26#ibcon#*after write, iclass 15, count 0 2006.239.07:47:48.26#ibcon#*before return 0, iclass 15, count 0 2006.239.07:47:48.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:47:48.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.07:47:48.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:47:48.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:47:48.26$vc4f8/valo=2,572.99 2006.239.07:47:48.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.07:47:48.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.07:47:48.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:48.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:47:48.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:47:48.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:47:48.26#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:47:48.26#ibcon#first serial, iclass 17, count 0 2006.239.07:47:48.26#ibcon#enter sib2, iclass 17, count 0 2006.239.07:47:48.26#ibcon#flushed, iclass 17, count 0 2006.239.07:47:48.26#ibcon#about to write, iclass 17, count 0 2006.239.07:47:48.26#ibcon#wrote, iclass 17, count 0 2006.239.07:47:48.26#ibcon#about to read 3, iclass 17, count 0 2006.239.07:47:48.28#ibcon#read 3, iclass 17, count 0 2006.239.07:47:48.28#ibcon#about to read 4, iclass 17, count 0 2006.239.07:47:48.28#ibcon#read 4, iclass 17, count 0 2006.239.07:47:48.28#ibcon#about to read 5, iclass 17, count 0 2006.239.07:47:48.28#ibcon#read 5, iclass 17, count 0 2006.239.07:47:48.28#ibcon#about to read 6, iclass 17, count 0 2006.239.07:47:48.28#ibcon#read 6, iclass 17, count 0 2006.239.07:47:48.28#ibcon#end of sib2, iclass 17, count 0 2006.239.07:47:48.28#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:47:48.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:47:48.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:47:48.28#ibcon#*before write, iclass 17, count 0 2006.239.07:47:48.28#ibcon#enter sib2, iclass 17, count 0 2006.239.07:47:48.28#ibcon#flushed, iclass 17, count 0 2006.239.07:47:48.28#ibcon#about to write, iclass 17, count 0 2006.239.07:47:48.29#ibcon#wrote, iclass 17, count 0 2006.239.07:47:48.29#ibcon#about to read 3, iclass 17, count 0 2006.239.07:47:48.32#ibcon#read 3, iclass 17, count 0 2006.239.07:47:48.32#ibcon#about to read 4, iclass 17, count 0 2006.239.07:47:48.32#ibcon#read 4, iclass 17, count 0 2006.239.07:47:48.32#ibcon#about to read 5, iclass 17, count 0 2006.239.07:47:48.32#ibcon#read 5, iclass 17, count 0 2006.239.07:47:48.32#ibcon#about to read 6, iclass 17, count 0 2006.239.07:47:48.32#ibcon#read 6, iclass 17, count 0 2006.239.07:47:48.32#ibcon#end of sib2, iclass 17, count 0 2006.239.07:47:48.32#ibcon#*after write, iclass 17, count 0 2006.239.07:47:48.32#ibcon#*before return 0, iclass 17, count 0 2006.239.07:47:48.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:47:48.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:47:48.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:47:48.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:47:48.32$vc4f8/va=2,7 2006.239.07:47:48.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.07:47:48.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.07:47:48.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:48.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:47:48.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:47:48.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:47:48.38#ibcon#enter wrdev, iclass 19, count 2 2006.239.07:47:48.38#ibcon#first serial, iclass 19, count 2 2006.239.07:47:48.38#ibcon#enter sib2, iclass 19, count 2 2006.239.07:47:48.38#ibcon#flushed, iclass 19, count 2 2006.239.07:47:48.38#ibcon#about to write, iclass 19, count 2 2006.239.07:47:48.38#ibcon#wrote, iclass 19, count 2 2006.239.07:47:48.38#ibcon#about to read 3, iclass 19, count 2 2006.239.07:47:48.40#ibcon#read 3, iclass 19, count 2 2006.239.07:47:48.40#ibcon#about to read 4, iclass 19, count 2 2006.239.07:47:48.40#ibcon#read 4, iclass 19, count 2 2006.239.07:47:48.40#ibcon#about to read 5, iclass 19, count 2 2006.239.07:47:48.40#ibcon#read 5, iclass 19, count 2 2006.239.07:47:48.40#ibcon#about to read 6, iclass 19, count 2 2006.239.07:47:48.40#ibcon#read 6, iclass 19, count 2 2006.239.07:47:48.40#ibcon#end of sib2, iclass 19, count 2 2006.239.07:47:48.40#ibcon#*mode == 0, iclass 19, count 2 2006.239.07:47:48.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.07:47:48.40#ibcon#[25=AT02-07\r\n] 2006.239.07:47:48.40#ibcon#*before write, iclass 19, count 2 2006.239.07:47:48.40#ibcon#enter sib2, iclass 19, count 2 2006.239.07:47:48.40#ibcon#flushed, iclass 19, count 2 2006.239.07:47:48.40#ibcon#about to write, iclass 19, count 2 2006.239.07:47:48.40#ibcon#wrote, iclass 19, count 2 2006.239.07:47:48.40#ibcon#about to read 3, iclass 19, count 2 2006.239.07:47:48.43#ibcon#read 3, iclass 19, count 2 2006.239.07:47:48.43#ibcon#about to read 4, iclass 19, count 2 2006.239.07:47:48.43#ibcon#read 4, iclass 19, count 2 2006.239.07:47:48.43#ibcon#about to read 5, iclass 19, count 2 2006.239.07:47:48.43#ibcon#read 5, iclass 19, count 2 2006.239.07:47:48.43#ibcon#about to read 6, iclass 19, count 2 2006.239.07:47:48.43#ibcon#read 6, iclass 19, count 2 2006.239.07:47:48.43#ibcon#end of sib2, iclass 19, count 2 2006.239.07:47:48.43#ibcon#*after write, iclass 19, count 2 2006.239.07:47:48.43#ibcon#*before return 0, iclass 19, count 2 2006.239.07:47:48.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:47:48.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:47:48.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.07:47:48.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:48.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:47:48.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:47:48.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:47:48.56#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:47:48.56#ibcon#first serial, iclass 19, count 0 2006.239.07:47:48.56#ibcon#enter sib2, iclass 19, count 0 2006.239.07:47:48.56#ibcon#flushed, iclass 19, count 0 2006.239.07:47:48.56#ibcon#about to write, iclass 19, count 0 2006.239.07:47:48.56#ibcon#wrote, iclass 19, count 0 2006.239.07:47:48.56#ibcon#about to read 3, iclass 19, count 0 2006.239.07:47:48.57#ibcon#read 3, iclass 19, count 0 2006.239.07:47:48.57#ibcon#about to read 4, iclass 19, count 0 2006.239.07:47:48.57#ibcon#read 4, iclass 19, count 0 2006.239.07:47:48.57#ibcon#about to read 5, iclass 19, count 0 2006.239.07:47:48.57#ibcon#read 5, iclass 19, count 0 2006.239.07:47:48.57#ibcon#about to read 6, iclass 19, count 0 2006.239.07:47:48.57#ibcon#read 6, iclass 19, count 0 2006.239.07:47:48.57#ibcon#end of sib2, iclass 19, count 0 2006.239.07:47:48.57#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:47:48.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:47:48.57#ibcon#[25=USB\r\n] 2006.239.07:47:48.57#ibcon#*before write, iclass 19, count 0 2006.239.07:47:48.57#ibcon#enter sib2, iclass 19, count 0 2006.239.07:47:48.57#ibcon#flushed, iclass 19, count 0 2006.239.07:47:48.57#ibcon#about to write, iclass 19, count 0 2006.239.07:47:48.57#ibcon#wrote, iclass 19, count 0 2006.239.07:47:48.57#ibcon#about to read 3, iclass 19, count 0 2006.239.07:47:48.60#ibcon#read 3, iclass 19, count 0 2006.239.07:47:48.60#ibcon#about to read 4, iclass 19, count 0 2006.239.07:47:48.60#ibcon#read 4, iclass 19, count 0 2006.239.07:47:48.60#ibcon#about to read 5, iclass 19, count 0 2006.239.07:47:48.60#ibcon#read 5, iclass 19, count 0 2006.239.07:47:48.60#ibcon#about to read 6, iclass 19, count 0 2006.239.07:47:48.60#ibcon#read 6, iclass 19, count 0 2006.239.07:47:48.60#ibcon#end of sib2, iclass 19, count 0 2006.239.07:47:48.60#ibcon#*after write, iclass 19, count 0 2006.239.07:47:48.60#ibcon#*before return 0, iclass 19, count 0 2006.239.07:47:48.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:47:48.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:47:48.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:47:48.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:47:48.60$vc4f8/valo=3,672.99 2006.239.07:47:48.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.07:47:48.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.07:47:48.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:48.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:48.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:48.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:48.60#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:47:48.60#ibcon#first serial, iclass 21, count 0 2006.239.07:47:48.60#ibcon#enter sib2, iclass 21, count 0 2006.239.07:47:48.60#ibcon#flushed, iclass 21, count 0 2006.239.07:47:48.60#ibcon#about to write, iclass 21, count 0 2006.239.07:47:48.60#ibcon#wrote, iclass 21, count 0 2006.239.07:47:48.60#ibcon#about to read 3, iclass 21, count 0 2006.239.07:47:48.62#ibcon#read 3, iclass 21, count 0 2006.239.07:47:48.62#ibcon#about to read 4, iclass 21, count 0 2006.239.07:47:48.62#ibcon#read 4, iclass 21, count 0 2006.239.07:47:48.62#ibcon#about to read 5, iclass 21, count 0 2006.239.07:47:48.62#ibcon#read 5, iclass 21, count 0 2006.239.07:47:48.62#ibcon#about to read 6, iclass 21, count 0 2006.239.07:47:48.62#ibcon#read 6, iclass 21, count 0 2006.239.07:47:48.62#ibcon#end of sib2, iclass 21, count 0 2006.239.07:47:48.62#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:47:48.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:47:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:47:48.62#ibcon#*before write, iclass 21, count 0 2006.239.07:47:48.62#ibcon#enter sib2, iclass 21, count 0 2006.239.07:47:48.62#ibcon#flushed, iclass 21, count 0 2006.239.07:47:48.62#ibcon#about to write, iclass 21, count 0 2006.239.07:47:48.62#ibcon#wrote, iclass 21, count 0 2006.239.07:47:48.62#ibcon#about to read 3, iclass 21, count 0 2006.239.07:47:48.66#ibcon#read 3, iclass 21, count 0 2006.239.07:47:48.66#ibcon#about to read 4, iclass 21, count 0 2006.239.07:47:48.66#ibcon#read 4, iclass 21, count 0 2006.239.07:47:48.66#ibcon#about to read 5, iclass 21, count 0 2006.239.07:47:48.66#ibcon#read 5, iclass 21, count 0 2006.239.07:47:48.66#ibcon#about to read 6, iclass 21, count 0 2006.239.07:47:48.66#ibcon#read 6, iclass 21, count 0 2006.239.07:47:48.66#ibcon#end of sib2, iclass 21, count 0 2006.239.07:47:48.66#ibcon#*after write, iclass 21, count 0 2006.239.07:47:48.66#ibcon#*before return 0, iclass 21, count 0 2006.239.07:47:48.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:48.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:48.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:47:48.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:47:48.66$vc4f8/va=3,7 2006.239.07:47:48.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.07:47:48.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.07:47:48.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:48.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:48.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:48.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:48.72#ibcon#enter wrdev, iclass 23, count 2 2006.239.07:47:48.72#ibcon#first serial, iclass 23, count 2 2006.239.07:47:48.72#ibcon#enter sib2, iclass 23, count 2 2006.239.07:47:48.72#ibcon#flushed, iclass 23, count 2 2006.239.07:47:48.72#ibcon#about to write, iclass 23, count 2 2006.239.07:47:48.72#ibcon#wrote, iclass 23, count 2 2006.239.07:47:48.72#ibcon#about to read 3, iclass 23, count 2 2006.239.07:47:48.74#ibcon#read 3, iclass 23, count 2 2006.239.07:47:48.74#ibcon#about to read 4, iclass 23, count 2 2006.239.07:47:48.74#ibcon#read 4, iclass 23, count 2 2006.239.07:47:48.74#ibcon#about to read 5, iclass 23, count 2 2006.239.07:47:48.74#ibcon#read 5, iclass 23, count 2 2006.239.07:47:48.74#ibcon#about to read 6, iclass 23, count 2 2006.239.07:47:48.74#ibcon#read 6, iclass 23, count 2 2006.239.07:47:48.74#ibcon#end of sib2, iclass 23, count 2 2006.239.07:47:48.74#ibcon#*mode == 0, iclass 23, count 2 2006.239.07:47:48.74#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.07:47:48.74#ibcon#[25=AT03-07\r\n] 2006.239.07:47:48.74#ibcon#*before write, iclass 23, count 2 2006.239.07:47:48.74#ibcon#enter sib2, iclass 23, count 2 2006.239.07:47:48.74#ibcon#flushed, iclass 23, count 2 2006.239.07:47:48.74#ibcon#about to write, iclass 23, count 2 2006.239.07:47:48.74#ibcon#wrote, iclass 23, count 2 2006.239.07:47:48.74#ibcon#about to read 3, iclass 23, count 2 2006.239.07:47:48.77#ibcon#read 3, iclass 23, count 2 2006.239.07:47:48.77#ibcon#about to read 4, iclass 23, count 2 2006.239.07:47:48.77#ibcon#read 4, iclass 23, count 2 2006.239.07:47:48.77#ibcon#about to read 5, iclass 23, count 2 2006.239.07:47:48.77#ibcon#read 5, iclass 23, count 2 2006.239.07:47:48.77#ibcon#about to read 6, iclass 23, count 2 2006.239.07:47:48.77#ibcon#read 6, iclass 23, count 2 2006.239.07:47:48.77#ibcon#end of sib2, iclass 23, count 2 2006.239.07:47:48.77#ibcon#*after write, iclass 23, count 2 2006.239.07:47:48.77#ibcon#*before return 0, iclass 23, count 2 2006.239.07:47:48.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:48.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:48.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.07:47:48.77#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:48.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:48.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:48.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:48.89#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:47:48.89#ibcon#first serial, iclass 23, count 0 2006.239.07:47:48.89#ibcon#enter sib2, iclass 23, count 0 2006.239.07:47:48.89#ibcon#flushed, iclass 23, count 0 2006.239.07:47:48.89#ibcon#about to write, iclass 23, count 0 2006.239.07:47:48.89#ibcon#wrote, iclass 23, count 0 2006.239.07:47:48.89#ibcon#about to read 3, iclass 23, count 0 2006.239.07:47:48.91#ibcon#read 3, iclass 23, count 0 2006.239.07:47:48.91#ibcon#about to read 4, iclass 23, count 0 2006.239.07:47:48.91#ibcon#read 4, iclass 23, count 0 2006.239.07:47:48.91#ibcon#about to read 5, iclass 23, count 0 2006.239.07:47:48.91#ibcon#read 5, iclass 23, count 0 2006.239.07:47:48.91#ibcon#about to read 6, iclass 23, count 0 2006.239.07:47:48.91#ibcon#read 6, iclass 23, count 0 2006.239.07:47:48.91#ibcon#end of sib2, iclass 23, count 0 2006.239.07:47:48.91#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:47:48.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:47:48.91#ibcon#[25=USB\r\n] 2006.239.07:47:48.91#ibcon#*before write, iclass 23, count 0 2006.239.07:47:48.91#ibcon#enter sib2, iclass 23, count 0 2006.239.07:47:48.91#ibcon#flushed, iclass 23, count 0 2006.239.07:47:48.91#ibcon#about to write, iclass 23, count 0 2006.239.07:47:48.91#ibcon#wrote, iclass 23, count 0 2006.239.07:47:48.91#ibcon#about to read 3, iclass 23, count 0 2006.239.07:47:48.94#ibcon#read 3, iclass 23, count 0 2006.239.07:47:48.94#ibcon#about to read 4, iclass 23, count 0 2006.239.07:47:48.94#ibcon#read 4, iclass 23, count 0 2006.239.07:47:48.94#ibcon#about to read 5, iclass 23, count 0 2006.239.07:47:48.94#ibcon#read 5, iclass 23, count 0 2006.239.07:47:48.94#ibcon#about to read 6, iclass 23, count 0 2006.239.07:47:48.94#ibcon#read 6, iclass 23, count 0 2006.239.07:47:48.94#ibcon#end of sib2, iclass 23, count 0 2006.239.07:47:48.94#ibcon#*after write, iclass 23, count 0 2006.239.07:47:48.94#ibcon#*before return 0, iclass 23, count 0 2006.239.07:47:48.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:48.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:48.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:47:48.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:47:48.94$vc4f8/valo=4,832.99 2006.239.07:47:48.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:47:48.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:47:48.94#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:48.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:48.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:48.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:48.94#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:47:48.94#ibcon#first serial, iclass 25, count 0 2006.239.07:47:48.94#ibcon#enter sib2, iclass 25, count 0 2006.239.07:47:48.94#ibcon#flushed, iclass 25, count 0 2006.239.07:47:48.94#ibcon#about to write, iclass 25, count 0 2006.239.07:47:48.94#ibcon#wrote, iclass 25, count 0 2006.239.07:47:48.94#ibcon#about to read 3, iclass 25, count 0 2006.239.07:47:48.96#ibcon#read 3, iclass 25, count 0 2006.239.07:47:48.96#ibcon#about to read 4, iclass 25, count 0 2006.239.07:47:48.96#ibcon#read 4, iclass 25, count 0 2006.239.07:47:48.96#ibcon#about to read 5, iclass 25, count 0 2006.239.07:47:48.96#ibcon#read 5, iclass 25, count 0 2006.239.07:47:48.96#ibcon#about to read 6, iclass 25, count 0 2006.239.07:47:48.96#ibcon#read 6, iclass 25, count 0 2006.239.07:47:48.96#ibcon#end of sib2, iclass 25, count 0 2006.239.07:47:48.96#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:47:48.96#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:47:48.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:47:48.96#ibcon#*before write, iclass 25, count 0 2006.239.07:47:48.96#ibcon#enter sib2, iclass 25, count 0 2006.239.07:47:48.96#ibcon#flushed, iclass 25, count 0 2006.239.07:47:48.96#ibcon#about to write, iclass 25, count 0 2006.239.07:47:48.96#ibcon#wrote, iclass 25, count 0 2006.239.07:47:48.96#ibcon#about to read 3, iclass 25, count 0 2006.239.07:47:49.00#ibcon#read 3, iclass 25, count 0 2006.239.07:47:49.00#ibcon#about to read 4, iclass 25, count 0 2006.239.07:47:49.00#ibcon#read 4, iclass 25, count 0 2006.239.07:47:49.00#ibcon#about to read 5, iclass 25, count 0 2006.239.07:47:49.00#ibcon#read 5, iclass 25, count 0 2006.239.07:47:49.00#ibcon#about to read 6, iclass 25, count 0 2006.239.07:47:49.00#ibcon#read 6, iclass 25, count 0 2006.239.07:47:49.00#ibcon#end of sib2, iclass 25, count 0 2006.239.07:47:49.00#ibcon#*after write, iclass 25, count 0 2006.239.07:47:49.00#ibcon#*before return 0, iclass 25, count 0 2006.239.07:47:49.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:49.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:49.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:47:49.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:47:49.00$vc4f8/va=4,7 2006.239.07:47:49.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:47:49.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:47:49.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:49.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:49.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:49.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:49.06#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:47:49.06#ibcon#first serial, iclass 27, count 2 2006.239.07:47:49.06#ibcon#enter sib2, iclass 27, count 2 2006.239.07:47:49.06#ibcon#flushed, iclass 27, count 2 2006.239.07:47:49.06#ibcon#about to write, iclass 27, count 2 2006.239.07:47:49.06#ibcon#wrote, iclass 27, count 2 2006.239.07:47:49.06#ibcon#about to read 3, iclass 27, count 2 2006.239.07:47:49.08#ibcon#read 3, iclass 27, count 2 2006.239.07:47:49.08#ibcon#about to read 4, iclass 27, count 2 2006.239.07:47:49.08#ibcon#read 4, iclass 27, count 2 2006.239.07:47:49.08#ibcon#about to read 5, iclass 27, count 2 2006.239.07:47:49.08#ibcon#read 5, iclass 27, count 2 2006.239.07:47:49.08#ibcon#about to read 6, iclass 27, count 2 2006.239.07:47:49.08#ibcon#read 6, iclass 27, count 2 2006.239.07:47:49.08#ibcon#end of sib2, iclass 27, count 2 2006.239.07:47:49.08#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:47:49.08#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:47:49.08#ibcon#[25=AT04-07\r\n] 2006.239.07:47:49.08#ibcon#*before write, iclass 27, count 2 2006.239.07:47:49.08#ibcon#enter sib2, iclass 27, count 2 2006.239.07:47:49.08#ibcon#flushed, iclass 27, count 2 2006.239.07:47:49.08#ibcon#about to write, iclass 27, count 2 2006.239.07:47:49.08#ibcon#wrote, iclass 27, count 2 2006.239.07:47:49.08#ibcon#about to read 3, iclass 27, count 2 2006.239.07:47:49.11#ibcon#read 3, iclass 27, count 2 2006.239.07:47:49.11#ibcon#about to read 4, iclass 27, count 2 2006.239.07:47:49.11#ibcon#read 4, iclass 27, count 2 2006.239.07:47:49.11#ibcon#about to read 5, iclass 27, count 2 2006.239.07:47:49.11#ibcon#read 5, iclass 27, count 2 2006.239.07:47:49.11#ibcon#about to read 6, iclass 27, count 2 2006.239.07:47:49.11#ibcon#read 6, iclass 27, count 2 2006.239.07:47:49.11#ibcon#end of sib2, iclass 27, count 2 2006.239.07:47:49.11#ibcon#*after write, iclass 27, count 2 2006.239.07:47:49.11#ibcon#*before return 0, iclass 27, count 2 2006.239.07:47:49.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:49.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:49.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:47:49.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:49.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:49.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:49.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:49.23#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:47:49.23#ibcon#first serial, iclass 27, count 0 2006.239.07:47:49.23#ibcon#enter sib2, iclass 27, count 0 2006.239.07:47:49.23#ibcon#flushed, iclass 27, count 0 2006.239.07:47:49.23#ibcon#about to write, iclass 27, count 0 2006.239.07:47:49.23#ibcon#wrote, iclass 27, count 0 2006.239.07:47:49.23#ibcon#about to read 3, iclass 27, count 0 2006.239.07:47:49.25#ibcon#read 3, iclass 27, count 0 2006.239.07:47:49.25#ibcon#about to read 4, iclass 27, count 0 2006.239.07:47:49.25#ibcon#read 4, iclass 27, count 0 2006.239.07:47:49.25#ibcon#about to read 5, iclass 27, count 0 2006.239.07:47:49.25#ibcon#read 5, iclass 27, count 0 2006.239.07:47:49.25#ibcon#about to read 6, iclass 27, count 0 2006.239.07:47:49.25#ibcon#read 6, iclass 27, count 0 2006.239.07:47:49.25#ibcon#end of sib2, iclass 27, count 0 2006.239.07:47:49.25#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:47:49.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:47:49.25#ibcon#[25=USB\r\n] 2006.239.07:47:49.25#ibcon#*before write, iclass 27, count 0 2006.239.07:47:49.25#ibcon#enter sib2, iclass 27, count 0 2006.239.07:47:49.25#ibcon#flushed, iclass 27, count 0 2006.239.07:47:49.25#ibcon#about to write, iclass 27, count 0 2006.239.07:47:49.25#ibcon#wrote, iclass 27, count 0 2006.239.07:47:49.25#ibcon#about to read 3, iclass 27, count 0 2006.239.07:47:49.28#ibcon#read 3, iclass 27, count 0 2006.239.07:47:49.28#ibcon#about to read 4, iclass 27, count 0 2006.239.07:47:49.28#ibcon#read 4, iclass 27, count 0 2006.239.07:47:49.28#ibcon#about to read 5, iclass 27, count 0 2006.239.07:47:49.28#ibcon#read 5, iclass 27, count 0 2006.239.07:47:49.28#ibcon#about to read 6, iclass 27, count 0 2006.239.07:47:49.28#ibcon#read 6, iclass 27, count 0 2006.239.07:47:49.28#ibcon#end of sib2, iclass 27, count 0 2006.239.07:47:49.28#ibcon#*after write, iclass 27, count 0 2006.239.07:47:49.28#ibcon#*before return 0, iclass 27, count 0 2006.239.07:47:49.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:49.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:49.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:47:49.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:47:49.28$vc4f8/valo=5,652.99 2006.239.07:47:49.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:47:49.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:47:49.28#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:49.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:49.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:49.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:49.28#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:47:49.28#ibcon#first serial, iclass 29, count 0 2006.239.07:47:49.28#ibcon#enter sib2, iclass 29, count 0 2006.239.07:47:49.28#ibcon#flushed, iclass 29, count 0 2006.239.07:47:49.28#ibcon#about to write, iclass 29, count 0 2006.239.07:47:49.28#ibcon#wrote, iclass 29, count 0 2006.239.07:47:49.28#ibcon#about to read 3, iclass 29, count 0 2006.239.07:47:49.30#ibcon#read 3, iclass 29, count 0 2006.239.07:47:49.30#ibcon#about to read 4, iclass 29, count 0 2006.239.07:47:49.30#ibcon#read 4, iclass 29, count 0 2006.239.07:47:49.30#ibcon#about to read 5, iclass 29, count 0 2006.239.07:47:49.30#ibcon#read 5, iclass 29, count 0 2006.239.07:47:49.30#ibcon#about to read 6, iclass 29, count 0 2006.239.07:47:49.30#ibcon#read 6, iclass 29, count 0 2006.239.07:47:49.30#ibcon#end of sib2, iclass 29, count 0 2006.239.07:47:49.30#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:47:49.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:47:49.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:47:49.30#ibcon#*before write, iclass 29, count 0 2006.239.07:47:49.30#ibcon#enter sib2, iclass 29, count 0 2006.239.07:47:49.30#ibcon#flushed, iclass 29, count 0 2006.239.07:47:49.30#ibcon#about to write, iclass 29, count 0 2006.239.07:47:49.30#ibcon#wrote, iclass 29, count 0 2006.239.07:47:49.30#ibcon#about to read 3, iclass 29, count 0 2006.239.07:47:49.34#ibcon#read 3, iclass 29, count 0 2006.239.07:47:49.34#ibcon#about to read 4, iclass 29, count 0 2006.239.07:47:49.34#ibcon#read 4, iclass 29, count 0 2006.239.07:47:49.34#ibcon#about to read 5, iclass 29, count 0 2006.239.07:47:49.34#ibcon#read 5, iclass 29, count 0 2006.239.07:47:49.34#ibcon#about to read 6, iclass 29, count 0 2006.239.07:47:49.34#ibcon#read 6, iclass 29, count 0 2006.239.07:47:49.34#ibcon#end of sib2, iclass 29, count 0 2006.239.07:47:49.34#ibcon#*after write, iclass 29, count 0 2006.239.07:47:49.34#ibcon#*before return 0, iclass 29, count 0 2006.239.07:47:49.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:49.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:49.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:47:49.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:47:49.34$vc4f8/va=5,8 2006.239.07:47:49.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:47:49.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:47:49.34#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:49.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:49.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:49.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:49.40#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:47:49.40#ibcon#first serial, iclass 31, count 2 2006.239.07:47:49.40#ibcon#enter sib2, iclass 31, count 2 2006.239.07:47:49.40#ibcon#flushed, iclass 31, count 2 2006.239.07:47:49.40#ibcon#about to write, iclass 31, count 2 2006.239.07:47:49.40#ibcon#wrote, iclass 31, count 2 2006.239.07:47:49.40#ibcon#about to read 3, iclass 31, count 2 2006.239.07:47:49.42#ibcon#read 3, iclass 31, count 2 2006.239.07:47:49.42#ibcon#about to read 4, iclass 31, count 2 2006.239.07:47:49.42#ibcon#read 4, iclass 31, count 2 2006.239.07:47:49.42#ibcon#about to read 5, iclass 31, count 2 2006.239.07:47:49.42#ibcon#read 5, iclass 31, count 2 2006.239.07:47:49.42#ibcon#about to read 6, iclass 31, count 2 2006.239.07:47:49.42#ibcon#read 6, iclass 31, count 2 2006.239.07:47:49.42#ibcon#end of sib2, iclass 31, count 2 2006.239.07:47:49.42#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:47:49.42#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:47:49.42#ibcon#[25=AT05-08\r\n] 2006.239.07:47:49.42#ibcon#*before write, iclass 31, count 2 2006.239.07:47:49.42#ibcon#enter sib2, iclass 31, count 2 2006.239.07:47:49.42#ibcon#flushed, iclass 31, count 2 2006.239.07:47:49.42#ibcon#about to write, iclass 31, count 2 2006.239.07:47:49.42#ibcon#wrote, iclass 31, count 2 2006.239.07:47:49.42#ibcon#about to read 3, iclass 31, count 2 2006.239.07:47:49.45#ibcon#read 3, iclass 31, count 2 2006.239.07:47:49.45#ibcon#about to read 4, iclass 31, count 2 2006.239.07:47:49.45#ibcon#read 4, iclass 31, count 2 2006.239.07:47:49.45#ibcon#about to read 5, iclass 31, count 2 2006.239.07:47:49.45#ibcon#read 5, iclass 31, count 2 2006.239.07:47:49.45#ibcon#about to read 6, iclass 31, count 2 2006.239.07:47:49.45#ibcon#read 6, iclass 31, count 2 2006.239.07:47:49.45#ibcon#end of sib2, iclass 31, count 2 2006.239.07:47:49.45#ibcon#*after write, iclass 31, count 2 2006.239.07:47:49.45#ibcon#*before return 0, iclass 31, count 2 2006.239.07:47:49.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:49.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:49.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:47:49.45#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:49.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:49.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:49.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:49.57#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:47:49.57#ibcon#first serial, iclass 31, count 0 2006.239.07:47:49.57#ibcon#enter sib2, iclass 31, count 0 2006.239.07:47:49.57#ibcon#flushed, iclass 31, count 0 2006.239.07:47:49.57#ibcon#about to write, iclass 31, count 0 2006.239.07:47:49.57#ibcon#wrote, iclass 31, count 0 2006.239.07:47:49.57#ibcon#about to read 3, iclass 31, count 0 2006.239.07:47:49.59#ibcon#read 3, iclass 31, count 0 2006.239.07:47:49.59#ibcon#about to read 4, iclass 31, count 0 2006.239.07:47:49.59#ibcon#read 4, iclass 31, count 0 2006.239.07:47:49.59#ibcon#about to read 5, iclass 31, count 0 2006.239.07:47:49.59#ibcon#read 5, iclass 31, count 0 2006.239.07:47:49.59#ibcon#about to read 6, iclass 31, count 0 2006.239.07:47:49.59#ibcon#read 6, iclass 31, count 0 2006.239.07:47:49.59#ibcon#end of sib2, iclass 31, count 0 2006.239.07:47:49.59#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:47:49.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:47:49.59#ibcon#[25=USB\r\n] 2006.239.07:47:49.59#ibcon#*before write, iclass 31, count 0 2006.239.07:47:49.59#ibcon#enter sib2, iclass 31, count 0 2006.239.07:47:49.59#ibcon#flushed, iclass 31, count 0 2006.239.07:47:49.59#ibcon#about to write, iclass 31, count 0 2006.239.07:47:49.59#ibcon#wrote, iclass 31, count 0 2006.239.07:47:49.59#ibcon#about to read 3, iclass 31, count 0 2006.239.07:47:49.62#ibcon#read 3, iclass 31, count 0 2006.239.07:47:49.62#ibcon#about to read 4, iclass 31, count 0 2006.239.07:47:49.62#ibcon#read 4, iclass 31, count 0 2006.239.07:47:49.62#ibcon#about to read 5, iclass 31, count 0 2006.239.07:47:49.62#ibcon#read 5, iclass 31, count 0 2006.239.07:47:49.62#ibcon#about to read 6, iclass 31, count 0 2006.239.07:47:49.62#ibcon#read 6, iclass 31, count 0 2006.239.07:47:49.62#ibcon#end of sib2, iclass 31, count 0 2006.239.07:47:49.62#ibcon#*after write, iclass 31, count 0 2006.239.07:47:49.62#ibcon#*before return 0, iclass 31, count 0 2006.239.07:47:49.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:49.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:49.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:47:49.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:47:49.62$vc4f8/valo=6,772.99 2006.239.07:47:49.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:47:49.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:47:49.62#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:49.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:49.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:49.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:49.62#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:47:49.62#ibcon#first serial, iclass 33, count 0 2006.239.07:47:49.62#ibcon#enter sib2, iclass 33, count 0 2006.239.07:47:49.62#ibcon#flushed, iclass 33, count 0 2006.239.07:47:49.62#ibcon#about to write, iclass 33, count 0 2006.239.07:47:49.62#ibcon#wrote, iclass 33, count 0 2006.239.07:47:49.62#ibcon#about to read 3, iclass 33, count 0 2006.239.07:47:49.66#ibcon#read 3, iclass 33, count 0 2006.239.07:47:49.66#ibcon#about to read 4, iclass 33, count 0 2006.239.07:47:49.66#ibcon#read 4, iclass 33, count 0 2006.239.07:47:49.66#ibcon#about to read 5, iclass 33, count 0 2006.239.07:47:49.66#ibcon#read 5, iclass 33, count 0 2006.239.07:47:49.66#ibcon#about to read 6, iclass 33, count 0 2006.239.07:47:49.66#ibcon#read 6, iclass 33, count 0 2006.239.07:47:49.66#ibcon#end of sib2, iclass 33, count 0 2006.239.07:47:49.66#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:47:49.66#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:47:49.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:47:49.66#ibcon#*before write, iclass 33, count 0 2006.239.07:47:49.66#ibcon#enter sib2, iclass 33, count 0 2006.239.07:47:49.66#ibcon#flushed, iclass 33, count 0 2006.239.07:47:49.66#ibcon#about to write, iclass 33, count 0 2006.239.07:47:49.66#ibcon#wrote, iclass 33, count 0 2006.239.07:47:49.66#ibcon#about to read 3, iclass 33, count 0 2006.239.07:47:49.70#ibcon#read 3, iclass 33, count 0 2006.239.07:47:49.70#ibcon#about to read 4, iclass 33, count 0 2006.239.07:47:49.70#ibcon#read 4, iclass 33, count 0 2006.239.07:47:49.70#ibcon#about to read 5, iclass 33, count 0 2006.239.07:47:49.70#ibcon#read 5, iclass 33, count 0 2006.239.07:47:49.70#ibcon#about to read 6, iclass 33, count 0 2006.239.07:47:49.70#ibcon#read 6, iclass 33, count 0 2006.239.07:47:49.70#ibcon#end of sib2, iclass 33, count 0 2006.239.07:47:49.70#ibcon#*after write, iclass 33, count 0 2006.239.07:47:49.70#ibcon#*before return 0, iclass 33, count 0 2006.239.07:47:49.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:49.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:49.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:47:49.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:47:49.70$vc4f8/va=6,7 2006.239.07:47:49.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:47:49.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:47:49.70#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:49.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:49.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:49.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:49.74#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:47:49.74#ibcon#first serial, iclass 35, count 2 2006.239.07:47:49.74#ibcon#enter sib2, iclass 35, count 2 2006.239.07:47:49.74#ibcon#flushed, iclass 35, count 2 2006.239.07:47:49.74#ibcon#about to write, iclass 35, count 2 2006.239.07:47:49.74#ibcon#wrote, iclass 35, count 2 2006.239.07:47:49.74#ibcon#about to read 3, iclass 35, count 2 2006.239.07:47:49.76#ibcon#read 3, iclass 35, count 2 2006.239.07:47:49.76#ibcon#about to read 4, iclass 35, count 2 2006.239.07:47:49.76#ibcon#read 4, iclass 35, count 2 2006.239.07:47:49.76#ibcon#about to read 5, iclass 35, count 2 2006.239.07:47:49.76#ibcon#read 5, iclass 35, count 2 2006.239.07:47:49.76#ibcon#about to read 6, iclass 35, count 2 2006.239.07:47:49.76#ibcon#read 6, iclass 35, count 2 2006.239.07:47:49.76#ibcon#end of sib2, iclass 35, count 2 2006.239.07:47:49.76#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:47:49.76#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:47:49.76#ibcon#[25=AT06-07\r\n] 2006.239.07:47:49.76#ibcon#*before write, iclass 35, count 2 2006.239.07:47:49.76#ibcon#enter sib2, iclass 35, count 2 2006.239.07:47:49.76#ibcon#flushed, iclass 35, count 2 2006.239.07:47:49.76#ibcon#about to write, iclass 35, count 2 2006.239.07:47:49.76#ibcon#wrote, iclass 35, count 2 2006.239.07:47:49.76#ibcon#about to read 3, iclass 35, count 2 2006.239.07:47:49.79#ibcon#read 3, iclass 35, count 2 2006.239.07:47:49.79#ibcon#about to read 4, iclass 35, count 2 2006.239.07:47:49.79#ibcon#read 4, iclass 35, count 2 2006.239.07:47:49.79#ibcon#about to read 5, iclass 35, count 2 2006.239.07:47:49.79#ibcon#read 5, iclass 35, count 2 2006.239.07:47:49.79#ibcon#about to read 6, iclass 35, count 2 2006.239.07:47:49.79#ibcon#read 6, iclass 35, count 2 2006.239.07:47:49.79#ibcon#end of sib2, iclass 35, count 2 2006.239.07:47:49.79#ibcon#*after write, iclass 35, count 2 2006.239.07:47:49.79#ibcon#*before return 0, iclass 35, count 2 2006.239.07:47:49.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:49.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:49.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:47:49.79#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:49.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:49.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:49.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:49.91#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:47:49.91#ibcon#first serial, iclass 35, count 0 2006.239.07:47:49.91#ibcon#enter sib2, iclass 35, count 0 2006.239.07:47:49.91#ibcon#flushed, iclass 35, count 0 2006.239.07:47:49.91#ibcon#about to write, iclass 35, count 0 2006.239.07:47:49.91#ibcon#wrote, iclass 35, count 0 2006.239.07:47:49.91#ibcon#about to read 3, iclass 35, count 0 2006.239.07:47:49.93#ibcon#read 3, iclass 35, count 0 2006.239.07:47:49.93#ibcon#about to read 4, iclass 35, count 0 2006.239.07:47:49.93#ibcon#read 4, iclass 35, count 0 2006.239.07:47:49.93#ibcon#about to read 5, iclass 35, count 0 2006.239.07:47:49.93#ibcon#read 5, iclass 35, count 0 2006.239.07:47:49.93#ibcon#about to read 6, iclass 35, count 0 2006.239.07:47:49.93#ibcon#read 6, iclass 35, count 0 2006.239.07:47:49.93#ibcon#end of sib2, iclass 35, count 0 2006.239.07:47:49.93#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:47:49.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:47:49.93#ibcon#[25=USB\r\n] 2006.239.07:47:49.93#ibcon#*before write, iclass 35, count 0 2006.239.07:47:49.93#ibcon#enter sib2, iclass 35, count 0 2006.239.07:47:49.93#ibcon#flushed, iclass 35, count 0 2006.239.07:47:49.93#ibcon#about to write, iclass 35, count 0 2006.239.07:47:49.93#ibcon#wrote, iclass 35, count 0 2006.239.07:47:49.93#ibcon#about to read 3, iclass 35, count 0 2006.239.07:47:49.96#ibcon#read 3, iclass 35, count 0 2006.239.07:47:49.96#ibcon#about to read 4, iclass 35, count 0 2006.239.07:47:49.96#ibcon#read 4, iclass 35, count 0 2006.239.07:47:49.96#ibcon#about to read 5, iclass 35, count 0 2006.239.07:47:49.96#ibcon#read 5, iclass 35, count 0 2006.239.07:47:49.96#ibcon#about to read 6, iclass 35, count 0 2006.239.07:47:49.96#ibcon#read 6, iclass 35, count 0 2006.239.07:47:49.96#ibcon#end of sib2, iclass 35, count 0 2006.239.07:47:49.96#ibcon#*after write, iclass 35, count 0 2006.239.07:47:49.96#ibcon#*before return 0, iclass 35, count 0 2006.239.07:47:49.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:49.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:49.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:47:49.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:47:49.96$vc4f8/valo=7,832.99 2006.239.07:47:49.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:47:49.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:47:49.96#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:49.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:49.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:49.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:49.96#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:47:49.96#ibcon#first serial, iclass 37, count 0 2006.239.07:47:49.96#ibcon#enter sib2, iclass 37, count 0 2006.239.07:47:49.96#ibcon#flushed, iclass 37, count 0 2006.239.07:47:49.96#ibcon#about to write, iclass 37, count 0 2006.239.07:47:49.96#ibcon#wrote, iclass 37, count 0 2006.239.07:47:49.96#ibcon#about to read 3, iclass 37, count 0 2006.239.07:47:49.98#ibcon#read 3, iclass 37, count 0 2006.239.07:47:49.98#ibcon#about to read 4, iclass 37, count 0 2006.239.07:47:49.98#ibcon#read 4, iclass 37, count 0 2006.239.07:47:49.98#ibcon#about to read 5, iclass 37, count 0 2006.239.07:47:49.98#ibcon#read 5, iclass 37, count 0 2006.239.07:47:49.98#ibcon#about to read 6, iclass 37, count 0 2006.239.07:47:49.98#ibcon#read 6, iclass 37, count 0 2006.239.07:47:49.98#ibcon#end of sib2, iclass 37, count 0 2006.239.07:47:49.98#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:47:49.98#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:47:49.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:47:49.98#ibcon#*before write, iclass 37, count 0 2006.239.07:47:49.98#ibcon#enter sib2, iclass 37, count 0 2006.239.07:47:49.98#ibcon#flushed, iclass 37, count 0 2006.239.07:47:49.98#ibcon#about to write, iclass 37, count 0 2006.239.07:47:49.98#ibcon#wrote, iclass 37, count 0 2006.239.07:47:49.98#ibcon#about to read 3, iclass 37, count 0 2006.239.07:47:50.02#ibcon#read 3, iclass 37, count 0 2006.239.07:47:50.02#ibcon#about to read 4, iclass 37, count 0 2006.239.07:47:50.02#ibcon#read 4, iclass 37, count 0 2006.239.07:47:50.02#ibcon#about to read 5, iclass 37, count 0 2006.239.07:47:50.02#ibcon#read 5, iclass 37, count 0 2006.239.07:47:50.02#ibcon#about to read 6, iclass 37, count 0 2006.239.07:47:50.02#ibcon#read 6, iclass 37, count 0 2006.239.07:47:50.02#ibcon#end of sib2, iclass 37, count 0 2006.239.07:47:50.02#ibcon#*after write, iclass 37, count 0 2006.239.07:47:50.02#ibcon#*before return 0, iclass 37, count 0 2006.239.07:47:50.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:50.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:50.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:47:50.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:47:50.02$vc4f8/va=7,7 2006.239.07:47:50.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:47:50.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:47:50.02#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:50.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:47:50.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:47:50.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:47:50.08#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:47:50.08#ibcon#first serial, iclass 39, count 2 2006.239.07:47:50.08#ibcon#enter sib2, iclass 39, count 2 2006.239.07:47:50.08#ibcon#flushed, iclass 39, count 2 2006.239.07:47:50.08#ibcon#about to write, iclass 39, count 2 2006.239.07:47:50.08#ibcon#wrote, iclass 39, count 2 2006.239.07:47:50.08#ibcon#about to read 3, iclass 39, count 2 2006.239.07:47:50.10#ibcon#read 3, iclass 39, count 2 2006.239.07:47:50.10#ibcon#about to read 4, iclass 39, count 2 2006.239.07:47:50.10#ibcon#read 4, iclass 39, count 2 2006.239.07:47:50.10#ibcon#about to read 5, iclass 39, count 2 2006.239.07:47:50.10#ibcon#read 5, iclass 39, count 2 2006.239.07:47:50.10#ibcon#about to read 6, iclass 39, count 2 2006.239.07:47:50.10#ibcon#read 6, iclass 39, count 2 2006.239.07:47:50.10#ibcon#end of sib2, iclass 39, count 2 2006.239.07:47:50.10#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:47:50.10#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:47:50.10#ibcon#[25=AT07-07\r\n] 2006.239.07:47:50.10#ibcon#*before write, iclass 39, count 2 2006.239.07:47:50.10#ibcon#enter sib2, iclass 39, count 2 2006.239.07:47:50.10#ibcon#flushed, iclass 39, count 2 2006.239.07:47:50.10#ibcon#about to write, iclass 39, count 2 2006.239.07:47:50.10#ibcon#wrote, iclass 39, count 2 2006.239.07:47:50.10#ibcon#about to read 3, iclass 39, count 2 2006.239.07:47:50.13#ibcon#read 3, iclass 39, count 2 2006.239.07:47:50.13#ibcon#about to read 4, iclass 39, count 2 2006.239.07:47:50.13#ibcon#read 4, iclass 39, count 2 2006.239.07:47:50.13#ibcon#about to read 5, iclass 39, count 2 2006.239.07:47:50.13#ibcon#read 5, iclass 39, count 2 2006.239.07:47:50.13#ibcon#about to read 6, iclass 39, count 2 2006.239.07:47:50.13#ibcon#read 6, iclass 39, count 2 2006.239.07:47:50.13#ibcon#end of sib2, iclass 39, count 2 2006.239.07:47:50.13#ibcon#*after write, iclass 39, count 2 2006.239.07:47:50.13#ibcon#*before return 0, iclass 39, count 2 2006.239.07:47:50.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:47:50.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:47:50.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:47:50.13#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:50.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:47:50.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:47:50.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:47:50.25#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:47:50.25#ibcon#first serial, iclass 39, count 0 2006.239.07:47:50.25#ibcon#enter sib2, iclass 39, count 0 2006.239.07:47:50.25#ibcon#flushed, iclass 39, count 0 2006.239.07:47:50.25#ibcon#about to write, iclass 39, count 0 2006.239.07:47:50.25#ibcon#wrote, iclass 39, count 0 2006.239.07:47:50.25#ibcon#about to read 3, iclass 39, count 0 2006.239.07:47:50.27#ibcon#read 3, iclass 39, count 0 2006.239.07:47:50.27#ibcon#about to read 4, iclass 39, count 0 2006.239.07:47:50.27#ibcon#read 4, iclass 39, count 0 2006.239.07:47:50.27#ibcon#about to read 5, iclass 39, count 0 2006.239.07:47:50.27#ibcon#read 5, iclass 39, count 0 2006.239.07:47:50.27#ibcon#about to read 6, iclass 39, count 0 2006.239.07:47:50.27#ibcon#read 6, iclass 39, count 0 2006.239.07:47:50.27#ibcon#end of sib2, iclass 39, count 0 2006.239.07:47:50.27#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:47:50.27#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:47:50.27#ibcon#[25=USB\r\n] 2006.239.07:47:50.27#ibcon#*before write, iclass 39, count 0 2006.239.07:47:50.27#ibcon#enter sib2, iclass 39, count 0 2006.239.07:47:50.27#ibcon#flushed, iclass 39, count 0 2006.239.07:47:50.27#ibcon#about to write, iclass 39, count 0 2006.239.07:47:50.27#ibcon#wrote, iclass 39, count 0 2006.239.07:47:50.27#ibcon#about to read 3, iclass 39, count 0 2006.239.07:47:50.30#ibcon#read 3, iclass 39, count 0 2006.239.07:47:50.30#ibcon#about to read 4, iclass 39, count 0 2006.239.07:47:50.30#ibcon#read 4, iclass 39, count 0 2006.239.07:47:50.30#ibcon#about to read 5, iclass 39, count 0 2006.239.07:47:50.30#ibcon#read 5, iclass 39, count 0 2006.239.07:47:50.30#ibcon#about to read 6, iclass 39, count 0 2006.239.07:47:50.30#ibcon#read 6, iclass 39, count 0 2006.239.07:47:50.30#ibcon#end of sib2, iclass 39, count 0 2006.239.07:47:50.30#ibcon#*after write, iclass 39, count 0 2006.239.07:47:50.30#ibcon#*before return 0, iclass 39, count 0 2006.239.07:47:50.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:47:50.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:47:50.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:47:50.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:47:50.30$vc4f8/valo=8,852.99 2006.239.07:47:50.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:47:50.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:47:50.30#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:50.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:47:50.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:47:50.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:47:50.30#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:47:50.30#ibcon#first serial, iclass 3, count 0 2006.239.07:47:50.30#ibcon#enter sib2, iclass 3, count 0 2006.239.07:47:50.30#ibcon#flushed, iclass 3, count 0 2006.239.07:47:50.30#ibcon#about to write, iclass 3, count 0 2006.239.07:47:50.30#ibcon#wrote, iclass 3, count 0 2006.239.07:47:50.30#ibcon#about to read 3, iclass 3, count 0 2006.239.07:47:50.32#ibcon#read 3, iclass 3, count 0 2006.239.07:47:50.32#ibcon#about to read 4, iclass 3, count 0 2006.239.07:47:50.32#ibcon#read 4, iclass 3, count 0 2006.239.07:47:50.32#ibcon#about to read 5, iclass 3, count 0 2006.239.07:47:50.32#ibcon#read 5, iclass 3, count 0 2006.239.07:47:50.32#ibcon#about to read 6, iclass 3, count 0 2006.239.07:47:50.32#ibcon#read 6, iclass 3, count 0 2006.239.07:47:50.32#ibcon#end of sib2, iclass 3, count 0 2006.239.07:47:50.32#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:47:50.32#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:47:50.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:47:50.32#ibcon#*before write, iclass 3, count 0 2006.239.07:47:50.32#ibcon#enter sib2, iclass 3, count 0 2006.239.07:47:50.32#ibcon#flushed, iclass 3, count 0 2006.239.07:47:50.32#ibcon#about to write, iclass 3, count 0 2006.239.07:47:50.32#ibcon#wrote, iclass 3, count 0 2006.239.07:47:50.32#ibcon#about to read 3, iclass 3, count 0 2006.239.07:47:50.36#ibcon#read 3, iclass 3, count 0 2006.239.07:47:50.36#ibcon#about to read 4, iclass 3, count 0 2006.239.07:47:50.36#ibcon#read 4, iclass 3, count 0 2006.239.07:47:50.36#ibcon#about to read 5, iclass 3, count 0 2006.239.07:47:50.36#ibcon#read 5, iclass 3, count 0 2006.239.07:47:50.36#ibcon#about to read 6, iclass 3, count 0 2006.239.07:47:50.36#ibcon#read 6, iclass 3, count 0 2006.239.07:47:50.36#ibcon#end of sib2, iclass 3, count 0 2006.239.07:47:50.36#ibcon#*after write, iclass 3, count 0 2006.239.07:47:50.36#ibcon#*before return 0, iclass 3, count 0 2006.239.07:47:50.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:47:50.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:47:50.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:47:50.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:47:50.36$vc4f8/va=8,7 2006.239.07:47:50.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.07:47:50.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.07:47:50.36#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:50.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:47:50.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:47:50.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:47:50.42#ibcon#enter wrdev, iclass 5, count 2 2006.239.07:47:50.42#ibcon#first serial, iclass 5, count 2 2006.239.07:47:50.42#ibcon#enter sib2, iclass 5, count 2 2006.239.07:47:50.42#ibcon#flushed, iclass 5, count 2 2006.239.07:47:50.42#ibcon#about to write, iclass 5, count 2 2006.239.07:47:50.42#ibcon#wrote, iclass 5, count 2 2006.239.07:47:50.42#ibcon#about to read 3, iclass 5, count 2 2006.239.07:47:50.44#ibcon#read 3, iclass 5, count 2 2006.239.07:47:50.44#ibcon#about to read 4, iclass 5, count 2 2006.239.07:47:50.44#ibcon#read 4, iclass 5, count 2 2006.239.07:47:50.44#ibcon#about to read 5, iclass 5, count 2 2006.239.07:47:50.44#ibcon#read 5, iclass 5, count 2 2006.239.07:47:50.44#ibcon#about to read 6, iclass 5, count 2 2006.239.07:47:50.44#ibcon#read 6, iclass 5, count 2 2006.239.07:47:50.44#ibcon#end of sib2, iclass 5, count 2 2006.239.07:47:50.44#ibcon#*mode == 0, iclass 5, count 2 2006.239.07:47:50.44#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.07:47:50.44#ibcon#[25=AT08-07\r\n] 2006.239.07:47:50.44#ibcon#*before write, iclass 5, count 2 2006.239.07:47:50.44#ibcon#enter sib2, iclass 5, count 2 2006.239.07:47:50.44#ibcon#flushed, iclass 5, count 2 2006.239.07:47:50.44#ibcon#about to write, iclass 5, count 2 2006.239.07:47:50.44#ibcon#wrote, iclass 5, count 2 2006.239.07:47:50.44#ibcon#about to read 3, iclass 5, count 2 2006.239.07:47:50.47#ibcon#read 3, iclass 5, count 2 2006.239.07:47:50.47#ibcon#about to read 4, iclass 5, count 2 2006.239.07:47:50.47#ibcon#read 4, iclass 5, count 2 2006.239.07:47:50.47#ibcon#about to read 5, iclass 5, count 2 2006.239.07:47:50.47#ibcon#read 5, iclass 5, count 2 2006.239.07:47:50.47#ibcon#about to read 6, iclass 5, count 2 2006.239.07:47:50.47#ibcon#read 6, iclass 5, count 2 2006.239.07:47:50.47#ibcon#end of sib2, iclass 5, count 2 2006.239.07:47:50.47#ibcon#*after write, iclass 5, count 2 2006.239.07:47:50.47#ibcon#*before return 0, iclass 5, count 2 2006.239.07:47:50.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:47:50.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:47:50.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.07:47:50.47#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:50.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:47:50.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:47:50.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:47:50.59#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:47:50.59#ibcon#first serial, iclass 5, count 0 2006.239.07:47:50.59#ibcon#enter sib2, iclass 5, count 0 2006.239.07:47:50.59#ibcon#flushed, iclass 5, count 0 2006.239.07:47:50.59#ibcon#about to write, iclass 5, count 0 2006.239.07:47:50.59#ibcon#wrote, iclass 5, count 0 2006.239.07:47:50.59#ibcon#about to read 3, iclass 5, count 0 2006.239.07:47:50.61#ibcon#read 3, iclass 5, count 0 2006.239.07:47:50.61#ibcon#about to read 4, iclass 5, count 0 2006.239.07:47:50.61#ibcon#read 4, iclass 5, count 0 2006.239.07:47:50.61#ibcon#about to read 5, iclass 5, count 0 2006.239.07:47:50.61#ibcon#read 5, iclass 5, count 0 2006.239.07:47:50.61#ibcon#about to read 6, iclass 5, count 0 2006.239.07:47:50.61#ibcon#read 6, iclass 5, count 0 2006.239.07:47:50.61#ibcon#end of sib2, iclass 5, count 0 2006.239.07:47:50.61#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:47:50.61#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:47:50.61#ibcon#[25=USB\r\n] 2006.239.07:47:50.61#ibcon#*before write, iclass 5, count 0 2006.239.07:47:50.61#ibcon#enter sib2, iclass 5, count 0 2006.239.07:47:50.61#ibcon#flushed, iclass 5, count 0 2006.239.07:47:50.61#ibcon#about to write, iclass 5, count 0 2006.239.07:47:50.61#ibcon#wrote, iclass 5, count 0 2006.239.07:47:50.61#ibcon#about to read 3, iclass 5, count 0 2006.239.07:47:50.64#ibcon#read 3, iclass 5, count 0 2006.239.07:47:50.64#ibcon#about to read 4, iclass 5, count 0 2006.239.07:47:50.64#ibcon#read 4, iclass 5, count 0 2006.239.07:47:50.64#ibcon#about to read 5, iclass 5, count 0 2006.239.07:47:50.64#ibcon#read 5, iclass 5, count 0 2006.239.07:47:50.64#ibcon#about to read 6, iclass 5, count 0 2006.239.07:47:50.64#ibcon#read 6, iclass 5, count 0 2006.239.07:47:50.64#ibcon#end of sib2, iclass 5, count 0 2006.239.07:47:50.64#ibcon#*after write, iclass 5, count 0 2006.239.07:47:50.64#ibcon#*before return 0, iclass 5, count 0 2006.239.07:47:50.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:47:50.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:47:50.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:47:50.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:47:50.64$vc4f8/vblo=1,632.99 2006.239.07:47:50.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:47:50.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:47:50.64#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:50.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:47:50.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:47:50.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:47:50.64#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:47:50.64#ibcon#first serial, iclass 7, count 0 2006.239.07:47:50.64#ibcon#enter sib2, iclass 7, count 0 2006.239.07:47:50.64#ibcon#flushed, iclass 7, count 0 2006.239.07:47:50.64#ibcon#about to write, iclass 7, count 0 2006.239.07:47:50.64#ibcon#wrote, iclass 7, count 0 2006.239.07:47:50.64#ibcon#about to read 3, iclass 7, count 0 2006.239.07:47:50.66#ibcon#read 3, iclass 7, count 0 2006.239.07:47:50.66#ibcon#about to read 4, iclass 7, count 0 2006.239.07:47:50.66#ibcon#read 4, iclass 7, count 0 2006.239.07:47:50.66#ibcon#about to read 5, iclass 7, count 0 2006.239.07:47:50.66#ibcon#read 5, iclass 7, count 0 2006.239.07:47:50.66#ibcon#about to read 6, iclass 7, count 0 2006.239.07:47:50.66#ibcon#read 6, iclass 7, count 0 2006.239.07:47:50.66#ibcon#end of sib2, iclass 7, count 0 2006.239.07:47:50.66#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:47:50.66#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:47:50.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:47:50.66#ibcon#*before write, iclass 7, count 0 2006.239.07:47:50.66#ibcon#enter sib2, iclass 7, count 0 2006.239.07:47:50.66#ibcon#flushed, iclass 7, count 0 2006.239.07:47:50.66#ibcon#about to write, iclass 7, count 0 2006.239.07:47:50.66#ibcon#wrote, iclass 7, count 0 2006.239.07:47:50.66#ibcon#about to read 3, iclass 7, count 0 2006.239.07:47:50.70#ibcon#read 3, iclass 7, count 0 2006.239.07:47:50.70#ibcon#about to read 4, iclass 7, count 0 2006.239.07:47:50.70#ibcon#read 4, iclass 7, count 0 2006.239.07:47:50.70#ibcon#about to read 5, iclass 7, count 0 2006.239.07:47:50.70#ibcon#read 5, iclass 7, count 0 2006.239.07:47:50.70#ibcon#about to read 6, iclass 7, count 0 2006.239.07:47:50.70#ibcon#read 6, iclass 7, count 0 2006.239.07:47:50.70#ibcon#end of sib2, iclass 7, count 0 2006.239.07:47:50.70#ibcon#*after write, iclass 7, count 0 2006.239.07:47:50.70#ibcon#*before return 0, iclass 7, count 0 2006.239.07:47:50.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:47:50.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:47:50.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:47:50.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:47:50.70$vc4f8/vb=1,4 2006.239.07:47:50.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.07:47:50.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.07:47:50.70#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:50.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:47:50.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:47:50.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:47:50.70#ibcon#enter wrdev, iclass 11, count 2 2006.239.07:47:50.70#ibcon#first serial, iclass 11, count 2 2006.239.07:47:50.70#ibcon#enter sib2, iclass 11, count 2 2006.239.07:47:50.70#ibcon#flushed, iclass 11, count 2 2006.239.07:47:50.70#ibcon#about to write, iclass 11, count 2 2006.239.07:47:50.70#ibcon#wrote, iclass 11, count 2 2006.239.07:47:50.70#ibcon#about to read 3, iclass 11, count 2 2006.239.07:47:50.72#ibcon#read 3, iclass 11, count 2 2006.239.07:47:50.72#ibcon#about to read 4, iclass 11, count 2 2006.239.07:47:50.72#ibcon#read 4, iclass 11, count 2 2006.239.07:47:50.72#ibcon#about to read 5, iclass 11, count 2 2006.239.07:47:50.72#ibcon#read 5, iclass 11, count 2 2006.239.07:47:50.72#ibcon#about to read 6, iclass 11, count 2 2006.239.07:47:50.72#ibcon#read 6, iclass 11, count 2 2006.239.07:47:50.72#ibcon#end of sib2, iclass 11, count 2 2006.239.07:47:50.72#ibcon#*mode == 0, iclass 11, count 2 2006.239.07:47:50.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.07:47:50.72#ibcon#[27=AT01-04\r\n] 2006.239.07:47:50.72#ibcon#*before write, iclass 11, count 2 2006.239.07:47:50.72#ibcon#enter sib2, iclass 11, count 2 2006.239.07:47:50.72#ibcon#flushed, iclass 11, count 2 2006.239.07:47:50.72#ibcon#about to write, iclass 11, count 2 2006.239.07:47:50.72#ibcon#wrote, iclass 11, count 2 2006.239.07:47:50.72#ibcon#about to read 3, iclass 11, count 2 2006.239.07:47:50.75#ibcon#read 3, iclass 11, count 2 2006.239.07:47:50.75#ibcon#about to read 4, iclass 11, count 2 2006.239.07:47:50.75#ibcon#read 4, iclass 11, count 2 2006.239.07:47:50.75#ibcon#about to read 5, iclass 11, count 2 2006.239.07:47:50.75#ibcon#read 5, iclass 11, count 2 2006.239.07:47:50.75#ibcon#about to read 6, iclass 11, count 2 2006.239.07:47:50.75#ibcon#read 6, iclass 11, count 2 2006.239.07:47:50.75#ibcon#end of sib2, iclass 11, count 2 2006.239.07:47:50.75#ibcon#*after write, iclass 11, count 2 2006.239.07:47:50.75#ibcon#*before return 0, iclass 11, count 2 2006.239.07:47:50.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:47:50.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:47:50.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.07:47:50.75#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:50.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:47:50.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:47:50.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:47:50.87#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:47:50.87#ibcon#first serial, iclass 11, count 0 2006.239.07:47:50.87#ibcon#enter sib2, iclass 11, count 0 2006.239.07:47:50.87#ibcon#flushed, iclass 11, count 0 2006.239.07:47:50.87#ibcon#about to write, iclass 11, count 0 2006.239.07:47:50.87#ibcon#wrote, iclass 11, count 0 2006.239.07:47:50.87#ibcon#about to read 3, iclass 11, count 0 2006.239.07:47:50.89#ibcon#read 3, iclass 11, count 0 2006.239.07:47:50.89#ibcon#about to read 4, iclass 11, count 0 2006.239.07:47:50.89#ibcon#read 4, iclass 11, count 0 2006.239.07:47:50.89#ibcon#about to read 5, iclass 11, count 0 2006.239.07:47:50.89#ibcon#read 5, iclass 11, count 0 2006.239.07:47:50.89#ibcon#about to read 6, iclass 11, count 0 2006.239.07:47:50.89#ibcon#read 6, iclass 11, count 0 2006.239.07:47:50.89#ibcon#end of sib2, iclass 11, count 0 2006.239.07:47:50.89#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:47:50.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:47:50.89#ibcon#[27=USB\r\n] 2006.239.07:47:50.89#ibcon#*before write, iclass 11, count 0 2006.239.07:47:50.89#ibcon#enter sib2, iclass 11, count 0 2006.239.07:47:50.89#ibcon#flushed, iclass 11, count 0 2006.239.07:47:50.89#ibcon#about to write, iclass 11, count 0 2006.239.07:47:50.89#ibcon#wrote, iclass 11, count 0 2006.239.07:47:50.89#ibcon#about to read 3, iclass 11, count 0 2006.239.07:47:50.92#ibcon#read 3, iclass 11, count 0 2006.239.07:47:50.92#ibcon#about to read 4, iclass 11, count 0 2006.239.07:47:50.92#ibcon#read 4, iclass 11, count 0 2006.239.07:47:50.92#ibcon#about to read 5, iclass 11, count 0 2006.239.07:47:50.92#ibcon#read 5, iclass 11, count 0 2006.239.07:47:50.92#ibcon#about to read 6, iclass 11, count 0 2006.239.07:47:50.92#ibcon#read 6, iclass 11, count 0 2006.239.07:47:50.92#ibcon#end of sib2, iclass 11, count 0 2006.239.07:47:50.92#ibcon#*after write, iclass 11, count 0 2006.239.07:47:50.92#ibcon#*before return 0, iclass 11, count 0 2006.239.07:47:50.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:47:50.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:47:50.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:47:50.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:47:50.92$vc4f8/vblo=2,640.99 2006.239.07:47:50.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.07:47:50.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.07:47:50.92#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:50.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:50.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:50.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:50.92#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:47:50.92#ibcon#first serial, iclass 13, count 0 2006.239.07:47:50.92#ibcon#enter sib2, iclass 13, count 0 2006.239.07:47:50.92#ibcon#flushed, iclass 13, count 0 2006.239.07:47:50.92#ibcon#about to write, iclass 13, count 0 2006.239.07:47:50.92#ibcon#wrote, iclass 13, count 0 2006.239.07:47:50.92#ibcon#about to read 3, iclass 13, count 0 2006.239.07:47:50.94#ibcon#read 3, iclass 13, count 0 2006.239.07:47:50.94#ibcon#about to read 4, iclass 13, count 0 2006.239.07:47:50.94#ibcon#read 4, iclass 13, count 0 2006.239.07:47:50.94#ibcon#about to read 5, iclass 13, count 0 2006.239.07:47:50.94#ibcon#read 5, iclass 13, count 0 2006.239.07:47:50.94#ibcon#about to read 6, iclass 13, count 0 2006.239.07:47:50.94#ibcon#read 6, iclass 13, count 0 2006.239.07:47:50.94#ibcon#end of sib2, iclass 13, count 0 2006.239.07:47:50.94#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:47:50.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:47:50.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:47:50.94#ibcon#*before write, iclass 13, count 0 2006.239.07:47:50.94#ibcon#enter sib2, iclass 13, count 0 2006.239.07:47:50.94#ibcon#flushed, iclass 13, count 0 2006.239.07:47:50.94#ibcon#about to write, iclass 13, count 0 2006.239.07:47:50.94#ibcon#wrote, iclass 13, count 0 2006.239.07:47:50.94#ibcon#about to read 3, iclass 13, count 0 2006.239.07:47:50.98#ibcon#read 3, iclass 13, count 0 2006.239.07:47:50.98#ibcon#about to read 4, iclass 13, count 0 2006.239.07:47:50.98#ibcon#read 4, iclass 13, count 0 2006.239.07:47:50.98#ibcon#about to read 5, iclass 13, count 0 2006.239.07:47:50.98#ibcon#read 5, iclass 13, count 0 2006.239.07:47:50.98#ibcon#about to read 6, iclass 13, count 0 2006.239.07:47:50.98#ibcon#read 6, iclass 13, count 0 2006.239.07:47:50.98#ibcon#end of sib2, iclass 13, count 0 2006.239.07:47:50.98#ibcon#*after write, iclass 13, count 0 2006.239.07:47:50.98#ibcon#*before return 0, iclass 13, count 0 2006.239.07:47:50.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:50.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:47:50.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:47:50.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:47:50.98$vc4f8/vb=2,4 2006.239.07:47:50.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:47:50.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:47:50.98#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:50.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:47:50.99#abcon#<5=/05 2.1 3.6 25.29 801011.5\r\n> 2006.239.07:47:51.01#abcon#{5=INTERFACE CLEAR} 2006.239.07:47:51.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:47:51.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:47:51.04#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:47:51.04#ibcon#first serial, iclass 16, count 2 2006.239.07:47:51.04#ibcon#enter sib2, iclass 16, count 2 2006.239.07:47:51.04#ibcon#flushed, iclass 16, count 2 2006.239.07:47:51.04#ibcon#about to write, iclass 16, count 2 2006.239.07:47:51.04#ibcon#wrote, iclass 16, count 2 2006.239.07:47:51.04#ibcon#about to read 3, iclass 16, count 2 2006.239.07:47:51.06#ibcon#read 3, iclass 16, count 2 2006.239.07:47:51.06#ibcon#about to read 4, iclass 16, count 2 2006.239.07:47:51.06#ibcon#read 4, iclass 16, count 2 2006.239.07:47:51.06#ibcon#about to read 5, iclass 16, count 2 2006.239.07:47:51.06#ibcon#read 5, iclass 16, count 2 2006.239.07:47:51.06#ibcon#about to read 6, iclass 16, count 2 2006.239.07:47:51.06#ibcon#read 6, iclass 16, count 2 2006.239.07:47:51.06#ibcon#end of sib2, iclass 16, count 2 2006.239.07:47:51.06#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:47:51.06#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:47:51.06#ibcon#[27=AT02-04\r\n] 2006.239.07:47:51.06#ibcon#*before write, iclass 16, count 2 2006.239.07:47:51.06#ibcon#enter sib2, iclass 16, count 2 2006.239.07:47:51.06#ibcon#flushed, iclass 16, count 2 2006.239.07:47:51.06#ibcon#about to write, iclass 16, count 2 2006.239.07:47:51.06#ibcon#wrote, iclass 16, count 2 2006.239.07:47:51.06#ibcon#about to read 3, iclass 16, count 2 2006.239.07:47:51.07#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:47:51.09#ibcon#read 3, iclass 16, count 2 2006.239.07:47:51.09#ibcon#about to read 4, iclass 16, count 2 2006.239.07:47:51.09#ibcon#read 4, iclass 16, count 2 2006.239.07:47:51.09#ibcon#about to read 5, iclass 16, count 2 2006.239.07:47:51.09#ibcon#read 5, iclass 16, count 2 2006.239.07:47:51.09#ibcon#about to read 6, iclass 16, count 2 2006.239.07:47:51.09#ibcon#read 6, iclass 16, count 2 2006.239.07:47:51.09#ibcon#end of sib2, iclass 16, count 2 2006.239.07:47:51.09#ibcon#*after write, iclass 16, count 2 2006.239.07:47:51.09#ibcon#*before return 0, iclass 16, count 2 2006.239.07:47:51.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:47:51.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:47:51.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:47:51.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:51.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:47:51.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:47:51.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:47:51.21#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:47:51.21#ibcon#first serial, iclass 16, count 0 2006.239.07:47:51.21#ibcon#enter sib2, iclass 16, count 0 2006.239.07:47:51.21#ibcon#flushed, iclass 16, count 0 2006.239.07:47:51.21#ibcon#about to write, iclass 16, count 0 2006.239.07:47:51.21#ibcon#wrote, iclass 16, count 0 2006.239.07:47:51.21#ibcon#about to read 3, iclass 16, count 0 2006.239.07:47:51.23#ibcon#read 3, iclass 16, count 0 2006.239.07:47:51.23#ibcon#about to read 4, iclass 16, count 0 2006.239.07:47:51.23#ibcon#read 4, iclass 16, count 0 2006.239.07:47:51.23#ibcon#about to read 5, iclass 16, count 0 2006.239.07:47:51.23#ibcon#read 5, iclass 16, count 0 2006.239.07:47:51.23#ibcon#about to read 6, iclass 16, count 0 2006.239.07:47:51.23#ibcon#read 6, iclass 16, count 0 2006.239.07:47:51.23#ibcon#end of sib2, iclass 16, count 0 2006.239.07:47:51.23#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:47:51.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:47:51.23#ibcon#[27=USB\r\n] 2006.239.07:47:51.23#ibcon#*before write, iclass 16, count 0 2006.239.07:47:51.23#ibcon#enter sib2, iclass 16, count 0 2006.239.07:47:51.23#ibcon#flushed, iclass 16, count 0 2006.239.07:47:51.23#ibcon#about to write, iclass 16, count 0 2006.239.07:47:51.23#ibcon#wrote, iclass 16, count 0 2006.239.07:47:51.23#ibcon#about to read 3, iclass 16, count 0 2006.239.07:47:51.26#ibcon#read 3, iclass 16, count 0 2006.239.07:47:51.26#ibcon#about to read 4, iclass 16, count 0 2006.239.07:47:51.26#ibcon#read 4, iclass 16, count 0 2006.239.07:47:51.26#ibcon#about to read 5, iclass 16, count 0 2006.239.07:47:51.26#ibcon#read 5, iclass 16, count 0 2006.239.07:47:51.26#ibcon#about to read 6, iclass 16, count 0 2006.239.07:47:51.26#ibcon#read 6, iclass 16, count 0 2006.239.07:47:51.26#ibcon#end of sib2, iclass 16, count 0 2006.239.07:47:51.26#ibcon#*after write, iclass 16, count 0 2006.239.07:47:51.26#ibcon#*before return 0, iclass 16, count 0 2006.239.07:47:51.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:47:51.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:47:51.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:47:51.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:47:51.26$vc4f8/vblo=3,656.99 2006.239.07:47:51.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.07:47:51.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.07:47:51.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:51.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:51.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:51.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:51.26#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:47:51.26#ibcon#first serial, iclass 21, count 0 2006.239.07:47:51.26#ibcon#enter sib2, iclass 21, count 0 2006.239.07:47:51.26#ibcon#flushed, iclass 21, count 0 2006.239.07:47:51.26#ibcon#about to write, iclass 21, count 0 2006.239.07:47:51.26#ibcon#wrote, iclass 21, count 0 2006.239.07:47:51.26#ibcon#about to read 3, iclass 21, count 0 2006.239.07:47:51.28#ibcon#read 3, iclass 21, count 0 2006.239.07:47:51.28#ibcon#about to read 4, iclass 21, count 0 2006.239.07:47:51.28#ibcon#read 4, iclass 21, count 0 2006.239.07:47:51.28#ibcon#about to read 5, iclass 21, count 0 2006.239.07:47:51.28#ibcon#read 5, iclass 21, count 0 2006.239.07:47:51.28#ibcon#about to read 6, iclass 21, count 0 2006.239.07:47:51.28#ibcon#read 6, iclass 21, count 0 2006.239.07:47:51.28#ibcon#end of sib2, iclass 21, count 0 2006.239.07:47:51.28#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:47:51.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:47:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:47:51.28#ibcon#*before write, iclass 21, count 0 2006.239.07:47:51.28#ibcon#enter sib2, iclass 21, count 0 2006.239.07:47:51.28#ibcon#flushed, iclass 21, count 0 2006.239.07:47:51.28#ibcon#about to write, iclass 21, count 0 2006.239.07:47:51.28#ibcon#wrote, iclass 21, count 0 2006.239.07:47:51.28#ibcon#about to read 3, iclass 21, count 0 2006.239.07:47:51.32#ibcon#read 3, iclass 21, count 0 2006.239.07:47:51.32#ibcon#about to read 4, iclass 21, count 0 2006.239.07:47:51.32#ibcon#read 4, iclass 21, count 0 2006.239.07:47:51.32#ibcon#about to read 5, iclass 21, count 0 2006.239.07:47:51.32#ibcon#read 5, iclass 21, count 0 2006.239.07:47:51.32#ibcon#about to read 6, iclass 21, count 0 2006.239.07:47:51.32#ibcon#read 6, iclass 21, count 0 2006.239.07:47:51.32#ibcon#end of sib2, iclass 21, count 0 2006.239.07:47:51.32#ibcon#*after write, iclass 21, count 0 2006.239.07:47:51.32#ibcon#*before return 0, iclass 21, count 0 2006.239.07:47:51.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:51.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:47:51.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:47:51.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:47:51.32$vc4f8/vb=3,4 2006.239.07:47:51.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.07:47:51.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.07:47:51.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:51.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:51.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:51.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:51.38#ibcon#enter wrdev, iclass 23, count 2 2006.239.07:47:51.38#ibcon#first serial, iclass 23, count 2 2006.239.07:47:51.38#ibcon#enter sib2, iclass 23, count 2 2006.239.07:47:51.38#ibcon#flushed, iclass 23, count 2 2006.239.07:47:51.38#ibcon#about to write, iclass 23, count 2 2006.239.07:47:51.38#ibcon#wrote, iclass 23, count 2 2006.239.07:47:51.38#ibcon#about to read 3, iclass 23, count 2 2006.239.07:47:51.40#ibcon#read 3, iclass 23, count 2 2006.239.07:47:51.40#ibcon#about to read 4, iclass 23, count 2 2006.239.07:47:51.40#ibcon#read 4, iclass 23, count 2 2006.239.07:47:51.40#ibcon#about to read 5, iclass 23, count 2 2006.239.07:47:51.40#ibcon#read 5, iclass 23, count 2 2006.239.07:47:51.40#ibcon#about to read 6, iclass 23, count 2 2006.239.07:47:51.40#ibcon#read 6, iclass 23, count 2 2006.239.07:47:51.40#ibcon#end of sib2, iclass 23, count 2 2006.239.07:47:51.40#ibcon#*mode == 0, iclass 23, count 2 2006.239.07:47:51.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.07:47:51.40#ibcon#[27=AT03-04\r\n] 2006.239.07:47:51.40#ibcon#*before write, iclass 23, count 2 2006.239.07:47:51.40#ibcon#enter sib2, iclass 23, count 2 2006.239.07:47:51.40#ibcon#flushed, iclass 23, count 2 2006.239.07:47:51.40#ibcon#about to write, iclass 23, count 2 2006.239.07:47:51.40#ibcon#wrote, iclass 23, count 2 2006.239.07:47:51.40#ibcon#about to read 3, iclass 23, count 2 2006.239.07:47:51.43#ibcon#read 3, iclass 23, count 2 2006.239.07:47:51.43#ibcon#about to read 4, iclass 23, count 2 2006.239.07:47:51.43#ibcon#read 4, iclass 23, count 2 2006.239.07:47:51.43#ibcon#about to read 5, iclass 23, count 2 2006.239.07:47:51.43#ibcon#read 5, iclass 23, count 2 2006.239.07:47:51.43#ibcon#about to read 6, iclass 23, count 2 2006.239.07:47:51.43#ibcon#read 6, iclass 23, count 2 2006.239.07:47:51.43#ibcon#end of sib2, iclass 23, count 2 2006.239.07:47:51.43#ibcon#*after write, iclass 23, count 2 2006.239.07:47:51.43#ibcon#*before return 0, iclass 23, count 2 2006.239.07:47:51.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:51.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:47:51.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.07:47:51.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:51.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:51.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:51.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:51.55#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:47:51.55#ibcon#first serial, iclass 23, count 0 2006.239.07:47:51.55#ibcon#enter sib2, iclass 23, count 0 2006.239.07:47:51.55#ibcon#flushed, iclass 23, count 0 2006.239.07:47:51.55#ibcon#about to write, iclass 23, count 0 2006.239.07:47:51.55#ibcon#wrote, iclass 23, count 0 2006.239.07:47:51.55#ibcon#about to read 3, iclass 23, count 0 2006.239.07:47:51.57#ibcon#read 3, iclass 23, count 0 2006.239.07:47:51.57#ibcon#about to read 4, iclass 23, count 0 2006.239.07:47:51.57#ibcon#read 4, iclass 23, count 0 2006.239.07:47:51.57#ibcon#about to read 5, iclass 23, count 0 2006.239.07:47:51.57#ibcon#read 5, iclass 23, count 0 2006.239.07:47:51.57#ibcon#about to read 6, iclass 23, count 0 2006.239.07:47:51.57#ibcon#read 6, iclass 23, count 0 2006.239.07:47:51.57#ibcon#end of sib2, iclass 23, count 0 2006.239.07:47:51.57#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:47:51.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:47:51.57#ibcon#[27=USB\r\n] 2006.239.07:47:51.57#ibcon#*before write, iclass 23, count 0 2006.239.07:47:51.57#ibcon#enter sib2, iclass 23, count 0 2006.239.07:47:51.57#ibcon#flushed, iclass 23, count 0 2006.239.07:47:51.57#ibcon#about to write, iclass 23, count 0 2006.239.07:47:51.57#ibcon#wrote, iclass 23, count 0 2006.239.07:47:51.57#ibcon#about to read 3, iclass 23, count 0 2006.239.07:47:51.60#ibcon#read 3, iclass 23, count 0 2006.239.07:47:51.60#ibcon#about to read 4, iclass 23, count 0 2006.239.07:47:51.60#ibcon#read 4, iclass 23, count 0 2006.239.07:47:51.60#ibcon#about to read 5, iclass 23, count 0 2006.239.07:47:51.60#ibcon#read 5, iclass 23, count 0 2006.239.07:47:51.60#ibcon#about to read 6, iclass 23, count 0 2006.239.07:47:51.60#ibcon#read 6, iclass 23, count 0 2006.239.07:47:51.60#ibcon#end of sib2, iclass 23, count 0 2006.239.07:47:51.60#ibcon#*after write, iclass 23, count 0 2006.239.07:47:51.60#ibcon#*before return 0, iclass 23, count 0 2006.239.07:47:51.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:51.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:47:51.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:47:51.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:47:51.60$vc4f8/vblo=4,712.99 2006.239.07:47:51.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:47:51.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:47:51.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:51.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:51.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:51.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:51.60#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:47:51.60#ibcon#first serial, iclass 25, count 0 2006.239.07:47:51.60#ibcon#enter sib2, iclass 25, count 0 2006.239.07:47:51.60#ibcon#flushed, iclass 25, count 0 2006.239.07:47:51.60#ibcon#about to write, iclass 25, count 0 2006.239.07:47:51.60#ibcon#wrote, iclass 25, count 0 2006.239.07:47:51.60#ibcon#about to read 3, iclass 25, count 0 2006.239.07:47:51.62#ibcon#read 3, iclass 25, count 0 2006.239.07:47:51.62#ibcon#about to read 4, iclass 25, count 0 2006.239.07:47:51.62#ibcon#read 4, iclass 25, count 0 2006.239.07:47:51.62#ibcon#about to read 5, iclass 25, count 0 2006.239.07:47:51.62#ibcon#read 5, iclass 25, count 0 2006.239.07:47:51.62#ibcon#about to read 6, iclass 25, count 0 2006.239.07:47:51.62#ibcon#read 6, iclass 25, count 0 2006.239.07:47:51.62#ibcon#end of sib2, iclass 25, count 0 2006.239.07:47:51.62#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:47:51.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:47:51.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:47:51.62#ibcon#*before write, iclass 25, count 0 2006.239.07:47:51.62#ibcon#enter sib2, iclass 25, count 0 2006.239.07:47:51.62#ibcon#flushed, iclass 25, count 0 2006.239.07:47:51.62#ibcon#about to write, iclass 25, count 0 2006.239.07:47:51.62#ibcon#wrote, iclass 25, count 0 2006.239.07:47:51.62#ibcon#about to read 3, iclass 25, count 0 2006.239.07:47:51.66#ibcon#read 3, iclass 25, count 0 2006.239.07:47:51.66#ibcon#about to read 4, iclass 25, count 0 2006.239.07:47:51.66#ibcon#read 4, iclass 25, count 0 2006.239.07:47:51.66#ibcon#about to read 5, iclass 25, count 0 2006.239.07:47:51.66#ibcon#read 5, iclass 25, count 0 2006.239.07:47:51.66#ibcon#about to read 6, iclass 25, count 0 2006.239.07:47:51.66#ibcon#read 6, iclass 25, count 0 2006.239.07:47:51.66#ibcon#end of sib2, iclass 25, count 0 2006.239.07:47:51.66#ibcon#*after write, iclass 25, count 0 2006.239.07:47:51.66#ibcon#*before return 0, iclass 25, count 0 2006.239.07:47:51.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:51.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:47:51.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:47:51.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:47:51.66$vc4f8/vb=4,4 2006.239.07:47:51.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:47:51.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:47:51.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:51.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:51.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:51.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:51.72#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:47:51.72#ibcon#first serial, iclass 27, count 2 2006.239.07:47:51.72#ibcon#enter sib2, iclass 27, count 2 2006.239.07:47:51.72#ibcon#flushed, iclass 27, count 2 2006.239.07:47:51.72#ibcon#about to write, iclass 27, count 2 2006.239.07:47:51.72#ibcon#wrote, iclass 27, count 2 2006.239.07:47:51.72#ibcon#about to read 3, iclass 27, count 2 2006.239.07:47:51.74#ibcon#read 3, iclass 27, count 2 2006.239.07:47:51.74#ibcon#about to read 4, iclass 27, count 2 2006.239.07:47:51.74#ibcon#read 4, iclass 27, count 2 2006.239.07:47:51.74#ibcon#about to read 5, iclass 27, count 2 2006.239.07:47:51.74#ibcon#read 5, iclass 27, count 2 2006.239.07:47:51.74#ibcon#about to read 6, iclass 27, count 2 2006.239.07:47:51.74#ibcon#read 6, iclass 27, count 2 2006.239.07:47:51.74#ibcon#end of sib2, iclass 27, count 2 2006.239.07:47:51.74#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:47:51.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:47:51.74#ibcon#[27=AT04-04\r\n] 2006.239.07:47:51.74#ibcon#*before write, iclass 27, count 2 2006.239.07:47:51.74#ibcon#enter sib2, iclass 27, count 2 2006.239.07:47:51.74#ibcon#flushed, iclass 27, count 2 2006.239.07:47:51.74#ibcon#about to write, iclass 27, count 2 2006.239.07:47:51.74#ibcon#wrote, iclass 27, count 2 2006.239.07:47:51.74#ibcon#about to read 3, iclass 27, count 2 2006.239.07:47:51.77#ibcon#read 3, iclass 27, count 2 2006.239.07:47:51.77#ibcon#about to read 4, iclass 27, count 2 2006.239.07:47:51.77#ibcon#read 4, iclass 27, count 2 2006.239.07:47:51.77#ibcon#about to read 5, iclass 27, count 2 2006.239.07:47:51.77#ibcon#read 5, iclass 27, count 2 2006.239.07:47:51.77#ibcon#about to read 6, iclass 27, count 2 2006.239.07:47:51.77#ibcon#read 6, iclass 27, count 2 2006.239.07:47:51.77#ibcon#end of sib2, iclass 27, count 2 2006.239.07:47:51.77#ibcon#*after write, iclass 27, count 2 2006.239.07:47:51.77#ibcon#*before return 0, iclass 27, count 2 2006.239.07:47:51.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:51.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:47:51.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:47:51.77#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:51.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:51.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:51.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:51.89#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:47:51.89#ibcon#first serial, iclass 27, count 0 2006.239.07:47:51.89#ibcon#enter sib2, iclass 27, count 0 2006.239.07:47:51.89#ibcon#flushed, iclass 27, count 0 2006.239.07:47:51.89#ibcon#about to write, iclass 27, count 0 2006.239.07:47:51.89#ibcon#wrote, iclass 27, count 0 2006.239.07:47:51.89#ibcon#about to read 3, iclass 27, count 0 2006.239.07:47:51.91#ibcon#read 3, iclass 27, count 0 2006.239.07:47:51.91#ibcon#about to read 4, iclass 27, count 0 2006.239.07:47:51.91#ibcon#read 4, iclass 27, count 0 2006.239.07:47:51.91#ibcon#about to read 5, iclass 27, count 0 2006.239.07:47:51.91#ibcon#read 5, iclass 27, count 0 2006.239.07:47:51.91#ibcon#about to read 6, iclass 27, count 0 2006.239.07:47:51.91#ibcon#read 6, iclass 27, count 0 2006.239.07:47:51.91#ibcon#end of sib2, iclass 27, count 0 2006.239.07:47:51.91#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:47:51.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:47:51.91#ibcon#[27=USB\r\n] 2006.239.07:47:51.91#ibcon#*before write, iclass 27, count 0 2006.239.07:47:51.91#ibcon#enter sib2, iclass 27, count 0 2006.239.07:47:51.91#ibcon#flushed, iclass 27, count 0 2006.239.07:47:51.91#ibcon#about to write, iclass 27, count 0 2006.239.07:47:51.91#ibcon#wrote, iclass 27, count 0 2006.239.07:47:51.91#ibcon#about to read 3, iclass 27, count 0 2006.239.07:47:51.94#ibcon#read 3, iclass 27, count 0 2006.239.07:47:51.94#ibcon#about to read 4, iclass 27, count 0 2006.239.07:47:51.94#ibcon#read 4, iclass 27, count 0 2006.239.07:47:51.94#ibcon#about to read 5, iclass 27, count 0 2006.239.07:47:51.94#ibcon#read 5, iclass 27, count 0 2006.239.07:47:51.94#ibcon#about to read 6, iclass 27, count 0 2006.239.07:47:51.94#ibcon#read 6, iclass 27, count 0 2006.239.07:47:51.94#ibcon#end of sib2, iclass 27, count 0 2006.239.07:47:51.94#ibcon#*after write, iclass 27, count 0 2006.239.07:47:51.94#ibcon#*before return 0, iclass 27, count 0 2006.239.07:47:51.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:51.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:47:51.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:47:51.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:47:51.94$vc4f8/vblo=5,744.99 2006.239.07:47:51.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:47:51.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:47:51.94#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:51.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:51.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:51.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:51.94#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:47:51.94#ibcon#first serial, iclass 29, count 0 2006.239.07:47:51.94#ibcon#enter sib2, iclass 29, count 0 2006.239.07:47:51.94#ibcon#flushed, iclass 29, count 0 2006.239.07:47:51.94#ibcon#about to write, iclass 29, count 0 2006.239.07:47:51.94#ibcon#wrote, iclass 29, count 0 2006.239.07:47:51.94#ibcon#about to read 3, iclass 29, count 0 2006.239.07:47:51.96#ibcon#read 3, iclass 29, count 0 2006.239.07:47:51.96#ibcon#about to read 4, iclass 29, count 0 2006.239.07:47:51.96#ibcon#read 4, iclass 29, count 0 2006.239.07:47:51.96#ibcon#about to read 5, iclass 29, count 0 2006.239.07:47:51.96#ibcon#read 5, iclass 29, count 0 2006.239.07:47:51.96#ibcon#about to read 6, iclass 29, count 0 2006.239.07:47:51.96#ibcon#read 6, iclass 29, count 0 2006.239.07:47:51.96#ibcon#end of sib2, iclass 29, count 0 2006.239.07:47:51.96#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:47:51.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:47:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:47:51.96#ibcon#*before write, iclass 29, count 0 2006.239.07:47:51.96#ibcon#enter sib2, iclass 29, count 0 2006.239.07:47:51.96#ibcon#flushed, iclass 29, count 0 2006.239.07:47:51.96#ibcon#about to write, iclass 29, count 0 2006.239.07:47:51.96#ibcon#wrote, iclass 29, count 0 2006.239.07:47:51.96#ibcon#about to read 3, iclass 29, count 0 2006.239.07:47:52.00#ibcon#read 3, iclass 29, count 0 2006.239.07:47:52.00#ibcon#about to read 4, iclass 29, count 0 2006.239.07:47:52.00#ibcon#read 4, iclass 29, count 0 2006.239.07:47:52.00#ibcon#about to read 5, iclass 29, count 0 2006.239.07:47:52.00#ibcon#read 5, iclass 29, count 0 2006.239.07:47:52.00#ibcon#about to read 6, iclass 29, count 0 2006.239.07:47:52.00#ibcon#read 6, iclass 29, count 0 2006.239.07:47:52.00#ibcon#end of sib2, iclass 29, count 0 2006.239.07:47:52.00#ibcon#*after write, iclass 29, count 0 2006.239.07:47:52.00#ibcon#*before return 0, iclass 29, count 0 2006.239.07:47:52.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:52.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:47:52.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:47:52.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:47:52.00$vc4f8/vb=5,4 2006.239.07:47:52.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:47:52.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:47:52.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:52.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:52.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:52.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:52.06#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:47:52.06#ibcon#first serial, iclass 31, count 2 2006.239.07:47:52.06#ibcon#enter sib2, iclass 31, count 2 2006.239.07:47:52.06#ibcon#flushed, iclass 31, count 2 2006.239.07:47:52.06#ibcon#about to write, iclass 31, count 2 2006.239.07:47:52.06#ibcon#wrote, iclass 31, count 2 2006.239.07:47:52.06#ibcon#about to read 3, iclass 31, count 2 2006.239.07:47:52.08#ibcon#read 3, iclass 31, count 2 2006.239.07:47:52.08#ibcon#about to read 4, iclass 31, count 2 2006.239.07:47:52.08#ibcon#read 4, iclass 31, count 2 2006.239.07:47:52.08#ibcon#about to read 5, iclass 31, count 2 2006.239.07:47:52.08#ibcon#read 5, iclass 31, count 2 2006.239.07:47:52.08#ibcon#about to read 6, iclass 31, count 2 2006.239.07:47:52.08#ibcon#read 6, iclass 31, count 2 2006.239.07:47:52.08#ibcon#end of sib2, iclass 31, count 2 2006.239.07:47:52.08#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:47:52.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:47:52.08#ibcon#[27=AT05-04\r\n] 2006.239.07:47:52.08#ibcon#*before write, iclass 31, count 2 2006.239.07:47:52.08#ibcon#enter sib2, iclass 31, count 2 2006.239.07:47:52.08#ibcon#flushed, iclass 31, count 2 2006.239.07:47:52.08#ibcon#about to write, iclass 31, count 2 2006.239.07:47:52.08#ibcon#wrote, iclass 31, count 2 2006.239.07:47:52.08#ibcon#about to read 3, iclass 31, count 2 2006.239.07:47:52.11#ibcon#read 3, iclass 31, count 2 2006.239.07:47:52.11#ibcon#about to read 4, iclass 31, count 2 2006.239.07:47:52.11#ibcon#read 4, iclass 31, count 2 2006.239.07:47:52.11#ibcon#about to read 5, iclass 31, count 2 2006.239.07:47:52.11#ibcon#read 5, iclass 31, count 2 2006.239.07:47:52.11#ibcon#about to read 6, iclass 31, count 2 2006.239.07:47:52.11#ibcon#read 6, iclass 31, count 2 2006.239.07:47:52.11#ibcon#end of sib2, iclass 31, count 2 2006.239.07:47:52.11#ibcon#*after write, iclass 31, count 2 2006.239.07:47:52.11#ibcon#*before return 0, iclass 31, count 2 2006.239.07:47:52.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:52.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:47:52.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:47:52.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:52.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:52.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:52.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:52.23#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:47:52.23#ibcon#first serial, iclass 31, count 0 2006.239.07:47:52.23#ibcon#enter sib2, iclass 31, count 0 2006.239.07:47:52.23#ibcon#flushed, iclass 31, count 0 2006.239.07:47:52.23#ibcon#about to write, iclass 31, count 0 2006.239.07:47:52.23#ibcon#wrote, iclass 31, count 0 2006.239.07:47:52.23#ibcon#about to read 3, iclass 31, count 0 2006.239.07:47:52.25#ibcon#read 3, iclass 31, count 0 2006.239.07:47:52.25#ibcon#about to read 4, iclass 31, count 0 2006.239.07:47:52.25#ibcon#read 4, iclass 31, count 0 2006.239.07:47:52.25#ibcon#about to read 5, iclass 31, count 0 2006.239.07:47:52.25#ibcon#read 5, iclass 31, count 0 2006.239.07:47:52.25#ibcon#about to read 6, iclass 31, count 0 2006.239.07:47:52.25#ibcon#read 6, iclass 31, count 0 2006.239.07:47:52.25#ibcon#end of sib2, iclass 31, count 0 2006.239.07:47:52.25#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:47:52.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:47:52.25#ibcon#[27=USB\r\n] 2006.239.07:47:52.25#ibcon#*before write, iclass 31, count 0 2006.239.07:47:52.25#ibcon#enter sib2, iclass 31, count 0 2006.239.07:47:52.25#ibcon#flushed, iclass 31, count 0 2006.239.07:47:52.25#ibcon#about to write, iclass 31, count 0 2006.239.07:47:52.25#ibcon#wrote, iclass 31, count 0 2006.239.07:47:52.25#ibcon#about to read 3, iclass 31, count 0 2006.239.07:47:52.28#ibcon#read 3, iclass 31, count 0 2006.239.07:47:52.28#ibcon#about to read 4, iclass 31, count 0 2006.239.07:47:52.28#ibcon#read 4, iclass 31, count 0 2006.239.07:47:52.28#ibcon#about to read 5, iclass 31, count 0 2006.239.07:47:52.28#ibcon#read 5, iclass 31, count 0 2006.239.07:47:52.28#ibcon#about to read 6, iclass 31, count 0 2006.239.07:47:52.28#ibcon#read 6, iclass 31, count 0 2006.239.07:47:52.28#ibcon#end of sib2, iclass 31, count 0 2006.239.07:47:52.28#ibcon#*after write, iclass 31, count 0 2006.239.07:47:52.28#ibcon#*before return 0, iclass 31, count 0 2006.239.07:47:52.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:52.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:47:52.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:47:52.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:47:52.28$vc4f8/vblo=6,752.99 2006.239.07:47:52.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:47:52.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:47:52.28#ibcon#ireg 17 cls_cnt 0 2006.239.07:47:52.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:52.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:52.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:52.28#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:47:52.28#ibcon#first serial, iclass 33, count 0 2006.239.07:47:52.28#ibcon#enter sib2, iclass 33, count 0 2006.239.07:47:52.28#ibcon#flushed, iclass 33, count 0 2006.239.07:47:52.28#ibcon#about to write, iclass 33, count 0 2006.239.07:47:52.28#ibcon#wrote, iclass 33, count 0 2006.239.07:47:52.28#ibcon#about to read 3, iclass 33, count 0 2006.239.07:47:52.30#ibcon#read 3, iclass 33, count 0 2006.239.07:47:52.30#ibcon#about to read 4, iclass 33, count 0 2006.239.07:47:52.30#ibcon#read 4, iclass 33, count 0 2006.239.07:47:52.30#ibcon#about to read 5, iclass 33, count 0 2006.239.07:47:52.30#ibcon#read 5, iclass 33, count 0 2006.239.07:47:52.30#ibcon#about to read 6, iclass 33, count 0 2006.239.07:47:52.30#ibcon#read 6, iclass 33, count 0 2006.239.07:47:52.30#ibcon#end of sib2, iclass 33, count 0 2006.239.07:47:52.30#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:47:52.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:47:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:47:52.30#ibcon#*before write, iclass 33, count 0 2006.239.07:47:52.30#ibcon#enter sib2, iclass 33, count 0 2006.239.07:47:52.30#ibcon#flushed, iclass 33, count 0 2006.239.07:47:52.30#ibcon#about to write, iclass 33, count 0 2006.239.07:47:52.30#ibcon#wrote, iclass 33, count 0 2006.239.07:47:52.30#ibcon#about to read 3, iclass 33, count 0 2006.239.07:47:52.34#ibcon#read 3, iclass 33, count 0 2006.239.07:47:52.34#ibcon#about to read 4, iclass 33, count 0 2006.239.07:47:52.34#ibcon#read 4, iclass 33, count 0 2006.239.07:47:52.34#ibcon#about to read 5, iclass 33, count 0 2006.239.07:47:52.34#ibcon#read 5, iclass 33, count 0 2006.239.07:47:52.34#ibcon#about to read 6, iclass 33, count 0 2006.239.07:47:52.34#ibcon#read 6, iclass 33, count 0 2006.239.07:47:52.34#ibcon#end of sib2, iclass 33, count 0 2006.239.07:47:52.34#ibcon#*after write, iclass 33, count 0 2006.239.07:47:52.34#ibcon#*before return 0, iclass 33, count 0 2006.239.07:47:52.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:52.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:47:52.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:47:52.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:47:52.34$vc4f8/vb=6,4 2006.239.07:47:52.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:47:52.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:47:52.34#ibcon#ireg 11 cls_cnt 2 2006.239.07:47:52.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:52.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:52.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:52.40#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:47:52.40#ibcon#first serial, iclass 35, count 2 2006.239.07:47:52.40#ibcon#enter sib2, iclass 35, count 2 2006.239.07:47:52.40#ibcon#flushed, iclass 35, count 2 2006.239.07:47:52.40#ibcon#about to write, iclass 35, count 2 2006.239.07:47:52.40#ibcon#wrote, iclass 35, count 2 2006.239.07:47:52.40#ibcon#about to read 3, iclass 35, count 2 2006.239.07:47:52.42#ibcon#read 3, iclass 35, count 2 2006.239.07:47:52.42#ibcon#about to read 4, iclass 35, count 2 2006.239.07:47:52.42#ibcon#read 4, iclass 35, count 2 2006.239.07:47:52.42#ibcon#about to read 5, iclass 35, count 2 2006.239.07:47:52.42#ibcon#read 5, iclass 35, count 2 2006.239.07:47:52.42#ibcon#about to read 6, iclass 35, count 2 2006.239.07:47:52.42#ibcon#read 6, iclass 35, count 2 2006.239.07:47:52.42#ibcon#end of sib2, iclass 35, count 2 2006.239.07:47:52.42#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:47:52.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:47:52.42#ibcon#[27=AT06-04\r\n] 2006.239.07:47:52.42#ibcon#*before write, iclass 35, count 2 2006.239.07:47:52.42#ibcon#enter sib2, iclass 35, count 2 2006.239.07:47:52.42#ibcon#flushed, iclass 35, count 2 2006.239.07:47:52.42#ibcon#about to write, iclass 35, count 2 2006.239.07:47:52.42#ibcon#wrote, iclass 35, count 2 2006.239.07:47:52.42#ibcon#about to read 3, iclass 35, count 2 2006.239.07:47:52.45#ibcon#read 3, iclass 35, count 2 2006.239.07:47:52.45#ibcon#about to read 4, iclass 35, count 2 2006.239.07:47:52.45#ibcon#read 4, iclass 35, count 2 2006.239.07:47:52.45#ibcon#about to read 5, iclass 35, count 2 2006.239.07:47:52.45#ibcon#read 5, iclass 35, count 2 2006.239.07:47:52.45#ibcon#about to read 6, iclass 35, count 2 2006.239.07:47:52.45#ibcon#read 6, iclass 35, count 2 2006.239.07:47:52.45#ibcon#end of sib2, iclass 35, count 2 2006.239.07:47:52.45#ibcon#*after write, iclass 35, count 2 2006.239.07:47:52.45#ibcon#*before return 0, iclass 35, count 2 2006.239.07:47:52.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:52.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:47:52.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:47:52.45#ibcon#ireg 7 cls_cnt 0 2006.239.07:47:52.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:52.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:52.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:52.58#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:47:52.58#ibcon#first serial, iclass 35, count 0 2006.239.07:47:52.58#ibcon#enter sib2, iclass 35, count 0 2006.239.07:47:52.58#ibcon#flushed, iclass 35, count 0 2006.239.07:47:52.58#ibcon#about to write, iclass 35, count 0 2006.239.07:47:52.58#ibcon#wrote, iclass 35, count 0 2006.239.07:47:52.58#ibcon#about to read 3, iclass 35, count 0 2006.239.07:47:52.59#ibcon#read 3, iclass 35, count 0 2006.239.07:47:52.59#ibcon#about to read 4, iclass 35, count 0 2006.239.07:47:52.59#ibcon#read 4, iclass 35, count 0 2006.239.07:47:52.59#ibcon#about to read 5, iclass 35, count 0 2006.239.07:47:52.59#ibcon#read 5, iclass 35, count 0 2006.239.07:47:52.59#ibcon#about to read 6, iclass 35, count 0 2006.239.07:47:52.59#ibcon#read 6, iclass 35, count 0 2006.239.07:47:52.59#ibcon#end of sib2, iclass 35, count 0 2006.239.07:47:52.59#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:47:52.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:47:52.59#ibcon#[27=USB\r\n] 2006.239.07:47:52.59#ibcon#*before write, iclass 35, count 0 2006.239.07:47:52.59#ibcon#enter sib2, iclass 35, count 0 2006.239.07:47:52.59#ibcon#flushed, iclass 35, count 0 2006.239.07:47:52.59#ibcon#about to write, iclass 35, count 0 2006.239.07:47:52.59#ibcon#wrote, iclass 35, count 0 2006.239.07:47:52.59#ibcon#about to read 3, iclass 35, count 0 2006.239.07:47:52.62#ibcon#read 3, iclass 35, count 0 2006.239.07:47:52.62#ibcon#about to read 4, iclass 35, count 0 2006.239.07:47:52.62#ibcon#read 4, iclass 35, count 0 2006.239.07:47:52.62#ibcon#about to read 5, iclass 35, count 0 2006.239.07:47:52.62#ibcon#read 5, iclass 35, count 0 2006.239.07:47:52.62#ibcon#about to read 6, iclass 35, count 0 2006.239.07:47:52.62#ibcon#read 6, iclass 35, count 0 2006.239.07:47:52.62#ibcon#end of sib2, iclass 35, count 0 2006.239.07:47:52.62#ibcon#*after write, iclass 35, count 0 2006.239.07:47:52.62#ibcon#*before return 0, iclass 35, count 0 2006.239.07:47:52.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:52.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:47:52.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:47:52.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:47:52.62$vc4f8/vabw=wide 2006.239.07:47:52.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:47:52.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:47:52.62#ibcon#ireg 8 cls_cnt 0 2006.239.07:47:52.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:52.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:52.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:52.62#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:47:52.62#ibcon#first serial, iclass 37, count 0 2006.239.07:47:52.62#ibcon#enter sib2, iclass 37, count 0 2006.239.07:47:52.62#ibcon#flushed, iclass 37, count 0 2006.239.07:47:52.62#ibcon#about to write, iclass 37, count 0 2006.239.07:47:52.62#ibcon#wrote, iclass 37, count 0 2006.239.07:47:52.62#ibcon#about to read 3, iclass 37, count 0 2006.239.07:47:52.64#ibcon#read 3, iclass 37, count 0 2006.239.07:47:52.64#ibcon#about to read 4, iclass 37, count 0 2006.239.07:47:52.64#ibcon#read 4, iclass 37, count 0 2006.239.07:47:52.64#ibcon#about to read 5, iclass 37, count 0 2006.239.07:47:52.64#ibcon#read 5, iclass 37, count 0 2006.239.07:47:52.64#ibcon#about to read 6, iclass 37, count 0 2006.239.07:47:52.64#ibcon#read 6, iclass 37, count 0 2006.239.07:47:52.64#ibcon#end of sib2, iclass 37, count 0 2006.239.07:47:52.64#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:47:52.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:47:52.64#ibcon#[25=BW32\r\n] 2006.239.07:47:52.64#ibcon#*before write, iclass 37, count 0 2006.239.07:47:52.64#ibcon#enter sib2, iclass 37, count 0 2006.239.07:47:52.64#ibcon#flushed, iclass 37, count 0 2006.239.07:47:52.64#ibcon#about to write, iclass 37, count 0 2006.239.07:47:52.64#ibcon#wrote, iclass 37, count 0 2006.239.07:47:52.64#ibcon#about to read 3, iclass 37, count 0 2006.239.07:47:52.67#ibcon#read 3, iclass 37, count 0 2006.239.07:47:52.67#ibcon#about to read 4, iclass 37, count 0 2006.239.07:47:52.67#ibcon#read 4, iclass 37, count 0 2006.239.07:47:52.67#ibcon#about to read 5, iclass 37, count 0 2006.239.07:47:52.67#ibcon#read 5, iclass 37, count 0 2006.239.07:47:52.67#ibcon#about to read 6, iclass 37, count 0 2006.239.07:47:52.67#ibcon#read 6, iclass 37, count 0 2006.239.07:47:52.67#ibcon#end of sib2, iclass 37, count 0 2006.239.07:47:52.67#ibcon#*after write, iclass 37, count 0 2006.239.07:47:52.67#ibcon#*before return 0, iclass 37, count 0 2006.239.07:47:52.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:52.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:47:52.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:47:52.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:47:52.67$vc4f8/vbbw=wide 2006.239.07:47:52.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.07:47:52.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.07:47:52.67#ibcon#ireg 8 cls_cnt 0 2006.239.07:47:52.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:47:52.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:47:52.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:47:52.74#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:47:52.74#ibcon#first serial, iclass 39, count 0 2006.239.07:47:52.74#ibcon#enter sib2, iclass 39, count 0 2006.239.07:47:52.74#ibcon#flushed, iclass 39, count 0 2006.239.07:47:52.74#ibcon#about to write, iclass 39, count 0 2006.239.07:47:52.74#ibcon#wrote, iclass 39, count 0 2006.239.07:47:52.74#ibcon#about to read 3, iclass 39, count 0 2006.239.07:47:52.76#ibcon#read 3, iclass 39, count 0 2006.239.07:47:52.76#ibcon#about to read 4, iclass 39, count 0 2006.239.07:47:52.76#ibcon#read 4, iclass 39, count 0 2006.239.07:47:52.76#ibcon#about to read 5, iclass 39, count 0 2006.239.07:47:52.76#ibcon#read 5, iclass 39, count 0 2006.239.07:47:52.76#ibcon#about to read 6, iclass 39, count 0 2006.239.07:47:52.76#ibcon#read 6, iclass 39, count 0 2006.239.07:47:52.76#ibcon#end of sib2, iclass 39, count 0 2006.239.07:47:52.76#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:47:52.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:47:52.76#ibcon#[27=BW32\r\n] 2006.239.07:47:52.76#ibcon#*before write, iclass 39, count 0 2006.239.07:47:52.76#ibcon#enter sib2, iclass 39, count 0 2006.239.07:47:52.76#ibcon#flushed, iclass 39, count 0 2006.239.07:47:52.76#ibcon#about to write, iclass 39, count 0 2006.239.07:47:52.76#ibcon#wrote, iclass 39, count 0 2006.239.07:47:52.76#ibcon#about to read 3, iclass 39, count 0 2006.239.07:47:52.79#ibcon#read 3, iclass 39, count 0 2006.239.07:47:52.79#ibcon#about to read 4, iclass 39, count 0 2006.239.07:47:52.79#ibcon#read 4, iclass 39, count 0 2006.239.07:47:52.79#ibcon#about to read 5, iclass 39, count 0 2006.239.07:47:52.79#ibcon#read 5, iclass 39, count 0 2006.239.07:47:52.79#ibcon#about to read 6, iclass 39, count 0 2006.239.07:47:52.79#ibcon#read 6, iclass 39, count 0 2006.239.07:47:52.79#ibcon#end of sib2, iclass 39, count 0 2006.239.07:47:52.79#ibcon#*after write, iclass 39, count 0 2006.239.07:47:52.79#ibcon#*before return 0, iclass 39, count 0 2006.239.07:47:52.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:47:52.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:47:52.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:47:52.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:47:52.79$4f8m12a/ifd4f 2006.239.07:47:52.79$ifd4f/lo= 2006.239.07:47:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:47:52.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:47:52.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:47:52.79$ifd4f/patch= 2006.239.07:47:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:47:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:47:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:47:52.79$4f8m12a/"form=m,16.000,1:2 2006.239.07:47:52.79$4f8m12a/"tpicd 2006.239.07:47:52.79$4f8m12a/echo=off 2006.239.07:47:52.79$4f8m12a/xlog=off 2006.239.07:47:52.79:!2006.239.07:48:20 2006.239.07:48:02.14#trakl#Source acquired 2006.239.07:48:02.14#flagr#flagr/antenna,acquired 2006.239.07:48:20.00:preob 2006.239.07:48:21.14/onsource/TRACKING 2006.239.07:48:21.14:!2006.239.07:48:30 2006.239.07:48:30.00:data_valid=on 2006.239.07:48:30.00:midob 2006.239.07:48:30.13/onsource/TRACKING 2006.239.07:48:30.13/wx/25.28,1011.5,80 2006.239.07:48:30.34/cable/+6.4130E-03 2006.239.07:48:31.43/va/01,08,usb,yes,31,32 2006.239.07:48:31.43/va/02,07,usb,yes,31,32 2006.239.07:48:31.43/va/03,07,usb,yes,29,29 2006.239.07:48:31.43/va/04,07,usb,yes,32,35 2006.239.07:48:31.43/va/05,08,usb,yes,29,31 2006.239.07:48:31.43/va/06,07,usb,yes,32,32 2006.239.07:48:31.43/va/07,07,usb,yes,32,31 2006.239.07:48:31.43/va/08,07,usb,yes,34,34 2006.239.07:48:31.66/valo/01,532.99,yes,locked 2006.239.07:48:31.66/valo/02,572.99,yes,locked 2006.239.07:48:31.66/valo/03,672.99,yes,locked 2006.239.07:48:31.66/valo/04,832.99,yes,locked 2006.239.07:48:31.66/valo/05,652.99,yes,locked 2006.239.07:48:31.66/valo/06,772.99,yes,locked 2006.239.07:48:31.66/valo/07,832.99,yes,locked 2006.239.07:48:31.66/valo/08,852.99,yes,locked 2006.239.07:48:32.75/vb/01,04,usb,yes,30,29 2006.239.07:48:32.75/vb/02,04,usb,yes,32,34 2006.239.07:48:32.75/vb/03,04,usb,yes,29,32 2006.239.07:48:32.75/vb/04,04,usb,yes,29,30 2006.239.07:48:32.75/vb/05,04,usb,yes,28,32 2006.239.07:48:32.75/vb/06,04,usb,yes,29,32 2006.239.07:48:32.75/vb/07,04,usb,yes,31,31 2006.239.07:48:32.75/vb/08,04,usb,yes,28,32 2006.239.07:48:32.99/vblo/01,632.99,yes,locked 2006.239.07:48:32.99/vblo/02,640.99,yes,locked 2006.239.07:48:32.99/vblo/03,656.99,yes,locked 2006.239.07:48:32.99/vblo/04,712.99,yes,locked 2006.239.07:48:32.99/vblo/05,744.99,yes,locked 2006.239.07:48:32.99/vblo/06,752.99,yes,locked 2006.239.07:48:32.99/vblo/07,734.99,yes,locked 2006.239.07:48:32.99/vblo/08,744.99,yes,locked 2006.239.07:48:33.14/vabw/8 2006.239.07:48:33.29/vbbw/8 2006.239.07:48:33.41/xfe/off,on,13.2 2006.239.07:48:33.79/ifatt/23,28,28,28 2006.239.07:48:34.07/fmout-gps/S +4.42E-07 2006.239.07:48:34.11:!2006.239.07:49:30 2006.239.07:49:30.00:data_valid=off 2006.239.07:49:30.00:postob 2006.239.07:49:30.06/cable/+6.4138E-03 2006.239.07:49:30.06/wx/25.27,1011.5,80 2006.239.07:49:31.08/fmout-gps/S +4.42E-07 2006.239.07:49:31.08:scan_name=239-0750,k06239,60 2006.239.07:49:31.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.239.07:49:32.13#flagr#flagr/antenna,new-source 2006.239.07:49:32.13:checkk5 2006.239.07:49:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:49:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:49:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:49:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:49:34.03/chk_obsdata//k5ts1/T2390748??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:49:34.40/chk_obsdata//k5ts2/T2390748??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:49:34.77/chk_obsdata//k5ts3/T2390748??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:49:35.15/chk_obsdata//k5ts4/T2390748??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:49:35.85/k5log//k5ts1_log_newline 2006.239.07:49:36.53/k5log//k5ts2_log_newline 2006.239.07:49:37.22/k5log//k5ts3_log_newline 2006.239.07:49:37.92/k5log//k5ts4_log_newline 2006.239.07:49:37.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:49:37.94:4f8m12a=1 2006.239.07:49:37.94$4f8m12a/echo=on 2006.239.07:49:37.94$4f8m12a/pcalon 2006.239.07:49:37.94$pcalon/"no phase cal control is implemented here 2006.239.07:49:37.94$4f8m12a/"tpicd=stop 2006.239.07:49:37.94$4f8m12a/vc4f8 2006.239.07:49:37.94$vc4f8/valo=1,532.99 2006.239.07:49:37.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:49:37.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:49:37.94#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:37.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:37.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:37.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:37.94#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:49:37.94#ibcon#first serial, iclass 10, count 0 2006.239.07:49:37.94#ibcon#enter sib2, iclass 10, count 0 2006.239.07:49:37.94#ibcon#flushed, iclass 10, count 0 2006.239.07:49:37.94#ibcon#about to write, iclass 10, count 0 2006.239.07:49:37.94#ibcon#wrote, iclass 10, count 0 2006.239.07:49:37.94#ibcon#about to read 3, iclass 10, count 0 2006.239.07:49:37.99#ibcon#read 3, iclass 10, count 0 2006.239.07:49:37.99#ibcon#about to read 4, iclass 10, count 0 2006.239.07:49:37.99#ibcon#read 4, iclass 10, count 0 2006.239.07:49:37.99#ibcon#about to read 5, iclass 10, count 0 2006.239.07:49:37.99#ibcon#read 5, iclass 10, count 0 2006.239.07:49:37.99#ibcon#about to read 6, iclass 10, count 0 2006.239.07:49:37.99#ibcon#read 6, iclass 10, count 0 2006.239.07:49:37.99#ibcon#end of sib2, iclass 10, count 0 2006.239.07:49:37.99#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:49:37.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:49:37.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:49:37.99#ibcon#*before write, iclass 10, count 0 2006.239.07:49:37.99#ibcon#enter sib2, iclass 10, count 0 2006.239.07:49:37.99#ibcon#flushed, iclass 10, count 0 2006.239.07:49:37.99#ibcon#about to write, iclass 10, count 0 2006.239.07:49:37.99#ibcon#wrote, iclass 10, count 0 2006.239.07:49:37.99#ibcon#about to read 3, iclass 10, count 0 2006.239.07:49:38.04#ibcon#read 3, iclass 10, count 0 2006.239.07:49:38.04#ibcon#about to read 4, iclass 10, count 0 2006.239.07:49:38.04#ibcon#read 4, iclass 10, count 0 2006.239.07:49:38.04#ibcon#about to read 5, iclass 10, count 0 2006.239.07:49:38.04#ibcon#read 5, iclass 10, count 0 2006.239.07:49:38.04#ibcon#about to read 6, iclass 10, count 0 2006.239.07:49:38.04#ibcon#read 6, iclass 10, count 0 2006.239.07:49:38.04#ibcon#end of sib2, iclass 10, count 0 2006.239.07:49:38.04#ibcon#*after write, iclass 10, count 0 2006.239.07:49:38.04#ibcon#*before return 0, iclass 10, count 0 2006.239.07:49:38.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:38.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:38.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:49:38.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:49:38.04$vc4f8/va=1,8 2006.239.07:49:38.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.07:49:38.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.07:49:38.04#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:38.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:38.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:38.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:38.04#ibcon#enter wrdev, iclass 12, count 2 2006.239.07:49:38.04#ibcon#first serial, iclass 12, count 2 2006.239.07:49:38.04#ibcon#enter sib2, iclass 12, count 2 2006.239.07:49:38.04#ibcon#flushed, iclass 12, count 2 2006.239.07:49:38.04#ibcon#about to write, iclass 12, count 2 2006.239.07:49:38.04#ibcon#wrote, iclass 12, count 2 2006.239.07:49:38.04#ibcon#about to read 3, iclass 12, count 2 2006.239.07:49:38.06#ibcon#read 3, iclass 12, count 2 2006.239.07:49:38.06#ibcon#about to read 4, iclass 12, count 2 2006.239.07:49:38.06#ibcon#read 4, iclass 12, count 2 2006.239.07:49:38.06#ibcon#about to read 5, iclass 12, count 2 2006.239.07:49:38.06#ibcon#read 5, iclass 12, count 2 2006.239.07:49:38.06#ibcon#about to read 6, iclass 12, count 2 2006.239.07:49:38.06#ibcon#read 6, iclass 12, count 2 2006.239.07:49:38.06#ibcon#end of sib2, iclass 12, count 2 2006.239.07:49:38.06#ibcon#*mode == 0, iclass 12, count 2 2006.239.07:49:38.06#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.07:49:38.06#ibcon#[25=AT01-08\r\n] 2006.239.07:49:38.06#ibcon#*before write, iclass 12, count 2 2006.239.07:49:38.06#ibcon#enter sib2, iclass 12, count 2 2006.239.07:49:38.06#ibcon#flushed, iclass 12, count 2 2006.239.07:49:38.06#ibcon#about to write, iclass 12, count 2 2006.239.07:49:38.06#ibcon#wrote, iclass 12, count 2 2006.239.07:49:38.06#ibcon#about to read 3, iclass 12, count 2 2006.239.07:49:38.09#ibcon#read 3, iclass 12, count 2 2006.239.07:49:38.09#ibcon#about to read 4, iclass 12, count 2 2006.239.07:49:38.09#ibcon#read 4, iclass 12, count 2 2006.239.07:49:38.09#ibcon#about to read 5, iclass 12, count 2 2006.239.07:49:38.09#ibcon#read 5, iclass 12, count 2 2006.239.07:49:38.09#ibcon#about to read 6, iclass 12, count 2 2006.239.07:49:38.09#ibcon#read 6, iclass 12, count 2 2006.239.07:49:38.09#ibcon#end of sib2, iclass 12, count 2 2006.239.07:49:38.09#ibcon#*after write, iclass 12, count 2 2006.239.07:49:38.09#ibcon#*before return 0, iclass 12, count 2 2006.239.07:49:38.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:38.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:38.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.07:49:38.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:38.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:38.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:38.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:38.21#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:49:38.21#ibcon#first serial, iclass 12, count 0 2006.239.07:49:38.21#ibcon#enter sib2, iclass 12, count 0 2006.239.07:49:38.21#ibcon#flushed, iclass 12, count 0 2006.239.07:49:38.21#ibcon#about to write, iclass 12, count 0 2006.239.07:49:38.21#ibcon#wrote, iclass 12, count 0 2006.239.07:49:38.21#ibcon#about to read 3, iclass 12, count 0 2006.239.07:49:38.23#ibcon#read 3, iclass 12, count 0 2006.239.07:49:38.23#ibcon#about to read 4, iclass 12, count 0 2006.239.07:49:38.23#ibcon#read 4, iclass 12, count 0 2006.239.07:49:38.23#ibcon#about to read 5, iclass 12, count 0 2006.239.07:49:38.23#ibcon#read 5, iclass 12, count 0 2006.239.07:49:38.23#ibcon#about to read 6, iclass 12, count 0 2006.239.07:49:38.23#ibcon#read 6, iclass 12, count 0 2006.239.07:49:38.23#ibcon#end of sib2, iclass 12, count 0 2006.239.07:49:38.23#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:49:38.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:49:38.23#ibcon#[25=USB\r\n] 2006.239.07:49:38.23#ibcon#*before write, iclass 12, count 0 2006.239.07:49:38.23#ibcon#enter sib2, iclass 12, count 0 2006.239.07:49:38.23#ibcon#flushed, iclass 12, count 0 2006.239.07:49:38.23#ibcon#about to write, iclass 12, count 0 2006.239.07:49:38.23#ibcon#wrote, iclass 12, count 0 2006.239.07:49:38.23#ibcon#about to read 3, iclass 12, count 0 2006.239.07:49:38.26#ibcon#read 3, iclass 12, count 0 2006.239.07:49:38.26#ibcon#about to read 4, iclass 12, count 0 2006.239.07:49:38.26#ibcon#read 4, iclass 12, count 0 2006.239.07:49:38.26#ibcon#about to read 5, iclass 12, count 0 2006.239.07:49:38.26#ibcon#read 5, iclass 12, count 0 2006.239.07:49:38.26#ibcon#about to read 6, iclass 12, count 0 2006.239.07:49:38.26#ibcon#read 6, iclass 12, count 0 2006.239.07:49:38.26#ibcon#end of sib2, iclass 12, count 0 2006.239.07:49:38.26#ibcon#*after write, iclass 12, count 0 2006.239.07:49:38.26#ibcon#*before return 0, iclass 12, count 0 2006.239.07:49:38.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:38.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:38.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:49:38.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:49:38.26$vc4f8/valo=2,572.99 2006.239.07:49:38.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:49:38.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:49:38.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:38.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:38.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:38.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:38.26#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:49:38.26#ibcon#first serial, iclass 14, count 0 2006.239.07:49:38.26#ibcon#enter sib2, iclass 14, count 0 2006.239.07:49:38.26#ibcon#flushed, iclass 14, count 0 2006.239.07:49:38.26#ibcon#about to write, iclass 14, count 0 2006.239.07:49:38.26#ibcon#wrote, iclass 14, count 0 2006.239.07:49:38.26#ibcon#about to read 3, iclass 14, count 0 2006.239.07:49:38.28#ibcon#read 3, iclass 14, count 0 2006.239.07:49:38.28#ibcon#about to read 4, iclass 14, count 0 2006.239.07:49:38.28#ibcon#read 4, iclass 14, count 0 2006.239.07:49:38.28#ibcon#about to read 5, iclass 14, count 0 2006.239.07:49:38.28#ibcon#read 5, iclass 14, count 0 2006.239.07:49:38.28#ibcon#about to read 6, iclass 14, count 0 2006.239.07:49:38.28#ibcon#read 6, iclass 14, count 0 2006.239.07:49:38.28#ibcon#end of sib2, iclass 14, count 0 2006.239.07:49:38.28#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:49:38.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:49:38.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:49:38.28#ibcon#*before write, iclass 14, count 0 2006.239.07:49:38.28#ibcon#enter sib2, iclass 14, count 0 2006.239.07:49:38.28#ibcon#flushed, iclass 14, count 0 2006.239.07:49:38.28#ibcon#about to write, iclass 14, count 0 2006.239.07:49:38.28#ibcon#wrote, iclass 14, count 0 2006.239.07:49:38.28#ibcon#about to read 3, iclass 14, count 0 2006.239.07:49:38.32#ibcon#read 3, iclass 14, count 0 2006.239.07:49:38.32#ibcon#about to read 4, iclass 14, count 0 2006.239.07:49:38.32#ibcon#read 4, iclass 14, count 0 2006.239.07:49:38.32#ibcon#about to read 5, iclass 14, count 0 2006.239.07:49:38.32#ibcon#read 5, iclass 14, count 0 2006.239.07:49:38.32#ibcon#about to read 6, iclass 14, count 0 2006.239.07:49:38.32#ibcon#read 6, iclass 14, count 0 2006.239.07:49:38.32#ibcon#end of sib2, iclass 14, count 0 2006.239.07:49:38.32#ibcon#*after write, iclass 14, count 0 2006.239.07:49:38.32#ibcon#*before return 0, iclass 14, count 0 2006.239.07:49:38.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:38.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:38.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:49:38.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:49:38.32$vc4f8/va=2,7 2006.239.07:49:38.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:49:38.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:49:38.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:38.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:38.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:38.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:38.38#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:49:38.38#ibcon#first serial, iclass 16, count 2 2006.239.07:49:38.38#ibcon#enter sib2, iclass 16, count 2 2006.239.07:49:38.38#ibcon#flushed, iclass 16, count 2 2006.239.07:49:38.38#ibcon#about to write, iclass 16, count 2 2006.239.07:49:38.38#ibcon#wrote, iclass 16, count 2 2006.239.07:49:38.38#ibcon#about to read 3, iclass 16, count 2 2006.239.07:49:38.40#ibcon#read 3, iclass 16, count 2 2006.239.07:49:38.40#ibcon#about to read 4, iclass 16, count 2 2006.239.07:49:38.40#ibcon#read 4, iclass 16, count 2 2006.239.07:49:38.40#ibcon#about to read 5, iclass 16, count 2 2006.239.07:49:38.40#ibcon#read 5, iclass 16, count 2 2006.239.07:49:38.40#ibcon#about to read 6, iclass 16, count 2 2006.239.07:49:38.40#ibcon#read 6, iclass 16, count 2 2006.239.07:49:38.40#ibcon#end of sib2, iclass 16, count 2 2006.239.07:49:38.40#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:49:38.40#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:49:38.40#ibcon#[25=AT02-07\r\n] 2006.239.07:49:38.40#ibcon#*before write, iclass 16, count 2 2006.239.07:49:38.40#ibcon#enter sib2, iclass 16, count 2 2006.239.07:49:38.40#ibcon#flushed, iclass 16, count 2 2006.239.07:49:38.40#ibcon#about to write, iclass 16, count 2 2006.239.07:49:38.40#ibcon#wrote, iclass 16, count 2 2006.239.07:49:38.40#ibcon#about to read 3, iclass 16, count 2 2006.239.07:49:38.43#ibcon#read 3, iclass 16, count 2 2006.239.07:49:38.43#ibcon#about to read 4, iclass 16, count 2 2006.239.07:49:38.43#ibcon#read 4, iclass 16, count 2 2006.239.07:49:38.43#ibcon#about to read 5, iclass 16, count 2 2006.239.07:49:38.43#ibcon#read 5, iclass 16, count 2 2006.239.07:49:38.43#ibcon#about to read 6, iclass 16, count 2 2006.239.07:49:38.43#ibcon#read 6, iclass 16, count 2 2006.239.07:49:38.43#ibcon#end of sib2, iclass 16, count 2 2006.239.07:49:38.43#ibcon#*after write, iclass 16, count 2 2006.239.07:49:38.43#ibcon#*before return 0, iclass 16, count 2 2006.239.07:49:38.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:38.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:38.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:49:38.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:38.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:38.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:38.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:38.55#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:49:38.55#ibcon#first serial, iclass 16, count 0 2006.239.07:49:38.55#ibcon#enter sib2, iclass 16, count 0 2006.239.07:49:38.55#ibcon#flushed, iclass 16, count 0 2006.239.07:49:38.55#ibcon#about to write, iclass 16, count 0 2006.239.07:49:38.55#ibcon#wrote, iclass 16, count 0 2006.239.07:49:38.55#ibcon#about to read 3, iclass 16, count 0 2006.239.07:49:38.58#ibcon#read 3, iclass 16, count 0 2006.239.07:49:38.58#ibcon#about to read 4, iclass 16, count 0 2006.239.07:49:38.58#ibcon#read 4, iclass 16, count 0 2006.239.07:49:38.58#ibcon#about to read 5, iclass 16, count 0 2006.239.07:49:38.58#ibcon#read 5, iclass 16, count 0 2006.239.07:49:38.58#ibcon#about to read 6, iclass 16, count 0 2006.239.07:49:38.58#ibcon#read 6, iclass 16, count 0 2006.239.07:49:38.58#ibcon#end of sib2, iclass 16, count 0 2006.239.07:49:38.58#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:49:38.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:49:38.58#ibcon#[25=USB\r\n] 2006.239.07:49:38.58#ibcon#*before write, iclass 16, count 0 2006.239.07:49:38.58#ibcon#enter sib2, iclass 16, count 0 2006.239.07:49:38.58#ibcon#flushed, iclass 16, count 0 2006.239.07:49:38.58#ibcon#about to write, iclass 16, count 0 2006.239.07:49:38.58#ibcon#wrote, iclass 16, count 0 2006.239.07:49:38.58#ibcon#about to read 3, iclass 16, count 0 2006.239.07:49:38.61#ibcon#read 3, iclass 16, count 0 2006.239.07:49:38.61#ibcon#about to read 4, iclass 16, count 0 2006.239.07:49:38.61#ibcon#read 4, iclass 16, count 0 2006.239.07:49:38.61#ibcon#about to read 5, iclass 16, count 0 2006.239.07:49:38.61#ibcon#read 5, iclass 16, count 0 2006.239.07:49:38.61#ibcon#about to read 6, iclass 16, count 0 2006.239.07:49:38.61#ibcon#read 6, iclass 16, count 0 2006.239.07:49:38.61#ibcon#end of sib2, iclass 16, count 0 2006.239.07:49:38.61#ibcon#*after write, iclass 16, count 0 2006.239.07:49:38.61#ibcon#*before return 0, iclass 16, count 0 2006.239.07:49:38.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:38.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:38.61#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:49:38.61#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:49:38.61$vc4f8/valo=3,672.99 2006.239.07:49:38.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.07:49:38.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.07:49:38.61#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:38.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:38.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:38.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:38.61#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:49:38.61#ibcon#first serial, iclass 18, count 0 2006.239.07:49:38.61#ibcon#enter sib2, iclass 18, count 0 2006.239.07:49:38.61#ibcon#flushed, iclass 18, count 0 2006.239.07:49:38.61#ibcon#about to write, iclass 18, count 0 2006.239.07:49:38.61#ibcon#wrote, iclass 18, count 0 2006.239.07:49:38.61#ibcon#about to read 3, iclass 18, count 0 2006.239.07:49:38.63#ibcon#read 3, iclass 18, count 0 2006.239.07:49:38.63#ibcon#about to read 4, iclass 18, count 0 2006.239.07:49:38.63#ibcon#read 4, iclass 18, count 0 2006.239.07:49:38.63#ibcon#about to read 5, iclass 18, count 0 2006.239.07:49:38.63#ibcon#read 5, iclass 18, count 0 2006.239.07:49:38.63#ibcon#about to read 6, iclass 18, count 0 2006.239.07:49:38.63#ibcon#read 6, iclass 18, count 0 2006.239.07:49:38.63#ibcon#end of sib2, iclass 18, count 0 2006.239.07:49:38.63#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:49:38.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:49:38.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:49:38.63#ibcon#*before write, iclass 18, count 0 2006.239.07:49:38.63#ibcon#enter sib2, iclass 18, count 0 2006.239.07:49:38.63#ibcon#flushed, iclass 18, count 0 2006.239.07:49:38.63#ibcon#about to write, iclass 18, count 0 2006.239.07:49:38.63#ibcon#wrote, iclass 18, count 0 2006.239.07:49:38.63#ibcon#about to read 3, iclass 18, count 0 2006.239.07:49:38.67#ibcon#read 3, iclass 18, count 0 2006.239.07:49:38.67#ibcon#about to read 4, iclass 18, count 0 2006.239.07:49:38.67#ibcon#read 4, iclass 18, count 0 2006.239.07:49:38.67#ibcon#about to read 5, iclass 18, count 0 2006.239.07:49:38.67#ibcon#read 5, iclass 18, count 0 2006.239.07:49:38.67#ibcon#about to read 6, iclass 18, count 0 2006.239.07:49:38.67#ibcon#read 6, iclass 18, count 0 2006.239.07:49:38.67#ibcon#end of sib2, iclass 18, count 0 2006.239.07:49:38.67#ibcon#*after write, iclass 18, count 0 2006.239.07:49:38.67#ibcon#*before return 0, iclass 18, count 0 2006.239.07:49:38.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:38.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:38.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:49:38.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:49:38.67$vc4f8/va=3,7 2006.239.07:49:38.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.07:49:38.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.07:49:38.67#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:38.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:38.73#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:38.73#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:38.73#ibcon#enter wrdev, iclass 20, count 2 2006.239.07:49:38.73#ibcon#first serial, iclass 20, count 2 2006.239.07:49:38.73#ibcon#enter sib2, iclass 20, count 2 2006.239.07:49:38.73#ibcon#flushed, iclass 20, count 2 2006.239.07:49:38.73#ibcon#about to write, iclass 20, count 2 2006.239.07:49:38.73#ibcon#wrote, iclass 20, count 2 2006.239.07:49:38.73#ibcon#about to read 3, iclass 20, count 2 2006.239.07:49:38.75#ibcon#read 3, iclass 20, count 2 2006.239.07:49:38.75#ibcon#about to read 4, iclass 20, count 2 2006.239.07:49:38.75#ibcon#read 4, iclass 20, count 2 2006.239.07:49:38.75#ibcon#about to read 5, iclass 20, count 2 2006.239.07:49:38.75#ibcon#read 5, iclass 20, count 2 2006.239.07:49:38.75#ibcon#about to read 6, iclass 20, count 2 2006.239.07:49:38.75#ibcon#read 6, iclass 20, count 2 2006.239.07:49:38.75#ibcon#end of sib2, iclass 20, count 2 2006.239.07:49:38.75#ibcon#*mode == 0, iclass 20, count 2 2006.239.07:49:38.75#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.07:49:38.75#ibcon#[25=AT03-07\r\n] 2006.239.07:49:38.75#ibcon#*before write, iclass 20, count 2 2006.239.07:49:38.75#ibcon#enter sib2, iclass 20, count 2 2006.239.07:49:38.75#ibcon#flushed, iclass 20, count 2 2006.239.07:49:38.75#ibcon#about to write, iclass 20, count 2 2006.239.07:49:38.75#ibcon#wrote, iclass 20, count 2 2006.239.07:49:38.75#ibcon#about to read 3, iclass 20, count 2 2006.239.07:49:38.79#ibcon#read 3, iclass 20, count 2 2006.239.07:49:38.79#ibcon#about to read 4, iclass 20, count 2 2006.239.07:49:38.79#ibcon#read 4, iclass 20, count 2 2006.239.07:49:38.79#ibcon#about to read 5, iclass 20, count 2 2006.239.07:49:38.79#ibcon#read 5, iclass 20, count 2 2006.239.07:49:38.79#ibcon#about to read 6, iclass 20, count 2 2006.239.07:49:38.79#ibcon#read 6, iclass 20, count 2 2006.239.07:49:38.79#ibcon#end of sib2, iclass 20, count 2 2006.239.07:49:38.79#ibcon#*after write, iclass 20, count 2 2006.239.07:49:38.79#ibcon#*before return 0, iclass 20, count 2 2006.239.07:49:38.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:38.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:38.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.07:49:38.79#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:38.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:38.90#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:38.90#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:38.90#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:49:38.90#ibcon#first serial, iclass 20, count 0 2006.239.07:49:38.90#ibcon#enter sib2, iclass 20, count 0 2006.239.07:49:38.90#ibcon#flushed, iclass 20, count 0 2006.239.07:49:38.90#ibcon#about to write, iclass 20, count 0 2006.239.07:49:38.90#ibcon#wrote, iclass 20, count 0 2006.239.07:49:38.90#ibcon#about to read 3, iclass 20, count 0 2006.239.07:49:38.92#ibcon#read 3, iclass 20, count 0 2006.239.07:49:38.92#ibcon#about to read 4, iclass 20, count 0 2006.239.07:49:38.92#ibcon#read 4, iclass 20, count 0 2006.239.07:49:38.92#ibcon#about to read 5, iclass 20, count 0 2006.239.07:49:38.92#ibcon#read 5, iclass 20, count 0 2006.239.07:49:38.92#ibcon#about to read 6, iclass 20, count 0 2006.239.07:49:38.92#ibcon#read 6, iclass 20, count 0 2006.239.07:49:38.92#ibcon#end of sib2, iclass 20, count 0 2006.239.07:49:38.92#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:49:38.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:49:38.92#ibcon#[25=USB\r\n] 2006.239.07:49:38.92#ibcon#*before write, iclass 20, count 0 2006.239.07:49:38.92#ibcon#enter sib2, iclass 20, count 0 2006.239.07:49:38.92#ibcon#flushed, iclass 20, count 0 2006.239.07:49:38.92#ibcon#about to write, iclass 20, count 0 2006.239.07:49:38.92#ibcon#wrote, iclass 20, count 0 2006.239.07:49:38.92#ibcon#about to read 3, iclass 20, count 0 2006.239.07:49:38.95#ibcon#read 3, iclass 20, count 0 2006.239.07:49:38.95#ibcon#about to read 4, iclass 20, count 0 2006.239.07:49:38.95#ibcon#read 4, iclass 20, count 0 2006.239.07:49:38.95#ibcon#about to read 5, iclass 20, count 0 2006.239.07:49:38.95#ibcon#read 5, iclass 20, count 0 2006.239.07:49:38.95#ibcon#about to read 6, iclass 20, count 0 2006.239.07:49:38.95#ibcon#read 6, iclass 20, count 0 2006.239.07:49:38.95#ibcon#end of sib2, iclass 20, count 0 2006.239.07:49:38.95#ibcon#*after write, iclass 20, count 0 2006.239.07:49:38.95#ibcon#*before return 0, iclass 20, count 0 2006.239.07:49:38.95#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:38.95#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:38.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:49:38.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:49:38.95$vc4f8/valo=4,832.99 2006.239.07:49:38.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.07:49:38.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.07:49:38.95#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:38.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:38.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:38.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:38.95#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:49:38.95#ibcon#first serial, iclass 22, count 0 2006.239.07:49:38.95#ibcon#enter sib2, iclass 22, count 0 2006.239.07:49:38.95#ibcon#flushed, iclass 22, count 0 2006.239.07:49:38.95#ibcon#about to write, iclass 22, count 0 2006.239.07:49:38.95#ibcon#wrote, iclass 22, count 0 2006.239.07:49:38.95#ibcon#about to read 3, iclass 22, count 0 2006.239.07:49:38.97#ibcon#read 3, iclass 22, count 0 2006.239.07:49:38.97#ibcon#about to read 4, iclass 22, count 0 2006.239.07:49:38.97#ibcon#read 4, iclass 22, count 0 2006.239.07:49:38.97#ibcon#about to read 5, iclass 22, count 0 2006.239.07:49:38.97#ibcon#read 5, iclass 22, count 0 2006.239.07:49:38.97#ibcon#about to read 6, iclass 22, count 0 2006.239.07:49:38.97#ibcon#read 6, iclass 22, count 0 2006.239.07:49:38.97#ibcon#end of sib2, iclass 22, count 0 2006.239.07:49:38.97#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:49:38.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:49:38.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:49:38.97#ibcon#*before write, iclass 22, count 0 2006.239.07:49:38.97#ibcon#enter sib2, iclass 22, count 0 2006.239.07:49:38.97#ibcon#flushed, iclass 22, count 0 2006.239.07:49:38.97#ibcon#about to write, iclass 22, count 0 2006.239.07:49:38.97#ibcon#wrote, iclass 22, count 0 2006.239.07:49:38.97#ibcon#about to read 3, iclass 22, count 0 2006.239.07:49:39.01#ibcon#read 3, iclass 22, count 0 2006.239.07:49:39.01#ibcon#about to read 4, iclass 22, count 0 2006.239.07:49:39.01#ibcon#read 4, iclass 22, count 0 2006.239.07:49:39.01#ibcon#about to read 5, iclass 22, count 0 2006.239.07:49:39.01#ibcon#read 5, iclass 22, count 0 2006.239.07:49:39.01#ibcon#about to read 6, iclass 22, count 0 2006.239.07:49:39.01#ibcon#read 6, iclass 22, count 0 2006.239.07:49:39.01#ibcon#end of sib2, iclass 22, count 0 2006.239.07:49:39.01#ibcon#*after write, iclass 22, count 0 2006.239.07:49:39.01#ibcon#*before return 0, iclass 22, count 0 2006.239.07:49:39.01#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:39.01#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:39.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:49:39.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:49:39.01$vc4f8/va=4,7 2006.239.07:49:39.01#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.07:49:39.01#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.07:49:39.01#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:39.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:39.07#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:39.07#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:39.07#ibcon#enter wrdev, iclass 24, count 2 2006.239.07:49:39.07#ibcon#first serial, iclass 24, count 2 2006.239.07:49:39.07#ibcon#enter sib2, iclass 24, count 2 2006.239.07:49:39.07#ibcon#flushed, iclass 24, count 2 2006.239.07:49:39.07#ibcon#about to write, iclass 24, count 2 2006.239.07:49:39.07#ibcon#wrote, iclass 24, count 2 2006.239.07:49:39.07#ibcon#about to read 3, iclass 24, count 2 2006.239.07:49:39.09#ibcon#read 3, iclass 24, count 2 2006.239.07:49:39.09#ibcon#about to read 4, iclass 24, count 2 2006.239.07:49:39.09#ibcon#read 4, iclass 24, count 2 2006.239.07:49:39.09#ibcon#about to read 5, iclass 24, count 2 2006.239.07:49:39.09#ibcon#read 5, iclass 24, count 2 2006.239.07:49:39.09#ibcon#about to read 6, iclass 24, count 2 2006.239.07:49:39.09#ibcon#read 6, iclass 24, count 2 2006.239.07:49:39.09#ibcon#end of sib2, iclass 24, count 2 2006.239.07:49:39.09#ibcon#*mode == 0, iclass 24, count 2 2006.239.07:49:39.09#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.07:49:39.09#ibcon#[25=AT04-07\r\n] 2006.239.07:49:39.09#ibcon#*before write, iclass 24, count 2 2006.239.07:49:39.09#ibcon#enter sib2, iclass 24, count 2 2006.239.07:49:39.09#ibcon#flushed, iclass 24, count 2 2006.239.07:49:39.09#ibcon#about to write, iclass 24, count 2 2006.239.07:49:39.09#ibcon#wrote, iclass 24, count 2 2006.239.07:49:39.09#ibcon#about to read 3, iclass 24, count 2 2006.239.07:49:39.12#ibcon#read 3, iclass 24, count 2 2006.239.07:49:39.12#ibcon#about to read 4, iclass 24, count 2 2006.239.07:49:39.12#ibcon#read 4, iclass 24, count 2 2006.239.07:49:39.12#ibcon#about to read 5, iclass 24, count 2 2006.239.07:49:39.12#ibcon#read 5, iclass 24, count 2 2006.239.07:49:39.12#ibcon#about to read 6, iclass 24, count 2 2006.239.07:49:39.12#ibcon#read 6, iclass 24, count 2 2006.239.07:49:39.12#ibcon#end of sib2, iclass 24, count 2 2006.239.07:49:39.12#ibcon#*after write, iclass 24, count 2 2006.239.07:49:39.12#ibcon#*before return 0, iclass 24, count 2 2006.239.07:49:39.12#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:39.12#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:39.12#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.07:49:39.12#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:39.12#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:39.24#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:39.24#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:39.24#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:49:39.24#ibcon#first serial, iclass 24, count 0 2006.239.07:49:39.24#ibcon#enter sib2, iclass 24, count 0 2006.239.07:49:39.24#ibcon#flushed, iclass 24, count 0 2006.239.07:49:39.24#ibcon#about to write, iclass 24, count 0 2006.239.07:49:39.24#ibcon#wrote, iclass 24, count 0 2006.239.07:49:39.24#ibcon#about to read 3, iclass 24, count 0 2006.239.07:49:39.26#ibcon#read 3, iclass 24, count 0 2006.239.07:49:39.26#ibcon#about to read 4, iclass 24, count 0 2006.239.07:49:39.26#ibcon#read 4, iclass 24, count 0 2006.239.07:49:39.26#ibcon#about to read 5, iclass 24, count 0 2006.239.07:49:39.26#ibcon#read 5, iclass 24, count 0 2006.239.07:49:39.26#ibcon#about to read 6, iclass 24, count 0 2006.239.07:49:39.26#ibcon#read 6, iclass 24, count 0 2006.239.07:49:39.26#ibcon#end of sib2, iclass 24, count 0 2006.239.07:49:39.26#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:49:39.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:49:39.26#ibcon#[25=USB\r\n] 2006.239.07:49:39.26#ibcon#*before write, iclass 24, count 0 2006.239.07:49:39.26#ibcon#enter sib2, iclass 24, count 0 2006.239.07:49:39.26#ibcon#flushed, iclass 24, count 0 2006.239.07:49:39.26#ibcon#about to write, iclass 24, count 0 2006.239.07:49:39.26#ibcon#wrote, iclass 24, count 0 2006.239.07:49:39.26#ibcon#about to read 3, iclass 24, count 0 2006.239.07:49:39.29#ibcon#read 3, iclass 24, count 0 2006.239.07:49:39.29#ibcon#about to read 4, iclass 24, count 0 2006.239.07:49:39.29#ibcon#read 4, iclass 24, count 0 2006.239.07:49:39.29#ibcon#about to read 5, iclass 24, count 0 2006.239.07:49:39.29#ibcon#read 5, iclass 24, count 0 2006.239.07:49:39.29#ibcon#about to read 6, iclass 24, count 0 2006.239.07:49:39.29#ibcon#read 6, iclass 24, count 0 2006.239.07:49:39.29#ibcon#end of sib2, iclass 24, count 0 2006.239.07:49:39.29#ibcon#*after write, iclass 24, count 0 2006.239.07:49:39.29#ibcon#*before return 0, iclass 24, count 0 2006.239.07:49:39.29#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:39.29#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:39.29#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:49:39.29#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:49:39.29$vc4f8/valo=5,652.99 2006.239.07:49:39.29#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:49:39.29#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:49:39.29#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:39.29#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:39.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:39.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:39.29#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:49:39.29#ibcon#first serial, iclass 26, count 0 2006.239.07:49:39.29#ibcon#enter sib2, iclass 26, count 0 2006.239.07:49:39.29#ibcon#flushed, iclass 26, count 0 2006.239.07:49:39.29#ibcon#about to write, iclass 26, count 0 2006.239.07:49:39.29#ibcon#wrote, iclass 26, count 0 2006.239.07:49:39.29#ibcon#about to read 3, iclass 26, count 0 2006.239.07:49:39.31#ibcon#read 3, iclass 26, count 0 2006.239.07:49:39.31#ibcon#about to read 4, iclass 26, count 0 2006.239.07:49:39.31#ibcon#read 4, iclass 26, count 0 2006.239.07:49:39.31#ibcon#about to read 5, iclass 26, count 0 2006.239.07:49:39.31#ibcon#read 5, iclass 26, count 0 2006.239.07:49:39.31#ibcon#about to read 6, iclass 26, count 0 2006.239.07:49:39.31#ibcon#read 6, iclass 26, count 0 2006.239.07:49:39.31#ibcon#end of sib2, iclass 26, count 0 2006.239.07:49:39.31#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:49:39.31#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:49:39.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:49:39.31#ibcon#*before write, iclass 26, count 0 2006.239.07:49:39.31#ibcon#enter sib2, iclass 26, count 0 2006.239.07:49:39.31#ibcon#flushed, iclass 26, count 0 2006.239.07:49:39.31#ibcon#about to write, iclass 26, count 0 2006.239.07:49:39.31#ibcon#wrote, iclass 26, count 0 2006.239.07:49:39.31#ibcon#about to read 3, iclass 26, count 0 2006.239.07:49:39.35#ibcon#read 3, iclass 26, count 0 2006.239.07:49:39.35#ibcon#about to read 4, iclass 26, count 0 2006.239.07:49:39.35#ibcon#read 4, iclass 26, count 0 2006.239.07:49:39.35#ibcon#about to read 5, iclass 26, count 0 2006.239.07:49:39.35#ibcon#read 5, iclass 26, count 0 2006.239.07:49:39.35#ibcon#about to read 6, iclass 26, count 0 2006.239.07:49:39.35#ibcon#read 6, iclass 26, count 0 2006.239.07:49:39.35#ibcon#end of sib2, iclass 26, count 0 2006.239.07:49:39.35#ibcon#*after write, iclass 26, count 0 2006.239.07:49:39.35#ibcon#*before return 0, iclass 26, count 0 2006.239.07:49:39.35#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:39.35#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:39.35#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:49:39.35#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:49:39.35$vc4f8/va=5,8 2006.239.07:49:39.35#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:49:39.35#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:49:39.35#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:39.35#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:39.41#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:39.41#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:39.41#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:49:39.41#ibcon#first serial, iclass 28, count 2 2006.239.07:49:39.41#ibcon#enter sib2, iclass 28, count 2 2006.239.07:49:39.41#ibcon#flushed, iclass 28, count 2 2006.239.07:49:39.41#ibcon#about to write, iclass 28, count 2 2006.239.07:49:39.41#ibcon#wrote, iclass 28, count 2 2006.239.07:49:39.41#ibcon#about to read 3, iclass 28, count 2 2006.239.07:49:39.43#ibcon#read 3, iclass 28, count 2 2006.239.07:49:39.43#ibcon#about to read 4, iclass 28, count 2 2006.239.07:49:39.43#ibcon#read 4, iclass 28, count 2 2006.239.07:49:39.43#ibcon#about to read 5, iclass 28, count 2 2006.239.07:49:39.43#ibcon#read 5, iclass 28, count 2 2006.239.07:49:39.43#ibcon#about to read 6, iclass 28, count 2 2006.239.07:49:39.43#ibcon#read 6, iclass 28, count 2 2006.239.07:49:39.43#ibcon#end of sib2, iclass 28, count 2 2006.239.07:49:39.43#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:49:39.43#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:49:39.43#ibcon#[25=AT05-08\r\n] 2006.239.07:49:39.43#ibcon#*before write, iclass 28, count 2 2006.239.07:49:39.43#ibcon#enter sib2, iclass 28, count 2 2006.239.07:49:39.43#ibcon#flushed, iclass 28, count 2 2006.239.07:49:39.43#ibcon#about to write, iclass 28, count 2 2006.239.07:49:39.43#ibcon#wrote, iclass 28, count 2 2006.239.07:49:39.43#ibcon#about to read 3, iclass 28, count 2 2006.239.07:49:39.46#ibcon#read 3, iclass 28, count 2 2006.239.07:49:39.46#ibcon#about to read 4, iclass 28, count 2 2006.239.07:49:39.46#ibcon#read 4, iclass 28, count 2 2006.239.07:49:39.46#ibcon#about to read 5, iclass 28, count 2 2006.239.07:49:39.46#ibcon#read 5, iclass 28, count 2 2006.239.07:49:39.46#ibcon#about to read 6, iclass 28, count 2 2006.239.07:49:39.46#ibcon#read 6, iclass 28, count 2 2006.239.07:49:39.46#ibcon#end of sib2, iclass 28, count 2 2006.239.07:49:39.46#ibcon#*after write, iclass 28, count 2 2006.239.07:49:39.46#ibcon#*before return 0, iclass 28, count 2 2006.239.07:49:39.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:39.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:39.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:49:39.46#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:39.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:39.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:39.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:39.58#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:49:39.58#ibcon#first serial, iclass 28, count 0 2006.239.07:49:39.58#ibcon#enter sib2, iclass 28, count 0 2006.239.07:49:39.58#ibcon#flushed, iclass 28, count 0 2006.239.07:49:39.58#ibcon#about to write, iclass 28, count 0 2006.239.07:49:39.58#ibcon#wrote, iclass 28, count 0 2006.239.07:49:39.58#ibcon#about to read 3, iclass 28, count 0 2006.239.07:49:39.60#ibcon#read 3, iclass 28, count 0 2006.239.07:49:39.60#ibcon#about to read 4, iclass 28, count 0 2006.239.07:49:39.60#ibcon#read 4, iclass 28, count 0 2006.239.07:49:39.60#ibcon#about to read 5, iclass 28, count 0 2006.239.07:49:39.60#ibcon#read 5, iclass 28, count 0 2006.239.07:49:39.60#ibcon#about to read 6, iclass 28, count 0 2006.239.07:49:39.60#ibcon#read 6, iclass 28, count 0 2006.239.07:49:39.60#ibcon#end of sib2, iclass 28, count 0 2006.239.07:49:39.60#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:49:39.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:49:39.60#ibcon#[25=USB\r\n] 2006.239.07:49:39.60#ibcon#*before write, iclass 28, count 0 2006.239.07:49:39.60#ibcon#enter sib2, iclass 28, count 0 2006.239.07:49:39.60#ibcon#flushed, iclass 28, count 0 2006.239.07:49:39.60#ibcon#about to write, iclass 28, count 0 2006.239.07:49:39.60#ibcon#wrote, iclass 28, count 0 2006.239.07:49:39.60#ibcon#about to read 3, iclass 28, count 0 2006.239.07:49:39.63#ibcon#read 3, iclass 28, count 0 2006.239.07:49:39.63#ibcon#about to read 4, iclass 28, count 0 2006.239.07:49:39.63#ibcon#read 4, iclass 28, count 0 2006.239.07:49:39.63#ibcon#about to read 5, iclass 28, count 0 2006.239.07:49:39.63#ibcon#read 5, iclass 28, count 0 2006.239.07:49:39.63#ibcon#about to read 6, iclass 28, count 0 2006.239.07:49:39.63#ibcon#read 6, iclass 28, count 0 2006.239.07:49:39.63#ibcon#end of sib2, iclass 28, count 0 2006.239.07:49:39.63#ibcon#*after write, iclass 28, count 0 2006.239.07:49:39.63#ibcon#*before return 0, iclass 28, count 0 2006.239.07:49:39.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:39.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:39.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:49:39.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:49:39.63$vc4f8/valo=6,772.99 2006.239.07:49:39.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:49:39.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:49:39.63#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:39.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:39.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:39.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:39.63#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:49:39.63#ibcon#first serial, iclass 30, count 0 2006.239.07:49:39.63#ibcon#enter sib2, iclass 30, count 0 2006.239.07:49:39.63#ibcon#flushed, iclass 30, count 0 2006.239.07:49:39.63#ibcon#about to write, iclass 30, count 0 2006.239.07:49:39.63#ibcon#wrote, iclass 30, count 0 2006.239.07:49:39.63#ibcon#about to read 3, iclass 30, count 0 2006.239.07:49:39.65#ibcon#read 3, iclass 30, count 0 2006.239.07:49:39.65#ibcon#about to read 4, iclass 30, count 0 2006.239.07:49:39.65#ibcon#read 4, iclass 30, count 0 2006.239.07:49:39.65#ibcon#about to read 5, iclass 30, count 0 2006.239.07:49:39.65#ibcon#read 5, iclass 30, count 0 2006.239.07:49:39.65#ibcon#about to read 6, iclass 30, count 0 2006.239.07:49:39.65#ibcon#read 6, iclass 30, count 0 2006.239.07:49:39.65#ibcon#end of sib2, iclass 30, count 0 2006.239.07:49:39.65#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:49:39.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:49:39.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:49:39.65#ibcon#*before write, iclass 30, count 0 2006.239.07:49:39.65#ibcon#enter sib2, iclass 30, count 0 2006.239.07:49:39.65#ibcon#flushed, iclass 30, count 0 2006.239.07:49:39.65#ibcon#about to write, iclass 30, count 0 2006.239.07:49:39.65#ibcon#wrote, iclass 30, count 0 2006.239.07:49:39.65#ibcon#about to read 3, iclass 30, count 0 2006.239.07:49:39.69#ibcon#read 3, iclass 30, count 0 2006.239.07:49:39.69#ibcon#about to read 4, iclass 30, count 0 2006.239.07:49:39.69#ibcon#read 4, iclass 30, count 0 2006.239.07:49:39.69#ibcon#about to read 5, iclass 30, count 0 2006.239.07:49:39.69#ibcon#read 5, iclass 30, count 0 2006.239.07:49:39.69#ibcon#about to read 6, iclass 30, count 0 2006.239.07:49:39.69#ibcon#read 6, iclass 30, count 0 2006.239.07:49:39.69#ibcon#end of sib2, iclass 30, count 0 2006.239.07:49:39.69#ibcon#*after write, iclass 30, count 0 2006.239.07:49:39.69#ibcon#*before return 0, iclass 30, count 0 2006.239.07:49:39.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:39.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:39.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:49:39.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:49:39.69$vc4f8/va=6,7 2006.239.07:49:39.69#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:49:39.69#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:49:39.69#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:39.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:49:39.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:49:39.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:49:39.75#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:49:39.75#ibcon#first serial, iclass 32, count 2 2006.239.07:49:39.75#ibcon#enter sib2, iclass 32, count 2 2006.239.07:49:39.75#ibcon#flushed, iclass 32, count 2 2006.239.07:49:39.75#ibcon#about to write, iclass 32, count 2 2006.239.07:49:39.75#ibcon#wrote, iclass 32, count 2 2006.239.07:49:39.75#ibcon#about to read 3, iclass 32, count 2 2006.239.07:49:39.77#ibcon#read 3, iclass 32, count 2 2006.239.07:49:39.77#ibcon#about to read 4, iclass 32, count 2 2006.239.07:49:39.77#ibcon#read 4, iclass 32, count 2 2006.239.07:49:39.77#ibcon#about to read 5, iclass 32, count 2 2006.239.07:49:39.77#ibcon#read 5, iclass 32, count 2 2006.239.07:49:39.77#ibcon#about to read 6, iclass 32, count 2 2006.239.07:49:39.77#ibcon#read 6, iclass 32, count 2 2006.239.07:49:39.77#ibcon#end of sib2, iclass 32, count 2 2006.239.07:49:39.77#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:49:39.77#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:49:39.77#ibcon#[25=AT06-07\r\n] 2006.239.07:49:39.77#ibcon#*before write, iclass 32, count 2 2006.239.07:49:39.77#ibcon#enter sib2, iclass 32, count 2 2006.239.07:49:39.77#ibcon#flushed, iclass 32, count 2 2006.239.07:49:39.77#ibcon#about to write, iclass 32, count 2 2006.239.07:49:39.77#ibcon#wrote, iclass 32, count 2 2006.239.07:49:39.77#ibcon#about to read 3, iclass 32, count 2 2006.239.07:49:39.80#ibcon#read 3, iclass 32, count 2 2006.239.07:49:39.80#ibcon#about to read 4, iclass 32, count 2 2006.239.07:49:39.80#ibcon#read 4, iclass 32, count 2 2006.239.07:49:39.80#ibcon#about to read 5, iclass 32, count 2 2006.239.07:49:39.80#ibcon#read 5, iclass 32, count 2 2006.239.07:49:39.80#ibcon#about to read 6, iclass 32, count 2 2006.239.07:49:39.80#ibcon#read 6, iclass 32, count 2 2006.239.07:49:39.80#ibcon#end of sib2, iclass 32, count 2 2006.239.07:49:39.80#ibcon#*after write, iclass 32, count 2 2006.239.07:49:39.80#ibcon#*before return 0, iclass 32, count 2 2006.239.07:49:39.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:49:39.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:49:39.80#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:49:39.80#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:39.80#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:49:39.92#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:49:39.92#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:49:39.92#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:49:39.92#ibcon#first serial, iclass 32, count 0 2006.239.07:49:39.92#ibcon#enter sib2, iclass 32, count 0 2006.239.07:49:39.92#ibcon#flushed, iclass 32, count 0 2006.239.07:49:39.92#ibcon#about to write, iclass 32, count 0 2006.239.07:49:39.92#ibcon#wrote, iclass 32, count 0 2006.239.07:49:39.92#ibcon#about to read 3, iclass 32, count 0 2006.239.07:49:39.94#ibcon#read 3, iclass 32, count 0 2006.239.07:49:39.94#ibcon#about to read 4, iclass 32, count 0 2006.239.07:49:39.94#ibcon#read 4, iclass 32, count 0 2006.239.07:49:39.94#ibcon#about to read 5, iclass 32, count 0 2006.239.07:49:39.94#ibcon#read 5, iclass 32, count 0 2006.239.07:49:39.94#ibcon#about to read 6, iclass 32, count 0 2006.239.07:49:39.94#ibcon#read 6, iclass 32, count 0 2006.239.07:49:39.94#ibcon#end of sib2, iclass 32, count 0 2006.239.07:49:39.94#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:49:39.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:49:39.94#ibcon#[25=USB\r\n] 2006.239.07:49:39.94#ibcon#*before write, iclass 32, count 0 2006.239.07:49:39.94#ibcon#enter sib2, iclass 32, count 0 2006.239.07:49:39.94#ibcon#flushed, iclass 32, count 0 2006.239.07:49:39.94#ibcon#about to write, iclass 32, count 0 2006.239.07:49:39.94#ibcon#wrote, iclass 32, count 0 2006.239.07:49:39.94#ibcon#about to read 3, iclass 32, count 0 2006.239.07:49:39.97#ibcon#read 3, iclass 32, count 0 2006.239.07:49:39.97#ibcon#about to read 4, iclass 32, count 0 2006.239.07:49:39.97#ibcon#read 4, iclass 32, count 0 2006.239.07:49:39.97#ibcon#about to read 5, iclass 32, count 0 2006.239.07:49:39.97#ibcon#read 5, iclass 32, count 0 2006.239.07:49:39.97#ibcon#about to read 6, iclass 32, count 0 2006.239.07:49:39.97#ibcon#read 6, iclass 32, count 0 2006.239.07:49:39.97#ibcon#end of sib2, iclass 32, count 0 2006.239.07:49:39.97#ibcon#*after write, iclass 32, count 0 2006.239.07:49:39.97#ibcon#*before return 0, iclass 32, count 0 2006.239.07:49:39.97#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:49:39.97#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:49:39.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:49:39.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:49:39.97$vc4f8/valo=7,832.99 2006.239.07:49:39.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:49:39.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:49:39.97#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:39.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:49:39.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:49:39.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:49:39.97#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:49:39.97#ibcon#first serial, iclass 34, count 0 2006.239.07:49:39.97#ibcon#enter sib2, iclass 34, count 0 2006.239.07:49:39.97#ibcon#flushed, iclass 34, count 0 2006.239.07:49:39.97#ibcon#about to write, iclass 34, count 0 2006.239.07:49:39.97#ibcon#wrote, iclass 34, count 0 2006.239.07:49:39.97#ibcon#about to read 3, iclass 34, count 0 2006.239.07:49:39.99#ibcon#read 3, iclass 34, count 0 2006.239.07:49:39.99#ibcon#about to read 4, iclass 34, count 0 2006.239.07:49:39.99#ibcon#read 4, iclass 34, count 0 2006.239.07:49:39.99#ibcon#about to read 5, iclass 34, count 0 2006.239.07:49:39.99#ibcon#read 5, iclass 34, count 0 2006.239.07:49:39.99#ibcon#about to read 6, iclass 34, count 0 2006.239.07:49:39.99#ibcon#read 6, iclass 34, count 0 2006.239.07:49:39.99#ibcon#end of sib2, iclass 34, count 0 2006.239.07:49:39.99#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:49:39.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:49:39.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:49:39.99#ibcon#*before write, iclass 34, count 0 2006.239.07:49:39.99#ibcon#enter sib2, iclass 34, count 0 2006.239.07:49:39.99#ibcon#flushed, iclass 34, count 0 2006.239.07:49:39.99#ibcon#about to write, iclass 34, count 0 2006.239.07:49:39.99#ibcon#wrote, iclass 34, count 0 2006.239.07:49:39.99#ibcon#about to read 3, iclass 34, count 0 2006.239.07:49:40.03#ibcon#read 3, iclass 34, count 0 2006.239.07:49:40.03#ibcon#about to read 4, iclass 34, count 0 2006.239.07:49:40.03#ibcon#read 4, iclass 34, count 0 2006.239.07:49:40.03#ibcon#about to read 5, iclass 34, count 0 2006.239.07:49:40.03#ibcon#read 5, iclass 34, count 0 2006.239.07:49:40.03#ibcon#about to read 6, iclass 34, count 0 2006.239.07:49:40.03#ibcon#read 6, iclass 34, count 0 2006.239.07:49:40.03#ibcon#end of sib2, iclass 34, count 0 2006.239.07:49:40.03#ibcon#*after write, iclass 34, count 0 2006.239.07:49:40.03#ibcon#*before return 0, iclass 34, count 0 2006.239.07:49:40.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:49:40.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:49:40.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:49:40.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:49:40.04$vc4f8/va=7,7 2006.239.07:49:40.04#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:49:40.04#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:49:40.04#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:40.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:49:40.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:49:40.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:49:40.08#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:49:40.08#ibcon#first serial, iclass 36, count 2 2006.239.07:49:40.08#ibcon#enter sib2, iclass 36, count 2 2006.239.07:49:40.08#ibcon#flushed, iclass 36, count 2 2006.239.07:49:40.08#ibcon#about to write, iclass 36, count 2 2006.239.07:49:40.08#ibcon#wrote, iclass 36, count 2 2006.239.07:49:40.08#ibcon#about to read 3, iclass 36, count 2 2006.239.07:49:40.11#ibcon#read 3, iclass 36, count 2 2006.239.07:49:40.11#ibcon#about to read 4, iclass 36, count 2 2006.239.07:49:40.11#ibcon#read 4, iclass 36, count 2 2006.239.07:49:40.11#ibcon#about to read 5, iclass 36, count 2 2006.239.07:49:40.11#ibcon#read 5, iclass 36, count 2 2006.239.07:49:40.11#ibcon#about to read 6, iclass 36, count 2 2006.239.07:49:40.11#ibcon#read 6, iclass 36, count 2 2006.239.07:49:40.11#ibcon#end of sib2, iclass 36, count 2 2006.239.07:49:40.11#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:49:40.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:49:40.11#ibcon#[25=AT07-07\r\n] 2006.239.07:49:40.11#ibcon#*before write, iclass 36, count 2 2006.239.07:49:40.11#ibcon#enter sib2, iclass 36, count 2 2006.239.07:49:40.11#ibcon#flushed, iclass 36, count 2 2006.239.07:49:40.11#ibcon#about to write, iclass 36, count 2 2006.239.07:49:40.11#ibcon#wrote, iclass 36, count 2 2006.239.07:49:40.11#ibcon#about to read 3, iclass 36, count 2 2006.239.07:49:40.14#ibcon#read 3, iclass 36, count 2 2006.239.07:49:40.14#ibcon#about to read 4, iclass 36, count 2 2006.239.07:49:40.14#ibcon#read 4, iclass 36, count 2 2006.239.07:49:40.14#ibcon#about to read 5, iclass 36, count 2 2006.239.07:49:40.14#ibcon#read 5, iclass 36, count 2 2006.239.07:49:40.14#ibcon#about to read 6, iclass 36, count 2 2006.239.07:49:40.14#ibcon#read 6, iclass 36, count 2 2006.239.07:49:40.14#ibcon#end of sib2, iclass 36, count 2 2006.239.07:49:40.14#ibcon#*after write, iclass 36, count 2 2006.239.07:49:40.14#ibcon#*before return 0, iclass 36, count 2 2006.239.07:49:40.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:49:40.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:49:40.14#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:49:40.14#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:40.14#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:49:40.26#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:49:40.26#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:49:40.26#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:49:40.26#ibcon#first serial, iclass 36, count 0 2006.239.07:49:40.26#ibcon#enter sib2, iclass 36, count 0 2006.239.07:49:40.26#ibcon#flushed, iclass 36, count 0 2006.239.07:49:40.26#ibcon#about to write, iclass 36, count 0 2006.239.07:49:40.26#ibcon#wrote, iclass 36, count 0 2006.239.07:49:40.26#ibcon#about to read 3, iclass 36, count 0 2006.239.07:49:40.28#ibcon#read 3, iclass 36, count 0 2006.239.07:49:40.28#ibcon#about to read 4, iclass 36, count 0 2006.239.07:49:40.28#ibcon#read 4, iclass 36, count 0 2006.239.07:49:40.28#ibcon#about to read 5, iclass 36, count 0 2006.239.07:49:40.28#ibcon#read 5, iclass 36, count 0 2006.239.07:49:40.28#ibcon#about to read 6, iclass 36, count 0 2006.239.07:49:40.28#ibcon#read 6, iclass 36, count 0 2006.239.07:49:40.28#ibcon#end of sib2, iclass 36, count 0 2006.239.07:49:40.28#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:49:40.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:49:40.28#ibcon#[25=USB\r\n] 2006.239.07:49:40.28#ibcon#*before write, iclass 36, count 0 2006.239.07:49:40.28#ibcon#enter sib2, iclass 36, count 0 2006.239.07:49:40.28#ibcon#flushed, iclass 36, count 0 2006.239.07:49:40.28#ibcon#about to write, iclass 36, count 0 2006.239.07:49:40.28#ibcon#wrote, iclass 36, count 0 2006.239.07:49:40.28#ibcon#about to read 3, iclass 36, count 0 2006.239.07:49:40.31#ibcon#read 3, iclass 36, count 0 2006.239.07:49:40.31#ibcon#about to read 4, iclass 36, count 0 2006.239.07:49:40.31#ibcon#read 4, iclass 36, count 0 2006.239.07:49:40.31#ibcon#about to read 5, iclass 36, count 0 2006.239.07:49:40.31#ibcon#read 5, iclass 36, count 0 2006.239.07:49:40.31#ibcon#about to read 6, iclass 36, count 0 2006.239.07:49:40.31#ibcon#read 6, iclass 36, count 0 2006.239.07:49:40.31#ibcon#end of sib2, iclass 36, count 0 2006.239.07:49:40.31#ibcon#*after write, iclass 36, count 0 2006.239.07:49:40.31#ibcon#*before return 0, iclass 36, count 0 2006.239.07:49:40.31#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:49:40.31#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:49:40.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:49:40.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:49:40.31$vc4f8/valo=8,852.99 2006.239.07:49:40.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.07:49:40.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.07:49:40.31#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:40.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:49:40.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:49:40.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:49:40.31#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:49:40.31#ibcon#first serial, iclass 38, count 0 2006.239.07:49:40.31#ibcon#enter sib2, iclass 38, count 0 2006.239.07:49:40.31#ibcon#flushed, iclass 38, count 0 2006.239.07:49:40.31#ibcon#about to write, iclass 38, count 0 2006.239.07:49:40.31#ibcon#wrote, iclass 38, count 0 2006.239.07:49:40.31#ibcon#about to read 3, iclass 38, count 0 2006.239.07:49:40.33#ibcon#read 3, iclass 38, count 0 2006.239.07:49:40.33#ibcon#about to read 4, iclass 38, count 0 2006.239.07:49:40.33#ibcon#read 4, iclass 38, count 0 2006.239.07:49:40.33#ibcon#about to read 5, iclass 38, count 0 2006.239.07:49:40.33#ibcon#read 5, iclass 38, count 0 2006.239.07:49:40.33#ibcon#about to read 6, iclass 38, count 0 2006.239.07:49:40.33#ibcon#read 6, iclass 38, count 0 2006.239.07:49:40.33#ibcon#end of sib2, iclass 38, count 0 2006.239.07:49:40.33#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:49:40.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:49:40.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:49:40.33#ibcon#*before write, iclass 38, count 0 2006.239.07:49:40.33#ibcon#enter sib2, iclass 38, count 0 2006.239.07:49:40.33#ibcon#flushed, iclass 38, count 0 2006.239.07:49:40.33#ibcon#about to write, iclass 38, count 0 2006.239.07:49:40.33#ibcon#wrote, iclass 38, count 0 2006.239.07:49:40.33#ibcon#about to read 3, iclass 38, count 0 2006.239.07:49:40.37#ibcon#read 3, iclass 38, count 0 2006.239.07:49:40.37#ibcon#about to read 4, iclass 38, count 0 2006.239.07:49:40.37#ibcon#read 4, iclass 38, count 0 2006.239.07:49:40.37#ibcon#about to read 5, iclass 38, count 0 2006.239.07:49:40.37#ibcon#read 5, iclass 38, count 0 2006.239.07:49:40.37#ibcon#about to read 6, iclass 38, count 0 2006.239.07:49:40.37#ibcon#read 6, iclass 38, count 0 2006.239.07:49:40.37#ibcon#end of sib2, iclass 38, count 0 2006.239.07:49:40.37#ibcon#*after write, iclass 38, count 0 2006.239.07:49:40.37#ibcon#*before return 0, iclass 38, count 0 2006.239.07:49:40.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:49:40.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:49:40.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:49:40.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:49:40.37$vc4f8/va=8,7 2006.239.07:49:40.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.07:49:40.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.07:49:40.37#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:40.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:49:40.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:49:40.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:49:40.43#ibcon#enter wrdev, iclass 40, count 2 2006.239.07:49:40.43#ibcon#first serial, iclass 40, count 2 2006.239.07:49:40.43#ibcon#enter sib2, iclass 40, count 2 2006.239.07:49:40.43#ibcon#flushed, iclass 40, count 2 2006.239.07:49:40.43#ibcon#about to write, iclass 40, count 2 2006.239.07:49:40.43#ibcon#wrote, iclass 40, count 2 2006.239.07:49:40.43#ibcon#about to read 3, iclass 40, count 2 2006.239.07:49:40.45#ibcon#read 3, iclass 40, count 2 2006.239.07:49:40.45#ibcon#about to read 4, iclass 40, count 2 2006.239.07:49:40.45#ibcon#read 4, iclass 40, count 2 2006.239.07:49:40.45#ibcon#about to read 5, iclass 40, count 2 2006.239.07:49:40.45#ibcon#read 5, iclass 40, count 2 2006.239.07:49:40.45#ibcon#about to read 6, iclass 40, count 2 2006.239.07:49:40.45#ibcon#read 6, iclass 40, count 2 2006.239.07:49:40.45#ibcon#end of sib2, iclass 40, count 2 2006.239.07:49:40.45#ibcon#*mode == 0, iclass 40, count 2 2006.239.07:49:40.45#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.07:49:40.45#ibcon#[25=AT08-07\r\n] 2006.239.07:49:40.45#ibcon#*before write, iclass 40, count 2 2006.239.07:49:40.45#ibcon#enter sib2, iclass 40, count 2 2006.239.07:49:40.45#ibcon#flushed, iclass 40, count 2 2006.239.07:49:40.45#ibcon#about to write, iclass 40, count 2 2006.239.07:49:40.45#ibcon#wrote, iclass 40, count 2 2006.239.07:49:40.45#ibcon#about to read 3, iclass 40, count 2 2006.239.07:49:40.48#ibcon#read 3, iclass 40, count 2 2006.239.07:49:40.48#ibcon#about to read 4, iclass 40, count 2 2006.239.07:49:40.48#ibcon#read 4, iclass 40, count 2 2006.239.07:49:40.48#ibcon#about to read 5, iclass 40, count 2 2006.239.07:49:40.48#ibcon#read 5, iclass 40, count 2 2006.239.07:49:40.48#ibcon#about to read 6, iclass 40, count 2 2006.239.07:49:40.48#ibcon#read 6, iclass 40, count 2 2006.239.07:49:40.48#ibcon#end of sib2, iclass 40, count 2 2006.239.07:49:40.48#ibcon#*after write, iclass 40, count 2 2006.239.07:49:40.48#ibcon#*before return 0, iclass 40, count 2 2006.239.07:49:40.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:49:40.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:49:40.48#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.07:49:40.48#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:40.48#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:49:40.60#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:49:40.60#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:49:40.60#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:49:40.60#ibcon#first serial, iclass 40, count 0 2006.239.07:49:40.60#ibcon#enter sib2, iclass 40, count 0 2006.239.07:49:40.60#ibcon#flushed, iclass 40, count 0 2006.239.07:49:40.60#ibcon#about to write, iclass 40, count 0 2006.239.07:49:40.60#ibcon#wrote, iclass 40, count 0 2006.239.07:49:40.60#ibcon#about to read 3, iclass 40, count 0 2006.239.07:49:40.62#ibcon#read 3, iclass 40, count 0 2006.239.07:49:40.62#ibcon#about to read 4, iclass 40, count 0 2006.239.07:49:40.62#ibcon#read 4, iclass 40, count 0 2006.239.07:49:40.62#ibcon#about to read 5, iclass 40, count 0 2006.239.07:49:40.62#ibcon#read 5, iclass 40, count 0 2006.239.07:49:40.62#ibcon#about to read 6, iclass 40, count 0 2006.239.07:49:40.62#ibcon#read 6, iclass 40, count 0 2006.239.07:49:40.62#ibcon#end of sib2, iclass 40, count 0 2006.239.07:49:40.62#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:49:40.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:49:40.62#ibcon#[25=USB\r\n] 2006.239.07:49:40.62#ibcon#*before write, iclass 40, count 0 2006.239.07:49:40.62#ibcon#enter sib2, iclass 40, count 0 2006.239.07:49:40.62#ibcon#flushed, iclass 40, count 0 2006.239.07:49:40.62#ibcon#about to write, iclass 40, count 0 2006.239.07:49:40.62#ibcon#wrote, iclass 40, count 0 2006.239.07:49:40.62#ibcon#about to read 3, iclass 40, count 0 2006.239.07:49:40.65#ibcon#read 3, iclass 40, count 0 2006.239.07:49:40.65#ibcon#about to read 4, iclass 40, count 0 2006.239.07:49:40.65#ibcon#read 4, iclass 40, count 0 2006.239.07:49:40.65#ibcon#about to read 5, iclass 40, count 0 2006.239.07:49:40.65#ibcon#read 5, iclass 40, count 0 2006.239.07:49:40.65#ibcon#about to read 6, iclass 40, count 0 2006.239.07:49:40.65#ibcon#read 6, iclass 40, count 0 2006.239.07:49:40.65#ibcon#end of sib2, iclass 40, count 0 2006.239.07:49:40.65#ibcon#*after write, iclass 40, count 0 2006.239.07:49:40.65#ibcon#*before return 0, iclass 40, count 0 2006.239.07:49:40.65#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:49:40.65#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:49:40.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:49:40.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:49:40.65$vc4f8/vblo=1,632.99 2006.239.07:49:40.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:49:40.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:49:40.65#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:40.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:49:40.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:49:40.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:49:40.65#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:49:40.65#ibcon#first serial, iclass 4, count 0 2006.239.07:49:40.65#ibcon#enter sib2, iclass 4, count 0 2006.239.07:49:40.65#ibcon#flushed, iclass 4, count 0 2006.239.07:49:40.65#ibcon#about to write, iclass 4, count 0 2006.239.07:49:40.65#ibcon#wrote, iclass 4, count 0 2006.239.07:49:40.65#ibcon#about to read 3, iclass 4, count 0 2006.239.07:49:40.67#ibcon#read 3, iclass 4, count 0 2006.239.07:49:40.67#ibcon#about to read 4, iclass 4, count 0 2006.239.07:49:40.67#ibcon#read 4, iclass 4, count 0 2006.239.07:49:40.67#ibcon#about to read 5, iclass 4, count 0 2006.239.07:49:40.67#ibcon#read 5, iclass 4, count 0 2006.239.07:49:40.67#ibcon#about to read 6, iclass 4, count 0 2006.239.07:49:40.67#ibcon#read 6, iclass 4, count 0 2006.239.07:49:40.67#ibcon#end of sib2, iclass 4, count 0 2006.239.07:49:40.67#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:49:40.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:49:40.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:49:40.67#ibcon#*before write, iclass 4, count 0 2006.239.07:49:40.67#ibcon#enter sib2, iclass 4, count 0 2006.239.07:49:40.67#ibcon#flushed, iclass 4, count 0 2006.239.07:49:40.67#ibcon#about to write, iclass 4, count 0 2006.239.07:49:40.67#ibcon#wrote, iclass 4, count 0 2006.239.07:49:40.67#ibcon#about to read 3, iclass 4, count 0 2006.239.07:49:40.71#ibcon#read 3, iclass 4, count 0 2006.239.07:49:40.71#ibcon#about to read 4, iclass 4, count 0 2006.239.07:49:40.71#ibcon#read 4, iclass 4, count 0 2006.239.07:49:40.71#ibcon#about to read 5, iclass 4, count 0 2006.239.07:49:40.71#ibcon#read 5, iclass 4, count 0 2006.239.07:49:40.71#ibcon#about to read 6, iclass 4, count 0 2006.239.07:49:40.71#ibcon#read 6, iclass 4, count 0 2006.239.07:49:40.71#ibcon#end of sib2, iclass 4, count 0 2006.239.07:49:40.71#ibcon#*after write, iclass 4, count 0 2006.239.07:49:40.71#ibcon#*before return 0, iclass 4, count 0 2006.239.07:49:40.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:49:40.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:49:40.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:49:40.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:49:40.71$vc4f8/vb=1,4 2006.239.07:49:40.71#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:49:40.71#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:49:40.71#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:40.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:49:40.71#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:49:40.71#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:49:40.71#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:49:40.71#ibcon#first serial, iclass 6, count 2 2006.239.07:49:40.71#ibcon#enter sib2, iclass 6, count 2 2006.239.07:49:40.71#ibcon#flushed, iclass 6, count 2 2006.239.07:49:40.71#ibcon#about to write, iclass 6, count 2 2006.239.07:49:40.71#ibcon#wrote, iclass 6, count 2 2006.239.07:49:40.71#ibcon#about to read 3, iclass 6, count 2 2006.239.07:49:40.73#ibcon#read 3, iclass 6, count 2 2006.239.07:49:40.73#ibcon#about to read 4, iclass 6, count 2 2006.239.07:49:40.73#ibcon#read 4, iclass 6, count 2 2006.239.07:49:40.73#ibcon#about to read 5, iclass 6, count 2 2006.239.07:49:40.73#ibcon#read 5, iclass 6, count 2 2006.239.07:49:40.73#ibcon#about to read 6, iclass 6, count 2 2006.239.07:49:40.73#ibcon#read 6, iclass 6, count 2 2006.239.07:49:40.73#ibcon#end of sib2, iclass 6, count 2 2006.239.07:49:40.73#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:49:40.73#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:49:40.73#ibcon#[27=AT01-04\r\n] 2006.239.07:49:40.73#ibcon#*before write, iclass 6, count 2 2006.239.07:49:40.73#ibcon#enter sib2, iclass 6, count 2 2006.239.07:49:40.73#ibcon#flushed, iclass 6, count 2 2006.239.07:49:40.73#ibcon#about to write, iclass 6, count 2 2006.239.07:49:40.73#ibcon#wrote, iclass 6, count 2 2006.239.07:49:40.73#ibcon#about to read 3, iclass 6, count 2 2006.239.07:49:40.76#ibcon#read 3, iclass 6, count 2 2006.239.07:49:40.76#ibcon#about to read 4, iclass 6, count 2 2006.239.07:49:40.76#ibcon#read 4, iclass 6, count 2 2006.239.07:49:40.76#ibcon#about to read 5, iclass 6, count 2 2006.239.07:49:40.76#ibcon#read 5, iclass 6, count 2 2006.239.07:49:40.76#ibcon#about to read 6, iclass 6, count 2 2006.239.07:49:40.76#ibcon#read 6, iclass 6, count 2 2006.239.07:49:40.76#ibcon#end of sib2, iclass 6, count 2 2006.239.07:49:40.76#ibcon#*after write, iclass 6, count 2 2006.239.07:49:40.76#ibcon#*before return 0, iclass 6, count 2 2006.239.07:49:40.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:49:40.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:49:40.76#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:49:40.76#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:40.76#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:49:40.88#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:49:40.88#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:49:40.88#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:49:40.88#ibcon#first serial, iclass 6, count 0 2006.239.07:49:40.88#ibcon#enter sib2, iclass 6, count 0 2006.239.07:49:40.88#ibcon#flushed, iclass 6, count 0 2006.239.07:49:40.88#ibcon#about to write, iclass 6, count 0 2006.239.07:49:40.88#ibcon#wrote, iclass 6, count 0 2006.239.07:49:40.88#ibcon#about to read 3, iclass 6, count 0 2006.239.07:49:40.90#ibcon#read 3, iclass 6, count 0 2006.239.07:49:40.90#ibcon#about to read 4, iclass 6, count 0 2006.239.07:49:40.90#ibcon#read 4, iclass 6, count 0 2006.239.07:49:40.90#ibcon#about to read 5, iclass 6, count 0 2006.239.07:49:40.90#ibcon#read 5, iclass 6, count 0 2006.239.07:49:40.90#ibcon#about to read 6, iclass 6, count 0 2006.239.07:49:40.90#ibcon#read 6, iclass 6, count 0 2006.239.07:49:40.90#ibcon#end of sib2, iclass 6, count 0 2006.239.07:49:40.90#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:49:40.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:49:40.90#ibcon#[27=USB\r\n] 2006.239.07:49:40.90#ibcon#*before write, iclass 6, count 0 2006.239.07:49:40.90#ibcon#enter sib2, iclass 6, count 0 2006.239.07:49:40.90#ibcon#flushed, iclass 6, count 0 2006.239.07:49:40.90#ibcon#about to write, iclass 6, count 0 2006.239.07:49:40.90#ibcon#wrote, iclass 6, count 0 2006.239.07:49:40.90#ibcon#about to read 3, iclass 6, count 0 2006.239.07:49:40.93#ibcon#read 3, iclass 6, count 0 2006.239.07:49:40.93#ibcon#about to read 4, iclass 6, count 0 2006.239.07:49:40.93#ibcon#read 4, iclass 6, count 0 2006.239.07:49:40.93#ibcon#about to read 5, iclass 6, count 0 2006.239.07:49:40.93#ibcon#read 5, iclass 6, count 0 2006.239.07:49:40.93#ibcon#about to read 6, iclass 6, count 0 2006.239.07:49:40.93#ibcon#read 6, iclass 6, count 0 2006.239.07:49:40.93#ibcon#end of sib2, iclass 6, count 0 2006.239.07:49:40.93#ibcon#*after write, iclass 6, count 0 2006.239.07:49:40.93#ibcon#*before return 0, iclass 6, count 0 2006.239.07:49:40.93#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:49:40.93#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:49:40.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:49:40.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:49:40.93$vc4f8/vblo=2,640.99 2006.239.07:49:40.93#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:49:40.93#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:49:40.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:40.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:40.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:40.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:40.93#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:49:40.93#ibcon#first serial, iclass 10, count 0 2006.239.07:49:40.93#ibcon#enter sib2, iclass 10, count 0 2006.239.07:49:40.93#ibcon#flushed, iclass 10, count 0 2006.239.07:49:40.93#ibcon#about to write, iclass 10, count 0 2006.239.07:49:40.93#ibcon#wrote, iclass 10, count 0 2006.239.07:49:40.93#ibcon#about to read 3, iclass 10, count 0 2006.239.07:49:40.95#ibcon#read 3, iclass 10, count 0 2006.239.07:49:40.95#ibcon#about to read 4, iclass 10, count 0 2006.239.07:49:40.95#ibcon#read 4, iclass 10, count 0 2006.239.07:49:40.95#ibcon#about to read 5, iclass 10, count 0 2006.239.07:49:40.95#ibcon#read 5, iclass 10, count 0 2006.239.07:49:40.95#ibcon#about to read 6, iclass 10, count 0 2006.239.07:49:40.95#ibcon#read 6, iclass 10, count 0 2006.239.07:49:40.95#ibcon#end of sib2, iclass 10, count 0 2006.239.07:49:40.95#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:49:40.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:49:40.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:49:40.95#ibcon#*before write, iclass 10, count 0 2006.239.07:49:40.95#ibcon#enter sib2, iclass 10, count 0 2006.239.07:49:40.95#ibcon#flushed, iclass 10, count 0 2006.239.07:49:40.95#ibcon#about to write, iclass 10, count 0 2006.239.07:49:40.95#ibcon#wrote, iclass 10, count 0 2006.239.07:49:40.95#ibcon#about to read 3, iclass 10, count 0 2006.239.07:49:40.99#ibcon#read 3, iclass 10, count 0 2006.239.07:49:40.99#ibcon#about to read 4, iclass 10, count 0 2006.239.07:49:40.99#ibcon#read 4, iclass 10, count 0 2006.239.07:49:40.99#ibcon#about to read 5, iclass 10, count 0 2006.239.07:49:40.99#ibcon#read 5, iclass 10, count 0 2006.239.07:49:40.99#ibcon#about to read 6, iclass 10, count 0 2006.239.07:49:40.99#ibcon#read 6, iclass 10, count 0 2006.239.07:49:40.99#ibcon#end of sib2, iclass 10, count 0 2006.239.07:49:40.99#ibcon#*after write, iclass 10, count 0 2006.239.07:49:40.99#ibcon#*before return 0, iclass 10, count 0 2006.239.07:49:40.99#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:40.99#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:49:40.99#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:49:40.99#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:49:40.99$vc4f8/vb=2,4 2006.239.07:49:40.99#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.07:49:40.99#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.07:49:40.99#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:40.99#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:41.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:41.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:41.05#ibcon#enter wrdev, iclass 12, count 2 2006.239.07:49:41.05#ibcon#first serial, iclass 12, count 2 2006.239.07:49:41.05#ibcon#enter sib2, iclass 12, count 2 2006.239.07:49:41.05#ibcon#flushed, iclass 12, count 2 2006.239.07:49:41.05#ibcon#about to write, iclass 12, count 2 2006.239.07:49:41.05#ibcon#wrote, iclass 12, count 2 2006.239.07:49:41.05#ibcon#about to read 3, iclass 12, count 2 2006.239.07:49:41.07#ibcon#read 3, iclass 12, count 2 2006.239.07:49:41.07#ibcon#about to read 4, iclass 12, count 2 2006.239.07:49:41.07#ibcon#read 4, iclass 12, count 2 2006.239.07:49:41.07#ibcon#about to read 5, iclass 12, count 2 2006.239.07:49:41.07#ibcon#read 5, iclass 12, count 2 2006.239.07:49:41.07#ibcon#about to read 6, iclass 12, count 2 2006.239.07:49:41.07#ibcon#read 6, iclass 12, count 2 2006.239.07:49:41.07#ibcon#end of sib2, iclass 12, count 2 2006.239.07:49:41.07#ibcon#*mode == 0, iclass 12, count 2 2006.239.07:49:41.07#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.07:49:41.07#ibcon#[27=AT02-04\r\n] 2006.239.07:49:41.07#ibcon#*before write, iclass 12, count 2 2006.239.07:49:41.07#ibcon#enter sib2, iclass 12, count 2 2006.239.07:49:41.07#ibcon#flushed, iclass 12, count 2 2006.239.07:49:41.07#ibcon#about to write, iclass 12, count 2 2006.239.07:49:41.07#ibcon#wrote, iclass 12, count 2 2006.239.07:49:41.07#ibcon#about to read 3, iclass 12, count 2 2006.239.07:49:41.10#ibcon#read 3, iclass 12, count 2 2006.239.07:49:41.10#ibcon#about to read 4, iclass 12, count 2 2006.239.07:49:41.10#ibcon#read 4, iclass 12, count 2 2006.239.07:49:41.10#ibcon#about to read 5, iclass 12, count 2 2006.239.07:49:41.10#ibcon#read 5, iclass 12, count 2 2006.239.07:49:41.10#ibcon#about to read 6, iclass 12, count 2 2006.239.07:49:41.10#ibcon#read 6, iclass 12, count 2 2006.239.07:49:41.10#ibcon#end of sib2, iclass 12, count 2 2006.239.07:49:41.10#ibcon#*after write, iclass 12, count 2 2006.239.07:49:41.10#ibcon#*before return 0, iclass 12, count 2 2006.239.07:49:41.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:41.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:49:41.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.07:49:41.10#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:41.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:41.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:41.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:41.22#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:49:41.22#ibcon#first serial, iclass 12, count 0 2006.239.07:49:41.22#ibcon#enter sib2, iclass 12, count 0 2006.239.07:49:41.22#ibcon#flushed, iclass 12, count 0 2006.239.07:49:41.22#ibcon#about to write, iclass 12, count 0 2006.239.07:49:41.22#ibcon#wrote, iclass 12, count 0 2006.239.07:49:41.22#ibcon#about to read 3, iclass 12, count 0 2006.239.07:49:41.24#ibcon#read 3, iclass 12, count 0 2006.239.07:49:41.24#ibcon#about to read 4, iclass 12, count 0 2006.239.07:49:41.24#ibcon#read 4, iclass 12, count 0 2006.239.07:49:41.24#ibcon#about to read 5, iclass 12, count 0 2006.239.07:49:41.24#ibcon#read 5, iclass 12, count 0 2006.239.07:49:41.24#ibcon#about to read 6, iclass 12, count 0 2006.239.07:49:41.24#ibcon#read 6, iclass 12, count 0 2006.239.07:49:41.24#ibcon#end of sib2, iclass 12, count 0 2006.239.07:49:41.24#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:49:41.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:49:41.24#ibcon#[27=USB\r\n] 2006.239.07:49:41.24#ibcon#*before write, iclass 12, count 0 2006.239.07:49:41.24#ibcon#enter sib2, iclass 12, count 0 2006.239.07:49:41.24#ibcon#flushed, iclass 12, count 0 2006.239.07:49:41.24#ibcon#about to write, iclass 12, count 0 2006.239.07:49:41.24#ibcon#wrote, iclass 12, count 0 2006.239.07:49:41.24#ibcon#about to read 3, iclass 12, count 0 2006.239.07:49:41.27#ibcon#read 3, iclass 12, count 0 2006.239.07:49:41.27#ibcon#about to read 4, iclass 12, count 0 2006.239.07:49:41.27#ibcon#read 4, iclass 12, count 0 2006.239.07:49:41.27#ibcon#about to read 5, iclass 12, count 0 2006.239.07:49:41.27#ibcon#read 5, iclass 12, count 0 2006.239.07:49:41.27#ibcon#about to read 6, iclass 12, count 0 2006.239.07:49:41.27#ibcon#read 6, iclass 12, count 0 2006.239.07:49:41.27#ibcon#end of sib2, iclass 12, count 0 2006.239.07:49:41.27#ibcon#*after write, iclass 12, count 0 2006.239.07:49:41.27#ibcon#*before return 0, iclass 12, count 0 2006.239.07:49:41.27#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:41.27#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:49:41.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:49:41.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:49:41.27$vc4f8/vblo=3,656.99 2006.239.07:49:41.27#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:49:41.27#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:49:41.27#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:41.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:41.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:41.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:41.27#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:49:41.27#ibcon#first serial, iclass 14, count 0 2006.239.07:49:41.27#ibcon#enter sib2, iclass 14, count 0 2006.239.07:49:41.27#ibcon#flushed, iclass 14, count 0 2006.239.07:49:41.27#ibcon#about to write, iclass 14, count 0 2006.239.07:49:41.27#ibcon#wrote, iclass 14, count 0 2006.239.07:49:41.27#ibcon#about to read 3, iclass 14, count 0 2006.239.07:49:41.29#ibcon#read 3, iclass 14, count 0 2006.239.07:49:41.29#ibcon#about to read 4, iclass 14, count 0 2006.239.07:49:41.29#ibcon#read 4, iclass 14, count 0 2006.239.07:49:41.29#ibcon#about to read 5, iclass 14, count 0 2006.239.07:49:41.29#ibcon#read 5, iclass 14, count 0 2006.239.07:49:41.29#ibcon#about to read 6, iclass 14, count 0 2006.239.07:49:41.29#ibcon#read 6, iclass 14, count 0 2006.239.07:49:41.29#ibcon#end of sib2, iclass 14, count 0 2006.239.07:49:41.29#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:49:41.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:49:41.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:49:41.29#ibcon#*before write, iclass 14, count 0 2006.239.07:49:41.29#ibcon#enter sib2, iclass 14, count 0 2006.239.07:49:41.29#ibcon#flushed, iclass 14, count 0 2006.239.07:49:41.29#ibcon#about to write, iclass 14, count 0 2006.239.07:49:41.29#ibcon#wrote, iclass 14, count 0 2006.239.07:49:41.29#ibcon#about to read 3, iclass 14, count 0 2006.239.07:49:41.33#ibcon#read 3, iclass 14, count 0 2006.239.07:49:41.33#ibcon#about to read 4, iclass 14, count 0 2006.239.07:49:41.33#ibcon#read 4, iclass 14, count 0 2006.239.07:49:41.33#ibcon#about to read 5, iclass 14, count 0 2006.239.07:49:41.33#ibcon#read 5, iclass 14, count 0 2006.239.07:49:41.33#ibcon#about to read 6, iclass 14, count 0 2006.239.07:49:41.33#ibcon#read 6, iclass 14, count 0 2006.239.07:49:41.33#ibcon#end of sib2, iclass 14, count 0 2006.239.07:49:41.33#ibcon#*after write, iclass 14, count 0 2006.239.07:49:41.33#ibcon#*before return 0, iclass 14, count 0 2006.239.07:49:41.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:41.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:49:41.33#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:49:41.33#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:49:41.33$vc4f8/vb=3,4 2006.239.07:49:41.33#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:49:41.33#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:49:41.33#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:41.33#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:41.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:41.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:41.39#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:49:41.39#ibcon#first serial, iclass 16, count 2 2006.239.07:49:41.39#ibcon#enter sib2, iclass 16, count 2 2006.239.07:49:41.39#ibcon#flushed, iclass 16, count 2 2006.239.07:49:41.39#ibcon#about to write, iclass 16, count 2 2006.239.07:49:41.39#ibcon#wrote, iclass 16, count 2 2006.239.07:49:41.39#ibcon#about to read 3, iclass 16, count 2 2006.239.07:49:41.41#ibcon#read 3, iclass 16, count 2 2006.239.07:49:41.41#ibcon#about to read 4, iclass 16, count 2 2006.239.07:49:41.41#ibcon#read 4, iclass 16, count 2 2006.239.07:49:41.41#ibcon#about to read 5, iclass 16, count 2 2006.239.07:49:41.41#ibcon#read 5, iclass 16, count 2 2006.239.07:49:41.41#ibcon#about to read 6, iclass 16, count 2 2006.239.07:49:41.41#ibcon#read 6, iclass 16, count 2 2006.239.07:49:41.41#ibcon#end of sib2, iclass 16, count 2 2006.239.07:49:41.41#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:49:41.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:49:41.41#ibcon#[27=AT03-04\r\n] 2006.239.07:49:41.41#ibcon#*before write, iclass 16, count 2 2006.239.07:49:41.41#ibcon#enter sib2, iclass 16, count 2 2006.239.07:49:41.41#ibcon#flushed, iclass 16, count 2 2006.239.07:49:41.41#ibcon#about to write, iclass 16, count 2 2006.239.07:49:41.41#ibcon#wrote, iclass 16, count 2 2006.239.07:49:41.41#ibcon#about to read 3, iclass 16, count 2 2006.239.07:49:41.44#ibcon#read 3, iclass 16, count 2 2006.239.07:49:41.44#ibcon#about to read 4, iclass 16, count 2 2006.239.07:49:41.44#ibcon#read 4, iclass 16, count 2 2006.239.07:49:41.44#ibcon#about to read 5, iclass 16, count 2 2006.239.07:49:41.44#ibcon#read 5, iclass 16, count 2 2006.239.07:49:41.44#ibcon#about to read 6, iclass 16, count 2 2006.239.07:49:41.44#ibcon#read 6, iclass 16, count 2 2006.239.07:49:41.44#ibcon#end of sib2, iclass 16, count 2 2006.239.07:49:41.44#ibcon#*after write, iclass 16, count 2 2006.239.07:49:41.44#ibcon#*before return 0, iclass 16, count 2 2006.239.07:49:41.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:41.44#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:49:41.44#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:49:41.44#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:41.44#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:41.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:41.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:41.56#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:49:41.56#ibcon#first serial, iclass 16, count 0 2006.239.07:49:41.56#ibcon#enter sib2, iclass 16, count 0 2006.239.07:49:41.56#ibcon#flushed, iclass 16, count 0 2006.239.07:49:41.56#ibcon#about to write, iclass 16, count 0 2006.239.07:49:41.56#ibcon#wrote, iclass 16, count 0 2006.239.07:49:41.56#ibcon#about to read 3, iclass 16, count 0 2006.239.07:49:41.60#ibcon#read 3, iclass 16, count 0 2006.239.07:49:41.60#ibcon#about to read 4, iclass 16, count 0 2006.239.07:49:41.60#ibcon#read 4, iclass 16, count 0 2006.239.07:49:41.60#ibcon#about to read 5, iclass 16, count 0 2006.239.07:49:41.60#ibcon#read 5, iclass 16, count 0 2006.239.07:49:41.60#ibcon#about to read 6, iclass 16, count 0 2006.239.07:49:41.60#ibcon#read 6, iclass 16, count 0 2006.239.07:49:41.60#ibcon#end of sib2, iclass 16, count 0 2006.239.07:49:41.60#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:49:41.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:49:41.60#ibcon#[27=USB\r\n] 2006.239.07:49:41.60#ibcon#*before write, iclass 16, count 0 2006.239.07:49:41.60#ibcon#enter sib2, iclass 16, count 0 2006.239.07:49:41.60#ibcon#flushed, iclass 16, count 0 2006.239.07:49:41.60#ibcon#about to write, iclass 16, count 0 2006.239.07:49:41.60#ibcon#wrote, iclass 16, count 0 2006.239.07:49:41.60#ibcon#about to read 3, iclass 16, count 0 2006.239.07:49:41.63#ibcon#read 3, iclass 16, count 0 2006.239.07:49:41.63#ibcon#about to read 4, iclass 16, count 0 2006.239.07:49:41.63#ibcon#read 4, iclass 16, count 0 2006.239.07:49:41.63#ibcon#about to read 5, iclass 16, count 0 2006.239.07:49:41.63#ibcon#read 5, iclass 16, count 0 2006.239.07:49:41.63#ibcon#about to read 6, iclass 16, count 0 2006.239.07:49:41.63#ibcon#read 6, iclass 16, count 0 2006.239.07:49:41.63#ibcon#end of sib2, iclass 16, count 0 2006.239.07:49:41.63#ibcon#*after write, iclass 16, count 0 2006.239.07:49:41.63#ibcon#*before return 0, iclass 16, count 0 2006.239.07:49:41.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:41.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:49:41.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:49:41.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:49:41.63$vc4f8/vblo=4,712.99 2006.239.07:49:41.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.07:49:41.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.07:49:41.63#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:41.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:41.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:41.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:41.63#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:49:41.63#ibcon#first serial, iclass 18, count 0 2006.239.07:49:41.63#ibcon#enter sib2, iclass 18, count 0 2006.239.07:49:41.63#ibcon#flushed, iclass 18, count 0 2006.239.07:49:41.63#ibcon#about to write, iclass 18, count 0 2006.239.07:49:41.63#ibcon#wrote, iclass 18, count 0 2006.239.07:49:41.63#ibcon#about to read 3, iclass 18, count 0 2006.239.07:49:41.65#ibcon#read 3, iclass 18, count 0 2006.239.07:49:41.65#ibcon#about to read 4, iclass 18, count 0 2006.239.07:49:41.65#ibcon#read 4, iclass 18, count 0 2006.239.07:49:41.65#ibcon#about to read 5, iclass 18, count 0 2006.239.07:49:41.65#ibcon#read 5, iclass 18, count 0 2006.239.07:49:41.65#ibcon#about to read 6, iclass 18, count 0 2006.239.07:49:41.65#ibcon#read 6, iclass 18, count 0 2006.239.07:49:41.65#ibcon#end of sib2, iclass 18, count 0 2006.239.07:49:41.65#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:49:41.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:49:41.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:49:41.65#ibcon#*before write, iclass 18, count 0 2006.239.07:49:41.65#ibcon#enter sib2, iclass 18, count 0 2006.239.07:49:41.65#ibcon#flushed, iclass 18, count 0 2006.239.07:49:41.65#ibcon#about to write, iclass 18, count 0 2006.239.07:49:41.65#ibcon#wrote, iclass 18, count 0 2006.239.07:49:41.65#ibcon#about to read 3, iclass 18, count 0 2006.239.07:49:41.69#ibcon#read 3, iclass 18, count 0 2006.239.07:49:41.69#ibcon#about to read 4, iclass 18, count 0 2006.239.07:49:41.69#ibcon#read 4, iclass 18, count 0 2006.239.07:49:41.69#ibcon#about to read 5, iclass 18, count 0 2006.239.07:49:41.69#ibcon#read 5, iclass 18, count 0 2006.239.07:49:41.69#ibcon#about to read 6, iclass 18, count 0 2006.239.07:49:41.69#ibcon#read 6, iclass 18, count 0 2006.239.07:49:41.69#ibcon#end of sib2, iclass 18, count 0 2006.239.07:49:41.69#ibcon#*after write, iclass 18, count 0 2006.239.07:49:41.69#ibcon#*before return 0, iclass 18, count 0 2006.239.07:49:41.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:41.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:49:41.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:49:41.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:49:41.69$vc4f8/vb=4,4 2006.239.07:49:41.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.07:49:41.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.07:49:41.69#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:41.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:41.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:41.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:41.75#ibcon#enter wrdev, iclass 20, count 2 2006.239.07:49:41.75#ibcon#first serial, iclass 20, count 2 2006.239.07:49:41.75#ibcon#enter sib2, iclass 20, count 2 2006.239.07:49:41.75#ibcon#flushed, iclass 20, count 2 2006.239.07:49:41.75#ibcon#about to write, iclass 20, count 2 2006.239.07:49:41.75#ibcon#wrote, iclass 20, count 2 2006.239.07:49:41.75#ibcon#about to read 3, iclass 20, count 2 2006.239.07:49:41.80#ibcon#read 3, iclass 20, count 2 2006.239.07:49:41.80#ibcon#about to read 4, iclass 20, count 2 2006.239.07:49:41.80#ibcon#read 4, iclass 20, count 2 2006.239.07:49:41.80#ibcon#about to read 5, iclass 20, count 2 2006.239.07:49:41.80#ibcon#read 5, iclass 20, count 2 2006.239.07:49:41.80#ibcon#about to read 6, iclass 20, count 2 2006.239.07:49:41.80#ibcon#read 6, iclass 20, count 2 2006.239.07:49:41.80#ibcon#end of sib2, iclass 20, count 2 2006.239.07:49:41.80#ibcon#*mode == 0, iclass 20, count 2 2006.239.07:49:41.80#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.07:49:41.80#ibcon#[27=AT04-04\r\n] 2006.239.07:49:41.80#ibcon#*before write, iclass 20, count 2 2006.239.07:49:41.80#ibcon#enter sib2, iclass 20, count 2 2006.239.07:49:41.80#ibcon#flushed, iclass 20, count 2 2006.239.07:49:41.80#ibcon#about to write, iclass 20, count 2 2006.239.07:49:41.80#ibcon#wrote, iclass 20, count 2 2006.239.07:49:41.80#ibcon#about to read 3, iclass 20, count 2 2006.239.07:49:41.83#ibcon#read 3, iclass 20, count 2 2006.239.07:49:41.83#ibcon#about to read 4, iclass 20, count 2 2006.239.07:49:41.83#ibcon#read 4, iclass 20, count 2 2006.239.07:49:41.83#ibcon#about to read 5, iclass 20, count 2 2006.239.07:49:41.83#ibcon#read 5, iclass 20, count 2 2006.239.07:49:41.83#ibcon#about to read 6, iclass 20, count 2 2006.239.07:49:41.83#ibcon#read 6, iclass 20, count 2 2006.239.07:49:41.83#ibcon#end of sib2, iclass 20, count 2 2006.239.07:49:41.83#ibcon#*after write, iclass 20, count 2 2006.239.07:49:41.83#ibcon#*before return 0, iclass 20, count 2 2006.239.07:49:41.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:41.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:49:41.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.07:49:41.83#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:41.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:41.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:41.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:41.95#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:49:41.95#ibcon#first serial, iclass 20, count 0 2006.239.07:49:41.95#ibcon#enter sib2, iclass 20, count 0 2006.239.07:49:41.95#ibcon#flushed, iclass 20, count 0 2006.239.07:49:41.95#ibcon#about to write, iclass 20, count 0 2006.239.07:49:41.95#ibcon#wrote, iclass 20, count 0 2006.239.07:49:41.95#ibcon#about to read 3, iclass 20, count 0 2006.239.07:49:41.97#ibcon#read 3, iclass 20, count 0 2006.239.07:49:41.97#ibcon#about to read 4, iclass 20, count 0 2006.239.07:49:41.97#ibcon#read 4, iclass 20, count 0 2006.239.07:49:41.97#ibcon#about to read 5, iclass 20, count 0 2006.239.07:49:41.97#ibcon#read 5, iclass 20, count 0 2006.239.07:49:41.97#ibcon#about to read 6, iclass 20, count 0 2006.239.07:49:41.97#ibcon#read 6, iclass 20, count 0 2006.239.07:49:41.97#ibcon#end of sib2, iclass 20, count 0 2006.239.07:49:41.97#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:49:41.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:49:41.97#ibcon#[27=USB\r\n] 2006.239.07:49:41.97#ibcon#*before write, iclass 20, count 0 2006.239.07:49:41.97#ibcon#enter sib2, iclass 20, count 0 2006.239.07:49:41.97#ibcon#flushed, iclass 20, count 0 2006.239.07:49:41.97#ibcon#about to write, iclass 20, count 0 2006.239.07:49:41.97#ibcon#wrote, iclass 20, count 0 2006.239.07:49:41.97#ibcon#about to read 3, iclass 20, count 0 2006.239.07:49:42.00#ibcon#read 3, iclass 20, count 0 2006.239.07:49:42.00#ibcon#about to read 4, iclass 20, count 0 2006.239.07:49:42.00#ibcon#read 4, iclass 20, count 0 2006.239.07:49:42.00#ibcon#about to read 5, iclass 20, count 0 2006.239.07:49:42.00#ibcon#read 5, iclass 20, count 0 2006.239.07:49:42.00#ibcon#about to read 6, iclass 20, count 0 2006.239.07:49:42.00#ibcon#read 6, iclass 20, count 0 2006.239.07:49:42.00#ibcon#end of sib2, iclass 20, count 0 2006.239.07:49:42.00#ibcon#*after write, iclass 20, count 0 2006.239.07:49:42.00#ibcon#*before return 0, iclass 20, count 0 2006.239.07:49:42.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:42.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:49:42.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:49:42.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:49:42.00$vc4f8/vblo=5,744.99 2006.239.07:49:42.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.07:49:42.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.07:49:42.00#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:42.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:42.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:42.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:42.00#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:49:42.00#ibcon#first serial, iclass 22, count 0 2006.239.07:49:42.00#ibcon#enter sib2, iclass 22, count 0 2006.239.07:49:42.00#ibcon#flushed, iclass 22, count 0 2006.239.07:49:42.00#ibcon#about to write, iclass 22, count 0 2006.239.07:49:42.00#ibcon#wrote, iclass 22, count 0 2006.239.07:49:42.00#ibcon#about to read 3, iclass 22, count 0 2006.239.07:49:42.02#ibcon#read 3, iclass 22, count 0 2006.239.07:49:42.02#ibcon#about to read 4, iclass 22, count 0 2006.239.07:49:42.02#ibcon#read 4, iclass 22, count 0 2006.239.07:49:42.02#ibcon#about to read 5, iclass 22, count 0 2006.239.07:49:42.02#ibcon#read 5, iclass 22, count 0 2006.239.07:49:42.02#ibcon#about to read 6, iclass 22, count 0 2006.239.07:49:42.02#ibcon#read 6, iclass 22, count 0 2006.239.07:49:42.02#ibcon#end of sib2, iclass 22, count 0 2006.239.07:49:42.02#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:49:42.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:49:42.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:49:42.02#ibcon#*before write, iclass 22, count 0 2006.239.07:49:42.02#ibcon#enter sib2, iclass 22, count 0 2006.239.07:49:42.02#ibcon#flushed, iclass 22, count 0 2006.239.07:49:42.02#ibcon#about to write, iclass 22, count 0 2006.239.07:49:42.02#ibcon#wrote, iclass 22, count 0 2006.239.07:49:42.02#ibcon#about to read 3, iclass 22, count 0 2006.239.07:49:42.06#ibcon#read 3, iclass 22, count 0 2006.239.07:49:42.06#ibcon#about to read 4, iclass 22, count 0 2006.239.07:49:42.06#ibcon#read 4, iclass 22, count 0 2006.239.07:49:42.06#ibcon#about to read 5, iclass 22, count 0 2006.239.07:49:42.06#ibcon#read 5, iclass 22, count 0 2006.239.07:49:42.06#ibcon#about to read 6, iclass 22, count 0 2006.239.07:49:42.06#ibcon#read 6, iclass 22, count 0 2006.239.07:49:42.06#ibcon#end of sib2, iclass 22, count 0 2006.239.07:49:42.06#ibcon#*after write, iclass 22, count 0 2006.239.07:49:42.06#ibcon#*before return 0, iclass 22, count 0 2006.239.07:49:42.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:42.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:49:42.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:49:42.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:49:42.06$vc4f8/vb=5,4 2006.239.07:49:42.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.07:49:42.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.07:49:42.06#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:42.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:42.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:42.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:42.12#ibcon#enter wrdev, iclass 24, count 2 2006.239.07:49:42.12#ibcon#first serial, iclass 24, count 2 2006.239.07:49:42.12#ibcon#enter sib2, iclass 24, count 2 2006.239.07:49:42.12#ibcon#flushed, iclass 24, count 2 2006.239.07:49:42.12#ibcon#about to write, iclass 24, count 2 2006.239.07:49:42.12#ibcon#wrote, iclass 24, count 2 2006.239.07:49:42.12#ibcon#about to read 3, iclass 24, count 2 2006.239.07:49:42.14#ibcon#read 3, iclass 24, count 2 2006.239.07:49:42.14#ibcon#about to read 4, iclass 24, count 2 2006.239.07:49:42.14#ibcon#read 4, iclass 24, count 2 2006.239.07:49:42.14#ibcon#about to read 5, iclass 24, count 2 2006.239.07:49:42.14#ibcon#read 5, iclass 24, count 2 2006.239.07:49:42.14#ibcon#about to read 6, iclass 24, count 2 2006.239.07:49:42.14#ibcon#read 6, iclass 24, count 2 2006.239.07:49:42.14#ibcon#end of sib2, iclass 24, count 2 2006.239.07:49:42.14#ibcon#*mode == 0, iclass 24, count 2 2006.239.07:49:42.14#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.07:49:42.14#ibcon#[27=AT05-04\r\n] 2006.239.07:49:42.14#ibcon#*before write, iclass 24, count 2 2006.239.07:49:42.14#ibcon#enter sib2, iclass 24, count 2 2006.239.07:49:42.14#ibcon#flushed, iclass 24, count 2 2006.239.07:49:42.14#ibcon#about to write, iclass 24, count 2 2006.239.07:49:42.14#ibcon#wrote, iclass 24, count 2 2006.239.07:49:42.14#ibcon#about to read 3, iclass 24, count 2 2006.239.07:49:42.17#ibcon#read 3, iclass 24, count 2 2006.239.07:49:42.17#ibcon#about to read 4, iclass 24, count 2 2006.239.07:49:42.17#ibcon#read 4, iclass 24, count 2 2006.239.07:49:42.17#ibcon#about to read 5, iclass 24, count 2 2006.239.07:49:42.17#ibcon#read 5, iclass 24, count 2 2006.239.07:49:42.17#ibcon#about to read 6, iclass 24, count 2 2006.239.07:49:42.17#ibcon#read 6, iclass 24, count 2 2006.239.07:49:42.17#ibcon#end of sib2, iclass 24, count 2 2006.239.07:49:42.17#ibcon#*after write, iclass 24, count 2 2006.239.07:49:42.17#ibcon#*before return 0, iclass 24, count 2 2006.239.07:49:42.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:42.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:49:42.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.07:49:42.17#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:42.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:42.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:42.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:42.29#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:49:42.29#ibcon#first serial, iclass 24, count 0 2006.239.07:49:42.29#ibcon#enter sib2, iclass 24, count 0 2006.239.07:49:42.29#ibcon#flushed, iclass 24, count 0 2006.239.07:49:42.29#ibcon#about to write, iclass 24, count 0 2006.239.07:49:42.29#ibcon#wrote, iclass 24, count 0 2006.239.07:49:42.29#ibcon#about to read 3, iclass 24, count 0 2006.239.07:49:42.31#ibcon#read 3, iclass 24, count 0 2006.239.07:49:42.31#ibcon#about to read 4, iclass 24, count 0 2006.239.07:49:42.31#ibcon#read 4, iclass 24, count 0 2006.239.07:49:42.31#ibcon#about to read 5, iclass 24, count 0 2006.239.07:49:42.31#ibcon#read 5, iclass 24, count 0 2006.239.07:49:42.31#ibcon#about to read 6, iclass 24, count 0 2006.239.07:49:42.31#ibcon#read 6, iclass 24, count 0 2006.239.07:49:42.31#ibcon#end of sib2, iclass 24, count 0 2006.239.07:49:42.31#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:49:42.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:49:42.31#ibcon#[27=USB\r\n] 2006.239.07:49:42.31#ibcon#*before write, iclass 24, count 0 2006.239.07:49:42.31#ibcon#enter sib2, iclass 24, count 0 2006.239.07:49:42.31#ibcon#flushed, iclass 24, count 0 2006.239.07:49:42.31#ibcon#about to write, iclass 24, count 0 2006.239.07:49:42.31#ibcon#wrote, iclass 24, count 0 2006.239.07:49:42.31#ibcon#about to read 3, iclass 24, count 0 2006.239.07:49:42.34#ibcon#read 3, iclass 24, count 0 2006.239.07:49:42.34#ibcon#about to read 4, iclass 24, count 0 2006.239.07:49:42.34#ibcon#read 4, iclass 24, count 0 2006.239.07:49:42.34#ibcon#about to read 5, iclass 24, count 0 2006.239.07:49:42.34#ibcon#read 5, iclass 24, count 0 2006.239.07:49:42.34#ibcon#about to read 6, iclass 24, count 0 2006.239.07:49:42.34#ibcon#read 6, iclass 24, count 0 2006.239.07:49:42.34#ibcon#end of sib2, iclass 24, count 0 2006.239.07:49:42.34#ibcon#*after write, iclass 24, count 0 2006.239.07:49:42.34#ibcon#*before return 0, iclass 24, count 0 2006.239.07:49:42.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:42.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:49:42.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:49:42.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:49:42.34$vc4f8/vblo=6,752.99 2006.239.07:49:42.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:49:42.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:49:42.34#ibcon#ireg 17 cls_cnt 0 2006.239.07:49:42.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:42.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:42.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:42.34#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:49:42.34#ibcon#first serial, iclass 26, count 0 2006.239.07:49:42.34#ibcon#enter sib2, iclass 26, count 0 2006.239.07:49:42.34#ibcon#flushed, iclass 26, count 0 2006.239.07:49:42.34#ibcon#about to write, iclass 26, count 0 2006.239.07:49:42.34#ibcon#wrote, iclass 26, count 0 2006.239.07:49:42.34#ibcon#about to read 3, iclass 26, count 0 2006.239.07:49:42.36#ibcon#read 3, iclass 26, count 0 2006.239.07:49:42.36#ibcon#about to read 4, iclass 26, count 0 2006.239.07:49:42.36#ibcon#read 4, iclass 26, count 0 2006.239.07:49:42.36#ibcon#about to read 5, iclass 26, count 0 2006.239.07:49:42.36#ibcon#read 5, iclass 26, count 0 2006.239.07:49:42.36#ibcon#about to read 6, iclass 26, count 0 2006.239.07:49:42.36#ibcon#read 6, iclass 26, count 0 2006.239.07:49:42.36#ibcon#end of sib2, iclass 26, count 0 2006.239.07:49:42.36#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:49:42.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:49:42.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:49:42.36#ibcon#*before write, iclass 26, count 0 2006.239.07:49:42.36#ibcon#enter sib2, iclass 26, count 0 2006.239.07:49:42.36#ibcon#flushed, iclass 26, count 0 2006.239.07:49:42.36#ibcon#about to write, iclass 26, count 0 2006.239.07:49:42.36#ibcon#wrote, iclass 26, count 0 2006.239.07:49:42.36#ibcon#about to read 3, iclass 26, count 0 2006.239.07:49:42.40#ibcon#read 3, iclass 26, count 0 2006.239.07:49:42.40#ibcon#about to read 4, iclass 26, count 0 2006.239.07:49:42.40#ibcon#read 4, iclass 26, count 0 2006.239.07:49:42.40#ibcon#about to read 5, iclass 26, count 0 2006.239.07:49:42.40#ibcon#read 5, iclass 26, count 0 2006.239.07:49:42.40#ibcon#about to read 6, iclass 26, count 0 2006.239.07:49:42.40#ibcon#read 6, iclass 26, count 0 2006.239.07:49:42.40#ibcon#end of sib2, iclass 26, count 0 2006.239.07:49:42.40#ibcon#*after write, iclass 26, count 0 2006.239.07:49:42.40#ibcon#*before return 0, iclass 26, count 0 2006.239.07:49:42.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:42.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:49:42.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:49:42.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:49:42.40$vc4f8/vb=6,4 2006.239.07:49:42.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:49:42.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:49:42.40#ibcon#ireg 11 cls_cnt 2 2006.239.07:49:42.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:42.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:42.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:42.46#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:49:42.46#ibcon#first serial, iclass 28, count 2 2006.239.07:49:42.46#ibcon#enter sib2, iclass 28, count 2 2006.239.07:49:42.46#ibcon#flushed, iclass 28, count 2 2006.239.07:49:42.46#ibcon#about to write, iclass 28, count 2 2006.239.07:49:42.46#ibcon#wrote, iclass 28, count 2 2006.239.07:49:42.46#ibcon#about to read 3, iclass 28, count 2 2006.239.07:49:42.48#ibcon#read 3, iclass 28, count 2 2006.239.07:49:42.48#ibcon#about to read 4, iclass 28, count 2 2006.239.07:49:42.48#ibcon#read 4, iclass 28, count 2 2006.239.07:49:42.48#ibcon#about to read 5, iclass 28, count 2 2006.239.07:49:42.48#ibcon#read 5, iclass 28, count 2 2006.239.07:49:42.48#ibcon#about to read 6, iclass 28, count 2 2006.239.07:49:42.48#ibcon#read 6, iclass 28, count 2 2006.239.07:49:42.48#ibcon#end of sib2, iclass 28, count 2 2006.239.07:49:42.48#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:49:42.48#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:49:42.48#ibcon#[27=AT06-04\r\n] 2006.239.07:49:42.48#ibcon#*before write, iclass 28, count 2 2006.239.07:49:42.48#ibcon#enter sib2, iclass 28, count 2 2006.239.07:49:42.48#ibcon#flushed, iclass 28, count 2 2006.239.07:49:42.48#ibcon#about to write, iclass 28, count 2 2006.239.07:49:42.48#ibcon#wrote, iclass 28, count 2 2006.239.07:49:42.48#ibcon#about to read 3, iclass 28, count 2 2006.239.07:49:42.51#ibcon#read 3, iclass 28, count 2 2006.239.07:49:42.51#ibcon#about to read 4, iclass 28, count 2 2006.239.07:49:42.51#ibcon#read 4, iclass 28, count 2 2006.239.07:49:42.51#ibcon#about to read 5, iclass 28, count 2 2006.239.07:49:42.51#ibcon#read 5, iclass 28, count 2 2006.239.07:49:42.51#ibcon#about to read 6, iclass 28, count 2 2006.239.07:49:42.51#ibcon#read 6, iclass 28, count 2 2006.239.07:49:42.51#ibcon#end of sib2, iclass 28, count 2 2006.239.07:49:42.51#ibcon#*after write, iclass 28, count 2 2006.239.07:49:42.51#ibcon#*before return 0, iclass 28, count 2 2006.239.07:49:42.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:42.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:49:42.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:49:42.51#ibcon#ireg 7 cls_cnt 0 2006.239.07:49:42.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:42.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:42.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:42.63#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:49:42.63#ibcon#first serial, iclass 28, count 0 2006.239.07:49:42.63#ibcon#enter sib2, iclass 28, count 0 2006.239.07:49:42.63#ibcon#flushed, iclass 28, count 0 2006.239.07:49:42.63#ibcon#about to write, iclass 28, count 0 2006.239.07:49:42.63#ibcon#wrote, iclass 28, count 0 2006.239.07:49:42.63#ibcon#about to read 3, iclass 28, count 0 2006.239.07:49:42.65#ibcon#read 3, iclass 28, count 0 2006.239.07:49:42.65#ibcon#about to read 4, iclass 28, count 0 2006.239.07:49:42.65#ibcon#read 4, iclass 28, count 0 2006.239.07:49:42.65#ibcon#about to read 5, iclass 28, count 0 2006.239.07:49:42.65#ibcon#read 5, iclass 28, count 0 2006.239.07:49:42.65#ibcon#about to read 6, iclass 28, count 0 2006.239.07:49:42.65#ibcon#read 6, iclass 28, count 0 2006.239.07:49:42.65#ibcon#end of sib2, iclass 28, count 0 2006.239.07:49:42.65#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:49:42.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:49:42.65#ibcon#[27=USB\r\n] 2006.239.07:49:42.65#ibcon#*before write, iclass 28, count 0 2006.239.07:49:42.65#ibcon#enter sib2, iclass 28, count 0 2006.239.07:49:42.65#ibcon#flushed, iclass 28, count 0 2006.239.07:49:42.65#ibcon#about to write, iclass 28, count 0 2006.239.07:49:42.65#ibcon#wrote, iclass 28, count 0 2006.239.07:49:42.65#ibcon#about to read 3, iclass 28, count 0 2006.239.07:49:42.68#ibcon#read 3, iclass 28, count 0 2006.239.07:49:42.68#ibcon#about to read 4, iclass 28, count 0 2006.239.07:49:42.68#ibcon#read 4, iclass 28, count 0 2006.239.07:49:42.68#ibcon#about to read 5, iclass 28, count 0 2006.239.07:49:42.68#ibcon#read 5, iclass 28, count 0 2006.239.07:49:42.68#ibcon#about to read 6, iclass 28, count 0 2006.239.07:49:42.68#ibcon#read 6, iclass 28, count 0 2006.239.07:49:42.68#ibcon#end of sib2, iclass 28, count 0 2006.239.07:49:42.68#ibcon#*after write, iclass 28, count 0 2006.239.07:49:42.68#ibcon#*before return 0, iclass 28, count 0 2006.239.07:49:42.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:42.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:49:42.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:49:42.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:49:42.68$vc4f8/vabw=wide 2006.239.07:49:42.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:49:42.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:49:42.68#ibcon#ireg 8 cls_cnt 0 2006.239.07:49:42.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:42.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:42.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:42.68#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:49:42.68#ibcon#first serial, iclass 30, count 0 2006.239.07:49:42.68#ibcon#enter sib2, iclass 30, count 0 2006.239.07:49:42.68#ibcon#flushed, iclass 30, count 0 2006.239.07:49:42.68#ibcon#about to write, iclass 30, count 0 2006.239.07:49:42.68#ibcon#wrote, iclass 30, count 0 2006.239.07:49:42.68#ibcon#about to read 3, iclass 30, count 0 2006.239.07:49:42.70#ibcon#read 3, iclass 30, count 0 2006.239.07:49:42.70#ibcon#about to read 4, iclass 30, count 0 2006.239.07:49:42.70#ibcon#read 4, iclass 30, count 0 2006.239.07:49:42.70#ibcon#about to read 5, iclass 30, count 0 2006.239.07:49:42.70#ibcon#read 5, iclass 30, count 0 2006.239.07:49:42.70#ibcon#about to read 6, iclass 30, count 0 2006.239.07:49:42.70#ibcon#read 6, iclass 30, count 0 2006.239.07:49:42.70#ibcon#end of sib2, iclass 30, count 0 2006.239.07:49:42.70#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:49:42.70#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:49:42.70#ibcon#[25=BW32\r\n] 2006.239.07:49:42.70#ibcon#*before write, iclass 30, count 0 2006.239.07:49:42.70#ibcon#enter sib2, iclass 30, count 0 2006.239.07:49:42.70#ibcon#flushed, iclass 30, count 0 2006.239.07:49:42.70#ibcon#about to write, iclass 30, count 0 2006.239.07:49:42.70#ibcon#wrote, iclass 30, count 0 2006.239.07:49:42.70#ibcon#about to read 3, iclass 30, count 0 2006.239.07:49:42.73#ibcon#read 3, iclass 30, count 0 2006.239.07:49:42.73#ibcon#about to read 4, iclass 30, count 0 2006.239.07:49:42.73#ibcon#read 4, iclass 30, count 0 2006.239.07:49:42.73#ibcon#about to read 5, iclass 30, count 0 2006.239.07:49:42.73#ibcon#read 5, iclass 30, count 0 2006.239.07:49:42.73#ibcon#about to read 6, iclass 30, count 0 2006.239.07:49:42.73#ibcon#read 6, iclass 30, count 0 2006.239.07:49:42.73#ibcon#end of sib2, iclass 30, count 0 2006.239.07:49:42.73#ibcon#*after write, iclass 30, count 0 2006.239.07:49:42.73#ibcon#*before return 0, iclass 30, count 0 2006.239.07:49:42.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:42.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:49:42.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:49:42.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:49:42.73$vc4f8/vbbw=wide 2006.239.07:49:42.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.07:49:42.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.07:49:42.73#ibcon#ireg 8 cls_cnt 0 2006.239.07:49:42.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:49:42.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:49:42.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:49:42.80#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:49:42.80#ibcon#first serial, iclass 32, count 0 2006.239.07:49:42.80#ibcon#enter sib2, iclass 32, count 0 2006.239.07:49:42.80#ibcon#flushed, iclass 32, count 0 2006.239.07:49:42.80#ibcon#about to write, iclass 32, count 0 2006.239.07:49:42.80#ibcon#wrote, iclass 32, count 0 2006.239.07:49:42.80#ibcon#about to read 3, iclass 32, count 0 2006.239.07:49:42.82#ibcon#read 3, iclass 32, count 0 2006.239.07:49:42.82#ibcon#about to read 4, iclass 32, count 0 2006.239.07:49:42.82#ibcon#read 4, iclass 32, count 0 2006.239.07:49:42.82#ibcon#about to read 5, iclass 32, count 0 2006.239.07:49:42.82#ibcon#read 5, iclass 32, count 0 2006.239.07:49:42.82#ibcon#about to read 6, iclass 32, count 0 2006.239.07:49:42.82#ibcon#read 6, iclass 32, count 0 2006.239.07:49:42.82#ibcon#end of sib2, iclass 32, count 0 2006.239.07:49:42.82#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:49:42.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:49:42.82#ibcon#[27=BW32\r\n] 2006.239.07:49:42.82#ibcon#*before write, iclass 32, count 0 2006.239.07:49:42.82#ibcon#enter sib2, iclass 32, count 0 2006.239.07:49:42.82#ibcon#flushed, iclass 32, count 0 2006.239.07:49:42.82#ibcon#about to write, iclass 32, count 0 2006.239.07:49:42.82#ibcon#wrote, iclass 32, count 0 2006.239.07:49:42.82#ibcon#about to read 3, iclass 32, count 0 2006.239.07:49:42.85#ibcon#read 3, iclass 32, count 0 2006.239.07:49:42.85#ibcon#about to read 4, iclass 32, count 0 2006.239.07:49:42.85#ibcon#read 4, iclass 32, count 0 2006.239.07:49:42.85#ibcon#about to read 5, iclass 32, count 0 2006.239.07:49:42.85#ibcon#read 5, iclass 32, count 0 2006.239.07:49:42.85#ibcon#about to read 6, iclass 32, count 0 2006.239.07:49:42.85#ibcon#read 6, iclass 32, count 0 2006.239.07:49:42.85#ibcon#end of sib2, iclass 32, count 0 2006.239.07:49:42.85#ibcon#*after write, iclass 32, count 0 2006.239.07:49:42.85#ibcon#*before return 0, iclass 32, count 0 2006.239.07:49:42.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:49:42.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:49:42.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:49:42.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:49:42.85$4f8m12a/ifd4f 2006.239.07:49:42.85$ifd4f/lo= 2006.239.07:49:42.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:49:42.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:49:42.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:49:42.85$ifd4f/patch= 2006.239.07:49:42.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:49:42.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:49:42.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:49:42.85$4f8m12a/"form=m,16.000,1:2 2006.239.07:49:42.85$4f8m12a/"tpicd 2006.239.07:49:42.85$4f8m12a/echo=off 2006.239.07:49:42.85$4f8m12a/xlog=off 2006.239.07:49:42.85:!2006.239.07:50:10 2006.239.07:49:53.13#trakl#Source acquired 2006.239.07:49:54.13#flagr#flagr/antenna,acquired 2006.239.07:50:10.00:preob 2006.239.07:50:10.13/onsource/TRACKING 2006.239.07:50:10.13:!2006.239.07:50:20 2006.239.07:50:20.00:data_valid=on 2006.239.07:50:20.00:midob 2006.239.07:50:21.13/onsource/TRACKING 2006.239.07:50:21.13/wx/25.27,1011.6,79 2006.239.07:50:21.22/cable/+6.4150E-03 2006.239.07:50:22.31/va/01,08,usb,yes,30,32 2006.239.07:50:22.31/va/02,07,usb,yes,30,32 2006.239.07:50:22.31/va/03,07,usb,yes,29,29 2006.239.07:50:22.31/va/04,07,usb,yes,32,35 2006.239.07:50:22.31/va/05,08,usb,yes,29,30 2006.239.07:50:22.31/va/06,07,usb,yes,31,31 2006.239.07:50:22.31/va/07,07,usb,yes,31,31 2006.239.07:50:22.31/va/08,07,usb,yes,34,33 2006.239.07:50:22.54/valo/01,532.99,yes,locked 2006.239.07:50:22.54/valo/02,572.99,yes,locked 2006.239.07:50:22.54/valo/03,672.99,yes,locked 2006.239.07:50:22.54/valo/04,832.99,yes,locked 2006.239.07:50:22.54/valo/05,652.99,yes,locked 2006.239.07:50:22.54/valo/06,772.99,yes,locked 2006.239.07:50:22.54/valo/07,832.99,yes,locked 2006.239.07:50:22.54/valo/08,852.99,yes,locked 2006.239.07:50:23.63/vb/01,04,usb,yes,30,29 2006.239.07:50:23.63/vb/02,04,usb,yes,32,33 2006.239.07:50:23.63/vb/03,04,usb,yes,28,32 2006.239.07:50:23.63/vb/04,04,usb,yes,29,29 2006.239.07:50:23.63/vb/05,04,usb,yes,27,31 2006.239.07:50:23.63/vb/06,04,usb,yes,28,31 2006.239.07:50:23.63/vb/07,04,usb,yes,30,30 2006.239.07:50:23.63/vb/08,04,usb,yes,28,31 2006.239.07:50:23.86/vblo/01,632.99,yes,locked 2006.239.07:50:23.86/vblo/02,640.99,yes,locked 2006.239.07:50:23.86/vblo/03,656.99,yes,locked 2006.239.07:50:23.86/vblo/04,712.99,yes,locked 2006.239.07:50:23.86/vblo/05,744.99,yes,locked 2006.239.07:50:23.86/vblo/06,752.99,yes,locked 2006.239.07:50:23.86/vblo/07,734.99,yes,locked 2006.239.07:50:23.86/vblo/08,744.99,yes,locked 2006.239.07:50:24.01/vabw/8 2006.239.07:50:24.16/vbbw/8 2006.239.07:50:24.25/xfe/off,on,14.0 2006.239.07:50:24.64/ifatt/23,28,28,28 2006.239.07:50:25.08/fmout-gps/S +4.42E-07 2006.239.07:50:25.12:!2006.239.07:51:20 2006.239.07:51:20.01:data_valid=off 2006.239.07:51:20.01:postob 2006.239.07:51:20.10/cable/+6.4146E-03 2006.239.07:51:20.10/wx/25.25,1011.6,80 2006.239.07:51:21.07/fmout-gps/S +4.43E-07 2006.239.07:51:21.07:scan_name=239-0752,k06239,60 2006.239.07:51:21.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.239.07:51:21.14#flagr#flagr/antenna,new-source 2006.239.07:51:22.14:checkk5 2006.239.07:51:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:51:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:51:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:51:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:51:24.04/chk_obsdata//k5ts1/T2390750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:51:24.42/chk_obsdata//k5ts2/T2390750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:51:24.80/chk_obsdata//k5ts3/T2390750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:51:25.18/chk_obsdata//k5ts4/T2390750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:51:25.87/k5log//k5ts1_log_newline 2006.239.07:51:26.56/k5log//k5ts2_log_newline 2006.239.07:51:27.26/k5log//k5ts3_log_newline 2006.239.07:51:27.95/k5log//k5ts4_log_newline 2006.239.07:51:27.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:51:27.97:4f8m12a=1 2006.239.07:51:27.97$4f8m12a/echo=on 2006.239.07:51:27.97$4f8m12a/pcalon 2006.239.07:51:27.97$pcalon/"no phase cal control is implemented here 2006.239.07:51:27.97$4f8m12a/"tpicd=stop 2006.239.07:51:27.97$4f8m12a/vc4f8 2006.239.07:51:27.97$vc4f8/valo=1,532.99 2006.239.07:51:27.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:51:27.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:51:27.97#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:27.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:27.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:27.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:27.97#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:51:27.97#ibcon#first serial, iclass 5, count 0 2006.239.07:51:27.97#ibcon#enter sib2, iclass 5, count 0 2006.239.07:51:27.97#ibcon#flushed, iclass 5, count 0 2006.239.07:51:27.97#ibcon#about to write, iclass 5, count 0 2006.239.07:51:27.97#ibcon#wrote, iclass 5, count 0 2006.239.07:51:27.97#ibcon#about to read 3, iclass 5, count 0 2006.239.07:51:28.02#ibcon#read 3, iclass 5, count 0 2006.239.07:51:28.02#ibcon#about to read 4, iclass 5, count 0 2006.239.07:51:28.02#ibcon#read 4, iclass 5, count 0 2006.239.07:51:28.02#ibcon#about to read 5, iclass 5, count 0 2006.239.07:51:28.02#ibcon#read 5, iclass 5, count 0 2006.239.07:51:28.02#ibcon#about to read 6, iclass 5, count 0 2006.239.07:51:28.02#ibcon#read 6, iclass 5, count 0 2006.239.07:51:28.02#ibcon#end of sib2, iclass 5, count 0 2006.239.07:51:28.02#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:51:28.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:51:28.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:51:28.02#ibcon#*before write, iclass 5, count 0 2006.239.07:51:28.02#ibcon#enter sib2, iclass 5, count 0 2006.239.07:51:28.02#ibcon#flushed, iclass 5, count 0 2006.239.07:51:28.02#ibcon#about to write, iclass 5, count 0 2006.239.07:51:28.02#ibcon#wrote, iclass 5, count 0 2006.239.07:51:28.02#ibcon#about to read 3, iclass 5, count 0 2006.239.07:51:28.07#ibcon#read 3, iclass 5, count 0 2006.239.07:51:28.07#ibcon#about to read 4, iclass 5, count 0 2006.239.07:51:28.07#ibcon#read 4, iclass 5, count 0 2006.239.07:51:28.07#ibcon#about to read 5, iclass 5, count 0 2006.239.07:51:28.07#ibcon#read 5, iclass 5, count 0 2006.239.07:51:28.07#ibcon#about to read 6, iclass 5, count 0 2006.239.07:51:28.07#ibcon#read 6, iclass 5, count 0 2006.239.07:51:28.07#ibcon#end of sib2, iclass 5, count 0 2006.239.07:51:28.07#ibcon#*after write, iclass 5, count 0 2006.239.07:51:28.07#ibcon#*before return 0, iclass 5, count 0 2006.239.07:51:28.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:28.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:28.07#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:51:28.07#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:51:28.07$vc4f8/va=1,8 2006.239.07:51:28.07#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.07:51:28.07#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.07:51:28.07#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:28.07#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:28.07#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:28.07#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:28.07#ibcon#enter wrdev, iclass 7, count 2 2006.239.07:51:28.07#ibcon#first serial, iclass 7, count 2 2006.239.07:51:28.07#ibcon#enter sib2, iclass 7, count 2 2006.239.07:51:28.07#ibcon#flushed, iclass 7, count 2 2006.239.07:51:28.07#ibcon#about to write, iclass 7, count 2 2006.239.07:51:28.07#ibcon#wrote, iclass 7, count 2 2006.239.07:51:28.07#ibcon#about to read 3, iclass 7, count 2 2006.239.07:51:28.09#ibcon#read 3, iclass 7, count 2 2006.239.07:51:28.09#ibcon#about to read 4, iclass 7, count 2 2006.239.07:51:28.09#ibcon#read 4, iclass 7, count 2 2006.239.07:51:28.09#ibcon#about to read 5, iclass 7, count 2 2006.239.07:51:28.09#ibcon#read 5, iclass 7, count 2 2006.239.07:51:28.09#ibcon#about to read 6, iclass 7, count 2 2006.239.07:51:28.09#ibcon#read 6, iclass 7, count 2 2006.239.07:51:28.09#ibcon#end of sib2, iclass 7, count 2 2006.239.07:51:28.09#ibcon#*mode == 0, iclass 7, count 2 2006.239.07:51:28.09#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.07:51:28.09#ibcon#[25=AT01-08\r\n] 2006.239.07:51:28.09#ibcon#*before write, iclass 7, count 2 2006.239.07:51:28.09#ibcon#enter sib2, iclass 7, count 2 2006.239.07:51:28.09#ibcon#flushed, iclass 7, count 2 2006.239.07:51:28.09#ibcon#about to write, iclass 7, count 2 2006.239.07:51:28.09#ibcon#wrote, iclass 7, count 2 2006.239.07:51:28.09#ibcon#about to read 3, iclass 7, count 2 2006.239.07:51:28.12#ibcon#read 3, iclass 7, count 2 2006.239.07:51:28.12#ibcon#about to read 4, iclass 7, count 2 2006.239.07:51:28.12#ibcon#read 4, iclass 7, count 2 2006.239.07:51:28.12#ibcon#about to read 5, iclass 7, count 2 2006.239.07:51:28.12#ibcon#read 5, iclass 7, count 2 2006.239.07:51:28.12#ibcon#about to read 6, iclass 7, count 2 2006.239.07:51:28.12#ibcon#read 6, iclass 7, count 2 2006.239.07:51:28.12#ibcon#end of sib2, iclass 7, count 2 2006.239.07:51:28.12#ibcon#*after write, iclass 7, count 2 2006.239.07:51:28.12#ibcon#*before return 0, iclass 7, count 2 2006.239.07:51:28.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:28.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:28.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.07:51:28.12#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:28.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:28.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:28.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:28.24#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:51:28.24#ibcon#first serial, iclass 7, count 0 2006.239.07:51:28.24#ibcon#enter sib2, iclass 7, count 0 2006.239.07:51:28.24#ibcon#flushed, iclass 7, count 0 2006.239.07:51:28.24#ibcon#about to write, iclass 7, count 0 2006.239.07:51:28.24#ibcon#wrote, iclass 7, count 0 2006.239.07:51:28.24#ibcon#about to read 3, iclass 7, count 0 2006.239.07:51:28.26#ibcon#read 3, iclass 7, count 0 2006.239.07:51:28.26#ibcon#about to read 4, iclass 7, count 0 2006.239.07:51:28.26#ibcon#read 4, iclass 7, count 0 2006.239.07:51:28.26#ibcon#about to read 5, iclass 7, count 0 2006.239.07:51:28.26#ibcon#read 5, iclass 7, count 0 2006.239.07:51:28.26#ibcon#about to read 6, iclass 7, count 0 2006.239.07:51:28.26#ibcon#read 6, iclass 7, count 0 2006.239.07:51:28.26#ibcon#end of sib2, iclass 7, count 0 2006.239.07:51:28.26#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:51:28.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:51:28.26#ibcon#[25=USB\r\n] 2006.239.07:51:28.26#ibcon#*before write, iclass 7, count 0 2006.239.07:51:28.26#ibcon#enter sib2, iclass 7, count 0 2006.239.07:51:28.26#ibcon#flushed, iclass 7, count 0 2006.239.07:51:28.26#ibcon#about to write, iclass 7, count 0 2006.239.07:51:28.26#ibcon#wrote, iclass 7, count 0 2006.239.07:51:28.26#ibcon#about to read 3, iclass 7, count 0 2006.239.07:51:28.29#ibcon#read 3, iclass 7, count 0 2006.239.07:51:28.29#ibcon#about to read 4, iclass 7, count 0 2006.239.07:51:28.29#ibcon#read 4, iclass 7, count 0 2006.239.07:51:28.29#ibcon#about to read 5, iclass 7, count 0 2006.239.07:51:28.29#ibcon#read 5, iclass 7, count 0 2006.239.07:51:28.29#ibcon#about to read 6, iclass 7, count 0 2006.239.07:51:28.29#ibcon#read 6, iclass 7, count 0 2006.239.07:51:28.29#ibcon#end of sib2, iclass 7, count 0 2006.239.07:51:28.29#ibcon#*after write, iclass 7, count 0 2006.239.07:51:28.29#ibcon#*before return 0, iclass 7, count 0 2006.239.07:51:28.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:28.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:28.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:51:28.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:51:28.29$vc4f8/valo=2,572.99 2006.239.07:51:28.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.07:51:28.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.07:51:28.29#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:28.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:28.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:28.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:28.29#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:51:28.29#ibcon#first serial, iclass 11, count 0 2006.239.07:51:28.29#ibcon#enter sib2, iclass 11, count 0 2006.239.07:51:28.29#ibcon#flushed, iclass 11, count 0 2006.239.07:51:28.29#ibcon#about to write, iclass 11, count 0 2006.239.07:51:28.29#ibcon#wrote, iclass 11, count 0 2006.239.07:51:28.29#ibcon#about to read 3, iclass 11, count 0 2006.239.07:51:28.31#ibcon#read 3, iclass 11, count 0 2006.239.07:51:28.31#ibcon#about to read 4, iclass 11, count 0 2006.239.07:51:28.31#ibcon#read 4, iclass 11, count 0 2006.239.07:51:28.31#ibcon#about to read 5, iclass 11, count 0 2006.239.07:51:28.31#ibcon#read 5, iclass 11, count 0 2006.239.07:51:28.31#ibcon#about to read 6, iclass 11, count 0 2006.239.07:51:28.31#ibcon#read 6, iclass 11, count 0 2006.239.07:51:28.31#ibcon#end of sib2, iclass 11, count 0 2006.239.07:51:28.31#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:51:28.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:51:28.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:51:28.31#ibcon#*before write, iclass 11, count 0 2006.239.07:51:28.31#ibcon#enter sib2, iclass 11, count 0 2006.239.07:51:28.31#ibcon#flushed, iclass 11, count 0 2006.239.07:51:28.31#ibcon#about to write, iclass 11, count 0 2006.239.07:51:28.31#ibcon#wrote, iclass 11, count 0 2006.239.07:51:28.31#ibcon#about to read 3, iclass 11, count 0 2006.239.07:51:28.35#ibcon#read 3, iclass 11, count 0 2006.239.07:51:28.35#ibcon#about to read 4, iclass 11, count 0 2006.239.07:51:28.35#ibcon#read 4, iclass 11, count 0 2006.239.07:51:28.35#ibcon#about to read 5, iclass 11, count 0 2006.239.07:51:28.35#ibcon#read 5, iclass 11, count 0 2006.239.07:51:28.35#ibcon#about to read 6, iclass 11, count 0 2006.239.07:51:28.35#ibcon#read 6, iclass 11, count 0 2006.239.07:51:28.35#ibcon#end of sib2, iclass 11, count 0 2006.239.07:51:28.35#ibcon#*after write, iclass 11, count 0 2006.239.07:51:28.35#ibcon#*before return 0, iclass 11, count 0 2006.239.07:51:28.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:28.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:28.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:51:28.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:51:28.35$vc4f8/va=2,7 2006.239.07:51:28.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.07:51:28.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.07:51:28.35#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:28.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:28.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:28.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:28.41#ibcon#enter wrdev, iclass 13, count 2 2006.239.07:51:28.41#ibcon#first serial, iclass 13, count 2 2006.239.07:51:28.41#ibcon#enter sib2, iclass 13, count 2 2006.239.07:51:28.41#ibcon#flushed, iclass 13, count 2 2006.239.07:51:28.41#ibcon#about to write, iclass 13, count 2 2006.239.07:51:28.41#ibcon#wrote, iclass 13, count 2 2006.239.07:51:28.41#ibcon#about to read 3, iclass 13, count 2 2006.239.07:51:28.44#ibcon#read 3, iclass 13, count 2 2006.239.07:51:28.44#ibcon#about to read 4, iclass 13, count 2 2006.239.07:51:28.44#ibcon#read 4, iclass 13, count 2 2006.239.07:51:28.44#ibcon#about to read 5, iclass 13, count 2 2006.239.07:51:28.44#ibcon#read 5, iclass 13, count 2 2006.239.07:51:28.44#ibcon#about to read 6, iclass 13, count 2 2006.239.07:51:28.44#ibcon#read 6, iclass 13, count 2 2006.239.07:51:28.44#ibcon#end of sib2, iclass 13, count 2 2006.239.07:51:28.44#ibcon#*mode == 0, iclass 13, count 2 2006.239.07:51:28.44#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.07:51:28.44#ibcon#[25=AT02-07\r\n] 2006.239.07:51:28.44#ibcon#*before write, iclass 13, count 2 2006.239.07:51:28.44#ibcon#enter sib2, iclass 13, count 2 2006.239.07:51:28.44#ibcon#flushed, iclass 13, count 2 2006.239.07:51:28.44#ibcon#about to write, iclass 13, count 2 2006.239.07:51:28.44#ibcon#wrote, iclass 13, count 2 2006.239.07:51:28.44#ibcon#about to read 3, iclass 13, count 2 2006.239.07:51:28.47#ibcon#read 3, iclass 13, count 2 2006.239.07:51:28.47#ibcon#about to read 4, iclass 13, count 2 2006.239.07:51:28.47#ibcon#read 4, iclass 13, count 2 2006.239.07:51:28.47#ibcon#about to read 5, iclass 13, count 2 2006.239.07:51:28.47#ibcon#read 5, iclass 13, count 2 2006.239.07:51:28.47#ibcon#about to read 6, iclass 13, count 2 2006.239.07:51:28.47#ibcon#read 6, iclass 13, count 2 2006.239.07:51:28.47#ibcon#end of sib2, iclass 13, count 2 2006.239.07:51:28.47#ibcon#*after write, iclass 13, count 2 2006.239.07:51:28.47#ibcon#*before return 0, iclass 13, count 2 2006.239.07:51:28.47#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:28.47#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:28.47#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.07:51:28.47#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:28.47#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:28.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:28.59#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:28.59#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:51:28.59#ibcon#first serial, iclass 13, count 0 2006.239.07:51:28.59#ibcon#enter sib2, iclass 13, count 0 2006.239.07:51:28.59#ibcon#flushed, iclass 13, count 0 2006.239.07:51:28.59#ibcon#about to write, iclass 13, count 0 2006.239.07:51:28.59#ibcon#wrote, iclass 13, count 0 2006.239.07:51:28.59#ibcon#about to read 3, iclass 13, count 0 2006.239.07:51:28.61#ibcon#read 3, iclass 13, count 0 2006.239.07:51:28.61#ibcon#about to read 4, iclass 13, count 0 2006.239.07:51:28.61#ibcon#read 4, iclass 13, count 0 2006.239.07:51:28.61#ibcon#about to read 5, iclass 13, count 0 2006.239.07:51:28.61#ibcon#read 5, iclass 13, count 0 2006.239.07:51:28.61#ibcon#about to read 6, iclass 13, count 0 2006.239.07:51:28.61#ibcon#read 6, iclass 13, count 0 2006.239.07:51:28.61#ibcon#end of sib2, iclass 13, count 0 2006.239.07:51:28.61#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:51:28.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:51:28.61#ibcon#[25=USB\r\n] 2006.239.07:51:28.61#ibcon#*before write, iclass 13, count 0 2006.239.07:51:28.61#ibcon#enter sib2, iclass 13, count 0 2006.239.07:51:28.61#ibcon#flushed, iclass 13, count 0 2006.239.07:51:28.61#ibcon#about to write, iclass 13, count 0 2006.239.07:51:28.61#ibcon#wrote, iclass 13, count 0 2006.239.07:51:28.61#ibcon#about to read 3, iclass 13, count 0 2006.239.07:51:28.64#ibcon#read 3, iclass 13, count 0 2006.239.07:51:28.64#ibcon#about to read 4, iclass 13, count 0 2006.239.07:51:28.64#ibcon#read 4, iclass 13, count 0 2006.239.07:51:28.64#ibcon#about to read 5, iclass 13, count 0 2006.239.07:51:28.64#ibcon#read 5, iclass 13, count 0 2006.239.07:51:28.64#ibcon#about to read 6, iclass 13, count 0 2006.239.07:51:28.64#ibcon#read 6, iclass 13, count 0 2006.239.07:51:28.64#ibcon#end of sib2, iclass 13, count 0 2006.239.07:51:28.64#ibcon#*after write, iclass 13, count 0 2006.239.07:51:28.64#ibcon#*before return 0, iclass 13, count 0 2006.239.07:51:28.64#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:28.64#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:28.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:51:28.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:51:28.64$vc4f8/valo=3,672.99 2006.239.07:51:28.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.07:51:28.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.07:51:28.64#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:28.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:28.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:28.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:28.64#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:51:28.64#ibcon#first serial, iclass 15, count 0 2006.239.07:51:28.64#ibcon#enter sib2, iclass 15, count 0 2006.239.07:51:28.64#ibcon#flushed, iclass 15, count 0 2006.239.07:51:28.64#ibcon#about to write, iclass 15, count 0 2006.239.07:51:28.64#ibcon#wrote, iclass 15, count 0 2006.239.07:51:28.64#ibcon#about to read 3, iclass 15, count 0 2006.239.07:51:28.66#ibcon#read 3, iclass 15, count 0 2006.239.07:51:28.66#ibcon#about to read 4, iclass 15, count 0 2006.239.07:51:28.66#ibcon#read 4, iclass 15, count 0 2006.239.07:51:28.66#ibcon#about to read 5, iclass 15, count 0 2006.239.07:51:28.66#ibcon#read 5, iclass 15, count 0 2006.239.07:51:28.66#ibcon#about to read 6, iclass 15, count 0 2006.239.07:51:28.66#ibcon#read 6, iclass 15, count 0 2006.239.07:51:28.66#ibcon#end of sib2, iclass 15, count 0 2006.239.07:51:28.66#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:51:28.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:51:28.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:51:28.66#ibcon#*before write, iclass 15, count 0 2006.239.07:51:28.66#ibcon#enter sib2, iclass 15, count 0 2006.239.07:51:28.66#ibcon#flushed, iclass 15, count 0 2006.239.07:51:28.66#ibcon#about to write, iclass 15, count 0 2006.239.07:51:28.66#ibcon#wrote, iclass 15, count 0 2006.239.07:51:28.66#ibcon#about to read 3, iclass 15, count 0 2006.239.07:51:28.70#ibcon#read 3, iclass 15, count 0 2006.239.07:51:28.70#ibcon#about to read 4, iclass 15, count 0 2006.239.07:51:28.70#ibcon#read 4, iclass 15, count 0 2006.239.07:51:28.70#ibcon#about to read 5, iclass 15, count 0 2006.239.07:51:28.70#ibcon#read 5, iclass 15, count 0 2006.239.07:51:28.70#ibcon#about to read 6, iclass 15, count 0 2006.239.07:51:28.70#ibcon#read 6, iclass 15, count 0 2006.239.07:51:28.70#ibcon#end of sib2, iclass 15, count 0 2006.239.07:51:28.70#ibcon#*after write, iclass 15, count 0 2006.239.07:51:28.70#ibcon#*before return 0, iclass 15, count 0 2006.239.07:51:28.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:28.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:28.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:51:28.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:51:28.70$vc4f8/va=3,7 2006.239.07:51:28.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.07:51:28.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.07:51:28.70#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:28.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:28.76#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:28.76#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:28.76#ibcon#enter wrdev, iclass 17, count 2 2006.239.07:51:28.76#ibcon#first serial, iclass 17, count 2 2006.239.07:51:28.76#ibcon#enter sib2, iclass 17, count 2 2006.239.07:51:28.76#ibcon#flushed, iclass 17, count 2 2006.239.07:51:28.76#ibcon#about to write, iclass 17, count 2 2006.239.07:51:28.76#ibcon#wrote, iclass 17, count 2 2006.239.07:51:28.76#ibcon#about to read 3, iclass 17, count 2 2006.239.07:51:28.78#ibcon#read 3, iclass 17, count 2 2006.239.07:51:28.78#ibcon#about to read 4, iclass 17, count 2 2006.239.07:51:28.78#ibcon#read 4, iclass 17, count 2 2006.239.07:51:28.78#ibcon#about to read 5, iclass 17, count 2 2006.239.07:51:28.78#ibcon#read 5, iclass 17, count 2 2006.239.07:51:28.78#ibcon#about to read 6, iclass 17, count 2 2006.239.07:51:28.78#ibcon#read 6, iclass 17, count 2 2006.239.07:51:28.78#ibcon#end of sib2, iclass 17, count 2 2006.239.07:51:28.78#ibcon#*mode == 0, iclass 17, count 2 2006.239.07:51:28.78#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.07:51:28.78#ibcon#[25=AT03-07\r\n] 2006.239.07:51:28.78#ibcon#*before write, iclass 17, count 2 2006.239.07:51:28.78#ibcon#enter sib2, iclass 17, count 2 2006.239.07:51:28.78#ibcon#flushed, iclass 17, count 2 2006.239.07:51:28.78#ibcon#about to write, iclass 17, count 2 2006.239.07:51:28.78#ibcon#wrote, iclass 17, count 2 2006.239.07:51:28.78#ibcon#about to read 3, iclass 17, count 2 2006.239.07:51:28.81#ibcon#read 3, iclass 17, count 2 2006.239.07:51:28.81#ibcon#about to read 4, iclass 17, count 2 2006.239.07:51:28.81#ibcon#read 4, iclass 17, count 2 2006.239.07:51:28.81#ibcon#about to read 5, iclass 17, count 2 2006.239.07:51:28.81#ibcon#read 5, iclass 17, count 2 2006.239.07:51:28.81#ibcon#about to read 6, iclass 17, count 2 2006.239.07:51:28.81#ibcon#read 6, iclass 17, count 2 2006.239.07:51:28.81#ibcon#end of sib2, iclass 17, count 2 2006.239.07:51:28.81#ibcon#*after write, iclass 17, count 2 2006.239.07:51:28.81#ibcon#*before return 0, iclass 17, count 2 2006.239.07:51:28.81#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:28.81#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:28.81#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.07:51:28.81#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:28.81#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:28.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:28.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:28.93#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:51:28.93#ibcon#first serial, iclass 17, count 0 2006.239.07:51:28.93#ibcon#enter sib2, iclass 17, count 0 2006.239.07:51:28.93#ibcon#flushed, iclass 17, count 0 2006.239.07:51:28.93#ibcon#about to write, iclass 17, count 0 2006.239.07:51:28.93#ibcon#wrote, iclass 17, count 0 2006.239.07:51:28.93#ibcon#about to read 3, iclass 17, count 0 2006.239.07:51:28.95#ibcon#read 3, iclass 17, count 0 2006.239.07:51:28.95#ibcon#about to read 4, iclass 17, count 0 2006.239.07:51:28.95#ibcon#read 4, iclass 17, count 0 2006.239.07:51:28.95#ibcon#about to read 5, iclass 17, count 0 2006.239.07:51:28.95#ibcon#read 5, iclass 17, count 0 2006.239.07:51:28.95#ibcon#about to read 6, iclass 17, count 0 2006.239.07:51:28.95#ibcon#read 6, iclass 17, count 0 2006.239.07:51:28.95#ibcon#end of sib2, iclass 17, count 0 2006.239.07:51:28.95#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:51:28.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:51:28.95#ibcon#[25=USB\r\n] 2006.239.07:51:28.95#ibcon#*before write, iclass 17, count 0 2006.239.07:51:28.95#ibcon#enter sib2, iclass 17, count 0 2006.239.07:51:28.95#ibcon#flushed, iclass 17, count 0 2006.239.07:51:28.95#ibcon#about to write, iclass 17, count 0 2006.239.07:51:28.95#ibcon#wrote, iclass 17, count 0 2006.239.07:51:28.95#ibcon#about to read 3, iclass 17, count 0 2006.239.07:51:28.98#ibcon#read 3, iclass 17, count 0 2006.239.07:51:28.98#ibcon#about to read 4, iclass 17, count 0 2006.239.07:51:28.98#ibcon#read 4, iclass 17, count 0 2006.239.07:51:28.98#ibcon#about to read 5, iclass 17, count 0 2006.239.07:51:28.98#ibcon#read 5, iclass 17, count 0 2006.239.07:51:28.98#ibcon#about to read 6, iclass 17, count 0 2006.239.07:51:28.98#ibcon#read 6, iclass 17, count 0 2006.239.07:51:28.98#ibcon#end of sib2, iclass 17, count 0 2006.239.07:51:28.98#ibcon#*after write, iclass 17, count 0 2006.239.07:51:28.98#ibcon#*before return 0, iclass 17, count 0 2006.239.07:51:28.98#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:28.98#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:28.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:51:28.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:51:28.98$vc4f8/valo=4,832.99 2006.239.07:51:28.98#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.07:51:28.98#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.07:51:28.98#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:28.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:28.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:28.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:28.98#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:51:28.98#ibcon#first serial, iclass 19, count 0 2006.239.07:51:28.98#ibcon#enter sib2, iclass 19, count 0 2006.239.07:51:28.98#ibcon#flushed, iclass 19, count 0 2006.239.07:51:28.98#ibcon#about to write, iclass 19, count 0 2006.239.07:51:28.98#ibcon#wrote, iclass 19, count 0 2006.239.07:51:28.98#ibcon#about to read 3, iclass 19, count 0 2006.239.07:51:29.00#ibcon#read 3, iclass 19, count 0 2006.239.07:51:29.00#ibcon#about to read 4, iclass 19, count 0 2006.239.07:51:29.00#ibcon#read 4, iclass 19, count 0 2006.239.07:51:29.00#ibcon#about to read 5, iclass 19, count 0 2006.239.07:51:29.00#ibcon#read 5, iclass 19, count 0 2006.239.07:51:29.00#ibcon#about to read 6, iclass 19, count 0 2006.239.07:51:29.00#ibcon#read 6, iclass 19, count 0 2006.239.07:51:29.00#ibcon#end of sib2, iclass 19, count 0 2006.239.07:51:29.00#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:51:29.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:51:29.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:51:29.00#ibcon#*before write, iclass 19, count 0 2006.239.07:51:29.00#ibcon#enter sib2, iclass 19, count 0 2006.239.07:51:29.00#ibcon#flushed, iclass 19, count 0 2006.239.07:51:29.00#ibcon#about to write, iclass 19, count 0 2006.239.07:51:29.00#ibcon#wrote, iclass 19, count 0 2006.239.07:51:29.00#ibcon#about to read 3, iclass 19, count 0 2006.239.07:51:29.04#ibcon#read 3, iclass 19, count 0 2006.239.07:51:29.04#ibcon#about to read 4, iclass 19, count 0 2006.239.07:51:29.04#ibcon#read 4, iclass 19, count 0 2006.239.07:51:29.04#ibcon#about to read 5, iclass 19, count 0 2006.239.07:51:29.04#ibcon#read 5, iclass 19, count 0 2006.239.07:51:29.04#ibcon#about to read 6, iclass 19, count 0 2006.239.07:51:29.04#ibcon#read 6, iclass 19, count 0 2006.239.07:51:29.04#ibcon#end of sib2, iclass 19, count 0 2006.239.07:51:29.04#ibcon#*after write, iclass 19, count 0 2006.239.07:51:29.04#ibcon#*before return 0, iclass 19, count 0 2006.239.07:51:29.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:29.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:29.04#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:51:29.04#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:51:29.04$vc4f8/va=4,7 2006.239.07:51:29.04#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.07:51:29.04#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.07:51:29.04#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:29.04#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:29.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:29.10#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:29.10#ibcon#enter wrdev, iclass 21, count 2 2006.239.07:51:29.10#ibcon#first serial, iclass 21, count 2 2006.239.07:51:29.10#ibcon#enter sib2, iclass 21, count 2 2006.239.07:51:29.10#ibcon#flushed, iclass 21, count 2 2006.239.07:51:29.10#ibcon#about to write, iclass 21, count 2 2006.239.07:51:29.10#ibcon#wrote, iclass 21, count 2 2006.239.07:51:29.10#ibcon#about to read 3, iclass 21, count 2 2006.239.07:51:29.12#ibcon#read 3, iclass 21, count 2 2006.239.07:51:29.12#ibcon#about to read 4, iclass 21, count 2 2006.239.07:51:29.12#ibcon#read 4, iclass 21, count 2 2006.239.07:51:29.12#ibcon#about to read 5, iclass 21, count 2 2006.239.07:51:29.12#ibcon#read 5, iclass 21, count 2 2006.239.07:51:29.12#ibcon#about to read 6, iclass 21, count 2 2006.239.07:51:29.12#ibcon#read 6, iclass 21, count 2 2006.239.07:51:29.12#ibcon#end of sib2, iclass 21, count 2 2006.239.07:51:29.12#ibcon#*mode == 0, iclass 21, count 2 2006.239.07:51:29.12#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.07:51:29.12#ibcon#[25=AT04-07\r\n] 2006.239.07:51:29.12#ibcon#*before write, iclass 21, count 2 2006.239.07:51:29.12#ibcon#enter sib2, iclass 21, count 2 2006.239.07:51:29.12#ibcon#flushed, iclass 21, count 2 2006.239.07:51:29.12#ibcon#about to write, iclass 21, count 2 2006.239.07:51:29.12#ibcon#wrote, iclass 21, count 2 2006.239.07:51:29.12#ibcon#about to read 3, iclass 21, count 2 2006.239.07:51:29.15#ibcon#read 3, iclass 21, count 2 2006.239.07:51:29.15#ibcon#about to read 4, iclass 21, count 2 2006.239.07:51:29.15#ibcon#read 4, iclass 21, count 2 2006.239.07:51:29.15#ibcon#about to read 5, iclass 21, count 2 2006.239.07:51:29.15#ibcon#read 5, iclass 21, count 2 2006.239.07:51:29.15#ibcon#about to read 6, iclass 21, count 2 2006.239.07:51:29.15#ibcon#read 6, iclass 21, count 2 2006.239.07:51:29.15#ibcon#end of sib2, iclass 21, count 2 2006.239.07:51:29.15#ibcon#*after write, iclass 21, count 2 2006.239.07:51:29.15#ibcon#*before return 0, iclass 21, count 2 2006.239.07:51:29.15#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:29.15#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:29.15#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.07:51:29.15#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:29.15#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:29.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:29.27#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:29.27#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:51:29.27#ibcon#first serial, iclass 21, count 0 2006.239.07:51:29.27#ibcon#enter sib2, iclass 21, count 0 2006.239.07:51:29.27#ibcon#flushed, iclass 21, count 0 2006.239.07:51:29.27#ibcon#about to write, iclass 21, count 0 2006.239.07:51:29.27#ibcon#wrote, iclass 21, count 0 2006.239.07:51:29.27#ibcon#about to read 3, iclass 21, count 0 2006.239.07:51:29.29#ibcon#read 3, iclass 21, count 0 2006.239.07:51:29.29#ibcon#about to read 4, iclass 21, count 0 2006.239.07:51:29.29#ibcon#read 4, iclass 21, count 0 2006.239.07:51:29.29#ibcon#about to read 5, iclass 21, count 0 2006.239.07:51:29.29#ibcon#read 5, iclass 21, count 0 2006.239.07:51:29.29#ibcon#about to read 6, iclass 21, count 0 2006.239.07:51:29.29#ibcon#read 6, iclass 21, count 0 2006.239.07:51:29.29#ibcon#end of sib2, iclass 21, count 0 2006.239.07:51:29.29#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:51:29.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:51:29.29#ibcon#[25=USB\r\n] 2006.239.07:51:29.29#ibcon#*before write, iclass 21, count 0 2006.239.07:51:29.29#ibcon#enter sib2, iclass 21, count 0 2006.239.07:51:29.29#ibcon#flushed, iclass 21, count 0 2006.239.07:51:29.29#ibcon#about to write, iclass 21, count 0 2006.239.07:51:29.29#ibcon#wrote, iclass 21, count 0 2006.239.07:51:29.29#ibcon#about to read 3, iclass 21, count 0 2006.239.07:51:29.32#ibcon#read 3, iclass 21, count 0 2006.239.07:51:29.32#ibcon#about to read 4, iclass 21, count 0 2006.239.07:51:29.32#ibcon#read 4, iclass 21, count 0 2006.239.07:51:29.32#ibcon#about to read 5, iclass 21, count 0 2006.239.07:51:29.32#ibcon#read 5, iclass 21, count 0 2006.239.07:51:29.32#ibcon#about to read 6, iclass 21, count 0 2006.239.07:51:29.32#ibcon#read 6, iclass 21, count 0 2006.239.07:51:29.32#ibcon#end of sib2, iclass 21, count 0 2006.239.07:51:29.32#ibcon#*after write, iclass 21, count 0 2006.239.07:51:29.32#ibcon#*before return 0, iclass 21, count 0 2006.239.07:51:29.32#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:29.32#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:29.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:51:29.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:51:29.32$vc4f8/valo=5,652.99 2006.239.07:51:29.32#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.07:51:29.32#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.07:51:29.32#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:29.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:29.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:29.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:29.32#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:51:29.32#ibcon#first serial, iclass 23, count 0 2006.239.07:51:29.32#ibcon#enter sib2, iclass 23, count 0 2006.239.07:51:29.32#ibcon#flushed, iclass 23, count 0 2006.239.07:51:29.32#ibcon#about to write, iclass 23, count 0 2006.239.07:51:29.32#ibcon#wrote, iclass 23, count 0 2006.239.07:51:29.32#ibcon#about to read 3, iclass 23, count 0 2006.239.07:51:29.34#ibcon#read 3, iclass 23, count 0 2006.239.07:51:29.34#ibcon#about to read 4, iclass 23, count 0 2006.239.07:51:29.34#ibcon#read 4, iclass 23, count 0 2006.239.07:51:29.34#ibcon#about to read 5, iclass 23, count 0 2006.239.07:51:29.34#ibcon#read 5, iclass 23, count 0 2006.239.07:51:29.34#ibcon#about to read 6, iclass 23, count 0 2006.239.07:51:29.34#ibcon#read 6, iclass 23, count 0 2006.239.07:51:29.34#ibcon#end of sib2, iclass 23, count 0 2006.239.07:51:29.34#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:51:29.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:51:29.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:51:29.34#ibcon#*before write, iclass 23, count 0 2006.239.07:51:29.34#ibcon#enter sib2, iclass 23, count 0 2006.239.07:51:29.34#ibcon#flushed, iclass 23, count 0 2006.239.07:51:29.34#ibcon#about to write, iclass 23, count 0 2006.239.07:51:29.34#ibcon#wrote, iclass 23, count 0 2006.239.07:51:29.34#ibcon#about to read 3, iclass 23, count 0 2006.239.07:51:29.38#ibcon#read 3, iclass 23, count 0 2006.239.07:51:29.38#ibcon#about to read 4, iclass 23, count 0 2006.239.07:51:29.38#ibcon#read 4, iclass 23, count 0 2006.239.07:51:29.38#ibcon#about to read 5, iclass 23, count 0 2006.239.07:51:29.38#ibcon#read 5, iclass 23, count 0 2006.239.07:51:29.38#ibcon#about to read 6, iclass 23, count 0 2006.239.07:51:29.38#ibcon#read 6, iclass 23, count 0 2006.239.07:51:29.38#ibcon#end of sib2, iclass 23, count 0 2006.239.07:51:29.38#ibcon#*after write, iclass 23, count 0 2006.239.07:51:29.38#ibcon#*before return 0, iclass 23, count 0 2006.239.07:51:29.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:29.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:29.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:51:29.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:51:29.38$vc4f8/va=5,8 2006.239.07:51:29.38#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.07:51:29.38#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.07:51:29.38#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:29.38#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:29.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:29.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:29.44#ibcon#enter wrdev, iclass 25, count 2 2006.239.07:51:29.44#ibcon#first serial, iclass 25, count 2 2006.239.07:51:29.44#ibcon#enter sib2, iclass 25, count 2 2006.239.07:51:29.44#ibcon#flushed, iclass 25, count 2 2006.239.07:51:29.44#ibcon#about to write, iclass 25, count 2 2006.239.07:51:29.44#ibcon#wrote, iclass 25, count 2 2006.239.07:51:29.44#ibcon#about to read 3, iclass 25, count 2 2006.239.07:51:29.46#ibcon#read 3, iclass 25, count 2 2006.239.07:51:29.46#ibcon#about to read 4, iclass 25, count 2 2006.239.07:51:29.46#ibcon#read 4, iclass 25, count 2 2006.239.07:51:29.46#ibcon#about to read 5, iclass 25, count 2 2006.239.07:51:29.46#ibcon#read 5, iclass 25, count 2 2006.239.07:51:29.46#ibcon#about to read 6, iclass 25, count 2 2006.239.07:51:29.46#ibcon#read 6, iclass 25, count 2 2006.239.07:51:29.46#ibcon#end of sib2, iclass 25, count 2 2006.239.07:51:29.46#ibcon#*mode == 0, iclass 25, count 2 2006.239.07:51:29.46#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.07:51:29.46#ibcon#[25=AT05-08\r\n] 2006.239.07:51:29.46#ibcon#*before write, iclass 25, count 2 2006.239.07:51:29.46#ibcon#enter sib2, iclass 25, count 2 2006.239.07:51:29.46#ibcon#flushed, iclass 25, count 2 2006.239.07:51:29.46#ibcon#about to write, iclass 25, count 2 2006.239.07:51:29.46#ibcon#wrote, iclass 25, count 2 2006.239.07:51:29.46#ibcon#about to read 3, iclass 25, count 2 2006.239.07:51:29.49#ibcon#read 3, iclass 25, count 2 2006.239.07:51:29.49#ibcon#about to read 4, iclass 25, count 2 2006.239.07:51:29.49#ibcon#read 4, iclass 25, count 2 2006.239.07:51:29.49#ibcon#about to read 5, iclass 25, count 2 2006.239.07:51:29.49#ibcon#read 5, iclass 25, count 2 2006.239.07:51:29.49#ibcon#about to read 6, iclass 25, count 2 2006.239.07:51:29.49#ibcon#read 6, iclass 25, count 2 2006.239.07:51:29.49#ibcon#end of sib2, iclass 25, count 2 2006.239.07:51:29.49#ibcon#*after write, iclass 25, count 2 2006.239.07:51:29.49#ibcon#*before return 0, iclass 25, count 2 2006.239.07:51:29.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:29.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:29.49#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.07:51:29.49#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:29.49#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:29.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:29.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:29.62#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:51:29.62#ibcon#first serial, iclass 25, count 0 2006.239.07:51:29.62#ibcon#enter sib2, iclass 25, count 0 2006.239.07:51:29.62#ibcon#flushed, iclass 25, count 0 2006.239.07:51:29.62#ibcon#about to write, iclass 25, count 0 2006.239.07:51:29.62#ibcon#wrote, iclass 25, count 0 2006.239.07:51:29.62#ibcon#about to read 3, iclass 25, count 0 2006.239.07:51:29.63#ibcon#read 3, iclass 25, count 0 2006.239.07:51:29.63#ibcon#about to read 4, iclass 25, count 0 2006.239.07:51:29.63#ibcon#read 4, iclass 25, count 0 2006.239.07:51:29.63#ibcon#about to read 5, iclass 25, count 0 2006.239.07:51:29.63#ibcon#read 5, iclass 25, count 0 2006.239.07:51:29.63#ibcon#about to read 6, iclass 25, count 0 2006.239.07:51:29.63#ibcon#read 6, iclass 25, count 0 2006.239.07:51:29.63#ibcon#end of sib2, iclass 25, count 0 2006.239.07:51:29.63#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:51:29.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:51:29.63#ibcon#[25=USB\r\n] 2006.239.07:51:29.63#ibcon#*before write, iclass 25, count 0 2006.239.07:51:29.63#ibcon#enter sib2, iclass 25, count 0 2006.239.07:51:29.63#ibcon#flushed, iclass 25, count 0 2006.239.07:51:29.63#ibcon#about to write, iclass 25, count 0 2006.239.07:51:29.63#ibcon#wrote, iclass 25, count 0 2006.239.07:51:29.63#ibcon#about to read 3, iclass 25, count 0 2006.239.07:51:29.66#ibcon#read 3, iclass 25, count 0 2006.239.07:51:29.66#ibcon#about to read 4, iclass 25, count 0 2006.239.07:51:29.66#ibcon#read 4, iclass 25, count 0 2006.239.07:51:29.66#ibcon#about to read 5, iclass 25, count 0 2006.239.07:51:29.66#ibcon#read 5, iclass 25, count 0 2006.239.07:51:29.66#ibcon#about to read 6, iclass 25, count 0 2006.239.07:51:29.66#ibcon#read 6, iclass 25, count 0 2006.239.07:51:29.66#ibcon#end of sib2, iclass 25, count 0 2006.239.07:51:29.66#ibcon#*after write, iclass 25, count 0 2006.239.07:51:29.66#ibcon#*before return 0, iclass 25, count 0 2006.239.07:51:29.66#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:29.66#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:29.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:51:29.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:51:29.66$vc4f8/valo=6,772.99 2006.239.07:51:29.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.07:51:29.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.07:51:29.66#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:29.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:29.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:29.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:29.66#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:51:29.66#ibcon#first serial, iclass 27, count 0 2006.239.07:51:29.66#ibcon#enter sib2, iclass 27, count 0 2006.239.07:51:29.66#ibcon#flushed, iclass 27, count 0 2006.239.07:51:29.66#ibcon#about to write, iclass 27, count 0 2006.239.07:51:29.66#ibcon#wrote, iclass 27, count 0 2006.239.07:51:29.66#ibcon#about to read 3, iclass 27, count 0 2006.239.07:51:29.68#ibcon#read 3, iclass 27, count 0 2006.239.07:51:29.68#ibcon#about to read 4, iclass 27, count 0 2006.239.07:51:29.68#ibcon#read 4, iclass 27, count 0 2006.239.07:51:29.68#ibcon#about to read 5, iclass 27, count 0 2006.239.07:51:29.68#ibcon#read 5, iclass 27, count 0 2006.239.07:51:29.68#ibcon#about to read 6, iclass 27, count 0 2006.239.07:51:29.68#ibcon#read 6, iclass 27, count 0 2006.239.07:51:29.68#ibcon#end of sib2, iclass 27, count 0 2006.239.07:51:29.68#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:51:29.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:51:29.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:51:29.68#ibcon#*before write, iclass 27, count 0 2006.239.07:51:29.68#ibcon#enter sib2, iclass 27, count 0 2006.239.07:51:29.68#ibcon#flushed, iclass 27, count 0 2006.239.07:51:29.68#ibcon#about to write, iclass 27, count 0 2006.239.07:51:29.68#ibcon#wrote, iclass 27, count 0 2006.239.07:51:29.68#ibcon#about to read 3, iclass 27, count 0 2006.239.07:51:29.72#ibcon#read 3, iclass 27, count 0 2006.239.07:51:29.72#ibcon#about to read 4, iclass 27, count 0 2006.239.07:51:29.72#ibcon#read 4, iclass 27, count 0 2006.239.07:51:29.72#ibcon#about to read 5, iclass 27, count 0 2006.239.07:51:29.72#ibcon#read 5, iclass 27, count 0 2006.239.07:51:29.72#ibcon#about to read 6, iclass 27, count 0 2006.239.07:51:29.72#ibcon#read 6, iclass 27, count 0 2006.239.07:51:29.72#ibcon#end of sib2, iclass 27, count 0 2006.239.07:51:29.72#ibcon#*after write, iclass 27, count 0 2006.239.07:51:29.72#ibcon#*before return 0, iclass 27, count 0 2006.239.07:51:29.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:29.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:29.72#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:51:29.72#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:51:29.72$vc4f8/va=6,7 2006.239.07:51:29.72#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.07:51:29.72#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.07:51:29.72#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:29.72#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:51:29.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:51:29.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:51:29.78#ibcon#enter wrdev, iclass 29, count 2 2006.239.07:51:29.78#ibcon#first serial, iclass 29, count 2 2006.239.07:51:29.78#ibcon#enter sib2, iclass 29, count 2 2006.239.07:51:29.78#ibcon#flushed, iclass 29, count 2 2006.239.07:51:29.78#ibcon#about to write, iclass 29, count 2 2006.239.07:51:29.78#ibcon#wrote, iclass 29, count 2 2006.239.07:51:29.78#ibcon#about to read 3, iclass 29, count 2 2006.239.07:51:29.80#ibcon#read 3, iclass 29, count 2 2006.239.07:51:29.80#ibcon#about to read 4, iclass 29, count 2 2006.239.07:51:29.80#ibcon#read 4, iclass 29, count 2 2006.239.07:51:29.80#ibcon#about to read 5, iclass 29, count 2 2006.239.07:51:29.80#ibcon#read 5, iclass 29, count 2 2006.239.07:51:29.80#ibcon#about to read 6, iclass 29, count 2 2006.239.07:51:29.80#ibcon#read 6, iclass 29, count 2 2006.239.07:51:29.80#ibcon#end of sib2, iclass 29, count 2 2006.239.07:51:29.80#ibcon#*mode == 0, iclass 29, count 2 2006.239.07:51:29.80#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.07:51:29.80#ibcon#[25=AT06-07\r\n] 2006.239.07:51:29.80#ibcon#*before write, iclass 29, count 2 2006.239.07:51:29.80#ibcon#enter sib2, iclass 29, count 2 2006.239.07:51:29.80#ibcon#flushed, iclass 29, count 2 2006.239.07:51:29.80#ibcon#about to write, iclass 29, count 2 2006.239.07:51:29.80#ibcon#wrote, iclass 29, count 2 2006.239.07:51:29.80#ibcon#about to read 3, iclass 29, count 2 2006.239.07:51:29.83#ibcon#read 3, iclass 29, count 2 2006.239.07:51:29.83#ibcon#about to read 4, iclass 29, count 2 2006.239.07:51:29.83#ibcon#read 4, iclass 29, count 2 2006.239.07:51:29.83#ibcon#about to read 5, iclass 29, count 2 2006.239.07:51:29.83#ibcon#read 5, iclass 29, count 2 2006.239.07:51:29.83#ibcon#about to read 6, iclass 29, count 2 2006.239.07:51:29.83#ibcon#read 6, iclass 29, count 2 2006.239.07:51:29.83#ibcon#end of sib2, iclass 29, count 2 2006.239.07:51:29.83#ibcon#*after write, iclass 29, count 2 2006.239.07:51:29.83#ibcon#*before return 0, iclass 29, count 2 2006.239.07:51:29.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:51:29.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.07:51:29.83#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.07:51:29.83#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:29.83#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:51:29.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:51:29.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:51:29.95#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:51:29.95#ibcon#first serial, iclass 29, count 0 2006.239.07:51:29.95#ibcon#enter sib2, iclass 29, count 0 2006.239.07:51:29.95#ibcon#flushed, iclass 29, count 0 2006.239.07:51:29.95#ibcon#about to write, iclass 29, count 0 2006.239.07:51:29.95#ibcon#wrote, iclass 29, count 0 2006.239.07:51:29.95#ibcon#about to read 3, iclass 29, count 0 2006.239.07:51:29.97#ibcon#read 3, iclass 29, count 0 2006.239.07:51:29.97#ibcon#about to read 4, iclass 29, count 0 2006.239.07:51:29.97#ibcon#read 4, iclass 29, count 0 2006.239.07:51:29.97#ibcon#about to read 5, iclass 29, count 0 2006.239.07:51:29.97#ibcon#read 5, iclass 29, count 0 2006.239.07:51:29.97#ibcon#about to read 6, iclass 29, count 0 2006.239.07:51:29.97#ibcon#read 6, iclass 29, count 0 2006.239.07:51:29.97#ibcon#end of sib2, iclass 29, count 0 2006.239.07:51:29.97#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:51:29.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:51:29.97#ibcon#[25=USB\r\n] 2006.239.07:51:29.97#ibcon#*before write, iclass 29, count 0 2006.239.07:51:29.97#ibcon#enter sib2, iclass 29, count 0 2006.239.07:51:29.97#ibcon#flushed, iclass 29, count 0 2006.239.07:51:29.97#ibcon#about to write, iclass 29, count 0 2006.239.07:51:29.97#ibcon#wrote, iclass 29, count 0 2006.239.07:51:29.97#ibcon#about to read 3, iclass 29, count 0 2006.239.07:51:30.00#ibcon#read 3, iclass 29, count 0 2006.239.07:51:30.00#ibcon#about to read 4, iclass 29, count 0 2006.239.07:51:30.00#ibcon#read 4, iclass 29, count 0 2006.239.07:51:30.00#ibcon#about to read 5, iclass 29, count 0 2006.239.07:51:30.00#ibcon#read 5, iclass 29, count 0 2006.239.07:51:30.00#ibcon#about to read 6, iclass 29, count 0 2006.239.07:51:30.00#ibcon#read 6, iclass 29, count 0 2006.239.07:51:30.00#ibcon#end of sib2, iclass 29, count 0 2006.239.07:51:30.00#ibcon#*after write, iclass 29, count 0 2006.239.07:51:30.00#ibcon#*before return 0, iclass 29, count 0 2006.239.07:51:30.00#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:51:30.00#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.07:51:30.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:51:30.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:51:30.00$vc4f8/valo=7,832.99 2006.239.07:51:30.00#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.07:51:30.00#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.07:51:30.00#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:30.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:51:30.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:51:30.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:51:30.00#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:51:30.00#ibcon#first serial, iclass 31, count 0 2006.239.07:51:30.00#ibcon#enter sib2, iclass 31, count 0 2006.239.07:51:30.00#ibcon#flushed, iclass 31, count 0 2006.239.07:51:30.00#ibcon#about to write, iclass 31, count 0 2006.239.07:51:30.00#ibcon#wrote, iclass 31, count 0 2006.239.07:51:30.00#ibcon#about to read 3, iclass 31, count 0 2006.239.07:51:30.02#ibcon#read 3, iclass 31, count 0 2006.239.07:51:30.02#ibcon#about to read 4, iclass 31, count 0 2006.239.07:51:30.02#ibcon#read 4, iclass 31, count 0 2006.239.07:51:30.02#ibcon#about to read 5, iclass 31, count 0 2006.239.07:51:30.02#ibcon#read 5, iclass 31, count 0 2006.239.07:51:30.02#ibcon#about to read 6, iclass 31, count 0 2006.239.07:51:30.02#ibcon#read 6, iclass 31, count 0 2006.239.07:51:30.02#ibcon#end of sib2, iclass 31, count 0 2006.239.07:51:30.02#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:51:30.02#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:51:30.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:51:30.02#ibcon#*before write, iclass 31, count 0 2006.239.07:51:30.02#ibcon#enter sib2, iclass 31, count 0 2006.239.07:51:30.02#ibcon#flushed, iclass 31, count 0 2006.239.07:51:30.02#ibcon#about to write, iclass 31, count 0 2006.239.07:51:30.02#ibcon#wrote, iclass 31, count 0 2006.239.07:51:30.02#ibcon#about to read 3, iclass 31, count 0 2006.239.07:51:30.06#ibcon#read 3, iclass 31, count 0 2006.239.07:51:30.06#ibcon#about to read 4, iclass 31, count 0 2006.239.07:51:30.06#ibcon#read 4, iclass 31, count 0 2006.239.07:51:30.06#ibcon#about to read 5, iclass 31, count 0 2006.239.07:51:30.06#ibcon#read 5, iclass 31, count 0 2006.239.07:51:30.06#ibcon#about to read 6, iclass 31, count 0 2006.239.07:51:30.06#ibcon#read 6, iclass 31, count 0 2006.239.07:51:30.06#ibcon#end of sib2, iclass 31, count 0 2006.239.07:51:30.06#ibcon#*after write, iclass 31, count 0 2006.239.07:51:30.06#ibcon#*before return 0, iclass 31, count 0 2006.239.07:51:30.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:51:30.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.07:51:30.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:51:30.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:51:30.06$vc4f8/va=7,7 2006.239.07:51:30.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.07:51:30.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.07:51:30.06#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:30.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:51:30.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:51:30.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:51:30.12#ibcon#enter wrdev, iclass 33, count 2 2006.239.07:51:30.12#ibcon#first serial, iclass 33, count 2 2006.239.07:51:30.12#ibcon#enter sib2, iclass 33, count 2 2006.239.07:51:30.12#ibcon#flushed, iclass 33, count 2 2006.239.07:51:30.12#ibcon#about to write, iclass 33, count 2 2006.239.07:51:30.12#ibcon#wrote, iclass 33, count 2 2006.239.07:51:30.12#ibcon#about to read 3, iclass 33, count 2 2006.239.07:51:30.14#ibcon#read 3, iclass 33, count 2 2006.239.07:51:30.14#ibcon#about to read 4, iclass 33, count 2 2006.239.07:51:30.14#ibcon#read 4, iclass 33, count 2 2006.239.07:51:30.14#ibcon#about to read 5, iclass 33, count 2 2006.239.07:51:30.14#ibcon#read 5, iclass 33, count 2 2006.239.07:51:30.14#ibcon#about to read 6, iclass 33, count 2 2006.239.07:51:30.14#ibcon#read 6, iclass 33, count 2 2006.239.07:51:30.14#ibcon#end of sib2, iclass 33, count 2 2006.239.07:51:30.14#ibcon#*mode == 0, iclass 33, count 2 2006.239.07:51:30.14#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.07:51:30.14#ibcon#[25=AT07-07\r\n] 2006.239.07:51:30.14#ibcon#*before write, iclass 33, count 2 2006.239.07:51:30.14#ibcon#enter sib2, iclass 33, count 2 2006.239.07:51:30.14#ibcon#flushed, iclass 33, count 2 2006.239.07:51:30.14#ibcon#about to write, iclass 33, count 2 2006.239.07:51:30.14#ibcon#wrote, iclass 33, count 2 2006.239.07:51:30.14#ibcon#about to read 3, iclass 33, count 2 2006.239.07:51:30.18#ibcon#read 3, iclass 33, count 2 2006.239.07:51:30.18#ibcon#about to read 4, iclass 33, count 2 2006.239.07:51:30.18#ibcon#read 4, iclass 33, count 2 2006.239.07:51:30.18#ibcon#about to read 5, iclass 33, count 2 2006.239.07:51:30.18#ibcon#read 5, iclass 33, count 2 2006.239.07:51:30.18#ibcon#about to read 6, iclass 33, count 2 2006.239.07:51:30.18#ibcon#read 6, iclass 33, count 2 2006.239.07:51:30.18#ibcon#end of sib2, iclass 33, count 2 2006.239.07:51:30.18#ibcon#*after write, iclass 33, count 2 2006.239.07:51:30.18#ibcon#*before return 0, iclass 33, count 2 2006.239.07:51:30.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:51:30.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.07:51:30.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.07:51:30.18#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:30.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:51:30.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:51:30.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:51:30.30#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:51:30.30#ibcon#first serial, iclass 33, count 0 2006.239.07:51:30.30#ibcon#enter sib2, iclass 33, count 0 2006.239.07:51:30.30#ibcon#flushed, iclass 33, count 0 2006.239.07:51:30.30#ibcon#about to write, iclass 33, count 0 2006.239.07:51:30.30#ibcon#wrote, iclass 33, count 0 2006.239.07:51:30.30#ibcon#about to read 3, iclass 33, count 0 2006.239.07:51:30.32#ibcon#read 3, iclass 33, count 0 2006.239.07:51:30.32#ibcon#about to read 4, iclass 33, count 0 2006.239.07:51:30.32#ibcon#read 4, iclass 33, count 0 2006.239.07:51:30.32#ibcon#about to read 5, iclass 33, count 0 2006.239.07:51:30.32#ibcon#read 5, iclass 33, count 0 2006.239.07:51:30.32#ibcon#about to read 6, iclass 33, count 0 2006.239.07:51:30.32#ibcon#read 6, iclass 33, count 0 2006.239.07:51:30.32#ibcon#end of sib2, iclass 33, count 0 2006.239.07:51:30.32#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:51:30.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:51:30.32#ibcon#[25=USB\r\n] 2006.239.07:51:30.32#ibcon#*before write, iclass 33, count 0 2006.239.07:51:30.32#ibcon#enter sib2, iclass 33, count 0 2006.239.07:51:30.32#ibcon#flushed, iclass 33, count 0 2006.239.07:51:30.32#ibcon#about to write, iclass 33, count 0 2006.239.07:51:30.32#ibcon#wrote, iclass 33, count 0 2006.239.07:51:30.32#ibcon#about to read 3, iclass 33, count 0 2006.239.07:51:30.35#ibcon#read 3, iclass 33, count 0 2006.239.07:51:30.35#ibcon#about to read 4, iclass 33, count 0 2006.239.07:51:30.35#ibcon#read 4, iclass 33, count 0 2006.239.07:51:30.35#ibcon#about to read 5, iclass 33, count 0 2006.239.07:51:30.35#ibcon#read 5, iclass 33, count 0 2006.239.07:51:30.35#ibcon#about to read 6, iclass 33, count 0 2006.239.07:51:30.35#ibcon#read 6, iclass 33, count 0 2006.239.07:51:30.35#ibcon#end of sib2, iclass 33, count 0 2006.239.07:51:30.35#ibcon#*after write, iclass 33, count 0 2006.239.07:51:30.35#ibcon#*before return 0, iclass 33, count 0 2006.239.07:51:30.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:51:30.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.07:51:30.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:51:30.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:51:30.35$vc4f8/valo=8,852.99 2006.239.07:51:30.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.07:51:30.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.07:51:30.35#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:30.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:51:30.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:51:30.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:51:30.35#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:51:30.35#ibcon#first serial, iclass 35, count 0 2006.239.07:51:30.35#ibcon#enter sib2, iclass 35, count 0 2006.239.07:51:30.35#ibcon#flushed, iclass 35, count 0 2006.239.07:51:30.35#ibcon#about to write, iclass 35, count 0 2006.239.07:51:30.35#ibcon#wrote, iclass 35, count 0 2006.239.07:51:30.35#ibcon#about to read 3, iclass 35, count 0 2006.239.07:51:30.37#ibcon#read 3, iclass 35, count 0 2006.239.07:51:30.37#ibcon#about to read 4, iclass 35, count 0 2006.239.07:51:30.37#ibcon#read 4, iclass 35, count 0 2006.239.07:51:30.37#ibcon#about to read 5, iclass 35, count 0 2006.239.07:51:30.37#ibcon#read 5, iclass 35, count 0 2006.239.07:51:30.37#ibcon#about to read 6, iclass 35, count 0 2006.239.07:51:30.37#ibcon#read 6, iclass 35, count 0 2006.239.07:51:30.37#ibcon#end of sib2, iclass 35, count 0 2006.239.07:51:30.37#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:51:30.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:51:30.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:51:30.37#ibcon#*before write, iclass 35, count 0 2006.239.07:51:30.37#ibcon#enter sib2, iclass 35, count 0 2006.239.07:51:30.37#ibcon#flushed, iclass 35, count 0 2006.239.07:51:30.37#ibcon#about to write, iclass 35, count 0 2006.239.07:51:30.37#ibcon#wrote, iclass 35, count 0 2006.239.07:51:30.37#ibcon#about to read 3, iclass 35, count 0 2006.239.07:51:30.41#ibcon#read 3, iclass 35, count 0 2006.239.07:51:30.41#ibcon#about to read 4, iclass 35, count 0 2006.239.07:51:30.41#ibcon#read 4, iclass 35, count 0 2006.239.07:51:30.41#ibcon#about to read 5, iclass 35, count 0 2006.239.07:51:30.41#ibcon#read 5, iclass 35, count 0 2006.239.07:51:30.41#ibcon#about to read 6, iclass 35, count 0 2006.239.07:51:30.41#ibcon#read 6, iclass 35, count 0 2006.239.07:51:30.41#ibcon#end of sib2, iclass 35, count 0 2006.239.07:51:30.41#ibcon#*after write, iclass 35, count 0 2006.239.07:51:30.41#ibcon#*before return 0, iclass 35, count 0 2006.239.07:51:30.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:51:30.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.07:51:30.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:51:30.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:51:30.41$vc4f8/va=8,7 2006.239.07:51:30.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.07:51:30.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.07:51:30.41#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:30.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:51:30.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:51:30.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:51:30.47#ibcon#enter wrdev, iclass 37, count 2 2006.239.07:51:30.47#ibcon#first serial, iclass 37, count 2 2006.239.07:51:30.47#ibcon#enter sib2, iclass 37, count 2 2006.239.07:51:30.47#ibcon#flushed, iclass 37, count 2 2006.239.07:51:30.47#ibcon#about to write, iclass 37, count 2 2006.239.07:51:30.47#ibcon#wrote, iclass 37, count 2 2006.239.07:51:30.47#ibcon#about to read 3, iclass 37, count 2 2006.239.07:51:30.49#ibcon#read 3, iclass 37, count 2 2006.239.07:51:30.49#ibcon#about to read 4, iclass 37, count 2 2006.239.07:51:30.49#ibcon#read 4, iclass 37, count 2 2006.239.07:51:30.49#ibcon#about to read 5, iclass 37, count 2 2006.239.07:51:30.49#ibcon#read 5, iclass 37, count 2 2006.239.07:51:30.49#ibcon#about to read 6, iclass 37, count 2 2006.239.07:51:30.49#ibcon#read 6, iclass 37, count 2 2006.239.07:51:30.49#ibcon#end of sib2, iclass 37, count 2 2006.239.07:51:30.49#ibcon#*mode == 0, iclass 37, count 2 2006.239.07:51:30.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.07:51:30.49#ibcon#[25=AT08-07\r\n] 2006.239.07:51:30.49#ibcon#*before write, iclass 37, count 2 2006.239.07:51:30.49#ibcon#enter sib2, iclass 37, count 2 2006.239.07:51:30.49#ibcon#flushed, iclass 37, count 2 2006.239.07:51:30.49#ibcon#about to write, iclass 37, count 2 2006.239.07:51:30.49#ibcon#wrote, iclass 37, count 2 2006.239.07:51:30.49#ibcon#about to read 3, iclass 37, count 2 2006.239.07:51:30.52#ibcon#read 3, iclass 37, count 2 2006.239.07:51:30.52#ibcon#about to read 4, iclass 37, count 2 2006.239.07:51:30.52#ibcon#read 4, iclass 37, count 2 2006.239.07:51:30.52#ibcon#about to read 5, iclass 37, count 2 2006.239.07:51:30.52#ibcon#read 5, iclass 37, count 2 2006.239.07:51:30.52#ibcon#about to read 6, iclass 37, count 2 2006.239.07:51:30.52#ibcon#read 6, iclass 37, count 2 2006.239.07:51:30.52#ibcon#end of sib2, iclass 37, count 2 2006.239.07:51:30.52#ibcon#*after write, iclass 37, count 2 2006.239.07:51:30.52#ibcon#*before return 0, iclass 37, count 2 2006.239.07:51:30.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:51:30.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.07:51:30.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.07:51:30.52#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:30.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:51:30.64#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:51:30.64#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:51:30.64#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:51:30.64#ibcon#first serial, iclass 37, count 0 2006.239.07:51:30.64#ibcon#enter sib2, iclass 37, count 0 2006.239.07:51:30.64#ibcon#flushed, iclass 37, count 0 2006.239.07:51:30.64#ibcon#about to write, iclass 37, count 0 2006.239.07:51:30.64#ibcon#wrote, iclass 37, count 0 2006.239.07:51:30.64#ibcon#about to read 3, iclass 37, count 0 2006.239.07:51:30.66#ibcon#read 3, iclass 37, count 0 2006.239.07:51:30.66#ibcon#about to read 4, iclass 37, count 0 2006.239.07:51:30.66#ibcon#read 4, iclass 37, count 0 2006.239.07:51:30.66#ibcon#about to read 5, iclass 37, count 0 2006.239.07:51:30.66#ibcon#read 5, iclass 37, count 0 2006.239.07:51:30.66#ibcon#about to read 6, iclass 37, count 0 2006.239.07:51:30.66#ibcon#read 6, iclass 37, count 0 2006.239.07:51:30.66#ibcon#end of sib2, iclass 37, count 0 2006.239.07:51:30.66#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:51:30.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:51:30.66#ibcon#[25=USB\r\n] 2006.239.07:51:30.66#ibcon#*before write, iclass 37, count 0 2006.239.07:51:30.66#ibcon#enter sib2, iclass 37, count 0 2006.239.07:51:30.66#ibcon#flushed, iclass 37, count 0 2006.239.07:51:30.66#ibcon#about to write, iclass 37, count 0 2006.239.07:51:30.66#ibcon#wrote, iclass 37, count 0 2006.239.07:51:30.66#ibcon#about to read 3, iclass 37, count 0 2006.239.07:51:30.69#ibcon#read 3, iclass 37, count 0 2006.239.07:51:30.69#ibcon#about to read 4, iclass 37, count 0 2006.239.07:51:30.69#ibcon#read 4, iclass 37, count 0 2006.239.07:51:30.69#ibcon#about to read 5, iclass 37, count 0 2006.239.07:51:30.69#ibcon#read 5, iclass 37, count 0 2006.239.07:51:30.69#ibcon#about to read 6, iclass 37, count 0 2006.239.07:51:30.69#ibcon#read 6, iclass 37, count 0 2006.239.07:51:30.69#ibcon#end of sib2, iclass 37, count 0 2006.239.07:51:30.69#ibcon#*after write, iclass 37, count 0 2006.239.07:51:30.69#ibcon#*before return 0, iclass 37, count 0 2006.239.07:51:30.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:51:30.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.07:51:30.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:51:30.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:51:30.69$vc4f8/vblo=1,632.99 2006.239.07:51:30.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.07:51:30.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.07:51:30.69#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:30.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:51:30.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:51:30.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:51:30.69#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:51:30.69#ibcon#first serial, iclass 39, count 0 2006.239.07:51:30.69#ibcon#enter sib2, iclass 39, count 0 2006.239.07:51:30.69#ibcon#flushed, iclass 39, count 0 2006.239.07:51:30.69#ibcon#about to write, iclass 39, count 0 2006.239.07:51:30.69#ibcon#wrote, iclass 39, count 0 2006.239.07:51:30.69#ibcon#about to read 3, iclass 39, count 0 2006.239.07:51:30.71#ibcon#read 3, iclass 39, count 0 2006.239.07:51:30.71#ibcon#about to read 4, iclass 39, count 0 2006.239.07:51:30.71#ibcon#read 4, iclass 39, count 0 2006.239.07:51:30.71#ibcon#about to read 5, iclass 39, count 0 2006.239.07:51:30.71#ibcon#read 5, iclass 39, count 0 2006.239.07:51:30.71#ibcon#about to read 6, iclass 39, count 0 2006.239.07:51:30.71#ibcon#read 6, iclass 39, count 0 2006.239.07:51:30.71#ibcon#end of sib2, iclass 39, count 0 2006.239.07:51:30.71#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:51:30.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:51:30.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:51:30.71#ibcon#*before write, iclass 39, count 0 2006.239.07:51:30.71#ibcon#enter sib2, iclass 39, count 0 2006.239.07:51:30.71#ibcon#flushed, iclass 39, count 0 2006.239.07:51:30.71#ibcon#about to write, iclass 39, count 0 2006.239.07:51:30.71#ibcon#wrote, iclass 39, count 0 2006.239.07:51:30.71#ibcon#about to read 3, iclass 39, count 0 2006.239.07:51:30.75#ibcon#read 3, iclass 39, count 0 2006.239.07:51:30.75#ibcon#about to read 4, iclass 39, count 0 2006.239.07:51:30.75#ibcon#read 4, iclass 39, count 0 2006.239.07:51:30.75#ibcon#about to read 5, iclass 39, count 0 2006.239.07:51:30.75#ibcon#read 5, iclass 39, count 0 2006.239.07:51:30.75#ibcon#about to read 6, iclass 39, count 0 2006.239.07:51:30.75#ibcon#read 6, iclass 39, count 0 2006.239.07:51:30.75#ibcon#end of sib2, iclass 39, count 0 2006.239.07:51:30.75#ibcon#*after write, iclass 39, count 0 2006.239.07:51:30.75#ibcon#*before return 0, iclass 39, count 0 2006.239.07:51:30.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:51:30.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.07:51:30.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:51:30.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:51:30.75$vc4f8/vb=1,4 2006.239.07:51:30.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.07:51:30.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.07:51:30.75#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:30.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:51:30.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:51:30.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:51:30.75#ibcon#enter wrdev, iclass 3, count 2 2006.239.07:51:30.75#ibcon#first serial, iclass 3, count 2 2006.239.07:51:30.75#ibcon#enter sib2, iclass 3, count 2 2006.239.07:51:30.75#ibcon#flushed, iclass 3, count 2 2006.239.07:51:30.75#ibcon#about to write, iclass 3, count 2 2006.239.07:51:30.75#ibcon#wrote, iclass 3, count 2 2006.239.07:51:30.75#ibcon#about to read 3, iclass 3, count 2 2006.239.07:51:30.77#ibcon#read 3, iclass 3, count 2 2006.239.07:51:30.77#ibcon#about to read 4, iclass 3, count 2 2006.239.07:51:30.77#ibcon#read 4, iclass 3, count 2 2006.239.07:51:30.77#ibcon#about to read 5, iclass 3, count 2 2006.239.07:51:30.77#ibcon#read 5, iclass 3, count 2 2006.239.07:51:30.77#ibcon#about to read 6, iclass 3, count 2 2006.239.07:51:30.77#ibcon#read 6, iclass 3, count 2 2006.239.07:51:30.77#ibcon#end of sib2, iclass 3, count 2 2006.239.07:51:30.77#ibcon#*mode == 0, iclass 3, count 2 2006.239.07:51:30.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.07:51:30.77#ibcon#[27=AT01-04\r\n] 2006.239.07:51:30.77#ibcon#*before write, iclass 3, count 2 2006.239.07:51:30.77#ibcon#enter sib2, iclass 3, count 2 2006.239.07:51:30.77#ibcon#flushed, iclass 3, count 2 2006.239.07:51:30.77#ibcon#about to write, iclass 3, count 2 2006.239.07:51:30.77#ibcon#wrote, iclass 3, count 2 2006.239.07:51:30.77#ibcon#about to read 3, iclass 3, count 2 2006.239.07:51:30.80#ibcon#read 3, iclass 3, count 2 2006.239.07:51:30.80#ibcon#about to read 4, iclass 3, count 2 2006.239.07:51:30.80#ibcon#read 4, iclass 3, count 2 2006.239.07:51:30.80#ibcon#about to read 5, iclass 3, count 2 2006.239.07:51:30.80#ibcon#read 5, iclass 3, count 2 2006.239.07:51:30.80#ibcon#about to read 6, iclass 3, count 2 2006.239.07:51:30.80#ibcon#read 6, iclass 3, count 2 2006.239.07:51:30.80#ibcon#end of sib2, iclass 3, count 2 2006.239.07:51:30.80#ibcon#*after write, iclass 3, count 2 2006.239.07:51:30.80#ibcon#*before return 0, iclass 3, count 2 2006.239.07:51:30.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:51:30.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.07:51:30.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.07:51:30.80#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:30.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:51:30.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:51:30.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:51:30.92#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:51:30.92#ibcon#first serial, iclass 3, count 0 2006.239.07:51:30.92#ibcon#enter sib2, iclass 3, count 0 2006.239.07:51:30.92#ibcon#flushed, iclass 3, count 0 2006.239.07:51:30.92#ibcon#about to write, iclass 3, count 0 2006.239.07:51:30.92#ibcon#wrote, iclass 3, count 0 2006.239.07:51:30.92#ibcon#about to read 3, iclass 3, count 0 2006.239.07:51:30.94#ibcon#read 3, iclass 3, count 0 2006.239.07:51:30.94#ibcon#about to read 4, iclass 3, count 0 2006.239.07:51:30.94#ibcon#read 4, iclass 3, count 0 2006.239.07:51:30.94#ibcon#about to read 5, iclass 3, count 0 2006.239.07:51:30.94#ibcon#read 5, iclass 3, count 0 2006.239.07:51:30.94#ibcon#about to read 6, iclass 3, count 0 2006.239.07:51:30.94#ibcon#read 6, iclass 3, count 0 2006.239.07:51:30.94#ibcon#end of sib2, iclass 3, count 0 2006.239.07:51:30.94#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:51:30.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:51:30.94#ibcon#[27=USB\r\n] 2006.239.07:51:30.94#ibcon#*before write, iclass 3, count 0 2006.239.07:51:30.94#ibcon#enter sib2, iclass 3, count 0 2006.239.07:51:30.94#ibcon#flushed, iclass 3, count 0 2006.239.07:51:30.94#ibcon#about to write, iclass 3, count 0 2006.239.07:51:30.94#ibcon#wrote, iclass 3, count 0 2006.239.07:51:30.94#ibcon#about to read 3, iclass 3, count 0 2006.239.07:51:30.97#ibcon#read 3, iclass 3, count 0 2006.239.07:51:30.97#ibcon#about to read 4, iclass 3, count 0 2006.239.07:51:30.97#ibcon#read 4, iclass 3, count 0 2006.239.07:51:30.97#ibcon#about to read 5, iclass 3, count 0 2006.239.07:51:30.97#ibcon#read 5, iclass 3, count 0 2006.239.07:51:30.97#ibcon#about to read 6, iclass 3, count 0 2006.239.07:51:30.97#ibcon#read 6, iclass 3, count 0 2006.239.07:51:30.97#ibcon#end of sib2, iclass 3, count 0 2006.239.07:51:30.97#ibcon#*after write, iclass 3, count 0 2006.239.07:51:30.97#ibcon#*before return 0, iclass 3, count 0 2006.239.07:51:30.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:51:30.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.07:51:30.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:51:30.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:51:30.97$vc4f8/vblo=2,640.99 2006.239.07:51:30.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.07:51:30.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.07:51:30.97#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:30.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:30.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:30.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:30.97#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:51:30.97#ibcon#first serial, iclass 5, count 0 2006.239.07:51:30.97#ibcon#enter sib2, iclass 5, count 0 2006.239.07:51:30.97#ibcon#flushed, iclass 5, count 0 2006.239.07:51:30.97#ibcon#about to write, iclass 5, count 0 2006.239.07:51:30.97#ibcon#wrote, iclass 5, count 0 2006.239.07:51:30.97#ibcon#about to read 3, iclass 5, count 0 2006.239.07:51:31.00#ibcon#read 3, iclass 5, count 0 2006.239.07:51:31.00#ibcon#about to read 4, iclass 5, count 0 2006.239.07:51:31.00#ibcon#read 4, iclass 5, count 0 2006.239.07:51:31.00#ibcon#about to read 5, iclass 5, count 0 2006.239.07:51:31.00#ibcon#read 5, iclass 5, count 0 2006.239.07:51:31.00#ibcon#about to read 6, iclass 5, count 0 2006.239.07:51:31.00#ibcon#read 6, iclass 5, count 0 2006.239.07:51:31.00#ibcon#end of sib2, iclass 5, count 0 2006.239.07:51:31.00#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:51:31.00#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:51:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:51:31.00#ibcon#*before write, iclass 5, count 0 2006.239.07:51:31.00#ibcon#enter sib2, iclass 5, count 0 2006.239.07:51:31.00#ibcon#flushed, iclass 5, count 0 2006.239.07:51:31.00#ibcon#about to write, iclass 5, count 0 2006.239.07:51:31.00#ibcon#wrote, iclass 5, count 0 2006.239.07:51:31.00#ibcon#about to read 3, iclass 5, count 0 2006.239.07:51:31.04#ibcon#read 3, iclass 5, count 0 2006.239.07:51:31.04#ibcon#about to read 4, iclass 5, count 0 2006.239.07:51:31.04#ibcon#read 4, iclass 5, count 0 2006.239.07:51:31.04#ibcon#about to read 5, iclass 5, count 0 2006.239.07:51:31.04#ibcon#read 5, iclass 5, count 0 2006.239.07:51:31.04#ibcon#about to read 6, iclass 5, count 0 2006.239.07:51:31.04#ibcon#read 6, iclass 5, count 0 2006.239.07:51:31.04#ibcon#end of sib2, iclass 5, count 0 2006.239.07:51:31.04#ibcon#*after write, iclass 5, count 0 2006.239.07:51:31.04#ibcon#*before return 0, iclass 5, count 0 2006.239.07:51:31.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:31.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.07:51:31.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:51:31.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:51:31.04$vc4f8/vb=2,4 2006.239.07:51:31.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.07:51:31.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.07:51:31.04#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:31.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:31.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:31.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:31.09#ibcon#enter wrdev, iclass 7, count 2 2006.239.07:51:31.09#ibcon#first serial, iclass 7, count 2 2006.239.07:51:31.09#ibcon#enter sib2, iclass 7, count 2 2006.239.07:51:31.09#ibcon#flushed, iclass 7, count 2 2006.239.07:51:31.09#ibcon#about to write, iclass 7, count 2 2006.239.07:51:31.09#ibcon#wrote, iclass 7, count 2 2006.239.07:51:31.09#ibcon#about to read 3, iclass 7, count 2 2006.239.07:51:31.12#ibcon#read 3, iclass 7, count 2 2006.239.07:51:31.12#ibcon#about to read 4, iclass 7, count 2 2006.239.07:51:31.12#ibcon#read 4, iclass 7, count 2 2006.239.07:51:31.12#ibcon#about to read 5, iclass 7, count 2 2006.239.07:51:31.12#ibcon#read 5, iclass 7, count 2 2006.239.07:51:31.12#ibcon#about to read 6, iclass 7, count 2 2006.239.07:51:31.12#ibcon#read 6, iclass 7, count 2 2006.239.07:51:31.12#ibcon#end of sib2, iclass 7, count 2 2006.239.07:51:31.12#ibcon#*mode == 0, iclass 7, count 2 2006.239.07:51:31.12#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.07:51:31.12#ibcon#[27=AT02-04\r\n] 2006.239.07:51:31.12#ibcon#*before write, iclass 7, count 2 2006.239.07:51:31.12#ibcon#enter sib2, iclass 7, count 2 2006.239.07:51:31.12#ibcon#flushed, iclass 7, count 2 2006.239.07:51:31.12#ibcon#about to write, iclass 7, count 2 2006.239.07:51:31.12#ibcon#wrote, iclass 7, count 2 2006.239.07:51:31.12#ibcon#about to read 3, iclass 7, count 2 2006.239.07:51:31.15#ibcon#read 3, iclass 7, count 2 2006.239.07:51:31.15#ibcon#about to read 4, iclass 7, count 2 2006.239.07:51:31.15#ibcon#read 4, iclass 7, count 2 2006.239.07:51:31.15#ibcon#about to read 5, iclass 7, count 2 2006.239.07:51:31.15#ibcon#read 5, iclass 7, count 2 2006.239.07:51:31.15#ibcon#about to read 6, iclass 7, count 2 2006.239.07:51:31.15#ibcon#read 6, iclass 7, count 2 2006.239.07:51:31.15#ibcon#end of sib2, iclass 7, count 2 2006.239.07:51:31.15#ibcon#*after write, iclass 7, count 2 2006.239.07:51:31.15#ibcon#*before return 0, iclass 7, count 2 2006.239.07:51:31.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:31.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.07:51:31.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.07:51:31.15#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:31.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:31.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:31.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:31.27#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:51:31.27#ibcon#first serial, iclass 7, count 0 2006.239.07:51:31.27#ibcon#enter sib2, iclass 7, count 0 2006.239.07:51:31.27#ibcon#flushed, iclass 7, count 0 2006.239.07:51:31.27#ibcon#about to write, iclass 7, count 0 2006.239.07:51:31.27#ibcon#wrote, iclass 7, count 0 2006.239.07:51:31.27#ibcon#about to read 3, iclass 7, count 0 2006.239.07:51:31.29#ibcon#read 3, iclass 7, count 0 2006.239.07:51:31.29#ibcon#about to read 4, iclass 7, count 0 2006.239.07:51:31.29#ibcon#read 4, iclass 7, count 0 2006.239.07:51:31.29#ibcon#about to read 5, iclass 7, count 0 2006.239.07:51:31.29#ibcon#read 5, iclass 7, count 0 2006.239.07:51:31.29#ibcon#about to read 6, iclass 7, count 0 2006.239.07:51:31.29#ibcon#read 6, iclass 7, count 0 2006.239.07:51:31.29#ibcon#end of sib2, iclass 7, count 0 2006.239.07:51:31.29#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:51:31.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:51:31.29#ibcon#[27=USB\r\n] 2006.239.07:51:31.29#ibcon#*before write, iclass 7, count 0 2006.239.07:51:31.29#ibcon#enter sib2, iclass 7, count 0 2006.239.07:51:31.29#ibcon#flushed, iclass 7, count 0 2006.239.07:51:31.29#ibcon#about to write, iclass 7, count 0 2006.239.07:51:31.29#ibcon#wrote, iclass 7, count 0 2006.239.07:51:31.29#ibcon#about to read 3, iclass 7, count 0 2006.239.07:51:31.32#ibcon#read 3, iclass 7, count 0 2006.239.07:51:31.32#ibcon#about to read 4, iclass 7, count 0 2006.239.07:51:31.32#ibcon#read 4, iclass 7, count 0 2006.239.07:51:31.32#ibcon#about to read 5, iclass 7, count 0 2006.239.07:51:31.32#ibcon#read 5, iclass 7, count 0 2006.239.07:51:31.32#ibcon#about to read 6, iclass 7, count 0 2006.239.07:51:31.32#ibcon#read 6, iclass 7, count 0 2006.239.07:51:31.32#ibcon#end of sib2, iclass 7, count 0 2006.239.07:51:31.32#ibcon#*after write, iclass 7, count 0 2006.239.07:51:31.32#ibcon#*before return 0, iclass 7, count 0 2006.239.07:51:31.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:31.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.07:51:31.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:51:31.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:51:31.32$vc4f8/vblo=3,656.99 2006.239.07:51:31.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.07:51:31.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.07:51:31.32#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:31.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:31.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:31.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:31.32#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:51:31.32#ibcon#first serial, iclass 11, count 0 2006.239.07:51:31.32#ibcon#enter sib2, iclass 11, count 0 2006.239.07:51:31.32#ibcon#flushed, iclass 11, count 0 2006.239.07:51:31.32#ibcon#about to write, iclass 11, count 0 2006.239.07:51:31.32#ibcon#wrote, iclass 11, count 0 2006.239.07:51:31.32#ibcon#about to read 3, iclass 11, count 0 2006.239.07:51:31.34#ibcon#read 3, iclass 11, count 0 2006.239.07:51:31.34#ibcon#about to read 4, iclass 11, count 0 2006.239.07:51:31.34#ibcon#read 4, iclass 11, count 0 2006.239.07:51:31.34#ibcon#about to read 5, iclass 11, count 0 2006.239.07:51:31.34#ibcon#read 5, iclass 11, count 0 2006.239.07:51:31.34#ibcon#about to read 6, iclass 11, count 0 2006.239.07:51:31.34#ibcon#read 6, iclass 11, count 0 2006.239.07:51:31.34#ibcon#end of sib2, iclass 11, count 0 2006.239.07:51:31.34#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:51:31.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:51:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:51:31.34#ibcon#*before write, iclass 11, count 0 2006.239.07:51:31.34#ibcon#enter sib2, iclass 11, count 0 2006.239.07:51:31.34#ibcon#flushed, iclass 11, count 0 2006.239.07:51:31.34#ibcon#about to write, iclass 11, count 0 2006.239.07:51:31.34#ibcon#wrote, iclass 11, count 0 2006.239.07:51:31.34#ibcon#about to read 3, iclass 11, count 0 2006.239.07:51:31.38#ibcon#read 3, iclass 11, count 0 2006.239.07:51:31.38#ibcon#about to read 4, iclass 11, count 0 2006.239.07:51:31.38#ibcon#read 4, iclass 11, count 0 2006.239.07:51:31.38#ibcon#about to read 5, iclass 11, count 0 2006.239.07:51:31.38#ibcon#read 5, iclass 11, count 0 2006.239.07:51:31.38#ibcon#about to read 6, iclass 11, count 0 2006.239.07:51:31.38#ibcon#read 6, iclass 11, count 0 2006.239.07:51:31.38#ibcon#end of sib2, iclass 11, count 0 2006.239.07:51:31.38#ibcon#*after write, iclass 11, count 0 2006.239.07:51:31.38#ibcon#*before return 0, iclass 11, count 0 2006.239.07:51:31.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:31.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.07:51:31.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:51:31.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:51:31.38$vc4f8/vb=3,4 2006.239.07:51:31.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.07:51:31.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.07:51:31.38#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:31.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:31.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:31.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:31.44#ibcon#enter wrdev, iclass 13, count 2 2006.239.07:51:31.44#ibcon#first serial, iclass 13, count 2 2006.239.07:51:31.44#ibcon#enter sib2, iclass 13, count 2 2006.239.07:51:31.44#ibcon#flushed, iclass 13, count 2 2006.239.07:51:31.44#ibcon#about to write, iclass 13, count 2 2006.239.07:51:31.44#ibcon#wrote, iclass 13, count 2 2006.239.07:51:31.44#ibcon#about to read 3, iclass 13, count 2 2006.239.07:51:31.46#ibcon#read 3, iclass 13, count 2 2006.239.07:51:31.46#ibcon#about to read 4, iclass 13, count 2 2006.239.07:51:31.46#ibcon#read 4, iclass 13, count 2 2006.239.07:51:31.46#ibcon#about to read 5, iclass 13, count 2 2006.239.07:51:31.46#ibcon#read 5, iclass 13, count 2 2006.239.07:51:31.46#ibcon#about to read 6, iclass 13, count 2 2006.239.07:51:31.46#ibcon#read 6, iclass 13, count 2 2006.239.07:51:31.46#ibcon#end of sib2, iclass 13, count 2 2006.239.07:51:31.46#ibcon#*mode == 0, iclass 13, count 2 2006.239.07:51:31.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.07:51:31.46#ibcon#[27=AT03-04\r\n] 2006.239.07:51:31.46#ibcon#*before write, iclass 13, count 2 2006.239.07:51:31.46#ibcon#enter sib2, iclass 13, count 2 2006.239.07:51:31.46#ibcon#flushed, iclass 13, count 2 2006.239.07:51:31.46#ibcon#about to write, iclass 13, count 2 2006.239.07:51:31.46#ibcon#wrote, iclass 13, count 2 2006.239.07:51:31.46#ibcon#about to read 3, iclass 13, count 2 2006.239.07:51:31.49#ibcon#read 3, iclass 13, count 2 2006.239.07:51:31.49#ibcon#about to read 4, iclass 13, count 2 2006.239.07:51:31.49#ibcon#read 4, iclass 13, count 2 2006.239.07:51:31.49#ibcon#about to read 5, iclass 13, count 2 2006.239.07:51:31.49#ibcon#read 5, iclass 13, count 2 2006.239.07:51:31.49#ibcon#about to read 6, iclass 13, count 2 2006.239.07:51:31.49#ibcon#read 6, iclass 13, count 2 2006.239.07:51:31.49#ibcon#end of sib2, iclass 13, count 2 2006.239.07:51:31.49#ibcon#*after write, iclass 13, count 2 2006.239.07:51:31.49#ibcon#*before return 0, iclass 13, count 2 2006.239.07:51:31.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:31.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.07:51:31.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.07:51:31.49#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:31.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:31.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:31.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:31.61#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:51:31.61#ibcon#first serial, iclass 13, count 0 2006.239.07:51:31.61#ibcon#enter sib2, iclass 13, count 0 2006.239.07:51:31.61#ibcon#flushed, iclass 13, count 0 2006.239.07:51:31.61#ibcon#about to write, iclass 13, count 0 2006.239.07:51:31.61#ibcon#wrote, iclass 13, count 0 2006.239.07:51:31.61#ibcon#about to read 3, iclass 13, count 0 2006.239.07:51:31.63#ibcon#read 3, iclass 13, count 0 2006.239.07:51:31.63#ibcon#about to read 4, iclass 13, count 0 2006.239.07:51:31.63#ibcon#read 4, iclass 13, count 0 2006.239.07:51:31.63#ibcon#about to read 5, iclass 13, count 0 2006.239.07:51:31.63#ibcon#read 5, iclass 13, count 0 2006.239.07:51:31.63#ibcon#about to read 6, iclass 13, count 0 2006.239.07:51:31.63#ibcon#read 6, iclass 13, count 0 2006.239.07:51:31.63#ibcon#end of sib2, iclass 13, count 0 2006.239.07:51:31.63#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:51:31.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:51:31.63#ibcon#[27=USB\r\n] 2006.239.07:51:31.63#ibcon#*before write, iclass 13, count 0 2006.239.07:51:31.63#ibcon#enter sib2, iclass 13, count 0 2006.239.07:51:31.63#ibcon#flushed, iclass 13, count 0 2006.239.07:51:31.63#ibcon#about to write, iclass 13, count 0 2006.239.07:51:31.63#ibcon#wrote, iclass 13, count 0 2006.239.07:51:31.63#ibcon#about to read 3, iclass 13, count 0 2006.239.07:51:31.66#ibcon#read 3, iclass 13, count 0 2006.239.07:51:31.66#ibcon#about to read 4, iclass 13, count 0 2006.239.07:51:31.66#ibcon#read 4, iclass 13, count 0 2006.239.07:51:31.66#ibcon#about to read 5, iclass 13, count 0 2006.239.07:51:31.66#ibcon#read 5, iclass 13, count 0 2006.239.07:51:31.66#ibcon#about to read 6, iclass 13, count 0 2006.239.07:51:31.66#ibcon#read 6, iclass 13, count 0 2006.239.07:51:31.66#ibcon#end of sib2, iclass 13, count 0 2006.239.07:51:31.66#ibcon#*after write, iclass 13, count 0 2006.239.07:51:31.66#ibcon#*before return 0, iclass 13, count 0 2006.239.07:51:31.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:31.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.07:51:31.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:51:31.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:51:31.66$vc4f8/vblo=4,712.99 2006.239.07:51:31.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.07:51:31.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.07:51:31.66#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:31.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:31.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:31.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:31.66#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:51:31.66#ibcon#first serial, iclass 15, count 0 2006.239.07:51:31.66#ibcon#enter sib2, iclass 15, count 0 2006.239.07:51:31.66#ibcon#flushed, iclass 15, count 0 2006.239.07:51:31.66#ibcon#about to write, iclass 15, count 0 2006.239.07:51:31.66#ibcon#wrote, iclass 15, count 0 2006.239.07:51:31.66#ibcon#about to read 3, iclass 15, count 0 2006.239.07:51:31.68#ibcon#read 3, iclass 15, count 0 2006.239.07:51:31.68#ibcon#about to read 4, iclass 15, count 0 2006.239.07:51:31.68#ibcon#read 4, iclass 15, count 0 2006.239.07:51:31.68#ibcon#about to read 5, iclass 15, count 0 2006.239.07:51:31.68#ibcon#read 5, iclass 15, count 0 2006.239.07:51:31.68#ibcon#about to read 6, iclass 15, count 0 2006.239.07:51:31.68#ibcon#read 6, iclass 15, count 0 2006.239.07:51:31.68#ibcon#end of sib2, iclass 15, count 0 2006.239.07:51:31.68#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:51:31.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:51:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:51:31.68#ibcon#*before write, iclass 15, count 0 2006.239.07:51:31.68#ibcon#enter sib2, iclass 15, count 0 2006.239.07:51:31.68#ibcon#flushed, iclass 15, count 0 2006.239.07:51:31.68#ibcon#about to write, iclass 15, count 0 2006.239.07:51:31.68#ibcon#wrote, iclass 15, count 0 2006.239.07:51:31.68#ibcon#about to read 3, iclass 15, count 0 2006.239.07:51:31.72#ibcon#read 3, iclass 15, count 0 2006.239.07:51:31.72#ibcon#about to read 4, iclass 15, count 0 2006.239.07:51:31.72#ibcon#read 4, iclass 15, count 0 2006.239.07:51:31.72#ibcon#about to read 5, iclass 15, count 0 2006.239.07:51:31.72#ibcon#read 5, iclass 15, count 0 2006.239.07:51:31.72#ibcon#about to read 6, iclass 15, count 0 2006.239.07:51:31.72#ibcon#read 6, iclass 15, count 0 2006.239.07:51:31.72#ibcon#end of sib2, iclass 15, count 0 2006.239.07:51:31.72#ibcon#*after write, iclass 15, count 0 2006.239.07:51:31.72#ibcon#*before return 0, iclass 15, count 0 2006.239.07:51:31.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:31.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:51:31.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:51:31.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:51:31.72$vc4f8/vb=4,4 2006.239.07:51:31.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.07:51:31.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.07:51:31.72#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:31.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:31.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:31.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:31.78#ibcon#enter wrdev, iclass 17, count 2 2006.239.07:51:31.78#ibcon#first serial, iclass 17, count 2 2006.239.07:51:31.78#ibcon#enter sib2, iclass 17, count 2 2006.239.07:51:31.78#ibcon#flushed, iclass 17, count 2 2006.239.07:51:31.78#ibcon#about to write, iclass 17, count 2 2006.239.07:51:31.78#ibcon#wrote, iclass 17, count 2 2006.239.07:51:31.78#ibcon#about to read 3, iclass 17, count 2 2006.239.07:51:31.80#ibcon#read 3, iclass 17, count 2 2006.239.07:51:31.80#ibcon#about to read 4, iclass 17, count 2 2006.239.07:51:31.80#ibcon#read 4, iclass 17, count 2 2006.239.07:51:31.80#ibcon#about to read 5, iclass 17, count 2 2006.239.07:51:31.80#ibcon#read 5, iclass 17, count 2 2006.239.07:51:31.80#ibcon#about to read 6, iclass 17, count 2 2006.239.07:51:31.80#ibcon#read 6, iclass 17, count 2 2006.239.07:51:31.80#ibcon#end of sib2, iclass 17, count 2 2006.239.07:51:31.80#ibcon#*mode == 0, iclass 17, count 2 2006.239.07:51:31.80#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.07:51:31.80#ibcon#[27=AT04-04\r\n] 2006.239.07:51:31.80#ibcon#*before write, iclass 17, count 2 2006.239.07:51:31.80#ibcon#enter sib2, iclass 17, count 2 2006.239.07:51:31.80#ibcon#flushed, iclass 17, count 2 2006.239.07:51:31.80#ibcon#about to write, iclass 17, count 2 2006.239.07:51:31.80#ibcon#wrote, iclass 17, count 2 2006.239.07:51:31.80#ibcon#about to read 3, iclass 17, count 2 2006.239.07:51:31.83#ibcon#read 3, iclass 17, count 2 2006.239.07:51:31.83#ibcon#about to read 4, iclass 17, count 2 2006.239.07:51:31.83#ibcon#read 4, iclass 17, count 2 2006.239.07:51:31.83#ibcon#about to read 5, iclass 17, count 2 2006.239.07:51:31.83#ibcon#read 5, iclass 17, count 2 2006.239.07:51:31.83#ibcon#about to read 6, iclass 17, count 2 2006.239.07:51:31.83#ibcon#read 6, iclass 17, count 2 2006.239.07:51:31.83#ibcon#end of sib2, iclass 17, count 2 2006.239.07:51:31.83#ibcon#*after write, iclass 17, count 2 2006.239.07:51:31.83#ibcon#*before return 0, iclass 17, count 2 2006.239.07:51:31.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:31.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.07:51:31.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.07:51:31.83#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:31.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:31.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:31.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:31.95#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:51:31.95#ibcon#first serial, iclass 17, count 0 2006.239.07:51:31.95#ibcon#enter sib2, iclass 17, count 0 2006.239.07:51:31.95#ibcon#flushed, iclass 17, count 0 2006.239.07:51:31.95#ibcon#about to write, iclass 17, count 0 2006.239.07:51:31.95#ibcon#wrote, iclass 17, count 0 2006.239.07:51:31.95#ibcon#about to read 3, iclass 17, count 0 2006.239.07:51:31.97#ibcon#read 3, iclass 17, count 0 2006.239.07:51:31.97#ibcon#about to read 4, iclass 17, count 0 2006.239.07:51:31.97#ibcon#read 4, iclass 17, count 0 2006.239.07:51:31.97#ibcon#about to read 5, iclass 17, count 0 2006.239.07:51:31.97#ibcon#read 5, iclass 17, count 0 2006.239.07:51:31.97#ibcon#about to read 6, iclass 17, count 0 2006.239.07:51:31.97#ibcon#read 6, iclass 17, count 0 2006.239.07:51:31.97#ibcon#end of sib2, iclass 17, count 0 2006.239.07:51:31.97#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:51:31.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:51:31.97#ibcon#[27=USB\r\n] 2006.239.07:51:31.97#ibcon#*before write, iclass 17, count 0 2006.239.07:51:31.97#ibcon#enter sib2, iclass 17, count 0 2006.239.07:51:31.97#ibcon#flushed, iclass 17, count 0 2006.239.07:51:31.97#ibcon#about to write, iclass 17, count 0 2006.239.07:51:31.97#ibcon#wrote, iclass 17, count 0 2006.239.07:51:31.97#ibcon#about to read 3, iclass 17, count 0 2006.239.07:51:32.00#ibcon#read 3, iclass 17, count 0 2006.239.07:51:32.00#ibcon#about to read 4, iclass 17, count 0 2006.239.07:51:32.00#ibcon#read 4, iclass 17, count 0 2006.239.07:51:32.00#ibcon#about to read 5, iclass 17, count 0 2006.239.07:51:32.00#ibcon#read 5, iclass 17, count 0 2006.239.07:51:32.00#ibcon#about to read 6, iclass 17, count 0 2006.239.07:51:32.00#ibcon#read 6, iclass 17, count 0 2006.239.07:51:32.00#ibcon#end of sib2, iclass 17, count 0 2006.239.07:51:32.00#ibcon#*after write, iclass 17, count 0 2006.239.07:51:32.00#ibcon#*before return 0, iclass 17, count 0 2006.239.07:51:32.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:32.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.07:51:32.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:51:32.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:51:32.00$vc4f8/vblo=5,744.99 2006.239.07:51:32.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.07:51:32.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.07:51:32.00#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:32.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:32.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:32.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:32.00#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:51:32.00#ibcon#first serial, iclass 19, count 0 2006.239.07:51:32.00#ibcon#enter sib2, iclass 19, count 0 2006.239.07:51:32.00#ibcon#flushed, iclass 19, count 0 2006.239.07:51:32.00#ibcon#about to write, iclass 19, count 0 2006.239.07:51:32.00#ibcon#wrote, iclass 19, count 0 2006.239.07:51:32.00#ibcon#about to read 3, iclass 19, count 0 2006.239.07:51:32.02#ibcon#read 3, iclass 19, count 0 2006.239.07:51:32.02#ibcon#about to read 4, iclass 19, count 0 2006.239.07:51:32.02#ibcon#read 4, iclass 19, count 0 2006.239.07:51:32.02#ibcon#about to read 5, iclass 19, count 0 2006.239.07:51:32.02#ibcon#read 5, iclass 19, count 0 2006.239.07:51:32.02#ibcon#about to read 6, iclass 19, count 0 2006.239.07:51:32.02#ibcon#read 6, iclass 19, count 0 2006.239.07:51:32.02#ibcon#end of sib2, iclass 19, count 0 2006.239.07:51:32.02#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:51:32.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:51:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:51:32.02#ibcon#*before write, iclass 19, count 0 2006.239.07:51:32.02#ibcon#enter sib2, iclass 19, count 0 2006.239.07:51:32.02#ibcon#flushed, iclass 19, count 0 2006.239.07:51:32.02#ibcon#about to write, iclass 19, count 0 2006.239.07:51:32.02#ibcon#wrote, iclass 19, count 0 2006.239.07:51:32.02#ibcon#about to read 3, iclass 19, count 0 2006.239.07:51:32.06#ibcon#read 3, iclass 19, count 0 2006.239.07:51:32.06#ibcon#about to read 4, iclass 19, count 0 2006.239.07:51:32.06#ibcon#read 4, iclass 19, count 0 2006.239.07:51:32.06#ibcon#about to read 5, iclass 19, count 0 2006.239.07:51:32.06#ibcon#read 5, iclass 19, count 0 2006.239.07:51:32.06#ibcon#about to read 6, iclass 19, count 0 2006.239.07:51:32.06#ibcon#read 6, iclass 19, count 0 2006.239.07:51:32.06#ibcon#end of sib2, iclass 19, count 0 2006.239.07:51:32.06#ibcon#*after write, iclass 19, count 0 2006.239.07:51:32.06#ibcon#*before return 0, iclass 19, count 0 2006.239.07:51:32.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:32.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.07:51:32.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:51:32.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:51:32.06$vc4f8/vb=5,4 2006.239.07:51:32.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.07:51:32.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.07:51:32.06#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:32.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:32.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:32.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:32.12#ibcon#enter wrdev, iclass 21, count 2 2006.239.07:51:32.12#ibcon#first serial, iclass 21, count 2 2006.239.07:51:32.12#ibcon#enter sib2, iclass 21, count 2 2006.239.07:51:32.12#ibcon#flushed, iclass 21, count 2 2006.239.07:51:32.12#ibcon#about to write, iclass 21, count 2 2006.239.07:51:32.12#ibcon#wrote, iclass 21, count 2 2006.239.07:51:32.12#ibcon#about to read 3, iclass 21, count 2 2006.239.07:51:32.14#ibcon#read 3, iclass 21, count 2 2006.239.07:51:32.14#ibcon#about to read 4, iclass 21, count 2 2006.239.07:51:32.14#ibcon#read 4, iclass 21, count 2 2006.239.07:51:32.14#ibcon#about to read 5, iclass 21, count 2 2006.239.07:51:32.14#ibcon#read 5, iclass 21, count 2 2006.239.07:51:32.14#ibcon#about to read 6, iclass 21, count 2 2006.239.07:51:32.14#ibcon#read 6, iclass 21, count 2 2006.239.07:51:32.14#ibcon#end of sib2, iclass 21, count 2 2006.239.07:51:32.14#ibcon#*mode == 0, iclass 21, count 2 2006.239.07:51:32.14#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.07:51:32.14#ibcon#[27=AT05-04\r\n] 2006.239.07:51:32.14#ibcon#*before write, iclass 21, count 2 2006.239.07:51:32.14#ibcon#enter sib2, iclass 21, count 2 2006.239.07:51:32.14#ibcon#flushed, iclass 21, count 2 2006.239.07:51:32.14#ibcon#about to write, iclass 21, count 2 2006.239.07:51:32.14#ibcon#wrote, iclass 21, count 2 2006.239.07:51:32.14#ibcon#about to read 3, iclass 21, count 2 2006.239.07:51:32.17#ibcon#read 3, iclass 21, count 2 2006.239.07:51:32.17#ibcon#about to read 4, iclass 21, count 2 2006.239.07:51:32.17#ibcon#read 4, iclass 21, count 2 2006.239.07:51:32.17#ibcon#about to read 5, iclass 21, count 2 2006.239.07:51:32.17#ibcon#read 5, iclass 21, count 2 2006.239.07:51:32.17#ibcon#about to read 6, iclass 21, count 2 2006.239.07:51:32.17#ibcon#read 6, iclass 21, count 2 2006.239.07:51:32.17#ibcon#end of sib2, iclass 21, count 2 2006.239.07:51:32.17#ibcon#*after write, iclass 21, count 2 2006.239.07:51:32.17#ibcon#*before return 0, iclass 21, count 2 2006.239.07:51:32.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:32.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.07:51:32.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.07:51:32.17#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:32.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:32.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:32.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:32.29#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:51:32.29#ibcon#first serial, iclass 21, count 0 2006.239.07:51:32.29#ibcon#enter sib2, iclass 21, count 0 2006.239.07:51:32.29#ibcon#flushed, iclass 21, count 0 2006.239.07:51:32.29#ibcon#about to write, iclass 21, count 0 2006.239.07:51:32.29#ibcon#wrote, iclass 21, count 0 2006.239.07:51:32.29#ibcon#about to read 3, iclass 21, count 0 2006.239.07:51:32.31#ibcon#read 3, iclass 21, count 0 2006.239.07:51:32.31#ibcon#about to read 4, iclass 21, count 0 2006.239.07:51:32.31#ibcon#read 4, iclass 21, count 0 2006.239.07:51:32.31#ibcon#about to read 5, iclass 21, count 0 2006.239.07:51:32.31#ibcon#read 5, iclass 21, count 0 2006.239.07:51:32.31#ibcon#about to read 6, iclass 21, count 0 2006.239.07:51:32.31#ibcon#read 6, iclass 21, count 0 2006.239.07:51:32.31#ibcon#end of sib2, iclass 21, count 0 2006.239.07:51:32.31#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:51:32.31#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:51:32.31#ibcon#[27=USB\r\n] 2006.239.07:51:32.31#ibcon#*before write, iclass 21, count 0 2006.239.07:51:32.31#ibcon#enter sib2, iclass 21, count 0 2006.239.07:51:32.31#ibcon#flushed, iclass 21, count 0 2006.239.07:51:32.31#ibcon#about to write, iclass 21, count 0 2006.239.07:51:32.31#ibcon#wrote, iclass 21, count 0 2006.239.07:51:32.31#ibcon#about to read 3, iclass 21, count 0 2006.239.07:51:32.34#ibcon#read 3, iclass 21, count 0 2006.239.07:51:32.34#ibcon#about to read 4, iclass 21, count 0 2006.239.07:51:32.34#ibcon#read 4, iclass 21, count 0 2006.239.07:51:32.34#ibcon#about to read 5, iclass 21, count 0 2006.239.07:51:32.34#ibcon#read 5, iclass 21, count 0 2006.239.07:51:32.34#ibcon#about to read 6, iclass 21, count 0 2006.239.07:51:32.34#ibcon#read 6, iclass 21, count 0 2006.239.07:51:32.34#ibcon#end of sib2, iclass 21, count 0 2006.239.07:51:32.34#ibcon#*after write, iclass 21, count 0 2006.239.07:51:32.34#ibcon#*before return 0, iclass 21, count 0 2006.239.07:51:32.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:32.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.07:51:32.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:51:32.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:51:32.34$vc4f8/vblo=6,752.99 2006.239.07:51:32.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.07:51:32.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.07:51:32.34#ibcon#ireg 17 cls_cnt 0 2006.239.07:51:32.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:32.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:32.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:32.34#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:51:32.34#ibcon#first serial, iclass 23, count 0 2006.239.07:51:32.34#ibcon#enter sib2, iclass 23, count 0 2006.239.07:51:32.34#ibcon#flushed, iclass 23, count 0 2006.239.07:51:32.34#ibcon#about to write, iclass 23, count 0 2006.239.07:51:32.34#ibcon#wrote, iclass 23, count 0 2006.239.07:51:32.34#ibcon#about to read 3, iclass 23, count 0 2006.239.07:51:32.36#ibcon#read 3, iclass 23, count 0 2006.239.07:51:32.36#ibcon#about to read 4, iclass 23, count 0 2006.239.07:51:32.36#ibcon#read 4, iclass 23, count 0 2006.239.07:51:32.36#ibcon#about to read 5, iclass 23, count 0 2006.239.07:51:32.36#ibcon#read 5, iclass 23, count 0 2006.239.07:51:32.36#ibcon#about to read 6, iclass 23, count 0 2006.239.07:51:32.36#ibcon#read 6, iclass 23, count 0 2006.239.07:51:32.36#ibcon#end of sib2, iclass 23, count 0 2006.239.07:51:32.36#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:51:32.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:51:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:51:32.36#ibcon#*before write, iclass 23, count 0 2006.239.07:51:32.36#ibcon#enter sib2, iclass 23, count 0 2006.239.07:51:32.36#ibcon#flushed, iclass 23, count 0 2006.239.07:51:32.36#ibcon#about to write, iclass 23, count 0 2006.239.07:51:32.36#ibcon#wrote, iclass 23, count 0 2006.239.07:51:32.36#ibcon#about to read 3, iclass 23, count 0 2006.239.07:51:32.40#ibcon#read 3, iclass 23, count 0 2006.239.07:51:32.40#ibcon#about to read 4, iclass 23, count 0 2006.239.07:51:32.40#ibcon#read 4, iclass 23, count 0 2006.239.07:51:32.40#ibcon#about to read 5, iclass 23, count 0 2006.239.07:51:32.40#ibcon#read 5, iclass 23, count 0 2006.239.07:51:32.40#ibcon#about to read 6, iclass 23, count 0 2006.239.07:51:32.40#ibcon#read 6, iclass 23, count 0 2006.239.07:51:32.40#ibcon#end of sib2, iclass 23, count 0 2006.239.07:51:32.40#ibcon#*after write, iclass 23, count 0 2006.239.07:51:32.40#ibcon#*before return 0, iclass 23, count 0 2006.239.07:51:32.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:32.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.07:51:32.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:51:32.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:51:32.40$vc4f8/vb=6,4 2006.239.07:51:32.40#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.07:51:32.40#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.07:51:32.40#ibcon#ireg 11 cls_cnt 2 2006.239.07:51:32.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:32.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:32.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:32.46#ibcon#enter wrdev, iclass 25, count 2 2006.239.07:51:32.46#ibcon#first serial, iclass 25, count 2 2006.239.07:51:32.46#ibcon#enter sib2, iclass 25, count 2 2006.239.07:51:32.46#ibcon#flushed, iclass 25, count 2 2006.239.07:51:32.46#ibcon#about to write, iclass 25, count 2 2006.239.07:51:32.46#ibcon#wrote, iclass 25, count 2 2006.239.07:51:32.46#ibcon#about to read 3, iclass 25, count 2 2006.239.07:51:32.48#ibcon#read 3, iclass 25, count 2 2006.239.07:51:32.48#ibcon#about to read 4, iclass 25, count 2 2006.239.07:51:32.48#ibcon#read 4, iclass 25, count 2 2006.239.07:51:32.48#ibcon#about to read 5, iclass 25, count 2 2006.239.07:51:32.48#ibcon#read 5, iclass 25, count 2 2006.239.07:51:32.48#ibcon#about to read 6, iclass 25, count 2 2006.239.07:51:32.48#ibcon#read 6, iclass 25, count 2 2006.239.07:51:32.48#ibcon#end of sib2, iclass 25, count 2 2006.239.07:51:32.48#ibcon#*mode == 0, iclass 25, count 2 2006.239.07:51:32.48#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.07:51:32.48#ibcon#[27=AT06-04\r\n] 2006.239.07:51:32.48#ibcon#*before write, iclass 25, count 2 2006.239.07:51:32.48#ibcon#enter sib2, iclass 25, count 2 2006.239.07:51:32.48#ibcon#flushed, iclass 25, count 2 2006.239.07:51:32.48#ibcon#about to write, iclass 25, count 2 2006.239.07:51:32.48#ibcon#wrote, iclass 25, count 2 2006.239.07:51:32.48#ibcon#about to read 3, iclass 25, count 2 2006.239.07:51:32.52#ibcon#read 3, iclass 25, count 2 2006.239.07:51:32.52#ibcon#about to read 4, iclass 25, count 2 2006.239.07:51:32.52#ibcon#read 4, iclass 25, count 2 2006.239.07:51:32.52#ibcon#about to read 5, iclass 25, count 2 2006.239.07:51:32.52#ibcon#read 5, iclass 25, count 2 2006.239.07:51:32.52#ibcon#about to read 6, iclass 25, count 2 2006.239.07:51:32.52#ibcon#read 6, iclass 25, count 2 2006.239.07:51:32.52#ibcon#end of sib2, iclass 25, count 2 2006.239.07:51:32.52#ibcon#*after write, iclass 25, count 2 2006.239.07:51:32.52#ibcon#*before return 0, iclass 25, count 2 2006.239.07:51:32.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:32.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.07:51:32.52#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.07:51:32.52#ibcon#ireg 7 cls_cnt 0 2006.239.07:51:32.52#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:32.64#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:32.64#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:32.64#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:51:32.64#ibcon#first serial, iclass 25, count 0 2006.239.07:51:32.64#ibcon#enter sib2, iclass 25, count 0 2006.239.07:51:32.64#ibcon#flushed, iclass 25, count 0 2006.239.07:51:32.64#ibcon#about to write, iclass 25, count 0 2006.239.07:51:32.64#ibcon#wrote, iclass 25, count 0 2006.239.07:51:32.64#ibcon#about to read 3, iclass 25, count 0 2006.239.07:51:32.65#ibcon#read 3, iclass 25, count 0 2006.239.07:51:32.65#ibcon#about to read 4, iclass 25, count 0 2006.239.07:51:32.65#ibcon#read 4, iclass 25, count 0 2006.239.07:51:32.65#ibcon#about to read 5, iclass 25, count 0 2006.239.07:51:32.65#ibcon#read 5, iclass 25, count 0 2006.239.07:51:32.65#ibcon#about to read 6, iclass 25, count 0 2006.239.07:51:32.65#ibcon#read 6, iclass 25, count 0 2006.239.07:51:32.65#ibcon#end of sib2, iclass 25, count 0 2006.239.07:51:32.65#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:51:32.65#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:51:32.65#ibcon#[27=USB\r\n] 2006.239.07:51:32.65#ibcon#*before write, iclass 25, count 0 2006.239.07:51:32.65#ibcon#enter sib2, iclass 25, count 0 2006.239.07:51:32.65#ibcon#flushed, iclass 25, count 0 2006.239.07:51:32.65#ibcon#about to write, iclass 25, count 0 2006.239.07:51:32.65#ibcon#wrote, iclass 25, count 0 2006.239.07:51:32.65#ibcon#about to read 3, iclass 25, count 0 2006.239.07:51:32.68#ibcon#read 3, iclass 25, count 0 2006.239.07:51:32.68#ibcon#about to read 4, iclass 25, count 0 2006.239.07:51:32.68#ibcon#read 4, iclass 25, count 0 2006.239.07:51:32.68#ibcon#about to read 5, iclass 25, count 0 2006.239.07:51:32.68#ibcon#read 5, iclass 25, count 0 2006.239.07:51:32.68#ibcon#about to read 6, iclass 25, count 0 2006.239.07:51:32.68#ibcon#read 6, iclass 25, count 0 2006.239.07:51:32.68#ibcon#end of sib2, iclass 25, count 0 2006.239.07:51:32.68#ibcon#*after write, iclass 25, count 0 2006.239.07:51:32.68#ibcon#*before return 0, iclass 25, count 0 2006.239.07:51:32.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:32.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.07:51:32.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:51:32.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:51:32.68$vc4f8/vabw=wide 2006.239.07:51:32.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.07:51:32.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.07:51:32.68#ibcon#ireg 8 cls_cnt 0 2006.239.07:51:32.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:32.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:32.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:32.68#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:51:32.68#ibcon#first serial, iclass 27, count 0 2006.239.07:51:32.68#ibcon#enter sib2, iclass 27, count 0 2006.239.07:51:32.68#ibcon#flushed, iclass 27, count 0 2006.239.07:51:32.68#ibcon#about to write, iclass 27, count 0 2006.239.07:51:32.68#ibcon#wrote, iclass 27, count 0 2006.239.07:51:32.68#ibcon#about to read 3, iclass 27, count 0 2006.239.07:51:32.70#ibcon#read 3, iclass 27, count 0 2006.239.07:51:32.70#ibcon#about to read 4, iclass 27, count 0 2006.239.07:51:32.70#ibcon#read 4, iclass 27, count 0 2006.239.07:51:32.70#ibcon#about to read 5, iclass 27, count 0 2006.239.07:51:32.70#ibcon#read 5, iclass 27, count 0 2006.239.07:51:32.70#ibcon#about to read 6, iclass 27, count 0 2006.239.07:51:32.70#ibcon#read 6, iclass 27, count 0 2006.239.07:51:32.70#ibcon#end of sib2, iclass 27, count 0 2006.239.07:51:32.70#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:51:32.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:51:32.70#ibcon#[25=BW32\r\n] 2006.239.07:51:32.70#ibcon#*before write, iclass 27, count 0 2006.239.07:51:32.70#ibcon#enter sib2, iclass 27, count 0 2006.239.07:51:32.70#ibcon#flushed, iclass 27, count 0 2006.239.07:51:32.70#ibcon#about to write, iclass 27, count 0 2006.239.07:51:32.70#ibcon#wrote, iclass 27, count 0 2006.239.07:51:32.70#ibcon#about to read 3, iclass 27, count 0 2006.239.07:51:32.73#ibcon#read 3, iclass 27, count 0 2006.239.07:51:32.73#ibcon#about to read 4, iclass 27, count 0 2006.239.07:51:32.73#ibcon#read 4, iclass 27, count 0 2006.239.07:51:32.73#ibcon#about to read 5, iclass 27, count 0 2006.239.07:51:32.73#ibcon#read 5, iclass 27, count 0 2006.239.07:51:32.73#ibcon#about to read 6, iclass 27, count 0 2006.239.07:51:32.73#ibcon#read 6, iclass 27, count 0 2006.239.07:51:32.73#ibcon#end of sib2, iclass 27, count 0 2006.239.07:51:32.73#ibcon#*after write, iclass 27, count 0 2006.239.07:51:32.73#ibcon#*before return 0, iclass 27, count 0 2006.239.07:51:32.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:32.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.07:51:32.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:51:32.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:51:32.73$vc4f8/vbbw=wide 2006.239.07:51:32.73#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:51:32.73#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:51:32.73#ibcon#ireg 8 cls_cnt 0 2006.239.07:51:32.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:51:32.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:51:32.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:51:32.80#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:51:32.80#ibcon#first serial, iclass 29, count 0 2006.239.07:51:32.80#ibcon#enter sib2, iclass 29, count 0 2006.239.07:51:32.80#ibcon#flushed, iclass 29, count 0 2006.239.07:51:32.80#ibcon#about to write, iclass 29, count 0 2006.239.07:51:32.80#ibcon#wrote, iclass 29, count 0 2006.239.07:51:32.80#ibcon#about to read 3, iclass 29, count 0 2006.239.07:51:32.82#ibcon#read 3, iclass 29, count 0 2006.239.07:51:32.82#ibcon#about to read 4, iclass 29, count 0 2006.239.07:51:32.82#ibcon#read 4, iclass 29, count 0 2006.239.07:51:32.82#ibcon#about to read 5, iclass 29, count 0 2006.239.07:51:32.82#ibcon#read 5, iclass 29, count 0 2006.239.07:51:32.82#ibcon#about to read 6, iclass 29, count 0 2006.239.07:51:32.82#ibcon#read 6, iclass 29, count 0 2006.239.07:51:32.82#ibcon#end of sib2, iclass 29, count 0 2006.239.07:51:32.82#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:51:32.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:51:32.82#ibcon#[27=BW32\r\n] 2006.239.07:51:32.82#ibcon#*before write, iclass 29, count 0 2006.239.07:51:32.82#ibcon#enter sib2, iclass 29, count 0 2006.239.07:51:32.82#ibcon#flushed, iclass 29, count 0 2006.239.07:51:32.82#ibcon#about to write, iclass 29, count 0 2006.239.07:51:32.82#ibcon#wrote, iclass 29, count 0 2006.239.07:51:32.82#ibcon#about to read 3, iclass 29, count 0 2006.239.07:51:32.85#ibcon#read 3, iclass 29, count 0 2006.239.07:51:32.85#ibcon#about to read 4, iclass 29, count 0 2006.239.07:51:32.85#ibcon#read 4, iclass 29, count 0 2006.239.07:51:32.85#ibcon#about to read 5, iclass 29, count 0 2006.239.07:51:32.85#ibcon#read 5, iclass 29, count 0 2006.239.07:51:32.85#ibcon#about to read 6, iclass 29, count 0 2006.239.07:51:32.85#ibcon#read 6, iclass 29, count 0 2006.239.07:51:32.85#ibcon#end of sib2, iclass 29, count 0 2006.239.07:51:32.85#ibcon#*after write, iclass 29, count 0 2006.239.07:51:32.85#ibcon#*before return 0, iclass 29, count 0 2006.239.07:51:32.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:51:32.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:51:32.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:51:32.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:51:32.85$4f8m12a/ifd4f 2006.239.07:51:32.85$ifd4f/lo= 2006.239.07:51:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:51:32.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:51:32.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:51:32.85$ifd4f/patch= 2006.239.07:51:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:51:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:51:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:51:32.85$4f8m12a/"form=m,16.000,1:2 2006.239.07:51:32.85$4f8m12a/"tpicd 2006.239.07:51:32.85$4f8m12a/echo=off 2006.239.07:51:32.85$4f8m12a/xlog=off 2006.239.07:51:32.85:!2006.239.07:52:00 2006.239.07:51:44.14#trakl#Source acquired 2006.239.07:51:45.14#flagr#flagr/antenna,acquired 2006.239.07:52:00.00:preob 2006.239.07:52:01.14/onsource/TRACKING 2006.239.07:52:01.14:!2006.239.07:52:10 2006.239.07:52:10.00:data_valid=on 2006.239.07:52:10.00:midob 2006.239.07:52:10.14/onsource/TRACKING 2006.239.07:52:10.14/wx/25.25,1011.6,80 2006.239.07:52:10.33/cable/+6.4153E-03 2006.239.07:52:11.42/va/01,08,usb,yes,31,32 2006.239.07:52:11.42/va/02,07,usb,yes,31,32 2006.239.07:52:11.42/va/03,07,usb,yes,29,29 2006.239.07:52:11.42/va/04,07,usb,yes,32,35 2006.239.07:52:11.42/va/05,08,usb,yes,30,31 2006.239.07:52:11.42/va/06,07,usb,yes,32,32 2006.239.07:52:11.42/va/07,07,usb,yes,32,32 2006.239.07:52:11.42/va/08,07,usb,yes,35,34 2006.239.07:52:11.65/valo/01,532.99,yes,locked 2006.239.07:52:11.65/valo/02,572.99,yes,locked 2006.239.07:52:11.65/valo/03,672.99,yes,locked 2006.239.07:52:11.65/valo/04,832.99,yes,locked 2006.239.07:52:11.65/valo/05,652.99,yes,locked 2006.239.07:52:11.65/valo/06,772.99,yes,locked 2006.239.07:52:11.65/valo/07,832.99,yes,locked 2006.239.07:52:11.65/valo/08,852.99,yes,locked 2006.239.07:52:12.74/vb/01,04,usb,yes,30,29 2006.239.07:52:12.74/vb/02,04,usb,yes,32,34 2006.239.07:52:12.74/vb/03,04,usb,yes,29,32 2006.239.07:52:12.74/vb/04,04,usb,yes,29,30 2006.239.07:52:12.74/vb/05,04,usb,yes,28,32 2006.239.07:52:12.74/vb/06,04,usb,yes,29,32 2006.239.07:52:12.74/vb/07,04,usb,yes,31,31 2006.239.07:52:12.74/vb/08,04,usb,yes,28,32 2006.239.07:52:12.97/vblo/01,632.99,yes,locked 2006.239.07:52:12.97/vblo/02,640.99,yes,locked 2006.239.07:52:12.97/vblo/03,656.99,yes,locked 2006.239.07:52:12.97/vblo/04,712.99,yes,locked 2006.239.07:52:12.97/vblo/05,744.99,yes,locked 2006.239.07:52:12.97/vblo/06,752.99,yes,locked 2006.239.07:52:12.97/vblo/07,734.99,yes,locked 2006.239.07:52:12.97/vblo/08,744.99,yes,locked 2006.239.07:52:13.12/vabw/8 2006.239.07:52:13.27/vbbw/8 2006.239.07:52:13.36/xfe/off,on,13.2 2006.239.07:52:13.74/ifatt/23,28,28,28 2006.239.07:52:14.08/fmout-gps/S +4.43E-07 2006.239.07:52:14.12:!2006.239.07:53:10 2006.239.07:53:10.00:data_valid=off 2006.239.07:53:10.00:postob 2006.239.07:53:10.08/cable/+6.4159E-03 2006.239.07:53:10.08/wx/25.24,1011.6,80 2006.239.07:53:11.08/fmout-gps/S +4.43E-07 2006.239.07:53:11.08:scan_name=239-0755,k06239,60 2006.239.07:53:11.08:source=oq208,140700.39,282714.7,2000.0,ccw 2006.239.07:53:11.14#flagr#flagr/antenna,new-source 2006.239.07:53:12.14:checkk5 2006.239.07:53:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:53:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:53:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:53:13.67/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:53:14.03/chk_obsdata//k5ts1/T2390752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:53:14.41/chk_obsdata//k5ts2/T2390752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:53:14.79/chk_obsdata//k5ts3/T2390752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:53:15.16/chk_obsdata//k5ts4/T2390752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:53:15.85/k5log//k5ts1_log_newline 2006.239.07:53:16.55/k5log//k5ts2_log_newline 2006.239.07:53:17.24/k5log//k5ts3_log_newline 2006.239.07:53:17.93/k5log//k5ts4_log_newline 2006.239.07:53:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:53:17.95:4f8m12a=2 2006.239.07:53:17.95$4f8m12a/echo=on 2006.239.07:53:17.95$4f8m12a/pcalon 2006.239.07:53:17.95$pcalon/"no phase cal control is implemented here 2006.239.07:53:17.95$4f8m12a/"tpicd=stop 2006.239.07:53:17.95$4f8m12a/vc4f8 2006.239.07:53:17.95$vc4f8/valo=1,532.99 2006.239.07:53:17.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:53:17.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:53:17.95#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:17.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:17.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:17.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:17.95#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:53:17.95#ibcon#first serial, iclass 40, count 0 2006.239.07:53:17.95#ibcon#enter sib2, iclass 40, count 0 2006.239.07:53:17.95#ibcon#flushed, iclass 40, count 0 2006.239.07:53:17.95#ibcon#about to write, iclass 40, count 0 2006.239.07:53:17.95#ibcon#wrote, iclass 40, count 0 2006.239.07:53:17.95#ibcon#about to read 3, iclass 40, count 0 2006.239.07:53:18.00#ibcon#read 3, iclass 40, count 0 2006.239.07:53:18.00#ibcon#about to read 4, iclass 40, count 0 2006.239.07:53:18.00#ibcon#read 4, iclass 40, count 0 2006.239.07:53:18.00#ibcon#about to read 5, iclass 40, count 0 2006.239.07:53:18.00#ibcon#read 5, iclass 40, count 0 2006.239.07:53:18.00#ibcon#about to read 6, iclass 40, count 0 2006.239.07:53:18.00#ibcon#read 6, iclass 40, count 0 2006.239.07:53:18.00#ibcon#end of sib2, iclass 40, count 0 2006.239.07:53:18.00#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:53:18.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:53:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:53:18.00#ibcon#*before write, iclass 40, count 0 2006.239.07:53:18.00#ibcon#enter sib2, iclass 40, count 0 2006.239.07:53:18.00#ibcon#flushed, iclass 40, count 0 2006.239.07:53:18.00#ibcon#about to write, iclass 40, count 0 2006.239.07:53:18.00#ibcon#wrote, iclass 40, count 0 2006.239.07:53:18.00#ibcon#about to read 3, iclass 40, count 0 2006.239.07:53:18.04#ibcon#read 3, iclass 40, count 0 2006.239.07:53:18.04#ibcon#about to read 4, iclass 40, count 0 2006.239.07:53:18.04#ibcon#read 4, iclass 40, count 0 2006.239.07:53:18.04#ibcon#about to read 5, iclass 40, count 0 2006.239.07:53:18.04#ibcon#read 5, iclass 40, count 0 2006.239.07:53:18.04#ibcon#about to read 6, iclass 40, count 0 2006.239.07:53:18.04#ibcon#read 6, iclass 40, count 0 2006.239.07:53:18.04#ibcon#end of sib2, iclass 40, count 0 2006.239.07:53:18.04#ibcon#*after write, iclass 40, count 0 2006.239.07:53:18.04#ibcon#*before return 0, iclass 40, count 0 2006.239.07:53:18.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:18.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:18.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:53:18.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:53:18.04$vc4f8/va=1,8 2006.239.07:53:18.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:53:18.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:53:18.04#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:18.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:18.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:18.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:18.04#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:53:18.04#ibcon#first serial, iclass 4, count 2 2006.239.07:53:18.04#ibcon#enter sib2, iclass 4, count 2 2006.239.07:53:18.04#ibcon#flushed, iclass 4, count 2 2006.239.07:53:18.04#ibcon#about to write, iclass 4, count 2 2006.239.07:53:18.04#ibcon#wrote, iclass 4, count 2 2006.239.07:53:18.04#ibcon#about to read 3, iclass 4, count 2 2006.239.07:53:18.06#ibcon#read 3, iclass 4, count 2 2006.239.07:53:18.06#ibcon#about to read 4, iclass 4, count 2 2006.239.07:53:18.06#ibcon#read 4, iclass 4, count 2 2006.239.07:53:18.06#ibcon#about to read 5, iclass 4, count 2 2006.239.07:53:18.06#ibcon#read 5, iclass 4, count 2 2006.239.07:53:18.06#ibcon#about to read 6, iclass 4, count 2 2006.239.07:53:18.06#ibcon#read 6, iclass 4, count 2 2006.239.07:53:18.06#ibcon#end of sib2, iclass 4, count 2 2006.239.07:53:18.06#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:53:18.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:53:18.06#ibcon#[25=AT01-08\r\n] 2006.239.07:53:18.06#ibcon#*before write, iclass 4, count 2 2006.239.07:53:18.06#ibcon#enter sib2, iclass 4, count 2 2006.239.07:53:18.06#ibcon#flushed, iclass 4, count 2 2006.239.07:53:18.06#ibcon#about to write, iclass 4, count 2 2006.239.07:53:18.06#ibcon#wrote, iclass 4, count 2 2006.239.07:53:18.06#ibcon#about to read 3, iclass 4, count 2 2006.239.07:53:18.09#ibcon#read 3, iclass 4, count 2 2006.239.07:53:18.09#ibcon#about to read 4, iclass 4, count 2 2006.239.07:53:18.09#ibcon#read 4, iclass 4, count 2 2006.239.07:53:18.09#ibcon#about to read 5, iclass 4, count 2 2006.239.07:53:18.09#ibcon#read 5, iclass 4, count 2 2006.239.07:53:18.09#ibcon#about to read 6, iclass 4, count 2 2006.239.07:53:18.09#ibcon#read 6, iclass 4, count 2 2006.239.07:53:18.09#ibcon#end of sib2, iclass 4, count 2 2006.239.07:53:18.09#ibcon#*after write, iclass 4, count 2 2006.239.07:53:18.09#ibcon#*before return 0, iclass 4, count 2 2006.239.07:53:18.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:18.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:18.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:53:18.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:18.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:18.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:18.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:18.21#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:53:18.21#ibcon#first serial, iclass 4, count 0 2006.239.07:53:18.21#ibcon#enter sib2, iclass 4, count 0 2006.239.07:53:18.21#ibcon#flushed, iclass 4, count 0 2006.239.07:53:18.21#ibcon#about to write, iclass 4, count 0 2006.239.07:53:18.21#ibcon#wrote, iclass 4, count 0 2006.239.07:53:18.21#ibcon#about to read 3, iclass 4, count 0 2006.239.07:53:18.23#ibcon#read 3, iclass 4, count 0 2006.239.07:53:18.23#ibcon#about to read 4, iclass 4, count 0 2006.239.07:53:18.23#ibcon#read 4, iclass 4, count 0 2006.239.07:53:18.23#ibcon#about to read 5, iclass 4, count 0 2006.239.07:53:18.23#ibcon#read 5, iclass 4, count 0 2006.239.07:53:18.23#ibcon#about to read 6, iclass 4, count 0 2006.239.07:53:18.23#ibcon#read 6, iclass 4, count 0 2006.239.07:53:18.23#ibcon#end of sib2, iclass 4, count 0 2006.239.07:53:18.23#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:53:18.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:53:18.23#ibcon#[25=USB\r\n] 2006.239.07:53:18.23#ibcon#*before write, iclass 4, count 0 2006.239.07:53:18.23#ibcon#enter sib2, iclass 4, count 0 2006.239.07:53:18.23#ibcon#flushed, iclass 4, count 0 2006.239.07:53:18.23#ibcon#about to write, iclass 4, count 0 2006.239.07:53:18.23#ibcon#wrote, iclass 4, count 0 2006.239.07:53:18.23#ibcon#about to read 3, iclass 4, count 0 2006.239.07:53:18.26#ibcon#read 3, iclass 4, count 0 2006.239.07:53:18.26#ibcon#about to read 4, iclass 4, count 0 2006.239.07:53:18.26#ibcon#read 4, iclass 4, count 0 2006.239.07:53:18.26#ibcon#about to read 5, iclass 4, count 0 2006.239.07:53:18.26#ibcon#read 5, iclass 4, count 0 2006.239.07:53:18.26#ibcon#about to read 6, iclass 4, count 0 2006.239.07:53:18.26#ibcon#read 6, iclass 4, count 0 2006.239.07:53:18.26#ibcon#end of sib2, iclass 4, count 0 2006.239.07:53:18.26#ibcon#*after write, iclass 4, count 0 2006.239.07:53:18.26#ibcon#*before return 0, iclass 4, count 0 2006.239.07:53:18.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:18.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:18.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:53:18.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:53:18.26$vc4f8/valo=2,572.99 2006.239.07:53:18.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:53:18.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:53:18.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:18.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:18.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:18.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:18.26#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:53:18.26#ibcon#first serial, iclass 6, count 0 2006.239.07:53:18.26#ibcon#enter sib2, iclass 6, count 0 2006.239.07:53:18.26#ibcon#flushed, iclass 6, count 0 2006.239.07:53:18.26#ibcon#about to write, iclass 6, count 0 2006.239.07:53:18.26#ibcon#wrote, iclass 6, count 0 2006.239.07:53:18.26#ibcon#about to read 3, iclass 6, count 0 2006.239.07:53:18.28#ibcon#read 3, iclass 6, count 0 2006.239.07:53:18.28#ibcon#about to read 4, iclass 6, count 0 2006.239.07:53:18.28#ibcon#read 4, iclass 6, count 0 2006.239.07:53:18.28#ibcon#about to read 5, iclass 6, count 0 2006.239.07:53:18.28#ibcon#read 5, iclass 6, count 0 2006.239.07:53:18.28#ibcon#about to read 6, iclass 6, count 0 2006.239.07:53:18.28#ibcon#read 6, iclass 6, count 0 2006.239.07:53:18.28#ibcon#end of sib2, iclass 6, count 0 2006.239.07:53:18.28#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:53:18.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:53:18.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:53:18.28#ibcon#*before write, iclass 6, count 0 2006.239.07:53:18.28#ibcon#enter sib2, iclass 6, count 0 2006.239.07:53:18.28#ibcon#flushed, iclass 6, count 0 2006.239.07:53:18.28#ibcon#about to write, iclass 6, count 0 2006.239.07:53:18.28#ibcon#wrote, iclass 6, count 0 2006.239.07:53:18.28#ibcon#about to read 3, iclass 6, count 0 2006.239.07:53:18.32#ibcon#read 3, iclass 6, count 0 2006.239.07:53:18.32#ibcon#about to read 4, iclass 6, count 0 2006.239.07:53:18.32#ibcon#read 4, iclass 6, count 0 2006.239.07:53:18.32#ibcon#about to read 5, iclass 6, count 0 2006.239.07:53:18.32#ibcon#read 5, iclass 6, count 0 2006.239.07:53:18.32#ibcon#about to read 6, iclass 6, count 0 2006.239.07:53:18.32#ibcon#read 6, iclass 6, count 0 2006.239.07:53:18.32#ibcon#end of sib2, iclass 6, count 0 2006.239.07:53:18.32#ibcon#*after write, iclass 6, count 0 2006.239.07:53:18.32#ibcon#*before return 0, iclass 6, count 0 2006.239.07:53:18.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:18.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:18.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:53:18.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:53:18.32$vc4f8/va=2,7 2006.239.07:53:18.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:53:18.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:53:18.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:18.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:18.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:18.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:18.38#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:53:18.38#ibcon#first serial, iclass 10, count 2 2006.239.07:53:18.38#ibcon#enter sib2, iclass 10, count 2 2006.239.07:53:18.38#ibcon#flushed, iclass 10, count 2 2006.239.07:53:18.38#ibcon#about to write, iclass 10, count 2 2006.239.07:53:18.38#ibcon#wrote, iclass 10, count 2 2006.239.07:53:18.38#ibcon#about to read 3, iclass 10, count 2 2006.239.07:53:18.40#ibcon#read 3, iclass 10, count 2 2006.239.07:53:18.40#ibcon#about to read 4, iclass 10, count 2 2006.239.07:53:18.40#ibcon#read 4, iclass 10, count 2 2006.239.07:53:18.40#ibcon#about to read 5, iclass 10, count 2 2006.239.07:53:18.40#ibcon#read 5, iclass 10, count 2 2006.239.07:53:18.40#ibcon#about to read 6, iclass 10, count 2 2006.239.07:53:18.40#ibcon#read 6, iclass 10, count 2 2006.239.07:53:18.40#ibcon#end of sib2, iclass 10, count 2 2006.239.07:53:18.40#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:53:18.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:53:18.40#ibcon#[25=AT02-07\r\n] 2006.239.07:53:18.40#ibcon#*before write, iclass 10, count 2 2006.239.07:53:18.40#ibcon#enter sib2, iclass 10, count 2 2006.239.07:53:18.40#ibcon#flushed, iclass 10, count 2 2006.239.07:53:18.40#ibcon#about to write, iclass 10, count 2 2006.239.07:53:18.40#ibcon#wrote, iclass 10, count 2 2006.239.07:53:18.40#ibcon#about to read 3, iclass 10, count 2 2006.239.07:53:18.43#ibcon#read 3, iclass 10, count 2 2006.239.07:53:18.43#ibcon#about to read 4, iclass 10, count 2 2006.239.07:53:18.43#ibcon#read 4, iclass 10, count 2 2006.239.07:53:18.43#ibcon#about to read 5, iclass 10, count 2 2006.239.07:53:18.43#ibcon#read 5, iclass 10, count 2 2006.239.07:53:18.43#ibcon#about to read 6, iclass 10, count 2 2006.239.07:53:18.43#ibcon#read 6, iclass 10, count 2 2006.239.07:53:18.43#ibcon#end of sib2, iclass 10, count 2 2006.239.07:53:18.43#ibcon#*after write, iclass 10, count 2 2006.239.07:53:18.43#ibcon#*before return 0, iclass 10, count 2 2006.239.07:53:18.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:18.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:18.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:53:18.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:18.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:18.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:18.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:18.55#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:53:18.55#ibcon#first serial, iclass 10, count 0 2006.239.07:53:18.55#ibcon#enter sib2, iclass 10, count 0 2006.239.07:53:18.55#ibcon#flushed, iclass 10, count 0 2006.239.07:53:18.55#ibcon#about to write, iclass 10, count 0 2006.239.07:53:18.55#ibcon#wrote, iclass 10, count 0 2006.239.07:53:18.55#ibcon#about to read 3, iclass 10, count 0 2006.239.07:53:18.57#ibcon#read 3, iclass 10, count 0 2006.239.07:53:18.57#ibcon#about to read 4, iclass 10, count 0 2006.239.07:53:18.57#ibcon#read 4, iclass 10, count 0 2006.239.07:53:18.57#ibcon#about to read 5, iclass 10, count 0 2006.239.07:53:18.57#ibcon#read 5, iclass 10, count 0 2006.239.07:53:18.57#ibcon#about to read 6, iclass 10, count 0 2006.239.07:53:18.57#ibcon#read 6, iclass 10, count 0 2006.239.07:53:18.57#ibcon#end of sib2, iclass 10, count 0 2006.239.07:53:18.57#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:53:18.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:53:18.57#ibcon#[25=USB\r\n] 2006.239.07:53:18.57#ibcon#*before write, iclass 10, count 0 2006.239.07:53:18.57#ibcon#enter sib2, iclass 10, count 0 2006.239.07:53:18.57#ibcon#flushed, iclass 10, count 0 2006.239.07:53:18.57#ibcon#about to write, iclass 10, count 0 2006.239.07:53:18.57#ibcon#wrote, iclass 10, count 0 2006.239.07:53:18.57#ibcon#about to read 3, iclass 10, count 0 2006.239.07:53:18.60#ibcon#read 3, iclass 10, count 0 2006.239.07:53:18.60#ibcon#about to read 4, iclass 10, count 0 2006.239.07:53:18.60#ibcon#read 4, iclass 10, count 0 2006.239.07:53:18.60#ibcon#about to read 5, iclass 10, count 0 2006.239.07:53:18.60#ibcon#read 5, iclass 10, count 0 2006.239.07:53:18.60#ibcon#about to read 6, iclass 10, count 0 2006.239.07:53:18.60#ibcon#read 6, iclass 10, count 0 2006.239.07:53:18.60#ibcon#end of sib2, iclass 10, count 0 2006.239.07:53:18.60#ibcon#*after write, iclass 10, count 0 2006.239.07:53:18.60#ibcon#*before return 0, iclass 10, count 0 2006.239.07:53:18.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:18.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:18.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:53:18.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:53:18.60$vc4f8/valo=3,672.99 2006.239.07:53:18.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:53:18.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:53:18.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:18.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:18.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:18.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:18.60#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:53:18.60#ibcon#first serial, iclass 12, count 0 2006.239.07:53:18.60#ibcon#enter sib2, iclass 12, count 0 2006.239.07:53:18.60#ibcon#flushed, iclass 12, count 0 2006.239.07:53:18.60#ibcon#about to write, iclass 12, count 0 2006.239.07:53:18.60#ibcon#wrote, iclass 12, count 0 2006.239.07:53:18.60#ibcon#about to read 3, iclass 12, count 0 2006.239.07:53:18.62#ibcon#read 3, iclass 12, count 0 2006.239.07:53:18.62#ibcon#about to read 4, iclass 12, count 0 2006.239.07:53:18.62#ibcon#read 4, iclass 12, count 0 2006.239.07:53:18.62#ibcon#about to read 5, iclass 12, count 0 2006.239.07:53:18.62#ibcon#read 5, iclass 12, count 0 2006.239.07:53:18.62#ibcon#about to read 6, iclass 12, count 0 2006.239.07:53:18.62#ibcon#read 6, iclass 12, count 0 2006.239.07:53:18.62#ibcon#end of sib2, iclass 12, count 0 2006.239.07:53:18.62#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:53:18.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:53:18.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:53:18.62#ibcon#*before write, iclass 12, count 0 2006.239.07:53:18.62#ibcon#enter sib2, iclass 12, count 0 2006.239.07:53:18.62#ibcon#flushed, iclass 12, count 0 2006.239.07:53:18.62#ibcon#about to write, iclass 12, count 0 2006.239.07:53:18.62#ibcon#wrote, iclass 12, count 0 2006.239.07:53:18.62#ibcon#about to read 3, iclass 12, count 0 2006.239.07:53:18.66#ibcon#read 3, iclass 12, count 0 2006.239.07:53:18.66#ibcon#about to read 4, iclass 12, count 0 2006.239.07:53:18.66#ibcon#read 4, iclass 12, count 0 2006.239.07:53:18.66#ibcon#about to read 5, iclass 12, count 0 2006.239.07:53:18.66#ibcon#read 5, iclass 12, count 0 2006.239.07:53:18.66#ibcon#about to read 6, iclass 12, count 0 2006.239.07:53:18.66#ibcon#read 6, iclass 12, count 0 2006.239.07:53:18.66#ibcon#end of sib2, iclass 12, count 0 2006.239.07:53:18.66#ibcon#*after write, iclass 12, count 0 2006.239.07:53:18.66#ibcon#*before return 0, iclass 12, count 0 2006.239.07:53:18.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:18.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:18.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:53:18.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:53:18.66$vc4f8/va=3,7 2006.239.07:53:18.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.07:53:18.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.07:53:18.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:18.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:18.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:18.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:18.72#ibcon#enter wrdev, iclass 14, count 2 2006.239.07:53:18.72#ibcon#first serial, iclass 14, count 2 2006.239.07:53:18.72#ibcon#enter sib2, iclass 14, count 2 2006.239.07:53:18.72#ibcon#flushed, iclass 14, count 2 2006.239.07:53:18.72#ibcon#about to write, iclass 14, count 2 2006.239.07:53:18.72#ibcon#wrote, iclass 14, count 2 2006.239.07:53:18.72#ibcon#about to read 3, iclass 14, count 2 2006.239.07:53:18.74#ibcon#read 3, iclass 14, count 2 2006.239.07:53:18.74#ibcon#about to read 4, iclass 14, count 2 2006.239.07:53:18.74#ibcon#read 4, iclass 14, count 2 2006.239.07:53:18.74#ibcon#about to read 5, iclass 14, count 2 2006.239.07:53:18.74#ibcon#read 5, iclass 14, count 2 2006.239.07:53:18.74#ibcon#about to read 6, iclass 14, count 2 2006.239.07:53:18.74#ibcon#read 6, iclass 14, count 2 2006.239.07:53:18.74#ibcon#end of sib2, iclass 14, count 2 2006.239.07:53:18.74#ibcon#*mode == 0, iclass 14, count 2 2006.239.07:53:18.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.07:53:18.74#ibcon#[25=AT03-07\r\n] 2006.239.07:53:18.74#ibcon#*before write, iclass 14, count 2 2006.239.07:53:18.74#ibcon#enter sib2, iclass 14, count 2 2006.239.07:53:18.74#ibcon#flushed, iclass 14, count 2 2006.239.07:53:18.74#ibcon#about to write, iclass 14, count 2 2006.239.07:53:18.74#ibcon#wrote, iclass 14, count 2 2006.239.07:53:18.74#ibcon#about to read 3, iclass 14, count 2 2006.239.07:53:18.77#ibcon#read 3, iclass 14, count 2 2006.239.07:53:18.78#ibcon#about to read 4, iclass 14, count 2 2006.239.07:53:18.78#ibcon#read 4, iclass 14, count 2 2006.239.07:53:18.78#ibcon#about to read 5, iclass 14, count 2 2006.239.07:53:18.78#ibcon#read 5, iclass 14, count 2 2006.239.07:53:18.78#ibcon#about to read 6, iclass 14, count 2 2006.239.07:53:18.78#ibcon#read 6, iclass 14, count 2 2006.239.07:53:18.78#ibcon#end of sib2, iclass 14, count 2 2006.239.07:53:18.78#ibcon#*after write, iclass 14, count 2 2006.239.07:53:18.78#ibcon#*before return 0, iclass 14, count 2 2006.239.07:53:18.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:18.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:18.78#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.07:53:18.78#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:18.78#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:18.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:18.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:18.89#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:53:18.89#ibcon#first serial, iclass 14, count 0 2006.239.07:53:18.89#ibcon#enter sib2, iclass 14, count 0 2006.239.07:53:18.89#ibcon#flushed, iclass 14, count 0 2006.239.07:53:18.89#ibcon#about to write, iclass 14, count 0 2006.239.07:53:18.89#ibcon#wrote, iclass 14, count 0 2006.239.07:53:18.89#ibcon#about to read 3, iclass 14, count 0 2006.239.07:53:18.91#ibcon#read 3, iclass 14, count 0 2006.239.07:53:18.91#ibcon#about to read 4, iclass 14, count 0 2006.239.07:53:18.91#ibcon#read 4, iclass 14, count 0 2006.239.07:53:18.91#ibcon#about to read 5, iclass 14, count 0 2006.239.07:53:18.91#ibcon#read 5, iclass 14, count 0 2006.239.07:53:18.91#ibcon#about to read 6, iclass 14, count 0 2006.239.07:53:18.91#ibcon#read 6, iclass 14, count 0 2006.239.07:53:18.91#ibcon#end of sib2, iclass 14, count 0 2006.239.07:53:18.91#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:53:18.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:53:18.91#ibcon#[25=USB\r\n] 2006.239.07:53:18.91#ibcon#*before write, iclass 14, count 0 2006.239.07:53:18.91#ibcon#enter sib2, iclass 14, count 0 2006.239.07:53:18.91#ibcon#flushed, iclass 14, count 0 2006.239.07:53:18.91#ibcon#about to write, iclass 14, count 0 2006.239.07:53:18.91#ibcon#wrote, iclass 14, count 0 2006.239.07:53:18.91#ibcon#about to read 3, iclass 14, count 0 2006.239.07:53:18.94#ibcon#read 3, iclass 14, count 0 2006.239.07:53:18.94#ibcon#about to read 4, iclass 14, count 0 2006.239.07:53:18.94#ibcon#read 4, iclass 14, count 0 2006.239.07:53:18.94#ibcon#about to read 5, iclass 14, count 0 2006.239.07:53:18.94#ibcon#read 5, iclass 14, count 0 2006.239.07:53:18.94#ibcon#about to read 6, iclass 14, count 0 2006.239.07:53:18.94#ibcon#read 6, iclass 14, count 0 2006.239.07:53:18.94#ibcon#end of sib2, iclass 14, count 0 2006.239.07:53:18.94#ibcon#*after write, iclass 14, count 0 2006.239.07:53:18.94#ibcon#*before return 0, iclass 14, count 0 2006.239.07:53:18.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:18.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:18.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:53:18.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:53:18.94$vc4f8/valo=4,832.99 2006.239.07:53:18.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:53:18.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:53:18.94#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:18.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:18.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:18.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:18.94#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:53:18.94#ibcon#first serial, iclass 16, count 0 2006.239.07:53:18.94#ibcon#enter sib2, iclass 16, count 0 2006.239.07:53:18.94#ibcon#flushed, iclass 16, count 0 2006.239.07:53:18.94#ibcon#about to write, iclass 16, count 0 2006.239.07:53:18.94#ibcon#wrote, iclass 16, count 0 2006.239.07:53:18.94#ibcon#about to read 3, iclass 16, count 0 2006.239.07:53:18.96#ibcon#read 3, iclass 16, count 0 2006.239.07:53:18.96#ibcon#about to read 4, iclass 16, count 0 2006.239.07:53:18.96#ibcon#read 4, iclass 16, count 0 2006.239.07:53:18.96#ibcon#about to read 5, iclass 16, count 0 2006.239.07:53:18.96#ibcon#read 5, iclass 16, count 0 2006.239.07:53:18.96#ibcon#about to read 6, iclass 16, count 0 2006.239.07:53:18.96#ibcon#read 6, iclass 16, count 0 2006.239.07:53:18.96#ibcon#end of sib2, iclass 16, count 0 2006.239.07:53:18.96#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:53:18.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:53:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:53:18.96#ibcon#*before write, iclass 16, count 0 2006.239.07:53:18.96#ibcon#enter sib2, iclass 16, count 0 2006.239.07:53:18.96#ibcon#flushed, iclass 16, count 0 2006.239.07:53:18.96#ibcon#about to write, iclass 16, count 0 2006.239.07:53:18.96#ibcon#wrote, iclass 16, count 0 2006.239.07:53:18.96#ibcon#about to read 3, iclass 16, count 0 2006.239.07:53:19.00#ibcon#read 3, iclass 16, count 0 2006.239.07:53:19.00#ibcon#about to read 4, iclass 16, count 0 2006.239.07:53:19.00#ibcon#read 4, iclass 16, count 0 2006.239.07:53:19.00#ibcon#about to read 5, iclass 16, count 0 2006.239.07:53:19.00#ibcon#read 5, iclass 16, count 0 2006.239.07:53:19.00#ibcon#about to read 6, iclass 16, count 0 2006.239.07:53:19.00#ibcon#read 6, iclass 16, count 0 2006.239.07:53:19.00#ibcon#end of sib2, iclass 16, count 0 2006.239.07:53:19.00#ibcon#*after write, iclass 16, count 0 2006.239.07:53:19.00#ibcon#*before return 0, iclass 16, count 0 2006.239.07:53:19.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:19.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:19.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:53:19.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:53:19.00$vc4f8/va=4,7 2006.239.07:53:19.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:53:19.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:53:19.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:19.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:19.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:19.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:19.06#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:53:19.06#ibcon#first serial, iclass 18, count 2 2006.239.07:53:19.06#ibcon#enter sib2, iclass 18, count 2 2006.239.07:53:19.06#ibcon#flushed, iclass 18, count 2 2006.239.07:53:19.06#ibcon#about to write, iclass 18, count 2 2006.239.07:53:19.06#ibcon#wrote, iclass 18, count 2 2006.239.07:53:19.06#ibcon#about to read 3, iclass 18, count 2 2006.239.07:53:19.08#ibcon#read 3, iclass 18, count 2 2006.239.07:53:19.08#ibcon#about to read 4, iclass 18, count 2 2006.239.07:53:19.08#ibcon#read 4, iclass 18, count 2 2006.239.07:53:19.08#ibcon#about to read 5, iclass 18, count 2 2006.239.07:53:19.08#ibcon#read 5, iclass 18, count 2 2006.239.07:53:19.08#ibcon#about to read 6, iclass 18, count 2 2006.239.07:53:19.08#ibcon#read 6, iclass 18, count 2 2006.239.07:53:19.08#ibcon#end of sib2, iclass 18, count 2 2006.239.07:53:19.08#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:53:19.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:53:19.08#ibcon#[25=AT04-07\r\n] 2006.239.07:53:19.08#ibcon#*before write, iclass 18, count 2 2006.239.07:53:19.08#ibcon#enter sib2, iclass 18, count 2 2006.239.07:53:19.08#ibcon#flushed, iclass 18, count 2 2006.239.07:53:19.08#ibcon#about to write, iclass 18, count 2 2006.239.07:53:19.08#ibcon#wrote, iclass 18, count 2 2006.239.07:53:19.08#ibcon#about to read 3, iclass 18, count 2 2006.239.07:53:19.11#ibcon#read 3, iclass 18, count 2 2006.239.07:53:19.11#ibcon#about to read 4, iclass 18, count 2 2006.239.07:53:19.11#ibcon#read 4, iclass 18, count 2 2006.239.07:53:19.11#ibcon#about to read 5, iclass 18, count 2 2006.239.07:53:19.11#ibcon#read 5, iclass 18, count 2 2006.239.07:53:19.11#ibcon#about to read 6, iclass 18, count 2 2006.239.07:53:19.11#ibcon#read 6, iclass 18, count 2 2006.239.07:53:19.11#ibcon#end of sib2, iclass 18, count 2 2006.239.07:53:19.11#ibcon#*after write, iclass 18, count 2 2006.239.07:53:19.11#ibcon#*before return 0, iclass 18, count 2 2006.239.07:53:19.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:19.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:19.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:53:19.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:19.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:19.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:19.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:19.23#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:53:19.23#ibcon#first serial, iclass 18, count 0 2006.239.07:53:19.23#ibcon#enter sib2, iclass 18, count 0 2006.239.07:53:19.23#ibcon#flushed, iclass 18, count 0 2006.239.07:53:19.23#ibcon#about to write, iclass 18, count 0 2006.239.07:53:19.23#ibcon#wrote, iclass 18, count 0 2006.239.07:53:19.23#ibcon#about to read 3, iclass 18, count 0 2006.239.07:53:19.25#ibcon#read 3, iclass 18, count 0 2006.239.07:53:19.25#ibcon#about to read 4, iclass 18, count 0 2006.239.07:53:19.25#ibcon#read 4, iclass 18, count 0 2006.239.07:53:19.25#ibcon#about to read 5, iclass 18, count 0 2006.239.07:53:19.25#ibcon#read 5, iclass 18, count 0 2006.239.07:53:19.25#ibcon#about to read 6, iclass 18, count 0 2006.239.07:53:19.25#ibcon#read 6, iclass 18, count 0 2006.239.07:53:19.25#ibcon#end of sib2, iclass 18, count 0 2006.239.07:53:19.25#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:53:19.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:53:19.25#ibcon#[25=USB\r\n] 2006.239.07:53:19.25#ibcon#*before write, iclass 18, count 0 2006.239.07:53:19.25#ibcon#enter sib2, iclass 18, count 0 2006.239.07:53:19.25#ibcon#flushed, iclass 18, count 0 2006.239.07:53:19.25#ibcon#about to write, iclass 18, count 0 2006.239.07:53:19.25#ibcon#wrote, iclass 18, count 0 2006.239.07:53:19.25#ibcon#about to read 3, iclass 18, count 0 2006.239.07:53:19.28#ibcon#read 3, iclass 18, count 0 2006.239.07:53:19.28#ibcon#about to read 4, iclass 18, count 0 2006.239.07:53:19.28#ibcon#read 4, iclass 18, count 0 2006.239.07:53:19.28#ibcon#about to read 5, iclass 18, count 0 2006.239.07:53:19.28#ibcon#read 5, iclass 18, count 0 2006.239.07:53:19.28#ibcon#about to read 6, iclass 18, count 0 2006.239.07:53:19.28#ibcon#read 6, iclass 18, count 0 2006.239.07:53:19.28#ibcon#end of sib2, iclass 18, count 0 2006.239.07:53:19.28#ibcon#*after write, iclass 18, count 0 2006.239.07:53:19.28#ibcon#*before return 0, iclass 18, count 0 2006.239.07:53:19.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:19.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:19.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:53:19.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:53:19.28$vc4f8/valo=5,652.99 2006.239.07:53:19.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:53:19.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:53:19.28#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:19.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:19.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:19.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:19.28#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:53:19.28#ibcon#first serial, iclass 20, count 0 2006.239.07:53:19.28#ibcon#enter sib2, iclass 20, count 0 2006.239.07:53:19.28#ibcon#flushed, iclass 20, count 0 2006.239.07:53:19.28#ibcon#about to write, iclass 20, count 0 2006.239.07:53:19.28#ibcon#wrote, iclass 20, count 0 2006.239.07:53:19.28#ibcon#about to read 3, iclass 20, count 0 2006.239.07:53:19.30#ibcon#read 3, iclass 20, count 0 2006.239.07:53:19.30#ibcon#about to read 4, iclass 20, count 0 2006.239.07:53:19.30#ibcon#read 4, iclass 20, count 0 2006.239.07:53:19.30#ibcon#about to read 5, iclass 20, count 0 2006.239.07:53:19.30#ibcon#read 5, iclass 20, count 0 2006.239.07:53:19.30#ibcon#about to read 6, iclass 20, count 0 2006.239.07:53:19.30#ibcon#read 6, iclass 20, count 0 2006.239.07:53:19.30#ibcon#end of sib2, iclass 20, count 0 2006.239.07:53:19.30#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:53:19.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:53:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:53:19.30#ibcon#*before write, iclass 20, count 0 2006.239.07:53:19.30#ibcon#enter sib2, iclass 20, count 0 2006.239.07:53:19.30#ibcon#flushed, iclass 20, count 0 2006.239.07:53:19.30#ibcon#about to write, iclass 20, count 0 2006.239.07:53:19.30#ibcon#wrote, iclass 20, count 0 2006.239.07:53:19.30#ibcon#about to read 3, iclass 20, count 0 2006.239.07:53:19.34#ibcon#read 3, iclass 20, count 0 2006.239.07:53:19.34#ibcon#about to read 4, iclass 20, count 0 2006.239.07:53:19.34#ibcon#read 4, iclass 20, count 0 2006.239.07:53:19.34#ibcon#about to read 5, iclass 20, count 0 2006.239.07:53:19.34#ibcon#read 5, iclass 20, count 0 2006.239.07:53:19.34#ibcon#about to read 6, iclass 20, count 0 2006.239.07:53:19.34#ibcon#read 6, iclass 20, count 0 2006.239.07:53:19.34#ibcon#end of sib2, iclass 20, count 0 2006.239.07:53:19.34#ibcon#*after write, iclass 20, count 0 2006.239.07:53:19.34#ibcon#*before return 0, iclass 20, count 0 2006.239.07:53:19.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:19.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:19.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:53:19.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:53:19.34$vc4f8/va=5,8 2006.239.07:53:19.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:53:19.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:53:19.34#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:19.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:19.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:19.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:19.40#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:53:19.40#ibcon#first serial, iclass 22, count 2 2006.239.07:53:19.40#ibcon#enter sib2, iclass 22, count 2 2006.239.07:53:19.40#ibcon#flushed, iclass 22, count 2 2006.239.07:53:19.40#ibcon#about to write, iclass 22, count 2 2006.239.07:53:19.40#ibcon#wrote, iclass 22, count 2 2006.239.07:53:19.40#ibcon#about to read 3, iclass 22, count 2 2006.239.07:53:19.42#ibcon#read 3, iclass 22, count 2 2006.239.07:53:19.42#ibcon#about to read 4, iclass 22, count 2 2006.239.07:53:19.42#ibcon#read 4, iclass 22, count 2 2006.239.07:53:19.42#ibcon#about to read 5, iclass 22, count 2 2006.239.07:53:19.42#ibcon#read 5, iclass 22, count 2 2006.239.07:53:19.42#ibcon#about to read 6, iclass 22, count 2 2006.239.07:53:19.42#ibcon#read 6, iclass 22, count 2 2006.239.07:53:19.42#ibcon#end of sib2, iclass 22, count 2 2006.239.07:53:19.42#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:53:19.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:53:19.42#ibcon#[25=AT05-08\r\n] 2006.239.07:53:19.42#ibcon#*before write, iclass 22, count 2 2006.239.07:53:19.42#ibcon#enter sib2, iclass 22, count 2 2006.239.07:53:19.42#ibcon#flushed, iclass 22, count 2 2006.239.07:53:19.42#ibcon#about to write, iclass 22, count 2 2006.239.07:53:19.42#ibcon#wrote, iclass 22, count 2 2006.239.07:53:19.42#ibcon#about to read 3, iclass 22, count 2 2006.239.07:53:19.45#ibcon#read 3, iclass 22, count 2 2006.239.07:53:19.45#ibcon#about to read 4, iclass 22, count 2 2006.239.07:53:19.45#ibcon#read 4, iclass 22, count 2 2006.239.07:53:19.45#ibcon#about to read 5, iclass 22, count 2 2006.239.07:53:19.45#ibcon#read 5, iclass 22, count 2 2006.239.07:53:19.45#ibcon#about to read 6, iclass 22, count 2 2006.239.07:53:19.45#ibcon#read 6, iclass 22, count 2 2006.239.07:53:19.45#ibcon#end of sib2, iclass 22, count 2 2006.239.07:53:19.45#ibcon#*after write, iclass 22, count 2 2006.239.07:53:19.45#ibcon#*before return 0, iclass 22, count 2 2006.239.07:53:19.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:19.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:19.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:53:19.45#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:19.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:19.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:19.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:19.57#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:53:19.57#ibcon#first serial, iclass 22, count 0 2006.239.07:53:19.57#ibcon#enter sib2, iclass 22, count 0 2006.239.07:53:19.57#ibcon#flushed, iclass 22, count 0 2006.239.07:53:19.57#ibcon#about to write, iclass 22, count 0 2006.239.07:53:19.57#ibcon#wrote, iclass 22, count 0 2006.239.07:53:19.57#ibcon#about to read 3, iclass 22, count 0 2006.239.07:53:19.59#ibcon#read 3, iclass 22, count 0 2006.239.07:53:19.59#ibcon#about to read 4, iclass 22, count 0 2006.239.07:53:19.59#ibcon#read 4, iclass 22, count 0 2006.239.07:53:19.59#ibcon#about to read 5, iclass 22, count 0 2006.239.07:53:19.59#ibcon#read 5, iclass 22, count 0 2006.239.07:53:19.59#ibcon#about to read 6, iclass 22, count 0 2006.239.07:53:19.59#ibcon#read 6, iclass 22, count 0 2006.239.07:53:19.59#ibcon#end of sib2, iclass 22, count 0 2006.239.07:53:19.59#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:53:19.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:53:19.59#ibcon#[25=USB\r\n] 2006.239.07:53:19.59#ibcon#*before write, iclass 22, count 0 2006.239.07:53:19.59#ibcon#enter sib2, iclass 22, count 0 2006.239.07:53:19.59#ibcon#flushed, iclass 22, count 0 2006.239.07:53:19.59#ibcon#about to write, iclass 22, count 0 2006.239.07:53:19.59#ibcon#wrote, iclass 22, count 0 2006.239.07:53:19.59#ibcon#about to read 3, iclass 22, count 0 2006.239.07:53:19.62#ibcon#read 3, iclass 22, count 0 2006.239.07:53:19.62#ibcon#about to read 4, iclass 22, count 0 2006.239.07:53:19.62#ibcon#read 4, iclass 22, count 0 2006.239.07:53:19.62#ibcon#about to read 5, iclass 22, count 0 2006.239.07:53:19.62#ibcon#read 5, iclass 22, count 0 2006.239.07:53:19.62#ibcon#about to read 6, iclass 22, count 0 2006.239.07:53:19.62#ibcon#read 6, iclass 22, count 0 2006.239.07:53:19.62#ibcon#end of sib2, iclass 22, count 0 2006.239.07:53:19.62#ibcon#*after write, iclass 22, count 0 2006.239.07:53:19.62#ibcon#*before return 0, iclass 22, count 0 2006.239.07:53:19.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:19.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:19.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:53:19.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:53:19.62$vc4f8/valo=6,772.99 2006.239.07:53:19.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:53:19.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:53:19.62#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:19.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:19.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:19.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:19.62#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:53:19.62#ibcon#first serial, iclass 24, count 0 2006.239.07:53:19.62#ibcon#enter sib2, iclass 24, count 0 2006.239.07:53:19.62#ibcon#flushed, iclass 24, count 0 2006.239.07:53:19.62#ibcon#about to write, iclass 24, count 0 2006.239.07:53:19.62#ibcon#wrote, iclass 24, count 0 2006.239.07:53:19.62#ibcon#about to read 3, iclass 24, count 0 2006.239.07:53:19.64#ibcon#read 3, iclass 24, count 0 2006.239.07:53:19.64#ibcon#about to read 4, iclass 24, count 0 2006.239.07:53:19.64#ibcon#read 4, iclass 24, count 0 2006.239.07:53:19.64#ibcon#about to read 5, iclass 24, count 0 2006.239.07:53:19.64#ibcon#read 5, iclass 24, count 0 2006.239.07:53:19.64#ibcon#about to read 6, iclass 24, count 0 2006.239.07:53:19.64#ibcon#read 6, iclass 24, count 0 2006.239.07:53:19.64#ibcon#end of sib2, iclass 24, count 0 2006.239.07:53:19.64#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:53:19.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:53:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:53:19.64#ibcon#*before write, iclass 24, count 0 2006.239.07:53:19.64#ibcon#enter sib2, iclass 24, count 0 2006.239.07:53:19.64#ibcon#flushed, iclass 24, count 0 2006.239.07:53:19.64#ibcon#about to write, iclass 24, count 0 2006.239.07:53:19.64#ibcon#wrote, iclass 24, count 0 2006.239.07:53:19.64#ibcon#about to read 3, iclass 24, count 0 2006.239.07:53:19.68#ibcon#read 3, iclass 24, count 0 2006.239.07:53:19.68#ibcon#about to read 4, iclass 24, count 0 2006.239.07:53:19.68#ibcon#read 4, iclass 24, count 0 2006.239.07:53:19.68#ibcon#about to read 5, iclass 24, count 0 2006.239.07:53:19.68#ibcon#read 5, iclass 24, count 0 2006.239.07:53:19.68#ibcon#about to read 6, iclass 24, count 0 2006.239.07:53:19.68#ibcon#read 6, iclass 24, count 0 2006.239.07:53:19.68#ibcon#end of sib2, iclass 24, count 0 2006.239.07:53:19.68#ibcon#*after write, iclass 24, count 0 2006.239.07:53:19.68#ibcon#*before return 0, iclass 24, count 0 2006.239.07:53:19.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:19.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:19.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:53:19.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:53:19.68$vc4f8/va=6,7 2006.239.07:53:19.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.07:53:19.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.07:53:19.68#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:19.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:53:19.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:53:19.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:53:19.74#ibcon#enter wrdev, iclass 26, count 2 2006.239.07:53:19.74#ibcon#first serial, iclass 26, count 2 2006.239.07:53:19.74#ibcon#enter sib2, iclass 26, count 2 2006.239.07:53:19.74#ibcon#flushed, iclass 26, count 2 2006.239.07:53:19.74#ibcon#about to write, iclass 26, count 2 2006.239.07:53:19.74#ibcon#wrote, iclass 26, count 2 2006.239.07:53:19.74#ibcon#about to read 3, iclass 26, count 2 2006.239.07:53:19.76#ibcon#read 3, iclass 26, count 2 2006.239.07:53:19.76#ibcon#about to read 4, iclass 26, count 2 2006.239.07:53:19.76#ibcon#read 4, iclass 26, count 2 2006.239.07:53:19.76#ibcon#about to read 5, iclass 26, count 2 2006.239.07:53:19.76#ibcon#read 5, iclass 26, count 2 2006.239.07:53:19.76#ibcon#about to read 6, iclass 26, count 2 2006.239.07:53:19.76#ibcon#read 6, iclass 26, count 2 2006.239.07:53:19.76#ibcon#end of sib2, iclass 26, count 2 2006.239.07:53:19.76#ibcon#*mode == 0, iclass 26, count 2 2006.239.07:53:19.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.07:53:19.76#ibcon#[25=AT06-07\r\n] 2006.239.07:53:19.76#ibcon#*before write, iclass 26, count 2 2006.239.07:53:19.76#ibcon#enter sib2, iclass 26, count 2 2006.239.07:53:19.76#ibcon#flushed, iclass 26, count 2 2006.239.07:53:19.76#ibcon#about to write, iclass 26, count 2 2006.239.07:53:19.76#ibcon#wrote, iclass 26, count 2 2006.239.07:53:19.76#ibcon#about to read 3, iclass 26, count 2 2006.239.07:53:19.79#ibcon#read 3, iclass 26, count 2 2006.239.07:53:19.79#ibcon#about to read 4, iclass 26, count 2 2006.239.07:53:19.79#ibcon#read 4, iclass 26, count 2 2006.239.07:53:19.79#ibcon#about to read 5, iclass 26, count 2 2006.239.07:53:19.79#ibcon#read 5, iclass 26, count 2 2006.239.07:53:19.79#ibcon#about to read 6, iclass 26, count 2 2006.239.07:53:19.79#ibcon#read 6, iclass 26, count 2 2006.239.07:53:19.79#ibcon#end of sib2, iclass 26, count 2 2006.239.07:53:19.79#ibcon#*after write, iclass 26, count 2 2006.239.07:53:19.79#ibcon#*before return 0, iclass 26, count 2 2006.239.07:53:19.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:53:19.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.07:53:19.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.07:53:19.79#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:19.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:53:19.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:53:19.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:53:19.91#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:53:19.91#ibcon#first serial, iclass 26, count 0 2006.239.07:53:19.91#ibcon#enter sib2, iclass 26, count 0 2006.239.07:53:19.91#ibcon#flushed, iclass 26, count 0 2006.239.07:53:19.91#ibcon#about to write, iclass 26, count 0 2006.239.07:53:19.91#ibcon#wrote, iclass 26, count 0 2006.239.07:53:19.91#ibcon#about to read 3, iclass 26, count 0 2006.239.07:53:19.93#ibcon#read 3, iclass 26, count 0 2006.239.07:53:19.93#ibcon#about to read 4, iclass 26, count 0 2006.239.07:53:19.93#ibcon#read 4, iclass 26, count 0 2006.239.07:53:19.93#ibcon#about to read 5, iclass 26, count 0 2006.239.07:53:19.93#ibcon#read 5, iclass 26, count 0 2006.239.07:53:19.93#ibcon#about to read 6, iclass 26, count 0 2006.239.07:53:19.93#ibcon#read 6, iclass 26, count 0 2006.239.07:53:19.93#ibcon#end of sib2, iclass 26, count 0 2006.239.07:53:19.93#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:53:19.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:53:19.93#ibcon#[25=USB\r\n] 2006.239.07:53:19.93#ibcon#*before write, iclass 26, count 0 2006.239.07:53:19.93#ibcon#enter sib2, iclass 26, count 0 2006.239.07:53:19.93#ibcon#flushed, iclass 26, count 0 2006.239.07:53:19.93#ibcon#about to write, iclass 26, count 0 2006.239.07:53:19.93#ibcon#wrote, iclass 26, count 0 2006.239.07:53:19.93#ibcon#about to read 3, iclass 26, count 0 2006.239.07:53:19.96#ibcon#read 3, iclass 26, count 0 2006.239.07:53:19.96#ibcon#about to read 4, iclass 26, count 0 2006.239.07:53:19.96#ibcon#read 4, iclass 26, count 0 2006.239.07:53:19.96#ibcon#about to read 5, iclass 26, count 0 2006.239.07:53:19.96#ibcon#read 5, iclass 26, count 0 2006.239.07:53:19.96#ibcon#about to read 6, iclass 26, count 0 2006.239.07:53:19.96#ibcon#read 6, iclass 26, count 0 2006.239.07:53:19.96#ibcon#end of sib2, iclass 26, count 0 2006.239.07:53:19.96#ibcon#*after write, iclass 26, count 0 2006.239.07:53:19.96#ibcon#*before return 0, iclass 26, count 0 2006.239.07:53:19.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:53:19.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.07:53:19.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:53:19.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:53:19.96$vc4f8/valo=7,832.99 2006.239.07:53:19.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.07:53:19.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.07:53:19.96#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:19.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:53:19.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:53:19.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:53:19.96#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:53:19.96#ibcon#first serial, iclass 28, count 0 2006.239.07:53:19.96#ibcon#enter sib2, iclass 28, count 0 2006.239.07:53:19.96#ibcon#flushed, iclass 28, count 0 2006.239.07:53:19.96#ibcon#about to write, iclass 28, count 0 2006.239.07:53:19.96#ibcon#wrote, iclass 28, count 0 2006.239.07:53:19.96#ibcon#about to read 3, iclass 28, count 0 2006.239.07:53:19.98#ibcon#read 3, iclass 28, count 0 2006.239.07:53:19.98#ibcon#about to read 4, iclass 28, count 0 2006.239.07:53:19.98#ibcon#read 4, iclass 28, count 0 2006.239.07:53:19.98#ibcon#about to read 5, iclass 28, count 0 2006.239.07:53:19.98#ibcon#read 5, iclass 28, count 0 2006.239.07:53:19.98#ibcon#about to read 6, iclass 28, count 0 2006.239.07:53:19.98#ibcon#read 6, iclass 28, count 0 2006.239.07:53:19.98#ibcon#end of sib2, iclass 28, count 0 2006.239.07:53:19.98#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:53:19.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:53:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:53:19.98#ibcon#*before write, iclass 28, count 0 2006.239.07:53:19.98#ibcon#enter sib2, iclass 28, count 0 2006.239.07:53:19.98#ibcon#flushed, iclass 28, count 0 2006.239.07:53:19.98#ibcon#about to write, iclass 28, count 0 2006.239.07:53:19.98#ibcon#wrote, iclass 28, count 0 2006.239.07:53:19.98#ibcon#about to read 3, iclass 28, count 0 2006.239.07:53:20.02#ibcon#read 3, iclass 28, count 0 2006.239.07:53:20.02#ibcon#about to read 4, iclass 28, count 0 2006.239.07:53:20.02#ibcon#read 4, iclass 28, count 0 2006.239.07:53:20.02#ibcon#about to read 5, iclass 28, count 0 2006.239.07:53:20.02#ibcon#read 5, iclass 28, count 0 2006.239.07:53:20.02#ibcon#about to read 6, iclass 28, count 0 2006.239.07:53:20.02#ibcon#read 6, iclass 28, count 0 2006.239.07:53:20.02#ibcon#end of sib2, iclass 28, count 0 2006.239.07:53:20.02#ibcon#*after write, iclass 28, count 0 2006.239.07:53:20.02#ibcon#*before return 0, iclass 28, count 0 2006.239.07:53:20.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:53:20.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.07:53:20.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:53:20.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:53:20.02$vc4f8/va=7,7 2006.239.07:53:20.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.07:53:20.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.07:53:20.02#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:20.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:53:20.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:53:20.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:53:20.08#ibcon#enter wrdev, iclass 30, count 2 2006.239.07:53:20.08#ibcon#first serial, iclass 30, count 2 2006.239.07:53:20.08#ibcon#enter sib2, iclass 30, count 2 2006.239.07:53:20.08#ibcon#flushed, iclass 30, count 2 2006.239.07:53:20.08#ibcon#about to write, iclass 30, count 2 2006.239.07:53:20.08#ibcon#wrote, iclass 30, count 2 2006.239.07:53:20.08#ibcon#about to read 3, iclass 30, count 2 2006.239.07:53:20.10#ibcon#read 3, iclass 30, count 2 2006.239.07:53:20.10#ibcon#about to read 4, iclass 30, count 2 2006.239.07:53:20.10#ibcon#read 4, iclass 30, count 2 2006.239.07:53:20.10#ibcon#about to read 5, iclass 30, count 2 2006.239.07:53:20.10#ibcon#read 5, iclass 30, count 2 2006.239.07:53:20.10#ibcon#about to read 6, iclass 30, count 2 2006.239.07:53:20.10#ibcon#read 6, iclass 30, count 2 2006.239.07:53:20.10#ibcon#end of sib2, iclass 30, count 2 2006.239.07:53:20.10#ibcon#*mode == 0, iclass 30, count 2 2006.239.07:53:20.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.07:53:20.10#ibcon#[25=AT07-07\r\n] 2006.239.07:53:20.10#ibcon#*before write, iclass 30, count 2 2006.239.07:53:20.10#ibcon#enter sib2, iclass 30, count 2 2006.239.07:53:20.10#ibcon#flushed, iclass 30, count 2 2006.239.07:53:20.10#ibcon#about to write, iclass 30, count 2 2006.239.07:53:20.10#ibcon#wrote, iclass 30, count 2 2006.239.07:53:20.10#ibcon#about to read 3, iclass 30, count 2 2006.239.07:53:20.13#ibcon#read 3, iclass 30, count 2 2006.239.07:53:20.13#ibcon#about to read 4, iclass 30, count 2 2006.239.07:53:20.13#ibcon#read 4, iclass 30, count 2 2006.239.07:53:20.13#ibcon#about to read 5, iclass 30, count 2 2006.239.07:53:20.13#ibcon#read 5, iclass 30, count 2 2006.239.07:53:20.13#ibcon#about to read 6, iclass 30, count 2 2006.239.07:53:20.13#ibcon#read 6, iclass 30, count 2 2006.239.07:53:20.13#ibcon#end of sib2, iclass 30, count 2 2006.239.07:53:20.13#ibcon#*after write, iclass 30, count 2 2006.239.07:53:20.13#ibcon#*before return 0, iclass 30, count 2 2006.239.07:53:20.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:53:20.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.07:53:20.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.07:53:20.13#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:20.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:53:20.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:53:20.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:53:20.25#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:53:20.25#ibcon#first serial, iclass 30, count 0 2006.239.07:53:20.25#ibcon#enter sib2, iclass 30, count 0 2006.239.07:53:20.25#ibcon#flushed, iclass 30, count 0 2006.239.07:53:20.25#ibcon#about to write, iclass 30, count 0 2006.239.07:53:20.25#ibcon#wrote, iclass 30, count 0 2006.239.07:53:20.25#ibcon#about to read 3, iclass 30, count 0 2006.239.07:53:20.27#ibcon#read 3, iclass 30, count 0 2006.239.07:53:20.27#ibcon#about to read 4, iclass 30, count 0 2006.239.07:53:20.27#ibcon#read 4, iclass 30, count 0 2006.239.07:53:20.27#ibcon#about to read 5, iclass 30, count 0 2006.239.07:53:20.27#ibcon#read 5, iclass 30, count 0 2006.239.07:53:20.27#ibcon#about to read 6, iclass 30, count 0 2006.239.07:53:20.27#ibcon#read 6, iclass 30, count 0 2006.239.07:53:20.27#ibcon#end of sib2, iclass 30, count 0 2006.239.07:53:20.27#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:53:20.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:53:20.27#ibcon#[25=USB\r\n] 2006.239.07:53:20.27#ibcon#*before write, iclass 30, count 0 2006.239.07:53:20.27#ibcon#enter sib2, iclass 30, count 0 2006.239.07:53:20.27#ibcon#flushed, iclass 30, count 0 2006.239.07:53:20.27#ibcon#about to write, iclass 30, count 0 2006.239.07:53:20.27#ibcon#wrote, iclass 30, count 0 2006.239.07:53:20.27#ibcon#about to read 3, iclass 30, count 0 2006.239.07:53:20.30#ibcon#read 3, iclass 30, count 0 2006.239.07:53:20.30#ibcon#about to read 4, iclass 30, count 0 2006.239.07:53:20.30#ibcon#read 4, iclass 30, count 0 2006.239.07:53:20.30#ibcon#about to read 5, iclass 30, count 0 2006.239.07:53:20.30#ibcon#read 5, iclass 30, count 0 2006.239.07:53:20.30#ibcon#about to read 6, iclass 30, count 0 2006.239.07:53:20.30#ibcon#read 6, iclass 30, count 0 2006.239.07:53:20.30#ibcon#end of sib2, iclass 30, count 0 2006.239.07:53:20.30#ibcon#*after write, iclass 30, count 0 2006.239.07:53:20.30#ibcon#*before return 0, iclass 30, count 0 2006.239.07:53:20.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:53:20.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.07:53:20.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:53:20.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:53:20.30$vc4f8/valo=8,852.99 2006.239.07:53:20.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.07:53:20.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.07:53:20.30#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:20.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:53:20.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:53:20.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:53:20.30#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:53:20.30#ibcon#first serial, iclass 32, count 0 2006.239.07:53:20.30#ibcon#enter sib2, iclass 32, count 0 2006.239.07:53:20.30#ibcon#flushed, iclass 32, count 0 2006.239.07:53:20.30#ibcon#about to write, iclass 32, count 0 2006.239.07:53:20.30#ibcon#wrote, iclass 32, count 0 2006.239.07:53:20.30#ibcon#about to read 3, iclass 32, count 0 2006.239.07:53:20.32#ibcon#read 3, iclass 32, count 0 2006.239.07:53:20.32#ibcon#about to read 4, iclass 32, count 0 2006.239.07:53:20.32#ibcon#read 4, iclass 32, count 0 2006.239.07:53:20.32#ibcon#about to read 5, iclass 32, count 0 2006.239.07:53:20.32#ibcon#read 5, iclass 32, count 0 2006.239.07:53:20.32#ibcon#about to read 6, iclass 32, count 0 2006.239.07:53:20.32#ibcon#read 6, iclass 32, count 0 2006.239.07:53:20.32#ibcon#end of sib2, iclass 32, count 0 2006.239.07:53:20.32#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:53:20.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:53:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:53:20.32#ibcon#*before write, iclass 32, count 0 2006.239.07:53:20.32#ibcon#enter sib2, iclass 32, count 0 2006.239.07:53:20.32#ibcon#flushed, iclass 32, count 0 2006.239.07:53:20.32#ibcon#about to write, iclass 32, count 0 2006.239.07:53:20.32#ibcon#wrote, iclass 32, count 0 2006.239.07:53:20.32#ibcon#about to read 3, iclass 32, count 0 2006.239.07:53:20.37#ibcon#read 3, iclass 32, count 0 2006.239.07:53:20.37#ibcon#about to read 4, iclass 32, count 0 2006.239.07:53:20.37#ibcon#read 4, iclass 32, count 0 2006.239.07:53:20.37#ibcon#about to read 5, iclass 32, count 0 2006.239.07:53:20.37#ibcon#read 5, iclass 32, count 0 2006.239.07:53:20.37#ibcon#about to read 6, iclass 32, count 0 2006.239.07:53:20.37#ibcon#read 6, iclass 32, count 0 2006.239.07:53:20.37#ibcon#end of sib2, iclass 32, count 0 2006.239.07:53:20.37#ibcon#*after write, iclass 32, count 0 2006.239.07:53:20.37#ibcon#*before return 0, iclass 32, count 0 2006.239.07:53:20.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:53:20.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.07:53:20.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:53:20.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:53:20.37$vc4f8/va=8,7 2006.239.07:53:20.37#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.07:53:20.37#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.07:53:20.37#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:20.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:53:20.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:53:20.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:53:20.41#ibcon#enter wrdev, iclass 34, count 2 2006.239.07:53:20.41#ibcon#first serial, iclass 34, count 2 2006.239.07:53:20.41#ibcon#enter sib2, iclass 34, count 2 2006.239.07:53:20.41#ibcon#flushed, iclass 34, count 2 2006.239.07:53:20.41#ibcon#about to write, iclass 34, count 2 2006.239.07:53:20.41#ibcon#wrote, iclass 34, count 2 2006.239.07:53:20.41#ibcon#about to read 3, iclass 34, count 2 2006.239.07:53:20.43#ibcon#read 3, iclass 34, count 2 2006.239.07:53:20.43#ibcon#about to read 4, iclass 34, count 2 2006.239.07:53:20.43#ibcon#read 4, iclass 34, count 2 2006.239.07:53:20.43#ibcon#about to read 5, iclass 34, count 2 2006.239.07:53:20.43#ibcon#read 5, iclass 34, count 2 2006.239.07:53:20.43#ibcon#about to read 6, iclass 34, count 2 2006.239.07:53:20.43#ibcon#read 6, iclass 34, count 2 2006.239.07:53:20.43#ibcon#end of sib2, iclass 34, count 2 2006.239.07:53:20.43#ibcon#*mode == 0, iclass 34, count 2 2006.239.07:53:20.43#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.07:53:20.43#ibcon#[25=AT08-07\r\n] 2006.239.07:53:20.43#ibcon#*before write, iclass 34, count 2 2006.239.07:53:20.43#ibcon#enter sib2, iclass 34, count 2 2006.239.07:53:20.43#ibcon#flushed, iclass 34, count 2 2006.239.07:53:20.43#ibcon#about to write, iclass 34, count 2 2006.239.07:53:20.43#ibcon#wrote, iclass 34, count 2 2006.239.07:53:20.43#ibcon#about to read 3, iclass 34, count 2 2006.239.07:53:20.46#ibcon#read 3, iclass 34, count 2 2006.239.07:53:20.46#ibcon#about to read 4, iclass 34, count 2 2006.239.07:53:20.46#ibcon#read 4, iclass 34, count 2 2006.239.07:53:20.46#ibcon#about to read 5, iclass 34, count 2 2006.239.07:53:20.46#ibcon#read 5, iclass 34, count 2 2006.239.07:53:20.46#ibcon#about to read 6, iclass 34, count 2 2006.239.07:53:20.46#ibcon#read 6, iclass 34, count 2 2006.239.07:53:20.46#ibcon#end of sib2, iclass 34, count 2 2006.239.07:53:20.46#ibcon#*after write, iclass 34, count 2 2006.239.07:53:20.46#ibcon#*before return 0, iclass 34, count 2 2006.239.07:53:20.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:53:20.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.07:53:20.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.07:53:20.46#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:20.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:53:20.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:53:20.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:53:20.58#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:53:20.58#ibcon#first serial, iclass 34, count 0 2006.239.07:53:20.58#ibcon#enter sib2, iclass 34, count 0 2006.239.07:53:20.58#ibcon#flushed, iclass 34, count 0 2006.239.07:53:20.58#ibcon#about to write, iclass 34, count 0 2006.239.07:53:20.58#ibcon#wrote, iclass 34, count 0 2006.239.07:53:20.58#ibcon#about to read 3, iclass 34, count 0 2006.239.07:53:20.60#ibcon#read 3, iclass 34, count 0 2006.239.07:53:20.60#ibcon#about to read 4, iclass 34, count 0 2006.239.07:53:20.60#ibcon#read 4, iclass 34, count 0 2006.239.07:53:20.60#ibcon#about to read 5, iclass 34, count 0 2006.239.07:53:20.60#ibcon#read 5, iclass 34, count 0 2006.239.07:53:20.60#ibcon#about to read 6, iclass 34, count 0 2006.239.07:53:20.60#ibcon#read 6, iclass 34, count 0 2006.239.07:53:20.60#ibcon#end of sib2, iclass 34, count 0 2006.239.07:53:20.60#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:53:20.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:53:20.60#ibcon#[25=USB\r\n] 2006.239.07:53:20.60#ibcon#*before write, iclass 34, count 0 2006.239.07:53:20.60#ibcon#enter sib2, iclass 34, count 0 2006.239.07:53:20.60#ibcon#flushed, iclass 34, count 0 2006.239.07:53:20.60#ibcon#about to write, iclass 34, count 0 2006.239.07:53:20.60#ibcon#wrote, iclass 34, count 0 2006.239.07:53:20.60#ibcon#about to read 3, iclass 34, count 0 2006.239.07:53:20.63#ibcon#read 3, iclass 34, count 0 2006.239.07:53:20.63#ibcon#about to read 4, iclass 34, count 0 2006.239.07:53:20.63#ibcon#read 4, iclass 34, count 0 2006.239.07:53:20.63#ibcon#about to read 5, iclass 34, count 0 2006.239.07:53:20.63#ibcon#read 5, iclass 34, count 0 2006.239.07:53:20.63#ibcon#about to read 6, iclass 34, count 0 2006.239.07:53:20.63#ibcon#read 6, iclass 34, count 0 2006.239.07:53:20.63#ibcon#end of sib2, iclass 34, count 0 2006.239.07:53:20.63#ibcon#*after write, iclass 34, count 0 2006.239.07:53:20.63#ibcon#*before return 0, iclass 34, count 0 2006.239.07:53:20.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:53:20.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.07:53:20.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:53:20.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:53:20.63$vc4f8/vblo=1,632.99 2006.239.07:53:20.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.07:53:20.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.07:53:20.63#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:20.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:53:20.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:53:20.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:53:20.63#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:53:20.63#ibcon#first serial, iclass 36, count 0 2006.239.07:53:20.63#ibcon#enter sib2, iclass 36, count 0 2006.239.07:53:20.63#ibcon#flushed, iclass 36, count 0 2006.239.07:53:20.63#ibcon#about to write, iclass 36, count 0 2006.239.07:53:20.63#ibcon#wrote, iclass 36, count 0 2006.239.07:53:20.63#ibcon#about to read 3, iclass 36, count 0 2006.239.07:53:20.65#ibcon#read 3, iclass 36, count 0 2006.239.07:53:20.65#ibcon#about to read 4, iclass 36, count 0 2006.239.07:53:20.65#ibcon#read 4, iclass 36, count 0 2006.239.07:53:20.65#ibcon#about to read 5, iclass 36, count 0 2006.239.07:53:20.65#ibcon#read 5, iclass 36, count 0 2006.239.07:53:20.65#ibcon#about to read 6, iclass 36, count 0 2006.239.07:53:20.65#ibcon#read 6, iclass 36, count 0 2006.239.07:53:20.65#ibcon#end of sib2, iclass 36, count 0 2006.239.07:53:20.65#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:53:20.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:53:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:53:20.65#ibcon#*before write, iclass 36, count 0 2006.239.07:53:20.65#ibcon#enter sib2, iclass 36, count 0 2006.239.07:53:20.65#ibcon#flushed, iclass 36, count 0 2006.239.07:53:20.65#ibcon#about to write, iclass 36, count 0 2006.239.07:53:20.65#ibcon#wrote, iclass 36, count 0 2006.239.07:53:20.65#ibcon#about to read 3, iclass 36, count 0 2006.239.07:53:20.69#ibcon#read 3, iclass 36, count 0 2006.239.07:53:20.69#ibcon#about to read 4, iclass 36, count 0 2006.239.07:53:20.69#ibcon#read 4, iclass 36, count 0 2006.239.07:53:20.69#ibcon#about to read 5, iclass 36, count 0 2006.239.07:53:20.69#ibcon#read 5, iclass 36, count 0 2006.239.07:53:20.69#ibcon#about to read 6, iclass 36, count 0 2006.239.07:53:20.69#ibcon#read 6, iclass 36, count 0 2006.239.07:53:20.69#ibcon#end of sib2, iclass 36, count 0 2006.239.07:53:20.69#ibcon#*after write, iclass 36, count 0 2006.239.07:53:20.69#ibcon#*before return 0, iclass 36, count 0 2006.239.07:53:20.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:53:20.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.07:53:20.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:53:20.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:53:20.69$vc4f8/vb=1,4 2006.239.07:53:20.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.07:53:20.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.07:53:20.69#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:20.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:53:20.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:53:20.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:53:20.69#ibcon#enter wrdev, iclass 38, count 2 2006.239.07:53:20.69#ibcon#first serial, iclass 38, count 2 2006.239.07:53:20.69#ibcon#enter sib2, iclass 38, count 2 2006.239.07:53:20.69#ibcon#flushed, iclass 38, count 2 2006.239.07:53:20.69#ibcon#about to write, iclass 38, count 2 2006.239.07:53:20.69#ibcon#wrote, iclass 38, count 2 2006.239.07:53:20.69#ibcon#about to read 3, iclass 38, count 2 2006.239.07:53:20.71#ibcon#read 3, iclass 38, count 2 2006.239.07:53:20.71#ibcon#about to read 4, iclass 38, count 2 2006.239.07:53:20.71#ibcon#read 4, iclass 38, count 2 2006.239.07:53:20.71#ibcon#about to read 5, iclass 38, count 2 2006.239.07:53:20.71#ibcon#read 5, iclass 38, count 2 2006.239.07:53:20.71#ibcon#about to read 6, iclass 38, count 2 2006.239.07:53:20.71#ibcon#read 6, iclass 38, count 2 2006.239.07:53:20.71#ibcon#end of sib2, iclass 38, count 2 2006.239.07:53:20.71#ibcon#*mode == 0, iclass 38, count 2 2006.239.07:53:20.71#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.07:53:20.71#ibcon#[27=AT01-04\r\n] 2006.239.07:53:20.71#ibcon#*before write, iclass 38, count 2 2006.239.07:53:20.71#ibcon#enter sib2, iclass 38, count 2 2006.239.07:53:20.71#ibcon#flushed, iclass 38, count 2 2006.239.07:53:20.71#ibcon#about to write, iclass 38, count 2 2006.239.07:53:20.71#ibcon#wrote, iclass 38, count 2 2006.239.07:53:20.71#ibcon#about to read 3, iclass 38, count 2 2006.239.07:53:20.74#ibcon#read 3, iclass 38, count 2 2006.239.07:53:20.74#ibcon#about to read 4, iclass 38, count 2 2006.239.07:53:20.74#ibcon#read 4, iclass 38, count 2 2006.239.07:53:20.74#ibcon#about to read 5, iclass 38, count 2 2006.239.07:53:20.74#ibcon#read 5, iclass 38, count 2 2006.239.07:53:20.74#ibcon#about to read 6, iclass 38, count 2 2006.239.07:53:20.74#ibcon#read 6, iclass 38, count 2 2006.239.07:53:20.74#ibcon#end of sib2, iclass 38, count 2 2006.239.07:53:20.74#ibcon#*after write, iclass 38, count 2 2006.239.07:53:20.74#ibcon#*before return 0, iclass 38, count 2 2006.239.07:53:20.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:53:20.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.07:53:20.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.07:53:20.74#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:20.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:53:20.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:53:20.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:53:20.86#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:53:20.86#ibcon#first serial, iclass 38, count 0 2006.239.07:53:20.86#ibcon#enter sib2, iclass 38, count 0 2006.239.07:53:20.86#ibcon#flushed, iclass 38, count 0 2006.239.07:53:20.86#ibcon#about to write, iclass 38, count 0 2006.239.07:53:20.86#ibcon#wrote, iclass 38, count 0 2006.239.07:53:20.86#ibcon#about to read 3, iclass 38, count 0 2006.239.07:53:20.88#ibcon#read 3, iclass 38, count 0 2006.239.07:53:20.88#ibcon#about to read 4, iclass 38, count 0 2006.239.07:53:20.88#ibcon#read 4, iclass 38, count 0 2006.239.07:53:20.88#ibcon#about to read 5, iclass 38, count 0 2006.239.07:53:20.88#ibcon#read 5, iclass 38, count 0 2006.239.07:53:20.88#ibcon#about to read 6, iclass 38, count 0 2006.239.07:53:20.88#ibcon#read 6, iclass 38, count 0 2006.239.07:53:20.88#ibcon#end of sib2, iclass 38, count 0 2006.239.07:53:20.88#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:53:20.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:53:20.88#ibcon#[27=USB\r\n] 2006.239.07:53:20.88#ibcon#*before write, iclass 38, count 0 2006.239.07:53:20.88#ibcon#enter sib2, iclass 38, count 0 2006.239.07:53:20.88#ibcon#flushed, iclass 38, count 0 2006.239.07:53:20.88#ibcon#about to write, iclass 38, count 0 2006.239.07:53:20.88#ibcon#wrote, iclass 38, count 0 2006.239.07:53:20.88#ibcon#about to read 3, iclass 38, count 0 2006.239.07:53:20.91#ibcon#read 3, iclass 38, count 0 2006.239.07:53:20.91#ibcon#about to read 4, iclass 38, count 0 2006.239.07:53:20.91#ibcon#read 4, iclass 38, count 0 2006.239.07:53:20.91#ibcon#about to read 5, iclass 38, count 0 2006.239.07:53:20.91#ibcon#read 5, iclass 38, count 0 2006.239.07:53:20.91#ibcon#about to read 6, iclass 38, count 0 2006.239.07:53:20.91#ibcon#read 6, iclass 38, count 0 2006.239.07:53:20.91#ibcon#end of sib2, iclass 38, count 0 2006.239.07:53:20.91#ibcon#*after write, iclass 38, count 0 2006.239.07:53:20.91#ibcon#*before return 0, iclass 38, count 0 2006.239.07:53:20.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:53:20.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.07:53:20.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:53:20.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:53:20.91$vc4f8/vblo=2,640.99 2006.239.07:53:20.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.07:53:20.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.07:53:20.91#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:20.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:20.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:20.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:20.91#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:53:20.91#ibcon#first serial, iclass 40, count 0 2006.239.07:53:20.91#ibcon#enter sib2, iclass 40, count 0 2006.239.07:53:20.91#ibcon#flushed, iclass 40, count 0 2006.239.07:53:20.91#ibcon#about to write, iclass 40, count 0 2006.239.07:53:20.91#ibcon#wrote, iclass 40, count 0 2006.239.07:53:20.91#ibcon#about to read 3, iclass 40, count 0 2006.239.07:53:20.93#ibcon#read 3, iclass 40, count 0 2006.239.07:53:20.93#ibcon#about to read 4, iclass 40, count 0 2006.239.07:53:20.93#ibcon#read 4, iclass 40, count 0 2006.239.07:53:20.93#ibcon#about to read 5, iclass 40, count 0 2006.239.07:53:20.93#ibcon#read 5, iclass 40, count 0 2006.239.07:53:20.93#ibcon#about to read 6, iclass 40, count 0 2006.239.07:53:20.93#ibcon#read 6, iclass 40, count 0 2006.239.07:53:20.93#ibcon#end of sib2, iclass 40, count 0 2006.239.07:53:20.93#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:53:20.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:53:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:53:20.93#ibcon#*before write, iclass 40, count 0 2006.239.07:53:20.93#ibcon#enter sib2, iclass 40, count 0 2006.239.07:53:20.93#ibcon#flushed, iclass 40, count 0 2006.239.07:53:20.93#ibcon#about to write, iclass 40, count 0 2006.239.07:53:20.93#ibcon#wrote, iclass 40, count 0 2006.239.07:53:20.93#ibcon#about to read 3, iclass 40, count 0 2006.239.07:53:20.97#ibcon#read 3, iclass 40, count 0 2006.239.07:53:20.97#ibcon#about to read 4, iclass 40, count 0 2006.239.07:53:20.97#ibcon#read 4, iclass 40, count 0 2006.239.07:53:20.97#ibcon#about to read 5, iclass 40, count 0 2006.239.07:53:20.97#ibcon#read 5, iclass 40, count 0 2006.239.07:53:20.97#ibcon#about to read 6, iclass 40, count 0 2006.239.07:53:20.97#ibcon#read 6, iclass 40, count 0 2006.239.07:53:20.97#ibcon#end of sib2, iclass 40, count 0 2006.239.07:53:20.97#ibcon#*after write, iclass 40, count 0 2006.239.07:53:20.97#ibcon#*before return 0, iclass 40, count 0 2006.239.07:53:20.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:20.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.07:53:20.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:53:20.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:53:20.97$vc4f8/vb=2,4 2006.239.07:53:20.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.07:53:20.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.07:53:20.97#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:20.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:21.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:21.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:21.03#ibcon#enter wrdev, iclass 4, count 2 2006.239.07:53:21.03#ibcon#first serial, iclass 4, count 2 2006.239.07:53:21.03#ibcon#enter sib2, iclass 4, count 2 2006.239.07:53:21.03#ibcon#flushed, iclass 4, count 2 2006.239.07:53:21.03#ibcon#about to write, iclass 4, count 2 2006.239.07:53:21.03#ibcon#wrote, iclass 4, count 2 2006.239.07:53:21.03#ibcon#about to read 3, iclass 4, count 2 2006.239.07:53:21.05#ibcon#read 3, iclass 4, count 2 2006.239.07:53:21.05#ibcon#about to read 4, iclass 4, count 2 2006.239.07:53:21.05#ibcon#read 4, iclass 4, count 2 2006.239.07:53:21.05#ibcon#about to read 5, iclass 4, count 2 2006.239.07:53:21.05#ibcon#read 5, iclass 4, count 2 2006.239.07:53:21.05#ibcon#about to read 6, iclass 4, count 2 2006.239.07:53:21.05#ibcon#read 6, iclass 4, count 2 2006.239.07:53:21.05#ibcon#end of sib2, iclass 4, count 2 2006.239.07:53:21.05#ibcon#*mode == 0, iclass 4, count 2 2006.239.07:53:21.05#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.07:53:21.05#ibcon#[27=AT02-04\r\n] 2006.239.07:53:21.05#ibcon#*before write, iclass 4, count 2 2006.239.07:53:21.05#ibcon#enter sib2, iclass 4, count 2 2006.239.07:53:21.05#ibcon#flushed, iclass 4, count 2 2006.239.07:53:21.05#ibcon#about to write, iclass 4, count 2 2006.239.07:53:21.05#ibcon#wrote, iclass 4, count 2 2006.239.07:53:21.05#ibcon#about to read 3, iclass 4, count 2 2006.239.07:53:21.08#ibcon#read 3, iclass 4, count 2 2006.239.07:53:21.08#ibcon#about to read 4, iclass 4, count 2 2006.239.07:53:21.08#ibcon#read 4, iclass 4, count 2 2006.239.07:53:21.08#ibcon#about to read 5, iclass 4, count 2 2006.239.07:53:21.08#ibcon#read 5, iclass 4, count 2 2006.239.07:53:21.08#ibcon#about to read 6, iclass 4, count 2 2006.239.07:53:21.08#ibcon#read 6, iclass 4, count 2 2006.239.07:53:21.08#ibcon#end of sib2, iclass 4, count 2 2006.239.07:53:21.08#ibcon#*after write, iclass 4, count 2 2006.239.07:53:21.08#ibcon#*before return 0, iclass 4, count 2 2006.239.07:53:21.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:21.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.07:53:21.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.07:53:21.08#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:21.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:21.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:21.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:21.20#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:53:21.20#ibcon#first serial, iclass 4, count 0 2006.239.07:53:21.20#ibcon#enter sib2, iclass 4, count 0 2006.239.07:53:21.20#ibcon#flushed, iclass 4, count 0 2006.239.07:53:21.20#ibcon#about to write, iclass 4, count 0 2006.239.07:53:21.20#ibcon#wrote, iclass 4, count 0 2006.239.07:53:21.20#ibcon#about to read 3, iclass 4, count 0 2006.239.07:53:21.22#ibcon#read 3, iclass 4, count 0 2006.239.07:53:21.22#ibcon#about to read 4, iclass 4, count 0 2006.239.07:53:21.22#ibcon#read 4, iclass 4, count 0 2006.239.07:53:21.22#ibcon#about to read 5, iclass 4, count 0 2006.239.07:53:21.22#ibcon#read 5, iclass 4, count 0 2006.239.07:53:21.22#ibcon#about to read 6, iclass 4, count 0 2006.239.07:53:21.22#ibcon#read 6, iclass 4, count 0 2006.239.07:53:21.22#ibcon#end of sib2, iclass 4, count 0 2006.239.07:53:21.22#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:53:21.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:53:21.22#ibcon#[27=USB\r\n] 2006.239.07:53:21.22#ibcon#*before write, iclass 4, count 0 2006.239.07:53:21.22#ibcon#enter sib2, iclass 4, count 0 2006.239.07:53:21.22#ibcon#flushed, iclass 4, count 0 2006.239.07:53:21.22#ibcon#about to write, iclass 4, count 0 2006.239.07:53:21.22#ibcon#wrote, iclass 4, count 0 2006.239.07:53:21.22#ibcon#about to read 3, iclass 4, count 0 2006.239.07:53:21.25#ibcon#read 3, iclass 4, count 0 2006.239.07:53:21.25#ibcon#about to read 4, iclass 4, count 0 2006.239.07:53:21.25#ibcon#read 4, iclass 4, count 0 2006.239.07:53:21.25#ibcon#about to read 5, iclass 4, count 0 2006.239.07:53:21.25#ibcon#read 5, iclass 4, count 0 2006.239.07:53:21.25#ibcon#about to read 6, iclass 4, count 0 2006.239.07:53:21.25#ibcon#read 6, iclass 4, count 0 2006.239.07:53:21.25#ibcon#end of sib2, iclass 4, count 0 2006.239.07:53:21.25#ibcon#*after write, iclass 4, count 0 2006.239.07:53:21.25#ibcon#*before return 0, iclass 4, count 0 2006.239.07:53:21.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:21.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.07:53:21.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:53:21.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:53:21.25$vc4f8/vblo=3,656.99 2006.239.07:53:21.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.07:53:21.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.07:53:21.25#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:21.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:21.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:21.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:21.25#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:53:21.25#ibcon#first serial, iclass 6, count 0 2006.239.07:53:21.25#ibcon#enter sib2, iclass 6, count 0 2006.239.07:53:21.25#ibcon#flushed, iclass 6, count 0 2006.239.07:53:21.25#ibcon#about to write, iclass 6, count 0 2006.239.07:53:21.25#ibcon#wrote, iclass 6, count 0 2006.239.07:53:21.25#ibcon#about to read 3, iclass 6, count 0 2006.239.07:53:21.27#ibcon#read 3, iclass 6, count 0 2006.239.07:53:21.27#ibcon#about to read 4, iclass 6, count 0 2006.239.07:53:21.27#ibcon#read 4, iclass 6, count 0 2006.239.07:53:21.27#ibcon#about to read 5, iclass 6, count 0 2006.239.07:53:21.27#ibcon#read 5, iclass 6, count 0 2006.239.07:53:21.27#ibcon#about to read 6, iclass 6, count 0 2006.239.07:53:21.27#ibcon#read 6, iclass 6, count 0 2006.239.07:53:21.27#ibcon#end of sib2, iclass 6, count 0 2006.239.07:53:21.27#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:53:21.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:53:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:53:21.27#ibcon#*before write, iclass 6, count 0 2006.239.07:53:21.27#ibcon#enter sib2, iclass 6, count 0 2006.239.07:53:21.27#ibcon#flushed, iclass 6, count 0 2006.239.07:53:21.27#ibcon#about to write, iclass 6, count 0 2006.239.07:53:21.27#ibcon#wrote, iclass 6, count 0 2006.239.07:53:21.27#ibcon#about to read 3, iclass 6, count 0 2006.239.07:53:21.31#ibcon#read 3, iclass 6, count 0 2006.239.07:53:21.31#ibcon#about to read 4, iclass 6, count 0 2006.239.07:53:21.31#ibcon#read 4, iclass 6, count 0 2006.239.07:53:21.31#ibcon#about to read 5, iclass 6, count 0 2006.239.07:53:21.31#ibcon#read 5, iclass 6, count 0 2006.239.07:53:21.31#ibcon#about to read 6, iclass 6, count 0 2006.239.07:53:21.31#ibcon#read 6, iclass 6, count 0 2006.239.07:53:21.31#ibcon#end of sib2, iclass 6, count 0 2006.239.07:53:21.31#ibcon#*after write, iclass 6, count 0 2006.239.07:53:21.31#ibcon#*before return 0, iclass 6, count 0 2006.239.07:53:21.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:21.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.07:53:21.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:53:21.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:53:21.31$vc4f8/vb=3,4 2006.239.07:53:21.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.07:53:21.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.07:53:21.31#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:21.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:21.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:21.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:21.37#ibcon#enter wrdev, iclass 10, count 2 2006.239.07:53:21.37#ibcon#first serial, iclass 10, count 2 2006.239.07:53:21.37#ibcon#enter sib2, iclass 10, count 2 2006.239.07:53:21.37#ibcon#flushed, iclass 10, count 2 2006.239.07:53:21.37#ibcon#about to write, iclass 10, count 2 2006.239.07:53:21.37#ibcon#wrote, iclass 10, count 2 2006.239.07:53:21.37#ibcon#about to read 3, iclass 10, count 2 2006.239.07:53:21.39#ibcon#read 3, iclass 10, count 2 2006.239.07:53:21.39#ibcon#about to read 4, iclass 10, count 2 2006.239.07:53:21.39#ibcon#read 4, iclass 10, count 2 2006.239.07:53:21.39#ibcon#about to read 5, iclass 10, count 2 2006.239.07:53:21.39#ibcon#read 5, iclass 10, count 2 2006.239.07:53:21.39#ibcon#about to read 6, iclass 10, count 2 2006.239.07:53:21.39#ibcon#read 6, iclass 10, count 2 2006.239.07:53:21.39#ibcon#end of sib2, iclass 10, count 2 2006.239.07:53:21.39#ibcon#*mode == 0, iclass 10, count 2 2006.239.07:53:21.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.07:53:21.39#ibcon#[27=AT03-04\r\n] 2006.239.07:53:21.39#ibcon#*before write, iclass 10, count 2 2006.239.07:53:21.39#ibcon#enter sib2, iclass 10, count 2 2006.239.07:53:21.39#ibcon#flushed, iclass 10, count 2 2006.239.07:53:21.39#ibcon#about to write, iclass 10, count 2 2006.239.07:53:21.39#ibcon#wrote, iclass 10, count 2 2006.239.07:53:21.39#ibcon#about to read 3, iclass 10, count 2 2006.239.07:53:21.42#ibcon#read 3, iclass 10, count 2 2006.239.07:53:21.42#ibcon#about to read 4, iclass 10, count 2 2006.239.07:53:21.42#ibcon#read 4, iclass 10, count 2 2006.239.07:53:21.42#ibcon#about to read 5, iclass 10, count 2 2006.239.07:53:21.42#ibcon#read 5, iclass 10, count 2 2006.239.07:53:21.42#ibcon#about to read 6, iclass 10, count 2 2006.239.07:53:21.42#ibcon#read 6, iclass 10, count 2 2006.239.07:53:21.42#ibcon#end of sib2, iclass 10, count 2 2006.239.07:53:21.42#ibcon#*after write, iclass 10, count 2 2006.239.07:53:21.42#ibcon#*before return 0, iclass 10, count 2 2006.239.07:53:21.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:21.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.07:53:21.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.07:53:21.42#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:21.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:21.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:21.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:21.54#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:53:21.54#ibcon#first serial, iclass 10, count 0 2006.239.07:53:21.54#ibcon#enter sib2, iclass 10, count 0 2006.239.07:53:21.54#ibcon#flushed, iclass 10, count 0 2006.239.07:53:21.54#ibcon#about to write, iclass 10, count 0 2006.239.07:53:21.54#ibcon#wrote, iclass 10, count 0 2006.239.07:53:21.54#ibcon#about to read 3, iclass 10, count 0 2006.239.07:53:21.56#ibcon#read 3, iclass 10, count 0 2006.239.07:53:21.56#ibcon#about to read 4, iclass 10, count 0 2006.239.07:53:21.56#ibcon#read 4, iclass 10, count 0 2006.239.07:53:21.56#ibcon#about to read 5, iclass 10, count 0 2006.239.07:53:21.56#ibcon#read 5, iclass 10, count 0 2006.239.07:53:21.56#ibcon#about to read 6, iclass 10, count 0 2006.239.07:53:21.56#ibcon#read 6, iclass 10, count 0 2006.239.07:53:21.56#ibcon#end of sib2, iclass 10, count 0 2006.239.07:53:21.56#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:53:21.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:53:21.56#ibcon#[27=USB\r\n] 2006.239.07:53:21.56#ibcon#*before write, iclass 10, count 0 2006.239.07:53:21.56#ibcon#enter sib2, iclass 10, count 0 2006.239.07:53:21.56#ibcon#flushed, iclass 10, count 0 2006.239.07:53:21.56#ibcon#about to write, iclass 10, count 0 2006.239.07:53:21.56#ibcon#wrote, iclass 10, count 0 2006.239.07:53:21.56#ibcon#about to read 3, iclass 10, count 0 2006.239.07:53:21.59#ibcon#read 3, iclass 10, count 0 2006.239.07:53:21.59#ibcon#about to read 4, iclass 10, count 0 2006.239.07:53:21.59#ibcon#read 4, iclass 10, count 0 2006.239.07:53:21.59#ibcon#about to read 5, iclass 10, count 0 2006.239.07:53:21.59#ibcon#read 5, iclass 10, count 0 2006.239.07:53:21.59#ibcon#about to read 6, iclass 10, count 0 2006.239.07:53:21.59#ibcon#read 6, iclass 10, count 0 2006.239.07:53:21.59#ibcon#end of sib2, iclass 10, count 0 2006.239.07:53:21.59#ibcon#*after write, iclass 10, count 0 2006.239.07:53:21.59#ibcon#*before return 0, iclass 10, count 0 2006.239.07:53:21.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:21.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.07:53:21.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:53:21.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:53:21.59$vc4f8/vblo=4,712.99 2006.239.07:53:21.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:53:21.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:53:21.59#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:21.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:21.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:21.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:21.59#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:53:21.59#ibcon#first serial, iclass 12, count 0 2006.239.07:53:21.59#ibcon#enter sib2, iclass 12, count 0 2006.239.07:53:21.59#ibcon#flushed, iclass 12, count 0 2006.239.07:53:21.59#ibcon#about to write, iclass 12, count 0 2006.239.07:53:21.59#ibcon#wrote, iclass 12, count 0 2006.239.07:53:21.59#ibcon#about to read 3, iclass 12, count 0 2006.239.07:53:21.61#ibcon#read 3, iclass 12, count 0 2006.239.07:53:21.61#ibcon#about to read 4, iclass 12, count 0 2006.239.07:53:21.61#ibcon#read 4, iclass 12, count 0 2006.239.07:53:21.61#ibcon#about to read 5, iclass 12, count 0 2006.239.07:53:21.61#ibcon#read 5, iclass 12, count 0 2006.239.07:53:21.61#ibcon#about to read 6, iclass 12, count 0 2006.239.07:53:21.61#ibcon#read 6, iclass 12, count 0 2006.239.07:53:21.61#ibcon#end of sib2, iclass 12, count 0 2006.239.07:53:21.61#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:53:21.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:53:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:53:21.61#ibcon#*before write, iclass 12, count 0 2006.239.07:53:21.61#ibcon#enter sib2, iclass 12, count 0 2006.239.07:53:21.61#ibcon#flushed, iclass 12, count 0 2006.239.07:53:21.61#ibcon#about to write, iclass 12, count 0 2006.239.07:53:21.61#ibcon#wrote, iclass 12, count 0 2006.239.07:53:21.61#ibcon#about to read 3, iclass 12, count 0 2006.239.07:53:21.65#ibcon#read 3, iclass 12, count 0 2006.239.07:53:21.65#ibcon#about to read 4, iclass 12, count 0 2006.239.07:53:21.65#ibcon#read 4, iclass 12, count 0 2006.239.07:53:21.65#ibcon#about to read 5, iclass 12, count 0 2006.239.07:53:21.65#ibcon#read 5, iclass 12, count 0 2006.239.07:53:21.65#ibcon#about to read 6, iclass 12, count 0 2006.239.07:53:21.65#ibcon#read 6, iclass 12, count 0 2006.239.07:53:21.65#ibcon#end of sib2, iclass 12, count 0 2006.239.07:53:21.65#ibcon#*after write, iclass 12, count 0 2006.239.07:53:21.65#ibcon#*before return 0, iclass 12, count 0 2006.239.07:53:21.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:21.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:53:21.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:53:21.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:53:21.65$vc4f8/vb=4,4 2006.239.07:53:21.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.07:53:21.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.07:53:21.65#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:21.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:21.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:21.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:21.72#ibcon#enter wrdev, iclass 14, count 2 2006.239.07:53:21.72#ibcon#first serial, iclass 14, count 2 2006.239.07:53:21.72#ibcon#enter sib2, iclass 14, count 2 2006.239.07:53:21.72#ibcon#flushed, iclass 14, count 2 2006.239.07:53:21.72#ibcon#about to write, iclass 14, count 2 2006.239.07:53:21.72#ibcon#wrote, iclass 14, count 2 2006.239.07:53:21.72#ibcon#about to read 3, iclass 14, count 2 2006.239.07:53:21.73#ibcon#read 3, iclass 14, count 2 2006.239.07:53:21.73#ibcon#about to read 4, iclass 14, count 2 2006.239.07:53:21.73#ibcon#read 4, iclass 14, count 2 2006.239.07:53:21.73#ibcon#about to read 5, iclass 14, count 2 2006.239.07:53:21.73#ibcon#read 5, iclass 14, count 2 2006.239.07:53:21.73#ibcon#about to read 6, iclass 14, count 2 2006.239.07:53:21.73#ibcon#read 6, iclass 14, count 2 2006.239.07:53:21.73#ibcon#end of sib2, iclass 14, count 2 2006.239.07:53:21.73#ibcon#*mode == 0, iclass 14, count 2 2006.239.07:53:21.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.07:53:21.73#ibcon#[27=AT04-04\r\n] 2006.239.07:53:21.73#ibcon#*before write, iclass 14, count 2 2006.239.07:53:21.73#ibcon#enter sib2, iclass 14, count 2 2006.239.07:53:21.73#ibcon#flushed, iclass 14, count 2 2006.239.07:53:21.73#ibcon#about to write, iclass 14, count 2 2006.239.07:53:21.73#ibcon#wrote, iclass 14, count 2 2006.239.07:53:21.73#ibcon#about to read 3, iclass 14, count 2 2006.239.07:53:21.76#ibcon#read 3, iclass 14, count 2 2006.239.07:53:21.76#ibcon#about to read 4, iclass 14, count 2 2006.239.07:53:21.76#ibcon#read 4, iclass 14, count 2 2006.239.07:53:21.76#ibcon#about to read 5, iclass 14, count 2 2006.239.07:53:21.76#ibcon#read 5, iclass 14, count 2 2006.239.07:53:21.76#ibcon#about to read 6, iclass 14, count 2 2006.239.07:53:21.76#ibcon#read 6, iclass 14, count 2 2006.239.07:53:21.76#ibcon#end of sib2, iclass 14, count 2 2006.239.07:53:21.76#ibcon#*after write, iclass 14, count 2 2006.239.07:53:21.76#ibcon#*before return 0, iclass 14, count 2 2006.239.07:53:21.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:21.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.07:53:21.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.07:53:21.76#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:21.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:21.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:21.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:21.88#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:53:21.88#ibcon#first serial, iclass 14, count 0 2006.239.07:53:21.88#ibcon#enter sib2, iclass 14, count 0 2006.239.07:53:21.88#ibcon#flushed, iclass 14, count 0 2006.239.07:53:21.88#ibcon#about to write, iclass 14, count 0 2006.239.07:53:21.88#ibcon#wrote, iclass 14, count 0 2006.239.07:53:21.88#ibcon#about to read 3, iclass 14, count 0 2006.239.07:53:21.90#ibcon#read 3, iclass 14, count 0 2006.239.07:53:21.90#ibcon#about to read 4, iclass 14, count 0 2006.239.07:53:21.90#ibcon#read 4, iclass 14, count 0 2006.239.07:53:21.90#ibcon#about to read 5, iclass 14, count 0 2006.239.07:53:21.90#ibcon#read 5, iclass 14, count 0 2006.239.07:53:21.90#ibcon#about to read 6, iclass 14, count 0 2006.239.07:53:21.90#ibcon#read 6, iclass 14, count 0 2006.239.07:53:21.90#ibcon#end of sib2, iclass 14, count 0 2006.239.07:53:21.90#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:53:21.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:53:21.90#ibcon#[27=USB\r\n] 2006.239.07:53:21.90#ibcon#*before write, iclass 14, count 0 2006.239.07:53:21.90#ibcon#enter sib2, iclass 14, count 0 2006.239.07:53:21.90#ibcon#flushed, iclass 14, count 0 2006.239.07:53:21.90#ibcon#about to write, iclass 14, count 0 2006.239.07:53:21.90#ibcon#wrote, iclass 14, count 0 2006.239.07:53:21.90#ibcon#about to read 3, iclass 14, count 0 2006.239.07:53:21.93#ibcon#read 3, iclass 14, count 0 2006.239.07:53:21.93#ibcon#about to read 4, iclass 14, count 0 2006.239.07:53:21.93#ibcon#read 4, iclass 14, count 0 2006.239.07:53:21.93#ibcon#about to read 5, iclass 14, count 0 2006.239.07:53:21.93#ibcon#read 5, iclass 14, count 0 2006.239.07:53:21.93#ibcon#about to read 6, iclass 14, count 0 2006.239.07:53:21.93#ibcon#read 6, iclass 14, count 0 2006.239.07:53:21.93#ibcon#end of sib2, iclass 14, count 0 2006.239.07:53:21.93#ibcon#*after write, iclass 14, count 0 2006.239.07:53:21.93#ibcon#*before return 0, iclass 14, count 0 2006.239.07:53:21.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:21.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.07:53:21.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:53:21.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:53:21.93$vc4f8/vblo=5,744.99 2006.239.07:53:21.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.07:53:21.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.07:53:21.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:21.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:21.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:21.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:21.93#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:53:21.93#ibcon#first serial, iclass 16, count 0 2006.239.07:53:21.93#ibcon#enter sib2, iclass 16, count 0 2006.239.07:53:21.93#ibcon#flushed, iclass 16, count 0 2006.239.07:53:21.93#ibcon#about to write, iclass 16, count 0 2006.239.07:53:21.93#ibcon#wrote, iclass 16, count 0 2006.239.07:53:21.93#ibcon#about to read 3, iclass 16, count 0 2006.239.07:53:21.95#ibcon#read 3, iclass 16, count 0 2006.239.07:53:21.95#ibcon#about to read 4, iclass 16, count 0 2006.239.07:53:21.95#ibcon#read 4, iclass 16, count 0 2006.239.07:53:21.95#ibcon#about to read 5, iclass 16, count 0 2006.239.07:53:21.95#ibcon#read 5, iclass 16, count 0 2006.239.07:53:21.95#ibcon#about to read 6, iclass 16, count 0 2006.239.07:53:21.95#ibcon#read 6, iclass 16, count 0 2006.239.07:53:21.95#ibcon#end of sib2, iclass 16, count 0 2006.239.07:53:21.95#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:53:21.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:53:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:53:21.95#ibcon#*before write, iclass 16, count 0 2006.239.07:53:21.95#ibcon#enter sib2, iclass 16, count 0 2006.239.07:53:21.95#ibcon#flushed, iclass 16, count 0 2006.239.07:53:21.95#ibcon#about to write, iclass 16, count 0 2006.239.07:53:21.95#ibcon#wrote, iclass 16, count 0 2006.239.07:53:21.95#ibcon#about to read 3, iclass 16, count 0 2006.239.07:53:22.00#ibcon#read 3, iclass 16, count 0 2006.239.07:53:22.00#ibcon#about to read 4, iclass 16, count 0 2006.239.07:53:22.00#ibcon#read 4, iclass 16, count 0 2006.239.07:53:22.00#ibcon#about to read 5, iclass 16, count 0 2006.239.07:53:22.00#ibcon#read 5, iclass 16, count 0 2006.239.07:53:22.00#ibcon#about to read 6, iclass 16, count 0 2006.239.07:53:22.00#ibcon#read 6, iclass 16, count 0 2006.239.07:53:22.00#ibcon#end of sib2, iclass 16, count 0 2006.239.07:53:22.00#ibcon#*after write, iclass 16, count 0 2006.239.07:53:22.00#ibcon#*before return 0, iclass 16, count 0 2006.239.07:53:22.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:22.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.07:53:22.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:53:22.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:53:22.00$vc4f8/vb=5,4 2006.239.07:53:22.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.07:53:22.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.07:53:22.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:22.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:22.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:22.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:22.04#ibcon#enter wrdev, iclass 18, count 2 2006.239.07:53:22.04#ibcon#first serial, iclass 18, count 2 2006.239.07:53:22.04#ibcon#enter sib2, iclass 18, count 2 2006.239.07:53:22.04#ibcon#flushed, iclass 18, count 2 2006.239.07:53:22.04#ibcon#about to write, iclass 18, count 2 2006.239.07:53:22.04#ibcon#wrote, iclass 18, count 2 2006.239.07:53:22.04#ibcon#about to read 3, iclass 18, count 2 2006.239.07:53:22.06#ibcon#read 3, iclass 18, count 2 2006.239.07:53:22.06#ibcon#about to read 4, iclass 18, count 2 2006.239.07:53:22.06#ibcon#read 4, iclass 18, count 2 2006.239.07:53:22.06#ibcon#about to read 5, iclass 18, count 2 2006.239.07:53:22.06#ibcon#read 5, iclass 18, count 2 2006.239.07:53:22.06#ibcon#about to read 6, iclass 18, count 2 2006.239.07:53:22.06#ibcon#read 6, iclass 18, count 2 2006.239.07:53:22.06#ibcon#end of sib2, iclass 18, count 2 2006.239.07:53:22.06#ibcon#*mode == 0, iclass 18, count 2 2006.239.07:53:22.06#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.07:53:22.06#ibcon#[27=AT05-04\r\n] 2006.239.07:53:22.06#ibcon#*before write, iclass 18, count 2 2006.239.07:53:22.06#ibcon#enter sib2, iclass 18, count 2 2006.239.07:53:22.06#ibcon#flushed, iclass 18, count 2 2006.239.07:53:22.06#ibcon#about to write, iclass 18, count 2 2006.239.07:53:22.06#ibcon#wrote, iclass 18, count 2 2006.239.07:53:22.06#ibcon#about to read 3, iclass 18, count 2 2006.239.07:53:22.09#ibcon#read 3, iclass 18, count 2 2006.239.07:53:22.09#ibcon#about to read 4, iclass 18, count 2 2006.239.07:53:22.09#ibcon#read 4, iclass 18, count 2 2006.239.07:53:22.09#ibcon#about to read 5, iclass 18, count 2 2006.239.07:53:22.09#ibcon#read 5, iclass 18, count 2 2006.239.07:53:22.09#ibcon#about to read 6, iclass 18, count 2 2006.239.07:53:22.09#ibcon#read 6, iclass 18, count 2 2006.239.07:53:22.09#ibcon#end of sib2, iclass 18, count 2 2006.239.07:53:22.09#ibcon#*after write, iclass 18, count 2 2006.239.07:53:22.09#ibcon#*before return 0, iclass 18, count 2 2006.239.07:53:22.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:22.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.07:53:22.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.07:53:22.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:22.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:22.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:22.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:22.21#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:53:22.21#ibcon#first serial, iclass 18, count 0 2006.239.07:53:22.21#ibcon#enter sib2, iclass 18, count 0 2006.239.07:53:22.21#ibcon#flushed, iclass 18, count 0 2006.239.07:53:22.21#ibcon#about to write, iclass 18, count 0 2006.239.07:53:22.21#ibcon#wrote, iclass 18, count 0 2006.239.07:53:22.21#ibcon#about to read 3, iclass 18, count 0 2006.239.07:53:22.23#ibcon#read 3, iclass 18, count 0 2006.239.07:53:22.23#ibcon#about to read 4, iclass 18, count 0 2006.239.07:53:22.23#ibcon#read 4, iclass 18, count 0 2006.239.07:53:22.23#ibcon#about to read 5, iclass 18, count 0 2006.239.07:53:22.23#ibcon#read 5, iclass 18, count 0 2006.239.07:53:22.23#ibcon#about to read 6, iclass 18, count 0 2006.239.07:53:22.23#ibcon#read 6, iclass 18, count 0 2006.239.07:53:22.23#ibcon#end of sib2, iclass 18, count 0 2006.239.07:53:22.23#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:53:22.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:53:22.23#ibcon#[27=USB\r\n] 2006.239.07:53:22.23#ibcon#*before write, iclass 18, count 0 2006.239.07:53:22.23#ibcon#enter sib2, iclass 18, count 0 2006.239.07:53:22.23#ibcon#flushed, iclass 18, count 0 2006.239.07:53:22.23#ibcon#about to write, iclass 18, count 0 2006.239.07:53:22.23#ibcon#wrote, iclass 18, count 0 2006.239.07:53:22.23#ibcon#about to read 3, iclass 18, count 0 2006.239.07:53:22.26#ibcon#read 3, iclass 18, count 0 2006.239.07:53:22.26#ibcon#about to read 4, iclass 18, count 0 2006.239.07:53:22.26#ibcon#read 4, iclass 18, count 0 2006.239.07:53:22.26#ibcon#about to read 5, iclass 18, count 0 2006.239.07:53:22.26#ibcon#read 5, iclass 18, count 0 2006.239.07:53:22.26#ibcon#about to read 6, iclass 18, count 0 2006.239.07:53:22.26#ibcon#read 6, iclass 18, count 0 2006.239.07:53:22.26#ibcon#end of sib2, iclass 18, count 0 2006.239.07:53:22.26#ibcon#*after write, iclass 18, count 0 2006.239.07:53:22.26#ibcon#*before return 0, iclass 18, count 0 2006.239.07:53:22.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:22.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.07:53:22.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:53:22.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:53:22.26$vc4f8/vblo=6,752.99 2006.239.07:53:22.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.07:53:22.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.07:53:22.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:53:22.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:22.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:22.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:22.26#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:53:22.26#ibcon#first serial, iclass 20, count 0 2006.239.07:53:22.26#ibcon#enter sib2, iclass 20, count 0 2006.239.07:53:22.26#ibcon#flushed, iclass 20, count 0 2006.239.07:53:22.26#ibcon#about to write, iclass 20, count 0 2006.239.07:53:22.26#ibcon#wrote, iclass 20, count 0 2006.239.07:53:22.26#ibcon#about to read 3, iclass 20, count 0 2006.239.07:53:22.28#ibcon#read 3, iclass 20, count 0 2006.239.07:53:22.28#ibcon#about to read 4, iclass 20, count 0 2006.239.07:53:22.28#ibcon#read 4, iclass 20, count 0 2006.239.07:53:22.28#ibcon#about to read 5, iclass 20, count 0 2006.239.07:53:22.28#ibcon#read 5, iclass 20, count 0 2006.239.07:53:22.28#ibcon#about to read 6, iclass 20, count 0 2006.239.07:53:22.28#ibcon#read 6, iclass 20, count 0 2006.239.07:53:22.28#ibcon#end of sib2, iclass 20, count 0 2006.239.07:53:22.28#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:53:22.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:53:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:53:22.28#ibcon#*before write, iclass 20, count 0 2006.239.07:53:22.28#ibcon#enter sib2, iclass 20, count 0 2006.239.07:53:22.28#ibcon#flushed, iclass 20, count 0 2006.239.07:53:22.28#ibcon#about to write, iclass 20, count 0 2006.239.07:53:22.28#ibcon#wrote, iclass 20, count 0 2006.239.07:53:22.28#ibcon#about to read 3, iclass 20, count 0 2006.239.07:53:22.32#ibcon#read 3, iclass 20, count 0 2006.239.07:53:22.32#ibcon#about to read 4, iclass 20, count 0 2006.239.07:53:22.32#ibcon#read 4, iclass 20, count 0 2006.239.07:53:22.32#ibcon#about to read 5, iclass 20, count 0 2006.239.07:53:22.32#ibcon#read 5, iclass 20, count 0 2006.239.07:53:22.32#ibcon#about to read 6, iclass 20, count 0 2006.239.07:53:22.32#ibcon#read 6, iclass 20, count 0 2006.239.07:53:22.32#ibcon#end of sib2, iclass 20, count 0 2006.239.07:53:22.32#ibcon#*after write, iclass 20, count 0 2006.239.07:53:22.32#ibcon#*before return 0, iclass 20, count 0 2006.239.07:53:22.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:22.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.07:53:22.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:53:22.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:53:22.32$vc4f8/vb=6,4 2006.239.07:53:22.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.07:53:22.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.07:53:22.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:53:22.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:22.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:22.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:22.38#ibcon#enter wrdev, iclass 22, count 2 2006.239.07:53:22.38#ibcon#first serial, iclass 22, count 2 2006.239.07:53:22.38#ibcon#enter sib2, iclass 22, count 2 2006.239.07:53:22.38#ibcon#flushed, iclass 22, count 2 2006.239.07:53:22.38#ibcon#about to write, iclass 22, count 2 2006.239.07:53:22.38#ibcon#wrote, iclass 22, count 2 2006.239.07:53:22.38#ibcon#about to read 3, iclass 22, count 2 2006.239.07:53:22.40#ibcon#read 3, iclass 22, count 2 2006.239.07:53:22.40#ibcon#about to read 4, iclass 22, count 2 2006.239.07:53:22.40#ibcon#read 4, iclass 22, count 2 2006.239.07:53:22.40#ibcon#about to read 5, iclass 22, count 2 2006.239.07:53:22.40#ibcon#read 5, iclass 22, count 2 2006.239.07:53:22.40#ibcon#about to read 6, iclass 22, count 2 2006.239.07:53:22.40#ibcon#read 6, iclass 22, count 2 2006.239.07:53:22.40#ibcon#end of sib2, iclass 22, count 2 2006.239.07:53:22.40#ibcon#*mode == 0, iclass 22, count 2 2006.239.07:53:22.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.07:53:22.40#ibcon#[27=AT06-04\r\n] 2006.239.07:53:22.40#ibcon#*before write, iclass 22, count 2 2006.239.07:53:22.40#ibcon#enter sib2, iclass 22, count 2 2006.239.07:53:22.40#ibcon#flushed, iclass 22, count 2 2006.239.07:53:22.40#ibcon#about to write, iclass 22, count 2 2006.239.07:53:22.40#ibcon#wrote, iclass 22, count 2 2006.239.07:53:22.40#ibcon#about to read 3, iclass 22, count 2 2006.239.07:53:22.43#ibcon#read 3, iclass 22, count 2 2006.239.07:53:22.43#ibcon#about to read 4, iclass 22, count 2 2006.239.07:53:22.43#ibcon#read 4, iclass 22, count 2 2006.239.07:53:22.43#ibcon#about to read 5, iclass 22, count 2 2006.239.07:53:22.43#ibcon#read 5, iclass 22, count 2 2006.239.07:53:22.43#ibcon#about to read 6, iclass 22, count 2 2006.239.07:53:22.43#ibcon#read 6, iclass 22, count 2 2006.239.07:53:22.43#ibcon#end of sib2, iclass 22, count 2 2006.239.07:53:22.43#ibcon#*after write, iclass 22, count 2 2006.239.07:53:22.43#ibcon#*before return 0, iclass 22, count 2 2006.239.07:53:22.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:22.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.07:53:22.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.07:53:22.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:53:22.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:22.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:22.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:22.55#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:53:22.55#ibcon#first serial, iclass 22, count 0 2006.239.07:53:22.55#ibcon#enter sib2, iclass 22, count 0 2006.239.07:53:22.55#ibcon#flushed, iclass 22, count 0 2006.239.07:53:22.55#ibcon#about to write, iclass 22, count 0 2006.239.07:53:22.55#ibcon#wrote, iclass 22, count 0 2006.239.07:53:22.55#ibcon#about to read 3, iclass 22, count 0 2006.239.07:53:22.57#ibcon#read 3, iclass 22, count 0 2006.239.07:53:22.57#ibcon#about to read 4, iclass 22, count 0 2006.239.07:53:22.57#ibcon#read 4, iclass 22, count 0 2006.239.07:53:22.57#ibcon#about to read 5, iclass 22, count 0 2006.239.07:53:22.57#ibcon#read 5, iclass 22, count 0 2006.239.07:53:22.57#ibcon#about to read 6, iclass 22, count 0 2006.239.07:53:22.57#ibcon#read 6, iclass 22, count 0 2006.239.07:53:22.57#ibcon#end of sib2, iclass 22, count 0 2006.239.07:53:22.57#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:53:22.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:53:22.57#ibcon#[27=USB\r\n] 2006.239.07:53:22.57#ibcon#*before write, iclass 22, count 0 2006.239.07:53:22.57#ibcon#enter sib2, iclass 22, count 0 2006.239.07:53:22.57#ibcon#flushed, iclass 22, count 0 2006.239.07:53:22.57#ibcon#about to write, iclass 22, count 0 2006.239.07:53:22.57#ibcon#wrote, iclass 22, count 0 2006.239.07:53:22.57#ibcon#about to read 3, iclass 22, count 0 2006.239.07:53:22.61#ibcon#read 3, iclass 22, count 0 2006.239.07:53:22.61#ibcon#about to read 4, iclass 22, count 0 2006.239.07:53:22.61#ibcon#read 4, iclass 22, count 0 2006.239.07:53:22.61#ibcon#about to read 5, iclass 22, count 0 2006.239.07:53:22.61#ibcon#read 5, iclass 22, count 0 2006.239.07:53:22.61#ibcon#about to read 6, iclass 22, count 0 2006.239.07:53:22.61#ibcon#read 6, iclass 22, count 0 2006.239.07:53:22.61#ibcon#end of sib2, iclass 22, count 0 2006.239.07:53:22.61#ibcon#*after write, iclass 22, count 0 2006.239.07:53:22.61#ibcon#*before return 0, iclass 22, count 0 2006.239.07:53:22.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:22.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.07:53:22.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:53:22.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:53:22.61$vc4f8/vabw=wide 2006.239.07:53:22.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.07:53:22.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.07:53:22.61#ibcon#ireg 8 cls_cnt 0 2006.239.07:53:22.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:22.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:22.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:22.61#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:53:22.61#ibcon#first serial, iclass 24, count 0 2006.239.07:53:22.61#ibcon#enter sib2, iclass 24, count 0 2006.239.07:53:22.61#ibcon#flushed, iclass 24, count 0 2006.239.07:53:22.61#ibcon#about to write, iclass 24, count 0 2006.239.07:53:22.61#ibcon#wrote, iclass 24, count 0 2006.239.07:53:22.61#ibcon#about to read 3, iclass 24, count 0 2006.239.07:53:22.62#ibcon#read 3, iclass 24, count 0 2006.239.07:53:22.62#ibcon#about to read 4, iclass 24, count 0 2006.239.07:53:22.62#ibcon#read 4, iclass 24, count 0 2006.239.07:53:22.62#ibcon#about to read 5, iclass 24, count 0 2006.239.07:53:22.62#ibcon#read 5, iclass 24, count 0 2006.239.07:53:22.62#ibcon#about to read 6, iclass 24, count 0 2006.239.07:53:22.62#ibcon#read 6, iclass 24, count 0 2006.239.07:53:22.62#ibcon#end of sib2, iclass 24, count 0 2006.239.07:53:22.62#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:53:22.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:53:22.62#ibcon#[25=BW32\r\n] 2006.239.07:53:22.62#ibcon#*before write, iclass 24, count 0 2006.239.07:53:22.62#ibcon#enter sib2, iclass 24, count 0 2006.239.07:53:22.62#ibcon#flushed, iclass 24, count 0 2006.239.07:53:22.62#ibcon#about to write, iclass 24, count 0 2006.239.07:53:22.62#ibcon#wrote, iclass 24, count 0 2006.239.07:53:22.62#ibcon#about to read 3, iclass 24, count 0 2006.239.07:53:22.65#ibcon#read 3, iclass 24, count 0 2006.239.07:53:22.65#ibcon#about to read 4, iclass 24, count 0 2006.239.07:53:22.65#ibcon#read 4, iclass 24, count 0 2006.239.07:53:22.65#ibcon#about to read 5, iclass 24, count 0 2006.239.07:53:22.65#ibcon#read 5, iclass 24, count 0 2006.239.07:53:22.65#ibcon#about to read 6, iclass 24, count 0 2006.239.07:53:22.65#ibcon#read 6, iclass 24, count 0 2006.239.07:53:22.65#ibcon#end of sib2, iclass 24, count 0 2006.239.07:53:22.65#ibcon#*after write, iclass 24, count 0 2006.239.07:53:22.65#ibcon#*before return 0, iclass 24, count 0 2006.239.07:53:22.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:22.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.07:53:22.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:53:22.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:53:22.65$vc4f8/vbbw=wide 2006.239.07:53:22.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:53:22.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:53:22.65#ibcon#ireg 8 cls_cnt 0 2006.239.07:53:22.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:53:22.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:53:22.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:53:22.73#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:53:22.73#ibcon#first serial, iclass 26, count 0 2006.239.07:53:22.73#ibcon#enter sib2, iclass 26, count 0 2006.239.07:53:22.73#ibcon#flushed, iclass 26, count 0 2006.239.07:53:22.73#ibcon#about to write, iclass 26, count 0 2006.239.07:53:22.73#ibcon#wrote, iclass 26, count 0 2006.239.07:53:22.73#ibcon#about to read 3, iclass 26, count 0 2006.239.07:53:22.75#ibcon#read 3, iclass 26, count 0 2006.239.07:53:22.75#ibcon#about to read 4, iclass 26, count 0 2006.239.07:53:22.75#ibcon#read 4, iclass 26, count 0 2006.239.07:53:22.75#ibcon#about to read 5, iclass 26, count 0 2006.239.07:53:22.75#ibcon#read 5, iclass 26, count 0 2006.239.07:53:22.75#ibcon#about to read 6, iclass 26, count 0 2006.239.07:53:22.75#ibcon#read 6, iclass 26, count 0 2006.239.07:53:22.75#ibcon#end of sib2, iclass 26, count 0 2006.239.07:53:22.75#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:53:22.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:53:22.75#ibcon#[27=BW32\r\n] 2006.239.07:53:22.75#ibcon#*before write, iclass 26, count 0 2006.239.07:53:22.75#ibcon#enter sib2, iclass 26, count 0 2006.239.07:53:22.75#ibcon#flushed, iclass 26, count 0 2006.239.07:53:22.75#ibcon#about to write, iclass 26, count 0 2006.239.07:53:22.75#ibcon#wrote, iclass 26, count 0 2006.239.07:53:22.75#ibcon#about to read 3, iclass 26, count 0 2006.239.07:53:22.78#ibcon#read 3, iclass 26, count 0 2006.239.07:53:22.78#ibcon#about to read 4, iclass 26, count 0 2006.239.07:53:22.78#ibcon#read 4, iclass 26, count 0 2006.239.07:53:22.78#ibcon#about to read 5, iclass 26, count 0 2006.239.07:53:22.78#ibcon#read 5, iclass 26, count 0 2006.239.07:53:22.78#ibcon#about to read 6, iclass 26, count 0 2006.239.07:53:22.78#ibcon#read 6, iclass 26, count 0 2006.239.07:53:22.78#ibcon#end of sib2, iclass 26, count 0 2006.239.07:53:22.78#ibcon#*after write, iclass 26, count 0 2006.239.07:53:22.78#ibcon#*before return 0, iclass 26, count 0 2006.239.07:53:22.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:53:22.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:53:22.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:53:22.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:53:22.78$4f8m12a/ifd4f 2006.239.07:53:22.78$ifd4f/lo= 2006.239.07:53:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:53:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:53:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:53:22.78$ifd4f/patch= 2006.239.07:53:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:53:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:53:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:53:22.78$4f8m12a/"form=m,16.000,1:2 2006.239.07:53:22.78$4f8m12a/"tpicd 2006.239.07:53:22.78$4f8m12a/echo=off 2006.239.07:53:22.78$4f8m12a/xlog=off 2006.239.07:53:22.78:!2006.239.07:55:00 2006.239.07:53:33.14#trakl#Source acquired 2006.239.07:53:35.14#flagr#flagr/antenna,acquired 2006.239.07:55:00.00:preob 2006.239.07:55:00.14/onsource/TRACKING 2006.239.07:55:00.14:!2006.239.07:55:10 2006.239.07:55:10.00:data_valid=on 2006.239.07:55:10.00:midob 2006.239.07:55:11.14/onsource/TRACKING 2006.239.07:55:11.14/wx/25.22,1011.6,79 2006.239.07:55:11.25/cable/+6.4141E-03 2006.239.07:55:12.34/va/01,08,usb,yes,30,32 2006.239.07:55:12.34/va/02,07,usb,yes,30,32 2006.239.07:55:12.34/va/03,07,usb,yes,29,29 2006.239.07:55:12.34/va/04,07,usb,yes,32,35 2006.239.07:55:12.34/va/05,08,usb,yes,29,30 2006.239.07:55:12.34/va/06,07,usb,yes,31,31 2006.239.07:55:12.34/va/07,07,usb,yes,31,31 2006.239.07:55:12.34/va/08,07,usb,yes,33,33 2006.239.07:55:12.57/valo/01,532.99,yes,locked 2006.239.07:55:12.57/valo/02,572.99,yes,locked 2006.239.07:55:12.57/valo/03,672.99,yes,locked 2006.239.07:55:12.57/valo/04,832.99,yes,locked 2006.239.07:55:12.57/valo/05,652.99,yes,locked 2006.239.07:55:12.57/valo/06,772.99,yes,locked 2006.239.07:55:12.57/valo/07,832.99,yes,locked 2006.239.07:55:12.57/valo/08,852.99,yes,locked 2006.239.07:55:13.66/vb/01,04,usb,yes,30,29 2006.239.07:55:13.66/vb/02,04,usb,yes,32,33 2006.239.07:55:13.66/vb/03,04,usb,yes,28,32 2006.239.07:55:13.66/vb/04,04,usb,yes,29,29 2006.239.07:55:13.66/vb/05,04,usb,yes,27,31 2006.239.07:55:13.66/vb/06,04,usb,yes,28,31 2006.239.07:55:13.66/vb/07,04,usb,yes,30,30 2006.239.07:55:13.66/vb/08,04,usb,yes,28,31 2006.239.07:55:13.89/vblo/01,632.99,yes,locked 2006.239.07:55:13.89/vblo/02,640.99,yes,locked 2006.239.07:55:13.89/vblo/03,656.99,yes,locked 2006.239.07:55:13.89/vblo/04,712.99,yes,locked 2006.239.07:55:13.89/vblo/05,744.99,yes,locked 2006.239.07:55:13.89/vblo/06,752.99,yes,locked 2006.239.07:55:13.89/vblo/07,734.99,yes,locked 2006.239.07:55:13.89/vblo/08,744.99,yes,locked 2006.239.07:55:14.04/vabw/8 2006.239.07:55:14.19/vbbw/8 2006.239.07:55:14.31/xfe/off,on,13.7 2006.239.07:55:14.68/ifatt/23,28,28,28 2006.239.07:55:15.07/fmout-gps/S +4.45E-07 2006.239.07:55:15.11:!2006.239.07:56:10 2006.239.07:56:10.00:data_valid=off 2006.239.07:56:10.00:postob 2006.239.07:56:10.09/cable/+6.4161E-03 2006.239.07:56:10.09/wx/25.21,1011.6,79 2006.239.07:56:11.08/fmout-gps/S +4.45E-07 2006.239.07:56:11.08:scan_name=239-0758,k06239,60 2006.239.07:56:11.09:source=3c418,203837.03,511912.7,2000.0,cw 2006.239.07:56:11.14#flagr#flagr/antenna,new-source 2006.239.07:56:12.14:checkk5 2006.239.07:56:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:56:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:56:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:56:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:56:14.03/chk_obsdata//k5ts1/T2390755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:56:14.41/chk_obsdata//k5ts2/T2390755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:56:14.78/chk_obsdata//k5ts3/T2390755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:56:15.15/chk_obsdata//k5ts4/T2390755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:56:15.84/k5log//k5ts1_log_newline 2006.239.07:56:16.53/k5log//k5ts2_log_newline 2006.239.07:56:17.22/k5log//k5ts3_log_newline 2006.239.07:56:17.91/k5log//k5ts4_log_newline 2006.239.07:56:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:56:17.93:4f8m12a=2 2006.239.07:56:17.93$4f8m12a/echo=on 2006.239.07:56:17.93$4f8m12a/pcalon 2006.239.07:56:17.93$pcalon/"no phase cal control is implemented here 2006.239.07:56:17.93$4f8m12a/"tpicd=stop 2006.239.07:56:17.93$4f8m12a/vc4f8 2006.239.07:56:17.93$vc4f8/valo=1,532.99 2006.239.07:56:17.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:56:17.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:56:17.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:17.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:17.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:17.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:17.93#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:56:17.93#ibcon#first serial, iclass 25, count 0 2006.239.07:56:17.93#ibcon#enter sib2, iclass 25, count 0 2006.239.07:56:17.93#ibcon#flushed, iclass 25, count 0 2006.239.07:56:17.93#ibcon#about to write, iclass 25, count 0 2006.239.07:56:17.93#ibcon#wrote, iclass 25, count 0 2006.239.07:56:17.93#ibcon#about to read 3, iclass 25, count 0 2006.239.07:56:17.95#ibcon#read 3, iclass 25, count 0 2006.239.07:56:17.95#ibcon#about to read 4, iclass 25, count 0 2006.239.07:56:17.95#ibcon#read 4, iclass 25, count 0 2006.239.07:56:17.95#ibcon#about to read 5, iclass 25, count 0 2006.239.07:56:17.95#ibcon#read 5, iclass 25, count 0 2006.239.07:56:17.95#ibcon#about to read 6, iclass 25, count 0 2006.239.07:56:17.95#ibcon#read 6, iclass 25, count 0 2006.239.07:56:17.95#ibcon#end of sib2, iclass 25, count 0 2006.239.07:56:17.95#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:56:17.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:56:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:56:17.95#ibcon#*before write, iclass 25, count 0 2006.239.07:56:17.95#ibcon#enter sib2, iclass 25, count 0 2006.239.07:56:17.95#ibcon#flushed, iclass 25, count 0 2006.239.07:56:17.95#ibcon#about to write, iclass 25, count 0 2006.239.07:56:17.95#ibcon#wrote, iclass 25, count 0 2006.239.07:56:17.95#ibcon#about to read 3, iclass 25, count 0 2006.239.07:56:18.00#ibcon#read 3, iclass 25, count 0 2006.239.07:56:18.00#ibcon#about to read 4, iclass 25, count 0 2006.239.07:56:18.00#ibcon#read 4, iclass 25, count 0 2006.239.07:56:18.00#ibcon#about to read 5, iclass 25, count 0 2006.239.07:56:18.00#ibcon#read 5, iclass 25, count 0 2006.239.07:56:18.00#ibcon#about to read 6, iclass 25, count 0 2006.239.07:56:18.00#ibcon#read 6, iclass 25, count 0 2006.239.07:56:18.00#ibcon#end of sib2, iclass 25, count 0 2006.239.07:56:18.00#ibcon#*after write, iclass 25, count 0 2006.239.07:56:18.00#ibcon#*before return 0, iclass 25, count 0 2006.239.07:56:18.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:18.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:18.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:56:18.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:56:18.00$vc4f8/va=1,8 2006.239.07:56:18.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:56:18.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:56:18.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:18.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:18.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:18.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:18.00#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:56:18.00#ibcon#first serial, iclass 27, count 2 2006.239.07:56:18.00#ibcon#enter sib2, iclass 27, count 2 2006.239.07:56:18.00#ibcon#flushed, iclass 27, count 2 2006.239.07:56:18.00#ibcon#about to write, iclass 27, count 2 2006.239.07:56:18.00#ibcon#wrote, iclass 27, count 2 2006.239.07:56:18.00#ibcon#about to read 3, iclass 27, count 2 2006.239.07:56:18.02#ibcon#read 3, iclass 27, count 2 2006.239.07:56:18.02#ibcon#about to read 4, iclass 27, count 2 2006.239.07:56:18.02#ibcon#read 4, iclass 27, count 2 2006.239.07:56:18.02#ibcon#about to read 5, iclass 27, count 2 2006.239.07:56:18.02#ibcon#read 5, iclass 27, count 2 2006.239.07:56:18.02#ibcon#about to read 6, iclass 27, count 2 2006.239.07:56:18.02#ibcon#read 6, iclass 27, count 2 2006.239.07:56:18.02#ibcon#end of sib2, iclass 27, count 2 2006.239.07:56:18.02#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:56:18.02#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:56:18.02#ibcon#[25=AT01-08\r\n] 2006.239.07:56:18.02#ibcon#*before write, iclass 27, count 2 2006.239.07:56:18.02#ibcon#enter sib2, iclass 27, count 2 2006.239.07:56:18.02#ibcon#flushed, iclass 27, count 2 2006.239.07:56:18.02#ibcon#about to write, iclass 27, count 2 2006.239.07:56:18.02#ibcon#wrote, iclass 27, count 2 2006.239.07:56:18.02#ibcon#about to read 3, iclass 27, count 2 2006.239.07:56:18.05#ibcon#read 3, iclass 27, count 2 2006.239.07:56:18.05#ibcon#about to read 4, iclass 27, count 2 2006.239.07:56:18.05#ibcon#read 4, iclass 27, count 2 2006.239.07:56:18.05#ibcon#about to read 5, iclass 27, count 2 2006.239.07:56:18.05#ibcon#read 5, iclass 27, count 2 2006.239.07:56:18.05#ibcon#about to read 6, iclass 27, count 2 2006.239.07:56:18.05#ibcon#read 6, iclass 27, count 2 2006.239.07:56:18.05#ibcon#end of sib2, iclass 27, count 2 2006.239.07:56:18.05#ibcon#*after write, iclass 27, count 2 2006.239.07:56:18.05#ibcon#*before return 0, iclass 27, count 2 2006.239.07:56:18.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:18.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:18.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:56:18.05#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:18.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:18.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:18.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:18.17#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:56:18.17#ibcon#first serial, iclass 27, count 0 2006.239.07:56:18.17#ibcon#enter sib2, iclass 27, count 0 2006.239.07:56:18.17#ibcon#flushed, iclass 27, count 0 2006.239.07:56:18.17#ibcon#about to write, iclass 27, count 0 2006.239.07:56:18.17#ibcon#wrote, iclass 27, count 0 2006.239.07:56:18.17#ibcon#about to read 3, iclass 27, count 0 2006.239.07:56:18.19#ibcon#read 3, iclass 27, count 0 2006.239.07:56:18.19#ibcon#about to read 4, iclass 27, count 0 2006.239.07:56:18.19#ibcon#read 4, iclass 27, count 0 2006.239.07:56:18.19#ibcon#about to read 5, iclass 27, count 0 2006.239.07:56:18.19#ibcon#read 5, iclass 27, count 0 2006.239.07:56:18.19#ibcon#about to read 6, iclass 27, count 0 2006.239.07:56:18.19#ibcon#read 6, iclass 27, count 0 2006.239.07:56:18.19#ibcon#end of sib2, iclass 27, count 0 2006.239.07:56:18.19#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:56:18.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:56:18.19#ibcon#[25=USB\r\n] 2006.239.07:56:18.19#ibcon#*before write, iclass 27, count 0 2006.239.07:56:18.19#ibcon#enter sib2, iclass 27, count 0 2006.239.07:56:18.19#ibcon#flushed, iclass 27, count 0 2006.239.07:56:18.19#ibcon#about to write, iclass 27, count 0 2006.239.07:56:18.19#ibcon#wrote, iclass 27, count 0 2006.239.07:56:18.19#ibcon#about to read 3, iclass 27, count 0 2006.239.07:56:18.22#ibcon#read 3, iclass 27, count 0 2006.239.07:56:18.22#ibcon#about to read 4, iclass 27, count 0 2006.239.07:56:18.22#ibcon#read 4, iclass 27, count 0 2006.239.07:56:18.22#ibcon#about to read 5, iclass 27, count 0 2006.239.07:56:18.22#ibcon#read 5, iclass 27, count 0 2006.239.07:56:18.22#ibcon#about to read 6, iclass 27, count 0 2006.239.07:56:18.22#ibcon#read 6, iclass 27, count 0 2006.239.07:56:18.22#ibcon#end of sib2, iclass 27, count 0 2006.239.07:56:18.22#ibcon#*after write, iclass 27, count 0 2006.239.07:56:18.22#ibcon#*before return 0, iclass 27, count 0 2006.239.07:56:18.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:18.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:18.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:56:18.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:56:18.22$vc4f8/valo=2,572.99 2006.239.07:56:18.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:56:18.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:56:18.22#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:18.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:18.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:18.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:18.22#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:56:18.22#ibcon#first serial, iclass 29, count 0 2006.239.07:56:18.22#ibcon#enter sib2, iclass 29, count 0 2006.239.07:56:18.22#ibcon#flushed, iclass 29, count 0 2006.239.07:56:18.22#ibcon#about to write, iclass 29, count 0 2006.239.07:56:18.22#ibcon#wrote, iclass 29, count 0 2006.239.07:56:18.22#ibcon#about to read 3, iclass 29, count 0 2006.239.07:56:18.24#ibcon#read 3, iclass 29, count 0 2006.239.07:56:18.24#ibcon#about to read 4, iclass 29, count 0 2006.239.07:56:18.24#ibcon#read 4, iclass 29, count 0 2006.239.07:56:18.24#ibcon#about to read 5, iclass 29, count 0 2006.239.07:56:18.24#ibcon#read 5, iclass 29, count 0 2006.239.07:56:18.24#ibcon#about to read 6, iclass 29, count 0 2006.239.07:56:18.24#ibcon#read 6, iclass 29, count 0 2006.239.07:56:18.24#ibcon#end of sib2, iclass 29, count 0 2006.239.07:56:18.24#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:56:18.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:56:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:56:18.24#ibcon#*before write, iclass 29, count 0 2006.239.07:56:18.24#ibcon#enter sib2, iclass 29, count 0 2006.239.07:56:18.24#ibcon#flushed, iclass 29, count 0 2006.239.07:56:18.24#ibcon#about to write, iclass 29, count 0 2006.239.07:56:18.24#ibcon#wrote, iclass 29, count 0 2006.239.07:56:18.24#ibcon#about to read 3, iclass 29, count 0 2006.239.07:56:18.28#ibcon#read 3, iclass 29, count 0 2006.239.07:56:18.28#ibcon#about to read 4, iclass 29, count 0 2006.239.07:56:18.28#ibcon#read 4, iclass 29, count 0 2006.239.07:56:18.28#ibcon#about to read 5, iclass 29, count 0 2006.239.07:56:18.28#ibcon#read 5, iclass 29, count 0 2006.239.07:56:18.28#ibcon#about to read 6, iclass 29, count 0 2006.239.07:56:18.28#ibcon#read 6, iclass 29, count 0 2006.239.07:56:18.28#ibcon#end of sib2, iclass 29, count 0 2006.239.07:56:18.28#ibcon#*after write, iclass 29, count 0 2006.239.07:56:18.28#ibcon#*before return 0, iclass 29, count 0 2006.239.07:56:18.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:18.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:18.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:56:18.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:56:18.28$vc4f8/va=2,7 2006.239.07:56:18.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:56:18.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:56:18.28#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:18.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:18.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:18.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:18.34#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:56:18.34#ibcon#first serial, iclass 31, count 2 2006.239.07:56:18.34#ibcon#enter sib2, iclass 31, count 2 2006.239.07:56:18.34#ibcon#flushed, iclass 31, count 2 2006.239.07:56:18.34#ibcon#about to write, iclass 31, count 2 2006.239.07:56:18.34#ibcon#wrote, iclass 31, count 2 2006.239.07:56:18.34#ibcon#about to read 3, iclass 31, count 2 2006.239.07:56:18.36#ibcon#read 3, iclass 31, count 2 2006.239.07:56:18.36#ibcon#about to read 4, iclass 31, count 2 2006.239.07:56:18.36#ibcon#read 4, iclass 31, count 2 2006.239.07:56:18.36#ibcon#about to read 5, iclass 31, count 2 2006.239.07:56:18.36#ibcon#read 5, iclass 31, count 2 2006.239.07:56:18.36#ibcon#about to read 6, iclass 31, count 2 2006.239.07:56:18.36#ibcon#read 6, iclass 31, count 2 2006.239.07:56:18.36#ibcon#end of sib2, iclass 31, count 2 2006.239.07:56:18.36#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:56:18.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:56:18.36#ibcon#[25=AT02-07\r\n] 2006.239.07:56:18.36#ibcon#*before write, iclass 31, count 2 2006.239.07:56:18.36#ibcon#enter sib2, iclass 31, count 2 2006.239.07:56:18.36#ibcon#flushed, iclass 31, count 2 2006.239.07:56:18.36#ibcon#about to write, iclass 31, count 2 2006.239.07:56:18.36#ibcon#wrote, iclass 31, count 2 2006.239.07:56:18.36#ibcon#about to read 3, iclass 31, count 2 2006.239.07:56:18.39#ibcon#read 3, iclass 31, count 2 2006.239.07:56:18.39#ibcon#about to read 4, iclass 31, count 2 2006.239.07:56:18.39#ibcon#read 4, iclass 31, count 2 2006.239.07:56:18.39#ibcon#about to read 5, iclass 31, count 2 2006.239.07:56:18.39#ibcon#read 5, iclass 31, count 2 2006.239.07:56:18.39#ibcon#about to read 6, iclass 31, count 2 2006.239.07:56:18.39#ibcon#read 6, iclass 31, count 2 2006.239.07:56:18.39#ibcon#end of sib2, iclass 31, count 2 2006.239.07:56:18.39#ibcon#*after write, iclass 31, count 2 2006.239.07:56:18.39#ibcon#*before return 0, iclass 31, count 2 2006.239.07:56:18.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:18.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:18.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:56:18.39#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:18.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:18.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:18.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:18.51#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:56:18.51#ibcon#first serial, iclass 31, count 0 2006.239.07:56:18.51#ibcon#enter sib2, iclass 31, count 0 2006.239.07:56:18.51#ibcon#flushed, iclass 31, count 0 2006.239.07:56:18.51#ibcon#about to write, iclass 31, count 0 2006.239.07:56:18.51#ibcon#wrote, iclass 31, count 0 2006.239.07:56:18.51#ibcon#about to read 3, iclass 31, count 0 2006.239.07:56:18.53#ibcon#read 3, iclass 31, count 0 2006.239.07:56:18.53#ibcon#about to read 4, iclass 31, count 0 2006.239.07:56:18.53#ibcon#read 4, iclass 31, count 0 2006.239.07:56:18.53#ibcon#about to read 5, iclass 31, count 0 2006.239.07:56:18.53#ibcon#read 5, iclass 31, count 0 2006.239.07:56:18.53#ibcon#about to read 6, iclass 31, count 0 2006.239.07:56:18.53#ibcon#read 6, iclass 31, count 0 2006.239.07:56:18.53#ibcon#end of sib2, iclass 31, count 0 2006.239.07:56:18.53#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:56:18.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:56:18.53#ibcon#[25=USB\r\n] 2006.239.07:56:18.53#ibcon#*before write, iclass 31, count 0 2006.239.07:56:18.53#ibcon#enter sib2, iclass 31, count 0 2006.239.07:56:18.53#ibcon#flushed, iclass 31, count 0 2006.239.07:56:18.53#ibcon#about to write, iclass 31, count 0 2006.239.07:56:18.53#ibcon#wrote, iclass 31, count 0 2006.239.07:56:18.53#ibcon#about to read 3, iclass 31, count 0 2006.239.07:56:18.58#ibcon#read 3, iclass 31, count 0 2006.239.07:56:18.58#ibcon#about to read 4, iclass 31, count 0 2006.239.07:56:18.58#ibcon#read 4, iclass 31, count 0 2006.239.07:56:18.58#ibcon#about to read 5, iclass 31, count 0 2006.239.07:56:18.58#ibcon#read 5, iclass 31, count 0 2006.239.07:56:18.58#ibcon#about to read 6, iclass 31, count 0 2006.239.07:56:18.58#ibcon#read 6, iclass 31, count 0 2006.239.07:56:18.58#ibcon#end of sib2, iclass 31, count 0 2006.239.07:56:18.58#ibcon#*after write, iclass 31, count 0 2006.239.07:56:18.58#ibcon#*before return 0, iclass 31, count 0 2006.239.07:56:18.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:18.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:18.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:56:18.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:56:18.58$vc4f8/valo=3,672.99 2006.239.07:56:18.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:56:18.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:56:18.58#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:18.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:18.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:18.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:18.58#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:56:18.58#ibcon#first serial, iclass 33, count 0 2006.239.07:56:18.58#ibcon#enter sib2, iclass 33, count 0 2006.239.07:56:18.58#ibcon#flushed, iclass 33, count 0 2006.239.07:56:18.58#ibcon#about to write, iclass 33, count 0 2006.239.07:56:18.58#ibcon#wrote, iclass 33, count 0 2006.239.07:56:18.58#ibcon#about to read 3, iclass 33, count 0 2006.239.07:56:18.59#ibcon#read 3, iclass 33, count 0 2006.239.07:56:18.59#ibcon#about to read 4, iclass 33, count 0 2006.239.07:56:18.59#ibcon#read 4, iclass 33, count 0 2006.239.07:56:18.59#ibcon#about to read 5, iclass 33, count 0 2006.239.07:56:18.59#ibcon#read 5, iclass 33, count 0 2006.239.07:56:18.59#ibcon#about to read 6, iclass 33, count 0 2006.239.07:56:18.60#ibcon#read 6, iclass 33, count 0 2006.239.07:56:18.60#ibcon#end of sib2, iclass 33, count 0 2006.239.07:56:18.60#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:56:18.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:56:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:56:18.60#ibcon#*before write, iclass 33, count 0 2006.239.07:56:18.60#ibcon#enter sib2, iclass 33, count 0 2006.239.07:56:18.60#ibcon#flushed, iclass 33, count 0 2006.239.07:56:18.60#ibcon#about to write, iclass 33, count 0 2006.239.07:56:18.60#ibcon#wrote, iclass 33, count 0 2006.239.07:56:18.60#ibcon#about to read 3, iclass 33, count 0 2006.239.07:56:18.64#ibcon#read 3, iclass 33, count 0 2006.239.07:56:18.64#ibcon#about to read 4, iclass 33, count 0 2006.239.07:56:18.64#ibcon#read 4, iclass 33, count 0 2006.239.07:56:18.64#ibcon#about to read 5, iclass 33, count 0 2006.239.07:56:18.64#ibcon#read 5, iclass 33, count 0 2006.239.07:56:18.64#ibcon#about to read 6, iclass 33, count 0 2006.239.07:56:18.64#ibcon#read 6, iclass 33, count 0 2006.239.07:56:18.64#ibcon#end of sib2, iclass 33, count 0 2006.239.07:56:18.64#ibcon#*after write, iclass 33, count 0 2006.239.07:56:18.64#ibcon#*before return 0, iclass 33, count 0 2006.239.07:56:18.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:18.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:18.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:56:18.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:56:18.64$vc4f8/va=3,7 2006.239.07:56:18.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:56:18.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:56:18.64#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:18.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:18.70#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:18.70#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:18.70#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:56:18.70#ibcon#first serial, iclass 35, count 2 2006.239.07:56:18.70#ibcon#enter sib2, iclass 35, count 2 2006.239.07:56:18.70#ibcon#flushed, iclass 35, count 2 2006.239.07:56:18.70#ibcon#about to write, iclass 35, count 2 2006.239.07:56:18.70#ibcon#wrote, iclass 35, count 2 2006.239.07:56:18.70#ibcon#about to read 3, iclass 35, count 2 2006.239.07:56:18.72#ibcon#read 3, iclass 35, count 2 2006.239.07:56:18.72#ibcon#about to read 4, iclass 35, count 2 2006.239.07:56:18.72#ibcon#read 4, iclass 35, count 2 2006.239.07:56:18.72#ibcon#about to read 5, iclass 35, count 2 2006.239.07:56:18.72#ibcon#read 5, iclass 35, count 2 2006.239.07:56:18.72#ibcon#about to read 6, iclass 35, count 2 2006.239.07:56:18.72#ibcon#read 6, iclass 35, count 2 2006.239.07:56:18.72#ibcon#end of sib2, iclass 35, count 2 2006.239.07:56:18.72#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:56:18.72#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:56:18.72#ibcon#[25=AT03-07\r\n] 2006.239.07:56:18.72#ibcon#*before write, iclass 35, count 2 2006.239.07:56:18.72#ibcon#enter sib2, iclass 35, count 2 2006.239.07:56:18.72#ibcon#flushed, iclass 35, count 2 2006.239.07:56:18.72#ibcon#about to write, iclass 35, count 2 2006.239.07:56:18.72#ibcon#wrote, iclass 35, count 2 2006.239.07:56:18.72#ibcon#about to read 3, iclass 35, count 2 2006.239.07:56:18.75#ibcon#read 3, iclass 35, count 2 2006.239.07:56:18.75#ibcon#about to read 4, iclass 35, count 2 2006.239.07:56:18.75#ibcon#read 4, iclass 35, count 2 2006.239.07:56:18.75#ibcon#about to read 5, iclass 35, count 2 2006.239.07:56:18.75#ibcon#read 5, iclass 35, count 2 2006.239.07:56:18.75#ibcon#about to read 6, iclass 35, count 2 2006.239.07:56:18.75#ibcon#read 6, iclass 35, count 2 2006.239.07:56:18.75#ibcon#end of sib2, iclass 35, count 2 2006.239.07:56:18.75#ibcon#*after write, iclass 35, count 2 2006.239.07:56:18.75#ibcon#*before return 0, iclass 35, count 2 2006.239.07:56:18.75#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:18.75#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:18.75#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:56:18.75#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:18.75#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:18.87#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:18.87#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:18.87#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:56:18.87#ibcon#first serial, iclass 35, count 0 2006.239.07:56:18.87#ibcon#enter sib2, iclass 35, count 0 2006.239.07:56:18.87#ibcon#flushed, iclass 35, count 0 2006.239.07:56:18.87#ibcon#about to write, iclass 35, count 0 2006.239.07:56:18.87#ibcon#wrote, iclass 35, count 0 2006.239.07:56:18.87#ibcon#about to read 3, iclass 35, count 0 2006.239.07:56:18.89#ibcon#read 3, iclass 35, count 0 2006.239.07:56:18.89#ibcon#about to read 4, iclass 35, count 0 2006.239.07:56:18.89#ibcon#read 4, iclass 35, count 0 2006.239.07:56:18.89#ibcon#about to read 5, iclass 35, count 0 2006.239.07:56:18.89#ibcon#read 5, iclass 35, count 0 2006.239.07:56:18.89#ibcon#about to read 6, iclass 35, count 0 2006.239.07:56:18.89#ibcon#read 6, iclass 35, count 0 2006.239.07:56:18.89#ibcon#end of sib2, iclass 35, count 0 2006.239.07:56:18.89#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:56:18.89#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:56:18.89#ibcon#[25=USB\r\n] 2006.239.07:56:18.89#ibcon#*before write, iclass 35, count 0 2006.239.07:56:18.89#ibcon#enter sib2, iclass 35, count 0 2006.239.07:56:18.89#ibcon#flushed, iclass 35, count 0 2006.239.07:56:18.89#ibcon#about to write, iclass 35, count 0 2006.239.07:56:18.89#ibcon#wrote, iclass 35, count 0 2006.239.07:56:18.89#ibcon#about to read 3, iclass 35, count 0 2006.239.07:56:18.92#ibcon#read 3, iclass 35, count 0 2006.239.07:56:18.92#ibcon#about to read 4, iclass 35, count 0 2006.239.07:56:18.92#ibcon#read 4, iclass 35, count 0 2006.239.07:56:18.92#ibcon#about to read 5, iclass 35, count 0 2006.239.07:56:18.92#ibcon#read 5, iclass 35, count 0 2006.239.07:56:18.92#ibcon#about to read 6, iclass 35, count 0 2006.239.07:56:18.92#ibcon#read 6, iclass 35, count 0 2006.239.07:56:18.92#ibcon#end of sib2, iclass 35, count 0 2006.239.07:56:18.92#ibcon#*after write, iclass 35, count 0 2006.239.07:56:18.92#ibcon#*before return 0, iclass 35, count 0 2006.239.07:56:18.92#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:18.92#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:18.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:56:18.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:56:18.92$vc4f8/valo=4,832.99 2006.239.07:56:18.92#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:56:18.92#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:56:18.92#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:18.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:18.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:18.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:18.92#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:56:18.92#ibcon#first serial, iclass 37, count 0 2006.239.07:56:18.92#ibcon#enter sib2, iclass 37, count 0 2006.239.07:56:18.92#ibcon#flushed, iclass 37, count 0 2006.239.07:56:18.92#ibcon#about to write, iclass 37, count 0 2006.239.07:56:18.92#ibcon#wrote, iclass 37, count 0 2006.239.07:56:18.92#ibcon#about to read 3, iclass 37, count 0 2006.239.07:56:18.94#ibcon#read 3, iclass 37, count 0 2006.239.07:56:18.94#ibcon#about to read 4, iclass 37, count 0 2006.239.07:56:18.94#ibcon#read 4, iclass 37, count 0 2006.239.07:56:18.94#ibcon#about to read 5, iclass 37, count 0 2006.239.07:56:18.94#ibcon#read 5, iclass 37, count 0 2006.239.07:56:18.94#ibcon#about to read 6, iclass 37, count 0 2006.239.07:56:18.94#ibcon#read 6, iclass 37, count 0 2006.239.07:56:18.94#ibcon#end of sib2, iclass 37, count 0 2006.239.07:56:18.94#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:56:18.94#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:56:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:56:18.94#ibcon#*before write, iclass 37, count 0 2006.239.07:56:18.94#ibcon#enter sib2, iclass 37, count 0 2006.239.07:56:18.94#ibcon#flushed, iclass 37, count 0 2006.239.07:56:18.94#ibcon#about to write, iclass 37, count 0 2006.239.07:56:18.94#ibcon#wrote, iclass 37, count 0 2006.239.07:56:18.94#ibcon#about to read 3, iclass 37, count 0 2006.239.07:56:18.98#ibcon#read 3, iclass 37, count 0 2006.239.07:56:18.98#ibcon#about to read 4, iclass 37, count 0 2006.239.07:56:18.98#ibcon#read 4, iclass 37, count 0 2006.239.07:56:18.98#ibcon#about to read 5, iclass 37, count 0 2006.239.07:56:18.98#ibcon#read 5, iclass 37, count 0 2006.239.07:56:18.98#ibcon#about to read 6, iclass 37, count 0 2006.239.07:56:18.98#ibcon#read 6, iclass 37, count 0 2006.239.07:56:18.98#ibcon#end of sib2, iclass 37, count 0 2006.239.07:56:18.98#ibcon#*after write, iclass 37, count 0 2006.239.07:56:18.98#ibcon#*before return 0, iclass 37, count 0 2006.239.07:56:18.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:18.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:18.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:56:18.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:56:18.98$vc4f8/va=4,7 2006.239.07:56:18.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:56:18.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:56:18.98#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:18.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:19.04#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:19.04#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:19.04#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:56:19.04#ibcon#first serial, iclass 39, count 2 2006.239.07:56:19.04#ibcon#enter sib2, iclass 39, count 2 2006.239.07:56:19.04#ibcon#flushed, iclass 39, count 2 2006.239.07:56:19.04#ibcon#about to write, iclass 39, count 2 2006.239.07:56:19.04#ibcon#wrote, iclass 39, count 2 2006.239.07:56:19.04#ibcon#about to read 3, iclass 39, count 2 2006.239.07:56:19.06#ibcon#read 3, iclass 39, count 2 2006.239.07:56:19.06#ibcon#about to read 4, iclass 39, count 2 2006.239.07:56:19.06#ibcon#read 4, iclass 39, count 2 2006.239.07:56:19.06#ibcon#about to read 5, iclass 39, count 2 2006.239.07:56:19.06#ibcon#read 5, iclass 39, count 2 2006.239.07:56:19.06#ibcon#about to read 6, iclass 39, count 2 2006.239.07:56:19.06#ibcon#read 6, iclass 39, count 2 2006.239.07:56:19.06#ibcon#end of sib2, iclass 39, count 2 2006.239.07:56:19.06#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:56:19.06#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:56:19.06#ibcon#[25=AT04-07\r\n] 2006.239.07:56:19.06#ibcon#*before write, iclass 39, count 2 2006.239.07:56:19.06#ibcon#enter sib2, iclass 39, count 2 2006.239.07:56:19.06#ibcon#flushed, iclass 39, count 2 2006.239.07:56:19.06#ibcon#about to write, iclass 39, count 2 2006.239.07:56:19.06#ibcon#wrote, iclass 39, count 2 2006.239.07:56:19.06#ibcon#about to read 3, iclass 39, count 2 2006.239.07:56:19.09#ibcon#read 3, iclass 39, count 2 2006.239.07:56:19.09#ibcon#about to read 4, iclass 39, count 2 2006.239.07:56:19.09#ibcon#read 4, iclass 39, count 2 2006.239.07:56:19.09#ibcon#about to read 5, iclass 39, count 2 2006.239.07:56:19.09#ibcon#read 5, iclass 39, count 2 2006.239.07:56:19.09#ibcon#about to read 6, iclass 39, count 2 2006.239.07:56:19.09#ibcon#read 6, iclass 39, count 2 2006.239.07:56:19.09#ibcon#end of sib2, iclass 39, count 2 2006.239.07:56:19.09#ibcon#*after write, iclass 39, count 2 2006.239.07:56:19.09#ibcon#*before return 0, iclass 39, count 2 2006.239.07:56:19.09#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:19.09#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:19.09#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:56:19.09#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:19.09#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:19.21#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:19.21#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:19.21#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:56:19.21#ibcon#first serial, iclass 39, count 0 2006.239.07:56:19.21#ibcon#enter sib2, iclass 39, count 0 2006.239.07:56:19.21#ibcon#flushed, iclass 39, count 0 2006.239.07:56:19.21#ibcon#about to write, iclass 39, count 0 2006.239.07:56:19.21#ibcon#wrote, iclass 39, count 0 2006.239.07:56:19.21#ibcon#about to read 3, iclass 39, count 0 2006.239.07:56:19.23#ibcon#read 3, iclass 39, count 0 2006.239.07:56:19.23#ibcon#about to read 4, iclass 39, count 0 2006.239.07:56:19.23#ibcon#read 4, iclass 39, count 0 2006.239.07:56:19.23#ibcon#about to read 5, iclass 39, count 0 2006.239.07:56:19.23#ibcon#read 5, iclass 39, count 0 2006.239.07:56:19.23#ibcon#about to read 6, iclass 39, count 0 2006.239.07:56:19.23#ibcon#read 6, iclass 39, count 0 2006.239.07:56:19.23#ibcon#end of sib2, iclass 39, count 0 2006.239.07:56:19.23#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:56:19.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:56:19.23#ibcon#[25=USB\r\n] 2006.239.07:56:19.23#ibcon#*before write, iclass 39, count 0 2006.239.07:56:19.23#ibcon#enter sib2, iclass 39, count 0 2006.239.07:56:19.23#ibcon#flushed, iclass 39, count 0 2006.239.07:56:19.23#ibcon#about to write, iclass 39, count 0 2006.239.07:56:19.23#ibcon#wrote, iclass 39, count 0 2006.239.07:56:19.23#ibcon#about to read 3, iclass 39, count 0 2006.239.07:56:19.26#ibcon#read 3, iclass 39, count 0 2006.239.07:56:19.26#ibcon#about to read 4, iclass 39, count 0 2006.239.07:56:19.26#ibcon#read 4, iclass 39, count 0 2006.239.07:56:19.26#ibcon#about to read 5, iclass 39, count 0 2006.239.07:56:19.26#ibcon#read 5, iclass 39, count 0 2006.239.07:56:19.26#ibcon#about to read 6, iclass 39, count 0 2006.239.07:56:19.26#ibcon#read 6, iclass 39, count 0 2006.239.07:56:19.26#ibcon#end of sib2, iclass 39, count 0 2006.239.07:56:19.26#ibcon#*after write, iclass 39, count 0 2006.239.07:56:19.26#ibcon#*before return 0, iclass 39, count 0 2006.239.07:56:19.26#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:19.26#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:19.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:56:19.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:56:19.26$vc4f8/valo=5,652.99 2006.239.07:56:19.26#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:56:19.26#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:56:19.26#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:19.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:19.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:19.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:19.26#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:56:19.26#ibcon#first serial, iclass 3, count 0 2006.239.07:56:19.26#ibcon#enter sib2, iclass 3, count 0 2006.239.07:56:19.26#ibcon#flushed, iclass 3, count 0 2006.239.07:56:19.26#ibcon#about to write, iclass 3, count 0 2006.239.07:56:19.26#ibcon#wrote, iclass 3, count 0 2006.239.07:56:19.26#ibcon#about to read 3, iclass 3, count 0 2006.239.07:56:19.28#ibcon#read 3, iclass 3, count 0 2006.239.07:56:19.28#ibcon#about to read 4, iclass 3, count 0 2006.239.07:56:19.28#ibcon#read 4, iclass 3, count 0 2006.239.07:56:19.28#ibcon#about to read 5, iclass 3, count 0 2006.239.07:56:19.28#ibcon#read 5, iclass 3, count 0 2006.239.07:56:19.28#ibcon#about to read 6, iclass 3, count 0 2006.239.07:56:19.28#ibcon#read 6, iclass 3, count 0 2006.239.07:56:19.28#ibcon#end of sib2, iclass 3, count 0 2006.239.07:56:19.28#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:56:19.28#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:56:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:56:19.28#ibcon#*before write, iclass 3, count 0 2006.239.07:56:19.28#ibcon#enter sib2, iclass 3, count 0 2006.239.07:56:19.28#ibcon#flushed, iclass 3, count 0 2006.239.07:56:19.28#ibcon#about to write, iclass 3, count 0 2006.239.07:56:19.28#ibcon#wrote, iclass 3, count 0 2006.239.07:56:19.28#ibcon#about to read 3, iclass 3, count 0 2006.239.07:56:19.32#ibcon#read 3, iclass 3, count 0 2006.239.07:56:19.32#ibcon#about to read 4, iclass 3, count 0 2006.239.07:56:19.32#ibcon#read 4, iclass 3, count 0 2006.239.07:56:19.32#ibcon#about to read 5, iclass 3, count 0 2006.239.07:56:19.32#ibcon#read 5, iclass 3, count 0 2006.239.07:56:19.32#ibcon#about to read 6, iclass 3, count 0 2006.239.07:56:19.32#ibcon#read 6, iclass 3, count 0 2006.239.07:56:19.32#ibcon#end of sib2, iclass 3, count 0 2006.239.07:56:19.32#ibcon#*after write, iclass 3, count 0 2006.239.07:56:19.32#ibcon#*before return 0, iclass 3, count 0 2006.239.07:56:19.32#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:19.32#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:19.32#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:56:19.32#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:56:19.32$vc4f8/va=5,8 2006.239.07:56:19.32#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.07:56:19.32#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.07:56:19.32#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:19.32#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:19.38#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:19.38#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:19.38#ibcon#enter wrdev, iclass 5, count 2 2006.239.07:56:19.38#ibcon#first serial, iclass 5, count 2 2006.239.07:56:19.38#ibcon#enter sib2, iclass 5, count 2 2006.239.07:56:19.38#ibcon#flushed, iclass 5, count 2 2006.239.07:56:19.38#ibcon#about to write, iclass 5, count 2 2006.239.07:56:19.38#ibcon#wrote, iclass 5, count 2 2006.239.07:56:19.38#ibcon#about to read 3, iclass 5, count 2 2006.239.07:56:19.40#ibcon#read 3, iclass 5, count 2 2006.239.07:56:19.40#ibcon#about to read 4, iclass 5, count 2 2006.239.07:56:19.40#ibcon#read 4, iclass 5, count 2 2006.239.07:56:19.40#ibcon#about to read 5, iclass 5, count 2 2006.239.07:56:19.40#ibcon#read 5, iclass 5, count 2 2006.239.07:56:19.40#ibcon#about to read 6, iclass 5, count 2 2006.239.07:56:19.40#ibcon#read 6, iclass 5, count 2 2006.239.07:56:19.40#ibcon#end of sib2, iclass 5, count 2 2006.239.07:56:19.40#ibcon#*mode == 0, iclass 5, count 2 2006.239.07:56:19.40#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.07:56:19.40#ibcon#[25=AT05-08\r\n] 2006.239.07:56:19.40#ibcon#*before write, iclass 5, count 2 2006.239.07:56:19.40#ibcon#enter sib2, iclass 5, count 2 2006.239.07:56:19.40#ibcon#flushed, iclass 5, count 2 2006.239.07:56:19.40#ibcon#about to write, iclass 5, count 2 2006.239.07:56:19.40#ibcon#wrote, iclass 5, count 2 2006.239.07:56:19.40#ibcon#about to read 3, iclass 5, count 2 2006.239.07:56:19.43#ibcon#read 3, iclass 5, count 2 2006.239.07:56:19.43#ibcon#about to read 4, iclass 5, count 2 2006.239.07:56:19.43#ibcon#read 4, iclass 5, count 2 2006.239.07:56:19.43#ibcon#about to read 5, iclass 5, count 2 2006.239.07:56:19.43#ibcon#read 5, iclass 5, count 2 2006.239.07:56:19.43#ibcon#about to read 6, iclass 5, count 2 2006.239.07:56:19.43#ibcon#read 6, iclass 5, count 2 2006.239.07:56:19.43#ibcon#end of sib2, iclass 5, count 2 2006.239.07:56:19.43#ibcon#*after write, iclass 5, count 2 2006.239.07:56:19.43#ibcon#*before return 0, iclass 5, count 2 2006.239.07:56:19.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:19.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:19.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.07:56:19.43#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:19.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:19.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:19.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:19.55#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:56:19.55#ibcon#first serial, iclass 5, count 0 2006.239.07:56:19.55#ibcon#enter sib2, iclass 5, count 0 2006.239.07:56:19.55#ibcon#flushed, iclass 5, count 0 2006.239.07:56:19.55#ibcon#about to write, iclass 5, count 0 2006.239.07:56:19.55#ibcon#wrote, iclass 5, count 0 2006.239.07:56:19.55#ibcon#about to read 3, iclass 5, count 0 2006.239.07:56:19.57#ibcon#read 3, iclass 5, count 0 2006.239.07:56:19.57#ibcon#about to read 4, iclass 5, count 0 2006.239.07:56:19.57#ibcon#read 4, iclass 5, count 0 2006.239.07:56:19.57#ibcon#about to read 5, iclass 5, count 0 2006.239.07:56:19.57#ibcon#read 5, iclass 5, count 0 2006.239.07:56:19.57#ibcon#about to read 6, iclass 5, count 0 2006.239.07:56:19.57#ibcon#read 6, iclass 5, count 0 2006.239.07:56:19.57#ibcon#end of sib2, iclass 5, count 0 2006.239.07:56:19.57#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:56:19.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:56:19.57#ibcon#[25=USB\r\n] 2006.239.07:56:19.57#ibcon#*before write, iclass 5, count 0 2006.239.07:56:19.57#ibcon#enter sib2, iclass 5, count 0 2006.239.07:56:19.57#ibcon#flushed, iclass 5, count 0 2006.239.07:56:19.57#ibcon#about to write, iclass 5, count 0 2006.239.07:56:19.57#ibcon#wrote, iclass 5, count 0 2006.239.07:56:19.57#ibcon#about to read 3, iclass 5, count 0 2006.239.07:56:19.60#ibcon#read 3, iclass 5, count 0 2006.239.07:56:19.60#ibcon#about to read 4, iclass 5, count 0 2006.239.07:56:19.60#ibcon#read 4, iclass 5, count 0 2006.239.07:56:19.60#ibcon#about to read 5, iclass 5, count 0 2006.239.07:56:19.60#ibcon#read 5, iclass 5, count 0 2006.239.07:56:19.60#ibcon#about to read 6, iclass 5, count 0 2006.239.07:56:19.60#ibcon#read 6, iclass 5, count 0 2006.239.07:56:19.60#ibcon#end of sib2, iclass 5, count 0 2006.239.07:56:19.60#ibcon#*after write, iclass 5, count 0 2006.239.07:56:19.60#ibcon#*before return 0, iclass 5, count 0 2006.239.07:56:19.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:19.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:19.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:56:19.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:56:19.60$vc4f8/valo=6,772.99 2006.239.07:56:19.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:56:19.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:56:19.60#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:19.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:19.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:19.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:19.60#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:56:19.60#ibcon#first serial, iclass 7, count 0 2006.239.07:56:19.60#ibcon#enter sib2, iclass 7, count 0 2006.239.07:56:19.60#ibcon#flushed, iclass 7, count 0 2006.239.07:56:19.60#ibcon#about to write, iclass 7, count 0 2006.239.07:56:19.60#ibcon#wrote, iclass 7, count 0 2006.239.07:56:19.60#ibcon#about to read 3, iclass 7, count 0 2006.239.07:56:19.62#ibcon#read 3, iclass 7, count 0 2006.239.07:56:19.62#ibcon#about to read 4, iclass 7, count 0 2006.239.07:56:19.62#ibcon#read 4, iclass 7, count 0 2006.239.07:56:19.62#ibcon#about to read 5, iclass 7, count 0 2006.239.07:56:19.62#ibcon#read 5, iclass 7, count 0 2006.239.07:56:19.62#ibcon#about to read 6, iclass 7, count 0 2006.239.07:56:19.62#ibcon#read 6, iclass 7, count 0 2006.239.07:56:19.62#ibcon#end of sib2, iclass 7, count 0 2006.239.07:56:19.62#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:56:19.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:56:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:56:19.62#ibcon#*before write, iclass 7, count 0 2006.239.07:56:19.62#ibcon#enter sib2, iclass 7, count 0 2006.239.07:56:19.62#ibcon#flushed, iclass 7, count 0 2006.239.07:56:19.62#ibcon#about to write, iclass 7, count 0 2006.239.07:56:19.62#ibcon#wrote, iclass 7, count 0 2006.239.07:56:19.62#ibcon#about to read 3, iclass 7, count 0 2006.239.07:56:19.66#ibcon#read 3, iclass 7, count 0 2006.239.07:56:19.66#ibcon#about to read 4, iclass 7, count 0 2006.239.07:56:19.66#ibcon#read 4, iclass 7, count 0 2006.239.07:56:19.66#ibcon#about to read 5, iclass 7, count 0 2006.239.07:56:19.66#ibcon#read 5, iclass 7, count 0 2006.239.07:56:19.66#ibcon#about to read 6, iclass 7, count 0 2006.239.07:56:19.66#ibcon#read 6, iclass 7, count 0 2006.239.07:56:19.66#ibcon#end of sib2, iclass 7, count 0 2006.239.07:56:19.66#ibcon#*after write, iclass 7, count 0 2006.239.07:56:19.66#ibcon#*before return 0, iclass 7, count 0 2006.239.07:56:19.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:19.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:19.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:56:19.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:56:19.66$vc4f8/va=6,7 2006.239.07:56:19.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.07:56:19.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.07:56:19.66#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:19.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:19.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:19.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:19.72#ibcon#enter wrdev, iclass 11, count 2 2006.239.07:56:19.72#ibcon#first serial, iclass 11, count 2 2006.239.07:56:19.72#ibcon#enter sib2, iclass 11, count 2 2006.239.07:56:19.72#ibcon#flushed, iclass 11, count 2 2006.239.07:56:19.72#ibcon#about to write, iclass 11, count 2 2006.239.07:56:19.72#ibcon#wrote, iclass 11, count 2 2006.239.07:56:19.72#ibcon#about to read 3, iclass 11, count 2 2006.239.07:56:19.73#abcon#<5=/04 2.1 4.1 25.21 791011.6\r\n> 2006.239.07:56:19.74#ibcon#read 3, iclass 11, count 2 2006.239.07:56:19.74#ibcon#about to read 4, iclass 11, count 2 2006.239.07:56:19.74#ibcon#read 4, iclass 11, count 2 2006.239.07:56:19.74#ibcon#about to read 5, iclass 11, count 2 2006.239.07:56:19.74#ibcon#read 5, iclass 11, count 2 2006.239.07:56:19.74#ibcon#about to read 6, iclass 11, count 2 2006.239.07:56:19.74#ibcon#read 6, iclass 11, count 2 2006.239.07:56:19.74#ibcon#end of sib2, iclass 11, count 2 2006.239.07:56:19.74#ibcon#*mode == 0, iclass 11, count 2 2006.239.07:56:19.74#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.07:56:19.74#ibcon#[25=AT06-07\r\n] 2006.239.07:56:19.74#ibcon#*before write, iclass 11, count 2 2006.239.07:56:19.74#ibcon#enter sib2, iclass 11, count 2 2006.239.07:56:19.74#ibcon#flushed, iclass 11, count 2 2006.239.07:56:19.74#ibcon#about to write, iclass 11, count 2 2006.239.07:56:19.74#ibcon#wrote, iclass 11, count 2 2006.239.07:56:19.74#ibcon#about to read 3, iclass 11, count 2 2006.239.07:56:19.75#abcon#{5=INTERFACE CLEAR} 2006.239.07:56:19.77#ibcon#read 3, iclass 11, count 2 2006.239.07:56:19.77#ibcon#about to read 4, iclass 11, count 2 2006.239.07:56:19.77#ibcon#read 4, iclass 11, count 2 2006.239.07:56:19.77#ibcon#about to read 5, iclass 11, count 2 2006.239.07:56:19.77#ibcon#read 5, iclass 11, count 2 2006.239.07:56:19.77#ibcon#about to read 6, iclass 11, count 2 2006.239.07:56:19.77#ibcon#read 6, iclass 11, count 2 2006.239.07:56:19.77#ibcon#end of sib2, iclass 11, count 2 2006.239.07:56:19.77#ibcon#*after write, iclass 11, count 2 2006.239.07:56:19.77#ibcon#*before return 0, iclass 11, count 2 2006.239.07:56:19.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:19.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:19.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.07:56:19.77#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:19.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:19.81#abcon#[5=S1D000X0/0*\r\n] 2006.239.07:56:19.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:19.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:19.89#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:56:19.89#ibcon#first serial, iclass 11, count 0 2006.239.07:56:19.89#ibcon#enter sib2, iclass 11, count 0 2006.239.07:56:19.89#ibcon#flushed, iclass 11, count 0 2006.239.07:56:19.89#ibcon#about to write, iclass 11, count 0 2006.239.07:56:19.89#ibcon#wrote, iclass 11, count 0 2006.239.07:56:19.89#ibcon#about to read 3, iclass 11, count 0 2006.239.07:56:19.91#ibcon#read 3, iclass 11, count 0 2006.239.07:56:19.91#ibcon#about to read 4, iclass 11, count 0 2006.239.07:56:19.91#ibcon#read 4, iclass 11, count 0 2006.239.07:56:19.91#ibcon#about to read 5, iclass 11, count 0 2006.239.07:56:19.91#ibcon#read 5, iclass 11, count 0 2006.239.07:56:19.91#ibcon#about to read 6, iclass 11, count 0 2006.239.07:56:19.91#ibcon#read 6, iclass 11, count 0 2006.239.07:56:19.91#ibcon#end of sib2, iclass 11, count 0 2006.239.07:56:19.91#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:56:19.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:56:19.91#ibcon#[25=USB\r\n] 2006.239.07:56:19.91#ibcon#*before write, iclass 11, count 0 2006.239.07:56:19.91#ibcon#enter sib2, iclass 11, count 0 2006.239.07:56:19.91#ibcon#flushed, iclass 11, count 0 2006.239.07:56:19.91#ibcon#about to write, iclass 11, count 0 2006.239.07:56:19.91#ibcon#wrote, iclass 11, count 0 2006.239.07:56:19.91#ibcon#about to read 3, iclass 11, count 0 2006.239.07:56:19.94#ibcon#read 3, iclass 11, count 0 2006.239.07:56:19.94#ibcon#about to read 4, iclass 11, count 0 2006.239.07:56:19.94#ibcon#read 4, iclass 11, count 0 2006.239.07:56:19.94#ibcon#about to read 5, iclass 11, count 0 2006.239.07:56:19.94#ibcon#read 5, iclass 11, count 0 2006.239.07:56:19.94#ibcon#about to read 6, iclass 11, count 0 2006.239.07:56:19.94#ibcon#read 6, iclass 11, count 0 2006.239.07:56:19.94#ibcon#end of sib2, iclass 11, count 0 2006.239.07:56:19.94#ibcon#*after write, iclass 11, count 0 2006.239.07:56:19.94#ibcon#*before return 0, iclass 11, count 0 2006.239.07:56:19.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:19.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:19.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:56:19.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:56:19.94$vc4f8/valo=7,832.99 2006.239.07:56:19.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.07:56:19.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.07:56:19.94#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:19.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:56:19.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:56:19.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:56:19.94#ibcon#enter wrdev, iclass 17, count 0 2006.239.07:56:19.94#ibcon#first serial, iclass 17, count 0 2006.239.07:56:19.94#ibcon#enter sib2, iclass 17, count 0 2006.239.07:56:19.94#ibcon#flushed, iclass 17, count 0 2006.239.07:56:19.94#ibcon#about to write, iclass 17, count 0 2006.239.07:56:19.94#ibcon#wrote, iclass 17, count 0 2006.239.07:56:19.94#ibcon#about to read 3, iclass 17, count 0 2006.239.07:56:19.96#ibcon#read 3, iclass 17, count 0 2006.239.07:56:19.96#ibcon#about to read 4, iclass 17, count 0 2006.239.07:56:19.96#ibcon#read 4, iclass 17, count 0 2006.239.07:56:19.96#ibcon#about to read 5, iclass 17, count 0 2006.239.07:56:19.96#ibcon#read 5, iclass 17, count 0 2006.239.07:56:19.96#ibcon#about to read 6, iclass 17, count 0 2006.239.07:56:19.96#ibcon#read 6, iclass 17, count 0 2006.239.07:56:19.96#ibcon#end of sib2, iclass 17, count 0 2006.239.07:56:19.96#ibcon#*mode == 0, iclass 17, count 0 2006.239.07:56:19.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.07:56:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:56:19.96#ibcon#*before write, iclass 17, count 0 2006.239.07:56:19.96#ibcon#enter sib2, iclass 17, count 0 2006.239.07:56:19.96#ibcon#flushed, iclass 17, count 0 2006.239.07:56:19.96#ibcon#about to write, iclass 17, count 0 2006.239.07:56:19.96#ibcon#wrote, iclass 17, count 0 2006.239.07:56:19.96#ibcon#about to read 3, iclass 17, count 0 2006.239.07:56:20.00#ibcon#read 3, iclass 17, count 0 2006.239.07:56:20.00#ibcon#about to read 4, iclass 17, count 0 2006.239.07:56:20.00#ibcon#read 4, iclass 17, count 0 2006.239.07:56:20.00#ibcon#about to read 5, iclass 17, count 0 2006.239.07:56:20.00#ibcon#read 5, iclass 17, count 0 2006.239.07:56:20.00#ibcon#about to read 6, iclass 17, count 0 2006.239.07:56:20.00#ibcon#read 6, iclass 17, count 0 2006.239.07:56:20.00#ibcon#end of sib2, iclass 17, count 0 2006.239.07:56:20.00#ibcon#*after write, iclass 17, count 0 2006.239.07:56:20.00#ibcon#*before return 0, iclass 17, count 0 2006.239.07:56:20.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:56:20.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.07:56:20.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.07:56:20.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.07:56:20.00$vc4f8/va=7,7 2006.239.07:56:20.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.07:56:20.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.07:56:20.00#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:20.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:56:20.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:56:20.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:56:20.06#ibcon#enter wrdev, iclass 19, count 2 2006.239.07:56:20.06#ibcon#first serial, iclass 19, count 2 2006.239.07:56:20.06#ibcon#enter sib2, iclass 19, count 2 2006.239.07:56:20.06#ibcon#flushed, iclass 19, count 2 2006.239.07:56:20.06#ibcon#about to write, iclass 19, count 2 2006.239.07:56:20.06#ibcon#wrote, iclass 19, count 2 2006.239.07:56:20.06#ibcon#about to read 3, iclass 19, count 2 2006.239.07:56:20.08#ibcon#read 3, iclass 19, count 2 2006.239.07:56:20.08#ibcon#about to read 4, iclass 19, count 2 2006.239.07:56:20.08#ibcon#read 4, iclass 19, count 2 2006.239.07:56:20.08#ibcon#about to read 5, iclass 19, count 2 2006.239.07:56:20.08#ibcon#read 5, iclass 19, count 2 2006.239.07:56:20.08#ibcon#about to read 6, iclass 19, count 2 2006.239.07:56:20.08#ibcon#read 6, iclass 19, count 2 2006.239.07:56:20.08#ibcon#end of sib2, iclass 19, count 2 2006.239.07:56:20.08#ibcon#*mode == 0, iclass 19, count 2 2006.239.07:56:20.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.07:56:20.08#ibcon#[25=AT07-07\r\n] 2006.239.07:56:20.08#ibcon#*before write, iclass 19, count 2 2006.239.07:56:20.08#ibcon#enter sib2, iclass 19, count 2 2006.239.07:56:20.08#ibcon#flushed, iclass 19, count 2 2006.239.07:56:20.08#ibcon#about to write, iclass 19, count 2 2006.239.07:56:20.08#ibcon#wrote, iclass 19, count 2 2006.239.07:56:20.08#ibcon#about to read 3, iclass 19, count 2 2006.239.07:56:20.11#ibcon#read 3, iclass 19, count 2 2006.239.07:56:20.11#ibcon#about to read 4, iclass 19, count 2 2006.239.07:56:20.11#ibcon#read 4, iclass 19, count 2 2006.239.07:56:20.11#ibcon#about to read 5, iclass 19, count 2 2006.239.07:56:20.11#ibcon#read 5, iclass 19, count 2 2006.239.07:56:20.11#ibcon#about to read 6, iclass 19, count 2 2006.239.07:56:20.11#ibcon#read 6, iclass 19, count 2 2006.239.07:56:20.11#ibcon#end of sib2, iclass 19, count 2 2006.239.07:56:20.11#ibcon#*after write, iclass 19, count 2 2006.239.07:56:20.11#ibcon#*before return 0, iclass 19, count 2 2006.239.07:56:20.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:56:20.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.07:56:20.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.07:56:20.11#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:20.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:56:20.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:56:20.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:56:20.23#ibcon#enter wrdev, iclass 19, count 0 2006.239.07:56:20.23#ibcon#first serial, iclass 19, count 0 2006.239.07:56:20.23#ibcon#enter sib2, iclass 19, count 0 2006.239.07:56:20.23#ibcon#flushed, iclass 19, count 0 2006.239.07:56:20.23#ibcon#about to write, iclass 19, count 0 2006.239.07:56:20.23#ibcon#wrote, iclass 19, count 0 2006.239.07:56:20.23#ibcon#about to read 3, iclass 19, count 0 2006.239.07:56:20.25#ibcon#read 3, iclass 19, count 0 2006.239.07:56:20.25#ibcon#about to read 4, iclass 19, count 0 2006.239.07:56:20.25#ibcon#read 4, iclass 19, count 0 2006.239.07:56:20.25#ibcon#about to read 5, iclass 19, count 0 2006.239.07:56:20.25#ibcon#read 5, iclass 19, count 0 2006.239.07:56:20.25#ibcon#about to read 6, iclass 19, count 0 2006.239.07:56:20.25#ibcon#read 6, iclass 19, count 0 2006.239.07:56:20.25#ibcon#end of sib2, iclass 19, count 0 2006.239.07:56:20.25#ibcon#*mode == 0, iclass 19, count 0 2006.239.07:56:20.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.07:56:20.25#ibcon#[25=USB\r\n] 2006.239.07:56:20.25#ibcon#*before write, iclass 19, count 0 2006.239.07:56:20.25#ibcon#enter sib2, iclass 19, count 0 2006.239.07:56:20.25#ibcon#flushed, iclass 19, count 0 2006.239.07:56:20.25#ibcon#about to write, iclass 19, count 0 2006.239.07:56:20.25#ibcon#wrote, iclass 19, count 0 2006.239.07:56:20.25#ibcon#about to read 3, iclass 19, count 0 2006.239.07:56:20.28#ibcon#read 3, iclass 19, count 0 2006.239.07:56:20.28#ibcon#about to read 4, iclass 19, count 0 2006.239.07:56:20.28#ibcon#read 4, iclass 19, count 0 2006.239.07:56:20.28#ibcon#about to read 5, iclass 19, count 0 2006.239.07:56:20.28#ibcon#read 5, iclass 19, count 0 2006.239.07:56:20.28#ibcon#about to read 6, iclass 19, count 0 2006.239.07:56:20.28#ibcon#read 6, iclass 19, count 0 2006.239.07:56:20.28#ibcon#end of sib2, iclass 19, count 0 2006.239.07:56:20.28#ibcon#*after write, iclass 19, count 0 2006.239.07:56:20.28#ibcon#*before return 0, iclass 19, count 0 2006.239.07:56:20.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:56:20.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.07:56:20.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.07:56:20.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.07:56:20.28$vc4f8/valo=8,852.99 2006.239.07:56:20.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.07:56:20.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.07:56:20.28#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:20.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:56:20.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:56:20.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:56:20.28#ibcon#enter wrdev, iclass 21, count 0 2006.239.07:56:20.28#ibcon#first serial, iclass 21, count 0 2006.239.07:56:20.28#ibcon#enter sib2, iclass 21, count 0 2006.239.07:56:20.28#ibcon#flushed, iclass 21, count 0 2006.239.07:56:20.28#ibcon#about to write, iclass 21, count 0 2006.239.07:56:20.28#ibcon#wrote, iclass 21, count 0 2006.239.07:56:20.28#ibcon#about to read 3, iclass 21, count 0 2006.239.07:56:20.30#ibcon#read 3, iclass 21, count 0 2006.239.07:56:20.30#ibcon#about to read 4, iclass 21, count 0 2006.239.07:56:20.30#ibcon#read 4, iclass 21, count 0 2006.239.07:56:20.30#ibcon#about to read 5, iclass 21, count 0 2006.239.07:56:20.30#ibcon#read 5, iclass 21, count 0 2006.239.07:56:20.30#ibcon#about to read 6, iclass 21, count 0 2006.239.07:56:20.30#ibcon#read 6, iclass 21, count 0 2006.239.07:56:20.30#ibcon#end of sib2, iclass 21, count 0 2006.239.07:56:20.30#ibcon#*mode == 0, iclass 21, count 0 2006.239.07:56:20.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.07:56:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:56:20.30#ibcon#*before write, iclass 21, count 0 2006.239.07:56:20.30#ibcon#enter sib2, iclass 21, count 0 2006.239.07:56:20.30#ibcon#flushed, iclass 21, count 0 2006.239.07:56:20.30#ibcon#about to write, iclass 21, count 0 2006.239.07:56:20.30#ibcon#wrote, iclass 21, count 0 2006.239.07:56:20.30#ibcon#about to read 3, iclass 21, count 0 2006.239.07:56:20.34#ibcon#read 3, iclass 21, count 0 2006.239.07:56:20.34#ibcon#about to read 4, iclass 21, count 0 2006.239.07:56:20.34#ibcon#read 4, iclass 21, count 0 2006.239.07:56:20.34#ibcon#about to read 5, iclass 21, count 0 2006.239.07:56:20.34#ibcon#read 5, iclass 21, count 0 2006.239.07:56:20.34#ibcon#about to read 6, iclass 21, count 0 2006.239.07:56:20.34#ibcon#read 6, iclass 21, count 0 2006.239.07:56:20.34#ibcon#end of sib2, iclass 21, count 0 2006.239.07:56:20.34#ibcon#*after write, iclass 21, count 0 2006.239.07:56:20.34#ibcon#*before return 0, iclass 21, count 0 2006.239.07:56:20.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:56:20.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.07:56:20.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.07:56:20.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.07:56:20.34$vc4f8/va=8,7 2006.239.07:56:20.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.07:56:20.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.07:56:20.34#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:20.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:56:20.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:56:20.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:56:20.40#ibcon#enter wrdev, iclass 23, count 2 2006.239.07:56:20.40#ibcon#first serial, iclass 23, count 2 2006.239.07:56:20.40#ibcon#enter sib2, iclass 23, count 2 2006.239.07:56:20.40#ibcon#flushed, iclass 23, count 2 2006.239.07:56:20.40#ibcon#about to write, iclass 23, count 2 2006.239.07:56:20.40#ibcon#wrote, iclass 23, count 2 2006.239.07:56:20.40#ibcon#about to read 3, iclass 23, count 2 2006.239.07:56:20.42#ibcon#read 3, iclass 23, count 2 2006.239.07:56:20.42#ibcon#about to read 4, iclass 23, count 2 2006.239.07:56:20.42#ibcon#read 4, iclass 23, count 2 2006.239.07:56:20.42#ibcon#about to read 5, iclass 23, count 2 2006.239.07:56:20.42#ibcon#read 5, iclass 23, count 2 2006.239.07:56:20.42#ibcon#about to read 6, iclass 23, count 2 2006.239.07:56:20.42#ibcon#read 6, iclass 23, count 2 2006.239.07:56:20.42#ibcon#end of sib2, iclass 23, count 2 2006.239.07:56:20.42#ibcon#*mode == 0, iclass 23, count 2 2006.239.07:56:20.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.07:56:20.42#ibcon#[25=AT08-07\r\n] 2006.239.07:56:20.42#ibcon#*before write, iclass 23, count 2 2006.239.07:56:20.42#ibcon#enter sib2, iclass 23, count 2 2006.239.07:56:20.42#ibcon#flushed, iclass 23, count 2 2006.239.07:56:20.42#ibcon#about to write, iclass 23, count 2 2006.239.07:56:20.42#ibcon#wrote, iclass 23, count 2 2006.239.07:56:20.42#ibcon#about to read 3, iclass 23, count 2 2006.239.07:56:20.45#ibcon#read 3, iclass 23, count 2 2006.239.07:56:20.45#ibcon#about to read 4, iclass 23, count 2 2006.239.07:56:20.45#ibcon#read 4, iclass 23, count 2 2006.239.07:56:20.45#ibcon#about to read 5, iclass 23, count 2 2006.239.07:56:20.45#ibcon#read 5, iclass 23, count 2 2006.239.07:56:20.45#ibcon#about to read 6, iclass 23, count 2 2006.239.07:56:20.45#ibcon#read 6, iclass 23, count 2 2006.239.07:56:20.45#ibcon#end of sib2, iclass 23, count 2 2006.239.07:56:20.45#ibcon#*after write, iclass 23, count 2 2006.239.07:56:20.45#ibcon#*before return 0, iclass 23, count 2 2006.239.07:56:20.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:56:20.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.07:56:20.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.07:56:20.45#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:20.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:56:20.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:56:20.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:56:20.57#ibcon#enter wrdev, iclass 23, count 0 2006.239.07:56:20.57#ibcon#first serial, iclass 23, count 0 2006.239.07:56:20.57#ibcon#enter sib2, iclass 23, count 0 2006.239.07:56:20.57#ibcon#flushed, iclass 23, count 0 2006.239.07:56:20.57#ibcon#about to write, iclass 23, count 0 2006.239.07:56:20.57#ibcon#wrote, iclass 23, count 0 2006.239.07:56:20.57#ibcon#about to read 3, iclass 23, count 0 2006.239.07:56:20.59#ibcon#read 3, iclass 23, count 0 2006.239.07:56:20.59#ibcon#about to read 4, iclass 23, count 0 2006.239.07:56:20.59#ibcon#read 4, iclass 23, count 0 2006.239.07:56:20.59#ibcon#about to read 5, iclass 23, count 0 2006.239.07:56:20.59#ibcon#read 5, iclass 23, count 0 2006.239.07:56:20.59#ibcon#about to read 6, iclass 23, count 0 2006.239.07:56:20.59#ibcon#read 6, iclass 23, count 0 2006.239.07:56:20.59#ibcon#end of sib2, iclass 23, count 0 2006.239.07:56:20.59#ibcon#*mode == 0, iclass 23, count 0 2006.239.07:56:20.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.07:56:20.59#ibcon#[25=USB\r\n] 2006.239.07:56:20.59#ibcon#*before write, iclass 23, count 0 2006.239.07:56:20.59#ibcon#enter sib2, iclass 23, count 0 2006.239.07:56:20.59#ibcon#flushed, iclass 23, count 0 2006.239.07:56:20.59#ibcon#about to write, iclass 23, count 0 2006.239.07:56:20.59#ibcon#wrote, iclass 23, count 0 2006.239.07:56:20.59#ibcon#about to read 3, iclass 23, count 0 2006.239.07:56:20.62#ibcon#read 3, iclass 23, count 0 2006.239.07:56:20.62#ibcon#about to read 4, iclass 23, count 0 2006.239.07:56:20.62#ibcon#read 4, iclass 23, count 0 2006.239.07:56:20.62#ibcon#about to read 5, iclass 23, count 0 2006.239.07:56:20.62#ibcon#read 5, iclass 23, count 0 2006.239.07:56:20.62#ibcon#about to read 6, iclass 23, count 0 2006.239.07:56:20.62#ibcon#read 6, iclass 23, count 0 2006.239.07:56:20.62#ibcon#end of sib2, iclass 23, count 0 2006.239.07:56:20.62#ibcon#*after write, iclass 23, count 0 2006.239.07:56:20.62#ibcon#*before return 0, iclass 23, count 0 2006.239.07:56:20.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:56:20.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.07:56:20.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.07:56:20.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.07:56:20.62$vc4f8/vblo=1,632.99 2006.239.07:56:20.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.07:56:20.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.07:56:20.62#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:20.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:20.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:20.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:20.62#ibcon#enter wrdev, iclass 25, count 0 2006.239.07:56:20.62#ibcon#first serial, iclass 25, count 0 2006.239.07:56:20.62#ibcon#enter sib2, iclass 25, count 0 2006.239.07:56:20.62#ibcon#flushed, iclass 25, count 0 2006.239.07:56:20.62#ibcon#about to write, iclass 25, count 0 2006.239.07:56:20.62#ibcon#wrote, iclass 25, count 0 2006.239.07:56:20.62#ibcon#about to read 3, iclass 25, count 0 2006.239.07:56:20.64#ibcon#read 3, iclass 25, count 0 2006.239.07:56:20.64#ibcon#about to read 4, iclass 25, count 0 2006.239.07:56:20.64#ibcon#read 4, iclass 25, count 0 2006.239.07:56:20.64#ibcon#about to read 5, iclass 25, count 0 2006.239.07:56:20.64#ibcon#read 5, iclass 25, count 0 2006.239.07:56:20.64#ibcon#about to read 6, iclass 25, count 0 2006.239.07:56:20.64#ibcon#read 6, iclass 25, count 0 2006.239.07:56:20.64#ibcon#end of sib2, iclass 25, count 0 2006.239.07:56:20.64#ibcon#*mode == 0, iclass 25, count 0 2006.239.07:56:20.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.07:56:20.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:56:20.64#ibcon#*before write, iclass 25, count 0 2006.239.07:56:20.64#ibcon#enter sib2, iclass 25, count 0 2006.239.07:56:20.64#ibcon#flushed, iclass 25, count 0 2006.239.07:56:20.64#ibcon#about to write, iclass 25, count 0 2006.239.07:56:20.64#ibcon#wrote, iclass 25, count 0 2006.239.07:56:20.64#ibcon#about to read 3, iclass 25, count 0 2006.239.07:56:20.68#ibcon#read 3, iclass 25, count 0 2006.239.07:56:20.68#ibcon#about to read 4, iclass 25, count 0 2006.239.07:56:20.68#ibcon#read 4, iclass 25, count 0 2006.239.07:56:20.68#ibcon#about to read 5, iclass 25, count 0 2006.239.07:56:20.68#ibcon#read 5, iclass 25, count 0 2006.239.07:56:20.68#ibcon#about to read 6, iclass 25, count 0 2006.239.07:56:20.68#ibcon#read 6, iclass 25, count 0 2006.239.07:56:20.68#ibcon#end of sib2, iclass 25, count 0 2006.239.07:56:20.68#ibcon#*after write, iclass 25, count 0 2006.239.07:56:20.68#ibcon#*before return 0, iclass 25, count 0 2006.239.07:56:20.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:20.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.07:56:20.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.07:56:20.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.07:56:20.68$vc4f8/vb=1,4 2006.239.07:56:20.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.07:56:20.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.07:56:20.68#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:20.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:20.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:20.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:20.68#ibcon#enter wrdev, iclass 27, count 2 2006.239.07:56:20.68#ibcon#first serial, iclass 27, count 2 2006.239.07:56:20.68#ibcon#enter sib2, iclass 27, count 2 2006.239.07:56:20.68#ibcon#flushed, iclass 27, count 2 2006.239.07:56:20.68#ibcon#about to write, iclass 27, count 2 2006.239.07:56:20.68#ibcon#wrote, iclass 27, count 2 2006.239.07:56:20.68#ibcon#about to read 3, iclass 27, count 2 2006.239.07:56:20.70#ibcon#read 3, iclass 27, count 2 2006.239.07:56:20.70#ibcon#about to read 4, iclass 27, count 2 2006.239.07:56:20.70#ibcon#read 4, iclass 27, count 2 2006.239.07:56:20.70#ibcon#about to read 5, iclass 27, count 2 2006.239.07:56:20.70#ibcon#read 5, iclass 27, count 2 2006.239.07:56:20.70#ibcon#about to read 6, iclass 27, count 2 2006.239.07:56:20.70#ibcon#read 6, iclass 27, count 2 2006.239.07:56:20.70#ibcon#end of sib2, iclass 27, count 2 2006.239.07:56:20.70#ibcon#*mode == 0, iclass 27, count 2 2006.239.07:56:20.70#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.07:56:20.70#ibcon#[27=AT01-04\r\n] 2006.239.07:56:20.70#ibcon#*before write, iclass 27, count 2 2006.239.07:56:20.70#ibcon#enter sib2, iclass 27, count 2 2006.239.07:56:20.70#ibcon#flushed, iclass 27, count 2 2006.239.07:56:20.70#ibcon#about to write, iclass 27, count 2 2006.239.07:56:20.70#ibcon#wrote, iclass 27, count 2 2006.239.07:56:20.70#ibcon#about to read 3, iclass 27, count 2 2006.239.07:56:20.73#ibcon#read 3, iclass 27, count 2 2006.239.07:56:20.73#ibcon#about to read 4, iclass 27, count 2 2006.239.07:56:20.73#ibcon#read 4, iclass 27, count 2 2006.239.07:56:20.73#ibcon#about to read 5, iclass 27, count 2 2006.239.07:56:20.73#ibcon#read 5, iclass 27, count 2 2006.239.07:56:20.73#ibcon#about to read 6, iclass 27, count 2 2006.239.07:56:20.73#ibcon#read 6, iclass 27, count 2 2006.239.07:56:20.73#ibcon#end of sib2, iclass 27, count 2 2006.239.07:56:20.73#ibcon#*after write, iclass 27, count 2 2006.239.07:56:20.73#ibcon#*before return 0, iclass 27, count 2 2006.239.07:56:20.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:20.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.07:56:20.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.07:56:20.73#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:20.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:20.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:20.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:20.85#ibcon#enter wrdev, iclass 27, count 0 2006.239.07:56:20.85#ibcon#first serial, iclass 27, count 0 2006.239.07:56:20.85#ibcon#enter sib2, iclass 27, count 0 2006.239.07:56:20.85#ibcon#flushed, iclass 27, count 0 2006.239.07:56:20.85#ibcon#about to write, iclass 27, count 0 2006.239.07:56:20.85#ibcon#wrote, iclass 27, count 0 2006.239.07:56:20.85#ibcon#about to read 3, iclass 27, count 0 2006.239.07:56:20.87#ibcon#read 3, iclass 27, count 0 2006.239.07:56:20.87#ibcon#about to read 4, iclass 27, count 0 2006.239.07:56:20.87#ibcon#read 4, iclass 27, count 0 2006.239.07:56:20.87#ibcon#about to read 5, iclass 27, count 0 2006.239.07:56:20.87#ibcon#read 5, iclass 27, count 0 2006.239.07:56:20.87#ibcon#about to read 6, iclass 27, count 0 2006.239.07:56:20.87#ibcon#read 6, iclass 27, count 0 2006.239.07:56:20.87#ibcon#end of sib2, iclass 27, count 0 2006.239.07:56:20.87#ibcon#*mode == 0, iclass 27, count 0 2006.239.07:56:20.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.07:56:20.87#ibcon#[27=USB\r\n] 2006.239.07:56:20.87#ibcon#*before write, iclass 27, count 0 2006.239.07:56:20.87#ibcon#enter sib2, iclass 27, count 0 2006.239.07:56:20.87#ibcon#flushed, iclass 27, count 0 2006.239.07:56:20.87#ibcon#about to write, iclass 27, count 0 2006.239.07:56:20.87#ibcon#wrote, iclass 27, count 0 2006.239.07:56:20.87#ibcon#about to read 3, iclass 27, count 0 2006.239.07:56:20.90#ibcon#read 3, iclass 27, count 0 2006.239.07:56:20.90#ibcon#about to read 4, iclass 27, count 0 2006.239.07:56:20.90#ibcon#read 4, iclass 27, count 0 2006.239.07:56:20.90#ibcon#about to read 5, iclass 27, count 0 2006.239.07:56:20.90#ibcon#read 5, iclass 27, count 0 2006.239.07:56:20.90#ibcon#about to read 6, iclass 27, count 0 2006.239.07:56:20.90#ibcon#read 6, iclass 27, count 0 2006.239.07:56:20.90#ibcon#end of sib2, iclass 27, count 0 2006.239.07:56:20.90#ibcon#*after write, iclass 27, count 0 2006.239.07:56:20.90#ibcon#*before return 0, iclass 27, count 0 2006.239.07:56:20.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:20.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.07:56:20.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.07:56:20.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.07:56:20.90$vc4f8/vblo=2,640.99 2006.239.07:56:20.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.07:56:20.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.07:56:20.90#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:20.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:20.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:20.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:20.90#ibcon#enter wrdev, iclass 29, count 0 2006.239.07:56:20.90#ibcon#first serial, iclass 29, count 0 2006.239.07:56:20.90#ibcon#enter sib2, iclass 29, count 0 2006.239.07:56:20.90#ibcon#flushed, iclass 29, count 0 2006.239.07:56:20.90#ibcon#about to write, iclass 29, count 0 2006.239.07:56:20.90#ibcon#wrote, iclass 29, count 0 2006.239.07:56:20.90#ibcon#about to read 3, iclass 29, count 0 2006.239.07:56:20.92#ibcon#read 3, iclass 29, count 0 2006.239.07:56:20.92#ibcon#about to read 4, iclass 29, count 0 2006.239.07:56:20.92#ibcon#read 4, iclass 29, count 0 2006.239.07:56:20.92#ibcon#about to read 5, iclass 29, count 0 2006.239.07:56:20.92#ibcon#read 5, iclass 29, count 0 2006.239.07:56:20.92#ibcon#about to read 6, iclass 29, count 0 2006.239.07:56:20.92#ibcon#read 6, iclass 29, count 0 2006.239.07:56:20.92#ibcon#end of sib2, iclass 29, count 0 2006.239.07:56:20.92#ibcon#*mode == 0, iclass 29, count 0 2006.239.07:56:20.92#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.07:56:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:56:20.92#ibcon#*before write, iclass 29, count 0 2006.239.07:56:20.92#ibcon#enter sib2, iclass 29, count 0 2006.239.07:56:20.92#ibcon#flushed, iclass 29, count 0 2006.239.07:56:20.92#ibcon#about to write, iclass 29, count 0 2006.239.07:56:20.92#ibcon#wrote, iclass 29, count 0 2006.239.07:56:20.92#ibcon#about to read 3, iclass 29, count 0 2006.239.07:56:20.96#ibcon#read 3, iclass 29, count 0 2006.239.07:56:20.96#ibcon#about to read 4, iclass 29, count 0 2006.239.07:56:20.96#ibcon#read 4, iclass 29, count 0 2006.239.07:56:20.96#ibcon#about to read 5, iclass 29, count 0 2006.239.07:56:20.96#ibcon#read 5, iclass 29, count 0 2006.239.07:56:20.96#ibcon#about to read 6, iclass 29, count 0 2006.239.07:56:20.96#ibcon#read 6, iclass 29, count 0 2006.239.07:56:20.96#ibcon#end of sib2, iclass 29, count 0 2006.239.07:56:20.96#ibcon#*after write, iclass 29, count 0 2006.239.07:56:20.96#ibcon#*before return 0, iclass 29, count 0 2006.239.07:56:20.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:20.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.07:56:20.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.07:56:20.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.07:56:20.96$vc4f8/vb=2,4 2006.239.07:56:20.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.07:56:20.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.07:56:20.96#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:20.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:21.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:21.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:21.02#ibcon#enter wrdev, iclass 31, count 2 2006.239.07:56:21.02#ibcon#first serial, iclass 31, count 2 2006.239.07:56:21.02#ibcon#enter sib2, iclass 31, count 2 2006.239.07:56:21.02#ibcon#flushed, iclass 31, count 2 2006.239.07:56:21.02#ibcon#about to write, iclass 31, count 2 2006.239.07:56:21.02#ibcon#wrote, iclass 31, count 2 2006.239.07:56:21.02#ibcon#about to read 3, iclass 31, count 2 2006.239.07:56:21.04#ibcon#read 3, iclass 31, count 2 2006.239.07:56:21.04#ibcon#about to read 4, iclass 31, count 2 2006.239.07:56:21.04#ibcon#read 4, iclass 31, count 2 2006.239.07:56:21.04#ibcon#about to read 5, iclass 31, count 2 2006.239.07:56:21.04#ibcon#read 5, iclass 31, count 2 2006.239.07:56:21.04#ibcon#about to read 6, iclass 31, count 2 2006.239.07:56:21.04#ibcon#read 6, iclass 31, count 2 2006.239.07:56:21.04#ibcon#end of sib2, iclass 31, count 2 2006.239.07:56:21.04#ibcon#*mode == 0, iclass 31, count 2 2006.239.07:56:21.04#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.07:56:21.04#ibcon#[27=AT02-04\r\n] 2006.239.07:56:21.04#ibcon#*before write, iclass 31, count 2 2006.239.07:56:21.04#ibcon#enter sib2, iclass 31, count 2 2006.239.07:56:21.04#ibcon#flushed, iclass 31, count 2 2006.239.07:56:21.04#ibcon#about to write, iclass 31, count 2 2006.239.07:56:21.04#ibcon#wrote, iclass 31, count 2 2006.239.07:56:21.04#ibcon#about to read 3, iclass 31, count 2 2006.239.07:56:21.07#ibcon#read 3, iclass 31, count 2 2006.239.07:56:21.07#ibcon#about to read 4, iclass 31, count 2 2006.239.07:56:21.07#ibcon#read 4, iclass 31, count 2 2006.239.07:56:21.07#ibcon#about to read 5, iclass 31, count 2 2006.239.07:56:21.07#ibcon#read 5, iclass 31, count 2 2006.239.07:56:21.07#ibcon#about to read 6, iclass 31, count 2 2006.239.07:56:21.07#ibcon#read 6, iclass 31, count 2 2006.239.07:56:21.07#ibcon#end of sib2, iclass 31, count 2 2006.239.07:56:21.07#ibcon#*after write, iclass 31, count 2 2006.239.07:56:21.07#ibcon#*before return 0, iclass 31, count 2 2006.239.07:56:21.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:21.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.07:56:21.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.07:56:21.07#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:21.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:21.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:21.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:21.19#ibcon#enter wrdev, iclass 31, count 0 2006.239.07:56:21.19#ibcon#first serial, iclass 31, count 0 2006.239.07:56:21.19#ibcon#enter sib2, iclass 31, count 0 2006.239.07:56:21.19#ibcon#flushed, iclass 31, count 0 2006.239.07:56:21.19#ibcon#about to write, iclass 31, count 0 2006.239.07:56:21.19#ibcon#wrote, iclass 31, count 0 2006.239.07:56:21.19#ibcon#about to read 3, iclass 31, count 0 2006.239.07:56:21.21#ibcon#read 3, iclass 31, count 0 2006.239.07:56:21.21#ibcon#about to read 4, iclass 31, count 0 2006.239.07:56:21.21#ibcon#read 4, iclass 31, count 0 2006.239.07:56:21.21#ibcon#about to read 5, iclass 31, count 0 2006.239.07:56:21.21#ibcon#read 5, iclass 31, count 0 2006.239.07:56:21.21#ibcon#about to read 6, iclass 31, count 0 2006.239.07:56:21.21#ibcon#read 6, iclass 31, count 0 2006.239.07:56:21.21#ibcon#end of sib2, iclass 31, count 0 2006.239.07:56:21.21#ibcon#*mode == 0, iclass 31, count 0 2006.239.07:56:21.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.07:56:21.21#ibcon#[27=USB\r\n] 2006.239.07:56:21.21#ibcon#*before write, iclass 31, count 0 2006.239.07:56:21.21#ibcon#enter sib2, iclass 31, count 0 2006.239.07:56:21.21#ibcon#flushed, iclass 31, count 0 2006.239.07:56:21.21#ibcon#about to write, iclass 31, count 0 2006.239.07:56:21.21#ibcon#wrote, iclass 31, count 0 2006.239.07:56:21.21#ibcon#about to read 3, iclass 31, count 0 2006.239.07:56:21.24#ibcon#read 3, iclass 31, count 0 2006.239.07:56:21.24#ibcon#about to read 4, iclass 31, count 0 2006.239.07:56:21.24#ibcon#read 4, iclass 31, count 0 2006.239.07:56:21.24#ibcon#about to read 5, iclass 31, count 0 2006.239.07:56:21.24#ibcon#read 5, iclass 31, count 0 2006.239.07:56:21.24#ibcon#about to read 6, iclass 31, count 0 2006.239.07:56:21.24#ibcon#read 6, iclass 31, count 0 2006.239.07:56:21.24#ibcon#end of sib2, iclass 31, count 0 2006.239.07:56:21.24#ibcon#*after write, iclass 31, count 0 2006.239.07:56:21.24#ibcon#*before return 0, iclass 31, count 0 2006.239.07:56:21.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:21.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.07:56:21.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.07:56:21.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.07:56:21.24$vc4f8/vblo=3,656.99 2006.239.07:56:21.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.07:56:21.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.07:56:21.24#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:21.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:21.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:21.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:21.24#ibcon#enter wrdev, iclass 33, count 0 2006.239.07:56:21.24#ibcon#first serial, iclass 33, count 0 2006.239.07:56:21.24#ibcon#enter sib2, iclass 33, count 0 2006.239.07:56:21.24#ibcon#flushed, iclass 33, count 0 2006.239.07:56:21.24#ibcon#about to write, iclass 33, count 0 2006.239.07:56:21.24#ibcon#wrote, iclass 33, count 0 2006.239.07:56:21.24#ibcon#about to read 3, iclass 33, count 0 2006.239.07:56:21.26#ibcon#read 3, iclass 33, count 0 2006.239.07:56:21.26#ibcon#about to read 4, iclass 33, count 0 2006.239.07:56:21.26#ibcon#read 4, iclass 33, count 0 2006.239.07:56:21.26#ibcon#about to read 5, iclass 33, count 0 2006.239.07:56:21.26#ibcon#read 5, iclass 33, count 0 2006.239.07:56:21.26#ibcon#about to read 6, iclass 33, count 0 2006.239.07:56:21.26#ibcon#read 6, iclass 33, count 0 2006.239.07:56:21.26#ibcon#end of sib2, iclass 33, count 0 2006.239.07:56:21.26#ibcon#*mode == 0, iclass 33, count 0 2006.239.07:56:21.26#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.07:56:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:56:21.26#ibcon#*before write, iclass 33, count 0 2006.239.07:56:21.26#ibcon#enter sib2, iclass 33, count 0 2006.239.07:56:21.26#ibcon#flushed, iclass 33, count 0 2006.239.07:56:21.26#ibcon#about to write, iclass 33, count 0 2006.239.07:56:21.26#ibcon#wrote, iclass 33, count 0 2006.239.07:56:21.26#ibcon#about to read 3, iclass 33, count 0 2006.239.07:56:21.30#ibcon#read 3, iclass 33, count 0 2006.239.07:56:21.30#ibcon#about to read 4, iclass 33, count 0 2006.239.07:56:21.30#ibcon#read 4, iclass 33, count 0 2006.239.07:56:21.30#ibcon#about to read 5, iclass 33, count 0 2006.239.07:56:21.30#ibcon#read 5, iclass 33, count 0 2006.239.07:56:21.30#ibcon#about to read 6, iclass 33, count 0 2006.239.07:56:21.30#ibcon#read 6, iclass 33, count 0 2006.239.07:56:21.30#ibcon#end of sib2, iclass 33, count 0 2006.239.07:56:21.30#ibcon#*after write, iclass 33, count 0 2006.239.07:56:21.30#ibcon#*before return 0, iclass 33, count 0 2006.239.07:56:21.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:21.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.07:56:21.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.07:56:21.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.07:56:21.30$vc4f8/vb=3,4 2006.239.07:56:21.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.07:56:21.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.07:56:21.30#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:21.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:21.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:21.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:21.36#ibcon#enter wrdev, iclass 35, count 2 2006.239.07:56:21.36#ibcon#first serial, iclass 35, count 2 2006.239.07:56:21.36#ibcon#enter sib2, iclass 35, count 2 2006.239.07:56:21.36#ibcon#flushed, iclass 35, count 2 2006.239.07:56:21.36#ibcon#about to write, iclass 35, count 2 2006.239.07:56:21.36#ibcon#wrote, iclass 35, count 2 2006.239.07:56:21.36#ibcon#about to read 3, iclass 35, count 2 2006.239.07:56:21.38#ibcon#read 3, iclass 35, count 2 2006.239.07:56:21.38#ibcon#about to read 4, iclass 35, count 2 2006.239.07:56:21.38#ibcon#read 4, iclass 35, count 2 2006.239.07:56:21.38#ibcon#about to read 5, iclass 35, count 2 2006.239.07:56:21.38#ibcon#read 5, iclass 35, count 2 2006.239.07:56:21.38#ibcon#about to read 6, iclass 35, count 2 2006.239.07:56:21.38#ibcon#read 6, iclass 35, count 2 2006.239.07:56:21.38#ibcon#end of sib2, iclass 35, count 2 2006.239.07:56:21.38#ibcon#*mode == 0, iclass 35, count 2 2006.239.07:56:21.38#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.07:56:21.38#ibcon#[27=AT03-04\r\n] 2006.239.07:56:21.38#ibcon#*before write, iclass 35, count 2 2006.239.07:56:21.38#ibcon#enter sib2, iclass 35, count 2 2006.239.07:56:21.38#ibcon#flushed, iclass 35, count 2 2006.239.07:56:21.38#ibcon#about to write, iclass 35, count 2 2006.239.07:56:21.38#ibcon#wrote, iclass 35, count 2 2006.239.07:56:21.38#ibcon#about to read 3, iclass 35, count 2 2006.239.07:56:21.41#ibcon#read 3, iclass 35, count 2 2006.239.07:56:21.41#ibcon#about to read 4, iclass 35, count 2 2006.239.07:56:21.41#ibcon#read 4, iclass 35, count 2 2006.239.07:56:21.41#ibcon#about to read 5, iclass 35, count 2 2006.239.07:56:21.41#ibcon#read 5, iclass 35, count 2 2006.239.07:56:21.41#ibcon#about to read 6, iclass 35, count 2 2006.239.07:56:21.41#ibcon#read 6, iclass 35, count 2 2006.239.07:56:21.41#ibcon#end of sib2, iclass 35, count 2 2006.239.07:56:21.41#ibcon#*after write, iclass 35, count 2 2006.239.07:56:21.41#ibcon#*before return 0, iclass 35, count 2 2006.239.07:56:21.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:21.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.07:56:21.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.07:56:21.41#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:21.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:21.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:21.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:21.53#ibcon#enter wrdev, iclass 35, count 0 2006.239.07:56:21.53#ibcon#first serial, iclass 35, count 0 2006.239.07:56:21.53#ibcon#enter sib2, iclass 35, count 0 2006.239.07:56:21.53#ibcon#flushed, iclass 35, count 0 2006.239.07:56:21.53#ibcon#about to write, iclass 35, count 0 2006.239.07:56:21.53#ibcon#wrote, iclass 35, count 0 2006.239.07:56:21.53#ibcon#about to read 3, iclass 35, count 0 2006.239.07:56:21.55#ibcon#read 3, iclass 35, count 0 2006.239.07:56:21.55#ibcon#about to read 4, iclass 35, count 0 2006.239.07:56:21.55#ibcon#read 4, iclass 35, count 0 2006.239.07:56:21.55#ibcon#about to read 5, iclass 35, count 0 2006.239.07:56:21.55#ibcon#read 5, iclass 35, count 0 2006.239.07:56:21.55#ibcon#about to read 6, iclass 35, count 0 2006.239.07:56:21.55#ibcon#read 6, iclass 35, count 0 2006.239.07:56:21.55#ibcon#end of sib2, iclass 35, count 0 2006.239.07:56:21.55#ibcon#*mode == 0, iclass 35, count 0 2006.239.07:56:21.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.07:56:21.55#ibcon#[27=USB\r\n] 2006.239.07:56:21.55#ibcon#*before write, iclass 35, count 0 2006.239.07:56:21.55#ibcon#enter sib2, iclass 35, count 0 2006.239.07:56:21.55#ibcon#flushed, iclass 35, count 0 2006.239.07:56:21.55#ibcon#about to write, iclass 35, count 0 2006.239.07:56:21.55#ibcon#wrote, iclass 35, count 0 2006.239.07:56:21.55#ibcon#about to read 3, iclass 35, count 0 2006.239.07:56:21.58#ibcon#read 3, iclass 35, count 0 2006.239.07:56:21.58#ibcon#about to read 4, iclass 35, count 0 2006.239.07:56:21.58#ibcon#read 4, iclass 35, count 0 2006.239.07:56:21.58#ibcon#about to read 5, iclass 35, count 0 2006.239.07:56:21.58#ibcon#read 5, iclass 35, count 0 2006.239.07:56:21.58#ibcon#about to read 6, iclass 35, count 0 2006.239.07:56:21.58#ibcon#read 6, iclass 35, count 0 2006.239.07:56:21.58#ibcon#end of sib2, iclass 35, count 0 2006.239.07:56:21.58#ibcon#*after write, iclass 35, count 0 2006.239.07:56:21.58#ibcon#*before return 0, iclass 35, count 0 2006.239.07:56:21.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:21.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.07:56:21.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.07:56:21.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.07:56:21.58$vc4f8/vblo=4,712.99 2006.239.07:56:21.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.07:56:21.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.07:56:21.58#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:21.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:21.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:21.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:21.58#ibcon#enter wrdev, iclass 37, count 0 2006.239.07:56:21.58#ibcon#first serial, iclass 37, count 0 2006.239.07:56:21.58#ibcon#enter sib2, iclass 37, count 0 2006.239.07:56:21.58#ibcon#flushed, iclass 37, count 0 2006.239.07:56:21.58#ibcon#about to write, iclass 37, count 0 2006.239.07:56:21.58#ibcon#wrote, iclass 37, count 0 2006.239.07:56:21.58#ibcon#about to read 3, iclass 37, count 0 2006.239.07:56:21.60#ibcon#read 3, iclass 37, count 0 2006.239.07:56:21.60#ibcon#about to read 4, iclass 37, count 0 2006.239.07:56:21.60#ibcon#read 4, iclass 37, count 0 2006.239.07:56:21.60#ibcon#about to read 5, iclass 37, count 0 2006.239.07:56:21.60#ibcon#read 5, iclass 37, count 0 2006.239.07:56:21.60#ibcon#about to read 6, iclass 37, count 0 2006.239.07:56:21.60#ibcon#read 6, iclass 37, count 0 2006.239.07:56:21.60#ibcon#end of sib2, iclass 37, count 0 2006.239.07:56:21.60#ibcon#*mode == 0, iclass 37, count 0 2006.239.07:56:21.60#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.07:56:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:56:21.60#ibcon#*before write, iclass 37, count 0 2006.239.07:56:21.60#ibcon#enter sib2, iclass 37, count 0 2006.239.07:56:21.60#ibcon#flushed, iclass 37, count 0 2006.239.07:56:21.60#ibcon#about to write, iclass 37, count 0 2006.239.07:56:21.60#ibcon#wrote, iclass 37, count 0 2006.239.07:56:21.60#ibcon#about to read 3, iclass 37, count 0 2006.239.07:56:21.64#ibcon#read 3, iclass 37, count 0 2006.239.07:56:21.64#ibcon#about to read 4, iclass 37, count 0 2006.239.07:56:21.64#ibcon#read 4, iclass 37, count 0 2006.239.07:56:21.64#ibcon#about to read 5, iclass 37, count 0 2006.239.07:56:21.64#ibcon#read 5, iclass 37, count 0 2006.239.07:56:21.64#ibcon#about to read 6, iclass 37, count 0 2006.239.07:56:21.64#ibcon#read 6, iclass 37, count 0 2006.239.07:56:21.64#ibcon#end of sib2, iclass 37, count 0 2006.239.07:56:21.64#ibcon#*after write, iclass 37, count 0 2006.239.07:56:21.64#ibcon#*before return 0, iclass 37, count 0 2006.239.07:56:21.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:21.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.07:56:21.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.07:56:21.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.07:56:21.64$vc4f8/vb=4,4 2006.239.07:56:21.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.07:56:21.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.07:56:21.64#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:21.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:21.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:21.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:21.70#ibcon#enter wrdev, iclass 39, count 2 2006.239.07:56:21.70#ibcon#first serial, iclass 39, count 2 2006.239.07:56:21.70#ibcon#enter sib2, iclass 39, count 2 2006.239.07:56:21.70#ibcon#flushed, iclass 39, count 2 2006.239.07:56:21.70#ibcon#about to write, iclass 39, count 2 2006.239.07:56:21.70#ibcon#wrote, iclass 39, count 2 2006.239.07:56:21.70#ibcon#about to read 3, iclass 39, count 2 2006.239.07:56:21.72#ibcon#read 3, iclass 39, count 2 2006.239.07:56:21.72#ibcon#about to read 4, iclass 39, count 2 2006.239.07:56:21.72#ibcon#read 4, iclass 39, count 2 2006.239.07:56:21.72#ibcon#about to read 5, iclass 39, count 2 2006.239.07:56:21.72#ibcon#read 5, iclass 39, count 2 2006.239.07:56:21.72#ibcon#about to read 6, iclass 39, count 2 2006.239.07:56:21.72#ibcon#read 6, iclass 39, count 2 2006.239.07:56:21.72#ibcon#end of sib2, iclass 39, count 2 2006.239.07:56:21.72#ibcon#*mode == 0, iclass 39, count 2 2006.239.07:56:21.72#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.07:56:21.72#ibcon#[27=AT04-04\r\n] 2006.239.07:56:21.72#ibcon#*before write, iclass 39, count 2 2006.239.07:56:21.72#ibcon#enter sib2, iclass 39, count 2 2006.239.07:56:21.72#ibcon#flushed, iclass 39, count 2 2006.239.07:56:21.72#ibcon#about to write, iclass 39, count 2 2006.239.07:56:21.72#ibcon#wrote, iclass 39, count 2 2006.239.07:56:21.72#ibcon#about to read 3, iclass 39, count 2 2006.239.07:56:21.75#ibcon#read 3, iclass 39, count 2 2006.239.07:56:21.75#ibcon#about to read 4, iclass 39, count 2 2006.239.07:56:21.75#ibcon#read 4, iclass 39, count 2 2006.239.07:56:21.75#ibcon#about to read 5, iclass 39, count 2 2006.239.07:56:21.75#ibcon#read 5, iclass 39, count 2 2006.239.07:56:21.75#ibcon#about to read 6, iclass 39, count 2 2006.239.07:56:21.75#ibcon#read 6, iclass 39, count 2 2006.239.07:56:21.75#ibcon#end of sib2, iclass 39, count 2 2006.239.07:56:21.75#ibcon#*after write, iclass 39, count 2 2006.239.07:56:21.75#ibcon#*before return 0, iclass 39, count 2 2006.239.07:56:21.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:21.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.07:56:21.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.07:56:21.75#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:21.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:21.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:21.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:21.87#ibcon#enter wrdev, iclass 39, count 0 2006.239.07:56:21.87#ibcon#first serial, iclass 39, count 0 2006.239.07:56:21.87#ibcon#enter sib2, iclass 39, count 0 2006.239.07:56:21.87#ibcon#flushed, iclass 39, count 0 2006.239.07:56:21.87#ibcon#about to write, iclass 39, count 0 2006.239.07:56:21.87#ibcon#wrote, iclass 39, count 0 2006.239.07:56:21.87#ibcon#about to read 3, iclass 39, count 0 2006.239.07:56:21.89#ibcon#read 3, iclass 39, count 0 2006.239.07:56:21.89#ibcon#about to read 4, iclass 39, count 0 2006.239.07:56:21.89#ibcon#read 4, iclass 39, count 0 2006.239.07:56:21.89#ibcon#about to read 5, iclass 39, count 0 2006.239.07:56:21.89#ibcon#read 5, iclass 39, count 0 2006.239.07:56:21.89#ibcon#about to read 6, iclass 39, count 0 2006.239.07:56:21.89#ibcon#read 6, iclass 39, count 0 2006.239.07:56:21.89#ibcon#end of sib2, iclass 39, count 0 2006.239.07:56:21.89#ibcon#*mode == 0, iclass 39, count 0 2006.239.07:56:21.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.07:56:21.89#ibcon#[27=USB\r\n] 2006.239.07:56:21.89#ibcon#*before write, iclass 39, count 0 2006.239.07:56:21.89#ibcon#enter sib2, iclass 39, count 0 2006.239.07:56:21.89#ibcon#flushed, iclass 39, count 0 2006.239.07:56:21.89#ibcon#about to write, iclass 39, count 0 2006.239.07:56:21.89#ibcon#wrote, iclass 39, count 0 2006.239.07:56:21.89#ibcon#about to read 3, iclass 39, count 0 2006.239.07:56:21.93#ibcon#read 3, iclass 39, count 0 2006.239.07:56:21.93#ibcon#about to read 4, iclass 39, count 0 2006.239.07:56:21.93#ibcon#read 4, iclass 39, count 0 2006.239.07:56:21.93#ibcon#about to read 5, iclass 39, count 0 2006.239.07:56:21.93#ibcon#read 5, iclass 39, count 0 2006.239.07:56:21.93#ibcon#about to read 6, iclass 39, count 0 2006.239.07:56:21.93#ibcon#read 6, iclass 39, count 0 2006.239.07:56:21.93#ibcon#end of sib2, iclass 39, count 0 2006.239.07:56:21.93#ibcon#*after write, iclass 39, count 0 2006.239.07:56:21.93#ibcon#*before return 0, iclass 39, count 0 2006.239.07:56:21.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:21.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.07:56:21.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.07:56:21.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.07:56:21.93$vc4f8/vblo=5,744.99 2006.239.07:56:21.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.07:56:21.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.07:56:21.93#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:21.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:21.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:21.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:21.93#ibcon#enter wrdev, iclass 3, count 0 2006.239.07:56:21.93#ibcon#first serial, iclass 3, count 0 2006.239.07:56:21.93#ibcon#enter sib2, iclass 3, count 0 2006.239.07:56:21.93#ibcon#flushed, iclass 3, count 0 2006.239.07:56:21.93#ibcon#about to write, iclass 3, count 0 2006.239.07:56:21.93#ibcon#wrote, iclass 3, count 0 2006.239.07:56:21.93#ibcon#about to read 3, iclass 3, count 0 2006.239.07:56:21.95#ibcon#read 3, iclass 3, count 0 2006.239.07:56:21.95#ibcon#about to read 4, iclass 3, count 0 2006.239.07:56:21.95#ibcon#read 4, iclass 3, count 0 2006.239.07:56:21.95#ibcon#about to read 5, iclass 3, count 0 2006.239.07:56:21.95#ibcon#read 5, iclass 3, count 0 2006.239.07:56:21.95#ibcon#about to read 6, iclass 3, count 0 2006.239.07:56:21.95#ibcon#read 6, iclass 3, count 0 2006.239.07:56:21.95#ibcon#end of sib2, iclass 3, count 0 2006.239.07:56:21.95#ibcon#*mode == 0, iclass 3, count 0 2006.239.07:56:21.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.07:56:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:56:21.95#ibcon#*before write, iclass 3, count 0 2006.239.07:56:21.95#ibcon#enter sib2, iclass 3, count 0 2006.239.07:56:21.95#ibcon#flushed, iclass 3, count 0 2006.239.07:56:21.95#ibcon#about to write, iclass 3, count 0 2006.239.07:56:21.95#ibcon#wrote, iclass 3, count 0 2006.239.07:56:21.95#ibcon#about to read 3, iclass 3, count 0 2006.239.07:56:21.99#ibcon#read 3, iclass 3, count 0 2006.239.07:56:21.99#ibcon#about to read 4, iclass 3, count 0 2006.239.07:56:21.99#ibcon#read 4, iclass 3, count 0 2006.239.07:56:21.99#ibcon#about to read 5, iclass 3, count 0 2006.239.07:56:21.99#ibcon#read 5, iclass 3, count 0 2006.239.07:56:21.99#ibcon#about to read 6, iclass 3, count 0 2006.239.07:56:21.99#ibcon#read 6, iclass 3, count 0 2006.239.07:56:21.99#ibcon#end of sib2, iclass 3, count 0 2006.239.07:56:21.99#ibcon#*after write, iclass 3, count 0 2006.239.07:56:21.99#ibcon#*before return 0, iclass 3, count 0 2006.239.07:56:21.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:21.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.07:56:21.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.07:56:21.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.07:56:21.99$vc4f8/vb=5,4 2006.239.07:56:21.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.07:56:21.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.07:56:21.99#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:21.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:22.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:22.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:22.05#ibcon#enter wrdev, iclass 5, count 2 2006.239.07:56:22.05#ibcon#first serial, iclass 5, count 2 2006.239.07:56:22.05#ibcon#enter sib2, iclass 5, count 2 2006.239.07:56:22.05#ibcon#flushed, iclass 5, count 2 2006.239.07:56:22.05#ibcon#about to write, iclass 5, count 2 2006.239.07:56:22.05#ibcon#wrote, iclass 5, count 2 2006.239.07:56:22.05#ibcon#about to read 3, iclass 5, count 2 2006.239.07:56:22.07#ibcon#read 3, iclass 5, count 2 2006.239.07:56:22.07#ibcon#about to read 4, iclass 5, count 2 2006.239.07:56:22.07#ibcon#read 4, iclass 5, count 2 2006.239.07:56:22.07#ibcon#about to read 5, iclass 5, count 2 2006.239.07:56:22.07#ibcon#read 5, iclass 5, count 2 2006.239.07:56:22.07#ibcon#about to read 6, iclass 5, count 2 2006.239.07:56:22.07#ibcon#read 6, iclass 5, count 2 2006.239.07:56:22.07#ibcon#end of sib2, iclass 5, count 2 2006.239.07:56:22.07#ibcon#*mode == 0, iclass 5, count 2 2006.239.07:56:22.07#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.07:56:22.07#ibcon#[27=AT05-04\r\n] 2006.239.07:56:22.07#ibcon#*before write, iclass 5, count 2 2006.239.07:56:22.07#ibcon#enter sib2, iclass 5, count 2 2006.239.07:56:22.07#ibcon#flushed, iclass 5, count 2 2006.239.07:56:22.07#ibcon#about to write, iclass 5, count 2 2006.239.07:56:22.07#ibcon#wrote, iclass 5, count 2 2006.239.07:56:22.07#ibcon#about to read 3, iclass 5, count 2 2006.239.07:56:22.10#ibcon#read 3, iclass 5, count 2 2006.239.07:56:22.10#ibcon#about to read 4, iclass 5, count 2 2006.239.07:56:22.10#ibcon#read 4, iclass 5, count 2 2006.239.07:56:22.10#ibcon#about to read 5, iclass 5, count 2 2006.239.07:56:22.10#ibcon#read 5, iclass 5, count 2 2006.239.07:56:22.10#ibcon#about to read 6, iclass 5, count 2 2006.239.07:56:22.10#ibcon#read 6, iclass 5, count 2 2006.239.07:56:22.10#ibcon#end of sib2, iclass 5, count 2 2006.239.07:56:22.10#ibcon#*after write, iclass 5, count 2 2006.239.07:56:22.10#ibcon#*before return 0, iclass 5, count 2 2006.239.07:56:22.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:22.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.07:56:22.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.07:56:22.10#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:22.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:22.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:22.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:22.22#ibcon#enter wrdev, iclass 5, count 0 2006.239.07:56:22.22#ibcon#first serial, iclass 5, count 0 2006.239.07:56:22.22#ibcon#enter sib2, iclass 5, count 0 2006.239.07:56:22.22#ibcon#flushed, iclass 5, count 0 2006.239.07:56:22.22#ibcon#about to write, iclass 5, count 0 2006.239.07:56:22.22#ibcon#wrote, iclass 5, count 0 2006.239.07:56:22.22#ibcon#about to read 3, iclass 5, count 0 2006.239.07:56:22.24#ibcon#read 3, iclass 5, count 0 2006.239.07:56:22.24#ibcon#about to read 4, iclass 5, count 0 2006.239.07:56:22.24#ibcon#read 4, iclass 5, count 0 2006.239.07:56:22.24#ibcon#about to read 5, iclass 5, count 0 2006.239.07:56:22.24#ibcon#read 5, iclass 5, count 0 2006.239.07:56:22.24#ibcon#about to read 6, iclass 5, count 0 2006.239.07:56:22.24#ibcon#read 6, iclass 5, count 0 2006.239.07:56:22.24#ibcon#end of sib2, iclass 5, count 0 2006.239.07:56:22.24#ibcon#*mode == 0, iclass 5, count 0 2006.239.07:56:22.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.07:56:22.24#ibcon#[27=USB\r\n] 2006.239.07:56:22.24#ibcon#*before write, iclass 5, count 0 2006.239.07:56:22.24#ibcon#enter sib2, iclass 5, count 0 2006.239.07:56:22.24#ibcon#flushed, iclass 5, count 0 2006.239.07:56:22.24#ibcon#about to write, iclass 5, count 0 2006.239.07:56:22.24#ibcon#wrote, iclass 5, count 0 2006.239.07:56:22.24#ibcon#about to read 3, iclass 5, count 0 2006.239.07:56:22.27#ibcon#read 3, iclass 5, count 0 2006.239.07:56:22.27#ibcon#about to read 4, iclass 5, count 0 2006.239.07:56:22.27#ibcon#read 4, iclass 5, count 0 2006.239.07:56:22.27#ibcon#about to read 5, iclass 5, count 0 2006.239.07:56:22.27#ibcon#read 5, iclass 5, count 0 2006.239.07:56:22.27#ibcon#about to read 6, iclass 5, count 0 2006.239.07:56:22.27#ibcon#read 6, iclass 5, count 0 2006.239.07:56:22.27#ibcon#end of sib2, iclass 5, count 0 2006.239.07:56:22.27#ibcon#*after write, iclass 5, count 0 2006.239.07:56:22.27#ibcon#*before return 0, iclass 5, count 0 2006.239.07:56:22.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:22.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.07:56:22.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.07:56:22.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.07:56:22.27$vc4f8/vblo=6,752.99 2006.239.07:56:22.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.07:56:22.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.07:56:22.27#ibcon#ireg 17 cls_cnt 0 2006.239.07:56:22.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:22.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:22.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:22.27#ibcon#enter wrdev, iclass 7, count 0 2006.239.07:56:22.27#ibcon#first serial, iclass 7, count 0 2006.239.07:56:22.27#ibcon#enter sib2, iclass 7, count 0 2006.239.07:56:22.27#ibcon#flushed, iclass 7, count 0 2006.239.07:56:22.27#ibcon#about to write, iclass 7, count 0 2006.239.07:56:22.27#ibcon#wrote, iclass 7, count 0 2006.239.07:56:22.27#ibcon#about to read 3, iclass 7, count 0 2006.239.07:56:22.29#ibcon#read 3, iclass 7, count 0 2006.239.07:56:22.29#ibcon#about to read 4, iclass 7, count 0 2006.239.07:56:22.29#ibcon#read 4, iclass 7, count 0 2006.239.07:56:22.29#ibcon#about to read 5, iclass 7, count 0 2006.239.07:56:22.29#ibcon#read 5, iclass 7, count 0 2006.239.07:56:22.29#ibcon#about to read 6, iclass 7, count 0 2006.239.07:56:22.29#ibcon#read 6, iclass 7, count 0 2006.239.07:56:22.29#ibcon#end of sib2, iclass 7, count 0 2006.239.07:56:22.29#ibcon#*mode == 0, iclass 7, count 0 2006.239.07:56:22.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.07:56:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:56:22.29#ibcon#*before write, iclass 7, count 0 2006.239.07:56:22.29#ibcon#enter sib2, iclass 7, count 0 2006.239.07:56:22.29#ibcon#flushed, iclass 7, count 0 2006.239.07:56:22.29#ibcon#about to write, iclass 7, count 0 2006.239.07:56:22.29#ibcon#wrote, iclass 7, count 0 2006.239.07:56:22.29#ibcon#about to read 3, iclass 7, count 0 2006.239.07:56:22.33#ibcon#read 3, iclass 7, count 0 2006.239.07:56:22.33#ibcon#about to read 4, iclass 7, count 0 2006.239.07:56:22.33#ibcon#read 4, iclass 7, count 0 2006.239.07:56:22.33#ibcon#about to read 5, iclass 7, count 0 2006.239.07:56:22.33#ibcon#read 5, iclass 7, count 0 2006.239.07:56:22.33#ibcon#about to read 6, iclass 7, count 0 2006.239.07:56:22.33#ibcon#read 6, iclass 7, count 0 2006.239.07:56:22.33#ibcon#end of sib2, iclass 7, count 0 2006.239.07:56:22.33#ibcon#*after write, iclass 7, count 0 2006.239.07:56:22.33#ibcon#*before return 0, iclass 7, count 0 2006.239.07:56:22.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:22.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.07:56:22.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.07:56:22.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.07:56:22.33$vc4f8/vb=6,4 2006.239.07:56:22.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.07:56:22.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.07:56:22.33#ibcon#ireg 11 cls_cnt 2 2006.239.07:56:22.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:22.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:22.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:22.39#ibcon#enter wrdev, iclass 11, count 2 2006.239.07:56:22.39#ibcon#first serial, iclass 11, count 2 2006.239.07:56:22.39#ibcon#enter sib2, iclass 11, count 2 2006.239.07:56:22.39#ibcon#flushed, iclass 11, count 2 2006.239.07:56:22.39#ibcon#about to write, iclass 11, count 2 2006.239.07:56:22.39#ibcon#wrote, iclass 11, count 2 2006.239.07:56:22.39#ibcon#about to read 3, iclass 11, count 2 2006.239.07:56:22.41#ibcon#read 3, iclass 11, count 2 2006.239.07:56:22.41#ibcon#about to read 4, iclass 11, count 2 2006.239.07:56:22.41#ibcon#read 4, iclass 11, count 2 2006.239.07:56:22.41#ibcon#about to read 5, iclass 11, count 2 2006.239.07:56:22.41#ibcon#read 5, iclass 11, count 2 2006.239.07:56:22.41#ibcon#about to read 6, iclass 11, count 2 2006.239.07:56:22.41#ibcon#read 6, iclass 11, count 2 2006.239.07:56:22.41#ibcon#end of sib2, iclass 11, count 2 2006.239.07:56:22.41#ibcon#*mode == 0, iclass 11, count 2 2006.239.07:56:22.41#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.07:56:22.41#ibcon#[27=AT06-04\r\n] 2006.239.07:56:22.41#ibcon#*before write, iclass 11, count 2 2006.239.07:56:22.41#ibcon#enter sib2, iclass 11, count 2 2006.239.07:56:22.41#ibcon#flushed, iclass 11, count 2 2006.239.07:56:22.41#ibcon#about to write, iclass 11, count 2 2006.239.07:56:22.41#ibcon#wrote, iclass 11, count 2 2006.239.07:56:22.41#ibcon#about to read 3, iclass 11, count 2 2006.239.07:56:22.44#ibcon#read 3, iclass 11, count 2 2006.239.07:56:22.44#ibcon#about to read 4, iclass 11, count 2 2006.239.07:56:22.44#ibcon#read 4, iclass 11, count 2 2006.239.07:56:22.44#ibcon#about to read 5, iclass 11, count 2 2006.239.07:56:22.44#ibcon#read 5, iclass 11, count 2 2006.239.07:56:22.44#ibcon#about to read 6, iclass 11, count 2 2006.239.07:56:22.44#ibcon#read 6, iclass 11, count 2 2006.239.07:56:22.44#ibcon#end of sib2, iclass 11, count 2 2006.239.07:56:22.44#ibcon#*after write, iclass 11, count 2 2006.239.07:56:22.44#ibcon#*before return 0, iclass 11, count 2 2006.239.07:56:22.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:22.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.07:56:22.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.07:56:22.44#ibcon#ireg 7 cls_cnt 0 2006.239.07:56:22.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:22.57#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:22.57#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:22.57#ibcon#enter wrdev, iclass 11, count 0 2006.239.07:56:22.57#ibcon#first serial, iclass 11, count 0 2006.239.07:56:22.57#ibcon#enter sib2, iclass 11, count 0 2006.239.07:56:22.57#ibcon#flushed, iclass 11, count 0 2006.239.07:56:22.57#ibcon#about to write, iclass 11, count 0 2006.239.07:56:22.57#ibcon#wrote, iclass 11, count 0 2006.239.07:56:22.57#ibcon#about to read 3, iclass 11, count 0 2006.239.07:56:22.59#ibcon#read 3, iclass 11, count 0 2006.239.07:56:22.59#ibcon#about to read 4, iclass 11, count 0 2006.239.07:56:22.59#ibcon#read 4, iclass 11, count 0 2006.239.07:56:22.59#ibcon#about to read 5, iclass 11, count 0 2006.239.07:56:22.59#ibcon#read 5, iclass 11, count 0 2006.239.07:56:22.59#ibcon#about to read 6, iclass 11, count 0 2006.239.07:56:22.59#ibcon#read 6, iclass 11, count 0 2006.239.07:56:22.59#ibcon#end of sib2, iclass 11, count 0 2006.239.07:56:22.59#ibcon#*mode == 0, iclass 11, count 0 2006.239.07:56:22.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.07:56:22.59#ibcon#[27=USB\r\n] 2006.239.07:56:22.59#ibcon#*before write, iclass 11, count 0 2006.239.07:56:22.59#ibcon#enter sib2, iclass 11, count 0 2006.239.07:56:22.59#ibcon#flushed, iclass 11, count 0 2006.239.07:56:22.59#ibcon#about to write, iclass 11, count 0 2006.239.07:56:22.59#ibcon#wrote, iclass 11, count 0 2006.239.07:56:22.59#ibcon#about to read 3, iclass 11, count 0 2006.239.07:56:22.62#ibcon#read 3, iclass 11, count 0 2006.239.07:56:22.62#ibcon#about to read 4, iclass 11, count 0 2006.239.07:56:22.62#ibcon#read 4, iclass 11, count 0 2006.239.07:56:22.62#ibcon#about to read 5, iclass 11, count 0 2006.239.07:56:22.62#ibcon#read 5, iclass 11, count 0 2006.239.07:56:22.62#ibcon#about to read 6, iclass 11, count 0 2006.239.07:56:22.62#ibcon#read 6, iclass 11, count 0 2006.239.07:56:22.62#ibcon#end of sib2, iclass 11, count 0 2006.239.07:56:22.62#ibcon#*after write, iclass 11, count 0 2006.239.07:56:22.62#ibcon#*before return 0, iclass 11, count 0 2006.239.07:56:22.62#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:22.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.07:56:22.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.07:56:22.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.07:56:22.62$vc4f8/vabw=wide 2006.239.07:56:22.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.07:56:22.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.07:56:22.62#ibcon#ireg 8 cls_cnt 0 2006.239.07:56:22.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:56:22.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:56:22.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:56:22.62#ibcon#enter wrdev, iclass 13, count 0 2006.239.07:56:22.62#ibcon#first serial, iclass 13, count 0 2006.239.07:56:22.62#ibcon#enter sib2, iclass 13, count 0 2006.239.07:56:22.62#ibcon#flushed, iclass 13, count 0 2006.239.07:56:22.62#ibcon#about to write, iclass 13, count 0 2006.239.07:56:22.62#ibcon#wrote, iclass 13, count 0 2006.239.07:56:22.62#ibcon#about to read 3, iclass 13, count 0 2006.239.07:56:22.64#ibcon#read 3, iclass 13, count 0 2006.239.07:56:22.64#ibcon#about to read 4, iclass 13, count 0 2006.239.07:56:22.64#ibcon#read 4, iclass 13, count 0 2006.239.07:56:22.64#ibcon#about to read 5, iclass 13, count 0 2006.239.07:56:22.64#ibcon#read 5, iclass 13, count 0 2006.239.07:56:22.64#ibcon#about to read 6, iclass 13, count 0 2006.239.07:56:22.64#ibcon#read 6, iclass 13, count 0 2006.239.07:56:22.64#ibcon#end of sib2, iclass 13, count 0 2006.239.07:56:22.64#ibcon#*mode == 0, iclass 13, count 0 2006.239.07:56:22.64#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.07:56:22.64#ibcon#[25=BW32\r\n] 2006.239.07:56:22.64#ibcon#*before write, iclass 13, count 0 2006.239.07:56:22.64#ibcon#enter sib2, iclass 13, count 0 2006.239.07:56:22.64#ibcon#flushed, iclass 13, count 0 2006.239.07:56:22.64#ibcon#about to write, iclass 13, count 0 2006.239.07:56:22.64#ibcon#wrote, iclass 13, count 0 2006.239.07:56:22.64#ibcon#about to read 3, iclass 13, count 0 2006.239.07:56:22.67#ibcon#read 3, iclass 13, count 0 2006.239.07:56:22.67#ibcon#about to read 4, iclass 13, count 0 2006.239.07:56:22.67#ibcon#read 4, iclass 13, count 0 2006.239.07:56:22.67#ibcon#about to read 5, iclass 13, count 0 2006.239.07:56:22.67#ibcon#read 5, iclass 13, count 0 2006.239.07:56:22.67#ibcon#about to read 6, iclass 13, count 0 2006.239.07:56:22.67#ibcon#read 6, iclass 13, count 0 2006.239.07:56:22.67#ibcon#end of sib2, iclass 13, count 0 2006.239.07:56:22.67#ibcon#*after write, iclass 13, count 0 2006.239.07:56:22.67#ibcon#*before return 0, iclass 13, count 0 2006.239.07:56:22.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:56:22.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.07:56:22.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.07:56:22.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.07:56:22.67$vc4f8/vbbw=wide 2006.239.07:56:22.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.07:56:22.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.07:56:22.67#ibcon#ireg 8 cls_cnt 0 2006.239.07:56:22.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:56:22.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:56:22.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:56:22.74#ibcon#enter wrdev, iclass 15, count 0 2006.239.07:56:22.74#ibcon#first serial, iclass 15, count 0 2006.239.07:56:22.74#ibcon#enter sib2, iclass 15, count 0 2006.239.07:56:22.74#ibcon#flushed, iclass 15, count 0 2006.239.07:56:22.74#ibcon#about to write, iclass 15, count 0 2006.239.07:56:22.74#ibcon#wrote, iclass 15, count 0 2006.239.07:56:22.74#ibcon#about to read 3, iclass 15, count 0 2006.239.07:56:22.76#ibcon#read 3, iclass 15, count 0 2006.239.07:56:22.76#ibcon#about to read 4, iclass 15, count 0 2006.239.07:56:22.76#ibcon#read 4, iclass 15, count 0 2006.239.07:56:22.76#ibcon#about to read 5, iclass 15, count 0 2006.239.07:56:22.76#ibcon#read 5, iclass 15, count 0 2006.239.07:56:22.76#ibcon#about to read 6, iclass 15, count 0 2006.239.07:56:22.76#ibcon#read 6, iclass 15, count 0 2006.239.07:56:22.76#ibcon#end of sib2, iclass 15, count 0 2006.239.07:56:22.76#ibcon#*mode == 0, iclass 15, count 0 2006.239.07:56:22.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.07:56:22.76#ibcon#[27=BW32\r\n] 2006.239.07:56:22.76#ibcon#*before write, iclass 15, count 0 2006.239.07:56:22.76#ibcon#enter sib2, iclass 15, count 0 2006.239.07:56:22.76#ibcon#flushed, iclass 15, count 0 2006.239.07:56:22.76#ibcon#about to write, iclass 15, count 0 2006.239.07:56:22.76#ibcon#wrote, iclass 15, count 0 2006.239.07:56:22.76#ibcon#about to read 3, iclass 15, count 0 2006.239.07:56:22.79#ibcon#read 3, iclass 15, count 0 2006.239.07:56:22.79#ibcon#about to read 4, iclass 15, count 0 2006.239.07:56:22.79#ibcon#read 4, iclass 15, count 0 2006.239.07:56:22.79#ibcon#about to read 5, iclass 15, count 0 2006.239.07:56:22.79#ibcon#read 5, iclass 15, count 0 2006.239.07:56:22.79#ibcon#about to read 6, iclass 15, count 0 2006.239.07:56:22.79#ibcon#read 6, iclass 15, count 0 2006.239.07:56:22.79#ibcon#end of sib2, iclass 15, count 0 2006.239.07:56:22.79#ibcon#*after write, iclass 15, count 0 2006.239.07:56:22.79#ibcon#*before return 0, iclass 15, count 0 2006.239.07:56:22.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:56:22.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.07:56:22.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.07:56:22.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.07:56:22.79$4f8m12a/ifd4f 2006.239.07:56:22.79$ifd4f/lo= 2006.239.07:56:22.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:56:22.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:56:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:56:22.79$ifd4f/patch= 2006.239.07:56:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:56:22.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:56:22.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:56:22.79$4f8m12a/"form=m,16.000,1:2 2006.239.07:56:22.79$4f8m12a/"tpicd 2006.239.07:56:22.79$4f8m12a/echo=off 2006.239.07:56:22.79$4f8m12a/xlog=off 2006.239.07:56:22.79:!2006.239.07:58:30 2006.239.07:57:09.13#trakl#Source acquired 2006.239.07:57:11.13#flagr#flagr/antenna,acquired 2006.239.07:58:30.00:preob 2006.239.07:58:30.13/onsource/TRACKING 2006.239.07:58:30.13:!2006.239.07:58:40 2006.239.07:58:40.00:data_valid=on 2006.239.07:58:40.00:midob 2006.239.07:58:41.13/onsource/TRACKING 2006.239.07:58:41.13/wx/25.19,1011.6,79 2006.239.07:58:41.21/cable/+6.4141E-03 2006.239.07:58:42.30/va/01,08,usb,yes,31,33 2006.239.07:58:42.30/va/02,07,usb,yes,31,33 2006.239.07:58:42.30/va/03,07,usb,yes,29,30 2006.239.07:58:42.30/va/04,07,usb,yes,33,35 2006.239.07:58:42.30/va/05,08,usb,yes,30,32 2006.239.07:58:42.30/va/06,07,usb,yes,33,33 2006.239.07:58:42.30/va/07,07,usb,yes,33,32 2006.239.07:58:42.30/va/08,07,usb,yes,35,35 2006.239.07:58:42.53/valo/01,532.99,yes,locked 2006.239.07:58:42.53/valo/02,572.99,yes,locked 2006.239.07:58:42.53/valo/03,672.99,yes,locked 2006.239.07:58:42.53/valo/04,832.99,yes,locked 2006.239.07:58:42.53/valo/05,652.99,yes,locked 2006.239.07:58:42.53/valo/06,772.99,yes,locked 2006.239.07:58:42.53/valo/07,832.99,yes,locked 2006.239.07:58:42.53/valo/08,852.99,yes,locked 2006.239.07:58:43.62/vb/01,04,usb,yes,31,30 2006.239.07:58:43.62/vb/02,04,usb,yes,33,34 2006.239.07:58:43.62/vb/03,04,usb,yes,29,33 2006.239.07:58:43.62/vb/04,04,usb,yes,30,30 2006.239.07:58:43.62/vb/05,04,usb,yes,28,32 2006.239.07:58:43.62/vb/06,04,usb,yes,29,32 2006.239.07:58:43.62/vb/07,04,usb,yes,32,31 2006.239.07:58:43.62/vb/08,04,usb,yes,29,32 2006.239.07:58:43.85/vblo/01,632.99,yes,locked 2006.239.07:58:43.85/vblo/02,640.99,yes,locked 2006.239.07:58:43.85/vblo/03,656.99,yes,locked 2006.239.07:58:43.85/vblo/04,712.99,yes,locked 2006.239.07:58:43.85/vblo/05,744.99,yes,locked 2006.239.07:58:43.85/vblo/06,752.99,yes,locked 2006.239.07:58:43.85/vblo/07,734.99,yes,locked 2006.239.07:58:43.85/vblo/08,744.99,yes,locked 2006.239.07:58:44.00/vabw/8 2006.239.07:58:44.15/vbbw/8 2006.239.07:58:44.24/xfe/off,on,14.0 2006.239.07:58:44.61/ifatt/23,28,28,28 2006.239.07:58:45.08/fmout-gps/S +4.44E-07 2006.239.07:58:45.12:!2006.239.07:59:40 2006.239.07:59:40.01:data_valid=off 2006.239.07:59:40.01:postob 2006.239.07:59:40.18/cable/+6.4134E-03 2006.239.07:59:40.22/wx/25.18,1011.6,79 2006.239.07:59:41.07/fmout-gps/S +4.43E-07 2006.239.07:59:41.07:scan_name=239-0800,k06239,60 2006.239.07:59:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.239.07:59:41.14#flagr#flagr/antenna,new-source 2006.239.07:59:42.14:checkk5 2006.239.07:59:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.239.07:59:42.98/chk_autoobs//k5ts2/ autoobs is running! 2006.239.07:59:43.36/chk_autoobs//k5ts3/ autoobs is running! 2006.239.07:59:43.75/chk_autoobs//k5ts4/ autoobs is running! 2006.239.07:59:44.12/chk_obsdata//k5ts1/T2390758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:59:44.50/chk_obsdata//k5ts2/T2390758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:59:44.87/chk_obsdata//k5ts3/T2390758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:59:45.24/chk_obsdata//k5ts4/T2390758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.07:59:45.93/k5log//k5ts1_log_newline 2006.239.07:59:46.63/k5log//k5ts2_log_newline 2006.239.07:59:47.32/k5log//k5ts3_log_newline 2006.239.07:59:48.01/k5log//k5ts4_log_newline 2006.239.07:59:48.03/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.07:59:48.03:4f8m12a=2 2006.239.07:59:48.03$4f8m12a/echo=on 2006.239.07:59:48.03$4f8m12a/pcalon 2006.239.07:59:48.03$pcalon/"no phase cal control is implemented here 2006.239.07:59:48.03$4f8m12a/"tpicd=stop 2006.239.07:59:48.03$4f8m12a/vc4f8 2006.239.07:59:48.03$vc4f8/valo=1,532.99 2006.239.07:59:48.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:59:48.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:59:48.04#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:48.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:48.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:48.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:48.04#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:59:48.04#ibcon#first serial, iclass 26, count 0 2006.239.07:59:48.04#ibcon#enter sib2, iclass 26, count 0 2006.239.07:59:48.04#ibcon#flushed, iclass 26, count 0 2006.239.07:59:48.04#ibcon#about to write, iclass 26, count 0 2006.239.07:59:48.04#ibcon#wrote, iclass 26, count 0 2006.239.07:59:48.04#ibcon#about to read 3, iclass 26, count 0 2006.239.07:59:48.08#ibcon#read 3, iclass 26, count 0 2006.239.07:59:48.08#ibcon#about to read 4, iclass 26, count 0 2006.239.07:59:48.08#ibcon#read 4, iclass 26, count 0 2006.239.07:59:48.08#ibcon#about to read 5, iclass 26, count 0 2006.239.07:59:48.08#ibcon#read 5, iclass 26, count 0 2006.239.07:59:48.08#ibcon#about to read 6, iclass 26, count 0 2006.239.07:59:48.08#ibcon#read 6, iclass 26, count 0 2006.239.07:59:48.08#ibcon#end of sib2, iclass 26, count 0 2006.239.07:59:48.08#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:59:48.08#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:59:48.08#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.07:59:48.08#ibcon#*before write, iclass 26, count 0 2006.239.07:59:48.08#ibcon#enter sib2, iclass 26, count 0 2006.239.07:59:48.08#ibcon#flushed, iclass 26, count 0 2006.239.07:59:48.08#ibcon#about to write, iclass 26, count 0 2006.239.07:59:48.08#ibcon#wrote, iclass 26, count 0 2006.239.07:59:48.08#ibcon#about to read 3, iclass 26, count 0 2006.239.07:59:48.13#ibcon#read 3, iclass 26, count 0 2006.239.07:59:48.13#ibcon#about to read 4, iclass 26, count 0 2006.239.07:59:48.13#ibcon#read 4, iclass 26, count 0 2006.239.07:59:48.13#ibcon#about to read 5, iclass 26, count 0 2006.239.07:59:48.13#ibcon#read 5, iclass 26, count 0 2006.239.07:59:48.13#ibcon#about to read 6, iclass 26, count 0 2006.239.07:59:48.13#ibcon#read 6, iclass 26, count 0 2006.239.07:59:48.13#ibcon#end of sib2, iclass 26, count 0 2006.239.07:59:48.13#ibcon#*after write, iclass 26, count 0 2006.239.07:59:48.13#ibcon#*before return 0, iclass 26, count 0 2006.239.07:59:48.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:48.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:48.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:59:48.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:59:48.13$vc4f8/va=1,8 2006.239.07:59:48.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:59:48.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:59:48.13#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:48.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:48.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:48.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:48.13#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:59:48.13#ibcon#first serial, iclass 28, count 2 2006.239.07:59:48.13#ibcon#enter sib2, iclass 28, count 2 2006.239.07:59:48.13#ibcon#flushed, iclass 28, count 2 2006.239.07:59:48.13#ibcon#about to write, iclass 28, count 2 2006.239.07:59:48.13#ibcon#wrote, iclass 28, count 2 2006.239.07:59:48.13#ibcon#about to read 3, iclass 28, count 2 2006.239.07:59:48.15#ibcon#read 3, iclass 28, count 2 2006.239.07:59:48.15#ibcon#about to read 4, iclass 28, count 2 2006.239.07:59:48.15#ibcon#read 4, iclass 28, count 2 2006.239.07:59:48.15#ibcon#about to read 5, iclass 28, count 2 2006.239.07:59:48.15#ibcon#read 5, iclass 28, count 2 2006.239.07:59:48.15#ibcon#about to read 6, iclass 28, count 2 2006.239.07:59:48.15#ibcon#read 6, iclass 28, count 2 2006.239.07:59:48.15#ibcon#end of sib2, iclass 28, count 2 2006.239.07:59:48.15#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:59:48.15#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:59:48.15#ibcon#[25=AT01-08\r\n] 2006.239.07:59:48.15#ibcon#*before write, iclass 28, count 2 2006.239.07:59:48.15#ibcon#enter sib2, iclass 28, count 2 2006.239.07:59:48.15#ibcon#flushed, iclass 28, count 2 2006.239.07:59:48.15#ibcon#about to write, iclass 28, count 2 2006.239.07:59:48.15#ibcon#wrote, iclass 28, count 2 2006.239.07:59:48.15#ibcon#about to read 3, iclass 28, count 2 2006.239.07:59:48.18#ibcon#read 3, iclass 28, count 2 2006.239.07:59:48.18#ibcon#about to read 4, iclass 28, count 2 2006.239.07:59:48.18#ibcon#read 4, iclass 28, count 2 2006.239.07:59:48.18#ibcon#about to read 5, iclass 28, count 2 2006.239.07:59:48.18#ibcon#read 5, iclass 28, count 2 2006.239.07:59:48.18#ibcon#about to read 6, iclass 28, count 2 2006.239.07:59:48.18#ibcon#read 6, iclass 28, count 2 2006.239.07:59:48.18#ibcon#end of sib2, iclass 28, count 2 2006.239.07:59:48.18#ibcon#*after write, iclass 28, count 2 2006.239.07:59:48.18#ibcon#*before return 0, iclass 28, count 2 2006.239.07:59:48.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:48.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:48.18#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:59:48.18#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:48.18#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:48.30#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:48.30#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:48.30#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:59:48.30#ibcon#first serial, iclass 28, count 0 2006.239.07:59:48.30#ibcon#enter sib2, iclass 28, count 0 2006.239.07:59:48.30#ibcon#flushed, iclass 28, count 0 2006.239.07:59:48.30#ibcon#about to write, iclass 28, count 0 2006.239.07:59:48.30#ibcon#wrote, iclass 28, count 0 2006.239.07:59:48.30#ibcon#about to read 3, iclass 28, count 0 2006.239.07:59:48.32#ibcon#read 3, iclass 28, count 0 2006.239.07:59:48.32#ibcon#about to read 4, iclass 28, count 0 2006.239.07:59:48.32#ibcon#read 4, iclass 28, count 0 2006.239.07:59:48.32#ibcon#about to read 5, iclass 28, count 0 2006.239.07:59:48.32#ibcon#read 5, iclass 28, count 0 2006.239.07:59:48.32#ibcon#about to read 6, iclass 28, count 0 2006.239.07:59:48.32#ibcon#read 6, iclass 28, count 0 2006.239.07:59:48.32#ibcon#end of sib2, iclass 28, count 0 2006.239.07:59:48.32#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:59:48.32#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:59:48.32#ibcon#[25=USB\r\n] 2006.239.07:59:48.32#ibcon#*before write, iclass 28, count 0 2006.239.07:59:48.32#ibcon#enter sib2, iclass 28, count 0 2006.239.07:59:48.32#ibcon#flushed, iclass 28, count 0 2006.239.07:59:48.32#ibcon#about to write, iclass 28, count 0 2006.239.07:59:48.32#ibcon#wrote, iclass 28, count 0 2006.239.07:59:48.32#ibcon#about to read 3, iclass 28, count 0 2006.239.07:59:48.35#ibcon#read 3, iclass 28, count 0 2006.239.07:59:48.35#ibcon#about to read 4, iclass 28, count 0 2006.239.07:59:48.35#ibcon#read 4, iclass 28, count 0 2006.239.07:59:48.35#ibcon#about to read 5, iclass 28, count 0 2006.239.07:59:48.35#ibcon#read 5, iclass 28, count 0 2006.239.07:59:48.35#ibcon#about to read 6, iclass 28, count 0 2006.239.07:59:48.35#ibcon#read 6, iclass 28, count 0 2006.239.07:59:48.35#ibcon#end of sib2, iclass 28, count 0 2006.239.07:59:48.35#ibcon#*after write, iclass 28, count 0 2006.239.07:59:48.35#ibcon#*before return 0, iclass 28, count 0 2006.239.07:59:48.35#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:48.35#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:48.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:59:48.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:59:48.35$vc4f8/valo=2,572.99 2006.239.07:59:48.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:59:48.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:59:48.35#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:48.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:48.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:48.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:48.35#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:59:48.35#ibcon#first serial, iclass 30, count 0 2006.239.07:59:48.35#ibcon#enter sib2, iclass 30, count 0 2006.239.07:59:48.35#ibcon#flushed, iclass 30, count 0 2006.239.07:59:48.35#ibcon#about to write, iclass 30, count 0 2006.239.07:59:48.35#ibcon#wrote, iclass 30, count 0 2006.239.07:59:48.35#ibcon#about to read 3, iclass 30, count 0 2006.239.07:59:48.37#ibcon#read 3, iclass 30, count 0 2006.239.07:59:48.37#ibcon#about to read 4, iclass 30, count 0 2006.239.07:59:48.37#ibcon#read 4, iclass 30, count 0 2006.239.07:59:48.37#ibcon#about to read 5, iclass 30, count 0 2006.239.07:59:48.37#ibcon#read 5, iclass 30, count 0 2006.239.07:59:48.37#ibcon#about to read 6, iclass 30, count 0 2006.239.07:59:48.37#ibcon#read 6, iclass 30, count 0 2006.239.07:59:48.37#ibcon#end of sib2, iclass 30, count 0 2006.239.07:59:48.37#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:59:48.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:59:48.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.07:59:48.37#ibcon#*before write, iclass 30, count 0 2006.239.07:59:48.37#ibcon#enter sib2, iclass 30, count 0 2006.239.07:59:48.37#ibcon#flushed, iclass 30, count 0 2006.239.07:59:48.37#ibcon#about to write, iclass 30, count 0 2006.239.07:59:48.37#ibcon#wrote, iclass 30, count 0 2006.239.07:59:48.37#ibcon#about to read 3, iclass 30, count 0 2006.239.07:59:48.41#ibcon#read 3, iclass 30, count 0 2006.239.07:59:48.41#ibcon#about to read 4, iclass 30, count 0 2006.239.07:59:48.41#ibcon#read 4, iclass 30, count 0 2006.239.07:59:48.41#ibcon#about to read 5, iclass 30, count 0 2006.239.07:59:48.41#ibcon#read 5, iclass 30, count 0 2006.239.07:59:48.41#ibcon#about to read 6, iclass 30, count 0 2006.239.07:59:48.41#ibcon#read 6, iclass 30, count 0 2006.239.07:59:48.41#ibcon#end of sib2, iclass 30, count 0 2006.239.07:59:48.41#ibcon#*after write, iclass 30, count 0 2006.239.07:59:48.41#ibcon#*before return 0, iclass 30, count 0 2006.239.07:59:48.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:48.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:48.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:59:48.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:59:48.41$vc4f8/va=2,7 2006.239.07:59:48.41#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:59:48.41#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:59:48.41#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:48.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:48.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:48.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:48.47#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:59:48.47#ibcon#first serial, iclass 32, count 2 2006.239.07:59:48.47#ibcon#enter sib2, iclass 32, count 2 2006.239.07:59:48.47#ibcon#flushed, iclass 32, count 2 2006.239.07:59:48.47#ibcon#about to write, iclass 32, count 2 2006.239.07:59:48.47#ibcon#wrote, iclass 32, count 2 2006.239.07:59:48.47#ibcon#about to read 3, iclass 32, count 2 2006.239.07:59:48.49#ibcon#read 3, iclass 32, count 2 2006.239.07:59:48.49#ibcon#about to read 4, iclass 32, count 2 2006.239.07:59:48.49#ibcon#read 4, iclass 32, count 2 2006.239.07:59:48.49#ibcon#about to read 5, iclass 32, count 2 2006.239.07:59:48.49#ibcon#read 5, iclass 32, count 2 2006.239.07:59:48.49#ibcon#about to read 6, iclass 32, count 2 2006.239.07:59:48.49#ibcon#read 6, iclass 32, count 2 2006.239.07:59:48.49#ibcon#end of sib2, iclass 32, count 2 2006.239.07:59:48.49#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:59:48.49#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:59:48.49#ibcon#[25=AT02-07\r\n] 2006.239.07:59:48.49#ibcon#*before write, iclass 32, count 2 2006.239.07:59:48.49#ibcon#enter sib2, iclass 32, count 2 2006.239.07:59:48.49#ibcon#flushed, iclass 32, count 2 2006.239.07:59:48.49#ibcon#about to write, iclass 32, count 2 2006.239.07:59:48.49#ibcon#wrote, iclass 32, count 2 2006.239.07:59:48.49#ibcon#about to read 3, iclass 32, count 2 2006.239.07:59:48.52#ibcon#read 3, iclass 32, count 2 2006.239.07:59:48.52#ibcon#about to read 4, iclass 32, count 2 2006.239.07:59:48.52#ibcon#read 4, iclass 32, count 2 2006.239.07:59:48.52#ibcon#about to read 5, iclass 32, count 2 2006.239.07:59:48.52#ibcon#read 5, iclass 32, count 2 2006.239.07:59:48.52#ibcon#about to read 6, iclass 32, count 2 2006.239.07:59:48.52#ibcon#read 6, iclass 32, count 2 2006.239.07:59:48.52#ibcon#end of sib2, iclass 32, count 2 2006.239.07:59:48.52#ibcon#*after write, iclass 32, count 2 2006.239.07:59:48.52#ibcon#*before return 0, iclass 32, count 2 2006.239.07:59:48.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:48.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:48.52#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:59:48.52#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:48.52#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:48.64#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:48.64#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:48.64#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:59:48.64#ibcon#first serial, iclass 32, count 0 2006.239.07:59:48.64#ibcon#enter sib2, iclass 32, count 0 2006.239.07:59:48.64#ibcon#flushed, iclass 32, count 0 2006.239.07:59:48.64#ibcon#about to write, iclass 32, count 0 2006.239.07:59:48.64#ibcon#wrote, iclass 32, count 0 2006.239.07:59:48.64#ibcon#about to read 3, iclass 32, count 0 2006.239.07:59:48.66#ibcon#read 3, iclass 32, count 0 2006.239.07:59:48.66#ibcon#about to read 4, iclass 32, count 0 2006.239.07:59:48.66#ibcon#read 4, iclass 32, count 0 2006.239.07:59:48.66#ibcon#about to read 5, iclass 32, count 0 2006.239.07:59:48.66#ibcon#read 5, iclass 32, count 0 2006.239.07:59:48.66#ibcon#about to read 6, iclass 32, count 0 2006.239.07:59:48.66#ibcon#read 6, iclass 32, count 0 2006.239.07:59:48.66#ibcon#end of sib2, iclass 32, count 0 2006.239.07:59:48.66#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:59:48.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:59:48.66#ibcon#[25=USB\r\n] 2006.239.07:59:48.66#ibcon#*before write, iclass 32, count 0 2006.239.07:59:48.66#ibcon#enter sib2, iclass 32, count 0 2006.239.07:59:48.66#ibcon#flushed, iclass 32, count 0 2006.239.07:59:48.66#ibcon#about to write, iclass 32, count 0 2006.239.07:59:48.66#ibcon#wrote, iclass 32, count 0 2006.239.07:59:48.66#ibcon#about to read 3, iclass 32, count 0 2006.239.07:59:48.69#ibcon#read 3, iclass 32, count 0 2006.239.07:59:48.69#ibcon#about to read 4, iclass 32, count 0 2006.239.07:59:48.69#ibcon#read 4, iclass 32, count 0 2006.239.07:59:48.69#ibcon#about to read 5, iclass 32, count 0 2006.239.07:59:48.69#ibcon#read 5, iclass 32, count 0 2006.239.07:59:48.69#ibcon#about to read 6, iclass 32, count 0 2006.239.07:59:48.69#ibcon#read 6, iclass 32, count 0 2006.239.07:59:48.69#ibcon#end of sib2, iclass 32, count 0 2006.239.07:59:48.69#ibcon#*after write, iclass 32, count 0 2006.239.07:59:48.69#ibcon#*before return 0, iclass 32, count 0 2006.239.07:59:48.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:48.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:48.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:59:48.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:59:48.69$vc4f8/valo=3,672.99 2006.239.07:59:48.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:59:48.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:59:48.69#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:48.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:48.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:48.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:48.69#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:59:48.69#ibcon#first serial, iclass 34, count 0 2006.239.07:59:48.69#ibcon#enter sib2, iclass 34, count 0 2006.239.07:59:48.69#ibcon#flushed, iclass 34, count 0 2006.239.07:59:48.69#ibcon#about to write, iclass 34, count 0 2006.239.07:59:48.69#ibcon#wrote, iclass 34, count 0 2006.239.07:59:48.69#ibcon#about to read 3, iclass 34, count 0 2006.239.07:59:48.71#ibcon#read 3, iclass 34, count 0 2006.239.07:59:48.71#ibcon#about to read 4, iclass 34, count 0 2006.239.07:59:48.71#ibcon#read 4, iclass 34, count 0 2006.239.07:59:48.71#ibcon#about to read 5, iclass 34, count 0 2006.239.07:59:48.71#ibcon#read 5, iclass 34, count 0 2006.239.07:59:48.71#ibcon#about to read 6, iclass 34, count 0 2006.239.07:59:48.71#ibcon#read 6, iclass 34, count 0 2006.239.07:59:48.71#ibcon#end of sib2, iclass 34, count 0 2006.239.07:59:48.71#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:59:48.71#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:59:48.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.07:59:48.71#ibcon#*before write, iclass 34, count 0 2006.239.07:59:48.71#ibcon#enter sib2, iclass 34, count 0 2006.239.07:59:48.71#ibcon#flushed, iclass 34, count 0 2006.239.07:59:48.71#ibcon#about to write, iclass 34, count 0 2006.239.07:59:48.71#ibcon#wrote, iclass 34, count 0 2006.239.07:59:48.71#ibcon#about to read 3, iclass 34, count 0 2006.239.07:59:48.75#ibcon#read 3, iclass 34, count 0 2006.239.07:59:48.75#ibcon#about to read 4, iclass 34, count 0 2006.239.07:59:48.75#ibcon#read 4, iclass 34, count 0 2006.239.07:59:48.75#ibcon#about to read 5, iclass 34, count 0 2006.239.07:59:48.75#ibcon#read 5, iclass 34, count 0 2006.239.07:59:48.75#ibcon#about to read 6, iclass 34, count 0 2006.239.07:59:48.75#ibcon#read 6, iclass 34, count 0 2006.239.07:59:48.75#ibcon#end of sib2, iclass 34, count 0 2006.239.07:59:48.75#ibcon#*after write, iclass 34, count 0 2006.239.07:59:48.75#ibcon#*before return 0, iclass 34, count 0 2006.239.07:59:48.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:48.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:48.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:59:48.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:59:48.75$vc4f8/va=3,7 2006.239.07:59:48.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:59:48.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:59:48.75#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:48.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:48.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:48.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:48.81#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:59:48.81#ibcon#first serial, iclass 36, count 2 2006.239.07:59:48.81#ibcon#enter sib2, iclass 36, count 2 2006.239.07:59:48.81#ibcon#flushed, iclass 36, count 2 2006.239.07:59:48.81#ibcon#about to write, iclass 36, count 2 2006.239.07:59:48.81#ibcon#wrote, iclass 36, count 2 2006.239.07:59:48.81#ibcon#about to read 3, iclass 36, count 2 2006.239.07:59:48.83#ibcon#read 3, iclass 36, count 2 2006.239.07:59:48.83#ibcon#about to read 4, iclass 36, count 2 2006.239.07:59:48.83#ibcon#read 4, iclass 36, count 2 2006.239.07:59:48.83#ibcon#about to read 5, iclass 36, count 2 2006.239.07:59:48.83#ibcon#read 5, iclass 36, count 2 2006.239.07:59:48.83#ibcon#about to read 6, iclass 36, count 2 2006.239.07:59:48.83#ibcon#read 6, iclass 36, count 2 2006.239.07:59:48.83#ibcon#end of sib2, iclass 36, count 2 2006.239.07:59:48.83#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:59:48.83#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:59:48.83#ibcon#[25=AT03-07\r\n] 2006.239.07:59:48.83#ibcon#*before write, iclass 36, count 2 2006.239.07:59:48.83#ibcon#enter sib2, iclass 36, count 2 2006.239.07:59:48.83#ibcon#flushed, iclass 36, count 2 2006.239.07:59:48.83#ibcon#about to write, iclass 36, count 2 2006.239.07:59:48.83#ibcon#wrote, iclass 36, count 2 2006.239.07:59:48.83#ibcon#about to read 3, iclass 36, count 2 2006.239.07:59:48.86#ibcon#read 3, iclass 36, count 2 2006.239.07:59:48.86#ibcon#about to read 4, iclass 36, count 2 2006.239.07:59:48.86#ibcon#read 4, iclass 36, count 2 2006.239.07:59:48.86#ibcon#about to read 5, iclass 36, count 2 2006.239.07:59:48.86#ibcon#read 5, iclass 36, count 2 2006.239.07:59:48.86#ibcon#about to read 6, iclass 36, count 2 2006.239.07:59:48.86#ibcon#read 6, iclass 36, count 2 2006.239.07:59:48.86#ibcon#end of sib2, iclass 36, count 2 2006.239.07:59:48.86#ibcon#*after write, iclass 36, count 2 2006.239.07:59:48.86#ibcon#*before return 0, iclass 36, count 2 2006.239.07:59:48.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:48.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:48.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:59:48.86#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:48.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:48.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:48.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:48.98#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:59:48.98#ibcon#first serial, iclass 36, count 0 2006.239.07:59:48.98#ibcon#enter sib2, iclass 36, count 0 2006.239.07:59:48.98#ibcon#flushed, iclass 36, count 0 2006.239.07:59:48.98#ibcon#about to write, iclass 36, count 0 2006.239.07:59:48.98#ibcon#wrote, iclass 36, count 0 2006.239.07:59:48.98#ibcon#about to read 3, iclass 36, count 0 2006.239.07:59:49.00#ibcon#read 3, iclass 36, count 0 2006.239.07:59:49.00#ibcon#about to read 4, iclass 36, count 0 2006.239.07:59:49.00#ibcon#read 4, iclass 36, count 0 2006.239.07:59:49.00#ibcon#about to read 5, iclass 36, count 0 2006.239.07:59:49.00#ibcon#read 5, iclass 36, count 0 2006.239.07:59:49.00#ibcon#about to read 6, iclass 36, count 0 2006.239.07:59:49.00#ibcon#read 6, iclass 36, count 0 2006.239.07:59:49.00#ibcon#end of sib2, iclass 36, count 0 2006.239.07:59:49.00#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:59:49.00#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:59:49.00#ibcon#[25=USB\r\n] 2006.239.07:59:49.00#ibcon#*before write, iclass 36, count 0 2006.239.07:59:49.00#ibcon#enter sib2, iclass 36, count 0 2006.239.07:59:49.00#ibcon#flushed, iclass 36, count 0 2006.239.07:59:49.00#ibcon#about to write, iclass 36, count 0 2006.239.07:59:49.00#ibcon#wrote, iclass 36, count 0 2006.239.07:59:49.00#ibcon#about to read 3, iclass 36, count 0 2006.239.07:59:49.03#ibcon#read 3, iclass 36, count 0 2006.239.07:59:49.03#ibcon#about to read 4, iclass 36, count 0 2006.239.07:59:49.03#ibcon#read 4, iclass 36, count 0 2006.239.07:59:49.03#ibcon#about to read 5, iclass 36, count 0 2006.239.07:59:49.03#ibcon#read 5, iclass 36, count 0 2006.239.07:59:49.03#ibcon#about to read 6, iclass 36, count 0 2006.239.07:59:49.03#ibcon#read 6, iclass 36, count 0 2006.239.07:59:49.03#ibcon#end of sib2, iclass 36, count 0 2006.239.07:59:49.03#ibcon#*after write, iclass 36, count 0 2006.239.07:59:49.03#ibcon#*before return 0, iclass 36, count 0 2006.239.07:59:49.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:49.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:49.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:59:49.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:59:49.03$vc4f8/valo=4,832.99 2006.239.07:59:49.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.07:59:49.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.07:59:49.03#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:49.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:49.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:49.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:49.03#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:59:49.03#ibcon#first serial, iclass 38, count 0 2006.239.07:59:49.03#ibcon#enter sib2, iclass 38, count 0 2006.239.07:59:49.03#ibcon#flushed, iclass 38, count 0 2006.239.07:59:49.03#ibcon#about to write, iclass 38, count 0 2006.239.07:59:49.03#ibcon#wrote, iclass 38, count 0 2006.239.07:59:49.03#ibcon#about to read 3, iclass 38, count 0 2006.239.07:59:49.05#ibcon#read 3, iclass 38, count 0 2006.239.07:59:49.05#ibcon#about to read 4, iclass 38, count 0 2006.239.07:59:49.05#ibcon#read 4, iclass 38, count 0 2006.239.07:59:49.05#ibcon#about to read 5, iclass 38, count 0 2006.239.07:59:49.05#ibcon#read 5, iclass 38, count 0 2006.239.07:59:49.05#ibcon#about to read 6, iclass 38, count 0 2006.239.07:59:49.05#ibcon#read 6, iclass 38, count 0 2006.239.07:59:49.05#ibcon#end of sib2, iclass 38, count 0 2006.239.07:59:49.05#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:59:49.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:59:49.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.07:59:49.05#ibcon#*before write, iclass 38, count 0 2006.239.07:59:49.05#ibcon#enter sib2, iclass 38, count 0 2006.239.07:59:49.05#ibcon#flushed, iclass 38, count 0 2006.239.07:59:49.05#ibcon#about to write, iclass 38, count 0 2006.239.07:59:49.05#ibcon#wrote, iclass 38, count 0 2006.239.07:59:49.05#ibcon#about to read 3, iclass 38, count 0 2006.239.07:59:49.09#ibcon#read 3, iclass 38, count 0 2006.239.07:59:49.09#ibcon#about to read 4, iclass 38, count 0 2006.239.07:59:49.09#ibcon#read 4, iclass 38, count 0 2006.239.07:59:49.09#ibcon#about to read 5, iclass 38, count 0 2006.239.07:59:49.09#ibcon#read 5, iclass 38, count 0 2006.239.07:59:49.09#ibcon#about to read 6, iclass 38, count 0 2006.239.07:59:49.09#ibcon#read 6, iclass 38, count 0 2006.239.07:59:49.09#ibcon#end of sib2, iclass 38, count 0 2006.239.07:59:49.09#ibcon#*after write, iclass 38, count 0 2006.239.07:59:49.09#ibcon#*before return 0, iclass 38, count 0 2006.239.07:59:49.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:49.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:49.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:59:49.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:59:49.09$vc4f8/va=4,7 2006.239.07:59:49.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.07:59:49.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.07:59:49.09#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:49.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:49.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:49.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:49.15#ibcon#enter wrdev, iclass 40, count 2 2006.239.07:59:49.15#ibcon#first serial, iclass 40, count 2 2006.239.07:59:49.15#ibcon#enter sib2, iclass 40, count 2 2006.239.07:59:49.15#ibcon#flushed, iclass 40, count 2 2006.239.07:59:49.15#ibcon#about to write, iclass 40, count 2 2006.239.07:59:49.15#ibcon#wrote, iclass 40, count 2 2006.239.07:59:49.15#ibcon#about to read 3, iclass 40, count 2 2006.239.07:59:49.17#ibcon#read 3, iclass 40, count 2 2006.239.07:59:49.17#ibcon#about to read 4, iclass 40, count 2 2006.239.07:59:49.17#ibcon#read 4, iclass 40, count 2 2006.239.07:59:49.17#ibcon#about to read 5, iclass 40, count 2 2006.239.07:59:49.17#ibcon#read 5, iclass 40, count 2 2006.239.07:59:49.17#ibcon#about to read 6, iclass 40, count 2 2006.239.07:59:49.17#ibcon#read 6, iclass 40, count 2 2006.239.07:59:49.17#ibcon#end of sib2, iclass 40, count 2 2006.239.07:59:49.17#ibcon#*mode == 0, iclass 40, count 2 2006.239.07:59:49.17#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.07:59:49.17#ibcon#[25=AT04-07\r\n] 2006.239.07:59:49.17#ibcon#*before write, iclass 40, count 2 2006.239.07:59:49.17#ibcon#enter sib2, iclass 40, count 2 2006.239.07:59:49.17#ibcon#flushed, iclass 40, count 2 2006.239.07:59:49.17#ibcon#about to write, iclass 40, count 2 2006.239.07:59:49.17#ibcon#wrote, iclass 40, count 2 2006.239.07:59:49.17#ibcon#about to read 3, iclass 40, count 2 2006.239.07:59:49.20#ibcon#read 3, iclass 40, count 2 2006.239.07:59:49.20#ibcon#about to read 4, iclass 40, count 2 2006.239.07:59:49.20#ibcon#read 4, iclass 40, count 2 2006.239.07:59:49.20#ibcon#about to read 5, iclass 40, count 2 2006.239.07:59:49.20#ibcon#read 5, iclass 40, count 2 2006.239.07:59:49.20#ibcon#about to read 6, iclass 40, count 2 2006.239.07:59:49.20#ibcon#read 6, iclass 40, count 2 2006.239.07:59:49.20#ibcon#end of sib2, iclass 40, count 2 2006.239.07:59:49.20#ibcon#*after write, iclass 40, count 2 2006.239.07:59:49.20#ibcon#*before return 0, iclass 40, count 2 2006.239.07:59:49.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:49.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:49.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.07:59:49.20#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:49.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:49.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:49.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:49.32#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:59:49.32#ibcon#first serial, iclass 40, count 0 2006.239.07:59:49.32#ibcon#enter sib2, iclass 40, count 0 2006.239.07:59:49.32#ibcon#flushed, iclass 40, count 0 2006.239.07:59:49.32#ibcon#about to write, iclass 40, count 0 2006.239.07:59:49.32#ibcon#wrote, iclass 40, count 0 2006.239.07:59:49.32#ibcon#about to read 3, iclass 40, count 0 2006.239.07:59:49.34#ibcon#read 3, iclass 40, count 0 2006.239.07:59:49.34#ibcon#about to read 4, iclass 40, count 0 2006.239.07:59:49.34#ibcon#read 4, iclass 40, count 0 2006.239.07:59:49.34#ibcon#about to read 5, iclass 40, count 0 2006.239.07:59:49.34#ibcon#read 5, iclass 40, count 0 2006.239.07:59:49.34#ibcon#about to read 6, iclass 40, count 0 2006.239.07:59:49.34#ibcon#read 6, iclass 40, count 0 2006.239.07:59:49.34#ibcon#end of sib2, iclass 40, count 0 2006.239.07:59:49.34#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:59:49.34#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:59:49.34#ibcon#[25=USB\r\n] 2006.239.07:59:49.34#ibcon#*before write, iclass 40, count 0 2006.239.07:59:49.34#ibcon#enter sib2, iclass 40, count 0 2006.239.07:59:49.34#ibcon#flushed, iclass 40, count 0 2006.239.07:59:49.34#ibcon#about to write, iclass 40, count 0 2006.239.07:59:49.34#ibcon#wrote, iclass 40, count 0 2006.239.07:59:49.34#ibcon#about to read 3, iclass 40, count 0 2006.239.07:59:49.37#ibcon#read 3, iclass 40, count 0 2006.239.07:59:49.37#ibcon#about to read 4, iclass 40, count 0 2006.239.07:59:49.37#ibcon#read 4, iclass 40, count 0 2006.239.07:59:49.37#ibcon#about to read 5, iclass 40, count 0 2006.239.07:59:49.37#ibcon#read 5, iclass 40, count 0 2006.239.07:59:49.37#ibcon#about to read 6, iclass 40, count 0 2006.239.07:59:49.37#ibcon#read 6, iclass 40, count 0 2006.239.07:59:49.37#ibcon#end of sib2, iclass 40, count 0 2006.239.07:59:49.37#ibcon#*after write, iclass 40, count 0 2006.239.07:59:49.37#ibcon#*before return 0, iclass 40, count 0 2006.239.07:59:49.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:49.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:49.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:59:49.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:59:49.37$vc4f8/valo=5,652.99 2006.239.07:59:49.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:59:49.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:59:49.37#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:49.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:49.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:49.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:49.37#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:59:49.37#ibcon#first serial, iclass 4, count 0 2006.239.07:59:49.37#ibcon#enter sib2, iclass 4, count 0 2006.239.07:59:49.37#ibcon#flushed, iclass 4, count 0 2006.239.07:59:49.37#ibcon#about to write, iclass 4, count 0 2006.239.07:59:49.37#ibcon#wrote, iclass 4, count 0 2006.239.07:59:49.37#ibcon#about to read 3, iclass 4, count 0 2006.239.07:59:49.39#ibcon#read 3, iclass 4, count 0 2006.239.07:59:49.39#ibcon#about to read 4, iclass 4, count 0 2006.239.07:59:49.39#ibcon#read 4, iclass 4, count 0 2006.239.07:59:49.39#ibcon#about to read 5, iclass 4, count 0 2006.239.07:59:49.39#ibcon#read 5, iclass 4, count 0 2006.239.07:59:49.39#ibcon#about to read 6, iclass 4, count 0 2006.239.07:59:49.39#ibcon#read 6, iclass 4, count 0 2006.239.07:59:49.39#ibcon#end of sib2, iclass 4, count 0 2006.239.07:59:49.39#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:59:49.39#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:59:49.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.07:59:49.39#ibcon#*before write, iclass 4, count 0 2006.239.07:59:49.39#ibcon#enter sib2, iclass 4, count 0 2006.239.07:59:49.39#ibcon#flushed, iclass 4, count 0 2006.239.07:59:49.39#ibcon#about to write, iclass 4, count 0 2006.239.07:59:49.39#ibcon#wrote, iclass 4, count 0 2006.239.07:59:49.39#ibcon#about to read 3, iclass 4, count 0 2006.239.07:59:49.43#ibcon#read 3, iclass 4, count 0 2006.239.07:59:49.43#ibcon#about to read 4, iclass 4, count 0 2006.239.07:59:49.43#ibcon#read 4, iclass 4, count 0 2006.239.07:59:49.43#ibcon#about to read 5, iclass 4, count 0 2006.239.07:59:49.43#ibcon#read 5, iclass 4, count 0 2006.239.07:59:49.43#ibcon#about to read 6, iclass 4, count 0 2006.239.07:59:49.43#ibcon#read 6, iclass 4, count 0 2006.239.07:59:49.43#ibcon#end of sib2, iclass 4, count 0 2006.239.07:59:49.43#ibcon#*after write, iclass 4, count 0 2006.239.07:59:49.43#ibcon#*before return 0, iclass 4, count 0 2006.239.07:59:49.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:49.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:49.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:59:49.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:59:49.43$vc4f8/va=5,8 2006.239.07:59:49.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:59:49.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:59:49.43#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:49.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:49.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:49.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:49.49#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:59:49.49#ibcon#first serial, iclass 6, count 2 2006.239.07:59:49.49#ibcon#enter sib2, iclass 6, count 2 2006.239.07:59:49.49#ibcon#flushed, iclass 6, count 2 2006.239.07:59:49.49#ibcon#about to write, iclass 6, count 2 2006.239.07:59:49.49#ibcon#wrote, iclass 6, count 2 2006.239.07:59:49.49#ibcon#about to read 3, iclass 6, count 2 2006.239.07:59:49.51#ibcon#read 3, iclass 6, count 2 2006.239.07:59:49.51#ibcon#about to read 4, iclass 6, count 2 2006.239.07:59:49.51#ibcon#read 4, iclass 6, count 2 2006.239.07:59:49.51#ibcon#about to read 5, iclass 6, count 2 2006.239.07:59:49.51#ibcon#read 5, iclass 6, count 2 2006.239.07:59:49.51#ibcon#about to read 6, iclass 6, count 2 2006.239.07:59:49.51#ibcon#read 6, iclass 6, count 2 2006.239.07:59:49.51#ibcon#end of sib2, iclass 6, count 2 2006.239.07:59:49.51#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:59:49.51#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:59:49.51#ibcon#[25=AT05-08\r\n] 2006.239.07:59:49.51#ibcon#*before write, iclass 6, count 2 2006.239.07:59:49.51#ibcon#enter sib2, iclass 6, count 2 2006.239.07:59:49.51#ibcon#flushed, iclass 6, count 2 2006.239.07:59:49.51#ibcon#about to write, iclass 6, count 2 2006.239.07:59:49.51#ibcon#wrote, iclass 6, count 2 2006.239.07:59:49.51#ibcon#about to read 3, iclass 6, count 2 2006.239.07:59:49.54#ibcon#read 3, iclass 6, count 2 2006.239.07:59:49.54#ibcon#about to read 4, iclass 6, count 2 2006.239.07:59:49.54#ibcon#read 4, iclass 6, count 2 2006.239.07:59:49.54#ibcon#about to read 5, iclass 6, count 2 2006.239.07:59:49.54#ibcon#read 5, iclass 6, count 2 2006.239.07:59:49.54#ibcon#about to read 6, iclass 6, count 2 2006.239.07:59:49.54#ibcon#read 6, iclass 6, count 2 2006.239.07:59:49.54#ibcon#end of sib2, iclass 6, count 2 2006.239.07:59:49.54#ibcon#*after write, iclass 6, count 2 2006.239.07:59:49.54#ibcon#*before return 0, iclass 6, count 2 2006.239.07:59:49.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:49.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:49.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:59:49.54#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:49.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:49.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:49.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:49.66#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:59:49.66#ibcon#first serial, iclass 6, count 0 2006.239.07:59:49.66#ibcon#enter sib2, iclass 6, count 0 2006.239.07:59:49.66#ibcon#flushed, iclass 6, count 0 2006.239.07:59:49.66#ibcon#about to write, iclass 6, count 0 2006.239.07:59:49.66#ibcon#wrote, iclass 6, count 0 2006.239.07:59:49.66#ibcon#about to read 3, iclass 6, count 0 2006.239.07:59:49.68#ibcon#read 3, iclass 6, count 0 2006.239.07:59:49.68#ibcon#about to read 4, iclass 6, count 0 2006.239.07:59:49.68#ibcon#read 4, iclass 6, count 0 2006.239.07:59:49.68#ibcon#about to read 5, iclass 6, count 0 2006.239.07:59:49.68#ibcon#read 5, iclass 6, count 0 2006.239.07:59:49.68#ibcon#about to read 6, iclass 6, count 0 2006.239.07:59:49.68#ibcon#read 6, iclass 6, count 0 2006.239.07:59:49.68#ibcon#end of sib2, iclass 6, count 0 2006.239.07:59:49.68#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:59:49.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:59:49.68#ibcon#[25=USB\r\n] 2006.239.07:59:49.68#ibcon#*before write, iclass 6, count 0 2006.239.07:59:49.68#ibcon#enter sib2, iclass 6, count 0 2006.239.07:59:49.68#ibcon#flushed, iclass 6, count 0 2006.239.07:59:49.68#ibcon#about to write, iclass 6, count 0 2006.239.07:59:49.68#ibcon#wrote, iclass 6, count 0 2006.239.07:59:49.68#ibcon#about to read 3, iclass 6, count 0 2006.239.07:59:49.71#ibcon#read 3, iclass 6, count 0 2006.239.07:59:49.71#ibcon#about to read 4, iclass 6, count 0 2006.239.07:59:49.71#ibcon#read 4, iclass 6, count 0 2006.239.07:59:49.71#ibcon#about to read 5, iclass 6, count 0 2006.239.07:59:49.71#ibcon#read 5, iclass 6, count 0 2006.239.07:59:49.71#ibcon#about to read 6, iclass 6, count 0 2006.239.07:59:49.71#ibcon#read 6, iclass 6, count 0 2006.239.07:59:49.71#ibcon#end of sib2, iclass 6, count 0 2006.239.07:59:49.71#ibcon#*after write, iclass 6, count 0 2006.239.07:59:49.71#ibcon#*before return 0, iclass 6, count 0 2006.239.07:59:49.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:49.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:49.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:59:49.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:59:49.71$vc4f8/valo=6,772.99 2006.239.07:59:49.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:59:49.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:59:49.71#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:49.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:49.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:49.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:49.71#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:59:49.71#ibcon#first serial, iclass 10, count 0 2006.239.07:59:49.71#ibcon#enter sib2, iclass 10, count 0 2006.239.07:59:49.71#ibcon#flushed, iclass 10, count 0 2006.239.07:59:49.71#ibcon#about to write, iclass 10, count 0 2006.239.07:59:49.71#ibcon#wrote, iclass 10, count 0 2006.239.07:59:49.71#ibcon#about to read 3, iclass 10, count 0 2006.239.07:59:49.73#ibcon#read 3, iclass 10, count 0 2006.239.07:59:49.73#ibcon#about to read 4, iclass 10, count 0 2006.239.07:59:49.73#ibcon#read 4, iclass 10, count 0 2006.239.07:59:49.73#ibcon#about to read 5, iclass 10, count 0 2006.239.07:59:49.73#ibcon#read 5, iclass 10, count 0 2006.239.07:59:49.73#ibcon#about to read 6, iclass 10, count 0 2006.239.07:59:49.73#ibcon#read 6, iclass 10, count 0 2006.239.07:59:49.73#ibcon#end of sib2, iclass 10, count 0 2006.239.07:59:49.73#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:59:49.73#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:59:49.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.07:59:49.73#ibcon#*before write, iclass 10, count 0 2006.239.07:59:49.73#ibcon#enter sib2, iclass 10, count 0 2006.239.07:59:49.73#ibcon#flushed, iclass 10, count 0 2006.239.07:59:49.73#ibcon#about to write, iclass 10, count 0 2006.239.07:59:49.73#ibcon#wrote, iclass 10, count 0 2006.239.07:59:49.73#ibcon#about to read 3, iclass 10, count 0 2006.239.07:59:49.77#ibcon#read 3, iclass 10, count 0 2006.239.07:59:49.77#ibcon#about to read 4, iclass 10, count 0 2006.239.07:59:49.77#ibcon#read 4, iclass 10, count 0 2006.239.07:59:49.77#ibcon#about to read 5, iclass 10, count 0 2006.239.07:59:49.77#ibcon#read 5, iclass 10, count 0 2006.239.07:59:49.77#ibcon#about to read 6, iclass 10, count 0 2006.239.07:59:49.77#ibcon#read 6, iclass 10, count 0 2006.239.07:59:49.77#ibcon#end of sib2, iclass 10, count 0 2006.239.07:59:49.77#ibcon#*after write, iclass 10, count 0 2006.239.07:59:49.77#ibcon#*before return 0, iclass 10, count 0 2006.239.07:59:49.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:49.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:49.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:59:49.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:59:49.77$vc4f8/va=6,7 2006.239.07:59:49.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.07:59:49.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.07:59:49.77#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:49.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:59:49.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:59:49.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:59:49.83#ibcon#enter wrdev, iclass 12, count 2 2006.239.07:59:49.83#ibcon#first serial, iclass 12, count 2 2006.239.07:59:49.83#ibcon#enter sib2, iclass 12, count 2 2006.239.07:59:49.83#ibcon#flushed, iclass 12, count 2 2006.239.07:59:49.83#ibcon#about to write, iclass 12, count 2 2006.239.07:59:49.83#ibcon#wrote, iclass 12, count 2 2006.239.07:59:49.83#ibcon#about to read 3, iclass 12, count 2 2006.239.07:59:49.85#ibcon#read 3, iclass 12, count 2 2006.239.07:59:49.85#ibcon#about to read 4, iclass 12, count 2 2006.239.07:59:49.85#ibcon#read 4, iclass 12, count 2 2006.239.07:59:49.85#ibcon#about to read 5, iclass 12, count 2 2006.239.07:59:49.85#ibcon#read 5, iclass 12, count 2 2006.239.07:59:49.85#ibcon#about to read 6, iclass 12, count 2 2006.239.07:59:49.85#ibcon#read 6, iclass 12, count 2 2006.239.07:59:49.85#ibcon#end of sib2, iclass 12, count 2 2006.239.07:59:49.85#ibcon#*mode == 0, iclass 12, count 2 2006.239.07:59:49.85#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.07:59:49.85#ibcon#[25=AT06-07\r\n] 2006.239.07:59:49.85#ibcon#*before write, iclass 12, count 2 2006.239.07:59:49.85#ibcon#enter sib2, iclass 12, count 2 2006.239.07:59:49.85#ibcon#flushed, iclass 12, count 2 2006.239.07:59:49.85#ibcon#about to write, iclass 12, count 2 2006.239.07:59:49.85#ibcon#wrote, iclass 12, count 2 2006.239.07:59:49.85#ibcon#about to read 3, iclass 12, count 2 2006.239.07:59:49.88#ibcon#read 3, iclass 12, count 2 2006.239.07:59:49.88#ibcon#about to read 4, iclass 12, count 2 2006.239.07:59:49.88#ibcon#read 4, iclass 12, count 2 2006.239.07:59:49.88#ibcon#about to read 5, iclass 12, count 2 2006.239.07:59:49.88#ibcon#read 5, iclass 12, count 2 2006.239.07:59:49.88#ibcon#about to read 6, iclass 12, count 2 2006.239.07:59:49.88#ibcon#read 6, iclass 12, count 2 2006.239.07:59:49.88#ibcon#end of sib2, iclass 12, count 2 2006.239.07:59:49.88#ibcon#*after write, iclass 12, count 2 2006.239.07:59:49.88#ibcon#*before return 0, iclass 12, count 2 2006.239.07:59:49.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:59:49.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.07:59:49.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.07:59:49.88#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:49.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:59:50.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:59:50.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:59:50.00#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:59:50.00#ibcon#first serial, iclass 12, count 0 2006.239.07:59:50.00#ibcon#enter sib2, iclass 12, count 0 2006.239.07:59:50.00#ibcon#flushed, iclass 12, count 0 2006.239.07:59:50.00#ibcon#about to write, iclass 12, count 0 2006.239.07:59:50.00#ibcon#wrote, iclass 12, count 0 2006.239.07:59:50.00#ibcon#about to read 3, iclass 12, count 0 2006.239.07:59:50.02#ibcon#read 3, iclass 12, count 0 2006.239.07:59:50.02#ibcon#about to read 4, iclass 12, count 0 2006.239.07:59:50.02#ibcon#read 4, iclass 12, count 0 2006.239.07:59:50.02#ibcon#about to read 5, iclass 12, count 0 2006.239.07:59:50.02#ibcon#read 5, iclass 12, count 0 2006.239.07:59:50.02#ibcon#about to read 6, iclass 12, count 0 2006.239.07:59:50.02#ibcon#read 6, iclass 12, count 0 2006.239.07:59:50.02#ibcon#end of sib2, iclass 12, count 0 2006.239.07:59:50.02#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:59:50.02#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:59:50.02#ibcon#[25=USB\r\n] 2006.239.07:59:50.02#ibcon#*before write, iclass 12, count 0 2006.239.07:59:50.02#ibcon#enter sib2, iclass 12, count 0 2006.239.07:59:50.02#ibcon#flushed, iclass 12, count 0 2006.239.07:59:50.02#ibcon#about to write, iclass 12, count 0 2006.239.07:59:50.02#ibcon#wrote, iclass 12, count 0 2006.239.07:59:50.02#ibcon#about to read 3, iclass 12, count 0 2006.239.07:59:50.05#ibcon#read 3, iclass 12, count 0 2006.239.07:59:50.05#ibcon#about to read 4, iclass 12, count 0 2006.239.07:59:50.05#ibcon#read 4, iclass 12, count 0 2006.239.07:59:50.05#ibcon#about to read 5, iclass 12, count 0 2006.239.07:59:50.05#ibcon#read 5, iclass 12, count 0 2006.239.07:59:50.05#ibcon#about to read 6, iclass 12, count 0 2006.239.07:59:50.05#ibcon#read 6, iclass 12, count 0 2006.239.07:59:50.05#ibcon#end of sib2, iclass 12, count 0 2006.239.07:59:50.05#ibcon#*after write, iclass 12, count 0 2006.239.07:59:50.05#ibcon#*before return 0, iclass 12, count 0 2006.239.07:59:50.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:59:50.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.07:59:50.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:59:50.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:59:50.05$vc4f8/valo=7,832.99 2006.239.07:59:50.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.07:59:50.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.07:59:50.05#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:50.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:59:50.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:59:50.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:59:50.05#ibcon#enter wrdev, iclass 14, count 0 2006.239.07:59:50.05#ibcon#first serial, iclass 14, count 0 2006.239.07:59:50.05#ibcon#enter sib2, iclass 14, count 0 2006.239.07:59:50.05#ibcon#flushed, iclass 14, count 0 2006.239.07:59:50.05#ibcon#about to write, iclass 14, count 0 2006.239.07:59:50.05#ibcon#wrote, iclass 14, count 0 2006.239.07:59:50.05#ibcon#about to read 3, iclass 14, count 0 2006.239.07:59:50.07#ibcon#read 3, iclass 14, count 0 2006.239.07:59:50.07#ibcon#about to read 4, iclass 14, count 0 2006.239.07:59:50.07#ibcon#read 4, iclass 14, count 0 2006.239.07:59:50.07#ibcon#about to read 5, iclass 14, count 0 2006.239.07:59:50.07#ibcon#read 5, iclass 14, count 0 2006.239.07:59:50.07#ibcon#about to read 6, iclass 14, count 0 2006.239.07:59:50.07#ibcon#read 6, iclass 14, count 0 2006.239.07:59:50.07#ibcon#end of sib2, iclass 14, count 0 2006.239.07:59:50.07#ibcon#*mode == 0, iclass 14, count 0 2006.239.07:59:50.07#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.07:59:50.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.07:59:50.07#ibcon#*before write, iclass 14, count 0 2006.239.07:59:50.07#ibcon#enter sib2, iclass 14, count 0 2006.239.07:59:50.07#ibcon#flushed, iclass 14, count 0 2006.239.07:59:50.07#ibcon#about to write, iclass 14, count 0 2006.239.07:59:50.07#ibcon#wrote, iclass 14, count 0 2006.239.07:59:50.07#ibcon#about to read 3, iclass 14, count 0 2006.239.07:59:50.11#ibcon#read 3, iclass 14, count 0 2006.239.07:59:50.11#ibcon#about to read 4, iclass 14, count 0 2006.239.07:59:50.11#ibcon#read 4, iclass 14, count 0 2006.239.07:59:50.11#ibcon#about to read 5, iclass 14, count 0 2006.239.07:59:50.11#ibcon#read 5, iclass 14, count 0 2006.239.07:59:50.11#ibcon#about to read 6, iclass 14, count 0 2006.239.07:59:50.11#ibcon#read 6, iclass 14, count 0 2006.239.07:59:50.11#ibcon#end of sib2, iclass 14, count 0 2006.239.07:59:50.11#ibcon#*after write, iclass 14, count 0 2006.239.07:59:50.11#ibcon#*before return 0, iclass 14, count 0 2006.239.07:59:50.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:59:50.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.07:59:50.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.07:59:50.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.07:59:50.11$vc4f8/va=7,7 2006.239.07:59:50.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.07:59:50.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.07:59:50.11#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:50.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:59:50.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:59:50.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:59:50.17#ibcon#enter wrdev, iclass 16, count 2 2006.239.07:59:50.17#ibcon#first serial, iclass 16, count 2 2006.239.07:59:50.17#ibcon#enter sib2, iclass 16, count 2 2006.239.07:59:50.17#ibcon#flushed, iclass 16, count 2 2006.239.07:59:50.17#ibcon#about to write, iclass 16, count 2 2006.239.07:59:50.17#ibcon#wrote, iclass 16, count 2 2006.239.07:59:50.17#ibcon#about to read 3, iclass 16, count 2 2006.239.07:59:50.19#ibcon#read 3, iclass 16, count 2 2006.239.07:59:50.19#ibcon#about to read 4, iclass 16, count 2 2006.239.07:59:50.19#ibcon#read 4, iclass 16, count 2 2006.239.07:59:50.19#ibcon#about to read 5, iclass 16, count 2 2006.239.07:59:50.19#ibcon#read 5, iclass 16, count 2 2006.239.07:59:50.19#ibcon#about to read 6, iclass 16, count 2 2006.239.07:59:50.19#ibcon#read 6, iclass 16, count 2 2006.239.07:59:50.19#ibcon#end of sib2, iclass 16, count 2 2006.239.07:59:50.19#ibcon#*mode == 0, iclass 16, count 2 2006.239.07:59:50.19#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.07:59:50.19#ibcon#[25=AT07-07\r\n] 2006.239.07:59:50.19#ibcon#*before write, iclass 16, count 2 2006.239.07:59:50.19#ibcon#enter sib2, iclass 16, count 2 2006.239.07:59:50.19#ibcon#flushed, iclass 16, count 2 2006.239.07:59:50.19#ibcon#about to write, iclass 16, count 2 2006.239.07:59:50.19#ibcon#wrote, iclass 16, count 2 2006.239.07:59:50.19#ibcon#about to read 3, iclass 16, count 2 2006.239.07:59:50.23#ibcon#read 3, iclass 16, count 2 2006.239.07:59:50.23#ibcon#about to read 4, iclass 16, count 2 2006.239.07:59:50.23#ibcon#read 4, iclass 16, count 2 2006.239.07:59:50.23#ibcon#about to read 5, iclass 16, count 2 2006.239.07:59:50.23#ibcon#read 5, iclass 16, count 2 2006.239.07:59:50.23#ibcon#about to read 6, iclass 16, count 2 2006.239.07:59:50.23#ibcon#read 6, iclass 16, count 2 2006.239.07:59:50.23#ibcon#end of sib2, iclass 16, count 2 2006.239.07:59:50.23#ibcon#*after write, iclass 16, count 2 2006.239.07:59:50.23#ibcon#*before return 0, iclass 16, count 2 2006.239.07:59:50.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:59:50.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.07:59:50.23#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.07:59:50.23#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:50.23#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:59:50.35#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:59:50.35#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:59:50.35#ibcon#enter wrdev, iclass 16, count 0 2006.239.07:59:50.35#ibcon#first serial, iclass 16, count 0 2006.239.07:59:50.35#ibcon#enter sib2, iclass 16, count 0 2006.239.07:59:50.35#ibcon#flushed, iclass 16, count 0 2006.239.07:59:50.35#ibcon#about to write, iclass 16, count 0 2006.239.07:59:50.35#ibcon#wrote, iclass 16, count 0 2006.239.07:59:50.35#ibcon#about to read 3, iclass 16, count 0 2006.239.07:59:50.37#ibcon#read 3, iclass 16, count 0 2006.239.07:59:50.37#ibcon#about to read 4, iclass 16, count 0 2006.239.07:59:50.37#ibcon#read 4, iclass 16, count 0 2006.239.07:59:50.37#ibcon#about to read 5, iclass 16, count 0 2006.239.07:59:50.37#ibcon#read 5, iclass 16, count 0 2006.239.07:59:50.37#ibcon#about to read 6, iclass 16, count 0 2006.239.07:59:50.37#ibcon#read 6, iclass 16, count 0 2006.239.07:59:50.37#ibcon#end of sib2, iclass 16, count 0 2006.239.07:59:50.37#ibcon#*mode == 0, iclass 16, count 0 2006.239.07:59:50.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.07:59:50.37#ibcon#[25=USB\r\n] 2006.239.07:59:50.37#ibcon#*before write, iclass 16, count 0 2006.239.07:59:50.37#ibcon#enter sib2, iclass 16, count 0 2006.239.07:59:50.37#ibcon#flushed, iclass 16, count 0 2006.239.07:59:50.37#ibcon#about to write, iclass 16, count 0 2006.239.07:59:50.37#ibcon#wrote, iclass 16, count 0 2006.239.07:59:50.37#ibcon#about to read 3, iclass 16, count 0 2006.239.07:59:50.40#ibcon#read 3, iclass 16, count 0 2006.239.07:59:50.40#ibcon#about to read 4, iclass 16, count 0 2006.239.07:59:50.40#ibcon#read 4, iclass 16, count 0 2006.239.07:59:50.40#ibcon#about to read 5, iclass 16, count 0 2006.239.07:59:50.40#ibcon#read 5, iclass 16, count 0 2006.239.07:59:50.40#ibcon#about to read 6, iclass 16, count 0 2006.239.07:59:50.40#ibcon#read 6, iclass 16, count 0 2006.239.07:59:50.40#ibcon#end of sib2, iclass 16, count 0 2006.239.07:59:50.40#ibcon#*after write, iclass 16, count 0 2006.239.07:59:50.40#ibcon#*before return 0, iclass 16, count 0 2006.239.07:59:50.40#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:59:50.40#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.07:59:50.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.07:59:50.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.07:59:50.40$vc4f8/valo=8,852.99 2006.239.07:59:50.40#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.07:59:50.40#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.07:59:50.40#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:50.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:59:50.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:59:50.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:59:50.40#ibcon#enter wrdev, iclass 18, count 0 2006.239.07:59:50.40#ibcon#first serial, iclass 18, count 0 2006.239.07:59:50.40#ibcon#enter sib2, iclass 18, count 0 2006.239.07:59:50.40#ibcon#flushed, iclass 18, count 0 2006.239.07:59:50.40#ibcon#about to write, iclass 18, count 0 2006.239.07:59:50.40#ibcon#wrote, iclass 18, count 0 2006.239.07:59:50.40#ibcon#about to read 3, iclass 18, count 0 2006.239.07:59:50.42#ibcon#read 3, iclass 18, count 0 2006.239.07:59:50.42#ibcon#about to read 4, iclass 18, count 0 2006.239.07:59:50.42#ibcon#read 4, iclass 18, count 0 2006.239.07:59:50.42#ibcon#about to read 5, iclass 18, count 0 2006.239.07:59:50.42#ibcon#read 5, iclass 18, count 0 2006.239.07:59:50.42#ibcon#about to read 6, iclass 18, count 0 2006.239.07:59:50.42#ibcon#read 6, iclass 18, count 0 2006.239.07:59:50.42#ibcon#end of sib2, iclass 18, count 0 2006.239.07:59:50.42#ibcon#*mode == 0, iclass 18, count 0 2006.239.07:59:50.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.07:59:50.42#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.07:59:50.42#ibcon#*before write, iclass 18, count 0 2006.239.07:59:50.42#ibcon#enter sib2, iclass 18, count 0 2006.239.07:59:50.42#ibcon#flushed, iclass 18, count 0 2006.239.07:59:50.42#ibcon#about to write, iclass 18, count 0 2006.239.07:59:50.42#ibcon#wrote, iclass 18, count 0 2006.239.07:59:50.42#ibcon#about to read 3, iclass 18, count 0 2006.239.07:59:50.46#ibcon#read 3, iclass 18, count 0 2006.239.07:59:50.46#ibcon#about to read 4, iclass 18, count 0 2006.239.07:59:50.46#ibcon#read 4, iclass 18, count 0 2006.239.07:59:50.46#ibcon#about to read 5, iclass 18, count 0 2006.239.07:59:50.46#ibcon#read 5, iclass 18, count 0 2006.239.07:59:50.46#ibcon#about to read 6, iclass 18, count 0 2006.239.07:59:50.46#ibcon#read 6, iclass 18, count 0 2006.239.07:59:50.46#ibcon#end of sib2, iclass 18, count 0 2006.239.07:59:50.46#ibcon#*after write, iclass 18, count 0 2006.239.07:59:50.46#ibcon#*before return 0, iclass 18, count 0 2006.239.07:59:50.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:59:50.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.07:59:50.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.07:59:50.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.07:59:50.46$vc4f8/va=8,7 2006.239.07:59:50.46#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.07:59:50.46#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.07:59:50.46#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:50.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:59:50.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:59:50.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:59:50.52#ibcon#enter wrdev, iclass 20, count 2 2006.239.07:59:50.52#ibcon#first serial, iclass 20, count 2 2006.239.07:59:50.52#ibcon#enter sib2, iclass 20, count 2 2006.239.07:59:50.52#ibcon#flushed, iclass 20, count 2 2006.239.07:59:50.52#ibcon#about to write, iclass 20, count 2 2006.239.07:59:50.52#ibcon#wrote, iclass 20, count 2 2006.239.07:59:50.52#ibcon#about to read 3, iclass 20, count 2 2006.239.07:59:50.54#ibcon#read 3, iclass 20, count 2 2006.239.07:59:50.54#ibcon#about to read 4, iclass 20, count 2 2006.239.07:59:50.54#ibcon#read 4, iclass 20, count 2 2006.239.07:59:50.54#ibcon#about to read 5, iclass 20, count 2 2006.239.07:59:50.54#ibcon#read 5, iclass 20, count 2 2006.239.07:59:50.54#ibcon#about to read 6, iclass 20, count 2 2006.239.07:59:50.54#ibcon#read 6, iclass 20, count 2 2006.239.07:59:50.54#ibcon#end of sib2, iclass 20, count 2 2006.239.07:59:50.54#ibcon#*mode == 0, iclass 20, count 2 2006.239.07:59:50.54#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.07:59:50.54#ibcon#[25=AT08-07\r\n] 2006.239.07:59:50.54#ibcon#*before write, iclass 20, count 2 2006.239.07:59:50.54#ibcon#enter sib2, iclass 20, count 2 2006.239.07:59:50.54#ibcon#flushed, iclass 20, count 2 2006.239.07:59:50.54#ibcon#about to write, iclass 20, count 2 2006.239.07:59:50.54#ibcon#wrote, iclass 20, count 2 2006.239.07:59:50.54#ibcon#about to read 3, iclass 20, count 2 2006.239.07:59:50.57#ibcon#read 3, iclass 20, count 2 2006.239.07:59:50.57#ibcon#about to read 4, iclass 20, count 2 2006.239.07:59:50.57#ibcon#read 4, iclass 20, count 2 2006.239.07:59:50.57#ibcon#about to read 5, iclass 20, count 2 2006.239.07:59:50.57#ibcon#read 5, iclass 20, count 2 2006.239.07:59:50.57#ibcon#about to read 6, iclass 20, count 2 2006.239.07:59:50.57#ibcon#read 6, iclass 20, count 2 2006.239.07:59:50.57#ibcon#end of sib2, iclass 20, count 2 2006.239.07:59:50.57#ibcon#*after write, iclass 20, count 2 2006.239.07:59:50.57#ibcon#*before return 0, iclass 20, count 2 2006.239.07:59:50.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:59:50.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.07:59:50.57#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.07:59:50.57#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:50.57#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:59:50.69#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:59:50.69#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:59:50.69#ibcon#enter wrdev, iclass 20, count 0 2006.239.07:59:50.69#ibcon#first serial, iclass 20, count 0 2006.239.07:59:50.69#ibcon#enter sib2, iclass 20, count 0 2006.239.07:59:50.69#ibcon#flushed, iclass 20, count 0 2006.239.07:59:50.69#ibcon#about to write, iclass 20, count 0 2006.239.07:59:50.69#ibcon#wrote, iclass 20, count 0 2006.239.07:59:50.69#ibcon#about to read 3, iclass 20, count 0 2006.239.07:59:50.71#ibcon#read 3, iclass 20, count 0 2006.239.07:59:50.71#ibcon#about to read 4, iclass 20, count 0 2006.239.07:59:50.71#ibcon#read 4, iclass 20, count 0 2006.239.07:59:50.71#ibcon#about to read 5, iclass 20, count 0 2006.239.07:59:50.71#ibcon#read 5, iclass 20, count 0 2006.239.07:59:50.71#ibcon#about to read 6, iclass 20, count 0 2006.239.07:59:50.71#ibcon#read 6, iclass 20, count 0 2006.239.07:59:50.71#ibcon#end of sib2, iclass 20, count 0 2006.239.07:59:50.71#ibcon#*mode == 0, iclass 20, count 0 2006.239.07:59:50.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.07:59:50.71#ibcon#[25=USB\r\n] 2006.239.07:59:50.71#ibcon#*before write, iclass 20, count 0 2006.239.07:59:50.71#ibcon#enter sib2, iclass 20, count 0 2006.239.07:59:50.71#ibcon#flushed, iclass 20, count 0 2006.239.07:59:50.71#ibcon#about to write, iclass 20, count 0 2006.239.07:59:50.71#ibcon#wrote, iclass 20, count 0 2006.239.07:59:50.71#ibcon#about to read 3, iclass 20, count 0 2006.239.07:59:50.74#ibcon#read 3, iclass 20, count 0 2006.239.07:59:50.74#ibcon#about to read 4, iclass 20, count 0 2006.239.07:59:50.74#ibcon#read 4, iclass 20, count 0 2006.239.07:59:50.74#ibcon#about to read 5, iclass 20, count 0 2006.239.07:59:50.74#ibcon#read 5, iclass 20, count 0 2006.239.07:59:50.74#ibcon#about to read 6, iclass 20, count 0 2006.239.07:59:50.74#ibcon#read 6, iclass 20, count 0 2006.239.07:59:50.74#ibcon#end of sib2, iclass 20, count 0 2006.239.07:59:50.74#ibcon#*after write, iclass 20, count 0 2006.239.07:59:50.74#ibcon#*before return 0, iclass 20, count 0 2006.239.07:59:50.74#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:59:50.74#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.07:59:50.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.07:59:50.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.07:59:50.74$vc4f8/vblo=1,632.99 2006.239.07:59:50.74#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.07:59:50.74#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.07:59:50.74#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:50.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:59:50.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:59:50.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:59:50.74#ibcon#enter wrdev, iclass 22, count 0 2006.239.07:59:50.74#ibcon#first serial, iclass 22, count 0 2006.239.07:59:50.74#ibcon#enter sib2, iclass 22, count 0 2006.239.07:59:50.74#ibcon#flushed, iclass 22, count 0 2006.239.07:59:50.74#ibcon#about to write, iclass 22, count 0 2006.239.07:59:50.74#ibcon#wrote, iclass 22, count 0 2006.239.07:59:50.74#ibcon#about to read 3, iclass 22, count 0 2006.239.07:59:50.76#ibcon#read 3, iclass 22, count 0 2006.239.07:59:50.76#ibcon#about to read 4, iclass 22, count 0 2006.239.07:59:50.76#ibcon#read 4, iclass 22, count 0 2006.239.07:59:50.76#ibcon#about to read 5, iclass 22, count 0 2006.239.07:59:50.76#ibcon#read 5, iclass 22, count 0 2006.239.07:59:50.76#ibcon#about to read 6, iclass 22, count 0 2006.239.07:59:50.76#ibcon#read 6, iclass 22, count 0 2006.239.07:59:50.76#ibcon#end of sib2, iclass 22, count 0 2006.239.07:59:50.76#ibcon#*mode == 0, iclass 22, count 0 2006.239.07:59:50.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.07:59:50.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.07:59:50.76#ibcon#*before write, iclass 22, count 0 2006.239.07:59:50.76#ibcon#enter sib2, iclass 22, count 0 2006.239.07:59:50.76#ibcon#flushed, iclass 22, count 0 2006.239.07:59:50.76#ibcon#about to write, iclass 22, count 0 2006.239.07:59:50.76#ibcon#wrote, iclass 22, count 0 2006.239.07:59:50.76#ibcon#about to read 3, iclass 22, count 0 2006.239.07:59:50.80#ibcon#read 3, iclass 22, count 0 2006.239.07:59:50.80#ibcon#about to read 4, iclass 22, count 0 2006.239.07:59:50.80#ibcon#read 4, iclass 22, count 0 2006.239.07:59:50.80#ibcon#about to read 5, iclass 22, count 0 2006.239.07:59:50.80#ibcon#read 5, iclass 22, count 0 2006.239.07:59:50.80#ibcon#about to read 6, iclass 22, count 0 2006.239.07:59:50.80#ibcon#read 6, iclass 22, count 0 2006.239.07:59:50.80#ibcon#end of sib2, iclass 22, count 0 2006.239.07:59:50.80#ibcon#*after write, iclass 22, count 0 2006.239.07:59:50.80#ibcon#*before return 0, iclass 22, count 0 2006.239.07:59:50.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:59:50.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.07:59:50.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.07:59:50.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.07:59:50.80$vc4f8/vb=1,4 2006.239.07:59:50.80#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.07:59:50.80#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.07:59:50.80#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:50.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:59:50.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:59:50.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:59:50.80#ibcon#enter wrdev, iclass 24, count 2 2006.239.07:59:50.80#ibcon#first serial, iclass 24, count 2 2006.239.07:59:50.80#ibcon#enter sib2, iclass 24, count 2 2006.239.07:59:50.80#ibcon#flushed, iclass 24, count 2 2006.239.07:59:50.80#ibcon#about to write, iclass 24, count 2 2006.239.07:59:50.80#ibcon#wrote, iclass 24, count 2 2006.239.07:59:50.80#ibcon#about to read 3, iclass 24, count 2 2006.239.07:59:50.82#ibcon#read 3, iclass 24, count 2 2006.239.07:59:50.82#ibcon#about to read 4, iclass 24, count 2 2006.239.07:59:50.82#ibcon#read 4, iclass 24, count 2 2006.239.07:59:50.82#ibcon#about to read 5, iclass 24, count 2 2006.239.07:59:50.82#ibcon#read 5, iclass 24, count 2 2006.239.07:59:50.82#ibcon#about to read 6, iclass 24, count 2 2006.239.07:59:50.82#ibcon#read 6, iclass 24, count 2 2006.239.07:59:50.82#ibcon#end of sib2, iclass 24, count 2 2006.239.07:59:50.82#ibcon#*mode == 0, iclass 24, count 2 2006.239.07:59:50.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.07:59:50.82#ibcon#[27=AT01-04\r\n] 2006.239.07:59:50.82#ibcon#*before write, iclass 24, count 2 2006.239.07:59:50.82#ibcon#enter sib2, iclass 24, count 2 2006.239.07:59:50.82#ibcon#flushed, iclass 24, count 2 2006.239.07:59:50.82#ibcon#about to write, iclass 24, count 2 2006.239.07:59:50.82#ibcon#wrote, iclass 24, count 2 2006.239.07:59:50.82#ibcon#about to read 3, iclass 24, count 2 2006.239.07:59:50.85#ibcon#read 3, iclass 24, count 2 2006.239.07:59:50.85#ibcon#about to read 4, iclass 24, count 2 2006.239.07:59:50.85#ibcon#read 4, iclass 24, count 2 2006.239.07:59:50.85#ibcon#about to read 5, iclass 24, count 2 2006.239.07:59:50.85#ibcon#read 5, iclass 24, count 2 2006.239.07:59:50.85#ibcon#about to read 6, iclass 24, count 2 2006.239.07:59:50.85#ibcon#read 6, iclass 24, count 2 2006.239.07:59:50.85#ibcon#end of sib2, iclass 24, count 2 2006.239.07:59:50.85#ibcon#*after write, iclass 24, count 2 2006.239.07:59:50.85#ibcon#*before return 0, iclass 24, count 2 2006.239.07:59:50.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:59:50.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.07:59:50.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.07:59:50.85#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:50.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:59:50.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:59:50.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:59:50.97#ibcon#enter wrdev, iclass 24, count 0 2006.239.07:59:50.97#ibcon#first serial, iclass 24, count 0 2006.239.07:59:50.97#ibcon#enter sib2, iclass 24, count 0 2006.239.07:59:50.97#ibcon#flushed, iclass 24, count 0 2006.239.07:59:50.97#ibcon#about to write, iclass 24, count 0 2006.239.07:59:50.97#ibcon#wrote, iclass 24, count 0 2006.239.07:59:50.97#ibcon#about to read 3, iclass 24, count 0 2006.239.07:59:50.99#ibcon#read 3, iclass 24, count 0 2006.239.07:59:50.99#ibcon#about to read 4, iclass 24, count 0 2006.239.07:59:50.99#ibcon#read 4, iclass 24, count 0 2006.239.07:59:50.99#ibcon#about to read 5, iclass 24, count 0 2006.239.07:59:50.99#ibcon#read 5, iclass 24, count 0 2006.239.07:59:50.99#ibcon#about to read 6, iclass 24, count 0 2006.239.07:59:50.99#ibcon#read 6, iclass 24, count 0 2006.239.07:59:50.99#ibcon#end of sib2, iclass 24, count 0 2006.239.07:59:50.99#ibcon#*mode == 0, iclass 24, count 0 2006.239.07:59:50.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.07:59:50.99#ibcon#[27=USB\r\n] 2006.239.07:59:50.99#ibcon#*before write, iclass 24, count 0 2006.239.07:59:50.99#ibcon#enter sib2, iclass 24, count 0 2006.239.07:59:50.99#ibcon#flushed, iclass 24, count 0 2006.239.07:59:50.99#ibcon#about to write, iclass 24, count 0 2006.239.07:59:50.99#ibcon#wrote, iclass 24, count 0 2006.239.07:59:50.99#ibcon#about to read 3, iclass 24, count 0 2006.239.07:59:51.02#ibcon#read 3, iclass 24, count 0 2006.239.07:59:51.02#ibcon#about to read 4, iclass 24, count 0 2006.239.07:59:51.02#ibcon#read 4, iclass 24, count 0 2006.239.07:59:51.02#ibcon#about to read 5, iclass 24, count 0 2006.239.07:59:51.02#ibcon#read 5, iclass 24, count 0 2006.239.07:59:51.02#ibcon#about to read 6, iclass 24, count 0 2006.239.07:59:51.02#ibcon#read 6, iclass 24, count 0 2006.239.07:59:51.02#ibcon#end of sib2, iclass 24, count 0 2006.239.07:59:51.02#ibcon#*after write, iclass 24, count 0 2006.239.07:59:51.02#ibcon#*before return 0, iclass 24, count 0 2006.239.07:59:51.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:59:51.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.07:59:51.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.07:59:51.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.07:59:51.02$vc4f8/vblo=2,640.99 2006.239.07:59:51.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.07:59:51.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.07:59:51.02#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:51.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:51.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:51.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:51.02#ibcon#enter wrdev, iclass 26, count 0 2006.239.07:59:51.02#ibcon#first serial, iclass 26, count 0 2006.239.07:59:51.02#ibcon#enter sib2, iclass 26, count 0 2006.239.07:59:51.02#ibcon#flushed, iclass 26, count 0 2006.239.07:59:51.02#ibcon#about to write, iclass 26, count 0 2006.239.07:59:51.02#ibcon#wrote, iclass 26, count 0 2006.239.07:59:51.02#ibcon#about to read 3, iclass 26, count 0 2006.239.07:59:51.04#ibcon#read 3, iclass 26, count 0 2006.239.07:59:51.04#ibcon#about to read 4, iclass 26, count 0 2006.239.07:59:51.04#ibcon#read 4, iclass 26, count 0 2006.239.07:59:51.04#ibcon#about to read 5, iclass 26, count 0 2006.239.07:59:51.04#ibcon#read 5, iclass 26, count 0 2006.239.07:59:51.04#ibcon#about to read 6, iclass 26, count 0 2006.239.07:59:51.04#ibcon#read 6, iclass 26, count 0 2006.239.07:59:51.04#ibcon#end of sib2, iclass 26, count 0 2006.239.07:59:51.04#ibcon#*mode == 0, iclass 26, count 0 2006.239.07:59:51.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.07:59:51.04#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.07:59:51.04#ibcon#*before write, iclass 26, count 0 2006.239.07:59:51.04#ibcon#enter sib2, iclass 26, count 0 2006.239.07:59:51.04#ibcon#flushed, iclass 26, count 0 2006.239.07:59:51.04#ibcon#about to write, iclass 26, count 0 2006.239.07:59:51.04#ibcon#wrote, iclass 26, count 0 2006.239.07:59:51.04#ibcon#about to read 3, iclass 26, count 0 2006.239.07:59:51.08#ibcon#read 3, iclass 26, count 0 2006.239.07:59:51.08#ibcon#about to read 4, iclass 26, count 0 2006.239.07:59:51.08#ibcon#read 4, iclass 26, count 0 2006.239.07:59:51.08#ibcon#about to read 5, iclass 26, count 0 2006.239.07:59:51.08#ibcon#read 5, iclass 26, count 0 2006.239.07:59:51.08#ibcon#about to read 6, iclass 26, count 0 2006.239.07:59:51.08#ibcon#read 6, iclass 26, count 0 2006.239.07:59:51.08#ibcon#end of sib2, iclass 26, count 0 2006.239.07:59:51.08#ibcon#*after write, iclass 26, count 0 2006.239.07:59:51.08#ibcon#*before return 0, iclass 26, count 0 2006.239.07:59:51.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:51.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.07:59:51.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.07:59:51.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.07:59:51.08$vc4f8/vb=2,4 2006.239.07:59:51.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.07:59:51.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.07:59:51.08#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:51.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:51.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:51.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:51.14#ibcon#enter wrdev, iclass 28, count 2 2006.239.07:59:51.14#ibcon#first serial, iclass 28, count 2 2006.239.07:59:51.14#ibcon#enter sib2, iclass 28, count 2 2006.239.07:59:51.14#ibcon#flushed, iclass 28, count 2 2006.239.07:59:51.14#ibcon#about to write, iclass 28, count 2 2006.239.07:59:51.14#ibcon#wrote, iclass 28, count 2 2006.239.07:59:51.14#ibcon#about to read 3, iclass 28, count 2 2006.239.07:59:51.16#ibcon#read 3, iclass 28, count 2 2006.239.07:59:51.16#ibcon#about to read 4, iclass 28, count 2 2006.239.07:59:51.16#ibcon#read 4, iclass 28, count 2 2006.239.07:59:51.16#ibcon#about to read 5, iclass 28, count 2 2006.239.07:59:51.16#ibcon#read 5, iclass 28, count 2 2006.239.07:59:51.16#ibcon#about to read 6, iclass 28, count 2 2006.239.07:59:51.16#ibcon#read 6, iclass 28, count 2 2006.239.07:59:51.16#ibcon#end of sib2, iclass 28, count 2 2006.239.07:59:51.16#ibcon#*mode == 0, iclass 28, count 2 2006.239.07:59:51.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.07:59:51.16#ibcon#[27=AT02-04\r\n] 2006.239.07:59:51.16#ibcon#*before write, iclass 28, count 2 2006.239.07:59:51.16#ibcon#enter sib2, iclass 28, count 2 2006.239.07:59:51.16#ibcon#flushed, iclass 28, count 2 2006.239.07:59:51.16#ibcon#about to write, iclass 28, count 2 2006.239.07:59:51.16#ibcon#wrote, iclass 28, count 2 2006.239.07:59:51.16#ibcon#about to read 3, iclass 28, count 2 2006.239.07:59:51.19#ibcon#read 3, iclass 28, count 2 2006.239.07:59:51.19#ibcon#about to read 4, iclass 28, count 2 2006.239.07:59:51.19#ibcon#read 4, iclass 28, count 2 2006.239.07:59:51.19#ibcon#about to read 5, iclass 28, count 2 2006.239.07:59:51.19#ibcon#read 5, iclass 28, count 2 2006.239.07:59:51.19#ibcon#about to read 6, iclass 28, count 2 2006.239.07:59:51.19#ibcon#read 6, iclass 28, count 2 2006.239.07:59:51.19#ibcon#end of sib2, iclass 28, count 2 2006.239.07:59:51.19#ibcon#*after write, iclass 28, count 2 2006.239.07:59:51.19#ibcon#*before return 0, iclass 28, count 2 2006.239.07:59:51.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:51.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.07:59:51.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.07:59:51.19#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:51.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:51.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:51.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:51.31#ibcon#enter wrdev, iclass 28, count 0 2006.239.07:59:51.31#ibcon#first serial, iclass 28, count 0 2006.239.07:59:51.31#ibcon#enter sib2, iclass 28, count 0 2006.239.07:59:51.31#ibcon#flushed, iclass 28, count 0 2006.239.07:59:51.31#ibcon#about to write, iclass 28, count 0 2006.239.07:59:51.31#ibcon#wrote, iclass 28, count 0 2006.239.07:59:51.31#ibcon#about to read 3, iclass 28, count 0 2006.239.07:59:51.33#ibcon#read 3, iclass 28, count 0 2006.239.07:59:51.33#ibcon#about to read 4, iclass 28, count 0 2006.239.07:59:51.33#ibcon#read 4, iclass 28, count 0 2006.239.07:59:51.33#ibcon#about to read 5, iclass 28, count 0 2006.239.07:59:51.33#ibcon#read 5, iclass 28, count 0 2006.239.07:59:51.33#ibcon#about to read 6, iclass 28, count 0 2006.239.07:59:51.33#ibcon#read 6, iclass 28, count 0 2006.239.07:59:51.33#ibcon#end of sib2, iclass 28, count 0 2006.239.07:59:51.33#ibcon#*mode == 0, iclass 28, count 0 2006.239.07:59:51.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.07:59:51.33#ibcon#[27=USB\r\n] 2006.239.07:59:51.33#ibcon#*before write, iclass 28, count 0 2006.239.07:59:51.33#ibcon#enter sib2, iclass 28, count 0 2006.239.07:59:51.33#ibcon#flushed, iclass 28, count 0 2006.239.07:59:51.33#ibcon#about to write, iclass 28, count 0 2006.239.07:59:51.33#ibcon#wrote, iclass 28, count 0 2006.239.07:59:51.33#ibcon#about to read 3, iclass 28, count 0 2006.239.07:59:51.36#ibcon#read 3, iclass 28, count 0 2006.239.07:59:51.36#ibcon#about to read 4, iclass 28, count 0 2006.239.07:59:51.36#ibcon#read 4, iclass 28, count 0 2006.239.07:59:51.36#ibcon#about to read 5, iclass 28, count 0 2006.239.07:59:51.36#ibcon#read 5, iclass 28, count 0 2006.239.07:59:51.36#ibcon#about to read 6, iclass 28, count 0 2006.239.07:59:51.36#ibcon#read 6, iclass 28, count 0 2006.239.07:59:51.36#ibcon#end of sib2, iclass 28, count 0 2006.239.07:59:51.36#ibcon#*after write, iclass 28, count 0 2006.239.07:59:51.36#ibcon#*before return 0, iclass 28, count 0 2006.239.07:59:51.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:51.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.07:59:51.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.07:59:51.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.07:59:51.36$vc4f8/vblo=3,656.99 2006.239.07:59:51.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.07:59:51.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.07:59:51.36#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:51.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:51.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:51.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:51.36#ibcon#enter wrdev, iclass 30, count 0 2006.239.07:59:51.36#ibcon#first serial, iclass 30, count 0 2006.239.07:59:51.36#ibcon#enter sib2, iclass 30, count 0 2006.239.07:59:51.36#ibcon#flushed, iclass 30, count 0 2006.239.07:59:51.36#ibcon#about to write, iclass 30, count 0 2006.239.07:59:51.36#ibcon#wrote, iclass 30, count 0 2006.239.07:59:51.36#ibcon#about to read 3, iclass 30, count 0 2006.239.07:59:51.38#ibcon#read 3, iclass 30, count 0 2006.239.07:59:51.38#ibcon#about to read 4, iclass 30, count 0 2006.239.07:59:51.38#ibcon#read 4, iclass 30, count 0 2006.239.07:59:51.38#ibcon#about to read 5, iclass 30, count 0 2006.239.07:59:51.38#ibcon#read 5, iclass 30, count 0 2006.239.07:59:51.38#ibcon#about to read 6, iclass 30, count 0 2006.239.07:59:51.38#ibcon#read 6, iclass 30, count 0 2006.239.07:59:51.38#ibcon#end of sib2, iclass 30, count 0 2006.239.07:59:51.38#ibcon#*mode == 0, iclass 30, count 0 2006.239.07:59:51.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.07:59:51.38#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.07:59:51.38#ibcon#*before write, iclass 30, count 0 2006.239.07:59:51.38#ibcon#enter sib2, iclass 30, count 0 2006.239.07:59:51.38#ibcon#flushed, iclass 30, count 0 2006.239.07:59:51.38#ibcon#about to write, iclass 30, count 0 2006.239.07:59:51.38#ibcon#wrote, iclass 30, count 0 2006.239.07:59:51.38#ibcon#about to read 3, iclass 30, count 0 2006.239.07:59:51.42#ibcon#read 3, iclass 30, count 0 2006.239.07:59:51.42#ibcon#about to read 4, iclass 30, count 0 2006.239.07:59:51.42#ibcon#read 4, iclass 30, count 0 2006.239.07:59:51.42#ibcon#about to read 5, iclass 30, count 0 2006.239.07:59:51.42#ibcon#read 5, iclass 30, count 0 2006.239.07:59:51.42#ibcon#about to read 6, iclass 30, count 0 2006.239.07:59:51.42#ibcon#read 6, iclass 30, count 0 2006.239.07:59:51.42#ibcon#end of sib2, iclass 30, count 0 2006.239.07:59:51.42#ibcon#*after write, iclass 30, count 0 2006.239.07:59:51.42#ibcon#*before return 0, iclass 30, count 0 2006.239.07:59:51.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:51.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.07:59:51.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.07:59:51.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.07:59:51.42$vc4f8/vb=3,4 2006.239.07:59:51.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.07:59:51.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.07:59:51.42#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:51.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:51.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:51.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:51.48#ibcon#enter wrdev, iclass 32, count 2 2006.239.07:59:51.48#ibcon#first serial, iclass 32, count 2 2006.239.07:59:51.48#ibcon#enter sib2, iclass 32, count 2 2006.239.07:59:51.48#ibcon#flushed, iclass 32, count 2 2006.239.07:59:51.48#ibcon#about to write, iclass 32, count 2 2006.239.07:59:51.48#ibcon#wrote, iclass 32, count 2 2006.239.07:59:51.48#ibcon#about to read 3, iclass 32, count 2 2006.239.07:59:51.50#ibcon#read 3, iclass 32, count 2 2006.239.07:59:51.50#ibcon#about to read 4, iclass 32, count 2 2006.239.07:59:51.50#ibcon#read 4, iclass 32, count 2 2006.239.07:59:51.50#ibcon#about to read 5, iclass 32, count 2 2006.239.07:59:51.50#ibcon#read 5, iclass 32, count 2 2006.239.07:59:51.50#ibcon#about to read 6, iclass 32, count 2 2006.239.07:59:51.50#ibcon#read 6, iclass 32, count 2 2006.239.07:59:51.50#ibcon#end of sib2, iclass 32, count 2 2006.239.07:59:51.50#ibcon#*mode == 0, iclass 32, count 2 2006.239.07:59:51.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.07:59:51.50#ibcon#[27=AT03-04\r\n] 2006.239.07:59:51.50#ibcon#*before write, iclass 32, count 2 2006.239.07:59:51.50#ibcon#enter sib2, iclass 32, count 2 2006.239.07:59:51.50#ibcon#flushed, iclass 32, count 2 2006.239.07:59:51.50#ibcon#about to write, iclass 32, count 2 2006.239.07:59:51.50#ibcon#wrote, iclass 32, count 2 2006.239.07:59:51.50#ibcon#about to read 3, iclass 32, count 2 2006.239.07:59:51.53#ibcon#read 3, iclass 32, count 2 2006.239.07:59:51.53#ibcon#about to read 4, iclass 32, count 2 2006.239.07:59:51.53#ibcon#read 4, iclass 32, count 2 2006.239.07:59:51.53#ibcon#about to read 5, iclass 32, count 2 2006.239.07:59:51.53#ibcon#read 5, iclass 32, count 2 2006.239.07:59:51.53#ibcon#about to read 6, iclass 32, count 2 2006.239.07:59:51.53#ibcon#read 6, iclass 32, count 2 2006.239.07:59:51.53#ibcon#end of sib2, iclass 32, count 2 2006.239.07:59:51.53#ibcon#*after write, iclass 32, count 2 2006.239.07:59:51.53#ibcon#*before return 0, iclass 32, count 2 2006.239.07:59:51.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:51.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.07:59:51.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.07:59:51.53#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:51.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:51.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:51.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:51.65#ibcon#enter wrdev, iclass 32, count 0 2006.239.07:59:51.65#ibcon#first serial, iclass 32, count 0 2006.239.07:59:51.65#ibcon#enter sib2, iclass 32, count 0 2006.239.07:59:51.65#ibcon#flushed, iclass 32, count 0 2006.239.07:59:51.65#ibcon#about to write, iclass 32, count 0 2006.239.07:59:51.65#ibcon#wrote, iclass 32, count 0 2006.239.07:59:51.65#ibcon#about to read 3, iclass 32, count 0 2006.239.07:59:51.67#ibcon#read 3, iclass 32, count 0 2006.239.07:59:51.67#ibcon#about to read 4, iclass 32, count 0 2006.239.07:59:51.67#ibcon#read 4, iclass 32, count 0 2006.239.07:59:51.67#ibcon#about to read 5, iclass 32, count 0 2006.239.07:59:51.67#ibcon#read 5, iclass 32, count 0 2006.239.07:59:51.67#ibcon#about to read 6, iclass 32, count 0 2006.239.07:59:51.67#ibcon#read 6, iclass 32, count 0 2006.239.07:59:51.67#ibcon#end of sib2, iclass 32, count 0 2006.239.07:59:51.67#ibcon#*mode == 0, iclass 32, count 0 2006.239.07:59:51.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.07:59:51.67#ibcon#[27=USB\r\n] 2006.239.07:59:51.67#ibcon#*before write, iclass 32, count 0 2006.239.07:59:51.67#ibcon#enter sib2, iclass 32, count 0 2006.239.07:59:51.67#ibcon#flushed, iclass 32, count 0 2006.239.07:59:51.67#ibcon#about to write, iclass 32, count 0 2006.239.07:59:51.67#ibcon#wrote, iclass 32, count 0 2006.239.07:59:51.67#ibcon#about to read 3, iclass 32, count 0 2006.239.07:59:51.70#ibcon#read 3, iclass 32, count 0 2006.239.07:59:51.70#ibcon#about to read 4, iclass 32, count 0 2006.239.07:59:51.70#ibcon#read 4, iclass 32, count 0 2006.239.07:59:51.70#ibcon#about to read 5, iclass 32, count 0 2006.239.07:59:51.70#ibcon#read 5, iclass 32, count 0 2006.239.07:59:51.70#ibcon#about to read 6, iclass 32, count 0 2006.239.07:59:51.70#ibcon#read 6, iclass 32, count 0 2006.239.07:59:51.70#ibcon#end of sib2, iclass 32, count 0 2006.239.07:59:51.70#ibcon#*after write, iclass 32, count 0 2006.239.07:59:51.70#ibcon#*before return 0, iclass 32, count 0 2006.239.07:59:51.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:51.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.07:59:51.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.07:59:51.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.07:59:51.70$vc4f8/vblo=4,712.99 2006.239.07:59:51.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.07:59:51.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.07:59:51.70#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:51.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:51.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:51.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:51.70#ibcon#enter wrdev, iclass 34, count 0 2006.239.07:59:51.70#ibcon#first serial, iclass 34, count 0 2006.239.07:59:51.70#ibcon#enter sib2, iclass 34, count 0 2006.239.07:59:51.70#ibcon#flushed, iclass 34, count 0 2006.239.07:59:51.70#ibcon#about to write, iclass 34, count 0 2006.239.07:59:51.70#ibcon#wrote, iclass 34, count 0 2006.239.07:59:51.70#ibcon#about to read 3, iclass 34, count 0 2006.239.07:59:51.72#ibcon#read 3, iclass 34, count 0 2006.239.07:59:51.72#ibcon#about to read 4, iclass 34, count 0 2006.239.07:59:51.72#ibcon#read 4, iclass 34, count 0 2006.239.07:59:51.72#ibcon#about to read 5, iclass 34, count 0 2006.239.07:59:51.72#ibcon#read 5, iclass 34, count 0 2006.239.07:59:51.72#ibcon#about to read 6, iclass 34, count 0 2006.239.07:59:51.72#ibcon#read 6, iclass 34, count 0 2006.239.07:59:51.72#ibcon#end of sib2, iclass 34, count 0 2006.239.07:59:51.72#ibcon#*mode == 0, iclass 34, count 0 2006.239.07:59:51.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.07:59:51.72#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.07:59:51.72#ibcon#*before write, iclass 34, count 0 2006.239.07:59:51.72#ibcon#enter sib2, iclass 34, count 0 2006.239.07:59:51.72#ibcon#flushed, iclass 34, count 0 2006.239.07:59:51.72#ibcon#about to write, iclass 34, count 0 2006.239.07:59:51.72#ibcon#wrote, iclass 34, count 0 2006.239.07:59:51.72#ibcon#about to read 3, iclass 34, count 0 2006.239.07:59:51.76#ibcon#read 3, iclass 34, count 0 2006.239.07:59:51.76#ibcon#about to read 4, iclass 34, count 0 2006.239.07:59:51.76#ibcon#read 4, iclass 34, count 0 2006.239.07:59:51.76#ibcon#about to read 5, iclass 34, count 0 2006.239.07:59:51.76#ibcon#read 5, iclass 34, count 0 2006.239.07:59:51.76#ibcon#about to read 6, iclass 34, count 0 2006.239.07:59:51.76#ibcon#read 6, iclass 34, count 0 2006.239.07:59:51.76#ibcon#end of sib2, iclass 34, count 0 2006.239.07:59:51.76#ibcon#*after write, iclass 34, count 0 2006.239.07:59:51.76#ibcon#*before return 0, iclass 34, count 0 2006.239.07:59:51.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:51.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.07:59:51.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.07:59:51.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.07:59:51.76$vc4f8/vb=4,4 2006.239.07:59:51.76#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.07:59:51.76#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.07:59:51.76#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:51.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:51.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:51.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:51.82#ibcon#enter wrdev, iclass 36, count 2 2006.239.07:59:51.82#ibcon#first serial, iclass 36, count 2 2006.239.07:59:51.82#ibcon#enter sib2, iclass 36, count 2 2006.239.07:59:51.82#ibcon#flushed, iclass 36, count 2 2006.239.07:59:51.82#ibcon#about to write, iclass 36, count 2 2006.239.07:59:51.82#ibcon#wrote, iclass 36, count 2 2006.239.07:59:51.82#ibcon#about to read 3, iclass 36, count 2 2006.239.07:59:51.84#ibcon#read 3, iclass 36, count 2 2006.239.07:59:51.84#ibcon#about to read 4, iclass 36, count 2 2006.239.07:59:51.84#ibcon#read 4, iclass 36, count 2 2006.239.07:59:51.84#ibcon#about to read 5, iclass 36, count 2 2006.239.07:59:51.84#ibcon#read 5, iclass 36, count 2 2006.239.07:59:51.84#ibcon#about to read 6, iclass 36, count 2 2006.239.07:59:51.84#ibcon#read 6, iclass 36, count 2 2006.239.07:59:51.84#ibcon#end of sib2, iclass 36, count 2 2006.239.07:59:51.84#ibcon#*mode == 0, iclass 36, count 2 2006.239.07:59:51.84#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.07:59:51.84#ibcon#[27=AT04-04\r\n] 2006.239.07:59:51.84#ibcon#*before write, iclass 36, count 2 2006.239.07:59:51.84#ibcon#enter sib2, iclass 36, count 2 2006.239.07:59:51.84#ibcon#flushed, iclass 36, count 2 2006.239.07:59:51.84#ibcon#about to write, iclass 36, count 2 2006.239.07:59:51.84#ibcon#wrote, iclass 36, count 2 2006.239.07:59:51.84#ibcon#about to read 3, iclass 36, count 2 2006.239.07:59:51.87#ibcon#read 3, iclass 36, count 2 2006.239.07:59:51.87#ibcon#about to read 4, iclass 36, count 2 2006.239.07:59:51.87#ibcon#read 4, iclass 36, count 2 2006.239.07:59:51.87#ibcon#about to read 5, iclass 36, count 2 2006.239.07:59:51.87#ibcon#read 5, iclass 36, count 2 2006.239.07:59:51.87#ibcon#about to read 6, iclass 36, count 2 2006.239.07:59:51.87#ibcon#read 6, iclass 36, count 2 2006.239.07:59:51.87#ibcon#end of sib2, iclass 36, count 2 2006.239.07:59:51.87#ibcon#*after write, iclass 36, count 2 2006.239.07:59:51.87#ibcon#*before return 0, iclass 36, count 2 2006.239.07:59:51.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:51.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.07:59:51.87#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.07:59:51.87#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:51.87#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:51.99#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:51.99#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:51.99#ibcon#enter wrdev, iclass 36, count 0 2006.239.07:59:51.99#ibcon#first serial, iclass 36, count 0 2006.239.07:59:51.99#ibcon#enter sib2, iclass 36, count 0 2006.239.07:59:51.99#ibcon#flushed, iclass 36, count 0 2006.239.07:59:51.99#ibcon#about to write, iclass 36, count 0 2006.239.07:59:51.99#ibcon#wrote, iclass 36, count 0 2006.239.07:59:51.99#ibcon#about to read 3, iclass 36, count 0 2006.239.07:59:52.01#ibcon#read 3, iclass 36, count 0 2006.239.07:59:52.01#ibcon#about to read 4, iclass 36, count 0 2006.239.07:59:52.01#ibcon#read 4, iclass 36, count 0 2006.239.07:59:52.01#ibcon#about to read 5, iclass 36, count 0 2006.239.07:59:52.01#ibcon#read 5, iclass 36, count 0 2006.239.07:59:52.01#ibcon#about to read 6, iclass 36, count 0 2006.239.07:59:52.01#ibcon#read 6, iclass 36, count 0 2006.239.07:59:52.01#ibcon#end of sib2, iclass 36, count 0 2006.239.07:59:52.01#ibcon#*mode == 0, iclass 36, count 0 2006.239.07:59:52.01#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.07:59:52.01#ibcon#[27=USB\r\n] 2006.239.07:59:52.01#ibcon#*before write, iclass 36, count 0 2006.239.07:59:52.01#ibcon#enter sib2, iclass 36, count 0 2006.239.07:59:52.01#ibcon#flushed, iclass 36, count 0 2006.239.07:59:52.01#ibcon#about to write, iclass 36, count 0 2006.239.07:59:52.01#ibcon#wrote, iclass 36, count 0 2006.239.07:59:52.01#ibcon#about to read 3, iclass 36, count 0 2006.239.07:59:52.04#ibcon#read 3, iclass 36, count 0 2006.239.07:59:52.04#ibcon#about to read 4, iclass 36, count 0 2006.239.07:59:52.04#ibcon#read 4, iclass 36, count 0 2006.239.07:59:52.04#ibcon#about to read 5, iclass 36, count 0 2006.239.07:59:52.04#ibcon#read 5, iclass 36, count 0 2006.239.07:59:52.04#ibcon#about to read 6, iclass 36, count 0 2006.239.07:59:52.04#ibcon#read 6, iclass 36, count 0 2006.239.07:59:52.04#ibcon#end of sib2, iclass 36, count 0 2006.239.07:59:52.04#ibcon#*after write, iclass 36, count 0 2006.239.07:59:52.04#ibcon#*before return 0, iclass 36, count 0 2006.239.07:59:52.04#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:52.04#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.07:59:52.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.07:59:52.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.07:59:52.04$vc4f8/vblo=5,744.99 2006.239.07:59:52.04#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.07:59:52.04#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.07:59:52.04#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:52.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:52.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:52.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:52.04#ibcon#enter wrdev, iclass 38, count 0 2006.239.07:59:52.04#ibcon#first serial, iclass 38, count 0 2006.239.07:59:52.04#ibcon#enter sib2, iclass 38, count 0 2006.239.07:59:52.04#ibcon#flushed, iclass 38, count 0 2006.239.07:59:52.04#ibcon#about to write, iclass 38, count 0 2006.239.07:59:52.04#ibcon#wrote, iclass 38, count 0 2006.239.07:59:52.04#ibcon#about to read 3, iclass 38, count 0 2006.239.07:59:52.06#ibcon#read 3, iclass 38, count 0 2006.239.07:59:52.06#ibcon#about to read 4, iclass 38, count 0 2006.239.07:59:52.06#ibcon#read 4, iclass 38, count 0 2006.239.07:59:52.06#ibcon#about to read 5, iclass 38, count 0 2006.239.07:59:52.06#ibcon#read 5, iclass 38, count 0 2006.239.07:59:52.06#ibcon#about to read 6, iclass 38, count 0 2006.239.07:59:52.06#ibcon#read 6, iclass 38, count 0 2006.239.07:59:52.06#ibcon#end of sib2, iclass 38, count 0 2006.239.07:59:52.06#ibcon#*mode == 0, iclass 38, count 0 2006.239.07:59:52.06#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.07:59:52.06#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.07:59:52.06#ibcon#*before write, iclass 38, count 0 2006.239.07:59:52.06#ibcon#enter sib2, iclass 38, count 0 2006.239.07:59:52.06#ibcon#flushed, iclass 38, count 0 2006.239.07:59:52.06#ibcon#about to write, iclass 38, count 0 2006.239.07:59:52.06#ibcon#wrote, iclass 38, count 0 2006.239.07:59:52.06#ibcon#about to read 3, iclass 38, count 0 2006.239.07:59:52.10#ibcon#read 3, iclass 38, count 0 2006.239.07:59:52.10#ibcon#about to read 4, iclass 38, count 0 2006.239.07:59:52.10#ibcon#read 4, iclass 38, count 0 2006.239.07:59:52.10#ibcon#about to read 5, iclass 38, count 0 2006.239.07:59:52.10#ibcon#read 5, iclass 38, count 0 2006.239.07:59:52.10#ibcon#about to read 6, iclass 38, count 0 2006.239.07:59:52.10#ibcon#read 6, iclass 38, count 0 2006.239.07:59:52.10#ibcon#end of sib2, iclass 38, count 0 2006.239.07:59:52.10#ibcon#*after write, iclass 38, count 0 2006.239.07:59:52.10#ibcon#*before return 0, iclass 38, count 0 2006.239.07:59:52.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:52.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.07:59:52.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.07:59:52.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.07:59:52.10$vc4f8/vb=5,4 2006.239.07:59:52.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.07:59:52.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.07:59:52.10#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:52.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:52.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:52.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:52.16#ibcon#enter wrdev, iclass 40, count 2 2006.239.07:59:52.16#ibcon#first serial, iclass 40, count 2 2006.239.07:59:52.16#ibcon#enter sib2, iclass 40, count 2 2006.239.07:59:52.16#ibcon#flushed, iclass 40, count 2 2006.239.07:59:52.16#ibcon#about to write, iclass 40, count 2 2006.239.07:59:52.16#ibcon#wrote, iclass 40, count 2 2006.239.07:59:52.16#ibcon#about to read 3, iclass 40, count 2 2006.239.07:59:52.18#ibcon#read 3, iclass 40, count 2 2006.239.07:59:52.18#ibcon#about to read 4, iclass 40, count 2 2006.239.07:59:52.18#ibcon#read 4, iclass 40, count 2 2006.239.07:59:52.18#ibcon#about to read 5, iclass 40, count 2 2006.239.07:59:52.18#ibcon#read 5, iclass 40, count 2 2006.239.07:59:52.18#ibcon#about to read 6, iclass 40, count 2 2006.239.07:59:52.18#ibcon#read 6, iclass 40, count 2 2006.239.07:59:52.18#ibcon#end of sib2, iclass 40, count 2 2006.239.07:59:52.18#ibcon#*mode == 0, iclass 40, count 2 2006.239.07:59:52.18#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.07:59:52.18#ibcon#[27=AT05-04\r\n] 2006.239.07:59:52.18#ibcon#*before write, iclass 40, count 2 2006.239.07:59:52.18#ibcon#enter sib2, iclass 40, count 2 2006.239.07:59:52.18#ibcon#flushed, iclass 40, count 2 2006.239.07:59:52.18#ibcon#about to write, iclass 40, count 2 2006.239.07:59:52.18#ibcon#wrote, iclass 40, count 2 2006.239.07:59:52.18#ibcon#about to read 3, iclass 40, count 2 2006.239.07:59:52.21#ibcon#read 3, iclass 40, count 2 2006.239.07:59:52.21#ibcon#about to read 4, iclass 40, count 2 2006.239.07:59:52.21#ibcon#read 4, iclass 40, count 2 2006.239.07:59:52.21#ibcon#about to read 5, iclass 40, count 2 2006.239.07:59:52.21#ibcon#read 5, iclass 40, count 2 2006.239.07:59:52.21#ibcon#about to read 6, iclass 40, count 2 2006.239.07:59:52.21#ibcon#read 6, iclass 40, count 2 2006.239.07:59:52.21#ibcon#end of sib2, iclass 40, count 2 2006.239.07:59:52.21#ibcon#*after write, iclass 40, count 2 2006.239.07:59:52.21#ibcon#*before return 0, iclass 40, count 2 2006.239.07:59:52.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:52.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.07:59:52.21#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.07:59:52.21#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:52.21#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:52.33#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:52.33#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:52.33#ibcon#enter wrdev, iclass 40, count 0 2006.239.07:59:52.33#ibcon#first serial, iclass 40, count 0 2006.239.07:59:52.33#ibcon#enter sib2, iclass 40, count 0 2006.239.07:59:52.33#ibcon#flushed, iclass 40, count 0 2006.239.07:59:52.33#ibcon#about to write, iclass 40, count 0 2006.239.07:59:52.33#ibcon#wrote, iclass 40, count 0 2006.239.07:59:52.33#ibcon#about to read 3, iclass 40, count 0 2006.239.07:59:52.35#ibcon#read 3, iclass 40, count 0 2006.239.07:59:52.35#ibcon#about to read 4, iclass 40, count 0 2006.239.07:59:52.35#ibcon#read 4, iclass 40, count 0 2006.239.07:59:52.35#ibcon#about to read 5, iclass 40, count 0 2006.239.07:59:52.35#ibcon#read 5, iclass 40, count 0 2006.239.07:59:52.35#ibcon#about to read 6, iclass 40, count 0 2006.239.07:59:52.35#ibcon#read 6, iclass 40, count 0 2006.239.07:59:52.35#ibcon#end of sib2, iclass 40, count 0 2006.239.07:59:52.35#ibcon#*mode == 0, iclass 40, count 0 2006.239.07:59:52.35#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.07:59:52.35#ibcon#[27=USB\r\n] 2006.239.07:59:52.35#ibcon#*before write, iclass 40, count 0 2006.239.07:59:52.35#ibcon#enter sib2, iclass 40, count 0 2006.239.07:59:52.35#ibcon#flushed, iclass 40, count 0 2006.239.07:59:52.35#ibcon#about to write, iclass 40, count 0 2006.239.07:59:52.35#ibcon#wrote, iclass 40, count 0 2006.239.07:59:52.35#ibcon#about to read 3, iclass 40, count 0 2006.239.07:59:52.38#ibcon#read 3, iclass 40, count 0 2006.239.07:59:52.38#ibcon#about to read 4, iclass 40, count 0 2006.239.07:59:52.38#ibcon#read 4, iclass 40, count 0 2006.239.07:59:52.38#ibcon#about to read 5, iclass 40, count 0 2006.239.07:59:52.38#ibcon#read 5, iclass 40, count 0 2006.239.07:59:52.38#ibcon#about to read 6, iclass 40, count 0 2006.239.07:59:52.38#ibcon#read 6, iclass 40, count 0 2006.239.07:59:52.38#ibcon#end of sib2, iclass 40, count 0 2006.239.07:59:52.38#ibcon#*after write, iclass 40, count 0 2006.239.07:59:52.38#ibcon#*before return 0, iclass 40, count 0 2006.239.07:59:52.38#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:52.38#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.07:59:52.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.07:59:52.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.07:59:52.38$vc4f8/vblo=6,752.99 2006.239.07:59:52.38#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.07:59:52.38#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.07:59:52.38#ibcon#ireg 17 cls_cnt 0 2006.239.07:59:52.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:52.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:52.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:52.38#ibcon#enter wrdev, iclass 4, count 0 2006.239.07:59:52.38#ibcon#first serial, iclass 4, count 0 2006.239.07:59:52.38#ibcon#enter sib2, iclass 4, count 0 2006.239.07:59:52.38#ibcon#flushed, iclass 4, count 0 2006.239.07:59:52.38#ibcon#about to write, iclass 4, count 0 2006.239.07:59:52.38#ibcon#wrote, iclass 4, count 0 2006.239.07:59:52.38#ibcon#about to read 3, iclass 4, count 0 2006.239.07:59:52.40#ibcon#read 3, iclass 4, count 0 2006.239.07:59:52.40#ibcon#about to read 4, iclass 4, count 0 2006.239.07:59:52.40#ibcon#read 4, iclass 4, count 0 2006.239.07:59:52.40#ibcon#about to read 5, iclass 4, count 0 2006.239.07:59:52.40#ibcon#read 5, iclass 4, count 0 2006.239.07:59:52.40#ibcon#about to read 6, iclass 4, count 0 2006.239.07:59:52.40#ibcon#read 6, iclass 4, count 0 2006.239.07:59:52.40#ibcon#end of sib2, iclass 4, count 0 2006.239.07:59:52.40#ibcon#*mode == 0, iclass 4, count 0 2006.239.07:59:52.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.07:59:52.40#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.07:59:52.40#ibcon#*before write, iclass 4, count 0 2006.239.07:59:52.40#ibcon#enter sib2, iclass 4, count 0 2006.239.07:59:52.40#ibcon#flushed, iclass 4, count 0 2006.239.07:59:52.40#ibcon#about to write, iclass 4, count 0 2006.239.07:59:52.40#ibcon#wrote, iclass 4, count 0 2006.239.07:59:52.40#ibcon#about to read 3, iclass 4, count 0 2006.239.07:59:52.44#ibcon#read 3, iclass 4, count 0 2006.239.07:59:52.44#ibcon#about to read 4, iclass 4, count 0 2006.239.07:59:52.44#ibcon#read 4, iclass 4, count 0 2006.239.07:59:52.44#ibcon#about to read 5, iclass 4, count 0 2006.239.07:59:52.44#ibcon#read 5, iclass 4, count 0 2006.239.07:59:52.44#ibcon#about to read 6, iclass 4, count 0 2006.239.07:59:52.44#ibcon#read 6, iclass 4, count 0 2006.239.07:59:52.44#ibcon#end of sib2, iclass 4, count 0 2006.239.07:59:52.44#ibcon#*after write, iclass 4, count 0 2006.239.07:59:52.44#ibcon#*before return 0, iclass 4, count 0 2006.239.07:59:52.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:52.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.07:59:52.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.07:59:52.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.07:59:52.44$vc4f8/vb=6,4 2006.239.07:59:52.44#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.07:59:52.44#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.07:59:52.44#ibcon#ireg 11 cls_cnt 2 2006.239.07:59:52.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:52.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:52.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:52.50#ibcon#enter wrdev, iclass 6, count 2 2006.239.07:59:52.50#ibcon#first serial, iclass 6, count 2 2006.239.07:59:52.50#ibcon#enter sib2, iclass 6, count 2 2006.239.07:59:52.50#ibcon#flushed, iclass 6, count 2 2006.239.07:59:52.50#ibcon#about to write, iclass 6, count 2 2006.239.07:59:52.50#ibcon#wrote, iclass 6, count 2 2006.239.07:59:52.50#ibcon#about to read 3, iclass 6, count 2 2006.239.07:59:52.52#ibcon#read 3, iclass 6, count 2 2006.239.07:59:52.52#ibcon#about to read 4, iclass 6, count 2 2006.239.07:59:52.52#ibcon#read 4, iclass 6, count 2 2006.239.07:59:52.52#ibcon#about to read 5, iclass 6, count 2 2006.239.07:59:52.52#ibcon#read 5, iclass 6, count 2 2006.239.07:59:52.52#ibcon#about to read 6, iclass 6, count 2 2006.239.07:59:52.52#ibcon#read 6, iclass 6, count 2 2006.239.07:59:52.52#ibcon#end of sib2, iclass 6, count 2 2006.239.07:59:52.52#ibcon#*mode == 0, iclass 6, count 2 2006.239.07:59:52.52#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.07:59:52.52#ibcon#[27=AT06-04\r\n] 2006.239.07:59:52.52#ibcon#*before write, iclass 6, count 2 2006.239.07:59:52.52#ibcon#enter sib2, iclass 6, count 2 2006.239.07:59:52.52#ibcon#flushed, iclass 6, count 2 2006.239.07:59:52.52#ibcon#about to write, iclass 6, count 2 2006.239.07:59:52.52#ibcon#wrote, iclass 6, count 2 2006.239.07:59:52.52#ibcon#about to read 3, iclass 6, count 2 2006.239.07:59:52.55#ibcon#read 3, iclass 6, count 2 2006.239.07:59:52.55#ibcon#about to read 4, iclass 6, count 2 2006.239.07:59:52.55#ibcon#read 4, iclass 6, count 2 2006.239.07:59:52.55#ibcon#about to read 5, iclass 6, count 2 2006.239.07:59:52.55#ibcon#read 5, iclass 6, count 2 2006.239.07:59:52.55#ibcon#about to read 6, iclass 6, count 2 2006.239.07:59:52.55#ibcon#read 6, iclass 6, count 2 2006.239.07:59:52.55#ibcon#end of sib2, iclass 6, count 2 2006.239.07:59:52.55#ibcon#*after write, iclass 6, count 2 2006.239.07:59:52.55#ibcon#*before return 0, iclass 6, count 2 2006.239.07:59:52.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:52.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.07:59:52.55#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.07:59:52.55#ibcon#ireg 7 cls_cnt 0 2006.239.07:59:52.55#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:52.67#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:52.67#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:52.67#ibcon#enter wrdev, iclass 6, count 0 2006.239.07:59:52.67#ibcon#first serial, iclass 6, count 0 2006.239.07:59:52.67#ibcon#enter sib2, iclass 6, count 0 2006.239.07:59:52.67#ibcon#flushed, iclass 6, count 0 2006.239.07:59:52.67#ibcon#about to write, iclass 6, count 0 2006.239.07:59:52.67#ibcon#wrote, iclass 6, count 0 2006.239.07:59:52.67#ibcon#about to read 3, iclass 6, count 0 2006.239.07:59:52.69#ibcon#read 3, iclass 6, count 0 2006.239.07:59:52.69#ibcon#about to read 4, iclass 6, count 0 2006.239.07:59:52.69#ibcon#read 4, iclass 6, count 0 2006.239.07:59:52.69#ibcon#about to read 5, iclass 6, count 0 2006.239.07:59:52.69#ibcon#read 5, iclass 6, count 0 2006.239.07:59:52.69#ibcon#about to read 6, iclass 6, count 0 2006.239.07:59:52.69#ibcon#read 6, iclass 6, count 0 2006.239.07:59:52.69#ibcon#end of sib2, iclass 6, count 0 2006.239.07:59:52.69#ibcon#*mode == 0, iclass 6, count 0 2006.239.07:59:52.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.07:59:52.69#ibcon#[27=USB\r\n] 2006.239.07:59:52.69#ibcon#*before write, iclass 6, count 0 2006.239.07:59:52.69#ibcon#enter sib2, iclass 6, count 0 2006.239.07:59:52.69#ibcon#flushed, iclass 6, count 0 2006.239.07:59:52.69#ibcon#about to write, iclass 6, count 0 2006.239.07:59:52.69#ibcon#wrote, iclass 6, count 0 2006.239.07:59:52.69#ibcon#about to read 3, iclass 6, count 0 2006.239.07:59:52.72#ibcon#read 3, iclass 6, count 0 2006.239.07:59:52.72#ibcon#about to read 4, iclass 6, count 0 2006.239.07:59:52.72#ibcon#read 4, iclass 6, count 0 2006.239.07:59:52.72#ibcon#about to read 5, iclass 6, count 0 2006.239.07:59:52.72#ibcon#read 5, iclass 6, count 0 2006.239.07:59:52.72#ibcon#about to read 6, iclass 6, count 0 2006.239.07:59:52.72#ibcon#read 6, iclass 6, count 0 2006.239.07:59:52.72#ibcon#end of sib2, iclass 6, count 0 2006.239.07:59:52.72#ibcon#*after write, iclass 6, count 0 2006.239.07:59:52.72#ibcon#*before return 0, iclass 6, count 0 2006.239.07:59:52.72#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:52.72#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.07:59:52.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.07:59:52.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.07:59:52.72$vc4f8/vabw=wide 2006.239.07:59:52.72#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.07:59:52.72#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.07:59:52.72#ibcon#ireg 8 cls_cnt 0 2006.239.07:59:52.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:52.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:52.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:52.72#ibcon#enter wrdev, iclass 10, count 0 2006.239.07:59:52.72#ibcon#first serial, iclass 10, count 0 2006.239.07:59:52.72#ibcon#enter sib2, iclass 10, count 0 2006.239.07:59:52.72#ibcon#flushed, iclass 10, count 0 2006.239.07:59:52.72#ibcon#about to write, iclass 10, count 0 2006.239.07:59:52.72#ibcon#wrote, iclass 10, count 0 2006.239.07:59:52.72#ibcon#about to read 3, iclass 10, count 0 2006.239.07:59:52.74#ibcon#read 3, iclass 10, count 0 2006.239.07:59:52.74#ibcon#about to read 4, iclass 10, count 0 2006.239.07:59:52.74#ibcon#read 4, iclass 10, count 0 2006.239.07:59:52.74#ibcon#about to read 5, iclass 10, count 0 2006.239.07:59:52.74#ibcon#read 5, iclass 10, count 0 2006.239.07:59:52.74#ibcon#about to read 6, iclass 10, count 0 2006.239.07:59:52.74#ibcon#read 6, iclass 10, count 0 2006.239.07:59:52.74#ibcon#end of sib2, iclass 10, count 0 2006.239.07:59:52.74#ibcon#*mode == 0, iclass 10, count 0 2006.239.07:59:52.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.07:59:52.74#ibcon#[25=BW32\r\n] 2006.239.07:59:52.74#ibcon#*before write, iclass 10, count 0 2006.239.07:59:52.74#ibcon#enter sib2, iclass 10, count 0 2006.239.07:59:52.74#ibcon#flushed, iclass 10, count 0 2006.239.07:59:52.74#ibcon#about to write, iclass 10, count 0 2006.239.07:59:52.74#ibcon#wrote, iclass 10, count 0 2006.239.07:59:52.74#ibcon#about to read 3, iclass 10, count 0 2006.239.07:59:52.77#ibcon#read 3, iclass 10, count 0 2006.239.07:59:52.77#ibcon#about to read 4, iclass 10, count 0 2006.239.07:59:52.77#ibcon#read 4, iclass 10, count 0 2006.239.07:59:52.77#ibcon#about to read 5, iclass 10, count 0 2006.239.07:59:52.77#ibcon#read 5, iclass 10, count 0 2006.239.07:59:52.77#ibcon#about to read 6, iclass 10, count 0 2006.239.07:59:52.77#ibcon#read 6, iclass 10, count 0 2006.239.07:59:52.77#ibcon#end of sib2, iclass 10, count 0 2006.239.07:59:52.77#ibcon#*after write, iclass 10, count 0 2006.239.07:59:52.77#ibcon#*before return 0, iclass 10, count 0 2006.239.07:59:52.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:52.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.07:59:52.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.07:59:52.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.07:59:52.77$vc4f8/vbbw=wide 2006.239.07:59:52.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.07:59:52.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.07:59:52.77#ibcon#ireg 8 cls_cnt 0 2006.239.07:59:52.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:59:52.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:59:52.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:59:52.84#ibcon#enter wrdev, iclass 12, count 0 2006.239.07:59:52.84#ibcon#first serial, iclass 12, count 0 2006.239.07:59:52.84#ibcon#enter sib2, iclass 12, count 0 2006.239.07:59:52.84#ibcon#flushed, iclass 12, count 0 2006.239.07:59:52.84#ibcon#about to write, iclass 12, count 0 2006.239.07:59:52.84#ibcon#wrote, iclass 12, count 0 2006.239.07:59:52.84#ibcon#about to read 3, iclass 12, count 0 2006.239.07:59:52.86#ibcon#read 3, iclass 12, count 0 2006.239.07:59:52.86#ibcon#about to read 4, iclass 12, count 0 2006.239.07:59:52.86#ibcon#read 4, iclass 12, count 0 2006.239.07:59:52.86#ibcon#about to read 5, iclass 12, count 0 2006.239.07:59:52.86#ibcon#read 5, iclass 12, count 0 2006.239.07:59:52.86#ibcon#about to read 6, iclass 12, count 0 2006.239.07:59:52.86#ibcon#read 6, iclass 12, count 0 2006.239.07:59:52.86#ibcon#end of sib2, iclass 12, count 0 2006.239.07:59:52.86#ibcon#*mode == 0, iclass 12, count 0 2006.239.07:59:52.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.07:59:52.86#ibcon#[27=BW32\r\n] 2006.239.07:59:52.86#ibcon#*before write, iclass 12, count 0 2006.239.07:59:52.86#ibcon#enter sib2, iclass 12, count 0 2006.239.07:59:52.86#ibcon#flushed, iclass 12, count 0 2006.239.07:59:52.86#ibcon#about to write, iclass 12, count 0 2006.239.07:59:52.86#ibcon#wrote, iclass 12, count 0 2006.239.07:59:52.86#ibcon#about to read 3, iclass 12, count 0 2006.239.07:59:52.89#ibcon#read 3, iclass 12, count 0 2006.239.07:59:52.89#ibcon#about to read 4, iclass 12, count 0 2006.239.07:59:52.89#ibcon#read 4, iclass 12, count 0 2006.239.07:59:52.89#ibcon#about to read 5, iclass 12, count 0 2006.239.07:59:52.89#ibcon#read 5, iclass 12, count 0 2006.239.07:59:52.89#ibcon#about to read 6, iclass 12, count 0 2006.239.07:59:52.89#ibcon#read 6, iclass 12, count 0 2006.239.07:59:52.89#ibcon#end of sib2, iclass 12, count 0 2006.239.07:59:52.89#ibcon#*after write, iclass 12, count 0 2006.239.07:59:52.89#ibcon#*before return 0, iclass 12, count 0 2006.239.07:59:52.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:59:52.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.07:59:52.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.07:59:52.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.07:59:52.89$4f8m12a/ifd4f 2006.239.07:59:52.89$ifd4f/lo= 2006.239.07:59:52.89$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.07:59:52.89$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.07:59:52.89$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.07:59:52.89$ifd4f/patch= 2006.239.07:59:52.89$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.07:59:52.89$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.07:59:52.89$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.07:59:52.89$4f8m12a/"form=m,16.000,1:2 2006.239.07:59:52.89$4f8m12a/"tpicd 2006.239.07:59:52.89$4f8m12a/echo=off 2006.239.07:59:52.89$4f8m12a/xlog=off 2006.239.07:59:52.89:!2006.239.08:00:20 2006.239.08:00:01.14#trakl#Source acquired 2006.239.08:00:02.14#flagr#flagr/antenna,acquired 2006.239.08:00:20.00:preob 2006.239.08:00:21.14/onsource/TRACKING 2006.239.08:00:21.14:!2006.239.08:00:30 2006.239.08:00:30.00:data_valid=on 2006.239.08:00:30.00:midob 2006.239.08:00:30.14/onsource/TRACKING 2006.239.08:00:30.14/wx/25.17,1011.6,79 2006.239.08:00:30.22/cable/+6.4150E-03 2006.239.08:00:31.31/va/01,08,usb,yes,31,32 2006.239.08:00:31.31/va/02,07,usb,yes,31,32 2006.239.08:00:31.31/va/03,07,usb,yes,29,29 2006.239.08:00:31.31/va/04,07,usb,yes,32,35 2006.239.08:00:31.31/va/05,08,usb,yes,29,31 2006.239.08:00:31.31/va/06,07,usb,yes,32,31 2006.239.08:00:31.31/va/07,07,usb,yes,31,31 2006.239.08:00:31.31/va/08,07,usb,yes,34,34 2006.239.08:00:31.54/valo/01,532.99,yes,locked 2006.239.08:00:31.54/valo/02,572.99,yes,locked 2006.239.08:00:31.54/valo/03,672.99,yes,locked 2006.239.08:00:31.54/valo/04,832.99,yes,locked 2006.239.08:00:31.54/valo/05,652.99,yes,locked 2006.239.08:00:31.54/valo/06,772.99,yes,locked 2006.239.08:00:31.54/valo/07,832.99,yes,locked 2006.239.08:00:31.54/valo/08,852.99,yes,locked 2006.239.08:00:32.63/vb/01,04,usb,yes,30,29 2006.239.08:00:32.63/vb/02,04,usb,yes,32,33 2006.239.08:00:32.63/vb/03,04,usb,yes,28,32 2006.239.08:00:32.63/vb/04,04,usb,yes,29,29 2006.239.08:00:32.63/vb/05,04,usb,yes,27,31 2006.239.08:00:32.63/vb/06,04,usb,yes,28,31 2006.239.08:00:32.63/vb/07,04,usb,yes,31,30 2006.239.08:00:32.63/vb/08,04,usb,yes,28,31 2006.239.08:00:32.87/vblo/01,632.99,yes,locked 2006.239.08:00:32.87/vblo/02,640.99,yes,locked 2006.239.08:00:32.87/vblo/03,656.99,yes,locked 2006.239.08:00:32.87/vblo/04,712.99,yes,locked 2006.239.08:00:32.87/vblo/05,744.99,yes,locked 2006.239.08:00:32.87/vblo/06,752.99,yes,locked 2006.239.08:00:32.87/vblo/07,734.99,yes,locked 2006.239.08:00:32.87/vblo/08,744.99,yes,locked 2006.239.08:00:33.02/vabw/8 2006.239.08:00:33.17/vbbw/8 2006.239.08:00:33.27/xfe/off,on,13.2 2006.239.08:00:33.65/ifatt/23,28,28,28 2006.239.08:00:34.07/fmout-gps/S +4.43E-07 2006.239.08:00:34.11:!2006.239.08:01:30 2006.239.08:01:30.00:data_valid=off 2006.239.08:01:30.00:postob 2006.239.08:01:30.17/cable/+6.4136E-03 2006.239.08:01:30.17/wx/25.16,1011.6,80 2006.239.08:01:31.08/fmout-gps/S +4.42E-07 2006.239.08:01:31.08:scan_name=239-0802,k06239,60 2006.239.08:01:31.09:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.239.08:01:31.14#flagr#flagr/antenna,new-source 2006.239.08:01:32.14:checkk5 2006.239.08:01:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:01:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:01:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:01:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:01:34.01/chk_obsdata//k5ts1/T2390800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:01:34.38/chk_obsdata//k5ts2/T2390800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:01:34.75/chk_obsdata//k5ts3/T2390800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:01:35.12/chk_obsdata//k5ts4/T2390800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:01:35.82/k5log//k5ts1_log_newline 2006.239.08:01:36.52/k5log//k5ts2_log_newline 2006.239.08:01:37.21/k5log//k5ts3_log_newline 2006.239.08:01:37.90/k5log//k5ts4_log_newline 2006.239.08:01:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:01:37.92:4f8m12a=2 2006.239.08:01:37.92$4f8m12a/echo=on 2006.239.08:01:37.92$4f8m12a/pcalon 2006.239.08:01:37.92$pcalon/"no phase cal control is implemented here 2006.239.08:01:37.92$4f8m12a/"tpicd=stop 2006.239.08:01:37.92$4f8m12a/vc4f8 2006.239.08:01:37.92$vc4f8/valo=1,532.99 2006.239.08:01:37.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.08:01:37.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.08:01:37.93#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:37.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:37.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:37.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:37.93#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:01:37.93#ibcon#first serial, iclass 23, count 0 2006.239.08:01:37.93#ibcon#enter sib2, iclass 23, count 0 2006.239.08:01:37.93#ibcon#flushed, iclass 23, count 0 2006.239.08:01:37.93#ibcon#about to write, iclass 23, count 0 2006.239.08:01:37.93#ibcon#wrote, iclass 23, count 0 2006.239.08:01:37.93#ibcon#about to read 3, iclass 23, count 0 2006.239.08:01:37.97#ibcon#read 3, iclass 23, count 0 2006.239.08:01:37.97#ibcon#about to read 4, iclass 23, count 0 2006.239.08:01:37.97#ibcon#read 4, iclass 23, count 0 2006.239.08:01:37.97#ibcon#about to read 5, iclass 23, count 0 2006.239.08:01:37.97#ibcon#read 5, iclass 23, count 0 2006.239.08:01:37.97#ibcon#about to read 6, iclass 23, count 0 2006.239.08:01:37.97#ibcon#read 6, iclass 23, count 0 2006.239.08:01:37.97#ibcon#end of sib2, iclass 23, count 0 2006.239.08:01:37.97#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:01:37.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:01:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:01:37.97#ibcon#*before write, iclass 23, count 0 2006.239.08:01:37.97#ibcon#enter sib2, iclass 23, count 0 2006.239.08:01:37.97#ibcon#flushed, iclass 23, count 0 2006.239.08:01:37.97#ibcon#about to write, iclass 23, count 0 2006.239.08:01:37.97#ibcon#wrote, iclass 23, count 0 2006.239.08:01:37.97#ibcon#about to read 3, iclass 23, count 0 2006.239.08:01:38.02#ibcon#read 3, iclass 23, count 0 2006.239.08:01:38.02#ibcon#about to read 4, iclass 23, count 0 2006.239.08:01:38.02#ibcon#read 4, iclass 23, count 0 2006.239.08:01:38.02#ibcon#about to read 5, iclass 23, count 0 2006.239.08:01:38.02#ibcon#read 5, iclass 23, count 0 2006.239.08:01:38.02#ibcon#about to read 6, iclass 23, count 0 2006.239.08:01:38.02#ibcon#read 6, iclass 23, count 0 2006.239.08:01:38.02#ibcon#end of sib2, iclass 23, count 0 2006.239.08:01:38.02#ibcon#*after write, iclass 23, count 0 2006.239.08:01:38.02#ibcon#*before return 0, iclass 23, count 0 2006.239.08:01:38.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:38.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:38.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:01:38.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:01:38.02$vc4f8/va=1,8 2006.239.08:01:38.02#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.08:01:38.02#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.08:01:38.02#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:38.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:38.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:38.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:38.02#ibcon#enter wrdev, iclass 25, count 2 2006.239.08:01:38.02#ibcon#first serial, iclass 25, count 2 2006.239.08:01:38.02#ibcon#enter sib2, iclass 25, count 2 2006.239.08:01:38.02#ibcon#flushed, iclass 25, count 2 2006.239.08:01:38.02#ibcon#about to write, iclass 25, count 2 2006.239.08:01:38.02#ibcon#wrote, iclass 25, count 2 2006.239.08:01:38.02#ibcon#about to read 3, iclass 25, count 2 2006.239.08:01:38.04#ibcon#read 3, iclass 25, count 2 2006.239.08:01:38.04#ibcon#about to read 4, iclass 25, count 2 2006.239.08:01:38.04#ibcon#read 4, iclass 25, count 2 2006.239.08:01:38.04#ibcon#about to read 5, iclass 25, count 2 2006.239.08:01:38.04#ibcon#read 5, iclass 25, count 2 2006.239.08:01:38.04#ibcon#about to read 6, iclass 25, count 2 2006.239.08:01:38.04#ibcon#read 6, iclass 25, count 2 2006.239.08:01:38.04#ibcon#end of sib2, iclass 25, count 2 2006.239.08:01:38.04#ibcon#*mode == 0, iclass 25, count 2 2006.239.08:01:38.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.08:01:38.04#ibcon#[25=AT01-08\r\n] 2006.239.08:01:38.04#ibcon#*before write, iclass 25, count 2 2006.239.08:01:38.04#ibcon#enter sib2, iclass 25, count 2 2006.239.08:01:38.04#ibcon#flushed, iclass 25, count 2 2006.239.08:01:38.04#ibcon#about to write, iclass 25, count 2 2006.239.08:01:38.04#ibcon#wrote, iclass 25, count 2 2006.239.08:01:38.04#ibcon#about to read 3, iclass 25, count 2 2006.239.08:01:38.07#ibcon#read 3, iclass 25, count 2 2006.239.08:01:38.07#ibcon#about to read 4, iclass 25, count 2 2006.239.08:01:38.07#ibcon#read 4, iclass 25, count 2 2006.239.08:01:38.07#ibcon#about to read 5, iclass 25, count 2 2006.239.08:01:38.07#ibcon#read 5, iclass 25, count 2 2006.239.08:01:38.07#ibcon#about to read 6, iclass 25, count 2 2006.239.08:01:38.07#ibcon#read 6, iclass 25, count 2 2006.239.08:01:38.07#ibcon#end of sib2, iclass 25, count 2 2006.239.08:01:38.07#ibcon#*after write, iclass 25, count 2 2006.239.08:01:38.07#ibcon#*before return 0, iclass 25, count 2 2006.239.08:01:38.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:38.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:38.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.08:01:38.07#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:38.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:38.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:38.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:38.19#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:01:38.19#ibcon#first serial, iclass 25, count 0 2006.239.08:01:38.19#ibcon#enter sib2, iclass 25, count 0 2006.239.08:01:38.19#ibcon#flushed, iclass 25, count 0 2006.239.08:01:38.19#ibcon#about to write, iclass 25, count 0 2006.239.08:01:38.19#ibcon#wrote, iclass 25, count 0 2006.239.08:01:38.19#ibcon#about to read 3, iclass 25, count 0 2006.239.08:01:38.21#ibcon#read 3, iclass 25, count 0 2006.239.08:01:38.21#ibcon#about to read 4, iclass 25, count 0 2006.239.08:01:38.21#ibcon#read 4, iclass 25, count 0 2006.239.08:01:38.21#ibcon#about to read 5, iclass 25, count 0 2006.239.08:01:38.21#ibcon#read 5, iclass 25, count 0 2006.239.08:01:38.21#ibcon#about to read 6, iclass 25, count 0 2006.239.08:01:38.21#ibcon#read 6, iclass 25, count 0 2006.239.08:01:38.21#ibcon#end of sib2, iclass 25, count 0 2006.239.08:01:38.21#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:01:38.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:01:38.21#ibcon#[25=USB\r\n] 2006.239.08:01:38.21#ibcon#*before write, iclass 25, count 0 2006.239.08:01:38.21#ibcon#enter sib2, iclass 25, count 0 2006.239.08:01:38.21#ibcon#flushed, iclass 25, count 0 2006.239.08:01:38.21#ibcon#about to write, iclass 25, count 0 2006.239.08:01:38.21#ibcon#wrote, iclass 25, count 0 2006.239.08:01:38.21#ibcon#about to read 3, iclass 25, count 0 2006.239.08:01:38.24#ibcon#read 3, iclass 25, count 0 2006.239.08:01:38.24#ibcon#about to read 4, iclass 25, count 0 2006.239.08:01:38.24#ibcon#read 4, iclass 25, count 0 2006.239.08:01:38.24#ibcon#about to read 5, iclass 25, count 0 2006.239.08:01:38.24#ibcon#read 5, iclass 25, count 0 2006.239.08:01:38.24#ibcon#about to read 6, iclass 25, count 0 2006.239.08:01:38.24#ibcon#read 6, iclass 25, count 0 2006.239.08:01:38.24#ibcon#end of sib2, iclass 25, count 0 2006.239.08:01:38.24#ibcon#*after write, iclass 25, count 0 2006.239.08:01:38.24#ibcon#*before return 0, iclass 25, count 0 2006.239.08:01:38.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:38.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:38.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:01:38.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:01:38.24$vc4f8/valo=2,572.99 2006.239.08:01:38.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.08:01:38.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.08:01:38.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:38.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:38.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:38.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:38.24#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:01:38.24#ibcon#first serial, iclass 27, count 0 2006.239.08:01:38.24#ibcon#enter sib2, iclass 27, count 0 2006.239.08:01:38.24#ibcon#flushed, iclass 27, count 0 2006.239.08:01:38.24#ibcon#about to write, iclass 27, count 0 2006.239.08:01:38.24#ibcon#wrote, iclass 27, count 0 2006.239.08:01:38.24#ibcon#about to read 3, iclass 27, count 0 2006.239.08:01:38.26#ibcon#read 3, iclass 27, count 0 2006.239.08:01:38.26#ibcon#about to read 4, iclass 27, count 0 2006.239.08:01:38.26#ibcon#read 4, iclass 27, count 0 2006.239.08:01:38.26#ibcon#about to read 5, iclass 27, count 0 2006.239.08:01:38.26#ibcon#read 5, iclass 27, count 0 2006.239.08:01:38.26#ibcon#about to read 6, iclass 27, count 0 2006.239.08:01:38.26#ibcon#read 6, iclass 27, count 0 2006.239.08:01:38.26#ibcon#end of sib2, iclass 27, count 0 2006.239.08:01:38.26#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:01:38.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:01:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:01:38.26#ibcon#*before write, iclass 27, count 0 2006.239.08:01:38.26#ibcon#enter sib2, iclass 27, count 0 2006.239.08:01:38.26#ibcon#flushed, iclass 27, count 0 2006.239.08:01:38.26#ibcon#about to write, iclass 27, count 0 2006.239.08:01:38.26#ibcon#wrote, iclass 27, count 0 2006.239.08:01:38.26#ibcon#about to read 3, iclass 27, count 0 2006.239.08:01:38.30#ibcon#read 3, iclass 27, count 0 2006.239.08:01:38.30#ibcon#about to read 4, iclass 27, count 0 2006.239.08:01:38.30#ibcon#read 4, iclass 27, count 0 2006.239.08:01:38.30#ibcon#about to read 5, iclass 27, count 0 2006.239.08:01:38.30#ibcon#read 5, iclass 27, count 0 2006.239.08:01:38.30#ibcon#about to read 6, iclass 27, count 0 2006.239.08:01:38.30#ibcon#read 6, iclass 27, count 0 2006.239.08:01:38.30#ibcon#end of sib2, iclass 27, count 0 2006.239.08:01:38.30#ibcon#*after write, iclass 27, count 0 2006.239.08:01:38.30#ibcon#*before return 0, iclass 27, count 0 2006.239.08:01:38.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:38.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:38.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:01:38.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:01:38.30$vc4f8/va=2,7 2006.239.08:01:38.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.08:01:38.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.08:01:38.30#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:38.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:38.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:38.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:38.36#ibcon#enter wrdev, iclass 29, count 2 2006.239.08:01:38.36#ibcon#first serial, iclass 29, count 2 2006.239.08:01:38.36#ibcon#enter sib2, iclass 29, count 2 2006.239.08:01:38.36#ibcon#flushed, iclass 29, count 2 2006.239.08:01:38.36#ibcon#about to write, iclass 29, count 2 2006.239.08:01:38.36#ibcon#wrote, iclass 29, count 2 2006.239.08:01:38.36#ibcon#about to read 3, iclass 29, count 2 2006.239.08:01:38.38#ibcon#read 3, iclass 29, count 2 2006.239.08:01:38.38#ibcon#about to read 4, iclass 29, count 2 2006.239.08:01:38.38#ibcon#read 4, iclass 29, count 2 2006.239.08:01:38.38#ibcon#about to read 5, iclass 29, count 2 2006.239.08:01:38.38#ibcon#read 5, iclass 29, count 2 2006.239.08:01:38.38#ibcon#about to read 6, iclass 29, count 2 2006.239.08:01:38.38#ibcon#read 6, iclass 29, count 2 2006.239.08:01:38.38#ibcon#end of sib2, iclass 29, count 2 2006.239.08:01:38.38#ibcon#*mode == 0, iclass 29, count 2 2006.239.08:01:38.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.08:01:38.38#ibcon#[25=AT02-07\r\n] 2006.239.08:01:38.38#ibcon#*before write, iclass 29, count 2 2006.239.08:01:38.38#ibcon#enter sib2, iclass 29, count 2 2006.239.08:01:38.38#ibcon#flushed, iclass 29, count 2 2006.239.08:01:38.38#ibcon#about to write, iclass 29, count 2 2006.239.08:01:38.38#ibcon#wrote, iclass 29, count 2 2006.239.08:01:38.38#ibcon#about to read 3, iclass 29, count 2 2006.239.08:01:38.41#ibcon#read 3, iclass 29, count 2 2006.239.08:01:38.41#ibcon#about to read 4, iclass 29, count 2 2006.239.08:01:38.41#ibcon#read 4, iclass 29, count 2 2006.239.08:01:38.41#ibcon#about to read 5, iclass 29, count 2 2006.239.08:01:38.41#ibcon#read 5, iclass 29, count 2 2006.239.08:01:38.41#ibcon#about to read 6, iclass 29, count 2 2006.239.08:01:38.41#ibcon#read 6, iclass 29, count 2 2006.239.08:01:38.41#ibcon#end of sib2, iclass 29, count 2 2006.239.08:01:38.41#ibcon#*after write, iclass 29, count 2 2006.239.08:01:38.41#ibcon#*before return 0, iclass 29, count 2 2006.239.08:01:38.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:38.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:38.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.08:01:38.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:38.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:38.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:38.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:38.53#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:01:38.53#ibcon#first serial, iclass 29, count 0 2006.239.08:01:38.53#ibcon#enter sib2, iclass 29, count 0 2006.239.08:01:38.53#ibcon#flushed, iclass 29, count 0 2006.239.08:01:38.53#ibcon#about to write, iclass 29, count 0 2006.239.08:01:38.53#ibcon#wrote, iclass 29, count 0 2006.239.08:01:38.53#ibcon#about to read 3, iclass 29, count 0 2006.239.08:01:38.55#ibcon#read 3, iclass 29, count 0 2006.239.08:01:38.55#ibcon#about to read 4, iclass 29, count 0 2006.239.08:01:38.55#ibcon#read 4, iclass 29, count 0 2006.239.08:01:38.55#ibcon#about to read 5, iclass 29, count 0 2006.239.08:01:38.55#ibcon#read 5, iclass 29, count 0 2006.239.08:01:38.55#ibcon#about to read 6, iclass 29, count 0 2006.239.08:01:38.55#ibcon#read 6, iclass 29, count 0 2006.239.08:01:38.55#ibcon#end of sib2, iclass 29, count 0 2006.239.08:01:38.55#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:01:38.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:01:38.55#ibcon#[25=USB\r\n] 2006.239.08:01:38.55#ibcon#*before write, iclass 29, count 0 2006.239.08:01:38.55#ibcon#enter sib2, iclass 29, count 0 2006.239.08:01:38.55#ibcon#flushed, iclass 29, count 0 2006.239.08:01:38.55#ibcon#about to write, iclass 29, count 0 2006.239.08:01:38.55#ibcon#wrote, iclass 29, count 0 2006.239.08:01:38.55#ibcon#about to read 3, iclass 29, count 0 2006.239.08:01:38.58#ibcon#read 3, iclass 29, count 0 2006.239.08:01:38.58#ibcon#about to read 4, iclass 29, count 0 2006.239.08:01:38.58#ibcon#read 4, iclass 29, count 0 2006.239.08:01:38.58#ibcon#about to read 5, iclass 29, count 0 2006.239.08:01:38.58#ibcon#read 5, iclass 29, count 0 2006.239.08:01:38.58#ibcon#about to read 6, iclass 29, count 0 2006.239.08:01:38.58#ibcon#read 6, iclass 29, count 0 2006.239.08:01:38.58#ibcon#end of sib2, iclass 29, count 0 2006.239.08:01:38.58#ibcon#*after write, iclass 29, count 0 2006.239.08:01:38.58#ibcon#*before return 0, iclass 29, count 0 2006.239.08:01:38.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:38.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:38.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:01:38.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:01:38.58$vc4f8/valo=3,672.99 2006.239.08:01:38.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.08:01:38.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.08:01:38.58#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:38.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:38.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:38.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:38.58#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:01:38.58#ibcon#first serial, iclass 31, count 0 2006.239.08:01:38.58#ibcon#enter sib2, iclass 31, count 0 2006.239.08:01:38.58#ibcon#flushed, iclass 31, count 0 2006.239.08:01:38.58#ibcon#about to write, iclass 31, count 0 2006.239.08:01:38.58#ibcon#wrote, iclass 31, count 0 2006.239.08:01:38.58#ibcon#about to read 3, iclass 31, count 0 2006.239.08:01:38.60#ibcon#read 3, iclass 31, count 0 2006.239.08:01:38.60#ibcon#about to read 4, iclass 31, count 0 2006.239.08:01:38.60#ibcon#read 4, iclass 31, count 0 2006.239.08:01:38.60#ibcon#about to read 5, iclass 31, count 0 2006.239.08:01:38.60#ibcon#read 5, iclass 31, count 0 2006.239.08:01:38.60#ibcon#about to read 6, iclass 31, count 0 2006.239.08:01:38.60#ibcon#read 6, iclass 31, count 0 2006.239.08:01:38.60#ibcon#end of sib2, iclass 31, count 0 2006.239.08:01:38.60#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:01:38.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:01:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:01:38.60#ibcon#*before write, iclass 31, count 0 2006.239.08:01:38.60#ibcon#enter sib2, iclass 31, count 0 2006.239.08:01:38.60#ibcon#flushed, iclass 31, count 0 2006.239.08:01:38.60#ibcon#about to write, iclass 31, count 0 2006.239.08:01:38.60#ibcon#wrote, iclass 31, count 0 2006.239.08:01:38.60#ibcon#about to read 3, iclass 31, count 0 2006.239.08:01:38.64#ibcon#read 3, iclass 31, count 0 2006.239.08:01:38.64#ibcon#about to read 4, iclass 31, count 0 2006.239.08:01:38.64#ibcon#read 4, iclass 31, count 0 2006.239.08:01:38.64#ibcon#about to read 5, iclass 31, count 0 2006.239.08:01:38.64#ibcon#read 5, iclass 31, count 0 2006.239.08:01:38.64#ibcon#about to read 6, iclass 31, count 0 2006.239.08:01:38.64#ibcon#read 6, iclass 31, count 0 2006.239.08:01:38.64#ibcon#end of sib2, iclass 31, count 0 2006.239.08:01:38.64#ibcon#*after write, iclass 31, count 0 2006.239.08:01:38.64#ibcon#*before return 0, iclass 31, count 0 2006.239.08:01:38.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:38.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:38.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:01:38.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:01:38.64$vc4f8/va=3,7 2006.239.08:01:38.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.08:01:38.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.08:01:38.64#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:38.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:38.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:38.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:38.70#ibcon#enter wrdev, iclass 33, count 2 2006.239.08:01:38.70#ibcon#first serial, iclass 33, count 2 2006.239.08:01:38.70#ibcon#enter sib2, iclass 33, count 2 2006.239.08:01:38.70#ibcon#flushed, iclass 33, count 2 2006.239.08:01:38.70#ibcon#about to write, iclass 33, count 2 2006.239.08:01:38.70#ibcon#wrote, iclass 33, count 2 2006.239.08:01:38.70#ibcon#about to read 3, iclass 33, count 2 2006.239.08:01:38.72#ibcon#read 3, iclass 33, count 2 2006.239.08:01:38.72#ibcon#about to read 4, iclass 33, count 2 2006.239.08:01:38.72#ibcon#read 4, iclass 33, count 2 2006.239.08:01:38.72#ibcon#about to read 5, iclass 33, count 2 2006.239.08:01:38.72#ibcon#read 5, iclass 33, count 2 2006.239.08:01:38.72#ibcon#about to read 6, iclass 33, count 2 2006.239.08:01:38.72#ibcon#read 6, iclass 33, count 2 2006.239.08:01:38.72#ibcon#end of sib2, iclass 33, count 2 2006.239.08:01:38.72#ibcon#*mode == 0, iclass 33, count 2 2006.239.08:01:38.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.08:01:38.72#ibcon#[25=AT03-07\r\n] 2006.239.08:01:38.72#ibcon#*before write, iclass 33, count 2 2006.239.08:01:38.72#ibcon#enter sib2, iclass 33, count 2 2006.239.08:01:38.72#ibcon#flushed, iclass 33, count 2 2006.239.08:01:38.72#ibcon#about to write, iclass 33, count 2 2006.239.08:01:38.72#ibcon#wrote, iclass 33, count 2 2006.239.08:01:38.72#ibcon#about to read 3, iclass 33, count 2 2006.239.08:01:38.75#ibcon#read 3, iclass 33, count 2 2006.239.08:01:38.75#ibcon#about to read 4, iclass 33, count 2 2006.239.08:01:38.75#ibcon#read 4, iclass 33, count 2 2006.239.08:01:38.75#ibcon#about to read 5, iclass 33, count 2 2006.239.08:01:38.75#ibcon#read 5, iclass 33, count 2 2006.239.08:01:38.75#ibcon#about to read 6, iclass 33, count 2 2006.239.08:01:38.75#ibcon#read 6, iclass 33, count 2 2006.239.08:01:38.75#ibcon#end of sib2, iclass 33, count 2 2006.239.08:01:38.75#ibcon#*after write, iclass 33, count 2 2006.239.08:01:38.75#ibcon#*before return 0, iclass 33, count 2 2006.239.08:01:38.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:38.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:38.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.08:01:38.75#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:38.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:38.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:38.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:38.87#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:01:38.87#ibcon#first serial, iclass 33, count 0 2006.239.08:01:38.87#ibcon#enter sib2, iclass 33, count 0 2006.239.08:01:38.87#ibcon#flushed, iclass 33, count 0 2006.239.08:01:38.87#ibcon#about to write, iclass 33, count 0 2006.239.08:01:38.87#ibcon#wrote, iclass 33, count 0 2006.239.08:01:38.87#ibcon#about to read 3, iclass 33, count 0 2006.239.08:01:38.89#ibcon#read 3, iclass 33, count 0 2006.239.08:01:38.89#ibcon#about to read 4, iclass 33, count 0 2006.239.08:01:38.89#ibcon#read 4, iclass 33, count 0 2006.239.08:01:38.89#ibcon#about to read 5, iclass 33, count 0 2006.239.08:01:38.89#ibcon#read 5, iclass 33, count 0 2006.239.08:01:38.89#ibcon#about to read 6, iclass 33, count 0 2006.239.08:01:38.89#ibcon#read 6, iclass 33, count 0 2006.239.08:01:38.89#ibcon#end of sib2, iclass 33, count 0 2006.239.08:01:38.89#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:01:38.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:01:38.89#ibcon#[25=USB\r\n] 2006.239.08:01:38.89#ibcon#*before write, iclass 33, count 0 2006.239.08:01:38.89#ibcon#enter sib2, iclass 33, count 0 2006.239.08:01:38.89#ibcon#flushed, iclass 33, count 0 2006.239.08:01:38.89#ibcon#about to write, iclass 33, count 0 2006.239.08:01:38.89#ibcon#wrote, iclass 33, count 0 2006.239.08:01:38.89#ibcon#about to read 3, iclass 33, count 0 2006.239.08:01:38.92#ibcon#read 3, iclass 33, count 0 2006.239.08:01:38.92#ibcon#about to read 4, iclass 33, count 0 2006.239.08:01:38.92#ibcon#read 4, iclass 33, count 0 2006.239.08:01:38.92#ibcon#about to read 5, iclass 33, count 0 2006.239.08:01:38.92#ibcon#read 5, iclass 33, count 0 2006.239.08:01:38.92#ibcon#about to read 6, iclass 33, count 0 2006.239.08:01:38.92#ibcon#read 6, iclass 33, count 0 2006.239.08:01:38.92#ibcon#end of sib2, iclass 33, count 0 2006.239.08:01:38.92#ibcon#*after write, iclass 33, count 0 2006.239.08:01:38.92#ibcon#*before return 0, iclass 33, count 0 2006.239.08:01:38.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:38.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:38.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:01:38.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:01:38.92$vc4f8/valo=4,832.99 2006.239.08:01:38.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.08:01:38.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.08:01:38.92#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:38.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:38.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:38.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:38.92#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:01:38.92#ibcon#first serial, iclass 35, count 0 2006.239.08:01:38.92#ibcon#enter sib2, iclass 35, count 0 2006.239.08:01:38.92#ibcon#flushed, iclass 35, count 0 2006.239.08:01:38.92#ibcon#about to write, iclass 35, count 0 2006.239.08:01:38.92#ibcon#wrote, iclass 35, count 0 2006.239.08:01:38.92#ibcon#about to read 3, iclass 35, count 0 2006.239.08:01:38.94#ibcon#read 3, iclass 35, count 0 2006.239.08:01:38.94#ibcon#about to read 4, iclass 35, count 0 2006.239.08:01:38.94#ibcon#read 4, iclass 35, count 0 2006.239.08:01:38.94#ibcon#about to read 5, iclass 35, count 0 2006.239.08:01:38.94#ibcon#read 5, iclass 35, count 0 2006.239.08:01:38.94#ibcon#about to read 6, iclass 35, count 0 2006.239.08:01:38.94#ibcon#read 6, iclass 35, count 0 2006.239.08:01:38.94#ibcon#end of sib2, iclass 35, count 0 2006.239.08:01:38.94#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:01:38.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:01:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:01:38.94#ibcon#*before write, iclass 35, count 0 2006.239.08:01:38.94#ibcon#enter sib2, iclass 35, count 0 2006.239.08:01:38.94#ibcon#flushed, iclass 35, count 0 2006.239.08:01:38.94#ibcon#about to write, iclass 35, count 0 2006.239.08:01:38.94#ibcon#wrote, iclass 35, count 0 2006.239.08:01:38.94#ibcon#about to read 3, iclass 35, count 0 2006.239.08:01:38.98#ibcon#read 3, iclass 35, count 0 2006.239.08:01:38.98#ibcon#about to read 4, iclass 35, count 0 2006.239.08:01:38.98#ibcon#read 4, iclass 35, count 0 2006.239.08:01:38.98#ibcon#about to read 5, iclass 35, count 0 2006.239.08:01:38.98#ibcon#read 5, iclass 35, count 0 2006.239.08:01:38.98#ibcon#about to read 6, iclass 35, count 0 2006.239.08:01:38.98#ibcon#read 6, iclass 35, count 0 2006.239.08:01:38.98#ibcon#end of sib2, iclass 35, count 0 2006.239.08:01:38.98#ibcon#*after write, iclass 35, count 0 2006.239.08:01:38.98#ibcon#*before return 0, iclass 35, count 0 2006.239.08:01:38.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:38.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:38.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:01:38.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:01:38.98$vc4f8/va=4,7 2006.239.08:01:38.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.08:01:38.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.08:01:38.98#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:38.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:39.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:39.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:39.04#ibcon#enter wrdev, iclass 37, count 2 2006.239.08:01:39.04#ibcon#first serial, iclass 37, count 2 2006.239.08:01:39.04#ibcon#enter sib2, iclass 37, count 2 2006.239.08:01:39.04#ibcon#flushed, iclass 37, count 2 2006.239.08:01:39.04#ibcon#about to write, iclass 37, count 2 2006.239.08:01:39.04#ibcon#wrote, iclass 37, count 2 2006.239.08:01:39.04#ibcon#about to read 3, iclass 37, count 2 2006.239.08:01:39.06#ibcon#read 3, iclass 37, count 2 2006.239.08:01:39.06#ibcon#about to read 4, iclass 37, count 2 2006.239.08:01:39.06#ibcon#read 4, iclass 37, count 2 2006.239.08:01:39.06#ibcon#about to read 5, iclass 37, count 2 2006.239.08:01:39.06#ibcon#read 5, iclass 37, count 2 2006.239.08:01:39.06#ibcon#about to read 6, iclass 37, count 2 2006.239.08:01:39.06#ibcon#read 6, iclass 37, count 2 2006.239.08:01:39.06#ibcon#end of sib2, iclass 37, count 2 2006.239.08:01:39.06#ibcon#*mode == 0, iclass 37, count 2 2006.239.08:01:39.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.08:01:39.06#ibcon#[25=AT04-07\r\n] 2006.239.08:01:39.06#ibcon#*before write, iclass 37, count 2 2006.239.08:01:39.06#ibcon#enter sib2, iclass 37, count 2 2006.239.08:01:39.06#ibcon#flushed, iclass 37, count 2 2006.239.08:01:39.06#ibcon#about to write, iclass 37, count 2 2006.239.08:01:39.06#ibcon#wrote, iclass 37, count 2 2006.239.08:01:39.06#ibcon#about to read 3, iclass 37, count 2 2006.239.08:01:39.09#ibcon#read 3, iclass 37, count 2 2006.239.08:01:39.09#ibcon#about to read 4, iclass 37, count 2 2006.239.08:01:39.09#ibcon#read 4, iclass 37, count 2 2006.239.08:01:39.09#ibcon#about to read 5, iclass 37, count 2 2006.239.08:01:39.09#ibcon#read 5, iclass 37, count 2 2006.239.08:01:39.09#ibcon#about to read 6, iclass 37, count 2 2006.239.08:01:39.09#ibcon#read 6, iclass 37, count 2 2006.239.08:01:39.09#ibcon#end of sib2, iclass 37, count 2 2006.239.08:01:39.09#ibcon#*after write, iclass 37, count 2 2006.239.08:01:39.09#ibcon#*before return 0, iclass 37, count 2 2006.239.08:01:39.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:39.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:39.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.08:01:39.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:39.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:39.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:39.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:39.21#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:01:39.21#ibcon#first serial, iclass 37, count 0 2006.239.08:01:39.21#ibcon#enter sib2, iclass 37, count 0 2006.239.08:01:39.21#ibcon#flushed, iclass 37, count 0 2006.239.08:01:39.21#ibcon#about to write, iclass 37, count 0 2006.239.08:01:39.21#ibcon#wrote, iclass 37, count 0 2006.239.08:01:39.21#ibcon#about to read 3, iclass 37, count 0 2006.239.08:01:39.23#ibcon#read 3, iclass 37, count 0 2006.239.08:01:39.23#ibcon#about to read 4, iclass 37, count 0 2006.239.08:01:39.23#ibcon#read 4, iclass 37, count 0 2006.239.08:01:39.23#ibcon#about to read 5, iclass 37, count 0 2006.239.08:01:39.23#ibcon#read 5, iclass 37, count 0 2006.239.08:01:39.23#ibcon#about to read 6, iclass 37, count 0 2006.239.08:01:39.23#ibcon#read 6, iclass 37, count 0 2006.239.08:01:39.23#ibcon#end of sib2, iclass 37, count 0 2006.239.08:01:39.23#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:01:39.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:01:39.23#ibcon#[25=USB\r\n] 2006.239.08:01:39.23#ibcon#*before write, iclass 37, count 0 2006.239.08:01:39.23#ibcon#enter sib2, iclass 37, count 0 2006.239.08:01:39.23#ibcon#flushed, iclass 37, count 0 2006.239.08:01:39.23#ibcon#about to write, iclass 37, count 0 2006.239.08:01:39.23#ibcon#wrote, iclass 37, count 0 2006.239.08:01:39.23#ibcon#about to read 3, iclass 37, count 0 2006.239.08:01:39.26#ibcon#read 3, iclass 37, count 0 2006.239.08:01:39.26#ibcon#about to read 4, iclass 37, count 0 2006.239.08:01:39.26#ibcon#read 4, iclass 37, count 0 2006.239.08:01:39.26#ibcon#about to read 5, iclass 37, count 0 2006.239.08:01:39.26#ibcon#read 5, iclass 37, count 0 2006.239.08:01:39.26#ibcon#about to read 6, iclass 37, count 0 2006.239.08:01:39.26#ibcon#read 6, iclass 37, count 0 2006.239.08:01:39.26#ibcon#end of sib2, iclass 37, count 0 2006.239.08:01:39.26#ibcon#*after write, iclass 37, count 0 2006.239.08:01:39.26#ibcon#*before return 0, iclass 37, count 0 2006.239.08:01:39.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:39.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:39.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:01:39.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:01:39.26$vc4f8/valo=5,652.99 2006.239.08:01:39.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:01:39.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:01:39.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:39.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:39.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:39.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:39.26#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:01:39.26#ibcon#first serial, iclass 39, count 0 2006.239.08:01:39.26#ibcon#enter sib2, iclass 39, count 0 2006.239.08:01:39.26#ibcon#flushed, iclass 39, count 0 2006.239.08:01:39.26#ibcon#about to write, iclass 39, count 0 2006.239.08:01:39.26#ibcon#wrote, iclass 39, count 0 2006.239.08:01:39.26#ibcon#about to read 3, iclass 39, count 0 2006.239.08:01:39.28#ibcon#read 3, iclass 39, count 0 2006.239.08:01:39.28#ibcon#about to read 4, iclass 39, count 0 2006.239.08:01:39.28#ibcon#read 4, iclass 39, count 0 2006.239.08:01:39.28#ibcon#about to read 5, iclass 39, count 0 2006.239.08:01:39.28#ibcon#read 5, iclass 39, count 0 2006.239.08:01:39.28#ibcon#about to read 6, iclass 39, count 0 2006.239.08:01:39.28#ibcon#read 6, iclass 39, count 0 2006.239.08:01:39.28#ibcon#end of sib2, iclass 39, count 0 2006.239.08:01:39.28#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:01:39.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:01:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:01:39.28#ibcon#*before write, iclass 39, count 0 2006.239.08:01:39.28#ibcon#enter sib2, iclass 39, count 0 2006.239.08:01:39.28#ibcon#flushed, iclass 39, count 0 2006.239.08:01:39.28#ibcon#about to write, iclass 39, count 0 2006.239.08:01:39.28#ibcon#wrote, iclass 39, count 0 2006.239.08:01:39.28#ibcon#about to read 3, iclass 39, count 0 2006.239.08:01:39.32#ibcon#read 3, iclass 39, count 0 2006.239.08:01:39.32#ibcon#about to read 4, iclass 39, count 0 2006.239.08:01:39.32#ibcon#read 4, iclass 39, count 0 2006.239.08:01:39.32#ibcon#about to read 5, iclass 39, count 0 2006.239.08:01:39.32#ibcon#read 5, iclass 39, count 0 2006.239.08:01:39.32#ibcon#about to read 6, iclass 39, count 0 2006.239.08:01:39.32#ibcon#read 6, iclass 39, count 0 2006.239.08:01:39.32#ibcon#end of sib2, iclass 39, count 0 2006.239.08:01:39.32#ibcon#*after write, iclass 39, count 0 2006.239.08:01:39.32#ibcon#*before return 0, iclass 39, count 0 2006.239.08:01:39.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:39.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:39.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:01:39.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:01:39.32$vc4f8/va=5,8 2006.239.08:01:39.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.08:01:39.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.08:01:39.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:39.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:39.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:39.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:39.38#ibcon#enter wrdev, iclass 3, count 2 2006.239.08:01:39.38#ibcon#first serial, iclass 3, count 2 2006.239.08:01:39.38#ibcon#enter sib2, iclass 3, count 2 2006.239.08:01:39.38#ibcon#flushed, iclass 3, count 2 2006.239.08:01:39.38#ibcon#about to write, iclass 3, count 2 2006.239.08:01:39.38#ibcon#wrote, iclass 3, count 2 2006.239.08:01:39.38#ibcon#about to read 3, iclass 3, count 2 2006.239.08:01:39.40#ibcon#read 3, iclass 3, count 2 2006.239.08:01:39.40#ibcon#about to read 4, iclass 3, count 2 2006.239.08:01:39.40#ibcon#read 4, iclass 3, count 2 2006.239.08:01:39.40#ibcon#about to read 5, iclass 3, count 2 2006.239.08:01:39.40#ibcon#read 5, iclass 3, count 2 2006.239.08:01:39.40#ibcon#about to read 6, iclass 3, count 2 2006.239.08:01:39.40#ibcon#read 6, iclass 3, count 2 2006.239.08:01:39.40#ibcon#end of sib2, iclass 3, count 2 2006.239.08:01:39.40#ibcon#*mode == 0, iclass 3, count 2 2006.239.08:01:39.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.08:01:39.40#ibcon#[25=AT05-08\r\n] 2006.239.08:01:39.40#ibcon#*before write, iclass 3, count 2 2006.239.08:01:39.40#ibcon#enter sib2, iclass 3, count 2 2006.239.08:01:39.40#ibcon#flushed, iclass 3, count 2 2006.239.08:01:39.40#ibcon#about to write, iclass 3, count 2 2006.239.08:01:39.40#ibcon#wrote, iclass 3, count 2 2006.239.08:01:39.40#ibcon#about to read 3, iclass 3, count 2 2006.239.08:01:39.43#ibcon#read 3, iclass 3, count 2 2006.239.08:01:39.43#ibcon#about to read 4, iclass 3, count 2 2006.239.08:01:39.43#ibcon#read 4, iclass 3, count 2 2006.239.08:01:39.43#ibcon#about to read 5, iclass 3, count 2 2006.239.08:01:39.43#ibcon#read 5, iclass 3, count 2 2006.239.08:01:39.43#ibcon#about to read 6, iclass 3, count 2 2006.239.08:01:39.43#ibcon#read 6, iclass 3, count 2 2006.239.08:01:39.43#ibcon#end of sib2, iclass 3, count 2 2006.239.08:01:39.43#ibcon#*after write, iclass 3, count 2 2006.239.08:01:39.43#ibcon#*before return 0, iclass 3, count 2 2006.239.08:01:39.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:39.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:39.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.08:01:39.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:39.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:39.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:39.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:39.55#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:01:39.55#ibcon#first serial, iclass 3, count 0 2006.239.08:01:39.55#ibcon#enter sib2, iclass 3, count 0 2006.239.08:01:39.55#ibcon#flushed, iclass 3, count 0 2006.239.08:01:39.55#ibcon#about to write, iclass 3, count 0 2006.239.08:01:39.55#ibcon#wrote, iclass 3, count 0 2006.239.08:01:39.55#ibcon#about to read 3, iclass 3, count 0 2006.239.08:01:39.57#ibcon#read 3, iclass 3, count 0 2006.239.08:01:39.57#ibcon#about to read 4, iclass 3, count 0 2006.239.08:01:39.57#ibcon#read 4, iclass 3, count 0 2006.239.08:01:39.57#ibcon#about to read 5, iclass 3, count 0 2006.239.08:01:39.57#ibcon#read 5, iclass 3, count 0 2006.239.08:01:39.57#ibcon#about to read 6, iclass 3, count 0 2006.239.08:01:39.57#ibcon#read 6, iclass 3, count 0 2006.239.08:01:39.57#ibcon#end of sib2, iclass 3, count 0 2006.239.08:01:39.57#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:01:39.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:01:39.57#ibcon#[25=USB\r\n] 2006.239.08:01:39.57#ibcon#*before write, iclass 3, count 0 2006.239.08:01:39.57#ibcon#enter sib2, iclass 3, count 0 2006.239.08:01:39.57#ibcon#flushed, iclass 3, count 0 2006.239.08:01:39.57#ibcon#about to write, iclass 3, count 0 2006.239.08:01:39.57#ibcon#wrote, iclass 3, count 0 2006.239.08:01:39.57#ibcon#about to read 3, iclass 3, count 0 2006.239.08:01:39.60#ibcon#read 3, iclass 3, count 0 2006.239.08:01:39.60#ibcon#about to read 4, iclass 3, count 0 2006.239.08:01:39.60#ibcon#read 4, iclass 3, count 0 2006.239.08:01:39.60#ibcon#about to read 5, iclass 3, count 0 2006.239.08:01:39.60#ibcon#read 5, iclass 3, count 0 2006.239.08:01:39.60#ibcon#about to read 6, iclass 3, count 0 2006.239.08:01:39.60#ibcon#read 6, iclass 3, count 0 2006.239.08:01:39.60#ibcon#end of sib2, iclass 3, count 0 2006.239.08:01:39.60#ibcon#*after write, iclass 3, count 0 2006.239.08:01:39.60#ibcon#*before return 0, iclass 3, count 0 2006.239.08:01:39.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:39.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:39.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:01:39.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:01:39.60$vc4f8/valo=6,772.99 2006.239.08:01:39.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:01:39.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:01:39.60#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:39.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:39.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:39.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:39.60#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:01:39.60#ibcon#first serial, iclass 5, count 0 2006.239.08:01:39.60#ibcon#enter sib2, iclass 5, count 0 2006.239.08:01:39.60#ibcon#flushed, iclass 5, count 0 2006.239.08:01:39.60#ibcon#about to write, iclass 5, count 0 2006.239.08:01:39.60#ibcon#wrote, iclass 5, count 0 2006.239.08:01:39.60#ibcon#about to read 3, iclass 5, count 0 2006.239.08:01:39.62#ibcon#read 3, iclass 5, count 0 2006.239.08:01:39.62#ibcon#about to read 4, iclass 5, count 0 2006.239.08:01:39.62#ibcon#read 4, iclass 5, count 0 2006.239.08:01:39.62#ibcon#about to read 5, iclass 5, count 0 2006.239.08:01:39.62#ibcon#read 5, iclass 5, count 0 2006.239.08:01:39.62#ibcon#about to read 6, iclass 5, count 0 2006.239.08:01:39.62#ibcon#read 6, iclass 5, count 0 2006.239.08:01:39.62#ibcon#end of sib2, iclass 5, count 0 2006.239.08:01:39.62#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:01:39.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:01:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:01:39.62#ibcon#*before write, iclass 5, count 0 2006.239.08:01:39.62#ibcon#enter sib2, iclass 5, count 0 2006.239.08:01:39.62#ibcon#flushed, iclass 5, count 0 2006.239.08:01:39.62#ibcon#about to write, iclass 5, count 0 2006.239.08:01:39.62#ibcon#wrote, iclass 5, count 0 2006.239.08:01:39.62#ibcon#about to read 3, iclass 5, count 0 2006.239.08:01:39.66#ibcon#read 3, iclass 5, count 0 2006.239.08:01:39.66#ibcon#about to read 4, iclass 5, count 0 2006.239.08:01:39.66#ibcon#read 4, iclass 5, count 0 2006.239.08:01:39.66#ibcon#about to read 5, iclass 5, count 0 2006.239.08:01:39.66#ibcon#read 5, iclass 5, count 0 2006.239.08:01:39.66#ibcon#about to read 6, iclass 5, count 0 2006.239.08:01:39.66#ibcon#read 6, iclass 5, count 0 2006.239.08:01:39.66#ibcon#end of sib2, iclass 5, count 0 2006.239.08:01:39.66#ibcon#*after write, iclass 5, count 0 2006.239.08:01:39.66#ibcon#*before return 0, iclass 5, count 0 2006.239.08:01:39.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:39.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:39.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:01:39.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:01:39.66$vc4f8/va=6,7 2006.239.08:01:39.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.08:01:39.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.08:01:39.66#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:39.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:01:39.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:01:39.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:01:39.72#ibcon#enter wrdev, iclass 7, count 2 2006.239.08:01:39.72#ibcon#first serial, iclass 7, count 2 2006.239.08:01:39.72#ibcon#enter sib2, iclass 7, count 2 2006.239.08:01:39.72#ibcon#flushed, iclass 7, count 2 2006.239.08:01:39.72#ibcon#about to write, iclass 7, count 2 2006.239.08:01:39.72#ibcon#wrote, iclass 7, count 2 2006.239.08:01:39.72#ibcon#about to read 3, iclass 7, count 2 2006.239.08:01:39.74#ibcon#read 3, iclass 7, count 2 2006.239.08:01:39.74#ibcon#about to read 4, iclass 7, count 2 2006.239.08:01:39.74#ibcon#read 4, iclass 7, count 2 2006.239.08:01:39.74#ibcon#about to read 5, iclass 7, count 2 2006.239.08:01:39.74#ibcon#read 5, iclass 7, count 2 2006.239.08:01:39.74#ibcon#about to read 6, iclass 7, count 2 2006.239.08:01:39.74#ibcon#read 6, iclass 7, count 2 2006.239.08:01:39.74#ibcon#end of sib2, iclass 7, count 2 2006.239.08:01:39.74#ibcon#*mode == 0, iclass 7, count 2 2006.239.08:01:39.74#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.08:01:39.74#ibcon#[25=AT06-07\r\n] 2006.239.08:01:39.74#ibcon#*before write, iclass 7, count 2 2006.239.08:01:39.74#ibcon#enter sib2, iclass 7, count 2 2006.239.08:01:39.74#ibcon#flushed, iclass 7, count 2 2006.239.08:01:39.74#ibcon#about to write, iclass 7, count 2 2006.239.08:01:39.74#ibcon#wrote, iclass 7, count 2 2006.239.08:01:39.74#ibcon#about to read 3, iclass 7, count 2 2006.239.08:01:39.77#ibcon#read 3, iclass 7, count 2 2006.239.08:01:39.77#ibcon#about to read 4, iclass 7, count 2 2006.239.08:01:39.77#ibcon#read 4, iclass 7, count 2 2006.239.08:01:39.77#ibcon#about to read 5, iclass 7, count 2 2006.239.08:01:39.77#ibcon#read 5, iclass 7, count 2 2006.239.08:01:39.77#ibcon#about to read 6, iclass 7, count 2 2006.239.08:01:39.77#ibcon#read 6, iclass 7, count 2 2006.239.08:01:39.77#ibcon#end of sib2, iclass 7, count 2 2006.239.08:01:39.77#ibcon#*after write, iclass 7, count 2 2006.239.08:01:39.77#ibcon#*before return 0, iclass 7, count 2 2006.239.08:01:39.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:01:39.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:01:39.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.08:01:39.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:39.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:01:39.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:01:39.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:01:39.89#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:01:39.89#ibcon#first serial, iclass 7, count 0 2006.239.08:01:39.89#ibcon#enter sib2, iclass 7, count 0 2006.239.08:01:39.89#ibcon#flushed, iclass 7, count 0 2006.239.08:01:39.89#ibcon#about to write, iclass 7, count 0 2006.239.08:01:39.89#ibcon#wrote, iclass 7, count 0 2006.239.08:01:39.89#ibcon#about to read 3, iclass 7, count 0 2006.239.08:01:39.91#ibcon#read 3, iclass 7, count 0 2006.239.08:01:39.91#ibcon#about to read 4, iclass 7, count 0 2006.239.08:01:39.91#ibcon#read 4, iclass 7, count 0 2006.239.08:01:39.91#ibcon#about to read 5, iclass 7, count 0 2006.239.08:01:39.91#ibcon#read 5, iclass 7, count 0 2006.239.08:01:39.91#ibcon#about to read 6, iclass 7, count 0 2006.239.08:01:39.91#ibcon#read 6, iclass 7, count 0 2006.239.08:01:39.91#ibcon#end of sib2, iclass 7, count 0 2006.239.08:01:39.91#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:01:39.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:01:39.91#ibcon#[25=USB\r\n] 2006.239.08:01:39.91#ibcon#*before write, iclass 7, count 0 2006.239.08:01:39.91#ibcon#enter sib2, iclass 7, count 0 2006.239.08:01:39.91#ibcon#flushed, iclass 7, count 0 2006.239.08:01:39.91#ibcon#about to write, iclass 7, count 0 2006.239.08:01:39.91#ibcon#wrote, iclass 7, count 0 2006.239.08:01:39.91#ibcon#about to read 3, iclass 7, count 0 2006.239.08:01:39.94#ibcon#read 3, iclass 7, count 0 2006.239.08:01:39.94#ibcon#about to read 4, iclass 7, count 0 2006.239.08:01:39.94#ibcon#read 4, iclass 7, count 0 2006.239.08:01:39.94#ibcon#about to read 5, iclass 7, count 0 2006.239.08:01:39.94#ibcon#read 5, iclass 7, count 0 2006.239.08:01:39.94#ibcon#about to read 6, iclass 7, count 0 2006.239.08:01:39.94#ibcon#read 6, iclass 7, count 0 2006.239.08:01:39.94#ibcon#end of sib2, iclass 7, count 0 2006.239.08:01:39.94#ibcon#*after write, iclass 7, count 0 2006.239.08:01:39.94#ibcon#*before return 0, iclass 7, count 0 2006.239.08:01:39.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:01:39.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:01:39.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:01:39.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:01:39.94$vc4f8/valo=7,832.99 2006.239.08:01:39.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.08:01:39.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.08:01:39.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:39.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:01:39.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:01:39.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:01:39.94#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:01:39.94#ibcon#first serial, iclass 11, count 0 2006.239.08:01:39.94#ibcon#enter sib2, iclass 11, count 0 2006.239.08:01:39.94#ibcon#flushed, iclass 11, count 0 2006.239.08:01:39.94#ibcon#about to write, iclass 11, count 0 2006.239.08:01:39.94#ibcon#wrote, iclass 11, count 0 2006.239.08:01:39.94#ibcon#about to read 3, iclass 11, count 0 2006.239.08:01:39.96#ibcon#read 3, iclass 11, count 0 2006.239.08:01:39.96#ibcon#about to read 4, iclass 11, count 0 2006.239.08:01:39.96#ibcon#read 4, iclass 11, count 0 2006.239.08:01:39.96#ibcon#about to read 5, iclass 11, count 0 2006.239.08:01:39.96#ibcon#read 5, iclass 11, count 0 2006.239.08:01:39.96#ibcon#about to read 6, iclass 11, count 0 2006.239.08:01:39.96#ibcon#read 6, iclass 11, count 0 2006.239.08:01:39.96#ibcon#end of sib2, iclass 11, count 0 2006.239.08:01:39.96#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:01:39.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:01:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:01:39.96#ibcon#*before write, iclass 11, count 0 2006.239.08:01:39.96#ibcon#enter sib2, iclass 11, count 0 2006.239.08:01:39.96#ibcon#flushed, iclass 11, count 0 2006.239.08:01:39.96#ibcon#about to write, iclass 11, count 0 2006.239.08:01:39.96#ibcon#wrote, iclass 11, count 0 2006.239.08:01:39.96#ibcon#about to read 3, iclass 11, count 0 2006.239.08:01:40.00#ibcon#read 3, iclass 11, count 0 2006.239.08:01:40.00#ibcon#about to read 4, iclass 11, count 0 2006.239.08:01:40.00#ibcon#read 4, iclass 11, count 0 2006.239.08:01:40.00#ibcon#about to read 5, iclass 11, count 0 2006.239.08:01:40.00#ibcon#read 5, iclass 11, count 0 2006.239.08:01:40.00#ibcon#about to read 6, iclass 11, count 0 2006.239.08:01:40.00#ibcon#read 6, iclass 11, count 0 2006.239.08:01:40.00#ibcon#end of sib2, iclass 11, count 0 2006.239.08:01:40.00#ibcon#*after write, iclass 11, count 0 2006.239.08:01:40.00#ibcon#*before return 0, iclass 11, count 0 2006.239.08:01:40.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:01:40.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:01:40.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:01:40.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:01:40.00$vc4f8/va=7,7 2006.239.08:01:40.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.08:01:40.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.08:01:40.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:40.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:01:40.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:01:40.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:01:40.06#ibcon#enter wrdev, iclass 13, count 2 2006.239.08:01:40.06#ibcon#first serial, iclass 13, count 2 2006.239.08:01:40.06#ibcon#enter sib2, iclass 13, count 2 2006.239.08:01:40.06#ibcon#flushed, iclass 13, count 2 2006.239.08:01:40.06#ibcon#about to write, iclass 13, count 2 2006.239.08:01:40.06#ibcon#wrote, iclass 13, count 2 2006.239.08:01:40.06#ibcon#about to read 3, iclass 13, count 2 2006.239.08:01:40.08#ibcon#read 3, iclass 13, count 2 2006.239.08:01:40.08#ibcon#about to read 4, iclass 13, count 2 2006.239.08:01:40.08#ibcon#read 4, iclass 13, count 2 2006.239.08:01:40.08#ibcon#about to read 5, iclass 13, count 2 2006.239.08:01:40.08#ibcon#read 5, iclass 13, count 2 2006.239.08:01:40.08#ibcon#about to read 6, iclass 13, count 2 2006.239.08:01:40.08#ibcon#read 6, iclass 13, count 2 2006.239.08:01:40.08#ibcon#end of sib2, iclass 13, count 2 2006.239.08:01:40.08#ibcon#*mode == 0, iclass 13, count 2 2006.239.08:01:40.08#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.08:01:40.08#ibcon#[25=AT07-07\r\n] 2006.239.08:01:40.08#ibcon#*before write, iclass 13, count 2 2006.239.08:01:40.08#ibcon#enter sib2, iclass 13, count 2 2006.239.08:01:40.08#ibcon#flushed, iclass 13, count 2 2006.239.08:01:40.08#ibcon#about to write, iclass 13, count 2 2006.239.08:01:40.08#ibcon#wrote, iclass 13, count 2 2006.239.08:01:40.08#ibcon#about to read 3, iclass 13, count 2 2006.239.08:01:40.11#ibcon#read 3, iclass 13, count 2 2006.239.08:01:40.11#ibcon#about to read 4, iclass 13, count 2 2006.239.08:01:40.11#ibcon#read 4, iclass 13, count 2 2006.239.08:01:40.11#ibcon#about to read 5, iclass 13, count 2 2006.239.08:01:40.11#ibcon#read 5, iclass 13, count 2 2006.239.08:01:40.11#ibcon#about to read 6, iclass 13, count 2 2006.239.08:01:40.11#ibcon#read 6, iclass 13, count 2 2006.239.08:01:40.11#ibcon#end of sib2, iclass 13, count 2 2006.239.08:01:40.11#ibcon#*after write, iclass 13, count 2 2006.239.08:01:40.11#ibcon#*before return 0, iclass 13, count 2 2006.239.08:01:40.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:01:40.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:01:40.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.08:01:40.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:40.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:01:40.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:01:40.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:01:40.23#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:01:40.23#ibcon#first serial, iclass 13, count 0 2006.239.08:01:40.23#ibcon#enter sib2, iclass 13, count 0 2006.239.08:01:40.23#ibcon#flushed, iclass 13, count 0 2006.239.08:01:40.23#ibcon#about to write, iclass 13, count 0 2006.239.08:01:40.23#ibcon#wrote, iclass 13, count 0 2006.239.08:01:40.23#ibcon#about to read 3, iclass 13, count 0 2006.239.08:01:40.25#ibcon#read 3, iclass 13, count 0 2006.239.08:01:40.25#ibcon#about to read 4, iclass 13, count 0 2006.239.08:01:40.25#ibcon#read 4, iclass 13, count 0 2006.239.08:01:40.25#ibcon#about to read 5, iclass 13, count 0 2006.239.08:01:40.25#ibcon#read 5, iclass 13, count 0 2006.239.08:01:40.25#ibcon#about to read 6, iclass 13, count 0 2006.239.08:01:40.25#ibcon#read 6, iclass 13, count 0 2006.239.08:01:40.25#ibcon#end of sib2, iclass 13, count 0 2006.239.08:01:40.25#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:01:40.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:01:40.25#ibcon#[25=USB\r\n] 2006.239.08:01:40.25#ibcon#*before write, iclass 13, count 0 2006.239.08:01:40.25#ibcon#enter sib2, iclass 13, count 0 2006.239.08:01:40.25#ibcon#flushed, iclass 13, count 0 2006.239.08:01:40.25#ibcon#about to write, iclass 13, count 0 2006.239.08:01:40.25#ibcon#wrote, iclass 13, count 0 2006.239.08:01:40.25#ibcon#about to read 3, iclass 13, count 0 2006.239.08:01:40.28#ibcon#read 3, iclass 13, count 0 2006.239.08:01:40.28#ibcon#about to read 4, iclass 13, count 0 2006.239.08:01:40.28#ibcon#read 4, iclass 13, count 0 2006.239.08:01:40.28#ibcon#about to read 5, iclass 13, count 0 2006.239.08:01:40.28#ibcon#read 5, iclass 13, count 0 2006.239.08:01:40.28#ibcon#about to read 6, iclass 13, count 0 2006.239.08:01:40.28#ibcon#read 6, iclass 13, count 0 2006.239.08:01:40.28#ibcon#end of sib2, iclass 13, count 0 2006.239.08:01:40.28#ibcon#*after write, iclass 13, count 0 2006.239.08:01:40.28#ibcon#*before return 0, iclass 13, count 0 2006.239.08:01:40.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:01:40.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:01:40.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:01:40.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:01:40.28$vc4f8/valo=8,852.99 2006.239.08:01:40.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.08:01:40.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.08:01:40.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:40.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:01:40.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:01:40.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:01:40.28#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:01:40.28#ibcon#first serial, iclass 15, count 0 2006.239.08:01:40.28#ibcon#enter sib2, iclass 15, count 0 2006.239.08:01:40.28#ibcon#flushed, iclass 15, count 0 2006.239.08:01:40.28#ibcon#about to write, iclass 15, count 0 2006.239.08:01:40.28#ibcon#wrote, iclass 15, count 0 2006.239.08:01:40.28#ibcon#about to read 3, iclass 15, count 0 2006.239.08:01:40.30#ibcon#read 3, iclass 15, count 0 2006.239.08:01:40.30#ibcon#about to read 4, iclass 15, count 0 2006.239.08:01:40.30#ibcon#read 4, iclass 15, count 0 2006.239.08:01:40.30#ibcon#about to read 5, iclass 15, count 0 2006.239.08:01:40.30#ibcon#read 5, iclass 15, count 0 2006.239.08:01:40.30#ibcon#about to read 6, iclass 15, count 0 2006.239.08:01:40.30#ibcon#read 6, iclass 15, count 0 2006.239.08:01:40.30#ibcon#end of sib2, iclass 15, count 0 2006.239.08:01:40.30#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:01:40.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:01:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:01:40.30#ibcon#*before write, iclass 15, count 0 2006.239.08:01:40.30#ibcon#enter sib2, iclass 15, count 0 2006.239.08:01:40.30#ibcon#flushed, iclass 15, count 0 2006.239.08:01:40.30#ibcon#about to write, iclass 15, count 0 2006.239.08:01:40.30#ibcon#wrote, iclass 15, count 0 2006.239.08:01:40.30#ibcon#about to read 3, iclass 15, count 0 2006.239.08:01:40.34#ibcon#read 3, iclass 15, count 0 2006.239.08:01:40.34#ibcon#about to read 4, iclass 15, count 0 2006.239.08:01:40.34#ibcon#read 4, iclass 15, count 0 2006.239.08:01:40.34#ibcon#about to read 5, iclass 15, count 0 2006.239.08:01:40.34#ibcon#read 5, iclass 15, count 0 2006.239.08:01:40.34#ibcon#about to read 6, iclass 15, count 0 2006.239.08:01:40.34#ibcon#read 6, iclass 15, count 0 2006.239.08:01:40.34#ibcon#end of sib2, iclass 15, count 0 2006.239.08:01:40.34#ibcon#*after write, iclass 15, count 0 2006.239.08:01:40.34#ibcon#*before return 0, iclass 15, count 0 2006.239.08:01:40.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:01:40.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:01:40.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:01:40.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:01:40.34$vc4f8/va=8,7 2006.239.08:01:40.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.08:01:40.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.08:01:40.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:40.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:01:40.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:01:40.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:01:40.40#ibcon#enter wrdev, iclass 17, count 2 2006.239.08:01:40.40#ibcon#first serial, iclass 17, count 2 2006.239.08:01:40.40#ibcon#enter sib2, iclass 17, count 2 2006.239.08:01:40.40#ibcon#flushed, iclass 17, count 2 2006.239.08:01:40.40#ibcon#about to write, iclass 17, count 2 2006.239.08:01:40.40#ibcon#wrote, iclass 17, count 2 2006.239.08:01:40.40#ibcon#about to read 3, iclass 17, count 2 2006.239.08:01:40.42#ibcon#read 3, iclass 17, count 2 2006.239.08:01:40.42#ibcon#about to read 4, iclass 17, count 2 2006.239.08:01:40.42#ibcon#read 4, iclass 17, count 2 2006.239.08:01:40.42#ibcon#about to read 5, iclass 17, count 2 2006.239.08:01:40.42#ibcon#read 5, iclass 17, count 2 2006.239.08:01:40.42#ibcon#about to read 6, iclass 17, count 2 2006.239.08:01:40.42#ibcon#read 6, iclass 17, count 2 2006.239.08:01:40.42#ibcon#end of sib2, iclass 17, count 2 2006.239.08:01:40.42#ibcon#*mode == 0, iclass 17, count 2 2006.239.08:01:40.42#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.08:01:40.42#ibcon#[25=AT08-07\r\n] 2006.239.08:01:40.42#ibcon#*before write, iclass 17, count 2 2006.239.08:01:40.42#ibcon#enter sib2, iclass 17, count 2 2006.239.08:01:40.42#ibcon#flushed, iclass 17, count 2 2006.239.08:01:40.42#ibcon#about to write, iclass 17, count 2 2006.239.08:01:40.42#ibcon#wrote, iclass 17, count 2 2006.239.08:01:40.42#ibcon#about to read 3, iclass 17, count 2 2006.239.08:01:40.45#ibcon#read 3, iclass 17, count 2 2006.239.08:01:40.45#ibcon#about to read 4, iclass 17, count 2 2006.239.08:01:40.45#ibcon#read 4, iclass 17, count 2 2006.239.08:01:40.45#ibcon#about to read 5, iclass 17, count 2 2006.239.08:01:40.45#ibcon#read 5, iclass 17, count 2 2006.239.08:01:40.45#ibcon#about to read 6, iclass 17, count 2 2006.239.08:01:40.45#ibcon#read 6, iclass 17, count 2 2006.239.08:01:40.45#ibcon#end of sib2, iclass 17, count 2 2006.239.08:01:40.45#ibcon#*after write, iclass 17, count 2 2006.239.08:01:40.45#ibcon#*before return 0, iclass 17, count 2 2006.239.08:01:40.45#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:01:40.45#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:01:40.45#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.08:01:40.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:40.45#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:01:40.57#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:01:40.57#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:01:40.57#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:01:40.57#ibcon#first serial, iclass 17, count 0 2006.239.08:01:40.57#ibcon#enter sib2, iclass 17, count 0 2006.239.08:01:40.57#ibcon#flushed, iclass 17, count 0 2006.239.08:01:40.57#ibcon#about to write, iclass 17, count 0 2006.239.08:01:40.57#ibcon#wrote, iclass 17, count 0 2006.239.08:01:40.57#ibcon#about to read 3, iclass 17, count 0 2006.239.08:01:40.59#ibcon#read 3, iclass 17, count 0 2006.239.08:01:40.59#ibcon#about to read 4, iclass 17, count 0 2006.239.08:01:40.59#ibcon#read 4, iclass 17, count 0 2006.239.08:01:40.59#ibcon#about to read 5, iclass 17, count 0 2006.239.08:01:40.59#ibcon#read 5, iclass 17, count 0 2006.239.08:01:40.59#ibcon#about to read 6, iclass 17, count 0 2006.239.08:01:40.59#ibcon#read 6, iclass 17, count 0 2006.239.08:01:40.59#ibcon#end of sib2, iclass 17, count 0 2006.239.08:01:40.59#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:01:40.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:01:40.59#ibcon#[25=USB\r\n] 2006.239.08:01:40.59#ibcon#*before write, iclass 17, count 0 2006.239.08:01:40.59#ibcon#enter sib2, iclass 17, count 0 2006.239.08:01:40.59#ibcon#flushed, iclass 17, count 0 2006.239.08:01:40.59#ibcon#about to write, iclass 17, count 0 2006.239.08:01:40.59#ibcon#wrote, iclass 17, count 0 2006.239.08:01:40.59#ibcon#about to read 3, iclass 17, count 0 2006.239.08:01:40.62#ibcon#read 3, iclass 17, count 0 2006.239.08:01:40.62#ibcon#about to read 4, iclass 17, count 0 2006.239.08:01:40.62#ibcon#read 4, iclass 17, count 0 2006.239.08:01:40.62#ibcon#about to read 5, iclass 17, count 0 2006.239.08:01:40.62#ibcon#read 5, iclass 17, count 0 2006.239.08:01:40.62#ibcon#about to read 6, iclass 17, count 0 2006.239.08:01:40.62#ibcon#read 6, iclass 17, count 0 2006.239.08:01:40.62#ibcon#end of sib2, iclass 17, count 0 2006.239.08:01:40.62#ibcon#*after write, iclass 17, count 0 2006.239.08:01:40.62#ibcon#*before return 0, iclass 17, count 0 2006.239.08:01:40.62#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:01:40.62#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:01:40.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:01:40.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:01:40.62$vc4f8/vblo=1,632.99 2006.239.08:01:40.62#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.08:01:40.62#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.08:01:40.62#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:40.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:01:40.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:01:40.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:01:40.62#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:01:40.62#ibcon#first serial, iclass 19, count 0 2006.239.08:01:40.62#ibcon#enter sib2, iclass 19, count 0 2006.239.08:01:40.62#ibcon#flushed, iclass 19, count 0 2006.239.08:01:40.62#ibcon#about to write, iclass 19, count 0 2006.239.08:01:40.62#ibcon#wrote, iclass 19, count 0 2006.239.08:01:40.62#ibcon#about to read 3, iclass 19, count 0 2006.239.08:01:40.64#ibcon#read 3, iclass 19, count 0 2006.239.08:01:40.64#ibcon#about to read 4, iclass 19, count 0 2006.239.08:01:40.64#ibcon#read 4, iclass 19, count 0 2006.239.08:01:40.64#ibcon#about to read 5, iclass 19, count 0 2006.239.08:01:40.64#ibcon#read 5, iclass 19, count 0 2006.239.08:01:40.64#ibcon#about to read 6, iclass 19, count 0 2006.239.08:01:40.64#ibcon#read 6, iclass 19, count 0 2006.239.08:01:40.64#ibcon#end of sib2, iclass 19, count 0 2006.239.08:01:40.64#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:01:40.64#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:01:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:01:40.64#ibcon#*before write, iclass 19, count 0 2006.239.08:01:40.64#ibcon#enter sib2, iclass 19, count 0 2006.239.08:01:40.64#ibcon#flushed, iclass 19, count 0 2006.239.08:01:40.64#ibcon#about to write, iclass 19, count 0 2006.239.08:01:40.64#ibcon#wrote, iclass 19, count 0 2006.239.08:01:40.64#ibcon#about to read 3, iclass 19, count 0 2006.239.08:01:40.68#ibcon#read 3, iclass 19, count 0 2006.239.08:01:40.68#ibcon#about to read 4, iclass 19, count 0 2006.239.08:01:40.68#ibcon#read 4, iclass 19, count 0 2006.239.08:01:40.68#ibcon#about to read 5, iclass 19, count 0 2006.239.08:01:40.68#ibcon#read 5, iclass 19, count 0 2006.239.08:01:40.68#ibcon#about to read 6, iclass 19, count 0 2006.239.08:01:40.68#ibcon#read 6, iclass 19, count 0 2006.239.08:01:40.68#ibcon#end of sib2, iclass 19, count 0 2006.239.08:01:40.68#ibcon#*after write, iclass 19, count 0 2006.239.08:01:40.68#ibcon#*before return 0, iclass 19, count 0 2006.239.08:01:40.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:01:40.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:01:40.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:01:40.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:01:40.68$vc4f8/vb=1,4 2006.239.08:01:40.68#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.08:01:40.68#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.08:01:40.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:40.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:01:40.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:01:40.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:01:40.68#ibcon#enter wrdev, iclass 21, count 2 2006.239.08:01:40.68#ibcon#first serial, iclass 21, count 2 2006.239.08:01:40.68#ibcon#enter sib2, iclass 21, count 2 2006.239.08:01:40.68#ibcon#flushed, iclass 21, count 2 2006.239.08:01:40.68#ibcon#about to write, iclass 21, count 2 2006.239.08:01:40.68#ibcon#wrote, iclass 21, count 2 2006.239.08:01:40.68#ibcon#about to read 3, iclass 21, count 2 2006.239.08:01:40.70#ibcon#read 3, iclass 21, count 2 2006.239.08:01:40.70#ibcon#about to read 4, iclass 21, count 2 2006.239.08:01:40.70#ibcon#read 4, iclass 21, count 2 2006.239.08:01:40.70#ibcon#about to read 5, iclass 21, count 2 2006.239.08:01:40.70#ibcon#read 5, iclass 21, count 2 2006.239.08:01:40.70#ibcon#about to read 6, iclass 21, count 2 2006.239.08:01:40.70#ibcon#read 6, iclass 21, count 2 2006.239.08:01:40.70#ibcon#end of sib2, iclass 21, count 2 2006.239.08:01:40.70#ibcon#*mode == 0, iclass 21, count 2 2006.239.08:01:40.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.08:01:40.70#ibcon#[27=AT01-04\r\n] 2006.239.08:01:40.70#ibcon#*before write, iclass 21, count 2 2006.239.08:01:40.70#ibcon#enter sib2, iclass 21, count 2 2006.239.08:01:40.70#ibcon#flushed, iclass 21, count 2 2006.239.08:01:40.70#ibcon#about to write, iclass 21, count 2 2006.239.08:01:40.70#ibcon#wrote, iclass 21, count 2 2006.239.08:01:40.70#ibcon#about to read 3, iclass 21, count 2 2006.239.08:01:40.73#ibcon#read 3, iclass 21, count 2 2006.239.08:01:40.73#ibcon#about to read 4, iclass 21, count 2 2006.239.08:01:40.73#ibcon#read 4, iclass 21, count 2 2006.239.08:01:40.73#ibcon#about to read 5, iclass 21, count 2 2006.239.08:01:40.73#ibcon#read 5, iclass 21, count 2 2006.239.08:01:40.73#ibcon#about to read 6, iclass 21, count 2 2006.239.08:01:40.73#ibcon#read 6, iclass 21, count 2 2006.239.08:01:40.73#ibcon#end of sib2, iclass 21, count 2 2006.239.08:01:40.73#ibcon#*after write, iclass 21, count 2 2006.239.08:01:40.73#ibcon#*before return 0, iclass 21, count 2 2006.239.08:01:40.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:01:40.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:01:40.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.08:01:40.73#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:40.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:01:40.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:01:40.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:01:40.85#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:01:40.85#ibcon#first serial, iclass 21, count 0 2006.239.08:01:40.85#ibcon#enter sib2, iclass 21, count 0 2006.239.08:01:40.85#ibcon#flushed, iclass 21, count 0 2006.239.08:01:40.85#ibcon#about to write, iclass 21, count 0 2006.239.08:01:40.85#ibcon#wrote, iclass 21, count 0 2006.239.08:01:40.85#ibcon#about to read 3, iclass 21, count 0 2006.239.08:01:40.87#ibcon#read 3, iclass 21, count 0 2006.239.08:01:40.87#ibcon#about to read 4, iclass 21, count 0 2006.239.08:01:40.87#ibcon#read 4, iclass 21, count 0 2006.239.08:01:40.87#ibcon#about to read 5, iclass 21, count 0 2006.239.08:01:40.87#ibcon#read 5, iclass 21, count 0 2006.239.08:01:40.87#ibcon#about to read 6, iclass 21, count 0 2006.239.08:01:40.87#ibcon#read 6, iclass 21, count 0 2006.239.08:01:40.87#ibcon#end of sib2, iclass 21, count 0 2006.239.08:01:40.87#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:01:40.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:01:40.87#ibcon#[27=USB\r\n] 2006.239.08:01:40.87#ibcon#*before write, iclass 21, count 0 2006.239.08:01:40.87#ibcon#enter sib2, iclass 21, count 0 2006.239.08:01:40.87#ibcon#flushed, iclass 21, count 0 2006.239.08:01:40.87#ibcon#about to write, iclass 21, count 0 2006.239.08:01:40.87#ibcon#wrote, iclass 21, count 0 2006.239.08:01:40.87#ibcon#about to read 3, iclass 21, count 0 2006.239.08:01:40.90#ibcon#read 3, iclass 21, count 0 2006.239.08:01:40.90#ibcon#about to read 4, iclass 21, count 0 2006.239.08:01:40.90#ibcon#read 4, iclass 21, count 0 2006.239.08:01:40.90#ibcon#about to read 5, iclass 21, count 0 2006.239.08:01:40.90#ibcon#read 5, iclass 21, count 0 2006.239.08:01:40.90#ibcon#about to read 6, iclass 21, count 0 2006.239.08:01:40.90#ibcon#read 6, iclass 21, count 0 2006.239.08:01:40.90#ibcon#end of sib2, iclass 21, count 0 2006.239.08:01:40.90#ibcon#*after write, iclass 21, count 0 2006.239.08:01:40.90#ibcon#*before return 0, iclass 21, count 0 2006.239.08:01:40.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:01:40.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:01:40.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:01:40.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:01:40.90$vc4f8/vblo=2,640.99 2006.239.08:01:40.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.08:01:40.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.08:01:40.90#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:40.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:40.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:40.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:40.90#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:01:40.90#ibcon#first serial, iclass 23, count 0 2006.239.08:01:40.90#ibcon#enter sib2, iclass 23, count 0 2006.239.08:01:40.90#ibcon#flushed, iclass 23, count 0 2006.239.08:01:40.90#ibcon#about to write, iclass 23, count 0 2006.239.08:01:40.90#ibcon#wrote, iclass 23, count 0 2006.239.08:01:40.90#ibcon#about to read 3, iclass 23, count 0 2006.239.08:01:40.92#ibcon#read 3, iclass 23, count 0 2006.239.08:01:40.92#ibcon#about to read 4, iclass 23, count 0 2006.239.08:01:40.92#ibcon#read 4, iclass 23, count 0 2006.239.08:01:40.92#ibcon#about to read 5, iclass 23, count 0 2006.239.08:01:40.92#ibcon#read 5, iclass 23, count 0 2006.239.08:01:40.92#ibcon#about to read 6, iclass 23, count 0 2006.239.08:01:40.92#ibcon#read 6, iclass 23, count 0 2006.239.08:01:40.92#ibcon#end of sib2, iclass 23, count 0 2006.239.08:01:40.92#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:01:40.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:01:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:01:40.92#ibcon#*before write, iclass 23, count 0 2006.239.08:01:40.92#ibcon#enter sib2, iclass 23, count 0 2006.239.08:01:40.92#ibcon#flushed, iclass 23, count 0 2006.239.08:01:40.92#ibcon#about to write, iclass 23, count 0 2006.239.08:01:40.92#ibcon#wrote, iclass 23, count 0 2006.239.08:01:40.92#ibcon#about to read 3, iclass 23, count 0 2006.239.08:01:40.96#ibcon#read 3, iclass 23, count 0 2006.239.08:01:40.96#ibcon#about to read 4, iclass 23, count 0 2006.239.08:01:40.96#ibcon#read 4, iclass 23, count 0 2006.239.08:01:40.96#ibcon#about to read 5, iclass 23, count 0 2006.239.08:01:40.96#ibcon#read 5, iclass 23, count 0 2006.239.08:01:40.96#ibcon#about to read 6, iclass 23, count 0 2006.239.08:01:40.96#ibcon#read 6, iclass 23, count 0 2006.239.08:01:40.96#ibcon#end of sib2, iclass 23, count 0 2006.239.08:01:40.96#ibcon#*after write, iclass 23, count 0 2006.239.08:01:40.96#ibcon#*before return 0, iclass 23, count 0 2006.239.08:01:40.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:40.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:01:40.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:01:40.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:01:40.96$vc4f8/vb=2,4 2006.239.08:01:40.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.08:01:40.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.08:01:40.96#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:40.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:41.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:41.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:41.02#ibcon#enter wrdev, iclass 25, count 2 2006.239.08:01:41.02#ibcon#first serial, iclass 25, count 2 2006.239.08:01:41.02#ibcon#enter sib2, iclass 25, count 2 2006.239.08:01:41.02#ibcon#flushed, iclass 25, count 2 2006.239.08:01:41.02#ibcon#about to write, iclass 25, count 2 2006.239.08:01:41.02#ibcon#wrote, iclass 25, count 2 2006.239.08:01:41.02#ibcon#about to read 3, iclass 25, count 2 2006.239.08:01:41.04#ibcon#read 3, iclass 25, count 2 2006.239.08:01:41.04#ibcon#about to read 4, iclass 25, count 2 2006.239.08:01:41.04#ibcon#read 4, iclass 25, count 2 2006.239.08:01:41.04#ibcon#about to read 5, iclass 25, count 2 2006.239.08:01:41.04#ibcon#read 5, iclass 25, count 2 2006.239.08:01:41.04#ibcon#about to read 6, iclass 25, count 2 2006.239.08:01:41.04#ibcon#read 6, iclass 25, count 2 2006.239.08:01:41.04#ibcon#end of sib2, iclass 25, count 2 2006.239.08:01:41.04#ibcon#*mode == 0, iclass 25, count 2 2006.239.08:01:41.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.08:01:41.04#ibcon#[27=AT02-04\r\n] 2006.239.08:01:41.04#ibcon#*before write, iclass 25, count 2 2006.239.08:01:41.04#ibcon#enter sib2, iclass 25, count 2 2006.239.08:01:41.04#ibcon#flushed, iclass 25, count 2 2006.239.08:01:41.04#ibcon#about to write, iclass 25, count 2 2006.239.08:01:41.04#ibcon#wrote, iclass 25, count 2 2006.239.08:01:41.04#ibcon#about to read 3, iclass 25, count 2 2006.239.08:01:41.07#ibcon#read 3, iclass 25, count 2 2006.239.08:01:41.07#ibcon#about to read 4, iclass 25, count 2 2006.239.08:01:41.07#ibcon#read 4, iclass 25, count 2 2006.239.08:01:41.07#ibcon#about to read 5, iclass 25, count 2 2006.239.08:01:41.07#ibcon#read 5, iclass 25, count 2 2006.239.08:01:41.07#ibcon#about to read 6, iclass 25, count 2 2006.239.08:01:41.07#ibcon#read 6, iclass 25, count 2 2006.239.08:01:41.07#ibcon#end of sib2, iclass 25, count 2 2006.239.08:01:41.07#ibcon#*after write, iclass 25, count 2 2006.239.08:01:41.07#ibcon#*before return 0, iclass 25, count 2 2006.239.08:01:41.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:41.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:01:41.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.08:01:41.07#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:41.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:41.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:41.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:41.19#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:01:41.19#ibcon#first serial, iclass 25, count 0 2006.239.08:01:41.19#ibcon#enter sib2, iclass 25, count 0 2006.239.08:01:41.19#ibcon#flushed, iclass 25, count 0 2006.239.08:01:41.19#ibcon#about to write, iclass 25, count 0 2006.239.08:01:41.19#ibcon#wrote, iclass 25, count 0 2006.239.08:01:41.19#ibcon#about to read 3, iclass 25, count 0 2006.239.08:01:41.21#ibcon#read 3, iclass 25, count 0 2006.239.08:01:41.21#ibcon#about to read 4, iclass 25, count 0 2006.239.08:01:41.21#ibcon#read 4, iclass 25, count 0 2006.239.08:01:41.21#ibcon#about to read 5, iclass 25, count 0 2006.239.08:01:41.21#ibcon#read 5, iclass 25, count 0 2006.239.08:01:41.21#ibcon#about to read 6, iclass 25, count 0 2006.239.08:01:41.21#ibcon#read 6, iclass 25, count 0 2006.239.08:01:41.21#ibcon#end of sib2, iclass 25, count 0 2006.239.08:01:41.21#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:01:41.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:01:41.21#ibcon#[27=USB\r\n] 2006.239.08:01:41.21#ibcon#*before write, iclass 25, count 0 2006.239.08:01:41.21#ibcon#enter sib2, iclass 25, count 0 2006.239.08:01:41.21#ibcon#flushed, iclass 25, count 0 2006.239.08:01:41.21#ibcon#about to write, iclass 25, count 0 2006.239.08:01:41.21#ibcon#wrote, iclass 25, count 0 2006.239.08:01:41.21#ibcon#about to read 3, iclass 25, count 0 2006.239.08:01:41.24#ibcon#read 3, iclass 25, count 0 2006.239.08:01:41.24#ibcon#about to read 4, iclass 25, count 0 2006.239.08:01:41.24#ibcon#read 4, iclass 25, count 0 2006.239.08:01:41.24#ibcon#about to read 5, iclass 25, count 0 2006.239.08:01:41.24#ibcon#read 5, iclass 25, count 0 2006.239.08:01:41.24#ibcon#about to read 6, iclass 25, count 0 2006.239.08:01:41.24#ibcon#read 6, iclass 25, count 0 2006.239.08:01:41.24#ibcon#end of sib2, iclass 25, count 0 2006.239.08:01:41.24#ibcon#*after write, iclass 25, count 0 2006.239.08:01:41.24#ibcon#*before return 0, iclass 25, count 0 2006.239.08:01:41.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:41.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:01:41.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:01:41.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:01:41.24$vc4f8/vblo=3,656.99 2006.239.08:01:41.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.08:01:41.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.08:01:41.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:41.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:41.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:41.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:41.24#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:01:41.24#ibcon#first serial, iclass 27, count 0 2006.239.08:01:41.24#ibcon#enter sib2, iclass 27, count 0 2006.239.08:01:41.24#ibcon#flushed, iclass 27, count 0 2006.239.08:01:41.24#ibcon#about to write, iclass 27, count 0 2006.239.08:01:41.24#ibcon#wrote, iclass 27, count 0 2006.239.08:01:41.24#ibcon#about to read 3, iclass 27, count 0 2006.239.08:01:41.26#ibcon#read 3, iclass 27, count 0 2006.239.08:01:41.26#ibcon#about to read 4, iclass 27, count 0 2006.239.08:01:41.26#ibcon#read 4, iclass 27, count 0 2006.239.08:01:41.26#ibcon#about to read 5, iclass 27, count 0 2006.239.08:01:41.26#ibcon#read 5, iclass 27, count 0 2006.239.08:01:41.26#ibcon#about to read 6, iclass 27, count 0 2006.239.08:01:41.26#ibcon#read 6, iclass 27, count 0 2006.239.08:01:41.26#ibcon#end of sib2, iclass 27, count 0 2006.239.08:01:41.26#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:01:41.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:01:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:01:41.26#ibcon#*before write, iclass 27, count 0 2006.239.08:01:41.26#ibcon#enter sib2, iclass 27, count 0 2006.239.08:01:41.26#ibcon#flushed, iclass 27, count 0 2006.239.08:01:41.26#ibcon#about to write, iclass 27, count 0 2006.239.08:01:41.26#ibcon#wrote, iclass 27, count 0 2006.239.08:01:41.26#ibcon#about to read 3, iclass 27, count 0 2006.239.08:01:41.30#ibcon#read 3, iclass 27, count 0 2006.239.08:01:41.30#ibcon#about to read 4, iclass 27, count 0 2006.239.08:01:41.30#ibcon#read 4, iclass 27, count 0 2006.239.08:01:41.30#ibcon#about to read 5, iclass 27, count 0 2006.239.08:01:41.30#ibcon#read 5, iclass 27, count 0 2006.239.08:01:41.30#ibcon#about to read 6, iclass 27, count 0 2006.239.08:01:41.30#ibcon#read 6, iclass 27, count 0 2006.239.08:01:41.30#ibcon#end of sib2, iclass 27, count 0 2006.239.08:01:41.30#ibcon#*after write, iclass 27, count 0 2006.239.08:01:41.30#ibcon#*before return 0, iclass 27, count 0 2006.239.08:01:41.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:41.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:01:41.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:01:41.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:01:41.30$vc4f8/vb=3,4 2006.239.08:01:41.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.08:01:41.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.08:01:41.30#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:41.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:41.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:41.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:41.36#ibcon#enter wrdev, iclass 29, count 2 2006.239.08:01:41.36#ibcon#first serial, iclass 29, count 2 2006.239.08:01:41.36#ibcon#enter sib2, iclass 29, count 2 2006.239.08:01:41.36#ibcon#flushed, iclass 29, count 2 2006.239.08:01:41.36#ibcon#about to write, iclass 29, count 2 2006.239.08:01:41.36#ibcon#wrote, iclass 29, count 2 2006.239.08:01:41.36#ibcon#about to read 3, iclass 29, count 2 2006.239.08:01:41.38#ibcon#read 3, iclass 29, count 2 2006.239.08:01:41.38#ibcon#about to read 4, iclass 29, count 2 2006.239.08:01:41.38#ibcon#read 4, iclass 29, count 2 2006.239.08:01:41.38#ibcon#about to read 5, iclass 29, count 2 2006.239.08:01:41.38#ibcon#read 5, iclass 29, count 2 2006.239.08:01:41.38#ibcon#about to read 6, iclass 29, count 2 2006.239.08:01:41.38#ibcon#read 6, iclass 29, count 2 2006.239.08:01:41.38#ibcon#end of sib2, iclass 29, count 2 2006.239.08:01:41.38#ibcon#*mode == 0, iclass 29, count 2 2006.239.08:01:41.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.08:01:41.38#ibcon#[27=AT03-04\r\n] 2006.239.08:01:41.38#ibcon#*before write, iclass 29, count 2 2006.239.08:01:41.38#ibcon#enter sib2, iclass 29, count 2 2006.239.08:01:41.38#ibcon#flushed, iclass 29, count 2 2006.239.08:01:41.38#ibcon#about to write, iclass 29, count 2 2006.239.08:01:41.38#ibcon#wrote, iclass 29, count 2 2006.239.08:01:41.38#ibcon#about to read 3, iclass 29, count 2 2006.239.08:01:41.41#ibcon#read 3, iclass 29, count 2 2006.239.08:01:41.41#ibcon#about to read 4, iclass 29, count 2 2006.239.08:01:41.41#ibcon#read 4, iclass 29, count 2 2006.239.08:01:41.41#ibcon#about to read 5, iclass 29, count 2 2006.239.08:01:41.41#ibcon#read 5, iclass 29, count 2 2006.239.08:01:41.41#ibcon#about to read 6, iclass 29, count 2 2006.239.08:01:41.41#ibcon#read 6, iclass 29, count 2 2006.239.08:01:41.41#ibcon#end of sib2, iclass 29, count 2 2006.239.08:01:41.41#ibcon#*after write, iclass 29, count 2 2006.239.08:01:41.41#ibcon#*before return 0, iclass 29, count 2 2006.239.08:01:41.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:41.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:01:41.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.08:01:41.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:41.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:41.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:41.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:41.53#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:01:41.53#ibcon#first serial, iclass 29, count 0 2006.239.08:01:41.53#ibcon#enter sib2, iclass 29, count 0 2006.239.08:01:41.53#ibcon#flushed, iclass 29, count 0 2006.239.08:01:41.53#ibcon#about to write, iclass 29, count 0 2006.239.08:01:41.53#ibcon#wrote, iclass 29, count 0 2006.239.08:01:41.53#ibcon#about to read 3, iclass 29, count 0 2006.239.08:01:41.55#ibcon#read 3, iclass 29, count 0 2006.239.08:01:41.55#ibcon#about to read 4, iclass 29, count 0 2006.239.08:01:41.55#ibcon#read 4, iclass 29, count 0 2006.239.08:01:41.55#ibcon#about to read 5, iclass 29, count 0 2006.239.08:01:41.55#ibcon#read 5, iclass 29, count 0 2006.239.08:01:41.55#ibcon#about to read 6, iclass 29, count 0 2006.239.08:01:41.55#ibcon#read 6, iclass 29, count 0 2006.239.08:01:41.55#ibcon#end of sib2, iclass 29, count 0 2006.239.08:01:41.55#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:01:41.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:01:41.55#ibcon#[27=USB\r\n] 2006.239.08:01:41.55#ibcon#*before write, iclass 29, count 0 2006.239.08:01:41.55#ibcon#enter sib2, iclass 29, count 0 2006.239.08:01:41.55#ibcon#flushed, iclass 29, count 0 2006.239.08:01:41.55#ibcon#about to write, iclass 29, count 0 2006.239.08:01:41.55#ibcon#wrote, iclass 29, count 0 2006.239.08:01:41.55#ibcon#about to read 3, iclass 29, count 0 2006.239.08:01:41.58#ibcon#read 3, iclass 29, count 0 2006.239.08:01:41.58#ibcon#about to read 4, iclass 29, count 0 2006.239.08:01:41.58#ibcon#read 4, iclass 29, count 0 2006.239.08:01:41.58#ibcon#about to read 5, iclass 29, count 0 2006.239.08:01:41.58#ibcon#read 5, iclass 29, count 0 2006.239.08:01:41.58#ibcon#about to read 6, iclass 29, count 0 2006.239.08:01:41.58#ibcon#read 6, iclass 29, count 0 2006.239.08:01:41.58#ibcon#end of sib2, iclass 29, count 0 2006.239.08:01:41.58#ibcon#*after write, iclass 29, count 0 2006.239.08:01:41.58#ibcon#*before return 0, iclass 29, count 0 2006.239.08:01:41.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:41.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:01:41.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:01:41.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:01:41.58$vc4f8/vblo=4,712.99 2006.239.08:01:41.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.08:01:41.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.08:01:41.58#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:41.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:41.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:41.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:41.58#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:01:41.58#ibcon#first serial, iclass 31, count 0 2006.239.08:01:41.58#ibcon#enter sib2, iclass 31, count 0 2006.239.08:01:41.58#ibcon#flushed, iclass 31, count 0 2006.239.08:01:41.58#ibcon#about to write, iclass 31, count 0 2006.239.08:01:41.58#ibcon#wrote, iclass 31, count 0 2006.239.08:01:41.58#ibcon#about to read 3, iclass 31, count 0 2006.239.08:01:41.60#ibcon#read 3, iclass 31, count 0 2006.239.08:01:41.60#ibcon#about to read 4, iclass 31, count 0 2006.239.08:01:41.60#ibcon#read 4, iclass 31, count 0 2006.239.08:01:41.60#ibcon#about to read 5, iclass 31, count 0 2006.239.08:01:41.60#ibcon#read 5, iclass 31, count 0 2006.239.08:01:41.60#ibcon#about to read 6, iclass 31, count 0 2006.239.08:01:41.60#ibcon#read 6, iclass 31, count 0 2006.239.08:01:41.60#ibcon#end of sib2, iclass 31, count 0 2006.239.08:01:41.60#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:01:41.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:01:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:01:41.60#ibcon#*before write, iclass 31, count 0 2006.239.08:01:41.60#ibcon#enter sib2, iclass 31, count 0 2006.239.08:01:41.60#ibcon#flushed, iclass 31, count 0 2006.239.08:01:41.60#ibcon#about to write, iclass 31, count 0 2006.239.08:01:41.60#ibcon#wrote, iclass 31, count 0 2006.239.08:01:41.60#ibcon#about to read 3, iclass 31, count 0 2006.239.08:01:41.64#ibcon#read 3, iclass 31, count 0 2006.239.08:01:41.64#ibcon#about to read 4, iclass 31, count 0 2006.239.08:01:41.64#ibcon#read 4, iclass 31, count 0 2006.239.08:01:41.64#ibcon#about to read 5, iclass 31, count 0 2006.239.08:01:41.64#ibcon#read 5, iclass 31, count 0 2006.239.08:01:41.64#ibcon#about to read 6, iclass 31, count 0 2006.239.08:01:41.64#ibcon#read 6, iclass 31, count 0 2006.239.08:01:41.64#ibcon#end of sib2, iclass 31, count 0 2006.239.08:01:41.64#ibcon#*after write, iclass 31, count 0 2006.239.08:01:41.64#ibcon#*before return 0, iclass 31, count 0 2006.239.08:01:41.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:41.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:01:41.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:01:41.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:01:41.64$vc4f8/vb=4,4 2006.239.08:01:41.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.08:01:41.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.08:01:41.64#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:41.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:41.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:41.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:41.70#ibcon#enter wrdev, iclass 33, count 2 2006.239.08:01:41.70#ibcon#first serial, iclass 33, count 2 2006.239.08:01:41.70#ibcon#enter sib2, iclass 33, count 2 2006.239.08:01:41.70#ibcon#flushed, iclass 33, count 2 2006.239.08:01:41.70#ibcon#about to write, iclass 33, count 2 2006.239.08:01:41.70#ibcon#wrote, iclass 33, count 2 2006.239.08:01:41.70#ibcon#about to read 3, iclass 33, count 2 2006.239.08:01:41.72#ibcon#read 3, iclass 33, count 2 2006.239.08:01:41.72#ibcon#about to read 4, iclass 33, count 2 2006.239.08:01:41.72#ibcon#read 4, iclass 33, count 2 2006.239.08:01:41.72#ibcon#about to read 5, iclass 33, count 2 2006.239.08:01:41.72#ibcon#read 5, iclass 33, count 2 2006.239.08:01:41.72#ibcon#about to read 6, iclass 33, count 2 2006.239.08:01:41.72#ibcon#read 6, iclass 33, count 2 2006.239.08:01:41.72#ibcon#end of sib2, iclass 33, count 2 2006.239.08:01:41.72#ibcon#*mode == 0, iclass 33, count 2 2006.239.08:01:41.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.08:01:41.72#ibcon#[27=AT04-04\r\n] 2006.239.08:01:41.72#ibcon#*before write, iclass 33, count 2 2006.239.08:01:41.72#ibcon#enter sib2, iclass 33, count 2 2006.239.08:01:41.72#ibcon#flushed, iclass 33, count 2 2006.239.08:01:41.72#ibcon#about to write, iclass 33, count 2 2006.239.08:01:41.72#ibcon#wrote, iclass 33, count 2 2006.239.08:01:41.72#ibcon#about to read 3, iclass 33, count 2 2006.239.08:01:41.75#ibcon#read 3, iclass 33, count 2 2006.239.08:01:41.75#ibcon#about to read 4, iclass 33, count 2 2006.239.08:01:41.75#ibcon#read 4, iclass 33, count 2 2006.239.08:01:41.75#ibcon#about to read 5, iclass 33, count 2 2006.239.08:01:41.75#ibcon#read 5, iclass 33, count 2 2006.239.08:01:41.75#ibcon#about to read 6, iclass 33, count 2 2006.239.08:01:41.75#ibcon#read 6, iclass 33, count 2 2006.239.08:01:41.75#ibcon#end of sib2, iclass 33, count 2 2006.239.08:01:41.75#ibcon#*after write, iclass 33, count 2 2006.239.08:01:41.75#ibcon#*before return 0, iclass 33, count 2 2006.239.08:01:41.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:41.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:01:41.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.08:01:41.75#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:41.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:41.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:41.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:41.87#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:01:41.87#ibcon#first serial, iclass 33, count 0 2006.239.08:01:41.87#ibcon#enter sib2, iclass 33, count 0 2006.239.08:01:41.87#ibcon#flushed, iclass 33, count 0 2006.239.08:01:41.87#ibcon#about to write, iclass 33, count 0 2006.239.08:01:41.87#ibcon#wrote, iclass 33, count 0 2006.239.08:01:41.87#ibcon#about to read 3, iclass 33, count 0 2006.239.08:01:41.89#ibcon#read 3, iclass 33, count 0 2006.239.08:01:41.89#ibcon#about to read 4, iclass 33, count 0 2006.239.08:01:41.89#ibcon#read 4, iclass 33, count 0 2006.239.08:01:41.89#ibcon#about to read 5, iclass 33, count 0 2006.239.08:01:41.89#ibcon#read 5, iclass 33, count 0 2006.239.08:01:41.89#ibcon#about to read 6, iclass 33, count 0 2006.239.08:01:41.89#ibcon#read 6, iclass 33, count 0 2006.239.08:01:41.89#ibcon#end of sib2, iclass 33, count 0 2006.239.08:01:41.89#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:01:41.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:01:41.89#ibcon#[27=USB\r\n] 2006.239.08:01:41.89#ibcon#*before write, iclass 33, count 0 2006.239.08:01:41.89#ibcon#enter sib2, iclass 33, count 0 2006.239.08:01:41.89#ibcon#flushed, iclass 33, count 0 2006.239.08:01:41.89#ibcon#about to write, iclass 33, count 0 2006.239.08:01:41.89#ibcon#wrote, iclass 33, count 0 2006.239.08:01:41.89#ibcon#about to read 3, iclass 33, count 0 2006.239.08:01:41.92#ibcon#read 3, iclass 33, count 0 2006.239.08:01:41.92#ibcon#about to read 4, iclass 33, count 0 2006.239.08:01:41.92#ibcon#read 4, iclass 33, count 0 2006.239.08:01:41.92#ibcon#about to read 5, iclass 33, count 0 2006.239.08:01:41.92#ibcon#read 5, iclass 33, count 0 2006.239.08:01:41.92#ibcon#about to read 6, iclass 33, count 0 2006.239.08:01:41.92#ibcon#read 6, iclass 33, count 0 2006.239.08:01:41.92#ibcon#end of sib2, iclass 33, count 0 2006.239.08:01:41.92#ibcon#*after write, iclass 33, count 0 2006.239.08:01:41.92#ibcon#*before return 0, iclass 33, count 0 2006.239.08:01:41.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:41.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:01:41.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:01:41.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:01:41.92$vc4f8/vblo=5,744.99 2006.239.08:01:41.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.08:01:41.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.08:01:41.92#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:41.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:41.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:41.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:41.92#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:01:41.92#ibcon#first serial, iclass 35, count 0 2006.239.08:01:41.92#ibcon#enter sib2, iclass 35, count 0 2006.239.08:01:41.92#ibcon#flushed, iclass 35, count 0 2006.239.08:01:41.92#ibcon#about to write, iclass 35, count 0 2006.239.08:01:41.92#ibcon#wrote, iclass 35, count 0 2006.239.08:01:41.92#ibcon#about to read 3, iclass 35, count 0 2006.239.08:01:41.94#ibcon#read 3, iclass 35, count 0 2006.239.08:01:41.94#ibcon#about to read 4, iclass 35, count 0 2006.239.08:01:41.94#ibcon#read 4, iclass 35, count 0 2006.239.08:01:41.94#ibcon#about to read 5, iclass 35, count 0 2006.239.08:01:41.94#ibcon#read 5, iclass 35, count 0 2006.239.08:01:41.94#ibcon#about to read 6, iclass 35, count 0 2006.239.08:01:41.94#ibcon#read 6, iclass 35, count 0 2006.239.08:01:41.94#ibcon#end of sib2, iclass 35, count 0 2006.239.08:01:41.94#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:01:41.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:01:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:01:41.94#ibcon#*before write, iclass 35, count 0 2006.239.08:01:41.94#ibcon#enter sib2, iclass 35, count 0 2006.239.08:01:41.94#ibcon#flushed, iclass 35, count 0 2006.239.08:01:41.94#ibcon#about to write, iclass 35, count 0 2006.239.08:01:41.94#ibcon#wrote, iclass 35, count 0 2006.239.08:01:41.94#ibcon#about to read 3, iclass 35, count 0 2006.239.08:01:41.98#ibcon#read 3, iclass 35, count 0 2006.239.08:01:41.98#ibcon#about to read 4, iclass 35, count 0 2006.239.08:01:41.98#ibcon#read 4, iclass 35, count 0 2006.239.08:01:41.98#ibcon#about to read 5, iclass 35, count 0 2006.239.08:01:41.98#ibcon#read 5, iclass 35, count 0 2006.239.08:01:41.98#ibcon#about to read 6, iclass 35, count 0 2006.239.08:01:41.98#ibcon#read 6, iclass 35, count 0 2006.239.08:01:41.98#ibcon#end of sib2, iclass 35, count 0 2006.239.08:01:41.98#ibcon#*after write, iclass 35, count 0 2006.239.08:01:41.98#ibcon#*before return 0, iclass 35, count 0 2006.239.08:01:41.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:41.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:01:41.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:01:41.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:01:41.98$vc4f8/vb=5,4 2006.239.08:01:41.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.08:01:41.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.08:01:41.98#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:41.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:42.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:42.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:42.04#ibcon#enter wrdev, iclass 37, count 2 2006.239.08:01:42.04#ibcon#first serial, iclass 37, count 2 2006.239.08:01:42.04#ibcon#enter sib2, iclass 37, count 2 2006.239.08:01:42.04#ibcon#flushed, iclass 37, count 2 2006.239.08:01:42.04#ibcon#about to write, iclass 37, count 2 2006.239.08:01:42.04#ibcon#wrote, iclass 37, count 2 2006.239.08:01:42.04#ibcon#about to read 3, iclass 37, count 2 2006.239.08:01:42.06#ibcon#read 3, iclass 37, count 2 2006.239.08:01:42.06#ibcon#about to read 4, iclass 37, count 2 2006.239.08:01:42.06#ibcon#read 4, iclass 37, count 2 2006.239.08:01:42.06#ibcon#about to read 5, iclass 37, count 2 2006.239.08:01:42.06#ibcon#read 5, iclass 37, count 2 2006.239.08:01:42.06#ibcon#about to read 6, iclass 37, count 2 2006.239.08:01:42.06#ibcon#read 6, iclass 37, count 2 2006.239.08:01:42.06#ibcon#end of sib2, iclass 37, count 2 2006.239.08:01:42.06#ibcon#*mode == 0, iclass 37, count 2 2006.239.08:01:42.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.08:01:42.06#ibcon#[27=AT05-04\r\n] 2006.239.08:01:42.06#ibcon#*before write, iclass 37, count 2 2006.239.08:01:42.06#ibcon#enter sib2, iclass 37, count 2 2006.239.08:01:42.06#ibcon#flushed, iclass 37, count 2 2006.239.08:01:42.06#ibcon#about to write, iclass 37, count 2 2006.239.08:01:42.06#ibcon#wrote, iclass 37, count 2 2006.239.08:01:42.06#ibcon#about to read 3, iclass 37, count 2 2006.239.08:01:42.09#ibcon#read 3, iclass 37, count 2 2006.239.08:01:42.09#ibcon#about to read 4, iclass 37, count 2 2006.239.08:01:42.09#ibcon#read 4, iclass 37, count 2 2006.239.08:01:42.09#ibcon#about to read 5, iclass 37, count 2 2006.239.08:01:42.09#ibcon#read 5, iclass 37, count 2 2006.239.08:01:42.09#ibcon#about to read 6, iclass 37, count 2 2006.239.08:01:42.09#ibcon#read 6, iclass 37, count 2 2006.239.08:01:42.09#ibcon#end of sib2, iclass 37, count 2 2006.239.08:01:42.09#ibcon#*after write, iclass 37, count 2 2006.239.08:01:42.09#ibcon#*before return 0, iclass 37, count 2 2006.239.08:01:42.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:42.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:01:42.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.08:01:42.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:42.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:42.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:42.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:42.21#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:01:42.21#ibcon#first serial, iclass 37, count 0 2006.239.08:01:42.21#ibcon#enter sib2, iclass 37, count 0 2006.239.08:01:42.21#ibcon#flushed, iclass 37, count 0 2006.239.08:01:42.21#ibcon#about to write, iclass 37, count 0 2006.239.08:01:42.21#ibcon#wrote, iclass 37, count 0 2006.239.08:01:42.21#ibcon#about to read 3, iclass 37, count 0 2006.239.08:01:42.23#ibcon#read 3, iclass 37, count 0 2006.239.08:01:42.23#ibcon#about to read 4, iclass 37, count 0 2006.239.08:01:42.23#ibcon#read 4, iclass 37, count 0 2006.239.08:01:42.23#ibcon#about to read 5, iclass 37, count 0 2006.239.08:01:42.23#ibcon#read 5, iclass 37, count 0 2006.239.08:01:42.23#ibcon#about to read 6, iclass 37, count 0 2006.239.08:01:42.23#ibcon#read 6, iclass 37, count 0 2006.239.08:01:42.23#ibcon#end of sib2, iclass 37, count 0 2006.239.08:01:42.23#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:01:42.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:01:42.23#ibcon#[27=USB\r\n] 2006.239.08:01:42.23#ibcon#*before write, iclass 37, count 0 2006.239.08:01:42.23#ibcon#enter sib2, iclass 37, count 0 2006.239.08:01:42.23#ibcon#flushed, iclass 37, count 0 2006.239.08:01:42.23#ibcon#about to write, iclass 37, count 0 2006.239.08:01:42.23#ibcon#wrote, iclass 37, count 0 2006.239.08:01:42.23#ibcon#about to read 3, iclass 37, count 0 2006.239.08:01:42.26#ibcon#read 3, iclass 37, count 0 2006.239.08:01:42.26#ibcon#about to read 4, iclass 37, count 0 2006.239.08:01:42.26#ibcon#read 4, iclass 37, count 0 2006.239.08:01:42.26#ibcon#about to read 5, iclass 37, count 0 2006.239.08:01:42.26#ibcon#read 5, iclass 37, count 0 2006.239.08:01:42.26#ibcon#about to read 6, iclass 37, count 0 2006.239.08:01:42.26#ibcon#read 6, iclass 37, count 0 2006.239.08:01:42.26#ibcon#end of sib2, iclass 37, count 0 2006.239.08:01:42.26#ibcon#*after write, iclass 37, count 0 2006.239.08:01:42.26#ibcon#*before return 0, iclass 37, count 0 2006.239.08:01:42.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:42.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:01:42.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:01:42.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:01:42.26$vc4f8/vblo=6,752.99 2006.239.08:01:42.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:01:42.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:01:42.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:01:42.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:42.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:42.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:42.26#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:01:42.26#ibcon#first serial, iclass 39, count 0 2006.239.08:01:42.26#ibcon#enter sib2, iclass 39, count 0 2006.239.08:01:42.26#ibcon#flushed, iclass 39, count 0 2006.239.08:01:42.26#ibcon#about to write, iclass 39, count 0 2006.239.08:01:42.26#ibcon#wrote, iclass 39, count 0 2006.239.08:01:42.26#ibcon#about to read 3, iclass 39, count 0 2006.239.08:01:42.28#ibcon#read 3, iclass 39, count 0 2006.239.08:01:42.28#ibcon#about to read 4, iclass 39, count 0 2006.239.08:01:42.28#ibcon#read 4, iclass 39, count 0 2006.239.08:01:42.28#ibcon#about to read 5, iclass 39, count 0 2006.239.08:01:42.28#ibcon#read 5, iclass 39, count 0 2006.239.08:01:42.28#ibcon#about to read 6, iclass 39, count 0 2006.239.08:01:42.28#ibcon#read 6, iclass 39, count 0 2006.239.08:01:42.28#ibcon#end of sib2, iclass 39, count 0 2006.239.08:01:42.28#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:01:42.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:01:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:01:42.28#ibcon#*before write, iclass 39, count 0 2006.239.08:01:42.28#ibcon#enter sib2, iclass 39, count 0 2006.239.08:01:42.28#ibcon#flushed, iclass 39, count 0 2006.239.08:01:42.28#ibcon#about to write, iclass 39, count 0 2006.239.08:01:42.28#ibcon#wrote, iclass 39, count 0 2006.239.08:01:42.28#ibcon#about to read 3, iclass 39, count 0 2006.239.08:01:42.32#ibcon#read 3, iclass 39, count 0 2006.239.08:01:42.32#ibcon#about to read 4, iclass 39, count 0 2006.239.08:01:42.32#ibcon#read 4, iclass 39, count 0 2006.239.08:01:42.32#ibcon#about to read 5, iclass 39, count 0 2006.239.08:01:42.32#ibcon#read 5, iclass 39, count 0 2006.239.08:01:42.32#ibcon#about to read 6, iclass 39, count 0 2006.239.08:01:42.32#ibcon#read 6, iclass 39, count 0 2006.239.08:01:42.32#ibcon#end of sib2, iclass 39, count 0 2006.239.08:01:42.32#ibcon#*after write, iclass 39, count 0 2006.239.08:01:42.32#ibcon#*before return 0, iclass 39, count 0 2006.239.08:01:42.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:42.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:01:42.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:01:42.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:01:42.32$vc4f8/vb=6,4 2006.239.08:01:42.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.08:01:42.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.08:01:42.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:01:42.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:42.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:42.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:42.38#ibcon#enter wrdev, iclass 3, count 2 2006.239.08:01:42.38#ibcon#first serial, iclass 3, count 2 2006.239.08:01:42.38#ibcon#enter sib2, iclass 3, count 2 2006.239.08:01:42.38#ibcon#flushed, iclass 3, count 2 2006.239.08:01:42.38#ibcon#about to write, iclass 3, count 2 2006.239.08:01:42.38#ibcon#wrote, iclass 3, count 2 2006.239.08:01:42.38#ibcon#about to read 3, iclass 3, count 2 2006.239.08:01:42.40#ibcon#read 3, iclass 3, count 2 2006.239.08:01:42.40#ibcon#about to read 4, iclass 3, count 2 2006.239.08:01:42.40#ibcon#read 4, iclass 3, count 2 2006.239.08:01:42.40#ibcon#about to read 5, iclass 3, count 2 2006.239.08:01:42.40#ibcon#read 5, iclass 3, count 2 2006.239.08:01:42.40#ibcon#about to read 6, iclass 3, count 2 2006.239.08:01:42.40#ibcon#read 6, iclass 3, count 2 2006.239.08:01:42.40#ibcon#end of sib2, iclass 3, count 2 2006.239.08:01:42.40#ibcon#*mode == 0, iclass 3, count 2 2006.239.08:01:42.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.08:01:42.40#ibcon#[27=AT06-04\r\n] 2006.239.08:01:42.40#ibcon#*before write, iclass 3, count 2 2006.239.08:01:42.40#ibcon#enter sib2, iclass 3, count 2 2006.239.08:01:42.40#ibcon#flushed, iclass 3, count 2 2006.239.08:01:42.40#ibcon#about to write, iclass 3, count 2 2006.239.08:01:42.40#ibcon#wrote, iclass 3, count 2 2006.239.08:01:42.40#ibcon#about to read 3, iclass 3, count 2 2006.239.08:01:42.43#ibcon#read 3, iclass 3, count 2 2006.239.08:01:42.43#ibcon#about to read 4, iclass 3, count 2 2006.239.08:01:42.43#ibcon#read 4, iclass 3, count 2 2006.239.08:01:42.43#ibcon#about to read 5, iclass 3, count 2 2006.239.08:01:42.43#ibcon#read 5, iclass 3, count 2 2006.239.08:01:42.43#ibcon#about to read 6, iclass 3, count 2 2006.239.08:01:42.43#ibcon#read 6, iclass 3, count 2 2006.239.08:01:42.43#ibcon#end of sib2, iclass 3, count 2 2006.239.08:01:42.43#ibcon#*after write, iclass 3, count 2 2006.239.08:01:42.43#ibcon#*before return 0, iclass 3, count 2 2006.239.08:01:42.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:42.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:01:42.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.08:01:42.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:01:42.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:42.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:42.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:42.55#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:01:42.55#ibcon#first serial, iclass 3, count 0 2006.239.08:01:42.55#ibcon#enter sib2, iclass 3, count 0 2006.239.08:01:42.55#ibcon#flushed, iclass 3, count 0 2006.239.08:01:42.55#ibcon#about to write, iclass 3, count 0 2006.239.08:01:42.55#ibcon#wrote, iclass 3, count 0 2006.239.08:01:42.55#ibcon#about to read 3, iclass 3, count 0 2006.239.08:01:42.57#ibcon#read 3, iclass 3, count 0 2006.239.08:01:42.57#ibcon#about to read 4, iclass 3, count 0 2006.239.08:01:42.57#ibcon#read 4, iclass 3, count 0 2006.239.08:01:42.57#ibcon#about to read 5, iclass 3, count 0 2006.239.08:01:42.57#ibcon#read 5, iclass 3, count 0 2006.239.08:01:42.57#ibcon#about to read 6, iclass 3, count 0 2006.239.08:01:42.57#ibcon#read 6, iclass 3, count 0 2006.239.08:01:42.57#ibcon#end of sib2, iclass 3, count 0 2006.239.08:01:42.57#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:01:42.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:01:42.57#ibcon#[27=USB\r\n] 2006.239.08:01:42.57#ibcon#*before write, iclass 3, count 0 2006.239.08:01:42.57#ibcon#enter sib2, iclass 3, count 0 2006.239.08:01:42.57#ibcon#flushed, iclass 3, count 0 2006.239.08:01:42.57#ibcon#about to write, iclass 3, count 0 2006.239.08:01:42.57#ibcon#wrote, iclass 3, count 0 2006.239.08:01:42.57#ibcon#about to read 3, iclass 3, count 0 2006.239.08:01:42.60#ibcon#read 3, iclass 3, count 0 2006.239.08:01:42.60#ibcon#about to read 4, iclass 3, count 0 2006.239.08:01:42.60#ibcon#read 4, iclass 3, count 0 2006.239.08:01:42.60#ibcon#about to read 5, iclass 3, count 0 2006.239.08:01:42.60#ibcon#read 5, iclass 3, count 0 2006.239.08:01:42.60#ibcon#about to read 6, iclass 3, count 0 2006.239.08:01:42.60#ibcon#read 6, iclass 3, count 0 2006.239.08:01:42.60#ibcon#end of sib2, iclass 3, count 0 2006.239.08:01:42.60#ibcon#*after write, iclass 3, count 0 2006.239.08:01:42.60#ibcon#*before return 0, iclass 3, count 0 2006.239.08:01:42.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:42.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:01:42.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:01:42.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:01:42.60$vc4f8/vabw=wide 2006.239.08:01:42.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:01:42.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:01:42.60#ibcon#ireg 8 cls_cnt 0 2006.239.08:01:42.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:42.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:42.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:42.60#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:01:42.60#ibcon#first serial, iclass 5, count 0 2006.239.08:01:42.60#ibcon#enter sib2, iclass 5, count 0 2006.239.08:01:42.60#ibcon#flushed, iclass 5, count 0 2006.239.08:01:42.60#ibcon#about to write, iclass 5, count 0 2006.239.08:01:42.60#ibcon#wrote, iclass 5, count 0 2006.239.08:01:42.60#ibcon#about to read 3, iclass 5, count 0 2006.239.08:01:42.62#ibcon#read 3, iclass 5, count 0 2006.239.08:01:42.62#ibcon#about to read 4, iclass 5, count 0 2006.239.08:01:42.62#ibcon#read 4, iclass 5, count 0 2006.239.08:01:42.62#ibcon#about to read 5, iclass 5, count 0 2006.239.08:01:42.62#ibcon#read 5, iclass 5, count 0 2006.239.08:01:42.62#ibcon#about to read 6, iclass 5, count 0 2006.239.08:01:42.62#ibcon#read 6, iclass 5, count 0 2006.239.08:01:42.62#ibcon#end of sib2, iclass 5, count 0 2006.239.08:01:42.62#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:01:42.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:01:42.62#ibcon#[25=BW32\r\n] 2006.239.08:01:42.62#ibcon#*before write, iclass 5, count 0 2006.239.08:01:42.62#ibcon#enter sib2, iclass 5, count 0 2006.239.08:01:42.62#ibcon#flushed, iclass 5, count 0 2006.239.08:01:42.62#ibcon#about to write, iclass 5, count 0 2006.239.08:01:42.62#ibcon#wrote, iclass 5, count 0 2006.239.08:01:42.62#ibcon#about to read 3, iclass 5, count 0 2006.239.08:01:42.65#ibcon#read 3, iclass 5, count 0 2006.239.08:01:42.65#ibcon#about to read 4, iclass 5, count 0 2006.239.08:01:42.65#ibcon#read 4, iclass 5, count 0 2006.239.08:01:42.65#ibcon#about to read 5, iclass 5, count 0 2006.239.08:01:42.65#ibcon#read 5, iclass 5, count 0 2006.239.08:01:42.65#ibcon#about to read 6, iclass 5, count 0 2006.239.08:01:42.65#ibcon#read 6, iclass 5, count 0 2006.239.08:01:42.65#ibcon#end of sib2, iclass 5, count 0 2006.239.08:01:42.65#ibcon#*after write, iclass 5, count 0 2006.239.08:01:42.65#ibcon#*before return 0, iclass 5, count 0 2006.239.08:01:42.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:42.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:01:42.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:01:42.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:01:42.65$vc4f8/vbbw=wide 2006.239.08:01:42.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.08:01:42.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.08:01:42.65#ibcon#ireg 8 cls_cnt 0 2006.239.08:01:42.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:01:42.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:01:42.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:01:42.72#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:01:42.72#ibcon#first serial, iclass 7, count 0 2006.239.08:01:42.72#ibcon#enter sib2, iclass 7, count 0 2006.239.08:01:42.72#ibcon#flushed, iclass 7, count 0 2006.239.08:01:42.72#ibcon#about to write, iclass 7, count 0 2006.239.08:01:42.72#ibcon#wrote, iclass 7, count 0 2006.239.08:01:42.72#ibcon#about to read 3, iclass 7, count 0 2006.239.08:01:42.74#ibcon#read 3, iclass 7, count 0 2006.239.08:01:42.74#ibcon#about to read 4, iclass 7, count 0 2006.239.08:01:42.74#ibcon#read 4, iclass 7, count 0 2006.239.08:01:42.74#ibcon#about to read 5, iclass 7, count 0 2006.239.08:01:42.74#ibcon#read 5, iclass 7, count 0 2006.239.08:01:42.74#ibcon#about to read 6, iclass 7, count 0 2006.239.08:01:42.74#ibcon#read 6, iclass 7, count 0 2006.239.08:01:42.74#ibcon#end of sib2, iclass 7, count 0 2006.239.08:01:42.74#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:01:42.74#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:01:42.74#ibcon#[27=BW32\r\n] 2006.239.08:01:42.74#ibcon#*before write, iclass 7, count 0 2006.239.08:01:42.74#ibcon#enter sib2, iclass 7, count 0 2006.239.08:01:42.74#ibcon#flushed, iclass 7, count 0 2006.239.08:01:42.74#ibcon#about to write, iclass 7, count 0 2006.239.08:01:42.74#ibcon#wrote, iclass 7, count 0 2006.239.08:01:42.74#ibcon#about to read 3, iclass 7, count 0 2006.239.08:01:42.77#ibcon#read 3, iclass 7, count 0 2006.239.08:01:42.77#ibcon#about to read 4, iclass 7, count 0 2006.239.08:01:42.77#ibcon#read 4, iclass 7, count 0 2006.239.08:01:42.77#ibcon#about to read 5, iclass 7, count 0 2006.239.08:01:42.77#ibcon#read 5, iclass 7, count 0 2006.239.08:01:42.77#ibcon#about to read 6, iclass 7, count 0 2006.239.08:01:42.77#ibcon#read 6, iclass 7, count 0 2006.239.08:01:42.77#ibcon#end of sib2, iclass 7, count 0 2006.239.08:01:42.77#ibcon#*after write, iclass 7, count 0 2006.239.08:01:42.77#ibcon#*before return 0, iclass 7, count 0 2006.239.08:01:42.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:01:42.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:01:42.77#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:01:42.77#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:01:42.77$4f8m12a/ifd4f 2006.239.08:01:42.77$ifd4f/lo= 2006.239.08:01:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:01:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:01:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:01:42.77$ifd4f/patch= 2006.239.08:01:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:01:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:01:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:01:42.77$4f8m12a/"form=m,16.000,1:2 2006.239.08:01:42.77$4f8m12a/"tpicd 2006.239.08:01:42.77$4f8m12a/echo=off 2006.239.08:01:42.77$4f8m12a/xlog=off 2006.239.08:01:42.77:!2006.239.08:02:10 2006.239.08:01:54.14#trakl#Source acquired 2006.239.08:01:55.14#flagr#flagr/antenna,acquired 2006.239.08:02:10.00:preob 2006.239.08:02:11.14/onsource/TRACKING 2006.239.08:02:11.14:!2006.239.08:02:20 2006.239.08:02:20.00:data_valid=on 2006.239.08:02:20.00:midob 2006.239.08:02:20.14/onsource/TRACKING 2006.239.08:02:20.14/wx/25.16,1011.6,80 2006.239.08:02:20.25/cable/+6.4148E-03 2006.239.08:02:21.34/va/01,08,usb,yes,31,33 2006.239.08:02:21.34/va/02,07,usb,yes,31,33 2006.239.08:02:21.34/va/03,07,usb,yes,29,30 2006.239.08:02:21.34/va/04,07,usb,yes,32,35 2006.239.08:02:21.34/va/05,08,usb,yes,29,31 2006.239.08:02:21.34/va/06,07,usb,yes,32,32 2006.239.08:02:21.34/va/07,07,usb,yes,32,32 2006.239.08:02:21.34/va/08,07,usb,yes,34,34 2006.239.08:02:21.57/valo/01,532.99,yes,locked 2006.239.08:02:21.57/valo/02,572.99,yes,locked 2006.239.08:02:21.57/valo/03,672.99,yes,locked 2006.239.08:02:21.57/valo/04,832.99,yes,locked 2006.239.08:02:21.57/valo/05,652.99,yes,locked 2006.239.08:02:21.57/valo/06,772.99,yes,locked 2006.239.08:02:21.57/valo/07,832.99,yes,locked 2006.239.08:02:21.57/valo/08,852.99,yes,locked 2006.239.08:02:22.66/vb/01,04,usb,yes,30,29 2006.239.08:02:22.66/vb/02,04,usb,yes,32,34 2006.239.08:02:22.66/vb/03,04,usb,yes,29,32 2006.239.08:02:22.66/vb/04,04,usb,yes,29,30 2006.239.08:02:22.66/vb/05,04,usb,yes,28,32 2006.239.08:02:22.66/vb/06,04,usb,yes,29,32 2006.239.08:02:22.66/vb/07,04,usb,yes,31,31 2006.239.08:02:22.66/vb/08,04,usb,yes,28,32 2006.239.08:02:22.90/vblo/01,632.99,yes,locked 2006.239.08:02:22.90/vblo/02,640.99,yes,locked 2006.239.08:02:22.90/vblo/03,656.99,yes,locked 2006.239.08:02:22.90/vblo/04,712.99,yes,locked 2006.239.08:02:22.90/vblo/05,744.99,yes,locked 2006.239.08:02:22.90/vblo/06,752.99,yes,locked 2006.239.08:02:22.90/vblo/07,734.99,yes,locked 2006.239.08:02:22.90/vblo/08,744.99,yes,locked 2006.239.08:02:23.05/vabw/8 2006.239.08:02:23.20/vbbw/8 2006.239.08:02:23.32/xfe/off,on,13.5 2006.239.08:02:23.69/ifatt/23,28,28,28 2006.239.08:02:24.08/fmout-gps/S +4.41E-07 2006.239.08:02:24.12:!2006.239.08:03:20 2006.239.08:03:20.00:data_valid=off 2006.239.08:03:20.00:postob 2006.239.08:03:20.14/cable/+6.4150E-03 2006.239.08:03:20.14/wx/25.15,1011.6,79 2006.239.08:03:21.08/fmout-gps/S +4.42E-07 2006.239.08:03:21.08:scan_name=239-0804,k06239,60 2006.239.08:03:21.09:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.239.08:03:21.14#flagr#flagr/antenna,new-source 2006.239.08:03:22.14:checkk5 2006.239.08:03:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:03:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:03:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:03:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:03:24.00/chk_obsdata//k5ts1/T2390802??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:03:24.38/chk_obsdata//k5ts2/T2390802??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:03:24.75/chk_obsdata//k5ts3/T2390802??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:03:25.12/chk_obsdata//k5ts4/T2390802??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:03:25.81/k5log//k5ts1_log_newline 2006.239.08:03:26.50/k5log//k5ts2_log_newline 2006.239.08:03:27.19/k5log//k5ts3_log_newline 2006.239.08:03:27.90/k5log//k5ts4_log_newline 2006.239.08:03:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:03:27.92:4f8m12a=2 2006.239.08:03:27.92$4f8m12a/echo=on 2006.239.08:03:27.92$4f8m12a/pcalon 2006.239.08:03:27.92$pcalon/"no phase cal control is implemented here 2006.239.08:03:27.92$4f8m12a/"tpicd=stop 2006.239.08:03:27.92$4f8m12a/vc4f8 2006.239.08:03:27.92$vc4f8/valo=1,532.99 2006.239.08:03:27.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.08:03:27.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.08:03:27.93#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:27.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:27.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:27.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:27.93#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:03:27.93#ibcon#first serial, iclass 20, count 0 2006.239.08:03:27.93#ibcon#enter sib2, iclass 20, count 0 2006.239.08:03:27.93#ibcon#flushed, iclass 20, count 0 2006.239.08:03:27.93#ibcon#about to write, iclass 20, count 0 2006.239.08:03:27.93#ibcon#wrote, iclass 20, count 0 2006.239.08:03:27.93#ibcon#about to read 3, iclass 20, count 0 2006.239.08:03:27.97#ibcon#read 3, iclass 20, count 0 2006.239.08:03:27.97#ibcon#about to read 4, iclass 20, count 0 2006.239.08:03:27.97#ibcon#read 4, iclass 20, count 0 2006.239.08:03:27.97#ibcon#about to read 5, iclass 20, count 0 2006.239.08:03:27.97#ibcon#read 5, iclass 20, count 0 2006.239.08:03:27.97#ibcon#about to read 6, iclass 20, count 0 2006.239.08:03:27.97#ibcon#read 6, iclass 20, count 0 2006.239.08:03:27.97#ibcon#end of sib2, iclass 20, count 0 2006.239.08:03:27.97#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:03:27.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:03:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:03:27.97#ibcon#*before write, iclass 20, count 0 2006.239.08:03:27.97#ibcon#enter sib2, iclass 20, count 0 2006.239.08:03:27.97#ibcon#flushed, iclass 20, count 0 2006.239.08:03:27.97#ibcon#about to write, iclass 20, count 0 2006.239.08:03:27.97#ibcon#wrote, iclass 20, count 0 2006.239.08:03:27.97#ibcon#about to read 3, iclass 20, count 0 2006.239.08:03:28.02#ibcon#read 3, iclass 20, count 0 2006.239.08:03:28.02#ibcon#about to read 4, iclass 20, count 0 2006.239.08:03:28.02#ibcon#read 4, iclass 20, count 0 2006.239.08:03:28.02#ibcon#about to read 5, iclass 20, count 0 2006.239.08:03:28.02#ibcon#read 5, iclass 20, count 0 2006.239.08:03:28.02#ibcon#about to read 6, iclass 20, count 0 2006.239.08:03:28.02#ibcon#read 6, iclass 20, count 0 2006.239.08:03:28.02#ibcon#end of sib2, iclass 20, count 0 2006.239.08:03:28.02#ibcon#*after write, iclass 20, count 0 2006.239.08:03:28.02#ibcon#*before return 0, iclass 20, count 0 2006.239.08:03:28.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:28.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:28.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:03:28.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:03:28.02$vc4f8/va=1,8 2006.239.08:03:28.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.08:03:28.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.08:03:28.02#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:28.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:28.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:28.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:28.02#ibcon#enter wrdev, iclass 22, count 2 2006.239.08:03:28.02#ibcon#first serial, iclass 22, count 2 2006.239.08:03:28.02#ibcon#enter sib2, iclass 22, count 2 2006.239.08:03:28.02#ibcon#flushed, iclass 22, count 2 2006.239.08:03:28.02#ibcon#about to write, iclass 22, count 2 2006.239.08:03:28.02#ibcon#wrote, iclass 22, count 2 2006.239.08:03:28.02#ibcon#about to read 3, iclass 22, count 2 2006.239.08:03:28.04#ibcon#read 3, iclass 22, count 2 2006.239.08:03:28.04#ibcon#about to read 4, iclass 22, count 2 2006.239.08:03:28.04#ibcon#read 4, iclass 22, count 2 2006.239.08:03:28.04#ibcon#about to read 5, iclass 22, count 2 2006.239.08:03:28.04#ibcon#read 5, iclass 22, count 2 2006.239.08:03:28.04#ibcon#about to read 6, iclass 22, count 2 2006.239.08:03:28.04#ibcon#read 6, iclass 22, count 2 2006.239.08:03:28.04#ibcon#end of sib2, iclass 22, count 2 2006.239.08:03:28.04#ibcon#*mode == 0, iclass 22, count 2 2006.239.08:03:28.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.08:03:28.04#ibcon#[25=AT01-08\r\n] 2006.239.08:03:28.04#ibcon#*before write, iclass 22, count 2 2006.239.08:03:28.04#ibcon#enter sib2, iclass 22, count 2 2006.239.08:03:28.04#ibcon#flushed, iclass 22, count 2 2006.239.08:03:28.04#ibcon#about to write, iclass 22, count 2 2006.239.08:03:28.04#ibcon#wrote, iclass 22, count 2 2006.239.08:03:28.04#ibcon#about to read 3, iclass 22, count 2 2006.239.08:03:28.07#ibcon#read 3, iclass 22, count 2 2006.239.08:03:28.07#ibcon#about to read 4, iclass 22, count 2 2006.239.08:03:28.07#ibcon#read 4, iclass 22, count 2 2006.239.08:03:28.07#ibcon#about to read 5, iclass 22, count 2 2006.239.08:03:28.07#ibcon#read 5, iclass 22, count 2 2006.239.08:03:28.07#ibcon#about to read 6, iclass 22, count 2 2006.239.08:03:28.07#ibcon#read 6, iclass 22, count 2 2006.239.08:03:28.07#ibcon#end of sib2, iclass 22, count 2 2006.239.08:03:28.07#ibcon#*after write, iclass 22, count 2 2006.239.08:03:28.07#ibcon#*before return 0, iclass 22, count 2 2006.239.08:03:28.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:28.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:28.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.08:03:28.07#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:28.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:28.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:28.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:28.19#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:03:28.19#ibcon#first serial, iclass 22, count 0 2006.239.08:03:28.19#ibcon#enter sib2, iclass 22, count 0 2006.239.08:03:28.19#ibcon#flushed, iclass 22, count 0 2006.239.08:03:28.19#ibcon#about to write, iclass 22, count 0 2006.239.08:03:28.19#ibcon#wrote, iclass 22, count 0 2006.239.08:03:28.19#ibcon#about to read 3, iclass 22, count 0 2006.239.08:03:28.21#ibcon#read 3, iclass 22, count 0 2006.239.08:03:28.21#ibcon#about to read 4, iclass 22, count 0 2006.239.08:03:28.21#ibcon#read 4, iclass 22, count 0 2006.239.08:03:28.21#ibcon#about to read 5, iclass 22, count 0 2006.239.08:03:28.21#ibcon#read 5, iclass 22, count 0 2006.239.08:03:28.21#ibcon#about to read 6, iclass 22, count 0 2006.239.08:03:28.21#ibcon#read 6, iclass 22, count 0 2006.239.08:03:28.21#ibcon#end of sib2, iclass 22, count 0 2006.239.08:03:28.21#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:03:28.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:03:28.21#ibcon#[25=USB\r\n] 2006.239.08:03:28.21#ibcon#*before write, iclass 22, count 0 2006.239.08:03:28.21#ibcon#enter sib2, iclass 22, count 0 2006.239.08:03:28.21#ibcon#flushed, iclass 22, count 0 2006.239.08:03:28.21#ibcon#about to write, iclass 22, count 0 2006.239.08:03:28.21#ibcon#wrote, iclass 22, count 0 2006.239.08:03:28.21#ibcon#about to read 3, iclass 22, count 0 2006.239.08:03:28.24#ibcon#read 3, iclass 22, count 0 2006.239.08:03:28.24#ibcon#about to read 4, iclass 22, count 0 2006.239.08:03:28.24#ibcon#read 4, iclass 22, count 0 2006.239.08:03:28.24#ibcon#about to read 5, iclass 22, count 0 2006.239.08:03:28.24#ibcon#read 5, iclass 22, count 0 2006.239.08:03:28.24#ibcon#about to read 6, iclass 22, count 0 2006.239.08:03:28.24#ibcon#read 6, iclass 22, count 0 2006.239.08:03:28.24#ibcon#end of sib2, iclass 22, count 0 2006.239.08:03:28.24#ibcon#*after write, iclass 22, count 0 2006.239.08:03:28.24#ibcon#*before return 0, iclass 22, count 0 2006.239.08:03:28.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:28.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:28.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:03:28.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:03:28.24$vc4f8/valo=2,572.99 2006.239.08:03:28.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.08:03:28.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.08:03:28.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:28.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:28.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:28.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:28.24#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:03:28.24#ibcon#first serial, iclass 24, count 0 2006.239.08:03:28.24#ibcon#enter sib2, iclass 24, count 0 2006.239.08:03:28.24#ibcon#flushed, iclass 24, count 0 2006.239.08:03:28.24#ibcon#about to write, iclass 24, count 0 2006.239.08:03:28.24#ibcon#wrote, iclass 24, count 0 2006.239.08:03:28.24#ibcon#about to read 3, iclass 24, count 0 2006.239.08:03:28.26#ibcon#read 3, iclass 24, count 0 2006.239.08:03:28.26#ibcon#about to read 4, iclass 24, count 0 2006.239.08:03:28.26#ibcon#read 4, iclass 24, count 0 2006.239.08:03:28.26#ibcon#about to read 5, iclass 24, count 0 2006.239.08:03:28.26#ibcon#read 5, iclass 24, count 0 2006.239.08:03:28.26#ibcon#about to read 6, iclass 24, count 0 2006.239.08:03:28.26#ibcon#read 6, iclass 24, count 0 2006.239.08:03:28.26#ibcon#end of sib2, iclass 24, count 0 2006.239.08:03:28.26#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:03:28.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:03:28.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:03:28.26#ibcon#*before write, iclass 24, count 0 2006.239.08:03:28.26#ibcon#enter sib2, iclass 24, count 0 2006.239.08:03:28.26#ibcon#flushed, iclass 24, count 0 2006.239.08:03:28.26#ibcon#about to write, iclass 24, count 0 2006.239.08:03:28.26#ibcon#wrote, iclass 24, count 0 2006.239.08:03:28.26#ibcon#about to read 3, iclass 24, count 0 2006.239.08:03:28.30#ibcon#read 3, iclass 24, count 0 2006.239.08:03:28.30#ibcon#about to read 4, iclass 24, count 0 2006.239.08:03:28.30#ibcon#read 4, iclass 24, count 0 2006.239.08:03:28.30#ibcon#about to read 5, iclass 24, count 0 2006.239.08:03:28.30#ibcon#read 5, iclass 24, count 0 2006.239.08:03:28.30#ibcon#about to read 6, iclass 24, count 0 2006.239.08:03:28.30#ibcon#read 6, iclass 24, count 0 2006.239.08:03:28.30#ibcon#end of sib2, iclass 24, count 0 2006.239.08:03:28.30#ibcon#*after write, iclass 24, count 0 2006.239.08:03:28.30#ibcon#*before return 0, iclass 24, count 0 2006.239.08:03:28.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:28.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:28.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:03:28.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:03:28.30$vc4f8/va=2,7 2006.239.08:03:28.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.08:03:28.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.08:03:28.30#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:28.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:28.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:28.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:28.36#ibcon#enter wrdev, iclass 26, count 2 2006.239.08:03:28.36#ibcon#first serial, iclass 26, count 2 2006.239.08:03:28.36#ibcon#enter sib2, iclass 26, count 2 2006.239.08:03:28.36#ibcon#flushed, iclass 26, count 2 2006.239.08:03:28.36#ibcon#about to write, iclass 26, count 2 2006.239.08:03:28.36#ibcon#wrote, iclass 26, count 2 2006.239.08:03:28.36#ibcon#about to read 3, iclass 26, count 2 2006.239.08:03:28.38#ibcon#read 3, iclass 26, count 2 2006.239.08:03:28.38#ibcon#about to read 4, iclass 26, count 2 2006.239.08:03:28.38#ibcon#read 4, iclass 26, count 2 2006.239.08:03:28.38#ibcon#about to read 5, iclass 26, count 2 2006.239.08:03:28.38#ibcon#read 5, iclass 26, count 2 2006.239.08:03:28.38#ibcon#about to read 6, iclass 26, count 2 2006.239.08:03:28.38#ibcon#read 6, iclass 26, count 2 2006.239.08:03:28.38#ibcon#end of sib2, iclass 26, count 2 2006.239.08:03:28.38#ibcon#*mode == 0, iclass 26, count 2 2006.239.08:03:28.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.08:03:28.38#ibcon#[25=AT02-07\r\n] 2006.239.08:03:28.38#ibcon#*before write, iclass 26, count 2 2006.239.08:03:28.38#ibcon#enter sib2, iclass 26, count 2 2006.239.08:03:28.38#ibcon#flushed, iclass 26, count 2 2006.239.08:03:28.38#ibcon#about to write, iclass 26, count 2 2006.239.08:03:28.38#ibcon#wrote, iclass 26, count 2 2006.239.08:03:28.38#ibcon#about to read 3, iclass 26, count 2 2006.239.08:03:28.41#ibcon#read 3, iclass 26, count 2 2006.239.08:03:28.41#ibcon#about to read 4, iclass 26, count 2 2006.239.08:03:28.41#ibcon#read 4, iclass 26, count 2 2006.239.08:03:28.41#ibcon#about to read 5, iclass 26, count 2 2006.239.08:03:28.41#ibcon#read 5, iclass 26, count 2 2006.239.08:03:28.41#ibcon#about to read 6, iclass 26, count 2 2006.239.08:03:28.41#ibcon#read 6, iclass 26, count 2 2006.239.08:03:28.41#ibcon#end of sib2, iclass 26, count 2 2006.239.08:03:28.41#ibcon#*after write, iclass 26, count 2 2006.239.08:03:28.41#ibcon#*before return 0, iclass 26, count 2 2006.239.08:03:28.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:28.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:28.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.08:03:28.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:28.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:28.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:28.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:28.53#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:03:28.53#ibcon#first serial, iclass 26, count 0 2006.239.08:03:28.53#ibcon#enter sib2, iclass 26, count 0 2006.239.08:03:28.53#ibcon#flushed, iclass 26, count 0 2006.239.08:03:28.53#ibcon#about to write, iclass 26, count 0 2006.239.08:03:28.53#ibcon#wrote, iclass 26, count 0 2006.239.08:03:28.53#ibcon#about to read 3, iclass 26, count 0 2006.239.08:03:28.55#ibcon#read 3, iclass 26, count 0 2006.239.08:03:28.55#ibcon#about to read 4, iclass 26, count 0 2006.239.08:03:28.55#ibcon#read 4, iclass 26, count 0 2006.239.08:03:28.55#ibcon#about to read 5, iclass 26, count 0 2006.239.08:03:28.55#ibcon#read 5, iclass 26, count 0 2006.239.08:03:28.55#ibcon#about to read 6, iclass 26, count 0 2006.239.08:03:28.55#ibcon#read 6, iclass 26, count 0 2006.239.08:03:28.55#ibcon#end of sib2, iclass 26, count 0 2006.239.08:03:28.55#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:03:28.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:03:28.55#ibcon#[25=USB\r\n] 2006.239.08:03:28.55#ibcon#*before write, iclass 26, count 0 2006.239.08:03:28.55#ibcon#enter sib2, iclass 26, count 0 2006.239.08:03:28.55#ibcon#flushed, iclass 26, count 0 2006.239.08:03:28.55#ibcon#about to write, iclass 26, count 0 2006.239.08:03:28.55#ibcon#wrote, iclass 26, count 0 2006.239.08:03:28.55#ibcon#about to read 3, iclass 26, count 0 2006.239.08:03:28.58#ibcon#read 3, iclass 26, count 0 2006.239.08:03:28.58#ibcon#about to read 4, iclass 26, count 0 2006.239.08:03:28.58#ibcon#read 4, iclass 26, count 0 2006.239.08:03:28.58#ibcon#about to read 5, iclass 26, count 0 2006.239.08:03:28.58#ibcon#read 5, iclass 26, count 0 2006.239.08:03:28.58#ibcon#about to read 6, iclass 26, count 0 2006.239.08:03:28.58#ibcon#read 6, iclass 26, count 0 2006.239.08:03:28.58#ibcon#end of sib2, iclass 26, count 0 2006.239.08:03:28.58#ibcon#*after write, iclass 26, count 0 2006.239.08:03:28.58#ibcon#*before return 0, iclass 26, count 0 2006.239.08:03:28.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:28.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:28.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:03:28.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:03:28.58$vc4f8/valo=3,672.99 2006.239.08:03:28.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:03:28.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:03:28.58#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:28.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:28.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:28.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:28.58#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:03:28.58#ibcon#first serial, iclass 28, count 0 2006.239.08:03:28.58#ibcon#enter sib2, iclass 28, count 0 2006.239.08:03:28.58#ibcon#flushed, iclass 28, count 0 2006.239.08:03:28.58#ibcon#about to write, iclass 28, count 0 2006.239.08:03:28.58#ibcon#wrote, iclass 28, count 0 2006.239.08:03:28.58#ibcon#about to read 3, iclass 28, count 0 2006.239.08:03:28.60#ibcon#read 3, iclass 28, count 0 2006.239.08:03:28.60#ibcon#about to read 4, iclass 28, count 0 2006.239.08:03:28.60#ibcon#read 4, iclass 28, count 0 2006.239.08:03:28.60#ibcon#about to read 5, iclass 28, count 0 2006.239.08:03:28.60#ibcon#read 5, iclass 28, count 0 2006.239.08:03:28.60#ibcon#about to read 6, iclass 28, count 0 2006.239.08:03:28.60#ibcon#read 6, iclass 28, count 0 2006.239.08:03:28.60#ibcon#end of sib2, iclass 28, count 0 2006.239.08:03:28.60#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:03:28.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:03:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:03:28.60#ibcon#*before write, iclass 28, count 0 2006.239.08:03:28.60#ibcon#enter sib2, iclass 28, count 0 2006.239.08:03:28.60#ibcon#flushed, iclass 28, count 0 2006.239.08:03:28.60#ibcon#about to write, iclass 28, count 0 2006.239.08:03:28.60#ibcon#wrote, iclass 28, count 0 2006.239.08:03:28.60#ibcon#about to read 3, iclass 28, count 0 2006.239.08:03:28.64#ibcon#read 3, iclass 28, count 0 2006.239.08:03:28.64#ibcon#about to read 4, iclass 28, count 0 2006.239.08:03:28.64#ibcon#read 4, iclass 28, count 0 2006.239.08:03:28.64#ibcon#about to read 5, iclass 28, count 0 2006.239.08:03:28.64#ibcon#read 5, iclass 28, count 0 2006.239.08:03:28.64#ibcon#about to read 6, iclass 28, count 0 2006.239.08:03:28.64#ibcon#read 6, iclass 28, count 0 2006.239.08:03:28.64#ibcon#end of sib2, iclass 28, count 0 2006.239.08:03:28.64#ibcon#*after write, iclass 28, count 0 2006.239.08:03:28.64#ibcon#*before return 0, iclass 28, count 0 2006.239.08:03:28.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:28.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:28.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:03:28.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:03:28.64$vc4f8/va=3,7 2006.239.08:03:28.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.08:03:28.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.08:03:28.64#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:28.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:28.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:28.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:28.70#ibcon#enter wrdev, iclass 30, count 2 2006.239.08:03:28.70#ibcon#first serial, iclass 30, count 2 2006.239.08:03:28.70#ibcon#enter sib2, iclass 30, count 2 2006.239.08:03:28.70#ibcon#flushed, iclass 30, count 2 2006.239.08:03:28.70#ibcon#about to write, iclass 30, count 2 2006.239.08:03:28.70#ibcon#wrote, iclass 30, count 2 2006.239.08:03:28.70#ibcon#about to read 3, iclass 30, count 2 2006.239.08:03:28.72#ibcon#read 3, iclass 30, count 2 2006.239.08:03:28.72#ibcon#about to read 4, iclass 30, count 2 2006.239.08:03:28.72#ibcon#read 4, iclass 30, count 2 2006.239.08:03:28.72#ibcon#about to read 5, iclass 30, count 2 2006.239.08:03:28.72#ibcon#read 5, iclass 30, count 2 2006.239.08:03:28.72#ibcon#about to read 6, iclass 30, count 2 2006.239.08:03:28.72#ibcon#read 6, iclass 30, count 2 2006.239.08:03:28.72#ibcon#end of sib2, iclass 30, count 2 2006.239.08:03:28.72#ibcon#*mode == 0, iclass 30, count 2 2006.239.08:03:28.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.08:03:28.72#ibcon#[25=AT03-07\r\n] 2006.239.08:03:28.72#ibcon#*before write, iclass 30, count 2 2006.239.08:03:28.72#ibcon#enter sib2, iclass 30, count 2 2006.239.08:03:28.72#ibcon#flushed, iclass 30, count 2 2006.239.08:03:28.72#ibcon#about to write, iclass 30, count 2 2006.239.08:03:28.72#ibcon#wrote, iclass 30, count 2 2006.239.08:03:28.72#ibcon#about to read 3, iclass 30, count 2 2006.239.08:03:28.75#ibcon#read 3, iclass 30, count 2 2006.239.08:03:28.75#ibcon#about to read 4, iclass 30, count 2 2006.239.08:03:28.75#ibcon#read 4, iclass 30, count 2 2006.239.08:03:28.75#ibcon#about to read 5, iclass 30, count 2 2006.239.08:03:28.75#ibcon#read 5, iclass 30, count 2 2006.239.08:03:28.75#ibcon#about to read 6, iclass 30, count 2 2006.239.08:03:28.75#ibcon#read 6, iclass 30, count 2 2006.239.08:03:28.75#ibcon#end of sib2, iclass 30, count 2 2006.239.08:03:28.75#ibcon#*after write, iclass 30, count 2 2006.239.08:03:28.75#ibcon#*before return 0, iclass 30, count 2 2006.239.08:03:28.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:28.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:28.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.08:03:28.75#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:28.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:28.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:28.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:28.87#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:03:28.87#ibcon#first serial, iclass 30, count 0 2006.239.08:03:28.87#ibcon#enter sib2, iclass 30, count 0 2006.239.08:03:28.87#ibcon#flushed, iclass 30, count 0 2006.239.08:03:28.87#ibcon#about to write, iclass 30, count 0 2006.239.08:03:28.87#ibcon#wrote, iclass 30, count 0 2006.239.08:03:28.87#ibcon#about to read 3, iclass 30, count 0 2006.239.08:03:28.89#ibcon#read 3, iclass 30, count 0 2006.239.08:03:28.89#ibcon#about to read 4, iclass 30, count 0 2006.239.08:03:28.89#ibcon#read 4, iclass 30, count 0 2006.239.08:03:28.89#ibcon#about to read 5, iclass 30, count 0 2006.239.08:03:28.89#ibcon#read 5, iclass 30, count 0 2006.239.08:03:28.89#ibcon#about to read 6, iclass 30, count 0 2006.239.08:03:28.89#ibcon#read 6, iclass 30, count 0 2006.239.08:03:28.89#ibcon#end of sib2, iclass 30, count 0 2006.239.08:03:28.89#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:03:28.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:03:28.89#ibcon#[25=USB\r\n] 2006.239.08:03:28.89#ibcon#*before write, iclass 30, count 0 2006.239.08:03:28.89#ibcon#enter sib2, iclass 30, count 0 2006.239.08:03:28.89#ibcon#flushed, iclass 30, count 0 2006.239.08:03:28.89#ibcon#about to write, iclass 30, count 0 2006.239.08:03:28.89#ibcon#wrote, iclass 30, count 0 2006.239.08:03:28.89#ibcon#about to read 3, iclass 30, count 0 2006.239.08:03:28.92#ibcon#read 3, iclass 30, count 0 2006.239.08:03:28.92#ibcon#about to read 4, iclass 30, count 0 2006.239.08:03:28.92#ibcon#read 4, iclass 30, count 0 2006.239.08:03:28.92#ibcon#about to read 5, iclass 30, count 0 2006.239.08:03:28.92#ibcon#read 5, iclass 30, count 0 2006.239.08:03:28.92#ibcon#about to read 6, iclass 30, count 0 2006.239.08:03:28.92#ibcon#read 6, iclass 30, count 0 2006.239.08:03:28.92#ibcon#end of sib2, iclass 30, count 0 2006.239.08:03:28.92#ibcon#*after write, iclass 30, count 0 2006.239.08:03:28.92#ibcon#*before return 0, iclass 30, count 0 2006.239.08:03:28.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:28.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:28.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:03:28.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:03:28.92$vc4f8/valo=4,832.99 2006.239.08:03:28.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.08:03:28.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.08:03:28.92#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:28.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:28.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:28.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:28.92#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:03:28.92#ibcon#first serial, iclass 32, count 0 2006.239.08:03:28.92#ibcon#enter sib2, iclass 32, count 0 2006.239.08:03:28.92#ibcon#flushed, iclass 32, count 0 2006.239.08:03:28.92#ibcon#about to write, iclass 32, count 0 2006.239.08:03:28.92#ibcon#wrote, iclass 32, count 0 2006.239.08:03:28.92#ibcon#about to read 3, iclass 32, count 0 2006.239.08:03:28.94#ibcon#read 3, iclass 32, count 0 2006.239.08:03:28.94#ibcon#about to read 4, iclass 32, count 0 2006.239.08:03:28.94#ibcon#read 4, iclass 32, count 0 2006.239.08:03:28.94#ibcon#about to read 5, iclass 32, count 0 2006.239.08:03:28.94#ibcon#read 5, iclass 32, count 0 2006.239.08:03:28.94#ibcon#about to read 6, iclass 32, count 0 2006.239.08:03:28.94#ibcon#read 6, iclass 32, count 0 2006.239.08:03:28.94#ibcon#end of sib2, iclass 32, count 0 2006.239.08:03:28.94#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:03:28.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:03:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:03:28.94#ibcon#*before write, iclass 32, count 0 2006.239.08:03:28.94#ibcon#enter sib2, iclass 32, count 0 2006.239.08:03:28.94#ibcon#flushed, iclass 32, count 0 2006.239.08:03:28.94#ibcon#about to write, iclass 32, count 0 2006.239.08:03:28.94#ibcon#wrote, iclass 32, count 0 2006.239.08:03:28.94#ibcon#about to read 3, iclass 32, count 0 2006.239.08:03:28.98#ibcon#read 3, iclass 32, count 0 2006.239.08:03:28.98#ibcon#about to read 4, iclass 32, count 0 2006.239.08:03:28.98#ibcon#read 4, iclass 32, count 0 2006.239.08:03:28.98#ibcon#about to read 5, iclass 32, count 0 2006.239.08:03:28.98#ibcon#read 5, iclass 32, count 0 2006.239.08:03:28.98#ibcon#about to read 6, iclass 32, count 0 2006.239.08:03:28.98#ibcon#read 6, iclass 32, count 0 2006.239.08:03:28.98#ibcon#end of sib2, iclass 32, count 0 2006.239.08:03:28.98#ibcon#*after write, iclass 32, count 0 2006.239.08:03:28.98#ibcon#*before return 0, iclass 32, count 0 2006.239.08:03:28.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:28.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:28.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:03:28.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:03:28.98$vc4f8/va=4,7 2006.239.08:03:28.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.08:03:28.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.08:03:28.98#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:28.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:29.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:29.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:29.04#ibcon#enter wrdev, iclass 34, count 2 2006.239.08:03:29.04#ibcon#first serial, iclass 34, count 2 2006.239.08:03:29.04#ibcon#enter sib2, iclass 34, count 2 2006.239.08:03:29.04#ibcon#flushed, iclass 34, count 2 2006.239.08:03:29.04#ibcon#about to write, iclass 34, count 2 2006.239.08:03:29.04#ibcon#wrote, iclass 34, count 2 2006.239.08:03:29.04#ibcon#about to read 3, iclass 34, count 2 2006.239.08:03:29.06#ibcon#read 3, iclass 34, count 2 2006.239.08:03:29.06#ibcon#about to read 4, iclass 34, count 2 2006.239.08:03:29.06#ibcon#read 4, iclass 34, count 2 2006.239.08:03:29.06#ibcon#about to read 5, iclass 34, count 2 2006.239.08:03:29.06#ibcon#read 5, iclass 34, count 2 2006.239.08:03:29.06#ibcon#about to read 6, iclass 34, count 2 2006.239.08:03:29.06#ibcon#read 6, iclass 34, count 2 2006.239.08:03:29.06#ibcon#end of sib2, iclass 34, count 2 2006.239.08:03:29.06#ibcon#*mode == 0, iclass 34, count 2 2006.239.08:03:29.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.08:03:29.06#ibcon#[25=AT04-07\r\n] 2006.239.08:03:29.06#ibcon#*before write, iclass 34, count 2 2006.239.08:03:29.06#ibcon#enter sib2, iclass 34, count 2 2006.239.08:03:29.06#ibcon#flushed, iclass 34, count 2 2006.239.08:03:29.06#ibcon#about to write, iclass 34, count 2 2006.239.08:03:29.06#ibcon#wrote, iclass 34, count 2 2006.239.08:03:29.06#ibcon#about to read 3, iclass 34, count 2 2006.239.08:03:29.09#ibcon#read 3, iclass 34, count 2 2006.239.08:03:29.09#ibcon#about to read 4, iclass 34, count 2 2006.239.08:03:29.09#ibcon#read 4, iclass 34, count 2 2006.239.08:03:29.09#ibcon#about to read 5, iclass 34, count 2 2006.239.08:03:29.09#ibcon#read 5, iclass 34, count 2 2006.239.08:03:29.09#ibcon#about to read 6, iclass 34, count 2 2006.239.08:03:29.09#ibcon#read 6, iclass 34, count 2 2006.239.08:03:29.09#ibcon#end of sib2, iclass 34, count 2 2006.239.08:03:29.09#ibcon#*after write, iclass 34, count 2 2006.239.08:03:29.09#ibcon#*before return 0, iclass 34, count 2 2006.239.08:03:29.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:29.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:29.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.08:03:29.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:29.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:29.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:29.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:29.21#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:03:29.21#ibcon#first serial, iclass 34, count 0 2006.239.08:03:29.21#ibcon#enter sib2, iclass 34, count 0 2006.239.08:03:29.21#ibcon#flushed, iclass 34, count 0 2006.239.08:03:29.21#ibcon#about to write, iclass 34, count 0 2006.239.08:03:29.21#ibcon#wrote, iclass 34, count 0 2006.239.08:03:29.21#ibcon#about to read 3, iclass 34, count 0 2006.239.08:03:29.23#ibcon#read 3, iclass 34, count 0 2006.239.08:03:29.23#ibcon#about to read 4, iclass 34, count 0 2006.239.08:03:29.23#ibcon#read 4, iclass 34, count 0 2006.239.08:03:29.23#ibcon#about to read 5, iclass 34, count 0 2006.239.08:03:29.23#ibcon#read 5, iclass 34, count 0 2006.239.08:03:29.23#ibcon#about to read 6, iclass 34, count 0 2006.239.08:03:29.23#ibcon#read 6, iclass 34, count 0 2006.239.08:03:29.23#ibcon#end of sib2, iclass 34, count 0 2006.239.08:03:29.23#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:03:29.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:03:29.23#ibcon#[25=USB\r\n] 2006.239.08:03:29.23#ibcon#*before write, iclass 34, count 0 2006.239.08:03:29.23#ibcon#enter sib2, iclass 34, count 0 2006.239.08:03:29.23#ibcon#flushed, iclass 34, count 0 2006.239.08:03:29.23#ibcon#about to write, iclass 34, count 0 2006.239.08:03:29.23#ibcon#wrote, iclass 34, count 0 2006.239.08:03:29.23#ibcon#about to read 3, iclass 34, count 0 2006.239.08:03:29.26#ibcon#read 3, iclass 34, count 0 2006.239.08:03:29.26#ibcon#about to read 4, iclass 34, count 0 2006.239.08:03:29.26#ibcon#read 4, iclass 34, count 0 2006.239.08:03:29.26#ibcon#about to read 5, iclass 34, count 0 2006.239.08:03:29.26#ibcon#read 5, iclass 34, count 0 2006.239.08:03:29.26#ibcon#about to read 6, iclass 34, count 0 2006.239.08:03:29.26#ibcon#read 6, iclass 34, count 0 2006.239.08:03:29.26#ibcon#end of sib2, iclass 34, count 0 2006.239.08:03:29.26#ibcon#*after write, iclass 34, count 0 2006.239.08:03:29.26#ibcon#*before return 0, iclass 34, count 0 2006.239.08:03:29.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:29.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:29.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:03:29.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:03:29.26$vc4f8/valo=5,652.99 2006.239.08:03:29.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.08:03:29.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.08:03:29.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:29.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:29.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:29.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:29.26#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:03:29.26#ibcon#first serial, iclass 36, count 0 2006.239.08:03:29.26#ibcon#enter sib2, iclass 36, count 0 2006.239.08:03:29.26#ibcon#flushed, iclass 36, count 0 2006.239.08:03:29.26#ibcon#about to write, iclass 36, count 0 2006.239.08:03:29.26#ibcon#wrote, iclass 36, count 0 2006.239.08:03:29.26#ibcon#about to read 3, iclass 36, count 0 2006.239.08:03:29.28#ibcon#read 3, iclass 36, count 0 2006.239.08:03:29.28#ibcon#about to read 4, iclass 36, count 0 2006.239.08:03:29.28#ibcon#read 4, iclass 36, count 0 2006.239.08:03:29.28#ibcon#about to read 5, iclass 36, count 0 2006.239.08:03:29.28#ibcon#read 5, iclass 36, count 0 2006.239.08:03:29.28#ibcon#about to read 6, iclass 36, count 0 2006.239.08:03:29.28#ibcon#read 6, iclass 36, count 0 2006.239.08:03:29.28#ibcon#end of sib2, iclass 36, count 0 2006.239.08:03:29.28#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:03:29.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:03:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:03:29.28#ibcon#*before write, iclass 36, count 0 2006.239.08:03:29.28#ibcon#enter sib2, iclass 36, count 0 2006.239.08:03:29.28#ibcon#flushed, iclass 36, count 0 2006.239.08:03:29.28#ibcon#about to write, iclass 36, count 0 2006.239.08:03:29.28#ibcon#wrote, iclass 36, count 0 2006.239.08:03:29.28#ibcon#about to read 3, iclass 36, count 0 2006.239.08:03:29.32#ibcon#read 3, iclass 36, count 0 2006.239.08:03:29.32#ibcon#about to read 4, iclass 36, count 0 2006.239.08:03:29.32#ibcon#read 4, iclass 36, count 0 2006.239.08:03:29.32#ibcon#about to read 5, iclass 36, count 0 2006.239.08:03:29.32#ibcon#read 5, iclass 36, count 0 2006.239.08:03:29.32#ibcon#about to read 6, iclass 36, count 0 2006.239.08:03:29.32#ibcon#read 6, iclass 36, count 0 2006.239.08:03:29.32#ibcon#end of sib2, iclass 36, count 0 2006.239.08:03:29.32#ibcon#*after write, iclass 36, count 0 2006.239.08:03:29.32#ibcon#*before return 0, iclass 36, count 0 2006.239.08:03:29.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:29.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:29.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:03:29.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:03:29.32$vc4f8/va=5,8 2006.239.08:03:29.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.08:03:29.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.08:03:29.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:29.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:29.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:29.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:29.38#ibcon#enter wrdev, iclass 38, count 2 2006.239.08:03:29.38#ibcon#first serial, iclass 38, count 2 2006.239.08:03:29.38#ibcon#enter sib2, iclass 38, count 2 2006.239.08:03:29.38#ibcon#flushed, iclass 38, count 2 2006.239.08:03:29.38#ibcon#about to write, iclass 38, count 2 2006.239.08:03:29.38#ibcon#wrote, iclass 38, count 2 2006.239.08:03:29.38#ibcon#about to read 3, iclass 38, count 2 2006.239.08:03:29.40#ibcon#read 3, iclass 38, count 2 2006.239.08:03:29.40#ibcon#about to read 4, iclass 38, count 2 2006.239.08:03:29.40#ibcon#read 4, iclass 38, count 2 2006.239.08:03:29.40#ibcon#about to read 5, iclass 38, count 2 2006.239.08:03:29.40#ibcon#read 5, iclass 38, count 2 2006.239.08:03:29.40#ibcon#about to read 6, iclass 38, count 2 2006.239.08:03:29.40#ibcon#read 6, iclass 38, count 2 2006.239.08:03:29.40#ibcon#end of sib2, iclass 38, count 2 2006.239.08:03:29.40#ibcon#*mode == 0, iclass 38, count 2 2006.239.08:03:29.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.08:03:29.40#ibcon#[25=AT05-08\r\n] 2006.239.08:03:29.40#ibcon#*before write, iclass 38, count 2 2006.239.08:03:29.40#ibcon#enter sib2, iclass 38, count 2 2006.239.08:03:29.40#ibcon#flushed, iclass 38, count 2 2006.239.08:03:29.40#ibcon#about to write, iclass 38, count 2 2006.239.08:03:29.40#ibcon#wrote, iclass 38, count 2 2006.239.08:03:29.40#ibcon#about to read 3, iclass 38, count 2 2006.239.08:03:29.43#ibcon#read 3, iclass 38, count 2 2006.239.08:03:29.43#ibcon#about to read 4, iclass 38, count 2 2006.239.08:03:29.43#ibcon#read 4, iclass 38, count 2 2006.239.08:03:29.43#ibcon#about to read 5, iclass 38, count 2 2006.239.08:03:29.43#ibcon#read 5, iclass 38, count 2 2006.239.08:03:29.43#ibcon#about to read 6, iclass 38, count 2 2006.239.08:03:29.43#ibcon#read 6, iclass 38, count 2 2006.239.08:03:29.43#ibcon#end of sib2, iclass 38, count 2 2006.239.08:03:29.43#ibcon#*after write, iclass 38, count 2 2006.239.08:03:29.43#ibcon#*before return 0, iclass 38, count 2 2006.239.08:03:29.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:29.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:29.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.08:03:29.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:29.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:29.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:29.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:29.55#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:03:29.55#ibcon#first serial, iclass 38, count 0 2006.239.08:03:29.55#ibcon#enter sib2, iclass 38, count 0 2006.239.08:03:29.55#ibcon#flushed, iclass 38, count 0 2006.239.08:03:29.55#ibcon#about to write, iclass 38, count 0 2006.239.08:03:29.55#ibcon#wrote, iclass 38, count 0 2006.239.08:03:29.55#ibcon#about to read 3, iclass 38, count 0 2006.239.08:03:29.57#ibcon#read 3, iclass 38, count 0 2006.239.08:03:29.57#ibcon#about to read 4, iclass 38, count 0 2006.239.08:03:29.57#ibcon#read 4, iclass 38, count 0 2006.239.08:03:29.57#ibcon#about to read 5, iclass 38, count 0 2006.239.08:03:29.57#ibcon#read 5, iclass 38, count 0 2006.239.08:03:29.57#ibcon#about to read 6, iclass 38, count 0 2006.239.08:03:29.57#ibcon#read 6, iclass 38, count 0 2006.239.08:03:29.57#ibcon#end of sib2, iclass 38, count 0 2006.239.08:03:29.57#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:03:29.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:03:29.57#ibcon#[25=USB\r\n] 2006.239.08:03:29.57#ibcon#*before write, iclass 38, count 0 2006.239.08:03:29.57#ibcon#enter sib2, iclass 38, count 0 2006.239.08:03:29.57#ibcon#flushed, iclass 38, count 0 2006.239.08:03:29.57#ibcon#about to write, iclass 38, count 0 2006.239.08:03:29.57#ibcon#wrote, iclass 38, count 0 2006.239.08:03:29.57#ibcon#about to read 3, iclass 38, count 0 2006.239.08:03:29.60#ibcon#read 3, iclass 38, count 0 2006.239.08:03:29.60#ibcon#about to read 4, iclass 38, count 0 2006.239.08:03:29.60#ibcon#read 4, iclass 38, count 0 2006.239.08:03:29.60#ibcon#about to read 5, iclass 38, count 0 2006.239.08:03:29.60#ibcon#read 5, iclass 38, count 0 2006.239.08:03:29.60#ibcon#about to read 6, iclass 38, count 0 2006.239.08:03:29.60#ibcon#read 6, iclass 38, count 0 2006.239.08:03:29.60#ibcon#end of sib2, iclass 38, count 0 2006.239.08:03:29.60#ibcon#*after write, iclass 38, count 0 2006.239.08:03:29.60#ibcon#*before return 0, iclass 38, count 0 2006.239.08:03:29.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:29.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:29.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:03:29.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:03:29.60$vc4f8/valo=6,772.99 2006.239.08:03:29.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.08:03:29.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.08:03:29.60#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:29.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:29.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:29.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:29.60#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:03:29.60#ibcon#first serial, iclass 40, count 0 2006.239.08:03:29.60#ibcon#enter sib2, iclass 40, count 0 2006.239.08:03:29.60#ibcon#flushed, iclass 40, count 0 2006.239.08:03:29.60#ibcon#about to write, iclass 40, count 0 2006.239.08:03:29.60#ibcon#wrote, iclass 40, count 0 2006.239.08:03:29.60#ibcon#about to read 3, iclass 40, count 0 2006.239.08:03:29.62#ibcon#read 3, iclass 40, count 0 2006.239.08:03:29.62#ibcon#about to read 4, iclass 40, count 0 2006.239.08:03:29.62#ibcon#read 4, iclass 40, count 0 2006.239.08:03:29.62#ibcon#about to read 5, iclass 40, count 0 2006.239.08:03:29.62#ibcon#read 5, iclass 40, count 0 2006.239.08:03:29.62#ibcon#about to read 6, iclass 40, count 0 2006.239.08:03:29.62#ibcon#read 6, iclass 40, count 0 2006.239.08:03:29.62#ibcon#end of sib2, iclass 40, count 0 2006.239.08:03:29.62#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:03:29.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:03:29.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:03:29.62#ibcon#*before write, iclass 40, count 0 2006.239.08:03:29.62#ibcon#enter sib2, iclass 40, count 0 2006.239.08:03:29.62#ibcon#flushed, iclass 40, count 0 2006.239.08:03:29.62#ibcon#about to write, iclass 40, count 0 2006.239.08:03:29.62#ibcon#wrote, iclass 40, count 0 2006.239.08:03:29.62#ibcon#about to read 3, iclass 40, count 0 2006.239.08:03:29.66#ibcon#read 3, iclass 40, count 0 2006.239.08:03:29.66#ibcon#about to read 4, iclass 40, count 0 2006.239.08:03:29.66#ibcon#read 4, iclass 40, count 0 2006.239.08:03:29.66#ibcon#about to read 5, iclass 40, count 0 2006.239.08:03:29.66#ibcon#read 5, iclass 40, count 0 2006.239.08:03:29.66#ibcon#about to read 6, iclass 40, count 0 2006.239.08:03:29.66#ibcon#read 6, iclass 40, count 0 2006.239.08:03:29.66#ibcon#end of sib2, iclass 40, count 0 2006.239.08:03:29.66#ibcon#*after write, iclass 40, count 0 2006.239.08:03:29.66#ibcon#*before return 0, iclass 40, count 0 2006.239.08:03:29.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:29.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:29.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:03:29.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:03:29.66$vc4f8/va=6,7 2006.239.08:03:29.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.08:03:29.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.08:03:29.66#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:29.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:03:29.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:03:29.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:03:29.72#ibcon#enter wrdev, iclass 4, count 2 2006.239.08:03:29.72#ibcon#first serial, iclass 4, count 2 2006.239.08:03:29.72#ibcon#enter sib2, iclass 4, count 2 2006.239.08:03:29.72#ibcon#flushed, iclass 4, count 2 2006.239.08:03:29.72#ibcon#about to write, iclass 4, count 2 2006.239.08:03:29.72#ibcon#wrote, iclass 4, count 2 2006.239.08:03:29.72#ibcon#about to read 3, iclass 4, count 2 2006.239.08:03:29.74#ibcon#read 3, iclass 4, count 2 2006.239.08:03:29.74#ibcon#about to read 4, iclass 4, count 2 2006.239.08:03:29.74#ibcon#read 4, iclass 4, count 2 2006.239.08:03:29.74#ibcon#about to read 5, iclass 4, count 2 2006.239.08:03:29.74#ibcon#read 5, iclass 4, count 2 2006.239.08:03:29.74#ibcon#about to read 6, iclass 4, count 2 2006.239.08:03:29.74#ibcon#read 6, iclass 4, count 2 2006.239.08:03:29.74#ibcon#end of sib2, iclass 4, count 2 2006.239.08:03:29.74#ibcon#*mode == 0, iclass 4, count 2 2006.239.08:03:29.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.08:03:29.74#ibcon#[25=AT06-07\r\n] 2006.239.08:03:29.74#ibcon#*before write, iclass 4, count 2 2006.239.08:03:29.74#ibcon#enter sib2, iclass 4, count 2 2006.239.08:03:29.74#ibcon#flushed, iclass 4, count 2 2006.239.08:03:29.74#ibcon#about to write, iclass 4, count 2 2006.239.08:03:29.74#ibcon#wrote, iclass 4, count 2 2006.239.08:03:29.74#ibcon#about to read 3, iclass 4, count 2 2006.239.08:03:29.77#ibcon#read 3, iclass 4, count 2 2006.239.08:03:29.77#ibcon#about to read 4, iclass 4, count 2 2006.239.08:03:29.77#ibcon#read 4, iclass 4, count 2 2006.239.08:03:29.77#ibcon#about to read 5, iclass 4, count 2 2006.239.08:03:29.77#ibcon#read 5, iclass 4, count 2 2006.239.08:03:29.77#ibcon#about to read 6, iclass 4, count 2 2006.239.08:03:29.77#ibcon#read 6, iclass 4, count 2 2006.239.08:03:29.77#ibcon#end of sib2, iclass 4, count 2 2006.239.08:03:29.77#ibcon#*after write, iclass 4, count 2 2006.239.08:03:29.77#ibcon#*before return 0, iclass 4, count 2 2006.239.08:03:29.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:03:29.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:03:29.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.08:03:29.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:29.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:03:29.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:03:29.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:03:29.89#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:03:29.89#ibcon#first serial, iclass 4, count 0 2006.239.08:03:29.89#ibcon#enter sib2, iclass 4, count 0 2006.239.08:03:29.89#ibcon#flushed, iclass 4, count 0 2006.239.08:03:29.89#ibcon#about to write, iclass 4, count 0 2006.239.08:03:29.89#ibcon#wrote, iclass 4, count 0 2006.239.08:03:29.89#ibcon#about to read 3, iclass 4, count 0 2006.239.08:03:29.91#ibcon#read 3, iclass 4, count 0 2006.239.08:03:29.91#ibcon#about to read 4, iclass 4, count 0 2006.239.08:03:29.91#ibcon#read 4, iclass 4, count 0 2006.239.08:03:29.91#ibcon#about to read 5, iclass 4, count 0 2006.239.08:03:29.91#ibcon#read 5, iclass 4, count 0 2006.239.08:03:29.91#ibcon#about to read 6, iclass 4, count 0 2006.239.08:03:29.91#ibcon#read 6, iclass 4, count 0 2006.239.08:03:29.91#ibcon#end of sib2, iclass 4, count 0 2006.239.08:03:29.91#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:03:29.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:03:29.91#ibcon#[25=USB\r\n] 2006.239.08:03:29.91#ibcon#*before write, iclass 4, count 0 2006.239.08:03:29.91#ibcon#enter sib2, iclass 4, count 0 2006.239.08:03:29.91#ibcon#flushed, iclass 4, count 0 2006.239.08:03:29.91#ibcon#about to write, iclass 4, count 0 2006.239.08:03:29.91#ibcon#wrote, iclass 4, count 0 2006.239.08:03:29.91#ibcon#about to read 3, iclass 4, count 0 2006.239.08:03:29.94#ibcon#read 3, iclass 4, count 0 2006.239.08:03:29.94#ibcon#about to read 4, iclass 4, count 0 2006.239.08:03:29.94#ibcon#read 4, iclass 4, count 0 2006.239.08:03:29.94#ibcon#about to read 5, iclass 4, count 0 2006.239.08:03:29.94#ibcon#read 5, iclass 4, count 0 2006.239.08:03:29.94#ibcon#about to read 6, iclass 4, count 0 2006.239.08:03:29.94#ibcon#read 6, iclass 4, count 0 2006.239.08:03:29.94#ibcon#end of sib2, iclass 4, count 0 2006.239.08:03:29.94#ibcon#*after write, iclass 4, count 0 2006.239.08:03:29.94#ibcon#*before return 0, iclass 4, count 0 2006.239.08:03:29.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:03:29.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:03:29.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:03:29.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:03:29.94$vc4f8/valo=7,832.99 2006.239.08:03:29.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.08:03:29.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.08:03:29.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:29.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:03:29.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:03:29.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:03:29.94#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:03:29.94#ibcon#first serial, iclass 6, count 0 2006.239.08:03:29.94#ibcon#enter sib2, iclass 6, count 0 2006.239.08:03:29.94#ibcon#flushed, iclass 6, count 0 2006.239.08:03:29.94#ibcon#about to write, iclass 6, count 0 2006.239.08:03:29.94#ibcon#wrote, iclass 6, count 0 2006.239.08:03:29.94#ibcon#about to read 3, iclass 6, count 0 2006.239.08:03:29.96#ibcon#read 3, iclass 6, count 0 2006.239.08:03:29.96#ibcon#about to read 4, iclass 6, count 0 2006.239.08:03:29.96#ibcon#read 4, iclass 6, count 0 2006.239.08:03:29.96#ibcon#about to read 5, iclass 6, count 0 2006.239.08:03:29.96#ibcon#read 5, iclass 6, count 0 2006.239.08:03:29.96#ibcon#about to read 6, iclass 6, count 0 2006.239.08:03:29.96#ibcon#read 6, iclass 6, count 0 2006.239.08:03:29.96#ibcon#end of sib2, iclass 6, count 0 2006.239.08:03:29.96#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:03:29.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:03:29.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:03:29.96#ibcon#*before write, iclass 6, count 0 2006.239.08:03:29.96#ibcon#enter sib2, iclass 6, count 0 2006.239.08:03:29.96#ibcon#flushed, iclass 6, count 0 2006.239.08:03:29.96#ibcon#about to write, iclass 6, count 0 2006.239.08:03:29.96#ibcon#wrote, iclass 6, count 0 2006.239.08:03:29.96#ibcon#about to read 3, iclass 6, count 0 2006.239.08:03:30.00#ibcon#read 3, iclass 6, count 0 2006.239.08:03:30.00#ibcon#about to read 4, iclass 6, count 0 2006.239.08:03:30.00#ibcon#read 4, iclass 6, count 0 2006.239.08:03:30.00#ibcon#about to read 5, iclass 6, count 0 2006.239.08:03:30.00#ibcon#read 5, iclass 6, count 0 2006.239.08:03:30.00#ibcon#about to read 6, iclass 6, count 0 2006.239.08:03:30.00#ibcon#read 6, iclass 6, count 0 2006.239.08:03:30.00#ibcon#end of sib2, iclass 6, count 0 2006.239.08:03:30.00#ibcon#*after write, iclass 6, count 0 2006.239.08:03:30.00#ibcon#*before return 0, iclass 6, count 0 2006.239.08:03:30.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:03:30.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:03:30.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:03:30.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:03:30.00$vc4f8/va=7,7 2006.239.08:03:30.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.08:03:30.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.08:03:30.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:30.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:03:30.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:03:30.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:03:30.06#ibcon#enter wrdev, iclass 10, count 2 2006.239.08:03:30.06#ibcon#first serial, iclass 10, count 2 2006.239.08:03:30.06#ibcon#enter sib2, iclass 10, count 2 2006.239.08:03:30.06#ibcon#flushed, iclass 10, count 2 2006.239.08:03:30.06#ibcon#about to write, iclass 10, count 2 2006.239.08:03:30.06#ibcon#wrote, iclass 10, count 2 2006.239.08:03:30.06#ibcon#about to read 3, iclass 10, count 2 2006.239.08:03:30.08#ibcon#read 3, iclass 10, count 2 2006.239.08:03:30.08#ibcon#about to read 4, iclass 10, count 2 2006.239.08:03:30.08#ibcon#read 4, iclass 10, count 2 2006.239.08:03:30.08#ibcon#about to read 5, iclass 10, count 2 2006.239.08:03:30.08#ibcon#read 5, iclass 10, count 2 2006.239.08:03:30.08#ibcon#about to read 6, iclass 10, count 2 2006.239.08:03:30.08#ibcon#read 6, iclass 10, count 2 2006.239.08:03:30.08#ibcon#end of sib2, iclass 10, count 2 2006.239.08:03:30.08#ibcon#*mode == 0, iclass 10, count 2 2006.239.08:03:30.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.08:03:30.08#ibcon#[25=AT07-07\r\n] 2006.239.08:03:30.08#ibcon#*before write, iclass 10, count 2 2006.239.08:03:30.08#ibcon#enter sib2, iclass 10, count 2 2006.239.08:03:30.08#ibcon#flushed, iclass 10, count 2 2006.239.08:03:30.08#ibcon#about to write, iclass 10, count 2 2006.239.08:03:30.08#ibcon#wrote, iclass 10, count 2 2006.239.08:03:30.08#ibcon#about to read 3, iclass 10, count 2 2006.239.08:03:30.11#ibcon#read 3, iclass 10, count 2 2006.239.08:03:30.11#ibcon#about to read 4, iclass 10, count 2 2006.239.08:03:30.11#ibcon#read 4, iclass 10, count 2 2006.239.08:03:30.11#ibcon#about to read 5, iclass 10, count 2 2006.239.08:03:30.11#ibcon#read 5, iclass 10, count 2 2006.239.08:03:30.11#ibcon#about to read 6, iclass 10, count 2 2006.239.08:03:30.11#ibcon#read 6, iclass 10, count 2 2006.239.08:03:30.11#ibcon#end of sib2, iclass 10, count 2 2006.239.08:03:30.11#ibcon#*after write, iclass 10, count 2 2006.239.08:03:30.11#ibcon#*before return 0, iclass 10, count 2 2006.239.08:03:30.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:03:30.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:03:30.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.08:03:30.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:30.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:03:30.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:03:30.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:03:30.23#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:03:30.23#ibcon#first serial, iclass 10, count 0 2006.239.08:03:30.23#ibcon#enter sib2, iclass 10, count 0 2006.239.08:03:30.23#ibcon#flushed, iclass 10, count 0 2006.239.08:03:30.23#ibcon#about to write, iclass 10, count 0 2006.239.08:03:30.23#ibcon#wrote, iclass 10, count 0 2006.239.08:03:30.23#ibcon#about to read 3, iclass 10, count 0 2006.239.08:03:30.25#ibcon#read 3, iclass 10, count 0 2006.239.08:03:30.25#ibcon#about to read 4, iclass 10, count 0 2006.239.08:03:30.25#ibcon#read 4, iclass 10, count 0 2006.239.08:03:30.25#ibcon#about to read 5, iclass 10, count 0 2006.239.08:03:30.25#ibcon#read 5, iclass 10, count 0 2006.239.08:03:30.25#ibcon#about to read 6, iclass 10, count 0 2006.239.08:03:30.25#ibcon#read 6, iclass 10, count 0 2006.239.08:03:30.25#ibcon#end of sib2, iclass 10, count 0 2006.239.08:03:30.25#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:03:30.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:03:30.25#ibcon#[25=USB\r\n] 2006.239.08:03:30.25#ibcon#*before write, iclass 10, count 0 2006.239.08:03:30.25#ibcon#enter sib2, iclass 10, count 0 2006.239.08:03:30.25#ibcon#flushed, iclass 10, count 0 2006.239.08:03:30.25#ibcon#about to write, iclass 10, count 0 2006.239.08:03:30.25#ibcon#wrote, iclass 10, count 0 2006.239.08:03:30.25#ibcon#about to read 3, iclass 10, count 0 2006.239.08:03:30.28#ibcon#read 3, iclass 10, count 0 2006.239.08:03:30.28#ibcon#about to read 4, iclass 10, count 0 2006.239.08:03:30.28#ibcon#read 4, iclass 10, count 0 2006.239.08:03:30.28#ibcon#about to read 5, iclass 10, count 0 2006.239.08:03:30.28#ibcon#read 5, iclass 10, count 0 2006.239.08:03:30.28#ibcon#about to read 6, iclass 10, count 0 2006.239.08:03:30.28#ibcon#read 6, iclass 10, count 0 2006.239.08:03:30.28#ibcon#end of sib2, iclass 10, count 0 2006.239.08:03:30.28#ibcon#*after write, iclass 10, count 0 2006.239.08:03:30.28#ibcon#*before return 0, iclass 10, count 0 2006.239.08:03:30.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:03:30.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:03:30.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:03:30.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:03:30.28$vc4f8/valo=8,852.99 2006.239.08:03:30.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.08:03:30.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.08:03:30.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:30.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:03:30.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:03:30.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:03:30.28#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:03:30.28#ibcon#first serial, iclass 12, count 0 2006.239.08:03:30.28#ibcon#enter sib2, iclass 12, count 0 2006.239.08:03:30.28#ibcon#flushed, iclass 12, count 0 2006.239.08:03:30.28#ibcon#about to write, iclass 12, count 0 2006.239.08:03:30.28#ibcon#wrote, iclass 12, count 0 2006.239.08:03:30.28#ibcon#about to read 3, iclass 12, count 0 2006.239.08:03:30.30#ibcon#read 3, iclass 12, count 0 2006.239.08:03:30.30#ibcon#about to read 4, iclass 12, count 0 2006.239.08:03:30.30#ibcon#read 4, iclass 12, count 0 2006.239.08:03:30.30#ibcon#about to read 5, iclass 12, count 0 2006.239.08:03:30.30#ibcon#read 5, iclass 12, count 0 2006.239.08:03:30.30#ibcon#about to read 6, iclass 12, count 0 2006.239.08:03:30.30#ibcon#read 6, iclass 12, count 0 2006.239.08:03:30.30#ibcon#end of sib2, iclass 12, count 0 2006.239.08:03:30.30#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:03:30.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:03:30.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:03:30.30#ibcon#*before write, iclass 12, count 0 2006.239.08:03:30.30#ibcon#enter sib2, iclass 12, count 0 2006.239.08:03:30.30#ibcon#flushed, iclass 12, count 0 2006.239.08:03:30.30#ibcon#about to write, iclass 12, count 0 2006.239.08:03:30.30#ibcon#wrote, iclass 12, count 0 2006.239.08:03:30.30#ibcon#about to read 3, iclass 12, count 0 2006.239.08:03:30.34#ibcon#read 3, iclass 12, count 0 2006.239.08:03:30.34#ibcon#about to read 4, iclass 12, count 0 2006.239.08:03:30.34#ibcon#read 4, iclass 12, count 0 2006.239.08:03:30.34#ibcon#about to read 5, iclass 12, count 0 2006.239.08:03:30.34#ibcon#read 5, iclass 12, count 0 2006.239.08:03:30.34#ibcon#about to read 6, iclass 12, count 0 2006.239.08:03:30.34#ibcon#read 6, iclass 12, count 0 2006.239.08:03:30.34#ibcon#end of sib2, iclass 12, count 0 2006.239.08:03:30.34#ibcon#*after write, iclass 12, count 0 2006.239.08:03:30.34#ibcon#*before return 0, iclass 12, count 0 2006.239.08:03:30.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:03:30.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:03:30.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:03:30.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:03:30.34$vc4f8/va=8,7 2006.239.08:03:30.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.08:03:30.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.08:03:30.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:30.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:03:30.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:03:30.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:03:30.40#ibcon#enter wrdev, iclass 14, count 2 2006.239.08:03:30.40#ibcon#first serial, iclass 14, count 2 2006.239.08:03:30.40#ibcon#enter sib2, iclass 14, count 2 2006.239.08:03:30.40#ibcon#flushed, iclass 14, count 2 2006.239.08:03:30.40#ibcon#about to write, iclass 14, count 2 2006.239.08:03:30.40#ibcon#wrote, iclass 14, count 2 2006.239.08:03:30.40#ibcon#about to read 3, iclass 14, count 2 2006.239.08:03:30.42#ibcon#read 3, iclass 14, count 2 2006.239.08:03:30.42#ibcon#about to read 4, iclass 14, count 2 2006.239.08:03:30.42#ibcon#read 4, iclass 14, count 2 2006.239.08:03:30.42#ibcon#about to read 5, iclass 14, count 2 2006.239.08:03:30.42#ibcon#read 5, iclass 14, count 2 2006.239.08:03:30.42#ibcon#about to read 6, iclass 14, count 2 2006.239.08:03:30.42#ibcon#read 6, iclass 14, count 2 2006.239.08:03:30.42#ibcon#end of sib2, iclass 14, count 2 2006.239.08:03:30.42#ibcon#*mode == 0, iclass 14, count 2 2006.239.08:03:30.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.08:03:30.42#ibcon#[25=AT08-07\r\n] 2006.239.08:03:30.42#ibcon#*before write, iclass 14, count 2 2006.239.08:03:30.42#ibcon#enter sib2, iclass 14, count 2 2006.239.08:03:30.42#ibcon#flushed, iclass 14, count 2 2006.239.08:03:30.42#ibcon#about to write, iclass 14, count 2 2006.239.08:03:30.42#ibcon#wrote, iclass 14, count 2 2006.239.08:03:30.42#ibcon#about to read 3, iclass 14, count 2 2006.239.08:03:30.45#ibcon#read 3, iclass 14, count 2 2006.239.08:03:30.45#ibcon#about to read 4, iclass 14, count 2 2006.239.08:03:30.45#ibcon#read 4, iclass 14, count 2 2006.239.08:03:30.45#ibcon#about to read 5, iclass 14, count 2 2006.239.08:03:30.45#ibcon#read 5, iclass 14, count 2 2006.239.08:03:30.45#ibcon#about to read 6, iclass 14, count 2 2006.239.08:03:30.45#ibcon#read 6, iclass 14, count 2 2006.239.08:03:30.45#ibcon#end of sib2, iclass 14, count 2 2006.239.08:03:30.45#ibcon#*after write, iclass 14, count 2 2006.239.08:03:30.45#ibcon#*before return 0, iclass 14, count 2 2006.239.08:03:30.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:03:30.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:03:30.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.08:03:30.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:30.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:03:30.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:03:30.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:03:30.57#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:03:30.57#ibcon#first serial, iclass 14, count 0 2006.239.08:03:30.57#ibcon#enter sib2, iclass 14, count 0 2006.239.08:03:30.57#ibcon#flushed, iclass 14, count 0 2006.239.08:03:30.57#ibcon#about to write, iclass 14, count 0 2006.239.08:03:30.57#ibcon#wrote, iclass 14, count 0 2006.239.08:03:30.57#ibcon#about to read 3, iclass 14, count 0 2006.239.08:03:30.59#ibcon#read 3, iclass 14, count 0 2006.239.08:03:30.59#ibcon#about to read 4, iclass 14, count 0 2006.239.08:03:30.59#ibcon#read 4, iclass 14, count 0 2006.239.08:03:30.59#ibcon#about to read 5, iclass 14, count 0 2006.239.08:03:30.59#ibcon#read 5, iclass 14, count 0 2006.239.08:03:30.59#ibcon#about to read 6, iclass 14, count 0 2006.239.08:03:30.59#ibcon#read 6, iclass 14, count 0 2006.239.08:03:30.59#ibcon#end of sib2, iclass 14, count 0 2006.239.08:03:30.59#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:03:30.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:03:30.59#ibcon#[25=USB\r\n] 2006.239.08:03:30.59#ibcon#*before write, iclass 14, count 0 2006.239.08:03:30.59#ibcon#enter sib2, iclass 14, count 0 2006.239.08:03:30.59#ibcon#flushed, iclass 14, count 0 2006.239.08:03:30.59#ibcon#about to write, iclass 14, count 0 2006.239.08:03:30.59#ibcon#wrote, iclass 14, count 0 2006.239.08:03:30.59#ibcon#about to read 3, iclass 14, count 0 2006.239.08:03:30.62#ibcon#read 3, iclass 14, count 0 2006.239.08:03:30.62#ibcon#about to read 4, iclass 14, count 0 2006.239.08:03:30.62#ibcon#read 4, iclass 14, count 0 2006.239.08:03:30.62#ibcon#about to read 5, iclass 14, count 0 2006.239.08:03:30.62#ibcon#read 5, iclass 14, count 0 2006.239.08:03:30.62#ibcon#about to read 6, iclass 14, count 0 2006.239.08:03:30.62#ibcon#read 6, iclass 14, count 0 2006.239.08:03:30.62#ibcon#end of sib2, iclass 14, count 0 2006.239.08:03:30.62#ibcon#*after write, iclass 14, count 0 2006.239.08:03:30.62#ibcon#*before return 0, iclass 14, count 0 2006.239.08:03:30.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:03:30.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:03:30.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:03:30.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:03:30.62$vc4f8/vblo=1,632.99 2006.239.08:03:30.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.08:03:30.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.08:03:30.62#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:30.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:03:30.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:03:30.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:03:30.62#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:03:30.62#ibcon#first serial, iclass 16, count 0 2006.239.08:03:30.62#ibcon#enter sib2, iclass 16, count 0 2006.239.08:03:30.62#ibcon#flushed, iclass 16, count 0 2006.239.08:03:30.62#ibcon#about to write, iclass 16, count 0 2006.239.08:03:30.62#ibcon#wrote, iclass 16, count 0 2006.239.08:03:30.62#ibcon#about to read 3, iclass 16, count 0 2006.239.08:03:30.64#ibcon#read 3, iclass 16, count 0 2006.239.08:03:30.64#ibcon#about to read 4, iclass 16, count 0 2006.239.08:03:30.64#ibcon#read 4, iclass 16, count 0 2006.239.08:03:30.64#ibcon#about to read 5, iclass 16, count 0 2006.239.08:03:30.64#ibcon#read 5, iclass 16, count 0 2006.239.08:03:30.64#ibcon#about to read 6, iclass 16, count 0 2006.239.08:03:30.64#ibcon#read 6, iclass 16, count 0 2006.239.08:03:30.64#ibcon#end of sib2, iclass 16, count 0 2006.239.08:03:30.64#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:03:30.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:03:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:03:30.64#ibcon#*before write, iclass 16, count 0 2006.239.08:03:30.64#ibcon#enter sib2, iclass 16, count 0 2006.239.08:03:30.64#ibcon#flushed, iclass 16, count 0 2006.239.08:03:30.64#ibcon#about to write, iclass 16, count 0 2006.239.08:03:30.64#ibcon#wrote, iclass 16, count 0 2006.239.08:03:30.64#ibcon#about to read 3, iclass 16, count 0 2006.239.08:03:30.68#ibcon#read 3, iclass 16, count 0 2006.239.08:03:30.68#ibcon#about to read 4, iclass 16, count 0 2006.239.08:03:30.68#ibcon#read 4, iclass 16, count 0 2006.239.08:03:30.68#ibcon#about to read 5, iclass 16, count 0 2006.239.08:03:30.68#ibcon#read 5, iclass 16, count 0 2006.239.08:03:30.68#ibcon#about to read 6, iclass 16, count 0 2006.239.08:03:30.68#ibcon#read 6, iclass 16, count 0 2006.239.08:03:30.68#ibcon#end of sib2, iclass 16, count 0 2006.239.08:03:30.68#ibcon#*after write, iclass 16, count 0 2006.239.08:03:30.68#ibcon#*before return 0, iclass 16, count 0 2006.239.08:03:30.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:03:30.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:03:30.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:03:30.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:03:30.68$vc4f8/vb=1,4 2006.239.08:03:30.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.08:03:30.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.08:03:30.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:30.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:03:30.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:03:30.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:03:30.68#ibcon#enter wrdev, iclass 18, count 2 2006.239.08:03:30.68#ibcon#first serial, iclass 18, count 2 2006.239.08:03:30.68#ibcon#enter sib2, iclass 18, count 2 2006.239.08:03:30.68#ibcon#flushed, iclass 18, count 2 2006.239.08:03:30.68#ibcon#about to write, iclass 18, count 2 2006.239.08:03:30.68#ibcon#wrote, iclass 18, count 2 2006.239.08:03:30.68#ibcon#about to read 3, iclass 18, count 2 2006.239.08:03:30.70#ibcon#read 3, iclass 18, count 2 2006.239.08:03:30.70#ibcon#about to read 4, iclass 18, count 2 2006.239.08:03:30.70#ibcon#read 4, iclass 18, count 2 2006.239.08:03:30.70#ibcon#about to read 5, iclass 18, count 2 2006.239.08:03:30.70#ibcon#read 5, iclass 18, count 2 2006.239.08:03:30.70#ibcon#about to read 6, iclass 18, count 2 2006.239.08:03:30.70#ibcon#read 6, iclass 18, count 2 2006.239.08:03:30.70#ibcon#end of sib2, iclass 18, count 2 2006.239.08:03:30.70#ibcon#*mode == 0, iclass 18, count 2 2006.239.08:03:30.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.08:03:30.70#ibcon#[27=AT01-04\r\n] 2006.239.08:03:30.70#ibcon#*before write, iclass 18, count 2 2006.239.08:03:30.70#ibcon#enter sib2, iclass 18, count 2 2006.239.08:03:30.70#ibcon#flushed, iclass 18, count 2 2006.239.08:03:30.70#ibcon#about to write, iclass 18, count 2 2006.239.08:03:30.70#ibcon#wrote, iclass 18, count 2 2006.239.08:03:30.70#ibcon#about to read 3, iclass 18, count 2 2006.239.08:03:30.73#ibcon#read 3, iclass 18, count 2 2006.239.08:03:30.73#ibcon#about to read 4, iclass 18, count 2 2006.239.08:03:30.73#ibcon#read 4, iclass 18, count 2 2006.239.08:03:30.73#ibcon#about to read 5, iclass 18, count 2 2006.239.08:03:30.73#ibcon#read 5, iclass 18, count 2 2006.239.08:03:30.73#ibcon#about to read 6, iclass 18, count 2 2006.239.08:03:30.73#ibcon#read 6, iclass 18, count 2 2006.239.08:03:30.73#ibcon#end of sib2, iclass 18, count 2 2006.239.08:03:30.73#ibcon#*after write, iclass 18, count 2 2006.239.08:03:30.73#ibcon#*before return 0, iclass 18, count 2 2006.239.08:03:30.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:03:30.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:03:30.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.08:03:30.73#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:30.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:03:30.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:03:30.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:03:30.85#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:03:30.85#ibcon#first serial, iclass 18, count 0 2006.239.08:03:30.85#ibcon#enter sib2, iclass 18, count 0 2006.239.08:03:30.85#ibcon#flushed, iclass 18, count 0 2006.239.08:03:30.85#ibcon#about to write, iclass 18, count 0 2006.239.08:03:30.85#ibcon#wrote, iclass 18, count 0 2006.239.08:03:30.85#ibcon#about to read 3, iclass 18, count 0 2006.239.08:03:30.87#ibcon#read 3, iclass 18, count 0 2006.239.08:03:30.87#ibcon#about to read 4, iclass 18, count 0 2006.239.08:03:30.87#ibcon#read 4, iclass 18, count 0 2006.239.08:03:30.87#ibcon#about to read 5, iclass 18, count 0 2006.239.08:03:30.87#ibcon#read 5, iclass 18, count 0 2006.239.08:03:30.87#ibcon#about to read 6, iclass 18, count 0 2006.239.08:03:30.87#ibcon#read 6, iclass 18, count 0 2006.239.08:03:30.87#ibcon#end of sib2, iclass 18, count 0 2006.239.08:03:30.87#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:03:30.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:03:30.87#ibcon#[27=USB\r\n] 2006.239.08:03:30.87#ibcon#*before write, iclass 18, count 0 2006.239.08:03:30.87#ibcon#enter sib2, iclass 18, count 0 2006.239.08:03:30.87#ibcon#flushed, iclass 18, count 0 2006.239.08:03:30.87#ibcon#about to write, iclass 18, count 0 2006.239.08:03:30.87#ibcon#wrote, iclass 18, count 0 2006.239.08:03:30.87#ibcon#about to read 3, iclass 18, count 0 2006.239.08:03:30.90#ibcon#read 3, iclass 18, count 0 2006.239.08:03:30.90#ibcon#about to read 4, iclass 18, count 0 2006.239.08:03:30.90#ibcon#read 4, iclass 18, count 0 2006.239.08:03:30.90#ibcon#about to read 5, iclass 18, count 0 2006.239.08:03:30.90#ibcon#read 5, iclass 18, count 0 2006.239.08:03:30.90#ibcon#about to read 6, iclass 18, count 0 2006.239.08:03:30.90#ibcon#read 6, iclass 18, count 0 2006.239.08:03:30.90#ibcon#end of sib2, iclass 18, count 0 2006.239.08:03:30.90#ibcon#*after write, iclass 18, count 0 2006.239.08:03:30.90#ibcon#*before return 0, iclass 18, count 0 2006.239.08:03:30.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:03:30.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:03:30.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:03:30.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:03:30.90$vc4f8/vblo=2,640.99 2006.239.08:03:30.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.08:03:30.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.08:03:30.90#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:30.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:30.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:30.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:30.90#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:03:30.90#ibcon#first serial, iclass 20, count 0 2006.239.08:03:30.90#ibcon#enter sib2, iclass 20, count 0 2006.239.08:03:30.90#ibcon#flushed, iclass 20, count 0 2006.239.08:03:30.90#ibcon#about to write, iclass 20, count 0 2006.239.08:03:30.90#ibcon#wrote, iclass 20, count 0 2006.239.08:03:30.90#ibcon#about to read 3, iclass 20, count 0 2006.239.08:03:30.92#ibcon#read 3, iclass 20, count 0 2006.239.08:03:30.92#ibcon#about to read 4, iclass 20, count 0 2006.239.08:03:30.92#ibcon#read 4, iclass 20, count 0 2006.239.08:03:30.92#ibcon#about to read 5, iclass 20, count 0 2006.239.08:03:30.92#ibcon#read 5, iclass 20, count 0 2006.239.08:03:30.92#ibcon#about to read 6, iclass 20, count 0 2006.239.08:03:30.92#ibcon#read 6, iclass 20, count 0 2006.239.08:03:30.92#ibcon#end of sib2, iclass 20, count 0 2006.239.08:03:30.92#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:03:30.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:03:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:03:30.92#ibcon#*before write, iclass 20, count 0 2006.239.08:03:30.92#ibcon#enter sib2, iclass 20, count 0 2006.239.08:03:30.92#ibcon#flushed, iclass 20, count 0 2006.239.08:03:30.92#ibcon#about to write, iclass 20, count 0 2006.239.08:03:30.92#ibcon#wrote, iclass 20, count 0 2006.239.08:03:30.92#ibcon#about to read 3, iclass 20, count 0 2006.239.08:03:30.96#ibcon#read 3, iclass 20, count 0 2006.239.08:03:30.96#ibcon#about to read 4, iclass 20, count 0 2006.239.08:03:30.96#ibcon#read 4, iclass 20, count 0 2006.239.08:03:30.96#ibcon#about to read 5, iclass 20, count 0 2006.239.08:03:30.96#ibcon#read 5, iclass 20, count 0 2006.239.08:03:30.96#ibcon#about to read 6, iclass 20, count 0 2006.239.08:03:30.96#ibcon#read 6, iclass 20, count 0 2006.239.08:03:30.96#ibcon#end of sib2, iclass 20, count 0 2006.239.08:03:30.96#ibcon#*after write, iclass 20, count 0 2006.239.08:03:30.96#ibcon#*before return 0, iclass 20, count 0 2006.239.08:03:30.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:30.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:03:30.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:03:30.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:03:30.96$vc4f8/vb=2,4 2006.239.08:03:30.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.08:03:30.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.08:03:30.96#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:30.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:31.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:31.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:31.02#ibcon#enter wrdev, iclass 22, count 2 2006.239.08:03:31.02#ibcon#first serial, iclass 22, count 2 2006.239.08:03:31.02#ibcon#enter sib2, iclass 22, count 2 2006.239.08:03:31.02#ibcon#flushed, iclass 22, count 2 2006.239.08:03:31.02#ibcon#about to write, iclass 22, count 2 2006.239.08:03:31.02#ibcon#wrote, iclass 22, count 2 2006.239.08:03:31.02#ibcon#about to read 3, iclass 22, count 2 2006.239.08:03:31.04#ibcon#read 3, iclass 22, count 2 2006.239.08:03:31.04#ibcon#about to read 4, iclass 22, count 2 2006.239.08:03:31.04#ibcon#read 4, iclass 22, count 2 2006.239.08:03:31.04#ibcon#about to read 5, iclass 22, count 2 2006.239.08:03:31.04#ibcon#read 5, iclass 22, count 2 2006.239.08:03:31.04#ibcon#about to read 6, iclass 22, count 2 2006.239.08:03:31.04#ibcon#read 6, iclass 22, count 2 2006.239.08:03:31.04#ibcon#end of sib2, iclass 22, count 2 2006.239.08:03:31.04#ibcon#*mode == 0, iclass 22, count 2 2006.239.08:03:31.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.08:03:31.04#ibcon#[27=AT02-04\r\n] 2006.239.08:03:31.04#ibcon#*before write, iclass 22, count 2 2006.239.08:03:31.04#ibcon#enter sib2, iclass 22, count 2 2006.239.08:03:31.04#ibcon#flushed, iclass 22, count 2 2006.239.08:03:31.04#ibcon#about to write, iclass 22, count 2 2006.239.08:03:31.04#ibcon#wrote, iclass 22, count 2 2006.239.08:03:31.04#ibcon#about to read 3, iclass 22, count 2 2006.239.08:03:31.07#ibcon#read 3, iclass 22, count 2 2006.239.08:03:31.07#ibcon#about to read 4, iclass 22, count 2 2006.239.08:03:31.07#ibcon#read 4, iclass 22, count 2 2006.239.08:03:31.07#ibcon#about to read 5, iclass 22, count 2 2006.239.08:03:31.07#ibcon#read 5, iclass 22, count 2 2006.239.08:03:31.07#ibcon#about to read 6, iclass 22, count 2 2006.239.08:03:31.07#ibcon#read 6, iclass 22, count 2 2006.239.08:03:31.07#ibcon#end of sib2, iclass 22, count 2 2006.239.08:03:31.07#ibcon#*after write, iclass 22, count 2 2006.239.08:03:31.07#ibcon#*before return 0, iclass 22, count 2 2006.239.08:03:31.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:31.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:03:31.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.08:03:31.07#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:31.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:31.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:31.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:31.19#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:03:31.19#ibcon#first serial, iclass 22, count 0 2006.239.08:03:31.19#ibcon#enter sib2, iclass 22, count 0 2006.239.08:03:31.19#ibcon#flushed, iclass 22, count 0 2006.239.08:03:31.19#ibcon#about to write, iclass 22, count 0 2006.239.08:03:31.19#ibcon#wrote, iclass 22, count 0 2006.239.08:03:31.19#ibcon#about to read 3, iclass 22, count 0 2006.239.08:03:31.21#ibcon#read 3, iclass 22, count 0 2006.239.08:03:31.21#ibcon#about to read 4, iclass 22, count 0 2006.239.08:03:31.21#ibcon#read 4, iclass 22, count 0 2006.239.08:03:31.21#ibcon#about to read 5, iclass 22, count 0 2006.239.08:03:31.21#ibcon#read 5, iclass 22, count 0 2006.239.08:03:31.21#ibcon#about to read 6, iclass 22, count 0 2006.239.08:03:31.21#ibcon#read 6, iclass 22, count 0 2006.239.08:03:31.21#ibcon#end of sib2, iclass 22, count 0 2006.239.08:03:31.21#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:03:31.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:03:31.21#ibcon#[27=USB\r\n] 2006.239.08:03:31.21#ibcon#*before write, iclass 22, count 0 2006.239.08:03:31.21#ibcon#enter sib2, iclass 22, count 0 2006.239.08:03:31.21#ibcon#flushed, iclass 22, count 0 2006.239.08:03:31.21#ibcon#about to write, iclass 22, count 0 2006.239.08:03:31.21#ibcon#wrote, iclass 22, count 0 2006.239.08:03:31.21#ibcon#about to read 3, iclass 22, count 0 2006.239.08:03:31.24#ibcon#read 3, iclass 22, count 0 2006.239.08:03:31.24#ibcon#about to read 4, iclass 22, count 0 2006.239.08:03:31.24#ibcon#read 4, iclass 22, count 0 2006.239.08:03:31.24#ibcon#about to read 5, iclass 22, count 0 2006.239.08:03:31.24#ibcon#read 5, iclass 22, count 0 2006.239.08:03:31.24#ibcon#about to read 6, iclass 22, count 0 2006.239.08:03:31.24#ibcon#read 6, iclass 22, count 0 2006.239.08:03:31.24#ibcon#end of sib2, iclass 22, count 0 2006.239.08:03:31.24#ibcon#*after write, iclass 22, count 0 2006.239.08:03:31.24#ibcon#*before return 0, iclass 22, count 0 2006.239.08:03:31.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:31.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:03:31.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:03:31.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:03:31.24$vc4f8/vblo=3,656.99 2006.239.08:03:31.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.08:03:31.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.08:03:31.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:31.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:31.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:31.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:31.24#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:03:31.24#ibcon#first serial, iclass 24, count 0 2006.239.08:03:31.24#ibcon#enter sib2, iclass 24, count 0 2006.239.08:03:31.24#ibcon#flushed, iclass 24, count 0 2006.239.08:03:31.24#ibcon#about to write, iclass 24, count 0 2006.239.08:03:31.24#ibcon#wrote, iclass 24, count 0 2006.239.08:03:31.24#ibcon#about to read 3, iclass 24, count 0 2006.239.08:03:31.26#ibcon#read 3, iclass 24, count 0 2006.239.08:03:31.26#ibcon#about to read 4, iclass 24, count 0 2006.239.08:03:31.26#ibcon#read 4, iclass 24, count 0 2006.239.08:03:31.26#ibcon#about to read 5, iclass 24, count 0 2006.239.08:03:31.26#ibcon#read 5, iclass 24, count 0 2006.239.08:03:31.26#ibcon#about to read 6, iclass 24, count 0 2006.239.08:03:31.26#ibcon#read 6, iclass 24, count 0 2006.239.08:03:31.26#ibcon#end of sib2, iclass 24, count 0 2006.239.08:03:31.26#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:03:31.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:03:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:03:31.26#ibcon#*before write, iclass 24, count 0 2006.239.08:03:31.26#ibcon#enter sib2, iclass 24, count 0 2006.239.08:03:31.26#ibcon#flushed, iclass 24, count 0 2006.239.08:03:31.26#ibcon#about to write, iclass 24, count 0 2006.239.08:03:31.26#ibcon#wrote, iclass 24, count 0 2006.239.08:03:31.26#ibcon#about to read 3, iclass 24, count 0 2006.239.08:03:31.30#ibcon#read 3, iclass 24, count 0 2006.239.08:03:31.30#ibcon#about to read 4, iclass 24, count 0 2006.239.08:03:31.30#ibcon#read 4, iclass 24, count 0 2006.239.08:03:31.30#ibcon#about to read 5, iclass 24, count 0 2006.239.08:03:31.30#ibcon#read 5, iclass 24, count 0 2006.239.08:03:31.30#ibcon#about to read 6, iclass 24, count 0 2006.239.08:03:31.30#ibcon#read 6, iclass 24, count 0 2006.239.08:03:31.30#ibcon#end of sib2, iclass 24, count 0 2006.239.08:03:31.30#ibcon#*after write, iclass 24, count 0 2006.239.08:03:31.30#ibcon#*before return 0, iclass 24, count 0 2006.239.08:03:31.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:31.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:03:31.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:03:31.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:03:31.30$vc4f8/vb=3,4 2006.239.08:03:31.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.08:03:31.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.08:03:31.30#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:31.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:31.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:31.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:31.36#ibcon#enter wrdev, iclass 26, count 2 2006.239.08:03:31.36#ibcon#first serial, iclass 26, count 2 2006.239.08:03:31.36#ibcon#enter sib2, iclass 26, count 2 2006.239.08:03:31.36#ibcon#flushed, iclass 26, count 2 2006.239.08:03:31.36#ibcon#about to write, iclass 26, count 2 2006.239.08:03:31.36#ibcon#wrote, iclass 26, count 2 2006.239.08:03:31.36#ibcon#about to read 3, iclass 26, count 2 2006.239.08:03:31.38#ibcon#read 3, iclass 26, count 2 2006.239.08:03:31.38#ibcon#about to read 4, iclass 26, count 2 2006.239.08:03:31.38#ibcon#read 4, iclass 26, count 2 2006.239.08:03:31.38#ibcon#about to read 5, iclass 26, count 2 2006.239.08:03:31.38#ibcon#read 5, iclass 26, count 2 2006.239.08:03:31.38#ibcon#about to read 6, iclass 26, count 2 2006.239.08:03:31.38#ibcon#read 6, iclass 26, count 2 2006.239.08:03:31.38#ibcon#end of sib2, iclass 26, count 2 2006.239.08:03:31.38#ibcon#*mode == 0, iclass 26, count 2 2006.239.08:03:31.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.08:03:31.38#ibcon#[27=AT03-04\r\n] 2006.239.08:03:31.38#ibcon#*before write, iclass 26, count 2 2006.239.08:03:31.38#ibcon#enter sib2, iclass 26, count 2 2006.239.08:03:31.38#ibcon#flushed, iclass 26, count 2 2006.239.08:03:31.38#ibcon#about to write, iclass 26, count 2 2006.239.08:03:31.38#ibcon#wrote, iclass 26, count 2 2006.239.08:03:31.38#ibcon#about to read 3, iclass 26, count 2 2006.239.08:03:31.41#ibcon#read 3, iclass 26, count 2 2006.239.08:03:31.41#ibcon#about to read 4, iclass 26, count 2 2006.239.08:03:31.41#ibcon#read 4, iclass 26, count 2 2006.239.08:03:31.41#ibcon#about to read 5, iclass 26, count 2 2006.239.08:03:31.41#ibcon#read 5, iclass 26, count 2 2006.239.08:03:31.41#ibcon#about to read 6, iclass 26, count 2 2006.239.08:03:31.41#ibcon#read 6, iclass 26, count 2 2006.239.08:03:31.41#ibcon#end of sib2, iclass 26, count 2 2006.239.08:03:31.41#ibcon#*after write, iclass 26, count 2 2006.239.08:03:31.41#ibcon#*before return 0, iclass 26, count 2 2006.239.08:03:31.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:31.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:03:31.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.08:03:31.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:31.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:31.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:31.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:31.53#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:03:31.53#ibcon#first serial, iclass 26, count 0 2006.239.08:03:31.53#ibcon#enter sib2, iclass 26, count 0 2006.239.08:03:31.53#ibcon#flushed, iclass 26, count 0 2006.239.08:03:31.53#ibcon#about to write, iclass 26, count 0 2006.239.08:03:31.53#ibcon#wrote, iclass 26, count 0 2006.239.08:03:31.53#ibcon#about to read 3, iclass 26, count 0 2006.239.08:03:31.55#ibcon#read 3, iclass 26, count 0 2006.239.08:03:31.55#ibcon#about to read 4, iclass 26, count 0 2006.239.08:03:31.55#ibcon#read 4, iclass 26, count 0 2006.239.08:03:31.55#ibcon#about to read 5, iclass 26, count 0 2006.239.08:03:31.55#ibcon#read 5, iclass 26, count 0 2006.239.08:03:31.55#ibcon#about to read 6, iclass 26, count 0 2006.239.08:03:31.55#ibcon#read 6, iclass 26, count 0 2006.239.08:03:31.55#ibcon#end of sib2, iclass 26, count 0 2006.239.08:03:31.55#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:03:31.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:03:31.55#ibcon#[27=USB\r\n] 2006.239.08:03:31.55#ibcon#*before write, iclass 26, count 0 2006.239.08:03:31.55#ibcon#enter sib2, iclass 26, count 0 2006.239.08:03:31.55#ibcon#flushed, iclass 26, count 0 2006.239.08:03:31.55#ibcon#about to write, iclass 26, count 0 2006.239.08:03:31.55#ibcon#wrote, iclass 26, count 0 2006.239.08:03:31.55#ibcon#about to read 3, iclass 26, count 0 2006.239.08:03:31.58#ibcon#read 3, iclass 26, count 0 2006.239.08:03:31.58#ibcon#about to read 4, iclass 26, count 0 2006.239.08:03:31.58#ibcon#read 4, iclass 26, count 0 2006.239.08:03:31.58#ibcon#about to read 5, iclass 26, count 0 2006.239.08:03:31.58#ibcon#read 5, iclass 26, count 0 2006.239.08:03:31.58#ibcon#about to read 6, iclass 26, count 0 2006.239.08:03:31.58#ibcon#read 6, iclass 26, count 0 2006.239.08:03:31.58#ibcon#end of sib2, iclass 26, count 0 2006.239.08:03:31.58#ibcon#*after write, iclass 26, count 0 2006.239.08:03:31.58#ibcon#*before return 0, iclass 26, count 0 2006.239.08:03:31.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:31.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:03:31.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:03:31.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:03:31.58$vc4f8/vblo=4,712.99 2006.239.08:03:31.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:03:31.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:03:31.58#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:31.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:31.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:31.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:31.58#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:03:31.58#ibcon#first serial, iclass 28, count 0 2006.239.08:03:31.58#ibcon#enter sib2, iclass 28, count 0 2006.239.08:03:31.58#ibcon#flushed, iclass 28, count 0 2006.239.08:03:31.58#ibcon#about to write, iclass 28, count 0 2006.239.08:03:31.58#ibcon#wrote, iclass 28, count 0 2006.239.08:03:31.58#ibcon#about to read 3, iclass 28, count 0 2006.239.08:03:31.60#ibcon#read 3, iclass 28, count 0 2006.239.08:03:31.60#ibcon#about to read 4, iclass 28, count 0 2006.239.08:03:31.60#ibcon#read 4, iclass 28, count 0 2006.239.08:03:31.60#ibcon#about to read 5, iclass 28, count 0 2006.239.08:03:31.60#ibcon#read 5, iclass 28, count 0 2006.239.08:03:31.60#ibcon#about to read 6, iclass 28, count 0 2006.239.08:03:31.60#ibcon#read 6, iclass 28, count 0 2006.239.08:03:31.60#ibcon#end of sib2, iclass 28, count 0 2006.239.08:03:31.60#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:03:31.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:03:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:03:31.60#ibcon#*before write, iclass 28, count 0 2006.239.08:03:31.60#ibcon#enter sib2, iclass 28, count 0 2006.239.08:03:31.60#ibcon#flushed, iclass 28, count 0 2006.239.08:03:31.60#ibcon#about to write, iclass 28, count 0 2006.239.08:03:31.60#ibcon#wrote, iclass 28, count 0 2006.239.08:03:31.60#ibcon#about to read 3, iclass 28, count 0 2006.239.08:03:31.64#ibcon#read 3, iclass 28, count 0 2006.239.08:03:31.64#ibcon#about to read 4, iclass 28, count 0 2006.239.08:03:31.64#ibcon#read 4, iclass 28, count 0 2006.239.08:03:31.64#ibcon#about to read 5, iclass 28, count 0 2006.239.08:03:31.64#ibcon#read 5, iclass 28, count 0 2006.239.08:03:31.64#ibcon#about to read 6, iclass 28, count 0 2006.239.08:03:31.64#ibcon#read 6, iclass 28, count 0 2006.239.08:03:31.64#ibcon#end of sib2, iclass 28, count 0 2006.239.08:03:31.64#ibcon#*after write, iclass 28, count 0 2006.239.08:03:31.64#ibcon#*before return 0, iclass 28, count 0 2006.239.08:03:31.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:31.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:03:31.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:03:31.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:03:31.64$vc4f8/vb=4,4 2006.239.08:03:31.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.08:03:31.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.08:03:31.64#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:31.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:31.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:31.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:31.70#ibcon#enter wrdev, iclass 30, count 2 2006.239.08:03:31.70#ibcon#first serial, iclass 30, count 2 2006.239.08:03:31.70#ibcon#enter sib2, iclass 30, count 2 2006.239.08:03:31.70#ibcon#flushed, iclass 30, count 2 2006.239.08:03:31.70#ibcon#about to write, iclass 30, count 2 2006.239.08:03:31.70#ibcon#wrote, iclass 30, count 2 2006.239.08:03:31.70#ibcon#about to read 3, iclass 30, count 2 2006.239.08:03:31.72#ibcon#read 3, iclass 30, count 2 2006.239.08:03:31.72#ibcon#about to read 4, iclass 30, count 2 2006.239.08:03:31.72#ibcon#read 4, iclass 30, count 2 2006.239.08:03:31.72#ibcon#about to read 5, iclass 30, count 2 2006.239.08:03:31.72#ibcon#read 5, iclass 30, count 2 2006.239.08:03:31.72#ibcon#about to read 6, iclass 30, count 2 2006.239.08:03:31.72#ibcon#read 6, iclass 30, count 2 2006.239.08:03:31.72#ibcon#end of sib2, iclass 30, count 2 2006.239.08:03:31.72#ibcon#*mode == 0, iclass 30, count 2 2006.239.08:03:31.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.08:03:31.72#ibcon#[27=AT04-04\r\n] 2006.239.08:03:31.72#ibcon#*before write, iclass 30, count 2 2006.239.08:03:31.72#ibcon#enter sib2, iclass 30, count 2 2006.239.08:03:31.72#ibcon#flushed, iclass 30, count 2 2006.239.08:03:31.72#ibcon#about to write, iclass 30, count 2 2006.239.08:03:31.72#ibcon#wrote, iclass 30, count 2 2006.239.08:03:31.72#ibcon#about to read 3, iclass 30, count 2 2006.239.08:03:31.75#ibcon#read 3, iclass 30, count 2 2006.239.08:03:31.75#ibcon#about to read 4, iclass 30, count 2 2006.239.08:03:31.75#ibcon#read 4, iclass 30, count 2 2006.239.08:03:31.75#ibcon#about to read 5, iclass 30, count 2 2006.239.08:03:31.75#ibcon#read 5, iclass 30, count 2 2006.239.08:03:31.75#ibcon#about to read 6, iclass 30, count 2 2006.239.08:03:31.75#ibcon#read 6, iclass 30, count 2 2006.239.08:03:31.75#ibcon#end of sib2, iclass 30, count 2 2006.239.08:03:31.75#ibcon#*after write, iclass 30, count 2 2006.239.08:03:31.75#ibcon#*before return 0, iclass 30, count 2 2006.239.08:03:31.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:31.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:03:31.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.08:03:31.75#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:31.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:31.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:31.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:31.87#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:03:31.87#ibcon#first serial, iclass 30, count 0 2006.239.08:03:31.87#ibcon#enter sib2, iclass 30, count 0 2006.239.08:03:31.87#ibcon#flushed, iclass 30, count 0 2006.239.08:03:31.87#ibcon#about to write, iclass 30, count 0 2006.239.08:03:31.87#ibcon#wrote, iclass 30, count 0 2006.239.08:03:31.87#ibcon#about to read 3, iclass 30, count 0 2006.239.08:03:31.89#ibcon#read 3, iclass 30, count 0 2006.239.08:03:31.89#ibcon#about to read 4, iclass 30, count 0 2006.239.08:03:31.89#ibcon#read 4, iclass 30, count 0 2006.239.08:03:31.89#ibcon#about to read 5, iclass 30, count 0 2006.239.08:03:31.89#ibcon#read 5, iclass 30, count 0 2006.239.08:03:31.89#ibcon#about to read 6, iclass 30, count 0 2006.239.08:03:31.89#ibcon#read 6, iclass 30, count 0 2006.239.08:03:31.89#ibcon#end of sib2, iclass 30, count 0 2006.239.08:03:31.89#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:03:31.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:03:31.89#ibcon#[27=USB\r\n] 2006.239.08:03:31.89#ibcon#*before write, iclass 30, count 0 2006.239.08:03:31.89#ibcon#enter sib2, iclass 30, count 0 2006.239.08:03:31.89#ibcon#flushed, iclass 30, count 0 2006.239.08:03:31.89#ibcon#about to write, iclass 30, count 0 2006.239.08:03:31.89#ibcon#wrote, iclass 30, count 0 2006.239.08:03:31.89#ibcon#about to read 3, iclass 30, count 0 2006.239.08:03:31.92#ibcon#read 3, iclass 30, count 0 2006.239.08:03:31.92#ibcon#about to read 4, iclass 30, count 0 2006.239.08:03:31.92#ibcon#read 4, iclass 30, count 0 2006.239.08:03:31.92#ibcon#about to read 5, iclass 30, count 0 2006.239.08:03:31.92#ibcon#read 5, iclass 30, count 0 2006.239.08:03:31.92#ibcon#about to read 6, iclass 30, count 0 2006.239.08:03:31.92#ibcon#read 6, iclass 30, count 0 2006.239.08:03:31.92#ibcon#end of sib2, iclass 30, count 0 2006.239.08:03:31.92#ibcon#*after write, iclass 30, count 0 2006.239.08:03:31.92#ibcon#*before return 0, iclass 30, count 0 2006.239.08:03:31.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:31.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:03:31.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:03:31.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:03:31.92$vc4f8/vblo=5,744.99 2006.239.08:03:31.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.08:03:31.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.08:03:31.92#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:31.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:31.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:31.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:31.92#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:03:31.92#ibcon#first serial, iclass 32, count 0 2006.239.08:03:31.92#ibcon#enter sib2, iclass 32, count 0 2006.239.08:03:31.92#ibcon#flushed, iclass 32, count 0 2006.239.08:03:31.92#ibcon#about to write, iclass 32, count 0 2006.239.08:03:31.92#ibcon#wrote, iclass 32, count 0 2006.239.08:03:31.92#ibcon#about to read 3, iclass 32, count 0 2006.239.08:03:31.94#ibcon#read 3, iclass 32, count 0 2006.239.08:03:31.94#ibcon#about to read 4, iclass 32, count 0 2006.239.08:03:31.94#ibcon#read 4, iclass 32, count 0 2006.239.08:03:31.94#ibcon#about to read 5, iclass 32, count 0 2006.239.08:03:31.94#ibcon#read 5, iclass 32, count 0 2006.239.08:03:31.94#ibcon#about to read 6, iclass 32, count 0 2006.239.08:03:31.94#ibcon#read 6, iclass 32, count 0 2006.239.08:03:31.94#ibcon#end of sib2, iclass 32, count 0 2006.239.08:03:31.94#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:03:31.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:03:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:03:31.94#ibcon#*before write, iclass 32, count 0 2006.239.08:03:31.94#ibcon#enter sib2, iclass 32, count 0 2006.239.08:03:31.94#ibcon#flushed, iclass 32, count 0 2006.239.08:03:31.94#ibcon#about to write, iclass 32, count 0 2006.239.08:03:31.94#ibcon#wrote, iclass 32, count 0 2006.239.08:03:31.94#ibcon#about to read 3, iclass 32, count 0 2006.239.08:03:31.98#ibcon#read 3, iclass 32, count 0 2006.239.08:03:31.98#ibcon#about to read 4, iclass 32, count 0 2006.239.08:03:31.98#ibcon#read 4, iclass 32, count 0 2006.239.08:03:31.98#ibcon#about to read 5, iclass 32, count 0 2006.239.08:03:31.98#ibcon#read 5, iclass 32, count 0 2006.239.08:03:31.98#ibcon#about to read 6, iclass 32, count 0 2006.239.08:03:31.98#ibcon#read 6, iclass 32, count 0 2006.239.08:03:31.98#ibcon#end of sib2, iclass 32, count 0 2006.239.08:03:31.98#ibcon#*after write, iclass 32, count 0 2006.239.08:03:31.98#ibcon#*before return 0, iclass 32, count 0 2006.239.08:03:31.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:31.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:03:31.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:03:31.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:03:31.98$vc4f8/vb=5,4 2006.239.08:03:31.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.08:03:31.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.08:03:31.98#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:31.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:32.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:32.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:32.04#ibcon#enter wrdev, iclass 34, count 2 2006.239.08:03:32.04#ibcon#first serial, iclass 34, count 2 2006.239.08:03:32.04#ibcon#enter sib2, iclass 34, count 2 2006.239.08:03:32.04#ibcon#flushed, iclass 34, count 2 2006.239.08:03:32.04#ibcon#about to write, iclass 34, count 2 2006.239.08:03:32.04#ibcon#wrote, iclass 34, count 2 2006.239.08:03:32.04#ibcon#about to read 3, iclass 34, count 2 2006.239.08:03:32.06#ibcon#read 3, iclass 34, count 2 2006.239.08:03:32.06#ibcon#about to read 4, iclass 34, count 2 2006.239.08:03:32.06#ibcon#read 4, iclass 34, count 2 2006.239.08:03:32.06#ibcon#about to read 5, iclass 34, count 2 2006.239.08:03:32.06#ibcon#read 5, iclass 34, count 2 2006.239.08:03:32.06#ibcon#about to read 6, iclass 34, count 2 2006.239.08:03:32.06#ibcon#read 6, iclass 34, count 2 2006.239.08:03:32.06#ibcon#end of sib2, iclass 34, count 2 2006.239.08:03:32.06#ibcon#*mode == 0, iclass 34, count 2 2006.239.08:03:32.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.08:03:32.06#ibcon#[27=AT05-04\r\n] 2006.239.08:03:32.06#ibcon#*before write, iclass 34, count 2 2006.239.08:03:32.06#ibcon#enter sib2, iclass 34, count 2 2006.239.08:03:32.06#ibcon#flushed, iclass 34, count 2 2006.239.08:03:32.06#ibcon#about to write, iclass 34, count 2 2006.239.08:03:32.06#ibcon#wrote, iclass 34, count 2 2006.239.08:03:32.06#ibcon#about to read 3, iclass 34, count 2 2006.239.08:03:32.09#ibcon#read 3, iclass 34, count 2 2006.239.08:03:32.09#ibcon#about to read 4, iclass 34, count 2 2006.239.08:03:32.09#ibcon#read 4, iclass 34, count 2 2006.239.08:03:32.09#ibcon#about to read 5, iclass 34, count 2 2006.239.08:03:32.09#ibcon#read 5, iclass 34, count 2 2006.239.08:03:32.09#ibcon#about to read 6, iclass 34, count 2 2006.239.08:03:32.09#ibcon#read 6, iclass 34, count 2 2006.239.08:03:32.09#ibcon#end of sib2, iclass 34, count 2 2006.239.08:03:32.09#ibcon#*after write, iclass 34, count 2 2006.239.08:03:32.09#ibcon#*before return 0, iclass 34, count 2 2006.239.08:03:32.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:32.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:03:32.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.08:03:32.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:32.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:32.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:32.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:32.21#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:03:32.21#ibcon#first serial, iclass 34, count 0 2006.239.08:03:32.21#ibcon#enter sib2, iclass 34, count 0 2006.239.08:03:32.21#ibcon#flushed, iclass 34, count 0 2006.239.08:03:32.21#ibcon#about to write, iclass 34, count 0 2006.239.08:03:32.21#ibcon#wrote, iclass 34, count 0 2006.239.08:03:32.21#ibcon#about to read 3, iclass 34, count 0 2006.239.08:03:32.23#ibcon#read 3, iclass 34, count 0 2006.239.08:03:32.23#ibcon#about to read 4, iclass 34, count 0 2006.239.08:03:32.23#ibcon#read 4, iclass 34, count 0 2006.239.08:03:32.23#ibcon#about to read 5, iclass 34, count 0 2006.239.08:03:32.23#ibcon#read 5, iclass 34, count 0 2006.239.08:03:32.23#ibcon#about to read 6, iclass 34, count 0 2006.239.08:03:32.23#ibcon#read 6, iclass 34, count 0 2006.239.08:03:32.23#ibcon#end of sib2, iclass 34, count 0 2006.239.08:03:32.23#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:03:32.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:03:32.23#ibcon#[27=USB\r\n] 2006.239.08:03:32.23#ibcon#*before write, iclass 34, count 0 2006.239.08:03:32.23#ibcon#enter sib2, iclass 34, count 0 2006.239.08:03:32.23#ibcon#flushed, iclass 34, count 0 2006.239.08:03:32.23#ibcon#about to write, iclass 34, count 0 2006.239.08:03:32.23#ibcon#wrote, iclass 34, count 0 2006.239.08:03:32.23#ibcon#about to read 3, iclass 34, count 0 2006.239.08:03:32.26#ibcon#read 3, iclass 34, count 0 2006.239.08:03:32.26#ibcon#about to read 4, iclass 34, count 0 2006.239.08:03:32.26#ibcon#read 4, iclass 34, count 0 2006.239.08:03:32.26#ibcon#about to read 5, iclass 34, count 0 2006.239.08:03:32.26#ibcon#read 5, iclass 34, count 0 2006.239.08:03:32.26#ibcon#about to read 6, iclass 34, count 0 2006.239.08:03:32.26#ibcon#read 6, iclass 34, count 0 2006.239.08:03:32.26#ibcon#end of sib2, iclass 34, count 0 2006.239.08:03:32.26#ibcon#*after write, iclass 34, count 0 2006.239.08:03:32.26#ibcon#*before return 0, iclass 34, count 0 2006.239.08:03:32.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:32.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:03:32.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:03:32.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:03:32.26$vc4f8/vblo=6,752.99 2006.239.08:03:32.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.08:03:32.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.08:03:32.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:03:32.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:32.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:32.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:32.26#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:03:32.26#ibcon#first serial, iclass 36, count 0 2006.239.08:03:32.26#ibcon#enter sib2, iclass 36, count 0 2006.239.08:03:32.26#ibcon#flushed, iclass 36, count 0 2006.239.08:03:32.26#ibcon#about to write, iclass 36, count 0 2006.239.08:03:32.26#ibcon#wrote, iclass 36, count 0 2006.239.08:03:32.26#ibcon#about to read 3, iclass 36, count 0 2006.239.08:03:32.28#ibcon#read 3, iclass 36, count 0 2006.239.08:03:32.28#ibcon#about to read 4, iclass 36, count 0 2006.239.08:03:32.28#ibcon#read 4, iclass 36, count 0 2006.239.08:03:32.28#ibcon#about to read 5, iclass 36, count 0 2006.239.08:03:32.28#ibcon#read 5, iclass 36, count 0 2006.239.08:03:32.28#ibcon#about to read 6, iclass 36, count 0 2006.239.08:03:32.28#ibcon#read 6, iclass 36, count 0 2006.239.08:03:32.28#ibcon#end of sib2, iclass 36, count 0 2006.239.08:03:32.28#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:03:32.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:03:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:03:32.28#ibcon#*before write, iclass 36, count 0 2006.239.08:03:32.28#ibcon#enter sib2, iclass 36, count 0 2006.239.08:03:32.28#ibcon#flushed, iclass 36, count 0 2006.239.08:03:32.28#ibcon#about to write, iclass 36, count 0 2006.239.08:03:32.28#ibcon#wrote, iclass 36, count 0 2006.239.08:03:32.28#ibcon#about to read 3, iclass 36, count 0 2006.239.08:03:32.32#ibcon#read 3, iclass 36, count 0 2006.239.08:03:32.32#ibcon#about to read 4, iclass 36, count 0 2006.239.08:03:32.32#ibcon#read 4, iclass 36, count 0 2006.239.08:03:32.32#ibcon#about to read 5, iclass 36, count 0 2006.239.08:03:32.32#ibcon#read 5, iclass 36, count 0 2006.239.08:03:32.32#ibcon#about to read 6, iclass 36, count 0 2006.239.08:03:32.32#ibcon#read 6, iclass 36, count 0 2006.239.08:03:32.32#ibcon#end of sib2, iclass 36, count 0 2006.239.08:03:32.32#ibcon#*after write, iclass 36, count 0 2006.239.08:03:32.32#ibcon#*before return 0, iclass 36, count 0 2006.239.08:03:32.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:32.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:03:32.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:03:32.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:03:32.32$vc4f8/vb=6,4 2006.239.08:03:32.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.08:03:32.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.08:03:32.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:03:32.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:32.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:32.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:32.38#ibcon#enter wrdev, iclass 38, count 2 2006.239.08:03:32.38#ibcon#first serial, iclass 38, count 2 2006.239.08:03:32.38#ibcon#enter sib2, iclass 38, count 2 2006.239.08:03:32.38#ibcon#flushed, iclass 38, count 2 2006.239.08:03:32.38#ibcon#about to write, iclass 38, count 2 2006.239.08:03:32.38#ibcon#wrote, iclass 38, count 2 2006.239.08:03:32.38#ibcon#about to read 3, iclass 38, count 2 2006.239.08:03:32.40#ibcon#read 3, iclass 38, count 2 2006.239.08:03:32.40#ibcon#about to read 4, iclass 38, count 2 2006.239.08:03:32.40#ibcon#read 4, iclass 38, count 2 2006.239.08:03:32.40#ibcon#about to read 5, iclass 38, count 2 2006.239.08:03:32.40#ibcon#read 5, iclass 38, count 2 2006.239.08:03:32.40#ibcon#about to read 6, iclass 38, count 2 2006.239.08:03:32.40#ibcon#read 6, iclass 38, count 2 2006.239.08:03:32.40#ibcon#end of sib2, iclass 38, count 2 2006.239.08:03:32.40#ibcon#*mode == 0, iclass 38, count 2 2006.239.08:03:32.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.08:03:32.40#ibcon#[27=AT06-04\r\n] 2006.239.08:03:32.40#ibcon#*before write, iclass 38, count 2 2006.239.08:03:32.40#ibcon#enter sib2, iclass 38, count 2 2006.239.08:03:32.40#ibcon#flushed, iclass 38, count 2 2006.239.08:03:32.40#ibcon#about to write, iclass 38, count 2 2006.239.08:03:32.40#ibcon#wrote, iclass 38, count 2 2006.239.08:03:32.40#ibcon#about to read 3, iclass 38, count 2 2006.239.08:03:32.43#ibcon#read 3, iclass 38, count 2 2006.239.08:03:32.43#ibcon#about to read 4, iclass 38, count 2 2006.239.08:03:32.43#ibcon#read 4, iclass 38, count 2 2006.239.08:03:32.43#ibcon#about to read 5, iclass 38, count 2 2006.239.08:03:32.43#ibcon#read 5, iclass 38, count 2 2006.239.08:03:32.43#ibcon#about to read 6, iclass 38, count 2 2006.239.08:03:32.43#ibcon#read 6, iclass 38, count 2 2006.239.08:03:32.43#ibcon#end of sib2, iclass 38, count 2 2006.239.08:03:32.43#ibcon#*after write, iclass 38, count 2 2006.239.08:03:32.43#ibcon#*before return 0, iclass 38, count 2 2006.239.08:03:32.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:32.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:03:32.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.08:03:32.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:03:32.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:32.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:32.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:32.55#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:03:32.55#ibcon#first serial, iclass 38, count 0 2006.239.08:03:32.55#ibcon#enter sib2, iclass 38, count 0 2006.239.08:03:32.55#ibcon#flushed, iclass 38, count 0 2006.239.08:03:32.55#ibcon#about to write, iclass 38, count 0 2006.239.08:03:32.55#ibcon#wrote, iclass 38, count 0 2006.239.08:03:32.55#ibcon#about to read 3, iclass 38, count 0 2006.239.08:03:32.57#ibcon#read 3, iclass 38, count 0 2006.239.08:03:32.57#ibcon#about to read 4, iclass 38, count 0 2006.239.08:03:32.57#ibcon#read 4, iclass 38, count 0 2006.239.08:03:32.57#ibcon#about to read 5, iclass 38, count 0 2006.239.08:03:32.57#ibcon#read 5, iclass 38, count 0 2006.239.08:03:32.57#ibcon#about to read 6, iclass 38, count 0 2006.239.08:03:32.57#ibcon#read 6, iclass 38, count 0 2006.239.08:03:32.57#ibcon#end of sib2, iclass 38, count 0 2006.239.08:03:32.57#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:03:32.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:03:32.57#ibcon#[27=USB\r\n] 2006.239.08:03:32.57#ibcon#*before write, iclass 38, count 0 2006.239.08:03:32.57#ibcon#enter sib2, iclass 38, count 0 2006.239.08:03:32.57#ibcon#flushed, iclass 38, count 0 2006.239.08:03:32.57#ibcon#about to write, iclass 38, count 0 2006.239.08:03:32.57#ibcon#wrote, iclass 38, count 0 2006.239.08:03:32.57#ibcon#about to read 3, iclass 38, count 0 2006.239.08:03:32.60#ibcon#read 3, iclass 38, count 0 2006.239.08:03:32.60#ibcon#about to read 4, iclass 38, count 0 2006.239.08:03:32.60#ibcon#read 4, iclass 38, count 0 2006.239.08:03:32.60#ibcon#about to read 5, iclass 38, count 0 2006.239.08:03:32.60#ibcon#read 5, iclass 38, count 0 2006.239.08:03:32.60#ibcon#about to read 6, iclass 38, count 0 2006.239.08:03:32.60#ibcon#read 6, iclass 38, count 0 2006.239.08:03:32.60#ibcon#end of sib2, iclass 38, count 0 2006.239.08:03:32.60#ibcon#*after write, iclass 38, count 0 2006.239.08:03:32.60#ibcon#*before return 0, iclass 38, count 0 2006.239.08:03:32.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:32.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:03:32.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:03:32.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:03:32.60$vc4f8/vabw=wide 2006.239.08:03:32.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.08:03:32.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.08:03:32.60#ibcon#ireg 8 cls_cnt 0 2006.239.08:03:32.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:32.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:32.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:32.60#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:03:32.60#ibcon#first serial, iclass 40, count 0 2006.239.08:03:32.60#ibcon#enter sib2, iclass 40, count 0 2006.239.08:03:32.60#ibcon#flushed, iclass 40, count 0 2006.239.08:03:32.60#ibcon#about to write, iclass 40, count 0 2006.239.08:03:32.60#ibcon#wrote, iclass 40, count 0 2006.239.08:03:32.60#ibcon#about to read 3, iclass 40, count 0 2006.239.08:03:32.62#ibcon#read 3, iclass 40, count 0 2006.239.08:03:32.62#ibcon#about to read 4, iclass 40, count 0 2006.239.08:03:32.62#ibcon#read 4, iclass 40, count 0 2006.239.08:03:32.62#ibcon#about to read 5, iclass 40, count 0 2006.239.08:03:32.62#ibcon#read 5, iclass 40, count 0 2006.239.08:03:32.62#ibcon#about to read 6, iclass 40, count 0 2006.239.08:03:32.62#ibcon#read 6, iclass 40, count 0 2006.239.08:03:32.62#ibcon#end of sib2, iclass 40, count 0 2006.239.08:03:32.62#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:03:32.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:03:32.62#ibcon#[25=BW32\r\n] 2006.239.08:03:32.62#ibcon#*before write, iclass 40, count 0 2006.239.08:03:32.62#ibcon#enter sib2, iclass 40, count 0 2006.239.08:03:32.62#ibcon#flushed, iclass 40, count 0 2006.239.08:03:32.62#ibcon#about to write, iclass 40, count 0 2006.239.08:03:32.62#ibcon#wrote, iclass 40, count 0 2006.239.08:03:32.62#ibcon#about to read 3, iclass 40, count 0 2006.239.08:03:32.65#ibcon#read 3, iclass 40, count 0 2006.239.08:03:32.65#ibcon#about to read 4, iclass 40, count 0 2006.239.08:03:32.65#ibcon#read 4, iclass 40, count 0 2006.239.08:03:32.65#ibcon#about to read 5, iclass 40, count 0 2006.239.08:03:32.65#ibcon#read 5, iclass 40, count 0 2006.239.08:03:32.65#ibcon#about to read 6, iclass 40, count 0 2006.239.08:03:32.65#ibcon#read 6, iclass 40, count 0 2006.239.08:03:32.65#ibcon#end of sib2, iclass 40, count 0 2006.239.08:03:32.65#ibcon#*after write, iclass 40, count 0 2006.239.08:03:32.65#ibcon#*before return 0, iclass 40, count 0 2006.239.08:03:32.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:32.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:03:32.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:03:32.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:03:32.65$vc4f8/vbbw=wide 2006.239.08:03:32.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.08:03:32.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.08:03:32.65#ibcon#ireg 8 cls_cnt 0 2006.239.08:03:32.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:03:32.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:03:32.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:03:32.72#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:03:32.72#ibcon#first serial, iclass 4, count 0 2006.239.08:03:32.72#ibcon#enter sib2, iclass 4, count 0 2006.239.08:03:32.72#ibcon#flushed, iclass 4, count 0 2006.239.08:03:32.72#ibcon#about to write, iclass 4, count 0 2006.239.08:03:32.72#ibcon#wrote, iclass 4, count 0 2006.239.08:03:32.72#ibcon#about to read 3, iclass 4, count 0 2006.239.08:03:32.74#ibcon#read 3, iclass 4, count 0 2006.239.08:03:32.74#ibcon#about to read 4, iclass 4, count 0 2006.239.08:03:32.74#ibcon#read 4, iclass 4, count 0 2006.239.08:03:32.74#ibcon#about to read 5, iclass 4, count 0 2006.239.08:03:32.74#ibcon#read 5, iclass 4, count 0 2006.239.08:03:32.74#ibcon#about to read 6, iclass 4, count 0 2006.239.08:03:32.74#ibcon#read 6, iclass 4, count 0 2006.239.08:03:32.74#ibcon#end of sib2, iclass 4, count 0 2006.239.08:03:32.74#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:03:32.74#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:03:32.74#ibcon#[27=BW32\r\n] 2006.239.08:03:32.74#ibcon#*before write, iclass 4, count 0 2006.239.08:03:32.74#ibcon#enter sib2, iclass 4, count 0 2006.239.08:03:32.74#ibcon#flushed, iclass 4, count 0 2006.239.08:03:32.74#ibcon#about to write, iclass 4, count 0 2006.239.08:03:32.74#ibcon#wrote, iclass 4, count 0 2006.239.08:03:32.74#ibcon#about to read 3, iclass 4, count 0 2006.239.08:03:32.77#ibcon#read 3, iclass 4, count 0 2006.239.08:03:32.77#ibcon#about to read 4, iclass 4, count 0 2006.239.08:03:32.77#ibcon#read 4, iclass 4, count 0 2006.239.08:03:32.77#ibcon#about to read 5, iclass 4, count 0 2006.239.08:03:32.77#ibcon#read 5, iclass 4, count 0 2006.239.08:03:32.77#ibcon#about to read 6, iclass 4, count 0 2006.239.08:03:32.77#ibcon#read 6, iclass 4, count 0 2006.239.08:03:32.77#ibcon#end of sib2, iclass 4, count 0 2006.239.08:03:32.77#ibcon#*after write, iclass 4, count 0 2006.239.08:03:32.77#ibcon#*before return 0, iclass 4, count 0 2006.239.08:03:32.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:03:32.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:03:32.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:03:32.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:03:32.77$4f8m12a/ifd4f 2006.239.08:03:32.77$ifd4f/lo= 2006.239.08:03:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:03:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:03:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:03:32.77$ifd4f/patch= 2006.239.08:03:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:03:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:03:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:03:32.77$4f8m12a/"form=m,16.000,1:2 2006.239.08:03:32.77$4f8m12a/"tpicd 2006.239.08:03:32.77$4f8m12a/echo=off 2006.239.08:03:32.77$4f8m12a/xlog=off 2006.239.08:03:32.77:!2006.239.08:04:00 2006.239.08:03:42.14#trakl#Source acquired 2006.239.08:03:42.14#flagr#flagr/antenna,acquired 2006.239.08:04:00.00:preob 2006.239.08:04:01.14/onsource/TRACKING 2006.239.08:04:01.14:!2006.239.08:04:10 2006.239.08:04:10.00:data_valid=on 2006.239.08:04:10.00:midob 2006.239.08:04:10.14/onsource/TRACKING 2006.239.08:04:10.14/wx/25.14,1011.6,80 2006.239.08:04:10.26/cable/+6.4157E-03 2006.239.08:04:11.35/va/01,08,usb,yes,34,35 2006.239.08:04:11.35/va/02,07,usb,yes,34,35 2006.239.08:04:11.35/va/03,07,usb,yes,32,32 2006.239.08:04:11.35/va/04,07,usb,yes,35,38 2006.239.08:04:11.35/va/05,08,usb,yes,33,34 2006.239.08:04:11.35/va/06,07,usb,yes,35,35 2006.239.08:04:11.35/va/07,07,usb,yes,35,35 2006.239.08:04:11.35/va/08,07,usb,yes,38,37 2006.239.08:04:11.58/valo/01,532.99,yes,locked 2006.239.08:04:11.58/valo/02,572.99,yes,locked 2006.239.08:04:11.58/valo/03,672.99,yes,locked 2006.239.08:04:11.58/valo/04,832.99,yes,locked 2006.239.08:04:11.58/valo/05,652.99,yes,locked 2006.239.08:04:11.58/valo/06,772.99,yes,locked 2006.239.08:04:11.58/valo/07,832.99,yes,locked 2006.239.08:04:11.58/valo/08,852.99,yes,locked 2006.239.08:04:12.67/vb/01,04,usb,yes,32,30 2006.239.08:04:12.67/vb/02,04,usb,yes,34,35 2006.239.08:04:12.67/vb/03,04,usb,yes,30,34 2006.239.08:04:12.67/vb/04,04,usb,yes,31,31 2006.239.08:04:12.67/vb/05,04,usb,yes,29,33 2006.239.08:04:12.67/vb/06,04,usb,yes,30,33 2006.239.08:04:12.67/vb/07,04,usb,yes,33,32 2006.239.08:04:12.67/vb/08,04,usb,yes,30,33 2006.239.08:04:12.91/vblo/01,632.99,yes,locked 2006.239.08:04:12.91/vblo/02,640.99,yes,locked 2006.239.08:04:12.91/vblo/03,656.99,yes,locked 2006.239.08:04:12.91/vblo/04,712.99,yes,locked 2006.239.08:04:12.91/vblo/05,744.99,yes,locked 2006.239.08:04:12.91/vblo/06,752.99,yes,locked 2006.239.08:04:12.91/vblo/07,734.99,yes,locked 2006.239.08:04:12.91/vblo/08,744.99,yes,locked 2006.239.08:04:13.06/vabw/8 2006.239.08:04:13.21/vbbw/8 2006.239.08:04:13.30/xfe/off,on,13.2 2006.239.08:04:13.67/ifatt/23,28,28,28 2006.239.08:04:14.08/fmout-gps/S +4.41E-07 2006.239.08:04:14.12:!2006.239.08:05:10 2006.239.08:05:10.00:data_valid=off 2006.239.08:05:10.00:postob 2006.239.08:05:10.18/cable/+6.4153E-03 2006.239.08:05:10.18/wx/25.13,1011.6,80 2006.239.08:05:11.08/fmout-gps/S +4.39E-07 2006.239.08:05:11.08:scan_name=239-0806,k06239,60 2006.239.08:05:11.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.239.08:05:11.14#flagr#flagr/antenna,new-source 2006.239.08:05:12.14:checkk5 2006.239.08:05:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:05:12.93/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:05:13.31/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:05:13.69/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:05:14.05/chk_obsdata//k5ts1/T2390804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:05:14.45/chk_obsdata//k5ts2/T2390804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:05:14.82/chk_obsdata//k5ts3/T2390804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:05:15.19/chk_obsdata//k5ts4/T2390804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:05:15.88/k5log//k5ts1_log_newline 2006.239.08:05:16.60/k5log//k5ts2_log_newline 2006.239.08:05:17.29/k5log//k5ts3_log_newline 2006.239.08:05:17.98/k5log//k5ts4_log_newline 2006.239.08:05:18.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:05:18.00:4f8m12a=2 2006.239.08:05:18.00$4f8m12a/echo=on 2006.239.08:05:18.00$4f8m12a/pcalon 2006.239.08:05:18.01$pcalon/"no phase cal control is implemented here 2006.239.08:05:18.01$4f8m12a/"tpicd=stop 2006.239.08:05:18.01$4f8m12a/vc4f8 2006.239.08:05:18.01$vc4f8/valo=1,532.99 2006.239.08:05:18.01#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.08:05:18.01#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.08:05:18.01#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:18.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:18.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:18.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:18.01#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:05:18.01#ibcon#first serial, iclass 13, count 0 2006.239.08:05:18.01#ibcon#enter sib2, iclass 13, count 0 2006.239.08:05:18.01#ibcon#flushed, iclass 13, count 0 2006.239.08:05:18.01#ibcon#about to write, iclass 13, count 0 2006.239.08:05:18.01#ibcon#wrote, iclass 13, count 0 2006.239.08:05:18.01#ibcon#about to read 3, iclass 13, count 0 2006.239.08:05:18.05#ibcon#read 3, iclass 13, count 0 2006.239.08:05:18.05#ibcon#about to read 4, iclass 13, count 0 2006.239.08:05:18.05#ibcon#read 4, iclass 13, count 0 2006.239.08:05:18.05#ibcon#about to read 5, iclass 13, count 0 2006.239.08:05:18.05#ibcon#read 5, iclass 13, count 0 2006.239.08:05:18.05#ibcon#about to read 6, iclass 13, count 0 2006.239.08:05:18.05#ibcon#read 6, iclass 13, count 0 2006.239.08:05:18.05#ibcon#end of sib2, iclass 13, count 0 2006.239.08:05:18.05#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:05:18.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:05:18.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:05:18.05#ibcon#*before write, iclass 13, count 0 2006.239.08:05:18.05#ibcon#enter sib2, iclass 13, count 0 2006.239.08:05:18.05#ibcon#flushed, iclass 13, count 0 2006.239.08:05:18.05#ibcon#about to write, iclass 13, count 0 2006.239.08:05:18.05#ibcon#wrote, iclass 13, count 0 2006.239.08:05:18.05#ibcon#about to read 3, iclass 13, count 0 2006.239.08:05:18.10#ibcon#read 3, iclass 13, count 0 2006.239.08:05:18.10#ibcon#about to read 4, iclass 13, count 0 2006.239.08:05:18.10#ibcon#read 4, iclass 13, count 0 2006.239.08:05:18.10#ibcon#about to read 5, iclass 13, count 0 2006.239.08:05:18.10#ibcon#read 5, iclass 13, count 0 2006.239.08:05:18.10#ibcon#about to read 6, iclass 13, count 0 2006.239.08:05:18.10#ibcon#read 6, iclass 13, count 0 2006.239.08:05:18.10#ibcon#end of sib2, iclass 13, count 0 2006.239.08:05:18.10#ibcon#*after write, iclass 13, count 0 2006.239.08:05:18.10#ibcon#*before return 0, iclass 13, count 0 2006.239.08:05:18.10#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:18.10#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:18.10#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:05:18.10#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:05:18.10$vc4f8/va=1,8 2006.239.08:05:18.10#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.08:05:18.10#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.08:05:18.10#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:18.10#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:18.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:18.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:18.10#ibcon#enter wrdev, iclass 15, count 2 2006.239.08:05:18.10#ibcon#first serial, iclass 15, count 2 2006.239.08:05:18.10#ibcon#enter sib2, iclass 15, count 2 2006.239.08:05:18.10#ibcon#flushed, iclass 15, count 2 2006.239.08:05:18.10#ibcon#about to write, iclass 15, count 2 2006.239.08:05:18.10#ibcon#wrote, iclass 15, count 2 2006.239.08:05:18.10#ibcon#about to read 3, iclass 15, count 2 2006.239.08:05:18.12#ibcon#read 3, iclass 15, count 2 2006.239.08:05:18.12#ibcon#about to read 4, iclass 15, count 2 2006.239.08:05:18.12#ibcon#read 4, iclass 15, count 2 2006.239.08:05:18.12#ibcon#about to read 5, iclass 15, count 2 2006.239.08:05:18.12#ibcon#read 5, iclass 15, count 2 2006.239.08:05:18.12#ibcon#about to read 6, iclass 15, count 2 2006.239.08:05:18.12#ibcon#read 6, iclass 15, count 2 2006.239.08:05:18.12#ibcon#end of sib2, iclass 15, count 2 2006.239.08:05:18.12#ibcon#*mode == 0, iclass 15, count 2 2006.239.08:05:18.12#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.08:05:18.12#ibcon#[25=AT01-08\r\n] 2006.239.08:05:18.12#ibcon#*before write, iclass 15, count 2 2006.239.08:05:18.12#ibcon#enter sib2, iclass 15, count 2 2006.239.08:05:18.12#ibcon#flushed, iclass 15, count 2 2006.239.08:05:18.12#ibcon#about to write, iclass 15, count 2 2006.239.08:05:18.12#ibcon#wrote, iclass 15, count 2 2006.239.08:05:18.12#ibcon#about to read 3, iclass 15, count 2 2006.239.08:05:18.15#ibcon#read 3, iclass 15, count 2 2006.239.08:05:18.15#ibcon#about to read 4, iclass 15, count 2 2006.239.08:05:18.15#ibcon#read 4, iclass 15, count 2 2006.239.08:05:18.15#ibcon#about to read 5, iclass 15, count 2 2006.239.08:05:18.15#ibcon#read 5, iclass 15, count 2 2006.239.08:05:18.15#ibcon#about to read 6, iclass 15, count 2 2006.239.08:05:18.15#ibcon#read 6, iclass 15, count 2 2006.239.08:05:18.15#ibcon#end of sib2, iclass 15, count 2 2006.239.08:05:18.15#ibcon#*after write, iclass 15, count 2 2006.239.08:05:18.15#ibcon#*before return 0, iclass 15, count 2 2006.239.08:05:18.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:18.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:18.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.08:05:18.15#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:18.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:18.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:18.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:18.27#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:05:18.27#ibcon#first serial, iclass 15, count 0 2006.239.08:05:18.27#ibcon#enter sib2, iclass 15, count 0 2006.239.08:05:18.27#ibcon#flushed, iclass 15, count 0 2006.239.08:05:18.27#ibcon#about to write, iclass 15, count 0 2006.239.08:05:18.27#ibcon#wrote, iclass 15, count 0 2006.239.08:05:18.27#ibcon#about to read 3, iclass 15, count 0 2006.239.08:05:18.29#ibcon#read 3, iclass 15, count 0 2006.239.08:05:18.29#ibcon#about to read 4, iclass 15, count 0 2006.239.08:05:18.29#ibcon#read 4, iclass 15, count 0 2006.239.08:05:18.29#ibcon#about to read 5, iclass 15, count 0 2006.239.08:05:18.29#ibcon#read 5, iclass 15, count 0 2006.239.08:05:18.29#ibcon#about to read 6, iclass 15, count 0 2006.239.08:05:18.29#ibcon#read 6, iclass 15, count 0 2006.239.08:05:18.29#ibcon#end of sib2, iclass 15, count 0 2006.239.08:05:18.29#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:05:18.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:05:18.29#ibcon#[25=USB\r\n] 2006.239.08:05:18.29#ibcon#*before write, iclass 15, count 0 2006.239.08:05:18.29#ibcon#enter sib2, iclass 15, count 0 2006.239.08:05:18.29#ibcon#flushed, iclass 15, count 0 2006.239.08:05:18.29#ibcon#about to write, iclass 15, count 0 2006.239.08:05:18.29#ibcon#wrote, iclass 15, count 0 2006.239.08:05:18.29#ibcon#about to read 3, iclass 15, count 0 2006.239.08:05:18.32#ibcon#read 3, iclass 15, count 0 2006.239.08:05:18.32#ibcon#about to read 4, iclass 15, count 0 2006.239.08:05:18.32#ibcon#read 4, iclass 15, count 0 2006.239.08:05:18.32#ibcon#about to read 5, iclass 15, count 0 2006.239.08:05:18.32#ibcon#read 5, iclass 15, count 0 2006.239.08:05:18.32#ibcon#about to read 6, iclass 15, count 0 2006.239.08:05:18.32#ibcon#read 6, iclass 15, count 0 2006.239.08:05:18.32#ibcon#end of sib2, iclass 15, count 0 2006.239.08:05:18.32#ibcon#*after write, iclass 15, count 0 2006.239.08:05:18.32#ibcon#*before return 0, iclass 15, count 0 2006.239.08:05:18.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:18.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:18.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:05:18.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:05:18.32$vc4f8/valo=2,572.99 2006.239.08:05:18.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.08:05:18.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.08:05:18.32#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:18.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:18.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:18.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:18.32#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:05:18.32#ibcon#first serial, iclass 17, count 0 2006.239.08:05:18.32#ibcon#enter sib2, iclass 17, count 0 2006.239.08:05:18.32#ibcon#flushed, iclass 17, count 0 2006.239.08:05:18.32#ibcon#about to write, iclass 17, count 0 2006.239.08:05:18.32#ibcon#wrote, iclass 17, count 0 2006.239.08:05:18.32#ibcon#about to read 3, iclass 17, count 0 2006.239.08:05:18.34#ibcon#read 3, iclass 17, count 0 2006.239.08:05:18.34#ibcon#about to read 4, iclass 17, count 0 2006.239.08:05:18.34#ibcon#read 4, iclass 17, count 0 2006.239.08:05:18.34#ibcon#about to read 5, iclass 17, count 0 2006.239.08:05:18.34#ibcon#read 5, iclass 17, count 0 2006.239.08:05:18.34#ibcon#about to read 6, iclass 17, count 0 2006.239.08:05:18.34#ibcon#read 6, iclass 17, count 0 2006.239.08:05:18.34#ibcon#end of sib2, iclass 17, count 0 2006.239.08:05:18.34#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:05:18.34#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:05:18.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:05:18.34#ibcon#*before write, iclass 17, count 0 2006.239.08:05:18.34#ibcon#enter sib2, iclass 17, count 0 2006.239.08:05:18.34#ibcon#flushed, iclass 17, count 0 2006.239.08:05:18.34#ibcon#about to write, iclass 17, count 0 2006.239.08:05:18.34#ibcon#wrote, iclass 17, count 0 2006.239.08:05:18.34#ibcon#about to read 3, iclass 17, count 0 2006.239.08:05:18.38#ibcon#read 3, iclass 17, count 0 2006.239.08:05:18.38#ibcon#about to read 4, iclass 17, count 0 2006.239.08:05:18.38#ibcon#read 4, iclass 17, count 0 2006.239.08:05:18.38#ibcon#about to read 5, iclass 17, count 0 2006.239.08:05:18.38#ibcon#read 5, iclass 17, count 0 2006.239.08:05:18.38#ibcon#about to read 6, iclass 17, count 0 2006.239.08:05:18.38#ibcon#read 6, iclass 17, count 0 2006.239.08:05:18.38#ibcon#end of sib2, iclass 17, count 0 2006.239.08:05:18.38#ibcon#*after write, iclass 17, count 0 2006.239.08:05:18.38#ibcon#*before return 0, iclass 17, count 0 2006.239.08:05:18.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:18.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:18.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:05:18.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:05:18.38$vc4f8/va=2,7 2006.239.08:05:18.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.08:05:18.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.08:05:18.38#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:18.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:18.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:18.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:18.44#ibcon#enter wrdev, iclass 19, count 2 2006.239.08:05:18.44#ibcon#first serial, iclass 19, count 2 2006.239.08:05:18.44#ibcon#enter sib2, iclass 19, count 2 2006.239.08:05:18.44#ibcon#flushed, iclass 19, count 2 2006.239.08:05:18.44#ibcon#about to write, iclass 19, count 2 2006.239.08:05:18.44#ibcon#wrote, iclass 19, count 2 2006.239.08:05:18.44#ibcon#about to read 3, iclass 19, count 2 2006.239.08:05:18.46#ibcon#read 3, iclass 19, count 2 2006.239.08:05:18.46#ibcon#about to read 4, iclass 19, count 2 2006.239.08:05:18.46#ibcon#read 4, iclass 19, count 2 2006.239.08:05:18.46#ibcon#about to read 5, iclass 19, count 2 2006.239.08:05:18.46#ibcon#read 5, iclass 19, count 2 2006.239.08:05:18.46#ibcon#about to read 6, iclass 19, count 2 2006.239.08:05:18.46#ibcon#read 6, iclass 19, count 2 2006.239.08:05:18.46#ibcon#end of sib2, iclass 19, count 2 2006.239.08:05:18.46#ibcon#*mode == 0, iclass 19, count 2 2006.239.08:05:18.46#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.08:05:18.46#ibcon#[25=AT02-07\r\n] 2006.239.08:05:18.46#ibcon#*before write, iclass 19, count 2 2006.239.08:05:18.46#ibcon#enter sib2, iclass 19, count 2 2006.239.08:05:18.46#ibcon#flushed, iclass 19, count 2 2006.239.08:05:18.46#ibcon#about to write, iclass 19, count 2 2006.239.08:05:18.46#ibcon#wrote, iclass 19, count 2 2006.239.08:05:18.46#ibcon#about to read 3, iclass 19, count 2 2006.239.08:05:18.49#ibcon#read 3, iclass 19, count 2 2006.239.08:05:18.49#ibcon#about to read 4, iclass 19, count 2 2006.239.08:05:18.49#ibcon#read 4, iclass 19, count 2 2006.239.08:05:18.49#ibcon#about to read 5, iclass 19, count 2 2006.239.08:05:18.49#ibcon#read 5, iclass 19, count 2 2006.239.08:05:18.49#ibcon#about to read 6, iclass 19, count 2 2006.239.08:05:18.49#ibcon#read 6, iclass 19, count 2 2006.239.08:05:18.49#ibcon#end of sib2, iclass 19, count 2 2006.239.08:05:18.49#ibcon#*after write, iclass 19, count 2 2006.239.08:05:18.49#ibcon#*before return 0, iclass 19, count 2 2006.239.08:05:18.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:18.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:18.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.08:05:18.49#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:18.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:18.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:18.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:18.61#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:05:18.61#ibcon#first serial, iclass 19, count 0 2006.239.08:05:18.61#ibcon#enter sib2, iclass 19, count 0 2006.239.08:05:18.61#ibcon#flushed, iclass 19, count 0 2006.239.08:05:18.61#ibcon#about to write, iclass 19, count 0 2006.239.08:05:18.61#ibcon#wrote, iclass 19, count 0 2006.239.08:05:18.61#ibcon#about to read 3, iclass 19, count 0 2006.239.08:05:18.63#ibcon#read 3, iclass 19, count 0 2006.239.08:05:18.63#ibcon#about to read 4, iclass 19, count 0 2006.239.08:05:18.63#ibcon#read 4, iclass 19, count 0 2006.239.08:05:18.63#ibcon#about to read 5, iclass 19, count 0 2006.239.08:05:18.63#ibcon#read 5, iclass 19, count 0 2006.239.08:05:18.63#ibcon#about to read 6, iclass 19, count 0 2006.239.08:05:18.63#ibcon#read 6, iclass 19, count 0 2006.239.08:05:18.63#ibcon#end of sib2, iclass 19, count 0 2006.239.08:05:18.63#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:05:18.63#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:05:18.63#ibcon#[25=USB\r\n] 2006.239.08:05:18.63#ibcon#*before write, iclass 19, count 0 2006.239.08:05:18.63#ibcon#enter sib2, iclass 19, count 0 2006.239.08:05:18.63#ibcon#flushed, iclass 19, count 0 2006.239.08:05:18.63#ibcon#about to write, iclass 19, count 0 2006.239.08:05:18.63#ibcon#wrote, iclass 19, count 0 2006.239.08:05:18.63#ibcon#about to read 3, iclass 19, count 0 2006.239.08:05:18.66#ibcon#read 3, iclass 19, count 0 2006.239.08:05:18.66#ibcon#about to read 4, iclass 19, count 0 2006.239.08:05:18.66#ibcon#read 4, iclass 19, count 0 2006.239.08:05:18.66#ibcon#about to read 5, iclass 19, count 0 2006.239.08:05:18.66#ibcon#read 5, iclass 19, count 0 2006.239.08:05:18.66#ibcon#about to read 6, iclass 19, count 0 2006.239.08:05:18.66#ibcon#read 6, iclass 19, count 0 2006.239.08:05:18.66#ibcon#end of sib2, iclass 19, count 0 2006.239.08:05:18.66#ibcon#*after write, iclass 19, count 0 2006.239.08:05:18.66#ibcon#*before return 0, iclass 19, count 0 2006.239.08:05:18.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:18.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:18.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:05:18.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:05:18.66$vc4f8/valo=3,672.99 2006.239.08:05:18.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:05:18.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:05:18.66#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:18.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:18.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:18.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:18.66#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:05:18.66#ibcon#first serial, iclass 21, count 0 2006.239.08:05:18.66#ibcon#enter sib2, iclass 21, count 0 2006.239.08:05:18.66#ibcon#flushed, iclass 21, count 0 2006.239.08:05:18.66#ibcon#about to write, iclass 21, count 0 2006.239.08:05:18.66#ibcon#wrote, iclass 21, count 0 2006.239.08:05:18.66#ibcon#about to read 3, iclass 21, count 0 2006.239.08:05:18.68#ibcon#read 3, iclass 21, count 0 2006.239.08:05:18.68#ibcon#about to read 4, iclass 21, count 0 2006.239.08:05:18.68#ibcon#read 4, iclass 21, count 0 2006.239.08:05:18.68#ibcon#about to read 5, iclass 21, count 0 2006.239.08:05:18.68#ibcon#read 5, iclass 21, count 0 2006.239.08:05:18.68#ibcon#about to read 6, iclass 21, count 0 2006.239.08:05:18.68#ibcon#read 6, iclass 21, count 0 2006.239.08:05:18.68#ibcon#end of sib2, iclass 21, count 0 2006.239.08:05:18.68#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:05:18.68#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:05:18.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:05:18.68#ibcon#*before write, iclass 21, count 0 2006.239.08:05:18.68#ibcon#enter sib2, iclass 21, count 0 2006.239.08:05:18.68#ibcon#flushed, iclass 21, count 0 2006.239.08:05:18.68#ibcon#about to write, iclass 21, count 0 2006.239.08:05:18.68#ibcon#wrote, iclass 21, count 0 2006.239.08:05:18.68#ibcon#about to read 3, iclass 21, count 0 2006.239.08:05:18.72#ibcon#read 3, iclass 21, count 0 2006.239.08:05:18.72#ibcon#about to read 4, iclass 21, count 0 2006.239.08:05:18.72#ibcon#read 4, iclass 21, count 0 2006.239.08:05:18.72#ibcon#about to read 5, iclass 21, count 0 2006.239.08:05:18.72#ibcon#read 5, iclass 21, count 0 2006.239.08:05:18.72#ibcon#about to read 6, iclass 21, count 0 2006.239.08:05:18.72#ibcon#read 6, iclass 21, count 0 2006.239.08:05:18.72#ibcon#end of sib2, iclass 21, count 0 2006.239.08:05:18.72#ibcon#*after write, iclass 21, count 0 2006.239.08:05:18.72#ibcon#*before return 0, iclass 21, count 0 2006.239.08:05:18.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:18.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:18.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:05:18.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:05:18.72$vc4f8/va=3,7 2006.239.08:05:18.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.08:05:18.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.08:05:18.72#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:18.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:18.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:18.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:18.78#ibcon#enter wrdev, iclass 23, count 2 2006.239.08:05:18.78#ibcon#first serial, iclass 23, count 2 2006.239.08:05:18.78#ibcon#enter sib2, iclass 23, count 2 2006.239.08:05:18.78#ibcon#flushed, iclass 23, count 2 2006.239.08:05:18.78#ibcon#about to write, iclass 23, count 2 2006.239.08:05:18.78#ibcon#wrote, iclass 23, count 2 2006.239.08:05:18.78#ibcon#about to read 3, iclass 23, count 2 2006.239.08:05:18.80#ibcon#read 3, iclass 23, count 2 2006.239.08:05:18.80#ibcon#about to read 4, iclass 23, count 2 2006.239.08:05:18.80#ibcon#read 4, iclass 23, count 2 2006.239.08:05:18.80#ibcon#about to read 5, iclass 23, count 2 2006.239.08:05:18.80#ibcon#read 5, iclass 23, count 2 2006.239.08:05:18.80#ibcon#about to read 6, iclass 23, count 2 2006.239.08:05:18.80#ibcon#read 6, iclass 23, count 2 2006.239.08:05:18.80#ibcon#end of sib2, iclass 23, count 2 2006.239.08:05:18.80#ibcon#*mode == 0, iclass 23, count 2 2006.239.08:05:18.80#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.08:05:18.80#ibcon#[25=AT03-07\r\n] 2006.239.08:05:18.80#ibcon#*before write, iclass 23, count 2 2006.239.08:05:18.80#ibcon#enter sib2, iclass 23, count 2 2006.239.08:05:18.80#ibcon#flushed, iclass 23, count 2 2006.239.08:05:18.80#ibcon#about to write, iclass 23, count 2 2006.239.08:05:18.80#ibcon#wrote, iclass 23, count 2 2006.239.08:05:18.80#ibcon#about to read 3, iclass 23, count 2 2006.239.08:05:18.83#ibcon#read 3, iclass 23, count 2 2006.239.08:05:18.83#ibcon#about to read 4, iclass 23, count 2 2006.239.08:05:18.83#ibcon#read 4, iclass 23, count 2 2006.239.08:05:18.83#ibcon#about to read 5, iclass 23, count 2 2006.239.08:05:18.83#ibcon#read 5, iclass 23, count 2 2006.239.08:05:18.83#ibcon#about to read 6, iclass 23, count 2 2006.239.08:05:18.83#ibcon#read 6, iclass 23, count 2 2006.239.08:05:18.83#ibcon#end of sib2, iclass 23, count 2 2006.239.08:05:18.83#ibcon#*after write, iclass 23, count 2 2006.239.08:05:18.83#ibcon#*before return 0, iclass 23, count 2 2006.239.08:05:18.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:18.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:18.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.08:05:18.83#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:18.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:18.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:18.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:18.95#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:05:18.95#ibcon#first serial, iclass 23, count 0 2006.239.08:05:18.95#ibcon#enter sib2, iclass 23, count 0 2006.239.08:05:18.95#ibcon#flushed, iclass 23, count 0 2006.239.08:05:18.95#ibcon#about to write, iclass 23, count 0 2006.239.08:05:18.95#ibcon#wrote, iclass 23, count 0 2006.239.08:05:18.95#ibcon#about to read 3, iclass 23, count 0 2006.239.08:05:18.97#ibcon#read 3, iclass 23, count 0 2006.239.08:05:18.97#ibcon#about to read 4, iclass 23, count 0 2006.239.08:05:18.97#ibcon#read 4, iclass 23, count 0 2006.239.08:05:18.97#ibcon#about to read 5, iclass 23, count 0 2006.239.08:05:18.97#ibcon#read 5, iclass 23, count 0 2006.239.08:05:18.97#ibcon#about to read 6, iclass 23, count 0 2006.239.08:05:18.97#ibcon#read 6, iclass 23, count 0 2006.239.08:05:18.97#ibcon#end of sib2, iclass 23, count 0 2006.239.08:05:18.97#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:05:18.97#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:05:18.97#ibcon#[25=USB\r\n] 2006.239.08:05:18.97#ibcon#*before write, iclass 23, count 0 2006.239.08:05:18.97#ibcon#enter sib2, iclass 23, count 0 2006.239.08:05:18.97#ibcon#flushed, iclass 23, count 0 2006.239.08:05:18.97#ibcon#about to write, iclass 23, count 0 2006.239.08:05:18.97#ibcon#wrote, iclass 23, count 0 2006.239.08:05:18.97#ibcon#about to read 3, iclass 23, count 0 2006.239.08:05:18.97#abcon#<5=/04 2.0 4.0 25.13 801011.6\r\n> 2006.239.08:05:18.99#abcon#{5=INTERFACE CLEAR} 2006.239.08:05:19.00#ibcon#read 3, iclass 23, count 0 2006.239.08:05:19.00#ibcon#about to read 4, iclass 23, count 0 2006.239.08:05:19.00#ibcon#read 4, iclass 23, count 0 2006.239.08:05:19.00#ibcon#about to read 5, iclass 23, count 0 2006.239.08:05:19.00#ibcon#read 5, iclass 23, count 0 2006.239.08:05:19.00#ibcon#about to read 6, iclass 23, count 0 2006.239.08:05:19.00#ibcon#read 6, iclass 23, count 0 2006.239.08:05:19.00#ibcon#end of sib2, iclass 23, count 0 2006.239.08:05:19.00#ibcon#*after write, iclass 23, count 0 2006.239.08:05:19.00#ibcon#*before return 0, iclass 23, count 0 2006.239.08:05:19.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:19.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:19.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:05:19.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:05:19.00$vc4f8/valo=4,832.99 2006.239.08:05:19.00#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:05:19.00#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:05:19.00#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:19.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:05:19.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:05:19.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:05:19.00#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:05:19.00#ibcon#first serial, iclass 28, count 0 2006.239.08:05:19.00#ibcon#enter sib2, iclass 28, count 0 2006.239.08:05:19.00#ibcon#flushed, iclass 28, count 0 2006.239.08:05:19.00#ibcon#about to write, iclass 28, count 0 2006.239.08:05:19.00#ibcon#wrote, iclass 28, count 0 2006.239.08:05:19.00#ibcon#about to read 3, iclass 28, count 0 2006.239.08:05:19.02#ibcon#read 3, iclass 28, count 0 2006.239.08:05:19.02#ibcon#about to read 4, iclass 28, count 0 2006.239.08:05:19.02#ibcon#read 4, iclass 28, count 0 2006.239.08:05:19.02#ibcon#about to read 5, iclass 28, count 0 2006.239.08:05:19.02#ibcon#read 5, iclass 28, count 0 2006.239.08:05:19.02#ibcon#about to read 6, iclass 28, count 0 2006.239.08:05:19.02#ibcon#read 6, iclass 28, count 0 2006.239.08:05:19.02#ibcon#end of sib2, iclass 28, count 0 2006.239.08:05:19.02#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:05:19.02#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:05:19.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:05:19.02#ibcon#*before write, iclass 28, count 0 2006.239.08:05:19.02#ibcon#enter sib2, iclass 28, count 0 2006.239.08:05:19.02#ibcon#flushed, iclass 28, count 0 2006.239.08:05:19.02#ibcon#about to write, iclass 28, count 0 2006.239.08:05:19.02#ibcon#wrote, iclass 28, count 0 2006.239.08:05:19.02#ibcon#about to read 3, iclass 28, count 0 2006.239.08:05:19.05#abcon#[5=S1D000X0/0*\r\n] 2006.239.08:05:19.06#ibcon#read 3, iclass 28, count 0 2006.239.08:05:19.06#ibcon#about to read 4, iclass 28, count 0 2006.239.08:05:19.06#ibcon#read 4, iclass 28, count 0 2006.239.08:05:19.06#ibcon#about to read 5, iclass 28, count 0 2006.239.08:05:19.06#ibcon#read 5, iclass 28, count 0 2006.239.08:05:19.06#ibcon#about to read 6, iclass 28, count 0 2006.239.08:05:19.06#ibcon#read 6, iclass 28, count 0 2006.239.08:05:19.06#ibcon#end of sib2, iclass 28, count 0 2006.239.08:05:19.06#ibcon#*after write, iclass 28, count 0 2006.239.08:05:19.06#ibcon#*before return 0, iclass 28, count 0 2006.239.08:05:19.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:05:19.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:05:19.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:05:19.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:05:19.06$vc4f8/va=4,7 2006.239.08:05:19.06#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.08:05:19.06#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.08:05:19.06#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:19.06#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:19.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:19.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:19.12#ibcon#enter wrdev, iclass 31, count 2 2006.239.08:05:19.12#ibcon#first serial, iclass 31, count 2 2006.239.08:05:19.12#ibcon#enter sib2, iclass 31, count 2 2006.239.08:05:19.12#ibcon#flushed, iclass 31, count 2 2006.239.08:05:19.12#ibcon#about to write, iclass 31, count 2 2006.239.08:05:19.12#ibcon#wrote, iclass 31, count 2 2006.239.08:05:19.12#ibcon#about to read 3, iclass 31, count 2 2006.239.08:05:19.14#ibcon#read 3, iclass 31, count 2 2006.239.08:05:19.14#ibcon#about to read 4, iclass 31, count 2 2006.239.08:05:19.14#ibcon#read 4, iclass 31, count 2 2006.239.08:05:19.14#ibcon#about to read 5, iclass 31, count 2 2006.239.08:05:19.14#ibcon#read 5, iclass 31, count 2 2006.239.08:05:19.14#ibcon#about to read 6, iclass 31, count 2 2006.239.08:05:19.14#ibcon#read 6, iclass 31, count 2 2006.239.08:05:19.14#ibcon#end of sib2, iclass 31, count 2 2006.239.08:05:19.14#ibcon#*mode == 0, iclass 31, count 2 2006.239.08:05:19.14#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.08:05:19.14#ibcon#[25=AT04-07\r\n] 2006.239.08:05:19.14#ibcon#*before write, iclass 31, count 2 2006.239.08:05:19.14#ibcon#enter sib2, iclass 31, count 2 2006.239.08:05:19.14#ibcon#flushed, iclass 31, count 2 2006.239.08:05:19.14#ibcon#about to write, iclass 31, count 2 2006.239.08:05:19.14#ibcon#wrote, iclass 31, count 2 2006.239.08:05:19.14#ibcon#about to read 3, iclass 31, count 2 2006.239.08:05:19.17#ibcon#read 3, iclass 31, count 2 2006.239.08:05:19.17#ibcon#about to read 4, iclass 31, count 2 2006.239.08:05:19.17#ibcon#read 4, iclass 31, count 2 2006.239.08:05:19.17#ibcon#about to read 5, iclass 31, count 2 2006.239.08:05:19.17#ibcon#read 5, iclass 31, count 2 2006.239.08:05:19.17#ibcon#about to read 6, iclass 31, count 2 2006.239.08:05:19.17#ibcon#read 6, iclass 31, count 2 2006.239.08:05:19.17#ibcon#end of sib2, iclass 31, count 2 2006.239.08:05:19.17#ibcon#*after write, iclass 31, count 2 2006.239.08:05:19.17#ibcon#*before return 0, iclass 31, count 2 2006.239.08:05:19.17#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:19.17#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:19.17#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.08:05:19.17#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:19.17#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:19.29#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:19.29#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:19.29#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:05:19.29#ibcon#first serial, iclass 31, count 0 2006.239.08:05:19.29#ibcon#enter sib2, iclass 31, count 0 2006.239.08:05:19.29#ibcon#flushed, iclass 31, count 0 2006.239.08:05:19.29#ibcon#about to write, iclass 31, count 0 2006.239.08:05:19.29#ibcon#wrote, iclass 31, count 0 2006.239.08:05:19.29#ibcon#about to read 3, iclass 31, count 0 2006.239.08:05:19.31#ibcon#read 3, iclass 31, count 0 2006.239.08:05:19.31#ibcon#about to read 4, iclass 31, count 0 2006.239.08:05:19.31#ibcon#read 4, iclass 31, count 0 2006.239.08:05:19.31#ibcon#about to read 5, iclass 31, count 0 2006.239.08:05:19.31#ibcon#read 5, iclass 31, count 0 2006.239.08:05:19.31#ibcon#about to read 6, iclass 31, count 0 2006.239.08:05:19.31#ibcon#read 6, iclass 31, count 0 2006.239.08:05:19.31#ibcon#end of sib2, iclass 31, count 0 2006.239.08:05:19.31#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:05:19.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:05:19.31#ibcon#[25=USB\r\n] 2006.239.08:05:19.31#ibcon#*before write, iclass 31, count 0 2006.239.08:05:19.31#ibcon#enter sib2, iclass 31, count 0 2006.239.08:05:19.31#ibcon#flushed, iclass 31, count 0 2006.239.08:05:19.31#ibcon#about to write, iclass 31, count 0 2006.239.08:05:19.31#ibcon#wrote, iclass 31, count 0 2006.239.08:05:19.31#ibcon#about to read 3, iclass 31, count 0 2006.239.08:05:19.34#ibcon#read 3, iclass 31, count 0 2006.239.08:05:19.34#ibcon#about to read 4, iclass 31, count 0 2006.239.08:05:19.34#ibcon#read 4, iclass 31, count 0 2006.239.08:05:19.34#ibcon#about to read 5, iclass 31, count 0 2006.239.08:05:19.34#ibcon#read 5, iclass 31, count 0 2006.239.08:05:19.34#ibcon#about to read 6, iclass 31, count 0 2006.239.08:05:19.34#ibcon#read 6, iclass 31, count 0 2006.239.08:05:19.34#ibcon#end of sib2, iclass 31, count 0 2006.239.08:05:19.34#ibcon#*after write, iclass 31, count 0 2006.239.08:05:19.34#ibcon#*before return 0, iclass 31, count 0 2006.239.08:05:19.34#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:19.34#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:19.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:05:19.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:05:19.34$vc4f8/valo=5,652.99 2006.239.08:05:19.34#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.08:05:19.34#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.08:05:19.34#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:19.34#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:19.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:19.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:19.34#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:05:19.34#ibcon#first serial, iclass 33, count 0 2006.239.08:05:19.34#ibcon#enter sib2, iclass 33, count 0 2006.239.08:05:19.34#ibcon#flushed, iclass 33, count 0 2006.239.08:05:19.34#ibcon#about to write, iclass 33, count 0 2006.239.08:05:19.34#ibcon#wrote, iclass 33, count 0 2006.239.08:05:19.34#ibcon#about to read 3, iclass 33, count 0 2006.239.08:05:19.36#ibcon#read 3, iclass 33, count 0 2006.239.08:05:19.36#ibcon#about to read 4, iclass 33, count 0 2006.239.08:05:19.36#ibcon#read 4, iclass 33, count 0 2006.239.08:05:19.36#ibcon#about to read 5, iclass 33, count 0 2006.239.08:05:19.36#ibcon#read 5, iclass 33, count 0 2006.239.08:05:19.36#ibcon#about to read 6, iclass 33, count 0 2006.239.08:05:19.36#ibcon#read 6, iclass 33, count 0 2006.239.08:05:19.36#ibcon#end of sib2, iclass 33, count 0 2006.239.08:05:19.36#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:05:19.36#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:05:19.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:05:19.36#ibcon#*before write, iclass 33, count 0 2006.239.08:05:19.36#ibcon#enter sib2, iclass 33, count 0 2006.239.08:05:19.36#ibcon#flushed, iclass 33, count 0 2006.239.08:05:19.36#ibcon#about to write, iclass 33, count 0 2006.239.08:05:19.36#ibcon#wrote, iclass 33, count 0 2006.239.08:05:19.36#ibcon#about to read 3, iclass 33, count 0 2006.239.08:05:19.40#ibcon#read 3, iclass 33, count 0 2006.239.08:05:19.40#ibcon#about to read 4, iclass 33, count 0 2006.239.08:05:19.40#ibcon#read 4, iclass 33, count 0 2006.239.08:05:19.40#ibcon#about to read 5, iclass 33, count 0 2006.239.08:05:19.40#ibcon#read 5, iclass 33, count 0 2006.239.08:05:19.40#ibcon#about to read 6, iclass 33, count 0 2006.239.08:05:19.40#ibcon#read 6, iclass 33, count 0 2006.239.08:05:19.40#ibcon#end of sib2, iclass 33, count 0 2006.239.08:05:19.40#ibcon#*after write, iclass 33, count 0 2006.239.08:05:19.40#ibcon#*before return 0, iclass 33, count 0 2006.239.08:05:19.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:19.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:19.40#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:05:19.40#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:05:19.40$vc4f8/va=5,8 2006.239.08:05:19.40#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.08:05:19.40#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.08:05:19.40#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:19.40#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:19.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:19.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:19.46#ibcon#enter wrdev, iclass 35, count 2 2006.239.08:05:19.46#ibcon#first serial, iclass 35, count 2 2006.239.08:05:19.46#ibcon#enter sib2, iclass 35, count 2 2006.239.08:05:19.46#ibcon#flushed, iclass 35, count 2 2006.239.08:05:19.46#ibcon#about to write, iclass 35, count 2 2006.239.08:05:19.46#ibcon#wrote, iclass 35, count 2 2006.239.08:05:19.46#ibcon#about to read 3, iclass 35, count 2 2006.239.08:05:19.48#ibcon#read 3, iclass 35, count 2 2006.239.08:05:19.48#ibcon#about to read 4, iclass 35, count 2 2006.239.08:05:19.48#ibcon#read 4, iclass 35, count 2 2006.239.08:05:19.48#ibcon#about to read 5, iclass 35, count 2 2006.239.08:05:19.48#ibcon#read 5, iclass 35, count 2 2006.239.08:05:19.48#ibcon#about to read 6, iclass 35, count 2 2006.239.08:05:19.48#ibcon#read 6, iclass 35, count 2 2006.239.08:05:19.48#ibcon#end of sib2, iclass 35, count 2 2006.239.08:05:19.48#ibcon#*mode == 0, iclass 35, count 2 2006.239.08:05:19.48#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.08:05:19.48#ibcon#[25=AT05-08\r\n] 2006.239.08:05:19.48#ibcon#*before write, iclass 35, count 2 2006.239.08:05:19.48#ibcon#enter sib2, iclass 35, count 2 2006.239.08:05:19.48#ibcon#flushed, iclass 35, count 2 2006.239.08:05:19.48#ibcon#about to write, iclass 35, count 2 2006.239.08:05:19.48#ibcon#wrote, iclass 35, count 2 2006.239.08:05:19.48#ibcon#about to read 3, iclass 35, count 2 2006.239.08:05:19.53#ibcon#read 3, iclass 35, count 2 2006.239.08:05:19.53#ibcon#about to read 4, iclass 35, count 2 2006.239.08:05:19.53#ibcon#read 4, iclass 35, count 2 2006.239.08:05:19.53#ibcon#about to read 5, iclass 35, count 2 2006.239.08:05:19.53#ibcon#read 5, iclass 35, count 2 2006.239.08:05:19.53#ibcon#about to read 6, iclass 35, count 2 2006.239.08:05:19.53#ibcon#read 6, iclass 35, count 2 2006.239.08:05:19.53#ibcon#end of sib2, iclass 35, count 2 2006.239.08:05:19.53#ibcon#*after write, iclass 35, count 2 2006.239.08:05:19.53#ibcon#*before return 0, iclass 35, count 2 2006.239.08:05:19.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:19.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:19.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.08:05:19.53#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:19.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:19.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:19.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:19.65#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:05:19.65#ibcon#first serial, iclass 35, count 0 2006.239.08:05:19.65#ibcon#enter sib2, iclass 35, count 0 2006.239.08:05:19.65#ibcon#flushed, iclass 35, count 0 2006.239.08:05:19.65#ibcon#about to write, iclass 35, count 0 2006.239.08:05:19.65#ibcon#wrote, iclass 35, count 0 2006.239.08:05:19.65#ibcon#about to read 3, iclass 35, count 0 2006.239.08:05:19.67#ibcon#read 3, iclass 35, count 0 2006.239.08:05:19.67#ibcon#about to read 4, iclass 35, count 0 2006.239.08:05:19.67#ibcon#read 4, iclass 35, count 0 2006.239.08:05:19.67#ibcon#about to read 5, iclass 35, count 0 2006.239.08:05:19.67#ibcon#read 5, iclass 35, count 0 2006.239.08:05:19.67#ibcon#about to read 6, iclass 35, count 0 2006.239.08:05:19.67#ibcon#read 6, iclass 35, count 0 2006.239.08:05:19.67#ibcon#end of sib2, iclass 35, count 0 2006.239.08:05:19.67#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:05:19.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:05:19.67#ibcon#[25=USB\r\n] 2006.239.08:05:19.67#ibcon#*before write, iclass 35, count 0 2006.239.08:05:19.67#ibcon#enter sib2, iclass 35, count 0 2006.239.08:05:19.67#ibcon#flushed, iclass 35, count 0 2006.239.08:05:19.67#ibcon#about to write, iclass 35, count 0 2006.239.08:05:19.67#ibcon#wrote, iclass 35, count 0 2006.239.08:05:19.67#ibcon#about to read 3, iclass 35, count 0 2006.239.08:05:19.70#ibcon#read 3, iclass 35, count 0 2006.239.08:05:19.70#ibcon#about to read 4, iclass 35, count 0 2006.239.08:05:19.70#ibcon#read 4, iclass 35, count 0 2006.239.08:05:19.70#ibcon#about to read 5, iclass 35, count 0 2006.239.08:05:19.70#ibcon#read 5, iclass 35, count 0 2006.239.08:05:19.70#ibcon#about to read 6, iclass 35, count 0 2006.239.08:05:19.70#ibcon#read 6, iclass 35, count 0 2006.239.08:05:19.70#ibcon#end of sib2, iclass 35, count 0 2006.239.08:05:19.70#ibcon#*after write, iclass 35, count 0 2006.239.08:05:19.70#ibcon#*before return 0, iclass 35, count 0 2006.239.08:05:19.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:19.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:19.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:05:19.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:05:19.70$vc4f8/valo=6,772.99 2006.239.08:05:19.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.08:05:19.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.08:05:19.70#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:19.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:19.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:19.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:19.70#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:05:19.70#ibcon#first serial, iclass 37, count 0 2006.239.08:05:19.70#ibcon#enter sib2, iclass 37, count 0 2006.239.08:05:19.70#ibcon#flushed, iclass 37, count 0 2006.239.08:05:19.70#ibcon#about to write, iclass 37, count 0 2006.239.08:05:19.70#ibcon#wrote, iclass 37, count 0 2006.239.08:05:19.70#ibcon#about to read 3, iclass 37, count 0 2006.239.08:05:19.72#ibcon#read 3, iclass 37, count 0 2006.239.08:05:19.72#ibcon#about to read 4, iclass 37, count 0 2006.239.08:05:19.72#ibcon#read 4, iclass 37, count 0 2006.239.08:05:19.72#ibcon#about to read 5, iclass 37, count 0 2006.239.08:05:19.72#ibcon#read 5, iclass 37, count 0 2006.239.08:05:19.72#ibcon#about to read 6, iclass 37, count 0 2006.239.08:05:19.72#ibcon#read 6, iclass 37, count 0 2006.239.08:05:19.72#ibcon#end of sib2, iclass 37, count 0 2006.239.08:05:19.72#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:05:19.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:05:19.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:05:19.72#ibcon#*before write, iclass 37, count 0 2006.239.08:05:19.72#ibcon#enter sib2, iclass 37, count 0 2006.239.08:05:19.72#ibcon#flushed, iclass 37, count 0 2006.239.08:05:19.72#ibcon#about to write, iclass 37, count 0 2006.239.08:05:19.72#ibcon#wrote, iclass 37, count 0 2006.239.08:05:19.72#ibcon#about to read 3, iclass 37, count 0 2006.239.08:05:19.76#ibcon#read 3, iclass 37, count 0 2006.239.08:05:19.76#ibcon#about to read 4, iclass 37, count 0 2006.239.08:05:19.76#ibcon#read 4, iclass 37, count 0 2006.239.08:05:19.76#ibcon#about to read 5, iclass 37, count 0 2006.239.08:05:19.76#ibcon#read 5, iclass 37, count 0 2006.239.08:05:19.76#ibcon#about to read 6, iclass 37, count 0 2006.239.08:05:19.76#ibcon#read 6, iclass 37, count 0 2006.239.08:05:19.76#ibcon#end of sib2, iclass 37, count 0 2006.239.08:05:19.76#ibcon#*after write, iclass 37, count 0 2006.239.08:05:19.76#ibcon#*before return 0, iclass 37, count 0 2006.239.08:05:19.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:19.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:19.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:05:19.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:05:19.76$vc4f8/va=6,7 2006.239.08:05:19.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.08:05:19.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.08:05:19.76#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:19.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:05:19.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:05:19.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:05:19.82#ibcon#enter wrdev, iclass 39, count 2 2006.239.08:05:19.82#ibcon#first serial, iclass 39, count 2 2006.239.08:05:19.82#ibcon#enter sib2, iclass 39, count 2 2006.239.08:05:19.82#ibcon#flushed, iclass 39, count 2 2006.239.08:05:19.82#ibcon#about to write, iclass 39, count 2 2006.239.08:05:19.82#ibcon#wrote, iclass 39, count 2 2006.239.08:05:19.82#ibcon#about to read 3, iclass 39, count 2 2006.239.08:05:19.84#ibcon#read 3, iclass 39, count 2 2006.239.08:05:19.84#ibcon#about to read 4, iclass 39, count 2 2006.239.08:05:19.84#ibcon#read 4, iclass 39, count 2 2006.239.08:05:19.84#ibcon#about to read 5, iclass 39, count 2 2006.239.08:05:19.84#ibcon#read 5, iclass 39, count 2 2006.239.08:05:19.84#ibcon#about to read 6, iclass 39, count 2 2006.239.08:05:19.84#ibcon#read 6, iclass 39, count 2 2006.239.08:05:19.84#ibcon#end of sib2, iclass 39, count 2 2006.239.08:05:19.84#ibcon#*mode == 0, iclass 39, count 2 2006.239.08:05:19.84#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.08:05:19.84#ibcon#[25=AT06-07\r\n] 2006.239.08:05:19.84#ibcon#*before write, iclass 39, count 2 2006.239.08:05:19.84#ibcon#enter sib2, iclass 39, count 2 2006.239.08:05:19.84#ibcon#flushed, iclass 39, count 2 2006.239.08:05:19.84#ibcon#about to write, iclass 39, count 2 2006.239.08:05:19.84#ibcon#wrote, iclass 39, count 2 2006.239.08:05:19.84#ibcon#about to read 3, iclass 39, count 2 2006.239.08:05:19.87#ibcon#read 3, iclass 39, count 2 2006.239.08:05:19.87#ibcon#about to read 4, iclass 39, count 2 2006.239.08:05:19.87#ibcon#read 4, iclass 39, count 2 2006.239.08:05:19.87#ibcon#about to read 5, iclass 39, count 2 2006.239.08:05:19.87#ibcon#read 5, iclass 39, count 2 2006.239.08:05:19.87#ibcon#about to read 6, iclass 39, count 2 2006.239.08:05:19.87#ibcon#read 6, iclass 39, count 2 2006.239.08:05:19.87#ibcon#end of sib2, iclass 39, count 2 2006.239.08:05:19.87#ibcon#*after write, iclass 39, count 2 2006.239.08:05:19.87#ibcon#*before return 0, iclass 39, count 2 2006.239.08:05:19.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:05:19.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:05:19.87#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.08:05:19.87#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:19.87#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:05:19.99#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:05:19.99#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:05:19.99#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:05:19.99#ibcon#first serial, iclass 39, count 0 2006.239.08:05:19.99#ibcon#enter sib2, iclass 39, count 0 2006.239.08:05:19.99#ibcon#flushed, iclass 39, count 0 2006.239.08:05:19.99#ibcon#about to write, iclass 39, count 0 2006.239.08:05:19.99#ibcon#wrote, iclass 39, count 0 2006.239.08:05:19.99#ibcon#about to read 3, iclass 39, count 0 2006.239.08:05:20.01#ibcon#read 3, iclass 39, count 0 2006.239.08:05:20.01#ibcon#about to read 4, iclass 39, count 0 2006.239.08:05:20.01#ibcon#read 4, iclass 39, count 0 2006.239.08:05:20.01#ibcon#about to read 5, iclass 39, count 0 2006.239.08:05:20.01#ibcon#read 5, iclass 39, count 0 2006.239.08:05:20.01#ibcon#about to read 6, iclass 39, count 0 2006.239.08:05:20.01#ibcon#read 6, iclass 39, count 0 2006.239.08:05:20.01#ibcon#end of sib2, iclass 39, count 0 2006.239.08:05:20.01#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:05:20.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:05:20.01#ibcon#[25=USB\r\n] 2006.239.08:05:20.01#ibcon#*before write, iclass 39, count 0 2006.239.08:05:20.01#ibcon#enter sib2, iclass 39, count 0 2006.239.08:05:20.01#ibcon#flushed, iclass 39, count 0 2006.239.08:05:20.01#ibcon#about to write, iclass 39, count 0 2006.239.08:05:20.01#ibcon#wrote, iclass 39, count 0 2006.239.08:05:20.01#ibcon#about to read 3, iclass 39, count 0 2006.239.08:05:20.04#ibcon#read 3, iclass 39, count 0 2006.239.08:05:20.04#ibcon#about to read 4, iclass 39, count 0 2006.239.08:05:20.04#ibcon#read 4, iclass 39, count 0 2006.239.08:05:20.04#ibcon#about to read 5, iclass 39, count 0 2006.239.08:05:20.04#ibcon#read 5, iclass 39, count 0 2006.239.08:05:20.04#ibcon#about to read 6, iclass 39, count 0 2006.239.08:05:20.04#ibcon#read 6, iclass 39, count 0 2006.239.08:05:20.04#ibcon#end of sib2, iclass 39, count 0 2006.239.08:05:20.04#ibcon#*after write, iclass 39, count 0 2006.239.08:05:20.04#ibcon#*before return 0, iclass 39, count 0 2006.239.08:05:20.04#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:05:20.04#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:05:20.04#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:05:20.04#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:05:20.04$vc4f8/valo=7,832.99 2006.239.08:05:20.04#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.08:05:20.04#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.08:05:20.04#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:20.04#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:05:20.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:05:20.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:05:20.04#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:05:20.04#ibcon#first serial, iclass 3, count 0 2006.239.08:05:20.04#ibcon#enter sib2, iclass 3, count 0 2006.239.08:05:20.04#ibcon#flushed, iclass 3, count 0 2006.239.08:05:20.04#ibcon#about to write, iclass 3, count 0 2006.239.08:05:20.04#ibcon#wrote, iclass 3, count 0 2006.239.08:05:20.04#ibcon#about to read 3, iclass 3, count 0 2006.239.08:05:20.06#ibcon#read 3, iclass 3, count 0 2006.239.08:05:20.06#ibcon#about to read 4, iclass 3, count 0 2006.239.08:05:20.06#ibcon#read 4, iclass 3, count 0 2006.239.08:05:20.06#ibcon#about to read 5, iclass 3, count 0 2006.239.08:05:20.06#ibcon#read 5, iclass 3, count 0 2006.239.08:05:20.06#ibcon#about to read 6, iclass 3, count 0 2006.239.08:05:20.06#ibcon#read 6, iclass 3, count 0 2006.239.08:05:20.06#ibcon#end of sib2, iclass 3, count 0 2006.239.08:05:20.06#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:05:20.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:05:20.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:05:20.06#ibcon#*before write, iclass 3, count 0 2006.239.08:05:20.06#ibcon#enter sib2, iclass 3, count 0 2006.239.08:05:20.06#ibcon#flushed, iclass 3, count 0 2006.239.08:05:20.06#ibcon#about to write, iclass 3, count 0 2006.239.08:05:20.06#ibcon#wrote, iclass 3, count 0 2006.239.08:05:20.06#ibcon#about to read 3, iclass 3, count 0 2006.239.08:05:20.10#ibcon#read 3, iclass 3, count 0 2006.239.08:05:20.10#ibcon#about to read 4, iclass 3, count 0 2006.239.08:05:20.10#ibcon#read 4, iclass 3, count 0 2006.239.08:05:20.10#ibcon#about to read 5, iclass 3, count 0 2006.239.08:05:20.10#ibcon#read 5, iclass 3, count 0 2006.239.08:05:20.10#ibcon#about to read 6, iclass 3, count 0 2006.239.08:05:20.10#ibcon#read 6, iclass 3, count 0 2006.239.08:05:20.10#ibcon#end of sib2, iclass 3, count 0 2006.239.08:05:20.10#ibcon#*after write, iclass 3, count 0 2006.239.08:05:20.10#ibcon#*before return 0, iclass 3, count 0 2006.239.08:05:20.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:05:20.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:05:20.10#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:05:20.10#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:05:20.10$vc4f8/va=7,7 2006.239.08:05:20.10#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.08:05:20.10#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.08:05:20.10#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:20.10#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:05:20.16#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:05:20.16#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:05:20.16#ibcon#enter wrdev, iclass 5, count 2 2006.239.08:05:20.16#ibcon#first serial, iclass 5, count 2 2006.239.08:05:20.16#ibcon#enter sib2, iclass 5, count 2 2006.239.08:05:20.16#ibcon#flushed, iclass 5, count 2 2006.239.08:05:20.16#ibcon#about to write, iclass 5, count 2 2006.239.08:05:20.16#ibcon#wrote, iclass 5, count 2 2006.239.08:05:20.16#ibcon#about to read 3, iclass 5, count 2 2006.239.08:05:20.18#ibcon#read 3, iclass 5, count 2 2006.239.08:05:20.18#ibcon#about to read 4, iclass 5, count 2 2006.239.08:05:20.18#ibcon#read 4, iclass 5, count 2 2006.239.08:05:20.18#ibcon#about to read 5, iclass 5, count 2 2006.239.08:05:20.18#ibcon#read 5, iclass 5, count 2 2006.239.08:05:20.18#ibcon#about to read 6, iclass 5, count 2 2006.239.08:05:20.18#ibcon#read 6, iclass 5, count 2 2006.239.08:05:20.18#ibcon#end of sib2, iclass 5, count 2 2006.239.08:05:20.18#ibcon#*mode == 0, iclass 5, count 2 2006.239.08:05:20.18#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.08:05:20.18#ibcon#[25=AT07-07\r\n] 2006.239.08:05:20.18#ibcon#*before write, iclass 5, count 2 2006.239.08:05:20.18#ibcon#enter sib2, iclass 5, count 2 2006.239.08:05:20.18#ibcon#flushed, iclass 5, count 2 2006.239.08:05:20.18#ibcon#about to write, iclass 5, count 2 2006.239.08:05:20.18#ibcon#wrote, iclass 5, count 2 2006.239.08:05:20.18#ibcon#about to read 3, iclass 5, count 2 2006.239.08:05:20.21#ibcon#read 3, iclass 5, count 2 2006.239.08:05:20.21#ibcon#about to read 4, iclass 5, count 2 2006.239.08:05:20.21#ibcon#read 4, iclass 5, count 2 2006.239.08:05:20.21#ibcon#about to read 5, iclass 5, count 2 2006.239.08:05:20.21#ibcon#read 5, iclass 5, count 2 2006.239.08:05:20.21#ibcon#about to read 6, iclass 5, count 2 2006.239.08:05:20.21#ibcon#read 6, iclass 5, count 2 2006.239.08:05:20.21#ibcon#end of sib2, iclass 5, count 2 2006.239.08:05:20.21#ibcon#*after write, iclass 5, count 2 2006.239.08:05:20.21#ibcon#*before return 0, iclass 5, count 2 2006.239.08:05:20.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:05:20.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:05:20.21#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.08:05:20.21#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:20.21#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:05:20.33#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:05:20.33#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:05:20.33#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:05:20.33#ibcon#first serial, iclass 5, count 0 2006.239.08:05:20.33#ibcon#enter sib2, iclass 5, count 0 2006.239.08:05:20.33#ibcon#flushed, iclass 5, count 0 2006.239.08:05:20.33#ibcon#about to write, iclass 5, count 0 2006.239.08:05:20.33#ibcon#wrote, iclass 5, count 0 2006.239.08:05:20.33#ibcon#about to read 3, iclass 5, count 0 2006.239.08:05:20.35#ibcon#read 3, iclass 5, count 0 2006.239.08:05:20.35#ibcon#about to read 4, iclass 5, count 0 2006.239.08:05:20.35#ibcon#read 4, iclass 5, count 0 2006.239.08:05:20.35#ibcon#about to read 5, iclass 5, count 0 2006.239.08:05:20.35#ibcon#read 5, iclass 5, count 0 2006.239.08:05:20.35#ibcon#about to read 6, iclass 5, count 0 2006.239.08:05:20.35#ibcon#read 6, iclass 5, count 0 2006.239.08:05:20.35#ibcon#end of sib2, iclass 5, count 0 2006.239.08:05:20.35#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:05:20.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:05:20.35#ibcon#[25=USB\r\n] 2006.239.08:05:20.35#ibcon#*before write, iclass 5, count 0 2006.239.08:05:20.35#ibcon#enter sib2, iclass 5, count 0 2006.239.08:05:20.35#ibcon#flushed, iclass 5, count 0 2006.239.08:05:20.35#ibcon#about to write, iclass 5, count 0 2006.239.08:05:20.35#ibcon#wrote, iclass 5, count 0 2006.239.08:05:20.35#ibcon#about to read 3, iclass 5, count 0 2006.239.08:05:20.38#ibcon#read 3, iclass 5, count 0 2006.239.08:05:20.38#ibcon#about to read 4, iclass 5, count 0 2006.239.08:05:20.38#ibcon#read 4, iclass 5, count 0 2006.239.08:05:20.38#ibcon#about to read 5, iclass 5, count 0 2006.239.08:05:20.38#ibcon#read 5, iclass 5, count 0 2006.239.08:05:20.38#ibcon#about to read 6, iclass 5, count 0 2006.239.08:05:20.38#ibcon#read 6, iclass 5, count 0 2006.239.08:05:20.38#ibcon#end of sib2, iclass 5, count 0 2006.239.08:05:20.38#ibcon#*after write, iclass 5, count 0 2006.239.08:05:20.38#ibcon#*before return 0, iclass 5, count 0 2006.239.08:05:20.38#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:05:20.38#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:05:20.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:05:20.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:05:20.38$vc4f8/valo=8,852.99 2006.239.08:05:20.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.08:05:20.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.08:05:20.38#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:20.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:05:20.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:05:20.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:05:20.38#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:05:20.38#ibcon#first serial, iclass 7, count 0 2006.239.08:05:20.38#ibcon#enter sib2, iclass 7, count 0 2006.239.08:05:20.38#ibcon#flushed, iclass 7, count 0 2006.239.08:05:20.38#ibcon#about to write, iclass 7, count 0 2006.239.08:05:20.38#ibcon#wrote, iclass 7, count 0 2006.239.08:05:20.38#ibcon#about to read 3, iclass 7, count 0 2006.239.08:05:20.40#ibcon#read 3, iclass 7, count 0 2006.239.08:05:20.40#ibcon#about to read 4, iclass 7, count 0 2006.239.08:05:20.40#ibcon#read 4, iclass 7, count 0 2006.239.08:05:20.40#ibcon#about to read 5, iclass 7, count 0 2006.239.08:05:20.40#ibcon#read 5, iclass 7, count 0 2006.239.08:05:20.40#ibcon#about to read 6, iclass 7, count 0 2006.239.08:05:20.40#ibcon#read 6, iclass 7, count 0 2006.239.08:05:20.40#ibcon#end of sib2, iclass 7, count 0 2006.239.08:05:20.40#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:05:20.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:05:20.40#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:05:20.40#ibcon#*before write, iclass 7, count 0 2006.239.08:05:20.40#ibcon#enter sib2, iclass 7, count 0 2006.239.08:05:20.40#ibcon#flushed, iclass 7, count 0 2006.239.08:05:20.40#ibcon#about to write, iclass 7, count 0 2006.239.08:05:20.40#ibcon#wrote, iclass 7, count 0 2006.239.08:05:20.40#ibcon#about to read 3, iclass 7, count 0 2006.239.08:05:20.44#ibcon#read 3, iclass 7, count 0 2006.239.08:05:20.44#ibcon#about to read 4, iclass 7, count 0 2006.239.08:05:20.44#ibcon#read 4, iclass 7, count 0 2006.239.08:05:20.44#ibcon#about to read 5, iclass 7, count 0 2006.239.08:05:20.44#ibcon#read 5, iclass 7, count 0 2006.239.08:05:20.44#ibcon#about to read 6, iclass 7, count 0 2006.239.08:05:20.44#ibcon#read 6, iclass 7, count 0 2006.239.08:05:20.44#ibcon#end of sib2, iclass 7, count 0 2006.239.08:05:20.44#ibcon#*after write, iclass 7, count 0 2006.239.08:05:20.44#ibcon#*before return 0, iclass 7, count 0 2006.239.08:05:20.44#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:05:20.44#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:05:20.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:05:20.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:05:20.44$vc4f8/va=8,7 2006.239.08:05:20.44#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.08:05:20.44#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.08:05:20.44#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:20.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:05:20.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:05:20.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:05:20.50#ibcon#enter wrdev, iclass 11, count 2 2006.239.08:05:20.50#ibcon#first serial, iclass 11, count 2 2006.239.08:05:20.50#ibcon#enter sib2, iclass 11, count 2 2006.239.08:05:20.50#ibcon#flushed, iclass 11, count 2 2006.239.08:05:20.50#ibcon#about to write, iclass 11, count 2 2006.239.08:05:20.50#ibcon#wrote, iclass 11, count 2 2006.239.08:05:20.50#ibcon#about to read 3, iclass 11, count 2 2006.239.08:05:20.52#ibcon#read 3, iclass 11, count 2 2006.239.08:05:20.52#ibcon#about to read 4, iclass 11, count 2 2006.239.08:05:20.52#ibcon#read 4, iclass 11, count 2 2006.239.08:05:20.52#ibcon#about to read 5, iclass 11, count 2 2006.239.08:05:20.52#ibcon#read 5, iclass 11, count 2 2006.239.08:05:20.52#ibcon#about to read 6, iclass 11, count 2 2006.239.08:05:20.52#ibcon#read 6, iclass 11, count 2 2006.239.08:05:20.52#ibcon#end of sib2, iclass 11, count 2 2006.239.08:05:20.52#ibcon#*mode == 0, iclass 11, count 2 2006.239.08:05:20.52#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.08:05:20.52#ibcon#[25=AT08-07\r\n] 2006.239.08:05:20.52#ibcon#*before write, iclass 11, count 2 2006.239.08:05:20.52#ibcon#enter sib2, iclass 11, count 2 2006.239.08:05:20.52#ibcon#flushed, iclass 11, count 2 2006.239.08:05:20.52#ibcon#about to write, iclass 11, count 2 2006.239.08:05:20.52#ibcon#wrote, iclass 11, count 2 2006.239.08:05:20.52#ibcon#about to read 3, iclass 11, count 2 2006.239.08:05:20.55#ibcon#read 3, iclass 11, count 2 2006.239.08:05:20.55#ibcon#about to read 4, iclass 11, count 2 2006.239.08:05:20.55#ibcon#read 4, iclass 11, count 2 2006.239.08:05:20.55#ibcon#about to read 5, iclass 11, count 2 2006.239.08:05:20.55#ibcon#read 5, iclass 11, count 2 2006.239.08:05:20.55#ibcon#about to read 6, iclass 11, count 2 2006.239.08:05:20.55#ibcon#read 6, iclass 11, count 2 2006.239.08:05:20.55#ibcon#end of sib2, iclass 11, count 2 2006.239.08:05:20.55#ibcon#*after write, iclass 11, count 2 2006.239.08:05:20.55#ibcon#*before return 0, iclass 11, count 2 2006.239.08:05:20.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:05:20.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:05:20.55#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.08:05:20.55#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:20.55#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:05:20.67#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:05:20.67#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:05:20.67#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:05:20.67#ibcon#first serial, iclass 11, count 0 2006.239.08:05:20.67#ibcon#enter sib2, iclass 11, count 0 2006.239.08:05:20.67#ibcon#flushed, iclass 11, count 0 2006.239.08:05:20.67#ibcon#about to write, iclass 11, count 0 2006.239.08:05:20.67#ibcon#wrote, iclass 11, count 0 2006.239.08:05:20.67#ibcon#about to read 3, iclass 11, count 0 2006.239.08:05:20.69#ibcon#read 3, iclass 11, count 0 2006.239.08:05:20.69#ibcon#about to read 4, iclass 11, count 0 2006.239.08:05:20.69#ibcon#read 4, iclass 11, count 0 2006.239.08:05:20.69#ibcon#about to read 5, iclass 11, count 0 2006.239.08:05:20.69#ibcon#read 5, iclass 11, count 0 2006.239.08:05:20.69#ibcon#about to read 6, iclass 11, count 0 2006.239.08:05:20.69#ibcon#read 6, iclass 11, count 0 2006.239.08:05:20.69#ibcon#end of sib2, iclass 11, count 0 2006.239.08:05:20.69#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:05:20.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:05:20.69#ibcon#[25=USB\r\n] 2006.239.08:05:20.69#ibcon#*before write, iclass 11, count 0 2006.239.08:05:20.69#ibcon#enter sib2, iclass 11, count 0 2006.239.08:05:20.69#ibcon#flushed, iclass 11, count 0 2006.239.08:05:20.69#ibcon#about to write, iclass 11, count 0 2006.239.08:05:20.69#ibcon#wrote, iclass 11, count 0 2006.239.08:05:20.69#ibcon#about to read 3, iclass 11, count 0 2006.239.08:05:20.72#ibcon#read 3, iclass 11, count 0 2006.239.08:05:20.72#ibcon#about to read 4, iclass 11, count 0 2006.239.08:05:20.72#ibcon#read 4, iclass 11, count 0 2006.239.08:05:20.72#ibcon#about to read 5, iclass 11, count 0 2006.239.08:05:20.72#ibcon#read 5, iclass 11, count 0 2006.239.08:05:20.72#ibcon#about to read 6, iclass 11, count 0 2006.239.08:05:20.72#ibcon#read 6, iclass 11, count 0 2006.239.08:05:20.72#ibcon#end of sib2, iclass 11, count 0 2006.239.08:05:20.72#ibcon#*after write, iclass 11, count 0 2006.239.08:05:20.72#ibcon#*before return 0, iclass 11, count 0 2006.239.08:05:20.72#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:05:20.72#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:05:20.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:05:20.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:05:20.72$vc4f8/vblo=1,632.99 2006.239.08:05:20.72#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.08:05:20.72#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.08:05:20.72#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:20.72#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:20.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:20.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:20.72#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:05:20.72#ibcon#first serial, iclass 13, count 0 2006.239.08:05:20.72#ibcon#enter sib2, iclass 13, count 0 2006.239.08:05:20.72#ibcon#flushed, iclass 13, count 0 2006.239.08:05:20.72#ibcon#about to write, iclass 13, count 0 2006.239.08:05:20.72#ibcon#wrote, iclass 13, count 0 2006.239.08:05:20.72#ibcon#about to read 3, iclass 13, count 0 2006.239.08:05:20.74#ibcon#read 3, iclass 13, count 0 2006.239.08:05:20.74#ibcon#about to read 4, iclass 13, count 0 2006.239.08:05:20.74#ibcon#read 4, iclass 13, count 0 2006.239.08:05:20.74#ibcon#about to read 5, iclass 13, count 0 2006.239.08:05:20.74#ibcon#read 5, iclass 13, count 0 2006.239.08:05:20.74#ibcon#about to read 6, iclass 13, count 0 2006.239.08:05:20.74#ibcon#read 6, iclass 13, count 0 2006.239.08:05:20.74#ibcon#end of sib2, iclass 13, count 0 2006.239.08:05:20.74#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:05:20.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:05:20.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:05:20.74#ibcon#*before write, iclass 13, count 0 2006.239.08:05:20.74#ibcon#enter sib2, iclass 13, count 0 2006.239.08:05:20.74#ibcon#flushed, iclass 13, count 0 2006.239.08:05:20.74#ibcon#about to write, iclass 13, count 0 2006.239.08:05:20.74#ibcon#wrote, iclass 13, count 0 2006.239.08:05:20.74#ibcon#about to read 3, iclass 13, count 0 2006.239.08:05:20.78#ibcon#read 3, iclass 13, count 0 2006.239.08:05:20.78#ibcon#about to read 4, iclass 13, count 0 2006.239.08:05:20.78#ibcon#read 4, iclass 13, count 0 2006.239.08:05:20.78#ibcon#about to read 5, iclass 13, count 0 2006.239.08:05:20.78#ibcon#read 5, iclass 13, count 0 2006.239.08:05:20.78#ibcon#about to read 6, iclass 13, count 0 2006.239.08:05:20.78#ibcon#read 6, iclass 13, count 0 2006.239.08:05:20.78#ibcon#end of sib2, iclass 13, count 0 2006.239.08:05:20.78#ibcon#*after write, iclass 13, count 0 2006.239.08:05:20.78#ibcon#*before return 0, iclass 13, count 0 2006.239.08:05:20.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:20.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:05:20.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:05:20.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:05:20.78$vc4f8/vb=1,4 2006.239.08:05:20.78#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.08:05:20.78#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.08:05:20.78#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:20.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:20.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:20.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:20.78#ibcon#enter wrdev, iclass 15, count 2 2006.239.08:05:20.78#ibcon#first serial, iclass 15, count 2 2006.239.08:05:20.78#ibcon#enter sib2, iclass 15, count 2 2006.239.08:05:20.78#ibcon#flushed, iclass 15, count 2 2006.239.08:05:20.78#ibcon#about to write, iclass 15, count 2 2006.239.08:05:20.78#ibcon#wrote, iclass 15, count 2 2006.239.08:05:20.78#ibcon#about to read 3, iclass 15, count 2 2006.239.08:05:20.80#ibcon#read 3, iclass 15, count 2 2006.239.08:05:20.80#ibcon#about to read 4, iclass 15, count 2 2006.239.08:05:20.80#ibcon#read 4, iclass 15, count 2 2006.239.08:05:20.80#ibcon#about to read 5, iclass 15, count 2 2006.239.08:05:20.80#ibcon#read 5, iclass 15, count 2 2006.239.08:05:20.80#ibcon#about to read 6, iclass 15, count 2 2006.239.08:05:20.80#ibcon#read 6, iclass 15, count 2 2006.239.08:05:20.80#ibcon#end of sib2, iclass 15, count 2 2006.239.08:05:20.80#ibcon#*mode == 0, iclass 15, count 2 2006.239.08:05:20.80#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.08:05:20.80#ibcon#[27=AT01-04\r\n] 2006.239.08:05:20.80#ibcon#*before write, iclass 15, count 2 2006.239.08:05:20.80#ibcon#enter sib2, iclass 15, count 2 2006.239.08:05:20.80#ibcon#flushed, iclass 15, count 2 2006.239.08:05:20.80#ibcon#about to write, iclass 15, count 2 2006.239.08:05:20.80#ibcon#wrote, iclass 15, count 2 2006.239.08:05:20.80#ibcon#about to read 3, iclass 15, count 2 2006.239.08:05:20.83#ibcon#read 3, iclass 15, count 2 2006.239.08:05:20.83#ibcon#about to read 4, iclass 15, count 2 2006.239.08:05:20.83#ibcon#read 4, iclass 15, count 2 2006.239.08:05:20.83#ibcon#about to read 5, iclass 15, count 2 2006.239.08:05:20.83#ibcon#read 5, iclass 15, count 2 2006.239.08:05:20.83#ibcon#about to read 6, iclass 15, count 2 2006.239.08:05:20.83#ibcon#read 6, iclass 15, count 2 2006.239.08:05:20.83#ibcon#end of sib2, iclass 15, count 2 2006.239.08:05:20.83#ibcon#*after write, iclass 15, count 2 2006.239.08:05:20.83#ibcon#*before return 0, iclass 15, count 2 2006.239.08:05:20.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:20.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:05:20.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.08:05:20.83#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:20.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:20.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:20.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:20.95#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:05:20.95#ibcon#first serial, iclass 15, count 0 2006.239.08:05:20.95#ibcon#enter sib2, iclass 15, count 0 2006.239.08:05:20.95#ibcon#flushed, iclass 15, count 0 2006.239.08:05:20.95#ibcon#about to write, iclass 15, count 0 2006.239.08:05:20.95#ibcon#wrote, iclass 15, count 0 2006.239.08:05:20.95#ibcon#about to read 3, iclass 15, count 0 2006.239.08:05:20.97#ibcon#read 3, iclass 15, count 0 2006.239.08:05:20.97#ibcon#about to read 4, iclass 15, count 0 2006.239.08:05:20.97#ibcon#read 4, iclass 15, count 0 2006.239.08:05:20.97#ibcon#about to read 5, iclass 15, count 0 2006.239.08:05:20.97#ibcon#read 5, iclass 15, count 0 2006.239.08:05:20.97#ibcon#about to read 6, iclass 15, count 0 2006.239.08:05:20.97#ibcon#read 6, iclass 15, count 0 2006.239.08:05:20.97#ibcon#end of sib2, iclass 15, count 0 2006.239.08:05:20.97#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:05:20.97#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:05:20.97#ibcon#[27=USB\r\n] 2006.239.08:05:20.97#ibcon#*before write, iclass 15, count 0 2006.239.08:05:20.97#ibcon#enter sib2, iclass 15, count 0 2006.239.08:05:20.97#ibcon#flushed, iclass 15, count 0 2006.239.08:05:20.97#ibcon#about to write, iclass 15, count 0 2006.239.08:05:20.97#ibcon#wrote, iclass 15, count 0 2006.239.08:05:20.97#ibcon#about to read 3, iclass 15, count 0 2006.239.08:05:21.00#ibcon#read 3, iclass 15, count 0 2006.239.08:05:21.00#ibcon#about to read 4, iclass 15, count 0 2006.239.08:05:21.00#ibcon#read 4, iclass 15, count 0 2006.239.08:05:21.00#ibcon#about to read 5, iclass 15, count 0 2006.239.08:05:21.00#ibcon#read 5, iclass 15, count 0 2006.239.08:05:21.00#ibcon#about to read 6, iclass 15, count 0 2006.239.08:05:21.00#ibcon#read 6, iclass 15, count 0 2006.239.08:05:21.00#ibcon#end of sib2, iclass 15, count 0 2006.239.08:05:21.00#ibcon#*after write, iclass 15, count 0 2006.239.08:05:21.00#ibcon#*before return 0, iclass 15, count 0 2006.239.08:05:21.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:21.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:05:21.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:05:21.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:05:21.00$vc4f8/vblo=2,640.99 2006.239.08:05:21.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.08:05:21.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.08:05:21.00#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:21.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:21.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:21.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:21.00#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:05:21.00#ibcon#first serial, iclass 17, count 0 2006.239.08:05:21.00#ibcon#enter sib2, iclass 17, count 0 2006.239.08:05:21.00#ibcon#flushed, iclass 17, count 0 2006.239.08:05:21.00#ibcon#about to write, iclass 17, count 0 2006.239.08:05:21.00#ibcon#wrote, iclass 17, count 0 2006.239.08:05:21.00#ibcon#about to read 3, iclass 17, count 0 2006.239.08:05:21.02#ibcon#read 3, iclass 17, count 0 2006.239.08:05:21.02#ibcon#about to read 4, iclass 17, count 0 2006.239.08:05:21.02#ibcon#read 4, iclass 17, count 0 2006.239.08:05:21.02#ibcon#about to read 5, iclass 17, count 0 2006.239.08:05:21.02#ibcon#read 5, iclass 17, count 0 2006.239.08:05:21.02#ibcon#about to read 6, iclass 17, count 0 2006.239.08:05:21.02#ibcon#read 6, iclass 17, count 0 2006.239.08:05:21.02#ibcon#end of sib2, iclass 17, count 0 2006.239.08:05:21.02#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:05:21.02#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:05:21.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:05:21.02#ibcon#*before write, iclass 17, count 0 2006.239.08:05:21.02#ibcon#enter sib2, iclass 17, count 0 2006.239.08:05:21.02#ibcon#flushed, iclass 17, count 0 2006.239.08:05:21.02#ibcon#about to write, iclass 17, count 0 2006.239.08:05:21.02#ibcon#wrote, iclass 17, count 0 2006.239.08:05:21.02#ibcon#about to read 3, iclass 17, count 0 2006.239.08:05:21.06#ibcon#read 3, iclass 17, count 0 2006.239.08:05:21.06#ibcon#about to read 4, iclass 17, count 0 2006.239.08:05:21.06#ibcon#read 4, iclass 17, count 0 2006.239.08:05:21.06#ibcon#about to read 5, iclass 17, count 0 2006.239.08:05:21.06#ibcon#read 5, iclass 17, count 0 2006.239.08:05:21.06#ibcon#about to read 6, iclass 17, count 0 2006.239.08:05:21.06#ibcon#read 6, iclass 17, count 0 2006.239.08:05:21.06#ibcon#end of sib2, iclass 17, count 0 2006.239.08:05:21.06#ibcon#*after write, iclass 17, count 0 2006.239.08:05:21.06#ibcon#*before return 0, iclass 17, count 0 2006.239.08:05:21.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:21.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:05:21.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:05:21.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:05:21.06$vc4f8/vb=2,4 2006.239.08:05:21.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.08:05:21.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.08:05:21.06#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:21.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:21.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:21.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:21.12#ibcon#enter wrdev, iclass 19, count 2 2006.239.08:05:21.12#ibcon#first serial, iclass 19, count 2 2006.239.08:05:21.12#ibcon#enter sib2, iclass 19, count 2 2006.239.08:05:21.12#ibcon#flushed, iclass 19, count 2 2006.239.08:05:21.12#ibcon#about to write, iclass 19, count 2 2006.239.08:05:21.12#ibcon#wrote, iclass 19, count 2 2006.239.08:05:21.12#ibcon#about to read 3, iclass 19, count 2 2006.239.08:05:21.14#ibcon#read 3, iclass 19, count 2 2006.239.08:05:21.14#ibcon#about to read 4, iclass 19, count 2 2006.239.08:05:21.14#ibcon#read 4, iclass 19, count 2 2006.239.08:05:21.14#ibcon#about to read 5, iclass 19, count 2 2006.239.08:05:21.14#ibcon#read 5, iclass 19, count 2 2006.239.08:05:21.14#ibcon#about to read 6, iclass 19, count 2 2006.239.08:05:21.14#ibcon#read 6, iclass 19, count 2 2006.239.08:05:21.14#ibcon#end of sib2, iclass 19, count 2 2006.239.08:05:21.14#ibcon#*mode == 0, iclass 19, count 2 2006.239.08:05:21.14#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.08:05:21.14#ibcon#[27=AT02-04\r\n] 2006.239.08:05:21.14#ibcon#*before write, iclass 19, count 2 2006.239.08:05:21.14#ibcon#enter sib2, iclass 19, count 2 2006.239.08:05:21.14#ibcon#flushed, iclass 19, count 2 2006.239.08:05:21.14#ibcon#about to write, iclass 19, count 2 2006.239.08:05:21.14#ibcon#wrote, iclass 19, count 2 2006.239.08:05:21.14#ibcon#about to read 3, iclass 19, count 2 2006.239.08:05:21.17#ibcon#read 3, iclass 19, count 2 2006.239.08:05:21.17#ibcon#about to read 4, iclass 19, count 2 2006.239.08:05:21.17#ibcon#read 4, iclass 19, count 2 2006.239.08:05:21.17#ibcon#about to read 5, iclass 19, count 2 2006.239.08:05:21.17#ibcon#read 5, iclass 19, count 2 2006.239.08:05:21.17#ibcon#about to read 6, iclass 19, count 2 2006.239.08:05:21.17#ibcon#read 6, iclass 19, count 2 2006.239.08:05:21.17#ibcon#end of sib2, iclass 19, count 2 2006.239.08:05:21.17#ibcon#*after write, iclass 19, count 2 2006.239.08:05:21.17#ibcon#*before return 0, iclass 19, count 2 2006.239.08:05:21.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:21.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:05:21.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.08:05:21.17#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:21.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:21.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:21.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:21.29#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:05:21.29#ibcon#first serial, iclass 19, count 0 2006.239.08:05:21.29#ibcon#enter sib2, iclass 19, count 0 2006.239.08:05:21.29#ibcon#flushed, iclass 19, count 0 2006.239.08:05:21.29#ibcon#about to write, iclass 19, count 0 2006.239.08:05:21.29#ibcon#wrote, iclass 19, count 0 2006.239.08:05:21.29#ibcon#about to read 3, iclass 19, count 0 2006.239.08:05:21.31#ibcon#read 3, iclass 19, count 0 2006.239.08:05:21.31#ibcon#about to read 4, iclass 19, count 0 2006.239.08:05:21.31#ibcon#read 4, iclass 19, count 0 2006.239.08:05:21.31#ibcon#about to read 5, iclass 19, count 0 2006.239.08:05:21.31#ibcon#read 5, iclass 19, count 0 2006.239.08:05:21.31#ibcon#about to read 6, iclass 19, count 0 2006.239.08:05:21.31#ibcon#read 6, iclass 19, count 0 2006.239.08:05:21.31#ibcon#end of sib2, iclass 19, count 0 2006.239.08:05:21.31#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:05:21.31#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:05:21.31#ibcon#[27=USB\r\n] 2006.239.08:05:21.31#ibcon#*before write, iclass 19, count 0 2006.239.08:05:21.31#ibcon#enter sib2, iclass 19, count 0 2006.239.08:05:21.31#ibcon#flushed, iclass 19, count 0 2006.239.08:05:21.31#ibcon#about to write, iclass 19, count 0 2006.239.08:05:21.31#ibcon#wrote, iclass 19, count 0 2006.239.08:05:21.31#ibcon#about to read 3, iclass 19, count 0 2006.239.08:05:21.34#ibcon#read 3, iclass 19, count 0 2006.239.08:05:21.34#ibcon#about to read 4, iclass 19, count 0 2006.239.08:05:21.34#ibcon#read 4, iclass 19, count 0 2006.239.08:05:21.34#ibcon#about to read 5, iclass 19, count 0 2006.239.08:05:21.34#ibcon#read 5, iclass 19, count 0 2006.239.08:05:21.34#ibcon#about to read 6, iclass 19, count 0 2006.239.08:05:21.34#ibcon#read 6, iclass 19, count 0 2006.239.08:05:21.34#ibcon#end of sib2, iclass 19, count 0 2006.239.08:05:21.34#ibcon#*after write, iclass 19, count 0 2006.239.08:05:21.34#ibcon#*before return 0, iclass 19, count 0 2006.239.08:05:21.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:21.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:05:21.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:05:21.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:05:21.34$vc4f8/vblo=3,656.99 2006.239.08:05:21.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:05:21.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:05:21.34#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:21.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:21.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:21.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:21.34#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:05:21.34#ibcon#first serial, iclass 21, count 0 2006.239.08:05:21.34#ibcon#enter sib2, iclass 21, count 0 2006.239.08:05:21.34#ibcon#flushed, iclass 21, count 0 2006.239.08:05:21.34#ibcon#about to write, iclass 21, count 0 2006.239.08:05:21.34#ibcon#wrote, iclass 21, count 0 2006.239.08:05:21.34#ibcon#about to read 3, iclass 21, count 0 2006.239.08:05:21.36#ibcon#read 3, iclass 21, count 0 2006.239.08:05:21.36#ibcon#about to read 4, iclass 21, count 0 2006.239.08:05:21.36#ibcon#read 4, iclass 21, count 0 2006.239.08:05:21.36#ibcon#about to read 5, iclass 21, count 0 2006.239.08:05:21.36#ibcon#read 5, iclass 21, count 0 2006.239.08:05:21.36#ibcon#about to read 6, iclass 21, count 0 2006.239.08:05:21.36#ibcon#read 6, iclass 21, count 0 2006.239.08:05:21.36#ibcon#end of sib2, iclass 21, count 0 2006.239.08:05:21.36#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:05:21.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:05:21.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:05:21.36#ibcon#*before write, iclass 21, count 0 2006.239.08:05:21.36#ibcon#enter sib2, iclass 21, count 0 2006.239.08:05:21.36#ibcon#flushed, iclass 21, count 0 2006.239.08:05:21.36#ibcon#about to write, iclass 21, count 0 2006.239.08:05:21.36#ibcon#wrote, iclass 21, count 0 2006.239.08:05:21.36#ibcon#about to read 3, iclass 21, count 0 2006.239.08:05:21.40#ibcon#read 3, iclass 21, count 0 2006.239.08:05:21.40#ibcon#about to read 4, iclass 21, count 0 2006.239.08:05:21.40#ibcon#read 4, iclass 21, count 0 2006.239.08:05:21.40#ibcon#about to read 5, iclass 21, count 0 2006.239.08:05:21.40#ibcon#read 5, iclass 21, count 0 2006.239.08:05:21.40#ibcon#about to read 6, iclass 21, count 0 2006.239.08:05:21.40#ibcon#read 6, iclass 21, count 0 2006.239.08:05:21.40#ibcon#end of sib2, iclass 21, count 0 2006.239.08:05:21.40#ibcon#*after write, iclass 21, count 0 2006.239.08:05:21.40#ibcon#*before return 0, iclass 21, count 0 2006.239.08:05:21.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:21.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:05:21.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:05:21.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:05:21.40$vc4f8/vb=3,4 2006.239.08:05:21.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.08:05:21.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.08:05:21.40#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:21.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:21.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:21.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:21.46#ibcon#enter wrdev, iclass 23, count 2 2006.239.08:05:21.46#ibcon#first serial, iclass 23, count 2 2006.239.08:05:21.46#ibcon#enter sib2, iclass 23, count 2 2006.239.08:05:21.46#ibcon#flushed, iclass 23, count 2 2006.239.08:05:21.46#ibcon#about to write, iclass 23, count 2 2006.239.08:05:21.46#ibcon#wrote, iclass 23, count 2 2006.239.08:05:21.46#ibcon#about to read 3, iclass 23, count 2 2006.239.08:05:21.48#ibcon#read 3, iclass 23, count 2 2006.239.08:05:21.48#ibcon#about to read 4, iclass 23, count 2 2006.239.08:05:21.48#ibcon#read 4, iclass 23, count 2 2006.239.08:05:21.48#ibcon#about to read 5, iclass 23, count 2 2006.239.08:05:21.48#ibcon#read 5, iclass 23, count 2 2006.239.08:05:21.48#ibcon#about to read 6, iclass 23, count 2 2006.239.08:05:21.48#ibcon#read 6, iclass 23, count 2 2006.239.08:05:21.48#ibcon#end of sib2, iclass 23, count 2 2006.239.08:05:21.48#ibcon#*mode == 0, iclass 23, count 2 2006.239.08:05:21.48#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.08:05:21.48#ibcon#[27=AT03-04\r\n] 2006.239.08:05:21.48#ibcon#*before write, iclass 23, count 2 2006.239.08:05:21.48#ibcon#enter sib2, iclass 23, count 2 2006.239.08:05:21.48#ibcon#flushed, iclass 23, count 2 2006.239.08:05:21.48#ibcon#about to write, iclass 23, count 2 2006.239.08:05:21.48#ibcon#wrote, iclass 23, count 2 2006.239.08:05:21.48#ibcon#about to read 3, iclass 23, count 2 2006.239.08:05:21.51#ibcon#read 3, iclass 23, count 2 2006.239.08:05:21.51#ibcon#about to read 4, iclass 23, count 2 2006.239.08:05:21.51#ibcon#read 4, iclass 23, count 2 2006.239.08:05:21.51#ibcon#about to read 5, iclass 23, count 2 2006.239.08:05:21.51#ibcon#read 5, iclass 23, count 2 2006.239.08:05:21.51#ibcon#about to read 6, iclass 23, count 2 2006.239.08:05:21.51#ibcon#read 6, iclass 23, count 2 2006.239.08:05:21.51#ibcon#end of sib2, iclass 23, count 2 2006.239.08:05:21.51#ibcon#*after write, iclass 23, count 2 2006.239.08:05:21.51#ibcon#*before return 0, iclass 23, count 2 2006.239.08:05:21.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:21.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:05:21.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.08:05:21.51#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:21.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:21.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:21.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:21.63#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:05:21.63#ibcon#first serial, iclass 23, count 0 2006.239.08:05:21.63#ibcon#enter sib2, iclass 23, count 0 2006.239.08:05:21.63#ibcon#flushed, iclass 23, count 0 2006.239.08:05:21.63#ibcon#about to write, iclass 23, count 0 2006.239.08:05:21.63#ibcon#wrote, iclass 23, count 0 2006.239.08:05:21.63#ibcon#about to read 3, iclass 23, count 0 2006.239.08:05:21.65#ibcon#read 3, iclass 23, count 0 2006.239.08:05:21.65#ibcon#about to read 4, iclass 23, count 0 2006.239.08:05:21.65#ibcon#read 4, iclass 23, count 0 2006.239.08:05:21.65#ibcon#about to read 5, iclass 23, count 0 2006.239.08:05:21.65#ibcon#read 5, iclass 23, count 0 2006.239.08:05:21.65#ibcon#about to read 6, iclass 23, count 0 2006.239.08:05:21.65#ibcon#read 6, iclass 23, count 0 2006.239.08:05:21.65#ibcon#end of sib2, iclass 23, count 0 2006.239.08:05:21.65#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:05:21.65#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:05:21.65#ibcon#[27=USB\r\n] 2006.239.08:05:21.65#ibcon#*before write, iclass 23, count 0 2006.239.08:05:21.65#ibcon#enter sib2, iclass 23, count 0 2006.239.08:05:21.65#ibcon#flushed, iclass 23, count 0 2006.239.08:05:21.65#ibcon#about to write, iclass 23, count 0 2006.239.08:05:21.65#ibcon#wrote, iclass 23, count 0 2006.239.08:05:21.65#ibcon#about to read 3, iclass 23, count 0 2006.239.08:05:21.68#ibcon#read 3, iclass 23, count 0 2006.239.08:05:21.68#ibcon#about to read 4, iclass 23, count 0 2006.239.08:05:21.68#ibcon#read 4, iclass 23, count 0 2006.239.08:05:21.68#ibcon#about to read 5, iclass 23, count 0 2006.239.08:05:21.68#ibcon#read 5, iclass 23, count 0 2006.239.08:05:21.68#ibcon#about to read 6, iclass 23, count 0 2006.239.08:05:21.68#ibcon#read 6, iclass 23, count 0 2006.239.08:05:21.68#ibcon#end of sib2, iclass 23, count 0 2006.239.08:05:21.68#ibcon#*after write, iclass 23, count 0 2006.239.08:05:21.68#ibcon#*before return 0, iclass 23, count 0 2006.239.08:05:21.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:21.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:05:21.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:05:21.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:05:21.68$vc4f8/vblo=4,712.99 2006.239.08:05:21.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.08:05:21.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.08:05:21.68#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:21.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:05:21.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:05:21.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:05:21.68#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:05:21.68#ibcon#first serial, iclass 25, count 0 2006.239.08:05:21.68#ibcon#enter sib2, iclass 25, count 0 2006.239.08:05:21.68#ibcon#flushed, iclass 25, count 0 2006.239.08:05:21.68#ibcon#about to write, iclass 25, count 0 2006.239.08:05:21.68#ibcon#wrote, iclass 25, count 0 2006.239.08:05:21.68#ibcon#about to read 3, iclass 25, count 0 2006.239.08:05:21.70#ibcon#read 3, iclass 25, count 0 2006.239.08:05:21.70#ibcon#about to read 4, iclass 25, count 0 2006.239.08:05:21.70#ibcon#read 4, iclass 25, count 0 2006.239.08:05:21.70#ibcon#about to read 5, iclass 25, count 0 2006.239.08:05:21.70#ibcon#read 5, iclass 25, count 0 2006.239.08:05:21.70#ibcon#about to read 6, iclass 25, count 0 2006.239.08:05:21.70#ibcon#read 6, iclass 25, count 0 2006.239.08:05:21.70#ibcon#end of sib2, iclass 25, count 0 2006.239.08:05:21.70#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:05:21.70#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:05:21.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:05:21.70#ibcon#*before write, iclass 25, count 0 2006.239.08:05:21.70#ibcon#enter sib2, iclass 25, count 0 2006.239.08:05:21.70#ibcon#flushed, iclass 25, count 0 2006.239.08:05:21.70#ibcon#about to write, iclass 25, count 0 2006.239.08:05:21.70#ibcon#wrote, iclass 25, count 0 2006.239.08:05:21.70#ibcon#about to read 3, iclass 25, count 0 2006.239.08:05:21.74#ibcon#read 3, iclass 25, count 0 2006.239.08:05:21.74#ibcon#about to read 4, iclass 25, count 0 2006.239.08:05:21.74#ibcon#read 4, iclass 25, count 0 2006.239.08:05:21.74#ibcon#about to read 5, iclass 25, count 0 2006.239.08:05:21.74#ibcon#read 5, iclass 25, count 0 2006.239.08:05:21.74#ibcon#about to read 6, iclass 25, count 0 2006.239.08:05:21.74#ibcon#read 6, iclass 25, count 0 2006.239.08:05:21.74#ibcon#end of sib2, iclass 25, count 0 2006.239.08:05:21.74#ibcon#*after write, iclass 25, count 0 2006.239.08:05:21.74#ibcon#*before return 0, iclass 25, count 0 2006.239.08:05:21.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:05:21.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:05:21.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:05:21.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:05:21.74$vc4f8/vb=4,4 2006.239.08:05:21.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.08:05:21.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.08:05:21.74#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:21.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:05:21.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:05:21.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:05:21.80#ibcon#enter wrdev, iclass 27, count 2 2006.239.08:05:21.80#ibcon#first serial, iclass 27, count 2 2006.239.08:05:21.80#ibcon#enter sib2, iclass 27, count 2 2006.239.08:05:21.80#ibcon#flushed, iclass 27, count 2 2006.239.08:05:21.80#ibcon#about to write, iclass 27, count 2 2006.239.08:05:21.80#ibcon#wrote, iclass 27, count 2 2006.239.08:05:21.80#ibcon#about to read 3, iclass 27, count 2 2006.239.08:05:21.82#ibcon#read 3, iclass 27, count 2 2006.239.08:05:21.82#ibcon#about to read 4, iclass 27, count 2 2006.239.08:05:21.82#ibcon#read 4, iclass 27, count 2 2006.239.08:05:21.82#ibcon#about to read 5, iclass 27, count 2 2006.239.08:05:21.82#ibcon#read 5, iclass 27, count 2 2006.239.08:05:21.82#ibcon#about to read 6, iclass 27, count 2 2006.239.08:05:21.82#ibcon#read 6, iclass 27, count 2 2006.239.08:05:21.82#ibcon#end of sib2, iclass 27, count 2 2006.239.08:05:21.82#ibcon#*mode == 0, iclass 27, count 2 2006.239.08:05:21.82#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.08:05:21.82#ibcon#[27=AT04-04\r\n] 2006.239.08:05:21.82#ibcon#*before write, iclass 27, count 2 2006.239.08:05:21.82#ibcon#enter sib2, iclass 27, count 2 2006.239.08:05:21.82#ibcon#flushed, iclass 27, count 2 2006.239.08:05:21.82#ibcon#about to write, iclass 27, count 2 2006.239.08:05:21.82#ibcon#wrote, iclass 27, count 2 2006.239.08:05:21.82#ibcon#about to read 3, iclass 27, count 2 2006.239.08:05:21.85#ibcon#read 3, iclass 27, count 2 2006.239.08:05:21.85#ibcon#about to read 4, iclass 27, count 2 2006.239.08:05:21.85#ibcon#read 4, iclass 27, count 2 2006.239.08:05:21.85#ibcon#about to read 5, iclass 27, count 2 2006.239.08:05:21.85#ibcon#read 5, iclass 27, count 2 2006.239.08:05:21.85#ibcon#about to read 6, iclass 27, count 2 2006.239.08:05:21.85#ibcon#read 6, iclass 27, count 2 2006.239.08:05:21.85#ibcon#end of sib2, iclass 27, count 2 2006.239.08:05:21.85#ibcon#*after write, iclass 27, count 2 2006.239.08:05:21.85#ibcon#*before return 0, iclass 27, count 2 2006.239.08:05:21.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:05:21.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:05:21.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.08:05:21.85#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:21.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:05:21.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:05:21.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:05:21.97#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:05:21.97#ibcon#first serial, iclass 27, count 0 2006.239.08:05:21.97#ibcon#enter sib2, iclass 27, count 0 2006.239.08:05:21.97#ibcon#flushed, iclass 27, count 0 2006.239.08:05:21.97#ibcon#about to write, iclass 27, count 0 2006.239.08:05:21.97#ibcon#wrote, iclass 27, count 0 2006.239.08:05:21.97#ibcon#about to read 3, iclass 27, count 0 2006.239.08:05:21.99#ibcon#read 3, iclass 27, count 0 2006.239.08:05:21.99#ibcon#about to read 4, iclass 27, count 0 2006.239.08:05:21.99#ibcon#read 4, iclass 27, count 0 2006.239.08:05:21.99#ibcon#about to read 5, iclass 27, count 0 2006.239.08:05:21.99#ibcon#read 5, iclass 27, count 0 2006.239.08:05:21.99#ibcon#about to read 6, iclass 27, count 0 2006.239.08:05:21.99#ibcon#read 6, iclass 27, count 0 2006.239.08:05:21.99#ibcon#end of sib2, iclass 27, count 0 2006.239.08:05:21.99#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:05:21.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:05:21.99#ibcon#[27=USB\r\n] 2006.239.08:05:21.99#ibcon#*before write, iclass 27, count 0 2006.239.08:05:21.99#ibcon#enter sib2, iclass 27, count 0 2006.239.08:05:21.99#ibcon#flushed, iclass 27, count 0 2006.239.08:05:21.99#ibcon#about to write, iclass 27, count 0 2006.239.08:05:21.99#ibcon#wrote, iclass 27, count 0 2006.239.08:05:21.99#ibcon#about to read 3, iclass 27, count 0 2006.239.08:05:22.02#ibcon#read 3, iclass 27, count 0 2006.239.08:05:22.02#ibcon#about to read 4, iclass 27, count 0 2006.239.08:05:22.02#ibcon#read 4, iclass 27, count 0 2006.239.08:05:22.02#ibcon#about to read 5, iclass 27, count 0 2006.239.08:05:22.02#ibcon#read 5, iclass 27, count 0 2006.239.08:05:22.02#ibcon#about to read 6, iclass 27, count 0 2006.239.08:05:22.02#ibcon#read 6, iclass 27, count 0 2006.239.08:05:22.02#ibcon#end of sib2, iclass 27, count 0 2006.239.08:05:22.02#ibcon#*after write, iclass 27, count 0 2006.239.08:05:22.02#ibcon#*before return 0, iclass 27, count 0 2006.239.08:05:22.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:05:22.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:05:22.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:05:22.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:05:22.02$vc4f8/vblo=5,744.99 2006.239.08:05:22.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.08:05:22.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.08:05:22.02#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:22.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:05:22.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:05:22.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:05:22.02#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:05:22.02#ibcon#first serial, iclass 29, count 0 2006.239.08:05:22.02#ibcon#enter sib2, iclass 29, count 0 2006.239.08:05:22.02#ibcon#flushed, iclass 29, count 0 2006.239.08:05:22.02#ibcon#about to write, iclass 29, count 0 2006.239.08:05:22.02#ibcon#wrote, iclass 29, count 0 2006.239.08:05:22.02#ibcon#about to read 3, iclass 29, count 0 2006.239.08:05:22.04#ibcon#read 3, iclass 29, count 0 2006.239.08:05:22.04#ibcon#about to read 4, iclass 29, count 0 2006.239.08:05:22.04#ibcon#read 4, iclass 29, count 0 2006.239.08:05:22.04#ibcon#about to read 5, iclass 29, count 0 2006.239.08:05:22.04#ibcon#read 5, iclass 29, count 0 2006.239.08:05:22.04#ibcon#about to read 6, iclass 29, count 0 2006.239.08:05:22.04#ibcon#read 6, iclass 29, count 0 2006.239.08:05:22.04#ibcon#end of sib2, iclass 29, count 0 2006.239.08:05:22.04#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:05:22.04#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:05:22.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:05:22.04#ibcon#*before write, iclass 29, count 0 2006.239.08:05:22.04#ibcon#enter sib2, iclass 29, count 0 2006.239.08:05:22.04#ibcon#flushed, iclass 29, count 0 2006.239.08:05:22.04#ibcon#about to write, iclass 29, count 0 2006.239.08:05:22.04#ibcon#wrote, iclass 29, count 0 2006.239.08:05:22.04#ibcon#about to read 3, iclass 29, count 0 2006.239.08:05:22.08#ibcon#read 3, iclass 29, count 0 2006.239.08:05:22.08#ibcon#about to read 4, iclass 29, count 0 2006.239.08:05:22.08#ibcon#read 4, iclass 29, count 0 2006.239.08:05:22.08#ibcon#about to read 5, iclass 29, count 0 2006.239.08:05:22.08#ibcon#read 5, iclass 29, count 0 2006.239.08:05:22.08#ibcon#about to read 6, iclass 29, count 0 2006.239.08:05:22.08#ibcon#read 6, iclass 29, count 0 2006.239.08:05:22.08#ibcon#end of sib2, iclass 29, count 0 2006.239.08:05:22.08#ibcon#*after write, iclass 29, count 0 2006.239.08:05:22.08#ibcon#*before return 0, iclass 29, count 0 2006.239.08:05:22.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:05:22.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:05:22.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:05:22.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:05:22.08$vc4f8/vb=5,4 2006.239.08:05:22.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.08:05:22.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.08:05:22.08#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:22.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:22.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:22.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:22.14#ibcon#enter wrdev, iclass 31, count 2 2006.239.08:05:22.14#ibcon#first serial, iclass 31, count 2 2006.239.08:05:22.14#ibcon#enter sib2, iclass 31, count 2 2006.239.08:05:22.14#ibcon#flushed, iclass 31, count 2 2006.239.08:05:22.14#ibcon#about to write, iclass 31, count 2 2006.239.08:05:22.14#ibcon#wrote, iclass 31, count 2 2006.239.08:05:22.14#ibcon#about to read 3, iclass 31, count 2 2006.239.08:05:22.16#ibcon#read 3, iclass 31, count 2 2006.239.08:05:22.16#ibcon#about to read 4, iclass 31, count 2 2006.239.08:05:22.16#ibcon#read 4, iclass 31, count 2 2006.239.08:05:22.16#ibcon#about to read 5, iclass 31, count 2 2006.239.08:05:22.16#ibcon#read 5, iclass 31, count 2 2006.239.08:05:22.16#ibcon#about to read 6, iclass 31, count 2 2006.239.08:05:22.16#ibcon#read 6, iclass 31, count 2 2006.239.08:05:22.16#ibcon#end of sib2, iclass 31, count 2 2006.239.08:05:22.16#ibcon#*mode == 0, iclass 31, count 2 2006.239.08:05:22.16#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.08:05:22.16#ibcon#[27=AT05-04\r\n] 2006.239.08:05:22.16#ibcon#*before write, iclass 31, count 2 2006.239.08:05:22.16#ibcon#enter sib2, iclass 31, count 2 2006.239.08:05:22.16#ibcon#flushed, iclass 31, count 2 2006.239.08:05:22.16#ibcon#about to write, iclass 31, count 2 2006.239.08:05:22.16#ibcon#wrote, iclass 31, count 2 2006.239.08:05:22.16#ibcon#about to read 3, iclass 31, count 2 2006.239.08:05:22.19#ibcon#read 3, iclass 31, count 2 2006.239.08:05:22.19#ibcon#about to read 4, iclass 31, count 2 2006.239.08:05:22.19#ibcon#read 4, iclass 31, count 2 2006.239.08:05:22.19#ibcon#about to read 5, iclass 31, count 2 2006.239.08:05:22.19#ibcon#read 5, iclass 31, count 2 2006.239.08:05:22.19#ibcon#about to read 6, iclass 31, count 2 2006.239.08:05:22.19#ibcon#read 6, iclass 31, count 2 2006.239.08:05:22.19#ibcon#end of sib2, iclass 31, count 2 2006.239.08:05:22.19#ibcon#*after write, iclass 31, count 2 2006.239.08:05:22.19#ibcon#*before return 0, iclass 31, count 2 2006.239.08:05:22.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:22.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:05:22.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.08:05:22.19#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:22.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:22.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:22.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:22.31#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:05:22.31#ibcon#first serial, iclass 31, count 0 2006.239.08:05:22.31#ibcon#enter sib2, iclass 31, count 0 2006.239.08:05:22.31#ibcon#flushed, iclass 31, count 0 2006.239.08:05:22.31#ibcon#about to write, iclass 31, count 0 2006.239.08:05:22.31#ibcon#wrote, iclass 31, count 0 2006.239.08:05:22.31#ibcon#about to read 3, iclass 31, count 0 2006.239.08:05:22.33#ibcon#read 3, iclass 31, count 0 2006.239.08:05:22.33#ibcon#about to read 4, iclass 31, count 0 2006.239.08:05:22.33#ibcon#read 4, iclass 31, count 0 2006.239.08:05:22.33#ibcon#about to read 5, iclass 31, count 0 2006.239.08:05:22.33#ibcon#read 5, iclass 31, count 0 2006.239.08:05:22.33#ibcon#about to read 6, iclass 31, count 0 2006.239.08:05:22.33#ibcon#read 6, iclass 31, count 0 2006.239.08:05:22.33#ibcon#end of sib2, iclass 31, count 0 2006.239.08:05:22.33#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:05:22.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:05:22.33#ibcon#[27=USB\r\n] 2006.239.08:05:22.33#ibcon#*before write, iclass 31, count 0 2006.239.08:05:22.33#ibcon#enter sib2, iclass 31, count 0 2006.239.08:05:22.33#ibcon#flushed, iclass 31, count 0 2006.239.08:05:22.33#ibcon#about to write, iclass 31, count 0 2006.239.08:05:22.33#ibcon#wrote, iclass 31, count 0 2006.239.08:05:22.33#ibcon#about to read 3, iclass 31, count 0 2006.239.08:05:22.36#ibcon#read 3, iclass 31, count 0 2006.239.08:05:22.36#ibcon#about to read 4, iclass 31, count 0 2006.239.08:05:22.36#ibcon#read 4, iclass 31, count 0 2006.239.08:05:22.36#ibcon#about to read 5, iclass 31, count 0 2006.239.08:05:22.36#ibcon#read 5, iclass 31, count 0 2006.239.08:05:22.36#ibcon#about to read 6, iclass 31, count 0 2006.239.08:05:22.36#ibcon#read 6, iclass 31, count 0 2006.239.08:05:22.36#ibcon#end of sib2, iclass 31, count 0 2006.239.08:05:22.36#ibcon#*after write, iclass 31, count 0 2006.239.08:05:22.36#ibcon#*before return 0, iclass 31, count 0 2006.239.08:05:22.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:22.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:05:22.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:05:22.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:05:22.36$vc4f8/vblo=6,752.99 2006.239.08:05:22.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.08:05:22.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.08:05:22.36#ibcon#ireg 17 cls_cnt 0 2006.239.08:05:22.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:22.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:22.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:22.36#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:05:22.36#ibcon#first serial, iclass 33, count 0 2006.239.08:05:22.36#ibcon#enter sib2, iclass 33, count 0 2006.239.08:05:22.36#ibcon#flushed, iclass 33, count 0 2006.239.08:05:22.36#ibcon#about to write, iclass 33, count 0 2006.239.08:05:22.36#ibcon#wrote, iclass 33, count 0 2006.239.08:05:22.36#ibcon#about to read 3, iclass 33, count 0 2006.239.08:05:22.38#ibcon#read 3, iclass 33, count 0 2006.239.08:05:22.38#ibcon#about to read 4, iclass 33, count 0 2006.239.08:05:22.38#ibcon#read 4, iclass 33, count 0 2006.239.08:05:22.38#ibcon#about to read 5, iclass 33, count 0 2006.239.08:05:22.38#ibcon#read 5, iclass 33, count 0 2006.239.08:05:22.38#ibcon#about to read 6, iclass 33, count 0 2006.239.08:05:22.38#ibcon#read 6, iclass 33, count 0 2006.239.08:05:22.38#ibcon#end of sib2, iclass 33, count 0 2006.239.08:05:22.38#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:05:22.38#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:05:22.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:05:22.38#ibcon#*before write, iclass 33, count 0 2006.239.08:05:22.38#ibcon#enter sib2, iclass 33, count 0 2006.239.08:05:22.38#ibcon#flushed, iclass 33, count 0 2006.239.08:05:22.38#ibcon#about to write, iclass 33, count 0 2006.239.08:05:22.38#ibcon#wrote, iclass 33, count 0 2006.239.08:05:22.38#ibcon#about to read 3, iclass 33, count 0 2006.239.08:05:22.42#ibcon#read 3, iclass 33, count 0 2006.239.08:05:22.42#ibcon#about to read 4, iclass 33, count 0 2006.239.08:05:22.42#ibcon#read 4, iclass 33, count 0 2006.239.08:05:22.42#ibcon#about to read 5, iclass 33, count 0 2006.239.08:05:22.42#ibcon#read 5, iclass 33, count 0 2006.239.08:05:22.42#ibcon#about to read 6, iclass 33, count 0 2006.239.08:05:22.42#ibcon#read 6, iclass 33, count 0 2006.239.08:05:22.42#ibcon#end of sib2, iclass 33, count 0 2006.239.08:05:22.42#ibcon#*after write, iclass 33, count 0 2006.239.08:05:22.42#ibcon#*before return 0, iclass 33, count 0 2006.239.08:05:22.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:22.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:05:22.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:05:22.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:05:22.42$vc4f8/vb=6,4 2006.239.08:05:22.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.08:05:22.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.08:05:22.42#ibcon#ireg 11 cls_cnt 2 2006.239.08:05:22.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:22.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:22.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:22.48#ibcon#enter wrdev, iclass 35, count 2 2006.239.08:05:22.48#ibcon#first serial, iclass 35, count 2 2006.239.08:05:22.48#ibcon#enter sib2, iclass 35, count 2 2006.239.08:05:22.48#ibcon#flushed, iclass 35, count 2 2006.239.08:05:22.48#ibcon#about to write, iclass 35, count 2 2006.239.08:05:22.48#ibcon#wrote, iclass 35, count 2 2006.239.08:05:22.48#ibcon#about to read 3, iclass 35, count 2 2006.239.08:05:22.50#ibcon#read 3, iclass 35, count 2 2006.239.08:05:22.50#ibcon#about to read 4, iclass 35, count 2 2006.239.08:05:22.50#ibcon#read 4, iclass 35, count 2 2006.239.08:05:22.50#ibcon#about to read 5, iclass 35, count 2 2006.239.08:05:22.50#ibcon#read 5, iclass 35, count 2 2006.239.08:05:22.50#ibcon#about to read 6, iclass 35, count 2 2006.239.08:05:22.50#ibcon#read 6, iclass 35, count 2 2006.239.08:05:22.50#ibcon#end of sib2, iclass 35, count 2 2006.239.08:05:22.50#ibcon#*mode == 0, iclass 35, count 2 2006.239.08:05:22.50#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.08:05:22.50#ibcon#[27=AT06-04\r\n] 2006.239.08:05:22.50#ibcon#*before write, iclass 35, count 2 2006.239.08:05:22.50#ibcon#enter sib2, iclass 35, count 2 2006.239.08:05:22.50#ibcon#flushed, iclass 35, count 2 2006.239.08:05:22.50#ibcon#about to write, iclass 35, count 2 2006.239.08:05:22.50#ibcon#wrote, iclass 35, count 2 2006.239.08:05:22.50#ibcon#about to read 3, iclass 35, count 2 2006.239.08:05:22.53#ibcon#read 3, iclass 35, count 2 2006.239.08:05:22.53#ibcon#about to read 4, iclass 35, count 2 2006.239.08:05:22.53#ibcon#read 4, iclass 35, count 2 2006.239.08:05:22.53#ibcon#about to read 5, iclass 35, count 2 2006.239.08:05:22.53#ibcon#read 5, iclass 35, count 2 2006.239.08:05:22.53#ibcon#about to read 6, iclass 35, count 2 2006.239.08:05:22.53#ibcon#read 6, iclass 35, count 2 2006.239.08:05:22.53#ibcon#end of sib2, iclass 35, count 2 2006.239.08:05:22.53#ibcon#*after write, iclass 35, count 2 2006.239.08:05:22.53#ibcon#*before return 0, iclass 35, count 2 2006.239.08:05:22.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:22.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:05:22.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.08:05:22.53#ibcon#ireg 7 cls_cnt 0 2006.239.08:05:22.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:22.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:22.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:22.65#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:05:22.65#ibcon#first serial, iclass 35, count 0 2006.239.08:05:22.65#ibcon#enter sib2, iclass 35, count 0 2006.239.08:05:22.65#ibcon#flushed, iclass 35, count 0 2006.239.08:05:22.65#ibcon#about to write, iclass 35, count 0 2006.239.08:05:22.65#ibcon#wrote, iclass 35, count 0 2006.239.08:05:22.65#ibcon#about to read 3, iclass 35, count 0 2006.239.08:05:22.67#ibcon#read 3, iclass 35, count 0 2006.239.08:05:22.67#ibcon#about to read 4, iclass 35, count 0 2006.239.08:05:22.67#ibcon#read 4, iclass 35, count 0 2006.239.08:05:22.67#ibcon#about to read 5, iclass 35, count 0 2006.239.08:05:22.67#ibcon#read 5, iclass 35, count 0 2006.239.08:05:22.67#ibcon#about to read 6, iclass 35, count 0 2006.239.08:05:22.67#ibcon#read 6, iclass 35, count 0 2006.239.08:05:22.67#ibcon#end of sib2, iclass 35, count 0 2006.239.08:05:22.67#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:05:22.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:05:22.67#ibcon#[27=USB\r\n] 2006.239.08:05:22.67#ibcon#*before write, iclass 35, count 0 2006.239.08:05:22.67#ibcon#enter sib2, iclass 35, count 0 2006.239.08:05:22.67#ibcon#flushed, iclass 35, count 0 2006.239.08:05:22.67#ibcon#about to write, iclass 35, count 0 2006.239.08:05:22.67#ibcon#wrote, iclass 35, count 0 2006.239.08:05:22.67#ibcon#about to read 3, iclass 35, count 0 2006.239.08:05:22.70#ibcon#read 3, iclass 35, count 0 2006.239.08:05:22.70#ibcon#about to read 4, iclass 35, count 0 2006.239.08:05:22.70#ibcon#read 4, iclass 35, count 0 2006.239.08:05:22.70#ibcon#about to read 5, iclass 35, count 0 2006.239.08:05:22.70#ibcon#read 5, iclass 35, count 0 2006.239.08:05:22.70#ibcon#about to read 6, iclass 35, count 0 2006.239.08:05:22.70#ibcon#read 6, iclass 35, count 0 2006.239.08:05:22.70#ibcon#end of sib2, iclass 35, count 0 2006.239.08:05:22.70#ibcon#*after write, iclass 35, count 0 2006.239.08:05:22.70#ibcon#*before return 0, iclass 35, count 0 2006.239.08:05:22.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:22.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:05:22.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:05:22.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:05:22.70$vc4f8/vabw=wide 2006.239.08:05:22.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.08:05:22.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.08:05:22.70#ibcon#ireg 8 cls_cnt 0 2006.239.08:05:22.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:22.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:22.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:22.70#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:05:22.70#ibcon#first serial, iclass 37, count 0 2006.239.08:05:22.70#ibcon#enter sib2, iclass 37, count 0 2006.239.08:05:22.70#ibcon#flushed, iclass 37, count 0 2006.239.08:05:22.70#ibcon#about to write, iclass 37, count 0 2006.239.08:05:22.70#ibcon#wrote, iclass 37, count 0 2006.239.08:05:22.70#ibcon#about to read 3, iclass 37, count 0 2006.239.08:05:22.72#ibcon#read 3, iclass 37, count 0 2006.239.08:05:22.72#ibcon#about to read 4, iclass 37, count 0 2006.239.08:05:22.72#ibcon#read 4, iclass 37, count 0 2006.239.08:05:22.72#ibcon#about to read 5, iclass 37, count 0 2006.239.08:05:22.72#ibcon#read 5, iclass 37, count 0 2006.239.08:05:22.72#ibcon#about to read 6, iclass 37, count 0 2006.239.08:05:22.72#ibcon#read 6, iclass 37, count 0 2006.239.08:05:22.72#ibcon#end of sib2, iclass 37, count 0 2006.239.08:05:22.72#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:05:22.72#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:05:22.72#ibcon#[25=BW32\r\n] 2006.239.08:05:22.72#ibcon#*before write, iclass 37, count 0 2006.239.08:05:22.72#ibcon#enter sib2, iclass 37, count 0 2006.239.08:05:22.72#ibcon#flushed, iclass 37, count 0 2006.239.08:05:22.72#ibcon#about to write, iclass 37, count 0 2006.239.08:05:22.72#ibcon#wrote, iclass 37, count 0 2006.239.08:05:22.72#ibcon#about to read 3, iclass 37, count 0 2006.239.08:05:22.75#ibcon#read 3, iclass 37, count 0 2006.239.08:05:22.75#ibcon#about to read 4, iclass 37, count 0 2006.239.08:05:22.75#ibcon#read 4, iclass 37, count 0 2006.239.08:05:22.75#ibcon#about to read 5, iclass 37, count 0 2006.239.08:05:22.75#ibcon#read 5, iclass 37, count 0 2006.239.08:05:22.75#ibcon#about to read 6, iclass 37, count 0 2006.239.08:05:22.75#ibcon#read 6, iclass 37, count 0 2006.239.08:05:22.75#ibcon#end of sib2, iclass 37, count 0 2006.239.08:05:22.75#ibcon#*after write, iclass 37, count 0 2006.239.08:05:22.75#ibcon#*before return 0, iclass 37, count 0 2006.239.08:05:22.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:22.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:05:22.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:05:22.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:05:22.75$vc4f8/vbbw=wide 2006.239.08:05:22.75#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:05:22.75#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:05:22.75#ibcon#ireg 8 cls_cnt 0 2006.239.08:05:22.75#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:05:22.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:05:22.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:05:22.82#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:05:22.82#ibcon#first serial, iclass 39, count 0 2006.239.08:05:22.82#ibcon#enter sib2, iclass 39, count 0 2006.239.08:05:22.82#ibcon#flushed, iclass 39, count 0 2006.239.08:05:22.82#ibcon#about to write, iclass 39, count 0 2006.239.08:05:22.82#ibcon#wrote, iclass 39, count 0 2006.239.08:05:22.82#ibcon#about to read 3, iclass 39, count 0 2006.239.08:05:22.84#ibcon#read 3, iclass 39, count 0 2006.239.08:05:22.84#ibcon#about to read 4, iclass 39, count 0 2006.239.08:05:22.84#ibcon#read 4, iclass 39, count 0 2006.239.08:05:22.84#ibcon#about to read 5, iclass 39, count 0 2006.239.08:05:22.84#ibcon#read 5, iclass 39, count 0 2006.239.08:05:22.84#ibcon#about to read 6, iclass 39, count 0 2006.239.08:05:22.84#ibcon#read 6, iclass 39, count 0 2006.239.08:05:22.84#ibcon#end of sib2, iclass 39, count 0 2006.239.08:05:22.84#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:05:22.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:05:22.84#ibcon#[27=BW32\r\n] 2006.239.08:05:22.84#ibcon#*before write, iclass 39, count 0 2006.239.08:05:22.84#ibcon#enter sib2, iclass 39, count 0 2006.239.08:05:22.84#ibcon#flushed, iclass 39, count 0 2006.239.08:05:22.84#ibcon#about to write, iclass 39, count 0 2006.239.08:05:22.84#ibcon#wrote, iclass 39, count 0 2006.239.08:05:22.84#ibcon#about to read 3, iclass 39, count 0 2006.239.08:05:22.87#ibcon#read 3, iclass 39, count 0 2006.239.08:05:22.87#ibcon#about to read 4, iclass 39, count 0 2006.239.08:05:22.87#ibcon#read 4, iclass 39, count 0 2006.239.08:05:22.87#ibcon#about to read 5, iclass 39, count 0 2006.239.08:05:22.87#ibcon#read 5, iclass 39, count 0 2006.239.08:05:22.87#ibcon#about to read 6, iclass 39, count 0 2006.239.08:05:22.87#ibcon#read 6, iclass 39, count 0 2006.239.08:05:22.87#ibcon#end of sib2, iclass 39, count 0 2006.239.08:05:22.87#ibcon#*after write, iclass 39, count 0 2006.239.08:05:22.87#ibcon#*before return 0, iclass 39, count 0 2006.239.08:05:22.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:05:22.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:05:22.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:05:22.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:05:22.87$4f8m12a/ifd4f 2006.239.08:05:22.87$ifd4f/lo= 2006.239.08:05:22.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:05:22.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:05:22.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:05:22.87$ifd4f/patch= 2006.239.08:05:22.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:05:22.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:05:22.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:05:22.87$4f8m12a/"form=m,16.000,1:2 2006.239.08:05:22.87$4f8m12a/"tpicd 2006.239.08:05:22.87$4f8m12a/echo=off 2006.239.08:05:22.87$4f8m12a/xlog=off 2006.239.08:05:22.87:!2006.239.08:05:50 2006.239.08:05:29.13#trakl#Source acquired 2006.239.08:05:29.13#flagr#flagr/antenna,acquired 2006.239.08:05:50.00:preob 2006.239.08:05:51.13/onsource/TRACKING 2006.239.08:05:51.13:!2006.239.08:06:00 2006.239.08:06:00.00:data_valid=on 2006.239.08:06:00.00:midob 2006.239.08:06:00.13/onsource/TRACKING 2006.239.08:06:00.13/wx/25.12,1011.6,80 2006.239.08:06:00.27/cable/+6.4137E-03 2006.239.08:06:01.36/va/01,08,usb,yes,31,32 2006.239.08:06:01.36/va/02,07,usb,yes,31,32 2006.239.08:06:01.36/va/03,07,usb,yes,29,29 2006.239.08:06:01.36/va/04,07,usb,yes,32,35 2006.239.08:06:01.36/va/05,08,usb,yes,30,31 2006.239.08:06:01.36/va/06,07,usb,yes,32,32 2006.239.08:06:01.36/va/07,07,usb,yes,32,32 2006.239.08:06:01.36/va/08,07,usb,yes,35,34 2006.239.08:06:01.59/valo/01,532.99,yes,locked 2006.239.08:06:01.59/valo/02,572.99,yes,locked 2006.239.08:06:01.59/valo/03,672.99,yes,locked 2006.239.08:06:01.59/valo/04,832.99,yes,locked 2006.239.08:06:01.59/valo/05,652.99,yes,locked 2006.239.08:06:01.59/valo/06,772.99,yes,locked 2006.239.08:06:01.59/valo/07,832.99,yes,locked 2006.239.08:06:01.59/valo/08,852.99,yes,locked 2006.239.08:06:02.68/vb/01,04,usb,yes,31,29 2006.239.08:06:02.68/vb/02,04,usb,yes,32,34 2006.239.08:06:02.68/vb/03,04,usb,yes,29,32 2006.239.08:06:02.68/vb/04,04,usb,yes,30,30 2006.239.08:06:02.68/vb/05,04,usb,yes,28,32 2006.239.08:06:02.68/vb/06,04,usb,yes,29,32 2006.239.08:06:02.68/vb/07,04,usb,yes,31,31 2006.239.08:06:02.68/vb/08,04,usb,yes,29,32 2006.239.08:06:02.91/vblo/01,632.99,yes,locked 2006.239.08:06:02.91/vblo/02,640.99,yes,locked 2006.239.08:06:02.91/vblo/03,656.99,yes,locked 2006.239.08:06:02.91/vblo/04,712.99,yes,locked 2006.239.08:06:02.91/vblo/05,744.99,yes,locked 2006.239.08:06:02.91/vblo/06,752.99,yes,locked 2006.239.08:06:02.91/vblo/07,734.99,yes,locked 2006.239.08:06:02.91/vblo/08,744.99,yes,locked 2006.239.08:06:03.06/vabw/8 2006.239.08:06:03.21/vbbw/8 2006.239.08:06:03.30/xfe/off,on,13.5 2006.239.08:06:03.68/ifatt/23,28,28,28 2006.239.08:06:04.08/fmout-gps/S +4.40E-07 2006.239.08:06:04.12:!2006.239.08:07:00 2006.239.08:07:00.00:data_valid=off 2006.239.08:07:00.00:postob 2006.239.08:07:00.13/cable/+6.4161E-03 2006.239.08:07:00.13/wx/25.12,1011.6,80 2006.239.08:07:01.07/fmout-gps/S +4.40E-07 2006.239.08:07:01.07:scan_name=239-0807,k06239,60 2006.239.08:07:01.07:source=oq208,140700.39,282714.7,2000.0,ccw 2006.239.08:07:01.14#flagr#flagr/antenna,new-source 2006.239.08:07:02.13:checkk5 2006.239.08:07:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:07:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:07:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:07:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:07:03.99/chk_obsdata//k5ts1/T2390806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:07:04.36/chk_obsdata//k5ts2/T2390806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:07:04.74/chk_obsdata//k5ts3/T2390806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:07:05.11/chk_obsdata//k5ts4/T2390806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:07:05.80/k5log//k5ts1_log_newline 2006.239.08:07:06.50/k5log//k5ts2_log_newline 2006.239.08:07:07.19/k5log//k5ts3_log_newline 2006.239.08:07:07.88/k5log//k5ts4_log_newline 2006.239.08:07:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:07:07.90:4f8m12a=2 2006.239.08:07:07.90$4f8m12a/echo=on 2006.239.08:07:07.90$4f8m12a/pcalon 2006.239.08:07:07.90$pcalon/"no phase cal control is implemented here 2006.239.08:07:07.90$4f8m12a/"tpicd=stop 2006.239.08:07:07.90$4f8m12a/vc4f8 2006.239.08:07:07.91$vc4f8/valo=1,532.99 2006.239.08:07:07.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.08:07:07.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.08:07:07.91#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:07.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:07:07.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:07:07.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:07:07.91#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:07:07.91#ibcon#first serial, iclass 10, count 0 2006.239.08:07:07.91#ibcon#enter sib2, iclass 10, count 0 2006.239.08:07:07.91#ibcon#flushed, iclass 10, count 0 2006.239.08:07:07.91#ibcon#about to write, iclass 10, count 0 2006.239.08:07:07.91#ibcon#wrote, iclass 10, count 0 2006.239.08:07:07.91#ibcon#about to read 3, iclass 10, count 0 2006.239.08:07:07.95#ibcon#read 3, iclass 10, count 0 2006.239.08:07:07.95#ibcon#about to read 4, iclass 10, count 0 2006.239.08:07:07.95#ibcon#read 4, iclass 10, count 0 2006.239.08:07:07.95#ibcon#about to read 5, iclass 10, count 0 2006.239.08:07:07.95#ibcon#read 5, iclass 10, count 0 2006.239.08:07:07.95#ibcon#about to read 6, iclass 10, count 0 2006.239.08:07:07.95#ibcon#read 6, iclass 10, count 0 2006.239.08:07:07.95#ibcon#end of sib2, iclass 10, count 0 2006.239.08:07:07.95#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:07:07.95#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:07:07.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:07:07.95#ibcon#*before write, iclass 10, count 0 2006.239.08:07:07.95#ibcon#enter sib2, iclass 10, count 0 2006.239.08:07:07.95#ibcon#flushed, iclass 10, count 0 2006.239.08:07:07.95#ibcon#about to write, iclass 10, count 0 2006.239.08:07:07.95#ibcon#wrote, iclass 10, count 0 2006.239.08:07:07.95#ibcon#about to read 3, iclass 10, count 0 2006.239.08:07:08.00#ibcon#read 3, iclass 10, count 0 2006.239.08:07:08.00#ibcon#about to read 4, iclass 10, count 0 2006.239.08:07:08.00#ibcon#read 4, iclass 10, count 0 2006.239.08:07:08.00#ibcon#about to read 5, iclass 10, count 0 2006.239.08:07:08.00#ibcon#read 5, iclass 10, count 0 2006.239.08:07:08.00#ibcon#about to read 6, iclass 10, count 0 2006.239.08:07:08.00#ibcon#read 6, iclass 10, count 0 2006.239.08:07:08.00#ibcon#end of sib2, iclass 10, count 0 2006.239.08:07:08.00#ibcon#*after write, iclass 10, count 0 2006.239.08:07:08.00#ibcon#*before return 0, iclass 10, count 0 2006.239.08:07:08.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:07:08.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:07:08.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:07:08.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:07:08.00$vc4f8/va=1,8 2006.239.08:07:08.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.08:07:08.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.08:07:08.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:08.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:07:08.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:07:08.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:07:08.00#ibcon#enter wrdev, iclass 12, count 2 2006.239.08:07:08.00#ibcon#first serial, iclass 12, count 2 2006.239.08:07:08.00#ibcon#enter sib2, iclass 12, count 2 2006.239.08:07:08.00#ibcon#flushed, iclass 12, count 2 2006.239.08:07:08.00#ibcon#about to write, iclass 12, count 2 2006.239.08:07:08.00#ibcon#wrote, iclass 12, count 2 2006.239.08:07:08.00#ibcon#about to read 3, iclass 12, count 2 2006.239.08:07:08.02#ibcon#read 3, iclass 12, count 2 2006.239.08:07:08.02#ibcon#about to read 4, iclass 12, count 2 2006.239.08:07:08.02#ibcon#read 4, iclass 12, count 2 2006.239.08:07:08.02#ibcon#about to read 5, iclass 12, count 2 2006.239.08:07:08.02#ibcon#read 5, iclass 12, count 2 2006.239.08:07:08.02#ibcon#about to read 6, iclass 12, count 2 2006.239.08:07:08.02#ibcon#read 6, iclass 12, count 2 2006.239.08:07:08.02#ibcon#end of sib2, iclass 12, count 2 2006.239.08:07:08.02#ibcon#*mode == 0, iclass 12, count 2 2006.239.08:07:08.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.08:07:08.02#ibcon#[25=AT01-08\r\n] 2006.239.08:07:08.02#ibcon#*before write, iclass 12, count 2 2006.239.08:07:08.02#ibcon#enter sib2, iclass 12, count 2 2006.239.08:07:08.02#ibcon#flushed, iclass 12, count 2 2006.239.08:07:08.02#ibcon#about to write, iclass 12, count 2 2006.239.08:07:08.02#ibcon#wrote, iclass 12, count 2 2006.239.08:07:08.02#ibcon#about to read 3, iclass 12, count 2 2006.239.08:07:08.05#ibcon#read 3, iclass 12, count 2 2006.239.08:07:08.05#ibcon#about to read 4, iclass 12, count 2 2006.239.08:07:08.05#ibcon#read 4, iclass 12, count 2 2006.239.08:07:08.05#ibcon#about to read 5, iclass 12, count 2 2006.239.08:07:08.05#ibcon#read 5, iclass 12, count 2 2006.239.08:07:08.05#ibcon#about to read 6, iclass 12, count 2 2006.239.08:07:08.05#ibcon#read 6, iclass 12, count 2 2006.239.08:07:08.05#ibcon#end of sib2, iclass 12, count 2 2006.239.08:07:08.05#ibcon#*after write, iclass 12, count 2 2006.239.08:07:08.05#ibcon#*before return 0, iclass 12, count 2 2006.239.08:07:08.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:07:08.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:07:08.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.08:07:08.05#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:08.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:07:08.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:07:08.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:07:08.17#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:07:08.17#ibcon#first serial, iclass 12, count 0 2006.239.08:07:08.17#ibcon#enter sib2, iclass 12, count 0 2006.239.08:07:08.17#ibcon#flushed, iclass 12, count 0 2006.239.08:07:08.17#ibcon#about to write, iclass 12, count 0 2006.239.08:07:08.17#ibcon#wrote, iclass 12, count 0 2006.239.08:07:08.17#ibcon#about to read 3, iclass 12, count 0 2006.239.08:07:08.19#ibcon#read 3, iclass 12, count 0 2006.239.08:07:08.19#ibcon#about to read 4, iclass 12, count 0 2006.239.08:07:08.19#ibcon#read 4, iclass 12, count 0 2006.239.08:07:08.19#ibcon#about to read 5, iclass 12, count 0 2006.239.08:07:08.19#ibcon#read 5, iclass 12, count 0 2006.239.08:07:08.19#ibcon#about to read 6, iclass 12, count 0 2006.239.08:07:08.19#ibcon#read 6, iclass 12, count 0 2006.239.08:07:08.19#ibcon#end of sib2, iclass 12, count 0 2006.239.08:07:08.19#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:07:08.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:07:08.19#ibcon#[25=USB\r\n] 2006.239.08:07:08.19#ibcon#*before write, iclass 12, count 0 2006.239.08:07:08.19#ibcon#enter sib2, iclass 12, count 0 2006.239.08:07:08.19#ibcon#flushed, iclass 12, count 0 2006.239.08:07:08.19#ibcon#about to write, iclass 12, count 0 2006.239.08:07:08.19#ibcon#wrote, iclass 12, count 0 2006.239.08:07:08.19#ibcon#about to read 3, iclass 12, count 0 2006.239.08:07:08.22#ibcon#read 3, iclass 12, count 0 2006.239.08:07:08.22#ibcon#about to read 4, iclass 12, count 0 2006.239.08:07:08.22#ibcon#read 4, iclass 12, count 0 2006.239.08:07:08.22#ibcon#about to read 5, iclass 12, count 0 2006.239.08:07:08.22#ibcon#read 5, iclass 12, count 0 2006.239.08:07:08.22#ibcon#about to read 6, iclass 12, count 0 2006.239.08:07:08.22#ibcon#read 6, iclass 12, count 0 2006.239.08:07:08.22#ibcon#end of sib2, iclass 12, count 0 2006.239.08:07:08.22#ibcon#*after write, iclass 12, count 0 2006.239.08:07:08.22#ibcon#*before return 0, iclass 12, count 0 2006.239.08:07:08.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:07:08.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:07:08.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:07:08.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:07:08.22$vc4f8/valo=2,572.99 2006.239.08:07:08.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.08:07:08.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.08:07:08.22#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:08.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:07:08.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:07:08.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:07:08.22#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:07:08.22#ibcon#first serial, iclass 14, count 0 2006.239.08:07:08.22#ibcon#enter sib2, iclass 14, count 0 2006.239.08:07:08.22#ibcon#flushed, iclass 14, count 0 2006.239.08:07:08.22#ibcon#about to write, iclass 14, count 0 2006.239.08:07:08.22#ibcon#wrote, iclass 14, count 0 2006.239.08:07:08.22#ibcon#about to read 3, iclass 14, count 0 2006.239.08:07:08.24#ibcon#read 3, iclass 14, count 0 2006.239.08:07:08.24#ibcon#about to read 4, iclass 14, count 0 2006.239.08:07:08.24#ibcon#read 4, iclass 14, count 0 2006.239.08:07:08.24#ibcon#about to read 5, iclass 14, count 0 2006.239.08:07:08.24#ibcon#read 5, iclass 14, count 0 2006.239.08:07:08.24#ibcon#about to read 6, iclass 14, count 0 2006.239.08:07:08.24#ibcon#read 6, iclass 14, count 0 2006.239.08:07:08.24#ibcon#end of sib2, iclass 14, count 0 2006.239.08:07:08.24#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:07:08.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:07:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:07:08.24#ibcon#*before write, iclass 14, count 0 2006.239.08:07:08.24#ibcon#enter sib2, iclass 14, count 0 2006.239.08:07:08.24#ibcon#flushed, iclass 14, count 0 2006.239.08:07:08.24#ibcon#about to write, iclass 14, count 0 2006.239.08:07:08.24#ibcon#wrote, iclass 14, count 0 2006.239.08:07:08.24#ibcon#about to read 3, iclass 14, count 0 2006.239.08:07:08.28#ibcon#read 3, iclass 14, count 0 2006.239.08:07:08.28#ibcon#about to read 4, iclass 14, count 0 2006.239.08:07:08.28#ibcon#read 4, iclass 14, count 0 2006.239.08:07:08.28#ibcon#about to read 5, iclass 14, count 0 2006.239.08:07:08.28#ibcon#read 5, iclass 14, count 0 2006.239.08:07:08.28#ibcon#about to read 6, iclass 14, count 0 2006.239.08:07:08.28#ibcon#read 6, iclass 14, count 0 2006.239.08:07:08.28#ibcon#end of sib2, iclass 14, count 0 2006.239.08:07:08.28#ibcon#*after write, iclass 14, count 0 2006.239.08:07:08.28#ibcon#*before return 0, iclass 14, count 0 2006.239.08:07:08.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:07:08.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:07:08.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:07:08.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:07:08.28$vc4f8/va=2,7 2006.239.08:07:08.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.08:07:08.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.08:07:08.28#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:08.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:08.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:08.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:08.34#ibcon#enter wrdev, iclass 16, count 2 2006.239.08:07:08.34#ibcon#first serial, iclass 16, count 2 2006.239.08:07:08.34#ibcon#enter sib2, iclass 16, count 2 2006.239.08:07:08.34#ibcon#flushed, iclass 16, count 2 2006.239.08:07:08.34#ibcon#about to write, iclass 16, count 2 2006.239.08:07:08.34#ibcon#wrote, iclass 16, count 2 2006.239.08:07:08.34#ibcon#about to read 3, iclass 16, count 2 2006.239.08:07:08.36#ibcon#read 3, iclass 16, count 2 2006.239.08:07:08.36#ibcon#about to read 4, iclass 16, count 2 2006.239.08:07:08.36#ibcon#read 4, iclass 16, count 2 2006.239.08:07:08.36#ibcon#about to read 5, iclass 16, count 2 2006.239.08:07:08.36#ibcon#read 5, iclass 16, count 2 2006.239.08:07:08.36#ibcon#about to read 6, iclass 16, count 2 2006.239.08:07:08.36#ibcon#read 6, iclass 16, count 2 2006.239.08:07:08.36#ibcon#end of sib2, iclass 16, count 2 2006.239.08:07:08.36#ibcon#*mode == 0, iclass 16, count 2 2006.239.08:07:08.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.08:07:08.36#ibcon#[25=AT02-07\r\n] 2006.239.08:07:08.36#ibcon#*before write, iclass 16, count 2 2006.239.08:07:08.36#ibcon#enter sib2, iclass 16, count 2 2006.239.08:07:08.36#ibcon#flushed, iclass 16, count 2 2006.239.08:07:08.36#ibcon#about to write, iclass 16, count 2 2006.239.08:07:08.36#ibcon#wrote, iclass 16, count 2 2006.239.08:07:08.36#ibcon#about to read 3, iclass 16, count 2 2006.239.08:07:08.39#ibcon#read 3, iclass 16, count 2 2006.239.08:07:08.39#ibcon#about to read 4, iclass 16, count 2 2006.239.08:07:08.39#ibcon#read 4, iclass 16, count 2 2006.239.08:07:08.39#ibcon#about to read 5, iclass 16, count 2 2006.239.08:07:08.39#ibcon#read 5, iclass 16, count 2 2006.239.08:07:08.39#ibcon#about to read 6, iclass 16, count 2 2006.239.08:07:08.39#ibcon#read 6, iclass 16, count 2 2006.239.08:07:08.39#ibcon#end of sib2, iclass 16, count 2 2006.239.08:07:08.39#ibcon#*after write, iclass 16, count 2 2006.239.08:07:08.39#ibcon#*before return 0, iclass 16, count 2 2006.239.08:07:08.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:08.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:08.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.08:07:08.39#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:08.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:08.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:08.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:08.51#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:07:08.51#ibcon#first serial, iclass 16, count 0 2006.239.08:07:08.51#ibcon#enter sib2, iclass 16, count 0 2006.239.08:07:08.51#ibcon#flushed, iclass 16, count 0 2006.239.08:07:08.51#ibcon#about to write, iclass 16, count 0 2006.239.08:07:08.51#ibcon#wrote, iclass 16, count 0 2006.239.08:07:08.51#ibcon#about to read 3, iclass 16, count 0 2006.239.08:07:08.53#ibcon#read 3, iclass 16, count 0 2006.239.08:07:08.53#ibcon#about to read 4, iclass 16, count 0 2006.239.08:07:08.53#ibcon#read 4, iclass 16, count 0 2006.239.08:07:08.53#ibcon#about to read 5, iclass 16, count 0 2006.239.08:07:08.53#ibcon#read 5, iclass 16, count 0 2006.239.08:07:08.53#ibcon#about to read 6, iclass 16, count 0 2006.239.08:07:08.53#ibcon#read 6, iclass 16, count 0 2006.239.08:07:08.53#ibcon#end of sib2, iclass 16, count 0 2006.239.08:07:08.53#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:07:08.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:07:08.53#ibcon#[25=USB\r\n] 2006.239.08:07:08.53#ibcon#*before write, iclass 16, count 0 2006.239.08:07:08.53#ibcon#enter sib2, iclass 16, count 0 2006.239.08:07:08.53#ibcon#flushed, iclass 16, count 0 2006.239.08:07:08.53#ibcon#about to write, iclass 16, count 0 2006.239.08:07:08.53#ibcon#wrote, iclass 16, count 0 2006.239.08:07:08.53#ibcon#about to read 3, iclass 16, count 0 2006.239.08:07:08.56#ibcon#read 3, iclass 16, count 0 2006.239.08:07:08.56#ibcon#about to read 4, iclass 16, count 0 2006.239.08:07:08.56#ibcon#read 4, iclass 16, count 0 2006.239.08:07:08.56#ibcon#about to read 5, iclass 16, count 0 2006.239.08:07:08.56#ibcon#read 5, iclass 16, count 0 2006.239.08:07:08.56#ibcon#about to read 6, iclass 16, count 0 2006.239.08:07:08.56#ibcon#read 6, iclass 16, count 0 2006.239.08:07:08.56#ibcon#end of sib2, iclass 16, count 0 2006.239.08:07:08.56#ibcon#*after write, iclass 16, count 0 2006.239.08:07:08.56#ibcon#*before return 0, iclass 16, count 0 2006.239.08:07:08.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:08.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:08.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:07:08.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:07:08.56$vc4f8/valo=3,672.99 2006.239.08:07:08.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:07:08.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:07:08.56#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:08.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:08.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:08.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:08.56#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:07:08.56#ibcon#first serial, iclass 18, count 0 2006.239.08:07:08.56#ibcon#enter sib2, iclass 18, count 0 2006.239.08:07:08.56#ibcon#flushed, iclass 18, count 0 2006.239.08:07:08.56#ibcon#about to write, iclass 18, count 0 2006.239.08:07:08.56#ibcon#wrote, iclass 18, count 0 2006.239.08:07:08.56#ibcon#about to read 3, iclass 18, count 0 2006.239.08:07:08.58#ibcon#read 3, iclass 18, count 0 2006.239.08:07:08.58#ibcon#about to read 4, iclass 18, count 0 2006.239.08:07:08.58#ibcon#read 4, iclass 18, count 0 2006.239.08:07:08.58#ibcon#about to read 5, iclass 18, count 0 2006.239.08:07:08.58#ibcon#read 5, iclass 18, count 0 2006.239.08:07:08.58#ibcon#about to read 6, iclass 18, count 0 2006.239.08:07:08.58#ibcon#read 6, iclass 18, count 0 2006.239.08:07:08.58#ibcon#end of sib2, iclass 18, count 0 2006.239.08:07:08.58#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:07:08.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:07:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:07:08.58#ibcon#*before write, iclass 18, count 0 2006.239.08:07:08.58#ibcon#enter sib2, iclass 18, count 0 2006.239.08:07:08.58#ibcon#flushed, iclass 18, count 0 2006.239.08:07:08.58#ibcon#about to write, iclass 18, count 0 2006.239.08:07:08.58#ibcon#wrote, iclass 18, count 0 2006.239.08:07:08.58#ibcon#about to read 3, iclass 18, count 0 2006.239.08:07:08.62#ibcon#read 3, iclass 18, count 0 2006.239.08:07:08.62#ibcon#about to read 4, iclass 18, count 0 2006.239.08:07:08.62#ibcon#read 4, iclass 18, count 0 2006.239.08:07:08.62#ibcon#about to read 5, iclass 18, count 0 2006.239.08:07:08.62#ibcon#read 5, iclass 18, count 0 2006.239.08:07:08.62#ibcon#about to read 6, iclass 18, count 0 2006.239.08:07:08.62#ibcon#read 6, iclass 18, count 0 2006.239.08:07:08.62#ibcon#end of sib2, iclass 18, count 0 2006.239.08:07:08.62#ibcon#*after write, iclass 18, count 0 2006.239.08:07:08.62#ibcon#*before return 0, iclass 18, count 0 2006.239.08:07:08.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:08.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:08.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:07:08.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:07:08.62$vc4f8/va=3,7 2006.239.08:07:08.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.08:07:08.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.08:07:08.62#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:08.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:08.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:08.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:08.68#ibcon#enter wrdev, iclass 20, count 2 2006.239.08:07:08.68#ibcon#first serial, iclass 20, count 2 2006.239.08:07:08.68#ibcon#enter sib2, iclass 20, count 2 2006.239.08:07:08.68#ibcon#flushed, iclass 20, count 2 2006.239.08:07:08.68#ibcon#about to write, iclass 20, count 2 2006.239.08:07:08.68#ibcon#wrote, iclass 20, count 2 2006.239.08:07:08.68#ibcon#about to read 3, iclass 20, count 2 2006.239.08:07:08.70#ibcon#read 3, iclass 20, count 2 2006.239.08:07:08.70#ibcon#about to read 4, iclass 20, count 2 2006.239.08:07:08.70#ibcon#read 4, iclass 20, count 2 2006.239.08:07:08.70#ibcon#about to read 5, iclass 20, count 2 2006.239.08:07:08.70#ibcon#read 5, iclass 20, count 2 2006.239.08:07:08.70#ibcon#about to read 6, iclass 20, count 2 2006.239.08:07:08.70#ibcon#read 6, iclass 20, count 2 2006.239.08:07:08.70#ibcon#end of sib2, iclass 20, count 2 2006.239.08:07:08.70#ibcon#*mode == 0, iclass 20, count 2 2006.239.08:07:08.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.08:07:08.70#ibcon#[25=AT03-07\r\n] 2006.239.08:07:08.70#ibcon#*before write, iclass 20, count 2 2006.239.08:07:08.70#ibcon#enter sib2, iclass 20, count 2 2006.239.08:07:08.70#ibcon#flushed, iclass 20, count 2 2006.239.08:07:08.70#ibcon#about to write, iclass 20, count 2 2006.239.08:07:08.70#ibcon#wrote, iclass 20, count 2 2006.239.08:07:08.70#ibcon#about to read 3, iclass 20, count 2 2006.239.08:07:08.73#ibcon#read 3, iclass 20, count 2 2006.239.08:07:08.73#ibcon#about to read 4, iclass 20, count 2 2006.239.08:07:08.73#ibcon#read 4, iclass 20, count 2 2006.239.08:07:08.73#ibcon#about to read 5, iclass 20, count 2 2006.239.08:07:08.73#ibcon#read 5, iclass 20, count 2 2006.239.08:07:08.73#ibcon#about to read 6, iclass 20, count 2 2006.239.08:07:08.73#ibcon#read 6, iclass 20, count 2 2006.239.08:07:08.73#ibcon#end of sib2, iclass 20, count 2 2006.239.08:07:08.73#ibcon#*after write, iclass 20, count 2 2006.239.08:07:08.73#ibcon#*before return 0, iclass 20, count 2 2006.239.08:07:08.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:08.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:08.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.08:07:08.73#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:08.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:08.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:08.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:08.85#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:07:08.85#ibcon#first serial, iclass 20, count 0 2006.239.08:07:08.85#ibcon#enter sib2, iclass 20, count 0 2006.239.08:07:08.85#ibcon#flushed, iclass 20, count 0 2006.239.08:07:08.85#ibcon#about to write, iclass 20, count 0 2006.239.08:07:08.85#ibcon#wrote, iclass 20, count 0 2006.239.08:07:08.85#ibcon#about to read 3, iclass 20, count 0 2006.239.08:07:08.87#ibcon#read 3, iclass 20, count 0 2006.239.08:07:08.87#ibcon#about to read 4, iclass 20, count 0 2006.239.08:07:08.87#ibcon#read 4, iclass 20, count 0 2006.239.08:07:08.87#ibcon#about to read 5, iclass 20, count 0 2006.239.08:07:08.87#ibcon#read 5, iclass 20, count 0 2006.239.08:07:08.87#ibcon#about to read 6, iclass 20, count 0 2006.239.08:07:08.87#ibcon#read 6, iclass 20, count 0 2006.239.08:07:08.87#ibcon#end of sib2, iclass 20, count 0 2006.239.08:07:08.87#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:07:08.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:07:08.87#ibcon#[25=USB\r\n] 2006.239.08:07:08.87#ibcon#*before write, iclass 20, count 0 2006.239.08:07:08.87#ibcon#enter sib2, iclass 20, count 0 2006.239.08:07:08.87#ibcon#flushed, iclass 20, count 0 2006.239.08:07:08.87#ibcon#about to write, iclass 20, count 0 2006.239.08:07:08.87#ibcon#wrote, iclass 20, count 0 2006.239.08:07:08.87#ibcon#about to read 3, iclass 20, count 0 2006.239.08:07:08.91#ibcon#read 3, iclass 20, count 0 2006.239.08:07:08.91#ibcon#about to read 4, iclass 20, count 0 2006.239.08:07:08.91#ibcon#read 4, iclass 20, count 0 2006.239.08:07:08.91#ibcon#about to read 5, iclass 20, count 0 2006.239.08:07:08.91#ibcon#read 5, iclass 20, count 0 2006.239.08:07:08.91#ibcon#about to read 6, iclass 20, count 0 2006.239.08:07:08.91#ibcon#read 6, iclass 20, count 0 2006.239.08:07:08.91#ibcon#end of sib2, iclass 20, count 0 2006.239.08:07:08.91#ibcon#*after write, iclass 20, count 0 2006.239.08:07:08.91#ibcon#*before return 0, iclass 20, count 0 2006.239.08:07:08.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:08.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:08.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:07:08.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:07:08.91$vc4f8/valo=4,832.99 2006.239.08:07:08.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.08:07:08.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.08:07:08.91#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:08.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:08.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:08.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:08.91#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:07:08.91#ibcon#first serial, iclass 22, count 0 2006.239.08:07:08.91#ibcon#enter sib2, iclass 22, count 0 2006.239.08:07:08.91#ibcon#flushed, iclass 22, count 0 2006.239.08:07:08.91#ibcon#about to write, iclass 22, count 0 2006.239.08:07:08.91#ibcon#wrote, iclass 22, count 0 2006.239.08:07:08.91#ibcon#about to read 3, iclass 22, count 0 2006.239.08:07:08.93#ibcon#read 3, iclass 22, count 0 2006.239.08:07:08.93#ibcon#about to read 4, iclass 22, count 0 2006.239.08:07:08.93#ibcon#read 4, iclass 22, count 0 2006.239.08:07:08.93#ibcon#about to read 5, iclass 22, count 0 2006.239.08:07:08.93#ibcon#read 5, iclass 22, count 0 2006.239.08:07:08.93#ibcon#about to read 6, iclass 22, count 0 2006.239.08:07:08.93#ibcon#read 6, iclass 22, count 0 2006.239.08:07:08.93#ibcon#end of sib2, iclass 22, count 0 2006.239.08:07:08.93#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:07:08.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:07:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:07:08.93#ibcon#*before write, iclass 22, count 0 2006.239.08:07:08.93#ibcon#enter sib2, iclass 22, count 0 2006.239.08:07:08.93#ibcon#flushed, iclass 22, count 0 2006.239.08:07:08.93#ibcon#about to write, iclass 22, count 0 2006.239.08:07:08.93#ibcon#wrote, iclass 22, count 0 2006.239.08:07:08.93#ibcon#about to read 3, iclass 22, count 0 2006.239.08:07:08.97#ibcon#read 3, iclass 22, count 0 2006.239.08:07:08.97#ibcon#about to read 4, iclass 22, count 0 2006.239.08:07:08.97#ibcon#read 4, iclass 22, count 0 2006.239.08:07:08.97#ibcon#about to read 5, iclass 22, count 0 2006.239.08:07:08.97#ibcon#read 5, iclass 22, count 0 2006.239.08:07:08.97#ibcon#about to read 6, iclass 22, count 0 2006.239.08:07:08.97#ibcon#read 6, iclass 22, count 0 2006.239.08:07:08.97#ibcon#end of sib2, iclass 22, count 0 2006.239.08:07:08.97#ibcon#*after write, iclass 22, count 0 2006.239.08:07:08.97#ibcon#*before return 0, iclass 22, count 0 2006.239.08:07:08.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:08.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:08.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:07:08.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:07:08.97$vc4f8/va=4,7 2006.239.08:07:08.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.08:07:08.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.08:07:08.97#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:08.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:09.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:09.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:09.03#ibcon#enter wrdev, iclass 24, count 2 2006.239.08:07:09.03#ibcon#first serial, iclass 24, count 2 2006.239.08:07:09.03#ibcon#enter sib2, iclass 24, count 2 2006.239.08:07:09.03#ibcon#flushed, iclass 24, count 2 2006.239.08:07:09.03#ibcon#about to write, iclass 24, count 2 2006.239.08:07:09.03#ibcon#wrote, iclass 24, count 2 2006.239.08:07:09.03#ibcon#about to read 3, iclass 24, count 2 2006.239.08:07:09.05#ibcon#read 3, iclass 24, count 2 2006.239.08:07:09.05#ibcon#about to read 4, iclass 24, count 2 2006.239.08:07:09.05#ibcon#read 4, iclass 24, count 2 2006.239.08:07:09.05#ibcon#about to read 5, iclass 24, count 2 2006.239.08:07:09.05#ibcon#read 5, iclass 24, count 2 2006.239.08:07:09.05#ibcon#about to read 6, iclass 24, count 2 2006.239.08:07:09.05#ibcon#read 6, iclass 24, count 2 2006.239.08:07:09.05#ibcon#end of sib2, iclass 24, count 2 2006.239.08:07:09.05#ibcon#*mode == 0, iclass 24, count 2 2006.239.08:07:09.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.08:07:09.05#ibcon#[25=AT04-07\r\n] 2006.239.08:07:09.05#ibcon#*before write, iclass 24, count 2 2006.239.08:07:09.05#ibcon#enter sib2, iclass 24, count 2 2006.239.08:07:09.05#ibcon#flushed, iclass 24, count 2 2006.239.08:07:09.05#ibcon#about to write, iclass 24, count 2 2006.239.08:07:09.05#ibcon#wrote, iclass 24, count 2 2006.239.08:07:09.05#ibcon#about to read 3, iclass 24, count 2 2006.239.08:07:09.08#ibcon#read 3, iclass 24, count 2 2006.239.08:07:09.08#ibcon#about to read 4, iclass 24, count 2 2006.239.08:07:09.08#ibcon#read 4, iclass 24, count 2 2006.239.08:07:09.08#ibcon#about to read 5, iclass 24, count 2 2006.239.08:07:09.08#ibcon#read 5, iclass 24, count 2 2006.239.08:07:09.08#ibcon#about to read 6, iclass 24, count 2 2006.239.08:07:09.08#ibcon#read 6, iclass 24, count 2 2006.239.08:07:09.08#ibcon#end of sib2, iclass 24, count 2 2006.239.08:07:09.08#ibcon#*after write, iclass 24, count 2 2006.239.08:07:09.08#ibcon#*before return 0, iclass 24, count 2 2006.239.08:07:09.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:09.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:09.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.08:07:09.08#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:09.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:09.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:09.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:09.20#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:07:09.20#ibcon#first serial, iclass 24, count 0 2006.239.08:07:09.20#ibcon#enter sib2, iclass 24, count 0 2006.239.08:07:09.20#ibcon#flushed, iclass 24, count 0 2006.239.08:07:09.20#ibcon#about to write, iclass 24, count 0 2006.239.08:07:09.20#ibcon#wrote, iclass 24, count 0 2006.239.08:07:09.20#ibcon#about to read 3, iclass 24, count 0 2006.239.08:07:09.22#ibcon#read 3, iclass 24, count 0 2006.239.08:07:09.22#ibcon#about to read 4, iclass 24, count 0 2006.239.08:07:09.22#ibcon#read 4, iclass 24, count 0 2006.239.08:07:09.22#ibcon#about to read 5, iclass 24, count 0 2006.239.08:07:09.22#ibcon#read 5, iclass 24, count 0 2006.239.08:07:09.22#ibcon#about to read 6, iclass 24, count 0 2006.239.08:07:09.22#ibcon#read 6, iclass 24, count 0 2006.239.08:07:09.22#ibcon#end of sib2, iclass 24, count 0 2006.239.08:07:09.22#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:07:09.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:07:09.22#ibcon#[25=USB\r\n] 2006.239.08:07:09.22#ibcon#*before write, iclass 24, count 0 2006.239.08:07:09.22#ibcon#enter sib2, iclass 24, count 0 2006.239.08:07:09.22#ibcon#flushed, iclass 24, count 0 2006.239.08:07:09.22#ibcon#about to write, iclass 24, count 0 2006.239.08:07:09.22#ibcon#wrote, iclass 24, count 0 2006.239.08:07:09.22#ibcon#about to read 3, iclass 24, count 0 2006.239.08:07:09.25#ibcon#read 3, iclass 24, count 0 2006.239.08:07:09.25#ibcon#about to read 4, iclass 24, count 0 2006.239.08:07:09.25#ibcon#read 4, iclass 24, count 0 2006.239.08:07:09.25#ibcon#about to read 5, iclass 24, count 0 2006.239.08:07:09.25#ibcon#read 5, iclass 24, count 0 2006.239.08:07:09.25#ibcon#about to read 6, iclass 24, count 0 2006.239.08:07:09.25#ibcon#read 6, iclass 24, count 0 2006.239.08:07:09.25#ibcon#end of sib2, iclass 24, count 0 2006.239.08:07:09.25#ibcon#*after write, iclass 24, count 0 2006.239.08:07:09.25#ibcon#*before return 0, iclass 24, count 0 2006.239.08:07:09.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:09.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:09.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:07:09.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:07:09.25$vc4f8/valo=5,652.99 2006.239.08:07:09.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.08:07:09.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.08:07:09.25#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:09.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:09.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:09.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:09.25#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:07:09.25#ibcon#first serial, iclass 26, count 0 2006.239.08:07:09.25#ibcon#enter sib2, iclass 26, count 0 2006.239.08:07:09.25#ibcon#flushed, iclass 26, count 0 2006.239.08:07:09.25#ibcon#about to write, iclass 26, count 0 2006.239.08:07:09.25#ibcon#wrote, iclass 26, count 0 2006.239.08:07:09.25#ibcon#about to read 3, iclass 26, count 0 2006.239.08:07:09.27#ibcon#read 3, iclass 26, count 0 2006.239.08:07:09.27#ibcon#about to read 4, iclass 26, count 0 2006.239.08:07:09.27#ibcon#read 4, iclass 26, count 0 2006.239.08:07:09.27#ibcon#about to read 5, iclass 26, count 0 2006.239.08:07:09.27#ibcon#read 5, iclass 26, count 0 2006.239.08:07:09.27#ibcon#about to read 6, iclass 26, count 0 2006.239.08:07:09.27#ibcon#read 6, iclass 26, count 0 2006.239.08:07:09.27#ibcon#end of sib2, iclass 26, count 0 2006.239.08:07:09.27#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:07:09.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:07:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:07:09.27#ibcon#*before write, iclass 26, count 0 2006.239.08:07:09.27#ibcon#enter sib2, iclass 26, count 0 2006.239.08:07:09.27#ibcon#flushed, iclass 26, count 0 2006.239.08:07:09.27#ibcon#about to write, iclass 26, count 0 2006.239.08:07:09.27#ibcon#wrote, iclass 26, count 0 2006.239.08:07:09.27#ibcon#about to read 3, iclass 26, count 0 2006.239.08:07:09.31#ibcon#read 3, iclass 26, count 0 2006.239.08:07:09.31#ibcon#about to read 4, iclass 26, count 0 2006.239.08:07:09.31#ibcon#read 4, iclass 26, count 0 2006.239.08:07:09.31#ibcon#about to read 5, iclass 26, count 0 2006.239.08:07:09.31#ibcon#read 5, iclass 26, count 0 2006.239.08:07:09.31#ibcon#about to read 6, iclass 26, count 0 2006.239.08:07:09.31#ibcon#read 6, iclass 26, count 0 2006.239.08:07:09.31#ibcon#end of sib2, iclass 26, count 0 2006.239.08:07:09.31#ibcon#*after write, iclass 26, count 0 2006.239.08:07:09.31#ibcon#*before return 0, iclass 26, count 0 2006.239.08:07:09.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:09.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:09.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:07:09.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:07:09.31$vc4f8/va=5,8 2006.239.08:07:09.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.08:07:09.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.08:07:09.31#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:09.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:09.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:09.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:09.37#ibcon#enter wrdev, iclass 28, count 2 2006.239.08:07:09.37#ibcon#first serial, iclass 28, count 2 2006.239.08:07:09.37#ibcon#enter sib2, iclass 28, count 2 2006.239.08:07:09.37#ibcon#flushed, iclass 28, count 2 2006.239.08:07:09.37#ibcon#about to write, iclass 28, count 2 2006.239.08:07:09.37#ibcon#wrote, iclass 28, count 2 2006.239.08:07:09.37#ibcon#about to read 3, iclass 28, count 2 2006.239.08:07:09.39#ibcon#read 3, iclass 28, count 2 2006.239.08:07:09.39#ibcon#about to read 4, iclass 28, count 2 2006.239.08:07:09.39#ibcon#read 4, iclass 28, count 2 2006.239.08:07:09.39#ibcon#about to read 5, iclass 28, count 2 2006.239.08:07:09.39#ibcon#read 5, iclass 28, count 2 2006.239.08:07:09.39#ibcon#about to read 6, iclass 28, count 2 2006.239.08:07:09.39#ibcon#read 6, iclass 28, count 2 2006.239.08:07:09.39#ibcon#end of sib2, iclass 28, count 2 2006.239.08:07:09.39#ibcon#*mode == 0, iclass 28, count 2 2006.239.08:07:09.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.08:07:09.39#ibcon#[25=AT05-08\r\n] 2006.239.08:07:09.39#ibcon#*before write, iclass 28, count 2 2006.239.08:07:09.39#ibcon#enter sib2, iclass 28, count 2 2006.239.08:07:09.39#ibcon#flushed, iclass 28, count 2 2006.239.08:07:09.39#ibcon#about to write, iclass 28, count 2 2006.239.08:07:09.39#ibcon#wrote, iclass 28, count 2 2006.239.08:07:09.39#ibcon#about to read 3, iclass 28, count 2 2006.239.08:07:09.42#ibcon#read 3, iclass 28, count 2 2006.239.08:07:09.42#ibcon#about to read 4, iclass 28, count 2 2006.239.08:07:09.42#ibcon#read 4, iclass 28, count 2 2006.239.08:07:09.42#ibcon#about to read 5, iclass 28, count 2 2006.239.08:07:09.42#ibcon#read 5, iclass 28, count 2 2006.239.08:07:09.42#ibcon#about to read 6, iclass 28, count 2 2006.239.08:07:09.42#ibcon#read 6, iclass 28, count 2 2006.239.08:07:09.42#ibcon#end of sib2, iclass 28, count 2 2006.239.08:07:09.42#ibcon#*after write, iclass 28, count 2 2006.239.08:07:09.42#ibcon#*before return 0, iclass 28, count 2 2006.239.08:07:09.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:09.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:09.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.08:07:09.42#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:09.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:09.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:09.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:09.54#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:07:09.54#ibcon#first serial, iclass 28, count 0 2006.239.08:07:09.54#ibcon#enter sib2, iclass 28, count 0 2006.239.08:07:09.54#ibcon#flushed, iclass 28, count 0 2006.239.08:07:09.54#ibcon#about to write, iclass 28, count 0 2006.239.08:07:09.54#ibcon#wrote, iclass 28, count 0 2006.239.08:07:09.54#ibcon#about to read 3, iclass 28, count 0 2006.239.08:07:09.56#ibcon#read 3, iclass 28, count 0 2006.239.08:07:09.56#ibcon#about to read 4, iclass 28, count 0 2006.239.08:07:09.56#ibcon#read 4, iclass 28, count 0 2006.239.08:07:09.56#ibcon#about to read 5, iclass 28, count 0 2006.239.08:07:09.56#ibcon#read 5, iclass 28, count 0 2006.239.08:07:09.56#ibcon#about to read 6, iclass 28, count 0 2006.239.08:07:09.56#ibcon#read 6, iclass 28, count 0 2006.239.08:07:09.56#ibcon#end of sib2, iclass 28, count 0 2006.239.08:07:09.56#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:07:09.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:07:09.56#ibcon#[25=USB\r\n] 2006.239.08:07:09.56#ibcon#*before write, iclass 28, count 0 2006.239.08:07:09.56#ibcon#enter sib2, iclass 28, count 0 2006.239.08:07:09.56#ibcon#flushed, iclass 28, count 0 2006.239.08:07:09.56#ibcon#about to write, iclass 28, count 0 2006.239.08:07:09.56#ibcon#wrote, iclass 28, count 0 2006.239.08:07:09.56#ibcon#about to read 3, iclass 28, count 0 2006.239.08:07:09.59#ibcon#read 3, iclass 28, count 0 2006.239.08:07:09.59#ibcon#about to read 4, iclass 28, count 0 2006.239.08:07:09.59#ibcon#read 4, iclass 28, count 0 2006.239.08:07:09.59#ibcon#about to read 5, iclass 28, count 0 2006.239.08:07:09.59#ibcon#read 5, iclass 28, count 0 2006.239.08:07:09.59#ibcon#about to read 6, iclass 28, count 0 2006.239.08:07:09.59#ibcon#read 6, iclass 28, count 0 2006.239.08:07:09.59#ibcon#end of sib2, iclass 28, count 0 2006.239.08:07:09.59#ibcon#*after write, iclass 28, count 0 2006.239.08:07:09.59#ibcon#*before return 0, iclass 28, count 0 2006.239.08:07:09.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:09.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:09.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:07:09.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:07:09.59$vc4f8/valo=6,772.99 2006.239.08:07:09.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.08:07:09.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.08:07:09.59#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:09.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:09.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:09.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:09.59#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:07:09.59#ibcon#first serial, iclass 30, count 0 2006.239.08:07:09.59#ibcon#enter sib2, iclass 30, count 0 2006.239.08:07:09.59#ibcon#flushed, iclass 30, count 0 2006.239.08:07:09.59#ibcon#about to write, iclass 30, count 0 2006.239.08:07:09.59#ibcon#wrote, iclass 30, count 0 2006.239.08:07:09.59#ibcon#about to read 3, iclass 30, count 0 2006.239.08:07:09.61#ibcon#read 3, iclass 30, count 0 2006.239.08:07:09.61#ibcon#about to read 4, iclass 30, count 0 2006.239.08:07:09.61#ibcon#read 4, iclass 30, count 0 2006.239.08:07:09.61#ibcon#about to read 5, iclass 30, count 0 2006.239.08:07:09.61#ibcon#read 5, iclass 30, count 0 2006.239.08:07:09.61#ibcon#about to read 6, iclass 30, count 0 2006.239.08:07:09.61#ibcon#read 6, iclass 30, count 0 2006.239.08:07:09.61#ibcon#end of sib2, iclass 30, count 0 2006.239.08:07:09.61#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:07:09.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:07:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:07:09.61#ibcon#*before write, iclass 30, count 0 2006.239.08:07:09.61#ibcon#enter sib2, iclass 30, count 0 2006.239.08:07:09.61#ibcon#flushed, iclass 30, count 0 2006.239.08:07:09.61#ibcon#about to write, iclass 30, count 0 2006.239.08:07:09.61#ibcon#wrote, iclass 30, count 0 2006.239.08:07:09.61#ibcon#about to read 3, iclass 30, count 0 2006.239.08:07:09.65#ibcon#read 3, iclass 30, count 0 2006.239.08:07:09.65#ibcon#about to read 4, iclass 30, count 0 2006.239.08:07:09.65#ibcon#read 4, iclass 30, count 0 2006.239.08:07:09.65#ibcon#about to read 5, iclass 30, count 0 2006.239.08:07:09.65#ibcon#read 5, iclass 30, count 0 2006.239.08:07:09.65#ibcon#about to read 6, iclass 30, count 0 2006.239.08:07:09.65#ibcon#read 6, iclass 30, count 0 2006.239.08:07:09.65#ibcon#end of sib2, iclass 30, count 0 2006.239.08:07:09.65#ibcon#*after write, iclass 30, count 0 2006.239.08:07:09.65#ibcon#*before return 0, iclass 30, count 0 2006.239.08:07:09.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:09.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:09.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:07:09.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:07:09.65$vc4f8/va=6,7 2006.239.08:07:09.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.08:07:09.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.08:07:09.65#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:09.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:09.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:09.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:09.71#ibcon#enter wrdev, iclass 32, count 2 2006.239.08:07:09.71#ibcon#first serial, iclass 32, count 2 2006.239.08:07:09.71#ibcon#enter sib2, iclass 32, count 2 2006.239.08:07:09.71#ibcon#flushed, iclass 32, count 2 2006.239.08:07:09.71#ibcon#about to write, iclass 32, count 2 2006.239.08:07:09.71#ibcon#wrote, iclass 32, count 2 2006.239.08:07:09.71#ibcon#about to read 3, iclass 32, count 2 2006.239.08:07:09.73#ibcon#read 3, iclass 32, count 2 2006.239.08:07:09.73#ibcon#about to read 4, iclass 32, count 2 2006.239.08:07:09.73#ibcon#read 4, iclass 32, count 2 2006.239.08:07:09.73#ibcon#about to read 5, iclass 32, count 2 2006.239.08:07:09.73#ibcon#read 5, iclass 32, count 2 2006.239.08:07:09.73#ibcon#about to read 6, iclass 32, count 2 2006.239.08:07:09.73#ibcon#read 6, iclass 32, count 2 2006.239.08:07:09.73#ibcon#end of sib2, iclass 32, count 2 2006.239.08:07:09.73#ibcon#*mode == 0, iclass 32, count 2 2006.239.08:07:09.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.08:07:09.73#ibcon#[25=AT06-07\r\n] 2006.239.08:07:09.73#ibcon#*before write, iclass 32, count 2 2006.239.08:07:09.73#ibcon#enter sib2, iclass 32, count 2 2006.239.08:07:09.73#ibcon#flushed, iclass 32, count 2 2006.239.08:07:09.73#ibcon#about to write, iclass 32, count 2 2006.239.08:07:09.73#ibcon#wrote, iclass 32, count 2 2006.239.08:07:09.73#ibcon#about to read 3, iclass 32, count 2 2006.239.08:07:09.76#ibcon#read 3, iclass 32, count 2 2006.239.08:07:09.76#ibcon#about to read 4, iclass 32, count 2 2006.239.08:07:09.76#ibcon#read 4, iclass 32, count 2 2006.239.08:07:09.76#ibcon#about to read 5, iclass 32, count 2 2006.239.08:07:09.76#ibcon#read 5, iclass 32, count 2 2006.239.08:07:09.76#ibcon#about to read 6, iclass 32, count 2 2006.239.08:07:09.76#ibcon#read 6, iclass 32, count 2 2006.239.08:07:09.76#ibcon#end of sib2, iclass 32, count 2 2006.239.08:07:09.76#ibcon#*after write, iclass 32, count 2 2006.239.08:07:09.76#ibcon#*before return 0, iclass 32, count 2 2006.239.08:07:09.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:09.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:09.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.08:07:09.76#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:09.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:09.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:09.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:09.88#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:07:09.88#ibcon#first serial, iclass 32, count 0 2006.239.08:07:09.88#ibcon#enter sib2, iclass 32, count 0 2006.239.08:07:09.88#ibcon#flushed, iclass 32, count 0 2006.239.08:07:09.88#ibcon#about to write, iclass 32, count 0 2006.239.08:07:09.88#ibcon#wrote, iclass 32, count 0 2006.239.08:07:09.88#ibcon#about to read 3, iclass 32, count 0 2006.239.08:07:09.90#ibcon#read 3, iclass 32, count 0 2006.239.08:07:09.90#ibcon#about to read 4, iclass 32, count 0 2006.239.08:07:09.90#ibcon#read 4, iclass 32, count 0 2006.239.08:07:09.90#ibcon#about to read 5, iclass 32, count 0 2006.239.08:07:09.90#ibcon#read 5, iclass 32, count 0 2006.239.08:07:09.90#ibcon#about to read 6, iclass 32, count 0 2006.239.08:07:09.90#ibcon#read 6, iclass 32, count 0 2006.239.08:07:09.90#ibcon#end of sib2, iclass 32, count 0 2006.239.08:07:09.90#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:07:09.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:07:09.90#ibcon#[25=USB\r\n] 2006.239.08:07:09.90#ibcon#*before write, iclass 32, count 0 2006.239.08:07:09.90#ibcon#enter sib2, iclass 32, count 0 2006.239.08:07:09.90#ibcon#flushed, iclass 32, count 0 2006.239.08:07:09.90#ibcon#about to write, iclass 32, count 0 2006.239.08:07:09.90#ibcon#wrote, iclass 32, count 0 2006.239.08:07:09.90#ibcon#about to read 3, iclass 32, count 0 2006.239.08:07:09.93#ibcon#read 3, iclass 32, count 0 2006.239.08:07:09.93#ibcon#about to read 4, iclass 32, count 0 2006.239.08:07:09.93#ibcon#read 4, iclass 32, count 0 2006.239.08:07:09.93#ibcon#about to read 5, iclass 32, count 0 2006.239.08:07:09.93#ibcon#read 5, iclass 32, count 0 2006.239.08:07:09.93#ibcon#about to read 6, iclass 32, count 0 2006.239.08:07:09.93#ibcon#read 6, iclass 32, count 0 2006.239.08:07:09.93#ibcon#end of sib2, iclass 32, count 0 2006.239.08:07:09.93#ibcon#*after write, iclass 32, count 0 2006.239.08:07:09.93#ibcon#*before return 0, iclass 32, count 0 2006.239.08:07:09.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:09.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:09.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:07:09.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:07:09.93$vc4f8/valo=7,832.99 2006.239.08:07:09.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.08:07:09.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.08:07:09.93#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:09.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:09.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:09.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:09.93#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:07:09.93#ibcon#first serial, iclass 34, count 0 2006.239.08:07:09.93#ibcon#enter sib2, iclass 34, count 0 2006.239.08:07:09.93#ibcon#flushed, iclass 34, count 0 2006.239.08:07:09.93#ibcon#about to write, iclass 34, count 0 2006.239.08:07:09.93#ibcon#wrote, iclass 34, count 0 2006.239.08:07:09.93#ibcon#about to read 3, iclass 34, count 0 2006.239.08:07:09.95#ibcon#read 3, iclass 34, count 0 2006.239.08:07:09.95#ibcon#about to read 4, iclass 34, count 0 2006.239.08:07:09.95#ibcon#read 4, iclass 34, count 0 2006.239.08:07:09.95#ibcon#about to read 5, iclass 34, count 0 2006.239.08:07:09.95#ibcon#read 5, iclass 34, count 0 2006.239.08:07:09.95#ibcon#about to read 6, iclass 34, count 0 2006.239.08:07:09.95#ibcon#read 6, iclass 34, count 0 2006.239.08:07:09.95#ibcon#end of sib2, iclass 34, count 0 2006.239.08:07:09.95#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:07:09.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:07:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:07:09.95#ibcon#*before write, iclass 34, count 0 2006.239.08:07:09.95#ibcon#enter sib2, iclass 34, count 0 2006.239.08:07:09.95#ibcon#flushed, iclass 34, count 0 2006.239.08:07:09.95#ibcon#about to write, iclass 34, count 0 2006.239.08:07:09.95#ibcon#wrote, iclass 34, count 0 2006.239.08:07:09.95#ibcon#about to read 3, iclass 34, count 0 2006.239.08:07:09.99#ibcon#read 3, iclass 34, count 0 2006.239.08:07:09.99#ibcon#about to read 4, iclass 34, count 0 2006.239.08:07:09.99#ibcon#read 4, iclass 34, count 0 2006.239.08:07:09.99#ibcon#about to read 5, iclass 34, count 0 2006.239.08:07:09.99#ibcon#read 5, iclass 34, count 0 2006.239.08:07:09.99#ibcon#about to read 6, iclass 34, count 0 2006.239.08:07:09.99#ibcon#read 6, iclass 34, count 0 2006.239.08:07:09.99#ibcon#end of sib2, iclass 34, count 0 2006.239.08:07:09.99#ibcon#*after write, iclass 34, count 0 2006.239.08:07:09.99#ibcon#*before return 0, iclass 34, count 0 2006.239.08:07:09.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:09.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:09.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:07:09.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:07:09.99$vc4f8/va=7,7 2006.239.08:07:09.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.08:07:09.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.08:07:09.99#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:09.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:07:10.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:07:10.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:07:10.05#ibcon#enter wrdev, iclass 36, count 2 2006.239.08:07:10.05#ibcon#first serial, iclass 36, count 2 2006.239.08:07:10.05#ibcon#enter sib2, iclass 36, count 2 2006.239.08:07:10.05#ibcon#flushed, iclass 36, count 2 2006.239.08:07:10.05#ibcon#about to write, iclass 36, count 2 2006.239.08:07:10.05#ibcon#wrote, iclass 36, count 2 2006.239.08:07:10.05#ibcon#about to read 3, iclass 36, count 2 2006.239.08:07:10.07#ibcon#read 3, iclass 36, count 2 2006.239.08:07:10.07#ibcon#about to read 4, iclass 36, count 2 2006.239.08:07:10.07#ibcon#read 4, iclass 36, count 2 2006.239.08:07:10.07#ibcon#about to read 5, iclass 36, count 2 2006.239.08:07:10.07#ibcon#read 5, iclass 36, count 2 2006.239.08:07:10.07#ibcon#about to read 6, iclass 36, count 2 2006.239.08:07:10.07#ibcon#read 6, iclass 36, count 2 2006.239.08:07:10.07#ibcon#end of sib2, iclass 36, count 2 2006.239.08:07:10.07#ibcon#*mode == 0, iclass 36, count 2 2006.239.08:07:10.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.08:07:10.07#ibcon#[25=AT07-07\r\n] 2006.239.08:07:10.07#ibcon#*before write, iclass 36, count 2 2006.239.08:07:10.07#ibcon#enter sib2, iclass 36, count 2 2006.239.08:07:10.07#ibcon#flushed, iclass 36, count 2 2006.239.08:07:10.07#ibcon#about to write, iclass 36, count 2 2006.239.08:07:10.07#ibcon#wrote, iclass 36, count 2 2006.239.08:07:10.07#ibcon#about to read 3, iclass 36, count 2 2006.239.08:07:10.10#ibcon#read 3, iclass 36, count 2 2006.239.08:07:10.10#ibcon#about to read 4, iclass 36, count 2 2006.239.08:07:10.10#ibcon#read 4, iclass 36, count 2 2006.239.08:07:10.10#ibcon#about to read 5, iclass 36, count 2 2006.239.08:07:10.10#ibcon#read 5, iclass 36, count 2 2006.239.08:07:10.10#ibcon#about to read 6, iclass 36, count 2 2006.239.08:07:10.10#ibcon#read 6, iclass 36, count 2 2006.239.08:07:10.10#ibcon#end of sib2, iclass 36, count 2 2006.239.08:07:10.10#ibcon#*after write, iclass 36, count 2 2006.239.08:07:10.10#ibcon#*before return 0, iclass 36, count 2 2006.239.08:07:10.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:07:10.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:07:10.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.08:07:10.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:10.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:07:10.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:07:10.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:07:10.22#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:07:10.22#ibcon#first serial, iclass 36, count 0 2006.239.08:07:10.22#ibcon#enter sib2, iclass 36, count 0 2006.239.08:07:10.22#ibcon#flushed, iclass 36, count 0 2006.239.08:07:10.22#ibcon#about to write, iclass 36, count 0 2006.239.08:07:10.22#ibcon#wrote, iclass 36, count 0 2006.239.08:07:10.22#ibcon#about to read 3, iclass 36, count 0 2006.239.08:07:10.24#ibcon#read 3, iclass 36, count 0 2006.239.08:07:10.24#ibcon#about to read 4, iclass 36, count 0 2006.239.08:07:10.24#ibcon#read 4, iclass 36, count 0 2006.239.08:07:10.24#ibcon#about to read 5, iclass 36, count 0 2006.239.08:07:10.24#ibcon#read 5, iclass 36, count 0 2006.239.08:07:10.24#ibcon#about to read 6, iclass 36, count 0 2006.239.08:07:10.24#ibcon#read 6, iclass 36, count 0 2006.239.08:07:10.24#ibcon#end of sib2, iclass 36, count 0 2006.239.08:07:10.24#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:07:10.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:07:10.24#ibcon#[25=USB\r\n] 2006.239.08:07:10.24#ibcon#*before write, iclass 36, count 0 2006.239.08:07:10.24#ibcon#enter sib2, iclass 36, count 0 2006.239.08:07:10.24#ibcon#flushed, iclass 36, count 0 2006.239.08:07:10.24#ibcon#about to write, iclass 36, count 0 2006.239.08:07:10.24#ibcon#wrote, iclass 36, count 0 2006.239.08:07:10.24#ibcon#about to read 3, iclass 36, count 0 2006.239.08:07:10.27#ibcon#read 3, iclass 36, count 0 2006.239.08:07:10.27#ibcon#about to read 4, iclass 36, count 0 2006.239.08:07:10.27#ibcon#read 4, iclass 36, count 0 2006.239.08:07:10.27#ibcon#about to read 5, iclass 36, count 0 2006.239.08:07:10.27#ibcon#read 5, iclass 36, count 0 2006.239.08:07:10.27#ibcon#about to read 6, iclass 36, count 0 2006.239.08:07:10.27#ibcon#read 6, iclass 36, count 0 2006.239.08:07:10.27#ibcon#end of sib2, iclass 36, count 0 2006.239.08:07:10.27#ibcon#*after write, iclass 36, count 0 2006.239.08:07:10.27#ibcon#*before return 0, iclass 36, count 0 2006.239.08:07:10.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:07:10.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:07:10.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:07:10.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:07:10.27$vc4f8/valo=8,852.99 2006.239.08:07:10.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.08:07:10.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.08:07:10.27#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:10.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:07:10.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:07:10.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:07:10.27#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:07:10.27#ibcon#first serial, iclass 38, count 0 2006.239.08:07:10.27#ibcon#enter sib2, iclass 38, count 0 2006.239.08:07:10.27#ibcon#flushed, iclass 38, count 0 2006.239.08:07:10.27#ibcon#about to write, iclass 38, count 0 2006.239.08:07:10.27#ibcon#wrote, iclass 38, count 0 2006.239.08:07:10.27#ibcon#about to read 3, iclass 38, count 0 2006.239.08:07:10.29#ibcon#read 3, iclass 38, count 0 2006.239.08:07:10.29#ibcon#about to read 4, iclass 38, count 0 2006.239.08:07:10.29#ibcon#read 4, iclass 38, count 0 2006.239.08:07:10.29#ibcon#about to read 5, iclass 38, count 0 2006.239.08:07:10.29#ibcon#read 5, iclass 38, count 0 2006.239.08:07:10.29#ibcon#about to read 6, iclass 38, count 0 2006.239.08:07:10.29#ibcon#read 6, iclass 38, count 0 2006.239.08:07:10.29#ibcon#end of sib2, iclass 38, count 0 2006.239.08:07:10.29#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:07:10.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:07:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:07:10.29#ibcon#*before write, iclass 38, count 0 2006.239.08:07:10.29#ibcon#enter sib2, iclass 38, count 0 2006.239.08:07:10.29#ibcon#flushed, iclass 38, count 0 2006.239.08:07:10.29#ibcon#about to write, iclass 38, count 0 2006.239.08:07:10.29#ibcon#wrote, iclass 38, count 0 2006.239.08:07:10.29#ibcon#about to read 3, iclass 38, count 0 2006.239.08:07:10.33#ibcon#read 3, iclass 38, count 0 2006.239.08:07:10.33#ibcon#about to read 4, iclass 38, count 0 2006.239.08:07:10.33#ibcon#read 4, iclass 38, count 0 2006.239.08:07:10.33#ibcon#about to read 5, iclass 38, count 0 2006.239.08:07:10.33#ibcon#read 5, iclass 38, count 0 2006.239.08:07:10.33#ibcon#about to read 6, iclass 38, count 0 2006.239.08:07:10.33#ibcon#read 6, iclass 38, count 0 2006.239.08:07:10.33#ibcon#end of sib2, iclass 38, count 0 2006.239.08:07:10.33#ibcon#*after write, iclass 38, count 0 2006.239.08:07:10.33#ibcon#*before return 0, iclass 38, count 0 2006.239.08:07:10.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:07:10.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:07:10.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:07:10.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:07:10.33$vc4f8/va=8,7 2006.239.08:07:10.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.08:07:10.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.08:07:10.33#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:10.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:07:10.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:07:10.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:07:10.39#ibcon#enter wrdev, iclass 40, count 2 2006.239.08:07:10.39#ibcon#first serial, iclass 40, count 2 2006.239.08:07:10.39#ibcon#enter sib2, iclass 40, count 2 2006.239.08:07:10.39#ibcon#flushed, iclass 40, count 2 2006.239.08:07:10.39#ibcon#about to write, iclass 40, count 2 2006.239.08:07:10.39#ibcon#wrote, iclass 40, count 2 2006.239.08:07:10.39#ibcon#about to read 3, iclass 40, count 2 2006.239.08:07:10.41#ibcon#read 3, iclass 40, count 2 2006.239.08:07:10.41#ibcon#about to read 4, iclass 40, count 2 2006.239.08:07:10.41#ibcon#read 4, iclass 40, count 2 2006.239.08:07:10.41#ibcon#about to read 5, iclass 40, count 2 2006.239.08:07:10.41#ibcon#read 5, iclass 40, count 2 2006.239.08:07:10.41#ibcon#about to read 6, iclass 40, count 2 2006.239.08:07:10.41#ibcon#read 6, iclass 40, count 2 2006.239.08:07:10.41#ibcon#end of sib2, iclass 40, count 2 2006.239.08:07:10.41#ibcon#*mode == 0, iclass 40, count 2 2006.239.08:07:10.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.08:07:10.41#ibcon#[25=AT08-07\r\n] 2006.239.08:07:10.41#ibcon#*before write, iclass 40, count 2 2006.239.08:07:10.41#ibcon#enter sib2, iclass 40, count 2 2006.239.08:07:10.41#ibcon#flushed, iclass 40, count 2 2006.239.08:07:10.41#ibcon#about to write, iclass 40, count 2 2006.239.08:07:10.41#ibcon#wrote, iclass 40, count 2 2006.239.08:07:10.41#ibcon#about to read 3, iclass 40, count 2 2006.239.08:07:10.44#ibcon#read 3, iclass 40, count 2 2006.239.08:07:10.44#ibcon#about to read 4, iclass 40, count 2 2006.239.08:07:10.44#ibcon#read 4, iclass 40, count 2 2006.239.08:07:10.44#ibcon#about to read 5, iclass 40, count 2 2006.239.08:07:10.44#ibcon#read 5, iclass 40, count 2 2006.239.08:07:10.44#ibcon#about to read 6, iclass 40, count 2 2006.239.08:07:10.44#ibcon#read 6, iclass 40, count 2 2006.239.08:07:10.44#ibcon#end of sib2, iclass 40, count 2 2006.239.08:07:10.44#ibcon#*after write, iclass 40, count 2 2006.239.08:07:10.44#ibcon#*before return 0, iclass 40, count 2 2006.239.08:07:10.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:07:10.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:07:10.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.08:07:10.44#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:10.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:07:10.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:07:10.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:07:10.56#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:07:10.56#ibcon#first serial, iclass 40, count 0 2006.239.08:07:10.56#ibcon#enter sib2, iclass 40, count 0 2006.239.08:07:10.56#ibcon#flushed, iclass 40, count 0 2006.239.08:07:10.56#ibcon#about to write, iclass 40, count 0 2006.239.08:07:10.56#ibcon#wrote, iclass 40, count 0 2006.239.08:07:10.56#ibcon#about to read 3, iclass 40, count 0 2006.239.08:07:10.58#ibcon#read 3, iclass 40, count 0 2006.239.08:07:10.58#ibcon#about to read 4, iclass 40, count 0 2006.239.08:07:10.58#ibcon#read 4, iclass 40, count 0 2006.239.08:07:10.58#ibcon#about to read 5, iclass 40, count 0 2006.239.08:07:10.58#ibcon#read 5, iclass 40, count 0 2006.239.08:07:10.58#ibcon#about to read 6, iclass 40, count 0 2006.239.08:07:10.58#ibcon#read 6, iclass 40, count 0 2006.239.08:07:10.58#ibcon#end of sib2, iclass 40, count 0 2006.239.08:07:10.58#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:07:10.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:07:10.58#ibcon#[25=USB\r\n] 2006.239.08:07:10.58#ibcon#*before write, iclass 40, count 0 2006.239.08:07:10.58#ibcon#enter sib2, iclass 40, count 0 2006.239.08:07:10.58#ibcon#flushed, iclass 40, count 0 2006.239.08:07:10.58#ibcon#about to write, iclass 40, count 0 2006.239.08:07:10.58#ibcon#wrote, iclass 40, count 0 2006.239.08:07:10.58#ibcon#about to read 3, iclass 40, count 0 2006.239.08:07:10.61#ibcon#read 3, iclass 40, count 0 2006.239.08:07:10.61#ibcon#about to read 4, iclass 40, count 0 2006.239.08:07:10.61#ibcon#read 4, iclass 40, count 0 2006.239.08:07:10.61#ibcon#about to read 5, iclass 40, count 0 2006.239.08:07:10.61#ibcon#read 5, iclass 40, count 0 2006.239.08:07:10.61#ibcon#about to read 6, iclass 40, count 0 2006.239.08:07:10.61#ibcon#read 6, iclass 40, count 0 2006.239.08:07:10.61#ibcon#end of sib2, iclass 40, count 0 2006.239.08:07:10.61#ibcon#*after write, iclass 40, count 0 2006.239.08:07:10.61#ibcon#*before return 0, iclass 40, count 0 2006.239.08:07:10.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:07:10.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:07:10.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:07:10.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:07:10.61$vc4f8/vblo=1,632.99 2006.239.08:07:10.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.08:07:10.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.08:07:10.61#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:10.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:07:10.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:07:10.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:07:10.61#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:07:10.61#ibcon#first serial, iclass 4, count 0 2006.239.08:07:10.61#ibcon#enter sib2, iclass 4, count 0 2006.239.08:07:10.61#ibcon#flushed, iclass 4, count 0 2006.239.08:07:10.61#ibcon#about to write, iclass 4, count 0 2006.239.08:07:10.61#ibcon#wrote, iclass 4, count 0 2006.239.08:07:10.61#ibcon#about to read 3, iclass 4, count 0 2006.239.08:07:10.63#ibcon#read 3, iclass 4, count 0 2006.239.08:07:10.63#ibcon#about to read 4, iclass 4, count 0 2006.239.08:07:10.63#ibcon#read 4, iclass 4, count 0 2006.239.08:07:10.63#ibcon#about to read 5, iclass 4, count 0 2006.239.08:07:10.63#ibcon#read 5, iclass 4, count 0 2006.239.08:07:10.63#ibcon#about to read 6, iclass 4, count 0 2006.239.08:07:10.63#ibcon#read 6, iclass 4, count 0 2006.239.08:07:10.63#ibcon#end of sib2, iclass 4, count 0 2006.239.08:07:10.63#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:07:10.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:07:10.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:07:10.63#ibcon#*before write, iclass 4, count 0 2006.239.08:07:10.63#ibcon#enter sib2, iclass 4, count 0 2006.239.08:07:10.63#ibcon#flushed, iclass 4, count 0 2006.239.08:07:10.63#ibcon#about to write, iclass 4, count 0 2006.239.08:07:10.63#ibcon#wrote, iclass 4, count 0 2006.239.08:07:10.63#ibcon#about to read 3, iclass 4, count 0 2006.239.08:07:10.67#ibcon#read 3, iclass 4, count 0 2006.239.08:07:10.67#ibcon#about to read 4, iclass 4, count 0 2006.239.08:07:10.67#ibcon#read 4, iclass 4, count 0 2006.239.08:07:10.67#ibcon#about to read 5, iclass 4, count 0 2006.239.08:07:10.67#ibcon#read 5, iclass 4, count 0 2006.239.08:07:10.67#ibcon#about to read 6, iclass 4, count 0 2006.239.08:07:10.67#ibcon#read 6, iclass 4, count 0 2006.239.08:07:10.67#ibcon#end of sib2, iclass 4, count 0 2006.239.08:07:10.67#ibcon#*after write, iclass 4, count 0 2006.239.08:07:10.67#ibcon#*before return 0, iclass 4, count 0 2006.239.08:07:10.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:07:10.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:07:10.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:07:10.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:07:10.67$vc4f8/vb=1,4 2006.239.08:07:10.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.08:07:10.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.08:07:10.67#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:10.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:07:10.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:07:10.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:07:10.67#ibcon#enter wrdev, iclass 6, count 2 2006.239.08:07:10.67#ibcon#first serial, iclass 6, count 2 2006.239.08:07:10.67#ibcon#enter sib2, iclass 6, count 2 2006.239.08:07:10.67#ibcon#flushed, iclass 6, count 2 2006.239.08:07:10.67#ibcon#about to write, iclass 6, count 2 2006.239.08:07:10.67#ibcon#wrote, iclass 6, count 2 2006.239.08:07:10.67#ibcon#about to read 3, iclass 6, count 2 2006.239.08:07:10.69#ibcon#read 3, iclass 6, count 2 2006.239.08:07:10.69#ibcon#about to read 4, iclass 6, count 2 2006.239.08:07:10.69#ibcon#read 4, iclass 6, count 2 2006.239.08:07:10.69#ibcon#about to read 5, iclass 6, count 2 2006.239.08:07:10.69#ibcon#read 5, iclass 6, count 2 2006.239.08:07:10.69#ibcon#about to read 6, iclass 6, count 2 2006.239.08:07:10.69#ibcon#read 6, iclass 6, count 2 2006.239.08:07:10.69#ibcon#end of sib2, iclass 6, count 2 2006.239.08:07:10.69#ibcon#*mode == 0, iclass 6, count 2 2006.239.08:07:10.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.08:07:10.69#ibcon#[27=AT01-04\r\n] 2006.239.08:07:10.69#ibcon#*before write, iclass 6, count 2 2006.239.08:07:10.69#ibcon#enter sib2, iclass 6, count 2 2006.239.08:07:10.69#ibcon#flushed, iclass 6, count 2 2006.239.08:07:10.69#ibcon#about to write, iclass 6, count 2 2006.239.08:07:10.69#ibcon#wrote, iclass 6, count 2 2006.239.08:07:10.69#ibcon#about to read 3, iclass 6, count 2 2006.239.08:07:10.72#ibcon#read 3, iclass 6, count 2 2006.239.08:07:10.72#ibcon#about to read 4, iclass 6, count 2 2006.239.08:07:10.72#ibcon#read 4, iclass 6, count 2 2006.239.08:07:10.72#ibcon#about to read 5, iclass 6, count 2 2006.239.08:07:10.72#ibcon#read 5, iclass 6, count 2 2006.239.08:07:10.72#ibcon#about to read 6, iclass 6, count 2 2006.239.08:07:10.72#ibcon#read 6, iclass 6, count 2 2006.239.08:07:10.72#ibcon#end of sib2, iclass 6, count 2 2006.239.08:07:10.72#ibcon#*after write, iclass 6, count 2 2006.239.08:07:10.72#ibcon#*before return 0, iclass 6, count 2 2006.239.08:07:10.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:07:10.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:07:10.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.08:07:10.72#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:10.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:07:10.84#abcon#<5=/04 2.0 4.0 25.12 801011.6\r\n> 2006.239.08:07:10.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:07:10.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:07:10.84#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:07:10.84#ibcon#first serial, iclass 6, count 0 2006.239.08:07:10.84#ibcon#enter sib2, iclass 6, count 0 2006.239.08:07:10.84#ibcon#flushed, iclass 6, count 0 2006.239.08:07:10.84#ibcon#about to write, iclass 6, count 0 2006.239.08:07:10.84#ibcon#wrote, iclass 6, count 0 2006.239.08:07:10.84#ibcon#about to read 3, iclass 6, count 0 2006.239.08:07:10.86#ibcon#read 3, iclass 6, count 0 2006.239.08:07:10.86#ibcon#about to read 4, iclass 6, count 0 2006.239.08:07:10.86#ibcon#read 4, iclass 6, count 0 2006.239.08:07:10.86#ibcon#about to read 5, iclass 6, count 0 2006.239.08:07:10.86#ibcon#read 5, iclass 6, count 0 2006.239.08:07:10.86#ibcon#about to read 6, iclass 6, count 0 2006.239.08:07:10.86#ibcon#read 6, iclass 6, count 0 2006.239.08:07:10.86#ibcon#end of sib2, iclass 6, count 0 2006.239.08:07:10.86#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:07:10.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:07:10.86#ibcon#[27=USB\r\n] 2006.239.08:07:10.86#ibcon#*before write, iclass 6, count 0 2006.239.08:07:10.86#ibcon#enter sib2, iclass 6, count 0 2006.239.08:07:10.86#ibcon#flushed, iclass 6, count 0 2006.239.08:07:10.86#ibcon#about to write, iclass 6, count 0 2006.239.08:07:10.86#ibcon#wrote, iclass 6, count 0 2006.239.08:07:10.86#ibcon#about to read 3, iclass 6, count 0 2006.239.08:07:10.86#abcon#{5=INTERFACE CLEAR} 2006.239.08:07:10.89#ibcon#read 3, iclass 6, count 0 2006.239.08:07:10.89#ibcon#about to read 4, iclass 6, count 0 2006.239.08:07:10.89#ibcon#read 4, iclass 6, count 0 2006.239.08:07:10.89#ibcon#about to read 5, iclass 6, count 0 2006.239.08:07:10.89#ibcon#read 5, iclass 6, count 0 2006.239.08:07:10.89#ibcon#about to read 6, iclass 6, count 0 2006.239.08:07:10.89#ibcon#read 6, iclass 6, count 0 2006.239.08:07:10.89#ibcon#end of sib2, iclass 6, count 0 2006.239.08:07:10.89#ibcon#*after write, iclass 6, count 0 2006.239.08:07:10.89#ibcon#*before return 0, iclass 6, count 0 2006.239.08:07:10.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:07:10.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:07:10.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:07:10.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:07:10.89$vc4f8/vblo=2,640.99 2006.239.08:07:10.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.08:07:10.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.08:07:10.89#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:10.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:07:10.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:07:10.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:07:10.89#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:07:10.89#ibcon#first serial, iclass 13, count 0 2006.239.08:07:10.89#ibcon#enter sib2, iclass 13, count 0 2006.239.08:07:10.89#ibcon#flushed, iclass 13, count 0 2006.239.08:07:10.89#ibcon#about to write, iclass 13, count 0 2006.239.08:07:10.89#ibcon#wrote, iclass 13, count 0 2006.239.08:07:10.89#ibcon#about to read 3, iclass 13, count 0 2006.239.08:07:10.91#ibcon#read 3, iclass 13, count 0 2006.239.08:07:10.91#ibcon#about to read 4, iclass 13, count 0 2006.239.08:07:10.91#ibcon#read 4, iclass 13, count 0 2006.239.08:07:10.91#ibcon#about to read 5, iclass 13, count 0 2006.239.08:07:10.91#ibcon#read 5, iclass 13, count 0 2006.239.08:07:10.91#ibcon#about to read 6, iclass 13, count 0 2006.239.08:07:10.91#ibcon#read 6, iclass 13, count 0 2006.239.08:07:10.91#ibcon#end of sib2, iclass 13, count 0 2006.239.08:07:10.91#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:07:10.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:07:10.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:07:10.91#ibcon#*before write, iclass 13, count 0 2006.239.08:07:10.91#ibcon#enter sib2, iclass 13, count 0 2006.239.08:07:10.91#ibcon#flushed, iclass 13, count 0 2006.239.08:07:10.91#ibcon#about to write, iclass 13, count 0 2006.239.08:07:10.91#ibcon#wrote, iclass 13, count 0 2006.239.08:07:10.91#ibcon#about to read 3, iclass 13, count 0 2006.239.08:07:10.92#abcon#[5=S1D000X0/0*\r\n] 2006.239.08:07:10.95#ibcon#read 3, iclass 13, count 0 2006.239.08:07:10.95#ibcon#about to read 4, iclass 13, count 0 2006.239.08:07:10.95#ibcon#read 4, iclass 13, count 0 2006.239.08:07:10.95#ibcon#about to read 5, iclass 13, count 0 2006.239.08:07:10.95#ibcon#read 5, iclass 13, count 0 2006.239.08:07:10.95#ibcon#about to read 6, iclass 13, count 0 2006.239.08:07:10.95#ibcon#read 6, iclass 13, count 0 2006.239.08:07:10.95#ibcon#end of sib2, iclass 13, count 0 2006.239.08:07:10.95#ibcon#*after write, iclass 13, count 0 2006.239.08:07:10.95#ibcon#*before return 0, iclass 13, count 0 2006.239.08:07:10.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:07:10.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:07:10.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:07:10.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:07:10.95$vc4f8/vb=2,4 2006.239.08:07:10.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.08:07:10.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.08:07:10.95#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:10.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:11.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:11.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:11.01#ibcon#enter wrdev, iclass 16, count 2 2006.239.08:07:11.01#ibcon#first serial, iclass 16, count 2 2006.239.08:07:11.01#ibcon#enter sib2, iclass 16, count 2 2006.239.08:07:11.01#ibcon#flushed, iclass 16, count 2 2006.239.08:07:11.01#ibcon#about to write, iclass 16, count 2 2006.239.08:07:11.01#ibcon#wrote, iclass 16, count 2 2006.239.08:07:11.01#ibcon#about to read 3, iclass 16, count 2 2006.239.08:07:11.03#ibcon#read 3, iclass 16, count 2 2006.239.08:07:11.03#ibcon#about to read 4, iclass 16, count 2 2006.239.08:07:11.03#ibcon#read 4, iclass 16, count 2 2006.239.08:07:11.03#ibcon#about to read 5, iclass 16, count 2 2006.239.08:07:11.03#ibcon#read 5, iclass 16, count 2 2006.239.08:07:11.03#ibcon#about to read 6, iclass 16, count 2 2006.239.08:07:11.03#ibcon#read 6, iclass 16, count 2 2006.239.08:07:11.03#ibcon#end of sib2, iclass 16, count 2 2006.239.08:07:11.03#ibcon#*mode == 0, iclass 16, count 2 2006.239.08:07:11.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.08:07:11.03#ibcon#[27=AT02-04\r\n] 2006.239.08:07:11.03#ibcon#*before write, iclass 16, count 2 2006.239.08:07:11.03#ibcon#enter sib2, iclass 16, count 2 2006.239.08:07:11.03#ibcon#flushed, iclass 16, count 2 2006.239.08:07:11.03#ibcon#about to write, iclass 16, count 2 2006.239.08:07:11.03#ibcon#wrote, iclass 16, count 2 2006.239.08:07:11.03#ibcon#about to read 3, iclass 16, count 2 2006.239.08:07:11.06#ibcon#read 3, iclass 16, count 2 2006.239.08:07:11.06#ibcon#about to read 4, iclass 16, count 2 2006.239.08:07:11.06#ibcon#read 4, iclass 16, count 2 2006.239.08:07:11.06#ibcon#about to read 5, iclass 16, count 2 2006.239.08:07:11.06#ibcon#read 5, iclass 16, count 2 2006.239.08:07:11.06#ibcon#about to read 6, iclass 16, count 2 2006.239.08:07:11.06#ibcon#read 6, iclass 16, count 2 2006.239.08:07:11.06#ibcon#end of sib2, iclass 16, count 2 2006.239.08:07:11.06#ibcon#*after write, iclass 16, count 2 2006.239.08:07:11.06#ibcon#*before return 0, iclass 16, count 2 2006.239.08:07:11.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:11.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:07:11.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.08:07:11.06#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:11.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:11.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:11.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:11.18#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:07:11.18#ibcon#first serial, iclass 16, count 0 2006.239.08:07:11.18#ibcon#enter sib2, iclass 16, count 0 2006.239.08:07:11.18#ibcon#flushed, iclass 16, count 0 2006.239.08:07:11.18#ibcon#about to write, iclass 16, count 0 2006.239.08:07:11.18#ibcon#wrote, iclass 16, count 0 2006.239.08:07:11.18#ibcon#about to read 3, iclass 16, count 0 2006.239.08:07:11.20#ibcon#read 3, iclass 16, count 0 2006.239.08:07:11.20#ibcon#about to read 4, iclass 16, count 0 2006.239.08:07:11.20#ibcon#read 4, iclass 16, count 0 2006.239.08:07:11.20#ibcon#about to read 5, iclass 16, count 0 2006.239.08:07:11.20#ibcon#read 5, iclass 16, count 0 2006.239.08:07:11.20#ibcon#about to read 6, iclass 16, count 0 2006.239.08:07:11.20#ibcon#read 6, iclass 16, count 0 2006.239.08:07:11.20#ibcon#end of sib2, iclass 16, count 0 2006.239.08:07:11.20#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:07:11.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:07:11.20#ibcon#[27=USB\r\n] 2006.239.08:07:11.20#ibcon#*before write, iclass 16, count 0 2006.239.08:07:11.20#ibcon#enter sib2, iclass 16, count 0 2006.239.08:07:11.20#ibcon#flushed, iclass 16, count 0 2006.239.08:07:11.20#ibcon#about to write, iclass 16, count 0 2006.239.08:07:11.20#ibcon#wrote, iclass 16, count 0 2006.239.08:07:11.20#ibcon#about to read 3, iclass 16, count 0 2006.239.08:07:11.23#ibcon#read 3, iclass 16, count 0 2006.239.08:07:11.23#ibcon#about to read 4, iclass 16, count 0 2006.239.08:07:11.23#ibcon#read 4, iclass 16, count 0 2006.239.08:07:11.23#ibcon#about to read 5, iclass 16, count 0 2006.239.08:07:11.23#ibcon#read 5, iclass 16, count 0 2006.239.08:07:11.23#ibcon#about to read 6, iclass 16, count 0 2006.239.08:07:11.23#ibcon#read 6, iclass 16, count 0 2006.239.08:07:11.23#ibcon#end of sib2, iclass 16, count 0 2006.239.08:07:11.23#ibcon#*after write, iclass 16, count 0 2006.239.08:07:11.23#ibcon#*before return 0, iclass 16, count 0 2006.239.08:07:11.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:11.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:07:11.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:07:11.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:07:11.23$vc4f8/vblo=3,656.99 2006.239.08:07:11.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:07:11.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:07:11.23#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:11.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:11.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:11.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:11.23#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:07:11.23#ibcon#first serial, iclass 18, count 0 2006.239.08:07:11.23#ibcon#enter sib2, iclass 18, count 0 2006.239.08:07:11.23#ibcon#flushed, iclass 18, count 0 2006.239.08:07:11.23#ibcon#about to write, iclass 18, count 0 2006.239.08:07:11.23#ibcon#wrote, iclass 18, count 0 2006.239.08:07:11.23#ibcon#about to read 3, iclass 18, count 0 2006.239.08:07:11.25#ibcon#read 3, iclass 18, count 0 2006.239.08:07:11.25#ibcon#about to read 4, iclass 18, count 0 2006.239.08:07:11.25#ibcon#read 4, iclass 18, count 0 2006.239.08:07:11.25#ibcon#about to read 5, iclass 18, count 0 2006.239.08:07:11.25#ibcon#read 5, iclass 18, count 0 2006.239.08:07:11.25#ibcon#about to read 6, iclass 18, count 0 2006.239.08:07:11.25#ibcon#read 6, iclass 18, count 0 2006.239.08:07:11.25#ibcon#end of sib2, iclass 18, count 0 2006.239.08:07:11.25#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:07:11.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:07:11.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:07:11.25#ibcon#*before write, iclass 18, count 0 2006.239.08:07:11.25#ibcon#enter sib2, iclass 18, count 0 2006.239.08:07:11.25#ibcon#flushed, iclass 18, count 0 2006.239.08:07:11.25#ibcon#about to write, iclass 18, count 0 2006.239.08:07:11.25#ibcon#wrote, iclass 18, count 0 2006.239.08:07:11.25#ibcon#about to read 3, iclass 18, count 0 2006.239.08:07:11.29#ibcon#read 3, iclass 18, count 0 2006.239.08:07:11.29#ibcon#about to read 4, iclass 18, count 0 2006.239.08:07:11.29#ibcon#read 4, iclass 18, count 0 2006.239.08:07:11.29#ibcon#about to read 5, iclass 18, count 0 2006.239.08:07:11.29#ibcon#read 5, iclass 18, count 0 2006.239.08:07:11.29#ibcon#about to read 6, iclass 18, count 0 2006.239.08:07:11.29#ibcon#read 6, iclass 18, count 0 2006.239.08:07:11.29#ibcon#end of sib2, iclass 18, count 0 2006.239.08:07:11.29#ibcon#*after write, iclass 18, count 0 2006.239.08:07:11.29#ibcon#*before return 0, iclass 18, count 0 2006.239.08:07:11.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:11.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:07:11.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:07:11.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:07:11.29$vc4f8/vb=3,4 2006.239.08:07:11.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.08:07:11.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.08:07:11.29#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:11.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:11.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:11.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:11.35#ibcon#enter wrdev, iclass 20, count 2 2006.239.08:07:11.35#ibcon#first serial, iclass 20, count 2 2006.239.08:07:11.35#ibcon#enter sib2, iclass 20, count 2 2006.239.08:07:11.35#ibcon#flushed, iclass 20, count 2 2006.239.08:07:11.35#ibcon#about to write, iclass 20, count 2 2006.239.08:07:11.35#ibcon#wrote, iclass 20, count 2 2006.239.08:07:11.35#ibcon#about to read 3, iclass 20, count 2 2006.239.08:07:11.37#ibcon#read 3, iclass 20, count 2 2006.239.08:07:11.37#ibcon#about to read 4, iclass 20, count 2 2006.239.08:07:11.37#ibcon#read 4, iclass 20, count 2 2006.239.08:07:11.37#ibcon#about to read 5, iclass 20, count 2 2006.239.08:07:11.37#ibcon#read 5, iclass 20, count 2 2006.239.08:07:11.37#ibcon#about to read 6, iclass 20, count 2 2006.239.08:07:11.37#ibcon#read 6, iclass 20, count 2 2006.239.08:07:11.37#ibcon#end of sib2, iclass 20, count 2 2006.239.08:07:11.37#ibcon#*mode == 0, iclass 20, count 2 2006.239.08:07:11.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.08:07:11.37#ibcon#[27=AT03-04\r\n] 2006.239.08:07:11.37#ibcon#*before write, iclass 20, count 2 2006.239.08:07:11.37#ibcon#enter sib2, iclass 20, count 2 2006.239.08:07:11.37#ibcon#flushed, iclass 20, count 2 2006.239.08:07:11.37#ibcon#about to write, iclass 20, count 2 2006.239.08:07:11.37#ibcon#wrote, iclass 20, count 2 2006.239.08:07:11.37#ibcon#about to read 3, iclass 20, count 2 2006.239.08:07:11.40#ibcon#read 3, iclass 20, count 2 2006.239.08:07:11.40#ibcon#about to read 4, iclass 20, count 2 2006.239.08:07:11.40#ibcon#read 4, iclass 20, count 2 2006.239.08:07:11.40#ibcon#about to read 5, iclass 20, count 2 2006.239.08:07:11.40#ibcon#read 5, iclass 20, count 2 2006.239.08:07:11.40#ibcon#about to read 6, iclass 20, count 2 2006.239.08:07:11.40#ibcon#read 6, iclass 20, count 2 2006.239.08:07:11.40#ibcon#end of sib2, iclass 20, count 2 2006.239.08:07:11.40#ibcon#*after write, iclass 20, count 2 2006.239.08:07:11.40#ibcon#*before return 0, iclass 20, count 2 2006.239.08:07:11.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:11.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:07:11.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.08:07:11.40#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:11.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:11.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:11.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:11.52#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:07:11.52#ibcon#first serial, iclass 20, count 0 2006.239.08:07:11.52#ibcon#enter sib2, iclass 20, count 0 2006.239.08:07:11.52#ibcon#flushed, iclass 20, count 0 2006.239.08:07:11.52#ibcon#about to write, iclass 20, count 0 2006.239.08:07:11.52#ibcon#wrote, iclass 20, count 0 2006.239.08:07:11.52#ibcon#about to read 3, iclass 20, count 0 2006.239.08:07:11.54#ibcon#read 3, iclass 20, count 0 2006.239.08:07:11.54#ibcon#about to read 4, iclass 20, count 0 2006.239.08:07:11.54#ibcon#read 4, iclass 20, count 0 2006.239.08:07:11.54#ibcon#about to read 5, iclass 20, count 0 2006.239.08:07:11.54#ibcon#read 5, iclass 20, count 0 2006.239.08:07:11.54#ibcon#about to read 6, iclass 20, count 0 2006.239.08:07:11.54#ibcon#read 6, iclass 20, count 0 2006.239.08:07:11.54#ibcon#end of sib2, iclass 20, count 0 2006.239.08:07:11.54#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:07:11.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:07:11.54#ibcon#[27=USB\r\n] 2006.239.08:07:11.54#ibcon#*before write, iclass 20, count 0 2006.239.08:07:11.54#ibcon#enter sib2, iclass 20, count 0 2006.239.08:07:11.54#ibcon#flushed, iclass 20, count 0 2006.239.08:07:11.54#ibcon#about to write, iclass 20, count 0 2006.239.08:07:11.54#ibcon#wrote, iclass 20, count 0 2006.239.08:07:11.54#ibcon#about to read 3, iclass 20, count 0 2006.239.08:07:11.57#ibcon#read 3, iclass 20, count 0 2006.239.08:07:11.57#ibcon#about to read 4, iclass 20, count 0 2006.239.08:07:11.57#ibcon#read 4, iclass 20, count 0 2006.239.08:07:11.57#ibcon#about to read 5, iclass 20, count 0 2006.239.08:07:11.57#ibcon#read 5, iclass 20, count 0 2006.239.08:07:11.57#ibcon#about to read 6, iclass 20, count 0 2006.239.08:07:11.57#ibcon#read 6, iclass 20, count 0 2006.239.08:07:11.57#ibcon#end of sib2, iclass 20, count 0 2006.239.08:07:11.57#ibcon#*after write, iclass 20, count 0 2006.239.08:07:11.57#ibcon#*before return 0, iclass 20, count 0 2006.239.08:07:11.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:11.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:07:11.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:07:11.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:07:11.57$vc4f8/vblo=4,712.99 2006.239.08:07:11.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.08:07:11.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.08:07:11.57#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:11.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:11.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:11.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:11.57#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:07:11.57#ibcon#first serial, iclass 22, count 0 2006.239.08:07:11.57#ibcon#enter sib2, iclass 22, count 0 2006.239.08:07:11.57#ibcon#flushed, iclass 22, count 0 2006.239.08:07:11.57#ibcon#about to write, iclass 22, count 0 2006.239.08:07:11.57#ibcon#wrote, iclass 22, count 0 2006.239.08:07:11.57#ibcon#about to read 3, iclass 22, count 0 2006.239.08:07:11.59#ibcon#read 3, iclass 22, count 0 2006.239.08:07:11.59#ibcon#about to read 4, iclass 22, count 0 2006.239.08:07:11.59#ibcon#read 4, iclass 22, count 0 2006.239.08:07:11.59#ibcon#about to read 5, iclass 22, count 0 2006.239.08:07:11.59#ibcon#read 5, iclass 22, count 0 2006.239.08:07:11.59#ibcon#about to read 6, iclass 22, count 0 2006.239.08:07:11.59#ibcon#read 6, iclass 22, count 0 2006.239.08:07:11.59#ibcon#end of sib2, iclass 22, count 0 2006.239.08:07:11.59#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:07:11.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:07:11.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:07:11.59#ibcon#*before write, iclass 22, count 0 2006.239.08:07:11.59#ibcon#enter sib2, iclass 22, count 0 2006.239.08:07:11.59#ibcon#flushed, iclass 22, count 0 2006.239.08:07:11.59#ibcon#about to write, iclass 22, count 0 2006.239.08:07:11.59#ibcon#wrote, iclass 22, count 0 2006.239.08:07:11.59#ibcon#about to read 3, iclass 22, count 0 2006.239.08:07:11.63#ibcon#read 3, iclass 22, count 0 2006.239.08:07:11.63#ibcon#about to read 4, iclass 22, count 0 2006.239.08:07:11.63#ibcon#read 4, iclass 22, count 0 2006.239.08:07:11.63#ibcon#about to read 5, iclass 22, count 0 2006.239.08:07:11.63#ibcon#read 5, iclass 22, count 0 2006.239.08:07:11.63#ibcon#about to read 6, iclass 22, count 0 2006.239.08:07:11.63#ibcon#read 6, iclass 22, count 0 2006.239.08:07:11.63#ibcon#end of sib2, iclass 22, count 0 2006.239.08:07:11.63#ibcon#*after write, iclass 22, count 0 2006.239.08:07:11.63#ibcon#*before return 0, iclass 22, count 0 2006.239.08:07:11.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:11.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:07:11.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:07:11.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:07:11.63$vc4f8/vb=4,4 2006.239.08:07:11.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.08:07:11.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.08:07:11.63#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:11.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:11.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:11.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:11.69#ibcon#enter wrdev, iclass 24, count 2 2006.239.08:07:11.69#ibcon#first serial, iclass 24, count 2 2006.239.08:07:11.69#ibcon#enter sib2, iclass 24, count 2 2006.239.08:07:11.69#ibcon#flushed, iclass 24, count 2 2006.239.08:07:11.69#ibcon#about to write, iclass 24, count 2 2006.239.08:07:11.69#ibcon#wrote, iclass 24, count 2 2006.239.08:07:11.69#ibcon#about to read 3, iclass 24, count 2 2006.239.08:07:11.71#ibcon#read 3, iclass 24, count 2 2006.239.08:07:11.71#ibcon#about to read 4, iclass 24, count 2 2006.239.08:07:11.71#ibcon#read 4, iclass 24, count 2 2006.239.08:07:11.71#ibcon#about to read 5, iclass 24, count 2 2006.239.08:07:11.71#ibcon#read 5, iclass 24, count 2 2006.239.08:07:11.71#ibcon#about to read 6, iclass 24, count 2 2006.239.08:07:11.71#ibcon#read 6, iclass 24, count 2 2006.239.08:07:11.71#ibcon#end of sib2, iclass 24, count 2 2006.239.08:07:11.71#ibcon#*mode == 0, iclass 24, count 2 2006.239.08:07:11.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.08:07:11.71#ibcon#[27=AT04-04\r\n] 2006.239.08:07:11.71#ibcon#*before write, iclass 24, count 2 2006.239.08:07:11.71#ibcon#enter sib2, iclass 24, count 2 2006.239.08:07:11.71#ibcon#flushed, iclass 24, count 2 2006.239.08:07:11.71#ibcon#about to write, iclass 24, count 2 2006.239.08:07:11.71#ibcon#wrote, iclass 24, count 2 2006.239.08:07:11.71#ibcon#about to read 3, iclass 24, count 2 2006.239.08:07:11.74#ibcon#read 3, iclass 24, count 2 2006.239.08:07:11.74#ibcon#about to read 4, iclass 24, count 2 2006.239.08:07:11.74#ibcon#read 4, iclass 24, count 2 2006.239.08:07:11.74#ibcon#about to read 5, iclass 24, count 2 2006.239.08:07:11.74#ibcon#read 5, iclass 24, count 2 2006.239.08:07:11.74#ibcon#about to read 6, iclass 24, count 2 2006.239.08:07:11.74#ibcon#read 6, iclass 24, count 2 2006.239.08:07:11.74#ibcon#end of sib2, iclass 24, count 2 2006.239.08:07:11.74#ibcon#*after write, iclass 24, count 2 2006.239.08:07:11.74#ibcon#*before return 0, iclass 24, count 2 2006.239.08:07:11.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:11.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:07:11.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.08:07:11.74#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:11.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:11.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:11.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:11.86#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:07:11.86#ibcon#first serial, iclass 24, count 0 2006.239.08:07:11.86#ibcon#enter sib2, iclass 24, count 0 2006.239.08:07:11.86#ibcon#flushed, iclass 24, count 0 2006.239.08:07:11.86#ibcon#about to write, iclass 24, count 0 2006.239.08:07:11.86#ibcon#wrote, iclass 24, count 0 2006.239.08:07:11.86#ibcon#about to read 3, iclass 24, count 0 2006.239.08:07:11.88#ibcon#read 3, iclass 24, count 0 2006.239.08:07:11.88#ibcon#about to read 4, iclass 24, count 0 2006.239.08:07:11.88#ibcon#read 4, iclass 24, count 0 2006.239.08:07:11.88#ibcon#about to read 5, iclass 24, count 0 2006.239.08:07:11.88#ibcon#read 5, iclass 24, count 0 2006.239.08:07:11.88#ibcon#about to read 6, iclass 24, count 0 2006.239.08:07:11.88#ibcon#read 6, iclass 24, count 0 2006.239.08:07:11.88#ibcon#end of sib2, iclass 24, count 0 2006.239.08:07:11.88#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:07:11.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:07:11.88#ibcon#[27=USB\r\n] 2006.239.08:07:11.88#ibcon#*before write, iclass 24, count 0 2006.239.08:07:11.88#ibcon#enter sib2, iclass 24, count 0 2006.239.08:07:11.88#ibcon#flushed, iclass 24, count 0 2006.239.08:07:11.88#ibcon#about to write, iclass 24, count 0 2006.239.08:07:11.88#ibcon#wrote, iclass 24, count 0 2006.239.08:07:11.88#ibcon#about to read 3, iclass 24, count 0 2006.239.08:07:11.91#ibcon#read 3, iclass 24, count 0 2006.239.08:07:11.91#ibcon#about to read 4, iclass 24, count 0 2006.239.08:07:11.91#ibcon#read 4, iclass 24, count 0 2006.239.08:07:11.91#ibcon#about to read 5, iclass 24, count 0 2006.239.08:07:11.91#ibcon#read 5, iclass 24, count 0 2006.239.08:07:11.91#ibcon#about to read 6, iclass 24, count 0 2006.239.08:07:11.91#ibcon#read 6, iclass 24, count 0 2006.239.08:07:11.91#ibcon#end of sib2, iclass 24, count 0 2006.239.08:07:11.91#ibcon#*after write, iclass 24, count 0 2006.239.08:07:11.91#ibcon#*before return 0, iclass 24, count 0 2006.239.08:07:11.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:11.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:07:11.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:07:11.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:07:11.91$vc4f8/vblo=5,744.99 2006.239.08:07:11.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.08:07:11.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.08:07:11.91#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:11.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:11.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:11.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:11.91#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:07:11.91#ibcon#first serial, iclass 26, count 0 2006.239.08:07:11.91#ibcon#enter sib2, iclass 26, count 0 2006.239.08:07:11.91#ibcon#flushed, iclass 26, count 0 2006.239.08:07:11.91#ibcon#about to write, iclass 26, count 0 2006.239.08:07:11.91#ibcon#wrote, iclass 26, count 0 2006.239.08:07:11.91#ibcon#about to read 3, iclass 26, count 0 2006.239.08:07:11.93#ibcon#read 3, iclass 26, count 0 2006.239.08:07:11.93#ibcon#about to read 4, iclass 26, count 0 2006.239.08:07:11.93#ibcon#read 4, iclass 26, count 0 2006.239.08:07:11.93#ibcon#about to read 5, iclass 26, count 0 2006.239.08:07:11.93#ibcon#read 5, iclass 26, count 0 2006.239.08:07:11.93#ibcon#about to read 6, iclass 26, count 0 2006.239.08:07:11.93#ibcon#read 6, iclass 26, count 0 2006.239.08:07:11.93#ibcon#end of sib2, iclass 26, count 0 2006.239.08:07:11.93#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:07:11.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:07:11.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:07:11.93#ibcon#*before write, iclass 26, count 0 2006.239.08:07:11.93#ibcon#enter sib2, iclass 26, count 0 2006.239.08:07:11.93#ibcon#flushed, iclass 26, count 0 2006.239.08:07:11.93#ibcon#about to write, iclass 26, count 0 2006.239.08:07:11.93#ibcon#wrote, iclass 26, count 0 2006.239.08:07:11.93#ibcon#about to read 3, iclass 26, count 0 2006.239.08:07:11.97#ibcon#read 3, iclass 26, count 0 2006.239.08:07:11.97#ibcon#about to read 4, iclass 26, count 0 2006.239.08:07:11.97#ibcon#read 4, iclass 26, count 0 2006.239.08:07:11.97#ibcon#about to read 5, iclass 26, count 0 2006.239.08:07:11.97#ibcon#read 5, iclass 26, count 0 2006.239.08:07:11.97#ibcon#about to read 6, iclass 26, count 0 2006.239.08:07:11.97#ibcon#read 6, iclass 26, count 0 2006.239.08:07:11.97#ibcon#end of sib2, iclass 26, count 0 2006.239.08:07:11.97#ibcon#*after write, iclass 26, count 0 2006.239.08:07:11.97#ibcon#*before return 0, iclass 26, count 0 2006.239.08:07:11.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:11.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:07:11.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:07:11.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:07:11.97$vc4f8/vb=5,4 2006.239.08:07:11.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.08:07:11.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.08:07:11.97#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:11.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:12.03#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:12.03#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:12.03#ibcon#enter wrdev, iclass 28, count 2 2006.239.08:07:12.03#ibcon#first serial, iclass 28, count 2 2006.239.08:07:12.03#ibcon#enter sib2, iclass 28, count 2 2006.239.08:07:12.03#ibcon#flushed, iclass 28, count 2 2006.239.08:07:12.03#ibcon#about to write, iclass 28, count 2 2006.239.08:07:12.03#ibcon#wrote, iclass 28, count 2 2006.239.08:07:12.03#ibcon#about to read 3, iclass 28, count 2 2006.239.08:07:12.05#ibcon#read 3, iclass 28, count 2 2006.239.08:07:12.05#ibcon#about to read 4, iclass 28, count 2 2006.239.08:07:12.05#ibcon#read 4, iclass 28, count 2 2006.239.08:07:12.05#ibcon#about to read 5, iclass 28, count 2 2006.239.08:07:12.05#ibcon#read 5, iclass 28, count 2 2006.239.08:07:12.05#ibcon#about to read 6, iclass 28, count 2 2006.239.08:07:12.05#ibcon#read 6, iclass 28, count 2 2006.239.08:07:12.05#ibcon#end of sib2, iclass 28, count 2 2006.239.08:07:12.05#ibcon#*mode == 0, iclass 28, count 2 2006.239.08:07:12.05#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.08:07:12.05#ibcon#[27=AT05-04\r\n] 2006.239.08:07:12.05#ibcon#*before write, iclass 28, count 2 2006.239.08:07:12.05#ibcon#enter sib2, iclass 28, count 2 2006.239.08:07:12.05#ibcon#flushed, iclass 28, count 2 2006.239.08:07:12.05#ibcon#about to write, iclass 28, count 2 2006.239.08:07:12.05#ibcon#wrote, iclass 28, count 2 2006.239.08:07:12.05#ibcon#about to read 3, iclass 28, count 2 2006.239.08:07:12.08#ibcon#read 3, iclass 28, count 2 2006.239.08:07:12.08#ibcon#about to read 4, iclass 28, count 2 2006.239.08:07:12.08#ibcon#read 4, iclass 28, count 2 2006.239.08:07:12.08#ibcon#about to read 5, iclass 28, count 2 2006.239.08:07:12.08#ibcon#read 5, iclass 28, count 2 2006.239.08:07:12.08#ibcon#about to read 6, iclass 28, count 2 2006.239.08:07:12.08#ibcon#read 6, iclass 28, count 2 2006.239.08:07:12.08#ibcon#end of sib2, iclass 28, count 2 2006.239.08:07:12.08#ibcon#*after write, iclass 28, count 2 2006.239.08:07:12.08#ibcon#*before return 0, iclass 28, count 2 2006.239.08:07:12.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:12.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:07:12.08#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.08:07:12.08#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:12.08#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:12.20#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:12.20#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:12.20#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:07:12.20#ibcon#first serial, iclass 28, count 0 2006.239.08:07:12.20#ibcon#enter sib2, iclass 28, count 0 2006.239.08:07:12.20#ibcon#flushed, iclass 28, count 0 2006.239.08:07:12.20#ibcon#about to write, iclass 28, count 0 2006.239.08:07:12.20#ibcon#wrote, iclass 28, count 0 2006.239.08:07:12.20#ibcon#about to read 3, iclass 28, count 0 2006.239.08:07:12.22#ibcon#read 3, iclass 28, count 0 2006.239.08:07:12.22#ibcon#about to read 4, iclass 28, count 0 2006.239.08:07:12.22#ibcon#read 4, iclass 28, count 0 2006.239.08:07:12.22#ibcon#about to read 5, iclass 28, count 0 2006.239.08:07:12.22#ibcon#read 5, iclass 28, count 0 2006.239.08:07:12.22#ibcon#about to read 6, iclass 28, count 0 2006.239.08:07:12.22#ibcon#read 6, iclass 28, count 0 2006.239.08:07:12.22#ibcon#end of sib2, iclass 28, count 0 2006.239.08:07:12.22#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:07:12.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:07:12.22#ibcon#[27=USB\r\n] 2006.239.08:07:12.22#ibcon#*before write, iclass 28, count 0 2006.239.08:07:12.22#ibcon#enter sib2, iclass 28, count 0 2006.239.08:07:12.22#ibcon#flushed, iclass 28, count 0 2006.239.08:07:12.22#ibcon#about to write, iclass 28, count 0 2006.239.08:07:12.22#ibcon#wrote, iclass 28, count 0 2006.239.08:07:12.22#ibcon#about to read 3, iclass 28, count 0 2006.239.08:07:12.25#ibcon#read 3, iclass 28, count 0 2006.239.08:07:12.25#ibcon#about to read 4, iclass 28, count 0 2006.239.08:07:12.25#ibcon#read 4, iclass 28, count 0 2006.239.08:07:12.25#ibcon#about to read 5, iclass 28, count 0 2006.239.08:07:12.25#ibcon#read 5, iclass 28, count 0 2006.239.08:07:12.25#ibcon#about to read 6, iclass 28, count 0 2006.239.08:07:12.25#ibcon#read 6, iclass 28, count 0 2006.239.08:07:12.25#ibcon#end of sib2, iclass 28, count 0 2006.239.08:07:12.25#ibcon#*after write, iclass 28, count 0 2006.239.08:07:12.25#ibcon#*before return 0, iclass 28, count 0 2006.239.08:07:12.25#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:12.25#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:07:12.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:07:12.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:07:12.25$vc4f8/vblo=6,752.99 2006.239.08:07:12.25#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.08:07:12.25#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.08:07:12.25#ibcon#ireg 17 cls_cnt 0 2006.239.08:07:12.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:12.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:12.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:12.25#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:07:12.25#ibcon#first serial, iclass 30, count 0 2006.239.08:07:12.25#ibcon#enter sib2, iclass 30, count 0 2006.239.08:07:12.25#ibcon#flushed, iclass 30, count 0 2006.239.08:07:12.25#ibcon#about to write, iclass 30, count 0 2006.239.08:07:12.25#ibcon#wrote, iclass 30, count 0 2006.239.08:07:12.25#ibcon#about to read 3, iclass 30, count 0 2006.239.08:07:12.27#ibcon#read 3, iclass 30, count 0 2006.239.08:07:12.27#ibcon#about to read 4, iclass 30, count 0 2006.239.08:07:12.27#ibcon#read 4, iclass 30, count 0 2006.239.08:07:12.27#ibcon#about to read 5, iclass 30, count 0 2006.239.08:07:12.27#ibcon#read 5, iclass 30, count 0 2006.239.08:07:12.27#ibcon#about to read 6, iclass 30, count 0 2006.239.08:07:12.27#ibcon#read 6, iclass 30, count 0 2006.239.08:07:12.27#ibcon#end of sib2, iclass 30, count 0 2006.239.08:07:12.27#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:07:12.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:07:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:07:12.27#ibcon#*before write, iclass 30, count 0 2006.239.08:07:12.27#ibcon#enter sib2, iclass 30, count 0 2006.239.08:07:12.27#ibcon#flushed, iclass 30, count 0 2006.239.08:07:12.27#ibcon#about to write, iclass 30, count 0 2006.239.08:07:12.27#ibcon#wrote, iclass 30, count 0 2006.239.08:07:12.27#ibcon#about to read 3, iclass 30, count 0 2006.239.08:07:12.31#ibcon#read 3, iclass 30, count 0 2006.239.08:07:12.31#ibcon#about to read 4, iclass 30, count 0 2006.239.08:07:12.31#ibcon#read 4, iclass 30, count 0 2006.239.08:07:12.31#ibcon#about to read 5, iclass 30, count 0 2006.239.08:07:12.31#ibcon#read 5, iclass 30, count 0 2006.239.08:07:12.31#ibcon#about to read 6, iclass 30, count 0 2006.239.08:07:12.31#ibcon#read 6, iclass 30, count 0 2006.239.08:07:12.31#ibcon#end of sib2, iclass 30, count 0 2006.239.08:07:12.31#ibcon#*after write, iclass 30, count 0 2006.239.08:07:12.31#ibcon#*before return 0, iclass 30, count 0 2006.239.08:07:12.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:12.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:07:12.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:07:12.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:07:12.31$vc4f8/vb=6,4 2006.239.08:07:12.31#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.08:07:12.31#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.08:07:12.31#ibcon#ireg 11 cls_cnt 2 2006.239.08:07:12.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:12.37#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:12.37#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:12.37#ibcon#enter wrdev, iclass 32, count 2 2006.239.08:07:12.37#ibcon#first serial, iclass 32, count 2 2006.239.08:07:12.37#ibcon#enter sib2, iclass 32, count 2 2006.239.08:07:12.37#ibcon#flushed, iclass 32, count 2 2006.239.08:07:12.37#ibcon#about to write, iclass 32, count 2 2006.239.08:07:12.37#ibcon#wrote, iclass 32, count 2 2006.239.08:07:12.37#ibcon#about to read 3, iclass 32, count 2 2006.239.08:07:12.39#ibcon#read 3, iclass 32, count 2 2006.239.08:07:12.39#ibcon#about to read 4, iclass 32, count 2 2006.239.08:07:12.39#ibcon#read 4, iclass 32, count 2 2006.239.08:07:12.39#ibcon#about to read 5, iclass 32, count 2 2006.239.08:07:12.39#ibcon#read 5, iclass 32, count 2 2006.239.08:07:12.39#ibcon#about to read 6, iclass 32, count 2 2006.239.08:07:12.39#ibcon#read 6, iclass 32, count 2 2006.239.08:07:12.39#ibcon#end of sib2, iclass 32, count 2 2006.239.08:07:12.39#ibcon#*mode == 0, iclass 32, count 2 2006.239.08:07:12.39#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.08:07:12.39#ibcon#[27=AT06-04\r\n] 2006.239.08:07:12.39#ibcon#*before write, iclass 32, count 2 2006.239.08:07:12.39#ibcon#enter sib2, iclass 32, count 2 2006.239.08:07:12.39#ibcon#flushed, iclass 32, count 2 2006.239.08:07:12.39#ibcon#about to write, iclass 32, count 2 2006.239.08:07:12.39#ibcon#wrote, iclass 32, count 2 2006.239.08:07:12.39#ibcon#about to read 3, iclass 32, count 2 2006.239.08:07:12.43#ibcon#read 3, iclass 32, count 2 2006.239.08:07:12.43#ibcon#about to read 4, iclass 32, count 2 2006.239.08:07:12.43#ibcon#read 4, iclass 32, count 2 2006.239.08:07:12.43#ibcon#about to read 5, iclass 32, count 2 2006.239.08:07:12.43#ibcon#read 5, iclass 32, count 2 2006.239.08:07:12.43#ibcon#about to read 6, iclass 32, count 2 2006.239.08:07:12.43#ibcon#read 6, iclass 32, count 2 2006.239.08:07:12.43#ibcon#end of sib2, iclass 32, count 2 2006.239.08:07:12.43#ibcon#*after write, iclass 32, count 2 2006.239.08:07:12.43#ibcon#*before return 0, iclass 32, count 2 2006.239.08:07:12.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:12.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:07:12.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.08:07:12.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:07:12.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:12.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:12.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:12.55#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:07:12.55#ibcon#first serial, iclass 32, count 0 2006.239.08:07:12.55#ibcon#enter sib2, iclass 32, count 0 2006.239.08:07:12.55#ibcon#flushed, iclass 32, count 0 2006.239.08:07:12.55#ibcon#about to write, iclass 32, count 0 2006.239.08:07:12.55#ibcon#wrote, iclass 32, count 0 2006.239.08:07:12.55#ibcon#about to read 3, iclass 32, count 0 2006.239.08:07:12.57#ibcon#read 3, iclass 32, count 0 2006.239.08:07:12.57#ibcon#about to read 4, iclass 32, count 0 2006.239.08:07:12.57#ibcon#read 4, iclass 32, count 0 2006.239.08:07:12.57#ibcon#about to read 5, iclass 32, count 0 2006.239.08:07:12.57#ibcon#read 5, iclass 32, count 0 2006.239.08:07:12.57#ibcon#about to read 6, iclass 32, count 0 2006.239.08:07:12.57#ibcon#read 6, iclass 32, count 0 2006.239.08:07:12.57#ibcon#end of sib2, iclass 32, count 0 2006.239.08:07:12.57#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:07:12.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:07:12.57#ibcon#[27=USB\r\n] 2006.239.08:07:12.57#ibcon#*before write, iclass 32, count 0 2006.239.08:07:12.57#ibcon#enter sib2, iclass 32, count 0 2006.239.08:07:12.57#ibcon#flushed, iclass 32, count 0 2006.239.08:07:12.57#ibcon#about to write, iclass 32, count 0 2006.239.08:07:12.57#ibcon#wrote, iclass 32, count 0 2006.239.08:07:12.57#ibcon#about to read 3, iclass 32, count 0 2006.239.08:07:12.60#ibcon#read 3, iclass 32, count 0 2006.239.08:07:12.60#ibcon#about to read 4, iclass 32, count 0 2006.239.08:07:12.60#ibcon#read 4, iclass 32, count 0 2006.239.08:07:12.60#ibcon#about to read 5, iclass 32, count 0 2006.239.08:07:12.60#ibcon#read 5, iclass 32, count 0 2006.239.08:07:12.60#ibcon#about to read 6, iclass 32, count 0 2006.239.08:07:12.60#ibcon#read 6, iclass 32, count 0 2006.239.08:07:12.60#ibcon#end of sib2, iclass 32, count 0 2006.239.08:07:12.60#ibcon#*after write, iclass 32, count 0 2006.239.08:07:12.60#ibcon#*before return 0, iclass 32, count 0 2006.239.08:07:12.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:12.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:07:12.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:07:12.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:07:12.60$vc4f8/vabw=wide 2006.239.08:07:12.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.08:07:12.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.08:07:12.60#ibcon#ireg 8 cls_cnt 0 2006.239.08:07:12.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:12.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:12.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:12.60#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:07:12.60#ibcon#first serial, iclass 34, count 0 2006.239.08:07:12.60#ibcon#enter sib2, iclass 34, count 0 2006.239.08:07:12.60#ibcon#flushed, iclass 34, count 0 2006.239.08:07:12.60#ibcon#about to write, iclass 34, count 0 2006.239.08:07:12.60#ibcon#wrote, iclass 34, count 0 2006.239.08:07:12.60#ibcon#about to read 3, iclass 34, count 0 2006.239.08:07:12.62#ibcon#read 3, iclass 34, count 0 2006.239.08:07:12.62#ibcon#about to read 4, iclass 34, count 0 2006.239.08:07:12.62#ibcon#read 4, iclass 34, count 0 2006.239.08:07:12.62#ibcon#about to read 5, iclass 34, count 0 2006.239.08:07:12.62#ibcon#read 5, iclass 34, count 0 2006.239.08:07:12.62#ibcon#about to read 6, iclass 34, count 0 2006.239.08:07:12.62#ibcon#read 6, iclass 34, count 0 2006.239.08:07:12.62#ibcon#end of sib2, iclass 34, count 0 2006.239.08:07:12.62#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:07:12.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:07:12.62#ibcon#[25=BW32\r\n] 2006.239.08:07:12.62#ibcon#*before write, iclass 34, count 0 2006.239.08:07:12.62#ibcon#enter sib2, iclass 34, count 0 2006.239.08:07:12.62#ibcon#flushed, iclass 34, count 0 2006.239.08:07:12.62#ibcon#about to write, iclass 34, count 0 2006.239.08:07:12.62#ibcon#wrote, iclass 34, count 0 2006.239.08:07:12.62#ibcon#about to read 3, iclass 34, count 0 2006.239.08:07:12.67#ibcon#read 3, iclass 34, count 0 2006.239.08:07:12.67#ibcon#about to read 4, iclass 34, count 0 2006.239.08:07:12.67#ibcon#read 4, iclass 34, count 0 2006.239.08:07:12.67#ibcon#about to read 5, iclass 34, count 0 2006.239.08:07:12.67#ibcon#read 5, iclass 34, count 0 2006.239.08:07:12.67#ibcon#about to read 6, iclass 34, count 0 2006.239.08:07:12.67#ibcon#read 6, iclass 34, count 0 2006.239.08:07:12.67#ibcon#end of sib2, iclass 34, count 0 2006.239.08:07:12.67#ibcon#*after write, iclass 34, count 0 2006.239.08:07:12.67#ibcon#*before return 0, iclass 34, count 0 2006.239.08:07:12.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:12.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:07:12.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:07:12.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:07:12.67$vc4f8/vbbw=wide 2006.239.08:07:12.67#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.08:07:12.67#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.08:07:12.67#ibcon#ireg 8 cls_cnt 0 2006.239.08:07:12.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:07:12.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:07:12.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:07:12.72#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:07:12.72#ibcon#first serial, iclass 36, count 0 2006.239.08:07:12.72#ibcon#enter sib2, iclass 36, count 0 2006.239.08:07:12.72#ibcon#flushed, iclass 36, count 0 2006.239.08:07:12.72#ibcon#about to write, iclass 36, count 0 2006.239.08:07:12.72#ibcon#wrote, iclass 36, count 0 2006.239.08:07:12.72#ibcon#about to read 3, iclass 36, count 0 2006.239.08:07:12.74#ibcon#read 3, iclass 36, count 0 2006.239.08:07:12.74#ibcon#about to read 4, iclass 36, count 0 2006.239.08:07:12.74#ibcon#read 4, iclass 36, count 0 2006.239.08:07:12.74#ibcon#about to read 5, iclass 36, count 0 2006.239.08:07:12.74#ibcon#read 5, iclass 36, count 0 2006.239.08:07:12.74#ibcon#about to read 6, iclass 36, count 0 2006.239.08:07:12.74#ibcon#read 6, iclass 36, count 0 2006.239.08:07:12.74#ibcon#end of sib2, iclass 36, count 0 2006.239.08:07:12.74#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:07:12.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:07:12.74#ibcon#[27=BW32\r\n] 2006.239.08:07:12.74#ibcon#*before write, iclass 36, count 0 2006.239.08:07:12.74#ibcon#enter sib2, iclass 36, count 0 2006.239.08:07:12.74#ibcon#flushed, iclass 36, count 0 2006.239.08:07:12.74#ibcon#about to write, iclass 36, count 0 2006.239.08:07:12.74#ibcon#wrote, iclass 36, count 0 2006.239.08:07:12.74#ibcon#about to read 3, iclass 36, count 0 2006.239.08:07:12.77#ibcon#read 3, iclass 36, count 0 2006.239.08:07:12.77#ibcon#about to read 4, iclass 36, count 0 2006.239.08:07:12.77#ibcon#read 4, iclass 36, count 0 2006.239.08:07:12.77#ibcon#about to read 5, iclass 36, count 0 2006.239.08:07:12.77#ibcon#read 5, iclass 36, count 0 2006.239.08:07:12.77#ibcon#about to read 6, iclass 36, count 0 2006.239.08:07:12.77#ibcon#read 6, iclass 36, count 0 2006.239.08:07:12.77#ibcon#end of sib2, iclass 36, count 0 2006.239.08:07:12.77#ibcon#*after write, iclass 36, count 0 2006.239.08:07:12.77#ibcon#*before return 0, iclass 36, count 0 2006.239.08:07:12.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:07:12.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:07:12.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:07:12.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:07:12.77$4f8m12a/ifd4f 2006.239.08:07:12.77$ifd4f/lo= 2006.239.08:07:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:07:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:07:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:07:12.77$ifd4f/patch= 2006.239.08:07:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:07:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:07:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:07:12.77$4f8m12a/"form=m,16.000,1:2 2006.239.08:07:12.77$4f8m12a/"tpicd 2006.239.08:07:12.77$4f8m12a/echo=off 2006.239.08:07:12.77$4f8m12a/xlog=off 2006.239.08:07:12.77:!2006.239.08:07:40 2006.239.08:07:23.13#trakl#Source acquired 2006.239.08:07:25.13#flagr#flagr/antenna,acquired 2006.239.08:07:40.00:preob 2006.239.08:07:41.14/onsource/TRACKING 2006.239.08:07:41.14:!2006.239.08:07:50 2006.239.08:07:50.00:data_valid=on 2006.239.08:07:50.00:midob 2006.239.08:07:50.14/onsource/TRACKING 2006.239.08:07:50.14/wx/25.11,1011.6,81 2006.239.08:07:50.31/cable/+6.4148E-03 2006.239.08:07:51.40/va/01,08,usb,yes,30,32 2006.239.08:07:51.40/va/02,07,usb,yes,30,32 2006.239.08:07:51.40/va/03,07,usb,yes,29,29 2006.239.08:07:51.40/va/04,07,usb,yes,32,34 2006.239.08:07:51.40/va/05,08,usb,yes,29,30 2006.239.08:07:51.40/va/06,07,usb,yes,31,31 2006.239.08:07:51.40/va/07,07,usb,yes,31,31 2006.239.08:07:51.40/va/08,07,usb,yes,33,33 2006.239.08:07:51.63/valo/01,532.99,yes,locked 2006.239.08:07:51.63/valo/02,572.99,yes,locked 2006.239.08:07:51.63/valo/03,672.99,yes,locked 2006.239.08:07:51.63/valo/04,832.99,yes,locked 2006.239.08:07:51.63/valo/05,652.99,yes,locked 2006.239.08:07:51.63/valo/06,772.99,yes,locked 2006.239.08:07:51.63/valo/07,832.99,yes,locked 2006.239.08:07:51.63/valo/08,852.99,yes,locked 2006.239.08:07:52.72/vb/01,04,usb,yes,30,29 2006.239.08:07:52.72/vb/02,04,usb,yes,32,33 2006.239.08:07:52.72/vb/03,04,usb,yes,28,32 2006.239.08:07:52.72/vb/04,04,usb,yes,29,29 2006.239.08:07:52.72/vb/05,04,usb,yes,27,31 2006.239.08:07:52.72/vb/06,04,usb,yes,28,31 2006.239.08:07:52.72/vb/07,04,usb,yes,30,30 2006.239.08:07:52.72/vb/08,04,usb,yes,28,31 2006.239.08:07:52.96/vblo/01,632.99,yes,locked 2006.239.08:07:52.96/vblo/02,640.99,yes,locked 2006.239.08:07:52.96/vblo/03,656.99,yes,locked 2006.239.08:07:52.96/vblo/04,712.99,yes,locked 2006.239.08:07:52.96/vblo/05,744.99,yes,locked 2006.239.08:07:52.96/vblo/06,752.99,yes,locked 2006.239.08:07:52.96/vblo/07,734.99,yes,locked 2006.239.08:07:52.96/vblo/08,744.99,yes,locked 2006.239.08:07:53.11/vabw/8 2006.239.08:07:53.26/vbbw/8 2006.239.08:07:53.35/xfe/off,on,14.0 2006.239.08:07:53.74/ifatt/23,28,28,28 2006.239.08:07:54.08/fmout-gps/S +4.39E-07 2006.239.08:07:54.12:!2006.239.08:08:50 2006.239.08:08:50.00:data_valid=off 2006.239.08:08:50.00:postob 2006.239.08:08:50.18/cable/+6.4157E-03 2006.239.08:08:50.18/wx/25.11,1011.5,80 2006.239.08:08:51.08/fmout-gps/S +4.38E-07 2006.239.08:08:51.08:scan_name=239-0809,k06239,60 2006.239.08:08:51.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.239.08:08:51.16#flagr#flagr/antenna,new-source 2006.239.08:08:52.14:checkk5 2006.239.08:08:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:08:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:08:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:08:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:08:54.04/chk_obsdata//k5ts1/T2390807??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:08:54.41/chk_obsdata//k5ts2/T2390807??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:08:54.79/chk_obsdata//k5ts3/T2390807??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:08:55.16/chk_obsdata//k5ts4/T2390807??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:08:55.86/k5log//k5ts1_log_newline 2006.239.08:08:56.56/k5log//k5ts2_log_newline 2006.239.08:08:57.26/k5log//k5ts3_log_newline 2006.239.08:08:57.95/k5log//k5ts4_log_newline 2006.239.08:08:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:08:57.97:4f8m12a=2 2006.239.08:08:57.97$4f8m12a/echo=on 2006.239.08:08:57.98$4f8m12a/pcalon 2006.239.08:08:57.98$pcalon/"no phase cal control is implemented here 2006.239.08:08:57.98$4f8m12a/"tpicd=stop 2006.239.08:08:57.98$4f8m12a/vc4f8 2006.239.08:08:57.98$vc4f8/valo=1,532.99 2006.239.08:08:57.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:08:57.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:08:57.98#ibcon#ireg 17 cls_cnt 0 2006.239.08:08:57.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:08:57.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:08:57.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:08:57.98#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:08:57.98#ibcon#first serial, iclass 5, count 0 2006.239.08:08:57.98#ibcon#enter sib2, iclass 5, count 0 2006.239.08:08:57.98#ibcon#flushed, iclass 5, count 0 2006.239.08:08:57.98#ibcon#about to write, iclass 5, count 0 2006.239.08:08:57.98#ibcon#wrote, iclass 5, count 0 2006.239.08:08:57.98#ibcon#about to read 3, iclass 5, count 0 2006.239.08:08:58.02#ibcon#read 3, iclass 5, count 0 2006.239.08:08:58.02#ibcon#about to read 4, iclass 5, count 0 2006.239.08:08:58.02#ibcon#read 4, iclass 5, count 0 2006.239.08:08:58.02#ibcon#about to read 5, iclass 5, count 0 2006.239.08:08:58.02#ibcon#read 5, iclass 5, count 0 2006.239.08:08:58.02#ibcon#about to read 6, iclass 5, count 0 2006.239.08:08:58.02#ibcon#read 6, iclass 5, count 0 2006.239.08:08:58.02#ibcon#end of sib2, iclass 5, count 0 2006.239.08:08:58.02#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:08:58.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:08:58.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:08:58.02#ibcon#*before write, iclass 5, count 0 2006.239.08:08:58.02#ibcon#enter sib2, iclass 5, count 0 2006.239.08:08:58.02#ibcon#flushed, iclass 5, count 0 2006.239.08:08:58.02#ibcon#about to write, iclass 5, count 0 2006.239.08:08:58.02#ibcon#wrote, iclass 5, count 0 2006.239.08:08:58.02#ibcon#about to read 3, iclass 5, count 0 2006.239.08:08:58.07#ibcon#read 3, iclass 5, count 0 2006.239.08:08:58.08#ibcon#about to read 4, iclass 5, count 0 2006.239.08:08:58.08#ibcon#read 4, iclass 5, count 0 2006.239.08:08:58.08#ibcon#about to read 5, iclass 5, count 0 2006.239.08:08:58.08#ibcon#read 5, iclass 5, count 0 2006.239.08:08:58.08#ibcon#about to read 6, iclass 5, count 0 2006.239.08:08:58.08#ibcon#read 6, iclass 5, count 0 2006.239.08:08:58.08#ibcon#end of sib2, iclass 5, count 0 2006.239.08:08:58.08#ibcon#*after write, iclass 5, count 0 2006.239.08:08:58.08#ibcon#*before return 0, iclass 5, count 0 2006.239.08:08:58.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:08:58.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:08:58.08#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:08:58.08#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:08:58.08$vc4f8/va=1,8 2006.239.08:08:58.08#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.08:08:58.08#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.08:08:58.08#ibcon#ireg 11 cls_cnt 2 2006.239.08:08:58.08#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:08:58.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:08:58.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:08:58.08#ibcon#enter wrdev, iclass 7, count 2 2006.239.08:08:58.08#ibcon#first serial, iclass 7, count 2 2006.239.08:08:58.08#ibcon#enter sib2, iclass 7, count 2 2006.239.08:08:58.08#ibcon#flushed, iclass 7, count 2 2006.239.08:08:58.08#ibcon#about to write, iclass 7, count 2 2006.239.08:08:58.08#ibcon#wrote, iclass 7, count 2 2006.239.08:08:58.08#ibcon#about to read 3, iclass 7, count 2 2006.239.08:08:58.10#ibcon#read 3, iclass 7, count 2 2006.239.08:08:58.10#ibcon#about to read 4, iclass 7, count 2 2006.239.08:08:58.10#ibcon#read 4, iclass 7, count 2 2006.239.08:08:58.10#ibcon#about to read 5, iclass 7, count 2 2006.239.08:08:58.10#ibcon#read 5, iclass 7, count 2 2006.239.08:08:58.10#ibcon#about to read 6, iclass 7, count 2 2006.239.08:08:58.10#ibcon#read 6, iclass 7, count 2 2006.239.08:08:58.10#ibcon#end of sib2, iclass 7, count 2 2006.239.08:08:58.10#ibcon#*mode == 0, iclass 7, count 2 2006.239.08:08:58.10#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.08:08:58.10#ibcon#[25=AT01-08\r\n] 2006.239.08:08:58.10#ibcon#*before write, iclass 7, count 2 2006.239.08:08:58.10#ibcon#enter sib2, iclass 7, count 2 2006.239.08:08:58.10#ibcon#flushed, iclass 7, count 2 2006.239.08:08:58.10#ibcon#about to write, iclass 7, count 2 2006.239.08:08:58.10#ibcon#wrote, iclass 7, count 2 2006.239.08:08:58.10#ibcon#about to read 3, iclass 7, count 2 2006.239.08:08:58.14#ibcon#read 3, iclass 7, count 2 2006.239.08:08:58.14#ibcon#about to read 4, iclass 7, count 2 2006.239.08:08:58.14#ibcon#read 4, iclass 7, count 2 2006.239.08:08:58.14#ibcon#about to read 5, iclass 7, count 2 2006.239.08:08:58.14#ibcon#read 5, iclass 7, count 2 2006.239.08:08:58.14#ibcon#about to read 6, iclass 7, count 2 2006.239.08:08:58.14#ibcon#read 6, iclass 7, count 2 2006.239.08:08:58.14#ibcon#end of sib2, iclass 7, count 2 2006.239.08:08:58.14#ibcon#*after write, iclass 7, count 2 2006.239.08:08:58.14#ibcon#*before return 0, iclass 7, count 2 2006.239.08:08:58.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:08:58.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:08:58.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.08:08:58.14#ibcon#ireg 7 cls_cnt 0 2006.239.08:08:58.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:08:58.25#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:08:58.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:08:58.26#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:08:58.26#ibcon#first serial, iclass 7, count 0 2006.239.08:08:58.26#ibcon#enter sib2, iclass 7, count 0 2006.239.08:08:58.26#ibcon#flushed, iclass 7, count 0 2006.239.08:08:58.26#ibcon#about to write, iclass 7, count 0 2006.239.08:08:58.26#ibcon#wrote, iclass 7, count 0 2006.239.08:08:58.26#ibcon#about to read 3, iclass 7, count 0 2006.239.08:08:58.27#ibcon#read 3, iclass 7, count 0 2006.239.08:08:58.28#ibcon#about to read 4, iclass 7, count 0 2006.239.08:08:58.28#ibcon#read 4, iclass 7, count 0 2006.239.08:08:58.28#ibcon#about to read 5, iclass 7, count 0 2006.239.08:08:58.28#ibcon#read 5, iclass 7, count 0 2006.239.08:08:58.28#ibcon#about to read 6, iclass 7, count 0 2006.239.08:08:58.28#ibcon#read 6, iclass 7, count 0 2006.239.08:08:58.28#ibcon#end of sib2, iclass 7, count 0 2006.239.08:08:58.28#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:08:58.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:08:58.28#ibcon#[25=USB\r\n] 2006.239.08:08:58.28#ibcon#*before write, iclass 7, count 0 2006.239.08:08:58.28#ibcon#enter sib2, iclass 7, count 0 2006.239.08:08:58.28#ibcon#flushed, iclass 7, count 0 2006.239.08:08:58.28#ibcon#about to write, iclass 7, count 0 2006.239.08:08:58.28#ibcon#wrote, iclass 7, count 0 2006.239.08:08:58.28#ibcon#about to read 3, iclass 7, count 0 2006.239.08:08:58.30#ibcon#read 3, iclass 7, count 0 2006.239.08:08:58.31#ibcon#about to read 4, iclass 7, count 0 2006.239.08:08:58.31#ibcon#read 4, iclass 7, count 0 2006.239.08:08:58.31#ibcon#about to read 5, iclass 7, count 0 2006.239.08:08:58.31#ibcon#read 5, iclass 7, count 0 2006.239.08:08:58.31#ibcon#about to read 6, iclass 7, count 0 2006.239.08:08:58.31#ibcon#read 6, iclass 7, count 0 2006.239.08:08:58.31#ibcon#end of sib2, iclass 7, count 0 2006.239.08:08:58.31#ibcon#*after write, iclass 7, count 0 2006.239.08:08:58.31#ibcon#*before return 0, iclass 7, count 0 2006.239.08:08:58.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:08:58.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:08:58.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:08:58.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:08:58.31$vc4f8/valo=2,572.99 2006.239.08:08:58.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.08:08:58.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.08:08:58.31#ibcon#ireg 17 cls_cnt 0 2006.239.08:08:58.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:08:58.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:08:58.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:08:58.31#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:08:58.31#ibcon#first serial, iclass 11, count 0 2006.239.08:08:58.31#ibcon#enter sib2, iclass 11, count 0 2006.239.08:08:58.31#ibcon#flushed, iclass 11, count 0 2006.239.08:08:58.31#ibcon#about to write, iclass 11, count 0 2006.239.08:08:58.31#ibcon#wrote, iclass 11, count 0 2006.239.08:08:58.31#ibcon#about to read 3, iclass 11, count 0 2006.239.08:08:58.32#ibcon#read 3, iclass 11, count 0 2006.239.08:08:58.33#ibcon#about to read 4, iclass 11, count 0 2006.239.08:08:58.33#ibcon#read 4, iclass 11, count 0 2006.239.08:08:58.33#ibcon#about to read 5, iclass 11, count 0 2006.239.08:08:58.33#ibcon#read 5, iclass 11, count 0 2006.239.08:08:58.33#ibcon#about to read 6, iclass 11, count 0 2006.239.08:08:58.33#ibcon#read 6, iclass 11, count 0 2006.239.08:08:58.33#ibcon#end of sib2, iclass 11, count 0 2006.239.08:08:58.33#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:08:58.33#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:08:58.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:08:58.33#ibcon#*before write, iclass 11, count 0 2006.239.08:08:58.33#ibcon#enter sib2, iclass 11, count 0 2006.239.08:08:58.33#ibcon#flushed, iclass 11, count 0 2006.239.08:08:58.33#ibcon#about to write, iclass 11, count 0 2006.239.08:08:58.33#ibcon#wrote, iclass 11, count 0 2006.239.08:08:58.33#ibcon#about to read 3, iclass 11, count 0 2006.239.08:08:58.37#ibcon#read 3, iclass 11, count 0 2006.239.08:08:58.37#ibcon#about to read 4, iclass 11, count 0 2006.239.08:08:58.37#ibcon#read 4, iclass 11, count 0 2006.239.08:08:58.37#ibcon#about to read 5, iclass 11, count 0 2006.239.08:08:58.37#ibcon#read 5, iclass 11, count 0 2006.239.08:08:58.37#ibcon#about to read 6, iclass 11, count 0 2006.239.08:08:58.37#ibcon#read 6, iclass 11, count 0 2006.239.08:08:58.37#ibcon#end of sib2, iclass 11, count 0 2006.239.08:08:58.37#ibcon#*after write, iclass 11, count 0 2006.239.08:08:58.37#ibcon#*before return 0, iclass 11, count 0 2006.239.08:08:58.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:08:58.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:08:58.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:08:58.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:08:58.37$vc4f8/va=2,7 2006.239.08:08:58.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.08:08:58.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.08:08:58.37#ibcon#ireg 11 cls_cnt 2 2006.239.08:08:58.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:08:58.42#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:08:58.42#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:08:58.43#ibcon#enter wrdev, iclass 13, count 2 2006.239.08:08:58.43#ibcon#first serial, iclass 13, count 2 2006.239.08:08:58.43#ibcon#enter sib2, iclass 13, count 2 2006.239.08:08:58.43#ibcon#flushed, iclass 13, count 2 2006.239.08:08:58.43#ibcon#about to write, iclass 13, count 2 2006.239.08:08:58.43#ibcon#wrote, iclass 13, count 2 2006.239.08:08:58.43#ibcon#about to read 3, iclass 13, count 2 2006.239.08:08:58.45#ibcon#read 3, iclass 13, count 2 2006.239.08:08:58.45#ibcon#about to read 4, iclass 13, count 2 2006.239.08:08:58.45#ibcon#read 4, iclass 13, count 2 2006.239.08:08:58.45#ibcon#about to read 5, iclass 13, count 2 2006.239.08:08:58.45#ibcon#read 5, iclass 13, count 2 2006.239.08:08:58.45#ibcon#about to read 6, iclass 13, count 2 2006.239.08:08:58.45#ibcon#read 6, iclass 13, count 2 2006.239.08:08:58.45#ibcon#end of sib2, iclass 13, count 2 2006.239.08:08:58.45#ibcon#*mode == 0, iclass 13, count 2 2006.239.08:08:58.45#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.08:08:58.45#ibcon#[25=AT02-07\r\n] 2006.239.08:08:58.45#ibcon#*before write, iclass 13, count 2 2006.239.08:08:58.45#ibcon#enter sib2, iclass 13, count 2 2006.239.08:08:58.45#ibcon#flushed, iclass 13, count 2 2006.239.08:08:58.45#ibcon#about to write, iclass 13, count 2 2006.239.08:08:58.45#ibcon#wrote, iclass 13, count 2 2006.239.08:08:58.45#ibcon#about to read 3, iclass 13, count 2 2006.239.08:08:58.47#ibcon#read 3, iclass 13, count 2 2006.239.08:08:58.48#ibcon#about to read 4, iclass 13, count 2 2006.239.08:08:58.48#ibcon#read 4, iclass 13, count 2 2006.239.08:08:58.48#ibcon#about to read 5, iclass 13, count 2 2006.239.08:08:58.48#ibcon#read 5, iclass 13, count 2 2006.239.08:08:58.48#ibcon#about to read 6, iclass 13, count 2 2006.239.08:08:58.48#ibcon#read 6, iclass 13, count 2 2006.239.08:08:58.48#ibcon#end of sib2, iclass 13, count 2 2006.239.08:08:58.48#ibcon#*after write, iclass 13, count 2 2006.239.08:08:58.48#ibcon#*before return 0, iclass 13, count 2 2006.239.08:08:58.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:08:58.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:08:58.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.08:08:58.48#ibcon#ireg 7 cls_cnt 0 2006.239.08:08:58.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:08:58.59#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:08:58.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:08:58.60#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:08:58.60#ibcon#first serial, iclass 13, count 0 2006.239.08:08:58.60#ibcon#enter sib2, iclass 13, count 0 2006.239.08:08:58.60#ibcon#flushed, iclass 13, count 0 2006.239.08:08:58.60#ibcon#about to write, iclass 13, count 0 2006.239.08:08:58.60#ibcon#wrote, iclass 13, count 0 2006.239.08:08:58.60#ibcon#about to read 3, iclass 13, count 0 2006.239.08:08:58.61#ibcon#read 3, iclass 13, count 0 2006.239.08:08:58.62#ibcon#about to read 4, iclass 13, count 0 2006.239.08:08:58.62#ibcon#read 4, iclass 13, count 0 2006.239.08:08:58.62#ibcon#about to read 5, iclass 13, count 0 2006.239.08:08:58.62#ibcon#read 5, iclass 13, count 0 2006.239.08:08:58.62#ibcon#about to read 6, iclass 13, count 0 2006.239.08:08:58.62#ibcon#read 6, iclass 13, count 0 2006.239.08:08:58.62#ibcon#end of sib2, iclass 13, count 0 2006.239.08:08:58.62#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:08:58.62#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:08:58.62#ibcon#[25=USB\r\n] 2006.239.08:08:58.62#ibcon#*before write, iclass 13, count 0 2006.239.08:08:58.62#ibcon#enter sib2, iclass 13, count 0 2006.239.08:08:58.62#ibcon#flushed, iclass 13, count 0 2006.239.08:08:58.62#ibcon#about to write, iclass 13, count 0 2006.239.08:08:58.62#ibcon#wrote, iclass 13, count 0 2006.239.08:08:58.62#ibcon#about to read 3, iclass 13, count 0 2006.239.08:08:58.65#ibcon#read 3, iclass 13, count 0 2006.239.08:08:58.65#ibcon#about to read 4, iclass 13, count 0 2006.239.08:08:58.65#ibcon#read 4, iclass 13, count 0 2006.239.08:08:58.65#ibcon#about to read 5, iclass 13, count 0 2006.239.08:08:58.65#ibcon#read 5, iclass 13, count 0 2006.239.08:08:58.65#ibcon#about to read 6, iclass 13, count 0 2006.239.08:08:58.65#ibcon#read 6, iclass 13, count 0 2006.239.08:08:58.65#ibcon#end of sib2, iclass 13, count 0 2006.239.08:08:58.65#ibcon#*after write, iclass 13, count 0 2006.239.08:08:58.65#ibcon#*before return 0, iclass 13, count 0 2006.239.08:08:58.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:08:58.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:08:58.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:08:58.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:08:58.65$vc4f8/valo=3,672.99 2006.239.08:08:58.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.08:08:58.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.08:08:58.65#ibcon#ireg 17 cls_cnt 0 2006.239.08:08:58.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:08:58.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:08:58.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:08:58.65#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:08:58.65#ibcon#first serial, iclass 15, count 0 2006.239.08:08:58.65#ibcon#enter sib2, iclass 15, count 0 2006.239.08:08:58.65#ibcon#flushed, iclass 15, count 0 2006.239.08:08:58.65#ibcon#about to write, iclass 15, count 0 2006.239.08:08:58.65#ibcon#wrote, iclass 15, count 0 2006.239.08:08:58.65#ibcon#about to read 3, iclass 15, count 0 2006.239.08:08:58.66#ibcon#read 3, iclass 15, count 0 2006.239.08:08:58.67#ibcon#about to read 4, iclass 15, count 0 2006.239.08:08:58.67#ibcon#read 4, iclass 15, count 0 2006.239.08:08:58.67#ibcon#about to read 5, iclass 15, count 0 2006.239.08:08:58.67#ibcon#read 5, iclass 15, count 0 2006.239.08:08:58.67#ibcon#about to read 6, iclass 15, count 0 2006.239.08:08:58.67#ibcon#read 6, iclass 15, count 0 2006.239.08:08:58.67#ibcon#end of sib2, iclass 15, count 0 2006.239.08:08:58.67#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:08:58.67#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:08:58.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:08:58.67#ibcon#*before write, iclass 15, count 0 2006.239.08:08:58.67#ibcon#enter sib2, iclass 15, count 0 2006.239.08:08:58.67#ibcon#flushed, iclass 15, count 0 2006.239.08:08:58.67#ibcon#about to write, iclass 15, count 0 2006.239.08:08:58.67#ibcon#wrote, iclass 15, count 0 2006.239.08:08:58.67#ibcon#about to read 3, iclass 15, count 0 2006.239.08:08:58.70#ibcon#read 3, iclass 15, count 0 2006.239.08:08:58.71#ibcon#about to read 4, iclass 15, count 0 2006.239.08:08:58.71#ibcon#read 4, iclass 15, count 0 2006.239.08:08:58.71#ibcon#about to read 5, iclass 15, count 0 2006.239.08:08:58.71#ibcon#read 5, iclass 15, count 0 2006.239.08:08:58.71#ibcon#about to read 6, iclass 15, count 0 2006.239.08:08:58.71#ibcon#read 6, iclass 15, count 0 2006.239.08:08:58.71#ibcon#end of sib2, iclass 15, count 0 2006.239.08:08:58.71#ibcon#*after write, iclass 15, count 0 2006.239.08:08:58.71#ibcon#*before return 0, iclass 15, count 0 2006.239.08:08:58.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:08:58.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:08:58.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:08:58.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:08:58.71$vc4f8/va=3,7 2006.239.08:08:58.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.08:08:58.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.08:08:58.71#ibcon#ireg 11 cls_cnt 2 2006.239.08:08:58.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:08:58.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:08:58.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:08:58.77#ibcon#enter wrdev, iclass 17, count 2 2006.239.08:08:58.77#ibcon#first serial, iclass 17, count 2 2006.239.08:08:58.77#ibcon#enter sib2, iclass 17, count 2 2006.239.08:08:58.77#ibcon#flushed, iclass 17, count 2 2006.239.08:08:58.77#ibcon#about to write, iclass 17, count 2 2006.239.08:08:58.77#ibcon#wrote, iclass 17, count 2 2006.239.08:08:58.77#ibcon#about to read 3, iclass 17, count 2 2006.239.08:08:58.79#ibcon#read 3, iclass 17, count 2 2006.239.08:08:58.79#ibcon#about to read 4, iclass 17, count 2 2006.239.08:08:58.79#ibcon#read 4, iclass 17, count 2 2006.239.08:08:58.79#ibcon#about to read 5, iclass 17, count 2 2006.239.08:08:58.79#ibcon#read 5, iclass 17, count 2 2006.239.08:08:58.79#ibcon#about to read 6, iclass 17, count 2 2006.239.08:08:58.79#ibcon#read 6, iclass 17, count 2 2006.239.08:08:58.79#ibcon#end of sib2, iclass 17, count 2 2006.239.08:08:58.79#ibcon#*mode == 0, iclass 17, count 2 2006.239.08:08:58.79#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.08:08:58.79#ibcon#[25=AT03-07\r\n] 2006.239.08:08:58.79#ibcon#*before write, iclass 17, count 2 2006.239.08:08:58.79#ibcon#enter sib2, iclass 17, count 2 2006.239.08:08:58.79#ibcon#flushed, iclass 17, count 2 2006.239.08:08:58.79#ibcon#about to write, iclass 17, count 2 2006.239.08:08:58.79#ibcon#wrote, iclass 17, count 2 2006.239.08:08:58.79#ibcon#about to read 3, iclass 17, count 2 2006.239.08:08:58.82#ibcon#read 3, iclass 17, count 2 2006.239.08:08:58.82#ibcon#about to read 4, iclass 17, count 2 2006.239.08:08:58.82#ibcon#read 4, iclass 17, count 2 2006.239.08:08:58.82#ibcon#about to read 5, iclass 17, count 2 2006.239.08:08:58.82#ibcon#read 5, iclass 17, count 2 2006.239.08:08:58.82#ibcon#about to read 6, iclass 17, count 2 2006.239.08:08:58.82#ibcon#read 6, iclass 17, count 2 2006.239.08:08:58.82#ibcon#end of sib2, iclass 17, count 2 2006.239.08:08:58.82#ibcon#*after write, iclass 17, count 2 2006.239.08:08:58.82#ibcon#*before return 0, iclass 17, count 2 2006.239.08:08:58.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:08:58.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:08:58.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.08:08:58.82#ibcon#ireg 7 cls_cnt 0 2006.239.08:08:58.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:08:58.93#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:08:58.93#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:08:58.94#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:08:58.94#ibcon#first serial, iclass 17, count 0 2006.239.08:08:58.94#ibcon#enter sib2, iclass 17, count 0 2006.239.08:08:58.94#ibcon#flushed, iclass 17, count 0 2006.239.08:08:58.94#ibcon#about to write, iclass 17, count 0 2006.239.08:08:58.94#ibcon#wrote, iclass 17, count 0 2006.239.08:08:58.94#ibcon#about to read 3, iclass 17, count 0 2006.239.08:08:58.96#ibcon#read 3, iclass 17, count 0 2006.239.08:08:58.96#ibcon#about to read 4, iclass 17, count 0 2006.239.08:08:58.96#ibcon#read 4, iclass 17, count 0 2006.239.08:08:58.96#ibcon#about to read 5, iclass 17, count 0 2006.239.08:08:58.96#ibcon#read 5, iclass 17, count 0 2006.239.08:08:58.96#ibcon#about to read 6, iclass 17, count 0 2006.239.08:08:58.96#ibcon#read 6, iclass 17, count 0 2006.239.08:08:58.96#ibcon#end of sib2, iclass 17, count 0 2006.239.08:08:58.96#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:08:58.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:08:58.96#ibcon#[25=USB\r\n] 2006.239.08:08:58.96#ibcon#*before write, iclass 17, count 0 2006.239.08:08:58.96#ibcon#enter sib2, iclass 17, count 0 2006.239.08:08:58.96#ibcon#flushed, iclass 17, count 0 2006.239.08:08:58.96#ibcon#about to write, iclass 17, count 0 2006.239.08:08:58.96#ibcon#wrote, iclass 17, count 0 2006.239.08:08:58.96#ibcon#about to read 3, iclass 17, count 0 2006.239.08:08:58.98#ibcon#read 3, iclass 17, count 0 2006.239.08:08:58.99#ibcon#about to read 4, iclass 17, count 0 2006.239.08:08:58.99#ibcon#read 4, iclass 17, count 0 2006.239.08:08:58.99#ibcon#about to read 5, iclass 17, count 0 2006.239.08:08:58.99#ibcon#read 5, iclass 17, count 0 2006.239.08:08:58.99#ibcon#about to read 6, iclass 17, count 0 2006.239.08:08:58.99#ibcon#read 6, iclass 17, count 0 2006.239.08:08:58.99#ibcon#end of sib2, iclass 17, count 0 2006.239.08:08:58.99#ibcon#*after write, iclass 17, count 0 2006.239.08:08:58.99#ibcon#*before return 0, iclass 17, count 0 2006.239.08:08:58.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:08:58.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:08:58.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:08:58.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:08:58.99$vc4f8/valo=4,832.99 2006.239.08:08:58.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.08:08:58.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.08:08:58.99#ibcon#ireg 17 cls_cnt 0 2006.239.08:08:58.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:08:58.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:08:58.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:08:58.99#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:08:58.99#ibcon#first serial, iclass 19, count 0 2006.239.08:08:58.99#ibcon#enter sib2, iclass 19, count 0 2006.239.08:08:58.99#ibcon#flushed, iclass 19, count 0 2006.239.08:08:58.99#ibcon#about to write, iclass 19, count 0 2006.239.08:08:58.99#ibcon#wrote, iclass 19, count 0 2006.239.08:08:58.99#ibcon#about to read 3, iclass 19, count 0 2006.239.08:08:59.01#ibcon#read 3, iclass 19, count 0 2006.239.08:08:59.01#ibcon#about to read 4, iclass 19, count 0 2006.239.08:08:59.01#ibcon#read 4, iclass 19, count 0 2006.239.08:08:59.01#ibcon#about to read 5, iclass 19, count 0 2006.239.08:08:59.01#ibcon#read 5, iclass 19, count 0 2006.239.08:08:59.01#ibcon#about to read 6, iclass 19, count 0 2006.239.08:08:59.01#ibcon#read 6, iclass 19, count 0 2006.239.08:08:59.01#ibcon#end of sib2, iclass 19, count 0 2006.239.08:08:59.01#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:08:59.01#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:08:59.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:08:59.01#ibcon#*before write, iclass 19, count 0 2006.239.08:08:59.01#ibcon#enter sib2, iclass 19, count 0 2006.239.08:08:59.01#ibcon#flushed, iclass 19, count 0 2006.239.08:08:59.01#ibcon#about to write, iclass 19, count 0 2006.239.08:08:59.01#ibcon#wrote, iclass 19, count 0 2006.239.08:08:59.01#ibcon#about to read 3, iclass 19, count 0 2006.239.08:08:59.04#ibcon#read 3, iclass 19, count 0 2006.239.08:08:59.05#ibcon#about to read 4, iclass 19, count 0 2006.239.08:08:59.05#ibcon#read 4, iclass 19, count 0 2006.239.08:08:59.05#ibcon#about to read 5, iclass 19, count 0 2006.239.08:08:59.05#ibcon#read 5, iclass 19, count 0 2006.239.08:08:59.05#ibcon#about to read 6, iclass 19, count 0 2006.239.08:08:59.05#ibcon#read 6, iclass 19, count 0 2006.239.08:08:59.05#ibcon#end of sib2, iclass 19, count 0 2006.239.08:08:59.05#ibcon#*after write, iclass 19, count 0 2006.239.08:08:59.05#ibcon#*before return 0, iclass 19, count 0 2006.239.08:08:59.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:08:59.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:08:59.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:08:59.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:08:59.05$vc4f8/va=4,7 2006.239.08:08:59.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.08:08:59.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.08:08:59.05#ibcon#ireg 11 cls_cnt 2 2006.239.08:08:59.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:08:59.10#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:08:59.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:08:59.11#ibcon#enter wrdev, iclass 21, count 2 2006.239.08:08:59.11#ibcon#first serial, iclass 21, count 2 2006.239.08:08:59.11#ibcon#enter sib2, iclass 21, count 2 2006.239.08:08:59.11#ibcon#flushed, iclass 21, count 2 2006.239.08:08:59.11#ibcon#about to write, iclass 21, count 2 2006.239.08:08:59.11#ibcon#wrote, iclass 21, count 2 2006.239.08:08:59.11#ibcon#about to read 3, iclass 21, count 2 2006.239.08:08:59.12#ibcon#read 3, iclass 21, count 2 2006.239.08:08:59.13#ibcon#about to read 4, iclass 21, count 2 2006.239.08:08:59.13#ibcon#read 4, iclass 21, count 2 2006.239.08:08:59.13#ibcon#about to read 5, iclass 21, count 2 2006.239.08:08:59.13#ibcon#read 5, iclass 21, count 2 2006.239.08:08:59.13#ibcon#about to read 6, iclass 21, count 2 2006.239.08:08:59.13#ibcon#read 6, iclass 21, count 2 2006.239.08:08:59.13#ibcon#end of sib2, iclass 21, count 2 2006.239.08:08:59.13#ibcon#*mode == 0, iclass 21, count 2 2006.239.08:08:59.13#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.08:08:59.13#ibcon#[25=AT04-07\r\n] 2006.239.08:08:59.13#ibcon#*before write, iclass 21, count 2 2006.239.08:08:59.13#ibcon#enter sib2, iclass 21, count 2 2006.239.08:08:59.13#ibcon#flushed, iclass 21, count 2 2006.239.08:08:59.13#ibcon#about to write, iclass 21, count 2 2006.239.08:08:59.13#ibcon#wrote, iclass 21, count 2 2006.239.08:08:59.13#ibcon#about to read 3, iclass 21, count 2 2006.239.08:08:59.16#ibcon#read 3, iclass 21, count 2 2006.239.08:08:59.16#ibcon#about to read 4, iclass 21, count 2 2006.239.08:08:59.16#ibcon#read 4, iclass 21, count 2 2006.239.08:08:59.16#ibcon#about to read 5, iclass 21, count 2 2006.239.08:08:59.16#ibcon#read 5, iclass 21, count 2 2006.239.08:08:59.16#ibcon#about to read 6, iclass 21, count 2 2006.239.08:08:59.16#ibcon#read 6, iclass 21, count 2 2006.239.08:08:59.16#ibcon#end of sib2, iclass 21, count 2 2006.239.08:08:59.16#ibcon#*after write, iclass 21, count 2 2006.239.08:08:59.16#ibcon#*before return 0, iclass 21, count 2 2006.239.08:08:59.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:08:59.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:08:59.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.08:08:59.16#ibcon#ireg 7 cls_cnt 0 2006.239.08:08:59.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:08:59.27#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:08:59.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:08:59.28#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:08:59.28#ibcon#first serial, iclass 21, count 0 2006.239.08:08:59.28#ibcon#enter sib2, iclass 21, count 0 2006.239.08:08:59.28#ibcon#flushed, iclass 21, count 0 2006.239.08:08:59.28#ibcon#about to write, iclass 21, count 0 2006.239.08:08:59.28#ibcon#wrote, iclass 21, count 0 2006.239.08:08:59.28#ibcon#about to read 3, iclass 21, count 0 2006.239.08:08:59.29#ibcon#read 3, iclass 21, count 0 2006.239.08:08:59.30#ibcon#about to read 4, iclass 21, count 0 2006.239.08:08:59.30#ibcon#read 4, iclass 21, count 0 2006.239.08:08:59.30#ibcon#about to read 5, iclass 21, count 0 2006.239.08:08:59.30#ibcon#read 5, iclass 21, count 0 2006.239.08:08:59.30#ibcon#about to read 6, iclass 21, count 0 2006.239.08:08:59.30#ibcon#read 6, iclass 21, count 0 2006.239.08:08:59.30#ibcon#end of sib2, iclass 21, count 0 2006.239.08:08:59.30#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:08:59.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:08:59.30#ibcon#[25=USB\r\n] 2006.239.08:08:59.30#ibcon#*before write, iclass 21, count 0 2006.239.08:08:59.30#ibcon#enter sib2, iclass 21, count 0 2006.239.08:08:59.30#ibcon#flushed, iclass 21, count 0 2006.239.08:08:59.30#ibcon#about to write, iclass 21, count 0 2006.239.08:08:59.30#ibcon#wrote, iclass 21, count 0 2006.239.08:08:59.30#ibcon#about to read 3, iclass 21, count 0 2006.239.08:08:59.32#ibcon#read 3, iclass 21, count 0 2006.239.08:08:59.33#ibcon#about to read 4, iclass 21, count 0 2006.239.08:08:59.33#ibcon#read 4, iclass 21, count 0 2006.239.08:08:59.33#ibcon#about to read 5, iclass 21, count 0 2006.239.08:08:59.33#ibcon#read 5, iclass 21, count 0 2006.239.08:08:59.33#ibcon#about to read 6, iclass 21, count 0 2006.239.08:08:59.33#ibcon#read 6, iclass 21, count 0 2006.239.08:08:59.33#ibcon#end of sib2, iclass 21, count 0 2006.239.08:08:59.33#ibcon#*after write, iclass 21, count 0 2006.239.08:08:59.33#ibcon#*before return 0, iclass 21, count 0 2006.239.08:08:59.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:08:59.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:08:59.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:08:59.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:08:59.33$vc4f8/valo=5,652.99 2006.239.08:08:59.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.08:08:59.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.08:08:59.33#ibcon#ireg 17 cls_cnt 0 2006.239.08:08:59.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:08:59.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:08:59.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:08:59.33#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:08:59.33#ibcon#first serial, iclass 23, count 0 2006.239.08:08:59.33#ibcon#enter sib2, iclass 23, count 0 2006.239.08:08:59.33#ibcon#flushed, iclass 23, count 0 2006.239.08:08:59.33#ibcon#about to write, iclass 23, count 0 2006.239.08:08:59.33#ibcon#wrote, iclass 23, count 0 2006.239.08:08:59.33#ibcon#about to read 3, iclass 23, count 0 2006.239.08:08:59.34#ibcon#read 3, iclass 23, count 0 2006.239.08:08:59.35#ibcon#about to read 4, iclass 23, count 0 2006.239.08:08:59.35#ibcon#read 4, iclass 23, count 0 2006.239.08:08:59.35#ibcon#about to read 5, iclass 23, count 0 2006.239.08:08:59.35#ibcon#read 5, iclass 23, count 0 2006.239.08:08:59.35#ibcon#about to read 6, iclass 23, count 0 2006.239.08:08:59.35#ibcon#read 6, iclass 23, count 0 2006.239.08:08:59.35#ibcon#end of sib2, iclass 23, count 0 2006.239.08:08:59.35#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:08:59.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:08:59.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:08:59.35#ibcon#*before write, iclass 23, count 0 2006.239.08:08:59.35#ibcon#enter sib2, iclass 23, count 0 2006.239.08:08:59.35#ibcon#flushed, iclass 23, count 0 2006.239.08:08:59.35#ibcon#about to write, iclass 23, count 0 2006.239.08:08:59.35#ibcon#wrote, iclass 23, count 0 2006.239.08:08:59.35#ibcon#about to read 3, iclass 23, count 0 2006.239.08:08:59.38#ibcon#read 3, iclass 23, count 0 2006.239.08:08:59.39#ibcon#about to read 4, iclass 23, count 0 2006.239.08:08:59.39#ibcon#read 4, iclass 23, count 0 2006.239.08:08:59.39#ibcon#about to read 5, iclass 23, count 0 2006.239.08:08:59.39#ibcon#read 5, iclass 23, count 0 2006.239.08:08:59.39#ibcon#about to read 6, iclass 23, count 0 2006.239.08:08:59.39#ibcon#read 6, iclass 23, count 0 2006.239.08:08:59.39#ibcon#end of sib2, iclass 23, count 0 2006.239.08:08:59.39#ibcon#*after write, iclass 23, count 0 2006.239.08:08:59.39#ibcon#*before return 0, iclass 23, count 0 2006.239.08:08:59.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:08:59.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:08:59.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:08:59.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:08:59.39$vc4f8/va=5,8 2006.239.08:08:59.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.08:08:59.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.08:08:59.39#ibcon#ireg 11 cls_cnt 2 2006.239.08:08:59.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:08:59.44#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:08:59.44#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:08:59.45#ibcon#enter wrdev, iclass 25, count 2 2006.239.08:08:59.45#ibcon#first serial, iclass 25, count 2 2006.239.08:08:59.45#ibcon#enter sib2, iclass 25, count 2 2006.239.08:08:59.45#ibcon#flushed, iclass 25, count 2 2006.239.08:08:59.45#ibcon#about to write, iclass 25, count 2 2006.239.08:08:59.45#ibcon#wrote, iclass 25, count 2 2006.239.08:08:59.45#ibcon#about to read 3, iclass 25, count 2 2006.239.08:08:59.46#ibcon#read 3, iclass 25, count 2 2006.239.08:08:59.47#ibcon#about to read 4, iclass 25, count 2 2006.239.08:08:59.47#ibcon#read 4, iclass 25, count 2 2006.239.08:08:59.47#ibcon#about to read 5, iclass 25, count 2 2006.239.08:08:59.47#ibcon#read 5, iclass 25, count 2 2006.239.08:08:59.47#ibcon#about to read 6, iclass 25, count 2 2006.239.08:08:59.47#ibcon#read 6, iclass 25, count 2 2006.239.08:08:59.47#ibcon#end of sib2, iclass 25, count 2 2006.239.08:08:59.47#ibcon#*mode == 0, iclass 25, count 2 2006.239.08:08:59.47#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.08:08:59.47#ibcon#[25=AT05-08\r\n] 2006.239.08:08:59.47#ibcon#*before write, iclass 25, count 2 2006.239.08:08:59.47#ibcon#enter sib2, iclass 25, count 2 2006.239.08:08:59.47#ibcon#flushed, iclass 25, count 2 2006.239.08:08:59.47#ibcon#about to write, iclass 25, count 2 2006.239.08:08:59.47#ibcon#wrote, iclass 25, count 2 2006.239.08:08:59.47#ibcon#about to read 3, iclass 25, count 2 2006.239.08:08:59.49#ibcon#read 3, iclass 25, count 2 2006.239.08:08:59.50#ibcon#about to read 4, iclass 25, count 2 2006.239.08:08:59.50#ibcon#read 4, iclass 25, count 2 2006.239.08:08:59.50#ibcon#about to read 5, iclass 25, count 2 2006.239.08:08:59.50#ibcon#read 5, iclass 25, count 2 2006.239.08:08:59.50#ibcon#about to read 6, iclass 25, count 2 2006.239.08:08:59.50#ibcon#read 6, iclass 25, count 2 2006.239.08:08:59.50#ibcon#end of sib2, iclass 25, count 2 2006.239.08:08:59.50#ibcon#*after write, iclass 25, count 2 2006.239.08:08:59.50#ibcon#*before return 0, iclass 25, count 2 2006.239.08:08:59.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:08:59.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:08:59.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.08:08:59.50#ibcon#ireg 7 cls_cnt 0 2006.239.08:08:59.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:08:59.61#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:08:59.61#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:08:59.62#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:08:59.62#ibcon#first serial, iclass 25, count 0 2006.239.08:08:59.62#ibcon#enter sib2, iclass 25, count 0 2006.239.08:08:59.62#ibcon#flushed, iclass 25, count 0 2006.239.08:08:59.62#ibcon#about to write, iclass 25, count 0 2006.239.08:08:59.62#ibcon#wrote, iclass 25, count 0 2006.239.08:08:59.62#ibcon#about to read 3, iclass 25, count 0 2006.239.08:08:59.63#ibcon#read 3, iclass 25, count 0 2006.239.08:08:59.64#ibcon#about to read 4, iclass 25, count 0 2006.239.08:08:59.64#ibcon#read 4, iclass 25, count 0 2006.239.08:08:59.64#ibcon#about to read 5, iclass 25, count 0 2006.239.08:08:59.64#ibcon#read 5, iclass 25, count 0 2006.239.08:08:59.64#ibcon#about to read 6, iclass 25, count 0 2006.239.08:08:59.64#ibcon#read 6, iclass 25, count 0 2006.239.08:08:59.64#ibcon#end of sib2, iclass 25, count 0 2006.239.08:08:59.64#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:08:59.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:08:59.64#ibcon#[25=USB\r\n] 2006.239.08:08:59.64#ibcon#*before write, iclass 25, count 0 2006.239.08:08:59.64#ibcon#enter sib2, iclass 25, count 0 2006.239.08:08:59.64#ibcon#flushed, iclass 25, count 0 2006.239.08:08:59.64#ibcon#about to write, iclass 25, count 0 2006.239.08:08:59.64#ibcon#wrote, iclass 25, count 0 2006.239.08:08:59.64#ibcon#about to read 3, iclass 25, count 0 2006.239.08:08:59.66#ibcon#read 3, iclass 25, count 0 2006.239.08:08:59.67#ibcon#about to read 4, iclass 25, count 0 2006.239.08:08:59.67#ibcon#read 4, iclass 25, count 0 2006.239.08:08:59.67#ibcon#about to read 5, iclass 25, count 0 2006.239.08:08:59.67#ibcon#read 5, iclass 25, count 0 2006.239.08:08:59.67#ibcon#about to read 6, iclass 25, count 0 2006.239.08:08:59.67#ibcon#read 6, iclass 25, count 0 2006.239.08:08:59.67#ibcon#end of sib2, iclass 25, count 0 2006.239.08:08:59.67#ibcon#*after write, iclass 25, count 0 2006.239.08:08:59.67#ibcon#*before return 0, iclass 25, count 0 2006.239.08:08:59.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:08:59.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:08:59.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:08:59.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:08:59.67$vc4f8/valo=6,772.99 2006.239.08:08:59.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.08:08:59.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.08:08:59.67#ibcon#ireg 17 cls_cnt 0 2006.239.08:08:59.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:08:59.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:08:59.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:08:59.67#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:08:59.67#ibcon#first serial, iclass 27, count 0 2006.239.08:08:59.67#ibcon#enter sib2, iclass 27, count 0 2006.239.08:08:59.67#ibcon#flushed, iclass 27, count 0 2006.239.08:08:59.67#ibcon#about to write, iclass 27, count 0 2006.239.08:08:59.67#ibcon#wrote, iclass 27, count 0 2006.239.08:08:59.67#ibcon#about to read 3, iclass 27, count 0 2006.239.08:08:59.68#ibcon#read 3, iclass 27, count 0 2006.239.08:08:59.69#ibcon#about to read 4, iclass 27, count 0 2006.239.08:08:59.69#ibcon#read 4, iclass 27, count 0 2006.239.08:08:59.69#ibcon#about to read 5, iclass 27, count 0 2006.239.08:08:59.69#ibcon#read 5, iclass 27, count 0 2006.239.08:08:59.69#ibcon#about to read 6, iclass 27, count 0 2006.239.08:08:59.69#ibcon#read 6, iclass 27, count 0 2006.239.08:08:59.69#ibcon#end of sib2, iclass 27, count 0 2006.239.08:08:59.69#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:08:59.69#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:08:59.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:08:59.69#ibcon#*before write, iclass 27, count 0 2006.239.08:08:59.69#ibcon#enter sib2, iclass 27, count 0 2006.239.08:08:59.69#ibcon#flushed, iclass 27, count 0 2006.239.08:08:59.69#ibcon#about to write, iclass 27, count 0 2006.239.08:08:59.69#ibcon#wrote, iclass 27, count 0 2006.239.08:08:59.69#ibcon#about to read 3, iclass 27, count 0 2006.239.08:08:59.72#ibcon#read 3, iclass 27, count 0 2006.239.08:08:59.73#ibcon#about to read 4, iclass 27, count 0 2006.239.08:08:59.73#ibcon#read 4, iclass 27, count 0 2006.239.08:08:59.73#ibcon#about to read 5, iclass 27, count 0 2006.239.08:08:59.73#ibcon#read 5, iclass 27, count 0 2006.239.08:08:59.73#ibcon#about to read 6, iclass 27, count 0 2006.239.08:08:59.73#ibcon#read 6, iclass 27, count 0 2006.239.08:08:59.73#ibcon#end of sib2, iclass 27, count 0 2006.239.08:08:59.73#ibcon#*after write, iclass 27, count 0 2006.239.08:08:59.73#ibcon#*before return 0, iclass 27, count 0 2006.239.08:08:59.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:08:59.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:08:59.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:08:59.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:08:59.73$vc4f8/va=6,7 2006.239.08:08:59.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.239.08:08:59.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.239.08:08:59.73#ibcon#ireg 11 cls_cnt 2 2006.239.08:08:59.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:08:59.78#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:08:59.78#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:08:59.79#ibcon#enter wrdev, iclass 29, count 2 2006.239.08:08:59.79#ibcon#first serial, iclass 29, count 2 2006.239.08:08:59.79#ibcon#enter sib2, iclass 29, count 2 2006.239.08:08:59.79#ibcon#flushed, iclass 29, count 2 2006.239.08:08:59.79#ibcon#about to write, iclass 29, count 2 2006.239.08:08:59.79#ibcon#wrote, iclass 29, count 2 2006.239.08:08:59.79#ibcon#about to read 3, iclass 29, count 2 2006.239.08:08:59.80#ibcon#read 3, iclass 29, count 2 2006.239.08:08:59.81#ibcon#about to read 4, iclass 29, count 2 2006.239.08:08:59.81#ibcon#read 4, iclass 29, count 2 2006.239.08:08:59.81#ibcon#about to read 5, iclass 29, count 2 2006.239.08:08:59.81#ibcon#read 5, iclass 29, count 2 2006.239.08:08:59.81#ibcon#about to read 6, iclass 29, count 2 2006.239.08:08:59.81#ibcon#read 6, iclass 29, count 2 2006.239.08:08:59.81#ibcon#end of sib2, iclass 29, count 2 2006.239.08:08:59.81#ibcon#*mode == 0, iclass 29, count 2 2006.239.08:08:59.81#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.239.08:08:59.81#ibcon#[25=AT06-07\r\n] 2006.239.08:08:59.81#ibcon#*before write, iclass 29, count 2 2006.239.08:08:59.81#ibcon#enter sib2, iclass 29, count 2 2006.239.08:08:59.81#ibcon#flushed, iclass 29, count 2 2006.239.08:08:59.81#ibcon#about to write, iclass 29, count 2 2006.239.08:08:59.81#ibcon#wrote, iclass 29, count 2 2006.239.08:08:59.81#ibcon#about to read 3, iclass 29, count 2 2006.239.08:08:59.83#ibcon#read 3, iclass 29, count 2 2006.239.08:08:59.84#ibcon#about to read 4, iclass 29, count 2 2006.239.08:08:59.84#ibcon#read 4, iclass 29, count 2 2006.239.08:08:59.84#ibcon#about to read 5, iclass 29, count 2 2006.239.08:08:59.84#ibcon#read 5, iclass 29, count 2 2006.239.08:08:59.84#ibcon#about to read 6, iclass 29, count 2 2006.239.08:08:59.84#ibcon#read 6, iclass 29, count 2 2006.239.08:08:59.84#ibcon#end of sib2, iclass 29, count 2 2006.239.08:08:59.84#ibcon#*after write, iclass 29, count 2 2006.239.08:08:59.84#ibcon#*before return 0, iclass 29, count 2 2006.239.08:08:59.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:08:59.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.239.08:08:59.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.239.08:08:59.84#ibcon#ireg 7 cls_cnt 0 2006.239.08:08:59.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:08:59.95#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:08:59.95#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:08:59.96#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:08:59.96#ibcon#first serial, iclass 29, count 0 2006.239.08:08:59.96#ibcon#enter sib2, iclass 29, count 0 2006.239.08:08:59.96#ibcon#flushed, iclass 29, count 0 2006.239.08:08:59.96#ibcon#about to write, iclass 29, count 0 2006.239.08:08:59.96#ibcon#wrote, iclass 29, count 0 2006.239.08:08:59.96#ibcon#about to read 3, iclass 29, count 0 2006.239.08:08:59.97#ibcon#read 3, iclass 29, count 0 2006.239.08:08:59.97#ibcon#about to read 4, iclass 29, count 0 2006.239.08:08:59.97#ibcon#read 4, iclass 29, count 0 2006.239.08:08:59.97#ibcon#about to read 5, iclass 29, count 0 2006.239.08:08:59.98#ibcon#read 5, iclass 29, count 0 2006.239.08:08:59.98#ibcon#about to read 6, iclass 29, count 0 2006.239.08:08:59.98#ibcon#read 6, iclass 29, count 0 2006.239.08:08:59.98#ibcon#end of sib2, iclass 29, count 0 2006.239.08:08:59.98#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:08:59.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:08:59.98#ibcon#[25=USB\r\n] 2006.239.08:08:59.98#ibcon#*before write, iclass 29, count 0 2006.239.08:08:59.98#ibcon#enter sib2, iclass 29, count 0 2006.239.08:08:59.98#ibcon#flushed, iclass 29, count 0 2006.239.08:08:59.98#ibcon#about to write, iclass 29, count 0 2006.239.08:08:59.98#ibcon#wrote, iclass 29, count 0 2006.239.08:08:59.98#ibcon#about to read 3, iclass 29, count 0 2006.239.08:09:00.00#ibcon#read 3, iclass 29, count 0 2006.239.08:09:00.01#ibcon#about to read 4, iclass 29, count 0 2006.239.08:09:00.01#ibcon#read 4, iclass 29, count 0 2006.239.08:09:00.01#ibcon#about to read 5, iclass 29, count 0 2006.239.08:09:00.01#ibcon#read 5, iclass 29, count 0 2006.239.08:09:00.01#ibcon#about to read 6, iclass 29, count 0 2006.239.08:09:00.01#ibcon#read 6, iclass 29, count 0 2006.239.08:09:00.01#ibcon#end of sib2, iclass 29, count 0 2006.239.08:09:00.01#ibcon#*after write, iclass 29, count 0 2006.239.08:09:00.01#ibcon#*before return 0, iclass 29, count 0 2006.239.08:09:00.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:09:00.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.239.08:09:00.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:09:00.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:09:00.01$vc4f8/valo=7,832.99 2006.239.08:09:00.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.08:09:00.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.08:09:00.01#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:00.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:09:00.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:09:00.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:09:00.01#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:09:00.01#ibcon#first serial, iclass 31, count 0 2006.239.08:09:00.01#ibcon#enter sib2, iclass 31, count 0 2006.239.08:09:00.01#ibcon#flushed, iclass 31, count 0 2006.239.08:09:00.01#ibcon#about to write, iclass 31, count 0 2006.239.08:09:00.01#ibcon#wrote, iclass 31, count 0 2006.239.08:09:00.01#ibcon#about to read 3, iclass 31, count 0 2006.239.08:09:00.02#ibcon#read 3, iclass 31, count 0 2006.239.08:09:00.03#ibcon#about to read 4, iclass 31, count 0 2006.239.08:09:00.03#ibcon#read 4, iclass 31, count 0 2006.239.08:09:00.03#ibcon#about to read 5, iclass 31, count 0 2006.239.08:09:00.03#ibcon#read 5, iclass 31, count 0 2006.239.08:09:00.03#ibcon#about to read 6, iclass 31, count 0 2006.239.08:09:00.03#ibcon#read 6, iclass 31, count 0 2006.239.08:09:00.03#ibcon#end of sib2, iclass 31, count 0 2006.239.08:09:00.03#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:09:00.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:09:00.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:09:00.03#ibcon#*before write, iclass 31, count 0 2006.239.08:09:00.03#ibcon#enter sib2, iclass 31, count 0 2006.239.08:09:00.03#ibcon#flushed, iclass 31, count 0 2006.239.08:09:00.03#ibcon#about to write, iclass 31, count 0 2006.239.08:09:00.03#ibcon#wrote, iclass 31, count 0 2006.239.08:09:00.03#ibcon#about to read 3, iclass 31, count 0 2006.239.08:09:00.06#ibcon#read 3, iclass 31, count 0 2006.239.08:09:00.07#ibcon#about to read 4, iclass 31, count 0 2006.239.08:09:00.07#ibcon#read 4, iclass 31, count 0 2006.239.08:09:00.07#ibcon#about to read 5, iclass 31, count 0 2006.239.08:09:00.07#ibcon#read 5, iclass 31, count 0 2006.239.08:09:00.07#ibcon#about to read 6, iclass 31, count 0 2006.239.08:09:00.07#ibcon#read 6, iclass 31, count 0 2006.239.08:09:00.07#ibcon#end of sib2, iclass 31, count 0 2006.239.08:09:00.07#ibcon#*after write, iclass 31, count 0 2006.239.08:09:00.07#ibcon#*before return 0, iclass 31, count 0 2006.239.08:09:00.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:09:00.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:09:00.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:09:00.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:09:00.07$vc4f8/va=7,7 2006.239.08:09:00.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.08:09:00.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.08:09:00.07#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:00.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:09:00.12#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:09:00.12#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:09:00.13#ibcon#enter wrdev, iclass 33, count 2 2006.239.08:09:00.13#ibcon#first serial, iclass 33, count 2 2006.239.08:09:00.13#ibcon#enter sib2, iclass 33, count 2 2006.239.08:09:00.13#ibcon#flushed, iclass 33, count 2 2006.239.08:09:00.13#ibcon#about to write, iclass 33, count 2 2006.239.08:09:00.13#ibcon#wrote, iclass 33, count 2 2006.239.08:09:00.13#ibcon#about to read 3, iclass 33, count 2 2006.239.08:09:00.14#ibcon#read 3, iclass 33, count 2 2006.239.08:09:00.15#ibcon#about to read 4, iclass 33, count 2 2006.239.08:09:00.15#ibcon#read 4, iclass 33, count 2 2006.239.08:09:00.15#ibcon#about to read 5, iclass 33, count 2 2006.239.08:09:00.15#ibcon#read 5, iclass 33, count 2 2006.239.08:09:00.15#ibcon#about to read 6, iclass 33, count 2 2006.239.08:09:00.15#ibcon#read 6, iclass 33, count 2 2006.239.08:09:00.15#ibcon#end of sib2, iclass 33, count 2 2006.239.08:09:00.15#ibcon#*mode == 0, iclass 33, count 2 2006.239.08:09:00.15#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.08:09:00.15#ibcon#[25=AT07-07\r\n] 2006.239.08:09:00.15#ibcon#*before write, iclass 33, count 2 2006.239.08:09:00.15#ibcon#enter sib2, iclass 33, count 2 2006.239.08:09:00.15#ibcon#flushed, iclass 33, count 2 2006.239.08:09:00.15#ibcon#about to write, iclass 33, count 2 2006.239.08:09:00.15#ibcon#wrote, iclass 33, count 2 2006.239.08:09:00.15#ibcon#about to read 3, iclass 33, count 2 2006.239.08:09:00.17#ibcon#read 3, iclass 33, count 2 2006.239.08:09:00.18#ibcon#about to read 4, iclass 33, count 2 2006.239.08:09:00.18#ibcon#read 4, iclass 33, count 2 2006.239.08:09:00.18#ibcon#about to read 5, iclass 33, count 2 2006.239.08:09:00.18#ibcon#read 5, iclass 33, count 2 2006.239.08:09:00.18#ibcon#about to read 6, iclass 33, count 2 2006.239.08:09:00.18#ibcon#read 6, iclass 33, count 2 2006.239.08:09:00.18#ibcon#end of sib2, iclass 33, count 2 2006.239.08:09:00.18#ibcon#*after write, iclass 33, count 2 2006.239.08:09:00.18#ibcon#*before return 0, iclass 33, count 2 2006.239.08:09:00.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:09:00.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:09:00.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.08:09:00.18#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:00.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:09:00.29#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:09:00.29#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:09:00.30#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:09:00.30#ibcon#first serial, iclass 33, count 0 2006.239.08:09:00.30#ibcon#enter sib2, iclass 33, count 0 2006.239.08:09:00.30#ibcon#flushed, iclass 33, count 0 2006.239.08:09:00.30#ibcon#about to write, iclass 33, count 0 2006.239.08:09:00.30#ibcon#wrote, iclass 33, count 0 2006.239.08:09:00.30#ibcon#about to read 3, iclass 33, count 0 2006.239.08:09:00.31#ibcon#read 3, iclass 33, count 0 2006.239.08:09:00.32#ibcon#about to read 4, iclass 33, count 0 2006.239.08:09:00.32#ibcon#read 4, iclass 33, count 0 2006.239.08:09:00.32#ibcon#about to read 5, iclass 33, count 0 2006.239.08:09:00.32#ibcon#read 5, iclass 33, count 0 2006.239.08:09:00.32#ibcon#about to read 6, iclass 33, count 0 2006.239.08:09:00.32#ibcon#read 6, iclass 33, count 0 2006.239.08:09:00.32#ibcon#end of sib2, iclass 33, count 0 2006.239.08:09:00.32#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:09:00.32#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:09:00.32#ibcon#[25=USB\r\n] 2006.239.08:09:00.32#ibcon#*before write, iclass 33, count 0 2006.239.08:09:00.32#ibcon#enter sib2, iclass 33, count 0 2006.239.08:09:00.32#ibcon#flushed, iclass 33, count 0 2006.239.08:09:00.32#ibcon#about to write, iclass 33, count 0 2006.239.08:09:00.32#ibcon#wrote, iclass 33, count 0 2006.239.08:09:00.32#ibcon#about to read 3, iclass 33, count 0 2006.239.08:09:00.34#ibcon#read 3, iclass 33, count 0 2006.239.08:09:00.35#ibcon#about to read 4, iclass 33, count 0 2006.239.08:09:00.35#ibcon#read 4, iclass 33, count 0 2006.239.08:09:00.35#ibcon#about to read 5, iclass 33, count 0 2006.239.08:09:00.35#ibcon#read 5, iclass 33, count 0 2006.239.08:09:00.35#ibcon#about to read 6, iclass 33, count 0 2006.239.08:09:00.35#ibcon#read 6, iclass 33, count 0 2006.239.08:09:00.35#ibcon#end of sib2, iclass 33, count 0 2006.239.08:09:00.35#ibcon#*after write, iclass 33, count 0 2006.239.08:09:00.35#ibcon#*before return 0, iclass 33, count 0 2006.239.08:09:00.35#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:09:00.35#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:09:00.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:09:00.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:09:00.35$vc4f8/valo=8,852.99 2006.239.08:09:00.35#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.08:09:00.35#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.08:09:00.35#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:00.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:09:00.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:09:00.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:09:00.35#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:09:00.35#ibcon#first serial, iclass 35, count 0 2006.239.08:09:00.35#ibcon#enter sib2, iclass 35, count 0 2006.239.08:09:00.35#ibcon#flushed, iclass 35, count 0 2006.239.08:09:00.35#ibcon#about to write, iclass 35, count 0 2006.239.08:09:00.35#ibcon#wrote, iclass 35, count 0 2006.239.08:09:00.35#ibcon#about to read 3, iclass 35, count 0 2006.239.08:09:00.36#ibcon#read 3, iclass 35, count 0 2006.239.08:09:00.36#ibcon#about to read 4, iclass 35, count 0 2006.239.08:09:00.36#ibcon#read 4, iclass 35, count 0 2006.239.08:09:00.36#ibcon#about to read 5, iclass 35, count 0 2006.239.08:09:00.37#ibcon#read 5, iclass 35, count 0 2006.239.08:09:00.37#ibcon#about to read 6, iclass 35, count 0 2006.239.08:09:00.37#ibcon#read 6, iclass 35, count 0 2006.239.08:09:00.37#ibcon#end of sib2, iclass 35, count 0 2006.239.08:09:00.37#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:09:00.37#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:09:00.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:09:00.37#ibcon#*before write, iclass 35, count 0 2006.239.08:09:00.37#ibcon#enter sib2, iclass 35, count 0 2006.239.08:09:00.37#ibcon#flushed, iclass 35, count 0 2006.239.08:09:00.37#ibcon#about to write, iclass 35, count 0 2006.239.08:09:00.37#ibcon#wrote, iclass 35, count 0 2006.239.08:09:00.37#ibcon#about to read 3, iclass 35, count 0 2006.239.08:09:00.40#ibcon#read 3, iclass 35, count 0 2006.239.08:09:00.41#ibcon#about to read 4, iclass 35, count 0 2006.239.08:09:00.41#ibcon#read 4, iclass 35, count 0 2006.239.08:09:00.41#ibcon#about to read 5, iclass 35, count 0 2006.239.08:09:00.41#ibcon#read 5, iclass 35, count 0 2006.239.08:09:00.41#ibcon#about to read 6, iclass 35, count 0 2006.239.08:09:00.41#ibcon#read 6, iclass 35, count 0 2006.239.08:09:00.41#ibcon#end of sib2, iclass 35, count 0 2006.239.08:09:00.41#ibcon#*after write, iclass 35, count 0 2006.239.08:09:00.41#ibcon#*before return 0, iclass 35, count 0 2006.239.08:09:00.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:09:00.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:09:00.41#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:09:00.41#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:09:00.41$vc4f8/va=8,7 2006.239.08:09:00.41#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.08:09:00.41#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.08:09:00.41#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:00.41#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:09:00.46#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:09:00.46#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:09:00.47#ibcon#enter wrdev, iclass 37, count 2 2006.239.08:09:00.47#ibcon#first serial, iclass 37, count 2 2006.239.08:09:00.47#ibcon#enter sib2, iclass 37, count 2 2006.239.08:09:00.47#ibcon#flushed, iclass 37, count 2 2006.239.08:09:00.47#ibcon#about to write, iclass 37, count 2 2006.239.08:09:00.47#ibcon#wrote, iclass 37, count 2 2006.239.08:09:00.47#ibcon#about to read 3, iclass 37, count 2 2006.239.08:09:00.49#ibcon#read 3, iclass 37, count 2 2006.239.08:09:00.49#ibcon#about to read 4, iclass 37, count 2 2006.239.08:09:00.49#ibcon#read 4, iclass 37, count 2 2006.239.08:09:00.49#ibcon#about to read 5, iclass 37, count 2 2006.239.08:09:00.49#ibcon#read 5, iclass 37, count 2 2006.239.08:09:00.49#ibcon#about to read 6, iclass 37, count 2 2006.239.08:09:00.49#ibcon#read 6, iclass 37, count 2 2006.239.08:09:00.49#ibcon#end of sib2, iclass 37, count 2 2006.239.08:09:00.49#ibcon#*mode == 0, iclass 37, count 2 2006.239.08:09:00.49#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.08:09:00.49#ibcon#[25=AT08-07\r\n] 2006.239.08:09:00.49#ibcon#*before write, iclass 37, count 2 2006.239.08:09:00.49#ibcon#enter sib2, iclass 37, count 2 2006.239.08:09:00.49#ibcon#flushed, iclass 37, count 2 2006.239.08:09:00.49#ibcon#about to write, iclass 37, count 2 2006.239.08:09:00.49#ibcon#wrote, iclass 37, count 2 2006.239.08:09:00.49#ibcon#about to read 3, iclass 37, count 2 2006.239.08:09:00.51#ibcon#read 3, iclass 37, count 2 2006.239.08:09:00.52#ibcon#about to read 4, iclass 37, count 2 2006.239.08:09:00.52#ibcon#read 4, iclass 37, count 2 2006.239.08:09:00.52#ibcon#about to read 5, iclass 37, count 2 2006.239.08:09:00.52#ibcon#read 5, iclass 37, count 2 2006.239.08:09:00.52#ibcon#about to read 6, iclass 37, count 2 2006.239.08:09:00.52#ibcon#read 6, iclass 37, count 2 2006.239.08:09:00.52#ibcon#end of sib2, iclass 37, count 2 2006.239.08:09:00.52#ibcon#*after write, iclass 37, count 2 2006.239.08:09:00.52#ibcon#*before return 0, iclass 37, count 2 2006.239.08:09:00.52#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:09:00.52#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:09:00.52#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.08:09:00.52#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:00.52#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:09:00.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:09:00.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:09:00.64#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:09:00.64#ibcon#first serial, iclass 37, count 0 2006.239.08:09:00.64#ibcon#enter sib2, iclass 37, count 0 2006.239.08:09:00.64#ibcon#flushed, iclass 37, count 0 2006.239.08:09:00.64#ibcon#about to write, iclass 37, count 0 2006.239.08:09:00.64#ibcon#wrote, iclass 37, count 0 2006.239.08:09:00.64#ibcon#about to read 3, iclass 37, count 0 2006.239.08:09:00.65#ibcon#read 3, iclass 37, count 0 2006.239.08:09:00.66#ibcon#about to read 4, iclass 37, count 0 2006.239.08:09:00.66#ibcon#read 4, iclass 37, count 0 2006.239.08:09:00.66#ibcon#about to read 5, iclass 37, count 0 2006.239.08:09:00.66#ibcon#read 5, iclass 37, count 0 2006.239.08:09:00.66#ibcon#about to read 6, iclass 37, count 0 2006.239.08:09:00.66#ibcon#read 6, iclass 37, count 0 2006.239.08:09:00.66#ibcon#end of sib2, iclass 37, count 0 2006.239.08:09:00.66#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:09:00.66#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:09:00.66#ibcon#[25=USB\r\n] 2006.239.08:09:00.66#ibcon#*before write, iclass 37, count 0 2006.239.08:09:00.66#ibcon#enter sib2, iclass 37, count 0 2006.239.08:09:00.66#ibcon#flushed, iclass 37, count 0 2006.239.08:09:00.66#ibcon#about to write, iclass 37, count 0 2006.239.08:09:00.66#ibcon#wrote, iclass 37, count 0 2006.239.08:09:00.66#ibcon#about to read 3, iclass 37, count 0 2006.239.08:09:00.68#ibcon#read 3, iclass 37, count 0 2006.239.08:09:00.69#ibcon#about to read 4, iclass 37, count 0 2006.239.08:09:00.69#ibcon#read 4, iclass 37, count 0 2006.239.08:09:00.69#ibcon#about to read 5, iclass 37, count 0 2006.239.08:09:00.69#ibcon#read 5, iclass 37, count 0 2006.239.08:09:00.69#ibcon#about to read 6, iclass 37, count 0 2006.239.08:09:00.69#ibcon#read 6, iclass 37, count 0 2006.239.08:09:00.69#ibcon#end of sib2, iclass 37, count 0 2006.239.08:09:00.69#ibcon#*after write, iclass 37, count 0 2006.239.08:09:00.69#ibcon#*before return 0, iclass 37, count 0 2006.239.08:09:00.69#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:09:00.69#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:09:00.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:09:00.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:09:00.69$vc4f8/vblo=1,632.99 2006.239.08:09:00.69#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:09:00.69#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:09:00.69#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:00.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:09:00.69#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:09:00.69#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:09:00.69#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:09:00.69#ibcon#first serial, iclass 39, count 0 2006.239.08:09:00.69#ibcon#enter sib2, iclass 39, count 0 2006.239.08:09:00.69#ibcon#flushed, iclass 39, count 0 2006.239.08:09:00.69#ibcon#about to write, iclass 39, count 0 2006.239.08:09:00.69#ibcon#wrote, iclass 39, count 0 2006.239.08:09:00.69#ibcon#about to read 3, iclass 39, count 0 2006.239.08:09:00.70#ibcon#read 3, iclass 39, count 0 2006.239.08:09:00.71#ibcon#about to read 4, iclass 39, count 0 2006.239.08:09:00.71#ibcon#read 4, iclass 39, count 0 2006.239.08:09:00.71#ibcon#about to read 5, iclass 39, count 0 2006.239.08:09:00.71#ibcon#read 5, iclass 39, count 0 2006.239.08:09:00.71#ibcon#about to read 6, iclass 39, count 0 2006.239.08:09:00.71#ibcon#read 6, iclass 39, count 0 2006.239.08:09:00.71#ibcon#end of sib2, iclass 39, count 0 2006.239.08:09:00.71#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:09:00.71#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:09:00.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:09:00.71#ibcon#*before write, iclass 39, count 0 2006.239.08:09:00.71#ibcon#enter sib2, iclass 39, count 0 2006.239.08:09:00.71#ibcon#flushed, iclass 39, count 0 2006.239.08:09:00.71#ibcon#about to write, iclass 39, count 0 2006.239.08:09:00.71#ibcon#wrote, iclass 39, count 0 2006.239.08:09:00.71#ibcon#about to read 3, iclass 39, count 0 2006.239.08:09:00.74#ibcon#read 3, iclass 39, count 0 2006.239.08:09:00.75#ibcon#about to read 4, iclass 39, count 0 2006.239.08:09:00.75#ibcon#read 4, iclass 39, count 0 2006.239.08:09:00.75#ibcon#about to read 5, iclass 39, count 0 2006.239.08:09:00.75#ibcon#read 5, iclass 39, count 0 2006.239.08:09:00.75#ibcon#about to read 6, iclass 39, count 0 2006.239.08:09:00.75#ibcon#read 6, iclass 39, count 0 2006.239.08:09:00.75#ibcon#end of sib2, iclass 39, count 0 2006.239.08:09:00.75#ibcon#*after write, iclass 39, count 0 2006.239.08:09:00.75#ibcon#*before return 0, iclass 39, count 0 2006.239.08:09:00.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:09:00.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:09:00.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:09:00.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:09:00.75$vc4f8/vb=1,4 2006.239.08:09:00.75#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.08:09:00.75#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.08:09:00.75#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:00.75#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:09:00.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:09:00.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:09:00.75#ibcon#enter wrdev, iclass 3, count 2 2006.239.08:09:00.75#ibcon#first serial, iclass 3, count 2 2006.239.08:09:00.75#ibcon#enter sib2, iclass 3, count 2 2006.239.08:09:00.75#ibcon#flushed, iclass 3, count 2 2006.239.08:09:00.75#ibcon#about to write, iclass 3, count 2 2006.239.08:09:00.75#ibcon#wrote, iclass 3, count 2 2006.239.08:09:00.75#ibcon#about to read 3, iclass 3, count 2 2006.239.08:09:00.76#ibcon#read 3, iclass 3, count 2 2006.239.08:09:00.77#ibcon#about to read 4, iclass 3, count 2 2006.239.08:09:00.77#ibcon#read 4, iclass 3, count 2 2006.239.08:09:00.77#ibcon#about to read 5, iclass 3, count 2 2006.239.08:09:00.77#ibcon#read 5, iclass 3, count 2 2006.239.08:09:00.77#ibcon#about to read 6, iclass 3, count 2 2006.239.08:09:00.77#ibcon#read 6, iclass 3, count 2 2006.239.08:09:00.77#ibcon#end of sib2, iclass 3, count 2 2006.239.08:09:00.77#ibcon#*mode == 0, iclass 3, count 2 2006.239.08:09:00.77#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.08:09:00.77#ibcon#[27=AT01-04\r\n] 2006.239.08:09:00.77#ibcon#*before write, iclass 3, count 2 2006.239.08:09:00.77#ibcon#enter sib2, iclass 3, count 2 2006.239.08:09:00.77#ibcon#flushed, iclass 3, count 2 2006.239.08:09:00.77#ibcon#about to write, iclass 3, count 2 2006.239.08:09:00.77#ibcon#wrote, iclass 3, count 2 2006.239.08:09:00.77#ibcon#about to read 3, iclass 3, count 2 2006.239.08:09:00.79#ibcon#read 3, iclass 3, count 2 2006.239.08:09:00.80#ibcon#about to read 4, iclass 3, count 2 2006.239.08:09:00.80#ibcon#read 4, iclass 3, count 2 2006.239.08:09:00.80#ibcon#about to read 5, iclass 3, count 2 2006.239.08:09:00.80#ibcon#read 5, iclass 3, count 2 2006.239.08:09:00.80#ibcon#about to read 6, iclass 3, count 2 2006.239.08:09:00.80#ibcon#read 6, iclass 3, count 2 2006.239.08:09:00.80#ibcon#end of sib2, iclass 3, count 2 2006.239.08:09:00.80#ibcon#*after write, iclass 3, count 2 2006.239.08:09:00.80#ibcon#*before return 0, iclass 3, count 2 2006.239.08:09:00.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:09:00.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:09:00.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.08:09:00.80#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:00.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:09:00.91#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:09:00.91#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:09:00.92#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:09:00.92#ibcon#first serial, iclass 3, count 0 2006.239.08:09:00.92#ibcon#enter sib2, iclass 3, count 0 2006.239.08:09:00.92#ibcon#flushed, iclass 3, count 0 2006.239.08:09:00.92#ibcon#about to write, iclass 3, count 0 2006.239.08:09:00.92#ibcon#wrote, iclass 3, count 0 2006.239.08:09:00.92#ibcon#about to read 3, iclass 3, count 0 2006.239.08:09:00.93#ibcon#read 3, iclass 3, count 0 2006.239.08:09:00.94#ibcon#about to read 4, iclass 3, count 0 2006.239.08:09:00.94#ibcon#read 4, iclass 3, count 0 2006.239.08:09:00.94#ibcon#about to read 5, iclass 3, count 0 2006.239.08:09:00.94#ibcon#read 5, iclass 3, count 0 2006.239.08:09:00.94#ibcon#about to read 6, iclass 3, count 0 2006.239.08:09:00.94#ibcon#read 6, iclass 3, count 0 2006.239.08:09:00.94#ibcon#end of sib2, iclass 3, count 0 2006.239.08:09:00.94#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:09:00.94#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:09:00.94#ibcon#[27=USB\r\n] 2006.239.08:09:00.94#ibcon#*before write, iclass 3, count 0 2006.239.08:09:00.94#ibcon#enter sib2, iclass 3, count 0 2006.239.08:09:00.94#ibcon#flushed, iclass 3, count 0 2006.239.08:09:00.94#ibcon#about to write, iclass 3, count 0 2006.239.08:09:00.94#ibcon#wrote, iclass 3, count 0 2006.239.08:09:00.94#ibcon#about to read 3, iclass 3, count 0 2006.239.08:09:00.96#ibcon#read 3, iclass 3, count 0 2006.239.08:09:00.97#ibcon#about to read 4, iclass 3, count 0 2006.239.08:09:00.97#ibcon#read 4, iclass 3, count 0 2006.239.08:09:00.97#ibcon#about to read 5, iclass 3, count 0 2006.239.08:09:00.97#ibcon#read 5, iclass 3, count 0 2006.239.08:09:00.97#ibcon#about to read 6, iclass 3, count 0 2006.239.08:09:00.97#ibcon#read 6, iclass 3, count 0 2006.239.08:09:00.97#ibcon#end of sib2, iclass 3, count 0 2006.239.08:09:00.97#ibcon#*after write, iclass 3, count 0 2006.239.08:09:00.97#ibcon#*before return 0, iclass 3, count 0 2006.239.08:09:00.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:09:00.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:09:00.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:09:00.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:09:00.97$vc4f8/vblo=2,640.99 2006.239.08:09:00.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:09:00.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:09:00.97#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:00.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:09:00.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:09:00.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:09:00.97#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:09:00.97#ibcon#first serial, iclass 5, count 0 2006.239.08:09:00.97#ibcon#enter sib2, iclass 5, count 0 2006.239.08:09:00.97#ibcon#flushed, iclass 5, count 0 2006.239.08:09:00.97#ibcon#about to write, iclass 5, count 0 2006.239.08:09:00.97#ibcon#wrote, iclass 5, count 0 2006.239.08:09:00.97#ibcon#about to read 3, iclass 5, count 0 2006.239.08:09:00.98#ibcon#read 3, iclass 5, count 0 2006.239.08:09:00.99#ibcon#about to read 4, iclass 5, count 0 2006.239.08:09:00.99#ibcon#read 4, iclass 5, count 0 2006.239.08:09:00.99#ibcon#about to read 5, iclass 5, count 0 2006.239.08:09:00.99#ibcon#read 5, iclass 5, count 0 2006.239.08:09:00.99#ibcon#about to read 6, iclass 5, count 0 2006.239.08:09:00.99#ibcon#read 6, iclass 5, count 0 2006.239.08:09:00.99#ibcon#end of sib2, iclass 5, count 0 2006.239.08:09:00.99#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:09:00.99#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:09:00.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:09:00.99#ibcon#*before write, iclass 5, count 0 2006.239.08:09:00.99#ibcon#enter sib2, iclass 5, count 0 2006.239.08:09:00.99#ibcon#flushed, iclass 5, count 0 2006.239.08:09:00.99#ibcon#about to write, iclass 5, count 0 2006.239.08:09:00.99#ibcon#wrote, iclass 5, count 0 2006.239.08:09:00.99#ibcon#about to read 3, iclass 5, count 0 2006.239.08:09:01.02#ibcon#read 3, iclass 5, count 0 2006.239.08:09:01.03#ibcon#about to read 4, iclass 5, count 0 2006.239.08:09:01.03#ibcon#read 4, iclass 5, count 0 2006.239.08:09:01.03#ibcon#about to read 5, iclass 5, count 0 2006.239.08:09:01.03#ibcon#read 5, iclass 5, count 0 2006.239.08:09:01.03#ibcon#about to read 6, iclass 5, count 0 2006.239.08:09:01.03#ibcon#read 6, iclass 5, count 0 2006.239.08:09:01.03#ibcon#end of sib2, iclass 5, count 0 2006.239.08:09:01.03#ibcon#*after write, iclass 5, count 0 2006.239.08:09:01.03#ibcon#*before return 0, iclass 5, count 0 2006.239.08:09:01.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:09:01.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:09:01.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:09:01.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:09:01.03$vc4f8/vb=2,4 2006.239.08:09:01.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.08:09:01.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.08:09:01.03#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:01.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:09:01.08#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:09:01.08#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:09:01.09#ibcon#enter wrdev, iclass 7, count 2 2006.239.08:09:01.09#ibcon#first serial, iclass 7, count 2 2006.239.08:09:01.09#ibcon#enter sib2, iclass 7, count 2 2006.239.08:09:01.09#ibcon#flushed, iclass 7, count 2 2006.239.08:09:01.09#ibcon#about to write, iclass 7, count 2 2006.239.08:09:01.09#ibcon#wrote, iclass 7, count 2 2006.239.08:09:01.09#ibcon#about to read 3, iclass 7, count 2 2006.239.08:09:01.10#ibcon#read 3, iclass 7, count 2 2006.239.08:09:01.11#ibcon#about to read 4, iclass 7, count 2 2006.239.08:09:01.11#ibcon#read 4, iclass 7, count 2 2006.239.08:09:01.11#ibcon#about to read 5, iclass 7, count 2 2006.239.08:09:01.11#ibcon#read 5, iclass 7, count 2 2006.239.08:09:01.11#ibcon#about to read 6, iclass 7, count 2 2006.239.08:09:01.11#ibcon#read 6, iclass 7, count 2 2006.239.08:09:01.11#ibcon#end of sib2, iclass 7, count 2 2006.239.08:09:01.11#ibcon#*mode == 0, iclass 7, count 2 2006.239.08:09:01.11#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.08:09:01.11#ibcon#[27=AT02-04\r\n] 2006.239.08:09:01.11#ibcon#*before write, iclass 7, count 2 2006.239.08:09:01.11#ibcon#enter sib2, iclass 7, count 2 2006.239.08:09:01.11#ibcon#flushed, iclass 7, count 2 2006.239.08:09:01.11#ibcon#about to write, iclass 7, count 2 2006.239.08:09:01.11#ibcon#wrote, iclass 7, count 2 2006.239.08:09:01.11#ibcon#about to read 3, iclass 7, count 2 2006.239.08:09:01.13#ibcon#read 3, iclass 7, count 2 2006.239.08:09:01.14#ibcon#about to read 4, iclass 7, count 2 2006.239.08:09:01.14#ibcon#read 4, iclass 7, count 2 2006.239.08:09:01.14#ibcon#about to read 5, iclass 7, count 2 2006.239.08:09:01.14#ibcon#read 5, iclass 7, count 2 2006.239.08:09:01.14#ibcon#about to read 6, iclass 7, count 2 2006.239.08:09:01.14#ibcon#read 6, iclass 7, count 2 2006.239.08:09:01.14#ibcon#end of sib2, iclass 7, count 2 2006.239.08:09:01.14#ibcon#*after write, iclass 7, count 2 2006.239.08:09:01.14#ibcon#*before return 0, iclass 7, count 2 2006.239.08:09:01.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:09:01.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:09:01.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.08:09:01.14#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:01.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:09:01.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:09:01.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:09:01.27#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:09:01.27#ibcon#first serial, iclass 7, count 0 2006.239.08:09:01.27#ibcon#enter sib2, iclass 7, count 0 2006.239.08:09:01.27#ibcon#flushed, iclass 7, count 0 2006.239.08:09:01.27#ibcon#about to write, iclass 7, count 0 2006.239.08:09:01.27#ibcon#wrote, iclass 7, count 0 2006.239.08:09:01.27#ibcon#about to read 3, iclass 7, count 0 2006.239.08:09:01.29#ibcon#read 3, iclass 7, count 0 2006.239.08:09:01.29#ibcon#about to read 4, iclass 7, count 0 2006.239.08:09:01.29#ibcon#read 4, iclass 7, count 0 2006.239.08:09:01.29#ibcon#about to read 5, iclass 7, count 0 2006.239.08:09:01.29#ibcon#read 5, iclass 7, count 0 2006.239.08:09:01.29#ibcon#about to read 6, iclass 7, count 0 2006.239.08:09:01.29#ibcon#read 6, iclass 7, count 0 2006.239.08:09:01.29#ibcon#end of sib2, iclass 7, count 0 2006.239.08:09:01.29#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:09:01.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:09:01.29#ibcon#[27=USB\r\n] 2006.239.08:09:01.29#ibcon#*before write, iclass 7, count 0 2006.239.08:09:01.29#ibcon#enter sib2, iclass 7, count 0 2006.239.08:09:01.29#ibcon#flushed, iclass 7, count 0 2006.239.08:09:01.29#ibcon#about to write, iclass 7, count 0 2006.239.08:09:01.29#ibcon#wrote, iclass 7, count 0 2006.239.08:09:01.29#ibcon#about to read 3, iclass 7, count 0 2006.239.08:09:01.31#ibcon#read 3, iclass 7, count 0 2006.239.08:09:01.31#ibcon#about to read 4, iclass 7, count 0 2006.239.08:09:01.32#ibcon#read 4, iclass 7, count 0 2006.239.08:09:01.32#ibcon#about to read 5, iclass 7, count 0 2006.239.08:09:01.32#ibcon#read 5, iclass 7, count 0 2006.239.08:09:01.32#ibcon#about to read 6, iclass 7, count 0 2006.239.08:09:01.32#ibcon#read 6, iclass 7, count 0 2006.239.08:09:01.32#ibcon#end of sib2, iclass 7, count 0 2006.239.08:09:01.32#ibcon#*after write, iclass 7, count 0 2006.239.08:09:01.32#ibcon#*before return 0, iclass 7, count 0 2006.239.08:09:01.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:09:01.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:09:01.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:09:01.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:09:01.32$vc4f8/vblo=3,656.99 2006.239.08:09:01.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.08:09:01.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.08:09:01.32#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:01.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:09:01.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:09:01.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:09:01.32#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:09:01.32#ibcon#first serial, iclass 11, count 0 2006.239.08:09:01.32#ibcon#enter sib2, iclass 11, count 0 2006.239.08:09:01.32#ibcon#flushed, iclass 11, count 0 2006.239.08:09:01.32#ibcon#about to write, iclass 11, count 0 2006.239.08:09:01.32#ibcon#wrote, iclass 11, count 0 2006.239.08:09:01.32#ibcon#about to read 3, iclass 11, count 0 2006.239.08:09:01.33#ibcon#read 3, iclass 11, count 0 2006.239.08:09:01.34#ibcon#about to read 4, iclass 11, count 0 2006.239.08:09:01.34#ibcon#read 4, iclass 11, count 0 2006.239.08:09:01.34#ibcon#about to read 5, iclass 11, count 0 2006.239.08:09:01.34#ibcon#read 5, iclass 11, count 0 2006.239.08:09:01.34#ibcon#about to read 6, iclass 11, count 0 2006.239.08:09:01.34#ibcon#read 6, iclass 11, count 0 2006.239.08:09:01.34#ibcon#end of sib2, iclass 11, count 0 2006.239.08:09:01.34#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:09:01.34#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:09:01.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:09:01.34#ibcon#*before write, iclass 11, count 0 2006.239.08:09:01.34#ibcon#enter sib2, iclass 11, count 0 2006.239.08:09:01.34#ibcon#flushed, iclass 11, count 0 2006.239.08:09:01.34#ibcon#about to write, iclass 11, count 0 2006.239.08:09:01.34#ibcon#wrote, iclass 11, count 0 2006.239.08:09:01.34#ibcon#about to read 3, iclass 11, count 0 2006.239.08:09:01.37#ibcon#read 3, iclass 11, count 0 2006.239.08:09:01.38#ibcon#about to read 4, iclass 11, count 0 2006.239.08:09:01.38#ibcon#read 4, iclass 11, count 0 2006.239.08:09:01.38#ibcon#about to read 5, iclass 11, count 0 2006.239.08:09:01.38#ibcon#read 5, iclass 11, count 0 2006.239.08:09:01.38#ibcon#about to read 6, iclass 11, count 0 2006.239.08:09:01.38#ibcon#read 6, iclass 11, count 0 2006.239.08:09:01.38#ibcon#end of sib2, iclass 11, count 0 2006.239.08:09:01.38#ibcon#*after write, iclass 11, count 0 2006.239.08:09:01.38#ibcon#*before return 0, iclass 11, count 0 2006.239.08:09:01.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:09:01.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:09:01.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:09:01.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:09:01.38$vc4f8/vb=3,4 2006.239.08:09:01.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.08:09:01.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.08:09:01.38#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:01.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:09:01.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:09:01.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:09:01.44#ibcon#enter wrdev, iclass 13, count 2 2006.239.08:09:01.44#ibcon#first serial, iclass 13, count 2 2006.239.08:09:01.44#ibcon#enter sib2, iclass 13, count 2 2006.239.08:09:01.44#ibcon#flushed, iclass 13, count 2 2006.239.08:09:01.44#ibcon#about to write, iclass 13, count 2 2006.239.08:09:01.44#ibcon#wrote, iclass 13, count 2 2006.239.08:09:01.44#ibcon#about to read 3, iclass 13, count 2 2006.239.08:09:01.45#ibcon#read 3, iclass 13, count 2 2006.239.08:09:01.46#ibcon#about to read 4, iclass 13, count 2 2006.239.08:09:01.46#ibcon#read 4, iclass 13, count 2 2006.239.08:09:01.46#ibcon#about to read 5, iclass 13, count 2 2006.239.08:09:01.46#ibcon#read 5, iclass 13, count 2 2006.239.08:09:01.46#ibcon#about to read 6, iclass 13, count 2 2006.239.08:09:01.46#ibcon#read 6, iclass 13, count 2 2006.239.08:09:01.46#ibcon#end of sib2, iclass 13, count 2 2006.239.08:09:01.46#ibcon#*mode == 0, iclass 13, count 2 2006.239.08:09:01.46#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.08:09:01.46#ibcon#[27=AT03-04\r\n] 2006.239.08:09:01.46#ibcon#*before write, iclass 13, count 2 2006.239.08:09:01.46#ibcon#enter sib2, iclass 13, count 2 2006.239.08:09:01.46#ibcon#flushed, iclass 13, count 2 2006.239.08:09:01.46#ibcon#about to write, iclass 13, count 2 2006.239.08:09:01.46#ibcon#wrote, iclass 13, count 2 2006.239.08:09:01.46#ibcon#about to read 3, iclass 13, count 2 2006.239.08:09:01.48#ibcon#read 3, iclass 13, count 2 2006.239.08:09:01.49#ibcon#about to read 4, iclass 13, count 2 2006.239.08:09:01.49#ibcon#read 4, iclass 13, count 2 2006.239.08:09:01.49#ibcon#about to read 5, iclass 13, count 2 2006.239.08:09:01.49#ibcon#read 5, iclass 13, count 2 2006.239.08:09:01.49#ibcon#about to read 6, iclass 13, count 2 2006.239.08:09:01.49#ibcon#read 6, iclass 13, count 2 2006.239.08:09:01.49#ibcon#end of sib2, iclass 13, count 2 2006.239.08:09:01.49#ibcon#*after write, iclass 13, count 2 2006.239.08:09:01.49#ibcon#*before return 0, iclass 13, count 2 2006.239.08:09:01.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:09:01.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:09:01.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.08:09:01.49#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:01.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:09:01.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:09:01.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:09:01.61#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:09:01.61#ibcon#first serial, iclass 13, count 0 2006.239.08:09:01.61#ibcon#enter sib2, iclass 13, count 0 2006.239.08:09:01.61#ibcon#flushed, iclass 13, count 0 2006.239.08:09:01.61#ibcon#about to write, iclass 13, count 0 2006.239.08:09:01.61#ibcon#wrote, iclass 13, count 0 2006.239.08:09:01.61#ibcon#about to read 3, iclass 13, count 0 2006.239.08:09:01.62#ibcon#read 3, iclass 13, count 0 2006.239.08:09:01.63#ibcon#about to read 4, iclass 13, count 0 2006.239.08:09:01.63#ibcon#read 4, iclass 13, count 0 2006.239.08:09:01.63#ibcon#about to read 5, iclass 13, count 0 2006.239.08:09:01.63#ibcon#read 5, iclass 13, count 0 2006.239.08:09:01.63#ibcon#about to read 6, iclass 13, count 0 2006.239.08:09:01.63#ibcon#read 6, iclass 13, count 0 2006.239.08:09:01.63#ibcon#end of sib2, iclass 13, count 0 2006.239.08:09:01.63#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:09:01.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:09:01.63#ibcon#[27=USB\r\n] 2006.239.08:09:01.63#ibcon#*before write, iclass 13, count 0 2006.239.08:09:01.63#ibcon#enter sib2, iclass 13, count 0 2006.239.08:09:01.63#ibcon#flushed, iclass 13, count 0 2006.239.08:09:01.63#ibcon#about to write, iclass 13, count 0 2006.239.08:09:01.63#ibcon#wrote, iclass 13, count 0 2006.239.08:09:01.63#ibcon#about to read 3, iclass 13, count 0 2006.239.08:09:01.65#ibcon#read 3, iclass 13, count 0 2006.239.08:09:01.66#ibcon#about to read 4, iclass 13, count 0 2006.239.08:09:01.66#ibcon#read 4, iclass 13, count 0 2006.239.08:09:01.66#ibcon#about to read 5, iclass 13, count 0 2006.239.08:09:01.66#ibcon#read 5, iclass 13, count 0 2006.239.08:09:01.66#ibcon#about to read 6, iclass 13, count 0 2006.239.08:09:01.66#ibcon#read 6, iclass 13, count 0 2006.239.08:09:01.66#ibcon#end of sib2, iclass 13, count 0 2006.239.08:09:01.66#ibcon#*after write, iclass 13, count 0 2006.239.08:09:01.66#ibcon#*before return 0, iclass 13, count 0 2006.239.08:09:01.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:09:01.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:09:01.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:09:01.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:09:01.66$vc4f8/vblo=4,712.99 2006.239.08:09:01.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.08:09:01.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.08:09:01.66#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:01.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:09:01.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:09:01.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:09:01.66#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:09:01.66#ibcon#first serial, iclass 15, count 0 2006.239.08:09:01.66#ibcon#enter sib2, iclass 15, count 0 2006.239.08:09:01.66#ibcon#flushed, iclass 15, count 0 2006.239.08:09:01.66#ibcon#about to write, iclass 15, count 0 2006.239.08:09:01.66#ibcon#wrote, iclass 15, count 0 2006.239.08:09:01.66#ibcon#about to read 3, iclass 15, count 0 2006.239.08:09:01.68#ibcon#read 3, iclass 15, count 0 2006.239.08:09:01.68#ibcon#about to read 4, iclass 15, count 0 2006.239.08:09:01.68#ibcon#read 4, iclass 15, count 0 2006.239.08:09:01.68#ibcon#about to read 5, iclass 15, count 0 2006.239.08:09:01.68#ibcon#read 5, iclass 15, count 0 2006.239.08:09:01.68#ibcon#about to read 6, iclass 15, count 0 2006.239.08:09:01.68#ibcon#read 6, iclass 15, count 0 2006.239.08:09:01.68#ibcon#end of sib2, iclass 15, count 0 2006.239.08:09:01.68#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:09:01.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:09:01.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:09:01.68#ibcon#*before write, iclass 15, count 0 2006.239.08:09:01.68#ibcon#enter sib2, iclass 15, count 0 2006.239.08:09:01.68#ibcon#flushed, iclass 15, count 0 2006.239.08:09:01.68#ibcon#about to write, iclass 15, count 0 2006.239.08:09:01.68#ibcon#wrote, iclass 15, count 0 2006.239.08:09:01.68#ibcon#about to read 3, iclass 15, count 0 2006.239.08:09:01.71#ibcon#read 3, iclass 15, count 0 2006.239.08:09:01.72#ibcon#about to read 4, iclass 15, count 0 2006.239.08:09:01.72#ibcon#read 4, iclass 15, count 0 2006.239.08:09:01.72#ibcon#about to read 5, iclass 15, count 0 2006.239.08:09:01.72#ibcon#read 5, iclass 15, count 0 2006.239.08:09:01.72#ibcon#about to read 6, iclass 15, count 0 2006.239.08:09:01.72#ibcon#read 6, iclass 15, count 0 2006.239.08:09:01.72#ibcon#end of sib2, iclass 15, count 0 2006.239.08:09:01.72#ibcon#*after write, iclass 15, count 0 2006.239.08:09:01.72#ibcon#*before return 0, iclass 15, count 0 2006.239.08:09:01.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:09:01.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:09:01.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:09:01.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:09:01.72$vc4f8/vb=4,4 2006.239.08:09:01.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.08:09:01.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.08:09:01.72#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:01.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:09:01.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:09:01.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:09:01.78#ibcon#enter wrdev, iclass 17, count 2 2006.239.08:09:01.78#ibcon#first serial, iclass 17, count 2 2006.239.08:09:01.78#ibcon#enter sib2, iclass 17, count 2 2006.239.08:09:01.78#ibcon#flushed, iclass 17, count 2 2006.239.08:09:01.78#ibcon#about to write, iclass 17, count 2 2006.239.08:09:01.78#ibcon#wrote, iclass 17, count 2 2006.239.08:09:01.78#ibcon#about to read 3, iclass 17, count 2 2006.239.08:09:01.79#ibcon#read 3, iclass 17, count 2 2006.239.08:09:01.80#ibcon#about to read 4, iclass 17, count 2 2006.239.08:09:01.80#ibcon#read 4, iclass 17, count 2 2006.239.08:09:01.80#ibcon#about to read 5, iclass 17, count 2 2006.239.08:09:01.80#ibcon#read 5, iclass 17, count 2 2006.239.08:09:01.80#ibcon#about to read 6, iclass 17, count 2 2006.239.08:09:01.80#ibcon#read 6, iclass 17, count 2 2006.239.08:09:01.80#ibcon#end of sib2, iclass 17, count 2 2006.239.08:09:01.80#ibcon#*mode == 0, iclass 17, count 2 2006.239.08:09:01.80#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.08:09:01.80#ibcon#[27=AT04-04\r\n] 2006.239.08:09:01.80#ibcon#*before write, iclass 17, count 2 2006.239.08:09:01.80#ibcon#enter sib2, iclass 17, count 2 2006.239.08:09:01.80#ibcon#flushed, iclass 17, count 2 2006.239.08:09:01.80#ibcon#about to write, iclass 17, count 2 2006.239.08:09:01.80#ibcon#wrote, iclass 17, count 2 2006.239.08:09:01.80#ibcon#about to read 3, iclass 17, count 2 2006.239.08:09:01.82#ibcon#read 3, iclass 17, count 2 2006.239.08:09:01.83#ibcon#about to read 4, iclass 17, count 2 2006.239.08:09:01.83#ibcon#read 4, iclass 17, count 2 2006.239.08:09:01.83#ibcon#about to read 5, iclass 17, count 2 2006.239.08:09:01.83#ibcon#read 5, iclass 17, count 2 2006.239.08:09:01.83#ibcon#about to read 6, iclass 17, count 2 2006.239.08:09:01.83#ibcon#read 6, iclass 17, count 2 2006.239.08:09:01.83#ibcon#end of sib2, iclass 17, count 2 2006.239.08:09:01.83#ibcon#*after write, iclass 17, count 2 2006.239.08:09:01.83#ibcon#*before return 0, iclass 17, count 2 2006.239.08:09:01.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:09:01.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:09:01.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.08:09:01.83#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:01.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:09:01.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:09:01.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:09:01.94#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:09:01.95#ibcon#first serial, iclass 17, count 0 2006.239.08:09:01.95#ibcon#enter sib2, iclass 17, count 0 2006.239.08:09:01.95#ibcon#flushed, iclass 17, count 0 2006.239.08:09:01.95#ibcon#about to write, iclass 17, count 0 2006.239.08:09:01.95#ibcon#wrote, iclass 17, count 0 2006.239.08:09:01.95#ibcon#about to read 3, iclass 17, count 0 2006.239.08:09:01.96#ibcon#read 3, iclass 17, count 0 2006.239.08:09:01.97#ibcon#about to read 4, iclass 17, count 0 2006.239.08:09:01.97#ibcon#read 4, iclass 17, count 0 2006.239.08:09:01.97#ibcon#about to read 5, iclass 17, count 0 2006.239.08:09:01.97#ibcon#read 5, iclass 17, count 0 2006.239.08:09:01.97#ibcon#about to read 6, iclass 17, count 0 2006.239.08:09:01.97#ibcon#read 6, iclass 17, count 0 2006.239.08:09:01.97#ibcon#end of sib2, iclass 17, count 0 2006.239.08:09:01.97#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:09:01.97#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:09:01.97#ibcon#[27=USB\r\n] 2006.239.08:09:01.97#ibcon#*before write, iclass 17, count 0 2006.239.08:09:01.97#ibcon#enter sib2, iclass 17, count 0 2006.239.08:09:01.97#ibcon#flushed, iclass 17, count 0 2006.239.08:09:01.97#ibcon#about to write, iclass 17, count 0 2006.239.08:09:01.97#ibcon#wrote, iclass 17, count 0 2006.239.08:09:01.97#ibcon#about to read 3, iclass 17, count 0 2006.239.08:09:01.99#ibcon#read 3, iclass 17, count 0 2006.239.08:09:02.00#ibcon#about to read 4, iclass 17, count 0 2006.239.08:09:02.00#ibcon#read 4, iclass 17, count 0 2006.239.08:09:02.00#ibcon#about to read 5, iclass 17, count 0 2006.239.08:09:02.00#ibcon#read 5, iclass 17, count 0 2006.239.08:09:02.00#ibcon#about to read 6, iclass 17, count 0 2006.239.08:09:02.00#ibcon#read 6, iclass 17, count 0 2006.239.08:09:02.00#ibcon#end of sib2, iclass 17, count 0 2006.239.08:09:02.00#ibcon#*after write, iclass 17, count 0 2006.239.08:09:02.00#ibcon#*before return 0, iclass 17, count 0 2006.239.08:09:02.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:09:02.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:09:02.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:09:02.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:09:02.00$vc4f8/vblo=5,744.99 2006.239.08:09:02.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.08:09:02.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.08:09:02.00#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:02.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:09:02.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:09:02.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:09:02.00#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:09:02.00#ibcon#first serial, iclass 19, count 0 2006.239.08:09:02.00#ibcon#enter sib2, iclass 19, count 0 2006.239.08:09:02.00#ibcon#flushed, iclass 19, count 0 2006.239.08:09:02.00#ibcon#about to write, iclass 19, count 0 2006.239.08:09:02.00#ibcon#wrote, iclass 19, count 0 2006.239.08:09:02.00#ibcon#about to read 3, iclass 19, count 0 2006.239.08:09:02.02#ibcon#read 3, iclass 19, count 0 2006.239.08:09:02.02#ibcon#about to read 4, iclass 19, count 0 2006.239.08:09:02.02#ibcon#read 4, iclass 19, count 0 2006.239.08:09:02.02#ibcon#about to read 5, iclass 19, count 0 2006.239.08:09:02.02#ibcon#read 5, iclass 19, count 0 2006.239.08:09:02.02#ibcon#about to read 6, iclass 19, count 0 2006.239.08:09:02.02#ibcon#read 6, iclass 19, count 0 2006.239.08:09:02.02#ibcon#end of sib2, iclass 19, count 0 2006.239.08:09:02.02#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:09:02.02#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:09:02.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:09:02.02#ibcon#*before write, iclass 19, count 0 2006.239.08:09:02.02#ibcon#enter sib2, iclass 19, count 0 2006.239.08:09:02.02#ibcon#flushed, iclass 19, count 0 2006.239.08:09:02.02#ibcon#about to write, iclass 19, count 0 2006.239.08:09:02.02#ibcon#wrote, iclass 19, count 0 2006.239.08:09:02.02#ibcon#about to read 3, iclass 19, count 0 2006.239.08:09:02.05#ibcon#read 3, iclass 19, count 0 2006.239.08:09:02.06#ibcon#about to read 4, iclass 19, count 0 2006.239.08:09:02.06#ibcon#read 4, iclass 19, count 0 2006.239.08:09:02.06#ibcon#about to read 5, iclass 19, count 0 2006.239.08:09:02.06#ibcon#read 5, iclass 19, count 0 2006.239.08:09:02.06#ibcon#about to read 6, iclass 19, count 0 2006.239.08:09:02.06#ibcon#read 6, iclass 19, count 0 2006.239.08:09:02.06#ibcon#end of sib2, iclass 19, count 0 2006.239.08:09:02.06#ibcon#*after write, iclass 19, count 0 2006.239.08:09:02.06#ibcon#*before return 0, iclass 19, count 0 2006.239.08:09:02.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:09:02.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:09:02.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:09:02.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:09:02.06$vc4f8/vb=5,4 2006.239.08:09:02.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.08:09:02.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.08:09:02.06#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:02.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:09:02.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:09:02.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:09:02.12#ibcon#enter wrdev, iclass 21, count 2 2006.239.08:09:02.12#ibcon#first serial, iclass 21, count 2 2006.239.08:09:02.12#ibcon#enter sib2, iclass 21, count 2 2006.239.08:09:02.12#ibcon#flushed, iclass 21, count 2 2006.239.08:09:02.12#ibcon#about to write, iclass 21, count 2 2006.239.08:09:02.12#ibcon#wrote, iclass 21, count 2 2006.239.08:09:02.12#ibcon#about to read 3, iclass 21, count 2 2006.239.08:09:02.13#ibcon#read 3, iclass 21, count 2 2006.239.08:09:02.14#ibcon#about to read 4, iclass 21, count 2 2006.239.08:09:02.14#ibcon#read 4, iclass 21, count 2 2006.239.08:09:02.14#ibcon#about to read 5, iclass 21, count 2 2006.239.08:09:02.14#ibcon#read 5, iclass 21, count 2 2006.239.08:09:02.14#ibcon#about to read 6, iclass 21, count 2 2006.239.08:09:02.14#ibcon#read 6, iclass 21, count 2 2006.239.08:09:02.14#ibcon#end of sib2, iclass 21, count 2 2006.239.08:09:02.14#ibcon#*mode == 0, iclass 21, count 2 2006.239.08:09:02.14#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.08:09:02.14#ibcon#[27=AT05-04\r\n] 2006.239.08:09:02.14#ibcon#*before write, iclass 21, count 2 2006.239.08:09:02.14#ibcon#enter sib2, iclass 21, count 2 2006.239.08:09:02.14#ibcon#flushed, iclass 21, count 2 2006.239.08:09:02.14#ibcon#about to write, iclass 21, count 2 2006.239.08:09:02.14#ibcon#wrote, iclass 21, count 2 2006.239.08:09:02.14#ibcon#about to read 3, iclass 21, count 2 2006.239.08:09:02.16#ibcon#read 3, iclass 21, count 2 2006.239.08:09:02.17#ibcon#about to read 4, iclass 21, count 2 2006.239.08:09:02.17#ibcon#read 4, iclass 21, count 2 2006.239.08:09:02.17#ibcon#about to read 5, iclass 21, count 2 2006.239.08:09:02.17#ibcon#read 5, iclass 21, count 2 2006.239.08:09:02.17#ibcon#about to read 6, iclass 21, count 2 2006.239.08:09:02.17#ibcon#read 6, iclass 21, count 2 2006.239.08:09:02.17#ibcon#end of sib2, iclass 21, count 2 2006.239.08:09:02.17#ibcon#*after write, iclass 21, count 2 2006.239.08:09:02.17#ibcon#*before return 0, iclass 21, count 2 2006.239.08:09:02.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:09:02.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:09:02.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.08:09:02.17#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:02.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:09:02.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:09:02.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:09:02.29#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:09:02.29#ibcon#first serial, iclass 21, count 0 2006.239.08:09:02.29#ibcon#enter sib2, iclass 21, count 0 2006.239.08:09:02.29#ibcon#flushed, iclass 21, count 0 2006.239.08:09:02.29#ibcon#about to write, iclass 21, count 0 2006.239.08:09:02.29#ibcon#wrote, iclass 21, count 0 2006.239.08:09:02.29#ibcon#about to read 3, iclass 21, count 0 2006.239.08:09:02.30#ibcon#read 3, iclass 21, count 0 2006.239.08:09:02.30#ibcon#about to read 4, iclass 21, count 0 2006.239.08:09:02.31#ibcon#read 4, iclass 21, count 0 2006.239.08:09:02.31#ibcon#about to read 5, iclass 21, count 0 2006.239.08:09:02.31#ibcon#read 5, iclass 21, count 0 2006.239.08:09:02.31#ibcon#about to read 6, iclass 21, count 0 2006.239.08:09:02.31#ibcon#read 6, iclass 21, count 0 2006.239.08:09:02.31#ibcon#end of sib2, iclass 21, count 0 2006.239.08:09:02.31#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:09:02.31#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:09:02.31#ibcon#[27=USB\r\n] 2006.239.08:09:02.31#ibcon#*before write, iclass 21, count 0 2006.239.08:09:02.31#ibcon#enter sib2, iclass 21, count 0 2006.239.08:09:02.31#ibcon#flushed, iclass 21, count 0 2006.239.08:09:02.31#ibcon#about to write, iclass 21, count 0 2006.239.08:09:02.31#ibcon#wrote, iclass 21, count 0 2006.239.08:09:02.31#ibcon#about to read 3, iclass 21, count 0 2006.239.08:09:02.33#ibcon#read 3, iclass 21, count 0 2006.239.08:09:02.34#ibcon#about to read 4, iclass 21, count 0 2006.239.08:09:02.34#ibcon#read 4, iclass 21, count 0 2006.239.08:09:02.34#ibcon#about to read 5, iclass 21, count 0 2006.239.08:09:02.34#ibcon#read 5, iclass 21, count 0 2006.239.08:09:02.34#ibcon#about to read 6, iclass 21, count 0 2006.239.08:09:02.34#ibcon#read 6, iclass 21, count 0 2006.239.08:09:02.34#ibcon#end of sib2, iclass 21, count 0 2006.239.08:09:02.34#ibcon#*after write, iclass 21, count 0 2006.239.08:09:02.34#ibcon#*before return 0, iclass 21, count 0 2006.239.08:09:02.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:09:02.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:09:02.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:09:02.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:09:02.34$vc4f8/vblo=6,752.99 2006.239.08:09:02.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.08:09:02.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.08:09:02.34#ibcon#ireg 17 cls_cnt 0 2006.239.08:09:02.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:09:02.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:09:02.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:09:02.34#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:09:02.34#ibcon#first serial, iclass 23, count 0 2006.239.08:09:02.34#ibcon#enter sib2, iclass 23, count 0 2006.239.08:09:02.34#ibcon#flushed, iclass 23, count 0 2006.239.08:09:02.34#ibcon#about to write, iclass 23, count 0 2006.239.08:09:02.34#ibcon#wrote, iclass 23, count 0 2006.239.08:09:02.34#ibcon#about to read 3, iclass 23, count 0 2006.239.08:09:02.35#ibcon#read 3, iclass 23, count 0 2006.239.08:09:02.36#ibcon#about to read 4, iclass 23, count 0 2006.239.08:09:02.36#ibcon#read 4, iclass 23, count 0 2006.239.08:09:02.36#ibcon#about to read 5, iclass 23, count 0 2006.239.08:09:02.36#ibcon#read 5, iclass 23, count 0 2006.239.08:09:02.36#ibcon#about to read 6, iclass 23, count 0 2006.239.08:09:02.36#ibcon#read 6, iclass 23, count 0 2006.239.08:09:02.36#ibcon#end of sib2, iclass 23, count 0 2006.239.08:09:02.36#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:09:02.36#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:09:02.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:09:02.36#ibcon#*before write, iclass 23, count 0 2006.239.08:09:02.36#ibcon#enter sib2, iclass 23, count 0 2006.239.08:09:02.36#ibcon#flushed, iclass 23, count 0 2006.239.08:09:02.36#ibcon#about to write, iclass 23, count 0 2006.239.08:09:02.36#ibcon#wrote, iclass 23, count 0 2006.239.08:09:02.36#ibcon#about to read 3, iclass 23, count 0 2006.239.08:09:02.40#ibcon#read 3, iclass 23, count 0 2006.239.08:09:02.40#ibcon#about to read 4, iclass 23, count 0 2006.239.08:09:02.40#ibcon#read 4, iclass 23, count 0 2006.239.08:09:02.40#ibcon#about to read 5, iclass 23, count 0 2006.239.08:09:02.40#ibcon#read 5, iclass 23, count 0 2006.239.08:09:02.40#ibcon#about to read 6, iclass 23, count 0 2006.239.08:09:02.40#ibcon#read 6, iclass 23, count 0 2006.239.08:09:02.40#ibcon#end of sib2, iclass 23, count 0 2006.239.08:09:02.40#ibcon#*after write, iclass 23, count 0 2006.239.08:09:02.40#ibcon#*before return 0, iclass 23, count 0 2006.239.08:09:02.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:09:02.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:09:02.40#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:09:02.40#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:09:02.40$vc4f8/vb=6,4 2006.239.08:09:02.40#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.08:09:02.40#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.08:09:02.40#ibcon#ireg 11 cls_cnt 2 2006.239.08:09:02.40#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:09:02.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:09:02.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:09:02.46#ibcon#enter wrdev, iclass 25, count 2 2006.239.08:09:02.46#ibcon#first serial, iclass 25, count 2 2006.239.08:09:02.46#ibcon#enter sib2, iclass 25, count 2 2006.239.08:09:02.46#ibcon#flushed, iclass 25, count 2 2006.239.08:09:02.46#ibcon#about to write, iclass 25, count 2 2006.239.08:09:02.46#ibcon#wrote, iclass 25, count 2 2006.239.08:09:02.46#ibcon#about to read 3, iclass 25, count 2 2006.239.08:09:02.47#ibcon#read 3, iclass 25, count 2 2006.239.08:09:02.47#ibcon#about to read 4, iclass 25, count 2 2006.239.08:09:02.48#ibcon#read 4, iclass 25, count 2 2006.239.08:09:02.48#ibcon#about to read 5, iclass 25, count 2 2006.239.08:09:02.48#ibcon#read 5, iclass 25, count 2 2006.239.08:09:02.48#ibcon#about to read 6, iclass 25, count 2 2006.239.08:09:02.48#ibcon#read 6, iclass 25, count 2 2006.239.08:09:02.48#ibcon#end of sib2, iclass 25, count 2 2006.239.08:09:02.48#ibcon#*mode == 0, iclass 25, count 2 2006.239.08:09:02.48#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.08:09:02.48#ibcon#[27=AT06-04\r\n] 2006.239.08:09:02.48#ibcon#*before write, iclass 25, count 2 2006.239.08:09:02.48#ibcon#enter sib2, iclass 25, count 2 2006.239.08:09:02.48#ibcon#flushed, iclass 25, count 2 2006.239.08:09:02.48#ibcon#about to write, iclass 25, count 2 2006.239.08:09:02.48#ibcon#wrote, iclass 25, count 2 2006.239.08:09:02.48#ibcon#about to read 3, iclass 25, count 2 2006.239.08:09:02.50#ibcon#read 3, iclass 25, count 2 2006.239.08:09:02.51#ibcon#about to read 4, iclass 25, count 2 2006.239.08:09:02.51#ibcon#read 4, iclass 25, count 2 2006.239.08:09:02.51#ibcon#about to read 5, iclass 25, count 2 2006.239.08:09:02.51#ibcon#read 5, iclass 25, count 2 2006.239.08:09:02.51#ibcon#about to read 6, iclass 25, count 2 2006.239.08:09:02.51#ibcon#read 6, iclass 25, count 2 2006.239.08:09:02.51#ibcon#end of sib2, iclass 25, count 2 2006.239.08:09:02.51#ibcon#*after write, iclass 25, count 2 2006.239.08:09:02.51#ibcon#*before return 0, iclass 25, count 2 2006.239.08:09:02.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:09:02.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:09:02.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.08:09:02.51#ibcon#ireg 7 cls_cnt 0 2006.239.08:09:02.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:09:02.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:09:02.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:09:02.63#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:09:02.63#ibcon#first serial, iclass 25, count 0 2006.239.08:09:02.63#ibcon#enter sib2, iclass 25, count 0 2006.239.08:09:02.63#ibcon#flushed, iclass 25, count 0 2006.239.08:09:02.63#ibcon#about to write, iclass 25, count 0 2006.239.08:09:02.63#ibcon#wrote, iclass 25, count 0 2006.239.08:09:02.63#ibcon#about to read 3, iclass 25, count 0 2006.239.08:09:02.64#ibcon#read 3, iclass 25, count 0 2006.239.08:09:02.65#ibcon#about to read 4, iclass 25, count 0 2006.239.08:09:02.65#ibcon#read 4, iclass 25, count 0 2006.239.08:09:02.65#ibcon#about to read 5, iclass 25, count 0 2006.239.08:09:02.65#ibcon#read 5, iclass 25, count 0 2006.239.08:09:02.65#ibcon#about to read 6, iclass 25, count 0 2006.239.08:09:02.65#ibcon#read 6, iclass 25, count 0 2006.239.08:09:02.65#ibcon#end of sib2, iclass 25, count 0 2006.239.08:09:02.65#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:09:02.65#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:09:02.65#ibcon#[27=USB\r\n] 2006.239.08:09:02.65#ibcon#*before write, iclass 25, count 0 2006.239.08:09:02.65#ibcon#enter sib2, iclass 25, count 0 2006.239.08:09:02.65#ibcon#flushed, iclass 25, count 0 2006.239.08:09:02.65#ibcon#about to write, iclass 25, count 0 2006.239.08:09:02.65#ibcon#wrote, iclass 25, count 0 2006.239.08:09:02.65#ibcon#about to read 3, iclass 25, count 0 2006.239.08:09:02.67#ibcon#read 3, iclass 25, count 0 2006.239.08:09:02.67#ibcon#about to read 4, iclass 25, count 0 2006.239.08:09:02.68#ibcon#read 4, iclass 25, count 0 2006.239.08:09:02.68#ibcon#about to read 5, iclass 25, count 0 2006.239.08:09:02.68#ibcon#read 5, iclass 25, count 0 2006.239.08:09:02.68#ibcon#about to read 6, iclass 25, count 0 2006.239.08:09:02.68#ibcon#read 6, iclass 25, count 0 2006.239.08:09:02.68#ibcon#end of sib2, iclass 25, count 0 2006.239.08:09:02.68#ibcon#*after write, iclass 25, count 0 2006.239.08:09:02.68#ibcon#*before return 0, iclass 25, count 0 2006.239.08:09:02.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:09:02.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:09:02.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:09:02.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:09:02.68$vc4f8/vabw=wide 2006.239.08:09:02.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.08:09:02.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.08:09:02.68#ibcon#ireg 8 cls_cnt 0 2006.239.08:09:02.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:09:02.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:09:02.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:09:02.68#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:09:02.68#ibcon#first serial, iclass 27, count 0 2006.239.08:09:02.68#ibcon#enter sib2, iclass 27, count 0 2006.239.08:09:02.68#ibcon#flushed, iclass 27, count 0 2006.239.08:09:02.68#ibcon#about to write, iclass 27, count 0 2006.239.08:09:02.68#ibcon#wrote, iclass 27, count 0 2006.239.08:09:02.68#ibcon#about to read 3, iclass 27, count 0 2006.239.08:09:02.69#ibcon#read 3, iclass 27, count 0 2006.239.08:09:02.70#ibcon#about to read 4, iclass 27, count 0 2006.239.08:09:02.70#ibcon#read 4, iclass 27, count 0 2006.239.08:09:02.70#ibcon#about to read 5, iclass 27, count 0 2006.239.08:09:02.70#ibcon#read 5, iclass 27, count 0 2006.239.08:09:02.70#ibcon#about to read 6, iclass 27, count 0 2006.239.08:09:02.70#ibcon#read 6, iclass 27, count 0 2006.239.08:09:02.70#ibcon#end of sib2, iclass 27, count 0 2006.239.08:09:02.70#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:09:02.70#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:09:02.70#ibcon#[25=BW32\r\n] 2006.239.08:09:02.70#ibcon#*before write, iclass 27, count 0 2006.239.08:09:02.70#ibcon#enter sib2, iclass 27, count 0 2006.239.08:09:02.70#ibcon#flushed, iclass 27, count 0 2006.239.08:09:02.70#ibcon#about to write, iclass 27, count 0 2006.239.08:09:02.70#ibcon#wrote, iclass 27, count 0 2006.239.08:09:02.70#ibcon#about to read 3, iclass 27, count 0 2006.239.08:09:02.72#ibcon#read 3, iclass 27, count 0 2006.239.08:09:02.73#ibcon#about to read 4, iclass 27, count 0 2006.239.08:09:02.73#ibcon#read 4, iclass 27, count 0 2006.239.08:09:02.73#ibcon#about to read 5, iclass 27, count 0 2006.239.08:09:02.73#ibcon#read 5, iclass 27, count 0 2006.239.08:09:02.73#ibcon#about to read 6, iclass 27, count 0 2006.239.08:09:02.73#ibcon#read 6, iclass 27, count 0 2006.239.08:09:02.73#ibcon#end of sib2, iclass 27, count 0 2006.239.08:09:02.73#ibcon#*after write, iclass 27, count 0 2006.239.08:09:02.73#ibcon#*before return 0, iclass 27, count 0 2006.239.08:09:02.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:09:02.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:09:02.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:09:02.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:09:02.73$vc4f8/vbbw=wide 2006.239.08:09:02.73#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.08:09:02.73#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.08:09:02.73#ibcon#ireg 8 cls_cnt 0 2006.239.08:09:02.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:09:02.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:09:02.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:09:02.80#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:09:02.80#ibcon#first serial, iclass 29, count 0 2006.239.08:09:02.80#ibcon#enter sib2, iclass 29, count 0 2006.239.08:09:02.80#ibcon#flushed, iclass 29, count 0 2006.239.08:09:02.80#ibcon#about to write, iclass 29, count 0 2006.239.08:09:02.80#ibcon#wrote, iclass 29, count 0 2006.239.08:09:02.80#ibcon#about to read 3, iclass 29, count 0 2006.239.08:09:02.81#ibcon#read 3, iclass 29, count 0 2006.239.08:09:02.82#ibcon#about to read 4, iclass 29, count 0 2006.239.08:09:02.82#ibcon#read 4, iclass 29, count 0 2006.239.08:09:02.82#ibcon#about to read 5, iclass 29, count 0 2006.239.08:09:02.82#ibcon#read 5, iclass 29, count 0 2006.239.08:09:02.82#ibcon#about to read 6, iclass 29, count 0 2006.239.08:09:02.82#ibcon#read 6, iclass 29, count 0 2006.239.08:09:02.82#ibcon#end of sib2, iclass 29, count 0 2006.239.08:09:02.82#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:09:02.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:09:02.82#ibcon#[27=BW32\r\n] 2006.239.08:09:02.82#ibcon#*before write, iclass 29, count 0 2006.239.08:09:02.82#ibcon#enter sib2, iclass 29, count 0 2006.239.08:09:02.82#ibcon#flushed, iclass 29, count 0 2006.239.08:09:02.82#ibcon#about to write, iclass 29, count 0 2006.239.08:09:02.82#ibcon#wrote, iclass 29, count 0 2006.239.08:09:02.82#ibcon#about to read 3, iclass 29, count 0 2006.239.08:09:02.84#ibcon#read 3, iclass 29, count 0 2006.239.08:09:02.84#ibcon#about to read 4, iclass 29, count 0 2006.239.08:09:02.85#ibcon#read 4, iclass 29, count 0 2006.239.08:09:02.85#ibcon#about to read 5, iclass 29, count 0 2006.239.08:09:02.85#ibcon#read 5, iclass 29, count 0 2006.239.08:09:02.85#ibcon#about to read 6, iclass 29, count 0 2006.239.08:09:02.85#ibcon#read 6, iclass 29, count 0 2006.239.08:09:02.85#ibcon#end of sib2, iclass 29, count 0 2006.239.08:09:02.85#ibcon#*after write, iclass 29, count 0 2006.239.08:09:02.85#ibcon#*before return 0, iclass 29, count 0 2006.239.08:09:02.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:09:02.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:09:02.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:09:02.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:09:02.85$4f8m12a/ifd4f 2006.239.08:09:02.85$ifd4f/lo= 2006.239.08:09:02.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:09:02.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:09:02.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:09:02.85$ifd4f/patch= 2006.239.08:09:02.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:09:02.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:09:02.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:09:02.85$4f8m12a/"form=m,16.000,1:2 2006.239.08:09:02.85$4f8m12a/"tpicd 2006.239.08:09:02.85$4f8m12a/echo=off 2006.239.08:09:02.85$4f8m12a/xlog=off 2006.239.08:09:02.85:!2006.239.08:09:40 2006.239.08:09:23.14#trakl#Source acquired 2006.239.08:09:24.15#flagr#flagr/antenna,acquired 2006.239.08:09:40.02:preob 2006.239.08:09:41.15/onsource/TRACKING 2006.239.08:09:41.15:!2006.239.08:09:50 2006.239.08:09:50.02:data_valid=on 2006.239.08:09:50.02:midob 2006.239.08:09:51.15/onsource/TRACKING 2006.239.08:09:51.15/wx/25.10,1011.5,81 2006.239.08:09:51.26/cable/+6.4162E-03 2006.239.08:09:52.35/va/01,08,usb,yes,30,32 2006.239.08:09:52.35/va/02,07,usb,yes,30,32 2006.239.08:09:52.35/va/03,07,usb,yes,29,29 2006.239.08:09:52.35/va/04,07,usb,yes,32,34 2006.239.08:09:52.35/va/05,08,usb,yes,29,30 2006.239.08:09:52.35/va/06,07,usb,yes,31,31 2006.239.08:09:52.35/va/07,07,usb,yes,31,31 2006.239.08:09:52.35/va/08,07,usb,yes,34,33 2006.239.08:09:52.58/valo/01,532.99,yes,locked 2006.239.08:09:52.58/valo/02,572.99,yes,locked 2006.239.08:09:52.58/valo/03,672.99,yes,locked 2006.239.08:09:52.59/valo/04,832.99,yes,locked 2006.239.08:09:52.59/valo/05,652.99,yes,locked 2006.239.08:09:52.59/valo/06,772.99,yes,locked 2006.239.08:09:52.59/valo/07,832.99,yes,locked 2006.239.08:09:52.59/valo/08,852.99,yes,locked 2006.239.08:09:53.67/vb/01,04,usb,yes,30,29 2006.239.08:09:53.67/vb/02,04,usb,yes,32,33 2006.239.08:09:53.67/vb/03,04,usb,yes,28,32 2006.239.08:09:53.67/vb/04,04,usb,yes,29,29 2006.239.08:09:53.67/vb/05,04,usb,yes,27,31 2006.239.08:09:53.67/vb/06,04,usb,yes,28,31 2006.239.08:09:53.67/vb/07,04,usb,yes,30,30 2006.239.08:09:53.67/vb/08,04,usb,yes,28,31 2006.239.08:09:53.91/vblo/01,632.99,yes,locked 2006.239.08:09:53.91/vblo/02,640.99,yes,locked 2006.239.08:09:53.91/vblo/03,656.99,yes,locked 2006.239.08:09:53.91/vblo/04,712.99,yes,locked 2006.239.08:09:53.91/vblo/05,744.99,yes,locked 2006.239.08:09:53.91/vblo/06,752.99,yes,locked 2006.239.08:09:53.91/vblo/07,734.99,yes,locked 2006.239.08:09:53.91/vblo/08,744.99,yes,locked 2006.239.08:09:54.06/vabw/8 2006.239.08:09:54.21/vbbw/8 2006.239.08:09:54.30/xfe/off,on,14.0 2006.239.08:09:54.67/ifatt/23,28,28,28 2006.239.08:09:55.07/fmout-gps/S +4.39E-07 2006.239.08:09:55.12:!2006.239.08:10:50 2006.239.08:10:50.00:data_valid=off 2006.239.08:10:50.01:postob 2006.239.08:10:50.18/cable/+6.4154E-03 2006.239.08:10:50.19/wx/25.09,1011.5,80 2006.239.08:10:51.07/fmout-gps/S +4.39E-07 2006.239.08:10:51.08:scan_name=239-0811,k06239,60 2006.239.08:10:51.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.239.08:10:52.15#flagr#flagr/antenna,new-source 2006.239.08:10:52.15:checkk5 2006.239.08:10:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:10:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:10:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:10:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:10:54.03/chk_obsdata//k5ts1/T2390809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:10:54.41/chk_obsdata//k5ts2/T2390809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:10:54.78/chk_obsdata//k5ts3/T2390809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:10:55.15/chk_obsdata//k5ts4/T2390809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:10:55.85/k5log//k5ts1_log_newline 2006.239.08:10:56.55/k5log//k5ts2_log_newline 2006.239.08:10:57.25/k5log//k5ts3_log_newline 2006.239.08:10:57.94/k5log//k5ts4_log_newline 2006.239.08:10:57.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:10:57.96:4f8m12a=2 2006.239.08:10:57.96$4f8m12a/echo=on 2006.239.08:10:57.96$4f8m12a/pcalon 2006.239.08:10:57.96$pcalon/"no phase cal control is implemented here 2006.239.08:10:57.96$4f8m12a/"tpicd=stop 2006.239.08:10:57.97$4f8m12a/vc4f8 2006.239.08:10:57.97$vc4f8/valo=1,532.99 2006.239.08:10:57.97#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.08:10:57.97#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.08:10:57.97#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:57.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:10:57.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:10:57.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:10:57.97#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:10:57.97#ibcon#first serial, iclass 6, count 0 2006.239.08:10:57.97#ibcon#enter sib2, iclass 6, count 0 2006.239.08:10:57.97#ibcon#flushed, iclass 6, count 0 2006.239.08:10:57.97#ibcon#about to write, iclass 6, count 0 2006.239.08:10:57.97#ibcon#wrote, iclass 6, count 0 2006.239.08:10:57.97#ibcon#about to read 3, iclass 6, count 0 2006.239.08:10:58.01#ibcon#read 3, iclass 6, count 0 2006.239.08:10:58.01#ibcon#about to read 4, iclass 6, count 0 2006.239.08:10:58.01#ibcon#read 4, iclass 6, count 0 2006.239.08:10:58.01#ibcon#about to read 5, iclass 6, count 0 2006.239.08:10:58.01#ibcon#read 5, iclass 6, count 0 2006.239.08:10:58.01#ibcon#about to read 6, iclass 6, count 0 2006.239.08:10:58.01#ibcon#read 6, iclass 6, count 0 2006.239.08:10:58.01#ibcon#end of sib2, iclass 6, count 0 2006.239.08:10:58.01#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:10:58.01#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:10:58.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:10:58.01#ibcon#*before write, iclass 6, count 0 2006.239.08:10:58.01#ibcon#enter sib2, iclass 6, count 0 2006.239.08:10:58.01#ibcon#flushed, iclass 6, count 0 2006.239.08:10:58.01#ibcon#about to write, iclass 6, count 0 2006.239.08:10:58.01#ibcon#wrote, iclass 6, count 0 2006.239.08:10:58.01#ibcon#about to read 3, iclass 6, count 0 2006.239.08:10:58.05#ibcon#read 3, iclass 6, count 0 2006.239.08:10:58.05#ibcon#about to read 4, iclass 6, count 0 2006.239.08:10:58.05#ibcon#read 4, iclass 6, count 0 2006.239.08:10:58.05#ibcon#about to read 5, iclass 6, count 0 2006.239.08:10:58.05#ibcon#read 5, iclass 6, count 0 2006.239.08:10:58.05#ibcon#about to read 6, iclass 6, count 0 2006.239.08:10:58.05#ibcon#read 6, iclass 6, count 0 2006.239.08:10:58.05#ibcon#end of sib2, iclass 6, count 0 2006.239.08:10:58.05#ibcon#*after write, iclass 6, count 0 2006.239.08:10:58.05#ibcon#*before return 0, iclass 6, count 0 2006.239.08:10:58.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:10:58.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:10:58.05#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:10:58.05#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:10:58.06$vc4f8/va=1,8 2006.239.08:10:58.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.08:10:58.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.08:10:58.06#ibcon#ireg 11 cls_cnt 2 2006.239.08:10:58.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:10:58.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:10:58.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:10:58.06#ibcon#enter wrdev, iclass 10, count 2 2006.239.08:10:58.06#ibcon#first serial, iclass 10, count 2 2006.239.08:10:58.06#ibcon#enter sib2, iclass 10, count 2 2006.239.08:10:58.06#ibcon#flushed, iclass 10, count 2 2006.239.08:10:58.06#ibcon#about to write, iclass 10, count 2 2006.239.08:10:58.06#ibcon#wrote, iclass 10, count 2 2006.239.08:10:58.06#ibcon#about to read 3, iclass 10, count 2 2006.239.08:10:58.07#ibcon#read 3, iclass 10, count 2 2006.239.08:10:58.07#ibcon#about to read 4, iclass 10, count 2 2006.239.08:10:58.07#ibcon#read 4, iclass 10, count 2 2006.239.08:10:58.07#ibcon#about to read 5, iclass 10, count 2 2006.239.08:10:58.07#ibcon#read 5, iclass 10, count 2 2006.239.08:10:58.07#ibcon#about to read 6, iclass 10, count 2 2006.239.08:10:58.07#ibcon#read 6, iclass 10, count 2 2006.239.08:10:58.07#ibcon#end of sib2, iclass 10, count 2 2006.239.08:10:58.07#ibcon#*mode == 0, iclass 10, count 2 2006.239.08:10:58.07#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.08:10:58.07#ibcon#[25=AT01-08\r\n] 2006.239.08:10:58.07#ibcon#*before write, iclass 10, count 2 2006.239.08:10:58.07#ibcon#enter sib2, iclass 10, count 2 2006.239.08:10:58.07#ibcon#flushed, iclass 10, count 2 2006.239.08:10:58.07#ibcon#about to write, iclass 10, count 2 2006.239.08:10:58.07#ibcon#wrote, iclass 10, count 2 2006.239.08:10:58.07#ibcon#about to read 3, iclass 10, count 2 2006.239.08:10:58.10#ibcon#read 3, iclass 10, count 2 2006.239.08:10:58.10#ibcon#about to read 4, iclass 10, count 2 2006.239.08:10:58.10#ibcon#read 4, iclass 10, count 2 2006.239.08:10:58.10#ibcon#about to read 5, iclass 10, count 2 2006.239.08:10:58.10#ibcon#read 5, iclass 10, count 2 2006.239.08:10:58.10#ibcon#about to read 6, iclass 10, count 2 2006.239.08:10:58.10#ibcon#read 6, iclass 10, count 2 2006.239.08:10:58.10#ibcon#end of sib2, iclass 10, count 2 2006.239.08:10:58.10#ibcon#*after write, iclass 10, count 2 2006.239.08:10:58.10#ibcon#*before return 0, iclass 10, count 2 2006.239.08:10:58.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:10:58.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:10:58.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.08:10:58.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:10:58.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:10:58.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:10:58.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:10:58.22#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:10:58.22#ibcon#first serial, iclass 10, count 0 2006.239.08:10:58.22#ibcon#enter sib2, iclass 10, count 0 2006.239.08:10:58.22#ibcon#flushed, iclass 10, count 0 2006.239.08:10:58.22#ibcon#about to write, iclass 10, count 0 2006.239.08:10:58.22#ibcon#wrote, iclass 10, count 0 2006.239.08:10:58.22#ibcon#about to read 3, iclass 10, count 0 2006.239.08:10:58.25#ibcon#read 3, iclass 10, count 0 2006.239.08:10:58.25#ibcon#about to read 4, iclass 10, count 0 2006.239.08:10:58.25#ibcon#read 4, iclass 10, count 0 2006.239.08:10:58.25#ibcon#about to read 5, iclass 10, count 0 2006.239.08:10:58.25#ibcon#read 5, iclass 10, count 0 2006.239.08:10:58.25#ibcon#about to read 6, iclass 10, count 0 2006.239.08:10:58.25#ibcon#read 6, iclass 10, count 0 2006.239.08:10:58.25#ibcon#end of sib2, iclass 10, count 0 2006.239.08:10:58.25#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:10:58.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:10:58.25#ibcon#[25=USB\r\n] 2006.239.08:10:58.25#ibcon#*before write, iclass 10, count 0 2006.239.08:10:58.25#ibcon#enter sib2, iclass 10, count 0 2006.239.08:10:58.25#ibcon#flushed, iclass 10, count 0 2006.239.08:10:58.25#ibcon#about to write, iclass 10, count 0 2006.239.08:10:58.25#ibcon#wrote, iclass 10, count 0 2006.239.08:10:58.25#ibcon#about to read 3, iclass 10, count 0 2006.239.08:10:58.27#ibcon#read 3, iclass 10, count 0 2006.239.08:10:58.27#ibcon#about to read 4, iclass 10, count 0 2006.239.08:10:58.27#ibcon#read 4, iclass 10, count 0 2006.239.08:10:58.27#ibcon#about to read 5, iclass 10, count 0 2006.239.08:10:58.27#ibcon#read 5, iclass 10, count 0 2006.239.08:10:58.27#ibcon#about to read 6, iclass 10, count 0 2006.239.08:10:58.27#ibcon#read 6, iclass 10, count 0 2006.239.08:10:58.27#ibcon#end of sib2, iclass 10, count 0 2006.239.08:10:58.27#ibcon#*after write, iclass 10, count 0 2006.239.08:10:58.27#ibcon#*before return 0, iclass 10, count 0 2006.239.08:10:58.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:10:58.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:10:58.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:10:58.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:10:58.28$vc4f8/valo=2,572.99 2006.239.08:10:58.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.08:10:58.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.08:10:58.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:58.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:10:58.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:10:58.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:10:58.28#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:10:58.28#ibcon#first serial, iclass 12, count 0 2006.239.08:10:58.28#ibcon#enter sib2, iclass 12, count 0 2006.239.08:10:58.28#ibcon#flushed, iclass 12, count 0 2006.239.08:10:58.28#ibcon#about to write, iclass 12, count 0 2006.239.08:10:58.28#ibcon#wrote, iclass 12, count 0 2006.239.08:10:58.28#ibcon#about to read 3, iclass 12, count 0 2006.239.08:10:58.29#ibcon#read 3, iclass 12, count 0 2006.239.08:10:58.29#ibcon#about to read 4, iclass 12, count 0 2006.239.08:10:58.29#ibcon#read 4, iclass 12, count 0 2006.239.08:10:58.29#ibcon#about to read 5, iclass 12, count 0 2006.239.08:10:58.29#ibcon#read 5, iclass 12, count 0 2006.239.08:10:58.29#ibcon#about to read 6, iclass 12, count 0 2006.239.08:10:58.29#ibcon#read 6, iclass 12, count 0 2006.239.08:10:58.29#ibcon#end of sib2, iclass 12, count 0 2006.239.08:10:58.29#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:10:58.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:10:58.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:10:58.29#ibcon#*before write, iclass 12, count 0 2006.239.08:10:58.29#ibcon#enter sib2, iclass 12, count 0 2006.239.08:10:58.29#ibcon#flushed, iclass 12, count 0 2006.239.08:10:58.29#ibcon#about to write, iclass 12, count 0 2006.239.08:10:58.29#ibcon#wrote, iclass 12, count 0 2006.239.08:10:58.29#ibcon#about to read 3, iclass 12, count 0 2006.239.08:10:58.33#ibcon#read 3, iclass 12, count 0 2006.239.08:10:58.33#ibcon#about to read 4, iclass 12, count 0 2006.239.08:10:58.33#ibcon#read 4, iclass 12, count 0 2006.239.08:10:58.33#ibcon#about to read 5, iclass 12, count 0 2006.239.08:10:58.33#ibcon#read 5, iclass 12, count 0 2006.239.08:10:58.33#ibcon#about to read 6, iclass 12, count 0 2006.239.08:10:58.33#ibcon#read 6, iclass 12, count 0 2006.239.08:10:58.33#ibcon#end of sib2, iclass 12, count 0 2006.239.08:10:58.33#ibcon#*after write, iclass 12, count 0 2006.239.08:10:58.33#ibcon#*before return 0, iclass 12, count 0 2006.239.08:10:58.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:10:58.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:10:58.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:10:58.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:10:58.34$vc4f8/va=2,7 2006.239.08:10:58.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.08:10:58.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.08:10:58.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:10:58.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:10:58.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:10:58.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:10:58.39#ibcon#enter wrdev, iclass 14, count 2 2006.239.08:10:58.39#ibcon#first serial, iclass 14, count 2 2006.239.08:10:58.39#ibcon#enter sib2, iclass 14, count 2 2006.239.08:10:58.39#ibcon#flushed, iclass 14, count 2 2006.239.08:10:58.39#ibcon#about to write, iclass 14, count 2 2006.239.08:10:58.39#ibcon#wrote, iclass 14, count 2 2006.239.08:10:58.39#ibcon#about to read 3, iclass 14, count 2 2006.239.08:10:58.40#ibcon#read 3, iclass 14, count 2 2006.239.08:10:58.40#ibcon#about to read 4, iclass 14, count 2 2006.239.08:10:58.40#ibcon#read 4, iclass 14, count 2 2006.239.08:10:58.40#ibcon#about to read 5, iclass 14, count 2 2006.239.08:10:58.40#ibcon#read 5, iclass 14, count 2 2006.239.08:10:58.40#ibcon#about to read 6, iclass 14, count 2 2006.239.08:10:58.40#ibcon#read 6, iclass 14, count 2 2006.239.08:10:58.40#ibcon#end of sib2, iclass 14, count 2 2006.239.08:10:58.40#ibcon#*mode == 0, iclass 14, count 2 2006.239.08:10:58.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.08:10:58.40#ibcon#[25=AT02-07\r\n] 2006.239.08:10:58.40#ibcon#*before write, iclass 14, count 2 2006.239.08:10:58.40#ibcon#enter sib2, iclass 14, count 2 2006.239.08:10:58.40#ibcon#flushed, iclass 14, count 2 2006.239.08:10:58.40#ibcon#about to write, iclass 14, count 2 2006.239.08:10:58.40#ibcon#wrote, iclass 14, count 2 2006.239.08:10:58.40#ibcon#about to read 3, iclass 14, count 2 2006.239.08:10:58.43#ibcon#read 3, iclass 14, count 2 2006.239.08:10:58.43#ibcon#about to read 4, iclass 14, count 2 2006.239.08:10:58.43#ibcon#read 4, iclass 14, count 2 2006.239.08:10:58.43#ibcon#about to read 5, iclass 14, count 2 2006.239.08:10:58.43#ibcon#read 5, iclass 14, count 2 2006.239.08:10:58.43#ibcon#about to read 6, iclass 14, count 2 2006.239.08:10:58.43#ibcon#read 6, iclass 14, count 2 2006.239.08:10:58.43#ibcon#end of sib2, iclass 14, count 2 2006.239.08:10:58.43#ibcon#*after write, iclass 14, count 2 2006.239.08:10:58.43#ibcon#*before return 0, iclass 14, count 2 2006.239.08:10:58.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:10:58.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:10:58.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.08:10:58.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:10:58.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:10:58.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:10:58.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:10:58.55#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:10:58.55#ibcon#first serial, iclass 14, count 0 2006.239.08:10:58.55#ibcon#enter sib2, iclass 14, count 0 2006.239.08:10:58.55#ibcon#flushed, iclass 14, count 0 2006.239.08:10:58.55#ibcon#about to write, iclass 14, count 0 2006.239.08:10:58.55#ibcon#wrote, iclass 14, count 0 2006.239.08:10:58.55#ibcon#about to read 3, iclass 14, count 0 2006.239.08:10:58.57#ibcon#read 3, iclass 14, count 0 2006.239.08:10:58.57#ibcon#about to read 4, iclass 14, count 0 2006.239.08:10:58.57#ibcon#read 4, iclass 14, count 0 2006.239.08:10:58.57#ibcon#about to read 5, iclass 14, count 0 2006.239.08:10:58.57#ibcon#read 5, iclass 14, count 0 2006.239.08:10:58.57#ibcon#about to read 6, iclass 14, count 0 2006.239.08:10:58.57#ibcon#read 6, iclass 14, count 0 2006.239.08:10:58.57#ibcon#end of sib2, iclass 14, count 0 2006.239.08:10:58.57#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:10:58.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:10:58.57#ibcon#[25=USB\r\n] 2006.239.08:10:58.57#ibcon#*before write, iclass 14, count 0 2006.239.08:10:58.57#ibcon#enter sib2, iclass 14, count 0 2006.239.08:10:58.57#ibcon#flushed, iclass 14, count 0 2006.239.08:10:58.57#ibcon#about to write, iclass 14, count 0 2006.239.08:10:58.57#ibcon#wrote, iclass 14, count 0 2006.239.08:10:58.57#ibcon#about to read 3, iclass 14, count 0 2006.239.08:10:58.61#ibcon#read 3, iclass 14, count 0 2006.239.08:10:58.61#ibcon#about to read 4, iclass 14, count 0 2006.239.08:10:58.61#ibcon#read 4, iclass 14, count 0 2006.239.08:10:58.61#ibcon#about to read 5, iclass 14, count 0 2006.239.08:10:58.61#ibcon#read 5, iclass 14, count 0 2006.239.08:10:58.61#ibcon#about to read 6, iclass 14, count 0 2006.239.08:10:58.61#ibcon#read 6, iclass 14, count 0 2006.239.08:10:58.61#ibcon#end of sib2, iclass 14, count 0 2006.239.08:10:58.61#ibcon#*after write, iclass 14, count 0 2006.239.08:10:58.61#ibcon#*before return 0, iclass 14, count 0 2006.239.08:10:58.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:10:58.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:10:58.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:10:58.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:10:58.61$vc4f8/valo=3,672.99 2006.239.08:10:58.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.08:10:58.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.08:10:58.61#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:58.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:10:58.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:10:58.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:10:58.61#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:10:58.61#ibcon#first serial, iclass 16, count 0 2006.239.08:10:58.61#ibcon#enter sib2, iclass 16, count 0 2006.239.08:10:58.61#ibcon#flushed, iclass 16, count 0 2006.239.08:10:58.61#ibcon#about to write, iclass 16, count 0 2006.239.08:10:58.61#ibcon#wrote, iclass 16, count 0 2006.239.08:10:58.61#ibcon#about to read 3, iclass 16, count 0 2006.239.08:10:58.63#ibcon#read 3, iclass 16, count 0 2006.239.08:10:58.63#ibcon#about to read 4, iclass 16, count 0 2006.239.08:10:58.63#ibcon#read 4, iclass 16, count 0 2006.239.08:10:58.63#ibcon#about to read 5, iclass 16, count 0 2006.239.08:10:58.63#ibcon#read 5, iclass 16, count 0 2006.239.08:10:58.63#ibcon#about to read 6, iclass 16, count 0 2006.239.08:10:58.63#ibcon#read 6, iclass 16, count 0 2006.239.08:10:58.63#ibcon#end of sib2, iclass 16, count 0 2006.239.08:10:58.63#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:10:58.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:10:58.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:10:58.63#ibcon#*before write, iclass 16, count 0 2006.239.08:10:58.63#ibcon#enter sib2, iclass 16, count 0 2006.239.08:10:58.63#ibcon#flushed, iclass 16, count 0 2006.239.08:10:58.63#ibcon#about to write, iclass 16, count 0 2006.239.08:10:58.63#ibcon#wrote, iclass 16, count 0 2006.239.08:10:58.63#ibcon#about to read 3, iclass 16, count 0 2006.239.08:10:58.66#ibcon#read 3, iclass 16, count 0 2006.239.08:10:58.66#ibcon#about to read 4, iclass 16, count 0 2006.239.08:10:58.66#ibcon#read 4, iclass 16, count 0 2006.239.08:10:58.66#ibcon#about to read 5, iclass 16, count 0 2006.239.08:10:58.66#ibcon#read 5, iclass 16, count 0 2006.239.08:10:58.66#ibcon#about to read 6, iclass 16, count 0 2006.239.08:10:58.66#ibcon#read 6, iclass 16, count 0 2006.239.08:10:58.66#ibcon#end of sib2, iclass 16, count 0 2006.239.08:10:58.66#ibcon#*after write, iclass 16, count 0 2006.239.08:10:58.66#ibcon#*before return 0, iclass 16, count 0 2006.239.08:10:58.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:10:58.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:10:58.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:10:58.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:10:58.67$vc4f8/va=3,7 2006.239.08:10:58.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.08:10:58.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.08:10:58.67#ibcon#ireg 11 cls_cnt 2 2006.239.08:10:58.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:10:58.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:10:58.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:10:58.73#ibcon#enter wrdev, iclass 18, count 2 2006.239.08:10:58.73#ibcon#first serial, iclass 18, count 2 2006.239.08:10:58.73#ibcon#enter sib2, iclass 18, count 2 2006.239.08:10:58.73#ibcon#flushed, iclass 18, count 2 2006.239.08:10:58.73#ibcon#about to write, iclass 18, count 2 2006.239.08:10:58.73#ibcon#wrote, iclass 18, count 2 2006.239.08:10:58.73#ibcon#about to read 3, iclass 18, count 2 2006.239.08:10:58.74#ibcon#read 3, iclass 18, count 2 2006.239.08:10:58.74#ibcon#about to read 4, iclass 18, count 2 2006.239.08:10:58.74#ibcon#read 4, iclass 18, count 2 2006.239.08:10:58.74#ibcon#about to read 5, iclass 18, count 2 2006.239.08:10:58.74#ibcon#read 5, iclass 18, count 2 2006.239.08:10:58.74#ibcon#about to read 6, iclass 18, count 2 2006.239.08:10:58.74#ibcon#read 6, iclass 18, count 2 2006.239.08:10:58.74#ibcon#end of sib2, iclass 18, count 2 2006.239.08:10:58.74#ibcon#*mode == 0, iclass 18, count 2 2006.239.08:10:58.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.08:10:58.74#ibcon#[25=AT03-07\r\n] 2006.239.08:10:58.74#ibcon#*before write, iclass 18, count 2 2006.239.08:10:58.74#ibcon#enter sib2, iclass 18, count 2 2006.239.08:10:58.74#ibcon#flushed, iclass 18, count 2 2006.239.08:10:58.74#ibcon#about to write, iclass 18, count 2 2006.239.08:10:58.74#ibcon#wrote, iclass 18, count 2 2006.239.08:10:58.74#ibcon#about to read 3, iclass 18, count 2 2006.239.08:10:58.77#ibcon#read 3, iclass 18, count 2 2006.239.08:10:58.77#ibcon#about to read 4, iclass 18, count 2 2006.239.08:10:58.77#ibcon#read 4, iclass 18, count 2 2006.239.08:10:58.77#ibcon#about to read 5, iclass 18, count 2 2006.239.08:10:58.77#ibcon#read 5, iclass 18, count 2 2006.239.08:10:58.77#ibcon#about to read 6, iclass 18, count 2 2006.239.08:10:58.77#ibcon#read 6, iclass 18, count 2 2006.239.08:10:58.77#ibcon#end of sib2, iclass 18, count 2 2006.239.08:10:58.77#ibcon#*after write, iclass 18, count 2 2006.239.08:10:58.77#ibcon#*before return 0, iclass 18, count 2 2006.239.08:10:58.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:10:58.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:10:58.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.08:10:58.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:10:58.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:10:58.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:10:58.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:10:58.89#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:10:58.89#ibcon#first serial, iclass 18, count 0 2006.239.08:10:58.89#ibcon#enter sib2, iclass 18, count 0 2006.239.08:10:58.89#ibcon#flushed, iclass 18, count 0 2006.239.08:10:58.89#ibcon#about to write, iclass 18, count 0 2006.239.08:10:58.89#ibcon#wrote, iclass 18, count 0 2006.239.08:10:58.89#ibcon#about to read 3, iclass 18, count 0 2006.239.08:10:58.91#ibcon#read 3, iclass 18, count 0 2006.239.08:10:58.91#ibcon#about to read 4, iclass 18, count 0 2006.239.08:10:58.91#ibcon#read 4, iclass 18, count 0 2006.239.08:10:58.91#ibcon#about to read 5, iclass 18, count 0 2006.239.08:10:58.91#ibcon#read 5, iclass 18, count 0 2006.239.08:10:58.91#ibcon#about to read 6, iclass 18, count 0 2006.239.08:10:58.91#ibcon#read 6, iclass 18, count 0 2006.239.08:10:58.91#ibcon#end of sib2, iclass 18, count 0 2006.239.08:10:58.91#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:10:58.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:10:58.91#ibcon#[25=USB\r\n] 2006.239.08:10:58.91#ibcon#*before write, iclass 18, count 0 2006.239.08:10:58.91#ibcon#enter sib2, iclass 18, count 0 2006.239.08:10:58.91#ibcon#flushed, iclass 18, count 0 2006.239.08:10:58.91#ibcon#about to write, iclass 18, count 0 2006.239.08:10:58.91#ibcon#wrote, iclass 18, count 0 2006.239.08:10:58.91#ibcon#about to read 3, iclass 18, count 0 2006.239.08:10:58.94#ibcon#read 3, iclass 18, count 0 2006.239.08:10:58.94#ibcon#about to read 4, iclass 18, count 0 2006.239.08:10:58.94#ibcon#read 4, iclass 18, count 0 2006.239.08:10:58.94#ibcon#about to read 5, iclass 18, count 0 2006.239.08:10:58.94#ibcon#read 5, iclass 18, count 0 2006.239.08:10:58.94#ibcon#about to read 6, iclass 18, count 0 2006.239.08:10:58.94#ibcon#read 6, iclass 18, count 0 2006.239.08:10:58.94#ibcon#end of sib2, iclass 18, count 0 2006.239.08:10:58.94#ibcon#*after write, iclass 18, count 0 2006.239.08:10:58.94#ibcon#*before return 0, iclass 18, count 0 2006.239.08:10:58.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:10:58.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:10:58.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:10:58.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:10:58.95$vc4f8/valo=4,832.99 2006.239.08:10:58.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.08:10:58.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.08:10:58.95#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:58.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:10:58.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:10:58.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:10:58.95#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:10:58.95#ibcon#first serial, iclass 20, count 0 2006.239.08:10:58.95#ibcon#enter sib2, iclass 20, count 0 2006.239.08:10:58.95#ibcon#flushed, iclass 20, count 0 2006.239.08:10:58.95#ibcon#about to write, iclass 20, count 0 2006.239.08:10:58.95#ibcon#wrote, iclass 20, count 0 2006.239.08:10:58.95#ibcon#about to read 3, iclass 20, count 0 2006.239.08:10:58.98#ibcon#read 3, iclass 20, count 0 2006.239.08:10:58.98#ibcon#about to read 4, iclass 20, count 0 2006.239.08:10:58.98#ibcon#read 4, iclass 20, count 0 2006.239.08:10:58.98#ibcon#about to read 5, iclass 20, count 0 2006.239.08:10:58.98#ibcon#read 5, iclass 20, count 0 2006.239.08:10:58.98#ibcon#about to read 6, iclass 20, count 0 2006.239.08:10:58.98#ibcon#read 6, iclass 20, count 0 2006.239.08:10:58.98#ibcon#end of sib2, iclass 20, count 0 2006.239.08:10:58.98#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:10:58.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:10:58.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:10:58.98#ibcon#*before write, iclass 20, count 0 2006.239.08:10:58.98#ibcon#enter sib2, iclass 20, count 0 2006.239.08:10:58.98#ibcon#flushed, iclass 20, count 0 2006.239.08:10:58.98#ibcon#about to write, iclass 20, count 0 2006.239.08:10:58.98#ibcon#wrote, iclass 20, count 0 2006.239.08:10:58.98#ibcon#about to read 3, iclass 20, count 0 2006.239.08:10:59.02#ibcon#read 3, iclass 20, count 0 2006.239.08:10:59.02#ibcon#about to read 4, iclass 20, count 0 2006.239.08:10:59.02#ibcon#read 4, iclass 20, count 0 2006.239.08:10:59.02#ibcon#about to read 5, iclass 20, count 0 2006.239.08:10:59.02#ibcon#read 5, iclass 20, count 0 2006.239.08:10:59.02#ibcon#about to read 6, iclass 20, count 0 2006.239.08:10:59.02#ibcon#read 6, iclass 20, count 0 2006.239.08:10:59.02#ibcon#end of sib2, iclass 20, count 0 2006.239.08:10:59.02#ibcon#*after write, iclass 20, count 0 2006.239.08:10:59.02#ibcon#*before return 0, iclass 20, count 0 2006.239.08:10:59.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:10:59.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:10:59.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:10:59.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:10:59.03$vc4f8/va=4,7 2006.239.08:10:59.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.08:10:59.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.08:10:59.03#ibcon#ireg 11 cls_cnt 2 2006.239.08:10:59.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:10:59.05#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:10:59.05#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:10:59.05#ibcon#enter wrdev, iclass 22, count 2 2006.239.08:10:59.05#ibcon#first serial, iclass 22, count 2 2006.239.08:10:59.05#ibcon#enter sib2, iclass 22, count 2 2006.239.08:10:59.05#ibcon#flushed, iclass 22, count 2 2006.239.08:10:59.05#ibcon#about to write, iclass 22, count 2 2006.239.08:10:59.05#ibcon#wrote, iclass 22, count 2 2006.239.08:10:59.05#ibcon#about to read 3, iclass 22, count 2 2006.239.08:10:59.07#ibcon#read 3, iclass 22, count 2 2006.239.08:10:59.07#ibcon#about to read 4, iclass 22, count 2 2006.239.08:10:59.07#ibcon#read 4, iclass 22, count 2 2006.239.08:10:59.07#ibcon#about to read 5, iclass 22, count 2 2006.239.08:10:59.07#ibcon#read 5, iclass 22, count 2 2006.239.08:10:59.07#ibcon#about to read 6, iclass 22, count 2 2006.239.08:10:59.07#ibcon#read 6, iclass 22, count 2 2006.239.08:10:59.07#ibcon#end of sib2, iclass 22, count 2 2006.239.08:10:59.07#ibcon#*mode == 0, iclass 22, count 2 2006.239.08:10:59.07#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.08:10:59.07#ibcon#[25=AT04-07\r\n] 2006.239.08:10:59.07#ibcon#*before write, iclass 22, count 2 2006.239.08:10:59.07#ibcon#enter sib2, iclass 22, count 2 2006.239.08:10:59.07#ibcon#flushed, iclass 22, count 2 2006.239.08:10:59.07#ibcon#about to write, iclass 22, count 2 2006.239.08:10:59.07#ibcon#wrote, iclass 22, count 2 2006.239.08:10:59.07#ibcon#about to read 3, iclass 22, count 2 2006.239.08:10:59.10#ibcon#read 3, iclass 22, count 2 2006.239.08:10:59.10#ibcon#about to read 4, iclass 22, count 2 2006.239.08:10:59.10#ibcon#read 4, iclass 22, count 2 2006.239.08:10:59.10#ibcon#about to read 5, iclass 22, count 2 2006.239.08:10:59.10#ibcon#read 5, iclass 22, count 2 2006.239.08:10:59.10#ibcon#about to read 6, iclass 22, count 2 2006.239.08:10:59.10#ibcon#read 6, iclass 22, count 2 2006.239.08:10:59.10#ibcon#end of sib2, iclass 22, count 2 2006.239.08:10:59.10#ibcon#*after write, iclass 22, count 2 2006.239.08:10:59.10#ibcon#*before return 0, iclass 22, count 2 2006.239.08:10:59.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:10:59.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:10:59.10#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.08:10:59.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:10:59.10#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:10:59.22#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:10:59.22#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:10:59.22#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:10:59.22#ibcon#first serial, iclass 22, count 0 2006.239.08:10:59.22#ibcon#enter sib2, iclass 22, count 0 2006.239.08:10:59.22#ibcon#flushed, iclass 22, count 0 2006.239.08:10:59.22#ibcon#about to write, iclass 22, count 0 2006.239.08:10:59.22#ibcon#wrote, iclass 22, count 0 2006.239.08:10:59.22#ibcon#about to read 3, iclass 22, count 0 2006.239.08:10:59.24#ibcon#read 3, iclass 22, count 0 2006.239.08:10:59.24#ibcon#about to read 4, iclass 22, count 0 2006.239.08:10:59.24#ibcon#read 4, iclass 22, count 0 2006.239.08:10:59.24#ibcon#about to read 5, iclass 22, count 0 2006.239.08:10:59.24#ibcon#read 5, iclass 22, count 0 2006.239.08:10:59.24#ibcon#about to read 6, iclass 22, count 0 2006.239.08:10:59.24#ibcon#read 6, iclass 22, count 0 2006.239.08:10:59.24#ibcon#end of sib2, iclass 22, count 0 2006.239.08:10:59.24#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:10:59.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:10:59.24#ibcon#[25=USB\r\n] 2006.239.08:10:59.24#ibcon#*before write, iclass 22, count 0 2006.239.08:10:59.24#ibcon#enter sib2, iclass 22, count 0 2006.239.08:10:59.24#ibcon#flushed, iclass 22, count 0 2006.239.08:10:59.24#ibcon#about to write, iclass 22, count 0 2006.239.08:10:59.24#ibcon#wrote, iclass 22, count 0 2006.239.08:10:59.24#ibcon#about to read 3, iclass 22, count 0 2006.239.08:10:59.27#ibcon#read 3, iclass 22, count 0 2006.239.08:10:59.27#ibcon#about to read 4, iclass 22, count 0 2006.239.08:10:59.27#ibcon#read 4, iclass 22, count 0 2006.239.08:10:59.27#ibcon#about to read 5, iclass 22, count 0 2006.239.08:10:59.27#ibcon#read 5, iclass 22, count 0 2006.239.08:10:59.27#ibcon#about to read 6, iclass 22, count 0 2006.239.08:10:59.27#ibcon#read 6, iclass 22, count 0 2006.239.08:10:59.27#ibcon#end of sib2, iclass 22, count 0 2006.239.08:10:59.27#ibcon#*after write, iclass 22, count 0 2006.239.08:10:59.27#ibcon#*before return 0, iclass 22, count 0 2006.239.08:10:59.27#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:10:59.27#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:10:59.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:10:59.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:10:59.28$vc4f8/valo=5,652.99 2006.239.08:10:59.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.08:10:59.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.08:10:59.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:59.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:10:59.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:10:59.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:10:59.28#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:10:59.28#ibcon#first serial, iclass 24, count 0 2006.239.08:10:59.28#ibcon#enter sib2, iclass 24, count 0 2006.239.08:10:59.28#ibcon#flushed, iclass 24, count 0 2006.239.08:10:59.28#ibcon#about to write, iclass 24, count 0 2006.239.08:10:59.28#ibcon#wrote, iclass 24, count 0 2006.239.08:10:59.28#ibcon#about to read 3, iclass 24, count 0 2006.239.08:10:59.29#ibcon#read 3, iclass 24, count 0 2006.239.08:10:59.29#ibcon#about to read 4, iclass 24, count 0 2006.239.08:10:59.29#ibcon#read 4, iclass 24, count 0 2006.239.08:10:59.29#ibcon#about to read 5, iclass 24, count 0 2006.239.08:10:59.29#ibcon#read 5, iclass 24, count 0 2006.239.08:10:59.29#ibcon#about to read 6, iclass 24, count 0 2006.239.08:10:59.29#ibcon#read 6, iclass 24, count 0 2006.239.08:10:59.29#ibcon#end of sib2, iclass 24, count 0 2006.239.08:10:59.29#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:10:59.29#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:10:59.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:10:59.29#ibcon#*before write, iclass 24, count 0 2006.239.08:10:59.29#ibcon#enter sib2, iclass 24, count 0 2006.239.08:10:59.29#ibcon#flushed, iclass 24, count 0 2006.239.08:10:59.29#ibcon#about to write, iclass 24, count 0 2006.239.08:10:59.29#ibcon#wrote, iclass 24, count 0 2006.239.08:10:59.29#ibcon#about to read 3, iclass 24, count 0 2006.239.08:10:59.33#ibcon#read 3, iclass 24, count 0 2006.239.08:10:59.33#ibcon#about to read 4, iclass 24, count 0 2006.239.08:10:59.33#ibcon#read 4, iclass 24, count 0 2006.239.08:10:59.33#ibcon#about to read 5, iclass 24, count 0 2006.239.08:10:59.33#ibcon#read 5, iclass 24, count 0 2006.239.08:10:59.33#ibcon#about to read 6, iclass 24, count 0 2006.239.08:10:59.33#ibcon#read 6, iclass 24, count 0 2006.239.08:10:59.33#ibcon#end of sib2, iclass 24, count 0 2006.239.08:10:59.33#ibcon#*after write, iclass 24, count 0 2006.239.08:10:59.33#ibcon#*before return 0, iclass 24, count 0 2006.239.08:10:59.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:10:59.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:10:59.33#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:10:59.33#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:10:59.34$vc4f8/va=5,8 2006.239.08:10:59.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.08:10:59.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.08:10:59.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:10:59.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:10:59.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:10:59.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:10:59.38#ibcon#enter wrdev, iclass 26, count 2 2006.239.08:10:59.38#ibcon#first serial, iclass 26, count 2 2006.239.08:10:59.38#ibcon#enter sib2, iclass 26, count 2 2006.239.08:10:59.38#ibcon#flushed, iclass 26, count 2 2006.239.08:10:59.38#ibcon#about to write, iclass 26, count 2 2006.239.08:10:59.38#ibcon#wrote, iclass 26, count 2 2006.239.08:10:59.38#ibcon#about to read 3, iclass 26, count 2 2006.239.08:10:59.40#ibcon#read 3, iclass 26, count 2 2006.239.08:10:59.40#ibcon#about to read 4, iclass 26, count 2 2006.239.08:10:59.40#ibcon#read 4, iclass 26, count 2 2006.239.08:10:59.40#ibcon#about to read 5, iclass 26, count 2 2006.239.08:10:59.40#ibcon#read 5, iclass 26, count 2 2006.239.08:10:59.40#ibcon#about to read 6, iclass 26, count 2 2006.239.08:10:59.40#ibcon#read 6, iclass 26, count 2 2006.239.08:10:59.40#ibcon#end of sib2, iclass 26, count 2 2006.239.08:10:59.40#ibcon#*mode == 0, iclass 26, count 2 2006.239.08:10:59.40#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.08:10:59.40#ibcon#[25=AT05-08\r\n] 2006.239.08:10:59.40#ibcon#*before write, iclass 26, count 2 2006.239.08:10:59.40#ibcon#enter sib2, iclass 26, count 2 2006.239.08:10:59.40#ibcon#flushed, iclass 26, count 2 2006.239.08:10:59.40#ibcon#about to write, iclass 26, count 2 2006.239.08:10:59.40#ibcon#wrote, iclass 26, count 2 2006.239.08:10:59.40#ibcon#about to read 3, iclass 26, count 2 2006.239.08:10:59.43#ibcon#read 3, iclass 26, count 2 2006.239.08:10:59.43#ibcon#about to read 4, iclass 26, count 2 2006.239.08:10:59.43#ibcon#read 4, iclass 26, count 2 2006.239.08:10:59.43#ibcon#about to read 5, iclass 26, count 2 2006.239.08:10:59.43#ibcon#read 5, iclass 26, count 2 2006.239.08:10:59.43#ibcon#about to read 6, iclass 26, count 2 2006.239.08:10:59.43#ibcon#read 6, iclass 26, count 2 2006.239.08:10:59.43#ibcon#end of sib2, iclass 26, count 2 2006.239.08:10:59.43#ibcon#*after write, iclass 26, count 2 2006.239.08:10:59.43#ibcon#*before return 0, iclass 26, count 2 2006.239.08:10:59.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:10:59.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:10:59.43#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.08:10:59.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:10:59.43#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:10:59.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:10:59.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:10:59.55#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:10:59.55#ibcon#first serial, iclass 26, count 0 2006.239.08:10:59.55#ibcon#enter sib2, iclass 26, count 0 2006.239.08:10:59.55#ibcon#flushed, iclass 26, count 0 2006.239.08:10:59.55#ibcon#about to write, iclass 26, count 0 2006.239.08:10:59.55#ibcon#wrote, iclass 26, count 0 2006.239.08:10:59.55#ibcon#about to read 3, iclass 26, count 0 2006.239.08:10:59.57#ibcon#read 3, iclass 26, count 0 2006.239.08:10:59.57#ibcon#about to read 4, iclass 26, count 0 2006.239.08:10:59.57#ibcon#read 4, iclass 26, count 0 2006.239.08:10:59.57#ibcon#about to read 5, iclass 26, count 0 2006.239.08:10:59.57#ibcon#read 5, iclass 26, count 0 2006.239.08:10:59.57#ibcon#about to read 6, iclass 26, count 0 2006.239.08:10:59.57#ibcon#read 6, iclass 26, count 0 2006.239.08:10:59.57#ibcon#end of sib2, iclass 26, count 0 2006.239.08:10:59.57#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:10:59.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:10:59.57#ibcon#[25=USB\r\n] 2006.239.08:10:59.57#ibcon#*before write, iclass 26, count 0 2006.239.08:10:59.57#ibcon#enter sib2, iclass 26, count 0 2006.239.08:10:59.57#ibcon#flushed, iclass 26, count 0 2006.239.08:10:59.57#ibcon#about to write, iclass 26, count 0 2006.239.08:10:59.57#ibcon#wrote, iclass 26, count 0 2006.239.08:10:59.57#ibcon#about to read 3, iclass 26, count 0 2006.239.08:10:59.60#ibcon#read 3, iclass 26, count 0 2006.239.08:10:59.60#ibcon#about to read 4, iclass 26, count 0 2006.239.08:10:59.60#ibcon#read 4, iclass 26, count 0 2006.239.08:10:59.60#ibcon#about to read 5, iclass 26, count 0 2006.239.08:10:59.60#ibcon#read 5, iclass 26, count 0 2006.239.08:10:59.60#ibcon#about to read 6, iclass 26, count 0 2006.239.08:10:59.60#ibcon#read 6, iclass 26, count 0 2006.239.08:10:59.60#ibcon#end of sib2, iclass 26, count 0 2006.239.08:10:59.60#ibcon#*after write, iclass 26, count 0 2006.239.08:10:59.60#ibcon#*before return 0, iclass 26, count 0 2006.239.08:10:59.60#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:10:59.60#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:10:59.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:10:59.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:10:59.61$vc4f8/valo=6,772.99 2006.239.08:10:59.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:10:59.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:10:59.61#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:59.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:10:59.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:10:59.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:10:59.61#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:10:59.61#ibcon#first serial, iclass 28, count 0 2006.239.08:10:59.61#ibcon#enter sib2, iclass 28, count 0 2006.239.08:10:59.61#ibcon#flushed, iclass 28, count 0 2006.239.08:10:59.61#ibcon#about to write, iclass 28, count 0 2006.239.08:10:59.61#ibcon#wrote, iclass 28, count 0 2006.239.08:10:59.61#ibcon#about to read 3, iclass 28, count 0 2006.239.08:10:59.62#ibcon#read 3, iclass 28, count 0 2006.239.08:10:59.62#ibcon#about to read 4, iclass 28, count 0 2006.239.08:10:59.62#ibcon#read 4, iclass 28, count 0 2006.239.08:10:59.62#ibcon#about to read 5, iclass 28, count 0 2006.239.08:10:59.62#ibcon#read 5, iclass 28, count 0 2006.239.08:10:59.62#ibcon#about to read 6, iclass 28, count 0 2006.239.08:10:59.62#ibcon#read 6, iclass 28, count 0 2006.239.08:10:59.62#ibcon#end of sib2, iclass 28, count 0 2006.239.08:10:59.62#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:10:59.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:10:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:10:59.62#ibcon#*before write, iclass 28, count 0 2006.239.08:10:59.62#ibcon#enter sib2, iclass 28, count 0 2006.239.08:10:59.62#ibcon#flushed, iclass 28, count 0 2006.239.08:10:59.62#ibcon#about to write, iclass 28, count 0 2006.239.08:10:59.62#ibcon#wrote, iclass 28, count 0 2006.239.08:10:59.62#ibcon#about to read 3, iclass 28, count 0 2006.239.08:10:59.66#ibcon#read 3, iclass 28, count 0 2006.239.08:10:59.66#ibcon#about to read 4, iclass 28, count 0 2006.239.08:10:59.66#ibcon#read 4, iclass 28, count 0 2006.239.08:10:59.66#ibcon#about to read 5, iclass 28, count 0 2006.239.08:10:59.66#ibcon#read 5, iclass 28, count 0 2006.239.08:10:59.66#ibcon#about to read 6, iclass 28, count 0 2006.239.08:10:59.66#ibcon#read 6, iclass 28, count 0 2006.239.08:10:59.66#ibcon#end of sib2, iclass 28, count 0 2006.239.08:10:59.66#ibcon#*after write, iclass 28, count 0 2006.239.08:10:59.66#ibcon#*before return 0, iclass 28, count 0 2006.239.08:10:59.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:10:59.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:10:59.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:10:59.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:10:59.67$vc4f8/va=6,7 2006.239.08:10:59.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.08:10:59.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.08:10:59.67#ibcon#ireg 11 cls_cnt 2 2006.239.08:10:59.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:10:59.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:10:59.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:10:59.71#ibcon#enter wrdev, iclass 30, count 2 2006.239.08:10:59.71#ibcon#first serial, iclass 30, count 2 2006.239.08:10:59.71#ibcon#enter sib2, iclass 30, count 2 2006.239.08:10:59.71#ibcon#flushed, iclass 30, count 2 2006.239.08:10:59.71#ibcon#about to write, iclass 30, count 2 2006.239.08:10:59.71#ibcon#wrote, iclass 30, count 2 2006.239.08:10:59.71#ibcon#about to read 3, iclass 30, count 2 2006.239.08:10:59.73#ibcon#read 3, iclass 30, count 2 2006.239.08:10:59.73#ibcon#about to read 4, iclass 30, count 2 2006.239.08:10:59.73#ibcon#read 4, iclass 30, count 2 2006.239.08:10:59.73#ibcon#about to read 5, iclass 30, count 2 2006.239.08:10:59.73#ibcon#read 5, iclass 30, count 2 2006.239.08:10:59.73#ibcon#about to read 6, iclass 30, count 2 2006.239.08:10:59.73#ibcon#read 6, iclass 30, count 2 2006.239.08:10:59.73#ibcon#end of sib2, iclass 30, count 2 2006.239.08:10:59.73#ibcon#*mode == 0, iclass 30, count 2 2006.239.08:10:59.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.08:10:59.73#ibcon#[25=AT06-07\r\n] 2006.239.08:10:59.73#ibcon#*before write, iclass 30, count 2 2006.239.08:10:59.73#ibcon#enter sib2, iclass 30, count 2 2006.239.08:10:59.73#ibcon#flushed, iclass 30, count 2 2006.239.08:10:59.73#ibcon#about to write, iclass 30, count 2 2006.239.08:10:59.73#ibcon#wrote, iclass 30, count 2 2006.239.08:10:59.73#ibcon#about to read 3, iclass 30, count 2 2006.239.08:10:59.76#ibcon#read 3, iclass 30, count 2 2006.239.08:10:59.76#ibcon#about to read 4, iclass 30, count 2 2006.239.08:10:59.76#ibcon#read 4, iclass 30, count 2 2006.239.08:10:59.76#ibcon#about to read 5, iclass 30, count 2 2006.239.08:10:59.76#ibcon#read 5, iclass 30, count 2 2006.239.08:10:59.76#ibcon#about to read 6, iclass 30, count 2 2006.239.08:10:59.76#ibcon#read 6, iclass 30, count 2 2006.239.08:10:59.76#ibcon#end of sib2, iclass 30, count 2 2006.239.08:10:59.76#ibcon#*after write, iclass 30, count 2 2006.239.08:10:59.76#ibcon#*before return 0, iclass 30, count 2 2006.239.08:10:59.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:10:59.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:10:59.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.08:10:59.76#ibcon#ireg 7 cls_cnt 0 2006.239.08:10:59.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:10:59.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:10:59.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:10:59.88#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:10:59.88#ibcon#first serial, iclass 30, count 0 2006.239.08:10:59.88#ibcon#enter sib2, iclass 30, count 0 2006.239.08:10:59.88#ibcon#flushed, iclass 30, count 0 2006.239.08:10:59.88#ibcon#about to write, iclass 30, count 0 2006.239.08:10:59.88#ibcon#wrote, iclass 30, count 0 2006.239.08:10:59.88#ibcon#about to read 3, iclass 30, count 0 2006.239.08:10:59.90#ibcon#read 3, iclass 30, count 0 2006.239.08:10:59.90#ibcon#about to read 4, iclass 30, count 0 2006.239.08:10:59.90#ibcon#read 4, iclass 30, count 0 2006.239.08:10:59.90#ibcon#about to read 5, iclass 30, count 0 2006.239.08:10:59.90#ibcon#read 5, iclass 30, count 0 2006.239.08:10:59.90#ibcon#about to read 6, iclass 30, count 0 2006.239.08:10:59.90#ibcon#read 6, iclass 30, count 0 2006.239.08:10:59.90#ibcon#end of sib2, iclass 30, count 0 2006.239.08:10:59.90#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:10:59.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:10:59.90#ibcon#[25=USB\r\n] 2006.239.08:10:59.90#ibcon#*before write, iclass 30, count 0 2006.239.08:10:59.90#ibcon#enter sib2, iclass 30, count 0 2006.239.08:10:59.90#ibcon#flushed, iclass 30, count 0 2006.239.08:10:59.90#ibcon#about to write, iclass 30, count 0 2006.239.08:10:59.90#ibcon#wrote, iclass 30, count 0 2006.239.08:10:59.90#ibcon#about to read 3, iclass 30, count 0 2006.239.08:10:59.93#ibcon#read 3, iclass 30, count 0 2006.239.08:10:59.93#ibcon#about to read 4, iclass 30, count 0 2006.239.08:10:59.93#ibcon#read 4, iclass 30, count 0 2006.239.08:10:59.93#ibcon#about to read 5, iclass 30, count 0 2006.239.08:10:59.93#ibcon#read 5, iclass 30, count 0 2006.239.08:10:59.93#ibcon#about to read 6, iclass 30, count 0 2006.239.08:10:59.93#ibcon#read 6, iclass 30, count 0 2006.239.08:10:59.93#ibcon#end of sib2, iclass 30, count 0 2006.239.08:10:59.93#ibcon#*after write, iclass 30, count 0 2006.239.08:10:59.93#ibcon#*before return 0, iclass 30, count 0 2006.239.08:10:59.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:10:59.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:10:59.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:10:59.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:10:59.93$vc4f8/valo=7,832.99 2006.239.08:10:59.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.08:10:59.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.08:10:59.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:10:59.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:10:59.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:10:59.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:10:59.94#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:10:59.94#ibcon#first serial, iclass 32, count 0 2006.239.08:10:59.94#ibcon#enter sib2, iclass 32, count 0 2006.239.08:10:59.94#ibcon#flushed, iclass 32, count 0 2006.239.08:10:59.94#ibcon#about to write, iclass 32, count 0 2006.239.08:10:59.94#ibcon#wrote, iclass 32, count 0 2006.239.08:10:59.94#ibcon#about to read 3, iclass 32, count 0 2006.239.08:10:59.95#ibcon#read 3, iclass 32, count 0 2006.239.08:10:59.95#ibcon#about to read 4, iclass 32, count 0 2006.239.08:10:59.95#ibcon#read 4, iclass 32, count 0 2006.239.08:10:59.95#ibcon#about to read 5, iclass 32, count 0 2006.239.08:10:59.95#ibcon#read 5, iclass 32, count 0 2006.239.08:10:59.95#ibcon#about to read 6, iclass 32, count 0 2006.239.08:10:59.95#ibcon#read 6, iclass 32, count 0 2006.239.08:10:59.95#ibcon#end of sib2, iclass 32, count 0 2006.239.08:10:59.95#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:10:59.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:10:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:10:59.95#ibcon#*before write, iclass 32, count 0 2006.239.08:10:59.95#ibcon#enter sib2, iclass 32, count 0 2006.239.08:10:59.95#ibcon#flushed, iclass 32, count 0 2006.239.08:10:59.95#ibcon#about to write, iclass 32, count 0 2006.239.08:10:59.95#ibcon#wrote, iclass 32, count 0 2006.239.08:10:59.95#ibcon#about to read 3, iclass 32, count 0 2006.239.08:10:59.99#ibcon#read 3, iclass 32, count 0 2006.239.08:10:59.99#ibcon#about to read 4, iclass 32, count 0 2006.239.08:10:59.99#ibcon#read 4, iclass 32, count 0 2006.239.08:10:59.99#ibcon#about to read 5, iclass 32, count 0 2006.239.08:10:59.99#ibcon#read 5, iclass 32, count 0 2006.239.08:10:59.99#ibcon#about to read 6, iclass 32, count 0 2006.239.08:10:59.99#ibcon#read 6, iclass 32, count 0 2006.239.08:10:59.99#ibcon#end of sib2, iclass 32, count 0 2006.239.08:10:59.99#ibcon#*after write, iclass 32, count 0 2006.239.08:10:59.99#ibcon#*before return 0, iclass 32, count 0 2006.239.08:10:59.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:10:59.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:10:59.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:10:59.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:10:59.99$vc4f8/va=7,7 2006.239.08:11:00.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.08:11:00.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.08:11:00.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:00.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:11:00.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:11:00.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:11:00.04#ibcon#enter wrdev, iclass 34, count 2 2006.239.08:11:00.04#ibcon#first serial, iclass 34, count 2 2006.239.08:11:00.04#ibcon#enter sib2, iclass 34, count 2 2006.239.08:11:00.04#ibcon#flushed, iclass 34, count 2 2006.239.08:11:00.04#ibcon#about to write, iclass 34, count 2 2006.239.08:11:00.04#ibcon#wrote, iclass 34, count 2 2006.239.08:11:00.04#ibcon#about to read 3, iclass 34, count 2 2006.239.08:11:00.06#ibcon#read 3, iclass 34, count 2 2006.239.08:11:00.06#ibcon#about to read 4, iclass 34, count 2 2006.239.08:11:00.06#ibcon#read 4, iclass 34, count 2 2006.239.08:11:00.06#ibcon#about to read 5, iclass 34, count 2 2006.239.08:11:00.06#ibcon#read 5, iclass 34, count 2 2006.239.08:11:00.06#ibcon#about to read 6, iclass 34, count 2 2006.239.08:11:00.06#ibcon#read 6, iclass 34, count 2 2006.239.08:11:00.06#ibcon#end of sib2, iclass 34, count 2 2006.239.08:11:00.06#ibcon#*mode == 0, iclass 34, count 2 2006.239.08:11:00.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.08:11:00.06#ibcon#[25=AT07-07\r\n] 2006.239.08:11:00.06#ibcon#*before write, iclass 34, count 2 2006.239.08:11:00.06#ibcon#enter sib2, iclass 34, count 2 2006.239.08:11:00.06#ibcon#flushed, iclass 34, count 2 2006.239.08:11:00.06#ibcon#about to write, iclass 34, count 2 2006.239.08:11:00.06#ibcon#wrote, iclass 34, count 2 2006.239.08:11:00.06#ibcon#about to read 3, iclass 34, count 2 2006.239.08:11:00.09#ibcon#read 3, iclass 34, count 2 2006.239.08:11:00.09#ibcon#about to read 4, iclass 34, count 2 2006.239.08:11:00.09#ibcon#read 4, iclass 34, count 2 2006.239.08:11:00.09#ibcon#about to read 5, iclass 34, count 2 2006.239.08:11:00.09#ibcon#read 5, iclass 34, count 2 2006.239.08:11:00.09#ibcon#about to read 6, iclass 34, count 2 2006.239.08:11:00.09#ibcon#read 6, iclass 34, count 2 2006.239.08:11:00.09#ibcon#end of sib2, iclass 34, count 2 2006.239.08:11:00.09#ibcon#*after write, iclass 34, count 2 2006.239.08:11:00.09#ibcon#*before return 0, iclass 34, count 2 2006.239.08:11:00.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:11:00.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:11:00.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.08:11:00.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:00.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:11:00.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:11:00.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:11:00.21#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:11:00.21#ibcon#first serial, iclass 34, count 0 2006.239.08:11:00.21#ibcon#enter sib2, iclass 34, count 0 2006.239.08:11:00.21#ibcon#flushed, iclass 34, count 0 2006.239.08:11:00.21#ibcon#about to write, iclass 34, count 0 2006.239.08:11:00.21#ibcon#wrote, iclass 34, count 0 2006.239.08:11:00.21#ibcon#about to read 3, iclass 34, count 0 2006.239.08:11:00.23#ibcon#read 3, iclass 34, count 0 2006.239.08:11:00.23#ibcon#about to read 4, iclass 34, count 0 2006.239.08:11:00.23#ibcon#read 4, iclass 34, count 0 2006.239.08:11:00.23#ibcon#about to read 5, iclass 34, count 0 2006.239.08:11:00.23#ibcon#read 5, iclass 34, count 0 2006.239.08:11:00.23#ibcon#about to read 6, iclass 34, count 0 2006.239.08:11:00.23#ibcon#read 6, iclass 34, count 0 2006.239.08:11:00.23#ibcon#end of sib2, iclass 34, count 0 2006.239.08:11:00.23#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:11:00.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:11:00.23#ibcon#[25=USB\r\n] 2006.239.08:11:00.23#ibcon#*before write, iclass 34, count 0 2006.239.08:11:00.23#ibcon#enter sib2, iclass 34, count 0 2006.239.08:11:00.23#ibcon#flushed, iclass 34, count 0 2006.239.08:11:00.23#ibcon#about to write, iclass 34, count 0 2006.239.08:11:00.23#ibcon#wrote, iclass 34, count 0 2006.239.08:11:00.23#ibcon#about to read 3, iclass 34, count 0 2006.239.08:11:00.26#ibcon#read 3, iclass 34, count 0 2006.239.08:11:00.26#ibcon#about to read 4, iclass 34, count 0 2006.239.08:11:00.26#ibcon#read 4, iclass 34, count 0 2006.239.08:11:00.26#ibcon#about to read 5, iclass 34, count 0 2006.239.08:11:00.26#ibcon#read 5, iclass 34, count 0 2006.239.08:11:00.26#ibcon#about to read 6, iclass 34, count 0 2006.239.08:11:00.26#ibcon#read 6, iclass 34, count 0 2006.239.08:11:00.26#ibcon#end of sib2, iclass 34, count 0 2006.239.08:11:00.26#ibcon#*after write, iclass 34, count 0 2006.239.08:11:00.26#ibcon#*before return 0, iclass 34, count 0 2006.239.08:11:00.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:11:00.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:11:00.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:11:00.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:11:00.27$vc4f8/valo=8,852.99 2006.239.08:11:00.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.08:11:00.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.08:11:00.27#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:00.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:11:00.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:11:00.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:11:00.27#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:11:00.27#ibcon#first serial, iclass 36, count 0 2006.239.08:11:00.27#ibcon#enter sib2, iclass 36, count 0 2006.239.08:11:00.27#ibcon#flushed, iclass 36, count 0 2006.239.08:11:00.27#ibcon#about to write, iclass 36, count 0 2006.239.08:11:00.27#ibcon#wrote, iclass 36, count 0 2006.239.08:11:00.27#ibcon#about to read 3, iclass 36, count 0 2006.239.08:11:00.29#ibcon#read 3, iclass 36, count 0 2006.239.08:11:00.29#ibcon#about to read 4, iclass 36, count 0 2006.239.08:11:00.29#ibcon#read 4, iclass 36, count 0 2006.239.08:11:00.29#ibcon#about to read 5, iclass 36, count 0 2006.239.08:11:00.29#ibcon#read 5, iclass 36, count 0 2006.239.08:11:00.29#ibcon#about to read 6, iclass 36, count 0 2006.239.08:11:00.29#ibcon#read 6, iclass 36, count 0 2006.239.08:11:00.29#ibcon#end of sib2, iclass 36, count 0 2006.239.08:11:00.29#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:11:00.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:11:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:11:00.29#ibcon#*before write, iclass 36, count 0 2006.239.08:11:00.29#ibcon#enter sib2, iclass 36, count 0 2006.239.08:11:00.29#ibcon#flushed, iclass 36, count 0 2006.239.08:11:00.29#ibcon#about to write, iclass 36, count 0 2006.239.08:11:00.29#ibcon#wrote, iclass 36, count 0 2006.239.08:11:00.29#ibcon#about to read 3, iclass 36, count 0 2006.239.08:11:00.33#ibcon#read 3, iclass 36, count 0 2006.239.08:11:00.33#ibcon#about to read 4, iclass 36, count 0 2006.239.08:11:00.33#ibcon#read 4, iclass 36, count 0 2006.239.08:11:00.33#ibcon#about to read 5, iclass 36, count 0 2006.239.08:11:00.33#ibcon#read 5, iclass 36, count 0 2006.239.08:11:00.33#ibcon#about to read 6, iclass 36, count 0 2006.239.08:11:00.33#ibcon#read 6, iclass 36, count 0 2006.239.08:11:00.33#ibcon#end of sib2, iclass 36, count 0 2006.239.08:11:00.33#ibcon#*after write, iclass 36, count 0 2006.239.08:11:00.33#ibcon#*before return 0, iclass 36, count 0 2006.239.08:11:00.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:11:00.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:11:00.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:11:00.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:11:00.34$vc4f8/va=8,7 2006.239.08:11:00.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.08:11:00.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.08:11:00.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:00.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:11:00.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:11:00.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:11:00.38#ibcon#enter wrdev, iclass 38, count 2 2006.239.08:11:00.38#ibcon#first serial, iclass 38, count 2 2006.239.08:11:00.38#ibcon#enter sib2, iclass 38, count 2 2006.239.08:11:00.38#ibcon#flushed, iclass 38, count 2 2006.239.08:11:00.38#ibcon#about to write, iclass 38, count 2 2006.239.08:11:00.38#ibcon#wrote, iclass 38, count 2 2006.239.08:11:00.38#ibcon#about to read 3, iclass 38, count 2 2006.239.08:11:00.39#ibcon#read 3, iclass 38, count 2 2006.239.08:11:00.39#ibcon#about to read 4, iclass 38, count 2 2006.239.08:11:00.39#ibcon#read 4, iclass 38, count 2 2006.239.08:11:00.39#ibcon#about to read 5, iclass 38, count 2 2006.239.08:11:00.39#ibcon#read 5, iclass 38, count 2 2006.239.08:11:00.39#ibcon#about to read 6, iclass 38, count 2 2006.239.08:11:00.39#ibcon#read 6, iclass 38, count 2 2006.239.08:11:00.39#ibcon#end of sib2, iclass 38, count 2 2006.239.08:11:00.39#ibcon#*mode == 0, iclass 38, count 2 2006.239.08:11:00.39#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.08:11:00.39#ibcon#[25=AT08-07\r\n] 2006.239.08:11:00.39#ibcon#*before write, iclass 38, count 2 2006.239.08:11:00.39#ibcon#enter sib2, iclass 38, count 2 2006.239.08:11:00.39#ibcon#flushed, iclass 38, count 2 2006.239.08:11:00.39#ibcon#about to write, iclass 38, count 2 2006.239.08:11:00.39#ibcon#wrote, iclass 38, count 2 2006.239.08:11:00.39#ibcon#about to read 3, iclass 38, count 2 2006.239.08:11:00.42#ibcon#read 3, iclass 38, count 2 2006.239.08:11:00.42#ibcon#about to read 4, iclass 38, count 2 2006.239.08:11:00.42#ibcon#read 4, iclass 38, count 2 2006.239.08:11:00.42#ibcon#about to read 5, iclass 38, count 2 2006.239.08:11:00.42#ibcon#read 5, iclass 38, count 2 2006.239.08:11:00.42#ibcon#about to read 6, iclass 38, count 2 2006.239.08:11:00.42#ibcon#read 6, iclass 38, count 2 2006.239.08:11:00.42#ibcon#end of sib2, iclass 38, count 2 2006.239.08:11:00.42#ibcon#*after write, iclass 38, count 2 2006.239.08:11:00.42#ibcon#*before return 0, iclass 38, count 2 2006.239.08:11:00.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:11:00.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:11:00.42#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.08:11:00.42#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:00.42#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:11:00.54#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:11:00.54#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:11:00.54#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:11:00.54#ibcon#first serial, iclass 38, count 0 2006.239.08:11:00.54#ibcon#enter sib2, iclass 38, count 0 2006.239.08:11:00.54#ibcon#flushed, iclass 38, count 0 2006.239.08:11:00.54#ibcon#about to write, iclass 38, count 0 2006.239.08:11:00.54#ibcon#wrote, iclass 38, count 0 2006.239.08:11:00.54#ibcon#about to read 3, iclass 38, count 0 2006.239.08:11:00.56#ibcon#read 3, iclass 38, count 0 2006.239.08:11:00.56#ibcon#about to read 4, iclass 38, count 0 2006.239.08:11:00.56#ibcon#read 4, iclass 38, count 0 2006.239.08:11:00.56#ibcon#about to read 5, iclass 38, count 0 2006.239.08:11:00.56#ibcon#read 5, iclass 38, count 0 2006.239.08:11:00.56#ibcon#about to read 6, iclass 38, count 0 2006.239.08:11:00.56#ibcon#read 6, iclass 38, count 0 2006.239.08:11:00.56#ibcon#end of sib2, iclass 38, count 0 2006.239.08:11:00.56#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:11:00.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:11:00.56#ibcon#[25=USB\r\n] 2006.239.08:11:00.56#ibcon#*before write, iclass 38, count 0 2006.239.08:11:00.56#ibcon#enter sib2, iclass 38, count 0 2006.239.08:11:00.56#ibcon#flushed, iclass 38, count 0 2006.239.08:11:00.56#ibcon#about to write, iclass 38, count 0 2006.239.08:11:00.56#ibcon#wrote, iclass 38, count 0 2006.239.08:11:00.56#ibcon#about to read 3, iclass 38, count 0 2006.239.08:11:00.59#ibcon#read 3, iclass 38, count 0 2006.239.08:11:00.59#ibcon#about to read 4, iclass 38, count 0 2006.239.08:11:00.59#ibcon#read 4, iclass 38, count 0 2006.239.08:11:00.59#ibcon#about to read 5, iclass 38, count 0 2006.239.08:11:00.59#ibcon#read 5, iclass 38, count 0 2006.239.08:11:00.59#ibcon#about to read 6, iclass 38, count 0 2006.239.08:11:00.59#ibcon#read 6, iclass 38, count 0 2006.239.08:11:00.59#ibcon#end of sib2, iclass 38, count 0 2006.239.08:11:00.59#ibcon#*after write, iclass 38, count 0 2006.239.08:11:00.59#ibcon#*before return 0, iclass 38, count 0 2006.239.08:11:00.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:11:00.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:11:00.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:11:00.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:11:00.59$vc4f8/vblo=1,632.99 2006.239.08:11:00.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.08:11:00.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.08:11:00.60#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:00.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:11:00.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:11:00.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:11:00.60#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:11:00.60#ibcon#first serial, iclass 40, count 0 2006.239.08:11:00.60#ibcon#enter sib2, iclass 40, count 0 2006.239.08:11:00.60#ibcon#flushed, iclass 40, count 0 2006.239.08:11:00.60#ibcon#about to write, iclass 40, count 0 2006.239.08:11:00.60#ibcon#wrote, iclass 40, count 0 2006.239.08:11:00.60#ibcon#about to read 3, iclass 40, count 0 2006.239.08:11:00.61#ibcon#read 3, iclass 40, count 0 2006.239.08:11:00.61#ibcon#about to read 4, iclass 40, count 0 2006.239.08:11:00.61#ibcon#read 4, iclass 40, count 0 2006.239.08:11:00.61#ibcon#about to read 5, iclass 40, count 0 2006.239.08:11:00.61#ibcon#read 5, iclass 40, count 0 2006.239.08:11:00.61#ibcon#about to read 6, iclass 40, count 0 2006.239.08:11:00.61#ibcon#read 6, iclass 40, count 0 2006.239.08:11:00.61#ibcon#end of sib2, iclass 40, count 0 2006.239.08:11:00.61#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:11:00.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:11:00.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:11:00.61#ibcon#*before write, iclass 40, count 0 2006.239.08:11:00.61#ibcon#enter sib2, iclass 40, count 0 2006.239.08:11:00.61#ibcon#flushed, iclass 40, count 0 2006.239.08:11:00.61#ibcon#about to write, iclass 40, count 0 2006.239.08:11:00.61#ibcon#wrote, iclass 40, count 0 2006.239.08:11:00.61#ibcon#about to read 3, iclass 40, count 0 2006.239.08:11:00.65#ibcon#read 3, iclass 40, count 0 2006.239.08:11:00.65#ibcon#about to read 4, iclass 40, count 0 2006.239.08:11:00.65#ibcon#read 4, iclass 40, count 0 2006.239.08:11:00.65#ibcon#about to read 5, iclass 40, count 0 2006.239.08:11:00.65#ibcon#read 5, iclass 40, count 0 2006.239.08:11:00.65#ibcon#about to read 6, iclass 40, count 0 2006.239.08:11:00.65#ibcon#read 6, iclass 40, count 0 2006.239.08:11:00.65#ibcon#end of sib2, iclass 40, count 0 2006.239.08:11:00.65#ibcon#*after write, iclass 40, count 0 2006.239.08:11:00.65#ibcon#*before return 0, iclass 40, count 0 2006.239.08:11:00.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:11:00.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:11:00.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:11:00.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:11:00.65$vc4f8/vb=1,4 2006.239.08:11:00.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.08:11:00.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.08:11:00.66#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:00.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:11:00.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:11:00.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:11:00.66#ibcon#enter wrdev, iclass 4, count 2 2006.239.08:11:00.66#ibcon#first serial, iclass 4, count 2 2006.239.08:11:00.66#ibcon#enter sib2, iclass 4, count 2 2006.239.08:11:00.66#ibcon#flushed, iclass 4, count 2 2006.239.08:11:00.66#ibcon#about to write, iclass 4, count 2 2006.239.08:11:00.66#ibcon#wrote, iclass 4, count 2 2006.239.08:11:00.66#ibcon#about to read 3, iclass 4, count 2 2006.239.08:11:00.67#ibcon#read 3, iclass 4, count 2 2006.239.08:11:00.67#ibcon#about to read 4, iclass 4, count 2 2006.239.08:11:00.67#ibcon#read 4, iclass 4, count 2 2006.239.08:11:00.67#ibcon#about to read 5, iclass 4, count 2 2006.239.08:11:00.67#ibcon#read 5, iclass 4, count 2 2006.239.08:11:00.67#ibcon#about to read 6, iclass 4, count 2 2006.239.08:11:00.67#ibcon#read 6, iclass 4, count 2 2006.239.08:11:00.67#ibcon#end of sib2, iclass 4, count 2 2006.239.08:11:00.67#ibcon#*mode == 0, iclass 4, count 2 2006.239.08:11:00.67#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.08:11:00.67#ibcon#[27=AT01-04\r\n] 2006.239.08:11:00.67#ibcon#*before write, iclass 4, count 2 2006.239.08:11:00.67#ibcon#enter sib2, iclass 4, count 2 2006.239.08:11:00.67#ibcon#flushed, iclass 4, count 2 2006.239.08:11:00.67#ibcon#about to write, iclass 4, count 2 2006.239.08:11:00.67#ibcon#wrote, iclass 4, count 2 2006.239.08:11:00.67#ibcon#about to read 3, iclass 4, count 2 2006.239.08:11:00.70#ibcon#read 3, iclass 4, count 2 2006.239.08:11:00.70#ibcon#about to read 4, iclass 4, count 2 2006.239.08:11:00.70#ibcon#read 4, iclass 4, count 2 2006.239.08:11:00.70#ibcon#about to read 5, iclass 4, count 2 2006.239.08:11:00.70#ibcon#read 5, iclass 4, count 2 2006.239.08:11:00.70#ibcon#about to read 6, iclass 4, count 2 2006.239.08:11:00.70#ibcon#read 6, iclass 4, count 2 2006.239.08:11:00.70#ibcon#end of sib2, iclass 4, count 2 2006.239.08:11:00.70#ibcon#*after write, iclass 4, count 2 2006.239.08:11:00.70#ibcon#*before return 0, iclass 4, count 2 2006.239.08:11:00.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:11:00.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:11:00.70#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.08:11:00.70#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:00.70#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:11:00.82#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:11:00.82#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:11:00.82#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:11:00.82#ibcon#first serial, iclass 4, count 0 2006.239.08:11:00.82#ibcon#enter sib2, iclass 4, count 0 2006.239.08:11:00.82#ibcon#flushed, iclass 4, count 0 2006.239.08:11:00.82#ibcon#about to write, iclass 4, count 0 2006.239.08:11:00.82#ibcon#wrote, iclass 4, count 0 2006.239.08:11:00.82#ibcon#about to read 3, iclass 4, count 0 2006.239.08:11:00.84#ibcon#read 3, iclass 4, count 0 2006.239.08:11:00.84#ibcon#about to read 4, iclass 4, count 0 2006.239.08:11:00.84#ibcon#read 4, iclass 4, count 0 2006.239.08:11:00.84#ibcon#about to read 5, iclass 4, count 0 2006.239.08:11:00.84#ibcon#read 5, iclass 4, count 0 2006.239.08:11:00.84#ibcon#about to read 6, iclass 4, count 0 2006.239.08:11:00.84#ibcon#read 6, iclass 4, count 0 2006.239.08:11:00.84#ibcon#end of sib2, iclass 4, count 0 2006.239.08:11:00.84#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:11:00.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:11:00.84#ibcon#[27=USB\r\n] 2006.239.08:11:00.84#ibcon#*before write, iclass 4, count 0 2006.239.08:11:00.84#ibcon#enter sib2, iclass 4, count 0 2006.239.08:11:00.84#ibcon#flushed, iclass 4, count 0 2006.239.08:11:00.84#ibcon#about to write, iclass 4, count 0 2006.239.08:11:00.84#ibcon#wrote, iclass 4, count 0 2006.239.08:11:00.84#ibcon#about to read 3, iclass 4, count 0 2006.239.08:11:00.87#ibcon#read 3, iclass 4, count 0 2006.239.08:11:00.87#ibcon#about to read 4, iclass 4, count 0 2006.239.08:11:00.87#ibcon#read 4, iclass 4, count 0 2006.239.08:11:00.87#ibcon#about to read 5, iclass 4, count 0 2006.239.08:11:00.87#ibcon#read 5, iclass 4, count 0 2006.239.08:11:00.87#ibcon#about to read 6, iclass 4, count 0 2006.239.08:11:00.87#ibcon#read 6, iclass 4, count 0 2006.239.08:11:00.87#ibcon#end of sib2, iclass 4, count 0 2006.239.08:11:00.87#ibcon#*after write, iclass 4, count 0 2006.239.08:11:00.87#ibcon#*before return 0, iclass 4, count 0 2006.239.08:11:00.87#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:11:00.87#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:11:00.87#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:11:00.87#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:11:00.88$vc4f8/vblo=2,640.99 2006.239.08:11:00.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.08:11:00.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.08:11:00.88#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:00.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:11:00.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:11:00.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:11:00.88#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:11:00.88#ibcon#first serial, iclass 6, count 0 2006.239.08:11:00.88#ibcon#enter sib2, iclass 6, count 0 2006.239.08:11:00.88#ibcon#flushed, iclass 6, count 0 2006.239.08:11:00.88#ibcon#about to write, iclass 6, count 0 2006.239.08:11:00.88#ibcon#wrote, iclass 6, count 0 2006.239.08:11:00.88#ibcon#about to read 3, iclass 6, count 0 2006.239.08:11:00.89#ibcon#read 3, iclass 6, count 0 2006.239.08:11:00.89#ibcon#about to read 4, iclass 6, count 0 2006.239.08:11:00.89#ibcon#read 4, iclass 6, count 0 2006.239.08:11:00.89#ibcon#about to read 5, iclass 6, count 0 2006.239.08:11:00.89#ibcon#read 5, iclass 6, count 0 2006.239.08:11:00.89#ibcon#about to read 6, iclass 6, count 0 2006.239.08:11:00.89#ibcon#read 6, iclass 6, count 0 2006.239.08:11:00.89#ibcon#end of sib2, iclass 6, count 0 2006.239.08:11:00.89#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:11:00.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:11:00.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:11:00.89#ibcon#*before write, iclass 6, count 0 2006.239.08:11:00.89#ibcon#enter sib2, iclass 6, count 0 2006.239.08:11:00.89#ibcon#flushed, iclass 6, count 0 2006.239.08:11:00.89#ibcon#about to write, iclass 6, count 0 2006.239.08:11:00.89#ibcon#wrote, iclass 6, count 0 2006.239.08:11:00.89#ibcon#about to read 3, iclass 6, count 0 2006.239.08:11:00.93#ibcon#read 3, iclass 6, count 0 2006.239.08:11:00.93#ibcon#about to read 4, iclass 6, count 0 2006.239.08:11:00.93#ibcon#read 4, iclass 6, count 0 2006.239.08:11:00.93#ibcon#about to read 5, iclass 6, count 0 2006.239.08:11:00.93#ibcon#read 5, iclass 6, count 0 2006.239.08:11:00.93#ibcon#about to read 6, iclass 6, count 0 2006.239.08:11:00.93#ibcon#read 6, iclass 6, count 0 2006.239.08:11:00.93#ibcon#end of sib2, iclass 6, count 0 2006.239.08:11:00.93#ibcon#*after write, iclass 6, count 0 2006.239.08:11:00.93#ibcon#*before return 0, iclass 6, count 0 2006.239.08:11:00.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:11:00.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:11:00.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:11:00.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:11:00.93$vc4f8/vb=2,4 2006.239.08:11:00.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.08:11:00.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.08:11:00.94#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:00.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:11:00.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:11:00.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:11:00.98#ibcon#enter wrdev, iclass 10, count 2 2006.239.08:11:00.98#ibcon#first serial, iclass 10, count 2 2006.239.08:11:00.98#ibcon#enter sib2, iclass 10, count 2 2006.239.08:11:00.98#ibcon#flushed, iclass 10, count 2 2006.239.08:11:00.98#ibcon#about to write, iclass 10, count 2 2006.239.08:11:00.98#ibcon#wrote, iclass 10, count 2 2006.239.08:11:00.98#ibcon#about to read 3, iclass 10, count 2 2006.239.08:11:01.00#ibcon#read 3, iclass 10, count 2 2006.239.08:11:01.00#ibcon#about to read 4, iclass 10, count 2 2006.239.08:11:01.00#ibcon#read 4, iclass 10, count 2 2006.239.08:11:01.00#ibcon#about to read 5, iclass 10, count 2 2006.239.08:11:01.00#ibcon#read 5, iclass 10, count 2 2006.239.08:11:01.00#ibcon#about to read 6, iclass 10, count 2 2006.239.08:11:01.00#ibcon#read 6, iclass 10, count 2 2006.239.08:11:01.00#ibcon#end of sib2, iclass 10, count 2 2006.239.08:11:01.00#ibcon#*mode == 0, iclass 10, count 2 2006.239.08:11:01.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.08:11:01.00#ibcon#[27=AT02-04\r\n] 2006.239.08:11:01.00#ibcon#*before write, iclass 10, count 2 2006.239.08:11:01.00#ibcon#enter sib2, iclass 10, count 2 2006.239.08:11:01.00#ibcon#flushed, iclass 10, count 2 2006.239.08:11:01.00#ibcon#about to write, iclass 10, count 2 2006.239.08:11:01.00#ibcon#wrote, iclass 10, count 2 2006.239.08:11:01.00#ibcon#about to read 3, iclass 10, count 2 2006.239.08:11:01.03#ibcon#read 3, iclass 10, count 2 2006.239.08:11:01.03#ibcon#about to read 4, iclass 10, count 2 2006.239.08:11:01.03#ibcon#read 4, iclass 10, count 2 2006.239.08:11:01.03#ibcon#about to read 5, iclass 10, count 2 2006.239.08:11:01.03#ibcon#read 5, iclass 10, count 2 2006.239.08:11:01.03#ibcon#about to read 6, iclass 10, count 2 2006.239.08:11:01.03#ibcon#read 6, iclass 10, count 2 2006.239.08:11:01.03#ibcon#end of sib2, iclass 10, count 2 2006.239.08:11:01.03#ibcon#*after write, iclass 10, count 2 2006.239.08:11:01.03#ibcon#*before return 0, iclass 10, count 2 2006.239.08:11:01.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:11:01.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:11:01.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.08:11:01.03#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:01.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:11:01.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:11:01.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:11:01.15#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:11:01.15#ibcon#first serial, iclass 10, count 0 2006.239.08:11:01.15#ibcon#enter sib2, iclass 10, count 0 2006.239.08:11:01.15#ibcon#flushed, iclass 10, count 0 2006.239.08:11:01.15#ibcon#about to write, iclass 10, count 0 2006.239.08:11:01.15#ibcon#wrote, iclass 10, count 0 2006.239.08:11:01.15#ibcon#about to read 3, iclass 10, count 0 2006.239.08:11:01.17#ibcon#read 3, iclass 10, count 0 2006.239.08:11:01.17#ibcon#about to read 4, iclass 10, count 0 2006.239.08:11:01.17#ibcon#read 4, iclass 10, count 0 2006.239.08:11:01.17#ibcon#about to read 5, iclass 10, count 0 2006.239.08:11:01.17#ibcon#read 5, iclass 10, count 0 2006.239.08:11:01.17#ibcon#about to read 6, iclass 10, count 0 2006.239.08:11:01.17#ibcon#read 6, iclass 10, count 0 2006.239.08:11:01.17#ibcon#end of sib2, iclass 10, count 0 2006.239.08:11:01.17#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:11:01.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:11:01.17#ibcon#[27=USB\r\n] 2006.239.08:11:01.17#ibcon#*before write, iclass 10, count 0 2006.239.08:11:01.17#ibcon#enter sib2, iclass 10, count 0 2006.239.08:11:01.17#ibcon#flushed, iclass 10, count 0 2006.239.08:11:01.17#ibcon#about to write, iclass 10, count 0 2006.239.08:11:01.17#ibcon#wrote, iclass 10, count 0 2006.239.08:11:01.17#ibcon#about to read 3, iclass 10, count 0 2006.239.08:11:01.20#ibcon#read 3, iclass 10, count 0 2006.239.08:11:01.20#ibcon#about to read 4, iclass 10, count 0 2006.239.08:11:01.20#ibcon#read 4, iclass 10, count 0 2006.239.08:11:01.20#ibcon#about to read 5, iclass 10, count 0 2006.239.08:11:01.20#ibcon#read 5, iclass 10, count 0 2006.239.08:11:01.20#ibcon#about to read 6, iclass 10, count 0 2006.239.08:11:01.20#ibcon#read 6, iclass 10, count 0 2006.239.08:11:01.20#ibcon#end of sib2, iclass 10, count 0 2006.239.08:11:01.20#ibcon#*after write, iclass 10, count 0 2006.239.08:11:01.20#ibcon#*before return 0, iclass 10, count 0 2006.239.08:11:01.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:11:01.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:11:01.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:11:01.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:11:01.21$vc4f8/vblo=3,656.99 2006.239.08:11:01.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.08:11:01.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.08:11:01.21#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:01.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:11:01.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:11:01.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:11:01.21#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:11:01.21#ibcon#first serial, iclass 12, count 0 2006.239.08:11:01.21#ibcon#enter sib2, iclass 12, count 0 2006.239.08:11:01.21#ibcon#flushed, iclass 12, count 0 2006.239.08:11:01.21#ibcon#about to write, iclass 12, count 0 2006.239.08:11:01.21#ibcon#wrote, iclass 12, count 0 2006.239.08:11:01.21#ibcon#about to read 3, iclass 12, count 0 2006.239.08:11:01.22#ibcon#read 3, iclass 12, count 0 2006.239.08:11:01.22#ibcon#about to read 4, iclass 12, count 0 2006.239.08:11:01.22#ibcon#read 4, iclass 12, count 0 2006.239.08:11:01.22#ibcon#about to read 5, iclass 12, count 0 2006.239.08:11:01.22#ibcon#read 5, iclass 12, count 0 2006.239.08:11:01.22#ibcon#about to read 6, iclass 12, count 0 2006.239.08:11:01.22#ibcon#read 6, iclass 12, count 0 2006.239.08:11:01.22#ibcon#end of sib2, iclass 12, count 0 2006.239.08:11:01.22#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:11:01.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:11:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:11:01.22#ibcon#*before write, iclass 12, count 0 2006.239.08:11:01.22#ibcon#enter sib2, iclass 12, count 0 2006.239.08:11:01.22#ibcon#flushed, iclass 12, count 0 2006.239.08:11:01.22#ibcon#about to write, iclass 12, count 0 2006.239.08:11:01.22#ibcon#wrote, iclass 12, count 0 2006.239.08:11:01.22#ibcon#about to read 3, iclass 12, count 0 2006.239.08:11:01.26#ibcon#read 3, iclass 12, count 0 2006.239.08:11:01.26#ibcon#about to read 4, iclass 12, count 0 2006.239.08:11:01.26#ibcon#read 4, iclass 12, count 0 2006.239.08:11:01.26#ibcon#about to read 5, iclass 12, count 0 2006.239.08:11:01.26#ibcon#read 5, iclass 12, count 0 2006.239.08:11:01.26#ibcon#about to read 6, iclass 12, count 0 2006.239.08:11:01.26#ibcon#read 6, iclass 12, count 0 2006.239.08:11:01.26#ibcon#end of sib2, iclass 12, count 0 2006.239.08:11:01.26#ibcon#*after write, iclass 12, count 0 2006.239.08:11:01.26#ibcon#*before return 0, iclass 12, count 0 2006.239.08:11:01.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:11:01.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:11:01.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:11:01.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:11:01.27$vc4f8/vb=3,4 2006.239.08:11:01.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.08:11:01.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.08:11:01.27#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:01.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:11:01.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:11:01.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:11:01.31#ibcon#enter wrdev, iclass 14, count 2 2006.239.08:11:01.31#ibcon#first serial, iclass 14, count 2 2006.239.08:11:01.31#ibcon#enter sib2, iclass 14, count 2 2006.239.08:11:01.31#ibcon#flushed, iclass 14, count 2 2006.239.08:11:01.31#ibcon#about to write, iclass 14, count 2 2006.239.08:11:01.31#ibcon#wrote, iclass 14, count 2 2006.239.08:11:01.31#ibcon#about to read 3, iclass 14, count 2 2006.239.08:11:01.33#ibcon#read 3, iclass 14, count 2 2006.239.08:11:01.33#ibcon#about to read 4, iclass 14, count 2 2006.239.08:11:01.33#ibcon#read 4, iclass 14, count 2 2006.239.08:11:01.33#ibcon#about to read 5, iclass 14, count 2 2006.239.08:11:01.33#ibcon#read 5, iclass 14, count 2 2006.239.08:11:01.33#ibcon#about to read 6, iclass 14, count 2 2006.239.08:11:01.33#ibcon#read 6, iclass 14, count 2 2006.239.08:11:01.33#ibcon#end of sib2, iclass 14, count 2 2006.239.08:11:01.33#ibcon#*mode == 0, iclass 14, count 2 2006.239.08:11:01.33#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.08:11:01.33#ibcon#[27=AT03-04\r\n] 2006.239.08:11:01.33#ibcon#*before write, iclass 14, count 2 2006.239.08:11:01.33#ibcon#enter sib2, iclass 14, count 2 2006.239.08:11:01.33#ibcon#flushed, iclass 14, count 2 2006.239.08:11:01.33#ibcon#about to write, iclass 14, count 2 2006.239.08:11:01.33#ibcon#wrote, iclass 14, count 2 2006.239.08:11:01.33#ibcon#about to read 3, iclass 14, count 2 2006.239.08:11:01.36#ibcon#read 3, iclass 14, count 2 2006.239.08:11:01.36#ibcon#about to read 4, iclass 14, count 2 2006.239.08:11:01.36#ibcon#read 4, iclass 14, count 2 2006.239.08:11:01.36#ibcon#about to read 5, iclass 14, count 2 2006.239.08:11:01.36#ibcon#read 5, iclass 14, count 2 2006.239.08:11:01.36#ibcon#about to read 6, iclass 14, count 2 2006.239.08:11:01.36#ibcon#read 6, iclass 14, count 2 2006.239.08:11:01.36#ibcon#end of sib2, iclass 14, count 2 2006.239.08:11:01.36#ibcon#*after write, iclass 14, count 2 2006.239.08:11:01.36#ibcon#*before return 0, iclass 14, count 2 2006.239.08:11:01.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:11:01.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:11:01.36#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.08:11:01.36#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:01.36#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:11:01.48#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:11:01.48#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:11:01.48#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:11:01.48#ibcon#first serial, iclass 14, count 0 2006.239.08:11:01.48#ibcon#enter sib2, iclass 14, count 0 2006.239.08:11:01.48#ibcon#flushed, iclass 14, count 0 2006.239.08:11:01.48#ibcon#about to write, iclass 14, count 0 2006.239.08:11:01.48#ibcon#wrote, iclass 14, count 0 2006.239.08:11:01.48#ibcon#about to read 3, iclass 14, count 0 2006.239.08:11:01.50#ibcon#read 3, iclass 14, count 0 2006.239.08:11:01.50#ibcon#about to read 4, iclass 14, count 0 2006.239.08:11:01.50#ibcon#read 4, iclass 14, count 0 2006.239.08:11:01.50#ibcon#about to read 5, iclass 14, count 0 2006.239.08:11:01.50#ibcon#read 5, iclass 14, count 0 2006.239.08:11:01.50#ibcon#about to read 6, iclass 14, count 0 2006.239.08:11:01.50#ibcon#read 6, iclass 14, count 0 2006.239.08:11:01.50#ibcon#end of sib2, iclass 14, count 0 2006.239.08:11:01.50#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:11:01.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:11:01.50#ibcon#[27=USB\r\n] 2006.239.08:11:01.50#ibcon#*before write, iclass 14, count 0 2006.239.08:11:01.50#ibcon#enter sib2, iclass 14, count 0 2006.239.08:11:01.50#ibcon#flushed, iclass 14, count 0 2006.239.08:11:01.50#ibcon#about to write, iclass 14, count 0 2006.239.08:11:01.50#ibcon#wrote, iclass 14, count 0 2006.239.08:11:01.50#ibcon#about to read 3, iclass 14, count 0 2006.239.08:11:01.53#ibcon#read 3, iclass 14, count 0 2006.239.08:11:01.53#ibcon#about to read 4, iclass 14, count 0 2006.239.08:11:01.53#ibcon#read 4, iclass 14, count 0 2006.239.08:11:01.53#ibcon#about to read 5, iclass 14, count 0 2006.239.08:11:01.53#ibcon#read 5, iclass 14, count 0 2006.239.08:11:01.53#ibcon#about to read 6, iclass 14, count 0 2006.239.08:11:01.53#ibcon#read 6, iclass 14, count 0 2006.239.08:11:01.53#ibcon#end of sib2, iclass 14, count 0 2006.239.08:11:01.53#ibcon#*after write, iclass 14, count 0 2006.239.08:11:01.53#ibcon#*before return 0, iclass 14, count 0 2006.239.08:11:01.53#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:11:01.53#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:11:01.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:11:01.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:11:01.54$vc4f8/vblo=4,712.99 2006.239.08:11:01.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.08:11:01.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.08:11:01.54#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:01.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:11:01.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:11:01.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:11:01.54#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:11:01.54#ibcon#first serial, iclass 16, count 0 2006.239.08:11:01.54#ibcon#enter sib2, iclass 16, count 0 2006.239.08:11:01.54#ibcon#flushed, iclass 16, count 0 2006.239.08:11:01.54#ibcon#about to write, iclass 16, count 0 2006.239.08:11:01.54#ibcon#wrote, iclass 16, count 0 2006.239.08:11:01.54#ibcon#about to read 3, iclass 16, count 0 2006.239.08:11:01.55#ibcon#read 3, iclass 16, count 0 2006.239.08:11:01.55#ibcon#about to read 4, iclass 16, count 0 2006.239.08:11:01.55#ibcon#read 4, iclass 16, count 0 2006.239.08:11:01.55#ibcon#about to read 5, iclass 16, count 0 2006.239.08:11:01.55#ibcon#read 5, iclass 16, count 0 2006.239.08:11:01.55#ibcon#about to read 6, iclass 16, count 0 2006.239.08:11:01.55#ibcon#read 6, iclass 16, count 0 2006.239.08:11:01.55#ibcon#end of sib2, iclass 16, count 0 2006.239.08:11:01.55#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:11:01.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:11:01.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:11:01.55#ibcon#*before write, iclass 16, count 0 2006.239.08:11:01.55#ibcon#enter sib2, iclass 16, count 0 2006.239.08:11:01.55#ibcon#flushed, iclass 16, count 0 2006.239.08:11:01.55#ibcon#about to write, iclass 16, count 0 2006.239.08:11:01.55#ibcon#wrote, iclass 16, count 0 2006.239.08:11:01.55#ibcon#about to read 3, iclass 16, count 0 2006.239.08:11:01.59#ibcon#read 3, iclass 16, count 0 2006.239.08:11:01.59#ibcon#about to read 4, iclass 16, count 0 2006.239.08:11:01.59#ibcon#read 4, iclass 16, count 0 2006.239.08:11:01.59#ibcon#about to read 5, iclass 16, count 0 2006.239.08:11:01.59#ibcon#read 5, iclass 16, count 0 2006.239.08:11:01.59#ibcon#about to read 6, iclass 16, count 0 2006.239.08:11:01.59#ibcon#read 6, iclass 16, count 0 2006.239.08:11:01.59#ibcon#end of sib2, iclass 16, count 0 2006.239.08:11:01.59#ibcon#*after write, iclass 16, count 0 2006.239.08:11:01.59#ibcon#*before return 0, iclass 16, count 0 2006.239.08:11:01.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:11:01.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:11:01.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:11:01.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:11:01.59$vc4f8/vb=4,4 2006.239.08:11:01.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.08:11:01.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.08:11:01.60#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:01.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:11:01.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:11:01.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:11:01.64#ibcon#enter wrdev, iclass 18, count 2 2006.239.08:11:01.64#ibcon#first serial, iclass 18, count 2 2006.239.08:11:01.64#ibcon#enter sib2, iclass 18, count 2 2006.239.08:11:01.64#ibcon#flushed, iclass 18, count 2 2006.239.08:11:01.64#ibcon#about to write, iclass 18, count 2 2006.239.08:11:01.64#ibcon#wrote, iclass 18, count 2 2006.239.08:11:01.64#ibcon#about to read 3, iclass 18, count 2 2006.239.08:11:01.66#ibcon#read 3, iclass 18, count 2 2006.239.08:11:01.66#ibcon#about to read 4, iclass 18, count 2 2006.239.08:11:01.66#ibcon#read 4, iclass 18, count 2 2006.239.08:11:01.66#ibcon#about to read 5, iclass 18, count 2 2006.239.08:11:01.66#ibcon#read 5, iclass 18, count 2 2006.239.08:11:01.66#ibcon#about to read 6, iclass 18, count 2 2006.239.08:11:01.66#ibcon#read 6, iclass 18, count 2 2006.239.08:11:01.66#ibcon#end of sib2, iclass 18, count 2 2006.239.08:11:01.66#ibcon#*mode == 0, iclass 18, count 2 2006.239.08:11:01.66#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.08:11:01.66#ibcon#[27=AT04-04\r\n] 2006.239.08:11:01.66#ibcon#*before write, iclass 18, count 2 2006.239.08:11:01.66#ibcon#enter sib2, iclass 18, count 2 2006.239.08:11:01.66#ibcon#flushed, iclass 18, count 2 2006.239.08:11:01.66#ibcon#about to write, iclass 18, count 2 2006.239.08:11:01.66#ibcon#wrote, iclass 18, count 2 2006.239.08:11:01.66#ibcon#about to read 3, iclass 18, count 2 2006.239.08:11:01.69#ibcon#read 3, iclass 18, count 2 2006.239.08:11:01.69#ibcon#about to read 4, iclass 18, count 2 2006.239.08:11:01.69#ibcon#read 4, iclass 18, count 2 2006.239.08:11:01.69#ibcon#about to read 5, iclass 18, count 2 2006.239.08:11:01.69#ibcon#read 5, iclass 18, count 2 2006.239.08:11:01.69#ibcon#about to read 6, iclass 18, count 2 2006.239.08:11:01.69#ibcon#read 6, iclass 18, count 2 2006.239.08:11:01.69#ibcon#end of sib2, iclass 18, count 2 2006.239.08:11:01.69#ibcon#*after write, iclass 18, count 2 2006.239.08:11:01.69#ibcon#*before return 0, iclass 18, count 2 2006.239.08:11:01.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:11:01.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:11:01.69#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.08:11:01.69#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:01.69#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:11:01.83#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:11:01.83#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:11:01.83#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:11:01.83#ibcon#first serial, iclass 18, count 0 2006.239.08:11:01.83#ibcon#enter sib2, iclass 18, count 0 2006.239.08:11:01.83#ibcon#flushed, iclass 18, count 0 2006.239.08:11:01.83#ibcon#about to write, iclass 18, count 0 2006.239.08:11:01.83#ibcon#wrote, iclass 18, count 0 2006.239.08:11:01.83#ibcon#about to read 3, iclass 18, count 0 2006.239.08:11:01.84#ibcon#read 3, iclass 18, count 0 2006.239.08:11:01.84#ibcon#about to read 4, iclass 18, count 0 2006.239.08:11:01.84#ibcon#read 4, iclass 18, count 0 2006.239.08:11:01.84#ibcon#about to read 5, iclass 18, count 0 2006.239.08:11:01.84#ibcon#read 5, iclass 18, count 0 2006.239.08:11:01.84#ibcon#about to read 6, iclass 18, count 0 2006.239.08:11:01.84#ibcon#read 6, iclass 18, count 0 2006.239.08:11:01.84#ibcon#end of sib2, iclass 18, count 0 2006.239.08:11:01.84#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:11:01.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:11:01.84#ibcon#[27=USB\r\n] 2006.239.08:11:01.84#ibcon#*before write, iclass 18, count 0 2006.239.08:11:01.84#ibcon#enter sib2, iclass 18, count 0 2006.239.08:11:01.84#ibcon#flushed, iclass 18, count 0 2006.239.08:11:01.84#ibcon#about to write, iclass 18, count 0 2006.239.08:11:01.84#ibcon#wrote, iclass 18, count 0 2006.239.08:11:01.84#ibcon#about to read 3, iclass 18, count 0 2006.239.08:11:01.87#ibcon#read 3, iclass 18, count 0 2006.239.08:11:01.87#ibcon#about to read 4, iclass 18, count 0 2006.239.08:11:01.87#ibcon#read 4, iclass 18, count 0 2006.239.08:11:01.87#ibcon#about to read 5, iclass 18, count 0 2006.239.08:11:01.87#ibcon#read 5, iclass 18, count 0 2006.239.08:11:01.87#ibcon#about to read 6, iclass 18, count 0 2006.239.08:11:01.87#ibcon#read 6, iclass 18, count 0 2006.239.08:11:01.87#ibcon#end of sib2, iclass 18, count 0 2006.239.08:11:01.87#ibcon#*after write, iclass 18, count 0 2006.239.08:11:01.87#ibcon#*before return 0, iclass 18, count 0 2006.239.08:11:01.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:11:01.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:11:01.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:11:01.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:11:01.87$vc4f8/vblo=5,744.99 2006.239.08:11:01.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.08:11:01.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.08:11:01.88#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:01.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:11:01.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:11:01.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:11:01.88#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:11:01.88#ibcon#first serial, iclass 20, count 0 2006.239.08:11:01.88#ibcon#enter sib2, iclass 20, count 0 2006.239.08:11:01.88#ibcon#flushed, iclass 20, count 0 2006.239.08:11:01.88#ibcon#about to write, iclass 20, count 0 2006.239.08:11:01.88#ibcon#wrote, iclass 20, count 0 2006.239.08:11:01.88#ibcon#about to read 3, iclass 20, count 0 2006.239.08:11:01.89#ibcon#read 3, iclass 20, count 0 2006.239.08:11:01.89#ibcon#about to read 4, iclass 20, count 0 2006.239.08:11:01.89#ibcon#read 4, iclass 20, count 0 2006.239.08:11:01.89#ibcon#about to read 5, iclass 20, count 0 2006.239.08:11:01.89#ibcon#read 5, iclass 20, count 0 2006.239.08:11:01.89#ibcon#about to read 6, iclass 20, count 0 2006.239.08:11:01.89#ibcon#read 6, iclass 20, count 0 2006.239.08:11:01.89#ibcon#end of sib2, iclass 20, count 0 2006.239.08:11:01.89#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:11:01.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:11:01.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:11:01.89#ibcon#*before write, iclass 20, count 0 2006.239.08:11:01.89#ibcon#enter sib2, iclass 20, count 0 2006.239.08:11:01.89#ibcon#flushed, iclass 20, count 0 2006.239.08:11:01.89#ibcon#about to write, iclass 20, count 0 2006.239.08:11:01.89#ibcon#wrote, iclass 20, count 0 2006.239.08:11:01.89#ibcon#about to read 3, iclass 20, count 0 2006.239.08:11:01.93#ibcon#read 3, iclass 20, count 0 2006.239.08:11:01.93#ibcon#about to read 4, iclass 20, count 0 2006.239.08:11:01.93#ibcon#read 4, iclass 20, count 0 2006.239.08:11:01.93#ibcon#about to read 5, iclass 20, count 0 2006.239.08:11:01.93#ibcon#read 5, iclass 20, count 0 2006.239.08:11:01.93#ibcon#about to read 6, iclass 20, count 0 2006.239.08:11:01.93#ibcon#read 6, iclass 20, count 0 2006.239.08:11:01.93#ibcon#end of sib2, iclass 20, count 0 2006.239.08:11:01.93#ibcon#*after write, iclass 20, count 0 2006.239.08:11:01.93#ibcon#*before return 0, iclass 20, count 0 2006.239.08:11:01.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:11:01.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:11:01.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:11:01.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:11:01.93$vc4f8/vb=5,4 2006.239.08:11:01.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.08:11:01.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.08:11:01.94#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:01.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:11:01.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:11:01.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:11:01.98#ibcon#enter wrdev, iclass 22, count 2 2006.239.08:11:01.98#ibcon#first serial, iclass 22, count 2 2006.239.08:11:01.98#ibcon#enter sib2, iclass 22, count 2 2006.239.08:11:01.98#ibcon#flushed, iclass 22, count 2 2006.239.08:11:01.98#ibcon#about to write, iclass 22, count 2 2006.239.08:11:01.98#ibcon#wrote, iclass 22, count 2 2006.239.08:11:01.98#ibcon#about to read 3, iclass 22, count 2 2006.239.08:11:02.00#ibcon#read 3, iclass 22, count 2 2006.239.08:11:02.00#ibcon#about to read 4, iclass 22, count 2 2006.239.08:11:02.00#ibcon#read 4, iclass 22, count 2 2006.239.08:11:02.00#ibcon#about to read 5, iclass 22, count 2 2006.239.08:11:02.00#ibcon#read 5, iclass 22, count 2 2006.239.08:11:02.00#ibcon#about to read 6, iclass 22, count 2 2006.239.08:11:02.00#ibcon#read 6, iclass 22, count 2 2006.239.08:11:02.00#ibcon#end of sib2, iclass 22, count 2 2006.239.08:11:02.00#ibcon#*mode == 0, iclass 22, count 2 2006.239.08:11:02.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.08:11:02.00#ibcon#[27=AT05-04\r\n] 2006.239.08:11:02.00#ibcon#*before write, iclass 22, count 2 2006.239.08:11:02.00#ibcon#enter sib2, iclass 22, count 2 2006.239.08:11:02.00#ibcon#flushed, iclass 22, count 2 2006.239.08:11:02.00#ibcon#about to write, iclass 22, count 2 2006.239.08:11:02.00#ibcon#wrote, iclass 22, count 2 2006.239.08:11:02.00#ibcon#about to read 3, iclass 22, count 2 2006.239.08:11:02.03#ibcon#read 3, iclass 22, count 2 2006.239.08:11:02.03#ibcon#about to read 4, iclass 22, count 2 2006.239.08:11:02.03#ibcon#read 4, iclass 22, count 2 2006.239.08:11:02.03#ibcon#about to read 5, iclass 22, count 2 2006.239.08:11:02.03#ibcon#read 5, iclass 22, count 2 2006.239.08:11:02.03#ibcon#about to read 6, iclass 22, count 2 2006.239.08:11:02.03#ibcon#read 6, iclass 22, count 2 2006.239.08:11:02.03#ibcon#end of sib2, iclass 22, count 2 2006.239.08:11:02.03#ibcon#*after write, iclass 22, count 2 2006.239.08:11:02.03#ibcon#*before return 0, iclass 22, count 2 2006.239.08:11:02.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:11:02.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:11:02.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.08:11:02.03#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:02.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:11:02.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:11:02.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:11:02.15#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:11:02.15#ibcon#first serial, iclass 22, count 0 2006.239.08:11:02.15#ibcon#enter sib2, iclass 22, count 0 2006.239.08:11:02.15#ibcon#flushed, iclass 22, count 0 2006.239.08:11:02.15#ibcon#about to write, iclass 22, count 0 2006.239.08:11:02.15#ibcon#wrote, iclass 22, count 0 2006.239.08:11:02.15#ibcon#about to read 3, iclass 22, count 0 2006.239.08:11:02.17#ibcon#read 3, iclass 22, count 0 2006.239.08:11:02.17#ibcon#about to read 4, iclass 22, count 0 2006.239.08:11:02.17#ibcon#read 4, iclass 22, count 0 2006.239.08:11:02.17#ibcon#about to read 5, iclass 22, count 0 2006.239.08:11:02.17#ibcon#read 5, iclass 22, count 0 2006.239.08:11:02.17#ibcon#about to read 6, iclass 22, count 0 2006.239.08:11:02.17#ibcon#read 6, iclass 22, count 0 2006.239.08:11:02.17#ibcon#end of sib2, iclass 22, count 0 2006.239.08:11:02.17#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:11:02.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:11:02.17#ibcon#[27=USB\r\n] 2006.239.08:11:02.17#ibcon#*before write, iclass 22, count 0 2006.239.08:11:02.17#ibcon#enter sib2, iclass 22, count 0 2006.239.08:11:02.17#ibcon#flushed, iclass 22, count 0 2006.239.08:11:02.17#ibcon#about to write, iclass 22, count 0 2006.239.08:11:02.17#ibcon#wrote, iclass 22, count 0 2006.239.08:11:02.17#ibcon#about to read 3, iclass 22, count 0 2006.239.08:11:02.20#ibcon#read 3, iclass 22, count 0 2006.239.08:11:02.20#ibcon#about to read 4, iclass 22, count 0 2006.239.08:11:02.20#ibcon#read 4, iclass 22, count 0 2006.239.08:11:02.20#ibcon#about to read 5, iclass 22, count 0 2006.239.08:11:02.20#ibcon#read 5, iclass 22, count 0 2006.239.08:11:02.20#ibcon#about to read 6, iclass 22, count 0 2006.239.08:11:02.20#ibcon#read 6, iclass 22, count 0 2006.239.08:11:02.20#ibcon#end of sib2, iclass 22, count 0 2006.239.08:11:02.20#ibcon#*after write, iclass 22, count 0 2006.239.08:11:02.20#ibcon#*before return 0, iclass 22, count 0 2006.239.08:11:02.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:11:02.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:11:02.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:11:02.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:11:02.20$vc4f8/vblo=6,752.99 2006.239.08:11:02.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.08:11:02.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.08:11:02.21#ibcon#ireg 17 cls_cnt 0 2006.239.08:11:02.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:11:02.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:11:02.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:11:02.21#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:11:02.21#ibcon#first serial, iclass 24, count 0 2006.239.08:11:02.21#ibcon#enter sib2, iclass 24, count 0 2006.239.08:11:02.21#ibcon#flushed, iclass 24, count 0 2006.239.08:11:02.21#ibcon#about to write, iclass 24, count 0 2006.239.08:11:02.21#ibcon#wrote, iclass 24, count 0 2006.239.08:11:02.21#ibcon#about to read 3, iclass 24, count 0 2006.239.08:11:02.22#ibcon#read 3, iclass 24, count 0 2006.239.08:11:02.22#ibcon#about to read 4, iclass 24, count 0 2006.239.08:11:02.22#ibcon#read 4, iclass 24, count 0 2006.239.08:11:02.22#ibcon#about to read 5, iclass 24, count 0 2006.239.08:11:02.22#ibcon#read 5, iclass 24, count 0 2006.239.08:11:02.22#ibcon#about to read 6, iclass 24, count 0 2006.239.08:11:02.22#ibcon#read 6, iclass 24, count 0 2006.239.08:11:02.22#ibcon#end of sib2, iclass 24, count 0 2006.239.08:11:02.22#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:11:02.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:11:02.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:11:02.22#ibcon#*before write, iclass 24, count 0 2006.239.08:11:02.22#ibcon#enter sib2, iclass 24, count 0 2006.239.08:11:02.22#ibcon#flushed, iclass 24, count 0 2006.239.08:11:02.22#ibcon#about to write, iclass 24, count 0 2006.239.08:11:02.22#ibcon#wrote, iclass 24, count 0 2006.239.08:11:02.22#ibcon#about to read 3, iclass 24, count 0 2006.239.08:11:02.26#ibcon#read 3, iclass 24, count 0 2006.239.08:11:02.26#ibcon#about to read 4, iclass 24, count 0 2006.239.08:11:02.26#ibcon#read 4, iclass 24, count 0 2006.239.08:11:02.26#ibcon#about to read 5, iclass 24, count 0 2006.239.08:11:02.26#ibcon#read 5, iclass 24, count 0 2006.239.08:11:02.26#ibcon#about to read 6, iclass 24, count 0 2006.239.08:11:02.26#ibcon#read 6, iclass 24, count 0 2006.239.08:11:02.26#ibcon#end of sib2, iclass 24, count 0 2006.239.08:11:02.26#ibcon#*after write, iclass 24, count 0 2006.239.08:11:02.26#ibcon#*before return 0, iclass 24, count 0 2006.239.08:11:02.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:11:02.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:11:02.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:11:02.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:11:02.27$vc4f8/vb=6,4 2006.239.08:11:02.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.08:11:02.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.08:11:02.27#ibcon#ireg 11 cls_cnt 2 2006.239.08:11:02.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:11:02.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:11:02.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:11:02.31#ibcon#enter wrdev, iclass 26, count 2 2006.239.08:11:02.31#ibcon#first serial, iclass 26, count 2 2006.239.08:11:02.31#ibcon#enter sib2, iclass 26, count 2 2006.239.08:11:02.31#ibcon#flushed, iclass 26, count 2 2006.239.08:11:02.31#ibcon#about to write, iclass 26, count 2 2006.239.08:11:02.31#ibcon#wrote, iclass 26, count 2 2006.239.08:11:02.31#ibcon#about to read 3, iclass 26, count 2 2006.239.08:11:02.33#ibcon#read 3, iclass 26, count 2 2006.239.08:11:02.33#ibcon#about to read 4, iclass 26, count 2 2006.239.08:11:02.33#ibcon#read 4, iclass 26, count 2 2006.239.08:11:02.33#ibcon#about to read 5, iclass 26, count 2 2006.239.08:11:02.33#ibcon#read 5, iclass 26, count 2 2006.239.08:11:02.33#ibcon#about to read 6, iclass 26, count 2 2006.239.08:11:02.33#ibcon#read 6, iclass 26, count 2 2006.239.08:11:02.33#ibcon#end of sib2, iclass 26, count 2 2006.239.08:11:02.33#ibcon#*mode == 0, iclass 26, count 2 2006.239.08:11:02.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.08:11:02.33#ibcon#[27=AT06-04\r\n] 2006.239.08:11:02.33#ibcon#*before write, iclass 26, count 2 2006.239.08:11:02.33#ibcon#enter sib2, iclass 26, count 2 2006.239.08:11:02.33#ibcon#flushed, iclass 26, count 2 2006.239.08:11:02.33#ibcon#about to write, iclass 26, count 2 2006.239.08:11:02.33#ibcon#wrote, iclass 26, count 2 2006.239.08:11:02.33#ibcon#about to read 3, iclass 26, count 2 2006.239.08:11:02.36#ibcon#read 3, iclass 26, count 2 2006.239.08:11:02.36#ibcon#about to read 4, iclass 26, count 2 2006.239.08:11:02.36#ibcon#read 4, iclass 26, count 2 2006.239.08:11:02.36#ibcon#about to read 5, iclass 26, count 2 2006.239.08:11:02.36#ibcon#read 5, iclass 26, count 2 2006.239.08:11:02.36#ibcon#about to read 6, iclass 26, count 2 2006.239.08:11:02.36#ibcon#read 6, iclass 26, count 2 2006.239.08:11:02.36#ibcon#end of sib2, iclass 26, count 2 2006.239.08:11:02.36#ibcon#*after write, iclass 26, count 2 2006.239.08:11:02.36#ibcon#*before return 0, iclass 26, count 2 2006.239.08:11:02.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:11:02.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:11:02.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.08:11:02.36#ibcon#ireg 7 cls_cnt 0 2006.239.08:11:02.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:11:02.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:11:02.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:11:02.48#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:11:02.48#ibcon#first serial, iclass 26, count 0 2006.239.08:11:02.48#ibcon#enter sib2, iclass 26, count 0 2006.239.08:11:02.48#ibcon#flushed, iclass 26, count 0 2006.239.08:11:02.48#ibcon#about to write, iclass 26, count 0 2006.239.08:11:02.48#ibcon#wrote, iclass 26, count 0 2006.239.08:11:02.48#ibcon#about to read 3, iclass 26, count 0 2006.239.08:11:02.50#ibcon#read 3, iclass 26, count 0 2006.239.08:11:02.50#ibcon#about to read 4, iclass 26, count 0 2006.239.08:11:02.50#ibcon#read 4, iclass 26, count 0 2006.239.08:11:02.50#ibcon#about to read 5, iclass 26, count 0 2006.239.08:11:02.50#ibcon#read 5, iclass 26, count 0 2006.239.08:11:02.50#ibcon#about to read 6, iclass 26, count 0 2006.239.08:11:02.50#ibcon#read 6, iclass 26, count 0 2006.239.08:11:02.50#ibcon#end of sib2, iclass 26, count 0 2006.239.08:11:02.50#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:11:02.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:11:02.50#ibcon#[27=USB\r\n] 2006.239.08:11:02.50#ibcon#*before write, iclass 26, count 0 2006.239.08:11:02.50#ibcon#enter sib2, iclass 26, count 0 2006.239.08:11:02.50#ibcon#flushed, iclass 26, count 0 2006.239.08:11:02.50#ibcon#about to write, iclass 26, count 0 2006.239.08:11:02.50#ibcon#wrote, iclass 26, count 0 2006.239.08:11:02.50#ibcon#about to read 3, iclass 26, count 0 2006.239.08:11:02.54#ibcon#read 3, iclass 26, count 0 2006.239.08:11:02.54#ibcon#about to read 4, iclass 26, count 0 2006.239.08:11:02.54#ibcon#read 4, iclass 26, count 0 2006.239.08:11:02.54#ibcon#about to read 5, iclass 26, count 0 2006.239.08:11:02.54#ibcon#read 5, iclass 26, count 0 2006.239.08:11:02.54#ibcon#about to read 6, iclass 26, count 0 2006.239.08:11:02.54#ibcon#read 6, iclass 26, count 0 2006.239.08:11:02.54#ibcon#end of sib2, iclass 26, count 0 2006.239.08:11:02.54#ibcon#*after write, iclass 26, count 0 2006.239.08:11:02.54#ibcon#*before return 0, iclass 26, count 0 2006.239.08:11:02.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:11:02.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:11:02.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:11:02.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:11:02.54$vc4f8/vabw=wide 2006.239.08:11:02.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:11:02.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:11:02.54#ibcon#ireg 8 cls_cnt 0 2006.239.08:11:02.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:11:02.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:11:02.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:11:02.54#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:11:02.54#ibcon#first serial, iclass 28, count 0 2006.239.08:11:02.54#ibcon#enter sib2, iclass 28, count 0 2006.239.08:11:02.54#ibcon#flushed, iclass 28, count 0 2006.239.08:11:02.54#ibcon#about to write, iclass 28, count 0 2006.239.08:11:02.54#ibcon#wrote, iclass 28, count 0 2006.239.08:11:02.54#ibcon#about to read 3, iclass 28, count 0 2006.239.08:11:02.55#ibcon#read 3, iclass 28, count 0 2006.239.08:11:02.55#ibcon#about to read 4, iclass 28, count 0 2006.239.08:11:02.55#ibcon#read 4, iclass 28, count 0 2006.239.08:11:02.55#ibcon#about to read 5, iclass 28, count 0 2006.239.08:11:02.55#ibcon#read 5, iclass 28, count 0 2006.239.08:11:02.55#ibcon#about to read 6, iclass 28, count 0 2006.239.08:11:02.55#ibcon#read 6, iclass 28, count 0 2006.239.08:11:02.55#ibcon#end of sib2, iclass 28, count 0 2006.239.08:11:02.55#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:11:02.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:11:02.55#ibcon#[25=BW32\r\n] 2006.239.08:11:02.55#ibcon#*before write, iclass 28, count 0 2006.239.08:11:02.55#ibcon#enter sib2, iclass 28, count 0 2006.239.08:11:02.55#ibcon#flushed, iclass 28, count 0 2006.239.08:11:02.55#ibcon#about to write, iclass 28, count 0 2006.239.08:11:02.55#ibcon#wrote, iclass 28, count 0 2006.239.08:11:02.55#ibcon#about to read 3, iclass 28, count 0 2006.239.08:11:02.58#ibcon#read 3, iclass 28, count 0 2006.239.08:11:02.58#ibcon#about to read 4, iclass 28, count 0 2006.239.08:11:02.58#ibcon#read 4, iclass 28, count 0 2006.239.08:11:02.58#ibcon#about to read 5, iclass 28, count 0 2006.239.08:11:02.58#ibcon#read 5, iclass 28, count 0 2006.239.08:11:02.58#ibcon#about to read 6, iclass 28, count 0 2006.239.08:11:02.58#ibcon#read 6, iclass 28, count 0 2006.239.08:11:02.58#ibcon#end of sib2, iclass 28, count 0 2006.239.08:11:02.58#ibcon#*after write, iclass 28, count 0 2006.239.08:11:02.58#ibcon#*before return 0, iclass 28, count 0 2006.239.08:11:02.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:11:02.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:11:02.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:11:02.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:11:02.59$vc4f8/vbbw=wide 2006.239.08:11:02.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.08:11:02.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.08:11:02.59#ibcon#ireg 8 cls_cnt 0 2006.239.08:11:02.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:11:02.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:11:02.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:11:02.65#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:11:02.65#ibcon#first serial, iclass 30, count 0 2006.239.08:11:02.65#ibcon#enter sib2, iclass 30, count 0 2006.239.08:11:02.65#ibcon#flushed, iclass 30, count 0 2006.239.08:11:02.65#ibcon#about to write, iclass 30, count 0 2006.239.08:11:02.65#ibcon#wrote, iclass 30, count 0 2006.239.08:11:02.65#ibcon#about to read 3, iclass 30, count 0 2006.239.08:11:02.67#ibcon#read 3, iclass 30, count 0 2006.239.08:11:02.67#ibcon#about to read 4, iclass 30, count 0 2006.239.08:11:02.67#ibcon#read 4, iclass 30, count 0 2006.239.08:11:02.67#ibcon#about to read 5, iclass 30, count 0 2006.239.08:11:02.67#ibcon#read 5, iclass 30, count 0 2006.239.08:11:02.67#ibcon#about to read 6, iclass 30, count 0 2006.239.08:11:02.67#ibcon#read 6, iclass 30, count 0 2006.239.08:11:02.67#ibcon#end of sib2, iclass 30, count 0 2006.239.08:11:02.67#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:11:02.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:11:02.67#ibcon#[27=BW32\r\n] 2006.239.08:11:02.67#ibcon#*before write, iclass 30, count 0 2006.239.08:11:02.67#ibcon#enter sib2, iclass 30, count 0 2006.239.08:11:02.67#ibcon#flushed, iclass 30, count 0 2006.239.08:11:02.67#ibcon#about to write, iclass 30, count 0 2006.239.08:11:02.67#ibcon#wrote, iclass 30, count 0 2006.239.08:11:02.67#ibcon#about to read 3, iclass 30, count 0 2006.239.08:11:02.70#ibcon#read 3, iclass 30, count 0 2006.239.08:11:02.70#ibcon#about to read 4, iclass 30, count 0 2006.239.08:11:02.70#ibcon#read 4, iclass 30, count 0 2006.239.08:11:02.70#ibcon#about to read 5, iclass 30, count 0 2006.239.08:11:02.70#ibcon#read 5, iclass 30, count 0 2006.239.08:11:02.70#ibcon#about to read 6, iclass 30, count 0 2006.239.08:11:02.70#ibcon#read 6, iclass 30, count 0 2006.239.08:11:02.70#ibcon#end of sib2, iclass 30, count 0 2006.239.08:11:02.70#ibcon#*after write, iclass 30, count 0 2006.239.08:11:02.70#ibcon#*before return 0, iclass 30, count 0 2006.239.08:11:02.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:11:02.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:11:02.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:11:02.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:11:02.71$4f8m12a/ifd4f 2006.239.08:11:02.71$ifd4f/lo= 2006.239.08:11:02.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:11:02.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:11:02.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:11:02.71$ifd4f/patch= 2006.239.08:11:02.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:11:02.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:11:02.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:11:02.71$4f8m12a/"form=m,16.000,1:2 2006.239.08:11:02.71$4f8m12a/"tpicd 2006.239.08:11:02.71$4f8m12a/echo=off 2006.239.08:11:02.71$4f8m12a/xlog=off 2006.239.08:11:02.71:!2006.239.08:11:30 2006.239.08:11:10.14#trakl#Source acquired 2006.239.08:11:12.15#flagr#flagr/antenna,acquired 2006.239.08:11:30.02:preob 2006.239.08:11:31.15/onsource/TRACKING 2006.239.08:11:31.15:!2006.239.08:11:40 2006.239.08:11:40.01:data_valid=on 2006.239.08:11:40.02:midob 2006.239.08:11:41.14/onsource/TRACKING 2006.239.08:11:41.15/wx/25.08,1011.5,80 2006.239.08:11:41.28/cable/+6.4140E-03 2006.239.08:11:42.37/va/01,08,usb,yes,31,32 2006.239.08:11:42.37/va/02,07,usb,yes,31,32 2006.239.08:11:42.37/va/03,07,usb,yes,29,29 2006.239.08:11:42.37/va/04,07,usb,yes,32,35 2006.239.08:11:42.37/va/05,08,usb,yes,29,30 2006.239.08:11:42.37/va/06,07,usb,yes,31,31 2006.239.08:11:42.37/va/07,07,usb,yes,31,31 2006.239.08:11:42.37/va/08,07,usb,yes,34,33 2006.239.08:11:42.60/valo/01,532.99,yes,locked 2006.239.08:11:42.60/valo/02,572.99,yes,locked 2006.239.08:11:42.60/valo/03,672.99,yes,locked 2006.239.08:11:42.60/valo/04,832.99,yes,locked 2006.239.08:11:42.60/valo/05,652.99,yes,locked 2006.239.08:11:42.60/valo/06,772.99,yes,locked 2006.239.08:11:42.60/valo/07,832.99,yes,locked 2006.239.08:11:42.60/valo/08,852.99,yes,locked 2006.239.08:11:43.69/vb/01,04,usb,yes,30,29 2006.239.08:11:43.69/vb/02,04,usb,yes,32,33 2006.239.08:11:43.69/vb/03,04,usb,yes,28,32 2006.239.08:11:43.69/vb/04,04,usb,yes,29,29 2006.239.08:11:43.69/vb/05,04,usb,yes,28,32 2006.239.08:11:43.69/vb/06,04,usb,yes,28,31 2006.239.08:11:43.69/vb/07,04,usb,yes,31,31 2006.239.08:11:43.69/vb/08,04,usb,yes,28,32 2006.239.08:11:43.92/vblo/01,632.99,yes,locked 2006.239.08:11:43.92/vblo/02,640.99,yes,locked 2006.239.08:11:43.92/vblo/03,656.99,yes,locked 2006.239.08:11:43.92/vblo/04,712.99,yes,locked 2006.239.08:11:43.92/vblo/05,744.99,yes,locked 2006.239.08:11:43.92/vblo/06,752.99,yes,locked 2006.239.08:11:43.92/vblo/07,734.99,yes,locked 2006.239.08:11:43.92/vblo/08,744.99,yes,locked 2006.239.08:11:44.07/vabw/8 2006.239.08:11:44.22/vbbw/8 2006.239.08:11:44.31/xfe/off,on,13.0 2006.239.08:11:44.68/ifatt/23,28,28,28 2006.239.08:11:45.07/fmout-gps/S +4.40E-07 2006.239.08:11:45.12:!2006.239.08:12:40 2006.239.08:12:40.01:data_valid=off 2006.239.08:12:40.02:postob 2006.239.08:12:40.13/cable/+6.4157E-03 2006.239.08:12:40.14/wx/25.07,1011.5,80 2006.239.08:12:40.19/fmout-gps/S +4.40E-07 2006.239.08:12:40.20:scan_name=239-0813,k06239,60 2006.239.08:12:40.20:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.239.08:12:41.14#flagr#flagr/antenna,new-source 2006.239.08:12:41.15:checkk5 2006.239.08:12:41.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:12:41.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:12:42.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:12:42.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:12:43.03/chk_obsdata//k5ts1/T2390811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:12:43.40/chk_obsdata//k5ts2/T2390811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:12:43.78/chk_obsdata//k5ts3/T2390811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:12:44.15/chk_obsdata//k5ts4/T2390811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:12:44.85/k5log//k5ts1_log_newline 2006.239.08:12:45.55/k5log//k5ts2_log_newline 2006.239.08:12:46.24/k5log//k5ts3_log_newline 2006.239.08:12:46.93/k5log//k5ts4_log_newline 2006.239.08:12:46.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:12:46.96:4f8m12a=2 2006.239.08:12:46.96$4f8m12a/echo=on 2006.239.08:12:46.96$4f8m12a/pcalon 2006.239.08:12:46.96$pcalon/"no phase cal control is implemented here 2006.239.08:12:46.96$4f8m12a/"tpicd=stop 2006.239.08:12:46.96$4f8m12a/vc4f8 2006.239.08:12:46.96$vc4f8/valo=1,532.99 2006.239.08:12:46.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.08:12:46.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.08:12:46.96#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:46.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:46.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:46.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:46.96#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:12:46.96#ibcon#first serial, iclass 3, count 0 2006.239.08:12:46.96#ibcon#enter sib2, iclass 3, count 0 2006.239.08:12:46.96#ibcon#flushed, iclass 3, count 0 2006.239.08:12:46.96#ibcon#about to write, iclass 3, count 0 2006.239.08:12:46.96#ibcon#wrote, iclass 3, count 0 2006.239.08:12:46.96#ibcon#about to read 3, iclass 3, count 0 2006.239.08:12:46.97#ibcon#read 3, iclass 3, count 0 2006.239.08:12:46.97#ibcon#about to read 4, iclass 3, count 0 2006.239.08:12:46.97#ibcon#read 4, iclass 3, count 0 2006.239.08:12:46.97#ibcon#about to read 5, iclass 3, count 0 2006.239.08:12:46.97#ibcon#read 5, iclass 3, count 0 2006.239.08:12:46.97#ibcon#about to read 6, iclass 3, count 0 2006.239.08:12:46.97#ibcon#read 6, iclass 3, count 0 2006.239.08:12:46.97#ibcon#end of sib2, iclass 3, count 0 2006.239.08:12:46.97#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:12:46.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:12:46.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:12:46.97#ibcon#*before write, iclass 3, count 0 2006.239.08:12:46.97#ibcon#enter sib2, iclass 3, count 0 2006.239.08:12:46.97#ibcon#flushed, iclass 3, count 0 2006.239.08:12:46.97#ibcon#about to write, iclass 3, count 0 2006.239.08:12:46.97#ibcon#wrote, iclass 3, count 0 2006.239.08:12:46.97#ibcon#about to read 3, iclass 3, count 0 2006.239.08:12:47.02#ibcon#read 3, iclass 3, count 0 2006.239.08:12:47.02#ibcon#about to read 4, iclass 3, count 0 2006.239.08:12:47.02#ibcon#read 4, iclass 3, count 0 2006.239.08:12:47.02#ibcon#about to read 5, iclass 3, count 0 2006.239.08:12:47.02#ibcon#read 5, iclass 3, count 0 2006.239.08:12:47.02#ibcon#about to read 6, iclass 3, count 0 2006.239.08:12:47.02#ibcon#read 6, iclass 3, count 0 2006.239.08:12:47.02#ibcon#end of sib2, iclass 3, count 0 2006.239.08:12:47.02#ibcon#*after write, iclass 3, count 0 2006.239.08:12:47.02#ibcon#*before return 0, iclass 3, count 0 2006.239.08:12:47.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:47.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:47.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:12:47.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:12:47.02$vc4f8/va=1,8 2006.239.08:12:47.02#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.08:12:47.02#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.08:12:47.02#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:47.02#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:47.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:47.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:47.02#ibcon#enter wrdev, iclass 5, count 2 2006.239.08:12:47.02#ibcon#first serial, iclass 5, count 2 2006.239.08:12:47.02#ibcon#enter sib2, iclass 5, count 2 2006.239.08:12:47.02#ibcon#flushed, iclass 5, count 2 2006.239.08:12:47.02#ibcon#about to write, iclass 5, count 2 2006.239.08:12:47.02#ibcon#wrote, iclass 5, count 2 2006.239.08:12:47.02#ibcon#about to read 3, iclass 5, count 2 2006.239.08:12:47.04#ibcon#read 3, iclass 5, count 2 2006.239.08:12:47.04#ibcon#about to read 4, iclass 5, count 2 2006.239.08:12:47.04#ibcon#read 4, iclass 5, count 2 2006.239.08:12:47.04#ibcon#about to read 5, iclass 5, count 2 2006.239.08:12:47.04#ibcon#read 5, iclass 5, count 2 2006.239.08:12:47.04#ibcon#about to read 6, iclass 5, count 2 2006.239.08:12:47.04#ibcon#read 6, iclass 5, count 2 2006.239.08:12:47.04#ibcon#end of sib2, iclass 5, count 2 2006.239.08:12:47.04#ibcon#*mode == 0, iclass 5, count 2 2006.239.08:12:47.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.08:12:47.04#ibcon#[25=AT01-08\r\n] 2006.239.08:12:47.04#ibcon#*before write, iclass 5, count 2 2006.239.08:12:47.04#ibcon#enter sib2, iclass 5, count 2 2006.239.08:12:47.04#ibcon#flushed, iclass 5, count 2 2006.239.08:12:47.04#ibcon#about to write, iclass 5, count 2 2006.239.08:12:47.04#ibcon#wrote, iclass 5, count 2 2006.239.08:12:47.04#ibcon#about to read 3, iclass 5, count 2 2006.239.08:12:47.07#ibcon#read 3, iclass 5, count 2 2006.239.08:12:47.07#ibcon#about to read 4, iclass 5, count 2 2006.239.08:12:47.07#ibcon#read 4, iclass 5, count 2 2006.239.08:12:47.07#ibcon#about to read 5, iclass 5, count 2 2006.239.08:12:47.07#ibcon#read 5, iclass 5, count 2 2006.239.08:12:47.07#ibcon#about to read 6, iclass 5, count 2 2006.239.08:12:47.07#ibcon#read 6, iclass 5, count 2 2006.239.08:12:47.07#ibcon#end of sib2, iclass 5, count 2 2006.239.08:12:47.07#ibcon#*after write, iclass 5, count 2 2006.239.08:12:47.07#ibcon#*before return 0, iclass 5, count 2 2006.239.08:12:47.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:47.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:47.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.08:12:47.07#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:47.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:47.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:47.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:47.19#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:12:47.19#ibcon#first serial, iclass 5, count 0 2006.239.08:12:47.19#ibcon#enter sib2, iclass 5, count 0 2006.239.08:12:47.19#ibcon#flushed, iclass 5, count 0 2006.239.08:12:47.19#ibcon#about to write, iclass 5, count 0 2006.239.08:12:47.19#ibcon#wrote, iclass 5, count 0 2006.239.08:12:47.19#ibcon#about to read 3, iclass 5, count 0 2006.239.08:12:47.21#ibcon#read 3, iclass 5, count 0 2006.239.08:12:47.21#ibcon#about to read 4, iclass 5, count 0 2006.239.08:12:47.21#ibcon#read 4, iclass 5, count 0 2006.239.08:12:47.21#ibcon#about to read 5, iclass 5, count 0 2006.239.08:12:47.21#ibcon#read 5, iclass 5, count 0 2006.239.08:12:47.21#ibcon#about to read 6, iclass 5, count 0 2006.239.08:12:47.21#ibcon#read 6, iclass 5, count 0 2006.239.08:12:47.21#ibcon#end of sib2, iclass 5, count 0 2006.239.08:12:47.21#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:12:47.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:12:47.21#ibcon#[25=USB\r\n] 2006.239.08:12:47.21#ibcon#*before write, iclass 5, count 0 2006.239.08:12:47.21#ibcon#enter sib2, iclass 5, count 0 2006.239.08:12:47.21#ibcon#flushed, iclass 5, count 0 2006.239.08:12:47.21#ibcon#about to write, iclass 5, count 0 2006.239.08:12:47.21#ibcon#wrote, iclass 5, count 0 2006.239.08:12:47.21#ibcon#about to read 3, iclass 5, count 0 2006.239.08:12:47.24#ibcon#read 3, iclass 5, count 0 2006.239.08:12:47.24#ibcon#about to read 4, iclass 5, count 0 2006.239.08:12:47.24#ibcon#read 4, iclass 5, count 0 2006.239.08:12:47.24#ibcon#about to read 5, iclass 5, count 0 2006.239.08:12:47.24#ibcon#read 5, iclass 5, count 0 2006.239.08:12:47.24#ibcon#about to read 6, iclass 5, count 0 2006.239.08:12:47.24#ibcon#read 6, iclass 5, count 0 2006.239.08:12:47.24#ibcon#end of sib2, iclass 5, count 0 2006.239.08:12:47.24#ibcon#*after write, iclass 5, count 0 2006.239.08:12:47.24#ibcon#*before return 0, iclass 5, count 0 2006.239.08:12:47.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:47.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:47.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:12:47.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:12:47.24$vc4f8/valo=2,572.99 2006.239.08:12:47.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.08:12:47.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.08:12:47.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:47.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:47.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:47.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:47.24#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:12:47.24#ibcon#first serial, iclass 7, count 0 2006.239.08:12:47.24#ibcon#enter sib2, iclass 7, count 0 2006.239.08:12:47.24#ibcon#flushed, iclass 7, count 0 2006.239.08:12:47.24#ibcon#about to write, iclass 7, count 0 2006.239.08:12:47.24#ibcon#wrote, iclass 7, count 0 2006.239.08:12:47.24#ibcon#about to read 3, iclass 7, count 0 2006.239.08:12:47.26#ibcon#read 3, iclass 7, count 0 2006.239.08:12:47.26#ibcon#about to read 4, iclass 7, count 0 2006.239.08:12:47.26#ibcon#read 4, iclass 7, count 0 2006.239.08:12:47.26#ibcon#about to read 5, iclass 7, count 0 2006.239.08:12:47.26#ibcon#read 5, iclass 7, count 0 2006.239.08:12:47.26#ibcon#about to read 6, iclass 7, count 0 2006.239.08:12:47.26#ibcon#read 6, iclass 7, count 0 2006.239.08:12:47.26#ibcon#end of sib2, iclass 7, count 0 2006.239.08:12:47.26#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:12:47.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:12:47.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:12:47.26#ibcon#*before write, iclass 7, count 0 2006.239.08:12:47.26#ibcon#enter sib2, iclass 7, count 0 2006.239.08:12:47.26#ibcon#flushed, iclass 7, count 0 2006.239.08:12:47.26#ibcon#about to write, iclass 7, count 0 2006.239.08:12:47.26#ibcon#wrote, iclass 7, count 0 2006.239.08:12:47.26#ibcon#about to read 3, iclass 7, count 0 2006.239.08:12:47.31#ibcon#read 3, iclass 7, count 0 2006.239.08:12:47.31#ibcon#about to read 4, iclass 7, count 0 2006.239.08:12:47.31#ibcon#read 4, iclass 7, count 0 2006.239.08:12:47.31#ibcon#about to read 5, iclass 7, count 0 2006.239.08:12:47.31#ibcon#read 5, iclass 7, count 0 2006.239.08:12:47.31#ibcon#about to read 6, iclass 7, count 0 2006.239.08:12:47.31#ibcon#read 6, iclass 7, count 0 2006.239.08:12:47.31#ibcon#end of sib2, iclass 7, count 0 2006.239.08:12:47.31#ibcon#*after write, iclass 7, count 0 2006.239.08:12:47.31#ibcon#*before return 0, iclass 7, count 0 2006.239.08:12:47.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:47.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:47.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:12:47.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:12:47.31$vc4f8/va=2,7 2006.239.08:12:47.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.08:12:47.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.08:12:47.31#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:47.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:47.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:47.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:47.35#ibcon#enter wrdev, iclass 11, count 2 2006.239.08:12:47.35#ibcon#first serial, iclass 11, count 2 2006.239.08:12:47.35#ibcon#enter sib2, iclass 11, count 2 2006.239.08:12:47.35#ibcon#flushed, iclass 11, count 2 2006.239.08:12:47.35#ibcon#about to write, iclass 11, count 2 2006.239.08:12:47.35#ibcon#wrote, iclass 11, count 2 2006.239.08:12:47.35#ibcon#about to read 3, iclass 11, count 2 2006.239.08:12:47.38#ibcon#read 3, iclass 11, count 2 2006.239.08:12:47.38#ibcon#about to read 4, iclass 11, count 2 2006.239.08:12:47.38#ibcon#read 4, iclass 11, count 2 2006.239.08:12:47.38#ibcon#about to read 5, iclass 11, count 2 2006.239.08:12:47.38#ibcon#read 5, iclass 11, count 2 2006.239.08:12:47.38#ibcon#about to read 6, iclass 11, count 2 2006.239.08:12:47.38#ibcon#read 6, iclass 11, count 2 2006.239.08:12:47.38#ibcon#end of sib2, iclass 11, count 2 2006.239.08:12:47.38#ibcon#*mode == 0, iclass 11, count 2 2006.239.08:12:47.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.08:12:47.38#ibcon#[25=AT02-07\r\n] 2006.239.08:12:47.38#ibcon#*before write, iclass 11, count 2 2006.239.08:12:47.38#ibcon#enter sib2, iclass 11, count 2 2006.239.08:12:47.38#ibcon#flushed, iclass 11, count 2 2006.239.08:12:47.38#ibcon#about to write, iclass 11, count 2 2006.239.08:12:47.38#ibcon#wrote, iclass 11, count 2 2006.239.08:12:47.38#ibcon#about to read 3, iclass 11, count 2 2006.239.08:12:47.41#ibcon#read 3, iclass 11, count 2 2006.239.08:12:47.41#ibcon#about to read 4, iclass 11, count 2 2006.239.08:12:47.41#ibcon#read 4, iclass 11, count 2 2006.239.08:12:47.41#ibcon#about to read 5, iclass 11, count 2 2006.239.08:12:47.41#ibcon#read 5, iclass 11, count 2 2006.239.08:12:47.41#ibcon#about to read 6, iclass 11, count 2 2006.239.08:12:47.41#ibcon#read 6, iclass 11, count 2 2006.239.08:12:47.41#ibcon#end of sib2, iclass 11, count 2 2006.239.08:12:47.41#ibcon#*after write, iclass 11, count 2 2006.239.08:12:47.41#ibcon#*before return 0, iclass 11, count 2 2006.239.08:12:47.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:47.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:47.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.08:12:47.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:47.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:47.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:47.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:47.53#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:12:47.53#ibcon#first serial, iclass 11, count 0 2006.239.08:12:47.53#ibcon#enter sib2, iclass 11, count 0 2006.239.08:12:47.53#ibcon#flushed, iclass 11, count 0 2006.239.08:12:47.53#ibcon#about to write, iclass 11, count 0 2006.239.08:12:47.53#ibcon#wrote, iclass 11, count 0 2006.239.08:12:47.53#ibcon#about to read 3, iclass 11, count 0 2006.239.08:12:47.55#ibcon#read 3, iclass 11, count 0 2006.239.08:12:47.55#ibcon#about to read 4, iclass 11, count 0 2006.239.08:12:47.55#ibcon#read 4, iclass 11, count 0 2006.239.08:12:47.55#ibcon#about to read 5, iclass 11, count 0 2006.239.08:12:47.55#ibcon#read 5, iclass 11, count 0 2006.239.08:12:47.55#ibcon#about to read 6, iclass 11, count 0 2006.239.08:12:47.55#ibcon#read 6, iclass 11, count 0 2006.239.08:12:47.55#ibcon#end of sib2, iclass 11, count 0 2006.239.08:12:47.55#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:12:47.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:12:47.55#ibcon#[25=USB\r\n] 2006.239.08:12:47.55#ibcon#*before write, iclass 11, count 0 2006.239.08:12:47.55#ibcon#enter sib2, iclass 11, count 0 2006.239.08:12:47.55#ibcon#flushed, iclass 11, count 0 2006.239.08:12:47.55#ibcon#about to write, iclass 11, count 0 2006.239.08:12:47.55#ibcon#wrote, iclass 11, count 0 2006.239.08:12:47.55#ibcon#about to read 3, iclass 11, count 0 2006.239.08:12:47.58#ibcon#read 3, iclass 11, count 0 2006.239.08:12:47.58#ibcon#about to read 4, iclass 11, count 0 2006.239.08:12:47.58#ibcon#read 4, iclass 11, count 0 2006.239.08:12:47.58#ibcon#about to read 5, iclass 11, count 0 2006.239.08:12:47.58#ibcon#read 5, iclass 11, count 0 2006.239.08:12:47.58#ibcon#about to read 6, iclass 11, count 0 2006.239.08:12:47.58#ibcon#read 6, iclass 11, count 0 2006.239.08:12:47.58#ibcon#end of sib2, iclass 11, count 0 2006.239.08:12:47.58#ibcon#*after write, iclass 11, count 0 2006.239.08:12:47.58#ibcon#*before return 0, iclass 11, count 0 2006.239.08:12:47.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:47.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:47.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:12:47.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:12:47.58$vc4f8/valo=3,672.99 2006.239.08:12:47.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.08:12:47.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.08:12:47.58#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:47.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:47.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:47.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:47.58#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:12:47.58#ibcon#first serial, iclass 13, count 0 2006.239.08:12:47.58#ibcon#enter sib2, iclass 13, count 0 2006.239.08:12:47.58#ibcon#flushed, iclass 13, count 0 2006.239.08:12:47.58#ibcon#about to write, iclass 13, count 0 2006.239.08:12:47.58#ibcon#wrote, iclass 13, count 0 2006.239.08:12:47.58#ibcon#about to read 3, iclass 13, count 0 2006.239.08:12:47.60#ibcon#read 3, iclass 13, count 0 2006.239.08:12:47.60#ibcon#about to read 4, iclass 13, count 0 2006.239.08:12:47.60#ibcon#read 4, iclass 13, count 0 2006.239.08:12:47.60#ibcon#about to read 5, iclass 13, count 0 2006.239.08:12:47.60#ibcon#read 5, iclass 13, count 0 2006.239.08:12:47.60#ibcon#about to read 6, iclass 13, count 0 2006.239.08:12:47.60#ibcon#read 6, iclass 13, count 0 2006.239.08:12:47.60#ibcon#end of sib2, iclass 13, count 0 2006.239.08:12:47.60#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:12:47.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:12:47.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:12:47.60#ibcon#*before write, iclass 13, count 0 2006.239.08:12:47.60#ibcon#enter sib2, iclass 13, count 0 2006.239.08:12:47.60#ibcon#flushed, iclass 13, count 0 2006.239.08:12:47.60#ibcon#about to write, iclass 13, count 0 2006.239.08:12:47.60#ibcon#wrote, iclass 13, count 0 2006.239.08:12:47.60#ibcon#about to read 3, iclass 13, count 0 2006.239.08:12:47.64#ibcon#read 3, iclass 13, count 0 2006.239.08:12:47.64#ibcon#about to read 4, iclass 13, count 0 2006.239.08:12:47.64#ibcon#read 4, iclass 13, count 0 2006.239.08:12:47.64#ibcon#about to read 5, iclass 13, count 0 2006.239.08:12:47.64#ibcon#read 5, iclass 13, count 0 2006.239.08:12:47.64#ibcon#about to read 6, iclass 13, count 0 2006.239.08:12:47.64#ibcon#read 6, iclass 13, count 0 2006.239.08:12:47.64#ibcon#end of sib2, iclass 13, count 0 2006.239.08:12:47.64#ibcon#*after write, iclass 13, count 0 2006.239.08:12:47.64#ibcon#*before return 0, iclass 13, count 0 2006.239.08:12:47.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:47.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:47.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:12:47.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:12:47.64$vc4f8/va=3,7 2006.239.08:12:47.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.08:12:47.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.08:12:47.64#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:47.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:47.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:47.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:47.70#ibcon#enter wrdev, iclass 15, count 2 2006.239.08:12:47.70#ibcon#first serial, iclass 15, count 2 2006.239.08:12:47.70#ibcon#enter sib2, iclass 15, count 2 2006.239.08:12:47.70#ibcon#flushed, iclass 15, count 2 2006.239.08:12:47.70#ibcon#about to write, iclass 15, count 2 2006.239.08:12:47.70#ibcon#wrote, iclass 15, count 2 2006.239.08:12:47.70#ibcon#about to read 3, iclass 15, count 2 2006.239.08:12:47.73#ibcon#read 3, iclass 15, count 2 2006.239.08:12:47.73#ibcon#about to read 4, iclass 15, count 2 2006.239.08:12:47.73#ibcon#read 4, iclass 15, count 2 2006.239.08:12:47.73#ibcon#about to read 5, iclass 15, count 2 2006.239.08:12:47.73#ibcon#read 5, iclass 15, count 2 2006.239.08:12:47.73#ibcon#about to read 6, iclass 15, count 2 2006.239.08:12:47.73#ibcon#read 6, iclass 15, count 2 2006.239.08:12:47.73#ibcon#end of sib2, iclass 15, count 2 2006.239.08:12:47.73#ibcon#*mode == 0, iclass 15, count 2 2006.239.08:12:47.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.08:12:47.73#ibcon#[25=AT03-07\r\n] 2006.239.08:12:47.73#ibcon#*before write, iclass 15, count 2 2006.239.08:12:47.73#ibcon#enter sib2, iclass 15, count 2 2006.239.08:12:47.73#ibcon#flushed, iclass 15, count 2 2006.239.08:12:47.73#ibcon#about to write, iclass 15, count 2 2006.239.08:12:47.73#ibcon#wrote, iclass 15, count 2 2006.239.08:12:47.73#ibcon#about to read 3, iclass 15, count 2 2006.239.08:12:47.76#ibcon#read 3, iclass 15, count 2 2006.239.08:12:47.76#ibcon#about to read 4, iclass 15, count 2 2006.239.08:12:47.76#ibcon#read 4, iclass 15, count 2 2006.239.08:12:47.76#ibcon#about to read 5, iclass 15, count 2 2006.239.08:12:47.76#ibcon#read 5, iclass 15, count 2 2006.239.08:12:47.76#ibcon#about to read 6, iclass 15, count 2 2006.239.08:12:47.76#ibcon#read 6, iclass 15, count 2 2006.239.08:12:47.76#ibcon#end of sib2, iclass 15, count 2 2006.239.08:12:47.76#ibcon#*after write, iclass 15, count 2 2006.239.08:12:47.76#ibcon#*before return 0, iclass 15, count 2 2006.239.08:12:47.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:47.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:47.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.08:12:47.76#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:47.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:47.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:47.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:47.88#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:12:47.88#ibcon#first serial, iclass 15, count 0 2006.239.08:12:47.88#ibcon#enter sib2, iclass 15, count 0 2006.239.08:12:47.88#ibcon#flushed, iclass 15, count 0 2006.239.08:12:47.88#ibcon#about to write, iclass 15, count 0 2006.239.08:12:47.88#ibcon#wrote, iclass 15, count 0 2006.239.08:12:47.88#ibcon#about to read 3, iclass 15, count 0 2006.239.08:12:47.90#ibcon#read 3, iclass 15, count 0 2006.239.08:12:47.90#ibcon#about to read 4, iclass 15, count 0 2006.239.08:12:47.90#ibcon#read 4, iclass 15, count 0 2006.239.08:12:47.90#ibcon#about to read 5, iclass 15, count 0 2006.239.08:12:47.90#ibcon#read 5, iclass 15, count 0 2006.239.08:12:47.90#ibcon#about to read 6, iclass 15, count 0 2006.239.08:12:47.90#ibcon#read 6, iclass 15, count 0 2006.239.08:12:47.90#ibcon#end of sib2, iclass 15, count 0 2006.239.08:12:47.90#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:12:47.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:12:47.90#ibcon#[25=USB\r\n] 2006.239.08:12:47.90#ibcon#*before write, iclass 15, count 0 2006.239.08:12:47.90#ibcon#enter sib2, iclass 15, count 0 2006.239.08:12:47.90#ibcon#flushed, iclass 15, count 0 2006.239.08:12:47.90#ibcon#about to write, iclass 15, count 0 2006.239.08:12:47.90#ibcon#wrote, iclass 15, count 0 2006.239.08:12:47.90#ibcon#about to read 3, iclass 15, count 0 2006.239.08:12:47.93#ibcon#read 3, iclass 15, count 0 2006.239.08:12:47.93#ibcon#about to read 4, iclass 15, count 0 2006.239.08:12:47.93#ibcon#read 4, iclass 15, count 0 2006.239.08:12:47.93#ibcon#about to read 5, iclass 15, count 0 2006.239.08:12:47.93#ibcon#read 5, iclass 15, count 0 2006.239.08:12:47.93#ibcon#about to read 6, iclass 15, count 0 2006.239.08:12:47.93#ibcon#read 6, iclass 15, count 0 2006.239.08:12:47.93#ibcon#end of sib2, iclass 15, count 0 2006.239.08:12:47.93#ibcon#*after write, iclass 15, count 0 2006.239.08:12:47.93#ibcon#*before return 0, iclass 15, count 0 2006.239.08:12:47.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:47.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:47.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:12:47.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:12:47.93$vc4f8/valo=4,832.99 2006.239.08:12:47.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.08:12:47.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.08:12:47.93#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:47.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:47.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:47.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:47.93#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:12:47.93#ibcon#first serial, iclass 17, count 0 2006.239.08:12:47.93#ibcon#enter sib2, iclass 17, count 0 2006.239.08:12:47.93#ibcon#flushed, iclass 17, count 0 2006.239.08:12:47.93#ibcon#about to write, iclass 17, count 0 2006.239.08:12:47.93#ibcon#wrote, iclass 17, count 0 2006.239.08:12:47.93#ibcon#about to read 3, iclass 17, count 0 2006.239.08:12:47.95#ibcon#read 3, iclass 17, count 0 2006.239.08:12:47.95#ibcon#about to read 4, iclass 17, count 0 2006.239.08:12:47.95#ibcon#read 4, iclass 17, count 0 2006.239.08:12:47.95#ibcon#about to read 5, iclass 17, count 0 2006.239.08:12:47.95#ibcon#read 5, iclass 17, count 0 2006.239.08:12:47.95#ibcon#about to read 6, iclass 17, count 0 2006.239.08:12:47.95#ibcon#read 6, iclass 17, count 0 2006.239.08:12:47.95#ibcon#end of sib2, iclass 17, count 0 2006.239.08:12:47.95#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:12:47.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:12:47.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:12:47.95#ibcon#*before write, iclass 17, count 0 2006.239.08:12:47.95#ibcon#enter sib2, iclass 17, count 0 2006.239.08:12:47.95#ibcon#flushed, iclass 17, count 0 2006.239.08:12:47.95#ibcon#about to write, iclass 17, count 0 2006.239.08:12:47.95#ibcon#wrote, iclass 17, count 0 2006.239.08:12:47.95#ibcon#about to read 3, iclass 17, count 0 2006.239.08:12:47.99#ibcon#read 3, iclass 17, count 0 2006.239.08:12:47.99#ibcon#about to read 4, iclass 17, count 0 2006.239.08:12:47.99#ibcon#read 4, iclass 17, count 0 2006.239.08:12:47.99#ibcon#about to read 5, iclass 17, count 0 2006.239.08:12:47.99#ibcon#read 5, iclass 17, count 0 2006.239.08:12:47.99#ibcon#about to read 6, iclass 17, count 0 2006.239.08:12:47.99#ibcon#read 6, iclass 17, count 0 2006.239.08:12:47.99#ibcon#end of sib2, iclass 17, count 0 2006.239.08:12:47.99#ibcon#*after write, iclass 17, count 0 2006.239.08:12:47.99#ibcon#*before return 0, iclass 17, count 0 2006.239.08:12:47.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:47.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:47.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:12:47.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:12:47.99$vc4f8/va=4,7 2006.239.08:12:47.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.08:12:47.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.08:12:47.99#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:47.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:48.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:48.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:48.05#ibcon#enter wrdev, iclass 19, count 2 2006.239.08:12:48.05#ibcon#first serial, iclass 19, count 2 2006.239.08:12:48.05#ibcon#enter sib2, iclass 19, count 2 2006.239.08:12:48.05#ibcon#flushed, iclass 19, count 2 2006.239.08:12:48.05#ibcon#about to write, iclass 19, count 2 2006.239.08:12:48.05#ibcon#wrote, iclass 19, count 2 2006.239.08:12:48.05#ibcon#about to read 3, iclass 19, count 2 2006.239.08:12:48.07#ibcon#read 3, iclass 19, count 2 2006.239.08:12:48.07#ibcon#about to read 4, iclass 19, count 2 2006.239.08:12:48.07#ibcon#read 4, iclass 19, count 2 2006.239.08:12:48.07#ibcon#about to read 5, iclass 19, count 2 2006.239.08:12:48.07#ibcon#read 5, iclass 19, count 2 2006.239.08:12:48.07#ibcon#about to read 6, iclass 19, count 2 2006.239.08:12:48.07#ibcon#read 6, iclass 19, count 2 2006.239.08:12:48.07#ibcon#end of sib2, iclass 19, count 2 2006.239.08:12:48.07#ibcon#*mode == 0, iclass 19, count 2 2006.239.08:12:48.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.08:12:48.07#ibcon#[25=AT04-07\r\n] 2006.239.08:12:48.07#ibcon#*before write, iclass 19, count 2 2006.239.08:12:48.07#ibcon#enter sib2, iclass 19, count 2 2006.239.08:12:48.07#ibcon#flushed, iclass 19, count 2 2006.239.08:12:48.07#ibcon#about to write, iclass 19, count 2 2006.239.08:12:48.07#ibcon#wrote, iclass 19, count 2 2006.239.08:12:48.07#ibcon#about to read 3, iclass 19, count 2 2006.239.08:12:48.10#ibcon#read 3, iclass 19, count 2 2006.239.08:12:48.10#ibcon#about to read 4, iclass 19, count 2 2006.239.08:12:48.10#ibcon#read 4, iclass 19, count 2 2006.239.08:12:48.10#ibcon#about to read 5, iclass 19, count 2 2006.239.08:12:48.10#ibcon#read 5, iclass 19, count 2 2006.239.08:12:48.10#ibcon#about to read 6, iclass 19, count 2 2006.239.08:12:48.10#ibcon#read 6, iclass 19, count 2 2006.239.08:12:48.10#ibcon#end of sib2, iclass 19, count 2 2006.239.08:12:48.10#ibcon#*after write, iclass 19, count 2 2006.239.08:12:48.10#ibcon#*before return 0, iclass 19, count 2 2006.239.08:12:48.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:48.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:48.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.08:12:48.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:48.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:48.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:48.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:48.22#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:12:48.22#ibcon#first serial, iclass 19, count 0 2006.239.08:12:48.22#ibcon#enter sib2, iclass 19, count 0 2006.239.08:12:48.22#ibcon#flushed, iclass 19, count 0 2006.239.08:12:48.22#ibcon#about to write, iclass 19, count 0 2006.239.08:12:48.22#ibcon#wrote, iclass 19, count 0 2006.239.08:12:48.22#ibcon#about to read 3, iclass 19, count 0 2006.239.08:12:48.24#ibcon#read 3, iclass 19, count 0 2006.239.08:12:48.24#ibcon#about to read 4, iclass 19, count 0 2006.239.08:12:48.24#ibcon#read 4, iclass 19, count 0 2006.239.08:12:48.24#ibcon#about to read 5, iclass 19, count 0 2006.239.08:12:48.24#ibcon#read 5, iclass 19, count 0 2006.239.08:12:48.24#ibcon#about to read 6, iclass 19, count 0 2006.239.08:12:48.24#ibcon#read 6, iclass 19, count 0 2006.239.08:12:48.24#ibcon#end of sib2, iclass 19, count 0 2006.239.08:12:48.24#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:12:48.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:12:48.24#ibcon#[25=USB\r\n] 2006.239.08:12:48.24#ibcon#*before write, iclass 19, count 0 2006.239.08:12:48.24#ibcon#enter sib2, iclass 19, count 0 2006.239.08:12:48.24#ibcon#flushed, iclass 19, count 0 2006.239.08:12:48.24#ibcon#about to write, iclass 19, count 0 2006.239.08:12:48.24#ibcon#wrote, iclass 19, count 0 2006.239.08:12:48.24#ibcon#about to read 3, iclass 19, count 0 2006.239.08:12:48.27#ibcon#read 3, iclass 19, count 0 2006.239.08:12:48.27#ibcon#about to read 4, iclass 19, count 0 2006.239.08:12:48.27#ibcon#read 4, iclass 19, count 0 2006.239.08:12:48.27#ibcon#about to read 5, iclass 19, count 0 2006.239.08:12:48.27#ibcon#read 5, iclass 19, count 0 2006.239.08:12:48.27#ibcon#about to read 6, iclass 19, count 0 2006.239.08:12:48.27#ibcon#read 6, iclass 19, count 0 2006.239.08:12:48.27#ibcon#end of sib2, iclass 19, count 0 2006.239.08:12:48.27#ibcon#*after write, iclass 19, count 0 2006.239.08:12:48.27#ibcon#*before return 0, iclass 19, count 0 2006.239.08:12:48.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:48.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:48.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:12:48.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:12:48.27$vc4f8/valo=5,652.99 2006.239.08:12:48.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:12:48.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:12:48.27#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:48.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:48.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:48.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:48.27#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:12:48.27#ibcon#first serial, iclass 21, count 0 2006.239.08:12:48.27#ibcon#enter sib2, iclass 21, count 0 2006.239.08:12:48.27#ibcon#flushed, iclass 21, count 0 2006.239.08:12:48.27#ibcon#about to write, iclass 21, count 0 2006.239.08:12:48.27#ibcon#wrote, iclass 21, count 0 2006.239.08:12:48.27#ibcon#about to read 3, iclass 21, count 0 2006.239.08:12:48.29#ibcon#read 3, iclass 21, count 0 2006.239.08:12:48.29#ibcon#about to read 4, iclass 21, count 0 2006.239.08:12:48.29#ibcon#read 4, iclass 21, count 0 2006.239.08:12:48.29#ibcon#about to read 5, iclass 21, count 0 2006.239.08:12:48.29#ibcon#read 5, iclass 21, count 0 2006.239.08:12:48.29#ibcon#about to read 6, iclass 21, count 0 2006.239.08:12:48.29#ibcon#read 6, iclass 21, count 0 2006.239.08:12:48.29#ibcon#end of sib2, iclass 21, count 0 2006.239.08:12:48.29#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:12:48.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:12:48.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:12:48.29#ibcon#*before write, iclass 21, count 0 2006.239.08:12:48.29#ibcon#enter sib2, iclass 21, count 0 2006.239.08:12:48.29#ibcon#flushed, iclass 21, count 0 2006.239.08:12:48.29#ibcon#about to write, iclass 21, count 0 2006.239.08:12:48.29#ibcon#wrote, iclass 21, count 0 2006.239.08:12:48.29#ibcon#about to read 3, iclass 21, count 0 2006.239.08:12:48.33#ibcon#read 3, iclass 21, count 0 2006.239.08:12:48.33#ibcon#about to read 4, iclass 21, count 0 2006.239.08:12:48.33#ibcon#read 4, iclass 21, count 0 2006.239.08:12:48.33#ibcon#about to read 5, iclass 21, count 0 2006.239.08:12:48.33#ibcon#read 5, iclass 21, count 0 2006.239.08:12:48.33#ibcon#about to read 6, iclass 21, count 0 2006.239.08:12:48.33#ibcon#read 6, iclass 21, count 0 2006.239.08:12:48.33#ibcon#end of sib2, iclass 21, count 0 2006.239.08:12:48.33#ibcon#*after write, iclass 21, count 0 2006.239.08:12:48.33#ibcon#*before return 0, iclass 21, count 0 2006.239.08:12:48.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:48.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:48.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:12:48.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:12:48.33$vc4f8/va=5,8 2006.239.08:12:48.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.08:12:48.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.08:12:48.33#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:48.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:48.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:48.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:48.39#ibcon#enter wrdev, iclass 23, count 2 2006.239.08:12:48.39#ibcon#first serial, iclass 23, count 2 2006.239.08:12:48.39#ibcon#enter sib2, iclass 23, count 2 2006.239.08:12:48.39#ibcon#flushed, iclass 23, count 2 2006.239.08:12:48.39#ibcon#about to write, iclass 23, count 2 2006.239.08:12:48.39#ibcon#wrote, iclass 23, count 2 2006.239.08:12:48.39#ibcon#about to read 3, iclass 23, count 2 2006.239.08:12:48.41#ibcon#read 3, iclass 23, count 2 2006.239.08:12:48.41#ibcon#about to read 4, iclass 23, count 2 2006.239.08:12:48.41#ibcon#read 4, iclass 23, count 2 2006.239.08:12:48.41#ibcon#about to read 5, iclass 23, count 2 2006.239.08:12:48.41#ibcon#read 5, iclass 23, count 2 2006.239.08:12:48.41#ibcon#about to read 6, iclass 23, count 2 2006.239.08:12:48.41#ibcon#read 6, iclass 23, count 2 2006.239.08:12:48.41#ibcon#end of sib2, iclass 23, count 2 2006.239.08:12:48.41#ibcon#*mode == 0, iclass 23, count 2 2006.239.08:12:48.41#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.08:12:48.41#ibcon#[25=AT05-08\r\n] 2006.239.08:12:48.41#ibcon#*before write, iclass 23, count 2 2006.239.08:12:48.41#ibcon#enter sib2, iclass 23, count 2 2006.239.08:12:48.41#ibcon#flushed, iclass 23, count 2 2006.239.08:12:48.41#ibcon#about to write, iclass 23, count 2 2006.239.08:12:48.41#ibcon#wrote, iclass 23, count 2 2006.239.08:12:48.41#ibcon#about to read 3, iclass 23, count 2 2006.239.08:12:48.44#ibcon#read 3, iclass 23, count 2 2006.239.08:12:48.44#ibcon#about to read 4, iclass 23, count 2 2006.239.08:12:48.44#ibcon#read 4, iclass 23, count 2 2006.239.08:12:48.44#ibcon#about to read 5, iclass 23, count 2 2006.239.08:12:48.44#ibcon#read 5, iclass 23, count 2 2006.239.08:12:48.44#ibcon#about to read 6, iclass 23, count 2 2006.239.08:12:48.44#ibcon#read 6, iclass 23, count 2 2006.239.08:12:48.44#ibcon#end of sib2, iclass 23, count 2 2006.239.08:12:48.44#ibcon#*after write, iclass 23, count 2 2006.239.08:12:48.44#ibcon#*before return 0, iclass 23, count 2 2006.239.08:12:48.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:48.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:48.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.08:12:48.44#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:48.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:48.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:48.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:48.56#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:12:48.56#ibcon#first serial, iclass 23, count 0 2006.239.08:12:48.56#ibcon#enter sib2, iclass 23, count 0 2006.239.08:12:48.56#ibcon#flushed, iclass 23, count 0 2006.239.08:12:48.56#ibcon#about to write, iclass 23, count 0 2006.239.08:12:48.56#ibcon#wrote, iclass 23, count 0 2006.239.08:12:48.56#ibcon#about to read 3, iclass 23, count 0 2006.239.08:12:48.58#ibcon#read 3, iclass 23, count 0 2006.239.08:12:48.58#ibcon#about to read 4, iclass 23, count 0 2006.239.08:12:48.58#ibcon#read 4, iclass 23, count 0 2006.239.08:12:48.58#ibcon#about to read 5, iclass 23, count 0 2006.239.08:12:48.58#ibcon#read 5, iclass 23, count 0 2006.239.08:12:48.58#ibcon#about to read 6, iclass 23, count 0 2006.239.08:12:48.58#ibcon#read 6, iclass 23, count 0 2006.239.08:12:48.58#ibcon#end of sib2, iclass 23, count 0 2006.239.08:12:48.58#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:12:48.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:12:48.58#ibcon#[25=USB\r\n] 2006.239.08:12:48.58#ibcon#*before write, iclass 23, count 0 2006.239.08:12:48.58#ibcon#enter sib2, iclass 23, count 0 2006.239.08:12:48.58#ibcon#flushed, iclass 23, count 0 2006.239.08:12:48.58#ibcon#about to write, iclass 23, count 0 2006.239.08:12:48.58#ibcon#wrote, iclass 23, count 0 2006.239.08:12:48.58#ibcon#about to read 3, iclass 23, count 0 2006.239.08:12:48.61#ibcon#read 3, iclass 23, count 0 2006.239.08:12:48.61#ibcon#about to read 4, iclass 23, count 0 2006.239.08:12:48.61#ibcon#read 4, iclass 23, count 0 2006.239.08:12:48.61#ibcon#about to read 5, iclass 23, count 0 2006.239.08:12:48.61#ibcon#read 5, iclass 23, count 0 2006.239.08:12:48.61#ibcon#about to read 6, iclass 23, count 0 2006.239.08:12:48.61#ibcon#read 6, iclass 23, count 0 2006.239.08:12:48.61#ibcon#end of sib2, iclass 23, count 0 2006.239.08:12:48.61#ibcon#*after write, iclass 23, count 0 2006.239.08:12:48.61#ibcon#*before return 0, iclass 23, count 0 2006.239.08:12:48.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:48.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:48.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:12:48.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:12:48.61$vc4f8/valo=6,772.99 2006.239.08:12:48.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.08:12:48.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.08:12:48.61#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:48.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:48.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:48.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:48.61#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:12:48.61#ibcon#first serial, iclass 25, count 0 2006.239.08:12:48.61#ibcon#enter sib2, iclass 25, count 0 2006.239.08:12:48.61#ibcon#flushed, iclass 25, count 0 2006.239.08:12:48.61#ibcon#about to write, iclass 25, count 0 2006.239.08:12:48.61#ibcon#wrote, iclass 25, count 0 2006.239.08:12:48.61#ibcon#about to read 3, iclass 25, count 0 2006.239.08:12:48.64#ibcon#read 3, iclass 25, count 0 2006.239.08:12:48.64#ibcon#about to read 4, iclass 25, count 0 2006.239.08:12:48.64#ibcon#read 4, iclass 25, count 0 2006.239.08:12:48.64#ibcon#about to read 5, iclass 25, count 0 2006.239.08:12:48.64#ibcon#read 5, iclass 25, count 0 2006.239.08:12:48.64#ibcon#about to read 6, iclass 25, count 0 2006.239.08:12:48.64#ibcon#read 6, iclass 25, count 0 2006.239.08:12:48.64#ibcon#end of sib2, iclass 25, count 0 2006.239.08:12:48.64#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:12:48.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:12:48.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:12:48.64#ibcon#*before write, iclass 25, count 0 2006.239.08:12:48.64#ibcon#enter sib2, iclass 25, count 0 2006.239.08:12:48.64#ibcon#flushed, iclass 25, count 0 2006.239.08:12:48.64#ibcon#about to write, iclass 25, count 0 2006.239.08:12:48.64#ibcon#wrote, iclass 25, count 0 2006.239.08:12:48.64#ibcon#about to read 3, iclass 25, count 0 2006.239.08:12:48.68#ibcon#read 3, iclass 25, count 0 2006.239.08:12:48.68#ibcon#about to read 4, iclass 25, count 0 2006.239.08:12:48.68#ibcon#read 4, iclass 25, count 0 2006.239.08:12:48.68#ibcon#about to read 5, iclass 25, count 0 2006.239.08:12:48.68#ibcon#read 5, iclass 25, count 0 2006.239.08:12:48.68#ibcon#about to read 6, iclass 25, count 0 2006.239.08:12:48.68#ibcon#read 6, iclass 25, count 0 2006.239.08:12:48.68#ibcon#end of sib2, iclass 25, count 0 2006.239.08:12:48.68#ibcon#*after write, iclass 25, count 0 2006.239.08:12:48.68#ibcon#*before return 0, iclass 25, count 0 2006.239.08:12:48.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:48.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:48.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:12:48.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:12:48.68$vc4f8/va=6,7 2006.239.08:12:48.68#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.08:12:48.68#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.08:12:48.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:48.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:12:48.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:12:48.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:12:48.73#ibcon#enter wrdev, iclass 27, count 2 2006.239.08:12:48.73#ibcon#first serial, iclass 27, count 2 2006.239.08:12:48.73#ibcon#enter sib2, iclass 27, count 2 2006.239.08:12:48.73#ibcon#flushed, iclass 27, count 2 2006.239.08:12:48.73#ibcon#about to write, iclass 27, count 2 2006.239.08:12:48.73#ibcon#wrote, iclass 27, count 2 2006.239.08:12:48.73#ibcon#about to read 3, iclass 27, count 2 2006.239.08:12:48.75#ibcon#read 3, iclass 27, count 2 2006.239.08:12:48.75#ibcon#about to read 4, iclass 27, count 2 2006.239.08:12:48.75#ibcon#read 4, iclass 27, count 2 2006.239.08:12:48.75#ibcon#about to read 5, iclass 27, count 2 2006.239.08:12:48.75#ibcon#read 5, iclass 27, count 2 2006.239.08:12:48.75#ibcon#about to read 6, iclass 27, count 2 2006.239.08:12:48.75#ibcon#read 6, iclass 27, count 2 2006.239.08:12:48.75#ibcon#end of sib2, iclass 27, count 2 2006.239.08:12:48.75#ibcon#*mode == 0, iclass 27, count 2 2006.239.08:12:48.75#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.08:12:48.75#ibcon#[25=AT06-07\r\n] 2006.239.08:12:48.75#ibcon#*before write, iclass 27, count 2 2006.239.08:12:48.75#ibcon#enter sib2, iclass 27, count 2 2006.239.08:12:48.75#ibcon#flushed, iclass 27, count 2 2006.239.08:12:48.75#ibcon#about to write, iclass 27, count 2 2006.239.08:12:48.75#ibcon#wrote, iclass 27, count 2 2006.239.08:12:48.75#ibcon#about to read 3, iclass 27, count 2 2006.239.08:12:48.78#ibcon#read 3, iclass 27, count 2 2006.239.08:12:48.78#ibcon#about to read 4, iclass 27, count 2 2006.239.08:12:48.78#ibcon#read 4, iclass 27, count 2 2006.239.08:12:48.78#ibcon#about to read 5, iclass 27, count 2 2006.239.08:12:48.78#ibcon#read 5, iclass 27, count 2 2006.239.08:12:48.78#ibcon#about to read 6, iclass 27, count 2 2006.239.08:12:48.78#ibcon#read 6, iclass 27, count 2 2006.239.08:12:48.78#ibcon#end of sib2, iclass 27, count 2 2006.239.08:12:48.78#ibcon#*after write, iclass 27, count 2 2006.239.08:12:48.78#ibcon#*before return 0, iclass 27, count 2 2006.239.08:12:48.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:12:48.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:12:48.78#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.08:12:48.78#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:48.78#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:12:48.90#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:12:48.90#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:12:48.90#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:12:48.90#ibcon#first serial, iclass 27, count 0 2006.239.08:12:48.90#ibcon#enter sib2, iclass 27, count 0 2006.239.08:12:48.90#ibcon#flushed, iclass 27, count 0 2006.239.08:12:48.90#ibcon#about to write, iclass 27, count 0 2006.239.08:12:48.90#ibcon#wrote, iclass 27, count 0 2006.239.08:12:48.90#ibcon#about to read 3, iclass 27, count 0 2006.239.08:12:48.92#ibcon#read 3, iclass 27, count 0 2006.239.08:12:48.92#ibcon#about to read 4, iclass 27, count 0 2006.239.08:12:48.92#ibcon#read 4, iclass 27, count 0 2006.239.08:12:48.92#ibcon#about to read 5, iclass 27, count 0 2006.239.08:12:48.92#ibcon#read 5, iclass 27, count 0 2006.239.08:12:48.92#ibcon#about to read 6, iclass 27, count 0 2006.239.08:12:48.92#ibcon#read 6, iclass 27, count 0 2006.239.08:12:48.92#ibcon#end of sib2, iclass 27, count 0 2006.239.08:12:48.92#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:12:48.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:12:48.92#ibcon#[25=USB\r\n] 2006.239.08:12:48.92#ibcon#*before write, iclass 27, count 0 2006.239.08:12:48.92#ibcon#enter sib2, iclass 27, count 0 2006.239.08:12:48.92#ibcon#flushed, iclass 27, count 0 2006.239.08:12:48.92#ibcon#about to write, iclass 27, count 0 2006.239.08:12:48.92#ibcon#wrote, iclass 27, count 0 2006.239.08:12:48.92#ibcon#about to read 3, iclass 27, count 0 2006.239.08:12:48.95#ibcon#read 3, iclass 27, count 0 2006.239.08:12:48.95#ibcon#about to read 4, iclass 27, count 0 2006.239.08:12:48.95#ibcon#read 4, iclass 27, count 0 2006.239.08:12:48.95#ibcon#about to read 5, iclass 27, count 0 2006.239.08:12:48.95#ibcon#read 5, iclass 27, count 0 2006.239.08:12:48.95#ibcon#about to read 6, iclass 27, count 0 2006.239.08:12:48.95#ibcon#read 6, iclass 27, count 0 2006.239.08:12:48.95#ibcon#end of sib2, iclass 27, count 0 2006.239.08:12:48.95#ibcon#*after write, iclass 27, count 0 2006.239.08:12:48.95#ibcon#*before return 0, iclass 27, count 0 2006.239.08:12:48.95#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:12:48.95#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:12:48.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:12:48.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:12:48.95$vc4f8/valo=7,832.99 2006.239.08:12:48.95#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.08:12:48.95#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.08:12:48.95#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:48.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:12:48.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:12:48.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:12:48.95#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:12:48.95#ibcon#first serial, iclass 29, count 0 2006.239.08:12:48.95#ibcon#enter sib2, iclass 29, count 0 2006.239.08:12:48.95#ibcon#flushed, iclass 29, count 0 2006.239.08:12:48.95#ibcon#about to write, iclass 29, count 0 2006.239.08:12:48.95#ibcon#wrote, iclass 29, count 0 2006.239.08:12:48.95#ibcon#about to read 3, iclass 29, count 0 2006.239.08:12:48.97#ibcon#read 3, iclass 29, count 0 2006.239.08:12:48.97#ibcon#about to read 4, iclass 29, count 0 2006.239.08:12:48.97#ibcon#read 4, iclass 29, count 0 2006.239.08:12:48.97#ibcon#about to read 5, iclass 29, count 0 2006.239.08:12:48.97#ibcon#read 5, iclass 29, count 0 2006.239.08:12:48.97#ibcon#about to read 6, iclass 29, count 0 2006.239.08:12:48.97#ibcon#read 6, iclass 29, count 0 2006.239.08:12:48.97#ibcon#end of sib2, iclass 29, count 0 2006.239.08:12:48.97#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:12:48.97#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:12:48.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:12:48.97#ibcon#*before write, iclass 29, count 0 2006.239.08:12:48.97#ibcon#enter sib2, iclass 29, count 0 2006.239.08:12:48.97#ibcon#flushed, iclass 29, count 0 2006.239.08:12:48.97#ibcon#about to write, iclass 29, count 0 2006.239.08:12:48.97#ibcon#wrote, iclass 29, count 0 2006.239.08:12:48.97#ibcon#about to read 3, iclass 29, count 0 2006.239.08:12:49.01#ibcon#read 3, iclass 29, count 0 2006.239.08:12:49.01#ibcon#about to read 4, iclass 29, count 0 2006.239.08:12:49.01#ibcon#read 4, iclass 29, count 0 2006.239.08:12:49.01#ibcon#about to read 5, iclass 29, count 0 2006.239.08:12:49.01#ibcon#read 5, iclass 29, count 0 2006.239.08:12:49.01#ibcon#about to read 6, iclass 29, count 0 2006.239.08:12:49.01#ibcon#read 6, iclass 29, count 0 2006.239.08:12:49.01#ibcon#end of sib2, iclass 29, count 0 2006.239.08:12:49.01#ibcon#*after write, iclass 29, count 0 2006.239.08:12:49.01#ibcon#*before return 0, iclass 29, count 0 2006.239.08:12:49.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:12:49.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:12:49.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:12:49.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:12:49.01$vc4f8/va=7,7 2006.239.08:12:49.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.08:12:49.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.08:12:49.01#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:49.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:12:49.07#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:12:49.07#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:12:49.07#ibcon#enter wrdev, iclass 31, count 2 2006.239.08:12:49.07#ibcon#first serial, iclass 31, count 2 2006.239.08:12:49.07#ibcon#enter sib2, iclass 31, count 2 2006.239.08:12:49.07#ibcon#flushed, iclass 31, count 2 2006.239.08:12:49.07#ibcon#about to write, iclass 31, count 2 2006.239.08:12:49.07#ibcon#wrote, iclass 31, count 2 2006.239.08:12:49.07#ibcon#about to read 3, iclass 31, count 2 2006.239.08:12:49.09#ibcon#read 3, iclass 31, count 2 2006.239.08:12:49.09#ibcon#about to read 4, iclass 31, count 2 2006.239.08:12:49.09#ibcon#read 4, iclass 31, count 2 2006.239.08:12:49.09#ibcon#about to read 5, iclass 31, count 2 2006.239.08:12:49.09#ibcon#read 5, iclass 31, count 2 2006.239.08:12:49.09#ibcon#about to read 6, iclass 31, count 2 2006.239.08:12:49.09#ibcon#read 6, iclass 31, count 2 2006.239.08:12:49.09#ibcon#end of sib2, iclass 31, count 2 2006.239.08:12:49.09#ibcon#*mode == 0, iclass 31, count 2 2006.239.08:12:49.09#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.08:12:49.09#ibcon#[25=AT07-07\r\n] 2006.239.08:12:49.09#ibcon#*before write, iclass 31, count 2 2006.239.08:12:49.09#ibcon#enter sib2, iclass 31, count 2 2006.239.08:12:49.09#ibcon#flushed, iclass 31, count 2 2006.239.08:12:49.09#ibcon#about to write, iclass 31, count 2 2006.239.08:12:49.09#ibcon#wrote, iclass 31, count 2 2006.239.08:12:49.09#ibcon#about to read 3, iclass 31, count 2 2006.239.08:12:49.12#ibcon#read 3, iclass 31, count 2 2006.239.08:12:49.12#ibcon#about to read 4, iclass 31, count 2 2006.239.08:12:49.12#ibcon#read 4, iclass 31, count 2 2006.239.08:12:49.12#ibcon#about to read 5, iclass 31, count 2 2006.239.08:12:49.12#ibcon#read 5, iclass 31, count 2 2006.239.08:12:49.12#ibcon#about to read 6, iclass 31, count 2 2006.239.08:12:49.12#ibcon#read 6, iclass 31, count 2 2006.239.08:12:49.12#ibcon#end of sib2, iclass 31, count 2 2006.239.08:12:49.12#ibcon#*after write, iclass 31, count 2 2006.239.08:12:49.12#ibcon#*before return 0, iclass 31, count 2 2006.239.08:12:49.12#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:12:49.12#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:12:49.12#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.08:12:49.12#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:49.12#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:12:49.24#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:12:49.24#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:12:49.24#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:12:49.24#ibcon#first serial, iclass 31, count 0 2006.239.08:12:49.24#ibcon#enter sib2, iclass 31, count 0 2006.239.08:12:49.24#ibcon#flushed, iclass 31, count 0 2006.239.08:12:49.24#ibcon#about to write, iclass 31, count 0 2006.239.08:12:49.24#ibcon#wrote, iclass 31, count 0 2006.239.08:12:49.24#ibcon#about to read 3, iclass 31, count 0 2006.239.08:12:49.27#ibcon#read 3, iclass 31, count 0 2006.239.08:12:49.27#ibcon#about to read 4, iclass 31, count 0 2006.239.08:12:49.27#ibcon#read 4, iclass 31, count 0 2006.239.08:12:49.27#ibcon#about to read 5, iclass 31, count 0 2006.239.08:12:49.27#ibcon#read 5, iclass 31, count 0 2006.239.08:12:49.27#ibcon#about to read 6, iclass 31, count 0 2006.239.08:12:49.27#ibcon#read 6, iclass 31, count 0 2006.239.08:12:49.27#ibcon#end of sib2, iclass 31, count 0 2006.239.08:12:49.27#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:12:49.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:12:49.27#ibcon#[25=USB\r\n] 2006.239.08:12:49.27#ibcon#*before write, iclass 31, count 0 2006.239.08:12:49.27#ibcon#enter sib2, iclass 31, count 0 2006.239.08:12:49.27#ibcon#flushed, iclass 31, count 0 2006.239.08:12:49.27#ibcon#about to write, iclass 31, count 0 2006.239.08:12:49.27#ibcon#wrote, iclass 31, count 0 2006.239.08:12:49.27#ibcon#about to read 3, iclass 31, count 0 2006.239.08:12:49.29#ibcon#read 3, iclass 31, count 0 2006.239.08:12:49.29#ibcon#about to read 4, iclass 31, count 0 2006.239.08:12:49.29#ibcon#read 4, iclass 31, count 0 2006.239.08:12:49.29#ibcon#about to read 5, iclass 31, count 0 2006.239.08:12:49.29#ibcon#read 5, iclass 31, count 0 2006.239.08:12:49.29#ibcon#about to read 6, iclass 31, count 0 2006.239.08:12:49.29#ibcon#read 6, iclass 31, count 0 2006.239.08:12:49.29#ibcon#end of sib2, iclass 31, count 0 2006.239.08:12:49.29#ibcon#*after write, iclass 31, count 0 2006.239.08:12:49.29#ibcon#*before return 0, iclass 31, count 0 2006.239.08:12:49.29#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:12:49.29#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:12:49.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:12:49.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:12:49.29$vc4f8/valo=8,852.99 2006.239.08:12:49.29#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.08:12:49.29#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.08:12:49.29#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:49.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:12:49.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:12:49.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:12:49.29#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:12:49.29#ibcon#first serial, iclass 33, count 0 2006.239.08:12:49.29#ibcon#enter sib2, iclass 33, count 0 2006.239.08:12:49.29#ibcon#flushed, iclass 33, count 0 2006.239.08:12:49.29#ibcon#about to write, iclass 33, count 0 2006.239.08:12:49.29#ibcon#wrote, iclass 33, count 0 2006.239.08:12:49.29#ibcon#about to read 3, iclass 33, count 0 2006.239.08:12:49.31#ibcon#read 3, iclass 33, count 0 2006.239.08:12:49.31#ibcon#about to read 4, iclass 33, count 0 2006.239.08:12:49.31#ibcon#read 4, iclass 33, count 0 2006.239.08:12:49.31#ibcon#about to read 5, iclass 33, count 0 2006.239.08:12:49.31#ibcon#read 5, iclass 33, count 0 2006.239.08:12:49.31#ibcon#about to read 6, iclass 33, count 0 2006.239.08:12:49.31#ibcon#read 6, iclass 33, count 0 2006.239.08:12:49.31#ibcon#end of sib2, iclass 33, count 0 2006.239.08:12:49.31#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:12:49.31#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:12:49.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:12:49.31#ibcon#*before write, iclass 33, count 0 2006.239.08:12:49.31#ibcon#enter sib2, iclass 33, count 0 2006.239.08:12:49.31#ibcon#flushed, iclass 33, count 0 2006.239.08:12:49.31#ibcon#about to write, iclass 33, count 0 2006.239.08:12:49.31#ibcon#wrote, iclass 33, count 0 2006.239.08:12:49.31#ibcon#about to read 3, iclass 33, count 0 2006.239.08:12:49.36#ibcon#read 3, iclass 33, count 0 2006.239.08:12:49.36#ibcon#about to read 4, iclass 33, count 0 2006.239.08:12:49.36#ibcon#read 4, iclass 33, count 0 2006.239.08:12:49.36#ibcon#about to read 5, iclass 33, count 0 2006.239.08:12:49.36#ibcon#read 5, iclass 33, count 0 2006.239.08:12:49.36#ibcon#about to read 6, iclass 33, count 0 2006.239.08:12:49.36#ibcon#read 6, iclass 33, count 0 2006.239.08:12:49.36#ibcon#end of sib2, iclass 33, count 0 2006.239.08:12:49.36#ibcon#*after write, iclass 33, count 0 2006.239.08:12:49.36#ibcon#*before return 0, iclass 33, count 0 2006.239.08:12:49.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:12:49.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:12:49.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:12:49.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:12:49.36$vc4f8/va=8,7 2006.239.08:12:49.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.08:12:49.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.08:12:49.36#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:49.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:12:49.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:12:49.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:12:49.40#ibcon#enter wrdev, iclass 35, count 2 2006.239.08:12:49.40#ibcon#first serial, iclass 35, count 2 2006.239.08:12:49.40#ibcon#enter sib2, iclass 35, count 2 2006.239.08:12:49.40#ibcon#flushed, iclass 35, count 2 2006.239.08:12:49.40#ibcon#about to write, iclass 35, count 2 2006.239.08:12:49.40#ibcon#wrote, iclass 35, count 2 2006.239.08:12:49.40#ibcon#about to read 3, iclass 35, count 2 2006.239.08:12:49.42#ibcon#read 3, iclass 35, count 2 2006.239.08:12:49.42#ibcon#about to read 4, iclass 35, count 2 2006.239.08:12:49.42#ibcon#read 4, iclass 35, count 2 2006.239.08:12:49.42#ibcon#about to read 5, iclass 35, count 2 2006.239.08:12:49.42#ibcon#read 5, iclass 35, count 2 2006.239.08:12:49.42#ibcon#about to read 6, iclass 35, count 2 2006.239.08:12:49.42#ibcon#read 6, iclass 35, count 2 2006.239.08:12:49.42#ibcon#end of sib2, iclass 35, count 2 2006.239.08:12:49.42#ibcon#*mode == 0, iclass 35, count 2 2006.239.08:12:49.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.08:12:49.42#ibcon#[25=AT08-07\r\n] 2006.239.08:12:49.42#ibcon#*before write, iclass 35, count 2 2006.239.08:12:49.42#ibcon#enter sib2, iclass 35, count 2 2006.239.08:12:49.42#ibcon#flushed, iclass 35, count 2 2006.239.08:12:49.42#ibcon#about to write, iclass 35, count 2 2006.239.08:12:49.42#ibcon#wrote, iclass 35, count 2 2006.239.08:12:49.42#ibcon#about to read 3, iclass 35, count 2 2006.239.08:12:49.45#ibcon#read 3, iclass 35, count 2 2006.239.08:12:49.45#ibcon#about to read 4, iclass 35, count 2 2006.239.08:12:49.45#ibcon#read 4, iclass 35, count 2 2006.239.08:12:49.45#ibcon#about to read 5, iclass 35, count 2 2006.239.08:12:49.45#ibcon#read 5, iclass 35, count 2 2006.239.08:12:49.45#ibcon#about to read 6, iclass 35, count 2 2006.239.08:12:49.45#ibcon#read 6, iclass 35, count 2 2006.239.08:12:49.45#ibcon#end of sib2, iclass 35, count 2 2006.239.08:12:49.45#ibcon#*after write, iclass 35, count 2 2006.239.08:12:49.45#ibcon#*before return 0, iclass 35, count 2 2006.239.08:12:49.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:12:49.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:12:49.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.08:12:49.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:49.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:12:49.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:12:49.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:12:49.57#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:12:49.57#ibcon#first serial, iclass 35, count 0 2006.239.08:12:49.57#ibcon#enter sib2, iclass 35, count 0 2006.239.08:12:49.57#ibcon#flushed, iclass 35, count 0 2006.239.08:12:49.57#ibcon#about to write, iclass 35, count 0 2006.239.08:12:49.57#ibcon#wrote, iclass 35, count 0 2006.239.08:12:49.57#ibcon#about to read 3, iclass 35, count 0 2006.239.08:12:49.59#ibcon#read 3, iclass 35, count 0 2006.239.08:12:49.59#ibcon#about to read 4, iclass 35, count 0 2006.239.08:12:49.59#ibcon#read 4, iclass 35, count 0 2006.239.08:12:49.59#ibcon#about to read 5, iclass 35, count 0 2006.239.08:12:49.59#ibcon#read 5, iclass 35, count 0 2006.239.08:12:49.59#ibcon#about to read 6, iclass 35, count 0 2006.239.08:12:49.59#ibcon#read 6, iclass 35, count 0 2006.239.08:12:49.59#ibcon#end of sib2, iclass 35, count 0 2006.239.08:12:49.59#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:12:49.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:12:49.59#ibcon#[25=USB\r\n] 2006.239.08:12:49.59#ibcon#*before write, iclass 35, count 0 2006.239.08:12:49.59#ibcon#enter sib2, iclass 35, count 0 2006.239.08:12:49.59#ibcon#flushed, iclass 35, count 0 2006.239.08:12:49.59#ibcon#about to write, iclass 35, count 0 2006.239.08:12:49.59#ibcon#wrote, iclass 35, count 0 2006.239.08:12:49.59#ibcon#about to read 3, iclass 35, count 0 2006.239.08:12:49.62#ibcon#read 3, iclass 35, count 0 2006.239.08:12:49.62#ibcon#about to read 4, iclass 35, count 0 2006.239.08:12:49.62#ibcon#read 4, iclass 35, count 0 2006.239.08:12:49.62#ibcon#about to read 5, iclass 35, count 0 2006.239.08:12:49.62#ibcon#read 5, iclass 35, count 0 2006.239.08:12:49.62#ibcon#about to read 6, iclass 35, count 0 2006.239.08:12:49.62#ibcon#read 6, iclass 35, count 0 2006.239.08:12:49.62#ibcon#end of sib2, iclass 35, count 0 2006.239.08:12:49.62#ibcon#*after write, iclass 35, count 0 2006.239.08:12:49.62#ibcon#*before return 0, iclass 35, count 0 2006.239.08:12:49.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:12:49.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:12:49.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:12:49.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:12:49.62$vc4f8/vblo=1,632.99 2006.239.08:12:49.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.08:12:49.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.08:12:49.62#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:49.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:12:49.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:12:49.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:12:49.62#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:12:49.62#ibcon#first serial, iclass 37, count 0 2006.239.08:12:49.62#ibcon#enter sib2, iclass 37, count 0 2006.239.08:12:49.62#ibcon#flushed, iclass 37, count 0 2006.239.08:12:49.62#ibcon#about to write, iclass 37, count 0 2006.239.08:12:49.62#ibcon#wrote, iclass 37, count 0 2006.239.08:12:49.62#ibcon#about to read 3, iclass 37, count 0 2006.239.08:12:49.64#ibcon#read 3, iclass 37, count 0 2006.239.08:12:49.64#ibcon#about to read 4, iclass 37, count 0 2006.239.08:12:49.64#ibcon#read 4, iclass 37, count 0 2006.239.08:12:49.64#ibcon#about to read 5, iclass 37, count 0 2006.239.08:12:49.64#ibcon#read 5, iclass 37, count 0 2006.239.08:12:49.64#ibcon#about to read 6, iclass 37, count 0 2006.239.08:12:49.64#ibcon#read 6, iclass 37, count 0 2006.239.08:12:49.64#ibcon#end of sib2, iclass 37, count 0 2006.239.08:12:49.64#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:12:49.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:12:49.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:12:49.64#ibcon#*before write, iclass 37, count 0 2006.239.08:12:49.64#ibcon#enter sib2, iclass 37, count 0 2006.239.08:12:49.64#ibcon#flushed, iclass 37, count 0 2006.239.08:12:49.64#ibcon#about to write, iclass 37, count 0 2006.239.08:12:49.64#ibcon#wrote, iclass 37, count 0 2006.239.08:12:49.64#ibcon#about to read 3, iclass 37, count 0 2006.239.08:12:49.68#ibcon#read 3, iclass 37, count 0 2006.239.08:12:49.68#ibcon#about to read 4, iclass 37, count 0 2006.239.08:12:49.68#ibcon#read 4, iclass 37, count 0 2006.239.08:12:49.68#ibcon#about to read 5, iclass 37, count 0 2006.239.08:12:49.68#ibcon#read 5, iclass 37, count 0 2006.239.08:12:49.68#ibcon#about to read 6, iclass 37, count 0 2006.239.08:12:49.68#ibcon#read 6, iclass 37, count 0 2006.239.08:12:49.68#ibcon#end of sib2, iclass 37, count 0 2006.239.08:12:49.68#ibcon#*after write, iclass 37, count 0 2006.239.08:12:49.68#ibcon#*before return 0, iclass 37, count 0 2006.239.08:12:49.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:12:49.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:12:49.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:12:49.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:12:49.68$vc4f8/vb=1,4 2006.239.08:12:49.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.08:12:49.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.08:12:49.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:49.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:12:49.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:12:49.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:12:49.68#ibcon#enter wrdev, iclass 39, count 2 2006.239.08:12:49.68#ibcon#first serial, iclass 39, count 2 2006.239.08:12:49.68#ibcon#enter sib2, iclass 39, count 2 2006.239.08:12:49.68#ibcon#flushed, iclass 39, count 2 2006.239.08:12:49.68#ibcon#about to write, iclass 39, count 2 2006.239.08:12:49.68#ibcon#wrote, iclass 39, count 2 2006.239.08:12:49.68#ibcon#about to read 3, iclass 39, count 2 2006.239.08:12:49.70#ibcon#read 3, iclass 39, count 2 2006.239.08:12:49.70#ibcon#about to read 4, iclass 39, count 2 2006.239.08:12:49.70#ibcon#read 4, iclass 39, count 2 2006.239.08:12:49.70#ibcon#about to read 5, iclass 39, count 2 2006.239.08:12:49.70#ibcon#read 5, iclass 39, count 2 2006.239.08:12:49.70#ibcon#about to read 6, iclass 39, count 2 2006.239.08:12:49.70#ibcon#read 6, iclass 39, count 2 2006.239.08:12:49.70#ibcon#end of sib2, iclass 39, count 2 2006.239.08:12:49.70#ibcon#*mode == 0, iclass 39, count 2 2006.239.08:12:49.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.08:12:49.70#ibcon#[27=AT01-04\r\n] 2006.239.08:12:49.70#ibcon#*before write, iclass 39, count 2 2006.239.08:12:49.70#ibcon#enter sib2, iclass 39, count 2 2006.239.08:12:49.70#ibcon#flushed, iclass 39, count 2 2006.239.08:12:49.70#ibcon#about to write, iclass 39, count 2 2006.239.08:12:49.70#ibcon#wrote, iclass 39, count 2 2006.239.08:12:49.70#ibcon#about to read 3, iclass 39, count 2 2006.239.08:12:49.73#ibcon#read 3, iclass 39, count 2 2006.239.08:12:49.73#ibcon#about to read 4, iclass 39, count 2 2006.239.08:12:49.73#ibcon#read 4, iclass 39, count 2 2006.239.08:12:49.73#ibcon#about to read 5, iclass 39, count 2 2006.239.08:12:49.73#ibcon#read 5, iclass 39, count 2 2006.239.08:12:49.73#ibcon#about to read 6, iclass 39, count 2 2006.239.08:12:49.73#ibcon#read 6, iclass 39, count 2 2006.239.08:12:49.73#ibcon#end of sib2, iclass 39, count 2 2006.239.08:12:49.73#ibcon#*after write, iclass 39, count 2 2006.239.08:12:49.73#ibcon#*before return 0, iclass 39, count 2 2006.239.08:12:49.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:12:49.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:12:49.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.08:12:49.73#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:49.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:12:49.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:12:49.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:12:49.85#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:12:49.85#ibcon#first serial, iclass 39, count 0 2006.239.08:12:49.85#ibcon#enter sib2, iclass 39, count 0 2006.239.08:12:49.85#ibcon#flushed, iclass 39, count 0 2006.239.08:12:49.85#ibcon#about to write, iclass 39, count 0 2006.239.08:12:49.85#ibcon#wrote, iclass 39, count 0 2006.239.08:12:49.85#ibcon#about to read 3, iclass 39, count 0 2006.239.08:12:49.87#ibcon#read 3, iclass 39, count 0 2006.239.08:12:49.87#ibcon#about to read 4, iclass 39, count 0 2006.239.08:12:49.87#ibcon#read 4, iclass 39, count 0 2006.239.08:12:49.87#ibcon#about to read 5, iclass 39, count 0 2006.239.08:12:49.87#ibcon#read 5, iclass 39, count 0 2006.239.08:12:49.87#ibcon#about to read 6, iclass 39, count 0 2006.239.08:12:49.87#ibcon#read 6, iclass 39, count 0 2006.239.08:12:49.87#ibcon#end of sib2, iclass 39, count 0 2006.239.08:12:49.87#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:12:49.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:12:49.87#ibcon#[27=USB\r\n] 2006.239.08:12:49.87#ibcon#*before write, iclass 39, count 0 2006.239.08:12:49.87#ibcon#enter sib2, iclass 39, count 0 2006.239.08:12:49.87#ibcon#flushed, iclass 39, count 0 2006.239.08:12:49.87#ibcon#about to write, iclass 39, count 0 2006.239.08:12:49.87#ibcon#wrote, iclass 39, count 0 2006.239.08:12:49.87#ibcon#about to read 3, iclass 39, count 0 2006.239.08:12:49.90#ibcon#read 3, iclass 39, count 0 2006.239.08:12:49.90#ibcon#about to read 4, iclass 39, count 0 2006.239.08:12:49.90#ibcon#read 4, iclass 39, count 0 2006.239.08:12:49.90#ibcon#about to read 5, iclass 39, count 0 2006.239.08:12:49.90#ibcon#read 5, iclass 39, count 0 2006.239.08:12:49.90#ibcon#about to read 6, iclass 39, count 0 2006.239.08:12:49.90#ibcon#read 6, iclass 39, count 0 2006.239.08:12:49.90#ibcon#end of sib2, iclass 39, count 0 2006.239.08:12:49.90#ibcon#*after write, iclass 39, count 0 2006.239.08:12:49.90#ibcon#*before return 0, iclass 39, count 0 2006.239.08:12:49.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:12:49.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:12:49.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:12:49.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:12:49.90$vc4f8/vblo=2,640.99 2006.239.08:12:49.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.08:12:49.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.08:12:49.90#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:49.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:49.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:49.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:49.90#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:12:49.90#ibcon#first serial, iclass 3, count 0 2006.239.08:12:49.90#ibcon#enter sib2, iclass 3, count 0 2006.239.08:12:49.90#ibcon#flushed, iclass 3, count 0 2006.239.08:12:49.90#ibcon#about to write, iclass 3, count 0 2006.239.08:12:49.90#ibcon#wrote, iclass 3, count 0 2006.239.08:12:49.90#ibcon#about to read 3, iclass 3, count 0 2006.239.08:12:49.92#ibcon#read 3, iclass 3, count 0 2006.239.08:12:49.92#ibcon#about to read 4, iclass 3, count 0 2006.239.08:12:49.92#ibcon#read 4, iclass 3, count 0 2006.239.08:12:49.92#ibcon#about to read 5, iclass 3, count 0 2006.239.08:12:49.92#ibcon#read 5, iclass 3, count 0 2006.239.08:12:49.92#ibcon#about to read 6, iclass 3, count 0 2006.239.08:12:49.92#ibcon#read 6, iclass 3, count 0 2006.239.08:12:49.92#ibcon#end of sib2, iclass 3, count 0 2006.239.08:12:49.92#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:12:49.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:12:49.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:12:49.92#ibcon#*before write, iclass 3, count 0 2006.239.08:12:49.92#ibcon#enter sib2, iclass 3, count 0 2006.239.08:12:49.92#ibcon#flushed, iclass 3, count 0 2006.239.08:12:49.92#ibcon#about to write, iclass 3, count 0 2006.239.08:12:49.92#ibcon#wrote, iclass 3, count 0 2006.239.08:12:49.92#ibcon#about to read 3, iclass 3, count 0 2006.239.08:12:49.96#ibcon#read 3, iclass 3, count 0 2006.239.08:12:49.96#ibcon#about to read 4, iclass 3, count 0 2006.239.08:12:49.96#ibcon#read 4, iclass 3, count 0 2006.239.08:12:49.96#ibcon#about to read 5, iclass 3, count 0 2006.239.08:12:49.96#ibcon#read 5, iclass 3, count 0 2006.239.08:12:49.96#ibcon#about to read 6, iclass 3, count 0 2006.239.08:12:49.96#ibcon#read 6, iclass 3, count 0 2006.239.08:12:49.96#ibcon#end of sib2, iclass 3, count 0 2006.239.08:12:49.96#ibcon#*after write, iclass 3, count 0 2006.239.08:12:49.96#ibcon#*before return 0, iclass 3, count 0 2006.239.08:12:49.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:49.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:12:49.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:12:49.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:12:49.96$vc4f8/vb=2,4 2006.239.08:12:49.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.08:12:49.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.08:12:49.96#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:49.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:50.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:50.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:50.02#ibcon#enter wrdev, iclass 5, count 2 2006.239.08:12:50.02#ibcon#first serial, iclass 5, count 2 2006.239.08:12:50.02#ibcon#enter sib2, iclass 5, count 2 2006.239.08:12:50.02#ibcon#flushed, iclass 5, count 2 2006.239.08:12:50.02#ibcon#about to write, iclass 5, count 2 2006.239.08:12:50.02#ibcon#wrote, iclass 5, count 2 2006.239.08:12:50.02#ibcon#about to read 3, iclass 5, count 2 2006.239.08:12:50.05#ibcon#read 3, iclass 5, count 2 2006.239.08:12:50.05#ibcon#about to read 4, iclass 5, count 2 2006.239.08:12:50.05#ibcon#read 4, iclass 5, count 2 2006.239.08:12:50.05#ibcon#about to read 5, iclass 5, count 2 2006.239.08:12:50.05#ibcon#read 5, iclass 5, count 2 2006.239.08:12:50.05#ibcon#about to read 6, iclass 5, count 2 2006.239.08:12:50.05#ibcon#read 6, iclass 5, count 2 2006.239.08:12:50.05#ibcon#end of sib2, iclass 5, count 2 2006.239.08:12:50.05#ibcon#*mode == 0, iclass 5, count 2 2006.239.08:12:50.05#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.08:12:50.05#ibcon#[27=AT02-04\r\n] 2006.239.08:12:50.05#ibcon#*before write, iclass 5, count 2 2006.239.08:12:50.05#ibcon#enter sib2, iclass 5, count 2 2006.239.08:12:50.05#ibcon#flushed, iclass 5, count 2 2006.239.08:12:50.05#ibcon#about to write, iclass 5, count 2 2006.239.08:12:50.05#ibcon#wrote, iclass 5, count 2 2006.239.08:12:50.05#ibcon#about to read 3, iclass 5, count 2 2006.239.08:12:50.08#ibcon#read 3, iclass 5, count 2 2006.239.08:12:50.08#ibcon#about to read 4, iclass 5, count 2 2006.239.08:12:50.08#ibcon#read 4, iclass 5, count 2 2006.239.08:12:50.08#ibcon#about to read 5, iclass 5, count 2 2006.239.08:12:50.08#ibcon#read 5, iclass 5, count 2 2006.239.08:12:50.08#ibcon#about to read 6, iclass 5, count 2 2006.239.08:12:50.08#ibcon#read 6, iclass 5, count 2 2006.239.08:12:50.08#ibcon#end of sib2, iclass 5, count 2 2006.239.08:12:50.08#ibcon#*after write, iclass 5, count 2 2006.239.08:12:50.08#ibcon#*before return 0, iclass 5, count 2 2006.239.08:12:50.08#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:50.08#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:12:50.08#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.08:12:50.08#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:50.08#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:50.20#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:50.20#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:50.20#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:12:50.20#ibcon#first serial, iclass 5, count 0 2006.239.08:12:50.20#ibcon#enter sib2, iclass 5, count 0 2006.239.08:12:50.20#ibcon#flushed, iclass 5, count 0 2006.239.08:12:50.20#ibcon#about to write, iclass 5, count 0 2006.239.08:12:50.20#ibcon#wrote, iclass 5, count 0 2006.239.08:12:50.20#ibcon#about to read 3, iclass 5, count 0 2006.239.08:12:50.22#ibcon#read 3, iclass 5, count 0 2006.239.08:12:50.22#ibcon#about to read 4, iclass 5, count 0 2006.239.08:12:50.22#ibcon#read 4, iclass 5, count 0 2006.239.08:12:50.22#ibcon#about to read 5, iclass 5, count 0 2006.239.08:12:50.22#ibcon#read 5, iclass 5, count 0 2006.239.08:12:50.22#ibcon#about to read 6, iclass 5, count 0 2006.239.08:12:50.22#ibcon#read 6, iclass 5, count 0 2006.239.08:12:50.22#ibcon#end of sib2, iclass 5, count 0 2006.239.08:12:50.22#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:12:50.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:12:50.22#ibcon#[27=USB\r\n] 2006.239.08:12:50.22#ibcon#*before write, iclass 5, count 0 2006.239.08:12:50.22#ibcon#enter sib2, iclass 5, count 0 2006.239.08:12:50.22#ibcon#flushed, iclass 5, count 0 2006.239.08:12:50.22#ibcon#about to write, iclass 5, count 0 2006.239.08:12:50.22#ibcon#wrote, iclass 5, count 0 2006.239.08:12:50.22#ibcon#about to read 3, iclass 5, count 0 2006.239.08:12:50.25#ibcon#read 3, iclass 5, count 0 2006.239.08:12:50.25#ibcon#about to read 4, iclass 5, count 0 2006.239.08:12:50.25#ibcon#read 4, iclass 5, count 0 2006.239.08:12:50.25#ibcon#about to read 5, iclass 5, count 0 2006.239.08:12:50.25#ibcon#read 5, iclass 5, count 0 2006.239.08:12:50.25#ibcon#about to read 6, iclass 5, count 0 2006.239.08:12:50.25#ibcon#read 6, iclass 5, count 0 2006.239.08:12:50.25#ibcon#end of sib2, iclass 5, count 0 2006.239.08:12:50.25#ibcon#*after write, iclass 5, count 0 2006.239.08:12:50.25#ibcon#*before return 0, iclass 5, count 0 2006.239.08:12:50.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:50.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:12:50.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:12:50.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:12:50.25$vc4f8/vblo=3,656.99 2006.239.08:12:50.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.08:12:50.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.08:12:50.25#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:50.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:50.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:50.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:50.25#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:12:50.25#ibcon#first serial, iclass 7, count 0 2006.239.08:12:50.25#ibcon#enter sib2, iclass 7, count 0 2006.239.08:12:50.25#ibcon#flushed, iclass 7, count 0 2006.239.08:12:50.25#ibcon#about to write, iclass 7, count 0 2006.239.08:12:50.25#ibcon#wrote, iclass 7, count 0 2006.239.08:12:50.25#ibcon#about to read 3, iclass 7, count 0 2006.239.08:12:50.27#ibcon#read 3, iclass 7, count 0 2006.239.08:12:50.27#ibcon#about to read 4, iclass 7, count 0 2006.239.08:12:50.27#ibcon#read 4, iclass 7, count 0 2006.239.08:12:50.27#ibcon#about to read 5, iclass 7, count 0 2006.239.08:12:50.27#ibcon#read 5, iclass 7, count 0 2006.239.08:12:50.27#ibcon#about to read 6, iclass 7, count 0 2006.239.08:12:50.27#ibcon#read 6, iclass 7, count 0 2006.239.08:12:50.27#ibcon#end of sib2, iclass 7, count 0 2006.239.08:12:50.27#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:12:50.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:12:50.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:12:50.27#ibcon#*before write, iclass 7, count 0 2006.239.08:12:50.27#ibcon#enter sib2, iclass 7, count 0 2006.239.08:12:50.27#ibcon#flushed, iclass 7, count 0 2006.239.08:12:50.27#ibcon#about to write, iclass 7, count 0 2006.239.08:12:50.27#ibcon#wrote, iclass 7, count 0 2006.239.08:12:50.27#ibcon#about to read 3, iclass 7, count 0 2006.239.08:12:50.31#ibcon#read 3, iclass 7, count 0 2006.239.08:12:50.31#ibcon#about to read 4, iclass 7, count 0 2006.239.08:12:50.31#ibcon#read 4, iclass 7, count 0 2006.239.08:12:50.31#ibcon#about to read 5, iclass 7, count 0 2006.239.08:12:50.31#ibcon#read 5, iclass 7, count 0 2006.239.08:12:50.31#ibcon#about to read 6, iclass 7, count 0 2006.239.08:12:50.31#ibcon#read 6, iclass 7, count 0 2006.239.08:12:50.31#ibcon#end of sib2, iclass 7, count 0 2006.239.08:12:50.31#ibcon#*after write, iclass 7, count 0 2006.239.08:12:50.31#ibcon#*before return 0, iclass 7, count 0 2006.239.08:12:50.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:50.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:12:50.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:12:50.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:12:50.31$vc4f8/vb=3,4 2006.239.08:12:50.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.08:12:50.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.08:12:50.31#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:50.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:50.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:50.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:50.37#ibcon#enter wrdev, iclass 11, count 2 2006.239.08:12:50.37#ibcon#first serial, iclass 11, count 2 2006.239.08:12:50.37#ibcon#enter sib2, iclass 11, count 2 2006.239.08:12:50.37#ibcon#flushed, iclass 11, count 2 2006.239.08:12:50.37#ibcon#about to write, iclass 11, count 2 2006.239.08:12:50.37#ibcon#wrote, iclass 11, count 2 2006.239.08:12:50.37#ibcon#about to read 3, iclass 11, count 2 2006.239.08:12:50.39#ibcon#read 3, iclass 11, count 2 2006.239.08:12:50.39#ibcon#about to read 4, iclass 11, count 2 2006.239.08:12:50.39#ibcon#read 4, iclass 11, count 2 2006.239.08:12:50.39#ibcon#about to read 5, iclass 11, count 2 2006.239.08:12:50.39#ibcon#read 5, iclass 11, count 2 2006.239.08:12:50.39#ibcon#about to read 6, iclass 11, count 2 2006.239.08:12:50.39#ibcon#read 6, iclass 11, count 2 2006.239.08:12:50.39#ibcon#end of sib2, iclass 11, count 2 2006.239.08:12:50.39#ibcon#*mode == 0, iclass 11, count 2 2006.239.08:12:50.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.08:12:50.39#ibcon#[27=AT03-04\r\n] 2006.239.08:12:50.39#ibcon#*before write, iclass 11, count 2 2006.239.08:12:50.39#ibcon#enter sib2, iclass 11, count 2 2006.239.08:12:50.39#ibcon#flushed, iclass 11, count 2 2006.239.08:12:50.39#ibcon#about to write, iclass 11, count 2 2006.239.08:12:50.39#ibcon#wrote, iclass 11, count 2 2006.239.08:12:50.39#ibcon#about to read 3, iclass 11, count 2 2006.239.08:12:50.42#ibcon#read 3, iclass 11, count 2 2006.239.08:12:50.42#ibcon#about to read 4, iclass 11, count 2 2006.239.08:12:50.42#ibcon#read 4, iclass 11, count 2 2006.239.08:12:50.42#ibcon#about to read 5, iclass 11, count 2 2006.239.08:12:50.42#ibcon#read 5, iclass 11, count 2 2006.239.08:12:50.42#ibcon#about to read 6, iclass 11, count 2 2006.239.08:12:50.42#ibcon#read 6, iclass 11, count 2 2006.239.08:12:50.42#ibcon#end of sib2, iclass 11, count 2 2006.239.08:12:50.42#ibcon#*after write, iclass 11, count 2 2006.239.08:12:50.42#ibcon#*before return 0, iclass 11, count 2 2006.239.08:12:50.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:50.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:12:50.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.08:12:50.42#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:50.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:50.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:50.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:50.54#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:12:50.54#ibcon#first serial, iclass 11, count 0 2006.239.08:12:50.54#ibcon#enter sib2, iclass 11, count 0 2006.239.08:12:50.54#ibcon#flushed, iclass 11, count 0 2006.239.08:12:50.54#ibcon#about to write, iclass 11, count 0 2006.239.08:12:50.54#ibcon#wrote, iclass 11, count 0 2006.239.08:12:50.54#ibcon#about to read 3, iclass 11, count 0 2006.239.08:12:50.56#ibcon#read 3, iclass 11, count 0 2006.239.08:12:50.56#ibcon#about to read 4, iclass 11, count 0 2006.239.08:12:50.56#ibcon#read 4, iclass 11, count 0 2006.239.08:12:50.56#ibcon#about to read 5, iclass 11, count 0 2006.239.08:12:50.56#ibcon#read 5, iclass 11, count 0 2006.239.08:12:50.56#ibcon#about to read 6, iclass 11, count 0 2006.239.08:12:50.56#ibcon#read 6, iclass 11, count 0 2006.239.08:12:50.56#ibcon#end of sib2, iclass 11, count 0 2006.239.08:12:50.56#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:12:50.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:12:50.56#ibcon#[27=USB\r\n] 2006.239.08:12:50.56#ibcon#*before write, iclass 11, count 0 2006.239.08:12:50.56#ibcon#enter sib2, iclass 11, count 0 2006.239.08:12:50.56#ibcon#flushed, iclass 11, count 0 2006.239.08:12:50.56#ibcon#about to write, iclass 11, count 0 2006.239.08:12:50.56#ibcon#wrote, iclass 11, count 0 2006.239.08:12:50.56#ibcon#about to read 3, iclass 11, count 0 2006.239.08:12:50.59#ibcon#read 3, iclass 11, count 0 2006.239.08:12:50.59#ibcon#about to read 4, iclass 11, count 0 2006.239.08:12:50.59#ibcon#read 4, iclass 11, count 0 2006.239.08:12:50.59#ibcon#about to read 5, iclass 11, count 0 2006.239.08:12:50.59#ibcon#read 5, iclass 11, count 0 2006.239.08:12:50.59#ibcon#about to read 6, iclass 11, count 0 2006.239.08:12:50.59#ibcon#read 6, iclass 11, count 0 2006.239.08:12:50.59#ibcon#end of sib2, iclass 11, count 0 2006.239.08:12:50.59#ibcon#*after write, iclass 11, count 0 2006.239.08:12:50.59#ibcon#*before return 0, iclass 11, count 0 2006.239.08:12:50.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:50.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:12:50.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:12:50.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:12:50.59$vc4f8/vblo=4,712.99 2006.239.08:12:50.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.08:12:50.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.08:12:50.59#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:50.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:50.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:50.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:50.59#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:12:50.59#ibcon#first serial, iclass 13, count 0 2006.239.08:12:50.59#ibcon#enter sib2, iclass 13, count 0 2006.239.08:12:50.59#ibcon#flushed, iclass 13, count 0 2006.239.08:12:50.59#ibcon#about to write, iclass 13, count 0 2006.239.08:12:50.59#ibcon#wrote, iclass 13, count 0 2006.239.08:12:50.59#ibcon#about to read 3, iclass 13, count 0 2006.239.08:12:50.61#ibcon#read 3, iclass 13, count 0 2006.239.08:12:50.61#ibcon#about to read 4, iclass 13, count 0 2006.239.08:12:50.61#ibcon#read 4, iclass 13, count 0 2006.239.08:12:50.61#ibcon#about to read 5, iclass 13, count 0 2006.239.08:12:50.61#ibcon#read 5, iclass 13, count 0 2006.239.08:12:50.61#ibcon#about to read 6, iclass 13, count 0 2006.239.08:12:50.61#ibcon#read 6, iclass 13, count 0 2006.239.08:12:50.61#ibcon#end of sib2, iclass 13, count 0 2006.239.08:12:50.61#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:12:50.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:12:50.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:12:50.61#ibcon#*before write, iclass 13, count 0 2006.239.08:12:50.61#ibcon#enter sib2, iclass 13, count 0 2006.239.08:12:50.61#ibcon#flushed, iclass 13, count 0 2006.239.08:12:50.61#ibcon#about to write, iclass 13, count 0 2006.239.08:12:50.61#ibcon#wrote, iclass 13, count 0 2006.239.08:12:50.61#ibcon#about to read 3, iclass 13, count 0 2006.239.08:12:50.65#ibcon#read 3, iclass 13, count 0 2006.239.08:12:50.65#ibcon#about to read 4, iclass 13, count 0 2006.239.08:12:50.65#ibcon#read 4, iclass 13, count 0 2006.239.08:12:50.65#ibcon#about to read 5, iclass 13, count 0 2006.239.08:12:50.65#ibcon#read 5, iclass 13, count 0 2006.239.08:12:50.65#ibcon#about to read 6, iclass 13, count 0 2006.239.08:12:50.65#ibcon#read 6, iclass 13, count 0 2006.239.08:12:50.65#ibcon#end of sib2, iclass 13, count 0 2006.239.08:12:50.65#ibcon#*after write, iclass 13, count 0 2006.239.08:12:50.65#ibcon#*before return 0, iclass 13, count 0 2006.239.08:12:50.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:50.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:12:50.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:12:50.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:12:50.65$vc4f8/vb=4,4 2006.239.08:12:50.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.08:12:50.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.08:12:50.65#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:50.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:50.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:50.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:50.72#ibcon#enter wrdev, iclass 15, count 2 2006.239.08:12:50.72#ibcon#first serial, iclass 15, count 2 2006.239.08:12:50.72#ibcon#enter sib2, iclass 15, count 2 2006.239.08:12:50.72#ibcon#flushed, iclass 15, count 2 2006.239.08:12:50.72#ibcon#about to write, iclass 15, count 2 2006.239.08:12:50.72#ibcon#wrote, iclass 15, count 2 2006.239.08:12:50.72#ibcon#about to read 3, iclass 15, count 2 2006.239.08:12:50.74#ibcon#read 3, iclass 15, count 2 2006.239.08:12:50.74#ibcon#about to read 4, iclass 15, count 2 2006.239.08:12:50.74#ibcon#read 4, iclass 15, count 2 2006.239.08:12:50.74#ibcon#about to read 5, iclass 15, count 2 2006.239.08:12:50.74#ibcon#read 5, iclass 15, count 2 2006.239.08:12:50.74#ibcon#about to read 6, iclass 15, count 2 2006.239.08:12:50.74#ibcon#read 6, iclass 15, count 2 2006.239.08:12:50.74#ibcon#end of sib2, iclass 15, count 2 2006.239.08:12:50.74#ibcon#*mode == 0, iclass 15, count 2 2006.239.08:12:50.74#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.08:12:50.74#ibcon#[27=AT04-04\r\n] 2006.239.08:12:50.74#ibcon#*before write, iclass 15, count 2 2006.239.08:12:50.74#ibcon#enter sib2, iclass 15, count 2 2006.239.08:12:50.74#ibcon#flushed, iclass 15, count 2 2006.239.08:12:50.74#ibcon#about to write, iclass 15, count 2 2006.239.08:12:50.74#ibcon#wrote, iclass 15, count 2 2006.239.08:12:50.74#ibcon#about to read 3, iclass 15, count 2 2006.239.08:12:50.76#ibcon#read 3, iclass 15, count 2 2006.239.08:12:50.76#ibcon#about to read 4, iclass 15, count 2 2006.239.08:12:50.76#ibcon#read 4, iclass 15, count 2 2006.239.08:12:50.76#ibcon#about to read 5, iclass 15, count 2 2006.239.08:12:50.76#ibcon#read 5, iclass 15, count 2 2006.239.08:12:50.76#ibcon#about to read 6, iclass 15, count 2 2006.239.08:12:50.76#ibcon#read 6, iclass 15, count 2 2006.239.08:12:50.76#ibcon#end of sib2, iclass 15, count 2 2006.239.08:12:50.76#ibcon#*after write, iclass 15, count 2 2006.239.08:12:50.76#ibcon#*before return 0, iclass 15, count 2 2006.239.08:12:50.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:50.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:12:50.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.08:12:50.76#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:50.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:50.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:50.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:50.88#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:12:50.88#ibcon#first serial, iclass 15, count 0 2006.239.08:12:50.88#ibcon#enter sib2, iclass 15, count 0 2006.239.08:12:50.88#ibcon#flushed, iclass 15, count 0 2006.239.08:12:50.88#ibcon#about to write, iclass 15, count 0 2006.239.08:12:50.88#ibcon#wrote, iclass 15, count 0 2006.239.08:12:50.88#ibcon#about to read 3, iclass 15, count 0 2006.239.08:12:50.91#ibcon#read 3, iclass 15, count 0 2006.239.08:12:50.91#ibcon#about to read 4, iclass 15, count 0 2006.239.08:12:50.91#ibcon#read 4, iclass 15, count 0 2006.239.08:12:50.91#ibcon#about to read 5, iclass 15, count 0 2006.239.08:12:50.91#ibcon#read 5, iclass 15, count 0 2006.239.08:12:50.91#ibcon#about to read 6, iclass 15, count 0 2006.239.08:12:50.91#ibcon#read 6, iclass 15, count 0 2006.239.08:12:50.91#ibcon#end of sib2, iclass 15, count 0 2006.239.08:12:50.91#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:12:50.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:12:50.91#ibcon#[27=USB\r\n] 2006.239.08:12:50.91#ibcon#*before write, iclass 15, count 0 2006.239.08:12:50.91#ibcon#enter sib2, iclass 15, count 0 2006.239.08:12:50.91#ibcon#flushed, iclass 15, count 0 2006.239.08:12:50.91#ibcon#about to write, iclass 15, count 0 2006.239.08:12:50.91#ibcon#wrote, iclass 15, count 0 2006.239.08:12:50.91#ibcon#about to read 3, iclass 15, count 0 2006.239.08:12:50.94#ibcon#read 3, iclass 15, count 0 2006.239.08:12:50.94#ibcon#about to read 4, iclass 15, count 0 2006.239.08:12:50.94#ibcon#read 4, iclass 15, count 0 2006.239.08:12:50.94#ibcon#about to read 5, iclass 15, count 0 2006.239.08:12:50.94#ibcon#read 5, iclass 15, count 0 2006.239.08:12:50.94#ibcon#about to read 6, iclass 15, count 0 2006.239.08:12:50.94#ibcon#read 6, iclass 15, count 0 2006.239.08:12:50.94#ibcon#end of sib2, iclass 15, count 0 2006.239.08:12:50.94#ibcon#*after write, iclass 15, count 0 2006.239.08:12:50.94#ibcon#*before return 0, iclass 15, count 0 2006.239.08:12:50.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:50.94#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:12:50.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:12:50.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:12:50.94$vc4f8/vblo=5,744.99 2006.239.08:12:50.94#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.08:12:50.94#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.08:12:50.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:50.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:50.94#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:50.94#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:50.94#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:12:50.94#ibcon#first serial, iclass 17, count 0 2006.239.08:12:50.94#ibcon#enter sib2, iclass 17, count 0 2006.239.08:12:50.94#ibcon#flushed, iclass 17, count 0 2006.239.08:12:50.94#ibcon#about to write, iclass 17, count 0 2006.239.08:12:50.94#ibcon#wrote, iclass 17, count 0 2006.239.08:12:50.94#ibcon#about to read 3, iclass 17, count 0 2006.239.08:12:50.96#ibcon#read 3, iclass 17, count 0 2006.239.08:12:50.96#ibcon#about to read 4, iclass 17, count 0 2006.239.08:12:50.96#ibcon#read 4, iclass 17, count 0 2006.239.08:12:50.96#ibcon#about to read 5, iclass 17, count 0 2006.239.08:12:50.96#ibcon#read 5, iclass 17, count 0 2006.239.08:12:50.96#ibcon#about to read 6, iclass 17, count 0 2006.239.08:12:50.96#ibcon#read 6, iclass 17, count 0 2006.239.08:12:50.96#ibcon#end of sib2, iclass 17, count 0 2006.239.08:12:50.96#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:12:50.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:12:50.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:12:50.96#ibcon#*before write, iclass 17, count 0 2006.239.08:12:50.96#ibcon#enter sib2, iclass 17, count 0 2006.239.08:12:50.96#ibcon#flushed, iclass 17, count 0 2006.239.08:12:50.96#ibcon#about to write, iclass 17, count 0 2006.239.08:12:50.96#ibcon#wrote, iclass 17, count 0 2006.239.08:12:50.96#ibcon#about to read 3, iclass 17, count 0 2006.239.08:12:51.00#ibcon#read 3, iclass 17, count 0 2006.239.08:12:51.00#ibcon#about to read 4, iclass 17, count 0 2006.239.08:12:51.00#ibcon#read 4, iclass 17, count 0 2006.239.08:12:51.00#ibcon#about to read 5, iclass 17, count 0 2006.239.08:12:51.00#ibcon#read 5, iclass 17, count 0 2006.239.08:12:51.00#ibcon#about to read 6, iclass 17, count 0 2006.239.08:12:51.00#ibcon#read 6, iclass 17, count 0 2006.239.08:12:51.00#ibcon#end of sib2, iclass 17, count 0 2006.239.08:12:51.00#ibcon#*after write, iclass 17, count 0 2006.239.08:12:51.00#ibcon#*before return 0, iclass 17, count 0 2006.239.08:12:51.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:51.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:12:51.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:12:51.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:12:51.00$vc4f8/vb=5,4 2006.239.08:12:51.00#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.08:12:51.00#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.08:12:51.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:51.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:51.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:51.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:51.06#ibcon#enter wrdev, iclass 19, count 2 2006.239.08:12:51.06#ibcon#first serial, iclass 19, count 2 2006.239.08:12:51.06#ibcon#enter sib2, iclass 19, count 2 2006.239.08:12:51.06#ibcon#flushed, iclass 19, count 2 2006.239.08:12:51.06#ibcon#about to write, iclass 19, count 2 2006.239.08:12:51.06#ibcon#wrote, iclass 19, count 2 2006.239.08:12:51.06#ibcon#about to read 3, iclass 19, count 2 2006.239.08:12:51.08#ibcon#read 3, iclass 19, count 2 2006.239.08:12:51.08#ibcon#about to read 4, iclass 19, count 2 2006.239.08:12:51.08#ibcon#read 4, iclass 19, count 2 2006.239.08:12:51.08#ibcon#about to read 5, iclass 19, count 2 2006.239.08:12:51.08#ibcon#read 5, iclass 19, count 2 2006.239.08:12:51.08#ibcon#about to read 6, iclass 19, count 2 2006.239.08:12:51.08#ibcon#read 6, iclass 19, count 2 2006.239.08:12:51.08#ibcon#end of sib2, iclass 19, count 2 2006.239.08:12:51.08#ibcon#*mode == 0, iclass 19, count 2 2006.239.08:12:51.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.08:12:51.08#ibcon#[27=AT05-04\r\n] 2006.239.08:12:51.08#ibcon#*before write, iclass 19, count 2 2006.239.08:12:51.08#ibcon#enter sib2, iclass 19, count 2 2006.239.08:12:51.08#ibcon#flushed, iclass 19, count 2 2006.239.08:12:51.08#ibcon#about to write, iclass 19, count 2 2006.239.08:12:51.08#ibcon#wrote, iclass 19, count 2 2006.239.08:12:51.08#ibcon#about to read 3, iclass 19, count 2 2006.239.08:12:51.11#ibcon#read 3, iclass 19, count 2 2006.239.08:12:51.11#ibcon#about to read 4, iclass 19, count 2 2006.239.08:12:51.11#ibcon#read 4, iclass 19, count 2 2006.239.08:12:51.11#ibcon#about to read 5, iclass 19, count 2 2006.239.08:12:51.11#ibcon#read 5, iclass 19, count 2 2006.239.08:12:51.11#ibcon#about to read 6, iclass 19, count 2 2006.239.08:12:51.11#ibcon#read 6, iclass 19, count 2 2006.239.08:12:51.11#ibcon#end of sib2, iclass 19, count 2 2006.239.08:12:51.11#ibcon#*after write, iclass 19, count 2 2006.239.08:12:51.11#ibcon#*before return 0, iclass 19, count 2 2006.239.08:12:51.11#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:51.11#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:12:51.11#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.08:12:51.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:51.11#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:51.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:51.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:51.23#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:12:51.23#ibcon#first serial, iclass 19, count 0 2006.239.08:12:51.23#ibcon#enter sib2, iclass 19, count 0 2006.239.08:12:51.23#ibcon#flushed, iclass 19, count 0 2006.239.08:12:51.23#ibcon#about to write, iclass 19, count 0 2006.239.08:12:51.23#ibcon#wrote, iclass 19, count 0 2006.239.08:12:51.23#ibcon#about to read 3, iclass 19, count 0 2006.239.08:12:51.25#ibcon#read 3, iclass 19, count 0 2006.239.08:12:51.25#ibcon#about to read 4, iclass 19, count 0 2006.239.08:12:51.25#ibcon#read 4, iclass 19, count 0 2006.239.08:12:51.25#ibcon#about to read 5, iclass 19, count 0 2006.239.08:12:51.25#ibcon#read 5, iclass 19, count 0 2006.239.08:12:51.25#ibcon#about to read 6, iclass 19, count 0 2006.239.08:12:51.25#ibcon#read 6, iclass 19, count 0 2006.239.08:12:51.25#ibcon#end of sib2, iclass 19, count 0 2006.239.08:12:51.25#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:12:51.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:12:51.25#ibcon#[27=USB\r\n] 2006.239.08:12:51.25#ibcon#*before write, iclass 19, count 0 2006.239.08:12:51.25#ibcon#enter sib2, iclass 19, count 0 2006.239.08:12:51.25#ibcon#flushed, iclass 19, count 0 2006.239.08:12:51.25#ibcon#about to write, iclass 19, count 0 2006.239.08:12:51.25#ibcon#wrote, iclass 19, count 0 2006.239.08:12:51.25#ibcon#about to read 3, iclass 19, count 0 2006.239.08:12:51.28#ibcon#read 3, iclass 19, count 0 2006.239.08:12:51.28#ibcon#about to read 4, iclass 19, count 0 2006.239.08:12:51.28#ibcon#read 4, iclass 19, count 0 2006.239.08:12:51.28#ibcon#about to read 5, iclass 19, count 0 2006.239.08:12:51.28#ibcon#read 5, iclass 19, count 0 2006.239.08:12:51.28#ibcon#about to read 6, iclass 19, count 0 2006.239.08:12:51.28#ibcon#read 6, iclass 19, count 0 2006.239.08:12:51.28#ibcon#end of sib2, iclass 19, count 0 2006.239.08:12:51.28#ibcon#*after write, iclass 19, count 0 2006.239.08:12:51.28#ibcon#*before return 0, iclass 19, count 0 2006.239.08:12:51.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:51.28#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:12:51.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:12:51.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:12:51.28$vc4f8/vblo=6,752.99 2006.239.08:12:51.28#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:12:51.28#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:12:51.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:12:51.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:51.28#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:51.28#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:51.28#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:12:51.28#ibcon#first serial, iclass 21, count 0 2006.239.08:12:51.28#ibcon#enter sib2, iclass 21, count 0 2006.239.08:12:51.28#ibcon#flushed, iclass 21, count 0 2006.239.08:12:51.28#ibcon#about to write, iclass 21, count 0 2006.239.08:12:51.28#ibcon#wrote, iclass 21, count 0 2006.239.08:12:51.28#ibcon#about to read 3, iclass 21, count 0 2006.239.08:12:51.30#ibcon#read 3, iclass 21, count 0 2006.239.08:12:51.30#ibcon#about to read 4, iclass 21, count 0 2006.239.08:12:51.30#ibcon#read 4, iclass 21, count 0 2006.239.08:12:51.30#ibcon#about to read 5, iclass 21, count 0 2006.239.08:12:51.30#ibcon#read 5, iclass 21, count 0 2006.239.08:12:51.30#ibcon#about to read 6, iclass 21, count 0 2006.239.08:12:51.30#ibcon#read 6, iclass 21, count 0 2006.239.08:12:51.30#ibcon#end of sib2, iclass 21, count 0 2006.239.08:12:51.30#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:12:51.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:12:51.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:12:51.30#ibcon#*before write, iclass 21, count 0 2006.239.08:12:51.30#ibcon#enter sib2, iclass 21, count 0 2006.239.08:12:51.30#ibcon#flushed, iclass 21, count 0 2006.239.08:12:51.30#ibcon#about to write, iclass 21, count 0 2006.239.08:12:51.30#ibcon#wrote, iclass 21, count 0 2006.239.08:12:51.30#ibcon#about to read 3, iclass 21, count 0 2006.239.08:12:51.34#ibcon#read 3, iclass 21, count 0 2006.239.08:12:51.34#ibcon#about to read 4, iclass 21, count 0 2006.239.08:12:51.34#ibcon#read 4, iclass 21, count 0 2006.239.08:12:51.34#ibcon#about to read 5, iclass 21, count 0 2006.239.08:12:51.34#ibcon#read 5, iclass 21, count 0 2006.239.08:12:51.34#ibcon#about to read 6, iclass 21, count 0 2006.239.08:12:51.34#ibcon#read 6, iclass 21, count 0 2006.239.08:12:51.34#ibcon#end of sib2, iclass 21, count 0 2006.239.08:12:51.34#ibcon#*after write, iclass 21, count 0 2006.239.08:12:51.34#ibcon#*before return 0, iclass 21, count 0 2006.239.08:12:51.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:51.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:12:51.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:12:51.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:12:51.34$vc4f8/vb=6,4 2006.239.08:12:51.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.08:12:51.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.08:12:51.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:12:51.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:51.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:51.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:51.40#ibcon#enter wrdev, iclass 23, count 2 2006.239.08:12:51.40#ibcon#first serial, iclass 23, count 2 2006.239.08:12:51.40#ibcon#enter sib2, iclass 23, count 2 2006.239.08:12:51.40#ibcon#flushed, iclass 23, count 2 2006.239.08:12:51.40#ibcon#about to write, iclass 23, count 2 2006.239.08:12:51.40#ibcon#wrote, iclass 23, count 2 2006.239.08:12:51.40#ibcon#about to read 3, iclass 23, count 2 2006.239.08:12:51.42#ibcon#read 3, iclass 23, count 2 2006.239.08:12:51.42#ibcon#about to read 4, iclass 23, count 2 2006.239.08:12:51.42#ibcon#read 4, iclass 23, count 2 2006.239.08:12:51.42#ibcon#about to read 5, iclass 23, count 2 2006.239.08:12:51.42#ibcon#read 5, iclass 23, count 2 2006.239.08:12:51.42#ibcon#about to read 6, iclass 23, count 2 2006.239.08:12:51.42#ibcon#read 6, iclass 23, count 2 2006.239.08:12:51.42#ibcon#end of sib2, iclass 23, count 2 2006.239.08:12:51.42#ibcon#*mode == 0, iclass 23, count 2 2006.239.08:12:51.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.08:12:51.42#ibcon#[27=AT06-04\r\n] 2006.239.08:12:51.42#ibcon#*before write, iclass 23, count 2 2006.239.08:12:51.42#ibcon#enter sib2, iclass 23, count 2 2006.239.08:12:51.42#ibcon#flushed, iclass 23, count 2 2006.239.08:12:51.42#ibcon#about to write, iclass 23, count 2 2006.239.08:12:51.42#ibcon#wrote, iclass 23, count 2 2006.239.08:12:51.42#ibcon#about to read 3, iclass 23, count 2 2006.239.08:12:51.45#ibcon#read 3, iclass 23, count 2 2006.239.08:12:51.45#ibcon#about to read 4, iclass 23, count 2 2006.239.08:12:51.45#ibcon#read 4, iclass 23, count 2 2006.239.08:12:51.45#ibcon#about to read 5, iclass 23, count 2 2006.239.08:12:51.45#ibcon#read 5, iclass 23, count 2 2006.239.08:12:51.45#ibcon#about to read 6, iclass 23, count 2 2006.239.08:12:51.45#ibcon#read 6, iclass 23, count 2 2006.239.08:12:51.45#ibcon#end of sib2, iclass 23, count 2 2006.239.08:12:51.45#ibcon#*after write, iclass 23, count 2 2006.239.08:12:51.45#ibcon#*before return 0, iclass 23, count 2 2006.239.08:12:51.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:51.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:12:51.45#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.08:12:51.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:12:51.45#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:51.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:51.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:51.57#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:12:51.57#ibcon#first serial, iclass 23, count 0 2006.239.08:12:51.57#ibcon#enter sib2, iclass 23, count 0 2006.239.08:12:51.57#ibcon#flushed, iclass 23, count 0 2006.239.08:12:51.57#ibcon#about to write, iclass 23, count 0 2006.239.08:12:51.57#ibcon#wrote, iclass 23, count 0 2006.239.08:12:51.57#ibcon#about to read 3, iclass 23, count 0 2006.239.08:12:51.59#ibcon#read 3, iclass 23, count 0 2006.239.08:12:51.59#ibcon#about to read 4, iclass 23, count 0 2006.239.08:12:51.59#ibcon#read 4, iclass 23, count 0 2006.239.08:12:51.59#ibcon#about to read 5, iclass 23, count 0 2006.239.08:12:51.59#ibcon#read 5, iclass 23, count 0 2006.239.08:12:51.59#ibcon#about to read 6, iclass 23, count 0 2006.239.08:12:51.59#ibcon#read 6, iclass 23, count 0 2006.239.08:12:51.59#ibcon#end of sib2, iclass 23, count 0 2006.239.08:12:51.59#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:12:51.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:12:51.59#ibcon#[27=USB\r\n] 2006.239.08:12:51.59#ibcon#*before write, iclass 23, count 0 2006.239.08:12:51.59#ibcon#enter sib2, iclass 23, count 0 2006.239.08:12:51.59#ibcon#flushed, iclass 23, count 0 2006.239.08:12:51.59#ibcon#about to write, iclass 23, count 0 2006.239.08:12:51.59#ibcon#wrote, iclass 23, count 0 2006.239.08:12:51.59#ibcon#about to read 3, iclass 23, count 0 2006.239.08:12:51.62#ibcon#read 3, iclass 23, count 0 2006.239.08:12:51.62#ibcon#about to read 4, iclass 23, count 0 2006.239.08:12:51.62#ibcon#read 4, iclass 23, count 0 2006.239.08:12:51.62#ibcon#about to read 5, iclass 23, count 0 2006.239.08:12:51.62#ibcon#read 5, iclass 23, count 0 2006.239.08:12:51.62#ibcon#about to read 6, iclass 23, count 0 2006.239.08:12:51.62#ibcon#read 6, iclass 23, count 0 2006.239.08:12:51.62#ibcon#end of sib2, iclass 23, count 0 2006.239.08:12:51.62#ibcon#*after write, iclass 23, count 0 2006.239.08:12:51.62#ibcon#*before return 0, iclass 23, count 0 2006.239.08:12:51.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:51.62#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:12:51.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:12:51.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:12:51.62$vc4f8/vabw=wide 2006.239.08:12:51.62#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.08:12:51.62#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.08:12:51.62#ibcon#ireg 8 cls_cnt 0 2006.239.08:12:51.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:51.62#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:51.62#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:51.62#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:12:51.62#ibcon#first serial, iclass 25, count 0 2006.239.08:12:51.62#ibcon#enter sib2, iclass 25, count 0 2006.239.08:12:51.62#ibcon#flushed, iclass 25, count 0 2006.239.08:12:51.62#ibcon#about to write, iclass 25, count 0 2006.239.08:12:51.62#ibcon#wrote, iclass 25, count 0 2006.239.08:12:51.62#ibcon#about to read 3, iclass 25, count 0 2006.239.08:12:51.66#ibcon#read 3, iclass 25, count 0 2006.239.08:12:51.66#ibcon#about to read 4, iclass 25, count 0 2006.239.08:12:51.66#ibcon#read 4, iclass 25, count 0 2006.239.08:12:51.66#ibcon#about to read 5, iclass 25, count 0 2006.239.08:12:51.66#ibcon#read 5, iclass 25, count 0 2006.239.08:12:51.66#ibcon#about to read 6, iclass 25, count 0 2006.239.08:12:51.66#ibcon#read 6, iclass 25, count 0 2006.239.08:12:51.66#ibcon#end of sib2, iclass 25, count 0 2006.239.08:12:51.66#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:12:51.66#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:12:51.66#ibcon#[25=BW32\r\n] 2006.239.08:12:51.66#ibcon#*before write, iclass 25, count 0 2006.239.08:12:51.66#ibcon#enter sib2, iclass 25, count 0 2006.239.08:12:51.66#ibcon#flushed, iclass 25, count 0 2006.239.08:12:51.66#ibcon#about to write, iclass 25, count 0 2006.239.08:12:51.66#ibcon#wrote, iclass 25, count 0 2006.239.08:12:51.66#ibcon#about to read 3, iclass 25, count 0 2006.239.08:12:51.68#ibcon#read 3, iclass 25, count 0 2006.239.08:12:51.68#ibcon#about to read 4, iclass 25, count 0 2006.239.08:12:51.68#ibcon#read 4, iclass 25, count 0 2006.239.08:12:51.68#ibcon#about to read 5, iclass 25, count 0 2006.239.08:12:51.68#ibcon#read 5, iclass 25, count 0 2006.239.08:12:51.68#ibcon#about to read 6, iclass 25, count 0 2006.239.08:12:51.68#ibcon#read 6, iclass 25, count 0 2006.239.08:12:51.68#ibcon#end of sib2, iclass 25, count 0 2006.239.08:12:51.68#ibcon#*after write, iclass 25, count 0 2006.239.08:12:51.68#ibcon#*before return 0, iclass 25, count 0 2006.239.08:12:51.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:51.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:12:51.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:12:51.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:12:51.68$vc4f8/vbbw=wide 2006.239.08:12:51.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.239.08:12:51.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.239.08:12:51.68#ibcon#ireg 8 cls_cnt 0 2006.239.08:12:51.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:12:51.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:12:51.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:12:51.74#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:12:51.74#ibcon#first serial, iclass 27, count 0 2006.239.08:12:51.74#ibcon#enter sib2, iclass 27, count 0 2006.239.08:12:51.74#ibcon#flushed, iclass 27, count 0 2006.239.08:12:51.74#ibcon#about to write, iclass 27, count 0 2006.239.08:12:51.74#ibcon#wrote, iclass 27, count 0 2006.239.08:12:51.74#ibcon#about to read 3, iclass 27, count 0 2006.239.08:12:51.76#ibcon#read 3, iclass 27, count 0 2006.239.08:12:51.76#ibcon#about to read 4, iclass 27, count 0 2006.239.08:12:51.76#ibcon#read 4, iclass 27, count 0 2006.239.08:12:51.76#ibcon#about to read 5, iclass 27, count 0 2006.239.08:12:51.76#ibcon#read 5, iclass 27, count 0 2006.239.08:12:51.76#ibcon#about to read 6, iclass 27, count 0 2006.239.08:12:51.76#ibcon#read 6, iclass 27, count 0 2006.239.08:12:51.76#ibcon#end of sib2, iclass 27, count 0 2006.239.08:12:51.76#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:12:51.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:12:51.76#ibcon#[27=BW32\r\n] 2006.239.08:12:51.76#ibcon#*before write, iclass 27, count 0 2006.239.08:12:51.76#ibcon#enter sib2, iclass 27, count 0 2006.239.08:12:51.76#ibcon#flushed, iclass 27, count 0 2006.239.08:12:51.76#ibcon#about to write, iclass 27, count 0 2006.239.08:12:51.76#ibcon#wrote, iclass 27, count 0 2006.239.08:12:51.76#ibcon#about to read 3, iclass 27, count 0 2006.239.08:12:51.79#ibcon#read 3, iclass 27, count 0 2006.239.08:12:51.79#ibcon#about to read 4, iclass 27, count 0 2006.239.08:12:51.79#ibcon#read 4, iclass 27, count 0 2006.239.08:12:51.79#ibcon#about to read 5, iclass 27, count 0 2006.239.08:12:51.79#ibcon#read 5, iclass 27, count 0 2006.239.08:12:51.79#ibcon#about to read 6, iclass 27, count 0 2006.239.08:12:51.79#ibcon#read 6, iclass 27, count 0 2006.239.08:12:51.79#ibcon#end of sib2, iclass 27, count 0 2006.239.08:12:51.79#ibcon#*after write, iclass 27, count 0 2006.239.08:12:51.79#ibcon#*before return 0, iclass 27, count 0 2006.239.08:12:51.79#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:12:51.79#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.239.08:12:51.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:12:51.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:12:51.79$4f8m12a/ifd4f 2006.239.08:12:51.79$ifd4f/lo= 2006.239.08:12:51.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:12:51.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:12:51.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:12:51.80$ifd4f/patch= 2006.239.08:12:51.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:12:51.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:12:51.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:12:51.80$4f8m12a/"form=m,16.000,1:2 2006.239.08:12:51.80$4f8m12a/"tpicd 2006.239.08:12:51.80$4f8m12a/echo=off 2006.239.08:12:51.80$4f8m12a/xlog=off 2006.239.08:12:51.80:!2006.239.08:13:20 2006.239.08:12:56.14#trakl#Source acquired 2006.239.08:12:57.14#flagr#flagr/antenna,acquired 2006.239.08:13:20.01:preob 2006.239.08:13:21.14/onsource/TRACKING 2006.239.08:13:21.14:!2006.239.08:13:30 2006.239.08:13:30.00:data_valid=on 2006.239.08:13:30.00:midob 2006.239.08:13:30.14/onsource/TRACKING 2006.239.08:13:30.14/wx/25.06,1011.5,80 2006.239.08:13:30.25/cable/+6.4149E-03 2006.239.08:13:31.34/va/01,08,usb,yes,31,32 2006.239.08:13:31.34/va/02,07,usb,yes,31,32 2006.239.08:13:31.34/va/03,07,usb,yes,29,29 2006.239.08:13:31.34/va/04,07,usb,yes,32,35 2006.239.08:13:31.34/va/05,08,usb,yes,29,31 2006.239.08:13:31.34/va/06,07,usb,yes,31,31 2006.239.08:13:31.34/va/07,07,usb,yes,31,31 2006.239.08:13:31.34/va/08,07,usb,yes,34,33 2006.239.08:13:31.57/valo/01,532.99,yes,locked 2006.239.08:13:31.57/valo/02,572.99,yes,locked 2006.239.08:13:31.57/valo/03,672.99,yes,locked 2006.239.08:13:31.57/valo/04,832.99,yes,locked 2006.239.08:13:31.57/valo/05,652.99,yes,locked 2006.239.08:13:31.57/valo/06,772.99,yes,locked 2006.239.08:13:31.57/valo/07,832.99,yes,locked 2006.239.08:13:31.57/valo/08,852.99,yes,locked 2006.239.08:13:32.66/vb/01,04,usb,yes,30,29 2006.239.08:13:32.66/vb/02,04,usb,yes,32,33 2006.239.08:13:32.66/vb/03,04,usb,yes,28,32 2006.239.08:13:32.66/vb/04,04,usb,yes,29,29 2006.239.08:13:32.66/vb/05,04,usb,yes,28,32 2006.239.08:13:32.66/vb/06,04,usb,yes,29,31 2006.239.08:13:32.66/vb/07,04,usb,yes,31,31 2006.239.08:13:32.66/vb/08,04,usb,yes,28,32 2006.239.08:13:32.90/vblo/01,632.99,yes,locked 2006.239.08:13:32.90/vblo/02,640.99,yes,locked 2006.239.08:13:32.90/vblo/03,656.99,yes,locked 2006.239.08:13:32.90/vblo/04,712.99,yes,locked 2006.239.08:13:32.90/vblo/05,744.99,yes,locked 2006.239.08:13:32.90/vblo/06,752.99,yes,locked 2006.239.08:13:32.90/vblo/07,734.99,yes,locked 2006.239.08:13:32.90/vblo/08,744.99,yes,locked 2006.239.08:13:33.05/vabw/8 2006.239.08:13:33.20/vbbw/8 2006.239.08:13:33.30/xfe/off,on,13.5 2006.239.08:13:33.67/ifatt/23,28,28,28 2006.239.08:13:34.08/fmout-gps/S +4.41E-07 2006.239.08:13:34.13:!2006.239.08:14:30 2006.239.08:14:30.01:data_valid=off 2006.239.08:14:30.02:postob 2006.239.08:14:30.18/cable/+6.4148E-03 2006.239.08:14:30.19/wx/25.05,1011.5,80 2006.239.08:14:30.27/fmout-gps/S +4.42E-07 2006.239.08:14:30.28:scan_name=239-0815,k06239,60 2006.239.08:14:30.28:source=3c371,180650.68,694928.1,2000.0,cw 2006.239.08:14:32.13#flagr#flagr/antenna,new-source 2006.239.08:14:32.13:checkk5 2006.239.08:14:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:14:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:14:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:14:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:14:34.03/chk_obsdata//k5ts1/T2390813??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:14:34.40/chk_obsdata//k5ts2/T2390813??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:14:34.77/chk_obsdata//k5ts3/T2390813??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:14:35.14/chk_obsdata//k5ts4/T2390813??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.239.08:14:35.84/k5log//k5ts1_log_newline 2006.239.08:14:36.55/k5log//k5ts2_log_newline 2006.239.08:14:37.26/k5log//k5ts3_log_newline 2006.239.08:14:37.96/k5log//k5ts4_log_newline 2006.239.08:14:37.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:14:37.99:4f8m12a=2 2006.239.08:14:37.99$4f8m12a/echo=on 2006.239.08:14:37.99$4f8m12a/pcalon 2006.239.08:14:37.99$pcalon/"no phase cal control is implemented here 2006.239.08:14:37.99$4f8m12a/"tpicd=stop 2006.239.08:14:37.99$4f8m12a/vc4f8 2006.239.08:14:37.99$vc4f8/valo=1,532.99 2006.239.08:14:37.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.08:14:37.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.08:14:37.99#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:37.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:37.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:37.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:37.99#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:14:37.99#ibcon#first serial, iclass 34, count 0 2006.239.08:14:37.99#ibcon#enter sib2, iclass 34, count 0 2006.239.08:14:37.99#ibcon#flushed, iclass 34, count 0 2006.239.08:14:37.99#ibcon#about to write, iclass 34, count 0 2006.239.08:14:37.99#ibcon#wrote, iclass 34, count 0 2006.239.08:14:37.99#ibcon#about to read 3, iclass 34, count 0 2006.239.08:14:38.00#ibcon#read 3, iclass 34, count 0 2006.239.08:14:38.00#ibcon#about to read 4, iclass 34, count 0 2006.239.08:14:38.00#ibcon#read 4, iclass 34, count 0 2006.239.08:14:38.00#ibcon#about to read 5, iclass 34, count 0 2006.239.08:14:38.00#ibcon#read 5, iclass 34, count 0 2006.239.08:14:38.00#ibcon#about to read 6, iclass 34, count 0 2006.239.08:14:38.00#ibcon#read 6, iclass 34, count 0 2006.239.08:14:38.00#ibcon#end of sib2, iclass 34, count 0 2006.239.08:14:38.00#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:14:38.00#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:14:38.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:14:38.00#ibcon#*before write, iclass 34, count 0 2006.239.08:14:38.00#ibcon#enter sib2, iclass 34, count 0 2006.239.08:14:38.00#ibcon#flushed, iclass 34, count 0 2006.239.08:14:38.00#ibcon#about to write, iclass 34, count 0 2006.239.08:14:38.00#ibcon#wrote, iclass 34, count 0 2006.239.08:14:38.00#ibcon#about to read 3, iclass 34, count 0 2006.239.08:14:38.05#ibcon#read 3, iclass 34, count 0 2006.239.08:14:38.05#ibcon#about to read 4, iclass 34, count 0 2006.239.08:14:38.05#ibcon#read 4, iclass 34, count 0 2006.239.08:14:38.05#ibcon#about to read 5, iclass 34, count 0 2006.239.08:14:38.05#ibcon#read 5, iclass 34, count 0 2006.239.08:14:38.05#ibcon#about to read 6, iclass 34, count 0 2006.239.08:14:38.05#ibcon#read 6, iclass 34, count 0 2006.239.08:14:38.05#ibcon#end of sib2, iclass 34, count 0 2006.239.08:14:38.05#ibcon#*after write, iclass 34, count 0 2006.239.08:14:38.05#ibcon#*before return 0, iclass 34, count 0 2006.239.08:14:38.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:38.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:38.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:14:38.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:14:38.05$vc4f8/va=1,8 2006.239.08:14:38.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.08:14:38.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.08:14:38.05#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:38.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:38.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:38.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:38.05#ibcon#enter wrdev, iclass 36, count 2 2006.239.08:14:38.05#ibcon#first serial, iclass 36, count 2 2006.239.08:14:38.05#ibcon#enter sib2, iclass 36, count 2 2006.239.08:14:38.05#ibcon#flushed, iclass 36, count 2 2006.239.08:14:38.05#ibcon#about to write, iclass 36, count 2 2006.239.08:14:38.05#ibcon#wrote, iclass 36, count 2 2006.239.08:14:38.05#ibcon#about to read 3, iclass 36, count 2 2006.239.08:14:38.07#ibcon#read 3, iclass 36, count 2 2006.239.08:14:38.07#ibcon#about to read 4, iclass 36, count 2 2006.239.08:14:38.07#ibcon#read 4, iclass 36, count 2 2006.239.08:14:38.07#ibcon#about to read 5, iclass 36, count 2 2006.239.08:14:38.07#ibcon#read 5, iclass 36, count 2 2006.239.08:14:38.07#ibcon#about to read 6, iclass 36, count 2 2006.239.08:14:38.07#ibcon#read 6, iclass 36, count 2 2006.239.08:14:38.07#ibcon#end of sib2, iclass 36, count 2 2006.239.08:14:38.07#ibcon#*mode == 0, iclass 36, count 2 2006.239.08:14:38.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.08:14:38.07#ibcon#[25=AT01-08\r\n] 2006.239.08:14:38.07#ibcon#*before write, iclass 36, count 2 2006.239.08:14:38.07#ibcon#enter sib2, iclass 36, count 2 2006.239.08:14:38.07#ibcon#flushed, iclass 36, count 2 2006.239.08:14:38.07#ibcon#about to write, iclass 36, count 2 2006.239.08:14:38.07#ibcon#wrote, iclass 36, count 2 2006.239.08:14:38.07#ibcon#about to read 3, iclass 36, count 2 2006.239.08:14:38.10#ibcon#read 3, iclass 36, count 2 2006.239.08:14:38.10#ibcon#about to read 4, iclass 36, count 2 2006.239.08:14:38.10#ibcon#read 4, iclass 36, count 2 2006.239.08:14:38.10#ibcon#about to read 5, iclass 36, count 2 2006.239.08:14:38.10#ibcon#read 5, iclass 36, count 2 2006.239.08:14:38.10#ibcon#about to read 6, iclass 36, count 2 2006.239.08:14:38.10#ibcon#read 6, iclass 36, count 2 2006.239.08:14:38.10#ibcon#end of sib2, iclass 36, count 2 2006.239.08:14:38.10#ibcon#*after write, iclass 36, count 2 2006.239.08:14:38.10#ibcon#*before return 0, iclass 36, count 2 2006.239.08:14:38.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:38.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:38.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.08:14:38.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:38.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:38.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:38.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:38.22#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:14:38.22#ibcon#first serial, iclass 36, count 0 2006.239.08:14:38.22#ibcon#enter sib2, iclass 36, count 0 2006.239.08:14:38.22#ibcon#flushed, iclass 36, count 0 2006.239.08:14:38.22#ibcon#about to write, iclass 36, count 0 2006.239.08:14:38.22#ibcon#wrote, iclass 36, count 0 2006.239.08:14:38.22#ibcon#about to read 3, iclass 36, count 0 2006.239.08:14:38.24#ibcon#read 3, iclass 36, count 0 2006.239.08:14:38.24#ibcon#about to read 4, iclass 36, count 0 2006.239.08:14:38.24#ibcon#read 4, iclass 36, count 0 2006.239.08:14:38.24#ibcon#about to read 5, iclass 36, count 0 2006.239.08:14:38.24#ibcon#read 5, iclass 36, count 0 2006.239.08:14:38.24#ibcon#about to read 6, iclass 36, count 0 2006.239.08:14:38.24#ibcon#read 6, iclass 36, count 0 2006.239.08:14:38.24#ibcon#end of sib2, iclass 36, count 0 2006.239.08:14:38.24#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:14:38.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:14:38.24#ibcon#[25=USB\r\n] 2006.239.08:14:38.24#ibcon#*before write, iclass 36, count 0 2006.239.08:14:38.24#ibcon#enter sib2, iclass 36, count 0 2006.239.08:14:38.24#ibcon#flushed, iclass 36, count 0 2006.239.08:14:38.24#ibcon#about to write, iclass 36, count 0 2006.239.08:14:38.24#ibcon#wrote, iclass 36, count 0 2006.239.08:14:38.24#ibcon#about to read 3, iclass 36, count 0 2006.239.08:14:38.27#ibcon#read 3, iclass 36, count 0 2006.239.08:14:38.27#ibcon#about to read 4, iclass 36, count 0 2006.239.08:14:38.27#ibcon#read 4, iclass 36, count 0 2006.239.08:14:38.27#ibcon#about to read 5, iclass 36, count 0 2006.239.08:14:38.27#ibcon#read 5, iclass 36, count 0 2006.239.08:14:38.27#ibcon#about to read 6, iclass 36, count 0 2006.239.08:14:38.27#ibcon#read 6, iclass 36, count 0 2006.239.08:14:38.27#ibcon#end of sib2, iclass 36, count 0 2006.239.08:14:38.27#ibcon#*after write, iclass 36, count 0 2006.239.08:14:38.27#ibcon#*before return 0, iclass 36, count 0 2006.239.08:14:38.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:38.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:38.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:14:38.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:14:38.27$vc4f8/valo=2,572.99 2006.239.08:14:38.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.08:14:38.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.08:14:38.27#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:38.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:38.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:38.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:38.27#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:14:38.27#ibcon#first serial, iclass 38, count 0 2006.239.08:14:38.27#ibcon#enter sib2, iclass 38, count 0 2006.239.08:14:38.27#ibcon#flushed, iclass 38, count 0 2006.239.08:14:38.27#ibcon#about to write, iclass 38, count 0 2006.239.08:14:38.27#ibcon#wrote, iclass 38, count 0 2006.239.08:14:38.27#ibcon#about to read 3, iclass 38, count 0 2006.239.08:14:38.29#ibcon#read 3, iclass 38, count 0 2006.239.08:14:38.29#ibcon#about to read 4, iclass 38, count 0 2006.239.08:14:38.29#ibcon#read 4, iclass 38, count 0 2006.239.08:14:38.29#ibcon#about to read 5, iclass 38, count 0 2006.239.08:14:38.29#ibcon#read 5, iclass 38, count 0 2006.239.08:14:38.29#ibcon#about to read 6, iclass 38, count 0 2006.239.08:14:38.29#ibcon#read 6, iclass 38, count 0 2006.239.08:14:38.29#ibcon#end of sib2, iclass 38, count 0 2006.239.08:14:38.29#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:14:38.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:14:38.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:14:38.29#ibcon#*before write, iclass 38, count 0 2006.239.08:14:38.29#ibcon#enter sib2, iclass 38, count 0 2006.239.08:14:38.29#ibcon#flushed, iclass 38, count 0 2006.239.08:14:38.29#ibcon#about to write, iclass 38, count 0 2006.239.08:14:38.29#ibcon#wrote, iclass 38, count 0 2006.239.08:14:38.29#ibcon#about to read 3, iclass 38, count 0 2006.239.08:14:38.33#ibcon#read 3, iclass 38, count 0 2006.239.08:14:38.33#ibcon#about to read 4, iclass 38, count 0 2006.239.08:14:38.33#ibcon#read 4, iclass 38, count 0 2006.239.08:14:38.33#ibcon#about to read 5, iclass 38, count 0 2006.239.08:14:38.33#ibcon#read 5, iclass 38, count 0 2006.239.08:14:38.33#ibcon#about to read 6, iclass 38, count 0 2006.239.08:14:38.33#ibcon#read 6, iclass 38, count 0 2006.239.08:14:38.33#ibcon#end of sib2, iclass 38, count 0 2006.239.08:14:38.33#ibcon#*after write, iclass 38, count 0 2006.239.08:14:38.33#ibcon#*before return 0, iclass 38, count 0 2006.239.08:14:38.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:38.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:38.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:14:38.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:14:38.33$vc4f8/va=2,7 2006.239.08:14:38.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.08:14:38.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.08:14:38.33#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:38.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:38.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:38.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:38.40#ibcon#enter wrdev, iclass 40, count 2 2006.239.08:14:38.40#ibcon#first serial, iclass 40, count 2 2006.239.08:14:38.40#ibcon#enter sib2, iclass 40, count 2 2006.239.08:14:38.40#ibcon#flushed, iclass 40, count 2 2006.239.08:14:38.40#ibcon#about to write, iclass 40, count 2 2006.239.08:14:38.40#ibcon#wrote, iclass 40, count 2 2006.239.08:14:38.40#ibcon#about to read 3, iclass 40, count 2 2006.239.08:14:38.41#ibcon#read 3, iclass 40, count 2 2006.239.08:14:38.41#ibcon#about to read 4, iclass 40, count 2 2006.239.08:14:38.41#ibcon#read 4, iclass 40, count 2 2006.239.08:14:38.41#ibcon#about to read 5, iclass 40, count 2 2006.239.08:14:38.41#ibcon#read 5, iclass 40, count 2 2006.239.08:14:38.41#ibcon#about to read 6, iclass 40, count 2 2006.239.08:14:38.41#ibcon#read 6, iclass 40, count 2 2006.239.08:14:38.41#ibcon#end of sib2, iclass 40, count 2 2006.239.08:14:38.41#ibcon#*mode == 0, iclass 40, count 2 2006.239.08:14:38.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.08:14:38.41#ibcon#[25=AT02-07\r\n] 2006.239.08:14:38.41#ibcon#*before write, iclass 40, count 2 2006.239.08:14:38.41#ibcon#enter sib2, iclass 40, count 2 2006.239.08:14:38.41#ibcon#flushed, iclass 40, count 2 2006.239.08:14:38.41#ibcon#about to write, iclass 40, count 2 2006.239.08:14:38.41#ibcon#wrote, iclass 40, count 2 2006.239.08:14:38.41#ibcon#about to read 3, iclass 40, count 2 2006.239.08:14:38.44#ibcon#read 3, iclass 40, count 2 2006.239.08:14:38.44#ibcon#about to read 4, iclass 40, count 2 2006.239.08:14:38.44#ibcon#read 4, iclass 40, count 2 2006.239.08:14:38.44#ibcon#about to read 5, iclass 40, count 2 2006.239.08:14:38.44#ibcon#read 5, iclass 40, count 2 2006.239.08:14:38.44#ibcon#about to read 6, iclass 40, count 2 2006.239.08:14:38.44#ibcon#read 6, iclass 40, count 2 2006.239.08:14:38.44#ibcon#end of sib2, iclass 40, count 2 2006.239.08:14:38.44#ibcon#*after write, iclass 40, count 2 2006.239.08:14:38.44#ibcon#*before return 0, iclass 40, count 2 2006.239.08:14:38.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:38.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:38.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.08:14:38.44#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:38.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:38.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:38.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:38.56#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:14:38.56#ibcon#first serial, iclass 40, count 0 2006.239.08:14:38.56#ibcon#enter sib2, iclass 40, count 0 2006.239.08:14:38.56#ibcon#flushed, iclass 40, count 0 2006.239.08:14:38.56#ibcon#about to write, iclass 40, count 0 2006.239.08:14:38.56#ibcon#wrote, iclass 40, count 0 2006.239.08:14:38.56#ibcon#about to read 3, iclass 40, count 0 2006.239.08:14:38.58#ibcon#read 3, iclass 40, count 0 2006.239.08:14:38.58#ibcon#about to read 4, iclass 40, count 0 2006.239.08:14:38.58#ibcon#read 4, iclass 40, count 0 2006.239.08:14:38.58#ibcon#about to read 5, iclass 40, count 0 2006.239.08:14:38.58#ibcon#read 5, iclass 40, count 0 2006.239.08:14:38.58#ibcon#about to read 6, iclass 40, count 0 2006.239.08:14:38.58#ibcon#read 6, iclass 40, count 0 2006.239.08:14:38.58#ibcon#end of sib2, iclass 40, count 0 2006.239.08:14:38.58#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:14:38.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:14:38.58#ibcon#[25=USB\r\n] 2006.239.08:14:38.58#ibcon#*before write, iclass 40, count 0 2006.239.08:14:38.58#ibcon#enter sib2, iclass 40, count 0 2006.239.08:14:38.58#ibcon#flushed, iclass 40, count 0 2006.239.08:14:38.58#ibcon#about to write, iclass 40, count 0 2006.239.08:14:38.58#ibcon#wrote, iclass 40, count 0 2006.239.08:14:38.58#ibcon#about to read 3, iclass 40, count 0 2006.239.08:14:38.61#ibcon#read 3, iclass 40, count 0 2006.239.08:14:38.61#ibcon#about to read 4, iclass 40, count 0 2006.239.08:14:38.61#ibcon#read 4, iclass 40, count 0 2006.239.08:14:38.61#ibcon#about to read 5, iclass 40, count 0 2006.239.08:14:38.61#ibcon#read 5, iclass 40, count 0 2006.239.08:14:38.61#ibcon#about to read 6, iclass 40, count 0 2006.239.08:14:38.61#ibcon#read 6, iclass 40, count 0 2006.239.08:14:38.61#ibcon#end of sib2, iclass 40, count 0 2006.239.08:14:38.61#ibcon#*after write, iclass 40, count 0 2006.239.08:14:38.61#ibcon#*before return 0, iclass 40, count 0 2006.239.08:14:38.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:38.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:38.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:14:38.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:14:38.61$vc4f8/valo=3,672.99 2006.239.08:14:38.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:14:38.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:14:38.61#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:38.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:14:38.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:14:38.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:14:38.61#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:14:38.61#ibcon#first serial, iclass 5, count 0 2006.239.08:14:38.61#ibcon#enter sib2, iclass 5, count 0 2006.239.08:14:38.61#ibcon#flushed, iclass 5, count 0 2006.239.08:14:38.61#ibcon#about to write, iclass 5, count 0 2006.239.08:14:38.61#ibcon#wrote, iclass 5, count 0 2006.239.08:14:38.61#ibcon#about to read 3, iclass 5, count 0 2006.239.08:14:38.62#abcon#<5=/04 2.0 4.2 25.05 801011.5\r\n> 2006.239.08:14:38.63#ibcon#read 3, iclass 5, count 0 2006.239.08:14:38.63#ibcon#about to read 4, iclass 5, count 0 2006.239.08:14:38.63#ibcon#read 4, iclass 5, count 0 2006.239.08:14:38.63#ibcon#about to read 5, iclass 5, count 0 2006.239.08:14:38.63#ibcon#read 5, iclass 5, count 0 2006.239.08:14:38.63#ibcon#about to read 6, iclass 5, count 0 2006.239.08:14:38.63#ibcon#read 6, iclass 5, count 0 2006.239.08:14:38.63#ibcon#end of sib2, iclass 5, count 0 2006.239.08:14:38.63#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:14:38.63#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:14:38.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:14:38.63#ibcon#*before write, iclass 5, count 0 2006.239.08:14:38.63#ibcon#enter sib2, iclass 5, count 0 2006.239.08:14:38.63#ibcon#flushed, iclass 5, count 0 2006.239.08:14:38.63#ibcon#about to write, iclass 5, count 0 2006.239.08:14:38.63#ibcon#wrote, iclass 5, count 0 2006.239.08:14:38.63#ibcon#about to read 3, iclass 5, count 0 2006.239.08:14:38.65#abcon#{5=INTERFACE CLEAR} 2006.239.08:14:38.68#ibcon#read 3, iclass 5, count 0 2006.239.08:14:38.68#ibcon#about to read 4, iclass 5, count 0 2006.239.08:14:38.68#ibcon#read 4, iclass 5, count 0 2006.239.08:14:38.68#ibcon#about to read 5, iclass 5, count 0 2006.239.08:14:38.68#ibcon#read 5, iclass 5, count 0 2006.239.08:14:38.68#ibcon#about to read 6, iclass 5, count 0 2006.239.08:14:38.68#ibcon#read 6, iclass 5, count 0 2006.239.08:14:38.68#ibcon#end of sib2, iclass 5, count 0 2006.239.08:14:38.68#ibcon#*after write, iclass 5, count 0 2006.239.08:14:38.68#ibcon#*before return 0, iclass 5, count 0 2006.239.08:14:38.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:14:38.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:14:38.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:14:38.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:14:38.68$vc4f8/va=3,7 2006.239.08:14:38.68#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.08:14:38.68#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.08:14:38.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:38.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:14:38.70#abcon#[5=S1D000X0/0*\r\n] 2006.239.08:14:38.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:14:38.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:14:38.72#ibcon#enter wrdev, iclass 11, count 2 2006.239.08:14:38.72#ibcon#first serial, iclass 11, count 2 2006.239.08:14:38.72#ibcon#enter sib2, iclass 11, count 2 2006.239.08:14:38.72#ibcon#flushed, iclass 11, count 2 2006.239.08:14:38.72#ibcon#about to write, iclass 11, count 2 2006.239.08:14:38.72#ibcon#wrote, iclass 11, count 2 2006.239.08:14:38.72#ibcon#about to read 3, iclass 11, count 2 2006.239.08:14:38.75#ibcon#read 3, iclass 11, count 2 2006.239.08:14:38.75#ibcon#about to read 4, iclass 11, count 2 2006.239.08:14:38.75#ibcon#read 4, iclass 11, count 2 2006.239.08:14:38.75#ibcon#about to read 5, iclass 11, count 2 2006.239.08:14:38.75#ibcon#read 5, iclass 11, count 2 2006.239.08:14:38.75#ibcon#about to read 6, iclass 11, count 2 2006.239.08:14:38.75#ibcon#read 6, iclass 11, count 2 2006.239.08:14:38.75#ibcon#end of sib2, iclass 11, count 2 2006.239.08:14:38.75#ibcon#*mode == 0, iclass 11, count 2 2006.239.08:14:38.75#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.08:14:38.75#ibcon#[25=AT03-07\r\n] 2006.239.08:14:38.75#ibcon#*before write, iclass 11, count 2 2006.239.08:14:38.75#ibcon#enter sib2, iclass 11, count 2 2006.239.08:14:38.75#ibcon#flushed, iclass 11, count 2 2006.239.08:14:38.75#ibcon#about to write, iclass 11, count 2 2006.239.08:14:38.75#ibcon#wrote, iclass 11, count 2 2006.239.08:14:38.75#ibcon#about to read 3, iclass 11, count 2 2006.239.08:14:38.78#ibcon#read 3, iclass 11, count 2 2006.239.08:14:38.78#ibcon#about to read 4, iclass 11, count 2 2006.239.08:14:38.78#ibcon#read 4, iclass 11, count 2 2006.239.08:14:38.78#ibcon#about to read 5, iclass 11, count 2 2006.239.08:14:38.78#ibcon#read 5, iclass 11, count 2 2006.239.08:14:38.78#ibcon#about to read 6, iclass 11, count 2 2006.239.08:14:38.78#ibcon#read 6, iclass 11, count 2 2006.239.08:14:38.78#ibcon#end of sib2, iclass 11, count 2 2006.239.08:14:38.78#ibcon#*after write, iclass 11, count 2 2006.239.08:14:38.78#ibcon#*before return 0, iclass 11, count 2 2006.239.08:14:38.78#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:14:38.78#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:14:38.78#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.08:14:38.78#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:38.78#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:14:38.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:14:38.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:14:38.89#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:14:38.89#ibcon#first serial, iclass 11, count 0 2006.239.08:14:38.89#ibcon#enter sib2, iclass 11, count 0 2006.239.08:14:38.89#ibcon#flushed, iclass 11, count 0 2006.239.08:14:38.89#ibcon#about to write, iclass 11, count 0 2006.239.08:14:38.89#ibcon#wrote, iclass 11, count 0 2006.239.08:14:38.89#ibcon#about to read 3, iclass 11, count 0 2006.239.08:14:38.91#ibcon#read 3, iclass 11, count 0 2006.239.08:14:38.91#ibcon#about to read 4, iclass 11, count 0 2006.239.08:14:38.91#ibcon#read 4, iclass 11, count 0 2006.239.08:14:38.91#ibcon#about to read 5, iclass 11, count 0 2006.239.08:14:38.91#ibcon#read 5, iclass 11, count 0 2006.239.08:14:38.91#ibcon#about to read 6, iclass 11, count 0 2006.239.08:14:38.91#ibcon#read 6, iclass 11, count 0 2006.239.08:14:38.91#ibcon#end of sib2, iclass 11, count 0 2006.239.08:14:38.91#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:14:38.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:14:38.91#ibcon#[25=USB\r\n] 2006.239.08:14:38.91#ibcon#*before write, iclass 11, count 0 2006.239.08:14:38.91#ibcon#enter sib2, iclass 11, count 0 2006.239.08:14:38.91#ibcon#flushed, iclass 11, count 0 2006.239.08:14:38.91#ibcon#about to write, iclass 11, count 0 2006.239.08:14:38.91#ibcon#wrote, iclass 11, count 0 2006.239.08:14:38.91#ibcon#about to read 3, iclass 11, count 0 2006.239.08:14:38.94#ibcon#read 3, iclass 11, count 0 2006.239.08:14:38.94#ibcon#about to read 4, iclass 11, count 0 2006.239.08:14:38.94#ibcon#read 4, iclass 11, count 0 2006.239.08:14:38.94#ibcon#about to read 5, iclass 11, count 0 2006.239.08:14:38.94#ibcon#read 5, iclass 11, count 0 2006.239.08:14:38.94#ibcon#about to read 6, iclass 11, count 0 2006.239.08:14:38.94#ibcon#read 6, iclass 11, count 0 2006.239.08:14:38.94#ibcon#end of sib2, iclass 11, count 0 2006.239.08:14:38.94#ibcon#*after write, iclass 11, count 0 2006.239.08:14:38.94#ibcon#*before return 0, iclass 11, count 0 2006.239.08:14:38.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:14:38.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:14:38.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:14:38.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:14:38.94$vc4f8/valo=4,832.99 2006.239.08:14:38.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.08:14:38.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.08:14:38.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:38.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:38.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:38.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:38.94#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:14:38.94#ibcon#first serial, iclass 14, count 0 2006.239.08:14:38.94#ibcon#enter sib2, iclass 14, count 0 2006.239.08:14:38.94#ibcon#flushed, iclass 14, count 0 2006.239.08:14:38.94#ibcon#about to write, iclass 14, count 0 2006.239.08:14:38.94#ibcon#wrote, iclass 14, count 0 2006.239.08:14:38.94#ibcon#about to read 3, iclass 14, count 0 2006.239.08:14:38.96#ibcon#read 3, iclass 14, count 0 2006.239.08:14:38.96#ibcon#about to read 4, iclass 14, count 0 2006.239.08:14:38.96#ibcon#read 4, iclass 14, count 0 2006.239.08:14:38.96#ibcon#about to read 5, iclass 14, count 0 2006.239.08:14:38.96#ibcon#read 5, iclass 14, count 0 2006.239.08:14:38.96#ibcon#about to read 6, iclass 14, count 0 2006.239.08:14:38.96#ibcon#read 6, iclass 14, count 0 2006.239.08:14:38.96#ibcon#end of sib2, iclass 14, count 0 2006.239.08:14:38.96#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:14:38.96#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:14:38.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:14:38.96#ibcon#*before write, iclass 14, count 0 2006.239.08:14:38.96#ibcon#enter sib2, iclass 14, count 0 2006.239.08:14:38.96#ibcon#flushed, iclass 14, count 0 2006.239.08:14:38.96#ibcon#about to write, iclass 14, count 0 2006.239.08:14:38.96#ibcon#wrote, iclass 14, count 0 2006.239.08:14:38.96#ibcon#about to read 3, iclass 14, count 0 2006.239.08:14:39.00#ibcon#read 3, iclass 14, count 0 2006.239.08:14:39.00#ibcon#about to read 4, iclass 14, count 0 2006.239.08:14:39.00#ibcon#read 4, iclass 14, count 0 2006.239.08:14:39.00#ibcon#about to read 5, iclass 14, count 0 2006.239.08:14:39.00#ibcon#read 5, iclass 14, count 0 2006.239.08:14:39.00#ibcon#about to read 6, iclass 14, count 0 2006.239.08:14:39.00#ibcon#read 6, iclass 14, count 0 2006.239.08:14:39.00#ibcon#end of sib2, iclass 14, count 0 2006.239.08:14:39.00#ibcon#*after write, iclass 14, count 0 2006.239.08:14:39.00#ibcon#*before return 0, iclass 14, count 0 2006.239.08:14:39.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:39.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:39.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:14:39.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:14:39.00$vc4f8/va=4,7 2006.239.08:14:39.00#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.08:14:39.00#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.08:14:39.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:39.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:39.06#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:39.06#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:39.06#ibcon#enter wrdev, iclass 16, count 2 2006.239.08:14:39.06#ibcon#first serial, iclass 16, count 2 2006.239.08:14:39.06#ibcon#enter sib2, iclass 16, count 2 2006.239.08:14:39.06#ibcon#flushed, iclass 16, count 2 2006.239.08:14:39.06#ibcon#about to write, iclass 16, count 2 2006.239.08:14:39.06#ibcon#wrote, iclass 16, count 2 2006.239.08:14:39.06#ibcon#about to read 3, iclass 16, count 2 2006.239.08:14:39.08#ibcon#read 3, iclass 16, count 2 2006.239.08:14:39.08#ibcon#about to read 4, iclass 16, count 2 2006.239.08:14:39.08#ibcon#read 4, iclass 16, count 2 2006.239.08:14:39.08#ibcon#about to read 5, iclass 16, count 2 2006.239.08:14:39.08#ibcon#read 5, iclass 16, count 2 2006.239.08:14:39.08#ibcon#about to read 6, iclass 16, count 2 2006.239.08:14:39.08#ibcon#read 6, iclass 16, count 2 2006.239.08:14:39.08#ibcon#end of sib2, iclass 16, count 2 2006.239.08:14:39.08#ibcon#*mode == 0, iclass 16, count 2 2006.239.08:14:39.08#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.08:14:39.08#ibcon#[25=AT04-07\r\n] 2006.239.08:14:39.08#ibcon#*before write, iclass 16, count 2 2006.239.08:14:39.08#ibcon#enter sib2, iclass 16, count 2 2006.239.08:14:39.08#ibcon#flushed, iclass 16, count 2 2006.239.08:14:39.08#ibcon#about to write, iclass 16, count 2 2006.239.08:14:39.08#ibcon#wrote, iclass 16, count 2 2006.239.08:14:39.08#ibcon#about to read 3, iclass 16, count 2 2006.239.08:14:39.11#ibcon#read 3, iclass 16, count 2 2006.239.08:14:39.11#ibcon#about to read 4, iclass 16, count 2 2006.239.08:14:39.11#ibcon#read 4, iclass 16, count 2 2006.239.08:14:39.11#ibcon#about to read 5, iclass 16, count 2 2006.239.08:14:39.11#ibcon#read 5, iclass 16, count 2 2006.239.08:14:39.11#ibcon#about to read 6, iclass 16, count 2 2006.239.08:14:39.11#ibcon#read 6, iclass 16, count 2 2006.239.08:14:39.11#ibcon#end of sib2, iclass 16, count 2 2006.239.08:14:39.11#ibcon#*after write, iclass 16, count 2 2006.239.08:14:39.11#ibcon#*before return 0, iclass 16, count 2 2006.239.08:14:39.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:39.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:39.11#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.08:14:39.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:39.11#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:39.23#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:39.23#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:39.23#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:14:39.23#ibcon#first serial, iclass 16, count 0 2006.239.08:14:39.23#ibcon#enter sib2, iclass 16, count 0 2006.239.08:14:39.23#ibcon#flushed, iclass 16, count 0 2006.239.08:14:39.23#ibcon#about to write, iclass 16, count 0 2006.239.08:14:39.23#ibcon#wrote, iclass 16, count 0 2006.239.08:14:39.23#ibcon#about to read 3, iclass 16, count 0 2006.239.08:14:39.26#ibcon#read 3, iclass 16, count 0 2006.239.08:14:39.26#ibcon#about to read 4, iclass 16, count 0 2006.239.08:14:39.26#ibcon#read 4, iclass 16, count 0 2006.239.08:14:39.26#ibcon#about to read 5, iclass 16, count 0 2006.239.08:14:39.26#ibcon#read 5, iclass 16, count 0 2006.239.08:14:39.26#ibcon#about to read 6, iclass 16, count 0 2006.239.08:14:39.26#ibcon#read 6, iclass 16, count 0 2006.239.08:14:39.26#ibcon#end of sib2, iclass 16, count 0 2006.239.08:14:39.26#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:14:39.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:14:39.26#ibcon#[25=USB\r\n] 2006.239.08:14:39.26#ibcon#*before write, iclass 16, count 0 2006.239.08:14:39.26#ibcon#enter sib2, iclass 16, count 0 2006.239.08:14:39.26#ibcon#flushed, iclass 16, count 0 2006.239.08:14:39.26#ibcon#about to write, iclass 16, count 0 2006.239.08:14:39.26#ibcon#wrote, iclass 16, count 0 2006.239.08:14:39.26#ibcon#about to read 3, iclass 16, count 0 2006.239.08:14:39.28#ibcon#read 3, iclass 16, count 0 2006.239.08:14:39.28#ibcon#about to read 4, iclass 16, count 0 2006.239.08:14:39.28#ibcon#read 4, iclass 16, count 0 2006.239.08:14:39.28#ibcon#about to read 5, iclass 16, count 0 2006.239.08:14:39.28#ibcon#read 5, iclass 16, count 0 2006.239.08:14:39.28#ibcon#about to read 6, iclass 16, count 0 2006.239.08:14:39.28#ibcon#read 6, iclass 16, count 0 2006.239.08:14:39.28#ibcon#end of sib2, iclass 16, count 0 2006.239.08:14:39.28#ibcon#*after write, iclass 16, count 0 2006.239.08:14:39.28#ibcon#*before return 0, iclass 16, count 0 2006.239.08:14:39.28#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:39.28#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:39.28#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:14:39.28#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:14:39.28$vc4f8/valo=5,652.99 2006.239.08:14:39.28#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:14:39.28#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:14:39.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:39.28#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:39.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:39.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:39.28#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:14:39.28#ibcon#first serial, iclass 18, count 0 2006.239.08:14:39.28#ibcon#enter sib2, iclass 18, count 0 2006.239.08:14:39.28#ibcon#flushed, iclass 18, count 0 2006.239.08:14:39.28#ibcon#about to write, iclass 18, count 0 2006.239.08:14:39.28#ibcon#wrote, iclass 18, count 0 2006.239.08:14:39.28#ibcon#about to read 3, iclass 18, count 0 2006.239.08:14:39.30#ibcon#read 3, iclass 18, count 0 2006.239.08:14:39.30#ibcon#about to read 4, iclass 18, count 0 2006.239.08:14:39.30#ibcon#read 4, iclass 18, count 0 2006.239.08:14:39.30#ibcon#about to read 5, iclass 18, count 0 2006.239.08:14:39.30#ibcon#read 5, iclass 18, count 0 2006.239.08:14:39.30#ibcon#about to read 6, iclass 18, count 0 2006.239.08:14:39.30#ibcon#read 6, iclass 18, count 0 2006.239.08:14:39.30#ibcon#end of sib2, iclass 18, count 0 2006.239.08:14:39.30#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:14:39.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:14:39.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:14:39.30#ibcon#*before write, iclass 18, count 0 2006.239.08:14:39.30#ibcon#enter sib2, iclass 18, count 0 2006.239.08:14:39.30#ibcon#flushed, iclass 18, count 0 2006.239.08:14:39.30#ibcon#about to write, iclass 18, count 0 2006.239.08:14:39.30#ibcon#wrote, iclass 18, count 0 2006.239.08:14:39.30#ibcon#about to read 3, iclass 18, count 0 2006.239.08:14:39.34#ibcon#read 3, iclass 18, count 0 2006.239.08:14:39.34#ibcon#about to read 4, iclass 18, count 0 2006.239.08:14:39.34#ibcon#read 4, iclass 18, count 0 2006.239.08:14:39.34#ibcon#about to read 5, iclass 18, count 0 2006.239.08:14:39.34#ibcon#read 5, iclass 18, count 0 2006.239.08:14:39.34#ibcon#about to read 6, iclass 18, count 0 2006.239.08:14:39.34#ibcon#read 6, iclass 18, count 0 2006.239.08:14:39.34#ibcon#end of sib2, iclass 18, count 0 2006.239.08:14:39.34#ibcon#*after write, iclass 18, count 0 2006.239.08:14:39.34#ibcon#*before return 0, iclass 18, count 0 2006.239.08:14:39.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:39.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:39.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:14:39.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:14:39.34$vc4f8/va=5,8 2006.239.08:14:39.34#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.08:14:39.34#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.08:14:39.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:39.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:39.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:39.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:39.41#ibcon#enter wrdev, iclass 20, count 2 2006.239.08:14:39.41#ibcon#first serial, iclass 20, count 2 2006.239.08:14:39.41#ibcon#enter sib2, iclass 20, count 2 2006.239.08:14:39.41#ibcon#flushed, iclass 20, count 2 2006.239.08:14:39.41#ibcon#about to write, iclass 20, count 2 2006.239.08:14:39.41#ibcon#wrote, iclass 20, count 2 2006.239.08:14:39.41#ibcon#about to read 3, iclass 20, count 2 2006.239.08:14:39.42#ibcon#read 3, iclass 20, count 2 2006.239.08:14:39.42#ibcon#about to read 4, iclass 20, count 2 2006.239.08:14:39.42#ibcon#read 4, iclass 20, count 2 2006.239.08:14:39.42#ibcon#about to read 5, iclass 20, count 2 2006.239.08:14:39.42#ibcon#read 5, iclass 20, count 2 2006.239.08:14:39.42#ibcon#about to read 6, iclass 20, count 2 2006.239.08:14:39.42#ibcon#read 6, iclass 20, count 2 2006.239.08:14:39.42#ibcon#end of sib2, iclass 20, count 2 2006.239.08:14:39.42#ibcon#*mode == 0, iclass 20, count 2 2006.239.08:14:39.42#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.08:14:39.42#ibcon#[25=AT05-08\r\n] 2006.239.08:14:39.42#ibcon#*before write, iclass 20, count 2 2006.239.08:14:39.42#ibcon#enter sib2, iclass 20, count 2 2006.239.08:14:39.42#ibcon#flushed, iclass 20, count 2 2006.239.08:14:39.42#ibcon#about to write, iclass 20, count 2 2006.239.08:14:39.42#ibcon#wrote, iclass 20, count 2 2006.239.08:14:39.42#ibcon#about to read 3, iclass 20, count 2 2006.239.08:14:39.45#ibcon#read 3, iclass 20, count 2 2006.239.08:14:39.45#ibcon#about to read 4, iclass 20, count 2 2006.239.08:14:39.45#ibcon#read 4, iclass 20, count 2 2006.239.08:14:39.45#ibcon#about to read 5, iclass 20, count 2 2006.239.08:14:39.45#ibcon#read 5, iclass 20, count 2 2006.239.08:14:39.45#ibcon#about to read 6, iclass 20, count 2 2006.239.08:14:39.45#ibcon#read 6, iclass 20, count 2 2006.239.08:14:39.45#ibcon#end of sib2, iclass 20, count 2 2006.239.08:14:39.45#ibcon#*after write, iclass 20, count 2 2006.239.08:14:39.45#ibcon#*before return 0, iclass 20, count 2 2006.239.08:14:39.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:39.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:39.45#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.08:14:39.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:39.45#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:39.57#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:39.57#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:39.57#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:14:39.57#ibcon#first serial, iclass 20, count 0 2006.239.08:14:39.57#ibcon#enter sib2, iclass 20, count 0 2006.239.08:14:39.57#ibcon#flushed, iclass 20, count 0 2006.239.08:14:39.57#ibcon#about to write, iclass 20, count 0 2006.239.08:14:39.57#ibcon#wrote, iclass 20, count 0 2006.239.08:14:39.57#ibcon#about to read 3, iclass 20, count 0 2006.239.08:14:39.59#ibcon#read 3, iclass 20, count 0 2006.239.08:14:39.59#ibcon#about to read 4, iclass 20, count 0 2006.239.08:14:39.59#ibcon#read 4, iclass 20, count 0 2006.239.08:14:39.59#ibcon#about to read 5, iclass 20, count 0 2006.239.08:14:39.59#ibcon#read 5, iclass 20, count 0 2006.239.08:14:39.59#ibcon#about to read 6, iclass 20, count 0 2006.239.08:14:39.59#ibcon#read 6, iclass 20, count 0 2006.239.08:14:39.59#ibcon#end of sib2, iclass 20, count 0 2006.239.08:14:39.59#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:14:39.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:14:39.59#ibcon#[25=USB\r\n] 2006.239.08:14:39.59#ibcon#*before write, iclass 20, count 0 2006.239.08:14:39.59#ibcon#enter sib2, iclass 20, count 0 2006.239.08:14:39.59#ibcon#flushed, iclass 20, count 0 2006.239.08:14:39.59#ibcon#about to write, iclass 20, count 0 2006.239.08:14:39.59#ibcon#wrote, iclass 20, count 0 2006.239.08:14:39.59#ibcon#about to read 3, iclass 20, count 0 2006.239.08:14:39.62#ibcon#read 3, iclass 20, count 0 2006.239.08:14:39.62#ibcon#about to read 4, iclass 20, count 0 2006.239.08:14:39.62#ibcon#read 4, iclass 20, count 0 2006.239.08:14:39.62#ibcon#about to read 5, iclass 20, count 0 2006.239.08:14:39.62#ibcon#read 5, iclass 20, count 0 2006.239.08:14:39.62#ibcon#about to read 6, iclass 20, count 0 2006.239.08:14:39.62#ibcon#read 6, iclass 20, count 0 2006.239.08:14:39.62#ibcon#end of sib2, iclass 20, count 0 2006.239.08:14:39.62#ibcon#*after write, iclass 20, count 0 2006.239.08:14:39.62#ibcon#*before return 0, iclass 20, count 0 2006.239.08:14:39.62#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:39.62#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:39.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:14:39.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:14:39.62$vc4f8/valo=6,772.99 2006.239.08:14:39.62#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.08:14:39.62#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.08:14:39.62#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:39.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:39.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:39.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:39.62#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:14:39.62#ibcon#first serial, iclass 22, count 0 2006.239.08:14:39.62#ibcon#enter sib2, iclass 22, count 0 2006.239.08:14:39.62#ibcon#flushed, iclass 22, count 0 2006.239.08:14:39.62#ibcon#about to write, iclass 22, count 0 2006.239.08:14:39.62#ibcon#wrote, iclass 22, count 0 2006.239.08:14:39.62#ibcon#about to read 3, iclass 22, count 0 2006.239.08:14:39.64#ibcon#read 3, iclass 22, count 0 2006.239.08:14:39.64#ibcon#about to read 4, iclass 22, count 0 2006.239.08:14:39.64#ibcon#read 4, iclass 22, count 0 2006.239.08:14:39.64#ibcon#about to read 5, iclass 22, count 0 2006.239.08:14:39.64#ibcon#read 5, iclass 22, count 0 2006.239.08:14:39.64#ibcon#about to read 6, iclass 22, count 0 2006.239.08:14:39.64#ibcon#read 6, iclass 22, count 0 2006.239.08:14:39.64#ibcon#end of sib2, iclass 22, count 0 2006.239.08:14:39.64#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:14:39.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:14:39.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:14:39.64#ibcon#*before write, iclass 22, count 0 2006.239.08:14:39.64#ibcon#enter sib2, iclass 22, count 0 2006.239.08:14:39.64#ibcon#flushed, iclass 22, count 0 2006.239.08:14:39.64#ibcon#about to write, iclass 22, count 0 2006.239.08:14:39.64#ibcon#wrote, iclass 22, count 0 2006.239.08:14:39.64#ibcon#about to read 3, iclass 22, count 0 2006.239.08:14:39.68#ibcon#read 3, iclass 22, count 0 2006.239.08:14:39.68#ibcon#about to read 4, iclass 22, count 0 2006.239.08:14:39.68#ibcon#read 4, iclass 22, count 0 2006.239.08:14:39.68#ibcon#about to read 5, iclass 22, count 0 2006.239.08:14:39.68#ibcon#read 5, iclass 22, count 0 2006.239.08:14:39.68#ibcon#about to read 6, iclass 22, count 0 2006.239.08:14:39.68#ibcon#read 6, iclass 22, count 0 2006.239.08:14:39.68#ibcon#end of sib2, iclass 22, count 0 2006.239.08:14:39.68#ibcon#*after write, iclass 22, count 0 2006.239.08:14:39.68#ibcon#*before return 0, iclass 22, count 0 2006.239.08:14:39.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:39.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:39.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:14:39.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:14:39.68$vc4f8/va=6,7 2006.239.08:14:39.68#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.08:14:39.68#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.08:14:39.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:39.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:14:39.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:14:39.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:14:39.74#ibcon#enter wrdev, iclass 24, count 2 2006.239.08:14:39.74#ibcon#first serial, iclass 24, count 2 2006.239.08:14:39.74#ibcon#enter sib2, iclass 24, count 2 2006.239.08:14:39.74#ibcon#flushed, iclass 24, count 2 2006.239.08:14:39.74#ibcon#about to write, iclass 24, count 2 2006.239.08:14:39.74#ibcon#wrote, iclass 24, count 2 2006.239.08:14:39.74#ibcon#about to read 3, iclass 24, count 2 2006.239.08:14:39.76#ibcon#read 3, iclass 24, count 2 2006.239.08:14:39.76#ibcon#about to read 4, iclass 24, count 2 2006.239.08:14:39.76#ibcon#read 4, iclass 24, count 2 2006.239.08:14:39.76#ibcon#about to read 5, iclass 24, count 2 2006.239.08:14:39.76#ibcon#read 5, iclass 24, count 2 2006.239.08:14:39.76#ibcon#about to read 6, iclass 24, count 2 2006.239.08:14:39.76#ibcon#read 6, iclass 24, count 2 2006.239.08:14:39.76#ibcon#end of sib2, iclass 24, count 2 2006.239.08:14:39.76#ibcon#*mode == 0, iclass 24, count 2 2006.239.08:14:39.76#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.08:14:39.76#ibcon#[25=AT06-07\r\n] 2006.239.08:14:39.76#ibcon#*before write, iclass 24, count 2 2006.239.08:14:39.76#ibcon#enter sib2, iclass 24, count 2 2006.239.08:14:39.76#ibcon#flushed, iclass 24, count 2 2006.239.08:14:39.76#ibcon#about to write, iclass 24, count 2 2006.239.08:14:39.76#ibcon#wrote, iclass 24, count 2 2006.239.08:14:39.76#ibcon#about to read 3, iclass 24, count 2 2006.239.08:14:39.79#ibcon#read 3, iclass 24, count 2 2006.239.08:14:39.79#ibcon#about to read 4, iclass 24, count 2 2006.239.08:14:39.79#ibcon#read 4, iclass 24, count 2 2006.239.08:14:39.79#ibcon#about to read 5, iclass 24, count 2 2006.239.08:14:39.79#ibcon#read 5, iclass 24, count 2 2006.239.08:14:39.79#ibcon#about to read 6, iclass 24, count 2 2006.239.08:14:39.79#ibcon#read 6, iclass 24, count 2 2006.239.08:14:39.79#ibcon#end of sib2, iclass 24, count 2 2006.239.08:14:39.79#ibcon#*after write, iclass 24, count 2 2006.239.08:14:39.79#ibcon#*before return 0, iclass 24, count 2 2006.239.08:14:39.79#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:14:39.79#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:14:39.79#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.08:14:39.79#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:39.79#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:14:39.91#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:14:39.91#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:14:39.91#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:14:39.91#ibcon#first serial, iclass 24, count 0 2006.239.08:14:39.91#ibcon#enter sib2, iclass 24, count 0 2006.239.08:14:39.91#ibcon#flushed, iclass 24, count 0 2006.239.08:14:39.91#ibcon#about to write, iclass 24, count 0 2006.239.08:14:39.91#ibcon#wrote, iclass 24, count 0 2006.239.08:14:39.91#ibcon#about to read 3, iclass 24, count 0 2006.239.08:14:39.93#ibcon#read 3, iclass 24, count 0 2006.239.08:14:39.93#ibcon#about to read 4, iclass 24, count 0 2006.239.08:14:39.93#ibcon#read 4, iclass 24, count 0 2006.239.08:14:39.93#ibcon#about to read 5, iclass 24, count 0 2006.239.08:14:39.93#ibcon#read 5, iclass 24, count 0 2006.239.08:14:39.93#ibcon#about to read 6, iclass 24, count 0 2006.239.08:14:39.93#ibcon#read 6, iclass 24, count 0 2006.239.08:14:39.93#ibcon#end of sib2, iclass 24, count 0 2006.239.08:14:39.93#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:14:39.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:14:39.93#ibcon#[25=USB\r\n] 2006.239.08:14:39.93#ibcon#*before write, iclass 24, count 0 2006.239.08:14:39.93#ibcon#enter sib2, iclass 24, count 0 2006.239.08:14:39.93#ibcon#flushed, iclass 24, count 0 2006.239.08:14:39.93#ibcon#about to write, iclass 24, count 0 2006.239.08:14:39.93#ibcon#wrote, iclass 24, count 0 2006.239.08:14:39.93#ibcon#about to read 3, iclass 24, count 0 2006.239.08:14:39.96#ibcon#read 3, iclass 24, count 0 2006.239.08:14:39.96#ibcon#about to read 4, iclass 24, count 0 2006.239.08:14:39.96#ibcon#read 4, iclass 24, count 0 2006.239.08:14:39.96#ibcon#about to read 5, iclass 24, count 0 2006.239.08:14:39.96#ibcon#read 5, iclass 24, count 0 2006.239.08:14:39.96#ibcon#about to read 6, iclass 24, count 0 2006.239.08:14:39.96#ibcon#read 6, iclass 24, count 0 2006.239.08:14:39.96#ibcon#end of sib2, iclass 24, count 0 2006.239.08:14:39.96#ibcon#*after write, iclass 24, count 0 2006.239.08:14:39.96#ibcon#*before return 0, iclass 24, count 0 2006.239.08:14:39.96#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:14:39.96#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:14:39.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:14:39.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:14:39.96$vc4f8/valo=7,832.99 2006.239.08:14:39.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.08:14:39.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.08:14:39.96#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:39.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:14:39.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:14:39.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:14:39.96#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:14:39.96#ibcon#first serial, iclass 26, count 0 2006.239.08:14:39.96#ibcon#enter sib2, iclass 26, count 0 2006.239.08:14:39.96#ibcon#flushed, iclass 26, count 0 2006.239.08:14:39.96#ibcon#about to write, iclass 26, count 0 2006.239.08:14:39.96#ibcon#wrote, iclass 26, count 0 2006.239.08:14:39.96#ibcon#about to read 3, iclass 26, count 0 2006.239.08:14:39.98#ibcon#read 3, iclass 26, count 0 2006.239.08:14:39.98#ibcon#about to read 4, iclass 26, count 0 2006.239.08:14:39.98#ibcon#read 4, iclass 26, count 0 2006.239.08:14:39.98#ibcon#about to read 5, iclass 26, count 0 2006.239.08:14:39.98#ibcon#read 5, iclass 26, count 0 2006.239.08:14:39.98#ibcon#about to read 6, iclass 26, count 0 2006.239.08:14:39.98#ibcon#read 6, iclass 26, count 0 2006.239.08:14:39.98#ibcon#end of sib2, iclass 26, count 0 2006.239.08:14:39.98#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:14:39.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:14:39.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:14:39.98#ibcon#*before write, iclass 26, count 0 2006.239.08:14:39.98#ibcon#enter sib2, iclass 26, count 0 2006.239.08:14:39.98#ibcon#flushed, iclass 26, count 0 2006.239.08:14:39.98#ibcon#about to write, iclass 26, count 0 2006.239.08:14:39.98#ibcon#wrote, iclass 26, count 0 2006.239.08:14:39.98#ibcon#about to read 3, iclass 26, count 0 2006.239.08:14:40.02#ibcon#read 3, iclass 26, count 0 2006.239.08:14:40.02#ibcon#about to read 4, iclass 26, count 0 2006.239.08:14:40.02#ibcon#read 4, iclass 26, count 0 2006.239.08:14:40.02#ibcon#about to read 5, iclass 26, count 0 2006.239.08:14:40.02#ibcon#read 5, iclass 26, count 0 2006.239.08:14:40.02#ibcon#about to read 6, iclass 26, count 0 2006.239.08:14:40.02#ibcon#read 6, iclass 26, count 0 2006.239.08:14:40.02#ibcon#end of sib2, iclass 26, count 0 2006.239.08:14:40.02#ibcon#*after write, iclass 26, count 0 2006.239.08:14:40.02#ibcon#*before return 0, iclass 26, count 0 2006.239.08:14:40.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:14:40.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:14:40.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:14:40.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:14:40.02$vc4f8/va=7,7 2006.239.08:14:40.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.08:14:40.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.08:14:40.02#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:40.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:14:40.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:14:40.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:14:40.08#ibcon#enter wrdev, iclass 28, count 2 2006.239.08:14:40.08#ibcon#first serial, iclass 28, count 2 2006.239.08:14:40.08#ibcon#enter sib2, iclass 28, count 2 2006.239.08:14:40.08#ibcon#flushed, iclass 28, count 2 2006.239.08:14:40.08#ibcon#about to write, iclass 28, count 2 2006.239.08:14:40.08#ibcon#wrote, iclass 28, count 2 2006.239.08:14:40.08#ibcon#about to read 3, iclass 28, count 2 2006.239.08:14:40.11#ibcon#read 3, iclass 28, count 2 2006.239.08:14:40.11#ibcon#about to read 4, iclass 28, count 2 2006.239.08:14:40.11#ibcon#read 4, iclass 28, count 2 2006.239.08:14:40.11#ibcon#about to read 5, iclass 28, count 2 2006.239.08:14:40.11#ibcon#read 5, iclass 28, count 2 2006.239.08:14:40.11#ibcon#about to read 6, iclass 28, count 2 2006.239.08:14:40.11#ibcon#read 6, iclass 28, count 2 2006.239.08:14:40.11#ibcon#end of sib2, iclass 28, count 2 2006.239.08:14:40.11#ibcon#*mode == 0, iclass 28, count 2 2006.239.08:14:40.11#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.08:14:40.11#ibcon#[25=AT07-07\r\n] 2006.239.08:14:40.11#ibcon#*before write, iclass 28, count 2 2006.239.08:14:40.11#ibcon#enter sib2, iclass 28, count 2 2006.239.08:14:40.11#ibcon#flushed, iclass 28, count 2 2006.239.08:14:40.11#ibcon#about to write, iclass 28, count 2 2006.239.08:14:40.11#ibcon#wrote, iclass 28, count 2 2006.239.08:14:40.11#ibcon#about to read 3, iclass 28, count 2 2006.239.08:14:40.14#ibcon#read 3, iclass 28, count 2 2006.239.08:14:40.14#ibcon#about to read 4, iclass 28, count 2 2006.239.08:14:40.14#ibcon#read 4, iclass 28, count 2 2006.239.08:14:40.14#ibcon#about to read 5, iclass 28, count 2 2006.239.08:14:40.14#ibcon#read 5, iclass 28, count 2 2006.239.08:14:40.14#ibcon#about to read 6, iclass 28, count 2 2006.239.08:14:40.14#ibcon#read 6, iclass 28, count 2 2006.239.08:14:40.14#ibcon#end of sib2, iclass 28, count 2 2006.239.08:14:40.14#ibcon#*after write, iclass 28, count 2 2006.239.08:14:40.14#ibcon#*before return 0, iclass 28, count 2 2006.239.08:14:40.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:14:40.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:14:40.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.08:14:40.14#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:40.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:14:40.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:14:40.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:14:40.26#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:14:40.26#ibcon#first serial, iclass 28, count 0 2006.239.08:14:40.26#ibcon#enter sib2, iclass 28, count 0 2006.239.08:14:40.26#ibcon#flushed, iclass 28, count 0 2006.239.08:14:40.26#ibcon#about to write, iclass 28, count 0 2006.239.08:14:40.26#ibcon#wrote, iclass 28, count 0 2006.239.08:14:40.26#ibcon#about to read 3, iclass 28, count 0 2006.239.08:14:40.28#ibcon#read 3, iclass 28, count 0 2006.239.08:14:40.28#ibcon#about to read 4, iclass 28, count 0 2006.239.08:14:40.28#ibcon#read 4, iclass 28, count 0 2006.239.08:14:40.28#ibcon#about to read 5, iclass 28, count 0 2006.239.08:14:40.28#ibcon#read 5, iclass 28, count 0 2006.239.08:14:40.28#ibcon#about to read 6, iclass 28, count 0 2006.239.08:14:40.28#ibcon#read 6, iclass 28, count 0 2006.239.08:14:40.28#ibcon#end of sib2, iclass 28, count 0 2006.239.08:14:40.28#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:14:40.28#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:14:40.28#ibcon#[25=USB\r\n] 2006.239.08:14:40.28#ibcon#*before write, iclass 28, count 0 2006.239.08:14:40.28#ibcon#enter sib2, iclass 28, count 0 2006.239.08:14:40.28#ibcon#flushed, iclass 28, count 0 2006.239.08:14:40.28#ibcon#about to write, iclass 28, count 0 2006.239.08:14:40.28#ibcon#wrote, iclass 28, count 0 2006.239.08:14:40.28#ibcon#about to read 3, iclass 28, count 0 2006.239.08:14:40.31#ibcon#read 3, iclass 28, count 0 2006.239.08:14:40.31#ibcon#about to read 4, iclass 28, count 0 2006.239.08:14:40.31#ibcon#read 4, iclass 28, count 0 2006.239.08:14:40.31#ibcon#about to read 5, iclass 28, count 0 2006.239.08:14:40.31#ibcon#read 5, iclass 28, count 0 2006.239.08:14:40.31#ibcon#about to read 6, iclass 28, count 0 2006.239.08:14:40.31#ibcon#read 6, iclass 28, count 0 2006.239.08:14:40.31#ibcon#end of sib2, iclass 28, count 0 2006.239.08:14:40.31#ibcon#*after write, iclass 28, count 0 2006.239.08:14:40.31#ibcon#*before return 0, iclass 28, count 0 2006.239.08:14:40.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:14:40.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:14:40.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:14:40.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:14:40.31$vc4f8/valo=8,852.99 2006.239.08:14:40.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.08:14:40.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.08:14:40.31#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:40.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:14:40.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:14:40.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:14:40.31#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:14:40.31#ibcon#first serial, iclass 30, count 0 2006.239.08:14:40.31#ibcon#enter sib2, iclass 30, count 0 2006.239.08:14:40.31#ibcon#flushed, iclass 30, count 0 2006.239.08:14:40.31#ibcon#about to write, iclass 30, count 0 2006.239.08:14:40.31#ibcon#wrote, iclass 30, count 0 2006.239.08:14:40.31#ibcon#about to read 3, iclass 30, count 0 2006.239.08:14:40.33#ibcon#read 3, iclass 30, count 0 2006.239.08:14:40.33#ibcon#about to read 4, iclass 30, count 0 2006.239.08:14:40.33#ibcon#read 4, iclass 30, count 0 2006.239.08:14:40.33#ibcon#about to read 5, iclass 30, count 0 2006.239.08:14:40.33#ibcon#read 5, iclass 30, count 0 2006.239.08:14:40.33#ibcon#about to read 6, iclass 30, count 0 2006.239.08:14:40.33#ibcon#read 6, iclass 30, count 0 2006.239.08:14:40.33#ibcon#end of sib2, iclass 30, count 0 2006.239.08:14:40.33#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:14:40.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:14:40.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:14:40.33#ibcon#*before write, iclass 30, count 0 2006.239.08:14:40.33#ibcon#enter sib2, iclass 30, count 0 2006.239.08:14:40.33#ibcon#flushed, iclass 30, count 0 2006.239.08:14:40.33#ibcon#about to write, iclass 30, count 0 2006.239.08:14:40.33#ibcon#wrote, iclass 30, count 0 2006.239.08:14:40.33#ibcon#about to read 3, iclass 30, count 0 2006.239.08:14:40.37#ibcon#read 3, iclass 30, count 0 2006.239.08:14:40.37#ibcon#about to read 4, iclass 30, count 0 2006.239.08:14:40.37#ibcon#read 4, iclass 30, count 0 2006.239.08:14:40.37#ibcon#about to read 5, iclass 30, count 0 2006.239.08:14:40.37#ibcon#read 5, iclass 30, count 0 2006.239.08:14:40.37#ibcon#about to read 6, iclass 30, count 0 2006.239.08:14:40.37#ibcon#read 6, iclass 30, count 0 2006.239.08:14:40.37#ibcon#end of sib2, iclass 30, count 0 2006.239.08:14:40.37#ibcon#*after write, iclass 30, count 0 2006.239.08:14:40.37#ibcon#*before return 0, iclass 30, count 0 2006.239.08:14:40.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:14:40.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:14:40.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:14:40.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:14:40.37$vc4f8/va=8,7 2006.239.08:14:40.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.08:14:40.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.08:14:40.37#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:40.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:14:40.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:14:40.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:14:40.43#ibcon#enter wrdev, iclass 32, count 2 2006.239.08:14:40.43#ibcon#first serial, iclass 32, count 2 2006.239.08:14:40.43#ibcon#enter sib2, iclass 32, count 2 2006.239.08:14:40.43#ibcon#flushed, iclass 32, count 2 2006.239.08:14:40.43#ibcon#about to write, iclass 32, count 2 2006.239.08:14:40.43#ibcon#wrote, iclass 32, count 2 2006.239.08:14:40.43#ibcon#about to read 3, iclass 32, count 2 2006.239.08:14:40.45#ibcon#read 3, iclass 32, count 2 2006.239.08:14:40.45#ibcon#about to read 4, iclass 32, count 2 2006.239.08:14:40.45#ibcon#read 4, iclass 32, count 2 2006.239.08:14:40.45#ibcon#about to read 5, iclass 32, count 2 2006.239.08:14:40.45#ibcon#read 5, iclass 32, count 2 2006.239.08:14:40.45#ibcon#about to read 6, iclass 32, count 2 2006.239.08:14:40.45#ibcon#read 6, iclass 32, count 2 2006.239.08:14:40.45#ibcon#end of sib2, iclass 32, count 2 2006.239.08:14:40.45#ibcon#*mode == 0, iclass 32, count 2 2006.239.08:14:40.45#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.08:14:40.45#ibcon#[25=AT08-07\r\n] 2006.239.08:14:40.45#ibcon#*before write, iclass 32, count 2 2006.239.08:14:40.45#ibcon#enter sib2, iclass 32, count 2 2006.239.08:14:40.45#ibcon#flushed, iclass 32, count 2 2006.239.08:14:40.45#ibcon#about to write, iclass 32, count 2 2006.239.08:14:40.45#ibcon#wrote, iclass 32, count 2 2006.239.08:14:40.45#ibcon#about to read 3, iclass 32, count 2 2006.239.08:14:40.48#ibcon#read 3, iclass 32, count 2 2006.239.08:14:40.48#ibcon#about to read 4, iclass 32, count 2 2006.239.08:14:40.48#ibcon#read 4, iclass 32, count 2 2006.239.08:14:40.48#ibcon#about to read 5, iclass 32, count 2 2006.239.08:14:40.48#ibcon#read 5, iclass 32, count 2 2006.239.08:14:40.48#ibcon#about to read 6, iclass 32, count 2 2006.239.08:14:40.48#ibcon#read 6, iclass 32, count 2 2006.239.08:14:40.48#ibcon#end of sib2, iclass 32, count 2 2006.239.08:14:40.48#ibcon#*after write, iclass 32, count 2 2006.239.08:14:40.48#ibcon#*before return 0, iclass 32, count 2 2006.239.08:14:40.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:14:40.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:14:40.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.08:14:40.48#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:40.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:14:40.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:14:40.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:14:40.60#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:14:40.60#ibcon#first serial, iclass 32, count 0 2006.239.08:14:40.60#ibcon#enter sib2, iclass 32, count 0 2006.239.08:14:40.60#ibcon#flushed, iclass 32, count 0 2006.239.08:14:40.60#ibcon#about to write, iclass 32, count 0 2006.239.08:14:40.60#ibcon#wrote, iclass 32, count 0 2006.239.08:14:40.60#ibcon#about to read 3, iclass 32, count 0 2006.239.08:14:40.62#ibcon#read 3, iclass 32, count 0 2006.239.08:14:40.62#ibcon#about to read 4, iclass 32, count 0 2006.239.08:14:40.62#ibcon#read 4, iclass 32, count 0 2006.239.08:14:40.62#ibcon#about to read 5, iclass 32, count 0 2006.239.08:14:40.62#ibcon#read 5, iclass 32, count 0 2006.239.08:14:40.62#ibcon#about to read 6, iclass 32, count 0 2006.239.08:14:40.62#ibcon#read 6, iclass 32, count 0 2006.239.08:14:40.62#ibcon#end of sib2, iclass 32, count 0 2006.239.08:14:40.62#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:14:40.62#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:14:40.62#ibcon#[25=USB\r\n] 2006.239.08:14:40.62#ibcon#*before write, iclass 32, count 0 2006.239.08:14:40.62#ibcon#enter sib2, iclass 32, count 0 2006.239.08:14:40.62#ibcon#flushed, iclass 32, count 0 2006.239.08:14:40.62#ibcon#about to write, iclass 32, count 0 2006.239.08:14:40.62#ibcon#wrote, iclass 32, count 0 2006.239.08:14:40.62#ibcon#about to read 3, iclass 32, count 0 2006.239.08:14:40.65#ibcon#read 3, iclass 32, count 0 2006.239.08:14:40.65#ibcon#about to read 4, iclass 32, count 0 2006.239.08:14:40.65#ibcon#read 4, iclass 32, count 0 2006.239.08:14:40.65#ibcon#about to read 5, iclass 32, count 0 2006.239.08:14:40.65#ibcon#read 5, iclass 32, count 0 2006.239.08:14:40.65#ibcon#about to read 6, iclass 32, count 0 2006.239.08:14:40.65#ibcon#read 6, iclass 32, count 0 2006.239.08:14:40.65#ibcon#end of sib2, iclass 32, count 0 2006.239.08:14:40.65#ibcon#*after write, iclass 32, count 0 2006.239.08:14:40.65#ibcon#*before return 0, iclass 32, count 0 2006.239.08:14:40.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:14:40.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:14:40.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:14:40.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:14:40.65$vc4f8/vblo=1,632.99 2006.239.08:14:40.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.08:14:40.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.08:14:40.65#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:40.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:40.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:40.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:40.65#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:14:40.65#ibcon#first serial, iclass 34, count 0 2006.239.08:14:40.65#ibcon#enter sib2, iclass 34, count 0 2006.239.08:14:40.65#ibcon#flushed, iclass 34, count 0 2006.239.08:14:40.65#ibcon#about to write, iclass 34, count 0 2006.239.08:14:40.65#ibcon#wrote, iclass 34, count 0 2006.239.08:14:40.65#ibcon#about to read 3, iclass 34, count 0 2006.239.08:14:40.67#ibcon#read 3, iclass 34, count 0 2006.239.08:14:40.67#ibcon#about to read 4, iclass 34, count 0 2006.239.08:14:40.67#ibcon#read 4, iclass 34, count 0 2006.239.08:14:40.67#ibcon#about to read 5, iclass 34, count 0 2006.239.08:14:40.67#ibcon#read 5, iclass 34, count 0 2006.239.08:14:40.67#ibcon#about to read 6, iclass 34, count 0 2006.239.08:14:40.67#ibcon#read 6, iclass 34, count 0 2006.239.08:14:40.67#ibcon#end of sib2, iclass 34, count 0 2006.239.08:14:40.67#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:14:40.67#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:14:40.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:14:40.67#ibcon#*before write, iclass 34, count 0 2006.239.08:14:40.67#ibcon#enter sib2, iclass 34, count 0 2006.239.08:14:40.67#ibcon#flushed, iclass 34, count 0 2006.239.08:14:40.67#ibcon#about to write, iclass 34, count 0 2006.239.08:14:40.67#ibcon#wrote, iclass 34, count 0 2006.239.08:14:40.67#ibcon#about to read 3, iclass 34, count 0 2006.239.08:14:40.71#ibcon#read 3, iclass 34, count 0 2006.239.08:14:40.71#ibcon#about to read 4, iclass 34, count 0 2006.239.08:14:40.71#ibcon#read 4, iclass 34, count 0 2006.239.08:14:40.71#ibcon#about to read 5, iclass 34, count 0 2006.239.08:14:40.71#ibcon#read 5, iclass 34, count 0 2006.239.08:14:40.71#ibcon#about to read 6, iclass 34, count 0 2006.239.08:14:40.71#ibcon#read 6, iclass 34, count 0 2006.239.08:14:40.71#ibcon#end of sib2, iclass 34, count 0 2006.239.08:14:40.71#ibcon#*after write, iclass 34, count 0 2006.239.08:14:40.71#ibcon#*before return 0, iclass 34, count 0 2006.239.08:14:40.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:40.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:14:40.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:14:40.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:14:40.71$vc4f8/vb=1,4 2006.239.08:14:40.71#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.08:14:40.71#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.08:14:40.71#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:40.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:40.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:40.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:40.71#ibcon#enter wrdev, iclass 36, count 2 2006.239.08:14:40.71#ibcon#first serial, iclass 36, count 2 2006.239.08:14:40.71#ibcon#enter sib2, iclass 36, count 2 2006.239.08:14:40.71#ibcon#flushed, iclass 36, count 2 2006.239.08:14:40.71#ibcon#about to write, iclass 36, count 2 2006.239.08:14:40.71#ibcon#wrote, iclass 36, count 2 2006.239.08:14:40.71#ibcon#about to read 3, iclass 36, count 2 2006.239.08:14:40.73#ibcon#read 3, iclass 36, count 2 2006.239.08:14:40.73#ibcon#about to read 4, iclass 36, count 2 2006.239.08:14:40.73#ibcon#read 4, iclass 36, count 2 2006.239.08:14:40.73#ibcon#about to read 5, iclass 36, count 2 2006.239.08:14:40.73#ibcon#read 5, iclass 36, count 2 2006.239.08:14:40.73#ibcon#about to read 6, iclass 36, count 2 2006.239.08:14:40.73#ibcon#read 6, iclass 36, count 2 2006.239.08:14:40.73#ibcon#end of sib2, iclass 36, count 2 2006.239.08:14:40.73#ibcon#*mode == 0, iclass 36, count 2 2006.239.08:14:40.73#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.08:14:40.73#ibcon#[27=AT01-04\r\n] 2006.239.08:14:40.73#ibcon#*before write, iclass 36, count 2 2006.239.08:14:40.73#ibcon#enter sib2, iclass 36, count 2 2006.239.08:14:40.73#ibcon#flushed, iclass 36, count 2 2006.239.08:14:40.73#ibcon#about to write, iclass 36, count 2 2006.239.08:14:40.73#ibcon#wrote, iclass 36, count 2 2006.239.08:14:40.73#ibcon#about to read 3, iclass 36, count 2 2006.239.08:14:40.76#ibcon#read 3, iclass 36, count 2 2006.239.08:14:40.76#ibcon#about to read 4, iclass 36, count 2 2006.239.08:14:40.76#ibcon#read 4, iclass 36, count 2 2006.239.08:14:40.76#ibcon#about to read 5, iclass 36, count 2 2006.239.08:14:40.76#ibcon#read 5, iclass 36, count 2 2006.239.08:14:40.76#ibcon#about to read 6, iclass 36, count 2 2006.239.08:14:40.76#ibcon#read 6, iclass 36, count 2 2006.239.08:14:40.76#ibcon#end of sib2, iclass 36, count 2 2006.239.08:14:40.76#ibcon#*after write, iclass 36, count 2 2006.239.08:14:40.76#ibcon#*before return 0, iclass 36, count 2 2006.239.08:14:40.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:40.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:14:40.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.08:14:40.76#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:40.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:40.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:40.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:40.89#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:14:40.89#ibcon#first serial, iclass 36, count 0 2006.239.08:14:40.89#ibcon#enter sib2, iclass 36, count 0 2006.239.08:14:40.89#ibcon#flushed, iclass 36, count 0 2006.239.08:14:40.89#ibcon#about to write, iclass 36, count 0 2006.239.08:14:40.89#ibcon#wrote, iclass 36, count 0 2006.239.08:14:40.89#ibcon#about to read 3, iclass 36, count 0 2006.239.08:14:40.90#ibcon#read 3, iclass 36, count 0 2006.239.08:14:40.90#ibcon#about to read 4, iclass 36, count 0 2006.239.08:14:40.90#ibcon#read 4, iclass 36, count 0 2006.239.08:14:40.90#ibcon#about to read 5, iclass 36, count 0 2006.239.08:14:40.90#ibcon#read 5, iclass 36, count 0 2006.239.08:14:40.90#ibcon#about to read 6, iclass 36, count 0 2006.239.08:14:40.90#ibcon#read 6, iclass 36, count 0 2006.239.08:14:40.90#ibcon#end of sib2, iclass 36, count 0 2006.239.08:14:40.90#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:14:40.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:14:40.90#ibcon#[27=USB\r\n] 2006.239.08:14:40.90#ibcon#*before write, iclass 36, count 0 2006.239.08:14:40.90#ibcon#enter sib2, iclass 36, count 0 2006.239.08:14:40.90#ibcon#flushed, iclass 36, count 0 2006.239.08:14:40.90#ibcon#about to write, iclass 36, count 0 2006.239.08:14:40.90#ibcon#wrote, iclass 36, count 0 2006.239.08:14:40.90#ibcon#about to read 3, iclass 36, count 0 2006.239.08:14:40.93#ibcon#read 3, iclass 36, count 0 2006.239.08:14:40.93#ibcon#about to read 4, iclass 36, count 0 2006.239.08:14:40.93#ibcon#read 4, iclass 36, count 0 2006.239.08:14:40.93#ibcon#about to read 5, iclass 36, count 0 2006.239.08:14:40.93#ibcon#read 5, iclass 36, count 0 2006.239.08:14:40.93#ibcon#about to read 6, iclass 36, count 0 2006.239.08:14:40.93#ibcon#read 6, iclass 36, count 0 2006.239.08:14:40.93#ibcon#end of sib2, iclass 36, count 0 2006.239.08:14:40.93#ibcon#*after write, iclass 36, count 0 2006.239.08:14:40.93#ibcon#*before return 0, iclass 36, count 0 2006.239.08:14:40.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:40.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:14:40.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:14:40.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:14:40.93$vc4f8/vblo=2,640.99 2006.239.08:14:40.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.08:14:40.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.08:14:40.93#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:40.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:40.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:40.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:40.93#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:14:40.93#ibcon#first serial, iclass 38, count 0 2006.239.08:14:40.93#ibcon#enter sib2, iclass 38, count 0 2006.239.08:14:40.93#ibcon#flushed, iclass 38, count 0 2006.239.08:14:40.93#ibcon#about to write, iclass 38, count 0 2006.239.08:14:40.93#ibcon#wrote, iclass 38, count 0 2006.239.08:14:40.93#ibcon#about to read 3, iclass 38, count 0 2006.239.08:14:40.95#ibcon#read 3, iclass 38, count 0 2006.239.08:14:40.95#ibcon#about to read 4, iclass 38, count 0 2006.239.08:14:40.95#ibcon#read 4, iclass 38, count 0 2006.239.08:14:40.95#ibcon#about to read 5, iclass 38, count 0 2006.239.08:14:40.95#ibcon#read 5, iclass 38, count 0 2006.239.08:14:40.95#ibcon#about to read 6, iclass 38, count 0 2006.239.08:14:40.95#ibcon#read 6, iclass 38, count 0 2006.239.08:14:40.95#ibcon#end of sib2, iclass 38, count 0 2006.239.08:14:40.95#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:14:40.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:14:40.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:14:40.95#ibcon#*before write, iclass 38, count 0 2006.239.08:14:40.95#ibcon#enter sib2, iclass 38, count 0 2006.239.08:14:40.95#ibcon#flushed, iclass 38, count 0 2006.239.08:14:40.95#ibcon#about to write, iclass 38, count 0 2006.239.08:14:40.95#ibcon#wrote, iclass 38, count 0 2006.239.08:14:40.95#ibcon#about to read 3, iclass 38, count 0 2006.239.08:14:40.99#ibcon#read 3, iclass 38, count 0 2006.239.08:14:40.99#ibcon#about to read 4, iclass 38, count 0 2006.239.08:14:40.99#ibcon#read 4, iclass 38, count 0 2006.239.08:14:40.99#ibcon#about to read 5, iclass 38, count 0 2006.239.08:14:40.99#ibcon#read 5, iclass 38, count 0 2006.239.08:14:40.99#ibcon#about to read 6, iclass 38, count 0 2006.239.08:14:40.99#ibcon#read 6, iclass 38, count 0 2006.239.08:14:40.99#ibcon#end of sib2, iclass 38, count 0 2006.239.08:14:40.99#ibcon#*after write, iclass 38, count 0 2006.239.08:14:40.99#ibcon#*before return 0, iclass 38, count 0 2006.239.08:14:40.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:40.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:14:40.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:14:40.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:14:40.99$vc4f8/vb=2,4 2006.239.08:14:40.99#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.239.08:14:40.99#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.239.08:14:40.99#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:40.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:41.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:41.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:41.05#ibcon#enter wrdev, iclass 40, count 2 2006.239.08:14:41.05#ibcon#first serial, iclass 40, count 2 2006.239.08:14:41.05#ibcon#enter sib2, iclass 40, count 2 2006.239.08:14:41.05#ibcon#flushed, iclass 40, count 2 2006.239.08:14:41.05#ibcon#about to write, iclass 40, count 2 2006.239.08:14:41.05#ibcon#wrote, iclass 40, count 2 2006.239.08:14:41.05#ibcon#about to read 3, iclass 40, count 2 2006.239.08:14:41.07#ibcon#read 3, iclass 40, count 2 2006.239.08:14:41.07#ibcon#about to read 4, iclass 40, count 2 2006.239.08:14:41.07#ibcon#read 4, iclass 40, count 2 2006.239.08:14:41.07#ibcon#about to read 5, iclass 40, count 2 2006.239.08:14:41.07#ibcon#read 5, iclass 40, count 2 2006.239.08:14:41.07#ibcon#about to read 6, iclass 40, count 2 2006.239.08:14:41.07#ibcon#read 6, iclass 40, count 2 2006.239.08:14:41.07#ibcon#end of sib2, iclass 40, count 2 2006.239.08:14:41.07#ibcon#*mode == 0, iclass 40, count 2 2006.239.08:14:41.07#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.239.08:14:41.07#ibcon#[27=AT02-04\r\n] 2006.239.08:14:41.07#ibcon#*before write, iclass 40, count 2 2006.239.08:14:41.07#ibcon#enter sib2, iclass 40, count 2 2006.239.08:14:41.07#ibcon#flushed, iclass 40, count 2 2006.239.08:14:41.07#ibcon#about to write, iclass 40, count 2 2006.239.08:14:41.07#ibcon#wrote, iclass 40, count 2 2006.239.08:14:41.07#ibcon#about to read 3, iclass 40, count 2 2006.239.08:14:41.10#ibcon#read 3, iclass 40, count 2 2006.239.08:14:41.10#ibcon#about to read 4, iclass 40, count 2 2006.239.08:14:41.10#ibcon#read 4, iclass 40, count 2 2006.239.08:14:41.10#ibcon#about to read 5, iclass 40, count 2 2006.239.08:14:41.10#ibcon#read 5, iclass 40, count 2 2006.239.08:14:41.10#ibcon#about to read 6, iclass 40, count 2 2006.239.08:14:41.10#ibcon#read 6, iclass 40, count 2 2006.239.08:14:41.10#ibcon#end of sib2, iclass 40, count 2 2006.239.08:14:41.10#ibcon#*after write, iclass 40, count 2 2006.239.08:14:41.10#ibcon#*before return 0, iclass 40, count 2 2006.239.08:14:41.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:41.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.239.08:14:41.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.239.08:14:41.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:41.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:41.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:41.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:41.22#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:14:41.22#ibcon#first serial, iclass 40, count 0 2006.239.08:14:41.22#ibcon#enter sib2, iclass 40, count 0 2006.239.08:14:41.22#ibcon#flushed, iclass 40, count 0 2006.239.08:14:41.22#ibcon#about to write, iclass 40, count 0 2006.239.08:14:41.22#ibcon#wrote, iclass 40, count 0 2006.239.08:14:41.22#ibcon#about to read 3, iclass 40, count 0 2006.239.08:14:41.24#ibcon#read 3, iclass 40, count 0 2006.239.08:14:41.24#ibcon#about to read 4, iclass 40, count 0 2006.239.08:14:41.24#ibcon#read 4, iclass 40, count 0 2006.239.08:14:41.24#ibcon#about to read 5, iclass 40, count 0 2006.239.08:14:41.24#ibcon#read 5, iclass 40, count 0 2006.239.08:14:41.24#ibcon#about to read 6, iclass 40, count 0 2006.239.08:14:41.24#ibcon#read 6, iclass 40, count 0 2006.239.08:14:41.24#ibcon#end of sib2, iclass 40, count 0 2006.239.08:14:41.24#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:14:41.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:14:41.24#ibcon#[27=USB\r\n] 2006.239.08:14:41.24#ibcon#*before write, iclass 40, count 0 2006.239.08:14:41.24#ibcon#enter sib2, iclass 40, count 0 2006.239.08:14:41.24#ibcon#flushed, iclass 40, count 0 2006.239.08:14:41.24#ibcon#about to write, iclass 40, count 0 2006.239.08:14:41.24#ibcon#wrote, iclass 40, count 0 2006.239.08:14:41.24#ibcon#about to read 3, iclass 40, count 0 2006.239.08:14:41.27#ibcon#read 3, iclass 40, count 0 2006.239.08:14:41.27#ibcon#about to read 4, iclass 40, count 0 2006.239.08:14:41.27#ibcon#read 4, iclass 40, count 0 2006.239.08:14:41.27#ibcon#about to read 5, iclass 40, count 0 2006.239.08:14:41.27#ibcon#read 5, iclass 40, count 0 2006.239.08:14:41.27#ibcon#about to read 6, iclass 40, count 0 2006.239.08:14:41.27#ibcon#read 6, iclass 40, count 0 2006.239.08:14:41.27#ibcon#end of sib2, iclass 40, count 0 2006.239.08:14:41.27#ibcon#*after write, iclass 40, count 0 2006.239.08:14:41.27#ibcon#*before return 0, iclass 40, count 0 2006.239.08:14:41.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:41.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.239.08:14:41.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:14:41.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:14:41.27$vc4f8/vblo=3,656.99 2006.239.08:14:41.27#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.239.08:14:41.27#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.239.08:14:41.27#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:41.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:14:41.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:14:41.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:14:41.27#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:14:41.27#ibcon#first serial, iclass 4, count 0 2006.239.08:14:41.27#ibcon#enter sib2, iclass 4, count 0 2006.239.08:14:41.27#ibcon#flushed, iclass 4, count 0 2006.239.08:14:41.27#ibcon#about to write, iclass 4, count 0 2006.239.08:14:41.27#ibcon#wrote, iclass 4, count 0 2006.239.08:14:41.27#ibcon#about to read 3, iclass 4, count 0 2006.239.08:14:41.29#ibcon#read 3, iclass 4, count 0 2006.239.08:14:41.29#ibcon#about to read 4, iclass 4, count 0 2006.239.08:14:41.29#ibcon#read 4, iclass 4, count 0 2006.239.08:14:41.29#ibcon#about to read 5, iclass 4, count 0 2006.239.08:14:41.29#ibcon#read 5, iclass 4, count 0 2006.239.08:14:41.29#ibcon#about to read 6, iclass 4, count 0 2006.239.08:14:41.29#ibcon#read 6, iclass 4, count 0 2006.239.08:14:41.29#ibcon#end of sib2, iclass 4, count 0 2006.239.08:14:41.29#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:14:41.29#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:14:41.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:14:41.29#ibcon#*before write, iclass 4, count 0 2006.239.08:14:41.29#ibcon#enter sib2, iclass 4, count 0 2006.239.08:14:41.29#ibcon#flushed, iclass 4, count 0 2006.239.08:14:41.29#ibcon#about to write, iclass 4, count 0 2006.239.08:14:41.29#ibcon#wrote, iclass 4, count 0 2006.239.08:14:41.29#ibcon#about to read 3, iclass 4, count 0 2006.239.08:14:41.33#ibcon#read 3, iclass 4, count 0 2006.239.08:14:41.33#ibcon#about to read 4, iclass 4, count 0 2006.239.08:14:41.33#ibcon#read 4, iclass 4, count 0 2006.239.08:14:41.33#ibcon#about to read 5, iclass 4, count 0 2006.239.08:14:41.33#ibcon#read 5, iclass 4, count 0 2006.239.08:14:41.33#ibcon#about to read 6, iclass 4, count 0 2006.239.08:14:41.33#ibcon#read 6, iclass 4, count 0 2006.239.08:14:41.33#ibcon#end of sib2, iclass 4, count 0 2006.239.08:14:41.33#ibcon#*after write, iclass 4, count 0 2006.239.08:14:41.33#ibcon#*before return 0, iclass 4, count 0 2006.239.08:14:41.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:14:41.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.239.08:14:41.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:14:41.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:14:41.33$vc4f8/vb=3,4 2006.239.08:14:41.33#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.08:14:41.33#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.08:14:41.33#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:41.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:14:41.39#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:14:41.39#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:14:41.39#ibcon#enter wrdev, iclass 6, count 2 2006.239.08:14:41.39#ibcon#first serial, iclass 6, count 2 2006.239.08:14:41.39#ibcon#enter sib2, iclass 6, count 2 2006.239.08:14:41.39#ibcon#flushed, iclass 6, count 2 2006.239.08:14:41.39#ibcon#about to write, iclass 6, count 2 2006.239.08:14:41.39#ibcon#wrote, iclass 6, count 2 2006.239.08:14:41.39#ibcon#about to read 3, iclass 6, count 2 2006.239.08:14:41.41#ibcon#read 3, iclass 6, count 2 2006.239.08:14:41.41#ibcon#about to read 4, iclass 6, count 2 2006.239.08:14:41.41#ibcon#read 4, iclass 6, count 2 2006.239.08:14:41.41#ibcon#about to read 5, iclass 6, count 2 2006.239.08:14:41.41#ibcon#read 5, iclass 6, count 2 2006.239.08:14:41.41#ibcon#about to read 6, iclass 6, count 2 2006.239.08:14:41.41#ibcon#read 6, iclass 6, count 2 2006.239.08:14:41.41#ibcon#end of sib2, iclass 6, count 2 2006.239.08:14:41.41#ibcon#*mode == 0, iclass 6, count 2 2006.239.08:14:41.41#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.08:14:41.41#ibcon#[27=AT03-04\r\n] 2006.239.08:14:41.41#ibcon#*before write, iclass 6, count 2 2006.239.08:14:41.41#ibcon#enter sib2, iclass 6, count 2 2006.239.08:14:41.41#ibcon#flushed, iclass 6, count 2 2006.239.08:14:41.41#ibcon#about to write, iclass 6, count 2 2006.239.08:14:41.41#ibcon#wrote, iclass 6, count 2 2006.239.08:14:41.41#ibcon#about to read 3, iclass 6, count 2 2006.239.08:14:41.44#ibcon#read 3, iclass 6, count 2 2006.239.08:14:41.44#ibcon#about to read 4, iclass 6, count 2 2006.239.08:14:41.44#ibcon#read 4, iclass 6, count 2 2006.239.08:14:41.44#ibcon#about to read 5, iclass 6, count 2 2006.239.08:14:41.44#ibcon#read 5, iclass 6, count 2 2006.239.08:14:41.44#ibcon#about to read 6, iclass 6, count 2 2006.239.08:14:41.44#ibcon#read 6, iclass 6, count 2 2006.239.08:14:41.44#ibcon#end of sib2, iclass 6, count 2 2006.239.08:14:41.44#ibcon#*after write, iclass 6, count 2 2006.239.08:14:41.44#ibcon#*before return 0, iclass 6, count 2 2006.239.08:14:41.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:14:41.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:14:41.44#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.08:14:41.44#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:41.44#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:14:41.56#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:14:41.56#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:14:41.56#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:14:41.56#ibcon#first serial, iclass 6, count 0 2006.239.08:14:41.56#ibcon#enter sib2, iclass 6, count 0 2006.239.08:14:41.56#ibcon#flushed, iclass 6, count 0 2006.239.08:14:41.56#ibcon#about to write, iclass 6, count 0 2006.239.08:14:41.56#ibcon#wrote, iclass 6, count 0 2006.239.08:14:41.56#ibcon#about to read 3, iclass 6, count 0 2006.239.08:14:41.59#ibcon#read 3, iclass 6, count 0 2006.239.08:14:41.59#ibcon#about to read 4, iclass 6, count 0 2006.239.08:14:41.59#ibcon#read 4, iclass 6, count 0 2006.239.08:14:41.59#ibcon#about to read 5, iclass 6, count 0 2006.239.08:14:41.59#ibcon#read 5, iclass 6, count 0 2006.239.08:14:41.59#ibcon#about to read 6, iclass 6, count 0 2006.239.08:14:41.59#ibcon#read 6, iclass 6, count 0 2006.239.08:14:41.59#ibcon#end of sib2, iclass 6, count 0 2006.239.08:14:41.59#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:14:41.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:14:41.59#ibcon#[27=USB\r\n] 2006.239.08:14:41.59#ibcon#*before write, iclass 6, count 0 2006.239.08:14:41.59#ibcon#enter sib2, iclass 6, count 0 2006.239.08:14:41.59#ibcon#flushed, iclass 6, count 0 2006.239.08:14:41.59#ibcon#about to write, iclass 6, count 0 2006.239.08:14:41.59#ibcon#wrote, iclass 6, count 0 2006.239.08:14:41.59#ibcon#about to read 3, iclass 6, count 0 2006.239.08:14:41.62#ibcon#read 3, iclass 6, count 0 2006.239.08:14:41.62#ibcon#about to read 4, iclass 6, count 0 2006.239.08:14:41.62#ibcon#read 4, iclass 6, count 0 2006.239.08:14:41.62#ibcon#about to read 5, iclass 6, count 0 2006.239.08:14:41.62#ibcon#read 5, iclass 6, count 0 2006.239.08:14:41.62#ibcon#about to read 6, iclass 6, count 0 2006.239.08:14:41.62#ibcon#read 6, iclass 6, count 0 2006.239.08:14:41.62#ibcon#end of sib2, iclass 6, count 0 2006.239.08:14:41.62#ibcon#*after write, iclass 6, count 0 2006.239.08:14:41.62#ibcon#*before return 0, iclass 6, count 0 2006.239.08:14:41.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:14:41.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:14:41.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:14:41.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:14:41.62$vc4f8/vblo=4,712.99 2006.239.08:14:41.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.08:14:41.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.08:14:41.62#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:41.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:14:41.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:14:41.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:14:41.62#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:14:41.62#ibcon#first serial, iclass 10, count 0 2006.239.08:14:41.62#ibcon#enter sib2, iclass 10, count 0 2006.239.08:14:41.62#ibcon#flushed, iclass 10, count 0 2006.239.08:14:41.62#ibcon#about to write, iclass 10, count 0 2006.239.08:14:41.62#ibcon#wrote, iclass 10, count 0 2006.239.08:14:41.62#ibcon#about to read 3, iclass 10, count 0 2006.239.08:14:41.63#ibcon#read 3, iclass 10, count 0 2006.239.08:14:41.63#ibcon#about to read 4, iclass 10, count 0 2006.239.08:14:41.63#ibcon#read 4, iclass 10, count 0 2006.239.08:14:41.63#ibcon#about to read 5, iclass 10, count 0 2006.239.08:14:41.63#ibcon#read 5, iclass 10, count 0 2006.239.08:14:41.63#ibcon#about to read 6, iclass 10, count 0 2006.239.08:14:41.63#ibcon#read 6, iclass 10, count 0 2006.239.08:14:41.63#ibcon#end of sib2, iclass 10, count 0 2006.239.08:14:41.63#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:14:41.63#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:14:41.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:14:41.63#ibcon#*before write, iclass 10, count 0 2006.239.08:14:41.63#ibcon#enter sib2, iclass 10, count 0 2006.239.08:14:41.63#ibcon#flushed, iclass 10, count 0 2006.239.08:14:41.63#ibcon#about to write, iclass 10, count 0 2006.239.08:14:41.63#ibcon#wrote, iclass 10, count 0 2006.239.08:14:41.63#ibcon#about to read 3, iclass 10, count 0 2006.239.08:14:41.67#ibcon#read 3, iclass 10, count 0 2006.239.08:14:41.67#ibcon#about to read 4, iclass 10, count 0 2006.239.08:14:41.67#ibcon#read 4, iclass 10, count 0 2006.239.08:14:41.67#ibcon#about to read 5, iclass 10, count 0 2006.239.08:14:41.67#ibcon#read 5, iclass 10, count 0 2006.239.08:14:41.67#ibcon#about to read 6, iclass 10, count 0 2006.239.08:14:41.67#ibcon#read 6, iclass 10, count 0 2006.239.08:14:41.67#ibcon#end of sib2, iclass 10, count 0 2006.239.08:14:41.67#ibcon#*after write, iclass 10, count 0 2006.239.08:14:41.67#ibcon#*before return 0, iclass 10, count 0 2006.239.08:14:41.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:14:41.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:14:41.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:14:41.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:14:41.67$vc4f8/vb=4,4 2006.239.08:14:41.67#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.08:14:41.67#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.08:14:41.67#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:41.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:14:41.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:14:41.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:14:41.74#ibcon#enter wrdev, iclass 12, count 2 2006.239.08:14:41.74#ibcon#first serial, iclass 12, count 2 2006.239.08:14:41.74#ibcon#enter sib2, iclass 12, count 2 2006.239.08:14:41.74#ibcon#flushed, iclass 12, count 2 2006.239.08:14:41.74#ibcon#about to write, iclass 12, count 2 2006.239.08:14:41.74#ibcon#wrote, iclass 12, count 2 2006.239.08:14:41.74#ibcon#about to read 3, iclass 12, count 2 2006.239.08:14:41.76#ibcon#read 3, iclass 12, count 2 2006.239.08:14:41.76#ibcon#about to read 4, iclass 12, count 2 2006.239.08:14:41.76#ibcon#read 4, iclass 12, count 2 2006.239.08:14:41.76#ibcon#about to read 5, iclass 12, count 2 2006.239.08:14:41.76#ibcon#read 5, iclass 12, count 2 2006.239.08:14:41.76#ibcon#about to read 6, iclass 12, count 2 2006.239.08:14:41.76#ibcon#read 6, iclass 12, count 2 2006.239.08:14:41.76#ibcon#end of sib2, iclass 12, count 2 2006.239.08:14:41.76#ibcon#*mode == 0, iclass 12, count 2 2006.239.08:14:41.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.08:14:41.76#ibcon#[27=AT04-04\r\n] 2006.239.08:14:41.76#ibcon#*before write, iclass 12, count 2 2006.239.08:14:41.76#ibcon#enter sib2, iclass 12, count 2 2006.239.08:14:41.76#ibcon#flushed, iclass 12, count 2 2006.239.08:14:41.76#ibcon#about to write, iclass 12, count 2 2006.239.08:14:41.76#ibcon#wrote, iclass 12, count 2 2006.239.08:14:41.76#ibcon#about to read 3, iclass 12, count 2 2006.239.08:14:41.79#ibcon#read 3, iclass 12, count 2 2006.239.08:14:41.79#ibcon#about to read 4, iclass 12, count 2 2006.239.08:14:41.79#ibcon#read 4, iclass 12, count 2 2006.239.08:14:41.79#ibcon#about to read 5, iclass 12, count 2 2006.239.08:14:41.79#ibcon#read 5, iclass 12, count 2 2006.239.08:14:41.79#ibcon#about to read 6, iclass 12, count 2 2006.239.08:14:41.79#ibcon#read 6, iclass 12, count 2 2006.239.08:14:41.79#ibcon#end of sib2, iclass 12, count 2 2006.239.08:14:41.79#ibcon#*after write, iclass 12, count 2 2006.239.08:14:41.79#ibcon#*before return 0, iclass 12, count 2 2006.239.08:14:41.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:14:41.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:14:41.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.08:14:41.79#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:41.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:14:41.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:14:41.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:14:41.91#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:14:41.91#ibcon#first serial, iclass 12, count 0 2006.239.08:14:41.91#ibcon#enter sib2, iclass 12, count 0 2006.239.08:14:41.91#ibcon#flushed, iclass 12, count 0 2006.239.08:14:41.91#ibcon#about to write, iclass 12, count 0 2006.239.08:14:41.91#ibcon#wrote, iclass 12, count 0 2006.239.08:14:41.91#ibcon#about to read 3, iclass 12, count 0 2006.239.08:14:41.93#ibcon#read 3, iclass 12, count 0 2006.239.08:14:41.93#ibcon#about to read 4, iclass 12, count 0 2006.239.08:14:41.93#ibcon#read 4, iclass 12, count 0 2006.239.08:14:41.93#ibcon#about to read 5, iclass 12, count 0 2006.239.08:14:41.93#ibcon#read 5, iclass 12, count 0 2006.239.08:14:41.93#ibcon#about to read 6, iclass 12, count 0 2006.239.08:14:41.93#ibcon#read 6, iclass 12, count 0 2006.239.08:14:41.93#ibcon#end of sib2, iclass 12, count 0 2006.239.08:14:41.93#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:14:41.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:14:41.93#ibcon#[27=USB\r\n] 2006.239.08:14:41.93#ibcon#*before write, iclass 12, count 0 2006.239.08:14:41.93#ibcon#enter sib2, iclass 12, count 0 2006.239.08:14:41.93#ibcon#flushed, iclass 12, count 0 2006.239.08:14:41.93#ibcon#about to write, iclass 12, count 0 2006.239.08:14:41.93#ibcon#wrote, iclass 12, count 0 2006.239.08:14:41.93#ibcon#about to read 3, iclass 12, count 0 2006.239.08:14:41.96#ibcon#read 3, iclass 12, count 0 2006.239.08:14:41.96#ibcon#about to read 4, iclass 12, count 0 2006.239.08:14:41.96#ibcon#read 4, iclass 12, count 0 2006.239.08:14:41.96#ibcon#about to read 5, iclass 12, count 0 2006.239.08:14:41.96#ibcon#read 5, iclass 12, count 0 2006.239.08:14:41.96#ibcon#about to read 6, iclass 12, count 0 2006.239.08:14:41.96#ibcon#read 6, iclass 12, count 0 2006.239.08:14:41.96#ibcon#end of sib2, iclass 12, count 0 2006.239.08:14:41.96#ibcon#*after write, iclass 12, count 0 2006.239.08:14:41.96#ibcon#*before return 0, iclass 12, count 0 2006.239.08:14:41.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:14:41.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:14:41.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:14:41.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:14:41.96$vc4f8/vblo=5,744.99 2006.239.08:14:41.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.08:14:41.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.08:14:41.96#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:41.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:41.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:41.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:41.96#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:14:41.96#ibcon#first serial, iclass 14, count 0 2006.239.08:14:41.96#ibcon#enter sib2, iclass 14, count 0 2006.239.08:14:41.96#ibcon#flushed, iclass 14, count 0 2006.239.08:14:41.96#ibcon#about to write, iclass 14, count 0 2006.239.08:14:41.96#ibcon#wrote, iclass 14, count 0 2006.239.08:14:41.96#ibcon#about to read 3, iclass 14, count 0 2006.239.08:14:41.98#ibcon#read 3, iclass 14, count 0 2006.239.08:14:41.98#ibcon#about to read 4, iclass 14, count 0 2006.239.08:14:41.98#ibcon#read 4, iclass 14, count 0 2006.239.08:14:41.98#ibcon#about to read 5, iclass 14, count 0 2006.239.08:14:41.98#ibcon#read 5, iclass 14, count 0 2006.239.08:14:41.98#ibcon#about to read 6, iclass 14, count 0 2006.239.08:14:41.98#ibcon#read 6, iclass 14, count 0 2006.239.08:14:41.98#ibcon#end of sib2, iclass 14, count 0 2006.239.08:14:41.98#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:14:41.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:14:41.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:14:41.98#ibcon#*before write, iclass 14, count 0 2006.239.08:14:41.98#ibcon#enter sib2, iclass 14, count 0 2006.239.08:14:41.98#ibcon#flushed, iclass 14, count 0 2006.239.08:14:41.98#ibcon#about to write, iclass 14, count 0 2006.239.08:14:41.98#ibcon#wrote, iclass 14, count 0 2006.239.08:14:41.98#ibcon#about to read 3, iclass 14, count 0 2006.239.08:14:42.02#ibcon#read 3, iclass 14, count 0 2006.239.08:14:42.02#ibcon#about to read 4, iclass 14, count 0 2006.239.08:14:42.02#ibcon#read 4, iclass 14, count 0 2006.239.08:14:42.02#ibcon#about to read 5, iclass 14, count 0 2006.239.08:14:42.02#ibcon#read 5, iclass 14, count 0 2006.239.08:14:42.02#ibcon#about to read 6, iclass 14, count 0 2006.239.08:14:42.02#ibcon#read 6, iclass 14, count 0 2006.239.08:14:42.02#ibcon#end of sib2, iclass 14, count 0 2006.239.08:14:42.02#ibcon#*after write, iclass 14, count 0 2006.239.08:14:42.02#ibcon#*before return 0, iclass 14, count 0 2006.239.08:14:42.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:42.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:14:42.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:14:42.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:14:42.02$vc4f8/vb=5,4 2006.239.08:14:42.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.08:14:42.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.08:14:42.02#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:42.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:42.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:42.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:42.08#ibcon#enter wrdev, iclass 16, count 2 2006.239.08:14:42.08#ibcon#first serial, iclass 16, count 2 2006.239.08:14:42.08#ibcon#enter sib2, iclass 16, count 2 2006.239.08:14:42.08#ibcon#flushed, iclass 16, count 2 2006.239.08:14:42.08#ibcon#about to write, iclass 16, count 2 2006.239.08:14:42.08#ibcon#wrote, iclass 16, count 2 2006.239.08:14:42.08#ibcon#about to read 3, iclass 16, count 2 2006.239.08:14:42.10#ibcon#read 3, iclass 16, count 2 2006.239.08:14:42.10#ibcon#about to read 4, iclass 16, count 2 2006.239.08:14:42.10#ibcon#read 4, iclass 16, count 2 2006.239.08:14:42.10#ibcon#about to read 5, iclass 16, count 2 2006.239.08:14:42.10#ibcon#read 5, iclass 16, count 2 2006.239.08:14:42.10#ibcon#about to read 6, iclass 16, count 2 2006.239.08:14:42.10#ibcon#read 6, iclass 16, count 2 2006.239.08:14:42.10#ibcon#end of sib2, iclass 16, count 2 2006.239.08:14:42.10#ibcon#*mode == 0, iclass 16, count 2 2006.239.08:14:42.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.08:14:42.10#ibcon#[27=AT05-04\r\n] 2006.239.08:14:42.10#ibcon#*before write, iclass 16, count 2 2006.239.08:14:42.10#ibcon#enter sib2, iclass 16, count 2 2006.239.08:14:42.10#ibcon#flushed, iclass 16, count 2 2006.239.08:14:42.10#ibcon#about to write, iclass 16, count 2 2006.239.08:14:42.10#ibcon#wrote, iclass 16, count 2 2006.239.08:14:42.10#ibcon#about to read 3, iclass 16, count 2 2006.239.08:14:42.13#ibcon#read 3, iclass 16, count 2 2006.239.08:14:42.13#ibcon#about to read 4, iclass 16, count 2 2006.239.08:14:42.13#ibcon#read 4, iclass 16, count 2 2006.239.08:14:42.13#ibcon#about to read 5, iclass 16, count 2 2006.239.08:14:42.13#ibcon#read 5, iclass 16, count 2 2006.239.08:14:42.13#ibcon#about to read 6, iclass 16, count 2 2006.239.08:14:42.13#ibcon#read 6, iclass 16, count 2 2006.239.08:14:42.13#ibcon#end of sib2, iclass 16, count 2 2006.239.08:14:42.13#ibcon#*after write, iclass 16, count 2 2006.239.08:14:42.13#ibcon#*before return 0, iclass 16, count 2 2006.239.08:14:42.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:42.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:14:42.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.08:14:42.13#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:42.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:42.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:42.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:42.25#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:14:42.25#ibcon#first serial, iclass 16, count 0 2006.239.08:14:42.25#ibcon#enter sib2, iclass 16, count 0 2006.239.08:14:42.25#ibcon#flushed, iclass 16, count 0 2006.239.08:14:42.25#ibcon#about to write, iclass 16, count 0 2006.239.08:14:42.25#ibcon#wrote, iclass 16, count 0 2006.239.08:14:42.25#ibcon#about to read 3, iclass 16, count 0 2006.239.08:14:42.27#ibcon#read 3, iclass 16, count 0 2006.239.08:14:42.27#ibcon#about to read 4, iclass 16, count 0 2006.239.08:14:42.27#ibcon#read 4, iclass 16, count 0 2006.239.08:14:42.27#ibcon#about to read 5, iclass 16, count 0 2006.239.08:14:42.27#ibcon#read 5, iclass 16, count 0 2006.239.08:14:42.27#ibcon#about to read 6, iclass 16, count 0 2006.239.08:14:42.27#ibcon#read 6, iclass 16, count 0 2006.239.08:14:42.27#ibcon#end of sib2, iclass 16, count 0 2006.239.08:14:42.27#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:14:42.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:14:42.27#ibcon#[27=USB\r\n] 2006.239.08:14:42.27#ibcon#*before write, iclass 16, count 0 2006.239.08:14:42.27#ibcon#enter sib2, iclass 16, count 0 2006.239.08:14:42.27#ibcon#flushed, iclass 16, count 0 2006.239.08:14:42.27#ibcon#about to write, iclass 16, count 0 2006.239.08:14:42.27#ibcon#wrote, iclass 16, count 0 2006.239.08:14:42.27#ibcon#about to read 3, iclass 16, count 0 2006.239.08:14:42.30#ibcon#read 3, iclass 16, count 0 2006.239.08:14:42.30#ibcon#about to read 4, iclass 16, count 0 2006.239.08:14:42.30#ibcon#read 4, iclass 16, count 0 2006.239.08:14:42.30#ibcon#about to read 5, iclass 16, count 0 2006.239.08:14:42.30#ibcon#read 5, iclass 16, count 0 2006.239.08:14:42.30#ibcon#about to read 6, iclass 16, count 0 2006.239.08:14:42.30#ibcon#read 6, iclass 16, count 0 2006.239.08:14:42.30#ibcon#end of sib2, iclass 16, count 0 2006.239.08:14:42.30#ibcon#*after write, iclass 16, count 0 2006.239.08:14:42.30#ibcon#*before return 0, iclass 16, count 0 2006.239.08:14:42.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:42.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:14:42.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:14:42.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:14:42.30$vc4f8/vblo=6,752.99 2006.239.08:14:42.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:14:42.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:14:42.30#ibcon#ireg 17 cls_cnt 0 2006.239.08:14:42.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:42.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:42.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:42.30#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:14:42.30#ibcon#first serial, iclass 18, count 0 2006.239.08:14:42.30#ibcon#enter sib2, iclass 18, count 0 2006.239.08:14:42.30#ibcon#flushed, iclass 18, count 0 2006.239.08:14:42.30#ibcon#about to write, iclass 18, count 0 2006.239.08:14:42.30#ibcon#wrote, iclass 18, count 0 2006.239.08:14:42.30#ibcon#about to read 3, iclass 18, count 0 2006.239.08:14:42.32#ibcon#read 3, iclass 18, count 0 2006.239.08:14:42.32#ibcon#about to read 4, iclass 18, count 0 2006.239.08:14:42.32#ibcon#read 4, iclass 18, count 0 2006.239.08:14:42.32#ibcon#about to read 5, iclass 18, count 0 2006.239.08:14:42.32#ibcon#read 5, iclass 18, count 0 2006.239.08:14:42.32#ibcon#about to read 6, iclass 18, count 0 2006.239.08:14:42.32#ibcon#read 6, iclass 18, count 0 2006.239.08:14:42.32#ibcon#end of sib2, iclass 18, count 0 2006.239.08:14:42.32#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:14:42.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:14:42.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:14:42.32#ibcon#*before write, iclass 18, count 0 2006.239.08:14:42.32#ibcon#enter sib2, iclass 18, count 0 2006.239.08:14:42.32#ibcon#flushed, iclass 18, count 0 2006.239.08:14:42.32#ibcon#about to write, iclass 18, count 0 2006.239.08:14:42.32#ibcon#wrote, iclass 18, count 0 2006.239.08:14:42.32#ibcon#about to read 3, iclass 18, count 0 2006.239.08:14:42.36#ibcon#read 3, iclass 18, count 0 2006.239.08:14:42.36#ibcon#about to read 4, iclass 18, count 0 2006.239.08:14:42.36#ibcon#read 4, iclass 18, count 0 2006.239.08:14:42.36#ibcon#about to read 5, iclass 18, count 0 2006.239.08:14:42.36#ibcon#read 5, iclass 18, count 0 2006.239.08:14:42.36#ibcon#about to read 6, iclass 18, count 0 2006.239.08:14:42.36#ibcon#read 6, iclass 18, count 0 2006.239.08:14:42.36#ibcon#end of sib2, iclass 18, count 0 2006.239.08:14:42.36#ibcon#*after write, iclass 18, count 0 2006.239.08:14:42.36#ibcon#*before return 0, iclass 18, count 0 2006.239.08:14:42.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:42.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:14:42.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:14:42.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:14:42.36$vc4f8/vb=6,4 2006.239.08:14:42.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.08:14:42.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.08:14:42.36#ibcon#ireg 11 cls_cnt 2 2006.239.08:14:42.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:42.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:42.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:42.42#ibcon#enter wrdev, iclass 20, count 2 2006.239.08:14:42.42#ibcon#first serial, iclass 20, count 2 2006.239.08:14:42.42#ibcon#enter sib2, iclass 20, count 2 2006.239.08:14:42.42#ibcon#flushed, iclass 20, count 2 2006.239.08:14:42.42#ibcon#about to write, iclass 20, count 2 2006.239.08:14:42.42#ibcon#wrote, iclass 20, count 2 2006.239.08:14:42.42#ibcon#about to read 3, iclass 20, count 2 2006.239.08:14:42.45#ibcon#read 3, iclass 20, count 2 2006.239.08:14:42.45#ibcon#about to read 4, iclass 20, count 2 2006.239.08:14:42.45#ibcon#read 4, iclass 20, count 2 2006.239.08:14:42.45#ibcon#about to read 5, iclass 20, count 2 2006.239.08:14:42.45#ibcon#read 5, iclass 20, count 2 2006.239.08:14:42.45#ibcon#about to read 6, iclass 20, count 2 2006.239.08:14:42.45#ibcon#read 6, iclass 20, count 2 2006.239.08:14:42.45#ibcon#end of sib2, iclass 20, count 2 2006.239.08:14:42.45#ibcon#*mode == 0, iclass 20, count 2 2006.239.08:14:42.45#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.08:14:42.45#ibcon#[27=AT06-04\r\n] 2006.239.08:14:42.45#ibcon#*before write, iclass 20, count 2 2006.239.08:14:42.45#ibcon#enter sib2, iclass 20, count 2 2006.239.08:14:42.45#ibcon#flushed, iclass 20, count 2 2006.239.08:14:42.45#ibcon#about to write, iclass 20, count 2 2006.239.08:14:42.45#ibcon#wrote, iclass 20, count 2 2006.239.08:14:42.45#ibcon#about to read 3, iclass 20, count 2 2006.239.08:14:42.48#ibcon#read 3, iclass 20, count 2 2006.239.08:14:42.48#ibcon#about to read 4, iclass 20, count 2 2006.239.08:14:42.48#ibcon#read 4, iclass 20, count 2 2006.239.08:14:42.48#ibcon#about to read 5, iclass 20, count 2 2006.239.08:14:42.48#ibcon#read 5, iclass 20, count 2 2006.239.08:14:42.48#ibcon#about to read 6, iclass 20, count 2 2006.239.08:14:42.48#ibcon#read 6, iclass 20, count 2 2006.239.08:14:42.48#ibcon#end of sib2, iclass 20, count 2 2006.239.08:14:42.48#ibcon#*after write, iclass 20, count 2 2006.239.08:14:42.48#ibcon#*before return 0, iclass 20, count 2 2006.239.08:14:42.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:42.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:14:42.48#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.08:14:42.48#ibcon#ireg 7 cls_cnt 0 2006.239.08:14:42.48#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:42.60#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:42.60#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:42.60#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:14:42.60#ibcon#first serial, iclass 20, count 0 2006.239.08:14:42.60#ibcon#enter sib2, iclass 20, count 0 2006.239.08:14:42.60#ibcon#flushed, iclass 20, count 0 2006.239.08:14:42.60#ibcon#about to write, iclass 20, count 0 2006.239.08:14:42.60#ibcon#wrote, iclass 20, count 0 2006.239.08:14:42.60#ibcon#about to read 3, iclass 20, count 0 2006.239.08:14:42.62#ibcon#read 3, iclass 20, count 0 2006.239.08:14:42.62#ibcon#about to read 4, iclass 20, count 0 2006.239.08:14:42.62#ibcon#read 4, iclass 20, count 0 2006.239.08:14:42.62#ibcon#about to read 5, iclass 20, count 0 2006.239.08:14:42.62#ibcon#read 5, iclass 20, count 0 2006.239.08:14:42.62#ibcon#about to read 6, iclass 20, count 0 2006.239.08:14:42.62#ibcon#read 6, iclass 20, count 0 2006.239.08:14:42.62#ibcon#end of sib2, iclass 20, count 0 2006.239.08:14:42.62#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:14:42.62#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:14:42.62#ibcon#[27=USB\r\n] 2006.239.08:14:42.62#ibcon#*before write, iclass 20, count 0 2006.239.08:14:42.62#ibcon#enter sib2, iclass 20, count 0 2006.239.08:14:42.62#ibcon#flushed, iclass 20, count 0 2006.239.08:14:42.62#ibcon#about to write, iclass 20, count 0 2006.239.08:14:42.62#ibcon#wrote, iclass 20, count 0 2006.239.08:14:42.62#ibcon#about to read 3, iclass 20, count 0 2006.239.08:14:42.65#ibcon#read 3, iclass 20, count 0 2006.239.08:14:42.65#ibcon#about to read 4, iclass 20, count 0 2006.239.08:14:42.65#ibcon#read 4, iclass 20, count 0 2006.239.08:14:42.65#ibcon#about to read 5, iclass 20, count 0 2006.239.08:14:42.65#ibcon#read 5, iclass 20, count 0 2006.239.08:14:42.65#ibcon#about to read 6, iclass 20, count 0 2006.239.08:14:42.65#ibcon#read 6, iclass 20, count 0 2006.239.08:14:42.65#ibcon#end of sib2, iclass 20, count 0 2006.239.08:14:42.65#ibcon#*after write, iclass 20, count 0 2006.239.08:14:42.65#ibcon#*before return 0, iclass 20, count 0 2006.239.08:14:42.65#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:42.65#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:14:42.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:14:42.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:14:42.65$vc4f8/vabw=wide 2006.239.08:14:42.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.08:14:42.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.08:14:42.65#ibcon#ireg 8 cls_cnt 0 2006.239.08:14:42.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:42.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:42.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:42.65#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:14:42.65#ibcon#first serial, iclass 22, count 0 2006.239.08:14:42.65#ibcon#enter sib2, iclass 22, count 0 2006.239.08:14:42.65#ibcon#flushed, iclass 22, count 0 2006.239.08:14:42.65#ibcon#about to write, iclass 22, count 0 2006.239.08:14:42.65#ibcon#wrote, iclass 22, count 0 2006.239.08:14:42.65#ibcon#about to read 3, iclass 22, count 0 2006.239.08:14:42.67#ibcon#read 3, iclass 22, count 0 2006.239.08:14:42.67#ibcon#about to read 4, iclass 22, count 0 2006.239.08:14:42.67#ibcon#read 4, iclass 22, count 0 2006.239.08:14:42.67#ibcon#about to read 5, iclass 22, count 0 2006.239.08:14:42.67#ibcon#read 5, iclass 22, count 0 2006.239.08:14:42.67#ibcon#about to read 6, iclass 22, count 0 2006.239.08:14:42.67#ibcon#read 6, iclass 22, count 0 2006.239.08:14:42.67#ibcon#end of sib2, iclass 22, count 0 2006.239.08:14:42.67#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:14:42.67#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:14:42.67#ibcon#[25=BW32\r\n] 2006.239.08:14:42.67#ibcon#*before write, iclass 22, count 0 2006.239.08:14:42.67#ibcon#enter sib2, iclass 22, count 0 2006.239.08:14:42.67#ibcon#flushed, iclass 22, count 0 2006.239.08:14:42.67#ibcon#about to write, iclass 22, count 0 2006.239.08:14:42.67#ibcon#wrote, iclass 22, count 0 2006.239.08:14:42.67#ibcon#about to read 3, iclass 22, count 0 2006.239.08:14:42.70#ibcon#read 3, iclass 22, count 0 2006.239.08:14:42.70#ibcon#about to read 4, iclass 22, count 0 2006.239.08:14:42.70#ibcon#read 4, iclass 22, count 0 2006.239.08:14:42.70#ibcon#about to read 5, iclass 22, count 0 2006.239.08:14:42.70#ibcon#read 5, iclass 22, count 0 2006.239.08:14:42.70#ibcon#about to read 6, iclass 22, count 0 2006.239.08:14:42.70#ibcon#read 6, iclass 22, count 0 2006.239.08:14:42.70#ibcon#end of sib2, iclass 22, count 0 2006.239.08:14:42.70#ibcon#*after write, iclass 22, count 0 2006.239.08:14:42.70#ibcon#*before return 0, iclass 22, count 0 2006.239.08:14:42.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:42.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:14:42.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:14:42.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:14:42.70$vc4f8/vbbw=wide 2006.239.08:14:42.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.08:14:42.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.08:14:42.70#ibcon#ireg 8 cls_cnt 0 2006.239.08:14:42.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:14:42.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:14:42.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:14:42.77#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:14:42.77#ibcon#first serial, iclass 24, count 0 2006.239.08:14:42.77#ibcon#enter sib2, iclass 24, count 0 2006.239.08:14:42.77#ibcon#flushed, iclass 24, count 0 2006.239.08:14:42.77#ibcon#about to write, iclass 24, count 0 2006.239.08:14:42.77#ibcon#wrote, iclass 24, count 0 2006.239.08:14:42.77#ibcon#about to read 3, iclass 24, count 0 2006.239.08:14:42.79#ibcon#read 3, iclass 24, count 0 2006.239.08:14:42.79#ibcon#about to read 4, iclass 24, count 0 2006.239.08:14:42.79#ibcon#read 4, iclass 24, count 0 2006.239.08:14:42.79#ibcon#about to read 5, iclass 24, count 0 2006.239.08:14:42.79#ibcon#read 5, iclass 24, count 0 2006.239.08:14:42.79#ibcon#about to read 6, iclass 24, count 0 2006.239.08:14:42.79#ibcon#read 6, iclass 24, count 0 2006.239.08:14:42.79#ibcon#end of sib2, iclass 24, count 0 2006.239.08:14:42.79#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:14:42.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:14:42.79#ibcon#[27=BW32\r\n] 2006.239.08:14:42.79#ibcon#*before write, iclass 24, count 0 2006.239.08:14:42.79#ibcon#enter sib2, iclass 24, count 0 2006.239.08:14:42.79#ibcon#flushed, iclass 24, count 0 2006.239.08:14:42.79#ibcon#about to write, iclass 24, count 0 2006.239.08:14:42.79#ibcon#wrote, iclass 24, count 0 2006.239.08:14:42.79#ibcon#about to read 3, iclass 24, count 0 2006.239.08:14:42.82#ibcon#read 3, iclass 24, count 0 2006.239.08:14:42.82#ibcon#about to read 4, iclass 24, count 0 2006.239.08:14:42.82#ibcon#read 4, iclass 24, count 0 2006.239.08:14:42.82#ibcon#about to read 5, iclass 24, count 0 2006.239.08:14:42.82#ibcon#read 5, iclass 24, count 0 2006.239.08:14:42.82#ibcon#about to read 6, iclass 24, count 0 2006.239.08:14:42.82#ibcon#read 6, iclass 24, count 0 2006.239.08:14:42.82#ibcon#end of sib2, iclass 24, count 0 2006.239.08:14:42.82#ibcon#*after write, iclass 24, count 0 2006.239.08:14:42.82#ibcon#*before return 0, iclass 24, count 0 2006.239.08:14:42.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:14:42.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:14:42.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:14:42.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:14:42.82$4f8m12a/ifd4f 2006.239.08:14:42.82$ifd4f/lo= 2006.239.08:14:42.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:14:42.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:14:42.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:14:42.82$ifd4f/patch= 2006.239.08:14:42.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:14:42.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:14:42.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:14:42.83$4f8m12a/"form=m,16.000,1:2 2006.239.08:14:42.83$4f8m12a/"tpicd 2006.239.08:14:42.83$4f8m12a/echo=off 2006.239.08:14:42.83$4f8m12a/xlog=off 2006.239.08:14:42.83:!2006.239.08:15:10 2006.239.08:14:45.13#trakl#Source acquired 2006.239.08:14:45.13#flagr#flagr/antenna,acquired 2006.239.08:15:10.01:preob 2006.239.08:15:11.13/onsource/TRACKING 2006.239.08:15:11.13:!2006.239.08:15:20 2006.239.08:15:20.00:data_valid=on 2006.239.08:15:20.00:midob 2006.239.08:15:20.13/onsource/TRACKING 2006.239.08:15:20.13/wx/25.04,1011.5,80 2006.239.08:15:20.21/cable/+6.4141E-03 2006.239.08:15:21.30/va/01,08,usb,yes,31,32 2006.239.08:15:21.30/va/02,07,usb,yes,30,32 2006.239.08:15:21.30/va/03,07,usb,yes,29,29 2006.239.08:15:21.30/va/04,07,usb,yes,32,35 2006.239.08:15:21.30/va/05,08,usb,yes,29,31 2006.239.08:15:21.30/va/06,07,usb,yes,31,31 2006.239.08:15:21.30/va/07,07,usb,yes,31,31 2006.239.08:15:21.30/va/08,07,usb,yes,34,33 2006.239.08:15:21.53/valo/01,532.99,yes,locked 2006.239.08:15:21.53/valo/02,572.99,yes,locked 2006.239.08:15:21.53/valo/03,672.99,yes,locked 2006.239.08:15:21.53/valo/04,832.99,yes,locked 2006.239.08:15:21.53/valo/05,652.99,yes,locked 2006.239.08:15:21.53/valo/06,772.99,yes,locked 2006.239.08:15:21.53/valo/07,832.99,yes,locked 2006.239.08:15:21.53/valo/08,852.99,yes,locked 2006.239.08:15:22.62/vb/01,04,usb,yes,30,29 2006.239.08:15:22.62/vb/02,04,usb,yes,32,33 2006.239.08:15:22.62/vb/03,04,usb,yes,28,32 2006.239.08:15:22.62/vb/04,04,usb,yes,29,29 2006.239.08:15:22.62/vb/05,04,usb,yes,27,31 2006.239.08:15:22.62/vb/06,04,usb,yes,28,31 2006.239.08:15:22.62/vb/07,04,usb,yes,31,30 2006.239.08:15:22.62/vb/08,04,usb,yes,28,31 2006.239.08:15:22.86/vblo/01,632.99,yes,locked 2006.239.08:15:22.86/vblo/02,640.99,yes,locked 2006.239.08:15:22.86/vblo/03,656.99,yes,locked 2006.239.08:15:22.86/vblo/04,712.99,yes,locked 2006.239.08:15:22.86/vblo/05,744.99,yes,locked 2006.239.08:15:22.86/vblo/06,752.99,yes,locked 2006.239.08:15:22.86/vblo/07,734.99,yes,locked 2006.239.08:15:22.86/vblo/08,744.99,yes,locked 2006.239.08:15:23.01/vabw/8 2006.239.08:15:23.16/vbbw/8 2006.239.08:15:23.25/xfe/off,on,13.0 2006.239.08:15:23.62/ifatt/23,28,28,28 2006.239.08:15:24.07/fmout-gps/S +4.42E-07 2006.239.08:15:24.12:!2006.239.08:16:20 2006.239.08:16:20.01:data_valid=off 2006.239.08:16:20.02:postob 2006.239.08:16:20.18/cable/+6.4141E-03 2006.239.08:16:20.19/wx/25.02,1011.5,81 2006.239.08:16:20.27/fmout-gps/S +4.42E-07 2006.239.08:16:20.28:scan_name=239-0817,k06239,60 2006.239.08:16:20.28:source=3c418,203837.03,511912.7,2000.0,cw 2006.239.08:16:22.14#flagr#flagr/antenna,new-source 2006.239.08:16:22.15:checkk5 2006.239.08:16:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:16:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:16:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:16:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:16:24.04/chk_obsdata//k5ts1/T2390815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:16:24.40/chk_obsdata//k5ts2/T2390815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:16:24.78/chk_obsdata//k5ts3/T2390815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:16:25.15/chk_obsdata//k5ts4/T2390815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:16:25.85/k5log//k5ts1_log_newline 2006.239.08:16:26.56/k5log//k5ts2_log_newline 2006.239.08:16:27.26/k5log//k5ts3_log_newline 2006.239.08:16:27.96/k5log//k5ts4_log_newline 2006.239.08:16:27.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:16:27.98:4f8m12a=2 2006.239.08:16:27.98$4f8m12a/echo=on 2006.239.08:16:27.98$4f8m12a/pcalon 2006.239.08:16:27.98$pcalon/"no phase cal control is implemented here 2006.239.08:16:27.98$4f8m12a/"tpicd=stop 2006.239.08:16:27.98$4f8m12a/vc4f8 2006.239.08:16:27.98$vc4f8/valo=1,532.99 2006.239.08:16:27.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.08:16:27.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.08:16:27.99#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:27.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:27.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:27.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:27.99#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:16:27.99#ibcon#first serial, iclass 31, count 0 2006.239.08:16:27.99#ibcon#enter sib2, iclass 31, count 0 2006.239.08:16:27.99#ibcon#flushed, iclass 31, count 0 2006.239.08:16:27.99#ibcon#about to write, iclass 31, count 0 2006.239.08:16:27.99#ibcon#wrote, iclass 31, count 0 2006.239.08:16:27.99#ibcon#about to read 3, iclass 31, count 0 2006.239.08:16:28.03#ibcon#read 3, iclass 31, count 0 2006.239.08:16:28.03#ibcon#about to read 4, iclass 31, count 0 2006.239.08:16:28.03#ibcon#read 4, iclass 31, count 0 2006.239.08:16:28.03#ibcon#about to read 5, iclass 31, count 0 2006.239.08:16:28.03#ibcon#read 5, iclass 31, count 0 2006.239.08:16:28.03#ibcon#about to read 6, iclass 31, count 0 2006.239.08:16:28.03#ibcon#read 6, iclass 31, count 0 2006.239.08:16:28.03#ibcon#end of sib2, iclass 31, count 0 2006.239.08:16:28.03#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:16:28.03#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:16:28.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:16:28.03#ibcon#*before write, iclass 31, count 0 2006.239.08:16:28.03#ibcon#enter sib2, iclass 31, count 0 2006.239.08:16:28.03#ibcon#flushed, iclass 31, count 0 2006.239.08:16:28.03#ibcon#about to write, iclass 31, count 0 2006.239.08:16:28.03#ibcon#wrote, iclass 31, count 0 2006.239.08:16:28.03#ibcon#about to read 3, iclass 31, count 0 2006.239.08:16:28.08#ibcon#read 3, iclass 31, count 0 2006.239.08:16:28.08#ibcon#about to read 4, iclass 31, count 0 2006.239.08:16:28.08#ibcon#read 4, iclass 31, count 0 2006.239.08:16:28.08#ibcon#about to read 5, iclass 31, count 0 2006.239.08:16:28.08#ibcon#read 5, iclass 31, count 0 2006.239.08:16:28.08#ibcon#about to read 6, iclass 31, count 0 2006.239.08:16:28.08#ibcon#read 6, iclass 31, count 0 2006.239.08:16:28.08#ibcon#end of sib2, iclass 31, count 0 2006.239.08:16:28.08#ibcon#*after write, iclass 31, count 0 2006.239.08:16:28.08#ibcon#*before return 0, iclass 31, count 0 2006.239.08:16:28.08#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:28.08#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:28.08#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:16:28.08#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:16:28.08$vc4f8/va=1,8 2006.239.08:16:28.08#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.08:16:28.08#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.08:16:28.08#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:28.08#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:28.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:28.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:28.08#ibcon#enter wrdev, iclass 33, count 2 2006.239.08:16:28.08#ibcon#first serial, iclass 33, count 2 2006.239.08:16:28.08#ibcon#enter sib2, iclass 33, count 2 2006.239.08:16:28.08#ibcon#flushed, iclass 33, count 2 2006.239.08:16:28.08#ibcon#about to write, iclass 33, count 2 2006.239.08:16:28.08#ibcon#wrote, iclass 33, count 2 2006.239.08:16:28.08#ibcon#about to read 3, iclass 33, count 2 2006.239.08:16:28.11#ibcon#read 3, iclass 33, count 2 2006.239.08:16:28.11#ibcon#about to read 4, iclass 33, count 2 2006.239.08:16:28.11#ibcon#read 4, iclass 33, count 2 2006.239.08:16:28.11#ibcon#about to read 5, iclass 33, count 2 2006.239.08:16:28.11#ibcon#read 5, iclass 33, count 2 2006.239.08:16:28.11#ibcon#about to read 6, iclass 33, count 2 2006.239.08:16:28.11#ibcon#read 6, iclass 33, count 2 2006.239.08:16:28.11#ibcon#end of sib2, iclass 33, count 2 2006.239.08:16:28.11#ibcon#*mode == 0, iclass 33, count 2 2006.239.08:16:28.11#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.08:16:28.11#ibcon#[25=AT01-08\r\n] 2006.239.08:16:28.11#ibcon#*before write, iclass 33, count 2 2006.239.08:16:28.11#ibcon#enter sib2, iclass 33, count 2 2006.239.08:16:28.11#ibcon#flushed, iclass 33, count 2 2006.239.08:16:28.11#ibcon#about to write, iclass 33, count 2 2006.239.08:16:28.11#ibcon#wrote, iclass 33, count 2 2006.239.08:16:28.11#ibcon#about to read 3, iclass 33, count 2 2006.239.08:16:28.14#ibcon#read 3, iclass 33, count 2 2006.239.08:16:28.14#ibcon#about to read 4, iclass 33, count 2 2006.239.08:16:28.14#ibcon#read 4, iclass 33, count 2 2006.239.08:16:28.14#ibcon#about to read 5, iclass 33, count 2 2006.239.08:16:28.14#ibcon#read 5, iclass 33, count 2 2006.239.08:16:28.14#ibcon#about to read 6, iclass 33, count 2 2006.239.08:16:28.14#ibcon#read 6, iclass 33, count 2 2006.239.08:16:28.14#ibcon#end of sib2, iclass 33, count 2 2006.239.08:16:28.14#ibcon#*after write, iclass 33, count 2 2006.239.08:16:28.14#ibcon#*before return 0, iclass 33, count 2 2006.239.08:16:28.14#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:28.14#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:28.14#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.08:16:28.14#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:28.14#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:28.26#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:28.26#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:28.26#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:16:28.26#ibcon#first serial, iclass 33, count 0 2006.239.08:16:28.26#ibcon#enter sib2, iclass 33, count 0 2006.239.08:16:28.26#ibcon#flushed, iclass 33, count 0 2006.239.08:16:28.26#ibcon#about to write, iclass 33, count 0 2006.239.08:16:28.26#ibcon#wrote, iclass 33, count 0 2006.239.08:16:28.26#ibcon#about to read 3, iclass 33, count 0 2006.239.08:16:28.28#ibcon#read 3, iclass 33, count 0 2006.239.08:16:28.28#ibcon#about to read 4, iclass 33, count 0 2006.239.08:16:28.28#ibcon#read 4, iclass 33, count 0 2006.239.08:16:28.28#ibcon#about to read 5, iclass 33, count 0 2006.239.08:16:28.28#ibcon#read 5, iclass 33, count 0 2006.239.08:16:28.28#ibcon#about to read 6, iclass 33, count 0 2006.239.08:16:28.28#ibcon#read 6, iclass 33, count 0 2006.239.08:16:28.28#ibcon#end of sib2, iclass 33, count 0 2006.239.08:16:28.28#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:16:28.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:16:28.28#ibcon#[25=USB\r\n] 2006.239.08:16:28.28#ibcon#*before write, iclass 33, count 0 2006.239.08:16:28.28#ibcon#enter sib2, iclass 33, count 0 2006.239.08:16:28.28#ibcon#flushed, iclass 33, count 0 2006.239.08:16:28.28#ibcon#about to write, iclass 33, count 0 2006.239.08:16:28.28#ibcon#wrote, iclass 33, count 0 2006.239.08:16:28.28#ibcon#about to read 3, iclass 33, count 0 2006.239.08:16:28.31#ibcon#read 3, iclass 33, count 0 2006.239.08:16:28.31#ibcon#about to read 4, iclass 33, count 0 2006.239.08:16:28.31#ibcon#read 4, iclass 33, count 0 2006.239.08:16:28.31#ibcon#about to read 5, iclass 33, count 0 2006.239.08:16:28.31#ibcon#read 5, iclass 33, count 0 2006.239.08:16:28.31#ibcon#about to read 6, iclass 33, count 0 2006.239.08:16:28.31#ibcon#read 6, iclass 33, count 0 2006.239.08:16:28.31#ibcon#end of sib2, iclass 33, count 0 2006.239.08:16:28.31#ibcon#*after write, iclass 33, count 0 2006.239.08:16:28.31#ibcon#*before return 0, iclass 33, count 0 2006.239.08:16:28.31#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:28.31#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:28.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:16:28.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:16:28.31$vc4f8/valo=2,572.99 2006.239.08:16:28.31#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.08:16:28.31#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.08:16:28.31#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:28.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:28.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:28.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:28.31#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:16:28.31#ibcon#first serial, iclass 35, count 0 2006.239.08:16:28.31#ibcon#enter sib2, iclass 35, count 0 2006.239.08:16:28.31#ibcon#flushed, iclass 35, count 0 2006.239.08:16:28.31#ibcon#about to write, iclass 35, count 0 2006.239.08:16:28.31#ibcon#wrote, iclass 35, count 0 2006.239.08:16:28.31#ibcon#about to read 3, iclass 35, count 0 2006.239.08:16:28.34#ibcon#read 3, iclass 35, count 0 2006.239.08:16:28.34#ibcon#about to read 4, iclass 35, count 0 2006.239.08:16:28.34#ibcon#read 4, iclass 35, count 0 2006.239.08:16:28.34#ibcon#about to read 5, iclass 35, count 0 2006.239.08:16:28.34#ibcon#read 5, iclass 35, count 0 2006.239.08:16:28.34#ibcon#about to read 6, iclass 35, count 0 2006.239.08:16:28.34#ibcon#read 6, iclass 35, count 0 2006.239.08:16:28.34#ibcon#end of sib2, iclass 35, count 0 2006.239.08:16:28.34#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:16:28.34#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:16:28.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:16:28.34#ibcon#*before write, iclass 35, count 0 2006.239.08:16:28.34#ibcon#enter sib2, iclass 35, count 0 2006.239.08:16:28.34#ibcon#flushed, iclass 35, count 0 2006.239.08:16:28.34#ibcon#about to write, iclass 35, count 0 2006.239.08:16:28.34#ibcon#wrote, iclass 35, count 0 2006.239.08:16:28.34#ibcon#about to read 3, iclass 35, count 0 2006.239.08:16:28.38#ibcon#read 3, iclass 35, count 0 2006.239.08:16:28.38#ibcon#about to read 4, iclass 35, count 0 2006.239.08:16:28.38#ibcon#read 4, iclass 35, count 0 2006.239.08:16:28.38#ibcon#about to read 5, iclass 35, count 0 2006.239.08:16:28.38#ibcon#read 5, iclass 35, count 0 2006.239.08:16:28.38#ibcon#about to read 6, iclass 35, count 0 2006.239.08:16:28.38#ibcon#read 6, iclass 35, count 0 2006.239.08:16:28.38#ibcon#end of sib2, iclass 35, count 0 2006.239.08:16:28.38#ibcon#*after write, iclass 35, count 0 2006.239.08:16:28.38#ibcon#*before return 0, iclass 35, count 0 2006.239.08:16:28.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:28.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:28.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:16:28.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:16:28.38$vc4f8/va=2,7 2006.239.08:16:28.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.08:16:28.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.08:16:28.38#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:28.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:28.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:28.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:28.43#ibcon#enter wrdev, iclass 37, count 2 2006.239.08:16:28.43#ibcon#first serial, iclass 37, count 2 2006.239.08:16:28.43#ibcon#enter sib2, iclass 37, count 2 2006.239.08:16:28.43#ibcon#flushed, iclass 37, count 2 2006.239.08:16:28.43#ibcon#about to write, iclass 37, count 2 2006.239.08:16:28.43#ibcon#wrote, iclass 37, count 2 2006.239.08:16:28.43#ibcon#about to read 3, iclass 37, count 2 2006.239.08:16:28.46#ibcon#read 3, iclass 37, count 2 2006.239.08:16:28.46#ibcon#about to read 4, iclass 37, count 2 2006.239.08:16:28.46#ibcon#read 4, iclass 37, count 2 2006.239.08:16:28.46#ibcon#about to read 5, iclass 37, count 2 2006.239.08:16:28.46#ibcon#read 5, iclass 37, count 2 2006.239.08:16:28.46#ibcon#about to read 6, iclass 37, count 2 2006.239.08:16:28.46#ibcon#read 6, iclass 37, count 2 2006.239.08:16:28.46#ibcon#end of sib2, iclass 37, count 2 2006.239.08:16:28.46#ibcon#*mode == 0, iclass 37, count 2 2006.239.08:16:28.46#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.08:16:28.46#ibcon#[25=AT02-07\r\n] 2006.239.08:16:28.46#ibcon#*before write, iclass 37, count 2 2006.239.08:16:28.46#ibcon#enter sib2, iclass 37, count 2 2006.239.08:16:28.46#ibcon#flushed, iclass 37, count 2 2006.239.08:16:28.46#ibcon#about to write, iclass 37, count 2 2006.239.08:16:28.46#ibcon#wrote, iclass 37, count 2 2006.239.08:16:28.46#ibcon#about to read 3, iclass 37, count 2 2006.239.08:16:28.49#ibcon#read 3, iclass 37, count 2 2006.239.08:16:28.49#ibcon#about to read 4, iclass 37, count 2 2006.239.08:16:28.49#ibcon#read 4, iclass 37, count 2 2006.239.08:16:28.49#ibcon#about to read 5, iclass 37, count 2 2006.239.08:16:28.49#ibcon#read 5, iclass 37, count 2 2006.239.08:16:28.49#ibcon#about to read 6, iclass 37, count 2 2006.239.08:16:28.49#ibcon#read 6, iclass 37, count 2 2006.239.08:16:28.49#ibcon#end of sib2, iclass 37, count 2 2006.239.08:16:28.49#ibcon#*after write, iclass 37, count 2 2006.239.08:16:28.49#ibcon#*before return 0, iclass 37, count 2 2006.239.08:16:28.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:28.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:28.49#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.08:16:28.49#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:28.49#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:28.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:28.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:28.61#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:16:28.61#ibcon#first serial, iclass 37, count 0 2006.239.08:16:28.61#ibcon#enter sib2, iclass 37, count 0 2006.239.08:16:28.61#ibcon#flushed, iclass 37, count 0 2006.239.08:16:28.61#ibcon#about to write, iclass 37, count 0 2006.239.08:16:28.61#ibcon#wrote, iclass 37, count 0 2006.239.08:16:28.61#ibcon#about to read 3, iclass 37, count 0 2006.239.08:16:28.63#ibcon#read 3, iclass 37, count 0 2006.239.08:16:28.63#ibcon#about to read 4, iclass 37, count 0 2006.239.08:16:28.63#ibcon#read 4, iclass 37, count 0 2006.239.08:16:28.63#ibcon#about to read 5, iclass 37, count 0 2006.239.08:16:28.63#ibcon#read 5, iclass 37, count 0 2006.239.08:16:28.63#ibcon#about to read 6, iclass 37, count 0 2006.239.08:16:28.63#ibcon#read 6, iclass 37, count 0 2006.239.08:16:28.63#ibcon#end of sib2, iclass 37, count 0 2006.239.08:16:28.63#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:16:28.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:16:28.63#ibcon#[25=USB\r\n] 2006.239.08:16:28.63#ibcon#*before write, iclass 37, count 0 2006.239.08:16:28.63#ibcon#enter sib2, iclass 37, count 0 2006.239.08:16:28.63#ibcon#flushed, iclass 37, count 0 2006.239.08:16:28.63#ibcon#about to write, iclass 37, count 0 2006.239.08:16:28.63#ibcon#wrote, iclass 37, count 0 2006.239.08:16:28.63#ibcon#about to read 3, iclass 37, count 0 2006.239.08:16:28.66#ibcon#read 3, iclass 37, count 0 2006.239.08:16:28.66#ibcon#about to read 4, iclass 37, count 0 2006.239.08:16:28.66#ibcon#read 4, iclass 37, count 0 2006.239.08:16:28.66#ibcon#about to read 5, iclass 37, count 0 2006.239.08:16:28.66#ibcon#read 5, iclass 37, count 0 2006.239.08:16:28.66#ibcon#about to read 6, iclass 37, count 0 2006.239.08:16:28.66#ibcon#read 6, iclass 37, count 0 2006.239.08:16:28.66#ibcon#end of sib2, iclass 37, count 0 2006.239.08:16:28.66#ibcon#*after write, iclass 37, count 0 2006.239.08:16:28.66#ibcon#*before return 0, iclass 37, count 0 2006.239.08:16:28.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:28.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:28.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:16:28.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:16:28.66$vc4f8/valo=3,672.99 2006.239.08:16:28.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:16:28.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:16:28.66#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:28.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:28.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:28.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:28.66#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:16:28.66#ibcon#first serial, iclass 39, count 0 2006.239.08:16:28.66#ibcon#enter sib2, iclass 39, count 0 2006.239.08:16:28.67#ibcon#flushed, iclass 39, count 0 2006.239.08:16:28.67#ibcon#about to write, iclass 39, count 0 2006.239.08:16:28.67#ibcon#wrote, iclass 39, count 0 2006.239.08:16:28.67#ibcon#about to read 3, iclass 39, count 0 2006.239.08:16:28.68#ibcon#read 3, iclass 39, count 0 2006.239.08:16:28.68#ibcon#about to read 4, iclass 39, count 0 2006.239.08:16:28.68#ibcon#read 4, iclass 39, count 0 2006.239.08:16:28.68#ibcon#about to read 5, iclass 39, count 0 2006.239.08:16:28.68#ibcon#read 5, iclass 39, count 0 2006.239.08:16:28.68#ibcon#about to read 6, iclass 39, count 0 2006.239.08:16:28.68#ibcon#read 6, iclass 39, count 0 2006.239.08:16:28.68#ibcon#end of sib2, iclass 39, count 0 2006.239.08:16:28.68#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:16:28.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:16:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:16:28.68#ibcon#*before write, iclass 39, count 0 2006.239.08:16:28.68#ibcon#enter sib2, iclass 39, count 0 2006.239.08:16:28.68#ibcon#flushed, iclass 39, count 0 2006.239.08:16:28.68#ibcon#about to write, iclass 39, count 0 2006.239.08:16:28.68#ibcon#wrote, iclass 39, count 0 2006.239.08:16:28.68#ibcon#about to read 3, iclass 39, count 0 2006.239.08:16:28.72#ibcon#read 3, iclass 39, count 0 2006.239.08:16:28.72#ibcon#about to read 4, iclass 39, count 0 2006.239.08:16:28.72#ibcon#read 4, iclass 39, count 0 2006.239.08:16:28.72#ibcon#about to read 5, iclass 39, count 0 2006.239.08:16:28.72#ibcon#read 5, iclass 39, count 0 2006.239.08:16:28.72#ibcon#about to read 6, iclass 39, count 0 2006.239.08:16:28.72#ibcon#read 6, iclass 39, count 0 2006.239.08:16:28.72#ibcon#end of sib2, iclass 39, count 0 2006.239.08:16:28.72#ibcon#*after write, iclass 39, count 0 2006.239.08:16:28.72#ibcon#*before return 0, iclass 39, count 0 2006.239.08:16:28.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:28.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:28.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:16:28.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:16:28.72$vc4f8/va=3,7 2006.239.08:16:28.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.08:16:28.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.08:16:28.72#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:28.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:28.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:28.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:28.78#ibcon#enter wrdev, iclass 3, count 2 2006.239.08:16:28.78#ibcon#first serial, iclass 3, count 2 2006.239.08:16:28.78#ibcon#enter sib2, iclass 3, count 2 2006.239.08:16:28.78#ibcon#flushed, iclass 3, count 2 2006.239.08:16:28.78#ibcon#about to write, iclass 3, count 2 2006.239.08:16:28.78#ibcon#wrote, iclass 3, count 2 2006.239.08:16:28.78#ibcon#about to read 3, iclass 3, count 2 2006.239.08:16:28.80#ibcon#read 3, iclass 3, count 2 2006.239.08:16:28.80#ibcon#about to read 4, iclass 3, count 2 2006.239.08:16:28.80#ibcon#read 4, iclass 3, count 2 2006.239.08:16:28.80#ibcon#about to read 5, iclass 3, count 2 2006.239.08:16:28.80#ibcon#read 5, iclass 3, count 2 2006.239.08:16:28.80#ibcon#about to read 6, iclass 3, count 2 2006.239.08:16:28.80#ibcon#read 6, iclass 3, count 2 2006.239.08:16:28.80#ibcon#end of sib2, iclass 3, count 2 2006.239.08:16:28.80#ibcon#*mode == 0, iclass 3, count 2 2006.239.08:16:28.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.08:16:28.80#ibcon#[25=AT03-07\r\n] 2006.239.08:16:28.80#ibcon#*before write, iclass 3, count 2 2006.239.08:16:28.80#ibcon#enter sib2, iclass 3, count 2 2006.239.08:16:28.80#ibcon#flushed, iclass 3, count 2 2006.239.08:16:28.80#ibcon#about to write, iclass 3, count 2 2006.239.08:16:28.80#ibcon#wrote, iclass 3, count 2 2006.239.08:16:28.80#ibcon#about to read 3, iclass 3, count 2 2006.239.08:16:28.83#ibcon#read 3, iclass 3, count 2 2006.239.08:16:28.83#ibcon#about to read 4, iclass 3, count 2 2006.239.08:16:28.83#ibcon#read 4, iclass 3, count 2 2006.239.08:16:28.83#ibcon#about to read 5, iclass 3, count 2 2006.239.08:16:28.83#ibcon#read 5, iclass 3, count 2 2006.239.08:16:28.83#ibcon#about to read 6, iclass 3, count 2 2006.239.08:16:28.83#ibcon#read 6, iclass 3, count 2 2006.239.08:16:28.83#ibcon#end of sib2, iclass 3, count 2 2006.239.08:16:28.83#ibcon#*after write, iclass 3, count 2 2006.239.08:16:28.83#ibcon#*before return 0, iclass 3, count 2 2006.239.08:16:28.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:28.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:28.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.08:16:28.83#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:28.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:28.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:28.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:28.95#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:16:28.95#ibcon#first serial, iclass 3, count 0 2006.239.08:16:28.95#ibcon#enter sib2, iclass 3, count 0 2006.239.08:16:28.95#ibcon#flushed, iclass 3, count 0 2006.239.08:16:28.95#ibcon#about to write, iclass 3, count 0 2006.239.08:16:28.95#ibcon#wrote, iclass 3, count 0 2006.239.08:16:28.95#ibcon#about to read 3, iclass 3, count 0 2006.239.08:16:28.97#ibcon#read 3, iclass 3, count 0 2006.239.08:16:28.97#ibcon#about to read 4, iclass 3, count 0 2006.239.08:16:28.97#ibcon#read 4, iclass 3, count 0 2006.239.08:16:28.97#ibcon#about to read 5, iclass 3, count 0 2006.239.08:16:28.97#ibcon#read 5, iclass 3, count 0 2006.239.08:16:28.97#ibcon#about to read 6, iclass 3, count 0 2006.239.08:16:28.97#ibcon#read 6, iclass 3, count 0 2006.239.08:16:28.97#ibcon#end of sib2, iclass 3, count 0 2006.239.08:16:28.97#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:16:28.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:16:28.97#ibcon#[25=USB\r\n] 2006.239.08:16:28.97#ibcon#*before write, iclass 3, count 0 2006.239.08:16:28.97#ibcon#enter sib2, iclass 3, count 0 2006.239.08:16:28.97#ibcon#flushed, iclass 3, count 0 2006.239.08:16:28.97#ibcon#about to write, iclass 3, count 0 2006.239.08:16:28.97#ibcon#wrote, iclass 3, count 0 2006.239.08:16:28.97#ibcon#about to read 3, iclass 3, count 0 2006.239.08:16:29.00#ibcon#read 3, iclass 3, count 0 2006.239.08:16:29.00#ibcon#about to read 4, iclass 3, count 0 2006.239.08:16:29.00#ibcon#read 4, iclass 3, count 0 2006.239.08:16:29.00#ibcon#about to read 5, iclass 3, count 0 2006.239.08:16:29.00#ibcon#read 5, iclass 3, count 0 2006.239.08:16:29.00#ibcon#about to read 6, iclass 3, count 0 2006.239.08:16:29.00#ibcon#read 6, iclass 3, count 0 2006.239.08:16:29.00#ibcon#end of sib2, iclass 3, count 0 2006.239.08:16:29.00#ibcon#*after write, iclass 3, count 0 2006.239.08:16:29.00#ibcon#*before return 0, iclass 3, count 0 2006.239.08:16:29.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:29.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:29.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:16:29.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:16:29.00$vc4f8/valo=4,832.99 2006.239.08:16:29.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:16:29.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:16:29.00#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:29.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:29.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:29.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:29.00#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:16:29.00#ibcon#first serial, iclass 5, count 0 2006.239.08:16:29.00#ibcon#enter sib2, iclass 5, count 0 2006.239.08:16:29.00#ibcon#flushed, iclass 5, count 0 2006.239.08:16:29.00#ibcon#about to write, iclass 5, count 0 2006.239.08:16:29.00#ibcon#wrote, iclass 5, count 0 2006.239.08:16:29.00#ibcon#about to read 3, iclass 5, count 0 2006.239.08:16:29.02#ibcon#read 3, iclass 5, count 0 2006.239.08:16:29.02#ibcon#about to read 4, iclass 5, count 0 2006.239.08:16:29.02#ibcon#read 4, iclass 5, count 0 2006.239.08:16:29.02#ibcon#about to read 5, iclass 5, count 0 2006.239.08:16:29.02#ibcon#read 5, iclass 5, count 0 2006.239.08:16:29.02#ibcon#about to read 6, iclass 5, count 0 2006.239.08:16:29.02#ibcon#read 6, iclass 5, count 0 2006.239.08:16:29.02#ibcon#end of sib2, iclass 5, count 0 2006.239.08:16:29.02#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:16:29.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:16:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:16:29.02#ibcon#*before write, iclass 5, count 0 2006.239.08:16:29.02#ibcon#enter sib2, iclass 5, count 0 2006.239.08:16:29.02#ibcon#flushed, iclass 5, count 0 2006.239.08:16:29.02#ibcon#about to write, iclass 5, count 0 2006.239.08:16:29.02#ibcon#wrote, iclass 5, count 0 2006.239.08:16:29.02#ibcon#about to read 3, iclass 5, count 0 2006.239.08:16:29.06#ibcon#read 3, iclass 5, count 0 2006.239.08:16:29.06#ibcon#about to read 4, iclass 5, count 0 2006.239.08:16:29.06#ibcon#read 4, iclass 5, count 0 2006.239.08:16:29.06#ibcon#about to read 5, iclass 5, count 0 2006.239.08:16:29.06#ibcon#read 5, iclass 5, count 0 2006.239.08:16:29.06#ibcon#about to read 6, iclass 5, count 0 2006.239.08:16:29.06#ibcon#read 6, iclass 5, count 0 2006.239.08:16:29.06#ibcon#end of sib2, iclass 5, count 0 2006.239.08:16:29.06#ibcon#*after write, iclass 5, count 0 2006.239.08:16:29.06#ibcon#*before return 0, iclass 5, count 0 2006.239.08:16:29.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:29.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:29.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:16:29.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:16:29.06$vc4f8/va=4,7 2006.239.08:16:29.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.08:16:29.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.08:16:29.06#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:29.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:29.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:29.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:29.12#ibcon#enter wrdev, iclass 7, count 2 2006.239.08:16:29.12#ibcon#first serial, iclass 7, count 2 2006.239.08:16:29.12#ibcon#enter sib2, iclass 7, count 2 2006.239.08:16:29.12#ibcon#flushed, iclass 7, count 2 2006.239.08:16:29.12#ibcon#about to write, iclass 7, count 2 2006.239.08:16:29.12#ibcon#wrote, iclass 7, count 2 2006.239.08:16:29.12#ibcon#about to read 3, iclass 7, count 2 2006.239.08:16:29.14#ibcon#read 3, iclass 7, count 2 2006.239.08:16:29.14#ibcon#about to read 4, iclass 7, count 2 2006.239.08:16:29.14#ibcon#read 4, iclass 7, count 2 2006.239.08:16:29.14#ibcon#about to read 5, iclass 7, count 2 2006.239.08:16:29.14#ibcon#read 5, iclass 7, count 2 2006.239.08:16:29.14#ibcon#about to read 6, iclass 7, count 2 2006.239.08:16:29.14#ibcon#read 6, iclass 7, count 2 2006.239.08:16:29.14#ibcon#end of sib2, iclass 7, count 2 2006.239.08:16:29.14#ibcon#*mode == 0, iclass 7, count 2 2006.239.08:16:29.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.08:16:29.14#ibcon#[25=AT04-07\r\n] 2006.239.08:16:29.14#ibcon#*before write, iclass 7, count 2 2006.239.08:16:29.14#ibcon#enter sib2, iclass 7, count 2 2006.239.08:16:29.14#ibcon#flushed, iclass 7, count 2 2006.239.08:16:29.14#ibcon#about to write, iclass 7, count 2 2006.239.08:16:29.14#ibcon#wrote, iclass 7, count 2 2006.239.08:16:29.14#ibcon#about to read 3, iclass 7, count 2 2006.239.08:16:29.17#ibcon#read 3, iclass 7, count 2 2006.239.08:16:29.17#ibcon#about to read 4, iclass 7, count 2 2006.239.08:16:29.17#ibcon#read 4, iclass 7, count 2 2006.239.08:16:29.17#ibcon#about to read 5, iclass 7, count 2 2006.239.08:16:29.17#ibcon#read 5, iclass 7, count 2 2006.239.08:16:29.17#ibcon#about to read 6, iclass 7, count 2 2006.239.08:16:29.17#ibcon#read 6, iclass 7, count 2 2006.239.08:16:29.17#ibcon#end of sib2, iclass 7, count 2 2006.239.08:16:29.17#ibcon#*after write, iclass 7, count 2 2006.239.08:16:29.17#ibcon#*before return 0, iclass 7, count 2 2006.239.08:16:29.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:29.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:29.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.08:16:29.17#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:29.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:29.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:29.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:29.29#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:16:29.29#ibcon#first serial, iclass 7, count 0 2006.239.08:16:29.29#ibcon#enter sib2, iclass 7, count 0 2006.239.08:16:29.29#ibcon#flushed, iclass 7, count 0 2006.239.08:16:29.29#ibcon#about to write, iclass 7, count 0 2006.239.08:16:29.29#ibcon#wrote, iclass 7, count 0 2006.239.08:16:29.29#ibcon#about to read 3, iclass 7, count 0 2006.239.08:16:29.31#ibcon#read 3, iclass 7, count 0 2006.239.08:16:29.31#ibcon#about to read 4, iclass 7, count 0 2006.239.08:16:29.31#ibcon#read 4, iclass 7, count 0 2006.239.08:16:29.31#ibcon#about to read 5, iclass 7, count 0 2006.239.08:16:29.31#ibcon#read 5, iclass 7, count 0 2006.239.08:16:29.31#ibcon#about to read 6, iclass 7, count 0 2006.239.08:16:29.31#ibcon#read 6, iclass 7, count 0 2006.239.08:16:29.31#ibcon#end of sib2, iclass 7, count 0 2006.239.08:16:29.31#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:16:29.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:16:29.31#ibcon#[25=USB\r\n] 2006.239.08:16:29.31#ibcon#*before write, iclass 7, count 0 2006.239.08:16:29.31#ibcon#enter sib2, iclass 7, count 0 2006.239.08:16:29.31#ibcon#flushed, iclass 7, count 0 2006.239.08:16:29.31#ibcon#about to write, iclass 7, count 0 2006.239.08:16:29.31#ibcon#wrote, iclass 7, count 0 2006.239.08:16:29.31#ibcon#about to read 3, iclass 7, count 0 2006.239.08:16:29.34#ibcon#read 3, iclass 7, count 0 2006.239.08:16:29.34#ibcon#about to read 4, iclass 7, count 0 2006.239.08:16:29.34#ibcon#read 4, iclass 7, count 0 2006.239.08:16:29.34#ibcon#about to read 5, iclass 7, count 0 2006.239.08:16:29.34#ibcon#read 5, iclass 7, count 0 2006.239.08:16:29.34#ibcon#about to read 6, iclass 7, count 0 2006.239.08:16:29.34#ibcon#read 6, iclass 7, count 0 2006.239.08:16:29.34#ibcon#end of sib2, iclass 7, count 0 2006.239.08:16:29.34#ibcon#*after write, iclass 7, count 0 2006.239.08:16:29.34#ibcon#*before return 0, iclass 7, count 0 2006.239.08:16:29.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:29.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:29.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:16:29.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:16:29.34$vc4f8/valo=5,652.99 2006.239.08:16:29.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.08:16:29.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.08:16:29.34#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:29.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:29.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:29.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:29.34#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:16:29.34#ibcon#first serial, iclass 11, count 0 2006.239.08:16:29.34#ibcon#enter sib2, iclass 11, count 0 2006.239.08:16:29.34#ibcon#flushed, iclass 11, count 0 2006.239.08:16:29.34#ibcon#about to write, iclass 11, count 0 2006.239.08:16:29.34#ibcon#wrote, iclass 11, count 0 2006.239.08:16:29.34#ibcon#about to read 3, iclass 11, count 0 2006.239.08:16:29.36#ibcon#read 3, iclass 11, count 0 2006.239.08:16:29.36#ibcon#about to read 4, iclass 11, count 0 2006.239.08:16:29.36#ibcon#read 4, iclass 11, count 0 2006.239.08:16:29.36#ibcon#about to read 5, iclass 11, count 0 2006.239.08:16:29.36#ibcon#read 5, iclass 11, count 0 2006.239.08:16:29.36#ibcon#about to read 6, iclass 11, count 0 2006.239.08:16:29.36#ibcon#read 6, iclass 11, count 0 2006.239.08:16:29.36#ibcon#end of sib2, iclass 11, count 0 2006.239.08:16:29.36#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:16:29.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:16:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:16:29.36#ibcon#*before write, iclass 11, count 0 2006.239.08:16:29.36#ibcon#enter sib2, iclass 11, count 0 2006.239.08:16:29.36#ibcon#flushed, iclass 11, count 0 2006.239.08:16:29.36#ibcon#about to write, iclass 11, count 0 2006.239.08:16:29.36#ibcon#wrote, iclass 11, count 0 2006.239.08:16:29.36#ibcon#about to read 3, iclass 11, count 0 2006.239.08:16:29.40#ibcon#read 3, iclass 11, count 0 2006.239.08:16:29.40#ibcon#about to read 4, iclass 11, count 0 2006.239.08:16:29.40#ibcon#read 4, iclass 11, count 0 2006.239.08:16:29.40#ibcon#about to read 5, iclass 11, count 0 2006.239.08:16:29.40#ibcon#read 5, iclass 11, count 0 2006.239.08:16:29.40#ibcon#about to read 6, iclass 11, count 0 2006.239.08:16:29.40#ibcon#read 6, iclass 11, count 0 2006.239.08:16:29.40#ibcon#end of sib2, iclass 11, count 0 2006.239.08:16:29.40#ibcon#*after write, iclass 11, count 0 2006.239.08:16:29.40#ibcon#*before return 0, iclass 11, count 0 2006.239.08:16:29.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:29.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:29.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:16:29.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:16:29.40$vc4f8/va=5,8 2006.239.08:16:29.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.08:16:29.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.08:16:29.40#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:29.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:29.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:29.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:29.46#ibcon#enter wrdev, iclass 13, count 2 2006.239.08:16:29.46#ibcon#first serial, iclass 13, count 2 2006.239.08:16:29.46#ibcon#enter sib2, iclass 13, count 2 2006.239.08:16:29.46#ibcon#flushed, iclass 13, count 2 2006.239.08:16:29.46#ibcon#about to write, iclass 13, count 2 2006.239.08:16:29.46#ibcon#wrote, iclass 13, count 2 2006.239.08:16:29.46#ibcon#about to read 3, iclass 13, count 2 2006.239.08:16:29.48#ibcon#read 3, iclass 13, count 2 2006.239.08:16:29.48#ibcon#about to read 4, iclass 13, count 2 2006.239.08:16:29.48#ibcon#read 4, iclass 13, count 2 2006.239.08:16:29.48#ibcon#about to read 5, iclass 13, count 2 2006.239.08:16:29.48#ibcon#read 5, iclass 13, count 2 2006.239.08:16:29.48#ibcon#about to read 6, iclass 13, count 2 2006.239.08:16:29.48#ibcon#read 6, iclass 13, count 2 2006.239.08:16:29.48#ibcon#end of sib2, iclass 13, count 2 2006.239.08:16:29.48#ibcon#*mode == 0, iclass 13, count 2 2006.239.08:16:29.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.08:16:29.48#ibcon#[25=AT05-08\r\n] 2006.239.08:16:29.48#ibcon#*before write, iclass 13, count 2 2006.239.08:16:29.48#ibcon#enter sib2, iclass 13, count 2 2006.239.08:16:29.48#ibcon#flushed, iclass 13, count 2 2006.239.08:16:29.48#ibcon#about to write, iclass 13, count 2 2006.239.08:16:29.48#ibcon#wrote, iclass 13, count 2 2006.239.08:16:29.48#ibcon#about to read 3, iclass 13, count 2 2006.239.08:16:29.51#ibcon#read 3, iclass 13, count 2 2006.239.08:16:29.51#ibcon#about to read 4, iclass 13, count 2 2006.239.08:16:29.51#ibcon#read 4, iclass 13, count 2 2006.239.08:16:29.51#ibcon#about to read 5, iclass 13, count 2 2006.239.08:16:29.51#ibcon#read 5, iclass 13, count 2 2006.239.08:16:29.51#ibcon#about to read 6, iclass 13, count 2 2006.239.08:16:29.51#ibcon#read 6, iclass 13, count 2 2006.239.08:16:29.51#ibcon#end of sib2, iclass 13, count 2 2006.239.08:16:29.51#ibcon#*after write, iclass 13, count 2 2006.239.08:16:29.51#ibcon#*before return 0, iclass 13, count 2 2006.239.08:16:29.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:29.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:29.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.08:16:29.51#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:29.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:29.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:29.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:29.63#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:16:29.63#ibcon#first serial, iclass 13, count 0 2006.239.08:16:29.63#ibcon#enter sib2, iclass 13, count 0 2006.239.08:16:29.63#ibcon#flushed, iclass 13, count 0 2006.239.08:16:29.63#ibcon#about to write, iclass 13, count 0 2006.239.08:16:29.63#ibcon#wrote, iclass 13, count 0 2006.239.08:16:29.63#ibcon#about to read 3, iclass 13, count 0 2006.239.08:16:29.65#ibcon#read 3, iclass 13, count 0 2006.239.08:16:29.65#ibcon#about to read 4, iclass 13, count 0 2006.239.08:16:29.65#ibcon#read 4, iclass 13, count 0 2006.239.08:16:29.65#ibcon#about to read 5, iclass 13, count 0 2006.239.08:16:29.65#ibcon#read 5, iclass 13, count 0 2006.239.08:16:29.65#ibcon#about to read 6, iclass 13, count 0 2006.239.08:16:29.65#ibcon#read 6, iclass 13, count 0 2006.239.08:16:29.65#ibcon#end of sib2, iclass 13, count 0 2006.239.08:16:29.65#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:16:29.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:16:29.65#ibcon#[25=USB\r\n] 2006.239.08:16:29.65#ibcon#*before write, iclass 13, count 0 2006.239.08:16:29.65#ibcon#enter sib2, iclass 13, count 0 2006.239.08:16:29.65#ibcon#flushed, iclass 13, count 0 2006.239.08:16:29.65#ibcon#about to write, iclass 13, count 0 2006.239.08:16:29.65#ibcon#wrote, iclass 13, count 0 2006.239.08:16:29.65#ibcon#about to read 3, iclass 13, count 0 2006.239.08:16:29.68#ibcon#read 3, iclass 13, count 0 2006.239.08:16:29.68#ibcon#about to read 4, iclass 13, count 0 2006.239.08:16:29.68#ibcon#read 4, iclass 13, count 0 2006.239.08:16:29.68#ibcon#about to read 5, iclass 13, count 0 2006.239.08:16:29.68#ibcon#read 5, iclass 13, count 0 2006.239.08:16:29.68#ibcon#about to read 6, iclass 13, count 0 2006.239.08:16:29.68#ibcon#read 6, iclass 13, count 0 2006.239.08:16:29.68#ibcon#end of sib2, iclass 13, count 0 2006.239.08:16:29.68#ibcon#*after write, iclass 13, count 0 2006.239.08:16:29.68#ibcon#*before return 0, iclass 13, count 0 2006.239.08:16:29.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:29.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:29.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:16:29.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:16:29.68$vc4f8/valo=6,772.99 2006.239.08:16:29.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.08:16:29.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.08:16:29.68#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:29.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:29.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:29.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:29.68#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:16:29.68#ibcon#first serial, iclass 15, count 0 2006.239.08:16:29.68#ibcon#enter sib2, iclass 15, count 0 2006.239.08:16:29.68#ibcon#flushed, iclass 15, count 0 2006.239.08:16:29.68#ibcon#about to write, iclass 15, count 0 2006.239.08:16:29.68#ibcon#wrote, iclass 15, count 0 2006.239.08:16:29.68#ibcon#about to read 3, iclass 15, count 0 2006.239.08:16:29.70#ibcon#read 3, iclass 15, count 0 2006.239.08:16:29.70#ibcon#about to read 4, iclass 15, count 0 2006.239.08:16:29.70#ibcon#read 4, iclass 15, count 0 2006.239.08:16:29.70#ibcon#about to read 5, iclass 15, count 0 2006.239.08:16:29.70#ibcon#read 5, iclass 15, count 0 2006.239.08:16:29.70#ibcon#about to read 6, iclass 15, count 0 2006.239.08:16:29.70#ibcon#read 6, iclass 15, count 0 2006.239.08:16:29.70#ibcon#end of sib2, iclass 15, count 0 2006.239.08:16:29.70#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:16:29.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:16:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:16:29.70#ibcon#*before write, iclass 15, count 0 2006.239.08:16:29.70#ibcon#enter sib2, iclass 15, count 0 2006.239.08:16:29.70#ibcon#flushed, iclass 15, count 0 2006.239.08:16:29.70#ibcon#about to write, iclass 15, count 0 2006.239.08:16:29.70#ibcon#wrote, iclass 15, count 0 2006.239.08:16:29.70#ibcon#about to read 3, iclass 15, count 0 2006.239.08:16:29.74#ibcon#read 3, iclass 15, count 0 2006.239.08:16:29.74#ibcon#about to read 4, iclass 15, count 0 2006.239.08:16:29.74#ibcon#read 4, iclass 15, count 0 2006.239.08:16:29.74#ibcon#about to read 5, iclass 15, count 0 2006.239.08:16:29.74#ibcon#read 5, iclass 15, count 0 2006.239.08:16:29.74#ibcon#about to read 6, iclass 15, count 0 2006.239.08:16:29.74#ibcon#read 6, iclass 15, count 0 2006.239.08:16:29.74#ibcon#end of sib2, iclass 15, count 0 2006.239.08:16:29.74#ibcon#*after write, iclass 15, count 0 2006.239.08:16:29.74#ibcon#*before return 0, iclass 15, count 0 2006.239.08:16:29.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:29.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:29.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:16:29.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:16:29.74$vc4f8/va=6,7 2006.239.08:16:29.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.08:16:29.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.08:16:29.74#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:29.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:29.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:29.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:29.80#ibcon#enter wrdev, iclass 17, count 2 2006.239.08:16:29.80#ibcon#first serial, iclass 17, count 2 2006.239.08:16:29.80#ibcon#enter sib2, iclass 17, count 2 2006.239.08:16:29.80#ibcon#flushed, iclass 17, count 2 2006.239.08:16:29.80#ibcon#about to write, iclass 17, count 2 2006.239.08:16:29.80#ibcon#wrote, iclass 17, count 2 2006.239.08:16:29.80#ibcon#about to read 3, iclass 17, count 2 2006.239.08:16:29.82#ibcon#read 3, iclass 17, count 2 2006.239.08:16:29.82#ibcon#about to read 4, iclass 17, count 2 2006.239.08:16:29.82#ibcon#read 4, iclass 17, count 2 2006.239.08:16:29.82#ibcon#about to read 5, iclass 17, count 2 2006.239.08:16:29.82#ibcon#read 5, iclass 17, count 2 2006.239.08:16:29.82#ibcon#about to read 6, iclass 17, count 2 2006.239.08:16:29.82#ibcon#read 6, iclass 17, count 2 2006.239.08:16:29.82#ibcon#end of sib2, iclass 17, count 2 2006.239.08:16:29.82#ibcon#*mode == 0, iclass 17, count 2 2006.239.08:16:29.82#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.08:16:29.82#ibcon#[25=AT06-07\r\n] 2006.239.08:16:29.82#ibcon#*before write, iclass 17, count 2 2006.239.08:16:29.82#ibcon#enter sib2, iclass 17, count 2 2006.239.08:16:29.82#ibcon#flushed, iclass 17, count 2 2006.239.08:16:29.82#ibcon#about to write, iclass 17, count 2 2006.239.08:16:29.82#ibcon#wrote, iclass 17, count 2 2006.239.08:16:29.82#ibcon#about to read 3, iclass 17, count 2 2006.239.08:16:29.85#ibcon#read 3, iclass 17, count 2 2006.239.08:16:29.85#ibcon#about to read 4, iclass 17, count 2 2006.239.08:16:29.85#ibcon#read 4, iclass 17, count 2 2006.239.08:16:29.85#ibcon#about to read 5, iclass 17, count 2 2006.239.08:16:29.85#ibcon#read 5, iclass 17, count 2 2006.239.08:16:29.85#ibcon#about to read 6, iclass 17, count 2 2006.239.08:16:29.85#ibcon#read 6, iclass 17, count 2 2006.239.08:16:29.85#ibcon#end of sib2, iclass 17, count 2 2006.239.08:16:29.85#ibcon#*after write, iclass 17, count 2 2006.239.08:16:29.85#ibcon#*before return 0, iclass 17, count 2 2006.239.08:16:29.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:29.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:29.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.08:16:29.85#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:29.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:29.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:29.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:29.97#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:16:29.97#ibcon#first serial, iclass 17, count 0 2006.239.08:16:29.97#ibcon#enter sib2, iclass 17, count 0 2006.239.08:16:29.97#ibcon#flushed, iclass 17, count 0 2006.239.08:16:29.97#ibcon#about to write, iclass 17, count 0 2006.239.08:16:29.97#ibcon#wrote, iclass 17, count 0 2006.239.08:16:29.97#ibcon#about to read 3, iclass 17, count 0 2006.239.08:16:29.99#ibcon#read 3, iclass 17, count 0 2006.239.08:16:29.99#ibcon#about to read 4, iclass 17, count 0 2006.239.08:16:29.99#ibcon#read 4, iclass 17, count 0 2006.239.08:16:29.99#ibcon#about to read 5, iclass 17, count 0 2006.239.08:16:29.99#ibcon#read 5, iclass 17, count 0 2006.239.08:16:29.99#ibcon#about to read 6, iclass 17, count 0 2006.239.08:16:29.99#ibcon#read 6, iclass 17, count 0 2006.239.08:16:29.99#ibcon#end of sib2, iclass 17, count 0 2006.239.08:16:29.99#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:16:29.99#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:16:29.99#ibcon#[25=USB\r\n] 2006.239.08:16:29.99#ibcon#*before write, iclass 17, count 0 2006.239.08:16:29.99#ibcon#enter sib2, iclass 17, count 0 2006.239.08:16:29.99#ibcon#flushed, iclass 17, count 0 2006.239.08:16:29.99#ibcon#about to write, iclass 17, count 0 2006.239.08:16:29.99#ibcon#wrote, iclass 17, count 0 2006.239.08:16:29.99#ibcon#about to read 3, iclass 17, count 0 2006.239.08:16:30.02#ibcon#read 3, iclass 17, count 0 2006.239.08:16:30.02#ibcon#about to read 4, iclass 17, count 0 2006.239.08:16:30.02#ibcon#read 4, iclass 17, count 0 2006.239.08:16:30.02#ibcon#about to read 5, iclass 17, count 0 2006.239.08:16:30.02#ibcon#read 5, iclass 17, count 0 2006.239.08:16:30.02#ibcon#about to read 6, iclass 17, count 0 2006.239.08:16:30.02#ibcon#read 6, iclass 17, count 0 2006.239.08:16:30.02#ibcon#end of sib2, iclass 17, count 0 2006.239.08:16:30.02#ibcon#*after write, iclass 17, count 0 2006.239.08:16:30.02#ibcon#*before return 0, iclass 17, count 0 2006.239.08:16:30.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:30.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:30.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:16:30.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:16:30.02$vc4f8/valo=7,832.99 2006.239.08:16:30.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.08:16:30.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.08:16:30.02#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:30.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:30.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:30.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:30.02#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:16:30.02#ibcon#first serial, iclass 19, count 0 2006.239.08:16:30.02#ibcon#enter sib2, iclass 19, count 0 2006.239.08:16:30.02#ibcon#flushed, iclass 19, count 0 2006.239.08:16:30.02#ibcon#about to write, iclass 19, count 0 2006.239.08:16:30.02#ibcon#wrote, iclass 19, count 0 2006.239.08:16:30.02#ibcon#about to read 3, iclass 19, count 0 2006.239.08:16:30.04#ibcon#read 3, iclass 19, count 0 2006.239.08:16:30.04#ibcon#about to read 4, iclass 19, count 0 2006.239.08:16:30.04#ibcon#read 4, iclass 19, count 0 2006.239.08:16:30.04#ibcon#about to read 5, iclass 19, count 0 2006.239.08:16:30.04#ibcon#read 5, iclass 19, count 0 2006.239.08:16:30.04#ibcon#about to read 6, iclass 19, count 0 2006.239.08:16:30.04#ibcon#read 6, iclass 19, count 0 2006.239.08:16:30.04#ibcon#end of sib2, iclass 19, count 0 2006.239.08:16:30.04#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:16:30.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:16:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:16:30.04#ibcon#*before write, iclass 19, count 0 2006.239.08:16:30.04#ibcon#enter sib2, iclass 19, count 0 2006.239.08:16:30.04#ibcon#flushed, iclass 19, count 0 2006.239.08:16:30.04#ibcon#about to write, iclass 19, count 0 2006.239.08:16:30.04#ibcon#wrote, iclass 19, count 0 2006.239.08:16:30.04#ibcon#about to read 3, iclass 19, count 0 2006.239.08:16:30.08#ibcon#read 3, iclass 19, count 0 2006.239.08:16:30.08#ibcon#about to read 4, iclass 19, count 0 2006.239.08:16:30.08#ibcon#read 4, iclass 19, count 0 2006.239.08:16:30.08#ibcon#about to read 5, iclass 19, count 0 2006.239.08:16:30.08#ibcon#read 5, iclass 19, count 0 2006.239.08:16:30.08#ibcon#about to read 6, iclass 19, count 0 2006.239.08:16:30.08#ibcon#read 6, iclass 19, count 0 2006.239.08:16:30.08#ibcon#end of sib2, iclass 19, count 0 2006.239.08:16:30.08#ibcon#*after write, iclass 19, count 0 2006.239.08:16:30.08#ibcon#*before return 0, iclass 19, count 0 2006.239.08:16:30.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:30.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:30.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:16:30.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:16:30.08$vc4f8/va=7,7 2006.239.08:16:30.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.239.08:16:30.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.239.08:16:30.08#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:30.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:16:30.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:16:30.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:16:30.14#ibcon#enter wrdev, iclass 21, count 2 2006.239.08:16:30.14#ibcon#first serial, iclass 21, count 2 2006.239.08:16:30.14#ibcon#enter sib2, iclass 21, count 2 2006.239.08:16:30.14#ibcon#flushed, iclass 21, count 2 2006.239.08:16:30.14#ibcon#about to write, iclass 21, count 2 2006.239.08:16:30.14#ibcon#wrote, iclass 21, count 2 2006.239.08:16:30.14#ibcon#about to read 3, iclass 21, count 2 2006.239.08:16:30.16#ibcon#read 3, iclass 21, count 2 2006.239.08:16:30.16#ibcon#about to read 4, iclass 21, count 2 2006.239.08:16:30.16#ibcon#read 4, iclass 21, count 2 2006.239.08:16:30.16#ibcon#about to read 5, iclass 21, count 2 2006.239.08:16:30.16#ibcon#read 5, iclass 21, count 2 2006.239.08:16:30.16#ibcon#about to read 6, iclass 21, count 2 2006.239.08:16:30.16#ibcon#read 6, iclass 21, count 2 2006.239.08:16:30.16#ibcon#end of sib2, iclass 21, count 2 2006.239.08:16:30.16#ibcon#*mode == 0, iclass 21, count 2 2006.239.08:16:30.16#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.239.08:16:30.16#ibcon#[25=AT07-07\r\n] 2006.239.08:16:30.16#ibcon#*before write, iclass 21, count 2 2006.239.08:16:30.16#ibcon#enter sib2, iclass 21, count 2 2006.239.08:16:30.16#ibcon#flushed, iclass 21, count 2 2006.239.08:16:30.16#ibcon#about to write, iclass 21, count 2 2006.239.08:16:30.16#ibcon#wrote, iclass 21, count 2 2006.239.08:16:30.16#ibcon#about to read 3, iclass 21, count 2 2006.239.08:16:30.19#ibcon#read 3, iclass 21, count 2 2006.239.08:16:30.19#ibcon#about to read 4, iclass 21, count 2 2006.239.08:16:30.19#ibcon#read 4, iclass 21, count 2 2006.239.08:16:30.19#ibcon#about to read 5, iclass 21, count 2 2006.239.08:16:30.19#ibcon#read 5, iclass 21, count 2 2006.239.08:16:30.19#ibcon#about to read 6, iclass 21, count 2 2006.239.08:16:30.19#ibcon#read 6, iclass 21, count 2 2006.239.08:16:30.19#ibcon#end of sib2, iclass 21, count 2 2006.239.08:16:30.19#ibcon#*after write, iclass 21, count 2 2006.239.08:16:30.19#ibcon#*before return 0, iclass 21, count 2 2006.239.08:16:30.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:16:30.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.239.08:16:30.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.239.08:16:30.19#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:30.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:16:30.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:16:30.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:16:30.31#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:16:30.31#ibcon#first serial, iclass 21, count 0 2006.239.08:16:30.31#ibcon#enter sib2, iclass 21, count 0 2006.239.08:16:30.31#ibcon#flushed, iclass 21, count 0 2006.239.08:16:30.31#ibcon#about to write, iclass 21, count 0 2006.239.08:16:30.31#ibcon#wrote, iclass 21, count 0 2006.239.08:16:30.31#ibcon#about to read 3, iclass 21, count 0 2006.239.08:16:30.33#ibcon#read 3, iclass 21, count 0 2006.239.08:16:30.33#ibcon#about to read 4, iclass 21, count 0 2006.239.08:16:30.33#ibcon#read 4, iclass 21, count 0 2006.239.08:16:30.33#ibcon#about to read 5, iclass 21, count 0 2006.239.08:16:30.33#ibcon#read 5, iclass 21, count 0 2006.239.08:16:30.33#ibcon#about to read 6, iclass 21, count 0 2006.239.08:16:30.33#ibcon#read 6, iclass 21, count 0 2006.239.08:16:30.33#ibcon#end of sib2, iclass 21, count 0 2006.239.08:16:30.33#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:16:30.33#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:16:30.33#ibcon#[25=USB\r\n] 2006.239.08:16:30.33#ibcon#*before write, iclass 21, count 0 2006.239.08:16:30.33#ibcon#enter sib2, iclass 21, count 0 2006.239.08:16:30.33#ibcon#flushed, iclass 21, count 0 2006.239.08:16:30.33#ibcon#about to write, iclass 21, count 0 2006.239.08:16:30.33#ibcon#wrote, iclass 21, count 0 2006.239.08:16:30.33#ibcon#about to read 3, iclass 21, count 0 2006.239.08:16:30.36#ibcon#read 3, iclass 21, count 0 2006.239.08:16:30.36#ibcon#about to read 4, iclass 21, count 0 2006.239.08:16:30.36#ibcon#read 4, iclass 21, count 0 2006.239.08:16:30.36#ibcon#about to read 5, iclass 21, count 0 2006.239.08:16:30.36#ibcon#read 5, iclass 21, count 0 2006.239.08:16:30.36#ibcon#about to read 6, iclass 21, count 0 2006.239.08:16:30.36#ibcon#read 6, iclass 21, count 0 2006.239.08:16:30.36#ibcon#end of sib2, iclass 21, count 0 2006.239.08:16:30.36#ibcon#*after write, iclass 21, count 0 2006.239.08:16:30.36#ibcon#*before return 0, iclass 21, count 0 2006.239.08:16:30.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:16:30.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.239.08:16:30.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:16:30.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:16:30.36$vc4f8/valo=8,852.99 2006.239.08:16:30.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.239.08:16:30.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.239.08:16:30.36#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:30.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:16:30.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:16:30.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:16:30.36#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:16:30.36#ibcon#first serial, iclass 23, count 0 2006.239.08:16:30.36#ibcon#enter sib2, iclass 23, count 0 2006.239.08:16:30.36#ibcon#flushed, iclass 23, count 0 2006.239.08:16:30.36#ibcon#about to write, iclass 23, count 0 2006.239.08:16:30.36#ibcon#wrote, iclass 23, count 0 2006.239.08:16:30.36#ibcon#about to read 3, iclass 23, count 0 2006.239.08:16:30.38#ibcon#read 3, iclass 23, count 0 2006.239.08:16:30.38#ibcon#about to read 4, iclass 23, count 0 2006.239.08:16:30.38#ibcon#read 4, iclass 23, count 0 2006.239.08:16:30.38#ibcon#about to read 5, iclass 23, count 0 2006.239.08:16:30.38#ibcon#read 5, iclass 23, count 0 2006.239.08:16:30.38#ibcon#about to read 6, iclass 23, count 0 2006.239.08:16:30.38#ibcon#read 6, iclass 23, count 0 2006.239.08:16:30.38#ibcon#end of sib2, iclass 23, count 0 2006.239.08:16:30.38#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:16:30.38#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:16:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:16:30.38#ibcon#*before write, iclass 23, count 0 2006.239.08:16:30.38#ibcon#enter sib2, iclass 23, count 0 2006.239.08:16:30.38#ibcon#flushed, iclass 23, count 0 2006.239.08:16:30.38#ibcon#about to write, iclass 23, count 0 2006.239.08:16:30.38#ibcon#wrote, iclass 23, count 0 2006.239.08:16:30.38#ibcon#about to read 3, iclass 23, count 0 2006.239.08:16:30.42#ibcon#read 3, iclass 23, count 0 2006.239.08:16:30.42#ibcon#about to read 4, iclass 23, count 0 2006.239.08:16:30.42#ibcon#read 4, iclass 23, count 0 2006.239.08:16:30.42#ibcon#about to read 5, iclass 23, count 0 2006.239.08:16:30.42#ibcon#read 5, iclass 23, count 0 2006.239.08:16:30.42#ibcon#about to read 6, iclass 23, count 0 2006.239.08:16:30.42#ibcon#read 6, iclass 23, count 0 2006.239.08:16:30.42#ibcon#end of sib2, iclass 23, count 0 2006.239.08:16:30.42#ibcon#*after write, iclass 23, count 0 2006.239.08:16:30.42#ibcon#*before return 0, iclass 23, count 0 2006.239.08:16:30.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:16:30.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.239.08:16:30.42#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:16:30.42#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:16:30.42$vc4f8/va=8,7 2006.239.08:16:30.42#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.239.08:16:30.42#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.239.08:16:30.42#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:30.42#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:16:30.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:16:30.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:16:30.48#ibcon#enter wrdev, iclass 25, count 2 2006.239.08:16:30.48#ibcon#first serial, iclass 25, count 2 2006.239.08:16:30.48#ibcon#enter sib2, iclass 25, count 2 2006.239.08:16:30.48#ibcon#flushed, iclass 25, count 2 2006.239.08:16:30.48#ibcon#about to write, iclass 25, count 2 2006.239.08:16:30.48#ibcon#wrote, iclass 25, count 2 2006.239.08:16:30.48#ibcon#about to read 3, iclass 25, count 2 2006.239.08:16:30.50#abcon#<5=/04 2.0 4.2 25.02 811011.5\r\n> 2006.239.08:16:30.50#ibcon#read 3, iclass 25, count 2 2006.239.08:16:30.50#ibcon#about to read 4, iclass 25, count 2 2006.239.08:16:30.50#ibcon#read 4, iclass 25, count 2 2006.239.08:16:30.50#ibcon#about to read 5, iclass 25, count 2 2006.239.08:16:30.50#ibcon#read 5, iclass 25, count 2 2006.239.08:16:30.50#ibcon#about to read 6, iclass 25, count 2 2006.239.08:16:30.50#ibcon#read 6, iclass 25, count 2 2006.239.08:16:30.50#ibcon#end of sib2, iclass 25, count 2 2006.239.08:16:30.50#ibcon#*mode == 0, iclass 25, count 2 2006.239.08:16:30.50#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.239.08:16:30.50#ibcon#[25=AT08-07\r\n] 2006.239.08:16:30.50#ibcon#*before write, iclass 25, count 2 2006.239.08:16:30.50#ibcon#enter sib2, iclass 25, count 2 2006.239.08:16:30.50#ibcon#flushed, iclass 25, count 2 2006.239.08:16:30.50#ibcon#about to write, iclass 25, count 2 2006.239.08:16:30.50#ibcon#wrote, iclass 25, count 2 2006.239.08:16:30.50#ibcon#about to read 3, iclass 25, count 2 2006.239.08:16:30.51#abcon#{5=INTERFACE CLEAR} 2006.239.08:16:30.53#ibcon#read 3, iclass 25, count 2 2006.239.08:16:30.53#ibcon#about to read 4, iclass 25, count 2 2006.239.08:16:30.53#ibcon#read 4, iclass 25, count 2 2006.239.08:16:30.53#ibcon#about to read 5, iclass 25, count 2 2006.239.08:16:30.53#ibcon#read 5, iclass 25, count 2 2006.239.08:16:30.53#ibcon#about to read 6, iclass 25, count 2 2006.239.08:16:30.53#ibcon#read 6, iclass 25, count 2 2006.239.08:16:30.53#ibcon#end of sib2, iclass 25, count 2 2006.239.08:16:30.53#ibcon#*after write, iclass 25, count 2 2006.239.08:16:30.53#ibcon#*before return 0, iclass 25, count 2 2006.239.08:16:30.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:16:30.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.239.08:16:30.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.239.08:16:30.53#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:30.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:16:30.57#abcon#[5=S1D000X0/0*\r\n] 2006.239.08:16:30.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:16:30.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:16:30.65#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:16:30.65#ibcon#first serial, iclass 25, count 0 2006.239.08:16:30.65#ibcon#enter sib2, iclass 25, count 0 2006.239.08:16:30.65#ibcon#flushed, iclass 25, count 0 2006.239.08:16:30.65#ibcon#about to write, iclass 25, count 0 2006.239.08:16:30.65#ibcon#wrote, iclass 25, count 0 2006.239.08:16:30.65#ibcon#about to read 3, iclass 25, count 0 2006.239.08:16:30.67#ibcon#read 3, iclass 25, count 0 2006.239.08:16:30.67#ibcon#about to read 4, iclass 25, count 0 2006.239.08:16:30.67#ibcon#read 4, iclass 25, count 0 2006.239.08:16:30.67#ibcon#about to read 5, iclass 25, count 0 2006.239.08:16:30.67#ibcon#read 5, iclass 25, count 0 2006.239.08:16:30.67#ibcon#about to read 6, iclass 25, count 0 2006.239.08:16:30.67#ibcon#read 6, iclass 25, count 0 2006.239.08:16:30.67#ibcon#end of sib2, iclass 25, count 0 2006.239.08:16:30.67#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:16:30.67#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:16:30.67#ibcon#[25=USB\r\n] 2006.239.08:16:30.67#ibcon#*before write, iclass 25, count 0 2006.239.08:16:30.67#ibcon#enter sib2, iclass 25, count 0 2006.239.08:16:30.67#ibcon#flushed, iclass 25, count 0 2006.239.08:16:30.67#ibcon#about to write, iclass 25, count 0 2006.239.08:16:30.67#ibcon#wrote, iclass 25, count 0 2006.239.08:16:30.67#ibcon#about to read 3, iclass 25, count 0 2006.239.08:16:30.70#ibcon#read 3, iclass 25, count 0 2006.239.08:16:30.70#ibcon#about to read 4, iclass 25, count 0 2006.239.08:16:30.70#ibcon#read 4, iclass 25, count 0 2006.239.08:16:30.70#ibcon#about to read 5, iclass 25, count 0 2006.239.08:16:30.70#ibcon#read 5, iclass 25, count 0 2006.239.08:16:30.70#ibcon#about to read 6, iclass 25, count 0 2006.239.08:16:30.70#ibcon#read 6, iclass 25, count 0 2006.239.08:16:30.70#ibcon#end of sib2, iclass 25, count 0 2006.239.08:16:30.70#ibcon#*after write, iclass 25, count 0 2006.239.08:16:30.70#ibcon#*before return 0, iclass 25, count 0 2006.239.08:16:30.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:16:30.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.239.08:16:30.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:16:30.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:16:30.70$vc4f8/vblo=1,632.99 2006.239.08:16:30.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.239.08:16:30.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.239.08:16:30.70#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:30.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:30.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:30.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:30.70#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:16:30.70#ibcon#first serial, iclass 31, count 0 2006.239.08:16:30.70#ibcon#enter sib2, iclass 31, count 0 2006.239.08:16:30.70#ibcon#flushed, iclass 31, count 0 2006.239.08:16:30.70#ibcon#about to write, iclass 31, count 0 2006.239.08:16:30.70#ibcon#wrote, iclass 31, count 0 2006.239.08:16:30.70#ibcon#about to read 3, iclass 31, count 0 2006.239.08:16:30.72#ibcon#read 3, iclass 31, count 0 2006.239.08:16:30.72#ibcon#about to read 4, iclass 31, count 0 2006.239.08:16:30.72#ibcon#read 4, iclass 31, count 0 2006.239.08:16:30.72#ibcon#about to read 5, iclass 31, count 0 2006.239.08:16:30.72#ibcon#read 5, iclass 31, count 0 2006.239.08:16:30.72#ibcon#about to read 6, iclass 31, count 0 2006.239.08:16:30.72#ibcon#read 6, iclass 31, count 0 2006.239.08:16:30.72#ibcon#end of sib2, iclass 31, count 0 2006.239.08:16:30.72#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:16:30.72#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:16:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:16:30.72#ibcon#*before write, iclass 31, count 0 2006.239.08:16:30.72#ibcon#enter sib2, iclass 31, count 0 2006.239.08:16:30.72#ibcon#flushed, iclass 31, count 0 2006.239.08:16:30.72#ibcon#about to write, iclass 31, count 0 2006.239.08:16:30.72#ibcon#wrote, iclass 31, count 0 2006.239.08:16:30.72#ibcon#about to read 3, iclass 31, count 0 2006.239.08:16:30.76#ibcon#read 3, iclass 31, count 0 2006.239.08:16:30.76#ibcon#about to read 4, iclass 31, count 0 2006.239.08:16:30.76#ibcon#read 4, iclass 31, count 0 2006.239.08:16:30.76#ibcon#about to read 5, iclass 31, count 0 2006.239.08:16:30.76#ibcon#read 5, iclass 31, count 0 2006.239.08:16:30.76#ibcon#about to read 6, iclass 31, count 0 2006.239.08:16:30.76#ibcon#read 6, iclass 31, count 0 2006.239.08:16:30.76#ibcon#end of sib2, iclass 31, count 0 2006.239.08:16:30.76#ibcon#*after write, iclass 31, count 0 2006.239.08:16:30.76#ibcon#*before return 0, iclass 31, count 0 2006.239.08:16:30.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:30.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.239.08:16:30.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:16:30.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:16:30.76$vc4f8/vb=1,4 2006.239.08:16:30.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.239.08:16:30.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.239.08:16:30.76#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:30.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:30.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:30.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:30.76#ibcon#enter wrdev, iclass 33, count 2 2006.239.08:16:30.76#ibcon#first serial, iclass 33, count 2 2006.239.08:16:30.76#ibcon#enter sib2, iclass 33, count 2 2006.239.08:16:30.76#ibcon#flushed, iclass 33, count 2 2006.239.08:16:30.76#ibcon#about to write, iclass 33, count 2 2006.239.08:16:30.76#ibcon#wrote, iclass 33, count 2 2006.239.08:16:30.76#ibcon#about to read 3, iclass 33, count 2 2006.239.08:16:30.78#ibcon#read 3, iclass 33, count 2 2006.239.08:16:30.78#ibcon#about to read 4, iclass 33, count 2 2006.239.08:16:30.78#ibcon#read 4, iclass 33, count 2 2006.239.08:16:30.78#ibcon#about to read 5, iclass 33, count 2 2006.239.08:16:30.78#ibcon#read 5, iclass 33, count 2 2006.239.08:16:30.78#ibcon#about to read 6, iclass 33, count 2 2006.239.08:16:30.78#ibcon#read 6, iclass 33, count 2 2006.239.08:16:30.78#ibcon#end of sib2, iclass 33, count 2 2006.239.08:16:30.78#ibcon#*mode == 0, iclass 33, count 2 2006.239.08:16:30.78#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.239.08:16:30.78#ibcon#[27=AT01-04\r\n] 2006.239.08:16:30.78#ibcon#*before write, iclass 33, count 2 2006.239.08:16:30.78#ibcon#enter sib2, iclass 33, count 2 2006.239.08:16:30.78#ibcon#flushed, iclass 33, count 2 2006.239.08:16:30.78#ibcon#about to write, iclass 33, count 2 2006.239.08:16:30.78#ibcon#wrote, iclass 33, count 2 2006.239.08:16:30.78#ibcon#about to read 3, iclass 33, count 2 2006.239.08:16:30.81#ibcon#read 3, iclass 33, count 2 2006.239.08:16:30.81#ibcon#about to read 4, iclass 33, count 2 2006.239.08:16:30.81#ibcon#read 4, iclass 33, count 2 2006.239.08:16:30.81#ibcon#about to read 5, iclass 33, count 2 2006.239.08:16:30.81#ibcon#read 5, iclass 33, count 2 2006.239.08:16:30.81#ibcon#about to read 6, iclass 33, count 2 2006.239.08:16:30.81#ibcon#read 6, iclass 33, count 2 2006.239.08:16:30.81#ibcon#end of sib2, iclass 33, count 2 2006.239.08:16:30.81#ibcon#*after write, iclass 33, count 2 2006.239.08:16:30.81#ibcon#*before return 0, iclass 33, count 2 2006.239.08:16:30.81#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:30.81#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.239.08:16:30.81#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.239.08:16:30.81#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:30.81#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:30.93#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:30.93#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:30.93#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:16:30.93#ibcon#first serial, iclass 33, count 0 2006.239.08:16:30.93#ibcon#enter sib2, iclass 33, count 0 2006.239.08:16:30.93#ibcon#flushed, iclass 33, count 0 2006.239.08:16:30.93#ibcon#about to write, iclass 33, count 0 2006.239.08:16:30.93#ibcon#wrote, iclass 33, count 0 2006.239.08:16:30.93#ibcon#about to read 3, iclass 33, count 0 2006.239.08:16:30.95#ibcon#read 3, iclass 33, count 0 2006.239.08:16:30.95#ibcon#about to read 4, iclass 33, count 0 2006.239.08:16:30.95#ibcon#read 4, iclass 33, count 0 2006.239.08:16:30.95#ibcon#about to read 5, iclass 33, count 0 2006.239.08:16:30.95#ibcon#read 5, iclass 33, count 0 2006.239.08:16:30.95#ibcon#about to read 6, iclass 33, count 0 2006.239.08:16:30.95#ibcon#read 6, iclass 33, count 0 2006.239.08:16:30.95#ibcon#end of sib2, iclass 33, count 0 2006.239.08:16:30.95#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:16:30.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:16:30.95#ibcon#[27=USB\r\n] 2006.239.08:16:30.95#ibcon#*before write, iclass 33, count 0 2006.239.08:16:30.95#ibcon#enter sib2, iclass 33, count 0 2006.239.08:16:30.95#ibcon#flushed, iclass 33, count 0 2006.239.08:16:30.95#ibcon#about to write, iclass 33, count 0 2006.239.08:16:30.95#ibcon#wrote, iclass 33, count 0 2006.239.08:16:30.95#ibcon#about to read 3, iclass 33, count 0 2006.239.08:16:30.98#ibcon#read 3, iclass 33, count 0 2006.239.08:16:30.98#ibcon#about to read 4, iclass 33, count 0 2006.239.08:16:30.98#ibcon#read 4, iclass 33, count 0 2006.239.08:16:30.98#ibcon#about to read 5, iclass 33, count 0 2006.239.08:16:30.98#ibcon#read 5, iclass 33, count 0 2006.239.08:16:30.98#ibcon#about to read 6, iclass 33, count 0 2006.239.08:16:30.98#ibcon#read 6, iclass 33, count 0 2006.239.08:16:30.98#ibcon#end of sib2, iclass 33, count 0 2006.239.08:16:30.98#ibcon#*after write, iclass 33, count 0 2006.239.08:16:30.98#ibcon#*before return 0, iclass 33, count 0 2006.239.08:16:30.98#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:30.98#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.239.08:16:30.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:16:30.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:16:30.98$vc4f8/vblo=2,640.99 2006.239.08:16:30.98#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.239.08:16:30.98#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.239.08:16:30.98#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:30.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:30.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:30.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:30.98#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:16:30.98#ibcon#first serial, iclass 35, count 0 2006.239.08:16:30.98#ibcon#enter sib2, iclass 35, count 0 2006.239.08:16:30.98#ibcon#flushed, iclass 35, count 0 2006.239.08:16:30.98#ibcon#about to write, iclass 35, count 0 2006.239.08:16:30.98#ibcon#wrote, iclass 35, count 0 2006.239.08:16:30.98#ibcon#about to read 3, iclass 35, count 0 2006.239.08:16:31.00#ibcon#read 3, iclass 35, count 0 2006.239.08:16:31.00#ibcon#about to read 4, iclass 35, count 0 2006.239.08:16:31.00#ibcon#read 4, iclass 35, count 0 2006.239.08:16:31.00#ibcon#about to read 5, iclass 35, count 0 2006.239.08:16:31.00#ibcon#read 5, iclass 35, count 0 2006.239.08:16:31.00#ibcon#about to read 6, iclass 35, count 0 2006.239.08:16:31.00#ibcon#read 6, iclass 35, count 0 2006.239.08:16:31.00#ibcon#end of sib2, iclass 35, count 0 2006.239.08:16:31.00#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:16:31.00#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:16:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:16:31.00#ibcon#*before write, iclass 35, count 0 2006.239.08:16:31.00#ibcon#enter sib2, iclass 35, count 0 2006.239.08:16:31.00#ibcon#flushed, iclass 35, count 0 2006.239.08:16:31.00#ibcon#about to write, iclass 35, count 0 2006.239.08:16:31.00#ibcon#wrote, iclass 35, count 0 2006.239.08:16:31.00#ibcon#about to read 3, iclass 35, count 0 2006.239.08:16:31.04#ibcon#read 3, iclass 35, count 0 2006.239.08:16:31.04#ibcon#about to read 4, iclass 35, count 0 2006.239.08:16:31.04#ibcon#read 4, iclass 35, count 0 2006.239.08:16:31.04#ibcon#about to read 5, iclass 35, count 0 2006.239.08:16:31.04#ibcon#read 5, iclass 35, count 0 2006.239.08:16:31.04#ibcon#about to read 6, iclass 35, count 0 2006.239.08:16:31.04#ibcon#read 6, iclass 35, count 0 2006.239.08:16:31.04#ibcon#end of sib2, iclass 35, count 0 2006.239.08:16:31.04#ibcon#*after write, iclass 35, count 0 2006.239.08:16:31.04#ibcon#*before return 0, iclass 35, count 0 2006.239.08:16:31.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:31.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.239.08:16:31.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:16:31.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:16:31.04$vc4f8/vb=2,4 2006.239.08:16:31.04#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.239.08:16:31.04#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.239.08:16:31.04#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:31.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:31.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:31.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:31.10#ibcon#enter wrdev, iclass 37, count 2 2006.239.08:16:31.10#ibcon#first serial, iclass 37, count 2 2006.239.08:16:31.10#ibcon#enter sib2, iclass 37, count 2 2006.239.08:16:31.10#ibcon#flushed, iclass 37, count 2 2006.239.08:16:31.10#ibcon#about to write, iclass 37, count 2 2006.239.08:16:31.10#ibcon#wrote, iclass 37, count 2 2006.239.08:16:31.10#ibcon#about to read 3, iclass 37, count 2 2006.239.08:16:31.12#ibcon#read 3, iclass 37, count 2 2006.239.08:16:31.12#ibcon#about to read 4, iclass 37, count 2 2006.239.08:16:31.12#ibcon#read 4, iclass 37, count 2 2006.239.08:16:31.12#ibcon#about to read 5, iclass 37, count 2 2006.239.08:16:31.12#ibcon#read 5, iclass 37, count 2 2006.239.08:16:31.12#ibcon#about to read 6, iclass 37, count 2 2006.239.08:16:31.12#ibcon#read 6, iclass 37, count 2 2006.239.08:16:31.12#ibcon#end of sib2, iclass 37, count 2 2006.239.08:16:31.12#ibcon#*mode == 0, iclass 37, count 2 2006.239.08:16:31.12#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.239.08:16:31.12#ibcon#[27=AT02-04\r\n] 2006.239.08:16:31.12#ibcon#*before write, iclass 37, count 2 2006.239.08:16:31.12#ibcon#enter sib2, iclass 37, count 2 2006.239.08:16:31.12#ibcon#flushed, iclass 37, count 2 2006.239.08:16:31.12#ibcon#about to write, iclass 37, count 2 2006.239.08:16:31.12#ibcon#wrote, iclass 37, count 2 2006.239.08:16:31.12#ibcon#about to read 3, iclass 37, count 2 2006.239.08:16:31.15#ibcon#read 3, iclass 37, count 2 2006.239.08:16:31.15#ibcon#about to read 4, iclass 37, count 2 2006.239.08:16:31.15#ibcon#read 4, iclass 37, count 2 2006.239.08:16:31.15#ibcon#about to read 5, iclass 37, count 2 2006.239.08:16:31.15#ibcon#read 5, iclass 37, count 2 2006.239.08:16:31.15#ibcon#about to read 6, iclass 37, count 2 2006.239.08:16:31.15#ibcon#read 6, iclass 37, count 2 2006.239.08:16:31.15#ibcon#end of sib2, iclass 37, count 2 2006.239.08:16:31.15#ibcon#*after write, iclass 37, count 2 2006.239.08:16:31.15#ibcon#*before return 0, iclass 37, count 2 2006.239.08:16:31.15#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:31.15#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.239.08:16:31.15#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.239.08:16:31.15#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:31.15#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:31.27#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:31.27#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:31.27#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:16:31.27#ibcon#first serial, iclass 37, count 0 2006.239.08:16:31.27#ibcon#enter sib2, iclass 37, count 0 2006.239.08:16:31.27#ibcon#flushed, iclass 37, count 0 2006.239.08:16:31.27#ibcon#about to write, iclass 37, count 0 2006.239.08:16:31.27#ibcon#wrote, iclass 37, count 0 2006.239.08:16:31.27#ibcon#about to read 3, iclass 37, count 0 2006.239.08:16:31.29#ibcon#read 3, iclass 37, count 0 2006.239.08:16:31.29#ibcon#about to read 4, iclass 37, count 0 2006.239.08:16:31.29#ibcon#read 4, iclass 37, count 0 2006.239.08:16:31.29#ibcon#about to read 5, iclass 37, count 0 2006.239.08:16:31.29#ibcon#read 5, iclass 37, count 0 2006.239.08:16:31.29#ibcon#about to read 6, iclass 37, count 0 2006.239.08:16:31.29#ibcon#read 6, iclass 37, count 0 2006.239.08:16:31.29#ibcon#end of sib2, iclass 37, count 0 2006.239.08:16:31.29#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:16:31.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:16:31.29#ibcon#[27=USB\r\n] 2006.239.08:16:31.29#ibcon#*before write, iclass 37, count 0 2006.239.08:16:31.29#ibcon#enter sib2, iclass 37, count 0 2006.239.08:16:31.29#ibcon#flushed, iclass 37, count 0 2006.239.08:16:31.29#ibcon#about to write, iclass 37, count 0 2006.239.08:16:31.29#ibcon#wrote, iclass 37, count 0 2006.239.08:16:31.29#ibcon#about to read 3, iclass 37, count 0 2006.239.08:16:31.32#ibcon#read 3, iclass 37, count 0 2006.239.08:16:31.32#ibcon#about to read 4, iclass 37, count 0 2006.239.08:16:31.32#ibcon#read 4, iclass 37, count 0 2006.239.08:16:31.32#ibcon#about to read 5, iclass 37, count 0 2006.239.08:16:31.32#ibcon#read 5, iclass 37, count 0 2006.239.08:16:31.32#ibcon#about to read 6, iclass 37, count 0 2006.239.08:16:31.32#ibcon#read 6, iclass 37, count 0 2006.239.08:16:31.32#ibcon#end of sib2, iclass 37, count 0 2006.239.08:16:31.32#ibcon#*after write, iclass 37, count 0 2006.239.08:16:31.32#ibcon#*before return 0, iclass 37, count 0 2006.239.08:16:31.32#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:31.32#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.239.08:16:31.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:16:31.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:16:31.32$vc4f8/vblo=3,656.99 2006.239.08:16:31.32#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:16:31.32#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:16:31.32#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:31.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:31.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:31.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:31.32#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:16:31.32#ibcon#first serial, iclass 39, count 0 2006.239.08:16:31.32#ibcon#enter sib2, iclass 39, count 0 2006.239.08:16:31.32#ibcon#flushed, iclass 39, count 0 2006.239.08:16:31.32#ibcon#about to write, iclass 39, count 0 2006.239.08:16:31.32#ibcon#wrote, iclass 39, count 0 2006.239.08:16:31.32#ibcon#about to read 3, iclass 39, count 0 2006.239.08:16:31.34#ibcon#read 3, iclass 39, count 0 2006.239.08:16:31.34#ibcon#about to read 4, iclass 39, count 0 2006.239.08:16:31.34#ibcon#read 4, iclass 39, count 0 2006.239.08:16:31.34#ibcon#about to read 5, iclass 39, count 0 2006.239.08:16:31.34#ibcon#read 5, iclass 39, count 0 2006.239.08:16:31.34#ibcon#about to read 6, iclass 39, count 0 2006.239.08:16:31.34#ibcon#read 6, iclass 39, count 0 2006.239.08:16:31.34#ibcon#end of sib2, iclass 39, count 0 2006.239.08:16:31.34#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:16:31.34#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:16:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:16:31.34#ibcon#*before write, iclass 39, count 0 2006.239.08:16:31.34#ibcon#enter sib2, iclass 39, count 0 2006.239.08:16:31.34#ibcon#flushed, iclass 39, count 0 2006.239.08:16:31.34#ibcon#about to write, iclass 39, count 0 2006.239.08:16:31.34#ibcon#wrote, iclass 39, count 0 2006.239.08:16:31.34#ibcon#about to read 3, iclass 39, count 0 2006.239.08:16:31.38#ibcon#read 3, iclass 39, count 0 2006.239.08:16:31.38#ibcon#about to read 4, iclass 39, count 0 2006.239.08:16:31.38#ibcon#read 4, iclass 39, count 0 2006.239.08:16:31.38#ibcon#about to read 5, iclass 39, count 0 2006.239.08:16:31.38#ibcon#read 5, iclass 39, count 0 2006.239.08:16:31.38#ibcon#about to read 6, iclass 39, count 0 2006.239.08:16:31.38#ibcon#read 6, iclass 39, count 0 2006.239.08:16:31.38#ibcon#end of sib2, iclass 39, count 0 2006.239.08:16:31.38#ibcon#*after write, iclass 39, count 0 2006.239.08:16:31.38#ibcon#*before return 0, iclass 39, count 0 2006.239.08:16:31.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:31.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:16:31.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:16:31.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:16:31.38$vc4f8/vb=3,4 2006.239.08:16:31.38#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.239.08:16:31.38#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.239.08:16:31.38#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:31.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:31.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:31.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:31.45#ibcon#enter wrdev, iclass 3, count 2 2006.239.08:16:31.45#ibcon#first serial, iclass 3, count 2 2006.239.08:16:31.45#ibcon#enter sib2, iclass 3, count 2 2006.239.08:16:31.45#ibcon#flushed, iclass 3, count 2 2006.239.08:16:31.45#ibcon#about to write, iclass 3, count 2 2006.239.08:16:31.45#ibcon#wrote, iclass 3, count 2 2006.239.08:16:31.45#ibcon#about to read 3, iclass 3, count 2 2006.239.08:16:31.46#ibcon#read 3, iclass 3, count 2 2006.239.08:16:31.46#ibcon#about to read 4, iclass 3, count 2 2006.239.08:16:31.46#ibcon#read 4, iclass 3, count 2 2006.239.08:16:31.46#ibcon#about to read 5, iclass 3, count 2 2006.239.08:16:31.46#ibcon#read 5, iclass 3, count 2 2006.239.08:16:31.46#ibcon#about to read 6, iclass 3, count 2 2006.239.08:16:31.46#ibcon#read 6, iclass 3, count 2 2006.239.08:16:31.46#ibcon#end of sib2, iclass 3, count 2 2006.239.08:16:31.46#ibcon#*mode == 0, iclass 3, count 2 2006.239.08:16:31.46#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.239.08:16:31.46#ibcon#[27=AT03-04\r\n] 2006.239.08:16:31.46#ibcon#*before write, iclass 3, count 2 2006.239.08:16:31.46#ibcon#enter sib2, iclass 3, count 2 2006.239.08:16:31.46#ibcon#flushed, iclass 3, count 2 2006.239.08:16:31.46#ibcon#about to write, iclass 3, count 2 2006.239.08:16:31.46#ibcon#wrote, iclass 3, count 2 2006.239.08:16:31.46#ibcon#about to read 3, iclass 3, count 2 2006.239.08:16:31.49#ibcon#read 3, iclass 3, count 2 2006.239.08:16:31.49#ibcon#about to read 4, iclass 3, count 2 2006.239.08:16:31.49#ibcon#read 4, iclass 3, count 2 2006.239.08:16:31.49#ibcon#about to read 5, iclass 3, count 2 2006.239.08:16:31.49#ibcon#read 5, iclass 3, count 2 2006.239.08:16:31.49#ibcon#about to read 6, iclass 3, count 2 2006.239.08:16:31.49#ibcon#read 6, iclass 3, count 2 2006.239.08:16:31.49#ibcon#end of sib2, iclass 3, count 2 2006.239.08:16:31.49#ibcon#*after write, iclass 3, count 2 2006.239.08:16:31.49#ibcon#*before return 0, iclass 3, count 2 2006.239.08:16:31.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:31.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.239.08:16:31.49#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.239.08:16:31.49#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:31.49#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:31.61#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:31.61#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:31.61#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:16:31.61#ibcon#first serial, iclass 3, count 0 2006.239.08:16:31.61#ibcon#enter sib2, iclass 3, count 0 2006.239.08:16:31.61#ibcon#flushed, iclass 3, count 0 2006.239.08:16:31.61#ibcon#about to write, iclass 3, count 0 2006.239.08:16:31.61#ibcon#wrote, iclass 3, count 0 2006.239.08:16:31.61#ibcon#about to read 3, iclass 3, count 0 2006.239.08:16:31.63#ibcon#read 3, iclass 3, count 0 2006.239.08:16:31.63#ibcon#about to read 4, iclass 3, count 0 2006.239.08:16:31.63#ibcon#read 4, iclass 3, count 0 2006.239.08:16:31.63#ibcon#about to read 5, iclass 3, count 0 2006.239.08:16:31.63#ibcon#read 5, iclass 3, count 0 2006.239.08:16:31.63#ibcon#about to read 6, iclass 3, count 0 2006.239.08:16:31.63#ibcon#read 6, iclass 3, count 0 2006.239.08:16:31.63#ibcon#end of sib2, iclass 3, count 0 2006.239.08:16:31.63#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:16:31.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:16:31.63#ibcon#[27=USB\r\n] 2006.239.08:16:31.63#ibcon#*before write, iclass 3, count 0 2006.239.08:16:31.63#ibcon#enter sib2, iclass 3, count 0 2006.239.08:16:31.63#ibcon#flushed, iclass 3, count 0 2006.239.08:16:31.63#ibcon#about to write, iclass 3, count 0 2006.239.08:16:31.63#ibcon#wrote, iclass 3, count 0 2006.239.08:16:31.63#ibcon#about to read 3, iclass 3, count 0 2006.239.08:16:31.66#ibcon#read 3, iclass 3, count 0 2006.239.08:16:31.66#ibcon#about to read 4, iclass 3, count 0 2006.239.08:16:31.66#ibcon#read 4, iclass 3, count 0 2006.239.08:16:31.66#ibcon#about to read 5, iclass 3, count 0 2006.239.08:16:31.66#ibcon#read 5, iclass 3, count 0 2006.239.08:16:31.66#ibcon#about to read 6, iclass 3, count 0 2006.239.08:16:31.66#ibcon#read 6, iclass 3, count 0 2006.239.08:16:31.66#ibcon#end of sib2, iclass 3, count 0 2006.239.08:16:31.66#ibcon#*after write, iclass 3, count 0 2006.239.08:16:31.66#ibcon#*before return 0, iclass 3, count 0 2006.239.08:16:31.66#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:31.66#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.239.08:16:31.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:16:31.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:16:31.66$vc4f8/vblo=4,712.99 2006.239.08:16:31.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.239.08:16:31.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.239.08:16:31.66#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:31.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:31.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:31.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:31.66#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:16:31.66#ibcon#first serial, iclass 5, count 0 2006.239.08:16:31.66#ibcon#enter sib2, iclass 5, count 0 2006.239.08:16:31.66#ibcon#flushed, iclass 5, count 0 2006.239.08:16:31.66#ibcon#about to write, iclass 5, count 0 2006.239.08:16:31.66#ibcon#wrote, iclass 5, count 0 2006.239.08:16:31.66#ibcon#about to read 3, iclass 5, count 0 2006.239.08:16:31.68#ibcon#read 3, iclass 5, count 0 2006.239.08:16:31.68#ibcon#about to read 4, iclass 5, count 0 2006.239.08:16:31.68#ibcon#read 4, iclass 5, count 0 2006.239.08:16:31.68#ibcon#about to read 5, iclass 5, count 0 2006.239.08:16:31.68#ibcon#read 5, iclass 5, count 0 2006.239.08:16:31.68#ibcon#about to read 6, iclass 5, count 0 2006.239.08:16:31.68#ibcon#read 6, iclass 5, count 0 2006.239.08:16:31.68#ibcon#end of sib2, iclass 5, count 0 2006.239.08:16:31.68#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:16:31.68#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:16:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:16:31.68#ibcon#*before write, iclass 5, count 0 2006.239.08:16:31.68#ibcon#enter sib2, iclass 5, count 0 2006.239.08:16:31.68#ibcon#flushed, iclass 5, count 0 2006.239.08:16:31.68#ibcon#about to write, iclass 5, count 0 2006.239.08:16:31.68#ibcon#wrote, iclass 5, count 0 2006.239.08:16:31.68#ibcon#about to read 3, iclass 5, count 0 2006.239.08:16:31.72#ibcon#read 3, iclass 5, count 0 2006.239.08:16:31.72#ibcon#about to read 4, iclass 5, count 0 2006.239.08:16:31.72#ibcon#read 4, iclass 5, count 0 2006.239.08:16:31.72#ibcon#about to read 5, iclass 5, count 0 2006.239.08:16:31.72#ibcon#read 5, iclass 5, count 0 2006.239.08:16:31.72#ibcon#about to read 6, iclass 5, count 0 2006.239.08:16:31.72#ibcon#read 6, iclass 5, count 0 2006.239.08:16:31.72#ibcon#end of sib2, iclass 5, count 0 2006.239.08:16:31.72#ibcon#*after write, iclass 5, count 0 2006.239.08:16:31.72#ibcon#*before return 0, iclass 5, count 0 2006.239.08:16:31.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:31.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.239.08:16:31.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:16:31.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:16:31.72$vc4f8/vb=4,4 2006.239.08:16:31.72#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.239.08:16:31.72#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.239.08:16:31.72#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:31.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:31.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:31.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:31.78#ibcon#enter wrdev, iclass 7, count 2 2006.239.08:16:31.78#ibcon#first serial, iclass 7, count 2 2006.239.08:16:31.78#ibcon#enter sib2, iclass 7, count 2 2006.239.08:16:31.78#ibcon#flushed, iclass 7, count 2 2006.239.08:16:31.78#ibcon#about to write, iclass 7, count 2 2006.239.08:16:31.78#ibcon#wrote, iclass 7, count 2 2006.239.08:16:31.78#ibcon#about to read 3, iclass 7, count 2 2006.239.08:16:31.80#ibcon#read 3, iclass 7, count 2 2006.239.08:16:31.80#ibcon#about to read 4, iclass 7, count 2 2006.239.08:16:31.80#ibcon#read 4, iclass 7, count 2 2006.239.08:16:31.80#ibcon#about to read 5, iclass 7, count 2 2006.239.08:16:31.80#ibcon#read 5, iclass 7, count 2 2006.239.08:16:31.80#ibcon#about to read 6, iclass 7, count 2 2006.239.08:16:31.80#ibcon#read 6, iclass 7, count 2 2006.239.08:16:31.80#ibcon#end of sib2, iclass 7, count 2 2006.239.08:16:31.80#ibcon#*mode == 0, iclass 7, count 2 2006.239.08:16:31.80#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.239.08:16:31.80#ibcon#[27=AT04-04\r\n] 2006.239.08:16:31.80#ibcon#*before write, iclass 7, count 2 2006.239.08:16:31.80#ibcon#enter sib2, iclass 7, count 2 2006.239.08:16:31.80#ibcon#flushed, iclass 7, count 2 2006.239.08:16:31.80#ibcon#about to write, iclass 7, count 2 2006.239.08:16:31.80#ibcon#wrote, iclass 7, count 2 2006.239.08:16:31.80#ibcon#about to read 3, iclass 7, count 2 2006.239.08:16:31.83#ibcon#read 3, iclass 7, count 2 2006.239.08:16:31.83#ibcon#about to read 4, iclass 7, count 2 2006.239.08:16:31.83#ibcon#read 4, iclass 7, count 2 2006.239.08:16:31.83#ibcon#about to read 5, iclass 7, count 2 2006.239.08:16:31.83#ibcon#read 5, iclass 7, count 2 2006.239.08:16:31.83#ibcon#about to read 6, iclass 7, count 2 2006.239.08:16:31.83#ibcon#read 6, iclass 7, count 2 2006.239.08:16:31.83#ibcon#end of sib2, iclass 7, count 2 2006.239.08:16:31.83#ibcon#*after write, iclass 7, count 2 2006.239.08:16:31.83#ibcon#*before return 0, iclass 7, count 2 2006.239.08:16:31.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:31.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.239.08:16:31.83#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.239.08:16:31.83#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:31.83#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:31.95#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:31.95#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:31.95#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:16:31.95#ibcon#first serial, iclass 7, count 0 2006.239.08:16:31.95#ibcon#enter sib2, iclass 7, count 0 2006.239.08:16:31.95#ibcon#flushed, iclass 7, count 0 2006.239.08:16:31.95#ibcon#about to write, iclass 7, count 0 2006.239.08:16:31.95#ibcon#wrote, iclass 7, count 0 2006.239.08:16:31.95#ibcon#about to read 3, iclass 7, count 0 2006.239.08:16:31.97#ibcon#read 3, iclass 7, count 0 2006.239.08:16:31.97#ibcon#about to read 4, iclass 7, count 0 2006.239.08:16:31.97#ibcon#read 4, iclass 7, count 0 2006.239.08:16:31.97#ibcon#about to read 5, iclass 7, count 0 2006.239.08:16:31.97#ibcon#read 5, iclass 7, count 0 2006.239.08:16:31.97#ibcon#about to read 6, iclass 7, count 0 2006.239.08:16:31.97#ibcon#read 6, iclass 7, count 0 2006.239.08:16:31.97#ibcon#end of sib2, iclass 7, count 0 2006.239.08:16:31.97#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:16:31.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:16:31.97#ibcon#[27=USB\r\n] 2006.239.08:16:31.97#ibcon#*before write, iclass 7, count 0 2006.239.08:16:31.97#ibcon#enter sib2, iclass 7, count 0 2006.239.08:16:31.97#ibcon#flushed, iclass 7, count 0 2006.239.08:16:31.97#ibcon#about to write, iclass 7, count 0 2006.239.08:16:31.97#ibcon#wrote, iclass 7, count 0 2006.239.08:16:31.97#ibcon#about to read 3, iclass 7, count 0 2006.239.08:16:32.00#ibcon#read 3, iclass 7, count 0 2006.239.08:16:32.00#ibcon#about to read 4, iclass 7, count 0 2006.239.08:16:32.00#ibcon#read 4, iclass 7, count 0 2006.239.08:16:32.00#ibcon#about to read 5, iclass 7, count 0 2006.239.08:16:32.00#ibcon#read 5, iclass 7, count 0 2006.239.08:16:32.00#ibcon#about to read 6, iclass 7, count 0 2006.239.08:16:32.00#ibcon#read 6, iclass 7, count 0 2006.239.08:16:32.00#ibcon#end of sib2, iclass 7, count 0 2006.239.08:16:32.00#ibcon#*after write, iclass 7, count 0 2006.239.08:16:32.00#ibcon#*before return 0, iclass 7, count 0 2006.239.08:16:32.00#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:32.00#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.239.08:16:32.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:16:32.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:16:32.00$vc4f8/vblo=5,744.99 2006.239.08:16:32.00#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.239.08:16:32.00#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.239.08:16:32.00#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:32.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:32.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:32.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:32.00#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:16:32.00#ibcon#first serial, iclass 11, count 0 2006.239.08:16:32.00#ibcon#enter sib2, iclass 11, count 0 2006.239.08:16:32.00#ibcon#flushed, iclass 11, count 0 2006.239.08:16:32.00#ibcon#about to write, iclass 11, count 0 2006.239.08:16:32.00#ibcon#wrote, iclass 11, count 0 2006.239.08:16:32.00#ibcon#about to read 3, iclass 11, count 0 2006.239.08:16:32.02#ibcon#read 3, iclass 11, count 0 2006.239.08:16:32.02#ibcon#about to read 4, iclass 11, count 0 2006.239.08:16:32.02#ibcon#read 4, iclass 11, count 0 2006.239.08:16:32.02#ibcon#about to read 5, iclass 11, count 0 2006.239.08:16:32.02#ibcon#read 5, iclass 11, count 0 2006.239.08:16:32.02#ibcon#about to read 6, iclass 11, count 0 2006.239.08:16:32.02#ibcon#read 6, iclass 11, count 0 2006.239.08:16:32.02#ibcon#end of sib2, iclass 11, count 0 2006.239.08:16:32.02#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:16:32.02#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:16:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:16:32.02#ibcon#*before write, iclass 11, count 0 2006.239.08:16:32.02#ibcon#enter sib2, iclass 11, count 0 2006.239.08:16:32.02#ibcon#flushed, iclass 11, count 0 2006.239.08:16:32.02#ibcon#about to write, iclass 11, count 0 2006.239.08:16:32.02#ibcon#wrote, iclass 11, count 0 2006.239.08:16:32.02#ibcon#about to read 3, iclass 11, count 0 2006.239.08:16:32.06#ibcon#read 3, iclass 11, count 0 2006.239.08:16:32.06#ibcon#about to read 4, iclass 11, count 0 2006.239.08:16:32.06#ibcon#read 4, iclass 11, count 0 2006.239.08:16:32.06#ibcon#about to read 5, iclass 11, count 0 2006.239.08:16:32.06#ibcon#read 5, iclass 11, count 0 2006.239.08:16:32.06#ibcon#about to read 6, iclass 11, count 0 2006.239.08:16:32.06#ibcon#read 6, iclass 11, count 0 2006.239.08:16:32.06#ibcon#end of sib2, iclass 11, count 0 2006.239.08:16:32.06#ibcon#*after write, iclass 11, count 0 2006.239.08:16:32.06#ibcon#*before return 0, iclass 11, count 0 2006.239.08:16:32.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:32.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.239.08:16:32.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:16:32.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:16:32.06$vc4f8/vb=5,4 2006.239.08:16:32.06#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.239.08:16:32.06#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.239.08:16:32.06#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:32.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:32.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:32.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:32.13#ibcon#enter wrdev, iclass 13, count 2 2006.239.08:16:32.13#ibcon#first serial, iclass 13, count 2 2006.239.08:16:32.13#ibcon#enter sib2, iclass 13, count 2 2006.239.08:16:32.13#ibcon#flushed, iclass 13, count 2 2006.239.08:16:32.13#ibcon#about to write, iclass 13, count 2 2006.239.08:16:32.13#ibcon#wrote, iclass 13, count 2 2006.239.08:16:32.13#ibcon#about to read 3, iclass 13, count 2 2006.239.08:16:32.15#ibcon#read 3, iclass 13, count 2 2006.239.08:16:32.15#ibcon#about to read 4, iclass 13, count 2 2006.239.08:16:32.15#ibcon#read 4, iclass 13, count 2 2006.239.08:16:32.15#ibcon#about to read 5, iclass 13, count 2 2006.239.08:16:32.15#ibcon#read 5, iclass 13, count 2 2006.239.08:16:32.15#ibcon#about to read 6, iclass 13, count 2 2006.239.08:16:32.15#ibcon#read 6, iclass 13, count 2 2006.239.08:16:32.15#ibcon#end of sib2, iclass 13, count 2 2006.239.08:16:32.15#ibcon#*mode == 0, iclass 13, count 2 2006.239.08:16:32.15#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.239.08:16:32.15#ibcon#[27=AT05-04\r\n] 2006.239.08:16:32.15#ibcon#*before write, iclass 13, count 2 2006.239.08:16:32.15#ibcon#enter sib2, iclass 13, count 2 2006.239.08:16:32.15#ibcon#flushed, iclass 13, count 2 2006.239.08:16:32.15#ibcon#about to write, iclass 13, count 2 2006.239.08:16:32.15#ibcon#wrote, iclass 13, count 2 2006.239.08:16:32.15#ibcon#about to read 3, iclass 13, count 2 2006.239.08:16:32.17#ibcon#read 3, iclass 13, count 2 2006.239.08:16:32.17#ibcon#about to read 4, iclass 13, count 2 2006.239.08:16:32.17#ibcon#read 4, iclass 13, count 2 2006.239.08:16:32.17#ibcon#about to read 5, iclass 13, count 2 2006.239.08:16:32.17#ibcon#read 5, iclass 13, count 2 2006.239.08:16:32.17#ibcon#about to read 6, iclass 13, count 2 2006.239.08:16:32.17#ibcon#read 6, iclass 13, count 2 2006.239.08:16:32.17#ibcon#end of sib2, iclass 13, count 2 2006.239.08:16:32.17#ibcon#*after write, iclass 13, count 2 2006.239.08:16:32.17#ibcon#*before return 0, iclass 13, count 2 2006.239.08:16:32.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:32.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.239.08:16:32.17#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.239.08:16:32.17#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:32.17#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:32.29#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:32.29#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:32.29#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:16:32.29#ibcon#first serial, iclass 13, count 0 2006.239.08:16:32.29#ibcon#enter sib2, iclass 13, count 0 2006.239.08:16:32.29#ibcon#flushed, iclass 13, count 0 2006.239.08:16:32.29#ibcon#about to write, iclass 13, count 0 2006.239.08:16:32.29#ibcon#wrote, iclass 13, count 0 2006.239.08:16:32.29#ibcon#about to read 3, iclass 13, count 0 2006.239.08:16:32.31#ibcon#read 3, iclass 13, count 0 2006.239.08:16:32.31#ibcon#about to read 4, iclass 13, count 0 2006.239.08:16:32.31#ibcon#read 4, iclass 13, count 0 2006.239.08:16:32.31#ibcon#about to read 5, iclass 13, count 0 2006.239.08:16:32.31#ibcon#read 5, iclass 13, count 0 2006.239.08:16:32.31#ibcon#about to read 6, iclass 13, count 0 2006.239.08:16:32.31#ibcon#read 6, iclass 13, count 0 2006.239.08:16:32.31#ibcon#end of sib2, iclass 13, count 0 2006.239.08:16:32.31#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:16:32.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:16:32.31#ibcon#[27=USB\r\n] 2006.239.08:16:32.31#ibcon#*before write, iclass 13, count 0 2006.239.08:16:32.31#ibcon#enter sib2, iclass 13, count 0 2006.239.08:16:32.31#ibcon#flushed, iclass 13, count 0 2006.239.08:16:32.31#ibcon#about to write, iclass 13, count 0 2006.239.08:16:32.31#ibcon#wrote, iclass 13, count 0 2006.239.08:16:32.31#ibcon#about to read 3, iclass 13, count 0 2006.239.08:16:32.34#ibcon#read 3, iclass 13, count 0 2006.239.08:16:32.34#ibcon#about to read 4, iclass 13, count 0 2006.239.08:16:32.34#ibcon#read 4, iclass 13, count 0 2006.239.08:16:32.34#ibcon#about to read 5, iclass 13, count 0 2006.239.08:16:32.34#ibcon#read 5, iclass 13, count 0 2006.239.08:16:32.34#ibcon#about to read 6, iclass 13, count 0 2006.239.08:16:32.34#ibcon#read 6, iclass 13, count 0 2006.239.08:16:32.34#ibcon#end of sib2, iclass 13, count 0 2006.239.08:16:32.34#ibcon#*after write, iclass 13, count 0 2006.239.08:16:32.34#ibcon#*before return 0, iclass 13, count 0 2006.239.08:16:32.34#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:32.34#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.239.08:16:32.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:16:32.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:16:32.34$vc4f8/vblo=6,752.99 2006.239.08:16:32.34#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.239.08:16:32.34#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.239.08:16:32.34#ibcon#ireg 17 cls_cnt 0 2006.239.08:16:32.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:32.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:32.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:32.34#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:16:32.34#ibcon#first serial, iclass 15, count 0 2006.239.08:16:32.34#ibcon#enter sib2, iclass 15, count 0 2006.239.08:16:32.34#ibcon#flushed, iclass 15, count 0 2006.239.08:16:32.34#ibcon#about to write, iclass 15, count 0 2006.239.08:16:32.34#ibcon#wrote, iclass 15, count 0 2006.239.08:16:32.34#ibcon#about to read 3, iclass 15, count 0 2006.239.08:16:32.36#ibcon#read 3, iclass 15, count 0 2006.239.08:16:32.36#ibcon#about to read 4, iclass 15, count 0 2006.239.08:16:32.36#ibcon#read 4, iclass 15, count 0 2006.239.08:16:32.36#ibcon#about to read 5, iclass 15, count 0 2006.239.08:16:32.36#ibcon#read 5, iclass 15, count 0 2006.239.08:16:32.36#ibcon#about to read 6, iclass 15, count 0 2006.239.08:16:32.36#ibcon#read 6, iclass 15, count 0 2006.239.08:16:32.36#ibcon#end of sib2, iclass 15, count 0 2006.239.08:16:32.36#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:16:32.36#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:16:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:16:32.36#ibcon#*before write, iclass 15, count 0 2006.239.08:16:32.36#ibcon#enter sib2, iclass 15, count 0 2006.239.08:16:32.36#ibcon#flushed, iclass 15, count 0 2006.239.08:16:32.36#ibcon#about to write, iclass 15, count 0 2006.239.08:16:32.36#ibcon#wrote, iclass 15, count 0 2006.239.08:16:32.36#ibcon#about to read 3, iclass 15, count 0 2006.239.08:16:32.40#ibcon#read 3, iclass 15, count 0 2006.239.08:16:32.40#ibcon#about to read 4, iclass 15, count 0 2006.239.08:16:32.40#ibcon#read 4, iclass 15, count 0 2006.239.08:16:32.40#ibcon#about to read 5, iclass 15, count 0 2006.239.08:16:32.40#ibcon#read 5, iclass 15, count 0 2006.239.08:16:32.40#ibcon#about to read 6, iclass 15, count 0 2006.239.08:16:32.40#ibcon#read 6, iclass 15, count 0 2006.239.08:16:32.40#ibcon#end of sib2, iclass 15, count 0 2006.239.08:16:32.40#ibcon#*after write, iclass 15, count 0 2006.239.08:16:32.40#ibcon#*before return 0, iclass 15, count 0 2006.239.08:16:32.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:32.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.239.08:16:32.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:16:32.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:16:32.40$vc4f8/vb=6,4 2006.239.08:16:32.40#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.239.08:16:32.40#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.239.08:16:32.40#ibcon#ireg 11 cls_cnt 2 2006.239.08:16:32.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:32.46#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:32.46#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:32.46#ibcon#enter wrdev, iclass 17, count 2 2006.239.08:16:32.46#ibcon#first serial, iclass 17, count 2 2006.239.08:16:32.46#ibcon#enter sib2, iclass 17, count 2 2006.239.08:16:32.46#ibcon#flushed, iclass 17, count 2 2006.239.08:16:32.46#ibcon#about to write, iclass 17, count 2 2006.239.08:16:32.46#ibcon#wrote, iclass 17, count 2 2006.239.08:16:32.46#ibcon#about to read 3, iclass 17, count 2 2006.239.08:16:32.48#ibcon#read 3, iclass 17, count 2 2006.239.08:16:32.48#ibcon#about to read 4, iclass 17, count 2 2006.239.08:16:32.48#ibcon#read 4, iclass 17, count 2 2006.239.08:16:32.48#ibcon#about to read 5, iclass 17, count 2 2006.239.08:16:32.48#ibcon#read 5, iclass 17, count 2 2006.239.08:16:32.48#ibcon#about to read 6, iclass 17, count 2 2006.239.08:16:32.48#ibcon#read 6, iclass 17, count 2 2006.239.08:16:32.48#ibcon#end of sib2, iclass 17, count 2 2006.239.08:16:32.48#ibcon#*mode == 0, iclass 17, count 2 2006.239.08:16:32.48#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.239.08:16:32.48#ibcon#[27=AT06-04\r\n] 2006.239.08:16:32.48#ibcon#*before write, iclass 17, count 2 2006.239.08:16:32.48#ibcon#enter sib2, iclass 17, count 2 2006.239.08:16:32.48#ibcon#flushed, iclass 17, count 2 2006.239.08:16:32.48#ibcon#about to write, iclass 17, count 2 2006.239.08:16:32.48#ibcon#wrote, iclass 17, count 2 2006.239.08:16:32.48#ibcon#about to read 3, iclass 17, count 2 2006.239.08:16:32.51#ibcon#read 3, iclass 17, count 2 2006.239.08:16:32.51#ibcon#about to read 4, iclass 17, count 2 2006.239.08:16:32.51#ibcon#read 4, iclass 17, count 2 2006.239.08:16:32.51#ibcon#about to read 5, iclass 17, count 2 2006.239.08:16:32.51#ibcon#read 5, iclass 17, count 2 2006.239.08:16:32.51#ibcon#about to read 6, iclass 17, count 2 2006.239.08:16:32.51#ibcon#read 6, iclass 17, count 2 2006.239.08:16:32.51#ibcon#end of sib2, iclass 17, count 2 2006.239.08:16:32.51#ibcon#*after write, iclass 17, count 2 2006.239.08:16:32.51#ibcon#*before return 0, iclass 17, count 2 2006.239.08:16:32.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:32.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.239.08:16:32.51#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.239.08:16:32.51#ibcon#ireg 7 cls_cnt 0 2006.239.08:16:32.51#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:32.63#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:32.63#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:32.63#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:16:32.63#ibcon#first serial, iclass 17, count 0 2006.239.08:16:32.63#ibcon#enter sib2, iclass 17, count 0 2006.239.08:16:32.63#ibcon#flushed, iclass 17, count 0 2006.239.08:16:32.63#ibcon#about to write, iclass 17, count 0 2006.239.08:16:32.63#ibcon#wrote, iclass 17, count 0 2006.239.08:16:32.63#ibcon#about to read 3, iclass 17, count 0 2006.239.08:16:32.65#ibcon#read 3, iclass 17, count 0 2006.239.08:16:32.65#ibcon#about to read 4, iclass 17, count 0 2006.239.08:16:32.65#ibcon#read 4, iclass 17, count 0 2006.239.08:16:32.65#ibcon#about to read 5, iclass 17, count 0 2006.239.08:16:32.65#ibcon#read 5, iclass 17, count 0 2006.239.08:16:32.65#ibcon#about to read 6, iclass 17, count 0 2006.239.08:16:32.65#ibcon#read 6, iclass 17, count 0 2006.239.08:16:32.65#ibcon#end of sib2, iclass 17, count 0 2006.239.08:16:32.65#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:16:32.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:16:32.65#ibcon#[27=USB\r\n] 2006.239.08:16:32.65#ibcon#*before write, iclass 17, count 0 2006.239.08:16:32.65#ibcon#enter sib2, iclass 17, count 0 2006.239.08:16:32.65#ibcon#flushed, iclass 17, count 0 2006.239.08:16:32.65#ibcon#about to write, iclass 17, count 0 2006.239.08:16:32.65#ibcon#wrote, iclass 17, count 0 2006.239.08:16:32.65#ibcon#about to read 3, iclass 17, count 0 2006.239.08:16:32.68#ibcon#read 3, iclass 17, count 0 2006.239.08:16:32.68#ibcon#about to read 4, iclass 17, count 0 2006.239.08:16:32.68#ibcon#read 4, iclass 17, count 0 2006.239.08:16:32.68#ibcon#about to read 5, iclass 17, count 0 2006.239.08:16:32.68#ibcon#read 5, iclass 17, count 0 2006.239.08:16:32.68#ibcon#about to read 6, iclass 17, count 0 2006.239.08:16:32.68#ibcon#read 6, iclass 17, count 0 2006.239.08:16:32.68#ibcon#end of sib2, iclass 17, count 0 2006.239.08:16:32.68#ibcon#*after write, iclass 17, count 0 2006.239.08:16:32.68#ibcon#*before return 0, iclass 17, count 0 2006.239.08:16:32.68#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:32.68#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.239.08:16:32.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:16:32.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:16:32.68$vc4f8/vabw=wide 2006.239.08:16:32.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.239.08:16:32.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.239.08:16:32.68#ibcon#ireg 8 cls_cnt 0 2006.239.08:16:32.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:32.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:32.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:32.68#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:16:32.68#ibcon#first serial, iclass 19, count 0 2006.239.08:16:32.68#ibcon#enter sib2, iclass 19, count 0 2006.239.08:16:32.68#ibcon#flushed, iclass 19, count 0 2006.239.08:16:32.68#ibcon#about to write, iclass 19, count 0 2006.239.08:16:32.68#ibcon#wrote, iclass 19, count 0 2006.239.08:16:32.68#ibcon#about to read 3, iclass 19, count 0 2006.239.08:16:32.70#ibcon#read 3, iclass 19, count 0 2006.239.08:16:32.70#ibcon#about to read 4, iclass 19, count 0 2006.239.08:16:32.70#ibcon#read 4, iclass 19, count 0 2006.239.08:16:32.70#ibcon#about to read 5, iclass 19, count 0 2006.239.08:16:32.70#ibcon#read 5, iclass 19, count 0 2006.239.08:16:32.70#ibcon#about to read 6, iclass 19, count 0 2006.239.08:16:32.70#ibcon#read 6, iclass 19, count 0 2006.239.08:16:32.70#ibcon#end of sib2, iclass 19, count 0 2006.239.08:16:32.70#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:16:32.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:16:32.70#ibcon#[25=BW32\r\n] 2006.239.08:16:32.70#ibcon#*before write, iclass 19, count 0 2006.239.08:16:32.70#ibcon#enter sib2, iclass 19, count 0 2006.239.08:16:32.70#ibcon#flushed, iclass 19, count 0 2006.239.08:16:32.70#ibcon#about to write, iclass 19, count 0 2006.239.08:16:32.70#ibcon#wrote, iclass 19, count 0 2006.239.08:16:32.70#ibcon#about to read 3, iclass 19, count 0 2006.239.08:16:32.73#ibcon#read 3, iclass 19, count 0 2006.239.08:16:32.73#ibcon#about to read 4, iclass 19, count 0 2006.239.08:16:32.73#ibcon#read 4, iclass 19, count 0 2006.239.08:16:32.73#ibcon#about to read 5, iclass 19, count 0 2006.239.08:16:32.73#ibcon#read 5, iclass 19, count 0 2006.239.08:16:32.73#ibcon#about to read 6, iclass 19, count 0 2006.239.08:16:32.73#ibcon#read 6, iclass 19, count 0 2006.239.08:16:32.73#ibcon#end of sib2, iclass 19, count 0 2006.239.08:16:32.73#ibcon#*after write, iclass 19, count 0 2006.239.08:16:32.73#ibcon#*before return 0, iclass 19, count 0 2006.239.08:16:32.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:32.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.239.08:16:32.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:16:32.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:16:32.73$vc4f8/vbbw=wide 2006.239.08:16:32.73#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:16:32.73#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:16:32.73#ibcon#ireg 8 cls_cnt 0 2006.239.08:16:32.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:16:32.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:16:32.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:16:32.80#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:16:32.80#ibcon#first serial, iclass 21, count 0 2006.239.08:16:32.80#ibcon#enter sib2, iclass 21, count 0 2006.239.08:16:32.80#ibcon#flushed, iclass 21, count 0 2006.239.08:16:32.80#ibcon#about to write, iclass 21, count 0 2006.239.08:16:32.80#ibcon#wrote, iclass 21, count 0 2006.239.08:16:32.80#ibcon#about to read 3, iclass 21, count 0 2006.239.08:16:32.82#ibcon#read 3, iclass 21, count 0 2006.239.08:16:32.82#ibcon#about to read 4, iclass 21, count 0 2006.239.08:16:32.82#ibcon#read 4, iclass 21, count 0 2006.239.08:16:32.82#ibcon#about to read 5, iclass 21, count 0 2006.239.08:16:32.82#ibcon#read 5, iclass 21, count 0 2006.239.08:16:32.82#ibcon#about to read 6, iclass 21, count 0 2006.239.08:16:32.82#ibcon#read 6, iclass 21, count 0 2006.239.08:16:32.82#ibcon#end of sib2, iclass 21, count 0 2006.239.08:16:32.82#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:16:32.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:16:32.82#ibcon#[27=BW32\r\n] 2006.239.08:16:32.82#ibcon#*before write, iclass 21, count 0 2006.239.08:16:32.82#ibcon#enter sib2, iclass 21, count 0 2006.239.08:16:32.82#ibcon#flushed, iclass 21, count 0 2006.239.08:16:32.82#ibcon#about to write, iclass 21, count 0 2006.239.08:16:32.82#ibcon#wrote, iclass 21, count 0 2006.239.08:16:32.82#ibcon#about to read 3, iclass 21, count 0 2006.239.08:16:32.86#ibcon#read 3, iclass 21, count 0 2006.239.08:16:32.86#ibcon#about to read 4, iclass 21, count 0 2006.239.08:16:32.86#ibcon#read 4, iclass 21, count 0 2006.239.08:16:32.86#ibcon#about to read 5, iclass 21, count 0 2006.239.08:16:32.86#ibcon#read 5, iclass 21, count 0 2006.239.08:16:32.86#ibcon#about to read 6, iclass 21, count 0 2006.239.08:16:32.86#ibcon#read 6, iclass 21, count 0 2006.239.08:16:32.86#ibcon#end of sib2, iclass 21, count 0 2006.239.08:16:32.86#ibcon#*after write, iclass 21, count 0 2006.239.08:16:32.86#ibcon#*before return 0, iclass 21, count 0 2006.239.08:16:32.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:16:32.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:16:32.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:16:32.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:16:32.86$4f8m12a/ifd4f 2006.239.08:16:32.86$ifd4f/lo= 2006.239.08:16:32.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:16:32.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:16:32.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:16:32.86$ifd4f/patch= 2006.239.08:16:32.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:16:32.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:16:32.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:16:32.86$4f8m12a/"form=m,16.000,1:2 2006.239.08:16:32.86$4f8m12a/"tpicd 2006.239.08:16:32.86$4f8m12a/echo=off 2006.239.08:16:32.86$4f8m12a/xlog=off 2006.239.08:16:32.86:!2006.239.08:17:00 2006.239.08:16:42.14#trakl#Source acquired 2006.239.08:16:44.14#flagr#flagr/antenna,acquired 2006.239.08:17:00.01:preob 2006.239.08:17:01.14/onsource/TRACKING 2006.239.08:17:01.14:!2006.239.08:17:10 2006.239.08:17:10.00:data_valid=on 2006.239.08:17:10.00:midob 2006.239.08:17:10.14/onsource/TRACKING 2006.239.08:17:10.14/wx/25.01,1011.5,80 2006.239.08:17:10.29/cable/+6.4135E-03 2006.239.08:17:11.38/va/01,08,usb,yes,31,33 2006.239.08:17:11.38/va/02,07,usb,yes,31,33 2006.239.08:17:11.38/va/03,07,usb,yes,29,29 2006.239.08:17:11.38/va/04,07,usb,yes,32,35 2006.239.08:17:11.38/va/05,08,usb,yes,30,32 2006.239.08:17:11.38/va/06,07,usb,yes,32,32 2006.239.08:17:11.38/va/07,07,usb,yes,32,32 2006.239.08:17:11.38/va/08,07,usb,yes,35,35 2006.239.08:17:11.61/valo/01,532.99,yes,locked 2006.239.08:17:11.61/valo/02,572.99,yes,locked 2006.239.08:17:11.61/valo/03,672.99,yes,locked 2006.239.08:17:11.61/valo/04,832.99,yes,locked 2006.239.08:17:11.61/valo/05,652.99,yes,locked 2006.239.08:17:11.61/valo/06,772.99,yes,locked 2006.239.08:17:11.61/valo/07,832.99,yes,locked 2006.239.08:17:11.61/valo/08,852.99,yes,locked 2006.239.08:17:12.70/vb/01,04,usb,yes,32,30 2006.239.08:17:12.70/vb/02,04,usb,yes,38,35 2006.239.08:17:12.70/vb/03,04,usb,yes,33,38 2006.239.08:17:12.70/vb/04,04,usb,yes,30,30 2006.239.08:17:12.70/vb/05,04,usb,yes,28,32 2006.239.08:17:12.70/vb/06,04,usb,yes,29,32 2006.239.08:17:12.70/vb/07,04,usb,yes,31,31 2006.239.08:17:12.70/vb/08,04,usb,yes,29,32 2006.239.08:17:12.93/vblo/01,632.99,yes,locked 2006.239.08:17:12.93/vblo/02,640.99,yes,locked 2006.239.08:17:12.93/vblo/03,656.99,yes,locked 2006.239.08:17:12.93/vblo/04,712.99,yes,locked 2006.239.08:17:12.93/vblo/05,744.99,yes,locked 2006.239.08:17:12.93/vblo/06,752.99,yes,locked 2006.239.08:17:12.93/vblo/07,734.99,yes,locked 2006.239.08:17:12.93/vblo/08,744.99,yes,locked 2006.239.08:17:13.08/vabw/8 2006.239.08:17:13.23/vbbw/8 2006.239.08:17:13.32/xfe/off,on,13.7 2006.239.08:17:13.69/ifatt/23,28,28,28 2006.239.08:17:14.07/fmout-gps/S +4.43E-07 2006.239.08:17:14.11:!2006.239.08:18:10 2006.239.08:18:10.00:data_valid=off 2006.239.08:18:10.01:postob 2006.239.08:18:10.06/cable/+6.4152E-03 2006.239.08:18:10.07/wx/25.00,1011.5,80 2006.239.08:18:11.07/fmout-gps/S +4.42E-07 2006.239.08:18:11.08:scan_name=239-0820,k06239,60 2006.239.08:18:11.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.239.08:18:12.14#flagr#flagr/antenna,new-source 2006.239.08:18:12.15:checkk5 2006.239.08:18:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:18:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:18:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:18:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:18:14.02/chk_obsdata//k5ts1/T2390817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:18:14.40/chk_obsdata//k5ts2/T2390817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:18:14.77/chk_obsdata//k5ts3/T2390817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:18:15.14/chk_obsdata//k5ts4/T2390817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:18:15.84/k5log//k5ts1_log_newline 2006.239.08:18:16.54/k5log//k5ts2_log_newline 2006.239.08:18:17.22/k5log//k5ts3_log_newline 2006.239.08:18:17.91/k5log//k5ts4_log_newline 2006.239.08:18:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:18:17.94:4f8m12a=3 2006.239.08:18:17.94$4f8m12a/echo=on 2006.239.08:18:17.94$4f8m12a/pcalon 2006.239.08:18:17.94$pcalon/"no phase cal control is implemented here 2006.239.08:18:17.94$4f8m12a/"tpicd=stop 2006.239.08:18:17.94$4f8m12a/vc4f8 2006.239.08:18:17.94$vc4f8/valo=1,532.99 2006.239.08:18:17.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:18:17.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:18:17.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:17.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:17.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:17.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:17.94#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:18:17.94#ibcon#first serial, iclass 28, count 0 2006.239.08:18:17.94#ibcon#enter sib2, iclass 28, count 0 2006.239.08:18:17.94#ibcon#flushed, iclass 28, count 0 2006.239.08:18:17.94#ibcon#about to write, iclass 28, count 0 2006.239.08:18:17.94#ibcon#wrote, iclass 28, count 0 2006.239.08:18:17.94#ibcon#about to read 3, iclass 28, count 0 2006.239.08:18:17.95#ibcon#read 3, iclass 28, count 0 2006.239.08:18:17.95#ibcon#about to read 4, iclass 28, count 0 2006.239.08:18:17.95#ibcon#read 4, iclass 28, count 0 2006.239.08:18:17.95#ibcon#about to read 5, iclass 28, count 0 2006.239.08:18:17.95#ibcon#read 5, iclass 28, count 0 2006.239.08:18:17.95#ibcon#about to read 6, iclass 28, count 0 2006.239.08:18:17.95#ibcon#read 6, iclass 28, count 0 2006.239.08:18:17.95#ibcon#end of sib2, iclass 28, count 0 2006.239.08:18:17.95#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:18:17.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:18:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:18:17.95#ibcon#*before write, iclass 28, count 0 2006.239.08:18:17.95#ibcon#enter sib2, iclass 28, count 0 2006.239.08:18:17.95#ibcon#flushed, iclass 28, count 0 2006.239.08:18:17.95#ibcon#about to write, iclass 28, count 0 2006.239.08:18:17.95#ibcon#wrote, iclass 28, count 0 2006.239.08:18:17.95#ibcon#about to read 3, iclass 28, count 0 2006.239.08:18:18.00#ibcon#read 3, iclass 28, count 0 2006.239.08:18:18.00#ibcon#about to read 4, iclass 28, count 0 2006.239.08:18:18.00#ibcon#read 4, iclass 28, count 0 2006.239.08:18:18.00#ibcon#about to read 5, iclass 28, count 0 2006.239.08:18:18.00#ibcon#read 5, iclass 28, count 0 2006.239.08:18:18.00#ibcon#about to read 6, iclass 28, count 0 2006.239.08:18:18.00#ibcon#read 6, iclass 28, count 0 2006.239.08:18:18.00#ibcon#end of sib2, iclass 28, count 0 2006.239.08:18:18.00#ibcon#*after write, iclass 28, count 0 2006.239.08:18:18.00#ibcon#*before return 0, iclass 28, count 0 2006.239.08:18:18.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:18.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:18.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:18:18.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:18:18.00$vc4f8/va=1,8 2006.239.08:18:18.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.08:18:18.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.08:18:18.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:18.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:18.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:18.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:18.00#ibcon#enter wrdev, iclass 30, count 2 2006.239.08:18:18.00#ibcon#first serial, iclass 30, count 2 2006.239.08:18:18.00#ibcon#enter sib2, iclass 30, count 2 2006.239.08:18:18.00#ibcon#flushed, iclass 30, count 2 2006.239.08:18:18.00#ibcon#about to write, iclass 30, count 2 2006.239.08:18:18.00#ibcon#wrote, iclass 30, count 2 2006.239.08:18:18.00#ibcon#about to read 3, iclass 30, count 2 2006.239.08:18:18.02#ibcon#read 3, iclass 30, count 2 2006.239.08:18:18.02#ibcon#about to read 4, iclass 30, count 2 2006.239.08:18:18.02#ibcon#read 4, iclass 30, count 2 2006.239.08:18:18.02#ibcon#about to read 5, iclass 30, count 2 2006.239.08:18:18.02#ibcon#read 5, iclass 30, count 2 2006.239.08:18:18.02#ibcon#about to read 6, iclass 30, count 2 2006.239.08:18:18.02#ibcon#read 6, iclass 30, count 2 2006.239.08:18:18.02#ibcon#end of sib2, iclass 30, count 2 2006.239.08:18:18.02#ibcon#*mode == 0, iclass 30, count 2 2006.239.08:18:18.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.08:18:18.02#ibcon#[25=AT01-08\r\n] 2006.239.08:18:18.02#ibcon#*before write, iclass 30, count 2 2006.239.08:18:18.02#ibcon#enter sib2, iclass 30, count 2 2006.239.08:18:18.02#ibcon#flushed, iclass 30, count 2 2006.239.08:18:18.02#ibcon#about to write, iclass 30, count 2 2006.239.08:18:18.02#ibcon#wrote, iclass 30, count 2 2006.239.08:18:18.02#ibcon#about to read 3, iclass 30, count 2 2006.239.08:18:18.05#ibcon#read 3, iclass 30, count 2 2006.239.08:18:18.05#ibcon#about to read 4, iclass 30, count 2 2006.239.08:18:18.05#ibcon#read 4, iclass 30, count 2 2006.239.08:18:18.05#ibcon#about to read 5, iclass 30, count 2 2006.239.08:18:18.05#ibcon#read 5, iclass 30, count 2 2006.239.08:18:18.05#ibcon#about to read 6, iclass 30, count 2 2006.239.08:18:18.05#ibcon#read 6, iclass 30, count 2 2006.239.08:18:18.05#ibcon#end of sib2, iclass 30, count 2 2006.239.08:18:18.05#ibcon#*after write, iclass 30, count 2 2006.239.08:18:18.05#ibcon#*before return 0, iclass 30, count 2 2006.239.08:18:18.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:18.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:18.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.08:18:18.05#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:18.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:18.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:18.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:18.17#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:18:18.17#ibcon#first serial, iclass 30, count 0 2006.239.08:18:18.17#ibcon#enter sib2, iclass 30, count 0 2006.239.08:18:18.17#ibcon#flushed, iclass 30, count 0 2006.239.08:18:18.17#ibcon#about to write, iclass 30, count 0 2006.239.08:18:18.17#ibcon#wrote, iclass 30, count 0 2006.239.08:18:18.17#ibcon#about to read 3, iclass 30, count 0 2006.239.08:18:18.19#ibcon#read 3, iclass 30, count 0 2006.239.08:18:18.19#ibcon#about to read 4, iclass 30, count 0 2006.239.08:18:18.19#ibcon#read 4, iclass 30, count 0 2006.239.08:18:18.19#ibcon#about to read 5, iclass 30, count 0 2006.239.08:18:18.19#ibcon#read 5, iclass 30, count 0 2006.239.08:18:18.19#ibcon#about to read 6, iclass 30, count 0 2006.239.08:18:18.19#ibcon#read 6, iclass 30, count 0 2006.239.08:18:18.19#ibcon#end of sib2, iclass 30, count 0 2006.239.08:18:18.19#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:18:18.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:18:18.19#ibcon#[25=USB\r\n] 2006.239.08:18:18.19#ibcon#*before write, iclass 30, count 0 2006.239.08:18:18.19#ibcon#enter sib2, iclass 30, count 0 2006.239.08:18:18.19#ibcon#flushed, iclass 30, count 0 2006.239.08:18:18.19#ibcon#about to write, iclass 30, count 0 2006.239.08:18:18.19#ibcon#wrote, iclass 30, count 0 2006.239.08:18:18.19#ibcon#about to read 3, iclass 30, count 0 2006.239.08:18:18.22#ibcon#read 3, iclass 30, count 0 2006.239.08:18:18.22#ibcon#about to read 4, iclass 30, count 0 2006.239.08:18:18.22#ibcon#read 4, iclass 30, count 0 2006.239.08:18:18.22#ibcon#about to read 5, iclass 30, count 0 2006.239.08:18:18.22#ibcon#read 5, iclass 30, count 0 2006.239.08:18:18.22#ibcon#about to read 6, iclass 30, count 0 2006.239.08:18:18.22#ibcon#read 6, iclass 30, count 0 2006.239.08:18:18.22#ibcon#end of sib2, iclass 30, count 0 2006.239.08:18:18.22#ibcon#*after write, iclass 30, count 0 2006.239.08:18:18.22#ibcon#*before return 0, iclass 30, count 0 2006.239.08:18:18.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:18.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:18.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:18:18.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:18:18.22$vc4f8/valo=2,572.99 2006.239.08:18:18.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.08:18:18.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.08:18:18.22#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:18.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:18.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:18.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:18.22#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:18:18.22#ibcon#first serial, iclass 32, count 0 2006.239.08:18:18.22#ibcon#enter sib2, iclass 32, count 0 2006.239.08:18:18.22#ibcon#flushed, iclass 32, count 0 2006.239.08:18:18.22#ibcon#about to write, iclass 32, count 0 2006.239.08:18:18.22#ibcon#wrote, iclass 32, count 0 2006.239.08:18:18.22#ibcon#about to read 3, iclass 32, count 0 2006.239.08:18:18.24#ibcon#read 3, iclass 32, count 0 2006.239.08:18:18.24#ibcon#about to read 4, iclass 32, count 0 2006.239.08:18:18.24#ibcon#read 4, iclass 32, count 0 2006.239.08:18:18.24#ibcon#about to read 5, iclass 32, count 0 2006.239.08:18:18.24#ibcon#read 5, iclass 32, count 0 2006.239.08:18:18.24#ibcon#about to read 6, iclass 32, count 0 2006.239.08:18:18.24#ibcon#read 6, iclass 32, count 0 2006.239.08:18:18.24#ibcon#end of sib2, iclass 32, count 0 2006.239.08:18:18.24#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:18:18.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:18:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:18:18.24#ibcon#*before write, iclass 32, count 0 2006.239.08:18:18.24#ibcon#enter sib2, iclass 32, count 0 2006.239.08:18:18.24#ibcon#flushed, iclass 32, count 0 2006.239.08:18:18.24#ibcon#about to write, iclass 32, count 0 2006.239.08:18:18.24#ibcon#wrote, iclass 32, count 0 2006.239.08:18:18.24#ibcon#about to read 3, iclass 32, count 0 2006.239.08:18:18.28#ibcon#read 3, iclass 32, count 0 2006.239.08:18:18.28#ibcon#about to read 4, iclass 32, count 0 2006.239.08:18:18.28#ibcon#read 4, iclass 32, count 0 2006.239.08:18:18.28#ibcon#about to read 5, iclass 32, count 0 2006.239.08:18:18.28#ibcon#read 5, iclass 32, count 0 2006.239.08:18:18.28#ibcon#about to read 6, iclass 32, count 0 2006.239.08:18:18.28#ibcon#read 6, iclass 32, count 0 2006.239.08:18:18.28#ibcon#end of sib2, iclass 32, count 0 2006.239.08:18:18.28#ibcon#*after write, iclass 32, count 0 2006.239.08:18:18.28#ibcon#*before return 0, iclass 32, count 0 2006.239.08:18:18.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:18.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:18.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:18:18.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:18:18.28$vc4f8/va=2,7 2006.239.08:18:18.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.08:18:18.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.08:18:18.28#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:18.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:18.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:18.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:18.34#ibcon#enter wrdev, iclass 34, count 2 2006.239.08:18:18.34#ibcon#first serial, iclass 34, count 2 2006.239.08:18:18.34#ibcon#enter sib2, iclass 34, count 2 2006.239.08:18:18.34#ibcon#flushed, iclass 34, count 2 2006.239.08:18:18.34#ibcon#about to write, iclass 34, count 2 2006.239.08:18:18.34#ibcon#wrote, iclass 34, count 2 2006.239.08:18:18.34#ibcon#about to read 3, iclass 34, count 2 2006.239.08:18:18.36#ibcon#read 3, iclass 34, count 2 2006.239.08:18:18.36#ibcon#about to read 4, iclass 34, count 2 2006.239.08:18:18.36#ibcon#read 4, iclass 34, count 2 2006.239.08:18:18.36#ibcon#about to read 5, iclass 34, count 2 2006.239.08:18:18.36#ibcon#read 5, iclass 34, count 2 2006.239.08:18:18.36#ibcon#about to read 6, iclass 34, count 2 2006.239.08:18:18.36#ibcon#read 6, iclass 34, count 2 2006.239.08:18:18.36#ibcon#end of sib2, iclass 34, count 2 2006.239.08:18:18.36#ibcon#*mode == 0, iclass 34, count 2 2006.239.08:18:18.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.08:18:18.36#ibcon#[25=AT02-07\r\n] 2006.239.08:18:18.36#ibcon#*before write, iclass 34, count 2 2006.239.08:18:18.36#ibcon#enter sib2, iclass 34, count 2 2006.239.08:18:18.36#ibcon#flushed, iclass 34, count 2 2006.239.08:18:18.36#ibcon#about to write, iclass 34, count 2 2006.239.08:18:18.36#ibcon#wrote, iclass 34, count 2 2006.239.08:18:18.36#ibcon#about to read 3, iclass 34, count 2 2006.239.08:18:18.40#ibcon#read 3, iclass 34, count 2 2006.239.08:18:18.40#ibcon#about to read 4, iclass 34, count 2 2006.239.08:18:18.40#ibcon#read 4, iclass 34, count 2 2006.239.08:18:18.40#ibcon#about to read 5, iclass 34, count 2 2006.239.08:18:18.40#ibcon#read 5, iclass 34, count 2 2006.239.08:18:18.40#ibcon#about to read 6, iclass 34, count 2 2006.239.08:18:18.40#ibcon#read 6, iclass 34, count 2 2006.239.08:18:18.40#ibcon#end of sib2, iclass 34, count 2 2006.239.08:18:18.40#ibcon#*after write, iclass 34, count 2 2006.239.08:18:18.40#ibcon#*before return 0, iclass 34, count 2 2006.239.08:18:18.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:18.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:18.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.08:18:18.40#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:18.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:18.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:18.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:18.51#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:18:18.51#ibcon#first serial, iclass 34, count 0 2006.239.08:18:18.51#ibcon#enter sib2, iclass 34, count 0 2006.239.08:18:18.51#ibcon#flushed, iclass 34, count 0 2006.239.08:18:18.51#ibcon#about to write, iclass 34, count 0 2006.239.08:18:18.51#ibcon#wrote, iclass 34, count 0 2006.239.08:18:18.51#ibcon#about to read 3, iclass 34, count 0 2006.239.08:18:18.54#ibcon#read 3, iclass 34, count 0 2006.239.08:18:18.54#ibcon#about to read 4, iclass 34, count 0 2006.239.08:18:18.54#ibcon#read 4, iclass 34, count 0 2006.239.08:18:18.54#ibcon#about to read 5, iclass 34, count 0 2006.239.08:18:18.54#ibcon#read 5, iclass 34, count 0 2006.239.08:18:18.54#ibcon#about to read 6, iclass 34, count 0 2006.239.08:18:18.54#ibcon#read 6, iclass 34, count 0 2006.239.08:18:18.54#ibcon#end of sib2, iclass 34, count 0 2006.239.08:18:18.54#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:18:18.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:18:18.54#ibcon#[25=USB\r\n] 2006.239.08:18:18.54#ibcon#*before write, iclass 34, count 0 2006.239.08:18:18.54#ibcon#enter sib2, iclass 34, count 0 2006.239.08:18:18.54#ibcon#flushed, iclass 34, count 0 2006.239.08:18:18.54#ibcon#about to write, iclass 34, count 0 2006.239.08:18:18.54#ibcon#wrote, iclass 34, count 0 2006.239.08:18:18.54#ibcon#about to read 3, iclass 34, count 0 2006.239.08:18:18.56#ibcon#read 3, iclass 34, count 0 2006.239.08:18:18.56#ibcon#about to read 4, iclass 34, count 0 2006.239.08:18:18.56#ibcon#read 4, iclass 34, count 0 2006.239.08:18:18.56#ibcon#about to read 5, iclass 34, count 0 2006.239.08:18:18.56#ibcon#read 5, iclass 34, count 0 2006.239.08:18:18.56#ibcon#about to read 6, iclass 34, count 0 2006.239.08:18:18.56#ibcon#read 6, iclass 34, count 0 2006.239.08:18:18.56#ibcon#end of sib2, iclass 34, count 0 2006.239.08:18:18.56#ibcon#*after write, iclass 34, count 0 2006.239.08:18:18.56#ibcon#*before return 0, iclass 34, count 0 2006.239.08:18:18.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:18.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:18.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:18:18.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:18:18.56$vc4f8/valo=3,672.99 2006.239.08:18:18.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.08:18:18.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.08:18:18.56#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:18.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:18.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:18.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:18.56#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:18:18.56#ibcon#first serial, iclass 36, count 0 2006.239.08:18:18.56#ibcon#enter sib2, iclass 36, count 0 2006.239.08:18:18.56#ibcon#flushed, iclass 36, count 0 2006.239.08:18:18.56#ibcon#about to write, iclass 36, count 0 2006.239.08:18:18.56#ibcon#wrote, iclass 36, count 0 2006.239.08:18:18.56#ibcon#about to read 3, iclass 36, count 0 2006.239.08:18:18.58#ibcon#read 3, iclass 36, count 0 2006.239.08:18:18.58#ibcon#about to read 4, iclass 36, count 0 2006.239.08:18:18.58#ibcon#read 4, iclass 36, count 0 2006.239.08:18:18.58#ibcon#about to read 5, iclass 36, count 0 2006.239.08:18:18.58#ibcon#read 5, iclass 36, count 0 2006.239.08:18:18.58#ibcon#about to read 6, iclass 36, count 0 2006.239.08:18:18.58#ibcon#read 6, iclass 36, count 0 2006.239.08:18:18.58#ibcon#end of sib2, iclass 36, count 0 2006.239.08:18:18.58#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:18:18.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:18:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:18:18.58#ibcon#*before write, iclass 36, count 0 2006.239.08:18:18.58#ibcon#enter sib2, iclass 36, count 0 2006.239.08:18:18.58#ibcon#flushed, iclass 36, count 0 2006.239.08:18:18.58#ibcon#about to write, iclass 36, count 0 2006.239.08:18:18.58#ibcon#wrote, iclass 36, count 0 2006.239.08:18:18.58#ibcon#about to read 3, iclass 36, count 0 2006.239.08:18:18.62#ibcon#read 3, iclass 36, count 0 2006.239.08:18:18.62#ibcon#about to read 4, iclass 36, count 0 2006.239.08:18:18.62#ibcon#read 4, iclass 36, count 0 2006.239.08:18:18.62#ibcon#about to read 5, iclass 36, count 0 2006.239.08:18:18.62#ibcon#read 5, iclass 36, count 0 2006.239.08:18:18.62#ibcon#about to read 6, iclass 36, count 0 2006.239.08:18:18.62#ibcon#read 6, iclass 36, count 0 2006.239.08:18:18.62#ibcon#end of sib2, iclass 36, count 0 2006.239.08:18:18.62#ibcon#*after write, iclass 36, count 0 2006.239.08:18:18.62#ibcon#*before return 0, iclass 36, count 0 2006.239.08:18:18.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:18.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:18.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:18:18.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:18:18.62$vc4f8/va=3,7 2006.239.08:18:18.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.08:18:18.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.08:18:18.62#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:18.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:18.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:18.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:18.68#ibcon#enter wrdev, iclass 38, count 2 2006.239.08:18:18.68#ibcon#first serial, iclass 38, count 2 2006.239.08:18:18.68#ibcon#enter sib2, iclass 38, count 2 2006.239.08:18:18.68#ibcon#flushed, iclass 38, count 2 2006.239.08:18:18.68#ibcon#about to write, iclass 38, count 2 2006.239.08:18:18.68#ibcon#wrote, iclass 38, count 2 2006.239.08:18:18.68#ibcon#about to read 3, iclass 38, count 2 2006.239.08:18:18.70#ibcon#read 3, iclass 38, count 2 2006.239.08:18:18.70#ibcon#about to read 4, iclass 38, count 2 2006.239.08:18:18.70#ibcon#read 4, iclass 38, count 2 2006.239.08:18:18.70#ibcon#about to read 5, iclass 38, count 2 2006.239.08:18:18.70#ibcon#read 5, iclass 38, count 2 2006.239.08:18:18.70#ibcon#about to read 6, iclass 38, count 2 2006.239.08:18:18.70#ibcon#read 6, iclass 38, count 2 2006.239.08:18:18.70#ibcon#end of sib2, iclass 38, count 2 2006.239.08:18:18.70#ibcon#*mode == 0, iclass 38, count 2 2006.239.08:18:18.70#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.08:18:18.70#ibcon#[25=AT03-07\r\n] 2006.239.08:18:18.70#ibcon#*before write, iclass 38, count 2 2006.239.08:18:18.70#ibcon#enter sib2, iclass 38, count 2 2006.239.08:18:18.70#ibcon#flushed, iclass 38, count 2 2006.239.08:18:18.70#ibcon#about to write, iclass 38, count 2 2006.239.08:18:18.70#ibcon#wrote, iclass 38, count 2 2006.239.08:18:18.70#ibcon#about to read 3, iclass 38, count 2 2006.239.08:18:18.73#ibcon#read 3, iclass 38, count 2 2006.239.08:18:18.73#ibcon#about to read 4, iclass 38, count 2 2006.239.08:18:18.73#ibcon#read 4, iclass 38, count 2 2006.239.08:18:18.73#ibcon#about to read 5, iclass 38, count 2 2006.239.08:18:18.73#ibcon#read 5, iclass 38, count 2 2006.239.08:18:18.73#ibcon#about to read 6, iclass 38, count 2 2006.239.08:18:18.73#ibcon#read 6, iclass 38, count 2 2006.239.08:18:18.73#ibcon#end of sib2, iclass 38, count 2 2006.239.08:18:18.73#ibcon#*after write, iclass 38, count 2 2006.239.08:18:18.73#ibcon#*before return 0, iclass 38, count 2 2006.239.08:18:18.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:18.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:18.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.08:18:18.73#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:18.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:18.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:18.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:18.85#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:18:18.85#ibcon#first serial, iclass 38, count 0 2006.239.08:18:18.85#ibcon#enter sib2, iclass 38, count 0 2006.239.08:18:18.85#ibcon#flushed, iclass 38, count 0 2006.239.08:18:18.85#ibcon#about to write, iclass 38, count 0 2006.239.08:18:18.85#ibcon#wrote, iclass 38, count 0 2006.239.08:18:18.85#ibcon#about to read 3, iclass 38, count 0 2006.239.08:18:18.87#ibcon#read 3, iclass 38, count 0 2006.239.08:18:18.87#ibcon#about to read 4, iclass 38, count 0 2006.239.08:18:18.87#ibcon#read 4, iclass 38, count 0 2006.239.08:18:18.87#ibcon#about to read 5, iclass 38, count 0 2006.239.08:18:18.87#ibcon#read 5, iclass 38, count 0 2006.239.08:18:18.87#ibcon#about to read 6, iclass 38, count 0 2006.239.08:18:18.87#ibcon#read 6, iclass 38, count 0 2006.239.08:18:18.87#ibcon#end of sib2, iclass 38, count 0 2006.239.08:18:18.87#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:18:18.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:18:18.87#ibcon#[25=USB\r\n] 2006.239.08:18:18.87#ibcon#*before write, iclass 38, count 0 2006.239.08:18:18.87#ibcon#enter sib2, iclass 38, count 0 2006.239.08:18:18.87#ibcon#flushed, iclass 38, count 0 2006.239.08:18:18.87#ibcon#about to write, iclass 38, count 0 2006.239.08:18:18.87#ibcon#wrote, iclass 38, count 0 2006.239.08:18:18.87#ibcon#about to read 3, iclass 38, count 0 2006.239.08:18:18.90#ibcon#read 3, iclass 38, count 0 2006.239.08:18:18.90#ibcon#about to read 4, iclass 38, count 0 2006.239.08:18:18.90#ibcon#read 4, iclass 38, count 0 2006.239.08:18:18.90#ibcon#about to read 5, iclass 38, count 0 2006.239.08:18:18.90#ibcon#read 5, iclass 38, count 0 2006.239.08:18:18.90#ibcon#about to read 6, iclass 38, count 0 2006.239.08:18:18.90#ibcon#read 6, iclass 38, count 0 2006.239.08:18:18.90#ibcon#end of sib2, iclass 38, count 0 2006.239.08:18:18.90#ibcon#*after write, iclass 38, count 0 2006.239.08:18:18.90#ibcon#*before return 0, iclass 38, count 0 2006.239.08:18:18.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:18.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:18.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:18:18.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:18:18.90$vc4f8/valo=4,832.99 2006.239.08:18:18.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.08:18:18.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.08:18:18.90#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:18.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:18.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:18.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:18.90#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:18:18.90#ibcon#first serial, iclass 40, count 0 2006.239.08:18:18.90#ibcon#enter sib2, iclass 40, count 0 2006.239.08:18:18.90#ibcon#flushed, iclass 40, count 0 2006.239.08:18:18.90#ibcon#about to write, iclass 40, count 0 2006.239.08:18:18.90#ibcon#wrote, iclass 40, count 0 2006.239.08:18:18.90#ibcon#about to read 3, iclass 40, count 0 2006.239.08:18:18.92#ibcon#read 3, iclass 40, count 0 2006.239.08:18:18.92#ibcon#about to read 4, iclass 40, count 0 2006.239.08:18:18.92#ibcon#read 4, iclass 40, count 0 2006.239.08:18:18.92#ibcon#about to read 5, iclass 40, count 0 2006.239.08:18:18.92#ibcon#read 5, iclass 40, count 0 2006.239.08:18:18.92#ibcon#about to read 6, iclass 40, count 0 2006.239.08:18:18.92#ibcon#read 6, iclass 40, count 0 2006.239.08:18:18.92#ibcon#end of sib2, iclass 40, count 0 2006.239.08:18:18.92#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:18:18.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:18:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:18:18.92#ibcon#*before write, iclass 40, count 0 2006.239.08:18:18.92#ibcon#enter sib2, iclass 40, count 0 2006.239.08:18:18.92#ibcon#flushed, iclass 40, count 0 2006.239.08:18:18.92#ibcon#about to write, iclass 40, count 0 2006.239.08:18:18.92#ibcon#wrote, iclass 40, count 0 2006.239.08:18:18.92#ibcon#about to read 3, iclass 40, count 0 2006.239.08:18:18.96#ibcon#read 3, iclass 40, count 0 2006.239.08:18:18.96#ibcon#about to read 4, iclass 40, count 0 2006.239.08:18:18.96#ibcon#read 4, iclass 40, count 0 2006.239.08:18:18.96#ibcon#about to read 5, iclass 40, count 0 2006.239.08:18:18.96#ibcon#read 5, iclass 40, count 0 2006.239.08:18:18.96#ibcon#about to read 6, iclass 40, count 0 2006.239.08:18:18.96#ibcon#read 6, iclass 40, count 0 2006.239.08:18:18.96#ibcon#end of sib2, iclass 40, count 0 2006.239.08:18:18.96#ibcon#*after write, iclass 40, count 0 2006.239.08:18:18.96#ibcon#*before return 0, iclass 40, count 0 2006.239.08:18:18.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:18.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:18.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:18:18.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:18:18.96$vc4f8/va=4,7 2006.239.08:18:18.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.08:18:18.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.08:18:18.96#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:18.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:19.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:19.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:19.02#ibcon#enter wrdev, iclass 4, count 2 2006.239.08:18:19.02#ibcon#first serial, iclass 4, count 2 2006.239.08:18:19.02#ibcon#enter sib2, iclass 4, count 2 2006.239.08:18:19.02#ibcon#flushed, iclass 4, count 2 2006.239.08:18:19.02#ibcon#about to write, iclass 4, count 2 2006.239.08:18:19.02#ibcon#wrote, iclass 4, count 2 2006.239.08:18:19.02#ibcon#about to read 3, iclass 4, count 2 2006.239.08:18:19.04#ibcon#read 3, iclass 4, count 2 2006.239.08:18:19.04#ibcon#about to read 4, iclass 4, count 2 2006.239.08:18:19.04#ibcon#read 4, iclass 4, count 2 2006.239.08:18:19.04#ibcon#about to read 5, iclass 4, count 2 2006.239.08:18:19.04#ibcon#read 5, iclass 4, count 2 2006.239.08:18:19.04#ibcon#about to read 6, iclass 4, count 2 2006.239.08:18:19.04#ibcon#read 6, iclass 4, count 2 2006.239.08:18:19.04#ibcon#end of sib2, iclass 4, count 2 2006.239.08:18:19.04#ibcon#*mode == 0, iclass 4, count 2 2006.239.08:18:19.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.08:18:19.04#ibcon#[25=AT04-07\r\n] 2006.239.08:18:19.04#ibcon#*before write, iclass 4, count 2 2006.239.08:18:19.04#ibcon#enter sib2, iclass 4, count 2 2006.239.08:18:19.04#ibcon#flushed, iclass 4, count 2 2006.239.08:18:19.04#ibcon#about to write, iclass 4, count 2 2006.239.08:18:19.04#ibcon#wrote, iclass 4, count 2 2006.239.08:18:19.04#ibcon#about to read 3, iclass 4, count 2 2006.239.08:18:19.07#ibcon#read 3, iclass 4, count 2 2006.239.08:18:19.07#ibcon#about to read 4, iclass 4, count 2 2006.239.08:18:19.07#ibcon#read 4, iclass 4, count 2 2006.239.08:18:19.07#ibcon#about to read 5, iclass 4, count 2 2006.239.08:18:19.07#ibcon#read 5, iclass 4, count 2 2006.239.08:18:19.07#ibcon#about to read 6, iclass 4, count 2 2006.239.08:18:19.07#ibcon#read 6, iclass 4, count 2 2006.239.08:18:19.07#ibcon#end of sib2, iclass 4, count 2 2006.239.08:18:19.07#ibcon#*after write, iclass 4, count 2 2006.239.08:18:19.07#ibcon#*before return 0, iclass 4, count 2 2006.239.08:18:19.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:19.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:19.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.08:18:19.07#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:19.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:19.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:19.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:19.19#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:18:19.19#ibcon#first serial, iclass 4, count 0 2006.239.08:18:19.19#ibcon#enter sib2, iclass 4, count 0 2006.239.08:18:19.19#ibcon#flushed, iclass 4, count 0 2006.239.08:18:19.19#ibcon#about to write, iclass 4, count 0 2006.239.08:18:19.19#ibcon#wrote, iclass 4, count 0 2006.239.08:18:19.19#ibcon#about to read 3, iclass 4, count 0 2006.239.08:18:19.21#ibcon#read 3, iclass 4, count 0 2006.239.08:18:19.21#ibcon#about to read 4, iclass 4, count 0 2006.239.08:18:19.21#ibcon#read 4, iclass 4, count 0 2006.239.08:18:19.21#ibcon#about to read 5, iclass 4, count 0 2006.239.08:18:19.21#ibcon#read 5, iclass 4, count 0 2006.239.08:18:19.21#ibcon#about to read 6, iclass 4, count 0 2006.239.08:18:19.21#ibcon#read 6, iclass 4, count 0 2006.239.08:18:19.21#ibcon#end of sib2, iclass 4, count 0 2006.239.08:18:19.21#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:18:19.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:18:19.21#ibcon#[25=USB\r\n] 2006.239.08:18:19.21#ibcon#*before write, iclass 4, count 0 2006.239.08:18:19.21#ibcon#enter sib2, iclass 4, count 0 2006.239.08:18:19.21#ibcon#flushed, iclass 4, count 0 2006.239.08:18:19.21#ibcon#about to write, iclass 4, count 0 2006.239.08:18:19.21#ibcon#wrote, iclass 4, count 0 2006.239.08:18:19.21#ibcon#about to read 3, iclass 4, count 0 2006.239.08:18:19.24#ibcon#read 3, iclass 4, count 0 2006.239.08:18:19.24#ibcon#about to read 4, iclass 4, count 0 2006.239.08:18:19.24#ibcon#read 4, iclass 4, count 0 2006.239.08:18:19.24#ibcon#about to read 5, iclass 4, count 0 2006.239.08:18:19.24#ibcon#read 5, iclass 4, count 0 2006.239.08:18:19.24#ibcon#about to read 6, iclass 4, count 0 2006.239.08:18:19.24#ibcon#read 6, iclass 4, count 0 2006.239.08:18:19.24#ibcon#end of sib2, iclass 4, count 0 2006.239.08:18:19.24#ibcon#*after write, iclass 4, count 0 2006.239.08:18:19.24#ibcon#*before return 0, iclass 4, count 0 2006.239.08:18:19.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:19.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:19.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:18:19.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:18:19.24$vc4f8/valo=5,652.99 2006.239.08:18:19.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.08:18:19.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.08:18:19.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:19.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:19.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:19.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:19.24#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:18:19.24#ibcon#first serial, iclass 6, count 0 2006.239.08:18:19.24#ibcon#enter sib2, iclass 6, count 0 2006.239.08:18:19.24#ibcon#flushed, iclass 6, count 0 2006.239.08:18:19.24#ibcon#about to write, iclass 6, count 0 2006.239.08:18:19.24#ibcon#wrote, iclass 6, count 0 2006.239.08:18:19.24#ibcon#about to read 3, iclass 6, count 0 2006.239.08:18:19.26#ibcon#read 3, iclass 6, count 0 2006.239.08:18:19.26#ibcon#about to read 4, iclass 6, count 0 2006.239.08:18:19.26#ibcon#read 4, iclass 6, count 0 2006.239.08:18:19.26#ibcon#about to read 5, iclass 6, count 0 2006.239.08:18:19.26#ibcon#read 5, iclass 6, count 0 2006.239.08:18:19.26#ibcon#about to read 6, iclass 6, count 0 2006.239.08:18:19.26#ibcon#read 6, iclass 6, count 0 2006.239.08:18:19.26#ibcon#end of sib2, iclass 6, count 0 2006.239.08:18:19.26#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:18:19.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:18:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:18:19.26#ibcon#*before write, iclass 6, count 0 2006.239.08:18:19.26#ibcon#enter sib2, iclass 6, count 0 2006.239.08:18:19.26#ibcon#flushed, iclass 6, count 0 2006.239.08:18:19.26#ibcon#about to write, iclass 6, count 0 2006.239.08:18:19.26#ibcon#wrote, iclass 6, count 0 2006.239.08:18:19.26#ibcon#about to read 3, iclass 6, count 0 2006.239.08:18:19.30#ibcon#read 3, iclass 6, count 0 2006.239.08:18:19.30#ibcon#about to read 4, iclass 6, count 0 2006.239.08:18:19.30#ibcon#read 4, iclass 6, count 0 2006.239.08:18:19.30#ibcon#about to read 5, iclass 6, count 0 2006.239.08:18:19.30#ibcon#read 5, iclass 6, count 0 2006.239.08:18:19.30#ibcon#about to read 6, iclass 6, count 0 2006.239.08:18:19.30#ibcon#read 6, iclass 6, count 0 2006.239.08:18:19.30#ibcon#end of sib2, iclass 6, count 0 2006.239.08:18:19.30#ibcon#*after write, iclass 6, count 0 2006.239.08:18:19.30#ibcon#*before return 0, iclass 6, count 0 2006.239.08:18:19.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:19.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:19.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:18:19.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:18:19.30$vc4f8/va=5,8 2006.239.08:18:19.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.08:18:19.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.08:18:19.30#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:19.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:19.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:19.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:19.36#ibcon#enter wrdev, iclass 10, count 2 2006.239.08:18:19.36#ibcon#first serial, iclass 10, count 2 2006.239.08:18:19.36#ibcon#enter sib2, iclass 10, count 2 2006.239.08:18:19.36#ibcon#flushed, iclass 10, count 2 2006.239.08:18:19.36#ibcon#about to write, iclass 10, count 2 2006.239.08:18:19.36#ibcon#wrote, iclass 10, count 2 2006.239.08:18:19.36#ibcon#about to read 3, iclass 10, count 2 2006.239.08:18:19.38#ibcon#read 3, iclass 10, count 2 2006.239.08:18:19.38#ibcon#about to read 4, iclass 10, count 2 2006.239.08:18:19.38#ibcon#read 4, iclass 10, count 2 2006.239.08:18:19.38#ibcon#about to read 5, iclass 10, count 2 2006.239.08:18:19.38#ibcon#read 5, iclass 10, count 2 2006.239.08:18:19.38#ibcon#about to read 6, iclass 10, count 2 2006.239.08:18:19.38#ibcon#read 6, iclass 10, count 2 2006.239.08:18:19.38#ibcon#end of sib2, iclass 10, count 2 2006.239.08:18:19.38#ibcon#*mode == 0, iclass 10, count 2 2006.239.08:18:19.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.08:18:19.38#ibcon#[25=AT05-08\r\n] 2006.239.08:18:19.38#ibcon#*before write, iclass 10, count 2 2006.239.08:18:19.38#ibcon#enter sib2, iclass 10, count 2 2006.239.08:18:19.38#ibcon#flushed, iclass 10, count 2 2006.239.08:18:19.38#ibcon#about to write, iclass 10, count 2 2006.239.08:18:19.38#ibcon#wrote, iclass 10, count 2 2006.239.08:18:19.38#ibcon#about to read 3, iclass 10, count 2 2006.239.08:18:19.41#ibcon#read 3, iclass 10, count 2 2006.239.08:18:19.41#ibcon#about to read 4, iclass 10, count 2 2006.239.08:18:19.41#ibcon#read 4, iclass 10, count 2 2006.239.08:18:19.41#ibcon#about to read 5, iclass 10, count 2 2006.239.08:18:19.41#ibcon#read 5, iclass 10, count 2 2006.239.08:18:19.41#ibcon#about to read 6, iclass 10, count 2 2006.239.08:18:19.41#ibcon#read 6, iclass 10, count 2 2006.239.08:18:19.41#ibcon#end of sib2, iclass 10, count 2 2006.239.08:18:19.41#ibcon#*after write, iclass 10, count 2 2006.239.08:18:19.41#ibcon#*before return 0, iclass 10, count 2 2006.239.08:18:19.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:19.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:19.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.08:18:19.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:19.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:19.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:19.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:19.53#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:18:19.53#ibcon#first serial, iclass 10, count 0 2006.239.08:18:19.53#ibcon#enter sib2, iclass 10, count 0 2006.239.08:18:19.53#ibcon#flushed, iclass 10, count 0 2006.239.08:18:19.53#ibcon#about to write, iclass 10, count 0 2006.239.08:18:19.53#ibcon#wrote, iclass 10, count 0 2006.239.08:18:19.53#ibcon#about to read 3, iclass 10, count 0 2006.239.08:18:19.55#ibcon#read 3, iclass 10, count 0 2006.239.08:18:19.55#ibcon#about to read 4, iclass 10, count 0 2006.239.08:18:19.55#ibcon#read 4, iclass 10, count 0 2006.239.08:18:19.55#ibcon#about to read 5, iclass 10, count 0 2006.239.08:18:19.55#ibcon#read 5, iclass 10, count 0 2006.239.08:18:19.55#ibcon#about to read 6, iclass 10, count 0 2006.239.08:18:19.55#ibcon#read 6, iclass 10, count 0 2006.239.08:18:19.55#ibcon#end of sib2, iclass 10, count 0 2006.239.08:18:19.55#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:18:19.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:18:19.55#ibcon#[25=USB\r\n] 2006.239.08:18:19.55#ibcon#*before write, iclass 10, count 0 2006.239.08:18:19.55#ibcon#enter sib2, iclass 10, count 0 2006.239.08:18:19.55#ibcon#flushed, iclass 10, count 0 2006.239.08:18:19.55#ibcon#about to write, iclass 10, count 0 2006.239.08:18:19.55#ibcon#wrote, iclass 10, count 0 2006.239.08:18:19.55#ibcon#about to read 3, iclass 10, count 0 2006.239.08:18:19.58#ibcon#read 3, iclass 10, count 0 2006.239.08:18:19.58#ibcon#about to read 4, iclass 10, count 0 2006.239.08:18:19.58#ibcon#read 4, iclass 10, count 0 2006.239.08:18:19.58#ibcon#about to read 5, iclass 10, count 0 2006.239.08:18:19.58#ibcon#read 5, iclass 10, count 0 2006.239.08:18:19.58#ibcon#about to read 6, iclass 10, count 0 2006.239.08:18:19.58#ibcon#read 6, iclass 10, count 0 2006.239.08:18:19.58#ibcon#end of sib2, iclass 10, count 0 2006.239.08:18:19.58#ibcon#*after write, iclass 10, count 0 2006.239.08:18:19.58#ibcon#*before return 0, iclass 10, count 0 2006.239.08:18:19.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:19.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:19.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:18:19.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:18:19.58$vc4f8/valo=6,772.99 2006.239.08:18:19.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.239.08:18:19.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.239.08:18:19.58#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:19.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:18:19.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:18:19.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:18:19.58#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:18:19.58#ibcon#first serial, iclass 12, count 0 2006.239.08:18:19.58#ibcon#enter sib2, iclass 12, count 0 2006.239.08:18:19.58#ibcon#flushed, iclass 12, count 0 2006.239.08:18:19.58#ibcon#about to write, iclass 12, count 0 2006.239.08:18:19.58#ibcon#wrote, iclass 12, count 0 2006.239.08:18:19.58#ibcon#about to read 3, iclass 12, count 0 2006.239.08:18:19.60#ibcon#read 3, iclass 12, count 0 2006.239.08:18:19.60#ibcon#about to read 4, iclass 12, count 0 2006.239.08:18:19.60#ibcon#read 4, iclass 12, count 0 2006.239.08:18:19.60#ibcon#about to read 5, iclass 12, count 0 2006.239.08:18:19.60#ibcon#read 5, iclass 12, count 0 2006.239.08:18:19.60#ibcon#about to read 6, iclass 12, count 0 2006.239.08:18:19.60#ibcon#read 6, iclass 12, count 0 2006.239.08:18:19.60#ibcon#end of sib2, iclass 12, count 0 2006.239.08:18:19.60#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:18:19.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:18:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:18:19.60#ibcon#*before write, iclass 12, count 0 2006.239.08:18:19.60#ibcon#enter sib2, iclass 12, count 0 2006.239.08:18:19.60#ibcon#flushed, iclass 12, count 0 2006.239.08:18:19.60#ibcon#about to write, iclass 12, count 0 2006.239.08:18:19.60#ibcon#wrote, iclass 12, count 0 2006.239.08:18:19.60#ibcon#about to read 3, iclass 12, count 0 2006.239.08:18:19.64#ibcon#read 3, iclass 12, count 0 2006.239.08:18:19.64#ibcon#about to read 4, iclass 12, count 0 2006.239.08:18:19.64#ibcon#read 4, iclass 12, count 0 2006.239.08:18:19.64#ibcon#about to read 5, iclass 12, count 0 2006.239.08:18:19.64#ibcon#read 5, iclass 12, count 0 2006.239.08:18:19.64#ibcon#about to read 6, iclass 12, count 0 2006.239.08:18:19.64#ibcon#read 6, iclass 12, count 0 2006.239.08:18:19.64#ibcon#end of sib2, iclass 12, count 0 2006.239.08:18:19.64#ibcon#*after write, iclass 12, count 0 2006.239.08:18:19.65#ibcon#*before return 0, iclass 12, count 0 2006.239.08:18:19.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:18:19.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.239.08:18:19.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:18:19.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:18:19.65$vc4f8/va=6,7 2006.239.08:18:19.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.239.08:18:19.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.239.08:18:19.65#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:19.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:18:19.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:18:19.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:18:19.69#ibcon#enter wrdev, iclass 14, count 2 2006.239.08:18:19.69#ibcon#first serial, iclass 14, count 2 2006.239.08:18:19.69#ibcon#enter sib2, iclass 14, count 2 2006.239.08:18:19.69#ibcon#flushed, iclass 14, count 2 2006.239.08:18:19.69#ibcon#about to write, iclass 14, count 2 2006.239.08:18:19.69#ibcon#wrote, iclass 14, count 2 2006.239.08:18:19.69#ibcon#about to read 3, iclass 14, count 2 2006.239.08:18:19.71#ibcon#read 3, iclass 14, count 2 2006.239.08:18:19.71#ibcon#about to read 4, iclass 14, count 2 2006.239.08:18:19.71#ibcon#read 4, iclass 14, count 2 2006.239.08:18:19.71#ibcon#about to read 5, iclass 14, count 2 2006.239.08:18:19.71#ibcon#read 5, iclass 14, count 2 2006.239.08:18:19.71#ibcon#about to read 6, iclass 14, count 2 2006.239.08:18:19.71#ibcon#read 6, iclass 14, count 2 2006.239.08:18:19.71#ibcon#end of sib2, iclass 14, count 2 2006.239.08:18:19.71#ibcon#*mode == 0, iclass 14, count 2 2006.239.08:18:19.71#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.239.08:18:19.71#ibcon#[25=AT06-07\r\n] 2006.239.08:18:19.71#ibcon#*before write, iclass 14, count 2 2006.239.08:18:19.71#ibcon#enter sib2, iclass 14, count 2 2006.239.08:18:19.71#ibcon#flushed, iclass 14, count 2 2006.239.08:18:19.71#ibcon#about to write, iclass 14, count 2 2006.239.08:18:19.71#ibcon#wrote, iclass 14, count 2 2006.239.08:18:19.71#ibcon#about to read 3, iclass 14, count 2 2006.239.08:18:19.74#ibcon#read 3, iclass 14, count 2 2006.239.08:18:19.74#ibcon#about to read 4, iclass 14, count 2 2006.239.08:18:19.74#ibcon#read 4, iclass 14, count 2 2006.239.08:18:19.74#ibcon#about to read 5, iclass 14, count 2 2006.239.08:18:19.74#ibcon#read 5, iclass 14, count 2 2006.239.08:18:19.74#ibcon#about to read 6, iclass 14, count 2 2006.239.08:18:19.74#ibcon#read 6, iclass 14, count 2 2006.239.08:18:19.74#ibcon#end of sib2, iclass 14, count 2 2006.239.08:18:19.74#ibcon#*after write, iclass 14, count 2 2006.239.08:18:19.74#ibcon#*before return 0, iclass 14, count 2 2006.239.08:18:19.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:18:19.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.239.08:18:19.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.239.08:18:19.74#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:19.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:18:19.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:18:19.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:18:19.86#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:18:19.86#ibcon#first serial, iclass 14, count 0 2006.239.08:18:19.86#ibcon#enter sib2, iclass 14, count 0 2006.239.08:18:19.86#ibcon#flushed, iclass 14, count 0 2006.239.08:18:19.86#ibcon#about to write, iclass 14, count 0 2006.239.08:18:19.86#ibcon#wrote, iclass 14, count 0 2006.239.08:18:19.86#ibcon#about to read 3, iclass 14, count 0 2006.239.08:18:19.88#ibcon#read 3, iclass 14, count 0 2006.239.08:18:19.88#ibcon#about to read 4, iclass 14, count 0 2006.239.08:18:19.88#ibcon#read 4, iclass 14, count 0 2006.239.08:18:19.88#ibcon#about to read 5, iclass 14, count 0 2006.239.08:18:19.88#ibcon#read 5, iclass 14, count 0 2006.239.08:18:19.88#ibcon#about to read 6, iclass 14, count 0 2006.239.08:18:19.88#ibcon#read 6, iclass 14, count 0 2006.239.08:18:19.88#ibcon#end of sib2, iclass 14, count 0 2006.239.08:18:19.88#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:18:19.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:18:19.88#ibcon#[25=USB\r\n] 2006.239.08:18:19.88#ibcon#*before write, iclass 14, count 0 2006.239.08:18:19.88#ibcon#enter sib2, iclass 14, count 0 2006.239.08:18:19.88#ibcon#flushed, iclass 14, count 0 2006.239.08:18:19.88#ibcon#about to write, iclass 14, count 0 2006.239.08:18:19.88#ibcon#wrote, iclass 14, count 0 2006.239.08:18:19.88#ibcon#about to read 3, iclass 14, count 0 2006.239.08:18:19.91#ibcon#read 3, iclass 14, count 0 2006.239.08:18:19.91#ibcon#about to read 4, iclass 14, count 0 2006.239.08:18:19.91#ibcon#read 4, iclass 14, count 0 2006.239.08:18:19.91#ibcon#about to read 5, iclass 14, count 0 2006.239.08:18:19.91#ibcon#read 5, iclass 14, count 0 2006.239.08:18:19.91#ibcon#about to read 6, iclass 14, count 0 2006.239.08:18:19.91#ibcon#read 6, iclass 14, count 0 2006.239.08:18:19.91#ibcon#end of sib2, iclass 14, count 0 2006.239.08:18:19.91#ibcon#*after write, iclass 14, count 0 2006.239.08:18:19.91#ibcon#*before return 0, iclass 14, count 0 2006.239.08:18:19.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:18:19.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.239.08:18:19.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:18:19.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:18:19.91$vc4f8/valo=7,832.99 2006.239.08:18:19.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.08:18:19.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.08:18:19.91#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:19.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:19.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:19.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:19.91#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:18:19.91#ibcon#first serial, iclass 16, count 0 2006.239.08:18:19.91#ibcon#enter sib2, iclass 16, count 0 2006.239.08:18:19.91#ibcon#flushed, iclass 16, count 0 2006.239.08:18:19.91#ibcon#about to write, iclass 16, count 0 2006.239.08:18:19.91#ibcon#wrote, iclass 16, count 0 2006.239.08:18:19.91#ibcon#about to read 3, iclass 16, count 0 2006.239.08:18:19.93#ibcon#read 3, iclass 16, count 0 2006.239.08:18:19.93#ibcon#about to read 4, iclass 16, count 0 2006.239.08:18:19.93#ibcon#read 4, iclass 16, count 0 2006.239.08:18:19.93#ibcon#about to read 5, iclass 16, count 0 2006.239.08:18:19.93#ibcon#read 5, iclass 16, count 0 2006.239.08:18:19.93#ibcon#about to read 6, iclass 16, count 0 2006.239.08:18:19.93#ibcon#read 6, iclass 16, count 0 2006.239.08:18:19.93#ibcon#end of sib2, iclass 16, count 0 2006.239.08:18:19.93#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:18:19.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:18:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:18:19.93#ibcon#*before write, iclass 16, count 0 2006.239.08:18:19.93#ibcon#enter sib2, iclass 16, count 0 2006.239.08:18:19.93#ibcon#flushed, iclass 16, count 0 2006.239.08:18:19.93#ibcon#about to write, iclass 16, count 0 2006.239.08:18:19.93#ibcon#wrote, iclass 16, count 0 2006.239.08:18:19.93#ibcon#about to read 3, iclass 16, count 0 2006.239.08:18:19.97#ibcon#read 3, iclass 16, count 0 2006.239.08:18:19.97#ibcon#about to read 4, iclass 16, count 0 2006.239.08:18:19.97#ibcon#read 4, iclass 16, count 0 2006.239.08:18:19.97#ibcon#about to read 5, iclass 16, count 0 2006.239.08:18:19.97#ibcon#read 5, iclass 16, count 0 2006.239.08:18:19.97#ibcon#about to read 6, iclass 16, count 0 2006.239.08:18:19.97#ibcon#read 6, iclass 16, count 0 2006.239.08:18:19.97#ibcon#end of sib2, iclass 16, count 0 2006.239.08:18:19.97#ibcon#*after write, iclass 16, count 0 2006.239.08:18:19.97#ibcon#*before return 0, iclass 16, count 0 2006.239.08:18:19.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:19.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:19.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:18:19.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:18:19.97$vc4f8/va=7,7 2006.239.08:18:19.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.239.08:18:19.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.239.08:18:19.97#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:19.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:18:20.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:18:20.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:18:20.03#ibcon#enter wrdev, iclass 18, count 2 2006.239.08:18:20.03#ibcon#first serial, iclass 18, count 2 2006.239.08:18:20.03#ibcon#enter sib2, iclass 18, count 2 2006.239.08:18:20.03#ibcon#flushed, iclass 18, count 2 2006.239.08:18:20.03#ibcon#about to write, iclass 18, count 2 2006.239.08:18:20.03#ibcon#wrote, iclass 18, count 2 2006.239.08:18:20.03#ibcon#about to read 3, iclass 18, count 2 2006.239.08:18:20.05#ibcon#read 3, iclass 18, count 2 2006.239.08:18:20.05#ibcon#about to read 4, iclass 18, count 2 2006.239.08:18:20.05#ibcon#read 4, iclass 18, count 2 2006.239.08:18:20.05#ibcon#about to read 5, iclass 18, count 2 2006.239.08:18:20.05#ibcon#read 5, iclass 18, count 2 2006.239.08:18:20.05#ibcon#about to read 6, iclass 18, count 2 2006.239.08:18:20.05#ibcon#read 6, iclass 18, count 2 2006.239.08:18:20.05#ibcon#end of sib2, iclass 18, count 2 2006.239.08:18:20.05#ibcon#*mode == 0, iclass 18, count 2 2006.239.08:18:20.05#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.239.08:18:20.05#ibcon#[25=AT07-07\r\n] 2006.239.08:18:20.05#ibcon#*before write, iclass 18, count 2 2006.239.08:18:20.05#ibcon#enter sib2, iclass 18, count 2 2006.239.08:18:20.05#ibcon#flushed, iclass 18, count 2 2006.239.08:18:20.05#ibcon#about to write, iclass 18, count 2 2006.239.08:18:20.05#ibcon#wrote, iclass 18, count 2 2006.239.08:18:20.05#ibcon#about to read 3, iclass 18, count 2 2006.239.08:18:20.08#ibcon#read 3, iclass 18, count 2 2006.239.08:18:20.08#ibcon#about to read 4, iclass 18, count 2 2006.239.08:18:20.08#ibcon#read 4, iclass 18, count 2 2006.239.08:18:20.08#ibcon#about to read 5, iclass 18, count 2 2006.239.08:18:20.08#ibcon#read 5, iclass 18, count 2 2006.239.08:18:20.08#ibcon#about to read 6, iclass 18, count 2 2006.239.08:18:20.08#ibcon#read 6, iclass 18, count 2 2006.239.08:18:20.08#ibcon#end of sib2, iclass 18, count 2 2006.239.08:18:20.08#ibcon#*after write, iclass 18, count 2 2006.239.08:18:20.08#ibcon#*before return 0, iclass 18, count 2 2006.239.08:18:20.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:18:20.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.239.08:18:20.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.239.08:18:20.08#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:20.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:18:20.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:18:20.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:18:20.20#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:18:20.20#ibcon#first serial, iclass 18, count 0 2006.239.08:18:20.20#ibcon#enter sib2, iclass 18, count 0 2006.239.08:18:20.20#ibcon#flushed, iclass 18, count 0 2006.239.08:18:20.20#ibcon#about to write, iclass 18, count 0 2006.239.08:18:20.20#ibcon#wrote, iclass 18, count 0 2006.239.08:18:20.20#ibcon#about to read 3, iclass 18, count 0 2006.239.08:18:20.23#ibcon#read 3, iclass 18, count 0 2006.239.08:18:20.23#ibcon#about to read 4, iclass 18, count 0 2006.239.08:18:20.23#ibcon#read 4, iclass 18, count 0 2006.239.08:18:20.23#ibcon#about to read 5, iclass 18, count 0 2006.239.08:18:20.23#ibcon#read 5, iclass 18, count 0 2006.239.08:18:20.23#ibcon#about to read 6, iclass 18, count 0 2006.239.08:18:20.23#ibcon#read 6, iclass 18, count 0 2006.239.08:18:20.23#ibcon#end of sib2, iclass 18, count 0 2006.239.08:18:20.23#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:18:20.23#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:18:20.23#ibcon#[25=USB\r\n] 2006.239.08:18:20.23#ibcon#*before write, iclass 18, count 0 2006.239.08:18:20.23#ibcon#enter sib2, iclass 18, count 0 2006.239.08:18:20.23#ibcon#flushed, iclass 18, count 0 2006.239.08:18:20.23#ibcon#about to write, iclass 18, count 0 2006.239.08:18:20.23#ibcon#wrote, iclass 18, count 0 2006.239.08:18:20.23#ibcon#about to read 3, iclass 18, count 0 2006.239.08:18:20.25#ibcon#read 3, iclass 18, count 0 2006.239.08:18:20.25#ibcon#about to read 4, iclass 18, count 0 2006.239.08:18:20.25#ibcon#read 4, iclass 18, count 0 2006.239.08:18:20.25#ibcon#about to read 5, iclass 18, count 0 2006.239.08:18:20.25#ibcon#read 5, iclass 18, count 0 2006.239.08:18:20.25#ibcon#about to read 6, iclass 18, count 0 2006.239.08:18:20.25#ibcon#read 6, iclass 18, count 0 2006.239.08:18:20.25#ibcon#end of sib2, iclass 18, count 0 2006.239.08:18:20.25#ibcon#*after write, iclass 18, count 0 2006.239.08:18:20.25#ibcon#*before return 0, iclass 18, count 0 2006.239.08:18:20.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:18:20.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.239.08:18:20.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:18:20.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:18:20.25$vc4f8/valo=8,852.99 2006.239.08:18:20.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.239.08:18:20.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.239.08:18:20.25#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:20.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:18:20.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:18:20.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:18:20.25#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:18:20.25#ibcon#first serial, iclass 20, count 0 2006.239.08:18:20.25#ibcon#enter sib2, iclass 20, count 0 2006.239.08:18:20.25#ibcon#flushed, iclass 20, count 0 2006.239.08:18:20.25#ibcon#about to write, iclass 20, count 0 2006.239.08:18:20.25#ibcon#wrote, iclass 20, count 0 2006.239.08:18:20.25#ibcon#about to read 3, iclass 20, count 0 2006.239.08:18:20.27#ibcon#read 3, iclass 20, count 0 2006.239.08:18:20.27#ibcon#about to read 4, iclass 20, count 0 2006.239.08:18:20.27#ibcon#read 4, iclass 20, count 0 2006.239.08:18:20.27#ibcon#about to read 5, iclass 20, count 0 2006.239.08:18:20.27#ibcon#read 5, iclass 20, count 0 2006.239.08:18:20.27#ibcon#about to read 6, iclass 20, count 0 2006.239.08:18:20.27#ibcon#read 6, iclass 20, count 0 2006.239.08:18:20.27#ibcon#end of sib2, iclass 20, count 0 2006.239.08:18:20.27#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:18:20.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:18:20.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:18:20.27#ibcon#*before write, iclass 20, count 0 2006.239.08:18:20.27#ibcon#enter sib2, iclass 20, count 0 2006.239.08:18:20.27#ibcon#flushed, iclass 20, count 0 2006.239.08:18:20.27#ibcon#about to write, iclass 20, count 0 2006.239.08:18:20.27#ibcon#wrote, iclass 20, count 0 2006.239.08:18:20.27#ibcon#about to read 3, iclass 20, count 0 2006.239.08:18:20.31#ibcon#read 3, iclass 20, count 0 2006.239.08:18:20.31#ibcon#about to read 4, iclass 20, count 0 2006.239.08:18:20.31#ibcon#read 4, iclass 20, count 0 2006.239.08:18:20.31#ibcon#about to read 5, iclass 20, count 0 2006.239.08:18:20.31#ibcon#read 5, iclass 20, count 0 2006.239.08:18:20.31#ibcon#about to read 6, iclass 20, count 0 2006.239.08:18:20.31#ibcon#read 6, iclass 20, count 0 2006.239.08:18:20.31#ibcon#end of sib2, iclass 20, count 0 2006.239.08:18:20.31#ibcon#*after write, iclass 20, count 0 2006.239.08:18:20.31#ibcon#*before return 0, iclass 20, count 0 2006.239.08:18:20.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:18:20.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.239.08:18:20.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:18:20.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:18:20.31$vc4f8/va=8,7 2006.239.08:18:20.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.239.08:18:20.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.239.08:18:20.31#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:20.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:18:20.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:18:20.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:18:20.37#ibcon#enter wrdev, iclass 22, count 2 2006.239.08:18:20.37#ibcon#first serial, iclass 22, count 2 2006.239.08:18:20.37#ibcon#enter sib2, iclass 22, count 2 2006.239.08:18:20.37#ibcon#flushed, iclass 22, count 2 2006.239.08:18:20.37#ibcon#about to write, iclass 22, count 2 2006.239.08:18:20.37#ibcon#wrote, iclass 22, count 2 2006.239.08:18:20.37#ibcon#about to read 3, iclass 22, count 2 2006.239.08:18:20.39#ibcon#read 3, iclass 22, count 2 2006.239.08:18:20.39#ibcon#about to read 4, iclass 22, count 2 2006.239.08:18:20.39#ibcon#read 4, iclass 22, count 2 2006.239.08:18:20.39#ibcon#about to read 5, iclass 22, count 2 2006.239.08:18:20.39#ibcon#read 5, iclass 22, count 2 2006.239.08:18:20.39#ibcon#about to read 6, iclass 22, count 2 2006.239.08:18:20.39#ibcon#read 6, iclass 22, count 2 2006.239.08:18:20.39#ibcon#end of sib2, iclass 22, count 2 2006.239.08:18:20.39#ibcon#*mode == 0, iclass 22, count 2 2006.239.08:18:20.39#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.239.08:18:20.39#ibcon#[25=AT08-07\r\n] 2006.239.08:18:20.39#ibcon#*before write, iclass 22, count 2 2006.239.08:18:20.39#ibcon#enter sib2, iclass 22, count 2 2006.239.08:18:20.39#ibcon#flushed, iclass 22, count 2 2006.239.08:18:20.39#ibcon#about to write, iclass 22, count 2 2006.239.08:18:20.39#ibcon#wrote, iclass 22, count 2 2006.239.08:18:20.39#ibcon#about to read 3, iclass 22, count 2 2006.239.08:18:20.42#ibcon#read 3, iclass 22, count 2 2006.239.08:18:20.42#ibcon#about to read 4, iclass 22, count 2 2006.239.08:18:20.42#ibcon#read 4, iclass 22, count 2 2006.239.08:18:20.42#ibcon#about to read 5, iclass 22, count 2 2006.239.08:18:20.42#ibcon#read 5, iclass 22, count 2 2006.239.08:18:20.42#ibcon#about to read 6, iclass 22, count 2 2006.239.08:18:20.42#ibcon#read 6, iclass 22, count 2 2006.239.08:18:20.42#ibcon#end of sib2, iclass 22, count 2 2006.239.08:18:20.42#ibcon#*after write, iclass 22, count 2 2006.239.08:18:20.42#ibcon#*before return 0, iclass 22, count 2 2006.239.08:18:20.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:18:20.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.239.08:18:20.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.239.08:18:20.42#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:20.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:18:20.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:18:20.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:18:20.54#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:18:20.54#ibcon#first serial, iclass 22, count 0 2006.239.08:18:20.54#ibcon#enter sib2, iclass 22, count 0 2006.239.08:18:20.54#ibcon#flushed, iclass 22, count 0 2006.239.08:18:20.54#ibcon#about to write, iclass 22, count 0 2006.239.08:18:20.54#ibcon#wrote, iclass 22, count 0 2006.239.08:18:20.54#ibcon#about to read 3, iclass 22, count 0 2006.239.08:18:20.56#ibcon#read 3, iclass 22, count 0 2006.239.08:18:20.56#ibcon#about to read 4, iclass 22, count 0 2006.239.08:18:20.56#ibcon#read 4, iclass 22, count 0 2006.239.08:18:20.56#ibcon#about to read 5, iclass 22, count 0 2006.239.08:18:20.56#ibcon#read 5, iclass 22, count 0 2006.239.08:18:20.56#ibcon#about to read 6, iclass 22, count 0 2006.239.08:18:20.56#ibcon#read 6, iclass 22, count 0 2006.239.08:18:20.56#ibcon#end of sib2, iclass 22, count 0 2006.239.08:18:20.56#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:18:20.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:18:20.56#ibcon#[25=USB\r\n] 2006.239.08:18:20.56#ibcon#*before write, iclass 22, count 0 2006.239.08:18:20.56#ibcon#enter sib2, iclass 22, count 0 2006.239.08:18:20.56#ibcon#flushed, iclass 22, count 0 2006.239.08:18:20.56#ibcon#about to write, iclass 22, count 0 2006.239.08:18:20.56#ibcon#wrote, iclass 22, count 0 2006.239.08:18:20.56#ibcon#about to read 3, iclass 22, count 0 2006.239.08:18:20.59#ibcon#read 3, iclass 22, count 0 2006.239.08:18:20.59#ibcon#about to read 4, iclass 22, count 0 2006.239.08:18:20.59#ibcon#read 4, iclass 22, count 0 2006.239.08:18:20.59#ibcon#about to read 5, iclass 22, count 0 2006.239.08:18:20.59#ibcon#read 5, iclass 22, count 0 2006.239.08:18:20.59#ibcon#about to read 6, iclass 22, count 0 2006.239.08:18:20.59#ibcon#read 6, iclass 22, count 0 2006.239.08:18:20.59#ibcon#end of sib2, iclass 22, count 0 2006.239.08:18:20.59#ibcon#*after write, iclass 22, count 0 2006.239.08:18:20.59#ibcon#*before return 0, iclass 22, count 0 2006.239.08:18:20.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:18:20.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.239.08:18:20.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:18:20.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:18:20.59$vc4f8/vblo=1,632.99 2006.239.08:18:20.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.239.08:18:20.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.239.08:18:20.59#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:20.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:18:20.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:18:20.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:18:20.59#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:18:20.59#ibcon#first serial, iclass 24, count 0 2006.239.08:18:20.59#ibcon#enter sib2, iclass 24, count 0 2006.239.08:18:20.59#ibcon#flushed, iclass 24, count 0 2006.239.08:18:20.59#ibcon#about to write, iclass 24, count 0 2006.239.08:18:20.59#ibcon#wrote, iclass 24, count 0 2006.239.08:18:20.59#ibcon#about to read 3, iclass 24, count 0 2006.239.08:18:20.61#ibcon#read 3, iclass 24, count 0 2006.239.08:18:20.61#ibcon#about to read 4, iclass 24, count 0 2006.239.08:18:20.61#ibcon#read 4, iclass 24, count 0 2006.239.08:18:20.61#ibcon#about to read 5, iclass 24, count 0 2006.239.08:18:20.61#ibcon#read 5, iclass 24, count 0 2006.239.08:18:20.61#ibcon#about to read 6, iclass 24, count 0 2006.239.08:18:20.61#ibcon#read 6, iclass 24, count 0 2006.239.08:18:20.61#ibcon#end of sib2, iclass 24, count 0 2006.239.08:18:20.61#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:18:20.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:18:20.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:18:20.61#ibcon#*before write, iclass 24, count 0 2006.239.08:18:20.61#ibcon#enter sib2, iclass 24, count 0 2006.239.08:18:20.61#ibcon#flushed, iclass 24, count 0 2006.239.08:18:20.61#ibcon#about to write, iclass 24, count 0 2006.239.08:18:20.61#ibcon#wrote, iclass 24, count 0 2006.239.08:18:20.61#ibcon#about to read 3, iclass 24, count 0 2006.239.08:18:20.65#ibcon#read 3, iclass 24, count 0 2006.239.08:18:20.65#ibcon#about to read 4, iclass 24, count 0 2006.239.08:18:20.65#ibcon#read 4, iclass 24, count 0 2006.239.08:18:20.65#ibcon#about to read 5, iclass 24, count 0 2006.239.08:18:20.65#ibcon#read 5, iclass 24, count 0 2006.239.08:18:20.65#ibcon#about to read 6, iclass 24, count 0 2006.239.08:18:20.65#ibcon#read 6, iclass 24, count 0 2006.239.08:18:20.65#ibcon#end of sib2, iclass 24, count 0 2006.239.08:18:20.65#ibcon#*after write, iclass 24, count 0 2006.239.08:18:20.65#ibcon#*before return 0, iclass 24, count 0 2006.239.08:18:20.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:18:20.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.239.08:18:20.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:18:20.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:18:20.65$vc4f8/vb=1,4 2006.239.08:18:20.65#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.239.08:18:20.65#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.239.08:18:20.65#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:20.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:18:20.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:18:20.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:18:20.65#ibcon#enter wrdev, iclass 26, count 2 2006.239.08:18:20.65#ibcon#first serial, iclass 26, count 2 2006.239.08:18:20.65#ibcon#enter sib2, iclass 26, count 2 2006.239.08:18:20.65#ibcon#flushed, iclass 26, count 2 2006.239.08:18:20.65#ibcon#about to write, iclass 26, count 2 2006.239.08:18:20.65#ibcon#wrote, iclass 26, count 2 2006.239.08:18:20.65#ibcon#about to read 3, iclass 26, count 2 2006.239.08:18:20.67#ibcon#read 3, iclass 26, count 2 2006.239.08:18:20.67#ibcon#about to read 4, iclass 26, count 2 2006.239.08:18:20.67#ibcon#read 4, iclass 26, count 2 2006.239.08:18:20.67#ibcon#about to read 5, iclass 26, count 2 2006.239.08:18:20.67#ibcon#read 5, iclass 26, count 2 2006.239.08:18:20.67#ibcon#about to read 6, iclass 26, count 2 2006.239.08:18:20.67#ibcon#read 6, iclass 26, count 2 2006.239.08:18:20.67#ibcon#end of sib2, iclass 26, count 2 2006.239.08:18:20.67#ibcon#*mode == 0, iclass 26, count 2 2006.239.08:18:20.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.239.08:18:20.67#ibcon#[27=AT01-04\r\n] 2006.239.08:18:20.67#ibcon#*before write, iclass 26, count 2 2006.239.08:18:20.67#ibcon#enter sib2, iclass 26, count 2 2006.239.08:18:20.67#ibcon#flushed, iclass 26, count 2 2006.239.08:18:20.67#ibcon#about to write, iclass 26, count 2 2006.239.08:18:20.67#ibcon#wrote, iclass 26, count 2 2006.239.08:18:20.67#ibcon#about to read 3, iclass 26, count 2 2006.239.08:18:20.70#ibcon#read 3, iclass 26, count 2 2006.239.08:18:20.70#ibcon#about to read 4, iclass 26, count 2 2006.239.08:18:20.70#ibcon#read 4, iclass 26, count 2 2006.239.08:18:20.70#ibcon#about to read 5, iclass 26, count 2 2006.239.08:18:20.70#ibcon#read 5, iclass 26, count 2 2006.239.08:18:20.70#ibcon#about to read 6, iclass 26, count 2 2006.239.08:18:20.70#ibcon#read 6, iclass 26, count 2 2006.239.08:18:20.70#ibcon#end of sib2, iclass 26, count 2 2006.239.08:18:20.70#ibcon#*after write, iclass 26, count 2 2006.239.08:18:20.70#ibcon#*before return 0, iclass 26, count 2 2006.239.08:18:20.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:18:20.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.239.08:18:20.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.239.08:18:20.70#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:20.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:18:20.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:18:20.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:18:20.82#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:18:20.82#ibcon#first serial, iclass 26, count 0 2006.239.08:18:20.82#ibcon#enter sib2, iclass 26, count 0 2006.239.08:18:20.82#ibcon#flushed, iclass 26, count 0 2006.239.08:18:20.82#ibcon#about to write, iclass 26, count 0 2006.239.08:18:20.82#ibcon#wrote, iclass 26, count 0 2006.239.08:18:20.82#ibcon#about to read 3, iclass 26, count 0 2006.239.08:18:20.85#ibcon#read 3, iclass 26, count 0 2006.239.08:18:20.85#ibcon#about to read 4, iclass 26, count 0 2006.239.08:18:20.85#ibcon#read 4, iclass 26, count 0 2006.239.08:18:20.85#ibcon#about to read 5, iclass 26, count 0 2006.239.08:18:20.85#ibcon#read 5, iclass 26, count 0 2006.239.08:18:20.85#ibcon#about to read 6, iclass 26, count 0 2006.239.08:18:20.85#ibcon#read 6, iclass 26, count 0 2006.239.08:18:20.85#ibcon#end of sib2, iclass 26, count 0 2006.239.08:18:20.85#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:18:20.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:18:20.85#ibcon#[27=USB\r\n] 2006.239.08:18:20.85#ibcon#*before write, iclass 26, count 0 2006.239.08:18:20.85#ibcon#enter sib2, iclass 26, count 0 2006.239.08:18:20.85#ibcon#flushed, iclass 26, count 0 2006.239.08:18:20.85#ibcon#about to write, iclass 26, count 0 2006.239.08:18:20.85#ibcon#wrote, iclass 26, count 0 2006.239.08:18:20.85#ibcon#about to read 3, iclass 26, count 0 2006.239.08:18:20.87#ibcon#read 3, iclass 26, count 0 2006.239.08:18:20.87#ibcon#about to read 4, iclass 26, count 0 2006.239.08:18:20.87#ibcon#read 4, iclass 26, count 0 2006.239.08:18:20.87#ibcon#about to read 5, iclass 26, count 0 2006.239.08:18:20.87#ibcon#read 5, iclass 26, count 0 2006.239.08:18:20.87#ibcon#about to read 6, iclass 26, count 0 2006.239.08:18:20.87#ibcon#read 6, iclass 26, count 0 2006.239.08:18:20.87#ibcon#end of sib2, iclass 26, count 0 2006.239.08:18:20.87#ibcon#*after write, iclass 26, count 0 2006.239.08:18:20.87#ibcon#*before return 0, iclass 26, count 0 2006.239.08:18:20.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:18:20.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.239.08:18:20.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:18:20.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:18:20.87$vc4f8/vblo=2,640.99 2006.239.08:18:20.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.239.08:18:20.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.239.08:18:20.87#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:20.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:20.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:20.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:20.87#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:18:20.87#ibcon#first serial, iclass 28, count 0 2006.239.08:18:20.87#ibcon#enter sib2, iclass 28, count 0 2006.239.08:18:20.87#ibcon#flushed, iclass 28, count 0 2006.239.08:18:20.87#ibcon#about to write, iclass 28, count 0 2006.239.08:18:20.87#ibcon#wrote, iclass 28, count 0 2006.239.08:18:20.87#ibcon#about to read 3, iclass 28, count 0 2006.239.08:18:20.89#ibcon#read 3, iclass 28, count 0 2006.239.08:18:20.89#ibcon#about to read 4, iclass 28, count 0 2006.239.08:18:20.89#ibcon#read 4, iclass 28, count 0 2006.239.08:18:20.89#ibcon#about to read 5, iclass 28, count 0 2006.239.08:18:20.89#ibcon#read 5, iclass 28, count 0 2006.239.08:18:20.89#ibcon#about to read 6, iclass 28, count 0 2006.239.08:18:20.89#ibcon#read 6, iclass 28, count 0 2006.239.08:18:20.89#ibcon#end of sib2, iclass 28, count 0 2006.239.08:18:20.89#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:18:20.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:18:20.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:18:20.89#ibcon#*before write, iclass 28, count 0 2006.239.08:18:20.89#ibcon#enter sib2, iclass 28, count 0 2006.239.08:18:20.89#ibcon#flushed, iclass 28, count 0 2006.239.08:18:20.89#ibcon#about to write, iclass 28, count 0 2006.239.08:18:20.89#ibcon#wrote, iclass 28, count 0 2006.239.08:18:20.89#ibcon#about to read 3, iclass 28, count 0 2006.239.08:18:20.93#ibcon#read 3, iclass 28, count 0 2006.239.08:18:20.93#ibcon#about to read 4, iclass 28, count 0 2006.239.08:18:20.93#ibcon#read 4, iclass 28, count 0 2006.239.08:18:20.93#ibcon#about to read 5, iclass 28, count 0 2006.239.08:18:20.93#ibcon#read 5, iclass 28, count 0 2006.239.08:18:20.93#ibcon#about to read 6, iclass 28, count 0 2006.239.08:18:20.93#ibcon#read 6, iclass 28, count 0 2006.239.08:18:20.93#ibcon#end of sib2, iclass 28, count 0 2006.239.08:18:20.93#ibcon#*after write, iclass 28, count 0 2006.239.08:18:20.93#ibcon#*before return 0, iclass 28, count 0 2006.239.08:18:20.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:20.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.239.08:18:20.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:18:20.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:18:20.93$vc4f8/vb=2,4 2006.239.08:18:20.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.239.08:18:20.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.239.08:18:20.93#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:20.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:20.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:20.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:20.99#ibcon#enter wrdev, iclass 30, count 2 2006.239.08:18:20.99#ibcon#first serial, iclass 30, count 2 2006.239.08:18:20.99#ibcon#enter sib2, iclass 30, count 2 2006.239.08:18:20.99#ibcon#flushed, iclass 30, count 2 2006.239.08:18:20.99#ibcon#about to write, iclass 30, count 2 2006.239.08:18:20.99#ibcon#wrote, iclass 30, count 2 2006.239.08:18:20.99#ibcon#about to read 3, iclass 30, count 2 2006.239.08:18:21.01#ibcon#read 3, iclass 30, count 2 2006.239.08:18:21.01#ibcon#about to read 4, iclass 30, count 2 2006.239.08:18:21.01#ibcon#read 4, iclass 30, count 2 2006.239.08:18:21.01#ibcon#about to read 5, iclass 30, count 2 2006.239.08:18:21.01#ibcon#read 5, iclass 30, count 2 2006.239.08:18:21.01#ibcon#about to read 6, iclass 30, count 2 2006.239.08:18:21.01#ibcon#read 6, iclass 30, count 2 2006.239.08:18:21.01#ibcon#end of sib2, iclass 30, count 2 2006.239.08:18:21.01#ibcon#*mode == 0, iclass 30, count 2 2006.239.08:18:21.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.239.08:18:21.01#ibcon#[27=AT02-04\r\n] 2006.239.08:18:21.01#ibcon#*before write, iclass 30, count 2 2006.239.08:18:21.01#ibcon#enter sib2, iclass 30, count 2 2006.239.08:18:21.01#ibcon#flushed, iclass 30, count 2 2006.239.08:18:21.01#ibcon#about to write, iclass 30, count 2 2006.239.08:18:21.01#ibcon#wrote, iclass 30, count 2 2006.239.08:18:21.01#ibcon#about to read 3, iclass 30, count 2 2006.239.08:18:21.04#ibcon#read 3, iclass 30, count 2 2006.239.08:18:21.04#ibcon#about to read 4, iclass 30, count 2 2006.239.08:18:21.04#ibcon#read 4, iclass 30, count 2 2006.239.08:18:21.04#ibcon#about to read 5, iclass 30, count 2 2006.239.08:18:21.04#ibcon#read 5, iclass 30, count 2 2006.239.08:18:21.04#ibcon#about to read 6, iclass 30, count 2 2006.239.08:18:21.04#ibcon#read 6, iclass 30, count 2 2006.239.08:18:21.04#ibcon#end of sib2, iclass 30, count 2 2006.239.08:18:21.04#ibcon#*after write, iclass 30, count 2 2006.239.08:18:21.04#ibcon#*before return 0, iclass 30, count 2 2006.239.08:18:21.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:21.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.239.08:18:21.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.239.08:18:21.04#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:21.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:21.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:21.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:21.16#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:18:21.16#ibcon#first serial, iclass 30, count 0 2006.239.08:18:21.16#ibcon#enter sib2, iclass 30, count 0 2006.239.08:18:21.16#ibcon#flushed, iclass 30, count 0 2006.239.08:18:21.16#ibcon#about to write, iclass 30, count 0 2006.239.08:18:21.16#ibcon#wrote, iclass 30, count 0 2006.239.08:18:21.16#ibcon#about to read 3, iclass 30, count 0 2006.239.08:18:21.18#ibcon#read 3, iclass 30, count 0 2006.239.08:18:21.18#ibcon#about to read 4, iclass 30, count 0 2006.239.08:18:21.18#ibcon#read 4, iclass 30, count 0 2006.239.08:18:21.18#ibcon#about to read 5, iclass 30, count 0 2006.239.08:18:21.18#ibcon#read 5, iclass 30, count 0 2006.239.08:18:21.18#ibcon#about to read 6, iclass 30, count 0 2006.239.08:18:21.18#ibcon#read 6, iclass 30, count 0 2006.239.08:18:21.18#ibcon#end of sib2, iclass 30, count 0 2006.239.08:18:21.18#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:18:21.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:18:21.18#ibcon#[27=USB\r\n] 2006.239.08:18:21.18#ibcon#*before write, iclass 30, count 0 2006.239.08:18:21.18#ibcon#enter sib2, iclass 30, count 0 2006.239.08:18:21.18#ibcon#flushed, iclass 30, count 0 2006.239.08:18:21.18#ibcon#about to write, iclass 30, count 0 2006.239.08:18:21.18#ibcon#wrote, iclass 30, count 0 2006.239.08:18:21.18#ibcon#about to read 3, iclass 30, count 0 2006.239.08:18:21.21#ibcon#read 3, iclass 30, count 0 2006.239.08:18:21.21#ibcon#about to read 4, iclass 30, count 0 2006.239.08:18:21.21#ibcon#read 4, iclass 30, count 0 2006.239.08:18:21.21#ibcon#about to read 5, iclass 30, count 0 2006.239.08:18:21.21#ibcon#read 5, iclass 30, count 0 2006.239.08:18:21.21#ibcon#about to read 6, iclass 30, count 0 2006.239.08:18:21.21#ibcon#read 6, iclass 30, count 0 2006.239.08:18:21.21#ibcon#end of sib2, iclass 30, count 0 2006.239.08:18:21.21#ibcon#*after write, iclass 30, count 0 2006.239.08:18:21.21#ibcon#*before return 0, iclass 30, count 0 2006.239.08:18:21.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:21.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.239.08:18:21.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:18:21.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:18:21.21$vc4f8/vblo=3,656.99 2006.239.08:18:21.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.239.08:18:21.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.239.08:18:21.21#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:21.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:21.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:21.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:21.21#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:18:21.21#ibcon#first serial, iclass 32, count 0 2006.239.08:18:21.21#ibcon#enter sib2, iclass 32, count 0 2006.239.08:18:21.21#ibcon#flushed, iclass 32, count 0 2006.239.08:18:21.21#ibcon#about to write, iclass 32, count 0 2006.239.08:18:21.21#ibcon#wrote, iclass 32, count 0 2006.239.08:18:21.21#ibcon#about to read 3, iclass 32, count 0 2006.239.08:18:21.23#ibcon#read 3, iclass 32, count 0 2006.239.08:18:21.23#ibcon#about to read 4, iclass 32, count 0 2006.239.08:18:21.23#ibcon#read 4, iclass 32, count 0 2006.239.08:18:21.23#ibcon#about to read 5, iclass 32, count 0 2006.239.08:18:21.23#ibcon#read 5, iclass 32, count 0 2006.239.08:18:21.23#ibcon#about to read 6, iclass 32, count 0 2006.239.08:18:21.23#ibcon#read 6, iclass 32, count 0 2006.239.08:18:21.23#ibcon#end of sib2, iclass 32, count 0 2006.239.08:18:21.23#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:18:21.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:18:21.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:18:21.23#ibcon#*before write, iclass 32, count 0 2006.239.08:18:21.23#ibcon#enter sib2, iclass 32, count 0 2006.239.08:18:21.23#ibcon#flushed, iclass 32, count 0 2006.239.08:18:21.23#ibcon#about to write, iclass 32, count 0 2006.239.08:18:21.23#ibcon#wrote, iclass 32, count 0 2006.239.08:18:21.23#ibcon#about to read 3, iclass 32, count 0 2006.239.08:18:21.27#ibcon#read 3, iclass 32, count 0 2006.239.08:18:21.27#ibcon#about to read 4, iclass 32, count 0 2006.239.08:18:21.27#ibcon#read 4, iclass 32, count 0 2006.239.08:18:21.27#ibcon#about to read 5, iclass 32, count 0 2006.239.08:18:21.27#ibcon#read 5, iclass 32, count 0 2006.239.08:18:21.27#ibcon#about to read 6, iclass 32, count 0 2006.239.08:18:21.27#ibcon#read 6, iclass 32, count 0 2006.239.08:18:21.27#ibcon#end of sib2, iclass 32, count 0 2006.239.08:18:21.27#ibcon#*after write, iclass 32, count 0 2006.239.08:18:21.27#ibcon#*before return 0, iclass 32, count 0 2006.239.08:18:21.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:21.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.239.08:18:21.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:18:21.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:18:21.27$vc4f8/vb=3,4 2006.239.08:18:21.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.239.08:18:21.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.239.08:18:21.27#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:21.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:21.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:21.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:21.33#ibcon#enter wrdev, iclass 34, count 2 2006.239.08:18:21.33#ibcon#first serial, iclass 34, count 2 2006.239.08:18:21.33#ibcon#enter sib2, iclass 34, count 2 2006.239.08:18:21.33#ibcon#flushed, iclass 34, count 2 2006.239.08:18:21.33#ibcon#about to write, iclass 34, count 2 2006.239.08:18:21.33#ibcon#wrote, iclass 34, count 2 2006.239.08:18:21.33#ibcon#about to read 3, iclass 34, count 2 2006.239.08:18:21.35#ibcon#read 3, iclass 34, count 2 2006.239.08:18:21.35#ibcon#about to read 4, iclass 34, count 2 2006.239.08:18:21.35#ibcon#read 4, iclass 34, count 2 2006.239.08:18:21.35#ibcon#about to read 5, iclass 34, count 2 2006.239.08:18:21.35#ibcon#read 5, iclass 34, count 2 2006.239.08:18:21.35#ibcon#about to read 6, iclass 34, count 2 2006.239.08:18:21.35#ibcon#read 6, iclass 34, count 2 2006.239.08:18:21.35#ibcon#end of sib2, iclass 34, count 2 2006.239.08:18:21.35#ibcon#*mode == 0, iclass 34, count 2 2006.239.08:18:21.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.239.08:18:21.35#ibcon#[27=AT03-04\r\n] 2006.239.08:18:21.35#ibcon#*before write, iclass 34, count 2 2006.239.08:18:21.35#ibcon#enter sib2, iclass 34, count 2 2006.239.08:18:21.35#ibcon#flushed, iclass 34, count 2 2006.239.08:18:21.35#ibcon#about to write, iclass 34, count 2 2006.239.08:18:21.35#ibcon#wrote, iclass 34, count 2 2006.239.08:18:21.35#ibcon#about to read 3, iclass 34, count 2 2006.239.08:18:21.38#ibcon#read 3, iclass 34, count 2 2006.239.08:18:21.38#ibcon#about to read 4, iclass 34, count 2 2006.239.08:18:21.38#ibcon#read 4, iclass 34, count 2 2006.239.08:18:21.38#ibcon#about to read 5, iclass 34, count 2 2006.239.08:18:21.38#ibcon#read 5, iclass 34, count 2 2006.239.08:18:21.38#ibcon#about to read 6, iclass 34, count 2 2006.239.08:18:21.38#ibcon#read 6, iclass 34, count 2 2006.239.08:18:21.38#ibcon#end of sib2, iclass 34, count 2 2006.239.08:18:21.38#ibcon#*after write, iclass 34, count 2 2006.239.08:18:21.38#ibcon#*before return 0, iclass 34, count 2 2006.239.08:18:21.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:21.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.239.08:18:21.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.239.08:18:21.38#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:21.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:21.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:21.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:21.50#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:18:21.50#ibcon#first serial, iclass 34, count 0 2006.239.08:18:21.50#ibcon#enter sib2, iclass 34, count 0 2006.239.08:18:21.50#ibcon#flushed, iclass 34, count 0 2006.239.08:18:21.50#ibcon#about to write, iclass 34, count 0 2006.239.08:18:21.50#ibcon#wrote, iclass 34, count 0 2006.239.08:18:21.50#ibcon#about to read 3, iclass 34, count 0 2006.239.08:18:21.52#ibcon#read 3, iclass 34, count 0 2006.239.08:18:21.52#ibcon#about to read 4, iclass 34, count 0 2006.239.08:18:21.52#ibcon#read 4, iclass 34, count 0 2006.239.08:18:21.52#ibcon#about to read 5, iclass 34, count 0 2006.239.08:18:21.52#ibcon#read 5, iclass 34, count 0 2006.239.08:18:21.52#ibcon#about to read 6, iclass 34, count 0 2006.239.08:18:21.52#ibcon#read 6, iclass 34, count 0 2006.239.08:18:21.52#ibcon#end of sib2, iclass 34, count 0 2006.239.08:18:21.52#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:18:21.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:18:21.52#ibcon#[27=USB\r\n] 2006.239.08:18:21.52#ibcon#*before write, iclass 34, count 0 2006.239.08:18:21.52#ibcon#enter sib2, iclass 34, count 0 2006.239.08:18:21.52#ibcon#flushed, iclass 34, count 0 2006.239.08:18:21.52#ibcon#about to write, iclass 34, count 0 2006.239.08:18:21.52#ibcon#wrote, iclass 34, count 0 2006.239.08:18:21.52#ibcon#about to read 3, iclass 34, count 0 2006.239.08:18:21.55#ibcon#read 3, iclass 34, count 0 2006.239.08:18:21.55#ibcon#about to read 4, iclass 34, count 0 2006.239.08:18:21.55#ibcon#read 4, iclass 34, count 0 2006.239.08:18:21.55#ibcon#about to read 5, iclass 34, count 0 2006.239.08:18:21.55#ibcon#read 5, iclass 34, count 0 2006.239.08:18:21.55#ibcon#about to read 6, iclass 34, count 0 2006.239.08:18:21.55#ibcon#read 6, iclass 34, count 0 2006.239.08:18:21.55#ibcon#end of sib2, iclass 34, count 0 2006.239.08:18:21.55#ibcon#*after write, iclass 34, count 0 2006.239.08:18:21.55#ibcon#*before return 0, iclass 34, count 0 2006.239.08:18:21.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:21.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.239.08:18:21.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:18:21.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:18:21.55$vc4f8/vblo=4,712.99 2006.239.08:18:21.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.239.08:18:21.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.239.08:18:21.55#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:21.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:21.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:21.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:21.55#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:18:21.55#ibcon#first serial, iclass 36, count 0 2006.239.08:18:21.55#ibcon#enter sib2, iclass 36, count 0 2006.239.08:18:21.55#ibcon#flushed, iclass 36, count 0 2006.239.08:18:21.55#ibcon#about to write, iclass 36, count 0 2006.239.08:18:21.55#ibcon#wrote, iclass 36, count 0 2006.239.08:18:21.55#ibcon#about to read 3, iclass 36, count 0 2006.239.08:18:21.57#ibcon#read 3, iclass 36, count 0 2006.239.08:18:21.57#ibcon#about to read 4, iclass 36, count 0 2006.239.08:18:21.57#ibcon#read 4, iclass 36, count 0 2006.239.08:18:21.57#ibcon#about to read 5, iclass 36, count 0 2006.239.08:18:21.57#ibcon#read 5, iclass 36, count 0 2006.239.08:18:21.57#ibcon#about to read 6, iclass 36, count 0 2006.239.08:18:21.57#ibcon#read 6, iclass 36, count 0 2006.239.08:18:21.57#ibcon#end of sib2, iclass 36, count 0 2006.239.08:18:21.57#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:18:21.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:18:21.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:18:21.57#ibcon#*before write, iclass 36, count 0 2006.239.08:18:21.57#ibcon#enter sib2, iclass 36, count 0 2006.239.08:18:21.57#ibcon#flushed, iclass 36, count 0 2006.239.08:18:21.57#ibcon#about to write, iclass 36, count 0 2006.239.08:18:21.57#ibcon#wrote, iclass 36, count 0 2006.239.08:18:21.57#ibcon#about to read 3, iclass 36, count 0 2006.239.08:18:21.61#ibcon#read 3, iclass 36, count 0 2006.239.08:18:21.61#ibcon#about to read 4, iclass 36, count 0 2006.239.08:18:21.61#ibcon#read 4, iclass 36, count 0 2006.239.08:18:21.61#ibcon#about to read 5, iclass 36, count 0 2006.239.08:18:21.61#ibcon#read 5, iclass 36, count 0 2006.239.08:18:21.61#ibcon#about to read 6, iclass 36, count 0 2006.239.08:18:21.61#ibcon#read 6, iclass 36, count 0 2006.239.08:18:21.61#ibcon#end of sib2, iclass 36, count 0 2006.239.08:18:21.61#ibcon#*after write, iclass 36, count 0 2006.239.08:18:21.61#ibcon#*before return 0, iclass 36, count 0 2006.239.08:18:21.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:21.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.239.08:18:21.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:18:21.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:18:21.61$vc4f8/vb=4,4 2006.239.08:18:21.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.239.08:18:21.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.239.08:18:21.61#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:21.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:21.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:21.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:21.67#ibcon#enter wrdev, iclass 38, count 2 2006.239.08:18:21.67#ibcon#first serial, iclass 38, count 2 2006.239.08:18:21.67#ibcon#enter sib2, iclass 38, count 2 2006.239.08:18:21.67#ibcon#flushed, iclass 38, count 2 2006.239.08:18:21.67#ibcon#about to write, iclass 38, count 2 2006.239.08:18:21.67#ibcon#wrote, iclass 38, count 2 2006.239.08:18:21.67#ibcon#about to read 3, iclass 38, count 2 2006.239.08:18:21.69#ibcon#read 3, iclass 38, count 2 2006.239.08:18:21.69#ibcon#about to read 4, iclass 38, count 2 2006.239.08:18:21.69#ibcon#read 4, iclass 38, count 2 2006.239.08:18:21.69#ibcon#about to read 5, iclass 38, count 2 2006.239.08:18:21.69#ibcon#read 5, iclass 38, count 2 2006.239.08:18:21.69#ibcon#about to read 6, iclass 38, count 2 2006.239.08:18:21.69#ibcon#read 6, iclass 38, count 2 2006.239.08:18:21.69#ibcon#end of sib2, iclass 38, count 2 2006.239.08:18:21.69#ibcon#*mode == 0, iclass 38, count 2 2006.239.08:18:21.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.239.08:18:21.69#ibcon#[27=AT04-04\r\n] 2006.239.08:18:21.69#ibcon#*before write, iclass 38, count 2 2006.239.08:18:21.69#ibcon#enter sib2, iclass 38, count 2 2006.239.08:18:21.69#ibcon#flushed, iclass 38, count 2 2006.239.08:18:21.69#ibcon#about to write, iclass 38, count 2 2006.239.08:18:21.69#ibcon#wrote, iclass 38, count 2 2006.239.08:18:21.69#ibcon#about to read 3, iclass 38, count 2 2006.239.08:18:21.72#ibcon#read 3, iclass 38, count 2 2006.239.08:18:21.72#ibcon#about to read 4, iclass 38, count 2 2006.239.08:18:21.72#ibcon#read 4, iclass 38, count 2 2006.239.08:18:21.72#ibcon#about to read 5, iclass 38, count 2 2006.239.08:18:21.72#ibcon#read 5, iclass 38, count 2 2006.239.08:18:21.72#ibcon#about to read 6, iclass 38, count 2 2006.239.08:18:21.72#ibcon#read 6, iclass 38, count 2 2006.239.08:18:21.72#ibcon#end of sib2, iclass 38, count 2 2006.239.08:18:21.72#ibcon#*after write, iclass 38, count 2 2006.239.08:18:21.72#ibcon#*before return 0, iclass 38, count 2 2006.239.08:18:21.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:21.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.239.08:18:21.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.239.08:18:21.72#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:21.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:21.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:21.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:21.84#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:18:21.84#ibcon#first serial, iclass 38, count 0 2006.239.08:18:21.84#ibcon#enter sib2, iclass 38, count 0 2006.239.08:18:21.84#ibcon#flushed, iclass 38, count 0 2006.239.08:18:21.84#ibcon#about to write, iclass 38, count 0 2006.239.08:18:21.84#ibcon#wrote, iclass 38, count 0 2006.239.08:18:21.84#ibcon#about to read 3, iclass 38, count 0 2006.239.08:18:21.86#ibcon#read 3, iclass 38, count 0 2006.239.08:18:21.86#ibcon#about to read 4, iclass 38, count 0 2006.239.08:18:21.86#ibcon#read 4, iclass 38, count 0 2006.239.08:18:21.86#ibcon#about to read 5, iclass 38, count 0 2006.239.08:18:21.86#ibcon#read 5, iclass 38, count 0 2006.239.08:18:21.86#ibcon#about to read 6, iclass 38, count 0 2006.239.08:18:21.86#ibcon#read 6, iclass 38, count 0 2006.239.08:18:21.86#ibcon#end of sib2, iclass 38, count 0 2006.239.08:18:21.86#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:18:21.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:18:21.86#ibcon#[27=USB\r\n] 2006.239.08:18:21.86#ibcon#*before write, iclass 38, count 0 2006.239.08:18:21.86#ibcon#enter sib2, iclass 38, count 0 2006.239.08:18:21.86#ibcon#flushed, iclass 38, count 0 2006.239.08:18:21.86#ibcon#about to write, iclass 38, count 0 2006.239.08:18:21.86#ibcon#wrote, iclass 38, count 0 2006.239.08:18:21.86#ibcon#about to read 3, iclass 38, count 0 2006.239.08:18:21.89#ibcon#read 3, iclass 38, count 0 2006.239.08:18:21.89#ibcon#about to read 4, iclass 38, count 0 2006.239.08:18:21.89#ibcon#read 4, iclass 38, count 0 2006.239.08:18:21.89#ibcon#about to read 5, iclass 38, count 0 2006.239.08:18:21.89#ibcon#read 5, iclass 38, count 0 2006.239.08:18:21.89#ibcon#about to read 6, iclass 38, count 0 2006.239.08:18:21.89#ibcon#read 6, iclass 38, count 0 2006.239.08:18:21.89#ibcon#end of sib2, iclass 38, count 0 2006.239.08:18:21.89#ibcon#*after write, iclass 38, count 0 2006.239.08:18:21.89#ibcon#*before return 0, iclass 38, count 0 2006.239.08:18:21.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:21.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.239.08:18:21.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:18:21.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:18:21.89$vc4f8/vblo=5,744.99 2006.239.08:18:21.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.08:18:21.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.08:18:21.89#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:21.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:21.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:21.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:21.89#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:18:21.89#ibcon#first serial, iclass 40, count 0 2006.239.08:18:21.89#ibcon#enter sib2, iclass 40, count 0 2006.239.08:18:21.89#ibcon#flushed, iclass 40, count 0 2006.239.08:18:21.89#ibcon#about to write, iclass 40, count 0 2006.239.08:18:21.89#ibcon#wrote, iclass 40, count 0 2006.239.08:18:21.89#ibcon#about to read 3, iclass 40, count 0 2006.239.08:18:21.91#ibcon#read 3, iclass 40, count 0 2006.239.08:18:21.91#ibcon#about to read 4, iclass 40, count 0 2006.239.08:18:21.91#ibcon#read 4, iclass 40, count 0 2006.239.08:18:21.91#ibcon#about to read 5, iclass 40, count 0 2006.239.08:18:21.91#ibcon#read 5, iclass 40, count 0 2006.239.08:18:21.91#ibcon#about to read 6, iclass 40, count 0 2006.239.08:18:21.91#ibcon#read 6, iclass 40, count 0 2006.239.08:18:21.91#ibcon#end of sib2, iclass 40, count 0 2006.239.08:18:21.91#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:18:21.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:18:21.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:18:21.91#ibcon#*before write, iclass 40, count 0 2006.239.08:18:21.91#ibcon#enter sib2, iclass 40, count 0 2006.239.08:18:21.91#ibcon#flushed, iclass 40, count 0 2006.239.08:18:21.91#ibcon#about to write, iclass 40, count 0 2006.239.08:18:21.91#ibcon#wrote, iclass 40, count 0 2006.239.08:18:21.91#ibcon#about to read 3, iclass 40, count 0 2006.239.08:18:21.95#ibcon#read 3, iclass 40, count 0 2006.239.08:18:21.95#ibcon#about to read 4, iclass 40, count 0 2006.239.08:18:21.95#ibcon#read 4, iclass 40, count 0 2006.239.08:18:21.95#ibcon#about to read 5, iclass 40, count 0 2006.239.08:18:21.95#ibcon#read 5, iclass 40, count 0 2006.239.08:18:21.95#ibcon#about to read 6, iclass 40, count 0 2006.239.08:18:21.95#ibcon#read 6, iclass 40, count 0 2006.239.08:18:21.95#ibcon#end of sib2, iclass 40, count 0 2006.239.08:18:21.95#ibcon#*after write, iclass 40, count 0 2006.239.08:18:21.95#ibcon#*before return 0, iclass 40, count 0 2006.239.08:18:21.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:21.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:18:21.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:18:21.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:18:21.95$vc4f8/vb=5,4 2006.239.08:18:21.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.239.08:18:21.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.239.08:18:21.95#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:21.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:22.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:22.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:22.01#ibcon#enter wrdev, iclass 4, count 2 2006.239.08:18:22.01#ibcon#first serial, iclass 4, count 2 2006.239.08:18:22.01#ibcon#enter sib2, iclass 4, count 2 2006.239.08:18:22.01#ibcon#flushed, iclass 4, count 2 2006.239.08:18:22.01#ibcon#about to write, iclass 4, count 2 2006.239.08:18:22.01#ibcon#wrote, iclass 4, count 2 2006.239.08:18:22.01#ibcon#about to read 3, iclass 4, count 2 2006.239.08:18:22.03#ibcon#read 3, iclass 4, count 2 2006.239.08:18:22.03#ibcon#about to read 4, iclass 4, count 2 2006.239.08:18:22.03#ibcon#read 4, iclass 4, count 2 2006.239.08:18:22.03#ibcon#about to read 5, iclass 4, count 2 2006.239.08:18:22.03#ibcon#read 5, iclass 4, count 2 2006.239.08:18:22.03#ibcon#about to read 6, iclass 4, count 2 2006.239.08:18:22.03#ibcon#read 6, iclass 4, count 2 2006.239.08:18:22.03#ibcon#end of sib2, iclass 4, count 2 2006.239.08:18:22.03#ibcon#*mode == 0, iclass 4, count 2 2006.239.08:18:22.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.239.08:18:22.03#ibcon#[27=AT05-04\r\n] 2006.239.08:18:22.03#ibcon#*before write, iclass 4, count 2 2006.239.08:18:22.03#ibcon#enter sib2, iclass 4, count 2 2006.239.08:18:22.03#ibcon#flushed, iclass 4, count 2 2006.239.08:18:22.03#ibcon#about to write, iclass 4, count 2 2006.239.08:18:22.03#ibcon#wrote, iclass 4, count 2 2006.239.08:18:22.03#ibcon#about to read 3, iclass 4, count 2 2006.239.08:18:22.06#ibcon#read 3, iclass 4, count 2 2006.239.08:18:22.06#ibcon#about to read 4, iclass 4, count 2 2006.239.08:18:22.06#ibcon#read 4, iclass 4, count 2 2006.239.08:18:22.06#ibcon#about to read 5, iclass 4, count 2 2006.239.08:18:22.06#ibcon#read 5, iclass 4, count 2 2006.239.08:18:22.06#ibcon#about to read 6, iclass 4, count 2 2006.239.08:18:22.06#ibcon#read 6, iclass 4, count 2 2006.239.08:18:22.06#ibcon#end of sib2, iclass 4, count 2 2006.239.08:18:22.06#ibcon#*after write, iclass 4, count 2 2006.239.08:18:22.06#ibcon#*before return 0, iclass 4, count 2 2006.239.08:18:22.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:22.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.239.08:18:22.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.239.08:18:22.06#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:22.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:22.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:22.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:22.18#ibcon#enter wrdev, iclass 4, count 0 2006.239.08:18:22.18#ibcon#first serial, iclass 4, count 0 2006.239.08:18:22.18#ibcon#enter sib2, iclass 4, count 0 2006.239.08:18:22.18#ibcon#flushed, iclass 4, count 0 2006.239.08:18:22.18#ibcon#about to write, iclass 4, count 0 2006.239.08:18:22.18#ibcon#wrote, iclass 4, count 0 2006.239.08:18:22.18#ibcon#about to read 3, iclass 4, count 0 2006.239.08:18:22.20#ibcon#read 3, iclass 4, count 0 2006.239.08:18:22.20#ibcon#about to read 4, iclass 4, count 0 2006.239.08:18:22.20#ibcon#read 4, iclass 4, count 0 2006.239.08:18:22.20#ibcon#about to read 5, iclass 4, count 0 2006.239.08:18:22.20#ibcon#read 5, iclass 4, count 0 2006.239.08:18:22.20#ibcon#about to read 6, iclass 4, count 0 2006.239.08:18:22.20#ibcon#read 6, iclass 4, count 0 2006.239.08:18:22.20#ibcon#end of sib2, iclass 4, count 0 2006.239.08:18:22.20#ibcon#*mode == 0, iclass 4, count 0 2006.239.08:18:22.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.239.08:18:22.20#ibcon#[27=USB\r\n] 2006.239.08:18:22.20#ibcon#*before write, iclass 4, count 0 2006.239.08:18:22.20#ibcon#enter sib2, iclass 4, count 0 2006.239.08:18:22.20#ibcon#flushed, iclass 4, count 0 2006.239.08:18:22.20#ibcon#about to write, iclass 4, count 0 2006.239.08:18:22.20#ibcon#wrote, iclass 4, count 0 2006.239.08:18:22.20#ibcon#about to read 3, iclass 4, count 0 2006.239.08:18:22.24#ibcon#read 3, iclass 4, count 0 2006.239.08:18:22.24#ibcon#about to read 4, iclass 4, count 0 2006.239.08:18:22.24#ibcon#read 4, iclass 4, count 0 2006.239.08:18:22.24#ibcon#about to read 5, iclass 4, count 0 2006.239.08:18:22.24#ibcon#read 5, iclass 4, count 0 2006.239.08:18:22.24#ibcon#about to read 6, iclass 4, count 0 2006.239.08:18:22.24#ibcon#read 6, iclass 4, count 0 2006.239.08:18:22.24#ibcon#end of sib2, iclass 4, count 0 2006.239.08:18:22.24#ibcon#*after write, iclass 4, count 0 2006.239.08:18:22.24#ibcon#*before return 0, iclass 4, count 0 2006.239.08:18:22.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:22.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.239.08:18:22.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.239.08:18:22.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.239.08:18:22.24$vc4f8/vblo=6,752.99 2006.239.08:18:22.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.239.08:18:22.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.239.08:18:22.24#ibcon#ireg 17 cls_cnt 0 2006.239.08:18:22.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:22.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:22.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:22.24#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:18:22.24#ibcon#first serial, iclass 6, count 0 2006.239.08:18:22.24#ibcon#enter sib2, iclass 6, count 0 2006.239.08:18:22.24#ibcon#flushed, iclass 6, count 0 2006.239.08:18:22.24#ibcon#about to write, iclass 6, count 0 2006.239.08:18:22.24#ibcon#wrote, iclass 6, count 0 2006.239.08:18:22.24#ibcon#about to read 3, iclass 6, count 0 2006.239.08:18:22.25#ibcon#read 3, iclass 6, count 0 2006.239.08:18:22.25#ibcon#about to read 4, iclass 6, count 0 2006.239.08:18:22.25#ibcon#read 4, iclass 6, count 0 2006.239.08:18:22.25#ibcon#about to read 5, iclass 6, count 0 2006.239.08:18:22.25#ibcon#read 5, iclass 6, count 0 2006.239.08:18:22.25#ibcon#about to read 6, iclass 6, count 0 2006.239.08:18:22.25#ibcon#read 6, iclass 6, count 0 2006.239.08:18:22.25#ibcon#end of sib2, iclass 6, count 0 2006.239.08:18:22.25#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:18:22.25#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:18:22.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:18:22.25#ibcon#*before write, iclass 6, count 0 2006.239.08:18:22.25#ibcon#enter sib2, iclass 6, count 0 2006.239.08:18:22.25#ibcon#flushed, iclass 6, count 0 2006.239.08:18:22.25#ibcon#about to write, iclass 6, count 0 2006.239.08:18:22.25#ibcon#wrote, iclass 6, count 0 2006.239.08:18:22.25#ibcon#about to read 3, iclass 6, count 0 2006.239.08:18:22.29#ibcon#read 3, iclass 6, count 0 2006.239.08:18:22.29#ibcon#about to read 4, iclass 6, count 0 2006.239.08:18:22.29#ibcon#read 4, iclass 6, count 0 2006.239.08:18:22.29#ibcon#about to read 5, iclass 6, count 0 2006.239.08:18:22.29#ibcon#read 5, iclass 6, count 0 2006.239.08:18:22.29#ibcon#about to read 6, iclass 6, count 0 2006.239.08:18:22.29#ibcon#read 6, iclass 6, count 0 2006.239.08:18:22.29#ibcon#end of sib2, iclass 6, count 0 2006.239.08:18:22.29#ibcon#*after write, iclass 6, count 0 2006.239.08:18:22.29#ibcon#*before return 0, iclass 6, count 0 2006.239.08:18:22.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:22.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.239.08:18:22.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:18:22.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:18:22.29$vc4f8/vb=6,4 2006.239.08:18:22.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.239.08:18:22.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.239.08:18:22.29#ibcon#ireg 11 cls_cnt 2 2006.239.08:18:22.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:22.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:22.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:22.36#ibcon#enter wrdev, iclass 10, count 2 2006.239.08:18:22.36#ibcon#first serial, iclass 10, count 2 2006.239.08:18:22.36#ibcon#enter sib2, iclass 10, count 2 2006.239.08:18:22.36#ibcon#flushed, iclass 10, count 2 2006.239.08:18:22.36#ibcon#about to write, iclass 10, count 2 2006.239.08:18:22.36#ibcon#wrote, iclass 10, count 2 2006.239.08:18:22.36#ibcon#about to read 3, iclass 10, count 2 2006.239.08:18:22.38#ibcon#read 3, iclass 10, count 2 2006.239.08:18:22.38#ibcon#about to read 4, iclass 10, count 2 2006.239.08:18:22.38#ibcon#read 4, iclass 10, count 2 2006.239.08:18:22.38#ibcon#about to read 5, iclass 10, count 2 2006.239.08:18:22.38#ibcon#read 5, iclass 10, count 2 2006.239.08:18:22.38#ibcon#about to read 6, iclass 10, count 2 2006.239.08:18:22.38#ibcon#read 6, iclass 10, count 2 2006.239.08:18:22.38#ibcon#end of sib2, iclass 10, count 2 2006.239.08:18:22.38#ibcon#*mode == 0, iclass 10, count 2 2006.239.08:18:22.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.239.08:18:22.38#ibcon#[27=AT06-04\r\n] 2006.239.08:18:22.38#ibcon#*before write, iclass 10, count 2 2006.239.08:18:22.38#ibcon#enter sib2, iclass 10, count 2 2006.239.08:18:22.38#ibcon#flushed, iclass 10, count 2 2006.239.08:18:22.38#ibcon#about to write, iclass 10, count 2 2006.239.08:18:22.38#ibcon#wrote, iclass 10, count 2 2006.239.08:18:22.38#ibcon#about to read 3, iclass 10, count 2 2006.239.08:18:22.41#ibcon#read 3, iclass 10, count 2 2006.239.08:18:22.41#ibcon#about to read 4, iclass 10, count 2 2006.239.08:18:22.41#ibcon#read 4, iclass 10, count 2 2006.239.08:18:22.41#ibcon#about to read 5, iclass 10, count 2 2006.239.08:18:22.41#ibcon#read 5, iclass 10, count 2 2006.239.08:18:22.41#ibcon#about to read 6, iclass 10, count 2 2006.239.08:18:22.41#ibcon#read 6, iclass 10, count 2 2006.239.08:18:22.41#ibcon#end of sib2, iclass 10, count 2 2006.239.08:18:22.41#ibcon#*after write, iclass 10, count 2 2006.239.08:18:22.41#ibcon#*before return 0, iclass 10, count 2 2006.239.08:18:22.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:22.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.239.08:18:22.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.239.08:18:22.41#ibcon#ireg 7 cls_cnt 0 2006.239.08:18:22.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:22.47#abcon#<5=/04 2.1 4.2 24.99 801011.5\r\n> 2006.239.08:18:22.49#abcon#{5=INTERFACE CLEAR} 2006.239.08:18:22.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:22.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:22.53#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:18:22.53#ibcon#first serial, iclass 10, count 0 2006.239.08:18:22.53#ibcon#enter sib2, iclass 10, count 0 2006.239.08:18:22.53#ibcon#flushed, iclass 10, count 0 2006.239.08:18:22.53#ibcon#about to write, iclass 10, count 0 2006.239.08:18:22.53#ibcon#wrote, iclass 10, count 0 2006.239.08:18:22.53#ibcon#about to read 3, iclass 10, count 0 2006.239.08:18:22.55#ibcon#read 3, iclass 10, count 0 2006.239.08:18:22.55#ibcon#about to read 4, iclass 10, count 0 2006.239.08:18:22.55#ibcon#read 4, iclass 10, count 0 2006.239.08:18:22.55#ibcon#about to read 5, iclass 10, count 0 2006.239.08:18:22.55#ibcon#read 5, iclass 10, count 0 2006.239.08:18:22.55#ibcon#about to read 6, iclass 10, count 0 2006.239.08:18:22.55#ibcon#read 6, iclass 10, count 0 2006.239.08:18:22.55#ibcon#end of sib2, iclass 10, count 0 2006.239.08:18:22.55#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:18:22.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:18:22.55#ibcon#[27=USB\r\n] 2006.239.08:18:22.55#ibcon#*before write, iclass 10, count 0 2006.239.08:18:22.55#ibcon#enter sib2, iclass 10, count 0 2006.239.08:18:22.55#ibcon#flushed, iclass 10, count 0 2006.239.08:18:22.55#ibcon#about to write, iclass 10, count 0 2006.239.08:18:22.55#ibcon#wrote, iclass 10, count 0 2006.239.08:18:22.55#ibcon#about to read 3, iclass 10, count 0 2006.239.08:18:22.55#abcon#[5=S1D000X0/0*\r\n] 2006.239.08:18:22.58#ibcon#read 3, iclass 10, count 0 2006.239.08:18:22.58#ibcon#about to read 4, iclass 10, count 0 2006.239.08:18:22.58#ibcon#read 4, iclass 10, count 0 2006.239.08:18:22.58#ibcon#about to read 5, iclass 10, count 0 2006.239.08:18:22.58#ibcon#read 5, iclass 10, count 0 2006.239.08:18:22.58#ibcon#about to read 6, iclass 10, count 0 2006.239.08:18:22.58#ibcon#read 6, iclass 10, count 0 2006.239.08:18:22.58#ibcon#end of sib2, iclass 10, count 0 2006.239.08:18:22.58#ibcon#*after write, iclass 10, count 0 2006.239.08:18:22.58#ibcon#*before return 0, iclass 10, count 0 2006.239.08:18:22.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:22.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.239.08:18:22.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:18:22.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:18:22.58$vc4f8/vabw=wide 2006.239.08:18:22.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.239.08:18:22.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.239.08:18:22.58#ibcon#ireg 8 cls_cnt 0 2006.239.08:18:22.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:22.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:22.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:22.58#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:18:22.58#ibcon#first serial, iclass 16, count 0 2006.239.08:18:22.58#ibcon#enter sib2, iclass 16, count 0 2006.239.08:18:22.58#ibcon#flushed, iclass 16, count 0 2006.239.08:18:22.58#ibcon#about to write, iclass 16, count 0 2006.239.08:18:22.58#ibcon#wrote, iclass 16, count 0 2006.239.08:18:22.58#ibcon#about to read 3, iclass 16, count 0 2006.239.08:18:22.60#ibcon#read 3, iclass 16, count 0 2006.239.08:18:22.60#ibcon#about to read 4, iclass 16, count 0 2006.239.08:18:22.60#ibcon#read 4, iclass 16, count 0 2006.239.08:18:22.60#ibcon#about to read 5, iclass 16, count 0 2006.239.08:18:22.60#ibcon#read 5, iclass 16, count 0 2006.239.08:18:22.60#ibcon#about to read 6, iclass 16, count 0 2006.239.08:18:22.60#ibcon#read 6, iclass 16, count 0 2006.239.08:18:22.60#ibcon#end of sib2, iclass 16, count 0 2006.239.08:18:22.60#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:18:22.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:18:22.60#ibcon#[25=BW32\r\n] 2006.239.08:18:22.60#ibcon#*before write, iclass 16, count 0 2006.239.08:18:22.60#ibcon#enter sib2, iclass 16, count 0 2006.239.08:18:22.60#ibcon#flushed, iclass 16, count 0 2006.239.08:18:22.60#ibcon#about to write, iclass 16, count 0 2006.239.08:18:22.60#ibcon#wrote, iclass 16, count 0 2006.239.08:18:22.60#ibcon#about to read 3, iclass 16, count 0 2006.239.08:18:22.63#ibcon#read 3, iclass 16, count 0 2006.239.08:18:22.63#ibcon#about to read 4, iclass 16, count 0 2006.239.08:18:22.63#ibcon#read 4, iclass 16, count 0 2006.239.08:18:22.63#ibcon#about to read 5, iclass 16, count 0 2006.239.08:18:22.63#ibcon#read 5, iclass 16, count 0 2006.239.08:18:22.63#ibcon#about to read 6, iclass 16, count 0 2006.239.08:18:22.63#ibcon#read 6, iclass 16, count 0 2006.239.08:18:22.63#ibcon#end of sib2, iclass 16, count 0 2006.239.08:18:22.63#ibcon#*after write, iclass 16, count 0 2006.239.08:18:22.63#ibcon#*before return 0, iclass 16, count 0 2006.239.08:18:22.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:22.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.239.08:18:22.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:18:22.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:18:22.63$vc4f8/vbbw=wide 2006.239.08:18:22.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:18:22.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:18:22.63#ibcon#ireg 8 cls_cnt 0 2006.239.08:18:22.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:18:22.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:18:22.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:18:22.70#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:18:22.70#ibcon#first serial, iclass 18, count 0 2006.239.08:18:22.70#ibcon#enter sib2, iclass 18, count 0 2006.239.08:18:22.70#ibcon#flushed, iclass 18, count 0 2006.239.08:18:22.70#ibcon#about to write, iclass 18, count 0 2006.239.08:18:22.70#ibcon#wrote, iclass 18, count 0 2006.239.08:18:22.70#ibcon#about to read 3, iclass 18, count 0 2006.239.08:18:22.72#ibcon#read 3, iclass 18, count 0 2006.239.08:18:22.72#ibcon#about to read 4, iclass 18, count 0 2006.239.08:18:22.72#ibcon#read 4, iclass 18, count 0 2006.239.08:18:22.72#ibcon#about to read 5, iclass 18, count 0 2006.239.08:18:22.72#ibcon#read 5, iclass 18, count 0 2006.239.08:18:22.72#ibcon#about to read 6, iclass 18, count 0 2006.239.08:18:22.72#ibcon#read 6, iclass 18, count 0 2006.239.08:18:22.72#ibcon#end of sib2, iclass 18, count 0 2006.239.08:18:22.72#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:18:22.72#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:18:22.72#ibcon#[27=BW32\r\n] 2006.239.08:18:22.72#ibcon#*before write, iclass 18, count 0 2006.239.08:18:22.72#ibcon#enter sib2, iclass 18, count 0 2006.239.08:18:22.72#ibcon#flushed, iclass 18, count 0 2006.239.08:18:22.72#ibcon#about to write, iclass 18, count 0 2006.239.08:18:22.72#ibcon#wrote, iclass 18, count 0 2006.239.08:18:22.72#ibcon#about to read 3, iclass 18, count 0 2006.239.08:18:22.75#ibcon#read 3, iclass 18, count 0 2006.239.08:18:22.75#ibcon#about to read 4, iclass 18, count 0 2006.239.08:18:22.75#ibcon#read 4, iclass 18, count 0 2006.239.08:18:22.75#ibcon#about to read 5, iclass 18, count 0 2006.239.08:18:22.75#ibcon#read 5, iclass 18, count 0 2006.239.08:18:22.75#ibcon#about to read 6, iclass 18, count 0 2006.239.08:18:22.75#ibcon#read 6, iclass 18, count 0 2006.239.08:18:22.75#ibcon#end of sib2, iclass 18, count 0 2006.239.08:18:22.75#ibcon#*after write, iclass 18, count 0 2006.239.08:18:22.75#ibcon#*before return 0, iclass 18, count 0 2006.239.08:18:22.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:18:22.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:18:22.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:18:22.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:18:22.75$4f8m12a/ifd4f 2006.239.08:18:22.75$ifd4f/lo= 2006.239.08:18:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:18:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:18:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:18:22.75$ifd4f/patch= 2006.239.08:18:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:18:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:18:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:18:22.75$4f8m12a/"form=m,16.000,1:2 2006.239.08:18:22.75$4f8m12a/"tpicd 2006.239.08:18:22.75$4f8m12a/echo=off 2006.239.08:18:22.75$4f8m12a/xlog=off 2006.239.08:18:22.76:!2006.239.08:20:00 2006.239.08:18:53.14#trakl#Source acquired 2006.239.08:18:55.14#flagr#flagr/antenna,acquired 2006.239.08:20:00.01:preob 2006.239.08:20:01.14/onsource/TRACKING 2006.239.08:20:01.14:!2006.239.08:20:10 2006.239.08:20:10.00:data_valid=on 2006.239.08:20:10.00:midob 2006.239.08:20:10.14/onsource/TRACKING 2006.239.08:20:10.14/wx/24.97,1011.5,80 2006.239.08:20:10.22/cable/+6.4154E-03 2006.239.08:20:11.31/va/01,08,usb,yes,37,39 2006.239.08:20:11.31/va/02,07,usb,yes,37,39 2006.239.08:20:11.31/va/03,07,usb,yes,35,35 2006.239.08:20:11.31/va/04,07,usb,yes,38,41 2006.239.08:20:11.31/va/05,08,usb,yes,36,38 2006.239.08:20:11.31/va/06,07,usb,yes,39,38 2006.239.08:20:11.31/va/07,07,usb,yes,38,38 2006.239.08:20:11.31/va/08,07,usb,yes,41,40 2006.239.08:20:11.54/valo/01,532.99,yes,locked 2006.239.08:20:11.54/valo/02,572.99,yes,locked 2006.239.08:20:11.54/valo/03,672.99,yes,locked 2006.239.08:20:11.54/valo/04,832.99,yes,locked 2006.239.08:20:11.54/valo/05,652.99,yes,locked 2006.239.08:20:11.54/valo/06,772.99,yes,locked 2006.239.08:20:11.54/valo/07,832.99,yes,locked 2006.239.08:20:11.54/valo/08,852.99,yes,locked 2006.239.08:20:12.63/vb/01,04,usb,yes,34,32 2006.239.08:20:12.63/vb/02,04,usb,yes,35,37 2006.239.08:20:12.63/vb/03,04,usb,yes,32,36 2006.239.08:20:12.63/vb/04,04,usb,yes,33,33 2006.239.08:20:12.63/vb/05,04,usb,yes,31,35 2006.239.08:20:12.63/vb/06,04,usb,yes,32,35 2006.239.08:20:12.63/vb/07,04,usb,yes,34,34 2006.239.08:20:12.63/vb/08,04,usb,yes,31,35 2006.239.08:20:12.87/vblo/01,632.99,yes,locked 2006.239.08:20:12.87/vblo/02,640.99,yes,locked 2006.239.08:20:12.87/vblo/03,656.99,yes,locked 2006.239.08:20:12.87/vblo/04,712.99,yes,locked 2006.239.08:20:12.87/vblo/05,744.99,yes,locked 2006.239.08:20:12.87/vblo/06,752.99,yes,locked 2006.239.08:20:12.87/vblo/07,734.99,yes,locked 2006.239.08:20:12.87/vblo/08,744.99,yes,locked 2006.239.08:20:13.02/vabw/8 2006.239.08:20:13.17/vbbw/8 2006.239.08:20:13.26/xfe/off,on,14.0 2006.239.08:20:13.63/ifatt/23,28,28,28 2006.239.08:20:14.07/fmout-gps/S +4.44E-07 2006.239.08:20:14.11:!2006.239.08:21:10 2006.239.08:21:10.01:data_valid=off 2006.239.08:21:10.02:postob 2006.239.08:21:10.18/cable/+6.4150E-03 2006.239.08:21:10.22/wx/24.96,1011.5,80 2006.239.08:21:11.08/fmout-gps/S +4.43E-07 2006.239.08:21:11.09:scan_name=239-0823,k06239,60 2006.239.08:21:11.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.239.08:21:12.14#flagr#flagr/antenna,new-source 2006.239.08:21:12.15:checkk5 2006.239.08:21:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:21:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:21:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:21:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:21:14.03/chk_obsdata//k5ts1/T2390820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:21:14.41/chk_obsdata//k5ts2/T2390820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:21:14.78/chk_obsdata//k5ts3/T2390820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:21:15.15/chk_obsdata//k5ts4/T2390820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:21:15.85/k5log//k5ts1_log_newline 2006.239.08:21:16.55/k5log//k5ts2_log_newline 2006.239.08:21:17.23/k5log//k5ts3_log_newline 2006.239.08:21:17.92/k5log//k5ts4_log_newline 2006.239.08:21:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:21:17.95:4f8m12a=3 2006.239.08:21:17.95$4f8m12a/echo=on 2006.239.08:21:17.95$4f8m12a/pcalon 2006.239.08:21:17.95$pcalon/"no phase cal control is implemented here 2006.239.08:21:17.95$4f8m12a/"tpicd=stop 2006.239.08:21:17.95$4f8m12a/vc4f8 2006.239.08:21:17.95$vc4f8/valo=1,532.99 2006.239.08:21:17.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.08:21:17.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.08:21:17.95#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:17.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:17.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:17.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:17.95#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:21:17.95#ibcon#first serial, iclass 17, count 0 2006.239.08:21:17.95#ibcon#enter sib2, iclass 17, count 0 2006.239.08:21:17.95#ibcon#flushed, iclass 17, count 0 2006.239.08:21:17.95#ibcon#about to write, iclass 17, count 0 2006.239.08:21:17.95#ibcon#wrote, iclass 17, count 0 2006.239.08:21:17.95#ibcon#about to read 3, iclass 17, count 0 2006.239.08:21:18.00#ibcon#read 3, iclass 17, count 0 2006.239.08:21:18.00#ibcon#about to read 4, iclass 17, count 0 2006.239.08:21:18.00#ibcon#read 4, iclass 17, count 0 2006.239.08:21:18.00#ibcon#about to read 5, iclass 17, count 0 2006.239.08:21:18.00#ibcon#read 5, iclass 17, count 0 2006.239.08:21:18.00#ibcon#about to read 6, iclass 17, count 0 2006.239.08:21:18.00#ibcon#read 6, iclass 17, count 0 2006.239.08:21:18.00#ibcon#end of sib2, iclass 17, count 0 2006.239.08:21:18.00#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:21:18.00#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:21:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:21:18.00#ibcon#*before write, iclass 17, count 0 2006.239.08:21:18.00#ibcon#enter sib2, iclass 17, count 0 2006.239.08:21:18.00#ibcon#flushed, iclass 17, count 0 2006.239.08:21:18.00#ibcon#about to write, iclass 17, count 0 2006.239.08:21:18.00#ibcon#wrote, iclass 17, count 0 2006.239.08:21:18.00#ibcon#about to read 3, iclass 17, count 0 2006.239.08:21:18.04#ibcon#read 3, iclass 17, count 0 2006.239.08:21:18.04#ibcon#about to read 4, iclass 17, count 0 2006.239.08:21:18.04#ibcon#read 4, iclass 17, count 0 2006.239.08:21:18.04#ibcon#about to read 5, iclass 17, count 0 2006.239.08:21:18.04#ibcon#read 5, iclass 17, count 0 2006.239.08:21:18.04#ibcon#about to read 6, iclass 17, count 0 2006.239.08:21:18.04#ibcon#read 6, iclass 17, count 0 2006.239.08:21:18.04#ibcon#end of sib2, iclass 17, count 0 2006.239.08:21:18.04#ibcon#*after write, iclass 17, count 0 2006.239.08:21:18.04#ibcon#*before return 0, iclass 17, count 0 2006.239.08:21:18.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:18.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:18.04#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:21:18.04#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:21:18.04$vc4f8/va=1,8 2006.239.08:21:18.04#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.08:21:18.04#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.08:21:18.04#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:18.04#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:18.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:18.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:18.04#ibcon#enter wrdev, iclass 19, count 2 2006.239.08:21:18.04#ibcon#first serial, iclass 19, count 2 2006.239.08:21:18.04#ibcon#enter sib2, iclass 19, count 2 2006.239.08:21:18.04#ibcon#flushed, iclass 19, count 2 2006.239.08:21:18.04#ibcon#about to write, iclass 19, count 2 2006.239.08:21:18.04#ibcon#wrote, iclass 19, count 2 2006.239.08:21:18.04#ibcon#about to read 3, iclass 19, count 2 2006.239.08:21:18.06#ibcon#read 3, iclass 19, count 2 2006.239.08:21:18.06#ibcon#about to read 4, iclass 19, count 2 2006.239.08:21:18.06#ibcon#read 4, iclass 19, count 2 2006.239.08:21:18.06#ibcon#about to read 5, iclass 19, count 2 2006.239.08:21:18.06#ibcon#read 5, iclass 19, count 2 2006.239.08:21:18.06#ibcon#about to read 6, iclass 19, count 2 2006.239.08:21:18.06#ibcon#read 6, iclass 19, count 2 2006.239.08:21:18.06#ibcon#end of sib2, iclass 19, count 2 2006.239.08:21:18.06#ibcon#*mode == 0, iclass 19, count 2 2006.239.08:21:18.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.08:21:18.06#ibcon#[25=AT01-08\r\n] 2006.239.08:21:18.06#ibcon#*before write, iclass 19, count 2 2006.239.08:21:18.06#ibcon#enter sib2, iclass 19, count 2 2006.239.08:21:18.06#ibcon#flushed, iclass 19, count 2 2006.239.08:21:18.06#ibcon#about to write, iclass 19, count 2 2006.239.08:21:18.06#ibcon#wrote, iclass 19, count 2 2006.239.08:21:18.06#ibcon#about to read 3, iclass 19, count 2 2006.239.08:21:18.10#ibcon#read 3, iclass 19, count 2 2006.239.08:21:18.10#ibcon#about to read 4, iclass 19, count 2 2006.239.08:21:18.10#ibcon#read 4, iclass 19, count 2 2006.239.08:21:18.10#ibcon#about to read 5, iclass 19, count 2 2006.239.08:21:18.10#ibcon#read 5, iclass 19, count 2 2006.239.08:21:18.10#ibcon#about to read 6, iclass 19, count 2 2006.239.08:21:18.10#ibcon#read 6, iclass 19, count 2 2006.239.08:21:18.10#ibcon#end of sib2, iclass 19, count 2 2006.239.08:21:18.10#ibcon#*after write, iclass 19, count 2 2006.239.08:21:18.10#ibcon#*before return 0, iclass 19, count 2 2006.239.08:21:18.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:18.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:18.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.08:21:18.10#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:18.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:18.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:18.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:18.21#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:21:18.21#ibcon#first serial, iclass 19, count 0 2006.239.08:21:18.21#ibcon#enter sib2, iclass 19, count 0 2006.239.08:21:18.21#ibcon#flushed, iclass 19, count 0 2006.239.08:21:18.21#ibcon#about to write, iclass 19, count 0 2006.239.08:21:18.21#ibcon#wrote, iclass 19, count 0 2006.239.08:21:18.21#ibcon#about to read 3, iclass 19, count 0 2006.239.08:21:18.23#ibcon#read 3, iclass 19, count 0 2006.239.08:21:18.23#ibcon#about to read 4, iclass 19, count 0 2006.239.08:21:18.23#ibcon#read 4, iclass 19, count 0 2006.239.08:21:18.23#ibcon#about to read 5, iclass 19, count 0 2006.239.08:21:18.23#ibcon#read 5, iclass 19, count 0 2006.239.08:21:18.23#ibcon#about to read 6, iclass 19, count 0 2006.239.08:21:18.23#ibcon#read 6, iclass 19, count 0 2006.239.08:21:18.23#ibcon#end of sib2, iclass 19, count 0 2006.239.08:21:18.23#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:21:18.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:21:18.23#ibcon#[25=USB\r\n] 2006.239.08:21:18.23#ibcon#*before write, iclass 19, count 0 2006.239.08:21:18.23#ibcon#enter sib2, iclass 19, count 0 2006.239.08:21:18.23#ibcon#flushed, iclass 19, count 0 2006.239.08:21:18.23#ibcon#about to write, iclass 19, count 0 2006.239.08:21:18.23#ibcon#wrote, iclass 19, count 0 2006.239.08:21:18.23#ibcon#about to read 3, iclass 19, count 0 2006.239.08:21:18.26#ibcon#read 3, iclass 19, count 0 2006.239.08:21:18.26#ibcon#about to read 4, iclass 19, count 0 2006.239.08:21:18.26#ibcon#read 4, iclass 19, count 0 2006.239.08:21:18.26#ibcon#about to read 5, iclass 19, count 0 2006.239.08:21:18.26#ibcon#read 5, iclass 19, count 0 2006.239.08:21:18.26#ibcon#about to read 6, iclass 19, count 0 2006.239.08:21:18.26#ibcon#read 6, iclass 19, count 0 2006.239.08:21:18.26#ibcon#end of sib2, iclass 19, count 0 2006.239.08:21:18.26#ibcon#*after write, iclass 19, count 0 2006.239.08:21:18.26#ibcon#*before return 0, iclass 19, count 0 2006.239.08:21:18.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:18.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:18.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:21:18.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:21:18.26$vc4f8/valo=2,572.99 2006.239.08:21:18.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:21:18.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:21:18.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:18.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:18.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:18.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:18.26#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:21:18.26#ibcon#first serial, iclass 21, count 0 2006.239.08:21:18.26#ibcon#enter sib2, iclass 21, count 0 2006.239.08:21:18.26#ibcon#flushed, iclass 21, count 0 2006.239.08:21:18.26#ibcon#about to write, iclass 21, count 0 2006.239.08:21:18.26#ibcon#wrote, iclass 21, count 0 2006.239.08:21:18.26#ibcon#about to read 3, iclass 21, count 0 2006.239.08:21:18.28#ibcon#read 3, iclass 21, count 0 2006.239.08:21:18.28#ibcon#about to read 4, iclass 21, count 0 2006.239.08:21:18.28#ibcon#read 4, iclass 21, count 0 2006.239.08:21:18.28#ibcon#about to read 5, iclass 21, count 0 2006.239.08:21:18.28#ibcon#read 5, iclass 21, count 0 2006.239.08:21:18.28#ibcon#about to read 6, iclass 21, count 0 2006.239.08:21:18.28#ibcon#read 6, iclass 21, count 0 2006.239.08:21:18.28#ibcon#end of sib2, iclass 21, count 0 2006.239.08:21:18.28#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:21:18.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:21:18.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:21:18.28#ibcon#*before write, iclass 21, count 0 2006.239.08:21:18.28#ibcon#enter sib2, iclass 21, count 0 2006.239.08:21:18.28#ibcon#flushed, iclass 21, count 0 2006.239.08:21:18.28#ibcon#about to write, iclass 21, count 0 2006.239.08:21:18.28#ibcon#wrote, iclass 21, count 0 2006.239.08:21:18.28#ibcon#about to read 3, iclass 21, count 0 2006.239.08:21:18.32#ibcon#read 3, iclass 21, count 0 2006.239.08:21:18.32#ibcon#about to read 4, iclass 21, count 0 2006.239.08:21:18.32#ibcon#read 4, iclass 21, count 0 2006.239.08:21:18.32#ibcon#about to read 5, iclass 21, count 0 2006.239.08:21:18.32#ibcon#read 5, iclass 21, count 0 2006.239.08:21:18.32#ibcon#about to read 6, iclass 21, count 0 2006.239.08:21:18.32#ibcon#read 6, iclass 21, count 0 2006.239.08:21:18.32#ibcon#end of sib2, iclass 21, count 0 2006.239.08:21:18.32#ibcon#*after write, iclass 21, count 0 2006.239.08:21:18.32#ibcon#*before return 0, iclass 21, count 0 2006.239.08:21:18.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:18.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:18.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:21:18.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:21:18.32$vc4f8/va=2,7 2006.239.08:21:18.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.08:21:18.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.08:21:18.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:18.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:18.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:18.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:18.38#ibcon#enter wrdev, iclass 23, count 2 2006.239.08:21:18.38#ibcon#first serial, iclass 23, count 2 2006.239.08:21:18.38#ibcon#enter sib2, iclass 23, count 2 2006.239.08:21:18.38#ibcon#flushed, iclass 23, count 2 2006.239.08:21:18.38#ibcon#about to write, iclass 23, count 2 2006.239.08:21:18.38#ibcon#wrote, iclass 23, count 2 2006.239.08:21:18.38#ibcon#about to read 3, iclass 23, count 2 2006.239.08:21:18.40#ibcon#read 3, iclass 23, count 2 2006.239.08:21:18.40#ibcon#about to read 4, iclass 23, count 2 2006.239.08:21:18.40#ibcon#read 4, iclass 23, count 2 2006.239.08:21:18.40#ibcon#about to read 5, iclass 23, count 2 2006.239.08:21:18.40#ibcon#read 5, iclass 23, count 2 2006.239.08:21:18.40#ibcon#about to read 6, iclass 23, count 2 2006.239.08:21:18.40#ibcon#read 6, iclass 23, count 2 2006.239.08:21:18.40#ibcon#end of sib2, iclass 23, count 2 2006.239.08:21:18.40#ibcon#*mode == 0, iclass 23, count 2 2006.239.08:21:18.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.08:21:18.40#ibcon#[25=AT02-07\r\n] 2006.239.08:21:18.40#ibcon#*before write, iclass 23, count 2 2006.239.08:21:18.40#ibcon#enter sib2, iclass 23, count 2 2006.239.08:21:18.40#ibcon#flushed, iclass 23, count 2 2006.239.08:21:18.40#ibcon#about to write, iclass 23, count 2 2006.239.08:21:18.40#ibcon#wrote, iclass 23, count 2 2006.239.08:21:18.40#ibcon#about to read 3, iclass 23, count 2 2006.239.08:21:18.43#ibcon#read 3, iclass 23, count 2 2006.239.08:21:18.43#ibcon#about to read 4, iclass 23, count 2 2006.239.08:21:18.43#ibcon#read 4, iclass 23, count 2 2006.239.08:21:18.43#ibcon#about to read 5, iclass 23, count 2 2006.239.08:21:18.43#ibcon#read 5, iclass 23, count 2 2006.239.08:21:18.43#ibcon#about to read 6, iclass 23, count 2 2006.239.08:21:18.43#ibcon#read 6, iclass 23, count 2 2006.239.08:21:18.43#ibcon#end of sib2, iclass 23, count 2 2006.239.08:21:18.43#ibcon#*after write, iclass 23, count 2 2006.239.08:21:18.43#ibcon#*before return 0, iclass 23, count 2 2006.239.08:21:18.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:18.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:18.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.08:21:18.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:18.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:18.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:18.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:18.55#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:21:18.55#ibcon#first serial, iclass 23, count 0 2006.239.08:21:18.55#ibcon#enter sib2, iclass 23, count 0 2006.239.08:21:18.55#ibcon#flushed, iclass 23, count 0 2006.239.08:21:18.55#ibcon#about to write, iclass 23, count 0 2006.239.08:21:18.55#ibcon#wrote, iclass 23, count 0 2006.239.08:21:18.55#ibcon#about to read 3, iclass 23, count 0 2006.239.08:21:18.57#ibcon#read 3, iclass 23, count 0 2006.239.08:21:18.57#ibcon#about to read 4, iclass 23, count 0 2006.239.08:21:18.57#ibcon#read 4, iclass 23, count 0 2006.239.08:21:18.57#ibcon#about to read 5, iclass 23, count 0 2006.239.08:21:18.57#ibcon#read 5, iclass 23, count 0 2006.239.08:21:18.57#ibcon#about to read 6, iclass 23, count 0 2006.239.08:21:18.57#ibcon#read 6, iclass 23, count 0 2006.239.08:21:18.57#ibcon#end of sib2, iclass 23, count 0 2006.239.08:21:18.57#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:21:18.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:21:18.57#ibcon#[25=USB\r\n] 2006.239.08:21:18.57#ibcon#*before write, iclass 23, count 0 2006.239.08:21:18.57#ibcon#enter sib2, iclass 23, count 0 2006.239.08:21:18.57#ibcon#flushed, iclass 23, count 0 2006.239.08:21:18.57#ibcon#about to write, iclass 23, count 0 2006.239.08:21:18.57#ibcon#wrote, iclass 23, count 0 2006.239.08:21:18.57#ibcon#about to read 3, iclass 23, count 0 2006.239.08:21:18.60#ibcon#read 3, iclass 23, count 0 2006.239.08:21:18.60#ibcon#about to read 4, iclass 23, count 0 2006.239.08:21:18.60#ibcon#read 4, iclass 23, count 0 2006.239.08:21:18.60#ibcon#about to read 5, iclass 23, count 0 2006.239.08:21:18.60#ibcon#read 5, iclass 23, count 0 2006.239.08:21:18.60#ibcon#about to read 6, iclass 23, count 0 2006.239.08:21:18.60#ibcon#read 6, iclass 23, count 0 2006.239.08:21:18.60#ibcon#end of sib2, iclass 23, count 0 2006.239.08:21:18.60#ibcon#*after write, iclass 23, count 0 2006.239.08:21:18.60#ibcon#*before return 0, iclass 23, count 0 2006.239.08:21:18.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:18.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:18.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:21:18.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:21:18.60$vc4f8/valo=3,672.99 2006.239.08:21:18.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.08:21:18.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.08:21:18.60#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:18.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:18.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:18.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:18.60#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:21:18.60#ibcon#first serial, iclass 25, count 0 2006.239.08:21:18.60#ibcon#enter sib2, iclass 25, count 0 2006.239.08:21:18.60#ibcon#flushed, iclass 25, count 0 2006.239.08:21:18.60#ibcon#about to write, iclass 25, count 0 2006.239.08:21:18.60#ibcon#wrote, iclass 25, count 0 2006.239.08:21:18.60#ibcon#about to read 3, iclass 25, count 0 2006.239.08:21:18.62#ibcon#read 3, iclass 25, count 0 2006.239.08:21:18.62#ibcon#about to read 4, iclass 25, count 0 2006.239.08:21:18.62#ibcon#read 4, iclass 25, count 0 2006.239.08:21:18.62#ibcon#about to read 5, iclass 25, count 0 2006.239.08:21:18.62#ibcon#read 5, iclass 25, count 0 2006.239.08:21:18.62#ibcon#about to read 6, iclass 25, count 0 2006.239.08:21:18.62#ibcon#read 6, iclass 25, count 0 2006.239.08:21:18.62#ibcon#end of sib2, iclass 25, count 0 2006.239.08:21:18.62#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:21:18.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:21:18.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:21:18.62#ibcon#*before write, iclass 25, count 0 2006.239.08:21:18.62#ibcon#enter sib2, iclass 25, count 0 2006.239.08:21:18.62#ibcon#flushed, iclass 25, count 0 2006.239.08:21:18.62#ibcon#about to write, iclass 25, count 0 2006.239.08:21:18.62#ibcon#wrote, iclass 25, count 0 2006.239.08:21:18.62#ibcon#about to read 3, iclass 25, count 0 2006.239.08:21:18.66#ibcon#read 3, iclass 25, count 0 2006.239.08:21:18.66#ibcon#about to read 4, iclass 25, count 0 2006.239.08:21:18.66#ibcon#read 4, iclass 25, count 0 2006.239.08:21:18.66#ibcon#about to read 5, iclass 25, count 0 2006.239.08:21:18.66#ibcon#read 5, iclass 25, count 0 2006.239.08:21:18.66#ibcon#about to read 6, iclass 25, count 0 2006.239.08:21:18.66#ibcon#read 6, iclass 25, count 0 2006.239.08:21:18.66#ibcon#end of sib2, iclass 25, count 0 2006.239.08:21:18.66#ibcon#*after write, iclass 25, count 0 2006.239.08:21:18.66#ibcon#*before return 0, iclass 25, count 0 2006.239.08:21:18.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:18.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:18.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:21:18.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:21:18.66$vc4f8/va=3,7 2006.239.08:21:18.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.08:21:18.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.08:21:18.66#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:18.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:18.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:18.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:18.72#ibcon#enter wrdev, iclass 27, count 2 2006.239.08:21:18.72#ibcon#first serial, iclass 27, count 2 2006.239.08:21:18.72#ibcon#enter sib2, iclass 27, count 2 2006.239.08:21:18.72#ibcon#flushed, iclass 27, count 2 2006.239.08:21:18.72#ibcon#about to write, iclass 27, count 2 2006.239.08:21:18.72#ibcon#wrote, iclass 27, count 2 2006.239.08:21:18.72#ibcon#about to read 3, iclass 27, count 2 2006.239.08:21:18.74#ibcon#read 3, iclass 27, count 2 2006.239.08:21:18.74#ibcon#about to read 4, iclass 27, count 2 2006.239.08:21:18.74#ibcon#read 4, iclass 27, count 2 2006.239.08:21:18.74#ibcon#about to read 5, iclass 27, count 2 2006.239.08:21:18.74#ibcon#read 5, iclass 27, count 2 2006.239.08:21:18.74#ibcon#about to read 6, iclass 27, count 2 2006.239.08:21:18.74#ibcon#read 6, iclass 27, count 2 2006.239.08:21:18.74#ibcon#end of sib2, iclass 27, count 2 2006.239.08:21:18.74#ibcon#*mode == 0, iclass 27, count 2 2006.239.08:21:18.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.08:21:18.74#ibcon#[25=AT03-07\r\n] 2006.239.08:21:18.74#ibcon#*before write, iclass 27, count 2 2006.239.08:21:18.74#ibcon#enter sib2, iclass 27, count 2 2006.239.08:21:18.74#ibcon#flushed, iclass 27, count 2 2006.239.08:21:18.74#ibcon#about to write, iclass 27, count 2 2006.239.08:21:18.74#ibcon#wrote, iclass 27, count 2 2006.239.08:21:18.74#ibcon#about to read 3, iclass 27, count 2 2006.239.08:21:18.77#ibcon#read 3, iclass 27, count 2 2006.239.08:21:18.77#ibcon#about to read 4, iclass 27, count 2 2006.239.08:21:18.77#ibcon#read 4, iclass 27, count 2 2006.239.08:21:18.77#ibcon#about to read 5, iclass 27, count 2 2006.239.08:21:18.77#ibcon#read 5, iclass 27, count 2 2006.239.08:21:18.77#ibcon#about to read 6, iclass 27, count 2 2006.239.08:21:18.77#ibcon#read 6, iclass 27, count 2 2006.239.08:21:18.77#ibcon#end of sib2, iclass 27, count 2 2006.239.08:21:18.77#ibcon#*after write, iclass 27, count 2 2006.239.08:21:18.77#ibcon#*before return 0, iclass 27, count 2 2006.239.08:21:18.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:18.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:18.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.08:21:18.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:18.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:18.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:18.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:18.89#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:21:18.89#ibcon#first serial, iclass 27, count 0 2006.239.08:21:18.89#ibcon#enter sib2, iclass 27, count 0 2006.239.08:21:18.89#ibcon#flushed, iclass 27, count 0 2006.239.08:21:18.89#ibcon#about to write, iclass 27, count 0 2006.239.08:21:18.89#ibcon#wrote, iclass 27, count 0 2006.239.08:21:18.89#ibcon#about to read 3, iclass 27, count 0 2006.239.08:21:18.91#ibcon#read 3, iclass 27, count 0 2006.239.08:21:18.91#ibcon#about to read 4, iclass 27, count 0 2006.239.08:21:18.91#ibcon#read 4, iclass 27, count 0 2006.239.08:21:18.91#ibcon#about to read 5, iclass 27, count 0 2006.239.08:21:18.91#ibcon#read 5, iclass 27, count 0 2006.239.08:21:18.91#ibcon#about to read 6, iclass 27, count 0 2006.239.08:21:18.91#ibcon#read 6, iclass 27, count 0 2006.239.08:21:18.91#ibcon#end of sib2, iclass 27, count 0 2006.239.08:21:18.91#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:21:18.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:21:18.91#ibcon#[25=USB\r\n] 2006.239.08:21:18.91#ibcon#*before write, iclass 27, count 0 2006.239.08:21:18.91#ibcon#enter sib2, iclass 27, count 0 2006.239.08:21:18.91#ibcon#flushed, iclass 27, count 0 2006.239.08:21:18.91#ibcon#about to write, iclass 27, count 0 2006.239.08:21:18.91#ibcon#wrote, iclass 27, count 0 2006.239.08:21:18.91#ibcon#about to read 3, iclass 27, count 0 2006.239.08:21:18.94#ibcon#read 3, iclass 27, count 0 2006.239.08:21:18.94#ibcon#about to read 4, iclass 27, count 0 2006.239.08:21:18.94#ibcon#read 4, iclass 27, count 0 2006.239.08:21:18.94#ibcon#about to read 5, iclass 27, count 0 2006.239.08:21:18.94#ibcon#read 5, iclass 27, count 0 2006.239.08:21:18.94#ibcon#about to read 6, iclass 27, count 0 2006.239.08:21:18.94#ibcon#read 6, iclass 27, count 0 2006.239.08:21:18.94#ibcon#end of sib2, iclass 27, count 0 2006.239.08:21:18.94#ibcon#*after write, iclass 27, count 0 2006.239.08:21:18.94#ibcon#*before return 0, iclass 27, count 0 2006.239.08:21:18.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:18.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:18.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:21:18.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:21:18.94$vc4f8/valo=4,832.99 2006.239.08:21:18.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.08:21:18.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.08:21:18.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:18.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:18.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:18.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:18.94#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:21:18.94#ibcon#first serial, iclass 29, count 0 2006.239.08:21:18.94#ibcon#enter sib2, iclass 29, count 0 2006.239.08:21:18.94#ibcon#flushed, iclass 29, count 0 2006.239.08:21:18.94#ibcon#about to write, iclass 29, count 0 2006.239.08:21:18.94#ibcon#wrote, iclass 29, count 0 2006.239.08:21:18.94#ibcon#about to read 3, iclass 29, count 0 2006.239.08:21:18.96#ibcon#read 3, iclass 29, count 0 2006.239.08:21:18.96#ibcon#about to read 4, iclass 29, count 0 2006.239.08:21:18.96#ibcon#read 4, iclass 29, count 0 2006.239.08:21:18.96#ibcon#about to read 5, iclass 29, count 0 2006.239.08:21:18.96#ibcon#read 5, iclass 29, count 0 2006.239.08:21:18.96#ibcon#about to read 6, iclass 29, count 0 2006.239.08:21:18.96#ibcon#read 6, iclass 29, count 0 2006.239.08:21:18.96#ibcon#end of sib2, iclass 29, count 0 2006.239.08:21:18.96#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:21:18.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:21:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:21:18.96#ibcon#*before write, iclass 29, count 0 2006.239.08:21:18.96#ibcon#enter sib2, iclass 29, count 0 2006.239.08:21:18.96#ibcon#flushed, iclass 29, count 0 2006.239.08:21:18.96#ibcon#about to write, iclass 29, count 0 2006.239.08:21:18.96#ibcon#wrote, iclass 29, count 0 2006.239.08:21:18.96#ibcon#about to read 3, iclass 29, count 0 2006.239.08:21:19.00#ibcon#read 3, iclass 29, count 0 2006.239.08:21:19.00#ibcon#about to read 4, iclass 29, count 0 2006.239.08:21:19.00#ibcon#read 4, iclass 29, count 0 2006.239.08:21:19.00#ibcon#about to read 5, iclass 29, count 0 2006.239.08:21:19.00#ibcon#read 5, iclass 29, count 0 2006.239.08:21:19.00#ibcon#about to read 6, iclass 29, count 0 2006.239.08:21:19.00#ibcon#read 6, iclass 29, count 0 2006.239.08:21:19.00#ibcon#end of sib2, iclass 29, count 0 2006.239.08:21:19.00#ibcon#*after write, iclass 29, count 0 2006.239.08:21:19.00#ibcon#*before return 0, iclass 29, count 0 2006.239.08:21:19.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:19.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:19.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:21:19.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:21:19.00$vc4f8/va=4,7 2006.239.08:21:19.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.08:21:19.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.08:21:19.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:19.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:19.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:19.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:19.06#ibcon#enter wrdev, iclass 31, count 2 2006.239.08:21:19.06#ibcon#first serial, iclass 31, count 2 2006.239.08:21:19.06#ibcon#enter sib2, iclass 31, count 2 2006.239.08:21:19.06#ibcon#flushed, iclass 31, count 2 2006.239.08:21:19.06#ibcon#about to write, iclass 31, count 2 2006.239.08:21:19.06#ibcon#wrote, iclass 31, count 2 2006.239.08:21:19.06#ibcon#about to read 3, iclass 31, count 2 2006.239.08:21:19.08#ibcon#read 3, iclass 31, count 2 2006.239.08:21:19.08#ibcon#about to read 4, iclass 31, count 2 2006.239.08:21:19.08#ibcon#read 4, iclass 31, count 2 2006.239.08:21:19.08#ibcon#about to read 5, iclass 31, count 2 2006.239.08:21:19.08#ibcon#read 5, iclass 31, count 2 2006.239.08:21:19.08#ibcon#about to read 6, iclass 31, count 2 2006.239.08:21:19.08#ibcon#read 6, iclass 31, count 2 2006.239.08:21:19.08#ibcon#end of sib2, iclass 31, count 2 2006.239.08:21:19.08#ibcon#*mode == 0, iclass 31, count 2 2006.239.08:21:19.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.08:21:19.08#ibcon#[25=AT04-07\r\n] 2006.239.08:21:19.08#ibcon#*before write, iclass 31, count 2 2006.239.08:21:19.08#ibcon#enter sib2, iclass 31, count 2 2006.239.08:21:19.08#ibcon#flushed, iclass 31, count 2 2006.239.08:21:19.08#ibcon#about to write, iclass 31, count 2 2006.239.08:21:19.08#ibcon#wrote, iclass 31, count 2 2006.239.08:21:19.08#ibcon#about to read 3, iclass 31, count 2 2006.239.08:21:19.11#ibcon#read 3, iclass 31, count 2 2006.239.08:21:19.11#ibcon#about to read 4, iclass 31, count 2 2006.239.08:21:19.11#ibcon#read 4, iclass 31, count 2 2006.239.08:21:19.11#ibcon#about to read 5, iclass 31, count 2 2006.239.08:21:19.11#ibcon#read 5, iclass 31, count 2 2006.239.08:21:19.11#ibcon#about to read 6, iclass 31, count 2 2006.239.08:21:19.11#ibcon#read 6, iclass 31, count 2 2006.239.08:21:19.11#ibcon#end of sib2, iclass 31, count 2 2006.239.08:21:19.11#ibcon#*after write, iclass 31, count 2 2006.239.08:21:19.11#ibcon#*before return 0, iclass 31, count 2 2006.239.08:21:19.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:19.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:19.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.08:21:19.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:19.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:19.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:19.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:19.23#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:21:19.23#ibcon#first serial, iclass 31, count 0 2006.239.08:21:19.23#ibcon#enter sib2, iclass 31, count 0 2006.239.08:21:19.23#ibcon#flushed, iclass 31, count 0 2006.239.08:21:19.23#ibcon#about to write, iclass 31, count 0 2006.239.08:21:19.23#ibcon#wrote, iclass 31, count 0 2006.239.08:21:19.23#ibcon#about to read 3, iclass 31, count 0 2006.239.08:21:19.25#ibcon#read 3, iclass 31, count 0 2006.239.08:21:19.25#ibcon#about to read 4, iclass 31, count 0 2006.239.08:21:19.25#ibcon#read 4, iclass 31, count 0 2006.239.08:21:19.25#ibcon#about to read 5, iclass 31, count 0 2006.239.08:21:19.25#ibcon#read 5, iclass 31, count 0 2006.239.08:21:19.25#ibcon#about to read 6, iclass 31, count 0 2006.239.08:21:19.25#ibcon#read 6, iclass 31, count 0 2006.239.08:21:19.25#ibcon#end of sib2, iclass 31, count 0 2006.239.08:21:19.25#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:21:19.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:21:19.25#ibcon#[25=USB\r\n] 2006.239.08:21:19.25#ibcon#*before write, iclass 31, count 0 2006.239.08:21:19.25#ibcon#enter sib2, iclass 31, count 0 2006.239.08:21:19.25#ibcon#flushed, iclass 31, count 0 2006.239.08:21:19.25#ibcon#about to write, iclass 31, count 0 2006.239.08:21:19.25#ibcon#wrote, iclass 31, count 0 2006.239.08:21:19.25#ibcon#about to read 3, iclass 31, count 0 2006.239.08:21:19.28#ibcon#read 3, iclass 31, count 0 2006.239.08:21:19.28#ibcon#about to read 4, iclass 31, count 0 2006.239.08:21:19.28#ibcon#read 4, iclass 31, count 0 2006.239.08:21:19.28#ibcon#about to read 5, iclass 31, count 0 2006.239.08:21:19.28#ibcon#read 5, iclass 31, count 0 2006.239.08:21:19.28#ibcon#about to read 6, iclass 31, count 0 2006.239.08:21:19.28#ibcon#read 6, iclass 31, count 0 2006.239.08:21:19.28#ibcon#end of sib2, iclass 31, count 0 2006.239.08:21:19.28#ibcon#*after write, iclass 31, count 0 2006.239.08:21:19.28#ibcon#*before return 0, iclass 31, count 0 2006.239.08:21:19.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:19.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:19.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:21:19.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:21:19.28$vc4f8/valo=5,652.99 2006.239.08:21:19.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.08:21:19.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.08:21:19.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:19.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:19.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:19.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:19.28#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:21:19.28#ibcon#first serial, iclass 33, count 0 2006.239.08:21:19.28#ibcon#enter sib2, iclass 33, count 0 2006.239.08:21:19.28#ibcon#flushed, iclass 33, count 0 2006.239.08:21:19.28#ibcon#about to write, iclass 33, count 0 2006.239.08:21:19.28#ibcon#wrote, iclass 33, count 0 2006.239.08:21:19.28#ibcon#about to read 3, iclass 33, count 0 2006.239.08:21:19.30#ibcon#read 3, iclass 33, count 0 2006.239.08:21:19.30#ibcon#about to read 4, iclass 33, count 0 2006.239.08:21:19.30#ibcon#read 4, iclass 33, count 0 2006.239.08:21:19.30#ibcon#about to read 5, iclass 33, count 0 2006.239.08:21:19.30#ibcon#read 5, iclass 33, count 0 2006.239.08:21:19.30#ibcon#about to read 6, iclass 33, count 0 2006.239.08:21:19.30#ibcon#read 6, iclass 33, count 0 2006.239.08:21:19.30#ibcon#end of sib2, iclass 33, count 0 2006.239.08:21:19.30#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:21:19.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:21:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:21:19.30#ibcon#*before write, iclass 33, count 0 2006.239.08:21:19.30#ibcon#enter sib2, iclass 33, count 0 2006.239.08:21:19.30#ibcon#flushed, iclass 33, count 0 2006.239.08:21:19.30#ibcon#about to write, iclass 33, count 0 2006.239.08:21:19.30#ibcon#wrote, iclass 33, count 0 2006.239.08:21:19.30#ibcon#about to read 3, iclass 33, count 0 2006.239.08:21:19.35#ibcon#read 3, iclass 33, count 0 2006.239.08:21:19.35#ibcon#about to read 4, iclass 33, count 0 2006.239.08:21:19.35#ibcon#read 4, iclass 33, count 0 2006.239.08:21:19.35#ibcon#about to read 5, iclass 33, count 0 2006.239.08:21:19.35#ibcon#read 5, iclass 33, count 0 2006.239.08:21:19.35#ibcon#about to read 6, iclass 33, count 0 2006.239.08:21:19.35#ibcon#read 6, iclass 33, count 0 2006.239.08:21:19.35#ibcon#end of sib2, iclass 33, count 0 2006.239.08:21:19.35#ibcon#*after write, iclass 33, count 0 2006.239.08:21:19.35#ibcon#*before return 0, iclass 33, count 0 2006.239.08:21:19.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:19.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:19.35#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:21:19.35#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:21:19.35$vc4f8/va=5,8 2006.239.08:21:19.35#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.08:21:19.35#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.08:21:19.35#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:19.35#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:19.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:19.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:19.39#ibcon#enter wrdev, iclass 35, count 2 2006.239.08:21:19.39#ibcon#first serial, iclass 35, count 2 2006.239.08:21:19.39#ibcon#enter sib2, iclass 35, count 2 2006.239.08:21:19.39#ibcon#flushed, iclass 35, count 2 2006.239.08:21:19.39#ibcon#about to write, iclass 35, count 2 2006.239.08:21:19.39#ibcon#wrote, iclass 35, count 2 2006.239.08:21:19.39#ibcon#about to read 3, iclass 35, count 2 2006.239.08:21:19.41#ibcon#read 3, iclass 35, count 2 2006.239.08:21:19.41#ibcon#about to read 4, iclass 35, count 2 2006.239.08:21:19.41#ibcon#read 4, iclass 35, count 2 2006.239.08:21:19.41#ibcon#about to read 5, iclass 35, count 2 2006.239.08:21:19.41#ibcon#read 5, iclass 35, count 2 2006.239.08:21:19.41#ibcon#about to read 6, iclass 35, count 2 2006.239.08:21:19.41#ibcon#read 6, iclass 35, count 2 2006.239.08:21:19.41#ibcon#end of sib2, iclass 35, count 2 2006.239.08:21:19.41#ibcon#*mode == 0, iclass 35, count 2 2006.239.08:21:19.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.08:21:19.41#ibcon#[25=AT05-08\r\n] 2006.239.08:21:19.41#ibcon#*before write, iclass 35, count 2 2006.239.08:21:19.41#ibcon#enter sib2, iclass 35, count 2 2006.239.08:21:19.41#ibcon#flushed, iclass 35, count 2 2006.239.08:21:19.41#ibcon#about to write, iclass 35, count 2 2006.239.08:21:19.41#ibcon#wrote, iclass 35, count 2 2006.239.08:21:19.41#ibcon#about to read 3, iclass 35, count 2 2006.239.08:21:19.44#ibcon#read 3, iclass 35, count 2 2006.239.08:21:19.44#ibcon#about to read 4, iclass 35, count 2 2006.239.08:21:19.44#ibcon#read 4, iclass 35, count 2 2006.239.08:21:19.44#ibcon#about to read 5, iclass 35, count 2 2006.239.08:21:19.44#ibcon#read 5, iclass 35, count 2 2006.239.08:21:19.44#ibcon#about to read 6, iclass 35, count 2 2006.239.08:21:19.44#ibcon#read 6, iclass 35, count 2 2006.239.08:21:19.44#ibcon#end of sib2, iclass 35, count 2 2006.239.08:21:19.44#ibcon#*after write, iclass 35, count 2 2006.239.08:21:19.44#ibcon#*before return 0, iclass 35, count 2 2006.239.08:21:19.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:19.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:19.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.08:21:19.44#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:19.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:19.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:19.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:19.56#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:21:19.56#ibcon#first serial, iclass 35, count 0 2006.239.08:21:19.56#ibcon#enter sib2, iclass 35, count 0 2006.239.08:21:19.56#ibcon#flushed, iclass 35, count 0 2006.239.08:21:19.56#ibcon#about to write, iclass 35, count 0 2006.239.08:21:19.56#ibcon#wrote, iclass 35, count 0 2006.239.08:21:19.56#ibcon#about to read 3, iclass 35, count 0 2006.239.08:21:19.58#ibcon#read 3, iclass 35, count 0 2006.239.08:21:19.58#ibcon#about to read 4, iclass 35, count 0 2006.239.08:21:19.58#ibcon#read 4, iclass 35, count 0 2006.239.08:21:19.58#ibcon#about to read 5, iclass 35, count 0 2006.239.08:21:19.58#ibcon#read 5, iclass 35, count 0 2006.239.08:21:19.58#ibcon#about to read 6, iclass 35, count 0 2006.239.08:21:19.58#ibcon#read 6, iclass 35, count 0 2006.239.08:21:19.58#ibcon#end of sib2, iclass 35, count 0 2006.239.08:21:19.58#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:21:19.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:21:19.58#ibcon#[25=USB\r\n] 2006.239.08:21:19.58#ibcon#*before write, iclass 35, count 0 2006.239.08:21:19.58#ibcon#enter sib2, iclass 35, count 0 2006.239.08:21:19.58#ibcon#flushed, iclass 35, count 0 2006.239.08:21:19.58#ibcon#about to write, iclass 35, count 0 2006.239.08:21:19.58#ibcon#wrote, iclass 35, count 0 2006.239.08:21:19.58#ibcon#about to read 3, iclass 35, count 0 2006.239.08:21:19.61#ibcon#read 3, iclass 35, count 0 2006.239.08:21:19.61#ibcon#about to read 4, iclass 35, count 0 2006.239.08:21:19.61#ibcon#read 4, iclass 35, count 0 2006.239.08:21:19.61#ibcon#about to read 5, iclass 35, count 0 2006.239.08:21:19.61#ibcon#read 5, iclass 35, count 0 2006.239.08:21:19.61#ibcon#about to read 6, iclass 35, count 0 2006.239.08:21:19.61#ibcon#read 6, iclass 35, count 0 2006.239.08:21:19.61#ibcon#end of sib2, iclass 35, count 0 2006.239.08:21:19.61#ibcon#*after write, iclass 35, count 0 2006.239.08:21:19.61#ibcon#*before return 0, iclass 35, count 0 2006.239.08:21:19.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:19.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:19.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:21:19.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:21:19.61$vc4f8/valo=6,772.99 2006.239.08:21:19.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.08:21:19.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.08:21:19.61#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:19.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:19.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:19.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:19.61#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:21:19.61#ibcon#first serial, iclass 37, count 0 2006.239.08:21:19.61#ibcon#enter sib2, iclass 37, count 0 2006.239.08:21:19.61#ibcon#flushed, iclass 37, count 0 2006.239.08:21:19.61#ibcon#about to write, iclass 37, count 0 2006.239.08:21:19.61#ibcon#wrote, iclass 37, count 0 2006.239.08:21:19.61#ibcon#about to read 3, iclass 37, count 0 2006.239.08:21:19.63#ibcon#read 3, iclass 37, count 0 2006.239.08:21:19.63#ibcon#about to read 4, iclass 37, count 0 2006.239.08:21:19.63#ibcon#read 4, iclass 37, count 0 2006.239.08:21:19.63#ibcon#about to read 5, iclass 37, count 0 2006.239.08:21:19.63#ibcon#read 5, iclass 37, count 0 2006.239.08:21:19.63#ibcon#about to read 6, iclass 37, count 0 2006.239.08:21:19.63#ibcon#read 6, iclass 37, count 0 2006.239.08:21:19.63#ibcon#end of sib2, iclass 37, count 0 2006.239.08:21:19.63#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:21:19.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:21:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:21:19.63#ibcon#*before write, iclass 37, count 0 2006.239.08:21:19.63#ibcon#enter sib2, iclass 37, count 0 2006.239.08:21:19.63#ibcon#flushed, iclass 37, count 0 2006.239.08:21:19.63#ibcon#about to write, iclass 37, count 0 2006.239.08:21:19.63#ibcon#wrote, iclass 37, count 0 2006.239.08:21:19.63#ibcon#about to read 3, iclass 37, count 0 2006.239.08:21:19.67#ibcon#read 3, iclass 37, count 0 2006.239.08:21:19.67#ibcon#about to read 4, iclass 37, count 0 2006.239.08:21:19.67#ibcon#read 4, iclass 37, count 0 2006.239.08:21:19.67#ibcon#about to read 5, iclass 37, count 0 2006.239.08:21:19.67#ibcon#read 5, iclass 37, count 0 2006.239.08:21:19.67#ibcon#about to read 6, iclass 37, count 0 2006.239.08:21:19.67#ibcon#read 6, iclass 37, count 0 2006.239.08:21:19.67#ibcon#end of sib2, iclass 37, count 0 2006.239.08:21:19.67#ibcon#*after write, iclass 37, count 0 2006.239.08:21:19.67#ibcon#*before return 0, iclass 37, count 0 2006.239.08:21:19.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:19.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:19.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:21:19.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:21:19.67$vc4f8/va=6,7 2006.239.08:21:19.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.239.08:21:19.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.239.08:21:19.67#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:19.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:21:19.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:21:19.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:21:19.73#ibcon#enter wrdev, iclass 39, count 2 2006.239.08:21:19.73#ibcon#first serial, iclass 39, count 2 2006.239.08:21:19.73#ibcon#enter sib2, iclass 39, count 2 2006.239.08:21:19.73#ibcon#flushed, iclass 39, count 2 2006.239.08:21:19.73#ibcon#about to write, iclass 39, count 2 2006.239.08:21:19.73#ibcon#wrote, iclass 39, count 2 2006.239.08:21:19.73#ibcon#about to read 3, iclass 39, count 2 2006.239.08:21:19.75#ibcon#read 3, iclass 39, count 2 2006.239.08:21:19.75#ibcon#about to read 4, iclass 39, count 2 2006.239.08:21:19.75#ibcon#read 4, iclass 39, count 2 2006.239.08:21:19.75#ibcon#about to read 5, iclass 39, count 2 2006.239.08:21:19.75#ibcon#read 5, iclass 39, count 2 2006.239.08:21:19.75#ibcon#about to read 6, iclass 39, count 2 2006.239.08:21:19.75#ibcon#read 6, iclass 39, count 2 2006.239.08:21:19.75#ibcon#end of sib2, iclass 39, count 2 2006.239.08:21:19.75#ibcon#*mode == 0, iclass 39, count 2 2006.239.08:21:19.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.239.08:21:19.75#ibcon#[25=AT06-07\r\n] 2006.239.08:21:19.75#ibcon#*before write, iclass 39, count 2 2006.239.08:21:19.75#ibcon#enter sib2, iclass 39, count 2 2006.239.08:21:19.75#ibcon#flushed, iclass 39, count 2 2006.239.08:21:19.75#ibcon#about to write, iclass 39, count 2 2006.239.08:21:19.75#ibcon#wrote, iclass 39, count 2 2006.239.08:21:19.75#ibcon#about to read 3, iclass 39, count 2 2006.239.08:21:19.78#ibcon#read 3, iclass 39, count 2 2006.239.08:21:19.78#ibcon#about to read 4, iclass 39, count 2 2006.239.08:21:19.78#ibcon#read 4, iclass 39, count 2 2006.239.08:21:19.78#ibcon#about to read 5, iclass 39, count 2 2006.239.08:21:19.78#ibcon#read 5, iclass 39, count 2 2006.239.08:21:19.78#ibcon#about to read 6, iclass 39, count 2 2006.239.08:21:19.78#ibcon#read 6, iclass 39, count 2 2006.239.08:21:19.78#ibcon#end of sib2, iclass 39, count 2 2006.239.08:21:19.78#ibcon#*after write, iclass 39, count 2 2006.239.08:21:19.78#ibcon#*before return 0, iclass 39, count 2 2006.239.08:21:19.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:21:19.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.239.08:21:19.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.239.08:21:19.78#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:19.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:21:19.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:21:19.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:21:19.90#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:21:19.90#ibcon#first serial, iclass 39, count 0 2006.239.08:21:19.90#ibcon#enter sib2, iclass 39, count 0 2006.239.08:21:19.90#ibcon#flushed, iclass 39, count 0 2006.239.08:21:19.90#ibcon#about to write, iclass 39, count 0 2006.239.08:21:19.90#ibcon#wrote, iclass 39, count 0 2006.239.08:21:19.90#ibcon#about to read 3, iclass 39, count 0 2006.239.08:21:19.92#ibcon#read 3, iclass 39, count 0 2006.239.08:21:19.92#ibcon#about to read 4, iclass 39, count 0 2006.239.08:21:19.92#ibcon#read 4, iclass 39, count 0 2006.239.08:21:19.92#ibcon#about to read 5, iclass 39, count 0 2006.239.08:21:19.92#ibcon#read 5, iclass 39, count 0 2006.239.08:21:19.92#ibcon#about to read 6, iclass 39, count 0 2006.239.08:21:19.92#ibcon#read 6, iclass 39, count 0 2006.239.08:21:19.92#ibcon#end of sib2, iclass 39, count 0 2006.239.08:21:19.92#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:21:19.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:21:19.92#ibcon#[25=USB\r\n] 2006.239.08:21:19.92#ibcon#*before write, iclass 39, count 0 2006.239.08:21:19.92#ibcon#enter sib2, iclass 39, count 0 2006.239.08:21:19.92#ibcon#flushed, iclass 39, count 0 2006.239.08:21:19.92#ibcon#about to write, iclass 39, count 0 2006.239.08:21:19.92#ibcon#wrote, iclass 39, count 0 2006.239.08:21:19.92#ibcon#about to read 3, iclass 39, count 0 2006.239.08:21:19.95#ibcon#read 3, iclass 39, count 0 2006.239.08:21:19.95#ibcon#about to read 4, iclass 39, count 0 2006.239.08:21:19.95#ibcon#read 4, iclass 39, count 0 2006.239.08:21:19.95#ibcon#about to read 5, iclass 39, count 0 2006.239.08:21:19.95#ibcon#read 5, iclass 39, count 0 2006.239.08:21:19.95#ibcon#about to read 6, iclass 39, count 0 2006.239.08:21:19.95#ibcon#read 6, iclass 39, count 0 2006.239.08:21:19.95#ibcon#end of sib2, iclass 39, count 0 2006.239.08:21:19.95#ibcon#*after write, iclass 39, count 0 2006.239.08:21:19.95#ibcon#*before return 0, iclass 39, count 0 2006.239.08:21:19.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:21:19.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.239.08:21:19.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:21:19.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:21:19.95$vc4f8/valo=7,832.99 2006.239.08:21:19.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.08:21:19.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.08:21:19.95#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:19.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:21:19.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:21:19.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:21:19.95#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:21:19.95#ibcon#first serial, iclass 3, count 0 2006.239.08:21:19.95#ibcon#enter sib2, iclass 3, count 0 2006.239.08:21:19.95#ibcon#flushed, iclass 3, count 0 2006.239.08:21:19.95#ibcon#about to write, iclass 3, count 0 2006.239.08:21:19.95#ibcon#wrote, iclass 3, count 0 2006.239.08:21:19.95#ibcon#about to read 3, iclass 3, count 0 2006.239.08:21:19.97#ibcon#read 3, iclass 3, count 0 2006.239.08:21:19.97#ibcon#about to read 4, iclass 3, count 0 2006.239.08:21:19.97#ibcon#read 4, iclass 3, count 0 2006.239.08:21:19.97#ibcon#about to read 5, iclass 3, count 0 2006.239.08:21:19.97#ibcon#read 5, iclass 3, count 0 2006.239.08:21:19.97#ibcon#about to read 6, iclass 3, count 0 2006.239.08:21:19.97#ibcon#read 6, iclass 3, count 0 2006.239.08:21:19.97#ibcon#end of sib2, iclass 3, count 0 2006.239.08:21:19.97#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:21:19.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:21:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:21:19.97#ibcon#*before write, iclass 3, count 0 2006.239.08:21:19.97#ibcon#enter sib2, iclass 3, count 0 2006.239.08:21:19.97#ibcon#flushed, iclass 3, count 0 2006.239.08:21:19.97#ibcon#about to write, iclass 3, count 0 2006.239.08:21:19.97#ibcon#wrote, iclass 3, count 0 2006.239.08:21:19.97#ibcon#about to read 3, iclass 3, count 0 2006.239.08:21:20.01#ibcon#read 3, iclass 3, count 0 2006.239.08:21:20.01#ibcon#about to read 4, iclass 3, count 0 2006.239.08:21:20.01#ibcon#read 4, iclass 3, count 0 2006.239.08:21:20.01#ibcon#about to read 5, iclass 3, count 0 2006.239.08:21:20.01#ibcon#read 5, iclass 3, count 0 2006.239.08:21:20.01#ibcon#about to read 6, iclass 3, count 0 2006.239.08:21:20.01#ibcon#read 6, iclass 3, count 0 2006.239.08:21:20.01#ibcon#end of sib2, iclass 3, count 0 2006.239.08:21:20.01#ibcon#*after write, iclass 3, count 0 2006.239.08:21:20.01#ibcon#*before return 0, iclass 3, count 0 2006.239.08:21:20.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:21:20.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:21:20.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:21:20.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:21:20.01$vc4f8/va=7,7 2006.239.08:21:20.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.239.08:21:20.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.239.08:21:20.01#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:20.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:21:20.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:21:20.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:21:20.07#ibcon#enter wrdev, iclass 5, count 2 2006.239.08:21:20.07#ibcon#first serial, iclass 5, count 2 2006.239.08:21:20.07#ibcon#enter sib2, iclass 5, count 2 2006.239.08:21:20.07#ibcon#flushed, iclass 5, count 2 2006.239.08:21:20.07#ibcon#about to write, iclass 5, count 2 2006.239.08:21:20.07#ibcon#wrote, iclass 5, count 2 2006.239.08:21:20.07#ibcon#about to read 3, iclass 5, count 2 2006.239.08:21:20.10#ibcon#read 3, iclass 5, count 2 2006.239.08:21:20.10#ibcon#about to read 4, iclass 5, count 2 2006.239.08:21:20.10#ibcon#read 4, iclass 5, count 2 2006.239.08:21:20.10#ibcon#about to read 5, iclass 5, count 2 2006.239.08:21:20.10#ibcon#read 5, iclass 5, count 2 2006.239.08:21:20.10#ibcon#about to read 6, iclass 5, count 2 2006.239.08:21:20.10#ibcon#read 6, iclass 5, count 2 2006.239.08:21:20.10#ibcon#end of sib2, iclass 5, count 2 2006.239.08:21:20.10#ibcon#*mode == 0, iclass 5, count 2 2006.239.08:21:20.10#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.239.08:21:20.10#ibcon#[25=AT07-07\r\n] 2006.239.08:21:20.10#ibcon#*before write, iclass 5, count 2 2006.239.08:21:20.10#ibcon#enter sib2, iclass 5, count 2 2006.239.08:21:20.10#ibcon#flushed, iclass 5, count 2 2006.239.08:21:20.10#ibcon#about to write, iclass 5, count 2 2006.239.08:21:20.10#ibcon#wrote, iclass 5, count 2 2006.239.08:21:20.10#ibcon#about to read 3, iclass 5, count 2 2006.239.08:21:20.13#ibcon#read 3, iclass 5, count 2 2006.239.08:21:20.13#ibcon#about to read 4, iclass 5, count 2 2006.239.08:21:20.13#ibcon#read 4, iclass 5, count 2 2006.239.08:21:20.13#ibcon#about to read 5, iclass 5, count 2 2006.239.08:21:20.13#ibcon#read 5, iclass 5, count 2 2006.239.08:21:20.13#ibcon#about to read 6, iclass 5, count 2 2006.239.08:21:20.13#ibcon#read 6, iclass 5, count 2 2006.239.08:21:20.13#ibcon#end of sib2, iclass 5, count 2 2006.239.08:21:20.13#ibcon#*after write, iclass 5, count 2 2006.239.08:21:20.13#ibcon#*before return 0, iclass 5, count 2 2006.239.08:21:20.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:21:20.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.239.08:21:20.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.239.08:21:20.13#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:20.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:21:20.25#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:21:20.25#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:21:20.25#ibcon#enter wrdev, iclass 5, count 0 2006.239.08:21:20.25#ibcon#first serial, iclass 5, count 0 2006.239.08:21:20.25#ibcon#enter sib2, iclass 5, count 0 2006.239.08:21:20.25#ibcon#flushed, iclass 5, count 0 2006.239.08:21:20.25#ibcon#about to write, iclass 5, count 0 2006.239.08:21:20.25#ibcon#wrote, iclass 5, count 0 2006.239.08:21:20.25#ibcon#about to read 3, iclass 5, count 0 2006.239.08:21:20.27#ibcon#read 3, iclass 5, count 0 2006.239.08:21:20.27#ibcon#about to read 4, iclass 5, count 0 2006.239.08:21:20.27#ibcon#read 4, iclass 5, count 0 2006.239.08:21:20.27#ibcon#about to read 5, iclass 5, count 0 2006.239.08:21:20.27#ibcon#read 5, iclass 5, count 0 2006.239.08:21:20.27#ibcon#about to read 6, iclass 5, count 0 2006.239.08:21:20.27#ibcon#read 6, iclass 5, count 0 2006.239.08:21:20.27#ibcon#end of sib2, iclass 5, count 0 2006.239.08:21:20.27#ibcon#*mode == 0, iclass 5, count 0 2006.239.08:21:20.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.239.08:21:20.27#ibcon#[25=USB\r\n] 2006.239.08:21:20.27#ibcon#*before write, iclass 5, count 0 2006.239.08:21:20.27#ibcon#enter sib2, iclass 5, count 0 2006.239.08:21:20.27#ibcon#flushed, iclass 5, count 0 2006.239.08:21:20.27#ibcon#about to write, iclass 5, count 0 2006.239.08:21:20.27#ibcon#wrote, iclass 5, count 0 2006.239.08:21:20.27#ibcon#about to read 3, iclass 5, count 0 2006.239.08:21:20.30#ibcon#read 3, iclass 5, count 0 2006.239.08:21:20.30#ibcon#about to read 4, iclass 5, count 0 2006.239.08:21:20.30#ibcon#read 4, iclass 5, count 0 2006.239.08:21:20.30#ibcon#about to read 5, iclass 5, count 0 2006.239.08:21:20.30#ibcon#read 5, iclass 5, count 0 2006.239.08:21:20.30#ibcon#about to read 6, iclass 5, count 0 2006.239.08:21:20.30#ibcon#read 6, iclass 5, count 0 2006.239.08:21:20.30#ibcon#end of sib2, iclass 5, count 0 2006.239.08:21:20.30#ibcon#*after write, iclass 5, count 0 2006.239.08:21:20.30#ibcon#*before return 0, iclass 5, count 0 2006.239.08:21:20.30#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:21:20.30#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.239.08:21:20.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.239.08:21:20.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.239.08:21:20.30$vc4f8/valo=8,852.99 2006.239.08:21:20.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.239.08:21:20.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.239.08:21:20.30#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:20.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:21:20.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:21:20.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:21:20.30#ibcon#enter wrdev, iclass 7, count 0 2006.239.08:21:20.30#ibcon#first serial, iclass 7, count 0 2006.239.08:21:20.30#ibcon#enter sib2, iclass 7, count 0 2006.239.08:21:20.30#ibcon#flushed, iclass 7, count 0 2006.239.08:21:20.30#ibcon#about to write, iclass 7, count 0 2006.239.08:21:20.30#ibcon#wrote, iclass 7, count 0 2006.239.08:21:20.30#ibcon#about to read 3, iclass 7, count 0 2006.239.08:21:20.32#ibcon#read 3, iclass 7, count 0 2006.239.08:21:20.32#ibcon#about to read 4, iclass 7, count 0 2006.239.08:21:20.32#ibcon#read 4, iclass 7, count 0 2006.239.08:21:20.32#ibcon#about to read 5, iclass 7, count 0 2006.239.08:21:20.32#ibcon#read 5, iclass 7, count 0 2006.239.08:21:20.32#ibcon#about to read 6, iclass 7, count 0 2006.239.08:21:20.32#ibcon#read 6, iclass 7, count 0 2006.239.08:21:20.32#ibcon#end of sib2, iclass 7, count 0 2006.239.08:21:20.32#ibcon#*mode == 0, iclass 7, count 0 2006.239.08:21:20.32#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.239.08:21:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:21:20.32#ibcon#*before write, iclass 7, count 0 2006.239.08:21:20.32#ibcon#enter sib2, iclass 7, count 0 2006.239.08:21:20.32#ibcon#flushed, iclass 7, count 0 2006.239.08:21:20.32#ibcon#about to write, iclass 7, count 0 2006.239.08:21:20.32#ibcon#wrote, iclass 7, count 0 2006.239.08:21:20.32#ibcon#about to read 3, iclass 7, count 0 2006.239.08:21:20.36#ibcon#read 3, iclass 7, count 0 2006.239.08:21:20.36#ibcon#about to read 4, iclass 7, count 0 2006.239.08:21:20.36#ibcon#read 4, iclass 7, count 0 2006.239.08:21:20.36#ibcon#about to read 5, iclass 7, count 0 2006.239.08:21:20.36#ibcon#read 5, iclass 7, count 0 2006.239.08:21:20.36#ibcon#about to read 6, iclass 7, count 0 2006.239.08:21:20.36#ibcon#read 6, iclass 7, count 0 2006.239.08:21:20.36#ibcon#end of sib2, iclass 7, count 0 2006.239.08:21:20.36#ibcon#*after write, iclass 7, count 0 2006.239.08:21:20.36#ibcon#*before return 0, iclass 7, count 0 2006.239.08:21:20.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:21:20.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.239.08:21:20.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.239.08:21:20.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.239.08:21:20.36$vc4f8/va=8,7 2006.239.08:21:20.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.239.08:21:20.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.239.08:21:20.36#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:20.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:21:20.42#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:21:20.42#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:21:20.42#ibcon#enter wrdev, iclass 11, count 2 2006.239.08:21:20.42#ibcon#first serial, iclass 11, count 2 2006.239.08:21:20.42#ibcon#enter sib2, iclass 11, count 2 2006.239.08:21:20.42#ibcon#flushed, iclass 11, count 2 2006.239.08:21:20.42#ibcon#about to write, iclass 11, count 2 2006.239.08:21:20.42#ibcon#wrote, iclass 11, count 2 2006.239.08:21:20.42#ibcon#about to read 3, iclass 11, count 2 2006.239.08:21:20.44#ibcon#read 3, iclass 11, count 2 2006.239.08:21:20.44#ibcon#about to read 4, iclass 11, count 2 2006.239.08:21:20.44#ibcon#read 4, iclass 11, count 2 2006.239.08:21:20.44#ibcon#about to read 5, iclass 11, count 2 2006.239.08:21:20.44#ibcon#read 5, iclass 11, count 2 2006.239.08:21:20.44#ibcon#about to read 6, iclass 11, count 2 2006.239.08:21:20.44#ibcon#read 6, iclass 11, count 2 2006.239.08:21:20.44#ibcon#end of sib2, iclass 11, count 2 2006.239.08:21:20.44#ibcon#*mode == 0, iclass 11, count 2 2006.239.08:21:20.44#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.239.08:21:20.44#ibcon#[25=AT08-07\r\n] 2006.239.08:21:20.44#ibcon#*before write, iclass 11, count 2 2006.239.08:21:20.44#ibcon#enter sib2, iclass 11, count 2 2006.239.08:21:20.44#ibcon#flushed, iclass 11, count 2 2006.239.08:21:20.44#ibcon#about to write, iclass 11, count 2 2006.239.08:21:20.44#ibcon#wrote, iclass 11, count 2 2006.239.08:21:20.44#ibcon#about to read 3, iclass 11, count 2 2006.239.08:21:20.47#ibcon#read 3, iclass 11, count 2 2006.239.08:21:20.47#ibcon#about to read 4, iclass 11, count 2 2006.239.08:21:20.47#ibcon#read 4, iclass 11, count 2 2006.239.08:21:20.47#ibcon#about to read 5, iclass 11, count 2 2006.239.08:21:20.47#ibcon#read 5, iclass 11, count 2 2006.239.08:21:20.47#ibcon#about to read 6, iclass 11, count 2 2006.239.08:21:20.47#ibcon#read 6, iclass 11, count 2 2006.239.08:21:20.47#ibcon#end of sib2, iclass 11, count 2 2006.239.08:21:20.47#ibcon#*after write, iclass 11, count 2 2006.239.08:21:20.47#ibcon#*before return 0, iclass 11, count 2 2006.239.08:21:20.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:21:20.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.239.08:21:20.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.239.08:21:20.47#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:20.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:21:20.59#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:21:20.59#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:21:20.59#ibcon#enter wrdev, iclass 11, count 0 2006.239.08:21:20.59#ibcon#first serial, iclass 11, count 0 2006.239.08:21:20.59#ibcon#enter sib2, iclass 11, count 0 2006.239.08:21:20.59#ibcon#flushed, iclass 11, count 0 2006.239.08:21:20.59#ibcon#about to write, iclass 11, count 0 2006.239.08:21:20.59#ibcon#wrote, iclass 11, count 0 2006.239.08:21:20.59#ibcon#about to read 3, iclass 11, count 0 2006.239.08:21:20.61#ibcon#read 3, iclass 11, count 0 2006.239.08:21:20.61#ibcon#about to read 4, iclass 11, count 0 2006.239.08:21:20.61#ibcon#read 4, iclass 11, count 0 2006.239.08:21:20.61#ibcon#about to read 5, iclass 11, count 0 2006.239.08:21:20.61#ibcon#read 5, iclass 11, count 0 2006.239.08:21:20.61#ibcon#about to read 6, iclass 11, count 0 2006.239.08:21:20.61#ibcon#read 6, iclass 11, count 0 2006.239.08:21:20.61#ibcon#end of sib2, iclass 11, count 0 2006.239.08:21:20.61#ibcon#*mode == 0, iclass 11, count 0 2006.239.08:21:20.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.239.08:21:20.61#ibcon#[25=USB\r\n] 2006.239.08:21:20.61#ibcon#*before write, iclass 11, count 0 2006.239.08:21:20.61#ibcon#enter sib2, iclass 11, count 0 2006.239.08:21:20.61#ibcon#flushed, iclass 11, count 0 2006.239.08:21:20.61#ibcon#about to write, iclass 11, count 0 2006.239.08:21:20.61#ibcon#wrote, iclass 11, count 0 2006.239.08:21:20.61#ibcon#about to read 3, iclass 11, count 0 2006.239.08:21:20.64#ibcon#read 3, iclass 11, count 0 2006.239.08:21:20.64#ibcon#about to read 4, iclass 11, count 0 2006.239.08:21:20.64#ibcon#read 4, iclass 11, count 0 2006.239.08:21:20.64#ibcon#about to read 5, iclass 11, count 0 2006.239.08:21:20.64#ibcon#read 5, iclass 11, count 0 2006.239.08:21:20.64#ibcon#about to read 6, iclass 11, count 0 2006.239.08:21:20.64#ibcon#read 6, iclass 11, count 0 2006.239.08:21:20.64#ibcon#end of sib2, iclass 11, count 0 2006.239.08:21:20.64#ibcon#*after write, iclass 11, count 0 2006.239.08:21:20.64#ibcon#*before return 0, iclass 11, count 0 2006.239.08:21:20.64#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:21:20.64#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.239.08:21:20.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.239.08:21:20.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.239.08:21:20.64$vc4f8/vblo=1,632.99 2006.239.08:21:20.64#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.239.08:21:20.64#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.239.08:21:20.64#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:20.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:21:20.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:21:20.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:21:20.64#ibcon#enter wrdev, iclass 13, count 0 2006.239.08:21:20.64#ibcon#first serial, iclass 13, count 0 2006.239.08:21:20.64#ibcon#enter sib2, iclass 13, count 0 2006.239.08:21:20.64#ibcon#flushed, iclass 13, count 0 2006.239.08:21:20.64#ibcon#about to write, iclass 13, count 0 2006.239.08:21:20.64#ibcon#wrote, iclass 13, count 0 2006.239.08:21:20.64#ibcon#about to read 3, iclass 13, count 0 2006.239.08:21:20.66#ibcon#read 3, iclass 13, count 0 2006.239.08:21:20.66#ibcon#about to read 4, iclass 13, count 0 2006.239.08:21:20.66#ibcon#read 4, iclass 13, count 0 2006.239.08:21:20.66#ibcon#about to read 5, iclass 13, count 0 2006.239.08:21:20.66#ibcon#read 5, iclass 13, count 0 2006.239.08:21:20.66#ibcon#about to read 6, iclass 13, count 0 2006.239.08:21:20.66#ibcon#read 6, iclass 13, count 0 2006.239.08:21:20.66#ibcon#end of sib2, iclass 13, count 0 2006.239.08:21:20.66#ibcon#*mode == 0, iclass 13, count 0 2006.239.08:21:20.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.239.08:21:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:21:20.66#ibcon#*before write, iclass 13, count 0 2006.239.08:21:20.66#ibcon#enter sib2, iclass 13, count 0 2006.239.08:21:20.66#ibcon#flushed, iclass 13, count 0 2006.239.08:21:20.66#ibcon#about to write, iclass 13, count 0 2006.239.08:21:20.66#ibcon#wrote, iclass 13, count 0 2006.239.08:21:20.66#ibcon#about to read 3, iclass 13, count 0 2006.239.08:21:20.70#ibcon#read 3, iclass 13, count 0 2006.239.08:21:20.70#ibcon#about to read 4, iclass 13, count 0 2006.239.08:21:20.70#ibcon#read 4, iclass 13, count 0 2006.239.08:21:20.70#ibcon#about to read 5, iclass 13, count 0 2006.239.08:21:20.70#ibcon#read 5, iclass 13, count 0 2006.239.08:21:20.70#ibcon#about to read 6, iclass 13, count 0 2006.239.08:21:20.70#ibcon#read 6, iclass 13, count 0 2006.239.08:21:20.70#ibcon#end of sib2, iclass 13, count 0 2006.239.08:21:20.70#ibcon#*after write, iclass 13, count 0 2006.239.08:21:20.70#ibcon#*before return 0, iclass 13, count 0 2006.239.08:21:20.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:21:20.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.239.08:21:20.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.239.08:21:20.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.239.08:21:20.70$vc4f8/vb=1,4 2006.239.08:21:20.70#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.239.08:21:20.70#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.239.08:21:20.70#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:20.70#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:21:20.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:21:20.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:21:20.70#ibcon#enter wrdev, iclass 15, count 2 2006.239.08:21:20.70#ibcon#first serial, iclass 15, count 2 2006.239.08:21:20.70#ibcon#enter sib2, iclass 15, count 2 2006.239.08:21:20.70#ibcon#flushed, iclass 15, count 2 2006.239.08:21:20.70#ibcon#about to write, iclass 15, count 2 2006.239.08:21:20.70#ibcon#wrote, iclass 15, count 2 2006.239.08:21:20.70#ibcon#about to read 3, iclass 15, count 2 2006.239.08:21:20.72#ibcon#read 3, iclass 15, count 2 2006.239.08:21:20.72#ibcon#about to read 4, iclass 15, count 2 2006.239.08:21:20.72#ibcon#read 4, iclass 15, count 2 2006.239.08:21:20.72#ibcon#about to read 5, iclass 15, count 2 2006.239.08:21:20.72#ibcon#read 5, iclass 15, count 2 2006.239.08:21:20.72#ibcon#about to read 6, iclass 15, count 2 2006.239.08:21:20.72#ibcon#read 6, iclass 15, count 2 2006.239.08:21:20.72#ibcon#end of sib2, iclass 15, count 2 2006.239.08:21:20.72#ibcon#*mode == 0, iclass 15, count 2 2006.239.08:21:20.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.239.08:21:20.72#ibcon#[27=AT01-04\r\n] 2006.239.08:21:20.72#ibcon#*before write, iclass 15, count 2 2006.239.08:21:20.72#ibcon#enter sib2, iclass 15, count 2 2006.239.08:21:20.72#ibcon#flushed, iclass 15, count 2 2006.239.08:21:20.72#ibcon#about to write, iclass 15, count 2 2006.239.08:21:20.72#ibcon#wrote, iclass 15, count 2 2006.239.08:21:20.72#ibcon#about to read 3, iclass 15, count 2 2006.239.08:21:20.75#ibcon#read 3, iclass 15, count 2 2006.239.08:21:20.75#ibcon#about to read 4, iclass 15, count 2 2006.239.08:21:20.75#ibcon#read 4, iclass 15, count 2 2006.239.08:21:20.75#ibcon#about to read 5, iclass 15, count 2 2006.239.08:21:20.75#ibcon#read 5, iclass 15, count 2 2006.239.08:21:20.75#ibcon#about to read 6, iclass 15, count 2 2006.239.08:21:20.75#ibcon#read 6, iclass 15, count 2 2006.239.08:21:20.75#ibcon#end of sib2, iclass 15, count 2 2006.239.08:21:20.75#ibcon#*after write, iclass 15, count 2 2006.239.08:21:20.75#ibcon#*before return 0, iclass 15, count 2 2006.239.08:21:20.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:21:20.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.239.08:21:20.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.239.08:21:20.75#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:20.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:21:20.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:21:20.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:21:20.87#ibcon#enter wrdev, iclass 15, count 0 2006.239.08:21:20.87#ibcon#first serial, iclass 15, count 0 2006.239.08:21:20.87#ibcon#enter sib2, iclass 15, count 0 2006.239.08:21:20.87#ibcon#flushed, iclass 15, count 0 2006.239.08:21:20.87#ibcon#about to write, iclass 15, count 0 2006.239.08:21:20.87#ibcon#wrote, iclass 15, count 0 2006.239.08:21:20.87#ibcon#about to read 3, iclass 15, count 0 2006.239.08:21:20.89#ibcon#read 3, iclass 15, count 0 2006.239.08:21:20.89#ibcon#about to read 4, iclass 15, count 0 2006.239.08:21:20.89#ibcon#read 4, iclass 15, count 0 2006.239.08:21:20.89#ibcon#about to read 5, iclass 15, count 0 2006.239.08:21:20.89#ibcon#read 5, iclass 15, count 0 2006.239.08:21:20.89#ibcon#about to read 6, iclass 15, count 0 2006.239.08:21:20.89#ibcon#read 6, iclass 15, count 0 2006.239.08:21:20.89#ibcon#end of sib2, iclass 15, count 0 2006.239.08:21:20.89#ibcon#*mode == 0, iclass 15, count 0 2006.239.08:21:20.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.239.08:21:20.89#ibcon#[27=USB\r\n] 2006.239.08:21:20.89#ibcon#*before write, iclass 15, count 0 2006.239.08:21:20.89#ibcon#enter sib2, iclass 15, count 0 2006.239.08:21:20.89#ibcon#flushed, iclass 15, count 0 2006.239.08:21:20.89#ibcon#about to write, iclass 15, count 0 2006.239.08:21:20.89#ibcon#wrote, iclass 15, count 0 2006.239.08:21:20.89#ibcon#about to read 3, iclass 15, count 0 2006.239.08:21:20.92#ibcon#read 3, iclass 15, count 0 2006.239.08:21:20.92#ibcon#about to read 4, iclass 15, count 0 2006.239.08:21:20.92#ibcon#read 4, iclass 15, count 0 2006.239.08:21:20.92#ibcon#about to read 5, iclass 15, count 0 2006.239.08:21:20.92#ibcon#read 5, iclass 15, count 0 2006.239.08:21:20.92#ibcon#about to read 6, iclass 15, count 0 2006.239.08:21:20.92#ibcon#read 6, iclass 15, count 0 2006.239.08:21:20.92#ibcon#end of sib2, iclass 15, count 0 2006.239.08:21:20.92#ibcon#*after write, iclass 15, count 0 2006.239.08:21:20.92#ibcon#*before return 0, iclass 15, count 0 2006.239.08:21:20.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:21:20.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.239.08:21:20.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.239.08:21:20.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.239.08:21:20.92$vc4f8/vblo=2,640.99 2006.239.08:21:20.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.239.08:21:20.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.239.08:21:20.92#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:20.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:20.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:20.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:20.92#ibcon#enter wrdev, iclass 17, count 0 2006.239.08:21:20.92#ibcon#first serial, iclass 17, count 0 2006.239.08:21:20.92#ibcon#enter sib2, iclass 17, count 0 2006.239.08:21:20.92#ibcon#flushed, iclass 17, count 0 2006.239.08:21:20.92#ibcon#about to write, iclass 17, count 0 2006.239.08:21:20.92#ibcon#wrote, iclass 17, count 0 2006.239.08:21:20.92#ibcon#about to read 3, iclass 17, count 0 2006.239.08:21:20.94#ibcon#read 3, iclass 17, count 0 2006.239.08:21:20.94#ibcon#about to read 4, iclass 17, count 0 2006.239.08:21:20.94#ibcon#read 4, iclass 17, count 0 2006.239.08:21:20.94#ibcon#about to read 5, iclass 17, count 0 2006.239.08:21:20.94#ibcon#read 5, iclass 17, count 0 2006.239.08:21:20.94#ibcon#about to read 6, iclass 17, count 0 2006.239.08:21:20.94#ibcon#read 6, iclass 17, count 0 2006.239.08:21:20.94#ibcon#end of sib2, iclass 17, count 0 2006.239.08:21:20.94#ibcon#*mode == 0, iclass 17, count 0 2006.239.08:21:20.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.239.08:21:20.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:21:20.94#ibcon#*before write, iclass 17, count 0 2006.239.08:21:20.94#ibcon#enter sib2, iclass 17, count 0 2006.239.08:21:20.94#ibcon#flushed, iclass 17, count 0 2006.239.08:21:20.94#ibcon#about to write, iclass 17, count 0 2006.239.08:21:20.94#ibcon#wrote, iclass 17, count 0 2006.239.08:21:20.94#ibcon#about to read 3, iclass 17, count 0 2006.239.08:21:20.98#ibcon#read 3, iclass 17, count 0 2006.239.08:21:20.98#ibcon#about to read 4, iclass 17, count 0 2006.239.08:21:20.98#ibcon#read 4, iclass 17, count 0 2006.239.08:21:20.98#ibcon#about to read 5, iclass 17, count 0 2006.239.08:21:20.98#ibcon#read 5, iclass 17, count 0 2006.239.08:21:20.98#ibcon#about to read 6, iclass 17, count 0 2006.239.08:21:20.98#ibcon#read 6, iclass 17, count 0 2006.239.08:21:20.98#ibcon#end of sib2, iclass 17, count 0 2006.239.08:21:20.98#ibcon#*after write, iclass 17, count 0 2006.239.08:21:20.98#ibcon#*before return 0, iclass 17, count 0 2006.239.08:21:20.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:20.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.239.08:21:20.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.239.08:21:20.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.239.08:21:20.98$vc4f8/vb=2,4 2006.239.08:21:20.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.239.08:21:20.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.239.08:21:20.98#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:20.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:21.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:21.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:21.04#ibcon#enter wrdev, iclass 19, count 2 2006.239.08:21:21.04#ibcon#first serial, iclass 19, count 2 2006.239.08:21:21.04#ibcon#enter sib2, iclass 19, count 2 2006.239.08:21:21.04#ibcon#flushed, iclass 19, count 2 2006.239.08:21:21.04#ibcon#about to write, iclass 19, count 2 2006.239.08:21:21.04#ibcon#wrote, iclass 19, count 2 2006.239.08:21:21.04#ibcon#about to read 3, iclass 19, count 2 2006.239.08:21:21.06#ibcon#read 3, iclass 19, count 2 2006.239.08:21:21.06#ibcon#about to read 4, iclass 19, count 2 2006.239.08:21:21.06#ibcon#read 4, iclass 19, count 2 2006.239.08:21:21.06#ibcon#about to read 5, iclass 19, count 2 2006.239.08:21:21.06#ibcon#read 5, iclass 19, count 2 2006.239.08:21:21.06#ibcon#about to read 6, iclass 19, count 2 2006.239.08:21:21.06#ibcon#read 6, iclass 19, count 2 2006.239.08:21:21.06#ibcon#end of sib2, iclass 19, count 2 2006.239.08:21:21.06#ibcon#*mode == 0, iclass 19, count 2 2006.239.08:21:21.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.239.08:21:21.06#ibcon#[27=AT02-04\r\n] 2006.239.08:21:21.06#ibcon#*before write, iclass 19, count 2 2006.239.08:21:21.06#ibcon#enter sib2, iclass 19, count 2 2006.239.08:21:21.06#ibcon#flushed, iclass 19, count 2 2006.239.08:21:21.06#ibcon#about to write, iclass 19, count 2 2006.239.08:21:21.06#ibcon#wrote, iclass 19, count 2 2006.239.08:21:21.06#ibcon#about to read 3, iclass 19, count 2 2006.239.08:21:21.09#ibcon#read 3, iclass 19, count 2 2006.239.08:21:21.09#ibcon#about to read 4, iclass 19, count 2 2006.239.08:21:21.09#ibcon#read 4, iclass 19, count 2 2006.239.08:21:21.09#ibcon#about to read 5, iclass 19, count 2 2006.239.08:21:21.09#ibcon#read 5, iclass 19, count 2 2006.239.08:21:21.09#ibcon#about to read 6, iclass 19, count 2 2006.239.08:21:21.09#ibcon#read 6, iclass 19, count 2 2006.239.08:21:21.09#ibcon#end of sib2, iclass 19, count 2 2006.239.08:21:21.09#ibcon#*after write, iclass 19, count 2 2006.239.08:21:21.09#ibcon#*before return 0, iclass 19, count 2 2006.239.08:21:21.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:21.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.239.08:21:21.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.239.08:21:21.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:21.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:21.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:21.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:21.21#ibcon#enter wrdev, iclass 19, count 0 2006.239.08:21:21.21#ibcon#first serial, iclass 19, count 0 2006.239.08:21:21.21#ibcon#enter sib2, iclass 19, count 0 2006.239.08:21:21.21#ibcon#flushed, iclass 19, count 0 2006.239.08:21:21.21#ibcon#about to write, iclass 19, count 0 2006.239.08:21:21.21#ibcon#wrote, iclass 19, count 0 2006.239.08:21:21.21#ibcon#about to read 3, iclass 19, count 0 2006.239.08:21:21.23#ibcon#read 3, iclass 19, count 0 2006.239.08:21:21.23#ibcon#about to read 4, iclass 19, count 0 2006.239.08:21:21.23#ibcon#read 4, iclass 19, count 0 2006.239.08:21:21.23#ibcon#about to read 5, iclass 19, count 0 2006.239.08:21:21.23#ibcon#read 5, iclass 19, count 0 2006.239.08:21:21.23#ibcon#about to read 6, iclass 19, count 0 2006.239.08:21:21.23#ibcon#read 6, iclass 19, count 0 2006.239.08:21:21.23#ibcon#end of sib2, iclass 19, count 0 2006.239.08:21:21.23#ibcon#*mode == 0, iclass 19, count 0 2006.239.08:21:21.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.239.08:21:21.23#ibcon#[27=USB\r\n] 2006.239.08:21:21.23#ibcon#*before write, iclass 19, count 0 2006.239.08:21:21.23#ibcon#enter sib2, iclass 19, count 0 2006.239.08:21:21.23#ibcon#flushed, iclass 19, count 0 2006.239.08:21:21.23#ibcon#about to write, iclass 19, count 0 2006.239.08:21:21.23#ibcon#wrote, iclass 19, count 0 2006.239.08:21:21.23#ibcon#about to read 3, iclass 19, count 0 2006.239.08:21:21.26#ibcon#read 3, iclass 19, count 0 2006.239.08:21:21.26#ibcon#about to read 4, iclass 19, count 0 2006.239.08:21:21.26#ibcon#read 4, iclass 19, count 0 2006.239.08:21:21.26#ibcon#about to read 5, iclass 19, count 0 2006.239.08:21:21.26#ibcon#read 5, iclass 19, count 0 2006.239.08:21:21.26#ibcon#about to read 6, iclass 19, count 0 2006.239.08:21:21.26#ibcon#read 6, iclass 19, count 0 2006.239.08:21:21.26#ibcon#end of sib2, iclass 19, count 0 2006.239.08:21:21.26#ibcon#*after write, iclass 19, count 0 2006.239.08:21:21.26#ibcon#*before return 0, iclass 19, count 0 2006.239.08:21:21.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:21.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.239.08:21:21.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.239.08:21:21.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.239.08:21:21.26$vc4f8/vblo=3,656.99 2006.239.08:21:21.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.239.08:21:21.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.239.08:21:21.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:21.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:21.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:21.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:21.26#ibcon#enter wrdev, iclass 21, count 0 2006.239.08:21:21.26#ibcon#first serial, iclass 21, count 0 2006.239.08:21:21.26#ibcon#enter sib2, iclass 21, count 0 2006.239.08:21:21.26#ibcon#flushed, iclass 21, count 0 2006.239.08:21:21.26#ibcon#about to write, iclass 21, count 0 2006.239.08:21:21.26#ibcon#wrote, iclass 21, count 0 2006.239.08:21:21.26#ibcon#about to read 3, iclass 21, count 0 2006.239.08:21:21.28#ibcon#read 3, iclass 21, count 0 2006.239.08:21:21.28#ibcon#about to read 4, iclass 21, count 0 2006.239.08:21:21.28#ibcon#read 4, iclass 21, count 0 2006.239.08:21:21.28#ibcon#about to read 5, iclass 21, count 0 2006.239.08:21:21.28#ibcon#read 5, iclass 21, count 0 2006.239.08:21:21.28#ibcon#about to read 6, iclass 21, count 0 2006.239.08:21:21.28#ibcon#read 6, iclass 21, count 0 2006.239.08:21:21.28#ibcon#end of sib2, iclass 21, count 0 2006.239.08:21:21.28#ibcon#*mode == 0, iclass 21, count 0 2006.239.08:21:21.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.239.08:21:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:21:21.28#ibcon#*before write, iclass 21, count 0 2006.239.08:21:21.28#ibcon#enter sib2, iclass 21, count 0 2006.239.08:21:21.28#ibcon#flushed, iclass 21, count 0 2006.239.08:21:21.28#ibcon#about to write, iclass 21, count 0 2006.239.08:21:21.28#ibcon#wrote, iclass 21, count 0 2006.239.08:21:21.28#ibcon#about to read 3, iclass 21, count 0 2006.239.08:21:21.32#ibcon#read 3, iclass 21, count 0 2006.239.08:21:21.32#ibcon#about to read 4, iclass 21, count 0 2006.239.08:21:21.32#ibcon#read 4, iclass 21, count 0 2006.239.08:21:21.32#ibcon#about to read 5, iclass 21, count 0 2006.239.08:21:21.32#ibcon#read 5, iclass 21, count 0 2006.239.08:21:21.32#ibcon#about to read 6, iclass 21, count 0 2006.239.08:21:21.32#ibcon#read 6, iclass 21, count 0 2006.239.08:21:21.32#ibcon#end of sib2, iclass 21, count 0 2006.239.08:21:21.32#ibcon#*after write, iclass 21, count 0 2006.239.08:21:21.32#ibcon#*before return 0, iclass 21, count 0 2006.239.08:21:21.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:21.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.239.08:21:21.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.239.08:21:21.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.239.08:21:21.32$vc4f8/vb=3,4 2006.239.08:21:21.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.239.08:21:21.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.239.08:21:21.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:21.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:21.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:21.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:21.38#ibcon#enter wrdev, iclass 23, count 2 2006.239.08:21:21.38#ibcon#first serial, iclass 23, count 2 2006.239.08:21:21.38#ibcon#enter sib2, iclass 23, count 2 2006.239.08:21:21.38#ibcon#flushed, iclass 23, count 2 2006.239.08:21:21.38#ibcon#about to write, iclass 23, count 2 2006.239.08:21:21.38#ibcon#wrote, iclass 23, count 2 2006.239.08:21:21.38#ibcon#about to read 3, iclass 23, count 2 2006.239.08:21:21.40#ibcon#read 3, iclass 23, count 2 2006.239.08:21:21.40#ibcon#about to read 4, iclass 23, count 2 2006.239.08:21:21.40#ibcon#read 4, iclass 23, count 2 2006.239.08:21:21.40#ibcon#about to read 5, iclass 23, count 2 2006.239.08:21:21.40#ibcon#read 5, iclass 23, count 2 2006.239.08:21:21.40#ibcon#about to read 6, iclass 23, count 2 2006.239.08:21:21.40#ibcon#read 6, iclass 23, count 2 2006.239.08:21:21.40#ibcon#end of sib2, iclass 23, count 2 2006.239.08:21:21.40#ibcon#*mode == 0, iclass 23, count 2 2006.239.08:21:21.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.239.08:21:21.40#ibcon#[27=AT03-04\r\n] 2006.239.08:21:21.40#ibcon#*before write, iclass 23, count 2 2006.239.08:21:21.40#ibcon#enter sib2, iclass 23, count 2 2006.239.08:21:21.40#ibcon#flushed, iclass 23, count 2 2006.239.08:21:21.40#ibcon#about to write, iclass 23, count 2 2006.239.08:21:21.40#ibcon#wrote, iclass 23, count 2 2006.239.08:21:21.40#ibcon#about to read 3, iclass 23, count 2 2006.239.08:21:21.44#ibcon#read 3, iclass 23, count 2 2006.239.08:21:21.44#ibcon#about to read 4, iclass 23, count 2 2006.239.08:21:21.44#ibcon#read 4, iclass 23, count 2 2006.239.08:21:21.44#ibcon#about to read 5, iclass 23, count 2 2006.239.08:21:21.44#ibcon#read 5, iclass 23, count 2 2006.239.08:21:21.44#ibcon#about to read 6, iclass 23, count 2 2006.239.08:21:21.44#ibcon#read 6, iclass 23, count 2 2006.239.08:21:21.44#ibcon#end of sib2, iclass 23, count 2 2006.239.08:21:21.44#ibcon#*after write, iclass 23, count 2 2006.239.08:21:21.44#ibcon#*before return 0, iclass 23, count 2 2006.239.08:21:21.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:21.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.239.08:21:21.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.239.08:21:21.44#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:21.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:21.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:21.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:21.55#ibcon#enter wrdev, iclass 23, count 0 2006.239.08:21:21.55#ibcon#first serial, iclass 23, count 0 2006.239.08:21:21.55#ibcon#enter sib2, iclass 23, count 0 2006.239.08:21:21.55#ibcon#flushed, iclass 23, count 0 2006.239.08:21:21.55#ibcon#about to write, iclass 23, count 0 2006.239.08:21:21.55#ibcon#wrote, iclass 23, count 0 2006.239.08:21:21.55#ibcon#about to read 3, iclass 23, count 0 2006.239.08:21:21.57#ibcon#read 3, iclass 23, count 0 2006.239.08:21:21.57#ibcon#about to read 4, iclass 23, count 0 2006.239.08:21:21.57#ibcon#read 4, iclass 23, count 0 2006.239.08:21:21.57#ibcon#about to read 5, iclass 23, count 0 2006.239.08:21:21.57#ibcon#read 5, iclass 23, count 0 2006.239.08:21:21.57#ibcon#about to read 6, iclass 23, count 0 2006.239.08:21:21.57#ibcon#read 6, iclass 23, count 0 2006.239.08:21:21.57#ibcon#end of sib2, iclass 23, count 0 2006.239.08:21:21.57#ibcon#*mode == 0, iclass 23, count 0 2006.239.08:21:21.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.239.08:21:21.57#ibcon#[27=USB\r\n] 2006.239.08:21:21.57#ibcon#*before write, iclass 23, count 0 2006.239.08:21:21.57#ibcon#enter sib2, iclass 23, count 0 2006.239.08:21:21.57#ibcon#flushed, iclass 23, count 0 2006.239.08:21:21.57#ibcon#about to write, iclass 23, count 0 2006.239.08:21:21.57#ibcon#wrote, iclass 23, count 0 2006.239.08:21:21.57#ibcon#about to read 3, iclass 23, count 0 2006.239.08:21:21.60#ibcon#read 3, iclass 23, count 0 2006.239.08:21:21.60#ibcon#about to read 4, iclass 23, count 0 2006.239.08:21:21.60#ibcon#read 4, iclass 23, count 0 2006.239.08:21:21.60#ibcon#about to read 5, iclass 23, count 0 2006.239.08:21:21.60#ibcon#read 5, iclass 23, count 0 2006.239.08:21:21.60#ibcon#about to read 6, iclass 23, count 0 2006.239.08:21:21.60#ibcon#read 6, iclass 23, count 0 2006.239.08:21:21.60#ibcon#end of sib2, iclass 23, count 0 2006.239.08:21:21.60#ibcon#*after write, iclass 23, count 0 2006.239.08:21:21.60#ibcon#*before return 0, iclass 23, count 0 2006.239.08:21:21.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:21.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.239.08:21:21.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.239.08:21:21.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.239.08:21:21.60$vc4f8/vblo=4,712.99 2006.239.08:21:21.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.239.08:21:21.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.239.08:21:21.60#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:21.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:21.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:21.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:21.60#ibcon#enter wrdev, iclass 25, count 0 2006.239.08:21:21.60#ibcon#first serial, iclass 25, count 0 2006.239.08:21:21.60#ibcon#enter sib2, iclass 25, count 0 2006.239.08:21:21.60#ibcon#flushed, iclass 25, count 0 2006.239.08:21:21.60#ibcon#about to write, iclass 25, count 0 2006.239.08:21:21.60#ibcon#wrote, iclass 25, count 0 2006.239.08:21:21.60#ibcon#about to read 3, iclass 25, count 0 2006.239.08:21:21.62#ibcon#read 3, iclass 25, count 0 2006.239.08:21:21.62#ibcon#about to read 4, iclass 25, count 0 2006.239.08:21:21.62#ibcon#read 4, iclass 25, count 0 2006.239.08:21:21.62#ibcon#about to read 5, iclass 25, count 0 2006.239.08:21:21.62#ibcon#read 5, iclass 25, count 0 2006.239.08:21:21.62#ibcon#about to read 6, iclass 25, count 0 2006.239.08:21:21.62#ibcon#read 6, iclass 25, count 0 2006.239.08:21:21.62#ibcon#end of sib2, iclass 25, count 0 2006.239.08:21:21.62#ibcon#*mode == 0, iclass 25, count 0 2006.239.08:21:21.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.239.08:21:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:21:21.62#ibcon#*before write, iclass 25, count 0 2006.239.08:21:21.62#ibcon#enter sib2, iclass 25, count 0 2006.239.08:21:21.62#ibcon#flushed, iclass 25, count 0 2006.239.08:21:21.62#ibcon#about to write, iclass 25, count 0 2006.239.08:21:21.62#ibcon#wrote, iclass 25, count 0 2006.239.08:21:21.62#ibcon#about to read 3, iclass 25, count 0 2006.239.08:21:21.66#ibcon#read 3, iclass 25, count 0 2006.239.08:21:21.66#ibcon#about to read 4, iclass 25, count 0 2006.239.08:21:21.66#ibcon#read 4, iclass 25, count 0 2006.239.08:21:21.66#ibcon#about to read 5, iclass 25, count 0 2006.239.08:21:21.66#ibcon#read 5, iclass 25, count 0 2006.239.08:21:21.66#ibcon#about to read 6, iclass 25, count 0 2006.239.08:21:21.66#ibcon#read 6, iclass 25, count 0 2006.239.08:21:21.66#ibcon#end of sib2, iclass 25, count 0 2006.239.08:21:21.66#ibcon#*after write, iclass 25, count 0 2006.239.08:21:21.66#ibcon#*before return 0, iclass 25, count 0 2006.239.08:21:21.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:21.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.239.08:21:21.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.239.08:21:21.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.239.08:21:21.66$vc4f8/vb=4,4 2006.239.08:21:21.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.239.08:21:21.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.239.08:21:21.66#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:21.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:21.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:21.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:21.72#ibcon#enter wrdev, iclass 27, count 2 2006.239.08:21:21.72#ibcon#first serial, iclass 27, count 2 2006.239.08:21:21.72#ibcon#enter sib2, iclass 27, count 2 2006.239.08:21:21.72#ibcon#flushed, iclass 27, count 2 2006.239.08:21:21.72#ibcon#about to write, iclass 27, count 2 2006.239.08:21:21.72#ibcon#wrote, iclass 27, count 2 2006.239.08:21:21.72#ibcon#about to read 3, iclass 27, count 2 2006.239.08:21:21.74#ibcon#read 3, iclass 27, count 2 2006.239.08:21:21.74#ibcon#about to read 4, iclass 27, count 2 2006.239.08:21:21.74#ibcon#read 4, iclass 27, count 2 2006.239.08:21:21.74#ibcon#about to read 5, iclass 27, count 2 2006.239.08:21:21.74#ibcon#read 5, iclass 27, count 2 2006.239.08:21:21.74#ibcon#about to read 6, iclass 27, count 2 2006.239.08:21:21.74#ibcon#read 6, iclass 27, count 2 2006.239.08:21:21.74#ibcon#end of sib2, iclass 27, count 2 2006.239.08:21:21.74#ibcon#*mode == 0, iclass 27, count 2 2006.239.08:21:21.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.239.08:21:21.74#ibcon#[27=AT04-04\r\n] 2006.239.08:21:21.74#ibcon#*before write, iclass 27, count 2 2006.239.08:21:21.74#ibcon#enter sib2, iclass 27, count 2 2006.239.08:21:21.74#ibcon#flushed, iclass 27, count 2 2006.239.08:21:21.74#ibcon#about to write, iclass 27, count 2 2006.239.08:21:21.74#ibcon#wrote, iclass 27, count 2 2006.239.08:21:21.74#ibcon#about to read 3, iclass 27, count 2 2006.239.08:21:21.77#ibcon#read 3, iclass 27, count 2 2006.239.08:21:21.77#ibcon#about to read 4, iclass 27, count 2 2006.239.08:21:21.77#ibcon#read 4, iclass 27, count 2 2006.239.08:21:21.77#ibcon#about to read 5, iclass 27, count 2 2006.239.08:21:21.77#ibcon#read 5, iclass 27, count 2 2006.239.08:21:21.77#ibcon#about to read 6, iclass 27, count 2 2006.239.08:21:21.77#ibcon#read 6, iclass 27, count 2 2006.239.08:21:21.77#ibcon#end of sib2, iclass 27, count 2 2006.239.08:21:21.77#ibcon#*after write, iclass 27, count 2 2006.239.08:21:21.77#ibcon#*before return 0, iclass 27, count 2 2006.239.08:21:21.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:21.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.239.08:21:21.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.239.08:21:21.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:21.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:21.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:21.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:21.89#ibcon#enter wrdev, iclass 27, count 0 2006.239.08:21:21.89#ibcon#first serial, iclass 27, count 0 2006.239.08:21:21.89#ibcon#enter sib2, iclass 27, count 0 2006.239.08:21:21.89#ibcon#flushed, iclass 27, count 0 2006.239.08:21:21.89#ibcon#about to write, iclass 27, count 0 2006.239.08:21:21.89#ibcon#wrote, iclass 27, count 0 2006.239.08:21:21.89#ibcon#about to read 3, iclass 27, count 0 2006.239.08:21:21.91#ibcon#read 3, iclass 27, count 0 2006.239.08:21:21.91#ibcon#about to read 4, iclass 27, count 0 2006.239.08:21:21.91#ibcon#read 4, iclass 27, count 0 2006.239.08:21:21.91#ibcon#about to read 5, iclass 27, count 0 2006.239.08:21:21.91#ibcon#read 5, iclass 27, count 0 2006.239.08:21:21.91#ibcon#about to read 6, iclass 27, count 0 2006.239.08:21:21.91#ibcon#read 6, iclass 27, count 0 2006.239.08:21:21.91#ibcon#end of sib2, iclass 27, count 0 2006.239.08:21:21.91#ibcon#*mode == 0, iclass 27, count 0 2006.239.08:21:21.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.239.08:21:21.91#ibcon#[27=USB\r\n] 2006.239.08:21:21.91#ibcon#*before write, iclass 27, count 0 2006.239.08:21:21.91#ibcon#enter sib2, iclass 27, count 0 2006.239.08:21:21.91#ibcon#flushed, iclass 27, count 0 2006.239.08:21:21.91#ibcon#about to write, iclass 27, count 0 2006.239.08:21:21.91#ibcon#wrote, iclass 27, count 0 2006.239.08:21:21.91#ibcon#about to read 3, iclass 27, count 0 2006.239.08:21:21.94#ibcon#read 3, iclass 27, count 0 2006.239.08:21:21.94#ibcon#about to read 4, iclass 27, count 0 2006.239.08:21:21.94#ibcon#read 4, iclass 27, count 0 2006.239.08:21:21.94#ibcon#about to read 5, iclass 27, count 0 2006.239.08:21:21.94#ibcon#read 5, iclass 27, count 0 2006.239.08:21:21.94#ibcon#about to read 6, iclass 27, count 0 2006.239.08:21:21.94#ibcon#read 6, iclass 27, count 0 2006.239.08:21:21.94#ibcon#end of sib2, iclass 27, count 0 2006.239.08:21:21.94#ibcon#*after write, iclass 27, count 0 2006.239.08:21:21.94#ibcon#*before return 0, iclass 27, count 0 2006.239.08:21:21.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:21.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.239.08:21:21.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.239.08:21:21.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.239.08:21:21.94$vc4f8/vblo=5,744.99 2006.239.08:21:21.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.239.08:21:21.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.239.08:21:21.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:21.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:21.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:21.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:21.94#ibcon#enter wrdev, iclass 29, count 0 2006.239.08:21:21.94#ibcon#first serial, iclass 29, count 0 2006.239.08:21:21.94#ibcon#enter sib2, iclass 29, count 0 2006.239.08:21:21.94#ibcon#flushed, iclass 29, count 0 2006.239.08:21:21.94#ibcon#about to write, iclass 29, count 0 2006.239.08:21:21.94#ibcon#wrote, iclass 29, count 0 2006.239.08:21:21.94#ibcon#about to read 3, iclass 29, count 0 2006.239.08:21:21.96#ibcon#read 3, iclass 29, count 0 2006.239.08:21:21.96#ibcon#about to read 4, iclass 29, count 0 2006.239.08:21:21.96#ibcon#read 4, iclass 29, count 0 2006.239.08:21:21.96#ibcon#about to read 5, iclass 29, count 0 2006.239.08:21:21.96#ibcon#read 5, iclass 29, count 0 2006.239.08:21:21.96#ibcon#about to read 6, iclass 29, count 0 2006.239.08:21:21.96#ibcon#read 6, iclass 29, count 0 2006.239.08:21:21.96#ibcon#end of sib2, iclass 29, count 0 2006.239.08:21:21.96#ibcon#*mode == 0, iclass 29, count 0 2006.239.08:21:21.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.239.08:21:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:21:21.96#ibcon#*before write, iclass 29, count 0 2006.239.08:21:21.96#ibcon#enter sib2, iclass 29, count 0 2006.239.08:21:21.96#ibcon#flushed, iclass 29, count 0 2006.239.08:21:21.96#ibcon#about to write, iclass 29, count 0 2006.239.08:21:21.96#ibcon#wrote, iclass 29, count 0 2006.239.08:21:21.96#ibcon#about to read 3, iclass 29, count 0 2006.239.08:21:22.00#ibcon#read 3, iclass 29, count 0 2006.239.08:21:22.00#ibcon#about to read 4, iclass 29, count 0 2006.239.08:21:22.00#ibcon#read 4, iclass 29, count 0 2006.239.08:21:22.00#ibcon#about to read 5, iclass 29, count 0 2006.239.08:21:22.00#ibcon#read 5, iclass 29, count 0 2006.239.08:21:22.00#ibcon#about to read 6, iclass 29, count 0 2006.239.08:21:22.00#ibcon#read 6, iclass 29, count 0 2006.239.08:21:22.00#ibcon#end of sib2, iclass 29, count 0 2006.239.08:21:22.00#ibcon#*after write, iclass 29, count 0 2006.239.08:21:22.00#ibcon#*before return 0, iclass 29, count 0 2006.239.08:21:22.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:22.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.239.08:21:22.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.239.08:21:22.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.239.08:21:22.00$vc4f8/vb=5,4 2006.239.08:21:22.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.239.08:21:22.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.239.08:21:22.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:22.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:22.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:22.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:22.06#ibcon#enter wrdev, iclass 31, count 2 2006.239.08:21:22.06#ibcon#first serial, iclass 31, count 2 2006.239.08:21:22.06#ibcon#enter sib2, iclass 31, count 2 2006.239.08:21:22.06#ibcon#flushed, iclass 31, count 2 2006.239.08:21:22.06#ibcon#about to write, iclass 31, count 2 2006.239.08:21:22.06#ibcon#wrote, iclass 31, count 2 2006.239.08:21:22.06#ibcon#about to read 3, iclass 31, count 2 2006.239.08:21:22.08#ibcon#read 3, iclass 31, count 2 2006.239.08:21:22.08#ibcon#about to read 4, iclass 31, count 2 2006.239.08:21:22.08#ibcon#read 4, iclass 31, count 2 2006.239.08:21:22.08#ibcon#about to read 5, iclass 31, count 2 2006.239.08:21:22.08#ibcon#read 5, iclass 31, count 2 2006.239.08:21:22.08#ibcon#about to read 6, iclass 31, count 2 2006.239.08:21:22.08#ibcon#read 6, iclass 31, count 2 2006.239.08:21:22.08#ibcon#end of sib2, iclass 31, count 2 2006.239.08:21:22.08#ibcon#*mode == 0, iclass 31, count 2 2006.239.08:21:22.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.239.08:21:22.08#ibcon#[27=AT05-04\r\n] 2006.239.08:21:22.08#ibcon#*before write, iclass 31, count 2 2006.239.08:21:22.08#ibcon#enter sib2, iclass 31, count 2 2006.239.08:21:22.08#ibcon#flushed, iclass 31, count 2 2006.239.08:21:22.08#ibcon#about to write, iclass 31, count 2 2006.239.08:21:22.08#ibcon#wrote, iclass 31, count 2 2006.239.08:21:22.08#ibcon#about to read 3, iclass 31, count 2 2006.239.08:21:22.11#ibcon#read 3, iclass 31, count 2 2006.239.08:21:22.11#ibcon#about to read 4, iclass 31, count 2 2006.239.08:21:22.11#ibcon#read 4, iclass 31, count 2 2006.239.08:21:22.11#ibcon#about to read 5, iclass 31, count 2 2006.239.08:21:22.11#ibcon#read 5, iclass 31, count 2 2006.239.08:21:22.11#ibcon#about to read 6, iclass 31, count 2 2006.239.08:21:22.11#ibcon#read 6, iclass 31, count 2 2006.239.08:21:22.11#ibcon#end of sib2, iclass 31, count 2 2006.239.08:21:22.11#ibcon#*after write, iclass 31, count 2 2006.239.08:21:22.11#ibcon#*before return 0, iclass 31, count 2 2006.239.08:21:22.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:22.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.239.08:21:22.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.239.08:21:22.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:22.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:22.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:22.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:22.23#ibcon#enter wrdev, iclass 31, count 0 2006.239.08:21:22.23#ibcon#first serial, iclass 31, count 0 2006.239.08:21:22.23#ibcon#enter sib2, iclass 31, count 0 2006.239.08:21:22.23#ibcon#flushed, iclass 31, count 0 2006.239.08:21:22.23#ibcon#about to write, iclass 31, count 0 2006.239.08:21:22.23#ibcon#wrote, iclass 31, count 0 2006.239.08:21:22.23#ibcon#about to read 3, iclass 31, count 0 2006.239.08:21:22.25#ibcon#read 3, iclass 31, count 0 2006.239.08:21:22.25#ibcon#about to read 4, iclass 31, count 0 2006.239.08:21:22.25#ibcon#read 4, iclass 31, count 0 2006.239.08:21:22.25#ibcon#about to read 5, iclass 31, count 0 2006.239.08:21:22.25#ibcon#read 5, iclass 31, count 0 2006.239.08:21:22.25#ibcon#about to read 6, iclass 31, count 0 2006.239.08:21:22.25#ibcon#read 6, iclass 31, count 0 2006.239.08:21:22.25#ibcon#end of sib2, iclass 31, count 0 2006.239.08:21:22.25#ibcon#*mode == 0, iclass 31, count 0 2006.239.08:21:22.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.239.08:21:22.25#ibcon#[27=USB\r\n] 2006.239.08:21:22.25#ibcon#*before write, iclass 31, count 0 2006.239.08:21:22.25#ibcon#enter sib2, iclass 31, count 0 2006.239.08:21:22.25#ibcon#flushed, iclass 31, count 0 2006.239.08:21:22.25#ibcon#about to write, iclass 31, count 0 2006.239.08:21:22.25#ibcon#wrote, iclass 31, count 0 2006.239.08:21:22.25#ibcon#about to read 3, iclass 31, count 0 2006.239.08:21:22.28#ibcon#read 3, iclass 31, count 0 2006.239.08:21:22.28#ibcon#about to read 4, iclass 31, count 0 2006.239.08:21:22.28#ibcon#read 4, iclass 31, count 0 2006.239.08:21:22.28#ibcon#about to read 5, iclass 31, count 0 2006.239.08:21:22.28#ibcon#read 5, iclass 31, count 0 2006.239.08:21:22.28#ibcon#about to read 6, iclass 31, count 0 2006.239.08:21:22.28#ibcon#read 6, iclass 31, count 0 2006.239.08:21:22.28#ibcon#end of sib2, iclass 31, count 0 2006.239.08:21:22.28#ibcon#*after write, iclass 31, count 0 2006.239.08:21:22.28#ibcon#*before return 0, iclass 31, count 0 2006.239.08:21:22.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:22.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.239.08:21:22.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.239.08:21:22.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.239.08:21:22.28$vc4f8/vblo=6,752.99 2006.239.08:21:22.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.239.08:21:22.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.239.08:21:22.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:21:22.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:22.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:22.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:22.28#ibcon#enter wrdev, iclass 33, count 0 2006.239.08:21:22.28#ibcon#first serial, iclass 33, count 0 2006.239.08:21:22.28#ibcon#enter sib2, iclass 33, count 0 2006.239.08:21:22.28#ibcon#flushed, iclass 33, count 0 2006.239.08:21:22.28#ibcon#about to write, iclass 33, count 0 2006.239.08:21:22.28#ibcon#wrote, iclass 33, count 0 2006.239.08:21:22.28#ibcon#about to read 3, iclass 33, count 0 2006.239.08:21:22.30#ibcon#read 3, iclass 33, count 0 2006.239.08:21:22.30#ibcon#about to read 4, iclass 33, count 0 2006.239.08:21:22.30#ibcon#read 4, iclass 33, count 0 2006.239.08:21:22.30#ibcon#about to read 5, iclass 33, count 0 2006.239.08:21:22.30#ibcon#read 5, iclass 33, count 0 2006.239.08:21:22.30#ibcon#about to read 6, iclass 33, count 0 2006.239.08:21:22.30#ibcon#read 6, iclass 33, count 0 2006.239.08:21:22.30#ibcon#end of sib2, iclass 33, count 0 2006.239.08:21:22.30#ibcon#*mode == 0, iclass 33, count 0 2006.239.08:21:22.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.239.08:21:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:21:22.30#ibcon#*before write, iclass 33, count 0 2006.239.08:21:22.30#ibcon#enter sib2, iclass 33, count 0 2006.239.08:21:22.30#ibcon#flushed, iclass 33, count 0 2006.239.08:21:22.30#ibcon#about to write, iclass 33, count 0 2006.239.08:21:22.30#ibcon#wrote, iclass 33, count 0 2006.239.08:21:22.30#ibcon#about to read 3, iclass 33, count 0 2006.239.08:21:22.34#ibcon#read 3, iclass 33, count 0 2006.239.08:21:22.34#ibcon#about to read 4, iclass 33, count 0 2006.239.08:21:22.34#ibcon#read 4, iclass 33, count 0 2006.239.08:21:22.34#ibcon#about to read 5, iclass 33, count 0 2006.239.08:21:22.34#ibcon#read 5, iclass 33, count 0 2006.239.08:21:22.34#ibcon#about to read 6, iclass 33, count 0 2006.239.08:21:22.34#ibcon#read 6, iclass 33, count 0 2006.239.08:21:22.34#ibcon#end of sib2, iclass 33, count 0 2006.239.08:21:22.34#ibcon#*after write, iclass 33, count 0 2006.239.08:21:22.34#ibcon#*before return 0, iclass 33, count 0 2006.239.08:21:22.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:22.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.239.08:21:22.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.239.08:21:22.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.239.08:21:22.34$vc4f8/vb=6,4 2006.239.08:21:22.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.239.08:21:22.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.239.08:21:22.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:21:22.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:22.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:22.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:22.40#ibcon#enter wrdev, iclass 35, count 2 2006.239.08:21:22.40#ibcon#first serial, iclass 35, count 2 2006.239.08:21:22.40#ibcon#enter sib2, iclass 35, count 2 2006.239.08:21:22.40#ibcon#flushed, iclass 35, count 2 2006.239.08:21:22.40#ibcon#about to write, iclass 35, count 2 2006.239.08:21:22.40#ibcon#wrote, iclass 35, count 2 2006.239.08:21:22.40#ibcon#about to read 3, iclass 35, count 2 2006.239.08:21:22.43#ibcon#read 3, iclass 35, count 2 2006.239.08:21:22.43#ibcon#about to read 4, iclass 35, count 2 2006.239.08:21:22.43#ibcon#read 4, iclass 35, count 2 2006.239.08:21:22.43#ibcon#about to read 5, iclass 35, count 2 2006.239.08:21:22.43#ibcon#read 5, iclass 35, count 2 2006.239.08:21:22.43#ibcon#about to read 6, iclass 35, count 2 2006.239.08:21:22.43#ibcon#read 6, iclass 35, count 2 2006.239.08:21:22.43#ibcon#end of sib2, iclass 35, count 2 2006.239.08:21:22.43#ibcon#*mode == 0, iclass 35, count 2 2006.239.08:21:22.43#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.239.08:21:22.43#ibcon#[27=AT06-04\r\n] 2006.239.08:21:22.43#ibcon#*before write, iclass 35, count 2 2006.239.08:21:22.43#ibcon#enter sib2, iclass 35, count 2 2006.239.08:21:22.43#ibcon#flushed, iclass 35, count 2 2006.239.08:21:22.43#ibcon#about to write, iclass 35, count 2 2006.239.08:21:22.43#ibcon#wrote, iclass 35, count 2 2006.239.08:21:22.43#ibcon#about to read 3, iclass 35, count 2 2006.239.08:21:22.46#ibcon#read 3, iclass 35, count 2 2006.239.08:21:22.46#ibcon#about to read 4, iclass 35, count 2 2006.239.08:21:22.46#ibcon#read 4, iclass 35, count 2 2006.239.08:21:22.46#ibcon#about to read 5, iclass 35, count 2 2006.239.08:21:22.46#ibcon#read 5, iclass 35, count 2 2006.239.08:21:22.46#ibcon#about to read 6, iclass 35, count 2 2006.239.08:21:22.46#ibcon#read 6, iclass 35, count 2 2006.239.08:21:22.46#ibcon#end of sib2, iclass 35, count 2 2006.239.08:21:22.46#ibcon#*after write, iclass 35, count 2 2006.239.08:21:22.46#ibcon#*before return 0, iclass 35, count 2 2006.239.08:21:22.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:22.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.239.08:21:22.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.239.08:21:22.46#ibcon#ireg 7 cls_cnt 0 2006.239.08:21:22.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:22.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:22.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:22.58#ibcon#enter wrdev, iclass 35, count 0 2006.239.08:21:22.58#ibcon#first serial, iclass 35, count 0 2006.239.08:21:22.58#ibcon#enter sib2, iclass 35, count 0 2006.239.08:21:22.58#ibcon#flushed, iclass 35, count 0 2006.239.08:21:22.58#ibcon#about to write, iclass 35, count 0 2006.239.08:21:22.58#ibcon#wrote, iclass 35, count 0 2006.239.08:21:22.58#ibcon#about to read 3, iclass 35, count 0 2006.239.08:21:22.60#ibcon#read 3, iclass 35, count 0 2006.239.08:21:22.60#ibcon#about to read 4, iclass 35, count 0 2006.239.08:21:22.60#ibcon#read 4, iclass 35, count 0 2006.239.08:21:22.60#ibcon#about to read 5, iclass 35, count 0 2006.239.08:21:22.60#ibcon#read 5, iclass 35, count 0 2006.239.08:21:22.60#ibcon#about to read 6, iclass 35, count 0 2006.239.08:21:22.60#ibcon#read 6, iclass 35, count 0 2006.239.08:21:22.60#ibcon#end of sib2, iclass 35, count 0 2006.239.08:21:22.60#ibcon#*mode == 0, iclass 35, count 0 2006.239.08:21:22.60#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.239.08:21:22.60#ibcon#[27=USB\r\n] 2006.239.08:21:22.60#ibcon#*before write, iclass 35, count 0 2006.239.08:21:22.60#ibcon#enter sib2, iclass 35, count 0 2006.239.08:21:22.60#ibcon#flushed, iclass 35, count 0 2006.239.08:21:22.60#ibcon#about to write, iclass 35, count 0 2006.239.08:21:22.60#ibcon#wrote, iclass 35, count 0 2006.239.08:21:22.60#ibcon#about to read 3, iclass 35, count 0 2006.239.08:21:22.63#ibcon#read 3, iclass 35, count 0 2006.239.08:21:22.63#ibcon#about to read 4, iclass 35, count 0 2006.239.08:21:22.63#ibcon#read 4, iclass 35, count 0 2006.239.08:21:22.63#ibcon#about to read 5, iclass 35, count 0 2006.239.08:21:22.63#ibcon#read 5, iclass 35, count 0 2006.239.08:21:22.63#ibcon#about to read 6, iclass 35, count 0 2006.239.08:21:22.63#ibcon#read 6, iclass 35, count 0 2006.239.08:21:22.63#ibcon#end of sib2, iclass 35, count 0 2006.239.08:21:22.63#ibcon#*after write, iclass 35, count 0 2006.239.08:21:22.63#ibcon#*before return 0, iclass 35, count 0 2006.239.08:21:22.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:22.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.239.08:21:22.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.239.08:21:22.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.239.08:21:22.63$vc4f8/vabw=wide 2006.239.08:21:22.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.239.08:21:22.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.239.08:21:22.63#ibcon#ireg 8 cls_cnt 0 2006.239.08:21:22.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:22.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:22.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:22.63#ibcon#enter wrdev, iclass 37, count 0 2006.239.08:21:22.63#ibcon#first serial, iclass 37, count 0 2006.239.08:21:22.63#ibcon#enter sib2, iclass 37, count 0 2006.239.08:21:22.63#ibcon#flushed, iclass 37, count 0 2006.239.08:21:22.63#ibcon#about to write, iclass 37, count 0 2006.239.08:21:22.63#ibcon#wrote, iclass 37, count 0 2006.239.08:21:22.63#ibcon#about to read 3, iclass 37, count 0 2006.239.08:21:22.65#ibcon#read 3, iclass 37, count 0 2006.239.08:21:22.65#ibcon#about to read 4, iclass 37, count 0 2006.239.08:21:22.65#ibcon#read 4, iclass 37, count 0 2006.239.08:21:22.65#ibcon#about to read 5, iclass 37, count 0 2006.239.08:21:22.65#ibcon#read 5, iclass 37, count 0 2006.239.08:21:22.65#ibcon#about to read 6, iclass 37, count 0 2006.239.08:21:22.65#ibcon#read 6, iclass 37, count 0 2006.239.08:21:22.65#ibcon#end of sib2, iclass 37, count 0 2006.239.08:21:22.65#ibcon#*mode == 0, iclass 37, count 0 2006.239.08:21:22.65#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.239.08:21:22.65#ibcon#[25=BW32\r\n] 2006.239.08:21:22.65#ibcon#*before write, iclass 37, count 0 2006.239.08:21:22.65#ibcon#enter sib2, iclass 37, count 0 2006.239.08:21:22.65#ibcon#flushed, iclass 37, count 0 2006.239.08:21:22.65#ibcon#about to write, iclass 37, count 0 2006.239.08:21:22.65#ibcon#wrote, iclass 37, count 0 2006.239.08:21:22.65#ibcon#about to read 3, iclass 37, count 0 2006.239.08:21:22.68#ibcon#read 3, iclass 37, count 0 2006.239.08:21:22.68#ibcon#about to read 4, iclass 37, count 0 2006.239.08:21:22.68#ibcon#read 4, iclass 37, count 0 2006.239.08:21:22.68#ibcon#about to read 5, iclass 37, count 0 2006.239.08:21:22.68#ibcon#read 5, iclass 37, count 0 2006.239.08:21:22.68#ibcon#about to read 6, iclass 37, count 0 2006.239.08:21:22.68#ibcon#read 6, iclass 37, count 0 2006.239.08:21:22.68#ibcon#end of sib2, iclass 37, count 0 2006.239.08:21:22.68#ibcon#*after write, iclass 37, count 0 2006.239.08:21:22.68#ibcon#*before return 0, iclass 37, count 0 2006.239.08:21:22.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:22.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.239.08:21:22.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.239.08:21:22.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.239.08:21:22.68$vc4f8/vbbw=wide 2006.239.08:21:22.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.239.08:21:22.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.239.08:21:22.68#ibcon#ireg 8 cls_cnt 0 2006.239.08:21:22.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:21:22.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:21:22.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:21:22.75#ibcon#enter wrdev, iclass 39, count 0 2006.239.08:21:22.75#ibcon#first serial, iclass 39, count 0 2006.239.08:21:22.75#ibcon#enter sib2, iclass 39, count 0 2006.239.08:21:22.75#ibcon#flushed, iclass 39, count 0 2006.239.08:21:22.75#ibcon#about to write, iclass 39, count 0 2006.239.08:21:22.75#ibcon#wrote, iclass 39, count 0 2006.239.08:21:22.75#ibcon#about to read 3, iclass 39, count 0 2006.239.08:21:22.77#ibcon#read 3, iclass 39, count 0 2006.239.08:21:22.77#ibcon#about to read 4, iclass 39, count 0 2006.239.08:21:22.77#ibcon#read 4, iclass 39, count 0 2006.239.08:21:22.77#ibcon#about to read 5, iclass 39, count 0 2006.239.08:21:22.77#ibcon#read 5, iclass 39, count 0 2006.239.08:21:22.77#ibcon#about to read 6, iclass 39, count 0 2006.239.08:21:22.77#ibcon#read 6, iclass 39, count 0 2006.239.08:21:22.77#ibcon#end of sib2, iclass 39, count 0 2006.239.08:21:22.77#ibcon#*mode == 0, iclass 39, count 0 2006.239.08:21:22.77#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.239.08:21:22.77#ibcon#[27=BW32\r\n] 2006.239.08:21:22.77#ibcon#*before write, iclass 39, count 0 2006.239.08:21:22.77#ibcon#enter sib2, iclass 39, count 0 2006.239.08:21:22.77#ibcon#flushed, iclass 39, count 0 2006.239.08:21:22.77#ibcon#about to write, iclass 39, count 0 2006.239.08:21:22.77#ibcon#wrote, iclass 39, count 0 2006.239.08:21:22.77#ibcon#about to read 3, iclass 39, count 0 2006.239.08:21:22.80#ibcon#read 3, iclass 39, count 0 2006.239.08:21:22.80#ibcon#about to read 4, iclass 39, count 0 2006.239.08:21:22.80#ibcon#read 4, iclass 39, count 0 2006.239.08:21:22.80#ibcon#about to read 5, iclass 39, count 0 2006.239.08:21:22.80#ibcon#read 5, iclass 39, count 0 2006.239.08:21:22.80#ibcon#about to read 6, iclass 39, count 0 2006.239.08:21:22.80#ibcon#read 6, iclass 39, count 0 2006.239.08:21:22.80#ibcon#end of sib2, iclass 39, count 0 2006.239.08:21:22.80#ibcon#*after write, iclass 39, count 0 2006.239.08:21:22.80#ibcon#*before return 0, iclass 39, count 0 2006.239.08:21:22.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:21:22.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.239.08:21:22.80#ibcon#about to clear, iclass 39 cls_cnt 0 2006.239.08:21:22.80#ibcon#cleared, iclass 39 cls_cnt 0 2006.239.08:21:22.80$4f8m12a/ifd4f 2006.239.08:21:22.80$ifd4f/lo= 2006.239.08:21:22.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:21:22.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:21:22.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:21:22.80$ifd4f/patch= 2006.239.08:21:22.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:21:22.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:21:22.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:21:22.80$4f8m12a/"form=m,16.000,1:2 2006.239.08:21:22.80$4f8m12a/"tpicd 2006.239.08:21:22.80$4f8m12a/echo=off 2006.239.08:21:22.80$4f8m12a/xlog=off 2006.239.08:21:22.80:!2006.239.08:23:30 2006.239.08:21:45.14#trakl#Source acquired 2006.239.08:21:46.14#flagr#flagr/antenna,acquired 2006.239.08:23:30.00:preob 2006.239.08:23:30.13/onsource/TRACKING 2006.239.08:23:30.13:!2006.239.08:23:40 2006.239.08:23:40.00:data_valid=on 2006.239.08:23:40.00:midob 2006.239.08:23:40.13/onsource/TRACKING 2006.239.08:23:40.13/wx/24.92,1011.5,79 2006.239.08:23:40.25/cable/+6.4137E-03 2006.239.08:23:41.34/va/01,08,usb,yes,35,37 2006.239.08:23:41.34/va/02,07,usb,yes,35,37 2006.239.08:23:41.34/va/03,07,usb,yes,33,33 2006.239.08:23:41.34/va/04,07,usb,yes,37,40 2006.239.08:23:41.34/va/05,08,usb,yes,34,36 2006.239.08:23:41.34/va/06,07,usb,yes,37,37 2006.239.08:23:41.34/va/07,07,usb,yes,37,36 2006.239.08:23:41.34/va/08,07,usb,yes,39,39 2006.239.08:23:41.57/valo/01,532.99,yes,locked 2006.239.08:23:41.57/valo/02,572.99,yes,locked 2006.239.08:23:41.57/valo/03,672.99,yes,locked 2006.239.08:23:41.57/valo/04,832.99,yes,locked 2006.239.08:23:41.57/valo/05,652.99,yes,locked 2006.239.08:23:41.57/valo/06,772.99,yes,locked 2006.239.08:23:41.57/valo/07,832.99,yes,locked 2006.239.08:23:41.57/valo/08,852.99,yes,locked 2006.239.08:23:42.66/vb/01,04,usb,yes,33,32 2006.239.08:23:42.66/vb/02,04,usb,yes,35,36 2006.239.08:23:42.66/vb/03,04,usb,yes,31,35 2006.239.08:23:42.66/vb/04,04,usb,yes,34,33 2006.239.08:23:42.66/vb/05,04,usb,yes,31,35 2006.239.08:23:42.66/vb/06,04,usb,yes,32,35 2006.239.08:23:42.66/vb/07,04,usb,yes,34,35 2006.239.08:23:42.66/vb/08,04,usb,yes,31,35 2006.239.08:23:42.89/vblo/01,632.99,yes,locked 2006.239.08:23:42.89/vblo/02,640.99,yes,locked 2006.239.08:23:42.89/vblo/03,656.99,yes,locked 2006.239.08:23:42.89/vblo/04,712.99,yes,locked 2006.239.08:23:42.89/vblo/05,744.99,yes,locked 2006.239.08:23:42.89/vblo/06,752.99,yes,locked 2006.239.08:23:42.89/vblo/07,734.99,yes,locked 2006.239.08:23:42.89/vblo/08,744.99,yes,locked 2006.239.08:23:43.04/vabw/8 2006.239.08:23:43.19/vbbw/8 2006.239.08:23:43.28/xfe/off,on,13.5 2006.239.08:23:43.65/ifatt/23,28,28,28 2006.239.08:23:44.08/fmout-gps/S +4.42E-07 2006.239.08:23:44.12:!2006.239.08:24:40 2006.239.08:24:40.01:data_valid=off 2006.239.08:24:40.02:postob 2006.239.08:24:40.10/cable/+6.4151E-03 2006.239.08:24:40.11/wx/24.91,1011.5,78 2006.239.08:24:40.18/fmout-gps/S +4.43E-07 2006.239.08:24:40.18:scan_name=239-0825,k06239,60 2006.239.08:24:40.19:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.239.08:24:41.14#flagr#flagr/antenna,new-source 2006.239.08:24:41.15:checkk5 2006.239.08:24:41.53/chk_autoobs//k5ts1/ autoobs is running! 2006.239.08:24:41.91/chk_autoobs//k5ts2/ autoobs is running! 2006.239.08:24:42.29/chk_autoobs//k5ts3/ autoobs is running! 2006.239.08:24:42.67/chk_autoobs//k5ts4/ autoobs is running! 2006.239.08:24:43.04/chk_obsdata//k5ts1/T2390823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:24:43.41/chk_obsdata//k5ts2/T2390823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:24:43.78/chk_obsdata//k5ts3/T2390823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:24:44.15/chk_obsdata//k5ts4/T2390823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:24:44.85/k5log//k5ts1_log_newline 2006.239.08:24:45.54/k5log//k5ts2_log_newline 2006.239.08:24:46.23/k5log//k5ts3_log_newline 2006.239.08:24:46.91/k5log//k5ts4_log_newline 2006.239.08:24:46.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:24:46.94:4f8m12a=3 2006.239.08:24:46.94$4f8m12a/echo=on 2006.239.08:24:46.94$4f8m12a/pcalon 2006.239.08:24:46.94$pcalon/"no phase cal control is implemented here 2006.239.08:24:46.94$4f8m12a/"tpicd=stop 2006.239.08:24:46.94$4f8m12a/vc4f8 2006.239.08:24:46.94$vc4f8/valo=1,532.99 2006.239.08:24:46.94#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.08:24:46.94#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.08:24:46.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:46.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:46.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:46.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:46.94#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:24:46.94#ibcon#first serial, iclass 14, count 0 2006.239.08:24:46.94#ibcon#enter sib2, iclass 14, count 0 2006.239.08:24:46.94#ibcon#flushed, iclass 14, count 0 2006.239.08:24:46.94#ibcon#about to write, iclass 14, count 0 2006.239.08:24:46.94#ibcon#wrote, iclass 14, count 0 2006.239.08:24:46.94#ibcon#about to read 3, iclass 14, count 0 2006.239.08:24:46.99#ibcon#read 3, iclass 14, count 0 2006.239.08:24:46.99#ibcon#about to read 4, iclass 14, count 0 2006.239.08:24:46.99#ibcon#read 4, iclass 14, count 0 2006.239.08:24:46.99#ibcon#about to read 5, iclass 14, count 0 2006.239.08:24:46.99#ibcon#read 5, iclass 14, count 0 2006.239.08:24:46.99#ibcon#about to read 6, iclass 14, count 0 2006.239.08:24:46.99#ibcon#read 6, iclass 14, count 0 2006.239.08:24:46.99#ibcon#end of sib2, iclass 14, count 0 2006.239.08:24:46.99#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:24:46.99#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:24:46.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.239.08:24:46.99#ibcon#*before write, iclass 14, count 0 2006.239.08:24:46.99#ibcon#enter sib2, iclass 14, count 0 2006.239.08:24:46.99#ibcon#flushed, iclass 14, count 0 2006.239.08:24:46.99#ibcon#about to write, iclass 14, count 0 2006.239.08:24:46.99#ibcon#wrote, iclass 14, count 0 2006.239.08:24:46.99#ibcon#about to read 3, iclass 14, count 0 2006.239.08:24:47.03#ibcon#read 3, iclass 14, count 0 2006.239.08:24:47.03#ibcon#about to read 4, iclass 14, count 0 2006.239.08:24:47.03#ibcon#read 4, iclass 14, count 0 2006.239.08:24:47.03#ibcon#about to read 5, iclass 14, count 0 2006.239.08:24:47.03#ibcon#read 5, iclass 14, count 0 2006.239.08:24:47.03#ibcon#about to read 6, iclass 14, count 0 2006.239.08:24:47.03#ibcon#read 6, iclass 14, count 0 2006.239.08:24:47.03#ibcon#end of sib2, iclass 14, count 0 2006.239.08:24:47.03#ibcon#*after write, iclass 14, count 0 2006.239.08:24:47.03#ibcon#*before return 0, iclass 14, count 0 2006.239.08:24:47.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:47.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:47.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:24:47.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:24:47.03$vc4f8/va=1,8 2006.239.08:24:47.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.08:24:47.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.08:24:47.03#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:47.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:47.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:47.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:47.03#ibcon#enter wrdev, iclass 16, count 2 2006.239.08:24:47.03#ibcon#first serial, iclass 16, count 2 2006.239.08:24:47.03#ibcon#enter sib2, iclass 16, count 2 2006.239.08:24:47.03#ibcon#flushed, iclass 16, count 2 2006.239.08:24:47.03#ibcon#about to write, iclass 16, count 2 2006.239.08:24:47.03#ibcon#wrote, iclass 16, count 2 2006.239.08:24:47.03#ibcon#about to read 3, iclass 16, count 2 2006.239.08:24:47.05#ibcon#read 3, iclass 16, count 2 2006.239.08:24:47.05#ibcon#about to read 4, iclass 16, count 2 2006.239.08:24:47.05#ibcon#read 4, iclass 16, count 2 2006.239.08:24:47.05#ibcon#about to read 5, iclass 16, count 2 2006.239.08:24:47.05#ibcon#read 5, iclass 16, count 2 2006.239.08:24:47.05#ibcon#about to read 6, iclass 16, count 2 2006.239.08:24:47.05#ibcon#read 6, iclass 16, count 2 2006.239.08:24:47.05#ibcon#end of sib2, iclass 16, count 2 2006.239.08:24:47.05#ibcon#*mode == 0, iclass 16, count 2 2006.239.08:24:47.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.08:24:47.05#ibcon#[25=AT01-08\r\n] 2006.239.08:24:47.05#ibcon#*before write, iclass 16, count 2 2006.239.08:24:47.05#ibcon#enter sib2, iclass 16, count 2 2006.239.08:24:47.05#ibcon#flushed, iclass 16, count 2 2006.239.08:24:47.05#ibcon#about to write, iclass 16, count 2 2006.239.08:24:47.05#ibcon#wrote, iclass 16, count 2 2006.239.08:24:47.05#ibcon#about to read 3, iclass 16, count 2 2006.239.08:24:47.08#ibcon#read 3, iclass 16, count 2 2006.239.08:24:47.08#ibcon#about to read 4, iclass 16, count 2 2006.239.08:24:47.08#ibcon#read 4, iclass 16, count 2 2006.239.08:24:47.08#ibcon#about to read 5, iclass 16, count 2 2006.239.08:24:47.08#ibcon#read 5, iclass 16, count 2 2006.239.08:24:47.08#ibcon#about to read 6, iclass 16, count 2 2006.239.08:24:47.08#ibcon#read 6, iclass 16, count 2 2006.239.08:24:47.08#ibcon#end of sib2, iclass 16, count 2 2006.239.08:24:47.08#ibcon#*after write, iclass 16, count 2 2006.239.08:24:47.08#ibcon#*before return 0, iclass 16, count 2 2006.239.08:24:47.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:47.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:47.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.08:24:47.08#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:47.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:47.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:47.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:47.20#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:24:47.20#ibcon#first serial, iclass 16, count 0 2006.239.08:24:47.20#ibcon#enter sib2, iclass 16, count 0 2006.239.08:24:47.20#ibcon#flushed, iclass 16, count 0 2006.239.08:24:47.20#ibcon#about to write, iclass 16, count 0 2006.239.08:24:47.20#ibcon#wrote, iclass 16, count 0 2006.239.08:24:47.20#ibcon#about to read 3, iclass 16, count 0 2006.239.08:24:47.22#ibcon#read 3, iclass 16, count 0 2006.239.08:24:47.22#ibcon#about to read 4, iclass 16, count 0 2006.239.08:24:47.22#ibcon#read 4, iclass 16, count 0 2006.239.08:24:47.22#ibcon#about to read 5, iclass 16, count 0 2006.239.08:24:47.22#ibcon#read 5, iclass 16, count 0 2006.239.08:24:47.22#ibcon#about to read 6, iclass 16, count 0 2006.239.08:24:47.22#ibcon#read 6, iclass 16, count 0 2006.239.08:24:47.22#ibcon#end of sib2, iclass 16, count 0 2006.239.08:24:47.22#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:24:47.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:24:47.22#ibcon#[25=USB\r\n] 2006.239.08:24:47.22#ibcon#*before write, iclass 16, count 0 2006.239.08:24:47.22#ibcon#enter sib2, iclass 16, count 0 2006.239.08:24:47.22#ibcon#flushed, iclass 16, count 0 2006.239.08:24:47.22#ibcon#about to write, iclass 16, count 0 2006.239.08:24:47.22#ibcon#wrote, iclass 16, count 0 2006.239.08:24:47.22#ibcon#about to read 3, iclass 16, count 0 2006.239.08:24:47.25#ibcon#read 3, iclass 16, count 0 2006.239.08:24:47.25#ibcon#about to read 4, iclass 16, count 0 2006.239.08:24:47.25#ibcon#read 4, iclass 16, count 0 2006.239.08:24:47.25#ibcon#about to read 5, iclass 16, count 0 2006.239.08:24:47.25#ibcon#read 5, iclass 16, count 0 2006.239.08:24:47.25#ibcon#about to read 6, iclass 16, count 0 2006.239.08:24:47.25#ibcon#read 6, iclass 16, count 0 2006.239.08:24:47.25#ibcon#end of sib2, iclass 16, count 0 2006.239.08:24:47.25#ibcon#*after write, iclass 16, count 0 2006.239.08:24:47.25#ibcon#*before return 0, iclass 16, count 0 2006.239.08:24:47.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:47.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:47.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:24:47.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:24:47.25$vc4f8/valo=2,572.99 2006.239.08:24:47.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:24:47.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:24:47.25#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:47.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:47.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:47.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:47.25#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:24:47.25#ibcon#first serial, iclass 18, count 0 2006.239.08:24:47.25#ibcon#enter sib2, iclass 18, count 0 2006.239.08:24:47.25#ibcon#flushed, iclass 18, count 0 2006.239.08:24:47.25#ibcon#about to write, iclass 18, count 0 2006.239.08:24:47.25#ibcon#wrote, iclass 18, count 0 2006.239.08:24:47.25#ibcon#about to read 3, iclass 18, count 0 2006.239.08:24:47.28#ibcon#read 3, iclass 18, count 0 2006.239.08:24:47.28#ibcon#about to read 4, iclass 18, count 0 2006.239.08:24:47.28#ibcon#read 4, iclass 18, count 0 2006.239.08:24:47.28#ibcon#about to read 5, iclass 18, count 0 2006.239.08:24:47.28#ibcon#read 5, iclass 18, count 0 2006.239.08:24:47.28#ibcon#about to read 6, iclass 18, count 0 2006.239.08:24:47.28#ibcon#read 6, iclass 18, count 0 2006.239.08:24:47.28#ibcon#end of sib2, iclass 18, count 0 2006.239.08:24:47.28#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:24:47.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:24:47.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.239.08:24:47.28#ibcon#*before write, iclass 18, count 0 2006.239.08:24:47.28#ibcon#enter sib2, iclass 18, count 0 2006.239.08:24:47.28#ibcon#flushed, iclass 18, count 0 2006.239.08:24:47.28#ibcon#about to write, iclass 18, count 0 2006.239.08:24:47.28#ibcon#wrote, iclass 18, count 0 2006.239.08:24:47.28#ibcon#about to read 3, iclass 18, count 0 2006.239.08:24:47.32#ibcon#read 3, iclass 18, count 0 2006.239.08:24:47.32#ibcon#about to read 4, iclass 18, count 0 2006.239.08:24:47.32#ibcon#read 4, iclass 18, count 0 2006.239.08:24:47.32#ibcon#about to read 5, iclass 18, count 0 2006.239.08:24:47.32#ibcon#read 5, iclass 18, count 0 2006.239.08:24:47.32#ibcon#about to read 6, iclass 18, count 0 2006.239.08:24:47.32#ibcon#read 6, iclass 18, count 0 2006.239.08:24:47.32#ibcon#end of sib2, iclass 18, count 0 2006.239.08:24:47.32#ibcon#*after write, iclass 18, count 0 2006.239.08:24:47.32#ibcon#*before return 0, iclass 18, count 0 2006.239.08:24:47.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:47.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:47.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:24:47.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:24:47.32$vc4f8/va=2,7 2006.239.08:24:47.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.08:24:47.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.08:24:47.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:47.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:47.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:47.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:47.37#ibcon#enter wrdev, iclass 20, count 2 2006.239.08:24:47.37#ibcon#first serial, iclass 20, count 2 2006.239.08:24:47.37#ibcon#enter sib2, iclass 20, count 2 2006.239.08:24:47.37#ibcon#flushed, iclass 20, count 2 2006.239.08:24:47.37#ibcon#about to write, iclass 20, count 2 2006.239.08:24:47.37#ibcon#wrote, iclass 20, count 2 2006.239.08:24:47.37#ibcon#about to read 3, iclass 20, count 2 2006.239.08:24:47.39#ibcon#read 3, iclass 20, count 2 2006.239.08:24:47.39#ibcon#about to read 4, iclass 20, count 2 2006.239.08:24:47.39#ibcon#read 4, iclass 20, count 2 2006.239.08:24:47.39#ibcon#about to read 5, iclass 20, count 2 2006.239.08:24:47.39#ibcon#read 5, iclass 20, count 2 2006.239.08:24:47.39#ibcon#about to read 6, iclass 20, count 2 2006.239.08:24:47.39#ibcon#read 6, iclass 20, count 2 2006.239.08:24:47.39#ibcon#end of sib2, iclass 20, count 2 2006.239.08:24:47.39#ibcon#*mode == 0, iclass 20, count 2 2006.239.08:24:47.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.08:24:47.39#ibcon#[25=AT02-07\r\n] 2006.239.08:24:47.39#ibcon#*before write, iclass 20, count 2 2006.239.08:24:47.39#ibcon#enter sib2, iclass 20, count 2 2006.239.08:24:47.39#ibcon#flushed, iclass 20, count 2 2006.239.08:24:47.39#ibcon#about to write, iclass 20, count 2 2006.239.08:24:47.39#ibcon#wrote, iclass 20, count 2 2006.239.08:24:47.39#ibcon#about to read 3, iclass 20, count 2 2006.239.08:24:47.42#ibcon#read 3, iclass 20, count 2 2006.239.08:24:47.42#ibcon#about to read 4, iclass 20, count 2 2006.239.08:24:47.42#ibcon#read 4, iclass 20, count 2 2006.239.08:24:47.42#ibcon#about to read 5, iclass 20, count 2 2006.239.08:24:47.42#ibcon#read 5, iclass 20, count 2 2006.239.08:24:47.42#ibcon#about to read 6, iclass 20, count 2 2006.239.08:24:47.42#ibcon#read 6, iclass 20, count 2 2006.239.08:24:47.42#ibcon#end of sib2, iclass 20, count 2 2006.239.08:24:47.42#ibcon#*after write, iclass 20, count 2 2006.239.08:24:47.42#ibcon#*before return 0, iclass 20, count 2 2006.239.08:24:47.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:47.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:47.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.08:24:47.42#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:47.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:47.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:47.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:47.54#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:24:47.54#ibcon#first serial, iclass 20, count 0 2006.239.08:24:47.54#ibcon#enter sib2, iclass 20, count 0 2006.239.08:24:47.54#ibcon#flushed, iclass 20, count 0 2006.239.08:24:47.54#ibcon#about to write, iclass 20, count 0 2006.239.08:24:47.54#ibcon#wrote, iclass 20, count 0 2006.239.08:24:47.54#ibcon#about to read 3, iclass 20, count 0 2006.239.08:24:47.56#ibcon#read 3, iclass 20, count 0 2006.239.08:24:47.56#ibcon#about to read 4, iclass 20, count 0 2006.239.08:24:47.56#ibcon#read 4, iclass 20, count 0 2006.239.08:24:47.56#ibcon#about to read 5, iclass 20, count 0 2006.239.08:24:47.56#ibcon#read 5, iclass 20, count 0 2006.239.08:24:47.56#ibcon#about to read 6, iclass 20, count 0 2006.239.08:24:47.56#ibcon#read 6, iclass 20, count 0 2006.239.08:24:47.56#ibcon#end of sib2, iclass 20, count 0 2006.239.08:24:47.56#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:24:47.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:24:47.56#ibcon#[25=USB\r\n] 2006.239.08:24:47.56#ibcon#*before write, iclass 20, count 0 2006.239.08:24:47.56#ibcon#enter sib2, iclass 20, count 0 2006.239.08:24:47.56#ibcon#flushed, iclass 20, count 0 2006.239.08:24:47.56#ibcon#about to write, iclass 20, count 0 2006.239.08:24:47.56#ibcon#wrote, iclass 20, count 0 2006.239.08:24:47.56#ibcon#about to read 3, iclass 20, count 0 2006.239.08:24:47.59#ibcon#read 3, iclass 20, count 0 2006.239.08:24:47.59#ibcon#about to read 4, iclass 20, count 0 2006.239.08:24:47.59#ibcon#read 4, iclass 20, count 0 2006.239.08:24:47.59#ibcon#about to read 5, iclass 20, count 0 2006.239.08:24:47.59#ibcon#read 5, iclass 20, count 0 2006.239.08:24:47.59#ibcon#about to read 6, iclass 20, count 0 2006.239.08:24:47.59#ibcon#read 6, iclass 20, count 0 2006.239.08:24:47.59#ibcon#end of sib2, iclass 20, count 0 2006.239.08:24:47.59#ibcon#*after write, iclass 20, count 0 2006.239.08:24:47.59#ibcon#*before return 0, iclass 20, count 0 2006.239.08:24:47.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:47.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:47.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:24:47.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:24:47.59$vc4f8/valo=3,672.99 2006.239.08:24:47.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.08:24:47.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.08:24:47.59#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:47.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:47.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:47.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:47.59#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:24:47.59#ibcon#first serial, iclass 22, count 0 2006.239.08:24:47.59#ibcon#enter sib2, iclass 22, count 0 2006.239.08:24:47.59#ibcon#flushed, iclass 22, count 0 2006.239.08:24:47.59#ibcon#about to write, iclass 22, count 0 2006.239.08:24:47.59#ibcon#wrote, iclass 22, count 0 2006.239.08:24:47.59#ibcon#about to read 3, iclass 22, count 0 2006.239.08:24:47.61#ibcon#read 3, iclass 22, count 0 2006.239.08:24:47.61#ibcon#about to read 4, iclass 22, count 0 2006.239.08:24:47.61#ibcon#read 4, iclass 22, count 0 2006.239.08:24:47.61#ibcon#about to read 5, iclass 22, count 0 2006.239.08:24:47.61#ibcon#read 5, iclass 22, count 0 2006.239.08:24:47.61#ibcon#about to read 6, iclass 22, count 0 2006.239.08:24:47.61#ibcon#read 6, iclass 22, count 0 2006.239.08:24:47.61#ibcon#end of sib2, iclass 22, count 0 2006.239.08:24:47.61#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:24:47.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:24:47.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.239.08:24:47.61#ibcon#*before write, iclass 22, count 0 2006.239.08:24:47.61#ibcon#enter sib2, iclass 22, count 0 2006.239.08:24:47.61#ibcon#flushed, iclass 22, count 0 2006.239.08:24:47.61#ibcon#about to write, iclass 22, count 0 2006.239.08:24:47.61#ibcon#wrote, iclass 22, count 0 2006.239.08:24:47.61#ibcon#about to read 3, iclass 22, count 0 2006.239.08:24:47.65#ibcon#read 3, iclass 22, count 0 2006.239.08:24:47.65#ibcon#about to read 4, iclass 22, count 0 2006.239.08:24:47.65#ibcon#read 4, iclass 22, count 0 2006.239.08:24:47.65#ibcon#about to read 5, iclass 22, count 0 2006.239.08:24:47.65#ibcon#read 5, iclass 22, count 0 2006.239.08:24:47.65#ibcon#about to read 6, iclass 22, count 0 2006.239.08:24:47.65#ibcon#read 6, iclass 22, count 0 2006.239.08:24:47.65#ibcon#end of sib2, iclass 22, count 0 2006.239.08:24:47.65#ibcon#*after write, iclass 22, count 0 2006.239.08:24:47.65#ibcon#*before return 0, iclass 22, count 0 2006.239.08:24:47.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:47.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:47.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:24:47.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:24:47.65$vc4f8/va=3,7 2006.239.08:24:47.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.08:24:47.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.08:24:47.65#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:47.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:47.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:47.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:47.71#ibcon#enter wrdev, iclass 24, count 2 2006.239.08:24:47.71#ibcon#first serial, iclass 24, count 2 2006.239.08:24:47.71#ibcon#enter sib2, iclass 24, count 2 2006.239.08:24:47.71#ibcon#flushed, iclass 24, count 2 2006.239.08:24:47.71#ibcon#about to write, iclass 24, count 2 2006.239.08:24:47.71#ibcon#wrote, iclass 24, count 2 2006.239.08:24:47.71#ibcon#about to read 3, iclass 24, count 2 2006.239.08:24:47.74#ibcon#read 3, iclass 24, count 2 2006.239.08:24:47.74#ibcon#about to read 4, iclass 24, count 2 2006.239.08:24:47.74#ibcon#read 4, iclass 24, count 2 2006.239.08:24:47.74#ibcon#about to read 5, iclass 24, count 2 2006.239.08:24:47.74#ibcon#read 5, iclass 24, count 2 2006.239.08:24:47.74#ibcon#about to read 6, iclass 24, count 2 2006.239.08:24:47.74#ibcon#read 6, iclass 24, count 2 2006.239.08:24:47.74#ibcon#end of sib2, iclass 24, count 2 2006.239.08:24:47.74#ibcon#*mode == 0, iclass 24, count 2 2006.239.08:24:47.74#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.08:24:47.74#ibcon#[25=AT03-07\r\n] 2006.239.08:24:47.74#ibcon#*before write, iclass 24, count 2 2006.239.08:24:47.74#ibcon#enter sib2, iclass 24, count 2 2006.239.08:24:47.74#ibcon#flushed, iclass 24, count 2 2006.239.08:24:47.74#ibcon#about to write, iclass 24, count 2 2006.239.08:24:47.74#ibcon#wrote, iclass 24, count 2 2006.239.08:24:47.74#ibcon#about to read 3, iclass 24, count 2 2006.239.08:24:47.77#ibcon#read 3, iclass 24, count 2 2006.239.08:24:47.77#ibcon#about to read 4, iclass 24, count 2 2006.239.08:24:47.77#ibcon#read 4, iclass 24, count 2 2006.239.08:24:47.77#ibcon#about to read 5, iclass 24, count 2 2006.239.08:24:47.77#ibcon#read 5, iclass 24, count 2 2006.239.08:24:47.77#ibcon#about to read 6, iclass 24, count 2 2006.239.08:24:47.77#ibcon#read 6, iclass 24, count 2 2006.239.08:24:47.77#ibcon#end of sib2, iclass 24, count 2 2006.239.08:24:47.77#ibcon#*after write, iclass 24, count 2 2006.239.08:24:47.77#ibcon#*before return 0, iclass 24, count 2 2006.239.08:24:47.77#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:47.77#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:47.77#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.08:24:47.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:47.77#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:47.89#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:47.89#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:47.89#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:24:47.89#ibcon#first serial, iclass 24, count 0 2006.239.08:24:47.89#ibcon#enter sib2, iclass 24, count 0 2006.239.08:24:47.89#ibcon#flushed, iclass 24, count 0 2006.239.08:24:47.89#ibcon#about to write, iclass 24, count 0 2006.239.08:24:47.89#ibcon#wrote, iclass 24, count 0 2006.239.08:24:47.89#ibcon#about to read 3, iclass 24, count 0 2006.239.08:24:47.91#ibcon#read 3, iclass 24, count 0 2006.239.08:24:47.91#ibcon#about to read 4, iclass 24, count 0 2006.239.08:24:47.91#ibcon#read 4, iclass 24, count 0 2006.239.08:24:47.91#ibcon#about to read 5, iclass 24, count 0 2006.239.08:24:47.91#ibcon#read 5, iclass 24, count 0 2006.239.08:24:47.91#ibcon#about to read 6, iclass 24, count 0 2006.239.08:24:47.91#ibcon#read 6, iclass 24, count 0 2006.239.08:24:47.91#ibcon#end of sib2, iclass 24, count 0 2006.239.08:24:47.91#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:24:47.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:24:47.91#ibcon#[25=USB\r\n] 2006.239.08:24:47.91#ibcon#*before write, iclass 24, count 0 2006.239.08:24:47.91#ibcon#enter sib2, iclass 24, count 0 2006.239.08:24:47.91#ibcon#flushed, iclass 24, count 0 2006.239.08:24:47.91#ibcon#about to write, iclass 24, count 0 2006.239.08:24:47.91#ibcon#wrote, iclass 24, count 0 2006.239.08:24:47.91#ibcon#about to read 3, iclass 24, count 0 2006.239.08:24:47.94#ibcon#read 3, iclass 24, count 0 2006.239.08:24:47.94#ibcon#about to read 4, iclass 24, count 0 2006.239.08:24:47.94#ibcon#read 4, iclass 24, count 0 2006.239.08:24:47.94#ibcon#about to read 5, iclass 24, count 0 2006.239.08:24:47.94#ibcon#read 5, iclass 24, count 0 2006.239.08:24:47.94#ibcon#about to read 6, iclass 24, count 0 2006.239.08:24:47.94#ibcon#read 6, iclass 24, count 0 2006.239.08:24:47.94#ibcon#end of sib2, iclass 24, count 0 2006.239.08:24:47.94#ibcon#*after write, iclass 24, count 0 2006.239.08:24:47.94#ibcon#*before return 0, iclass 24, count 0 2006.239.08:24:47.94#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:47.94#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:47.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:24:47.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:24:47.94$vc4f8/valo=4,832.99 2006.239.08:24:47.94#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.08:24:47.94#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.08:24:47.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:47.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:47.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:47.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:47.94#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:24:47.94#ibcon#first serial, iclass 26, count 0 2006.239.08:24:47.94#ibcon#enter sib2, iclass 26, count 0 2006.239.08:24:47.94#ibcon#flushed, iclass 26, count 0 2006.239.08:24:47.94#ibcon#about to write, iclass 26, count 0 2006.239.08:24:47.94#ibcon#wrote, iclass 26, count 0 2006.239.08:24:47.94#ibcon#about to read 3, iclass 26, count 0 2006.239.08:24:47.96#ibcon#read 3, iclass 26, count 0 2006.239.08:24:47.96#ibcon#about to read 4, iclass 26, count 0 2006.239.08:24:47.96#ibcon#read 4, iclass 26, count 0 2006.239.08:24:47.96#ibcon#about to read 5, iclass 26, count 0 2006.239.08:24:47.96#ibcon#read 5, iclass 26, count 0 2006.239.08:24:47.96#ibcon#about to read 6, iclass 26, count 0 2006.239.08:24:47.96#ibcon#read 6, iclass 26, count 0 2006.239.08:24:47.96#ibcon#end of sib2, iclass 26, count 0 2006.239.08:24:47.96#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:24:47.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:24:47.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.239.08:24:47.96#ibcon#*before write, iclass 26, count 0 2006.239.08:24:47.96#ibcon#enter sib2, iclass 26, count 0 2006.239.08:24:47.96#ibcon#flushed, iclass 26, count 0 2006.239.08:24:47.96#ibcon#about to write, iclass 26, count 0 2006.239.08:24:47.96#ibcon#wrote, iclass 26, count 0 2006.239.08:24:47.96#ibcon#about to read 3, iclass 26, count 0 2006.239.08:24:48.00#ibcon#read 3, iclass 26, count 0 2006.239.08:24:48.00#ibcon#about to read 4, iclass 26, count 0 2006.239.08:24:48.00#ibcon#read 4, iclass 26, count 0 2006.239.08:24:48.00#ibcon#about to read 5, iclass 26, count 0 2006.239.08:24:48.00#ibcon#read 5, iclass 26, count 0 2006.239.08:24:48.00#ibcon#about to read 6, iclass 26, count 0 2006.239.08:24:48.00#ibcon#read 6, iclass 26, count 0 2006.239.08:24:48.00#ibcon#end of sib2, iclass 26, count 0 2006.239.08:24:48.00#ibcon#*after write, iclass 26, count 0 2006.239.08:24:48.00#ibcon#*before return 0, iclass 26, count 0 2006.239.08:24:48.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:48.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:48.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:24:48.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:24:48.00$vc4f8/va=4,7 2006.239.08:24:48.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.08:24:48.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.08:24:48.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:48.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:48.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:48.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:48.06#ibcon#enter wrdev, iclass 28, count 2 2006.239.08:24:48.06#ibcon#first serial, iclass 28, count 2 2006.239.08:24:48.06#ibcon#enter sib2, iclass 28, count 2 2006.239.08:24:48.06#ibcon#flushed, iclass 28, count 2 2006.239.08:24:48.06#ibcon#about to write, iclass 28, count 2 2006.239.08:24:48.06#ibcon#wrote, iclass 28, count 2 2006.239.08:24:48.06#ibcon#about to read 3, iclass 28, count 2 2006.239.08:24:48.08#ibcon#read 3, iclass 28, count 2 2006.239.08:24:48.08#ibcon#about to read 4, iclass 28, count 2 2006.239.08:24:48.08#ibcon#read 4, iclass 28, count 2 2006.239.08:24:48.08#ibcon#about to read 5, iclass 28, count 2 2006.239.08:24:48.08#ibcon#read 5, iclass 28, count 2 2006.239.08:24:48.08#ibcon#about to read 6, iclass 28, count 2 2006.239.08:24:48.08#ibcon#read 6, iclass 28, count 2 2006.239.08:24:48.08#ibcon#end of sib2, iclass 28, count 2 2006.239.08:24:48.08#ibcon#*mode == 0, iclass 28, count 2 2006.239.08:24:48.08#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.08:24:48.08#ibcon#[25=AT04-07\r\n] 2006.239.08:24:48.08#ibcon#*before write, iclass 28, count 2 2006.239.08:24:48.08#ibcon#enter sib2, iclass 28, count 2 2006.239.08:24:48.08#ibcon#flushed, iclass 28, count 2 2006.239.08:24:48.08#ibcon#about to write, iclass 28, count 2 2006.239.08:24:48.08#ibcon#wrote, iclass 28, count 2 2006.239.08:24:48.08#ibcon#about to read 3, iclass 28, count 2 2006.239.08:24:48.11#ibcon#read 3, iclass 28, count 2 2006.239.08:24:48.11#ibcon#about to read 4, iclass 28, count 2 2006.239.08:24:48.11#ibcon#read 4, iclass 28, count 2 2006.239.08:24:48.11#ibcon#about to read 5, iclass 28, count 2 2006.239.08:24:48.11#ibcon#read 5, iclass 28, count 2 2006.239.08:24:48.11#ibcon#about to read 6, iclass 28, count 2 2006.239.08:24:48.11#ibcon#read 6, iclass 28, count 2 2006.239.08:24:48.11#ibcon#end of sib2, iclass 28, count 2 2006.239.08:24:48.11#ibcon#*after write, iclass 28, count 2 2006.239.08:24:48.11#ibcon#*before return 0, iclass 28, count 2 2006.239.08:24:48.11#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:48.11#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:48.11#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.08:24:48.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:48.11#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:48.23#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:48.23#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:48.23#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:24:48.23#ibcon#first serial, iclass 28, count 0 2006.239.08:24:48.23#ibcon#enter sib2, iclass 28, count 0 2006.239.08:24:48.23#ibcon#flushed, iclass 28, count 0 2006.239.08:24:48.23#ibcon#about to write, iclass 28, count 0 2006.239.08:24:48.23#ibcon#wrote, iclass 28, count 0 2006.239.08:24:48.23#ibcon#about to read 3, iclass 28, count 0 2006.239.08:24:48.25#ibcon#read 3, iclass 28, count 0 2006.239.08:24:48.25#ibcon#about to read 4, iclass 28, count 0 2006.239.08:24:48.25#ibcon#read 4, iclass 28, count 0 2006.239.08:24:48.25#ibcon#about to read 5, iclass 28, count 0 2006.239.08:24:48.25#ibcon#read 5, iclass 28, count 0 2006.239.08:24:48.25#ibcon#about to read 6, iclass 28, count 0 2006.239.08:24:48.25#ibcon#read 6, iclass 28, count 0 2006.239.08:24:48.25#ibcon#end of sib2, iclass 28, count 0 2006.239.08:24:48.25#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:24:48.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:24:48.25#ibcon#[25=USB\r\n] 2006.239.08:24:48.25#ibcon#*before write, iclass 28, count 0 2006.239.08:24:48.25#ibcon#enter sib2, iclass 28, count 0 2006.239.08:24:48.25#ibcon#flushed, iclass 28, count 0 2006.239.08:24:48.25#ibcon#about to write, iclass 28, count 0 2006.239.08:24:48.25#ibcon#wrote, iclass 28, count 0 2006.239.08:24:48.25#ibcon#about to read 3, iclass 28, count 0 2006.239.08:24:48.28#ibcon#read 3, iclass 28, count 0 2006.239.08:24:48.28#ibcon#about to read 4, iclass 28, count 0 2006.239.08:24:48.28#ibcon#read 4, iclass 28, count 0 2006.239.08:24:48.28#ibcon#about to read 5, iclass 28, count 0 2006.239.08:24:48.28#ibcon#read 5, iclass 28, count 0 2006.239.08:24:48.28#ibcon#about to read 6, iclass 28, count 0 2006.239.08:24:48.28#ibcon#read 6, iclass 28, count 0 2006.239.08:24:48.28#ibcon#end of sib2, iclass 28, count 0 2006.239.08:24:48.28#ibcon#*after write, iclass 28, count 0 2006.239.08:24:48.28#ibcon#*before return 0, iclass 28, count 0 2006.239.08:24:48.28#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:48.28#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:48.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:24:48.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:24:48.28$vc4f8/valo=5,652.99 2006.239.08:24:48.28#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.08:24:48.28#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.08:24:48.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:48.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:48.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:48.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:48.28#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:24:48.28#ibcon#first serial, iclass 30, count 0 2006.239.08:24:48.28#ibcon#enter sib2, iclass 30, count 0 2006.239.08:24:48.28#ibcon#flushed, iclass 30, count 0 2006.239.08:24:48.28#ibcon#about to write, iclass 30, count 0 2006.239.08:24:48.28#ibcon#wrote, iclass 30, count 0 2006.239.08:24:48.28#ibcon#about to read 3, iclass 30, count 0 2006.239.08:24:48.30#ibcon#read 3, iclass 30, count 0 2006.239.08:24:48.30#ibcon#about to read 4, iclass 30, count 0 2006.239.08:24:48.30#ibcon#read 4, iclass 30, count 0 2006.239.08:24:48.30#ibcon#about to read 5, iclass 30, count 0 2006.239.08:24:48.30#ibcon#read 5, iclass 30, count 0 2006.239.08:24:48.30#ibcon#about to read 6, iclass 30, count 0 2006.239.08:24:48.30#ibcon#read 6, iclass 30, count 0 2006.239.08:24:48.30#ibcon#end of sib2, iclass 30, count 0 2006.239.08:24:48.30#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:24:48.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:24:48.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.239.08:24:48.30#ibcon#*before write, iclass 30, count 0 2006.239.08:24:48.30#ibcon#enter sib2, iclass 30, count 0 2006.239.08:24:48.30#ibcon#flushed, iclass 30, count 0 2006.239.08:24:48.30#ibcon#about to write, iclass 30, count 0 2006.239.08:24:48.30#ibcon#wrote, iclass 30, count 0 2006.239.08:24:48.30#ibcon#about to read 3, iclass 30, count 0 2006.239.08:24:48.34#ibcon#read 3, iclass 30, count 0 2006.239.08:24:48.34#ibcon#about to read 4, iclass 30, count 0 2006.239.08:24:48.34#ibcon#read 4, iclass 30, count 0 2006.239.08:24:48.34#ibcon#about to read 5, iclass 30, count 0 2006.239.08:24:48.34#ibcon#read 5, iclass 30, count 0 2006.239.08:24:48.34#ibcon#about to read 6, iclass 30, count 0 2006.239.08:24:48.34#ibcon#read 6, iclass 30, count 0 2006.239.08:24:48.34#ibcon#end of sib2, iclass 30, count 0 2006.239.08:24:48.34#ibcon#*after write, iclass 30, count 0 2006.239.08:24:48.34#ibcon#*before return 0, iclass 30, count 0 2006.239.08:24:48.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:48.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:48.34#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:24:48.34#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:24:48.34$vc4f8/va=5,8 2006.239.08:24:48.34#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.08:24:48.34#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.08:24:48.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:48.34#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:48.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:48.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:48.40#ibcon#enter wrdev, iclass 32, count 2 2006.239.08:24:48.40#ibcon#first serial, iclass 32, count 2 2006.239.08:24:48.40#ibcon#enter sib2, iclass 32, count 2 2006.239.08:24:48.40#ibcon#flushed, iclass 32, count 2 2006.239.08:24:48.40#ibcon#about to write, iclass 32, count 2 2006.239.08:24:48.40#ibcon#wrote, iclass 32, count 2 2006.239.08:24:48.40#ibcon#about to read 3, iclass 32, count 2 2006.239.08:24:48.42#ibcon#read 3, iclass 32, count 2 2006.239.08:24:48.42#ibcon#about to read 4, iclass 32, count 2 2006.239.08:24:48.42#ibcon#read 4, iclass 32, count 2 2006.239.08:24:48.42#ibcon#about to read 5, iclass 32, count 2 2006.239.08:24:48.42#ibcon#read 5, iclass 32, count 2 2006.239.08:24:48.42#ibcon#about to read 6, iclass 32, count 2 2006.239.08:24:48.42#ibcon#read 6, iclass 32, count 2 2006.239.08:24:48.42#ibcon#end of sib2, iclass 32, count 2 2006.239.08:24:48.42#ibcon#*mode == 0, iclass 32, count 2 2006.239.08:24:48.42#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.08:24:48.42#ibcon#[25=AT05-08\r\n] 2006.239.08:24:48.42#ibcon#*before write, iclass 32, count 2 2006.239.08:24:48.42#ibcon#enter sib2, iclass 32, count 2 2006.239.08:24:48.42#ibcon#flushed, iclass 32, count 2 2006.239.08:24:48.42#ibcon#about to write, iclass 32, count 2 2006.239.08:24:48.42#ibcon#wrote, iclass 32, count 2 2006.239.08:24:48.42#ibcon#about to read 3, iclass 32, count 2 2006.239.08:24:48.45#ibcon#read 3, iclass 32, count 2 2006.239.08:24:48.45#ibcon#about to read 4, iclass 32, count 2 2006.239.08:24:48.45#ibcon#read 4, iclass 32, count 2 2006.239.08:24:48.45#ibcon#about to read 5, iclass 32, count 2 2006.239.08:24:48.45#ibcon#read 5, iclass 32, count 2 2006.239.08:24:48.45#ibcon#about to read 6, iclass 32, count 2 2006.239.08:24:48.45#ibcon#read 6, iclass 32, count 2 2006.239.08:24:48.45#ibcon#end of sib2, iclass 32, count 2 2006.239.08:24:48.45#ibcon#*after write, iclass 32, count 2 2006.239.08:24:48.45#ibcon#*before return 0, iclass 32, count 2 2006.239.08:24:48.45#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:48.45#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:48.45#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.08:24:48.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:48.45#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:48.57#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:48.57#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:48.57#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:24:48.57#ibcon#first serial, iclass 32, count 0 2006.239.08:24:48.57#ibcon#enter sib2, iclass 32, count 0 2006.239.08:24:48.57#ibcon#flushed, iclass 32, count 0 2006.239.08:24:48.57#ibcon#about to write, iclass 32, count 0 2006.239.08:24:48.57#ibcon#wrote, iclass 32, count 0 2006.239.08:24:48.57#ibcon#about to read 3, iclass 32, count 0 2006.239.08:24:48.59#ibcon#read 3, iclass 32, count 0 2006.239.08:24:48.59#ibcon#about to read 4, iclass 32, count 0 2006.239.08:24:48.59#ibcon#read 4, iclass 32, count 0 2006.239.08:24:48.59#ibcon#about to read 5, iclass 32, count 0 2006.239.08:24:48.59#ibcon#read 5, iclass 32, count 0 2006.239.08:24:48.59#ibcon#about to read 6, iclass 32, count 0 2006.239.08:24:48.59#ibcon#read 6, iclass 32, count 0 2006.239.08:24:48.59#ibcon#end of sib2, iclass 32, count 0 2006.239.08:24:48.59#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:24:48.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:24:48.59#ibcon#[25=USB\r\n] 2006.239.08:24:48.59#ibcon#*before write, iclass 32, count 0 2006.239.08:24:48.59#ibcon#enter sib2, iclass 32, count 0 2006.239.08:24:48.59#ibcon#flushed, iclass 32, count 0 2006.239.08:24:48.59#ibcon#about to write, iclass 32, count 0 2006.239.08:24:48.59#ibcon#wrote, iclass 32, count 0 2006.239.08:24:48.59#ibcon#about to read 3, iclass 32, count 0 2006.239.08:24:48.62#ibcon#read 3, iclass 32, count 0 2006.239.08:24:48.62#ibcon#about to read 4, iclass 32, count 0 2006.239.08:24:48.62#ibcon#read 4, iclass 32, count 0 2006.239.08:24:48.62#ibcon#about to read 5, iclass 32, count 0 2006.239.08:24:48.62#ibcon#read 5, iclass 32, count 0 2006.239.08:24:48.62#ibcon#about to read 6, iclass 32, count 0 2006.239.08:24:48.62#ibcon#read 6, iclass 32, count 0 2006.239.08:24:48.62#ibcon#end of sib2, iclass 32, count 0 2006.239.08:24:48.62#ibcon#*after write, iclass 32, count 0 2006.239.08:24:48.62#ibcon#*before return 0, iclass 32, count 0 2006.239.08:24:48.62#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:48.62#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:48.62#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:24:48.62#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:24:48.62$vc4f8/valo=6,772.99 2006.239.08:24:48.62#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.08:24:48.62#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.08:24:48.62#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:48.62#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:48.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:48.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:48.62#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:24:48.62#ibcon#first serial, iclass 34, count 0 2006.239.08:24:48.62#ibcon#enter sib2, iclass 34, count 0 2006.239.08:24:48.62#ibcon#flushed, iclass 34, count 0 2006.239.08:24:48.62#ibcon#about to write, iclass 34, count 0 2006.239.08:24:48.62#ibcon#wrote, iclass 34, count 0 2006.239.08:24:48.62#ibcon#about to read 3, iclass 34, count 0 2006.239.08:24:48.64#ibcon#read 3, iclass 34, count 0 2006.239.08:24:48.64#ibcon#about to read 4, iclass 34, count 0 2006.239.08:24:48.64#ibcon#read 4, iclass 34, count 0 2006.239.08:24:48.64#ibcon#about to read 5, iclass 34, count 0 2006.239.08:24:48.64#ibcon#read 5, iclass 34, count 0 2006.239.08:24:48.64#ibcon#about to read 6, iclass 34, count 0 2006.239.08:24:48.64#ibcon#read 6, iclass 34, count 0 2006.239.08:24:48.64#ibcon#end of sib2, iclass 34, count 0 2006.239.08:24:48.64#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:24:48.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:24:48.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.239.08:24:48.64#ibcon#*before write, iclass 34, count 0 2006.239.08:24:48.64#ibcon#enter sib2, iclass 34, count 0 2006.239.08:24:48.64#ibcon#flushed, iclass 34, count 0 2006.239.08:24:48.64#ibcon#about to write, iclass 34, count 0 2006.239.08:24:48.64#ibcon#wrote, iclass 34, count 0 2006.239.08:24:48.64#ibcon#about to read 3, iclass 34, count 0 2006.239.08:24:48.68#ibcon#read 3, iclass 34, count 0 2006.239.08:24:48.68#ibcon#about to read 4, iclass 34, count 0 2006.239.08:24:48.68#ibcon#read 4, iclass 34, count 0 2006.239.08:24:48.68#ibcon#about to read 5, iclass 34, count 0 2006.239.08:24:48.68#ibcon#read 5, iclass 34, count 0 2006.239.08:24:48.68#ibcon#about to read 6, iclass 34, count 0 2006.239.08:24:48.68#ibcon#read 6, iclass 34, count 0 2006.239.08:24:48.68#ibcon#end of sib2, iclass 34, count 0 2006.239.08:24:48.68#ibcon#*after write, iclass 34, count 0 2006.239.08:24:48.68#ibcon#*before return 0, iclass 34, count 0 2006.239.08:24:48.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:48.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:48.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:24:48.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:24:48.68$vc4f8/va=6,7 2006.239.08:24:48.68#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.08:24:48.68#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.08:24:48.68#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:48.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:48.74#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:48.74#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:48.74#ibcon#enter wrdev, iclass 36, count 2 2006.239.08:24:48.74#ibcon#first serial, iclass 36, count 2 2006.239.08:24:48.74#ibcon#enter sib2, iclass 36, count 2 2006.239.08:24:48.74#ibcon#flushed, iclass 36, count 2 2006.239.08:24:48.74#ibcon#about to write, iclass 36, count 2 2006.239.08:24:48.74#ibcon#wrote, iclass 36, count 2 2006.239.08:24:48.74#ibcon#about to read 3, iclass 36, count 2 2006.239.08:24:48.76#ibcon#read 3, iclass 36, count 2 2006.239.08:24:48.76#ibcon#about to read 4, iclass 36, count 2 2006.239.08:24:48.76#ibcon#read 4, iclass 36, count 2 2006.239.08:24:48.76#ibcon#about to read 5, iclass 36, count 2 2006.239.08:24:48.76#ibcon#read 5, iclass 36, count 2 2006.239.08:24:48.76#ibcon#about to read 6, iclass 36, count 2 2006.239.08:24:48.76#ibcon#read 6, iclass 36, count 2 2006.239.08:24:48.76#ibcon#end of sib2, iclass 36, count 2 2006.239.08:24:48.76#ibcon#*mode == 0, iclass 36, count 2 2006.239.08:24:48.76#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.08:24:48.76#ibcon#[25=AT06-07\r\n] 2006.239.08:24:48.76#ibcon#*before write, iclass 36, count 2 2006.239.08:24:48.76#ibcon#enter sib2, iclass 36, count 2 2006.239.08:24:48.76#ibcon#flushed, iclass 36, count 2 2006.239.08:24:48.76#ibcon#about to write, iclass 36, count 2 2006.239.08:24:48.76#ibcon#wrote, iclass 36, count 2 2006.239.08:24:48.76#ibcon#about to read 3, iclass 36, count 2 2006.239.08:24:48.79#ibcon#read 3, iclass 36, count 2 2006.239.08:24:48.79#ibcon#about to read 4, iclass 36, count 2 2006.239.08:24:48.79#ibcon#read 4, iclass 36, count 2 2006.239.08:24:48.79#ibcon#about to read 5, iclass 36, count 2 2006.239.08:24:48.79#ibcon#read 5, iclass 36, count 2 2006.239.08:24:48.79#ibcon#about to read 6, iclass 36, count 2 2006.239.08:24:48.79#ibcon#read 6, iclass 36, count 2 2006.239.08:24:48.79#ibcon#end of sib2, iclass 36, count 2 2006.239.08:24:48.79#ibcon#*after write, iclass 36, count 2 2006.239.08:24:48.79#ibcon#*before return 0, iclass 36, count 2 2006.239.08:24:48.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:48.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:48.79#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.08:24:48.79#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:48.79#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:48.91#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:48.91#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:48.91#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:24:48.91#ibcon#first serial, iclass 36, count 0 2006.239.08:24:48.91#ibcon#enter sib2, iclass 36, count 0 2006.239.08:24:48.91#ibcon#flushed, iclass 36, count 0 2006.239.08:24:48.91#ibcon#about to write, iclass 36, count 0 2006.239.08:24:48.91#ibcon#wrote, iclass 36, count 0 2006.239.08:24:48.91#ibcon#about to read 3, iclass 36, count 0 2006.239.08:24:48.93#ibcon#read 3, iclass 36, count 0 2006.239.08:24:48.93#ibcon#about to read 4, iclass 36, count 0 2006.239.08:24:48.93#ibcon#read 4, iclass 36, count 0 2006.239.08:24:48.93#ibcon#about to read 5, iclass 36, count 0 2006.239.08:24:48.93#ibcon#read 5, iclass 36, count 0 2006.239.08:24:48.93#ibcon#about to read 6, iclass 36, count 0 2006.239.08:24:48.93#ibcon#read 6, iclass 36, count 0 2006.239.08:24:48.93#ibcon#end of sib2, iclass 36, count 0 2006.239.08:24:48.93#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:24:48.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:24:48.93#ibcon#[25=USB\r\n] 2006.239.08:24:48.93#ibcon#*before write, iclass 36, count 0 2006.239.08:24:48.93#ibcon#enter sib2, iclass 36, count 0 2006.239.08:24:48.93#ibcon#flushed, iclass 36, count 0 2006.239.08:24:48.93#ibcon#about to write, iclass 36, count 0 2006.239.08:24:48.93#ibcon#wrote, iclass 36, count 0 2006.239.08:24:48.93#ibcon#about to read 3, iclass 36, count 0 2006.239.08:24:48.93#abcon#<5=/04 2.2 4.4 24.91 781011.5\r\n> 2006.239.08:24:48.95#abcon#{5=INTERFACE CLEAR} 2006.239.08:24:48.96#ibcon#read 3, iclass 36, count 0 2006.239.08:24:48.96#ibcon#about to read 4, iclass 36, count 0 2006.239.08:24:48.96#ibcon#read 4, iclass 36, count 0 2006.239.08:24:48.96#ibcon#about to read 5, iclass 36, count 0 2006.239.08:24:48.96#ibcon#read 5, iclass 36, count 0 2006.239.08:24:48.96#ibcon#about to read 6, iclass 36, count 0 2006.239.08:24:48.96#ibcon#read 6, iclass 36, count 0 2006.239.08:24:48.96#ibcon#end of sib2, iclass 36, count 0 2006.239.08:24:48.96#ibcon#*after write, iclass 36, count 0 2006.239.08:24:48.96#ibcon#*before return 0, iclass 36, count 0 2006.239.08:24:48.96#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:48.96#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:48.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:24:48.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:24:48.96$vc4f8/valo=7,832.99 2006.239.08:24:48.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.239.08:24:48.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.239.08:24:48.96#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:48.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:24:48.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:24:48.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:24:48.96#ibcon#enter wrdev, iclass 3, count 0 2006.239.08:24:48.96#ibcon#first serial, iclass 3, count 0 2006.239.08:24:48.96#ibcon#enter sib2, iclass 3, count 0 2006.239.08:24:48.96#ibcon#flushed, iclass 3, count 0 2006.239.08:24:48.96#ibcon#about to write, iclass 3, count 0 2006.239.08:24:48.96#ibcon#wrote, iclass 3, count 0 2006.239.08:24:48.96#ibcon#about to read 3, iclass 3, count 0 2006.239.08:24:48.98#ibcon#read 3, iclass 3, count 0 2006.239.08:24:48.98#ibcon#about to read 4, iclass 3, count 0 2006.239.08:24:48.98#ibcon#read 4, iclass 3, count 0 2006.239.08:24:48.98#ibcon#about to read 5, iclass 3, count 0 2006.239.08:24:48.98#ibcon#read 5, iclass 3, count 0 2006.239.08:24:48.98#ibcon#about to read 6, iclass 3, count 0 2006.239.08:24:48.98#ibcon#read 6, iclass 3, count 0 2006.239.08:24:48.98#ibcon#end of sib2, iclass 3, count 0 2006.239.08:24:48.98#ibcon#*mode == 0, iclass 3, count 0 2006.239.08:24:48.98#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.239.08:24:48.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.239.08:24:48.98#ibcon#*before write, iclass 3, count 0 2006.239.08:24:48.98#ibcon#enter sib2, iclass 3, count 0 2006.239.08:24:48.98#ibcon#flushed, iclass 3, count 0 2006.239.08:24:48.98#ibcon#about to write, iclass 3, count 0 2006.239.08:24:48.98#ibcon#wrote, iclass 3, count 0 2006.239.08:24:48.98#ibcon#about to read 3, iclass 3, count 0 2006.239.08:24:49.01#abcon#[5=S1D000X0/0*\r\n] 2006.239.08:24:49.02#ibcon#read 3, iclass 3, count 0 2006.239.08:24:49.02#ibcon#about to read 4, iclass 3, count 0 2006.239.08:24:49.02#ibcon#read 4, iclass 3, count 0 2006.239.08:24:49.02#ibcon#about to read 5, iclass 3, count 0 2006.239.08:24:49.02#ibcon#read 5, iclass 3, count 0 2006.239.08:24:49.02#ibcon#about to read 6, iclass 3, count 0 2006.239.08:24:49.02#ibcon#read 6, iclass 3, count 0 2006.239.08:24:49.02#ibcon#end of sib2, iclass 3, count 0 2006.239.08:24:49.02#ibcon#*after write, iclass 3, count 0 2006.239.08:24:49.02#ibcon#*before return 0, iclass 3, count 0 2006.239.08:24:49.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:24:49.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.239.08:24:49.02#ibcon#about to clear, iclass 3 cls_cnt 0 2006.239.08:24:49.02#ibcon#cleared, iclass 3 cls_cnt 0 2006.239.08:24:49.02$vc4f8/va=7,7 2006.239.08:24:49.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.239.08:24:49.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.239.08:24:49.02#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:49.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:24:49.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:24:49.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:24:49.08#ibcon#enter wrdev, iclass 6, count 2 2006.239.08:24:49.08#ibcon#first serial, iclass 6, count 2 2006.239.08:24:49.08#ibcon#enter sib2, iclass 6, count 2 2006.239.08:24:49.08#ibcon#flushed, iclass 6, count 2 2006.239.08:24:49.08#ibcon#about to write, iclass 6, count 2 2006.239.08:24:49.08#ibcon#wrote, iclass 6, count 2 2006.239.08:24:49.08#ibcon#about to read 3, iclass 6, count 2 2006.239.08:24:49.10#ibcon#read 3, iclass 6, count 2 2006.239.08:24:49.10#ibcon#about to read 4, iclass 6, count 2 2006.239.08:24:49.10#ibcon#read 4, iclass 6, count 2 2006.239.08:24:49.10#ibcon#about to read 5, iclass 6, count 2 2006.239.08:24:49.10#ibcon#read 5, iclass 6, count 2 2006.239.08:24:49.10#ibcon#about to read 6, iclass 6, count 2 2006.239.08:24:49.10#ibcon#read 6, iclass 6, count 2 2006.239.08:24:49.10#ibcon#end of sib2, iclass 6, count 2 2006.239.08:24:49.10#ibcon#*mode == 0, iclass 6, count 2 2006.239.08:24:49.10#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.239.08:24:49.10#ibcon#[25=AT07-07\r\n] 2006.239.08:24:49.10#ibcon#*before write, iclass 6, count 2 2006.239.08:24:49.10#ibcon#enter sib2, iclass 6, count 2 2006.239.08:24:49.10#ibcon#flushed, iclass 6, count 2 2006.239.08:24:49.10#ibcon#about to write, iclass 6, count 2 2006.239.08:24:49.10#ibcon#wrote, iclass 6, count 2 2006.239.08:24:49.10#ibcon#about to read 3, iclass 6, count 2 2006.239.08:24:49.13#ibcon#read 3, iclass 6, count 2 2006.239.08:24:49.13#ibcon#about to read 4, iclass 6, count 2 2006.239.08:24:49.13#ibcon#read 4, iclass 6, count 2 2006.239.08:24:49.13#ibcon#about to read 5, iclass 6, count 2 2006.239.08:24:49.13#ibcon#read 5, iclass 6, count 2 2006.239.08:24:49.13#ibcon#about to read 6, iclass 6, count 2 2006.239.08:24:49.13#ibcon#read 6, iclass 6, count 2 2006.239.08:24:49.13#ibcon#end of sib2, iclass 6, count 2 2006.239.08:24:49.13#ibcon#*after write, iclass 6, count 2 2006.239.08:24:49.13#ibcon#*before return 0, iclass 6, count 2 2006.239.08:24:49.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:24:49.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.239.08:24:49.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.239.08:24:49.13#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:49.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:24:49.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:24:49.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:24:49.25#ibcon#enter wrdev, iclass 6, count 0 2006.239.08:24:49.25#ibcon#first serial, iclass 6, count 0 2006.239.08:24:49.25#ibcon#enter sib2, iclass 6, count 0 2006.239.08:24:49.25#ibcon#flushed, iclass 6, count 0 2006.239.08:24:49.25#ibcon#about to write, iclass 6, count 0 2006.239.08:24:49.25#ibcon#wrote, iclass 6, count 0 2006.239.08:24:49.25#ibcon#about to read 3, iclass 6, count 0 2006.239.08:24:49.27#ibcon#read 3, iclass 6, count 0 2006.239.08:24:49.27#ibcon#about to read 4, iclass 6, count 0 2006.239.08:24:49.27#ibcon#read 4, iclass 6, count 0 2006.239.08:24:49.27#ibcon#about to read 5, iclass 6, count 0 2006.239.08:24:49.27#ibcon#read 5, iclass 6, count 0 2006.239.08:24:49.27#ibcon#about to read 6, iclass 6, count 0 2006.239.08:24:49.27#ibcon#read 6, iclass 6, count 0 2006.239.08:24:49.27#ibcon#end of sib2, iclass 6, count 0 2006.239.08:24:49.27#ibcon#*mode == 0, iclass 6, count 0 2006.239.08:24:49.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.239.08:24:49.27#ibcon#[25=USB\r\n] 2006.239.08:24:49.27#ibcon#*before write, iclass 6, count 0 2006.239.08:24:49.27#ibcon#enter sib2, iclass 6, count 0 2006.239.08:24:49.27#ibcon#flushed, iclass 6, count 0 2006.239.08:24:49.27#ibcon#about to write, iclass 6, count 0 2006.239.08:24:49.27#ibcon#wrote, iclass 6, count 0 2006.239.08:24:49.27#ibcon#about to read 3, iclass 6, count 0 2006.239.08:24:49.30#ibcon#read 3, iclass 6, count 0 2006.239.08:24:49.30#ibcon#about to read 4, iclass 6, count 0 2006.239.08:24:49.30#ibcon#read 4, iclass 6, count 0 2006.239.08:24:49.30#ibcon#about to read 5, iclass 6, count 0 2006.239.08:24:49.30#ibcon#read 5, iclass 6, count 0 2006.239.08:24:49.30#ibcon#about to read 6, iclass 6, count 0 2006.239.08:24:49.30#ibcon#read 6, iclass 6, count 0 2006.239.08:24:49.30#ibcon#end of sib2, iclass 6, count 0 2006.239.08:24:49.30#ibcon#*after write, iclass 6, count 0 2006.239.08:24:49.30#ibcon#*before return 0, iclass 6, count 0 2006.239.08:24:49.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:24:49.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.239.08:24:49.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.239.08:24:49.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.239.08:24:49.30$vc4f8/valo=8,852.99 2006.239.08:24:49.30#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.239.08:24:49.30#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.239.08:24:49.30#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:49.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:24:49.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:24:49.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:24:49.30#ibcon#enter wrdev, iclass 10, count 0 2006.239.08:24:49.30#ibcon#first serial, iclass 10, count 0 2006.239.08:24:49.30#ibcon#enter sib2, iclass 10, count 0 2006.239.08:24:49.30#ibcon#flushed, iclass 10, count 0 2006.239.08:24:49.30#ibcon#about to write, iclass 10, count 0 2006.239.08:24:49.30#ibcon#wrote, iclass 10, count 0 2006.239.08:24:49.30#ibcon#about to read 3, iclass 10, count 0 2006.239.08:24:49.33#ibcon#read 3, iclass 10, count 0 2006.239.08:24:49.33#ibcon#about to read 4, iclass 10, count 0 2006.239.08:24:49.33#ibcon#read 4, iclass 10, count 0 2006.239.08:24:49.33#ibcon#about to read 5, iclass 10, count 0 2006.239.08:24:49.33#ibcon#read 5, iclass 10, count 0 2006.239.08:24:49.33#ibcon#about to read 6, iclass 10, count 0 2006.239.08:24:49.33#ibcon#read 6, iclass 10, count 0 2006.239.08:24:49.33#ibcon#end of sib2, iclass 10, count 0 2006.239.08:24:49.33#ibcon#*mode == 0, iclass 10, count 0 2006.239.08:24:49.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.239.08:24:49.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.239.08:24:49.33#ibcon#*before write, iclass 10, count 0 2006.239.08:24:49.33#ibcon#enter sib2, iclass 10, count 0 2006.239.08:24:49.33#ibcon#flushed, iclass 10, count 0 2006.239.08:24:49.33#ibcon#about to write, iclass 10, count 0 2006.239.08:24:49.33#ibcon#wrote, iclass 10, count 0 2006.239.08:24:49.33#ibcon#about to read 3, iclass 10, count 0 2006.239.08:24:49.37#ibcon#read 3, iclass 10, count 0 2006.239.08:24:49.37#ibcon#about to read 4, iclass 10, count 0 2006.239.08:24:49.37#ibcon#read 4, iclass 10, count 0 2006.239.08:24:49.37#ibcon#about to read 5, iclass 10, count 0 2006.239.08:24:49.37#ibcon#read 5, iclass 10, count 0 2006.239.08:24:49.37#ibcon#about to read 6, iclass 10, count 0 2006.239.08:24:49.37#ibcon#read 6, iclass 10, count 0 2006.239.08:24:49.37#ibcon#end of sib2, iclass 10, count 0 2006.239.08:24:49.37#ibcon#*after write, iclass 10, count 0 2006.239.08:24:49.37#ibcon#*before return 0, iclass 10, count 0 2006.239.08:24:49.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:24:49.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.239.08:24:49.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.239.08:24:49.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.239.08:24:49.37$vc4f8/va=8,7 2006.239.08:24:49.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.239.08:24:49.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.239.08:24:49.37#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:49.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:24:49.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:24:49.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:24:49.42#ibcon#enter wrdev, iclass 12, count 2 2006.239.08:24:49.42#ibcon#first serial, iclass 12, count 2 2006.239.08:24:49.42#ibcon#enter sib2, iclass 12, count 2 2006.239.08:24:49.42#ibcon#flushed, iclass 12, count 2 2006.239.08:24:49.42#ibcon#about to write, iclass 12, count 2 2006.239.08:24:49.42#ibcon#wrote, iclass 12, count 2 2006.239.08:24:49.42#ibcon#about to read 3, iclass 12, count 2 2006.239.08:24:49.44#ibcon#read 3, iclass 12, count 2 2006.239.08:24:49.44#ibcon#about to read 4, iclass 12, count 2 2006.239.08:24:49.44#ibcon#read 4, iclass 12, count 2 2006.239.08:24:49.44#ibcon#about to read 5, iclass 12, count 2 2006.239.08:24:49.44#ibcon#read 5, iclass 12, count 2 2006.239.08:24:49.44#ibcon#about to read 6, iclass 12, count 2 2006.239.08:24:49.44#ibcon#read 6, iclass 12, count 2 2006.239.08:24:49.44#ibcon#end of sib2, iclass 12, count 2 2006.239.08:24:49.44#ibcon#*mode == 0, iclass 12, count 2 2006.239.08:24:49.44#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.239.08:24:49.44#ibcon#[25=AT08-07\r\n] 2006.239.08:24:49.44#ibcon#*before write, iclass 12, count 2 2006.239.08:24:49.44#ibcon#enter sib2, iclass 12, count 2 2006.239.08:24:49.44#ibcon#flushed, iclass 12, count 2 2006.239.08:24:49.44#ibcon#about to write, iclass 12, count 2 2006.239.08:24:49.44#ibcon#wrote, iclass 12, count 2 2006.239.08:24:49.44#ibcon#about to read 3, iclass 12, count 2 2006.239.08:24:49.47#ibcon#read 3, iclass 12, count 2 2006.239.08:24:49.47#ibcon#about to read 4, iclass 12, count 2 2006.239.08:24:49.48#ibcon#read 4, iclass 12, count 2 2006.239.08:24:49.48#ibcon#about to read 5, iclass 12, count 2 2006.239.08:24:49.48#ibcon#read 5, iclass 12, count 2 2006.239.08:24:49.48#ibcon#about to read 6, iclass 12, count 2 2006.239.08:24:49.48#ibcon#read 6, iclass 12, count 2 2006.239.08:24:49.48#ibcon#end of sib2, iclass 12, count 2 2006.239.08:24:49.48#ibcon#*after write, iclass 12, count 2 2006.239.08:24:49.48#ibcon#*before return 0, iclass 12, count 2 2006.239.08:24:49.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:24:49.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.239.08:24:49.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.239.08:24:49.48#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:49.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:24:49.59#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:24:49.59#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:24:49.59#ibcon#enter wrdev, iclass 12, count 0 2006.239.08:24:49.59#ibcon#first serial, iclass 12, count 0 2006.239.08:24:49.59#ibcon#enter sib2, iclass 12, count 0 2006.239.08:24:49.59#ibcon#flushed, iclass 12, count 0 2006.239.08:24:49.59#ibcon#about to write, iclass 12, count 0 2006.239.08:24:49.59#ibcon#wrote, iclass 12, count 0 2006.239.08:24:49.59#ibcon#about to read 3, iclass 12, count 0 2006.239.08:24:49.61#ibcon#read 3, iclass 12, count 0 2006.239.08:24:49.61#ibcon#about to read 4, iclass 12, count 0 2006.239.08:24:49.61#ibcon#read 4, iclass 12, count 0 2006.239.08:24:49.61#ibcon#about to read 5, iclass 12, count 0 2006.239.08:24:49.61#ibcon#read 5, iclass 12, count 0 2006.239.08:24:49.61#ibcon#about to read 6, iclass 12, count 0 2006.239.08:24:49.61#ibcon#read 6, iclass 12, count 0 2006.239.08:24:49.61#ibcon#end of sib2, iclass 12, count 0 2006.239.08:24:49.61#ibcon#*mode == 0, iclass 12, count 0 2006.239.08:24:49.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.239.08:24:49.61#ibcon#[25=USB\r\n] 2006.239.08:24:49.61#ibcon#*before write, iclass 12, count 0 2006.239.08:24:49.61#ibcon#enter sib2, iclass 12, count 0 2006.239.08:24:49.61#ibcon#flushed, iclass 12, count 0 2006.239.08:24:49.61#ibcon#about to write, iclass 12, count 0 2006.239.08:24:49.61#ibcon#wrote, iclass 12, count 0 2006.239.08:24:49.61#ibcon#about to read 3, iclass 12, count 0 2006.239.08:24:49.64#ibcon#read 3, iclass 12, count 0 2006.239.08:24:49.64#ibcon#about to read 4, iclass 12, count 0 2006.239.08:24:49.64#ibcon#read 4, iclass 12, count 0 2006.239.08:24:49.64#ibcon#about to read 5, iclass 12, count 0 2006.239.08:24:49.64#ibcon#read 5, iclass 12, count 0 2006.239.08:24:49.64#ibcon#about to read 6, iclass 12, count 0 2006.239.08:24:49.64#ibcon#read 6, iclass 12, count 0 2006.239.08:24:49.64#ibcon#end of sib2, iclass 12, count 0 2006.239.08:24:49.64#ibcon#*after write, iclass 12, count 0 2006.239.08:24:49.64#ibcon#*before return 0, iclass 12, count 0 2006.239.08:24:49.64#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:24:49.64#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.239.08:24:49.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.239.08:24:49.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.239.08:24:49.64$vc4f8/vblo=1,632.99 2006.239.08:24:49.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.239.08:24:49.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.239.08:24:49.64#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:49.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:49.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:49.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:49.64#ibcon#enter wrdev, iclass 14, count 0 2006.239.08:24:49.64#ibcon#first serial, iclass 14, count 0 2006.239.08:24:49.64#ibcon#enter sib2, iclass 14, count 0 2006.239.08:24:49.64#ibcon#flushed, iclass 14, count 0 2006.239.08:24:49.64#ibcon#about to write, iclass 14, count 0 2006.239.08:24:49.64#ibcon#wrote, iclass 14, count 0 2006.239.08:24:49.64#ibcon#about to read 3, iclass 14, count 0 2006.239.08:24:49.66#ibcon#read 3, iclass 14, count 0 2006.239.08:24:49.66#ibcon#about to read 4, iclass 14, count 0 2006.239.08:24:49.66#ibcon#read 4, iclass 14, count 0 2006.239.08:24:49.66#ibcon#about to read 5, iclass 14, count 0 2006.239.08:24:49.66#ibcon#read 5, iclass 14, count 0 2006.239.08:24:49.66#ibcon#about to read 6, iclass 14, count 0 2006.239.08:24:49.66#ibcon#read 6, iclass 14, count 0 2006.239.08:24:49.66#ibcon#end of sib2, iclass 14, count 0 2006.239.08:24:49.66#ibcon#*mode == 0, iclass 14, count 0 2006.239.08:24:49.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.239.08:24:49.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.239.08:24:49.66#ibcon#*before write, iclass 14, count 0 2006.239.08:24:49.66#ibcon#enter sib2, iclass 14, count 0 2006.239.08:24:49.66#ibcon#flushed, iclass 14, count 0 2006.239.08:24:49.66#ibcon#about to write, iclass 14, count 0 2006.239.08:24:49.66#ibcon#wrote, iclass 14, count 0 2006.239.08:24:49.66#ibcon#about to read 3, iclass 14, count 0 2006.239.08:24:49.70#ibcon#read 3, iclass 14, count 0 2006.239.08:24:49.70#ibcon#about to read 4, iclass 14, count 0 2006.239.08:24:49.70#ibcon#read 4, iclass 14, count 0 2006.239.08:24:49.70#ibcon#about to read 5, iclass 14, count 0 2006.239.08:24:49.70#ibcon#read 5, iclass 14, count 0 2006.239.08:24:49.70#ibcon#about to read 6, iclass 14, count 0 2006.239.08:24:49.70#ibcon#read 6, iclass 14, count 0 2006.239.08:24:49.70#ibcon#end of sib2, iclass 14, count 0 2006.239.08:24:49.70#ibcon#*after write, iclass 14, count 0 2006.239.08:24:49.70#ibcon#*before return 0, iclass 14, count 0 2006.239.08:24:49.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:49.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.239.08:24:49.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.239.08:24:49.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.239.08:24:49.70$vc4f8/vb=1,4 2006.239.08:24:49.70#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.239.08:24:49.70#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.239.08:24:49.70#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:49.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:49.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:49.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:49.70#ibcon#enter wrdev, iclass 16, count 2 2006.239.08:24:49.70#ibcon#first serial, iclass 16, count 2 2006.239.08:24:49.70#ibcon#enter sib2, iclass 16, count 2 2006.239.08:24:49.70#ibcon#flushed, iclass 16, count 2 2006.239.08:24:49.70#ibcon#about to write, iclass 16, count 2 2006.239.08:24:49.70#ibcon#wrote, iclass 16, count 2 2006.239.08:24:49.70#ibcon#about to read 3, iclass 16, count 2 2006.239.08:24:49.72#ibcon#read 3, iclass 16, count 2 2006.239.08:24:49.72#ibcon#about to read 4, iclass 16, count 2 2006.239.08:24:49.72#ibcon#read 4, iclass 16, count 2 2006.239.08:24:49.72#ibcon#about to read 5, iclass 16, count 2 2006.239.08:24:49.72#ibcon#read 5, iclass 16, count 2 2006.239.08:24:49.72#ibcon#about to read 6, iclass 16, count 2 2006.239.08:24:49.72#ibcon#read 6, iclass 16, count 2 2006.239.08:24:49.72#ibcon#end of sib2, iclass 16, count 2 2006.239.08:24:49.72#ibcon#*mode == 0, iclass 16, count 2 2006.239.08:24:49.72#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.239.08:24:49.72#ibcon#[27=AT01-04\r\n] 2006.239.08:24:49.72#ibcon#*before write, iclass 16, count 2 2006.239.08:24:49.72#ibcon#enter sib2, iclass 16, count 2 2006.239.08:24:49.72#ibcon#flushed, iclass 16, count 2 2006.239.08:24:49.72#ibcon#about to write, iclass 16, count 2 2006.239.08:24:49.72#ibcon#wrote, iclass 16, count 2 2006.239.08:24:49.72#ibcon#about to read 3, iclass 16, count 2 2006.239.08:24:49.75#ibcon#read 3, iclass 16, count 2 2006.239.08:24:49.75#ibcon#about to read 4, iclass 16, count 2 2006.239.08:24:49.75#ibcon#read 4, iclass 16, count 2 2006.239.08:24:49.75#ibcon#about to read 5, iclass 16, count 2 2006.239.08:24:49.75#ibcon#read 5, iclass 16, count 2 2006.239.08:24:49.75#ibcon#about to read 6, iclass 16, count 2 2006.239.08:24:49.75#ibcon#read 6, iclass 16, count 2 2006.239.08:24:49.75#ibcon#end of sib2, iclass 16, count 2 2006.239.08:24:49.75#ibcon#*after write, iclass 16, count 2 2006.239.08:24:49.75#ibcon#*before return 0, iclass 16, count 2 2006.239.08:24:49.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:49.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.239.08:24:49.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.239.08:24:49.75#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:49.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:49.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:49.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:49.87#ibcon#enter wrdev, iclass 16, count 0 2006.239.08:24:49.87#ibcon#first serial, iclass 16, count 0 2006.239.08:24:49.87#ibcon#enter sib2, iclass 16, count 0 2006.239.08:24:49.87#ibcon#flushed, iclass 16, count 0 2006.239.08:24:49.87#ibcon#about to write, iclass 16, count 0 2006.239.08:24:49.87#ibcon#wrote, iclass 16, count 0 2006.239.08:24:49.87#ibcon#about to read 3, iclass 16, count 0 2006.239.08:24:49.89#ibcon#read 3, iclass 16, count 0 2006.239.08:24:49.89#ibcon#about to read 4, iclass 16, count 0 2006.239.08:24:49.89#ibcon#read 4, iclass 16, count 0 2006.239.08:24:49.89#ibcon#about to read 5, iclass 16, count 0 2006.239.08:24:49.89#ibcon#read 5, iclass 16, count 0 2006.239.08:24:49.89#ibcon#about to read 6, iclass 16, count 0 2006.239.08:24:49.89#ibcon#read 6, iclass 16, count 0 2006.239.08:24:49.89#ibcon#end of sib2, iclass 16, count 0 2006.239.08:24:49.89#ibcon#*mode == 0, iclass 16, count 0 2006.239.08:24:49.89#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.239.08:24:49.89#ibcon#[27=USB\r\n] 2006.239.08:24:49.89#ibcon#*before write, iclass 16, count 0 2006.239.08:24:49.89#ibcon#enter sib2, iclass 16, count 0 2006.239.08:24:49.89#ibcon#flushed, iclass 16, count 0 2006.239.08:24:49.89#ibcon#about to write, iclass 16, count 0 2006.239.08:24:49.89#ibcon#wrote, iclass 16, count 0 2006.239.08:24:49.89#ibcon#about to read 3, iclass 16, count 0 2006.239.08:24:49.92#ibcon#read 3, iclass 16, count 0 2006.239.08:24:49.92#ibcon#about to read 4, iclass 16, count 0 2006.239.08:24:49.92#ibcon#read 4, iclass 16, count 0 2006.239.08:24:49.92#ibcon#about to read 5, iclass 16, count 0 2006.239.08:24:49.92#ibcon#read 5, iclass 16, count 0 2006.239.08:24:49.92#ibcon#about to read 6, iclass 16, count 0 2006.239.08:24:49.92#ibcon#read 6, iclass 16, count 0 2006.239.08:24:49.92#ibcon#end of sib2, iclass 16, count 0 2006.239.08:24:49.92#ibcon#*after write, iclass 16, count 0 2006.239.08:24:49.92#ibcon#*before return 0, iclass 16, count 0 2006.239.08:24:49.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:49.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.239.08:24:49.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.239.08:24:49.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.239.08:24:49.92$vc4f8/vblo=2,640.99 2006.239.08:24:49.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.239.08:24:49.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.239.08:24:49.92#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:49.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:49.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:49.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:49.92#ibcon#enter wrdev, iclass 18, count 0 2006.239.08:24:49.92#ibcon#first serial, iclass 18, count 0 2006.239.08:24:49.92#ibcon#enter sib2, iclass 18, count 0 2006.239.08:24:49.92#ibcon#flushed, iclass 18, count 0 2006.239.08:24:49.92#ibcon#about to write, iclass 18, count 0 2006.239.08:24:49.92#ibcon#wrote, iclass 18, count 0 2006.239.08:24:49.92#ibcon#about to read 3, iclass 18, count 0 2006.239.08:24:49.94#ibcon#read 3, iclass 18, count 0 2006.239.08:24:49.94#ibcon#about to read 4, iclass 18, count 0 2006.239.08:24:49.94#ibcon#read 4, iclass 18, count 0 2006.239.08:24:49.94#ibcon#about to read 5, iclass 18, count 0 2006.239.08:24:49.94#ibcon#read 5, iclass 18, count 0 2006.239.08:24:49.94#ibcon#about to read 6, iclass 18, count 0 2006.239.08:24:49.94#ibcon#read 6, iclass 18, count 0 2006.239.08:24:49.94#ibcon#end of sib2, iclass 18, count 0 2006.239.08:24:49.94#ibcon#*mode == 0, iclass 18, count 0 2006.239.08:24:49.94#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.239.08:24:49.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.239.08:24:49.94#ibcon#*before write, iclass 18, count 0 2006.239.08:24:49.94#ibcon#enter sib2, iclass 18, count 0 2006.239.08:24:49.94#ibcon#flushed, iclass 18, count 0 2006.239.08:24:49.94#ibcon#about to write, iclass 18, count 0 2006.239.08:24:49.94#ibcon#wrote, iclass 18, count 0 2006.239.08:24:49.94#ibcon#about to read 3, iclass 18, count 0 2006.239.08:24:49.98#ibcon#read 3, iclass 18, count 0 2006.239.08:24:49.98#ibcon#about to read 4, iclass 18, count 0 2006.239.08:24:49.98#ibcon#read 4, iclass 18, count 0 2006.239.08:24:49.98#ibcon#about to read 5, iclass 18, count 0 2006.239.08:24:49.98#ibcon#read 5, iclass 18, count 0 2006.239.08:24:49.98#ibcon#about to read 6, iclass 18, count 0 2006.239.08:24:49.98#ibcon#read 6, iclass 18, count 0 2006.239.08:24:49.98#ibcon#end of sib2, iclass 18, count 0 2006.239.08:24:49.98#ibcon#*after write, iclass 18, count 0 2006.239.08:24:49.98#ibcon#*before return 0, iclass 18, count 0 2006.239.08:24:49.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:49.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.239.08:24:49.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.239.08:24:49.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.239.08:24:49.98$vc4f8/vb=2,4 2006.239.08:24:49.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.239.08:24:49.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.239.08:24:49.98#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:49.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:50.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:50.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:50.04#ibcon#enter wrdev, iclass 20, count 2 2006.239.08:24:50.04#ibcon#first serial, iclass 20, count 2 2006.239.08:24:50.04#ibcon#enter sib2, iclass 20, count 2 2006.239.08:24:50.04#ibcon#flushed, iclass 20, count 2 2006.239.08:24:50.04#ibcon#about to write, iclass 20, count 2 2006.239.08:24:50.04#ibcon#wrote, iclass 20, count 2 2006.239.08:24:50.04#ibcon#about to read 3, iclass 20, count 2 2006.239.08:24:50.06#ibcon#read 3, iclass 20, count 2 2006.239.08:24:50.06#ibcon#about to read 4, iclass 20, count 2 2006.239.08:24:50.06#ibcon#read 4, iclass 20, count 2 2006.239.08:24:50.06#ibcon#about to read 5, iclass 20, count 2 2006.239.08:24:50.06#ibcon#read 5, iclass 20, count 2 2006.239.08:24:50.06#ibcon#about to read 6, iclass 20, count 2 2006.239.08:24:50.06#ibcon#read 6, iclass 20, count 2 2006.239.08:24:50.06#ibcon#end of sib2, iclass 20, count 2 2006.239.08:24:50.06#ibcon#*mode == 0, iclass 20, count 2 2006.239.08:24:50.06#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.239.08:24:50.06#ibcon#[27=AT02-04\r\n] 2006.239.08:24:50.06#ibcon#*before write, iclass 20, count 2 2006.239.08:24:50.06#ibcon#enter sib2, iclass 20, count 2 2006.239.08:24:50.06#ibcon#flushed, iclass 20, count 2 2006.239.08:24:50.06#ibcon#about to write, iclass 20, count 2 2006.239.08:24:50.06#ibcon#wrote, iclass 20, count 2 2006.239.08:24:50.06#ibcon#about to read 3, iclass 20, count 2 2006.239.08:24:50.09#ibcon#read 3, iclass 20, count 2 2006.239.08:24:50.09#ibcon#about to read 4, iclass 20, count 2 2006.239.08:24:50.09#ibcon#read 4, iclass 20, count 2 2006.239.08:24:50.09#ibcon#about to read 5, iclass 20, count 2 2006.239.08:24:50.09#ibcon#read 5, iclass 20, count 2 2006.239.08:24:50.09#ibcon#about to read 6, iclass 20, count 2 2006.239.08:24:50.09#ibcon#read 6, iclass 20, count 2 2006.239.08:24:50.09#ibcon#end of sib2, iclass 20, count 2 2006.239.08:24:50.09#ibcon#*after write, iclass 20, count 2 2006.239.08:24:50.09#ibcon#*before return 0, iclass 20, count 2 2006.239.08:24:50.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:50.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.239.08:24:50.09#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.239.08:24:50.09#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:50.09#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:50.21#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:50.21#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:50.21#ibcon#enter wrdev, iclass 20, count 0 2006.239.08:24:50.21#ibcon#first serial, iclass 20, count 0 2006.239.08:24:50.21#ibcon#enter sib2, iclass 20, count 0 2006.239.08:24:50.21#ibcon#flushed, iclass 20, count 0 2006.239.08:24:50.21#ibcon#about to write, iclass 20, count 0 2006.239.08:24:50.21#ibcon#wrote, iclass 20, count 0 2006.239.08:24:50.21#ibcon#about to read 3, iclass 20, count 0 2006.239.08:24:50.23#ibcon#read 3, iclass 20, count 0 2006.239.08:24:50.23#ibcon#about to read 4, iclass 20, count 0 2006.239.08:24:50.23#ibcon#read 4, iclass 20, count 0 2006.239.08:24:50.23#ibcon#about to read 5, iclass 20, count 0 2006.239.08:24:50.23#ibcon#read 5, iclass 20, count 0 2006.239.08:24:50.23#ibcon#about to read 6, iclass 20, count 0 2006.239.08:24:50.23#ibcon#read 6, iclass 20, count 0 2006.239.08:24:50.23#ibcon#end of sib2, iclass 20, count 0 2006.239.08:24:50.23#ibcon#*mode == 0, iclass 20, count 0 2006.239.08:24:50.23#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.239.08:24:50.23#ibcon#[27=USB\r\n] 2006.239.08:24:50.23#ibcon#*before write, iclass 20, count 0 2006.239.08:24:50.23#ibcon#enter sib2, iclass 20, count 0 2006.239.08:24:50.23#ibcon#flushed, iclass 20, count 0 2006.239.08:24:50.23#ibcon#about to write, iclass 20, count 0 2006.239.08:24:50.23#ibcon#wrote, iclass 20, count 0 2006.239.08:24:50.23#ibcon#about to read 3, iclass 20, count 0 2006.239.08:24:50.26#ibcon#read 3, iclass 20, count 0 2006.239.08:24:50.26#ibcon#about to read 4, iclass 20, count 0 2006.239.08:24:50.26#ibcon#read 4, iclass 20, count 0 2006.239.08:24:50.26#ibcon#about to read 5, iclass 20, count 0 2006.239.08:24:50.26#ibcon#read 5, iclass 20, count 0 2006.239.08:24:50.26#ibcon#about to read 6, iclass 20, count 0 2006.239.08:24:50.26#ibcon#read 6, iclass 20, count 0 2006.239.08:24:50.26#ibcon#end of sib2, iclass 20, count 0 2006.239.08:24:50.26#ibcon#*after write, iclass 20, count 0 2006.239.08:24:50.26#ibcon#*before return 0, iclass 20, count 0 2006.239.08:24:50.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:50.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.239.08:24:50.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.239.08:24:50.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.239.08:24:50.26$vc4f8/vblo=3,656.99 2006.239.08:24:50.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.239.08:24:50.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.239.08:24:50.26#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:50.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:50.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:50.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:50.26#ibcon#enter wrdev, iclass 22, count 0 2006.239.08:24:50.26#ibcon#first serial, iclass 22, count 0 2006.239.08:24:50.26#ibcon#enter sib2, iclass 22, count 0 2006.239.08:24:50.26#ibcon#flushed, iclass 22, count 0 2006.239.08:24:50.26#ibcon#about to write, iclass 22, count 0 2006.239.08:24:50.26#ibcon#wrote, iclass 22, count 0 2006.239.08:24:50.26#ibcon#about to read 3, iclass 22, count 0 2006.239.08:24:50.28#ibcon#read 3, iclass 22, count 0 2006.239.08:24:50.28#ibcon#about to read 4, iclass 22, count 0 2006.239.08:24:50.28#ibcon#read 4, iclass 22, count 0 2006.239.08:24:50.28#ibcon#about to read 5, iclass 22, count 0 2006.239.08:24:50.28#ibcon#read 5, iclass 22, count 0 2006.239.08:24:50.28#ibcon#about to read 6, iclass 22, count 0 2006.239.08:24:50.28#ibcon#read 6, iclass 22, count 0 2006.239.08:24:50.28#ibcon#end of sib2, iclass 22, count 0 2006.239.08:24:50.28#ibcon#*mode == 0, iclass 22, count 0 2006.239.08:24:50.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.239.08:24:50.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.239.08:24:50.28#ibcon#*before write, iclass 22, count 0 2006.239.08:24:50.28#ibcon#enter sib2, iclass 22, count 0 2006.239.08:24:50.28#ibcon#flushed, iclass 22, count 0 2006.239.08:24:50.28#ibcon#about to write, iclass 22, count 0 2006.239.08:24:50.28#ibcon#wrote, iclass 22, count 0 2006.239.08:24:50.28#ibcon#about to read 3, iclass 22, count 0 2006.239.08:24:50.32#ibcon#read 3, iclass 22, count 0 2006.239.08:24:50.32#ibcon#about to read 4, iclass 22, count 0 2006.239.08:24:50.32#ibcon#read 4, iclass 22, count 0 2006.239.08:24:50.32#ibcon#about to read 5, iclass 22, count 0 2006.239.08:24:50.32#ibcon#read 5, iclass 22, count 0 2006.239.08:24:50.32#ibcon#about to read 6, iclass 22, count 0 2006.239.08:24:50.32#ibcon#read 6, iclass 22, count 0 2006.239.08:24:50.32#ibcon#end of sib2, iclass 22, count 0 2006.239.08:24:50.32#ibcon#*after write, iclass 22, count 0 2006.239.08:24:50.32#ibcon#*before return 0, iclass 22, count 0 2006.239.08:24:50.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:50.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.239.08:24:50.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.239.08:24:50.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.239.08:24:50.32$vc4f8/vb=3,4 2006.239.08:24:50.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.239.08:24:50.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.239.08:24:50.32#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:50.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:50.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:50.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:50.38#ibcon#enter wrdev, iclass 24, count 2 2006.239.08:24:50.38#ibcon#first serial, iclass 24, count 2 2006.239.08:24:50.38#ibcon#enter sib2, iclass 24, count 2 2006.239.08:24:50.38#ibcon#flushed, iclass 24, count 2 2006.239.08:24:50.38#ibcon#about to write, iclass 24, count 2 2006.239.08:24:50.38#ibcon#wrote, iclass 24, count 2 2006.239.08:24:50.38#ibcon#about to read 3, iclass 24, count 2 2006.239.08:24:50.40#ibcon#read 3, iclass 24, count 2 2006.239.08:24:50.40#ibcon#about to read 4, iclass 24, count 2 2006.239.08:24:50.40#ibcon#read 4, iclass 24, count 2 2006.239.08:24:50.40#ibcon#about to read 5, iclass 24, count 2 2006.239.08:24:50.40#ibcon#read 5, iclass 24, count 2 2006.239.08:24:50.40#ibcon#about to read 6, iclass 24, count 2 2006.239.08:24:50.40#ibcon#read 6, iclass 24, count 2 2006.239.08:24:50.40#ibcon#end of sib2, iclass 24, count 2 2006.239.08:24:50.40#ibcon#*mode == 0, iclass 24, count 2 2006.239.08:24:50.40#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.239.08:24:50.40#ibcon#[27=AT03-04\r\n] 2006.239.08:24:50.40#ibcon#*before write, iclass 24, count 2 2006.239.08:24:50.40#ibcon#enter sib2, iclass 24, count 2 2006.239.08:24:50.40#ibcon#flushed, iclass 24, count 2 2006.239.08:24:50.40#ibcon#about to write, iclass 24, count 2 2006.239.08:24:50.40#ibcon#wrote, iclass 24, count 2 2006.239.08:24:50.40#ibcon#about to read 3, iclass 24, count 2 2006.239.08:24:50.43#ibcon#read 3, iclass 24, count 2 2006.239.08:24:50.43#ibcon#about to read 4, iclass 24, count 2 2006.239.08:24:50.43#ibcon#read 4, iclass 24, count 2 2006.239.08:24:50.43#ibcon#about to read 5, iclass 24, count 2 2006.239.08:24:50.43#ibcon#read 5, iclass 24, count 2 2006.239.08:24:50.43#ibcon#about to read 6, iclass 24, count 2 2006.239.08:24:50.43#ibcon#read 6, iclass 24, count 2 2006.239.08:24:50.43#ibcon#end of sib2, iclass 24, count 2 2006.239.08:24:50.43#ibcon#*after write, iclass 24, count 2 2006.239.08:24:50.43#ibcon#*before return 0, iclass 24, count 2 2006.239.08:24:50.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:50.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.239.08:24:50.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.239.08:24:50.43#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:50.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:50.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:50.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:50.55#ibcon#enter wrdev, iclass 24, count 0 2006.239.08:24:50.55#ibcon#first serial, iclass 24, count 0 2006.239.08:24:50.55#ibcon#enter sib2, iclass 24, count 0 2006.239.08:24:50.55#ibcon#flushed, iclass 24, count 0 2006.239.08:24:50.55#ibcon#about to write, iclass 24, count 0 2006.239.08:24:50.55#ibcon#wrote, iclass 24, count 0 2006.239.08:24:50.55#ibcon#about to read 3, iclass 24, count 0 2006.239.08:24:50.57#ibcon#read 3, iclass 24, count 0 2006.239.08:24:50.57#ibcon#about to read 4, iclass 24, count 0 2006.239.08:24:50.57#ibcon#read 4, iclass 24, count 0 2006.239.08:24:50.57#ibcon#about to read 5, iclass 24, count 0 2006.239.08:24:50.57#ibcon#read 5, iclass 24, count 0 2006.239.08:24:50.57#ibcon#about to read 6, iclass 24, count 0 2006.239.08:24:50.57#ibcon#read 6, iclass 24, count 0 2006.239.08:24:50.57#ibcon#end of sib2, iclass 24, count 0 2006.239.08:24:50.57#ibcon#*mode == 0, iclass 24, count 0 2006.239.08:24:50.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.239.08:24:50.57#ibcon#[27=USB\r\n] 2006.239.08:24:50.57#ibcon#*before write, iclass 24, count 0 2006.239.08:24:50.57#ibcon#enter sib2, iclass 24, count 0 2006.239.08:24:50.57#ibcon#flushed, iclass 24, count 0 2006.239.08:24:50.57#ibcon#about to write, iclass 24, count 0 2006.239.08:24:50.57#ibcon#wrote, iclass 24, count 0 2006.239.08:24:50.57#ibcon#about to read 3, iclass 24, count 0 2006.239.08:24:50.60#ibcon#read 3, iclass 24, count 0 2006.239.08:24:50.60#ibcon#about to read 4, iclass 24, count 0 2006.239.08:24:50.60#ibcon#read 4, iclass 24, count 0 2006.239.08:24:50.60#ibcon#about to read 5, iclass 24, count 0 2006.239.08:24:50.60#ibcon#read 5, iclass 24, count 0 2006.239.08:24:50.60#ibcon#about to read 6, iclass 24, count 0 2006.239.08:24:50.60#ibcon#read 6, iclass 24, count 0 2006.239.08:24:50.60#ibcon#end of sib2, iclass 24, count 0 2006.239.08:24:50.60#ibcon#*after write, iclass 24, count 0 2006.239.08:24:50.60#ibcon#*before return 0, iclass 24, count 0 2006.239.08:24:50.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:50.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.239.08:24:50.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.239.08:24:50.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.239.08:24:50.60$vc4f8/vblo=4,712.99 2006.239.08:24:50.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.239.08:24:50.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.239.08:24:50.60#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:50.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:50.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:50.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:50.60#ibcon#enter wrdev, iclass 26, count 0 2006.239.08:24:50.60#ibcon#first serial, iclass 26, count 0 2006.239.08:24:50.60#ibcon#enter sib2, iclass 26, count 0 2006.239.08:24:50.60#ibcon#flushed, iclass 26, count 0 2006.239.08:24:50.60#ibcon#about to write, iclass 26, count 0 2006.239.08:24:50.60#ibcon#wrote, iclass 26, count 0 2006.239.08:24:50.60#ibcon#about to read 3, iclass 26, count 0 2006.239.08:24:50.62#ibcon#read 3, iclass 26, count 0 2006.239.08:24:50.62#ibcon#about to read 4, iclass 26, count 0 2006.239.08:24:50.62#ibcon#read 4, iclass 26, count 0 2006.239.08:24:50.62#ibcon#about to read 5, iclass 26, count 0 2006.239.08:24:50.62#ibcon#read 5, iclass 26, count 0 2006.239.08:24:50.62#ibcon#about to read 6, iclass 26, count 0 2006.239.08:24:50.62#ibcon#read 6, iclass 26, count 0 2006.239.08:24:50.62#ibcon#end of sib2, iclass 26, count 0 2006.239.08:24:50.62#ibcon#*mode == 0, iclass 26, count 0 2006.239.08:24:50.62#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.239.08:24:50.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.239.08:24:50.62#ibcon#*before write, iclass 26, count 0 2006.239.08:24:50.62#ibcon#enter sib2, iclass 26, count 0 2006.239.08:24:50.62#ibcon#flushed, iclass 26, count 0 2006.239.08:24:50.62#ibcon#about to write, iclass 26, count 0 2006.239.08:24:50.62#ibcon#wrote, iclass 26, count 0 2006.239.08:24:50.62#ibcon#about to read 3, iclass 26, count 0 2006.239.08:24:50.66#ibcon#read 3, iclass 26, count 0 2006.239.08:24:50.66#ibcon#about to read 4, iclass 26, count 0 2006.239.08:24:50.66#ibcon#read 4, iclass 26, count 0 2006.239.08:24:50.66#ibcon#about to read 5, iclass 26, count 0 2006.239.08:24:50.66#ibcon#read 5, iclass 26, count 0 2006.239.08:24:50.66#ibcon#about to read 6, iclass 26, count 0 2006.239.08:24:50.66#ibcon#read 6, iclass 26, count 0 2006.239.08:24:50.66#ibcon#end of sib2, iclass 26, count 0 2006.239.08:24:50.66#ibcon#*after write, iclass 26, count 0 2006.239.08:24:50.66#ibcon#*before return 0, iclass 26, count 0 2006.239.08:24:50.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:50.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.239.08:24:50.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.239.08:24:50.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.239.08:24:50.66$vc4f8/vb=4,4 2006.239.08:24:50.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.239.08:24:50.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.239.08:24:50.66#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:50.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:50.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:50.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:50.72#ibcon#enter wrdev, iclass 28, count 2 2006.239.08:24:50.72#ibcon#first serial, iclass 28, count 2 2006.239.08:24:50.72#ibcon#enter sib2, iclass 28, count 2 2006.239.08:24:50.72#ibcon#flushed, iclass 28, count 2 2006.239.08:24:50.72#ibcon#about to write, iclass 28, count 2 2006.239.08:24:50.72#ibcon#wrote, iclass 28, count 2 2006.239.08:24:50.72#ibcon#about to read 3, iclass 28, count 2 2006.239.08:24:50.74#ibcon#read 3, iclass 28, count 2 2006.239.08:24:50.74#ibcon#about to read 4, iclass 28, count 2 2006.239.08:24:50.74#ibcon#read 4, iclass 28, count 2 2006.239.08:24:50.74#ibcon#about to read 5, iclass 28, count 2 2006.239.08:24:50.74#ibcon#read 5, iclass 28, count 2 2006.239.08:24:50.74#ibcon#about to read 6, iclass 28, count 2 2006.239.08:24:50.74#ibcon#read 6, iclass 28, count 2 2006.239.08:24:50.74#ibcon#end of sib2, iclass 28, count 2 2006.239.08:24:50.74#ibcon#*mode == 0, iclass 28, count 2 2006.239.08:24:50.74#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.239.08:24:50.74#ibcon#[27=AT04-04\r\n] 2006.239.08:24:50.74#ibcon#*before write, iclass 28, count 2 2006.239.08:24:50.74#ibcon#enter sib2, iclass 28, count 2 2006.239.08:24:50.74#ibcon#flushed, iclass 28, count 2 2006.239.08:24:50.74#ibcon#about to write, iclass 28, count 2 2006.239.08:24:50.74#ibcon#wrote, iclass 28, count 2 2006.239.08:24:50.74#ibcon#about to read 3, iclass 28, count 2 2006.239.08:24:50.77#ibcon#read 3, iclass 28, count 2 2006.239.08:24:50.77#ibcon#about to read 4, iclass 28, count 2 2006.239.08:24:50.77#ibcon#read 4, iclass 28, count 2 2006.239.08:24:50.77#ibcon#about to read 5, iclass 28, count 2 2006.239.08:24:50.77#ibcon#read 5, iclass 28, count 2 2006.239.08:24:50.77#ibcon#about to read 6, iclass 28, count 2 2006.239.08:24:50.77#ibcon#read 6, iclass 28, count 2 2006.239.08:24:50.77#ibcon#end of sib2, iclass 28, count 2 2006.239.08:24:50.77#ibcon#*after write, iclass 28, count 2 2006.239.08:24:50.77#ibcon#*before return 0, iclass 28, count 2 2006.239.08:24:50.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:50.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.239.08:24:50.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.239.08:24:50.77#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:50.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:50.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:50.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:50.89#ibcon#enter wrdev, iclass 28, count 0 2006.239.08:24:50.89#ibcon#first serial, iclass 28, count 0 2006.239.08:24:50.89#ibcon#enter sib2, iclass 28, count 0 2006.239.08:24:50.89#ibcon#flushed, iclass 28, count 0 2006.239.08:24:50.89#ibcon#about to write, iclass 28, count 0 2006.239.08:24:50.89#ibcon#wrote, iclass 28, count 0 2006.239.08:24:50.89#ibcon#about to read 3, iclass 28, count 0 2006.239.08:24:50.91#ibcon#read 3, iclass 28, count 0 2006.239.08:24:50.91#ibcon#about to read 4, iclass 28, count 0 2006.239.08:24:50.91#ibcon#read 4, iclass 28, count 0 2006.239.08:24:50.91#ibcon#about to read 5, iclass 28, count 0 2006.239.08:24:50.91#ibcon#read 5, iclass 28, count 0 2006.239.08:24:50.91#ibcon#about to read 6, iclass 28, count 0 2006.239.08:24:50.91#ibcon#read 6, iclass 28, count 0 2006.239.08:24:50.91#ibcon#end of sib2, iclass 28, count 0 2006.239.08:24:50.91#ibcon#*mode == 0, iclass 28, count 0 2006.239.08:24:50.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.239.08:24:50.91#ibcon#[27=USB\r\n] 2006.239.08:24:50.91#ibcon#*before write, iclass 28, count 0 2006.239.08:24:50.91#ibcon#enter sib2, iclass 28, count 0 2006.239.08:24:50.91#ibcon#flushed, iclass 28, count 0 2006.239.08:24:50.91#ibcon#about to write, iclass 28, count 0 2006.239.08:24:50.91#ibcon#wrote, iclass 28, count 0 2006.239.08:24:50.91#ibcon#about to read 3, iclass 28, count 0 2006.239.08:24:50.94#ibcon#read 3, iclass 28, count 0 2006.239.08:24:50.94#ibcon#about to read 4, iclass 28, count 0 2006.239.08:24:50.94#ibcon#read 4, iclass 28, count 0 2006.239.08:24:50.94#ibcon#about to read 5, iclass 28, count 0 2006.239.08:24:50.94#ibcon#read 5, iclass 28, count 0 2006.239.08:24:50.94#ibcon#about to read 6, iclass 28, count 0 2006.239.08:24:50.94#ibcon#read 6, iclass 28, count 0 2006.239.08:24:50.94#ibcon#end of sib2, iclass 28, count 0 2006.239.08:24:50.94#ibcon#*after write, iclass 28, count 0 2006.239.08:24:50.94#ibcon#*before return 0, iclass 28, count 0 2006.239.08:24:50.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:50.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.239.08:24:50.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.239.08:24:50.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.239.08:24:50.94$vc4f8/vblo=5,744.99 2006.239.08:24:50.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.239.08:24:50.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.239.08:24:50.94#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:50.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:50.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:50.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:50.94#ibcon#enter wrdev, iclass 30, count 0 2006.239.08:24:50.94#ibcon#first serial, iclass 30, count 0 2006.239.08:24:50.94#ibcon#enter sib2, iclass 30, count 0 2006.239.08:24:50.94#ibcon#flushed, iclass 30, count 0 2006.239.08:24:50.94#ibcon#about to write, iclass 30, count 0 2006.239.08:24:50.94#ibcon#wrote, iclass 30, count 0 2006.239.08:24:50.94#ibcon#about to read 3, iclass 30, count 0 2006.239.08:24:50.96#ibcon#read 3, iclass 30, count 0 2006.239.08:24:50.96#ibcon#about to read 4, iclass 30, count 0 2006.239.08:24:50.96#ibcon#read 4, iclass 30, count 0 2006.239.08:24:50.96#ibcon#about to read 5, iclass 30, count 0 2006.239.08:24:50.96#ibcon#read 5, iclass 30, count 0 2006.239.08:24:50.96#ibcon#about to read 6, iclass 30, count 0 2006.239.08:24:50.96#ibcon#read 6, iclass 30, count 0 2006.239.08:24:50.96#ibcon#end of sib2, iclass 30, count 0 2006.239.08:24:50.96#ibcon#*mode == 0, iclass 30, count 0 2006.239.08:24:50.96#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.239.08:24:50.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.239.08:24:50.96#ibcon#*before write, iclass 30, count 0 2006.239.08:24:50.96#ibcon#enter sib2, iclass 30, count 0 2006.239.08:24:50.96#ibcon#flushed, iclass 30, count 0 2006.239.08:24:50.96#ibcon#about to write, iclass 30, count 0 2006.239.08:24:50.96#ibcon#wrote, iclass 30, count 0 2006.239.08:24:50.96#ibcon#about to read 3, iclass 30, count 0 2006.239.08:24:51.00#ibcon#read 3, iclass 30, count 0 2006.239.08:24:51.00#ibcon#about to read 4, iclass 30, count 0 2006.239.08:24:51.00#ibcon#read 4, iclass 30, count 0 2006.239.08:24:51.00#ibcon#about to read 5, iclass 30, count 0 2006.239.08:24:51.00#ibcon#read 5, iclass 30, count 0 2006.239.08:24:51.00#ibcon#about to read 6, iclass 30, count 0 2006.239.08:24:51.00#ibcon#read 6, iclass 30, count 0 2006.239.08:24:51.00#ibcon#end of sib2, iclass 30, count 0 2006.239.08:24:51.00#ibcon#*after write, iclass 30, count 0 2006.239.08:24:51.00#ibcon#*before return 0, iclass 30, count 0 2006.239.08:24:51.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:51.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.239.08:24:51.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.239.08:24:51.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.239.08:24:51.00$vc4f8/vb=5,4 2006.239.08:24:51.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.239.08:24:51.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.239.08:24:51.00#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:51.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:51.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:51.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:51.06#ibcon#enter wrdev, iclass 32, count 2 2006.239.08:24:51.06#ibcon#first serial, iclass 32, count 2 2006.239.08:24:51.06#ibcon#enter sib2, iclass 32, count 2 2006.239.08:24:51.06#ibcon#flushed, iclass 32, count 2 2006.239.08:24:51.06#ibcon#about to write, iclass 32, count 2 2006.239.08:24:51.06#ibcon#wrote, iclass 32, count 2 2006.239.08:24:51.06#ibcon#about to read 3, iclass 32, count 2 2006.239.08:24:51.08#ibcon#read 3, iclass 32, count 2 2006.239.08:24:51.08#ibcon#about to read 4, iclass 32, count 2 2006.239.08:24:51.08#ibcon#read 4, iclass 32, count 2 2006.239.08:24:51.08#ibcon#about to read 5, iclass 32, count 2 2006.239.08:24:51.08#ibcon#read 5, iclass 32, count 2 2006.239.08:24:51.08#ibcon#about to read 6, iclass 32, count 2 2006.239.08:24:51.08#ibcon#read 6, iclass 32, count 2 2006.239.08:24:51.08#ibcon#end of sib2, iclass 32, count 2 2006.239.08:24:51.08#ibcon#*mode == 0, iclass 32, count 2 2006.239.08:24:51.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.239.08:24:51.08#ibcon#[27=AT05-04\r\n] 2006.239.08:24:51.08#ibcon#*before write, iclass 32, count 2 2006.239.08:24:51.08#ibcon#enter sib2, iclass 32, count 2 2006.239.08:24:51.08#ibcon#flushed, iclass 32, count 2 2006.239.08:24:51.08#ibcon#about to write, iclass 32, count 2 2006.239.08:24:51.08#ibcon#wrote, iclass 32, count 2 2006.239.08:24:51.08#ibcon#about to read 3, iclass 32, count 2 2006.239.08:24:51.11#ibcon#read 3, iclass 32, count 2 2006.239.08:24:51.11#ibcon#about to read 4, iclass 32, count 2 2006.239.08:24:51.11#ibcon#read 4, iclass 32, count 2 2006.239.08:24:51.11#ibcon#about to read 5, iclass 32, count 2 2006.239.08:24:51.11#ibcon#read 5, iclass 32, count 2 2006.239.08:24:51.11#ibcon#about to read 6, iclass 32, count 2 2006.239.08:24:51.11#ibcon#read 6, iclass 32, count 2 2006.239.08:24:51.11#ibcon#end of sib2, iclass 32, count 2 2006.239.08:24:51.11#ibcon#*after write, iclass 32, count 2 2006.239.08:24:51.11#ibcon#*before return 0, iclass 32, count 2 2006.239.08:24:51.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:51.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.239.08:24:51.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.239.08:24:51.11#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:51.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:51.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:51.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:51.23#ibcon#enter wrdev, iclass 32, count 0 2006.239.08:24:51.23#ibcon#first serial, iclass 32, count 0 2006.239.08:24:51.23#ibcon#enter sib2, iclass 32, count 0 2006.239.08:24:51.23#ibcon#flushed, iclass 32, count 0 2006.239.08:24:51.23#ibcon#about to write, iclass 32, count 0 2006.239.08:24:51.23#ibcon#wrote, iclass 32, count 0 2006.239.08:24:51.23#ibcon#about to read 3, iclass 32, count 0 2006.239.08:24:51.25#ibcon#read 3, iclass 32, count 0 2006.239.08:24:51.25#ibcon#about to read 4, iclass 32, count 0 2006.239.08:24:51.25#ibcon#read 4, iclass 32, count 0 2006.239.08:24:51.25#ibcon#about to read 5, iclass 32, count 0 2006.239.08:24:51.25#ibcon#read 5, iclass 32, count 0 2006.239.08:24:51.25#ibcon#about to read 6, iclass 32, count 0 2006.239.08:24:51.25#ibcon#read 6, iclass 32, count 0 2006.239.08:24:51.25#ibcon#end of sib2, iclass 32, count 0 2006.239.08:24:51.25#ibcon#*mode == 0, iclass 32, count 0 2006.239.08:24:51.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.239.08:24:51.25#ibcon#[27=USB\r\n] 2006.239.08:24:51.25#ibcon#*before write, iclass 32, count 0 2006.239.08:24:51.25#ibcon#enter sib2, iclass 32, count 0 2006.239.08:24:51.25#ibcon#flushed, iclass 32, count 0 2006.239.08:24:51.25#ibcon#about to write, iclass 32, count 0 2006.239.08:24:51.25#ibcon#wrote, iclass 32, count 0 2006.239.08:24:51.25#ibcon#about to read 3, iclass 32, count 0 2006.239.08:24:51.28#ibcon#read 3, iclass 32, count 0 2006.239.08:24:51.28#ibcon#about to read 4, iclass 32, count 0 2006.239.08:24:51.28#ibcon#read 4, iclass 32, count 0 2006.239.08:24:51.28#ibcon#about to read 5, iclass 32, count 0 2006.239.08:24:51.28#ibcon#read 5, iclass 32, count 0 2006.239.08:24:51.28#ibcon#about to read 6, iclass 32, count 0 2006.239.08:24:51.28#ibcon#read 6, iclass 32, count 0 2006.239.08:24:51.28#ibcon#end of sib2, iclass 32, count 0 2006.239.08:24:51.28#ibcon#*after write, iclass 32, count 0 2006.239.08:24:51.28#ibcon#*before return 0, iclass 32, count 0 2006.239.08:24:51.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:51.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.239.08:24:51.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.239.08:24:51.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.239.08:24:51.28$vc4f8/vblo=6,752.99 2006.239.08:24:51.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.239.08:24:51.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.239.08:24:51.28#ibcon#ireg 17 cls_cnt 0 2006.239.08:24:51.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:51.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:51.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:51.28#ibcon#enter wrdev, iclass 34, count 0 2006.239.08:24:51.28#ibcon#first serial, iclass 34, count 0 2006.239.08:24:51.28#ibcon#enter sib2, iclass 34, count 0 2006.239.08:24:51.28#ibcon#flushed, iclass 34, count 0 2006.239.08:24:51.28#ibcon#about to write, iclass 34, count 0 2006.239.08:24:51.28#ibcon#wrote, iclass 34, count 0 2006.239.08:24:51.28#ibcon#about to read 3, iclass 34, count 0 2006.239.08:24:51.30#ibcon#read 3, iclass 34, count 0 2006.239.08:24:51.30#ibcon#about to read 4, iclass 34, count 0 2006.239.08:24:51.30#ibcon#read 4, iclass 34, count 0 2006.239.08:24:51.30#ibcon#about to read 5, iclass 34, count 0 2006.239.08:24:51.30#ibcon#read 5, iclass 34, count 0 2006.239.08:24:51.30#ibcon#about to read 6, iclass 34, count 0 2006.239.08:24:51.30#ibcon#read 6, iclass 34, count 0 2006.239.08:24:51.30#ibcon#end of sib2, iclass 34, count 0 2006.239.08:24:51.30#ibcon#*mode == 0, iclass 34, count 0 2006.239.08:24:51.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.239.08:24:51.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.239.08:24:51.30#ibcon#*before write, iclass 34, count 0 2006.239.08:24:51.30#ibcon#enter sib2, iclass 34, count 0 2006.239.08:24:51.30#ibcon#flushed, iclass 34, count 0 2006.239.08:24:51.30#ibcon#about to write, iclass 34, count 0 2006.239.08:24:51.30#ibcon#wrote, iclass 34, count 0 2006.239.08:24:51.30#ibcon#about to read 3, iclass 34, count 0 2006.239.08:24:51.34#ibcon#read 3, iclass 34, count 0 2006.239.08:24:51.34#ibcon#about to read 4, iclass 34, count 0 2006.239.08:24:51.34#ibcon#read 4, iclass 34, count 0 2006.239.08:24:51.34#ibcon#about to read 5, iclass 34, count 0 2006.239.08:24:51.34#ibcon#read 5, iclass 34, count 0 2006.239.08:24:51.34#ibcon#about to read 6, iclass 34, count 0 2006.239.08:24:51.34#ibcon#read 6, iclass 34, count 0 2006.239.08:24:51.34#ibcon#end of sib2, iclass 34, count 0 2006.239.08:24:51.34#ibcon#*after write, iclass 34, count 0 2006.239.08:24:51.34#ibcon#*before return 0, iclass 34, count 0 2006.239.08:24:51.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:51.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.239.08:24:51.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.239.08:24:51.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.239.08:24:51.34$vc4f8/vb=6,4 2006.239.08:24:51.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.239.08:24:51.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.239.08:24:51.34#ibcon#ireg 11 cls_cnt 2 2006.239.08:24:51.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:51.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:51.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:51.40#ibcon#enter wrdev, iclass 36, count 2 2006.239.08:24:51.40#ibcon#first serial, iclass 36, count 2 2006.239.08:24:51.40#ibcon#enter sib2, iclass 36, count 2 2006.239.08:24:51.40#ibcon#flushed, iclass 36, count 2 2006.239.08:24:51.40#ibcon#about to write, iclass 36, count 2 2006.239.08:24:51.40#ibcon#wrote, iclass 36, count 2 2006.239.08:24:51.40#ibcon#about to read 3, iclass 36, count 2 2006.239.08:24:51.42#ibcon#read 3, iclass 36, count 2 2006.239.08:24:51.42#ibcon#about to read 4, iclass 36, count 2 2006.239.08:24:51.42#ibcon#read 4, iclass 36, count 2 2006.239.08:24:51.42#ibcon#about to read 5, iclass 36, count 2 2006.239.08:24:51.42#ibcon#read 5, iclass 36, count 2 2006.239.08:24:51.42#ibcon#about to read 6, iclass 36, count 2 2006.239.08:24:51.42#ibcon#read 6, iclass 36, count 2 2006.239.08:24:51.42#ibcon#end of sib2, iclass 36, count 2 2006.239.08:24:51.42#ibcon#*mode == 0, iclass 36, count 2 2006.239.08:24:51.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.239.08:24:51.42#ibcon#[27=AT06-04\r\n] 2006.239.08:24:51.42#ibcon#*before write, iclass 36, count 2 2006.239.08:24:51.42#ibcon#enter sib2, iclass 36, count 2 2006.239.08:24:51.42#ibcon#flushed, iclass 36, count 2 2006.239.08:24:51.42#ibcon#about to write, iclass 36, count 2 2006.239.08:24:51.42#ibcon#wrote, iclass 36, count 2 2006.239.08:24:51.42#ibcon#about to read 3, iclass 36, count 2 2006.239.08:24:51.45#ibcon#read 3, iclass 36, count 2 2006.239.08:24:51.45#ibcon#about to read 4, iclass 36, count 2 2006.239.08:24:51.45#ibcon#read 4, iclass 36, count 2 2006.239.08:24:51.45#ibcon#about to read 5, iclass 36, count 2 2006.239.08:24:51.45#ibcon#read 5, iclass 36, count 2 2006.239.08:24:51.45#ibcon#about to read 6, iclass 36, count 2 2006.239.08:24:51.45#ibcon#read 6, iclass 36, count 2 2006.239.08:24:51.45#ibcon#end of sib2, iclass 36, count 2 2006.239.08:24:51.45#ibcon#*after write, iclass 36, count 2 2006.239.08:24:51.45#ibcon#*before return 0, iclass 36, count 2 2006.239.08:24:51.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:51.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.239.08:24:51.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.239.08:24:51.45#ibcon#ireg 7 cls_cnt 0 2006.239.08:24:51.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:51.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:51.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:51.57#ibcon#enter wrdev, iclass 36, count 0 2006.239.08:24:51.57#ibcon#first serial, iclass 36, count 0 2006.239.08:24:51.57#ibcon#enter sib2, iclass 36, count 0 2006.239.08:24:51.57#ibcon#flushed, iclass 36, count 0 2006.239.08:24:51.57#ibcon#about to write, iclass 36, count 0 2006.239.08:24:51.57#ibcon#wrote, iclass 36, count 0 2006.239.08:24:51.57#ibcon#about to read 3, iclass 36, count 0 2006.239.08:24:51.59#ibcon#read 3, iclass 36, count 0 2006.239.08:24:51.59#ibcon#about to read 4, iclass 36, count 0 2006.239.08:24:51.59#ibcon#read 4, iclass 36, count 0 2006.239.08:24:51.59#ibcon#about to read 5, iclass 36, count 0 2006.239.08:24:51.59#ibcon#read 5, iclass 36, count 0 2006.239.08:24:51.59#ibcon#about to read 6, iclass 36, count 0 2006.239.08:24:51.59#ibcon#read 6, iclass 36, count 0 2006.239.08:24:51.59#ibcon#end of sib2, iclass 36, count 0 2006.239.08:24:51.59#ibcon#*mode == 0, iclass 36, count 0 2006.239.08:24:51.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.239.08:24:51.59#ibcon#[27=USB\r\n] 2006.239.08:24:51.59#ibcon#*before write, iclass 36, count 0 2006.239.08:24:51.59#ibcon#enter sib2, iclass 36, count 0 2006.239.08:24:51.59#ibcon#flushed, iclass 36, count 0 2006.239.08:24:51.59#ibcon#about to write, iclass 36, count 0 2006.239.08:24:51.59#ibcon#wrote, iclass 36, count 0 2006.239.08:24:51.59#ibcon#about to read 3, iclass 36, count 0 2006.239.08:24:51.62#ibcon#read 3, iclass 36, count 0 2006.239.08:24:51.62#ibcon#about to read 4, iclass 36, count 0 2006.239.08:24:51.62#ibcon#read 4, iclass 36, count 0 2006.239.08:24:51.62#ibcon#about to read 5, iclass 36, count 0 2006.239.08:24:51.62#ibcon#read 5, iclass 36, count 0 2006.239.08:24:51.62#ibcon#about to read 6, iclass 36, count 0 2006.239.08:24:51.62#ibcon#read 6, iclass 36, count 0 2006.239.08:24:51.62#ibcon#end of sib2, iclass 36, count 0 2006.239.08:24:51.62#ibcon#*after write, iclass 36, count 0 2006.239.08:24:51.62#ibcon#*before return 0, iclass 36, count 0 2006.239.08:24:51.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:51.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.239.08:24:51.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.239.08:24:51.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.239.08:24:51.62$vc4f8/vabw=wide 2006.239.08:24:51.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.239.08:24:51.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.239.08:24:51.62#ibcon#ireg 8 cls_cnt 0 2006.239.08:24:51.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:24:51.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:24:51.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:24:51.62#ibcon#enter wrdev, iclass 38, count 0 2006.239.08:24:51.62#ibcon#first serial, iclass 38, count 0 2006.239.08:24:51.62#ibcon#enter sib2, iclass 38, count 0 2006.239.08:24:51.62#ibcon#flushed, iclass 38, count 0 2006.239.08:24:51.62#ibcon#about to write, iclass 38, count 0 2006.239.08:24:51.62#ibcon#wrote, iclass 38, count 0 2006.239.08:24:51.62#ibcon#about to read 3, iclass 38, count 0 2006.239.08:24:51.65#ibcon#read 3, iclass 38, count 0 2006.239.08:24:51.65#ibcon#about to read 4, iclass 38, count 0 2006.239.08:24:51.65#ibcon#read 4, iclass 38, count 0 2006.239.08:24:51.65#ibcon#about to read 5, iclass 38, count 0 2006.239.08:24:51.65#ibcon#read 5, iclass 38, count 0 2006.239.08:24:51.65#ibcon#about to read 6, iclass 38, count 0 2006.239.08:24:51.65#ibcon#read 6, iclass 38, count 0 2006.239.08:24:51.65#ibcon#end of sib2, iclass 38, count 0 2006.239.08:24:51.65#ibcon#*mode == 0, iclass 38, count 0 2006.239.08:24:51.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.239.08:24:51.65#ibcon#[25=BW32\r\n] 2006.239.08:24:51.65#ibcon#*before write, iclass 38, count 0 2006.239.08:24:51.65#ibcon#enter sib2, iclass 38, count 0 2006.239.08:24:51.65#ibcon#flushed, iclass 38, count 0 2006.239.08:24:51.65#ibcon#about to write, iclass 38, count 0 2006.239.08:24:51.65#ibcon#wrote, iclass 38, count 0 2006.239.08:24:51.65#ibcon#about to read 3, iclass 38, count 0 2006.239.08:24:51.68#ibcon#read 3, iclass 38, count 0 2006.239.08:24:51.68#ibcon#about to read 4, iclass 38, count 0 2006.239.08:24:51.68#ibcon#read 4, iclass 38, count 0 2006.239.08:24:51.68#ibcon#about to read 5, iclass 38, count 0 2006.239.08:24:51.68#ibcon#read 5, iclass 38, count 0 2006.239.08:24:51.68#ibcon#about to read 6, iclass 38, count 0 2006.239.08:24:51.68#ibcon#read 6, iclass 38, count 0 2006.239.08:24:51.68#ibcon#end of sib2, iclass 38, count 0 2006.239.08:24:51.68#ibcon#*after write, iclass 38, count 0 2006.239.08:24:51.68#ibcon#*before return 0, iclass 38, count 0 2006.239.08:24:51.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:24:51.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.239.08:24:51.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.239.08:24:51.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.239.08:24:51.68$vc4f8/vbbw=wide 2006.239.08:24:51.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.239.08:24:51.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.239.08:24:51.68#ibcon#ireg 8 cls_cnt 0 2006.239.08:24:51.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:24:51.74#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:24:51.74#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:24:51.74#ibcon#enter wrdev, iclass 40, count 0 2006.239.08:24:51.74#ibcon#first serial, iclass 40, count 0 2006.239.08:24:51.74#ibcon#enter sib2, iclass 40, count 0 2006.239.08:24:51.74#ibcon#flushed, iclass 40, count 0 2006.239.08:24:51.74#ibcon#about to write, iclass 40, count 0 2006.239.08:24:51.74#ibcon#wrote, iclass 40, count 0 2006.239.08:24:51.74#ibcon#about to read 3, iclass 40, count 0 2006.239.08:24:51.76#ibcon#read 3, iclass 40, count 0 2006.239.08:24:51.76#ibcon#about to read 4, iclass 40, count 0 2006.239.08:24:51.76#ibcon#read 4, iclass 40, count 0 2006.239.08:24:51.76#ibcon#about to read 5, iclass 40, count 0 2006.239.08:24:51.76#ibcon#read 5, iclass 40, count 0 2006.239.08:24:51.76#ibcon#about to read 6, iclass 40, count 0 2006.239.08:24:51.76#ibcon#read 6, iclass 40, count 0 2006.239.08:24:51.76#ibcon#end of sib2, iclass 40, count 0 2006.239.08:24:51.76#ibcon#*mode == 0, iclass 40, count 0 2006.239.08:24:51.76#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.239.08:24:51.76#ibcon#[27=BW32\r\n] 2006.239.08:24:51.76#ibcon#*before write, iclass 40, count 0 2006.239.08:24:51.76#ibcon#enter sib2, iclass 40, count 0 2006.239.08:24:51.76#ibcon#flushed, iclass 40, count 0 2006.239.08:24:51.76#ibcon#about to write, iclass 40, count 0 2006.239.08:24:51.76#ibcon#wrote, iclass 40, count 0 2006.239.08:24:51.76#ibcon#about to read 3, iclass 40, count 0 2006.239.08:24:51.80#ibcon#read 3, iclass 40, count 0 2006.239.08:24:51.80#ibcon#about to read 4, iclass 40, count 0 2006.239.08:24:51.80#ibcon#read 4, iclass 40, count 0 2006.239.08:24:51.80#ibcon#about to read 5, iclass 40, count 0 2006.239.08:24:51.80#ibcon#read 5, iclass 40, count 0 2006.239.08:24:51.80#ibcon#about to read 6, iclass 40, count 0 2006.239.08:24:51.80#ibcon#read 6, iclass 40, count 0 2006.239.08:24:51.80#ibcon#end of sib2, iclass 40, count 0 2006.239.08:24:51.80#ibcon#*after write, iclass 40, count 0 2006.239.08:24:51.80#ibcon#*before return 0, iclass 40, count 0 2006.239.08:24:51.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:24:51.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.239.08:24:51.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.239.08:24:51.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.239.08:24:51.80$4f8m12a/ifd4f 2006.239.08:24:51.80$ifd4f/lo= 2006.239.08:24:51.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.239.08:24:51.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.239.08:24:51.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.239.08:24:51.80$ifd4f/patch= 2006.239.08:24:51.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.239.08:24:51.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.239.08:24:51.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.239.08:24:51.80$4f8m12a/"form=m,16.000,1:2 2006.239.08:24:51.80$4f8m12a/"tpicd 2006.239.08:24:51.80$4f8m12a/echo=off 2006.239.08:24:51.80$4f8m12a/xlog=off 2006.239.08:24:51.80:!2006.239.08:25:20 2006.239.08:25:02.14#trakl#Source acquired 2006.239.08:25:04.14#flagr#flagr/antenna,acquired 2006.239.08:25:20.01:preob 2006.239.08:25:21.14/onsource/TRACKING 2006.239.08:25:21.14:!2006.239.08:25:30 2006.239.08:25:30.00:data_valid=on 2006.239.08:25:30.00:midob 2006.239.08:25:30.14/onsource/TRACKING 2006.239.08:25:30.14/wx/24.89,1011.5,78 2006.239.08:25:30.30/cable/+6.4139E-03 2006.239.08:25:31.39/va/01,08,usb,yes,31,32 2006.239.08:25:31.39/va/02,07,usb,yes,31,32 2006.239.08:25:31.39/va/03,07,usb,yes,29,29 2006.239.08:25:31.39/va/04,07,usb,yes,32,35 2006.239.08:25:31.39/va/05,08,usb,yes,29,31 2006.239.08:25:31.39/va/06,07,usb,yes,32,32 2006.239.08:25:31.39/va/07,07,usb,yes,32,31 2006.239.08:25:31.39/va/08,07,usb,yes,34,34 2006.239.08:25:31.62/valo/01,532.99,yes,locked 2006.239.08:25:31.62/valo/02,572.99,yes,locked 2006.239.08:25:31.62/valo/03,672.99,yes,locked 2006.239.08:25:31.62/valo/04,832.99,yes,locked 2006.239.08:25:31.62/valo/05,652.99,yes,locked 2006.239.08:25:31.62/valo/06,772.99,yes,locked 2006.239.08:25:31.62/valo/07,832.99,yes,locked 2006.239.08:25:31.62/valo/08,852.99,yes,locked 2006.239.08:25:32.71/vb/01,04,usb,yes,30,29 2006.239.08:25:32.71/vb/02,04,usb,yes,32,34 2006.239.08:25:32.71/vb/03,04,usb,yes,29,32 2006.239.08:25:32.71/vb/04,04,usb,yes,29,29 2006.239.08:25:32.71/vb/05,04,usb,yes,28,32 2006.239.08:25:32.71/vb/06,04,usb,yes,29,31 2006.239.08:25:32.71/vb/07,04,usb,yes,31,31 2006.239.08:25:32.71/vb/08,04,usb,yes,28,32 2006.239.08:25:32.95/vblo/01,632.99,yes,locked 2006.239.08:25:32.95/vblo/02,640.99,yes,locked 2006.239.08:25:32.95/vblo/03,656.99,yes,locked 2006.239.08:25:32.95/vblo/04,712.99,yes,locked 2006.239.08:25:32.95/vblo/05,744.99,yes,locked 2006.239.08:25:32.95/vblo/06,752.99,yes,locked 2006.239.08:25:32.95/vblo/07,734.99,yes,locked 2006.239.08:25:32.95/vblo/08,744.99,yes,locked 2006.239.08:25:33.10/vabw/8 2006.239.08:25:33.25/vbbw/8 2006.239.08:25:33.34/xfe/off,on,13.0 2006.239.08:25:33.72/ifatt/23,28,28,28 2006.239.08:25:34.07/fmout-gps/S +4.41E-07 2006.239.08:25:34.11:!2006.239.08:26:30 2006.239.08:26:30.00:data_valid=off 2006.239.08:26:30.00:postob 2006.239.08:26:30.10/cable/+6.4149E-03 2006.239.08:26:30.10/wx/24.88,1011.5,79 2006.239.08:26:31.08/fmout-gps/S +4.42E-07 2006.239.08:26:31.08:checkk5last 2006.239.08:26:31.09&checkk5last/chk_obsdata=1 2006.239.08:26:31.09&checkk5last/chk_obsdata=2 2006.239.08:26:31.10&checkk5last/chk_obsdata=3 2006.239.08:26:31.10&checkk5last/chk_obsdata=4 2006.239.08:26:31.10&checkk5last/k5log=1 2006.239.08:26:31.11&checkk5last/k5log=2 2006.239.08:26:31.11&checkk5last/k5log=3 2006.239.08:26:31.12&checkk5last/k5log=4 2006.239.08:26:31.12&checkk5last/obsinfo 2006.239.08:26:31.51/chk_obsdata//k5ts1/T2390825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:26:31.88/chk_obsdata//k5ts2/T2390825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:26:32.26/chk_obsdata//k5ts3/T2390825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:26:32.63/chk_obsdata//k5ts4/T2390825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.239.08:26:33.33/k5log//k5ts1_log_newline 2006.239.08:26:34.02/k5log//k5ts2_log_newline 2006.239.08:26:34.70/k5log//k5ts3_log_newline 2006.239.08:26:35.40/k5log//k5ts4_log_newline 2006.239.08:26:35.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.239.08:26:35.43:sched_end 2006.239.08:26:35.43&sched_end/stopcheck 2006.239.08:26:35.43&stopcheck/sy=killall check_fsrun.pl 2006.239.08:26:35.43&stopcheck/" sy=killall chmem.sh 2006.239.08:26:35.52:source=idle 2006.239.08:26:36.14#flagr#flagr/antenna,new-source 2006.239.08:26:36.15:stow 2006.239.08:26:36.15&stow/source=idle 2006.239.08:26:36.15&stow/"this is stow command. 2006.239.08:26:36.16&stow/antenna=m3 2006.239.08:26:40.01:!+10m 2006.239.08:36:40.02:standby 2006.239.08:36:40.02&standby/"this is standby command. 2006.239.08:36:40.03&standby/antenna=m0 2006.239.08:36:41.01:checkk5hdd 2006.239.08:36:41.01&checkk5hdd/chk_hdd=1 2006.239.08:36:41.02&checkk5hdd/chk_hdd=2 2006.239.08:36:41.02&checkk5hdd/chk_hdd=3 2006.239.08:36:41.02&checkk5hdd/chk_hdd=4 2006.239.08:36:43.82/chk_hdd//k5ts1/GSI00275:T239073000a.dat~T239082530a.dat[12769492992Byte] 2006.239.08:36:46.63/chk_hdd//k5ts2/GSI00163:T239073000b.dat~T239082530b.dat[12769492992Byte] 2006.239.08:36:49.45/chk_hdd//k5ts3/GSI00278:T239073000c.dat~T239082530c.dat[12769492992Byte] 2006.239.08:36:52.26/chk_hdd//k5ts4/GSI00141:T239073000d.dat~T239082530d.dat[12769492992Byte] 2006.239.08:36:52.27:sy=cp /usr2/log/k06239ts.log /usr2/log_backup/ 2006.239.08:36:52.37:*end of schedule 2006.239.18:06:25.60?ERROR st -97 Trouble decoding pressure data 2006.239.18:06:25.60#wxget#05 1.4 2.0 22.93 911010.1